repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
jc38x/X38-02FO16 | benchmarks/LEKO_LEKU/leku/LEKU-CB.vhd | 1 | 36,920 | Library IEEE;
use IEEE.std_logic_1164.all;
entity testing is
Port (
A302,A301,A300,A299,A298,A269,A268,A267,A266,A265,A236,A235,A234,A233,A232,A203,A202,A201,A200,A199,A166,A167,A168,A169,A170: in std_logic;
A142,A141,A140,A139,A138,A109,A108,A107,A106,A105,A76,A75,A74,A73,A72,A43,A42,A41,A40,A39,A6,A7,A8,A9,A10: buffer std_logic
);
end testing;
architecture testing_behav of testing is
signal a50a,a51a,a52a,a53a,a54a,a55a,a56a,a57a,a58a,a59a,a60a,a61a,a62a,a63a,a64a,a65a,a66a,a67a,a68a,a69a,a70a,a71a,a72a,a73a,a74a,a75a,a76a,a77a,a78a,a79a,a80a,a81a,a82a,a83a,a84a,a85a,a86a,a87a,a88a,a89a,a90a,a91a,a92a,a93a,a94a,a95a,a96a,a97a,a98a,a99a,a100a,a101a,a102a,a103a,a104a,a105a,a106a,a107a,a108a,a109a,a110a,a111a,a112a,a113a,a114a,a115a,a116a,a117a,a118a,a119a,a120a,a121a,a122a,a123a,a124a,a125a,a126a,a127a,a128a,a129a,a130a,a131a,a132a,a133a,a134a,a135a,a136a,a137a,a138a,a139a,a140a,a141a,a142a,a143a,a144a,a145a,a146a,a147a,a148a,a149a,a150a,a151a,a152a,a153a,a154a,a155a,a156a,a157a,a158a,a160a,a161a,a162a,a163a,a164a,a165a,a166a,a167a,a168a,a169a,a170a,a171a,a173a,a174a,a175a,a176a,a177a,a178a,a179a,a180a,a181a,a182a,a183a,a184a,a185a,a186a,a187a,a188a,a189a,a190a,a191a,a192a,a193a,a194a,a195a,a196a,a197a,a198a,a199a,a200a,a201a,a202a,a203a,a204a,a205a,a206a,a207a,a208a,a209a,a210a,a211a,a212a,a213a,a214a,a215a,a216a,a217a,a218a,a219a,a220a,a221a,a222a,a223a,a224a,a225a,a226a,a227a,a228a,a229a,a230a,a231a,a232a,a233a,a234a,a235a,a236a,a237a,a238a,a239a,a240a,a241a,a242a,a243a,a244a,a245a,a246a,a247a,a248a,a249a,a250a,a252a,a253a,a254a,a255a,a256a,a257a,a258a,a259a,a260a,a261a,a262a,a263a,a264a,a265a,a266a,a267a,a268a,a269a,a270a,a271a,a272a,a273a,a274a,a275a,a276a,a277a,a278a,a279a,a280a,a281a,a282a,a283a,a284a,a285a,a286a,a287a,a288a,a289a,a290a,a291a,a292a,a293a,a294a,a295a,a296a,a297a,a298a,a299a,a300a,a301a,a302a,a303a,a304a,a305a,a306a,a307a,a308a,a309a,a310a,a311a,a312a,a314a,a315a,a316a,a317a,a318a,a320a,a321a,a322a,a323a,a324a,a325a,a326a,a327a,a328a,a329a,a330a,a331a,a332a,a333a,a334a,a335a,a336a,a337a,a338a,a339a,a340a,a341a,a342a,a343a,a344a,a345a,a346a,a347a,a348a,a349a,a350a,a351a,a352a,a354a,a355a,a356a,a357a,a358a,a359a,a360a,a361a,a362a,a363a,a364a,a365a,a366a,a367a,a368a,a369a,a370a,a371a,a372a,a373a,a374a,a375a,a376a,a377a,a378a,a379a,a380a,a381a,a382a,a383a,a384a,a385a,a386a,a387a,a388a,a389a,a390a,a391a,a392a,a393a,a394a,a395a,a396a,a397a,a398a,a399a,a400a,a401a,a402a,a403a,a404a,a406a,a407a,a408a,a409a,a410a,a412a,a413a,a414a,a415a,a416a,a417a,a418a,a419a,a420a,a421a,a422a,a423a,a424a,a425a,a426a,a427a,a428a,a429a,a430a,a431a,a432a,a433a,a434a,a435a,a436a,a437a,a438a,a439a,a440a,a441a,a442a,a443a,a444a,a445a,a446a,a447a,a448a,a449a,a450a,a451a,a452a,a453a,a454a,a455a,a457a,a458a,a459a,a460a,a461a,a462a,a463a,a464a,a465a,a466a,a467a,a468a,a469a,a470a,a471a,a472a,a473a,a474a,a475a,a476a,a477a,a478a,a479a,a480a,a481a,a482a,a483a,a484a,a485a,a486a,a487a,a488a,a489a,a490a,a491a,a492a,a493a,a494a,a495a,a496a,a497a,a498a,a499a,a500a,a501a,a502a,a503a,a504a,a505a,a506a,a507a,a508a,a509a,a510a,a511a,a512a,a513a,a514a,a515a,a516a,a517a,a518a,a519a,a520a,a521a,a522a,a523a,a524a,a525a,a526a,a527a,a528a,a529a,a530a,a531a,a532a,a533a,a534a,a535a,a536a,a538a,a539a,a540a,a541a,a542a,a543a,a544a,a545a,a546a,a547a,a548a,a549a,a550a,a552a,a553a,a554a,a555a,a556a,a557a,a558a,a559a,a560a,a561a,a562a,a563a,a564a,a565a,a566a,a567a,a568a,a569a,a570a,a571a,a572a,a573a,a574a,a575a,a576a,a577a,a578a,a579a,a580a,a581a,a582a,a583a,a584a,a585a,a586a,a587a,a588a,a589a,a590a,a591a,a592a,a593a,a594a,a595a,a596a,a597a,a598a,a599a,a600a,a601a,a602a,a603a,a604a,a605a,a606a,a607a,a608a,a609a,a610a,a611a,a612a,a613a,a614a,a615a,a616a,a617a,a618a,a619a,a620a,a621a,a622a,a623a,a624a,a625a,a626a,a627a,a628a,a629a,a630a,a631a,a632a,a633a,a634a,a635a,a636a,a637a,a638a,a639a,a640a,a641a,a642a,a643a,a644a,a645a,a646a,a647a,a648a,a649a,a650a,a651a,a652a,a653a,a654a,a656a,a657a,a658a,a659a,a660a,a661a,a662a,a663a,a664a,a665a,a666a,a667a,a668a,a669a,a670a,a671a,a672a,a673a,a674a,a675a,a676a,a677a,a678a,a679a,a680a,a681a,a682a,a683a,a684a,a685a,a686a,a687a,a688a,a689a,a690a,a691a,a692a,a693a,a694a,a695a,a696a,a697a,a698a,a699a,a700a,a701a,a702a,a703a,a704a,a705a,a706a,a707a,a708a,a709a,a710a,a711a,a712a,a713a,a714a,a715a,a716a,a717a,a718a,a719a,a720a,a721a,a722a,a723a,a724a,a725a,a726a,a727a,a728a,a729a,a730a,a731a,a732a,a733a,a734a,a736a,a737a,a738a,a739a,a740a,a741a,a742a,a743a,a744a,a745a,a746a,a747a,a748a,a749a,a750a,a751a,a752a,a753a,a754a,a755a,a756a,a757a,a758a,a759a,a760a,a761a,a762a,a763a,a764a,a765a,a766a,a767a,a768a,a769a,a770a,a771a,a772a,a773a,a774a,a775a,a776a,a777a,a778a,a779a,a780a,a781a,a782a,a783a,a784a,a785a,a786a,a787a,a788a,a789a,a790a,a791a,a792a,a793a,a794a,a795a,a796a,a797a,a798a,a799a,a800a,a801a,a802a,a803a,a804a,a805a,a806a,a808a,a809a,a810a,a811a,a812a,a813a,a814a,a815a,a816a,a817a,a818a,a819a,a820a,a821a,a822a,a823a,a824a,a825a,a826a,a827a,a828a,a829a,a830a,a831a,a832a,a833a,a834a,a835a,a836a,a837a,a839a,a840a,a841a,a842a,a843a,a844a,a845a,a846a,a847a,a848a,a849a,a850a,a851a,a852a,a853a: std_logic;
begin
a50a <=( (not A169) and A170 );
a51a <=( (not A166) and A167 );
a52a <=( A166 and (not A167) );
a53a <=( (not a51a) and (not a52a) );
a54a <=( (not A200) and A199 );
a55a <=( A200 and (not A199) );
a56a <=( (not a54a) and (not a55a) );
a57a <=( (not A203) and (not A202) );
a58a <=( A201 and (not a57a) );
a59a <=( (not A203) and (not A201) );
a60a <=( (not A202) and a59a );
a61a <=( (not a58a) and (not a60a) );
a62a <=( (not a56a) and (not a61a) );
a63a <=( A168 and (not a53a) );
a64a <=( a62a and a63a );
a65a <=( (not A201) and (not a57a) );
a66a <=( (not A203) and A201 );
a67a <=( (not A202) and a66a );
a68a <=( A200 and A199 );
a69a <=( (not A200) and (not A199) );
a70a <=( (not a68a) and (not a69a) );
a71a <=( (not a67a) and a70a );
a72a <=( (not a65a) and a71a );
a73a <=( (not A168) and (not a72a) );
a74a <=( (not a64a) and (not a73a) );
a75a <=( (not a50a) and (not a74a) );
a76a <=( (not a53a) and (not a56a) );
a77a <=( A201 and (not A168) );
a78a <=( a76a and a77a );
a79a <=( (not A201) and A168 );
a80a <=( (not a78a) and (not a79a) );
a81a <=( a50a and (not a80a) );
a82a <=( A166 and A167 );
a83a <=( (not A166) and (not A167) );
a84a <=( (not a82a) and (not a83a) );
a85a <=( (not A201) and (not a84a) );
a86a <=( (not a81a) and (not a85a) );
a87a <=( (not a57a) and (not a86a) );
a88a <=( A168 and a50a );
a89a <=( a84a and (not a88a) );
a90a <=( (not a71a) and (not a89a) );
a91a <=( (not A201) and (not A168) );
a92a <=( a57a and a91a );
a93a <=( a50a and a92a );
a94a <=( a76a and a93a );
a95a <=( (not A236) and (not A235) );
a96a <=( A299 and (not A298) );
a97a <=( (not A299) and A298 );
a98a <=( (not a96a) and (not a97a) );
a99a <=( (not A302) and (not A301) );
a100a <=( A300 and (not a99a) );
a101a <=( (not A302) and (not A300) );
a102a <=( (not A301) and a101a );
a103a <=( (not a100a) and (not a102a) );
a104a <=( (not a98a) and (not a103a) );
a105a <=( A266 and (not A265) );
a106a <=( (not A266) and A265 );
a107a <=( (not a105a) and (not a106a) );
a108a <=( (not A269) and (not A268) );
a109a <=( A267 and (not a108a) );
a110a <=( (not A269) and (not A267) );
a111a <=( (not A268) and a110a );
a112a <=( (not a109a) and (not a111a) );
a113a <=( (not a107a) and (not a112a) );
a114a <=( (not a104a) and (not a113a) );
a115a <=( (not A234) and (not a114a) );
a116a <=( (not A233) and A232 );
a117a <=( A233 and (not A232) );
a118a <=( (not a116a) and (not a117a) );
a119a <=( (not A267) and (not a108a) );
a120a <=( (not A269) and A267 );
a121a <=( (not A268) and a120a );
a122a <=( A266 and A265 );
a123a <=( (not A266) and (not A265) );
a124a <=( (not a122a) and (not a123a) );
a125a <=( (not a121a) and a124a );
a126a <=( (not a119a) and a125a );
a127a <=( (not A300) and (not a99a) );
a128a <=( (not A302) and A300 );
a129a <=( (not A301) and a128a );
a130a <=( A299 and A298 );
a131a <=( (not A299) and (not A298) );
a132a <=( (not a130a) and (not a131a) );
a133a <=( (not a129a) and a132a );
a134a <=( (not a127a) and a133a );
a135a <=( (not a126a) and (not a134a) );
a136a <=( (not a118a) and a135a );
a137a <=( A234 and a136a );
a138a <=( (not a115a) and (not a137a) );
a139a <=( (not a95a) and (not a138a) );
a140a <=( (not A236) and A234 );
a141a <=( (not A235) and a140a );
a142a <=( A233 and A232 );
a143a <=( (not A233) and (not A232) );
a144a <=( (not a142a) and (not a143a) );
a145a <=( (not a141a) and a144a );
a146a <=( (not a98a) and (not a145a) );
a147a <=( (not a103a) and a146a );
a148a <=( (not a107a) and (not a145a) );
a149a <=( (not a112a) and a148a );
a150a <=( (not A236) and (not A234) );
a151a <=( (not A235) and a150a );
a152a <=( a136a and a151a );
a153a <=( (not a90a) and (not a94a) );
a154a <=( (not a149a) and a153a );
a155a <=( (not a147a) and a154a );
a156a <=( (not a152a) and a155a );
a157a <=( (not a75a) and a156a );
a158a <=( (not a87a) and a157a );
A142 <=( (not a139a) and a158a );
a160a <=( A168 and (not a50a) );
a161a <=( (not A168) and a50a );
a162a <=( (not a160a) and (not a161a) );
a163a <=( (not A234) and (not a95a) );
a164a <=( a145a and (not a163a) );
a165a <=( (not a62a) and a164a );
a166a <=( (not a135a) and a165a );
a167a <=( (not a53a) and (not a162a) );
a168a <=( (not a166a) and a167a );
a169a <=( (not A168) and (not a50a) );
a170a <=( a89a and (not a169a) );
a171a <=( (not a72a) and (not a170a) );
A141 <=( (not a168a) and (not a171a) );
a173a <=( A234 and (not a95a) );
a174a <=( (not a151a) and (not a173a) );
a175a <=( (not a118a) and (not a174a) );
a176a <=( (not a61a) and a175a );
a177a <=( (not a61a) and a104a );
a178a <=( (not a170a) and a177a );
a179a <=( (not a176a) and (not a178a) );
a180a <=( (not a56a) and (not a179a) );
a181a <=( (not a162a) and a175a );
a182a <=( a104a and (not a162a) );
a183a <=( (not a72a) and a182a );
a184a <=( (not a181a) and (not a183a) );
a185a <=( (not a53a) and (not a184a) );
a186a <=( (not a113a) and (not a185a) );
a187a <=( (not a180a) and a186a );
a188a <=( (not A267) and (not A168) );
a189a <=( a104a and a188a );
a190a <=( A168 and (not a107a) );
a191a <=( (not a53a) and a190a );
a192a <=( (not a134a) and a191a );
a193a <=( A267 and a192a );
a194a <=( (not a189a) and (not a193a) );
a195a <=( (not a108a) and (not a194a) );
a196a <=( (not A168) and (not a98a) );
a197a <=( (not a125a) and a196a );
a198a <=( (not a103a) and a197a );
a199a <=( a111a and a192a );
a200a <=( (not a198a) and (not a199a) );
a201a <=( (not a195a) and a200a );
a202a <=( (not a50a) and (not a201a) );
a203a <=( (not a89a) and a104a );
a204a <=( (not a126a) and a203a );
a205a <=( (not a107a) and a161a );
a206a <=( (not a53a) and a205a );
a207a <=( (not a112a) and a206a );
a208a <=( (not a134a) and a207a );
a209a <=( (not a204a) and (not a208a) );
a210a <=( (not a202a) and a209a );
a211a <=( (not a61a) and (not a210a) );
a212a <=( (not a176a) and (not a211a) );
a213a <=( (not a56a) and (not a212a) );
a214a <=( (not a72a) and (not a126a) );
a215a <=( a182a and a214a );
a216a <=( (not a181a) and (not a215a) );
a217a <=( (not a53a) and (not a216a) );
a218a <=( a113a and (not a134a) );
a219a <=( a171a and a218a );
a220a <=( (not a217a) and (not a219a) );
a221a <=( (not a213a) and a220a );
a222a <=( (not a98a) and (not a118a) );
a223a <=( (not a126a) and a222a );
a224a <=( A234 and a223a );
a225a <=( A300 and a224a );
a226a <=( (not A300) and (not A234) );
a227a <=( (not a225a) and (not a226a) );
a228a <=( (not a99a) and (not a227a) );
a229a <=( (not A300) and a224a );
a230a <=( A300 and (not A234) );
a231a <=( (not a229a) and (not a230a) );
a232a <=( a99a and (not a231a) );
a233a <=( (not a113a) and a132a );
a234a <=( (not A234) and (not a233a) );
a235a <=( (not a232a) and (not a234a) );
a236a <=( (not a228a) and a235a );
a237a <=( (not a95a) and (not a236a) );
a238a <=( (not A300) and (not a145a) );
a239a <=( a151a and a223a );
a240a <=( A300 and a239a );
a241a <=( (not a238a) and (not a240a) );
a242a <=( (not a99a) and (not a241a) );
a243a <=( (not a113a) and a133a );
a244a <=( (not a145a) and (not a243a) );
a245a <=( a102a and a239a );
a246a <=( a153a and (not a244a) );
a247a <=( (not a245a) and a246a );
a248a <=( (not a75a) and a247a );
a249a <=( (not a87a) and a248a );
a250a <=( (not a242a) and a249a );
A138 <=( (not a237a) and a250a );
a252a <=( A234 and (not A233) );
a253a <=( (not a95a) and a252a );
a254a <=( A232 and (not a253a) );
a255a <=( (not a143a) and (not a254a) );
a256a <=( A300 and a97a );
a257a <=( (not a99a) and a256a );
a258a <=( A267 and a106a );
a259a <=( (not a108a) and a258a );
a260a <=( (not a96a) and (not a105a) );
a261a <=( (not a259a) and a260a );
a262a <=( (not a257a) and a261a );
a263a <=( (not a255a) and (not a262a) );
a264a <=( A169 and (not A170) );
a265a <=( (not A167) and a264a );
a266a <=( A167 and a50a );
a267a <=( (not a265a) and (not a266a) );
a268a <=( (not A166) and (not a267a) );
a269a <=( A166 and a264a );
a270a <=( (not A168) and (not a269a) );
a271a <=( A167 and (not a270a) );
a272a <=( (not A167) and a50a );
a273a <=( (not A168) and (not a272a) );
a274a <=( A166 and (not a273a) );
a275a <=( (not a271a) and (not a274a) );
a276a <=( (not a268a) and a275a );
a277a <=( A201 and a54a );
a278a <=( (not a57a) and a277a );
a279a <=( (not a55a) and (not a278a) );
a280a <=( (not a276a) and (not a279a) );
a281a <=( A201 and (not A200) );
a282a <=( (not a57a) and a281a );
a283a <=( A199 and (not a282a) );
a284a <=( (not a69a) and (not a283a) );
a285a <=( (not A167) and A169 );
a286a <=( A167 and (not A169) );
a287a <=( (not a285a) and (not a286a) );
a288a <=( A166 and (not a287a) );
a289a <=( (not A170) and (not a51a) );
a290a <=( A169 and (not a289a) );
a291a <=( (not A169) and (not A170) );
a292a <=( (not a290a) and (not a291a) );
a293a <=( (not a288a) and a292a );
a294a <=( (not A168) and (not a293a) );
a295a <=( a83a and (not a264a) );
a296a <=( (not a294a) and (not a295a) );
a297a <=( (not a284a) and (not a296a) );
a298a <=( A234 and a116a );
a299a <=( (not a95a) and a298a );
a300a <=( (not a117a) and (not a299a) );
a301a <=( A267 and A265 );
a302a <=( (not a108a) and a301a );
a303a <=( (not A266) and (not a302a) );
a304a <=( (not a122a) and (not a303a) );
a305a <=( A300 and A298 );
a306a <=( (not a99a) and a305a );
a307a <=( (not A299) and (not a306a) );
a308a <=( (not a130a) and (not a307a) );
a309a <=( (not a304a) and (not a308a) );
a310a <=( (not a300a) and a309a );
a311a <=( (not a263a) and (not a310a) );
a312a <=( (not a280a) and a311a );
A109 <=( (not a297a) and a312a );
a314a <=( (not a55a) and (not a143a) );
a315a <=( (not a254a) and a314a );
a316a <=( (not a278a) and a315a );
a317a <=( (not a309a) and a316a );
a318a <=( (not a276a) and (not a317a) );
A108 <=( (not a297a) and (not a318a) );
a320a <=( (not a96a) and (not a257a) );
a321a <=( (not a296a) and (not a320a) );
a322a <=( a300a and (not a321a) );
a323a <=( (not a279a) and (not a322a) );
a324a <=( (not a284a) and (not a320a) );
a325a <=( a300a and (not a324a) );
a326a <=( (not a276a) and (not a325a) );
a327a <=( (not a105a) and (not a259a) );
a328a <=( (not a326a) and a327a );
a329a <=( (not a323a) and a328a );
a330a <=( (not a308a) and (not a327a) );
a331a <=( (not a276a) and a330a );
a332a <=( (not a304a) and (not a320a) );
a333a <=( (not a296a) and a332a );
a334a <=( a300a and (not a331a) );
a335a <=( (not a333a) and a334a );
a336a <=( (not a279a) and (not a335a) );
a337a <=( (not a284a) and (not a304a) );
a338a <=( (not a320a) and a337a );
a339a <=( a300a and (not a338a) );
a340a <=( (not a276a) and (not a339a) );
a341a <=( (not a284a) and (not a308a) );
a342a <=( (not a327a) and a341a );
a343a <=( (not a296a) and a342a );
a344a <=( (not a340a) and (not a343a) );
a345a <=( (not a336a) and a344a );
a346a <=( (not a105a) and (not a130a) );
a347a <=( (not a307a) and a346a );
a348a <=( (not a259a) and a347a );
a349a <=( (not a255a) and (not a348a) );
a350a <=( (not a300a) and a332a );
a351a <=( (not a349a) and (not a350a) );
a352a <=( (not a280a) and a351a );
A105 <=( (not a297a) and a352a );
a354a <=( A236 and (not a142a) );
a355a <=( (not A234) and (not a354a) );
a356a <=( (not a143a) and (not a355a) );
a357a <=( A302 and (not a98a) );
a358a <=( A300 and (not a131a) );
a359a <=( A269 and (not a107a) );
a360a <=( A267 and (not a123a) );
a361a <=( (not A301) and (not A268) );
a362a <=( (not a360a) and a361a );
a363a <=( (not a358a) and a362a );
a364a <=( (not a357a) and (not a359a) );
a365a <=( a363a and a364a );
a366a <=( (not A235) and (not a356a) );
a367a <=( (not a365a) and a366a );
a368a <=( A170 and (not a82a) );
a369a <=( (not A168) and (not a368a) );
a370a <=( (not a83a) and (not a369a) );
a371a <=( A203 and (not a68a) );
a372a <=( (not A201) and (not a371a) );
a373a <=( (not a69a) and (not a372a) );
a374a <=( (not A202) and (not A169) );
a375a <=( (not a373a) and a374a );
a376a <=( (not a370a) and a375a );
a377a <=( (not A167) and A170 );
a378a <=( (not A168) and (not a377a) );
a379a <=( A166 and (not a378a) );
a380a <=( (not A166) and A170 );
a381a <=( (not A168) and (not a380a) );
a382a <=( A167 and (not a381a) );
a383a <=( (not A169) and (not a382a) );
a384a <=( (not a379a) and a383a );
a385a <=( A203 and (not a56a) );
a386a <=( A201 and (not a69a) );
a387a <=( (not A202) and (not a386a) );
a388a <=( (not a385a) and a387a );
a389a <=( (not a384a) and (not a388a) );
a390a <=( A269 and (not a122a) );
a391a <=( (not A267) and (not a390a) );
a392a <=( (not a123a) and (not a391a) );
a393a <=( A302 and (not a130a) );
a394a <=( (not A300) and (not a393a) );
a395a <=( (not a131a) and (not a394a) );
a396a <=( A236 and (not a118a) );
a397a <=( A234 and (not a143a) );
a398a <=( (not A235) and (not a397a) );
a399a <=( (not a396a) and a398a );
a400a <=( a361a and (not a399a) );
a401a <=( (not a392a) and (not a395a) );
a402a <=( a400a and a401a );
a403a <=( (not a389a) and (not a402a) );
a404a <=( (not a367a) and (not a376a) );
A76 <=( a403a and a404a );
a406a <=( a361a and (not a395a) );
a407a <=( (not a392a) and a406a );
a408a <=( (not a366a) and a388a );
a409a <=( (not a407a) and a408a );
a410a <=( (not a384a) and (not a409a) );
A75 <=( (not a376a) and (not a410a) );
a412a <=( (not A301) and (not a358a) );
a413a <=( (not a357a) and a412a );
a414a <=( (not A169) and (not a413a) );
a415a <=( (not a370a) and a414a );
a416a <=( a399a and (not a415a) );
a417a <=( (not a388a) and (not a416a) );
a418a <=( (not A202) and (not a413a) );
a419a <=( (not a373a) and a418a );
a420a <=( a399a and (not a419a) );
a421a <=( (not a384a) and (not a420a) );
a422a <=( (not A268) and (not a360a) );
a423a <=( (not a359a) and a422a );
a424a <=( (not a421a) and a423a );
a425a <=( (not a417a) and a424a );
a426a <=( (not a392a) and (not a413a) );
a427a <=( (not A268) and (not A169) );
a428a <=( (not a370a) and a427a );
a429a <=( a426a and a428a );
a430a <=( (not A301) and (not a423a) );
a431a <=( (not a395a) and a430a );
a432a <=( (not a384a) and a431a );
a433a <=( a399a and (not a429a) );
a434a <=( (not a432a) and a433a );
a435a <=( (not a388a) and (not a434a) );
a436a <=( (not A268) and (not A202) );
a437a <=( (not a373a) and a436a );
a438a <=( a426a and a437a );
a439a <=( a399a and (not a438a) );
a440a <=( (not a384a) and (not a439a) );
a441a <=( (not A301) and a374a );
a442a <=( (not a423a) and a441a );
a443a <=( (not a373a) and (not a395a) );
a444a <=( (not a370a) and a443a );
a445a <=( a442a and a444a );
a446a <=( (not a440a) and (not a445a) );
a447a <=( (not a435a) and a446a );
a448a <=( (not A301) and (not a395a) );
a449a <=( a423a and (not a448a) );
a450a <=( a366a and (not a449a) );
a451a <=( (not A268) and (not a413a) );
a452a <=( (not a392a) and (not a399a) );
a453a <=( a451a and a452a );
a454a <=( (not a389a) and (not a453a) );
a455a <=( (not a376a) and a454a );
A72 <=( (not a450a) and a455a );
a457a <=( (not A203) and A202 );
a458a <=( (not a70a) and a457a );
a459a <=( (not A202) and a385a );
a460a <=( (not a386a) and (not a458a) );
a461a <=( (not a459a) and a460a );
a462a <=( A168 and (not a291a) );
a463a <=( a52a and a462a );
a464a <=( (not a51a) and (not a463a) );
a465a <=( (not a461a) and (not a464a) );
a466a <=( A166 and a462a );
a467a <=( (not A167) and (not a466a) );
a468a <=( (not a82a) and (not a467a) );
a469a <=( A203 and (not A202) );
a470a <=( (not a56a) and (not a469a) );
a471a <=( a68a and (not a457a) );
a472a <=( (not a470a) and (not a471a) );
a473a <=( (not a468a) and (not a472a) );
a474a <=( (not A201) and a473a );
a475a <=( a69a and (not a457a) );
a476a <=( (not a468a) and a475a );
a477a <=( A236 and (not A235) );
a478a <=( (not A302) and A301 );
a479a <=( (not a132a) and a478a );
a480a <=( (not A301) and a357a );
a481a <=( (not A269) and A268 );
a482a <=( (not a124a) and a481a );
a483a <=( (not A268) and a359a );
a484a <=( (not a360a) and (not a482a) );
a485a <=( (not a483a) and a484a );
a486a <=( (not a358a) and (not a479a) );
a487a <=( (not a480a) and a486a );
a488a <=( a485a and a487a );
a489a <=( (not A234) and (not a477a) );
a490a <=( (not a488a) and a489a );
a491a <=( A269 and (not A268) );
a492a <=( A302 and (not A301) );
a493a <=( (not a98a) and (not a492a) );
a494a <=( a130a and (not a478a) );
a495a <=( (not a493a) and (not a494a) );
a496a <=( (not a107a) and (not a491a) );
a497a <=( (not a495a) and a496a );
a498a <=( a122a and (not a481a) );
a499a <=( (not a495a) and a498a );
a500a <=( (not a497a) and (not a499a) );
a501a <=( (not A300) and (not a500a) );
a502a <=( (not a496a) and (not a498a) );
a503a <=( a131a and (not a478a) );
a504a <=( (not a502a) and a503a );
a505a <=( (not a501a) and (not a504a) );
a506a <=( (not A267) and (not a505a) );
a507a <=( (not A300) and (not a495a) );
a508a <=( (not a503a) and (not a507a) );
a509a <=( a123a and (not a481a) );
a510a <=( (not a508a) and a509a );
a511a <=( (not a506a) and (not a510a) );
a512a <=( a477a and (not a511a) );
a513a <=( (not a490a) and (not a512a) );
a514a <=( (not a118a) and (not a513a) );
a515a <=( (not A234) and a142a );
a516a <=( (not a143a) and (not a515a) );
a517a <=( (not A236) and A235 );
a518a <=( (not a516a) and (not a517a) );
a519a <=( (not a488a) and a518a );
a520a <=( (not a144a) and a517a );
a521a <=( (not a397a) and (not a520a) );
a522a <=( (not A300) and (not a521a) );
a523a <=( (not a500a) and a522a );
a524a <=( (not a502a) and (not a521a) );
a525a <=( a503a and a524a );
a526a <=( (not a523a) and (not a525a) );
a527a <=( (not A267) and (not a526a) );
a528a <=( (not a495a) and a522a );
a529a <=( a503a and (not a521a) );
a530a <=( (not a528a) and (not a529a) );
a531a <=( a509a and (not a530a) );
a532a <=( (not a465a) and (not a476a) );
a533a <=( (not a519a) and a532a );
a534a <=( (not a474a) and a533a );
a535a <=( (not a531a) and a534a );
a536a <=( (not a527a) and a535a );
A43 <=( (not a514a) and a536a );
a538a <=( (not a118a) and (not a477a) );
a539a <=( a142a and (not a517a) );
a540a <=( (not a538a) and (not a539a) );
a541a <=( (not A234) and (not a540a) );
a542a <=( (not a464a) and a541a );
a543a <=( a143a and (not a517a) );
a544a <=( (not a386a) and (not a543a) );
a545a <=( (not a458a) and a544a );
a546a <=( (not a459a) and a545a );
a547a <=( a511a and a546a );
a548a <=( (not a464a) and (not a547a) );
a549a <=( (not a476a) and (not a542a) );
a550a <=( (not a474a) and a549a );
A42 <=( (not a548a) and a550a );
a552a <=( (not A235) and a396a );
a553a <=( a521a and (not a552a) );
a554a <=( a460a and a464a );
a555a <=( (not a459a) and a554a );
a556a <=( (not a553a) and (not a555a) );
a557a <=( (not a468a) and (not a487a) );
a558a <=( (not a461a) and a557a );
a559a <=( (not a464a) and (not a472a) );
a560a <=( (not a487a) and a559a );
a561a <=( (not A201) and a560a );
a562a <=( (not a464a) and (not a487a) );
a563a <=( a475a and a562a );
a564a <=( a485a and (not a563a) );
a565a <=( (not a558a) and (not a561a) );
a566a <=( (not a556a) and a565a );
a567a <=( a564a and a566a );
a568a <=( (not a464a) and a507a );
a569a <=( (not a464a) and a503a );
a570a <=( (not a568a) and (not a569a) );
a571a <=( (not a485a) and (not a570a) );
a572a <=( (not A267) and (not a502a) );
a573a <=( (not a468a) and a572a );
a574a <=( (not a487a) and a573a );
a575a <=( a509a and a557a );
a576a <=( (not a574a) and (not a575a) );
a577a <=( (not a571a) and a576a );
a578a <=( (not a461a) and (not a577a) );
a579a <=( (not A300) and a491a );
a580a <=( (not a492a) and a579a );
a581a <=( a473a and a580a );
a582a <=( A302 and (not A267) );
a583a <=( (not A301) and a582a );
a584a <=( (not a491a) and a583a );
a585a <=( a559a and a584a );
a586a <=( (not a581a) and (not a585a) );
a587a <=( (not a98a) and (not a586a) );
a588a <=( (not A300) and a130a );
a589a <=( (not a131a) and (not a588a) );
a590a <=( (not a478a) and a491a );
a591a <=( (not a589a) and a590a );
a592a <=( a473a and a591a );
a593a <=( (not A267) and (not a491a) );
a594a <=( (not a486a) and a593a );
a595a <=( a559a and a594a );
a596a <=( (not a592a) and (not a595a) );
a597a <=( (not a587a) and a596a );
a598a <=( (not a107a) and (not a597a) );
a599a <=( (not A267) and a122a );
a600a <=( (not a123a) and (not a599a) );
a601a <=( (not a481a) and (not a600a) );
a602a <=( a560a and a601a );
a603a <=( a470a and (not a495a) );
a604a <=( a471a and (not a495a) );
a605a <=( (not a603a) and (not a604a) );
a606a <=( (not A300) and (not a484a) );
a607a <=( (not a468a) and a606a );
a608a <=( (not a605a) and a607a );
a609a <=( (not a484a) and a503a );
a610a <=( (not a472a) and a609a );
a611a <=( (not a468a) and a610a );
a612a <=( (not a608a) and (not a611a) );
a613a <=( (not a602a) and a612a );
a614a <=( (not a598a) and a613a );
a615a <=( (not A201) and (not a614a) );
a616a <=( (not a468a) and a580a );
a617a <=( (not a464a) and a584a );
a618a <=( (not a616a) and (not a617a) );
a619a <=( (not a98a) and (not a618a) );
a620a <=( (not a468a) and a591a );
a621a <=( (not a464a) and a594a );
a622a <=( (not a620a) and (not a621a) );
a623a <=( (not a619a) and a622a );
a624a <=( (not a107a) and (not a623a) );
a625a <=( a562a and a601a );
a626a <=( (not a495a) and a606a );
a627a <=( (not a468a) and a626a );
a628a <=( (not a468a) and a609a );
a629a <=( (not a627a) and (not a628a) );
a630a <=( (not a625a) and a629a );
a631a <=( (not a624a) and a630a );
a632a <=( a475a and (not a631a) );
a633a <=( (not a556a) and (not a578a) );
a634a <=( (not a632a) and a633a );
a635a <=( (not a615a) and a634a );
a636a <=( a485a and (not a503a) );
a637a <=( (not a507a) and a636a );
a638a <=( a489a and (not a637a) );
a639a <=( (not a487a) and a572a );
a640a <=( (not a487a) and a509a );
a641a <=( (not a639a) and (not a640a) );
a642a <=( a477a and (not a641a) );
a643a <=( (not a638a) and (not a642a) );
a644a <=( (not a118a) and (not a643a) );
a645a <=( a518a and (not a637a) );
a646a <=( (not A267) and (not a487a) );
a647a <=( a524a and a646a );
a648a <=( a509a and (not a521a) );
a649a <=( (not a487a) and a648a );
a650a <=( (not a476a) and (not a649a) );
a651a <=( (not a465a) and a650a );
a652a <=( (not a474a) and (not a647a) );
a653a <=( a651a and a652a );
a654a <=( (not a645a) and a653a );
A39 <=( (not a644a) and a654a );
a656a <=( A300 and (not a492a) );
a657a <=( A302 and (not A300) );
a658a <=( (not A301) and a657a );
a659a <=( (not a656a) and (not a658a) );
a660a <=( (not a98a) and (not a107a) );
a661a <=( (not a659a) and a660a );
a662a <=( A267 and a661a );
a663a <=( (not A300) and (not a492a) );
a664a <=( A302 and A300 );
a665a <=( (not A301) and a664a );
a666a <=( a132a and (not a665a) );
a667a <=( (not a663a) and a666a );
a668a <=( (not A267) and (not a667a) );
a669a <=( (not a662a) and (not a668a) );
a670a <=( (not a491a) and (not a669a) );
a671a <=( (not A267) and (not a107a) );
a672a <=( (not a98a) and a671a );
a673a <=( A300 and a672a );
a674a <=( (not A300) and A267 );
a675a <=( (not a673a) and (not a674a) );
a676a <=( a491a and (not a675a) );
a677a <=( (not A300) and (not a124a) );
a678a <=( (not a676a) and (not a677a) );
a679a <=( (not a492a) and (not a678a) );
a680a <=( A269 and A267 );
a681a <=( (not A268) and a680a );
a682a <=( a124a and (not a681a) );
a683a <=( (not a666a) and (not a682a) );
a684a <=( a491a and a658a );
a685a <=( a672a and a684a );
a686a <=( A201 and (not a469a) );
a687a <=( A203 and (not A201) );
a688a <=( (not A202) and a687a );
a689a <=( (not a686a) and (not a688a) );
a690a <=( (not a56a) and (not a689a) );
a691a <=( (not A168) and (not a291a) );
a692a <=( A168 and a291a );
a693a <=( a84a and (not a692a) );
a694a <=( (not a691a) and a693a );
a695a <=( (not a690a) and a694a );
a696a <=( (not A234) and (not a695a) );
a697a <=( (not A168) and a291a );
a698a <=( (not a462a) and (not a697a) );
a699a <=( (not A201) and (not a469a) );
a700a <=( A203 and A201 );
a701a <=( (not A202) and a700a );
a702a <=( a70a and (not a701a) );
a703a <=( (not a699a) and a702a );
a704a <=( A234 and (not a118a) );
a705a <=( (not a53a) and a704a );
a706a <=( (not a698a) and a705a );
a707a <=( (not a703a) and a706a );
a708a <=( (not a696a) and (not a707a) );
a709a <=( (not a477a) and (not a708a) );
a710a <=( A236 and A234 );
a711a <=( (not A235) and a710a );
a712a <=( a144a and (not a711a) );
a713a <=( (not a56a) and (not a712a) );
a714a <=( (not a689a) and a713a );
a715a <=( (not A168) and (not a712a) );
a716a <=( (not a53a) and (not a118a) );
a717a <=( (not a703a) and a716a );
a718a <=( (not A234) and A168 );
a719a <=( a477a and a718a );
a720a <=( a717a and a719a );
a721a <=( (not a715a) and (not a720a) );
a722a <=( (not a291a) and (not a721a) );
a723a <=( (not a693a) and (not a712a) );
a724a <=( (not A234) and (not A168) );
a725a <=( a477a and a724a );
a726a <=( a291a and a725a );
a727a <=( a717a and a726a );
a728a <=( (not a683a) and (not a723a) );
a729a <=( (not a714a) and a728a );
a730a <=( (not a685a) and a729a );
a731a <=( (not a727a) and a730a );
a732a <=( (not a670a) and a731a );
a733a <=( (not a709a) and (not a722a) );
a734a <=( a732a and a733a );
A6 <=( (not a679a) and a734a );
a736a <=( (not a53a) and (not a698a) );
a737a <=( a703a and (not a736a) );
a738a <=( (not A267) and (not a737a) );
a739a <=( (not a489a) and a712a );
a740a <=( (not a694a) and (not a739a) );
a741a <=( A267 and (not a107a) );
a742a <=( a740a and a741a );
a743a <=( (not a738a) and (not a742a) );
a744a <=( (not A300) and (not a743a) );
a745a <=( (not a53a) and (not a107a) );
a746a <=( A267 and A168 );
a747a <=( a745a and a746a );
a748a <=( (not a188a) and (not a747a) );
a749a <=( (not a291a) and (not a739a) );
a750a <=( (not a748a) and a749a );
a751a <=( A267 and (not A168) );
a752a <=( a745a and a751a );
a753a <=( (not A267) and A168 );
a754a <=( (not a752a) and (not a753a) );
a755a <=( a291a and (not a754a) );
a756a <=( (not A267) and (not a84a) );
a757a <=( (not a755a) and (not a756a) );
a758a <=( (not a739a) and (not a757a) );
a759a <=( (not a750a) and (not a758a) );
a760a <=( (not a98a) and (not a759a) );
a761a <=( A300 and a760a );
a762a <=( (not a744a) and (not a761a) );
a763a <=( (not a492a) and (not a762a) );
a764a <=( (not a666a) and (not a743a) );
a765a <=( a658a and a760a );
a766a <=( (not a764a) and (not a765a) );
a767a <=( (not a763a) and a766a );
a768a <=( (not a491a) and (not a767a) );
a769a <=( (not A300) and (not a737a) );
a770a <=( (not a98a) and a740a );
a771a <=( A300 and a770a );
a772a <=( (not a769a) and (not a771a) );
a773a <=( (not a492a) and (not a772a) );
a774a <=( (not a666a) and (not a737a) );
a775a <=( a658a and a770a );
a776a <=( (not a774a) and (not a775a) );
a777a <=( (not a773a) and a776a );
a778a <=( (not a682a) and (not a777a) );
a779a <=( a690a and (not a739a) );
a780a <=( A269 and (not A267) );
a781a <=( (not A268) and a780a );
a782a <=( (not a98a) and a781a );
a783a <=( (not a107a) and a782a );
a784a <=( (not a659a) and a783a );
a785a <=( (not a739a) and a784a );
a786a <=( (not a779a) and (not a785a) );
a787a <=( a63a and (not a786a) );
a788a <=( (not a107a) and a781a );
a789a <=( (not a667a) and a788a );
a790a <=( a703a and (not a789a) );
a791a <=( (not A168) and (not a739a) );
a792a <=( (not a790a) and a791a );
a793a <=( (not a787a) and (not a792a) );
a794a <=( (not a291a) and (not a793a) );
a795a <=( a661a and a781a );
a796a <=( (not a690a) and (not a795a) );
a797a <=( (not A168) and (not a53a) );
a798a <=( (not a796a) and a797a );
a799a <=( A168 and (not a790a) );
a800a <=( (not a798a) and (not a799a) );
a801a <=( a291a and (not a800a) );
a802a <=( (not a84a) and (not a790a) );
a803a <=( (not a801a) and (not a802a) );
a804a <=( (not a739a) and (not a803a) );
a805a <=( (not a794a) and (not a804a) );
a806a <=( (not a778a) and a805a );
A7 <=( (not a768a) and a806a );
a808a <=( A234 and (not a477a) );
a809a <=( A236 and (not A234) );
a810a <=( (not A235) and a809a );
a811a <=( (not a808a) and (not a810a) );
a812a <=( (not a98a) and (not a811a) );
a813a <=( (not a659a) and a812a );
a814a <=( A267 and (not a491a) );
a815a <=( (not a781a) and (not a814a) );
a816a <=( (not a107a) and (not a815a) );
a817a <=( (not a811a) and a816a );
a818a <=( (not a813a) and (not a817a) );
a819a <=( (not a118a) and (not a818a) );
a820a <=( (not a593a) and a682a );
a821a <=( (not a98a) and (not a659a) );
a822a <=( (not a820a) and a821a );
a823a <=( (not a667a) and a816a );
a824a <=( (not a822a) and (not a823a) );
a825a <=( a736a and (not a824a) );
a826a <=( (not a690a) and (not a825a) );
a827a <=( (not a819a) and a826a );
a828a <=( (not a694a) and (not a703a) );
a829a <=( (not a489a) and (not a663a) );
a830a <=( a712a and a829a );
a831a <=( a666a and a830a );
a832a <=( (not a828a) and a831a );
a833a <=( (not A267) and (not a832a) );
a834a <=( (not a662a) and (not a833a) );
a835a <=( (not a491a) and (not a834a) );
a836a <=( (not a682a) and (not a832a) );
a837a <=( (not a795a) and (not a836a) );
A9 <=( (not a835a) and a837a );
a839a <=( (not a690a) and (not a736a) );
a840a <=( (not A234) and (not a839a) );
a841a <=( (not a118a) and a828a );
a842a <=( A234 and a841a );
a843a <=( (not a840a) and (not a842a) );
a844a <=( (not a477a) and (not a843a) );
a845a <=( (not a53a) and (not a712a) );
a846a <=( (not a698a) and a845a );
a847a <=( a810a and a841a );
a848a <=( (not a683a) and (not a846a) );
a849a <=( (not a685a) and (not a714a) );
a850a <=( a848a and a849a );
a851a <=( (not a847a) and a850a );
a852a <=( (not a670a) and a851a );
a853a <=( (not a844a) and a852a );
A10 <=( (not a679a) and a853a );
A140 <=( (not a187a) );
A139 <=( (not a221a) );
A107 <=( (not a329a) );
A106 <=( (not a345a) );
A74 <=( (not a425a) );
A73 <=( (not a447a) );
A41 <=( (not a567a) );
A40 <=( (not a635a) );
A8 <=( (not a827a) );
end testing_behav;
| gpl-3.0 | 7faf5ac46a76412bcd0ecdb13fbc17bd | 0.581419 | 2.006304 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/microblaze_types_pkg.vhd | 1 | 13,071 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
F38K0TiQb7M3B98eBpn5bolStEqZ3mfpoQo/VKW+34Wg/9DYgc1Y9OXw617TVDXhRwUlu8EJxNbh
MJ5czPA62A==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
ax+w44Vii6thdsoLUGs9RVPy1GHUfCsZ72DAMssSf49xnRS2MkjE+NIMUt4Jw/UeKRL6GqS2u9cY
R/srsxiKSrNipqX+TEjcNX77+SHx4twc/zOz2HHx2OcOyr2ybX/RlMFoC/5pyJuPJX7zMCGmsOfB
t54AStlt1Sq6Rj6huj8=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
TtkF/k73zzfLPVgrYbYRFqBzydKXJyE9H8FUPYiKGp1nIqjq/7o72tqDmLAXmMLixGFduRCldKRp
sSi2n5YbeuZqXQVPvkZ7Ejl2mVL7jvc/EUlEVUP1ut1usV8SvEYHzoCtYIu6DULYyPd+FVrIhM4C
WJujOrP9bIV3xsg/rJ/Xgokt5cBLJ0kMNKL5GngSXLt09Ibu3+92zDtaUc/wZVz4LZzKFlA7ZBdk
KR3HJWw9ZODW8MmPQWaCjYsiq+GhvhWvFzPR4qFJPyurbKtXDAl2ha3yEq7ne6ajM1Mk2mkIezdK
c71zzTg80kHyeEKzZO9NA66NprXMM2Ueu4doYg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
yRwrnBZMY62RFWLB7Ani1nh0E8qLHmopm4Pe3pH//hATPz2ZGWx4P3Qe+4SU7esIePBfyNjxh4Rk
ayY0wSI3K2FyO5nLw3VhBdw6Y63xRwV9F0+Az3RWN9pM1AUH5lnCKx64vZGM4vJktfej5F8tT2Ik
JfA8JBf7LPVJUzJq+fw=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
adkidPwGI7UeQLbMkxpiALN0Kuw9/9hLO6pyb/hwyjVvPVgbBeTDx1sLTLPaD8k2NIlZRGCrXaEM
7HkNNUpTp4GZWMms1G4bowvpx6QrIZsu7mZ4dqLpWNcRpC0XFuPw7prt9h1DsAc+cNlMlCb03Rkw
3HI31v9YoL28V2F8kr4T0UZz2kFlkVOpVHNlxLOZKcKt7VBFpNhCSNAWy+zcQH7+mCQo4FypJ1ju
ynv2A61aORBtSSgG4btlMoNH7mCW65Ldpz0q7+lZmErmnhz7y8bIPFHJz2U/xIoY3/7X3cz/6AtZ
IvXi1Hzvrwq6/LMxdVSYz3ilVxD5DKuVPiddFw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7936)
`protect data_block
o7qLriJD+bAkd0CCQq/6BYrXAvHkXyY5X+VB+hf780/mqbAAWl00gEf8dT1CSxF3uEa7cDfjpu7C
93d0NTLUBUuo0H2c/RFlNfnis7hPgIN26GVl8JO8gFQvIpb/wbbh/wTzDyxEN0SCqNjMwK/wLyYB
X32mfxBp1v95go6o3hLYBIqaHbX6HyCLmsHiEguils5Fub8T8DDKy9e3X2VEI0eVvzkDdxvdAF5B
vsmEjyCp3JajOdiLYdyoyMiSqe1ltvmlXqdSFA99VH9Q0of8eVPs7CneFtgk7SzpQ2MmoJXfOtgE
cuc3JfcsZp/Vy5D2XICWCDLuSoJ4Ahqua1PU1/7ZqpB1rWXKW2LXvNXG+UJJxCJTeYxMOfqG/+2r
Kn6v2tUCorRKI1A4jqvSDnZROzEmeOp6DEoqRugtTzcMXakqscE5a4wcXHkwU2hyOGx1BWaKvtEU
5su1sJ4TQ2EnhdFryJdYyGPyCe/R/DK1VIj8SHRdWuAVQR/XKcP7nZ1NyvAOvKExnsO1QWSLuAsa
/550k0gbw/lup6BxvSz/ePjeYpdAtTs5tTsQK13UrQM3sq+BsOdoQ9emmWABv1B+WUtCrTtMXSMD
6jADNG46aymsSTq3YJ22viPPfotwTmOD0qSEjb7XoDlzn7YTYGcZryGkyPQ24E2/RFlKwulvoux+
SQVTs0nxXqt7pndFRtnELXIMlH9vWOYKlxhHmmFiJ5t87bQhVModE1y3ubvQa1+5IuMT32egr5ph
bcRvz1z82r7lmX6g3n1XyLyMDycIBXj+mwTdCEA53vJLXfy8pjtAXLTPBARgnZmh4/zlRIvume+e
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| apache-2.0 | 3dbcca5d70e649008561064d1d15cae4 | 0.931528 | 1.877478 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/dynshreg_i_f.vhd | 15 | 20,708 | -------------------------------------------------------------------------------
-- $Id: dynshreg_i_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- dynshreg_i_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
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-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
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-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2007-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: dynshreg_i_f.vhd
--
-- Description: This module implements a dynamic shift register with clock
-- enable. (Think, for example, of the function of the SRL16E.)
-- The width and depth of the shift register are selectable
-- via generics C_WIDTH and C_DEPTH, respectively. The C_FAMILY
-- allows the implementation to be tailored to the target
-- FPGA family. An inferred implementation is used if C_FAMILY
-- is "nofamily" (the default) or if synthesis will not produce
-- an optimal implementation. Otherwise, a structural
-- implementation will be generated.
--
-- There is no restriction on the values of C_WIDTH and
-- C_DEPTH and, in particular, the C_DEPTH does not have
-- to be a power of two.
--
-- This version allows the client to specify the initial value
-- of the contents of the shift register, as applied
-- during configuration.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: FLO
--
-- History:
-- FLO 01/03/07 First Version. Derived from dynshreg_f.
--
-- ~~~~~~
-- FLO 12/20/07
-- ^^^^^^
-- -Now using clog2 instead of log2.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
---(
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.TO_INTEGER;
--
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.clog2;
--------------------------------------------------------------------------------
-- Explanations of generics and ports regarding aspects that may not be obvious.
--
-- C_DWIDTH
--------
-- Theoretically, C_DWIDTH may be set to zero and this could be a more
-- natural or preferrable way of excluding a dynamic shift register
-- in a client than using a VHDL Generate statement. However, this usage is not
-- tested, and the user should expect that some VHDL tools will be deficient
-- with respect to handling this properly.
--
-- C_INIT_VALUE
---------------
-- C_INIT_VALUE can be used to specify the initial values of the elements
-- in the dynamic shift register, i.e. the values to be present after config-
-- uration. C_INIT_VALUE need not be the same size as the dynamic shift
-- register, i.e. C_DWIDTH*C_DEPTH. When smaller, C_INIT_VALUE
-- is replicated as many times as needed (possibly fractionally the last time)
-- to form a full initial value that is the size of the shift register.
-- So, if C_INIT_VALUE is left at its default value--an array of size one
-- whose value is '0'--the shift register will initialize with all bits at
-- all addresses set to '0'. This will also be the case if C_INIT_VALUE is a
-- null (size zero) array.
-- When determined according to the rules outlined above, the full
-- initial value is a std_logic_vector value from (0 to C_DWIDTH*C_DEPTH-1). It
-- is allocated to the addresses of the dynamic shift register in this
-- manner: The first C_DWIDTH values (i.e. 0 to C_CWIDTH-1) assigned to
-- the corresponding indices at address 0, the second C_DWIDTH values
-- assigned to address 1, and so forth.
-- Please note that the shift register is not resettable after configuration.
--
-- Addr
----
-- Addr addresses the elements of the dynamic shift register. Addr=0 causes
-- the most recently shifted-in element to appear at Dout, Addr=1
-- the second most recently shifted in element, etc. If C_DEPTH is not
-- a power of two, then not all of the values of Addr correspond to an
-- element in the shift register. When such an address is applied, the value
-- of Dout is undefined until a valid address is established.
--------------------------------------------------------------------------------
entity dynshreg_i_f is
generic (
C_DEPTH : positive := 32;
C_DWIDTH : natural := 1;
C_INIT_VALUE : bit_vector := "0";
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Clken : in std_logic;
Addr : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Din : in std_logic_vector(0 to C_DWIDTH-1);
Dout : out std_logic_vector(0 to C_DWIDTH-1)
);
end dynshreg_i_f;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
library unisim;
use unisim.all; -- Make unisim entities available for default binding.
architecture behavioral of dynshreg_i_f is
type bv2sl_type is array(bit) of std_logic;
constant bv2sl : bv2sl_type := ('0' => '0', '1' => '1');
function min(a, b: natural) return natural is
begin
if a<b then return a; else return b; end if;
end min;
--
------------------------------------------------------------------------------
-- Function used to establish the full initial value. (See the comments for
-- C_INIT_VALUE, above.)
------------------------------------------------------------------------------
function full_initial_value(w : natural; d : positive; v : bit_vector
) return bit_vector is
variable r : bit_vector(0 to w*d-1);
variable i, j : natural;
-- i - the index where filling of r continues
-- j - the amount to fill on the cur. iteration of the while loop
begin
if w = 0 then null; -- Handle the case where the shift reg width is zero
elsif v'length = 0 then r := (others => '0');
else
i := 0;
while i /= r'length loop
j := min(v'length, r'length-i);
r(i to i+j-1) := v(0 to j-1);
i := i+j;
end loop;
end if;
return r;
end full_initial_value;
constant FULL_INIT_VAL : bit_vector(0 to C_DWIDTH*C_DEPTH -1)
:= full_initial_value(C_DWIDTH, C_DEPTH, C_INIT_VALUE);
--
constant K_FAMILY : families_type := str2fam(C_FAMILY);
--
constant W32 : boolean := supported(K_FAMILY, u_SRLC32E) and
(C_DEPTH > 16 or not supported(K_FAMILY, u_SRL16E));
constant W16 : boolean := supported(K_FAMILY, u_SRLC16E) and not W32;
-- XST faster if these two constants are declared here
-- instead of in STRUCTURAL_A_GEN. (I.25)
--
function power_of_2(n: positive) return boolean is
variable i: positive := 1;
begin
while n > i loop i := i*2; end loop;
return n = i;
end power_of_2;
--
constant USE_INFERRED : boolean := ( power_of_2(C_DEPTH)
and ( (W16 and C_DEPTH >= 16)
or (W32 and C_DEPTH >= 32)
)
)
or (not W32 and not W16);
-- As of I.32, XST is not infering optimal dynamic shift registers for
-- depths not a power of two (by not taking advantage of don't care
-- at output when address not within the range of the depth)
-- or a power of two less than the native SRL depth (by building shift
-- register out of discrete FFs and LUTs instead of SRLs).
constant USE_STRUCTURAL_A : boolean := not USE_INFERRED;
----------------------------------------------------------------------------
-- Unisim components declared locally for maximum avoidance of default
-- binding and vcomponents version issues.
----------------------------------------------------------------------------
component SRLC16E
generic
(
INIT : bit_vector := X"0000"
);
port
(
Q : out STD_ULOGIC;
Q15 : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end component;
component SRLC32E
generic
(
INIT : bit_vector := X"00000000"
);
port
(
Q : out STD_ULOGIC;
Q31 : out STD_ULOGIC;
A : in STD_LOGIC_VECTOR (4 downto 0);
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end component;
begin
---(
STRUCTURAL_A_GEN : if USE_STRUCTURAL_A = true generate
type bo2na_type is array(boolean) of natural;
constant bo2na : bo2na_type := (false => 0, true => 1);
constant BPSRL : natural := bo2na(W16)*16 + bo2na(W32)*32; -- Bits per SRL
constant BTASRL : natural := clog2(BPSRL); -- Bits To Address SRL
constant NUM_SRLS_DEEP : natural := (C_DEPTH + BPSRL-1)/BPSRL;
constant ADDR_BITS : integer := Addr'length;
signal dynshreg_addr : std_logic_vector(ADDR_BITS-1 downto 0);
signal cascade_sigs : std_logic_vector(0 to C_DWIDTH*(NUM_SRLS_DEEP+1) - 1);
-- The data signals at the inputs and daisy-chain outputs of SRLs.
-- The last signal of each cascade is not used.
--
signal q_sigs : std_logic_vector(0 to C_DWIDTH*NUM_SRLS_DEEP - 1);
-- The data signals at the addressble outputs of SRLs.
function srl_init_string(i, j : natural;
w : natural;
d : positive;
bpsrl : positive;
v : bit_vector
) return bit_vector is
variable base : natural := j*bpsrl*w + i;
variable r : bit_vector(bpsrl-1 downto 0) := (others => '0');
begin
for k in 0 to min(bpsrl, d-j*bpsrl)-1 loop
r(k) := v(base+k*w);
end loop;
return r;
end srl_init_string;
---)(
begin
DIN_TO_CASCADE_GEN : for i in 0 to C_DWIDTH-1 generate
cascade_sigs(i*(NUM_SRLS_DEEP+1)) <= Din(i);
end generate;
dynshreg_addr(ADDR_BITS-1 downto 0) <= Addr(0 to ADDR_BITS-1);
BIT_OF_WIDTH_GEN : for i in 0 to C_DWIDTH-1 generate
CASCADES_GEN : for j in 0 to NUM_SRLS_DEEP-1 generate
signal srl_addr: std_logic_vector(4 downto 0);
begin
-- Here we form the address for the SRL elements. This is just
-- the corresponding low-order bits of dynshreg_addr but we
-- also handle the case where we have to zero-pad to the left
-- a dynshreg_addr that is smaller than the SRL address port.
SRL_ADDR_LO_GEN : for i in 0 to min(ADDR_BITS-1,4) generate
srl_addr(i) <= dynshreg_addr(i);
end generate;
SRL_ADDR_HI_GEN : for i in min(ADDR_BITS-1,4)+1 to 4 generate
srl_addr(i) <= '0';
end generate;
W16_GEN : if W16 generate
SRLC16E_I : component SRLC16E
generic map (
INIT => srl_init_string(i, j,
C_DWIDTH,
C_DEPTH,
BPSRL,
FULL_INIT_VAL)
)
port map
(
Q => q_sigs(j + i*NUM_SRLS_DEEP),
Q15 => cascade_sigs(j+1 + i*(NUM_SRLS_DEEP+1)),
A0 => srl_addr(0),
A1 => srl_addr(1),
A2 => srl_addr(2),
A3 => srl_addr(3),
CE => Clken,
Clk => Clk,
D => cascade_sigs(j + i*(NUM_SRLS_DEEP+1))
)
;
end generate;
W32_GEN : if W32 generate
begin
SRLC32E_I : component SRLC32E
generic map (
INIT => srl_init_string(i, j,
C_DWIDTH,
C_DEPTH,
BPSRL,
FULL_INIT_VAL)
)
port map
(
Q => q_sigs(j + i*NUM_SRLS_DEEP),
Q31 => cascade_sigs(j+1 + i*(NUM_SRLS_DEEP+1)),
A => srl_addr(4 downto 0),
CE => Clken,
Clk => Clk,
D => cascade_sigs(j + i*(NUM_SRLS_DEEP+1))
)
;
end generate;
end generate CASCADES_GEN;
end generate BIT_OF_WIDTH_GEN;
----------------------------------------------------------------------------
-- Generate a MUXFn structure to select the proper SRL
-- as the output of each shift register.
----------------------------------------------------------------------------
SINGLE_SRL_GEN : if NUM_SRLS_DEEP = 1 generate
Dout <= q_sigs;
end generate;
--
MULTI_SRL_GEN : if NUM_SRLS_DEEP > 1 generate
PER_BIT_GEN : for i in 0 to C_DWIDTH-1 generate
begin
MUXF_STRUCT_I0 : entity proc_common_v4_0.muxf_struct_f
generic map (
C_START_LEVEL => native_lut_size(fam => K_FAMILY,
no_lut_return_val => 10000),
-- Artificially high value for C_START_LEVEL when no LUT is
-- supported will cause muxf_struct_f to default to inferred
-- multiplexers.
C_NUM_INPUTS => NUM_SRLS_DEEP,
C_FAMILY => C_FAMILY
)
port map (
O => Dout(i),
Iv => q_sigs(i * (NUM_SRLS_DEEP) to
(i+1) * (NUM_SRLS_DEEP) - 1),
Sel => dynshreg_addr(ADDR_BITS-1 downto BTASRL)
--Bits To Addr SRL
)
;
end generate;
end generate;
end generate STRUCTURAL_A_GEN;
---)
---(
INFERRED_GEN : if USE_INFERRED = true generate
--
type dataType is array (0 to C_DEPTH-1) of std_logic_vector(0 to C_DWIDTH-1);
--
function fill_data(w: natural; d: positive; v: bit_vector
) return dataType is
variable r : dataType;
begin
for i in 0 to d-1 loop
for j in 0 to w-1 loop
r(i)(j) := bv2sl(v(i*w+j));
end loop;
end loop;
return r;
end fill_data;
signal data: dataType := fill_data(C_DWIDTH, C_DEPTH, FULL_INIT_VAL);
--
begin
process(Clk)
begin
if Clk'event and Clk = '1' then
if Clken = '1' then
data <= Din & data(0 to C_DEPTH-2);
end if;
end if;
end process;
Dout <= data(TO_INTEGER(UNSIGNED(Addr)))
when (TO_INTEGER(UNSIGNED(Addr)) < C_DEPTH)
else
(others => '-');
end generate INFERRED_GEN;
---)
end behavioral;
---)
| apache-2.0 | 3883ad771d92244a5b28dd378463984c | 0.478028 | 4.492949 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-30bits_outputs31bits/2-MESA-HB/metaheurísticas/mesahb_femo.vhd | 1 | 2,051 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.10:16:46)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mesahb_femo_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5: IN unsigned(0 TO 30);
output1, output2: OUT unsigned(0 TO 31));
END mesahb_femo_entity;
ARCHITECTURE mesahb_femo_description OF mesahb_femo_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "0000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
output1 <= input1 + 1;
register1 := input2 * 2;
WHEN "00000010" =>
register2 := input3 * 3;
register1 := register1 + 5;
WHEN "00000011" =>
register1 := ((NOT register1) + 1) XOR register1;
register2 := register2 + 9;
WHEN "00000100" =>
register2 := register2 * 11;
WHEN "00000101" =>
register3 := input4 * 12;
register2 := register2 + 14;
WHEN "00000110" =>
register2 := ((NOT register2) + 1) XOR register2;
register1 := register3 * register1;
WHEN "00000111" =>
register2 := register2 * 18;
WHEN "00001000" =>
register1 := register2 + register1;
register2 := input5 * 19;
WHEN "00001001" =>
register2 := register2 + 21;
WHEN "00001010" =>
register2 := register2 * 23;
WHEN "00001011" =>
register2 := register2 + 25;
WHEN "00001100" =>
output2 <= register1(0 TO 14) & register2(0 TO 15);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mesahb_femo_description; | gpl-3.0 | a33e8803d78d7a5fc0d6e9f8ff12fcdb | 0.665529 | 3.160247 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/address_data_hit.vhd | 1 | 18,020 | `protect begin_protected
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`protect end_protected
| apache-2.0 | 6d60ace9139bac15c31776706e27e286 | 0.937736 | 1.862532 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/4-MPEG-MV/metaheurísticas/mpegmv_nsga2.vhd | 1 | 2,794 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-13.07:45:24)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mpegmv_nsga2_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14: IN unsigned(0 TO 3);
output1, output2, output3: OUT unsigned(0 TO 4));
END mpegmv_nsga2_entity;
ARCHITECTURE mpegmv_nsga2_description OF mpegmv_nsga2_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
WHEN "00000010" =>
register1 := register1 + 3;
register2 := input2 * 4;
register3 := input3 * 5;
WHEN "00000011" =>
register3 := register3 + 7;
register2 := register2 + 9;
register4 := input4 * 10;
register5 := input5 * 11;
WHEN "00000100" =>
register4 := register4 + 13;
register6 := input6 * 14;
register1 := register5 + register1;
register5 := input7 * 15;
register7 := input8 * 16;
WHEN "00000101" =>
register1 := register7 + register1;
register7 := input9 * 17;
WHEN "00000110" =>
output1 <= register7 + register3;
register3 := input10 * 19;
register4 := register6 + register4;
register2 := register5 + register2;
register1 := ((NOT register1) + 1) XOR register1;
register5 := input11 * 22;
WHEN "00000111" =>
register4 := register5 + register4;
register5 := input12 * 23;
WHEN "00001000" =>
output2 <= register1(0 TO 1) & register4(0 TO 2);
register1 := input13 * 25;
register2 := register5 + register2;
WHEN "00001001" =>
register2 := ((NOT register2) + 1) XOR register2;
register4 := input14 * 28;
register1 := register1 + 30;
WHEN "00001010" =>
register1 := register4 + register1;
WHEN "00001011" =>
register1 := register3 + register1;
WHEN "00001100" =>
output3 <= register2(0 TO 1) & register1(0 TO 2);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mpegmv_nsga2_description; | gpl-3.0 | b57dfb247d47175307da2d62a2e8c683 | 0.654975 | 3.056893 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/axi_uartlite_v2_0/6e58ba99/hdl/src/vhdl/axi_uartlite.vhd | 1 | 17,784 | -------------------------------------------------------------------------------
-- axi_uartlite - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] Xilinx, Inc. All rights reserved.*
-- -- ** *
-- -- ** This file contains confidential and proprietary information *
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
-- -- ** international copyright and other intellectual property *
-- -- ** laws. *
-- -- ** *
-- -- ** DISCLAIMER *
-- -- ** This disclaimer is not a license and does not grant any *
-- -- ** rights to the materials distributed herewith. Except as *
-- -- ** otherwise provided in a valid license issued to you by *
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- -- ** including negligence, or under any other theory of *
-- -- ** liability) for any loss or damage of any kind or nature *
-- -- ** related to, arising under or in connection with these *
-- -- ** materials, including for any direct, or any indirect, *
-- -- ** special, incidental, or consequential loss or damage *
-- -- ** (including loss of data, profits, goodwill, or any type of *
-- -- ** loss or damage suffered as a result of any action brought *
-- -- ** by a third party) even if such damage or loss was *
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
-- -- ** possibility of the same. *
-- -- ** *
-- -- ** CRITICAL APPLICATIONS *
-- -- ** Xilinx products are not designed or intended to be fail- *
-- -- ** safe, or for use in any application requiring fail-safe *
-- -- ** performance, such as life-support or safety devices or *
-- -- ** systems, Class III medical devices, nuclear facilities, *
-- -- ** applications related to the deployment of airbags, or any *
-- -- ** other applications that could lead to death, personal *
-- -- ** injury, or severe property or environmental damage *
-- -- ** (individually and collectively, "Critical *
-- -- ** Applications"). Customer assumes the sole risk and *
-- -- ** liability of any use of Xilinx products in Critical *
-- -- ** Applications, subject only to applicable laws and *
-- -- ** regulations governing limitations on product liability. *
-- -- ** *
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- -- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_uartlite.vhd
-- Version: v1.02.a
-- Description: AXI UART Lite Interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_uartlite.
--
-- axi_uartlite.vhd
-- --axi_lite_ipif.vhd
-- --uartlite_core.vhd
-- --uartlite_tx.vhd
-- --uartlite_rx.vhd
-- --baudrate.vhd
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 07/22/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
-- 20/09/20 SK
-- - 1. Updated the version as AXI Lite IPIF version is updated.
-- - 2. constant C_DPHASE_TIMEOUT value changed from 4 to 0
-- ^^^^^^
-- ~~~~~~
-- 01/02/10 NLR
-- - 1. Updated the version of axi_uartlite as uartlite_core.vhd changed
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library proc_common_v4_0;
-- SLV64_ARRAY_TYPE refered from ipif_pkg
use proc_common_v4_0.ipif_pkg.SLV64_ARRAY_TYPE;
-- INTEGER_ARRAY_TYPE refered from ipif_pkg
use proc_common_v4_0.ipif_pkg.INTEGER_ARRAY_TYPE;
-- calc_num_ce comoponent refered from ipif_pkg
use proc_common_v4_0.ipif_pkg.calc_num_ce;
library axi_lite_ipif_v2_0;
-- axi_lite_ipif refered from axi_lite_ipif_v2_0
use axi_lite_ipif_v2_0.axi_lite_ipif;
library axi_uartlite_v2_0;
-- uartlite_core refered from axi_uartlite_v2_0
use axi_uartlite_v2_0.uartlite_core;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- System generics
-- C_FAMILY -- Xilinx FPGA Family
-- C_S_AXI_ACLK_FREQ_HZ -- System clock frequency driving UART lite
-- peripheral in Hz
-- AXI generics
-- C_S_AXI_ADDR_WIDTH -- Width of AXI Address Bus (in bits)
-- C_S_AXI_DATA_WIDTH -- Width of the AXI Data Bus (in bits)
--
-- UART Lite generics
-- C_BAUDRATE -- Baud rate of UART Lite in bits per second
-- C_DATA_BITS -- The number of data bits in the serial frame
-- C_USE_PARITY -- Determines whether parity is used or not
-- C_ODD_PARITY -- If parity is used determines whether parity
-- is even or odd
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
--System signals
-- s_axi_aclk -- AXI Clock
-- s_axi_aresetn -- AXI Reset
-- Interrupt -- UART Interrupt
--AXI signals
-- s_axi_awaddr -- AXI Write address
-- s_axi_awvalid -- Write address valid
-- s_axi_awready -- Write address ready
-- s_axi_wdata -- Write data
-- s_axi_wstrb -- Write strobes
-- s_axi_wvalid -- Write valid
-- s_axi_wready -- Write ready
-- s_axi_bresp -- Write response
-- s_axi_bvalid -- Write response valid
-- s_axi_bready -- Response ready
-- s_axi_araddr -- Read address
-- s_axi_arvalid -- Read address valid
-- s_axi_arready -- Read address ready
-- s_axi_rdata -- Read data
-- s_axi_rresp -- Read response
-- s_axi_rvalid -- Read valid
-- s_axi_rready -- Read ready
--UARTLite Interface Signals
-- rx -- Receive Data
-- tx -- Transmit Data
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity axi_uartlite is
generic
(
-- -- System Parameter
C_FAMILY : string := "virtex7";
C_S_AXI_ACLK_FREQ_HZ : integer := 100_000_000;
-- -- AXI Parameters
C_S_AXI_ADDR_WIDTH : integer := 4;
C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32;
-- -- UARTLite Parameters
C_BAUDRATE : integer := 9600;
C_DATA_BITS : integer range 5 to 8 := 8;
C_USE_PARITY : integer range 0 to 1 := 0;
C_ODD_PARITY : integer range 0 to 1 := 0
);
port
(
-- System signals
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
interrupt : out std_logic;
-- AXI signals
s_axi_awaddr : in std_logic_vector
(3 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector
(31 downto 0);
s_axi_wstrb : in std_logic_vector
(3 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector
(3 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector
(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- UARTLite Interface Signals
rx : in std_logic;
tx : out std_logic
);
-------------------------------------------------------------------------------
-- Attributes
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Fan-Out attributes for XST
-------------------------------------------------------------------------------
ATTRIBUTE MAX_FANOUT : string;
ATTRIBUTE MAX_FANOUT of s_axi_aclk : signal is "10000";
ATTRIBUTE MAX_FANOUT of s_axi_aresetn : signal is "10000";
end entity axi_uartlite;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture RTL of axi_uartlite is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
--------------------------------------------------------------------------
-- Constant declarations
--------------------------------------------------------------------------
constant ZEROES : std_logic_vector(31 downto 0)
:= X"00000000";
constant C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
-- UARTLite registers Base Address
ZEROES & X"00000000",
ZEROES & (X"00000000" or X"0000000F")
);
constant C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 4
);
constant C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0)
:= X"0000000F";
constant C_USE_WSTRB : integer := 0;
constant C_DPHASE_TIMEOUT : integer := 0;
--------------------------------------------------------------------------
-- Signal declarations
--------------------------------------------------------------------------
signal bus2ip_clk : std_logic;
signal bus2ip_reset : std_logic;
signal bus2ip_resetn : std_logic;
signal ip2bus_data : std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0)
:= (others => '0');
signal ip2bus_error : std_logic := '0';
signal ip2bus_wrack : std_logic := '0';
signal ip2bus_rdack : std_logic := '0';
signal bus2ip_data : std_logic_vector
(C_S_AXI_DATA_WIDTH - 1 downto 0);
signal bus2ip_cs : std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1 downto 0);
signal bus2ip_rdce : std_logic_vector
(calc_num_ce(C_ARD_NUM_CE_ARRAY)-1 downto 0);
signal bus2ip_wrce : std_logic_vector
(calc_num_ce(C_ARD_NUM_CE_ARRAY)-1 downto 0);
begin -- architecture IMP
--------------------------------------------------------------------------
-- RESET signal assignment - IPIC RESET is active low
--------------------------------------------------------------------------
bus2ip_reset <= not bus2ip_resetn;
--------------------------------------------------------------------------
-- ip2bus_data assignment - as core is using maximum upto 8 bits
--------------------------------------------------------------------------
ip2bus_data((C_S_AXI_DATA_WIDTH-1) downto 8) <= (others => '0');
--------------------------------------------------------------------------
-- Instansiating the UART core
--------------------------------------------------------------------------
UARTLITE_CORE_I : entity axi_uartlite_v2_0.uartlite_core
generic map
(
C_FAMILY => C_FAMILY,
C_S_AXI_ACLK_FREQ_HZ => C_S_AXI_ACLK_FREQ_HZ,
C_BAUDRATE => C_BAUDRATE,
C_DATA_BITS => C_DATA_BITS,
C_USE_PARITY => C_USE_PARITY,
C_ODD_PARITY => C_ODD_PARITY
)
port map
(
Clk => bus2ip_clk,
Reset => bus2ip_reset,
bus2ip_data => bus2ip_data(7 downto 0),
bus2ip_rdce => bus2ip_rdce(3 downto 0),
bus2ip_wrce => bus2ip_wrce(3 downto 0),
bus2ip_cs => bus2ip_cs(0),
ip2bus_rdack => ip2bus_rdack,
ip2bus_wrack => ip2bus_wrack,
ip2bus_error => ip2bus_error,
SIn_DBus => ip2bus_data(7 downto 0),
RX => rx,
TX => tx,
Interrupt => Interrupt
);
--------------------------------------------------------------------------
-- Instantiate AXI lite IPIF
--------------------------------------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v2_0.axi_lite_ipif
generic map
(
C_FAMILY => C_FAMILY,
C_S_AXI_ADDR_WIDTH => 4,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY
)
port map
(
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready,
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk,
Bus2IP_Resetn => bus2ip_resetn,
IP2Bus_Data => ip2bus_data,
IP2Bus_WrAck => ip2bus_wrack,
IP2Bus_RdAck => ip2bus_rdack,
IP2Bus_Error => ip2bus_error,
Bus2IP_Addr => open,
Bus2IP_Data => bus2ip_data,
Bus2IP_RNW => open,
Bus2IP_BE => open,
Bus2IP_CS => bus2ip_cs,
Bus2IP_RdCE => bus2ip_rdce,
Bus2IP_WrCE => bus2ip_wrce
);
end architecture RTL;
| apache-2.0 | 221c7ce92eaf159af33c9c15618a3c2c | 0.421221 | 4.528648 | false | false | false | false |
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`protect end_protected
| apache-2.0 | 6380252a0ce31480cd27fd7ff1ac103c | 0.947813 | 1.826525 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/ramfifo/rd_status_flags_sshft.vhd | 5 | 19,232 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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1A1gkI6+LkiPcaxvFkY=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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l64FGbnzPpyT8FCzCgs=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12496)
`protect data_block
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`protect end_protected
| apache-2.0 | 9573c01cb4127e2f706d5416a4b19f85 | 0.93932 | 1.850654 | false | false | false | false |
CyAScott/CIS4930.DatapathSynthesisTool | src/components/c_divider.vhd | 2 | 888 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
entity c_divider is
generic
(
width : integer := 4;
const : integer := 16
);
port
(
input : std_logic_vector((width - 1) downto 0);
output : out std_logic_vector((width - 1) downto 0)
);
end c_divider;
architecture behavior of c_divider is
begin
P0 : process (input)
variable l_val, r_val, value : integer;
variable flag : integer := 0;
variable result : std_logic_vector(width - 1 downto 0);
begin
if ((const > 2 ** (width - 2)) or (const = 0)) then
for i in 0 to (width - 1) loop
result(i) := '0';
end loop;
end if;
if ((const > 0) and (const <= 2 ** (width - 2))) then
l_val := CONV_INTEGER(input);
value := l_val / const;
result := CONV_STD_LOGIC_VECTOR(value, width);
end if;
output <= result;
end process P0;
end behavior; | mit | 94263af24998a574675818aa9114e14b | 0.628378 | 2.801262 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/eval_timer.vhd | 15 | 11,230 | -------------------------------------------------------------------------------
-- $Id: eval_timer.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- eval_timer.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: eval_timer.vhd
-- Version: v1.00a
-- Description: 40-bit counter that enables IP to be used in an evaluation
-- mode. Once the counter expires, the eval_timeout signal
-- asserts and can be used to reset the IP.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- eval_timer.vhd
--
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 09/12/01 -- Created from PCI eval timer
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.all;
use proc_common_v4_0.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- No generics
--
-- Definition of Ports:
-- Clk -- clock
-- Rst -- active high reset
-- Eval_timeout -- timer has expired
-------------------------------------------------------------------------------
entity eval_timer is
port (
Clk : in std_logic;
Rst : in std_logic;
Eval_timeout : out std_logic
);
end entity eval_timer;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of eval_timer is
-----------------------------------------------------------------------------
-- Constant Declarations
-----------------------------------------------------------------------------
constant NUM_BITS : integer := 8;
-----------------------------------------------------------------------------
-- Signal Declarations
-----------------------------------------------------------------------------
signal co : std_logic_vector(0 to 4); -- carry out
signal ceo : std_logic_vector(0 to 4); -- count enable out
signal ceo_d1 : std_logic_vector(0 to 4); -- registered count enable out
signal zeros : std_logic_vector(NUM_BITS-1 downto 0);
-----------------------------------------------------------------------------
-- Component Declarations
-----------------------------------------------------------------------------
component Counter is
generic(
C_NUM_BITS : Integer := 9
);
port (
Clk : in std_logic;
Rst : in std_logic;
Load_In : in std_logic_vector(C_NUM_BITS - 1 downto 0);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Count_Out : out std_logic_vector(C_NUM_BITS - 1 downto 0);
Carry_Out : out std_logic
);
end component Counter;
component FDRE
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
component FDR
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
begin -- VHDL_RTL
-- set the load value to zero
zeros <= (others => '0');
-- Generate a 40-bit counter from 5 8-bit counters. Register the carry-out between counters
-- to avoid timing problems.
COUNTER_GEN: for i in 0 to 4 generate
-- first 8-bit counter
FIRST: if i = 0 generate
COUNT_0_I: Counter
generic map (C_NUM_BITS => NUM_BITS)
port map ( Clk => Clk,
Rst => Rst,
Load_in => zeros,
Count_Enable => '1',
Count_Load => '0',
Count_Down => '0',
Count_out => open,
Carry_Out => co(0)
);
-- register the carry out to create the count enable out
ceo(i) <= co(i);
FDR_0_I: FDR
port map (
Q => ceo_d1(i),
C => Clk,
D => ceo(i),
R => Rst
);
end generate FIRST;
-- all other eight bit counters and the carry out register
ALL_OTHERS: if i /= 0 generate
COUNT_I: Counter
generic map (C_NUM_BITS => NUM_BITS)
port map ( Clk => Clk,
Rst => Rst,
Load_in => zeros,
Count_Enable => ceo_d1(i-1),
Count_Load => '0',
Count_Down => '0',
Count_out => open,
Carry_Out => co(i)
);
-- register the carry out AND the count enable to create the count enable out
ceo(i) <= co(i) and ceo_d1(i-1);
FDR_0_I: FDR
port map (
Q => ceo_d1(i),
C => Clk,
D => ceo(i),
R => Rst
);
end generate ALL_OTHERS;
end generate COUNTER_GEN;
-- Using the final carry out as a CE, clock a '1' to assert and hold the eval_timeout signal.
FDRE_I: FDRE
port map (
Q => eval_timeout, --[out]
C => Clk, --[in]
CE => ceo_d1(4), --[in]
D => '1', --[in]
R => Rst --[in]
);
end imp;
| apache-2.0 | b412c147485d0a32349dd2b489836c7b | 0.396705 | 5.223256 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/7-FIR1/metaheurísticas/fir1_nsga2.vhd | 1 | 3,854 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-26.15:29:16)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY fir1_nsga2_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16, input17, input18, input19, input20, input21, input22: IN unsigned(0 TO 3);
output1: OUT unsigned(0 TO 4));
END fir1_nsga2_entity;
ARCHITECTURE fir1_nsga2_description OF fir1_nsga2_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register9: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register10: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register11: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register12: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 and input1;
register2 := input2 and input2;
WHEN "00000010" =>
register3 := input3 and input3;
register4 := input4 and input4;
register1 := register2 * register1;
WHEN "00000011" =>
register2 := input5 and input5;
register3 := register4 * register3;
register4 := input6 and input6;
WHEN "00000100" =>
register5 := input7 and input7;
register6 := input8 and input8;
WHEN "00000101" =>
register5 := register5 * register6;
register6 := input9 and input9;
register7 := input10 and input10;
WHEN "00000110" =>
register8 := input11 and input11;
register6 := register6 * register7;
WHEN "00000111" =>
register2 := register8 * register2;
register7 := input12 and input12;
register8 := input13 and input13;
WHEN "00001000" =>
register9 := input14 and input14;
register10 := input15 and input15;
WHEN "00001001" =>
register11 := input16 and input16;
register2 := register3 + register2;
register3 := register10 * register7;
register7 := input17 and input17;
WHEN "00001010" =>
register10 := input18 and input18;
register12 := input19 and input19;
register7 := register11 * register7;
WHEN "00001011" =>
register11 := input20 and input20;
register9 := register9 * register12;
WHEN "00001100" =>
register4 := register11 * register4;
register11 := input21 and input21;
register7 := register7 + register9;
WHEN "00001101" =>
register1 := register1 + register4;
register3 := register7 + register3;
register4 := register10 * register11;
register7 := input22 and input22;
WHEN "00001110" =>
register7 := register7 * register8;
register3 := register4 + register3;
WHEN "00001111" =>
register1 := register1 + register3;
WHEN "00010000" =>
register1 := register1 + register5;
WHEN "00010001" =>
register1 := register2 + register1;
WHEN "00010010" =>
register1 := register1 + register7;
WHEN "00010011" =>
register1 := register6 + register1;
WHEN "00010100" =>
output1 <= register1 and register1;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END fir1_nsga2_description; | gpl-3.0 | 75cb2aced4c98d0a5e1b608762c372e2 | 0.677218 | 3.241379 | false | false | false | false |
sils1297/HWPrak14 | task_4/project_1.srcs/sources_1/new/ALU.vhd | 1 | 1,729 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ALU is
generic(
WIDTH : integer := 16
);
Port(
clock : in std_ulogic;
register_D : in std_ulogic_vector(WIDTH - 1 downto 0);
A_or_M : in std_ulogic_vector(WIDTH - 1 downto 0);
c : in std_ulogic_vector(WIDTH - 1 downto 0);
comp : out std_ulogic_vector(WIDTH - 1 downto 0)
);
end ALU;
architecture Behavioral of ALU is
signal c1_6 : std_ulogic_vector(5 downto 0);
signal comp : std_ulogic_vector(WIDTH - 1 downto 0);
begin
c1_6 <= c(11 downto 6);
ALU_operation : process(clock)
begin
case c1_6 is
when "101010" => comp <= (others => '0');
when "111111" => comp <= std_ulogic_vector(1);
when "111010" => comp <= (others => '1');
when "001100" => comp <= register_D;
when "110000" => comp <= A_or_M;
when "001101" => comp <= not register_D;
when "110001" => comp <= not A_or_M;
when "001111" => comp <= std_ulogic_vector(-signed(register_D));
when "110011" => comp <= std_ulogic_vector(-signed(A_or_M));
when "011111" => comp <= std_ulogic_vector(signed(register_D) + 1);
when "110111" => comp <= std_ulogic_vector(signed(A_or_M) + 1);
when "001110" => comp <= std_ulogic_vector(signed(register_D) - 1);
when "110010" => comp <= std_ulogic_vector(signed(A_or_M) - 1);
when "000010" => comp <= std_ulogic_vector(signed(register_D) + signed(A_or_M));
when "010011" => comp <= std_ulogic_vector(signed(register_D) - signed(A_or_M));
when "000111" => comp <= std_ulogic_vector(signed(A_or_M) - signed(register_D));
when "000000" => comp <= register_D and A_or_M;
when "010101" => comp <= register_D or A_or_M;
end case;
end process;
end Behavioral;
| agpl-3.0 | 5038d7e7d31468282e234bf4fea3d062 | 0.618276 | 2.806818 | false | false | false | false |
mbgh/aes128-hdl | src/vhdl/subWord.vhd | 1 | 3,031 | -------------------------------------------------------------------------------
--! @file subWord.vhd
--! @brief AES substitude word function (SubWord)
--! @project VLSI Book - AES-128 Example
--! @author Michael Muehlberghuber ([email protected])
--! @company Integrated Systems Laboratory, ETH Zurich
--! @copyright Copyright (C) 2014 Integrated Systems Laboratory, ETH Zurich
--! @date 2014-06-05
--! @updated 2014-06-05
--! @platform Simulation: ModelSim; Synthesis: Synopsys
--! @standard VHDL'93/02
-------------------------------------------------------------------------------
-- Revision Control System Information:
-- File ID : $Id: subWord.vhd 6 2014-06-12 12:49:55Z u59323933 $
-- Revision : $Revision: 6 $
-- Local Date : $Date: 2014-06-12 14:49:55 +0200 (Thu, 12 Jun 2014) $
-- Modified By : $Author: u59323933 $
-------------------------------------------------------------------------------
-- Major Revisions:
-- Date Version Author Description
-- 2014-06-05 1.0 michmueh Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library work;
use work.aes128Pkg.all;
-------------------------------------------------------------------------------
--! @brief AES substitude word function (SubWord)
--!
--! Takes a word (i.e., four bytes) and substitudes the word using the
--! substitution box (S-box) of the Advanced Encryption Standard (AES). This is
--! done by instantiating four S-boxes, each operating on a single byte.
-------------------------------------------------------------------------------
entity subWord is
port (
--! @brief Input to the "SubWord" function.
In_DI : in Word;
--! @brief Substituted output of the "SubWord" function.
Out_DO : out Word);
end entity subWord;
-------------------------------------------------------------------------------
--! @brief Structural architecture of the "SubWord" function.
-------------------------------------------------------------------------------
architecture Structural of subWord is
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
component sbox is
port (
In_DI : in Byte;
Out_DO : out Byte);
end component sbox;
begin -- architecture structural
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
sbox_0 : sbox
port map (
In_DI => In_DI(0),
Out_DO => Out_DO(0));
sbox_1 : sbox
port map (
In_DI => In_DI(1),
Out_DO => Out_DO(1));
sbox_2 : sbox
port map (
In_DI => In_DI(2),
Out_DO => Out_DO(2));
sbox_3 : sbox
port map (
In_DI => In_DI(3),
Out_DO => Out_DO(3));
end architecture Structural;
| gpl-2.0 | 0ad76feedd6895ddeb52872c58ab8bed | 0.430881 | 4.670262 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/common/shft_ram.vhd | 5 | 17,157 | `protect begin_protected
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rhexsel/xinu-cMIPS | vhdl/uart.vhd | 2 | 39,301 | -- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
package p_UART is
constant BAUD_RT_0 : integer := 4/2;
constant BAUD_RT_1 : integer := 8/2;
constant BAUD_RT_2 : integer := 16/2;
constant BAUD_RT_3 : integer := 32/2;
constant BAUD_RT_4 : integer := 64/2;
constant BAUD_RT_5 : integer := 128/2;
constant BAUD_RT_6 : integer := 2604/2; -- 19.200, 434/2 = 115.200
constant BAUD_RT_7 : integer := 5208/2; -- 9.600
-- top limit for baud-rate divider: 50.000.000 Hz / 4 = 12.500.000 baud
-- which, adjusted to the next upward power of two is 16M
constant BAUD_CNTR_LIMIT : integer := ((16*1024*1024)-1); --
end p_UART;
-- package body p_UART is
-- end p_UART;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- UART internals; the external/processor interface is defined in io.vhdl
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- control register, least significant byte only
-- b2..b0: transmit/receive clock speed
-- 000: 1/4 CPU clock rate -- for VHDL/C debugging only
-- 001: 1/8 CPU clock rate -- for VHDL/C debugging only
-- 010: 1/16 CPU clock rate -- for VHDL/C debugging only
-- 011: 1/32 CPU clock rate -- for VHDL/C debugging only
-- 100: 1/64 CPU clock rate -- for VHDL/C debugging only
-- 101: 1/128 CPU clock rate -- for VHDL/C debugging only
-- 110: 19.200 bits per second
-- 111: 9.600 bits per second
-- b3-b6: ignored, not used
-- b7=1: turn on Request to Send (RTS)
--
-- Baud rates dividers (BAUD_RT_n) are defined in packageWires.vhd
--
-- status register, least significant byte only
-- b0: overurn error, last octet received overwrote previous in buffer
-- b1: framing error, last octet was not framed by START, STOP bits
-- b2: not used, returns zero
-- b3: interrupt pending on RX buffer full
-- b4: interrupt pending on TX buffer empty
-- b5: receive buffer is full
-- b6: transmit buffer is empty
-- b7: Clear to Send (CTS) is active (=1)
--
-- when CPU reads from RXdat register, bits 0 and 1 of status are cleared
--
-- interrupt register, least significant byte only
-- b0=1: program interrupt on RX buffer full, when a new octet is available
-- b1=1: program interrupt on TX buffer empty, when TX space is available
-- b2: ignored, not used
-- b3=1: clear interrupt bit on RX buffer full (IRQ -> 0)
-- b4=1: clear interrupt bit on TX buffer empty (IRQ -> 0)
-- b5=1: set interrupt bit on RX buffer full (IRQ -> 1)
-- b6=1: set interrupt bit on TX buffer empty (IRQ -> 1)
-- b7: ignored, not used
--
-- reading the interrupr register returns bits b0,b1, remaining return 0
--
-- RX and TX circuits are dobule-buffered
--
library ieee; use ieee.std_logic_1164.all;
use work.p_WIRES.all;
use work.p_UART.all;
entity uart_int is
port(clk, rst: in std_logic;
s_ctrlwr, s_stat : in std_logic; -- select registers
s_tx, s_rx : in std_logic; -- select registers
s_intwr, s_intrd : in std_logic; -- select interrupt register
d_inp : in reg32; -- input
d_out : out reg32; -- output
txdat : out std_logic; -- interface: serial transmission
rxdat : in std_logic; -- interface: serial reception
rts : out std_logic; -- interface: request to send
cts : in std_logic; -- interface: clear to send
irq_all : out std_logic; -- interrupt request
bit_rt : out reg3); -- communication speed, for debugging
end uart_int;
architecture rtl of uart_int is
constant CLOCK_DIVIDER : integer := 50;
-- bit in ctrl register to set/clear the RTS serial interface signal
constant RTS_B : integer := 7;
-- bit in interrupt register to set RX interrupt request
constant SET_IRQ_TX : integer := 6;
-- bit in interrupt register to set TX interrupt request
constant SET_IRQ_RX : integer := 5;
-- bit in interrupt register to clear TX interrupt request
constant CLR_IRQ_TX : integer := 4;
-- bit in interrupt register to clear RX interrupt request
constant CLR_IRQ_RX : integer := 3;
-- bit in interr register to program a TX interrupt request
constant IRQ_TX_B : integer := 1;
-- bit in interr register to program a RX interrupt request
constant IRQ_RX_B : integer := 0;
component register8 is
port(clk, rst, ld: in std_logic;
D: in std_logic_vector;
Q: out std_logic_vector);
end component register8;
component register2 is
port(clk, rst, ld: in std_logic;
D: in std_logic_vector;
Q: out std_logic_vector);
end component register2;
component par_ser10 is
port(clk, rst, ld, desl: in std_logic;
D: in std_logic_vector;
Q: out std_logic);
end component par_ser10;
component ser_par10 is
port(clk, rst, desl: in std_logic;
D: in std_logic;
Q: out std_logic_vector);
end component ser_par10;
component FFDsimple is
port(clk, rst, D : in std_logic; Q : out std_logic);
end component FFDsimple;
-- state machine for transmission-CPU interface
type txcpu_state is (st_idle, st_check, st_done);
signal txcpu_current_st, txcpu_next_st : txcpu_state;
attribute SYN_ENCODING of txcpu_state : type is "safe";
-- state machine for transmission circuit
type tx_state is (st_idle, st_check, st_start,
st_b0, st_b1, st_b2, st_b3, st_b4, st_b5, st_b6, st_b7,
st_stop, st_end, st_done);
signal tx_current_st, tx_next_st : tx_state;
attribute SYN_ENCODING of tx_state : type is "safe";
-- state machine for reception-CPU interface
type rxcpu_state is (st_idle, st_copy, st_check, st_error);
signal rxcpu_current_st, rxcpu_next_st : rxcpu_state;
attribute SYN_ENCODING of rxcpu_state : type is "safe";
-- state machine for reception circuit
type rx_state is (st_idle, st_check, st_start,
st_b0, st_b1, st_b2, st_b3, st_b4, st_b5, st_b6, st_b7,
st_stop, st_done);
signal rx_current_st, rx_next_st : rx_state;
attribute SYN_ENCODING of rx_state : type is "safe";
-- for debugging only
signal tx_dbg_st, txcpu_dbg_st, rx_dbg_st, rxcpu_dbg_st : integer;
signal ctrl, status, txreg, rxreg, received : reg8;
signal interr : reg2;
signal tx_bit_rt, rx_bit_rt : std_logic;
signal en_tx_clk, txclk, txclk_rise : std_logic;
signal tx_ld, tx_shift, tx_next, tx_bfr_empt, tx_shr_full : std_logic;
signal rx_ld, rx_shift, rx_next, rx_bfr_full : std_logic;
signal rxdat_1to0, rxdat_new, rxdat_int, rxdat_old : std_logic;
signal rxclk_fall, rxclk_rise, en_rx_clk, rx_done, rxclk : std_logic;
signal a_overrun, a_framing, reset_rxck : std_logic;
signal sta_xmit_sto, sta_recv_sto : reg10;
signal err_overrun, err_framing : std_logic;
signal rx_int_set, interr_RX_full, tx_int_set, interr_TX_empty : std_logic;
signal d_int_tx_empty,d_rx_int_set,d_err_framing,d_err_overrun : std_logic;
signal clear_tx_irq, clear_rx_irq : std_logic;
signal tx_baud_div, rx_baud_div : integer := 0;
begin
-- interrupt register must read 0's as compiler generates RD-mod-WR
-- sequences to set or clear individual bits
d_out <= x"000000" & received when s_rx = '1' else
x"000000" & status when s_stat = '1' else
x"0000000" & b"00" & interr when s_intrd = '1' else -- RD-mod-WR
x"000000" & ctrl; -- show ctrl all other times
rts <= ctrl(RTS_B);
-- for testing only: tells remote unit what is the transmission speed
bit_rt <= ctrl(2 downto 0);
U_ctrl: register8 port map (clk,rst, s_ctrlwr, d_inp(7 downto 0), ctrl);
U_interr: register2 port map (clk,rst, s_intwr, d_inp(1 downto 0), interr);
status <= cts & tx_bfr_empt & rx_bfr_full &
interr_TX_empty & interr_RX_full &
'0' & err_framing & err_overrun;
irq_all <= interr_TX_empty or interr_RX_full;
-- TRANSMISSION ===========================================================
-- txreg is updated under the assumption that SW checked TXempty beforehand
U_txreg: register8 port map (clk,rst, s_tx, d_inp(7 downto 0), txreg);
sta_xmit_sto <= '1' & txreg & '0'; -- start (b0), octet, stop (b9)
tx_next <= txclk_rise and tx_shift;
U_transmit: par_ser10 port map (clk, rst, tx_ld, tx_next,
sta_xmit_sto, txdat);
clear_tx_irq <= '0' when s_intwr = '1' and d_inp(CLR_IRQ_TX) = '1' else '1';
tx_int_set <= ( (interr(IRQ_TX_B) and tx_ld) or
(s_intwr and d_inp(SET_IRQ_TX)) );
d_int_tx_empty <= (interr_TX_empty or tx_int_set) and clear_tx_irq;
U_tx_int: FFDsimple port map (clk, rst, d_int_tx_empty, interr_TX_empty);
-- this state machine contols the CPU-transmission interface -------------
U_TXCPU_st_reg: process(rst,clk)
begin
if rst = '0' then
txcpu_current_st <= st_idle;
elsif rising_edge(clk) then
txcpu_current_st <= txcpu_next_st;
end if;
end process U_TXCPU_st_reg; ----------------------------------------------
txcpu_dbg_st <= integer(txcpu_state'pos(txcpu_current_st)); -- for debugging
U_TXCPU_st_transitions: process(txcpu_current_st, s_tx, tx_shr_full) -----
begin
case txcpu_current_st is
when st_idle => -- 0
if s_tx = '1' then
txcpu_next_st <= st_check;
else
txcpu_next_st <= st_idle;
end if;
when st_check => -- 1
if tx_shr_full = '1' then
txcpu_next_st <= st_check;
else
txcpu_next_st <= st_done;
end if;
when st_done => -- 2
txcpu_next_st <= st_idle;
when others =>
assert false report "TX-CPU stateMachine broken"
& integer'image(txcpu_state'pos(txcpu_current_st)) severity failure;
end case;
end process U_TXCPU_st_transitions; ------------------------------------
U_TXCPU_outputs: process(txcpu_current_st) ------------------------------
begin
case txcpu_current_st is
when st_idle => -- 0
tx_ld <= '0';
tx_bfr_empt <= '1';
when st_check => -- 1
tx_ld <= '0';
tx_bfr_empt <= '0';
when st_done => -- 2
tx_ld <= '1';
tx_bfr_empt <= '0';
end case;
end process U_TXCPU_outputs; -------------------------------------------
-- state machine controls data transmission circuit ----------------------
U_TX_st_reg: process(rst,clk)
begin
if rst = '0' then
tx_current_st <= st_idle;
elsif rising_edge(clk) then
tx_current_st <= tx_next_st;
end if;
end process U_TX_st_reg;
tx_dbg_st <= integer(tx_state'pos(tx_current_st)); -- debugging
U_TX_st_transitions: process(tx_current_st,tx_ld,txclk_rise)
begin
case tx_current_st is
when st_idle =>
if tx_ld = '1' then
tx_next_st <= st_check;
else
tx_next_st <= st_idle;
end if;
when st_check =>
tx_next_st <= st_start;
when st_start =>
if txclk_rise = '1' then
tx_next_st <= st_b0; -- synchronize CPUclock with TXclock
else
tx_next_st <= st_start;
end if;
when st_b0 =>
if txclk_rise = '1' then
tx_next_st <= st_b1;
else
tx_next_st <= st_b0;
end if;
when st_b1 =>
if txclk_rise = '1' then
tx_next_st <= st_b2;
else
tx_next_st <= st_b1;
end if;
when st_b2 =>
if txclk_rise = '1' then
tx_next_st <= st_b3;
else
tx_next_st <= st_b2;
end if;
when st_b3 =>
if txclk_rise = '1' then
tx_next_st <= st_b4;
else
tx_next_st <= st_b3;
end if;
when st_b4 =>
if txclk_rise = '1' then
tx_next_st <= st_b5;
else
tx_next_st <= st_b4;
end if;
when st_b5 =>
if txclk_rise = '1' then
tx_next_st <= st_b6;
else
tx_next_st <= st_b5;
end if;
when st_b6 =>
if txclk_rise = '1' then
tx_next_st <= st_b7;
else
tx_next_st <= st_b6;
end if;
when st_b7 =>
if txclk_rise = '1' then
tx_next_st <= st_stop;
else
tx_next_st <= st_b7;
end if;
when st_stop =>
if txclk_rise = '1' then
tx_next_st <= st_end;
else
tx_next_st <= st_stop;
end if;
when st_end =>
if txclk_rise = '1' then -- wait for stop-bit to end
tx_next_st <= st_done;
else
tx_next_st <= st_end;
end if;
when st_done =>
tx_next_st <= st_idle;
when others =>
assert false report "TX stateMachine broken"
& integer'image(tx_state'pos(tx_current_st)) severity failure;
end case;
end process U_TX_st_transitions; -- -----------------------------------
U_TX_outputs: process(tx_current_st) -- --------------------------------
begin
case tx_current_st is
when st_idle =>
tx_shr_full <= '0';
tx_shift <= '0';
en_tx_clk <= '0';
when st_check =>
tx_shift <= '0';
tx_shr_full <= '1';
en_tx_clk <= '1';
when st_start | st_b0 | st_b1 | st_b2 | st_b3 | st_b4 | st_b5 | st_b6 | st_b7 | st_stop | st_end =>
tx_shift <= '1';
tx_shr_full <= '1';
en_tx_clk <= '1';
when st_done =>
tx_shr_full <= '1';
tx_shift <= '0';
en_tx_clk <= '0';
end case;
end process U_TX_outputs; ----------------------------------------------
-- RECEPTION =============================================================
U_rxreg: register8 port map (clk,rst, rx_ld, rxreg, received);
rx_next <= rx_shift and rxclk_rise;
U_receive: ser_par10 port map (clk, rst, rx_next, rxdat, sta_recv_sto);
rxreg <= sta_recv_sto(8 downto 1);
U_edgeDetect0: FFDsimple port map (clk, rst, rxdat, rxdat_new);
U_edgeDetect1: FFDsimple port map (clk, rst, rxdat_new, rxdat_int);
U_edgeDetect2: FFDsimple port map (clk, rst, rxdat_int, rxdat_old);
rxdat_1to0 <= rxdat_old and not(rxdat_new);
-- framing error: 10th bit not a STOP=1 or 1st bit not a START=0
a_framing <= '1' when ( (rx_ld = '1') and
(sta_recv_sto(9) /= '1' or sta_recv_sto(0)/='0') )
else '0';
d_err_framing <= (a_framing or err_framing) and not(s_rx);
U_framing: FFDsimple port map (clk, rst, d_err_framing, err_framing);
d_err_overrun <= (a_overrun or err_overrun) and not(s_rx);
U_overrun: FFDsimple port map (clk, rst, d_err_overrun, err_overrun);
clear_rx_irq <= '0' when s_intwr = '1' and d_inp(CLR_IRQ_RX) = '1' else '1';
rx_int_set <= ( (interr(IRQ_RX_B) and rx_done) or
(s_intwr and d_inp(SET_IRQ_RX)) );
d_rx_int_set <= (rx_int_set or interr_RX_full) and clear_rx_irq;
U_rx_int: FFDsimple port map (clk, rst, d_rx_int_set, interr_RX_full);
-- SM controls reception-CPU interface -------------------------------
U_RXCPU_st_reg: process(rst,clk)
begin
if rst = '0' then
rxcpu_current_st <= st_idle;
elsif rising_edge(clk) then
rxcpu_current_st <= rxcpu_next_st;
end if;
end process U_RXCPU_st_reg;
rxcpu_dbg_st <= integer(rxcpu_state'pos(rxcpu_current_st)); -- debugging
U_RXCPU_st_transitions: process(rxcpu_current_st, rx_done, s_rx)
begin
case rxcpu_current_st is
when st_idle => -- 0
if rx_done = '1' then -- rx buffer full
rxcpu_next_st <= st_copy;
else
rxcpu_next_st <= st_idle;
end if;
when st_copy => -- 1
rxcpu_next_st <= st_check;
when st_check => -- 2
if rx_done = '1' then
rxcpu_next_st <= st_error;
elsif s_rx = '1' then
rxcpu_next_st <= st_idle;
else
rxcpu_next_st <= st_check;
end if;
when st_error => -- 3
rxcpu_next_st <= st_check;
when others =>
assert false report "RX-CPU stateMachine broken"
& integer'image(rxcpu_state'pos(rxcpu_current_st)) severity failure;
end case;
end process U_RXCPU_st_transitions; --------------------------------------
U_RXCPU_outputs: process(rxcpu_current_st)
begin
case rxcpu_current_st is
when st_idle => -- 0
rx_ld <= '0';
rx_bfr_full <= '0';
a_overrun <= '0';
when st_copy => -- 1
rx_ld <= '1';
rx_bfr_full <= '1';
a_overrun <= '0';
when st_check => -- 2
rx_ld <= '0';
rx_bfr_full <= '1';
a_overrun <= '0';
when st_error => -- 3
rx_ld <= '0';
rx_bfr_full <= '1';
a_overrun <= '1'; -- assert overrun error, char overwritten
end case;
end process U_RXCPU_outputs; ---------------------------------------------
-- SM controls data reception circuit ------------------------------------
U_RX_st_reg: process(rst,clk)
begin
if rst = '0' then
rx_current_st <= st_idle;
elsif rising_edge(clk) then
rx_current_st <= rx_next_st;
end if;
end process U_RX_st_reg;
rx_dbg_st <= integer(rx_state'pos(rx_current_st)); -- debugging only
U_RX_st_transitions: process(rx_current_st, rxclk_fall, rxdat_1to0, rxdat)
begin
case rx_current_st is
when st_idle =>
if rxdat_1to0 = '1' then -- start bit = falling edge on rxdat
rx_next_st <= st_check;
else
rx_next_st <= st_idle;
end if;
when st_check =>
if rxdat = '0' then
rx_next_st <= st_start;
else
rx_next_st <= st_idle;
end if;
when st_start =>
if rxclk_fall = '1' then
rx_next_st <= st_b0;
else
rx_next_st <= st_start;
end if;
when st_b0 =>
if rxclk_fall = '1' then
rx_next_st <= st_b1;
else
rx_next_st <= st_b0;
end if;
when st_b1 =>
if rxclk_fall = '1' then
rx_next_st <= st_b2;
else
rx_next_st <= st_b1;
end if;
when st_b2 =>
if rxclk_fall = '1' then
rx_next_st <= st_b3;
else
rx_next_st <= st_b2;
end if;
when st_b3 =>
if rxclk_fall = '1' then
rx_next_st <= st_b4;
else
rx_next_st <= st_b3;
end if;
when st_b4 =>
if rxclk_fall = '1' then
rx_next_st <= st_b5;
else
rx_next_st <= st_b4;
end if;
when st_b5 =>
if rxclk_fall = '1' then
rx_next_st <= st_b6;
else
rx_next_st <= st_b5;
end if;
when st_b6 =>
if rxclk_fall = '1' then
rx_next_st <= st_b7;
else
rx_next_st <= st_b6;
end if;
when st_b7 =>
if rxclk_fall = '1' then
rx_next_st <= st_stop;
else
rx_next_st <= st_b7;
end if;
when st_stop =>
if rxclk_fall = '1' then
rx_next_st <= st_done;
else
rx_next_st <= st_stop;
end if;
when st_done =>
rx_next_st <= st_idle;
when others =>
assert false report "RX stateMachine broken"
& integer'image(rx_state'pos(rx_current_st)) severity failure;
end case;
end process U_RX_st_transitions; ------------------------------------
U_RX_outputs: process(rx_current_st)
begin
case rx_current_st is
when st_idle =>
rx_done <= '0';
rx_shift <= '0';
reset_rxck <= '0';
en_rx_clk <= '0';
when st_check =>
rx_done <= '0';
rx_shift <= '0';
reset_rxck <= '1';
en_rx_clk <= '1';
when st_start | st_b0 | st_b1 | st_b2 | st_b3 | st_b4 | st_b5 | st_b6 | st_b7 | st_stop =>
rx_done <= '0';
rx_shift <= '1';
reset_rxck <= '0';
en_rx_clk <= '1';
when st_done =>
rx_done <= '1';
rx_shift <= '0';
reset_rxck <= '0';
en_rx_clk <= '0';
end case;
end process U_RX_outputs; -------------------------------------------
-- baud rate generators ---------------------------------------------
-- U_bit_rt_tx: counter8 port map (clk,rst,tx_ld,en_tx_clk,x"00",tx_bit_rt);
with ctrl(2 downto 0) select
tx_baud_div <= BAUD_RT_0 when b"000",
BAUD_RT_1 when b"001",
BAUD_RT_2 when b"010",
BAUD_RT_3 when b"011",
BAUD_RT_4 when b"100",
BAUD_RT_5 when b"101",
BAUD_RT_6 when b"110",
BAUD_RT_7 when others;
-- max divisor would be 50,000,000 / 1,200 bps = 46.667 < 64k-1
U_bit_rt_tx: process(clk, rst, tx_ld, en_tx_clk)
variable baud_cnt : integer range 0 to BAUD_CNTR_LIMIT;
begin
if rst = '0' then
baud_cnt := 0;
txclk <= '0';
txclk_rise <= '0';
elsif tx_ld = '1' and rising_edge(clk) then
baud_cnt := 1;
txclk <= '0';
txclk_rise <= '0';
elsif en_tx_clk = '1' and rising_edge(clk) then
if baud_cnt = tx_baud_div then
if txclk = '0' then
txclk_rise <= '1';
else
txclk_rise <= '0';
end if;
txclk <= not(txclk);
baud_cnt := 1;
else
baud_cnt := baud_cnt + 1;
txclk_rise <= '0';
end if;
end if;
end process U_bit_rt_tx;
-- U_bit_rt_rx:counter8 port map(clk,rst,reset_rxck,en_rx_clk,00,rx_bit_rt);
with ctrl(2 downto 0) select
rx_baud_div <= BAUD_RT_0 when b"000",
BAUD_RT_1 when b"001",
BAUD_RT_2 when b"010",
BAUD_RT_3 when b"011",
BAUD_RT_4 when b"100",
BAUD_RT_5 when b"101",
BAUD_RT_6 when b"110",
BAUD_RT_7 when others;
U_bit_rt_rx: process(clk, rst, reset_rxck, en_rx_clk)
variable baud_cnt : integer range 0 to BAUD_CNTR_LIMIT;
begin
if rst = '0' then
baud_cnt := 0;
rxclk <= '0';
rxclk_fall <= '0';
rxclk_rise <= '0';
elsif reset_rxck = '1' and rising_edge(clk) then
baud_cnt := (rx_baud_div / 2);
rxclk <= '0';
rxclk_fall <= '0';
rxclk_rise <= '0';
elsif en_rx_clk = '1' and rising_edge(clk) then
if baud_cnt = rx_baud_div then
if rxclk = '1' then
rxclk_fall <= '1';
else
rxclk_fall <= '0';
rxclk_rise <= '1';
end if;
baud_cnt := 1;
rxclk <= not(rxclk);
else
baud_cnt := baud_cnt + 1;
rxclk_fall <= '0';
rxclk_rise <= '0';
end if;
end if;
end process U_bit_rt_rx;
end architecture rtl;
-- -------------------------------------------------------------------
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- 8 bit register, reset=0 asynchronous, load=1 synchronous
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library ieee; use ieee.std_logic_1164.all;
use work.p_WIRES.all;
entity register8 is
port(clk, rst, ld: in std_logic;
D: in reg8;
Q: out reg8);
end register8;
architecture functional of register8 is
begin
process(clk, rst)
variable value: reg8;
begin
if rst = '0' then
value := x"00";
elsif rising_edge(clk) then
if ld = '1' then
value := D;
end if;
end if;
Q <= value;
end process;
end functional;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- 2 bit register, reset=0 asynchronous, load=1 synchronous
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library ieee; use ieee.std_logic_1164.all;
use work.p_WIRES.all;
entity register2 is
port(clk, rst, ld: in std_logic;
D: in reg2;
Q: out reg2);
end register2;
architecture functional of register2 is
begin
process(clk, rst)
variable value: reg2;
begin
if rst = '0' then
value := b"00";
elsif rising_edge(clk) then
if ld = '1' then
value := D;
end if;
end if;
Q <= value;
end process;
end functional;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- 10 bit shift-register, parallel load, serial output
-- reset=0 asynch, load=1 asynch, shift=1 synch, fills with '1's
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library ieee; use ieee.std_logic_1164.all;
use work.p_WIRES.all;
entity par_ser10 is
port(clk, rst, ld, desl: in std_logic;
D: in reg10;
Q: out std_logic);
end par_ser10;
architecture functional of par_ser10 is
begin
process(clk, rst, ld, desl, D)
variable value: reg10;
begin
if rst = '0' then
value := b"1111111111";
Q <= '1';
elsif ld = '1' and rising_edge(clk) then
value := D;
elsif desl = '1' and rising_edge(clk) then
Q <= value(0);
value(8 downto 0) := value(9 downto 1);
value(9) := '1'; -- when idle, send stop-bits
end if;
end process;
end functional;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- 10 bit shift register, serial input, parallel output
-- reset=0 asynch, load,shift=1 synch
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library ieee; use ieee.std_logic_1164.all;
use work.p_WIRES.all;
entity ser_par10 is
port(clk, rst, desl: in std_logic;
D: in std_logic;
Q: out reg10);
end ser_par10;
architecture functional of ser_par10 is
begin
process(clk, rst, desl)
variable value: reg10;
begin
if rst = '0' then
value := b"0000000000";
elsif desl = '1' and rising_edge(clk) then
value(8 downto 0) := value(9 downto 1);
value(9) := D;
end if;
Q <= value;
end process;
end functional;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- functional model for the "remote computer" -- for testing only
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.p_WIRES.all;
use work.p_UART.all;
entity remota is
generic(OUTPUT_FILE_NAME : string := "serial.out";
INPUT_FILE_NAME : string := "serial.inp");
port(rst, clk : in std_logic;
start : in std_logic; -- start operation =1
inpDat : in std_logic; -- serial input
outDat : out std_logic; -- serial output
bit_rt : in reg3); -- selects bit rate
constant EOT : reg8 := x"04"; -- end of transmission character
end remota;
architecture simulation of remota is
component counter8 is
port(clk, rst, ld, en: in std_logic;
D: in std_logic_vector;
Q: out std_logic_vector);
end component counter8;
-- transmission signals & states -----------------------------------------
type tx_state is (st_init, st_idle, st_start,
st_b0, st_b1, st_b2, st_b3, st_b4, st_b5, st_b6, st_b7,
st_stop, st_wait, st_done);
signal tx_current_st, tx_next_st : tx_state;
signal tx_dbg_st : integer; -- for debugging only
attribute SYN_ENCODING of tx_state : type is "safe";
signal tx_bit_rt : reg8;
signal tx_clk, tx_run : std_logic;
file input_stream : text open read_mode is INPUT_FILE_NAME;
-- file input_stream : text open read_mode is "STD_INPUT";
-- -----------------------------------------------------------------------
-- reception signals & states --------------------------------------------
type rx_state is (st_idle, st_check, st_start,
st_b0, st_b1, st_b2, st_b3, st_b4, st_b5, st_b6, st_b7,
st_stop, st_done);
signal rx_current_st, rx_next_st : rx_state;
signal rx_dbg_st : integer; -- for debugging only
attribute SYN_ENCODING of rx_state : type is "safe";
signal recv, rx_bit_rt : reg8;
signal rx_clk, rx_run, reset_rxck : std_logic;
signal tx_baud_div, rx_baud_div : integer := 0;
-- file output_stream : text open write_mode is OUTPUT_FILE_NAME;
file output_stream : text open write_mode is "STD_OUTPUT";
-- -----------------------------------------------------------------------
begin
-- transmission control SM ----------------------------------------------
U_TX_st_reg: process(rst,tx_clk)
begin
if rst = '0' then
tx_current_st <= st_wait;
elsif rising_edge(tx_clk) then
tx_current_st <= tx_next_st;
end if;
end process U_TX_st_reg;
tx_dbg_st <= integer(tx_state'pos(tx_current_st)); -- debugging only
U_tx: process (tx_current_st, start, rst)
variable sentence : line;
variable char : character;
variable good, send_eot : boolean;
variable bfr : reg8;
variable j : integer;
begin
case tx_current_st is
when st_wait => -- 12 wait for starting signal
outDat <= '1';
tx_run <= '0'; -- hold TX clock
send_eot := FALSE;
if start = '0' then
tx_next_st <= st_wait;
else
if not endfile(input_stream) and rst = '1' then
readline( input_stream, sentence ); -- read first line of text
assert TRUE report "fst line: "&integer'image(sentence'length);
j := 1;
tx_next_st <= st_init;
else
tx_next_st <= st_done; -- no input, done!
end if;
end if;
when st_init => -- 0
outDat <= '1';
tx_run <= '1'; -- start TX clock
tx_next_st <= st_idle;
when st_idle => -- 1
if not endfile(input_stream) then
if j > sentence'right then -- read new line of input
readline( input_stream, sentence );
assert TRUE report "new line: "&integer'image(sentence'length);
bfr := x"0a"; -- new line
j := 0;
elsif sentence'length = 0 then
bfr := x"0a"; -- send new line for empty line
assert TRUE report "empty line: " & integer'image(j)&" " & LF;
else
read (sentence, char, good);
assert TRUE report "read: " & integer'image(j) & " " &char;
bfr := std_logic_vector(to_signed( character'pos(char), 8));
end if;
tx_next_st <= st_start;
else
tx_next_st <= st_done; -- no more input, done!
end if;
when st_start => -- 2
outDat <= '0';
tx_next_st <= st_b0;
when st_b0 => -- 3
outDat <= bfr(0);
tx_next_st <= st_b1;
when st_b1 => -- 4
outDat <= bfr(1);
tx_next_st <= st_b2;
when st_b2 => -- 5
outDat <= bfr(2);
tx_next_st <= st_b3;
when st_b3 => -- 6
outDat <= bfr(3);
tx_next_st <= st_b4;
when st_b4 => -- 7
outDat <= bfr(4);
tx_next_st <= st_b5;
when st_b5 => -- 8
outDat <= bfr(5);
tx_next_st <= st_b6;
when st_b6 => -- 9
outDat <= bfr(6);
tx_next_st <= st_b7;
when st_b7 => -- 10
outDat <= bfr(7);
tx_next_st <= st_stop;
when st_stop => -- 11
j := j + 1;
outDat <= '1';
tx_next_st <= st_idle;
when st_done => -- 13 wait forever
if send_eot = FALSE then
bfr := EOT; -- send out an END-OF-TRANSMISSION
send_eot := TRUE;
tx_next_st <= st_start;
else
tx_next_st <= st_done; -- no more input, wait forever
outDat <= '1';
end if;
tx_run <= '0'; -- stop clock
when others =>
assert false report "REMOTE TX stateMachine broken"
& integer'image(tx_state'pos(tx_current_st)) severity failure;
end case;
end process U_tx;
-- ======================================================================
-- reception ============================================================
-- reception control SM -------------------------------------------------
U_RX_st_reg: process(rst,clk)
begin
if rst = '0' then
rx_current_st <= st_idle;
elsif rising_edge(clk) then
rx_current_st <= rx_next_st;
end if;
end process U_RX_st_reg;
rx_dbg_st <= integer(rx_state'pos(rx_current_st)); -- debugging only
U_rx: process(rx_current_st, rx_clk, inpDat)
variable msg : line;
begin
case rx_current_st is
when st_idle =>
reset_rxck <= '0';
rx_run <= '0';
recv <= (others => 'U');
if falling_edge(inpDat) then -- start bit
rx_next_st <= st_check;
else
rx_next_st <= st_idle;
end if;
when st_check =>
reset_rxck <= '1';
rx_run <= '1';
rx_next_st <= st_start;
when st_start =>
reset_rxck <= '0';
rx_next_st <= st_b0;
when st_b0 =>
if falling_edge(rx_clk) then
recv(0) <= inpDat;
rx_next_st <= st_b1;
else
rx_next_st <= st_b0;
end if;
when st_b1 =>
if falling_edge(rx_clk) then
recv(1) <= inpDat;
rx_next_st <= st_b2;
else
rx_next_st <= st_b1;
end if;
when st_b2 =>
if falling_edge(rx_clk) then
recv(2) <= inpDat;
rx_next_st <= st_b3;
else
rx_next_st <= st_b2;
end if;
when st_b3 =>
if falling_edge(rx_clk) then
recv(3) <= inpDat;
rx_next_st <= st_b4;
else
rx_next_st <= st_b3;
end if;
when st_b4 =>
if falling_edge(rx_clk) then
recv(4) <= inpDat;
rx_next_st <= st_b5;
else
rx_next_st <= st_b4;
end if;
when st_b5 =>
if falling_edge(rx_clk) then
recv(5) <= inpDat;
rx_next_st <= st_b6;
else
rx_next_st <= st_b5;
end if;
when st_b6 =>
if falling_edge(rx_clk) then
recv(6) <= inpDat;
rx_next_st <= st_b7;
else
rx_next_st <= st_b6;
end if;
when st_b7 =>
if falling_edge(rx_clk) then
recv(7) <= inpDat;
rx_next_st <= st_stop;
else
rx_next_st <= st_b7;
end if;
when st_stop =>
if falling_edge(rx_clk) then
rx_next_st <= st_done;
else
rx_next_st <= st_stop;
end if;
when st_done =>
rx_run <= '0';
rx_next_st <= st_idle;
if ((recv /= x"0a") and (recv /= x"04") and (recv /= x"00")) then
write ( msg, character'val(to_integer(unsigned(recv))) );
end if;
if ((recv = x"0a") or (recv = x"04") or (recv = x"00")) then
writeline( output_stream, msg );
end if;
when others =>
assert false report "REMOTE RX stateMachine broken"
& integer'image(rx_state'pos(rx_current_st)) severity failure;
end case;
end process U_rx;
-- baud rate generators ---------------------------------------------
with bit_rt select
tx_baud_div <= BAUD_RT_0 when b"000",
BAUD_RT_1 when b"001",
BAUD_RT_2 when b"010",
BAUD_RT_3 when b"011",
BAUD_RT_4 when b"100",
BAUD_RT_5 when b"101",
BAUD_RT_6 when b"110",
BAUD_RT_7 when others;
U_bit_rt_tx: process(clk, rst)
variable baud_cnt : integer;
begin
if rst = '0' then
baud_cnt := 0;
tx_clk <= '0';
elsif rising_edge(clk) then
if baud_cnt = tx_baud_div then
tx_clk <= not(tx_clk);
baud_cnt := 1;
else
baud_cnt := baud_cnt + 1;
end if;
end if;
end process U_bit_rt_tx;
-- RX clock daud rate
with bit_rt select
rx_baud_div <= BAUD_RT_0 when b"000",
BAUD_RT_1 when b"001",
BAUD_RT_2 when b"010",
BAUD_RT_3 when b"011",
BAUD_RT_4 when b"100",
BAUD_RT_5 when b"101",
BAUD_RT_6 when b"110",
BAUD_RT_7 when others;
U_bit_rt_rx: process(clk, rst, reset_rxck, rx_run)
variable baud_cnt : integer;
begin
if rst = '0' then
baud_cnt := 0;
rx_clk <= '0';
elsif reset_rxck = '1' and rising_edge(clk) then
baud_cnt := 1;
rx_clk <= '0';
elsif rx_run = '1' and rising_edge(clk) then
if baud_cnt = rx_baud_div then
rx_clk <= not(rx_clk);
baud_cnt := 1;
else
baud_cnt := baud_cnt + 1;
end if;
end if;
end process U_bit_rt_rx;
end architecture simulation;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
architecture fake of remota is
begin -- fake
outDat <= 'X';
end architecture fake;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| gpl-3.0 | f9933f9d7c64ed680fd3f6a7576c212d | 0.493499 | 3.477041 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/3-ARF/metaheurísticas/arf_hype.vhd | 1 | 2,433 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-13.07:34:57)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY arf_hype_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8: IN unsigned(0 TO 3);
output1, output2: OUT unsigned(0 TO 4));
END arf_hype_entity;
ARCHITECTURE arf_hype_description OF arf_hype_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
register2 := input2 * 2;
WHEN "00000010" =>
register1 := register1 + register2;
register2 := input3 * 3;
register3 := input4 * 4;
WHEN "00000011" =>
register4 := input5 * 5;
register1 := register1 + 7;
register5 := input6 * 8;
register2 := register3 + register2;
WHEN "00000100" =>
register3 := input7 * 9;
register6 := input8 * 10;
register4 := register5 + register4;
WHEN "00000101" =>
register5 := register1 * 12;
register1 := register1 * 14;
register3 := register3 + register6;
register4 := register4 + 16;
WHEN "00000110" =>
register6 := register4 * 18;
register4 := register4 * 20;
WHEN "00000111" =>
register1 := register1 + register4;
register4 := register5 + register6;
WHEN "00001000" =>
register5 := register4 * 22;
register6 := register1 * 24;
WHEN "00001001" =>
register1 := register1 * 26;
register4 := register4 * 28;
register5 := register5 + register6;
WHEN "00001010" =>
register1 := register4 + register1;
output1 <= register3 + register5;
WHEN "00001011" =>
output2 <= register2 + register1;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END arf_hype_description; | gpl-3.0 | ad61ee4a752ee8e2919b5811629f8e06 | 0.654336 | 3.09542 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/1-HAL/metaheurísticas/hal_spea2.vhd | 1 | 1,546 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.09:05:51)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY hal_spea2_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5: IN unsigned(0 TO 3);
output1, output2, output3: OUT unsigned(0 TO 4));
END hal_spea2_entity;
ARCHITECTURE hal_spea2_description OF hal_spea2_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
register2 := input2 * 2;
WHEN "00000010" =>
output1 <= register2 + 3;
register2 := input3 * 4;
IF (register1 < 5) THEN
output2 <= register1;
ELSE
output2 <= "00101";
END IF;
register1 := input4 * 6;
WHEN "00000011" =>
register1 := register2 * register1;
WHEN "00000100" =>
register1 := register1 - 8;
register2 := input5 * 9;
WHEN "00000101" =>
register2 := register2 * 11;
WHEN "00000110" =>
output3 <= register1 - register2;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END hal_spea2_description; | gpl-3.0 | 8aa179f73e0359367f590714da03d12d | 0.655239 | 2.956023 | false | false | false | false |
rhexsel/xinu-cMIPS | vhdl/units.vhd | 2 | 21,553 | -- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Altera's design for a dual-port RAM that can be synthesized
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library ieee;
use ieee.std_logic_1164.all;
entity ram_dual is
generic (N_WORDS : integer := 64;
WIDTH : integer := 8);
port (data : in std_logic_vector(WIDTH - 1 downto 0);
raddr : in natural range 0 to N_WORDS - 1;
waddr : in natural range 0 to N_WORDS - 1;
we : in std_logic;
rclk : in std_logic;
wclk : in std_logic;
q : out std_logic_vector(WIDTH - 1 downto 0));
end ram_dual;
architecture rtl of ram_dual is
-- Build a 2-D array type for the RAM
subtype word_t is std_logic_vector(WIDTH - 1 downto 0);
type memory_t is array(N_WORDS - 1 downto 0) of word_t;
-- Declare the RAM signal.
signal ram : memory_t; -- := (others => (others => '0'));
begin
process(wclk)
begin
if(rising_edge(wclk)) then
if(we = '1') then
ram(waddr) <= data;
end if;
end if;
end process;
process(rclk)
begin
if(rising_edge(rclk)) then
q <= ram(raddr);
end if;
end process;
end rtl;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- register bank, reg(0) always 0, write-enable=0
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_Logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
entity reg_bank is
port(wrclk, rdclk, wren : in std_logic;
a_rs, a_rt, a_rd : in reg5;
C : in reg32;
A, B : out reg32);
end reg_bank;
-- -----------------------------------------------------------------------
-- RTL with implicit memory
-- -----------------------------------------------------------------------
architecture rtl of reg_bank is
type reg_file is array(0 to 31) of reg32;
signal reg_file_A : reg_file;
signal reg_file_B : reg_file;
signal int_rs, int_rt, int_rd : integer range 0 to 31;
signal pre_A, pre_B : reg32;
begin
int_rs <= to_integer(unsigned(a_rs));
int_rt <= to_integer(unsigned(a_rt));
int_rd <= to_integer(unsigned(a_rd));
-- forwarding WB -> RF, external to RAM
A <= C when (a_rd = a_rs) and (wren = '0') and (a_rs /= b"00000")
else pre_A when a_rs /= b"00000"
else x"00000000"; -- reg0 always zero
B <= C when (a_rd = a_rt) and (wren = '0') and (a_rt /= b"00000")
else pre_B when a_rt /= b"00000"
else x"00000000";
WRITE_REG_BANKS: process(wrclk, rdclk)
begin
if rising_edge(rdclk) then -- read early
pre_A <= reg_file_A( int_rs );
pre_B <= reg_file_B( int_rt );
end if;
-- write to enforce setup (forwarding is external to RAM)
if rising_edge(wrclk) then
if wren = '0' and int_rd /= 0 then
reg_file_A( int_rd ) <= C;
reg_file_B( int_rd ) <= C;
end if;
end if;
end process WRITE_REG_BANKS;
end rtl;
-- -----------------------------------------------------------------------
-- -----------------------------------------------------------------------
-- RTL with explicitly declared dual-port RAMs (FPGA friendly)
-- -----------------------------------------------------------------------
architecture dual_port_ram of reg_bank is
component ram_dual is
generic (N_WORDS : integer;
WIDTH : integer);
port (data : in std_logic_vector;
raddr : in natural range 0 to N_WORDS-1;
waddr : in natural range 0 to N_WORDS-1;
we : in std_logic;
rclk : in std_logic;
wclk : in std_logic;
q : out std_logic_vector);
end component ram_dual;
signal int_rs, int_rt, int_rd : integer range 0 to 31;
signal pre_A, pre_B : reg32;
signal update : std_logic;
begin
int_rs <= to_integer(unsigned(a_rs));
int_rt <= to_integer(unsigned(a_rt));
int_rd <= to_integer(unsigned(a_rd));
update <= '1' when wren = '0' and int_rd /= 0 else '0';
PORT_A: ram_dual generic map (32, 32)
port map (C, int_rs, int_rd, update, rdclk, wrclk, pre_A);
PORT_B: ram_dual generic map (32, 32)
port map (C, int_rt, int_rd, update, rdclk, wrclk, pre_B);
-- internal forwarding WB -> RF
A <= C when (a_rd = a_rs) and (wren = '0') and (a_rs /= b"00000") else
pre_A when a_rs /= b"00000"
else x"00000000"; -- reg0 always zero
B <= C when (a_rd = a_rt) and (wren = '0') and (a_rt /= b"00000") else
pre_B when a_rt /= b"00000"
else x"00000000";
end architecture dual_port_ram;
-- -----------------------------------------------------------------------
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ALU
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
entity alu is
port(clk,rst: in std_logic;
A, B: in reg32;
C: out reg32;
LO: out reg32;
HI: out reg32;
wr_hilo: in std_logic; -- write to HI & LO, active high
move_ok: out std_logic;
fun: in t_alu_fun;
postn: in reg5;
shamt: in reg5;
ovfl: out std_logic);
end alu;
architecture functional of alu is
component register32 is
generic (INITIAL_VALUE: std_logic_vector);
port(clk, rst, ld: in std_logic;
D: in std_logic_vector;
Q: out std_logic_vector);
end component register32;
component mf_alt_add_sub is
port(add_sub : IN STD_LOGIC; -- add=1, sub=0
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
overflow : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0));
end component mf_alt_add_sub;
component mf_alt_add_sub_u is
port(add_sub : IN STD_LOGIC; -- add=1, sub=0
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0));
end component mf_alt_add_sub_u;
component mask_off_bits is
port(B : in std_logic_vector;
X : out std_logic_vector);
end component mask_off_bits;
component shift_left32 is
port(inp : in reg32;
shamt : in reg5;
otp : out reg32);
end component shift_left32;
component shift_right32 is
port(inp : in reg32;
arith: in std_logic;
shamt : in reg5;
otp : out reg32);
end component shift_right32;
signal operation : integer;
signal s_HI,s_LO, loc_HI,loc_LO, inp_HI,inp_LO, mask,mask_and : reg32;
signal sh_left, sh_right, sh_inp, sh_lft_ins, summ_diff, summ_diff_u : reg32;
signal addition, overflow, overflow_u, shift_arith, wr_hi,wr_lo : std_logic;
signal size,index, shift_amnt : reg5;
begin
assert fun /= invalid_op
report "INVALID ALU OPERATION: " & integer'image(operation)
severity failure;
operation <= t_alu_fun'pos(fun); -- for debugging only
U_alu: process (A,B, fun, sh_left,sh_right,sh_lft_ins,
mask, loc_HI,loc_LO, summ_diff, summ_diff_u, overflow)
variable i_C, i_and, i_or: reg32;
variable i_prod : reg64;
variable i_move_ok, B_is_zero : std_logic := 'L';
begin
ovfl <= '0';
addition <= '0';
i_move_ok := '0';
if (B = x"00000000") then B_is_zero := '1'; else B_is_zero := '0'; end if;
i_C := (others => '0');
case fun is
when opSLL | opSLLV => i_C := sh_left;
when opSRL | opSRA | opSRLV | opSRAV => i_C := sh_right;
when opMOVZ => -- reg_update handled at EX_stage
if (B_is_zero = '1') then
i_C := A;
i_move_ok := '1';
end if;
when opMOVN => -- reg_update handled at EX_stage
if (B_is_zero /= '1') then
i_C := A;
i_move_ok := '1';
end if;
when opMFHI => i_C := loc_HI;
when opMFLO => i_C := loc_LO;
when opADD => addition <= '1';
i_C := summ_diff;
ovfl <= overflow;
when opADDU => addition <= '1';
i_C := summ_diff_u;
ovfl <= '0';
when opSUB => addition <= '0';
i_C := summ_diff;
ovfl <= overflow;
when opSUBU => addition <= '0';
i_C := summ_diff_u;
ovfl <= '0';
when opAND => i_C := A and B;
when opOR => i_C := A or B;
when opXOR => i_C := A xor B;
when opNOR => i_C := A nor B;
when opSLT => addition <= '0';
if ( overflow = '1' ) then -- ovfl
i_C := x"0000000" & b"000" & not(summ_diff(31));
else
i_C := x"0000000" & b"000" & summ_diff(31);
end if;
-- this instr cannot cause an exception
when opSLTU => addition <= '0'; -- ignore overflow/signal
i_C := x"0000000" & b"000" & summ_diff_u(31);
ovfl <= '0';
when opLUI => i_C := B(15 downto 0) & x"0000";
when opSWAP => -- word swap bytes within halfwords
i_C := B(23 downto 16)&B(31 downto 24)&B(7 downto 0) &B(15 downto 8);
when opEXT => -- extract bit field
i_C := sh_right and mask;
when opINS => -- insert bit field
i_and := B and not(sh_left);
i_or := sh_lft_ins;
i_C := i_and or i_or;
when opSEB => -- sign-extend byte
if B(7) = '0' then
i_C := x"000000" & B(7 downto 0);
else
i_C := x"FFFFFF" & B(7 downto 0);
end if;
when opSEH => -- sign-extend halfword
if B(15) = '0' then
i_C := x"0000" & B(15 downto 0);
else
i_C := x"FFFF" & B(15 downto 0);
end if;
when opMUL =>
i_prod := std_logic_vector(signed(A) * signed(B));
i_C := i_prod(31 downto 0);
when others =>
i_C := (others => 'X');
end case;
--assert false report "alu: " &
-- "A="& SLV32HEX(A) &" ["& natural'image(operation) &"] B="&
-- SLV32HEX(B) &" ="& SLV32HEX( i_C ); -- DEBUG
move_ok <= i_move_ok;
C <= i_C;
end process U_alu; -- -------------------------------------------
U_ADD_SUB: mf_alt_add_sub -- signed add/subtract
port map (add_sub => addition, overflow => overflow,
dataa => A, datab => B, result => summ_diff);
U_ADD_SUB_U: mf_alt_add_sub_u -- UNsigned add/subtract, no overflow
port map (add_sub => addition,
dataa => A, datab => B, result => summ_diff_u);
U_HILO: process (A,B, fun, loc_HI,loc_LO)
variable i_hi,i_lo, i_quoc,i_rem: reg32;
variable i_prod : reg64;
variable s_quoc, s_rem : unsigned(31 downto 0);
begin
i_LO := (others => '0');
i_HI := (others => '0');
s_quoc := (others => '0');
s_rem := (others => '0');
case fun is
when opMULT | opMULTU =>
i_prod := std_logic_vector(signed(A) * signed(B));
i_LO := i_prod(31 downto 0);
i_HI := i_prod(63 downto 32);
when opDIV | opDIVU =>
if ( B = x"00000000" ) then -- NO exceptions caused by division
assert true report
"div by zero A="& SLV32HEX(A) &"["& integer'image(operation)&"]"
& SLV32HEX(B); -- DEBUG
i_quoc := x"FFFFFFFF";
i_rem := x"FFFFFFFF";
else
-- divmod(unsigned(A),unsigned(B),s_quoc,s_rem);
s_quoc := unsigned(A) / unsigned(B);
s_rem := unsigned(A) rem unsigned(B);
end if;
i_quoc := std_logic_vector(s_quoc);
i_rem := std_logic_vector(s_rem);
i_LO := i_quoc;
i_HI := i_rem;
when others =>
i_hi := (others => 'X'); -- to help synthesis
i_lo := (others => 'X'); -- to help synthesis
s_quoc := (others => 'X'); -- to help synthesis
s_rem := (others => 'X'); -- to help synthesis
end case;
s_HI <= i_hi;
s_LO <= i_lo;
end process U_HILO; -- -------------------------------------------
U_hilo_inp: process (A, fun, s_HI, s_LO, wr_hilo)
begin
wr_lo <= '1';
wr_hi <= '1';
case fun is
when opMULT | opMULTU | opDIV | opDIVU =>
wr_lo <= wr_hilo;
wr_hi <= wr_hilo;
inp_HI <= s_HI;
inp_LO <= s_LO;
when opMTLO =>
wr_lo <= wr_hilo;
inp_LO <= A;
wr_hi <= '1';
inp_HI <= (others => 'X');
when opMTHI =>
wr_hi <= wr_hilo;
inp_HI <= A;
wr_lo <= '1';
inp_LO <= (others => 'X');
when others =>
wr_lo <= '1';
wr_hi <= '1';
inp_LO <= (others => 'X');
inp_HI <= (others => 'X');
end case;
end process U_hilo_inp; -- -------------------------------------------
U_HI: register32 generic map (x"00000000")
port map(clk, rst, wr_hi, inp_HI, loc_HI);
U_LO: register32 generic map (x"00000000")
port map(clk, rst, wr_lo, inp_LO, loc_LO);
HI <= loc_HI;
LO <= loc_LO;
U_shifts: process (A,B, fun, shamt, mask)
begin
case fun is
when opSLL | opSRL =>
sh_inp <= B;
shift_arith <= '0';
shift_amnt <= shamt;
when opSRA =>
sh_inp <= B;
shift_arith <= '1';
shift_amnt <= shamt;
when opSLLV | opSRLV => -- operators RS and RT exchanged!!
sh_inp <= B;
shift_arith <= '0';
shift_amnt <= A(4 downto 0);
when opSRAV => -- operators RS and RT exchanged!!
sh_inp <= B;
shift_arith <= '1';
shift_amnt <= A(4 downto 0);
when opEXT =>
sh_inp <= A;
shift_arith <= '0';
shift_amnt <= shamt;
when opINS =>
sh_inp <= mask;
shift_arith <= '0';
shift_amnt <= shamt;
when others =>
-- sh_inp <= B;
-- shift_arith <= '0';
-- shift_amnt <= b"00000";
sh_inp <= (others => 'X');
shift_arith <= '0';
shift_amnt <= (others => 'X');
end case;
end process U_shifts; -- -------------------------------------------
U_sh_left: shift_left32 port map (sh_inp,shift_amnt, sh_left);
U_sh_right: shift_right32 port map (sh_inp,shift_arith,shift_amnt, sh_right);
U_sh_left_ins: shift_left32 port map (mask_and,shift_amnt, sh_lft_ins);
size <= std_logic_vector(unsigned(postn) - unsigned(shamt));
index <= size when (fun = opINS) else postn;
U_mask: mask_off_bits port map (index, mask);
mask_and <= A and mask;
end functional;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- sel32: select bit field (right aligned)
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all;
use work.p_wires.all;
entity mask_off_bits is
port(B : in reg5;
X : out reg32);
end mask_off_bits;
architecture table of mask_off_bits is
type sel_vector is array (0 to 31) of reg32;
constant sel_array : sel_vector := (
x"00000001",--0
x"00000003",
x"00000007",
x"0000000f",
x"0000001f",--4
x"0000003f",
x"0000007f",
x"000000ff",
x"000001ff",--8
x"000003ff",
x"000007ff",
x"00000fff",
x"00001fff",--12
x"00003fff",
x"00007fff",
x"0000ffff",
x"0001ffff",--16
x"0003ffff",
x"0007ffff",
x"000fffff",
x"001fffff",--20
x"003fffff",
x"007fffff",
x"00ffffff",
x"01ffffff",--24
x"03ffffff",
x"07ffffff",
x"0fffffff",
x"1fffffff",--28
x"3fffffff",
x"7fffffff",
x"ffffffff");
begin
X <= sel_array(to_integer(unsigned(B)));
end table;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- shift-left32: shift left a specified number of bits
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE; use IEEE.std_logic_1164.all;
use work.p_wires.all;
entity shift_left32 is
port(inp : in reg32;
shamt : in reg5;
otp : out reg32);
end shift_left32;
architecture functional of shift_left32 is
begin
U_shift_left: process (inp, shamt)
variable i_1, i_2, i_4, i_8, i_16 : reg32;
begin
if shamt(0) = '1' then i_1 := inp(30 downto 0) & b"0";
else i_1 := inp;
end if;
if shamt(1) = '1' then i_2 := i_1(29 downto 0) & b"00";
else i_2 := i_1;
end if;
if shamt(2) = '1' then i_4 := i_2(27 downto 0) & b"0000";
else i_4 := i_2;
end if;
if shamt(3) = '1' then i_8 := i_4(23 downto 0) & b"00000000";
else i_8 := i_4;
end if;
if shamt(4) = '1' then i_16 := i_8(15 downto 0) & b"0000000000000000";
else i_16 := i_8;
end if;
otp <= i_16;
end process U_shift_left;
end functional;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- shift-right32: shift right a specified number of bits
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE; use IEEE.std_logic_1164.all;
use work.p_wires.all;
entity shift_right32 is
port(inp : in reg32;
arith: in std_logic;
shamt : in reg5;
otp : out reg32);
end shift_right32;
architecture functional of shift_right32 is
begin
U_shift_right: process (inp, arith, shamt)
variable i_1, i_2, i_4, i_8, i_16, sign_ext : reg32;
begin -- process U_shift_right
if arith = '1' then sign_ext := (others => inp(31));
else sign_ext := (others => '0');
end if;
if shamt(0) = '1' then i_1 := sign_ext(31) & inp(31 downto 1);
else i_1 := inp;
end if;
if shamt(1) = '1' then i_2 := sign_ext(31 downto 30) & i_1(31 downto 2);
else i_2 := i_1;
end if;
if shamt(2) = '1' then i_4 := sign_ext(31 downto 28) & i_2(31 downto 4);
else i_4 := i_2;
end if;
if shamt(3) = '1' then i_8 := sign_ext(31 downto 24) & i_4(31 downto 8);
else i_8 := i_4;
end if;
if shamt(4) = '1' then i_16 := sign_ext(31 downto 16) & i_8(31 downto 16);
else i_16 := i_8;
end if;
otp <= i_16;
end process U_shift_right;
end functional;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- bus interface: generates ONE wait-state request
-- peripheral/mem must generate additional waits, if needed
-- "waiting" is active only for the first clock cycle of reference
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE; use IEEE.std_logic_1164.all;
use work.p_wires.all;
entity wait_states is
generic (NUM_WAIT_STATES :integer := 0);
port(rst : in std_logic;
clk : in std_logic;
sel : in std_logic; -- active in '0'
waiting : out std_logic); -- active in '1'
end wait_states;
architecture structural of wait_states is
component FFD is
port(clk, rst, set, D : in std_logic; Q : out std_logic);
end component FFD;
component FFT is
port(clk, rst, T : in std_logic; Q : out std_logic);
end component FFT;
signal will_wait, w, w_d, n_sel, cycle, this : std_logic;
begin
n_sel <= not(sel);
will_wait <= '0' when NUM_WAIT_STATES = 0 else '1';
-- modulo 2 reference counter, changes at every reference
U_DO_WAIT: FFT port map
(clk => clk, rst => rst, T => n_sel, Q => cycle);
-- ref counter delayed, so will deactivate "waiting" at end of 1st clock
U_OLD_CYCLE: FFD port map
(clk => clk, rst => rst, set => '1', D => cycle, Q => this);
-- w_d <= this xor cycle; -- active for ONE cycle only
waiting <= not(this xor cycle) and n_sel and will_wait;
end;
-- ++ wait_states +++++++++++++++++++++++++++++++++++++++++++++++++++++
| gpl-3.0 | 0e615a84b242785c3a89a943f1f79917 | 0.477985 | 3.444622 | false | false | false | false |
sils1297/HWPrak14 | task_4/project_1.srcs/sources_1/new/DataMemory.vhd | 1 | 746 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity DataMemory is
Port(
writeM : in std_ulogic;
outM : in std_ulogic_vector(15 downto 0);
addressM : in std_ulogic_vector(9 downto 0);
inM : out std_ulogic_vector(15 downto 0);
clock : in std_ulogic
);
end DataMemory;
architecture Behavioral of DataMemory is
begin
BRAM_inst : entity work.BRAM(Behavioral)
generic map(MEM_ADDR_WIDTH => 10,
MEM_DATA_WIDTH => 16,
EDGE_TYPE => false,
MEM_NAME => "H:\hwprak\task_4\data.hack")
port map(Clock => clock,
WriteEnable => writeM,
Address => addressM,
WriteData => outM,
ReadData => inM);
end Behavioral;
| agpl-3.0 | ebcf6a3d0341b93b442cce309902c726 | 0.604558 | 3.257642 | false | false | false | false |
freecores/twofish | vhdl/twofish_cbc_decryption_monte_carlo_testbench_128bits.vhd | 1 | 11,356 | -- Twofish_cbc_decryption_monte_carlo_testbench_128bits.vhd
-- Copyright (C) 2006 Spyros Ninos
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this library; see the file COPYING. If not, write to:
--
-- Free Software Foundation
-- 59 Temple Place - Suite 330
-- Boston, MA 02111-1307, USA.
--
-- description : this file is the testbench for the Decryption Monte Carlo KAT of the twofish cipher with 128 bit key
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_arith.all;
use std.textio.all;
entity cbc_decryption_monte_carlo_testbench128 is
end cbc_decryption_monte_carlo_testbench128;
architecture cbc_decryption128_monte_carlo_testbench_arch of cbc_decryption_monte_carlo_testbench128 is
component reg128
port (
in_reg128 : in std_logic_vector(127 downto 0);
out_reg128 : out std_logic_vector(127 downto 0);
enable_reg128, reset_reg128, clk_reg128 : in std_logic
);
end component;
component twofish_keysched128
port (
odd_in_tk128,
even_in_tk128 : in std_logic_vector(7 downto 0);
in_key_tk128 : in std_logic_vector(127 downto 0);
out_key_up_tk128,
out_key_down_tk128 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_whit_keysched128
port (
in_key_twk128 : in std_logic_vector(127 downto 0);
out_K0_twk128,
out_K1_twk128,
out_K2_twk128,
out_K3_twk128,
out_K4_twk128,
out_K5_twk128,
out_K6_twk128,
out_K7_twk128 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_decryption_round128
port (
in1_tdr128,
in2_tdr128,
in3_tdr128,
in4_tdr128,
in_Sfirst_tdr128,
in_Ssecond_tdr128,
in_key_up_tdr128,
in_key_down_tdr128 : in std_logic_vector(31 downto 0);
out1_tdr128,
out2_tdr128,
out3_tdr128,
out4_tdr128 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_data_input
port (
in_tdi : in std_logic_vector(127 downto 0);
out_tdi : out std_logic_vector(127 downto 0)
);
end component;
component twofish_data_output
port (
in_tdo : in std_logic_vector(127 downto 0);
out_tdo : out std_logic_vector(127 downto 0)
);
end component;
component demux128
port ( in_demux128 : in std_logic_vector(127 downto 0);
out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0);
selection_demux128 : in std_logic
);
end component;
component mux128
port ( in1_mux128, in2_mux128 : in std_logic_vector(127 downto 0);
selection_mux128 : in std_logic;
out_mux128 : out std_logic_vector(127 downto 0)
);
end component;
component twofish_S128
port (
in_key_ts128 : in std_logic_vector(127 downto 0);
out_Sfirst_ts128,
out_Ssecond_ts128 : out std_logic_vector(31 downto 0)
);
end component;
FILE input_file : text is in "twofish_cbc_decryption_monte_carlo_testvalues_128bits.txt";
FILE output_file : text is out "twofish_cbc_decryption_monte_carlo_128bits_results.txt";
-- we create the functions that transform a number to text
-- transforming a signle digit to a character
function digit_to_char(number : integer range 0 to 9) return character is
begin
case number is
when 0 => return '0';
when 1 => return '1';
when 2 => return '2';
when 3 => return '3';
when 4 => return '4';
when 5 => return '5';
when 6 => return '6';
when 7 => return '7';
when 8 => return '8';
when 9 => return '9';
end case;
end;
-- transforming multi-digit number to text
function to_text(int_number : integer range 0 to 9999) return string is
variable our_text : string (1 to 4) := (others => ' ');
variable thousands,
hundreds,
tens,
ones : integer range 0 to 9;
begin
ones := int_number mod 10;
tens := ((int_number mod 100) - ones) / 10;
hundreds := ((int_number mod 1000) - (int_number mod 100)) / 100;
thousands := (int_number - (int_number mod 1000)) / 1000;
our_text(1) := digit_to_char(thousands);
our_text(2) := digit_to_char(hundreds);
our_text(3) := digit_to_char(tens);
our_text(4) := digit_to_char(ones);
return our_text;
end;
signal odd_number,
even_number : std_logic_vector(7 downto 0);
signal input_data,
output_data,
twofish_key,
to_encr_reg128,
from_tdi_to_xors,
to_output_whit_xors,
from_xors_to_tdo,
to_mux, to_demux,
from_input_whit_xors,
to_round,
to_input_mux : std_logic_vector(127 downto 0) ;
signal key_up,
key_down,
Sfirst,
Ssecond,
from_xor0,
from_xor1,
from_xor2,
from_xor3,
K0,K1,K2,K3,
K4,K5,K6,K7 : std_logic_vector(31 downto 0);
signal clk : std_logic := '0';
signal mux_selection : std_logic := '0';
signal demux_selection: std_logic := '0';
signal enable_encr_reg : std_logic := '0';
signal reset : std_logic := '0';
signal enable_round_reg : std_logic := '0';
-- begin the testbench arch description
begin
-- getting data to encrypt
data_input: twofish_data_input
port map (
in_tdi => input_data,
out_tdi => from_tdi_to_xors
);
-- producing whitening keys K0..7
the_whitening_step: twofish_whit_keysched128
port map (
in_key_twk128 => twofish_key,
out_K0_twk128 => K0,
out_K1_twk128 => K1,
out_K2_twk128 => K2,
out_K3_twk128 => K3,
out_K4_twk128 => K4,
out_K5_twk128 => K5,
out_K6_twk128 => K6,
out_K7_twk128 => K7
);
-- performing the input whitening XORs
from_xor0 <= K4 XOR from_tdi_to_xors(127 downto 96);
from_xor1 <= K5 XOR from_tdi_to_xors(95 downto 64);
from_xor2 <= K6 XOR from_tdi_to_xors(63 downto 32);
from_xor3 <= K7 XOR from_tdi_to_xors(31 downto 0);
from_input_whit_xors <= from_xor0 & from_xor1 & from_xor2 & from_xor3;
round_reg: reg128
port map ( in_reg128 => from_input_whit_xors,
out_reg128 => to_input_mux,
enable_reg128 => enable_round_reg,
reset_reg128 => reset,
clk_reg128 => clk );
input_mux: mux128
port map ( in1_mux128 => to_input_mux,
in2_mux128 => to_mux,
out_mux128 => to_round,
selection_mux128 => mux_selection
);
-- creating a round
the_keysched_of_the_round: twofish_keysched128
port map (
odd_in_tk128 => odd_number,
even_in_tk128 => even_number,
in_key_tk128 => twofish_key,
out_key_up_tk128 => key_up,
out_key_down_tk128 => key_down
);
producing_the_Skeys: twofish_S128
port map (
in_key_ts128 => twofish_key,
out_Sfirst_ts128 => Sfirst,
out_Ssecond_ts128 => Ssecond
);
the_decryption_circuit: twofish_decryption_round128
port map (
in1_tdr128 => to_round(127 downto 96),
in2_tdr128 => to_round(95 downto 64),
in3_tdr128 => to_round(63 downto 32),
in4_tdr128 => to_round(31 downto 0),
in_Sfirst_tdr128 => Sfirst,
in_Ssecond_tdr128 => Ssecond,
in_key_up_tdr128 => key_up,
in_key_down_tdr128 => key_down,
out1_tdr128 => to_encr_reg128(127 downto 96),
out2_tdr128 => to_encr_reg128(95 downto 64),
out3_tdr128 => to_encr_reg128(63 downto 32),
out4_tdr128 => to_encr_reg128(31 downto 0)
);
encr_reg: reg128
port map ( in_reg128 => to_encr_reg128,
out_reg128 => to_demux,
enable_reg128 => enable_encr_reg,
reset_reg128 => reset,
clk_reg128 => clk );
output_demux: demux128
port map ( in_demux128 => to_demux,
out1_demux128 => to_output_whit_xors,
out2_demux128 => to_mux,
selection_demux128 => demux_selection );
-- don't forget the last swap !!!
from_xors_to_tdo(127 downto 96) <= K0 XOR to_output_whit_xors(63 downto 32);
from_xors_to_tdo(95 downto 64) <= K1 XOR to_output_whit_xors(31 downto 0);
from_xors_to_tdo(63 downto 32) <= K2 XOR to_output_whit_xors(127 downto 96);
from_xors_to_tdo(31 downto 0) <= K3 XOR to_output_whit_xors(95 downto 64);
taking_the_output: twofish_data_output
port map (
in_tdo => from_xors_to_tdo,
out_tdo => output_data
);
-- we create the clock
clk <= not clk after 50 ns; -- period 100 ns
cbc_dmc_proc: process
variable key_f, -- key input from file
pt_f, -- plaintext from file
ct_f,
iv_f : line; -- ciphertext from file
variable key_v, -- key vector input
pt_v , -- plaintext vector
ct_v,
iv_v : std_logic_vector(127 downto 0); -- ciphertext vector
variable counter_10000 : integer range 0 to 9999 := 0; -- counter for the 10.000 repeats in the 400 next ones
variable counter_400 : integer range 0 to 399 := 0; -- counter for the 400 repeats
variable round : integer range 0 to 16 := 0; -- holds the rounds
variable PT, CT, CV, CTj_1 : std_logic_vector(127 downto 0) := (others => '0');
begin
while not endfile(input_file) loop
readline(input_file, key_f);
readline(input_file, iv_f);
readline(input_file,ct_f);
readline(input_file, pt_f);
hread(key_f,key_v);
hread(iv_f, iv_v);
hread(ct_f,ct_v);
hread(pt_f,pt_v);
twofish_key <= key_v;
CV := iv_v;
CT := ct_v;
for counter_10000 in 0 to 9999 loop
input_data <= CT;
wait for 25 ns;
reset <= '1';
wait for 50 ns;
reset <= '0';
mux_selection <= '0';
demux_selection <= '1';
enable_encr_reg <= '0';
enable_round_reg <= '0';
wait for 50 ns;
enable_round_reg <= '1';
wait for 50 ns;
enable_round_reg <= '0';
-- the first round
even_number <= "00100110"; -- 38
odd_number <= "00100111"; -- 39
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
demux_selection <= '1';
mux_selection <= '1';
-- the rest 15 rounds
for round in 1 to 15 loop
even_number <= conv_std_logic_vector((((15-round)*2)+8), 8);
odd_number <= conv_std_logic_vector((((15-round)*2)+9), 8);
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
end loop;
-- taking final results
demux_selection <= '0';
wait for 25 ns;
PT := output_data XOR CV;
CV := CT;
CT := PT;
assert false report "I=" & to_text(counter_400) & " R=" & to_text(counter_10000) severity note;
end loop; -- counter_10000
hwrite(key_f, key_v);
hwrite(iv_f, iv_v);
hwrite(ct_f, ct_v);
hwrite(pt_f, PT);
writeline(output_file,key_f);
writeline(output_file, iv_f);
writeline(output_file,ct_f);
writeline(output_file,pt_f);
assert (pt_v = PT) report "file entry and decryption result DO NOT match!!! :( " severity failure;
assert (pt_v /= PT) report "Decryption I=" & to_text(counter_400) &" OK" severity note;
counter_400 := counter_400 + 1;
end loop;
assert false report "***** CBC Decryption Monte Carlo Test with 128 bits key size ended succesfully! :) *****" severity failure;
end process cbc_dmc_proc;
end cbc_decryption128_monte_carlo_testbench_arch;
| gpl-2.0 | c6cbc53cd94daaf5665a1b550111730c | 0.645386 | 2.705742 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/3-ARF/metaheurísticas/arf_wsga.vhd | 1 | 2,433 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-13.07:35:29)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY arf_wsga_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8: IN unsigned(0 TO 3);
output1, output2: OUT unsigned(0 TO 4));
END arf_wsga_entity;
ARCHITECTURE arf_wsga_description OF arf_wsga_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
register2 := input2 * 2;
WHEN "00000010" =>
register1 := register2 + register1;
register2 := input3 * 3;
register3 := input4 * 4;
WHEN "00000011" =>
register2 := register3 + register2;
register3 := input5 * 5;
register4 := input6 * 6;
WHEN "00000100" =>
register3 := register4 + register3;
register4 := input7 * 7;
register5 := input8 * 8;
WHEN "00000101" =>
register4 := register5 + register4;
register2 := register2 + 10;
register3 := register3 + 12;
WHEN "00000110" =>
register5 := register2 * 14;
register6 := register3 * 16;
WHEN "00000111" =>
register5 := register6 + register5;
register2 := register2 * 18;
register3 := register3 * 20;
WHEN "00001000" =>
register6 := register5 * 22;
register5 := register5 * 24;
register2 := register3 + register2;
WHEN "00001001" =>
register3 := register2 * 26;
register2 := register2 * 28;
WHEN "00001010" =>
register2 := register5 + register2;
register3 := register6 + register3;
WHEN "00001011" =>
output1 <= register1 + register3;
output2 <= register4 + register2;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END arf_wsga_description; | gpl-3.0 | 09e3d9100367ae13be7a1c0affb426ab | 0.654336 | 3.09542 | false | false | false | false |
CyAScott/CIS4930.DatapathSynthesisTool | docs/sample2/input_dp.vhd | 1 | 8,489 | ---------------------------------------------------------------------
--
-- Registers:
-- REG00 (i, t0)
-- REG01 (t1, t5)
-- REG02 (e, t4)
-- REG03 (a, t3)
-- REG04 (b, t2)
-- REG05 (h)
-- REG06 (g)
-- REG07 (f)
-- REG08 (d)
-- REG09 (c)
-- Functional Units:
-- MULT00 (op1, op3, op5)
-- MULT01 (op2, op4)
-- SUB00 (op6, op7)
-- Multiplexers:
-- MX_MULT00 (op1, op3, op5)
-- MX_MULT01 (op2, op4)
-- MX_SUB00 (op6, op7)
-- MX_REG00 (i, t0)
-- MX_REG01 (t1, t5)
-- MX_REG02 (e, t4)
-- MX_REG03 (a, t3)
-- MX_REG04 (b, t2)
-- Expressions:
-- i = f(a, b, c, d, e, f, g, h) = (a * b * c * d) - h - (g * e * f)
--
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity input_dp is
port
(
a, b, c, d, e, f, g, h : IN std_logic_vector(3 downto 0);
i : OUT std_logic_vector(3 downto 0);
ctrl : IN std_logic_vector(0 to 18);
clear, clock : IN std_logic
);
end input_dp;
architecture rtl1 of input_dp is
component c_multiplexer
generic
(
width : integer := 4;
no_of_inputs : integer := 2;
select_size : integer := 1
);
port
(
input : in std_logic_vector(((width * no_of_inputs) - 1) downto 0);
mux_select : in std_logic_vector ((select_size - 1) downto 0);
output : out std_logic_vector ((width - 1) downto 0)
);
end component;
for all : c_multiplexer use entity work.c_multiplexer(behavior);
component c_register
generic
(
width : integer := 4
);
port
(
input : in std_logic_vector((width - 1) downto 0);
WR : in std_logic;
clear : in std_logic;
clock : in std_logic;
output : out std_logic_vector((width - 1) downto 0)
);
end component;
for all : c_register use entity work.c_register(behavior);
component c_multiplier
generic
(
width : integer := 4
);
port
(
input1 : std_logic_vector((width - 1) downto 0);
input2 : std_logic_vector((width - 1) downto 0);
output : out std_logic_vector((width - 1) downto 0)
);
end component;
for all : c_multiplier use entity work.c_multiplier(behavior);
component c_subtractor
generic
(
width : integer := 4
);
port
(
input1, input2 : in std_logic_vector((width - 1) downto 0);
output : out std_logic_vector((width - 1) downto 0)
);
end component;
for all : c_subtractor use entity work.c_subtractor(behavior);
-- Outputs of registers
signal REG00_out, REG01_out, REG02_out, REG03_out, REG04_out, REG05_out, REG06_out, REG07_out, REG08_out, REG09_out : std_logic_vector(3 downto 0);
-- Outputs of FUs
signal MULT00_out, MULT01_out, SUB00_out : std_logic_vector(3 downto 0);
-- Outputs of Interconnect Units
signal MX_MULT00_out, MX_MULT01_out, MX_SUB00_out : std_logic_vector(7 downto 0);
signal MX_REG00_out, MX_REG01_out, MX_REG02_out, MX_REG03_out, MX_REG04_out : std_logic_vector(3 downto 0);
begin
-- Registers
-- REG00 (i, t0)
REG00 : c_register
generic map(4)
port map
(
input(3 downto 0) => MX_REG00_out(3 downto 0), -- Items: i, t0
wr => ctrl(0),
clear => clear,
clock => clock,
output => REG00_out
);
-- REG01 (t1, t5)
REG01 : c_register
generic map(4)
port map
(
input(3 downto 0) => MX_REG01_out(3 downto 0), -- Items: t1, t5
wr => ctrl(1),
clear => clear,
clock => clock,
output => REG01_out
);
-- REG02 (e, t4)
REG02 : c_register
generic map(4)
port map
(
input(3 downto 0) => MX_REG02_out(3 downto 0), -- Items: e, t4
wr => ctrl(2),
clear => clear,
clock => clock,
output => REG02_out
);
-- REG03 (a, t3)
REG03 : c_register
generic map(4)
port map
(
input(3 downto 0) => MX_REG03_out(3 downto 0), -- Items: a, t3
wr => ctrl(3),
clear => clear,
clock => clock,
output => REG03_out
);
-- REG04 (b, t2)
REG04 : c_register
generic map(4)
port map
(
input(3 downto 0) => MX_REG04_out(3 downto 0), -- Items: b, t2
wr => ctrl(4),
clear => clear,
clock => clock,
output => REG04_out
);
-- REG05 (h)
REG05 : c_register
generic map(4)
port map
(
input(3 downto 0) => h(3 downto 0),
wr => ctrl(5),
clear => clear,
clock => clock,
output => REG05_out
);
-- REG06 (g)
REG06 : c_register
generic map(4)
port map
(
input(3 downto 0) => g(3 downto 0),
wr => ctrl(6),
clear => clear,
clock => clock,
output => REG06_out
);
-- REG07 (f)
REG07 : c_register
generic map(4)
port map
(
input(3 downto 0) => f(3 downto 0),
wr => ctrl(7),
clear => clear,
clock => clock,
output => REG07_out
);
-- REG08 (d)
REG08 : c_register
generic map(4)
port map
(
input(3 downto 0) => d(3 downto 0),
wr => ctrl(8),
clear => clear,
clock => clock,
output => REG08_out
);
-- REG09 (c)
REG09 : c_register
generic map(4)
port map
(
input(3 downto 0) => c(3 downto 0),
wr => ctrl(9),
clear => clear,
clock => clock,
output => REG09_out
);
-- Functional Units
-- MULT00 MULT(op1, op3, op5)
MULT00 : c_multiplier
generic map(4)
port map
(
input1(3 downto 0) => MX_MULT00_out(3 downto 0), -- a, e, g
input2(3 downto 0) => MX_MULT00_out(7 downto 4), -- b, f, t2
output(3 downto 0) => MULT00_out(3 downto 0)
);
-- MULT01 MULT(op2, op4)
MULT01 : c_multiplier
generic map(4)
port map
(
input1(3 downto 0) => MX_MULT01_out(3 downto 0), -- c, t0
input2(3 downto 0) => MX_MULT01_out(7 downto 4), -- d, t1
output(3 downto 0) => MULT01_out(3 downto 0)
);
-- SUB00 SUB(op6, op7)
SUB00 : c_subtractor
generic map(4)
port map
(
input1(3 downto 0) => MX_SUB00_out(3 downto 0), -- t3, t5
input2(3 downto 0) => MX_SUB00_out(7 downto 4), -- h, t4
output(3 downto 0) => SUB00_out(3 downto 0)
);
-- Multiplexers
-- MX_MULT00: op1, op3, op5
MX_MULT00 : c_multiplexer
generic map(8, 3, 2)
port map
(
-- Operation op1: MULT(a, b)
input(3 downto 0) => REG03_out(3 downto 0), -- a
input(7 downto 4) => REG04_out(3 downto 0), -- b
-- Operation op3: MULT(e, f)
input(11 downto 8) => REG02_out(3 downto 0), -- e
input(15 downto 12) => REG07_out(3 downto 0), -- f
-- Operation op5: MULT(g, t2)
input(19 downto 16) => REG06_out(3 downto 0), -- g
input(23 downto 20) => REG04_out(3 downto 0), -- t2
mux_select(1 downto 0) => ctrl(10 to 11),
output => MX_MULT00_out
);
-- MX_MULT01: op2, op4
MX_MULT01 : c_multiplexer
generic map(8, 2, 1)
port map
(
-- Operation op2: MULT(c, d)
input(3 downto 0) => REG09_out(3 downto 0), -- c
input(7 downto 4) => REG08_out(3 downto 0), -- d
-- Operation op4: MULT(t0, t1)
input(11 downto 8) => REG00_out(3 downto 0), -- t0
input(15 downto 12) => REG01_out(3 downto 0), -- t1
mux_select(0) => ctrl(12),
output => MX_MULT01_out
);
-- MX_SUB00: op6, op7
MX_SUB00 : c_multiplexer
generic map(8, 2, 1)
port map
(
-- Operation op6: SUB(t3, h)
input(3 downto 0) => REG03_out(3 downto 0), -- t3
input(7 downto 4) => REG05_out(3 downto 0), -- h
-- Operation op7: SUB(t5, t4)
input(11 downto 8) => REG01_out(3 downto 0), -- t5
input(15 downto 12) => REG02_out(3 downto 0), -- t4
mux_select(0) => ctrl(13),
output => MX_SUB00_out
);
-- MX_REG00: i, t0
MX_REG00 : c_multiplexer
generic map(4, 2, 1)
port map
(
input(3 downto 0) => SUB00_out(3 downto 0), -- i
input(7 downto 4) => MULT00_out(3 downto 0), -- t0
mux_select(0) => ctrl(14),
output => MX_REG00_out
);
-- MX_REG01: t1, t5
MX_REG01 : c_multiplexer
generic map(4, 2, 1)
port map
(
input(3 downto 0) => MULT01_out(3 downto 0), -- t1
input(7 downto 4) => SUB00_out(3 downto 0), -- t5
mux_select(0) => ctrl(15),
output => MX_REG01_out
);
-- MX_REG02: e, t4
MX_REG02 : c_multiplexer
generic map(4, 2, 1)
port map
(
input(3 downto 0) => e(3 downto 0), -- e
input(7 downto 4) => MULT00_out(3 downto 0), -- t4
mux_select(0) => ctrl(16),
output => MX_REG02_out
);
-- MX_REG03: a, t3
MX_REG03 : c_multiplexer
generic map(4, 2, 1)
port map
(
input(3 downto 0) => a(3 downto 0), -- a
input(7 downto 4) => MULT01_out(3 downto 0), -- t3
mux_select(0) => ctrl(17),
output => MX_REG03_out
);
-- MX_REG04: b, t2
MX_REG04 : c_multiplexer
generic map(4, 2, 1)
port map
(
input(3 downto 0) => b(3 downto 0), -- b
input(7 downto 4) => MULT00_out(3 downto 0), -- t2
mux_select(0) => ctrl(18),
output => MX_REG04_out
);
-- Primary outputs
i(3 downto 0) <= REG00_out(3 downto 0);
end rtl1;
| mit | ead678876ee47393461832397baaf138 | 0.57439 | 2.477817 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/gen_srlfifo.vhd | 1 | 14,303 | `protect begin_protected
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`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8848)
`protect data_block
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| apache-2.0 | d8a25bd69c0d42ed0b4f38a5e8874156 | 0.930924 | 1.873592 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/IP/ov7670_marker_tracker_ip/ov7670_marker_tracker_ip_1.0/src/clk_wiz_0/clk_wiz_0_funcsim.vhdl | 1 | 6,490 | -- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
-- Date : Mon Jan 26 10:14:21 2015
-- Host : xilinxvivadotools running 64-bit unknown
-- Command : write_vhdl -force -mode funcsim
-- /home/ece532/testing/ov7670/nexys4ddr_ov7670/nexys4ddr_ov7670.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_funcsim.vhdl
-- Design : clk_wiz_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a100tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity clk_wiz_0clk_wiz_0_clk_wiz is
port (
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC;
clk_out2 : out STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of clk_wiz_0clk_wiz_0_clk_wiz : entity is "clk_wiz_0_clk_wiz";
end clk_wiz_0clk_wiz_0_clk_wiz;
architecture STRUCTURE of clk_wiz_0clk_wiz_0_clk_wiz is
signal clk_in1_clk_wiz_0 : STD_LOGIC;
signal clk_out1_clk_wiz_0 : STD_LOGIC;
signal clk_out2_clk_wiz_0 : STD_LOGIC;
signal clkfbout_buf_clk_wiz_0 : STD_LOGIC;
signal clkfbout_clk_wiz_0 : STD_LOGIC;
signal NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_plle2_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_plle2_adv_inst_LOCKED_UNCONNECTED : STD_LOGIC;
signal NLW_plle2_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkout2_buf : label is "PRIMITIVE";
attribute BOX_TYPE of plle2_adv_inst : label is "PRIMITIVE";
begin
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_clk_wiz_0,
O => clkfbout_buf_clk_wiz_0
);
clkin1_ibufg: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clk_in1,
O => clk_in1_clk_wiz_0
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_out1_clk_wiz_0,
O => clk_out1
);
clkout2_buf: unisim.vcomponents.BUFG
port map (
I => clk_out2_clk_wiz_0,
O => clk_out2
);
plle2_adv_inst: unisim.vcomponents.PLLE2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT => 8,
CLKFBOUT_PHASE => 0.000000,
CLKIN1_PERIOD => 10.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE => 16,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT1_DIVIDE => 32,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 1,
IS_CLKINSEL_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.010000,
STARTUP_WAIT => "FALSE"
)
port map (
CLKFBIN => clkfbout_buf_clk_wiz_0,
CLKFBOUT => clkfbout_clk_wiz_0,
CLKIN1 => clk_in1_clk_wiz_0,
CLKIN2 => '0',
CLKINSEL => '1',
CLKOUT0 => clk_out1_clk_wiz_0,
CLKOUT1 => clk_out2_clk_wiz_0,
CLKOUT2 => NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT3 => NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT4 => NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED,
DADDR(6) => '0',
DADDR(5) => '0',
DADDR(4) => '0',
DADDR(3) => '0',
DADDR(2) => '0',
DADDR(1) => '0',
DADDR(0) => '0',
DCLK => '0',
DEN => '0',
DI(15) => '0',
DI(14) => '0',
DI(13) => '0',
DI(12) => '0',
DI(11) => '0',
DI(10) => '0',
DI(9) => '0',
DI(8) => '0',
DI(7) => '0',
DI(6) => '0',
DI(5) => '0',
DI(4) => '0',
DI(3) => '0',
DI(2) => '0',
DI(1) => '0',
DI(0) => '0',
DO(15 downto 0) => NLW_plle2_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_plle2_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => NLW_plle2_adv_inst_LOCKED_UNCONNECTED,
PWRDWN => '0',
RST => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity clk_wiz_0 is
port (
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC;
clk_out2 : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of clk_wiz_0 : entity is true;
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of clk_wiz_0 : entity is "clk_wiz_0,clk_wiz_v5_1,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=PLL,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
end clk_wiz_0;
architecture STRUCTURE of clk_wiz_0 is
begin
inst: entity work.clk_wiz_0clk_wiz_0_clk_wiz
port map (
clk_in1 => clk_in1,
clk_out1 => clk_out1,
clk_out2 => clk_out2
);
end STRUCTURE;
| apache-2.0 | 8717ba9f6a6aa3b762284a5a2d36e72b | 0.613405 | 3.135266 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/10-EPIC/asap-alap-random/epic_random.vhd | 1 | 4,541 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-26.16:17:17)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY epic_random_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6: IN unsigned(0 TO 3);
output1, output2, output3, output4, output5, output6, output7, output8, output9: OUT unsigned(0 TO 4));
END epic_random_entity;
ARCHITECTURE epic_random_description OF epic_random_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register9: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register10: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register11: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register12: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register13: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
register2 := input2 * 2;
WHEN "00000010" =>
register2 := register2 + 4;
register3 := input3 + 5;
register4 := input4 - 6;
register1 := register1 * 8;
WHEN "00000011" =>
register5 := ((NOT register2) + 1) XOR register2;
register4 := register4 * 12;
register6 := input5 - 13;
WHEN "00000100" =>
register7 := register6 + register3;
register8 := input6 srl 14;
register9 := register3 * 16;
register3 := register6 - register3;
register5 := register5 + 18;
register10 := register6 + 20;
WHEN "00000101" =>
output1 <= register2(0 TO 1) & register5(0 TO 2);
register2 := register4 + 23;
register3 := register3 * 25;
register4 := register8 srl 27;
WHEN "00000110" =>
register5 := register8 sll to_integer(register4);
register11 := ((NOT register2) + 1) XOR register2;
WHEN "00000111" =>
register11 := register8 - register11;
register12 := register6 - 31;
WHEN "00001000" =>
output2 <= register2(0 TO 1) & register11(0 TO 2);
register2 := register10 * 34;
register3 := register3 + 36;
WHEN "00001001" =>
register10 := ((NOT register3) + 1) XOR register3;
register9 := register9 + 40;
register1 := register1 + 42;
WHEN "00001010" =>
register11 := ((NOT register9) + 1) XOR register9;
register10 := register8 + register4 + register10;
register12 := register12 * 46;
register7 := register7 * 48;
WHEN "00001011" =>
register13 := ((NOT register1) + 1) XOR register1;
register7 := register7 + 52;
register2 := register2 + 54;
WHEN "00001100" =>
register13 := register8 - register13;
output3 <= register3(0 TO 1) & register10(0 TO 2);
register3 := ((NOT register2) + 1) XOR register2;
WHEN "00001101" =>
register10 := ((NOT register7) + 1) XOR register7;
register3 := register8 + register4 + register3;
register12 := register12 + 61;
register5 := register11 - register5;
WHEN "00001110" =>
output4 <= register9(0 TO 1) & register5(0 TO 2);
register5 := ((NOT register12) + 1) XOR register12;
register9 := register8 + register4 + register10;
WHEN "00001111" =>
output5 <= register2(0 TO 1) & register3(0 TO 2);
register2 := register4 + register5;
WHEN "00010000" =>
output6 <= register7(0 TO 1) & register9(0 TO 2);
WHEN "00010001" =>
output7 <= register1(0 TO 1) & register13(0 TO 2);
WHEN "00010010" =>
output8 <= register12(0 TO 1) & register2(0 TO 2);
register1 := register6 * 70;
WHEN "00010011" =>
register1 := register1 + 72;
WHEN "00010100" =>
register2 := ((NOT register1) + 1) XOR register1;
WHEN "00010101" =>
register2 := register8 - register2;
WHEN "00010110" =>
output9 <= register1(0 TO 1) & register2(0 TO 2);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END epic_random_description; | gpl-3.0 | 400286e534ab87a603ff063fb56f99c9 | 0.650297 | 3.155664 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/data_flow_logic_gti.vhd | 1 | 18,409 | `protect begin_protected
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`protect end_protected
| apache-2.0 | f3c4242c8576c6a1821958f5ed98a9ce | 0.938726 | 1.851453 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/counter.vhd | 15 | 9,030 | -------------------------------------------------------------------------------
-- Counter - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter.vhd
--
-- Description: Implements a parameterizable N-bit counter
-- Up/Down Counter
-- Count Enable
-- Parallel Load
-- Synchronous Reset
-- 1 - LUT per bit plus 3 LUTS for extra features
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- counter.vhd
-- counter_bit.vhd
--
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- KC 2002-01-23 First Version
-- LCW 2004-10-08 Updated for NCSim
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library Unisim;
use Unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.counter_bit;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity Counter is
generic(
C_NUM_BITS : Integer := 9
);
port (
Clk : in std_logic;
Rst : in std_logic;
Load_In : in std_logic_vector(C_NUM_BITS - 1 downto 0);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Count_Out : out std_logic_vector(C_NUM_BITS - 1 downto 0);
Carry_Out : out std_logic
);
end entity Counter;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of Counter is
signal alu_cy : std_logic_vector(C_NUM_BITS downto 0);
signal iCount_Out : std_logic_vector(C_NUM_BITS - 1 downto 0);
signal count_clock_en : std_logic;
signal carry_active_high : std_logic;
begin -- VHDL_RTL
-----------------------------------------------------------------------------
-- Generate the Counter bits
-----------------------------------------------------------------------------
alu_cy(0) <= (Count_Down and Count_Load) or
(not Count_Down and not Count_load);
count_clock_en <= Count_Enable or Count_Load;
I_ADDSUB_GEN : for I in 0 to (C_NUM_BITS - 1) generate
begin
Counter_Bit_I : entity proc_common_v4_0.counter_bit
port map (
Clk => Clk, -- [in]
Rst => Rst, -- [in]
Count_In => iCount_Out(i), -- [in]
Load_In => Load_In(i), -- [in]
Count_Load => Count_Load, -- [in]
Count_Down => Count_Down, -- [in]
Carry_In => alu_cy(I), -- [in]
Clock_Enable => count_clock_en, -- [in]
Result => iCount_Out(I), -- [out]
Carry_Out => alu_cy(I+1) -- [out]
);
end generate I_ADDSUB_GEN;
carry_active_high <= alu_cy(C_NUM_BITS) xor Count_Down;
CARRY_OUT_I: FDRE
port map (
Q => Carry_Out, -- [out]
C => Clk, -- [in]
CE => count_clock_en, -- [in]
D => carry_active_high, -- [in]
R => Rst -- [in]
);
Count_Out <= iCount_Out;
end architecture imp;
| apache-2.0 | fe6535933f197d5967a10203e4b98eaf | 0.398782 | 5.286885 | false | false | false | false |
CyAScott/CIS4930.DatapathSynthesisTool | src/components/test_c_bus.vhd | 1 | 1,262 | use Std.Textio.all;
library IEEE;
use ieee.std_logic_1164.ALL;
entity test_c_bus is end;
architecture test_c_bus of test_c_bus is
component c_bus
generic (width : integer;
no_of_inputs : integer);
port(
input : in Std_logic_vector (((width*no_of_inputs) - 1) downto 0);
BUS_SELECT : in Std_logic_vector ((no_of_inputs - 1) downto 0);
output : out Std_logic_vector ((width - 1) downto 0));
end component;
for all : c_bus use entity work.c_bus(behavior);
signal INPUT : std_logic_vector(15 downto 0);
signal OUTPUT : std_logic_vector(3 downto 0);
signal BUS_SELECT : std_logic_vector(3 downto 0);
begin
bus1 : c_bus generic map(4, 4)
port map( input, bus_select, output);
test_process : process
begin
bus_select <= "0001";
input <= "0011001000010000";
wait for 10 ns;
bus_select <= "0010";
wait for 10 ns;
bus_select <= "0100";
wait for 10 ns;
bus_select <= "1000";
wait for 10 ns;
bus_select <= "0000";
wait for 10 ns;
wait;
end process test_process ;
end test_c_bus;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
| mit | a8cf90730e5286965bf3d805a5ba565b | 0.538035 | 3.51532 | false | true | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/or_bits.vhd | 15 | 10,956 | -------------------------------------------------------------------------------
-- $Id: or_bits.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- Or_bits
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_bits.vhd
--
-- Description: This file is used to OR together consecutive bits within
-- sections of a bus.
--
-------------------------------------------------------------------------------
-- Structure: Common use module
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 04/06/01 -- First version
--
-- ALS 05/18/01
-- ^^^^^^
-- Added use of carry chain muxes if number of bits is > 4
-- ~~~~~~
-- BLT 05/23/01
-- ^^^^^^
-- Removed pad_4 function, replaced with arithmetic expression
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- Unisim library contains Xilinx primitives
library Unisim;
use Unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_BITS -- number of bits to OR in bus section
-- C_START_BIT -- starting bit location of bits to OR
-- C_BUS_SIZE -- total size of the bus
--
-- Definition of Ports:
-- input In_Bus -- bus containing bits to be ORd
-- input Sig -- another signal not in the bus to be ORd with the
-- -- bus section
-- output Or_out -- OR result
--
-------------------------------------------------------------------------------
entity or_bits is
generic (
C_NUM_BITS : integer := 8;
C_START_BIT : integer := 0;
C_BUS_SIZE : integer := 8);
port (
In_bus : in std_logic_vector(0 to C_BUS_SIZE-1);
Sig : in std_logic;
Or_out : out std_logic
);
end or_bits;
architecture implementation of or_bits is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Pad the number of bits to OR to the next multiple of 4
constant NUM_BITS_PAD : integer := ((C_NUM_BITS-1)/4+1)*4;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
-- define output of OR chain
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- Carry Chain muxes are used to implement OR of 4 bits or more
component MUXCY
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component;
begin
-- If the number of bits to OR is 4 or less (including Sig), a simple LUT can be used
LESSTHAN4_GEN: if C_NUM_BITS < 4 generate
-- define output of OR chain
signal or_tmp : std_logic_vector(0 to C_NUM_BITS-1) := (others => '0');
begin
BIT_LOOP: for i in 0 to C_NUM_BITS-1 generate
FIRST: if i = 0 generate
or_tmp(i) <= Sig or In_bus(C_START_BIT);
end generate FIRST;
REST: if i /= 0 generate
or_tmp(i) <= or_tmp(i-1) or In_bus(C_START_BIT + i);
end generate REST;
end generate BIT_LOOP;
Or_out <= or_tmp(C_NUM_BITS-1);
end generate LESSTHAN4_GEN;
-- If the number of bits to OR is 4 or more (including Sig), then use LUTs and
-- carry chain. Pad the number of bits to the nearest multiple of 4
MORETHAN4_GEN: if C_NUM_BITS >= 4 generate
-- define output of LUTs
signal lut_out : std_logic_vector(0 to NUM_BITS_PAD/4-1) := (others => '0');
-- define padded input bus
signal in_bus_pad : std_logic_vector(0 to NUM_BITS_PAD-1) := (others => '0');
-- define output of OR chain
signal or_tmp : std_logic_vector(0 to NUM_BITS_PAD/4-1) := (others => '0');
begin
-- pad input bus
in_bus_pad(0 to C_NUM_BITS-1) <= In_bus(C_START_BIT to C_START_BIT+C_NUM_BITS-1);
OR_GENERATE: for i in 0 to NUM_BITS_PAD/4-1 generate
lut_out(i) <= not( in_bus_pad(i*4) or
in_bus_pad(i*4+1) or
in_bus_pad(i*4+2) or
in_bus_pad(i*4+3) );
FIRST: if i = 0 generate
FIRSTMUX_I: MUXCY
port map (
O => or_tmp(i), --[out]
--CI => '0' , --[in]
CI => Sig , --[in]
DI => '1' , --[in]
S => lut_out(i) --[in]
);
end generate FIRST;
REST: if i /= 0 generate
RESTMUX_I: MUXCY
port map (
O => or_tmp(i), --[out]
CI => or_tmp(i-1), --[in]
DI => '1' , --[in]
S => lut_out(i) --[in]
);
end generate REST;
end generate OR_GENERATE;
Or_out <= or_tmp(NUM_BITS_PAD/4-1);
end generate MORETHAN4_GEN;
end implementation;
| apache-2.0 | 4cfddfe05bb317955fcb5784c012c6a6 | 0.404162 | 4.991344 | false | false | false | false |
BBN-Q/APS2-Comms | src/tcp_bridge_pkg.vhd | 1 | 5,035 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
package tcp_bridge_pkg is
function byte_swap(word_in : std_logic_vector) return std_logic_vector;
component axis_srl_fifo
generic (
DATA_WIDTH : natural := 8;
DEPTH : natural := 16
);
port (
clk : in std_logic;
rst : in std_logic;
input_axis_tdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
input_axis_tvalid : in std_logic;
input_axis_tready : out std_logic;
input_axis_tlast : in std_logic;
input_axis_tuser : in std_logic;
output_axis_tdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
output_axis_tvalid : out std_logic;
output_axis_tready : in std_logic;
output_axis_tlast : out std_logic;
output_axis_tuser : out std_logic;
count : out std_logic_vector(integer(ceil(log2(real(DEPTH+1))))-1 downto 0)
);
end component;
component axis_demux_2
generic (
DATA_WIDTH : natural := 8
);
port (
clk : in std_logic;
rst : in std_logic;
input_axis_tdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
input_axis_tvalid : in std_logic;
input_axis_tready : out std_logic;
input_axis_tlast : in std_logic;
input_axis_tuser : in std_logic;
output_0_axis_tdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
output_0_axis_tvalid : out std_logic;
output_0_axis_tready : in std_logic;
output_0_axis_tlast : out std_logic;
output_0_axis_tuser : out std_logic;
output_1_axis_tdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
output_1_axis_tvalid : out std_logic;
output_1_axis_tready : in std_logic;
output_1_axis_tlast : out std_logic;
output_1_axis_tuser : out std_logic;
enable : in std_logic;
control : in std_logic_vector(0 downto 0)
);
end component;
component axis_adapter
generic (
INPUT_DATA_WIDTH : natural := 8;
INPUT_KEEP_WIDTH : natural := 1;
OUTPUT_DATA_WIDTH : natural := 8;
OUTPUT_KEEP_WIDTH : natural := 1
);
port (
clk : in std_logic;
rst : in std_logic;
--AXIS input
input_axis_tdata : in std_logic_vector(INPUT_DATA_WIDTH-1 downto 0);
input_axis_tkeep : in std_logic_vector(INPUT_KEEP_WIDTH-1 downto 0);
input_axis_tvalid : in std_logic;
input_axis_tready : out std_logic;
input_axis_tlast : in std_logic;
input_axis_tuser : in std_logic;
--AXIS input
output_axis_tdata : out std_logic_vector(OUTPUT_DATA_WIDTH-1 downto 0);
output_axis_tkeep : out std_logic_vector(OUTPUT_KEEP_WIDTH-1 downto 0);
output_axis_tvalid : out std_logic;
output_axis_tready : in std_logic;
output_axis_tlast : out std_logic;
output_axis_tuser : out std_logic
);
end component;
component axis_arb_mux_3
generic (
DATA_WIDTH : natural := 8;
ARB_TYPE : string := "PRIORITY"; --"PRIORITY" or "ROUND_ROBIN"
LSB_PRIORITY : string := "HIGH" --"LOW" or "HIGH"
);
port (
clk : in std_logic;
rst : in std_logic;
input_0_axis_tdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
input_0_axis_tvalid : in std_logic;
input_0_axis_tready : out std_logic;
input_0_axis_tlast : in std_logic;
input_0_axis_tuser : in std_logic;
input_1_axis_tdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
input_1_axis_tvalid : in std_logic;
input_1_axis_tready : out std_logic;
input_1_axis_tlast : in std_logic;
input_1_axis_tuser : in std_logic;
input_2_axis_tdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
input_2_axis_tvalid : in std_logic;
input_2_axis_tready : out std_logic;
input_2_axis_tlast : in std_logic;
input_2_axis_tuser : in std_logic;
output_axis_tdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
output_axis_tvalid : out std_logic;
output_axis_tready : in std_logic;
output_axis_tlast : out std_logic;
output_axis_tuser : out std_logic
);
end component;
component axis_async_fifo
generic (
ADDR_WIDTH : natural := 12;
DATA_WIDTH : natural := 8
);
port (
async_rst : in std_logic;
input_clk : in std_logic;
input_axis_tdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
input_axis_tvalid : in std_logic;
input_axis_tready : out std_logic;
input_axis_tlast : in std_logic;
input_axis_tuser : in std_logic;
output_clk : in std_logic;
output_axis_tdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
output_axis_tvalid : out std_logic;
output_axis_tready : in std_logic;
output_axis_tlast : out std_logic;
output_axis_tuser : out std_logic
);
end component;
end tcp_bridge_pkg;
package body tcp_bridge_pkg is
function byte_swap(word_in : std_logic_vector) return std_logic_vector is
variable word_out : std_logic_vector(word_in'range);
variable num_bytes : natural := word_in'length/8;
begin
for ct in 0 to num_bytes-1 loop
word_out(8*(ct+1)-1 downto 8*ct) := word_in(8*(num_bytes-ct)-1 downto 8*(num_bytes-ct-1));
end loop;
return word_out;
end function byte_swap;
end package body;
| mpl-2.0 | 1f57e15015bebdded2c3a77eb1f48338 | 0.656405 | 2.79102 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/axi_uartlite_v2_0/6e58ba99/hdl/src/vhdl/baudrate.vhd | 1 | 8,909 | -------------------------------------------------------------------------------
-- baudrate - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] Xilinx, Inc. All rights reserved.*
-- -- ** *
-- -- ** This file contains confidential and proprietary information *
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
-- -- ** international copyright and other intellectual property *
-- -- ** laws. *
-- -- ** *
-- -- ** DISCLAIMER *
-- -- ** This disclaimer is not a license and does not grant any *
-- -- ** rights to the materials distributed herewith. Except as *
-- -- ** otherwise provided in a valid license issued to you by *
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- -- ** including negligence, or under any other theory of *
-- -- ** liability) for any loss or damage of any kind or nature *
-- -- ** related to, arising under or in connection with these *
-- -- ** materials, including for any direct, or any indirect, *
-- -- ** special, incidental, or consequential loss or damage *
-- -- ** (including loss of data, profits, goodwill, or any type of *
-- -- ** loss or damage suffered as a result of any action brought *
-- -- ** by a third party) even if such damage or loss was *
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
-- -- ** possibility of the same. *
-- -- ** *
-- -- ** CRITICAL APPLICATIONS *
-- -- ** Xilinx products are not designed or intended to be fail- *
-- -- ** safe, or for use in any application requiring fail-safe *
-- -- ** performance, such as life-support or safety devices or *
-- -- ** systems, Class III medical devices, nuclear facilities, *
-- -- ** applications related to the deployment of airbags, or any *
-- -- ** other applications that could lead to death, personal *
-- -- ** injury, or severe property or environmental damage *
-- -- ** (individually and collectively, "Critical *
-- -- ** Applications"). Customer assumes the sole risk and *
-- -- ** liability of any use of Xilinx products in Critical *
-- -- ** Applications, subject only to applicable laws and *
-- -- ** regulations governing limitations on product liability. *
-- -- ** *
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- -- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: baudrate.vhd
-- Version: v2.0
-- Description: Baud rate enable logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_uartlite.
--
-- axi_uartlite.vhd
-- --axi_lite_ipif.vhd
-- --uartlite_core.vhd
-- --uartlite_tx.vhd
-- --uartlite_rx.vhd
-- --baudrate.vhd
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 07/22/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
-- ~~~~~~
-- 20/09/20 SK
-- - Updated the version as AXI Lite IPIF version is updated.
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- UART Lite generics
-- C_RATIO -- The ratio between clk and the asked baudrate
-- multiplied with 16
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
-- System Signals
-- Clk -- Clock signal
-- Reset -- Reset signal
-- Internal UART interface signals
-- EN_16x_Baud -- Enable signal which is 16x times baud rate
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity baudrate is
generic
(
C_RATIO : integer := 48 -- The ratio between clk and the asked
-- baudrate multiplied with 16
);
port
(
Clk : in std_logic;
Reset : in std_logic;
EN_16x_Baud : out std_logic
);
end entity baudrate;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture RTL of baudrate is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
---------------------------------------------------------------------------
-- Signal Declarations
---------------------------------------------------------------------------
signal count : natural range 0 to C_RATIO-1;
begin -- architecture VHDL_RTL
---------------------------------------------------------------------------
-- COUNTER_PROCESS : Down counter for generating EN_16x_Baud signal
---------------------------------------------------------------------------
COUNTER_PROCESS : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then
count <= 0;
EN_16x_Baud <= '0';
else
if (count = 0) then
count <= C_RATIO-1;
EN_16x_Baud <= '1';
else
count <= count - 1;
EN_16x_Baud <= '0';
end if;
end if;
end if;
end process COUNTER_PROCESS;
end architecture RTL;
| apache-2.0 | d85fb5a1a71b59a1e3d6806b5d03a6ab | 0.37883 | 5.923537 | false | false | false | false |
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| apache-2.0 | 7f5b3de31bc6ec45adc789fb0cf51909 | 0.947931 | 1.821241 | false | false | false | false |
BBN-Q/APS2-Comms | test/cpld_bridge_tb.vhd | 1 | 5,470 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cpld_bridge_tb is
end;
architecture bench of cpld_bridge_tb is
signal cfg_act : std_logic := '0';
signal cfg_clk : std_logic := '0';
signal cfg_err : std_logic := '0';
signal cfg_rdy : std_logic := '0';
signal cfgd : std_logic_vector ( 15 downto 0 ) := (others => '0');
signal clk : std_logic := '0';
signal rx_tdata : std_logic_vector ( 31 downto 0 ) := (others => '0');
signal rx_tlast : std_logic := '0';
signal rx_tready : std_logic := '0';
signal rx_tvalid : std_logic := '0';
signal tx_tdata : std_logic_vector ( 31 downto 0 ) := (others => '0');
signal tx_tlast : std_logic := '0';
signal tx_tready : std_logic := '1';
signal tx_tvalid : std_logic := '0';
signal fpga_cmdl : std_logic := '0';
signal fpga_rdyl : std_logic := '0';
signal rst : std_logic := '0';
signal stat_oel : std_logic := '0';
constant clock_period : time := 10 ns;
constant cfg_clock_period : time := 10 ns;
signal stop_the_clocks : boolean := false;
type TestBenchState_t is (RESET, STATUS_REQUEST, STATUS_REQUEST2, FINISHED);
signal testBench_state : TestBenchState_t;
type APSCommand_t is record
ack : std_logic;
seq : std_logic;
sel : std_logic;
rw : std_logic;
cmd : std_logic_vector(3 downto 0);
mode : std_logic_vector(7 downto 0);
cnt : std_logic_vector(15 downto 0);
end record;
begin
uut : entity work.cpld_bridge
port map (
clk => clk,
rst => rst,
rx_tdata => rx_tdata,
rx_tlast => rx_tlast,
rx_tready => rx_tready,
rx_tvalid => rx_tvalid,
tx_tdata => tx_tdata,
tx_tlast => tx_tlast,
tx_tready => tx_tready,
tx_tvalid => tx_tvalid,
cfg_clk => cfg_clk,
cfg_act => cfg_act,
cfg_err => cfg_err,
cfg_rdy => cfg_rdy,
cfgd => cfgd,
fpga_cmdl => fpga_cmdl,
fpga_rdyl => fpga_rdyl,
stat_oel => stat_oel
);
clk <= not clk after clock_period / 2 when not stop_the_clocks;
cfg_clk <= not cfg_clk after cfg_clock_period / 2 when not stop_the_clocks;
stimulus : process
variable command_word : APSCommand_t := (ack => '0', seq => '0', sel => '0', rw => '0', cmd => (others => '0'), mode => (others => '0'), cnt => x"0000");
begin
wait until rising_edge(clk);
testBench_state <= RESET;
rst <= '1';
wait for 100ns;
rst <= '0';
wait for 100ns;
--Clock in a status request
wait until rising_edge(clk);
testBench_state <= STATUS_REQUEST;
command_word.rw := '1';
command_word.cmd := x"7";
command_word.sel := '1';
rx_tdata <= command_word.ack & command_word.seq & command_word.sel & command_word.rw & command_word.cmd & x"000010";
rx_tvalid <= '1';
rx_tlast <= '1';
wait until rising_edge(clk) and rx_tready = '1';
rx_tvalid <= '0';
rx_tlast <= '0';
wait until tx_tlast = '1';
--Clock in a 2nd status request
wait until rising_edge(clk);
testBench_state <= STATUS_REQUEST2;
rx_tdata <= command_word.ack & command_word.seq & command_word.sel & command_word.rw & command_word.cmd & x"000010";
rx_tvalid <= '1';
rx_tlast <= '1';
wait until rising_edge(clk) and rx_tready = '1';
rx_tvalid <= '0';
rx_tlast <= '0';
wait until tx_tlast = '1';
wait for 10ns;
stop_the_clocks <= true;
end process;
checking : process
begin
--First thing back in the status registers
--command word
wait until rising_edge(clk) and tx_tvalid = '1';
assert tx_tdata = x"97000010" report "Incorrect STATUS_REQUEST command word response";
--host firmware version
wait until rising_edge(clk) and tx_tvalid = '1';
assert tx_tdata = x"00000a01" report "Incorrect STATUS_REQUEST host firmware version";
--user firmware version
wait until rising_edge(clk) and tx_tvalid = '1';
assert tx_tdata = x"badda555" report "Incorrect STATUS_REQUEST user firmware version";
--config source
wait until rising_edge(clk) and tx_tvalid = '1';
assert tx_tdata = x"bbbbbbbb" report "Incorrect STATUS_REQUEST config source";
--user status
wait until rising_edge(clk) and tx_tvalid = '1';
assert tx_tdata = x"0ddba111" report "Incorrect STATUS_REQUEST user status";
--dac0 status, dac1 status, pll status, temperature
for ct in 1 to 4 loop
wait until rising_edge(clk) and tx_tvalid = '1';
assert tx_tdata = x"00000000" report "Incorrect STATUS_REQUEST dac0/dac1/pll status";
end loop;
--send pkt count
wait until rising_edge(clk) and tx_tvalid = '1';
assert tx_tdata = x"00000000" report "Incorrect STATUS_REQUEST send packet count";
--receive pkt count
wait until rising_edge(clk) and tx_tvalid = '1';
assert tx_tdata = x"00000001" report "Incorrect STATUS_REQUEST receive packet count";
--skip pkt count, dup pkt count, fcs error pkt count, overrun count
for ct in 1 to 4 loop
wait until rising_edge(clk) and tx_tvalid = '1';
assert tx_tdata = x"00000000" report "Incorrect STATUS_REQUEST skip/dup/fcs errors/overrun pkt count";
end loop;
--uptime
wait until rising_edge(clk) and tx_tvalid = '1';
assert tx_tdata = x"00000000" report "Incorrect STATUS_REQUEST uptime seconds";
wait until rising_edge(clk) and tx_tvalid = '1';
assert tx_tdata = x"000002b8" report "Incorrect STATUS_REQUEST updtime nanoseconds";
assert tx_tlast = '1' report "tlast did not go high when expected";
end process;
end;
| mpl-2.0 | 8f6dd155a0c135c1adb45caac10eed31 | 0.633455 | 3.261777 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/2-MESA-HB/asap-alap-random/mesahb_alap.vhd | 1 | 1,934 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.10:15:30)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mesahb_alap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5: IN unsigned(0 TO 3);
output1, output2: OUT unsigned(0 TO 4));
END mesahb_alap_entity;
ARCHITECTURE mesahb_alap_description OF mesahb_alap_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
WHEN "00000010" =>
register1 := register1 + 3;
register2 := input2 * 4;
WHEN "00000011" =>
register1 := register1 * 6;
register3 := input3 * 7;
register2 := register2 + 9;
WHEN "00000100" =>
register1 := register1 + 11;
register3 := register3 + 13;
register2 := ((NOT register2) + 1) XOR register2;
register4 := input4 * 16;
WHEN "00000101" =>
register1 := ((NOT register1) + 1) XOR register1;
register3 := register3 * 20;
register2 := register4 * register2;
WHEN "00000110" =>
register1 := register1 * 22;
register3 := register3 + 24;
WHEN "00000111" =>
register1 := register1 + register2;
output1 <= input5 + 25;
WHEN "00001000" =>
output2 <= register1(0 TO 1) & register3(0 TO 2);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mesahb_alap_description; | gpl-3.0 | fe87cc9bed7fe1eaf1ce94e912e07f1b | 0.657187 | 3.031348 | false | false | false | false |
CyAScott/CIS4930.DatapathSynthesisTool | docs/sample/input_con.vhd | 1 | 3,876 | ---------------------------------------------------------------------
-- --
-- This file is generated automatically by AUDI (AUtomatic --
-- Design Instantiation) system, a behavioral synthesis system, --
-- developed at the University of South Florida. This project --
-- is supported by the National Science Foundation (NSF) under --
-- the project number XYZ. If you have any questions, contact --
-- Dr. Srinivas Katkoori ([email protected]), Computer --
-- Science & Engineering Department, University of South Florida, --
-- Tampa, FL 33647. --
-- --
---------------------------------------------------------------------
--
-- Date & Time:
-- User login id/name:
--
-- File name:
-- Type:
--
-- Input aif file name:
--
-- CDFG statistics:
-- * Number of PI's:
-- * Number of PO's:
-- * Number of internal edges:
-- * Number of Operations:
-- * Conditionals:
-- * Loops:
-- * Types of Operations:
--
-- Design Flow/Algorithm Information:
-- * Scheduling Algorithm:
-- * Allocation:
-- * Binding:
-- Interconnect style: Multiplexor-Based or Bus-based
--
-- Design Information:
--
-- Datapath:
-- * Registers:
-- * Functional units:
-- * Number of Multiplexors:
-- * Number of Buses:
--
-- * Operator Binding Information:
--
-- * Register Optimization Information:
--
-- * Register Binding Information:
--
--
-- Controller:
-- * Type: Moore/Mealy
-- * Number of states:
-- * Number of control bits:
--
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library Beh_Lib;
use Beh_Lib.all;
entity input_controller is
port (clock, reset : IN Std_logic;
s_tart : IN Std_logic;
finish : OUT Std_logic;
control_out : Out Std_logic_vector(0 to 14));
end input_controller;
architecture Moore of input_controller is
type State_enum is ( S0, S1, S2, S3, S4, S5, S6 );
signal Current_state : State_enum;
signal Next_state : State_enum;
signal Internal_finish : Std_logic;
signal Control_bus : Std_logic_vector(0 to 14);
begin
process(clock, Reset)
begin
if (Reset = '1') then
Current_state <= S0;
elsif (clock = '1' and clock'event) then
Current_state <= Next_state;
end if;
end process;
process
begin
wait until clock = '0';
Control_out <= Control_bus;
finish <= Internal_finish;
end process;
process(Current_state, s_tart)
begin
case Current_state is
when S0 =>
-- Timestep = 0
Internal_finish <= '0';
Control_bus <= "000000000000000";
case s_tart is
when '1' => Next_state <= S1;
when '0' => Next_state <= S0;
when others => null;
end case;
when S1 =>
-- Timestep = 1
Internal_finish <= '0';
Control_bus <= "101111110110000";
Next_state <= S2;
when S2 =>
-- Timestep = 2
Internal_finish <= '0';
Control_bus <= "010000001001000";
Next_state <= S3;
when S3 =>
-- Timestep = 3
Internal_finish <= '0';
Control_bus <= "010000001000110";
Next_state <= S4;
when S4 =>
-- Timestep = 4
Internal_finish <= '0';
Control_bus <= "010000001000001";
Next_state <= S5;
when S5 =>
-- Timestep = 5
Internal_finish <= '0';
Control_bus <= "100000000000000";
Next_state <= S6;
when S6 =>
-- Timestep = 6
Internal_finish <= '1';
Control_bus <= "000000000000000";
Next_state <= S0;
end case;
end process;
end Moore;
| mit | 4bd3ed4d9baf884c9f9da9d8018f1ab2 | 0.513158 | 3.636023 | false | false | false | false |
witoldo7/puc-2 | PUC/PUC_567/PUC_2/udcounter.vhd | 1 | 932 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity udcounter is
generic ( WIDTH : integer := 8);
port (CLK, UP, DOWN, RESET : in std_logic;
Q : out unsigned(WIDTH-1 downto 0) );
end entity udcounter;
architecture udcounter_a of udcounter is
signal cnt : unsigned(WIDTH-1 downto 0);
signal up1, dw1 : std_logic;
begin
process(RESET, CLK)
begin
if RESET = '1' then
cnt <= (others => '0');
elsif rising_edge(CLK) then
if (UP='1' and up1='0' and DOWN='0') then
cnt <= cnt + 1;
elsif (DOWN='1' and dw1='0' and UP='0') then
cnt <= cnt - 1;
--else leave cnt unchanged
end if;
up1 <= UP;
dw1 <= DOWN;
end if;
end process;
Q <= cnt;
end architecture udcounter_a; | gpl-3.0 | b58f50e562e062cf0c8ec4bfdca88fa0 | 0.526824 | 3.584615 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/common/shft_wrapper.vhd | 5 | 13,889 | `protect begin_protected
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`protect end_protected
| apache-2.0 | 7aa30a61c86f56fbff2e25815964be2b | 0.934409 | 1.882999 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/lmb_bram_if_cntlr_v4_0/816dc01c/hdl/vhdl/correct_one_bit.vhd | 1 | 6,592 | -------------------------------------------------------------------------------
-- $Id: correct_one_bit.vhd,v 1.1.2.3 2010/09/06 09:01:24 rolandp Exp $
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
------------------------------------------------------------------------------
-- Filename: correct_one_bit.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- correct_one_bit
-------------------------------------------------------------------------------
-- Author: rolandp
-- Revision: $Revision: 1.1.2.3 $
-- Date: $Date: 2010/09/06 09:01:24 $
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity Correct_One_Bit is
generic (
C_USE_LUT6 : boolean := true;
Correct_Value : std_logic_vector(0 to 6));
port (
DIn : in std_logic;
Syndrome : in std_logic_vector(0 to 6);
DCorr : out std_logic);
end entity Correct_One_Bit;
architecture IMP of Correct_One_Bit is
-----------------------------------------------------------------------------
-- Find which bit that has a '1'
-- There is always one bit which has a '1'
-----------------------------------------------------------------------------
function find_one (Syn : std_logic_vector(0 to 6)) return natural is
begin -- function find_one
for I in 0 to 6 loop
if (Syn(I) = '1') then
return I;
end if;
end loop; -- I
return 0; -- Should never reach this statement
end function find_one;
constant di_index : natural := find_one(Correct_Value);
signal corr_sel : std_logic;
signal corr_c : std_logic;
signal lut_compare : std_logic_vector(0 to 5);
signal lut_corr_val : std_logic_vector(0 to 5);
begin -- architecture IMP
Remove_DI_Index : process (Syndrome) is
begin -- process Remove_DI_Index
if (di_index = 0) then
lut_compare <= Syndrome(1 to 6);
lut_corr_val <= Correct_Value(1 to 6);
elsif (di_index = 6) then
lut_compare <= Syndrome(0 to 5);
lut_corr_val <= Correct_Value(0 to 5);
else
lut_compare <= Syndrome(0 to di_index-1) & Syndrome(di_index+1 to 6);
lut_corr_val <= Correct_Value(0 to di_index-1) & Correct_Value(di_index+1 to 6);
end if;
end process Remove_DI_Index;
-- Corr_LUT : LUT6
-- generic map(
-- INIT => X"6996966996696996"
-- )
-- port map(
-- O => corr_sel, -- [out]
-- I0 => InA(5), -- [in]
-- I1 => InA(4), -- [in]
-- I2 => InA(3), -- [in]
-- I3 => InA(2), -- [in]
-- I4 => InA(1), -- [in]
-- I5 => InA(0) -- [in]
-- );
corr_sel <= '0' when lut_compare = lut_corr_val else '1';
Corr_MUXCY : MUXCY_L
port map (
DI => Syndrome(di_index),
CI => '0',
S => corr_sel,
LO => corr_c);
Corr_XORCY : XORCY
port map (
LI => DIn,
CI => corr_c,
O => DCorr);
end architecture IMP;
| apache-2.0 | abaee52a6bc5b5fa252abe83e010b1ba | 0.525334 | 4.258398 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-30bits_outputs31bits/3-ARF/metaheurísticas/arf_wsga.vhd | 1 | 2,603 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-13.07:35:29)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY arf_wsga_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8: IN unsigned(0 TO 30);
output1, output2: OUT unsigned(0 TO 31));
END arf_wsga_entity;
ARCHITECTURE arf_wsga_description OF arf_wsga_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register4: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register5: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register6: unsigned(0 TO 31) := "00000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
register2 := input2 * 2;
WHEN "00000010" =>
register1 := register2 + register1;
register2 := input3 * 3;
register3 := input4 * 4;
WHEN "00000011" =>
register2 := register3 + register2;
register3 := input5 * 5;
register4 := input6 * 6;
WHEN "00000100" =>
register3 := register4 + register3;
register4 := input7 * 7;
register5 := input8 * 8;
WHEN "00000101" =>
register4 := register5 + register4;
register2 := register2 + 10;
register3 := register3 + 12;
WHEN "00000110" =>
register5 := register2 * 14;
register6 := register3 * 16;
WHEN "00000111" =>
register5 := register6 + register5;
register2 := register2 * 18;
register3 := register3 * 20;
WHEN "00001000" =>
register6 := register5 * 22;
register5 := register5 * 24;
register2 := register3 + register2;
WHEN "00001001" =>
register3 := register2 * 26;
register2 := register2 * 28;
WHEN "00001010" =>
register2 := register5 + register2;
register3 := register6 + register3;
WHEN "00001011" =>
output1 <= register1 + register3;
output2 <= register4 + register2;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END arf_wsga_description; | gpl-3.0 | 752535b33486fe56bf69f9e4ceabaa9c | 0.676911 | 3.311705 | false | false | false | false |
freecores/twofish | vhdl/twofish_ecb_encryption_monte_carlo_testbench_128bits.vhd | 1 | 11,309 | -- Twofish_ecb_encryption_monte_carlo_testbench_128bits.vhd
-- Copyright (C) 2006 Spyros Ninos
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this library; see the file COPYING. If not, write to:
--
-- Free Software Foundation
-- 59 Temple Place - Suite 330
-- Boston, MA 02111-1307, USA.
--
-- description : this file is the testbench for the Encryption Monte Carlo KAT of the twofish cipher with 128 bit key
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_arith.all;
use std.textio.all;
entity ecb_encryption_monte_carlo_testbench128 is
end ecb_encryption_monte_carlo_testbench128;
architecture ecb_encryption128_monte_carlo_testbench_arch of ecb_encryption_monte_carlo_testbench128 is
component reg128
port (
in_reg128 : in std_logic_vector(127 downto 0);
out_reg128 : out std_logic_vector(127 downto 0);
enable_reg128, reset_reg128, clk_reg128 : in std_logic
);
end component;
component twofish_keysched128
port (
odd_in_tk128,
even_in_tk128 : in std_logic_vector(7 downto 0);
in_key_tk128 : in std_logic_vector(127 downto 0);
out_key_up_tk128,
out_key_down_tk128 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_whit_keysched128
port (
in_key_twk128 : in std_logic_vector(127 downto 0);
out_K0_twk128,
out_K1_twk128,
out_K2_twk128,
out_K3_twk128,
out_K4_twk128,
out_K5_twk128,
out_K6_twk128,
out_K7_twk128 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_encryption_round128
port (
in1_ter128,
in2_ter128,
in3_ter128,
in4_ter128,
in_Sfirst_ter128,
in_Ssecond_ter128,
in_key_up_ter128,
in_key_down_ter128 : in std_logic_vector(31 downto 0);
out1_ter128,
out2_ter128,
out3_ter128,
out4_ter128 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_data_input
port (
in_tdi : in std_logic_vector(127 downto 0);
out_tdi : out std_logic_vector(127 downto 0)
);
end component;
component twofish_data_output
port (
in_tdo : in std_logic_vector(127 downto 0);
out_tdo : out std_logic_vector(127 downto 0)
);
end component;
component demux128
port ( in_demux128 : in std_logic_vector(127 downto 0);
out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0);
selection_demux128 : in std_logic
);
end component;
component mux128
port ( in1_mux128, in2_mux128 : in std_logic_vector(127 downto 0);
selection_mux128 : in std_logic;
out_mux128 : out std_logic_vector(127 downto 0)
);
end component;
component twofish_S128
port (
in_key_ts128 : in std_logic_vector(127 downto 0);
out_Sfirst_ts128,
out_Ssecond_ts128 : out std_logic_vector(31 downto 0)
);
end component;
FILE input_file : text is in "twofish_ecb_encryption_monte_carlo_testvalues_128bits.txt";
FILE output_file : text is out "twofish_ecb_encryption_monte_carlo_128bits_results.txt";
-- we create the functions that transform a number to text
-- transforming a signle digit to a character
function digit_to_char(number : integer range 0 to 9) return character is
begin
case number is
when 0 => return '0';
when 1 => return '1';
when 2 => return '2';
when 3 => return '3';
when 4 => return '4';
when 5 => return '5';
when 6 => return '6';
when 7 => return '7';
when 8 => return '8';
when 9 => return '9';
end case;
end;
-- transforming multi-digit number to text
function to_text(int_number : integer range 0 to 9999) return string is
variable our_text : string (1 to 4) := (others => ' ');
variable thousands,
hundreds,
tens,
ones : integer range 0 to 9;
begin
ones := int_number mod 10;
tens := ((int_number mod 100) - ones) / 10;
hundreds := ((int_number mod 1000) - (int_number mod 100)) / 100;
thousands := (int_number - (int_number mod 1000)) / 1000;
our_text(1) := digit_to_char(thousands);
our_text(2) := digit_to_char(hundreds);
our_text(3) := digit_to_char(tens);
our_text(4) := digit_to_char(ones);
return our_text;
end;
signal odd_number,
even_number : std_logic_vector(7 downto 0);
signal input_data,
output_data,
twofish_key,
to_encr_reg128,
from_tdi_to_xors,
to_output_whit_xors,
from_xors_to_tdo,
to_mux, to_demux,
from_input_whit_xors,
to_round,
to_input_mux : std_logic_vector(127 downto 0) ;
signal key_up,
key_down,
Sfirst,
Ssecond,
from_xor0,
from_xor1,
from_xor2,
from_xor3,
K0,K1,K2,K3,
K4,K5,K6,K7 : std_logic_vector(31 downto 0);
signal clk : std_logic := '0';
signal mux_selection : std_logic := '0';
signal demux_selection: std_logic := '0';
signal enable_encr_reg : std_logic := '0';
signal reset : std_logic := '0';
signal enable_round_reg : std_logic := '0';
-- begin the testbench arch description
begin
-- getting data to encrypt
data_input: twofish_data_input
port map (
in_tdi => input_data,
out_tdi => from_tdi_to_xors
);
-- producing whitening keys K0..7
the_whitening_step: twofish_whit_keysched128
port map (
in_key_twk128 => twofish_key,
out_K0_twk128 => K0,
out_K1_twk128 => K1,
out_K2_twk128 => K2,
out_K3_twk128 => K3,
out_K4_twk128 => K4,
out_K5_twk128 => K5,
out_K6_twk128 => K6,
out_K7_twk128 => K7
);
-- performing the input whitening XORs
from_xor0 <= K0 XOR from_tdi_to_xors(127 downto 96);
from_xor1 <= K1 XOR from_tdi_to_xors(95 downto 64);
from_xor2 <= K2 XOR from_tdi_to_xors(63 downto 32);
from_xor3 <= K3 XOR from_tdi_to_xors(31 downto 0);
from_input_whit_xors <= from_xor0 & from_xor1 & from_xor2 & from_xor3;
round_reg: reg128
port map ( in_reg128 => from_input_whit_xors,
out_reg128 => to_input_mux,
enable_reg128 => enable_round_reg,
reset_reg128 => reset,
clk_reg128 => clk );
input_mux: mux128
port map ( in1_mux128 => to_input_mux,
in2_mux128 => to_mux,
out_mux128 => to_round,
selection_mux128 => mux_selection
);
-- creating a round
the_keysched_of_the_round: twofish_keysched128
port map (
odd_in_tk128 => odd_number,
even_in_tk128 => even_number,
in_key_tk128 => twofish_key,
out_key_up_tk128 => key_up,
out_key_down_tk128 => key_down
);
producing_the_Skeys: twofish_S128
port map (
in_key_ts128 => twofish_key,
out_Sfirst_ts128 => Sfirst,
out_Ssecond_ts128 => Ssecond
);
the_encryption_circuit: twofish_encryption_round128
port map (
in1_ter128 => to_round(127 downto 96),
in2_ter128 => to_round(95 downto 64),
in3_ter128 => to_round(63 downto 32),
in4_ter128 => to_round(31 downto 0),
in_Sfirst_ter128 => Sfirst,
in_Ssecond_ter128 => Ssecond,
in_key_up_ter128 => key_up,
in_key_down_ter128 => key_down,
out1_ter128 => to_encr_reg128(127 downto 96),
out2_ter128 => to_encr_reg128(95 downto 64),
out3_ter128 => to_encr_reg128(63 downto 32),
out4_ter128 => to_encr_reg128(31 downto 0)
);
encr_reg: reg128
port map ( in_reg128 => to_encr_reg128,
out_reg128 => to_demux,
enable_reg128 => enable_encr_reg,
reset_reg128 => reset,
clk_reg128 => clk );
output_demux: demux128
port map ( in_demux128 => to_demux,
out1_demux128 => to_output_whit_xors,
out2_demux128 => to_mux,
selection_demux128 => demux_selection );
-- don't forget the last swap !!!
from_xors_to_tdo(127 downto 96) <= K4 XOR to_output_whit_xors(63 downto 32);
from_xors_to_tdo(95 downto 64) <= K5 XOR to_output_whit_xors(31 downto 0);
from_xors_to_tdo(63 downto 32) <= K6 XOR to_output_whit_xors(127 downto 96);
from_xors_to_tdo(31 downto 0) <= K7 XOR to_output_whit_xors(95 downto 64);
taking_the_output: twofish_data_output
port map (
in_tdo => from_xors_to_tdo,
out_tdo => output_data
);
-- we create the clock
clk <= not clk after 50 ns; -- period 100 ns
ecb_emc_proc: process
variable key_f, -- key input from file
pt_f, -- plaintext from file
ct_f : line; -- ciphertext from file
variable key_v, -- key vector input
pt_v , -- plaintext vector
ct_v : std_logic_vector(127 downto 0); -- ciphertext vector
variable counter_10000 : integer range 0 to 9999 := 0; -- counter for the 10.000 repeats in the 400 next ones
variable counter_400 : integer range 0 to 399 := 0; -- counter for the 400 repeats
variable round : integer range 0 to 16 := 0; -- holds the rounds
variable intermediate_encryption_result : std_logic_vector(127 downto 0); -- holds the intermediate encryption result
begin
while not endfile(input_file) loop
readline(input_file, key_f);
readline(input_file, pt_f);
readline(input_file,ct_f);
hread(key_f,key_v);
hread(pt_f,pt_v);
hread(ct_f,ct_v);
twofish_key <= key_v;
intermediate_encryption_result := pt_v;
for counter_10000 in 0 to 9999 loop
input_data <= intermediate_encryption_result;
wait for 25 ns;
reset <= '1';
wait for 50 ns;
reset <= '0';
mux_selection <= '0';
demux_selection <= '1';
enable_encr_reg <= '0';
enable_round_reg <= '0';
wait for 50 ns;
enable_round_reg <= '1';
wait for 50 ns;
enable_round_reg <= '0';
-- the first round
even_number <= "00001000"; -- 8
odd_number <= "00001001"; -- 9
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
demux_selection <= '1';
mux_selection <= '1';
-- the rest 15 rounds
for round in 1 to 15 loop
even_number <= conv_std_logic_vector(((round*2)+8), 8);
odd_number <= conv_std_logic_vector(((round*2)+9), 8);
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
end loop;
-- taking final results
demux_selection <= '0';
wait for 25 ns;
intermediate_encryption_result := output_data;
assert false report "I=" & to_text(counter_400) & " R=" & to_text(counter_10000) severity note;
end loop; -- counter_10000
hwrite(key_f, key_v);
hwrite(pt_f, pt_v);
hwrite(ct_f,output_data);
writeline(output_file,key_f);
writeline(output_file,pt_f);
writeline(output_file,ct_f);
assert (ct_v = output_data) report "file entry and encryption result DO NOT match!!! :( " severity failure;
assert (ct_v /= output_data) report "Encryption I=" & to_text(counter_400) &" OK" severity note;
counter_400 := counter_400 + 1;
end loop;
assert false report "***** ECB Encryption Monte Carlo Test with 128 bits key size ended succesfully! :) *****" severity failure;
end process ecb_emc_proc;
end ecb_encryption128_monte_carlo_testbench_arch;
| gpl-2.0 | d11bde101461b4b3b8c20c6032393679 | 0.652843 | 2.739583 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/axi_master_burst_v2_0/1af76933/hdl/src/vhdl/axi_master_burst_rd_status_cntl.vhd | 1 | 15,497 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- Filename: axi_master_burst_rd_status_cntl.vhd
--
-- Description:
-- This file implements the AXI Master Burst Read Status Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_master_burst_rd_status_cntl.vhd
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.0 $
-- Date: $1/19/2011$
--
-- History:
-- DET 1/19/2011 Initial
-- ~~~~~~
-- - Adapted from AXI datamover v2_00_a axi_datamover_rd_status_cntl.vhd
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI MASTER BURST to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_master_burst_rd_status_cntl is
generic (
C_STS_WIDTH : Integer := 8;
C_TAG_WIDTH : Integer range 1 to 8 := 4
);
port (
-- Clock input
primary_aclk : in std_logic;
-- Primary synchronization clock for the Master side
-- interface and internal logic. It is also used
-- for the User interface synchronization when
-- C_STSCMD_IS_ASYNC = 0.
-- Reset input
mmap_reset : in std_logic;
-- Reset used for the internal master logic
-- Command Calculator Interface --------------------------
calc2rsc_calc_error : in std_logic ;
-- Indication from the Command Calculator that a calculation
-- error has occured.
-- Address Controller Status --------------------------
addr2rsc_calc_error : In std_logic ;
-- Indication from the Data Channel Controller FIFO that it
-- is empty (no commands pending)
addr2rsc_fifo_empty : In std_logic ;
-- Indication from the Address Controller FIFO that it
-- is empty (no commands pending)
-- Data Controller Status --------------------------
data2rsc_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- The command tag
data2rsc_calc_error : In std_logic ;
-- Indication from the Data Channel Controller FIFO that it
-- is empty (no commands pending)
data2rsc_okay : In std_logic ;
-- Indication that the AXI Read transfer completed with OK status
data2rsc_decerr : In std_logic ;
-- Indication that the AXI Read transfer completed with decode error status
data2rsc_slverr : In std_logic ;
-- Indication that the AXI Read transfer completed with slave error status
data2rsc_cmd_cmplt : In std_logic ;
-- Indication by the Data Channel Controller that the
-- corresponding status is the last status for a parent command
-- pulled from the command FIFO
rsc2data_ready : Out std_logic;
-- Handshake bit from the Read Status Controller Module indicating
-- that the it is ready to accept a new Read status transfer
data2rsc_valid : in std_logic ;
-- Handshake bit output to the Read Status Controller Module
-- indicating that the Data Controller has valid tag and status
-- indicators to transfer
-- Command/Status Interface --------------------------
rsc2stat_status : Out std_logic_vector(C_STS_WIDTH-1 downto 0);
-- Read Status value collected during a Read Data transfer
-- Output to the Command/Status Module
stat2rsc_status_ready : In std_logic;
-- Input from the Command/Status Module indicating that the
-- Status Reg/FIFO is ready to accept a transfer
rsc2stat_status_valid : Out std_logic ;
-- Control Signal to the Status Reg/FIFO indicating a new status
-- output value is valid and ready for transfer
-- Address and Data Controller Pipe halt --------------------------
rsc2mstr_halt_pipe : Out std_logic
-- Indication to Halt the Data and Address Command pipeline due
-- to the Status FIFO going full or an internal error being logged
);
end entity axi_master_burst_rd_status_cntl;
architecture implementation of axi_master_burst_rd_status_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Constant Declarations --------------------------------------------
Constant OKAY : std_logic_vector(1 downto 0) := "00";
Constant EXOKAY : std_logic_vector(1 downto 0) := "01";
Constant SLVERR : std_logic_vector(1 downto 0) := "10";
Constant DECERR : std_logic_vector(1 downto 0) := "11";
Constant STAT_RSVD : std_logic_vector(3 downto 0) := "0000";
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant STAT_REG_TAG_WIDTH : integer := 4;
-- Signal Declarations --------------------------------------------
signal sig_tag2status : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_rsc2status_valid : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_rd_sts_okay_reg : std_logic := '0';
signal sig_rd_sts_interr_reg : std_logic := '0';
signal sig_rd_sts_decerr_reg : std_logic := '0';
signal sig_rd_sts_slverr_reg : std_logic := '0';
signal sig_rd_sts_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_rd_sts_reg : std_logic := '0';
signal sig_push_rd_sts_reg : std_logic := '0';
Signal sig_rd_sts_push_ok : std_logic := '0';
signal sig_rd_sts_reg_empty : std_logic := '0';
signal sig_rd_sts_reg_full : std_logic := '0';
begin --(architecture implementation)
-- Assign the status write output control
rsc2stat_status_valid <= sig_rsc2status_valid ;
sig_rsc2status_valid <= sig_rd_sts_reg_full;
-- Formulate the status outout value (assumes an 8-bit status width)
rsc2stat_status <= sig_rd_sts_okay_reg &
sig_rd_sts_slverr_reg &
sig_rd_sts_decerr_reg &
sig_rd_sts_interr_reg &
sig_tag2status;
-- Detect that a push of a new status word is completing
sig_rd_sts_push_ok <= sig_rsc2status_valid and
stat2rsc_status_ready;
-- Signal a halt to the execution pipe if new status
-- is valid but the Status FIFO is not accepting it
rsc2mstr_halt_pipe <= sig_rsc2status_valid and
(not(stat2rsc_status_ready) );
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_LE_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is less than or equal to the available number
-- of bits in the Status word.
--
------------------------------------------------------------
GEN_TAG_LE_STAT : if (TAG_WIDTH <= STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_small : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0');
begin
sig_tag2status <= lsig_temp_tag_small;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_SMALL_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_rd_sts_tag_reg)
begin
-- Set default value
lsig_temp_tag_small <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_small(TAG_WIDTH-1 downto 0) <= sig_rd_sts_tag_reg;
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_LE_STAT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_GT_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is greater than the available number of
-- bits in the Status word. The upper bits of the TAG are
-- clipped off (discarded).
--
------------------------------------------------------------
GEN_TAG_GT_STAT : if (TAG_WIDTH > STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_big : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0);
begin
sig_tag2status <= lsig_temp_tag_big;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_BIG_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_rd_sts_tag_reg)
begin
-- Set default value
lsig_temp_tag_big <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_big <= sig_rd_sts_tag_reg(STAT_REG_TAG_WIDTH-1 downto 0);
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_GT_STAT;
------- Read Status Collection Logic --------------------------------
rsc2data_ready <= sig_rsc2data_ready ;
sig_rsc2data_ready <= sig_rd_sts_reg_empty;
sig_push_rd_sts_reg <= data2rsc_valid and
sig_rsc2data_ready;
sig_pop_rd_sts_reg <= sig_rd_sts_push_ok;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: RD_STATUS_FIFO_REG
--
-- Process Description:
-- Implement Read status FIFO register.
-- This register holds the Read status from the Data Controller
-- until it is transfered to the Status FIFO.
--
-------------------------------------------------------------
RD_STATUS_FIFO_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_rd_sts_reg = '1') then
sig_rd_sts_tag_reg <= (others => '0');
sig_rd_sts_interr_reg <= '0';
sig_rd_sts_decerr_reg <= '0';
sig_rd_sts_slverr_reg <= '0';
sig_rd_sts_okay_reg <= '1'; -- set back to default of "OKAY"
sig_rd_sts_reg_full <= '0';
sig_rd_sts_reg_empty <= '1';
Elsif (sig_push_rd_sts_reg = '1') Then
sig_rd_sts_tag_reg <= data2rsc_tag;
sig_rd_sts_interr_reg <= data2rsc_calc_error or
sig_rd_sts_interr_reg;
sig_rd_sts_decerr_reg <= data2rsc_decerr or sig_rd_sts_decerr_reg;
sig_rd_sts_slverr_reg <= data2rsc_slverr or sig_rd_sts_slverr_reg;
sig_rd_sts_okay_reg <= data2rsc_okay and
not(data2rsc_decerr or
sig_rd_sts_decerr_reg or
data2rsc_slverr or
sig_rd_sts_slverr_reg or
data2rsc_calc_error or
sig_rd_sts_interr_reg
);
sig_rd_sts_reg_full <= data2rsc_cmd_cmplt or
data2rsc_calc_error;
sig_rd_sts_reg_empty <= not(data2rsc_cmd_cmplt or
data2rsc_calc_error);
else
null; -- hold current state
end if;
end if;
end process RD_STATUS_FIFO_REG;
end implementation;
| apache-2.0 | 76b91288187cd8c86303f356d009189e | 0.516874 | 4.555262 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/family_support.vhd | 1 | 329,235 | --------------------------------------------------------------------------------
-- $Id: family_support.vhd,v 1.5.2.55 2010/12/16 15:10:57 ostlerf Exp $
--------------------------------------------------------------------------------
-- family_support.vhd - package
--------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
--------------------------------------------------------------------------------
-- Filename: family_support.vhd
--
-- Description:
--
-- FAMILIES, PRIMITIVES and PRIMITIVE AVAILABILITY GUARDS
--
-- This package allows to determine whether a given primitive
-- or set of primitives is available in an FPGA family of interest.
--
-- The key element is the function, 'supported', which is
-- available in four variants (overloads). Here are examples
-- of each:
--
-- supported(virtex2, u_RAMB16_S2)
--
-- supported("Virtex2", u_RAMB16_S2)
--
-- supported(spartan3, (u_MUXCY, u_XORCY, u_FD))
--
-- supported("spartan3", (u_MUXCY, u_XORCY, u_FD))
--
-- The 'supported' function returns true if and only
-- if all of the primitives being tested, as given in the
-- second argument, are available in the FPGA family that
-- is given in the first argument.
--
-- The first argument can be either one of the FPGA family
-- names from the enumeration type, 'families_type', or a
-- (case insensitive) string giving the same information.
-- The family name 'nofamily' is special and supports
-- none of the primitives.
--
-- The second argument is either a primitive or a list of
-- primitives. The set of primitive names that can be
-- tested is defined by the declaration of the
-- enumeration type, 'primitives_type'. The names are
-- the UNISIM-library names for the primitives, prefixed
-- by "u_". (The prefix avoids introducing a name that
-- conflicts with the component declaration for the primitive.)
--
-- The array type, 'primitive_array_type' is the basis for
-- forming lists of primitives. Typically, a fixed list
-- of primitves is expressed as a VHDL aggregate, a
-- comma separated list of primitives enclosed in
-- parentheses. (See the last two examples, above.)
--
-- The 'supported' function can be used as a guard
-- condition for a piece of code that depends on primitives
-- (primitive availability guard). Here is an example:
--
--
-- GEN : if supported(C_FAMILY, (u_MUXCY, u_XORCY)) generate
-- begin
-- ... Here, an implementation that depends on
-- ... MUXCY and XORCY.
-- end generate;
--
--
-- It can also be used in an assertion statement
-- to give warnings about problems that can arise from
-- attempting to implement into a family that does not
-- support all of the required primitives:
--
--
-- assert supported(C_FAMILY, <primtive list>)
-- report "This module cannot be implemnted " &
-- "into family, " & C_FAMILY &
-- ", because one or more of the primitives, " &
-- "<primitive_list>" & ", is not supported."
-- severity error;
--
--
-- A NOTE ON USAGE
--
-- It is probably best to take an exception to the coding
-- guidelines and make the names that are needed
-- from this package visible to a VHDL compilation unit by
--
-- library <libname>;
-- use <libname>.family_support.all;
--
-- rather than by calling out individual names in use clauses.
-- (VHDL tools do not have a common interpretation at present
-- on whether
--
-- use <libname>.family_support.primitives_type"
--
-- makes the enumeration literals visible.)
--
-- ADDITIONAL FEATURES
--
-- - A function, native_lut_size, is available to allow
-- the caller to query the largest sized LUT available in a given
-- FPGA family.
--
-- - A function, equalIgnoringCase, is available to compare strings
-- with case insensitivity. While this can be used to establish
-- whether the target family is some particular family, such
-- usage is discouraged and should be limited to legacy
-- situations or the rare situations where primitive
-- availability guards will not suffice.
--
--------------------------------------------------------------------------------
-- Author: FLO
-- History:
-- FLO 2005Mar24 - First Version
--
-- FLO 11/30/05
-- ^^^^^^
-- Virtex5 added.
-- ~~~~~~
-- TK 03/17/06 Corrected a Spartan3e issue in myimage
-- ~~~~~~
-- FLO 04/26/06
-- ^^^^^^
-- Added the native_lut_size function.
-- ~~~~~~
-- FLO 08/10/06
-- ^^^^^^
-- Added support for families virtex, spartan2 and spartan2e.
-- ~~~~~~
-- FLO 08/25/06
-- ^^^^^^
-- Enhanced the warning in function str2fam. Now when a string that is
-- passed in the call as a parameter does not correspond to a supported fpga
-- family, the string value of the passed string is mentioned in the warning
-- and it is explicitly stated that the returned value is 'nofamily'.
-- ~~~~~~
-- FLO 08/26/06
-- ^^^^^^
-- - Updated the virtex5 primitive set to a more recent list and
-- removed primitives (TEMAC, PCIE, etc.) that are not present
-- in all virtex5 family members.
-- - Added function equalIgnoringCase and an admonition to use it
-- as little as possible.
-- - Made some improvements to descriptions inside comments.
-- ~~~~~~
-- FLO 08/28/06
-- ^^^^^^
-- Added support for families spartan3a and spartan3an. These are initially
-- taken to have the same primitives as spartan3e.
-- ~~~~~~
-- FLO 10/28/06
-- ^^^^^^
-- Changed function str2fam so that it no longer depends on the VHDL
-- attribute, 'VAL. This is an XST workaround.
-- ~~~~~~
-- FLO 03/08/07
-- ^^^^^^
-- Updated spartan3a and sparan3an.
-- Added spartan3adsp.
-- ~~~~~~
-- FLO 08/31/07
-- ^^^^^^
-- A performance XST workaround was implemented to address slowness
-- associated with primitive availability guards. The workaround changes
-- the way that the fam_has_prim constant is initialized (aggregate
-- rather than a system of function and procedure calls).
-- ~~~~~~
-- FLO 04/11/08
-- ^^^^^^
-- Added these families: aspartan3e, aspartan3a, aspartan3an, aspartan3adsp
-- ~~~~~~
-- FLO 04/14/08
-- ^^^^^^
-- Removed family: aspartan3an
-- ~~~~~~
-- FLO 06/25/08
-- ^^^^^^
-- Added these families: qvirtex4, qrvirtex4
-- ~~~~~~
-- FLO 07/26/08
-- ^^^^^^
-- The BSCAN primitive for spartan3e is now BSCAN_SPARTAN3 instead
-- of BSCAN_SPARTAN3E.
-- ~~~~~~
-- FLO 09/02/06
-- ^^^^^^
-- Added an initial approximation of primitives for spartan6 and virtex6.
-- ~~~~~~
-- FLO 09/04/28
-- ^^^^^^
-- -Removed primitive u_BSCAN_SPARTAN3A from spartan6.
-- -Added the 5 and 6 LUTs to spartan6.
-- ~~~~~~
-- FLO 02/09/10 (back to MM/DD/YY)
-- ^^^^^^
-- -Removed primitive u_BSCAN_VIRTEX5 from virtex6.
-- -Added families spartan6l, qspartan6, aspartan6 and virtex6l.
-- ~~~~~~
-- FLO 04/26/10 (MM/DD/YY)
-- ^^^^^^
-- -Added families qspartan6l, qvirtex5 and qvirtex6.
-- ~~~~~~
-- FLO 06/21/10 (MM/DD/YY)
-- ^^^^^^
-- -Added family qrvirtex5.
-- ~~~~~~
--
-- DET 9/7/2010 For 12.4
-- ~~~~~~
-- -- Per CR573867
-- - Added the function get_root_family() as part of the derivative part
-- support improvements.
-- - Added the Virtex7 and Kintex7 device families
-- ^^^^^^
-- ~~~~~~
-- FLO 10/28/10 (MM/DD/YY)
-- ^^^^^^
-- -Added u_SRLC32E as supported for spartan6 (and its derivatives). (CR 575828)
-- ~~~~~~
-- FLO 12/15/10 (MM/DD/YY)
-- ^^^^^^
-- -Changed virtex6cx to be equal to virtex6 (instead of virtex5)
-- -Move kintex7 and virtex7 to the primitives in the Rodin unisim.btl file
-- -Added artix7 from the primitives in the Rodin unisim.btl file
-- ~~~~~~
--
-- DET 3/2/2011 EDk 13.2
-- ~~~~~~
-- -- Per CR595477
-- - Added zynq support in the get_root_family function.
-- ^^^^^^
--
-- DET 03/18/2011
-- ^^^^^^
-- Per CR602290
-- - Added u_RAMB16_S4_S36 for kintex7, virtex7, artix7 to grandfather axi_ethernetlite_v1_00_a.
-- - This change was lost from 13.1 O.40d to 13.2 branch.
-- - Copied the Virtex7 primitive info to zynq primitive entry (instead of the artix7 info)
-- ~~~~~~
--
-- DET 4/4/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR604652
-- - Added kintex7l and virtex7l
-- ^^^^^^
--
--------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinational signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports:- Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
--------------------------------------------------------------------------------
package family_support is
type families_type is
(
nofamily
, kintexu
, kintex7
, kintex7l
, qkintex7
, qkintex7l
, virtexu
, virtex7
, virtex7l
, qvirtex7
, qvirtex7l
, artixu
, artix7
, aartix7
, artix7l
, qartix7
, qartix7l
, zynq
, azynq
, qzynq
);
type primitives_type is range 0 to 865;
constant u_AND2: primitives_type := 0;
constant u_AND2B1L: primitives_type := u_AND2 + 1;
constant u_AND3: primitives_type := u_AND2B1L + 1;
constant u_AND4: primitives_type := u_AND3 + 1;
constant u_AUTOBUF: primitives_type := u_AND4 + 1;
constant u_BSCAN_SPARTAN2: primitives_type := u_AUTOBUF + 1;
constant u_BSCAN_SPARTAN3: primitives_type := u_BSCAN_SPARTAN2 + 1;
constant u_BSCAN_SPARTAN3A: primitives_type := u_BSCAN_SPARTAN3 + 1;
constant u_BSCAN_SPARTAN3E: primitives_type := u_BSCAN_SPARTAN3A + 1;
constant u_BSCAN_SPARTAN6: primitives_type := u_BSCAN_SPARTAN3E + 1;
constant u_BSCAN_VIRTEX: primitives_type := u_BSCAN_SPARTAN6 + 1;
constant u_BSCAN_VIRTEX2: primitives_type := u_BSCAN_VIRTEX + 1;
constant u_BSCAN_VIRTEX4: primitives_type := u_BSCAN_VIRTEX2 + 1;
constant u_BSCAN_VIRTEX5: primitives_type := u_BSCAN_VIRTEX4 + 1;
constant u_BSCAN_VIRTEX6: primitives_type := u_BSCAN_VIRTEX5 + 1;
constant u_BUF: primitives_type := u_BSCAN_VIRTEX6 + 1;
constant u_BUFCF: primitives_type := u_BUF + 1;
constant u_BUFE: primitives_type := u_BUFCF + 1;
constant u_BUFG: primitives_type := u_BUFE + 1;
constant u_BUFGCE: primitives_type := u_BUFG + 1;
constant u_BUFGCE_1: primitives_type := u_BUFGCE + 1;
constant u_BUFGCTRL: primitives_type := u_BUFGCE_1 + 1;
constant u_BUFGDLL: primitives_type := u_BUFGCTRL + 1;
constant u_BUFGMUX: primitives_type := u_BUFGDLL + 1;
constant u_BUFGMUX_1: primitives_type := u_BUFGMUX + 1;
constant u_BUFGMUX_CTRL: primitives_type := u_BUFGMUX_1 + 1;
constant u_BUFGMUX_VIRTEX4: primitives_type := u_BUFGMUX_CTRL + 1;
constant u_BUFGP: primitives_type := u_BUFGMUX_VIRTEX4 + 1;
constant u_BUFH: primitives_type := u_BUFGP + 1;
constant u_BUFHCE: primitives_type := u_BUFH + 1;
constant u_BUFIO: primitives_type := u_BUFHCE + 1;
constant u_BUFIO2: primitives_type := u_BUFIO + 1;
constant u_BUFIO2_2CLK: primitives_type := u_BUFIO2 + 1;
constant u_BUFIO2FB: primitives_type := u_BUFIO2_2CLK + 1;
constant u_BUFIO2FB_2CLK: primitives_type := u_BUFIO2FB + 1;
constant u_BUFIODQS: primitives_type := u_BUFIO2FB_2CLK + 1;
constant u_BUFPLL: primitives_type := u_BUFIODQS + 1;
constant u_BUFPLL_MCB: primitives_type := u_BUFPLL + 1;
constant u_BUFR: primitives_type := u_BUFPLL_MCB + 1;
constant u_BUFT: primitives_type := u_BUFR + 1;
constant u_CAPTURE_SPARTAN2: primitives_type := u_BUFT + 1;
constant u_CAPTURE_SPARTAN3: primitives_type := u_CAPTURE_SPARTAN2 + 1;
constant u_CAPTURE_SPARTAN3A: primitives_type := u_CAPTURE_SPARTAN3 + 1;
constant u_CAPTURE_SPARTAN3E: primitives_type := u_CAPTURE_SPARTAN3A + 1;
constant u_CAPTURE_VIRTEX: primitives_type := u_CAPTURE_SPARTAN3E + 1;
constant u_CAPTURE_VIRTEX2: primitives_type := u_CAPTURE_VIRTEX + 1;
constant u_CAPTURE_VIRTEX4: primitives_type := u_CAPTURE_VIRTEX2 + 1;
constant u_CAPTURE_VIRTEX5: primitives_type := u_CAPTURE_VIRTEX4 + 1;
constant u_CAPTURE_VIRTEX6: primitives_type := u_CAPTURE_VIRTEX5 + 1;
constant u_CARRY4: primitives_type := u_CAPTURE_VIRTEX6 + 1;
constant u_CFGLUT5: primitives_type := u_CARRY4 + 1;
constant u_CLKDLL: primitives_type := u_CFGLUT5 + 1;
constant u_CLKDLLE: primitives_type := u_CLKDLL + 1;
constant u_CLKDLLHF: primitives_type := u_CLKDLLE + 1;
constant u_CRC32: primitives_type := u_CLKDLLHF + 1;
constant u_CRC64: primitives_type := u_CRC32 + 1;
constant u_DCIRESET: primitives_type := u_CRC64 + 1;
constant u_DCM: primitives_type := u_DCIRESET + 1;
constant u_DCM_ADV: primitives_type := u_DCM + 1;
constant u_DCM_BASE: primitives_type := u_DCM_ADV + 1;
constant u_DCM_CLKGEN: primitives_type := u_DCM_BASE + 1;
constant u_DCM_PS: primitives_type := u_DCM_CLKGEN + 1;
constant u_DNA_PORT: primitives_type := u_DCM_PS + 1;
constant u_DSP48: primitives_type := u_DNA_PORT + 1;
constant u_DSP48A: primitives_type := u_DSP48 + 1;
constant u_DSP48A1: primitives_type := u_DSP48A + 1;
constant u_DSP48E: primitives_type := u_DSP48A1 + 1;
constant u_DSP48E1: primitives_type := u_DSP48E + 1;
constant u_DUMMY_INV: primitives_type := u_DSP48E1 + 1;
constant u_DUMMY_NOR2: primitives_type := u_DUMMY_INV + 1;
constant u_EFUSE_USR: primitives_type := u_DUMMY_NOR2 + 1;
constant u_EMAC: primitives_type := u_EFUSE_USR + 1;
constant u_FD: primitives_type := u_EMAC + 1;
constant u_FD_1: primitives_type := u_FD + 1;
constant u_FDC: primitives_type := u_FD_1 + 1;
constant u_FDC_1: primitives_type := u_FDC + 1;
constant u_FDCE: primitives_type := u_FDC_1 + 1;
constant u_FDCE_1: primitives_type := u_FDCE + 1;
constant u_FDCP: primitives_type := u_FDCE_1 + 1;
constant u_FDCP_1: primitives_type := u_FDCP + 1;
constant u_FDCPE: primitives_type := u_FDCP_1 + 1;
constant u_FDCPE_1: primitives_type := u_FDCPE + 1;
constant u_FDDRCPE: primitives_type := u_FDCPE_1 + 1;
constant u_FDDRRSE: primitives_type := u_FDDRCPE + 1;
constant u_FDE: primitives_type := u_FDDRRSE + 1;
constant u_FDE_1: primitives_type := u_FDE + 1;
constant u_FDP: primitives_type := u_FDE_1 + 1;
constant u_FDP_1: primitives_type := u_FDP + 1;
constant u_FDPE: primitives_type := u_FDP_1 + 1;
constant u_FDPE_1: primitives_type := u_FDPE + 1;
constant u_FDR: primitives_type := u_FDPE_1 + 1;
constant u_FDR_1: primitives_type := u_FDR + 1;
constant u_FDRE: primitives_type := u_FDR_1 + 1;
constant u_FDRE_1: primitives_type := u_FDRE + 1;
constant u_FDRS: primitives_type := u_FDRE_1 + 1;
constant u_FDRS_1: primitives_type := u_FDRS + 1;
constant u_FDRSE: primitives_type := u_FDRS_1 + 1;
constant u_FDRSE_1: primitives_type := u_FDRSE + 1;
constant u_FDS: primitives_type := u_FDRSE_1 + 1;
constant u_FDS_1: primitives_type := u_FDS + 1;
constant u_FDSE: primitives_type := u_FDS_1 + 1;
constant u_FDSE_1: primitives_type := u_FDSE + 1;
constant u_FIFO16: primitives_type := u_FDSE_1 + 1;
constant u_FIFO18: primitives_type := u_FIFO16 + 1;
constant u_FIFO18_36: primitives_type := u_FIFO18 + 1;
constant u_FIFO18E1: primitives_type := u_FIFO18_36 + 1;
constant u_FIFO36: primitives_type := u_FIFO18E1 + 1;
constant u_FIFO36_72: primitives_type := u_FIFO36 + 1;
constant u_FIFO36E1: primitives_type := u_FIFO36_72 + 1;
constant u_FMAP: primitives_type := u_FIFO36E1 + 1;
constant u_FRAME_ECC_VIRTEX4: primitives_type := u_FMAP + 1;
constant u_FRAME_ECC_VIRTEX5: primitives_type := u_FRAME_ECC_VIRTEX4 + 1;
constant u_FRAME_ECC_VIRTEX6: primitives_type := u_FRAME_ECC_VIRTEX5 + 1;
constant u_GND: primitives_type := u_FRAME_ECC_VIRTEX6 + 1;
constant u_GT10_10GE_4: primitives_type := u_GND + 1;
constant u_GT10_10GE_8: primitives_type := u_GT10_10GE_4 + 1;
constant u_GT10_10GFC_4: primitives_type := u_GT10_10GE_8 + 1;
constant u_GT10_10GFC_8: primitives_type := u_GT10_10GFC_4 + 1;
constant u_GT10_AURORA_1: primitives_type := u_GT10_10GFC_8 + 1;
constant u_GT10_AURORA_2: primitives_type := u_GT10_AURORA_1 + 1;
constant u_GT10_AURORA_4: primitives_type := u_GT10_AURORA_2 + 1;
constant u_GT10_AURORAX_4: primitives_type := u_GT10_AURORA_4 + 1;
constant u_GT10_AURORAX_8: primitives_type := u_GT10_AURORAX_4 + 1;
constant u_GT10_CUSTOM: primitives_type := u_GT10_AURORAX_8 + 1;
constant u_GT10_INFINIBAND_1: primitives_type := u_GT10_CUSTOM + 1;
constant u_GT10_INFINIBAND_2: primitives_type := u_GT10_INFINIBAND_1 + 1;
constant u_GT10_INFINIBAND_4: primitives_type := u_GT10_INFINIBAND_2 + 1;
constant u_GT10_OC192_4: primitives_type := u_GT10_INFINIBAND_4 + 1;
constant u_GT10_OC192_8: primitives_type := u_GT10_OC192_4 + 1;
constant u_GT10_OC48_1: primitives_type := u_GT10_OC192_8 + 1;
constant u_GT10_OC48_2: primitives_type := u_GT10_OC48_1 + 1;
constant u_GT10_OC48_4: primitives_type := u_GT10_OC48_2 + 1;
constant u_GT10_PCI_EXPRESS_1: primitives_type := u_GT10_OC48_4 + 1;
constant u_GT10_PCI_EXPRESS_2: primitives_type := u_GT10_PCI_EXPRESS_1 + 1;
constant u_GT10_PCI_EXPRESS_4: primitives_type := u_GT10_PCI_EXPRESS_2 + 1;
constant u_GT10_XAUI_1: primitives_type := u_GT10_PCI_EXPRESS_4 + 1;
constant u_GT10_XAUI_2: primitives_type := u_GT10_XAUI_1 + 1;
constant u_GT10_XAUI_4: primitives_type := u_GT10_XAUI_2 + 1;
constant u_GT11CLK: primitives_type := u_GT10_XAUI_4 + 1;
constant u_GT11CLK_MGT: primitives_type := u_GT11CLK + 1;
constant u_GT11_CUSTOM: primitives_type := u_GT11CLK_MGT + 1;
constant u_GT_AURORA_1: primitives_type := u_GT11_CUSTOM + 1;
constant u_GT_AURORA_2: primitives_type := u_GT_AURORA_1 + 1;
constant u_GT_AURORA_4: primitives_type := u_GT_AURORA_2 + 1;
constant u_GT_CUSTOM: primitives_type := u_GT_AURORA_4 + 1;
constant u_GT_ETHERNET_1: primitives_type := u_GT_CUSTOM + 1;
constant u_GT_ETHERNET_2: primitives_type := u_GT_ETHERNET_1 + 1;
constant u_GT_ETHERNET_4: primitives_type := u_GT_ETHERNET_2 + 1;
constant u_GT_FIBRE_CHAN_1: primitives_type := u_GT_ETHERNET_4 + 1;
constant u_GT_FIBRE_CHAN_2: primitives_type := u_GT_FIBRE_CHAN_1 + 1;
constant u_GT_FIBRE_CHAN_4: primitives_type := u_GT_FIBRE_CHAN_2 + 1;
constant u_GT_INFINIBAND_1: primitives_type := u_GT_FIBRE_CHAN_4 + 1;
constant u_GT_INFINIBAND_2: primitives_type := u_GT_INFINIBAND_1 + 1;
constant u_GT_INFINIBAND_4: primitives_type := u_GT_INFINIBAND_2 + 1;
constant u_GTPA1_DUAL: primitives_type := u_GT_INFINIBAND_4 + 1;
constant u_GT_XAUI_1: primitives_type := u_GTPA1_DUAL + 1;
constant u_GT_XAUI_2: primitives_type := u_GT_XAUI_1 + 1;
constant u_GT_XAUI_4: primitives_type := u_GT_XAUI_2 + 1;
constant u_GTXE1: primitives_type := u_GT_XAUI_4 + 1;
constant u_IBUF: primitives_type := u_GTXE1 + 1;
constant u_IBUF_AGP: primitives_type := u_IBUF + 1;
constant u_IBUF_CTT: primitives_type := u_IBUF_AGP + 1;
constant u_IBUF_DLY_ADJ: primitives_type := u_IBUF_CTT + 1;
constant u_IBUFDS: primitives_type := u_IBUF_DLY_ADJ + 1;
constant u_IBUFDS_DIFF_OUT: primitives_type := u_IBUFDS + 1;
constant u_IBUFDS_DLY_ADJ: primitives_type := u_IBUFDS_DIFF_OUT + 1;
constant u_IBUFDS_GTXE1: primitives_type := u_IBUFDS_DLY_ADJ + 1;
constant u_IBUFG: primitives_type := u_IBUFDS_GTXE1 + 1;
constant u_IBUFG_AGP: primitives_type := u_IBUFG + 1;
constant u_IBUFG_CTT: primitives_type := u_IBUFG_AGP + 1;
constant u_IBUFGDS: primitives_type := u_IBUFG_CTT + 1;
constant u_IBUFGDS_DIFF_OUT: primitives_type := u_IBUFGDS + 1;
constant u_IBUFG_GTL: primitives_type := u_IBUFGDS_DIFF_OUT + 1;
constant u_IBUFG_GTLP: primitives_type := u_IBUFG_GTL + 1;
constant u_IBUFG_HSTL_I: primitives_type := u_IBUFG_GTLP + 1;
constant u_IBUFG_HSTL_III: primitives_type := u_IBUFG_HSTL_I + 1;
constant u_IBUFG_HSTL_IV: primitives_type := u_IBUFG_HSTL_III + 1;
constant u_IBUFG_LVCMOS18: primitives_type := u_IBUFG_HSTL_IV + 1;
constant u_IBUFG_LVCMOS2: primitives_type := u_IBUFG_LVCMOS18 + 1;
constant u_IBUFG_LVDS: primitives_type := u_IBUFG_LVCMOS2 + 1;
constant u_IBUFG_LVPECL: primitives_type := u_IBUFG_LVDS + 1;
constant u_IBUFG_PCI33_3: primitives_type := u_IBUFG_LVPECL + 1;
constant u_IBUFG_PCI33_5: primitives_type := u_IBUFG_PCI33_3 + 1;
constant u_IBUFG_PCI66_3: primitives_type := u_IBUFG_PCI33_5 + 1;
constant u_IBUFG_PCIX66_3: primitives_type := u_IBUFG_PCI66_3 + 1;
constant u_IBUFG_SSTL2_I: primitives_type := u_IBUFG_PCIX66_3 + 1;
constant u_IBUFG_SSTL2_II: primitives_type := u_IBUFG_SSTL2_I + 1;
constant u_IBUFG_SSTL3_I: primitives_type := u_IBUFG_SSTL2_II + 1;
constant u_IBUFG_SSTL3_II: primitives_type := u_IBUFG_SSTL3_I + 1;
constant u_IBUF_GTL: primitives_type := u_IBUFG_SSTL3_II + 1;
constant u_IBUF_GTLP: primitives_type := u_IBUF_GTL + 1;
constant u_IBUF_HSTL_I: primitives_type := u_IBUF_GTLP + 1;
constant u_IBUF_HSTL_III: primitives_type := u_IBUF_HSTL_I + 1;
constant u_IBUF_HSTL_IV: primitives_type := u_IBUF_HSTL_III + 1;
constant u_IBUF_LVCMOS18: primitives_type := u_IBUF_HSTL_IV + 1;
constant u_IBUF_LVCMOS2: primitives_type := u_IBUF_LVCMOS18 + 1;
constant u_IBUF_LVDS: primitives_type := u_IBUF_LVCMOS2 + 1;
constant u_IBUF_LVPECL: primitives_type := u_IBUF_LVDS + 1;
constant u_IBUF_PCI33_3: primitives_type := u_IBUF_LVPECL + 1;
constant u_IBUF_PCI33_5: primitives_type := u_IBUF_PCI33_3 + 1;
constant u_IBUF_PCI66_3: primitives_type := u_IBUF_PCI33_5 + 1;
constant u_IBUF_PCIX66_3: primitives_type := u_IBUF_PCI66_3 + 1;
constant u_IBUF_SSTL2_I: primitives_type := u_IBUF_PCIX66_3 + 1;
constant u_IBUF_SSTL2_II: primitives_type := u_IBUF_SSTL2_I + 1;
constant u_IBUF_SSTL3_I: primitives_type := u_IBUF_SSTL2_II + 1;
constant u_IBUF_SSTL3_II: primitives_type := u_IBUF_SSTL3_I + 1;
constant u_ICAP_SPARTAN3A: primitives_type := u_IBUF_SSTL3_II + 1;
constant u_ICAP_SPARTAN6: primitives_type := u_ICAP_SPARTAN3A + 1;
constant u_ICAP_VIRTEX2: primitives_type := u_ICAP_SPARTAN6 + 1;
constant u_ICAP_VIRTEX4: primitives_type := u_ICAP_VIRTEX2 + 1;
constant u_ICAP_VIRTEX5: primitives_type := u_ICAP_VIRTEX4 + 1;
constant u_ICAP_VIRTEX6: primitives_type := u_ICAP_VIRTEX5 + 1;
constant u_IDDR: primitives_type := u_ICAP_VIRTEX6 + 1;
constant u_IDDR2: primitives_type := u_IDDR + 1;
constant u_IDDR_2CLK: primitives_type := u_IDDR2 + 1;
constant u_IDELAY: primitives_type := u_IDDR_2CLK + 1;
constant u_IDELAYCTRL: primitives_type := u_IDELAY + 1;
constant u_IFDDRCPE: primitives_type := u_IDELAYCTRL + 1;
constant u_IFDDRRSE: primitives_type := u_IFDDRCPE + 1;
constant u_INV: primitives_type := u_IFDDRRSE + 1;
constant u_IOBUF: primitives_type := u_INV + 1;
constant u_IOBUF_AGP: primitives_type := u_IOBUF + 1;
constant u_IOBUF_CTT: primitives_type := u_IOBUF_AGP + 1;
constant u_IOBUFDS: primitives_type := u_IOBUF_CTT + 1;
constant u_IOBUFDS_DIFF_OUT: primitives_type := u_IOBUFDS + 1;
constant u_IOBUF_F_12: primitives_type := u_IOBUFDS_DIFF_OUT + 1;
constant u_IOBUF_F_16: primitives_type := u_IOBUF_F_12 + 1;
constant u_IOBUF_F_2: primitives_type := u_IOBUF_F_16 + 1;
constant u_IOBUF_F_24: primitives_type := u_IOBUF_F_2 + 1;
constant u_IOBUF_F_4: primitives_type := u_IOBUF_F_24 + 1;
constant u_IOBUF_F_6: primitives_type := u_IOBUF_F_4 + 1;
constant u_IOBUF_F_8: primitives_type := u_IOBUF_F_6 + 1;
constant u_IOBUF_GTL: primitives_type := u_IOBUF_F_8 + 1;
constant u_IOBUF_GTLP: primitives_type := u_IOBUF_GTL + 1;
constant u_IOBUF_HSTL_I: primitives_type := u_IOBUF_GTLP + 1;
constant u_IOBUF_HSTL_III: primitives_type := u_IOBUF_HSTL_I + 1;
constant u_IOBUF_HSTL_IV: primitives_type := u_IOBUF_HSTL_III + 1;
constant u_IOBUF_LVCMOS18: primitives_type := u_IOBUF_HSTL_IV + 1;
constant u_IOBUF_LVCMOS2: primitives_type := u_IOBUF_LVCMOS18 + 1;
constant u_IOBUF_LVDS: primitives_type := u_IOBUF_LVCMOS2 + 1;
constant u_IOBUF_LVPECL: primitives_type := u_IOBUF_LVDS + 1;
constant u_IOBUF_PCI33_3: primitives_type := u_IOBUF_LVPECL + 1;
constant u_IOBUF_PCI33_5: primitives_type := u_IOBUF_PCI33_3 + 1;
constant u_IOBUF_PCI66_3: primitives_type := u_IOBUF_PCI33_5 + 1;
constant u_IOBUF_PCIX66_3: primitives_type := u_IOBUF_PCI66_3 + 1;
constant u_IOBUF_S_12: primitives_type := u_IOBUF_PCIX66_3 + 1;
constant u_IOBUF_S_16: primitives_type := u_IOBUF_S_12 + 1;
constant u_IOBUF_S_2: primitives_type := u_IOBUF_S_16 + 1;
constant u_IOBUF_S_24: primitives_type := u_IOBUF_S_2 + 1;
constant u_IOBUF_S_4: primitives_type := u_IOBUF_S_24 + 1;
constant u_IOBUF_S_6: primitives_type := u_IOBUF_S_4 + 1;
constant u_IOBUF_S_8: primitives_type := u_IOBUF_S_6 + 1;
constant u_IOBUF_SSTL2_I: primitives_type := u_IOBUF_S_8 + 1;
constant u_IOBUF_SSTL2_II: primitives_type := u_IOBUF_SSTL2_I + 1;
constant u_IOBUF_SSTL3_I: primitives_type := u_IOBUF_SSTL2_II + 1;
constant u_IOBUF_SSTL3_II: primitives_type := u_IOBUF_SSTL3_I + 1;
constant u_IODELAY: primitives_type := u_IOBUF_SSTL3_II + 1;
constant u_IODELAY2: primitives_type := u_IODELAY + 1;
constant u_IODELAYE1: primitives_type := u_IODELAY2 + 1;
constant u_IODRP2: primitives_type := u_IODELAYE1 + 1;
constant u_IODRP2_MCB: primitives_type := u_IODRP2 + 1;
constant u_ISERDES: primitives_type := u_IODRP2_MCB + 1;
constant u_ISERDES2: primitives_type := u_ISERDES + 1;
constant u_ISERDESE1: primitives_type := u_ISERDES2 + 1;
constant u_ISERDES_NODELAY: primitives_type := u_ISERDESE1 + 1;
constant u_JTAGPPC: primitives_type := u_ISERDES_NODELAY + 1;
constant u_JTAG_SIM_SPARTAN6: primitives_type := u_JTAGPPC + 1;
constant u_JTAG_SIM_VIRTEX6: primitives_type := u_JTAG_SIM_SPARTAN6 + 1;
constant u_KEEPER: primitives_type := u_JTAG_SIM_VIRTEX6 + 1;
constant u_KEY_CLEAR: primitives_type := u_KEEPER + 1;
constant u_LD: primitives_type := u_KEY_CLEAR + 1;
constant u_LD_1: primitives_type := u_LD + 1;
constant u_LDC: primitives_type := u_LD_1 + 1;
constant u_LDC_1: primitives_type := u_LDC + 1;
constant u_LDCE: primitives_type := u_LDC_1 + 1;
constant u_LDCE_1: primitives_type := u_LDCE + 1;
constant u_LDCP: primitives_type := u_LDCE_1 + 1;
constant u_LDCP_1: primitives_type := u_LDCP + 1;
constant u_LDCPE: primitives_type := u_LDCP_1 + 1;
constant u_LDCPE_1: primitives_type := u_LDCPE + 1;
constant u_LDE: primitives_type := u_LDCPE_1 + 1;
constant u_LDE_1: primitives_type := u_LDE + 1;
constant u_LDP: primitives_type := u_LDE_1 + 1;
constant u_LDP_1: primitives_type := u_LDP + 1;
constant u_LDPE: primitives_type := u_LDP_1 + 1;
constant u_LDPE_1: primitives_type := u_LDPE + 1;
constant u_LUT1: primitives_type := u_LDPE_1 + 1;
constant u_LUT1_D: primitives_type := u_LUT1 + 1;
constant u_LUT1_L: primitives_type := u_LUT1_D + 1;
constant u_LUT2: primitives_type := u_LUT1_L + 1;
constant u_LUT2_D: primitives_type := u_LUT2 + 1;
constant u_LUT2_L: primitives_type := u_LUT2_D + 1;
constant u_LUT3: primitives_type := u_LUT2_L + 1;
constant u_LUT3_D: primitives_type := u_LUT3 + 1;
constant u_LUT3_L: primitives_type := u_LUT3_D + 1;
constant u_LUT4: primitives_type := u_LUT3_L + 1;
constant u_LUT4_D: primitives_type := u_LUT4 + 1;
constant u_LUT4_L: primitives_type := u_LUT4_D + 1;
constant u_LUT5: primitives_type := u_LUT4_L + 1;
constant u_LUT5_D: primitives_type := u_LUT5 + 1;
constant u_LUT5_L: primitives_type := u_LUT5_D + 1;
constant u_LUT6: primitives_type := u_LUT5_L + 1;
constant u_LUT6_D: primitives_type := u_LUT6 + 1;
constant u_LUT6_L: primitives_type := u_LUT6_D + 1;
constant u_MCB: primitives_type := u_LUT6_L + 1;
constant u_MMCM_ADV: primitives_type := u_MCB + 1;
constant u_MMCM_BASE: primitives_type := u_MMCM_ADV + 1;
constant u_MULT18X18: primitives_type := u_MMCM_BASE + 1;
constant u_MULT18X18S: primitives_type := u_MULT18X18 + 1;
constant u_MULT18X18SIO: primitives_type := u_MULT18X18S + 1;
constant u_MULT_AND: primitives_type := u_MULT18X18SIO + 1;
constant u_MUXCY: primitives_type := u_MULT_AND + 1;
constant u_MUXCY_D: primitives_type := u_MUXCY + 1;
constant u_MUXCY_L: primitives_type := u_MUXCY_D + 1;
constant u_MUXF5: primitives_type := u_MUXCY_L + 1;
constant u_MUXF5_D: primitives_type := u_MUXF5 + 1;
constant u_MUXF5_L: primitives_type := u_MUXF5_D + 1;
constant u_MUXF6: primitives_type := u_MUXF5_L + 1;
constant u_MUXF6_D: primitives_type := u_MUXF6 + 1;
constant u_MUXF6_L: primitives_type := u_MUXF6_D + 1;
constant u_MUXF7: primitives_type := u_MUXF6_L + 1;
constant u_MUXF7_D: primitives_type := u_MUXF7 + 1;
constant u_MUXF7_L: primitives_type := u_MUXF7_D + 1;
constant u_MUXF8: primitives_type := u_MUXF7_L + 1;
constant u_MUXF8_D: primitives_type := u_MUXF8 + 1;
constant u_MUXF8_L: primitives_type := u_MUXF8_D + 1;
constant u_NAND2: primitives_type := u_MUXF8_L + 1;
constant u_NAND3: primitives_type := u_NAND2 + 1;
constant u_NAND4: primitives_type := u_NAND3 + 1;
constant u_NOR2: primitives_type := u_NAND4 + 1;
constant u_NOR3: primitives_type := u_NOR2 + 1;
constant u_NOR4: primitives_type := u_NOR3 + 1;
constant u_OBUF: primitives_type := u_NOR4 + 1;
constant u_OBUF_AGP: primitives_type := u_OBUF + 1;
constant u_OBUF_CTT: primitives_type := u_OBUF_AGP + 1;
constant u_OBUFDS: primitives_type := u_OBUF_CTT + 1;
constant u_OBUF_F_12: primitives_type := u_OBUFDS + 1;
constant u_OBUF_F_16: primitives_type := u_OBUF_F_12 + 1;
constant u_OBUF_F_2: primitives_type := u_OBUF_F_16 + 1;
constant u_OBUF_F_24: primitives_type := u_OBUF_F_2 + 1;
constant u_OBUF_F_4: primitives_type := u_OBUF_F_24 + 1;
constant u_OBUF_F_6: primitives_type := u_OBUF_F_4 + 1;
constant u_OBUF_F_8: primitives_type := u_OBUF_F_6 + 1;
constant u_OBUF_GTL: primitives_type := u_OBUF_F_8 + 1;
constant u_OBUF_GTLP: primitives_type := u_OBUF_GTL + 1;
constant u_OBUF_HSTL_I: primitives_type := u_OBUF_GTLP + 1;
constant u_OBUF_HSTL_III: primitives_type := u_OBUF_HSTL_I + 1;
constant u_OBUF_HSTL_IV: primitives_type := u_OBUF_HSTL_III + 1;
constant u_OBUF_LVCMOS18: primitives_type := u_OBUF_HSTL_IV + 1;
constant u_OBUF_LVCMOS2: primitives_type := u_OBUF_LVCMOS18 + 1;
constant u_OBUF_LVDS: primitives_type := u_OBUF_LVCMOS2 + 1;
constant u_OBUF_LVPECL: primitives_type := u_OBUF_LVDS + 1;
constant u_OBUF_PCI33_3: primitives_type := u_OBUF_LVPECL + 1;
constant u_OBUF_PCI33_5: primitives_type := u_OBUF_PCI33_3 + 1;
constant u_OBUF_PCI66_3: primitives_type := u_OBUF_PCI33_5 + 1;
constant u_OBUF_PCIX66_3: primitives_type := u_OBUF_PCI66_3 + 1;
constant u_OBUF_S_12: primitives_type := u_OBUF_PCIX66_3 + 1;
constant u_OBUF_S_16: primitives_type := u_OBUF_S_12 + 1;
constant u_OBUF_S_2: primitives_type := u_OBUF_S_16 + 1;
constant u_OBUF_S_24: primitives_type := u_OBUF_S_2 + 1;
constant u_OBUF_S_4: primitives_type := u_OBUF_S_24 + 1;
constant u_OBUF_S_6: primitives_type := u_OBUF_S_4 + 1;
constant u_OBUF_S_8: primitives_type := u_OBUF_S_6 + 1;
constant u_OBUF_SSTL2_I: primitives_type := u_OBUF_S_8 + 1;
constant u_OBUF_SSTL2_II: primitives_type := u_OBUF_SSTL2_I + 1;
constant u_OBUF_SSTL3_I: primitives_type := u_OBUF_SSTL2_II + 1;
constant u_OBUF_SSTL3_II: primitives_type := u_OBUF_SSTL3_I + 1;
constant u_OBUFT: primitives_type := u_OBUF_SSTL3_II + 1;
constant u_OBUFT_AGP: primitives_type := u_OBUFT + 1;
constant u_OBUFT_CTT: primitives_type := u_OBUFT_AGP + 1;
constant u_OBUFTDS: primitives_type := u_OBUFT_CTT + 1;
constant u_OBUFT_F_12: primitives_type := u_OBUFTDS + 1;
constant u_OBUFT_F_16: primitives_type := u_OBUFT_F_12 + 1;
constant u_OBUFT_F_2: primitives_type := u_OBUFT_F_16 + 1;
constant u_OBUFT_F_24: primitives_type := u_OBUFT_F_2 + 1;
constant u_OBUFT_F_4: primitives_type := u_OBUFT_F_24 + 1;
constant u_OBUFT_F_6: primitives_type := u_OBUFT_F_4 + 1;
constant u_OBUFT_F_8: primitives_type := u_OBUFT_F_6 + 1;
constant u_OBUFT_GTL: primitives_type := u_OBUFT_F_8 + 1;
constant u_OBUFT_GTLP: primitives_type := u_OBUFT_GTL + 1;
constant u_OBUFT_HSTL_I: primitives_type := u_OBUFT_GTLP + 1;
constant u_OBUFT_HSTL_III: primitives_type := u_OBUFT_HSTL_I + 1;
constant u_OBUFT_HSTL_IV: primitives_type := u_OBUFT_HSTL_III + 1;
constant u_OBUFT_LVCMOS18: primitives_type := u_OBUFT_HSTL_IV + 1;
constant u_OBUFT_LVCMOS2: primitives_type := u_OBUFT_LVCMOS18 + 1;
constant u_OBUFT_LVDS: primitives_type := u_OBUFT_LVCMOS2 + 1;
constant u_OBUFT_LVPECL: primitives_type := u_OBUFT_LVDS + 1;
constant u_OBUFT_PCI33_3: primitives_type := u_OBUFT_LVPECL + 1;
constant u_OBUFT_PCI33_5: primitives_type := u_OBUFT_PCI33_3 + 1;
constant u_OBUFT_PCI66_3: primitives_type := u_OBUFT_PCI33_5 + 1;
constant u_OBUFT_PCIX66_3: primitives_type := u_OBUFT_PCI66_3 + 1;
constant u_OBUFT_S_12: primitives_type := u_OBUFT_PCIX66_3 + 1;
constant u_OBUFT_S_16: primitives_type := u_OBUFT_S_12 + 1;
constant u_OBUFT_S_2: primitives_type := u_OBUFT_S_16 + 1;
constant u_OBUFT_S_24: primitives_type := u_OBUFT_S_2 + 1;
constant u_OBUFT_S_4: primitives_type := u_OBUFT_S_24 + 1;
constant u_OBUFT_S_6: primitives_type := u_OBUFT_S_4 + 1;
constant u_OBUFT_S_8: primitives_type := u_OBUFT_S_6 + 1;
constant u_OBUFT_SSTL2_I: primitives_type := u_OBUFT_S_8 + 1;
constant u_OBUFT_SSTL2_II: primitives_type := u_OBUFT_SSTL2_I + 1;
constant u_OBUFT_SSTL3_I: primitives_type := u_OBUFT_SSTL2_II + 1;
constant u_OBUFT_SSTL3_II: primitives_type := u_OBUFT_SSTL3_I + 1;
constant u_OCT_CALIBRATE: primitives_type := u_OBUFT_SSTL3_II + 1;
constant u_ODDR: primitives_type := u_OCT_CALIBRATE + 1;
constant u_ODDR2: primitives_type := u_ODDR + 1;
constant u_OFDDRCPE: primitives_type := u_ODDR2 + 1;
constant u_OFDDRRSE: primitives_type := u_OFDDRCPE + 1;
constant u_OFDDRTCPE: primitives_type := u_OFDDRRSE + 1;
constant u_OFDDRTRSE: primitives_type := u_OFDDRTCPE + 1;
constant u_OR2: primitives_type := u_OFDDRTRSE + 1;
constant u_OR2L: primitives_type := u_OR2 + 1;
constant u_OR3: primitives_type := u_OR2L + 1;
constant u_OR4: primitives_type := u_OR3 + 1;
constant u_ORCY: primitives_type := u_OR4 + 1;
constant u_OSERDES: primitives_type := u_ORCY + 1;
constant u_OSERDES2: primitives_type := u_OSERDES + 1;
constant u_OSERDESE1: primitives_type := u_OSERDES2 + 1;
constant u_PCIE_2_0: primitives_type := u_OSERDESE1 + 1;
constant u_PCIE_A1: primitives_type := u_PCIE_2_0 + 1;
constant u_PLL_ADV: primitives_type := u_PCIE_A1 + 1;
constant u_PLL_BASE: primitives_type := u_PLL_ADV + 1;
constant u_PMCD: primitives_type := u_PLL_BASE + 1;
constant u_POST_CRC_INTERNAL: primitives_type := u_PMCD + 1;
constant u_PPC405: primitives_type := u_POST_CRC_INTERNAL + 1;
constant u_PPC405_ADV: primitives_type := u_PPC405 + 1;
constant u_PPR_FRAME: primitives_type := u_PPC405_ADV + 1;
constant u_PULLDOWN: primitives_type := u_PPR_FRAME + 1;
constant u_PULLUP: primitives_type := u_PULLDOWN + 1;
constant u_RAM128X1D: primitives_type := u_PULLUP + 1;
constant u_RAM128X1S: primitives_type := u_RAM128X1D + 1;
constant u_RAM128X1S_1: primitives_type := u_RAM128X1S + 1;
constant u_RAM16X1D: primitives_type := u_RAM128X1S_1 + 1;
constant u_RAM16X1D_1: primitives_type := u_RAM16X1D + 1;
constant u_RAM16X1S: primitives_type := u_RAM16X1D_1 + 1;
constant u_RAM16X1S_1: primitives_type := u_RAM16X1S + 1;
constant u_RAM16X2S: primitives_type := u_RAM16X1S_1 + 1;
constant u_RAM16X4S: primitives_type := u_RAM16X2S + 1;
constant u_RAM16X8S: primitives_type := u_RAM16X4S + 1;
constant u_RAM256X1S: primitives_type := u_RAM16X8S + 1;
constant u_RAM32M: primitives_type := u_RAM256X1S + 1;
constant u_RAM32X1D: primitives_type := u_RAM32M + 1;
constant u_RAM32X1D_1: primitives_type := u_RAM32X1D + 1;
constant u_RAM32X1S: primitives_type := u_RAM32X1D_1 + 1;
constant u_RAM32X1S_1: primitives_type := u_RAM32X1S + 1;
constant u_RAM32X2S: primitives_type := u_RAM32X1S_1 + 1;
constant u_RAM32X4S: primitives_type := u_RAM32X2S + 1;
constant u_RAM32X8S: primitives_type := u_RAM32X4S + 1;
constant u_RAM64M: primitives_type := u_RAM32X8S + 1;
constant u_RAM64X1D: primitives_type := u_RAM64M + 1;
constant u_RAM64X1D_1: primitives_type := u_RAM64X1D + 1;
constant u_RAM64X1S: primitives_type := u_RAM64X1D_1 + 1;
constant u_RAM64X1S_1: primitives_type := u_RAM64X1S + 1;
constant u_RAM64X2S: primitives_type := u_RAM64X1S_1 + 1;
constant u_RAMB16: primitives_type := u_RAM64X2S + 1;
constant u_RAMB16BWE: primitives_type := u_RAMB16 + 1;
constant u_RAMB16BWER: primitives_type := u_RAMB16BWE + 1;
constant u_RAMB16BWE_S18: primitives_type := u_RAMB16BWER + 1;
constant u_RAMB16BWE_S18_S18: primitives_type := u_RAMB16BWE_S18 + 1;
constant u_RAMB16BWE_S18_S9: primitives_type := u_RAMB16BWE_S18_S18 + 1;
constant u_RAMB16BWE_S36: primitives_type := u_RAMB16BWE_S18_S9 + 1;
constant u_RAMB16BWE_S36_S18: primitives_type := u_RAMB16BWE_S36 + 1;
constant u_RAMB16BWE_S36_S36: primitives_type := u_RAMB16BWE_S36_S18 + 1;
constant u_RAMB16BWE_S36_S9: primitives_type := u_RAMB16BWE_S36_S36 + 1;
constant u_RAMB16_S1: primitives_type := u_RAMB16BWE_S36_S9 + 1;
constant u_RAMB16_S18: primitives_type := u_RAMB16_S1 + 1;
constant u_RAMB16_S18_S18: primitives_type := u_RAMB16_S18 + 1;
constant u_RAMB16_S18_S36: primitives_type := u_RAMB16_S18_S18 + 1;
constant u_RAMB16_S1_S1: primitives_type := u_RAMB16_S18_S36 + 1;
constant u_RAMB16_S1_S18: primitives_type := u_RAMB16_S1_S1 + 1;
constant u_RAMB16_S1_S2: primitives_type := u_RAMB16_S1_S18 + 1;
constant u_RAMB16_S1_S36: primitives_type := u_RAMB16_S1_S2 + 1;
constant u_RAMB16_S1_S4: primitives_type := u_RAMB16_S1_S36 + 1;
constant u_RAMB16_S1_S9: primitives_type := u_RAMB16_S1_S4 + 1;
constant u_RAMB16_S2: primitives_type := u_RAMB16_S1_S9 + 1;
constant u_RAMB16_S2_S18: primitives_type := u_RAMB16_S2 + 1;
constant u_RAMB16_S2_S2: primitives_type := u_RAMB16_S2_S18 + 1;
constant u_RAMB16_S2_S36: primitives_type := u_RAMB16_S2_S2 + 1;
constant u_RAMB16_S2_S4: primitives_type := u_RAMB16_S2_S36 + 1;
constant u_RAMB16_S2_S9: primitives_type := u_RAMB16_S2_S4 + 1;
constant u_RAMB16_S36: primitives_type := u_RAMB16_S2_S9 + 1;
constant u_RAMB16_S36_S36: primitives_type := u_RAMB16_S36 + 1;
constant u_RAMB16_S4: primitives_type := u_RAMB16_S36_S36 + 1;
constant u_RAMB16_S4_S18: primitives_type := u_RAMB16_S4 + 1;
constant u_RAMB16_S4_S36: primitives_type := u_RAMB16_S4_S18 + 1;
constant u_RAMB16_S4_S4: primitives_type := u_RAMB16_S4_S36 + 1;
constant u_RAMB16_S4_S9: primitives_type := u_RAMB16_S4_S4 + 1;
constant u_RAMB16_S9: primitives_type := u_RAMB16_S4_S9 + 1;
constant u_RAMB16_S9_S18: primitives_type := u_RAMB16_S9 + 1;
constant u_RAMB16_S9_S36: primitives_type := u_RAMB16_S9_S18 + 1;
constant u_RAMB16_S9_S9: primitives_type := u_RAMB16_S9_S36 + 1;
constant u_RAMB18: primitives_type := u_RAMB16_S9_S9 + 1;
constant u_RAMB18E1: primitives_type := u_RAMB18 + 1;
constant u_RAMB18SDP: primitives_type := u_RAMB18E1 + 1;
constant u_RAMB32_S64_ECC: primitives_type := u_RAMB18SDP + 1;
constant u_RAMB36: primitives_type := u_RAMB32_S64_ECC + 1;
constant u_RAMB36E1: primitives_type := u_RAMB36 + 1;
constant u_RAMB36_EXP: primitives_type := u_RAMB36E1 + 1;
constant u_RAMB36SDP: primitives_type := u_RAMB36_EXP + 1;
constant u_RAMB36SDP_EXP: primitives_type := u_RAMB36SDP + 1;
constant u_RAMB4_S1: primitives_type := u_RAMB36SDP_EXP + 1;
constant u_RAMB4_S16: primitives_type := u_RAMB4_S1 + 1;
constant u_RAMB4_S16_S16: primitives_type := u_RAMB4_S16 + 1;
constant u_RAMB4_S1_S1: primitives_type := u_RAMB4_S16_S16 + 1;
constant u_RAMB4_S1_S16: primitives_type := u_RAMB4_S1_S1 + 1;
constant u_RAMB4_S1_S2: primitives_type := u_RAMB4_S1_S16 + 1;
constant u_RAMB4_S1_S4: primitives_type := u_RAMB4_S1_S2 + 1;
constant u_RAMB4_S1_S8: primitives_type := u_RAMB4_S1_S4 + 1;
constant u_RAMB4_S2: primitives_type := u_RAMB4_S1_S8 + 1;
constant u_RAMB4_S2_S16: primitives_type := u_RAMB4_S2 + 1;
constant u_RAMB4_S2_S2: primitives_type := u_RAMB4_S2_S16 + 1;
constant u_RAMB4_S2_S4: primitives_type := u_RAMB4_S2_S2 + 1;
constant u_RAMB4_S2_S8: primitives_type := u_RAMB4_S2_S4 + 1;
constant u_RAMB4_S4: primitives_type := u_RAMB4_S2_S8 + 1;
constant u_RAMB4_S4_S16: primitives_type := u_RAMB4_S4 + 1;
constant u_RAMB4_S4_S4: primitives_type := u_RAMB4_S4_S16 + 1;
constant u_RAMB4_S4_S8: primitives_type := u_RAMB4_S4_S4 + 1;
constant u_RAMB4_S8: primitives_type := u_RAMB4_S4_S8 + 1;
constant u_RAMB4_S8_S16: primitives_type := u_RAMB4_S8 + 1;
constant u_RAMB4_S8_S8: primitives_type := u_RAMB4_S8_S16 + 1;
constant u_RAMB8BWER: primitives_type := u_RAMB4_S8_S8 + 1;
constant u_ROM128X1: primitives_type := u_RAMB8BWER + 1;
constant u_ROM16X1: primitives_type := u_ROM128X1 + 1;
constant u_ROM256X1: primitives_type := u_ROM16X1 + 1;
constant u_ROM32X1: primitives_type := u_ROM256X1 + 1;
constant u_ROM64X1: primitives_type := u_ROM32X1 + 1;
constant u_SLAVE_SPI: primitives_type := u_ROM64X1 + 1;
constant u_SPI_ACCESS: primitives_type := u_SLAVE_SPI + 1;
constant u_SRL16: primitives_type := u_SPI_ACCESS + 1;
constant u_SRL16_1: primitives_type := u_SRL16 + 1;
constant u_SRL16E: primitives_type := u_SRL16_1 + 1;
constant u_SRL16E_1: primitives_type := u_SRL16E + 1;
constant u_SRLC16: primitives_type := u_SRL16E_1 + 1;
constant u_SRLC16_1: primitives_type := u_SRLC16 + 1;
constant u_SRLC16E: primitives_type := u_SRLC16_1 + 1;
constant u_SRLC16E_1: primitives_type := u_SRLC16E + 1;
constant u_SRLC32E: primitives_type := u_SRLC16E_1 + 1;
constant u_STARTBUF_SPARTAN2: primitives_type := u_SRLC32E + 1;
constant u_STARTBUF_SPARTAN3: primitives_type := u_STARTBUF_SPARTAN2 + 1;
constant u_STARTBUF_SPARTAN3E: primitives_type := u_STARTBUF_SPARTAN3 + 1;
constant u_STARTBUF_VIRTEX: primitives_type := u_STARTBUF_SPARTAN3E + 1;
constant u_STARTBUF_VIRTEX2: primitives_type := u_STARTBUF_VIRTEX + 1;
constant u_STARTBUF_VIRTEX4: primitives_type := u_STARTBUF_VIRTEX2 + 1;
constant u_STARTUP_SPARTAN2: primitives_type := u_STARTBUF_VIRTEX4 + 1;
constant u_STARTUP_SPARTAN3: primitives_type := u_STARTUP_SPARTAN2 + 1;
constant u_STARTUP_SPARTAN3A: primitives_type := u_STARTUP_SPARTAN3 + 1;
constant u_STARTUP_SPARTAN3E: primitives_type := u_STARTUP_SPARTAN3A + 1;
constant u_STARTUP_SPARTAN6: primitives_type := u_STARTUP_SPARTAN3E + 1;
constant u_STARTUP_VIRTEX: primitives_type := u_STARTUP_SPARTAN6 + 1;
constant u_STARTUP_VIRTEX2: primitives_type := u_STARTUP_VIRTEX + 1;
constant u_STARTUP_VIRTEX4: primitives_type := u_STARTUP_VIRTEX2 + 1;
constant u_STARTUP_VIRTEX5: primitives_type := u_STARTUP_VIRTEX4 + 1;
constant u_STARTUP_VIRTEX6: primitives_type := u_STARTUP_VIRTEX5 + 1;
constant u_SUSPEND_SYNC: primitives_type := u_STARTUP_VIRTEX6 + 1;
constant u_SYSMON: primitives_type := u_SUSPEND_SYNC + 1;
constant u_TEMAC_SINGLE: primitives_type := u_SYSMON + 1;
constant u_TOC: primitives_type := u_TEMAC_SINGLE + 1;
constant u_TOCBUF: primitives_type := u_TOC + 1;
constant u_USR_ACCESS_VIRTEX4: primitives_type := u_TOCBUF + 1;
constant u_USR_ACCESS_VIRTEX5: primitives_type := u_USR_ACCESS_VIRTEX4 + 1;
constant u_USR_ACCESS_VIRTEX6: primitives_type := u_USR_ACCESS_VIRTEX5 + 1;
constant u_VCC: primitives_type := u_USR_ACCESS_VIRTEX6 + 1;
constant u_XNOR2: primitives_type := u_VCC + 1;
constant u_XNOR3: primitives_type := u_XNOR2 + 1;
constant u_XNOR4: primitives_type := u_XNOR3 + 1;
constant u_XOR2: primitives_type := u_XNOR4 + 1;
constant u_XOR3: primitives_type := u_XOR2 + 1;
constant u_XOR4: primitives_type := u_XOR3 + 1;
constant u_XORCY: primitives_type := u_XOR4 + 1;
constant u_XORCY_D: primitives_type := u_XORCY + 1;
constant u_XORCY_L: primitives_type := u_XORCY_D + 1;
-- Primitives added for artix7, kintex6, virtex7, and zynq
constant u_AND2B1: primitives_type := u_XORCY_L + 1;
constant u_AND2B2: primitives_type := u_AND2B1 + 1;
constant u_AND3B1: primitives_type := u_AND2B2 + 1;
constant u_AND3B2: primitives_type := u_AND3B1 + 1;
constant u_AND3B3: primitives_type := u_AND3B2 + 1;
constant u_AND4B1: primitives_type := u_AND3B3 + 1;
constant u_AND4B2: primitives_type := u_AND4B1 + 1;
constant u_AND4B3: primitives_type := u_AND4B2 + 1;
constant u_AND4B4: primitives_type := u_AND4B3 + 1;
constant u_AND5: primitives_type := u_AND4B4 + 1;
constant u_AND5B1: primitives_type := u_AND5 + 1;
constant u_AND5B2: primitives_type := u_AND5B1 + 1;
constant u_AND5B3: primitives_type := u_AND5B2 + 1;
constant u_AND5B4: primitives_type := u_AND5B3 + 1;
constant u_AND5B5: primitives_type := u_AND5B4 + 1;
constant u_BSCANE2: primitives_type := u_AND5B5 + 1;
constant u_BUFMR: primitives_type := u_BSCANE2 + 1;
constant u_BUFMRCE: primitives_type := u_BUFMR + 1;
constant u_CAPTUREE2: primitives_type := u_BUFMRCE + 1;
constant u_CFG_IO_ACCESS: primitives_type := u_CAPTUREE2 + 1;
constant u_FRAME_ECCE2: primitives_type := u_CFG_IO_ACCESS + 1;
constant u_GTXE2_CHANNEL: primitives_type := u_FRAME_ECCE2 + 1;
constant u_GTXE2_COMMON: primitives_type := u_GTXE2_CHANNEL + 1;
constant u_IBUF_DCIEN: primitives_type := u_GTXE2_COMMON + 1;
constant u_IBUFDS_BLVDS_25: primitives_type := u_IBUF_DCIEN + 1;
constant u_IBUFDS_DCIEN: primitives_type := u_IBUFDS_BLVDS_25 + 1;
constant u_IBUFDS_DIFF_OUT_DCIEN: primitives_type := u_IBUFDS_DCIEN + 1;
constant u_IBUFDS_GTE2: primitives_type := u_IBUFDS_DIFF_OUT_DCIEN + 1;
constant u_IBUFDS_LVDS_25: primitives_type := u_IBUFDS_GTE2 + 1;
constant u_IBUFGDS_BLVDS_25: primitives_type := u_IBUFDS_LVDS_25 + 1;
constant u_IBUFGDS_LVDS_25: primitives_type := u_IBUFGDS_BLVDS_25 + 1;
constant u_IBUFG_HSTL_I_18: primitives_type := u_IBUFGDS_LVDS_25 + 1;
constant u_IBUFG_HSTL_I_DCI: primitives_type := u_IBUFG_HSTL_I_18 + 1;
constant u_IBUFG_HSTL_I_DCI_18: primitives_type := u_IBUFG_HSTL_I_DCI + 1;
constant u_IBUFG_HSTL_II: primitives_type := u_IBUFG_HSTL_I_DCI_18 + 1;
constant u_IBUFG_HSTL_II_18: primitives_type := u_IBUFG_HSTL_II + 1;
constant u_IBUFG_HSTL_II_DCI: primitives_type := u_IBUFG_HSTL_II_18 + 1;
constant u_IBUFG_HSTL_II_DCI_18: primitives_type := u_IBUFG_HSTL_II_DCI + 1;
constant u_IBUFG_HSTL_III_18: primitives_type := u_IBUFG_HSTL_II_DCI_18 + 1;
constant u_IBUFG_HSTL_III_DCI: primitives_type := u_IBUFG_HSTL_III_18 + 1;
constant u_IBUFG_HSTL_III_DCI_18: primitives_type := u_IBUFG_HSTL_III_DCI + 1;
constant u_IBUFG_LVCMOS12: primitives_type := u_IBUFG_HSTL_III_DCI_18 + 1;
constant u_IBUFG_LVCMOS15: primitives_type := u_IBUFG_LVCMOS12 + 1;
constant u_IBUFG_LVCMOS25: primitives_type := u_IBUFG_LVCMOS15 + 1;
constant u_IBUFG_LVCMOS33: primitives_type := u_IBUFG_LVCMOS25 + 1;
constant u_IBUFG_LVDCI_15: primitives_type := u_IBUFG_LVCMOS33 + 1;
constant u_IBUFG_LVDCI_18: primitives_type := u_IBUFG_LVDCI_15 + 1;
constant u_IBUFG_LVDCI_DV2_15: primitives_type := u_IBUFG_LVDCI_18 + 1;
constant u_IBUFG_LVDCI_DV2_18: primitives_type := u_IBUFG_LVDCI_DV2_15 + 1;
constant u_IBUFG_LVTTL: primitives_type := u_IBUFG_LVDCI_DV2_18 + 1;
constant u_IBUFG_SSTL18_I: primitives_type := u_IBUFG_LVTTL + 1;
constant u_IBUFG_SSTL18_I_DCI: primitives_type := u_IBUFG_SSTL18_I + 1;
constant u_IBUFG_SSTL18_II: primitives_type := u_IBUFG_SSTL18_I_DCI + 1;
constant u_IBUFG_SSTL18_II_DCI: primitives_type := u_IBUFG_SSTL18_II + 1;
constant u_IBUF_HSTL_I_18: primitives_type := u_IBUFG_SSTL18_II_DCI + 1;
constant u_IBUF_HSTL_I_DCI: primitives_type := u_IBUF_HSTL_I_18 + 1;
constant u_IBUF_HSTL_I_DCI_18: primitives_type := u_IBUF_HSTL_I_DCI + 1;
constant u_IBUF_HSTL_II: primitives_type := u_IBUF_HSTL_I_DCI_18 + 1;
constant u_IBUF_HSTL_II_18: primitives_type := u_IBUF_HSTL_II + 1;
constant u_IBUF_HSTL_II_DCI: primitives_type := u_IBUF_HSTL_II_18 + 1;
constant u_IBUF_HSTL_II_DCI_18: primitives_type := u_IBUF_HSTL_II_DCI + 1;
constant u_IBUF_HSTL_III_18: primitives_type := u_IBUF_HSTL_II_DCI_18 + 1;
constant u_IBUF_HSTL_III_DCI: primitives_type := u_IBUF_HSTL_III_18 + 1;
constant u_IBUF_HSTL_III_DCI_18: primitives_type := u_IBUF_HSTL_III_DCI + 1;
constant u_IBUF_LVCMOS12: primitives_type := u_IBUF_HSTL_III_DCI_18 + 1;
constant u_IBUF_LVCMOS15: primitives_type := u_IBUF_LVCMOS12 + 1;
constant u_IBUF_LVCMOS25: primitives_type := u_IBUF_LVCMOS15 + 1;
constant u_IBUF_LVCMOS33: primitives_type := u_IBUF_LVCMOS25 + 1;
constant u_IBUF_LVDCI_15: primitives_type := u_IBUF_LVCMOS33 + 1;
constant u_IBUF_LVDCI_18: primitives_type := u_IBUF_LVDCI_15 + 1;
constant u_IBUF_LVDCI_DV2_15: primitives_type := u_IBUF_LVDCI_18 + 1;
constant u_IBUF_LVDCI_DV2_18: primitives_type := u_IBUF_LVDCI_DV2_15 + 1;
constant u_IBUF_LVTTL: primitives_type := u_IBUF_LVDCI_DV2_18 + 1;
constant u_IBUF_SSTL18_I: primitives_type := u_IBUF_LVTTL + 1;
constant u_IBUF_SSTL18_I_DCI: primitives_type := u_IBUF_SSTL18_I + 1;
constant u_IBUF_SSTL18_II: primitives_type := u_IBUF_SSTL18_I_DCI + 1;
constant u_IBUF_SSTL18_II_DCI: primitives_type := u_IBUF_SSTL18_II + 1;
constant u_ICAPE2: primitives_type := u_IBUF_SSTL18_II_DCI + 1;
constant u_IDELAYE2: primitives_type := u_ICAPE2 + 1;
constant u_IN_FIFO: primitives_type := u_IDELAYE2 + 1;
constant u_IOBUFDS_BLVDS_25: primitives_type := u_IN_FIFO + 1;
constant u_IOBUFDS_DIFF_OUT_DCIEN: primitives_type := u_IOBUFDS_BLVDS_25 + 1;
constant u_IOBUF_HSTL_I_18: primitives_type := u_IOBUFDS_DIFF_OUT_DCIEN + 1;
constant u_IOBUF_HSTL_II: primitives_type := u_IOBUF_HSTL_I_18 + 1;
constant u_IOBUF_HSTL_II_18: primitives_type := u_IOBUF_HSTL_II + 1;
constant u_IOBUF_HSTL_II_DCI: primitives_type := u_IOBUF_HSTL_II_18 + 1;
constant u_IOBUF_HSTL_II_DCI_18: primitives_type := u_IOBUF_HSTL_II_DCI + 1;
constant u_IOBUF_HSTL_III_18: primitives_type := u_IOBUF_HSTL_II_DCI_18 + 1;
constant u_IOBUF_LVCMOS12: primitives_type := u_IOBUF_HSTL_III_18 + 1;
constant u_IOBUF_LVCMOS15: primitives_type := u_IOBUF_LVCMOS12 + 1;
constant u_IOBUF_LVCMOS25: primitives_type := u_IOBUF_LVCMOS15 + 1;
constant u_IOBUF_LVCMOS33: primitives_type := u_IOBUF_LVCMOS25 + 1;
constant u_IOBUF_LVDCI_15: primitives_type := u_IOBUF_LVCMOS33 + 1;
constant u_IOBUF_LVDCI_18: primitives_type := u_IOBUF_LVDCI_15 + 1;
constant u_IOBUF_LVDCI_DV2_15: primitives_type := u_IOBUF_LVDCI_18 + 1;
constant u_IOBUF_LVDCI_DV2_18: primitives_type := u_IOBUF_LVDCI_DV2_15 + 1;
constant u_IOBUF_LVTTL: primitives_type := u_IOBUF_LVDCI_DV2_18 + 1;
constant u_IOBUF_SSTL18_I: primitives_type := u_IOBUF_LVTTL + 1;
constant u_IOBUF_SSTL18_II: primitives_type := u_IOBUF_SSTL18_I + 1;
constant u_IOBUF_SSTL18_II_DCI: primitives_type := u_IOBUF_SSTL18_II + 1;
constant u_ISERDESE2: primitives_type := u_IOBUF_SSTL18_II_DCI + 1;
constant u_JTAG_SIME2: primitives_type := u_ISERDESE2 + 1;
constant u_LUT6_2: primitives_type := u_JTAG_SIME2 + 1;
constant u_MMCME2_ADV: primitives_type := u_LUT6_2 + 1;
constant u_MMCME2_BASE: primitives_type := u_MMCME2_ADV + 1;
constant u_NAND2B1: primitives_type := u_MMCME2_BASE + 1;
constant u_NAND2B2: primitives_type := u_NAND2B1 + 1;
constant u_NAND3B1: primitives_type := u_NAND2B2 + 1;
constant u_NAND3B2: primitives_type := u_NAND3B1 + 1;
constant u_NAND3B3: primitives_type := u_NAND3B2 + 1;
constant u_NAND4B1: primitives_type := u_NAND3B3 + 1;
constant u_NAND4B2: primitives_type := u_NAND4B1 + 1;
constant u_NAND4B3: primitives_type := u_NAND4B2 + 1;
constant u_NAND4B4: primitives_type := u_NAND4B3 + 1;
constant u_NAND5: primitives_type := u_NAND4B4 + 1;
constant u_NAND5B1: primitives_type := u_NAND5 + 1;
constant u_NAND5B2: primitives_type := u_NAND5B1 + 1;
constant u_NAND5B3: primitives_type := u_NAND5B2 + 1;
constant u_NAND5B4: primitives_type := u_NAND5B3 + 1;
constant u_NAND5B5: primitives_type := u_NAND5B4 + 1;
constant u_NOR2B1: primitives_type := u_NAND5B5 + 1;
constant u_NOR2B2: primitives_type := u_NOR2B1 + 1;
constant u_NOR3B1: primitives_type := u_NOR2B2 + 1;
constant u_NOR3B2: primitives_type := u_NOR3B1 + 1;
constant u_NOR3B3: primitives_type := u_NOR3B2 + 1;
constant u_NOR4B1: primitives_type := u_NOR3B3 + 1;
constant u_NOR4B2: primitives_type := u_NOR4B1 + 1;
constant u_NOR4B3: primitives_type := u_NOR4B2 + 1;
constant u_NOR4B4: primitives_type := u_NOR4B3 + 1;
constant u_NOR5: primitives_type := u_NOR4B4 + 1;
constant u_NOR5B1: primitives_type := u_NOR5 + 1;
constant u_NOR5B2: primitives_type := u_NOR5B1 + 1;
constant u_NOR5B3: primitives_type := u_NOR5B2 + 1;
constant u_NOR5B4: primitives_type := u_NOR5B3 + 1;
constant u_NOR5B5: primitives_type := u_NOR5B4 + 1;
constant u_OBUFDS_BLVDS_25: primitives_type := u_NOR5B5 + 1;
constant u_OBUFDS_DUAL_BUF: primitives_type := u_OBUFDS_BLVDS_25 + 1;
constant u_OBUFDS_LVDS_25: primitives_type := u_OBUFDS_DUAL_BUF + 1;
constant u_OBUF_HSTL_I_18: primitives_type := u_OBUFDS_LVDS_25 + 1;
constant u_OBUF_HSTL_I_DCI: primitives_type := u_OBUF_HSTL_I_18 + 1;
constant u_OBUF_HSTL_I_DCI_18: primitives_type := u_OBUF_HSTL_I_DCI + 1;
constant u_OBUF_HSTL_II: primitives_type := u_OBUF_HSTL_I_DCI_18 + 1;
constant u_OBUF_HSTL_II_18: primitives_type := u_OBUF_HSTL_II + 1;
constant u_OBUF_HSTL_II_DCI: primitives_type := u_OBUF_HSTL_II_18 + 1;
constant u_OBUF_HSTL_II_DCI_18: primitives_type := u_OBUF_HSTL_II_DCI + 1;
constant u_OBUF_HSTL_III_18: primitives_type := u_OBUF_HSTL_II_DCI_18 + 1;
constant u_OBUF_HSTL_III_DCI: primitives_type := u_OBUF_HSTL_III_18 + 1;
constant u_OBUF_HSTL_III_DCI_18: primitives_type := u_OBUF_HSTL_III_DCI + 1;
constant u_OBUF_LVCMOS12: primitives_type := u_OBUF_HSTL_III_DCI_18 + 1;
constant u_OBUF_LVCMOS15: primitives_type := u_OBUF_LVCMOS12 + 1;
constant u_OBUF_LVCMOS25: primitives_type := u_OBUF_LVCMOS15 + 1;
constant u_OBUF_LVCMOS33: primitives_type := u_OBUF_LVCMOS25 + 1;
constant u_OBUF_LVDCI_15: primitives_type := u_OBUF_LVCMOS33 + 1;
constant u_OBUF_LVDCI_18: primitives_type := u_OBUF_LVDCI_15 + 1;
constant u_OBUF_LVDCI_DV2_15: primitives_type := u_OBUF_LVDCI_18 + 1;
constant u_OBUF_LVDCI_DV2_18: primitives_type := u_OBUF_LVDCI_DV2_15 + 1;
constant u_OBUF_LVTTL: primitives_type := u_OBUF_LVDCI_DV2_18 + 1;
constant u_OBUF_SSTL18_I: primitives_type := u_OBUF_LVTTL + 1;
constant u_OBUF_SSTL18_I_DCI: primitives_type := u_OBUF_SSTL18_I + 1;
constant u_OBUF_SSTL18_II: primitives_type := u_OBUF_SSTL18_I_DCI + 1;
constant u_OBUF_SSTL18_II_DCI: primitives_type := u_OBUF_SSTL18_II + 1;
constant u_OBUFT_DCIEN: primitives_type := u_OBUF_SSTL18_II_DCI + 1;
constant u_OBUFTDS_BLVDS_25: primitives_type := u_OBUFT_DCIEN + 1;
constant u_OBUFTDS_DCIEN: primitives_type := u_OBUFTDS_BLVDS_25 + 1;
constant u_OBUFTDS_DCIEN_DUAL_BUF: primitives_type := u_OBUFTDS_DCIEN + 1;
constant u_OBUFTDS_DUAL_BUF: primitives_type := u_OBUFTDS_DCIEN_DUAL_BUF + 1;
constant u_OBUFTDS_LVDS_25: primitives_type := u_OBUFTDS_DUAL_BUF + 1;
constant u_OBUFT_HSTL_I_18: primitives_type := u_OBUFTDS_LVDS_25 + 1;
constant u_OBUFT_HSTL_I_DCI: primitives_type := u_OBUFT_HSTL_I_18 + 1;
constant u_OBUFT_HSTL_I_DCI_18: primitives_type := u_OBUFT_HSTL_I_DCI + 1;
constant u_OBUFT_HSTL_II: primitives_type := u_OBUFT_HSTL_I_DCI_18 + 1;
constant u_OBUFT_HSTL_II_18: primitives_type := u_OBUFT_HSTL_II + 1;
constant u_OBUFT_HSTL_II_DCI: primitives_type := u_OBUFT_HSTL_II_18 + 1;
constant u_OBUFT_HSTL_II_DCI_18: primitives_type := u_OBUFT_HSTL_II_DCI + 1;
constant u_OBUFT_HSTL_III_18: primitives_type := u_OBUFT_HSTL_II_DCI_18 + 1;
constant u_OBUFT_HSTL_III_DCI: primitives_type := u_OBUFT_HSTL_III_18 + 1;
constant u_OBUFT_HSTL_III_DCI_18: primitives_type := u_OBUFT_HSTL_III_DCI + 1;
constant u_OBUFT_LVCMOS12: primitives_type := u_OBUFT_HSTL_III_DCI_18 + 1;
constant u_OBUFT_LVCMOS15: primitives_type := u_OBUFT_LVCMOS12 + 1;
constant u_OBUFT_LVCMOS25: primitives_type := u_OBUFT_LVCMOS15 + 1;
constant u_OBUFT_LVCMOS33: primitives_type := u_OBUFT_LVCMOS25 + 1;
constant u_OBUFT_LVDCI_15: primitives_type := u_OBUFT_LVCMOS33 + 1;
constant u_OBUFT_LVDCI_18: primitives_type := u_OBUFT_LVDCI_15 + 1;
constant u_OBUFT_LVDCI_DV2_15: primitives_type := u_OBUFT_LVDCI_18 + 1;
constant u_OBUFT_LVDCI_DV2_18: primitives_type := u_OBUFT_LVDCI_DV2_15 + 1;
constant u_OBUFT_LVTTL: primitives_type := u_OBUFT_LVDCI_DV2_18 + 1;
constant u_OBUFT_SSTL18_I: primitives_type := u_OBUFT_LVTTL + 1;
constant u_OBUFT_SSTL18_I_DCI: primitives_type := u_OBUFT_SSTL18_I + 1;
constant u_OBUFT_SSTL18_II: primitives_type := u_OBUFT_SSTL18_I_DCI + 1;
constant u_OBUFT_SSTL18_II_DCI: primitives_type := u_OBUFT_SSTL18_II + 1;
constant u_ODELAYE2: primitives_type := u_OBUFT_SSTL18_II_DCI + 1;
constant u_OR2B1: primitives_type := u_ODELAYE2 + 1;
constant u_OR2B2: primitives_type := u_OR2B1 + 1;
constant u_OR3B1: primitives_type := u_OR2B2 + 1;
constant u_OR3B2: primitives_type := u_OR3B1 + 1;
constant u_OR3B3: primitives_type := u_OR3B2 + 1;
constant u_OR4B1: primitives_type := u_OR3B3 + 1;
constant u_OR4B2: primitives_type := u_OR4B1 + 1;
constant u_OR4B3: primitives_type := u_OR4B2 + 1;
constant u_OR4B4: primitives_type := u_OR4B3 + 1;
constant u_OR5: primitives_type := u_OR4B4 + 1;
constant u_OR5B1: primitives_type := u_OR5 + 1;
constant u_OR5B2: primitives_type := u_OR5B1 + 1;
constant u_OR5B3: primitives_type := u_OR5B2 + 1;
constant u_OR5B4: primitives_type := u_OR5B3 + 1;
constant u_OR5B5: primitives_type := u_OR5B4 + 1;
constant u_OSERDESE2: primitives_type := u_OR5B5 + 1;
constant u_OUT_FIFO: primitives_type := u_OSERDESE2 + 1;
constant u_PCIE_2_1: primitives_type := u_OUT_FIFO + 1;
constant u_PHASER_IN: primitives_type := u_PCIE_2_1 + 1;
constant u_PHASER_IN_PHY: primitives_type := u_PHASER_IN + 1;
constant u_PHASER_OUT: primitives_type := u_PHASER_IN_PHY + 1;
constant u_PHASER_OUT_PHY: primitives_type := u_PHASER_OUT + 1;
constant u_PHASER_REF: primitives_type := u_PHASER_OUT_PHY + 1;
constant u_PHY_CONTROL: primitives_type := u_PHASER_REF + 1;
constant u_PLLE2_ADV: primitives_type := u_PHY_CONTROL + 1;
constant u_PLLE2_BASE: primitives_type := u_PLLE2_ADV + 1;
constant u_PSS: primitives_type := u_PLLE2_BASE + 1;
constant u_RAMD32: primitives_type := u_PSS + 1;
constant u_RAMD64E: primitives_type := u_RAMD32 + 1;
constant u_RAMS32: primitives_type := u_RAMD64E + 1;
constant u_RAMS64E: primitives_type := u_RAMS32 + 1;
constant u_SIM_CONFIGE2: primitives_type := u_RAMS64E + 1;
constant u_STARTUPE2: primitives_type := u_SIM_CONFIGE2 + 1;
constant u_USR_ACCESSE2: primitives_type := u_STARTUPE2 + 1;
constant u_XADC: primitives_type := u_USR_ACCESSE2 + 1;
constant u_XNOR5: primitives_type := u_XADC + 1;
constant u_XOR5: primitives_type := u_XNOR5 + 1;
constant u_ZHOLD_DELAY: primitives_type := u_XOR5 + 1;
-- Primitives added for OLYMPUS support
constant u_BUFGCE_DIV : primitives_type := u_ZHOLD_DELAY +1;
constant u_BUFCE_ROW : primitives_type := u_BUFGCE_DIV +1;
constant u_BUFCE_LEAF : primitives_type := u_BUFCE_ROW +1;
constant u_MMCME3_ADV : primitives_type := u_BUFCE_LEAF +1;
constant u_MMCME3_BASE : primitives_type := u_MMCME3_ADV +1;
constant u_DNA_PORTE3 : primitives_type := u_MMCME3_BASE +1;
constant u_FRAME_ECCE3 : primitives_type := u_DNA_PORTE3 +1;
constant u_ICAPE3 : primitives_type := u_FRAME_ECCE3 +1;
constant u_JTAG_SIME3 : primitives_type := u_ICAPE3 +1;
constant u_MCAP : primitives_type := u_JTAG_SIME3 +1;
constant u_SIM_CONFIGE3 : primitives_type := u_MCAP +1;
constant u_SYSMONE1 : primitives_type := u_SIM_CONFIGE3 +1;
constant u_CARRY8 : primitives_type := u_SYSMONE1 +1;
constant u_DSP48E2 : primitives_type := u_CARRY8 +1;
constant u_DSP_A_B_DATA : primitives_type := u_DSP48E2 +1;
constant u_DSP_ALU : primitives_type := u_DSP_A_B_DATA +1;
constant u_DSP_C_DATA : primitives_type := u_DSP_ALU +1;
constant u_DSP_M_DATA : primitives_type := u_DSP_C_DATA +1;
constant u_DSP_MULTIPLIER : primitives_type := u_DSP_M_DATA +1;
constant u_DSP_OUTPUT : primitives_type := u_DSP_MULTIPLIER +1;
constant u_DSP_PREADD : primitives_type := u_DSP_OUTPUT +1;
constant u_DSP_PREADD_DATA : primitives_type := u_DSP_PREADD +1;
constant u_FIFO18E2 : primitives_type := u_DSP_PREADD_DATA +1;
constant u_FIFO36E2 : primitives_type := u_FIFO18E2 +1;
constant u_RAMB18E2 : primitives_type := u_FIFO36E2 +1;
constant u_RAMB36E2 : primitives_type := u_RAMB18E2 +1;
constant u_RAM256X1D : primitives_type := u_RAMB36E2 +1;
constant u_RAM512X1S : primitives_type := u_RAM256X1D +1;
constant u_RAM32M16 : primitives_type := u_RAM512X1S +1;
constant u_RAM64M8 : primitives_type := u_RAM32M16 +1;
constant u_SYNC_UNIT : primitives_type := u_RAM64M8 +1;
constant u_BUFG_GT : primitives_type := u_SYNC_UNIT +1;
constant u_GTHE3_CHANNEL : primitives_type := u_BUFG_GT +1;
constant u_GTHE3_COMMON : primitives_type := u_GTHE3_CHANNEL +1;
constant u_GTPE3_CHANNEL : primitives_type := u_GTHE3_COMMON +1;
constant u_GTPE3_COMMON : primitives_type := u_GTPE3_CHANNEL +1;
constant u_GTY : primitives_type := u_GTPE3_COMMON +1;
constant u_GTZE2_OCTAL : primitives_type := u_GTY +1;
constant u_IBUFDS_GTE3 : primitives_type := u_GTZE2_OCTAL +1;
constant u_OBUFDS_GTE3 : primitives_type := u_IBUFDS_GTE3 +1;
constant u_PCIE_3_1 : primitives_type := u_OBUFDS_GTE3 +1;
constant u_IDELAYE3 : primitives_type := u_PCIE_3_1 +1;
constant u_ISERDESE3 : primitives_type := u_IDELAYE3 +1;
constant u_ODELAYE3 : primitives_type := u_ISERDESE3 +1;
constant u_OSERDESE3 : primitives_type := u_ODELAYE3 +1;
constant u_TXPLL : primitives_type := u_OSERDESE3 +1;
constant u_BITSLICE_CONTROL : primitives_type := u_TXPLL +1;
constant u_RX_BITSLICE : primitives_type := u_BITSLICE_CONTROL +1;
constant u_TX_BITSLICE : primitives_type := u_RX_BITSLICE +1;
constant u_IBUFCTRL : primitives_type := u_TX_BITSLICE +1;
constant u_DIFFINBUF : primitives_type := u_IBUFCTRL +1;
constant u_ADDMACC_MACRO : primitives_type := u_DIFFINBUF +1;
constant u_ADDSUB_MACRO : primitives_type := u_ADDMACC_MACRO +1;
constant u_BRAM_SDP_MACRO : primitives_type := u_ADDSUB_MACRO +1;
constant u_BRAM_SINGLE_MACRO : primitives_type := u_BRAM_SDP_MACRO +1;
constant u_BRAM_TDP_MACRO : primitives_type := u_BRAM_SINGLE_MACRO +1;
constant u_COUNTER_LOAD_MACRO : primitives_type := u_BRAM_TDP_MACRO +1;
constant u_COUNTER_TC_MACRO : primitives_type := u_COUNTER_LOAD_MACRO +1;
constant u_EQ_COMPARE_MACRO : primitives_type := u_COUNTER_TC_MACRO +1;
constant u_FIFO_DUALCLOCK_MACRO : primitives_type := u_EQ_COMPARE_MACRO +1;
constant u_FIFO_SYNC_MACRO : primitives_type := u_FIFO_DUALCLOCK_MACRO +1;
constant u_MACC_MACRO : primitives_type := u_FIFO_SYNC_MACRO +1;
constant u_MULT_MACRO : primitives_type := u_MACC_MACRO +1;
constant u_PLLE3_ADV : primitives_type := u_MULT_MACRO +1;
constant u_PLLE3_BASE : primitives_type := u_PLLE3_ADV +1;
constant u_ODDRE1 : primitives_type := u_PLLE3_BASE +1;
constant u_IDDRE1 : primitives_type := u_ODDRE1 +1;
type primitive_array_type is array (natural range <>) of primitives_type;
----------------------------------------------------------------------------
-- Returns true if primitive is available in family.
--
-- Examples:
--
-- supported(virtex2, u_RAMB16_S2) returns true because the RAMB16_S2
-- primitive is available in the
-- virtex2 family.
--
-- supported(spartan3, u_RAM4B_S4) returns false because the RAMB4_S4
-- primitive is not available in the
-- spartan3 family.
----------------------------------------------------------------------------
function supported( family : families_type;
primitive : primitives_type
) return boolean;
----------------------------------------------------------------------------
-- This is an overload of function 'supported' (see above). It allows a list
-- of primitives to be tested.
--
-- Returns true if all of primitives in the list are available in family.
--
-- Example: supported(spartan3, (u_MUXCY, u_XORCY, u_FD))
-- is
-- equivalent to: supported(spartan3, u_MUXCY) and
-- supported(spartan3, u_XORCY) and
-- supported(spartan3, u_FD);
----------------------------------------------------------------------------
function supported( family : families_type;
primitives : primitive_array_type
) return boolean;
----------------------------------------------------------------------------
-- Below, are overloads of function 'supported' that allow the family
-- parameter to be passed as a string. These correspond to the above two
-- functions otherwise.
----------------------------------------------------------------------------
function supported( fam_as_str : string;
primitive : primitives_type
) return boolean;
function supported( fam_as_str : string;
primitives : primitive_array_type
) return boolean;
----------------------------------------------------------------------------
-- Conversions from/to STRING to/from families_type.
-- These are convenience functions that are not normally needed when
-- using the 'supported' functions.
----------------------------------------------------------------------------
function str2fam( fam_as_string : string ) return families_type;
function fam2str( fam : families_type ) return string;
----------------------------------------------------------------------------
-- Function: native_lut_size
--
-- Returns the largest LUT size available in FPGA family, fam.
-- If no LUT is available in fam, then returns zero by default, unless
-- the call specifies a no_lut_return_val, in which case this value
-- is returned.
--
-- The function is available in two overload versions, one for each
-- way of passing the fam argument.
----------------------------------------------------------------------------
function native_lut_size( fam : families_type;
no_lut_return_val : natural := 0
) return natural;
function native_lut_size( fam_as_string : string;
no_lut_return_val : natural := 0
) return natural;
----------------------------------------------------------------------------
-- Function: equalIgnoringCase
--
-- Compare one string against another for equality with case insensitivity.
-- Can be used to test see if a family, C_FAMILY, is equal to some
-- family. However such usage is discouraged. Use instead availability
-- primitive guards based on the function, 'supported', wherever possible.
----------------------------------------------------------------------------
function equalIgnoringCase( str1, str2 : string ) return boolean;
----------------------------------------------------------------------------
-- Function: get_root_family
--
-- This function takes in the string for the desired FPGA family type and
-- returns the root FPGA family type. This is used for derivative part
-- aliasing to the root family.
----------------------------------------------------------------------------
function get_root_family( family_in : string ) return string;
end package family_support;
package body family_support is
type prim_status_type is (
n -- no
, y -- yes
, u -- unknown, not used. However, we use
-- an enumeration to allow for
-- possible future enhancement.
);
type fam_prim_status is array (primitives_type) of prim_status_type;
type fam_has_prim_type is array (families_type) of fam_prim_status;
-- Performance workaround (XST procedure and function handling).
-- The fam_has_prim constant is initialized by an aggregate rather than by the
-- following function. A version of this file with this function not
-- commented was employed in building the aggregate. So, what is below still
-- defines the family-primitive matirix.
--# ----------------------------------------------------------------------------
--# -- This function is used to populate the matrix of family/primitive values.
--# ----------------------------------------------------------------------------
--# ---(
--# function prim_population return fam_has_prim_type is
--# variable pp : fam_has_prim_type := (others => (others => n));
--#
--# procedure set_to( stat : prim_status_type
--# ; fam : families_type
--# ; prim_list : primitive_array_type
--# ) is
--# begin
--# for i in prim_list'range loop
--# pp(fam)(prim_list(i)) := stat;
--# end loop;
--# end set_to;
--#
--# begin
--# set_to(y, virtex, (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGDLL
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_VIRTEX
--# , u_CLKDLL
--# , u_CLKDLLHF
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFG
--# , u_IBUFG_AGP
--# , u_IBUFG_CTT
--# , u_IBUFG_GTL
--# , u_IBUFG_GTLP
--# , u_IBUFG_HSTL_I
--# , u_IBUFG_HSTL_III
--# , u_IBUFG_HSTL_IV
--# , u_IBUFG_LVCMOS2
--# , u_IBUFG_PCI33_3
--# , u_IBUFG_PCI33_5
--# , u_IBUFG_PCI66_3
--# , u_IBUFG_SSTL2_I
--# , u_IBUFG_SSTL2_II
--# , u_IBUFG_SSTL3_I
--# , u_IBUFG_SSTL3_II
--# , u_IBUF_AGP
--# , u_IBUF_CTT
--# , u_IBUF_GTL
--# , u_IBUF_GTLP
--# , u_IBUF_HSTL_I
--# , u_IBUF_HSTL_III
--# , u_IBUF_HSTL_IV
--# , u_IBUF_LVCMOS2
--# , u_IBUF_PCI33_3
--# , u_IBUF_PCI33_5
--# , u_IBUF_PCI66_3
--# , u_IBUF_SSTL2_I
--# , u_IBUF_SSTL2_II
--# , u_IBUF_SSTL3_I
--# , u_IBUF_SSTL3_II
--# , u_INV
--# , u_IOBUF
--# , u_IOBUF_AGP
--# , u_IOBUF_CTT
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_GTL
--# , u_IOBUF_GTLP
--# , u_IOBUF_HSTL_I
--# , u_IOBUF_HSTL_III
--# , u_IOBUF_HSTL_IV
--# , u_IOBUF_LVCMOS2
--# , u_IOBUF_PCI33_3
--# , u_IOBUF_PCI33_5
--# , u_IOBUF_PCI66_3
--# , u_IOBUF_SSTL2_I
--# , u_IOBUF_SSTL2_II
--# , u_IOBUF_SSTL3_I
--# , u_IOBUF_SSTL3_II
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFT
--# , u_OBUFT_AGP
--# , u_OBUFT_CTT
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_GTL
--# , u_OBUFT_GTLP
--# , u_OBUFT_HSTL_I
--# , u_OBUFT_HSTL_III
--# , u_OBUFT_HSTL_IV
--# , u_OBUFT_LVCMOS2
--# , u_OBUFT_PCI33_3
--# , u_OBUFT_PCI33_5
--# , u_OBUFT_PCI66_3
--# , u_OBUFT_SSTL2_I
--# , u_OBUFT_SSTL2_II
--# , u_OBUFT_SSTL3_I
--# , u_OBUFT_SSTL3_II
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_OBUF_AGP
--# , u_OBUF_CTT
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_GTL
--# , u_OBUF_GTLP
--# , u_OBUF_HSTL_I
--# , u_OBUF_HSTL_III
--# , u_OBUF_HSTL_IV
--# , u_OBUF_LVCMOS2
--# , u_OBUF_PCI33_3
--# , u_OBUF_PCI33_5
--# , u_OBUF_PCI66_3
--# , u_OBUF_SSTL2_I
--# , u_OBUF_SSTL2_II
--# , u_OBUF_SSTL3_I
--# , u_OBUF_SSTL3_II
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAMB4_S1
--# , u_RAMB4_S16
--# , u_RAMB4_S16_S16
--# , u_RAMB4_S1_S1
--# , u_RAMB4_S1_S16
--# , u_RAMB4_S1_S2
--# , u_RAMB4_S1_S4
--# , u_RAMB4_S1_S8
--# , u_RAMB4_S2
--# , u_RAMB4_S2_S16
--# , u_RAMB4_S2_S2
--# , u_RAMB4_S2_S4
--# , u_RAMB4_S2_S8
--# , u_RAMB4_S4
--# , u_RAMB4_S4_S16
--# , u_RAMB4_S4_S4
--# , u_RAMB4_S4_S8
--# , u_RAMB4_S8
--# , u_RAMB4_S8_S16
--# , u_RAMB4_S8_S8
--# , u_ROM16X1
--# , u_ROM32X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_STARTBUF_VIRTEX
--# , u_STARTUP_VIRTEX
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# set_to(y, spartan2, (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_SPARTAN2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGDLL
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_SPARTAN2
--# , u_CLKDLL
--# , u_CLKDLLHF
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFG
--# , u_IBUFG_AGP
--# , u_IBUFG_CTT
--# , u_IBUFG_GTL
--# , u_IBUFG_GTLP
--# , u_IBUFG_HSTL_I
--# , u_IBUFG_HSTL_III
--# , u_IBUFG_HSTL_IV
--# , u_IBUFG_LVCMOS2
--# , u_IBUFG_PCI33_3
--# , u_IBUFG_PCI33_5
--# , u_IBUFG_PCI66_3
--# , u_IBUFG_SSTL2_I
--# , u_IBUFG_SSTL2_II
--# , u_IBUFG_SSTL3_I
--# , u_IBUFG_SSTL3_II
--# , u_IBUF_AGP
--# , u_IBUF_CTT
--# , u_IBUF_GTL
--# , u_IBUF_GTLP
--# , u_IBUF_HSTL_I
--# , u_IBUF_HSTL_III
--# , u_IBUF_HSTL_IV
--# , u_IBUF_LVCMOS2
--# , u_IBUF_PCI33_3
--# , u_IBUF_PCI33_5
--# , u_IBUF_PCI66_3
--# , u_IBUF_SSTL2_I
--# , u_IBUF_SSTL2_II
--# , u_IBUF_SSTL3_I
--# , u_IBUF_SSTL3_II
--# , u_INV
--# , u_IOBUF
--# , u_IOBUF_AGP
--# , u_IOBUF_CTT
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_GTL
--# , u_IOBUF_GTLP
--# , u_IOBUF_HSTL_I
--# , u_IOBUF_HSTL_III
--# , u_IOBUF_HSTL_IV
--# , u_IOBUF_LVCMOS2
--# , u_IOBUF_PCI33_3
--# , u_IOBUF_PCI33_5
--# , u_IOBUF_PCI66_3
--# , u_IOBUF_SSTL2_I
--# , u_IOBUF_SSTL2_II
--# , u_IOBUF_SSTL3_I
--# , u_IOBUF_SSTL3_II
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFT
--# , u_OBUFT_AGP
--# , u_OBUFT_CTT
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_GTL
--# , u_OBUFT_GTLP
--# , u_OBUFT_HSTL_I
--# , u_OBUFT_HSTL_III
--# , u_OBUFT_HSTL_IV
--# , u_OBUFT_LVCMOS2
--# , u_OBUFT_PCI33_3
--# , u_OBUFT_PCI33_5
--# , u_OBUFT_PCI66_3
--# , u_OBUFT_SSTL2_I
--# , u_OBUFT_SSTL2_II
--# , u_OBUFT_SSTL3_I
--# , u_OBUFT_SSTL3_II
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_OBUF_AGP
--# , u_OBUF_CTT
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_GTL
--# , u_OBUF_GTLP
--# , u_OBUF_HSTL_I
--# , u_OBUF_HSTL_III
--# , u_OBUF_HSTL_IV
--# , u_OBUF_LVCMOS2
--# , u_OBUF_PCI33_3
--# , u_OBUF_PCI33_5
--# , u_OBUF_PCI66_3
--# , u_OBUF_SSTL2_I
--# , u_OBUF_SSTL2_II
--# , u_OBUF_SSTL3_I
--# , u_OBUF_SSTL3_II
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAMB4_S1
--# , u_RAMB4_S16
--# , u_RAMB4_S16_S16
--# , u_RAMB4_S1_S1
--# , u_RAMB4_S1_S16
--# , u_RAMB4_S1_S2
--# , u_RAMB4_S1_S4
--# , u_RAMB4_S1_S8
--# , u_RAMB4_S2
--# , u_RAMB4_S2_S16
--# , u_RAMB4_S2_S2
--# , u_RAMB4_S2_S4
--# , u_RAMB4_S2_S8
--# , u_RAMB4_S4
--# , u_RAMB4_S4_S16
--# , u_RAMB4_S4_S4
--# , u_RAMB4_S4_S8
--# , u_RAMB4_S8
--# , u_RAMB4_S8_S16
--# , u_RAMB4_S8_S8
--# , u_ROM16X1
--# , u_ROM32X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_STARTBUF_SPARTAN2
--# , u_STARTUP_SPARTAN2
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# set_to(y, spartan2e, (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_SPARTAN2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGDLL
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_SPARTAN2
--# , u_CLKDLL
--# , u_CLKDLLE
--# , u_CLKDLLHF
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFG
--# , u_IBUFG_AGP
--# , u_IBUFG_CTT
--# , u_IBUFG_GTL
--# , u_IBUFG_GTLP
--# , u_IBUFG_HSTL_I
--# , u_IBUFG_HSTL_III
--# , u_IBUFG_HSTL_IV
--# , u_IBUFG_LVCMOS18
--# , u_IBUFG_LVCMOS2
--# , u_IBUFG_LVDS
--# , u_IBUFG_LVPECL
--# , u_IBUFG_PCI33_3
--# , u_IBUFG_PCI66_3
--# , u_IBUFG_PCIX66_3
--# , u_IBUFG_SSTL2_I
--# , u_IBUFG_SSTL2_II
--# , u_IBUFG_SSTL3_I
--# , u_IBUFG_SSTL3_II
--# , u_IBUF_AGP
--# , u_IBUF_CTT
--# , u_IBUF_GTL
--# , u_IBUF_GTLP
--# , u_IBUF_HSTL_I
--# , u_IBUF_HSTL_III
--# , u_IBUF_HSTL_IV
--# , u_IBUF_LVCMOS18
--# , u_IBUF_LVCMOS2
--# , u_IBUF_LVDS
--# , u_IBUF_LVPECL
--# , u_IBUF_PCI33_3
--# , u_IBUF_PCI66_3
--# , u_IBUF_PCIX66_3
--# , u_IBUF_SSTL2_I
--# , u_IBUF_SSTL2_II
--# , u_IBUF_SSTL3_I
--# , u_IBUF_SSTL3_II
--# , u_INV
--# , u_IOBUF
--# , u_IOBUF_AGP
--# , u_IOBUF_CTT
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_GTL
--# , u_IOBUF_GTLP
--# , u_IOBUF_HSTL_I
--# , u_IOBUF_HSTL_III
--# , u_IOBUF_HSTL_IV
--# , u_IOBUF_LVCMOS18
--# , u_IOBUF_LVCMOS2
--# , u_IOBUF_LVDS
--# , u_IOBUF_LVPECL
--# , u_IOBUF_PCI33_3
--# , u_IOBUF_PCI66_3
--# , u_IOBUF_PCIX66_3
--# , u_IOBUF_SSTL2_I
--# , u_IOBUF_SSTL2_II
--# , u_IOBUF_SSTL3_I
--# , u_IOBUF_SSTL3_II
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFT
--# , u_OBUFT_AGP
--# , u_OBUFT_CTT
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_GTL
--# , u_OBUFT_GTLP
--# , u_OBUFT_HSTL_I
--# , u_OBUFT_HSTL_III
--# , u_OBUFT_HSTL_IV
--# , u_OBUFT_LVCMOS18
--# , u_OBUFT_LVCMOS2
--# , u_OBUFT_LVDS
--# , u_OBUFT_LVPECL
--# , u_OBUFT_PCI33_3
--# , u_OBUFT_PCI66_3
--# , u_OBUFT_PCIX66_3
--# , u_OBUFT_SSTL2_I
--# , u_OBUFT_SSTL2_II
--# , u_OBUFT_SSTL3_I
--# , u_OBUFT_SSTL3_II
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_OBUF_AGP
--# , u_OBUF_CTT
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_GTL
--# , u_OBUF_GTLP
--# , u_OBUF_HSTL_I
--# , u_OBUF_HSTL_III
--# , u_OBUF_HSTL_IV
--# , u_OBUF_LVCMOS18
--# , u_OBUF_LVCMOS2
--# , u_OBUF_LVDS
--# , u_OBUF_LVPECL
--# , u_OBUF_PCI33_3
--# , u_OBUF_PCI66_3
--# , u_OBUF_PCIX66_3
--# , u_OBUF_SSTL2_I
--# , u_OBUF_SSTL2_II
--# , u_OBUF_SSTL3_I
--# , u_OBUF_SSTL3_II
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAMB4_S1
--# , u_RAMB4_S16
--# , u_RAMB4_S16_S16
--# , u_RAMB4_S1_S1
--# , u_RAMB4_S1_S16
--# , u_RAMB4_S1_S2
--# , u_RAMB4_S1_S4
--# , u_RAMB4_S1_S8
--# , u_RAMB4_S2
--# , u_RAMB4_S2_S16
--# , u_RAMB4_S2_S2
--# , u_RAMB4_S2_S4
--# , u_RAMB4_S2_S8
--# , u_RAMB4_S4
--# , u_RAMB4_S4_S16
--# , u_RAMB4_S4_S4
--# , u_RAMB4_S4_S8
--# , u_RAMB4_S8
--# , u_RAMB4_S8_S16
--# , u_RAMB4_S8_S8
--# , u_ROM16X1
--# , u_ROM32X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_STARTBUF_SPARTAN2
--# , u_STARTUP_SPARTAN2
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# set_to(y, virtexe, (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGDLL
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_VIRTEX
--# , u_CLKDLL
--# , u_CLKDLLE
--# , u_CLKDLLHF
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFG
--# , u_INV
--# , u_IOBUF
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFT
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAMB4_S1
--# , u_RAMB4_S16
--# , u_RAMB4_S16_S16
--# , u_RAMB4_S1_S1
--# , u_RAMB4_S1_S16
--# , u_RAMB4_S1_S2
--# , u_RAMB4_S1_S4
--# , u_RAMB4_S1_S8
--# , u_RAMB4_S2
--# , u_RAMB4_S2_S16
--# , u_RAMB4_S2_S2
--# , u_RAMB4_S2_S4
--# , u_RAMB4_S2_S8
--# , u_RAMB4_S4
--# , u_RAMB4_S4_S16
--# , u_RAMB4_S4_S4
--# , u_RAMB4_S4_S8
--# , u_RAMB4_S8
--# , u_RAMB4_S8_S16
--# , u_RAMB4_S8_S8
--# , u_ROM16X1
--# , u_ROM32X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_STARTBUF_VIRTEX
--# , u_STARTUP_VIRTEX
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# set_to(y, virtex2, (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGDLL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_VIRTEX2
--# , u_CLKDLL
--# , u_CLKDLLE
--# , u_CLKDLLHF
--# , u_DCM
--# , u_DUMMY_INV
--# , u_DUMMY_NOR2
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_VIRTEX2
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_ORCY
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1S
--# , u_RAM128X1S_1
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM32X1D
--# , u_RAM32X1D_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64X1D
--# , u_RAM64X1D_1
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_STARTBUF_VIRTEX2
--# , u_STARTUP_VIRTEX2
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# pp(qvirtex2) := pp(virtex2);
--# --
--# pp(qrvirtex2) := pp(virtex2);
--# --
--# set_to(y, virtex2p,
--# (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGDLL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_VIRTEX2
--# , u_CLKDLL
--# , u_CLKDLLE
--# , u_CLKDLLHF
--# , u_DCM
--# , u_DUMMY_INV
--# , u_DUMMY_NOR2
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_GT10_10GE_4
--# , u_GT10_10GE_8
--# , u_GT10_10GFC_4
--# , u_GT10_10GFC_8
--# , u_GT10_AURORAX_4
--# , u_GT10_AURORAX_8
--# , u_GT10_AURORA_1
--# , u_GT10_AURORA_2
--# , u_GT10_AURORA_4
--# , u_GT10_CUSTOM
--# , u_GT10_INFINIBAND_1
--# , u_GT10_INFINIBAND_2
--# , u_GT10_INFINIBAND_4
--# , u_GT10_OC192_4
--# , u_GT10_OC192_8
--# , u_GT10_OC48_1
--# , u_GT10_OC48_2
--# , u_GT10_OC48_4
--# , u_GT10_PCI_EXPRESS_1
--# , u_GT10_PCI_EXPRESS_2
--# , u_GT10_PCI_EXPRESS_4
--# , u_GT10_XAUI_1
--# , u_GT10_XAUI_2
--# , u_GT10_XAUI_4
--# , u_GT_AURORA_1
--# , u_GT_AURORA_2
--# , u_GT_AURORA_4
--# , u_GT_CUSTOM
--# , u_GT_ETHERNET_1
--# , u_GT_ETHERNET_2
--# , u_GT_ETHERNET_4
--# , u_GT_FIBRE_CHAN_1
--# , u_GT_FIBRE_CHAN_2
--# , u_GT_FIBRE_CHAN_4
--# , u_GT_INFINIBAND_1
--# , u_GT_INFINIBAND_2
--# , u_GT_INFINIBAND_4
--# , u_GT_XAUI_1
--# , u_GT_XAUI_2
--# , u_GT_XAUI_4
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_VIRTEX2
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_JTAGPPC
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_ORCY
--# , u_PPC405
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1S
--# , u_RAM128X1S_1
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM32X1D
--# , u_RAM32X1D_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64X1D
--# , u_RAM64X1D_1
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_STARTBUF_VIRTEX2
--# , u_STARTUP_VIRTEX2
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# set_to(y, spartan3,
--# (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_SPARTAN3
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGDLL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_CAPTURE_SPARTAN3
--# , u_DCM
--# , u_DUMMY_INV
--# , u_DUMMY_NOR2
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_ORCY
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_STARTBUF_SPARTAN3
--# , u_STARTUP_SPARTAN3
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# pp(aspartan3) := pp(spartan3);
--# --
--# set_to(y, spartan3e,
--# (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_SPARTAN3
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGDLL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_CAPTURE_SPARTAN3E
--# , u_DCM
--# , u_DUMMY_INV
--# , u_DUMMY_NOR2
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_IDDR2
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT18X18SIO
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_ODDR2
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_ORCY
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_STARTBUF_SPARTAN3E
--# , u_STARTUP_SPARTAN3E
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# pp(aspartan3e) := pp(spartan3e);
--# --
--# set_to(y, virtex4fx,
--# (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX4
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGMUX_VIRTEX4
--# , u_BUFGP
--# , u_BUFGP
--# , u_BUFIO
--# , u_BUFR
--# , u_CAPTURE_VIRTEX4
--# , u_DCIRESET
--# , u_DCM
--# , u_DCM_ADV
--# , u_DCM_BASE
--# , u_DCM_PS
--# , u_DSP48
--# , u_EMAC
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FIFO16
--# , u_FMAP
--# , u_FRAME_ECC_VIRTEX4
--# , u_GND
--# , u_GT11CLK
--# , u_GT11CLK_MGT
--# , u_GT11_CUSTOM
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_VIRTEX4
--# , u_IDDR
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_ISERDES
--# , u_JTAGPPC
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_ODDR
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_OSERDES
--# , u_PMCD
--# , u_PPC405
--# , u_PPC405_ADV
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_RAMB32_S64_ECC
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_STARTBUF_VIRTEX4
--# , u_STARTUP_VIRTEX4
--# , u_TOC
--# , u_TOCBUF
--# , u_USR_ACCESS_VIRTEX4
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# pp(virtex4sx) := pp(virtex4fx);
--# --
--# pp(virtex4lx) := pp(virtex4fx);
--# set_to(n, virtex4lx, (u_EMAC,
--# u_GT11CLK, u_GT11CLK_MGT, u_GT11_CUSTOM,
--# u_JTAGPPC, u_PPC405, u_PPC405_ADV
--# ) );
--# --
--# pp(virtex4) := pp(virtex4lx); -- virtex4 is defined as the largest set
--# -- of primitives that EVERY virtex4
--# -- device supports, i.e.. a design that uses
--# -- the virtex4 subset of primitives
--# -- is compatible with any variant of
--# -- the virtex4 family.
--# --
--# pp(qvirtex4) := pp(virtex4);
--# --
--# pp(qrvirtex4) := pp(virtex4);
--# --
--# set_to(y, virtex5,
--# (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX5
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGMUX_CTRL
--# , u_BUFGP
--# , u_BUFIO
--# , u_BUFR
--# , u_CAPTURE_VIRTEX5
--# , u_CARRY4
--# , u_CFGLUT5
--# , u_CRC32
--# , u_CRC64
--# , u_DCIRESET
--# , u_DCM
--# , u_DCM_ADV
--# , u_DCM_BASE
--# , u_DCM_PS
--# , u_DSP48
--# , u_DSP48E
--# , u_EMAC
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FIFO16
--# , u_FIFO18
--# , u_FIFO18_36
--# , u_FIFO36
--# , u_FIFO36_72
--# , u_FMAP
--# , u_FRAME_ECC_VIRTEX5
--# , u_GND
--# , u_GT11CLK
--# , u_GT11CLK_MGT
--# , u_GT11_CUSTOM
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_VIRTEX5
--# , u_IDDR
--# , u_IDDR_2CLK
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IODELAY
--# , u_ISERDES
--# , u_ISERDES_NODELAY
--# , u_KEEPER
--# , u_KEY_CLEAR
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_ODDR
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_OSERDES
--# , u_PLL_ADV
--# , u_PLL_BASE
--# , u_PMCD
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1D
--# , u_RAM128X1S
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM256X1S
--# , u_RAM32M
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64M
--# , u_RAM64X1D
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_RAMB18
--# , u_RAMB18SDP
--# , u_RAMB32_S64_ECC
--# , u_RAMB36
--# , u_RAMB36SDP
--# , u_RAMB36SDP_EXP
--# , u_RAMB36_EXP
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_SRLC32E
--# , u_STARTUP_VIRTEX5
--# , u_SYSMON
--# , u_TOC
--# , u_TOCBUF
--# , u_USR_ACCESS_VIRTEX5
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# pp(spartan3a) := pp(spartan3e); -- Populate spartan3a by taking
--# -- differences from spartan3e.
--# set_to(n, spartan3a, (
--# u_BSCAN_SPARTAN3
--# , u_CAPTURE_SPARTAN3E
--# , u_DUMMY_INV
--# , u_DUMMY_NOR2
--# , u_STARTBUF_SPARTAN3E
--# , u_STARTUP_SPARTAN3E
--# ) );
--# set_to(y, spartan3a, (
--# u_BSCAN_SPARTAN3A
--# , u_CAPTURE_SPARTAN3A
--# , u_DCM_PS
--# , u_DNA_PORT
--# , u_IBUF_DLY_ADJ
--# , u_IBUFDS_DLY_ADJ
--# , u_ICAP_SPARTAN3A
--# , u_RAMB16BWE
--# , u_RAMB16BWE_S18
--# , u_RAMB16BWE_S18_S18
--# , u_RAMB16BWE_S18_S9
--# , u_RAMB16BWE_S36
--# , u_RAMB16BWE_S36_S18
--# , u_RAMB16BWE_S36_S36
--# , u_RAMB16BWE_S36_S9
--# , u_SPI_ACCESS
--# , u_STARTUP_SPARTAN3A
--# ) );
--#
--# --
--# pp(aspartan3a) := pp(spartan3a);
--# --
--# pp(spartan3an) := pp(spartan3a);
--# --
--# pp(spartan3adsp) := pp(spartan3a);
--# set_to(y, spartan3adsp, (
--# u_DSP48A
--# , u_RAMB16BWER
--# ) );
--# --
--# pp(aspartan3adsp) := pp(spartan3adsp);
--# --
--# set_to(y, spartan6, (
--# u_AND2
--# , u_AND2B1L
--# , u_AND3
--# , u_AND4
--# , u_AUTOBUF
--# , u_BSCAN_SPARTAN6
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGDLL
--# , u_BUFGMUX
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFH
--# , u_BUFIO2
--# , u_BUFIO2_2CLK
--# , u_BUFIO2FB
--# , u_BUFIO2FB_2CLK
--# , u_BUFPLL
--# , u_BUFPLL_MCB
--# , u_CAPTURE_SPARTAN3A
--# , u_DCM
--# , u_DCM_CLKGEN
--# , u_DCM_PS
--# , u_DNA_PORT
--# , u_DSP48A1
--# , u_FD
--# , u_FD_1
--# , u_FDC
--# , u_FDC_1
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCP_1
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDP_1
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDR
--# , u_FDR_1
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRS_1
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDS
--# , u_FDS_1
--# , u_FDSE
--# , u_FDSE_1
--# , u_FMAP
--# , u_GND
--# , u_GTPA1_DUAL
--# , u_IBUF
--# , u_IBUF_DLY_ADJ
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFDS_DLY_ADJ
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_SPARTAN3A
--# , u_ICAP_SPARTAN6
--# , u_IDDR2
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IODELAY2
--# , u_IODRP2
--# , u_IODRP2_MCB
--# , u_ISERDES2
--# , u_JTAG_SIM_SPARTAN6
--# , u_KEEPER
--# , u_LD
--# , u_LD_1
--# , u_LDC
--# , u_LDC_1
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCP_1
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDP_1
--# , u_LDPE
--# , u_LDPE_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MCB
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT18X18SIO
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_OCT_CALIBRATE
--# , u_ODDR2
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR2L
--# , u_OR3
--# , u_OR4
--# , u_ORCY
--# , u_OSERDES2
--# , u_PCIE_A1
--# , u_PLL_ADV
--# , u_POST_CRC_INTERNAL
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAMB16BWE
--# , u_RAMB16BWE_S18
--# , u_RAMB16BWE_S18_S18
--# , u_RAMB16BWE_S18_S9
--# , u_RAMB16BWE_S36
--# , u_RAMB16BWE_S36_S18
--# , u_RAMB16BWE_S36_S36
--# , u_RAMB16BWE_S36_S9
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_RAMB8BWER
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SLAVE_SPI
--# , u_SPI_ACCESS
--# , u_SRL16
--# , u_SRL16_1
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRLC16
--# , u_SRLC16_1
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC32E
--# , u_STARTUP_SPARTAN3A
--# , u_STARTUP_SPARTAN6
--# , u_SUSPEND_SYNC
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# ) );
--# --
--# --
--# set_to(y, virtex6, (
--# u_AND2
--# , u_AND2B1L
--# , u_AND3
--# , u_AND4
--# , u_AUTOBUF
--# , u_BSCAN_VIRTEX6
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGMUX_CTRL
--# , u_BUFGP
--# , u_BUFH
--# , u_BUFHCE
--# , u_BUFIO
--# , u_BUFIODQS
--# , u_BUFR
--# , u_CAPTURE_VIRTEX5
--# , u_CAPTURE_VIRTEX6
--# , u_CARRY4
--# , u_CFGLUT5
--# , u_CRC32
--# , u_CRC64
--# , u_DCIRESET
--# , u_DCIRESET
--# , u_DCM
--# , u_DCM_ADV
--# , u_DCM_BASE
--# , u_DCM_PS
--# , u_DSP48
--# , u_DSP48E
--# , u_DSP48E1
--# , u_EFUSE_USR
--# , u_EMAC
--# , u_FD
--# , u_FD_1
--# , u_FDC
--# , u_FDC_1
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCP_1
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDP_1
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDR
--# , u_FDR_1
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRS_1
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDS
--# , u_FDS_1
--# , u_FDSE
--# , u_FDSE_1
--# , u_FIFO16
--# , u_FIFO18
--# , u_FIFO18_36
--# , u_FIFO18E1
--# , u_FIFO36
--# , u_FIFO36_72
--# , u_FIFO36E1
--# , u_FMAP
--# , u_FRAME_ECC_VIRTEX5
--# , u_FRAME_ECC_VIRTEX6
--# , u_GND
--# , u_GT11CLK
--# , u_GT11CLK_MGT
--# , u_GT11_CUSTOM
--# , u_GTXE1
--# , u_IBUF
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFDS_GTXE1
--# , u_IBUFG
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_VIRTEX5
--# , u_ICAP_VIRTEX6
--# , u_IDDR
--# , u_IDDR_2CLK
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IOBUFDS
--# , u_IOBUFDS_DIFF_OUT
--# , u_IODELAY
--# , u_IODELAYE1
--# , u_ISERDES
--# , u_ISERDESE1
--# , u_ISERDES_NODELAY
--# , u_JTAG_SIM_VIRTEX6
--# , u_KEEPER
--# , u_KEY_CLEAR
--# , u_LD
--# , u_LD_1
--# , u_LDC
--# , u_LDC_1
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCP_1
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDP_1
--# , u_LDPE
--# , u_LDPE_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MMCM_ADV
--# , u_MMCM_BASE
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_ODDR
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR2L
--# , u_OR3
--# , u_OR4
--# , u_OSERDES
--# , u_OSERDESE1
--# , u_PCIE_2_0
--# , u_PLL_ADV
--# , u_PLL_BASE
--# , u_PMCD
--# , u_PPR_FRAME
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1D
--# , u_RAM128X1S
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM256X1S
--# , u_RAM32M
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64M
--# , u_RAM64X1D
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_RAMB18
--# , u_RAMB18E1
--# , u_RAMB18SDP
--# , u_RAMB32_S64_ECC
--# , u_RAMB36
--# , u_RAMB36E1
--# , u_RAMB36_EXP
--# , u_RAMB36SDP
--# , u_RAMB36SDP_EXP
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16_1
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRLC16
--# , u_SRLC16_1
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC32E
--# , u_STARTUP_VIRTEX5
--# , u_STARTUP_VIRTEX6
--# , u_SYSMON
--# , u_SYSMON
--# , u_TEMAC_SINGLE
--# , u_TOC
--# , u_TOCBUF
--# , u_USR_ACCESS_VIRTEX5
--# , u_USR_ACCESS_VIRTEX6
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# ) );
--# --
--# pp(spartan6l) := pp(spartan6);
--# --
--# pp(qspartan6) := pp(spartan6);
--# --
--# pp(aspartan6) := pp(spartan6);
--# --
--# pp(virtex6l) := pp(virtex6);
--# --
--# pp(qspartan6l) := pp(spartan6);
--# --
--# pp(qvirtex5) := pp(virtex5);
--# --
--# pp(qvirtex6) := pp(virtex6);
--# --
--# pp(qrvirtex5) := pp(virtex5);
--# --
--# pp(virtex5tx) := pp(virtex5);
--# --
--# pp(virtex5fx) := pp(virtex5);
--# --
--# pp(virtex6cx) := pp(virtex6);
--# --
--# set_to(y, kintex7, (
--# u_AND2
--# , u_AND2B1
--# , u_AND2B1L
--# , u_AND2B2
--# , u_AND3
--# , u_AND3B1
--# , u_AND3B2
--# , u_AND3B3
--# , u_AND4
--# , u_AND4B1
--# , u_AND4B2
--# , u_AND4B3
--# , u_AND4B4
--# , u_AND5
--# , u_AND5B1
--# , u_AND5B2
--# , u_AND5B3
--# , u_AND5B4
--# , u_AND5B5
--# , u_AUTOBUF
--# , u_BSCANE2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFH
--# , u_BUFHCE
--# , u_BUFIO
--# , u_BUFMR
--# , u_BUFMRCE
--# , u_BUFR
--# , u_BUFT
--# , u_CAPTUREE2
--# , u_CARRY4
--# , u_CFGLUT5
--# , u_DCIRESET
--# , u_DNA_PORT
--# , u_DSP48E1
--# , u_EFUSE_USR
--# , u_FD
--# , u_FD_1
--# , u_FDC
--# , u_FDC_1
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCP_1
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDP_1
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDR
--# , u_FDR_1
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRS_1
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDS
--# , u_FDS_1
--# , u_FDSE
--# , u_FDSE_1
--# , u_FIFO18E1
--# , u_FIFO36E1
--# , u_FMAP
--# , u_FRAME_ECCE2
--# , u_GND
--# , u_GTXE2_CHANNEL
--# , u_GTXE2_COMMON
--# , u_IBUF
--# , u_IBUF_DCIEN
--# , u_IBUFDS
--# , u_IBUFDS_BLVDS_25
--# , u_IBUFDS_DCIEN
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFDS_DIFF_OUT_DCIEN
--# , u_IBUFDS_GTE2
--# , u_IBUFDS_LVDS_25
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_BLVDS_25
--# , u_IBUFGDS_DIFF_OUT
--# , u_IBUFGDS_LVDS_25
--# , u_IBUFG_HSTL_I
--# , u_IBUFG_HSTL_I_18
--# , u_IBUFG_HSTL_I_DCI
--# , u_IBUFG_HSTL_I_DCI_18
--# , u_IBUFG_HSTL_II
--# , u_IBUFG_HSTL_II_18
--# , u_IBUFG_HSTL_II_DCI
--# , u_IBUFG_HSTL_II_DCI_18
--# , u_IBUFG_HSTL_III
--# , u_IBUFG_HSTL_III_18
--# , u_IBUFG_HSTL_III_DCI
--# , u_IBUFG_HSTL_III_DCI_18
--# , u_IBUFG_LVCMOS12
--# , u_IBUFG_LVCMOS15
--# , u_IBUFG_LVCMOS18
--# , u_IBUFG_LVCMOS25
--# , u_IBUFG_LVCMOS33
--# , u_IBUFG_LVDCI_15
--# , u_IBUFG_LVDCI_18
--# , u_IBUFG_LVDCI_DV2_15
--# , u_IBUFG_LVDCI_DV2_18
--# , u_IBUFG_LVDS
--# , u_IBUFG_LVPECL
--# , u_IBUFG_LVTTL
--# , u_IBUFG_PCI33_3
--# , u_IBUFG_PCI66_3
--# , u_IBUFG_PCIX66_3
--# , u_IBUFG_SSTL18_I
--# , u_IBUFG_SSTL18_I_DCI
--# , u_IBUFG_SSTL18_II
--# , u_IBUFG_SSTL18_II_DCI
--# , u_IBUF_HSTL_I
--# , u_IBUF_HSTL_I_18
--# , u_IBUF_HSTL_I_DCI
--# , u_IBUF_HSTL_I_DCI_18
--# , u_IBUF_HSTL_II
--# , u_IBUF_HSTL_II_18
--# , u_IBUF_HSTL_II_DCI
--# , u_IBUF_HSTL_II_DCI_18
--# , u_IBUF_HSTL_III
--# , u_IBUF_HSTL_III_18
--# , u_IBUF_HSTL_III_DCI
--# , u_IBUF_HSTL_III_DCI_18
--# , u_IBUF_LVCMOS12
--# , u_IBUF_LVCMOS15
--# , u_IBUF_LVCMOS18
--# , u_IBUF_LVCMOS25
--# , u_IBUF_LVCMOS33
--# , u_IBUF_LVDCI_15
--# , u_IBUF_LVDCI_18
--# , u_IBUF_LVDCI_DV2_15
--# , u_IBUF_LVDCI_DV2_18
--# , u_IBUF_LVDS
--# , u_IBUF_LVPECL
--# , u_IBUF_LVTTL
--# , u_IBUF_PCI33_3
--# , u_IBUF_PCI66_3
--# , u_IBUF_PCIX66_3
--# , u_IBUF_SSTL18_I
--# , u_IBUF_SSTL18_I_DCI
--# , u_IBUF_SSTL18_II
--# , u_IBUF_SSTL18_II_DCI
--# , u_ICAPE2
--# , u_IDDR
--# , u_IDDR_2CLK
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_IDELAYE2
--# , u_IN_FIFO
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IOBUFDS_BLVDS_25
--# , u_IOBUFDS_DIFF_OUT
--# , u_IOBUFDS_DIFF_OUT_DCIEN
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_HSTL_I
--# , u_IOBUF_HSTL_I_18
--# , u_IOBUF_HSTL_II
--# , u_IOBUF_HSTL_II_18
--# , u_IOBUF_HSTL_II_DCI
--# , u_IOBUF_HSTL_II_DCI_18
--# , u_IOBUF_HSTL_III
--# , u_IOBUF_HSTL_III_18
--# , u_IOBUF_LVCMOS12
--# , u_IOBUF_LVCMOS15
--# , u_IOBUF_LVCMOS18
--# , u_IOBUF_LVCMOS25
--# , u_IOBUF_LVCMOS33
--# , u_IOBUF_LVDCI_15
--# , u_IOBUF_LVDCI_18
--# , u_IOBUF_LVDCI_DV2_15
--# , u_IOBUF_LVDCI_DV2_18
--# , u_IOBUF_LVDS
--# , u_IOBUF_LVPECL
--# , u_IOBUF_LVTTL
--# , u_IOBUF_PCI33_3
--# , u_IOBUF_PCI66_3
--# , u_IOBUF_PCIX66_3
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_IOBUF_SSTL18_I
--# , u_IOBUF_SSTL18_II
--# , u_IOBUF_SSTL18_II_DCI
--# , u_IODELAY
--# , u_IODELAYE1
--# , u_ISERDESE2
--# , u_JTAG_SIME2
--# , u_KEEPER
--# , u_LD
--# , u_LD_1
--# , u_LDC
--# , u_LDC_1
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCP_1
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDP_1
--# , u_LDPE
--# , u_LDPE_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_2
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MMCME2_ADV
--# , u_MMCME2_BASE
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND2B1
--# , u_NAND2B2
--# , u_NAND3
--# , u_NAND3B1
--# , u_NAND3B2
--# , u_NAND3B3
--# , u_NAND4
--# , u_NAND4B1
--# , u_NAND4B2
--# , u_NAND4B3
--# , u_NAND4B4
--# , u_NAND5
--# , u_NAND5B1
--# , u_NAND5B2
--# , u_NAND5B3
--# , u_NAND5B4
--# , u_NAND5B5
--# , u_NOR2
--# , u_NOR2B1
--# , u_NOR2B2
--# , u_NOR3
--# , u_NOR3B1
--# , u_NOR3B2
--# , u_NOR3B3
--# , u_NOR4
--# , u_NOR4B1
--# , u_NOR4B2
--# , u_NOR4B3
--# , u_NOR4B4
--# , u_NOR5
--# , u_NOR5B1
--# , u_NOR5B2
--# , u_NOR5B3
--# , u_NOR5B4
--# , u_NOR5B5
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFDS_BLVDS_25
--# , u_OBUFDS_DUAL_BUF
--# , u_OBUFDS_LVDS_25
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_HSTL_I
--# , u_OBUF_HSTL_I_18
--# , u_OBUF_HSTL_I_DCI
--# , u_OBUF_HSTL_I_DCI_18
--# , u_OBUF_HSTL_II
--# , u_OBUF_HSTL_II_18
--# , u_OBUF_HSTL_II_DCI
--# , u_OBUF_HSTL_II_DCI_18
--# , u_OBUF_HSTL_III
--# , u_OBUF_HSTL_III_18
--# , u_OBUF_HSTL_III_DCI
--# , u_OBUF_HSTL_III_DCI_18
--# , u_OBUF_LVCMOS12
--# , u_OBUF_LVCMOS15
--# , u_OBUF_LVCMOS18
--# , u_OBUF_LVCMOS25
--# , u_OBUF_LVCMOS33
--# , u_OBUF_LVDCI_15
--# , u_OBUF_LVDCI_18
--# , u_OBUF_LVDCI_DV2_15
--# , u_OBUF_LVDCI_DV2_18
--# , u_OBUF_LVDS
--# , u_OBUF_LVPECL
--# , u_OBUF_LVTTL
--# , u_OBUF_PCI33_3
--# , u_OBUF_PCI66_3
--# , u_OBUF_PCIX66_3
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OBUF_SSTL18_I
--# , u_OBUF_SSTL18_I_DCI
--# , u_OBUF_SSTL18_II
--# , u_OBUF_SSTL18_II_DCI
--# , u_OBUFT
--# , u_OBUFT_DCIEN
--# , u_OBUFTDS
--# , u_OBUFTDS_BLVDS_25
--# , u_OBUFTDS_DCIEN
--# , u_OBUFTDS_DCIEN_DUAL_BUF
--# , u_OBUFTDS_DUAL_BUF
--# , u_OBUFTDS_LVDS_25
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_HSTL_I
--# , u_OBUFT_HSTL_I_18
--# , u_OBUFT_HSTL_I_DCI
--# , u_OBUFT_HSTL_I_DCI_18
--# , u_OBUFT_HSTL_II
--# , u_OBUFT_HSTL_II_18
--# , u_OBUFT_HSTL_II_DCI
--# , u_OBUFT_HSTL_II_DCI_18
--# , u_OBUFT_HSTL_III
--# , u_OBUFT_HSTL_III_18
--# , u_OBUFT_HSTL_III_DCI
--# , u_OBUFT_HSTL_III_DCI_18
--# , u_OBUFT_LVCMOS12
--# , u_OBUFT_LVCMOS15
--# , u_OBUFT_LVCMOS18
--# , u_OBUFT_LVCMOS25
--# , u_OBUFT_LVCMOS33
--# , u_OBUFT_LVDCI_15
--# , u_OBUFT_LVDCI_18
--# , u_OBUFT_LVDCI_DV2_15
--# , u_OBUFT_LVDCI_DV2_18
--# , u_OBUFT_LVDS
--# , u_OBUFT_LVPECL
--# , u_OBUFT_LVTTL
--# , u_OBUFT_PCI33_3
--# , u_OBUFT_PCI66_3
--# , u_OBUFT_PCIX66_3
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_OBUFT_SSTL18_I
--# , u_OBUFT_SSTL18_I_DCI
--# , u_OBUFT_SSTL18_II
--# , u_OBUFT_SSTL18_II_DCI
--# , u_ODDR
--# , u_ODELAYE2
--# , u_OR2
--# , u_OR2B1
--# , u_OR2B2
--# , u_OR2L
--# , u_OR3
--# , u_OR3B1
--# , u_OR3B2
--# , u_OR3B3
--# , u_OR4
--# , u_OR4B1
--# , u_OR4B2
--# , u_OR4B3
--# , u_OR4B4
--# , u_OR5
--# , u_OR5B1
--# , u_OR5B2
--# , u_OR5B3
--# , u_OR5B4
--# , u_OR5B5
--# , u_OSERDESE2
--# , u_OUT_FIFO
--# , u_PCIE_2_1
--# , u_PHASER_IN
--# , u_PHASER_IN_PHY
--# , u_PHASER_OUT
--# , u_PHASER_OUT_PHY
--# , u_PHASER_REF
--# , u_PHY_CONTROL
--# , u_PLLE2_ADV
--# , u_PLLE2_BASE
--# , u_PSS
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1D
--# , u_RAM128X1S
--# , u_RAM128X1S_1
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM256X1S
--# , u_RAM32M
--# , u_RAM32X1D
--# , u_RAM32X1D_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64M
--# , u_RAM64X1D
--# , u_RAM64X1D_1
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16_S4_S36
--# , u_RAMB18E1
--# , u_RAMB36E1
--# , u_RAMD32
--# , u_RAMD64E
--# , u_RAMS32
--# , u_RAMS64E
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SIM_CONFIGE2
--# , u_SRL16
--# , u_SRL16_1
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRLC16
--# , u_SRLC16_1
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC32E
--# , u_STARTUPE2
--# , u_USR_ACCESSE2
--# , u_VCC
--# , u_XADC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XNOR5
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XOR5
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# , u_ZHOLD_DELAY
--# ) );
--# --
--# set_to(y, virtex7, (
--# u_AND2
--# , u_AND2B1
--# , u_AND2B1L
--# , u_AND2B2
--# , u_AND3
--# , u_AND3B1
--# , u_AND3B2
--# , u_AND3B3
--# , u_AND4
--# , u_AND4B1
--# , u_AND4B2
--# , u_AND4B3
--# , u_AND4B4
--# , u_AND5
--# , u_AND5B1
--# , u_AND5B2
--# , u_AND5B3
--# , u_AND5B4
--# , u_AND5B5
--# , u_AUTOBUF
--# , u_BSCANE2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFH
--# , u_BUFHCE
--# , u_BUFIO
--# , u_BUFMR
--# , u_BUFMRCE
--# , u_BUFR
--# , u_BUFT
--# , u_CAPTUREE2
--# , u_CARRY4
--# , u_CFG_IO_ACCESS
--# , u_CFGLUT5
--# , u_DCIRESET
--# , u_DNA_PORT
--# , u_DSP48E1
--# , u_EFUSE_USR
--# , u_FD
--# , u_FD_1
--# , u_FDC
--# , u_FDC_1
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCP_1
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDP_1
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDR
--# , u_FDR_1
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRS_1
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDS
--# , u_FDS_1
--# , u_FDSE
--# , u_FDSE_1
--# , u_FIFO18E1
--# , u_FIFO36E1
--# , u_FMAP
--# , u_FRAME_ECCE2
--# , u_GND
--# , u_GTXE2_CHANNEL
--# , u_GTXE2_COMMON
--# , u_IBUF
--# , u_IBUF_DCIEN
--# , u_IBUFDS
--# , u_IBUFDS_BLVDS_25
--# , u_IBUFDS_DCIEN
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFDS_DIFF_OUT_DCIEN
--# , u_IBUFDS_GTE2
--# , u_IBUFDS_LVDS_25
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_BLVDS_25
--# , u_IBUFGDS_DIFF_OUT
--# , u_IBUFGDS_LVDS_25
--# , u_IBUFG_HSTL_I
--# , u_IBUFG_HSTL_I_18
--# , u_IBUFG_HSTL_I_DCI
--# , u_IBUFG_HSTL_I_DCI_18
--# , u_IBUFG_HSTL_II
--# , u_IBUFG_HSTL_II_18
--# , u_IBUFG_HSTL_II_DCI
--# , u_IBUFG_HSTL_II_DCI_18
--# , u_IBUFG_HSTL_III
--# , u_IBUFG_HSTL_III_18
--# , u_IBUFG_HSTL_III_DCI
--# , u_IBUFG_HSTL_III_DCI_18
--# , u_IBUFG_LVCMOS12
--# , u_IBUFG_LVCMOS15
--# , u_IBUFG_LVCMOS18
--# , u_IBUFG_LVCMOS25
--# , u_IBUFG_LVCMOS33
--# , u_IBUFG_LVDCI_15
--# , u_IBUFG_LVDCI_18
--# , u_IBUFG_LVDCI_DV2_15
--# , u_IBUFG_LVDCI_DV2_18
--# , u_IBUFG_LVDS
--# , u_IBUFG_LVPECL
--# , u_IBUFG_LVTTL
--# , u_IBUFG_PCI33_3
--# , u_IBUFG_PCI66_3
--# , u_IBUFG_PCIX66_3
--# , u_IBUFG_SSTL18_I
--# , u_IBUFG_SSTL18_I_DCI
--# , u_IBUFG_SSTL18_II
--# , u_IBUFG_SSTL18_II_DCI
--# , u_IBUF_HSTL_I
--# , u_IBUF_HSTL_I_18
--# , u_IBUF_HSTL_I_DCI
--# , u_IBUF_HSTL_I_DCI_18
--# , u_IBUF_HSTL_II
--# , u_IBUF_HSTL_II_18
--# , u_IBUF_HSTL_II_DCI
--# , u_IBUF_HSTL_II_DCI_18
--# , u_IBUF_HSTL_III
--# , u_IBUF_HSTL_III_18
--# , u_IBUF_HSTL_III_DCI
--# , u_IBUF_HSTL_III_DCI_18
--# , u_IBUF_LVCMOS12
--# , u_IBUF_LVCMOS15
--# , u_IBUF_LVCMOS18
--# , u_IBUF_LVCMOS25
--# , u_IBUF_LVCMOS33
--# , u_IBUF_LVDCI_15
--# , u_IBUF_LVDCI_18
--# , u_IBUF_LVDCI_DV2_15
--# , u_IBUF_LVDCI_DV2_18
--# , u_IBUF_LVDS
--# , u_IBUF_LVPECL
--# , u_IBUF_LVTTL
--# , u_IBUF_PCI33_3
--# , u_IBUF_PCI66_3
--# , u_IBUF_PCIX66_3
--# , u_IBUF_SSTL18_I
--# , u_IBUF_SSTL18_I_DCI
--# , u_IBUF_SSTL18_II
--# , u_IBUF_SSTL18_II_DCI
--# , u_ICAPE2
--# , u_IDDR
--# , u_IDDR_2CLK
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_IDELAYE2
--# , u_IN_FIFO
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IOBUFDS_BLVDS_25
--# , u_IOBUFDS_DIFF_OUT
--# , u_IOBUFDS_DIFF_OUT_DCIEN
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_HSTL_I
--# , u_IOBUF_HSTL_I_18
--# , u_IOBUF_HSTL_II
--# , u_IOBUF_HSTL_II_18
--# , u_IOBUF_HSTL_II_DCI
--# , u_IOBUF_HSTL_II_DCI_18
--# , u_IOBUF_HSTL_III
--# , u_IOBUF_HSTL_III_18
--# , u_IOBUF_LVCMOS12
--# , u_IOBUF_LVCMOS15
--# , u_IOBUF_LVCMOS18
--# , u_IOBUF_LVCMOS25
--# , u_IOBUF_LVCMOS33
--# , u_IOBUF_LVDCI_15
--# , u_IOBUF_LVDCI_18
--# , u_IOBUF_LVDCI_DV2_15
--# , u_IOBUF_LVDCI_DV2_18
--# , u_IOBUF_LVDS
--# , u_IOBUF_LVPECL
--# , u_IOBUF_LVTTL
--# , u_IOBUF_PCI33_3
--# , u_IOBUF_PCI66_3
--# , u_IOBUF_PCIX66_3
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_IOBUF_SSTL18_I
--# , u_IOBUF_SSTL18_II
--# , u_IOBUF_SSTL18_II_DCI
--# , u_IODELAY
--# , u_IODELAYE1
--# , u_ISERDESE2
--# , u_JTAG_SIME2
--# , u_KEEPER
--# , u_LD
--# , u_LD_1
--# , u_LDC
--# , u_LDC_1
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCP_1
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDP_1
--# , u_LDPE
--# , u_LDPE_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_2
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MMCME2_ADV
--# , u_MMCME2_BASE
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND2B1
--# , u_NAND2B2
--# , u_NAND3
--# , u_NAND3B1
--# , u_NAND3B2
--# , u_NAND3B3
--# , u_NAND4
--# , u_NAND4B1
--# , u_NAND4B2
--# , u_NAND4B3
--# , u_NAND4B4
--# , u_NAND5
--# , u_NAND5B1
--# , u_NAND5B2
--# , u_NAND5B3
--# , u_NAND5B4
--# , u_NAND5B5
--# , u_NOR2
--# , u_NOR2B1
--# , u_NOR2B2
--# , u_NOR3
--# , u_NOR3B1
--# , u_NOR3B2
--# , u_NOR3B3
--# , u_NOR4
--# , u_NOR4B1
--# , u_NOR4B2
--# , u_NOR4B3
--# , u_NOR4B4
--# , u_NOR5
--# , u_NOR5B1
--# , u_NOR5B2
--# , u_NOR5B3
--# , u_NOR5B4
--# , u_NOR5B5
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFDS_BLVDS_25
--# , u_OBUFDS_DUAL_BUF
--# , u_OBUFDS_LVDS_25
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_HSTL_I
--# , u_OBUF_HSTL_I_18
--# , u_OBUF_HSTL_I_DCI
--# , u_OBUF_HSTL_I_DCI_18
--# , u_OBUF_HSTL_II
--# , u_OBUF_HSTL_II_18
--# , u_OBUF_HSTL_II_DCI
--# , u_OBUF_HSTL_II_DCI_18
--# , u_OBUF_HSTL_III
--# , u_OBUF_HSTL_III_18
--# , u_OBUF_HSTL_III_DCI
--# , u_OBUF_HSTL_III_DCI_18
--# , u_OBUF_LVCMOS12
--# , u_OBUF_LVCMOS15
--# , u_OBUF_LVCMOS18
--# , u_OBUF_LVCMOS25
--# , u_OBUF_LVCMOS33
--# , u_OBUF_LVDCI_15
--# , u_OBUF_LVDCI_18
--# , u_OBUF_LVDCI_DV2_15
--# , u_OBUF_LVDCI_DV2_18
--# , u_OBUF_LVDS
--# , u_OBUF_LVPECL
--# , u_OBUF_LVTTL
--# , u_OBUF_PCI33_3
--# , u_OBUF_PCI66_3
--# , u_OBUF_PCIX66_3
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OBUF_SSTL18_I
--# , u_OBUF_SSTL18_I_DCI
--# , u_OBUF_SSTL18_II
--# , u_OBUF_SSTL18_II_DCI
--# , u_OBUFT
--# , u_OBUFT_DCIEN
--# , u_OBUFTDS
--# , u_OBUFTDS_BLVDS_25
--# , u_OBUFTDS_DCIEN
--# , u_OBUFTDS_DCIEN_DUAL_BUF
--# , u_OBUFTDS_DUAL_BUF
--# , u_OBUFTDS_LVDS_25
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_HSTL_I
--# , u_OBUFT_HSTL_I_18
--# , u_OBUFT_HSTL_I_DCI
--# , u_OBUFT_HSTL_I_DCI_18
--# , u_OBUFT_HSTL_II
--# , u_OBUFT_HSTL_II_18
--# , u_OBUFT_HSTL_II_DCI
--# , u_OBUFT_HSTL_II_DCI_18
--# , u_OBUFT_HSTL_III
--# , u_OBUFT_HSTL_III_18
--# , u_OBUFT_HSTL_III_DCI
--# , u_OBUFT_HSTL_III_DCI_18
--# , u_OBUFT_LVCMOS12
--# , u_OBUFT_LVCMOS15
--# , u_OBUFT_LVCMOS18
--# , u_OBUFT_LVCMOS25
--# , u_OBUFT_LVCMOS33
--# , u_OBUFT_LVDCI_15
--# , u_OBUFT_LVDCI_18
--# , u_OBUFT_LVDCI_DV2_15
--# , u_OBUFT_LVDCI_DV2_18
--# , u_OBUFT_LVDS
--# , u_OBUFT_LVPECL
--# , u_OBUFT_LVTTL
--# , u_OBUFT_PCI33_3
--# , u_OBUFT_PCI66_3
--# , u_OBUFT_PCIX66_3
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_OBUFT_SSTL18_I
--# , u_OBUFT_SSTL18_I_DCI
--# , u_OBUFT_SSTL18_II
--# , u_OBUFT_SSTL18_II_DCI
--# , u_ODDR
--# , u_ODELAYE2
--# , u_OR2
--# , u_OR2B1
--# , u_OR2B2
--# , u_OR2L
--# , u_OR3
--# , u_OR3B1
--# , u_OR3B2
--# , u_OR3B3
--# , u_OR4
--# , u_OR4B1
--# , u_OR4B2
--# , u_OR4B3
--# , u_OR4B4
--# , u_OR5
--# , u_OR5B1
--# , u_OR5B2
--# , u_OR5B3
--# , u_OR5B4
--# , u_OR5B5
--# , u_OSERDESE2
--# , u_OUT_FIFO
--# , u_PCIE_2_1
--# , u_PHASER_IN
--# , u_PHASER_IN_PHY
--# , u_PHASER_OUT
--# , u_PHASER_OUT_PHY
--# , u_PHASER_REF
--# , u_PHY_CONTROL
--# , u_PLLE2_ADV
--# , u_PLLE2_BASE
--# , u_PSS
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1D
--# , u_RAM128X1S
--# , u_RAM128X1S_1
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM256X1S
--# , u_RAM32M
--# , u_RAM32X1D
--# , u_RAM32X1D_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64M
--# , u_RAM64X1D
--# , u_RAM64X1D_1
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16_S4_S36
--# , u_RAMB36E1
--# , u_RAMB36E1
--# , u_RAMD32
--# , u_RAMD64E
--# , u_RAMS32
--# , u_RAMS64E
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SIM_CONFIGE2
--# , u_SRL16
--# , u_SRL16_1
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRLC16
--# , u_SRLC16_1
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC32E
--# , u_STARTUPE2
--# , u_USR_ACCESSE2
--# , u_VCC
--# , u_XADC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XNOR5
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XOR5
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# , u_ZHOLD_DELAY
--# ) );
--# --
--# set_to(y, artix7, (
--# u_AND2
--# , u_AND2B1
--# , u_AND2B1L
--# , u_AND2B2
--# , u_AND3
--# , u_AND3B1
--# , u_AND3B2
--# , u_AND3B3
--# , u_AND4
--# , u_AND4B1
--# , u_AND4B2
--# , u_AND4B3
--# , u_AND4B4
--# , u_AND5
--# , u_AND5B1
--# , u_AND5B2
--# , u_AND5B3
--# , u_AND5B4
--# , u_AND5B5
--# , u_AUTOBUF
--# , u_BSCANE2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFH
--# , u_BUFHCE
--# , u_BUFIO
--# , u_BUFMR
--# , u_BUFMRCE
--# , u_BUFR
--# , u_BUFT
--# , u_CAPTUREE2
--# , u_CARRY4
--# , u_CFGLUT5
--# , u_DCIRESET
--# , u_DNA_PORT
--# , u_DSP48E1
--# , u_EFUSE_USR
--# , u_FD
--# , u_FD_1
--# , u_FDC
--# , u_FDC_1
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCP_1
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDP_1
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDR
--# , u_FDR_1
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRS_1
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDS
--# , u_FDS_1
--# , u_FDSE
--# , u_FDSE_1
--# , u_FIFO18E1
--# , u_FIFO36E1
--# , u_FMAP
--# , u_FRAME_ECCE2
--# , u_GND
--# , u_IBUF
--# , u_IBUF_DCIEN
--# , u_IBUFDS
--# , u_IBUFDS_DCIEN
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFDS_DIFF_OUT_DCIEN
--# , u_IBUFDS_GTE2
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_IBUFG_LVDS
--# , u_IBUFG_LVPECL
--# , u_IBUFG_PCIX66_3
--# , u_IBUF_LVDS
--# , u_IBUF_LVPECL
--# , u_IBUF_PCIX66_3
--# , u_ICAPE2
--# , u_IDDR
--# , u_IDDR_2CLK
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_IDELAYE2
--# , u_IN_FIFO
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IOBUFDS_DIFF_OUT
--# , u_IOBUFDS_DIFF_OUT_DCIEN
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_LVDS
--# , u_IOBUF_LVPECL
--# , u_IOBUF_PCIX66_3
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_IODELAY
--# , u_IODELAYE1
--# , u_ISERDESE2
--# , u_JTAG_SIME2
--# , u_KEEPER
--# , u_LD
--# , u_LD_1
--# , u_LDC
--# , u_LDC_1
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCP_1
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDP_1
--# , u_LDPE
--# , u_LDPE_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_2
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MMCME2_ADV
--# , u_MMCME2_BASE
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND2B1
--# , u_NAND2B2
--# , u_NAND3
--# , u_NAND3B1
--# , u_NAND3B2
--# , u_NAND3B3
--# , u_NAND4
--# , u_NAND4B1
--# , u_NAND4B2
--# , u_NAND4B3
--# , u_NAND4B4
--# , u_NAND5
--# , u_NAND5B1
--# , u_NAND5B2
--# , u_NAND5B3
--# , u_NAND5B4
--# , u_NAND5B5
--# , u_NOR2
--# , u_NOR2B1
--# , u_NOR2B2
--# , u_NOR3
--# , u_NOR3B1
--# , u_NOR3B2
--# , u_NOR3B3
--# , u_NOR4
--# , u_NOR4B1
--# , u_NOR4B2
--# , u_NOR4B3
--# , u_NOR4B4
--# , u_NOR5
--# , u_NOR5B1
--# , u_NOR5B2
--# , u_NOR5B3
--# , u_NOR5B4
--# , u_NOR5B5
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFDS_DUAL_BUF
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_LVDS
--# , u_OBUF_LVPECL
--# , u_OBUF_PCIX66_3
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OBUFT
--# , u_OBUFT_DCIEN
--# , u_OBUFTDS
--# , u_OBUFTDS_DCIEN
--# , u_OBUFTDS_DCIEN_DUAL_BUF
--# , u_OBUFTDS_DUAL_BUF
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_LVDS
--# , u_OBUFT_LVPECL
--# , u_OBUFT_PCIX66_3
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_ODDR
--# , u_ODELAYE2
--# , u_OR2
--# , u_OR2B1
--# , u_OR2B2
--# , u_OR2L
--# , u_OR3
--# , u_OR3B1
--# , u_OR3B2
--# , u_OR3B3
--# , u_OR4
--# , u_OR4B1
--# , u_OR4B2
--# , u_OR4B3
--# , u_OR4B4
--# , u_OR5
--# , u_OR5B1
--# , u_OR5B2
--# , u_OR5B3
--# , u_OR5B4
--# , u_OR5B5
--# , u_OSERDESE2
--# , u_OUT_FIFO
--# , u_PCIE_2_1
--# , u_PHASER_IN
--# , u_PHASER_IN_PHY
--# , u_PHASER_OUT
--# , u_PHASER_OUT_PHY
--# , u_PHASER_REF
--# , u_PHY_CONTROL
--# , u_PLLE2_ADV
--# , u_PLLE2_BASE
--# , u_PSS
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1D
--# , u_RAM128X1S
--# , u_RAM128X1S_1
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM256X1S
--# , u_RAM32M
--# , u_RAM32X1D
--# , u_RAM32X1D_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64M
--# , u_RAM64X1D
--# , u_RAM64X1D_1
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16_S4_S36
--# , u_RAMB18E1
--# , u_RAMB36E1
--# , u_RAMD32
--# , u_RAMD64E
--# , u_RAMS32
--# , u_RAMS64E
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SIM_CONFIGE2
--# , u_SRL16
--# , u_SRL16_1
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRLC16
--# , u_SRLC16_1
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC32E
--# , u_STARTUPE2
--# , u_USR_ACCESSE2
--# , u_VCC
--# , u_XADC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XNOR5
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XOR5
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# , u_ZHOLD_DELAY
--# ) );
--# --
--# return pp;
--# end prim_population;
--# ---)
--#
--#constant fam_has_prim : fam_has_prim_type := prim_population;
constant fam_has_prim : fam_has_prim_type :=
(
nofamily => (
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
kintex7 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n,
y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n,
y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
kintex7l => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n,
y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n,
y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qkintex7 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n,
y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n,
y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qkintex7l => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n,
y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n,
y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex7 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n,
y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n,
y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex7l => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n,
y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n,
y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qvirtex7 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n,
y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n,
y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qvirtex7l => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n,
y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n,
y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
artix7 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n,
n, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n,
y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, n, y, y, y, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y,
n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
aartix7 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n,
n, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n,
y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, n, y, y, y, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y,
n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
artix7l => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n,
n, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n,
y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, n, y, y, y, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y,
n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qartix7 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n,
n, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n,
y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, n, y, y, y, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y,
n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qartix7l => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n,
n, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n,
y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, n, y, y, y, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y,
n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
zynq => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n,
y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n,
y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
azynq => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n,
y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n,
y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qzynq => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n,
y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n,
y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtexu => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n,
y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n,
y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n,
n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, n, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, y, y, y, y, y, y, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y),
kintexu => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n,
y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n,
y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n,
n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, n, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, y, y, y, y, y, y, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y),
artixu => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n,
y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n,
y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n,
n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, n, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, y, y, y, y, y, y, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y)
);
function supported( family : families_type;
primitive : primitives_type
) return boolean is
begin
return fam_has_prim(family)(primitive) = y;
end supported;
function supported( family : families_type;
primitives : primitive_array_type
) return boolean is
begin
for i in primitives'range loop
if fam_has_prim(family)(primitives(i)) /= y then
return false;
end if;
end loop;
return true;
end supported;
----------------------------------------------------------------------------
-- This function is used as alternative to the 'IMAGE attribute, which
-- is not correctly interpretted by some vhdl tools.
----------------------------------------------------------------------------
function myimage (fam_type : families_type) return string is
variable temp : families_type :=fam_type;
begin
case temp is
when nofamily => return "nofamily" ;
when virtexu => return "virtexu" ;
when virtex7 => return "virtex7" ;
when virtex7l => return "virtex7l" ;
when qvirtex7 => return "qvirtex7" ;
when qvirtex7l => return "qvirtex7l" ;
when kintexu => return "kintexu" ;
when kintex7 => return "kintex7" ;
when kintex7l => return "kintex7l" ;
when qkintex7 => return "qkintex7" ;
when qkintex7l => return "qkintex7l" ;
when artixu => return "artixu" ;
when artix7 => return "artix7" ;
when aartix7 => return "aartix7" ;
when artix7l => return "artix7l" ;
when qartix7 => return "qartix7" ;
when qartix7l => return "qartix7l" ;
when zynq => return "zynq" ;
when azynq => return "azynq" ;
when qzynq => return "qzynq" ;
end case;
end myimage;
----------------------------------------------------------------------------
-- Function: get_root_family
--
-- This function takes in the string for the desired FPGA family type and
-- returns the root FPGA family type string. This is used for derivative part
-- aliasing to the root family. This is primarily for fifo_generator and
-- blk_mem_gen calls that need the root family passed to the call.
----------------------------------------------------------------------------
function get_root_family(family_in : string) return string is
begin
-- Virtex7 Root family
if (equalIgnoringCase(family_in, "virtex7" )) Then return "virtex7" ;
Elsif (equalIgnoringCase(family_in, "virtex7l" )) Then return "virtex7" ;
Elsif (equalIgnoringCase(family_in, "qvirtex7" )) Then return "virtex7" ;
Elsif (equalIgnoringCase(family_in, "qvirtex7l" )) Then return "virtex7" ;
-- Kintex7 Root family
Elsif (equalIgnoringCase(family_in, "kintex7" )) Then return "kintex7" ;
Elsif (equalIgnoringCase(family_in, "kintex7l" )) Then return "kintex7" ;
Elsif (equalIgnoringCase(family_in, "qkintex7" )) Then return "kintex7" ;
Elsif (equalIgnoringCase(family_in, "qkintex7l" )) Then return "kintex7" ;
-- artix7 Root family
Elsif (equalIgnoringCase(family_in, "artix7" )) Then return "artix7" ;
Elsif (equalIgnoringCase(family_in, "aartix7" )) Then return "artix7" ;
Elsif (equalIgnoringCase(family_in, "artix7l" )) Then return "artix7" ;
Elsif (equalIgnoringCase(family_in, "qartix7" )) Then return "artix7" ;
Elsif (equalIgnoringCase(family_in, "qartix7l" )) Then return "artix7" ;
-- zynq Root family
Elsif (equalIgnoringCase(family_in, "zynq" )) Then return "zynq" ;
Elsif (equalIgnoringCase(family_in, "azynq" )) Then return "zynq" ;
Elsif (equalIgnoringCase(family_in, "qzynq" )) Then return "zynq" ;
-- KintexU Root family
Elsif (equalIgnoringCase(family_in, "kintexu" )) Then return "kintexu" ;
-- VirtexU Root family
Elsif (equalIgnoringCase(family_in, "virtexu" )) Then return "virtexu" ;
-- artixu Root family
Elsif (equalIgnoringCase(family_in, "artixu" )) Then return "artixu" ;
-- No Match to supported families and derivatives
Else return "nofamily";
End if;
end get_root_family;
function toLowerCaseChar( char : character ) return character is
begin
-- If char is not an upper case letter then return char
if char < 'A' OR char > 'Z' then
return char;
end if;
-- Otherwise map char to its corresponding lower case character and
-- return that
case char is
when 'A' => return 'a';
when 'B' => return 'b';
when 'C' => return 'c';
when 'D' => return 'd';
when 'E' => return 'e';
when 'F' => return 'f';
when 'G' => return 'g';
when 'H' => return 'h';
when 'I' => return 'i';
when 'J' => return 'j';
when 'K' => return 'k';
when 'L' => return 'l';
when 'M' => return 'm';
when 'N' => return 'n';
when 'O' => return 'o';
when 'P' => return 'p';
when 'Q' => return 'q';
when 'R' => return 'r';
when 'S' => return 's';
when 'T' => return 't';
when 'U' => return 'u';
when 'V' => return 'v';
when 'W' => return 'w';
when 'X' => return 'x';
when 'Y' => return 'y';
when 'Z' => return 'z';
when others => return char;
end case;
end toLowerCaseChar;
----------------------------------------------------------------------------
-- Function: equalIgnoringCase
--
-- Compare one string against another for equality with case insensitivity.
-- Can be used to test see if a family, C_FAMILY, is equal to some
-- family. However such usage is discouraged. Use instead availability
-- primitive guards based on the function, 'supported', wherever possible.
----------------------------------------------------------------------------
function equalIgnoringCase( str1, str2 : string ) return boolean is
constant LEN1 : integer := str1'length;
constant LEN2 : integer := str2'length;
variable equal : boolean := TRUE;
begin
if not (LEN1 = LEN2) then
equal := FALSE;
else
for i in str1'range loop
if not (toLowerCaseChar(str1(i)) = toLowerCaseChar(str2(i))) then
equal := FALSE;
end if;
end loop;
end if;
return equal;
end equalIgnoringCase;
----------------------------------------------------------------------------
-- Conversions from/to STRING to/from families_type.
-- These are convenience functions that are not normally needed when
-- using the 'supported' functions.
----------------------------------------------------------------------------
function str2fam( fam_as_string : string ) return families_type is
--
variable fas : string(1 to fam_as_string'length) := fam_as_string;
variable fam : families_type;
--
begin
-- Search for and return the corresponding family.
for fam in families_type'low to families_type'high loop
if equalIgnoringCase(fas, myimage(fam)) then return fam; end if;
end loop;
-- If there is no matching family, report a warning and return nofamily.
assert false
report "Package family_support: Function str2fam called" &
" with string parameter, " & fam_as_string &
", that does not correspond" &
" to a supported family. Returning nofamily."
severity warning;
return nofamily;
end str2fam;
function fam2str( fam : families_type) return string is
begin
--return families_type'IMAGE(fam);
return myimage(fam);
end fam2str;
function supported( fam_as_str : string;
primitive : primitives_type
) return boolean is
begin
return supported(str2fam(fam_as_str), primitive);
end supported;
function supported( fam_as_str : string;
primitives : primitive_array_type
) return boolean is
begin
return supported(str2fam(fam_as_str), primitives);
end supported;
----------------------------------------------------------------------------
-- Function: native_lut_size, two overloads.
----------------------------------------------------------------------------
function native_lut_size( fam : families_type;
no_lut_return_val : natural := 0
) return natural is
begin
if supported(fam, u_LUT6) then return 6;
elsif supported(fam, u_LUT5) then return 5;
elsif supported(fam, u_LUT4) then return 4;
elsif supported(fam, u_LUT3) then return 3;
elsif supported(fam, u_LUT2) then return 2;
elsif supported(fam, u_LUT1) then return 1;
else return no_lut_return_val;
end if;
end;
function native_lut_size( fam_as_string : string;
no_lut_return_val : natural := 0
) return natural is
begin
return native_lut_size( fam => str2fam(fam_as_string),
no_lut_return_val => no_lut_return_val
);
end;
end package body family_support;
| apache-2.0 | 13dcb6527f0b09f0c10fddc01e3256e5 | 0.320134 | 3.089687 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/ipif_steer128.vhd | 15 | 44,922 | --SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: ipif_steer128.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- IPIF_Steer128 - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ipif_steer128.vhd
-- Version: v1.00b
-- Description: Read and Write Steering logic for IPIF
--
-- For writes, this logic steers data from the correct byte
-- lane to IPIF devices which may be smaller than the bus
-- width. The BE signals are also steered if the BE_Steer
-- signal is asserted, which indicates that the address space
-- being accessed has a smaller maximum data transfer size
-- than the bus size.
--
-- For writes, the Decode_size signal determines how read
-- data is steered onto the byte lanes. To simplify the
-- logic, the read data is mirrored onto the entire data
-- bus, insuring that the lanes corrsponding to the BE's
-- have correct data.
--
--
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ipif_steer128.vhd
--
-------------------------------------------------------------------------------
-- Author: BLT
-- History:
-- BLT 2-5-2002 -- First version
-- ^^^^^^
-- First version of IPIF steering logic.
-- ~~~~~~
-- BLT 2-12-2002 -- Removed BE_Steer, now generated internally
--
-- DET 2-24-2002 -- Added 'When others' to size case statement
-- in BE_STEER_PROC process.
--
-- BLT 10-10-2002 -- Rewrote to get around some XST synthesis
-- issues.
--
-- BLT 11-18-2002 -- Added addr_bits to sensitivity lists to
-- fix simulation bug
--
-- GAB 06-27-2005
-- ~~~~~~
-- Modified to support C_DWIDTH=128
-- Added second Decode_size input to reduce fanout for 128-bit cases
-- Renamed to ipif_steer128.vhd
-- ^^^^^^
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Port declarations
-- generic definitions:
-- C_DWIDTH : integer := width of host databus attached to the IPIF
-- C_SMALLEST : integer := width of smallest device (not access size)
-- attached to the IPIF
-- C_AWIDTH : integer := width of the host address bus attached to
-- the IPIF
-- port definitions:
-- Wr_Data_In : in Write Data In (from host data bus)
-- Rd_Data_In : in Read Data In (from IPIC data bus)
-- Addr : in Address bus from host address bus
-- BE_In : in Byte Enables In from host side
-- Decode_size : in Size of MAXIMUM data access allowed to
-- a particular address map decode.
--
-- Size indication (Decode_size)
-- 001 - byte
-- 010 - halfword
-- 011 - word
-- 100 - doubleword
-- 101 - 128-b
-- 110 - 256-b
-- 111 - 512-b
-- num_bytes = 2^(n-1)
--
-- Wr_Data_Out : out Write Data Out (to IPIF data bus)
-- Rd_Data_Out : out Read Data Out (to host data bus)
-- BE_Out : out Byte Enables Out to IPIF side
--
-------------------------------------------------------------------------------
entity ipif_steer128 is
generic (
C_DWIDTH : integer := 32; -- 8, 16, 32, 64, 128
C_SMALLEST : integer := 32; -- 8, 16, 32, 64, 128
C_AWIDTH : integer := 32
);
port (
Wr_Data_In : in std_logic_vector(0 to C_DWIDTH-1);
Rd_Data_In : in std_logic_vector(0 to C_DWIDTH-1);
Addr : in std_logic_vector(0 to C_AWIDTH-1);
BE_In : in std_logic_vector(0 to C_DWIDTH/8-1);
Decode_size1 : in std_logic_vector(0 to 2);
Decode_size2 : in std_logic_vector(0 to 2);
Wr_Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
Rd_Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
BE_Out : out std_logic_vector(0 to C_DWIDTH/8-1)
);
end entity ipif_steer128;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of ipif_steer128 is
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-----------------------------------------------------------------------------
-- OPB Data Muxing and Steering
-----------------------------------------------------------------------------
-- GEN_DWIDTH_SMALLEST
GEN_SAME: if C_DWIDTH = C_SMALLEST generate
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
end generate GEN_SAME;
GEN_16_8: if C_DWIDTH = 16 and C_SMALLEST = 8 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size1)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-1);
case addr_bits is
when '1' =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(8 to 15);
case Decode_size1 is
when "001" => --B
BE_Out(0) <= BE_In(1);
BE_Out(1) <= '0';
Rd_Data_Out(8 to 15) <= Rd_Data_In(0 to 7);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_16_8;
GEN_32_8: if C_DWIDTH = 32 and C_SMALLEST = 8 generate
signal addr_bits : std_logic_vector(0 to 1);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size1)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-2 to C_AWIDTH-1); --a30 to a31
case addr_bits is
when "01" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(8 to 15);
case Decode_size1 is
when "001" => --B
BE_Out(0) <= BE_In(1);
BE_Out(1 to 3) <= (others => '0');
Rd_Data_Out(8 to 15) <= Rd_Data_In(0 to 7);
when "010" => --HW
Rd_Data_Out(8 to 15) <= Rd_Data_In(8 to 15);
when others => null;
end case;
when "10" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(2);
BE_Out(1 to 3) <= (others => '0');
Rd_Data_Out(16 to 23) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 3) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "11" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(24 to 31);
Wr_Data_Out(8 to 15) <= Wr_Data_In(24 to 31);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(3);
BE_Out(1 to 3) <= (others => '0');
Rd_Data_Out(24 to 31) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(1) <= BE_In(3);
BE_Out(2 to 3) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_32_8;
GEN_32_16: if C_DWIDTH = 32 and C_SMALLEST = 16 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size1)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-2); --a30
case addr_bits is
when '1' =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size1 is
when "010" => --HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 3) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_32_16;
GEN_64_8: if C_DWIDTH = 64 and C_SMALLEST = 8 generate
signal addr_bits : std_logic_vector(0 to 2);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size1,Decode_size2)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-3 to C_AWIDTH-1); --a29 to a31
case addr_bits is
when "001" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(8 to 15);
case Decode_size1 is
when "001" => --B
BE_Out(0) <= BE_In(1);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(8 to 15) <= Rd_Data_In(0 to 7);
when others => null;
end case;
when "010" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(2);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(16 to 23) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "011" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(24 to 31);
Wr_Data_Out(8 to 15) <= Wr_Data_In(24 to 31);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(3);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(24 to 31) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 7) <= (others => '0');
-- Rd_Data_Out(24 to 31) <= Rd_Data_In(8 to 15);
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "100" =>
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(4);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(32 to 39) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "101" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(40 to 47);
Wr_Data_Out(8 to 15) <= Wr_Data_In(40 to 47);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(5);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(40 to 47) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "110" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(48 to 63);
Wr_Data_Out(16 to 31) <= Wr_Data_In(48 to 63);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(6);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(48 to 55) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "111" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(56 to 63);
Wr_Data_Out(8 to 15) <= Wr_Data_In(56 to 63);
Wr_Data_Out(24 to 31) <= Wr_Data_In(56 to 63);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(7);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(56 to 63) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_64_8;
GEN_64_16: if C_DWIDTH = 64 and C_SMALLEST = 16 generate
signal addr_bits : std_logic_vector(0 to 1);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size1,Decode_size2)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-3 to C_AWIDTH-2); --a29 to a30
case addr_bits is
when "01" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size1 is
when "010" => --HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "10" =>
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size1 is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "11" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(48 to 63);
Wr_Data_Out(16 to 31) <= Wr_Data_In(48 to 63);
case Decode_size2 is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_64_16;
GEN_64_32: if C_DWIDTH = 64 and C_SMALLEST = 32 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size1)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-3); --a29
case addr_bits is
when '1' =>
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size1 is
when "011" =>
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_64_32;
---------------------
-- 128 Bit Support --
---------------------
GEN_128_8: if C_DWIDTH = 128 and C_SMALLEST = 8 generate
signal addr_bits : std_logic_vector(0 to 3);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,
Decode_size1,Decode_size2)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-4 to C_AWIDTH-1);
case addr_bits is
when "0001" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(8 to 15);
case Decode_size1 is
when "001" => --B
BE_Out(0) <= BE_In(1);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(8 to 15) <= Rd_Data_In(0 to 7);
when others => null;
end case;
when "0010" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(2);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(16 to 23) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "0011" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(24 to 31);
Wr_Data_Out(8 to 15) <= Wr_Data_In(24 to 31);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(3);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(24 to 31) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "0100" =>
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(4);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(32 to 39) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "0101" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(40 to 47);
Wr_Data_Out(8 to 15) <= Wr_Data_In(40 to 47);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(5);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(40 to 47) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "0110" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(48 to 63);
Wr_Data_Out(16 to 31) <= Wr_Data_In(48 to 63);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(6);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(48 to 55) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "0111" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(56 to 63);
Wr_Data_Out(8 to 15) <= Wr_Data_In(56 to 63);
Wr_Data_Out(24 to 31) <= Wr_Data_In(56 to 63);
case Decode_size1 is
when "001" => -- B
BE_Out(0) <= BE_In(7);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(56 to 63) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "1000" =>
Wr_Data_Out(0 to 63) <= Wr_Data_In(64 to 127);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(8);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(64 to 71) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(8 to 9);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(64 to 79) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(8 to 11);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(64 to 95) <= Rd_Data_In(0 to 31);
when "100" => -- DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "1001" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(72 to 79);
Wr_Data_Out(8 to 15) <= Wr_Data_In(72 to 79);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(9);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(72 to 79) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(8 to 9);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(64 to 79) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(8 to 11);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(64 to 95) <= Rd_Data_In(0 to 31);
when "100" => -- DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "1010" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(80 to 95);
Wr_Data_Out(16 to 31) <= Wr_Data_In(80 to 95);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(10);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(80 to 87) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(10 to 11);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(80 to 95) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(8 to 11);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(64 to 95) <= Rd_Data_In(0 to 31);
when "100" => -- DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "1011" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(88 to 95);
Wr_Data_Out(8 to 15) <= Wr_Data_In(88 to 95);
Wr_Data_Out(24 to 31) <= Wr_Data_In(88 to 95);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(11);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(88 to 95) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(10 to 11);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(80 to 95) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(8 to 11);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(64 to 95) <= Rd_Data_In(0 to 31);
when "100" => -- DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "1100" =>
Wr_Data_Out(0 to 31) <= Wr_Data_In(96 to 127);
Wr_Data_Out(32 to 63) <= Wr_Data_In(96 to 127);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(12);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(96 to 103) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(12 to 13);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(96 to 111) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(12 to 15);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(96 to 127) <= Rd_Data_In(0 to 31);
when "100" => -- DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "1101" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(104 to 111);
Wr_Data_Out(8 to 15) <= Wr_Data_In(104 to 111);
Wr_Data_Out(40 to 47) <= Wr_Data_In(104 to 111);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(13);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(104 to 111) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(12 to 13);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(96 to 111) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(12 to 15);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(96 to 127) <= Rd_Data_In(0 to 31);
when "100" => -- DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "1110" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(112 to 127);
Wr_Data_Out(16 to 31) <= Wr_Data_In(112 to 127);
Wr_Data_Out(48 to 63) <= Wr_Data_In(112 to 127);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(14);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(112 to 119) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(14 to 15);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(112 to 127) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(12 to 15);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(96 to 127) <= Rd_Data_In(0 to 31);
when "100" => -- DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "1111" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(120 to 127);
Wr_Data_Out(8 to 15) <= Wr_Data_In(120 to 127);
Wr_Data_Out(24 to 31) <= Wr_Data_In(120 to 127);
Wr_Data_Out(56 to 63) <= Wr_Data_In(120 to 127);
case Decode_size2 is
when "001" => -- B
BE_Out(0) <= BE_In(15);
BE_Out(1 to 15) <= (others => '0');
Rd_Data_Out(120 to 127) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(14 to 15);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(112 to 127) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(12 to 15);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(96 to 127) <= Rd_Data_In(0 to 31);
when "100" => -- DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_128_8;
GEN_128_16: if C_DWIDTH = 128 and C_SMALLEST = 16 generate
signal addr_bits : std_logic_vector(0 to 2);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,
Decode_size1,Decode_size2)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-4 to C_AWIDTH-2);
case addr_bits is
when "001" => --2
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size1 is
when "010" => --HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "010" => --4
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size1 is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "011" => --6
Wr_Data_Out(0 to 15) <= Wr_Data_In(48 to 63);
Wr_Data_Out(16 to 31) <= Wr_Data_In(48 to 63);
case Decode_size1 is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "100" => --8
Wr_Data_Out(0 to 63) <= Wr_Data_In(64 to 127);
case Decode_size2 is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(8 to 9);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(64 to 79) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(8 to 11);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(64 to 95) <= Rd_Data_In(0 to 31);
when "100" => --DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "101" => --A
Wr_Data_Out(0 to 15) <= Wr_Data_In(80 to 95);
Wr_Data_Out(16 to 31) <= Wr_Data_In(80 to 95);
case Decode_size2 is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(10 to 11);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(80 to 95) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(8 to 11);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(64 to 95) <= Rd_Data_In(0 to 31);
when "100" => --DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "110" => --C
Wr_Data_Out(0 to 31) <= Wr_Data_In(96 to 127);
Wr_Data_Out(32 to 63) <= Wr_Data_In(96 to 127);
case Decode_size2 is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(12 to 13);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(96 to 111) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(12 to 15);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(96 to 127) <= Rd_Data_In(0 to 31);
when "100" => --DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "111" => --E
Wr_Data_Out(0 to 15) <= Wr_Data_In(112 to 127);
Wr_Data_Out(16 to 31) <= Wr_Data_In(112 to 127);
Wr_Data_Out(48 to 63) <= Wr_Data_In(112 to 127);
case Decode_size2 is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(14 to 15);
BE_Out(2 to 15) <= (others => '0');
Rd_Data_Out(112 to 127) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(12 to 15);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(96 to 127) <= Rd_Data_In(0 to 31);
when "100" => --DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_128_16;
GEN_128_32: if C_DWIDTH = 128 and C_SMALLEST = 32 generate
signal addr_bits : std_logic_vector(0 to 1);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,
Decode_size1,Decode_size2)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-4 to C_AWIDTH-3);
case addr_bits is
when "01" => --4
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size1 is
when "011" => --FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "10" => --8
Wr_Data_Out(0 to 63) <= Wr_Data_In(64 to 127);
case Decode_size1 is
when "011" => --FW
BE_Out(0 to 3) <= BE_In(8 to 11);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(64 to 95) <= Rd_Data_In(0 to 31);
when "100" => --DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when "11" => --C
Wr_Data_Out(0 to 31) <= Wr_Data_In(96 to 127);
Wr_Data_Out(32 to 63) <= Wr_Data_In(96 to 127);
case Decode_size2 is
when "011" => --FW
BE_Out(0 to 3) <= BE_In(12 to 15);
BE_Out(4 to 15) <= (others => '0');
Rd_Data_Out(96 to 127) <= Rd_Data_In(0 to 31);
when "100" => --DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_128_32;
GEN_128_64: if C_DWIDTH = 128 and C_SMALLEST = 64 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size1)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-4);
case addr_bits is
when '1' => --8
Wr_Data_Out(0 to 63) <= Wr_Data_In(64 to 127);
case Decode_size1 is
when "100" => --DW
BE_Out(0 to 7) <= BE_In(8 to 15);
BE_Out(8 to 15) <= (others => '0');
Rd_Data_Out(64 to 127) <= Rd_Data_In(0 to 63);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_128_64;
-- Size indication (Decode_size)
-- n = 001 byte 2^0
-- n = 010 halfword 2^1
-- n = 011 word 2^2
-- n = 100 doubleword 2^3
-- n = 101 128-b
-- n = 110 256-b
-- n = 111 512-b
-- num_bytes = 2^(n-1)
end architecture IMP;
| apache-2.0 | 72ce2d4c4f7693275c91da2ca16eb77c | 0.414719 | 3.482596 | false | false | false | false |
marceloboeira/vhdl-examples | 008-state-machine-calculator/_example/meu_proj_topo.vhd | 1 | 2,195 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:06:32 05/14/2014
-- Design Name:
-- Module Name: meu_proj_topo - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity meu_proj_topo is
Port ( clock : in STD_LOGIC;
bot0 : in STD_LOGIC;
bot1 : in STD_LOGIC;
sw7 : in STD_LOGIC;
sw6 : in STD_LOGIC;
sw5 : in STD_LOGIC;
botao_modo : in STD_LOGIC;
reset : in STD_LOGIC;
-- led : out std_logic;
disp_sel_o : out STD_LOGIC_VECTOR (3 downto 0);
display : out STD_LOGIC_VECTOR (7 downto 0));
end meu_proj_topo;
architecture Behavioral of meu_proj_topo is
signal botao_DB0,botao_DB1 : std_logic;
signal saida_display : STD_LOGIC_VECTOR (15 downto 0);
begin
arquivo_topo : entity work.calc_avancada
port map ( clock => clock,
reset => reset,
bot0 => botao_DB0,
bot1 => botao_DB1,
sw7 => sw7,
sw6 => sw6,
sw5 => sw5,
saida_display => saida_display);
debouce_n1 :entity work.debounce
port map ( clock => clock,
entrada => bot1,
saida_DB => botao_DB1);
debouce_n0 :entity work.debounce
port map ( clock => clock,
entrada => bot0,
saida_DB => botao_DB0);
display_1 : entity work.display_topo
Port Map ( clock => clock,
reset => reset,
display_mode => botao_modo,
display_in => saida_display,
disp_sel => disp_sel_o,
display_out => display );
end Behavioral;
| mit | 9a78dfe8bb6ec39b4d122df296d97413 | 0.548064 | 3.440439 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/LEKO_LEKU/leku/LEKU-CD'/25_8.vhd | 1 | 60,949 | Library IEEE;
use IEEE.std_logic_1164.all;
entity x25_8x is
Port (
A302,A301,A300,A299,A298,A269,A268,A267,A266,A265,A236,A235,A234,A233,A232,A203,A202,A201,A200,A199,A166,A167,A168,A169,A170: in std_logic;
A107: buffer std_logic
);
end x25_8x;
architecture x25_8x_behav of x25_8x is
signal a1a,a2a,a3a,a4a,a5a,a6a,a7a,a8a,a9a,a10a,a11a,a12a,a13a,a14a,a15a,a16a,a17a,a18a,a19a,a20a,a21a,a22a,a23a,a24a,a25a,a26a,a27a,a28a,a29a,a30a,a31a,a32a,a33a,a34a,a35a,a36a,a37a,a38a,a39a,a40a,a41a,a42a,a43a,a44a,a45a,a46a,a47a,a48a,a49a,a50a,a51a,a52a,a53a,a54a,a55a,a56a,a57a,a58a,a59a,a60a,a61a,a62a,a63a,a64a,a65a,a66a,a67a,a68a,a69a,a70a,a71a,a72a,a73a,a74a,a75a,a76a,a77a,a78a,a79a,a80a,a81a,a82a,a83a,a84a,a85a,a86a,a87a,a88a,a89a,a90a,a91a,a92a,a93a,a94a,a95a,a96a,a97a,a98a,a99a,a100a,a101a,a102a,a103a,a104a,a105a,a106a,a107a,a108a,a109a,a110a,a111a,a112a,a113a,a114a,a115a,a116a,a117a,a118a,a119a,a120a,a121a,a122a,a123a,a124a,a125a,a126a,a127a,a128a,a129a,a130a,a131a,a132a,a133a,a134a,a135a,a136a,a137a,a138a,a139a,a140a,a141a,a142a,a143a,a144a,a145a,a146a,a147a,a148a,a149a,a150a,a151a,a152a,a153a,a154a,a155a,a156a,a157a,a158a,a159a,a160a,a161a,a162a,a163a,a164a,a165a,a168a,a172a,a173a,a174a,a177a,a181a,a182a,a183a,a184a,a187a,a191a,a192a,a193a,a196a,a200a,a201a,a202a,a203a,a204a,a207a,a211a,a212a,a213a,a216a,a220a,a221a,a222a,a223a,a226a,a230a,a231a,a232a,a236a,a237a,a241a,a242a,a243a,a244a,a245a,a246a,a249a,a253a,a254a,a255a,a258a,a262a,a263a,a264a,a265a,a268a,a272a,a273a,a274a,a277a,a281a,a282a,a283a,a284a,a285a,a288a,a292a,a293a,a294a,a297a,a301a,a302a,a303a,a304a,a307a,a311a,a312a,a313a,a317a,a318a,a322a,a323a,a324a,a325a,a326a,a327a,a328a,a331a,a335a,a336a,a337a,a340a,a344a,a345a,a346a,a347a,a350a,a354a,a355a,a356a,a359a,a363a,a364a,a365a,a366a,a367a,a370a,a374a,a375a,a376a,a379a,a383a,a384a,a385a,a386a,a389a,a393a,a394a,a395a,a399a,a400a,a404a,a405a,a406a,a407a,a408a,a409a,a412a,a416a,a417a,a418a,a421a,a425a,a426a,a427a,a428a,a431a,a435a,a436a,a437a,a441a,a442a,a446a,a447a,a448a,a449a,a450a,a453a,a457a,a458a,a459a,a462a,a466a,a467a,a468a,a469a,a472a,a476a,a477a,a478a,a482a,a483a,a487a,a488a,a489a,a490a,a491a,a492a,a493a,a498a,a501a,a504a,a507a,a510a,a513a,a516a,a519a,a522a,a525a,a529a,a530a,a534a,a535a,a539a,a540a,a544a,a545a,a549a,a550a,a554a,a555a,a559a,a560a,a564a,a565a,a569a,a570a,a574a,a575a,a579a,a580a,a584a,a585a,a589a,a590a,a594a,a595a,a599a,a600a,a604a,a605a,a609a,a610a,a614a,a615a,a619a,a620a,a624a,a625a,a629a,a630a,a634a,a635a,a639a,a640a,a644a,a645a,a649a,a650a,a654a,a655a,a659a,a660a,a664a,a665a,a669a,a670a,a674a,a675a,a679a,a680a,a684a,a685a,a689a,a690a,a694a,a695a,a699a,a700a,a704a,a705a,a709a,a710a,a713a,a716a,a717a,a721a,a722a,a725a,a728a,a729a,a733a,a734a,a737a,a740a,a741a,a745a,a746a,a749a,a752a,a753a,a757a,a758a,a761a,a764a,a765a,a769a,a770a,a773a,a776a,a777a,a780a,a783a,a784a,a787a,a790a,a791a,a794a,a797a,a798a,a801a,a804a,a805a,a808a,a811a,a812a,a815a,a818a,a819a,a822a,a825a,a826a,a829a,a832a,a833a,a836a,a839a,a840a,a843a,a846a,a847a,a850a,a853a,a854a,a857a,a860a,a861a,a864a,a867a,a868a,a871a,a874a,a875a,a878a,a881a,a882a,a885a,a888a,a889a,a892a,a895a,a896a,a899a,a902a,a903a,a906a,a909a,a910a,a913a,a916a,a917a,a920a,a923a,a924a,a927a,a930a,a931a,a934a,a937a,a938a,a941a,a944a,a945a,a948a,a951a,a952a,a955a,a958a,a959a,a962a,a965a,a966a,a969a,a972a,a973a,a976a,a979a,a980a,a983a,a986a,a987a,a990a,a993a,a994a,a997a,a1000a,a1001a,a1004a,a1007a,a1008a,a1011a,a1014a,a1015a,a1018a,a1021a,a1022a,a1025a,a1028a,a1029a,a1032a,a1035a,a1036a,a1039a,a1042a,a1043a,a1046a,a1049a,a1050a,a1053a,a1056a,a1057a,a1060a,a1063a,a1064a,a1067a,a1070a,a1071a,a1074a,a1077a,a1078a,a1081a,a1084a,a1085a,a1088a,a1091a,a1092a,a1095a,a1098a,a1099a,a1102a,a1105a,a1106a,a1109a,a1112a,a1113a,a1116a,a1119a,a1120a,a1123a,a1126a,a1127a,a1130a,a1133a,a1134a,a1137a,a1140a,a1141a,a1144a,a1147a,a1148a,a1151a,a1154a,a1155a,a1158a,a1161a,a1162a,a1165a,a1168a,a1169a,a1172a,a1175a,a1176a,a1179a,a1182a,a1183a,a1186a,a1189a,a1190a,a1193a,a1196a,a1197a,a1200a,a1203a,a1204a,a1207a,a1210a,a1211a,a1214a,a1217a,a1218a,a1221a,a1224a,a1225a,a1228a,a1231a,a1232a,a1235a,a1238a,a1239a,a1242a,a1245a,a1246a,a1249a,a1252a,a1253a,a1256a,a1259a,a1260a,a1263a,a1266a,a1267a,a1270a,a1273a,a1274a,a1277a,a1280a,a1281a,a1284a,a1287a,a1288a,a1291a,a1294a,a1295a,a1298a,a1301a,a1302a,a1305a,a1308a,a1309a,a1312a,a1315a,a1316a,a1319a,a1322a,a1323a,a1326a,a1329a,a1330a,a1333a,a1337a,a1338a,a1339a,a1342a,a1345a,a1346a,a1349a,a1353a,a1354a,a1355a,a1358a,a1361a,a1362a,a1365a,a1369a,a1370a,a1371a,a1374a,a1377a,a1378a,a1381a,a1385a,a1386a,a1387a,a1390a,a1393a,a1394a,a1397a,a1401a,a1402a,a1403a,a1406a,a1409a,a1410a,a1413a,a1417a,a1418a,a1419a,a1422a,a1425a,a1426a,a1429a,a1433a,a1434a,a1435a,a1438a,a1441a,a1442a,a1445a,a1449a,a1450a,a1451a,a1454a,a1457a,a1458a,a1461a,a1465a,a1466a,a1467a,a1470a,a1473a,a1474a,a1477a,a1481a,a1482a,a1483a,a1486a,a1489a,a1490a,a1493a,a1497a,a1498a,a1499a,a1502a,a1505a,a1506a,a1509a,a1513a,a1514a,a1515a,a1518a,a1521a,a1522a,a1525a,a1529a,a1530a,a1531a,a1534a,a1537a,a1538a,a1541a,a1545a,a1546a,a1547a,a1550a,a1553a,a1554a,a1557a,a1561a,a1562a,a1563a,a1566a,a1569a,a1570a,a1573a,a1577a,a1578a,a1579a,a1582a,a1585a,a1586a,a1589a,a1593a,a1594a,a1595a,a1598a,a1601a,a1602a,a1605a,a1609a,a1610a,a1611a,a1614a,a1617a,a1618a,a1621a,a1625a,a1626a,a1627a,a1630a,a1633a,a1634a,a1637a,a1641a,a1642a,a1643a,a1646a,a1649a,a1650a,a1653a,a1657a,a1658a,a1659a,a1662a,a1665a,a1666a,a1669a,a1673a,a1674a,a1675a,a1678a,a1681a,a1682a,a1685a,a1689a,a1690a,a1691a,a1694a,a1697a,a1698a,a1701a,a1705a,a1706a,a1707a,a1710a,a1714a,a1715a,a1716a,a1719a,a1723a,a1724a,a1725a,a1728a,a1732a,a1733a,a1734a,a1737a,a1741a,a1742a,a1743a,a1746a,a1750a,a1751a,a1752a,a1755a,a1759a,a1760a,a1761a,a1764a,a1768a,a1769a,a1770a,a1773a,a1777a,a1778a,a1779a,a1782a,a1786a,a1787a,a1788a,a1791a,a1795a,a1796a,a1797a,a1800a,a1804a,a1805a,a1806a,a1809a,a1813a,a1814a,a1815a,a1818a,a1822a,a1823a,a1824a,a1827a,a1831a,a1832a,a1833a,a1836a,a1840a,a1841a,a1842a,a1845a,a1849a,a1850a,a1851a,a1854a,a1858a,a1859a,a1860a,a1863a,a1867a,a1868a,a1869a,a1872a,a1876a,a1877a,a1878a,a1881a,a1885a,a1886a,a1887a,a1890a,a1894a,a1895a,a1896a,a1899a,a1903a,a1904a,a1905a,a1908a,a1912a,a1913a,a1914a,a1917a,a1921a,a1922a,a1923a,a1926a,a1930a,a1931a,a1932a,a1935a,a1939a,a1940a,a1941a,a1944a,a1948a,a1949a,a1950a,a1953a,a1957a,a1958a,a1959a,a1962a,a1966a,a1967a,a1968a,a1971a,a1975a,a1976a,a1977a,a1980a,a1984a,a1985a,a1986a,a1989a,a1993a,a1994a,a1995a,a1998a,a2002a,a2003a,a2004a,a2007a,a2011a,a2012a,a2013a,a2016a,a2020a,a2021a,a2022a,a2025a,a2029a,a2030a,a2031a,a2034a,a2038a,a2039a,a2040a,a2043a,a2047a,a2048a,a2049a,a2052a,a2056a,a2057a,a2058a,a2061a,a2065a,a2066a,a2067a,a2070a,a2074a,a2075a,a2076a,a2079a,a2083a,a2084a,a2085a,a2088a,a2092a,a2093a,a2094a,a2097a,a2101a,a2102a,a2103a,a2106a,a2110a,a2111a,a2112a,a2115a,a2119a,a2120a,a2121a,a2124a,a2128a,a2129a,a2130a,a2133a,a2137a,a2138a,a2139a,a2142a,a2146a,a2147a,a2148a,a2151a,a2155a,a2156a,a2157a,a2160a,a2164a,a2165a,a2166a,a2169a,a2173a,a2174a,a2175a,a2178a,a2182a,a2183a,a2184a,a2187a,a2191a,a2192a,a2193a,a2196a,a2200a,a2201a,a2202a,a2205a,a2209a,a2210a,a2211a,a2214a,a2218a,a2219a,a2220a,a2223a,a2227a,a2228a,a2229a,a2232a,a2236a,a2237a,a2238a,a2241a,a2245a,a2246a,a2247a,a2250a,a2254a,a2255a,a2256a,a2259a,a2263a,a2264a,a2265a,a2268a,a2272a,a2273a,a2274a,a2277a,a2281a,a2282a,a2283a,a2286a,a2290a,a2291a,a2292a,a2295a,a2299a,a2300a,a2301a,a2304a,a2308a,a2309a,a2310a,a2313a,a2317a,a2318a,a2319a,a2322a,a2326a,a2327a,a2328a,a2331a,a2335a,a2336a,a2337a,a2340a,a2344a,a2345a,a2346a,a2349a,a2353a,a2354a,a2355a,a2358a,a2362a,a2363a,a2364a,a2368a,a2369a,a2373a,a2374a,a2375a,a2378a,a2382a,a2383a,a2384a,a2388a,a2389a,a2393a,a2394a,a2395a,a2398a,a2402a,a2403a,a2404a,a2408a,a2409a,a2413a,a2414a,a2415a,a2418a,a2422a,a2423a,a2424a,a2428a,a2429a,a2433a,a2434a,a2435a,a2438a,a2442a,a2443a,a2444a,a2448a,a2449a,a2453a,a2454a,a2455a,a2458a,a2462a,a2463a,a2464a,a2468a,a2469a,a2473a,a2474a,a2475a,a2478a,a2482a,a2483a,a2484a,a2488a,a2489a,a2493a,a2494a,a2495a,a2498a,a2502a,a2503a,a2504a,a2508a,a2509a,a2513a,a2514a,a2515a,a2518a,a2522a,a2523a,a2524a,a2528a,a2529a,a2533a,a2534a,a2535a,a2538a,a2542a,a2543a,a2544a,a2548a,a2549a,a2553a,a2554a,a2555a,a2558a,a2562a,a2563a,a2564a,a2568a,a2569a,a2573a,a2574a,a2575a,a2578a,a2582a,a2583a,a2584a,a2588a,a2589a,a2593a,a2594a,a2595a,a2598a,a2602a,a2603a,a2604a,a2608a,a2609a,a2613a,a2614a,a2615a,a2618a,a2622a,a2623a,a2624a,a2628a,a2629a,a2633a,a2634a,a2635a,a2638a,a2642a,a2643a,a2644a,a2648a,a2649a,a2653a,a2654a,a2655a,a2658a,a2662a,a2663a,a2664a,a2668a,a2669a,a2673a,a2674a,a2675a,a2678a,a2682a,a2683a,a2684a,a2688a,a2689a,a2693a,a2694a,a2695a,a2698a,a2702a,a2703a,a2704a,a2708a,a2709a,a2713a,a2714a,a2715a,a2718a,a2722a,a2723a,a2724a,a2728a,a2729a,a2733a,a2734a,a2735a,a2738a,a2742a,a2743a,a2744a,a2748a,a2749a,a2753a,a2754a,a2755a,a2758a,a2762a,a2763a,a2764a,a2768a,a2769a,a2773a,a2774a,a2775a,a2778a,a2782a,a2783a,a2784a,a2788a,a2789a,a2793a,a2794a,a2795a,a2798a,a2802a,a2803a,a2804a,a2808a,a2809a,a2813a,a2814a,a2815a,a2818a,a2822a,a2823a,a2824a,a2828a,a2829a,a2833a,a2834a,a2835a,a2839a,a2840a,a2844a,a2845a,a2846a,a2850a,a2851a,a2855a,a2856a,a2857a,a2861a,a2862a,a2866a,a2867a,a2868a,a2872a,a2873a,a2877a,a2878a,a2879a,a2883a,a2884a,a2888a,a2889a,a2890a,a2894a,a2895a,a2899a,a2900a,a2901a,a2905a,a2906a,a2910a,a2911a,a2912a,a2916a,a2917a,a2921a,a2922a,a2923a,a2927a,a2928a,a2932a,a2933a,a2934a,a2938a,a2939a,a2943a,a2944a,a2945a,a2949a,a2950a,a2954a,a2955a,a2956a,a2960a,a2961a,a2965a,a2966a,a2967a,a2971a,a2972a,a2976a,a2977a,a2978a,a2982a,a2983a,a2987a,a2988a,a2989a,a2993a,a2994a,a2998a,a2999a,a3000a,a3004a,a3005a,a3009a,a3010a,a3011a,a3015a,a3016a,a3020a,a3021a,a3022a,a3026a,a3027a,a3031a,a3032a,a3033a,a3037a,a3038a,a3042a,a3043a,a3044a,a3048a,a3049a,a3053a,a3054a,a3055a,a3059a,a3060a,a3064a,a3065a,a3066a,a3070a,a3071a,a3075a,a3076a,a3077a,a3081a,a3082a,a3086a,a3087a,a3088a,a3092a,a3093a,a3097a,a3098a,a3099a: std_logic;
begin
A107 <=( a493a ) or ( a328a );
a1a <=( a3099a and a3088a );
a2a <=( a3077a and a3066a );
a3a <=( a3055a and a3044a );
a4a <=( a3033a and a3022a );
a5a <=( a3011a and a3000a );
a6a <=( a2989a and a2978a );
a7a <=( a2967a and a2956a );
a8a <=( a2945a and a2934a );
a9a <=( a2923a and a2912a );
a10a <=( a2901a and a2890a );
a11a <=( a2879a and a2868a );
a12a <=( a2857a and a2846a );
a13a <=( a2835a and a2824a );
a14a <=( a2815a and a2804a );
a15a <=( a2795a and a2784a );
a16a <=( a2775a and a2764a );
a17a <=( a2755a and a2744a );
a18a <=( a2735a and a2724a );
a19a <=( a2715a and a2704a );
a20a <=( a2695a and a2684a );
a21a <=( a2675a and a2664a );
a22a <=( a2655a and a2644a );
a23a <=( a2635a and a2624a );
a24a <=( a2615a and a2604a );
a25a <=( a2595a and a2584a );
a26a <=( a2575a and a2564a );
a27a <=( a2555a and a2544a );
a28a <=( a2535a and a2524a );
a29a <=( a2515a and a2504a );
a30a <=( a2495a and a2484a );
a31a <=( a2475a and a2464a );
a32a <=( a2455a and a2444a );
a33a <=( a2435a and a2424a );
a34a <=( a2415a and a2404a );
a35a <=( a2395a and a2384a );
a36a <=( a2375a and a2364a );
a37a <=( a2355a and a2346a );
a38a <=( a2337a and a2328a );
a39a <=( a2319a and a2310a );
a40a <=( a2301a and a2292a );
a41a <=( a2283a and a2274a );
a42a <=( a2265a and a2256a );
a43a <=( a2247a and a2238a );
a44a <=( a2229a and a2220a );
a45a <=( a2211a and a2202a );
a46a <=( a2193a and a2184a );
a47a <=( a2175a and a2166a );
a48a <=( a2157a and a2148a );
a49a <=( a2139a and a2130a );
a50a <=( a2121a and a2112a );
a51a <=( a2103a and a2094a );
a52a <=( a2085a and a2076a );
a53a <=( a2067a and a2058a );
a54a <=( a2049a and a2040a );
a55a <=( a2031a and a2022a );
a56a <=( a2013a and a2004a );
a57a <=( a1995a and a1986a );
a58a <=( a1977a and a1968a );
a59a <=( a1959a and a1950a );
a60a <=( a1941a and a1932a );
a61a <=( a1923a and a1914a );
a62a <=( a1905a and a1896a );
a63a <=( a1887a and a1878a );
a64a <=( a1869a and a1860a );
a65a <=( a1851a and a1842a );
a66a <=( a1833a and a1824a );
a67a <=( a1815a and a1806a );
a68a <=( a1797a and a1788a );
a69a <=( a1779a and a1770a );
a70a <=( a1761a and a1752a );
a71a <=( a1743a and a1734a );
a72a <=( a1725a and a1716a );
a73a <=( a1707a and a1698a );
a74a <=( a1691a and a1682a );
a75a <=( a1675a and a1666a );
a76a <=( a1659a and a1650a );
a77a <=( a1643a and a1634a );
a78a <=( a1627a and a1618a );
a79a <=( a1611a and a1602a );
a80a <=( a1595a and a1586a );
a81a <=( a1579a and a1570a );
a82a <=( a1563a and a1554a );
a83a <=( a1547a and a1538a );
a84a <=( a1531a and a1522a );
a85a <=( a1515a and a1506a );
a86a <=( a1499a and a1490a );
a87a <=( a1483a and a1474a );
a88a <=( a1467a and a1458a );
a89a <=( a1451a and a1442a );
a90a <=( a1435a and a1426a );
a91a <=( a1419a and a1410a );
a92a <=( a1403a and a1394a );
a93a <=( a1387a and a1378a );
a94a <=( a1371a and a1362a );
a95a <=( a1355a and a1346a );
a96a <=( a1339a and a1330a );
a97a <=( a1323a and a1316a );
a98a <=( a1309a and a1302a );
a99a <=( a1295a and a1288a );
a100a <=( a1281a and a1274a );
a101a <=( a1267a and a1260a );
a102a <=( a1253a and a1246a );
a103a <=( a1239a and a1232a );
a104a <=( a1225a and a1218a );
a105a <=( a1211a and a1204a );
a106a <=( a1197a and a1190a );
a107a <=( a1183a and a1176a );
a108a <=( a1169a and a1162a );
a109a <=( a1155a and a1148a );
a110a <=( a1141a and a1134a );
a111a <=( a1127a and a1120a );
a112a <=( a1113a and a1106a );
a113a <=( a1099a and a1092a );
a114a <=( a1085a and a1078a );
a115a <=( a1071a and a1064a );
a116a <=( a1057a and a1050a );
a117a <=( a1043a and a1036a );
a118a <=( a1029a and a1022a );
a119a <=( a1015a and a1008a );
a120a <=( a1001a and a994a );
a121a <=( a987a and a980a );
a122a <=( a973a and a966a );
a123a <=( a959a and a952a );
a124a <=( a945a and a938a );
a125a <=( a931a and a924a );
a126a <=( a917a and a910a );
a127a <=( a903a and a896a );
a128a <=( a889a and a882a );
a129a <=( a875a and a868a );
a130a <=( a861a and a854a );
a131a <=( a847a and a840a );
a132a <=( a833a and a826a );
a133a <=( a819a and a812a );
a134a <=( a805a and a798a );
a135a <=( a791a and a784a );
a136a <=( a777a and a770a );
a137a <=( a765a and a758a );
a138a <=( a753a and a746a );
a139a <=( a741a and a734a );
a140a <=( a729a and a722a );
a141a <=( a717a and a710a );
a142a <=( a705a and a700a );
a143a <=( a695a and a690a );
a144a <=( a685a and a680a );
a145a <=( a675a and a670a );
a146a <=( a665a and a660a );
a147a <=( a655a and a650a );
a148a <=( a645a and a640a );
a149a <=( a635a and a630a );
a150a <=( a625a and a620a );
a151a <=( a615a and a610a );
a152a <=( a605a and a600a );
a153a <=( a595a and a590a );
a154a <=( a585a and a580a );
a155a <=( a575a and a570a );
a156a <=( a565a and a560a );
a157a <=( a555a and a550a );
a158a <=( a545a and a540a );
a159a <=( a535a and a530a );
a160a <=( a525a and a522a );
a161a <=( a519a and a516a );
a162a <=( a513a and a510a );
a163a <=( a507a and a504a );
a164a <=( a501a and a498a );
a165a <=( A266 and (not A265) );
a168a <=( a164a ) or ( a165a );
a172a <=( a161a ) or ( a162a );
a173a <=( a163a ) or ( a172a );
a174a <=( a173a ) or ( a168a );
a177a <=( a159a ) or ( a160a );
a181a <=( a156a ) or ( a157a );
a182a <=( a158a ) or ( a181a );
a183a <=( a182a ) or ( a177a );
a184a <=( a183a ) or ( a174a );
a187a <=( a154a ) or ( a155a );
a191a <=( a151a ) or ( a152a );
a192a <=( a153a ) or ( a191a );
a193a <=( a192a ) or ( a187a );
a196a <=( a149a ) or ( a150a );
a200a <=( a146a ) or ( a147a );
a201a <=( a148a ) or ( a200a );
a202a <=( a201a ) or ( a196a );
a203a <=( a202a ) or ( a193a );
a204a <=( a203a ) or ( a184a );
a207a <=( a144a ) or ( a145a );
a211a <=( a141a ) or ( a142a );
a212a <=( a143a ) or ( a211a );
a213a <=( a212a ) or ( a207a );
a216a <=( a139a ) or ( a140a );
a220a <=( a136a ) or ( a137a );
a221a <=( a138a ) or ( a220a );
a222a <=( a221a ) or ( a216a );
a223a <=( a222a ) or ( a213a );
a226a <=( a134a ) or ( a135a );
a230a <=( a131a ) or ( a132a );
a231a <=( a133a ) or ( a230a );
a232a <=( a231a ) or ( a226a );
a236a <=( a128a ) or ( a129a );
a237a <=( a130a ) or ( a236a );
a241a <=( a125a ) or ( a126a );
a242a <=( a127a ) or ( a241a );
a243a <=( a242a ) or ( a237a );
a244a <=( a243a ) or ( a232a );
a245a <=( a244a ) or ( a223a );
a246a <=( a245a ) or ( a204a );
a249a <=( a123a ) or ( a124a );
a253a <=( a120a ) or ( a121a );
a254a <=( a122a ) or ( a253a );
a255a <=( a254a ) or ( a249a );
a258a <=( a118a ) or ( a119a );
a262a <=( a115a ) or ( a116a );
a263a <=( a117a ) or ( a262a );
a264a <=( a263a ) or ( a258a );
a265a <=( a264a ) or ( a255a );
a268a <=( a113a ) or ( a114a );
a272a <=( a110a ) or ( a111a );
a273a <=( a112a ) or ( a272a );
a274a <=( a273a ) or ( a268a );
a277a <=( a108a ) or ( a109a );
a281a <=( a105a ) or ( a106a );
a282a <=( a107a ) or ( a281a );
a283a <=( a282a ) or ( a277a );
a284a <=( a283a ) or ( a274a );
a285a <=( a284a ) or ( a265a );
a288a <=( a103a ) or ( a104a );
a292a <=( a100a ) or ( a101a );
a293a <=( a102a ) or ( a292a );
a294a <=( a293a ) or ( a288a );
a297a <=( a98a ) or ( a99a );
a301a <=( a95a ) or ( a96a );
a302a <=( a97a ) or ( a301a );
a303a <=( a302a ) or ( a297a );
a304a <=( a303a ) or ( a294a );
a307a <=( a93a ) or ( a94a );
a311a <=( a90a ) or ( a91a );
a312a <=( a92a ) or ( a311a );
a313a <=( a312a ) or ( a307a );
a317a <=( a87a ) or ( a88a );
a318a <=( a89a ) or ( a317a );
a322a <=( a84a ) or ( a85a );
a323a <=( a86a ) or ( a322a );
a324a <=( a323a ) or ( a318a );
a325a <=( a324a ) or ( a313a );
a326a <=( a325a ) or ( a304a );
a327a <=( a326a ) or ( a285a );
a328a <=( a327a ) or ( a246a );
a331a <=( a82a ) or ( a83a );
a335a <=( a79a ) or ( a80a );
a336a <=( a81a ) or ( a335a );
a337a <=( a336a ) or ( a331a );
a340a <=( a77a ) or ( a78a );
a344a <=( a74a ) or ( a75a );
a345a <=( a76a ) or ( a344a );
a346a <=( a345a ) or ( a340a );
a347a <=( a346a ) or ( a337a );
a350a <=( a72a ) or ( a73a );
a354a <=( a69a ) or ( a70a );
a355a <=( a71a ) or ( a354a );
a356a <=( a355a ) or ( a350a );
a359a <=( a67a ) or ( a68a );
a363a <=( a64a ) or ( a65a );
a364a <=( a66a ) or ( a363a );
a365a <=( a364a ) or ( a359a );
a366a <=( a365a ) or ( a356a );
a367a <=( a366a ) or ( a347a );
a370a <=( a62a ) or ( a63a );
a374a <=( a59a ) or ( a60a );
a375a <=( a61a ) or ( a374a );
a376a <=( a375a ) or ( a370a );
a379a <=( a57a ) or ( a58a );
a383a <=( a54a ) or ( a55a );
a384a <=( a56a ) or ( a383a );
a385a <=( a384a ) or ( a379a );
a386a <=( a385a ) or ( a376a );
a389a <=( a52a ) or ( a53a );
a393a <=( a49a ) or ( a50a );
a394a <=( a51a ) or ( a393a );
a395a <=( a394a ) or ( a389a );
a399a <=( a46a ) or ( a47a );
a400a <=( a48a ) or ( a399a );
a404a <=( a43a ) or ( a44a );
a405a <=( a45a ) or ( a404a );
a406a <=( a405a ) or ( a400a );
a407a <=( a406a ) or ( a395a );
a408a <=( a407a ) or ( a386a );
a409a <=( a408a ) or ( a367a );
a412a <=( a41a ) or ( a42a );
a416a <=( a38a ) or ( a39a );
a417a <=( a40a ) or ( a416a );
a418a <=( a417a ) or ( a412a );
a421a <=( a36a ) or ( a37a );
a425a <=( a33a ) or ( a34a );
a426a <=( a35a ) or ( a425a );
a427a <=( a426a ) or ( a421a );
a428a <=( a427a ) or ( a418a );
a431a <=( a31a ) or ( a32a );
a435a <=( a28a ) or ( a29a );
a436a <=( a30a ) or ( a435a );
a437a <=( a436a ) or ( a431a );
a441a <=( a25a ) or ( a26a );
a442a <=( a27a ) or ( a441a );
a446a <=( a22a ) or ( a23a );
a447a <=( a24a ) or ( a446a );
a448a <=( a447a ) or ( a442a );
a449a <=( a448a ) or ( a437a );
a450a <=( a449a ) or ( a428a );
a453a <=( a20a ) or ( a21a );
a457a <=( a17a ) or ( a18a );
a458a <=( a19a ) or ( a457a );
a459a <=( a458a ) or ( a453a );
a462a <=( a15a ) or ( a16a );
a466a <=( a12a ) or ( a13a );
a467a <=( a14a ) or ( a466a );
a468a <=( a467a ) or ( a462a );
a469a <=( a468a ) or ( a459a );
a472a <=( a10a ) or ( a11a );
a476a <=( a7a ) or ( a8a );
a477a <=( a9a ) or ( a476a );
a478a <=( a477a ) or ( a472a );
a482a <=( a4a ) or ( a5a );
a483a <=( a6a ) or ( a482a );
a487a <=( a1a ) or ( a2a );
a488a <=( a3a ) or ( a487a );
a489a <=( a488a ) or ( a483a );
a490a <=( a489a ) or ( a478a );
a491a <=( a490a ) or ( a469a );
a492a <=( a491a ) or ( a450a );
a493a <=( a492a ) or ( a409a );
a498a <=( (not A266) and A265 );
a501a <=( A268 and A267 );
a504a <=( (not A266) and A265 );
a507a <=( A269 and A267 );
a510a <=( A200 and (not A199) );
a513a <=( A233 and (not A232) );
a516a <=( A166 and A168 );
a519a <=( A233 and (not A232) );
a522a <=( A167 and A168 );
a525a <=( A233 and (not A232) );
a529a <=( A232 and A200 );
a530a <=( (not A199) and a529a );
a534a <=( A235 and A234 );
a535a <=( (not A233) and a534a );
a539a <=( A232 and A200 );
a540a <=( (not A199) and a539a );
a544a <=( A236 and A234 );
a545a <=( (not A233) and a544a );
a549a <=( A201 and (not A200) );
a550a <=( A199 and a549a );
a554a <=( A233 and (not A232) );
a555a <=( A202 and a554a );
a559a <=( A201 and (not A200) );
a560a <=( A199 and a559a );
a564a <=( A233 and (not A232) );
a565a <=( A203 and a564a );
a569a <=( A232 and A166 );
a570a <=( A168 and a569a );
a574a <=( A235 and A234 );
a575a <=( (not A233) and a574a );
a579a <=( A232 and A166 );
a580a <=( A168 and a579a );
a584a <=( A236 and A234 );
a585a <=( (not A233) and a584a );
a589a <=( A199 and A166 );
a590a <=( A168 and a589a );
a594a <=( A299 and (not A298) );
a595a <=( A200 and a594a );
a599a <=( (not A200) and A166 );
a600a <=( A168 and a599a );
a604a <=( A299 and (not A298) );
a605a <=( (not A201) and a604a );
a609a <=( (not A199) and A166 );
a610a <=( A168 and a609a );
a614a <=( A299 and (not A298) );
a615a <=( (not A200) and a614a );
a619a <=( A232 and A167 );
a620a <=( A168 and a619a );
a624a <=( A235 and A234 );
a625a <=( (not A233) and a624a );
a629a <=( A232 and A167 );
a630a <=( A168 and a629a );
a634a <=( A236 and A234 );
a635a <=( (not A233) and a634a );
a639a <=( A199 and A167 );
a640a <=( A168 and a639a );
a644a <=( A299 and (not A298) );
a645a <=( A200 and a644a );
a649a <=( (not A200) and A167 );
a650a <=( A168 and a649a );
a654a <=( A299 and (not A298) );
a655a <=( (not A201) and a654a );
a659a <=( (not A199) and A167 );
a660a <=( A168 and a659a );
a664a <=( A299 and (not A298) );
a665a <=( (not A200) and a664a );
a669a <=( A167 and A169 );
a670a <=( (not A170) and a669a );
a674a <=( A233 and (not A232) );
a675a <=( A166 and a674a );
a679a <=( (not A167) and A169 );
a680a <=( (not A170) and a679a );
a684a <=( A233 and (not A232) );
a685a <=( (not A166) and a684a );
a689a <=( A167 and (not A169) );
a690a <=( A170 and a689a );
a694a <=( A233 and (not A232) );
a695a <=( (not A166) and a694a );
a699a <=( (not A167) and (not A169) );
a700a <=( A170 and a699a );
a704a <=( A233 and (not A232) );
a705a <=( A166 and a704a );
a709a <=( (not A200) and A166 );
a710a <=( A168 and a709a );
a713a <=( (not A203) and (not A202) );
a716a <=( A299 and (not A298) );
a717a <=( a716a and a713a );
a721a <=( (not A200) and A167 );
a722a <=( A168 and a721a );
a725a <=( (not A203) and (not A202) );
a728a <=( A299 and (not A298) );
a729a <=( a728a and a725a );
a733a <=( (not A166) and (not A167) );
a734a <=( A170 and a733a );
a737a <=( A200 and (not A199) );
a740a <=( A299 and (not A298) );
a741a <=( a740a and a737a );
a745a <=( (not A168) and A169 );
a746a <=( A170 and a745a );
a749a <=( A200 and (not A199) );
a752a <=( A299 and (not A298) );
a753a <=( a752a and a749a );
a757a <=( (not A166) and (not A167) );
a758a <=( (not A169) and a757a );
a761a <=( A200 and (not A199) );
a764a <=( A299 and (not A298) );
a765a <=( a764a and a761a );
a769a <=( (not A168) and (not A169) );
a770a <=( (not A170) and a769a );
a773a <=( A200 and (not A199) );
a776a <=( A299 and (not A298) );
a777a <=( a776a and a773a );
a780a <=( (not A200) and A199 );
a783a <=( A202 and A201 );
a784a <=( a783a and a780a );
a787a <=( (not A233) and A232 );
a790a <=( A235 and A234 );
a791a <=( a790a and a787a );
a794a <=( (not A200) and A199 );
a797a <=( A202 and A201 );
a798a <=( a797a and a794a );
a801a <=( (not A233) and A232 );
a804a <=( A236 and A234 );
a805a <=( a804a and a801a );
a808a <=( (not A200) and A199 );
a811a <=( A203 and A201 );
a812a <=( a811a and a808a );
a815a <=( (not A233) and A232 );
a818a <=( A235 and A234 );
a819a <=( a818a and a815a );
a822a <=( (not A200) and A199 );
a825a <=( A203 and A201 );
a826a <=( a825a and a822a );
a829a <=( (not A233) and A232 );
a832a <=( A236 and A234 );
a833a <=( a832a and a829a );
a836a <=( A166 and A168 );
a839a <=( A200 and A199 );
a840a <=( a839a and a836a );
a843a <=( (not A299) and A298 );
a846a <=( A301 and A300 );
a847a <=( a846a and a843a );
a850a <=( A166 and A168 );
a853a <=( A200 and A199 );
a854a <=( a853a and a850a );
a857a <=( (not A299) and A298 );
a860a <=( A302 and A300 );
a861a <=( a860a and a857a );
a864a <=( A166 and A168 );
a867a <=( (not A201) and (not A200) );
a868a <=( a867a and a864a );
a871a <=( (not A299) and A298 );
a874a <=( A301 and A300 );
a875a <=( a874a and a871a );
a878a <=( A166 and A168 );
a881a <=( (not A201) and (not A200) );
a882a <=( a881a and a878a );
a885a <=( (not A299) and A298 );
a888a <=( A302 and A300 );
a889a <=( a888a and a885a );
a892a <=( A166 and A168 );
a895a <=( (not A200) and (not A199) );
a896a <=( a895a and a892a );
a899a <=( (not A299) and A298 );
a902a <=( A301 and A300 );
a903a <=( a902a and a899a );
a906a <=( A166 and A168 );
a909a <=( (not A200) and (not A199) );
a910a <=( a909a and a906a );
a913a <=( (not A299) and A298 );
a916a <=( A302 and A300 );
a917a <=( a916a and a913a );
a920a <=( A167 and A168 );
a923a <=( A200 and A199 );
a924a <=( a923a and a920a );
a927a <=( (not A299) and A298 );
a930a <=( A301 and A300 );
a931a <=( a930a and a927a );
a934a <=( A167 and A168 );
a937a <=( A200 and A199 );
a938a <=( a937a and a934a );
a941a <=( (not A299) and A298 );
a944a <=( A302 and A300 );
a945a <=( a944a and a941a );
a948a <=( A167 and A168 );
a951a <=( (not A201) and (not A200) );
a952a <=( a951a and a948a );
a955a <=( (not A299) and A298 );
a958a <=( A301 and A300 );
a959a <=( a958a and a955a );
a962a <=( A167 and A168 );
a965a <=( (not A201) and (not A200) );
a966a <=( a965a and a962a );
a969a <=( (not A299) and A298 );
a972a <=( A302 and A300 );
a973a <=( a972a and a969a );
a976a <=( A167 and A168 );
a979a <=( (not A200) and (not A199) );
a980a <=( a979a and a976a );
a983a <=( (not A299) and A298 );
a986a <=( A301 and A300 );
a987a <=( a986a and a983a );
a990a <=( A167 and A168 );
a993a <=( (not A200) and (not A199) );
a994a <=( a993a and a990a );
a997a <=( (not A299) and A298 );
a1000a <=( A302 and A300 );
a1001a <=( a1000a and a997a );
a1004a <=( (not A168) and A169 );
a1007a <=( (not A166) and A167 );
a1008a <=( a1007a and a1004a );
a1011a <=( A200 and (not A199) );
a1014a <=( A299 and (not A298) );
a1015a <=( a1014a and a1011a );
a1018a <=( (not A168) and A169 );
a1021a <=( A166 and (not A167) );
a1022a <=( a1021a and a1018a );
a1025a <=( A200 and (not A199) );
a1028a <=( A299 and (not A298) );
a1029a <=( a1028a and a1025a );
a1032a <=( A169 and (not A170) );
a1035a <=( A166 and A167 );
a1036a <=( a1035a and a1032a );
a1039a <=( (not A233) and A232 );
a1042a <=( A235 and A234 );
a1043a <=( a1042a and a1039a );
a1046a <=( A169 and (not A170) );
a1049a <=( A166 and A167 );
a1050a <=( a1049a and a1046a );
a1053a <=( (not A233) and A232 );
a1056a <=( A236 and A234 );
a1057a <=( a1056a and a1053a );
a1060a <=( A169 and (not A170) );
a1063a <=( A166 and A167 );
a1064a <=( a1063a and a1060a );
a1067a <=( A200 and A199 );
a1070a <=( A299 and (not A298) );
a1071a <=( a1070a and a1067a );
a1074a <=( A169 and (not A170) );
a1077a <=( A166 and A167 );
a1078a <=( a1077a and a1074a );
a1081a <=( (not A201) and (not A200) );
a1084a <=( A299 and (not A298) );
a1085a <=( a1084a and a1081a );
a1088a <=( A169 and (not A170) );
a1091a <=( A166 and A167 );
a1092a <=( a1091a and a1088a );
a1095a <=( (not A200) and (not A199) );
a1098a <=( A299 and (not A298) );
a1099a <=( a1098a and a1095a );
a1102a <=( A169 and (not A170) );
a1105a <=( (not A166) and (not A167) );
a1106a <=( a1105a and a1102a );
a1109a <=( (not A233) and A232 );
a1112a <=( A235 and A234 );
a1113a <=( a1112a and a1109a );
a1116a <=( A169 and (not A170) );
a1119a <=( (not A166) and (not A167) );
a1120a <=( a1119a and a1116a );
a1123a <=( (not A233) and A232 );
a1126a <=( A236 and A234 );
a1127a <=( a1126a and a1123a );
a1130a <=( A169 and (not A170) );
a1133a <=( (not A166) and (not A167) );
a1134a <=( a1133a and a1130a );
a1137a <=( A200 and A199 );
a1140a <=( A299 and (not A298) );
a1141a <=( a1140a and a1137a );
a1144a <=( A169 and (not A170) );
a1147a <=( (not A166) and (not A167) );
a1148a <=( a1147a and a1144a );
a1151a <=( (not A201) and (not A200) );
a1154a <=( A299 and (not A298) );
a1155a <=( a1154a and a1151a );
a1158a <=( A169 and (not A170) );
a1161a <=( (not A166) and (not A167) );
a1162a <=( a1161a and a1158a );
a1165a <=( (not A200) and (not A199) );
a1168a <=( A299 and (not A298) );
a1169a <=( a1168a and a1165a );
a1172a <=( (not A168) and (not A169) );
a1175a <=( A166 and A167 );
a1176a <=( a1175a and a1172a );
a1179a <=( A200 and (not A199) );
a1182a <=( A299 and (not A298) );
a1183a <=( a1182a and a1179a );
a1186a <=( (not A169) and A170 );
a1189a <=( (not A166) and A167 );
a1190a <=( a1189a and a1186a );
a1193a <=( (not A233) and A232 );
a1196a <=( A235 and A234 );
a1197a <=( a1196a and a1193a );
a1200a <=( (not A169) and A170 );
a1203a <=( (not A166) and A167 );
a1204a <=( a1203a and a1200a );
a1207a <=( (not A233) and A232 );
a1210a <=( A236 and A234 );
a1211a <=( a1210a and a1207a );
a1214a <=( (not A169) and A170 );
a1217a <=( (not A166) and A167 );
a1218a <=( a1217a and a1214a );
a1221a <=( A200 and A199 );
a1224a <=( A299 and (not A298) );
a1225a <=( a1224a and a1221a );
a1228a <=( (not A169) and A170 );
a1231a <=( (not A166) and A167 );
a1232a <=( a1231a and a1228a );
a1235a <=( (not A201) and (not A200) );
a1238a <=( A299 and (not A298) );
a1239a <=( a1238a and a1235a );
a1242a <=( (not A169) and A170 );
a1245a <=( (not A166) and A167 );
a1246a <=( a1245a and a1242a );
a1249a <=( (not A200) and (not A199) );
a1252a <=( A299 and (not A298) );
a1253a <=( a1252a and a1249a );
a1256a <=( (not A169) and A170 );
a1259a <=( A166 and (not A167) );
a1260a <=( a1259a and a1256a );
a1263a <=( (not A233) and A232 );
a1266a <=( A235 and A234 );
a1267a <=( a1266a and a1263a );
a1270a <=( (not A169) and A170 );
a1273a <=( A166 and (not A167) );
a1274a <=( a1273a and a1270a );
a1277a <=( (not A233) and A232 );
a1280a <=( A236 and A234 );
a1281a <=( a1280a and a1277a );
a1284a <=( (not A169) and A170 );
a1287a <=( A166 and (not A167) );
a1288a <=( a1287a and a1284a );
a1291a <=( A200 and A199 );
a1294a <=( A299 and (not A298) );
a1295a <=( a1294a and a1291a );
a1298a <=( (not A169) and A170 );
a1301a <=( A166 and (not A167) );
a1302a <=( a1301a and a1298a );
a1305a <=( (not A201) and (not A200) );
a1308a <=( A299 and (not A298) );
a1309a <=( a1308a and a1305a );
a1312a <=( (not A169) and A170 );
a1315a <=( A166 and (not A167) );
a1316a <=( a1315a and a1312a );
a1319a <=( (not A200) and (not A199) );
a1322a <=( A299 and (not A298) );
a1323a <=( a1322a and a1319a );
a1326a <=( A166 and A168 );
a1329a <=( (not A202) and (not A200) );
a1330a <=( a1329a and a1326a );
a1333a <=( A298 and (not A203) );
a1337a <=( A301 and A300 );
a1338a <=( (not A299) and a1337a );
a1339a <=( a1338a and a1333a );
a1342a <=( A166 and A168 );
a1345a <=( (not A202) and (not A200) );
a1346a <=( a1345a and a1342a );
a1349a <=( A298 and (not A203) );
a1353a <=( A302 and A300 );
a1354a <=( (not A299) and a1353a );
a1355a <=( a1354a and a1349a );
a1358a <=( A167 and A168 );
a1361a <=( (not A202) and (not A200) );
a1362a <=( a1361a and a1358a );
a1365a <=( A298 and (not A203) );
a1369a <=( A301 and A300 );
a1370a <=( (not A299) and a1369a );
a1371a <=( a1370a and a1365a );
a1374a <=( A167 and A168 );
a1377a <=( (not A202) and (not A200) );
a1378a <=( a1377a and a1374a );
a1381a <=( A298 and (not A203) );
a1385a <=( A302 and A300 );
a1386a <=( (not A299) and a1385a );
a1387a <=( a1386a and a1381a );
a1390a <=( (not A167) and A170 );
a1393a <=( (not A199) and (not A166) );
a1394a <=( a1393a and a1390a );
a1397a <=( A298 and A200 );
a1401a <=( A301 and A300 );
a1402a <=( (not A299) and a1401a );
a1403a <=( a1402a and a1397a );
a1406a <=( (not A167) and A170 );
a1409a <=( (not A199) and (not A166) );
a1410a <=( a1409a and a1406a );
a1413a <=( A298 and A200 );
a1417a <=( A302 and A300 );
a1418a <=( (not A299) and a1417a );
a1419a <=( a1418a and a1413a );
a1422a <=( (not A167) and A170 );
a1425a <=( A199 and (not A166) );
a1426a <=( a1425a and a1422a );
a1429a <=( A201 and (not A200) );
a1433a <=( A299 and (not A298) );
a1434a <=( A202 and a1433a );
a1435a <=( a1434a and a1429a );
a1438a <=( (not A167) and A170 );
a1441a <=( A199 and (not A166) );
a1442a <=( a1441a and a1438a );
a1445a <=( A201 and (not A200) );
a1449a <=( A299 and (not A298) );
a1450a <=( A203 and a1449a );
a1451a <=( a1450a and a1445a );
a1454a <=( A169 and A170 );
a1457a <=( (not A199) and (not A168) );
a1458a <=( a1457a and a1454a );
a1461a <=( A298 and A200 );
a1465a <=( A301 and A300 );
a1466a <=( (not A299) and a1465a );
a1467a <=( a1466a and a1461a );
a1470a <=( A169 and A170 );
a1473a <=( (not A199) and (not A168) );
a1474a <=( a1473a and a1470a );
a1477a <=( A298 and A200 );
a1481a <=( A302 and A300 );
a1482a <=( (not A299) and a1481a );
a1483a <=( a1482a and a1477a );
a1486a <=( A169 and A170 );
a1489a <=( A199 and (not A168) );
a1490a <=( a1489a and a1486a );
a1493a <=( A201 and (not A200) );
a1497a <=( A299 and (not A298) );
a1498a <=( A202 and a1497a );
a1499a <=( a1498a and a1493a );
a1502a <=( A169 and A170 );
a1505a <=( A199 and (not A168) );
a1506a <=( a1505a and a1502a );
a1509a <=( A201 and (not A200) );
a1513a <=( A299 and (not A298) );
a1514a <=( A203 and a1513a );
a1515a <=( a1514a and a1509a );
a1518a <=( A169 and (not A170) );
a1521a <=( A166 and A167 );
a1522a <=( a1521a and a1518a );
a1525a <=( (not A202) and (not A200) );
a1529a <=( A299 and (not A298) );
a1530a <=( (not A203) and a1529a );
a1531a <=( a1530a and a1525a );
a1534a <=( A169 and (not A170) );
a1537a <=( (not A166) and (not A167) );
a1538a <=( a1537a and a1534a );
a1541a <=( (not A202) and (not A200) );
a1545a <=( A299 and (not A298) );
a1546a <=( (not A203) and a1545a );
a1547a <=( a1546a and a1541a );
a1550a <=( (not A167) and (not A169) );
a1553a <=( (not A199) and (not A166) );
a1554a <=( a1553a and a1550a );
a1557a <=( A298 and A200 );
a1561a <=( A301 and A300 );
a1562a <=( (not A299) and a1561a );
a1563a <=( a1562a and a1557a );
a1566a <=( (not A167) and (not A169) );
a1569a <=( (not A199) and (not A166) );
a1570a <=( a1569a and a1566a );
a1573a <=( A298 and A200 );
a1577a <=( A302 and A300 );
a1578a <=( (not A299) and a1577a );
a1579a <=( a1578a and a1573a );
a1582a <=( (not A167) and (not A169) );
a1585a <=( A199 and (not A166) );
a1586a <=( a1585a and a1582a );
a1589a <=( A201 and (not A200) );
a1593a <=( A299 and (not A298) );
a1594a <=( A202 and a1593a );
a1595a <=( a1594a and a1589a );
a1598a <=( (not A167) and (not A169) );
a1601a <=( A199 and (not A166) );
a1602a <=( a1601a and a1598a );
a1605a <=( A201 and (not A200) );
a1609a <=( A299 and (not A298) );
a1610a <=( A203 and a1609a );
a1611a <=( a1610a and a1605a );
a1614a <=( (not A169) and A170 );
a1617a <=( (not A166) and A167 );
a1618a <=( a1617a and a1614a );
a1621a <=( (not A202) and (not A200) );
a1625a <=( A299 and (not A298) );
a1626a <=( (not A203) and a1625a );
a1627a <=( a1626a and a1621a );
a1630a <=( (not A169) and A170 );
a1633a <=( A166 and (not A167) );
a1634a <=( a1633a and a1630a );
a1637a <=( (not A202) and (not A200) );
a1641a <=( A299 and (not A298) );
a1642a <=( (not A203) and a1641a );
a1643a <=( a1642a and a1637a );
a1646a <=( (not A169) and (not A170) );
a1649a <=( (not A199) and (not A168) );
a1650a <=( a1649a and a1646a );
a1653a <=( A298 and A200 );
a1657a <=( A301 and A300 );
a1658a <=( (not A299) and a1657a );
a1659a <=( a1658a and a1653a );
a1662a <=( (not A169) and (not A170) );
a1665a <=( (not A199) and (not A168) );
a1666a <=( a1665a and a1662a );
a1669a <=( A298 and A200 );
a1673a <=( A302 and A300 );
a1674a <=( (not A299) and a1673a );
a1675a <=( a1674a and a1669a );
a1678a <=( (not A169) and (not A170) );
a1681a <=( A199 and (not A168) );
a1682a <=( a1681a and a1678a );
a1685a <=( A201 and (not A200) );
a1689a <=( A299 and (not A298) );
a1690a <=( A202 and a1689a );
a1691a <=( a1690a and a1685a );
a1694a <=( (not A169) and (not A170) );
a1697a <=( A199 and (not A168) );
a1698a <=( a1697a and a1694a );
a1701a <=( A201 and (not A200) );
a1705a <=( A299 and (not A298) );
a1706a <=( A203 and a1705a );
a1707a <=( a1706a and a1701a );
a1710a <=( (not A168) and A169 );
a1714a <=( (not A199) and (not A166) );
a1715a <=( A167 and a1714a );
a1716a <=( a1715a and a1710a );
a1719a <=( A298 and A200 );
a1723a <=( A301 and A300 );
a1724a <=( (not A299) and a1723a );
a1725a <=( a1724a and a1719a );
a1728a <=( (not A168) and A169 );
a1732a <=( (not A199) and (not A166) );
a1733a <=( A167 and a1732a );
a1734a <=( a1733a and a1728a );
a1737a <=( A298 and A200 );
a1741a <=( A302 and A300 );
a1742a <=( (not A299) and a1741a );
a1743a <=( a1742a and a1737a );
a1746a <=( (not A168) and A169 );
a1750a <=( A199 and (not A166) );
a1751a <=( A167 and a1750a );
a1752a <=( a1751a and a1746a );
a1755a <=( A201 and (not A200) );
a1759a <=( A299 and (not A298) );
a1760a <=( A202 and a1759a );
a1761a <=( a1760a and a1755a );
a1764a <=( (not A168) and A169 );
a1768a <=( A199 and (not A166) );
a1769a <=( A167 and a1768a );
a1770a <=( a1769a and a1764a );
a1773a <=( A201 and (not A200) );
a1777a <=( A299 and (not A298) );
a1778a <=( A203 and a1777a );
a1779a <=( a1778a and a1773a );
a1782a <=( (not A168) and A169 );
a1786a <=( (not A199) and A166 );
a1787a <=( (not A167) and a1786a );
a1788a <=( a1787a and a1782a );
a1791a <=( A298 and A200 );
a1795a <=( A301 and A300 );
a1796a <=( (not A299) and a1795a );
a1797a <=( a1796a and a1791a );
a1800a <=( (not A168) and A169 );
a1804a <=( (not A199) and A166 );
a1805a <=( (not A167) and a1804a );
a1806a <=( a1805a and a1800a );
a1809a <=( A298 and A200 );
a1813a <=( A302 and A300 );
a1814a <=( (not A299) and a1813a );
a1815a <=( a1814a and a1809a );
a1818a <=( (not A168) and A169 );
a1822a <=( A199 and A166 );
a1823a <=( (not A167) and a1822a );
a1824a <=( a1823a and a1818a );
a1827a <=( A201 and (not A200) );
a1831a <=( A299 and (not A298) );
a1832a <=( A202 and a1831a );
a1833a <=( a1832a and a1827a );
a1836a <=( (not A168) and A169 );
a1840a <=( A199 and A166 );
a1841a <=( (not A167) and a1840a );
a1842a <=( a1841a and a1836a );
a1845a <=( A201 and (not A200) );
a1849a <=( A299 and (not A298) );
a1850a <=( A203 and a1849a );
a1851a <=( a1850a and a1845a );
a1854a <=( A169 and (not A170) );
a1858a <=( A199 and A166 );
a1859a <=( A167 and a1858a );
a1860a <=( a1859a and a1854a );
a1863a <=( A298 and A200 );
a1867a <=( A301 and A300 );
a1868a <=( (not A299) and a1867a );
a1869a <=( a1868a and a1863a );
a1872a <=( A169 and (not A170) );
a1876a <=( A199 and A166 );
a1877a <=( A167 and a1876a );
a1878a <=( a1877a and a1872a );
a1881a <=( A298 and A200 );
a1885a <=( A302 and A300 );
a1886a <=( (not A299) and a1885a );
a1887a <=( a1886a and a1881a );
a1890a <=( A169 and (not A170) );
a1894a <=( (not A200) and A166 );
a1895a <=( A167 and a1894a );
a1896a <=( a1895a and a1890a );
a1899a <=( A298 and (not A201) );
a1903a <=( A301 and A300 );
a1904a <=( (not A299) and a1903a );
a1905a <=( a1904a and a1899a );
a1908a <=( A169 and (not A170) );
a1912a <=( (not A200) and A166 );
a1913a <=( A167 and a1912a );
a1914a <=( a1913a and a1908a );
a1917a <=( A298 and (not A201) );
a1921a <=( A302 and A300 );
a1922a <=( (not A299) and a1921a );
a1923a <=( a1922a and a1917a );
a1926a <=( A169 and (not A170) );
a1930a <=( (not A199) and A166 );
a1931a <=( A167 and a1930a );
a1932a <=( a1931a and a1926a );
a1935a <=( A298 and (not A200) );
a1939a <=( A301 and A300 );
a1940a <=( (not A299) and a1939a );
a1941a <=( a1940a and a1935a );
a1944a <=( A169 and (not A170) );
a1948a <=( (not A199) and A166 );
a1949a <=( A167 and a1948a );
a1950a <=( a1949a and a1944a );
a1953a <=( A298 and (not A200) );
a1957a <=( A302 and A300 );
a1958a <=( (not A299) and a1957a );
a1959a <=( a1958a and a1953a );
a1962a <=( A169 and (not A170) );
a1966a <=( A199 and (not A166) );
a1967a <=( (not A167) and a1966a );
a1968a <=( a1967a and a1962a );
a1971a <=( A298 and A200 );
a1975a <=( A301 and A300 );
a1976a <=( (not A299) and a1975a );
a1977a <=( a1976a and a1971a );
a1980a <=( A169 and (not A170) );
a1984a <=( A199 and (not A166) );
a1985a <=( (not A167) and a1984a );
a1986a <=( a1985a and a1980a );
a1989a <=( A298 and A200 );
a1993a <=( A302 and A300 );
a1994a <=( (not A299) and a1993a );
a1995a <=( a1994a and a1989a );
a1998a <=( A169 and (not A170) );
a2002a <=( (not A200) and (not A166) );
a2003a <=( (not A167) and a2002a );
a2004a <=( a2003a and a1998a );
a2007a <=( A298 and (not A201) );
a2011a <=( A301 and A300 );
a2012a <=( (not A299) and a2011a );
a2013a <=( a2012a and a2007a );
a2016a <=( A169 and (not A170) );
a2020a <=( (not A200) and (not A166) );
a2021a <=( (not A167) and a2020a );
a2022a <=( a2021a and a2016a );
a2025a <=( A298 and (not A201) );
a2029a <=( A302 and A300 );
a2030a <=( (not A299) and a2029a );
a2031a <=( a2030a and a2025a );
a2034a <=( A169 and (not A170) );
a2038a <=( (not A199) and (not A166) );
a2039a <=( (not A167) and a2038a );
a2040a <=( a2039a and a2034a );
a2043a <=( A298 and (not A200) );
a2047a <=( A301 and A300 );
a2048a <=( (not A299) and a2047a );
a2049a <=( a2048a and a2043a );
a2052a <=( A169 and (not A170) );
a2056a <=( (not A199) and (not A166) );
a2057a <=( (not A167) and a2056a );
a2058a <=( a2057a and a2052a );
a2061a <=( A298 and (not A200) );
a2065a <=( A302 and A300 );
a2066a <=( (not A299) and a2065a );
a2067a <=( a2066a and a2061a );
a2070a <=( (not A168) and (not A169) );
a2074a <=( (not A199) and A166 );
a2075a <=( A167 and a2074a );
a2076a <=( a2075a and a2070a );
a2079a <=( A298 and A200 );
a2083a <=( A301 and A300 );
a2084a <=( (not A299) and a2083a );
a2085a <=( a2084a and a2079a );
a2088a <=( (not A168) and (not A169) );
a2092a <=( (not A199) and A166 );
a2093a <=( A167 and a2092a );
a2094a <=( a2093a and a2088a );
a2097a <=( A298 and A200 );
a2101a <=( A302 and A300 );
a2102a <=( (not A299) and a2101a );
a2103a <=( a2102a and a2097a );
a2106a <=( (not A168) and (not A169) );
a2110a <=( A199 and A166 );
a2111a <=( A167 and a2110a );
a2112a <=( a2111a and a2106a );
a2115a <=( A201 and (not A200) );
a2119a <=( A299 and (not A298) );
a2120a <=( A202 and a2119a );
a2121a <=( a2120a and a2115a );
a2124a <=( (not A168) and (not A169) );
a2128a <=( A199 and A166 );
a2129a <=( A167 and a2128a );
a2130a <=( a2129a and a2124a );
a2133a <=( A201 and (not A200) );
a2137a <=( A299 and (not A298) );
a2138a <=( A203 and a2137a );
a2139a <=( a2138a and a2133a );
a2142a <=( (not A169) and A170 );
a2146a <=( A199 and (not A166) );
a2147a <=( A167 and a2146a );
a2148a <=( a2147a and a2142a );
a2151a <=( A298 and A200 );
a2155a <=( A301 and A300 );
a2156a <=( (not A299) and a2155a );
a2157a <=( a2156a and a2151a );
a2160a <=( (not A169) and A170 );
a2164a <=( A199 and (not A166) );
a2165a <=( A167 and a2164a );
a2166a <=( a2165a and a2160a );
a2169a <=( A298 and A200 );
a2173a <=( A302 and A300 );
a2174a <=( (not A299) and a2173a );
a2175a <=( a2174a and a2169a );
a2178a <=( (not A169) and A170 );
a2182a <=( (not A200) and (not A166) );
a2183a <=( A167 and a2182a );
a2184a <=( a2183a and a2178a );
a2187a <=( A298 and (not A201) );
a2191a <=( A301 and A300 );
a2192a <=( (not A299) and a2191a );
a2193a <=( a2192a and a2187a );
a2196a <=( (not A169) and A170 );
a2200a <=( (not A200) and (not A166) );
a2201a <=( A167 and a2200a );
a2202a <=( a2201a and a2196a );
a2205a <=( A298 and (not A201) );
a2209a <=( A302 and A300 );
a2210a <=( (not A299) and a2209a );
a2211a <=( a2210a and a2205a );
a2214a <=( (not A169) and A170 );
a2218a <=( (not A199) and (not A166) );
a2219a <=( A167 and a2218a );
a2220a <=( a2219a and a2214a );
a2223a <=( A298 and (not A200) );
a2227a <=( A301 and A300 );
a2228a <=( (not A299) and a2227a );
a2229a <=( a2228a and a2223a );
a2232a <=( (not A169) and A170 );
a2236a <=( (not A199) and (not A166) );
a2237a <=( A167 and a2236a );
a2238a <=( a2237a and a2232a );
a2241a <=( A298 and (not A200) );
a2245a <=( A302 and A300 );
a2246a <=( (not A299) and a2245a );
a2247a <=( a2246a and a2241a );
a2250a <=( (not A169) and A170 );
a2254a <=( A199 and A166 );
a2255a <=( (not A167) and a2254a );
a2256a <=( a2255a and a2250a );
a2259a <=( A298 and A200 );
a2263a <=( A301 and A300 );
a2264a <=( (not A299) and a2263a );
a2265a <=( a2264a and a2259a );
a2268a <=( (not A169) and A170 );
a2272a <=( A199 and A166 );
a2273a <=( (not A167) and a2272a );
a2274a <=( a2273a and a2268a );
a2277a <=( A298 and A200 );
a2281a <=( A302 and A300 );
a2282a <=( (not A299) and a2281a );
a2283a <=( a2282a and a2277a );
a2286a <=( (not A169) and A170 );
a2290a <=( (not A200) and A166 );
a2291a <=( (not A167) and a2290a );
a2292a <=( a2291a and a2286a );
a2295a <=( A298 and (not A201) );
a2299a <=( A301 and A300 );
a2300a <=( (not A299) and a2299a );
a2301a <=( a2300a and a2295a );
a2304a <=( (not A169) and A170 );
a2308a <=( (not A200) and A166 );
a2309a <=( (not A167) and a2308a );
a2310a <=( a2309a and a2304a );
a2313a <=( A298 and (not A201) );
a2317a <=( A302 and A300 );
a2318a <=( (not A299) and a2317a );
a2319a <=( a2318a and a2313a );
a2322a <=( (not A169) and A170 );
a2326a <=( (not A199) and A166 );
a2327a <=( (not A167) and a2326a );
a2328a <=( a2327a and a2322a );
a2331a <=( A298 and (not A200) );
a2335a <=( A301 and A300 );
a2336a <=( (not A299) and a2335a );
a2337a <=( a2336a and a2331a );
a2340a <=( (not A169) and A170 );
a2344a <=( (not A199) and A166 );
a2345a <=( (not A167) and a2344a );
a2346a <=( a2345a and a2340a );
a2349a <=( A298 and (not A200) );
a2353a <=( A302 and A300 );
a2354a <=( (not A299) and a2353a );
a2355a <=( a2354a and a2349a );
a2358a <=( (not A167) and A170 );
a2362a <=( (not A200) and A199 );
a2363a <=( (not A166) and a2362a );
a2364a <=( a2363a and a2358a );
a2368a <=( A298 and A202 );
a2369a <=( A201 and a2368a );
a2373a <=( A301 and A300 );
a2374a <=( (not A299) and a2373a );
a2375a <=( a2374a and a2369a );
a2378a <=( (not A167) and A170 );
a2382a <=( (not A200) and A199 );
a2383a <=( (not A166) and a2382a );
a2384a <=( a2383a and a2378a );
a2388a <=( A298 and A202 );
a2389a <=( A201 and a2388a );
a2393a <=( A302 and A300 );
a2394a <=( (not A299) and a2393a );
a2395a <=( a2394a and a2389a );
a2398a <=( (not A167) and A170 );
a2402a <=( (not A200) and A199 );
a2403a <=( (not A166) and a2402a );
a2404a <=( a2403a and a2398a );
a2408a <=( A298 and A203 );
a2409a <=( A201 and a2408a );
a2413a <=( A301 and A300 );
a2414a <=( (not A299) and a2413a );
a2415a <=( a2414a and a2409a );
a2418a <=( (not A167) and A170 );
a2422a <=( (not A200) and A199 );
a2423a <=( (not A166) and a2422a );
a2424a <=( a2423a and a2418a );
a2428a <=( A298 and A203 );
a2429a <=( A201 and a2428a );
a2433a <=( A302 and A300 );
a2434a <=( (not A299) and a2433a );
a2435a <=( a2434a and a2429a );
a2438a <=( A169 and A170 );
a2442a <=( (not A200) and A199 );
a2443a <=( (not A168) and a2442a );
a2444a <=( a2443a and a2438a );
a2448a <=( A298 and A202 );
a2449a <=( A201 and a2448a );
a2453a <=( A301 and A300 );
a2454a <=( (not A299) and a2453a );
a2455a <=( a2454a and a2449a );
a2458a <=( A169 and A170 );
a2462a <=( (not A200) and A199 );
a2463a <=( (not A168) and a2462a );
a2464a <=( a2463a and a2458a );
a2468a <=( A298 and A202 );
a2469a <=( A201 and a2468a );
a2473a <=( A302 and A300 );
a2474a <=( (not A299) and a2473a );
a2475a <=( a2474a and a2469a );
a2478a <=( A169 and A170 );
a2482a <=( (not A200) and A199 );
a2483a <=( (not A168) and a2482a );
a2484a <=( a2483a and a2478a );
a2488a <=( A298 and A203 );
a2489a <=( A201 and a2488a );
a2493a <=( A301 and A300 );
a2494a <=( (not A299) and a2493a );
a2495a <=( a2494a and a2489a );
a2498a <=( A169 and A170 );
a2502a <=( (not A200) and A199 );
a2503a <=( (not A168) and a2502a );
a2504a <=( a2503a and a2498a );
a2508a <=( A298 and A203 );
a2509a <=( A201 and a2508a );
a2513a <=( A302 and A300 );
a2514a <=( (not A299) and a2513a );
a2515a <=( a2514a and a2509a );
a2518a <=( A169 and (not A170) );
a2522a <=( (not A200) and A166 );
a2523a <=( A167 and a2522a );
a2524a <=( a2523a and a2518a );
a2528a <=( A298 and (not A203) );
a2529a <=( (not A202) and a2528a );
a2533a <=( A301 and A300 );
a2534a <=( (not A299) and a2533a );
a2535a <=( a2534a and a2529a );
a2538a <=( A169 and (not A170) );
a2542a <=( (not A200) and A166 );
a2543a <=( A167 and a2542a );
a2544a <=( a2543a and a2538a );
a2548a <=( A298 and (not A203) );
a2549a <=( (not A202) and a2548a );
a2553a <=( A302 and A300 );
a2554a <=( (not A299) and a2553a );
a2555a <=( a2554a and a2549a );
a2558a <=( A169 and (not A170) );
a2562a <=( (not A200) and (not A166) );
a2563a <=( (not A167) and a2562a );
a2564a <=( a2563a and a2558a );
a2568a <=( A298 and (not A203) );
a2569a <=( (not A202) and a2568a );
a2573a <=( A301 and A300 );
a2574a <=( (not A299) and a2573a );
a2575a <=( a2574a and a2569a );
a2578a <=( A169 and (not A170) );
a2582a <=( (not A200) and (not A166) );
a2583a <=( (not A167) and a2582a );
a2584a <=( a2583a and a2578a );
a2588a <=( A298 and (not A203) );
a2589a <=( (not A202) and a2588a );
a2593a <=( A302 and A300 );
a2594a <=( (not A299) and a2593a );
a2595a <=( a2594a and a2589a );
a2598a <=( (not A167) and (not A169) );
a2602a <=( (not A200) and A199 );
a2603a <=( (not A166) and a2602a );
a2604a <=( a2603a and a2598a );
a2608a <=( A298 and A202 );
a2609a <=( A201 and a2608a );
a2613a <=( A301 and A300 );
a2614a <=( (not A299) and a2613a );
a2615a <=( a2614a and a2609a );
a2618a <=( (not A167) and (not A169) );
a2622a <=( (not A200) and A199 );
a2623a <=( (not A166) and a2622a );
a2624a <=( a2623a and a2618a );
a2628a <=( A298 and A202 );
a2629a <=( A201 and a2628a );
a2633a <=( A302 and A300 );
a2634a <=( (not A299) and a2633a );
a2635a <=( a2634a and a2629a );
a2638a <=( (not A167) and (not A169) );
a2642a <=( (not A200) and A199 );
a2643a <=( (not A166) and a2642a );
a2644a <=( a2643a and a2638a );
a2648a <=( A298 and A203 );
a2649a <=( A201 and a2648a );
a2653a <=( A301 and A300 );
a2654a <=( (not A299) and a2653a );
a2655a <=( a2654a and a2649a );
a2658a <=( (not A167) and (not A169) );
a2662a <=( (not A200) and A199 );
a2663a <=( (not A166) and a2662a );
a2664a <=( a2663a and a2658a );
a2668a <=( A298 and A203 );
a2669a <=( A201 and a2668a );
a2673a <=( A302 and A300 );
a2674a <=( (not A299) and a2673a );
a2675a <=( a2674a and a2669a );
a2678a <=( (not A169) and A170 );
a2682a <=( (not A200) and (not A166) );
a2683a <=( A167 and a2682a );
a2684a <=( a2683a and a2678a );
a2688a <=( A298 and (not A203) );
a2689a <=( (not A202) and a2688a );
a2693a <=( A301 and A300 );
a2694a <=( (not A299) and a2693a );
a2695a <=( a2694a and a2689a );
a2698a <=( (not A169) and A170 );
a2702a <=( (not A200) and (not A166) );
a2703a <=( A167 and a2702a );
a2704a <=( a2703a and a2698a );
a2708a <=( A298 and (not A203) );
a2709a <=( (not A202) and a2708a );
a2713a <=( A302 and A300 );
a2714a <=( (not A299) and a2713a );
a2715a <=( a2714a and a2709a );
a2718a <=( (not A169) and A170 );
a2722a <=( (not A200) and A166 );
a2723a <=( (not A167) and a2722a );
a2724a <=( a2723a and a2718a );
a2728a <=( A298 and (not A203) );
a2729a <=( (not A202) and a2728a );
a2733a <=( A301 and A300 );
a2734a <=( (not A299) and a2733a );
a2735a <=( a2734a and a2729a );
a2738a <=( (not A169) and A170 );
a2742a <=( (not A200) and A166 );
a2743a <=( (not A167) and a2742a );
a2744a <=( a2743a and a2738a );
a2748a <=( A298 and (not A203) );
a2749a <=( (not A202) and a2748a );
a2753a <=( A302 and A300 );
a2754a <=( (not A299) and a2753a );
a2755a <=( a2754a and a2749a );
a2758a <=( (not A169) and (not A170) );
a2762a <=( (not A200) and A199 );
a2763a <=( (not A168) and a2762a );
a2764a <=( a2763a and a2758a );
a2768a <=( A298 and A202 );
a2769a <=( A201 and a2768a );
a2773a <=( A301 and A300 );
a2774a <=( (not A299) and a2773a );
a2775a <=( a2774a and a2769a );
a2778a <=( (not A169) and (not A170) );
a2782a <=( (not A200) and A199 );
a2783a <=( (not A168) and a2782a );
a2784a <=( a2783a and a2778a );
a2788a <=( A298 and A202 );
a2789a <=( A201 and a2788a );
a2793a <=( A302 and A300 );
a2794a <=( (not A299) and a2793a );
a2795a <=( a2794a and a2789a );
a2798a <=( (not A169) and (not A170) );
a2802a <=( (not A200) and A199 );
a2803a <=( (not A168) and a2802a );
a2804a <=( a2803a and a2798a );
a2808a <=( A298 and A203 );
a2809a <=( A201 and a2808a );
a2813a <=( A301 and A300 );
a2814a <=( (not A299) and a2813a );
a2815a <=( a2814a and a2809a );
a2818a <=( (not A169) and (not A170) );
a2822a <=( (not A200) and A199 );
a2823a <=( (not A168) and a2822a );
a2824a <=( a2823a and a2818a );
a2828a <=( A298 and A203 );
a2829a <=( A201 and a2828a );
a2833a <=( A302 and A300 );
a2834a <=( (not A299) and a2833a );
a2835a <=( a2834a and a2829a );
a2839a <=( A167 and (not A168) );
a2840a <=( A169 and a2839a );
a2844a <=( (not A200) and A199 );
a2845a <=( (not A166) and a2844a );
a2846a <=( a2845a and a2840a );
a2850a <=( A298 and A202 );
a2851a <=( A201 and a2850a );
a2855a <=( A301 and A300 );
a2856a <=( (not A299) and a2855a );
a2857a <=( a2856a and a2851a );
a2861a <=( A167 and (not A168) );
a2862a <=( A169 and a2861a );
a2866a <=( (not A200) and A199 );
a2867a <=( (not A166) and a2866a );
a2868a <=( a2867a and a2862a );
a2872a <=( A298 and A202 );
a2873a <=( A201 and a2872a );
a2877a <=( A302 and A300 );
a2878a <=( (not A299) and a2877a );
a2879a <=( a2878a and a2873a );
a2883a <=( A167 and (not A168) );
a2884a <=( A169 and a2883a );
a2888a <=( (not A200) and A199 );
a2889a <=( (not A166) and a2888a );
a2890a <=( a2889a and a2884a );
a2894a <=( A298 and A203 );
a2895a <=( A201 and a2894a );
a2899a <=( A301 and A300 );
a2900a <=( (not A299) and a2899a );
a2901a <=( a2900a and a2895a );
a2905a <=( A167 and (not A168) );
a2906a <=( A169 and a2905a );
a2910a <=( (not A200) and A199 );
a2911a <=( (not A166) and a2910a );
a2912a <=( a2911a and a2906a );
a2916a <=( A298 and A203 );
a2917a <=( A201 and a2916a );
a2921a <=( A302 and A300 );
a2922a <=( (not A299) and a2921a );
a2923a <=( a2922a and a2917a );
a2927a <=( (not A167) and (not A168) );
a2928a <=( A169 and a2927a );
a2932a <=( (not A200) and A199 );
a2933a <=( A166 and a2932a );
a2934a <=( a2933a and a2928a );
a2938a <=( A298 and A202 );
a2939a <=( A201 and a2938a );
a2943a <=( A301 and A300 );
a2944a <=( (not A299) and a2943a );
a2945a <=( a2944a and a2939a );
a2949a <=( (not A167) and (not A168) );
a2950a <=( A169 and a2949a );
a2954a <=( (not A200) and A199 );
a2955a <=( A166 and a2954a );
a2956a <=( a2955a and a2950a );
a2960a <=( A298 and A202 );
a2961a <=( A201 and a2960a );
a2965a <=( A302 and A300 );
a2966a <=( (not A299) and a2965a );
a2967a <=( a2966a and a2961a );
a2971a <=( (not A167) and (not A168) );
a2972a <=( A169 and a2971a );
a2976a <=( (not A200) and A199 );
a2977a <=( A166 and a2976a );
a2978a <=( a2977a and a2972a );
a2982a <=( A298 and A203 );
a2983a <=( A201 and a2982a );
a2987a <=( A301 and A300 );
a2988a <=( (not A299) and a2987a );
a2989a <=( a2988a and a2983a );
a2993a <=( (not A167) and (not A168) );
a2994a <=( A169 and a2993a );
a2998a <=( (not A200) and A199 );
a2999a <=( A166 and a2998a );
a3000a <=( a2999a and a2994a );
a3004a <=( A298 and A203 );
a3005a <=( A201 and a3004a );
a3009a <=( A302 and A300 );
a3010a <=( (not A299) and a3009a );
a3011a <=( a3010a and a3005a );
a3015a <=( A167 and (not A168) );
a3016a <=( (not A169) and a3015a );
a3020a <=( (not A200) and A199 );
a3021a <=( A166 and a3020a );
a3022a <=( a3021a and a3016a );
a3026a <=( A298 and A202 );
a3027a <=( A201 and a3026a );
a3031a <=( A301 and A300 );
a3032a <=( (not A299) and a3031a );
a3033a <=( a3032a and a3027a );
a3037a <=( A167 and (not A168) );
a3038a <=( (not A169) and a3037a );
a3042a <=( (not A200) and A199 );
a3043a <=( A166 and a3042a );
a3044a <=( a3043a and a3038a );
a3048a <=( A298 and A202 );
a3049a <=( A201 and a3048a );
a3053a <=( A302 and A300 );
a3054a <=( (not A299) and a3053a );
a3055a <=( a3054a and a3049a );
a3059a <=( A167 and (not A168) );
a3060a <=( (not A169) and a3059a );
a3064a <=( (not A200) and A199 );
a3065a <=( A166 and a3064a );
a3066a <=( a3065a and a3060a );
a3070a <=( A298 and A203 );
a3071a <=( A201 and a3070a );
a3075a <=( A301 and A300 );
a3076a <=( (not A299) and a3075a );
a3077a <=( a3076a and a3071a );
a3081a <=( A167 and (not A168) );
a3082a <=( (not A169) and a3081a );
a3086a <=( (not A200) and A199 );
a3087a <=( A166 and a3086a );
a3088a <=( a3087a and a3082a );
a3092a <=( A298 and A203 );
a3093a <=( A201 and a3092a );
a3097a <=( A302 and A300 );
a3098a <=( (not A299) and a3097a );
a3099a <=( a3098a and a3093a );
end x25_8x_behav;
| gpl-3.0 | 46251ff438d28b813d00e262998b278b | 0.601782 | 2.144053 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/pvr.vhd | 1 | 28,350 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
KlFwHfKTRwCKKQ8OsOJrLXmWQaAqsuGYzM7jt9i6PHr5MGF1EBQkd7mGzHXD6w9oDR0BfAjDqPSn
e40Tq2SNYg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
DUtMNb0k8hb7CRCQirSapxdDFoa3oF38Yt/E3OO7iFkmV/dkZCfbtzE6uaOSY6nBP58SXp0M2jQT
bi0qYbcLovfrcGM3st2pUXmj/CrfXRibJVNGf73KfBRSiZmFynOcVibOoiQqhTPo0s5qvpIpWtg0
CPIMMzfh7Hv1BmIcYu4=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Sh2hLsQeL1/cyjcRJiClfqRYOnHqNAc9Fldt/78v+5tKCdFyBdONON7Ex4Z/+iHDJRTH4zWRUJMM
nud2Rm/oxGit6YllOJ9HuUue4OUITY5FiVvPcN9tLh2JQLRVOL7/1Lg3X824V+ZqmvXuTTrGaQ9B
m0HIfcJV8Y4vyfcgdJ6YdokHV1LXVRBcGVH9baq+tCiqXvVKNwXrZzLJ3msO0g4vYM4EwNBZ+VK0
5ZpYlth4lbnsrtyRttLyK1FogebZHsr9T86i5QocJqPEcVvX7+AF71PaayshCF//IvB5jYRbJ5je
5UbNd5sTg8JAa/brmxEZcptS168rb4ZAB0h+VA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
IoJWy/nuaE9iV7on2puma7EtEpIIQXrBepH5REm0uLbUxWPIccYO9znRab8E3v5cLhLc/2unMwhz
5fOKcGSXzdMED3hqwZx0yxYDUNIHGsrLPd26Fu6+XqqRfHg36MXXfYtE8AC+6s4bLLTvSzq2a8k6
0VHFgjEZQNF3Hdb9Azs=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 19248)
`protect data_block
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`protect end_protected
| apache-2.0 | 0c9fd28ee1e10e63f6c54a0b3e560b6f | 0.944868 | 1.845703 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/mmu_utlb_ram.vhd | 1 | 10,088 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5728)
`protect data_block
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| apache-2.0 | e9817bb2b67b903c927ed142a8c78668 | 0.924762 | 1.902319 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/axi_master_burst_v2_0/1af76933/hdl/src/vhdl/axi_master_burst_wr_status_cntl.vhd | 1 | 52,306 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- Filename: axi_master_burst_wr_status_cntl.vhd
--
-- Description:
-- This file implements the AXI Master Burst Write Status Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_master_burst_wr_status_cntl.vhd
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.0 $
-- Date: $1/19/2011$
--
-- History:
-- DET 1/19/2011 Initial
-- ~~~~~~
-- - Adapted from AXI dataMover V2_00_a axi_datamover_wr_status_cntl.vhd
-- ^^^^^^
--
-- DET 2/15/2011 Initial for EDk 13.2
-- ~~~~~~
-- -- Per CR593812
-- - Modifications to remove unused features to improve Code coverage.
-- Used "-- coverage off" and "-- coverage on" strings.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI MASTER BURST to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_master_burst_v2_0;
use axi_master_burst_v2_0.axi_master_burst_fifo;
-------------------------------------------------------------------------------
entity axi_master_burst_wr_status_cntl is
generic (
C_ENABLE_STORE_FORWARD : Integer range 0 to 1 := 0;
C_SF_BYTES_RCVD_WIDTH : Integer range 1 to 23 := 1;
C_STS_FIFO_DEPTH : Integer range 1 to 32 := 8;
C_STS_WIDTH : Integer range 8 to 32 := 8;
C_TAG_WIDTH : Integer range 1 to 8 := 4;
C_FAMILY : String := "virtex7"
);
port (
-- Clock input
primary_aclk : in std_logic;
-- Primary synchronization clock for the Master side
-- interface and internal logic. It is also used
-- for the User interface synchronization when
-- C_STSCMD_IS_ASYNC = 0.
-- Reset input
mmap_reset : in std_logic;
-- Reset used for the internal master logic
-- Soft Shutdown internal interface ---------------------------
rst2wsc_stop_request : in std_logic;
-- Active high soft stop request to modules
wsc2rst_stop_cmplt : Out std_logic;
-- Active high indication that the Write status Controller
-- has completed any pending transfers committed by the
-- Address Controller after a stop has been requested by
-- the Reset module.
addr2wsc_addr_posted : In std_logic ;
-- Indication from the Address Channel Controller to the
-- write Status Controller that an address has been posted
-- to the AXI Address Channel
-- Write Response Channel Interface --------------------------
s2mm_bresp : In std_logic_vector(1 downto 0);
-- The Write response value
s2mm_bvalid : In std_logic ;
-- Indication from the Write Response Channel that a new
-- write status input is valid
s2mm_bready : out std_logic ;
-- Indication to the Write Response Channel that the
-- Status module is ready for a new status input
-- Command Calculator Interface --------------------------
calc2wsc_calc_error : in std_logic ;
-- Indication from the Command Calculator that a calculation
-- error has occured.
-- Address Controller Status --------------------------
addr2wsc_calc_error : In std_logic ;
-- Indication from the Address Channel Controller that it
-- has encountered a calculation error from the command
-- Calculator
addr2wsc_fifo_empty : In std_logic ;
-- Indication from the Address Controller FIFO that it
-- is empty (no commands pending)
-- Data Controller Status --------------------------
data2wsc_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- The command tag
data2wsc_calc_error : In std_logic ;
-- Indication from the Data Channel Controller FIFO that it
-- has encountered a Calculation error in the command pipe
data2wsc_last_error : In std_logic ;
-- Indication from the Write Data Channel Controller that a
-- premature TLAST assertion was encountered on the incoming
-- Stream Channel
data2wsc_cmd_cmplt : In std_logic ;
-- Indication from the Data Channel Controller that the
-- corresponding status is the final status for a parent
-- command fetched from the command FIFO
data2wsc_valid : In std_logic ;
-- Indication from the Data Channel Controller FIFO that it
-- has a new tag/error status to transfer
wsc2data_ready : out std_logic ;
-- Indication to the Data Channel Controller FIFO that the
-- Status module is ready for a new tag/error status input
data2wsc_eop : In std_logic;
-- Input from the Write Data Controller indicating that the
-- associated command status also corresponds to a End of Packet
-- marker for the input Stream. This is only used when Store and
-- Forward is enabled in the S2MM.
data2wsc_bytes_rcvd : In std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0);
-- Input from the Write Data Controller indicating the actual
-- number of bytes received from the Stream input for the
-- corresponding command status. This is only used when Store and
-- Forward is enabled in the S2MM.
-- Command/Status Interface --------------------------
wsc2stat_status : Out std_logic_vector(C_STS_WIDTH-1 downto 0);
-- Read Status value collected during a Read Data transfer
-- Output to the Command/Status Module
stat2wsc_status_ready : In std_logic;
-- Input from the Command/Status Module indicating that the
-- Status Reg/FIFO is Full and cannot accept more staus writes
wsc2stat_status_valid : Out std_logic ;
-- Control Signal to Write the Status value to the Status
-- Reg/FIFO
-- Address and Data Controller Pipe halt --------------------------
wsc2mstr_halt_pipe : Out std_logic
-- Indication to Halt the Data and Address Command pipeline due
-- to the Status pipe getting full at some point
);
end entity axi_master_burst_wr_status_cntl;
architecture implementation of axi_master_burst_wr_status_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
-- coverage off
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
-- coverage on
end if;
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant OKAY : std_logic_vector(1 downto 0) := "00";
Constant EXOKAY : std_logic_vector(1 downto 0) := "01";
Constant SLVERR : std_logic_vector(1 downto 0) := "10";
Constant DECERR : std_logic_vector(1 downto 0) := "11";
Constant STAT_RSVD : std_logic_vector(3 downto 0) := "0000";
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant STAT_REG_TAG_WIDTH : integer := 4;
Constant SYNC_FIFO_SELECT : integer := 0;
Constant SRL_FIFO_TYPE : integer := 2;
Constant DCNTL_SFIFO_DEPTH : integer := C_STS_FIFO_DEPTH;
Constant DCNTL_STATCNT_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits
Constant DCNTL_HALT_THRES : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(DCNTL_SFIFO_DEPTH-2,DCNTL_STATCNT_WIDTH);
Constant DCNTL_STATCNT_ZERO : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0');
Constant DCNTL_STATCNT_MAX : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(DCNTL_SFIFO_DEPTH,DCNTL_STATCNT_WIDTH);
Constant DCNTL_STATCNT_ONE : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, DCNTL_STATCNT_WIDTH);
Constant WRESP_WIDTH : integer := 2;
Constant WRESP_SFIFO_WIDTH : integer := WRESP_WIDTH;
Constant WRESP_SFIFO_DEPTH : integer := DCNTL_SFIFO_DEPTH;
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_valid_status_rdy : std_logic := '0';
signal sig_decerr : std_logic := '0';
signal sig_slverr : std_logic := '0';
signal sig_coelsc_okay_reg : std_logic := '0';
signal sig_coelsc_interr_reg : std_logic := '0';
signal sig_coelsc_decerr_reg : std_logic := '0';
signal sig_coelsc_slverr_reg : std_logic := '0';
signal sig_coelsc_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_coelsc_reg : std_logic := '0';
signal sig_push_coelsc_reg : std_logic := '0';
signal sig_coelsc_reg_empty : std_logic := '0';
signal sig_coelsc_reg_full : std_logic := '0';
signal sig_tag2status : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data_err_reg : std_logic := '0';
signal sig_data_last_err_reg : std_logic := '0';
signal sig_data_cmd_cmplt_reg : std_logic := '0';
signal sig_bresp_reg : std_logic_vector(1 downto 0) := (others => '0');
signal sig_push_status : std_logic := '0';
Signal sig_status_push_ok : std_logic := '0';
signal sig_status_valid : std_logic := '0';
signal sig_wsc2data_ready : std_logic := '0';
signal sig_s2mm_bready : std_logic := '0';
signal sig_wresp_sfifo_in : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_wresp_sfifo_out : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_wresp_sfifo_wr_valid : std_logic := '0';
signal sig_wresp_sfifo_wr_ready : std_logic := '0';
signal sig_wresp_sfifo_wr_full : std_logic := '0';
signal sig_wresp_sfifo_rd_valid : std_logic := '0';
signal sig_wresp_sfifo_rd_ready : std_logic := '0';
signal sig_wresp_sfifo_rd_empty : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_eq_1 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_no_posted_cmds : std_logic := '0';
signal sig_addr_posted : std_logic := '0';
signal sig_all_cmds_done : std_logic := '0';
signal sig_wsc2stat_status : std_logic_vector(C_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_wr_valid : std_logic := '0';
signal sig_dcntl_sfifo_wr_ready : std_logic := '0';
signal sig_dcntl_sfifo_wr_full : std_logic := '0';
signal sig_dcntl_sfifo_rd_valid : std_logic := '0';
signal sig_dcntl_sfifo_rd_ready : std_logic := '0';
signal sig_dcntl_sfifo_rd_empty : std_logic := '0';
signal sig_wdc_statcnt : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_statcnt : std_logic := '0';
signal sig_decr_statcnt : std_logic := '0';
signal sig_statcnt_eq_max : std_logic := '0';
signal sig_statcnt_eq_0 : std_logic := '0';
signal sig_statcnt_gt_eq_thres : std_logic := '0';
signal sig_wdc_status_going_full : std_logic := '0';
begin --(architecture implementation)
-- Assign the ready output to the AXI Write Response Channel
s2mm_bready <= sig_s2mm_bready or
sig_halt_reg; -- force bready if a Halt is requested
-- Assign the ready output to the Data Controller status interface
wsc2data_ready <= sig_wsc2data_ready;
-- Assign the status valid output control to the Status FIFO
wsc2stat_status_valid <= sig_status_valid ;
-- Formulate the status output value to the Status FIFO
wsc2stat_status <= sig_wsc2stat_status;
-- Formulate the status write request signal
sig_status_valid <= sig_push_status;
-- Indicate the desire to push a coelesced status word
-- to the Status FIFO
sig_push_status <= sig_coelsc_reg_full;
-- Detect that a push of a new status word is completing
sig_status_push_ok <= sig_status_valid and
stat2wsc_status_ready;
sig_pop_coelsc_reg <= sig_status_push_ok;
-- Signal a halt to the execution pipe if new status
-- is valid but the Status FIFO is not accepting it or
-- the WDC Status FIFO is going full
wsc2mstr_halt_pipe <= (sig_status_valid and
not(stat2wsc_status_ready)) or
sig_wdc_status_going_full;
-- Monitor the Status capture registers to detect a
-- qualified Status set and push to the coelescing register
-- when available to do so
sig_push_coelsc_reg <= sig_valid_status_rdy and
sig_coelsc_reg_empty;
sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and
sig_dcntl_sfifo_rd_valid) or
(sig_data_err_reg and
sig_dcntl_sfifo_rd_valid);
-- Decode the AXI MMap Read Respose
sig_decerr <= '1'
When sig_bresp_reg = DECERR
Else '0';
sig_slverr <= '1'
When sig_bresp_reg = SLVERR
Else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_LE_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is less than or equal to the available number
-- of bits in the Status word.
--
------------------------------------------------------------
GEN_TAG_LE_STAT : if (TAG_WIDTH <= STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_small : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0');
begin
sig_tag2status <= lsig_temp_tag_small;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_SMALL_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg)
begin
-- Set default value
lsig_temp_tag_small <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_small(TAG_WIDTH-1 downto 0) <= sig_coelsc_tag_reg;
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_LE_STAT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_GT_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is greater than the available number of
-- bits in the Status word. The upper bits of the TAG are
-- clipped off (discarded).
--
------------------------------------------------------------
GEN_TAG_GT_STAT : if (TAG_WIDTH > STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_big : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0');
begin
sig_tag2status <= lsig_temp_tag_big;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_BIG_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg)
begin
-- Set default value
lsig_temp_tag_big <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_big <= sig_coelsc_tag_reg(STAT_REG_TAG_WIDTH-1 downto 0);
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_GT_STAT;
-------------------------------------------------------------------------
-- Write Response Channel input FIFO and logic
-- BRESP is the only fifo data
sig_wresp_sfifo_in <= s2mm_bresp;
-- The fifo output is already in the right format
sig_bresp_reg <= sig_wresp_sfifo_out;
-- Write Side assignments
sig_wresp_sfifo_wr_valid <= s2mm_bvalid;
sig_s2mm_bready <= sig_wresp_sfifo_wr_ready;
-- read Side ready assignment
sig_wresp_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_WRESP_STATUS_FIFO
--
-- Description:
-- Instance for the AXI Write Response FIFO
--
------------------------------------------------------------
I_WRESP_STATUS_FIFO : entity axi_master_burst_v2_0.axi_master_burst_fifo
generic map (
C_DWIDTH => WRESP_SFIFO_WIDTH ,
C_DEPTH => WRESP_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_wresp_sfifo_wr_valid ,
fifo_wr_tready => sig_wresp_sfifo_wr_ready ,
fifo_wr_tdata => sig_wresp_sfifo_in ,
fifo_wr_full => sig_wresp_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_wresp_sfifo_rd_valid ,
fifo_rd_tready => sig_wresp_sfifo_rd_ready ,
fifo_rd_tdata => sig_wresp_sfifo_out ,
fifo_rd_empty => sig_wresp_sfifo_rd_empty
);
-------- Write Data Controller Status FIFO Going Full Logic -------------
sig_incr_statcnt <= sig_dcntl_sfifo_wr_valid and
sig_dcntl_sfifo_wr_ready;
sig_decr_statcnt <= sig_dcntl_sfifo_rd_valid and
sig_dcntl_sfifo_rd_ready;
sig_statcnt_eq_max <= '1'
when (sig_wdc_statcnt = DCNTL_STATCNT_MAX)
Else '0';
sig_statcnt_eq_0 <= '1'
when (sig_wdc_statcnt = DCNTL_STATCNT_ZERO)
Else '0';
sig_statcnt_gt_eq_thres <= '1'
when (sig_wdc_statcnt >= DCNTL_HALT_THRES)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WDC_GOING_FULL_FLOP
--
-- Process Description:
-- Implements a flop for the WDC Status FIFO going full flag.
--
-------------------------------------------------------------
IMP_WDC_GOING_FULL_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wdc_status_going_full <= '0';
else
sig_wdc_status_going_full <= sig_statcnt_gt_eq_thres;
end if;
end if;
end process IMP_WDC_GOING_FULL_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DCNTL_FIFO_CNTR
--
-- Process Description:
-- Implements a simple counter keeping track of the number
-- of entries in the WDC Status FIFO. If the Status FIFO gets
-- too full, the S2MM Data Pipe has to be halted.
--
-------------------------------------------------------------
IMP_DCNTL_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wdc_statcnt <= (others => '0');
elsif (sig_incr_statcnt = '1' and
sig_decr_statcnt = '0' and
sig_statcnt_eq_max = '0') then
sig_wdc_statcnt <= sig_wdc_statcnt + DCNTL_STATCNT_ONE;
elsif (sig_incr_statcnt = '0' and
sig_decr_statcnt = '1' and
sig_statcnt_eq_0 = '0') then
sig_wdc_statcnt <= sig_wdc_statcnt - DCNTL_STATCNT_ONE;
else
null; -- Hold current count value
end if;
end if;
end process IMP_DCNTL_FIFO_CNTR;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_STORE_FORWARD
--
-- If Generate Description:
-- Implements the logic needed when Store and Forward is
-- not enabled in the S2MM function.
--
------------------------------------------------------------
GEN_OMIT_STORE_FORWARD : if (C_ENABLE_STORE_FORWARD = 0) generate
-- Local Constants
Constant DCNTL_SFIFO_WIDTH : integer := STAT_REG_TAG_WIDTH+3;
Constant DCNTL_SFIFO_CMD_CMPLT_INDEX : integer := 0;
Constant DCNTL_SFIFO_TLAST_ERR_INDEX : integer := 1;
Constant DCNTL_SFIFO_CALC_ERR_INDEX : integer := 2;
Constant DCNTL_SFIFO_TAG_INDEX : integer := DCNTL_SFIFO_CALC_ERR_INDEX+1;
-- local signals
signal sig_dcntl_sfifo_in : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_out : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
begin
sig_wsc2stat_status <= sig_coelsc_okay_reg &
sig_coelsc_slverr_reg &
sig_coelsc_decerr_reg &
sig_coelsc_interr_reg &
sig_tag2status;
-----------------------------------------------------------------------------
-- Data Controller Status FIFO and Logic
-- Concatonate Input bits to build Dcntl fifo data word
sig_dcntl_sfifo_in <= data2wsc_tag & -- bit 3 to tag Width+2
data2wsc_calc_error & -- bit 2
data2wsc_last_error & -- bit 1
data2wsc_cmd_cmplt ; -- bit 0
-- Rip the DCntl fifo outputs back to constituant pieces
sig_data_tag_reg <= sig_dcntl_sfifo_out((DCNTL_SFIFO_TAG_INDEX+STAT_REG_TAG_WIDTH)-1 downto
DCNTL_SFIFO_TAG_INDEX);
sig_data_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CALC_ERR_INDEX) ;
sig_data_last_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_TLAST_ERR_INDEX);
sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CMD_CMPLT_INDEX);
-- Data Control Valid/Ready assignments
sig_dcntl_sfifo_wr_valid <= data2wsc_valid ;
sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready;
-- read side ready assignment
sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_DATA_CNTL_STATUS_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_STATUS_FIFO : entity axi_master_burst_v2_0.axi_master_burst_fifo
generic map (
C_DWIDTH => DCNTL_SFIFO_WIDTH ,
C_DEPTH => DCNTL_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid ,
fifo_wr_tready => sig_dcntl_sfifo_wr_ready ,
fifo_wr_tdata => sig_dcntl_sfifo_in ,
fifo_wr_full => sig_dcntl_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid ,
fifo_rd_tready => sig_dcntl_sfifo_rd_ready ,
fifo_rd_tdata => sig_dcntl_sfifo_out ,
fifo_rd_empty => sig_dcntl_sfifo_rd_empty
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: STATUS_COELESC_REG
--
-- Process Description:
-- Implement error status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status FIFO.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_coelsc_reg = '1') then
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_data_tag_reg;
sig_coelsc_interr_reg <= sig_data_err_reg or
sig_data_last_err_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= not(sig_data_err_reg) and
(sig_decerr or
sig_coelsc_decerr_reg);
sig_coelsc_slverr_reg <= not(sig_data_err_reg) and
(sig_slverr or
sig_coelsc_slverr_reg);
sig_coelsc_okay_reg <= not(sig_decerr or
sig_coelsc_decerr_reg or
sig_slverr or
sig_coelsc_slverr_reg or
sig_data_err_reg or
sig_data_last_err_reg or
sig_coelsc_interr_reg
);
sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg;
sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg);
else
null; -- hold current state
end if;
end if;
end process STATUS_COELESC_REG;
end generate GEN_OMIT_STORE_FORWARD;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ENABLE_STORE_FORWARD
--
-- If Generate Description:
-- Implements the logic needed when Store and Forward is
-- enabled in the S2MM function. Primary difference is the
-- addition to the reported status of the End of Packet
-- marker (EOP) and the received byte count for the parent
-- command.
--
------------------------------------------------------------
GEN_ENABLE_STORE_FORWARD : if (C_ENABLE_STORE_FORWARD = 1) generate
-- Local Constants
Constant SF_DCNTL_SFIFO_WIDTH : integer := TAG_WIDTH +
C_SF_BYTES_RCVD_WIDTH + 3;
Constant SF_SFIFO_LS_TAG_INDEX : integer := 0;
Constant SF_SFIFO_MS_TAG_INDEX : integer := SF_SFIFO_LS_TAG_INDEX + (TAG_WIDTH-1);
Constant SF_SFIFO_CALC_ERR_INDEX : integer := SF_SFIFO_MS_TAG_INDEX+1;
Constant SF_SFIFO_CMD_CMPLT_INDEX : integer := SF_SFIFO_CALC_ERR_INDEX+1;
Constant SF_SFIFO_LS_BYTES_RCVD_INDEX : integer := SF_SFIFO_CMD_CMPLT_INDEX+1;
Constant SF_SFIFO_MS_BYTES_RCVD_INDEX : integer := SF_SFIFO_LS_BYTES_RCVD_INDEX+
(C_SF_BYTES_RCVD_WIDTH-1);
Constant SF_SFIFO_EOP_INDEX : integer := SF_SFIFO_MS_BYTES_RCVD_INDEX+1;
Constant BYTES_RCVD_FIELD_WIDTH : integer := 23;
-- local signals
signal sig_dcntl_sfifo_in : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_out : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_data_eop : std_logic := '0';
signal sig_coelsc_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_coelsc_eop : std_logic := '0';
signal sig_coelsc_bytes_rcvd_pad : std_logic_vector(BYTES_RCVD_FIELD_WIDTH-1 downto 0) := (others => '0');
begin
sig_wsc2stat_status <= sig_coelsc_eop &
sig_coelsc_bytes_rcvd_pad &
sig_coelsc_okay_reg &
sig_coelsc_slverr_reg &
sig_coelsc_decerr_reg &
sig_coelsc_interr_reg &
sig_tag2status;
-----------------------------------------------------------------------------
-- Data Controller Status FIFO and Logic
-- Concatonate Input bits to build Dcntl fifo input data word
sig_dcntl_sfifo_in <= data2wsc_eop & -- ms bit
data2wsc_bytes_rcvd & -- bit 7 to C_SF_BYTES_RCVD_WIDTH+7
data2wsc_cmd_cmplt & -- bit 6
data2wsc_calc_error & -- bit 4
data2wsc_tag; -- bits 0 to 3
-- Rip the DCntl fifo outputs back to constituant pieces
sig_data_eop <= sig_dcntl_sfifo_out(SF_SFIFO_EOP_INDEX);
sig_data_bytes_rcvd <= sig_dcntl_sfifo_out(SF_SFIFO_MS_BYTES_RCVD_INDEX downto
SF_SFIFO_LS_BYTES_RCVD_INDEX);
sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CMD_CMPLT_INDEX);
sig_data_err_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CALC_ERR_INDEX);
sig_data_tag_reg <= sig_dcntl_sfifo_out(SF_SFIFO_MS_TAG_INDEX downto
SF_SFIFO_LS_TAG_INDEX) ;
-- Data Control Valid/Ready assignments
sig_dcntl_sfifo_wr_valid <= data2wsc_valid ;
sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready;
-- read side ready assignment
sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_SF_DATA_CNTL_STATUS_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO when Store and
-- Forward is included.
--
------------------------------------------------------------
I_SF_DATA_CNTL_STATUS_FIFO : entity axi_master_burst_v2_0.axi_master_burst_fifo
generic map (
C_DWIDTH => SF_DCNTL_SFIFO_WIDTH ,
C_DEPTH => DCNTL_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid ,
fifo_wr_tready => sig_dcntl_sfifo_wr_ready ,
fifo_wr_tdata => sig_dcntl_sfifo_in ,
fifo_wr_full => sig_dcntl_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid ,
fifo_rd_tready => sig_dcntl_sfifo_rd_ready ,
fifo_rd_tdata => sig_dcntl_sfifo_out ,
fifo_rd_empty => sig_dcntl_sfifo_rd_empty
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SF_STATUS_COELESC_REG
--
-- Process Description:
-- Implement error status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status FIFO.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
SF_STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_coelsc_reg = '1') then
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_bytes_rcvd <= (others => '0');
sig_coelsc_eop <= '0';
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_data_tag_reg;
sig_coelsc_interr_reg <= sig_data_err_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= not(sig_data_err_reg) and
(sig_decerr or
sig_coelsc_decerr_reg);
sig_coelsc_slverr_reg <= not(sig_data_err_reg) and
(sig_slverr or
sig_coelsc_slverr_reg);
sig_coelsc_okay_reg <= not(sig_decerr or
sig_coelsc_decerr_reg or
sig_slverr or
sig_coelsc_slverr_reg or
sig_data_err_reg or
sig_coelsc_interr_reg
);
sig_coelsc_bytes_rcvd <= sig_data_bytes_rcvd;
sig_coelsc_eop <= sig_data_eop;
sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg;
sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg);
else
null; -- hold current state
end if;
end if;
end process SF_STATUS_COELESC_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: SF_GEN_PAD_BYTES_RCVD
--
-- If Generate Description:
-- Pad the bytes received value with zeros to fill in the
-- status field width.
--
--
------------------------------------------------------------
SF_GEN_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH < BYTES_RCVD_FIELD_WIDTH) generate
begin
sig_coelsc_bytes_rcvd_pad(BYTES_RCVD_FIELD_WIDTH-1 downto
C_SF_BYTES_RCVD_WIDTH) <= (others => '0');
sig_coelsc_bytes_rcvd_pad(C_SF_BYTES_RCVD_WIDTH-1 downto 0) <= sig_coelsc_bytes_rcvd;
end generate SF_GEN_PAD_BYTES_RCVD;
------------------------------------------------------------
-- If Generate
--
-- Label: SF_GEN_NO_PAD_BYTES_RCVD
--
-- If Generate Description:
-- No padding required for the bytes received value.
--
--
------------------------------------------------------------
SF_GEN_NO_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH = BYTES_RCVD_FIELD_WIDTH) generate
begin
sig_coelsc_bytes_rcvd_pad <= sig_coelsc_bytes_rcvd; -- no pad required
end generate SF_GEN_NO_PAD_BYTES_RCVD;
end generate GEN_ENABLE_STORE_FORWARD;
------- Soft Shutdown Logic -------------------------------
-- Address Posted Counter Logic ---------------------t-----------------
-- Supports soft shutdown by tracking when all commited Write
-- transfers to the AXI Bus have had corresponding Write Status
-- Reponses Received.
sig_addr_posted <= addr2wsc_addr_posted ;
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_s2mm_bready and
s2mm_bvalid ;
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_eq_1 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ONE)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a counter for the tracking
-- if an Address has been posted on the AXI address channel.
-- The counter is used to track flushing operations where all
-- transfers committed on the AXI Address Channel have to
-- be completed before a halt can occur.
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
wsc2rst_stop_cmplt <= sig_all_cmds_done;
sig_no_posted_cmds <= (sig_addr_posted_cntr_eq_0 and
not(addr2wsc_calc_error)) or
(sig_addr_posted_cntr_eq_1 and
addr2wsc_calc_error);
sig_all_cmds_done <= sig_no_posted_cmds and
sig_halt_reg_dly3;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
-- coverage off
elsif (rst2wsc_stop_request = '1') then
sig_halt_reg <= '1';
-- coverage on
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
| apache-2.0 | 120be77d4a24bf0bfb322d2ad0bc7b82 | 0.452778 | 4.728867 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/2-MESA-HB/metaheurísticas/mesahb_wsga.vhd | 1 | 1,934 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.10:17:23)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mesahb_wsga_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5: IN unsigned(0 TO 3);
output1, output2: OUT unsigned(0 TO 4));
END mesahb_wsga_entity;
ARCHITECTURE mesahb_wsga_description OF mesahb_wsga_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
register2 := input2 * 2;
WHEN "00000010" =>
register2 := register2 + 4;
output1 <= input3 + 5;
register1 := register1 + 7;
WHEN "00000011" =>
register2 := register2 * 9;
register1 := ((NOT register1) + 1) XOR register1;
WHEN "00000100" =>
register2 := register2 + 13;
register3 := input4 * 14;
WHEN "00000101" =>
register2 := ((NOT register2) + 1) XOR register2;
register3 := register3 + 18;
register4 := input5 * 19;
WHEN "00000110" =>
register3 := register3 * 21;
register1 := register4 * register1;
register2 := register2 * 23;
WHEN "00000111" =>
register1 := register2 + register1;
register2 := register3 + 25;
WHEN "00001000" =>
output2 <= register1(0 TO 1) & register2(0 TO 2);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mesahb_wsga_description; | gpl-3.0 | 2d991be1f46294c703d796832b886728 | 0.657187 | 3.031348 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/operand_select.vhd | 1 | 40,780 | `protect begin_protected
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`protect end_protected
| apache-2.0 | 1a0dea7b0ae667e3b22e1eb0ebd5188f | 0.947597 | 1.831081 | false | false | false | false |
sandrosalvato94/System-Design-Project | src/polito/sdp2017/Tests/constants.vhd | 1 | 568 | library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package CONSTANTS is
constant NUM_IPS : integer := 3;
constant DATA_WIDTH : integer := 16;
constant ADD_WIDTH : integer := 6;
type data_array is array (0 to NUM_IPS - 1) of std_logic_vector(DATA_WIDTH-1 downto 0);
type add_array is array (0 to NUM_IPS - 1) of std_logic_vector(ADD_WIDTH-1 downto 0);
constant INT_POS : integer := 13;
constant BE_POS : integer := 12;
constant IPADD_POS : integer := 11; -- downto 0
end package CONSTANTS;
| lgpl-3.0 | c503f039e32ae2976101ba0db2cf9a65 | 0.639085 | 3.120879 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/axi_master_burst_v2_0/1af76933/hdl/src/vhdl/axi_master_burst_stbs_set.vhd | 1 | 17,012 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- Filename: axi_master_burst_stbs_set.vhd
--
-- Description:
-- This file implements a module to count the number of strobe bits that
-- are asserted active high on the input strobe bus. This module does not
-- support sparse strobe assertions (asserted strobes must be contiguous
-- with each other).
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_master_burst_stbs_set.vhd
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.0 $
-- Date: $1/19/2011$
--
-- History:
-- DET 1/19/2011 Initial
-- ~~~~~~
-- - Adapted from AXI DataMover v2_00_a axi_datamvore_stbs_set.vhd
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI MASTER BURST to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_master_burst_stbs_set is
generic (
C_STROBE_WIDTH : Integer range 1 to 32 := 8
-- Specifies the width (in bits) ob the input strobe bus.
);
port (
tstrb_in : in std_logic_vector(C_STROBE_WIDTH-1 downto 0);
-- Input Strobe bus
num_stbs_asserted : Out std_logic_vector(7 downto 0)
-- Indicates the number of asserted tstrb_in bits
);
end entity axi_master_burst_stbs_set;
architecture implementation of axi_master_burst_stbs_set is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_8bit_stbs_set
--
-- Function Description:
-- Implements an 8-bit lookup table for calculating the number
-- of asserted bits within an 8-bit strobe vector.
--
-- Note that this function assumes that asserted strobes are
-- contiguous with each other (no sparse strobe assertions).
--
-------------------------------------------------------------------
function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 8 := 0;
begin
case strb_8 is
------- 1 bit --------------------------
when "00000001" | "00000010" | "00000100" | "00001000" |
"00010000" | "00100000" | "01000000" | "10000000" =>
lvar_num_set := 1;
------- 2 bit --------------------------
when "00000011" | "00000110" | "00001100" | "00011000" |
"00110000" | "01100000" | "11000000" =>
lvar_num_set := 2;
------- 3 bit --------------------------
when "00000111" | "00001110" | "00011100" | "00111000" |
"01110000" | "11100000" =>
lvar_num_set := 3;
------- 4 bit --------------------------
when "00001111" | "00011110" | "00111100" | "01111000" |
"11110000" =>
lvar_num_set := 4;
------- 5 bit --------------------------
when "00011111" | "00111110" | "01111100" | "11111000" =>
lvar_num_set := 5;
------- 6 bit --------------------------
when "00111111" | "01111110" | "11111100" =>
lvar_num_set := 6;
------- 7 bit --------------------------
when "01111111" | "11111110" =>
lvar_num_set := 7;
------- 8 bit --------------------------
when "11111111" =>
lvar_num_set := 8;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_8bit_stbs_set;
-- Constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BITS_FOR_STBS_ASSERTED : integer := 8; -- increments of 8 bits
Constant NUM_ZEROS_WIDTH : integer := BITS_FOR_STBS_ASSERTED;
-- Signals
signal sig_strb_input : std_logic_vector(C_STROBE_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs_asserted : std_logic_vector(BITS_FOR_STBS_ASSERTED-1 downto 0) := (others => '0');
begin --(architecture implementation)
num_stbs_asserted <= sig_stbs_asserted;
sig_strb_input <= tstrb_in ;
-------------------------------------------------------------------------
---------------- Asserted TSTRB calculation logic ---------------------
-------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1_STRB
--
-- If Generate Description:
-- 1-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_1_STRB : if (C_STROBE_WIDTH = 1) generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_1BIT_STRB
--
-- Process Description:
--
--
-------------------------------------------------------------
IMP_1BIT_STRB : process (sig_strb_input)
begin
-- Concatonate the strobe to the ls bit of
-- the asserted value
sig_stbs_asserted <= "0000000" &
sig_strb_input(0);
end process IMP_1BIT_STRB;
end generate GEN_1_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2_STRB
--
-- If Generate Description:
-- 2-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_2_STRB : if (C_STROBE_WIDTH = 2) generate
signal lsig_num_set : integer range 0 to 2 := 0;
signal lsig_strb_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_2BIT_STRB
--
-- Process Description:
-- Calculates the number of strobes set fo the 2-bit
-- strobe case
--
-------------------------------------------------------------
IMP_2BIT_STRB : process (lsig_strb_vect)
begin
case lsig_strb_vect is
when "01" | "10" =>
lsig_num_set <= 1;
when "11" =>
lsig_num_set <= 2;
when others =>
lsig_num_set <= 0;
end case;
end process IMP_2BIT_STRB;
sig_stbs_asserted <= STD_LOGIC_VECTOR(TO_UNSIGNED(lsig_num_set,
BITS_FOR_STBS_ASSERTED));
end generate GEN_2_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4_STRB
--
-- If Generate Description:
-- 4-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_4_STRB : if (C_STROBE_WIDTH = 4) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= "0000" & sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_4_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8_STRB
--
-- If Generate Description:
-- 8-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_8_STRB : if (C_STROBE_WIDTH = 8) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_8_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16_STRB
--
-- If Generate Description:
-- 16-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_16_STRB : if (C_STROBE_WIDTH = 16) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
end generate GEN_16_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32_STRB
--
-- If Generate Description:
-- 32-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_32_STRB : if (C_STROBE_WIDTH = 32) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
end generate GEN_32_STRB;
end implementation;
| apache-2.0 | d56ace1fc9e47d44782aa15d7803ea3d | 0.445862 | 4.835702 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/2-MESA-HB/asap-alap-random/mesahb_random.vhd | 1 | 1,987 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.10:15:41)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mesahb_random_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5: IN unsigned(0 TO 3);
output1, output2: OUT unsigned(0 TO 4));
END mesahb_random_entity;
ARCHITECTURE mesahb_random_description OF mesahb_random_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
register2 := input2 * 2;
register3 := input3 * 3;
register4 := input4 * 4;
WHEN "00000010" =>
register2 := register2 + 6;
register4 := register4 + 8;
output1 <= input5 + 9;
WHEN "00000011" =>
register4 := ((NOT register4) + 1) XOR register4;
WHEN "00000100" =>
register3 := register3 * register4;
register1 := register1 + 13;
register2 := register2 * 15;
WHEN "00000101" =>
register2 := register2 + 17;
WHEN "00000110" =>
register2 := ((NOT register2) + 1) XOR register2;
WHEN "00000111" =>
register2 := register2 * 21;
WHEN "00001000" =>
register2 := register2 + register3;
register1 := register1 * 23;
WHEN "00001001" =>
register1 := register1 + 25;
WHEN "00001010" =>
output2 <= register2(0 TO 1) & register1(0 TO 2);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mesahb_random_description; | gpl-3.0 | 6aba076c025618c75affcfc86c71c822 | 0.656266 | 3.071097 | false | false | false | false |
CyAScott/CIS4930.DatapathSynthesisTool | docs/sample2/c_subtractor.vhd | 1 | 1,032 | library ieee;
use ieee.std_logic_1164.all;
library WORK;
use WORK.all;
entity c_subtractor is
generic
(
width : integer := 4
);
port
(
input1, input2 : in std_logic_vector((width - 1) downto 0);
output : out std_logic_vector((width - 1) downto 0)
);
end c_subtractor;
architecture behavior of c_subtractor is
function bits_to_int (input : std_logic_vector) return integer is
variable ret_val : integer := 0;
begin
for i in input'range loop
if input(i) = '1' then
ret_val := 2 ** i + ret_val;
end if;
end loop; return ret_val;
end bits_to_int;
begin
process (input1, input2)
variable value : integer;
variable result : std_logic_vector((width - 1) downto 0);
begin
value := bits_to_int(input1) - bits_to_int(input2);
if (value < 0) then
value := (2 ** width) + value;
end if;
for i in 0 to width - 1 loop
if (value rem 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
value := value / 2;
end loop;
output <= result;
end process;
end behavior;
| mit | ef960f8533346d1a3f62b455a7c81292 | 0.632752 | 2.766756 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/operand_select_bit.vhd | 1 | 27,118 | `protect begin_protected
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`protect end_protected
| apache-2.0 | 25aff35283aab1bbb503ab80c37c6375 | 0.945092 | 1.854603 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-30bits_outputs31bits/5-EWF/metaheurísticas/ewf_hype.vhd | 1 | 3,138 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-17.11:31:21)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY ewf_hype_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2: IN unsigned(0 TO 30);
output1, output2, output3, output4, output5: OUT unsigned(0 TO 31));
END ewf_hype_entity;
ARCHITECTURE ewf_hype_description OF ewf_hype_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register4: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register5: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register6: unsigned(0 TO 31) := "00000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
WHEN "00000010" =>
register2 := register1 + 3;
register3 := input2 + 4;
WHEN "00000011" =>
register4 := register2 + 6;
WHEN "00000100" =>
register4 := register3 + register4;
WHEN "00000101" =>
register5 := register4 * 8;
register6 := register4 * 10;
WHEN "00000110" =>
register5 := register2 + register5;
WHEN "00000111" =>
register2 := register2 + register5;
WHEN "00001000" =>
register2 := register2 * 12;
WHEN "00001001" =>
register2 := register1 + register2;
WHEN "00001010" =>
register1 := register1 + register2;
WHEN "00001011" =>
register1 := register1 * 14;
WHEN "00001100" =>
register1 := register1 + 16;
WHEN "00001101" =>
output1 <= register2 + register1;
register1 := register5 + register2;
register2 := register4 + register5;
WHEN "00001110" =>
register4 := register3 + register6;
WHEN "00001111" =>
register3 := register3 + register4;
output2 <= register4 + register2;
register1 := register1 + 20;
WHEN "00010000" =>
register2 := register1 * 22;
WHEN "00010001" =>
register2 := register2 + 24;
WHEN "00010010" =>
output3 <= register1 + register2;
register1 := register3 * 27;
WHEN "00010011" =>
register1 := register1 + 29;
WHEN "00010100" =>
register2 := register4 + register1;
register3 := register1 + 31;
WHEN "00010101" =>
register3 := register3 * 33;
WHEN "00010110" =>
output4 <= register1 + register3;
register1 := register2 + 36;
WHEN "00010111" =>
register2 := register1 * 38;
WHEN "00011000" =>
register2 := register2 + 40;
WHEN "00011001" =>
output5 <= register1 + register2;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END ewf_hype_description; | gpl-3.0 | be9dcff7dc66a11512302f8a5299afe8 | 0.664436 | 3.338298 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/axi_master_burst_v2_0/1af76933/hdl/src/vhdl/axi_master_burst_addr_cntl.vhd | 1 | 30,435 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- Filename: axi_master_burst_addr_cntl.vhd
--
-- Description:
-- This file implements the AXI Master Burst Address Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_master_burst.vhd
-- |
-- |-- proc_common_v4_0 (helper library)
-- |
-- |-- axi_master_burst_reset.vhd
-- |
-- |-- axi_master_rd_llink.vhd
-- |
-- |-- axi_master_wr_llink.vhd
-- |
-- |
-- |-- axi_master_burst_cmd_status.vhd
-- | |-- axi_master_burst_first_stb_offset.vhd
-- | |-- axi_master_burst_stbs_set.vhd
-- |
-- |-- axi_master_burst_rd_wr_cntlr.vhd
-- |-- axi_master_burst_pcc.vhd
-- | |-- axi_master_burst_strb_gen.vhd
-- |-- axi_master_burst_addr_cntl.vhd
-- | |-- axi_master_burst_fifo.vhd
-- | |-- proc_common_v4_0.srl_fifo_f
-- | |-- axi_master_burst_sfifo_autord.vhd
-- |-- axi_master_burst_rddata_cntl.vhd
-- | |-- axi_master_burst_rdmux.vhd
-- | |-- axi_master_burst_fifo.vhd
-- | |-- proc_common_v4_0.srl_fifo_f
-- | |-- axi_master_burst_sfifo_autord.vhd
-- |-- axi_master_burst_wrdata_cntl.vhd
-- | |-- axi_master_burst_strb_gen
-- | |-- axi_master_burst_fifo.vhd
-- | |-- proc_common_v4_0.srl_fifo_f
-- | |-- axi_master_burst_sfifo_autord.vhd
-- |-- axi_master_burst_rd_status_cntl.vhd
-- |-- axi_master_burst_wr_status_cntl.vhd
-- | |-- axi_master_burst_fifo.vhd
-- | |-- proc_common_v4_0.srl_fifo_f
-- | |-- axi_master_burst_sfifo_autord.vhd
-- |-- axi_master_burst_skid_buf.vhd
-- |-- axi_master_burst_skid2mm_buf.vhd
--
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.1.2.9 $
-- Date: $1/19/2011$
--
-- History:
-- DET 1/19/2011 Initial
-- ~~~~~~
-- - Adapted from AXI DataMover v2_00_a axi_datamover_addr_cntl.vhd
-- ^^^^^^
--
-- DET 2/10/2011 Initial for EDK 13.2
-- ~~~~~~
-- - Added the inputs doing_read and doing_write
-- - Split the addr2axi_avalid output into two separate
-- outputs addr2axi_arvalid and addr2axi_awvalid. This
-- was required to provide registered outputs per Lint
-- guidelines.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI MASTER BURST to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_master_burst_v2_0;
Use axi_master_burst_v2_0.axi_master_burst_fifo;
-------------------------------------------------------------------------------
entity axi_master_burst_addr_cntl is
generic (
C_ADDR_FIFO_DEPTH : Integer range 1 to 32 := 4;
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
C_ADDR_ID : Integer range 0 to 255 := 0;
C_ADDR_ID_WIDTH : Integer range 1 to 8 := 4;
C_TAG_WIDTH : Integer range 1 to 8 := 4;
C_FAMILY : String := "virtex7"
);
port (
-- Clock input
primary_aclk : in std_logic;
-- Primary synchronization clock for the Master side
-- interface and internal logic. It is also used
-- for the User interface synchronization when
-- C_STSCMD_IS_ASYNC = 0.
-- Reset input
mmap_reset : in std_logic;
-- Reset used for the internal master logic
-- Read Command Type Discrete Input
doing_read : in std_logic;
-- Write Command Type Discrete Input
doing_write : in std_logic;
-- AXI Address Channel I/O -------------------------------
addr2axi_aid : out std_logic_vector(C_ADDR_ID_WIDTH-1 downto 0);
-- AXI Address Channel ID output
addr2axi_aaddr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0);
-- AXI Address Channel Address output
addr2axi_alen : out std_logic_vector(7 downto 0);
-- AXI Address Channel LEN output
-- Sized to support 256 data beat bursts
addr2axi_asize : out std_logic_vector(2 downto 0);
-- AXI Address Channel SIZE output
addr2axi_aburst : out std_logic_vector(1 downto 0);
-- AXI Address Channel BURST output
addr2axi_aprot : out std_logic_vector(2 downto 0);
-- AXI Address Channel PROT output
addr2axi_arvalid : out std_logic;
-- AXI Read Address Channel VALID output
addr2axi_awvalid : out std_logic;
-- AXI Write Address Channel VALID output
axi2addr_aready : in std_logic;
-- AXI Address Channel READY input
-- Currently unsupported AXI Address Channel output signals ------------
-- addr2axi_alock : out std_logic_vector(2 downto 0);
-- addr2axi_acache : out std_logic_vector(4 downto 0);
-- addr2axi_aqos : out std_logic_vector(3 downto 0);
-- addr2axi_aregion : out std_logic_vector(3 downto 0);
-----------------------------------------------------------------
-- Command Calculation Interface -------------------------------------
mstr2addr_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- The next command tag
mstr2addr_addr : In std_logic_vector(C_ADDR_WIDTH-1 downto 0);
-- The next command address to put on the AXI MMap ADDR
mstr2addr_len : In std_logic_vector(7 downto 0);
-- The next command length to put on the AXI MMap LEN
-- Sized to support 256 data beat bursts
mstr2addr_size : In std_logic_vector(2 downto 0);
-- The next command size to put on the AXI MMap SIZE
mstr2addr_burst : In std_logic_vector(1 downto 0);
-- The next command burst type to put on the AXI MMap BURST
mstr2addr_cmd_cmplt : In std_logic;
-- The indication to the Address Channel that the current
-- sub-command output is the last one compiled from the
-- parent command pulled from the Command FIFO
mstr2addr_calc_error : In std_logic;
-- Indication if the next command in the calculation pipe
-- has a calculation error
mstr2addr_cmd_valid : in std_logic;
-- The next command valid indication to the Address Channel
-- Controller for the AXI MMap
addr2mstr_cmd_ready : out std_logic;
-- Indication to the Command Calculator that the
-- command is being accepted
-- Halted Indication to Reset Module ----------------------------
addr2rst_stop_cmplt : out std_logic;
-- Output flag indicating the address controller has stopped
-- posting commands to the Address Channel due to a stop
-- request vai the data2addr_stop_req input port
-- Address Generation Control ---------------------------------
allow_addr_req : in std_logic;
-- Input used to enable/stall the posting of address requests.
-- 0 = stall address request generation.
-- 1 = Enable Address request geneartion
addr_req_posted : out std_logic;
-- Indication from the Address Channel Controller to external
-- User logic that an address has been posted to the
-- AXI Address Channel.
-- Data Channel Interface -------------------------------------
addr2data_addr_posted : Out std_logic;
-- Indication from the Address Channel Controller to the
-- Data Controller that an address has been posted to the
-- AXI Address Channel.
data2addr_data_rdy : In std_logic;
-- Indication that the Data Channel is ready to send the first
-- databeat of the next command on the write data channel.
-- This is used for the "wait for data" feature which keeps the
-- address controller from issuing a transfer requset until the
-- corresponding data is ready. This is expected to be held in
-- the asserted state until the addr2data_addr_posted signal is
-- asserted.
data2addr_stop_req : In std_logic;
-- Indication that the Data Channel has encountered an error
-- or a soft shutdown request and needs the Address Controller
-- to stop posting commands to the AXI Address channel
-- Status Module Interface -------------------------------------
addr2stat_calc_error : out std_logic;
-- Indication to the Status Module that the Addr Cntl FIFO
-- is loaded with a Calc error
addr2stat_cmd_fifo_empty : out std_logic
-- Indication to the Status Module that the Addr Cntl FIFO
-- is empty
);
end entity axi_master_burst_addr_cntl;
architecture implementation of axi_master_burst_addr_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Constant Declarations --------------------------------------------
Constant APROT_VALUE : std_logic_vector(3-1 downto 0) :=
'0' & -- bit 2, Normal Access
'0' & -- bit 1, Nonsecure Access
'0'; -- bit 0, Data Access
Constant LEN_WIDTH : integer := 8;
Constant SIZE_WIDTH : integer := 3;
Constant BURST_WIDTH : integer := 2;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant CALC_ERROR_WIDTH : integer := 1;
Constant ADDR_QUAL_WIDTH : integer := C_TAG_WIDTH + -- Cmd Tag field width
C_ADDR_WIDTH + -- Cmd Address field width
LEN_WIDTH + -- Cmd Len field width
SIZE_WIDTH + -- Cmd Size field width
BURST_WIDTH + -- Cmd Burst field width
CMD_CMPLT_WIDTH + -- Cmd Cmplt filed width
CALC_ERROR_WIDTH; -- Cmd Calc Error flag
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
-- Signal Declarations --------------------------------------------
signal sig_axi_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_axi_alen : std_logic_vector(7 downto 0) := (others => '0');
signal sig_axi_asize : std_logic_vector(2 downto 0) := (others => '0');
signal sig_axi_aburst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_axi_arvalid : std_logic := '0';
signal sig_axi_awvalid : std_logic := '0';
signal sig_axi_aready : std_logic := '0';
signal sig_addr_posted : std_logic := '0';
signal sig_calc_error : std_logic := '0';
signal sig_cmd_fifo_empty : std_logic := '0';
Signal sig_aq_fifo_data_in : std_logic_vector(ADDR_QUAL_WIDTH-1 downto 0) := (others => '0');
Signal sig_aq_fifo_data_out : std_logic_vector(ADDR_QUAL_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_fifo_next_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_fifo_next_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_calc_error : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_next_len_reg : std_logic_vector(7 downto 0) := (others => '0');
signal sig_next_size_reg : std_logic_vector(2 downto 0) := (others => '0');
signal sig_next_burst_reg : std_logic_vector(1 downto 0) := (others => '0');
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_rd_addr_valid_reg : std_logic := '0';
signal sig_wr_addr_valid_reg : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_pop_addr_reg : std_logic := '0';
signal sig_push_addr_reg : std_logic := '0';
signal sig_addr_reg_empty : std_logic := '0';
signal sig_addr_reg_full : std_logic := '0';
signal sig_posted_to_axi : std_logic := '0';
signal sig_allow_addr_req : std_logic := '0';
signal sig_posted_to_axi_2 : std_logic := '0';
------------------------------------------------------------------------------------
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_posted_to_axi : signal is "TRUE"; -- definition
Attribute KEEP of sig_posted_to_axi_2 : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_posted_to_axi : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_posted_to_axi_2 : signal is "no";
begin --(architecture implementation)
-- AXI I/O Port assignments
addr2axi_aid <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_ADDR_ID, C_ADDR_ID_WIDTH));
addr2axi_aaddr <= sig_axi_addr ;
addr2axi_alen <= sig_axi_alen ;
addr2axi_asize <= sig_axi_asize ;
addr2axi_aburst <= sig_axi_aburst;
addr2axi_aprot <= APROT_VALUE ;
sig_axi_aready <= axi2addr_aready;
addr2axi_arvalid <= sig_axi_arvalid;
addr2axi_awvalid <= sig_axi_awvalid;
-- Command Calculator Handshake output
sig_fifo_wr_cmd_valid <= mstr2addr_cmd_valid ;
addr2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
-- Data Channel Controller synchro pulse output
addr2data_addr_posted <= sig_addr_posted;
-- Status Module Interface outputs
addr2stat_calc_error <= sig_calc_error ;
addr2stat_cmd_fifo_empty <= sig_addr_reg_empty and
sig_cmd_fifo_empty;
-- Flag Indicating the Address Controller has completed a Stop
addr2rst_stop_cmplt <= (data2addr_stop_req and -- normal shutdown case
sig_addr_reg_empty) or
(data2addr_stop_req and -- shutdown after error trap
sig_calc_error);
-- Assign the address posting control and status
sig_allow_addr_req <= allow_addr_req ;
addr_req_posted <= sig_posted_to_axi_2 ;
-- Internal logic ------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_FIFO
--
-- If Generate Description:
-- Implements the case where the cmd qualifier depth is
-- greater than 1.
--
------------------------------------------------------------
GEN_ADDR_FIFO : if (C_ADDR_FIFO_DEPTH > 1) generate
begin
-- Format the input FIFO data word
sig_aq_fifo_data_in <= mstr2addr_calc_error &
mstr2addr_cmd_cmplt &
mstr2addr_burst &
mstr2addr_size &
mstr2addr_len &
mstr2addr_addr &
mstr2addr_tag ;
-- Rip fields from FIFO output data word
sig_fifo_calc_error <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH +
CMD_CMPLT_WIDTH +
CALC_ERROR_WIDTH)-1);
sig_fifo_next_cmd_cmplt <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH +
CMD_CMPLT_WIDTH)-1);
sig_fifo_next_burst <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH)-1
downto
C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH) ;
sig_fifo_next_size <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH)-1
downto
C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH) ;
sig_fifo_next_len <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH)-1
downto
C_ADDR_WIDTH +
C_TAG_WIDTH) ;
sig_fifo_next_addr <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH)-1
downto
C_TAG_WIDTH) ;
sig_fifo_next_tag <= sig_aq_fifo_data_out(C_TAG_WIDTH-1 downto 0);
------------------------------------------------------------
-- Instance: I_ADDR_QUAL_FIFO
--
-- Description:
-- Instance for the Address/Qualifier FIFO
--
------------------------------------------------------------
I_ADDR_QUAL_FIFO : entity axi_master_burst_v2_0.axi_master_burst_fifo
generic map (
C_DWIDTH => ADDR_QUAL_WIDTH ,
C_DEPTH => C_ADDR_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_aq_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_fifo_rd_cmd_ready ,
fifo_rd_tdata => sig_aq_fifo_data_out ,
fifo_rd_empty => sig_cmd_fifo_empty
);
end generate GEN_ADDR_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_ADDR_FIFO
--
-- If Generate Description:
-- Implements the case where no additional FIFOing is needed
-- on the input command address/qualifiers.
--
------------------------------------------------------------
GEN_NO_ADDR_FIFO : if (C_ADDR_FIFO_DEPTH = 1) generate
begin
-- Bypass FIFO
sig_fifo_next_tag <= mstr2addr_tag ;
sig_fifo_next_addr <= mstr2addr_addr ;
sig_fifo_next_len <= mstr2addr_len ;
sig_fifo_next_size <= mstr2addr_size ;
sig_fifo_next_burst <= mstr2addr_burst ;
sig_fifo_next_cmd_cmplt <= mstr2addr_cmd_cmplt ;
sig_fifo_calc_error <= mstr2addr_calc_error ;
sig_cmd_fifo_empty <= sig_addr_reg_empty ;
sig_fifo_wr_cmd_ready <= sig_fifo_rd_cmd_ready ;
sig_fifo_rd_cmd_valid <= sig_fifo_wr_cmd_valid ;
end generate GEN_NO_ADDR_FIFO;
-- Output Register Logic -------------------------------------------
sig_axi_addr <= sig_next_addr_reg ;
sig_axi_alen <= sig_next_len_reg ;
sig_axi_asize <= sig_next_size_reg ;
sig_axi_aburst <= sig_next_burst_reg ;
sig_axi_arvalid <= sig_rd_addr_valid_reg ;
sig_axi_awvalid <= sig_wr_addr_valid_reg ;
sig_calc_error <= sig_calc_error_reg ;
sig_fifo_rd_cmd_ready <= sig_addr_reg_empty and
sig_allow_addr_req and
not(data2addr_stop_req);
sig_addr_posted <= sig_posted_to_axi ;
-- Internal signals
sig_push_addr_reg <= sig_addr_reg_empty and
sig_fifo_rd_cmd_valid and
sig_allow_addr_req and
not(data2addr_stop_req);
sig_pop_addr_reg <= not(sig_calc_error_reg) and
sig_axi_aready and
sig_addr_reg_full;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_FIFO_REG
--
-- Process Description:
-- This process implements a register for the Address
-- Control FIFO that operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_ADDR_FIFO_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_addr_reg = '1') then
sig_next_tag_reg <= (others => '0') ;
sig_next_addr_reg <= (others => '0') ;
sig_next_len_reg <= (others => '0') ;
sig_next_size_reg <= (others => '0') ;
sig_next_burst_reg <= (others => '0') ;
sig_next_cmd_cmplt_reg <= '0' ;
sig_rd_addr_valid_reg <= '0' ;
sig_wr_addr_valid_reg <= '0' ;
sig_calc_error_reg <= '0' ;
sig_addr_reg_empty <= '1' ;
sig_addr_reg_full <= '0' ;
elsif (sig_push_addr_reg = '1') then
sig_next_tag_reg <= sig_fifo_next_tag ;
sig_next_addr_reg <= sig_fifo_next_addr ;
sig_next_len_reg <= sig_fifo_next_len ;
sig_next_size_reg <= sig_fifo_next_size ;
sig_next_burst_reg <= sig_fifo_next_burst ;
sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
sig_rd_addr_valid_reg <= not(sig_fifo_calc_error) and
doing_read ;
sig_wr_addr_valid_reg <= not(sig_fifo_calc_error) and
doing_write ;
sig_calc_error_reg <= sig_fifo_calc_error ;
sig_addr_reg_empty <= '0' ;
sig_addr_reg_full <= '1' ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_FIFO_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_POSTED_FLAG
--
-- Process Description:
-- This implements a FLOP that creates a 1 clock wide pulse
-- indicating a new address/qualifier set has been posted to
-- the AXI Addres Channel outputs. This is used to synchronize
-- the Data Channel Controller.
--
-------------------------------------------------------------
IMP_POSTED_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_posted_to_axi <= '0';
sig_posted_to_axi_2 <= '0';
elsif (sig_push_addr_reg = '1') then
sig_posted_to_axi <= '1';
sig_posted_to_axi_2 <= '1';
else
sig_posted_to_axi <= '0';
sig_posted_to_axi_2 <= '0';
end if;
end if;
end process IMP_POSTED_FLAG;
end implementation;
| apache-2.0 | b6994b796a14cb20d651bb5564b868cd | 0.469985 | 4.386079 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/lmb_bram_if_cntlr_v4_0/816dc01c/hdl/vhdl/pselect_mask.vhd | 1 | 7,196 | -------------------------------------------------------------------------------
-- $Id: pselect_mask.vhd,v 1.1.2.2 2010/09/06 09:01:24 rolandp Exp $
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
------------------------------------------------------------------------------
-- Filename: pselect_mask.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pselect_mask.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.1.2.2 $
-- Date: $Date: 2010/09/06 09:01:24 $
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library Unisim;
use Unisim.all;
entity pselect_mask is
generic (
C_AW : integer := 32;
C_BAR : std_logic_vector(0 to 31) := "00000000000000100000000000000000";
C_MASK : std_logic_vector(0 to 31) := "00000000000001111100000000000000"
);
port (
A : in std_logic_vector(0 to C_AW-1);
Valid : in std_logic;
CS : out std_logic
);
end entity pselect_mask;
library unisim;
use unisim.all;
architecture imp of pselect_mask is
function Nr_Of_Ones (S : std_logic_vector) return natural is
variable tmp : natural := 0;
begin -- function Nr_Of_Ones
for I in S'range loop
if (S(I) = '1') then
tmp := tmp + 1;
end if;
end loop; -- I
return tmp;
end function Nr_Of_Ones;
function fix_AB (B : boolean; I : integer) return integer is
begin -- function fix_AB
if (not B) then
return I + 1;
else
return I;
end if;
end function fix_AB;
constant Nr : integer := Nr_Of_Ones(C_MASK);
constant Use_CIN : boolean := ((Nr mod 4) = 0);
constant AB : integer := fix_AB(Use_CIN, Nr);
attribute INIT : string;
constant NUM_LUTS : integer := (AB-1)/4+1;
-- function to initialize LUT within pselect
type int4 is array (3 downto 0) of integer;
function pselect_init_lut(i : integer;
AB : integer;
NUM_LUTS : integer;
C_AW : integer;
C_BAR : std_logic_vector(0 to 31))
return bit_vector is
variable init_vector : bit_vector(15 downto 0) := X"0001";
variable j : integer := 0;
variable val_in : int4;
begin
for j in 0 to 3 loop
if i < NUM_LUTS-1 or j <= ((AB-1) mod 4) then
val_in(j) := conv_integer(C_BAR(i*4+j));
else val_in(j) := 0;
end if;
end loop;
init_vector := To_bitvector(conv_std_logic_vector(2**(val_in(3)*8+
val_in(2)*4+val_in(1)*2+val_in(0)*1),16));
return init_vector;
end pselect_init_lut;
signal A_Bus : std_logic_vector(0 to AB);
signal BAR : std_logic_vector(0 to AB);
-------------------------------------------------------------------------------
-- Begin architecture section
-------------------------------------------------------------------------------
begin -- VHDL_RTL
Make_Busses : process (A,Valid) is
variable tmp : natural;
begin -- process Make_Busses
tmp := 0;
A_Bus <= (others => '0');
BAR <= (others => '0');
for I in C_MASK'range loop
if (C_MASK(I) = '1') then
A_Bus(tmp) <= A(I);
BAR(tmp) <= C_BAR(I);
tmp := tmp + 1;
end if;
end loop; -- I
if (not Use_CIN) then
BAR(tmp) <= '1';
A_Bus(tmp) <= Valid;
end if;
end process Make_Busses;
CS <= Valid when A_Bus=BAR else '0';
end imp;
| apache-2.0 | ca79fea739773510349bed3a47ee6f18 | 0.529044 | 4.198366 | false | false | false | false |
rcls/sdr | vhdl/defs.vhd | 1 | 2,412 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
package defs is
subtype unsigned36 is unsigned(35 downto 0);
subtype unsigned24 is unsigned(23 downto 0);
subtype unsigned18 is unsigned(17 downto 0);
subtype unsigned16 is unsigned(15 downto 0);
subtype unsigned9 is unsigned(8 downto 0);
subtype unsigned8 is unsigned(7 downto 0);
subtype unsigned7 is unsigned(6 downto 0);
subtype unsigned3 is unsigned(2 downto 0);
subtype unsigned2 is unsigned(1 downto 0);
subtype signed36 is signed(35 downto 0);
subtype signed32 is signed(31 downto 0);
subtype signed18 is signed(17 downto 0);
subtype signed16 is signed(15 downto 0);
subtype signed15 is signed(14 downto 0);
subtype signed14 is signed(13 downto 0);
type sinrom_t is array (0 to 1023) of unsigned18;
constant mf_width : integer := 28;
subtype mf_signed is signed(mf_width - 1 downto 0);
type four_mf_signed is array (0 to 3) of mf_signed;
subtype command_t is std_logic_vector(23 downto 0);
type program_t is array(integer range <>) of command_t;
attribute keep : string;
function b2s (x : boolean) return std_logic is
begin
if x then
return '1';
else
return '0';
end if;
end b2s;
-- The bottom 3 bits are added mod 5, so the overall effect is adding mod320.
function addmod320(x : unsigned9; y : unsigned9) return unsigned9 is
variable lo : unsigned(2 downto 0);
variable carry : unsigned(0 downto 0);
begin
if x(2 downto 0) + ('0' & y(2 downto 0)) >= x"5" then
lo := x(2 downto 0) + y(2 downto 0) + "011";
carry := "1";
else
lo := x(2 downto 0) + y(2 downto 0);
carry := "0";
end if;
return (x(8 downto 3) + y(8 downto 3) + carry) & lo;
end;
-- Extend by n bits; the shift parameter selects which of upper and lower
-- bits to take the shift from.
function take(x : signed; reduce : integer; shift : unsigned)
return signed is
variable shifted : signed(x'high downto x'low);
begin
shifted := x sll to_integer(shift);
return shifted(shifted'high downto x'low + reduce);
end;
function minimum(x : integer; y : integer) return integer is
begin
if x < y then return x; else return y; end if;
end minimum;
function maximum(x : integer; y : integer) return integer is
begin
if x > y then return x; else return y; end if;
end maximum;
end defs;
| gpl-3.0 | 5d9119c97cd72afa78b3ff8a460730ed | 0.671227 | 3.536657 | false | false | false | false |
BBN-Q/APS2-Comms | src/eprom_cfg_reader.vhd | 1 | 3,996 | -- Reads configuration bytes from EPROM
-- * MAC address
-- * IPv4 address
-- * DHCP enable bit
--
-- Original authors: Brian Donnovan, Colm Ryan
-- Copyright 2015, Raytheon BBN Technologies
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity eprom_cfg_reader is
generic (
DEFAULT_MAC_ADDR : std_logic_vector(47 downto 0) := x"4651dbbada55";
DEFAULT_IP_ADDR : std_logic_vector(31 downto 0) := x"c0a8027b"
);
port (
clk : in std_logic;
rst : in std_logic;
-- coming from ethernet
rx_in_tdata : in std_logic_vector(31 downto 0);
rx_in_tvalid : in std_logic;
rx_in_tready : out std_logic;
rx_in_tlast : in std_logic;
-- going to CPLD
rx_out_tdata : out std_logic_vector(31 downto 0);
rx_out_tvalid : out std_logic;
rx_out_tlast : out std_logic;
rx_out_tready : in std_logic;
-- coming from CPLD
tx_in_tdata : in std_logic_vector(31 downto 0);
tx_in_tvalid : in std_logic;
tx_in_tready : out std_logic;
tx_in_tlast : in std_logic;
-- going to ethernet
tx_out_tdata : out std_logic_vector(31 downto 0);
tx_out_tvalid : out std_logic;
tx_out_tlast : out std_logic;
tx_out_tready : in std_logic;
-- configuration/status ports
mac_addr : out std_logic_vector(47 downto 0);
ip_addr : out std_logic_vector(31 downto 0);
dhcp_enable : out std_logic;
done : out std_logic
);
end entity;
architecture arch of eprom_cfg_reader is
constant READ_EPROM_CMD : std_logic_vector(31 downto 0) := x"12000004"; -- read 4 32 bit words
constant EPROM_ADDR : std_logic_vector(31 downto 0) := x"00FF0000"; --starting at 0x00FF0000
type main_state_t is (START, WRITE_CMD, WRITE_ADDR, READ_RESPONSE, FINISHED);
signal main_state : main_state_t;
signal recv_eprom_cmd : std_logic_vector(31 downto 0);
begin
main : process(clk)
variable read_ct : natural range 0 to 5;
begin
if rising_edge(clk) then
if rst = '1' then
main_state <= START;
read_ct := 0;
mac_addr <= DEFAULT_MAC_ADDR;
ip_addr <= DEFAULT_IP_ADDR;
dhcp_enable <= '0';
else
case( main_state ) is
when START =>
main_state <= WRITE_CMD;
when WRITE_CMD =>
if rx_out_tready = '1' then
main_state <= WRITE_ADDR;
end if;
when WRITE_ADDR =>
if rx_out_tready = '1' then
main_state <= READ_RESPONSE;
end if;
when READ_RESPONSE =>
--TODO: do we need a timeout here?
if tx_in_tvalid = '1' then
case( read_ct ) is
when 0 =>
recv_eprom_cmd <= tx_in_tdata;
when 1 =>
mac_addr(47 downto 16) <= tx_in_tdata;
when 2 =>
mac_addr(15 downto 0) <= tx_in_tdata(31 downto 16);
when 3 =>
ip_addr <= tx_in_tdata;
when 4 =>
dhcp_enable <= tx_in_tdata(0);
main_state <= FINISHED;
when others =>
null;
end case;
read_ct := read_ct + 1;
end if;
when FINISHED =>
null;
end case;
end if;
end if;
end process;
done <= '1' when main_state = FINISHED else '0';
--Mux streams
with main_state select rx_out_tdata <=
READ_EPROM_CMD when WRITE_CMD,
EPROM_ADDR when WRITE_ADDR,
rx_in_tdata when others;
with main_state select rx_out_tvalid <=
rx_in_tvalid when FINISHED,
'1' when WRITE_CMD | WRITE_ADDR,
'0' when others;
with main_state select rx_out_tlast <=
rx_in_tlast when FINISHED,
'1' when WRITE_ADDR,
'0' when others;
rx_in_tready <= rx_out_tready when main_state = FINISHED else '0';
tx_out_tdata <= tx_in_tdata;
tx_out_tvalid <= tx_in_tvalid when main_state = FINISHED else '0';
tx_out_tlast <= tx_in_tlast when main_state = FINISHED else '0';
tx_in_tready <= tx_out_tready when main_state = FINISHED else '1';
end architecture;
| mpl-2.0 | e265c4c2ad9b04f7d5c70748d6ff25fe | 0.589089 | 3.305211 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/9-MESA-FP/asap-alap-random/mesafp_random.vhd | 1 | 4,525 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-26.16:15:41)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mesafp_random_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16, input17, input18, input19, input20, input21: IN unsigned(0 TO 3);
output1, output2, output3, output4, output5: OUT unsigned(0 TO 4));
END mesafp_random_entity;
ARCHITECTURE mesafp_random_description OF mesafp_random_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register9: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register10: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register11: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register12: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register13: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register14: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register15: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register16: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register17: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
register2 := input2 * 2;
register3 := input3 * 3;
WHEN "00000010" =>
register2 := register2 + 5;
register4 := input4 * 6;
register5 := input5 * 7;
WHEN "00000011" =>
register4 := register4 + 9;
register6 := input6 * 10;
register7 := input7 + 11;
register8 := input8 * 12;
register9 := input9 * 13;
register10 := input10 + 14;
register11 := input11 + 15;
register12 := input12 * 16;
WHEN "00000100" =>
register8 := register8 + 18;
register13 := input13 * 19;
register11 := register12 + register11;
register12 := input14 + 20;
register14 := input15 + 21;
register15 := input16 + 22;
register16 := input17 * 23;
WHEN "00000101" =>
register12 := register12 + 25;
register17 := input18 * 26;
register10 := register13 + register10;
WHEN "00000110" =>
register13 := register17 + register15;
register15 := input19 * 27;
register5 := register5 + 29;
register17 := input20 * 30;
register6 := register6 + register10;
register10 := input21 * 31;
register9 := register9 + register14;
register11 := register16 + register11;
WHEN "00000111" =>
register11 := ((NOT register11) + 1) XOR register11;
WHEN "00001000" =>
output1 <= register11(0 TO 1) & register8(0 TO 2);
register7 := register10 + register7;
register8 := register15 + register13;
WHEN "00001001" =>
register7 := register17 + register7;
register6 := ((NOT register6) + 1) XOR register6;
register3 := register3 + register9;
WHEN "00001010" =>
register7 := ((NOT register7) + 1) XOR register7;
register6 := register6 / 2;
register3 := ((NOT register3) + 1) XOR register3;
register8 := ((NOT register8) + 1) XOR register8;
WHEN "00001011" =>
register7 := register6 * register7;
WHEN "00001100" =>
output2 <= register7(0 TO 1) & register5(0 TO 2);
register5 := register6 * register8;
register7 := ((NOT register12) + 1) XOR register12;
WHEN "00001101" =>
output3 <= register5(0 TO 1) & register4(0 TO 2);
register3 := register6 * register3;
WHEN "00001110" =>
output4 <= register3(0 TO 1) & register2(0 TO 2);
register1 := register1 + 51;
WHEN "00001111" =>
register1 := ((NOT register1) + 1) XOR register1;
WHEN "00010000" =>
IF (register7 = 54 or register1 = 54) THEN
output5 <= register7;
ELSE
output5 <= "10110";
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mesafp_random_description; | gpl-3.0 | 0c4c5715cc45d6bb914063d91b19b86b | 0.656133 | 3.170988 | false | false | false | false |
BBN-Q/APS2-Comms | test/tcp_bridge_tb.vhd | 1 | 5,630 | -- Test bench for the TCP-AXI Bridge
-- Tests:
-- * no-ack write
-- * ack write
-- * read
--
-- Original author: Colm Ryan
-- Copyright 2015,2016 Raytheon BBN Technologies
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tcp_bridge_tb is
end;
architecture bench of tcp_bridge_tb is
signal axi_resetn : std_logic := '0';
signal clk : std_logic := '0';
signal clk_tcp : std_logic := '0';
signal rst : std_logic := '0';
signal rst_tcp : std_logic := '0';
signal cpld_rx_tdata : std_logic_vector (31 downto 0) := (others => '0');
signal cpld_rx_tready : std_logic := '0';
signal cpld_rx_tvalid : std_logic := '0';
signal cpld_rx_tlast : std_logic := '0';
signal cpld_tx_tdata : std_logic_vector (31 downto 0) := (others => '0');
signal cpld_tx_tready : std_logic := '1';
signal cpld_tx_tvalid : std_logic := '0';
signal cpld_tx_tlast : std_logic := '0';
signal tcp_rx_tdata : std_logic_vector (7 downto 0) := (others => '0');
signal tcp_rx_tready : std_logic := '0';
signal tcp_rx_tvalid : std_logic := '0';
signal tcp_tx_tdata : std_logic_vector (7 downto 0) := (others => '0');
signal tcp_tx_tready : std_logic := '1';
signal tcp_tx_tvalid : std_logic := '0';
signal mm2s_err : std_logic := '0';
signal s2mm_err : std_logic := '0';
constant clock_period : time := 10 ns;
constant clock_tcp_period : time := 8 ns;
signal stop_the_clocks : boolean := false;
signal checking_finished : boolean := false;
type TestBenchState_t is (RESET, WRITE_SHORT_NOACK, WRITE_SHORT_ACK, READ_SHORT, FINISHED);
signal testBench_state : TestBenchState_t;
begin
uut: entity work.tcp_bridge_tb_bd
port map (
clk => clk,
clk_tcp => clk_tcp,
rst => rst,
rst_tcp => rst_tcp,
axi_resetn => axi_resetn,
cpld_rx_tdata => cpld_rx_tdata,
cpld_rx_tready => cpld_rx_tready,
cpld_rx_tvalid => cpld_rx_tvalid,
cpld_rx_tlast => cpld_rx_tlast,
cpld_tx_tdata => cpld_tx_tdata,
cpld_tx_tready => cpld_tx_tready,
cpld_tx_tvalid => cpld_tx_tvalid,
cpld_tx_tlast => cpld_tx_tlast,
tcp_rx_tdata => tcp_rx_tdata,
tcp_rx_tready => tcp_rx_tready,
tcp_rx_tvalid => tcp_rx_tvalid,
tcp_tx_tdata => tcp_tx_tdata,
tcp_tx_tready => tcp_tx_tready,
tcp_tx_tvalid => tcp_tx_tvalid,
mm2s_err => mm2s_err,
s2mm_err => s2mm_err
);
clk <= not clk after clock_period / 2 when not stop_the_clocks;
clk_tcp <= not clk_tcp after clock_tcp_period / 2 when not stop_the_clocks;
stimulus: process
procedure write_word(word : std_logic_vector(31 downto 0)) is
begin
tcp_rx_tvalid <= '1';
for ct in 0 to 3 loop
tcp_rx_tdata <= word(31-ct*8 downto 24-ct*8);
wait until rising_edge(clk_tcp) and tcp_rx_tready = '1';
end loop;
tcp_rx_tvalid <= '0';
end procedure write_word;
begin
wait until rising_edge(clk_tcp);
testBench_state <= RESET;
axi_resetn <= '0';
rst <= '1';
rst_tcp <= '1';
wait for 100ns;
wait until rising_edge(clk_tcp);
rst_tcp <= '0';
wait until rising_edge(clk);
axi_resetn <= '1';
rst <= '0';
wait for 100ns;
--Clock in a write request with no-ack
wait until rising_edge(clk_tcp);
testBench_state <= WRITE_SHORT_NOACK;
--control word
write_word(x"00000004");
--address
write_word(x"C0000000");
--data
tcp_rx_tvalid <= '1';
for ct in 1 to 16 loop
tcp_rx_tdata <= std_logic_vector(to_unsigned(ct, 8));
wait until rising_edge(clk_tcp) and tcp_rx_tready = '1';
end loop;
--ifg
tcp_rx_tvalid <= '0';
for ct in 1 to 4 loop
wait until rising_edge(clk_tcp);
end loop;
--Clock in a write request with ack req.
wait until rising_edge(clk_tcp);
testBench_state <= WRITE_SHORT_ACK;
--control word
write_word(x"80000004");
--address
write_word(x"C0000010");
--data
tcp_rx_tvalid <= '1';
for ct in 1 to 16 loop
tcp_rx_tdata <= std_logic_vector(to_unsigned(16+ct, 8));
wait until rising_edge(clk_tcp) and tcp_rx_tready = '1';
end loop;
--ifg
tcp_rx_tvalid <= '0';
for ct in 1 to 4 loop
wait until rising_edge(clk_tcp);
end loop;
--Clock in a read request
wait until rising_edge(clk_tcp);
testBench_state <= READ_SHORT;
--control word
write_word(x"10000008");
--address
write_word(x"C0000000");
tcp_rx_tvalid <= '0';
wait for 1 us;
assert checking_finished report "Checking incomplete!";
testBench_state <= FINISHED;
stop_the_clocks <= true;
end process;
checking : process
procedure check_word(word : std_logic_vector(31 downto 0); error_str : string) is
begin
for ct in 0 to 3 loop
wait until rising_edge(clk_tcp) and tcp_tx_tvalid = '1';
assert tcp_tx_tdata = word(31-8*ct downto 24-8*ct) report error_str;
end loop;
end procedure check_word;
begin
--READ_SHORT comes out first because it's response starts before WRITE_SHORT_ACK
--command and address
check_word(x"10000008", "Incorrect READ_SHORT command response received.");
check_word(x"c0000000", "Incorrect READ_SHORT address response received.");
--data
for ct in 1 to 32 loop
wait until rising_edge(clk_tcp) and tcp_tx_tvalid = '1';
assert tcp_tx_tdata = std_logic_vector(to_unsigned(ct, 8)) report "Incorrect READ_SHORT data response received.";
end loop;
--Next thing that should come out is the WRITE_SHORT_ACK
check_word(x"80800004", "Incorrect WRITE_SHORT_ACK command response received.");
check_word(x"c0000010", "Incorrect WRITE_SHORT_ACK address response received.");
checking_finished <= true;
end process;
end;
| mpl-2.0 | 127dc2be67c777a150d09e698cc9b414 | 0.6373 | 3.03014 | false | true | false | false |
sandrosalvato94/System-Design-Project | src/polito/sdp2017/Tests/Shifter.vhd | 1 | 735 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity Shifter is
generic (N : integer := 16);
port (A : in std_logic_vector(N-1 downto 0);
B : out std_logic_vector(N-1 downto 0);
C : out std_logic_vector(N-1 downto 0);
D : out std_logic_vector(N-1 downto 0);
E : out std_logic_vector(N-1 downto 0)
);
end Shifter;
architecture Behavioral of Shifter is
begin
B <= A; -- A
C <= not(A) + 1; -- -A
D(N-1 downto 1) <= A(N-2 downto 0); -- 2A
D(0) <= '0';
process(A) -- -2A
variable var : std_logic_vector(N-1 downto 0);
begin
var := not(A) + 1;
E(N-1 downto 1) <= var(N-2 downto 0);
E(0) <= '0';
end process;
end Behavioral;
| lgpl-3.0 | b8bc249b9f63ea3d2812f79b96295b41 | 0.567347 | 2.588028 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/debug_stat_counter.vhd | 1 | 25,262 | `protect begin_protected
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| apache-2.0 | 9af141650eebcccbb832c02dbe53b5d4 | 0.945333 | 1.846098 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/pf_dpram_select.vhd | 15 | 118,961 | -------------------------------------------------------------------------------
-- $Id: pf_dpram_select.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_dpram_select.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_dpram_select.vhd
--
-- Description: This vhdl design file uses three input parameters describing
-- the desired storage depth, data width, and FPGA family type.
-- From these, the design selects the optimum Block RAM
-- primitive for the basic storage element and connects them
-- in parallel to accomodate the desired data width.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_dpram_select.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- DET Oct. 7, 2001 First Version
-- - Adopted design concepts from Goran Bilski's
-- opb_bram.vhd design in the formulation of this
-- design for the Mauna Loa packet FIFO dual port
-- core function.
--
-- DET Oct-31-2001
-- - Changed the generic input parameter C_FAMILY of type string
-- back to the boolean type parameter C_VIRTEX_II. XST support
-- change.
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library unisim;
use unisim.all; -- uses BRAM primitives
-------------------------------------------------------------------------------
entity pf_dpram_select is
generic (
C_DP_DATA_WIDTH : Integer := 32;
C_DP_ADDRESS_WIDTH : Integer := 9;
C_VIRTEX_II : Boolean := true
);
port (
-- Write Port signals
Wr_rst : In std_logic;
Wr_Clk : in std_logic;
Wr_Enable : In std_logic;
Wr_Req : In std_logic;
Wr_Address : in std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
Wr_Data : In std_logic_vector(0 to C_DP_DATA_WIDTH-1);
-- Read Port Signals
Rd_rst : In std_logic;
Rd_Clk : in std_logic;
Rd_Enable : In std_logic;
Rd_Address : in std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
Rd_Data : out std_logic_vector(0 to C_DP_DATA_WIDTH-1)
);
end entity pf_dpram_select;
architecture implementation of pf_dpram_select is
Type family_type is (
any ,
x4k ,
x4ke ,
x4kl ,
x4kex ,
x4kxl ,
x4kxv ,
x4kxla ,
spartan ,
spartanxl,
spartan2 ,
spartan2e,
virtex ,
virtexe ,
virtex2 ,
virtex2p ,
unsupported
);
Type bram_prim_type is (
use_srl ,
B4_S1_S1 ,
B4_S2_S2 ,
B4_S4_S4 ,
B4_S8_S8 ,
B4_S16_S16 ,
B16_S1_S1 ,
B16_S2_S2 ,
B16_S4_S4 ,
B16_S9_S9 ,
B16_S18_S18 ,
B16_S36_S36 ,
indeterminate
);
-----------------------------------------------------------------------------
-- This function converts the input C_VIRTEX_II boolean type to an enumerated
-- type. Only Virtex and Virtex II types are currently supported. This
-- used to convert a string to a family type function but string support in
-- the synthesis tools was found to be mutually exclusive between Synplicity
-- and XST.
-----------------------------------------------------------------------------
function get_prim_family (vertex2_select : boolean) return family_type is
Variable prim_family : family_type;
begin
If (vertex2_select) Then
prim_family := virtex2;
else
prim_family := virtex;
End if;
Return (prim_family);
end function get_prim_family;
-----------------------------------------------------------------------------
-- This function chooses the optimum BRAM primitive to utilize as
-- specified by the inputs for data depth, data width, and FPGA part family.
-----------------------------------------------------------------------------
function get_bram_primitive (target_depth: integer;
target_width: integer;
family : family_type )
return bram_prim_type is
Variable primitive : bram_prim_type;
begin
Case family Is
When virtex2p | virtex2 =>
Case target_depth Is
When 1 | 2 =>
primitive := indeterminate; -- depth is too small for BRAM
-- based fifo control logic
When 4 | 8 | 16 =>
-- primitive := use_srl; -- activate when SRL FIFO incorporated
Case target_width Is -- use BRAM for now
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 =>
primitive := B16_S18_S18;
When others =>
primitive := B16_S36_S36;
End case;
when 32 | 64 | 128 | 256 | 512 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 =>
primitive := B16_S18_S18;
When others =>
primitive := B16_S36_S36;
End case;
When 1024 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When others =>
primitive := B16_S18_S18;
End case;
When 2048 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When others =>
primitive := B16_S9_S9;
End case;
When 4096 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When others =>
primitive := B16_S4_S4;
End case;
When 8192 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When others =>
primitive := B16_S2_S2;
End case;
When 16384 =>
primitive := B16_S1_S1;
When others =>
primitive := indeterminate;
End case;
When spartan2 | spartan2e | virtex | virtexe =>
Case target_depth Is
When 1 | 2 =>
primitive := indeterminate; -- depth is too small for BRAM
-- based fifo control logic
When 4 | 8 | 16 =>
-- primitive := use_srl; -- activate this when SRL FIFO is
-- incorporated
Case target_width Is -- use BRAM for now
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When 5 | 6 | 7 | 8 =>
primitive := B4_S8_S8;
When others =>
primitive := B4_S16_S16;
End case;
when 32 | 64 | 128 | 256 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When 5 | 6 | 7 | 8 =>
primitive := B4_S8_S8;
When others =>
primitive := B4_S16_S16;
End case;
when 512 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When others =>
primitive := B4_S8_S8;
End case;
When 1024 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When others =>
primitive := B4_S4_S4;
End case;
When 2048 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When others =>
primitive := B4_S2_S2;
End case;
When 4096 =>
primitive := B4_S1_S1;
When others =>
primitive := indeterminate;
End case;
When others =>
primitive := indeterminate;
End case;
Return primitive;
end function get_bram_primitive;
-----------------------------------------------------------------------------
-- This function calculates the number of BRAM primitives required as
-- specified by the inputs for data width and BRAM primitive type.
-----------------------------------------------------------------------------
function get_num_prims (bram_prim : bram_prim_type;
mem_width : integer)
return integer is
Variable bram_num : integer;
begin
Case bram_prim Is
When B16_S1_S1 | B4_S1_S1 =>
bram_num := mem_width;
When B16_S2_S2 | B4_S2_S2 =>
bram_num := (mem_width+1)/2;
When B16_S4_S4 | B4_S4_S4 =>
bram_num := (mem_width+3)/4;
When B4_S8_S8 =>
bram_num := (mem_width+7)/8;
When B16_S9_S9 =>
bram_num := (mem_width+8)/9;
When B4_S16_S16 =>
bram_num := (mem_width+15)/16;
When B16_S18_S18 =>
bram_num := (mem_width+17)/18;
When B16_S36_S36 =>
bram_num := (mem_width+35)/36;
When others =>
bram_num := 1;
End case;
Return (bram_num);
end function get_num_prims;
-- Now set the global CONSTANTS needed for IF-Generates
-- Determine the number of BRAM storage locations needed
constant FIFO_DEPTH : Integer := 2**C_DP_ADDRESS_WIDTH;
-- Convert the input C_VIRTEX_II generic boolean to enumerated type
Constant BRAM_FAMILY : family_type :=
get_prim_family(C_VIRTEX_II);
-- Select the optimum BRAM primitive to use
constant BRAM_PRIMITIVE : bram_prim_type :=
get_bram_primitive(FIFO_DEPTH,
C_DP_DATA_WIDTH,
BRAM_FAMILY);
-- Calculate how many of the selected primitives are needed
-- to populate the desired data width
constant BRAM_NUM : integer :=
get_num_prims(BRAM_PRIMITIVE,
C_DP_DATA_WIDTH);
begin -- architecture
----------------------------------------------------------------------------
-- Using VII 512 x 36 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S36_S36 : if (BRAM_PRIMITIVE = B16_S36_S36) generate
component RAMB16_S36_S36
port (DIA : in STD_LOGIC_VECTOR (31 downto 0);
DIB : in STD_LOGIC_VECTOR (31 downto 0);
DIPA : in STD_LOGIC_VECTOR (3 downto 0);
DIPB : in STD_LOGIC_VECTOR (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (8 downto 0);
ADDRB : in STD_LOGIC_VECTOR (8 downto 0);
DOA : out STD_LOGIC_VECTOR (31 downto 0);
DOB : out STD_LOGIC_VECTOR (31 downto 0);
DOPA : out STD_LOGIC_VECTOR (3 downto 0);
DOPB : out STD_LOGIC_VECTOR (3 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 9; -- 512 deep
Constant PRIM_PDBUS_WIDTH : integer := 4; -- 4 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 32; -- 4 parity data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_512x32 : RAMB16_S36_S36
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S36_S36;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 1024 x 18 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S18_S18 : if (BRAM_PRIMITIVE = B16_S18_S18) generate
component RAMB16_S18_S18
port (DIA : in STD_LOGIC_VECTOR (15 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
DIPA : in STD_LOGIC_VECTOR (1 downto 0);
DIPB : in STD_LOGIC_VECTOR (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (9 downto 0);
ADDRB : in STD_LOGIC_VECTOR (9 downto 0);
DOA : out STD_LOGIC_VECTOR (15 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0);
DOPA : out STD_LOGIC_VECTOR (1 downto 0);
DOPB : out STD_LOGIC_VECTOR (1 downto 0)
);
end component;
Constant PRIM_ADDR_WIDTH : integer := 10; -- 1024 deep
Constant PRIM_PDBUS_WIDTH : integer := 2; -- 2 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 16; -- 16 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_1024x18 : RAMB16_S18_S18
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S18_S18;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 2048 x 9 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S9_S9 : if (BRAM_PRIMITIVE = B16_S9_S9) generate
component RAMB16_S9_S9
port (
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
DIPA : in std_logic_vector (0 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPA : out std_logic_vector (0 downto 0);
DOPB : out std_logic_vector (0 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 11; -- 2048 deep
Constant PRIM_PDBUS_WIDTH : integer := 1; -- 1 parity data bit
Constant PRIM_DBUS_WIDTH : integer := 8; -- 8 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_2048x9 : RAMB16_S9_S9
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S9_S9;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 4096 x 4 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S4_S4 : if (BRAM_PRIMITIVE = B16_S4_S4) generate
component RAMB16_S4_S4
port (
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 12; -- 4096 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 4; -- 4 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_4096x4 : RAMB16_S4_S4
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S4_S4;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 8192 x 2 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S2_S2 : if (BRAM_PRIMITIVE = B16_S2_S2) generate
component RAMB16_S2_S2
port (
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (12 downto 0);
ADDRB : in std_logic_vector (12 downto 0);
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 13; -- 8192 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 2; -- 2 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_8192x2 : RAMB16_S2_S2
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S2_S2;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 16384 x 1 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S1_S1 : if (BRAM_PRIMITIVE = B16_S1_S1) generate
component RAMB16_S1_S1
port (
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (13 downto 0);
ADDRB : in std_logic_vector (13 downto 0);
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 14; -- 16384 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 1; -- 1 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_16384x1 : RAMB16_S1_S1
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S1_S1;
--==========================================================================
-- End of Virtex-II and Virtex-II Pro support
--///////////////////////////////////////////////////////////////////////////
--///////////////////////////////////////////////////////////////////////////
-- Start Spartan-II, Spartan-IIE, Virtex, and VirtexE support
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 4096 x 1 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S1_S1 : if (BRAM_PRIMITIVE = B4_S1_S1) generate
component RAMB4_S1_S1
port (
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 12; -- 4096 deep
Constant PRIM_DBUS_WIDTH : integer := 1; -- 1 data bit
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_4096x1 : RAMB4_S1_S1
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S1_S1;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 2048 x 2 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S2_S2 : if (BRAM_PRIMITIVE = B4_S2_S2) generate
component RAMB4_S2_S2
port (
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 11; -- 2048 deep
Constant PRIM_DBUS_WIDTH : integer := 2; -- 2 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_2048x2 : RAMB4_S2_S2
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S2_S2;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 1024 x 4 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S4_S4 : if (BRAM_PRIMITIVE = B4_S4_S4) generate
component RAMB4_S4_S4
port (
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (9 downto 0);
ADDRB : in std_logic_vector (9 downto 0);
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 10; -- 1024 deep
Constant PRIM_DBUS_WIDTH : integer := 4; -- 4 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_1024x4 : RAMB4_S4_S4
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S4_S4;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 512 x 8 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S8_S8 : if (BRAM_PRIMITIVE = B4_S8_S8) generate
component RAMB4_S8_S8
port (
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 9; -- 512 deep
Constant PRIM_DBUS_WIDTH : integer := 8; -- 8 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_512x8 : RAMB4_S8_S8
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S8_S8;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 256 x 16 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S16_S16 : if (BRAM_PRIMITIVE = B4_S16_S16) generate
component RAMB4_S16_S16
port (DIA : in STD_LOGIC_VECTOR (15 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (7 downto 0);
ADDRB : in STD_LOGIC_VECTOR (7 downto 0);
DOA : out STD_LOGIC_VECTOR (15 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 8; -- 256 deep
Constant PRIM_DBUS_WIDTH : integer := 16; -- 16 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_256x16 : RAMB4_S16_S16
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S16_S16;
--==========================================================================
UNSUPPORTED_FAMILY : if (BRAM_PRIMITIVE = indeterminate) generate
begin
-- assert (false)
-- report "Unsupported Part Family Selected or FIFO Depth/Width is invalid!"
-- severity failure;
--
end generate UNSUPPORTED_FAMILY;
end architecture implementation;
| apache-2.0 | 40d4a209ccbcb5876b48a4a2996224a3 | 0.371567 | 4.809031 | false | false | false | false |
sandrosalvato94/System-Design-Project | src/polito/sdp2017/Tests/registerfile.vhd | 1 | 3,472 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.all;
use WORK.constants.all;
-- N : number of register 32
-- M : bitwidth 64
-- K : number of bit address 5
entity register_file is
generic(N: integer := 32;
M: integer := 64;
K: integer := 5
);
port ( CLK: IN std_logic;
RESET: IN std_logic;
ENABLE: IN std_logic;
RD1: IN std_logic;
RD2: IN std_logic;
WR: IN std_logic;
ADD_WR: IN std_logic_vector(K-1 downto 0);
ADD_RD1: IN std_logic_vector(K-1 downto 0);
ADD_RD2: IN std_logic_vector(K-1 downto 0);
DATAIN: IN std_logic_vector(M-1 downto 0);
OUT1: OUT std_logic_vector(M-1 downto 0);
OUT2: OUT std_logic_vector(M-1 downto 0));
end register_file;
architecture Behavioral of register_file is
-- suggested structures
subtype REG_ADDR is natural range 0 to N-1; -- using natural type
type REG_ARRAY is array(REG_ADDR) of std_logic_vector(M-1 downto 0);
signal REGISTERS : REG_ARRAY;
signal cntr1,cntr2, cntr0: std_logic;
begin
-- write your RF code
wrt_proc: process(clk)
begin
if(enable = '1') then
if(clk = '1') then
if(reset = '1') then
REGISTERS <= (others => (others => '0'));
elsif(WR = '1') then
if(cntr1 = '0' AND cntr2 = '0') then --no conflict!
REGISTERS(conv_integer(ADD_WR)) <= DATAIN;
end if;
end if;
end if;
if(clk = '0') then
-- if(cntr1 = '1' OR cntr2 = '1') then
-- REGISTERS(conv_integer(ADD_WR)) <= DATAIN;
-- end if;
if(cntr0 = '1') then
REGISTERS(conv_integer(ADD_WR)) <= DATAIN;
end if;
end if;
end if;
end process;
read_proc: process(clk, enable)
begin
if(enable = '1') then
if(clk = '1' and clk'event) then
if(reset = '0') then -- if reset \= '1'
if(cntr1 = '1' or cntr2 = '1') then -- se conflitto
if(RD1 = '1') then
OUT1 <= REGISTERS(conv_integer(ADD_RD1));
end if;
if(RD2 = '1') then
OUT2 <= REGISTERS(conv_integer(ADD_RD2));
end if;
cntr0 <= '1';
else
if(RD1 = '1') then
OUT1 <= REGISTERS(conv_integer(ADD_RD1));
end if;
if(RD2 = '1') then
OUT2 <= REGISTERS(conv_integer(ADD_RD2));
end if;
cntr0 <= '0';
end if;
else
OUT1 <= (others => '0');
OUT2 <= (others => '0');
cntr0 <= '0';
end if;
end if;
end if;
end process;
-- process(cntr1, clk)
-- begin
-- if (cntr1 = '1') then -- conflict
-- if(clk = '0' and clk'event) then --updates at falling edge
-- REGISTERS(conv_integer(ADD_WR)) <= DATAIN;
-- end if;
--
-- end if;
-- end process;
--
-- process(cntr2, clk)
-- begin
-- if(cntr2 = '1') then -- conflict
-- if(clk = '0' and clk'event) then -- updates at falling edge
-- REGISTERS(conv_integer(ADD_WR)) <= DATAIN;
-- end if;
-- end if;
-- end process;
conflict: process(RD1, RD2, WR, ADD_RD1, ADD_RD2, ADD_WR)
begin
if((RD1 = '1' AND WR = '1') AND (ADD_RD1 = ADD_WR)) then
cntr1 <= '1';
else
cntr1 <= '0';
end if;
if((RD2 = '1' AND WR = '1') AND (ADD_RD2 = ADD_WR)) then
cntr2 <= '1';
else
cntr2 <= '0';
end if;
--cntr0 <= cntr1 or cntr2;
end process;
end behavioral;
----
configuration CFG_RF_BEH of register_file is
for behavioral
end for;
end configuration;
| lgpl-3.0 | 043891aff1146f87835a5939bf130fbe | 0.548387 | 2.7125 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/lmb_bram_if_cntlr_v4_0/816dc01c/hdl/vhdl/axi_interface.vhd | 1 | 9,447 | -------------------------------------------------------------------------------
-- $Id: axi_interface.vhd,v 1.1.2.3 2010/10/11 08:21:49 rolandp Exp $
-------------------------------------------------------------------------------
--
-- (c) Copyright 2003-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: axi_interface.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_interface.vhd
--
-------------------------------------------------------------------------------
-- Author: rolandp
-- Revision: $Revision: 1.1.2.3 $
-- Date: $Date: 2010/10/11 08:21:49 $
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity axi_interface is
generic (
-- AXI4-Lite slave generics
C_S_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S_AXI_HIGHADDR : std_logic_vector := X"0000_0000";
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_DATA_WIDTH : integer := 32;
C_REGADDR_WIDTH : integer := 5; -- Address bits including register offset.
C_DWIDTH : integer := 32); -- Width of data bus.
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
-- AXI4-Lite SLAVE SINGLE INTERFACE
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- lmb_bram_if_cntlr signals
RegWr : out std_logic;
RegWrData : out std_logic_vector(0 to C_DWIDTH - 1);
RegAddr : out std_logic_vector(0 to C_REGADDR_WIDTH-1);
RegRdData : in std_logic_vector(0 to C_DWIDTH - 1));
end entity axi_interface;
library unisim;
use unisim.vcomponents.all;
architecture IMP of axi_interface is
-----------------------------------------------------------------------------
-- Signal declaration
-----------------------------------------------------------------------------
signal new_write_access : std_logic;
signal new_read_access : std_logic;
signal ongoing_write : std_logic;
signal ongoing_read : std_logic;
signal S_AXI_RVALID_i : std_logic;
signal RegRdData_i : std_logic_vector(C_DWIDTH - 1 downto 0);
begin -- architecture IMP
-----------------------------------------------------------------------------
-- Handling the AXI4-Lite bus interface (AR/AW/W)
-----------------------------------------------------------------------------
-- Detect new transaction.
-- Only allow one access at a time
new_write_access <= not (ongoing_read or ongoing_write) and S_AXI_AWVALID and S_AXI_WVALID;
new_read_access <= not (ongoing_read or ongoing_write) and S_AXI_ARVALID and not new_write_access;
-- Acknowledge new transaction.
S_AXI_AWREADY <= new_write_access;
S_AXI_WREADY <= new_write_access;
S_AXI_ARREADY <= new_read_access;
-- Store register address and write data
Reg: process (LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
RegAddr <= (others => '0');
RegWrData <= (others => '0');
elsif new_write_access = '1' then
RegAddr <= S_AXI_AWADDR(C_REGADDR_WIDTH-1+2 downto 2);
RegWrData <= S_AXI_WDATA(C_DWIDTH-1 downto 0);
elsif new_read_access = '1' then
RegAddr <= S_AXI_ARADDR(C_REGADDR_WIDTH-1+2 downto 2);
end if;
end if;
end process Reg;
-- Handle write access.
WriteAccess: process (LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
ongoing_write <= '0';
elsif new_write_access = '1' then
ongoing_write <= '1';
elsif ongoing_write = '1' and S_AXI_BREADY = '1' then
ongoing_write <= '0';
end if;
RegWr <= new_write_access;
end if;
end process WriteAccess;
S_AXI_BVALID <= ongoing_write;
S_AXI_BRESP <= (others => '0');
-- Handle read access
ReadAccess: process (LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
ongoing_read <= '0';
S_AXI_RVALID_i <= '0';
elsif new_read_access = '1' then
ongoing_read <= '1';
S_AXI_RVALID_i <= '0';
elsif ongoing_read = '1' then
if S_AXI_RREADY = '1' and S_AXI_RVALID_i = '1' then
ongoing_read <= '0';
S_AXI_RVALID_i <= '0';
else
S_AXI_RVALID_i <= '1'; -- Asserted one cycle after ongoing_read to match S_AXI_RDDATA
end if;
end if;
end if;
end process ReadAccess;
S_AXI_RVALID <= S_AXI_RVALID_i;
S_AXI_RRESP <= (others => '0');
Not_All_Bits_Are_Used: if (C_DWIDTH < C_S_AXI_DATA_WIDTH) generate
begin
S_AXI_RDATA(C_S_AXI_DATA_WIDTH-1 downto C_S_AXI_DATA_WIDTH - C_DWIDTH) <= (others=>'0');
end generate Not_All_Bits_Are_Used;
RegRdData_i <= RegRdData; -- Swap to - downto
S_AXI_RDATA_DFF : for I in C_DWIDTH - 1 downto 0 generate
begin
S_AXI_RDATA_FDRE : FDRE
port map (
Q => S_AXI_RDATA(I),
C => LMB_Clk,
CE => ongoing_read,
D => RegRdData_i(I),
R => LMB_Rst);
end generate S_AXI_RDATA_DFF;
end architecture IMP;
| apache-2.0 | 55804653924b1d75d37601295791e272 | 0.545993 | 3.915044 | false | false | false | false |
CyAScott/CIS4930.DatapathSynthesisTool | docs/sample/input_des.vhd | 1 | 3,989 | ---------------------------------------------------------------------
-- --
-- This file is generated automatically by AUDI (AUtomatic --
-- Design Instantiation) system, a behavioral synthesis system, --
-- developed at the University of South Florida. This project --
-- is supported by the National Science Foundation (NSF) under --
-- the project number XYZ. If you have any questions, contact --
-- Dr. Srinivas Katkoori ([email protected]), Computer --
-- Science & Engineering Department, University of South Florida, --
-- Tampa, FL 33647. --
-- --
---------------------------------------------------------------------
--
-- Date & Time:
-- User login id/name:
--
-- File name:
-- Type:
--
-- Input aif file name:
--
-- CDFG statistics:
-- * Number of PI's:
-- * Number of PO's:
-- * Number of internal edges:
-- * Number of Operations:
-- * Conditionals:
-- * Loops:
-- * Types of Operations:
--
-- Design Flow/Algorithm Information:
-- * Scheduling Algorithm:
-- * Allocation:
-- * Binding:
-- Interconnect style: Multiplexor-Based or Bus-based
--
-- Design Information:
--
-- Datapath:
-- * Registers:
-- * Functional units:
-- * Number of Multiplexors:
-- * Number of Buses:
--
-- * Operator Binding Information:
--
-- * Register Optimization Information:
--
-- * Register Binding Information:
--
--
-- Controller:
-- * Type: Moore/Mealy
-- * Number of states:
-- * Number of control bits:
--
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library Beh_Lib;
use Beh_Lib.all;
entity input is
port(
a : IN std_logic_vector(3 downto 0);
b : IN std_logic_vector(3 downto 0);
c : IN std_logic_vector(3 downto 0);
d : IN std_logic_vector(3 downto 0);
e : IN std_logic_vector(3 downto 0);
f : IN std_logic_vector(3 downto 0);
g : IN std_logic_vector(3 downto 0);
h : IN std_logic_vector(3 downto 0);
i : OUT std_logic_vector(3 downto 0);
clock : IN Std_logic;
s_tart : IN Std_logic;
clear : IN Std_logic;
Finish : OUT Std_logic);
end input;
architecture RTL of input is
component input_controller
port(clock, reset : IN Std_logic;
s_tart : IN Std_logic;
finish : Out Std_logic;
control_out : Out Std_logic_vector(0 to 14));
end component;
for all : input_controller use entity Work.input_controller(Moore);
component input_dp
port( a : IN std_logic_vector(3 downto 0);
b : IN std_logic_vector(3 downto 0);
c : IN std_logic_vector(3 downto 0);
d : IN std_logic_vector(3 downto 0);
e : IN std_logic_vector(3 downto 0);
f : IN std_logic_vector(3 downto 0);
g : IN std_logic_vector(3 downto 0);
h : IN std_logic_vector(3 downto 0);
i : OUT std_logic_vector(3 downto 0);
ctrl: IN std_logic_vector(14 downto 0);
clear: IN std_logic;
clock: IN std_logic);
end component;
for all : input_dp use entity Work.input_dp(RTL);
signal sig_con_out : Std_logic_Vector(0 to 14);
begin
inputcon : input_controller
port map(clock => clock,
s_tart => s_tart,
reset => clear,
finish => finish,
control_out => sig_con_out);
inputdp : input_dp
port map(
a => a,
b => b,
c => c,
d => d,
e => e,
f => f,
g => g,
h => h,
i => i,
ctrl(0) => sig_con_out(0),
ctrl(1) => sig_con_out(1),
ctrl(2) => sig_con_out(2),
ctrl(3) => sig_con_out(3),
ctrl(4) => sig_con_out(4),
ctrl(5) => sig_con_out(5),
ctrl(6) => sig_con_out(6),
ctrl(7) => sig_con_out(7),
ctrl(8) => sig_con_out(8),
ctrl(9) => sig_con_out(9),
ctrl(10) => sig_con_out(10),
ctrl(11) => sig_con_out(11),
ctrl(12) => sig_con_out(12),
ctrl(13) => sig_con_out(13),
ctrl(14) => sig_con_out(14),
clock => clock,
clear => clear);
end RTL; | mit | 8bee1a68754a4fe0237694b852804871 | 0.551015 | 3.049694 | false | false | false | false |
marceloboeira/vhdl-examples | 008-state-machine-calculator/_example/meu_projeto.vhd | 1 | 1,818 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:20:16 11/04/2014
-- Design Name:
-- Module Name: meu_projeto - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity meu_projeto is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
botao : in STD_LOGIC;
saida : out STD_LOGIC_VECTOR (15 downto 0);
led : out STD_LOGIC);
end meu_projeto;
architecture Behavioral of meu_projeto is
signal clk1s : std_logic;
signal cnt : integer range 0 to 9999;
begin
conta_botao : process (reset, botao)
begin
if reset = '1' then
cnt <= 0;
elsif botao'event and botao='1' then
cnt <= cnt +1;
else
cnt <= cnt;
end if;
end process;
saida <= conv_std_logic_vector(cnt,16);
pisca_led : process (reset, clock)
variable cnt : integer range 0 to 25000001;
begin
if reset = '1' then
clk1s <= '0';
cnt := 0;
elsif clock'event and clock ='1' then
if(cnt >= 25000000) then
clk1s <= not clk1s;
cnt := 0;
else
cnt := cnt +1;
end if;
else
cnt := cnt;
end if;
end process;
led <= clk1s;
end Behavioral;
| mit | cd088436b48908c5c73288295d689c98 | 0.567107 | 3.348066 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/common/wr_pf_as.vhd | 5 | 27,402 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 18544)
`protect data_block
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`protect end_protected
| apache-2.0 | 855cb32d65558ed29b385bf87bcf95a0 | 0.944931 | 1.832542 | false | false | false | false |
freecores/twofish | vhdl/twofish_testbenches_secondary_circuits.vhd | 1 | 3,119 | -- Twofish_testbenches_secondary_circuits.vhd
-- Copyright (C) 2006 Spyros Ninos
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this library; see the file COPYING. If not, write to:
--
-- Free Software Foundation
-- 59 Temple Place - Suite 330
-- Boston, MA 02111-1307, USA.
--
-- description : this file contains all the secondary circuits that are needed for running the testbenches
--
--
-- reg128
--
library ieee;
use ieee.std_logic_1164.all;
entity reg128 is
port ( in_reg128 : in std_logic_vector(127 downto 0);
out_reg128 : out std_logic_vector(127 downto 0);
enable_reg128, reset_reg128,clk_reg128 : in std_logic
);
end reg128;
architecture reg128_arch of reg128 is
begin
clk_proc: process(clk_reg128, reset_reg128,enable_reg128)
variable internal_state : std_logic_vector(127 downto 0);
begin
if reset_reg128 = '1' then
internal_state := ( others => '0' );
elsif (clk_reg128'event and clk_reg128 = '1') then
if enable_reg128='1' then
internal_state := in_reg128;
else
internal_state := internal_state;
end if;
end if;
out_reg128 <= internal_state;
end process clk_proc;
end reg128_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- mux128
--
library ieee;
use ieee.std_logic_1164.all;
entity mux128 is
port ( in1_mux128, in2_mux128 : in std_logic_vector(127 downto 0);
selection_mux128 : in std_logic;
out_mux128 : out std_logic_vector(127 downto 0)
);
end mux128;
architecture mux128_arch of mux128 is
begin
with selection_mux128 select
out_mux128 <= in1_mux128 when '0',
in2_mux128 when others;
end mux128_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- demux128
--
library ieee;
use ieee.std_logic_1164.all;
entity demux128 is
port ( in_demux128 : in std_logic_vector(127 downto 0);
out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0);
selection_demux128 : in std_logic
);
end demux128;
architecture demux128_arch of demux128 is
begin
demux_proc: process(in_demux128, selection_demux128)
begin
if selection_demux128 = '0' then
out1_demux128 <= in_demux128;
else
out2_demux128 <= in_demux128;
end if;
end process demux_proc;
end demux128_arch;
| gpl-2.0 | 37cacd8a81e70c2572eeb34b51a2f058 | 0.613658 | 3.461709 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/LEKO_LEKU/leko/g625.vhd | 1 | 670,739 | -- Xilinx XPort Language Converter, Version 4.1 (110)
--
-- ABEL Design Source: C:\home\kirill\xillinx\testing.abl
-- VHDL Design Output: testing.vhd
-- Created 01-Sep-2005 07:40 PM
--
-- Copyright (c) 2005, Xilinx, Inc. All Rights Reserved.
-- Xilinx Inc makes no warranty, expressed or implied, with respect to
-- the operation and/or functionality of the converted output files.
--
-- ee200 assignment 1
Library IEEE;
use IEEE.std_logic_1164.all;
entity testing is
Port (
A4927, A6112: buffer std_logic;
B7362: in std_logic;
A4530, A6673: buffer std_logic;
B7030: in std_logic;
A5583: buffer std_logic;
B8945: in std_logic;
A3210, A4263, A3044, A6904: buffer std_logic;
B5613, B9011: in std_logic;
A4498: buffer std_logic;
B6374: in std_logic;
A5485: buffer std_logic;
B7264, B5644, B7693: in std_logic;
A3702, A5451: buffer std_logic;
B6636: in std_logic;
A6575: buffer std_logic;
B5812: in std_logic;
A3243, A6047, A6179, A3572: buffer std_logic;
B8517: in std_logic;
A5520, A4560: buffer std_logic;
B8156, B7727: in std_logic;
A5221: buffer std_logic;
B9145, B8287: in std_logic;
A3867: buffer std_logic;
B6440: in std_logic;
A6245: buffer std_logic;
B6076: in std_logic;
A6804, A3439: buffer std_logic;
B6869, B6737: in std_logic;
A5422, A5090: buffer std_logic;
B8024, B5415, B6274, B7756: in std_logic;
A4362: buffer std_logic;
B7397, B7526, B9179, B7163: in std_logic;
A4267, A5121, A3341, A6510: buffer std_logic;
B6176, B7132: in std_logic;
A4032, A6012, A2947, A3475: buffer std_logic;
B6471, B8086, B8812: in std_logic;
A5649: buffer std_logic;
B6902: in std_logic;
A4396, A6310, A6643: buffer std_logic;
B7129, B6536, B8684: in std_logic;
A3009, A5848: buffer std_logic;
B9047: in std_logic;
A5289, A3075: buffer std_logic;
B5878, B5581, B5380, B7229: in std_logic;
A3077, A3176, A4791, A5851, A5125: buffer std_logic;
B7198: in std_logic;
A5191: buffer std_logic;
B7098: in std_logic;
A5056: buffer std_logic;
B8218: in std_logic;
A4034, A6276, A3109, A4068: buffer std_logic;
B5549: in std_logic;
A3178, A4663, A3838, A4201: buffer std_logic;
B5578, B9109: in std_logic;
A4662: buffer std_logic;
B8714: in std_logic;
A6211: buffer std_logic;
B6106: in std_logic;
A3606, A2914, A6144: buffer std_logic;
B6572: in std_logic;
A6046: buffer std_logic;
B8055, B8581: in std_logic;
A5651: buffer std_logic;
B6110, B5482, B5383, B8651, B8849: in std_logic;
A6279, A4725, A5816: buffer std_logic;
B6601, B7987, B9079, B5281: in std_logic;
A4793: buffer std_logic;
B6207, B5217, B6836, B8947, B6967: in std_logic;
A2813: buffer std_logic;
B8911: in std_logic;
A4197: buffer std_logic;
B7130: in std_logic;
A3603: buffer std_logic;
B5976, B5842, B6635: in std_logic;
A6676: buffer std_logic;
B5250, B5843: in std_logic;
A3376, A5319, A4593, A6873: buffer std_logic;
B5347: in std_logic;
A6607, A3043, A3078, A3768: buffer std_logic;
B6504: in std_logic;
A4298, A5223: buffer std_logic;
B8384: in std_logic;
A3144, A5521, A4496: buffer std_logic;
B5315: in std_logic;
A6243: buffer std_logic;
B7294, B8022: in std_logic;
A6573, A4465: buffer std_logic;
B6074, B7990: in std_logic;
A5585: buffer std_logic;
B6473, B5711: in std_logic;
A4925, A5418: buffer std_logic;
B9077, B8188, B7231: in std_logic;
A4858: buffer std_logic;
B7262: in std_logic;
A6841: buffer std_logic;
B9212: in std_logic;
A4168: buffer std_logic;
B7461, B7559, B8451, B7492, B7989: in std_logic;
A3209: buffer std_logic;
B8814, B8550, B9276, B6304, B6770, B7857: in std_logic;
A6641: buffer std_logic;
B8682: in std_logic;
A6345: buffer std_logic;
B6143, B8485, B7628, B6174: in std_logic;
A4758: buffer std_logic;
B5382: in std_logic;
A5946, A3540: buffer std_logic;
B8782: in std_logic;
A4066, A5387: buffer std_logic;
B7591: in std_logic;
A3012, A6312: buffer std_logic;
B7921, B5743: in std_logic;
A6177: buffer std_logic;
B8420, B7658: in std_logic;
A6906: buffer std_logic;
B7888, B6571, B7891: in std_logic;
A3406: buffer std_logic;
B7956, B5875, B6141: in std_logic;
A3574: buffer std_logic;
B6538: in std_logic;
A4464: buffer std_logic;
B5546: in std_logic;
A3671, A2846, A6078, A6806, A5748: buffer std_logic;
B5283, B8185, B6502: in std_logic;
A3507: buffer std_logic;
B5219, B8717: in std_logic;
A3737, A3835, A3441, A3735, A3969, A6839, A3868, A3374, A6379, A3308:
buffer std_logic;
B5516, B6999: in std_logic;
A5686: buffer std_logic;
B8615, B8053: in std_logic;
A3273: buffer std_logic;
B6040, B5911, B7561: in std_logic;
A4660, A5092, A3870, A6213, A5022: buffer std_logic;
B6108, B7327: in std_logic;
A6870, A6707: buffer std_logic;
B7067, B8285, B5349, B5681: in std_logic;
A5187: buffer std_logic;
B8254, B6008: in std_logic;
A3903, A5653: buffer std_logic;
B6604, B9241, B5417: in std_logic;
A6837, A4696: buffer std_logic;
B8350, B7429: in std_logic;
A2979, A4828: buffer std_logic;
B5646: in std_logic;
A3409, A4230, A5553: buffer std_logic;
B6372, B7760: in std_logic;
A3538: buffer std_logic;
B6172: in std_logic;
A4727: buffer std_logic;
B8088: in std_logic;
A5123: buffer std_logic;
B8352, B6638: in std_logic;
A2811: buffer std_logic;
B5974: in std_logic;
A5257: buffer std_logic;
B5480: in std_logic;
A3670, A3706, A3970: buffer std_logic;
B8320: in std_logic;
A5091: buffer std_logic;
B7560, B5909, B5648, B7166, B5978: in std_logic;
A4628, A5587: buffer std_logic;
B6403: in std_logic;
A4431: buffer std_logic;
B8681, B6733, B7626: in std_logic;
A6907: buffer std_logic;
B7725, B7859: in std_logic;
A4626: buffer std_logic;
B8152: in std_logic;
A3440, A6309: buffer std_logic;
B6734, B6506, B5350: in std_logic;
A6708, A3508: buffer std_logic;
B5679, B5944: in std_logic;
A5718: buffer std_logic;
B5582: in std_logic;
A6410, A3805, A5948: buffer std_logic;
B6935: in std_logic;
A6313, A6872: buffer std_logic;
B8649: in std_logic;
A2911: buffer std_logic;
B7393, B8552, B8879, B7558: in std_logic;
A2977, A5057: buffer std_logic;
B8452, B8419, B8255, B7066, B6240: in std_logic;
A4462, A4365, A6180: buffer std_logic;
B5317, B6306: in std_logic;
A5979: buffer std_logic;
B6865, B8020: in std_logic;
A5353, A6508, A5224, A3837, A6477, A3211: buffer std_logic;
B7328: in std_logic;
A2913, A5290: buffer std_logic;
B8155: in std_logic;
A6544: buffer std_logic;
B8915: in std_logic;
A3966: buffer std_logic;
B5414, B7690, B7923, B6703: in std_logic;
A5154, A4826: buffer std_logic;
B9175, B7295: in std_logic;
A5026: buffer std_logic;
B8617, B7131, B6011: in std_logic;
A4265, A4694: buffer std_logic;
B8977, B6338: in std_logic;
A5519, A5916: buffer std_logic;
B6206: in std_logic;
A5982, A6574, A4924: buffer std_logic;
B7789: in std_logic;
A3275, A4002, A4231: buffer std_logic;
B5877, B7496: in std_logic;
A2944, A4165, A5815, A3739, A4398, A6808: buffer std_logic;
B8780, B7823: in std_logic;
A5455: buffer std_logic;
B5448, B5182: in std_logic;
A3111, A4135, A4529: buffer std_logic;
B7758: in std_logic;
A5517: buffer std_logic;
B9112: in std_logic;
A5025, A3771, A3935: buffer std_logic;
B6667, B8090: in std_logic;
A5550: buffer std_logic;
B7196: in std_logic;
A3306: buffer std_logic;
B7660: in std_logic;
A4989: buffer std_logic;
B7426, B9243, B7331: in std_logic;
A3373: buffer std_logic;
B7988, B7427, B8221: in std_logic;
A5059: buffer std_logic;
B5450: in std_logic;
A6443: buffer std_logic;
B6867: in std_logic;
A3340: buffer std_logic;
B5615: in std_logic;
A5784: buffer std_logic;
B7657, B5809, B6042, B6273: in std_logic;
A6111, A6148, A4759: buffer std_logic;
B9110, B5314: in std_logic;
A4594: buffer std_logic;
B8748, B8317: in std_logic;
A5421, A4958: buffer std_logic;
B7001, B7463: in std_logic;
A5385, A6773: buffer std_logic;
B8846: in std_logic;
A5620: buffer std_logic;
B5285, B6899, B6340: in std_logic;
A6210, A5717: buffer std_logic;
B8583: in std_logic;
A4957: buffer std_logic;
B6568: in std_logic;
A3241: buffer std_logic;
B7298: in std_logic;
A4893, A6114: buffer std_logic;
B6406: in std_logic;
A6706, A6049, A4794: buffer std_logic;
B5845: in std_logic;
A5256, A6475: buffer std_logic;
B8253, B5942, B8387, B8515, B7594: in std_logic;
A6342: buffer std_logic;
B7395: in std_logic;
A3704, A3342, A6772, A3506, A4891: buffer std_logic;
B8747, B7659, B6931, B7856: in std_logic;
A4102: buffer std_logic;
B8123: in std_logic;
A4198, A5389: buffer std_logic;
B9043: in std_logic;
A3438, A4824: buffer std_logic;
B6933: in std_logic;
A3442, A3208: buffer std_logic;
B9209, B8944: in std_logic;
A6412: buffer std_logic;
B6242: in std_logic;
A6542, A2877: buffer std_logic;
B5677: in std_logic;
A5618: buffer std_logic;
B8746, B5251: in std_logic;
A4563: buffer std_logic;
B8618, B5747, B5611: in std_logic;
A2878, A3240: buffer std_logic;
B5645: in std_logic;
A2880, A5554: buffer std_logic;
B6736, B5216, B7430, B6800, B6308: in std_logic;
A2945: buffer std_logic;
B5384: in std_logic;
A6874: buffer std_logic;
B5479: in std_logic;
A3045: buffer std_logic;
B6769: in std_logic;
A6014: buffer std_logic;
B7232, B6436, B7958, B7624: in std_logic;
A3541, A5287: buffer std_logic;
B8386, B9244, B9013: in std_logic;
A3933: buffer std_logic;
B5248: in std_logic;
A4233, A6675, A5715, A4036, A4861: buffer std_logic;
B7925, B8089, B8847, B9010, B7033, B7494, B8881, B6766: in std_logic;
A5881: buffer std_logic;
B8417, B8979, B5580, B7297: in std_logic;
A5750: buffer std_logic;
B8518, B7133, B6997: in std_logic;
A4333, A6146: buffer std_logic;
B6044: in std_logic;
A5914, A4264: buffer std_logic;
B7529: in std_logic;
A5650: buffer std_logic;
B5778: in std_logic;
A5322: buffer std_logic;
B7825: in std_logic;
A4760, A5817, A3637, A4099, A6247, A6742: buffer std_logic;
B8121, B9274: in std_logic;
A6577, A4993: buffer std_logic;
B8980: in std_logic;
A2815: buffer std_logic;
B5184, B5712, B7363, B7954, B6701: in std_logic;
A4000, A3472: buffer std_logic;
B8585: in std_logic;
A3902, A5782: buffer std_logic;
B7790, B8750, B8549, B8913: in std_logic;
A3570: buffer std_logic;
B9210, B6965, B8483, B8319: in std_logic;
A5883: buffer std_logic;
B7692: in std_logic;
A5253, A5950, A4101, A6444: buffer std_logic;
B7063, B6669: in std_logic;
A3277, A6081: buffer std_logic;
B5513: in std_logic;
A4363, A3605, A3869, A5122, A2980: buffer std_logic;
B8878: in std_logic;
A4792: buffer std_logic;
B5548, B7199: in std_logic;
A3801, A5619: buffer std_logic;
B8416, B6605, B8848, B8981: in std_logic;
A5352, A6441: buffer std_logic;
B6241, B5975, B6107, B8948, B7097, B5745: in std_logic;
A4199, A6903: buffer std_logic;
B5579: in std_logic;
A3309, A3871, A3177, A3175: buffer std_logic;
B8219, B6009: in std_logic;
A5190, A5552: buffer std_logic;
B5318: in std_logic;
A6378: buffer std_logic;
B6832: in std_logic;
A4661, A6212: buffer std_logic;
B8551, B6802, B7627: in std_logic;
A4726, A3640, A6409: buffer std_logic;
B7034, B9177, B6469, B8582: in std_logic;
A3900: buffer std_logic;
B8880, B8912: in std_logic;
A3770, A6346: buffer std_logic;
B7100: in std_logic;
A5454: buffer std_logic;
B9044: in std_logic;
A4331: buffer std_logic;
B9076, B6570, B8650: in std_logic;
A4991, A2814, A5652, A6709: buffer std_logic;
B5483: in std_logic;
A6639, A3339: buffer std_logic;
B6371, B5218: in std_logic;
A4035: buffer std_logic;
B7228, B6272: in std_logic;
A4300: buffer std_logic;
B5844, B5714: in std_logic;
A4857: buffer std_logic;
B7361, B6637, B6472, B5776, B6407, B7694: in std_logic;
A5484: buffer std_logic;
B8087, B7826: in std_logic;
A6246, A5089, A6080: buffer std_logic;
B9142: in std_logic;
A3042: buffer std_logic;
B6833: in std_logic;
A2879, A6606, A6738, A3408: buffer std_logic;
B7032: in std_logic;
A5320: buffer std_logic;
B5780: in std_logic;
A6541: buffer std_logic;
B6208: in std_logic;
A3145: buffer std_logic;
B8946: in std_logic;
A6775, A4131: buffer std_logic;
B8286: in std_logic;
A4299, A3242, A3310, A3407: buffer std_logic;
B5680: in std_logic;
A6048, A3639: buffer std_logic;
B7527: in std_logic;
A3079: buffer std_logic;
B6339, B7858: in std_logic;
A6511: buffer std_logic;
B5647, B5912, B8813, B7723: in std_logic;
A6408: buffer std_logic;
B6175, B6075: in std_logic;
A2845: buffer std_logic;
B5813: in std_logic;
A4497, A3474: buffer std_logic;
B6373, B8683, B5249: in std_logic;
A3571: buffer std_logic;
B5416: in std_logic;
A4761: buffer std_logic;
B7793, B7265: in std_logic;
A3672, A3141: buffer std_logic;
B8351, B7162, B6768: in std_logic;
A6178, A4693, A3669: buffer std_logic;
B5910: in std_logic;
A4429, A6478, A3736: buffer std_logic;
B5515: in std_logic;
A3738: buffer std_logic;
B8486: in std_logic;
A5850: buffer std_logic;
B8716, B7197: in std_logic;
A4827, A3834, A3803, A3937, A6280: buffer std_logic;
B6007, B5879: in std_logic;
A3607, A3375: buffer std_logic;
B8189, B6173: in std_logic;
A6344, A6610, A6509: buffer std_logic;
B8614: in std_logic;
A5055, A3108: buffer std_logic;
B6503: in std_logic;
A5323, A4728, A5685, A4428, A5917, A6376, A4596, A2910: buffer std_logic;
B5481: in std_logic;
A5486: buffer std_logic;
B9046, B6603, B6239: in std_logic;
A6045: buffer std_logic;
B9242: in std_logic;
A4033: buffer std_logic;
B8054, B6139: in std_logic;
A5058: buffer std_logic;
B8516, B6109: in std_logic;
A5189: buffer std_logic;
B8647: in std_logic;
A4200: buffer std_logic;
B6438: in std_logic;
A6838: buffer std_logic;
B5348, B7099, B5977, B8187, B8353: in std_logic;
A2812: buffer std_logic;
B6671: in std_logic;
A3244, A5355, A5188, A4296, A4960, A5818, A5222, A5023: buffer std_logic;
B8450: in std_logic;
A3143, A2847: buffer std_logic;
B6799, B6835, B7261, B6968: in std_logic;
A6905: buffer std_logic;
B9144: in std_logic;
A4926, A6244, A4329, A5286: buffer std_logic;
B5351: in std_logic;
A6674, A4430, A4561, A5158: buffer std_logic;
B7991: in std_logic;
A5981, A5452: buffer std_logic;
B5811: in std_logic;
A6576, A3471: buffer std_logic;
B6073: in std_logic;
A4495: buffer std_logic;
B5186, B6205, B7230: in std_logic;
A6608, A4297: buffer std_logic;
B7031, B6140: in std_logic;
A4659: buffer std_logic;
B6142, B7661: in std_logic;
A6840: buffer std_logic;
B5612: in std_logic;
A6278, A5752, A4167: buffer std_logic;
B7525: in std_logic;
A6411: buffer std_logic;
B6602, B6238: in std_logic;
A3076: buffer std_logic;
B7164: in std_logic;
A4860: buffer std_logic;
B7957: in std_logic;
A3968, A3011: buffer std_logic;
B6271: in std_logic;
A5749: buffer std_logic;
B9277, B8815, B7592: in std_logic;
A6805, A6181: buffer std_logic;
B5945, B5381: in std_logic;
A6016, A4762, A6642, A4069: buffer std_logic;
B7394: in std_logic;
A4531: buffer std_logic;
B7460: in std_logic;
A5683: buffer std_logic;
B7889: in std_logic;
A4133: buffer std_logic;
B8023, B6901: in std_logic;
A3405: buffer std_logic;
B7922, B7263, B6535, B5810: in std_logic;
A5388, A3573, A5947, A4630, A6079: buffer std_logic;
B6437: in std_logic;
A3936, A4266: buffer std_logic;
B5252, B8186, B7757, B8616: in std_logic;
A6147, A5884, A3274, A6741, A6705: buffer std_logic;
B8453, B7296: in std_logic;
A5847: buffer std_logic;
B8781, B7890: in std_logic;
A4528, A4232, A5356, A4825: buffer std_logic;
B7428, B5183: in std_logic;
A4695, A5551: buffer std_logic;
B9278, B6370: in std_logic;
A3967: buffer std_logic;
B6704, B7495: in std_logic;
A6214: buffer std_logic;
B8122: in std_logic;
A5518, A3636: buffer std_logic;
B9176, B5282: in std_logic;
A4003, A6277: buffer std_logic;
B7822: in std_logic;
A5321, A5024, A3276: buffer std_logic;
B5447, B8680: in std_logic;
A4527, A3112: buffer std_logic;
B9211: in std_logic;
A6082, A5419, A3673, A6640, A3537, A5488, A2943: buffer std_logic;
B7955, B6668, B8783: in std_logic;
A6442, A5157: buffer std_logic;
B8482, B7459: in std_logic;
A4395: buffer std_logic;
B7462, B9113, B6868: in std_logic;
A4132, A4166: buffer std_logic;
B6767: in std_logic;
A4597: buffer std_logic;
B5514, B8978, B8284: in std_logic;
A5915: buffer std_logic;
B5614, B7593: in std_logic;
A3307: buffer std_logic;
B7360: in std_logic;
A3142: buffer std_logic;
B9080: in std_logic;
A6115: buffer std_logic;
B8318: in std_logic;
A6015, A5584: buffer std_logic;
B6041, B8749, B6404: in std_logic;
A5386, A4595: buffer std_logic;
B7064: in std_logic;
A5716, A4729, A3705, A3904: buffer std_logic;
B7065: in std_logic;
A3343, A6774: buffer std_logic;
B8252, B6900: in std_logic;
A6311, A5684: buffer std_logic;
B5710: in std_logic;
A4494, A3013: buffer std_logic;
B5413, B8321, B8648, B5943, B7562, B8449, B6866, B8548: in std_logic;
A4890, A5719: buffer std_logic;
B5678: in std_logic;
A6343, A3505, A3802: buffer std_logic;
B7165, B8119: in std_logic;
A2881, A4432: buffer std_logic;
B9014, B8383: in std_logic;
A5783, A4366: buffer std_logic;
B7396: in std_logic;
A4364: buffer std_logic;
B5316: in std_logic;
A6507, A6476, A6377, A6543, A6807, A4923: buffer std_logic;
B6305, B8021, B5547, B8418: in std_logic;
A4463: buffer std_logic;
B8816, B8354, B6702: in std_logic;
A4399: buffer std_logic;
B5746, B9146, B7625, B5446, B7726, B6537: in std_logic;
A2848, A5980, A5949, A2978: buffer std_logic;
B5779: in std_logic;
A4067: buffer std_logic;
B6801, B8713, B9275, B6670: in std_logic;
A5880: buffer std_logic;
B8153: in std_logic;
A5487: buffer std_logic;
B9245: in std_logic;
A6672: buffer std_logic;
B6209, B9143, B6337, B5777, B6964: in std_logic;
A5751: buffer std_logic;
B8484, B7691: in std_logic;
A4332, A4164: buffer std_logic;
B5449, B6307: in std_logic;
A5420, A3934: buffer std_logic;
B7924, B8882: in std_logic;
A5913, A6739, A6145: buffer std_logic;
B8715: in std_logic;
A4001: buffer std_logic;
B6043, B8584: in std_logic;
A5354, A5155: buffer std_logic;
B7195, B7791, B8385: in std_logic;
A3110: buffer std_logic;
B8519, B7824, B7364, B7892: in std_logic;
A5785, A3638, A3010, A4234: buffer std_logic;
B8120, B5876: in std_logic;
A4134: buffer std_logic;
B9012: in std_logic;
A3772: buffer std_logic;
B6505, B7330, B9078: in std_logic;
A4992: buffer std_logic;
B6966: in std_logic;
A5586: buffer std_logic;
B6634, B5185: in std_logic;
A4330, A6445, A4100, A2844: buffer std_logic;
B8288, B8222, B5512: in std_logic;
A3901: buffer std_logic;
B9111: in std_logic;
A3473, A5254, A5255, A4627, A6609: buffer std_logic;
B7595: in std_logic;
A3769, A5781, A5288, A5124, A3604: buffer std_logic;
B6700: in std_logic;
A5882: buffer std_logic;
B5908: in std_logic;
A4692: buffer std_logic;
B8220: in std_logic;
A5220, A6740, A3372: buffer std_logic;
B7528, B7096, B7792, B6898: in std_logic;
A4959, A5616: buffer std_logic;
B6010, B6934, B5941: in std_logic;
A4629: buffer std_logic;
B7759: in std_logic;
A4956, A3539: buffer std_logic;
B8251, B6077, B7329, B6569: in std_logic;
A4859: buffer std_logic;
B6735, B6932: in std_logic;
A6113: buffer std_logic;
B6275: in std_logic;
A3703: buffer std_logic;
B8057: in std_logic;
A4795, A3804: buffer std_logic;
B7855: in std_logic;
A3207: buffer std_logic;
B5846, B5284: in std_logic;
A4894: buffer std_logic;
B6341: in std_logic;
A3174: buffer std_logic;
B5545, B7000, B8056, B6405: in std_logic;
A4065: buffer std_logic;
B7724: in std_logic;
A3046, A5682, A4892, A5156: buffer std_logic;
B5744, B8154: in std_logic;
A4461: buffer std_logic;
B6539: in std_logic;
A6871: buffer std_logic;
B6803, B5215, B8779: in std_logic;
A6771, A5617, A6474, A6375, A6013, A3836, A4564, A5983, A4990: buffer
std_logic;
B9208: in std_logic;
A6540, A4397, A3504: buffer std_logic;
B8845, B7493, B9178: in std_logic;
A4562: buffer std_logic;
B6439: in std_logic;
A2946, A4098, A2912, A5849: buffer std_logic;
B6998, B8914: in std_logic;
A3999, A5814: buffer std_logic;
B6470: in std_logic;
A2976: buffer std_logic;
B6834, B9045, B5713: in std_logic;
A5453, A5088: buffer std_logic
);
end testing;
architecture testing_behav of testing is
signal B3558, B7543, B5269, B8370, B5868, B7775, B9072, B1469, B3363, B5861,
B3519, A7214, A5860, B4683, A8424, A7048, B5206, A9214, A9297, B7221,
A5840, A3589, A4499, A6787, B4170, A2949, B7682, B9071, B3738, A4310,
A3532, B9238, A9281, A9047, B2495, B8314, A5054, B3872, B5338, B3011,
B7588, A9038, A6647, B4150, A7702, B469, A7709, A2951, B6419, A7315,
B6002, A3814, A8023, A3519, B4872, A7893, A3989, A3609, A2962, B4266,
B5275, A9768, B4226, A8927, B682, B7732, B7886, B5109, A4434, B4626,
A8123, A4814, B8836, A8750, B6327, A4436, B6098, B1219, A6780, A2856,
B2161, B9020, A8726, B2445, B8315, B4367, B1765, B499, B3308, B3920,
A5734, A3133, B3961, B6853, B4309, B2727, B2175, B7521, B60, B4413,
A9400, A3557, B2667, B3897, B3799, A7065, B1569, A4450, B7840, A4120,
A3980, B5236, A8118, B8372, B3881, B6087, A3282, A3997, B6435, B688,
B4590, A9312, B3157, B5057, A7494, A6019, B8377, B2929, A3590, B3304,
B1825, A3114, B3606, B1338, B8476, A8075, B3550, A5869, A3029, B8264,
B9268, A3791, A8278, B3788, B538, A5658, B6413, B854, B6285, B2742,
B8097, B874, B6555, A5042, A6929, A2991, A9254, A4664, A8115, A3411,
B5703, B5132, B8162, B116, A7433, A9776, A7060, B4405, B9100, A9300,
B5621, A4647, B1538, B2060, B3532, B2109, B4535, A8708, B6534, A6234,
A6171, A4184, B3273, A8640, B90, A6794, B2312, A3512, B2501, B1131,
B3077, B9019, A3483, B3520, B1794, B6872, B7114, B4604, B99, B2065,
B8530, A5099, B8060, B7120, A7450, B4537, A6628, B4654, B8770, A9726,
A7123, B1829, B7788, B8405, B3372, B7017, B891, A6619, B4299, B2181,
B785, B5871, B1952, A7935, B6353, B2545, B4404, B9134, A8337, A3827,
A2909, B7106, B8197, B3695, B4863, B6020, A5954, B2481, A7847, B5061,
A6682, A6335, A8088, B479, B4661, A3057, B8468, A6077, A8930, B3929,
B2486, B5254, B8761, B6673, A6652, B1115, A3502, A7007, B2219, B7143,
A5677, B5378, B6114, A7262, B6752, B6657, B7973, B2043, B9293, B492,
B8988, B2850, A8271, B8428, B5360, B2613, B1905, A7111, A8084, A5725,
A8608, B4584, A9622, B2185, B2657, A3258, B9199, A7167, B2047, B2231,
A4797, B5737, A8631, B5792, B8719, A7812, A5976, B6486, A5742, B7051,
B343, B3200, B7914, B8593, A4475, B3342, A3973, B7086, A4897, B8004,
B3349, A3680, A7083, A7284, B4964, B4462, B4386, A7954, A9505, B3510,
A9828, A7963, B637, B7769, B8275, A7235, B4838, B2903, B8398, B955,
A5501, B1591, A9821, B8016, A4473, B293, A8979, B2738, A7462, B7948,
A7855, A9009, A9274, A7341, B4073, B2861, A3694, B1014, A6762, A4138,
B4093, B7272, B8028, A3246, B8637, B1501, A4457, A5038, A8829, A6614,
B7454, A8070, A3066, B2197, A8719, A9898, B747, B7802, A3334, A7263,
B8975, B7800, A6800, A3289, B5245, B1431, A8820, B8710, B2459, A4021,
B8560, B6912, A6924, A3251, B5204, A9758, B1710, A5858, B8572, A5664,
A5707, A5208, A5198, B3255, B8808, B4498, A5640, B4066, A7558, A6850,
B1456, A9974, B183, A6556, B8493, A5610, A9238, A9716, A6195, B303,
B4133, B4833, A7466, B5128, B5017, B4453, B8117, B4900, B1262, A8402,
A3404, A7593, B1196, B2516, B7218, B1446, B185, A6857, B7267, B6684,
A8471, B2937, A5368, B7400, B6984, A3186, A4209, B7279, A9571, A8354,
A7924, A8853, A5465, B2332, A5126, B4168, B4981, B1319, A4849, B1149,
A7796, B6510, B6330, B3576, B2347, B661, B4581, A7349, B7211, A7243,
B2236, B2028, B928, A6314, A8649, B597, B1275, A7677, A6007, A5933,
A6520, B6047, B3722, B8169, B124, A4850, B1923, B4614, B6196, A7036,
B6889, B1990, B2021, B7535, A3166, A7118, A4422, A3602, A9772, B6844,
B9117, B7439, B2913, B6159, B3216, A6196, B3094, B4506, A2942, A9995,
B4556, A7829, B6739, B7832, B3029, B2124, A8792, B742, B654, A9002,
B3176, B6243, B2360, B2, A3022, A6402, A4406, A6500, A6163, A5073,
B8006, A5235, A6942, B1862, A7711, B4186, A3467, B7391, B6759, A7393,
B5461, A3302, B7679, A9618, B4288, B935, B3469, B8818, B8553, A2821,
A7619, B6681, A8246, B4814, B6394, A7574, A3461, A6989, B3593, B2980,
B8724, A6810, A5346, B4955, B8037, B4709, B2868, B9027, A8817, A8990,
B4947, B1593, A4009, B1488, B4513, B6514, B2382, B7487, A6110, B1966,
A7055, A8652, B767, B9124, B1047, A5119, A3389, B8158, B2273, B9164,
B6882, A5019, B365, B6166, B7876, B1157, B3202, B3511, A9651, B6913,
A8909, B249, A6135, A7012, B9062, B151, B3022, A5524, B2681, B6710,
B5735, A7415, B2074, B7903, B8423, A5478, B7896, A8495, A3662, B5558,
B6050, A2927, B6226, A7685, A8759, A9721, B4530, B3225, A3858, A6960,
B1743, B318, A5314, B1408, A7739, B173, B4732, B5662, A5758, B5032,
B4693, B3931, B4071, B8217, A6723, B1839, A7882, A9933, A6881, A4038,
B4761, B2526, B4275, B6587, A4558, A2969, B2589, B5440, B444, B6989,
A8940, A3447, B7533, B5631, A9561, B5418, B1506, A5919, B5164, B1095,
A4336, A6712, B4493, B988, A8552, A5965, B1030, B3150, B5761, A8004,
A5281, A3509, B4330, B2325, B1493, A9522, A8415, A8680, A4836, B194,
A3878, B3745, B6922, B8178, A3953, A6382, A5672, B6344, A6888, B6361,
A6569, B3066, A6502, A6489, B3164, B7944, A3263, B6557, A7631, B7599,
A6562, A8261, A8905, A8037, B4819, B7469, B1212, A5632, B706, A5990,
B5177, B7783, B698, B71, A5071, A7211, A4043, B4353, B1067, B9258,
B5371, A4504, B4052, B4632, B2945, B2250, B5002, A7609, B3708, B5010,
A5175, B8792, B5823, B413, A8583, B8661, B93, B442, B551, A3759, B26,
B6643, A7775, B1898, B700, A5103, B5587, A8607, A4490, A3625, B1332,
A7527, B5669, B1848, B314, A3653, B7036, B4858, B4669, A4921, A4485,
B1873, A8850, A5435, B6457, B4933, B3062, B6149, A6823, A7295, B6021,
B3131, A9634, B4447, B3849, A6696, B2361, A7913, A9131, B6956, A4515,
A4551, B7996, A8340, B6491, A9246, A9598, B7041, B8445, B7606, A4867,
B6122, B5888, A5788, B2157, A9796, A4820, A4640, B6400, B502, B3679,
A6011, B7185, B5881, B5561, A6935, A6896, B4767, A5483, B7849, B2519,
A6748, B6598, B3943, B2812, B8943, A6065, B888, B2699, B2150, B2614,
B1656, A3851, B7728, B3442, B2370, B131, A3563, A8333, A9408, B1004,
A6819, B610, A6496, A8873, B7638, B8702, B6057, A7425, A8154, A8432,
B2698, B5232, A3153, B4988, A6434, A7730, A9548, B7007, B7257, B3319,
B6730, B8903, A4715, A3298, A9252, B4895, A9461, B6829, B8045, B8609,
B871, A4604, A3380, A8748, A2929, B8579, A9190, A3595, A8843, B6027,
A9953, B3080, A5252, B3623, A8710, B720, A3362, B4020, A8870, A9676,
B3386, B9215, B3452, A6293, B8280, A4574, A3747, B4242, A6121, B6988,
A7947, B4508, B3688, B3471, B7351, A9124, A9744, B5229, B5341, A7307,
B4059, A3740, B5708, A9322, A6529, B3280, A7862, A9022, A9393, A7500,
A8625, B8151, A7762, B6183, A8228, B464, A6635, A5213, B8507, A3125,
A6333, A5110, A4944, B7048, B6104, A3584, A9498, A6028, B4847, B2987,
B4381, B4155, A9509, A2872, B7206, A8019, A8518, A9835, A6327, A7513,
A6287, B1237, B2373, A7831, B2774, A4441, A4387, B2128, A9817, A8963,
B8110, A9349, B2057, A9711, B2920, B727, A6731, B2801, B2019, B8522,
B6612, A9663, A9946, B2006, B2575, B1027, B7409, A8997, B4396, B1957,
B1771, A8299, B1885, A5412, A8349, A6585, B7501, A5047, A3270, B9059,
B6592, B5907, B4921, B7172, B386, A4156, B3876, B1747, A6184, B7482,
B7812, A4721, B5692, A5532, B9223, B1328, A6799, B1060, B234, B1937,
B6947, A4870, A8161, B7141, A5140, A4684, B6633, A8462, A8487, B6827,
A7972, B76, A5899, A6572, A9485, A9385, A3356, A3001, A5808, B8888,
A6452, A4676, A4938, B5118, A7185, A8469, B6351, B8242, A4581, A8148,
A3288, B2462, B7201, A8569, A6668, B8996, B2301, B8642, A5794, B1029,
B3903, B3648, B6493, A3311, B4123, B515, B5157, B6201, A4313, A9306,
B3054, B512, A9459, A9925, A5361, B3627, B4489, B1757, B6211, A7144,
B2996, B1850, B1698, A8216, B5772, A3416, B1988, B7636, B8259, B7645,
A7436, A9518, A5430, B9140, A7480, A8229, B5466, B824, A6093, A9803,
A5799, B4843, A6615, A6962, B8415, B1420, B240, A5590, B4597, B7674,
B1058, B3599, B1995, B2323, B3210, A6792, B1564, B9126, B8210, A9092,
B619, B1914, A3316, A8095, A4621, B8074, A7704, B2763, A9391, B4928,
A9853, A5599, A5309, B3713, A4915, A3223, A4015, B4080, A8050, B5445,
B754, B7326, A5892, B2962, B1857, B8876, B7434, B8380, A3646, A7579,
A7387, A6289, A5771, A5240, B9000, B1418, B222, B3437, A5109, B2147,
B6326, A8231, A4226, B2797, A9617, B272, B2896, A9451, B2954, B7317,
A8210, A3291, A5908, A4876, A7780, B1612, B7929, A4631, B6016, B1397,
B7616, A9167, B5685, A5377, B7398, A4707, A8991, B298, B3838, B1053,
B9095, B1781, B921, B7731, A8676, B2476, A7421, A3922, B2201, B1458,
B2724, B2285, B6384, A9110, B586, A8307, B7310, A5563, B3534, A5174,
B8322, B1107, A6910, B7738, B765, B3186, B5856, B8250, B782, B3895,
B6191, B1722, B5412, A2894, B7410, A5901, B3975, B5638, B6630, B3885,
B2776, B626, A6362, B8773, A7164, A7085, B2193, A4540, A7198, A3072,
B5474, B7834, A7155, B3980, B6771, A7564, B1968, B7285, A5988, A9868,
B6609, B5332, A4192, B5536, B1517, A4023, A5827, A5391, A9115, B8789,
B3348, A3994, A9605, A5199, B6346, A6221, A4149, B6764, A5275, B1460,
B2135, B9083, B5029, B397, B3244, B8893, B2712, B2598, B7551, B7506,
A7380, A3102, A3085, A8646, B8623, B1287, B8828, B8620, A7572, B2569,
A7653, A9937, B8289, A7699, A9794, B260, B3327, B8233, B7517, A9930,
B399, A5609, B9217, B8030, A8006, B421, B3268, B5020, A6429, A9520,
B624, B6516, B4569, B1093, A9656, A7281, A7559, B5728, B4486, B1229,
B5034, B3335, A7636, B1849, A8493, A4176, B3420, B4324, B1690, B8830,
A6253, A8250, A8762, B772, B4543, B8269, A5547, B4785, A6466, B3863,
B3755, B2753, B2305, A6083, B3388, A5468, B1701, A3728, B279, A4854,
B4188, A8889, B4244, B1717, B6809, A9418, B834, B5009, B8855, A7851,
A6834, B3632, A8287, B3050, A3829, B5301, B945, B267, B1745, B1222,
B3096, A7100, A7552, B3498, B1650, B984, A6522, A9102, B7490, B4003,
B866, A2863, A3559, A6980, B7137, A6760, A2886, B287, B5151, B4511,
A8366, B2857, B9156, B7168, A9107, B8712, B7766, A7449, B3166, B1945,
B8346, B4210, A6721, A4775, B3667, B3433, B5550, B7863, B9304, A4262,
A4080, B5431, B5741, B5287, B1020, A4480, B283, A6911, A9185, A9097,
A9891, B792, A6599, A7334, B5214, A9060, B6081, B7563, B7371, B3809,
A3171, B6952, B4181, B3480, A8572, A5492, B103, B9048, B8704, B4013,
A6042, B4046, B5505, B4917, A7987, B3835, A4883, A7159, A9536, A5941,
B7316, A8977, B3642, A9582, B8668, B3710, B3261, A6395, B1618, A8057,
A8542, A8396, A9441, B3672, A8724, B5091, A9644, B9186, B6520, A8545,
A7789, B5896, B7695, A4723, A4785, A7490, B2428, B6796, A6291, B1177,
B639, B2686, A9262, A5302, B2692, B4029, B1868, B5641, B8823, A3685,
A8302, A7208, B8192, A4573, A9363, A4638, B595, A7800, B5429, A3798,
B4856, A3877, B4677, A5263, B4378, B7112, B4472, A7132, B6421, A8206,
B6045, B9041, A8943, A3611, A8698, B408, B8297, A4961, A6877, A7548,
B5754, A8168, B4728, A8478, B577, A4404, B3989, A9691, B1410, B8273,
B1159, B4310, A8319, B8562, A6236, B3810, A8970, B205, A4969, B3709,
B3408, A8060, B7852, A6519, B9107, A4256, B9171, A5559, B5997, B2535,
B9295, B978, A6359, A3327, B1543, B3584, B6566, B1268, A8186, B1872,
A8784, B4232, B7620, A4305, A6039, B7741, B5145, B5626, B2732, A8862,
B6873, A8377, B4203, A8919, B5947, B3761, B6697, B602, A6208, A3032,
B7134, B2550, B732, B4104, B2563, B9147, B1361, B142, B2837, A7038,
B7092, B6818, B53, B2502, B1861, A3051, B3937, B2555, B4179, B7417,
B7151, B1548, B2832, B3037, A6302, B6754, A6532, B675, B6210, A3665,
B3731, B1554, B246, A4832, B4197, B3491, B8332, A6462, B7269, B8677,
B2874, A8691, B7216, B3036, A9014, A3660, B1356, A8013, A3942, B7717,
B5352, B3999, A5503, B45, A9439, A7679, A4004, B2978, A3554, B4238,
A9914, A5130, A5128, A7323, A7662, A7745, B200, A9088, B2973, B7447,
B739, A5755, B6257, A8987, A9764, B5398, A9968, B3112, B902, A6265,
A5924, A4852, B4345, A9359, A5401, B3957, A5017, B5902, A6003, A3700,
A8665, B845, B1201, A9516, B3018, A9861, B1261, B3687, B3119, B3766,
B8928, B8921, A4360, B642, A4816, A3518, B4970, B7260, A8615, A6224,
B5946, A7803, B7575, B7244, A8980, B4373, B8245, A8209, B4797, B6842,
A4730, B5395, A6974, B7354, B162, A6322, B5273, B5992, B3856, B3616,
B4714, B8935, A8314, B8606, A9961, B3971, B9299, A5330, A3860, B1280,
B377, A9884, B5674, B4870, A8312, B1392, B2435, A3816, B3820, A9170,
B6909, A9732, B371, B9206, B1138, A4616, A3232, A7046, B3382, B546,
B1835, B6862, A6469, B7071, A8339, A4369, B8149, B7442, B5520, B1292,
B3826, B2795, B1188, A8577, A9204, A5143, A9872, A5440, A3367, B4997,
B7952, A4344, B1732, B536, A4713, A4645, B1619, B9021, A7799, B4707,
A6750, A8243, A4618, A7486, B6728, A9370, B3509, B2817, A3899, A5082,
B2623, A5621, B4822, B1576, A7626, A7922, A3534, B1776, B6091, B8290,
A7966, B2403, B353, A7325, A3964, A3733, B4143, B3564, B5967, B4563,
B5935, A4569, A8389, B3782, B5794, B7670, B8105, B6454, B3502, A3917,
B8127, B5565, B8065, A3949, A6414, A2931, A7298, A8090, B5725, B5329,
B8867, A9784, A5790, B5961, A7857, A7649, A3618, A7172, A4739, A5201,
B5926, A3526, A9317, A5333, A5243, B87, A4057, B1900, B8962, A8042,
A6215, A4755, B4747, B4478, B6137, A5408, B6389, B6062, A6032, A9075,
B2959, B8860, A7176, B8339, A4370, A7936, B3729, A8141, B4755, B2115,
B4162, A9558, A7076, A7752, A9040, A6998, B7010, B6973, B1625, B4217,
A7275, B2210, B1727, B118, B437, B7935, A6605, A3746, A7027, B432,
B8466, A4698, B8208, A7225, A6976, B3702, A6427, A4379, A3193, A9330,
A4977, A4073, A9704, A7373, B6262, B7932, A7511, A6770, B4775, A4228,
A6054, B9088, A7136, B2706, B5036, A5137, B1631, B4526, B5320, A8442,
A8924, B217, A5832, A6109, A3844, A6494, B6849, A7764, A7201, B7303,
A9065, B4711, B525, A4468, B3677, A8637, B122, A5481, B2099, A9382,
A7584, B2964, B1582, B567, B4954, B1954, A7260, B5601, B7581, B8236,
B4247, B7088, B1384, A8501, A4535, A3514, B4192, A6166, B1142, B1797,
B351, A7952, A8841, A7734, A7389, A8757, B2217, B8026, B4118, A4899,
A7343, B2207, A7680, B4615, A9770, A5679, B4667, B8100, A6564, A5952,
A3696, A7460, B6488, A5960, B9263, A9826, B6320, A4477, B4680, A8410,
A9714, A7814, B187, A2818, A7885, A8273, A3445, B8825, B6962, A6187,
A6931, A6785, A6802, B8941, B2038, B4619, B2437, B3548, B7916, B1117,
A3007, B2810, B2969, B6579, B4041, B2107, A6470, A3690, A5702, B2015,
A9625, A5974, B291, B4131, A8001, A7335, B3763, A9824, B1815, B6543,
B2876, B2213, A8194, B7145, B2241, A8974, A4513, B4460, B4091, B6017,
B7402, A8434, B7804, B9188, B3547, A7614, A5722, B6080, A4780, A6957,
A3091, B1596, A4999, B7019, B3204, B2757, B2049, B762, B8635, B490,
A7496, B5234, A6388, A3895, B4139, B1375, A7382, B7213, B2918, A5942,
A5666, A5668, A3184, A8882, B66, B1666, B3398, B7505, B8278, B1595,
A6133, A3550, B5519, A4492, A7464, B4986, B6332, B5107, B6102, A8528,
B4282, A8294, A3943, A9415, A3664, B2224, B1255, B8505, B4068, B1503,
A3164, B4451, B2537, B462, A4424, B5015, A9234, A9841, B2017, A3149,
A8729, B8392, A7830, B6412, A5935, B2137, B8568, A8864, B8112, B8213,
A6859, B8685, B6318, B8574, A7927, B2548, B2602, A7864, B6068, A7233,
A7949, B2084, B2514, A6714, B4166, B965, B3428, A8064, A2870, A5040,
B4300, B997, B2826, B5727, A4393, B2457, A9496, A6316, B5025, A7595,
B4962, B8794, B1925, B4945, B3278, B2363, A9801, A8516, A6331, A9420,
B2045, A5005, A8670, B7971, A9276, A7634, B1194, B3574, A9573, A2998,
B2608, B5924, B1629, B3048, B2611, A9427, B2238, B9115, A8789, B2187,
B1805, B2935, B8656, B2220, A7273, B5617, B831, A7556, B4586, A7906,
A2823, B5369, B8008, A6809, B4583, A2919, B4874, B851, B2911, A8025,
A9900, B5556, B1495, B6855, A5097, A9693, A4169, B2126, B6095, A7146,
B1943, A2953, A8638, A6684, B3302, B7614, B6741, B7478, B5298, A7940,
A7707, A5344, B6004, A5046, A3579, B8364, B1076, A4254, A3530, B9236,
B3552, A6926, A4521, B7476, A3020, B4173, B5654, B8742, A3576, B9074,
B4969, A6626, A2850, B4228, B3370, A9538, B2288, A6419, B6217, B5687,
B4675, A9791, B1783, A4148, B3870, A3711, B4731, B2067, B5951, B1823,
B2674, B7680, A6165, B6716, B9017, B4688, B8478, B3306, B2173, B1551,
A6623, B2010, A6368, A5612, B7734, B6905, B898, A5963, B4491, B5485,
A8929, A4324, B8206, A7217, B5055, A7001, B3887, B9054, B7842, A4063,
B1155, B651, B4407, A3116, B6085, B8843, B213, A3064, A4242, B3337,
A6655, B3901, B4087, B4628, B680, A6480, B3604, B2601, A3140, B4624,
B4434, B3899, B6433, B7025, A6950, B7773, A5878, B3793, B8375, A8855,
A6693, B332, B5886, B5569, A4666, A6239, A6232, B1100, A3191, B7021,
A9256, B7647, A8686, B43, B6355, A2907, B114, B1002, B4327, B995,
A4294, B6553, A6634, A6204, B3670, B257, A5647, A8146, A3793, B3527,
A4052, A9808, B3990, A3055, B6194, B9102, B5172, A7438, B4606, B6311,
A7257, A8002, B1827, B9136, A8113, B153, A2834, A5895, B7978, B6278,
B8532, A9774, B7604, B8160, B4738, B5180, B3948, A2831, A5051, B783,
A2950, B9031, B3412, A7314, B2669, B2483, B9007, A3773, A8163, B3395,
A3132, A3529, B7122, B7104, A6700, B8745, A9659, B8312, B3526, B477,
B3850, B912, B818, A6743, A8171, B6532, A9161, B2450, B2319, B1792,
B8048, B3355, A3425, B4634, B8199, A4518, B6124, A6654, B7270, A5740,
B1658, B5430, B7640, A7845, A4340, B3789, A6669, B1536, B2680, B8443,
A9406, B7381, B7548, A8484, A7525, A5373, A8628, A4060, B3060, B4429,
B6150, A3977, A6746, B7795, B8949, B1334, A6457, B1025, A3825, A6894,
A4946, B5524, A8819, A8765, B4201, B553, B6301, A4413, A3623, B2372,
B1449, B4484, A7454, A9941, A8605, B702, B7721, B4025, B8224, B692,
A8375, A4672, A3336, B7847, B6891, A7901, A9287, A6009, A9244, A4384,
B5818, A4822, A4757, B4940, B7043, B3941, B3237, A3468, B8520, B4621,
B3209, A8465, B4936, B9282, B1133, A5218, B3747, A4979, B6589, A9542,
B1481, B6427, A9242, A8342, A8627, A5336, A7427, B316, B5841, B6474,
A3390, A9851, A4439, A7686, B6838, B468, A3649, A9568, B8167, B7816,
B6622, A9064, B7009, A6825, A8331, B2152, B4391, A7876, B886, B9289,
B3563, A7732, A8910, B6329, B8865, B3814, B8832, A5508, A8764, B3195,
A5529, A5283, A4487, A4970, B5585, B7946, A3655, A3495, B7899, B2696,
B816, B1454, A2924, A8875, B5573, A8222, A9179, B5570, B7664, A7043,
B1523, A7376, B7586, B7608, A7000, B972, A6325, B1833, A6982, A9028,
A6666, A5654, B5964, B6804, B320, A3561, A4806, B5478, A4284, A3364,
B4765, B7375, B3503, B1959, A3781, B7154, A7515, A7305, B5068, B1346,
A6659, A3230, B4897, A3535, A6095, B1235, A5211, B1437, B1123, A4338,
B711, B4673, B7226, A8156, B305, B1753, A4553, B580, B5331, A8744,
B6614, A8579, B7208, A9264, A5705, A5540, B5227, A4768, A8800, B1677,
A6733, A4031, B8905, B589, B5511, B6459, B6781, A9395, B6287, B164,
A8961, A8746, A7081, B1009, A8073, A5259, B4398, B1992, B8336, B8134,
B472, B3790, A5568, A3272, A6590, A5516, B4845, A9674, A5459, A9979,
A5490, B1773, A3369, A4936, B2443, B5366, B8738, B9060, A8612, B4550,
A8010, B7838, A9448, B3614, A4285, A3955, B2384, B6224, B2508, A7507,
B107, A9608, B918, B4763, B9296, A8039, A9993, A5233, B8325, B7081,
A5912, B3026, A8413, B2927, B4279, B3513, B3698, B7590, A9155, A5985,
B5892, B8358, B4781, B4411, B7631, A4817, B4691, A9741, B5175, B3288,
B4756, B8722, A8810, A4011, B3027, A9146, B2998, B4861, B1427, B1588,
A8642, B1214, B78, A6645, A6282, A7107, A7014, B6398, B51, A7128,
B3082, A5522, B435, B8799, A8845, B4911, B6585, A5476, A7575, A6267,
A4928, B1389, A5160, A4045, A6940, A7607, A8791, B2076, B8768, A2890,
A6158, B7444, B7942, B415, B736, B6548, B7489, A3842, B5166, B8067,
A9195, A9398, B7467, A7998, B1315, B2339, B4332, B3020, A6702, B1184,
B2771, A3463, A2899, B520, B1045, B2755, B9302, B4515, B3890, A9295,
A5688, B7672, B7986, A8939, A9031, B1406, A9314, B41, A6949, B1738,
B6392, B6915, B8139, A9189, B3147, B7689, B1162, B527, A3481, B7247,
A4162, A4013, B2253, A3760, B2629, A8475, B704, B4979, B5442, A8880,
B3908, B3865, A6380, A5117, B1976, A5186, A4178, A4244, A6764, B8853,
B454, A6473, B4666, B1012, A6271, B1069, B1310, B840, B3223, B5671,
A8419, A3351, B3008, B3217, B270, A5857, B699, B5030, B749, A8554,
B3927, A6876, B5660, A5887, A5623, B4351, B2956, B175, B7905, B8382,
A4327, A7390, B4369, B3735, B3140, B4805, B1741, B2365, A5630, B6659,
B8342, B2845, B883, B3178, B7421, B9166, B33, A6198, B6924, A5316,
B2943, B2892, A4104, A7880, B3977, B3693, B3064, B5825, B9252, A7398,
A7884, A8174, A6812, A7713, A5999, A9133, A3992, A5350, B2618, A3542,
B3843, A3387, A9355, B3933, B5940, B7094, A5714, A9500, A8321, B4277,
B2252, A9327, B6501, B8958, B8490, B5105, B7366, A3089, B9081, B4541,
B7190, B5123, B3454, B3242, B2298, B8736, A8597, A9935, B101, B822,
A5820, A6131, A5150, B5894, B4918, B7715, A7153, A6138, B403, B5453,
B598, A3986, B2538, B8891, A6372, B3125, B5303, B8076, A3522, B2740,
B6464, A7853, A6779, A7150, B2905, A6460, A8540, B177, A5437, B8323,
B156, A8731, A9086, A3215, A7566, B2938, A4889, A7194, B2117, B8235,
B7666, B6376, A8264, B3090, B5636, B8430, B7994, B3212, B7179, A9525,
B3422, B774, B9195, B5007, A3189, B5289, B5984, A9090, B8907, A3882,
A5803, B1904, B1250, A9636, B2767, A6260, A8993, B4758, B6860, B7553,
B4285, A3714, A5179, A5028, A6284, B4787, A7782, B5027, B7255, B7283,
A7628, B8595, B1497, A9746, A9963, A5573, A6088, A4904, B137, B6820,
B6168, B9254, B1911, A8574, A3545, B8107, B4312, B1000, A4549, A7658,
A8398, A5829, B2881, B1715, A4246, B7880, B8043, A4115, A8952, A4482,
B1819, B7249, B1175, A7157, B4995, B6071, B1390, B8456, B7012, A9837,
A4082, B1086, A3103, A6539, A6464, B4048, A4686, A8252, B281, A4097,
A8285, B35, A5691, B3816, A7478, B7865, A3755, B6518, A9119, B8652,
B2527, A4746, B5918, A8204, B2375, B4001, A8044, B907, A3083, B3087,
A9858, B7170, B8666, A6814, A4741, B9149, A7134, A6201, A7492, B6607,
B1369, A7985, A6040, B6508, A7098, A5604, A5338, A9226, A4086, B4456,
B1736, A4691, A8300, B1893, B1399, B1788, B7565, B3704, A8316, A8562,
A8891, B1339, A8259, B4831, B8039, A7647, A9580, A7815, A8499, B2391,
B7343, B7116, B2641, A8592, B4319, A9646, B7312, B1616, A9534, B5116,
B215, B4011, A4350, A3063, B6688, A3919, B2855, A4783, B5262, A9991,
B5433, A8809, B8226, B9184, B790, A4554, A9203, B7161, A8059, B7814,
A8689, B1090, A6790, B6719, A9457, B8991, B1326, B1223, A3313, B5836,
A3279, B4854, A9641, A5897, A3457, B4923, B4259, B2159, A4489, B7253,
B8629, B1444, A3979, B1689, B406, A6797, B3874, B1981, A6554, B2321,
B7192, A7582, A3070, A8068, A3227, B8413, B1852, B1696, B1422, A6587,
B4608, A3358, B3105, A4705, A6579, A9073, B2478, A7489, B5041, B1395,
A5371, A7248, A5274, B2579, A9927, B1935, B1881, B6038, A6861, A8786,
B4794, B5848, A5557, A9489, B923, A9465, B8883, A5527, A7064, A7482,
A7970, B6495, B9009, A9989, A5997, B3485, B9098, A9069, A4656, B5158,
B1682, A4804, A6649, A5432, B3435, A5890, B8692, B1755, B6390, A5534,
B5386, A8464, B5192, B7522, B8282, B9093, A3418, B8686, A7979, A7206,
A8026, A8214, B617, B1038, A4917, B2023, B1552, B588, B2341, B5472,
A9480, B1859, B2722, B2351, A5597, B5224, B2637, B330, B504, B8771,
A4221, B3536, A7822, B4639, B9221, A8099, B1007, A2892, B3001, B5424,
A9096, B752, B5538, A9555, B8837, A4674, B1298, A8508, A5906, B6023,
B6773, B7076, B3773, A8899, B8874, A3221, B5488, B5293, A3325, B5161,
B9057, A4874, A3849, B9234, A8903, B2330, B9203, B5858, B2765, B5400,
A3058, A8093, A2967, A5566, B4776, B3496, B6525, B5694, B8328, A7674,
A7015, B5774, A7867, A9863, A2922, B7484, B5081, B950, A3552, A4546,
A8015, A5536, A3261, B5322, A4583, A7187, B2471, B5153, A3318, B3076,
B7240, A8328, A9527, B1230, B2149, A8047, B3804, B7779, A5265, A9148,
A5970, B1875, A4951, B6131, B5863, A7241, B8096, B780, A7272, B4339,
A6530, B4877, B6481, B1939, A5796, B5000, B3822, B1305, B3628, A8957,
B8000, B2089, A9353, B8951, B3631, B4573, A7196, B244, A5107, B3330,
B9154, B3296, B5748, B2778, B8062, A5066, B5522, A7024, B5786, A3862,
B451, B5130, A9702, A6320, A6582, A4623, A7409, A4402, A8779, B8125,
A6067, B1578, B378, A4213, A8912, A8712, A5442, A5095, B914, B6031,
B8018, B8306, B8147, B2781, B7334, B6387, A6752, A6259, B1245, A9357,
A3676, B1713, B5633, B8608, A6978, A5080, A7423, A7069, A6436, A5830,
A8867, A9194, B548, B3030, B2790, A9982, A7025, B4889, B8480, A9627,
B8541, B6442, A4732, B1778, B8436, B3691, B1519, A9672, A9341, B534,
A6836, B3824, B5221, A6152, B6138, A4182, B798, A5167, B1180, B2195,
B4054, A9874, A9413, A9544, A9041, B3982, B5971, B2700, B1476, A6425,
B89, A8774, A6996, B2718, B8982, A7178, B6624, A9846, A4146, B2411,
B373, B2894, B2404, A3800, B3384, A9896, A4837, B4362, B3777, B5075,
B6255, A7724, A5305, B2295, B8964, A9591, A4271, B2584, B4565, A8249,
B2708, A3395, A7327, B4497, B7380, A5203, A7291, B6665, A9228, B1055,
B2562, B2215, A6033, A3093, B3447, A8344, A5463, B4824, A4985, A9361,
B4039, B2031, A9136, A5293, B7930, A6252, A6149, A4347, B1467, A4260,
B3784, A9187, A4377, B3852, B3449, B5238, B5499, B6417, B7356, B4745,
B8129, A9475, A4711, B9131, B5212, B6467, B3312, B560, B4841, A4763,
A8129, A5145, B7301, A8444, B7907, B6456, A3744, A4532, B5507, A8188,
A8364, A2970, B2059, A4106, B1734, A4054, A6893, B8937, A3436, B4601,
B4307, B4146, A7589, B2497, B1909, A6350, A9051, A4823, A7174, B1809,
B3146, B8757, A3528, B3440, B8708, A7758, B1720, B9264, B4219, A8136,
B6938, A4218, A7078, B1674, B7139, A7750, A3810, B7078, B1630, B4576,
A4158, B1104, B6979, B9028, B8425, B3916, A7472, B6260, B7677, A8722,
A9919, B1956, B6690, A9347, B7960, B1817, A3616, B555, A7141, A7116,
B430, B6788, A7938, A5241, A8422, B569, B3015, B6748, A7612, B571,
A7891, B2279, B6743, B2734, B2888, A5875, B4032, B1370, B3582, B3329,
B4205, B3039, B2991, A8101, A9109, A2988, B8544, B3812, B6794, B8644,
B3298, B6756, A7794, B4985, B7829, B940, B5195, A9648, A8476, B4374,
A6933, A7968, B7622, B3597, B486, B6747, A8380, A8693, B6875, B8472,
A7162, B725, B7378, A9483, B7764, A8941, A3775, B8334, B2283, B255,
A9680, A4910, B4470, A4303, A7254, B4172, B6679, B7656, B3935, B5050,
B7708, A6955, B6382, B5850, B5603, A8972, B644, B6591, B3151, B1412,
B9167, A8831, B80, A2933, A4409, B6940, B2520, A4963, B5628, B3402,
A9815, B4459, B3463, B6811, A6512, B4902, B196, A5922, A4235, A2930,
B8721, A4643, B5074, A8108, B8344, B6564, B947, A8485, B6957, B5093,
B7539, B8898, A6400, B5407, B1528, B8266, B8032, B578, A2852, A6454,
B9173, B2418, B7449, A5403, B3252, B2651, B4195, A6100, B144, B1358,
B7950, A5969, A5200, A4026, B262, B5113, B7023, B220, A9016, A6248,
B5592, B986, B3320, B8804, A6759, A7534, A8400, B7436, A9437, B4102,
B1978, B2082, B2835, B2386, B3634, A3819, B2557, A9153, B1266, B3266,
A5972, B5672, B8675, B423, A3667, B202, B6446, A7801, B743, A6407,
A5929, B5143, A9302, B9248, B6215, B4501, A5228, B847, B3467, B2191,
A6307, B4023, B6291, A5753, A5230, A5021, B6699, B8930, B9271, B7387,
B810, B2975, A7356, A7667, A7984, A9905, A3159, A3206, A8635, A8667,
A9782, B900, B734, B8926, B3685, B8247, B3955, B1842, B5993, B5999,
B3346, B6179, A9579, A4636, B1208, A7747, A6360, A4204, B3665, B5540,
B6298, B7412, B5376, B2310, B1186, B3768, A3323, A5768, B4466, B5804,
B6269, B5530, A6005, B937, B4716, B2830, B7419, B4022, A6122, B2209,
A7825, B2652, A6704, B2367, B4810, A9154, A6406, B6162, A4459, B8041,
A4557, A9638, A9799, B671, A3489, B3206, B7745, A6059, A5115, B1173,
B4697, A7694, A5010, A4609, B4334, B4975, B5575, A5015, A3026, B4467,
B3138, A5225, A2876, B2506, A7392, B4558, B322, A4912, B1917, B5827,
A7350, B5610, A3195, A6506, B3541, B4959, B3946, B1317, B6160, B3098,
B8959, B5225, B4437, B3286, B1078, B5354, B4788, B3741, A6366, A4808,
A7303, A9376, B5815, A4028, B3006, B2891, A7105, A4592, B4815, A9147,
B970, A6297, B8645, A9956, B155, B2385, A7720, B5953, A6691, A8877,
A4452, B1043, B7452, A7727, B337, B4899, A9266, B974, A6551, A4047,
B4759, B2377, A8742, B5765, B5820, B6714, B7423, A5162, A9128, A5656,
A4411, B8204, B7457, A6304, A8179, A5936, B9023, A3813, B4089, B3711,
A8032, A4819, A7996, A7664, B8402, B2898, B209, A5931, A8556, A7690,
A9034, A9111, B136, B4718, A5415, A8585, B2864, A5855, A4205, A3852,
B2358, B3867, B4271, B7713, A7715, B8628, A7402, B6348, A5951, B4721,
A8921, A6305, A7517, B2671, B7602, B4664, B7202, B925, A4866, A9369,
B605, A4172, B6985, A5417, A3249, B2786, B8083, A9683, B2467, B2320,
A8684, A3854, A6720, A6947, A9565, B487, A2897, B5583, A9380, B2660,
B2254, A6515, B7003, A9160, B5197, A9470, A6885, A5061, A5184, B4807,
B2431, A6964, B3315, B6583, A8563, B3168, A7605, B5529, B3041, B5666,
A4634, A6945, A7532, B1152, B2585, B1008, B2168, B6152, A7138, B4471,
B3235, B5730, A8417, A5889, B6056, B4204, B2806, B2281, B8526, B802,
B1091, A4129, B2151, B2942, B2380, B2261, A8814, B668, A7766, A3762,
B3229, B428, A3779, B7374, B4842, B480, B2205, B1404, B957, B2773,
B1795, A9208, A6069, A4986, B1615, B7466, B6221, A8150, B4249, B6650,
A4110, B4016, B9305, B6577, A5560, A5638, B8619, A9848, A4571, A4839,
A9630, A6736, A4972, B3973, A7887, B1886, B6261, A7504, A5216, B5659,
B4384, A4681, B445, A9949, A3443, B9287, A9810, A5337, A3622, A8514,
B8728, A5628, B3845, B5364, B1048, B3834, A8370, A9526, A4382, A8603,
A6492, B367, A5458, B8538, A5260, A9907, A7523, B4212, B3045, B9265,
B880, B6145, B7224, B6653, B3848, B4890, B554, B7248, B5634, B8174,
B94, A3873, B4593, B8732, B4253, A9074, A8531, B2985, A4157, B716,
B4182, A8823, B917, A5394, A4625, A5070, B1971, A2920, B4393, B7585,
A7835, B8766, B1465, A8498, B6288, A2996, B3505, B7871, B8276, B2268,
A8078, B1439, B7044, A8491, A7103, B7983, A7457, B7568, A8382, B4853,
B8362, B68, A4539, B3192, A3783, A6373, B57, B4868, A6959, A3657,
A8799, B2407, B5591, A7041, A4282, B6171, B9161, B2711, B6228, A2836,
B3696, B7193, B3619, A7918, A8766, A7854, B1062, A8014, B2606, B1751,
B6608, B3656, A6290, A4381, B2568, A8158, B723, A4287, B8739, A8481,
B8388, A6155, B6375, B3419, B166, B629, B4269, B6625, B5966, A3254,
B4793, A2857, A8224, A3568, A9977, B7125, A6727, B6783, A3035, B8607,
A5473, B3675, B4427, A8580, B5719, A6458, A9138, A5696, B2120, B6233,
A8874, A7357, B9085, B1098, A5077, B8556, B799, A5821, B3301, A6283,
A9610, B7365, A3098, A9889, B470, B6465, A4879, B5874, A5762, B1672,
A5031, B476, A3452, A6611, A8644, A4447, A3455, A7239, B2925, B4549,
B7026, B2505, A6892, B3376, A3593, B5566, B4240, B9132, B7275, B3609,
B5334, B7083, A5614, A8098, A9396, B6396, A4437, B6281, B2096, B5689,
B3089, B6484, B6295, A2917, B3285, B8744, A4599, B3925, B5652, B8373,
A4500, B3516, B65, A9743, A8655, B8632, B2033, B3568, B4658, B4610,
B3651, A7061, B5425, A6050, B4999, B582, B8690, B6857, B4607, A7705,
B2012, B4061, B7686, B498, A4934, A4222, A7246, B4967, B8311, B3414,
B5323, A3818, A6970, A9970, A3906, A3346, A3487, B2676, B3161, A6854,
B5179, B2092, A4810, B24, B1191, A5249, A9010, A7279, A7080, B3321,
B7572, A7428, B39, B8069, A3515, B7102, A7590, A7474, A5266, B894,
A5767, B7485, A7126, A3840, A7366, B5053, B2723, B8215, A5839, B3601,
B3524, A6798, A2841, A3476, B4262, B3776, B496, B4984, B2627, A8884,
B1019, B4686, B8502, B1790, A7844, A2868, B3379, B2488, B1940, B180,
A3642, A2987, B1296, A4210, B2759, B6126, A4844, B6706, B1010, A4440,
B7473, B4175, A7117, B4432, B8260, B2069, B5830, B6943, A7600, B9213,
B829, B7844, B4263, B8511, A6338, A6141, B2635, B2485, B8137, A6624,
B6188, A6524, B2574, B760, A8756, A4545, B8741, A3285, A6685, A3338,
A8049, B9075, A8406, A8523, B3952, B683, A4577, B712, A8754, A3776,
A3117, A9193, B4363, B5170, B7649, A4241, A2833, A5845, B347, B4651,
B6550, A4668, A8121, A7453, B529, B1451, A9329, A4316, A6952, A2956,
B3182, A9492, A7824, B4321, A6930, B7642, B2746, B3351, B8271, A4509,
A9748, B4802, B2087, A8029, A4941, A9044, B7187, B3561, B4574, B9229,
A4840, A7189, B8046, B6358, A7054, B7784, A7859, A6656, B789, B881,
A8119, B7966, B1534, B4408, B197, B418, B2846, A5192, B2663, B7140,
B6530, A8166, B8103, A3236, A2861, B1144, A6717, B8193, B7806, B5742,
B3057, A4470, B4449, A7671, B412, B4082, B2646, A4426, B4096, B2166,
A9387, B2439, A3392, B7770, B5938, A4907, B5506, B128, A6846, A5605,
B561, A6644, B2105, B1161, B1372, A8715, A6536, A7697, A4653, B2454,
A9374, B3572, B2531, B5796, A7202, B3851, B7055, A4483, B6996, A6595,
A3008, A4996, B1140, B1198, B987, A9005, A9751, B2448, B189, A8196,
A4058, A6715, B3171, A3497, B4589, B4960, B8803, B4510, B6925, A3017,
A6920, A5865, B4284, A6548, A5958, A5528, B4913, B4114, A7383, B1502,
B5013, B3276, A3830, B2933, A9219, A9292, A6318, A6689, A6991, B4018,
B8165, B6113, B878, A2828, B297, A4887, B2917, A3647, A6909, B6848,
A7994, A9425, B340, B6778, B4617, A9822, A4932, B6154, B5602, A7215,
B6292, B6083, B7404, A9270, B7057, B1789, A7818, B1388, A5034, A5424,
B8463, A4219, A8275, B1813, B8394, B964, A2824, B2079, A3412, B2070,
B8796, A8857, A5341, A4778, A4373, B1073, A9806, B2227, B1636, B5837,
A3767, A3796, B1135, A7499, A3889, B2353, B1111, B2188, B7977, A8358,
A6783, A5100, A4510, B1580, B1628, B4108, B9034, B5258, A8976, A4523,
A9268, B8699, B1434, B8457, A6192, B2232, B7182, A4965, A3188, A3038,
A2960, A4479, B1226, B307, A5029, B4295, B1509, A6765, B4130, A9404,
B4191, A7656, A5008, A3097, B8974, A7736, B4540, B7765, B4494, A6087,
B4153, B6333, A5746, A7597, B4053, A3151, B630, B5979, A3129, A3120,
A3105, A9212, B8424, B8181, B8379, B1129, B8471, B1490, A9709, B4137,
B176, B2854, B7178, B3703, A9159, A5739, B7736, B3220, B7062, B9067,
A6188, A3170, B6980, A7268, B665, A4150, B2620, B6118, B5957, B7882,
A5713, A6385, B2798, B2058, A5966, A5673, A6191, A8351, A9232, A7978,
B960, A6835, B3248, B6573, A3721, B9052, A4025, B9240, B1342, B2824,
B6181, B3383, A2904, B3197, B1597, B440, A7039, B3073, A9462, A6021,
B9068, B6600, A9755, A6174, B1654, B2026, B161, A9843, A5096, B841,
A4276, B5021, B1518, A3586, A7345, B3893, B6193, A9414, A2882, B7503,
A7087, B8369, A4390, A5172, A8296, B9196, A8267, A6778, B4078, B2596,
B1089, B190, A6150, B2308, A4074, B3251, A7792, B5071, A3614, B3911,
A4407, A5920, B2441, B8546, A3794, A8145, A9880, B5356, B6792, A7666,
B591, B7786, A3689, B8754, B5995, B2512, B5543, B2337, B4700, B2132,
A3394, A3371, A7440, B7675, B1521, A8066, A6844, A5231, B646, B2551,
B3187, B8304, B5095, B4943, B5168, B6267, A3663, B3587, A6900, A7541,
B3059, B4643, B2886, A2853, B6562, A5405, A6417, A8369, A6105, A8833,
A7258, A3923, B3033, B2412, B6814, A3946, B2580, A4776, A7419, B4354,
B253, A5461, B7, A5295, B1740, B8851, B6511, A7756, A9918, B1271,
B4534, B4206, B8473, B5345, A8986, B1352, B4904, B1165, A8164, B7650,
A8989, B6420, B7555, A7226, A7768, B3461, B145, A7204, B1137, B8293,
B5623, A7623, B8108, B4055, B3032, B3580, A4719, A4077, A4163, B981,
B7654, A9724, B3483, A8788, B4347, B6178, A4981, B3232, A9695, B2968,
B1544, B8349, B941, B6775, B7074, A6381, A5602, A4699, A9609, A3400,
A7544, B1512, B1572, A3788, A3708, B6252, B913, B5141, A3161, B108,
A6269, A7022, B5839, B8183, B1706, A3385, B6448, B2110, A4565, B1200,
B5409, B5394, B5532, A5575, B7446, B8426, B5458, B6096, B6236, B6693,
B7613, A8428, A9780, A7444, B7910, B6575, A5778, A6979, B6878, B1483,
B5111, B2836, B3995, B3401, A5927, B3465, B6745, A8901, B3590, A7270,
A6485, B1550, A8918, A6763, A7807, A8694, A6526, A9734, B3682, A9338,
A9007, B9272, B6133, B6368, B7979, B4886, A6295, A8435, A7362, A5732,
B5915, A6257, B1206, B5460, A3807, B5209, B6049, B2784, A3354, A7338,
B7992, B805, A7877, B1657, B4882, B4377, A2808, B5508, A7381, B434,
A5765, B2689, A4217, B4258, B5387, B5326, B1365, B5240, B2248, A7741,
A4710, B4851, B9194, B1252, A3213, A3591, B5451, B12, A5689, B7962,
A8702, A3450, B5312, A8777, A7057, B2119, B8599, A9411, B3791, B1844,
A7610, B5852, A6851, A3730, A7640, B5527, A9084, B1265, B3923, B9119,
A5064, A4882, A6262, A6036, A9965, A4735, B4442, A6446, B8706, A8017,
B49, A8959, B4474, A7072, A3378, B1864, B5757, B5832, B7887, A6354,
A8054, B648, B3785, B2703, B1479, A3485, A7031, A8189, B4743, A9285,
B8924, B7155, A9141, A7320, B8900, B3445, B8409, A9660, A4278, B4509,
A4358, A6438, A3809, A9789, B2009, A8772, B1642, B7909, B6335, A3887,
B2265, A6127, B558, B5784, A8983, B3538, B8487, A8203, A6219, A9343,
B4778, A4274, B9096, B5696, B4527, B3123, B4982, A5178, A3864, A9911,
A3712, A7689, A7161, B562, A7407, A2810, B4148, B8672, B4424, B1804,
A8330, B4522, B1347, B5077, A8893, B1665, B6627, B7931, B4771, B1083,
A8733, B8481, A5069, A4375, A7221, A9621, A6098, A7833, B8939, B8146,
B6451, B6850, B8528, A7969, A9345, B3954, A9699, A6424, B1821, A4748,
A3644, B6724, B4193, B5922, B6720, A8348, A4117, A8781, A4467, B2791,
B6977, B4937, B3377, B1419, B5149, B6941, A7615, B4365, A8536, B5270,
B5083, B8534, A6886, A5645, B4503, B4925, B1017, A4534, A6939, B7835,
B1622, A3719, A9334, B1430, B6186, A6753, B6431, B7706, B6019, B1830,
B1646, A2889, A8134, B4402, A9079, A8440, B8355, A9473, A9497, A9902,
B6976, A7476, B813, B6425, B9139, B5898, B3706, A3158, A8318, A8420,
A4612, A3911, B5497, A8869, A6352, B1559, B9015, B8513, B7413, A3397,
B1429, A4671, B1284, B6086, A5147, B4317, B5750, B5200, A9299, A6816,
A4095, A3434, B4419, B3013, A4400, B905, B7384, B7510, B2257, B2002,
A9703, A8447, A9201, A8826, B6444, A9700, B3725, B8101, B6751, A9150,
B290, B309, A6490, B8011, A6250, B7547, A9089, B333, B3663, B1453,
B390, B6837, B7014, B5931, A9876, A3197, B5391, A7082, A8182, A3600,
A5872, B8543, A5306, A4306, B3595, A9857, B1984, A7193, A8565, B9200,
A6875, A5810, B3367, B1102, B7468, B6760, B8858, B6065, B6356, A9556,
A4322, B540, B1895, B828, B959, B1684, B8002, A5795, B7587, B5043,
B7251, B6549, A7908, B8588, A5877, A5595, B1324, A6431, B2884, A3359,
A3004, B5114, B3153, B5299, B5475, A6393, A4786, A8512, B72, A4769,
A9163, A7089, B897, A5896, A8954, B3430, A5104, A3448, B1243, B1888,
B6409, B7376, B284, B516, A6914, B5822, B9091, B5859, A3239, B1761,
A4239, B708, B83, A8803, B380, B2852, B5802, A2866, B4840, B7632,
B3079, A4124, B4736, B11, A3202, A5365, B819, A7567, B7810, B6509,
B751, A3321, B3879, B1571, B8498, B3354, B4454, A6915, B8932, B7111,
A4248, B8997, B5261, B3641, A9094, A4237, A4919, B776, A8811, A9309,
B8646, B7762, B7322, B4780, B8521, B5927, B6490, A9476, B862, B6616,
B382, A4107, A8404, B7289, B2594, B1930, A3192, A5995, B2993, B6449,
B8132, B9153, B3889, B8954, B3117, B3339, A5577, A5904, B2080, A8466,
A7644, A8836, A6589, A3984, B8802, B3880, B3264, A8483, A8996, B7862,
B1231, B5594, B1726, A4188, B3122, B2720, B264, B3630, B1854, B2829,
A2859, B653, B3979, A9792, A3319, A6071, B5903, B7308, B6377, B3072,
B3796, B3102, B8411, B3646, A4798, A3960, B837, A4151, B5893, B850,
B3992, B8070, A7576, A4703, B1786, A5543, B4952, A4019, A9972, B2343,
A3927, A4585, A3219, A6449, A8235, B657, B2473, A6456, A7982, A6984,
B1531, A9223, A9922, B3332, B2328, A7700, B5100, A3284, B1964, B7867,
B5191, B5762, B8034, B7830, A6863, A6699, B3473, B7437, B5422, A8326,
A5159, B4579, B7817, B6846, A3427, B5607, A5439, A4743, B1215, A9350,
A5538, B3966, B8966, B2317, A7931, B9122, B6906, B111, B4875, B3759,
B3477, A8595, A8678, B7735, B3802, B8597, A2974, B5189, B2768, B7748,
A8392, B1424, A5134, A5511, B4849, B2908, A8080, A3679, A3723, A8106,
A9984, B1035, A7003, B8142, A5694, A5272, B5494, A4805, B8785, B2143,
A7096, B16, A5667, B1307, A8305, A3741, B4435, B6687, B5305, B7566,
A5447, B32, A2935, A5819, A7784, B2716, A7151, B6647, B453, B4826,
B7579, A3256, B8435, A9175, B5402, A6364, B2893, B4670, B7663, A8031,
B506, B8919, B1603, B533, A8254, A6584, A4144, B1360, B6606, B1006,
B7118, A9058, B8909, B857, B5783, A2819, A8219, B2456, B8896, B952,
B6886, A9596, B1910, A7928, A8451, B4125, A4900, A5496, B2393, A8560,
A6661, A3908, B9039, A3684, B1474, B5467, A3266, B5006, B4292, B4630,
B6831, A5276, A8549, A7067, A3752, A6024, A7094, B2549, A8504, A9126,
B1560, A7672, A3536, A8509, B1928, A9435, A5369, B2729, A8038, B1154,
B8776, A5196, B1300, A6796, B3637, B6524, A5823, B4006, B1606, B233,
B157, B7235, A7865, B409, B1877, B3805, B3293, B1377, B3456, B8576,
B7346, B3271, A5310, B3109, B1024, B3423, A8672, B4115, A4756, B8654,
A8937, B9227, B1301, B1694, A9586, A8643, B4033, A5395, B1708, A5588,
A5434, B1902, A7430, B275, B6822, B7175, B4120, A3555, B5619, B8872,
B9187, B2632, A9055, B634, A4084, B6892, B2292, A5918, B3530, A7632,
A4688, A4088, A7770, B8078, A9307, A7470, A4355, B3103, B8308, B615,
A3896, B7536, A9455, B7258, A9468, B613, B1278, A8590, A8456, B8329,
B9182, A9171, B6917, B793, B3653, B1414, A9643, B3918, B7499, B3426,
B5267, A8139, B2737, B8664, B5374, A9864, A5002, A3295, B8701, A3498,
B8755, B3817, A7560, B5435, A7898, B3241, A2923, A8660, B3543, B6540,
A5721, B226, B9250, B8536, A7309, B522, B4050, B7583, A9248, A6899,
A4388, A5214, A9221, B2848, B3068, B718, B358, B812, B4425, B5576,
B5247, A9321, B1402, A7837, B4382, B3317, A5801, A8324, B4512, B3475,
A9838, B4799, B5202, A3918, A9080, B6366, B3904, A5456, A4847, B911,
A4801, A5555, B6927, A3491, B4772, B7222, B1426, B4214, B6399, B3227,
B6147, A4578, B4817, B5551, B745, A8825, B312, A4189, B8195, B3841,
B920, A7379, B9003, A3360, B8554, A6637, A3525, B6655, A6349, B9291,
A7528, A6060, A7372, A6678, A6828, B2155, B3199, A7121, B7464, A5873,
B6402, A6937, B9285, A3785, A9947, A8076, A8379, B2775, A5526, B5707,
A6329, B5657, A3777, B3743, B4014, A3155, A7019, B5088, B8734, B1080,
B2401, A8152, B4415, A9207, B216, B5243, A8533, A3287, A5376, A9503,
B8726, A3847, B4892, B4483, B2055, B6025, B3860, B6861, A7916, B59,
B1448, A3597, B2090, A9578, B6069, A7484, A8601, B4866, A3122, B8395,
A2981, B7668, B5311, B3415, A4812, A4443, A9324, A4683, A8968, B6826,
A3123, B7046, A8240, B3043, B2616, B7895, B2983, A6856, A3582, B1845,
A4502, A3365, B1127, A8225, B9225, B7385, B6203, B2052, A9402, B7399,
B6256, A9546, B3998, B7425, B1189, B778, A4454, B7545, A5697, A8020,
A3659, A6299, A9490, B1096, A7369, B2432, A7521, A3135, A8908, A7459,
A2816, B3194, A5690, B4157, A5370, B2655, B3724, B1860, B6919, A8622,
A8768, A5094, B8524, A9745, B54, A6725, A7502, A7347, A6371, A8797,
B5063, B4524, B8301, B2035, A9944, A3620, B8558, A5027, B1837, A9975,
A8935, A6729, A4600, B4267, B4790, B3269, B4251, B584, A5759, A9713,
A9250, A3566, B360, B4076, B6895, A8846, B1996, A6107, B5223, A9929,
A6207, B2683, B6920, A9507, A2895, A8616, B3557, A5909, A3237, B5342,
A3018, A7617, A9186, B2422, A8263, A7562, A5086, A3212, B8630, B439,
B6164, A3892, B7090, A7603, A8096, A9685, B1800, B6581, B9127, B150,
B8400, A6890, B2275, B804, A9958, A9241, A2874, B4568, A8034, B5038,
A8220, A3138, A7317, B2425, B7703, B5829, B37, A3517, B4977, A5680,
A6504, A6274, B4973, B3610, A7719, B4, A8752, A6056, B3283, A5113,
B4812, B3023, B1336, A8956, B2951, B2286, A9882, B1124, A9310, B1663,
A7788, B1210, B769, B575, B4551, A9939, A6710, A3248, B1363, A7827,
A4051, A7351, B6054, A8914, B4656, B2915, A2999, B1549, B223, A3951,
B3213, A7133, B3673, A9191, B3136, A8558, B2808, B632, B4336, B2572,
B5684, A8794, B192, B4723, A3553, A4280, A5661, B3208, A9152, B4439,
B2200, A9831, B1711, B3004, B6618, A3947, A7301, A8749, B8135, B7450,
A6124, A2985, A9833, B8764, A6966, B4648, B7853, B2841, B7204, B2271,
B2673, B7941, B670, A3828, A9581, A7400, B1150, A6116, A6943, B8262,
A4174, A4041, B2947, A6264, B6248, A6026, B1311, B8447, B2744, A4334,
B2804, A7394, A9731, B8081, B677, B2543, B3129, B171, B3875, A8346,
B2387, A7710, B4768, B3869, A4864, A5312, A6927, B2788, B3410, B7796,
A7860, B5047, B2469, A7717, A7339, A6075, B4037, B5469, A7519, A8291,
A6517, B3083, A3856, B3245, A3645, A3465, A4119, B4273, B3144, A8177,
B6544, B4539, A8414, B933, B1967, B5664, A7018, B4695, B4030, A7975,
A8587, A8061, A5426, B8091, B6675, B422, A3940, B4342, B2940, A6821,
B2827, A8479, A4765, B6648, A9670, A4949, A3821, B481, B8209, B6954,
A5012, B2072, B659, B4445, A9431, B693, A4607, B2256, B2153, B6012,
A3958, A8132, B4804, B6806, A3627, A5132, B4554, B6559, B5199, B696,
A4127, B8407, B5798, B4094, B4135, B4996, A7620, B1511, B8983, B2040,
B3910, B3274, B9198, B7038, A3990, B5011, A3757, A3061, B4611, B7215,
B7053, A9632, B5596, A5956, B4297, B2164, B1220, B8491, A6160, B4086,
B2533, A7992, B4122, A2826, A6719, A7413, B1113, B6641, A4472, B6527,
B6156, B1477, B7912, B1626, A5863, B8688, A6487, A5730, B7975, A7627,
A3839, A3040, B2452, B2648, B9032, A7311, B2139, A6602, B6972, A9362,
B3173, A4856, B7080, A5607, A9082, B4112, A4056, B8390, A7805, A6546,
B4304, B6994, A9718, A7957, B8805, A4445, A5250, B7900, B6324, B2498,
B2315, B1504, B1227, A4356, B1146, A5636, B4119, B3570, B1259, B927,
B5137, A7588, A6337, A9722, B1949, A5986, B7183, A6085, A6194, A6176,
B992, B1118, B2263, B3578, A7310, B2355, A5193, B4084, A5938, B1374,
A9753, B6128, A5001, B6121, A4290, B1075, B295, A7896, A2965, B5230,
B2116, B8461, B5872, B494, B8639, B6676, A6922, B2234, B5276, B5701,
B1288, B8360, B5883, A4772, B846, A6781, B4580, B8986, A7902, B5791,
A5205, A7265, B4941, A9166, B1386, A9272, A3510, A8506, B4057, B449,
B1436, A6172, A4590, B7710, B9201, B8116, A3500, A9951, B4098, A7168,
B8841, B1540, B5211, B4045, A7654, B1379, A9819, A7599, B126, B8610,
A8438, B1867, B4224, B3246, B1139, A4179, B6198, A9444, A9766, A3832,
B7108, B6013, A4603, B4909, B4914, B5280, B962, A6292, A7468, B63,
B7981, B9065, A9210, B300, A3095, A2994, B6732, A8978, A4717, B4839,
A5711, A4994, B6887, B5959, B1064, A2925, B5126, B556, B2931, B163,
B5717, B4151, B2223, B6116, B5403, B6111, B8798, B8365, A6285, A4930,
B4545, B7367, B5919, B5955, A8717, B966, B1169, A5081, A8859, B949,
A4517, A9707, A9230, B2814, B1811, A8384, A9290, A4953, A8391, B2183,
A3003, A4967, B8590, A6767, A9665, B547, B7743, B2379, B2004, A7944,
B5272, A9603, B1041, A8277, A7332, A3588, B9106, B8971, A5744, A5675,
B8171, B5363, A7553, B7777, A9820, A9845, A5006, B1344, B7839, A5410,
B2172, A6597, A5760, B4641, B8509, B3589, A5182, B7919, B4645, B843,
B8367, B969, B5308, A8128, B8421, B7028, A6622, B3374, B6000, B3230,
B2179, B1947, B6283, A8897, B2062, B5769, A4005, B2510, B6231, A5409,
B8202, B9267, B474, B979, B7684, B3323, A5268, B3518, B4547, B8331,
A6902, A5504, A2843, B3984, A7237, B4420, B1499, A3716, B5501, B5866,
A5075, B4465, B2177, B1599, B8310, B7874, A6182, B3391, B2503, B5564,
A5149, B7938, B1532, A9785, A3168, A6169, B4710, A8191, B6078, B2244,
B199, A7368, A7703, B178, B7753, B2665, B6034, B363, B8834, A9036,
A9181, A6558, A2948, A5708, B8602, B7113, A8521, A4207, B9232, A7592,
B3521, A8125, A6617, A3876, A7277, B931, A5049, B2493, B3770, B4635,
B3968, B2487, A4435, B998, B7846, B1685, A8879, B4517, B6946, A7683,
A4224, B5147, B9246, A5774, A4588, B4260, A7754, B3091, A8431, A7113,
B2170, B5495, B2228, B836, B2094, B5738, B4684, B3617, B1108, B7480,
B7127, B5295, A8496, A3234, B4409, B6415, B7069, A7209, A8923, A8706,
A3691, B8500, A4842, B1281, B7471, A5701, B7135, B2278, A4829, B6880,
B369, B4161, A6568, A3068, B1644, A3577, A7286, B4532, B2408, A6687,
A4315, B4177, B97, A3119, A9524, A9778, A3148, B5051, B3753, A5053,
A7778, A8699, B1574, A9029, B2491, A8657, A3414, A6396, A5843, B4184,
A7873, A4542, B8180, A7842, A8720, A5836, B4388, B22, B1071, B8064,
B594, A4846, A3753, A3280, B991, A8112, A6658, B1293, A4524, B7189,
B6859, A7678, B7338, B7142, A6954, A3348, B4965, A5325, A6136, A5727,
A8362, A6680, B1566, A5247, A4575, A6143, B3258, B6708, A8408, A4136,
A9532, B5767, A8704, A4943, B4609, B5604, A8117, A6630, A9263, A9986,
B3358, B685, B2346, B1891, B8099, A5728, B787, A6883, A6847, A4895,
A7052, B3544, B2103, B1731, A2958, A2937, B1882, A5036, B1182, A9909,
B4869, B5698, A5643, A9615, A7405, A4641, B3019, A9117, A7959, B8506,
A7538, B168, A2939, B6478, A7861, A3015, B7357, B7577, B5503, A5565,
A9446, B977, B5544, B7515, A7028, B4931, A7915, A8916, A3619, B1242,
B374, B3769, A4614, A9239, A9654, B8347, A6356, A4186, B3680, B8140,
B4507, A7509, B6134, A6226, B1614, A8727, A4342, B3772, A4988, A3885,
A7029, B1085, A5471, A7115, A6156, A9697, B5456, A9024, B1557, A7033,
B3831, B3986, A8760, B641, B2565, B8592, B4422, B302, B738, A7921,
A3931, B5736, A7171, B1951, B8144, A6217, B2793, B3325, B4927, B1349,
A9372, A9677, B2211, B7128, A4877, B4163, B1527, B5358, A6129, A2839,
B7780, A8783, B600, A8933, A7251, B6839, B6974, B8604, A5067, B5759,
A5127, B9024, B5805, B6386, A8948, B2923, B6970, B6629, B6660, B6620,
B9292, B2630, B7415, A6697, B1217, B3882, A4536, A9551, B8810, B6722,
A9893, B3508, A8662, A5570, A5331, B2605, B5807, B2871, B85, A9067,
A2864, A8575, B3239, A9623, B3669, A4767, B4529, A3501, A8360, A8610,
B4679, B2141, A3433, B5256, A4771, A7871, A8538, A9008, A9197, B8902,
A8238, A6422, B510, A8040, A9466, A9261, A6499, B8862, A9122, A9282,
A6824, A5348, A9217, A6096, B3807, A8087, A8449, B6852, B1249, A4833,
B542, B564, B1282, A5297, B6597, B140, A5245, A4880, A5397, B6297,
A4418, A6030, B8467, B326, B2348, A9077, A9904, B636, A8828, B1015,
B392, A9530, B4741, B5721, B14, B7389, B7596, B1648, B7964, A9878,
A4753, B3219, B2739, A8282, B7280, A7294, A5102, A4737, A7950, B954,
B8869, B4570, B3921, A9688, A4251, A3874, B7937, A3054, A7074, A6241,
B1472, A8725, A3399, A7191, B9120, A9332, B1432, B5854, A3732, B3655,
A3173, B2705, B2014, B4149, B4142, B3828, A7495, B4349, B4702, B1394,
A8143, A4983, A7442, B3959, B2582, B8976, A2855, B7699, A5657, A9012,
B2578, B1749, B5070, B7652, B2878, A6238, B6314, B4270, B2414, B4906,
B1675, B6790, A3482, B6265, B2134, B8679, B721, B4035, B1514, A6415,
A7228, B3310, B3035, B1463, B5643, B983, A4070, B5097, A5852, B2819,
A7569, B2843, B3403, A5407, B4599, B2460, B7570, B7639, B663, A7180,
B231, B4749, B1492, A3037, B2230, B2839, B8561, B8058, A4079, A4090,
B5534, A9960, A6879, A3190, B3913, A3925, A3543, A4405, B2948, B1022,
B4371, A8860, B8752, A4122, A3763, B7634, A7668, A3049, B3787, A7772,
A6831, B7534, B6726, B3394, B3257, A8582, A6001, A4292, B2313, A7790,
A7417, B4027, B3406, A5207, B4782, B5625, A6037, B4340, B5555, A5925,
B4753, B9257, A5292, B6816, A8473, A4289, B4356, B4208, A9478, B2976,
B1204, A9433, B4222, B3141, A9645, B6250, B3493, B4256, B2834, A9736,
A8480, B8114, A8426, B748, A4215, B4358, A8436, B2971, B356, B7242,
B133, A3988, B4236, A9762, B2112, A4142, A7040, A5345, B1167, B7406,
A8367, A7411, B4198, B1546, B7611, B4958, A8245, B5891, B5800, B1768,
A7446, B100, B943, A7166, B1354, B6100, A9336, B3120, A9367, A9539,
A4796, A3682, B4884, B2553, A9157, A7109, B4725, A6374, B4106, B6560,
B339, A3402, B5913, A9652, A6057, A8835, B7557, A7743, B3114, A6249,
A5763, A4813, B2587, B7432, B5389, A9001, B6497, A5671, B3133, B868,
B5492, A6648, A8658, A7625, A7546, B2960, A8619, B251, A3303, A7378,
B4231, B2816, A8335, B4828, B3612, B2866, B7350, B8934, A8696, B2524,
B5187, B531, B8821, B7968, A9511, B6245, B5834, B2335, B6005, A3688,
B4880, B8338, B6595, A7364, B6259, B8340, B6184, B6051, A5879, B3360,
B8051, B3939, A9720, B807, B3189, B6908, A6404, A6758, B9104, A5018,
A7047, A5776, A3929, B3733, A7543, B1485, B4837, B8274, B6695, B455,
B3740, B2730, B3997, A9143, A3975, B345, A3725, A8008, A5737, A3204,
B9192, B6685, B8641, A9177, A4112, B7688, A4194, B8670, A7131, A8201,
B259, B3718, B5340, A9871, B3156, B7497, A7962, B4243, A9173, A5358,
A8104, A6528, A8544, A6398, A7099, B8176, B2427, B9216, B1692, A8303,
B483, A6420, B6969, B1303, A4651, A8309, B5065, B3639, B609, B3854,
A9687, A7219, A4195, B4469, B5163, B3052, B1263, B6460, B8697, A6044,
B6064, A9424, B8894, B7711, A7786, B3107, B6522, A7353, B6824, B6094,
B1033, A7385, B1667, A7850, A3383, B3184, B622, A9866, A4955, B3262,
A3250, A5449, A3677, A9594, B3489, A8570, A3257, A7230, B7348, A6300,
B5988, B9220, B508, B2901, B6864, B18, B4294, A5176, B1879, A4049,
A8895, B8612, A9667, A5812, B5307, B2050, B9158, A8083, A8256, B3458,
A2972, B7060, B5004, B1916, B277, B795, A3913, A2884, B4187, A7932,
A4872, B2398, B2659, A4567, A3226, B1847, A6073, B4992, B2202, A3631,
A6440, A6206, B8433, A4902, B4505, B8870, B2303, A9729, A3717, B8564,
A9348, A5825, A6868, A8453, A9100, A8981, B6950, B6753, A8547, A8356,
B2859, A4353, B7148, B701, B5920, B5437, A7722, A6818, A9998, A8394,
A8458, B7455, A8593, B2395, A6479, B5090, B3819, B8223, B5372, A8198,
B771, B2642, B7173, B6546, A6134, B3488, A4658, B1586, B9037, B1870,
A7531, A5642, B2761, A3823, B5723, B4127, B2290, B8231, A7819, B1989,
B224, A3087, A9053, A9584, A9612, B800, A3890, A3633, A3067, A7692,
B211, B8886, B7287, A8735, B1729, A7738, B2122, B2688, B1277, A5381,
A8567, B5781, A5634, B2822, B8917, A9388, B289, B1608, A8137, A7748,
A3651, A8289, A8268, A8632, A7989, B5154, B8994, B8130, A6604, B1171,
A8298, A5993, B3481, B2145, B6461, A3524, A7761, A8998, B8013, A9453,
A8062, A6917, B707, B3661, B1986, B207, A6570, B9180, A6391, B1056,
B8240, B5139, A7432, B74, A5797, A5506, B5045, B9005, A9045, B7237,
B3906, B3797, B5444, A7973, A5164, B500, A3420, B8238, A6118, B3115,
B7926, B324, B7314, B1921, A8517, B8228, B766, B519, A7124, B3624,
A9319, A5593, B239, A9554, B269, A4093, A9669, B3658, A5328, B2130,
A5278, A3329, A9920, B2882, B8999, B5291, B4735, A4648, B3291, A6091,
A8805, A4109, B1633, B8249, B3694, B826, B4315, B7873, A3024, A6968,
B4043, B2592, B6343, B1932, A3053, B4561, A6755, B5176, B6492, A8184,
A5494, B2326, B8877, B7512, B7158, B1897, B6910, B3877, A8906, B1416,
B5085, B2678, A7848, B236, B4322, B1624, B6960, B6529, B384, A8806,
A5579, B1763, A9105, B1724, B5337, A8838, A9017, B5121, A6534, B1233,
A3920, A2983, B1962, B3891, B5462, B3056, B1856, B1802, B6777, B1051,
A6451, B106, B4395, B4220, B5650, A7142, B4631, B6893, B9261, B7324,
B869, B2101, A7578, A5770, A4153, B856, B3751, B7600, B4864, A5363,
A7244, A7729, A9628, A7642, A6865, A4678, A4258, A8468, A5531, B1322,
B593, A3217, B3862, B3592, A9924, A5581, A4701, A4017, B607, B3644,
B5023, B3334, B8072, A7651, A3710, B5427, A3479, A8217, A9855, A9563,
A5894, B402, A8233, B9237, A5792, B7005, B5682, A8669, A4909, B8625,
B6393, A9916, B47, A3429, B7618, A8212, A6986, B7819, B5981, A9458,
A3312, B3361, B1994, B1661, A4745, A2963, B6213, B5690, B248, B756,
B5905, B8299, A7586, A5545, B8968, B5770, B7291, A7999, A5806, B5297,
A5261, B6513, B3439, B29, A6972, A5902, B2475, B7869, A4587, B8956,
B9151, B6379, A5300, B1758, B8626, B8281, B6325, B3110, A7199, B627,
A5779, A8401, A8232, A3459, B3113, A8522, B5292, A5772, B6299, A3297,
B2897, A4620, A8500, B1613, A7501, A9852, B4637, A4337, A3965, A7781,
B6828, A6919, A5546, B2796, B4564, B5917, B3535, A8169, B8961, A5692,
B3451, B587, A9862, B7619, B5408, A6413, B6391, A8992, B5968, B4325,
B6190, B2953, B1979, A3073, B2331, B2794, B5286, A5756, A8329, A8397,
B2764, A5108, B8200, A5384, B9157, B2148, B3645, B6219, B221, A5998,
A4675, A7820, B2284, B1291, B299, B1457, B243, B8774, A6988, B7739,
B1697, B3884, A8958, A4875, B9204, B7200, A8336, B755, B1721, B6060,
A3031, B530, A5900, B3837, B1106, A3551, B7615, B1780, A9442, B1934,
B8875, A7086, B2390, B1890, B3085, B5897, B5855, B5471, B8950, B8514,
B1960, B7349, B1589, A9168, B5411, B3357, A8808, A9528, B867, A9227,
A5399, B1874, B2576, B4499, B7673, B5588, A3521, A3731, A6531, B405,
B8256, B3956, A4720, B6948, B8621, A6918, B5753, B387, A8293, A6185,
B9224, A6394, A4632, B9008, A8541, B611, A3971, A6586, B8624, B5040,
A8069, B7576, B570, B5463, A9091, B1770, B4920, B6494, B518, A8896,
A7483, B278, A6578, A5793, B3281, A9678, B848, B3620, A3654, A3355,
A3082, B513, A8147, A9482, B7997, A5436, B8889, B6526, B1754, B4124,
B6352, B9190, A4939, B3443, B1982, A7253, A6433, B3434, B4488, B237,
B5174, A6791, B3771, A3745, A3713, B4250, B8603, B7798, B6808, B4766,
A8459, B3486, B5119, B7256, B1987, B416, A8486, A8739, B4598, A5809,
B8327, A6961, A9802, B1178, B4994, B8414, B7646, B601, B1756, B2118,
A4639, A5141, B503, B3635, A5362, A3320, A8162, A8761, B8333, B3053,
A3048, B5593, A8215, B2352, B8073, A6667, A2903, A6094, B3421, B823,
B2566, A6849, A5533, B7117, B8571, A3278, B7209, A4722, A7410, A5598,
A9410, A4081, B8866, B2995, B4331, A7222, A8505, B1028, B1176, B4481,
A7749, A7868, A9106, B3974, B7167, B4287, A9103, A9390, B214, B4311,
A8848, A7646, B9141, A8888, B230, B5432, B5773, B7718, B7372, B9001,
B2636, A6598, B9148, A7333, B2880, A3546, A5569, B4047, A4774, B4600,
A8251, B6082, A3630, A8258, A6421, B6711, B7233, B4514, A5166, B7325,
B4379, A4039, A7894, A9599, B77, A9859, B6364, B2904, B1584, B1211,
A8546, A6041, A9689, A3493, B6921, A8591, B565, A5007, A3720, B5934,
B4571, A9535, A8135, A7158, A9981, B5491, A4784, A5940, B5213, B8705,
B5080, B6015, B5502, B7523, B6631, A5564, B4916, A9474, B8916, A6200,
B7498, B7698, A7300, A9647, B7864, A6842, B1946, A3002, A7140, A7135,
A6256, A8663, B3260, A5378, B6951, B5639, B7315, B5390, A7170, B8758,
B5001, B549, B9049, A6222, A7416, A3792, B8687, B1938, A8056, A9869,
B5104, B6270, A7240, B9185, B1359, B2075, B1286, A3088, B2820, A9118,
B1084, A5989, A6591, B7342, B5640, A7563, A5802, B172, A9606, A7154,
B4519, B8990, A9422, B7507, B2381, A3910, A7698, B9218, B7550, B5787,
B6463, A8308, B109, B228, B2752, B8036, B4129, A7652, A8732, B3681,
B7333, B8232, B8225, A3264, B5439, B3201, B3813, B6212, A9938, A4690,
B1709, A7639, A3229, B7217, B2304, A6660, B1092, B8566, A9450, A3569,
B3100, B2296, A7101, B9099, B273, A3350, A7551, A4272, B4189, A5153,
B8431, A6209, B7238, B2766, A8109, B4784, B266, A9592, A7092, A7663,
B1702, B4760, A4914, B5972, B3224, A3101, B3417, A4191, B5300, A4831,
B1744, B8856, B8658, B5537, A3756, B5031, A8787, A9417, A6463, A9738,
B8955, B3721, B4326, A5294, A8614, B4901, A8982, B5925, B1601, A3052,
B149, A7326, A5859, A3941, A8863, B5353, B7091, B1364, B424, B6664,
B3732, B1120, A4416, A5299, B8345, B4211, A9237, B2831, B6381, B4754,
A7804, B3038, A5120, B4134, A7324, B5998, B6279, B731, B8440, B3991,
B4463, A9449, B203, A5131, A9183, B52, A8690, B6786, B2198, B5724,
B4038, B4971, A9303, B676, A3300, B3798, A5466, B2194, A8208, B4230,
A9087, A9358, A8675, B9150, A9432, B8788, B7418, B8922, B903, B1922,
B3297, B7750, B1609, B7448, A5301, B2556, A5400, B8080, B3686, A8568,
B7388, A6266, A5016, B3765, B6424, A7988, A8723, A7744, B5675, A7676,
B2972, B3915, B1553, B3938, A9513, A9967, A5641, A9765, B908, B5948,
B2246, A9733, A4815, A4568, A7207, B2599, B6218, B4031, B5060, B1639,
B1908, B6797, B3405, A3866, B6810, B773, A9885, B400, A9649, B8824,
B2687, B6749, B6784, A8913, B6567, B7245, A3245, B3343, A7354, B5803,
A4368, A9705, A6975, A3668, B1052, A4147, A8944, B8207, B4729, B3143,
A7182, B1468, A7797, B638, B3400, B7411, B1808, B3326, B4194, B2656,
A3179, B8399, A4078, A2807, B7851, B3666, B1039, A5084, B147, B1475,
B4370, A4304, A2989, B3585, B4739, B4239, B9172, B1417, B8272, B1915,
B4103, B2875, A8130, A9906, B6030, B5627, A4968, A4403, B1246, B1269,
B2534, B3873, A7773, B5073, A9890, B3253, B1733, B3336, B1158, B4233,
B6092, A5495, B2410, A8477, B946, B6048, B2417, B8191, B650, A3419,
B8563, B5490, B3716, B4836, A9897, B922, B6841, B3981, B6037, B452,
B759, B8969, B4344, B1669, A3845, B2958, A6997, A9066, A6455, A5334,
B8676, A4114, B6819, A9316, A2932, B5092, A7479, B3808, A5968, A5244,
B3267, B6696, B3438, A9360, B5328, A3939, B2707, B3501, A7535, A6004,
B3170, A2984, B8066, B8439, B524, A4346, A3612, B1276, B8106, B431,
B4496, A8443, B4746, A4754, B796, B6429, A5308, A7681, A4685, A6860,
A4708, A8140, A8091, A6216, B1539, B6284, A9550, A7753, A9543, B8126,
A7177, A3224, B8291, A9467, B2693, B5120, A4183, A7435, B3737, B4308,
A3765, A7137, A3527, A3194, B2212, A4736, B6937, B3078, B1355, B5541,
B5397, A8043, B1673, B288, B4302, A9331, A4615, B3139, A8022, B5049,
A4378, A6428, A5138, B3243, B115, B1818, B394, A4747, B8525, B4774,
A6053, A3799, A2885, A7173, B5870, B1209, B4750, A9915, B44, A7937,
B8993, B7306, B3781, A7009, A5398, B7934, A7200, B3654, A5262, B1187,
B5268, A4617, B86, B3853, A7374, A5659, A9371, A4731, B4145, B7072,
A7190, B7353, B1953, A5065, A7904, A9188, B1522, A8966, A3678, A6973,
A7549, B6789, A8386, B7377, B2434, B9089, B121, B6316, B3126, B1869,
B3362, B4144, A5622, A3431, B5454, B81, A4886, B3470, B7121, A8242,
B6871, B7564, B5135, B5523, A9686, A8218, A5876, B8465, A9873, A7849,
B484, B566, B3012, B4888, A3817, A8110, A8770, A4121, B1577, A9205,
A5448, B1679, B1181, B2818, A7629, A8185, B4821, B4704, A7487, A4345,
B1775, A5699, B9284, B61, A5209, B9298, A7297, B6755, A7045, A5142,
B2051, A3368, B2715, B6254, B3565, A4878, A3734, A9614, B9108, B1858,
A8775, B9191, B4178, A8425, A4255, A5572, B1542, B3159, A3983, B3832,
A3531, A5591, B4678, A7965, B5983, B5693, A7923, A4646, B3825, A5441,
A5681, B1764, A3883, A3861, B3183, B4414, A9059, B7542, B2622, A9690,
B4171, A9257, B1494, A3065, A8403, A3748, A5076, B1130, B8163, B1680,
B5702, B3567, A8388, B2624, B4406, B5237, B2225, B6414, A5037, B3750,
A6233, B3950, A6347, A3915, B8636, A7995, B2919, B368, A4665, B5484,
B8015, B6036, B2136, B5133, B2540, B9269, B40, B6328, A6858, B2061,
B3528, B9018, B1461, B1114, A8527, A7122, A6713, A6923, A7948, A3124,
A8730, B5880, A8651, B91, B8494, A7594, B884, B3396, B2186, B4689,
A8170, A8116, B9135, A8769, A9169, B8406, B6896, A3056, A7035, A7276,
A9139, A6074, B8009, B714, B7037, B8657, B6123, B1828, B3928, B8531,
A3231, A6934, A8515, A6653, B3371, A4419, B5062, A5726, A3422, B2182,
B96, B2825, A5833, B8835, B6554, B4662, A3480, B2619, A2908, B7115,
B9030, B7107, A8946, B705, A3575, B4603, A2992, B4791, A7050, B4806,
B7751, A7701, A9662, A4433, B4490, A6055, B9235, B4629, A7997, A6627,
B7011, A9491, A9019, B7479, A6620, B7681, B5255, B5620, A5048, B6830,
B20, B3364, A7066, A8740, B5768, B7304, A8085, B6146, B4591, A5800,
A3610, B1568, B9070, B5274, A4006, B4713, A7870, A9294, A5238, B6182,
A3893, A2961, A9783, B4625, A4920, B4871, A6646, B5339, A7242, B681,
A5045, A8124, B6097, B362, B4227, A9537, A5343, B8098, B1944, B36,
A6164, B3871, A5834, B2176, B8840, B4368, B1824, A3281, B8475, B1687,
A7964, A8003, A2990, B3962, B537, B7808, B2518, A9777, B8371, B1766,
B184, B3309, A9773, A5327, B6729, B2162, A9988, A5962, A4929, B6001,
B5233, B2037, A5180, A8878, A7497, B6310, B3305, A3981, B1525, B7266,
B7022, B6854, B5887, B1649, B7774, A6690, B3546, B8936, B2494, A9162,
A5428, A3564, A2915, A8071, A3113, B3551, B5814, A7216, B3607, B3898,
A3909, A9600, B1438, B6897, A7467, A2928, A3511, B8807, B8265, B2517,
B4088, B4727, B1594, B3254, B2468, B643, A8470, A8269, A6521, B4674,
B994, B6411, A4449, B5960, A6020, A4020, A4352, B1001, B182, A4995,
B8082, B2359, A7869, A6330, B328, B2027, B2654, B4063, B1254, B4167,
A5411, B4681, B4655, B4834, A9757, A3520, A6533, B8504, B154, B2644,
A6132, B3762, B2240, B4948, B6674, A7907, A5129, B8422, B6545, B2603,
A9727, A4848, A3185, B1197, B4980, B9116, B304, B2333, A8648, B968,
A6788, B4633, B929, B5018, A7863, B1487, B2609, A4512, B1816, B662,
A6488, B8313, B7210, B2685, B6981, A5868, B8470, A3252, B2237, A4394,
A7776, A3466, B7016, B7667, B5598, A4809, B5278, B678, A3165, B5226,
B9230, B4990, A7846, A5932, A7990, B5459, B123, A5515, B2480, A2997,
B2912, A8589, B2169, B3215, B596, B5793, A4421, B6197, B5405, B1793,
A7536, A4974, A7583, A7955, A9037, A4601, B1906, B7915, A7264, B8695,
B2046, A4474, B8027, B5869, B2042, B5361, B7085, A6503, A5743, B2873,
B1470, B7052, B2858, B3175, B8079, B996, A3494, B5368, A8639, A8270,
B5379, B491, B703, B3577, B8791, B2218, A7934, B9262, B6640, B7433,
B1924, A3693, B7803, B2733, A7463, B7408, B1077, A2954, B9064, A4476,
A9829, B7761, A4469, A6197, A9769, B3341, A6561, A7811, B6485, B4733,
B832, B7144, B8363, A8630, A5118, B4092, B544, A4533, B2016, A5735,
B4699, A8821, B786, A7856, B7453, A3972, B8460, B5950, B8718, A5502,
B7801, B3158, A9275, A8931, B5203, A4491, B5144, A7110, B4387, B7273,
B2902, A3247, A7892, B1376, A6801, A7342, B1337, A5704, B256, B870,
B2098, A8257, B1500, B8759, A3092, B4074, B8987, B9294, A8707, B8397,
B669, A8664, B2324, A5111, A4012, B6914, B4647, A5955, B6499, B2251,
A6294, A7881, A8842, B6599, B3021, B1838, A5315, B8044, B6731, A9942,
B1031, B6029, B3932, B989, A6880, B4072, B6369, A7763, B1122, B6586,
A9506, B7999, B7742, A8551, A2893, A9934, B7701, B4487, B9303, A8647,
A6159, B3692, A4543, B6561, A3859, B4694, A6734, A5282, B5370, B6117,
A6254, A8751, A5060, B8499, B2597, B3707, B4051, B8177, B2750, A3446,
B7207, B1769, B7945, A5493, B6345, B6955, A9750, B195, A5631, B7320,
A7491, A9588, A2873, A7512, A3469, B2988, B2844, A8072, B6758, B2867,
B697, B5663, A4042, B9051, B8216, B319, A3954, B9259, A5977, A7395,
B7029, A9354, B6817, B2525, A6596, A9027, B2944, B6246, A8320, B7883,
B414, B5732, A9003, B1899, B7972, B6765, B7093, A5379, B3028, A3978,
B9058, B4412, B4862, A8683, A8175, A9996, B7160, B2123, A7573, B6120,
A7013, A4328, B1428, B8760, B6276, B4548, A5826, B2682, A6501, A3995,
A3361, B3065, B79, A7414, B3967, A2849, B8769, A8926, A4385, B8725,
B50, B2936, B3236, A8011, A3137, A9030, B8150, B6167, A9365, B5655,
B4956, A9158, B6656, B6682, A5678, B5181, B1313, A8247, B2374, A7618,
A8886, A4010, A4175, A7308, B1316, B3, A8463, A8626, B6632, A7108,
A5624, B4978, B1046, A9650, B104, A6268, B6515, B875, B2675, A3301,
B7488, B3864, B4963, A6928, B9063, A3347, B5518, B4811, A3460, B7949,
B7509, B741, B6593, B5244, A8510, B9125, B2981, A9196, B2446, B1975,
A7056, B139, A9569, B9163, B7831, B7671, B5210, B7293, A9834, B6713,
B1965, A5907, A4139, B5562, A5479, A8153, A3843, B6798, B2274, A7234,
B6992, A7282, A6481, B6225, B7902, B7875, B3512, B8068, B5165, B6028,
B1772, B5788, B1884, A9313, B2056, B6987, B3196, B4546, A9635, A6679,
A4835, B7352, B1013, B5670, B4848, A7874, B2990, B2269, B6317, B461,
B625, B6331, A8051, B8904, A6855, B9128, B1735, B4245, A9945, A4442,
B3385, A8280, B8838, A5210, B7609, A6270, A8439, A3583, A3381, A4386,
B8578, A8227, A9562, A3121, B1066, B7472, A5212, B5849, B2921, A8871,
A6636, A6326, B3127, A9289, B1228, A3596, B8211, A6724, A8737, A9326,
B9283, B7359, A6027, B2127, B7530, B7598, A8058, B6458, B5263, B4156,
A8816, B3746, A8260, B6230, A5251, B1238, A6811, B1247, B429, B1168,
A4103, B9094, B4352, B5766, B1240, B3844, B4079, B67, B764, B1958,
A7006, A9675, B4894, A8018, B2777, A4505, A3826, A9323, B7047, B2018,
B4012, A8964, A3503, A3259, B4276, B2392, B7392, B7049, B1061, B354,
A4714, B6611, A8399, B5824, A9952, B8660, B6300, A7956, A4550, B4555,
A9574, B8569, A5861, A8193, A3023, B1798, A3331, A9280, B6397, A8089,
B2371, B6202, B6500, B3163, B9026, A7731, B3093, B4857, A6183, B8198,
A9078, A7608, B6362, A9215, B8444, B2300, B6507, B457, A7424, B7813,
B690, B3061, A7506, B4026, B3700, B4910, A4456, B8735, B5553, B5586,
A7458, B4446, A4945, B1600, B315, A7296, A9247, B27, B441, A3136,
B2639, A6497, B2813, A9517, A6695, B7605, B2114, B2955, B219, A6895,
A6936, B6621, A9132, B1327, A8795, B7500, A3154, B2270, A4321, A4821,
A9795, A9407, B6556, A7526, B4987, A3624, A8334, B294, A8584, A6747,
B6408, B3944, A9804, B7637, B7644, B7006, B550, A6062, B6309, B3318,
B1583, B526, A8374, A8494, A5665, B6022, B2697, A8094, B5571, B887,
A6826, A8606, A4486, B447, B1997, B3441, A8284, B3622, B271, A4555,
A3386, B426, A8561, A3780, B2856, B410, B5676, A9392, B2389, A6593,
B7696, A8529, B2590, A4261, A5168, B3185, A6523, B8864, B7866, B7665,
B1037, B3815, A5603, A4116, B1473, B8873, A3222, A7816, B1411, B4313,
A7477, B1320, B3340, B5457, B34, A4481, B6939, B7390, B2294, A3548,
A4749, A7675, B1174, B102, B7435, B1565, B2528, B3714, B6698, B8455,
B7904, A7329, B4290, A8951, B261, B1068, B8234, B7928, A8830, A5567,
A5202, A4706, A6202, B8227, B7345, B3106, A5562, A5349, A4724, A9597,
A3722, B4040, A4083, A4547, A6538, B7169, A3292, B1285, B3917, B8653,
B6574, B6223, B7767, B3836, A4782, B7370, B1787, A5136, A4751, B2647,
B6772, A7156, B8038, B6290, B1026, B8667, A9061, B7311, B3075, B3976,
B8790, A4937, B3800, A9098, B7246, B7344, B7630, A5392, B1912, A7165,
A4087, B5434, B919, B5994, B6689, B5452, B5122, B879, B3855, B1087,
B2640, B2779, A3080, B1224, A3262, B1652, B2595, B404, B2311, A9399,
A6089, A9640, A3305, B3088, A7090, A9936, A4155, B8594, B860, B7985,
B620, B1840, A7637, B7516, B4844, B1520, B7079, A8311, A8598, B2741,
B7483, B4397, A6227, A3200, B3124, A9590, B9183, B8643, B1306, B8673,
B3830, B7878, A7809, B2997, B3295, B8324, A4022, A4582, B5302, B1331,
B8892, A9456, B7241, A3181, A8133, B3381, A4037, B4757, A3727, B3495,
B6995, B5785, A5279, A6281, A6130, A5359, B5008, B5695, A7152, B4706,
B5028, A5804, B3649, B833, A8507, B599, A8265, B5637, B2939, B7716,
B3689, B4286, B4542, B1929, B5985, B3626, B3756, B7552, A3314, A5280,
B8854, A8092, A8890, B9253, A9616, B1620, B1903, B4786, A9305, B2713,
A9999, A9747, B1496, B5970, B8703, A4655, B1362, B3031, B1325, A7195,
A8107, B7309, B3432, A6465, B4318, B9233, B865, B753, B8772, B3537,
B885, B1297, B247, A6754, A5144, A3643, B3988, A4220, A6981, A8327,
A6912, A4190, A2968, B7254, B1876, A9042, B6949, B6903, A6220, A9781,
B5487, A7197, B3499, B5539, A5777, B1678, A6665, B8075, A9850, A5558,
A4667, B467, A8994, A4873, B2895, A4673, B2024, B2470, A7821, B3002,
A9481, B1570, B505, B5169, A4777, A4950, B5749, A7212, A5438, A7097,
B896, B9137, B4147, A9378, B398, A9225, B8496, B3886, A3172, B3111,
A6789, A5106, B8952, B5857, B3603, A5769, A4096, B1782, B7318, A5754,
B2342, B3774, A7422, A3811, A5173, B5423, B5160, A7493, B3964, A7986,
A8677, B8995, A9419, B4338, A7289, A9352, B4602, A5500, B3009, B4002,
A9384, A3315, B3629, B8184, B2725, A4552, B4009, A7119, B6482, B5862,
B4878, B8931, A2862, B4690, B7815, B5102, A7725, A5537, A4351, B5333,
B3994, B4572, B4140, B8512, A8573, B6884, A5273, B3643, B590, B1396,
B235, A3456, B5330, A4212, B603, A3328, B5622, B1806, A8450, A5509,
A6555, A5372, B1695, B70, A4311, B8133, A9472, B241, A9049, B370,
A6029, B8412, B1892, B8884, B7191, A5828, A7053, B8095, B6496, B3347,
A7249, A5264, A3335, A4318, B4708, B389, A4884, B5042, B5159, A6571,
A4637, B8622, B3453, B4430, B9222, B7171, A8802, A3216, A8898, B9130,
A9284, A9140, A3000, B2479, A3269, B1443, A8695, A5898, A6363, B2691,
B2429, A6447, B5193, B3436, A7581, A8812, B8258, A3228, B8586, B5156,
B7995, A8213, A3299, A5535, B6475, B25, B8283, B1421, B6517, B1681,
A6588, B797, B5801, A9308, A7063, A6862, A8230, A5548, A7437, A5996,
B775, A9486, A7488, A8027, B1640, B3598, B572, A9477, B4922, A8763,
B5775, B2709, B514, B618, B1913, A3059, B9092, B7282, A4803, A6995,
A7205, A4905, B5150, B2214, B8031, B821, B5385, B1936, B1274, A8446,
B7906, B7136, B5936, A4268, B3783, B4479, B5740, A2869, B8085, B1054,
A6633, A8187, B1101, B7700, B6455, A9717, B141, A7175, A2887, B6263,
B1671, A5360, A9076, A5576, B2561, A7911, B784, A9135, A6034, A3743,
A8445, A7255, A9913, A6251, B3121, A2901, B4744, B1977, A4055, B8205,
A3808, B7119, A8904, A4738, B6303, B6468, A8365, A6031, A7448, A8852,
A6820, B8700, A7224, A7759, B7441, B438, B5755, B8128, A4348, B1791,
B3479, A6495, A9494, A8239, A4697, A8423, A7939, B1955, A8207, B1638,
B5504, B809, B4795, B915, A4376, A9052, A9585, B645, B3016, B7050,
B3739, B3821, A5242, B6978, B2259, A6351, A3437, A4341, B4577, A7471,
A9039, A7751, B396, B5531, B3010, A7355, A9116, B3720, B7933, B1841,
B8001, B5835, B4440, A4687, B4306, B9174, B568, A7290, A8313, A9346,
B3265, A6387, A8081, B379, A6321, B6930, B7252, B2780, B8148, B5991,
A9787, A9279, B1516, B254, B4676, A6833, A5475, B6388, A6435, B4855,
A3881, B7828, B42, B2192, B541, A6153, A7070, A8180, A9340, A6694,
A6751, B8305, B2612, A5304, A5063, B3701, B3936, B7335, A7179, A7925,
B376, A7408, A4253, B2862, A5443, A5098, A3675, B8437, B3289, B4730,
A4733, A8711, B8019, A9962, B8605, A5020, A5574, A3686, B8540, B2405,
B8827, A6925, B1834, B5632, B791, A4181, A7967, B7621, A9692, B985,
A9875, B9097, B2299, A7030, B5220, A6426, B7070, A7299, A9847, B5076,
B10, B2986, A4916, A3050, A3863, A2906, B8899, B1777, B8963, B1621,
A4619, B2735, B6623, B2030, A6101, B1718, A7665, A8709, A5648, B3823,
A4572, B8124, A9095, B1579, A4610, B9029, B1826, A9673, A7852, A8949,
B2838, B4566, A6301, A7765, B9, A5296, B936, A9895, B3730, B9300,
B2419, B3448, A3617, B1529, B2748, A4622, B579, A4361, B1963, B138,
A4027, B7538, B4235, B4717, B4929, B4024, A8865, B9123, B7959, A9515,
A9926, A3806, A5945, A6613, A3921, B5904, A9438, B2564, B2583, B4903,
B750, B6662, B7782, B5673, B5355, B6533, B88, B3313, B3993, A8012,
A9910, B3407, B2536, B5595, B2877, B2650, B2558, B1611, B6136, A7026,
A7596, A5014, A4072, B8927, B3017, B8600, A3033, B8709, B6216, A9430,
B8920, B673, A3205, A9085, B733, B9270, B5112, B4218, B3468, B901,
A5831, B5142, A9356, B6445, B6691, A8666, B4328, A2851, B2974, B1207,
A7322, A7930, B1202, B3767, A9229, B4974, A3701, B3279, A5905, B7180,
B2465, A7077, A5227, B8756, B6489, B4500, A7510, A6052, B4525, B7574,
B7277, B5726, B8157, B3684, B129, B227, B5923, B5321, B3664, B9249,
B4417, A6108, B8246, B5629, A7802, B1260, B4596, A8692, B4800, B5346,
A7746, A8721, A9760, B2521, B8296, B5396, B3328, B3484, A7795, B6746,
A8758, A7360, B4372, A7149, A9108, A7184, A8911, A6461, A8942, A8988,
B5194, B6268, A4401, B485, A8381, A3377, B335, B6422, B2889, A5303,
B7821, B6795, A9771, B8309, B4375, A4302, B8826, B726, B9168, A9681,
B4473, B1381, B3778, A8045, A5011, B3145, A9983, B1193, B6032, B2906,
B1350, B2044, B7655, B7159, B6678, B535, B8938, B3154, B4101, A4984,
B2666, B7707, B5058, A6513, A4712, B3338, A3370, B4737, B8545, B2196,
B349, A4145, A8550, B3583, A7971, A9814, B6441, B652, B6039, A3963,
B6874, B3983, A8253, B6565, B8720, B4458, A2934, B8343, A6956, B6812,
B6958, B4202, A4160, A9533, B5465, A3349, B6742, A5464, B2967, B3464,
A5923, B3811, A7866, A4962, A6358, B8267, B1195, A8279, A3183, A5943,
B5094, A8747, A3410, B5205, B2221, B3671, B6286, B2458, A8295, B113,
B1256, A9235, A8671, B2547, B1357, A5197, B5962, B1063, B2267, B3221,
A7926, A8383, A8950, B2515, B2928, B3397, A8971, B8674, A5402, B1267,
B8170, B2668, A7232, A9607, B6088, B6480, B3152, B459, A9025, A6006,
A4526, A7075, A3090, B7470, B7212, A9416, A6629, B7219, A4423, B3858,
A9840, B4653, B5117, B4065, B5560, B2500, A4391, B5016, A5445, B6067,
A6190, A4976, B2934, B5069, A8065, B6319, A4392, A8713, B1926, A7983,
B4946, B2064, A7635, A9301, A6323, A3513, B7271, B6090, B7059, B938,
A5934, B2085, B7018, B6289, B4216, B8168, B7970, A4911, B1537, B7504,
B4165, B3272, A7465, A3268, A5637, B5795, B5470, A7550, B2167, B8793,
B7837, B8809, B2451, A6993, A5423, B2610, B4930, A7774, A4460, A7557,
A2918, B4585, A5866, B6576, B69, B342, A8636, A6563, B6222, B1340,
B4117, B9114, B6843, A6167, A7613, A6471, A3907, B6115, B1887, B7805,
B4616, A8513, B352, A6786, A9812, A7261, A4781, B6926, B3356, A2830,
B5826, B7220, B2910, B4613, A7696, A7890, B6578, B5377, A6681, B8237,
B5952, B1383, B8357, B4077, B4582, B7580, B1143, A7344, A5984, B2206,
B6105, B7087, B6487, A6803, A5961, B956, B4110, A9827, A8840, A5703,
B6590, A7813, B864, B8454, B5600, B1079, B4008, A4326, A9797, B744,
A5482, B2000, B4049, A3253, A8502, A6186, B4301, B4953, A6199, A3894,
B7740, B7123, B3764, B4461, B8784, B5056, A7084, B6584, B8025, A9602,
B7917, A4788, B1116, B2216, B1378, B6961, A3134, A9499, A5975, A3698,
B7401, A8822, B6542, B7953, B2048, B4132, B3727, A4644, B2965, A9825,
B2860, A6566, A9624, A4998, B8634, B7146, A5004, A7858, B687, B2242,
B4649, B660, B5929, B6757, A7953, B4183, B2108, A7461, A8272, A4308,
B1814, B1455, B9189, B2811, B4891, A8000, B7149, B3299, A4933, A3695,
A9209, A3333, B5324, B6552, A8248, A6203, B7095, B4823, B6229, B3203,
A8883, B2482, A4295, B3909, B6347, B5235, A8172, B5106, B7961, B8391,
B7268, B5253, B5131, A9973, B8212, B7020, B2743, B5239, B8573, B3780,
B2489, B4860, B7877, B6983, A8653, B3757, B5173, B7520, A7328, A9809,
B817, B8161, B873, A9259, A5655, B4660, A8114, B4605, A6631, A4704,
A6749, A6103, B3690, A8854, A9541, A4519, B6466, B7278, B3180, B4536,
B6762, B5477, B1562, A6963, A2820, B1148, B8533, A9013, B9006, B3070,
A7037, A5885, B6125, A3879, B1132, B5885, B3525, A4922, B6158, B8295,
B98, B4538, B5196, B2032, A9790, B8378, B6354, B6312, B2306, B7369,
B7105, B2318, A9715, B212, B3429, A8353, B6890, A9048, A8641, B5568,
A6389, A7313, A5846, B1273, B6395, A3131, A3488, A3635, B8244, B7885,
A3750, B8061, A7942, B9281, B9073, B7477, B1704, A3558, B4873, A7147,
B4410, A3774, B6856, B4246, A6625, A4140, A5258, A8525, B3234, A5329,
B1822, B2029, B4229, B1796, B3902, A8024, B5207, B2022, A7473, A5724,
A5087, A4383, B7540, A6932, A5723, B890, A8036, A8700, A6340, B2430,
B2496, A7274, B3303, B3284, A6483, B4265, B6418, B4961, B839, B899,
B7420, B2661, A6977, A7735, B1784, A7008, A7451, B3540, B2289, B4160,
A5611, B8477, B9219, A8405, B8017, B3794, A9849, B6003, A3344, B4452,
A8155, B4623, A9164, A8520, B7733, B5686, B7772, B8844, B7475, B6434,
B2436, A7306, A4243, B2160, A9759, B3555, B5486, A7941, B7841, B4687,
A3470, B6990, B4627, B2600, B5609, A5043, B3605, A6761, B4281, B3365,
B3549, A5039, A3115, B2174, A6231, B6881, B2719, B2782, B763, B3553,
B7024, B859, A6018, B852, B3888, A3283, B5420, B4433, B4476, B292,
A6663, A4203, A8872, A3848, B7227, A6722, B9087, A6064, B7532, B1236,
A7375, B815, B973, B1832, B1617, B1973, B2573, A3962, B7519, B1489,
B4595, B460, B7729, B6195, A2835, B8381, A9315, A4605, B5572, A9560,
B1441, B64, A6324, A3199, B7089, B5718, B5265, A3656, B6058, B306,
A6022, B1737, B321, B7008, B282, A5450, B3007, B4896, A9243, B465,
A6467, B6024, A9775, B4544, A4507, A2995, B1295, B1752, A5513, B4764,
B2607, B3307, B3387, B9056, A4283, A3363, B5760, A7287, A9071, A9265,
A8801, B5082, A9328, A7630, B4399, B3615, A8571, A5217, B3132, A6383,
B2129, B3198, A3357, B8778, B4672, A5219, A5457, A5367, B7607, B6923,
B3504, A7044, B4180, B728, B1345, A4286, B3165, B3190, A6229, B9082,
B471, A8221, B8906, A5600, B5705, B8335, A5413, A7058, B1011, A4030,
B4520, B8633, B5510, B6613, A8620, B165, A6889, A7823, B2125, B4846,
B7124, B1851, A4488, A9405, A4971, A2941, A7733, A8195, A9134, B3095,
A8962, B8992, A3454, A3486, B691, A7712, A3453, A9576, A9887, A6008,
A3021, B3840, A3824, B8737, B6642, B7284, B7153, B7898, A8341, A4061,
A3629, A3496, B3562, A6671, B830, A5541, A4105, A8604, B1774, B92,
B7794, B3172, B3846, A5236, B3177, B3803, B4200, A3071, B7040, B4777,
A7524, B2362, A9286, B1480, B5817, B3942, A7455, B7042, B2869, A3293,
B5819, A8818, B6705, B3748, B5525, B4935, A9519, A9004, B1581, B1863,
B2077, A9740, A6010, A8688, B5840, A7900, A9488, B2802, A6369, A3126,
B6718, B7382, B3678, A6272, A5079, A9245, A6745, A9464, A4008, B9016,
A9063, B5847, A6776, B7603, B6588, A4493, B6321, B2957, A7016, A7875,
B581, A5870, B7186, A4458, A4414, A5856, A8286, B3411, B310, B9288,
B7549, A5284, A3127, B6151, B4010, B5584, B1919, A7687, B6302, B5963,
A6941, A4947, A8332, A6553, B8361, B552, A8530, B132, B4360, A7426,
A8492, B7720, A5335, A4170, A4044, B6428, A8372, B6200, A5626, B6651,
A2921, B8442, B31, B2444, B286, B3222, A4868, B9101, B7943, A3271,
B2695, A8052, A9123, B1128, B8042, A5787, B6805, A4548, A7883, A9501,
A6296, A8790, A9836, B8831, A7783, B1660, A8881, B4070, A5116, A4177,
B1163, A5185, B3218, B3866, A3782, A9277, A7336, A3028, B924, A3006,
B6916, B6237, B174, B5661, B331, B781, A6120, B5288, A7280, B3148,
B6680, A8418, A3462, A3352, A9954, B7947, B2542, B4090, A8173, A9749,
B9155, A8553, A6472, B882, A4245, A5741, A9145, B1742, B8523, B3926,
A7565, B667, B6367, A3444, A5991, B8270, B2239, B3063, B2477, A9113,
B4801, A3388, B1398, A8322, B317, A5498, B8970, B5630, B4692, A3993,
B6244, A6076, A4161, A4541, A4478, B3934, A5072, B1545, B6658, A5491,
A3976, B8111, A7397, B3049, B1999, B8662, A4740, A3944, A5317, A4339,
A2871, A9510, A8613, A9156, B3949, B1044, B1213, B4813, B5864, B8723,
B8957, A9940, B6148, B2165, B655, B1333, B2552, B4100, B7785, B7897,
A7660, A9994, B1405, B4241, A4935, A3850, B1318, B5124, B5895, B4516,
B4762, A5953, B5653, B2509, A7210, B1367, B5313, A7106, A5074, B5367,
A4818, A5687, B3575, B1942, A8681, B2677, B3287, A8844, A6813, B8093,
B3490, B3699, B8800, B3390, B1156, B6738, B1610, B6645, B2823, A8928,
B5930, A9447, B2420, B4485, B6672, B3025, B7589, B7848, B2770, B3000,
A5477, B8179, B4715, A2891, B5167, A5669, B6169, A9440, A8629, B9301,
B3497, B9214, B2007, A9020, A9129, B1655, B2376, B186, A9032, B8404,
B8767, A9567, A3562, B364, B5901, B436, B5178, A9637, B5668, B9061,
B6821, A8412, B1185, B5734, B3969, A3661, B5559, A3391, B8279, B6189,
B2383, A7993, A5911, A8793, B9165, B3514, B4333, A9932, A5161, A7912,
B7860, A4301, B7481, A8433, B2322, A7227, A6701, A5937, B1484, A3401,
A9436, A7601, A3707, B4019, B942, B8033, A4766, B1703, A9708, A7361,
A8474, B433, B5375, B6235, B7836, A5342, B6523, B5393, B1676, B4007,
A8429, A8780, B6907, A4359, A7143, B1547, B2001, A8656, B1513, A8576,
B8811, B820, A6756, B3953, A5248, B8897, B6877, B1290, B4350, B9042,
B6072, B8427, A9668, B1716, B2870, B4221, A9928, B592, A4247, A5971,
B8341, A9339, B8356, B863, A6482, A5298, B7443, B3331, B735, B198,
B8182, A7384, B4341, A5601, B4724, B4107, B5831, B456, B7705, B814,
A9779, B5110, A7577, B4495, A5967, B4034, A5146, B6385, B2530, B4457,
B930, B9181, B1205, A9006, B8307, A3379, B4141, B5140, A4980, A5903,
A3353, B7747, B2277, B3829, A9761, A7545, B4278, B9121, A4216, B6447,
B8933, B4234, A6139, A9735, B1961, B4257, B806, A8315, A9655, A9531,
B2559, A6403, B3736, B3366, B245, B7963, A7793, A9964, B5014, B3613,
A4075, A3393, B980, A2936, A8460, A8917, B6563, B6360, B7787, B4346,
B8925, B3322, B4701, A6994, A7808, A3326, B6258, A3729, B5996, B3581,
A3016, B8337, B6663, B1183, A7321, A9366, A3956, B5937, B8753, B3250,
B4912, B3912, B4887, A7186, B1251, A5921, B8348, B6959, B3014, B2932,
B5079, A7441, B420, A5928, B2440, A6632, B2523, B4829, B5344, B1464,
B8241, B7754, B308, B2461, A9881, A5766, A7330, A7514, B849, B3081,
A3795, A4314, B5096, A3421, B2413, B4905, A6000, A5462, A3267, B3985,
B3596, A8985, A6908, A6418, A8934, A5578, B7653, B521, A3945, A4862,
B3142, B2131, B8474, B1164, A7606, A8467, B1880, A3415, B2307, B3316,
A5101, A4143, B8547, A8441, A8452, A3162, B3462, A5232, A5822, A9375,
B7850, A4125, B1351, B6975, B5542, A8947, A3544, B143, B6942, A3683,
B3149, B8820, A9083, B7976, B4207, B6815, A6830, B119, A9479, B7281,
B8109, B9247, B4820, B2977, B5921, A6151, A8102, B6692, B5388, A9559,
A6525, A4187, B4081, A4252, B1563, A9694, B4364, A2888, B357, A4466,
B6187, B4401, B7302, A4374, B1573, A3599, B7013, A9273, B5148, B2588,
A9901, B9280, B4938, A7475, B7967, A8714, A8969, B4477, A5844, A5444,
B6450, A9335, A3396, A8421, A6240, A6230, A6339, B6721, A8611, A4602,
B758, A4159, A3384, B3071, A8535, B8777, A3294, B6322, B4924, A7377,
A5625, B7075, B2190, B7546, A8122, A5347, A9050, B9138, B5201, A9701,
A4611, A8373, A9344, B6130, A3432, A6353, A5646, A8046, B951, B6443,
B1645, B3188, B6744, B8529, B4808, B5498, A7079, B3919, A8448, B649,
B8960, A5404, A4881, B3792, A7878, B2887, A7622, B6079, A7688, A8866,
B5526, B4832, B2783, A7641, A9298, B8102, A6099, A7337, A9202, B5916,
B1558, B1471, A8181, A3928, B5756, A8832, A3435, A9583, B3662, A3198,
B2088, B528, B391, B2097, A9992, A6815, A6601, A6887, A6843, B1683,
A7740, A5811, A3987, A4202, A3484, B8707, B48, B8671, A3451, B4883,
B6380, B4423, A3930, B146, B1348, B372, B5357, A7127, A7539, A8778,
A4273, B5277, B7383, A9540, A5608, B4825, A9912, A4679, B6410, A4584,
A9026, B7518, B3857, A6355, B8303, B7358, B1843, A7757, B8488, A3841,
B2356, B8598, B4919, A6581, A7611, A4277, B3924, A9549, A3924, B2924,
B6294, B3466, A8902, B4852, B1831, B1023, B7103, A9813, A5556, B8408,
B1865, A6126, B8542, B2690, A5431, A3104, B5697, A7250, A7406, B8908,
A9788, A9626, A3865, B939, B1760, A9072, B1018, B82, B5404, B7156,
B3034, B280, A7032, A6437, B5078, B7573, B1779, A5507, A3787, A9342,
A7659, B1272, B1668, B2539, B2593, B6793, B4770, B9255, B4993, A4349,
A4259, B1641, B4983, A8773, B3446, A9661, A7370, B640, B8059, B8965,
B4528, A4152, A3961, B7307, A9429, A5580, B8885, B1853, A9886, B5436,
B3118, A7834, B3795, A8892, B5296, A4018, A5393, A4180, B3494, B5890,
A6795, A8599, A6560, B7755, B1232, A9114, A5973, A5910, A8079, A3751,
B838, B5821, B7633, B7901, B7908, B2760, B1785, A7319, A9015, A6516,
A6448, B3801, B2102, A6535, B9004, A6090, A4908, B2701, B9228, A8325,
B2344, B2144, B7077, B5980, A8526, B6876, A7288, B2472, B5101, A6552,
A5549, B388, B112, B3758, B1530, A3317, B5899, A9611, A3034, B2541,
B4876, B4578, A5271, A8736, B958, B210, A3225, A3214, B5222, B2567,
A8634, B5290, B1105, B3474, B3531, A5539, A4742, A9971, B105, B5608,
A7976, B7511, B8143, A9921, B1323, B3478, B2039, B4436, B6845, A3615,
B7678, B1931, B3482, A5499, B5325, B285, B517, B1894, B4594, A5994,
A3549, A9142, B827, B3833, B7110, B1983, A7271, B1393, A8009, A4111,
B7687, A5871, A6117, A3449, B1057, B73, B5851, B8859, A3523, B8587,
B5624, B3640, A8063, A9222, A3560, A6983, A7071, B8294, B3431, A9969,
A5380, B8012, A6102, A3974, A6439, A5582, A4094, A3324, B4696, A6913,
A8202, A8236, A4323, A4635, A3201, B1974, A5893, A5798, A3621, A8697,
B4316, B7704, A7909, A7163, A5594, B7225, A8804, B709, B5152, A7386,
B9090, A9553, B7541, B6093, B8203, B2992, A6392, B6063, B2710, B3353,
B2885, B381, B6763, B616, B2900, A7439, A5530, B507, A3634, A8030,
B2633, B8497, B574, A7960, B7811, B4783, B2111, B3657, A4624, B8094,
B3539, B383, B5271, B8131, B5084, B2961, A9589, A6237, A7708, B1423,
A2867, B4394, A7023, B5865, B8998, B5554, B2728, B777, B5260, B3424,
B4126, A5003, A8283, B3425, B7340, B6774, B1878, B5125, B7321, B263,
B6725, B7920, A5720, B3459, A5589, A8021, B4893, B5533, B7714, B2643,
B7951, B5616, B7458, B7234, A5469, A8255, B7347, A9894, B647, B3978,
B1803, A6769, B2999, A4652, A5366, B2138, A5204, B621, A4901, B6823,
A4670, B3892, B2399, A6308, B3270, B3455, B7567, B3636, B8655, A9575,
A3914, B8829, A8503, A8237, A3086, A3005, B906, A5151, B327, A9601,
B8077, B7288, B3104, B5044, A5639, B8871, B1664, A8205, B8302, B5115,
A4085, B1382, B1413, A8824, A5805, A4537, B3240, A8455, B7290, A9642,
A8953, B225, B4116, A4089, B9086, A3778, B2083, A7555, A9172, A9865,
A9180, B6477, B1901, B3292, B1759, B7993, B30, B7138, B1279, B6541,
B7319, B7818, B8577, B3542, B4361, A7570, B1216, A6315, A7899, B466,
B8665, B2247, A3220, B401, B719, B3345, B5421, B1172, B2769, B4291,
A9639, B8239, B1308, B2008, A6361, A3255, A5114, B6863, B4042, B5476,
A4790, A6399, A5561, A5135, A8596, B2297, A4196, A2973, A9471, A4309,
B2909, A5163, A5693, B6885, A8900, A8105, B1927, A4789, B8596, B1526,
A5357, B8003, B8852, A7095, A6225, B1693, B5264, A5514, B8434, B1005,
B5517, B4280, B3728, A7540, B5026, B7250, B1302, B17, B543, B2291,
B4671, A7785, A9176, B604, A7920, A8306, B4000, A6664, B7623, A9793,
A5195, A9093, B5455, B1714, A7721, B274, A4269, A6328, B8890, A8363,
A9950, A8053, A4918, B6018, B2394, A6070, B7176, B3719, B1623, B1725,
B3179, A8393, B1034, B5188, B252, B1941, B5005, A3260, A9454, B7554,
A7004, A6205, A4680, B5468, B1442, A7673, A3081, A3724, A7929, B2853,
A3074, A9595, A3897, B1257, B1309, A7093, B8696, B1368, B2890, A5270,
B6066, B4272, B4751, B7827, B1225, B8393, B2840, A3761, A5416, B573,
A6306, B3861, A7516, A8813, B7203, B2907, A8967, A3957, B6177, B8277,
B1605, A4293, B3868, A5318, B6349, A9682, A3853, B9103, B4720, A8378,
A8555, A8586, A5854, B2805, B3294, A6948, A9368, A4046, B4769, B7879,
B4138, B5906, B4450, B1042, B8627, B8765, B1126, A7661, B3042, B4185,
A5414, B4552, A3039, B1192, B3369, B3024, B5667, A8352, A9487, B5771,
B4792, B478, A5183, A3855, A3499, B6813, A6514, A4171, B6249, B1153,
B2255, B9169, B7150, B6644, A8416, A8938, B3779, A8847, A4865, B6963,
B2364, A2858, B6531, B8575, A6683, B6055, A8564, B2282, A8323, B2522,
A7714, A9523, B3972, B6677, B1807, B4698, A8097, A2822, A6946, A9959,
B8049, B3427, A7670, A7148, B2941, A7304, A6600, A9931, B6918, A9631,
B7940, A4654, A7767, A7399, A7977, A7533, A3424, B2208, B1604, A6703,
B2424, A8999, B9022, B2154, B4416, B2287, B3205, A7691, B2366, A8716,
B6883, A4913, B6740, B1099, B2653, A9529, B628, A4389, B5577, B7544,
A6123, B2772, A7826, B7451, B6365, A9151, B971, B2586, B3069, A9658,
A6677, A7695, B3116, A6967, B4557, A5215, B3697, B1918, A7391, A3163,
B1998, A2975, B6161, B3749, B4502, A7886, A9798, A5169, B9286, B2243,
B2749, A7002, A5761, B3282, A3650, B5731, B1036, B4021, A7017, B6163,
B5304, A6405, A5351, A4062, B2756, B348, B3963, B4976, B8403, B5046,
B3092, B3137, A5226, B2378, A9955, B9160, A6303, A9112, A9502, B8173,
B4789, B9055, A9320, B4213, B8113, A7836, A3556, B2293, B135, B8729,
A8033, A4451, B2421, A8687, B4335, B2679, A8973, B9038, B4816, A9192,
B5635, B5039, A9948, A6550, B7648, B334, B7276, A9990, B158, A9057,
A6023, A5930, B8040, B2571, A7104, B717, B2809, B4636, B6717, B3506,
A7042, A9888, B56, B1505, A8157, A6728, B5103, B5986, B1312, A6386,
A4380, A8226, B4058, B7355, B557, B8557, A6864, B694, B2388, A6958,
A3366, A5474, A7292, A5939, B3191, A7485, B1750, B167, A4053, B8410,
B2406, B4431, A8343, A5489, A8482, B5438, A6827, B7870, B1466, A6286,
A9199, B6170, A9566, B975, B4867, B6378, B6626, B5066, B710, A3567,
A6228, A9577, B3263, A4288, B5763, B8441, A8798, B4668, A9978, A3628,
B6234, B9279, A8385, B3389, B488, A6459, A6154, A4516, A5324, B7002,
B2507, A8223, A3822, B6103, B730, A2837, A6493, B2847, A9251, A3674,
B6280, B1535, A7102, B1651, A8621, A5780, B8863, A3950, A3658, B5965,
A3938, B1403, A9818, A6066, A7919, B8448, B1103, B6476, B656, B4428,
A6298, B5335, A7358, B3723, A8490, B932, A4948, B7368, A5512, A3998,
B8469, B8396, B3228, A4412, B311, A3330, A5480, A9856, B1244, B3167,
B7584, A9383, A4319, B6220, B3554, A6822, A8532, A6612, A4570, B583,
B350, A7604, B9084, A9267, A5627, B8631, A6670, A4973, B1889, B4075,
B746, A3041, B7465, A4506, A9742, A7331, A9240, A6891, A7645, B323,
B5828, B4305, B3097, B8942, B6153, B5574, B3174, B2041, A6951, A7403,
A6884, A8511, A4608, B8495, A9800, B7868, A3027, A8960, A4689, A4987,
B6582, A9174, A9839, A5052, B95, A9379, A2940, B3842, B4898, B5790,
A6367, B1972, B1739, A4325, B8839, B4560, A9666, B8539, A9671, B6928,
A9883, B425, A8178, A7726, B4592, B5054, A8371, B5089, B3940, B208,
A3872, B7373, B7601, B1119, B3046, B258, B8731, B6615, A4838, A8920,
A6735, A4750, A2986, B3847, B6652, A3812, B5704, A9062, A9224, A6592,
B4385, B4400, A9908, B2156, B4650, B8508, B5441, B5059, B8214, B3378,
A6965, B8535, B5838, A9278, B8458, B4159, A4843, B3515, B5362, B8973,
B6357, A8048, B7641, B2093, B8503, A3069, A5886, A7843, A9698, B2628,
A3784, A2832, B8740, A9271, A4952, B4264, A7160, B689, A3641, B8510,
A9823, B4223, A7598, A5789, B1387, A7839, B4174, A4544, B5171, B2484,
A7580, A5837, B7820, A5596, A4669, B2066, B761, B684, A4940, B9231,
A9269, A8743, B4803, A7505, A8028, A9293, B2025, B1508, A5044, A4576,
B3560, B4665, A3235, B1991, A4800, A7452, B2634, B4418, B8330, A3912,
B3859, A8165, B8092, B2863, B5259, A5747, B8201, B7414, B3181, B8172,
A4471, B3996, B6707, B1948, B3894, B4320, B4248, A3580, B7082, B417,
B2086, B4448, A8407, A6017, A3758, B3352, A7943, A5775, A6657, A3585,
B9266, A2955, B7778, A8144, B4095, A6341, A7365, B5605, B8693, B8194,
B8806, B3900, B5198, B5557, B3084, A7910, B8010, B4998, B497, B2702,
A6370, B5884, B2926, B475, B8819, B6432, A6168, B5426, B8376, B8,
A7346, A4448, B2662, B4968, A7256, A4520, B188, A5613, B4329, A8701,
B1134, A8654, A2916, A6051, A9200, A6852, B6483, B3573, A9811, A7238,
B674, B2163, B4622, A6744, B3392, A9258, A7049, B2034, A4978, B179,
A4501, A3157, B8743, B4060, B2916, B1065, A9182, A7181, B895, A6273,
B7486, B8166, B3602, A6193, B5688, B4879, A7991, A8734, B3947, B5048,
B768, B5958, A4130, B2950, B2011, B2354, B4390, B926, B7797, A7129,
B6127, A9807, A5033, A3477, B2338, B2229, B2754, A2860, A5085, A2898,
B4190, A5838, A5267, A4223, B1, B4254, A5987, A9403, B7612, B3608,
A9125, B1820, B7524, B6227, B559, A4964, A8885, A5032, B2266, B3775,
B4464, B2233, B3907, A6686, A3152, B1081, B4056, B7181, A8297, B4685,
B1341, A8266, A2840, A6565, B6070, B127, A9842, A5237, B3399, B62,
B631, A7285, B9069, B1088, B2226, B2617, A5700, A6766, B2140, A7903,
B948, B6334, B1491, A8856, B1258, A7737, A3096, A5660, B1283, B7984,
B2464, B4640, A9023, A9213, A9233, B8698, B5067, B5716, A2993, B4154,
A9445, A7879, A4206, B3047, B2799, B2222, B3005, B4482, A9786, A3594,
B4296, B3259, A5733, A4211, A3187, A8524, A6086, A3128, A9394, A5674,
B2800, B4067, A6484, B2966, B7422, B3130, B3249, B4062, A9712, A5712,
A3182, B8138, A4024, B5797, B2262, B666, B9290, B990, B5365, B1705,
B5136, A7951, B448, A9463, B961, B2529, B7911, A2902, B8479, A3831,
B3074, B7336, A4896, B9197, A8127, B6904, B6858, B4587, A9043, A4410,
B5208, B5241, A8067, A8745, B1447, B1452, B4575, B7177, B801, A3880,
B5072, A6777, B7502, A3697, A7269, B1199, B2621, B6253, A9604, B8989,
B120, B2171, A5171, B6180, B2204, B3827, B7746, B842, B1160, B169,
B1371, A6718, A6537, B2309, B7771, B8326, B2106, B3058, A7062, B3523,
A5944, B4588, B1812, B3676, A7312, B1145, B4944, A8359, A4484, B8972,
B1598, B4069, A4906, A5864, A3062, A9386, B1498, B3742, B8464, A2829,
B4932, A3169, B8984, B3314, A2825, B3522, B393, A8411, A7203, B4099,
B6780, B7807, B2189, B4644, A6175, B4113, B2449, B9133, B2455, A6716,
B7722, B3650, A9426, B1110, A7529, A4556, B2071, A6549, A7498, A6737,
A6140, A5234, B3211, B6155, A3547, B6266, A9754, B7056, A7445, B6293,
B6112, A3888, B6779, B713, B7403, B4533, A5093, A7817, B1141, B341,
A4888, A5959, B2442, A9033, A3413, A6992, A4931, B3277, B1482, A9495,
A6559, A6336, A3905, A3692, B4618, B3233, B5954, B3162, B4283, A8497,
B4441, B3413, A7897, B495, A4811, A5867, B7126, B2499, A7114, A5606,
A2966, B7058, A6317, B6323, B4652, A8274, A6784, A5525, A5374, A2883,
B7685, B8261, A5425, B1637, A4579, B5509, A9725, A4779, B130, B5873,
A6999, A7587, B2513, B9035, B2438, A4511, A5571, B6264, B5392, B355,
B6185, B1415, B3507, A6038, B7299, B1218, A9068, B6723, A4770, B296,
A6097, A7777, A3106, B8861, A4649, A3332, B5932, B2142, A4834, B1575,
A7020, A7760, A6698, B3818, A6491, A8183, A6242, B511, A5339, B1050,
B6750, B7531, A4123, B6061, A5644, A8041, A8771, B84, B2258, A8361,
B7407, B268, A5978, B4017, B7323, B3726, A3754, B1643, A9552, A6897,
B7073, A9056, A8086, A8537, A9903, B28, A3789, B1730, B635, A8111,
B6296, A3430, A7648, A8776, B4376, A6258, B953, A5148, B46, B6426,
B5808, B8489, A2957, B6132, B3409, B329, B4475, B1515, B7339, A6063,
A5791, A3398, B2625, B2704, B5739, B160, A6845, A4613, A8868, A4275,
B1647, A9121, B6251, A7958, A4752, A2809, B5720, A6527, B5327, B904,
B2199, B1670, A8661, A6035, B2736, B2249, B5751, B7936, A3036, B6452,
A9333, A4250, B8730, A9899, A5332, A7073, B5699, B2922, A7682, A4343,
B5496, B4521, B4859, A9070, A7508, A6603, B6135, A3916, A4425, A7252,
A6261, A4279, B7969, B2982, B4907, B8316, B8438, B1688, B3660, A3749,
A8728, A9512, A6971, B5359, B4164, B1241, B6596, B7379, B715, A4372,
B1021, A4417, B7571, B5642, B7537, B6035, B532, A2854, A4185, B4850,
A3932, B5493, B7965, B375, B2785, A6901, A8738, A8016, B4504, A5467,
A5709, A7669, A7832, B1072, B3256, A3875, B6785, A9547, B8795, A4709,
A4257, B1407, A5446, A7229, B4355, B7300, B2100, A8782, A5470, A9657,
B4926, B2638, A7245, B250, B5279, B9025, B4289, B4421, B3380, A7034,
A7145, A3884, B5033, A7418, A6662, A5068, B5146, B4957, A4642, B1433,
B1883, A6157, B8850, A7914, B1264, A7404, B5806, B4991, A9696, A6128,
B1855, A7220, A7755, A7657, A8984, B5758, B6628, B3922, A4975, B1270,
B7635, B7861, B3734, B4105, A5764, B7188, B4199, A9000, A9283, B2447,
B3633, A8244, B1203, B3668, B4359, B4885, A7021, A4007, A3709, A8395,
B6851, B1659, B2872, A6616, A5307, A8559, A9763, B9159, A4091, A5000,
A4566, B8953, B4237, A8347, B4255, A9149, B7445, A9434, A6423, B1385,
A8276, B8694, A3681, B1767, A5390, B8145, A8650, B134, A6058, B808,
B7556, B2970, A9892, B5406, B7431, B2340, B4196, B9152, A7388, B6683,
B1762, A5745, B9202, B2792, B2979, A4249, B8190, A9216, A9337, A6782,
B7243, B3951, A8995, B301, B737, A5291, B2989, A9879, B4740, A6757,
A7363, B5833, B3586, A7806, A9291, B6991, B7843, B2416, A9737, B740,
B3588, B2554, B6594, A3014, B9040, B1147, A8368, A3687, B7578, A4071,
B3705, A7542, A9980, A4227, A8659, B7749, A4307, B6006, B2731, B8940,
A4281, B8115, B148, B8050, A5429, A9351, B4827, B1366, A8317, B2833,
A2938, A3926, B6052, B2003, A7447, B338, A4214, B3375, A6401, B3134,
A4076, A8618, B4455, A4559, A4141, B9105, B6879, B5990, A8190, B2577,
A7188, B7918, B2415, B4703, A3613, B6313, A6104, B545, B5853, B5599,
A9653, B8822, B4036, B1748, B7332, B7651, B7833, B3786, A8488, B15,
A4734, B6512, A9081, B8292, A7293, B6498, A4408, A3587, B5162, B4779,
A8915, A3423, B6870, B3311, A5926, A5460, B2879, A8861, B2133, A3084,
B3404, B3500, B982, B8857, B8243, A7571, A9987, A5853, A4853, B2581,
B9170, B2842, B3914, B722, B7416, B1478, A7530, B7809, B3566, A6416,
B2994, B4348, A4718, A3764, B5722, A3160, B2751, A8472, A3403, B3987,
B4752, A9966, A4869, A3322, A8461, B944, B7184, B7980, B3457, B6936,
B8923, A9917, A6498, B8751, A8581, B5535, B2560, A7443, A5177, A9484,
B2314, B2949, B2963, B4209, B1486, B2504, B909, B1221, B6101, B9256,
B4712, A6453, B6727, A5523, A3417, A6832, B5939, B2235, A4312, B6944,
A4446, B3324, A8945, A4357, B276, B1400, A9373, B6661, A4982, B6519,
A7791, B3571, B7752, B6825, B1950, A8932, B3055, B265, A5396, A8827,
A9104, A6545, B5649, A5824, A5433, A6817, A6002, B8663, A8454, B2203,
A8288, A5152, B7629, A8197, B2745, A8355, B1561, B8801, B2821, B8300,
B8432, B7569, A8602, A7933, B5729, A5170, B2081, A4903, B8929, A8594,
B2397, B229, A6866, B1871, B3108, A9728, A3632, B7456, B5618, A8457,
A9364, B5928, B8868, B2658, A8142, A8290, A4354, A9288, B458, B1353,
B7236, B7341, B9036, B3290, A9101, B1728, B8230, B8565, B757, B2717,
A8281, B7239, B7286, A7091, B238, B612, B6547, B8678, B5190, B5098,
A7318, A4238, B876, A5695, A5633, A3428, B7491, B407, A9469, A5406,
B1391, B1801, A9054, B117, B5035, B8918, B4128, B6479, B5399, B3594,
A4208, B1712, A7787, B3638, A8138, B6059, B1587, A6223, B7292, B3958,
A8679, B4796, B563, A5133, B3128, A8633, A9620, B614, B7438, B3487,
A4113, B7259, B1170, A9860, A8543, A8301, A8839, B7313, B8910, B6686,
A9178, B3368, B4293, A2971, B8580, A4787, A5736, A5542, A3238, B4726,
A3742, B7763, A4193, B7068, A3898, B5789, B9273, A4682, B1524, B4881,
B482, B5563, A3296, B2645, A8304, A7231, A3726, B5266, A3533, B6646,
A9870, A7068, B7015, A7961, B5024, A7633, A9684, A7192, B5973, A7742,
A4606, A6468, A4650, A8955, B9193, B7617, A3797, A7547, B344, A6430,
B3051, B3155, B5658, A5165, A9389, A4371, B8711, A4538, B7768, B1304,
B2396, B729, B4748, B2544, B6521, A4677, A8055, B2851, B1032, B6666,
B7712, A9570, B450, B4562, A7723, B19, B623, A5813, B7884, A5105,
B1719, A6583, B6776, B4044, B5129, A9423, A9867, B8895, B9050, A8082,
A9412, B3450, A7005, B2591, A7522, B3674, B5989, B1691, A3382, B3717,
A4657, A9593, B7508, B2334, B606, B608, B5003, A7537, A8578, A7130,
B6580, B8104, B3806, A8007, B4005, B8613, B8459, B5651, B2316, B2762,
B6099, B4323, A4016, A8894, B1607, A8673, B5606, A9144, A3790, B8967,
B1969, A6867, A6793, B2670, B3044, B1321, A8925, B539, A9923, B1993,
B3591, B2302, A9997, B855, B1723, A4744, B5982, A9127, A6580, B1746,
A4702, B6982, B3647, A7650, B5552, A6518, B1707, B6894, B6277, B8901,
B3492, B9260, B2631, A8167, A8211, A5670, A4154, A3218, B6383, A4871,
A9018, B779, B9226, B2570, B3416, A8887, B5336, B1980, B4951, A4128,
B8887, B1462, B1700, A5269, A7771, A3478, B2787, B501, B892, A4455,
B3476, A7981, B8035, A6985, A2964, B8071, B2020, A4320, B2726, A4586,
A8234, B9205, B3683, A8668, B5691, B1234, A7643, B3472, B3752, A5544,
B7610, B218, B7719, A9220, B7386, B811, B6214, B6712, B7894, A8200,
A9854, B3101, A7585, A9805, B1555, B2463, B2146, B3839, A6390, A5992,
B6761, A6432, B3905, A7838, B4438, A3985, A9046, B8141, B8570, A5229,
B7702, B8786, A5382, B6462, B7676, A7125, A3490, A6916, B1920, A9587,
A7840, B385, B7424, A8149, A4633, B4830, A9318, B825, A6878, B8229,
A5383, A4229, B8589, A6119, B5443, B2899, A3203, B1380, B5108, B8014,
A9613, B7709, A5786, B7998, B7927, B8640, B6046, B21, B7643, B5155,
A7974, B858, A5505, B5683, B9129, A7431, A8807, A4799, A4954, A5592,
B8555, A4851, B1985, A4270, B8389, A9557, B1896, B75, B4215, A7568,
A2865, B1632, B8727, A6235, A4236, B7147, B1248, A3265, B3878, B2327,
B2113, B204, A5497, B6619, B2721, B2883, B576, A5311, B7597, A5807,
B8775, A8785, B4734, A6092, A4108, B7513, B5086, B4314, A7798, A8159,
A8100, B5138, A8160, B232, A4092, B5306, B8248, A3718, B1699, B1933,
B3659, B1059, B2402, B5410, A8548, B861, B58, B1109, B489, B1653,
A5277, B6617, A9421, A3601, B2672, B2789, B7157, B7061, B3559, B1445,
A8922, B1097, A7059, A9545, A3996, A5706, B5709, A6332, A5698, A9325,
A3581, A9120, A6726, A4059, A7905, A9830, B8446, B2433, B2984, B6204,
A2926, B2400, B3418, A2982, B6342, B1179, A5364, B1634, B7004, A8310,
B5134, A8624, B2466, A7420, A2896, A9629, A4444, B8084, B2054, A8241,
A9206, A8907, A3304, B4158, B4865, A8623, B7045, A9564, A3565, B2053,
B5900, B7982, B4523, A6334, B6026, B794, B916, B5521, A9976, B788,
A4050, B1970, A5472, A3464, B4444, B7893, B6232, A6869, B1425, B1836,
A8796, B4252, A3139, B3169, A5030, A8876, A9943, B361, B585, B9297,
A6106, B8298, B1662, B3556, B4719, B411, B9207, B5064, B2474, A4126,
B5310, A7917, B658, B8559, B2714, B4268, A9253, A6068, B1401, B4620,
A5629, B7582, B3712, A6594, A7503, B3067, B1049, A9664, B313, B5867,
A8609, B4383, B4949, B679, A3626, B443, B3460, B523, A7139, B910,
A3820, B4798, A7371, B5373, A8534, A3025, B4773, A5510, B2849, B3193,
A2817, A5313, A3815, B5246, B3099, B6453, A9249, B3625, A7769, A6365,
A6505, A9130, B8429, B1635, B5589, B325, B889, B9251, A7728, B5706,
B1329, A7283, B724, A9099, B3618, B8063, B1239, A3492, B5782, A3047,
A3846, B8005, B1846, B2276, B4809, A5112, A3786, B3214, A6061, B5889,
B3533, B6401, A7889, B1330, A9377, B5419, B193, B170, B3744, B4722,
A4700, B8733, A6557, A5874, B1627, A9452, A8345, A5663, B2684, A6898,
A9311, B206, A6450, B3970, A9381, A8151, A8199, B5428, B7872, B2158,
A6938, B6654, B9306, B6911, B2828, A3156, A6944, B1585, B5590, B2865,
A6072, A8376, A7396, A7518, B5242, A4173, B6986, B3579, A3666, A8936,
B8763, B7174, B2280, A6263, A3099, A7716, B6551, A4040, A6348, B3621,
B5987, B9162, A3857, B3930, A5139, B5528, B7152, B8567, B110, B6247,
A6025, B6363, A8489, B2758, B5733, B2546, A8292, A3118, A8077, A4335,
B5816, A7120, A9409, A9572, B5464, B3040, A8176, A4317, B6929, B6649,
A5181, B3444, A4764, A4863, B2184, B1151, B4274, A7693, A8131, B201,
A5013, A8103, A8566, A5662, A2952, A2806, B2073, B5567, A8837, A3019,
B4343, A8767, A8338, B6558, A6319, B1602, B2946, B4818, B1409, B2121,
A7401, A3426, B8659, A7456, A5078, B4389, A7359, A8588, A9493, A6882,
A4118, B2803, B4553, A8600, A9137, A9304, A6162, A7010, B7854, A9633,
A6730, B6639, B4366, B5656, A9739, A5757, A8035, B509, A7718, A5615,
A7616, B5343, B8527, A6969, A7561, B3086, B2952, A7213, B5, A7429,
A3196, B803, B2368, A3652, B1510, A3458, B7440, A9508, B4468, A2875,
B1125, B3003, B4480, B5860, B1541, A8262, B6787, B6165, B6144, B7027,
A8682, A9296, B1299, B446, B336, B1314, B4559, B4972, A3891, A7520,
B3333, B2329, A6275, B359, B6953, B2423, B5037, B3715, B55, B3569,
B366, A7352, B3945, B4950, B4567, B2369, B8118, B8175, A7316, A4830,
A3598, B7799, A6987, A6692, A4453, A7302, A8005, B242, B2426, B1866,
B5949, B3207, A6043, A3952, A7980, A4966, A4029, A5285, A9184, A7218,
B853, B5665, A8557, B38, B2807, A9957, B6971, B3611, A7828, B4492,
A8674, B770, B4392, A2959, B5019, B4337, A9730, B5764, B6014, B2626,
B4638, A7888, B695, A3948, B6053, A9504, B3135, A8617, A6255, A9514,
A3345, A9832, A6170, A6125, A4048, B7223, B8401, B2350, B3965, B4357,
B633, A9816, B5489, A5009, B6888, B7474, A7169, B963, A6173, A9710,
B4109, A8975, A7469, A8834, A3150, B8591, B4169, A9443, B463, A6829,
B2005, B7845, B1003, A4522, B7109, B7662, B8136, B8611, A8437, B3344,
A3146, B1435, B6199, A9460, A6768, B8263, B8366, A3886, B967, A4367,
B2914, B872, A3147, B4531, A5710, B1335, A9021, B5914, A9035, B1590,
B4908, A4716, B1507, A8387, A3337, B9066, A9211, A4591, B4152, A5738,
B5127, B4705, A5964, B8164, B1450, A6853, A6137, A7655, A4898, B8797,
A3608, A7624, A9218, B4915, A9877, B5319, B4642, A4514, A9756, B5401,
A7267, A6384, B5799, B1040, A3100, B7939, B125, B1294, B1016, B5022,
B8368, A7554, B8047, B2409, B4097, A5676, B2349, A8858, B6084, B8052,
B5969, A5326, A4427, A4420, B1166, B6528, B6807, A3833, B3247, B4064,
A8718, A3107, B4004, B1533, B2180, A9844, B1253, A9767, A6621, A4240,
B5956, B4646, B844, B7744, A8851, B7669, B1343, A6567, B6694, A3167,
B5309, B7194, B3300, A3094, A2905, B7084, B427, B7039, A6161, B4015,
A3592, B2104, A3991, A5862, B4136, A2827, B4085, A7621, A8350, B2264,
A4855, A7088, A5206, A7051, B13, B2260, B4682, B8985, A3180, B3226,
A5731, B8492, B4443, B1082, B1112, B993, A4802, B3652, B5099, A6547,
B5597, B1121, A3060, B2694, B3160, A4997, A3699, B4028, B4934, A7602,
B2815, A6142, B8669, A6486, B3760, A7638, B664, B2532, B4303, A7412,
B1592, B3231, A8849, A5427, B7913, B6157, A5957, B6782, B4111, A5194,
B23, A3766, A9752, B2272, B2649, B3238, B4121, B4742, A4773, A7895,
B7205, B9033, B6315, B2453, B9118, A6921, B6336, B1289, B7054, B7697,
B7101, B4989, B7305, B8462, A7112, A7591, B8029, B1373, B4083, A9723,
A5635, B493, B7405, B8268, A4291, B2511, A8645, B3393, B395, A3959,
B1459, A9011, B4659, B8501, A7223, A4885, B4939, B6423, B2615, B4298,
B6847, B8638, B6993, B3275, B9239, B8787, A8430, A6084, B8689, A8427,
B6791, B1907, B5933, A8357, B4942, A7266, B4612, B2068, B3545, A9985,
A3233, B4176, A8965, B1567, B181, B6129, B6350, B2490, B8842, A5340,
A8539, B5087, B419, B7737, A7841, B5294, B2604, A7779, B5257, B2345,
B3896, A6711, B5700, A7011, A8755, A5375, B191, A4014, A9255, A7481,
A5050, B1094, A9165, B159, A6397, A5888, A8409, A8815, A9260, B3754,
A6688, B5052, A9521, B1070, A8753, A8705, A7183, A2838, B4663, A7946,
A6189, B7035, B6715, A7340, A8192, B7881, B7683, A5842, B8257, A4525,
A5835, B3960, A6357, A4415, A8703, B7337, B3529, A4841, A6953, B6709,
B3350, B9002, B2036, B7514, B4403, A4942, A4137, B6119, A9706, A4508,
B6430, A6732, B6840, B976, B5752, B9053, A5062, B6192, A5729, B8359,
B3359, B686, B5500, A9397, A7945, A9236, A2900, B4966, A6288, A8120,
B8537, B8762, A8074, B5473, A9719, A6651, A9428, B4426, B6416, A3290,
A5773, B7776, B7781, B4835, B6610, B2063, B473, B8374, B5012, B8196,
B1799, B4657, B2664, B8817, B2013, A9619, A6848, A7247, A5841, B2336,
B6282, B3373, B835, B7274, A4598, A3982, A5083, B8159, A3715, A2842,
A4807, B934, B1810, B2747, B3883, B7214, A5246, B999, A4580, B7974,
A9679, A7706, A8390, A7236, A8126, A9401, B5228, B6089, B8007, B3517,
B877, A6990, B8691, B7730, A7434, B1440, B1136, B672, B1686, A7348,
B5231, A6218, A9231, B6945, B2930, A7367, A6618, A3030, B4518, A6638,
B5715, B2095, A8685, B5882, B6359, B6033, B2178, A5035, A3286, A4589,
A9198, B346, B2357, A7872, B8833, A4225, B3600, B152, A3648, A4845,
B4261, B4380, A7810, A8519, A3516, B1190, A7684, B2245, B4225, A4503,
A6650, A3130, B1556, A3578, B2078, B1074, B893, A5239, A5041, A7259,
A4438, A8741, B6, A5891, B8601, B2091, A4064, B2492, A7278: std_logic;
begin
-- Start of original equations
B5214 <= B5192 and B5207;
B5213 <= (not B5192) and (not B5214);
B5212 <= B5192 or B5207;
B5211 <= (not B5185) or (not B5186);
B5210 <= B5192 or B5207;
B5209 <= (not B5208) and (not B5192);
B5208 <= B5192 and B5207;
B5207 <= (not B5183) or (not B5184);
B5206 <= B5184 and B5196;
B5205 <= B5185 or B5192;
B5204 <= B5185 or B5186;
B5203 <= (not B5213) or (not B5212);
B5202 <= B5211 and B5204;
B5201 <= ((not B5185) and B5192) or (B5185 and (not B5192));
B5200 <= (not B5209) or (not B5210);
B5199 <= (B5184 and B5196) or ((not B5184) and (not B5196));
B5198 <= B5206 or B5183;
B5197 <= B5203 and B5184;
B5196 <= B5205 and B5204;
B5195 <= B5200 and B5184;
B5194 <= B5202 and B5201;
B5193 <= ((not B5194) and B5184) or (B5194 and (not B5184));
B5192 <= ((not B5182) and B5183) or (B5182 and (not B5183));
B5191 <= B5192 and B5199;
B5190 <= B5192 and B5198;
B5189 <= B5197 or B5196;
B5188 <= B5195 or B5194;
B5187 <= B5193 and B5192;
B5220 <= B5226 and B5225;
B5221 <= B5228 or B5227;
B5222 <= B5230 or B5229;
B5223 <= B5225 and B5231;
B5224 <= B5225 and B5232;
B5225 <= ((not B5215) and B5216) or (B5215 and (not B5216));
B5226 <= ((not B5227) and B5217) or (B5227 and (not B5217));
B5227 <= B5235 and B5234;
B5228 <= B5233 and B5217;
B5229 <= B5238 and B5237;
B5230 <= B5236 and B5217;
B5231 <= B5239 or B5216;
B5232 <= (B5217 and B5229) or ((not B5217) and (not B5229));
B5233 <= (not B5242) or (not B5243);
B5234 <= ((not B5218) and B5225) or (B5218 and (not B5225));
B5235 <= B5244 and B5237;
B5236 <= (not B5246) or (not B5245);
B5237 <= B5218 or B5219;
B5238 <= B5218 or B5225;
B5239 <= B5217 and B5229;
B5240 <= (not B5216) or (not B5217);
B5241 <= B5225 and B5240;
B5242 <= (not B5241) and (not B5225);
B5243 <= B5225 or B5240;
B5244 <= (not B5218) or (not B5219);
B5245 <= B5225 or B5240;
B5246 <= (not B5225) and (not B5247);
B5247 <= B5225 and B5240;
B5253 <= B5259 and B5258;
B5254 <= B5261 or B5260;
B5255 <= B5263 or B5262;
B5256 <= B5258 and B5264;
B5257 <= B5258 and B5265;
B5258 <= ((not B5248) and B5249) or (B5248 and (not B5249));
B5259 <= ((not B5260) and B5250) or (B5260 and (not B5250));
B5260 <= B5268 and B5267;
B5261 <= B5266 and B5250;
B5262 <= B5271 and B5270;
B5263 <= B5269 and B5250;
B5264 <= B5272 or B5249;
B5265 <= (B5250 and B5262) or ((not B5250) and (not B5262));
B5266 <= (not B5275) or (not B5276);
B5267 <= ((not B5251) and B5258) or (B5251 and (not B5258));
B5268 <= B5277 and B5270;
B5269 <= (not B5279) or (not B5278);
B5270 <= B5251 or B5252;
B5271 <= B5251 or B5258;
B5272 <= B5250 and B5262;
B5273 <= (not B5249) or (not B5250);
B5274 <= B5258 and B5273;
B5275 <= (not B5274) and (not B5258);
B5276 <= B5258 or B5273;
B5277 <= (not B5251) or (not B5252);
B5278 <= B5258 or B5273;
B5279 <= (not B5258) and (not B5280);
B5280 <= B5258 and B5273;
B5286 <= B5292 and B5291;
B5287 <= B5294 or B5293;
B5288 <= B5296 or B5295;
B5289 <= B5291 and B5297;
B5290 <= B5291 and B5298;
B5291 <= ((not B5281) and B5282) or (B5281 and (not B5282));
B5292 <= ((not B5293) and B5283) or (B5293 and (not B5283));
B5293 <= B5301 and B5300;
B5294 <= B5299 and B5283;
B5295 <= B5304 and B5303;
B5296 <= B5302 and B5283;
B5297 <= B5305 or B5282;
B5298 <= (B5283 and B5295) or ((not B5283) and (not B5295));
B5299 <= (not B5308) or (not B5309);
B5300 <= ((not B5284) and B5291) or (B5284 and (not B5291));
B5301 <= B5310 and B5303;
B5302 <= (not B5312) or (not B5311);
B5303 <= B5284 or B5285;
B5304 <= B5284 or B5291;
B5305 <= B5283 and B5295;
B5306 <= (not B5282) or (not B5283);
B5307 <= B5291 and B5306;
B5308 <= (not B5307) and (not B5291);
B5309 <= B5291 or B5306;
B5310 <= (not B5284) or (not B5285);
B5311 <= B5291 or B5306;
B5312 <= (not B5291) and (not B5313);
B5313 <= B5291 and B5306;
B5319 <= B5325 and B5324;
B5320 <= B5327 or B5326;
B5321 <= B5329 or B5328;
B5322 <= B5324 and B5330;
B5323 <= B5324 and B5331;
B5324 <= ((not B5314) and B5315) or (B5314 and (not B5315));
B5325 <= ((not B5326) and B5316) or (B5326 and (not B5316));
B5326 <= B5334 and B5333;
B5327 <= B5332 and B5316;
B5328 <= B5337 and B5336;
B5329 <= B5335 and B5316;
B5330 <= B5338 or B5315;
B5331 <= (B5316 and B5328) or ((not B5316) and (not B5328));
B5332 <= (not B5341) or (not B5342);
B5333 <= ((not B5317) and B5324) or (B5317 and (not B5324));
B5334 <= B5343 and B5336;
B5335 <= (not B5345) or (not B5344);
B5336 <= B5317 or B5318;
B5337 <= B5317 or B5324;
B5338 <= B5316 and B5328;
B5339 <= (not B5315) or (not B5316);
B5340 <= B5324 and B5339;
B5341 <= (not B5340) and (not B5324);
B5342 <= B5324 or B5339;
B5343 <= (not B5317) or (not B5318);
B5344 <= B5324 or B5339;
B5345 <= (not B5324) and (not B5346);
B5346 <= B5324 and B5339;
B5352 <= B5358 and B5357;
B5353 <= B5360 or B5359;
B5354 <= B5362 or B5361;
B5355 <= B5357 and B5363;
B5356 <= B5357 and B5364;
B5357 <= ((not B5347) and B5348) or (B5347 and (not B5348));
B5358 <= ((not B5359) and B5349) or (B5359 and (not B5349));
B5359 <= B5367 and B5366;
B5360 <= B5365 and B5349;
B5361 <= B5370 and B5369;
B5362 <= B5368 and B5349;
B5363 <= B5371 or B5348;
B5364 <= (B5349 and B5361) or ((not B5349) and (not B5361));
B5365 <= (not B5374) or (not B5375);
B5366 <= ((not B5350) and B5357) or (B5350 and (not B5357));
B5367 <= B5376 and B5369;
B5368 <= (not B5378) or (not B5377);
B5369 <= B5350 or B5351;
B5370 <= B5350 or B5357;
B5371 <= B5349 and B5361;
B5372 <= (not B5348) or (not B5349);
B5373 <= B5357 and B5372;
B5374 <= (not B5373) and (not B5357);
B5375 <= B5357 or B5372;
B5376 <= (not B5350) or (not B5351);
B5377 <= B5357 or B5372;
B5378 <= (not B5357) and (not B5379);
B5379 <= B5357 and B5372;
B5385 <= B5391 and B5390;
B5386 <= B5393 or B5392;
B5387 <= B5395 or B5394;
B5388 <= B5390 and B5396;
B5389 <= B5390 and B5397;
B5390 <= ((not B5380) and B5381) or (B5380 and (not B5381));
B5391 <= ((not B5392) and B5382) or (B5392 and (not B5382));
B5392 <= B5400 and B5399;
B5393 <= B5398 and B5382;
B5394 <= B5403 and B5402;
B5395 <= B5401 and B5382;
B5396 <= B5404 or B5381;
B5397 <= (B5382 and B5394) or ((not B5382) and (not B5394));
B5398 <= (not B5407) or (not B5408);
B5399 <= ((not B5383) and B5390) or (B5383 and (not B5390));
B5400 <= B5409 and B5402;
B5401 <= (not B5411) or (not B5410);
B5402 <= B5383 or B5384;
B5403 <= B5383 or B5390;
B5404 <= B5382 and B5394;
B5405 <= (not B5381) or (not B5382);
B5406 <= B5390 and B5405;
B5407 <= (not B5406) and (not B5390);
B5408 <= B5390 or B5405;
B5409 <= (not B5383) or (not B5384);
B5410 <= B5390 or B5405;
B5411 <= (not B5390) and (not B5412);
B5412 <= B5390 and B5405;
B5418 <= B5424 and B5423;
B5419 <= B5426 or B5425;
B5420 <= B5428 or B5427;
B5421 <= B5423 and B5429;
B5422 <= B5423 and B5430;
B5423 <= ((not B5413) and B5414) or (B5413 and (not B5414));
B5424 <= ((not B5425) and B5415) or (B5425 and (not B5415));
B5425 <= B5433 and B5432;
B5426 <= B5431 and B5415;
B5427 <= B5436 and B5435;
B5428 <= B5434 and B5415;
B5429 <= B5437 or B5414;
B5430 <= (B5415 and B5427) or ((not B5415) and (not B5427));
B5431 <= (not B5440) or (not B5441);
B5432 <= ((not B5416) and B5423) or (B5416 and (not B5423));
B5433 <= B5442 and B5435;
B5434 <= (not B5444) or (not B5443);
B5435 <= B5416 or B5417;
B5436 <= B5416 or B5423;
B5437 <= B5415 and B5427;
B5438 <= (not B5414) or (not B5415);
B5439 <= B5423 and B5438;
B5440 <= (not B5439) and (not B5423);
B5441 <= B5423 or B5438;
B5442 <= (not B5416) or (not B5417);
B5443 <= B5423 or B5438;
B5444 <= (not B5423) and (not B5445);
B5445 <= B5423 and B5438;
B5451 <= B5457 and B5456;
B5452 <= B5459 or B5458;
B5453 <= B5461 or B5460;
B5454 <= B5456 and B5462;
B5455 <= B5456 and B5463;
B5456 <= ((not B5446) and B5447) or (B5446 and (not B5447));
B5457 <= ((not B5458) and B5448) or (B5458 and (not B5448));
B5458 <= B5466 and B5465;
B5459 <= B5464 and B5448;
B5460 <= B5469 and B5468;
B5461 <= B5467 and B5448;
B5462 <= B5470 or B5447;
B5463 <= (B5448 and B5460) or ((not B5448) and (not B5460));
B5464 <= (not B5473) or (not B5474);
B5465 <= ((not B5449) and B5456) or (B5449 and (not B5456));
B5466 <= B5475 and B5468;
B5467 <= (not B5477) or (not B5476);
B5468 <= B5449 or B5450;
B5469 <= B5449 or B5456;
B5470 <= B5448 and B5460;
B5471 <= (not B5447) or (not B5448);
B5472 <= B5456 and B5471;
B5473 <= (not B5472) and (not B5456);
B5474 <= B5456 or B5471;
B5475 <= (not B5449) or (not B5450);
B5476 <= B5456 or B5471;
B5477 <= (not B5456) and (not B5478);
B5478 <= B5456 and B5471;
B5484 <= B5490 and B5489;
B5485 <= B5492 or B5491;
B5486 <= B5494 or B5493;
B5487 <= B5489 and B5495;
B5488 <= B5489 and B5496;
B5489 <= ((not B5479) and B5480) or (B5479 and (not B5480));
B5490 <= ((not B5491) and B5481) or (B5491 and (not B5481));
B5491 <= B5499 and B5498;
B5492 <= B5497 and B5481;
B5493 <= B5502 and B5501;
B5494 <= B5500 and B5481;
B5495 <= B5503 or B5480;
B5496 <= (B5481 and B5493) or ((not B5481) and (not B5493));
B5497 <= (not B5506) or (not B5507);
B5498 <= ((not B5482) and B5489) or (B5482 and (not B5489));
B5499 <= B5508 and B5501;
B5500 <= (not B5510) or (not B5509);
B5501 <= B5482 or B5483;
B5502 <= B5482 or B5489;
B5503 <= B5481 and B5493;
B5504 <= (not B5480) or (not B5481);
B5505 <= B5489 and B5504;
B5506 <= (not B5505) and (not B5489);
B5507 <= B5489 or B5504;
B5508 <= (not B5482) or (not B5483);
B5509 <= B5489 or B5504;
B5510 <= (not B5489) and (not B5511);
B5511 <= B5489 and B5504;
B5517 <= B5523 and B5522;
B5518 <= B5525 or B5524;
B5519 <= B5527 or B5526;
B5520 <= B5522 and B5528;
B5521 <= B5522 and B5529;
B5522 <= ((not B5512) and B5513) or (B5512 and (not B5513));
B5523 <= ((not B5524) and B5514) or (B5524 and (not B5514));
B5524 <= B5532 and B5531;
B5525 <= B5530 and B5514;
B5526 <= B5535 and B5534;
B5527 <= B5533 and B5514;
B5528 <= B5536 or B5513;
B5529 <= (B5514 and B5526) or ((not B5514) and (not B5526));
B5530 <= (not B5539) or (not B5540);
B5531 <= ((not B5515) and B5522) or (B5515 and (not B5522));
B5532 <= B5541 and B5534;
B5533 <= (not B5543) or (not B5542);
B5534 <= B5515 or B5516;
B5535 <= B5515 or B5522;
B5536 <= B5514 and B5526;
B5537 <= (not B5513) or (not B5514);
B5538 <= B5522 and B5537;
B5539 <= (not B5538) and (not B5522);
B5540 <= B5522 or B5537;
B5541 <= (not B5515) or (not B5516);
B5542 <= B5522 or B5537;
B5543 <= (not B5522) and (not B5544);
B5544 <= B5522 and B5537;
B5550 <= B5556 and B5555;
B5551 <= B5558 or B5557;
B5552 <= B5560 or B5559;
B5553 <= B5555 and B5561;
B5554 <= B5555 and B5562;
B5555 <= ((not B5545) and B5546) or (B5545 and (not B5546));
B5556 <= ((not B5557) and B5547) or (B5557 and (not B5547));
B5557 <= B5565 and B5564;
B5558 <= B5563 and B5547;
B5559 <= B5568 and B5567;
B5560 <= B5566 and B5547;
B5561 <= B5569 or B5546;
B5562 <= (B5547 and B5559) or ((not B5547) and (not B5559));
B5563 <= (not B5572) or (not B5573);
B5564 <= ((not B5548) and B5555) or (B5548 and (not B5555));
B5565 <= B5574 and B5567;
B5566 <= (not B5576) or (not B5575);
B5567 <= B5548 or B5549;
B5568 <= B5548 or B5555;
B5569 <= B5547 and B5559;
B5570 <= (not B5546) or (not B5547);
B5571 <= B5555 and B5570;
B5572 <= (not B5571) and (not B5555);
B5573 <= B5555 or B5570;
B5574 <= (not B5548) or (not B5549);
B5575 <= B5555 or B5570;
B5576 <= (not B5555) and (not B5577);
B5577 <= B5555 and B5570;
B5583 <= B5589 and B5588;
B5584 <= B5591 or B5590;
B5585 <= B5593 or B5592;
B5586 <= B5588 and B5594;
B5587 <= B5588 and B5595;
B5588 <= ((not B5578) and B5579) or (B5578 and (not B5579));
B5589 <= ((not B5590) and B5580) or (B5590 and (not B5580));
B5590 <= B5598 and B5597;
B5591 <= B5596 and B5580;
B5592 <= B5601 and B5600;
B5593 <= B5599 and B5580;
B5594 <= B5602 or B5579;
B5595 <= (B5580 and B5592) or ((not B5580) and (not B5592));
B5596 <= (not B5605) or (not B5606);
B5597 <= ((not B5581) and B5588) or (B5581 and (not B5588));
B5598 <= B5607 and B5600;
B5599 <= (not B5609) or (not B5608);
B5600 <= B5581 or B5582;
B5601 <= B5581 or B5588;
B5602 <= B5580 and B5592;
B5603 <= (not B5579) or (not B5580);
B5604 <= B5588 and B5603;
B5605 <= (not B5604) and (not B5588);
B5606 <= B5588 or B5603;
B5607 <= (not B5581) or (not B5582);
B5608 <= B5588 or B5603;
B5609 <= (not B5588) and (not B5610);
B5610 <= B5588 and B5603;
B5616 <= B5622 and B5621;
B5617 <= B5624 or B5623;
B5618 <= B5626 or B5625;
B5619 <= B5621 and B5627;
B5620 <= B5621 and B5628;
B5621 <= ((not B5611) and B5612) or (B5611 and (not B5612));
B5622 <= ((not B5623) and B5613) or (B5623 and (not B5613));
B5623 <= B5631 and B5630;
B5624 <= B5629 and B5613;
B5625 <= B5634 and B5633;
B5626 <= B5632 and B5613;
B5627 <= B5635 or B5612;
B5628 <= (B5613 and B5625) or ((not B5613) and (not B5625));
B5629 <= (not B5638) or (not B5639);
B5630 <= ((not B5614) and B5621) or (B5614 and (not B5621));
B5631 <= B5640 and B5633;
B5632 <= (not B5642) or (not B5641);
B5633 <= B5614 or B5615;
B5634 <= B5614 or B5621;
B5635 <= B5613 and B5625;
B5636 <= (not B5612) or (not B5613);
B5637 <= B5621 and B5636;
B5638 <= (not B5637) and (not B5621);
B5639 <= B5621 or B5636;
B5640 <= (not B5614) or (not B5615);
B5641 <= B5621 or B5636;
B5642 <= (not B5621) and (not B5643);
B5643 <= B5621 and B5636;
B5649 <= B5655 and B5654;
B5650 <= B5657 or B5656;
B5651 <= B5659 or B5658;
B5652 <= B5654 and B5660;
B5653 <= B5654 and B5661;
B5654 <= ((not B5644) and B5645) or (B5644 and (not B5645));
B5655 <= ((not B5656) and B5646) or (B5656 and (not B5646));
B5656 <= B5664 and B5663;
B5657 <= B5662 and B5646;
B5658 <= B5667 and B5666;
B5659 <= B5665 and B5646;
B5660 <= B5668 or B5645;
B5661 <= (B5646 and B5658) or ((not B5646) and (not B5658));
B5662 <= (not B5671) or (not B5672);
B5663 <= ((not B5647) and B5654) or (B5647 and (not B5654));
B5664 <= B5673 and B5666;
B5665 <= (not B5675) or (not B5674);
B5666 <= B5647 or B5648;
B5667 <= B5647 or B5654;
B5668 <= B5646 and B5658;
B5669 <= (not B5645) or (not B5646);
B5670 <= B5654 and B5669;
B5671 <= (not B5670) and (not B5654);
B5672 <= B5654 or B5669;
B5673 <= (not B5647) or (not B5648);
B5674 <= B5654 or B5669;
B5675 <= (not B5654) and (not B5676);
B5676 <= B5654 and B5669;
B5682 <= B5688 and B5687;
B5683 <= B5690 or B5689;
B5684 <= B5692 or B5691;
B5685 <= B5687 and B5693;
B5686 <= B5687 and B5694;
B5687 <= ((not B5677) and B5678) or (B5677 and (not B5678));
B5688 <= ((not B5689) and B5679) or (B5689 and (not B5679));
B5689 <= B5697 and B5696;
B5690 <= B5695 and B5679;
B5691 <= B5700 and B5699;
B5692 <= B5698 and B5679;
B5693 <= B5701 or B5678;
B5694 <= (B5679 and B5691) or ((not B5679) and (not B5691));
B5695 <= (not B5704) or (not B5705);
B5696 <= ((not B5680) and B5687) or (B5680 and (not B5687));
B5697 <= B5706 and B5699;
B5698 <= (not B5708) or (not B5707);
B5699 <= B5680 or B5681;
B5700 <= B5680 or B5687;
B5701 <= B5679 and B5691;
B5702 <= (not B5678) or (not B5679);
B5703 <= B5687 and B5702;
B5704 <= (not B5703) and (not B5687);
B5705 <= B5687 or B5702;
B5706 <= (not B5680) or (not B5681);
B5707 <= B5687 or B5702;
B5708 <= (not B5687) and (not B5709);
B5709 <= B5687 and B5702;
B5715 <= B5721 and B5720;
B5716 <= B5723 or B5722;
B5717 <= B5725 or B5724;
B5718 <= B5720 and B5726;
B5719 <= B5720 and B5727;
B5720 <= ((not B5710) and B5711) or (B5710 and (not B5711));
B5721 <= ((not B5722) and B5712) or (B5722 and (not B5712));
B5722 <= B5730 and B5729;
B5723 <= B5728 and B5712;
B5724 <= B5733 and B5732;
B5725 <= B5731 and B5712;
B5726 <= B5734 or B5711;
B5727 <= (B5712 and B5724) or ((not B5712) and (not B5724));
B5728 <= (not B5737) or (not B5738);
B5729 <= ((not B5713) and B5720) or (B5713 and (not B5720));
B5730 <= B5739 and B5732;
B5731 <= (not B5741) or (not B5740);
B5732 <= B5713 or B5714;
B5733 <= B5713 or B5720;
B5734 <= B5712 and B5724;
B5735 <= (not B5711) or (not B5712);
B5736 <= B5720 and B5735;
B5737 <= (not B5736) and (not B5720);
B5738 <= B5720 or B5735;
B5739 <= (not B5713) or (not B5714);
B5740 <= B5720 or B5735;
B5741 <= (not B5720) and (not B5742);
B5742 <= B5720 and B5735;
B5748 <= B5754 and B5753;
B5749 <= B5756 or B5755;
B5750 <= B5758 or B5757;
B5751 <= B5753 and B5759;
B5752 <= B5753 and B5760;
B5753 <= ((not B5743) and B5744) or (B5743 and (not B5744));
B5754 <= ((not B5755) and B5745) or (B5755 and (not B5745));
B5755 <= B5763 and B5762;
B5756 <= B5761 and B5745;
B5757 <= B5766 and B5765;
B5758 <= B5764 and B5745;
B5759 <= B5767 or B5744;
B5760 <= (B5745 and B5757) or ((not B5745) and (not B5757));
B5761 <= (not B5770) or (not B5771);
B5762 <= ((not B5746) and B5753) or (B5746 and (not B5753));
B5763 <= B5772 and B5765;
B5764 <= (not B5774) or (not B5773);
B5765 <= B5746 or B5747;
B5766 <= B5746 or B5753;
B5767 <= B5745 and B5757;
B5768 <= (not B5744) or (not B5745);
B5769 <= B5753 and B5768;
B5770 <= (not B5769) and (not B5753);
B5771 <= B5753 or B5768;
B5772 <= (not B5746) or (not B5747);
B5773 <= B5753 or B5768;
B5774 <= (not B5753) and (not B5775);
B5775 <= B5753 and B5768;
B5781 <= B5787 and B5786;
B5782 <= B5789 or B5788;
B5783 <= B5791 or B5790;
B5784 <= B5786 and B5792;
B5785 <= B5786 and B5793;
B5786 <= ((not B5776) and B5777) or (B5776 and (not B5777));
B5787 <= ((not B5788) and B5778) or (B5788 and (not B5778));
B5788 <= B5796 and B5795;
B5789 <= B5794 and B5778;
B5790 <= B5799 and B5798;
B5791 <= B5797 and B5778;
B5792 <= B5800 or B5777;
B5793 <= (B5778 and B5790) or ((not B5778) and (not B5790));
B5794 <= (not B5803) or (not B5804);
B5795 <= ((not B5779) and B5786) or (B5779 and (not B5786));
B5796 <= B5805 and B5798;
B5797 <= (not B5807) or (not B5806);
B5798 <= B5779 or B5780;
B5799 <= B5779 or B5786;
B5800 <= B5778 and B5790;
B5801 <= (not B5777) or (not B5778);
B5802 <= B5786 and B5801;
B5803 <= (not B5802) and (not B5786);
B5804 <= B5786 or B5801;
B5805 <= (not B5779) or (not B5780);
B5806 <= B5786 or B5801;
B5807 <= (not B5786) and (not B5808);
B5808 <= B5786 and B5801;
B5814 <= B5820 and B5819;
B5815 <= B5822 or B5821;
B5816 <= B5824 or B5823;
B5817 <= B5819 and B5825;
B5818 <= B5819 and B5826;
B5819 <= ((not B5809) and B5810) or (B5809 and (not B5810));
B5820 <= ((not B5821) and B5811) or (B5821 and (not B5811));
B5821 <= B5829 and B5828;
B5822 <= B5827 and B5811;
B5823 <= B5832 and B5831;
B5824 <= B5830 and B5811;
B5825 <= B5833 or B5810;
B5826 <= (B5811 and B5823) or ((not B5811) and (not B5823));
B5827 <= (not B5836) or (not B5837);
B5828 <= ((not B5812) and B5819) or (B5812 and (not B5819));
B5829 <= B5838 and B5831;
B5830 <= (not B5840) or (not B5839);
B5831 <= B5812 or B5813;
B5832 <= B5812 or B5819;
B5833 <= B5811 and B5823;
B5834 <= (not B5810) or (not B5811);
B5835 <= B5819 and B5834;
B5836 <= (not B5835) and (not B5819);
B5837 <= B5819 or B5834;
B5838 <= (not B5812) or (not B5813);
B5839 <= B5819 or B5834;
B5840 <= (not B5819) and (not B5841);
B5841 <= B5819 and B5834;
B5847 <= B5853 and B5852;
B5848 <= B5855 or B5854;
B5849 <= B5857 or B5856;
B5850 <= B5852 and B5858;
B5851 <= B5852 and B5859;
B5852 <= ((not B5842) and B5843) or (B5842 and (not B5843));
B5853 <= ((not B5854) and B5844) or (B5854 and (not B5844));
B5854 <= B5862 and B5861;
B5855 <= B5860 and B5844;
B5856 <= B5865 and B5864;
B5857 <= B5863 and B5844;
B5858 <= B5866 or B5843;
B5859 <= (B5844 and B5856) or ((not B5844) and (not B5856));
B5860 <= (not B5869) or (not B5870);
B5861 <= ((not B5845) and B5852) or (B5845 and (not B5852));
B5862 <= B5871 and B5864;
B5863 <= (not B5873) or (not B5872);
B5864 <= B5845 or B5846;
B5865 <= B5845 or B5852;
B5866 <= B5844 and B5856;
B5867 <= (not B5843) or (not B5844);
B5868 <= B5852 and B5867;
B5869 <= (not B5868) and (not B5852);
B5870 <= B5852 or B5867;
B5871 <= (not B5845) or (not B5846);
B5872 <= B5852 or B5867;
B5873 <= (not B5852) and (not B5874);
B5874 <= B5852 and B5867;
B5880 <= B5886 and B5885;
B5881 <= B5888 or B5887;
B5882 <= B5890 or B5889;
B5883 <= B5885 and B5891;
B5884 <= B5885 and B5892;
B5885 <= ((not B5875) and B5876) or (B5875 and (not B5876));
B5886 <= ((not B5887) and B5877) or (B5887 and (not B5877));
B5887 <= B5895 and B5894;
B5888 <= B5893 and B5877;
B5889 <= B5898 and B5897;
B5890 <= B5896 and B5877;
B5891 <= B5899 or B5876;
B5892 <= (B5877 and B5889) or ((not B5877) and (not B5889));
B5893 <= (not B5902) or (not B5903);
B5894 <= ((not B5878) and B5885) or (B5878 and (not B5885));
B5895 <= B5904 and B5897;
B5896 <= (not B5906) or (not B5905);
B5897 <= B5878 or B5879;
B5898 <= B5878 or B5885;
B5899 <= B5877 and B5889;
B5900 <= (not B5876) or (not B5877);
B5901 <= B5885 and B5900;
B5902 <= (not B5901) and (not B5885);
B5903 <= B5885 or B5900;
B5904 <= (not B5878) or (not B5879);
B5905 <= B5885 or B5900;
B5906 <= (not B5885) and (not B5907);
B5907 <= B5885 and B5900;
B5913 <= B5919 and B5918;
B5914 <= B5921 or B5920;
B5915 <= B5923 or B5922;
B5916 <= B5918 and B5924;
B5917 <= B5918 and B5925;
B5918 <= ((not B5908) and B5909) or (B5908 and (not B5909));
B5919 <= ((not B5920) and B5910) or (B5920 and (not B5910));
B5920 <= B5928 and B5927;
B5921 <= B5926 and B5910;
B5922 <= B5931 and B5930;
B5923 <= B5929 and B5910;
B5924 <= B5932 or B5909;
B5925 <= (B5910 and B5922) or ((not B5910) and (not B5922));
B5926 <= (not B5935) or (not B5936);
B5927 <= ((not B5911) and B5918) or (B5911 and (not B5918));
B5928 <= B5937 and B5930;
B5929 <= (not B5939) or (not B5938);
B5930 <= B5911 or B5912;
B5931 <= B5911 or B5918;
B5932 <= B5910 and B5922;
B5933 <= (not B5909) or (not B5910);
B5934 <= B5918 and B5933;
B5935 <= (not B5934) and (not B5918);
B5936 <= B5918 or B5933;
B5937 <= (not B5911) or (not B5912);
B5938 <= B5918 or B5933;
B5939 <= (not B5918) and (not B5940);
B5940 <= B5918 and B5933;
B5946 <= B5952 and B5951;
B5947 <= B5954 or B5953;
B5948 <= B5956 or B5955;
B5949 <= B5951 and B5957;
B5950 <= B5951 and B5958;
B5951 <= ((not B5941) and B5942) or (B5941 and (not B5942));
B5952 <= ((not B5953) and B5943) or (B5953 and (not B5943));
B5953 <= B5961 and B5960;
B5954 <= B5959 and B5943;
B5955 <= B5964 and B5963;
B5956 <= B5962 and B5943;
B5957 <= B5965 or B5942;
B5958 <= (B5943 and B5955) or ((not B5943) and (not B5955));
B5959 <= (not B5968) or (not B5969);
B5960 <= ((not B5944) and B5951) or (B5944 and (not B5951));
B5961 <= B5970 and B5963;
B5962 <= (not B5972) or (not B5971);
B5963 <= B5944 or B5945;
B5964 <= B5944 or B5951;
B5965 <= B5943 and B5955;
B5966 <= (not B5942) or (not B5943);
B5967 <= B5951 and B5966;
B5968 <= (not B5967) and (not B5951);
B5969 <= B5951 or B5966;
B5970 <= (not B5944) or (not B5945);
B5971 <= B5951 or B5966;
B5972 <= (not B5951) and (not B5973);
B5973 <= B5951 and B5966;
B5979 <= B5985 and B5984;
B5980 <= B5987 or B5986;
B5981 <= B5989 or B5988;
B5982 <= B5984 and B5990;
B5983 <= B5984 and B5991;
B5984 <= ((not B5974) and B5975) or (B5974 and (not B5975));
B5985 <= ((not B5986) and B5976) or (B5986 and (not B5976));
B5986 <= B5994 and B5993;
B5987 <= B5992 and B5976;
B5988 <= B5997 and B5996;
B5989 <= B5995 and B5976;
B5990 <= B5998 or B5975;
B5991 <= (B5976 and B5988) or ((not B5976) and (not B5988));
B5992 <= (not B6001) or (not B6002);
B5993 <= ((not B5977) and B5984) or (B5977 and (not B5984));
B5994 <= B6003 and B5996;
B5995 <= (not B6005) or (not B6004);
B5996 <= B5977 or B5978;
B5997 <= B5977 or B5984;
B5998 <= B5976 and B5988;
B5999 <= (not B5975) or (not B5976);
B6000 <= B5984 and B5999;
B6001 <= (not B6000) and (not B5984);
B6002 <= B5984 or B5999;
B6003 <= (not B5977) or (not B5978);
B6004 <= B5984 or B5999;
B6005 <= (not B5984) and (not B6006);
B6006 <= B5984 and B5999;
B6012 <= B6018 and B6017;
B6013 <= B6020 or B6019;
B6014 <= B6022 or B6021;
B6015 <= B6017 and B6023;
B6016 <= B6017 and B6024;
B6017 <= ((not B6007) and B6008) or (B6007 and (not B6008));
B6018 <= ((not B6019) and B6009) or (B6019 and (not B6009));
B6019 <= B6027 and B6026;
B6020 <= B6025 and B6009;
B6021 <= B6030 and B6029;
B6022 <= B6028 and B6009;
B6023 <= B6031 or B6008;
B6024 <= (B6009 and B6021) or ((not B6009) and (not B6021));
B6025 <= (not B6034) or (not B6035);
B6026 <= ((not B6010) and B6017) or (B6010 and (not B6017));
B6027 <= B6036 and B6029;
B6028 <= (not B6038) or (not B6037);
B6029 <= B6010 or B6011;
B6030 <= B6010 or B6017;
B6031 <= B6009 and B6021;
B6032 <= (not B6008) or (not B6009);
B6033 <= B6017 and B6032;
B6034 <= (not B6033) and (not B6017);
B6035 <= B6017 or B6032;
B6036 <= (not B6010) or (not B6011);
B6037 <= B6017 or B6032;
B6038 <= (not B6017) and (not B6039);
B6039 <= B6017 and B6032;
B6045 <= B6051 and B6050;
B6046 <= B6053 or B6052;
B6047 <= B6055 or B6054;
B6048 <= B6050 and B6056;
B6049 <= B6050 and B6057;
B6050 <= ((not B6040) and B6041) or (B6040 and (not B6041));
B6051 <= ((not B6052) and B6042) or (B6052 and (not B6042));
B6052 <= B6060 and B6059;
B6053 <= B6058 and B6042;
B6054 <= B6063 and B6062;
B6055 <= B6061 and B6042;
B6056 <= B6064 or B6041;
B6057 <= (B6042 and B6054) or ((not B6042) and (not B6054));
B6058 <= (not B6067) or (not B6068);
B6059 <= ((not B6043) and B6050) or (B6043 and (not B6050));
B6060 <= B6069 and B6062;
B6061 <= (not B6071) or (not B6070);
B6062 <= B6043 or B6044;
B6063 <= B6043 or B6050;
B6064 <= B6042 and B6054;
B6065 <= (not B6041) or (not B6042);
B6066 <= B6050 and B6065;
B6067 <= (not B6066) and (not B6050);
B6068 <= B6050 or B6065;
B6069 <= (not B6043) or (not B6044);
B6070 <= B6050 or B6065;
B6071 <= (not B6050) and (not B6072);
B6072 <= B6050 and B6065;
B6078 <= B6084 and B6083;
B6079 <= B6086 or B6085;
B6080 <= B6088 or B6087;
B6081 <= B6083 and B6089;
B6082 <= B6083 and B6090;
B6083 <= ((not B6073) and B6074) or (B6073 and (not B6074));
B6084 <= ((not B6085) and B6075) or (B6085 and (not B6075));
B6085 <= B6093 and B6092;
B6086 <= B6091 and B6075;
B6087 <= B6096 and B6095;
B6088 <= B6094 and B6075;
B6089 <= B6097 or B6074;
B6090 <= (B6075 and B6087) or ((not B6075) and (not B6087));
B6091 <= (not B6100) or (not B6101);
B6092 <= ((not B6076) and B6083) or (B6076 and (not B6083));
B6093 <= B6102 and B6095;
B6094 <= (not B6104) or (not B6103);
B6095 <= B6076 or B6077;
B6096 <= B6076 or B6083;
B6097 <= B6075 and B6087;
B6098 <= (not B6074) or (not B6075);
B6099 <= B6083 and B6098;
B6100 <= (not B6099) and (not B6083);
B6101 <= B6083 or B6098;
B6102 <= (not B6076) or (not B6077);
B6103 <= B6083 or B6098;
B6104 <= (not B6083) and (not B6105);
B6105 <= B6083 and B6098;
B6111 <= B6117 and B6116;
B6112 <= B6119 or B6118;
B6113 <= B6121 or B6120;
B6114 <= B6116 and B6122;
B6115 <= B6116 and B6123;
B6116 <= ((not B6106) and B6107) or (B6106 and (not B6107));
B6117 <= ((not B6118) and B6108) or (B6118 and (not B6108));
B6118 <= B6126 and B6125;
B6119 <= B6124 and B6108;
B6120 <= B6129 and B6128;
B6121 <= B6127 and B6108;
B6122 <= B6130 or B6107;
B6123 <= (B6108 and B6120) or ((not B6108) and (not B6120));
B6124 <= (not B6133) or (not B6134);
B6125 <= ((not B6109) and B6116) or (B6109 and (not B6116));
B6126 <= B6135 and B6128;
B6127 <= (not B6137) or (not B6136);
B6128 <= B6109 or B6110;
B6129 <= B6109 or B6116;
B6130 <= B6108 and B6120;
B6131 <= (not B6107) or (not B6108);
B6132 <= B6116 and B6131;
B6133 <= (not B6132) and (not B6116);
B6134 <= B6116 or B6131;
B6135 <= (not B6109) or (not B6110);
B6136 <= B6116 or B6131;
B6137 <= (not B6116) and (not B6138);
B6138 <= B6116 and B6131;
B6144 <= B6150 and B6149;
B6145 <= B6152 or B6151;
B6146 <= B6154 or B6153;
B6147 <= B6149 and B6155;
B6148 <= B6149 and B6156;
B6149 <= ((not B6139) and B6140) or (B6139 and (not B6140));
B6150 <= ((not B6151) and B6141) or (B6151 and (not B6141));
B6151 <= B6159 and B6158;
B6152 <= B6157 and B6141;
B6153 <= B6162 and B6161;
B6154 <= B6160 and B6141;
B6155 <= B6163 or B6140;
B6156 <= (B6141 and B6153) or ((not B6141) and (not B6153));
B6157 <= (not B6166) or (not B6167);
B6158 <= ((not B6142) and B6149) or (B6142 and (not B6149));
B6159 <= B6168 and B6161;
B6160 <= (not B6170) or (not B6169);
B6161 <= B6142 or B6143;
B6162 <= B6142 or B6149;
B6163 <= B6141 and B6153;
B6164 <= (not B6140) or (not B6141);
B6165 <= B6149 and B6164;
B6166 <= (not B6165) and (not B6149);
B6167 <= B6149 or B6164;
B6168 <= (not B6142) or (not B6143);
B6169 <= B6149 or B6164;
B6170 <= (not B6149) and (not B6171);
B6171 <= B6149 and B6164;
B6177 <= B6183 and B6182;
B6178 <= B6185 or B6184;
B6179 <= B6187 or B6186;
B6180 <= B6182 and B6188;
B6181 <= B6182 and B6189;
B6182 <= ((not B6172) and B6173) or (B6172 and (not B6173));
B6183 <= ((not B6184) and B6174) or (B6184 and (not B6174));
B6184 <= B6192 and B6191;
B6185 <= B6190 and B6174;
B6186 <= B6195 and B6194;
B6187 <= B6193 and B6174;
B6188 <= B6196 or B6173;
B6189 <= (B6174 and B6186) or ((not B6174) and (not B6186));
B6190 <= (not B6199) or (not B6200);
B6191 <= ((not B6175) and B6182) or (B6175 and (not B6182));
B6192 <= B6201 and B6194;
B6193 <= (not B6203) or (not B6202);
B6194 <= B6175 or B6176;
B6195 <= B6175 or B6182;
B6196 <= B6174 and B6186;
B6197 <= (not B6173) or (not B6174);
B6198 <= B6182 and B6197;
B6199 <= (not B6198) and (not B6182);
B6200 <= B6182 or B6197;
B6201 <= (not B6175) or (not B6176);
B6202 <= B6182 or B6197;
B6203 <= (not B6182) and (not B6204);
B6204 <= B6182 and B6197;
B6210 <= B6216 and B6215;
B6211 <= B6218 or B6217;
B6212 <= B6220 or B6219;
B6213 <= B6215 and B6221;
B6214 <= B6215 and B6222;
B6215 <= ((not B6205) and B6206) or (B6205 and (not B6206));
B6216 <= ((not B6217) and B6207) or (B6217 and (not B6207));
B6217 <= B6225 and B6224;
B6218 <= B6223 and B6207;
B6219 <= B6228 and B6227;
B6220 <= B6226 and B6207;
B6221 <= B6229 or B6206;
B6222 <= (B6207 and B6219) or ((not B6207) and (not B6219));
B6223 <= (not B6232) or (not B6233);
B6224 <= ((not B6208) and B6215) or (B6208 and (not B6215));
B6225 <= B6234 and B6227;
B6226 <= (not B6236) or (not B6235);
B6227 <= B6208 or B6209;
B6228 <= B6208 or B6215;
B6229 <= B6207 and B6219;
B6230 <= (not B6206) or (not B6207);
B6231 <= B6215 and B6230;
B6232 <= (not B6231) and (not B6215);
B6233 <= B6215 or B6230;
B6234 <= (not B6208) or (not B6209);
B6235 <= B6215 or B6230;
B6236 <= (not B6215) and (not B6237);
B6237 <= B6215 and B6230;
B6243 <= B6249 and B6248;
B6244 <= B6251 or B6250;
B6245 <= B6253 or B6252;
B6246 <= B6248 and B6254;
B6247 <= B6248 and B6255;
B6248 <= ((not B6238) and B6239) or (B6238 and (not B6239));
B6249 <= ((not B6250) and B6240) or (B6250 and (not B6240));
B6250 <= B6258 and B6257;
B6251 <= B6256 and B6240;
B6252 <= B6261 and B6260;
B6253 <= B6259 and B6240;
B6254 <= B6262 or B6239;
B6255 <= (B6240 and B6252) or ((not B6240) and (not B6252));
B6256 <= (not B6265) or (not B6266);
B6257 <= ((not B6241) and B6248) or (B6241 and (not B6248));
B6258 <= B6267 and B6260;
B6259 <= (not B6269) or (not B6268);
B6260 <= B6241 or B6242;
B6261 <= B6241 or B6248;
B6262 <= B6240 and B6252;
B6263 <= (not B6239) or (not B6240);
B6264 <= B6248 and B6263;
B6265 <= (not B6264) and (not B6248);
B6266 <= B6248 or B6263;
B6267 <= (not B6241) or (not B6242);
B6268 <= B6248 or B6263;
B6269 <= (not B6248) and (not B6270);
B6270 <= B6248 and B6263;
B6276 <= B6282 and B6281;
B6277 <= B6284 or B6283;
B6278 <= B6286 or B6285;
B6279 <= B6281 and B6287;
B6280 <= B6281 and B6288;
B6281 <= ((not B6271) and B6272) or (B6271 and (not B6272));
B6282 <= ((not B6283) and B6273) or (B6283 and (not B6273));
B6283 <= B6291 and B6290;
B6284 <= B6289 and B6273;
B6285 <= B6294 and B6293;
B6286 <= B6292 and B6273;
B6287 <= B6295 or B6272;
B6288 <= (B6273 and B6285) or ((not B6273) and (not B6285));
B6289 <= (not B6298) or (not B6299);
B6290 <= ((not B6274) and B6281) or (B6274 and (not B6281));
B6291 <= B6300 and B6293;
B6292 <= (not B6302) or (not B6301);
B6293 <= B6274 or B6275;
B6294 <= B6274 or B6281;
B6295 <= B6273 and B6285;
B6296 <= (not B6272) or (not B6273);
B6297 <= B6281 and B6296;
B6298 <= (not B6297) and (not B6281);
B6299 <= B6281 or B6296;
B6300 <= (not B6274) or (not B6275);
B6301 <= B6281 or B6296;
B6302 <= (not B6281) and (not B6303);
B6303 <= B6281 and B6296;
B6309 <= B6315 and B6314;
B6310 <= B6317 or B6316;
B6311 <= B6319 or B6318;
B6312 <= B6314 and B6320;
B6313 <= B6314 and B6321;
B6314 <= ((not B6304) and B6305) or (B6304 and (not B6305));
B6315 <= ((not B6316) and B6306) or (B6316 and (not B6306));
B6316 <= B6324 and B6323;
B6317 <= B6322 and B6306;
B6318 <= B6327 and B6326;
B6319 <= B6325 and B6306;
B6320 <= B6328 or B6305;
B6321 <= (B6306 and B6318) or ((not B6306) and (not B6318));
B6322 <= (not B6331) or (not B6332);
B6323 <= ((not B6307) and B6314) or (B6307 and (not B6314));
B6324 <= B6333 and B6326;
B6325 <= (not B6335) or (not B6334);
B6326 <= B6307 or B6308;
B6327 <= B6307 or B6314;
B6328 <= B6306 and B6318;
B6329 <= (not B6305) or (not B6306);
B6330 <= B6314 and B6329;
B6331 <= (not B6330) and (not B6314);
B6332 <= B6314 or B6329;
B6333 <= (not B6307) or (not B6308);
B6334 <= B6314 or B6329;
B6335 <= (not B6314) and (not B6336);
B6336 <= B6314 and B6329;
B6342 <= B6348 and B6347;
B6343 <= B6350 or B6349;
B6344 <= B6352 or B6351;
B6345 <= B6347 and B6353;
B6346 <= B6347 and B6354;
B6347 <= ((not B6337) and B6338) or (B6337 and (not B6338));
B6348 <= ((not B6349) and B6339) or (B6349 and (not B6339));
B6349 <= B6357 and B6356;
B6350 <= B6355 and B6339;
B6351 <= B6360 and B6359;
B6352 <= B6358 and B6339;
B6353 <= B6361 or B6338;
B6354 <= (B6339 and B6351) or ((not B6339) and (not B6351));
B6355 <= (not B6364) or (not B6365);
B6356 <= ((not B6340) and B6347) or (B6340 and (not B6347));
B6357 <= B6366 and B6359;
B6358 <= (not B6368) or (not B6367);
B6359 <= B6340 or B6341;
B6360 <= B6340 or B6347;
B6361 <= B6339 and B6351;
B6362 <= (not B6338) or (not B6339);
B6363 <= B6347 and B6362;
B6364 <= (not B6363) and (not B6347);
B6365 <= B6347 or B6362;
B6366 <= (not B6340) or (not B6341);
B6367 <= B6347 or B6362;
B6368 <= (not B6347) and (not B6369);
B6369 <= B6347 and B6362;
B6375 <= B6381 and B6380;
B6376 <= B6383 or B6382;
B6377 <= B6385 or B6384;
B6378 <= B6380 and B6386;
B6379 <= B6380 and B6387;
B6380 <= ((not B6370) and B6371) or (B6370 and (not B6371));
B6381 <= ((not B6382) and B6372) or (B6382 and (not B6372));
B6382 <= B6390 and B6389;
B6383 <= B6388 and B6372;
B6384 <= B6393 and B6392;
B6385 <= B6391 and B6372;
B6386 <= B6394 or B6371;
B6387 <= (B6372 and B6384) or ((not B6372) and (not B6384));
B6388 <= (not B6397) or (not B6398);
B6389 <= ((not B6373) and B6380) or (B6373 and (not B6380));
B6390 <= B6399 and B6392;
B6391 <= (not B6401) or (not B6400);
B6392 <= B6373 or B6374;
B6393 <= B6373 or B6380;
B6394 <= B6372 and B6384;
B6395 <= (not B6371) or (not B6372);
B6396 <= B6380 and B6395;
B6397 <= (not B6396) and (not B6380);
B6398 <= B6380 or B6395;
B6399 <= (not B6373) or (not B6374);
B6400 <= B6380 or B6395;
B6401 <= (not B6380) and (not B6402);
B6402 <= B6380 and B6395;
B6408 <= B6414 and B6413;
B6409 <= B6416 or B6415;
B6410 <= B6418 or B6417;
B6411 <= B6413 and B6419;
B6412 <= B6413 and B6420;
B6413 <= ((not B6403) and B6404) or (B6403 and (not B6404));
B6414 <= ((not B6415) and B6405) or (B6415 and (not B6405));
B6415 <= B6423 and B6422;
B6416 <= B6421 and B6405;
B6417 <= B6426 and B6425;
B6418 <= B6424 and B6405;
B6419 <= B6427 or B6404;
B6420 <= (B6405 and B6417) or ((not B6405) and (not B6417));
B6421 <= (not B6430) or (not B6431);
B6422 <= ((not B6406) and B6413) or (B6406 and (not B6413));
B6423 <= B6432 and B6425;
B6424 <= (not B6434) or (not B6433);
B6425 <= B6406 or B6407;
B6426 <= B6406 or B6413;
B6427 <= B6405 and B6417;
B6428 <= (not B6404) or (not B6405);
B6429 <= B6413 and B6428;
B6430 <= (not B6429) and (not B6413);
B6431 <= B6413 or B6428;
B6432 <= (not B6406) or (not B6407);
B6433 <= B6413 or B6428;
B6434 <= (not B6413) and (not B6435);
B6435 <= B6413 and B6428;
B6441 <= B6447 and B6446;
B6442 <= B6449 or B6448;
B6443 <= B6451 or B6450;
B6444 <= B6446 and B6452;
B6445 <= B6446 and B6453;
B6446 <= ((not B6436) and B6437) or (B6436 and (not B6437));
B6447 <= ((not B6448) and B6438) or (B6448 and (not B6438));
B6448 <= B6456 and B6455;
B6449 <= B6454 and B6438;
B6450 <= B6459 and B6458;
B6451 <= B6457 and B6438;
B6452 <= B6460 or B6437;
B6453 <= (B6438 and B6450) or ((not B6438) and (not B6450));
B6454 <= (not B6463) or (not B6464);
B6455 <= ((not B6439) and B6446) or (B6439 and (not B6446));
B6456 <= B6465 and B6458;
B6457 <= (not B6467) or (not B6466);
B6458 <= B6439 or B6440;
B6459 <= B6439 or B6446;
B6460 <= B6438 and B6450;
B6461 <= (not B6437) or (not B6438);
B6462 <= B6446 and B6461;
B6463 <= (not B6462) and (not B6446);
B6464 <= B6446 or B6461;
B6465 <= (not B6439) or (not B6440);
B6466 <= B6446 or B6461;
B6467 <= (not B6446) and (not B6468);
B6468 <= B6446 and B6461;
B6474 <= B6480 and B6479;
B6475 <= B6482 or B6481;
B6476 <= B6484 or B6483;
B6477 <= B6479 and B6485;
B6478 <= B6479 and B6486;
B6479 <= ((not B6469) and B6470) or (B6469 and (not B6470));
B6480 <= ((not B6481) and B6471) or (B6481 and (not B6471));
B6481 <= B6489 and B6488;
B6482 <= B6487 and B6471;
B6483 <= B6492 and B6491;
B6484 <= B6490 and B6471;
B6485 <= B6493 or B6470;
B6486 <= (B6471 and B6483) or ((not B6471) and (not B6483));
B6487 <= (not B6496) or (not B6497);
B6488 <= ((not B6472) and B6479) or (B6472 and (not B6479));
B6489 <= B6498 and B6491;
B6490 <= (not B6500) or (not B6499);
B6491 <= B6472 or B6473;
B6492 <= B6472 or B6479;
B6493 <= B6471 and B6483;
B6494 <= (not B6470) or (not B6471);
B6495 <= B6479 and B6494;
B6496 <= (not B6495) and (not B6479);
B6497 <= B6479 or B6494;
B6498 <= (not B6472) or (not B6473);
B6499 <= B6479 or B6494;
B6500 <= (not B6479) and (not B6501);
B6501 <= B6479 and B6494;
B6507 <= B6513 and B6512;
B6508 <= B6515 or B6514;
B6509 <= B6517 or B6516;
B6510 <= B6512 and B6518;
B6511 <= B6512 and B6519;
B6512 <= ((not B6502) and B6503) or (B6502 and (not B6503));
B6513 <= ((not B6514) and B6504) or (B6514 and (not B6504));
B6514 <= B6522 and B6521;
B6515 <= B6520 and B6504;
B6516 <= B6525 and B6524;
B6517 <= B6523 and B6504;
B6518 <= B6526 or B6503;
B6519 <= (B6504 and B6516) or ((not B6504) and (not B6516));
B6520 <= (not B6529) or (not B6530);
B6521 <= ((not B6505) and B6512) or (B6505 and (not B6512));
B6522 <= B6531 and B6524;
B6523 <= (not B6533) or (not B6532);
B6524 <= B6505 or B6506;
B6525 <= B6505 or B6512;
B6526 <= B6504 and B6516;
B6527 <= (not B6503) or (not B6504);
B6528 <= B6512 and B6527;
B6529 <= (not B6528) and (not B6512);
B6530 <= B6512 or B6527;
B6531 <= (not B6505) or (not B6506);
B6532 <= B6512 or B6527;
B6533 <= (not B6512) and (not B6534);
B6534 <= B6512 and B6527;
B6540 <= B6546 and B6545;
B6541 <= B6548 or B6547;
B6542 <= B6550 or B6549;
B6543 <= B6545 and B6551;
B6544 <= B6545 and B6552;
B6545 <= ((not B6535) and B6536) or (B6535 and (not B6536));
B6546 <= ((not B6547) and B6537) or (B6547 and (not B6537));
B6547 <= B6555 and B6554;
B6548 <= B6553 and B6537;
B6549 <= B6558 and B6557;
B6550 <= B6556 and B6537;
B6551 <= B6559 or B6536;
B6552 <= (B6537 and B6549) or ((not B6537) and (not B6549));
B6553 <= (not B6562) or (not B6563);
B6554 <= ((not B6538) and B6545) or (B6538 and (not B6545));
B6555 <= B6564 and B6557;
B6556 <= (not B6566) or (not B6565);
B6557 <= B6538 or B6539;
B6558 <= B6538 or B6545;
B6559 <= B6537 and B6549;
B6560 <= (not B6536) or (not B6537);
B6561 <= B6545 and B6560;
B6562 <= (not B6561) and (not B6545);
B6563 <= B6545 or B6560;
B6564 <= (not B6538) or (not B6539);
B6565 <= B6545 or B6560;
B6566 <= (not B6545) and (not B6567);
B6567 <= B6545 and B6560;
B6573 <= B6579 and B6578;
B6574 <= B6581 or B6580;
B6575 <= B6583 or B6582;
B6576 <= B6578 and B6584;
B6577 <= B6578 and B6585;
B6578 <= ((not B6568) and B6569) or (B6568 and (not B6569));
B6579 <= ((not B6580) and B6570) or (B6580 and (not B6570));
B6580 <= B6588 and B6587;
B6581 <= B6586 and B6570;
B6582 <= B6591 and B6590;
B6583 <= B6589 and B6570;
B6584 <= B6592 or B6569;
B6585 <= (B6570 and B6582) or ((not B6570) and (not B6582));
B6586 <= (not B6595) or (not B6596);
B6587 <= ((not B6571) and B6578) or (B6571 and (not B6578));
B6588 <= B6597 and B6590;
B6589 <= (not B6599) or (not B6598);
B6590 <= B6571 or B6572;
B6591 <= B6571 or B6578;
B6592 <= B6570 and B6582;
B6593 <= (not B6569) or (not B6570);
B6594 <= B6578 and B6593;
B6595 <= (not B6594) and (not B6578);
B6596 <= B6578 or B6593;
B6597 <= (not B6571) or (not B6572);
B6598 <= B6578 or B6593;
B6599 <= (not B6578) and (not B6600);
B6600 <= B6578 and B6593;
B6606 <= B6612 and B6611;
B6607 <= B6614 or B6613;
B6608 <= B6616 or B6615;
B6609 <= B6611 and B6617;
B6610 <= B6611 and B6618;
B6611 <= ((not B6601) and B6602) or (B6601 and (not B6602));
B6612 <= ((not B6613) and B6603) or (B6613 and (not B6603));
B6613 <= B6621 and B6620;
B6614 <= B6619 and B6603;
B6615 <= B6624 and B6623;
B6616 <= B6622 and B6603;
B6617 <= B6625 or B6602;
B6618 <= (B6603 and B6615) or ((not B6603) and (not B6615));
B6619 <= (not B6628) or (not B6629);
B6620 <= ((not B6604) and B6611) or (B6604 and (not B6611));
B6621 <= B6630 and B6623;
B6622 <= (not B6632) or (not B6631);
B6623 <= B6604 or B6605;
B6624 <= B6604 or B6611;
B6625 <= B6603 and B6615;
B6626 <= (not B6602) or (not B6603);
B6627 <= B6611 and B6626;
B6628 <= (not B6627) and (not B6611);
B6629 <= B6611 or B6626;
B6630 <= (not B6604) or (not B6605);
B6631 <= B6611 or B6626;
B6632 <= (not B6611) and (not B6633);
B6633 <= B6611 and B6626;
B6639 <= B6645 and B6644;
B6640 <= B6647 or B6646;
B6641 <= B6649 or B6648;
B6642 <= B6644 and B6650;
B6643 <= B6644 and B6651;
B6644 <= ((not B6634) and B6635) or (B6634 and (not B6635));
B6645 <= ((not B6646) and B6636) or (B6646 and (not B6636));
B6646 <= B6654 and B6653;
B6647 <= B6652 and B6636;
B6648 <= B6657 and B6656;
B6649 <= B6655 and B6636;
B6650 <= B6658 or B6635;
B6651 <= (B6636 and B6648) or ((not B6636) and (not B6648));
B6652 <= (not B6661) or (not B6662);
B6653 <= ((not B6637) and B6644) or (B6637 and (not B6644));
B6654 <= B6663 and B6656;
B6655 <= (not B6665) or (not B6664);
B6656 <= B6637 or B6638;
B6657 <= B6637 or B6644;
B6658 <= B6636 and B6648;
B6659 <= (not B6635) or (not B6636);
B6660 <= B6644 and B6659;
B6661 <= (not B6660) and (not B6644);
B6662 <= B6644 or B6659;
B6663 <= (not B6637) or (not B6638);
B6664 <= B6644 or B6659;
B6665 <= (not B6644) and (not B6666);
B6666 <= B6644 and B6659;
B6672 <= B6678 and B6677;
B6673 <= B6680 or B6679;
B6674 <= B6682 or B6681;
B6675 <= B6677 and B6683;
B6676 <= B6677 and B6684;
B6677 <= ((not B6667) and B6668) or (B6667 and (not B6668));
B6678 <= ((not B6679) and B6669) or (B6679 and (not B6669));
B6679 <= B6687 and B6686;
B6680 <= B6685 and B6669;
B6681 <= B6690 and B6689;
B6682 <= B6688 and B6669;
B6683 <= B6691 or B6668;
B6684 <= (B6669 and B6681) or ((not B6669) and (not B6681));
B6685 <= (not B6694) or (not B6695);
B6686 <= ((not B6670) and B6677) or (B6670 and (not B6677));
B6687 <= B6696 and B6689;
B6688 <= (not B6698) or (not B6697);
B6689 <= B6670 or B6671;
B6690 <= B6670 or B6677;
B6691 <= B6669 and B6681;
B6692 <= (not B6668) or (not B6669);
B6693 <= B6677 and B6692;
B6694 <= (not B6693) and (not B6677);
B6695 <= B6677 or B6692;
B6696 <= (not B6670) or (not B6671);
B6697 <= B6677 or B6692;
B6698 <= (not B6677) and (not B6699);
B6699 <= B6677 and B6692;
B6705 <= B6711 and B6710;
B6706 <= B6713 or B6712;
B6707 <= B6715 or B6714;
B6708 <= B6710 and B6716;
B6709 <= B6710 and B6717;
B6710 <= ((not B6700) and B6701) or (B6700 and (not B6701));
B6711 <= ((not B6712) and B6702) or (B6712 and (not B6702));
B6712 <= B6720 and B6719;
B6713 <= B6718 and B6702;
B6714 <= B6723 and B6722;
B6715 <= B6721 and B6702;
B6716 <= B6724 or B6701;
B6717 <= (B6702 and B6714) or ((not B6702) and (not B6714));
B6718 <= (not B6727) or (not B6728);
B6719 <= ((not B6703) and B6710) or (B6703 and (not B6710));
B6720 <= B6729 and B6722;
B6721 <= (not B6731) or (not B6730);
B6722 <= B6703 or B6704;
B6723 <= B6703 or B6710;
B6724 <= B6702 and B6714;
B6725 <= (not B6701) or (not B6702);
B6726 <= B6710 and B6725;
B6727 <= (not B6726) and (not B6710);
B6728 <= B6710 or B6725;
B6729 <= (not B6703) or (not B6704);
B6730 <= B6710 or B6725;
B6731 <= (not B6710) and (not B6732);
B6732 <= B6710 and B6725;
B6738 <= B6744 and B6743;
B6739 <= B6746 or B6745;
B6740 <= B6748 or B6747;
B6741 <= B6743 and B6749;
B6742 <= B6743 and B6750;
B6743 <= ((not B6733) and B6734) or (B6733 and (not B6734));
B6744 <= ((not B6745) and B6735) or (B6745 and (not B6735));
B6745 <= B6753 and B6752;
B6746 <= B6751 and B6735;
B6747 <= B6756 and B6755;
B6748 <= B6754 and B6735;
B6749 <= B6757 or B6734;
B6750 <= (B6735 and B6747) or ((not B6735) and (not B6747));
B6751 <= (not B6760) or (not B6761);
B6752 <= ((not B6736) and B6743) or (B6736 and (not B6743));
B6753 <= B6762 and B6755;
B6754 <= (not B6764) or (not B6763);
B6755 <= B6736 or B6737;
B6756 <= B6736 or B6743;
B6757 <= B6735 and B6747;
B6758 <= (not B6734) or (not B6735);
B6759 <= B6743 and B6758;
B6760 <= (not B6759) and (not B6743);
B6761 <= B6743 or B6758;
B6762 <= (not B6736) or (not B6737);
B6763 <= B6743 or B6758;
B6764 <= (not B6743) and (not B6765);
B6765 <= B6743 and B6758;
B6771 <= B6777 and B6776;
B6772 <= B6779 or B6778;
B6773 <= B6781 or B6780;
B6774 <= B6776 and B6782;
B6775 <= B6776 and B6783;
B6776 <= ((not B6766) and B6767) or (B6766 and (not B6767));
B6777 <= ((not B6778) and B6768) or (B6778 and (not B6768));
B6778 <= B6786 and B6785;
B6779 <= B6784 and B6768;
B6780 <= B6789 and B6788;
B6781 <= B6787 and B6768;
B6782 <= B6790 or B6767;
B6783 <= (B6768 and B6780) or ((not B6768) and (not B6780));
B6784 <= (not B6793) or (not B6794);
B6785 <= ((not B6769) and B6776) or (B6769 and (not B6776));
B6786 <= B6795 and B6788;
B6787 <= (not B6797) or (not B6796);
B6788 <= B6769 or B6770;
B6789 <= B6769 or B6776;
B6790 <= B6768 and B6780;
B6791 <= (not B6767) or (not B6768);
B6792 <= B6776 and B6791;
B6793 <= (not B6792) and (not B6776);
B6794 <= B6776 or B6791;
B6795 <= (not B6769) or (not B6770);
B6796 <= B6776 or B6791;
B6797 <= (not B6776) and (not B6798);
B6798 <= B6776 and B6791;
B6804 <= B6810 and B6809;
B6805 <= B6812 or B6811;
B6806 <= B6814 or B6813;
B6807 <= B6809 and B6815;
B6808 <= B6809 and B6816;
B6809 <= ((not B6799) and B6800) or (B6799 and (not B6800));
B6810 <= ((not B6811) and B6801) or (B6811 and (not B6801));
B6811 <= B6819 and B6818;
B6812 <= B6817 and B6801;
B6813 <= B6822 and B6821;
B6814 <= B6820 and B6801;
B6815 <= B6823 or B6800;
B6816 <= (B6801 and B6813) or ((not B6801) and (not B6813));
B6817 <= (not B6826) or (not B6827);
B6818 <= ((not B6802) and B6809) or (B6802 and (not B6809));
B6819 <= B6828 and B6821;
B6820 <= (not B6830) or (not B6829);
B6821 <= B6802 or B6803;
B6822 <= B6802 or B6809;
B6823 <= B6801 and B6813;
B6824 <= (not B6800) or (not B6801);
B6825 <= B6809 and B6824;
B6826 <= (not B6825) and (not B6809);
B6827 <= B6809 or B6824;
B6828 <= (not B6802) or (not B6803);
B6829 <= B6809 or B6824;
B6830 <= (not B6809) and (not B6831);
B6831 <= B6809 and B6824;
B6837 <= B6843 and B6842;
B6838 <= B6845 or B6844;
B6839 <= B6847 or B6846;
B6840 <= B6842 and B6848;
B6841 <= B6842 and B6849;
B6842 <= ((not B6832) and B6833) or (B6832 and (not B6833));
B6843 <= ((not B6844) and B6834) or (B6844 and (not B6834));
B6844 <= B6852 and B6851;
B6845 <= B6850 and B6834;
B6846 <= B6855 and B6854;
B6847 <= B6853 and B6834;
B6848 <= B6856 or B6833;
B6849 <= (B6834 and B6846) or ((not B6834) and (not B6846));
B6850 <= (not B6859) or (not B6860);
B6851 <= ((not B6835) and B6842) or (B6835 and (not B6842));
B6852 <= B6861 and B6854;
B6853 <= (not B6863) or (not B6862);
B6854 <= B6835 or B6836;
B6855 <= B6835 or B6842;
B6856 <= B6834 and B6846;
B6857 <= (not B6833) or (not B6834);
B6858 <= B6842 and B6857;
B6859 <= (not B6858) and (not B6842);
B6860 <= B6842 or B6857;
B6861 <= (not B6835) or (not B6836);
B6862 <= B6842 or B6857;
B6863 <= (not B6842) and (not B6864);
B6864 <= B6842 and B6857;
B6870 <= B6876 and B6875;
B6871 <= B6878 or B6877;
B6872 <= B6880 or B6879;
B6873 <= B6875 and B6881;
B6874 <= B6875 and B6882;
B6875 <= ((not B6865) and B6866) or (B6865 and (not B6866));
B6876 <= ((not B6877) and B6867) or (B6877 and (not B6867));
B6877 <= B6885 and B6884;
B6878 <= B6883 and B6867;
B6879 <= B6888 and B6887;
B6880 <= B6886 and B6867;
B6881 <= B6889 or B6866;
B6882 <= (B6867 and B6879) or ((not B6867) and (not B6879));
B6883 <= (not B6892) or (not B6893);
B6884 <= ((not B6868) and B6875) or (B6868 and (not B6875));
B6885 <= B6894 and B6887;
B6886 <= (not B6896) or (not B6895);
B6887 <= B6868 or B6869;
B6888 <= B6868 or B6875;
B6889 <= B6867 and B6879;
B6890 <= (not B6866) or (not B6867);
B6891 <= B6875 and B6890;
B6892 <= (not B6891) and (not B6875);
B6893 <= B6875 or B6890;
B6894 <= (not B6868) or (not B6869);
B6895 <= B6875 or B6890;
B6896 <= (not B6875) and (not B6897);
B6897 <= B6875 and B6890;
B6903 <= B6909 and B6908;
B6904 <= B6911 or B6910;
B6905 <= B6913 or B6912;
B6906 <= B6908 and B6914;
B6907 <= B6908 and B6915;
B6908 <= ((not B6898) and B6899) or (B6898 and (not B6899));
B6909 <= ((not B6910) and B6900) or (B6910 and (not B6900));
B6910 <= B6918 and B6917;
B6911 <= B6916 and B6900;
B6912 <= B6921 and B6920;
B6913 <= B6919 and B6900;
B6914 <= B6922 or B6899;
B6915 <= (B6900 and B6912) or ((not B6900) and (not B6912));
B6916 <= (not B6925) or (not B6926);
B6917 <= ((not B6901) and B6908) or (B6901 and (not B6908));
B6918 <= B6927 and B6920;
B6919 <= (not B6929) or (not B6928);
B6920 <= B6901 or B6902;
B6921 <= B6901 or B6908;
B6922 <= B6900 and B6912;
B6923 <= (not B6899) or (not B6900);
B6924 <= B6908 and B6923;
B6925 <= (not B6924) and (not B6908);
B6926 <= B6908 or B6923;
B6927 <= (not B6901) or (not B6902);
B6928 <= B6908 or B6923;
B6929 <= (not B6908) and (not B6930);
B6930 <= B6908 and B6923;
B6936 <= B6942 and B6941;
B6937 <= B6944 or B6943;
B6938 <= B6946 or B6945;
B6939 <= B6941 and B6947;
B6940 <= B6941 and B6948;
B6941 <= ((not B6931) and B6932) or (B6931 and (not B6932));
B6942 <= ((not B6943) and B6933) or (B6943 and (not B6933));
B6943 <= B6951 and B6950;
B6944 <= B6949 and B6933;
B6945 <= B6954 and B6953;
B6946 <= B6952 and B6933;
B6947 <= B6955 or B6932;
B6948 <= (B6933 and B6945) or ((not B6933) and (not B6945));
B6949 <= (not B6958) or (not B6959);
B6950 <= ((not B6934) and B6941) or (B6934 and (not B6941));
B6951 <= B6960 and B6953;
B6952 <= (not B6962) or (not B6961);
B6953 <= B6934 or B6935;
B6954 <= B6934 or B6941;
B6955 <= B6933 and B6945;
B6956 <= (not B6932) or (not B6933);
B6957 <= B6941 and B6956;
B6958 <= (not B6957) and (not B6941);
B6959 <= B6941 or B6956;
B6960 <= (not B6934) or (not B6935);
B6961 <= B6941 or B6956;
B6962 <= (not B6941) and (not B6963);
B6963 <= B6941 and B6956;
B6969 <= B6975 and B6974;
B6970 <= B6977 or B6976;
B6971 <= B6979 or B6978;
B6972 <= B6974 and B6980;
B6973 <= B6974 and B6981;
B6974 <= ((not B6964) and B6965) or (B6964 and (not B6965));
B6975 <= ((not B6976) and B6966) or (B6976 and (not B6966));
B6976 <= B6984 and B6983;
B6977 <= B6982 and B6966;
B6978 <= B6987 and B6986;
B6979 <= B6985 and B6966;
B6980 <= B6988 or B6965;
B6981 <= (B6966 and B6978) or ((not B6966) and (not B6978));
B6982 <= (not B6991) or (not B6992);
B6983 <= ((not B6967) and B6974) or (B6967 and (not B6974));
B6984 <= B6993 and B6986;
B6985 <= (not B6995) or (not B6994);
B6986 <= B6967 or B6968;
B6987 <= B6967 or B6974;
B6988 <= B6966 and B6978;
B6989 <= (not B6965) or (not B6966);
B6990 <= B6974 and B6989;
B6991 <= (not B6990) and (not B6974);
B6992 <= B6974 or B6989;
B6993 <= (not B6967) or (not B6968);
B6994 <= B6974 or B6989;
B6995 <= (not B6974) and (not B6996);
B6996 <= B6974 and B6989;
B7002 <= B7008 and B7007;
B7003 <= B7010 or B7009;
B7004 <= B7012 or B7011;
B7005 <= B7007 and B7013;
B7006 <= B7007 and B7014;
B7007 <= ((not B6997) and B6998) or (B6997 and (not B6998));
B7008 <= ((not B7009) and B6999) or (B7009 and (not B6999));
B7009 <= B7017 and B7016;
B7010 <= B7015 and B6999;
B7011 <= B7020 and B7019;
B7012 <= B7018 and B6999;
B7013 <= B7021 or B6998;
B7014 <= (B6999 and B7011) or ((not B6999) and (not B7011));
B7015 <= (not B7024) or (not B7025);
B7016 <= ((not B7000) and B7007) or (B7000 and (not B7007));
B7017 <= B7026 and B7019;
B7018 <= (not B7028) or (not B7027);
B7019 <= B7000 or B7001;
B7020 <= B7000 or B7007;
B7021 <= B6999 and B7011;
B7022 <= (not B6998) or (not B6999);
B7023 <= B7007 and B7022;
B7024 <= (not B7023) and (not B7007);
B7025 <= B7007 or B7022;
B7026 <= (not B7000) or (not B7001);
B7027 <= B7007 or B7022;
B7028 <= (not B7007) and (not B7029);
B7029 <= B7007 and B7022;
B7035 <= B7041 and B7040;
B7036 <= B7043 or B7042;
B7037 <= B7045 or B7044;
B7038 <= B7040 and B7046;
B7039 <= B7040 and B7047;
B7040 <= ((not B7030) and B7031) or (B7030 and (not B7031));
B7041 <= ((not B7042) and B7032) or (B7042 and (not B7032));
B7042 <= B7050 and B7049;
B7043 <= B7048 and B7032;
B7044 <= B7053 and B7052;
B7045 <= B7051 and B7032;
B7046 <= B7054 or B7031;
B7047 <= (B7032 and B7044) or ((not B7032) and (not B7044));
B7048 <= (not B7057) or (not B7058);
B7049 <= ((not B7033) and B7040) or (B7033 and (not B7040));
B7050 <= B7059 and B7052;
B7051 <= (not B7061) or (not B7060);
B7052 <= B7033 or B7034;
B7053 <= B7033 or B7040;
B7054 <= B7032 and B7044;
B7055 <= (not B7031) or (not B7032);
B7056 <= B7040 and B7055;
B7057 <= (not B7056) and (not B7040);
B7058 <= B7040 or B7055;
B7059 <= (not B7033) or (not B7034);
B7060 <= B7040 or B7055;
B7061 <= (not B7040) and (not B7062);
B7062 <= B7040 and B7055;
B7068 <= B7074 and B7073;
B7069 <= B7076 or B7075;
B7070 <= B7078 or B7077;
B7071 <= B7073 and B7079;
B7072 <= B7073 and B7080;
B7073 <= ((not B7063) and B7064) or (B7063 and (not B7064));
B7074 <= ((not B7075) and B7065) or (B7075 and (not B7065));
B7075 <= B7083 and B7082;
B7076 <= B7081 and B7065;
B7077 <= B7086 and B7085;
B7078 <= B7084 and B7065;
B7079 <= B7087 or B7064;
B7080 <= (B7065 and B7077) or ((not B7065) and (not B7077));
B7081 <= (not B7090) or (not B7091);
B7082 <= ((not B7066) and B7073) or (B7066 and (not B7073));
B7083 <= B7092 and B7085;
B7084 <= (not B7094) or (not B7093);
B7085 <= B7066 or B7067;
B7086 <= B7066 or B7073;
B7087 <= B7065 and B7077;
B7088 <= (not B7064) or (not B7065);
B7089 <= B7073 and B7088;
B7090 <= (not B7089) and (not B7073);
B7091 <= B7073 or B7088;
B7092 <= (not B7066) or (not B7067);
B7093 <= B7073 or B7088;
B7094 <= (not B7073) and (not B7095);
B7095 <= B7073 and B7088;
B7101 <= B7107 and B7106;
B7102 <= B7109 or B7108;
B7103 <= B7111 or B7110;
B7104 <= B7106 and B7112;
B7105 <= B7106 and B7113;
B7106 <= ((not B7096) and B7097) or (B7096 and (not B7097));
B7107 <= ((not B7108) and B7098) or (B7108 and (not B7098));
B7108 <= B7116 and B7115;
B7109 <= B7114 and B7098;
B7110 <= B7119 and B7118;
B7111 <= B7117 and B7098;
B7112 <= B7120 or B7097;
B7113 <= (B7098 and B7110) or ((not B7098) and (not B7110));
B7114 <= (not B7123) or (not B7124);
B7115 <= ((not B7099) and B7106) or (B7099 and (not B7106));
B7116 <= B7125 and B7118;
B7117 <= (not B7127) or (not B7126);
B7118 <= B7099 or B7100;
B7119 <= B7099 or B7106;
B7120 <= B7098 and B7110;
B7121 <= (not B7097) or (not B7098);
B7122 <= B7106 and B7121;
B7123 <= (not B7122) and (not B7106);
B7124 <= B7106 or B7121;
B7125 <= (not B7099) or (not B7100);
B7126 <= B7106 or B7121;
B7127 <= (not B7106) and (not B7128);
B7128 <= B7106 and B7121;
B7134 <= B7140 and B7139;
B7135 <= B7142 or B7141;
B7136 <= B7144 or B7143;
B7137 <= B7139 and B7145;
B7138 <= B7139 and B7146;
B7139 <= ((not B7129) and B7130) or (B7129 and (not B7130));
B7140 <= ((not B7141) and B7131) or (B7141 and (not B7131));
B7141 <= B7149 and B7148;
B7142 <= B7147 and B7131;
B7143 <= B7152 and B7151;
B7144 <= B7150 and B7131;
B7145 <= B7153 or B7130;
B7146 <= (B7131 and B7143) or ((not B7131) and (not B7143));
B7147 <= (not B7156) or (not B7157);
B7148 <= ((not B7132) and B7139) or (B7132 and (not B7139));
B7149 <= B7158 and B7151;
B7150 <= (not B7160) or (not B7159);
B7151 <= B7132 or B7133;
B7152 <= B7132 or B7139;
B7153 <= B7131 and B7143;
B7154 <= (not B7130) or (not B7131);
B7155 <= B7139 and B7154;
B7156 <= (not B7155) and (not B7139);
B7157 <= B7139 or B7154;
B7158 <= (not B7132) or (not B7133);
B7159 <= B7139 or B7154;
B7160 <= (not B7139) and (not B7161);
B7161 <= B7139 and B7154;
B7167 <= B7173 and B7172;
B7168 <= B7175 or B7174;
B7169 <= B7177 or B7176;
B7170 <= B7172 and B7178;
B7171 <= B7172 and B7179;
B7172 <= ((not B7162) and B7163) or (B7162 and (not B7163));
B7173 <= ((not B7174) and B7164) or (B7174 and (not B7164));
B7174 <= B7182 and B7181;
B7175 <= B7180 and B7164;
B7176 <= B7185 and B7184;
B7177 <= B7183 and B7164;
B7178 <= B7186 or B7163;
B7179 <= (B7164 and B7176) or ((not B7164) and (not B7176));
B7180 <= (not B7189) or (not B7190);
B7181 <= ((not B7165) and B7172) or (B7165 and (not B7172));
B7182 <= B7191 and B7184;
B7183 <= (not B7193) or (not B7192);
B7184 <= B7165 or B7166;
B7185 <= B7165 or B7172;
B7186 <= B7164 and B7176;
B7187 <= (not B7163) or (not B7164);
B7188 <= B7172 and B7187;
B7189 <= (not B7188) and (not B7172);
B7190 <= B7172 or B7187;
B7191 <= (not B7165) or (not B7166);
B7192 <= B7172 or B7187;
B7193 <= (not B7172) and (not B7194);
B7194 <= B7172 and B7187;
B7200 <= B7206 and B7205;
B7201 <= B7208 or B7207;
B7202 <= B7210 or B7209;
B7203 <= B7205 and B7211;
B7204 <= B7205 and B7212;
B7205 <= ((not B7195) and B7196) or (B7195 and (not B7196));
B7206 <= ((not B7207) and B7197) or (B7207 and (not B7197));
B7207 <= B7215 and B7214;
B7208 <= B7213 and B7197;
B7209 <= B7218 and B7217;
B7210 <= B7216 and B7197;
B7211 <= B7219 or B7196;
B7212 <= (B7197 and B7209) or ((not B7197) and (not B7209));
B7213 <= (not B7222) or (not B7223);
B7214 <= ((not B7198) and B7205) or (B7198 and (not B7205));
B7215 <= B7224 and B7217;
B7216 <= (not B7226) or (not B7225);
B7217 <= B7198 or B7199;
B7218 <= B7198 or B7205;
B7219 <= B7197 and B7209;
B7220 <= (not B7196) or (not B7197);
B7221 <= B7205 and B7220;
B7222 <= (not B7221) and (not B7205);
B7223 <= B7205 or B7220;
B7224 <= (not B7198) or (not B7199);
B7225 <= B7205 or B7220;
B7226 <= (not B7205) and (not B7227);
B7227 <= B7205 and B7220;
B7233 <= B7239 and B7238;
B7234 <= B7241 or B7240;
B7235 <= B7243 or B7242;
B7236 <= B7238 and B7244;
B7237 <= B7238 and B7245;
B7238 <= ((not B7228) and B7229) or (B7228 and (not B7229));
B7239 <= ((not B7240) and B7230) or (B7240 and (not B7230));
B7240 <= B7248 and B7247;
B7241 <= B7246 and B7230;
B7242 <= B7251 and B7250;
B7243 <= B7249 and B7230;
B7244 <= B7252 or B7229;
B7245 <= (B7230 and B7242) or ((not B7230) and (not B7242));
B7246 <= (not B7255) or (not B7256);
B7247 <= ((not B7231) and B7238) or (B7231 and (not B7238));
B7248 <= B7257 and B7250;
B7249 <= (not B7259) or (not B7258);
B7250 <= B7231 or B7232;
B7251 <= B7231 or B7238;
B7252 <= B7230 and B7242;
B7253 <= (not B7229) or (not B7230);
B7254 <= B7238 and B7253;
B7255 <= (not B7254) and (not B7238);
B7256 <= B7238 or B7253;
B7257 <= (not B7231) or (not B7232);
B7258 <= B7238 or B7253;
B7259 <= (not B7238) and (not B7260);
B7260 <= B7238 and B7253;
B7266 <= B7272 and B7271;
B7267 <= B7274 or B7273;
B7268 <= B7276 or B7275;
B7269 <= B7271 and B7277;
B7270 <= B7271 and B7278;
B7271 <= ((not B7261) and B7262) or (B7261 and (not B7262));
B7272 <= ((not B7273) and B7263) or (B7273 and (not B7263));
B7273 <= B7281 and B7280;
B7274 <= B7279 and B7263;
B7275 <= B7284 and B7283;
B7276 <= B7282 and B7263;
B7277 <= B7285 or B7262;
B7278 <= (B7263 and B7275) or ((not B7263) and (not B7275));
B7279 <= (not B7288) or (not B7289);
B7280 <= ((not B7264) and B7271) or (B7264 and (not B7271));
B7281 <= B7290 and B7283;
B7282 <= (not B7292) or (not B7291);
B7283 <= B7264 or B7265;
B7284 <= B7264 or B7271;
B7285 <= B7263 and B7275;
B7286 <= (not B7262) or (not B7263);
B7287 <= B7271 and B7286;
B7288 <= (not B7287) and (not B7271);
B7289 <= B7271 or B7286;
B7290 <= (not B7264) or (not B7265);
B7291 <= B7271 or B7286;
B7292 <= (not B7271) and (not B7293);
B7293 <= B7271 and B7286;
B7299 <= B7305 and B7304;
B7300 <= B7307 or B7306;
B7301 <= B7309 or B7308;
B7302 <= B7304 and B7310;
B7303 <= B7304 and B7311;
B7304 <= ((not B7294) and B7295) or (B7294 and (not B7295));
B7305 <= ((not B7306) and B7296) or (B7306 and (not B7296));
B7306 <= B7314 and B7313;
B7307 <= B7312 and B7296;
B7308 <= B7317 and B7316;
B7309 <= B7315 and B7296;
B7310 <= B7318 or B7295;
B7311 <= (B7296 and B7308) or ((not B7296) and (not B7308));
B7312 <= (not B7321) or (not B7322);
B7313 <= ((not B7297) and B7304) or (B7297 and (not B7304));
B7314 <= B7323 and B7316;
B7315 <= (not B7325) or (not B7324);
B7316 <= B7297 or B7298;
B7317 <= B7297 or B7304;
B7318 <= B7296 and B7308;
B7319 <= (not B7295) or (not B7296);
B7320 <= B7304 and B7319;
B7321 <= (not B7320) and (not B7304);
B7322 <= B7304 or B7319;
B7323 <= (not B7297) or (not B7298);
B7324 <= B7304 or B7319;
B7325 <= (not B7304) and (not B7326);
B7326 <= B7304 and B7319;
B7332 <= B7338 and B7337;
B7333 <= B7340 or B7339;
B7334 <= B7342 or B7341;
B7335 <= B7337 and B7343;
B7336 <= B7337 and B7344;
B7337 <= ((not B7327) and B7328) or (B7327 and (not B7328));
B7338 <= ((not B7339) and B7329) or (B7339 and (not B7329));
B7339 <= B7347 and B7346;
B7340 <= B7345 and B7329;
B7341 <= B7350 and B7349;
B7342 <= B7348 and B7329;
B7343 <= B7351 or B7328;
B7344 <= (B7329 and B7341) or ((not B7329) and (not B7341));
B7345 <= (not B7354) or (not B7355);
B7346 <= ((not B7330) and B7337) or (B7330 and (not B7337));
B7347 <= B7356 and B7349;
B7348 <= (not B7358) or (not B7357);
B7349 <= B7330 or B7331;
B7350 <= B7330 or B7337;
B7351 <= B7329 and B7341;
B7352 <= (not B7328) or (not B7329);
B7353 <= B7337 and B7352;
B7354 <= (not B7353) and (not B7337);
B7355 <= B7337 or B7352;
B7356 <= (not B7330) or (not B7331);
B7357 <= B7337 or B7352;
B7358 <= (not B7337) and (not B7359);
B7359 <= B7337 and B7352;
B7365 <= B7371 and B7370;
B7366 <= B7373 or B7372;
B7367 <= B7375 or B7374;
B7368 <= B7370 and B7376;
B7369 <= B7370 and B7377;
B7370 <= ((not B7360) and B7361) or (B7360 and (not B7361));
B7371 <= ((not B7372) and B7362) or (B7372 and (not B7362));
B7372 <= B7380 and B7379;
B7373 <= B7378 and B7362;
B7374 <= B7383 and B7382;
B7375 <= B7381 and B7362;
B7376 <= B7384 or B7361;
B7377 <= (B7362 and B7374) or ((not B7362) and (not B7374));
B7378 <= (not B7387) or (not B7388);
B7379 <= ((not B7363) and B7370) or (B7363 and (not B7370));
B7380 <= B7389 and B7382;
B7381 <= (not B7391) or (not B7390);
B7382 <= B7363 or B7364;
B7383 <= B7363 or B7370;
B7384 <= B7362 and B7374;
B7385 <= (not B7361) or (not B7362);
B7386 <= B7370 and B7385;
B7387 <= (not B7386) and (not B7370);
B7388 <= B7370 or B7385;
B7389 <= (not B7363) or (not B7364);
B7390 <= B7370 or B7385;
B7391 <= (not B7370) and (not B7392);
B7392 <= B7370 and B7385;
B7398 <= B7404 and B7403;
B7399 <= B7406 or B7405;
B7400 <= B7408 or B7407;
B7401 <= B7403 and B7409;
B7402 <= B7403 and B7410;
B7403 <= ((not B7393) and B7394) or (B7393 and (not B7394));
B7404 <= ((not B7405) and B7395) or (B7405 and (not B7395));
B7405 <= B7413 and B7412;
B7406 <= B7411 and B7395;
B7407 <= B7416 and B7415;
B7408 <= B7414 and B7395;
B7409 <= B7417 or B7394;
B7410 <= (B7395 and B7407) or ((not B7395) and (not B7407));
B7411 <= (not B7420) or (not B7421);
B7412 <= ((not B7396) and B7403) or (B7396 and (not B7403));
B7413 <= B7422 and B7415;
B7414 <= (not B7424) or (not B7423);
B7415 <= B7396 or B7397;
B7416 <= B7396 or B7403;
B7417 <= B7395 and B7407;
B7418 <= (not B7394) or (not B7395);
B7419 <= B7403 and B7418;
B7420 <= (not B7419) and (not B7403);
B7421 <= B7403 or B7418;
B7422 <= (not B7396) or (not B7397);
B7423 <= B7403 or B7418;
B7424 <= (not B7403) and (not B7425);
B7425 <= B7403 and B7418;
B7431 <= B7437 and B7436;
B7432 <= B7439 or B7438;
B7433 <= B7441 or B7440;
B7434 <= B7436 and B7442;
B7435 <= B7436 and B7443;
B7436 <= ((not B7426) and B7427) or (B7426 and (not B7427));
B7437 <= ((not B7438) and B7428) or (B7438 and (not B7428));
B7438 <= B7446 and B7445;
B7439 <= B7444 and B7428;
B7440 <= B7449 and B7448;
B7441 <= B7447 and B7428;
B7442 <= B7450 or B7427;
B7443 <= (B7428 and B7440) or ((not B7428) and (not B7440));
B7444 <= (not B7453) or (not B7454);
B7445 <= ((not B7429) and B7436) or (B7429 and (not B7436));
B7446 <= B7455 and B7448;
B7447 <= (not B7457) or (not B7456);
B7448 <= B7429 or B7430;
B7449 <= B7429 or B7436;
B7450 <= B7428 and B7440;
B7451 <= (not B7427) or (not B7428);
B7452 <= B7436 and B7451;
B7453 <= (not B7452) and (not B7436);
B7454 <= B7436 or B7451;
B7455 <= (not B7429) or (not B7430);
B7456 <= B7436 or B7451;
B7457 <= (not B7436) and (not B7458);
B7458 <= B7436 and B7451;
B7464 <= B7470 and B7469;
B7465 <= B7472 or B7471;
B7466 <= B7474 or B7473;
B7467 <= B7469 and B7475;
B7468 <= B7469 and B7476;
B7469 <= ((not B7459) and B7460) or (B7459 and (not B7460));
B7470 <= ((not B7471) and B7461) or (B7471 and (not B7461));
B7471 <= B7479 and B7478;
B7472 <= B7477 and B7461;
B7473 <= B7482 and B7481;
B7474 <= B7480 and B7461;
B7475 <= B7483 or B7460;
B7476 <= (B7461 and B7473) or ((not B7461) and (not B7473));
B7477 <= (not B7486) or (not B7487);
B7478 <= ((not B7462) and B7469) or (B7462 and (not B7469));
B7479 <= B7488 and B7481;
B7480 <= (not B7490) or (not B7489);
B7481 <= B7462 or B7463;
B7482 <= B7462 or B7469;
B7483 <= B7461 and B7473;
B7484 <= (not B7460) or (not B7461);
B7485 <= B7469 and B7484;
B7486 <= (not B7485) and (not B7469);
B7487 <= B7469 or B7484;
B7488 <= (not B7462) or (not B7463);
B7489 <= B7469 or B7484;
B7490 <= (not B7469) and (not B7491);
B7491 <= B7469 and B7484;
B7497 <= B7503 and B7502;
B7498 <= B7505 or B7504;
B7499 <= B7507 or B7506;
B7500 <= B7502 and B7508;
B7501 <= B7502 and B7509;
B7502 <= ((not B7492) and B7493) or (B7492 and (not B7493));
B7503 <= ((not B7504) and B7494) or (B7504 and (not B7494));
B7504 <= B7512 and B7511;
B7505 <= B7510 and B7494;
B7506 <= B7515 and B7514;
B7507 <= B7513 and B7494;
B7508 <= B7516 or B7493;
B7509 <= (B7494 and B7506) or ((not B7494) and (not B7506));
B7510 <= (not B7519) or (not B7520);
B7511 <= ((not B7495) and B7502) or (B7495 and (not B7502));
B7512 <= B7521 and B7514;
B7513 <= (not B7523) or (not B7522);
B7514 <= B7495 or B7496;
B7515 <= B7495 or B7502;
B7516 <= B7494 and B7506;
B7517 <= (not B7493) or (not B7494);
B7518 <= B7502 and B7517;
B7519 <= (not B7518) and (not B7502);
B7520 <= B7502 or B7517;
B7521 <= (not B7495) or (not B7496);
B7522 <= B7502 or B7517;
B7523 <= (not B7502) and (not B7524);
B7524 <= B7502 and B7517;
B7530 <= B7536 and B7535;
B7531 <= B7538 or B7537;
B7532 <= B7540 or B7539;
B7533 <= B7535 and B7541;
B7534 <= B7535 and B7542;
B7535 <= ((not B7525) and B7526) or (B7525 and (not B7526));
B7536 <= ((not B7537) and B7527) or (B7537 and (not B7527));
B7537 <= B7545 and B7544;
B7538 <= B7543 and B7527;
B7539 <= B7548 and B7547;
B7540 <= B7546 and B7527;
B7541 <= B7549 or B7526;
B7542 <= (B7527 and B7539) or ((not B7527) and (not B7539));
B7543 <= (not B7552) or (not B7553);
B7544 <= ((not B7528) and B7535) or (B7528 and (not B7535));
B7545 <= B7554 and B7547;
B7546 <= (not B7556) or (not B7555);
B7547 <= B7528 or B7529;
B7548 <= B7528 or B7535;
B7549 <= B7527 and B7539;
B7550 <= (not B7526) or (not B7527);
B7551 <= B7535 and B7550;
B7552 <= (not B7551) and (not B7535);
B7553 <= B7535 or B7550;
B7554 <= (not B7528) or (not B7529);
B7555 <= B7535 or B7550;
B7556 <= (not B7535) and (not B7557);
B7557 <= B7535 and B7550;
B7563 <= B7569 and B7568;
B7564 <= B7571 or B7570;
B7565 <= B7573 or B7572;
B7566 <= B7568 and B7574;
B7567 <= B7568 and B7575;
B7568 <= ((not B7558) and B7559) or (B7558 and (not B7559));
B7569 <= ((not B7570) and B7560) or (B7570 and (not B7560));
B7570 <= B7578 and B7577;
B7571 <= B7576 and B7560;
B7572 <= B7581 and B7580;
B7573 <= B7579 and B7560;
B7574 <= B7582 or B7559;
B7575 <= (B7560 and B7572) or ((not B7560) and (not B7572));
B7576 <= (not B7585) or (not B7586);
B7577 <= ((not B7561) and B7568) or (B7561 and (not B7568));
B7578 <= B7587 and B7580;
B7579 <= (not B7589) or (not B7588);
B7580 <= B7561 or B7562;
B7581 <= B7561 or B7568;
B7582 <= B7560 and B7572;
B7583 <= (not B7559) or (not B7560);
B7584 <= B7568 and B7583;
B7585 <= (not B7584) and (not B7568);
B7586 <= B7568 or B7583;
B7587 <= (not B7561) or (not B7562);
B7588 <= B7568 or B7583;
B7589 <= (not B7568) and (not B7590);
B7590 <= B7568 and B7583;
B7596 <= B7602 and B7601;
B7597 <= B7604 or B7603;
B7598 <= B7606 or B7605;
B7599 <= B7601 and B7607;
B7600 <= B7601 and B7608;
B7601 <= ((not B7591) and B7592) or (B7591 and (not B7592));
B7602 <= ((not B7603) and B7593) or (B7603 and (not B7593));
B7603 <= B7611 and B7610;
B7604 <= B7609 and B7593;
B7605 <= B7614 and B7613;
B7606 <= B7612 and B7593;
B7607 <= B7615 or B7592;
B7608 <= (B7593 and B7605) or ((not B7593) and (not B7605));
B7609 <= (not B7618) or (not B7619);
B7610 <= ((not B7594) and B7601) or (B7594 and (not B7601));
B7611 <= B7620 and B7613;
B7612 <= (not B7622) or (not B7621);
B7613 <= B7594 or B7595;
B7614 <= B7594 or B7601;
B7615 <= B7593 and B7605;
B7616 <= (not B7592) or (not B7593);
B7617 <= B7601 and B7616;
B7618 <= (not B7617) and (not B7601);
B7619 <= B7601 or B7616;
B7620 <= (not B7594) or (not B7595);
B7621 <= B7601 or B7616;
B7622 <= (not B7601) and (not B7623);
B7623 <= B7601 and B7616;
B7629 <= B7635 and B7634;
B7630 <= B7637 or B7636;
B7631 <= B7639 or B7638;
B7632 <= B7634 and B7640;
B7633 <= B7634 and B7641;
B7634 <= ((not B7624) and B7625) or (B7624 and (not B7625));
B7635 <= ((not B7636) and B7626) or (B7636 and (not B7626));
B7636 <= B7644 and B7643;
B7637 <= B7642 and B7626;
B7638 <= B7647 and B7646;
B7639 <= B7645 and B7626;
B7640 <= B7648 or B7625;
B7641 <= (B7626 and B7638) or ((not B7626) and (not B7638));
B7642 <= (not B7651) or (not B7652);
B7643 <= ((not B7627) and B7634) or (B7627 and (not B7634));
B7644 <= B7653 and B7646;
B7645 <= (not B7655) or (not B7654);
B7646 <= B7627 or B7628;
B7647 <= B7627 or B7634;
B7648 <= B7626 and B7638;
B7649 <= (not B7625) or (not B7626);
B7650 <= B7634 and B7649;
B7651 <= (not B7650) and (not B7634);
B7652 <= B7634 or B7649;
B7653 <= (not B7627) or (not B7628);
B7654 <= B7634 or B7649;
B7655 <= (not B7634) and (not B7656);
B7656 <= B7634 and B7649;
B7662 <= B7668 and B7667;
B7663 <= B7670 or B7669;
B7664 <= B7672 or B7671;
B7665 <= B7667 and B7673;
B7666 <= B7667 and B7674;
B7667 <= ((not B7657) and B7658) or (B7657 and (not B7658));
B7668 <= ((not B7669) and B7659) or (B7669 and (not B7659));
B7669 <= B7677 and B7676;
B7670 <= B7675 and B7659;
B7671 <= B7680 and B7679;
B7672 <= B7678 and B7659;
B7673 <= B7681 or B7658;
B7674 <= (B7659 and B7671) or ((not B7659) and (not B7671));
B7675 <= (not B7684) or (not B7685);
B7676 <= ((not B7660) and B7667) or (B7660 and (not B7667));
B7677 <= B7686 and B7679;
B7678 <= (not B7688) or (not B7687);
B7679 <= B7660 or B7661;
B7680 <= B7660 or B7667;
B7681 <= B7659 and B7671;
B7682 <= (not B7658) or (not B7659);
B7683 <= B7667 and B7682;
B7684 <= (not B7683) and (not B7667);
B7685 <= B7667 or B7682;
B7686 <= (not B7660) or (not B7661);
B7687 <= B7667 or B7682;
B7688 <= (not B7667) and (not B7689);
B7689 <= B7667 and B7682;
B7695 <= B7701 and B7700;
B7696 <= B7703 or B7702;
B7697 <= B7705 or B7704;
B7698 <= B7700 and B7706;
B7699 <= B7700 and B7707;
B7700 <= ((not B7690) and B7691) or (B7690 and (not B7691));
B7701 <= ((not B7702) and B7692) or (B7702 and (not B7692));
B7702 <= B7710 and B7709;
B7703 <= B7708 and B7692;
B7704 <= B7713 and B7712;
B7705 <= B7711 and B7692;
B7706 <= B7714 or B7691;
B7707 <= (B7692 and B7704) or ((not B7692) and (not B7704));
B7708 <= (not B7717) or (not B7718);
B7709 <= ((not B7693) and B7700) or (B7693 and (not B7700));
B7710 <= B7719 and B7712;
B7711 <= (not B7721) or (not B7720);
B7712 <= B7693 or B7694;
B7713 <= B7693 or B7700;
B7714 <= B7692 and B7704;
B7715 <= (not B7691) or (not B7692);
B7716 <= B7700 and B7715;
B7717 <= (not B7716) and (not B7700);
B7718 <= B7700 or B7715;
B7719 <= (not B7693) or (not B7694);
B7720 <= B7700 or B7715;
B7721 <= (not B7700) and (not B7722);
B7722 <= B7700 and B7715;
B7728 <= B7734 and B7733;
B7729 <= B7736 or B7735;
B7730 <= B7738 or B7737;
B7731 <= B7733 and B7739;
B7732 <= B7733 and B7740;
B7733 <= ((not B7723) and B7724) or (B7723 and (not B7724));
B7734 <= ((not B7735) and B7725) or (B7735 and (not B7725));
B7735 <= B7743 and B7742;
B7736 <= B7741 and B7725;
B7737 <= B7746 and B7745;
B7738 <= B7744 and B7725;
B7739 <= B7747 or B7724;
B7740 <= (B7725 and B7737) or ((not B7725) and (not B7737));
B7741 <= (not B7750) or (not B7751);
B7742 <= ((not B7726) and B7733) or (B7726 and (not B7733));
B7743 <= B7752 and B7745;
B7744 <= (not B7754) or (not B7753);
B7745 <= B7726 or B7727;
B7746 <= B7726 or B7733;
B7747 <= B7725 and B7737;
B7748 <= (not B7724) or (not B7725);
B7749 <= B7733 and B7748;
B7750 <= (not B7749) and (not B7733);
B7751 <= B7733 or B7748;
B7752 <= (not B7726) or (not B7727);
B7753 <= B7733 or B7748;
B7754 <= (not B7733) and (not B7755);
B7755 <= B7733 and B7748;
B7761 <= B7767 and B7766;
B7762 <= B7769 or B7768;
B7763 <= B7771 or B7770;
B7764 <= B7766 and B7772;
B7765 <= B7766 and B7773;
B7766 <= ((not B7756) and B7757) or (B7756 and (not B7757));
B7767 <= ((not B7768) and B7758) or (B7768 and (not B7758));
B7768 <= B7776 and B7775;
B7769 <= B7774 and B7758;
B7770 <= B7779 and B7778;
B7771 <= B7777 and B7758;
B7772 <= B7780 or B7757;
B7773 <= (B7758 and B7770) or ((not B7758) and (not B7770));
B7774 <= (not B7783) or (not B7784);
B7775 <= ((not B7759) and B7766) or (B7759 and (not B7766));
B7776 <= B7785 and B7778;
B7777 <= (not B7787) or (not B7786);
B7778 <= B7759 or B7760;
B7779 <= B7759 or B7766;
B7780 <= B7758 and B7770;
B7781 <= (not B7757) or (not B7758);
B7782 <= B7766 and B7781;
B7783 <= (not B7782) and (not B7766);
B7784 <= B7766 or B7781;
B7785 <= (not B7759) or (not B7760);
B7786 <= B7766 or B7781;
B7787 <= (not B7766) and (not B7788);
B7788 <= B7766 and B7781;
B7794 <= B7800 and B7799;
B7795 <= B7802 or B7801;
B7796 <= B7804 or B7803;
B7797 <= B7799 and B7805;
B7798 <= B7799 and B7806;
B7799 <= ((not B7789) and B7790) or (B7789 and (not B7790));
B7800 <= ((not B7801) and B7791) or (B7801 and (not B7791));
B7801 <= B7809 and B7808;
B7802 <= B7807 and B7791;
B7803 <= B7812 and B7811;
B7804 <= B7810 and B7791;
B7805 <= B7813 or B7790;
B7806 <= (B7791 and B7803) or ((not B7791) and (not B7803));
B7807 <= (not B7816) or (not B7817);
B7808 <= ((not B7792) and B7799) or (B7792 and (not B7799));
B7809 <= B7818 and B7811;
B7810 <= (not B7820) or (not B7819);
B7811 <= B7792 or B7793;
B7812 <= B7792 or B7799;
B7813 <= B7791 and B7803;
B7814 <= (not B7790) or (not B7791);
B7815 <= B7799 and B7814;
B7816 <= (not B7815) and (not B7799);
B7817 <= B7799 or B7814;
B7818 <= (not B7792) or (not B7793);
B7819 <= B7799 or B7814;
B7820 <= (not B7799) and (not B7821);
B7821 <= B7799 and B7814;
B7827 <= B7833 and B7832;
B7828 <= B7835 or B7834;
B7829 <= B7837 or B7836;
B7830 <= B7832 and B7838;
B7831 <= B7832 and B7839;
B7832 <= ((not B7822) and B7823) or (B7822 and (not B7823));
B7833 <= ((not B7834) and B7824) or (B7834 and (not B7824));
B7834 <= B7842 and B7841;
B7835 <= B7840 and B7824;
B7836 <= B7845 and B7844;
B7837 <= B7843 and B7824;
B7838 <= B7846 or B7823;
B7839 <= (B7824 and B7836) or ((not B7824) and (not B7836));
B7840 <= (not B7849) or (not B7850);
B7841 <= ((not B7825) and B7832) or (B7825 and (not B7832));
B7842 <= B7851 and B7844;
B7843 <= (not B7853) or (not B7852);
B7844 <= B7825 or B7826;
B7845 <= B7825 or B7832;
B7846 <= B7824 and B7836;
B7847 <= (not B7823) or (not B7824);
B7848 <= B7832 and B7847;
B7849 <= (not B7848) and (not B7832);
B7850 <= B7832 or B7847;
B7851 <= (not B7825) or (not B7826);
B7852 <= B7832 or B7847;
B7853 <= (not B7832) and (not B7854);
B7854 <= B7832 and B7847;
B7860 <= B7866 and B7865;
B7861 <= B7868 or B7867;
B7862 <= B7870 or B7869;
B7863 <= B7865 and B7871;
B7864 <= B7865 and B7872;
B7865 <= ((not B7855) and B7856) or (B7855 and (not B7856));
B7866 <= ((not B7867) and B7857) or (B7867 and (not B7857));
B7867 <= B7875 and B7874;
B7868 <= B7873 and B7857;
B7869 <= B7878 and B7877;
B7870 <= B7876 and B7857;
B7871 <= B7879 or B7856;
B7872 <= (B7857 and B7869) or ((not B7857) and (not B7869));
B7873 <= (not B7882) or (not B7883);
B7874 <= ((not B7858) and B7865) or (B7858 and (not B7865));
B7875 <= B7884 and B7877;
B7876 <= (not B7886) or (not B7885);
B7877 <= B7858 or B7859;
B7878 <= B7858 or B7865;
B7879 <= B7857 and B7869;
B7880 <= (not B7856) or (not B7857);
B7881 <= B7865 and B7880;
B7882 <= (not B7881) and (not B7865);
B7883 <= B7865 or B7880;
B7884 <= (not B7858) or (not B7859);
B7885 <= B7865 or B7880;
B7886 <= (not B7865) and (not B7887);
B7887 <= B7865 and B7880;
B7893 <= B7899 and B7898;
B7894 <= B7901 or B7900;
B7895 <= B7903 or B7902;
B7896 <= B7898 and B7904;
B7897 <= B7898 and B7905;
B7898 <= ((not B7888) and B7889) or (B7888 and (not B7889));
B7899 <= ((not B7900) and B7890) or (B7900 and (not B7890));
B7900 <= B7908 and B7907;
B7901 <= B7906 and B7890;
B7902 <= B7911 and B7910;
B7903 <= B7909 and B7890;
B7904 <= B7912 or B7889;
B7905 <= (B7890 and B7902) or ((not B7890) and (not B7902));
B7906 <= (not B7915) or (not B7916);
B7907 <= ((not B7891) and B7898) or (B7891 and (not B7898));
B7908 <= B7917 and B7910;
B7909 <= (not B7919) or (not B7918);
B7910 <= B7891 or B7892;
B7911 <= B7891 or B7898;
B7912 <= B7890 and B7902;
B7913 <= (not B7889) or (not B7890);
B7914 <= B7898 and B7913;
B7915 <= (not B7914) and (not B7898);
B7916 <= B7898 or B7913;
B7917 <= (not B7891) or (not B7892);
B7918 <= B7898 or B7913;
B7919 <= (not B7898) and (not B7920);
B7920 <= B7898 and B7913;
B7926 <= B7932 and B7931;
B7927 <= B7934 or B7933;
B7928 <= B7936 or B7935;
B7929 <= B7931 and B7937;
B7930 <= B7931 and B7938;
B7931 <= ((not B7921) and B7922) or (B7921 and (not B7922));
B7932 <= ((not B7933) and B7923) or (B7933 and (not B7923));
B7933 <= B7941 and B7940;
B7934 <= B7939 and B7923;
B7935 <= B7944 and B7943;
B7936 <= B7942 and B7923;
B7937 <= B7945 or B7922;
B7938 <= (B7923 and B7935) or ((not B7923) and (not B7935));
B7939 <= (not B7948) or (not B7949);
B7940 <= ((not B7924) and B7931) or (B7924 and (not B7931));
B7941 <= B7950 and B7943;
B7942 <= (not B7952) or (not B7951);
B7943 <= B7924 or B7925;
B7944 <= B7924 or B7931;
B7945 <= B7923 and B7935;
B7946 <= (not B7922) or (not B7923);
B7947 <= B7931 and B7946;
B7948 <= (not B7947) and (not B7931);
B7949 <= B7931 or B7946;
B7950 <= (not B7924) or (not B7925);
B7951 <= B7931 or B7946;
B7952 <= (not B7931) and (not B7953);
B7953 <= B7931 and B7946;
B7959 <= B7965 and B7964;
B7960 <= B7967 or B7966;
B7961 <= B7969 or B7968;
B7962 <= B7964 and B7970;
B7963 <= B7964 and B7971;
B7964 <= ((not B7954) and B7955) or (B7954 and (not B7955));
B7965 <= ((not B7966) and B7956) or (B7966 and (not B7956));
B7966 <= B7974 and B7973;
B7967 <= B7972 and B7956;
B7968 <= B7977 and B7976;
B7969 <= B7975 and B7956;
B7970 <= B7978 or B7955;
B7971 <= (B7956 and B7968) or ((not B7956) and (not B7968));
B7972 <= (not B7981) or (not B7982);
B7973 <= ((not B7957) and B7964) or (B7957 and (not B7964));
B7974 <= B7983 and B7976;
B7975 <= (not B7985) or (not B7984);
B7976 <= B7957 or B7958;
B7977 <= B7957 or B7964;
B7978 <= B7956 and B7968;
B7979 <= (not B7955) or (not B7956);
B7980 <= B7964 and B7979;
B7981 <= (not B7980) and (not B7964);
B7982 <= B7964 or B7979;
B7983 <= (not B7957) or (not B7958);
B7984 <= B7964 or B7979;
B7985 <= (not B7964) and (not B7986);
B7986 <= B7964 and B7979;
B7992 <= B7998 and B7997;
B7993 <= B8000 or B7999;
B7994 <= B8002 or B8001;
B7995 <= B7997 and B8003;
B7996 <= B7997 and B8004;
B7997 <= ((not B7987) and B7988) or (B7987 and (not B7988));
B7998 <= ((not B7999) and B7989) or (B7999 and (not B7989));
B7999 <= B8007 and B8006;
B8000 <= B8005 and B7989;
B8001 <= B8010 and B8009;
B8002 <= B8008 and B7989;
B8003 <= B8011 or B7988;
B8004 <= (B7989 and B8001) or ((not B7989) and (not B8001));
B8005 <= (not B8014) or (not B8015);
B8006 <= ((not B7990) and B7997) or (B7990 and (not B7997));
B8007 <= B8016 and B8009;
B8008 <= (not B8018) or (not B8017);
B8009 <= B7990 or B7991;
B8010 <= B7990 or B7997;
B8011 <= B7989 and B8001;
B8012 <= (not B7988) or (not B7989);
B8013 <= B7997 and B8012;
B8014 <= (not B8013) and (not B7997);
B8015 <= B7997 or B8012;
B8016 <= (not B7990) or (not B7991);
B8017 <= B7997 or B8012;
B8018 <= (not B7997) and (not B8019);
B8019 <= B7997 and B8012;
B8025 <= B8031 and B8030;
B8026 <= B8033 or B8032;
B8027 <= B8035 or B8034;
B8028 <= B8030 and B8036;
B8029 <= B8030 and B8037;
B8030 <= ((not B8020) and B8021) or (B8020 and (not B8021));
B8031 <= ((not B8032) and B8022) or (B8032 and (not B8022));
B8032 <= B8040 and B8039;
B8033 <= B8038 and B8022;
B8034 <= B8043 and B8042;
B8035 <= B8041 and B8022;
B8036 <= B8044 or B8021;
B8037 <= (B8022 and B8034) or ((not B8022) and (not B8034));
B8038 <= (not B8047) or (not B8048);
B8039 <= ((not B8023) and B8030) or (B8023 and (not B8030));
B8040 <= B8049 and B8042;
B8041 <= (not B8051) or (not B8050);
B8042 <= B8023 or B8024;
B8043 <= B8023 or B8030;
B8044 <= B8022 and B8034;
B8045 <= (not B8021) or (not B8022);
B8046 <= B8030 and B8045;
B8047 <= (not B8046) and (not B8030);
B8048 <= B8030 or B8045;
B8049 <= (not B8023) or (not B8024);
B8050 <= B8030 or B8045;
B8051 <= (not B8030) and (not B8052);
B8052 <= B8030 and B8045;
B8058 <= B8064 and B8063;
B8059 <= B8066 or B8065;
B8060 <= B8068 or B8067;
B8061 <= B8063 and B8069;
B8062 <= B8063 and B8070;
B8063 <= ((not B8053) and B8054) or (B8053 and (not B8054));
B8064 <= ((not B8065) and B8055) or (B8065 and (not B8055));
B8065 <= B8073 and B8072;
B8066 <= B8071 and B8055;
B8067 <= B8076 and B8075;
B8068 <= B8074 and B8055;
B8069 <= B8077 or B8054;
B8070 <= (B8055 and B8067) or ((not B8055) and (not B8067));
B8071 <= (not B8080) or (not B8081);
B8072 <= ((not B8056) and B8063) or (B8056 and (not B8063));
B8073 <= B8082 and B8075;
B8074 <= (not B8084) or (not B8083);
B8075 <= B8056 or B8057;
B8076 <= B8056 or B8063;
B8077 <= B8055 and B8067;
B8078 <= (not B8054) or (not B8055);
B8079 <= B8063 and B8078;
B8080 <= (not B8079) and (not B8063);
B8081 <= B8063 or B8078;
B8082 <= (not B8056) or (not B8057);
B8083 <= B8063 or B8078;
B8084 <= (not B8063) and (not B8085);
B8085 <= B8063 and B8078;
B8091 <= B8097 and B8096;
B8092 <= B8099 or B8098;
B8093 <= B8101 or B8100;
B8094 <= B8096 and B8102;
B8095 <= B8096 and B8103;
B8096 <= ((not B8086) and B8087) or (B8086 and (not B8087));
B8097 <= ((not B8098) and B8088) or (B8098 and (not B8088));
B8098 <= B8106 and B8105;
B8099 <= B8104 and B8088;
B8100 <= B8109 and B8108;
B8101 <= B8107 and B8088;
B8102 <= B8110 or B8087;
B8103 <= (B8088 and B8100) or ((not B8088) and (not B8100));
B8104 <= (not B8113) or (not B8114);
B8105 <= ((not B8089) and B8096) or (B8089 and (not B8096));
B8106 <= B8115 and B8108;
B8107 <= (not B8117) or (not B8116);
B8108 <= B8089 or B8090;
B8109 <= B8089 or B8096;
B8110 <= B8088 and B8100;
B8111 <= (not B8087) or (not B8088);
B8112 <= B8096 and B8111;
B8113 <= (not B8112) and (not B8096);
B8114 <= B8096 or B8111;
B8115 <= (not B8089) or (not B8090);
B8116 <= B8096 or B8111;
B8117 <= (not B8096) and (not B8118);
B8118 <= B8096 and B8111;
B8124 <= B8130 and B8129;
B8125 <= B8132 or B8131;
B8126 <= B8134 or B8133;
B8127 <= B8129 and B8135;
B8128 <= B8129 and B8136;
B8129 <= ((not B8119) and B8120) or (B8119 and (not B8120));
B8130 <= ((not B8131) and B8121) or (B8131 and (not B8121));
B8131 <= B8139 and B8138;
B8132 <= B8137 and B8121;
B8133 <= B8142 and B8141;
B8134 <= B8140 and B8121;
B8135 <= B8143 or B8120;
B8136 <= (B8121 and B8133) or ((not B8121) and (not B8133));
B8137 <= (not B8146) or (not B8147);
B8138 <= ((not B8122) and B8129) or (B8122 and (not B8129));
B8139 <= B8148 and B8141;
B8140 <= (not B8150) or (not B8149);
B8141 <= B8122 or B8123;
B8142 <= B8122 or B8129;
B8143 <= B8121 and B8133;
B8144 <= (not B8120) or (not B8121);
B8145 <= B8129 and B8144;
B8146 <= (not B8145) and (not B8129);
B8147 <= B8129 or B8144;
B8148 <= (not B8122) or (not B8123);
B8149 <= B8129 or B8144;
B8150 <= (not B8129) and (not B8151);
B8151 <= B8129 and B8144;
B8157 <= B8163 and B8162;
B8158 <= B8165 or B8164;
B8159 <= B8167 or B8166;
B8160 <= B8162 and B8168;
B8161 <= B8162 and B8169;
B8162 <= ((not B8152) and B8153) or (B8152 and (not B8153));
B8163 <= ((not B8164) and B8154) or (B8164 and (not B8154));
B8164 <= B8172 and B8171;
B8165 <= B8170 and B8154;
B8166 <= B8175 and B8174;
B8167 <= B8173 and B8154;
B8168 <= B8176 or B8153;
B8169 <= (B8154 and B8166) or ((not B8154) and (not B8166));
B8170 <= (not B8179) or (not B8180);
B8171 <= ((not B8155) and B8162) or (B8155 and (not B8162));
B8172 <= B8181 and B8174;
B8173 <= (not B8183) or (not B8182);
B8174 <= B8155 or B8156;
B8175 <= B8155 or B8162;
B8176 <= B8154 and B8166;
B8177 <= (not B8153) or (not B8154);
B8178 <= B8162 and B8177;
B8179 <= (not B8178) and (not B8162);
B8180 <= B8162 or B8177;
B8181 <= (not B8155) or (not B8156);
B8182 <= B8162 or B8177;
B8183 <= (not B8162) and (not B8184);
B8184 <= B8162 and B8177;
B8190 <= B8196 and B8195;
B8191 <= B8198 or B8197;
B8192 <= B8200 or B8199;
B8193 <= B8195 and B8201;
B8194 <= B8195 and B8202;
B8195 <= ((not B8185) and B8186) or (B8185 and (not B8186));
B8196 <= ((not B8197) and B8187) or (B8197 and (not B8187));
B8197 <= B8205 and B8204;
B8198 <= B8203 and B8187;
B8199 <= B8208 and B8207;
B8200 <= B8206 and B8187;
B8201 <= B8209 or B8186;
B8202 <= (B8187 and B8199) or ((not B8187) and (not B8199));
B8203 <= (not B8212) or (not B8213);
B8204 <= ((not B8188) and B8195) or (B8188 and (not B8195));
B8205 <= B8214 and B8207;
B8206 <= (not B8216) or (not B8215);
B8207 <= B8188 or B8189;
B8208 <= B8188 or B8195;
B8209 <= B8187 and B8199;
B8210 <= (not B8186) or (not B8187);
B8211 <= B8195 and B8210;
B8212 <= (not B8211) and (not B8195);
B8213 <= B8195 or B8210;
B8214 <= (not B8188) or (not B8189);
B8215 <= B8195 or B8210;
B8216 <= (not B8195) and (not B8217);
B8217 <= B8195 and B8210;
B8223 <= B8229 and B8228;
B8224 <= B8231 or B8230;
B8225 <= B8233 or B8232;
B8226 <= B8228 and B8234;
B8227 <= B8228 and B8235;
B8228 <= ((not B8218) and B8219) or (B8218 and (not B8219));
B8229 <= ((not B8230) and B8220) or (B8230 and (not B8220));
B8230 <= B8238 and B8237;
B8231 <= B8236 and B8220;
B8232 <= B8241 and B8240;
B8233 <= B8239 and B8220;
B8234 <= B8242 or B8219;
B8235 <= (B8220 and B8232) or ((not B8220) and (not B8232));
B8236 <= (not B8245) or (not B8246);
B8237 <= ((not B8221) and B8228) or (B8221 and (not B8228));
B8238 <= B8247 and B8240;
B8239 <= (not B8249) or (not B8248);
B8240 <= B8221 or B8222;
B8241 <= B8221 or B8228;
B8242 <= B8220 and B8232;
B8243 <= (not B8219) or (not B8220);
B8244 <= B8228 and B8243;
B8245 <= (not B8244) and (not B8228);
B8246 <= B8228 or B8243;
B8247 <= (not B8221) or (not B8222);
B8248 <= B8228 or B8243;
B8249 <= (not B8228) and (not B8250);
B8250 <= B8228 and B8243;
B8256 <= B8262 and B8261;
B8257 <= B8264 or B8263;
B8258 <= B8266 or B8265;
B8259 <= B8261 and B8267;
B8260 <= B8261 and B8268;
B8261 <= ((not B8251) and B8252) or (B8251 and (not B8252));
B8262 <= ((not B8263) and B8253) or (B8263 and (not B8253));
B8263 <= B8271 and B8270;
B8264 <= B8269 and B8253;
B8265 <= B8274 and B8273;
B8266 <= B8272 and B8253;
B8267 <= B8275 or B8252;
B8268 <= (B8253 and B8265) or ((not B8253) and (not B8265));
B8269 <= (not B8278) or (not B8279);
B8270 <= ((not B8254) and B8261) or (B8254 and (not B8261));
B8271 <= B8280 and B8273;
B8272 <= (not B8282) or (not B8281);
B8273 <= B8254 or B8255;
B8274 <= B8254 or B8261;
B8275 <= B8253 and B8265;
B8276 <= (not B8252) or (not B8253);
B8277 <= B8261 and B8276;
B8278 <= (not B8277) and (not B8261);
B8279 <= B8261 or B8276;
B8280 <= (not B8254) or (not B8255);
B8281 <= B8261 or B8276;
B8282 <= (not B8261) and (not B8283);
B8283 <= B8261 and B8276;
B8289 <= B8295 and B8294;
B8290 <= B8297 or B8296;
B8291 <= B8299 or B8298;
B8292 <= B8294 and B8300;
B8293 <= B8294 and B8301;
B8294 <= ((not B8284) and B8285) or (B8284 and (not B8285));
B8295 <= ((not B8296) and B8286) or (B8296 and (not B8286));
B8296 <= B8304 and B8303;
B8297 <= B8302 and B8286;
B8298 <= B8307 and B8306;
B8299 <= B8305 and B8286;
B8300 <= B8308 or B8285;
B8301 <= (B8286 and B8298) or ((not B8286) and (not B8298));
B8302 <= (not B8311) or (not B8312);
B8303 <= ((not B8287) and B8294) or (B8287 and (not B8294));
B8304 <= B8313 and B8306;
B8305 <= (not B8315) or (not B8314);
B8306 <= B8287 or B8288;
B8307 <= B8287 or B8294;
B8308 <= B8286 and B8298;
B8309 <= (not B8285) or (not B8286);
B8310 <= B8294 and B8309;
B8311 <= (not B8310) and (not B8294);
B8312 <= B8294 or B8309;
B8313 <= (not B8287) or (not B8288);
B8314 <= B8294 or B8309;
B8315 <= (not B8294) and (not B8316);
B8316 <= B8294 and B8309;
B8322 <= B8328 and B8327;
B8323 <= B8330 or B8329;
B8324 <= B8332 or B8331;
B8325 <= B8327 and B8333;
B8326 <= B8327 and B8334;
B8327 <= ((not B8317) and B8318) or (B8317 and (not B8318));
B8328 <= ((not B8329) and B8319) or (B8329 and (not B8319));
B8329 <= B8337 and B8336;
B8330 <= B8335 and B8319;
B8331 <= B8340 and B8339;
B8332 <= B8338 and B8319;
B8333 <= B8341 or B8318;
B8334 <= (B8319 and B8331) or ((not B8319) and (not B8331));
B8335 <= (not B8344) or (not B8345);
B8336 <= ((not B8320) and B8327) or (B8320 and (not B8327));
B8337 <= B8346 and B8339;
B8338 <= (not B8348) or (not B8347);
B8339 <= B8320 or B8321;
B8340 <= B8320 or B8327;
B8341 <= B8319 and B8331;
B8342 <= (not B8318) or (not B8319);
B8343 <= B8327 and B8342;
B8344 <= (not B8343) and (not B8327);
B8345 <= B8327 or B8342;
B8346 <= (not B8320) or (not B8321);
B8347 <= B8327 or B8342;
B8348 <= (not B8327) and (not B8349);
B8349 <= B8327 and B8342;
B8355 <= B8361 and B8360;
B8356 <= B8363 or B8362;
B8357 <= B8365 or B8364;
B8358 <= B8360 and B8366;
B8359 <= B8360 and B8367;
B8360 <= ((not B8350) and B8351) or (B8350 and (not B8351));
B8361 <= ((not B8362) and B8352) or (B8362 and (not B8352));
B8362 <= B8370 and B8369;
B8363 <= B8368 and B8352;
B8364 <= B8373 and B8372;
B8365 <= B8371 and B8352;
B8366 <= B8374 or B8351;
B8367 <= (B8352 and B8364) or ((not B8352) and (not B8364));
B8368 <= (not B8377) or (not B8378);
B8369 <= ((not B8353) and B8360) or (B8353 and (not B8360));
B8370 <= B8379 and B8372;
B8371 <= (not B8381) or (not B8380);
B8372 <= B8353 or B8354;
B8373 <= B8353 or B8360;
B8374 <= B8352 and B8364;
B8375 <= (not B8351) or (not B8352);
B8376 <= B8360 and B8375;
B8377 <= (not B8376) and (not B8360);
B8378 <= B8360 or B8375;
B8379 <= (not B8353) or (not B8354);
B8380 <= B8360 or B8375;
B8381 <= (not B8360) and (not B8382);
B8382 <= B8360 and B8375;
B8388 <= B8394 and B8393;
B8389 <= B8396 or B8395;
B8390 <= B8398 or B8397;
B8391 <= B8393 and B8399;
B8392 <= B8393 and B8400;
B8393 <= ((not B8383) and B8384) or (B8383 and (not B8384));
B8394 <= ((not B8395) and B8385) or (B8395 and (not B8385));
B8395 <= B8403 and B8402;
B8396 <= B8401 and B8385;
B8397 <= B8406 and B8405;
B8398 <= B8404 and B8385;
B8399 <= B8407 or B8384;
B8400 <= (B8385 and B8397) or ((not B8385) and (not B8397));
B8401 <= (not B8410) or (not B8411);
B8402 <= ((not B8386) and B8393) or (B8386 and (not B8393));
B8403 <= B8412 and B8405;
B8404 <= (not B8414) or (not B8413);
B8405 <= B8386 or B8387;
B8406 <= B8386 or B8393;
B8407 <= B8385 and B8397;
B8408 <= (not B8384) or (not B8385);
B8409 <= B8393 and B8408;
B8410 <= (not B8409) and (not B8393);
B8411 <= B8393 or B8408;
B8412 <= (not B8386) or (not B8387);
B8413 <= B8393 or B8408;
B8414 <= (not B8393) and (not B8415);
B8415 <= B8393 and B8408;
B8421 <= B8427 and B8426;
B8422 <= B8429 or B8428;
B8423 <= B8431 or B8430;
B8424 <= B8426 and B8432;
B8425 <= B8426 and B8433;
B8426 <= ((not B8416) and B8417) or (B8416 and (not B8417));
B8427 <= ((not B8428) and B8418) or (B8428 and (not B8418));
B8428 <= B8436 and B8435;
B8429 <= B8434 and B8418;
B8430 <= B8439 and B8438;
B8431 <= B8437 and B8418;
B8432 <= B8440 or B8417;
B8433 <= (B8418 and B8430) or ((not B8418) and (not B8430));
B8434 <= (not B8443) or (not B8444);
B8435 <= ((not B8419) and B8426) or (B8419 and (not B8426));
B8436 <= B8445 and B8438;
B8437 <= (not B8447) or (not B8446);
B8438 <= B8419 or B8420;
B8439 <= B8419 or B8426;
B8440 <= B8418 and B8430;
B8441 <= (not B8417) or (not B8418);
B8442 <= B8426 and B8441;
B8443 <= (not B8442) and (not B8426);
B8444 <= B8426 or B8441;
B8445 <= (not B8419) or (not B8420);
B8446 <= B8426 or B8441;
B8447 <= (not B8426) and (not B8448);
B8448 <= B8426 and B8441;
B8454 <= B8460 and B8459;
B8455 <= B8462 or B8461;
B8456 <= B8464 or B8463;
B8457 <= B8459 and B8465;
B8458 <= B8459 and B8466;
B8459 <= ((not B8449) and B8450) or (B8449 and (not B8450));
B8460 <= ((not B8461) and B8451) or (B8461 and (not B8451));
B8461 <= B8469 and B8468;
B8462 <= B8467 and B8451;
B8463 <= B8472 and B8471;
B8464 <= B8470 and B8451;
B8465 <= B8473 or B8450;
B8466 <= (B8451 and B8463) or ((not B8451) and (not B8463));
B8467 <= (not B8476) or (not B8477);
B8468 <= ((not B8452) and B8459) or (B8452 and (not B8459));
B8469 <= B8478 and B8471;
B8470 <= (not B8480) or (not B8479);
B8471 <= B8452 or B8453;
B8472 <= B8452 or B8459;
B8473 <= B8451 and B8463;
B8474 <= (not B8450) or (not B8451);
B8475 <= B8459 and B8474;
B8476 <= (not B8475) and (not B8459);
B8477 <= B8459 or B8474;
B8478 <= (not B8452) or (not B8453);
B8479 <= B8459 or B8474;
B8480 <= (not B8459) and (not B8481);
B8481 <= B8459 and B8474;
B8487 <= B8493 and B8492;
B8488 <= B8495 or B8494;
B8489 <= B8497 or B8496;
B8490 <= B8492 and B8498;
B8491 <= B8492 and B8499;
B8492 <= ((not B8482) and B8483) or (B8482 and (not B8483));
B8493 <= ((not B8494) and B8484) or (B8494 and (not B8484));
B8494 <= B8502 and B8501;
B8495 <= B8500 and B8484;
B8496 <= B8505 and B8504;
B8497 <= B8503 and B8484;
B8498 <= B8506 or B8483;
B8499 <= (B8484 and B8496) or ((not B8484) and (not B8496));
B8500 <= (not B8509) or (not B8510);
B8501 <= ((not B8485) and B8492) or (B8485 and (not B8492));
B8502 <= B8511 and B8504;
B8503 <= (not B8513) or (not B8512);
B8504 <= B8485 or B8486;
B8505 <= B8485 or B8492;
B8506 <= B8484 and B8496;
B8507 <= (not B8483) or (not B8484);
B8508 <= B8492 and B8507;
B8509 <= (not B8508) and (not B8492);
B8510 <= B8492 or B8507;
B8511 <= (not B8485) or (not B8486);
B8512 <= B8492 or B8507;
B8513 <= (not B8492) and (not B8514);
B8514 <= B8492 and B8507;
B8520 <= B8526 and B8525;
B8521 <= B8528 or B8527;
B8522 <= B8530 or B8529;
B8523 <= B8525 and B8531;
B8524 <= B8525 and B8532;
B8525 <= ((not B8515) and B8516) or (B8515 and (not B8516));
B8526 <= ((not B8527) and B8517) or (B8527 and (not B8517));
B8527 <= B8535 and B8534;
B8528 <= B8533 and B8517;
B8529 <= B8538 and B8537;
B8530 <= B8536 and B8517;
B8531 <= B8539 or B8516;
B8532 <= (B8517 and B8529) or ((not B8517) and (not B8529));
B8533 <= (not B8542) or (not B8543);
B8534 <= ((not B8518) and B8525) or (B8518 and (not B8525));
B8535 <= B8544 and B8537;
B8536 <= (not B8546) or (not B8545);
B8537 <= B8518 or B8519;
B8538 <= B8518 or B8525;
B8539 <= B8517 and B8529;
B8540 <= (not B8516) or (not B8517);
B8541 <= B8525 and B8540;
B8542 <= (not B8541) and (not B8525);
B8543 <= B8525 or B8540;
B8544 <= (not B8518) or (not B8519);
B8545 <= B8525 or B8540;
B8546 <= (not B8525) and (not B8547);
B8547 <= B8525 and B8540;
B8553 <= B8559 and B8558;
B8554 <= B8561 or B8560;
B8555 <= B8563 or B8562;
B8556 <= B8558 and B8564;
B8557 <= B8558 and B8565;
B8558 <= ((not B8548) and B8549) or (B8548 and (not B8549));
B8559 <= ((not B8560) and B8550) or (B8560 and (not B8550));
B8560 <= B8568 and B8567;
B8561 <= B8566 and B8550;
B8562 <= B8571 and B8570;
B8563 <= B8569 and B8550;
B8564 <= B8572 or B8549;
B8565 <= (B8550 and B8562) or ((not B8550) and (not B8562));
B8566 <= (not B8575) or (not B8576);
B8567 <= ((not B8551) and B8558) or (B8551 and (not B8558));
B8568 <= B8577 and B8570;
B8569 <= (not B8579) or (not B8578);
B8570 <= B8551 or B8552;
B8571 <= B8551 or B8558;
B8572 <= B8550 and B8562;
B8573 <= (not B8549) or (not B8550);
B8574 <= B8558 and B8573;
B8575 <= (not B8574) and (not B8558);
B8576 <= B8558 or B8573;
B8577 <= (not B8551) or (not B8552);
B8578 <= B8558 or B8573;
B8579 <= (not B8558) and (not B8580);
B8580 <= B8558 and B8573;
B8586 <= B8592 and B8591;
B8587 <= B8594 or B8593;
B8588 <= B8596 or B8595;
B8589 <= B8591 and B8597;
B8590 <= B8591 and B8598;
B8591 <= ((not B8581) and B8582) or (B8581 and (not B8582));
B8592 <= ((not B8593) and B8583) or (B8593 and (not B8583));
B8593 <= B8601 and B8600;
B8594 <= B8599 and B8583;
B8595 <= B8604 and B8603;
B8596 <= B8602 and B8583;
B8597 <= B8605 or B8582;
B8598 <= (B8583 and B8595) or ((not B8583) and (not B8595));
B8599 <= (not B8608) or (not B8609);
B8600 <= ((not B8584) and B8591) or (B8584 and (not B8591));
B8601 <= B8610 and B8603;
B8602 <= (not B8612) or (not B8611);
B8603 <= B8584 or B8585;
B8604 <= B8584 or B8591;
B8605 <= B8583 and B8595;
B8606 <= (not B8582) or (not B8583);
B8607 <= B8591 and B8606;
B8608 <= (not B8607) and (not B8591);
B8609 <= B8591 or B8606;
B8610 <= (not B8584) or (not B8585);
B8611 <= B8591 or B8606;
B8612 <= (not B8591) and (not B8613);
B8613 <= B8591 and B8606;
B8619 <= B8625 and B8624;
B8620 <= B8627 or B8626;
B8621 <= B8629 or B8628;
B8622 <= B8624 and B8630;
B8623 <= B8624 and B8631;
B8624 <= ((not B8614) and B8615) or (B8614 and (not B8615));
B8625 <= ((not B8626) and B8616) or (B8626 and (not B8616));
B8626 <= B8634 and B8633;
B8627 <= B8632 and B8616;
B8628 <= B8637 and B8636;
B8629 <= B8635 and B8616;
B8630 <= B8638 or B8615;
B8631 <= (B8616 and B8628) or ((not B8616) and (not B8628));
B8632 <= (not B8641) or (not B8642);
B8633 <= ((not B8617) and B8624) or (B8617 and (not B8624));
B8634 <= B8643 and B8636;
B8635 <= (not B8645) or (not B8644);
B8636 <= B8617 or B8618;
B8637 <= B8617 or B8624;
B8638 <= B8616 and B8628;
B8639 <= (not B8615) or (not B8616);
B8640 <= B8624 and B8639;
B8641 <= (not B8640) and (not B8624);
B8642 <= B8624 or B8639;
B8643 <= (not B8617) or (not B8618);
B8644 <= B8624 or B8639;
B8645 <= (not B8624) and (not B8646);
B8646 <= B8624 and B8639;
B8652 <= B8658 and B8657;
B8653 <= B8660 or B8659;
B8654 <= B8662 or B8661;
B8655 <= B8657 and B8663;
B8656 <= B8657 and B8664;
B8657 <= ((not B8647) and B8648) or (B8647 and (not B8648));
B8658 <= ((not B8659) and B8649) or (B8659 and (not B8649));
B8659 <= B8667 and B8666;
B8660 <= B8665 and B8649;
B8661 <= B8670 and B8669;
B8662 <= B8668 and B8649;
B8663 <= B8671 or B8648;
B8664 <= (B8649 and B8661) or ((not B8649) and (not B8661));
B8665 <= (not B8674) or (not B8675);
B8666 <= ((not B8650) and B8657) or (B8650 and (not B8657));
B8667 <= B8676 and B8669;
B8668 <= (not B8678) or (not B8677);
B8669 <= B8650 or B8651;
B8670 <= B8650 or B8657;
B8671 <= B8649 and B8661;
B8672 <= (not B8648) or (not B8649);
B8673 <= B8657 and B8672;
B8674 <= (not B8673) and (not B8657);
B8675 <= B8657 or B8672;
B8676 <= (not B8650) or (not B8651);
B8677 <= B8657 or B8672;
B8678 <= (not B8657) and (not B8679);
B8679 <= B8657 and B8672;
B8685 <= B8691 and B8690;
B8686 <= B8693 or B8692;
B8687 <= B8695 or B8694;
B8688 <= B8690 and B8696;
B8689 <= B8690 and B8697;
B8690 <= ((not B8680) and B8681) or (B8680 and (not B8681));
B8691 <= ((not B8692) and B8682) or (B8692 and (not B8682));
B8692 <= B8700 and B8699;
B8693 <= B8698 and B8682;
B8694 <= B8703 and B8702;
B8695 <= B8701 and B8682;
B8696 <= B8704 or B8681;
B8697 <= (B8682 and B8694) or ((not B8682) and (not B8694));
B8698 <= (not B8707) or (not B8708);
B8699 <= ((not B8683) and B8690) or (B8683 and (not B8690));
B8700 <= B8709 and B8702;
B8701 <= (not B8711) or (not B8710);
B8702 <= B8683 or B8684;
B8703 <= B8683 or B8690;
B8704 <= B8682 and B8694;
B8705 <= (not B8681) or (not B8682);
B8706 <= B8690 and B8705;
B8707 <= (not B8706) and (not B8690);
B8708 <= B8690 or B8705;
B8709 <= (not B8683) or (not B8684);
B8710 <= B8690 or B8705;
B8711 <= (not B8690) and (not B8712);
B8712 <= B8690 and B8705;
B8718 <= B8724 and B8723;
B8719 <= B8726 or B8725;
B8720 <= B8728 or B8727;
B8721 <= B8723 and B8729;
B8722 <= B8723 and B8730;
B8723 <= ((not B8713) and B8714) or (B8713 and (not B8714));
B8724 <= ((not B8725) and B8715) or (B8725 and (not B8715));
B8725 <= B8733 and B8732;
B8726 <= B8731 and B8715;
B8727 <= B8736 and B8735;
B8728 <= B8734 and B8715;
B8729 <= B8737 or B8714;
B8730 <= (B8715 and B8727) or ((not B8715) and (not B8727));
B8731 <= (not B8740) or (not B8741);
B8732 <= ((not B8716) and B8723) or (B8716 and (not B8723));
B8733 <= B8742 and B8735;
B8734 <= (not B8744) or (not B8743);
B8735 <= B8716 or B8717;
B8736 <= B8716 or B8723;
B8737 <= B8715 and B8727;
B8738 <= (not B8714) or (not B8715);
B8739 <= B8723 and B8738;
B8740 <= (not B8739) and (not B8723);
B8741 <= B8723 or B8738;
B8742 <= (not B8716) or (not B8717);
B8743 <= B8723 or B8738;
B8744 <= (not B8723) and (not B8745);
B8745 <= B8723 and B8738;
B8751 <= B8757 and B8756;
B8752 <= B8759 or B8758;
B8753 <= B8761 or B8760;
B8754 <= B8756 and B8762;
B8755 <= B8756 and B8763;
B8756 <= ((not B8746) and B8747) or (B8746 and (not B8747));
B8757 <= ((not B8758) and B8748) or (B8758 and (not B8748));
B8758 <= B8766 and B8765;
B8759 <= B8764 and B8748;
B8760 <= B8769 and B8768;
B8761 <= B8767 and B8748;
B8762 <= B8770 or B8747;
B8763 <= (B8748 and B8760) or ((not B8748) and (not B8760));
B8764 <= (not B8773) or (not B8774);
B8765 <= ((not B8749) and B8756) or (B8749 and (not B8756));
B8766 <= B8775 and B8768;
B8767 <= (not B8777) or (not B8776);
B8768 <= B8749 or B8750;
B8769 <= B8749 or B8756;
B8770 <= B8748 and B8760;
B8771 <= (not B8747) or (not B8748);
B8772 <= B8756 and B8771;
B8773 <= (not B8772) and (not B8756);
B8774 <= B8756 or B8771;
B8775 <= (not B8749) or (not B8750);
B8776 <= B8756 or B8771;
B8777 <= (not B8756) and (not B8778);
B8778 <= B8756 and B8771;
B8784 <= B8790 and B8789;
B8785 <= B8792 or B8791;
B8786 <= B8794 or B8793;
B8787 <= B8789 and B8795;
B8788 <= B8789 and B8796;
B8789 <= ((not B8779) and B8780) or (B8779 and (not B8780));
B8790 <= ((not B8791) and B8781) or (B8791 and (not B8781));
B8791 <= B8799 and B8798;
B8792 <= B8797 and B8781;
B8793 <= B8802 and B8801;
B8794 <= B8800 and B8781;
B8795 <= B8803 or B8780;
B8796 <= (B8781 and B8793) or ((not B8781) and (not B8793));
B8797 <= (not B8806) or (not B8807);
B8798 <= ((not B8782) and B8789) or (B8782 and (not B8789));
B8799 <= B8808 and B8801;
B8800 <= (not B8810) or (not B8809);
B8801 <= B8782 or B8783;
B8802 <= B8782 or B8789;
B8803 <= B8781 and B8793;
B8804 <= (not B8780) or (not B8781);
B8805 <= B8789 and B8804;
B8806 <= (not B8805) and (not B8789);
B8807 <= B8789 or B8804;
B8808 <= (not B8782) or (not B8783);
B8809 <= B8789 or B8804;
B8810 <= (not B8789) and (not B8811);
B8811 <= B8789 and B8804;
B8817 <= B8823 and B8822;
B8818 <= B8825 or B8824;
B8819 <= B8827 or B8826;
B8820 <= B8822 and B8828;
B8821 <= B8822 and B8829;
B8822 <= ((not B8812) and B8813) or (B8812 and (not B8813));
B8823 <= ((not B8824) and B8814) or (B8824 and (not B8814));
B8824 <= B8832 and B8831;
B8825 <= B8830 and B8814;
B8826 <= B8835 and B8834;
B8827 <= B8833 and B8814;
B8828 <= B8836 or B8813;
B8829 <= (B8814 and B8826) or ((not B8814) and (not B8826));
B8830 <= (not B8839) or (not B8840);
B8831 <= ((not B8815) and B8822) or (B8815 and (not B8822));
B8832 <= B8841 and B8834;
B8833 <= (not B8843) or (not B8842);
B8834 <= B8815 or B8816;
B8835 <= B8815 or B8822;
B8836 <= B8814 and B8826;
B8837 <= (not B8813) or (not B8814);
B8838 <= B8822 and B8837;
B8839 <= (not B8838) and (not B8822);
B8840 <= B8822 or B8837;
B8841 <= (not B8815) or (not B8816);
B8842 <= B8822 or B8837;
B8843 <= (not B8822) and (not B8844);
B8844 <= B8822 and B8837;
B8850 <= B8856 and B8855;
B8851 <= B8858 or B8857;
B8852 <= B8860 or B8859;
B8853 <= B8855 and B8861;
B8854 <= B8855 and B8862;
B8855 <= ((not B8845) and B8846) or (B8845 and (not B8846));
B8856 <= ((not B8857) and B8847) or (B8857 and (not B8847));
B8857 <= B8865 and B8864;
B8858 <= B8863 and B8847;
B8859 <= B8868 and B8867;
B8860 <= B8866 and B8847;
B8861 <= B8869 or B8846;
B8862 <= (B8847 and B8859) or ((not B8847) and (not B8859));
B8863 <= (not B8872) or (not B8873);
B8864 <= ((not B8848) and B8855) or (B8848 and (not B8855));
B8865 <= B8874 and B8867;
B8866 <= (not B8876) or (not B8875);
B8867 <= B8848 or B8849;
B8868 <= B8848 or B8855;
B8869 <= B8847 and B8859;
B8870 <= (not B8846) or (not B8847);
B8871 <= B8855 and B8870;
B8872 <= (not B8871) and (not B8855);
B8873 <= B8855 or B8870;
B8874 <= (not B8848) or (not B8849);
B8875 <= B8855 or B8870;
B8876 <= (not B8855) and (not B8877);
B8877 <= B8855 and B8870;
B8883 <= B8889 and B8888;
B8884 <= B8891 or B8890;
B8885 <= B8893 or B8892;
B8886 <= B8888 and B8894;
B8887 <= B8888 and B8895;
B8888 <= ((not B8878) and B8879) or (B8878 and (not B8879));
B8889 <= ((not B8890) and B8880) or (B8890 and (not B8880));
B8890 <= B8898 and B8897;
B8891 <= B8896 and B8880;
B8892 <= B8901 and B8900;
B8893 <= B8899 and B8880;
B8894 <= B8902 or B8879;
B8895 <= (B8880 and B8892) or ((not B8880) and (not B8892));
B8896 <= (not B8905) or (not B8906);
B8897 <= ((not B8881) and B8888) or (B8881 and (not B8888));
B8898 <= B8907 and B8900;
B8899 <= (not B8909) or (not B8908);
B8900 <= B8881 or B8882;
B8901 <= B8881 or B8888;
B8902 <= B8880 and B8892;
B8903 <= (not B8879) or (not B8880);
B8904 <= B8888 and B8903;
B8905 <= (not B8904) and (not B8888);
B8906 <= B8888 or B8903;
B8907 <= (not B8881) or (not B8882);
B8908 <= B8888 or B8903;
B8909 <= (not B8888) and (not B8910);
B8910 <= B8888 and B8903;
B8916 <= B8922 and B8921;
B8917 <= B8924 or B8923;
B8918 <= B8926 or B8925;
B8919 <= B8921 and B8927;
B8920 <= B8921 and B8928;
B8921 <= ((not B8911) and B8912) or (B8911 and (not B8912));
B8922 <= ((not B8923) and B8913) or (B8923 and (not B8913));
B8923 <= B8931 and B8930;
B8924 <= B8929 and B8913;
B8925 <= B8934 and B8933;
B8926 <= B8932 and B8913;
B8927 <= B8935 or B8912;
B8928 <= (B8913 and B8925) or ((not B8913) and (not B8925));
B8929 <= (not B8938) or (not B8939);
B8930 <= ((not B8914) and B8921) or (B8914 and (not B8921));
B8931 <= B8940 and B8933;
B8932 <= (not B8942) or (not B8941);
B8933 <= B8914 or B8915;
B8934 <= B8914 or B8921;
B8935 <= B8913 and B8925;
B8936 <= (not B8912) or (not B8913);
B8937 <= B8921 and B8936;
B8938 <= (not B8937) and (not B8921);
B8939 <= B8921 or B8936;
B8940 <= (not B8914) or (not B8915);
B8941 <= B8921 or B8936;
B8942 <= (not B8921) and (not B8943);
B8943 <= B8921 and B8936;
B8949 <= B8955 and B8954;
B8950 <= B8957 or B8956;
B8951 <= B8959 or B8958;
B8952 <= B8954 and B8960;
B8953 <= B8954 and B8961;
B8954 <= ((not B8944) and B8945) or (B8944 and (not B8945));
B8955 <= ((not B8956) and B8946) or (B8956 and (not B8946));
B8956 <= B8964 and B8963;
B8957 <= B8962 and B8946;
B8958 <= B8967 and B8966;
B8959 <= B8965 and B8946;
B8960 <= B8968 or B8945;
B8961 <= (B8946 and B8958) or ((not B8946) and (not B8958));
B8962 <= (not B8971) or (not B8972);
B8963 <= ((not B8947) and B8954) or (B8947 and (not B8954));
B8964 <= B8973 and B8966;
B8965 <= (not B8975) or (not B8974);
B8966 <= B8947 or B8948;
B8967 <= B8947 or B8954;
B8968 <= B8946 and B8958;
B8969 <= (not B8945) or (not B8946);
B8970 <= B8954 and B8969;
B8971 <= (not B8970) and (not B8954);
B8972 <= B8954 or B8969;
B8973 <= (not B8947) or (not B8948);
B8974 <= B8954 or B8969;
B8975 <= (not B8954) and (not B8976);
B8976 <= B8954 and B8969;
B8982 <= B8988 and B8987;
B8983 <= B8990 or B8989;
B8984 <= B8992 or B8991;
B8985 <= B8987 and B8993;
B8986 <= B8987 and B8994;
B8987 <= ((not B8977) and B8978) or (B8977 and (not B8978));
B8988 <= ((not B8989) and B8979) or (B8989 and (not B8979));
B8989 <= B8997 and B8996;
B8990 <= B8995 and B8979;
B8991 <= B9000 and B8999;
B8992 <= B8998 and B8979;
B8993 <= B9001 or B8978;
B8994 <= (B8979 and B8991) or ((not B8979) and (not B8991));
B8995 <= (not B9004) or (not B9005);
B8996 <= ((not B8980) and B8987) or (B8980 and (not B8987));
B8997 <= B9006 and B8999;
B8998 <= (not B9008) or (not B9007);
B8999 <= B8980 or B8981;
B9000 <= B8980 or B8987;
B9001 <= B8979 and B8991;
B9002 <= (not B8978) or (not B8979);
B9003 <= B8987 and B9002;
B9004 <= (not B9003) and (not B8987);
B9005 <= B8987 or B9002;
B9006 <= (not B8980) or (not B8981);
B9007 <= B8987 or B9002;
B9008 <= (not B8987) and (not B9009);
B9009 <= B8987 and B9002;
B9015 <= B9021 and B9020;
B9016 <= B9023 or B9022;
B9017 <= B9025 or B9024;
B9018 <= B9020 and B9026;
B9019 <= B9020 and B9027;
B9020 <= ((not B9010) and B9011) or (B9010 and (not B9011));
B9021 <= ((not B9022) and B9012) or (B9022 and (not B9012));
B9022 <= B9030 and B9029;
B9023 <= B9028 and B9012;
B9024 <= B9033 and B9032;
B9025 <= B9031 and B9012;
B9026 <= B9034 or B9011;
B9027 <= (B9012 and B9024) or ((not B9012) and (not B9024));
B9028 <= (not B9037) or (not B9038);
B9029 <= ((not B9013) and B9020) or (B9013 and (not B9020));
B9030 <= B9039 and B9032;
B9031 <= (not B9041) or (not B9040);
B9032 <= B9013 or B9014;
B9033 <= B9013 or B9020;
B9034 <= B9012 and B9024;
B9035 <= (not B9011) or (not B9012);
B9036 <= B9020 and B9035;
B9037 <= (not B9036) and (not B9020);
B9038 <= B9020 or B9035;
B9039 <= (not B9013) or (not B9014);
B9040 <= B9020 or B9035;
B9041 <= (not B9020) and (not B9042);
B9042 <= B9020 and B9035;
B9048 <= B9054 and B9053;
B9049 <= B9056 or B9055;
B9050 <= B9058 or B9057;
B9051 <= B9053 and B9059;
B9052 <= B9053 and B9060;
B9053 <= ((not B9043) and B9044) or (B9043 and (not B9044));
B9054 <= ((not B9055) and B9045) or (B9055 and (not B9045));
B9055 <= B9063 and B9062;
B9056 <= B9061 and B9045;
B9057 <= B9066 and B9065;
B9058 <= B9064 and B9045;
B9059 <= B9067 or B9044;
B9060 <= (B9045 and B9057) or ((not B9045) and (not B9057));
B9061 <= (not B9070) or (not B9071);
B9062 <= ((not B9046) and B9053) or (B9046 and (not B9053));
B9063 <= B9072 and B9065;
B9064 <= (not B9074) or (not B9073);
B9065 <= B9046 or B9047;
B9066 <= B9046 or B9053;
B9067 <= B9045 and B9057;
B9068 <= (not B9044) or (not B9045);
B9069 <= B9053 and B9068;
B9070 <= (not B9069) and (not B9053);
B9071 <= B9053 or B9068;
B9072 <= (not B9046) or (not B9047);
B9073 <= B9053 or B9068;
B9074 <= (not B9053) and (not B9075);
B9075 <= B9053 and B9068;
B9081 <= B9087 and B9086;
B9082 <= B9089 or B9088;
B9083 <= B9091 or B9090;
B9084 <= B9086 and B9092;
B9085 <= B9086 and B9093;
B9086 <= ((not B9076) and B9077) or (B9076 and (not B9077));
B9087 <= ((not B9088) and B9078) or (B9088 and (not B9078));
B9088 <= B9096 and B9095;
B9089 <= B9094 and B9078;
B9090 <= B9099 and B9098;
B9091 <= B9097 and B9078;
B9092 <= B9100 or B9077;
B9093 <= (B9078 and B9090) or ((not B9078) and (not B9090));
B9094 <= (not B9103) or (not B9104);
B9095 <= ((not B9079) and B9086) or (B9079 and (not B9086));
B9096 <= B9105 and B9098;
B9097 <= (not B9107) or (not B9106);
B9098 <= B9079 or B9080;
B9099 <= B9079 or B9086;
B9100 <= B9078 and B9090;
B9101 <= (not B9077) or (not B9078);
B9102 <= B9086 and B9101;
B9103 <= (not B9102) and (not B9086);
B9104 <= B9086 or B9101;
B9105 <= (not B9079) or (not B9080);
B9106 <= B9086 or B9101;
B9107 <= (not B9086) and (not B9108);
B9108 <= B9086 and B9101;
B9114 <= B9120 and B9119;
B9115 <= B9122 or B9121;
B9116 <= B9124 or B9123;
B9117 <= B9119 and B9125;
B9118 <= B9119 and B9126;
B9119 <= ((not B9109) and B9110) or (B9109 and (not B9110));
B9120 <= ((not B9121) and B9111) or (B9121 and (not B9111));
B9121 <= B9129 and B9128;
B9122 <= B9127 and B9111;
B9123 <= B9132 and B9131;
B9124 <= B9130 and B9111;
B9125 <= B9133 or B9110;
B9126 <= (B9111 and B9123) or ((not B9111) and (not B9123));
B9127 <= (not B9136) or (not B9137);
B9128 <= ((not B9112) and B9119) or (B9112 and (not B9119));
B9129 <= B9138 and B9131;
B9130 <= (not B9140) or (not B9139);
B9131 <= B9112 or B9113;
B9132 <= B9112 or B9119;
B9133 <= B9111 and B9123;
B9134 <= (not B9110) or (not B9111);
B9135 <= B9119 and B9134;
B9136 <= (not B9135) and (not B9119);
B9137 <= B9119 or B9134;
B9138 <= (not B9112) or (not B9113);
B9139 <= B9119 or B9134;
B9140 <= (not B9119) and (not B9141);
B9141 <= B9119 and B9134;
B9147 <= B9153 and B9152;
B9148 <= B9155 or B9154;
B9149 <= B9157 or B9156;
B9150 <= B9152 and B9158;
B9151 <= B9152 and B9159;
B9152 <= ((not B9142) and B9143) or (B9142 and (not B9143));
B9153 <= ((not B9154) and B9144) or (B9154 and (not B9144));
B9154 <= B9162 and B9161;
B9155 <= B9160 and B9144;
B9156 <= B9165 and B9164;
B9157 <= B9163 and B9144;
B9158 <= B9166 or B9143;
B9159 <= (B9144 and B9156) or ((not B9144) and (not B9156));
B9160 <= (not B9169) or (not B9170);
B9161 <= ((not B9145) and B9152) or (B9145 and (not B9152));
B9162 <= B9171 and B9164;
B9163 <= (not B9173) or (not B9172);
B9164 <= B9145 or B9146;
B9165 <= B9145 or B9152;
B9166 <= B9144 and B9156;
B9167 <= (not B9143) or (not B9144);
B9168 <= B9152 and B9167;
B9169 <= (not B9168) and (not B9152);
B9170 <= B9152 or B9167;
B9171 <= (not B9145) or (not B9146);
B9172 <= B9152 or B9167;
B9173 <= (not B9152) and (not B9174);
B9174 <= B9152 and B9167;
B9180 <= B9186 and B9185;
B9181 <= B9188 or B9187;
B9182 <= B9190 or B9189;
B9183 <= B9185 and B9191;
B9184 <= B9185 and B9192;
B9185 <= ((not B9175) and B9176) or (B9175 and (not B9176));
B9186 <= ((not B9187) and B9177) or (B9187 and (not B9177));
B9187 <= B9195 and B9194;
B9188 <= B9193 and B9177;
B9189 <= B9198 and B9197;
B9190 <= B9196 and B9177;
B9191 <= B9199 or B9176;
B9192 <= (B9177 and B9189) or ((not B9177) and (not B9189));
B9193 <= (not B9202) or (not B9203);
B9194 <= ((not B9178) and B9185) or (B9178 and (not B9185));
B9195 <= B9204 and B9197;
B9196 <= (not B9206) or (not B9205);
B9197 <= B9178 or B9179;
B9198 <= B9178 or B9185;
B9199 <= B9177 and B9189;
B9200 <= (not B9176) or (not B9177);
B9201 <= B9185 and B9200;
B9202 <= (not B9201) and (not B9185);
B9203 <= B9185 or B9200;
B9204 <= (not B9178) or (not B9179);
B9205 <= B9185 or B9200;
B9206 <= (not B9185) and (not B9207);
B9207 <= B9185 and B9200;
B9213 <= B9219 and B9218;
B9214 <= B9221 or B9220;
B9215 <= B9223 or B9222;
B9216 <= B9218 and B9224;
B9217 <= B9218 and B9225;
B9218 <= ((not B9208) and B9209) or (B9208 and (not B9209));
B9219 <= ((not B9220) and B9210) or (B9220 and (not B9210));
B9220 <= B9228 and B9227;
B9221 <= B9226 and B9210;
B9222 <= B9231 and B9230;
B9223 <= B9229 and B9210;
B9224 <= B9232 or B9209;
B9225 <= (B9210 and B9222) or ((not B9210) and (not B9222));
B9226 <= (not B9235) or (not B9236);
B9227 <= ((not B9211) and B9218) or (B9211 and (not B9218));
B9228 <= B9237 and B9230;
B9229 <= (not B9239) or (not B9238);
B9230 <= B9211 or B9212;
B9231 <= B9211 or B9218;
B9232 <= B9210 and B9222;
B9233 <= (not B9209) or (not B9210);
B9234 <= B9218 and B9233;
B9235 <= (not B9234) and (not B9218);
B9236 <= B9218 or B9233;
B9237 <= (not B9211) or (not B9212);
B9238 <= B9218 or B9233;
B9239 <= (not B9218) and (not B9240);
B9240 <= B9218 and B9233;
B9246 <= B9252 and B9251;
B9247 <= B9254 or B9253;
B9248 <= B9256 or B9255;
B9249 <= B9251 and B9257;
B9250 <= B9251 and B9258;
B9251 <= ((not B9241) and B9242) or (B9241 and (not B9242));
B9252 <= ((not B9253) and B9243) or (B9253 and (not B9243));
B9253 <= B9261 and B9260;
B9254 <= B9259 and B9243;
B9255 <= B9264 and B9263;
B9256 <= B9262 and B9243;
B9257 <= B9265 or B9242;
B9258 <= (B9243 and B9255) or ((not B9243) and (not B9255));
B9259 <= (not B9268) or (not B9269);
B9260 <= ((not B9244) and B9251) or (B9244 and (not B9251));
B9261 <= B9270 and B9263;
B9262 <= (not B9272) or (not B9271);
B9263 <= B9244 or B9245;
B9264 <= B9244 or B9251;
B9265 <= B9243 and B9255;
B9266 <= (not B9242) or (not B9243);
B9267 <= B9251 and B9266;
B9268 <= (not B9267) and (not B9251);
B9269 <= B9251 or B9266;
B9270 <= (not B9244) or (not B9245);
B9271 <= B9251 or B9266;
B9272 <= (not B9251) and (not B9273);
B9273 <= B9251 and B9266;
B9279 <= B9285 and B9284;
B9280 <= B9287 or B9286;
B9281 <= B9289 or B9288;
B9282 <= B9284 and B9290;
B9283 <= B9284 and B9291;
B9284 <= ((not B9274) and B9275) or (B9274 and (not B9275));
B9285 <= ((not B9286) and B9276) or (B9286 and (not B9276));
B9286 <= B9294 and B9293;
B9287 <= B9292 and B9276;
B9288 <= B9297 and B9296;
B9289 <= B9295 and B9276;
B9290 <= B9298 or B9275;
B9291 <= (B9276 and B9288) or ((not B9276) and (not B9288));
B9292 <= (not B9301) or (not B9302);
B9293 <= ((not B9277) and B9284) or (B9277 and (not B9284));
B9294 <= B9303 and B9296;
B9295 <= (not B9305) or (not B9304);
B9296 <= B9277 or B9278;
B9297 <= B9277 or B9284;
B9298 <= B9276 and B9288;
B9299 <= (not B9275) or (not B9276);
B9300 <= B9284 and B9299;
B9301 <= (not B9300) and (not B9284);
B9302 <= B9284 or B9299;
B9303 <= (not B9277) or (not B9278);
B9304 <= B9284 or B9299;
B9305 <= (not B9284) and (not B9306);
B9306 <= B9284 and B9299;
B1089 <= B1067 and B1082;
B1088 <= (not B1067) and (not B1089);
B1087 <= B1067 or B1082;
B1086 <= (not B1060) or (not B1061);
B1085 <= B1067 or B1082;
B1084 <= (not B1083) and (not B1067);
B1083 <= B1067 and B1082;
B1082 <= (not B1058) or (not B1059);
B1081 <= B1059 and B1071;
B1080 <= B1060 or B1067;
B1079 <= B1060 or B1061;
B1078 <= (not B1088) or (not B1087);
B1077 <= B1086 and B1079;
B1076 <= ((not B1060) and B1067) or (B1060 and (not B1067));
B1075 <= (not B1084) or (not B1085);
B1074 <= (B1059 and B1071) or ((not B1059) and (not B1071));
B1073 <= B1081 or B1058;
B1072 <= B1078 and B1059;
B1071 <= B1080 and B1079;
B1070 <= B1075 and B1059;
B1069 <= B1077 and B1076;
B1068 <= ((not B1069) and B1059) or (B1069 and (not B1059));
B1067 <= ((not B1057) and B1058) or (B1057 and (not B1058));
B1066 <= B1067 and B1074;
B1065 <= B1067 and B1073;
B1064 <= B1072 or B1071;
B1063 <= B1070 or B1069;
B1062 <= B1068 and B1067;
B1061 <= B5191;
B1060 <= B5220;
B1059 <= B5253;
B1058 <= B5286;
B1057 <= B5319;
B1090 <= B5352;
B1091 <= B5385;
B1092 <= B5418;
B1093 <= B5451;
B1094 <= B5484;
B1095 <= B1101 and B1100;
B1096 <= B1103 or B1102;
B1097 <= B1105 or B1104;
B1098 <= B1100 and B1106;
B1099 <= B1100 and B1107;
B1100 <= ((not B1090) and B1091) or (B1090 and (not B1091));
B1101 <= ((not B1102) and B1092) or (B1102 and (not B1092));
B1102 <= B1110 and B1109;
B1103 <= B1108 and B1092;
B1104 <= B1113 and B1112;
B1105 <= B1111 and B1092;
B1106 <= B1114 or B1091;
B1107 <= (B1092 and B1104) or ((not B1092) and (not B1104));
B1108 <= (not B1117) or (not B1118);
B1109 <= ((not B1093) and B1100) or (B1093 and (not B1100));
B1110 <= B1119 and B1112;
B1111 <= (not B1121) or (not B1120);
B1112 <= B1093 or B1094;
B1113 <= B1093 or B1100;
B1114 <= B1092 and B1104;
B1115 <= (not B1091) or (not B1092);
B1116 <= B1100 and B1115;
B1117 <= (not B1116) and (not B1100);
B1118 <= B1100 or B1115;
B1119 <= (not B1093) or (not B1094);
B1120 <= B1100 or B1115;
B1121 <= (not B1100) and (not B1122);
B1122 <= B1100 and B1115;
B1123 <= B5517;
B1124 <= B5550;
B1125 <= B5583;
B1126 <= B5616;
B1127 <= B5649;
B1128 <= B1134 and B1133;
B1129 <= B1136 or B1135;
B1130 <= B1138 or B1137;
B1131 <= B1133 and B1139;
B1132 <= B1133 and B1140;
B1133 <= ((not B1123) and B1124) or (B1123 and (not B1124));
B1134 <= ((not B1135) and B1125) or (B1135 and (not B1125));
B1135 <= B1143 and B1142;
B1136 <= B1141 and B1125;
B1137 <= B1146 and B1145;
B1138 <= B1144 and B1125;
B1139 <= B1147 or B1124;
B1140 <= (B1125 and B1137) or ((not B1125) and (not B1137));
B1141 <= (not B1150) or (not B1151);
B1142 <= ((not B1126) and B1133) or (B1126 and (not B1133));
B1143 <= B1152 and B1145;
B1144 <= (not B1154) or (not B1153);
B1145 <= B1126 or B1127;
B1146 <= B1126 or B1133;
B1147 <= B1125 and B1137;
B1148 <= (not B1124) or (not B1125);
B1149 <= B1133 and B1148;
B1150 <= (not B1149) and (not B1133);
B1151 <= B1133 or B1148;
B1152 <= (not B1126) or (not B1127);
B1153 <= B1133 or B1148;
B1154 <= (not B1133) and (not B1155);
B1155 <= B1133 and B1148;
B1156 <= B5682;
B1157 <= B5715;
B1158 <= B5748;
B1159 <= B5781;
B1160 <= B5814;
B1161 <= B1167 and B1166;
B1162 <= B1169 or B1168;
B1163 <= B1171 or B1170;
B1164 <= B1166 and B1172;
B1165 <= B1166 and B1173;
B1166 <= ((not B1156) and B1157) or (B1156 and (not B1157));
B1167 <= ((not B1168) and B1158) or (B1168 and (not B1158));
B1168 <= B1176 and B1175;
B1169 <= B1174 and B1158;
B1170 <= B1179 and B1178;
B1171 <= B1177 and B1158;
B1172 <= B1180 or B1157;
B1173 <= (B1158 and B1170) or ((not B1158) and (not B1170));
B1174 <= (not B1183) or (not B1184);
B1175 <= ((not B1159) and B1166) or (B1159 and (not B1166));
B1176 <= B1185 and B1178;
B1177 <= (not B1187) or (not B1186);
B1178 <= B1159 or B1160;
B1179 <= B1159 or B1166;
B1180 <= B1158 and B1170;
B1181 <= (not B1157) or (not B1158);
B1182 <= B1166 and B1181;
B1183 <= (not B1182) and (not B1166);
B1184 <= B1166 or B1181;
B1185 <= (not B1159) or (not B1160);
B1186 <= B1166 or B1181;
B1187 <= (not B1166) and (not B1188);
B1188 <= B1166 and B1181;
B1189 <= B5847;
B1190 <= B5880;
B1191 <= B5913;
B1192 <= B5946;
B1193 <= B5979;
B1194 <= B1200 and B1199;
B1195 <= B1202 or B1201;
B1196 <= B1204 or B1203;
B1197 <= B1199 and B1205;
B1198 <= B1199 and B1206;
B1199 <= ((not B1189) and B1190) or (B1189 and (not B1190));
B1200 <= ((not B1201) and B1191) or (B1201 and (not B1191));
B1201 <= B1209 and B1208;
B1202 <= B1207 and B1191;
B1203 <= B1212 and B1211;
B1204 <= B1210 and B1191;
B1205 <= B1213 or B1190;
B1206 <= (B1191 and B1203) or ((not B1191) and (not B1203));
B1207 <= (not B1216) or (not B1217);
B1208 <= ((not B1192) and B1199) or (B1192 and (not B1199));
B1209 <= B1218 and B1211;
B1210 <= (not B1220) or (not B1219);
B1211 <= B1192 or B1193;
B1212 <= B1192 or B1199;
B1213 <= B1191 and B1203;
B1214 <= (not B1190) or (not B1191);
B1215 <= B1199 and B1214;
B1216 <= (not B1215) and (not B1199);
B1217 <= B1199 or B1214;
B1218 <= (not B1192) or (not B1193);
B1219 <= B1199 or B1214;
B1220 <= (not B1199) and (not B1221);
B1221 <= B1199 and B1214;
B1222 <= B6012;
B1223 <= B6045;
B1224 <= B6078;
B1225 <= B6111;
B1226 <= B6144;
B1227 <= B1233 and B1232;
B1228 <= B1235 or B1234;
B1229 <= B1237 or B1236;
B1230 <= B1232 and B1238;
B1231 <= B1232 and B1239;
B1232 <= ((not B1222) and B1223) or (B1222 and (not B1223));
B1233 <= ((not B1234) and B1224) or (B1234 and (not B1224));
B1234 <= B1242 and B1241;
B1235 <= B1240 and B1224;
B1236 <= B1245 and B1244;
B1237 <= B1243 and B1224;
B1238 <= B1246 or B1223;
B1239 <= (B1224 and B1236) or ((not B1224) and (not B1236));
B1240 <= (not B1249) or (not B1250);
B1241 <= ((not B1225) and B1232) or (B1225 and (not B1232));
B1242 <= B1251 and B1244;
B1243 <= (not B1253) or (not B1252);
B1244 <= B1225 or B1226;
B1245 <= B1225 or B1232;
B1246 <= B1224 and B1236;
B1247 <= (not B1223) or (not B1224);
B1248 <= B1232 and B1247;
B1249 <= (not B1248) and (not B1232);
B1250 <= B1232 or B1247;
B1251 <= (not B1225) or (not B1226);
B1252 <= B1232 or B1247;
B1253 <= (not B1232) and (not B1254);
B1254 <= B1232 and B1247;
B1255 <= B6177;
B1256 <= B6210;
B1257 <= B6243;
B1258 <= B6276;
B1259 <= B6309;
B1260 <= B1266 and B1265;
B1261 <= B1268 or B1267;
B1262 <= B1270 or B1269;
B1263 <= B1265 and B1271;
B1264 <= B1265 and B1272;
B1265 <= ((not B1255) and B1256) or (B1255 and (not B1256));
B1266 <= ((not B1267) and B1257) or (B1267 and (not B1257));
B1267 <= B1275 and B1274;
B1268 <= B1273 and B1257;
B1269 <= B1278 and B1277;
B1270 <= B1276 and B1257;
B1271 <= B1279 or B1256;
B1272 <= (B1257 and B1269) or ((not B1257) and (not B1269));
B1273 <= (not B1282) or (not B1283);
B1274 <= ((not B1258) and B1265) or (B1258 and (not B1265));
B1275 <= B1284 and B1277;
B1276 <= (not B1286) or (not B1285);
B1277 <= B1258 or B1259;
B1278 <= B1258 or B1265;
B1279 <= B1257 and B1269;
B1280 <= (not B1256) or (not B1257);
B1281 <= B1265 and B1280;
B1282 <= (not B1281) and (not B1265);
B1283 <= B1265 or B1280;
B1284 <= (not B1258) or (not B1259);
B1285 <= B1265 or B1280;
B1286 <= (not B1265) and (not B1287);
B1287 <= B1265 and B1280;
B1288 <= B6342;
B1289 <= B6375;
B1290 <= B6408;
B1291 <= B6441;
B1292 <= B6474;
B1293 <= B1299 and B1298;
B1294 <= B1301 or B1300;
B1295 <= B1303 or B1302;
B1296 <= B1298 and B1304;
B1297 <= B1298 and B1305;
B1298 <= ((not B1288) and B1289) or (B1288 and (not B1289));
B1299 <= ((not B1300) and B1290) or (B1300 and (not B1290));
B1300 <= B1308 and B1307;
B1301 <= B1306 and B1290;
B1302 <= B1311 and B1310;
B1303 <= B1309 and B1290;
B1304 <= B1312 or B1289;
B1305 <= (B1290 and B1302) or ((not B1290) and (not B1302));
B1306 <= (not B1315) or (not B1316);
B1307 <= ((not B1291) and B1298) or (B1291 and (not B1298));
B1308 <= B1317 and B1310;
B1309 <= (not B1319) or (not B1318);
B1310 <= B1291 or B1292;
B1311 <= B1291 or B1298;
B1312 <= B1290 and B1302;
B1313 <= (not B1289) or (not B1290);
B1314 <= B1298 and B1313;
B1315 <= (not B1314) and (not B1298);
B1316 <= B1298 or B1313;
B1317 <= (not B1291) or (not B1292);
B1318 <= B1298 or B1313;
B1319 <= (not B1298) and (not B1320);
B1320 <= B1298 and B1313;
B1321 <= B6507;
B1322 <= B6540;
B1323 <= B6573;
B1324 <= B6606;
B1325 <= B6639;
B1326 <= B1332 and B1331;
B1327 <= B1334 or B1333;
B1328 <= B1336 or B1335;
B1329 <= B1331 and B1337;
B1330 <= B1331 and B1338;
B1331 <= ((not B1321) and B1322) or (B1321 and (not B1322));
B1332 <= ((not B1333) and B1323) or (B1333 and (not B1323));
B1333 <= B1341 and B1340;
B1334 <= B1339 and B1323;
B1335 <= B1344 and B1343;
B1336 <= B1342 and B1323;
B1337 <= B1345 or B1322;
B1338 <= (B1323 and B1335) or ((not B1323) and (not B1335));
B1339 <= (not B1348) or (not B1349);
B1340 <= ((not B1324) and B1331) or (B1324 and (not B1331));
B1341 <= B1350 and B1343;
B1342 <= (not B1352) or (not B1351);
B1343 <= B1324 or B1325;
B1344 <= B1324 or B1331;
B1345 <= B1323 and B1335;
B1346 <= (not B1322) or (not B1323);
B1347 <= B1331 and B1346;
B1348 <= (not B1347) and (not B1331);
B1349 <= B1331 or B1346;
B1350 <= (not B1324) or (not B1325);
B1351 <= B1331 or B1346;
B1352 <= (not B1331) and (not B1353);
B1353 <= B1331 and B1346;
B1354 <= B6672;
B1355 <= B6705;
B1356 <= B6738;
B1357 <= B6771;
B1358 <= B6804;
B1359 <= B1365 and B1364;
B1360 <= B1367 or B1366;
B1361 <= B1369 or B1368;
B1362 <= B1364 and B1370;
B1363 <= B1364 and B1371;
B1364 <= ((not B1354) and B1355) or (B1354 and (not B1355));
B1365 <= ((not B1366) and B1356) or (B1366 and (not B1356));
B1366 <= B1374 and B1373;
B1367 <= B1372 and B1356;
B1368 <= B1377 and B1376;
B1369 <= B1375 and B1356;
B1370 <= B1378 or B1355;
B1371 <= (B1356 and B1368) or ((not B1356) and (not B1368));
B1372 <= (not B1381) or (not B1382);
B1373 <= ((not B1357) and B1364) or (B1357 and (not B1364));
B1374 <= B1383 and B1376;
B1375 <= (not B1385) or (not B1384);
B1376 <= B1357 or B1358;
B1377 <= B1357 or B1364;
B1378 <= B1356 and B1368;
B1379 <= (not B1355) or (not B1356);
B1380 <= B1364 and B1379;
B1381 <= (not B1380) and (not B1364);
B1382 <= B1364 or B1379;
B1383 <= (not B1357) or (not B1358);
B1384 <= B1364 or B1379;
B1385 <= (not B1364) and (not B1386);
B1386 <= B1364 and B1379;
B1387 <= B6837;
B1388 <= B6870;
B1389 <= B6903;
B1390 <= B6936;
B1391 <= B6969;
B1392 <= B1398 and B1397;
B1393 <= B1400 or B1399;
B1394 <= B1402 or B1401;
B1395 <= B1397 and B1403;
B1396 <= B1397 and B1404;
B1397 <= ((not B1387) and B1388) or (B1387 and (not B1388));
B1398 <= ((not B1399) and B1389) or (B1399 and (not B1389));
B1399 <= B1407 and B1406;
B1400 <= B1405 and B1389;
B1401 <= B1410 and B1409;
B1402 <= B1408 and B1389;
B1403 <= B1411 or B1388;
B1404 <= (B1389 and B1401) or ((not B1389) and (not B1401));
B1405 <= (not B1414) or (not B1415);
B1406 <= ((not B1390) and B1397) or (B1390 and (not B1397));
B1407 <= B1416 and B1409;
B1408 <= (not B1418) or (not B1417);
B1409 <= B1390 or B1391;
B1410 <= B1390 or B1397;
B1411 <= B1389 and B1401;
B1412 <= (not B1388) or (not B1389);
B1413 <= B1397 and B1412;
B1414 <= (not B1413) and (not B1397);
B1415 <= B1397 or B1412;
B1416 <= (not B1390) or (not B1391);
B1417 <= B1397 or B1412;
B1418 <= (not B1397) and (not B1419);
B1419 <= B1397 and B1412;
B1420 <= B7002;
B1421 <= B7035;
B1422 <= B7068;
B1423 <= B7101;
B1424 <= B7134;
B1425 <= B1431 and B1430;
B1426 <= B1433 or B1432;
B1427 <= B1435 or B1434;
B1428 <= B1430 and B1436;
B1429 <= B1430 and B1437;
B1430 <= ((not B1420) and B1421) or (B1420 and (not B1421));
B1431 <= ((not B1432) and B1422) or (B1432 and (not B1422));
B1432 <= B1440 and B1439;
B1433 <= B1438 and B1422;
B1434 <= B1443 and B1442;
B1435 <= B1441 and B1422;
B1436 <= B1444 or B1421;
B1437 <= (B1422 and B1434) or ((not B1422) and (not B1434));
B1438 <= (not B1447) or (not B1448);
B1439 <= ((not B1423) and B1430) or (B1423 and (not B1430));
B1440 <= B1449 and B1442;
B1441 <= (not B1451) or (not B1450);
B1442 <= B1423 or B1424;
B1443 <= B1423 or B1430;
B1444 <= B1422 and B1434;
B1445 <= (not B1421) or (not B1422);
B1446 <= B1430 and B1445;
B1447 <= (not B1446) and (not B1430);
B1448 <= B1430 or B1445;
B1449 <= (not B1423) or (not B1424);
B1450 <= B1430 or B1445;
B1451 <= (not B1430) and (not B1452);
B1452 <= B1430 and B1445;
B1453 <= B7167;
B1454 <= B7200;
B1455 <= B7233;
B1456 <= B7266;
B1457 <= B7299;
B1458 <= B1464 and B1463;
B1459 <= B1466 or B1465;
B1460 <= B1468 or B1467;
B1461 <= B1463 and B1469;
B1462 <= B1463 and B1470;
B1463 <= ((not B1453) and B1454) or (B1453 and (not B1454));
B1464 <= ((not B1465) and B1455) or (B1465 and (not B1455));
B1465 <= B1473 and B1472;
B1466 <= B1471 and B1455;
B1467 <= B1476 and B1475;
B1468 <= B1474 and B1455;
B1469 <= B1477 or B1454;
B1470 <= (B1455 and B1467) or ((not B1455) and (not B1467));
B1471 <= (not B1480) or (not B1481);
B1472 <= ((not B1456) and B1463) or (B1456 and (not B1463));
B1473 <= B1482 and B1475;
B1474 <= (not B1484) or (not B1483);
B1475 <= B1456 or B1457;
B1476 <= B1456 or B1463;
B1477 <= B1455 and B1467;
B1478 <= (not B1454) or (not B1455);
B1479 <= B1463 and B1478;
B1480 <= (not B1479) and (not B1463);
B1481 <= B1463 or B1478;
B1482 <= (not B1456) or (not B1457);
B1483 <= B1463 or B1478;
B1484 <= (not B1463) and (not B1485);
B1485 <= B1463 and B1478;
B1486 <= B7332;
B1487 <= B7365;
B1488 <= B7398;
B1489 <= B7431;
B1490 <= B7464;
B1491 <= B1497 and B1496;
B1492 <= B1499 or B1498;
B1493 <= B1501 or B1500;
B1494 <= B1496 and B1502;
B1495 <= B1496 and B1503;
B1496 <= ((not B1486) and B1487) or (B1486 and (not B1487));
B1497 <= ((not B1498) and B1488) or (B1498 and (not B1488));
B1498 <= B1506 and B1505;
B1499 <= B1504 and B1488;
B1500 <= B1509 and B1508;
B1501 <= B1507 and B1488;
B1502 <= B1510 or B1487;
B1503 <= (B1488 and B1500) or ((not B1488) and (not B1500));
B1504 <= (not B1513) or (not B1514);
B1505 <= ((not B1489) and B1496) or (B1489 and (not B1496));
B1506 <= B1515 and B1508;
B1507 <= (not B1517) or (not B1516);
B1508 <= B1489 or B1490;
B1509 <= B1489 or B1496;
B1510 <= B1488 and B1500;
B1511 <= (not B1487) or (not B1488);
B1512 <= B1496 and B1511;
B1513 <= (not B1512) and (not B1496);
B1514 <= B1496 or B1511;
B1515 <= (not B1489) or (not B1490);
B1516 <= B1496 or B1511;
B1517 <= (not B1496) and (not B1518);
B1518 <= B1496 and B1511;
B1519 <= B7497;
B1520 <= B7530;
B1521 <= B7563;
B1522 <= B7596;
B1523 <= B7629;
B1524 <= B1530 and B1529;
B1525 <= B1532 or B1531;
B1526 <= B1534 or B1533;
B1527 <= B1529 and B1535;
B1528 <= B1529 and B1536;
B1529 <= ((not B1519) and B1520) or (B1519 and (not B1520));
B1530 <= ((not B1531) and B1521) or (B1531 and (not B1521));
B1531 <= B1539 and B1538;
B1532 <= B1537 and B1521;
B1533 <= B1542 and B1541;
B1534 <= B1540 and B1521;
B1535 <= B1543 or B1520;
B1536 <= (B1521 and B1533) or ((not B1521) and (not B1533));
B1537 <= (not B1546) or (not B1547);
B1538 <= ((not B1522) and B1529) or (B1522 and (not B1529));
B1539 <= B1548 and B1541;
B1540 <= (not B1550) or (not B1549);
B1541 <= B1522 or B1523;
B1542 <= B1522 or B1529;
B1543 <= B1521 and B1533;
B1544 <= (not B1520) or (not B1521);
B1545 <= B1529 and B1544;
B1546 <= (not B1545) and (not B1529);
B1547 <= B1529 or B1544;
B1548 <= (not B1522) or (not B1523);
B1549 <= B1529 or B1544;
B1550 <= (not B1529) and (not B1551);
B1551 <= B1529 and B1544;
B1552 <= B7662;
B1553 <= B7695;
B1554 <= B7728;
B1555 <= B7761;
B1556 <= B7794;
B1557 <= B1563 and B1562;
B1558 <= B1565 or B1564;
B1559 <= B1567 or B1566;
B1560 <= B1562 and B1568;
B1561 <= B1562 and B1569;
B1562 <= ((not B1552) and B1553) or (B1552 and (not B1553));
B1563 <= ((not B1564) and B1554) or (B1564 and (not B1554));
B1564 <= B1572 and B1571;
B1565 <= B1570 and B1554;
B1566 <= B1575 and B1574;
B1567 <= B1573 and B1554;
B1568 <= B1576 or B1553;
B1569 <= (B1554 and B1566) or ((not B1554) and (not B1566));
B1570 <= (not B1579) or (not B1580);
B1571 <= ((not B1555) and B1562) or (B1555 and (not B1562));
B1572 <= B1581 and B1574;
B1573 <= (not B1583) or (not B1582);
B1574 <= B1555 or B1556;
B1575 <= B1555 or B1562;
B1576 <= B1554 and B1566;
B1577 <= (not B1553) or (not B1554);
B1578 <= B1562 and B1577;
B1579 <= (not B1578) and (not B1562);
B1580 <= B1562 or B1577;
B1581 <= (not B1555) or (not B1556);
B1582 <= B1562 or B1577;
B1583 <= (not B1562) and (not B1584);
B1584 <= B1562 and B1577;
B1585 <= B7827;
B1586 <= B7860;
B1587 <= B7893;
B1588 <= B7926;
B1589 <= B7959;
B1590 <= B1596 and B1595;
B1591 <= B1598 or B1597;
B1592 <= B1600 or B1599;
B1593 <= B1595 and B1601;
B1594 <= B1595 and B1602;
B1595 <= ((not B1585) and B1586) or (B1585 and (not B1586));
B1596 <= ((not B1597) and B1587) or (B1597 and (not B1587));
B1597 <= B1605 and B1604;
B1598 <= B1603 and B1587;
B1599 <= B1608 and B1607;
B1600 <= B1606 and B1587;
B1601 <= B1609 or B1586;
B1602 <= (B1587 and B1599) or ((not B1587) and (not B1599));
B1603 <= (not B1612) or (not B1613);
B1604 <= ((not B1588) and B1595) or (B1588 and (not B1595));
B1605 <= B1614 and B1607;
B1606 <= (not B1616) or (not B1615);
B1607 <= B1588 or B1589;
B1608 <= B1588 or B1595;
B1609 <= B1587 and B1599;
B1610 <= (not B1586) or (not B1587);
B1611 <= B1595 and B1610;
B1612 <= (not B1611) and (not B1595);
B1613 <= B1595 or B1610;
B1614 <= (not B1588) or (not B1589);
B1615 <= B1595 or B1610;
B1616 <= (not B1595) and (not B1617);
B1617 <= B1595 and B1610;
B1618 <= B7992;
B1619 <= B8025;
B1620 <= B8058;
B1621 <= B8091;
B1622 <= B8124;
B1623 <= B1629 and B1628;
B1624 <= B1631 or B1630;
B1625 <= B1633 or B1632;
B1626 <= B1628 and B1634;
B1627 <= B1628 and B1635;
B1628 <= ((not B1618) and B1619) or (B1618 and (not B1619));
B1629 <= ((not B1630) and B1620) or (B1630 and (not B1620));
B1630 <= B1638 and B1637;
B1631 <= B1636 and B1620;
B1632 <= B1641 and B1640;
B1633 <= B1639 and B1620;
B1634 <= B1642 or B1619;
B1635 <= (B1620 and B1632) or ((not B1620) and (not B1632));
B1636 <= (not B1645) or (not B1646);
B1637 <= ((not B1621) and B1628) or (B1621 and (not B1628));
B1638 <= B1647 and B1640;
B1639 <= (not B1649) or (not B1648);
B1640 <= B1621 or B1622;
B1641 <= B1621 or B1628;
B1642 <= B1620 and B1632;
B1643 <= (not B1619) or (not B1620);
B1644 <= B1628 and B1643;
B1645 <= (not B1644) and (not B1628);
B1646 <= B1628 or B1643;
B1647 <= (not B1621) or (not B1622);
B1648 <= B1628 or B1643;
B1649 <= (not B1628) and (not B1650);
B1650 <= B1628 and B1643;
B1651 <= B8157;
B1652 <= B8190;
B1653 <= B8223;
B1654 <= B8256;
B1655 <= B8289;
B1656 <= B1662 and B1661;
B1657 <= B1664 or B1663;
B1658 <= B1666 or B1665;
B1659 <= B1661 and B1667;
B1660 <= B1661 and B1668;
B1661 <= ((not B1651) and B1652) or (B1651 and (not B1652));
B1662 <= ((not B1663) and B1653) or (B1663 and (not B1653));
B1663 <= B1671 and B1670;
B1664 <= B1669 and B1653;
B1665 <= B1674 and B1673;
B1666 <= B1672 and B1653;
B1667 <= B1675 or B1652;
B1668 <= (B1653 and B1665) or ((not B1653) and (not B1665));
B1669 <= (not B1678) or (not B1679);
B1670 <= ((not B1654) and B1661) or (B1654 and (not B1661));
B1671 <= B1680 and B1673;
B1672 <= (not B1682) or (not B1681);
B1673 <= B1654 or B1655;
B1674 <= B1654 or B1661;
B1675 <= B1653 and B1665;
B1676 <= (not B1652) or (not B1653);
B1677 <= B1661 and B1676;
B1678 <= (not B1677) and (not B1661);
B1679 <= B1661 or B1676;
B1680 <= (not B1654) or (not B1655);
B1681 <= B1661 or B1676;
B1682 <= (not B1661) and (not B1683);
B1683 <= B1661 and B1676;
B1684 <= B8322;
B1685 <= B8355;
B1686 <= B8388;
B1687 <= B8421;
B1688 <= B8454;
B1689 <= B1695 and B1694;
B1690 <= B1697 or B1696;
B1691 <= B1699 or B1698;
B1692 <= B1694 and B1700;
B1693 <= B1694 and B1701;
B1694 <= ((not B1684) and B1685) or (B1684 and (not B1685));
B1695 <= ((not B1696) and B1686) or (B1696 and (not B1686));
B1696 <= B1704 and B1703;
B1697 <= B1702 and B1686;
B1698 <= B1707 and B1706;
B1699 <= B1705 and B1686;
B1700 <= B1708 or B1685;
B1701 <= (B1686 and B1698) or ((not B1686) and (not B1698));
B1702 <= (not B1711) or (not B1712);
B1703 <= ((not B1687) and B1694) or (B1687 and (not B1694));
B1704 <= B1713 and B1706;
B1705 <= (not B1715) or (not B1714);
B1706 <= B1687 or B1688;
B1707 <= B1687 or B1694;
B1708 <= B1686 and B1698;
B1709 <= (not B1685) or (not B1686);
B1710 <= B1694 and B1709;
B1711 <= (not B1710) and (not B1694);
B1712 <= B1694 or B1709;
B1713 <= (not B1687) or (not B1688);
B1714 <= B1694 or B1709;
B1715 <= (not B1694) and (not B1716);
B1716 <= B1694 and B1709;
B1717 <= B8487;
B1718 <= B8520;
B1719 <= B8553;
B1720 <= B8586;
B1721 <= B8619;
B1722 <= B1728 and B1727;
B1723 <= B1730 or B1729;
B1724 <= B1732 or B1731;
B1725 <= B1727 and B1733;
B1726 <= B1727 and B1734;
B1727 <= ((not B1717) and B1718) or (B1717 and (not B1718));
B1728 <= ((not B1729) and B1719) or (B1729 and (not B1719));
B1729 <= B1737 and B1736;
B1730 <= B1735 and B1719;
B1731 <= B1740 and B1739;
B1732 <= B1738 and B1719;
B1733 <= B1741 or B1718;
B1734 <= (B1719 and B1731) or ((not B1719) and (not B1731));
B1735 <= (not B1744) or (not B1745);
B1736 <= ((not B1720) and B1727) or (B1720 and (not B1727));
B1737 <= B1746 and B1739;
B1738 <= (not B1748) or (not B1747);
B1739 <= B1720 or B1721;
B1740 <= B1720 or B1727;
B1741 <= B1719 and B1731;
B1742 <= (not B1718) or (not B1719);
B1743 <= B1727 and B1742;
B1744 <= (not B1743) and (not B1727);
B1745 <= B1727 or B1742;
B1746 <= (not B1720) or (not B1721);
B1747 <= B1727 or B1742;
B1748 <= (not B1727) and (not B1749);
B1749 <= B1727 and B1742;
B1750 <= B8652;
B1751 <= B8685;
B1752 <= B8718;
B1753 <= B8751;
B1754 <= B8784;
B1755 <= B1761 and B1760;
B1756 <= B1763 or B1762;
B1757 <= B1765 or B1764;
B1758 <= B1760 and B1766;
B1759 <= B1760 and B1767;
B1760 <= ((not B1750) and B1751) or (B1750 and (not B1751));
B1761 <= ((not B1762) and B1752) or (B1762 and (not B1752));
B1762 <= B1770 and B1769;
B1763 <= B1768 and B1752;
B1764 <= B1773 and B1772;
B1765 <= B1771 and B1752;
B1766 <= B1774 or B1751;
B1767 <= (B1752 and B1764) or ((not B1752) and (not B1764));
B1768 <= (not B1777) or (not B1778);
B1769 <= ((not B1753) and B1760) or (B1753 and (not B1760));
B1770 <= B1779 and B1772;
B1771 <= (not B1781) or (not B1780);
B1772 <= B1753 or B1754;
B1773 <= B1753 or B1760;
B1774 <= B1752 and B1764;
B1775 <= (not B1751) or (not B1752);
B1776 <= B1760 and B1775;
B1777 <= (not B1776) and (not B1760);
B1778 <= B1760 or B1775;
B1779 <= (not B1753) or (not B1754);
B1780 <= B1760 or B1775;
B1781 <= (not B1760) and (not B1782);
B1782 <= B1760 and B1775;
B1783 <= B8817;
B1784 <= B8850;
B1785 <= B8883;
B1786 <= B8916;
B1787 <= B8949;
B1788 <= B1794 and B1793;
B1789 <= B1796 or B1795;
B1790 <= B1798 or B1797;
B1791 <= B1793 and B1799;
B1792 <= B1793 and B1800;
B1793 <= ((not B1783) and B1784) or (B1783 and (not B1784));
B1794 <= ((not B1795) and B1785) or (B1795 and (not B1785));
B1795 <= B1803 and B1802;
B1796 <= B1801 and B1785;
B1797 <= B1806 and B1805;
B1798 <= B1804 and B1785;
B1799 <= B1807 or B1784;
B1800 <= (B1785 and B1797) or ((not B1785) and (not B1797));
B1801 <= (not B1810) or (not B1811);
B1802 <= ((not B1786) and B1793) or (B1786 and (not B1793));
B1803 <= B1812 and B1805;
B1804 <= (not B1814) or (not B1813);
B1805 <= B1786 or B1787;
B1806 <= B1786 or B1793;
B1807 <= B1785 and B1797;
B1808 <= (not B1784) or (not B1785);
B1809 <= B1793 and B1808;
B1810 <= (not B1809) and (not B1793);
B1811 <= B1793 or B1808;
B1812 <= (not B1786) or (not B1787);
B1813 <= B1793 or B1808;
B1814 <= (not B1793) and (not B1815);
B1815 <= B1793 and B1808;
B1816 <= B8982;
B1817 <= B9015;
B1818 <= B9048;
B1819 <= B9081;
B1820 <= B9114;
B1821 <= B1827 and B1826;
B1822 <= B1829 or B1828;
B1823 <= B1831 or B1830;
B1824 <= B1826 and B1832;
B1825 <= B1826 and B1833;
B1826 <= ((not B1816) and B1817) or (B1816 and (not B1817));
B1827 <= ((not B1828) and B1818) or (B1828 and (not B1818));
B1828 <= B1836 and B1835;
B1829 <= B1834 and B1818;
B1830 <= B1839 and B1838;
B1831 <= B1837 and B1818;
B1832 <= B1840 or B1817;
B1833 <= (B1818 and B1830) or ((not B1818) and (not B1830));
B1834 <= (not B1843) or (not B1844);
B1835 <= ((not B1819) and B1826) or (B1819 and (not B1826));
B1836 <= B1845 and B1838;
B1837 <= (not B1847) or (not B1846);
B1838 <= B1819 or B1820;
B1839 <= B1819 or B1826;
B1840 <= B1818 and B1830;
B1841 <= (not B1817) or (not B1818);
B1842 <= B1826 and B1841;
B1843 <= (not B1842) and (not B1826);
B1844 <= B1826 or B1841;
B1845 <= (not B1819) or (not B1820);
B1846 <= B1826 or B1841;
B1847 <= (not B1826) and (not B1848);
B1848 <= B1826 and B1841;
B1849 <= B9147;
B1850 <= B9180;
B1851 <= B9213;
B1852 <= B9246;
B1853 <= B9279;
B1854 <= B1860 and B1859;
B1855 <= B1862 or B1861;
B1856 <= B1864 or B1863;
B1857 <= B1859 and B1865;
B1858 <= B1859 and B1866;
B1859 <= ((not B1849) and B1850) or (B1849 and (not B1850));
B1860 <= ((not B1861) and B1851) or (B1861 and (not B1851));
B1861 <= B1869 and B1868;
B1862 <= B1867 and B1851;
B1863 <= B1872 and B1871;
B1864 <= B1870 and B1851;
B1865 <= B1873 or B1850;
B1866 <= (B1851 and B1863) or ((not B1851) and (not B1863));
B1867 <= (not B1876) or (not B1877);
B1868 <= ((not B1852) and B1859) or (B1852 and (not B1859));
B1869 <= B1878 and B1871;
B1870 <= (not B1880) or (not B1879);
B1871 <= B1852 or B1853;
B1872 <= B1852 or B1859;
B1873 <= B1851 and B1863;
B1874 <= (not B1850) or (not B1851);
B1875 <= B1859 and B1874;
B1876 <= (not B1875) and (not B1859);
B1877 <= B1859 or B1874;
B1878 <= (not B1852) or (not B1853);
B1879 <= B1859 or B1874;
B1880 <= (not B1859) and (not B1881);
B1881 <= B1859 and B1874;
B1882 <= B5190;
B1883 <= B5221;
B1884 <= B5254;
B1885 <= B5287;
B1886 <= B5320;
B1887 <= B1893 and B1892;
B1888 <= B1895 or B1894;
B1889 <= B1897 or B1896;
B1890 <= B1892 and B1898;
B1891 <= B1892 and B1899;
B1892 <= ((not B1882) and B1883) or (B1882 and (not B1883));
B1893 <= ((not B1894) and B1884) or (B1894 and (not B1884));
B1894 <= B1902 and B1901;
B1895 <= B1900 and B1884;
B1896 <= B1905 and B1904;
B1897 <= B1903 and B1884;
B1898 <= B1906 or B1883;
B1899 <= (B1884 and B1896) or ((not B1884) and (not B1896));
B1900 <= (not B1909) or (not B1910);
B1901 <= ((not B1885) and B1892) or (B1885 and (not B1892));
B1902 <= B1911 and B1904;
B1903 <= (not B1913) or (not B1912);
B1904 <= B1885 or B1886;
B1905 <= B1885 or B1892;
B1906 <= B1884 and B1896;
B1907 <= (not B1883) or (not B1884);
B1908 <= B1892 and B1907;
B1909 <= (not B1908) and (not B1892);
B1910 <= B1892 or B1907;
B1911 <= (not B1885) or (not B1886);
B1912 <= B1892 or B1907;
B1913 <= (not B1892) and (not B1914);
B1914 <= B1892 and B1907;
B1915 <= B5353;
B1916 <= B5386;
B1917 <= B5419;
B1918 <= B5452;
B1919 <= B5485;
B1920 <= B1926 and B1925;
B1921 <= B1928 or B1927;
B1922 <= B1930 or B1929;
B1923 <= B1925 and B1931;
B1924 <= B1925 and B1932;
B1925 <= ((not B1915) and B1916) or (B1915 and (not B1916));
B1926 <= ((not B1927) and B1917) or (B1927 and (not B1917));
B1927 <= B1935 and B1934;
B1928 <= B1933 and B1917;
B1929 <= B1938 and B1937;
B1930 <= B1936 and B1917;
B1931 <= B1939 or B1916;
B1932 <= (B1917 and B1929) or ((not B1917) and (not B1929));
B1933 <= (not B1942) or (not B1943);
B1934 <= ((not B1918) and B1925) or (B1918 and (not B1925));
B1935 <= B1944 and B1937;
B1936 <= (not B1946) or (not B1945);
B1937 <= B1918 or B1919;
B1938 <= B1918 or B1925;
B1939 <= B1917 and B1929;
B1940 <= (not B1916) or (not B1917);
B1941 <= B1925 and B1940;
B1942 <= (not B1941) and (not B1925);
B1943 <= B1925 or B1940;
B1944 <= (not B1918) or (not B1919);
B1945 <= B1925 or B1940;
B1946 <= (not B1925) and (not B1947);
B1947 <= B1925 and B1940;
B1948 <= B5518;
B1949 <= B5551;
B1950 <= B5584;
B1951 <= B5617;
B1952 <= B5650;
B1953 <= B1959 and B1958;
B1954 <= B1961 or B1960;
B1955 <= B1963 or B1962;
B1956 <= B1958 and B1964;
B1957 <= B1958 and B1965;
B1958 <= ((not B1948) and B1949) or (B1948 and (not B1949));
B1959 <= ((not B1960) and B1950) or (B1960 and (not B1950));
B1960 <= B1968 and B1967;
B1961 <= B1966 and B1950;
B1962 <= B1971 and B1970;
B1963 <= B1969 and B1950;
B1964 <= B1972 or B1949;
B1965 <= (B1950 and B1962) or ((not B1950) and (not B1962));
B1966 <= (not B1975) or (not B1976);
B1967 <= ((not B1951) and B1958) or (B1951 and (not B1958));
B1968 <= B1977 and B1970;
B1969 <= (not B1979) or (not B1978);
B1970 <= B1951 or B1952;
B1971 <= B1951 or B1958;
B1972 <= B1950 and B1962;
B1973 <= (not B1949) or (not B1950);
B1974 <= B1958 and B1973;
B1975 <= (not B1974) and (not B1958);
B1976 <= B1958 or B1973;
B1977 <= (not B1951) or (not B1952);
B1978 <= B1958 or B1973;
B1979 <= (not B1958) and (not B1980);
B1980 <= B1958 and B1973;
B1981 <= B5683;
B1982 <= B5716;
B1983 <= B5749;
B1984 <= B5782;
B1985 <= B5815;
B1986 <= B1992 and B1991;
B1987 <= B1994 or B1993;
B1988 <= B1996 or B1995;
B1989 <= B1991 and B1997;
B1990 <= B1991 and B1998;
B1991 <= ((not B1981) and B1982) or (B1981 and (not B1982));
B1992 <= ((not B1993) and B1983) or (B1993 and (not B1983));
B1993 <= B2001 and B2000;
B1994 <= B1999 and B1983;
B1995 <= B2004 and B2003;
B1996 <= B2002 and B1983;
B1997 <= B2005 or B1982;
B1998 <= (B1983 and B1995) or ((not B1983) and (not B1995));
B1999 <= (not B2008) or (not B2009);
B2000 <= ((not B1984) and B1991) or (B1984 and (not B1991));
B2001 <= B2010 and B2003;
B2002 <= (not B2012) or (not B2011);
B2003 <= B1984 or B1985;
B2004 <= B1984 or B1991;
B2005 <= B1983 and B1995;
B2006 <= (not B1982) or (not B1983);
B2007 <= B1991 and B2006;
B2008 <= (not B2007) and (not B1991);
B2009 <= B1991 or B2006;
B2010 <= (not B1984) or (not B1985);
B2011 <= B1991 or B2006;
B2012 <= (not B1991) and (not B2013);
B2013 <= B1991 and B2006;
B2014 <= B5848;
B2015 <= B5881;
B2016 <= B5914;
B2017 <= B5947;
B2018 <= B5980;
B2019 <= B2025 and B2024;
B2020 <= B2027 or B2026;
B2021 <= B2029 or B2028;
B2022 <= B2024 and B2030;
B2023 <= B2024 and B2031;
B2024 <= ((not B2014) and B2015) or (B2014 and (not B2015));
B2025 <= ((not B2026) and B2016) or (B2026 and (not B2016));
B2026 <= B2034 and B2033;
B2027 <= B2032 and B2016;
B2028 <= B2037 and B2036;
B2029 <= B2035 and B2016;
B2030 <= B2038 or B2015;
B2031 <= (B2016 and B2028) or ((not B2016) and (not B2028));
B2032 <= (not B2041) or (not B2042);
B2033 <= ((not B2017) and B2024) or (B2017 and (not B2024));
B2034 <= B2043 and B2036;
B2035 <= (not B2045) or (not B2044);
B2036 <= B2017 or B2018;
B2037 <= B2017 or B2024;
B2038 <= B2016 and B2028;
B2039 <= (not B2015) or (not B2016);
B2040 <= B2024 and B2039;
B2041 <= (not B2040) and (not B2024);
B2042 <= B2024 or B2039;
B2043 <= (not B2017) or (not B2018);
B2044 <= B2024 or B2039;
B2045 <= (not B2024) and (not B2046);
B2046 <= B2024 and B2039;
B2047 <= B6013;
B2048 <= B6046;
B2049 <= B6079;
B2050 <= B6112;
B2051 <= B6145;
B2052 <= B2058 and B2057;
B2053 <= B2060 or B2059;
B2054 <= B2062 or B2061;
B2055 <= B2057 and B2063;
B2056 <= B2057 and B2064;
B2057 <= ((not B2047) and B2048) or (B2047 and (not B2048));
B2058 <= ((not B2059) and B2049) or (B2059 and (not B2049));
B2059 <= B2067 and B2066;
B2060 <= B2065 and B2049;
B2061 <= B2070 and B2069;
B2062 <= B2068 and B2049;
B2063 <= B2071 or B2048;
B2064 <= (B2049 and B2061) or ((not B2049) and (not B2061));
B2065 <= (not B2074) or (not B2075);
B2066 <= ((not B2050) and B2057) or (B2050 and (not B2057));
B2067 <= B2076 and B2069;
B2068 <= (not B2078) or (not B2077);
B2069 <= B2050 or B2051;
B2070 <= B2050 or B2057;
B2071 <= B2049 and B2061;
B2072 <= (not B2048) or (not B2049);
B2073 <= B2057 and B2072;
B2074 <= (not B2073) and (not B2057);
B2075 <= B2057 or B2072;
B2076 <= (not B2050) or (not B2051);
B2077 <= B2057 or B2072;
B2078 <= (not B2057) and (not B2079);
B2079 <= B2057 and B2072;
B2080 <= B6178;
B2081 <= B6211;
B2082 <= B6244;
B2083 <= B6277;
B2084 <= B6310;
B2085 <= B2091 and B2090;
B2086 <= B2093 or B2092;
B2087 <= B2095 or B2094;
B2088 <= B2090 and B2096;
B2089 <= B2090 and B2097;
B2090 <= ((not B2080) and B2081) or (B2080 and (not B2081));
B2091 <= ((not B2092) and B2082) or (B2092 and (not B2082));
B2092 <= B2100 and B2099;
B2093 <= B2098 and B2082;
B2094 <= B2103 and B2102;
B2095 <= B2101 and B2082;
B2096 <= B2104 or B2081;
B2097 <= (B2082 and B2094) or ((not B2082) and (not B2094));
B2098 <= (not B2107) or (not B2108);
B2099 <= ((not B2083) and B2090) or (B2083 and (not B2090));
B2100 <= B2109 and B2102;
B2101 <= (not B2111) or (not B2110);
B2102 <= B2083 or B2084;
B2103 <= B2083 or B2090;
B2104 <= B2082 and B2094;
B2105 <= (not B2081) or (not B2082);
B2106 <= B2090 and B2105;
B2107 <= (not B2106) and (not B2090);
B2108 <= B2090 or B2105;
B2109 <= (not B2083) or (not B2084);
B2110 <= B2090 or B2105;
B2111 <= (not B2090) and (not B2112);
B2112 <= B2090 and B2105;
B2113 <= B6343;
B2114 <= B6376;
B2115 <= B6409;
B2116 <= B6442;
B2117 <= B6475;
B2118 <= B2124 and B2123;
B2119 <= B2126 or B2125;
B2120 <= B2128 or B2127;
B2121 <= B2123 and B2129;
B2122 <= B2123 and B2130;
B2123 <= ((not B2113) and B2114) or (B2113 and (not B2114));
B2124 <= ((not B2125) and B2115) or (B2125 and (not B2115));
B2125 <= B2133 and B2132;
B2126 <= B2131 and B2115;
B2127 <= B2136 and B2135;
B2128 <= B2134 and B2115;
B2129 <= B2137 or B2114;
B2130 <= (B2115 and B2127) or ((not B2115) and (not B2127));
B2131 <= (not B2140) or (not B2141);
B2132 <= ((not B2116) and B2123) or (B2116 and (not B2123));
B2133 <= B2142 and B2135;
B2134 <= (not B2144) or (not B2143);
B2135 <= B2116 or B2117;
B2136 <= B2116 or B2123;
B2137 <= B2115 and B2127;
B2138 <= (not B2114) or (not B2115);
B2139 <= B2123 and B2138;
B2140 <= (not B2139) and (not B2123);
B2141 <= B2123 or B2138;
B2142 <= (not B2116) or (not B2117);
B2143 <= B2123 or B2138;
B2144 <= (not B2123) and (not B2145);
B2145 <= B2123 and B2138;
B2146 <= B6508;
B2147 <= B6541;
B2148 <= B6574;
B2149 <= B6607;
B2150 <= B6640;
B2151 <= B2157 and B2156;
B2152 <= B2159 or B2158;
B2153 <= B2161 or B2160;
B2154 <= B2156 and B2162;
B2155 <= B2156 and B2163;
B2156 <= ((not B2146) and B2147) or (B2146 and (not B2147));
B2157 <= ((not B2158) and B2148) or (B2158 and (not B2148));
B2158 <= B2166 and B2165;
B2159 <= B2164 and B2148;
B2160 <= B2169 and B2168;
B2161 <= B2167 and B2148;
B2162 <= B2170 or B2147;
B2163 <= (B2148 and B2160) or ((not B2148) and (not B2160));
B2164 <= (not B2173) or (not B2174);
B2165 <= ((not B2149) and B2156) or (B2149 and (not B2156));
B2166 <= B2175 and B2168;
B2167 <= (not B2177) or (not B2176);
B2168 <= B2149 or B2150;
B2169 <= B2149 or B2156;
B2170 <= B2148 and B2160;
B2171 <= (not B2147) or (not B2148);
B2172 <= B2156 and B2171;
B2173 <= (not B2172) and (not B2156);
B2174 <= B2156 or B2171;
B2175 <= (not B2149) or (not B2150);
B2176 <= B2156 or B2171;
B2177 <= (not B2156) and (not B2178);
B2178 <= B2156 and B2171;
B2179 <= B6673;
B2180 <= B6706;
B2181 <= B6739;
B2182 <= B6772;
B2183 <= B6805;
B2184 <= B2190 and B2189;
B2185 <= B2192 or B2191;
B2186 <= B2194 or B2193;
B2187 <= B2189 and B2195;
B2188 <= B2189 and B2196;
B2189 <= ((not B2179) and B2180) or (B2179 and (not B2180));
B2190 <= ((not B2191) and B2181) or (B2191 and (not B2181));
B2191 <= B2199 and B2198;
B2192 <= B2197 and B2181;
B2193 <= B2202 and B2201;
B2194 <= B2200 and B2181;
B2195 <= B2203 or B2180;
B2196 <= (B2181 and B2193) or ((not B2181) and (not B2193));
B2197 <= (not B2206) or (not B2207);
B2198 <= ((not B2182) and B2189) or (B2182 and (not B2189));
B2199 <= B2208 and B2201;
B2200 <= (not B2210) or (not B2209);
B2201 <= B2182 or B2183;
B2202 <= B2182 or B2189;
B2203 <= B2181 and B2193;
B2204 <= (not B2180) or (not B2181);
B2205 <= B2189 and B2204;
B2206 <= (not B2205) and (not B2189);
B2207 <= B2189 or B2204;
B2208 <= (not B2182) or (not B2183);
B2209 <= B2189 or B2204;
B2210 <= (not B2189) and (not B2211);
B2211 <= B2189 and B2204;
B2212 <= B6838;
B2213 <= B6871;
B2214 <= B6904;
B2215 <= B6937;
B2216 <= B6970;
B2217 <= B2223 and B2222;
B2218 <= B2225 or B2224;
B2219 <= B2227 or B2226;
B2220 <= B2222 and B2228;
B2221 <= B2222 and B2229;
B2222 <= ((not B2212) and B2213) or (B2212 and (not B2213));
B2223 <= ((not B2224) and B2214) or (B2224 and (not B2214));
B2224 <= B2232 and B2231;
B2225 <= B2230 and B2214;
B2226 <= B2235 and B2234;
B2227 <= B2233 and B2214;
B2228 <= B2236 or B2213;
B2229 <= (B2214 and B2226) or ((not B2214) and (not B2226));
B2230 <= (not B2239) or (not B2240);
B2231 <= ((not B2215) and B2222) or (B2215 and (not B2222));
B2232 <= B2241 and B2234;
B2233 <= (not B2243) or (not B2242);
B2234 <= B2215 or B2216;
B2235 <= B2215 or B2222;
B2236 <= B2214 and B2226;
B2237 <= (not B2213) or (not B2214);
B2238 <= B2222 and B2237;
B2239 <= (not B2238) and (not B2222);
B2240 <= B2222 or B2237;
B2241 <= (not B2215) or (not B2216);
B2242 <= B2222 or B2237;
B2243 <= (not B2222) and (not B2244);
B2244 <= B2222 and B2237;
B2245 <= B7003;
B2246 <= B7036;
B2247 <= B7069;
B2248 <= B7102;
B2249 <= B7135;
B2250 <= B2256 and B2255;
B2251 <= B2258 or B2257;
B2252 <= B2260 or B2259;
B2253 <= B2255 and B2261;
B2254 <= B2255 and B2262;
B2255 <= ((not B2245) and B2246) or (B2245 and (not B2246));
B2256 <= ((not B2257) and B2247) or (B2257 and (not B2247));
B2257 <= B2265 and B2264;
B2258 <= B2263 and B2247;
B2259 <= B2268 and B2267;
B2260 <= B2266 and B2247;
B2261 <= B2269 or B2246;
B2262 <= (B2247 and B2259) or ((not B2247) and (not B2259));
B2263 <= (not B2272) or (not B2273);
B2264 <= ((not B2248) and B2255) or (B2248 and (not B2255));
B2265 <= B2274 and B2267;
B2266 <= (not B2276) or (not B2275);
B2267 <= B2248 or B2249;
B2268 <= B2248 or B2255;
B2269 <= B2247 and B2259;
B2270 <= (not B2246) or (not B2247);
B2271 <= B2255 and B2270;
B2272 <= (not B2271) and (not B2255);
B2273 <= B2255 or B2270;
B2274 <= (not B2248) or (not B2249);
B2275 <= B2255 or B2270;
B2276 <= (not B2255) and (not B2277);
B2277 <= B2255 and B2270;
B2278 <= B7168;
B2279 <= B7201;
B2280 <= B7234;
B2281 <= B7267;
B2282 <= B7300;
B2283 <= B2289 and B2288;
B2284 <= B2291 or B2290;
B2285 <= B2293 or B2292;
B2286 <= B2288 and B2294;
B2287 <= B2288 and B2295;
B2288 <= ((not B2278) and B2279) or (B2278 and (not B2279));
B2289 <= ((not B2290) and B2280) or (B2290 and (not B2280));
B2290 <= B2298 and B2297;
B2291 <= B2296 and B2280;
B2292 <= B2301 and B2300;
B2293 <= B2299 and B2280;
B2294 <= B2302 or B2279;
B2295 <= (B2280 and B2292) or ((not B2280) and (not B2292));
B2296 <= (not B2305) or (not B2306);
B2297 <= ((not B2281) and B2288) or (B2281 and (not B2288));
B2298 <= B2307 and B2300;
B2299 <= (not B2309) or (not B2308);
B2300 <= B2281 or B2282;
B2301 <= B2281 or B2288;
B2302 <= B2280 and B2292;
B2303 <= (not B2279) or (not B2280);
B2304 <= B2288 and B2303;
B2305 <= (not B2304) and (not B2288);
B2306 <= B2288 or B2303;
B2307 <= (not B2281) or (not B2282);
B2308 <= B2288 or B2303;
B2309 <= (not B2288) and (not B2310);
B2310 <= B2288 and B2303;
B2311 <= B7333;
B2312 <= B7366;
B2313 <= B7399;
B2314 <= B7432;
B2315 <= B7465;
B2316 <= B2322 and B2321;
B2317 <= B2324 or B2323;
B2318 <= B2326 or B2325;
B2319 <= B2321 and B2327;
B2320 <= B2321 and B2328;
B2321 <= ((not B2311) and B2312) or (B2311 and (not B2312));
B2322 <= ((not B2323) and B2313) or (B2323 and (not B2313));
B2323 <= B2331 and B2330;
B2324 <= B2329 and B2313;
B2325 <= B2334 and B2333;
B2326 <= B2332 and B2313;
B2327 <= B2335 or B2312;
B2328 <= (B2313 and B2325) or ((not B2313) and (not B2325));
B2329 <= (not B2338) or (not B2339);
B2330 <= ((not B2314) and B2321) or (B2314 and (not B2321));
B2331 <= B2340 and B2333;
B2332 <= (not B2342) or (not B2341);
B2333 <= B2314 or B2315;
B2334 <= B2314 or B2321;
B2335 <= B2313 and B2325;
B2336 <= (not B2312) or (not B2313);
B2337 <= B2321 and B2336;
B2338 <= (not B2337) and (not B2321);
B2339 <= B2321 or B2336;
B2340 <= (not B2314) or (not B2315);
B2341 <= B2321 or B2336;
B2342 <= (not B2321) and (not B2343);
B2343 <= B2321 and B2336;
B2344 <= B7498;
B2345 <= B7531;
B2346 <= B7564;
B2347 <= B7597;
B2348 <= B7630;
B2349 <= B2355 and B2354;
B2350 <= B2357 or B2356;
B2351 <= B2359 or B2358;
B2352 <= B2354 and B2360;
B2353 <= B2354 and B2361;
B2354 <= ((not B2344) and B2345) or (B2344 and (not B2345));
B2355 <= ((not B2356) and B2346) or (B2356 and (not B2346));
B2356 <= B2364 and B2363;
B2357 <= B2362 and B2346;
B2358 <= B2367 and B2366;
B2359 <= B2365 and B2346;
B2360 <= B2368 or B2345;
B2361 <= (B2346 and B2358) or ((not B2346) and (not B2358));
B2362 <= (not B2371) or (not B2372);
B2363 <= ((not B2347) and B2354) or (B2347 and (not B2354));
B2364 <= B2373 and B2366;
B2365 <= (not B2375) or (not B2374);
B2366 <= B2347 or B2348;
B2367 <= B2347 or B2354;
B2368 <= B2346 and B2358;
B2369 <= (not B2345) or (not B2346);
B2370 <= B2354 and B2369;
B2371 <= (not B2370) and (not B2354);
B2372 <= B2354 or B2369;
B2373 <= (not B2347) or (not B2348);
B2374 <= B2354 or B2369;
B2375 <= (not B2354) and (not B2376);
B2376 <= B2354 and B2369;
B2377 <= B7663;
B2378 <= B7696;
B2379 <= B7729;
B2380 <= B7762;
B2381 <= B7795;
B2382 <= B2388 and B2387;
B2383 <= B2390 or B2389;
B2384 <= B2392 or B2391;
B2385 <= B2387 and B2393;
B2386 <= B2387 and B2394;
B2387 <= ((not B2377) and B2378) or (B2377 and (not B2378));
B2388 <= ((not B2389) and B2379) or (B2389 and (not B2379));
B2389 <= B2397 and B2396;
B2390 <= B2395 and B2379;
B2391 <= B2400 and B2399;
B2392 <= B2398 and B2379;
B2393 <= B2401 or B2378;
B2394 <= (B2379 and B2391) or ((not B2379) and (not B2391));
B2395 <= (not B2404) or (not B2405);
B2396 <= ((not B2380) and B2387) or (B2380 and (not B2387));
B2397 <= B2406 and B2399;
B2398 <= (not B2408) or (not B2407);
B2399 <= B2380 or B2381;
B2400 <= B2380 or B2387;
B2401 <= B2379 and B2391;
B2402 <= (not B2378) or (not B2379);
B2403 <= B2387 and B2402;
B2404 <= (not B2403) and (not B2387);
B2405 <= B2387 or B2402;
B2406 <= (not B2380) or (not B2381);
B2407 <= B2387 or B2402;
B2408 <= (not B2387) and (not B2409);
B2409 <= B2387 and B2402;
B2410 <= B7828;
B2411 <= B7861;
B2412 <= B7894;
B2413 <= B7927;
B2414 <= B7960;
B2415 <= B2421 and B2420;
B2416 <= B2423 or B2422;
B2417 <= B2425 or B2424;
B2418 <= B2420 and B2426;
B2419 <= B2420 and B2427;
B2420 <= ((not B2410) and B2411) or (B2410 and (not B2411));
B2421 <= ((not B2422) and B2412) or (B2422 and (not B2412));
B2422 <= B2430 and B2429;
B2423 <= B2428 and B2412;
B2424 <= B2433 and B2432;
B2425 <= B2431 and B2412;
B2426 <= B2434 or B2411;
B2427 <= (B2412 and B2424) or ((not B2412) and (not B2424));
B2428 <= (not B2437) or (not B2438);
B2429 <= ((not B2413) and B2420) or (B2413 and (not B2420));
B2430 <= B2439 and B2432;
B2431 <= (not B2441) or (not B2440);
B2432 <= B2413 or B2414;
B2433 <= B2413 or B2420;
B2434 <= B2412 and B2424;
B2435 <= (not B2411) or (not B2412);
B2436 <= B2420 and B2435;
B2437 <= (not B2436) and (not B2420);
B2438 <= B2420 or B2435;
B2439 <= (not B2413) or (not B2414);
B2440 <= B2420 or B2435;
B2441 <= (not B2420) and (not B2442);
B2442 <= B2420 and B2435;
B2443 <= B7993;
B2444 <= B8026;
B2445 <= B8059;
B2446 <= B8092;
B2447 <= B8125;
B2448 <= B2454 and B2453;
B2449 <= B2456 or B2455;
B2450 <= B2458 or B2457;
B2451 <= B2453 and B2459;
B2452 <= B2453 and B2460;
B2453 <= ((not B2443) and B2444) or (B2443 and (not B2444));
B2454 <= ((not B2455) and B2445) or (B2455 and (not B2445));
B2455 <= B2463 and B2462;
B2456 <= B2461 and B2445;
B2457 <= B2466 and B2465;
B2458 <= B2464 and B2445;
B2459 <= B2467 or B2444;
B2460 <= (B2445 and B2457) or ((not B2445) and (not B2457));
B2461 <= (not B2470) or (not B2471);
B2462 <= ((not B2446) and B2453) or (B2446 and (not B2453));
B2463 <= B2472 and B2465;
B2464 <= (not B2474) or (not B2473);
B2465 <= B2446 or B2447;
B2466 <= B2446 or B2453;
B2467 <= B2445 and B2457;
B2468 <= (not B2444) or (not B2445);
B2469 <= B2453 and B2468;
B2470 <= (not B2469) and (not B2453);
B2471 <= B2453 or B2468;
B2472 <= (not B2446) or (not B2447);
B2473 <= B2453 or B2468;
B2474 <= (not B2453) and (not B2475);
B2475 <= B2453 and B2468;
B2476 <= B8158;
B2477 <= B8191;
B2478 <= B8224;
B2479 <= B8257;
B2480 <= B8290;
B2481 <= B2487 and B2486;
B2482 <= B2489 or B2488;
B2483 <= B2491 or B2490;
B2484 <= B2486 and B2492;
B2485 <= B2486 and B2493;
B2486 <= ((not B2476) and B2477) or (B2476 and (not B2477));
B2487 <= ((not B2488) and B2478) or (B2488 and (not B2478));
B2488 <= B2496 and B2495;
B2489 <= B2494 and B2478;
B2490 <= B2499 and B2498;
B2491 <= B2497 and B2478;
B2492 <= B2500 or B2477;
B2493 <= (B2478 and B2490) or ((not B2478) and (not B2490));
B2494 <= (not B2503) or (not B2504);
B2495 <= ((not B2479) and B2486) or (B2479 and (not B2486));
B2496 <= B2505 and B2498;
B2497 <= (not B2507) or (not B2506);
B2498 <= B2479 or B2480;
B2499 <= B2479 or B2486;
B2500 <= B2478 and B2490;
B2501 <= (not B2477) or (not B2478);
B2502 <= B2486 and B2501;
B2503 <= (not B2502) and (not B2486);
B2504 <= B2486 or B2501;
B2505 <= (not B2479) or (not B2480);
B2506 <= B2486 or B2501;
B2507 <= (not B2486) and (not B2508);
B2508 <= B2486 and B2501;
B2509 <= B8323;
B2510 <= B8356;
B2511 <= B8389;
B2512 <= B8422;
B2513 <= B8455;
B2514 <= B2520 and B2519;
B2515 <= B2522 or B2521;
B2516 <= B2524 or B2523;
B2517 <= B2519 and B2525;
B2518 <= B2519 and B2526;
B2519 <= ((not B2509) and B2510) or (B2509 and (not B2510));
B2520 <= ((not B2521) and B2511) or (B2521 and (not B2511));
B2521 <= B2529 and B2528;
B2522 <= B2527 and B2511;
B2523 <= B2532 and B2531;
B2524 <= B2530 and B2511;
B2525 <= B2533 or B2510;
B2526 <= (B2511 and B2523) or ((not B2511) and (not B2523));
B2527 <= (not B2536) or (not B2537);
B2528 <= ((not B2512) and B2519) or (B2512 and (not B2519));
B2529 <= B2538 and B2531;
B2530 <= (not B2540) or (not B2539);
B2531 <= B2512 or B2513;
B2532 <= B2512 or B2519;
B2533 <= B2511 and B2523;
B2534 <= (not B2510) or (not B2511);
B2535 <= B2519 and B2534;
B2536 <= (not B2535) and (not B2519);
B2537 <= B2519 or B2534;
B2538 <= (not B2512) or (not B2513);
B2539 <= B2519 or B2534;
B2540 <= (not B2519) and (not B2541);
B2541 <= B2519 and B2534;
B2542 <= B8488;
B2543 <= B8521;
B2544 <= B8554;
B2545 <= B8587;
B2546 <= B8620;
B2547 <= B2553 and B2552;
B2548 <= B2555 or B2554;
B2549 <= B2557 or B2556;
B2550 <= B2552 and B2558;
B2551 <= B2552 and B2559;
B2552 <= ((not B2542) and B2543) or (B2542 and (not B2543));
B2553 <= ((not B2554) and B2544) or (B2554 and (not B2544));
B2554 <= B2562 and B2561;
B2555 <= B2560 and B2544;
B2556 <= B2565 and B2564;
B2557 <= B2563 and B2544;
B2558 <= B2566 or B2543;
B2559 <= (B2544 and B2556) or ((not B2544) and (not B2556));
B2560 <= (not B2569) or (not B2570);
B2561 <= ((not B2545) and B2552) or (B2545 and (not B2552));
B2562 <= B2571 and B2564;
B2563 <= (not B2573) or (not B2572);
B2564 <= B2545 or B2546;
B2565 <= B2545 or B2552;
B2566 <= B2544 and B2556;
B2567 <= (not B2543) or (not B2544);
B2568 <= B2552 and B2567;
B2569 <= (not B2568) and (not B2552);
B2570 <= B2552 or B2567;
B2571 <= (not B2545) or (not B2546);
B2572 <= B2552 or B2567;
B2573 <= (not B2552) and (not B2574);
B2574 <= B2552 and B2567;
B2575 <= B8653;
B2576 <= B8686;
B2577 <= B8719;
B2578 <= B8752;
B2579 <= B8785;
B2580 <= B2586 and B2585;
B2581 <= B2588 or B2587;
B2582 <= B2590 or B2589;
B2583 <= B2585 and B2591;
B2584 <= B2585 and B2592;
B2585 <= ((not B2575) and B2576) or (B2575 and (not B2576));
B2586 <= ((not B2587) and B2577) or (B2587 and (not B2577));
B2587 <= B2595 and B2594;
B2588 <= B2593 and B2577;
B2589 <= B2598 and B2597;
B2590 <= B2596 and B2577;
B2591 <= B2599 or B2576;
B2592 <= (B2577 and B2589) or ((not B2577) and (not B2589));
B2593 <= (not B2602) or (not B2603);
B2594 <= ((not B2578) and B2585) or (B2578 and (not B2585));
B2595 <= B2604 and B2597;
B2596 <= (not B2606) or (not B2605);
B2597 <= B2578 or B2579;
B2598 <= B2578 or B2585;
B2599 <= B2577 and B2589;
B2600 <= (not B2576) or (not B2577);
B2601 <= B2585 and B2600;
B2602 <= (not B2601) and (not B2585);
B2603 <= B2585 or B2600;
B2604 <= (not B2578) or (not B2579);
B2605 <= B2585 or B2600;
B2606 <= (not B2585) and (not B2607);
B2607 <= B2585 and B2600;
B2608 <= B8818;
B2609 <= B8851;
B2610 <= B8884;
B2611 <= B8917;
B2612 <= B8950;
B2613 <= B2619 and B2618;
B2614 <= B2621 or B2620;
B2615 <= B2623 or B2622;
B2616 <= B2618 and B2624;
B2617 <= B2618 and B2625;
B2618 <= ((not B2608) and B2609) or (B2608 and (not B2609));
B2619 <= ((not B2620) and B2610) or (B2620 and (not B2610));
B2620 <= B2628 and B2627;
B2621 <= B2626 and B2610;
B2622 <= B2631 and B2630;
B2623 <= B2629 and B2610;
B2624 <= B2632 or B2609;
B2625 <= (B2610 and B2622) or ((not B2610) and (not B2622));
B2626 <= (not B2635) or (not B2636);
B2627 <= ((not B2611) and B2618) or (B2611 and (not B2618));
B2628 <= B2637 and B2630;
B2629 <= (not B2639) or (not B2638);
B2630 <= B2611 or B2612;
B2631 <= B2611 or B2618;
B2632 <= B2610 and B2622;
B2633 <= (not B2609) or (not B2610);
B2634 <= B2618 and B2633;
B2635 <= (not B2634) and (not B2618);
B2636 <= B2618 or B2633;
B2637 <= (not B2611) or (not B2612);
B2638 <= B2618 or B2633;
B2639 <= (not B2618) and (not B2640);
B2640 <= B2618 and B2633;
B2641 <= B8983;
B2642 <= B9016;
B2643 <= B9049;
B2644 <= B9082;
B2645 <= B9115;
B2646 <= B2652 and B2651;
B2647 <= B2654 or B2653;
B2648 <= B2656 or B2655;
B2649 <= B2651 and B2657;
B2650 <= B2651 and B2658;
B2651 <= ((not B2641) and B2642) or (B2641 and (not B2642));
B2652 <= ((not B2653) and B2643) or (B2653 and (not B2643));
B2653 <= B2661 and B2660;
B2654 <= B2659 and B2643;
B2655 <= B2664 and B2663;
B2656 <= B2662 and B2643;
B2657 <= B2665 or B2642;
B2658 <= (B2643 and B2655) or ((not B2643) and (not B2655));
B2659 <= (not B2668) or (not B2669);
B2660 <= ((not B2644) and B2651) or (B2644 and (not B2651));
B2661 <= B2670 and B2663;
B2662 <= (not B2672) or (not B2671);
B2663 <= B2644 or B2645;
B2664 <= B2644 or B2651;
B2665 <= B2643 and B2655;
B2666 <= (not B2642) or (not B2643);
B2667 <= B2651 and B2666;
B2668 <= (not B2667) and (not B2651);
B2669 <= B2651 or B2666;
B2670 <= (not B2644) or (not B2645);
B2671 <= B2651 or B2666;
B2672 <= (not B2651) and (not B2673);
B2673 <= B2651 and B2666;
B2674 <= B9148;
B2675 <= B9181;
B2676 <= B9214;
B2677 <= B9247;
B2678 <= B9280;
B2679 <= B2685 and B2684;
B2680 <= B2687 or B2686;
B2681 <= B2689 or B2688;
B2682 <= B2684 and B2690;
B2683 <= B2684 and B2691;
B2684 <= ((not B2674) and B2675) or (B2674 and (not B2675));
B2685 <= ((not B2686) and B2676) or (B2686 and (not B2676));
B2686 <= B2694 and B2693;
B2687 <= B2692 and B2676;
B2688 <= B2697 and B2696;
B2689 <= B2695 and B2676;
B2690 <= B2698 or B2675;
B2691 <= (B2676 and B2688) or ((not B2676) and (not B2688));
B2692 <= (not B2701) or (not B2702);
B2693 <= ((not B2677) and B2684) or (B2677 and (not B2684));
B2694 <= B2703 and B2696;
B2695 <= (not B2705) or (not B2704);
B2696 <= B2677 or B2678;
B2697 <= B2677 or B2684;
B2698 <= B2676 and B2688;
B2699 <= (not B2675) or (not B2676);
B2700 <= B2684 and B2699;
B2701 <= (not B2700) and (not B2684);
B2702 <= B2684 or B2699;
B2703 <= (not B2677) or (not B2678);
B2704 <= B2684 or B2699;
B2705 <= (not B2684) and (not B2706);
B2706 <= B2684 and B2699;
B2707 <= B5189;
B2708 <= B5222;
B2709 <= B5255;
B2710 <= B5288;
B2711 <= B5321;
B2712 <= B2718 and B2717;
B2713 <= B2720 or B2719;
B2714 <= B2722 or B2721;
B2715 <= B2717 and B2723;
B2716 <= B2717 and B2724;
B2717 <= ((not B2707) and B2708) or (B2707 and (not B2708));
B2718 <= ((not B2719) and B2709) or (B2719 and (not B2709));
B2719 <= B2727 and B2726;
B2720 <= B2725 and B2709;
B2721 <= B2730 and B2729;
B2722 <= B2728 and B2709;
B2723 <= B2731 or B2708;
B2724 <= (B2709 and B2721) or ((not B2709) and (not B2721));
B2725 <= (not B2734) or (not B2735);
B2726 <= ((not B2710) and B2717) or (B2710 and (not B2717));
B2727 <= B2736 and B2729;
B2728 <= (not B2738) or (not B2737);
B2729 <= B2710 or B2711;
B2730 <= B2710 or B2717;
B2731 <= B2709 and B2721;
B2732 <= (not B2708) or (not B2709);
B2733 <= B2717 and B2732;
B2734 <= (not B2733) and (not B2717);
B2735 <= B2717 or B2732;
B2736 <= (not B2710) or (not B2711);
B2737 <= B2717 or B2732;
B2738 <= (not B2717) and (not B2739);
B2739 <= B2717 and B2732;
B2740 <= B5354;
B2741 <= B5387;
B2742 <= B5420;
B2743 <= B5453;
B2744 <= B5486;
B2745 <= B2751 and B2750;
B2746 <= B2753 or B2752;
B2747 <= B2755 or B2754;
B2748 <= B2750 and B2756;
B2749 <= B2750 and B2757;
B2750 <= ((not B2740) and B2741) or (B2740 and (not B2741));
B2751 <= ((not B2752) and B2742) or (B2752 and (not B2742));
B2752 <= B2760 and B2759;
B2753 <= B2758 and B2742;
B2754 <= B2763 and B2762;
B2755 <= B2761 and B2742;
B2756 <= B2764 or B2741;
B2757 <= (B2742 and B2754) or ((not B2742) and (not B2754));
B2758 <= (not B2767) or (not B2768);
B2759 <= ((not B2743) and B2750) or (B2743 and (not B2750));
B2760 <= B2769 and B2762;
B2761 <= (not B2771) or (not B2770);
B2762 <= B2743 or B2744;
B2763 <= B2743 or B2750;
B2764 <= B2742 and B2754;
B2765 <= (not B2741) or (not B2742);
B2766 <= B2750 and B2765;
B2767 <= (not B2766) and (not B2750);
B2768 <= B2750 or B2765;
B2769 <= (not B2743) or (not B2744);
B2770 <= B2750 or B2765;
B2771 <= (not B2750) and (not B2772);
B2772 <= B2750 and B2765;
B2773 <= B5519;
B2774 <= B5552;
B2775 <= B5585;
B2776 <= B5618;
B2777 <= B5651;
B2778 <= B2784 and B2783;
B2779 <= B2786 or B2785;
B2780 <= B2788 or B2787;
B2781 <= B2783 and B2789;
B2782 <= B2783 and B2790;
B2783 <= ((not B2773) and B2774) or (B2773 and (not B2774));
B2784 <= ((not B2785) and B2775) or (B2785 and (not B2775));
B2785 <= B2793 and B2792;
B2786 <= B2791 and B2775;
B2787 <= B2796 and B2795;
B2788 <= B2794 and B2775;
B2789 <= B2797 or B2774;
B2790 <= (B2775 and B2787) or ((not B2775) and (not B2787));
B2791 <= (not B2800) or (not B2801);
B2792 <= ((not B2776) and B2783) or (B2776 and (not B2783));
B2793 <= B2802 and B2795;
B2794 <= (not B2804) or (not B2803);
B2795 <= B2776 or B2777;
B2796 <= B2776 or B2783;
B2797 <= B2775 and B2787;
B2798 <= (not B2774) or (not B2775);
B2799 <= B2783 and B2798;
B2800 <= (not B2799) and (not B2783);
B2801 <= B2783 or B2798;
B2802 <= (not B2776) or (not B2777);
B2803 <= B2783 or B2798;
B2804 <= (not B2783) and (not B2805);
B2805 <= B2783 and B2798;
B2806 <= B5684;
B2807 <= B5717;
B2808 <= B5750;
B2809 <= B5783;
B2810 <= B5816;
B2811 <= B2817 and B2816;
B2812 <= B2819 or B2818;
B2813 <= B2821 or B2820;
B2814 <= B2816 and B2822;
B2815 <= B2816 and B2823;
B2816 <= ((not B2806) and B2807) or (B2806 and (not B2807));
B2817 <= ((not B2818) and B2808) or (B2818 and (not B2808));
B2818 <= B2826 and B2825;
B2819 <= B2824 and B2808;
B2820 <= B2829 and B2828;
B2821 <= B2827 and B2808;
B2822 <= B2830 or B2807;
B2823 <= (B2808 and B2820) or ((not B2808) and (not B2820));
B2824 <= (not B2833) or (not B2834);
B2825 <= ((not B2809) and B2816) or (B2809 and (not B2816));
B2826 <= B2835 and B2828;
B2827 <= (not B2837) or (not B2836);
B2828 <= B2809 or B2810;
B2829 <= B2809 or B2816;
B2830 <= B2808 and B2820;
B2831 <= (not B2807) or (not B2808);
B2832 <= B2816 and B2831;
B2833 <= (not B2832) and (not B2816);
B2834 <= B2816 or B2831;
B2835 <= (not B2809) or (not B2810);
B2836 <= B2816 or B2831;
B2837 <= (not B2816) and (not B2838);
B2838 <= B2816 and B2831;
B2839 <= B5849;
B2840 <= B5882;
B2841 <= B5915;
B2842 <= B5948;
B2843 <= B5981;
B2844 <= B2850 and B2849;
B2845 <= B2852 or B2851;
B2846 <= B2854 or B2853;
B2847 <= B2849 and B2855;
B2848 <= B2849 and B2856;
B2849 <= ((not B2839) and B2840) or (B2839 and (not B2840));
B2850 <= ((not B2851) and B2841) or (B2851 and (not B2841));
B2851 <= B2859 and B2858;
B2852 <= B2857 and B2841;
B2853 <= B2862 and B2861;
B2854 <= B2860 and B2841;
B2855 <= B2863 or B2840;
B2856 <= (B2841 and B2853) or ((not B2841) and (not B2853));
B2857 <= (not B2866) or (not B2867);
B2858 <= ((not B2842) and B2849) or (B2842 and (not B2849));
B2859 <= B2868 and B2861;
B2860 <= (not B2870) or (not B2869);
B2861 <= B2842 or B2843;
B2862 <= B2842 or B2849;
B2863 <= B2841 and B2853;
B2864 <= (not B2840) or (not B2841);
B2865 <= B2849 and B2864;
B2866 <= (not B2865) and (not B2849);
B2867 <= B2849 or B2864;
B2868 <= (not B2842) or (not B2843);
B2869 <= B2849 or B2864;
B2870 <= (not B2849) and (not B2871);
B2871 <= B2849 and B2864;
B2872 <= B6014;
B2873 <= B6047;
B2874 <= B6080;
B2875 <= B6113;
B2876 <= B6146;
B2877 <= B2883 and B2882;
B2878 <= B2885 or B2884;
B2879 <= B2887 or B2886;
B2880 <= B2882 and B2888;
B2881 <= B2882 and B2889;
B2882 <= ((not B2872) and B2873) or (B2872 and (not B2873));
B2883 <= ((not B2884) and B2874) or (B2884 and (not B2874));
B2884 <= B2892 and B2891;
B2885 <= B2890 and B2874;
B2886 <= B2895 and B2894;
B2887 <= B2893 and B2874;
B2888 <= B2896 or B2873;
B2889 <= (B2874 and B2886) or ((not B2874) and (not B2886));
B2890 <= (not B2899) or (not B2900);
B2891 <= ((not B2875) and B2882) or (B2875 and (not B2882));
B2892 <= B2901 and B2894;
B2893 <= (not B2903) or (not B2902);
B2894 <= B2875 or B2876;
B2895 <= B2875 or B2882;
B2896 <= B2874 and B2886;
B2897 <= (not B2873) or (not B2874);
B2898 <= B2882 and B2897;
B2899 <= (not B2898) and (not B2882);
B2900 <= B2882 or B2897;
B2901 <= (not B2875) or (not B2876);
B2902 <= B2882 or B2897;
B2903 <= (not B2882) and (not B2904);
B2904 <= B2882 and B2897;
B2905 <= B6179;
B2906 <= B6212;
B2907 <= B6245;
B2908 <= B6278;
B2909 <= B6311;
B2910 <= B2916 and B2915;
B2911 <= B2918 or B2917;
B2912 <= B2920 or B2919;
B2913 <= B2915 and B2921;
B2914 <= B2915 and B2922;
B2915 <= ((not B2905) and B2906) or (B2905 and (not B2906));
B2916 <= ((not B2917) and B2907) or (B2917 and (not B2907));
B2917 <= B2925 and B2924;
B2918 <= B2923 and B2907;
B2919 <= B2928 and B2927;
B2920 <= B2926 and B2907;
B2921 <= B2929 or B2906;
B2922 <= (B2907 and B2919) or ((not B2907) and (not B2919));
B2923 <= (not B2932) or (not B2933);
B2924 <= ((not B2908) and B2915) or (B2908 and (not B2915));
B2925 <= B2934 and B2927;
B2926 <= (not B2936) or (not B2935);
B2927 <= B2908 or B2909;
B2928 <= B2908 or B2915;
B2929 <= B2907 and B2919;
B2930 <= (not B2906) or (not B2907);
B2931 <= B2915 and B2930;
B2932 <= (not B2931) and (not B2915);
B2933 <= B2915 or B2930;
B2934 <= (not B2908) or (not B2909);
B2935 <= B2915 or B2930;
B2936 <= (not B2915) and (not B2937);
B2937 <= B2915 and B2930;
B2938 <= B6344;
B2939 <= B6377;
B2940 <= B6410;
B2941 <= B6443;
B2942 <= B6476;
B2943 <= B2949 and B2948;
B2944 <= B2951 or B2950;
B2945 <= B2953 or B2952;
B2946 <= B2948 and B2954;
B2947 <= B2948 and B2955;
B2948 <= ((not B2938) and B2939) or (B2938 and (not B2939));
B2949 <= ((not B2950) and B2940) or (B2950 and (not B2940));
B2950 <= B2958 and B2957;
B2951 <= B2956 and B2940;
B2952 <= B2961 and B2960;
B2953 <= B2959 and B2940;
B2954 <= B2962 or B2939;
B2955 <= (B2940 and B2952) or ((not B2940) and (not B2952));
B2956 <= (not B2965) or (not B2966);
B2957 <= ((not B2941) and B2948) or (B2941 and (not B2948));
B2958 <= B2967 and B2960;
B2959 <= (not B2969) or (not B2968);
B2960 <= B2941 or B2942;
B2961 <= B2941 or B2948;
B2962 <= B2940 and B2952;
B2963 <= (not B2939) or (not B2940);
B2964 <= B2948 and B2963;
B2965 <= (not B2964) and (not B2948);
B2966 <= B2948 or B2963;
B2967 <= (not B2941) or (not B2942);
B2968 <= B2948 or B2963;
B2969 <= (not B2948) and (not B2970);
B2970 <= B2948 and B2963;
B2971 <= B6509;
B2972 <= B6542;
B2973 <= B6575;
B2974 <= B6608;
B2975 <= B6641;
B2976 <= B2982 and B2981;
B2977 <= B2984 or B2983;
B2978 <= B2986 or B2985;
B2979 <= B2981 and B2987;
B2980 <= B2981 and B2988;
B2981 <= ((not B2971) and B2972) or (B2971 and (not B2972));
B2982 <= ((not B2983) and B2973) or (B2983 and (not B2973));
B2983 <= B2991 and B2990;
B2984 <= B2989 and B2973;
B2985 <= B2994 and B2993;
B2986 <= B2992 and B2973;
B2987 <= B2995 or B2972;
B2988 <= (B2973 and B2985) or ((not B2973) and (not B2985));
B2989 <= (not B2998) or (not B2999);
B2990 <= ((not B2974) and B2981) or (B2974 and (not B2981));
B2991 <= B3000 and B2993;
B2992 <= (not B3002) or (not B3001);
B2993 <= B2974 or B2975;
B2994 <= B2974 or B2981;
B2995 <= B2973 and B2985;
B2996 <= (not B2972) or (not B2973);
B2997 <= B2981 and B2996;
B2998 <= (not B2997) and (not B2981);
B2999 <= B2981 or B2996;
B3000 <= (not B2974) or (not B2975);
B3001 <= B2981 or B2996;
B3002 <= (not B2981) and (not B3003);
B3003 <= B2981 and B2996;
B3004 <= B6674;
B3005 <= B6707;
B3006 <= B6740;
B3007 <= B6773;
B3008 <= B6806;
B3009 <= B3015 and B3014;
B3010 <= B3017 or B3016;
B3011 <= B3019 or B3018;
B3012 <= B3014 and B3020;
B3013 <= B3014 and B3021;
B3014 <= ((not B3004) and B3005) or (B3004 and (not B3005));
B3015 <= ((not B3016) and B3006) or (B3016 and (not B3006));
B3016 <= B3024 and B3023;
B3017 <= B3022 and B3006;
B3018 <= B3027 and B3026;
B3019 <= B3025 and B3006;
B3020 <= B3028 or B3005;
B3021 <= (B3006 and B3018) or ((not B3006) and (not B3018));
B3022 <= (not B3031) or (not B3032);
B3023 <= ((not B3007) and B3014) or (B3007 and (not B3014));
B3024 <= B3033 and B3026;
B3025 <= (not B3035) or (not B3034);
B3026 <= B3007 or B3008;
B3027 <= B3007 or B3014;
B3028 <= B3006 and B3018;
B3029 <= (not B3005) or (not B3006);
B3030 <= B3014 and B3029;
B3031 <= (not B3030) and (not B3014);
B3032 <= B3014 or B3029;
B3033 <= (not B3007) or (not B3008);
B3034 <= B3014 or B3029;
B3035 <= (not B3014) and (not B3036);
B3036 <= B3014 and B3029;
B3037 <= B6839;
B3038 <= B6872;
B3039 <= B6905;
B3040 <= B6938;
B3041 <= B6971;
B3042 <= B3048 and B3047;
B3043 <= B3050 or B3049;
B3044 <= B3052 or B3051;
B3045 <= B3047 and B3053;
B3046 <= B3047 and B3054;
B3047 <= ((not B3037) and B3038) or (B3037 and (not B3038));
B3048 <= ((not B3049) and B3039) or (B3049 and (not B3039));
B3049 <= B3057 and B3056;
B3050 <= B3055 and B3039;
B3051 <= B3060 and B3059;
B3052 <= B3058 and B3039;
B3053 <= B3061 or B3038;
B3054 <= (B3039 and B3051) or ((not B3039) and (not B3051));
B3055 <= (not B3064) or (not B3065);
B3056 <= ((not B3040) and B3047) or (B3040 and (not B3047));
B3057 <= B3066 and B3059;
B3058 <= (not B3068) or (not B3067);
B3059 <= B3040 or B3041;
B3060 <= B3040 or B3047;
B3061 <= B3039 and B3051;
B3062 <= (not B3038) or (not B3039);
B3063 <= B3047 and B3062;
B3064 <= (not B3063) and (not B3047);
B3065 <= B3047 or B3062;
B3066 <= (not B3040) or (not B3041);
B3067 <= B3047 or B3062;
B3068 <= (not B3047) and (not B3069);
B3069 <= B3047 and B3062;
B3070 <= B7004;
B3071 <= B7037;
B3072 <= B7070;
B3073 <= B7103;
B3074 <= B7136;
B3075 <= B3081 and B3080;
B3076 <= B3083 or B3082;
B3077 <= B3085 or B3084;
B3078 <= B3080 and B3086;
B3079 <= B3080 and B3087;
B3080 <= ((not B3070) and B3071) or (B3070 and (not B3071));
B3081 <= ((not B3082) and B3072) or (B3082 and (not B3072));
B3082 <= B3090 and B3089;
B3083 <= B3088 and B3072;
B3084 <= B3093 and B3092;
B3085 <= B3091 and B3072;
B3086 <= B3094 or B3071;
B3087 <= (B3072 and B3084) or ((not B3072) and (not B3084));
B3088 <= (not B3097) or (not B3098);
B3089 <= ((not B3073) and B3080) or (B3073 and (not B3080));
B3090 <= B3099 and B3092;
B3091 <= (not B3101) or (not B3100);
B3092 <= B3073 or B3074;
B3093 <= B3073 or B3080;
B3094 <= B3072 and B3084;
B3095 <= (not B3071) or (not B3072);
B3096 <= B3080 and B3095;
B3097 <= (not B3096) and (not B3080);
B3098 <= B3080 or B3095;
B3099 <= (not B3073) or (not B3074);
B3100 <= B3080 or B3095;
B3101 <= (not B3080) and (not B3102);
B3102 <= B3080 and B3095;
B3103 <= B7169;
B3104 <= B7202;
B3105 <= B7235;
B3106 <= B7268;
B3107 <= B7301;
B3108 <= B3114 and B3113;
B3109 <= B3116 or B3115;
B3110 <= B3118 or B3117;
B3111 <= B3113 and B3119;
B3112 <= B3113 and B3120;
B3113 <= ((not B3103) and B3104) or (B3103 and (not B3104));
B3114 <= ((not B3115) and B3105) or (B3115 and (not B3105));
B3115 <= B3123 and B3122;
B3116 <= B3121 and B3105;
B3117 <= B3126 and B3125;
B3118 <= B3124 and B3105;
B3119 <= B3127 or B3104;
B3120 <= (B3105 and B3117) or ((not B3105) and (not B3117));
B3121 <= (not B3130) or (not B3131);
B3122 <= ((not B3106) and B3113) or (B3106 and (not B3113));
B3123 <= B3132 and B3125;
B3124 <= (not B3134) or (not B3133);
B3125 <= B3106 or B3107;
B3126 <= B3106 or B3113;
B3127 <= B3105 and B3117;
B3128 <= (not B3104) or (not B3105);
B3129 <= B3113 and B3128;
B3130 <= (not B3129) and (not B3113);
B3131 <= B3113 or B3128;
B3132 <= (not B3106) or (not B3107);
B3133 <= B3113 or B3128;
B3134 <= (not B3113) and (not B3135);
B3135 <= B3113 and B3128;
B3136 <= B7334;
B3137 <= B7367;
B3138 <= B7400;
B3139 <= B7433;
B3140 <= B7466;
B3141 <= B3147 and B3146;
B3142 <= B3149 or B3148;
B3143 <= B3151 or B3150;
B3144 <= B3146 and B3152;
B3145 <= B3146 and B3153;
B3146 <= ((not B3136) and B3137) or (B3136 and (not B3137));
B3147 <= ((not B3148) and B3138) or (B3148 and (not B3138));
B3148 <= B3156 and B3155;
B3149 <= B3154 and B3138;
B3150 <= B3159 and B3158;
B3151 <= B3157 and B3138;
B3152 <= B3160 or B3137;
B3153 <= (B3138 and B3150) or ((not B3138) and (not B3150));
B3154 <= (not B3163) or (not B3164);
B3155 <= ((not B3139) and B3146) or (B3139 and (not B3146));
B3156 <= B3165 and B3158;
B3157 <= (not B3167) or (not B3166);
B3158 <= B3139 or B3140;
B3159 <= B3139 or B3146;
B3160 <= B3138 and B3150;
B3161 <= (not B3137) or (not B3138);
B3162 <= B3146 and B3161;
B3163 <= (not B3162) and (not B3146);
B3164 <= B3146 or B3161;
B3165 <= (not B3139) or (not B3140);
B3166 <= B3146 or B3161;
B3167 <= (not B3146) and (not B3168);
B3168 <= B3146 and B3161;
B3169 <= B7499;
B3170 <= B7532;
B3171 <= B7565;
B3172 <= B7598;
B3173 <= B7631;
B3174 <= B3180 and B3179;
B3175 <= B3182 or B3181;
B3176 <= B3184 or B3183;
B3177 <= B3179 and B3185;
B3178 <= B3179 and B3186;
B3179 <= ((not B3169) and B3170) or (B3169 and (not B3170));
B3180 <= ((not B3181) and B3171) or (B3181 and (not B3171));
B3181 <= B3189 and B3188;
B3182 <= B3187 and B3171;
B3183 <= B3192 and B3191;
B3184 <= B3190 and B3171;
B3185 <= B3193 or B3170;
B3186 <= (B3171 and B3183) or ((not B3171) and (not B3183));
B3187 <= (not B3196) or (not B3197);
B3188 <= ((not B3172) and B3179) or (B3172 and (not B3179));
B3189 <= B3198 and B3191;
B3190 <= (not B3200) or (not B3199);
B3191 <= B3172 or B3173;
B3192 <= B3172 or B3179;
B3193 <= B3171 and B3183;
B3194 <= (not B3170) or (not B3171);
B3195 <= B3179 and B3194;
B3196 <= (not B3195) and (not B3179);
B3197 <= B3179 or B3194;
B3198 <= (not B3172) or (not B3173);
B3199 <= B3179 or B3194;
B3200 <= (not B3179) and (not B3201);
B3201 <= B3179 and B3194;
B3202 <= B7664;
B3203 <= B7697;
B3204 <= B7730;
B3205 <= B7763;
B3206 <= B7796;
B3207 <= B3213 and B3212;
B3208 <= B3215 or B3214;
B3209 <= B3217 or B3216;
B3210 <= B3212 and B3218;
B3211 <= B3212 and B3219;
B3212 <= ((not B3202) and B3203) or (B3202 and (not B3203));
B3213 <= ((not B3214) and B3204) or (B3214 and (not B3204));
B3214 <= B3222 and B3221;
B3215 <= B3220 and B3204;
B3216 <= B3225 and B3224;
B3217 <= B3223 and B3204;
B3218 <= B3226 or B3203;
B3219 <= (B3204 and B3216) or ((not B3204) and (not B3216));
B3220 <= (not B3229) or (not B3230);
B3221 <= ((not B3205) and B3212) or (B3205 and (not B3212));
B3222 <= B3231 and B3224;
B3223 <= (not B3233) or (not B3232);
B3224 <= B3205 or B3206;
B3225 <= B3205 or B3212;
B3226 <= B3204 and B3216;
B3227 <= (not B3203) or (not B3204);
B3228 <= B3212 and B3227;
B3229 <= (not B3228) and (not B3212);
B3230 <= B3212 or B3227;
B3231 <= (not B3205) or (not B3206);
B3232 <= B3212 or B3227;
B3233 <= (not B3212) and (not B3234);
B3234 <= B3212 and B3227;
B3235 <= B7829;
B3236 <= B7862;
B3237 <= B7895;
B3238 <= B7928;
B3239 <= B7961;
B3240 <= B3246 and B3245;
B3241 <= B3248 or B3247;
B3242 <= B3250 or B3249;
B3243 <= B3245 and B3251;
B3244 <= B3245 and B3252;
B3245 <= ((not B3235) and B3236) or (B3235 and (not B3236));
B3246 <= ((not B3247) and B3237) or (B3247 and (not B3237));
B3247 <= B3255 and B3254;
B3248 <= B3253 and B3237;
B3249 <= B3258 and B3257;
B3250 <= B3256 and B3237;
B3251 <= B3259 or B3236;
B3252 <= (B3237 and B3249) or ((not B3237) and (not B3249));
B3253 <= (not B3262) or (not B3263);
B3254 <= ((not B3238) and B3245) or (B3238 and (not B3245));
B3255 <= B3264 and B3257;
B3256 <= (not B3266) or (not B3265);
B3257 <= B3238 or B3239;
B3258 <= B3238 or B3245;
B3259 <= B3237 and B3249;
B3260 <= (not B3236) or (not B3237);
B3261 <= B3245 and B3260;
B3262 <= (not B3261) and (not B3245);
B3263 <= B3245 or B3260;
B3264 <= (not B3238) or (not B3239);
B3265 <= B3245 or B3260;
B3266 <= (not B3245) and (not B3267);
B3267 <= B3245 and B3260;
B3268 <= B7994;
B3269 <= B8027;
B3270 <= B8060;
B3271 <= B8093;
B3272 <= B8126;
B3273 <= B3279 and B3278;
B3274 <= B3281 or B3280;
B3275 <= B3283 or B3282;
B3276 <= B3278 and B3284;
B3277 <= B3278 and B3285;
B3278 <= ((not B3268) and B3269) or (B3268 and (not B3269));
B3279 <= ((not B3280) and B3270) or (B3280 and (not B3270));
B3280 <= B3288 and B3287;
B3281 <= B3286 and B3270;
B3282 <= B3291 and B3290;
B3283 <= B3289 and B3270;
B3284 <= B3292 or B3269;
B3285 <= (B3270 and B3282) or ((not B3270) and (not B3282));
B3286 <= (not B3295) or (not B3296);
B3287 <= ((not B3271) and B3278) or (B3271 and (not B3278));
B3288 <= B3297 and B3290;
B3289 <= (not B3299) or (not B3298);
B3290 <= B3271 or B3272;
B3291 <= B3271 or B3278;
B3292 <= B3270 and B3282;
B3293 <= (not B3269) or (not B3270);
B3294 <= B3278 and B3293;
B3295 <= (not B3294) and (not B3278);
B3296 <= B3278 or B3293;
B3297 <= (not B3271) or (not B3272);
B3298 <= B3278 or B3293;
B3299 <= (not B3278) and (not B3300);
B3300 <= B3278 and B3293;
B3301 <= B8159;
B3302 <= B8192;
B3303 <= B8225;
B3304 <= B8258;
B3305 <= B8291;
B3306 <= B3312 and B3311;
B3307 <= B3314 or B3313;
B3308 <= B3316 or B3315;
B3309 <= B3311 and B3317;
B3310 <= B3311 and B3318;
B3311 <= ((not B3301) and B3302) or (B3301 and (not B3302));
B3312 <= ((not B3313) and B3303) or (B3313 and (not B3303));
B3313 <= B3321 and B3320;
B3314 <= B3319 and B3303;
B3315 <= B3324 and B3323;
B3316 <= B3322 and B3303;
B3317 <= B3325 or B3302;
B3318 <= (B3303 and B3315) or ((not B3303) and (not B3315));
B3319 <= (not B3328) or (not B3329);
B3320 <= ((not B3304) and B3311) or (B3304 and (not B3311));
B3321 <= B3330 and B3323;
B3322 <= (not B3332) or (not B3331);
B3323 <= B3304 or B3305;
B3324 <= B3304 or B3311;
B3325 <= B3303 and B3315;
B3326 <= (not B3302) or (not B3303);
B3327 <= B3311 and B3326;
B3328 <= (not B3327) and (not B3311);
B3329 <= B3311 or B3326;
B3330 <= (not B3304) or (not B3305);
B3331 <= B3311 or B3326;
B3332 <= (not B3311) and (not B3333);
B3333 <= B3311 and B3326;
B3334 <= B8324;
B3335 <= B8357;
B3336 <= B8390;
B3337 <= B8423;
B3338 <= B8456;
B3339 <= B3345 and B3344;
B3340 <= B3347 or B3346;
B3341 <= B3349 or B3348;
B3342 <= B3344 and B3350;
B3343 <= B3344 and B3351;
B3344 <= ((not B3334) and B3335) or (B3334 and (not B3335));
B3345 <= ((not B3346) and B3336) or (B3346 and (not B3336));
B3346 <= B3354 and B3353;
B3347 <= B3352 and B3336;
B3348 <= B3357 and B3356;
B3349 <= B3355 and B3336;
B3350 <= B3358 or B3335;
B3351 <= (B3336 and B3348) or ((not B3336) and (not B3348));
B3352 <= (not B3361) or (not B3362);
B3353 <= ((not B3337) and B3344) or (B3337 and (not B3344));
B3354 <= B3363 and B3356;
B3355 <= (not B3365) or (not B3364);
B3356 <= B3337 or B3338;
B3357 <= B3337 or B3344;
B3358 <= B3336 and B3348;
B3359 <= (not B3335) or (not B3336);
B3360 <= B3344 and B3359;
B3361 <= (not B3360) and (not B3344);
B3362 <= B3344 or B3359;
B3363 <= (not B3337) or (not B3338);
B3364 <= B3344 or B3359;
B3365 <= (not B3344) and (not B3366);
B3366 <= B3344 and B3359;
B3367 <= B8489;
B3368 <= B8522;
B3369 <= B8555;
B3370 <= B8588;
B3371 <= B8621;
B3372 <= B3378 and B3377;
B3373 <= B3380 or B3379;
B3374 <= B3382 or B3381;
B3375 <= B3377 and B3383;
B3376 <= B3377 and B3384;
B3377 <= ((not B3367) and B3368) or (B3367 and (not B3368));
B3378 <= ((not B3379) and B3369) or (B3379 and (not B3369));
B3379 <= B3387 and B3386;
B3380 <= B3385 and B3369;
B3381 <= B3390 and B3389;
B3382 <= B3388 and B3369;
B3383 <= B3391 or B3368;
B3384 <= (B3369 and B3381) or ((not B3369) and (not B3381));
B3385 <= (not B3394) or (not B3395);
B3386 <= ((not B3370) and B3377) or (B3370 and (not B3377));
B3387 <= B3396 and B3389;
B3388 <= (not B3398) or (not B3397);
B3389 <= B3370 or B3371;
B3390 <= B3370 or B3377;
B3391 <= B3369 and B3381;
B3392 <= (not B3368) or (not B3369);
B3393 <= B3377 and B3392;
B3394 <= (not B3393) and (not B3377);
B3395 <= B3377 or B3392;
B3396 <= (not B3370) or (not B3371);
B3397 <= B3377 or B3392;
B3398 <= (not B3377) and (not B3399);
B3399 <= B3377 and B3392;
B3400 <= B8654;
B3401 <= B8687;
B3402 <= B8720;
B3403 <= B8753;
B3404 <= B8786;
B3405 <= B3411 and B3410;
B3406 <= B3413 or B3412;
B3407 <= B3415 or B3414;
B3408 <= B3410 and B3416;
B3409 <= B3410 and B3417;
B3410 <= ((not B3400) and B3401) or (B3400 and (not B3401));
B3411 <= ((not B3412) and B3402) or (B3412 and (not B3402));
B3412 <= B3420 and B3419;
B3413 <= B3418 and B3402;
B3414 <= B3423 and B3422;
B3415 <= B3421 and B3402;
B3416 <= B3424 or B3401;
B3417 <= (B3402 and B3414) or ((not B3402) and (not B3414));
B3418 <= (not B3427) or (not B3428);
B3419 <= ((not B3403) and B3410) or (B3403 and (not B3410));
B3420 <= B3429 and B3422;
B3421 <= (not B3431) or (not B3430);
B3422 <= B3403 or B3404;
B3423 <= B3403 or B3410;
B3424 <= B3402 and B3414;
B3425 <= (not B3401) or (not B3402);
B3426 <= B3410 and B3425;
B3427 <= (not B3426) and (not B3410);
B3428 <= B3410 or B3425;
B3429 <= (not B3403) or (not B3404);
B3430 <= B3410 or B3425;
B3431 <= (not B3410) and (not B3432);
B3432 <= B3410 and B3425;
B3433 <= B8819;
B3434 <= B8852;
B3435 <= B8885;
B3436 <= B8918;
B3437 <= B8951;
B3438 <= B3444 and B3443;
B3439 <= B3446 or B3445;
B3440 <= B3448 or B3447;
B3441 <= B3443 and B3449;
B3442 <= B3443 and B3450;
B3443 <= ((not B3433) and B3434) or (B3433 and (not B3434));
B3444 <= ((not B3445) and B3435) or (B3445 and (not B3435));
B3445 <= B3453 and B3452;
B3446 <= B3451 and B3435;
B3447 <= B3456 and B3455;
B3448 <= B3454 and B3435;
B3449 <= B3457 or B3434;
B3450 <= (B3435 and B3447) or ((not B3435) and (not B3447));
B3451 <= (not B3460) or (not B3461);
B3452 <= ((not B3436) and B3443) or (B3436 and (not B3443));
B3453 <= B3462 and B3455;
B3454 <= (not B3464) or (not B3463);
B3455 <= B3436 or B3437;
B3456 <= B3436 or B3443;
B3457 <= B3435 and B3447;
B3458 <= (not B3434) or (not B3435);
B3459 <= B3443 and B3458;
B3460 <= (not B3459) and (not B3443);
B3461 <= B3443 or B3458;
B3462 <= (not B3436) or (not B3437);
B3463 <= B3443 or B3458;
B3464 <= (not B3443) and (not B3465);
B3465 <= B3443 and B3458;
B3466 <= B8984;
B3467 <= B9017;
B3468 <= B9050;
B3469 <= B9083;
B3470 <= B9116;
B3471 <= B3477 and B3476;
B3472 <= B3479 or B3478;
B3473 <= B3481 or B3480;
B3474 <= B3476 and B3482;
B3475 <= B3476 and B3483;
B3476 <= ((not B3466) and B3467) or (B3466 and (not B3467));
B3477 <= ((not B3478) and B3468) or (B3478 and (not B3468));
B3478 <= B3486 and B3485;
B3479 <= B3484 and B3468;
B3480 <= B3489 and B3488;
B3481 <= B3487 and B3468;
B3482 <= B3490 or B3467;
B3483 <= (B3468 and B3480) or ((not B3468) and (not B3480));
B3484 <= (not B3493) or (not B3494);
B3485 <= ((not B3469) and B3476) or (B3469 and (not B3476));
B3486 <= B3495 and B3488;
B3487 <= (not B3497) or (not B3496);
B3488 <= B3469 or B3470;
B3489 <= B3469 or B3476;
B3490 <= B3468 and B3480;
B3491 <= (not B3467) or (not B3468);
B3492 <= B3476 and B3491;
B3493 <= (not B3492) and (not B3476);
B3494 <= B3476 or B3491;
B3495 <= (not B3469) or (not B3470);
B3496 <= B3476 or B3491;
B3497 <= (not B3476) and (not B3498);
B3498 <= B3476 and B3491;
B3499 <= B9149;
B3500 <= B9182;
B3501 <= B9215;
B3502 <= B9248;
B3503 <= B9281;
B3504 <= B3510 and B3509;
B3505 <= B3512 or B3511;
B3506 <= B3514 or B3513;
B3507 <= B3509 and B3515;
B3508 <= B3509 and B3516;
B3509 <= ((not B3499) and B3500) or (B3499 and (not B3500));
B3510 <= ((not B3511) and B3501) or (B3511 and (not B3501));
B3511 <= B3519 and B3518;
B3512 <= B3517 and B3501;
B3513 <= B3522 and B3521;
B3514 <= B3520 and B3501;
B3515 <= B3523 or B3500;
B3516 <= (B3501 and B3513) or ((not B3501) and (not B3513));
B3517 <= (not B3526) or (not B3527);
B3518 <= ((not B3502) and B3509) or (B3502 and (not B3509));
B3519 <= B3528 and B3521;
B3520 <= (not B3530) or (not B3529);
B3521 <= B3502 or B3503;
B3522 <= B3502 or B3509;
B3523 <= B3501 and B3513;
B3524 <= (not B3500) or (not B3501);
B3525 <= B3509 and B3524;
B3526 <= (not B3525) and (not B3509);
B3527 <= B3509 or B3524;
B3528 <= (not B3502) or (not B3503);
B3529 <= B3509 or B3524;
B3530 <= (not B3509) and (not B3531);
B3531 <= B3509 and B3524;
B3532 <= B5188;
B3533 <= B5223;
B3534 <= B5256;
B3535 <= B5289;
B3536 <= B5322;
B3537 <= B3543 and B3542;
B3538 <= B3545 or B3544;
B3539 <= B3547 or B3546;
B3540 <= B3542 and B3548;
B3541 <= B3542 and B3549;
B3542 <= ((not B3532) and B3533) or (B3532 and (not B3533));
B3543 <= ((not B3544) and B3534) or (B3544 and (not B3534));
B3544 <= B3552 and B3551;
B3545 <= B3550 and B3534;
B3546 <= B3555 and B3554;
B3547 <= B3553 and B3534;
B3548 <= B3556 or B3533;
B3549 <= (B3534 and B3546) or ((not B3534) and (not B3546));
B3550 <= (not B3559) or (not B3560);
B3551 <= ((not B3535) and B3542) or (B3535 and (not B3542));
B3552 <= B3561 and B3554;
B3553 <= (not B3563) or (not B3562);
B3554 <= B3535 or B3536;
B3555 <= B3535 or B3542;
B3556 <= B3534 and B3546;
B3557 <= (not B3533) or (not B3534);
B3558 <= B3542 and B3557;
B3559 <= (not B3558) and (not B3542);
B3560 <= B3542 or B3557;
B3561 <= (not B3535) or (not B3536);
B3562 <= B3542 or B3557;
B3563 <= (not B3542) and (not B3564);
B3564 <= B3542 and B3557;
B3565 <= B5355;
B3566 <= B5388;
B3567 <= B5421;
B3568 <= B5454;
B3569 <= B5487;
B3570 <= B3576 and B3575;
B3571 <= B3578 or B3577;
B3572 <= B3580 or B3579;
B3573 <= B3575 and B3581;
B3574 <= B3575 and B3582;
B3575 <= ((not B3565) and B3566) or (B3565 and (not B3566));
B3576 <= ((not B3577) and B3567) or (B3577 and (not B3567));
B3577 <= B3585 and B3584;
B3578 <= B3583 and B3567;
B3579 <= B3588 and B3587;
B3580 <= B3586 and B3567;
B3581 <= B3589 or B3566;
B3582 <= (B3567 and B3579) or ((not B3567) and (not B3579));
B3583 <= (not B3592) or (not B3593);
B3584 <= ((not B3568) and B3575) or (B3568 and (not B3575));
B3585 <= B3594 and B3587;
B3586 <= (not B3596) or (not B3595);
B3587 <= B3568 or B3569;
B3588 <= B3568 or B3575;
B3589 <= B3567 and B3579;
B3590 <= (not B3566) or (not B3567);
B3591 <= B3575 and B3590;
B3592 <= (not B3591) and (not B3575);
B3593 <= B3575 or B3590;
B3594 <= (not B3568) or (not B3569);
B3595 <= B3575 or B3590;
B3596 <= (not B3575) and (not B3597);
B3597 <= B3575 and B3590;
B3598 <= B5520;
B3599 <= B5553;
B3600 <= B5586;
B3601 <= B5619;
B3602 <= B5652;
B3603 <= B3609 and B3608;
B3604 <= B3611 or B3610;
B3605 <= B3613 or B3612;
B3606 <= B3608 and B3614;
B3607 <= B3608 and B3615;
B3608 <= ((not B3598) and B3599) or (B3598 and (not B3599));
B3609 <= ((not B3610) and B3600) or (B3610 and (not B3600));
B3610 <= B3618 and B3617;
B3611 <= B3616 and B3600;
B3612 <= B3621 and B3620;
B3613 <= B3619 and B3600;
B3614 <= B3622 or B3599;
B3615 <= (B3600 and B3612) or ((not B3600) and (not B3612));
B3616 <= (not B3625) or (not B3626);
B3617 <= ((not B3601) and B3608) or (B3601 and (not B3608));
B3618 <= B3627 and B3620;
B3619 <= (not B3629) or (not B3628);
B3620 <= B3601 or B3602;
B3621 <= B3601 or B3608;
B3622 <= B3600 and B3612;
B3623 <= (not B3599) or (not B3600);
B3624 <= B3608 and B3623;
B3625 <= (not B3624) and (not B3608);
B3626 <= B3608 or B3623;
B3627 <= (not B3601) or (not B3602);
B3628 <= B3608 or B3623;
B3629 <= (not B3608) and (not B3630);
B3630 <= B3608 and B3623;
B3631 <= B5685;
B3632 <= B5718;
B3633 <= B5751;
B3634 <= B5784;
B3635 <= B5817;
B3636 <= B3642 and B3641;
B3637 <= B3644 or B3643;
B3638 <= B3646 or B3645;
B3639 <= B3641 and B3647;
B3640 <= B3641 and B3648;
B3641 <= ((not B3631) and B3632) or (B3631 and (not B3632));
B3642 <= ((not B3643) and B3633) or (B3643 and (not B3633));
B3643 <= B3651 and B3650;
B3644 <= B3649 and B3633;
B3645 <= B3654 and B3653;
B3646 <= B3652 and B3633;
B3647 <= B3655 or B3632;
B3648 <= (B3633 and B3645) or ((not B3633) and (not B3645));
B3649 <= (not B3658) or (not B3659);
B3650 <= ((not B3634) and B3641) or (B3634 and (not B3641));
B3651 <= B3660 and B3653;
B3652 <= (not B3662) or (not B3661);
B3653 <= B3634 or B3635;
B3654 <= B3634 or B3641;
B3655 <= B3633 and B3645;
B3656 <= (not B3632) or (not B3633);
B3657 <= B3641 and B3656;
B3658 <= (not B3657) and (not B3641);
B3659 <= B3641 or B3656;
B3660 <= (not B3634) or (not B3635);
B3661 <= B3641 or B3656;
B3662 <= (not B3641) and (not B3663);
B3663 <= B3641 and B3656;
B3664 <= B5850;
B3665 <= B5883;
B3666 <= B5916;
B3667 <= B5949;
B3668 <= B5982;
B3669 <= B3675 and B3674;
B3670 <= B3677 or B3676;
B3671 <= B3679 or B3678;
B3672 <= B3674 and B3680;
B3673 <= B3674 and B3681;
B3674 <= ((not B3664) and B3665) or (B3664 and (not B3665));
B3675 <= ((not B3676) and B3666) or (B3676 and (not B3666));
B3676 <= B3684 and B3683;
B3677 <= B3682 and B3666;
B3678 <= B3687 and B3686;
B3679 <= B3685 and B3666;
B3680 <= B3688 or B3665;
B3681 <= (B3666 and B3678) or ((not B3666) and (not B3678));
B3682 <= (not B3691) or (not B3692);
B3683 <= ((not B3667) and B3674) or (B3667 and (not B3674));
B3684 <= B3693 and B3686;
B3685 <= (not B3695) or (not B3694);
B3686 <= B3667 or B3668;
B3687 <= B3667 or B3674;
B3688 <= B3666 and B3678;
B3689 <= (not B3665) or (not B3666);
B3690 <= B3674 and B3689;
B3691 <= (not B3690) and (not B3674);
B3692 <= B3674 or B3689;
B3693 <= (not B3667) or (not B3668);
B3694 <= B3674 or B3689;
B3695 <= (not B3674) and (not B3696);
B3696 <= B3674 and B3689;
B3697 <= B6015;
B3698 <= B6048;
B3699 <= B6081;
B3700 <= B6114;
B3701 <= B6147;
B3702 <= B3708 and B3707;
B3703 <= B3710 or B3709;
B3704 <= B3712 or B3711;
B3705 <= B3707 and B3713;
B3706 <= B3707 and B3714;
B3707 <= ((not B3697) and B3698) or (B3697 and (not B3698));
B3708 <= ((not B3709) and B3699) or (B3709 and (not B3699));
B3709 <= B3717 and B3716;
B3710 <= B3715 and B3699;
B3711 <= B3720 and B3719;
B3712 <= B3718 and B3699;
B3713 <= B3721 or B3698;
B3714 <= (B3699 and B3711) or ((not B3699) and (not B3711));
B3715 <= (not B3724) or (not B3725);
B3716 <= ((not B3700) and B3707) or (B3700 and (not B3707));
B3717 <= B3726 and B3719;
B3718 <= (not B3728) or (not B3727);
B3719 <= B3700 or B3701;
B3720 <= B3700 or B3707;
B3721 <= B3699 and B3711;
B3722 <= (not B3698) or (not B3699);
B3723 <= B3707 and B3722;
B3724 <= (not B3723) and (not B3707);
B3725 <= B3707 or B3722;
B3726 <= (not B3700) or (not B3701);
B3727 <= B3707 or B3722;
B3728 <= (not B3707) and (not B3729);
B3729 <= B3707 and B3722;
B3730 <= B6180;
B3731 <= B6213;
B3732 <= B6246;
B3733 <= B6279;
B3734 <= B6312;
B3735 <= B3741 and B3740;
B3736 <= B3743 or B3742;
B3737 <= B3745 or B3744;
B3738 <= B3740 and B3746;
B3739 <= B3740 and B3747;
B3740 <= ((not B3730) and B3731) or (B3730 and (not B3731));
B3741 <= ((not B3742) and B3732) or (B3742 and (not B3732));
B3742 <= B3750 and B3749;
B3743 <= B3748 and B3732;
B3744 <= B3753 and B3752;
B3745 <= B3751 and B3732;
B3746 <= B3754 or B3731;
B3747 <= (B3732 and B3744) or ((not B3732) and (not B3744));
B3748 <= (not B3757) or (not B3758);
B3749 <= ((not B3733) and B3740) or (B3733 and (not B3740));
B3750 <= B3759 and B3752;
B3751 <= (not B3761) or (not B3760);
B3752 <= B3733 or B3734;
B3753 <= B3733 or B3740;
B3754 <= B3732 and B3744;
B3755 <= (not B3731) or (not B3732);
B3756 <= B3740 and B3755;
B3757 <= (not B3756) and (not B3740);
B3758 <= B3740 or B3755;
B3759 <= (not B3733) or (not B3734);
B3760 <= B3740 or B3755;
B3761 <= (not B3740) and (not B3762);
B3762 <= B3740 and B3755;
B3763 <= B6345;
B3764 <= B6378;
B3765 <= B6411;
B3766 <= B6444;
B3767 <= B6477;
B3768 <= B3774 and B3773;
B3769 <= B3776 or B3775;
B3770 <= B3778 or B3777;
B3771 <= B3773 and B3779;
B3772 <= B3773 and B3780;
B3773 <= ((not B3763) and B3764) or (B3763 and (not B3764));
B3774 <= ((not B3775) and B3765) or (B3775 and (not B3765));
B3775 <= B3783 and B3782;
B3776 <= B3781 and B3765;
B3777 <= B3786 and B3785;
B3778 <= B3784 and B3765;
B3779 <= B3787 or B3764;
B3780 <= (B3765 and B3777) or ((not B3765) and (not B3777));
B3781 <= (not B3790) or (not B3791);
B3782 <= ((not B3766) and B3773) or (B3766 and (not B3773));
B3783 <= B3792 and B3785;
B3784 <= (not B3794) or (not B3793);
B3785 <= B3766 or B3767;
B3786 <= B3766 or B3773;
B3787 <= B3765 and B3777;
B3788 <= (not B3764) or (not B3765);
B3789 <= B3773 and B3788;
B3790 <= (not B3789) and (not B3773);
B3791 <= B3773 or B3788;
B3792 <= (not B3766) or (not B3767);
B3793 <= B3773 or B3788;
B3794 <= (not B3773) and (not B3795);
B3795 <= B3773 and B3788;
B3796 <= B6510;
B3797 <= B6543;
B3798 <= B6576;
B3799 <= B6609;
B3800 <= B6642;
B3801 <= B3807 and B3806;
B3802 <= B3809 or B3808;
B3803 <= B3811 or B3810;
B3804 <= B3806 and B3812;
B3805 <= B3806 and B3813;
B3806 <= ((not B3796) and B3797) or (B3796 and (not B3797));
B3807 <= ((not B3808) and B3798) or (B3808 and (not B3798));
B3808 <= B3816 and B3815;
B3809 <= B3814 and B3798;
B3810 <= B3819 and B3818;
B3811 <= B3817 and B3798;
B3812 <= B3820 or B3797;
B3813 <= (B3798 and B3810) or ((not B3798) and (not B3810));
B3814 <= (not B3823) or (not B3824);
B3815 <= ((not B3799) and B3806) or (B3799 and (not B3806));
B3816 <= B3825 and B3818;
B3817 <= (not B3827) or (not B3826);
B3818 <= B3799 or B3800;
B3819 <= B3799 or B3806;
B3820 <= B3798 and B3810;
B3821 <= (not B3797) or (not B3798);
B3822 <= B3806 and B3821;
B3823 <= (not B3822) and (not B3806);
B3824 <= B3806 or B3821;
B3825 <= (not B3799) or (not B3800);
B3826 <= B3806 or B3821;
B3827 <= (not B3806) and (not B3828);
B3828 <= B3806 and B3821;
B3829 <= B6675;
B3830 <= B6708;
B3831 <= B6741;
B3832 <= B6774;
B3833 <= B6807;
B3834 <= B3840 and B3839;
B3835 <= B3842 or B3841;
B3836 <= B3844 or B3843;
B3837 <= B3839 and B3845;
B3838 <= B3839 and B3846;
B3839 <= ((not B3829) and B3830) or (B3829 and (not B3830));
B3840 <= ((not B3841) and B3831) or (B3841 and (not B3831));
B3841 <= B3849 and B3848;
B3842 <= B3847 and B3831;
B3843 <= B3852 and B3851;
B3844 <= B3850 and B3831;
B3845 <= B3853 or B3830;
B3846 <= (B3831 and B3843) or ((not B3831) and (not B3843));
B3847 <= (not B3856) or (not B3857);
B3848 <= ((not B3832) and B3839) or (B3832 and (not B3839));
B3849 <= B3858 and B3851;
B3850 <= (not B3860) or (not B3859);
B3851 <= B3832 or B3833;
B3852 <= B3832 or B3839;
B3853 <= B3831 and B3843;
B3854 <= (not B3830) or (not B3831);
B3855 <= B3839 and B3854;
B3856 <= (not B3855) and (not B3839);
B3857 <= B3839 or B3854;
B3858 <= (not B3832) or (not B3833);
B3859 <= B3839 or B3854;
B3860 <= (not B3839) and (not B3861);
B3861 <= B3839 and B3854;
B3862 <= B6840;
B3863 <= B6873;
B3864 <= B6906;
B3865 <= B6939;
B3866 <= B6972;
B3867 <= B3873 and B3872;
B3868 <= B3875 or B3874;
B3869 <= B3877 or B3876;
B3870 <= B3872 and B3878;
B3871 <= B3872 and B3879;
B3872 <= ((not B3862) and B3863) or (B3862 and (not B3863));
B3873 <= ((not B3874) and B3864) or (B3874 and (not B3864));
B3874 <= B3882 and B3881;
B3875 <= B3880 and B3864;
B3876 <= B3885 and B3884;
B3877 <= B3883 and B3864;
B3878 <= B3886 or B3863;
B3879 <= (B3864 and B3876) or ((not B3864) and (not B3876));
B3880 <= (not B3889) or (not B3890);
B3881 <= ((not B3865) and B3872) or (B3865 and (not B3872));
B3882 <= B3891 and B3884;
B3883 <= (not B3893) or (not B3892);
B3884 <= B3865 or B3866;
B3885 <= B3865 or B3872;
B3886 <= B3864 and B3876;
B3887 <= (not B3863) or (not B3864);
B3888 <= B3872 and B3887;
B3889 <= (not B3888) and (not B3872);
B3890 <= B3872 or B3887;
B3891 <= (not B3865) or (not B3866);
B3892 <= B3872 or B3887;
B3893 <= (not B3872) and (not B3894);
B3894 <= B3872 and B3887;
B3895 <= B7005;
B3896 <= B7038;
B3897 <= B7071;
B3898 <= B7104;
B3899 <= B7137;
B3900 <= B3906 and B3905;
B3901 <= B3908 or B3907;
B3902 <= B3910 or B3909;
B3903 <= B3905 and B3911;
B3904 <= B3905 and B3912;
B3905 <= ((not B3895) and B3896) or (B3895 and (not B3896));
B3906 <= ((not B3907) and B3897) or (B3907 and (not B3897));
B3907 <= B3915 and B3914;
B3908 <= B3913 and B3897;
B3909 <= B3918 and B3917;
B3910 <= B3916 and B3897;
B3911 <= B3919 or B3896;
B3912 <= (B3897 and B3909) or ((not B3897) and (not B3909));
B3913 <= (not B3922) or (not B3923);
B3914 <= ((not B3898) and B3905) or (B3898 and (not B3905));
B3915 <= B3924 and B3917;
B3916 <= (not B3926) or (not B3925);
B3917 <= B3898 or B3899;
B3918 <= B3898 or B3905;
B3919 <= B3897 and B3909;
B3920 <= (not B3896) or (not B3897);
B3921 <= B3905 and B3920;
B3922 <= (not B3921) and (not B3905);
B3923 <= B3905 or B3920;
B3924 <= (not B3898) or (not B3899);
B3925 <= B3905 or B3920;
B3926 <= (not B3905) and (not B3927);
B3927 <= B3905 and B3920;
B3928 <= B7170;
B3929 <= B7203;
B3930 <= B7236;
B3931 <= B7269;
B3932 <= B7302;
B3933 <= B3939 and B3938;
B3934 <= B3941 or B3940;
B3935 <= B3943 or B3942;
B3936 <= B3938 and B3944;
B3937 <= B3938 and B3945;
B3938 <= ((not B3928) and B3929) or (B3928 and (not B3929));
B3939 <= ((not B3940) and B3930) or (B3940 and (not B3930));
B3940 <= B3948 and B3947;
B3941 <= B3946 and B3930;
B3942 <= B3951 and B3950;
B3943 <= B3949 and B3930;
B3944 <= B3952 or B3929;
B3945 <= (B3930 and B3942) or ((not B3930) and (not B3942));
B3946 <= (not B3955) or (not B3956);
B3947 <= ((not B3931) and B3938) or (B3931 and (not B3938));
B3948 <= B3957 and B3950;
B3949 <= (not B3959) or (not B3958);
B3950 <= B3931 or B3932;
B3951 <= B3931 or B3938;
B3952 <= B3930 and B3942;
B3953 <= (not B3929) or (not B3930);
B3954 <= B3938 and B3953;
B3955 <= (not B3954) and (not B3938);
B3956 <= B3938 or B3953;
B3957 <= (not B3931) or (not B3932);
B3958 <= B3938 or B3953;
B3959 <= (not B3938) and (not B3960);
B3960 <= B3938 and B3953;
B3961 <= B7335;
B3962 <= B7368;
B3963 <= B7401;
B3964 <= B7434;
B3965 <= B7467;
B3966 <= B3972 and B3971;
B3967 <= B3974 or B3973;
B3968 <= B3976 or B3975;
B3969 <= B3971 and B3977;
B3970 <= B3971 and B3978;
B3971 <= ((not B3961) and B3962) or (B3961 and (not B3962));
B3972 <= ((not B3973) and B3963) or (B3973 and (not B3963));
B3973 <= B3981 and B3980;
B3974 <= B3979 and B3963;
B3975 <= B3984 and B3983;
B3976 <= B3982 and B3963;
B3977 <= B3985 or B3962;
B3978 <= (B3963 and B3975) or ((not B3963) and (not B3975));
B3979 <= (not B3988) or (not B3989);
B3980 <= ((not B3964) and B3971) or (B3964 and (not B3971));
B3981 <= B3990 and B3983;
B3982 <= (not B3992) or (not B3991);
B3983 <= B3964 or B3965;
B3984 <= B3964 or B3971;
B3985 <= B3963 and B3975;
B3986 <= (not B3962) or (not B3963);
B3987 <= B3971 and B3986;
B3988 <= (not B3987) and (not B3971);
B3989 <= B3971 or B3986;
B3990 <= (not B3964) or (not B3965);
B3991 <= B3971 or B3986;
B3992 <= (not B3971) and (not B3993);
B3993 <= B3971 and B3986;
B3994 <= B7500;
B3995 <= B7533;
B3996 <= B7566;
B3997 <= B7599;
B3998 <= B7632;
B3999 <= B4005 and B4004;
B4000 <= B4007 or B4006;
B4001 <= B4009 or B4008;
B4002 <= B4004 and B4010;
B4003 <= B4004 and B4011;
B4004 <= ((not B3994) and B3995) or (B3994 and (not B3995));
B4005 <= ((not B4006) and B3996) or (B4006 and (not B3996));
B4006 <= B4014 and B4013;
B4007 <= B4012 and B3996;
B4008 <= B4017 and B4016;
B4009 <= B4015 and B3996;
B4010 <= B4018 or B3995;
B4011 <= (B3996 and B4008) or ((not B3996) and (not B4008));
B4012 <= (not B4021) or (not B4022);
B4013 <= ((not B3997) and B4004) or (B3997 and (not B4004));
B4014 <= B4023 and B4016;
B4015 <= (not B4025) or (not B4024);
B4016 <= B3997 or B3998;
B4017 <= B3997 or B4004;
B4018 <= B3996 and B4008;
B4019 <= (not B3995) or (not B3996);
B4020 <= B4004 and B4019;
B4021 <= (not B4020) and (not B4004);
B4022 <= B4004 or B4019;
B4023 <= (not B3997) or (not B3998);
B4024 <= B4004 or B4019;
B4025 <= (not B4004) and (not B4026);
B4026 <= B4004 and B4019;
B4027 <= B7665;
B4028 <= B7698;
B4029 <= B7731;
B4030 <= B7764;
B4031 <= B7797;
B4032 <= B4038 and B4037;
B4033 <= B4040 or B4039;
B4034 <= B4042 or B4041;
B4035 <= B4037 and B4043;
B4036 <= B4037 and B4044;
B4037 <= ((not B4027) and B4028) or (B4027 and (not B4028));
B4038 <= ((not B4039) and B4029) or (B4039 and (not B4029));
B4039 <= B4047 and B4046;
B4040 <= B4045 and B4029;
B4041 <= B4050 and B4049;
B4042 <= B4048 and B4029;
B4043 <= B4051 or B4028;
B4044 <= (B4029 and B4041) or ((not B4029) and (not B4041));
B4045 <= (not B4054) or (not B4055);
B4046 <= ((not B4030) and B4037) or (B4030 and (not B4037));
B4047 <= B4056 and B4049;
B4048 <= (not B4058) or (not B4057);
B4049 <= B4030 or B4031;
B4050 <= B4030 or B4037;
B4051 <= B4029 and B4041;
B4052 <= (not B4028) or (not B4029);
B4053 <= B4037 and B4052;
B4054 <= (not B4053) and (not B4037);
B4055 <= B4037 or B4052;
B4056 <= (not B4030) or (not B4031);
B4057 <= B4037 or B4052;
B4058 <= (not B4037) and (not B4059);
B4059 <= B4037 and B4052;
B4060 <= B7830;
B4061 <= B7863;
B4062 <= B7896;
B4063 <= B7929;
B4064 <= B7962;
B4065 <= B4071 and B4070;
B4066 <= B4073 or B4072;
B4067 <= B4075 or B4074;
B4068 <= B4070 and B4076;
B4069 <= B4070 and B4077;
B4070 <= ((not B4060) and B4061) or (B4060 and (not B4061));
B4071 <= ((not B4072) and B4062) or (B4072 and (not B4062));
B4072 <= B4080 and B4079;
B4073 <= B4078 and B4062;
B4074 <= B4083 and B4082;
B4075 <= B4081 and B4062;
B4076 <= B4084 or B4061;
B4077 <= (B4062 and B4074) or ((not B4062) and (not B4074));
B4078 <= (not B4087) or (not B4088);
B4079 <= ((not B4063) and B4070) or (B4063 and (not B4070));
B4080 <= B4089 and B4082;
B4081 <= (not B4091) or (not B4090);
B4082 <= B4063 or B4064;
B4083 <= B4063 or B4070;
B4084 <= B4062 and B4074;
B4085 <= (not B4061) or (not B4062);
B4086 <= B4070 and B4085;
B4087 <= (not B4086) and (not B4070);
B4088 <= B4070 or B4085;
B4089 <= (not B4063) or (not B4064);
B4090 <= B4070 or B4085;
B4091 <= (not B4070) and (not B4092);
B4092 <= B4070 and B4085;
B4093 <= B7995;
B4094 <= B8028;
B4095 <= B8061;
B4096 <= B8094;
B4097 <= B8127;
B4098 <= B4104 and B4103;
B4099 <= B4106 or B4105;
B4100 <= B4108 or B4107;
B4101 <= B4103 and B4109;
B4102 <= B4103 and B4110;
B4103 <= ((not B4093) and B4094) or (B4093 and (not B4094));
B4104 <= ((not B4105) and B4095) or (B4105 and (not B4095));
B4105 <= B4113 and B4112;
B4106 <= B4111 and B4095;
B4107 <= B4116 and B4115;
B4108 <= B4114 and B4095;
B4109 <= B4117 or B4094;
B4110 <= (B4095 and B4107) or ((not B4095) and (not B4107));
B4111 <= (not B4120) or (not B4121);
B4112 <= ((not B4096) and B4103) or (B4096 and (not B4103));
B4113 <= B4122 and B4115;
B4114 <= (not B4124) or (not B4123);
B4115 <= B4096 or B4097;
B4116 <= B4096 or B4103;
B4117 <= B4095 and B4107;
B4118 <= (not B4094) or (not B4095);
B4119 <= B4103 and B4118;
B4120 <= (not B4119) and (not B4103);
B4121 <= B4103 or B4118;
B4122 <= (not B4096) or (not B4097);
B4123 <= B4103 or B4118;
B4124 <= (not B4103) and (not B4125);
B4125 <= B4103 and B4118;
B4126 <= B8160;
B4127 <= B8193;
B4128 <= B8226;
B4129 <= B8259;
B4130 <= B8292;
B4131 <= B4137 and B4136;
B4132 <= B4139 or B4138;
B4133 <= B4141 or B4140;
B4134 <= B4136 and B4142;
B4135 <= B4136 and B4143;
B4136 <= ((not B4126) and B4127) or (B4126 and (not B4127));
B4137 <= ((not B4138) and B4128) or (B4138 and (not B4128));
B4138 <= B4146 and B4145;
B4139 <= B4144 and B4128;
B4140 <= B4149 and B4148;
B4141 <= B4147 and B4128;
B4142 <= B4150 or B4127;
B4143 <= (B4128 and B4140) or ((not B4128) and (not B4140));
B4144 <= (not B4153) or (not B4154);
B4145 <= ((not B4129) and B4136) or (B4129 and (not B4136));
B4146 <= B4155 and B4148;
B4147 <= (not B4157) or (not B4156);
B4148 <= B4129 or B4130;
B4149 <= B4129 or B4136;
B4150 <= B4128 and B4140;
B4151 <= (not B4127) or (not B4128);
B4152 <= B4136 and B4151;
B4153 <= (not B4152) and (not B4136);
B4154 <= B4136 or B4151;
B4155 <= (not B4129) or (not B4130);
B4156 <= B4136 or B4151;
B4157 <= (not B4136) and (not B4158);
B4158 <= B4136 and B4151;
B4159 <= B8325;
B4160 <= B8358;
B4161 <= B8391;
B4162 <= B8424;
B4163 <= B8457;
B4164 <= B4170 and B4169;
B4165 <= B4172 or B4171;
B4166 <= B4174 or B4173;
B4167 <= B4169 and B4175;
B4168 <= B4169 and B4176;
B4169 <= ((not B4159) and B4160) or (B4159 and (not B4160));
B4170 <= ((not B4171) and B4161) or (B4171 and (not B4161));
B4171 <= B4179 and B4178;
B4172 <= B4177 and B4161;
B4173 <= B4182 and B4181;
B4174 <= B4180 and B4161;
B4175 <= B4183 or B4160;
B4176 <= (B4161 and B4173) or ((not B4161) and (not B4173));
B4177 <= (not B4186) or (not B4187);
B4178 <= ((not B4162) and B4169) or (B4162 and (not B4169));
B4179 <= B4188 and B4181;
B4180 <= (not B4190) or (not B4189);
B4181 <= B4162 or B4163;
B4182 <= B4162 or B4169;
B4183 <= B4161 and B4173;
B4184 <= (not B4160) or (not B4161);
B4185 <= B4169 and B4184;
B4186 <= (not B4185) and (not B4169);
B4187 <= B4169 or B4184;
B4188 <= (not B4162) or (not B4163);
B4189 <= B4169 or B4184;
B4190 <= (not B4169) and (not B4191);
B4191 <= B4169 and B4184;
B4192 <= B8490;
B4193 <= B8523;
B4194 <= B8556;
B4195 <= B8589;
B4196 <= B8622;
B4197 <= B4203 and B4202;
B4198 <= B4205 or B4204;
B4199 <= B4207 or B4206;
B4200 <= B4202 and B4208;
B4201 <= B4202 and B4209;
B4202 <= ((not B4192) and B4193) or (B4192 and (not B4193));
B4203 <= ((not B4204) and B4194) or (B4204 and (not B4194));
B4204 <= B4212 and B4211;
B4205 <= B4210 and B4194;
B4206 <= B4215 and B4214;
B4207 <= B4213 and B4194;
B4208 <= B4216 or B4193;
B4209 <= (B4194 and B4206) or ((not B4194) and (not B4206));
B4210 <= (not B4219) or (not B4220);
B4211 <= ((not B4195) and B4202) or (B4195 and (not B4202));
B4212 <= B4221 and B4214;
B4213 <= (not B4223) or (not B4222);
B4214 <= B4195 or B4196;
B4215 <= B4195 or B4202;
B4216 <= B4194 and B4206;
B4217 <= (not B4193) or (not B4194);
B4218 <= B4202 and B4217;
B4219 <= (not B4218) and (not B4202);
B4220 <= B4202 or B4217;
B4221 <= (not B4195) or (not B4196);
B4222 <= B4202 or B4217;
B4223 <= (not B4202) and (not B4224);
B4224 <= B4202 and B4217;
B4225 <= B8655;
B4226 <= B8688;
B4227 <= B8721;
B4228 <= B8754;
B4229 <= B8787;
B4230 <= B4236 and B4235;
B4231 <= B4238 or B4237;
B4232 <= B4240 or B4239;
B4233 <= B4235 and B4241;
B4234 <= B4235 and B4242;
B4235 <= ((not B4225) and B4226) or (B4225 and (not B4226));
B4236 <= ((not B4237) and B4227) or (B4237 and (not B4227));
B4237 <= B4245 and B4244;
B4238 <= B4243 and B4227;
B4239 <= B4248 and B4247;
B4240 <= B4246 and B4227;
B4241 <= B4249 or B4226;
B4242 <= (B4227 and B4239) or ((not B4227) and (not B4239));
B4243 <= (not B4252) or (not B4253);
B4244 <= ((not B4228) and B4235) or (B4228 and (not B4235));
B4245 <= B4254 and B4247;
B4246 <= (not B4256) or (not B4255);
B4247 <= B4228 or B4229;
B4248 <= B4228 or B4235;
B4249 <= B4227 and B4239;
B4250 <= (not B4226) or (not B4227);
B4251 <= B4235 and B4250;
B4252 <= (not B4251) and (not B4235);
B4253 <= B4235 or B4250;
B4254 <= (not B4228) or (not B4229);
B4255 <= B4235 or B4250;
B4256 <= (not B4235) and (not B4257);
B4257 <= B4235 and B4250;
B4258 <= B8820;
B4259 <= B8853;
B4260 <= B8886;
B4261 <= B8919;
B4262 <= B8952;
B4263 <= B4269 and B4268;
B4264 <= B4271 or B4270;
B4265 <= B4273 or B4272;
B4266 <= B4268 and B4274;
B4267 <= B4268 and B4275;
B4268 <= ((not B4258) and B4259) or (B4258 and (not B4259));
B4269 <= ((not B4270) and B4260) or (B4270 and (not B4260));
B4270 <= B4278 and B4277;
B4271 <= B4276 and B4260;
B4272 <= B4281 and B4280;
B4273 <= B4279 and B4260;
B4274 <= B4282 or B4259;
B4275 <= (B4260 and B4272) or ((not B4260) and (not B4272));
B4276 <= (not B4285) or (not B4286);
B4277 <= ((not B4261) and B4268) or (B4261 and (not B4268));
B4278 <= B4287 and B4280;
B4279 <= (not B4289) or (not B4288);
B4280 <= B4261 or B4262;
B4281 <= B4261 or B4268;
B4282 <= B4260 and B4272;
B4283 <= (not B4259) or (not B4260);
B4284 <= B4268 and B4283;
B4285 <= (not B4284) and (not B4268);
B4286 <= B4268 or B4283;
B4287 <= (not B4261) or (not B4262);
B4288 <= B4268 or B4283;
B4289 <= (not B4268) and (not B4290);
B4290 <= B4268 and B4283;
B4291 <= B8985;
B4292 <= B9018;
B4293 <= B9051;
B4294 <= B9084;
B4295 <= B9117;
B4296 <= B4302 and B4301;
B4297 <= B4304 or B4303;
B4298 <= B4306 or B4305;
B4299 <= B4301 and B4307;
B4300 <= B4301 and B4308;
B4301 <= ((not B4291) and B4292) or (B4291 and (not B4292));
B4302 <= ((not B4303) and B4293) or (B4303 and (not B4293));
B4303 <= B4311 and B4310;
B4304 <= B4309 and B4293;
B4305 <= B4314 and B4313;
B4306 <= B4312 and B4293;
B4307 <= B4315 or B4292;
B4308 <= (B4293 and B4305) or ((not B4293) and (not B4305));
B4309 <= (not B4318) or (not B4319);
B4310 <= ((not B4294) and B4301) or (B4294 and (not B4301));
B4311 <= B4320 and B4313;
B4312 <= (not B4322) or (not B4321);
B4313 <= B4294 or B4295;
B4314 <= B4294 or B4301;
B4315 <= B4293 and B4305;
B4316 <= (not B4292) or (not B4293);
B4317 <= B4301 and B4316;
B4318 <= (not B4317) and (not B4301);
B4319 <= B4301 or B4316;
B4320 <= (not B4294) or (not B4295);
B4321 <= B4301 or B4316;
B4322 <= (not B4301) and (not B4323);
B4323 <= B4301 and B4316;
B4324 <= B9150;
B4325 <= B9183;
B4326 <= B9216;
B4327 <= B9249;
B4328 <= B9282;
B4329 <= B4335 and B4334;
B4330 <= B4337 or B4336;
B4331 <= B4339 or B4338;
B4332 <= B4334 and B4340;
B4333 <= B4334 and B4341;
B4334 <= ((not B4324) and B4325) or (B4324 and (not B4325));
B4335 <= ((not B4336) and B4326) or (B4336 and (not B4326));
B4336 <= B4344 and B4343;
B4337 <= B4342 and B4326;
B4338 <= B4347 and B4346;
B4339 <= B4345 and B4326;
B4340 <= B4348 or B4325;
B4341 <= (B4326 and B4338) or ((not B4326) and (not B4338));
B4342 <= (not B4351) or (not B4352);
B4343 <= ((not B4327) and B4334) or (B4327 and (not B4334));
B4344 <= B4353 and B4346;
B4345 <= (not B4355) or (not B4354);
B4346 <= B4327 or B4328;
B4347 <= B4327 or B4334;
B4348 <= B4326 and B4338;
B4349 <= (not B4325) or (not B4326);
B4350 <= B4334 and B4349;
B4351 <= (not B4350) and (not B4334);
B4352 <= B4334 or B4349;
B4353 <= (not B4327) or (not B4328);
B4354 <= B4334 or B4349;
B4355 <= (not B4334) and (not B4356);
B4356 <= B4334 and B4349;
B4357 <= B5187;
B4358 <= B5224;
B4359 <= B5257;
B4360 <= B5290;
B4361 <= B5323;
B4362 <= B4368 and B4367;
B4363 <= B4370 or B4369;
B4364 <= B4372 or B4371;
B4365 <= B4367 and B4373;
B4366 <= B4367 and B4374;
B4367 <= ((not B4357) and B4358) or (B4357 and (not B4358));
B4368 <= ((not B4369) and B4359) or (B4369 and (not B4359));
B4369 <= B4377 and B4376;
B4370 <= B4375 and B4359;
B4371 <= B4380 and B4379;
B4372 <= B4378 and B4359;
B4373 <= B4381 or B4358;
B4374 <= (B4359 and B4371) or ((not B4359) and (not B4371));
B4375 <= (not B4384) or (not B4385);
B4376 <= ((not B4360) and B4367) or (B4360 and (not B4367));
B4377 <= B4386 and B4379;
B4378 <= (not B4388) or (not B4387);
B4379 <= B4360 or B4361;
B4380 <= B4360 or B4367;
B4381 <= B4359 and B4371;
B4382 <= (not B4358) or (not B4359);
B4383 <= B4367 and B4382;
B4384 <= (not B4383) and (not B4367);
B4385 <= B4367 or B4382;
B4386 <= (not B4360) or (not B4361);
B4387 <= B4367 or B4382;
B4388 <= (not B4367) and (not B4389);
B4389 <= B4367 and B4382;
B4390 <= B5356;
B4391 <= B5389;
B4392 <= B5422;
B4393 <= B5455;
B4394 <= B5488;
B4395 <= B4401 and B4400;
B4396 <= B4403 or B4402;
B4397 <= B4405 or B4404;
B4398 <= B4400 and B4406;
B4399 <= B4400 and B4407;
B4400 <= ((not B4390) and B4391) or (B4390 and (not B4391));
B4401 <= ((not B4402) and B4392) or (B4402 and (not B4392));
B4402 <= B4410 and B4409;
B4403 <= B4408 and B4392;
B4404 <= B4413 and B4412;
B4405 <= B4411 and B4392;
B4406 <= B4414 or B4391;
B4407 <= (B4392 and B4404) or ((not B4392) and (not B4404));
B4408 <= (not B4417) or (not B4418);
B4409 <= ((not B4393) and B4400) or (B4393 and (not B4400));
B4410 <= B4419 and B4412;
B4411 <= (not B4421) or (not B4420);
B4412 <= B4393 or B4394;
B4413 <= B4393 or B4400;
B4414 <= B4392 and B4404;
B4415 <= (not B4391) or (not B4392);
B4416 <= B4400 and B4415;
B4417 <= (not B4416) and (not B4400);
B4418 <= B4400 or B4415;
B4419 <= (not B4393) or (not B4394);
B4420 <= B4400 or B4415;
B4421 <= (not B4400) and (not B4422);
B4422 <= B4400 and B4415;
B4423 <= B5521;
B4424 <= B5554;
B4425 <= B5587;
B4426 <= B5620;
B4427 <= B5653;
B4428 <= B4434 and B4433;
B4429 <= B4436 or B4435;
B4430 <= B4438 or B4437;
B4431 <= B4433 and B4439;
B4432 <= B4433 and B4440;
B4433 <= ((not B4423) and B4424) or (B4423 and (not B4424));
B4434 <= ((not B4435) and B4425) or (B4435 and (not B4425));
B4435 <= B4443 and B4442;
B4436 <= B4441 and B4425;
B4437 <= B4446 and B4445;
B4438 <= B4444 and B4425;
B4439 <= B4447 or B4424;
B4440 <= (B4425 and B4437) or ((not B4425) and (not B4437));
B4441 <= (not B4450) or (not B4451);
B4442 <= ((not B4426) and B4433) or (B4426 and (not B4433));
B4443 <= B4452 and B4445;
B4444 <= (not B4454) or (not B4453);
B4445 <= B4426 or B4427;
B4446 <= B4426 or B4433;
B4447 <= B4425 and B4437;
B4448 <= (not B4424) or (not B4425);
B4449 <= B4433 and B4448;
B4450 <= (not B4449) and (not B4433);
B4451 <= B4433 or B4448;
B4452 <= (not B4426) or (not B4427);
B4453 <= B4433 or B4448;
B4454 <= (not B4433) and (not B4455);
B4455 <= B4433 and B4448;
B4456 <= B5686;
B4457 <= B5719;
B4458 <= B5752;
B4459 <= B5785;
B4460 <= B5818;
B4461 <= B4467 and B4466;
B4462 <= B4469 or B4468;
B4463 <= B4471 or B4470;
B4464 <= B4466 and B4472;
B4465 <= B4466 and B4473;
B4466 <= ((not B4456) and B4457) or (B4456 and (not B4457));
B4467 <= ((not B4468) and B4458) or (B4468 and (not B4458));
B4468 <= B4476 and B4475;
B4469 <= B4474 and B4458;
B4470 <= B4479 and B4478;
B4471 <= B4477 and B4458;
B4472 <= B4480 or B4457;
B4473 <= (B4458 and B4470) or ((not B4458) and (not B4470));
B4474 <= (not B4483) or (not B4484);
B4475 <= ((not B4459) and B4466) or (B4459 and (not B4466));
B4476 <= B4485 and B4478;
B4477 <= (not B4487) or (not B4486);
B4478 <= B4459 or B4460;
B4479 <= B4459 or B4466;
B4480 <= B4458 and B4470;
B4481 <= (not B4457) or (not B4458);
B4482 <= B4466 and B4481;
B4483 <= (not B4482) and (not B4466);
B4484 <= B4466 or B4481;
B4485 <= (not B4459) or (not B4460);
B4486 <= B4466 or B4481;
B4487 <= (not B4466) and (not B4488);
B4488 <= B4466 and B4481;
B4489 <= B5851;
B4490 <= B5884;
B4491 <= B5917;
B4492 <= B5950;
B4493 <= B5983;
B4494 <= B4500 and B4499;
B4495 <= B4502 or B4501;
B4496 <= B4504 or B4503;
B4497 <= B4499 and B4505;
B4498 <= B4499 and B4506;
B4499 <= ((not B4489) and B4490) or (B4489 and (not B4490));
B4500 <= ((not B4501) and B4491) or (B4501 and (not B4491));
B4501 <= B4509 and B4508;
B4502 <= B4507 and B4491;
B4503 <= B4512 and B4511;
B4504 <= B4510 and B4491;
B4505 <= B4513 or B4490;
B4506 <= (B4491 and B4503) or ((not B4491) and (not B4503));
B4507 <= (not B4516) or (not B4517);
B4508 <= ((not B4492) and B4499) or (B4492 and (not B4499));
B4509 <= B4518 and B4511;
B4510 <= (not B4520) or (not B4519);
B4511 <= B4492 or B4493;
B4512 <= B4492 or B4499;
B4513 <= B4491 and B4503;
B4514 <= (not B4490) or (not B4491);
B4515 <= B4499 and B4514;
B4516 <= (not B4515) and (not B4499);
B4517 <= B4499 or B4514;
B4518 <= (not B4492) or (not B4493);
B4519 <= B4499 or B4514;
B4520 <= (not B4499) and (not B4521);
B4521 <= B4499 and B4514;
B4522 <= B6016;
B4523 <= B6049;
B4524 <= B6082;
B4525 <= B6115;
B4526 <= B6148;
B4527 <= B4533 and B4532;
B4528 <= B4535 or B4534;
B4529 <= B4537 or B4536;
B4530 <= B4532 and B4538;
B4531 <= B4532 and B4539;
B4532 <= ((not B4522) and B4523) or (B4522 and (not B4523));
B4533 <= ((not B4534) and B4524) or (B4534 and (not B4524));
B4534 <= B4542 and B4541;
B4535 <= B4540 and B4524;
B4536 <= B4545 and B4544;
B4537 <= B4543 and B4524;
B4538 <= B4546 or B4523;
B4539 <= (B4524 and B4536) or ((not B4524) and (not B4536));
B4540 <= (not B4549) or (not B4550);
B4541 <= ((not B4525) and B4532) or (B4525 and (not B4532));
B4542 <= B4551 and B4544;
B4543 <= (not B4553) or (not B4552);
B4544 <= B4525 or B4526;
B4545 <= B4525 or B4532;
B4546 <= B4524 and B4536;
B4547 <= (not B4523) or (not B4524);
B4548 <= B4532 and B4547;
B4549 <= (not B4548) and (not B4532);
B4550 <= B4532 or B4547;
B4551 <= (not B4525) or (not B4526);
B4552 <= B4532 or B4547;
B4553 <= (not B4532) and (not B4554);
B4554 <= B4532 and B4547;
B4555 <= B6181;
B4556 <= B6214;
B4557 <= B6247;
B4558 <= B6280;
B4559 <= B6313;
B4560 <= B4566 and B4565;
B4561 <= B4568 or B4567;
B4562 <= B4570 or B4569;
B4563 <= B4565 and B4571;
B4564 <= B4565 and B4572;
B4565 <= ((not B4555) and B4556) or (B4555 and (not B4556));
B4566 <= ((not B4567) and B4557) or (B4567 and (not B4557));
B4567 <= B4575 and B4574;
B4568 <= B4573 and B4557;
B4569 <= B4578 and B4577;
B4570 <= B4576 and B4557;
B4571 <= B4579 or B4556;
B4572 <= (B4557 and B4569) or ((not B4557) and (not B4569));
B4573 <= (not B4582) or (not B4583);
B4574 <= ((not B4558) and B4565) or (B4558 and (not B4565));
B4575 <= B4584 and B4577;
B4576 <= (not B4586) or (not B4585);
B4577 <= B4558 or B4559;
B4578 <= B4558 or B4565;
B4579 <= B4557 and B4569;
B4580 <= (not B4556) or (not B4557);
B4581 <= B4565 and B4580;
B4582 <= (not B4581) and (not B4565);
B4583 <= B4565 or B4580;
B4584 <= (not B4558) or (not B4559);
B4585 <= B4565 or B4580;
B4586 <= (not B4565) and (not B4587);
B4587 <= B4565 and B4580;
B4588 <= B6346;
B4589 <= B6379;
B4590 <= B6412;
B4591 <= B6445;
B4592 <= B6478;
B4593 <= B4599 and B4598;
B4594 <= B4601 or B4600;
B4595 <= B4603 or B4602;
B4596 <= B4598 and B4604;
B4597 <= B4598 and B4605;
B4598 <= ((not B4588) and B4589) or (B4588 and (not B4589));
B4599 <= ((not B4600) and B4590) or (B4600 and (not B4590));
B4600 <= B4608 and B4607;
B4601 <= B4606 and B4590;
B4602 <= B4611 and B4610;
B4603 <= B4609 and B4590;
B4604 <= B4612 or B4589;
B4605 <= (B4590 and B4602) or ((not B4590) and (not B4602));
B4606 <= (not B4615) or (not B4616);
B4607 <= ((not B4591) and B4598) or (B4591 and (not B4598));
B4608 <= B4617 and B4610;
B4609 <= (not B4619) or (not B4618);
B4610 <= B4591 or B4592;
B4611 <= B4591 or B4598;
B4612 <= B4590 and B4602;
B4613 <= (not B4589) or (not B4590);
B4614 <= B4598 and B4613;
B4615 <= (not B4614) and (not B4598);
B4616 <= B4598 or B4613;
B4617 <= (not B4591) or (not B4592);
B4618 <= B4598 or B4613;
B4619 <= (not B4598) and (not B4620);
B4620 <= B4598 and B4613;
B4621 <= B6511;
B4622 <= B6544;
B4623 <= B6577;
B4624 <= B6610;
B4625 <= B6643;
B4626 <= B4632 and B4631;
B4627 <= B4634 or B4633;
B4628 <= B4636 or B4635;
B4629 <= B4631 and B4637;
B4630 <= B4631 and B4638;
B4631 <= ((not B4621) and B4622) or (B4621 and (not B4622));
B4632 <= ((not B4633) and B4623) or (B4633 and (not B4623));
B4633 <= B4641 and B4640;
B4634 <= B4639 and B4623;
B4635 <= B4644 and B4643;
B4636 <= B4642 and B4623;
B4637 <= B4645 or B4622;
B4638 <= (B4623 and B4635) or ((not B4623) and (not B4635));
B4639 <= (not B4648) or (not B4649);
B4640 <= ((not B4624) and B4631) or (B4624 and (not B4631));
B4641 <= B4650 and B4643;
B4642 <= (not B4652) or (not B4651);
B4643 <= B4624 or B4625;
B4644 <= B4624 or B4631;
B4645 <= B4623 and B4635;
B4646 <= (not B4622) or (not B4623);
B4647 <= B4631 and B4646;
B4648 <= (not B4647) and (not B4631);
B4649 <= B4631 or B4646;
B4650 <= (not B4624) or (not B4625);
B4651 <= B4631 or B4646;
B4652 <= (not B4631) and (not B4653);
B4653 <= B4631 and B4646;
B4654 <= B6676;
B4655 <= B6709;
B4656 <= B6742;
B4657 <= B6775;
B4658 <= B6808;
B4659 <= B4665 and B4664;
B4660 <= B4667 or B4666;
B4661 <= B4669 or B4668;
B4662 <= B4664 and B4670;
B4663 <= B4664 and B4671;
B4664 <= ((not B4654) and B4655) or (B4654 and (not B4655));
B4665 <= ((not B4666) and B4656) or (B4666 and (not B4656));
B4666 <= B4674 and B4673;
B4667 <= B4672 and B4656;
B4668 <= B4677 and B4676;
B4669 <= B4675 and B4656;
B4670 <= B4678 or B4655;
B4671 <= (B4656 and B4668) or ((not B4656) and (not B4668));
B4672 <= (not B4681) or (not B4682);
B4673 <= ((not B4657) and B4664) or (B4657 and (not B4664));
B4674 <= B4683 and B4676;
B4675 <= (not B4685) or (not B4684);
B4676 <= B4657 or B4658;
B4677 <= B4657 or B4664;
B4678 <= B4656 and B4668;
B4679 <= (not B4655) or (not B4656);
B4680 <= B4664 and B4679;
B4681 <= (not B4680) and (not B4664);
B4682 <= B4664 or B4679;
B4683 <= (not B4657) or (not B4658);
B4684 <= B4664 or B4679;
B4685 <= (not B4664) and (not B4686);
B4686 <= B4664 and B4679;
B4687 <= B6841;
B4688 <= B6874;
B4689 <= B6907;
B4690 <= B6940;
B4691 <= B6973;
B4692 <= B4698 and B4697;
B4693 <= B4700 or B4699;
B4694 <= B4702 or B4701;
B4695 <= B4697 and B4703;
B4696 <= B4697 and B4704;
B4697 <= ((not B4687) and B4688) or (B4687 and (not B4688));
B4698 <= ((not B4699) and B4689) or (B4699 and (not B4689));
B4699 <= B4707 and B4706;
B4700 <= B4705 and B4689;
B4701 <= B4710 and B4709;
B4702 <= B4708 and B4689;
B4703 <= B4711 or B4688;
B4704 <= (B4689 and B4701) or ((not B4689) and (not B4701));
B4705 <= (not B4714) or (not B4715);
B4706 <= ((not B4690) and B4697) or (B4690 and (not B4697));
B4707 <= B4716 and B4709;
B4708 <= (not B4718) or (not B4717);
B4709 <= B4690 or B4691;
B4710 <= B4690 or B4697;
B4711 <= B4689 and B4701;
B4712 <= (not B4688) or (not B4689);
B4713 <= B4697 and B4712;
B4714 <= (not B4713) and (not B4697);
B4715 <= B4697 or B4712;
B4716 <= (not B4690) or (not B4691);
B4717 <= B4697 or B4712;
B4718 <= (not B4697) and (not B4719);
B4719 <= B4697 and B4712;
B4720 <= B7006;
B4721 <= B7039;
B4722 <= B7072;
B4723 <= B7105;
B4724 <= B7138;
B4725 <= B4731 and B4730;
B4726 <= B4733 or B4732;
B4727 <= B4735 or B4734;
B4728 <= B4730 and B4736;
B4729 <= B4730 and B4737;
B4730 <= ((not B4720) and B4721) or (B4720 and (not B4721));
B4731 <= ((not B4732) and B4722) or (B4732 and (not B4722));
B4732 <= B4740 and B4739;
B4733 <= B4738 and B4722;
B4734 <= B4743 and B4742;
B4735 <= B4741 and B4722;
B4736 <= B4744 or B4721;
B4737 <= (B4722 and B4734) or ((not B4722) and (not B4734));
B4738 <= (not B4747) or (not B4748);
B4739 <= ((not B4723) and B4730) or (B4723 and (not B4730));
B4740 <= B4749 and B4742;
B4741 <= (not B4751) or (not B4750);
B4742 <= B4723 or B4724;
B4743 <= B4723 or B4730;
B4744 <= B4722 and B4734;
B4745 <= (not B4721) or (not B4722);
B4746 <= B4730 and B4745;
B4747 <= (not B4746) and (not B4730);
B4748 <= B4730 or B4745;
B4749 <= (not B4723) or (not B4724);
B4750 <= B4730 or B4745;
B4751 <= (not B4730) and (not B4752);
B4752 <= B4730 and B4745;
B4753 <= B7171;
B4754 <= B7204;
B4755 <= B7237;
B4756 <= B7270;
B4757 <= B7303;
B4758 <= B4764 and B4763;
B4759 <= B4766 or B4765;
B4760 <= B4768 or B4767;
B4761 <= B4763 and B4769;
B4762 <= B4763 and B4770;
B4763 <= ((not B4753) and B4754) or (B4753 and (not B4754));
B4764 <= ((not B4765) and B4755) or (B4765 and (not B4755));
B4765 <= B4773 and B4772;
B4766 <= B4771 and B4755;
B4767 <= B4776 and B4775;
B4768 <= B4774 and B4755;
B4769 <= B4777 or B4754;
B4770 <= (B4755 and B4767) or ((not B4755) and (not B4767));
B4771 <= (not B4780) or (not B4781);
B4772 <= ((not B4756) and B4763) or (B4756 and (not B4763));
B4773 <= B4782 and B4775;
B4774 <= (not B4784) or (not B4783);
B4775 <= B4756 or B4757;
B4776 <= B4756 or B4763;
B4777 <= B4755 and B4767;
B4778 <= (not B4754) or (not B4755);
B4779 <= B4763 and B4778;
B4780 <= (not B4779) and (not B4763);
B4781 <= B4763 or B4778;
B4782 <= (not B4756) or (not B4757);
B4783 <= B4763 or B4778;
B4784 <= (not B4763) and (not B4785);
B4785 <= B4763 and B4778;
B4786 <= B7336;
B4787 <= B7369;
B4788 <= B7402;
B4789 <= B7435;
B4790 <= B7468;
B4791 <= B4797 and B4796;
B4792 <= B4799 or B4798;
B4793 <= B4801 or B4800;
B4794 <= B4796 and B4802;
B4795 <= B4796 and B4803;
B4796 <= ((not B4786) and B4787) or (B4786 and (not B4787));
B4797 <= ((not B4798) and B4788) or (B4798 and (not B4788));
B4798 <= B4806 and B4805;
B4799 <= B4804 and B4788;
B4800 <= B4809 and B4808;
B4801 <= B4807 and B4788;
B4802 <= B4810 or B4787;
B4803 <= (B4788 and B4800) or ((not B4788) and (not B4800));
B4804 <= (not B4813) or (not B4814);
B4805 <= ((not B4789) and B4796) or (B4789 and (not B4796));
B4806 <= B4815 and B4808;
B4807 <= (not B4817) or (not B4816);
B4808 <= B4789 or B4790;
B4809 <= B4789 or B4796;
B4810 <= B4788 and B4800;
B4811 <= (not B4787) or (not B4788);
B4812 <= B4796 and B4811;
B4813 <= (not B4812) and (not B4796);
B4814 <= B4796 or B4811;
B4815 <= (not B4789) or (not B4790);
B4816 <= B4796 or B4811;
B4817 <= (not B4796) and (not B4818);
B4818 <= B4796 and B4811;
B4819 <= B7501;
B4820 <= B7534;
B4821 <= B7567;
B4822 <= B7600;
B4823 <= B7633;
B4824 <= B4830 and B4829;
B4825 <= B4832 or B4831;
B4826 <= B4834 or B4833;
B4827 <= B4829 and B4835;
B4828 <= B4829 and B4836;
B4829 <= ((not B4819) and B4820) or (B4819 and (not B4820));
B4830 <= ((not B4831) and B4821) or (B4831 and (not B4821));
B4831 <= B4839 and B4838;
B4832 <= B4837 and B4821;
B4833 <= B4842 and B4841;
B4834 <= B4840 and B4821;
B4835 <= B4843 or B4820;
B4836 <= (B4821 and B4833) or ((not B4821) and (not B4833));
B4837 <= (not B4846) or (not B4847);
B4838 <= ((not B4822) and B4829) or (B4822 and (not B4829));
B4839 <= B4848 and B4841;
B4840 <= (not B4850) or (not B4849);
B4841 <= B4822 or B4823;
B4842 <= B4822 or B4829;
B4843 <= B4821 and B4833;
B4844 <= (not B4820) or (not B4821);
B4845 <= B4829 and B4844;
B4846 <= (not B4845) and (not B4829);
B4847 <= B4829 or B4844;
B4848 <= (not B4822) or (not B4823);
B4849 <= B4829 or B4844;
B4850 <= (not B4829) and (not B4851);
B4851 <= B4829 and B4844;
B4852 <= B7666;
B4853 <= B7699;
B4854 <= B7732;
B4855 <= B7765;
B4856 <= B7798;
B4857 <= B4863 and B4862;
B4858 <= B4865 or B4864;
B4859 <= B4867 or B4866;
B4860 <= B4862 and B4868;
B4861 <= B4862 and B4869;
B4862 <= ((not B4852) and B4853) or (B4852 and (not B4853));
B4863 <= ((not B4864) and B4854) or (B4864 and (not B4854));
B4864 <= B4872 and B4871;
B4865 <= B4870 and B4854;
B4866 <= B4875 and B4874;
B4867 <= B4873 and B4854;
B4868 <= B4876 or B4853;
B4869 <= (B4854 and B4866) or ((not B4854) and (not B4866));
B4870 <= (not B4879) or (not B4880);
B4871 <= ((not B4855) and B4862) or (B4855 and (not B4862));
B4872 <= B4881 and B4874;
B4873 <= (not B4883) or (not B4882);
B4874 <= B4855 or B4856;
B4875 <= B4855 or B4862;
B4876 <= B4854 and B4866;
B4877 <= (not B4853) or (not B4854);
B4878 <= B4862 and B4877;
B4879 <= (not B4878) and (not B4862);
B4880 <= B4862 or B4877;
B4881 <= (not B4855) or (not B4856);
B4882 <= B4862 or B4877;
B4883 <= (not B4862) and (not B4884);
B4884 <= B4862 and B4877;
B4885 <= B7831;
B4886 <= B7864;
B4887 <= B7897;
B4888 <= B7930;
B4889 <= B7963;
B4890 <= B4896 and B4895;
B4891 <= B4898 or B4897;
B4892 <= B4900 or B4899;
B4893 <= B4895 and B4901;
B4894 <= B4895 and B4902;
B4895 <= ((not B4885) and B4886) or (B4885 and (not B4886));
B4896 <= ((not B4897) and B4887) or (B4897 and (not B4887));
B4897 <= B4905 and B4904;
B4898 <= B4903 and B4887;
B4899 <= B4908 and B4907;
B4900 <= B4906 and B4887;
B4901 <= B4909 or B4886;
B4902 <= (B4887 and B4899) or ((not B4887) and (not B4899));
B4903 <= (not B4912) or (not B4913);
B4904 <= ((not B4888) and B4895) or (B4888 and (not B4895));
B4905 <= B4914 and B4907;
B4906 <= (not B4916) or (not B4915);
B4907 <= B4888 or B4889;
B4908 <= B4888 or B4895;
B4909 <= B4887 and B4899;
B4910 <= (not B4886) or (not B4887);
B4911 <= B4895 and B4910;
B4912 <= (not B4911) and (not B4895);
B4913 <= B4895 or B4910;
B4914 <= (not B4888) or (not B4889);
B4915 <= B4895 or B4910;
B4916 <= (not B4895) and (not B4917);
B4917 <= B4895 and B4910;
B4918 <= B7996;
B4919 <= B8029;
B4920 <= B8062;
B4921 <= B8095;
B4922 <= B8128;
B4923 <= B4929 and B4928;
B4924 <= B4931 or B4930;
B4925 <= B4933 or B4932;
B4926 <= B4928 and B4934;
B4927 <= B4928 and B4935;
B4928 <= ((not B4918) and B4919) or (B4918 and (not B4919));
B4929 <= ((not B4930) and B4920) or (B4930 and (not B4920));
B4930 <= B4938 and B4937;
B4931 <= B4936 and B4920;
B4932 <= B4941 and B4940;
B4933 <= B4939 and B4920;
B4934 <= B4942 or B4919;
B4935 <= (B4920 and B4932) or ((not B4920) and (not B4932));
B4936 <= (not B4945) or (not B4946);
B4937 <= ((not B4921) and B4928) or (B4921 and (not B4928));
B4938 <= B4947 and B4940;
B4939 <= (not B4949) or (not B4948);
B4940 <= B4921 or B4922;
B4941 <= B4921 or B4928;
B4942 <= B4920 and B4932;
B4943 <= (not B4919) or (not B4920);
B4944 <= B4928 and B4943;
B4945 <= (not B4944) and (not B4928);
B4946 <= B4928 or B4943;
B4947 <= (not B4921) or (not B4922);
B4948 <= B4928 or B4943;
B4949 <= (not B4928) and (not B4950);
B4950 <= B4928 and B4943;
B4951 <= B8161;
B4952 <= B8194;
B4953 <= B8227;
B4954 <= B8260;
B4955 <= B8293;
B4956 <= B4962 and B4961;
B4957 <= B4964 or B4963;
B4958 <= B4966 or B4965;
B4959 <= B4961 and B4967;
B4960 <= B4961 and B4968;
B4961 <= ((not B4951) and B4952) or (B4951 and (not B4952));
B4962 <= ((not B4963) and B4953) or (B4963 and (not B4953));
B4963 <= B4971 and B4970;
B4964 <= B4969 and B4953;
B4965 <= B4974 and B4973;
B4966 <= B4972 and B4953;
B4967 <= B4975 or B4952;
B4968 <= (B4953 and B4965) or ((not B4953) and (not B4965));
B4969 <= (not B4978) or (not B4979);
B4970 <= ((not B4954) and B4961) or (B4954 and (not B4961));
B4971 <= B4980 and B4973;
B4972 <= (not B4982) or (not B4981);
B4973 <= B4954 or B4955;
B4974 <= B4954 or B4961;
B4975 <= B4953 and B4965;
B4976 <= (not B4952) or (not B4953);
B4977 <= B4961 and B4976;
B4978 <= (not B4977) and (not B4961);
B4979 <= B4961 or B4976;
B4980 <= (not B4954) or (not B4955);
B4981 <= B4961 or B4976;
B4982 <= (not B4961) and (not B4983);
B4983 <= B4961 and B4976;
B4984 <= B8326;
B4985 <= B8359;
B4986 <= B8392;
B4987 <= B8425;
B4988 <= B8458;
B4989 <= B4995 and B4994;
B4990 <= B4997 or B4996;
B4991 <= B4999 or B4998;
B4992 <= B4994 and B5000;
B4993 <= B4994 and B5001;
B4994 <= ((not B4984) and B4985) or (B4984 and (not B4985));
B4995 <= ((not B4996) and B4986) or (B4996 and (not B4986));
B4996 <= B5004 and B5003;
B4997 <= B5002 and B4986;
B4998 <= B5007 and B5006;
B4999 <= B5005 and B4986;
B5000 <= B5008 or B4985;
B5001 <= (B4986 and B4998) or ((not B4986) and (not B4998));
B5002 <= (not B5011) or (not B5012);
B5003 <= ((not B4987) and B4994) or (B4987 and (not B4994));
B5004 <= B5013 and B5006;
B5005 <= (not B5015) or (not B5014);
B5006 <= B4987 or B4988;
B5007 <= B4987 or B4994;
B5008 <= B4986 and B4998;
B5009 <= (not B4985) or (not B4986);
B5010 <= B4994 and B5009;
B5011 <= (not B5010) and (not B4994);
B5012 <= B4994 or B5009;
B5013 <= (not B4987) or (not B4988);
B5014 <= B4994 or B5009;
B5015 <= (not B4994) and (not B5016);
B5016 <= B4994 and B5009;
B5017 <= B8491;
B5018 <= B8524;
B5019 <= B8557;
B5020 <= B8590;
B5021 <= B8623;
B5022 <= B5028 and B5027;
B5023 <= B5030 or B5029;
B5024 <= B5032 or B5031;
B5025 <= B5027 and B5033;
B5026 <= B5027 and B5034;
B5027 <= ((not B5017) and B5018) or (B5017 and (not B5018));
B5028 <= ((not B5029) and B5019) or (B5029 and (not B5019));
B5029 <= B5037 and B5036;
B5030 <= B5035 and B5019;
B5031 <= B5040 and B5039;
B5032 <= B5038 and B5019;
B5033 <= B5041 or B5018;
B5034 <= (B5019 and B5031) or ((not B5019) and (not B5031));
B5035 <= (not B5044) or (not B5045);
B5036 <= ((not B5020) and B5027) or (B5020 and (not B5027));
B5037 <= B5046 and B5039;
B5038 <= (not B5048) or (not B5047);
B5039 <= B5020 or B5021;
B5040 <= B5020 or B5027;
B5041 <= B5019 and B5031;
B5042 <= (not B5018) or (not B5019);
B5043 <= B5027 and B5042;
B5044 <= (not B5043) and (not B5027);
B5045 <= B5027 or B5042;
B5046 <= (not B5020) or (not B5021);
B5047 <= B5027 or B5042;
B5048 <= (not B5027) and (not B5049);
B5049 <= B5027 and B5042;
B5050 <= B8656;
B5051 <= B8689;
B5052 <= B8722;
B5053 <= B8755;
B5054 <= B8788;
B5055 <= B5061 and B5060;
B5056 <= B5063 or B5062;
B5057 <= B5065 or B5064;
B5058 <= B5060 and B5066;
B5059 <= B5060 and B5067;
B5060 <= ((not B5050) and B5051) or (B5050 and (not B5051));
B5061 <= ((not B5062) and B5052) or (B5062 and (not B5052));
B5062 <= B5070 and B5069;
B5063 <= B5068 and B5052;
B5064 <= B5073 and B5072;
B5065 <= B5071 and B5052;
B5066 <= B5074 or B5051;
B5067 <= (B5052 and B5064) or ((not B5052) and (not B5064));
B5068 <= (not B5077) or (not B5078);
B5069 <= ((not B5053) and B5060) or (B5053 and (not B5060));
B5070 <= B5079 and B5072;
B5071 <= (not B5081) or (not B5080);
B5072 <= B5053 or B5054;
B5073 <= B5053 or B5060;
B5074 <= B5052 and B5064;
B5075 <= (not B5051) or (not B5052);
B5076 <= B5060 and B5075;
B5077 <= (not B5076) and (not B5060);
B5078 <= B5060 or B5075;
B5079 <= (not B5053) or (not B5054);
B5080 <= B5060 or B5075;
B5081 <= (not B5060) and (not B5082);
B5082 <= B5060 and B5075;
B5083 <= B8821;
B5084 <= B8854;
B5085 <= B8887;
B5086 <= B8920;
B5087 <= B8953;
B5088 <= B5094 and B5093;
B5089 <= B5096 or B5095;
B5090 <= B5098 or B5097;
B5091 <= B5093 and B5099;
B5092 <= B5093 and B5100;
B5093 <= ((not B5083) and B5084) or (B5083 and (not B5084));
B5094 <= ((not B5095) and B5085) or (B5095 and (not B5085));
B5095 <= B5103 and B5102;
B5096 <= B5101 and B5085;
B5097 <= B5106 and B5105;
B5098 <= B5104 and B5085;
B5099 <= B5107 or B5084;
B5100 <= (B5085 and B5097) or ((not B5085) and (not B5097));
B5101 <= (not B5110) or (not B5111);
B5102 <= ((not B5086) and B5093) or (B5086 and (not B5093));
B5103 <= B5112 and B5105;
B5104 <= (not B5114) or (not B5113);
B5105 <= B5086 or B5087;
B5106 <= B5086 or B5093;
B5107 <= B5085 and B5097;
B5108 <= (not B5084) or (not B5085);
B5109 <= B5093 and B5108;
B5110 <= (not B5109) and (not B5093);
B5111 <= B5093 or B5108;
B5112 <= (not B5086) or (not B5087);
B5113 <= B5093 or B5108;
B5114 <= (not B5093) and (not B5115);
B5115 <= B5093 and B5108;
B5116 <= B8986;
B5117 <= B9019;
B5118 <= B9052;
B5119 <= B9085;
B5120 <= B9118;
B5121 <= B5127 and B5126;
B5122 <= B5129 or B5128;
B5123 <= B5131 or B5130;
B5124 <= B5126 and B5132;
B5125 <= B5126 and B5133;
B5126 <= ((not B5116) and B5117) or (B5116 and (not B5117));
B5127 <= ((not B5128) and B5118) or (B5128 and (not B5118));
B5128 <= B5136 and B5135;
B5129 <= B5134 and B5118;
B5130 <= B5139 and B5138;
B5131 <= B5137 and B5118;
B5132 <= B5140 or B5117;
B5133 <= (B5118 and B5130) or ((not B5118) and (not B5130));
B5134 <= (not B5143) or (not B5144);
B5135 <= ((not B5119) and B5126) or (B5119 and (not B5126));
B5136 <= B5145 and B5138;
B5137 <= (not B5147) or (not B5146);
B5138 <= B5119 or B5120;
B5139 <= B5119 or B5126;
B5140 <= B5118 and B5130;
B5141 <= (not B5117) or (not B5118);
B5142 <= B5126 and B5141;
B5143 <= (not B5142) and (not B5126);
B5144 <= B5126 or B5141;
B5145 <= (not B5119) or (not B5120);
B5146 <= B5126 or B5141;
B5147 <= (not B5126) and (not B5148);
B5148 <= B5126 and B5141;
B5149 <= B9151;
B5150 <= B9184;
B5151 <= B9217;
B5152 <= B9250;
B5153 <= B9283;
B5154 <= B5160 and B5159;
B5155 <= B5162 or B5161;
B5156 <= B5164 or B5163;
B5157 <= B5159 and B5165;
B5158 <= B5159 and B5166;
B5159 <= ((not B5149) and B5150) or (B5149 and (not B5150));
B5160 <= ((not B5161) and B5151) or (B5161 and (not B5151));
B5161 <= B5169 and B5168;
B5162 <= B5167 and B5151;
B5163 <= B5172 and B5171;
B5164 <= B5170 and B5151;
B5165 <= B5173 or B5150;
B5166 <= (B5151 and B5163) or ((not B5151) and (not B5163));
B5167 <= (not B5176) or (not B5177);
B5168 <= ((not B5152) and B5159) or (B5152 and (not B5159));
B5169 <= B5178 and B5171;
B5170 <= (not B5180) or (not B5179);
B5171 <= B5152 or B5153;
B5172 <= B5152 or B5159;
B5173 <= B5151 and B5163;
B5174 <= (not B5150) or (not B5151);
B5175 <= B5159 and B5174;
B5176 <= (not B5175) and (not B5159);
B5177 <= B5159 or B5174;
B5178 <= (not B5152) or (not B5153);
B5179 <= B5159 or B5174;
B5180 <= (not B5159) and (not B5181);
B5181 <= B5159 and B5174;
A6963 <= A6941 and A6956;
A6962 <= (not A6941) and (not A6963);
A6961 <= A6941 or A6956;
A6960 <= (not A6934) or (not A6935);
A6959 <= A6941 or A6956;
A6958 <= (not A6957) and (not A6941);
A6957 <= A6941 and A6956;
A6956 <= (not A6932) or (not A6933);
A6955 <= A6933 and A6945;
A6954 <= A6934 or A6941;
A6953 <= A6934 or A6935;
A6952 <= (not A6962) or (not A6961);
A6951 <= A6960 and A6953;
A6950 <= ((not A6934) and A6941) or (A6934 and (not A6941));
A6949 <= (not A6958) or (not A6959);
A6948 <= (A6933 and A6945) or ((not A6933) and (not A6945));
A6947 <= A6955 or A6932;
A6946 <= A6952 and A6933;
A6945 <= A6954 and A6953;
A6944 <= A6949 and A6933;
A6943 <= A6951 and A6950;
A6942 <= ((not A6943) and A6933) or (A6943 and (not A6933));
A6941 <= ((not A6931) and A6932) or (A6931 and (not A6932));
A6940 <= A6941 and A6948;
A6939 <= A6941 and A6947;
A6938 <= A6946 or A6945;
A6937 <= A6944 or A6943;
A6936 <= A6942 and A6941;
A6935 <= B1066;
A6934 <= B1095;
A6933 <= B1128;
A6932 <= B1161;
A6931 <= B1194;
A6964 <= B1227;
A6965 <= B1260;
A6966 <= B1293;
A6967 <= B1326;
A6968 <= B1359;
A6969 <= A6975 and A6974;
A6970 <= A6977 or A6976;
A6971 <= A6979 or A6978;
A6972 <= A6974 and A6980;
A6973 <= A6974 and A6981;
A6974 <= ((not A6964) and A6965) or (A6964 and (not A6965));
A6975 <= ((not A6976) and A6966) or (A6976 and (not A6966));
A6976 <= A6984 and A6983;
A6977 <= A6982 and A6966;
A6978 <= A6987 and A6986;
A6979 <= A6985 and A6966;
A6980 <= A6988 or A6965;
A6981 <= (A6966 and A6978) or ((not A6966) and (not A6978));
A6982 <= (not A6991) or (not A6992);
A6983 <= ((not A6967) and A6974) or (A6967 and (not A6974));
A6984 <= A6993 and A6986;
A6985 <= (not A6995) or (not A6994);
A6986 <= A6967 or A6968;
A6987 <= A6967 or A6974;
A6988 <= A6966 and A6978;
A6989 <= (not A6965) or (not A6966);
A6990 <= A6974 and A6989;
A6991 <= (not A6990) and (not A6974);
A6992 <= A6974 or A6989;
A6993 <= (not A6967) or (not A6968);
A6994 <= A6974 or A6989;
A6995 <= (not A6974) and (not A6996);
A6996 <= A6974 and A6989;
A6997 <= B1392;
A6998 <= B1425;
A6999 <= B1458;
A7000 <= B1491;
A7001 <= B1524;
A7002 <= A7008 and A7007;
A7003 <= A7010 or A7009;
A7004 <= A7012 or A7011;
A7005 <= A7007 and A7013;
A7006 <= A7007 and A7014;
A7007 <= ((not A6997) and A6998) or (A6997 and (not A6998));
A7008 <= ((not A7009) and A6999) or (A7009 and (not A6999));
A7009 <= A7017 and A7016;
A7010 <= A7015 and A6999;
A7011 <= A7020 and A7019;
A7012 <= A7018 and A6999;
A7013 <= A7021 or A6998;
A7014 <= (A6999 and A7011) or ((not A6999) and (not A7011));
A7015 <= (not A7024) or (not A7025);
A7016 <= ((not A7000) and A7007) or (A7000 and (not A7007));
A7017 <= A7026 and A7019;
A7018 <= (not A7028) or (not A7027);
A7019 <= A7000 or A7001;
A7020 <= A7000 or A7007;
A7021 <= A6999 and A7011;
A7022 <= (not A6998) or (not A6999);
A7023 <= A7007 and A7022;
A7024 <= (not A7023) and (not A7007);
A7025 <= A7007 or A7022;
A7026 <= (not A7000) or (not A7001);
A7027 <= A7007 or A7022;
A7028 <= (not A7007) and (not A7029);
A7029 <= A7007 and A7022;
A7030 <= B1557;
A7031 <= B1590;
A7032 <= B1623;
A7033 <= B1656;
A7034 <= B1689;
A7035 <= A7041 and A7040;
A7036 <= A7043 or A7042;
A7037 <= A7045 or A7044;
A7038 <= A7040 and A7046;
A7039 <= A7040 and A7047;
A7040 <= ((not A7030) and A7031) or (A7030 and (not A7031));
A7041 <= ((not A7042) and A7032) or (A7042 and (not A7032));
A7042 <= A7050 and A7049;
A7043 <= A7048 and A7032;
A7044 <= A7053 and A7052;
A7045 <= A7051 and A7032;
A7046 <= A7054 or A7031;
A7047 <= (A7032 and A7044) or ((not A7032) and (not A7044));
A7048 <= (not A7057) or (not A7058);
A7049 <= ((not A7033) and A7040) or (A7033 and (not A7040));
A7050 <= A7059 and A7052;
A7051 <= (not A7061) or (not A7060);
A7052 <= A7033 or A7034;
A7053 <= A7033 or A7040;
A7054 <= A7032 and A7044;
A7055 <= (not A7031) or (not A7032);
A7056 <= A7040 and A7055;
A7057 <= (not A7056) and (not A7040);
A7058 <= A7040 or A7055;
A7059 <= (not A7033) or (not A7034);
A7060 <= A7040 or A7055;
A7061 <= (not A7040) and (not A7062);
A7062 <= A7040 and A7055;
A7063 <= B1722;
A7064 <= B1755;
A7065 <= B1788;
A7066 <= B1821;
A7067 <= B1854;
A7068 <= A7074 and A7073;
A7069 <= A7076 or A7075;
A7070 <= A7078 or A7077;
A7071 <= A7073 and A7079;
A7072 <= A7073 and A7080;
A7073 <= ((not A7063) and A7064) or (A7063 and (not A7064));
A7074 <= ((not A7075) and A7065) or (A7075 and (not A7065));
A7075 <= A7083 and A7082;
A7076 <= A7081 and A7065;
A7077 <= A7086 and A7085;
A7078 <= A7084 and A7065;
A7079 <= A7087 or A7064;
A7080 <= (A7065 and A7077) or ((not A7065) and (not A7077));
A7081 <= (not A7090) or (not A7091);
A7082 <= ((not A7066) and A7073) or (A7066 and (not A7073));
A7083 <= A7092 and A7085;
A7084 <= (not A7094) or (not A7093);
A7085 <= A7066 or A7067;
A7086 <= A7066 or A7073;
A7087 <= A7065 and A7077;
A7088 <= (not A7064) or (not A7065);
A7089 <= A7073 and A7088;
A7090 <= (not A7089) and (not A7073);
A7091 <= A7073 or A7088;
A7092 <= (not A7066) or (not A7067);
A7093 <= A7073 or A7088;
A7094 <= (not A7073) and (not A7095);
A7095 <= A7073 and A7088;
A7096 <= B1887;
A7097 <= B1920;
A7098 <= B1953;
A7099 <= B1986;
A7100 <= B2019;
A7101 <= A7107 and A7106;
A7102 <= A7109 or A7108;
A7103 <= A7111 or A7110;
A7104 <= A7106 and A7112;
A7105 <= A7106 and A7113;
A7106 <= ((not A7096) and A7097) or (A7096 and (not A7097));
A7107 <= ((not A7108) and A7098) or (A7108 and (not A7098));
A7108 <= A7116 and A7115;
A7109 <= A7114 and A7098;
A7110 <= A7119 and A7118;
A7111 <= A7117 and A7098;
A7112 <= A7120 or A7097;
A7113 <= (A7098 and A7110) or ((not A7098) and (not A7110));
A7114 <= (not A7123) or (not A7124);
A7115 <= ((not A7099) and A7106) or (A7099 and (not A7106));
A7116 <= A7125 and A7118;
A7117 <= (not A7127) or (not A7126);
A7118 <= A7099 or A7100;
A7119 <= A7099 or A7106;
A7120 <= A7098 and A7110;
A7121 <= (not A7097) or (not A7098);
A7122 <= A7106 and A7121;
A7123 <= (not A7122) and (not A7106);
A7124 <= A7106 or A7121;
A7125 <= (not A7099) or (not A7100);
A7126 <= A7106 or A7121;
A7127 <= (not A7106) and (not A7128);
A7128 <= A7106 and A7121;
A7129 <= B2052;
A7130 <= B2085;
A7131 <= B2118;
A7132 <= B2151;
A7133 <= B2184;
A7134 <= A7140 and A7139;
A7135 <= A7142 or A7141;
A7136 <= A7144 or A7143;
A7137 <= A7139 and A7145;
A7138 <= A7139 and A7146;
A7139 <= ((not A7129) and A7130) or (A7129 and (not A7130));
A7140 <= ((not A7141) and A7131) or (A7141 and (not A7131));
A7141 <= A7149 and A7148;
A7142 <= A7147 and A7131;
A7143 <= A7152 and A7151;
A7144 <= A7150 and A7131;
A7145 <= A7153 or A7130;
A7146 <= (A7131 and A7143) or ((not A7131) and (not A7143));
A7147 <= (not A7156) or (not A7157);
A7148 <= ((not A7132) and A7139) or (A7132 and (not A7139));
A7149 <= A7158 and A7151;
A7150 <= (not A7160) or (not A7159);
A7151 <= A7132 or A7133;
A7152 <= A7132 or A7139;
A7153 <= A7131 and A7143;
A7154 <= (not A7130) or (not A7131);
A7155 <= A7139 and A7154;
A7156 <= (not A7155) and (not A7139);
A7157 <= A7139 or A7154;
A7158 <= (not A7132) or (not A7133);
A7159 <= A7139 or A7154;
A7160 <= (not A7139) and (not A7161);
A7161 <= A7139 and A7154;
A7162 <= B2217;
A7163 <= B2250;
A7164 <= B2283;
A7165 <= B2316;
A7166 <= B2349;
A7167 <= A7173 and A7172;
A7168 <= A7175 or A7174;
A7169 <= A7177 or A7176;
A7170 <= A7172 and A7178;
A7171 <= A7172 and A7179;
A7172 <= ((not A7162) and A7163) or (A7162 and (not A7163));
A7173 <= ((not A7174) and A7164) or (A7174 and (not A7164));
A7174 <= A7182 and A7181;
A7175 <= A7180 and A7164;
A7176 <= A7185 and A7184;
A7177 <= A7183 and A7164;
A7178 <= A7186 or A7163;
A7179 <= (A7164 and A7176) or ((not A7164) and (not A7176));
A7180 <= (not A7189) or (not A7190);
A7181 <= ((not A7165) and A7172) or (A7165 and (not A7172));
A7182 <= A7191 and A7184;
A7183 <= (not A7193) or (not A7192);
A7184 <= A7165 or A7166;
A7185 <= A7165 or A7172;
A7186 <= A7164 and A7176;
A7187 <= (not A7163) or (not A7164);
A7188 <= A7172 and A7187;
A7189 <= (not A7188) and (not A7172);
A7190 <= A7172 or A7187;
A7191 <= (not A7165) or (not A7166);
A7192 <= A7172 or A7187;
A7193 <= (not A7172) and (not A7194);
A7194 <= A7172 and A7187;
A7195 <= B2382;
A7196 <= B2415;
A7197 <= B2448;
A7198 <= B2481;
A7199 <= B2514;
A7200 <= A7206 and A7205;
A7201 <= A7208 or A7207;
A7202 <= A7210 or A7209;
A7203 <= A7205 and A7211;
A7204 <= A7205 and A7212;
A7205 <= ((not A7195) and A7196) or (A7195 and (not A7196));
A7206 <= ((not A7207) and A7197) or (A7207 and (not A7197));
A7207 <= A7215 and A7214;
A7208 <= A7213 and A7197;
A7209 <= A7218 and A7217;
A7210 <= A7216 and A7197;
A7211 <= A7219 or A7196;
A7212 <= (A7197 and A7209) or ((not A7197) and (not A7209));
A7213 <= (not A7222) or (not A7223);
A7214 <= ((not A7198) and A7205) or (A7198 and (not A7205));
A7215 <= A7224 and A7217;
A7216 <= (not A7226) or (not A7225);
A7217 <= A7198 or A7199;
A7218 <= A7198 or A7205;
A7219 <= A7197 and A7209;
A7220 <= (not A7196) or (not A7197);
A7221 <= A7205 and A7220;
A7222 <= (not A7221) and (not A7205);
A7223 <= A7205 or A7220;
A7224 <= (not A7198) or (not A7199);
A7225 <= A7205 or A7220;
A7226 <= (not A7205) and (not A7227);
A7227 <= A7205 and A7220;
A7228 <= B2547;
A7229 <= B2580;
A7230 <= B2613;
A7231 <= B2646;
A7232 <= B2679;
A7233 <= A7239 and A7238;
A7234 <= A7241 or A7240;
A7235 <= A7243 or A7242;
A7236 <= A7238 and A7244;
A7237 <= A7238 and A7245;
A7238 <= ((not A7228) and A7229) or (A7228 and (not A7229));
A7239 <= ((not A7240) and A7230) or (A7240 and (not A7230));
A7240 <= A7248 and A7247;
A7241 <= A7246 and A7230;
A7242 <= A7251 and A7250;
A7243 <= A7249 and A7230;
A7244 <= A7252 or A7229;
A7245 <= (A7230 and A7242) or ((not A7230) and (not A7242));
A7246 <= (not A7255) or (not A7256);
A7247 <= ((not A7231) and A7238) or (A7231 and (not A7238));
A7248 <= A7257 and A7250;
A7249 <= (not A7259) or (not A7258);
A7250 <= A7231 or A7232;
A7251 <= A7231 or A7238;
A7252 <= A7230 and A7242;
A7253 <= (not A7229) or (not A7230);
A7254 <= A7238 and A7253;
A7255 <= (not A7254) and (not A7238);
A7256 <= A7238 or A7253;
A7257 <= (not A7231) or (not A7232);
A7258 <= A7238 or A7253;
A7259 <= (not A7238) and (not A7260);
A7260 <= A7238 and A7253;
A7261 <= B2712;
A7262 <= B2745;
A7263 <= B2778;
A7264 <= B2811;
A7265 <= B2844;
A7266 <= A7272 and A7271;
A7267 <= A7274 or A7273;
A7268 <= A7276 or A7275;
A7269 <= A7271 and A7277;
A7270 <= A7271 and A7278;
A7271 <= ((not A7261) and A7262) or (A7261 and (not A7262));
A7272 <= ((not A7273) and A7263) or (A7273 and (not A7263));
A7273 <= A7281 and A7280;
A7274 <= A7279 and A7263;
A7275 <= A7284 and A7283;
A7276 <= A7282 and A7263;
A7277 <= A7285 or A7262;
A7278 <= (A7263 and A7275) or ((not A7263) and (not A7275));
A7279 <= (not A7288) or (not A7289);
A7280 <= ((not A7264) and A7271) or (A7264 and (not A7271));
A7281 <= A7290 and A7283;
A7282 <= (not A7292) or (not A7291);
A7283 <= A7264 or A7265;
A7284 <= A7264 or A7271;
A7285 <= A7263 and A7275;
A7286 <= (not A7262) or (not A7263);
A7287 <= A7271 and A7286;
A7288 <= (not A7287) and (not A7271);
A7289 <= A7271 or A7286;
A7290 <= (not A7264) or (not A7265);
A7291 <= A7271 or A7286;
A7292 <= (not A7271) and (not A7293);
A7293 <= A7271 and A7286;
A7294 <= B2877;
A7295 <= B2910;
A7296 <= B2943;
A7297 <= B2976;
A7298 <= B3009;
A7299 <= A7305 and A7304;
A7300 <= A7307 or A7306;
A7301 <= A7309 or A7308;
A7302 <= A7304 and A7310;
A7303 <= A7304 and A7311;
A7304 <= ((not A7294) and A7295) or (A7294 and (not A7295));
A7305 <= ((not A7306) and A7296) or (A7306 and (not A7296));
A7306 <= A7314 and A7313;
A7307 <= A7312 and A7296;
A7308 <= A7317 and A7316;
A7309 <= A7315 and A7296;
A7310 <= A7318 or A7295;
A7311 <= (A7296 and A7308) or ((not A7296) and (not A7308));
A7312 <= (not A7321) or (not A7322);
A7313 <= ((not A7297) and A7304) or (A7297 and (not A7304));
A7314 <= A7323 and A7316;
A7315 <= (not A7325) or (not A7324);
A7316 <= A7297 or A7298;
A7317 <= A7297 or A7304;
A7318 <= A7296 and A7308;
A7319 <= (not A7295) or (not A7296);
A7320 <= A7304 and A7319;
A7321 <= (not A7320) and (not A7304);
A7322 <= A7304 or A7319;
A7323 <= (not A7297) or (not A7298);
A7324 <= A7304 or A7319;
A7325 <= (not A7304) and (not A7326);
A7326 <= A7304 and A7319;
A7327 <= B3042;
A7328 <= B3075;
A7329 <= B3108;
A7330 <= B3141;
A7331 <= B3174;
A7332 <= A7338 and A7337;
A7333 <= A7340 or A7339;
A7334 <= A7342 or A7341;
A7335 <= A7337 and A7343;
A7336 <= A7337 and A7344;
A7337 <= ((not A7327) and A7328) or (A7327 and (not A7328));
A7338 <= ((not A7339) and A7329) or (A7339 and (not A7329));
A7339 <= A7347 and A7346;
A7340 <= A7345 and A7329;
A7341 <= A7350 and A7349;
A7342 <= A7348 and A7329;
A7343 <= A7351 or A7328;
A7344 <= (A7329 and A7341) or ((not A7329) and (not A7341));
A7345 <= (not A7354) or (not A7355);
A7346 <= ((not A7330) and A7337) or (A7330 and (not A7337));
A7347 <= A7356 and A7349;
A7348 <= (not A7358) or (not A7357);
A7349 <= A7330 or A7331;
A7350 <= A7330 or A7337;
A7351 <= A7329 and A7341;
A7352 <= (not A7328) or (not A7329);
A7353 <= A7337 and A7352;
A7354 <= (not A7353) and (not A7337);
A7355 <= A7337 or A7352;
A7356 <= (not A7330) or (not A7331);
A7357 <= A7337 or A7352;
A7358 <= (not A7337) and (not A7359);
A7359 <= A7337 and A7352;
A7360 <= B3207;
A7361 <= B3240;
A7362 <= B3273;
A7363 <= B3306;
A7364 <= B3339;
A7365 <= A7371 and A7370;
A7366 <= A7373 or A7372;
A7367 <= A7375 or A7374;
A7368 <= A7370 and A7376;
A7369 <= A7370 and A7377;
A7370 <= ((not A7360) and A7361) or (A7360 and (not A7361));
A7371 <= ((not A7372) and A7362) or (A7372 and (not A7362));
A7372 <= A7380 and A7379;
A7373 <= A7378 and A7362;
A7374 <= A7383 and A7382;
A7375 <= A7381 and A7362;
A7376 <= A7384 or A7361;
A7377 <= (A7362 and A7374) or ((not A7362) and (not A7374));
A7378 <= (not A7387) or (not A7388);
A7379 <= ((not A7363) and A7370) or (A7363 and (not A7370));
A7380 <= A7389 and A7382;
A7381 <= (not A7391) or (not A7390);
A7382 <= A7363 or A7364;
A7383 <= A7363 or A7370;
A7384 <= A7362 and A7374;
A7385 <= (not A7361) or (not A7362);
A7386 <= A7370 and A7385;
A7387 <= (not A7386) and (not A7370);
A7388 <= A7370 or A7385;
A7389 <= (not A7363) or (not A7364);
A7390 <= A7370 or A7385;
A7391 <= (not A7370) and (not A7392);
A7392 <= A7370 and A7385;
A7393 <= B3372;
A7394 <= B3405;
A7395 <= B3438;
A7396 <= B3471;
A7397 <= B3504;
A7398 <= A7404 and A7403;
A7399 <= A7406 or A7405;
A7400 <= A7408 or A7407;
A7401 <= A7403 and A7409;
A7402 <= A7403 and A7410;
A7403 <= ((not A7393) and A7394) or (A7393 and (not A7394));
A7404 <= ((not A7405) and A7395) or (A7405 and (not A7395));
A7405 <= A7413 and A7412;
A7406 <= A7411 and A7395;
A7407 <= A7416 and A7415;
A7408 <= A7414 and A7395;
A7409 <= A7417 or A7394;
A7410 <= (A7395 and A7407) or ((not A7395) and (not A7407));
A7411 <= (not A7420) or (not A7421);
A7412 <= ((not A7396) and A7403) or (A7396 and (not A7403));
A7413 <= A7422 and A7415;
A7414 <= (not A7424) or (not A7423);
A7415 <= A7396 or A7397;
A7416 <= A7396 or A7403;
A7417 <= A7395 and A7407;
A7418 <= (not A7394) or (not A7395);
A7419 <= A7403 and A7418;
A7420 <= (not A7419) and (not A7403);
A7421 <= A7403 or A7418;
A7422 <= (not A7396) or (not A7397);
A7423 <= A7403 or A7418;
A7424 <= (not A7403) and (not A7425);
A7425 <= A7403 and A7418;
A7426 <= B3537;
A7427 <= B3570;
A7428 <= B3603;
A7429 <= B3636;
A7430 <= B3669;
A7431 <= A7437 and A7436;
A7432 <= A7439 or A7438;
A7433 <= A7441 or A7440;
A7434 <= A7436 and A7442;
A7435 <= A7436 and A7443;
A7436 <= ((not A7426) and A7427) or (A7426 and (not A7427));
A7437 <= ((not A7438) and A7428) or (A7438 and (not A7428));
A7438 <= A7446 and A7445;
A7439 <= A7444 and A7428;
A7440 <= A7449 and A7448;
A7441 <= A7447 and A7428;
A7442 <= A7450 or A7427;
A7443 <= (A7428 and A7440) or ((not A7428) and (not A7440));
A7444 <= (not A7453) or (not A7454);
A7445 <= ((not A7429) and A7436) or (A7429 and (not A7436));
A7446 <= A7455 and A7448;
A7447 <= (not A7457) or (not A7456);
A7448 <= A7429 or A7430;
A7449 <= A7429 or A7436;
A7450 <= A7428 and A7440;
A7451 <= (not A7427) or (not A7428);
A7452 <= A7436 and A7451;
A7453 <= (not A7452) and (not A7436);
A7454 <= A7436 or A7451;
A7455 <= (not A7429) or (not A7430);
A7456 <= A7436 or A7451;
A7457 <= (not A7436) and (not A7458);
A7458 <= A7436 and A7451;
A7459 <= B3702;
A7460 <= B3735;
A7461 <= B3768;
A7462 <= B3801;
A7463 <= B3834;
A7464 <= A7470 and A7469;
A7465 <= A7472 or A7471;
A7466 <= A7474 or A7473;
A7467 <= A7469 and A7475;
A7468 <= A7469 and A7476;
A7469 <= ((not A7459) and A7460) or (A7459 and (not A7460));
A7470 <= ((not A7471) and A7461) or (A7471 and (not A7461));
A7471 <= A7479 and A7478;
A7472 <= A7477 and A7461;
A7473 <= A7482 and A7481;
A7474 <= A7480 and A7461;
A7475 <= A7483 or A7460;
A7476 <= (A7461 and A7473) or ((not A7461) and (not A7473));
A7477 <= (not A7486) or (not A7487);
A7478 <= ((not A7462) and A7469) or (A7462 and (not A7469));
A7479 <= A7488 and A7481;
A7480 <= (not A7490) or (not A7489);
A7481 <= A7462 or A7463;
A7482 <= A7462 or A7469;
A7483 <= A7461 and A7473;
A7484 <= (not A7460) or (not A7461);
A7485 <= A7469 and A7484;
A7486 <= (not A7485) and (not A7469);
A7487 <= A7469 or A7484;
A7488 <= (not A7462) or (not A7463);
A7489 <= A7469 or A7484;
A7490 <= (not A7469) and (not A7491);
A7491 <= A7469 and A7484;
A7492 <= B3867;
A7493 <= B3900;
A7494 <= B3933;
A7495 <= B3966;
A7496 <= B3999;
A7497 <= A7503 and A7502;
A7498 <= A7505 or A7504;
A7499 <= A7507 or A7506;
A7500 <= A7502 and A7508;
A7501 <= A7502 and A7509;
A7502 <= ((not A7492) and A7493) or (A7492 and (not A7493));
A7503 <= ((not A7504) and A7494) or (A7504 and (not A7494));
A7504 <= A7512 and A7511;
A7505 <= A7510 and A7494;
A7506 <= A7515 and A7514;
A7507 <= A7513 and A7494;
A7508 <= A7516 or A7493;
A7509 <= (A7494 and A7506) or ((not A7494) and (not A7506));
A7510 <= (not A7519) or (not A7520);
A7511 <= ((not A7495) and A7502) or (A7495 and (not A7502));
A7512 <= A7521 and A7514;
A7513 <= (not A7523) or (not A7522);
A7514 <= A7495 or A7496;
A7515 <= A7495 or A7502;
A7516 <= A7494 and A7506;
A7517 <= (not A7493) or (not A7494);
A7518 <= A7502 and A7517;
A7519 <= (not A7518) and (not A7502);
A7520 <= A7502 or A7517;
A7521 <= (not A7495) or (not A7496);
A7522 <= A7502 or A7517;
A7523 <= (not A7502) and (not A7524);
A7524 <= A7502 and A7517;
A7525 <= B4032;
A7526 <= B4065;
A7527 <= B4098;
A7528 <= B4131;
A7529 <= B4164;
A7530 <= A7536 and A7535;
A7531 <= A7538 or A7537;
A7532 <= A7540 or A7539;
A7533 <= A7535 and A7541;
A7534 <= A7535 and A7542;
A7535 <= ((not A7525) and A7526) or (A7525 and (not A7526));
A7536 <= ((not A7537) and A7527) or (A7537 and (not A7527));
A7537 <= A7545 and A7544;
A7538 <= A7543 and A7527;
A7539 <= A7548 and A7547;
A7540 <= A7546 and A7527;
A7541 <= A7549 or A7526;
A7542 <= (A7527 and A7539) or ((not A7527) and (not A7539));
A7543 <= (not A7552) or (not A7553);
A7544 <= ((not A7528) and A7535) or (A7528 and (not A7535));
A7545 <= A7554 and A7547;
A7546 <= (not A7556) or (not A7555);
A7547 <= A7528 or A7529;
A7548 <= A7528 or A7535;
A7549 <= A7527 and A7539;
A7550 <= (not A7526) or (not A7527);
A7551 <= A7535 and A7550;
A7552 <= (not A7551) and (not A7535);
A7553 <= A7535 or A7550;
A7554 <= (not A7528) or (not A7529);
A7555 <= A7535 or A7550;
A7556 <= (not A7535) and (not A7557);
A7557 <= A7535 and A7550;
A7558 <= B4197;
A7559 <= B4230;
A7560 <= B4263;
A7561 <= B4296;
A7562 <= B4329;
A7563 <= A7569 and A7568;
A7564 <= A7571 or A7570;
A7565 <= A7573 or A7572;
A7566 <= A7568 and A7574;
A7567 <= A7568 and A7575;
A7568 <= ((not A7558) and A7559) or (A7558 and (not A7559));
A7569 <= ((not A7570) and A7560) or (A7570 and (not A7560));
A7570 <= A7578 and A7577;
A7571 <= A7576 and A7560;
A7572 <= A7581 and A7580;
A7573 <= A7579 and A7560;
A7574 <= A7582 or A7559;
A7575 <= (A7560 and A7572) or ((not A7560) and (not A7572));
A7576 <= (not A7585) or (not A7586);
A7577 <= ((not A7561) and A7568) or (A7561 and (not A7568));
A7578 <= A7587 and A7580;
A7579 <= (not A7589) or (not A7588);
A7580 <= A7561 or A7562;
A7581 <= A7561 or A7568;
A7582 <= A7560 and A7572;
A7583 <= (not A7559) or (not A7560);
A7584 <= A7568 and A7583;
A7585 <= (not A7584) and (not A7568);
A7586 <= A7568 or A7583;
A7587 <= (not A7561) or (not A7562);
A7588 <= A7568 or A7583;
A7589 <= (not A7568) and (not A7590);
A7590 <= A7568 and A7583;
A7591 <= B4362;
A7592 <= B4395;
A7593 <= B4428;
A7594 <= B4461;
A7595 <= B4494;
A7596 <= A7602 and A7601;
A7597 <= A7604 or A7603;
A7598 <= A7606 or A7605;
A7599 <= A7601 and A7607;
A7600 <= A7601 and A7608;
A7601 <= ((not A7591) and A7592) or (A7591 and (not A7592));
A7602 <= ((not A7603) and A7593) or (A7603 and (not A7593));
A7603 <= A7611 and A7610;
A7604 <= A7609 and A7593;
A7605 <= A7614 and A7613;
A7606 <= A7612 and A7593;
A7607 <= A7615 or A7592;
A7608 <= (A7593 and A7605) or ((not A7593) and (not A7605));
A7609 <= (not A7618) or (not A7619);
A7610 <= ((not A7594) and A7601) or (A7594 and (not A7601));
A7611 <= A7620 and A7613;
A7612 <= (not A7622) or (not A7621);
A7613 <= A7594 or A7595;
A7614 <= A7594 or A7601;
A7615 <= A7593 and A7605;
A7616 <= (not A7592) or (not A7593);
A7617 <= A7601 and A7616;
A7618 <= (not A7617) and (not A7601);
A7619 <= A7601 or A7616;
A7620 <= (not A7594) or (not A7595);
A7621 <= A7601 or A7616;
A7622 <= (not A7601) and (not A7623);
A7623 <= A7601 and A7616;
A7624 <= B4527;
A7625 <= B4560;
A7626 <= B4593;
A7627 <= B4626;
A7628 <= B4659;
A7629 <= A7635 and A7634;
A7630 <= A7637 or A7636;
A7631 <= A7639 or A7638;
A7632 <= A7634 and A7640;
A7633 <= A7634 and A7641;
A7634 <= ((not A7624) and A7625) or (A7624 and (not A7625));
A7635 <= ((not A7636) and A7626) or (A7636 and (not A7626));
A7636 <= A7644 and A7643;
A7637 <= A7642 and A7626;
A7638 <= A7647 and A7646;
A7639 <= A7645 and A7626;
A7640 <= A7648 or A7625;
A7641 <= (A7626 and A7638) or ((not A7626) and (not A7638));
A7642 <= (not A7651) or (not A7652);
A7643 <= ((not A7627) and A7634) or (A7627 and (not A7634));
A7644 <= A7653 and A7646;
A7645 <= (not A7655) or (not A7654);
A7646 <= A7627 or A7628;
A7647 <= A7627 or A7634;
A7648 <= A7626 and A7638;
A7649 <= (not A7625) or (not A7626);
A7650 <= A7634 and A7649;
A7651 <= (not A7650) and (not A7634);
A7652 <= A7634 or A7649;
A7653 <= (not A7627) or (not A7628);
A7654 <= A7634 or A7649;
A7655 <= (not A7634) and (not A7656);
A7656 <= A7634 and A7649;
A7657 <= B4692;
A7658 <= B4725;
A7659 <= B4758;
A7660 <= B4791;
A7661 <= B4824;
A7662 <= A7668 and A7667;
A7663 <= A7670 or A7669;
A7664 <= A7672 or A7671;
A7665 <= A7667 and A7673;
A7666 <= A7667 and A7674;
A7667 <= ((not A7657) and A7658) or (A7657 and (not A7658));
A7668 <= ((not A7669) and A7659) or (A7669 and (not A7659));
A7669 <= A7677 and A7676;
A7670 <= A7675 and A7659;
A7671 <= A7680 and A7679;
A7672 <= A7678 and A7659;
A7673 <= A7681 or A7658;
A7674 <= (A7659 and A7671) or ((not A7659) and (not A7671));
A7675 <= (not A7684) or (not A7685);
A7676 <= ((not A7660) and A7667) or (A7660 and (not A7667));
A7677 <= A7686 and A7679;
A7678 <= (not A7688) or (not A7687);
A7679 <= A7660 or A7661;
A7680 <= A7660 or A7667;
A7681 <= A7659 and A7671;
A7682 <= (not A7658) or (not A7659);
A7683 <= A7667 and A7682;
A7684 <= (not A7683) and (not A7667);
A7685 <= A7667 or A7682;
A7686 <= (not A7660) or (not A7661);
A7687 <= A7667 or A7682;
A7688 <= (not A7667) and (not A7689);
A7689 <= A7667 and A7682;
A7690 <= B4857;
A7691 <= B4890;
A7692 <= B4923;
A7693 <= B4956;
A7694 <= B4989;
A7695 <= A7701 and A7700;
A7696 <= A7703 or A7702;
A7697 <= A7705 or A7704;
A7698 <= A7700 and A7706;
A7699 <= A7700 and A7707;
A7700 <= ((not A7690) and A7691) or (A7690 and (not A7691));
A7701 <= ((not A7702) and A7692) or (A7702 and (not A7692));
A7702 <= A7710 and A7709;
A7703 <= A7708 and A7692;
A7704 <= A7713 and A7712;
A7705 <= A7711 and A7692;
A7706 <= A7714 or A7691;
A7707 <= (A7692 and A7704) or ((not A7692) and (not A7704));
A7708 <= (not A7717) or (not A7718);
A7709 <= ((not A7693) and A7700) or (A7693 and (not A7700));
A7710 <= A7719 and A7712;
A7711 <= (not A7721) or (not A7720);
A7712 <= A7693 or A7694;
A7713 <= A7693 or A7700;
A7714 <= A7692 and A7704;
A7715 <= (not A7691) or (not A7692);
A7716 <= A7700 and A7715;
A7717 <= (not A7716) and (not A7700);
A7718 <= A7700 or A7715;
A7719 <= (not A7693) or (not A7694);
A7720 <= A7700 or A7715;
A7721 <= (not A7700) and (not A7722);
A7722 <= A7700 and A7715;
A7723 <= B5022;
A7724 <= B5055;
A7725 <= B5088;
A7726 <= B5121;
A7727 <= B5154;
A7728 <= A7734 and A7733;
A7729 <= A7736 or A7735;
A7730 <= A7738 or A7737;
A7731 <= A7733 and A7739;
A7732 <= A7733 and A7740;
A7733 <= ((not A7723) and A7724) or (A7723 and (not A7724));
A7734 <= ((not A7735) and A7725) or (A7735 and (not A7725));
A7735 <= A7743 and A7742;
A7736 <= A7741 and A7725;
A7737 <= A7746 and A7745;
A7738 <= A7744 and A7725;
A7739 <= A7747 or A7724;
A7740 <= (A7725 and A7737) or ((not A7725) and (not A7737));
A7741 <= (not A7750) or (not A7751);
A7742 <= ((not A7726) and A7733) or (A7726 and (not A7733));
A7743 <= A7752 and A7745;
A7744 <= (not A7754) or (not A7753);
A7745 <= A7726 or A7727;
A7746 <= A7726 or A7733;
A7747 <= A7725 and A7737;
A7748 <= (not A7724) or (not A7725);
A7749 <= A7733 and A7748;
A7750 <= (not A7749) and (not A7733);
A7751 <= A7733 or A7748;
A7752 <= (not A7726) or (not A7727);
A7753 <= A7733 or A7748;
A7754 <= (not A7733) and (not A7755);
A7755 <= A7733 and A7748;
A7756 <= B1065;
A7757 <= B1096;
A7758 <= B1129;
A7759 <= B1162;
A7760 <= B1195;
A7761 <= A7767 and A7766;
A7762 <= A7769 or A7768;
A7763 <= A7771 or A7770;
A7764 <= A7766 and A7772;
A7765 <= A7766 and A7773;
A7766 <= ((not A7756) and A7757) or (A7756 and (not A7757));
A7767 <= ((not A7768) and A7758) or (A7768 and (not A7758));
A7768 <= A7776 and A7775;
A7769 <= A7774 and A7758;
A7770 <= A7779 and A7778;
A7771 <= A7777 and A7758;
A7772 <= A7780 or A7757;
A7773 <= (A7758 and A7770) or ((not A7758) and (not A7770));
A7774 <= (not A7783) or (not A7784);
A7775 <= ((not A7759) and A7766) or (A7759 and (not A7766));
A7776 <= A7785 and A7778;
A7777 <= (not A7787) or (not A7786);
A7778 <= A7759 or A7760;
A7779 <= A7759 or A7766;
A7780 <= A7758 and A7770;
A7781 <= (not A7757) or (not A7758);
A7782 <= A7766 and A7781;
A7783 <= (not A7782) and (not A7766);
A7784 <= A7766 or A7781;
A7785 <= (not A7759) or (not A7760);
A7786 <= A7766 or A7781;
A7787 <= (not A7766) and (not A7788);
A7788 <= A7766 and A7781;
A7789 <= B1228;
A7790 <= B1261;
A7791 <= B1294;
A7792 <= B1327;
A7793 <= B1360;
A7794 <= A7800 and A7799;
A7795 <= A7802 or A7801;
A7796 <= A7804 or A7803;
A7797 <= A7799 and A7805;
A7798 <= A7799 and A7806;
A7799 <= ((not A7789) and A7790) or (A7789 and (not A7790));
A7800 <= ((not A7801) and A7791) or (A7801 and (not A7791));
A7801 <= A7809 and A7808;
A7802 <= A7807 and A7791;
A7803 <= A7812 and A7811;
A7804 <= A7810 and A7791;
A7805 <= A7813 or A7790;
A7806 <= (A7791 and A7803) or ((not A7791) and (not A7803));
A7807 <= (not A7816) or (not A7817);
A7808 <= ((not A7792) and A7799) or (A7792 and (not A7799));
A7809 <= A7818 and A7811;
A7810 <= (not A7820) or (not A7819);
A7811 <= A7792 or A7793;
A7812 <= A7792 or A7799;
A7813 <= A7791 and A7803;
A7814 <= (not A7790) or (not A7791);
A7815 <= A7799 and A7814;
A7816 <= (not A7815) and (not A7799);
A7817 <= A7799 or A7814;
A7818 <= (not A7792) or (not A7793);
A7819 <= A7799 or A7814;
A7820 <= (not A7799) and (not A7821);
A7821 <= A7799 and A7814;
A7822 <= B1393;
A7823 <= B1426;
A7824 <= B1459;
A7825 <= B1492;
A7826 <= B1525;
A7827 <= A7833 and A7832;
A7828 <= A7835 or A7834;
A7829 <= A7837 or A7836;
A7830 <= A7832 and A7838;
A7831 <= A7832 and A7839;
A7832 <= ((not A7822) and A7823) or (A7822 and (not A7823));
A7833 <= ((not A7834) and A7824) or (A7834 and (not A7824));
A7834 <= A7842 and A7841;
A7835 <= A7840 and A7824;
A7836 <= A7845 and A7844;
A7837 <= A7843 and A7824;
A7838 <= A7846 or A7823;
A7839 <= (A7824 and A7836) or ((not A7824) and (not A7836));
A7840 <= (not A7849) or (not A7850);
A7841 <= ((not A7825) and A7832) or (A7825 and (not A7832));
A7842 <= A7851 and A7844;
A7843 <= (not A7853) or (not A7852);
A7844 <= A7825 or A7826;
A7845 <= A7825 or A7832;
A7846 <= A7824 and A7836;
A7847 <= (not A7823) or (not A7824);
A7848 <= A7832 and A7847;
A7849 <= (not A7848) and (not A7832);
A7850 <= A7832 or A7847;
A7851 <= (not A7825) or (not A7826);
A7852 <= A7832 or A7847;
A7853 <= (not A7832) and (not A7854);
A7854 <= A7832 and A7847;
A7855 <= B1558;
A7856 <= B1591;
A7857 <= B1624;
A7858 <= B1657;
A7859 <= B1690;
A7860 <= A7866 and A7865;
A7861 <= A7868 or A7867;
A7862 <= A7870 or A7869;
A7863 <= A7865 and A7871;
A7864 <= A7865 and A7872;
A7865 <= ((not A7855) and A7856) or (A7855 and (not A7856));
A7866 <= ((not A7867) and A7857) or (A7867 and (not A7857));
A7867 <= A7875 and A7874;
A7868 <= A7873 and A7857;
A7869 <= A7878 and A7877;
A7870 <= A7876 and A7857;
A7871 <= A7879 or A7856;
A7872 <= (A7857 and A7869) or ((not A7857) and (not A7869));
A7873 <= (not A7882) or (not A7883);
A7874 <= ((not A7858) and A7865) or (A7858 and (not A7865));
A7875 <= A7884 and A7877;
A7876 <= (not A7886) or (not A7885);
A7877 <= A7858 or A7859;
A7878 <= A7858 or A7865;
A7879 <= A7857 and A7869;
A7880 <= (not A7856) or (not A7857);
A7881 <= A7865 and A7880;
A7882 <= (not A7881) and (not A7865);
A7883 <= A7865 or A7880;
A7884 <= (not A7858) or (not A7859);
A7885 <= A7865 or A7880;
A7886 <= (not A7865) and (not A7887);
A7887 <= A7865 and A7880;
A7888 <= B1723;
A7889 <= B1756;
A7890 <= B1789;
A7891 <= B1822;
A7892 <= B1855;
A7893 <= A7899 and A7898;
A7894 <= A7901 or A7900;
A7895 <= A7903 or A7902;
A7896 <= A7898 and A7904;
A7897 <= A7898 and A7905;
A7898 <= ((not A7888) and A7889) or (A7888 and (not A7889));
A7899 <= ((not A7900) and A7890) or (A7900 and (not A7890));
A7900 <= A7908 and A7907;
A7901 <= A7906 and A7890;
A7902 <= A7911 and A7910;
A7903 <= A7909 and A7890;
A7904 <= A7912 or A7889;
A7905 <= (A7890 and A7902) or ((not A7890) and (not A7902));
A7906 <= (not A7915) or (not A7916);
A7907 <= ((not A7891) and A7898) or (A7891 and (not A7898));
A7908 <= A7917 and A7910;
A7909 <= (not A7919) or (not A7918);
A7910 <= A7891 or A7892;
A7911 <= A7891 or A7898;
A7912 <= A7890 and A7902;
A7913 <= (not A7889) or (not A7890);
A7914 <= A7898 and A7913;
A7915 <= (not A7914) and (not A7898);
A7916 <= A7898 or A7913;
A7917 <= (not A7891) or (not A7892);
A7918 <= A7898 or A7913;
A7919 <= (not A7898) and (not A7920);
A7920 <= A7898 and A7913;
A7921 <= B1888;
A7922 <= B1921;
A7923 <= B1954;
A7924 <= B1987;
A7925 <= B2020;
A7926 <= A7932 and A7931;
A7927 <= A7934 or A7933;
A7928 <= A7936 or A7935;
A7929 <= A7931 and A7937;
A7930 <= A7931 and A7938;
A7931 <= ((not A7921) and A7922) or (A7921 and (not A7922));
A7932 <= ((not A7933) and A7923) or (A7933 and (not A7923));
A7933 <= A7941 and A7940;
A7934 <= A7939 and A7923;
A7935 <= A7944 and A7943;
A7936 <= A7942 and A7923;
A7937 <= A7945 or A7922;
A7938 <= (A7923 and A7935) or ((not A7923) and (not A7935));
A7939 <= (not A7948) or (not A7949);
A7940 <= ((not A7924) and A7931) or (A7924 and (not A7931));
A7941 <= A7950 and A7943;
A7942 <= (not A7952) or (not A7951);
A7943 <= A7924 or A7925;
A7944 <= A7924 or A7931;
A7945 <= A7923 and A7935;
A7946 <= (not A7922) or (not A7923);
A7947 <= A7931 and A7946;
A7948 <= (not A7947) and (not A7931);
A7949 <= A7931 or A7946;
A7950 <= (not A7924) or (not A7925);
A7951 <= A7931 or A7946;
A7952 <= (not A7931) and (not A7953);
A7953 <= A7931 and A7946;
A7954 <= B2053;
A7955 <= B2086;
A7956 <= B2119;
A7957 <= B2152;
A7958 <= B2185;
A7959 <= A7965 and A7964;
A7960 <= A7967 or A7966;
A7961 <= A7969 or A7968;
A7962 <= A7964 and A7970;
A7963 <= A7964 and A7971;
A7964 <= ((not A7954) and A7955) or (A7954 and (not A7955));
A7965 <= ((not A7966) and A7956) or (A7966 and (not A7956));
A7966 <= A7974 and A7973;
A7967 <= A7972 and A7956;
A7968 <= A7977 and A7976;
A7969 <= A7975 and A7956;
A7970 <= A7978 or A7955;
A7971 <= (A7956 and A7968) or ((not A7956) and (not A7968));
A7972 <= (not A7981) or (not A7982);
A7973 <= ((not A7957) and A7964) or (A7957 and (not A7964));
A7974 <= A7983 and A7976;
A7975 <= (not A7985) or (not A7984);
A7976 <= A7957 or A7958;
A7977 <= A7957 or A7964;
A7978 <= A7956 and A7968;
A7979 <= (not A7955) or (not A7956);
A7980 <= A7964 and A7979;
A7981 <= (not A7980) and (not A7964);
A7982 <= A7964 or A7979;
A7983 <= (not A7957) or (not A7958);
A7984 <= A7964 or A7979;
A7985 <= (not A7964) and (not A7986);
A7986 <= A7964 and A7979;
A7987 <= B2218;
A7988 <= B2251;
A7989 <= B2284;
A7990 <= B2317;
A7991 <= B2350;
A7992 <= A7998 and A7997;
A7993 <= A8000 or A7999;
A7994 <= A8002 or A8001;
A7995 <= A7997 and A8003;
A7996 <= A7997 and A8004;
A7997 <= ((not A7987) and A7988) or (A7987 and (not A7988));
A7998 <= ((not A7999) and A7989) or (A7999 and (not A7989));
A7999 <= A8007 and A8006;
A8000 <= A8005 and A7989;
A8001 <= A8010 and A8009;
A8002 <= A8008 and A7989;
A8003 <= A8011 or A7988;
A8004 <= (A7989 and A8001) or ((not A7989) and (not A8001));
A8005 <= (not A8014) or (not A8015);
A8006 <= ((not A7990) and A7997) or (A7990 and (not A7997));
A8007 <= A8016 and A8009;
A8008 <= (not A8018) or (not A8017);
A8009 <= A7990 or A7991;
A8010 <= A7990 or A7997;
A8011 <= A7989 and A8001;
A8012 <= (not A7988) or (not A7989);
A8013 <= A7997 and A8012;
A8014 <= (not A8013) and (not A7997);
A8015 <= A7997 or A8012;
A8016 <= (not A7990) or (not A7991);
A8017 <= A7997 or A8012;
A8018 <= (not A7997) and (not A8019);
A8019 <= A7997 and A8012;
A8020 <= B2383;
A8021 <= B2416;
A8022 <= B2449;
A8023 <= B2482;
A8024 <= B2515;
A8025 <= A8031 and A8030;
A8026 <= A8033 or A8032;
A8027 <= A8035 or A8034;
A8028 <= A8030 and A8036;
A8029 <= A8030 and A8037;
A8030 <= ((not A8020) and A8021) or (A8020 and (not A8021));
A8031 <= ((not A8032) and A8022) or (A8032 and (not A8022));
A8032 <= A8040 and A8039;
A8033 <= A8038 and A8022;
A8034 <= A8043 and A8042;
A8035 <= A8041 and A8022;
A8036 <= A8044 or A8021;
A8037 <= (A8022 and A8034) or ((not A8022) and (not A8034));
A8038 <= (not A8047) or (not A8048);
A8039 <= ((not A8023) and A8030) or (A8023 and (not A8030));
A8040 <= A8049 and A8042;
A8041 <= (not A8051) or (not A8050);
A8042 <= A8023 or A8024;
A8043 <= A8023 or A8030;
A8044 <= A8022 and A8034;
A8045 <= (not A8021) or (not A8022);
A8046 <= A8030 and A8045;
A8047 <= (not A8046) and (not A8030);
A8048 <= A8030 or A8045;
A8049 <= (not A8023) or (not A8024);
A8050 <= A8030 or A8045;
A8051 <= (not A8030) and (not A8052);
A8052 <= A8030 and A8045;
A8053 <= B2548;
A8054 <= B2581;
A8055 <= B2614;
A8056 <= B2647;
A8057 <= B2680;
A8058 <= A8064 and A8063;
A8059 <= A8066 or A8065;
A8060 <= A8068 or A8067;
A8061 <= A8063 and A8069;
A8062 <= A8063 and A8070;
A8063 <= ((not A8053) and A8054) or (A8053 and (not A8054));
A8064 <= ((not A8065) and A8055) or (A8065 and (not A8055));
A8065 <= A8073 and A8072;
A8066 <= A8071 and A8055;
A8067 <= A8076 and A8075;
A8068 <= A8074 and A8055;
A8069 <= A8077 or A8054;
A8070 <= (A8055 and A8067) or ((not A8055) and (not A8067));
A8071 <= (not A8080) or (not A8081);
A8072 <= ((not A8056) and A8063) or (A8056 and (not A8063));
A8073 <= A8082 and A8075;
A8074 <= (not A8084) or (not A8083);
A8075 <= A8056 or A8057;
A8076 <= A8056 or A8063;
A8077 <= A8055 and A8067;
A8078 <= (not A8054) or (not A8055);
A8079 <= A8063 and A8078;
A8080 <= (not A8079) and (not A8063);
A8081 <= A8063 or A8078;
A8082 <= (not A8056) or (not A8057);
A8083 <= A8063 or A8078;
A8084 <= (not A8063) and (not A8085);
A8085 <= A8063 and A8078;
A8086 <= B2713;
A8087 <= B2746;
A8088 <= B2779;
A8089 <= B2812;
A8090 <= B2845;
A8091 <= A8097 and A8096;
A8092 <= A8099 or A8098;
A8093 <= A8101 or A8100;
A8094 <= A8096 and A8102;
A8095 <= A8096 and A8103;
A8096 <= ((not A8086) and A8087) or (A8086 and (not A8087));
A8097 <= ((not A8098) and A8088) or (A8098 and (not A8088));
A8098 <= A8106 and A8105;
A8099 <= A8104 and A8088;
A8100 <= A8109 and A8108;
A8101 <= A8107 and A8088;
A8102 <= A8110 or A8087;
A8103 <= (A8088 and A8100) or ((not A8088) and (not A8100));
A8104 <= (not A8113) or (not A8114);
A8105 <= ((not A8089) and A8096) or (A8089 and (not A8096));
A8106 <= A8115 and A8108;
A8107 <= (not A8117) or (not A8116);
A8108 <= A8089 or A8090;
A8109 <= A8089 or A8096;
A8110 <= A8088 and A8100;
A8111 <= (not A8087) or (not A8088);
A8112 <= A8096 and A8111;
A8113 <= (not A8112) and (not A8096);
A8114 <= A8096 or A8111;
A8115 <= (not A8089) or (not A8090);
A8116 <= A8096 or A8111;
A8117 <= (not A8096) and (not A8118);
A8118 <= A8096 and A8111;
A8119 <= B2878;
A8120 <= B2911;
A8121 <= B2944;
A8122 <= B2977;
A8123 <= B3010;
A8124 <= A8130 and A8129;
A8125 <= A8132 or A8131;
A8126 <= A8134 or A8133;
A8127 <= A8129 and A8135;
A8128 <= A8129 and A8136;
A8129 <= ((not A8119) and A8120) or (A8119 and (not A8120));
A8130 <= ((not A8131) and A8121) or (A8131 and (not A8121));
A8131 <= A8139 and A8138;
A8132 <= A8137 and A8121;
A8133 <= A8142 and A8141;
A8134 <= A8140 and A8121;
A8135 <= A8143 or A8120;
A8136 <= (A8121 and A8133) or ((not A8121) and (not A8133));
A8137 <= (not A8146) or (not A8147);
A8138 <= ((not A8122) and A8129) or (A8122 and (not A8129));
A8139 <= A8148 and A8141;
A8140 <= (not A8150) or (not A8149);
A8141 <= A8122 or A8123;
A8142 <= A8122 or A8129;
A8143 <= A8121 and A8133;
A8144 <= (not A8120) or (not A8121);
A8145 <= A8129 and A8144;
A8146 <= (not A8145) and (not A8129);
A8147 <= A8129 or A8144;
A8148 <= (not A8122) or (not A8123);
A8149 <= A8129 or A8144;
A8150 <= (not A8129) and (not A8151);
A8151 <= A8129 and A8144;
A8152 <= B3043;
A8153 <= B3076;
A8154 <= B3109;
A8155 <= B3142;
A8156 <= B3175;
A8157 <= A8163 and A8162;
A8158 <= A8165 or A8164;
A8159 <= A8167 or A8166;
A8160 <= A8162 and A8168;
A8161 <= A8162 and A8169;
A8162 <= ((not A8152) and A8153) or (A8152 and (not A8153));
A8163 <= ((not A8164) and A8154) or (A8164 and (not A8154));
A8164 <= A8172 and A8171;
A8165 <= A8170 and A8154;
A8166 <= A8175 and A8174;
A8167 <= A8173 and A8154;
A8168 <= A8176 or A8153;
A8169 <= (A8154 and A8166) or ((not A8154) and (not A8166));
A8170 <= (not A8179) or (not A8180);
A8171 <= ((not A8155) and A8162) or (A8155 and (not A8162));
A8172 <= A8181 and A8174;
A8173 <= (not A8183) or (not A8182);
A8174 <= A8155 or A8156;
A8175 <= A8155 or A8162;
A8176 <= A8154 and A8166;
A8177 <= (not A8153) or (not A8154);
A8178 <= A8162 and A8177;
A8179 <= (not A8178) and (not A8162);
A8180 <= A8162 or A8177;
A8181 <= (not A8155) or (not A8156);
A8182 <= A8162 or A8177;
A8183 <= (not A8162) and (not A8184);
A8184 <= A8162 and A8177;
A8185 <= B3208;
A8186 <= B3241;
A8187 <= B3274;
A8188 <= B3307;
A8189 <= B3340;
A8190 <= A8196 and A8195;
A8191 <= A8198 or A8197;
A8192 <= A8200 or A8199;
A8193 <= A8195 and A8201;
A8194 <= A8195 and A8202;
A8195 <= ((not A8185) and A8186) or (A8185 and (not A8186));
A8196 <= ((not A8197) and A8187) or (A8197 and (not A8187));
A8197 <= A8205 and A8204;
A8198 <= A8203 and A8187;
A8199 <= A8208 and A8207;
A8200 <= A8206 and A8187;
A8201 <= A8209 or A8186;
A8202 <= (A8187 and A8199) or ((not A8187) and (not A8199));
A8203 <= (not A8212) or (not A8213);
A8204 <= ((not A8188) and A8195) or (A8188 and (not A8195));
A8205 <= A8214 and A8207;
A8206 <= (not A8216) or (not A8215);
A8207 <= A8188 or A8189;
A8208 <= A8188 or A8195;
A8209 <= A8187 and A8199;
A8210 <= (not A8186) or (not A8187);
A8211 <= A8195 and A8210;
A8212 <= (not A8211) and (not A8195);
A8213 <= A8195 or A8210;
A8214 <= (not A8188) or (not A8189);
A8215 <= A8195 or A8210;
A8216 <= (not A8195) and (not A8217);
A8217 <= A8195 and A8210;
A8218 <= B3373;
A8219 <= B3406;
A8220 <= B3439;
A8221 <= B3472;
A8222 <= B3505;
A8223 <= A8229 and A8228;
A8224 <= A8231 or A8230;
A8225 <= A8233 or A8232;
A8226 <= A8228 and A8234;
A8227 <= A8228 and A8235;
A8228 <= ((not A8218) and A8219) or (A8218 and (not A8219));
A8229 <= ((not A8230) and A8220) or (A8230 and (not A8220));
A8230 <= A8238 and A8237;
A8231 <= A8236 and A8220;
A8232 <= A8241 and A8240;
A8233 <= A8239 and A8220;
A8234 <= A8242 or A8219;
A8235 <= (A8220 and A8232) or ((not A8220) and (not A8232));
A8236 <= (not A8245) or (not A8246);
A8237 <= ((not A8221) and A8228) or (A8221 and (not A8228));
A8238 <= A8247 and A8240;
A8239 <= (not A8249) or (not A8248);
A8240 <= A8221 or A8222;
A8241 <= A8221 or A8228;
A8242 <= A8220 and A8232;
A8243 <= (not A8219) or (not A8220);
A8244 <= A8228 and A8243;
A8245 <= (not A8244) and (not A8228);
A8246 <= A8228 or A8243;
A8247 <= (not A8221) or (not A8222);
A8248 <= A8228 or A8243;
A8249 <= (not A8228) and (not A8250);
A8250 <= A8228 and A8243;
A8251 <= B3538;
A8252 <= B3571;
A8253 <= B3604;
A8254 <= B3637;
A8255 <= B3670;
A8256 <= A8262 and A8261;
A8257 <= A8264 or A8263;
A8258 <= A8266 or A8265;
A8259 <= A8261 and A8267;
A8260 <= A8261 and A8268;
A8261 <= ((not A8251) and A8252) or (A8251 and (not A8252));
A8262 <= ((not A8263) and A8253) or (A8263 and (not A8253));
A8263 <= A8271 and A8270;
A8264 <= A8269 and A8253;
A8265 <= A8274 and A8273;
A8266 <= A8272 and A8253;
A8267 <= A8275 or A8252;
A8268 <= (A8253 and A8265) or ((not A8253) and (not A8265));
A8269 <= (not A8278) or (not A8279);
A8270 <= ((not A8254) and A8261) or (A8254 and (not A8261));
A8271 <= A8280 and A8273;
A8272 <= (not A8282) or (not A8281);
A8273 <= A8254 or A8255;
A8274 <= A8254 or A8261;
A8275 <= A8253 and A8265;
A8276 <= (not A8252) or (not A8253);
A8277 <= A8261 and A8276;
A8278 <= (not A8277) and (not A8261);
A8279 <= A8261 or A8276;
A8280 <= (not A8254) or (not A8255);
A8281 <= A8261 or A8276;
A8282 <= (not A8261) and (not A8283);
A8283 <= A8261 and A8276;
A8284 <= B3703;
A8285 <= B3736;
A8286 <= B3769;
A8287 <= B3802;
A8288 <= B3835;
A8289 <= A8295 and A8294;
A8290 <= A8297 or A8296;
A8291 <= A8299 or A8298;
A8292 <= A8294 and A8300;
A8293 <= A8294 and A8301;
A8294 <= ((not A8284) and A8285) or (A8284 and (not A8285));
A8295 <= ((not A8296) and A8286) or (A8296 and (not A8286));
A8296 <= A8304 and A8303;
A8297 <= A8302 and A8286;
A8298 <= A8307 and A8306;
A8299 <= A8305 and A8286;
A8300 <= A8308 or A8285;
A8301 <= (A8286 and A8298) or ((not A8286) and (not A8298));
A8302 <= (not A8311) or (not A8312);
A8303 <= ((not A8287) and A8294) or (A8287 and (not A8294));
A8304 <= A8313 and A8306;
A8305 <= (not A8315) or (not A8314);
A8306 <= A8287 or A8288;
A8307 <= A8287 or A8294;
A8308 <= A8286 and A8298;
A8309 <= (not A8285) or (not A8286);
A8310 <= A8294 and A8309;
A8311 <= (not A8310) and (not A8294);
A8312 <= A8294 or A8309;
A8313 <= (not A8287) or (not A8288);
A8314 <= A8294 or A8309;
A8315 <= (not A8294) and (not A8316);
A8316 <= A8294 and A8309;
A8317 <= B3868;
A8318 <= B3901;
A8319 <= B3934;
A8320 <= B3967;
A8321 <= B4000;
A8322 <= A8328 and A8327;
A8323 <= A8330 or A8329;
A8324 <= A8332 or A8331;
A8325 <= A8327 and A8333;
A8326 <= A8327 and A8334;
A8327 <= ((not A8317) and A8318) or (A8317 and (not A8318));
A8328 <= ((not A8329) and A8319) or (A8329 and (not A8319));
A8329 <= A8337 and A8336;
A8330 <= A8335 and A8319;
A8331 <= A8340 and A8339;
A8332 <= A8338 and A8319;
A8333 <= A8341 or A8318;
A8334 <= (A8319 and A8331) or ((not A8319) and (not A8331));
A8335 <= (not A8344) or (not A8345);
A8336 <= ((not A8320) and A8327) or (A8320 and (not A8327));
A8337 <= A8346 and A8339;
A8338 <= (not A8348) or (not A8347);
A8339 <= A8320 or A8321;
A8340 <= A8320 or A8327;
A8341 <= A8319 and A8331;
A8342 <= (not A8318) or (not A8319);
A8343 <= A8327 and A8342;
A8344 <= (not A8343) and (not A8327);
A8345 <= A8327 or A8342;
A8346 <= (not A8320) or (not A8321);
A8347 <= A8327 or A8342;
A8348 <= (not A8327) and (not A8349);
A8349 <= A8327 and A8342;
A8350 <= B4033;
A8351 <= B4066;
A8352 <= B4099;
A8353 <= B4132;
A8354 <= B4165;
A8355 <= A8361 and A8360;
A8356 <= A8363 or A8362;
A8357 <= A8365 or A8364;
A8358 <= A8360 and A8366;
A8359 <= A8360 and A8367;
A8360 <= ((not A8350) and A8351) or (A8350 and (not A8351));
A8361 <= ((not A8362) and A8352) or (A8362 and (not A8352));
A8362 <= A8370 and A8369;
A8363 <= A8368 and A8352;
A8364 <= A8373 and A8372;
A8365 <= A8371 and A8352;
A8366 <= A8374 or A8351;
A8367 <= (A8352 and A8364) or ((not A8352) and (not A8364));
A8368 <= (not A8377) or (not A8378);
A8369 <= ((not A8353) and A8360) or (A8353 and (not A8360));
A8370 <= A8379 and A8372;
A8371 <= (not A8381) or (not A8380);
A8372 <= A8353 or A8354;
A8373 <= A8353 or A8360;
A8374 <= A8352 and A8364;
A8375 <= (not A8351) or (not A8352);
A8376 <= A8360 and A8375;
A8377 <= (not A8376) and (not A8360);
A8378 <= A8360 or A8375;
A8379 <= (not A8353) or (not A8354);
A8380 <= A8360 or A8375;
A8381 <= (not A8360) and (not A8382);
A8382 <= A8360 and A8375;
A8383 <= B4198;
A8384 <= B4231;
A8385 <= B4264;
A8386 <= B4297;
A8387 <= B4330;
A8388 <= A8394 and A8393;
A8389 <= A8396 or A8395;
A8390 <= A8398 or A8397;
A8391 <= A8393 and A8399;
A8392 <= A8393 and A8400;
A8393 <= ((not A8383) and A8384) or (A8383 and (not A8384));
A8394 <= ((not A8395) and A8385) or (A8395 and (not A8385));
A8395 <= A8403 and A8402;
A8396 <= A8401 and A8385;
A8397 <= A8406 and A8405;
A8398 <= A8404 and A8385;
A8399 <= A8407 or A8384;
A8400 <= (A8385 and A8397) or ((not A8385) and (not A8397));
A8401 <= (not A8410) or (not A8411);
A8402 <= ((not A8386) and A8393) or (A8386 and (not A8393));
A8403 <= A8412 and A8405;
A8404 <= (not A8414) or (not A8413);
A8405 <= A8386 or A8387;
A8406 <= A8386 or A8393;
A8407 <= A8385 and A8397;
A8408 <= (not A8384) or (not A8385);
A8409 <= A8393 and A8408;
A8410 <= (not A8409) and (not A8393);
A8411 <= A8393 or A8408;
A8412 <= (not A8386) or (not A8387);
A8413 <= A8393 or A8408;
A8414 <= (not A8393) and (not A8415);
A8415 <= A8393 and A8408;
A8416 <= B4363;
A8417 <= B4396;
A8418 <= B4429;
A8419 <= B4462;
A8420 <= B4495;
A8421 <= A8427 and A8426;
A8422 <= A8429 or A8428;
A8423 <= A8431 or A8430;
A8424 <= A8426 and A8432;
A8425 <= A8426 and A8433;
A8426 <= ((not A8416) and A8417) or (A8416 and (not A8417));
A8427 <= ((not A8428) and A8418) or (A8428 and (not A8418));
A8428 <= A8436 and A8435;
A8429 <= A8434 and A8418;
A8430 <= A8439 and A8438;
A8431 <= A8437 and A8418;
A8432 <= A8440 or A8417;
A8433 <= (A8418 and A8430) or ((not A8418) and (not A8430));
A8434 <= (not A8443) or (not A8444);
A8435 <= ((not A8419) and A8426) or (A8419 and (not A8426));
A8436 <= A8445 and A8438;
A8437 <= (not A8447) or (not A8446);
A8438 <= A8419 or A8420;
A8439 <= A8419 or A8426;
A8440 <= A8418 and A8430;
A8441 <= (not A8417) or (not A8418);
A8442 <= A8426 and A8441;
A8443 <= (not A8442) and (not A8426);
A8444 <= A8426 or A8441;
A8445 <= (not A8419) or (not A8420);
A8446 <= A8426 or A8441;
A8447 <= (not A8426) and (not A8448);
A8448 <= A8426 and A8441;
A8449 <= B4528;
A8450 <= B4561;
A8451 <= B4594;
A8452 <= B4627;
A8453 <= B4660;
A8454 <= A8460 and A8459;
A8455 <= A8462 or A8461;
A8456 <= A8464 or A8463;
A8457 <= A8459 and A8465;
A8458 <= A8459 and A8466;
A8459 <= ((not A8449) and A8450) or (A8449 and (not A8450));
A8460 <= ((not A8461) and A8451) or (A8461 and (not A8451));
A8461 <= A8469 and A8468;
A8462 <= A8467 and A8451;
A8463 <= A8472 and A8471;
A8464 <= A8470 and A8451;
A8465 <= A8473 or A8450;
A8466 <= (A8451 and A8463) or ((not A8451) and (not A8463));
A8467 <= (not A8476) or (not A8477);
A8468 <= ((not A8452) and A8459) or (A8452 and (not A8459));
A8469 <= A8478 and A8471;
A8470 <= (not A8480) or (not A8479);
A8471 <= A8452 or A8453;
A8472 <= A8452 or A8459;
A8473 <= A8451 and A8463;
A8474 <= (not A8450) or (not A8451);
A8475 <= A8459 and A8474;
A8476 <= (not A8475) and (not A8459);
A8477 <= A8459 or A8474;
A8478 <= (not A8452) or (not A8453);
A8479 <= A8459 or A8474;
A8480 <= (not A8459) and (not A8481);
A8481 <= A8459 and A8474;
A8482 <= B4693;
A8483 <= B4726;
A8484 <= B4759;
A8485 <= B4792;
A8486 <= B4825;
A8487 <= A8493 and A8492;
A8488 <= A8495 or A8494;
A8489 <= A8497 or A8496;
A8490 <= A8492 and A8498;
A8491 <= A8492 and A8499;
A8492 <= ((not A8482) and A8483) or (A8482 and (not A8483));
A8493 <= ((not A8494) and A8484) or (A8494 and (not A8484));
A8494 <= A8502 and A8501;
A8495 <= A8500 and A8484;
A8496 <= A8505 and A8504;
A8497 <= A8503 and A8484;
A8498 <= A8506 or A8483;
A8499 <= (A8484 and A8496) or ((not A8484) and (not A8496));
A8500 <= (not A8509) or (not A8510);
A8501 <= ((not A8485) and A8492) or (A8485 and (not A8492));
A8502 <= A8511 and A8504;
A8503 <= (not A8513) or (not A8512);
A8504 <= A8485 or A8486;
A8505 <= A8485 or A8492;
A8506 <= A8484 and A8496;
A8507 <= (not A8483) or (not A8484);
A8508 <= A8492 and A8507;
A8509 <= (not A8508) and (not A8492);
A8510 <= A8492 or A8507;
A8511 <= (not A8485) or (not A8486);
A8512 <= A8492 or A8507;
A8513 <= (not A8492) and (not A8514);
A8514 <= A8492 and A8507;
A8515 <= B4858;
A8516 <= B4891;
A8517 <= B4924;
A8518 <= B4957;
A8519 <= B4990;
A8520 <= A8526 and A8525;
A8521 <= A8528 or A8527;
A8522 <= A8530 or A8529;
A8523 <= A8525 and A8531;
A8524 <= A8525 and A8532;
A8525 <= ((not A8515) and A8516) or (A8515 and (not A8516));
A8526 <= ((not A8527) and A8517) or (A8527 and (not A8517));
A8527 <= A8535 and A8534;
A8528 <= A8533 and A8517;
A8529 <= A8538 and A8537;
A8530 <= A8536 and A8517;
A8531 <= A8539 or A8516;
A8532 <= (A8517 and A8529) or ((not A8517) and (not A8529));
A8533 <= (not A8542) or (not A8543);
A8534 <= ((not A8518) and A8525) or (A8518 and (not A8525));
A8535 <= A8544 and A8537;
A8536 <= (not A8546) or (not A8545);
A8537 <= A8518 or A8519;
A8538 <= A8518 or A8525;
A8539 <= A8517 and A8529;
A8540 <= (not A8516) or (not A8517);
A8541 <= A8525 and A8540;
A8542 <= (not A8541) and (not A8525);
A8543 <= A8525 or A8540;
A8544 <= (not A8518) or (not A8519);
A8545 <= A8525 or A8540;
A8546 <= (not A8525) and (not A8547);
A8547 <= A8525 and A8540;
A8548 <= B5023;
A8549 <= B5056;
A8550 <= B5089;
A8551 <= B5122;
A8552 <= B5155;
A8553 <= A8559 and A8558;
A8554 <= A8561 or A8560;
A8555 <= A8563 or A8562;
A8556 <= A8558 and A8564;
A8557 <= A8558 and A8565;
A8558 <= ((not A8548) and A8549) or (A8548 and (not A8549));
A8559 <= ((not A8560) and A8550) or (A8560 and (not A8550));
A8560 <= A8568 and A8567;
A8561 <= A8566 and A8550;
A8562 <= A8571 and A8570;
A8563 <= A8569 and A8550;
A8564 <= A8572 or A8549;
A8565 <= (A8550 and A8562) or ((not A8550) and (not A8562));
A8566 <= (not A8575) or (not A8576);
A8567 <= ((not A8551) and A8558) or (A8551 and (not A8558));
A8568 <= A8577 and A8570;
A8569 <= (not A8579) or (not A8578);
A8570 <= A8551 or A8552;
A8571 <= A8551 or A8558;
A8572 <= A8550 and A8562;
A8573 <= (not A8549) or (not A8550);
A8574 <= A8558 and A8573;
A8575 <= (not A8574) and (not A8558);
A8576 <= A8558 or A8573;
A8577 <= (not A8551) or (not A8552);
A8578 <= A8558 or A8573;
A8579 <= (not A8558) and (not A8580);
A8580 <= A8558 and A8573;
A8581 <= B1064;
A8582 <= B1097;
A8583 <= B1130;
A8584 <= B1163;
A8585 <= B1196;
A8586 <= A8592 and A8591;
A8587 <= A8594 or A8593;
A8588 <= A8596 or A8595;
A8589 <= A8591 and A8597;
A8590 <= A8591 and A8598;
A8591 <= ((not A8581) and A8582) or (A8581 and (not A8582));
A8592 <= ((not A8593) and A8583) or (A8593 and (not A8583));
A8593 <= A8601 and A8600;
A8594 <= A8599 and A8583;
A8595 <= A8604 and A8603;
A8596 <= A8602 and A8583;
A8597 <= A8605 or A8582;
A8598 <= (A8583 and A8595) or ((not A8583) and (not A8595));
A8599 <= (not A8608) or (not A8609);
A8600 <= ((not A8584) and A8591) or (A8584 and (not A8591));
A8601 <= A8610 and A8603;
A8602 <= (not A8612) or (not A8611);
A8603 <= A8584 or A8585;
A8604 <= A8584 or A8591;
A8605 <= A8583 and A8595;
A8606 <= (not A8582) or (not A8583);
A8607 <= A8591 and A8606;
A8608 <= (not A8607) and (not A8591);
A8609 <= A8591 or A8606;
A8610 <= (not A8584) or (not A8585);
A8611 <= A8591 or A8606;
A8612 <= (not A8591) and (not A8613);
A8613 <= A8591 and A8606;
A8614 <= B1229;
A8615 <= B1262;
A8616 <= B1295;
A8617 <= B1328;
A8618 <= B1361;
A8619 <= A8625 and A8624;
A8620 <= A8627 or A8626;
A8621 <= A8629 or A8628;
A8622 <= A8624 and A8630;
A8623 <= A8624 and A8631;
A8624 <= ((not A8614) and A8615) or (A8614 and (not A8615));
A8625 <= ((not A8626) and A8616) or (A8626 and (not A8616));
A8626 <= A8634 and A8633;
A8627 <= A8632 and A8616;
A8628 <= A8637 and A8636;
A8629 <= A8635 and A8616;
A8630 <= A8638 or A8615;
A8631 <= (A8616 and A8628) or ((not A8616) and (not A8628));
A8632 <= (not A8641) or (not A8642);
A8633 <= ((not A8617) and A8624) or (A8617 and (not A8624));
A8634 <= A8643 and A8636;
A8635 <= (not A8645) or (not A8644);
A8636 <= A8617 or A8618;
A8637 <= A8617 or A8624;
A8638 <= A8616 and A8628;
A8639 <= (not A8615) or (not A8616);
A8640 <= A8624 and A8639;
A8641 <= (not A8640) and (not A8624);
A8642 <= A8624 or A8639;
A8643 <= (not A8617) or (not A8618);
A8644 <= A8624 or A8639;
A8645 <= (not A8624) and (not A8646);
A8646 <= A8624 and A8639;
A8647 <= B1394;
A8648 <= B1427;
A8649 <= B1460;
A8650 <= B1493;
A8651 <= B1526;
A8652 <= A8658 and A8657;
A8653 <= A8660 or A8659;
A8654 <= A8662 or A8661;
A8655 <= A8657 and A8663;
A8656 <= A8657 and A8664;
A8657 <= ((not A8647) and A8648) or (A8647 and (not A8648));
A8658 <= ((not A8659) and A8649) or (A8659 and (not A8649));
A8659 <= A8667 and A8666;
A8660 <= A8665 and A8649;
A8661 <= A8670 and A8669;
A8662 <= A8668 and A8649;
A8663 <= A8671 or A8648;
A8664 <= (A8649 and A8661) or ((not A8649) and (not A8661));
A8665 <= (not A8674) or (not A8675);
A8666 <= ((not A8650) and A8657) or (A8650 and (not A8657));
A8667 <= A8676 and A8669;
A8668 <= (not A8678) or (not A8677);
A8669 <= A8650 or A8651;
A8670 <= A8650 or A8657;
A8671 <= A8649 and A8661;
A8672 <= (not A8648) or (not A8649);
A8673 <= A8657 and A8672;
A8674 <= (not A8673) and (not A8657);
A8675 <= A8657 or A8672;
A8676 <= (not A8650) or (not A8651);
A8677 <= A8657 or A8672;
A8678 <= (not A8657) and (not A8679);
A8679 <= A8657 and A8672;
A8680 <= B1559;
A8681 <= B1592;
A8682 <= B1625;
A8683 <= B1658;
A8684 <= B1691;
A8685 <= A8691 and A8690;
A8686 <= A8693 or A8692;
A8687 <= A8695 or A8694;
A8688 <= A8690 and A8696;
A8689 <= A8690 and A8697;
A8690 <= ((not A8680) and A8681) or (A8680 and (not A8681));
A8691 <= ((not A8692) and A8682) or (A8692 and (not A8682));
A8692 <= A8700 and A8699;
A8693 <= A8698 and A8682;
A8694 <= A8703 and A8702;
A8695 <= A8701 and A8682;
A8696 <= A8704 or A8681;
A8697 <= (A8682 and A8694) or ((not A8682) and (not A8694));
A8698 <= (not A8707) or (not A8708);
A8699 <= ((not A8683) and A8690) or (A8683 and (not A8690));
A8700 <= A8709 and A8702;
A8701 <= (not A8711) or (not A8710);
A8702 <= A8683 or A8684;
A8703 <= A8683 or A8690;
A8704 <= A8682 and A8694;
A8705 <= (not A8681) or (not A8682);
A8706 <= A8690 and A8705;
A8707 <= (not A8706) and (not A8690);
A8708 <= A8690 or A8705;
A8709 <= (not A8683) or (not A8684);
A8710 <= A8690 or A8705;
A8711 <= (not A8690) and (not A8712);
A8712 <= A8690 and A8705;
A8713 <= B1724;
A8714 <= B1757;
A8715 <= B1790;
A8716 <= B1823;
A8717 <= B1856;
A8718 <= A8724 and A8723;
A8719 <= A8726 or A8725;
A8720 <= A8728 or A8727;
A8721 <= A8723 and A8729;
A8722 <= A8723 and A8730;
A8723 <= ((not A8713) and A8714) or (A8713 and (not A8714));
A8724 <= ((not A8725) and A8715) or (A8725 and (not A8715));
A8725 <= A8733 and A8732;
A8726 <= A8731 and A8715;
A8727 <= A8736 and A8735;
A8728 <= A8734 and A8715;
A8729 <= A8737 or A8714;
A8730 <= (A8715 and A8727) or ((not A8715) and (not A8727));
A8731 <= (not A8740) or (not A8741);
A8732 <= ((not A8716) and A8723) or (A8716 and (not A8723));
A8733 <= A8742 and A8735;
A8734 <= (not A8744) or (not A8743);
A8735 <= A8716 or A8717;
A8736 <= A8716 or A8723;
A8737 <= A8715 and A8727;
A8738 <= (not A8714) or (not A8715);
A8739 <= A8723 and A8738;
A8740 <= (not A8739) and (not A8723);
A8741 <= A8723 or A8738;
A8742 <= (not A8716) or (not A8717);
A8743 <= A8723 or A8738;
A8744 <= (not A8723) and (not A8745);
A8745 <= A8723 and A8738;
A8746 <= B1889;
A8747 <= B1922;
A8748 <= B1955;
A8749 <= B1988;
A8750 <= B2021;
A8751 <= A8757 and A8756;
A8752 <= A8759 or A8758;
A8753 <= A8761 or A8760;
A8754 <= A8756 and A8762;
A8755 <= A8756 and A8763;
A8756 <= ((not A8746) and A8747) or (A8746 and (not A8747));
A8757 <= ((not A8758) and A8748) or (A8758 and (not A8748));
A8758 <= A8766 and A8765;
A8759 <= A8764 and A8748;
A8760 <= A8769 and A8768;
A8761 <= A8767 and A8748;
A8762 <= A8770 or A8747;
A8763 <= (A8748 and A8760) or ((not A8748) and (not A8760));
A8764 <= (not A8773) or (not A8774);
A8765 <= ((not A8749) and A8756) or (A8749 and (not A8756));
A8766 <= A8775 and A8768;
A8767 <= (not A8777) or (not A8776);
A8768 <= A8749 or A8750;
A8769 <= A8749 or A8756;
A8770 <= A8748 and A8760;
A8771 <= (not A8747) or (not A8748);
A8772 <= A8756 and A8771;
A8773 <= (not A8772) and (not A8756);
A8774 <= A8756 or A8771;
A8775 <= (not A8749) or (not A8750);
A8776 <= A8756 or A8771;
A8777 <= (not A8756) and (not A8778);
A8778 <= A8756 and A8771;
A8779 <= B2054;
A8780 <= B2087;
A8781 <= B2120;
A8782 <= B2153;
A8783 <= B2186;
A8784 <= A8790 and A8789;
A8785 <= A8792 or A8791;
A8786 <= A8794 or A8793;
A8787 <= A8789 and A8795;
A8788 <= A8789 and A8796;
A8789 <= ((not A8779) and A8780) or (A8779 and (not A8780));
A8790 <= ((not A8791) and A8781) or (A8791 and (not A8781));
A8791 <= A8799 and A8798;
A8792 <= A8797 and A8781;
A8793 <= A8802 and A8801;
A8794 <= A8800 and A8781;
A8795 <= A8803 or A8780;
A8796 <= (A8781 and A8793) or ((not A8781) and (not A8793));
A8797 <= (not A8806) or (not A8807);
A8798 <= ((not A8782) and A8789) or (A8782 and (not A8789));
A8799 <= A8808 and A8801;
A8800 <= (not A8810) or (not A8809);
A8801 <= A8782 or A8783;
A8802 <= A8782 or A8789;
A8803 <= A8781 and A8793;
A8804 <= (not A8780) or (not A8781);
A8805 <= A8789 and A8804;
A8806 <= (not A8805) and (not A8789);
A8807 <= A8789 or A8804;
A8808 <= (not A8782) or (not A8783);
A8809 <= A8789 or A8804;
A8810 <= (not A8789) and (not A8811);
A8811 <= A8789 and A8804;
A8812 <= B2219;
A8813 <= B2252;
A8814 <= B2285;
A8815 <= B2318;
A8816 <= B2351;
A8817 <= A8823 and A8822;
A8818 <= A8825 or A8824;
A8819 <= A8827 or A8826;
A8820 <= A8822 and A8828;
A8821 <= A8822 and A8829;
A8822 <= ((not A8812) and A8813) or (A8812 and (not A8813));
A8823 <= ((not A8824) and A8814) or (A8824 and (not A8814));
A8824 <= A8832 and A8831;
A8825 <= A8830 and A8814;
A8826 <= A8835 and A8834;
A8827 <= A8833 and A8814;
A8828 <= A8836 or A8813;
A8829 <= (A8814 and A8826) or ((not A8814) and (not A8826));
A8830 <= (not A8839) or (not A8840);
A8831 <= ((not A8815) and A8822) or (A8815 and (not A8822));
A8832 <= A8841 and A8834;
A8833 <= (not A8843) or (not A8842);
A8834 <= A8815 or A8816;
A8835 <= A8815 or A8822;
A8836 <= A8814 and A8826;
A8837 <= (not A8813) or (not A8814);
A8838 <= A8822 and A8837;
A8839 <= (not A8838) and (not A8822);
A8840 <= A8822 or A8837;
A8841 <= (not A8815) or (not A8816);
A8842 <= A8822 or A8837;
A8843 <= (not A8822) and (not A8844);
A8844 <= A8822 and A8837;
A8845 <= B2384;
A8846 <= B2417;
A8847 <= B2450;
A8848 <= B2483;
A8849 <= B2516;
A8850 <= A8856 and A8855;
A8851 <= A8858 or A8857;
A8852 <= A8860 or A8859;
A8853 <= A8855 and A8861;
A8854 <= A8855 and A8862;
A8855 <= ((not A8845) and A8846) or (A8845 and (not A8846));
A8856 <= ((not A8857) and A8847) or (A8857 and (not A8847));
A8857 <= A8865 and A8864;
A8858 <= A8863 and A8847;
A8859 <= A8868 and A8867;
A8860 <= A8866 and A8847;
A8861 <= A8869 or A8846;
A8862 <= (A8847 and A8859) or ((not A8847) and (not A8859));
A8863 <= (not A8872) or (not A8873);
A8864 <= ((not A8848) and A8855) or (A8848 and (not A8855));
A8865 <= A8874 and A8867;
A8866 <= (not A8876) or (not A8875);
A8867 <= A8848 or A8849;
A8868 <= A8848 or A8855;
A8869 <= A8847 and A8859;
A8870 <= (not A8846) or (not A8847);
A8871 <= A8855 and A8870;
A8872 <= (not A8871) and (not A8855);
A8873 <= A8855 or A8870;
A8874 <= (not A8848) or (not A8849);
A8875 <= A8855 or A8870;
A8876 <= (not A8855) and (not A8877);
A8877 <= A8855 and A8870;
A8878 <= B2549;
A8879 <= B2582;
A8880 <= B2615;
A8881 <= B2648;
A8882 <= B2681;
A8883 <= A8889 and A8888;
A8884 <= A8891 or A8890;
A8885 <= A8893 or A8892;
A8886 <= A8888 and A8894;
A8887 <= A8888 and A8895;
A8888 <= ((not A8878) and A8879) or (A8878 and (not A8879));
A8889 <= ((not A8890) and A8880) or (A8890 and (not A8880));
A8890 <= A8898 and A8897;
A8891 <= A8896 and A8880;
A8892 <= A8901 and A8900;
A8893 <= A8899 and A8880;
A8894 <= A8902 or A8879;
A8895 <= (A8880 and A8892) or ((not A8880) and (not A8892));
A8896 <= (not A8905) or (not A8906);
A8897 <= ((not A8881) and A8888) or (A8881 and (not A8888));
A8898 <= A8907 and A8900;
A8899 <= (not A8909) or (not A8908);
A8900 <= A8881 or A8882;
A8901 <= A8881 or A8888;
A8902 <= A8880 and A8892;
A8903 <= (not A8879) or (not A8880);
A8904 <= A8888 and A8903;
A8905 <= (not A8904) and (not A8888);
A8906 <= A8888 or A8903;
A8907 <= (not A8881) or (not A8882);
A8908 <= A8888 or A8903;
A8909 <= (not A8888) and (not A8910);
A8910 <= A8888 and A8903;
A8911 <= B2714;
A8912 <= B2747;
A8913 <= B2780;
A8914 <= B2813;
A8915 <= B2846;
A8916 <= A8922 and A8921;
A8917 <= A8924 or A8923;
A8918 <= A8926 or A8925;
A8919 <= A8921 and A8927;
A8920 <= A8921 and A8928;
A8921 <= ((not A8911) and A8912) or (A8911 and (not A8912));
A8922 <= ((not A8923) and A8913) or (A8923 and (not A8913));
A8923 <= A8931 and A8930;
A8924 <= A8929 and A8913;
A8925 <= A8934 and A8933;
A8926 <= A8932 and A8913;
A8927 <= A8935 or A8912;
A8928 <= (A8913 and A8925) or ((not A8913) and (not A8925));
A8929 <= (not A8938) or (not A8939);
A8930 <= ((not A8914) and A8921) or (A8914 and (not A8921));
A8931 <= A8940 and A8933;
A8932 <= (not A8942) or (not A8941);
A8933 <= A8914 or A8915;
A8934 <= A8914 or A8921;
A8935 <= A8913 and A8925;
A8936 <= (not A8912) or (not A8913);
A8937 <= A8921 and A8936;
A8938 <= (not A8937) and (not A8921);
A8939 <= A8921 or A8936;
A8940 <= (not A8914) or (not A8915);
A8941 <= A8921 or A8936;
A8942 <= (not A8921) and (not A8943);
A8943 <= A8921 and A8936;
A8944 <= B2879;
A8945 <= B2912;
A8946 <= B2945;
A8947 <= B2978;
A8948 <= B3011;
A8949 <= A8955 and A8954;
A8950 <= A8957 or A8956;
A8951 <= A8959 or A8958;
A8952 <= A8954 and A8960;
A8953 <= A8954 and A8961;
A8954 <= ((not A8944) and A8945) or (A8944 and (not A8945));
A8955 <= ((not A8956) and A8946) or (A8956 and (not A8946));
A8956 <= A8964 and A8963;
A8957 <= A8962 and A8946;
A8958 <= A8967 and A8966;
A8959 <= A8965 and A8946;
A8960 <= A8968 or A8945;
A8961 <= (A8946 and A8958) or ((not A8946) and (not A8958));
A8962 <= (not A8971) or (not A8972);
A8963 <= ((not A8947) and A8954) or (A8947 and (not A8954));
A8964 <= A8973 and A8966;
A8965 <= (not A8975) or (not A8974);
A8966 <= A8947 or A8948;
A8967 <= A8947 or A8954;
A8968 <= A8946 and A8958;
A8969 <= (not A8945) or (not A8946);
A8970 <= A8954 and A8969;
A8971 <= (not A8970) and (not A8954);
A8972 <= A8954 or A8969;
A8973 <= (not A8947) or (not A8948);
A8974 <= A8954 or A8969;
A8975 <= (not A8954) and (not A8976);
A8976 <= A8954 and A8969;
A8977 <= B3044;
A8978 <= B3077;
A8979 <= B3110;
A8980 <= B3143;
A8981 <= B3176;
A8982 <= A8988 and A8987;
A8983 <= A8990 or A8989;
A8984 <= A8992 or A8991;
A8985 <= A8987 and A8993;
A8986 <= A8987 and A8994;
A8987 <= ((not A8977) and A8978) or (A8977 and (not A8978));
A8988 <= ((not A8989) and A8979) or (A8989 and (not A8979));
A8989 <= A8997 and A8996;
A8990 <= A8995 and A8979;
A8991 <= A9000 and A8999;
A8992 <= A8998 and A8979;
A8993 <= A9001 or A8978;
A8994 <= (A8979 and A8991) or ((not A8979) and (not A8991));
A8995 <= (not A9004) or (not A9005);
A8996 <= ((not A8980) and A8987) or (A8980 and (not A8987));
A8997 <= A9006 and A8999;
A8998 <= (not A9008) or (not A9007);
A8999 <= A8980 or A8981;
A9000 <= A8980 or A8987;
A9001 <= A8979 and A8991;
A9002 <= (not A8978) or (not A8979);
A9003 <= A8987 and A9002;
A9004 <= (not A9003) and (not A8987);
A9005 <= A8987 or A9002;
A9006 <= (not A8980) or (not A8981);
A9007 <= A8987 or A9002;
A9008 <= (not A8987) and (not A9009);
A9009 <= A8987 and A9002;
A9010 <= B3209;
A9011 <= B3242;
A9012 <= B3275;
A9013 <= B3308;
A9014 <= B3341;
A9015 <= A9021 and A9020;
A9016 <= A9023 or A9022;
A9017 <= A9025 or A9024;
A9018 <= A9020 and A9026;
A9019 <= A9020 and A9027;
A9020 <= ((not A9010) and A9011) or (A9010 and (not A9011));
A9021 <= ((not A9022) and A9012) or (A9022 and (not A9012));
A9022 <= A9030 and A9029;
A9023 <= A9028 and A9012;
A9024 <= A9033 and A9032;
A9025 <= A9031 and A9012;
A9026 <= A9034 or A9011;
A9027 <= (A9012 and A9024) or ((not A9012) and (not A9024));
A9028 <= (not A9037) or (not A9038);
A9029 <= ((not A9013) and A9020) or (A9013 and (not A9020));
A9030 <= A9039 and A9032;
A9031 <= (not A9041) or (not A9040);
A9032 <= A9013 or A9014;
A9033 <= A9013 or A9020;
A9034 <= A9012 and A9024;
A9035 <= (not A9011) or (not A9012);
A9036 <= A9020 and A9035;
A9037 <= (not A9036) and (not A9020);
A9038 <= A9020 or A9035;
A9039 <= (not A9013) or (not A9014);
A9040 <= A9020 or A9035;
A9041 <= (not A9020) and (not A9042);
A9042 <= A9020 and A9035;
A9043 <= B3374;
A9044 <= B3407;
A9045 <= B3440;
A9046 <= B3473;
A9047 <= B3506;
A9048 <= A9054 and A9053;
A9049 <= A9056 or A9055;
A9050 <= A9058 or A9057;
A9051 <= A9053 and A9059;
A9052 <= A9053 and A9060;
A9053 <= ((not A9043) and A9044) or (A9043 and (not A9044));
A9054 <= ((not A9055) and A9045) or (A9055 and (not A9045));
A9055 <= A9063 and A9062;
A9056 <= A9061 and A9045;
A9057 <= A9066 and A9065;
A9058 <= A9064 and A9045;
A9059 <= A9067 or A9044;
A9060 <= (A9045 and A9057) or ((not A9045) and (not A9057));
A9061 <= (not A9070) or (not A9071);
A9062 <= ((not A9046) and A9053) or (A9046 and (not A9053));
A9063 <= A9072 and A9065;
A9064 <= (not A9074) or (not A9073);
A9065 <= A9046 or A9047;
A9066 <= A9046 or A9053;
A9067 <= A9045 and A9057;
A9068 <= (not A9044) or (not A9045);
A9069 <= A9053 and A9068;
A9070 <= (not A9069) and (not A9053);
A9071 <= A9053 or A9068;
A9072 <= (not A9046) or (not A9047);
A9073 <= A9053 or A9068;
A9074 <= (not A9053) and (not A9075);
A9075 <= A9053 and A9068;
A9076 <= B3539;
A9077 <= B3572;
A9078 <= B3605;
A9079 <= B3638;
A9080 <= B3671;
A9081 <= A9087 and A9086;
A9082 <= A9089 or A9088;
A9083 <= A9091 or A9090;
A9084 <= A9086 and A9092;
A9085 <= A9086 and A9093;
A9086 <= ((not A9076) and A9077) or (A9076 and (not A9077));
A9087 <= ((not A9088) and A9078) or (A9088 and (not A9078));
A9088 <= A9096 and A9095;
A9089 <= A9094 and A9078;
A9090 <= A9099 and A9098;
A9091 <= A9097 and A9078;
A9092 <= A9100 or A9077;
A9093 <= (A9078 and A9090) or ((not A9078) and (not A9090));
A9094 <= (not A9103) or (not A9104);
A9095 <= ((not A9079) and A9086) or (A9079 and (not A9086));
A9096 <= A9105 and A9098;
A9097 <= (not A9107) or (not A9106);
A9098 <= A9079 or A9080;
A9099 <= A9079 or A9086;
A9100 <= A9078 and A9090;
A9101 <= (not A9077) or (not A9078);
A9102 <= A9086 and A9101;
A9103 <= (not A9102) and (not A9086);
A9104 <= A9086 or A9101;
A9105 <= (not A9079) or (not A9080);
A9106 <= A9086 or A9101;
A9107 <= (not A9086) and (not A9108);
A9108 <= A9086 and A9101;
A9109 <= B3704;
A9110 <= B3737;
A9111 <= B3770;
A9112 <= B3803;
A9113 <= B3836;
A9114 <= A9120 and A9119;
A9115 <= A9122 or A9121;
A9116 <= A9124 or A9123;
A9117 <= A9119 and A9125;
A9118 <= A9119 and A9126;
A9119 <= ((not A9109) and A9110) or (A9109 and (not A9110));
A9120 <= ((not A9121) and A9111) or (A9121 and (not A9111));
A9121 <= A9129 and A9128;
A9122 <= A9127 and A9111;
A9123 <= A9132 and A9131;
A9124 <= A9130 and A9111;
A9125 <= A9133 or A9110;
A9126 <= (A9111 and A9123) or ((not A9111) and (not A9123));
A9127 <= (not A9136) or (not A9137);
A9128 <= ((not A9112) and A9119) or (A9112 and (not A9119));
A9129 <= A9138 and A9131;
A9130 <= (not A9140) or (not A9139);
A9131 <= A9112 or A9113;
A9132 <= A9112 or A9119;
A9133 <= A9111 and A9123;
A9134 <= (not A9110) or (not A9111);
A9135 <= A9119 and A9134;
A9136 <= (not A9135) and (not A9119);
A9137 <= A9119 or A9134;
A9138 <= (not A9112) or (not A9113);
A9139 <= A9119 or A9134;
A9140 <= (not A9119) and (not A9141);
A9141 <= A9119 and A9134;
A9142 <= B3869;
A9143 <= B3902;
A9144 <= B3935;
A9145 <= B3968;
A9146 <= B4001;
A9147 <= A9153 and A9152;
A9148 <= A9155 or A9154;
A9149 <= A9157 or A9156;
A9150 <= A9152 and A9158;
A9151 <= A9152 and A9159;
A9152 <= ((not A9142) and A9143) or (A9142 and (not A9143));
A9153 <= ((not A9154) and A9144) or (A9154 and (not A9144));
A9154 <= A9162 and A9161;
A9155 <= A9160 and A9144;
A9156 <= A9165 and A9164;
A9157 <= A9163 and A9144;
A9158 <= A9166 or A9143;
A9159 <= (A9144 and A9156) or ((not A9144) and (not A9156));
A9160 <= (not A9169) or (not A9170);
A9161 <= ((not A9145) and A9152) or (A9145 and (not A9152));
A9162 <= A9171 and A9164;
A9163 <= (not A9173) or (not A9172);
A9164 <= A9145 or A9146;
A9165 <= A9145 or A9152;
A9166 <= A9144 and A9156;
A9167 <= (not A9143) or (not A9144);
A9168 <= A9152 and A9167;
A9169 <= (not A9168) and (not A9152);
A9170 <= A9152 or A9167;
A9171 <= (not A9145) or (not A9146);
A9172 <= A9152 or A9167;
A9173 <= (not A9152) and (not A9174);
A9174 <= A9152 and A9167;
A9175 <= B4034;
A9176 <= B4067;
A9177 <= B4100;
A9178 <= B4133;
A9179 <= B4166;
A9180 <= A9186 and A9185;
A9181 <= A9188 or A9187;
A9182 <= A9190 or A9189;
A9183 <= A9185 and A9191;
A9184 <= A9185 and A9192;
A9185 <= ((not A9175) and A9176) or (A9175 and (not A9176));
A9186 <= ((not A9187) and A9177) or (A9187 and (not A9177));
A9187 <= A9195 and A9194;
A9188 <= A9193 and A9177;
A9189 <= A9198 and A9197;
A9190 <= A9196 and A9177;
A9191 <= A9199 or A9176;
A9192 <= (A9177 and A9189) or ((not A9177) and (not A9189));
A9193 <= (not A9202) or (not A9203);
A9194 <= ((not A9178) and A9185) or (A9178 and (not A9185));
A9195 <= A9204 and A9197;
A9196 <= (not A9206) or (not A9205);
A9197 <= A9178 or A9179;
A9198 <= A9178 or A9185;
A9199 <= A9177 and A9189;
A9200 <= (not A9176) or (not A9177);
A9201 <= A9185 and A9200;
A9202 <= (not A9201) and (not A9185);
A9203 <= A9185 or A9200;
A9204 <= (not A9178) or (not A9179);
A9205 <= A9185 or A9200;
A9206 <= (not A9185) and (not A9207);
A9207 <= A9185 and A9200;
A9208 <= B4199;
A9209 <= B4232;
A9210 <= B4265;
A9211 <= B4298;
A9212 <= B4331;
A9213 <= A9219 and A9218;
A9214 <= A9221 or A9220;
A9215 <= A9223 or A9222;
A9216 <= A9218 and A9224;
A9217 <= A9218 and A9225;
A9218 <= ((not A9208) and A9209) or (A9208 and (not A9209));
A9219 <= ((not A9220) and A9210) or (A9220 and (not A9210));
A9220 <= A9228 and A9227;
A9221 <= A9226 and A9210;
A9222 <= A9231 and A9230;
A9223 <= A9229 and A9210;
A9224 <= A9232 or A9209;
A9225 <= (A9210 and A9222) or ((not A9210) and (not A9222));
A9226 <= (not A9235) or (not A9236);
A9227 <= ((not A9211) and A9218) or (A9211 and (not A9218));
A9228 <= A9237 and A9230;
A9229 <= (not A9239) or (not A9238);
A9230 <= A9211 or A9212;
A9231 <= A9211 or A9218;
A9232 <= A9210 and A9222;
A9233 <= (not A9209) or (not A9210);
A9234 <= A9218 and A9233;
A9235 <= (not A9234) and (not A9218);
A9236 <= A9218 or A9233;
A9237 <= (not A9211) or (not A9212);
A9238 <= A9218 or A9233;
A9239 <= (not A9218) and (not A9240);
A9240 <= A9218 and A9233;
A9241 <= B4364;
A9242 <= B4397;
A9243 <= B4430;
A9244 <= B4463;
A9245 <= B4496;
A9246 <= A9252 and A9251;
A9247 <= A9254 or A9253;
A9248 <= A9256 or A9255;
A9249 <= A9251 and A9257;
A9250 <= A9251 and A9258;
A9251 <= ((not A9241) and A9242) or (A9241 and (not A9242));
A9252 <= ((not A9253) and A9243) or (A9253 and (not A9243));
A9253 <= A9261 and A9260;
A9254 <= A9259 and A9243;
A9255 <= A9264 and A9263;
A9256 <= A9262 and A9243;
A9257 <= A9265 or A9242;
A9258 <= (A9243 and A9255) or ((not A9243) and (not A9255));
A9259 <= (not A9268) or (not A9269);
A9260 <= ((not A9244) and A9251) or (A9244 and (not A9251));
A9261 <= A9270 and A9263;
A9262 <= (not A9272) or (not A9271);
A9263 <= A9244 or A9245;
A9264 <= A9244 or A9251;
A9265 <= A9243 and A9255;
A9266 <= (not A9242) or (not A9243);
A9267 <= A9251 and A9266;
A9268 <= (not A9267) and (not A9251);
A9269 <= A9251 or A9266;
A9270 <= (not A9244) or (not A9245);
A9271 <= A9251 or A9266;
A9272 <= (not A9251) and (not A9273);
A9273 <= A9251 and A9266;
A9274 <= B4529;
A9275 <= B4562;
A9276 <= B4595;
A9277 <= B4628;
A9278 <= B4661;
A9279 <= A9285 and A9284;
A9280 <= A9287 or A9286;
A9281 <= A9289 or A9288;
A9282 <= A9284 and A9290;
A9283 <= A9284 and A9291;
A9284 <= ((not A9274) and A9275) or (A9274 and (not A9275));
A9285 <= ((not A9286) and A9276) or (A9286 and (not A9276));
A9286 <= A9294 and A9293;
A9287 <= A9292 and A9276;
A9288 <= A9297 and A9296;
A9289 <= A9295 and A9276;
A9290 <= A9298 or A9275;
A9291 <= (A9276 and A9288) or ((not A9276) and (not A9288));
A9292 <= (not A9301) or (not A9302);
A9293 <= ((not A9277) and A9284) or (A9277 and (not A9284));
A9294 <= A9303 and A9296;
A9295 <= (not A9305) or (not A9304);
A9296 <= A9277 or A9278;
A9297 <= A9277 or A9284;
A9298 <= A9276 and A9288;
A9299 <= (not A9275) or (not A9276);
A9300 <= A9284 and A9299;
A9301 <= (not A9300) and (not A9284);
A9302 <= A9284 or A9299;
A9303 <= (not A9277) or (not A9278);
A9304 <= A9284 or A9299;
A9305 <= (not A9284) and (not A9306);
A9306 <= A9284 and A9299;
A9307 <= B4694;
A9308 <= B4727;
A9309 <= B4760;
A9310 <= B4793;
A9311 <= B4826;
A9312 <= A9318 and A9317;
A9313 <= A9320 or A9319;
A9314 <= A9322 or A9321;
A9315 <= A9317 and A9323;
A9316 <= A9317 and A9324;
A9317 <= ((not A9307) and A9308) or (A9307 and (not A9308));
A9318 <= ((not A9319) and A9309) or (A9319 and (not A9309));
A9319 <= A9327 and A9326;
A9320 <= A9325 and A9309;
A9321 <= A9330 and A9329;
A9322 <= A9328 and A9309;
A9323 <= A9331 or A9308;
A9324 <= (A9309 and A9321) or ((not A9309) and (not A9321));
A9325 <= (not A9334) or (not A9335);
A9326 <= ((not A9310) and A9317) or (A9310 and (not A9317));
A9327 <= A9336 and A9329;
A9328 <= (not A9338) or (not A9337);
A9329 <= A9310 or A9311;
A9330 <= A9310 or A9317;
A9331 <= A9309 and A9321;
A9332 <= (not A9308) or (not A9309);
A9333 <= A9317 and A9332;
A9334 <= (not A9333) and (not A9317);
A9335 <= A9317 or A9332;
A9336 <= (not A9310) or (not A9311);
A9337 <= A9317 or A9332;
A9338 <= (not A9317) and (not A9339);
A9339 <= A9317 and A9332;
A9340 <= B4859;
A9341 <= B4892;
A9342 <= B4925;
A9343 <= B4958;
A9344 <= B4991;
A9345 <= A9351 and A9350;
A9346 <= A9353 or A9352;
A9347 <= A9355 or A9354;
A9348 <= A9350 and A9356;
A9349 <= A9350 and A9357;
A9350 <= ((not A9340) and A9341) or (A9340 and (not A9341));
A9351 <= ((not A9352) and A9342) or (A9352 and (not A9342));
A9352 <= A9360 and A9359;
A9353 <= A9358 and A9342;
A9354 <= A9363 and A9362;
A9355 <= A9361 and A9342;
A9356 <= A9364 or A9341;
A9357 <= (A9342 and A9354) or ((not A9342) and (not A9354));
A9358 <= (not A9367) or (not A9368);
A9359 <= ((not A9343) and A9350) or (A9343 and (not A9350));
A9360 <= A9369 and A9362;
A9361 <= (not A9371) or (not A9370);
A9362 <= A9343 or A9344;
A9363 <= A9343 or A9350;
A9364 <= A9342 and A9354;
A9365 <= (not A9341) or (not A9342);
A9366 <= A9350 and A9365;
A9367 <= (not A9366) and (not A9350);
A9368 <= A9350 or A9365;
A9369 <= (not A9343) or (not A9344);
A9370 <= A9350 or A9365;
A9371 <= (not A9350) and (not A9372);
A9372 <= A9350 and A9365;
A9373 <= B5024;
A9374 <= B5057;
A9375 <= B5090;
A9376 <= B5123;
A9377 <= B5156;
A9378 <= A9384 and A9383;
A9379 <= A9386 or A9385;
A9380 <= A9388 or A9387;
A9381 <= A9383 and A9389;
A9382 <= A9383 and A9390;
A9383 <= ((not A9373) and A9374) or (A9373 and (not A9374));
A9384 <= ((not A9385) and A9375) or (A9385 and (not A9375));
A9385 <= A9393 and A9392;
A9386 <= A9391 and A9375;
A9387 <= A9396 and A9395;
A9388 <= A9394 and A9375;
A9389 <= A9397 or A9374;
A9390 <= (A9375 and A9387) or ((not A9375) and (not A9387));
A9391 <= (not A9400) or (not A9401);
A9392 <= ((not A9376) and A9383) or (A9376 and (not A9383));
A9393 <= A9402 and A9395;
A9394 <= (not A9404) or (not A9403);
A9395 <= A9376 or A9377;
A9396 <= A9376 or A9383;
A9397 <= A9375 and A9387;
A9398 <= (not A9374) or (not A9375);
A9399 <= A9383 and A9398;
A9400 <= (not A9399) and (not A9383);
A9401 <= A9383 or A9398;
A9402 <= (not A9376) or (not A9377);
A9403 <= A9383 or A9398;
A9404 <= (not A9383) and (not A9405);
A9405 <= A9383 and A9398;
A9406 <= B1063;
A9407 <= B1098;
A9408 <= B1131;
A9409 <= B1164;
A9410 <= B1197;
A9411 <= A9417 and A9416;
A9412 <= A9419 or A9418;
A9413 <= A9421 or A9420;
A9414 <= A9416 and A9422;
A9415 <= A9416 and A9423;
A9416 <= ((not A9406) and A9407) or (A9406 and (not A9407));
A9417 <= ((not A9418) and A9408) or (A9418 and (not A9408));
A9418 <= A9426 and A9425;
A9419 <= A9424 and A9408;
A9420 <= A9429 and A9428;
A9421 <= A9427 and A9408;
A9422 <= A9430 or A9407;
A9423 <= (A9408 and A9420) or ((not A9408) and (not A9420));
A9424 <= (not A9433) or (not A9434);
A9425 <= ((not A9409) and A9416) or (A9409 and (not A9416));
A9426 <= A9435 and A9428;
A9427 <= (not A9437) or (not A9436);
A9428 <= A9409 or A9410;
A9429 <= A9409 or A9416;
A9430 <= A9408 and A9420;
A9431 <= (not A9407) or (not A9408);
A9432 <= A9416 and A9431;
A9433 <= (not A9432) and (not A9416);
A9434 <= A9416 or A9431;
A9435 <= (not A9409) or (not A9410);
A9436 <= A9416 or A9431;
A9437 <= (not A9416) and (not A9438);
A9438 <= A9416 and A9431;
A9439 <= B1230;
A9440 <= B1263;
A9441 <= B1296;
A9442 <= B1329;
A9443 <= B1362;
A9444 <= A9450 and A9449;
A9445 <= A9452 or A9451;
A9446 <= A9454 or A9453;
A9447 <= A9449 and A9455;
A9448 <= A9449 and A9456;
A9449 <= ((not A9439) and A9440) or (A9439 and (not A9440));
A9450 <= ((not A9451) and A9441) or (A9451 and (not A9441));
A9451 <= A9459 and A9458;
A9452 <= A9457 and A9441;
A9453 <= A9462 and A9461;
A9454 <= A9460 and A9441;
A9455 <= A9463 or A9440;
A9456 <= (A9441 and A9453) or ((not A9441) and (not A9453));
A9457 <= (not A9466) or (not A9467);
A9458 <= ((not A9442) and A9449) or (A9442 and (not A9449));
A9459 <= A9468 and A9461;
A9460 <= (not A9470) or (not A9469);
A9461 <= A9442 or A9443;
A9462 <= A9442 or A9449;
A9463 <= A9441 and A9453;
A9464 <= (not A9440) or (not A9441);
A9465 <= A9449 and A9464;
A9466 <= (not A9465) and (not A9449);
A9467 <= A9449 or A9464;
A9468 <= (not A9442) or (not A9443);
A9469 <= A9449 or A9464;
A9470 <= (not A9449) and (not A9471);
A9471 <= A9449 and A9464;
A9472 <= B1395;
A9473 <= B1428;
A9474 <= B1461;
A9475 <= B1494;
A9476 <= B1527;
A9477 <= A9483 and A9482;
A9478 <= A9485 or A9484;
A9479 <= A9487 or A9486;
A9480 <= A9482 and A9488;
A9481 <= A9482 and A9489;
A9482 <= ((not A9472) and A9473) or (A9472 and (not A9473));
A9483 <= ((not A9484) and A9474) or (A9484 and (not A9474));
A9484 <= A9492 and A9491;
A9485 <= A9490 and A9474;
A9486 <= A9495 and A9494;
A9487 <= A9493 and A9474;
A9488 <= A9496 or A9473;
A9489 <= (A9474 and A9486) or ((not A9474) and (not A9486));
A9490 <= (not A9499) or (not A9500);
A9491 <= ((not A9475) and A9482) or (A9475 and (not A9482));
A9492 <= A9501 and A9494;
A9493 <= (not A9503) or (not A9502);
A9494 <= A9475 or A9476;
A9495 <= A9475 or A9482;
A9496 <= A9474 and A9486;
A9497 <= (not A9473) or (not A9474);
A9498 <= A9482 and A9497;
A9499 <= (not A9498) and (not A9482);
A9500 <= A9482 or A9497;
A9501 <= (not A9475) or (not A9476);
A9502 <= A9482 or A9497;
A9503 <= (not A9482) and (not A9504);
A9504 <= A9482 and A9497;
A9505 <= B1560;
A9506 <= B1593;
A9507 <= B1626;
A9508 <= B1659;
A9509 <= B1692;
A9510 <= A9516 and A9515;
A9511 <= A9518 or A9517;
A9512 <= A9520 or A9519;
A9513 <= A9515 and A9521;
A9514 <= A9515 and A9522;
A9515 <= ((not A9505) and A9506) or (A9505 and (not A9506));
A9516 <= ((not A9517) and A9507) or (A9517 and (not A9507));
A9517 <= A9525 and A9524;
A9518 <= A9523 and A9507;
A9519 <= A9528 and A9527;
A9520 <= A9526 and A9507;
A9521 <= A9529 or A9506;
A9522 <= (A9507 and A9519) or ((not A9507) and (not A9519));
A9523 <= (not A9532) or (not A9533);
A9524 <= ((not A9508) and A9515) or (A9508 and (not A9515));
A9525 <= A9534 and A9527;
A9526 <= (not A9536) or (not A9535);
A9527 <= A9508 or A9509;
A9528 <= A9508 or A9515;
A9529 <= A9507 and A9519;
A9530 <= (not A9506) or (not A9507);
A9531 <= A9515 and A9530;
A9532 <= (not A9531) and (not A9515);
A9533 <= A9515 or A9530;
A9534 <= (not A9508) or (not A9509);
A9535 <= A9515 or A9530;
A9536 <= (not A9515) and (not A9537);
A9537 <= A9515 and A9530;
A9538 <= B1725;
A9539 <= B1758;
A9540 <= B1791;
A9541 <= B1824;
A9542 <= B1857;
A9543 <= A9549 and A9548;
A9544 <= A9551 or A9550;
A9545 <= A9553 or A9552;
A9546 <= A9548 and A9554;
A9547 <= A9548 and A9555;
A9548 <= ((not A9538) and A9539) or (A9538 and (not A9539));
A9549 <= ((not A9550) and A9540) or (A9550 and (not A9540));
A9550 <= A9558 and A9557;
A9551 <= A9556 and A9540;
A9552 <= A9561 and A9560;
A9553 <= A9559 and A9540;
A9554 <= A9562 or A9539;
A9555 <= (A9540 and A9552) or ((not A9540) and (not A9552));
A9556 <= (not A9565) or (not A9566);
A9557 <= ((not A9541) and A9548) or (A9541 and (not A9548));
A9558 <= A9567 and A9560;
A9559 <= (not A9569) or (not A9568);
A9560 <= A9541 or A9542;
A9561 <= A9541 or A9548;
A9562 <= A9540 and A9552;
A9563 <= (not A9539) or (not A9540);
A9564 <= A9548 and A9563;
A9565 <= (not A9564) and (not A9548);
A9566 <= A9548 or A9563;
A9567 <= (not A9541) or (not A9542);
A9568 <= A9548 or A9563;
A9569 <= (not A9548) and (not A9570);
A9570 <= A9548 and A9563;
A9571 <= B1890;
A9572 <= B1923;
A9573 <= B1956;
A9574 <= B1989;
A9575 <= B2022;
A9576 <= A9582 and A9581;
A9577 <= A9584 or A9583;
A9578 <= A9586 or A9585;
A9579 <= A9581 and A9587;
A9580 <= A9581 and A9588;
A9581 <= ((not A9571) and A9572) or (A9571 and (not A9572));
A9582 <= ((not A9583) and A9573) or (A9583 and (not A9573));
A9583 <= A9591 and A9590;
A9584 <= A9589 and A9573;
A9585 <= A9594 and A9593;
A9586 <= A9592 and A9573;
A9587 <= A9595 or A9572;
A9588 <= (A9573 and A9585) or ((not A9573) and (not A9585));
A9589 <= (not A9598) or (not A9599);
A9590 <= ((not A9574) and A9581) or (A9574 and (not A9581));
A9591 <= A9600 and A9593;
A9592 <= (not A9602) or (not A9601);
A9593 <= A9574 or A9575;
A9594 <= A9574 or A9581;
A9595 <= A9573 and A9585;
A9596 <= (not A9572) or (not A9573);
A9597 <= A9581 and A9596;
A9598 <= (not A9597) and (not A9581);
A9599 <= A9581 or A9596;
A9600 <= (not A9574) or (not A9575);
A9601 <= A9581 or A9596;
A9602 <= (not A9581) and (not A9603);
A9603 <= A9581 and A9596;
A9604 <= B2055;
A9605 <= B2088;
A9606 <= B2121;
A9607 <= B2154;
A9608 <= B2187;
A9609 <= A9615 and A9614;
A9610 <= A9617 or A9616;
A9611 <= A9619 or A9618;
A9612 <= A9614 and A9620;
A9613 <= A9614 and A9621;
A9614 <= ((not A9604) and A9605) or (A9604 and (not A9605));
A9615 <= ((not A9616) and A9606) or (A9616 and (not A9606));
A9616 <= A9624 and A9623;
A9617 <= A9622 and A9606;
A9618 <= A9627 and A9626;
A9619 <= A9625 and A9606;
A9620 <= A9628 or A9605;
A9621 <= (A9606 and A9618) or ((not A9606) and (not A9618));
A9622 <= (not A9631) or (not A9632);
A9623 <= ((not A9607) and A9614) or (A9607 and (not A9614));
A9624 <= A9633 and A9626;
A9625 <= (not A9635) or (not A9634);
A9626 <= A9607 or A9608;
A9627 <= A9607 or A9614;
A9628 <= A9606 and A9618;
A9629 <= (not A9605) or (not A9606);
A9630 <= A9614 and A9629;
A9631 <= (not A9630) and (not A9614);
A9632 <= A9614 or A9629;
A9633 <= (not A9607) or (not A9608);
A9634 <= A9614 or A9629;
A9635 <= (not A9614) and (not A9636);
A9636 <= A9614 and A9629;
A9637 <= B2220;
A9638 <= B2253;
A9639 <= B2286;
A9640 <= B2319;
A9641 <= B2352;
A9642 <= A9648 and A9647;
A9643 <= A9650 or A9649;
A9644 <= A9652 or A9651;
A9645 <= A9647 and A9653;
A9646 <= A9647 and A9654;
A9647 <= ((not A9637) and A9638) or (A9637 and (not A9638));
A9648 <= ((not A9649) and A9639) or (A9649 and (not A9639));
A9649 <= A9657 and A9656;
A9650 <= A9655 and A9639;
A9651 <= A9660 and A9659;
A9652 <= A9658 and A9639;
A9653 <= A9661 or A9638;
A9654 <= (A9639 and A9651) or ((not A9639) and (not A9651));
A9655 <= (not A9664) or (not A9665);
A9656 <= ((not A9640) and A9647) or (A9640 and (not A9647));
A9657 <= A9666 and A9659;
A9658 <= (not A9668) or (not A9667);
A9659 <= A9640 or A9641;
A9660 <= A9640 or A9647;
A9661 <= A9639 and A9651;
A9662 <= (not A9638) or (not A9639);
A9663 <= A9647 and A9662;
A9664 <= (not A9663) and (not A9647);
A9665 <= A9647 or A9662;
A9666 <= (not A9640) or (not A9641);
A9667 <= A9647 or A9662;
A9668 <= (not A9647) and (not A9669);
A9669 <= A9647 and A9662;
A9670 <= B2385;
A9671 <= B2418;
A9672 <= B2451;
A9673 <= B2484;
A9674 <= B2517;
A9675 <= A9681 and A9680;
A9676 <= A9683 or A9682;
A9677 <= A9685 or A9684;
A9678 <= A9680 and A9686;
A9679 <= A9680 and A9687;
A9680 <= ((not A9670) and A9671) or (A9670 and (not A9671));
A9681 <= ((not A9682) and A9672) or (A9682 and (not A9672));
A9682 <= A9690 and A9689;
A9683 <= A9688 and A9672;
A9684 <= A9693 and A9692;
A9685 <= A9691 and A9672;
A9686 <= A9694 or A9671;
A9687 <= (A9672 and A9684) or ((not A9672) and (not A9684));
A9688 <= (not A9697) or (not A9698);
A9689 <= ((not A9673) and A9680) or (A9673 and (not A9680));
A9690 <= A9699 and A9692;
A9691 <= (not A9701) or (not A9700);
A9692 <= A9673 or A9674;
A9693 <= A9673 or A9680;
A9694 <= A9672 and A9684;
A9695 <= (not A9671) or (not A9672);
A9696 <= A9680 and A9695;
A9697 <= (not A9696) and (not A9680);
A9698 <= A9680 or A9695;
A9699 <= (not A9673) or (not A9674);
A9700 <= A9680 or A9695;
A9701 <= (not A9680) and (not A9702);
A9702 <= A9680 and A9695;
A9703 <= B2550;
A9704 <= B2583;
A9705 <= B2616;
A9706 <= B2649;
A9707 <= B2682;
A9708 <= A9714 and A9713;
A9709 <= A9716 or A9715;
A9710 <= A9718 or A9717;
A9711 <= A9713 and A9719;
A9712 <= A9713 and A9720;
A9713 <= ((not A9703) and A9704) or (A9703 and (not A9704));
A9714 <= ((not A9715) and A9705) or (A9715 and (not A9705));
A9715 <= A9723 and A9722;
A9716 <= A9721 and A9705;
A9717 <= A9726 and A9725;
A9718 <= A9724 and A9705;
A9719 <= A9727 or A9704;
A9720 <= (A9705 and A9717) or ((not A9705) and (not A9717));
A9721 <= (not A9730) or (not A9731);
A9722 <= ((not A9706) and A9713) or (A9706 and (not A9713));
A9723 <= A9732 and A9725;
A9724 <= (not A9734) or (not A9733);
A9725 <= A9706 or A9707;
A9726 <= A9706 or A9713;
A9727 <= A9705 and A9717;
A9728 <= (not A9704) or (not A9705);
A9729 <= A9713 and A9728;
A9730 <= (not A9729) and (not A9713);
A9731 <= A9713 or A9728;
A9732 <= (not A9706) or (not A9707);
A9733 <= A9713 or A9728;
A9734 <= (not A9713) and (not A9735);
A9735 <= A9713 and A9728;
A9736 <= B2715;
A9737 <= B2748;
A9738 <= B2781;
A9739 <= B2814;
A9740 <= B2847;
A9741 <= A9747 and A9746;
A9742 <= A9749 or A9748;
A9743 <= A9751 or A9750;
A9744 <= A9746 and A9752;
A9745 <= A9746 and A9753;
A9746 <= ((not A9736) and A9737) or (A9736 and (not A9737));
A9747 <= ((not A9748) and A9738) or (A9748 and (not A9738));
A9748 <= A9756 and A9755;
A9749 <= A9754 and A9738;
A9750 <= A9759 and A9758;
A9751 <= A9757 and A9738;
A9752 <= A9760 or A9737;
A9753 <= (A9738 and A9750) or ((not A9738) and (not A9750));
A9754 <= (not A9763) or (not A9764);
A9755 <= ((not A9739) and A9746) or (A9739 and (not A9746));
A9756 <= A9765 and A9758;
A9757 <= (not A9767) or (not A9766);
A9758 <= A9739 or A9740;
A9759 <= A9739 or A9746;
A9760 <= A9738 and A9750;
A9761 <= (not A9737) or (not A9738);
A9762 <= A9746 and A9761;
A9763 <= (not A9762) and (not A9746);
A9764 <= A9746 or A9761;
A9765 <= (not A9739) or (not A9740);
A9766 <= A9746 or A9761;
A9767 <= (not A9746) and (not A9768);
A9768 <= A9746 and A9761;
A9769 <= B2880;
A9770 <= B2913;
A9771 <= B2946;
A9772 <= B2979;
A9773 <= B3012;
A9774 <= A9780 and A9779;
A9775 <= A9782 or A9781;
A9776 <= A9784 or A9783;
A9777 <= A9779 and A9785;
A9778 <= A9779 and A9786;
A9779 <= ((not A9769) and A9770) or (A9769 and (not A9770));
A9780 <= ((not A9781) and A9771) or (A9781 and (not A9771));
A9781 <= A9789 and A9788;
A9782 <= A9787 and A9771;
A9783 <= A9792 and A9791;
A9784 <= A9790 and A9771;
A9785 <= A9793 or A9770;
A9786 <= (A9771 and A9783) or ((not A9771) and (not A9783));
A9787 <= (not A9796) or (not A9797);
A9788 <= ((not A9772) and A9779) or (A9772 and (not A9779));
A9789 <= A9798 and A9791;
A9790 <= (not A9800) or (not A9799);
A9791 <= A9772 or A9773;
A9792 <= A9772 or A9779;
A9793 <= A9771 and A9783;
A9794 <= (not A9770) or (not A9771);
A9795 <= A9779 and A9794;
A9796 <= (not A9795) and (not A9779);
A9797 <= A9779 or A9794;
A9798 <= (not A9772) or (not A9773);
A9799 <= A9779 or A9794;
A9800 <= (not A9779) and (not A9801);
A9801 <= A9779 and A9794;
A9802 <= B3045;
A9803 <= B3078;
A9804 <= B3111;
A9805 <= B3144;
A9806 <= B3177;
A9807 <= A9813 and A9812;
A9808 <= A9815 or A9814;
A9809 <= A9817 or A9816;
A9810 <= A9812 and A9818;
A9811 <= A9812 and A9819;
A9812 <= ((not A9802) and A9803) or (A9802 and (not A9803));
A9813 <= ((not A9814) and A9804) or (A9814 and (not A9804));
A9814 <= A9822 and A9821;
A9815 <= A9820 and A9804;
A9816 <= A9825 and A9824;
A9817 <= A9823 and A9804;
A9818 <= A9826 or A9803;
A9819 <= (A9804 and A9816) or ((not A9804) and (not A9816));
A9820 <= (not A9829) or (not A9830);
A9821 <= ((not A9805) and A9812) or (A9805 and (not A9812));
A9822 <= A9831 and A9824;
A9823 <= (not A9833) or (not A9832);
A9824 <= A9805 or A9806;
A9825 <= A9805 or A9812;
A9826 <= A9804 and A9816;
A9827 <= (not A9803) or (not A9804);
A9828 <= A9812 and A9827;
A9829 <= (not A9828) and (not A9812);
A9830 <= A9812 or A9827;
A9831 <= (not A9805) or (not A9806);
A9832 <= A9812 or A9827;
A9833 <= (not A9812) and (not A9834);
A9834 <= A9812 and A9827;
A9835 <= B3210;
A9836 <= B3243;
A9837 <= B3276;
A9838 <= B3309;
A9839 <= B3342;
A9840 <= A9846 and A9845;
A9841 <= A9848 or A9847;
A9842 <= A9850 or A9849;
A9843 <= A9845 and A9851;
A9844 <= A9845 and A9852;
A9845 <= ((not A9835) and A9836) or (A9835 and (not A9836));
A9846 <= ((not A9847) and A9837) or (A9847 and (not A9837));
A9847 <= A9855 and A9854;
A9848 <= A9853 and A9837;
A9849 <= A9858 and A9857;
A9850 <= A9856 and A9837;
A9851 <= A9859 or A9836;
A9852 <= (A9837 and A9849) or ((not A9837) and (not A9849));
A9853 <= (not A9862) or (not A9863);
A9854 <= ((not A9838) and A9845) or (A9838 and (not A9845));
A9855 <= A9864 and A9857;
A9856 <= (not A9866) or (not A9865);
A9857 <= A9838 or A9839;
A9858 <= A9838 or A9845;
A9859 <= A9837 and A9849;
A9860 <= (not A9836) or (not A9837);
A9861 <= A9845 and A9860;
A9862 <= (not A9861) and (not A9845);
A9863 <= A9845 or A9860;
A9864 <= (not A9838) or (not A9839);
A9865 <= A9845 or A9860;
A9866 <= (not A9845) and (not A9867);
A9867 <= A9845 and A9860;
A9868 <= B3375;
A9869 <= B3408;
A9870 <= B3441;
A9871 <= B3474;
A9872 <= B3507;
A9873 <= A9879 and A9878;
A9874 <= A9881 or A9880;
A9875 <= A9883 or A9882;
A9876 <= A9878 and A9884;
A9877 <= A9878 and A9885;
A9878 <= ((not A9868) and A9869) or (A9868 and (not A9869));
A9879 <= ((not A9880) and A9870) or (A9880 and (not A9870));
A9880 <= A9888 and A9887;
A9881 <= A9886 and A9870;
A9882 <= A9891 and A9890;
A9883 <= A9889 and A9870;
A9884 <= A9892 or A9869;
A9885 <= (A9870 and A9882) or ((not A9870) and (not A9882));
A9886 <= (not A9895) or (not A9896);
A9887 <= ((not A9871) and A9878) or (A9871 and (not A9878));
A9888 <= A9897 and A9890;
A9889 <= (not A9899) or (not A9898);
A9890 <= A9871 or A9872;
A9891 <= A9871 or A9878;
A9892 <= A9870 and A9882;
A9893 <= (not A9869) or (not A9870);
A9894 <= A9878 and A9893;
A9895 <= (not A9894) and (not A9878);
A9896 <= A9878 or A9893;
A9897 <= (not A9871) or (not A9872);
A9898 <= A9878 or A9893;
A9899 <= (not A9878) and (not A9900);
A9900 <= A9878 and A9893;
A9901 <= B3540;
A9902 <= B3573;
A9903 <= B3606;
A9904 <= B3639;
A9905 <= B3672;
A9906 <= A9912 and A9911;
A9907 <= A9914 or A9913;
A9908 <= A9916 or A9915;
A9909 <= A9911 and A9917;
A9910 <= A9911 and A9918;
A9911 <= ((not A9901) and A9902) or (A9901 and (not A9902));
A9912 <= ((not A9913) and A9903) or (A9913 and (not A9903));
A9913 <= A9921 and A9920;
A9914 <= A9919 and A9903;
A9915 <= A9924 and A9923;
A9916 <= A9922 and A9903;
A9917 <= A9925 or A9902;
A9918 <= (A9903 and A9915) or ((not A9903) and (not A9915));
A9919 <= (not A9928) or (not A9929);
A9920 <= ((not A9904) and A9911) or (A9904 and (not A9911));
A9921 <= A9930 and A9923;
A9922 <= (not A9932) or (not A9931);
A9923 <= A9904 or A9905;
A9924 <= A9904 or A9911;
A9925 <= A9903 and A9915;
A9926 <= (not A9902) or (not A9903);
A9927 <= A9911 and A9926;
A9928 <= (not A9927) and (not A9911);
A9929 <= A9911 or A9926;
A9930 <= (not A9904) or (not A9905);
A9931 <= A9911 or A9926;
A9932 <= (not A9911) and (not A9933);
A9933 <= A9911 and A9926;
A9934 <= B3705;
A9935 <= B3738;
A9936 <= B3771;
A9937 <= B3804;
A9938 <= B3837;
A9939 <= A9945 and A9944;
A9940 <= A9947 or A9946;
A9941 <= A9949 or A9948;
A9942 <= A9944 and A9950;
A9943 <= A9944 and A9951;
A9944 <= ((not A9934) and A9935) or (A9934 and (not A9935));
A9945 <= ((not A9946) and A9936) or (A9946 and (not A9936));
A9946 <= A9954 and A9953;
A9947 <= A9952 and A9936;
A9948 <= A9957 and A9956;
A9949 <= A9955 and A9936;
A9950 <= A9958 or A9935;
A9951 <= (A9936 and A9948) or ((not A9936) and (not A9948));
A9952 <= (not A9961) or (not A9962);
A9953 <= ((not A9937) and A9944) or (A9937 and (not A9944));
A9954 <= A9963 and A9956;
A9955 <= (not A9965) or (not A9964);
A9956 <= A9937 or A9938;
A9957 <= A9937 or A9944;
A9958 <= A9936 and A9948;
A9959 <= (not A9935) or (not A9936);
A9960 <= A9944 and A9959;
A9961 <= (not A9960) and (not A9944);
A9962 <= A9944 or A9959;
A9963 <= (not A9937) or (not A9938);
A9964 <= A9944 or A9959;
A9965 <= (not A9944) and (not A9966);
A9966 <= A9944 and A9959;
A9967 <= B3870;
A9968 <= B3903;
A9969 <= B3936;
A9970 <= B3969;
A9971 <= B4002;
A9972 <= A9978 and A9977;
A9973 <= A9980 or A9979;
A9974 <= A9982 or A9981;
A9975 <= A9977 and A9983;
A9976 <= A9977 and A9984;
A9977 <= ((not A9967) and A9968) or (A9967 and (not A9968));
A9978 <= ((not A9979) and A9969) or (A9979 and (not A9969));
A9979 <= A9987 and A9986;
A9980 <= A9985 and A9969;
A9981 <= A9990 and A9989;
A9982 <= A9988 and A9969;
A9983 <= A9991 or A9968;
A9984 <= (A9969 and A9981) or ((not A9969) and (not A9981));
A9985 <= (not A9994) or (not A9995);
A9986 <= ((not A9970) and A9977) or (A9970 and (not A9977));
A9987 <= A9996 and A9989;
A9988 <= (not A9998) or (not A9997);
A9989 <= A9970 or A9971;
A9990 <= A9970 or A9977;
A9991 <= A9969 and A9981;
A9992 <= (not A9968) or (not A9969);
A9993 <= A9977 and A9992;
A9994 <= (not A9993) and (not A9977);
A9995 <= A9977 or A9992;
A9996 <= (not A9970) or (not A9971);
A9997 <= A9977 or A9992;
A9998 <= (not A9977) and (not A9999);
A9999 <= A9977 and A9992;
B1 <= B4035;
B2 <= B4068;
B3 <= B4101;
B4 <= B4134;
B5 <= B4167;
B6 <= B12 and B11;
B7 <= B14 or B13;
B8 <= B16 or B15;
B9 <= B11 and B17;
B10 <= B11 and B18;
B11 <= ((not B1) and B2) or (B1 and (not B2));
B12 <= ((not B13) and B3) or (B13 and (not B3));
B13 <= B21 and B20;
B14 <= B19 and B3;
B15 <= B24 and B23;
B16 <= B22 and B3;
B17 <= B25 or B2;
B18 <= (B3 and B15) or ((not B3) and (not B15));
B19 <= (not B28) or (not B29);
B20 <= ((not B4) and B11) or (B4 and (not B11));
B21 <= B30 and B23;
B22 <= (not B32) or (not B31);
B23 <= B4 or B5;
B24 <= B4 or B11;
B25 <= B3 and B15;
B26 <= (not B2) or (not B3);
B27 <= B11 and B26;
B28 <= (not B27) and (not B11);
B29 <= B11 or B26;
B30 <= (not B4) or (not B5);
B31 <= B11 or B26;
B32 <= (not B11) and (not B33);
B33 <= B11 and B26;
B34 <= B4200;
B35 <= B4233;
B36 <= B4266;
B37 <= B4299;
B38 <= B4332;
B39 <= B45 and B44;
B40 <= B47 or B46;
B41 <= B49 or B48;
B42 <= B44 and B50;
B43 <= B44 and B51;
B44 <= ((not B34) and B35) or (B34 and (not B35));
B45 <= ((not B46) and B36) or (B46 and (not B36));
B46 <= B54 and B53;
B47 <= B52 and B36;
B48 <= B57 and B56;
B49 <= B55 and B36;
B50 <= B58 or B35;
B51 <= (B36 and B48) or ((not B36) and (not B48));
B52 <= (not B61) or (not B62);
B53 <= ((not B37) and B44) or (B37 and (not B44));
B54 <= B63 and B56;
B55 <= (not B65) or (not B64);
B56 <= B37 or B38;
B57 <= B37 or B44;
B58 <= B36 and B48;
B59 <= (not B35) or (not B36);
B60 <= B44 and B59;
B61 <= (not B60) and (not B44);
B62 <= B44 or B59;
B63 <= (not B37) or (not B38);
B64 <= B44 or B59;
B65 <= (not B44) and (not B66);
B66 <= B44 and B59;
B67 <= B4365;
B68 <= B4398;
B69 <= B4431;
B70 <= B4464;
B71 <= B4497;
B72 <= B78 and B77;
B73 <= B80 or B79;
B74 <= B82 or B81;
B75 <= B77 and B83;
B76 <= B77 and B84;
B77 <= ((not B67) and B68) or (B67 and (not B68));
B78 <= ((not B79) and B69) or (B79 and (not B69));
B79 <= B87 and B86;
B80 <= B85 and B69;
B81 <= B90 and B89;
B82 <= B88 and B69;
B83 <= B91 or B68;
B84 <= (B69 and B81) or ((not B69) and (not B81));
B85 <= (not B94) or (not B95);
B86 <= ((not B70) and B77) or (B70 and (not B77));
B87 <= B96 and B89;
B88 <= (not B98) or (not B97);
B89 <= B70 or B71;
B90 <= B70 or B77;
B91 <= B69 and B81;
B92 <= (not B68) or (not B69);
B93 <= B77 and B92;
B94 <= (not B93) and (not B77);
B95 <= B77 or B92;
B96 <= (not B70) or (not B71);
B97 <= B77 or B92;
B98 <= (not B77) and (not B99);
B99 <= B77 and B92;
B100 <= B4530;
B101 <= B4563;
B102 <= B4596;
B103 <= B4629;
B104 <= B4662;
B105 <= B111 and B110;
B106 <= B113 or B112;
B107 <= B115 or B114;
B108 <= B110 and B116;
B109 <= B110 and B117;
B110 <= ((not B100) and B101) or (B100 and (not B101));
B111 <= ((not B112) and B102) or (B112 and (not B102));
B112 <= B120 and B119;
B113 <= B118 and B102;
B114 <= B123 and B122;
B115 <= B121 and B102;
B116 <= B124 or B101;
B117 <= (B102 and B114) or ((not B102) and (not B114));
B118 <= (not B127) or (not B128);
B119 <= ((not B103) and B110) or (B103 and (not B110));
B120 <= B129 and B122;
B121 <= (not B131) or (not B130);
B122 <= B103 or B104;
B123 <= B103 or B110;
B124 <= B102 and B114;
B125 <= (not B101) or (not B102);
B126 <= B110 and B125;
B127 <= (not B126) and (not B110);
B128 <= B110 or B125;
B129 <= (not B103) or (not B104);
B130 <= B110 or B125;
B131 <= (not B110) and (not B132);
B132 <= B110 and B125;
B133 <= B4695;
B134 <= B4728;
B135 <= B4761;
B136 <= B4794;
B137 <= B4827;
B138 <= B144 and B143;
B139 <= B146 or B145;
B140 <= B148 or B147;
B141 <= B143 and B149;
B142 <= B143 and B150;
B143 <= ((not B133) and B134) or (B133 and (not B134));
B144 <= ((not B145) and B135) or (B145 and (not B135));
B145 <= B153 and B152;
B146 <= B151 and B135;
B147 <= B156 and B155;
B148 <= B154 and B135;
B149 <= B157 or B134;
B150 <= (B135 and B147) or ((not B135) and (not B147));
B151 <= (not B160) or (not B161);
B152 <= ((not B136) and B143) or (B136 and (not B143));
B153 <= B162 and B155;
B154 <= (not B164) or (not B163);
B155 <= B136 or B137;
B156 <= B136 or B143;
B157 <= B135 and B147;
B158 <= (not B134) or (not B135);
B159 <= B143 and B158;
B160 <= (not B159) and (not B143);
B161 <= B143 or B158;
B162 <= (not B136) or (not B137);
B163 <= B143 or B158;
B164 <= (not B143) and (not B165);
B165 <= B143 and B158;
B166 <= B4860;
B167 <= B4893;
B168 <= B4926;
B169 <= B4959;
B170 <= B4992;
B171 <= B177 and B176;
B172 <= B179 or B178;
B173 <= B181 or B180;
B174 <= B176 and B182;
B175 <= B176 and B183;
B176 <= ((not B166) and B167) or (B166 and (not B167));
B177 <= ((not B178) and B168) or (B178 and (not B168));
B178 <= B186 and B185;
B179 <= B184 and B168;
B180 <= B189 and B188;
B181 <= B187 and B168;
B182 <= B190 or B167;
B183 <= (B168 and B180) or ((not B168) and (not B180));
B184 <= (not B193) or (not B194);
B185 <= ((not B169) and B176) or (B169 and (not B176));
B186 <= B195 and B188;
B187 <= (not B197) or (not B196);
B188 <= B169 or B170;
B189 <= B169 or B176;
B190 <= B168 and B180;
B191 <= (not B167) or (not B168);
B192 <= B176 and B191;
B193 <= (not B192) and (not B176);
B194 <= B176 or B191;
B195 <= (not B169) or (not B170);
B196 <= B176 or B191;
B197 <= (not B176) and (not B198);
B198 <= B176 and B191;
B199 <= B5025;
B200 <= B5058;
B201 <= B5091;
B202 <= B5124;
B203 <= B5157;
B204 <= B210 and B209;
B205 <= B212 or B211;
B206 <= B214 or B213;
B207 <= B209 and B215;
B208 <= B209 and B216;
B209 <= ((not B199) and B200) or (B199 and (not B200));
B210 <= ((not B211) and B201) or (B211 and (not B201));
B211 <= B219 and B218;
B212 <= B217 and B201;
B213 <= B222 and B221;
B214 <= B220 and B201;
B215 <= B223 or B200;
B216 <= (B201 and B213) or ((not B201) and (not B213));
B217 <= (not B226) or (not B227);
B218 <= ((not B202) and B209) or (B202 and (not B209));
B219 <= B228 and B221;
B220 <= (not B230) or (not B229);
B221 <= B202 or B203;
B222 <= B202 or B209;
B223 <= B201 and B213;
B224 <= (not B200) or (not B201);
B225 <= B209 and B224;
B226 <= (not B225) and (not B209);
B227 <= B209 or B224;
B228 <= (not B202) or (not B203);
B229 <= B209 or B224;
B230 <= (not B209) and (not B231);
B231 <= B209 and B224;
B232 <= B1062;
B233 <= B1099;
B234 <= B1132;
B235 <= B1165;
B236 <= B1198;
B237 <= B243 and B242;
B238 <= B245 or B244;
B239 <= B247 or B246;
B240 <= B242 and B248;
B241 <= B242 and B249;
B242 <= ((not B232) and B233) or (B232 and (not B233));
B243 <= ((not B244) and B234) or (B244 and (not B234));
B244 <= B252 and B251;
B245 <= B250 and B234;
B246 <= B255 and B254;
B247 <= B253 and B234;
B248 <= B256 or B233;
B249 <= (B234 and B246) or ((not B234) and (not B246));
B250 <= (not B259) or (not B260);
B251 <= ((not B235) and B242) or (B235 and (not B242));
B252 <= B261 and B254;
B253 <= (not B263) or (not B262);
B254 <= B235 or B236;
B255 <= B235 or B242;
B256 <= B234 and B246;
B257 <= (not B233) or (not B234);
B258 <= B242 and B257;
B259 <= (not B258) and (not B242);
B260 <= B242 or B257;
B261 <= (not B235) or (not B236);
B262 <= B242 or B257;
B263 <= (not B242) and (not B264);
B264 <= B242 and B257;
B265 <= B1231;
B266 <= B1264;
B267 <= B1297;
B268 <= B1330;
B269 <= B1363;
B270 <= B276 and B275;
B271 <= B278 or B277;
B272 <= B280 or B279;
B273 <= B275 and B281;
B274 <= B275 and B282;
B275 <= ((not B265) and B266) or (B265 and (not B266));
B276 <= ((not B277) and B267) or (B277 and (not B267));
B277 <= B285 and B284;
B278 <= B283 and B267;
B279 <= B288 and B287;
B280 <= B286 and B267;
B281 <= B289 or B266;
B282 <= (B267 and B279) or ((not B267) and (not B279));
B283 <= (not B292) or (not B293);
B284 <= ((not B268) and B275) or (B268 and (not B275));
B285 <= B294 and B287;
B286 <= (not B296) or (not B295);
B287 <= B268 or B269;
B288 <= B268 or B275;
B289 <= B267 and B279;
B290 <= (not B266) or (not B267);
B291 <= B275 and B290;
B292 <= (not B291) and (not B275);
B293 <= B275 or B290;
B294 <= (not B268) or (not B269);
B295 <= B275 or B290;
B296 <= (not B275) and (not B297);
B297 <= B275 and B290;
B298 <= B1396;
B299 <= B1429;
B300 <= B1462;
B301 <= B1495;
B302 <= B1528;
B303 <= B309 and B308;
B304 <= B311 or B310;
B305 <= B313 or B312;
B306 <= B308 and B314;
B307 <= B308 and B315;
B308 <= ((not B298) and B299) or (B298 and (not B299));
B309 <= ((not B310) and B300) or (B310 and (not B300));
B310 <= B318 and B317;
B311 <= B316 and B300;
B312 <= B321 and B320;
B313 <= B319 and B300;
B314 <= B322 or B299;
B315 <= (B300 and B312) or ((not B300) and (not B312));
B316 <= (not B325) or (not B326);
B317 <= ((not B301) and B308) or (B301 and (not B308));
B318 <= B327 and B320;
B319 <= (not B329) or (not B328);
B320 <= B301 or B302;
B321 <= B301 or B308;
B322 <= B300 and B312;
B323 <= (not B299) or (not B300);
B324 <= B308 and B323;
B325 <= (not B324) and (not B308);
B326 <= B308 or B323;
B327 <= (not B301) or (not B302);
B328 <= B308 or B323;
B329 <= (not B308) and (not B330);
B330 <= B308 and B323;
B331 <= B1561;
B332 <= B1594;
B333 <= B1627;
B334 <= B1660;
B335 <= B1693;
B336 <= B342 and B341;
B337 <= B344 or B343;
B338 <= B346 or B345;
B339 <= B341 and B347;
B340 <= B341 and B348;
B341 <= ((not B331) and B332) or (B331 and (not B332));
B342 <= ((not B343) and B333) or (B343 and (not B333));
B343 <= B351 and B350;
B344 <= B349 and B333;
B345 <= B354 and B353;
B346 <= B352 and B333;
B347 <= B355 or B332;
B348 <= (B333 and B345) or ((not B333) and (not B345));
B349 <= (not B358) or (not B359);
B350 <= ((not B334) and B341) or (B334 and (not B341));
B351 <= B360 and B353;
B352 <= (not B362) or (not B361);
B353 <= B334 or B335;
B354 <= B334 or B341;
B355 <= B333 and B345;
B356 <= (not B332) or (not B333);
B357 <= B341 and B356;
B358 <= (not B357) and (not B341);
B359 <= B341 or B356;
B360 <= (not B334) or (not B335);
B361 <= B341 or B356;
B362 <= (not B341) and (not B363);
B363 <= B341 and B356;
B364 <= B1726;
B365 <= B1759;
B366 <= B1792;
B367 <= B1825;
B368 <= B1858;
B369 <= B375 and B374;
B370 <= B377 or B376;
B371 <= B379 or B378;
B372 <= B374 and B380;
B373 <= B374 and B381;
B374 <= ((not B364) and B365) or (B364 and (not B365));
B375 <= ((not B376) and B366) or (B376 and (not B366));
B376 <= B384 and B383;
B377 <= B382 and B366;
B378 <= B387 and B386;
B379 <= B385 and B366;
B380 <= B388 or B365;
B381 <= (B366 and B378) or ((not B366) and (not B378));
B382 <= (not B391) or (not B392);
B383 <= ((not B367) and B374) or (B367 and (not B374));
B384 <= B393 and B386;
B385 <= (not B395) or (not B394);
B386 <= B367 or B368;
B387 <= B367 or B374;
B388 <= B366 and B378;
B389 <= (not B365) or (not B366);
B390 <= B374 and B389;
B391 <= (not B390) and (not B374);
B392 <= B374 or B389;
B393 <= (not B367) or (not B368);
B394 <= B374 or B389;
B395 <= (not B374) and (not B396);
B396 <= B374 and B389;
B397 <= B1891;
B398 <= B1924;
B399 <= B1957;
B400 <= B1990;
B401 <= B2023;
B402 <= B408 and B407;
B403 <= B410 or B409;
B404 <= B412 or B411;
B405 <= B407 and B413;
B406 <= B407 and B414;
B407 <= ((not B397) and B398) or (B397 and (not B398));
B408 <= ((not B409) and B399) or (B409 and (not B399));
B409 <= B417 and B416;
B410 <= B415 and B399;
B411 <= B420 and B419;
B412 <= B418 and B399;
B413 <= B421 or B398;
B414 <= (B399 and B411) or ((not B399) and (not B411));
B415 <= (not B424) or (not B425);
B416 <= ((not B400) and B407) or (B400 and (not B407));
B417 <= B426 and B419;
B418 <= (not B428) or (not B427);
B419 <= B400 or B401;
B420 <= B400 or B407;
B421 <= B399 and B411;
B422 <= (not B398) or (not B399);
B423 <= B407 and B422;
B424 <= (not B423) and (not B407);
B425 <= B407 or B422;
B426 <= (not B400) or (not B401);
B427 <= B407 or B422;
B428 <= (not B407) and (not B429);
B429 <= B407 and B422;
B430 <= B2056;
B431 <= B2089;
B432 <= B2122;
B433 <= B2155;
B434 <= B2188;
B435 <= B441 and B440;
B436 <= B443 or B442;
B437 <= B445 or B444;
B438 <= B440 and B446;
B439 <= B440 and B447;
B440 <= ((not B430) and B431) or (B430 and (not B431));
B441 <= ((not B442) and B432) or (B442 and (not B432));
B442 <= B450 and B449;
B443 <= B448 and B432;
B444 <= B453 and B452;
B445 <= B451 and B432;
B446 <= B454 or B431;
B447 <= (B432 and B444) or ((not B432) and (not B444));
B448 <= (not B457) or (not B458);
B449 <= ((not B433) and B440) or (B433 and (not B440));
B450 <= B459 and B452;
B451 <= (not B461) or (not B460);
B452 <= B433 or B434;
B453 <= B433 or B440;
B454 <= B432 and B444;
B455 <= (not B431) or (not B432);
B456 <= B440 and B455;
B457 <= (not B456) and (not B440);
B458 <= B440 or B455;
B459 <= (not B433) or (not B434);
B460 <= B440 or B455;
B461 <= (not B440) and (not B462);
B462 <= B440 and B455;
B463 <= B2221;
B464 <= B2254;
B465 <= B2287;
B466 <= B2320;
B467 <= B2353;
B468 <= B474 and B473;
B469 <= B476 or B475;
B470 <= B478 or B477;
B471 <= B473 and B479;
B472 <= B473 and B480;
B473 <= ((not B463) and B464) or (B463 and (not B464));
B474 <= ((not B475) and B465) or (B475 and (not B465));
B475 <= B483 and B482;
B476 <= B481 and B465;
B477 <= B486 and B485;
B478 <= B484 and B465;
B479 <= B487 or B464;
B480 <= (B465 and B477) or ((not B465) and (not B477));
B481 <= (not B490) or (not B491);
B482 <= ((not B466) and B473) or (B466 and (not B473));
B483 <= B492 and B485;
B484 <= (not B494) or (not B493);
B485 <= B466 or B467;
B486 <= B466 or B473;
B487 <= B465 and B477;
B488 <= (not B464) or (not B465);
B489 <= B473 and B488;
B490 <= (not B489) and (not B473);
B491 <= B473 or B488;
B492 <= (not B466) or (not B467);
B493 <= B473 or B488;
B494 <= (not B473) and (not B495);
B495 <= B473 and B488;
B496 <= B2386;
B497 <= B2419;
B498 <= B2452;
B499 <= B2485;
B500 <= B2518;
B501 <= B507 and B506;
B502 <= B509 or B508;
B503 <= B511 or B510;
B504 <= B506 and B512;
B505 <= B506 and B513;
B506 <= ((not B496) and B497) or (B496 and (not B497));
B507 <= ((not B508) and B498) or (B508 and (not B498));
B508 <= B516 and B515;
B509 <= B514 and B498;
B510 <= B519 and B518;
B511 <= B517 and B498;
B512 <= B520 or B497;
B513 <= (B498 and B510) or ((not B498) and (not B510));
B514 <= (not B523) or (not B524);
B515 <= ((not B499) and B506) or (B499 and (not B506));
B516 <= B525 and B518;
B517 <= (not B527) or (not B526);
B518 <= B499 or B500;
B519 <= B499 or B506;
B520 <= B498 and B510;
B521 <= (not B497) or (not B498);
B522 <= B506 and B521;
B523 <= (not B522) and (not B506);
B524 <= B506 or B521;
B525 <= (not B499) or (not B500);
B526 <= B506 or B521;
B527 <= (not B506) and (not B528);
B528 <= B506 and B521;
B529 <= B2551;
B530 <= B2584;
B531 <= B2617;
B532 <= B2650;
B533 <= B2683;
B534 <= B540 and B539;
B535 <= B542 or B541;
B536 <= B544 or B543;
B537 <= B539 and B545;
B538 <= B539 and B546;
B539 <= ((not B529) and B530) or (B529 and (not B530));
B540 <= ((not B541) and B531) or (B541 and (not B531));
B541 <= B549 and B548;
B542 <= B547 and B531;
B543 <= B552 and B551;
B544 <= B550 and B531;
B545 <= B553 or B530;
B546 <= (B531 and B543) or ((not B531) and (not B543));
B547 <= (not B556) or (not B557);
B548 <= ((not B532) and B539) or (B532 and (not B539));
B549 <= B558 and B551;
B550 <= (not B560) or (not B559);
B551 <= B532 or B533;
B552 <= B532 or B539;
B553 <= B531 and B543;
B554 <= (not B530) or (not B531);
B555 <= B539 and B554;
B556 <= (not B555) and (not B539);
B557 <= B539 or B554;
B558 <= (not B532) or (not B533);
B559 <= B539 or B554;
B560 <= (not B539) and (not B561);
B561 <= B539 and B554;
B562 <= B2716;
B563 <= B2749;
B564 <= B2782;
B565 <= B2815;
B566 <= B2848;
B567 <= B573 and B572;
B568 <= B575 or B574;
B569 <= B577 or B576;
B570 <= B572 and B578;
B571 <= B572 and B579;
B572 <= ((not B562) and B563) or (B562 and (not B563));
B573 <= ((not B574) and B564) or (B574 and (not B564));
B574 <= B582 and B581;
B575 <= B580 and B564;
B576 <= B585 and B584;
B577 <= B583 and B564;
B578 <= B586 or B563;
B579 <= (B564 and B576) or ((not B564) and (not B576));
B580 <= (not B589) or (not B590);
B581 <= ((not B565) and B572) or (B565 and (not B572));
B582 <= B591 and B584;
B583 <= (not B593) or (not B592);
B584 <= B565 or B566;
B585 <= B565 or B572;
B586 <= B564 and B576;
B587 <= (not B563) or (not B564);
B588 <= B572 and B587;
B589 <= (not B588) and (not B572);
B590 <= B572 or B587;
B591 <= (not B565) or (not B566);
B592 <= B572 or B587;
B593 <= (not B572) and (not B594);
B594 <= B572 and B587;
B595 <= B2881;
B596 <= B2914;
B597 <= B2947;
B598 <= B2980;
B599 <= B3013;
B600 <= B606 and B605;
B601 <= B608 or B607;
B602 <= B610 or B609;
B603 <= B605 and B611;
B604 <= B605 and B612;
B605 <= ((not B595) and B596) or (B595 and (not B596));
B606 <= ((not B607) and B597) or (B607 and (not B597));
B607 <= B615 and B614;
B608 <= B613 and B597;
B609 <= B618 and B617;
B610 <= B616 and B597;
B611 <= B619 or B596;
B612 <= (B597 and B609) or ((not B597) and (not B609));
B613 <= (not B622) or (not B623);
B614 <= ((not B598) and B605) or (B598 and (not B605));
B615 <= B624 and B617;
B616 <= (not B626) or (not B625);
B617 <= B598 or B599;
B618 <= B598 or B605;
B619 <= B597 and B609;
B620 <= (not B596) or (not B597);
B621 <= B605 and B620;
B622 <= (not B621) and (not B605);
B623 <= B605 or B620;
B624 <= (not B598) or (not B599);
B625 <= B605 or B620;
B626 <= (not B605) and (not B627);
B627 <= B605 and B620;
B628 <= B3046;
B629 <= B3079;
B630 <= B3112;
B631 <= B3145;
B632 <= B3178;
B633 <= B639 and B638;
B634 <= B641 or B640;
B635 <= B643 or B642;
B636 <= B638 and B644;
B637 <= B638 and B645;
B638 <= ((not B628) and B629) or (B628 and (not B629));
B639 <= ((not B640) and B630) or (B640 and (not B630));
B640 <= B648 and B647;
B641 <= B646 and B630;
B642 <= B651 and B650;
B643 <= B649 and B630;
B644 <= B652 or B629;
B645 <= (B630 and B642) or ((not B630) and (not B642));
B646 <= (not B655) or (not B656);
B647 <= ((not B631) and B638) or (B631 and (not B638));
B648 <= B657 and B650;
B649 <= (not B659) or (not B658);
B650 <= B631 or B632;
B651 <= B631 or B638;
B652 <= B630 and B642;
B653 <= (not B629) or (not B630);
B654 <= B638 and B653;
B655 <= (not B654) and (not B638);
B656 <= B638 or B653;
B657 <= (not B631) or (not B632);
B658 <= B638 or B653;
B659 <= (not B638) and (not B660);
B660 <= B638 and B653;
B661 <= B3211;
B662 <= B3244;
B663 <= B3277;
B664 <= B3310;
B665 <= B3343;
B666 <= B672 and B671;
B667 <= B674 or B673;
B668 <= B676 or B675;
B669 <= B671 and B677;
B670 <= B671 and B678;
B671 <= ((not B661) and B662) or (B661 and (not B662));
B672 <= ((not B673) and B663) or (B673 and (not B663));
B673 <= B681 and B680;
B674 <= B679 and B663;
B675 <= B684 and B683;
B676 <= B682 and B663;
B677 <= B685 or B662;
B678 <= (B663 and B675) or ((not B663) and (not B675));
B679 <= (not B688) or (not B689);
B680 <= ((not B664) and B671) or (B664 and (not B671));
B681 <= B690 and B683;
B682 <= (not B692) or (not B691);
B683 <= B664 or B665;
B684 <= B664 or B671;
B685 <= B663 and B675;
B686 <= (not B662) or (not B663);
B687 <= B671 and B686;
B688 <= (not B687) and (not B671);
B689 <= B671 or B686;
B690 <= (not B664) or (not B665);
B691 <= B671 or B686;
B692 <= (not B671) and (not B693);
B693 <= B671 and B686;
B694 <= B3376;
B695 <= B3409;
B696 <= B3442;
B697 <= B3475;
B698 <= B3508;
B699 <= B705 and B704;
B700 <= B707 or B706;
B701 <= B709 or B708;
B702 <= B704 and B710;
B703 <= B704 and B711;
B704 <= ((not B694) and B695) or (B694 and (not B695));
B705 <= ((not B706) and B696) or (B706 and (not B696));
B706 <= B714 and B713;
B707 <= B712 and B696;
B708 <= B717 and B716;
B709 <= B715 and B696;
B710 <= B718 or B695;
B711 <= (B696 and B708) or ((not B696) and (not B708));
B712 <= (not B721) or (not B722);
B713 <= ((not B697) and B704) or (B697 and (not B704));
B714 <= B723 and B716;
B715 <= (not B725) or (not B724);
B716 <= B697 or B698;
B717 <= B697 or B704;
B718 <= B696 and B708;
B719 <= (not B695) or (not B696);
B720 <= B704 and B719;
B721 <= (not B720) and (not B704);
B722 <= B704 or B719;
B723 <= (not B697) or (not B698);
B724 <= B704 or B719;
B725 <= (not B704) and (not B726);
B726 <= B704 and B719;
B727 <= B3541;
B728 <= B3574;
B729 <= B3607;
B730 <= B3640;
B731 <= B3673;
B732 <= B738 and B737;
B733 <= B740 or B739;
B734 <= B742 or B741;
B735 <= B737 and B743;
B736 <= B737 and B744;
B737 <= ((not B727) and B728) or (B727 and (not B728));
B738 <= ((not B739) and B729) or (B739 and (not B729));
B739 <= B747 and B746;
B740 <= B745 and B729;
B741 <= B750 and B749;
B742 <= B748 and B729;
B743 <= B751 or B728;
B744 <= (B729 and B741) or ((not B729) and (not B741));
B745 <= (not B754) or (not B755);
B746 <= ((not B730) and B737) or (B730 and (not B737));
B747 <= B756 and B749;
B748 <= (not B758) or (not B757);
B749 <= B730 or B731;
B750 <= B730 or B737;
B751 <= B729 and B741;
B752 <= (not B728) or (not B729);
B753 <= B737 and B752;
B754 <= (not B753) and (not B737);
B755 <= B737 or B752;
B756 <= (not B730) or (not B731);
B757 <= B737 or B752;
B758 <= (not B737) and (not B759);
B759 <= B737 and B752;
B760 <= B3706;
B761 <= B3739;
B762 <= B3772;
B763 <= B3805;
B764 <= B3838;
B765 <= B771 and B770;
B766 <= B773 or B772;
B767 <= B775 or B774;
B768 <= B770 and B776;
B769 <= B770 and B777;
B770 <= ((not B760) and B761) or (B760 and (not B761));
B771 <= ((not B772) and B762) or (B772 and (not B762));
B772 <= B780 and B779;
B773 <= B778 and B762;
B774 <= B783 and B782;
B775 <= B781 and B762;
B776 <= B784 or B761;
B777 <= (B762 and B774) or ((not B762) and (not B774));
B778 <= (not B787) or (not B788);
B779 <= ((not B763) and B770) or (B763 and (not B770));
B780 <= B789 and B782;
B781 <= (not B791) or (not B790);
B782 <= B763 or B764;
B783 <= B763 or B770;
B784 <= B762 and B774;
B785 <= (not B761) or (not B762);
B786 <= B770 and B785;
B787 <= (not B786) and (not B770);
B788 <= B770 or B785;
B789 <= (not B763) or (not B764);
B790 <= B770 or B785;
B791 <= (not B770) and (not B792);
B792 <= B770 and B785;
B793 <= B3871;
B794 <= B3904;
B795 <= B3937;
B796 <= B3970;
B797 <= B4003;
B798 <= B804 and B803;
B799 <= B806 or B805;
B800 <= B808 or B807;
B801 <= B803 and B809;
B802 <= B803 and B810;
B803 <= ((not B793) and B794) or (B793 and (not B794));
B804 <= ((not B805) and B795) or (B805 and (not B795));
B805 <= B813 and B812;
B806 <= B811 and B795;
B807 <= B816 and B815;
B808 <= B814 and B795;
B809 <= B817 or B794;
B810 <= (B795 and B807) or ((not B795) and (not B807));
B811 <= (not B820) or (not B821);
B812 <= ((not B796) and B803) or (B796 and (not B803));
B813 <= B822 and B815;
B814 <= (not B824) or (not B823);
B815 <= B796 or B797;
B816 <= B796 or B803;
B817 <= B795 and B807;
B818 <= (not B794) or (not B795);
B819 <= B803 and B818;
B820 <= (not B819) and (not B803);
B821 <= B803 or B818;
B822 <= (not B796) or (not B797);
B823 <= B803 or B818;
B824 <= (not B803) and (not B825);
B825 <= B803 and B818;
B826 <= B4036;
B827 <= B4069;
B828 <= B4102;
B829 <= B4135;
B830 <= B4168;
B831 <= B837 and B836;
B832 <= B839 or B838;
B833 <= B841 or B840;
B834 <= B836 and B842;
B835 <= B836 and B843;
B836 <= ((not B826) and B827) or (B826 and (not B827));
B837 <= ((not B838) and B828) or (B838 and (not B828));
B838 <= B846 and B845;
B839 <= B844 and B828;
B840 <= B849 and B848;
B841 <= B847 and B828;
B842 <= B850 or B827;
B843 <= (B828 and B840) or ((not B828) and (not B840));
B844 <= (not B853) or (not B854);
B845 <= ((not B829) and B836) or (B829 and (not B836));
B846 <= B855 and B848;
B847 <= (not B857) or (not B856);
B848 <= B829 or B830;
B849 <= B829 or B836;
B850 <= B828 and B840;
B851 <= (not B827) or (not B828);
B852 <= B836 and B851;
B853 <= (not B852) and (not B836);
B854 <= B836 or B851;
B855 <= (not B829) or (not B830);
B856 <= B836 or B851;
B857 <= (not B836) and (not B858);
B858 <= B836 and B851;
B859 <= B4201;
B860 <= B4234;
B861 <= B4267;
B862 <= B4300;
B863 <= B4333;
B864 <= B870 and B869;
B865 <= B872 or B871;
B866 <= B874 or B873;
B867 <= B869 and B875;
B868 <= B869 and B876;
B869 <= ((not B859) and B860) or (B859 and (not B860));
B870 <= ((not B871) and B861) or (B871 and (not B861));
B871 <= B879 and B878;
B872 <= B877 and B861;
B873 <= B882 and B881;
B874 <= B880 and B861;
B875 <= B883 or B860;
B876 <= (B861 and B873) or ((not B861) and (not B873));
B877 <= (not B886) or (not B887);
B878 <= ((not B862) and B869) or (B862 and (not B869));
B879 <= B888 and B881;
B880 <= (not B890) or (not B889);
B881 <= B862 or B863;
B882 <= B862 or B869;
B883 <= B861 and B873;
B884 <= (not B860) or (not B861);
B885 <= B869 and B884;
B886 <= (not B885) and (not B869);
B887 <= B869 or B884;
B888 <= (not B862) or (not B863);
B889 <= B869 or B884;
B890 <= (not B869) and (not B891);
B891 <= B869 and B884;
B892 <= B4366;
B893 <= B4399;
B894 <= B4432;
B895 <= B4465;
B896 <= B4498;
B897 <= B903 and B902;
B898 <= B905 or B904;
B899 <= B907 or B906;
B900 <= B902 and B908;
B901 <= B902 and B909;
B902 <= ((not B892) and B893) or (B892 and (not B893));
B903 <= ((not B904) and B894) or (B904 and (not B894));
B904 <= B912 and B911;
B905 <= B910 and B894;
B906 <= B915 and B914;
B907 <= B913 and B894;
B908 <= B916 or B893;
B909 <= (B894 and B906) or ((not B894) and (not B906));
B910 <= (not B919) or (not B920);
B911 <= ((not B895) and B902) or (B895 and (not B902));
B912 <= B921 and B914;
B913 <= (not B923) or (not B922);
B914 <= B895 or B896;
B915 <= B895 or B902;
B916 <= B894 and B906;
B917 <= (not B893) or (not B894);
B918 <= B902 and B917;
B919 <= (not B918) and (not B902);
B920 <= B902 or B917;
B921 <= (not B895) or (not B896);
B922 <= B902 or B917;
B923 <= (not B902) and (not B924);
B924 <= B902 and B917;
B925 <= B4531;
B926 <= B4564;
B927 <= B4597;
B928 <= B4630;
B929 <= B4663;
B930 <= B936 and B935;
B931 <= B938 or B937;
B932 <= B940 or B939;
B933 <= B935 and B941;
B934 <= B935 and B942;
B935 <= ((not B925) and B926) or (B925 and (not B926));
B936 <= ((not B937) and B927) or (B937 and (not B927));
B937 <= B945 and B944;
B938 <= B943 and B927;
B939 <= B948 and B947;
B940 <= B946 and B927;
B941 <= B949 or B926;
B942 <= (B927 and B939) or ((not B927) and (not B939));
B943 <= (not B952) or (not B953);
B944 <= ((not B928) and B935) or (B928 and (not B935));
B945 <= B954 and B947;
B946 <= (not B956) or (not B955);
B947 <= B928 or B929;
B948 <= B928 or B935;
B949 <= B927 and B939;
B950 <= (not B926) or (not B927);
B951 <= B935 and B950;
B952 <= (not B951) and (not B935);
B953 <= B935 or B950;
B954 <= (not B928) or (not B929);
B955 <= B935 or B950;
B956 <= (not B935) and (not B957);
B957 <= B935 and B950;
B958 <= B4696;
B959 <= B4729;
B960 <= B4762;
B961 <= B4795;
B962 <= B4828;
B963 <= B969 and B968;
B964 <= B971 or B970;
B965 <= B973 or B972;
B966 <= B968 and B974;
B967 <= B968 and B975;
B968 <= ((not B958) and B959) or (B958 and (not B959));
B969 <= ((not B970) and B960) or (B970 and (not B960));
B970 <= B978 and B977;
B971 <= B976 and B960;
B972 <= B981 and B980;
B973 <= B979 and B960;
B974 <= B982 or B959;
B975 <= (B960 and B972) or ((not B960) and (not B972));
B976 <= (not B985) or (not B986);
B977 <= ((not B961) and B968) or (B961 and (not B968));
B978 <= B987 and B980;
B979 <= (not B989) or (not B988);
B980 <= B961 or B962;
B981 <= B961 or B968;
B982 <= B960 and B972;
B983 <= (not B959) or (not B960);
B984 <= B968 and B983;
B985 <= (not B984) and (not B968);
B986 <= B968 or B983;
B987 <= (not B961) or (not B962);
B988 <= B968 or B983;
B989 <= (not B968) and (not B990);
B990 <= B968 and B983;
B991 <= B4861;
B992 <= B4894;
B993 <= B4927;
B994 <= B4960;
B995 <= B4993;
B996 <= B1002 and B1001;
B997 <= B1004 or B1003;
B998 <= B1006 or B1005;
B999 <= B1001 and B1007;
B1000 <= B1001 and B1008;
B1001 <= ((not B991) and B992) or (B991 and (not B992));
B1002 <= ((not B1003) and B993) or (B1003 and (not B993));
B1003 <= B1011 and B1010;
B1004 <= B1009 and B993;
B1005 <= B1014 and B1013;
B1006 <= B1012 and B993;
B1007 <= B1015 or B992;
B1008 <= (B993 and B1005) or ((not B993) and (not B1005));
B1009 <= (not B1018) or (not B1019);
B1010 <= ((not B994) and B1001) or (B994 and (not B1001));
B1011 <= B1020 and B1013;
B1012 <= (not B1022) or (not B1021);
B1013 <= B994 or B995;
B1014 <= B994 or B1001;
B1015 <= B993 and B1005;
B1016 <= (not B992) or (not B993);
B1017 <= B1001 and B1016;
B1018 <= (not B1017) and (not B1001);
B1019 <= B1001 or B1016;
B1020 <= (not B994) or (not B995);
B1021 <= B1001 or B1016;
B1022 <= (not B1001) and (not B1023);
B1023 <= B1001 and B1016;
B1024 <= B5026;
B1025 <= B5059;
B1026 <= B5092;
B1027 <= B5125;
B1028 <= B5158;
B1029 <= B1035 and B1034;
B1030 <= B1037 or B1036;
B1031 <= B1039 or B1038;
B1032 <= B1034 and B1040;
B1033 <= B1034 and B1041;
B1034 <= ((not B1024) and B1025) or (B1024 and (not B1025));
B1035 <= ((not B1036) and B1026) or (B1036 and (not B1026));
B1036 <= B1044 and B1043;
B1037 <= B1042 and B1026;
B1038 <= B1047 and B1046;
B1039 <= B1045 and B1026;
B1040 <= B1048 or B1025;
B1041 <= (B1026 and B1038) or ((not B1026) and (not B1038));
B1042 <= (not B1051) or (not B1052);
B1043 <= ((not B1027) and B1034) or (B1027 and (not B1034));
B1044 <= B1053 and B1046;
B1045 <= (not B1055) or (not B1054);
B1046 <= B1027 or B1028;
B1047 <= B1027 or B1034;
B1048 <= B1026 and B1038;
B1049 <= (not B1025) or (not B1026);
B1050 <= B1034 and B1049;
B1051 <= (not B1050) and (not B1034);
B1052 <= B1034 or B1049;
B1053 <= (not B1027) or (not B1028);
B1054 <= B1034 or B1049;
B1055 <= (not B1034) and (not B1056);
B1056 <= B1034 and B1049;
A6930 <= A6908 and A6923;
A6929 <= (not A6908) and (not A6930);
A6928 <= A6908 or A6923;
A6927 <= (not A6901) or (not A6902);
A6926 <= A6908 or A6923;
A6925 <= (not A6924) and (not A6908);
A6924 <= A6908 and A6923;
A6923 <= (not A6899) or (not A6900);
A6922 <= A6900 and A6912;
A6921 <= A6901 or A6908;
A6920 <= A6901 or A6902;
A6919 <= (not A6929) or (not A6928);
A6918 <= A6927 and A6920;
A6917 <= ((not A6901) and A6908) or (A6901 and (not A6908));
A6916 <= (not A6925) or (not A6926);
A6915 <= (A6900 and A6912) or ((not A6900) and (not A6912));
A6914 <= A6922 or A6899;
A6913 <= A6919 and A6900;
A6912 <= A6921 and A6920;
A6911 <= A6916 and A6900;
A6910 <= A6918 and A6917;
A6909 <= ((not A6910) and A6900) or (A6910 and (not A6900));
A6908 <= ((not A6898) and A6899) or (A6898 and (not A6899));
A6907 <= A6908 and A6915;
A6906 <= A6908 and A6914;
A6905 <= A6913 or A6912;
A6904 <= A6911 or A6910;
A6903 <= A6909 and A6908;
A6902 <= B1033;
A6901 <= B1000;
A6900 <= B967;
A6899 <= B934;
A6898 <= B901;
A6897 <= A6875 and A6890;
A6896 <= (not A6875) and (not A6897);
A6895 <= A6875 or A6890;
A6894 <= (not A6868) or (not A6869);
A6893 <= A6875 or A6890;
A6892 <= (not A6891) and (not A6875);
A6891 <= A6875 and A6890;
A6890 <= (not A6866) or (not A6867);
A6889 <= A6867 and A6879;
A6888 <= A6868 or A6875;
A6887 <= A6868 or A6869;
A6886 <= (not A6896) or (not A6895);
A6885 <= A6894 and A6887;
A6884 <= ((not A6868) and A6875) or (A6868 and (not A6875));
A6883 <= (not A6892) or (not A6893);
A6882 <= (A6867 and A6879) or ((not A6867) and (not A6879));
A6881 <= A6889 or A6866;
A6880 <= A6886 and A6867;
A6879 <= A6888 and A6887;
A6878 <= A6883 and A6867;
A6877 <= A6885 and A6884;
A6876 <= ((not A6877) and A6867) or (A6877 and (not A6867));
A6875 <= ((not A6865) and A6866) or (A6865 and (not A6866));
A6874 <= A6875 and A6882;
A6873 <= A6875 and A6881;
A6872 <= A6880 or A6879;
A6871 <= A6878 or A6877;
A6870 <= A6876 and A6875;
A6869 <= B868;
A6868 <= B835;
A6867 <= B802;
A6866 <= B769;
A6865 <= B736;
A6864 <= A6842 and A6857;
A6863 <= (not A6842) and (not A6864);
A6862 <= A6842 or A6857;
A6861 <= (not A6835) or (not A6836);
A6860 <= A6842 or A6857;
A6859 <= (not A6858) and (not A6842);
A6858 <= A6842 and A6857;
A6857 <= (not A6833) or (not A6834);
A6856 <= A6834 and A6846;
A6855 <= A6835 or A6842;
A6854 <= A6835 or A6836;
A6853 <= (not A6863) or (not A6862);
A6852 <= A6861 and A6854;
A6851 <= ((not A6835) and A6842) or (A6835 and (not A6842));
A6850 <= (not A6859) or (not A6860);
A6849 <= (A6834 and A6846) or ((not A6834) and (not A6846));
A6848 <= A6856 or A6833;
A6847 <= A6853 and A6834;
A6846 <= A6855 and A6854;
A6845 <= A6850 and A6834;
A6844 <= A6852 and A6851;
A6843 <= ((not A6844) and A6834) or (A6844 and (not A6834));
A6842 <= ((not A6832) and A6833) or (A6832 and (not A6833));
A6841 <= A6842 and A6849;
A6840 <= A6842 and A6848;
A6839 <= A6847 or A6846;
A6838 <= A6845 or A6844;
A6837 <= A6843 and A6842;
A6836 <= B703;
A6835 <= B670;
A6834 <= B637;
A6833 <= B604;
A6832 <= B571;
A6831 <= A6809 and A6824;
A6830 <= (not A6809) and (not A6831);
A6829 <= A6809 or A6824;
A6828 <= (not A6802) or (not A6803);
A6827 <= A6809 or A6824;
A6826 <= (not A6825) and (not A6809);
A6825 <= A6809 and A6824;
A6824 <= (not A6800) or (not A6801);
A6823 <= A6801 and A6813;
A6822 <= A6802 or A6809;
A6821 <= A6802 or A6803;
A6820 <= (not A6830) or (not A6829);
A6819 <= A6828 and A6821;
A6818 <= ((not A6802) and A6809) or (A6802 and (not A6809));
A6817 <= (not A6826) or (not A6827);
A6816 <= (A6801 and A6813) or ((not A6801) and (not A6813));
A6815 <= A6823 or A6800;
A6814 <= A6820 and A6801;
A6813 <= A6822 and A6821;
A6812 <= A6817 and A6801;
A6811 <= A6819 and A6818;
A6810 <= ((not A6811) and A6801) or (A6811 and (not A6801));
A6809 <= ((not A6799) and A6800) or (A6799 and (not A6800));
A6808 <= A6809 and A6816;
A6807 <= A6809 and A6815;
A6806 <= A6814 or A6813;
A6805 <= A6812 or A6811;
A6804 <= A6810 and A6809;
A6803 <= B538;
A6802 <= B505;
A6801 <= B472;
A6800 <= B439;
A6799 <= B406;
A6798 <= A6776 and A6791;
A6797 <= (not A6776) and (not A6798);
A6796 <= A6776 or A6791;
A6795 <= (not A6769) or (not A6770);
A6794 <= A6776 or A6791;
A6793 <= (not A6792) and (not A6776);
A6792 <= A6776 and A6791;
A6791 <= (not A6767) or (not A6768);
A6790 <= A6768 and A6780;
A6789 <= A6769 or A6776;
A6788 <= A6769 or A6770;
A6787 <= (not A6797) or (not A6796);
A6786 <= A6795 and A6788;
A6785 <= ((not A6769) and A6776) or (A6769 and (not A6776));
A6784 <= (not A6793) or (not A6794);
A6783 <= (A6768 and A6780) or ((not A6768) and (not A6780));
A6782 <= A6790 or A6767;
A6781 <= A6787 and A6768;
A6780 <= A6789 and A6788;
A6779 <= A6784 and A6768;
A6778 <= A6786 and A6785;
A6777 <= ((not A6778) and A6768) or (A6778 and (not A6768));
A6776 <= ((not A6766) and A6767) or (A6766 and (not A6767));
A6775 <= A6776 and A6783;
A6774 <= A6776 and A6782;
A6773 <= A6781 or A6780;
A6772 <= A6779 or A6778;
A6771 <= A6777 and A6776;
A6770 <= B373;
A6769 <= B340;
A6768 <= B307;
A6767 <= B274;
A6766 <= B241;
A6765 <= A6743 and A6758;
A6764 <= (not A6743) and (not A6765);
A6763 <= A6743 or A6758;
A6762 <= (not A6736) or (not A6737);
A6761 <= A6743 or A6758;
A6760 <= (not A6759) and (not A6743);
A6759 <= A6743 and A6758;
A6758 <= (not A6734) or (not A6735);
A6757 <= A6735 and A6747;
A6756 <= A6736 or A6743;
A6755 <= A6736 or A6737;
A6754 <= (not A6764) or (not A6763);
A6753 <= A6762 and A6755;
A6752 <= ((not A6736) and A6743) or (A6736 and (not A6743));
A6751 <= (not A6760) or (not A6761);
A6750 <= (A6735 and A6747) or ((not A6735) and (not A6747));
A6749 <= A6757 or A6734;
A6748 <= A6754 and A6735;
A6747 <= A6756 and A6755;
A6746 <= A6751 and A6735;
A6745 <= A6753 and A6752;
A6744 <= ((not A6745) and A6735) or (A6745 and (not A6735));
A6743 <= ((not A6733) and A6734) or (A6733 and (not A6734));
A6742 <= A6743 and A6750;
A6741 <= A6743 and A6749;
A6740 <= A6748 or A6747;
A6739 <= A6746 or A6745;
A6738 <= A6744 and A6743;
A6737 <= B208;
A6736 <= B175;
A6735 <= B142;
A6734 <= B109;
A6733 <= B76;
A6732 <= A6710 and A6725;
A6731 <= (not A6710) and (not A6732);
A6730 <= A6710 or A6725;
A6729 <= (not A6703) or (not A6704);
A6728 <= A6710 or A6725;
A6727 <= (not A6726) and (not A6710);
A6726 <= A6710 and A6725;
A6725 <= (not A6701) or (not A6702);
A6724 <= A6702 and A6714;
A6723 <= A6703 or A6710;
A6722 <= A6703 or A6704;
A6721 <= (not A6731) or (not A6730);
A6720 <= A6729 and A6722;
A6719 <= ((not A6703) and A6710) or (A6703 and (not A6710));
A6718 <= (not A6727) or (not A6728);
A6717 <= (A6702 and A6714) or ((not A6702) and (not A6714));
A6716 <= A6724 or A6701;
A6715 <= A6721 and A6702;
A6714 <= A6723 and A6722;
A6713 <= A6718 and A6702;
A6712 <= A6720 and A6719;
A6711 <= ((not A6712) and A6702) or (A6712 and (not A6702));
A6710 <= ((not A6700) and A6701) or (A6700 and (not A6701));
A6709 <= A6710 and A6717;
A6708 <= A6710 and A6716;
A6707 <= A6715 or A6714;
A6706 <= A6713 or A6712;
A6705 <= A6711 and A6710;
A6704 <= B43;
A6703 <= B10;
A6702 <= A9976;
A6701 <= A9943;
A6700 <= A9910;
A6699 <= A6677 and A6692;
A6698 <= (not A6677) and (not A6699);
A6697 <= A6677 or A6692;
A6696 <= (not A6670) or (not A6671);
A6695 <= A6677 or A6692;
A6694 <= (not A6693) and (not A6677);
A6693 <= A6677 and A6692;
A6692 <= (not A6668) or (not A6669);
A6691 <= A6669 and A6681;
A6690 <= A6670 or A6677;
A6689 <= A6670 or A6671;
A6688 <= (not A6698) or (not A6697);
A6687 <= A6696 and A6689;
A6686 <= ((not A6670) and A6677) or (A6670 and (not A6677));
A6685 <= (not A6694) or (not A6695);
A6684 <= (A6669 and A6681) or ((not A6669) and (not A6681));
A6683 <= A6691 or A6668;
A6682 <= A6688 and A6669;
A6681 <= A6690 and A6689;
A6680 <= A6685 and A6669;
A6679 <= A6687 and A6686;
A6678 <= ((not A6679) and A6669) or (A6679 and (not A6669));
A6677 <= ((not A6667) and A6668) or (A6667 and (not A6668));
A6676 <= A6677 and A6684;
A6675 <= A6677 and A6683;
A6674 <= A6682 or A6681;
A6673 <= A6680 or A6679;
A6672 <= A6678 and A6677;
A6671 <= A9877;
A6670 <= A9844;
A6669 <= A9811;
A6668 <= A9778;
A6667 <= A9745;
A6666 <= A6644 and A6659;
A6665 <= (not A6644) and (not A6666);
A6664 <= A6644 or A6659;
A6663 <= (not A6637) or (not A6638);
A6662 <= A6644 or A6659;
A6661 <= (not A6660) and (not A6644);
A6660 <= A6644 and A6659;
A6659 <= (not A6635) or (not A6636);
A6658 <= A6636 and A6648;
A6657 <= A6637 or A6644;
A6656 <= A6637 or A6638;
A6655 <= (not A6665) or (not A6664);
A6654 <= A6663 and A6656;
A6653 <= ((not A6637) and A6644) or (A6637 and (not A6644));
A6652 <= (not A6661) or (not A6662);
A6651 <= (A6636 and A6648) or ((not A6636) and (not A6648));
A6650 <= A6658 or A6635;
A6649 <= A6655 and A6636;
A6648 <= A6657 and A6656;
A6647 <= A6652 and A6636;
A6646 <= A6654 and A6653;
A6645 <= ((not A6646) and A6636) or (A6646 and (not A6636));
A6644 <= ((not A6634) and A6635) or (A6634 and (not A6635));
A6643 <= A6644 and A6651;
A6642 <= A6644 and A6650;
A6641 <= A6649 or A6648;
A6640 <= A6647 or A6646;
A6639 <= A6645 and A6644;
A6638 <= A9712;
A6637 <= A9679;
A6636 <= A9646;
A6635 <= A9613;
A6634 <= A9580;
A6633 <= A6611 and A6626;
A6632 <= (not A6611) and (not A6633);
A6631 <= A6611 or A6626;
A6630 <= (not A6604) or (not A6605);
A6629 <= A6611 or A6626;
A6628 <= (not A6627) and (not A6611);
A6627 <= A6611 and A6626;
A6626 <= (not A6602) or (not A6603);
A6625 <= A6603 and A6615;
A6624 <= A6604 or A6611;
A6623 <= A6604 or A6605;
A6622 <= (not A6632) or (not A6631);
A6621 <= A6630 and A6623;
A6620 <= ((not A6604) and A6611) or (A6604 and (not A6611));
A6619 <= (not A6628) or (not A6629);
A6618 <= (A6603 and A6615) or ((not A6603) and (not A6615));
A6617 <= A6625 or A6602;
A6616 <= A6622 and A6603;
A6615 <= A6624 and A6623;
A6614 <= A6619 and A6603;
A6613 <= A6621 and A6620;
A6612 <= ((not A6613) and A6603) or (A6613 and (not A6603));
A6611 <= ((not A6601) and A6602) or (A6601 and (not A6602));
A6610 <= A6611 and A6618;
A6609 <= A6611 and A6617;
A6608 <= A6616 or A6615;
A6607 <= A6614 or A6613;
A6606 <= A6612 and A6611;
A6605 <= A9547;
A6604 <= A9514;
A6603 <= A9481;
A6602 <= A9448;
A6601 <= A9415;
A6600 <= A6578 and A6593;
A6599 <= (not A6578) and (not A6600);
A6598 <= A6578 or A6593;
A6597 <= (not A6571) or (not A6572);
A6596 <= A6578 or A6593;
A6595 <= (not A6594) and (not A6578);
A6594 <= A6578 and A6593;
A6593 <= (not A6569) or (not A6570);
A6592 <= A6570 and A6582;
A6591 <= A6571 or A6578;
A6590 <= A6571 or A6572;
A6589 <= (not A6599) or (not A6598);
A6588 <= A6597 and A6590;
A6587 <= ((not A6571) and A6578) or (A6571 and (not A6578));
A6586 <= (not A6595) or (not A6596);
A6585 <= (A6570 and A6582) or ((not A6570) and (not A6582));
A6584 <= A6592 or A6569;
A6583 <= A6589 and A6570;
A6582 <= A6591 and A6590;
A6581 <= A6586 and A6570;
A6580 <= A6588 and A6587;
A6579 <= ((not A6580) and A6570) or (A6580 and (not A6570));
A6578 <= ((not A6568) and A6569) or (A6568 and (not A6569));
A6577 <= A6578 and A6585;
A6576 <= A6578 and A6584;
A6575 <= A6583 or A6582;
A6574 <= A6581 or A6580;
A6573 <= A6579 and A6578;
A6572 <= A9382;
A6571 <= A9349;
A6570 <= A9316;
A6569 <= A9283;
A6568 <= A9250;
A6567 <= A6545 and A6560;
A6566 <= (not A6545) and (not A6567);
A6565 <= A6545 or A6560;
A6564 <= (not A6538) or (not A6539);
A6563 <= A6545 or A6560;
A6562 <= (not A6561) and (not A6545);
A6561 <= A6545 and A6560;
A6560 <= (not A6536) or (not A6537);
A6559 <= A6537 and A6549;
A6558 <= A6538 or A6545;
A6557 <= A6538 or A6539;
A6556 <= (not A6566) or (not A6565);
A6555 <= A6564 and A6557;
A6554 <= ((not A6538) and A6545) or (A6538 and (not A6545));
A6553 <= (not A6562) or (not A6563);
A6552 <= (A6537 and A6549) or ((not A6537) and (not A6549));
A6551 <= A6559 or A6536;
A6550 <= A6556 and A6537;
A6549 <= A6558 and A6557;
A6548 <= A6553 and A6537;
A6547 <= A6555 and A6554;
A6546 <= ((not A6547) and A6537) or (A6547 and (not A6537));
A6545 <= ((not A6535) and A6536) or (A6535 and (not A6536));
A6544 <= A6545 and A6552;
A6543 <= A6545 and A6551;
A6542 <= A6550 or A6549;
A6541 <= A6548 or A6547;
A6540 <= A6546 and A6545;
A6539 <= A9217;
A6538 <= A9184;
A6537 <= A9151;
A6536 <= A9118;
A6535 <= A9085;
A6534 <= A6512 and A6527;
A6533 <= (not A6512) and (not A6534);
A6532 <= A6512 or A6527;
A6531 <= (not A6505) or (not A6506);
A6530 <= A6512 or A6527;
A6529 <= (not A6528) and (not A6512);
A6528 <= A6512 and A6527;
A6527 <= (not A6503) or (not A6504);
A6526 <= A6504 and A6516;
A6525 <= A6505 or A6512;
A6524 <= A6505 or A6506;
A6523 <= (not A6533) or (not A6532);
A6522 <= A6531 and A6524;
A6521 <= ((not A6505) and A6512) or (A6505 and (not A6512));
A6520 <= (not A6529) or (not A6530);
A6519 <= (A6504 and A6516) or ((not A6504) and (not A6516));
A6518 <= A6526 or A6503;
A6517 <= A6523 and A6504;
A6516 <= A6525 and A6524;
A6515 <= A6520 and A6504;
A6514 <= A6522 and A6521;
A6513 <= ((not A6514) and A6504) or (A6514 and (not A6504));
A6512 <= ((not A6502) and A6503) or (A6502 and (not A6503));
A6511 <= A6512 and A6519;
A6510 <= A6512 and A6518;
A6509 <= A6517 or A6516;
A6508 <= A6515 or A6514;
A6507 <= A6513 and A6512;
A6506 <= A9052;
A6505 <= A9019;
A6504 <= A8986;
A6503 <= A8953;
A6502 <= A8920;
A6501 <= A6479 and A6494;
A6500 <= (not A6479) and (not A6501);
A6499 <= A6479 or A6494;
A6498 <= (not A6472) or (not A6473);
A6497 <= A6479 or A6494;
A6496 <= (not A6495) and (not A6479);
A6495 <= A6479 and A6494;
A6494 <= (not A6470) or (not A6471);
A6493 <= A6471 and A6483;
A6492 <= A6472 or A6479;
A6491 <= A6472 or A6473;
A6490 <= (not A6500) or (not A6499);
A6489 <= A6498 and A6491;
A6488 <= ((not A6472) and A6479) or (A6472 and (not A6479));
A6487 <= (not A6496) or (not A6497);
A6486 <= (A6471 and A6483) or ((not A6471) and (not A6483));
A6485 <= A6493 or A6470;
A6484 <= A6490 and A6471;
A6483 <= A6492 and A6491;
A6482 <= A6487 and A6471;
A6481 <= A6489 and A6488;
A6480 <= ((not A6481) and A6471) or (A6481 and (not A6471));
A6479 <= ((not A6469) and A6470) or (A6469 and (not A6470));
A6478 <= A6479 and A6486;
A6477 <= A6479 and A6485;
A6476 <= A6484 or A6483;
A6475 <= A6482 or A6481;
A6474 <= A6480 and A6479;
A6473 <= A8887;
A6472 <= A8854;
A6471 <= A8821;
A6470 <= A8788;
A6469 <= A8755;
A6468 <= A6446 and A6461;
A6467 <= (not A6446) and (not A6468);
A6466 <= A6446 or A6461;
A6465 <= (not A6439) or (not A6440);
A6464 <= A6446 or A6461;
A6463 <= (not A6462) and (not A6446);
A6462 <= A6446 and A6461;
A6461 <= (not A6437) or (not A6438);
A6460 <= A6438 and A6450;
A6459 <= A6439 or A6446;
A6458 <= A6439 or A6440;
A6457 <= (not A6467) or (not A6466);
A6456 <= A6465 and A6458;
A6455 <= ((not A6439) and A6446) or (A6439 and (not A6446));
A6454 <= (not A6463) or (not A6464);
A6453 <= (A6438 and A6450) or ((not A6438) and (not A6450));
A6452 <= A6460 or A6437;
A6451 <= A6457 and A6438;
A6450 <= A6459 and A6458;
A6449 <= A6454 and A6438;
A6448 <= A6456 and A6455;
A6447 <= ((not A6448) and A6438) or (A6448 and (not A6438));
A6446 <= ((not A6436) and A6437) or (A6436 and (not A6437));
A6445 <= A6446 and A6453;
A6444 <= A6446 and A6452;
A6443 <= A6451 or A6450;
A6442 <= A6449 or A6448;
A6441 <= A6447 and A6446;
A6440 <= A8722;
A6439 <= A8689;
A6438 <= A8656;
A6437 <= A8623;
A6436 <= A8590;
A6435 <= A6413 and A6428;
A6434 <= (not A6413) and (not A6435);
A6433 <= A6413 or A6428;
A6432 <= (not A6406) or (not A6407);
A6431 <= A6413 or A6428;
A6430 <= (not A6429) and (not A6413);
A6429 <= A6413 and A6428;
A6428 <= (not A6404) or (not A6405);
A6427 <= A6405 and A6417;
A6426 <= A6406 or A6413;
A6425 <= A6406 or A6407;
A6424 <= (not A6434) or (not A6433);
A6423 <= A6432 and A6425;
A6422 <= ((not A6406) and A6413) or (A6406 and (not A6413));
A6421 <= (not A6430) or (not A6431);
A6420 <= (A6405 and A6417) or ((not A6405) and (not A6417));
A6419 <= A6427 or A6404;
A6418 <= A6424 and A6405;
A6417 <= A6426 and A6425;
A6416 <= A6421 and A6405;
A6415 <= A6423 and A6422;
A6414 <= ((not A6415) and A6405) or (A6415 and (not A6405));
A6413 <= ((not A6403) and A6404) or (A6403 and (not A6404));
A6412 <= A6413 and A6420;
A6411 <= A6413 and A6419;
A6410 <= A6418 or A6417;
A6409 <= A6416 or A6415;
A6408 <= A6414 and A6413;
A6407 <= A8557;
A6406 <= A8524;
A6405 <= A8491;
A6404 <= A8458;
A6403 <= A8425;
A6402 <= A6380 and A6395;
A6401 <= (not A6380) and (not A6402);
A6400 <= A6380 or A6395;
A6399 <= (not A6373) or (not A6374);
A6398 <= A6380 or A6395;
A6397 <= (not A6396) and (not A6380);
A6396 <= A6380 and A6395;
A6395 <= (not A6371) or (not A6372);
A6394 <= A6372 and A6384;
A6393 <= A6373 or A6380;
A6392 <= A6373 or A6374;
A6391 <= (not A6401) or (not A6400);
A6390 <= A6399 and A6392;
A6389 <= ((not A6373) and A6380) or (A6373 and (not A6380));
A6388 <= (not A6397) or (not A6398);
A6387 <= (A6372 and A6384) or ((not A6372) and (not A6384));
A6386 <= A6394 or A6371;
A6385 <= A6391 and A6372;
A6384 <= A6393 and A6392;
A6383 <= A6388 and A6372;
A6382 <= A6390 and A6389;
A6381 <= ((not A6382) and A6372) or (A6382 and (not A6372));
A6380 <= ((not A6370) and A6371) or (A6370 and (not A6371));
A6379 <= A6380 and A6387;
A6378 <= A6380 and A6386;
A6377 <= A6385 or A6384;
A6376 <= A6383 or A6382;
A6375 <= A6381 and A6380;
A6374 <= A8392;
A6373 <= A8359;
A6372 <= A8326;
A6371 <= A8293;
A6370 <= A8260;
A6369 <= A6347 and A6362;
A6368 <= (not A6347) and (not A6369);
A6367 <= A6347 or A6362;
A6366 <= (not A6340) or (not A6341);
A6365 <= A6347 or A6362;
A6364 <= (not A6363) and (not A6347);
A6363 <= A6347 and A6362;
A6362 <= (not A6338) or (not A6339);
A6361 <= A6339 and A6351;
A6360 <= A6340 or A6347;
A6359 <= A6340 or A6341;
A6358 <= (not A6368) or (not A6367);
A6357 <= A6366 and A6359;
A6356 <= ((not A6340) and A6347) or (A6340 and (not A6347));
A6355 <= (not A6364) or (not A6365);
A6354 <= (A6339 and A6351) or ((not A6339) and (not A6351));
A6353 <= A6361 or A6338;
A6352 <= A6358 and A6339;
A6351 <= A6360 and A6359;
A6350 <= A6355 and A6339;
A6349 <= A6357 and A6356;
A6348 <= ((not A6349) and A6339) or (A6349 and (not A6339));
A6347 <= ((not A6337) and A6338) or (A6337 and (not A6338));
A6346 <= A6347 and A6354;
A6345 <= A6347 and A6353;
A6344 <= A6352 or A6351;
A6343 <= A6350 or A6349;
A6342 <= A6348 and A6347;
A6341 <= A8227;
A6340 <= A8194;
A6339 <= A8161;
A6338 <= A8128;
A6337 <= A8095;
A6336 <= A6314 and A6329;
A6335 <= (not A6314) and (not A6336);
A6334 <= A6314 or A6329;
A6333 <= (not A6307) or (not A6308);
A6332 <= A6314 or A6329;
A6331 <= (not A6330) and (not A6314);
A6330 <= A6314 and A6329;
A6329 <= (not A6305) or (not A6306);
A6328 <= A6306 and A6318;
A6327 <= A6307 or A6314;
A6326 <= A6307 or A6308;
A6325 <= (not A6335) or (not A6334);
A6324 <= A6333 and A6326;
A6323 <= ((not A6307) and A6314) or (A6307 and (not A6314));
A6322 <= (not A6331) or (not A6332);
A6321 <= (A6306 and A6318) or ((not A6306) and (not A6318));
A6320 <= A6328 or A6305;
A6319 <= A6325 and A6306;
A6318 <= A6327 and A6326;
A6317 <= A6322 and A6306;
A6316 <= A6324 and A6323;
A6315 <= ((not A6316) and A6306) or (A6316 and (not A6306));
A6314 <= ((not A6304) and A6305) or (A6304 and (not A6305));
A6313 <= A6314 and A6321;
A6312 <= A6314 and A6320;
A6311 <= A6319 or A6318;
A6310 <= A6317 or A6316;
A6309 <= A6315 and A6314;
A6308 <= A8062;
A6307 <= A8029;
A6306 <= A7996;
A6305 <= A7963;
A6304 <= A7930;
A6303 <= A6281 and A6296;
A6302 <= (not A6281) and (not A6303);
A6301 <= A6281 or A6296;
A6300 <= (not A6274) or (not A6275);
A6299 <= A6281 or A6296;
A6298 <= (not A6297) and (not A6281);
A6297 <= A6281 and A6296;
A6296 <= (not A6272) or (not A6273);
A6295 <= A6273 and A6285;
A6294 <= A6274 or A6281;
A6293 <= A6274 or A6275;
A6292 <= (not A6302) or (not A6301);
A6291 <= A6300 and A6293;
A6290 <= ((not A6274) and A6281) or (A6274 and (not A6281));
A6289 <= (not A6298) or (not A6299);
A6288 <= (A6273 and A6285) or ((not A6273) and (not A6285));
A6287 <= A6295 or A6272;
A6286 <= A6292 and A6273;
A6285 <= A6294 and A6293;
A6284 <= A6289 and A6273;
A6283 <= A6291 and A6290;
A6282 <= ((not A6283) and A6273) or (A6283 and (not A6273));
A6281 <= ((not A6271) and A6272) or (A6271 and (not A6272));
A6280 <= A6281 and A6288;
A6279 <= A6281 and A6287;
A6278 <= A6286 or A6285;
A6277 <= A6284 or A6283;
A6276 <= A6282 and A6281;
A6275 <= A7897;
A6274 <= A7864;
A6273 <= A7831;
A6272 <= A7798;
A6271 <= A7765;
A6270 <= A6248 and A6263;
A6269 <= (not A6248) and (not A6270);
A6268 <= A6248 or A6263;
A6267 <= (not A6241) or (not A6242);
A6266 <= A6248 or A6263;
A6265 <= (not A6264) and (not A6248);
A6264 <= A6248 and A6263;
A6263 <= (not A6239) or (not A6240);
A6262 <= A6240 and A6252;
A6261 <= A6241 or A6248;
A6260 <= A6241 or A6242;
A6259 <= (not A6269) or (not A6268);
A6258 <= A6267 and A6260;
A6257 <= ((not A6241) and A6248) or (A6241 and (not A6248));
A6256 <= (not A6265) or (not A6266);
A6255 <= (A6240 and A6252) or ((not A6240) and (not A6252));
A6254 <= A6262 or A6239;
A6253 <= A6259 and A6240;
A6252 <= A6261 and A6260;
A6251 <= A6256 and A6240;
A6250 <= A6258 and A6257;
A6249 <= ((not A6250) and A6240) or (A6250 and (not A6240));
A6248 <= ((not A6238) and A6239) or (A6238 and (not A6239));
A6247 <= A6248 and A6255;
A6246 <= A6248 and A6254;
A6245 <= A6253 or A6252;
A6244 <= A6251 or A6250;
A6243 <= A6249 and A6248;
A6242 <= A7732;
A6241 <= A7699;
A6240 <= A7666;
A6239 <= A7633;
A6238 <= A7600;
A6237 <= A6215 and A6230;
A6236 <= (not A6215) and (not A6237);
A6235 <= A6215 or A6230;
A6234 <= (not A6208) or (not A6209);
A6233 <= A6215 or A6230;
A6232 <= (not A6231) and (not A6215);
A6231 <= A6215 and A6230;
A6230 <= (not A6206) or (not A6207);
A6229 <= A6207 and A6219;
A6228 <= A6208 or A6215;
A6227 <= A6208 or A6209;
A6226 <= (not A6236) or (not A6235);
A6225 <= A6234 and A6227;
A6224 <= ((not A6208) and A6215) or (A6208 and (not A6215));
A6223 <= (not A6232) or (not A6233);
A6222 <= (A6207 and A6219) or ((not A6207) and (not A6219));
A6221 <= A6229 or A6206;
A6220 <= A6226 and A6207;
A6219 <= A6228 and A6227;
A6218 <= A6223 and A6207;
A6217 <= A6225 and A6224;
A6216 <= ((not A6217) and A6207) or (A6217 and (not A6207));
A6215 <= ((not A6205) and A6206) or (A6205 and (not A6206));
A6214 <= A6215 and A6222;
A6213 <= A6215 and A6221;
A6212 <= A6220 or A6219;
A6211 <= A6218 or A6217;
A6210 <= A6216 and A6215;
A6209 <= A7567;
A6208 <= A7534;
A6207 <= A7501;
A6206 <= A7468;
A6205 <= A7435;
A6204 <= A6182 and A6197;
A6203 <= (not A6182) and (not A6204);
A6202 <= A6182 or A6197;
A6201 <= (not A6175) or (not A6176);
A6200 <= A6182 or A6197;
A6199 <= (not A6198) and (not A6182);
A6198 <= A6182 and A6197;
A6197 <= (not A6173) or (not A6174);
A6196 <= A6174 and A6186;
A6195 <= A6175 or A6182;
A6194 <= A6175 or A6176;
A6193 <= (not A6203) or (not A6202);
A6192 <= A6201 and A6194;
A6191 <= ((not A6175) and A6182) or (A6175 and (not A6182));
A6190 <= (not A6199) or (not A6200);
A6189 <= (A6174 and A6186) or ((not A6174) and (not A6186));
A6188 <= A6196 or A6173;
A6187 <= A6193 and A6174;
A6186 <= A6195 and A6194;
A6185 <= A6190 and A6174;
A6184 <= A6192 and A6191;
A6183 <= ((not A6184) and A6174) or (A6184 and (not A6174));
A6182 <= ((not A6172) and A6173) or (A6172 and (not A6173));
A6181 <= A6182 and A6189;
A6180 <= A6182 and A6188;
A6179 <= A6187 or A6186;
A6178 <= A6185 or A6184;
A6177 <= A6183 and A6182;
A6176 <= A7402;
A6175 <= A7369;
A6174 <= A7336;
A6173 <= A7303;
A6172 <= A7270;
A6171 <= A6149 and A6164;
A6170 <= (not A6149) and (not A6171);
A6169 <= A6149 or A6164;
A6168 <= (not A6142) or (not A6143);
A6167 <= A6149 or A6164;
A6166 <= (not A6165) and (not A6149);
A6165 <= A6149 and A6164;
A6164 <= (not A6140) or (not A6141);
A6163 <= A6141 and A6153;
A6162 <= A6142 or A6149;
A6161 <= A6142 or A6143;
A6160 <= (not A6170) or (not A6169);
A6159 <= A6168 and A6161;
A6158 <= ((not A6142) and A6149) or (A6142 and (not A6149));
A6157 <= (not A6166) or (not A6167);
A6156 <= (A6141 and A6153) or ((not A6141) and (not A6153));
A6155 <= A6163 or A6140;
A6154 <= A6160 and A6141;
A6153 <= A6162 and A6161;
A6152 <= A6157 and A6141;
A6151 <= A6159 and A6158;
A6150 <= ((not A6151) and A6141) or (A6151 and (not A6141));
A6149 <= ((not A6139) and A6140) or (A6139 and (not A6140));
A6148 <= A6149 and A6156;
A6147 <= A6149 and A6155;
A6146 <= A6154 or A6153;
A6145 <= A6152 or A6151;
A6144 <= A6150 and A6149;
A6143 <= A7237;
A6142 <= A7204;
A6141 <= A7171;
A6140 <= A7138;
A6139 <= A7105;
A6138 <= A6116 and A6131;
A6137 <= (not A6116) and (not A6138);
A6136 <= A6116 or A6131;
A6135 <= (not A6109) or (not A6110);
A6134 <= A6116 or A6131;
A6133 <= (not A6132) and (not A6116);
A6132 <= A6116 and A6131;
A6131 <= (not A6107) or (not A6108);
A6130 <= A6108 and A6120;
A6129 <= A6109 or A6116;
A6128 <= A6109 or A6110;
A6127 <= (not A6137) or (not A6136);
A6126 <= A6135 and A6128;
A6125 <= ((not A6109) and A6116) or (A6109 and (not A6116));
A6124 <= (not A6133) or (not A6134);
A6123 <= (A6108 and A6120) or ((not A6108) and (not A6120));
A6122 <= A6130 or A6107;
A6121 <= A6127 and A6108;
A6120 <= A6129 and A6128;
A6119 <= A6124 and A6108;
A6118 <= A6126 and A6125;
A6117 <= ((not A6118) and A6108) or (A6118 and (not A6108));
A6116 <= ((not A6106) and A6107) or (A6106 and (not A6107));
A6115 <= A6116 and A6123;
A6114 <= A6116 and A6122;
A6113 <= A6121 or A6120;
A6112 <= A6119 or A6118;
A6111 <= A6117 and A6116;
A6110 <= A7072;
A6109 <= A7039;
A6108 <= A7006;
A6107 <= A6973;
A6106 <= A6936;
A6105 <= A6083 and A6098;
A6104 <= (not A6083) and (not A6105);
A6103 <= A6083 or A6098;
A6102 <= (not A6076) or (not A6077);
A6101 <= A6083 or A6098;
A6100 <= (not A6099) and (not A6083);
A6099 <= A6083 and A6098;
A6098 <= (not A6074) or (not A6075);
A6097 <= A6075 and A6087;
A6096 <= A6076 or A6083;
A6095 <= A6076 or A6077;
A6094 <= (not A6104) or (not A6103);
A6093 <= A6102 and A6095;
A6092 <= ((not A6076) and A6083) or (A6076 and (not A6083));
A6091 <= (not A6100) or (not A6101);
A6090 <= (A6075 and A6087) or ((not A6075) and (not A6087));
A6089 <= A6097 or A6074;
A6088 <= A6094 and A6075;
A6087 <= A6096 and A6095;
A6086 <= A6091 and A6075;
A6085 <= A6093 and A6092;
A6084 <= ((not A6085) and A6075) or (A6085 and (not A6075));
A6083 <= ((not A6073) and A6074) or (A6073 and (not A6074));
A6082 <= A6083 and A6090;
A6081 <= A6083 and A6089;
A6080 <= A6088 or A6087;
A6079 <= A6086 or A6085;
A6078 <= A6084 and A6083;
A6077 <= B1032;
A6076 <= B999;
A6075 <= B966;
A6074 <= B933;
A6073 <= B900;
A6072 <= A6050 and A6065;
A6071 <= (not A6050) and (not A6072);
A6070 <= A6050 or A6065;
A6069 <= (not A6043) or (not A6044);
A6068 <= A6050 or A6065;
A6067 <= (not A6066) and (not A6050);
A6066 <= A6050 and A6065;
A6065 <= (not A6041) or (not A6042);
A6064 <= A6042 and A6054;
A6063 <= A6043 or A6050;
A6062 <= A6043 or A6044;
A6061 <= (not A6071) or (not A6070);
A6060 <= A6069 and A6062;
A6059 <= ((not A6043) and A6050) or (A6043 and (not A6050));
A6058 <= (not A6067) or (not A6068);
A6057 <= (A6042 and A6054) or ((not A6042) and (not A6054));
A6056 <= A6064 or A6041;
A6055 <= A6061 and A6042;
A6054 <= A6063 and A6062;
A6053 <= A6058 and A6042;
A6052 <= A6060 and A6059;
A6051 <= ((not A6052) and A6042) or (A6052 and (not A6042));
A6050 <= ((not A6040) and A6041) or (A6040 and (not A6041));
A6049 <= A6050 and A6057;
A6048 <= A6050 and A6056;
A6047 <= A6055 or A6054;
A6046 <= A6053 or A6052;
A6045 <= A6051 and A6050;
A6044 <= B867;
A6043 <= B834;
A6042 <= B801;
A6041 <= B768;
A6040 <= B735;
A6039 <= A6017 and A6032;
A6038 <= (not A6017) and (not A6039);
A6037 <= A6017 or A6032;
A6036 <= (not A6010) or (not A6011);
A6035 <= A6017 or A6032;
A6034 <= (not A6033) and (not A6017);
A6033 <= A6017 and A6032;
A6032 <= (not A6008) or (not A6009);
A6031 <= A6009 and A6021;
A6030 <= A6010 or A6017;
A6029 <= A6010 or A6011;
A6028 <= (not A6038) or (not A6037);
A6027 <= A6036 and A6029;
A6026 <= ((not A6010) and A6017) or (A6010 and (not A6017));
A6025 <= (not A6034) or (not A6035);
A6024 <= (A6009 and A6021) or ((not A6009) and (not A6021));
A6023 <= A6031 or A6008;
A6022 <= A6028 and A6009;
A6021 <= A6030 and A6029;
A6020 <= A6025 and A6009;
A6019 <= A6027 and A6026;
A6018 <= ((not A6019) and A6009) or (A6019 and (not A6009));
A6017 <= ((not A6007) and A6008) or (A6007 and (not A6008));
A6016 <= A6017 and A6024;
A6015 <= A6017 and A6023;
A6014 <= A6022 or A6021;
A6013 <= A6020 or A6019;
A6012 <= A6018 and A6017;
A6011 <= B702;
A6010 <= B669;
A6009 <= B636;
A6008 <= B603;
A6007 <= B570;
A6006 <= A5984 and A5999;
A6005 <= (not A5984) and (not A6006);
A6004 <= A5984 or A5999;
A6003 <= (not A5977) or (not A5978);
A6002 <= A5984 or A5999;
A6001 <= (not A6000) and (not A5984);
A6000 <= A5984 and A5999;
A5999 <= (not A5975) or (not A5976);
A5998 <= A5976 and A5988;
A5997 <= A5977 or A5984;
A5996 <= A5977 or A5978;
A5995 <= (not A6005) or (not A6004);
A5994 <= A6003 and A5996;
A5993 <= ((not A5977) and A5984) or (A5977 and (not A5984));
A5992 <= (not A6001) or (not A6002);
A5991 <= (A5976 and A5988) or ((not A5976) and (not A5988));
A5990 <= A5998 or A5975;
A5989 <= A5995 and A5976;
A5988 <= A5997 and A5996;
A5987 <= A5992 and A5976;
A5986 <= A5994 and A5993;
A5985 <= ((not A5986) and A5976) or (A5986 and (not A5976));
A5984 <= ((not A5974) and A5975) or (A5974 and (not A5975));
A5983 <= A5984 and A5991;
A5982 <= A5984 and A5990;
A5981 <= A5989 or A5988;
A5980 <= A5987 or A5986;
A5979 <= A5985 and A5984;
A5978 <= B537;
A5977 <= B504;
A5976 <= B471;
A5975 <= B438;
A5974 <= B405;
A5973 <= A5951 and A5966;
A5972 <= (not A5951) and (not A5973);
A5971 <= A5951 or A5966;
A5970 <= (not A5944) or (not A5945);
A5969 <= A5951 or A5966;
A5968 <= (not A5967) and (not A5951);
A5967 <= A5951 and A5966;
A5966 <= (not A5942) or (not A5943);
A5965 <= A5943 and A5955;
A5964 <= A5944 or A5951;
A5963 <= A5944 or A5945;
A5962 <= (not A5972) or (not A5971);
A5961 <= A5970 and A5963;
A5960 <= ((not A5944) and A5951) or (A5944 and (not A5951));
A5959 <= (not A5968) or (not A5969);
A5958 <= (A5943 and A5955) or ((not A5943) and (not A5955));
A5957 <= A5965 or A5942;
A5956 <= A5962 and A5943;
A5955 <= A5964 and A5963;
A5954 <= A5959 and A5943;
A5953 <= A5961 and A5960;
A5952 <= ((not A5953) and A5943) or (A5953 and (not A5943));
A5951 <= ((not A5941) and A5942) or (A5941 and (not A5942));
A5950 <= A5951 and A5958;
A5949 <= A5951 and A5957;
A5948 <= A5956 or A5955;
A5947 <= A5954 or A5953;
A5946 <= A5952 and A5951;
A5945 <= B372;
A5944 <= B339;
A5943 <= B306;
A5942 <= B273;
A5941 <= B240;
A5940 <= A5918 and A5933;
A5939 <= (not A5918) and (not A5940);
A5938 <= A5918 or A5933;
A5937 <= (not A5911) or (not A5912);
A5936 <= A5918 or A5933;
A5935 <= (not A5934) and (not A5918);
A5934 <= A5918 and A5933;
A5933 <= (not A5909) or (not A5910);
A5932 <= A5910 and A5922;
A5931 <= A5911 or A5918;
A5930 <= A5911 or A5912;
A5929 <= (not A5939) or (not A5938);
A5928 <= A5937 and A5930;
A5927 <= ((not A5911) and A5918) or (A5911 and (not A5918));
A5926 <= (not A5935) or (not A5936);
A5925 <= (A5910 and A5922) or ((not A5910) and (not A5922));
A5924 <= A5932 or A5909;
A5923 <= A5929 and A5910;
A5922 <= A5931 and A5930;
A5921 <= A5926 and A5910;
A5920 <= A5928 and A5927;
A5919 <= ((not A5920) and A5910) or (A5920 and (not A5910));
A5918 <= ((not A5908) and A5909) or (A5908 and (not A5909));
A5917 <= A5918 and A5925;
A5916 <= A5918 and A5924;
A5915 <= A5923 or A5922;
A5914 <= A5921 or A5920;
A5913 <= A5919 and A5918;
A5912 <= B207;
A5911 <= B174;
A5910 <= B141;
A5909 <= B108;
A5908 <= B75;
A5907 <= A5885 and A5900;
A5906 <= (not A5885) and (not A5907);
A5905 <= A5885 or A5900;
A5904 <= (not A5878) or (not A5879);
A5903 <= A5885 or A5900;
A5902 <= (not A5901) and (not A5885);
A5901 <= A5885 and A5900;
A5900 <= (not A5876) or (not A5877);
A5899 <= A5877 and A5889;
A5898 <= A5878 or A5885;
A5897 <= A5878 or A5879;
A5896 <= (not A5906) or (not A5905);
A5895 <= A5904 and A5897;
A5894 <= ((not A5878) and A5885) or (A5878 and (not A5885));
A5893 <= (not A5902) or (not A5903);
A5892 <= (A5877 and A5889) or ((not A5877) and (not A5889));
A5891 <= A5899 or A5876;
A5890 <= A5896 and A5877;
A5889 <= A5898 and A5897;
A5888 <= A5893 and A5877;
A5887 <= A5895 and A5894;
A5886 <= ((not A5887) and A5877) or (A5887 and (not A5877));
A5885 <= ((not A5875) and A5876) or (A5875 and (not A5876));
A5884 <= A5885 and A5892;
A5883 <= A5885 and A5891;
A5882 <= A5890 or A5889;
A5881 <= A5888 or A5887;
A5880 <= A5886 and A5885;
A5879 <= B42;
A5878 <= B9;
A5877 <= A9975;
A5876 <= A9942;
A5875 <= A9909;
A5874 <= A5852 and A5867;
A5873 <= (not A5852) and (not A5874);
A5872 <= A5852 or A5867;
A5871 <= (not A5845) or (not A5846);
A5870 <= A5852 or A5867;
A5869 <= (not A5868) and (not A5852);
A5868 <= A5852 and A5867;
A5867 <= (not A5843) or (not A5844);
A5866 <= A5844 and A5856;
A5865 <= A5845 or A5852;
A5864 <= A5845 or A5846;
A5863 <= (not A5873) or (not A5872);
A5862 <= A5871 and A5864;
A5861 <= ((not A5845) and A5852) or (A5845 and (not A5852));
A5860 <= (not A5869) or (not A5870);
A5859 <= (A5844 and A5856) or ((not A5844) and (not A5856));
A5858 <= A5866 or A5843;
A5857 <= A5863 and A5844;
A5856 <= A5865 and A5864;
A5855 <= A5860 and A5844;
A5854 <= A5862 and A5861;
A5853 <= ((not A5854) and A5844) or (A5854 and (not A5844));
A5852 <= ((not A5842) and A5843) or (A5842 and (not A5843));
A5851 <= A5852 and A5859;
A5850 <= A5852 and A5858;
A5849 <= A5857 or A5856;
A5848 <= A5855 or A5854;
A5847 <= A5853 and A5852;
A5846 <= A9876;
A5845 <= A9843;
A5844 <= A9810;
A5843 <= A9777;
A5842 <= A9744;
A5841 <= A5819 and A5834;
A5840 <= (not A5819) and (not A5841);
A5839 <= A5819 or A5834;
A5838 <= (not A5812) or (not A5813);
A5837 <= A5819 or A5834;
A5836 <= (not A5835) and (not A5819);
A5835 <= A5819 and A5834;
A5834 <= (not A5810) or (not A5811);
A5833 <= A5811 and A5823;
A5832 <= A5812 or A5819;
A5831 <= A5812 or A5813;
A5830 <= (not A5840) or (not A5839);
A5829 <= A5838 and A5831;
A5828 <= ((not A5812) and A5819) or (A5812 and (not A5819));
A5827 <= (not A5836) or (not A5837);
A5826 <= (A5811 and A5823) or ((not A5811) and (not A5823));
A5825 <= A5833 or A5810;
A5824 <= A5830 and A5811;
A5823 <= A5832 and A5831;
A5822 <= A5827 and A5811;
A5821 <= A5829 and A5828;
A5820 <= ((not A5821) and A5811) or (A5821 and (not A5811));
A5819 <= ((not A5809) and A5810) or (A5809 and (not A5810));
A5818 <= A5819 and A5826;
A5817 <= A5819 and A5825;
A5816 <= A5824 or A5823;
A5815 <= A5822 or A5821;
A5814 <= A5820 and A5819;
A5813 <= A9711;
A5812 <= A9678;
A5811 <= A9645;
A5810 <= A9612;
A5809 <= A9579;
A5808 <= A5786 and A5801;
A5807 <= (not A5786) and (not A5808);
A5806 <= A5786 or A5801;
A5805 <= (not A5779) or (not A5780);
A5804 <= A5786 or A5801;
A5803 <= (not A5802) and (not A5786);
A5802 <= A5786 and A5801;
A5801 <= (not A5777) or (not A5778);
A5800 <= A5778 and A5790;
A5799 <= A5779 or A5786;
A5798 <= A5779 or A5780;
A5797 <= (not A5807) or (not A5806);
A5796 <= A5805 and A5798;
A5795 <= ((not A5779) and A5786) or (A5779 and (not A5786));
A5794 <= (not A5803) or (not A5804);
A5793 <= (A5778 and A5790) or ((not A5778) and (not A5790));
A5792 <= A5800 or A5777;
A5791 <= A5797 and A5778;
A5790 <= A5799 and A5798;
A5789 <= A5794 and A5778;
A5788 <= A5796 and A5795;
A5787 <= ((not A5788) and A5778) or (A5788 and (not A5778));
A5786 <= ((not A5776) and A5777) or (A5776 and (not A5777));
A5785 <= A5786 and A5793;
A5784 <= A5786 and A5792;
A5783 <= A5791 or A5790;
A5782 <= A5789 or A5788;
A5781 <= A5787 and A5786;
A5780 <= A9546;
A5779 <= A9513;
A5778 <= A9480;
A5777 <= A9447;
A5776 <= A9414;
A5775 <= A5753 and A5768;
A5774 <= (not A5753) and (not A5775);
A5773 <= A5753 or A5768;
A5772 <= (not A5746) or (not A5747);
A5771 <= A5753 or A5768;
A5770 <= (not A5769) and (not A5753);
A5769 <= A5753 and A5768;
A5768 <= (not A5744) or (not A5745);
A5767 <= A5745 and A5757;
A5766 <= A5746 or A5753;
A5765 <= A5746 or A5747;
A5764 <= (not A5774) or (not A5773);
A5763 <= A5772 and A5765;
A5762 <= ((not A5746) and A5753) or (A5746 and (not A5753));
A5761 <= (not A5770) or (not A5771);
A5760 <= (A5745 and A5757) or ((not A5745) and (not A5757));
A5759 <= A5767 or A5744;
A5758 <= A5764 and A5745;
A5757 <= A5766 and A5765;
A5756 <= A5761 and A5745;
A5755 <= A5763 and A5762;
A5754 <= ((not A5755) and A5745) or (A5755 and (not A5745));
A5753 <= ((not A5743) and A5744) or (A5743 and (not A5744));
A5752 <= A5753 and A5760;
A5751 <= A5753 and A5759;
A5750 <= A5758 or A5757;
A5749 <= A5756 or A5755;
A5748 <= A5754 and A5753;
A5747 <= A9381;
A5746 <= A9348;
A5745 <= A9315;
A5744 <= A9282;
A5743 <= A9249;
A5742 <= A5720 and A5735;
A5741 <= (not A5720) and (not A5742);
A5740 <= A5720 or A5735;
A5739 <= (not A5713) or (not A5714);
A5738 <= A5720 or A5735;
A5737 <= (not A5736) and (not A5720);
A5736 <= A5720 and A5735;
A5735 <= (not A5711) or (not A5712);
A5734 <= A5712 and A5724;
A5733 <= A5713 or A5720;
A5732 <= A5713 or A5714;
A5731 <= (not A5741) or (not A5740);
A5730 <= A5739 and A5732;
A5729 <= ((not A5713) and A5720) or (A5713 and (not A5720));
A5728 <= (not A5737) or (not A5738);
A5727 <= (A5712 and A5724) or ((not A5712) and (not A5724));
A5726 <= A5734 or A5711;
A5725 <= A5731 and A5712;
A5724 <= A5733 and A5732;
A5723 <= A5728 and A5712;
A5722 <= A5730 and A5729;
A5721 <= ((not A5722) and A5712) or (A5722 and (not A5712));
A5720 <= ((not A5710) and A5711) or (A5710 and (not A5711));
A5719 <= A5720 and A5727;
A5718 <= A5720 and A5726;
A5717 <= A5725 or A5724;
A5716 <= A5723 or A5722;
A5715 <= A5721 and A5720;
A5714 <= A9216;
A5713 <= A9183;
A5712 <= A9150;
A5711 <= A9117;
A5710 <= A9084;
A5709 <= A5687 and A5702;
A5708 <= (not A5687) and (not A5709);
A5707 <= A5687 or A5702;
A5706 <= (not A5680) or (not A5681);
A5705 <= A5687 or A5702;
A5704 <= (not A5703) and (not A5687);
A5703 <= A5687 and A5702;
A5702 <= (not A5678) or (not A5679);
A5701 <= A5679 and A5691;
A5700 <= A5680 or A5687;
A5699 <= A5680 or A5681;
A5698 <= (not A5708) or (not A5707);
A5697 <= A5706 and A5699;
A5696 <= ((not A5680) and A5687) or (A5680 and (not A5687));
A5695 <= (not A5704) or (not A5705);
A5694 <= (A5679 and A5691) or ((not A5679) and (not A5691));
A5693 <= A5701 or A5678;
A5692 <= A5698 and A5679;
A5691 <= A5700 and A5699;
A5690 <= A5695 and A5679;
A5689 <= A5697 and A5696;
A5688 <= ((not A5689) and A5679) or (A5689 and (not A5679));
A5687 <= ((not A5677) and A5678) or (A5677 and (not A5678));
A5686 <= A5687 and A5694;
A5685 <= A5687 and A5693;
A5684 <= A5692 or A5691;
A5683 <= A5690 or A5689;
A5682 <= A5688 and A5687;
A5681 <= A9051;
A5680 <= A9018;
A5679 <= A8985;
A5678 <= A8952;
A5677 <= A8919;
A5676 <= A5654 and A5669;
A5675 <= (not A5654) and (not A5676);
A5674 <= A5654 or A5669;
A5673 <= (not A5647) or (not A5648);
A5672 <= A5654 or A5669;
A5671 <= (not A5670) and (not A5654);
A5670 <= A5654 and A5669;
A5669 <= (not A5645) or (not A5646);
A5668 <= A5646 and A5658;
A5667 <= A5647 or A5654;
A5666 <= A5647 or A5648;
A5665 <= (not A5675) or (not A5674);
A5664 <= A5673 and A5666;
A5663 <= ((not A5647) and A5654) or (A5647 and (not A5654));
A5662 <= (not A5671) or (not A5672);
A5661 <= (A5646 and A5658) or ((not A5646) and (not A5658));
A5660 <= A5668 or A5645;
A5659 <= A5665 and A5646;
A5658 <= A5667 and A5666;
A5657 <= A5662 and A5646;
A5656 <= A5664 and A5663;
A5655 <= ((not A5656) and A5646) or (A5656 and (not A5646));
A5654 <= ((not A5644) and A5645) or (A5644 and (not A5645));
A5653 <= A5654 and A5661;
A5652 <= A5654 and A5660;
A5651 <= A5659 or A5658;
A5650 <= A5657 or A5656;
A5649 <= A5655 and A5654;
A5648 <= A8886;
A5647 <= A8853;
A5646 <= A8820;
A5645 <= A8787;
A5644 <= A8754;
A5643 <= A5621 and A5636;
A5642 <= (not A5621) and (not A5643);
A5641 <= A5621 or A5636;
A5640 <= (not A5614) or (not A5615);
A5639 <= A5621 or A5636;
A5638 <= (not A5637) and (not A5621);
A5637 <= A5621 and A5636;
A5636 <= (not A5612) or (not A5613);
A5635 <= A5613 and A5625;
A5634 <= A5614 or A5621;
A5633 <= A5614 or A5615;
A5632 <= (not A5642) or (not A5641);
A5631 <= A5640 and A5633;
A5630 <= ((not A5614) and A5621) or (A5614 and (not A5621));
A5629 <= (not A5638) or (not A5639);
A5628 <= (A5613 and A5625) or ((not A5613) and (not A5625));
A5627 <= A5635 or A5612;
A5626 <= A5632 and A5613;
A5625 <= A5634 and A5633;
A5624 <= A5629 and A5613;
A5623 <= A5631 and A5630;
A5622 <= ((not A5623) and A5613) or (A5623 and (not A5613));
A5621 <= ((not A5611) and A5612) or (A5611 and (not A5612));
A5620 <= A5621 and A5628;
A5619 <= A5621 and A5627;
A5618 <= A5626 or A5625;
A5617 <= A5624 or A5623;
A5616 <= A5622 and A5621;
A5615 <= A8721;
A5614 <= A8688;
A5613 <= A8655;
A5612 <= A8622;
A5611 <= A8589;
A5610 <= A5588 and A5603;
A5609 <= (not A5588) and (not A5610);
A5608 <= A5588 or A5603;
A5607 <= (not A5581) or (not A5582);
A5606 <= A5588 or A5603;
A5605 <= (not A5604) and (not A5588);
A5604 <= A5588 and A5603;
A5603 <= (not A5579) or (not A5580);
A5602 <= A5580 and A5592;
A5601 <= A5581 or A5588;
A5600 <= A5581 or A5582;
A5599 <= (not A5609) or (not A5608);
A5598 <= A5607 and A5600;
A5597 <= ((not A5581) and A5588) or (A5581 and (not A5588));
A5596 <= (not A5605) or (not A5606);
A5595 <= (A5580 and A5592) or ((not A5580) and (not A5592));
A5594 <= A5602 or A5579;
A5593 <= A5599 and A5580;
A5592 <= A5601 and A5600;
A5591 <= A5596 and A5580;
A5590 <= A5598 and A5597;
A5589 <= ((not A5590) and A5580) or (A5590 and (not A5580));
A5588 <= ((not A5578) and A5579) or (A5578 and (not A5579));
A5587 <= A5588 and A5595;
A5586 <= A5588 and A5594;
A5585 <= A5593 or A5592;
A5584 <= A5591 or A5590;
A5583 <= A5589 and A5588;
A5582 <= A8556;
A5581 <= A8523;
A5580 <= A8490;
A5579 <= A8457;
A5578 <= A8424;
A5577 <= A5555 and A5570;
A5576 <= (not A5555) and (not A5577);
A5575 <= A5555 or A5570;
A5574 <= (not A5548) or (not A5549);
A5573 <= A5555 or A5570;
A5572 <= (not A5571) and (not A5555);
A5571 <= A5555 and A5570;
A5570 <= (not A5546) or (not A5547);
A5569 <= A5547 and A5559;
A5568 <= A5548 or A5555;
A5567 <= A5548 or A5549;
A5566 <= (not A5576) or (not A5575);
A5565 <= A5574 and A5567;
A5564 <= ((not A5548) and A5555) or (A5548 and (not A5555));
A5563 <= (not A5572) or (not A5573);
A5562 <= (A5547 and A5559) or ((not A5547) and (not A5559));
A5561 <= A5569 or A5546;
A5560 <= A5566 and A5547;
A5559 <= A5568 and A5567;
A5558 <= A5563 and A5547;
A5557 <= A5565 and A5564;
A5556 <= ((not A5557) and A5547) or (A5557 and (not A5547));
A5555 <= ((not A5545) and A5546) or (A5545 and (not A5546));
A5554 <= A5555 and A5562;
A5553 <= A5555 and A5561;
A5552 <= A5560 or A5559;
A5551 <= A5558 or A5557;
A5550 <= A5556 and A5555;
A5549 <= A8391;
A5548 <= A8358;
A5547 <= A8325;
A5546 <= A8292;
A5545 <= A8259;
A5544 <= A5522 and A5537;
A5543 <= (not A5522) and (not A5544);
A5542 <= A5522 or A5537;
A5541 <= (not A5515) or (not A5516);
A5540 <= A5522 or A5537;
A5539 <= (not A5538) and (not A5522);
A5538 <= A5522 and A5537;
A5537 <= (not A5513) or (not A5514);
A5536 <= A5514 and A5526;
A5535 <= A5515 or A5522;
A5534 <= A5515 or A5516;
A5533 <= (not A5543) or (not A5542);
A5532 <= A5541 and A5534;
A5531 <= ((not A5515) and A5522) or (A5515 and (not A5522));
A5530 <= (not A5539) or (not A5540);
A5529 <= (A5514 and A5526) or ((not A5514) and (not A5526));
A5528 <= A5536 or A5513;
A5527 <= A5533 and A5514;
A5526 <= A5535 and A5534;
A5525 <= A5530 and A5514;
A5524 <= A5532 and A5531;
A5523 <= ((not A5524) and A5514) or (A5524 and (not A5514));
A5522 <= ((not A5512) and A5513) or (A5512 and (not A5513));
A5521 <= A5522 and A5529;
A5520 <= A5522 and A5528;
A5519 <= A5527 or A5526;
A5518 <= A5525 or A5524;
A5517 <= A5523 and A5522;
A5516 <= A8226;
A5515 <= A8193;
A5514 <= A8160;
A5513 <= A8127;
A5512 <= A8094;
A5511 <= A5489 and A5504;
A5510 <= (not A5489) and (not A5511);
A5509 <= A5489 or A5504;
A5508 <= (not A5482) or (not A5483);
A5507 <= A5489 or A5504;
A5506 <= (not A5505) and (not A5489);
A5505 <= A5489 and A5504;
A5504 <= (not A5480) or (not A5481);
A5503 <= A5481 and A5493;
A5502 <= A5482 or A5489;
A5501 <= A5482 or A5483;
A5500 <= (not A5510) or (not A5509);
A5499 <= A5508 and A5501;
A5498 <= ((not A5482) and A5489) or (A5482 and (not A5489));
A5497 <= (not A5506) or (not A5507);
A5496 <= (A5481 and A5493) or ((not A5481) and (not A5493));
A5495 <= A5503 or A5480;
A5494 <= A5500 and A5481;
A5493 <= A5502 and A5501;
A5492 <= A5497 and A5481;
A5491 <= A5499 and A5498;
A5490 <= ((not A5491) and A5481) or (A5491 and (not A5481));
A5489 <= ((not A5479) and A5480) or (A5479 and (not A5480));
A5488 <= A5489 and A5496;
A5487 <= A5489 and A5495;
A5486 <= A5494 or A5493;
A5485 <= A5492 or A5491;
A5484 <= A5490 and A5489;
A5483 <= A8061;
A5482 <= A8028;
A5481 <= A7995;
A5480 <= A7962;
A5479 <= A7929;
A5478 <= A5456 and A5471;
A5477 <= (not A5456) and (not A5478);
A5476 <= A5456 or A5471;
A5475 <= (not A5449) or (not A5450);
A5474 <= A5456 or A5471;
A5473 <= (not A5472) and (not A5456);
A5472 <= A5456 and A5471;
A5471 <= (not A5447) or (not A5448);
A5470 <= A5448 and A5460;
A5469 <= A5449 or A5456;
A5468 <= A5449 or A5450;
A5467 <= (not A5477) or (not A5476);
A5466 <= A5475 and A5468;
A5465 <= ((not A5449) and A5456) or (A5449 and (not A5456));
A5464 <= (not A5473) or (not A5474);
A5463 <= (A5448 and A5460) or ((not A5448) and (not A5460));
A5462 <= A5470 or A5447;
A5461 <= A5467 and A5448;
A5460 <= A5469 and A5468;
A5459 <= A5464 and A5448;
A5458 <= A5466 and A5465;
A5457 <= ((not A5458) and A5448) or (A5458 and (not A5448));
A5456 <= ((not A5446) and A5447) or (A5446 and (not A5447));
A5455 <= A5456 and A5463;
A5454 <= A5456 and A5462;
A5453 <= A5461 or A5460;
A5452 <= A5459 or A5458;
A5451 <= A5457 and A5456;
A5450 <= A7896;
A5449 <= A7863;
A5448 <= A7830;
A5447 <= A7797;
A5446 <= A7764;
A5445 <= A5423 and A5438;
A5444 <= (not A5423) and (not A5445);
A5443 <= A5423 or A5438;
A5442 <= (not A5416) or (not A5417);
A5441 <= A5423 or A5438;
A5440 <= (not A5439) and (not A5423);
A5439 <= A5423 and A5438;
A5438 <= (not A5414) or (not A5415);
A5437 <= A5415 and A5427;
A5436 <= A5416 or A5423;
A5435 <= A5416 or A5417;
A5434 <= (not A5444) or (not A5443);
A5433 <= A5442 and A5435;
A5432 <= ((not A5416) and A5423) or (A5416 and (not A5423));
A5431 <= (not A5440) or (not A5441);
A5430 <= (A5415 and A5427) or ((not A5415) and (not A5427));
A5429 <= A5437 or A5414;
A5428 <= A5434 and A5415;
A5427 <= A5436 and A5435;
A5426 <= A5431 and A5415;
A5425 <= A5433 and A5432;
A5424 <= ((not A5425) and A5415) or (A5425 and (not A5415));
A5423 <= ((not A5413) and A5414) or (A5413 and (not A5414));
A5422 <= A5423 and A5430;
A5421 <= A5423 and A5429;
A5420 <= A5428 or A5427;
A5419 <= A5426 or A5425;
A5418 <= A5424 and A5423;
A5417 <= A7731;
A5416 <= A7698;
A5415 <= A7665;
A5414 <= A7632;
A5413 <= A7599;
A5412 <= A5390 and A5405;
A5411 <= (not A5390) and (not A5412);
A5410 <= A5390 or A5405;
A5409 <= (not A5383) or (not A5384);
A5408 <= A5390 or A5405;
A5407 <= (not A5406) and (not A5390);
A5406 <= A5390 and A5405;
A5405 <= (not A5381) or (not A5382);
A5404 <= A5382 and A5394;
A5403 <= A5383 or A5390;
A5402 <= A5383 or A5384;
A5401 <= (not A5411) or (not A5410);
A5400 <= A5409 and A5402;
A5399 <= ((not A5383) and A5390) or (A5383 and (not A5390));
A5398 <= (not A5407) or (not A5408);
A5397 <= (A5382 and A5394) or ((not A5382) and (not A5394));
A5396 <= A5404 or A5381;
A5395 <= A5401 and A5382;
A5394 <= A5403 and A5402;
A5393 <= A5398 and A5382;
A5392 <= A5400 and A5399;
A5391 <= ((not A5392) and A5382) or (A5392 and (not A5382));
A5390 <= ((not A5380) and A5381) or (A5380 and (not A5381));
A5389 <= A5390 and A5397;
A5388 <= A5390 and A5396;
A5387 <= A5395 or A5394;
A5386 <= A5393 or A5392;
A5385 <= A5391 and A5390;
A5384 <= A7566;
A5383 <= A7533;
A5382 <= A7500;
A5381 <= A7467;
A5380 <= A7434;
A5379 <= A5357 and A5372;
A5378 <= (not A5357) and (not A5379);
A5377 <= A5357 or A5372;
A5376 <= (not A5350) or (not A5351);
A5375 <= A5357 or A5372;
A5374 <= (not A5373) and (not A5357);
A5373 <= A5357 and A5372;
A5372 <= (not A5348) or (not A5349);
A5371 <= A5349 and A5361;
A5370 <= A5350 or A5357;
A5369 <= A5350 or A5351;
A5368 <= (not A5378) or (not A5377);
A5367 <= A5376 and A5369;
A5366 <= ((not A5350) and A5357) or (A5350 and (not A5357));
A5365 <= (not A5374) or (not A5375);
A5364 <= (A5349 and A5361) or ((not A5349) and (not A5361));
A5363 <= A5371 or A5348;
A5362 <= A5368 and A5349;
A5361 <= A5370 and A5369;
A5360 <= A5365 and A5349;
A5359 <= A5367 and A5366;
A5358 <= ((not A5359) and A5349) or (A5359 and (not A5349));
A5357 <= ((not A5347) and A5348) or (A5347 and (not A5348));
A5356 <= A5357 and A5364;
A5355 <= A5357 and A5363;
A5354 <= A5362 or A5361;
A5353 <= A5360 or A5359;
A5352 <= A5358 and A5357;
A5351 <= A7401;
A5350 <= A7368;
A5349 <= A7335;
A5348 <= A7302;
A5347 <= A7269;
A5346 <= A5324 and A5339;
A5345 <= (not A5324) and (not A5346);
A5344 <= A5324 or A5339;
A5343 <= (not A5317) or (not A5318);
A5342 <= A5324 or A5339;
A5341 <= (not A5340) and (not A5324);
A5340 <= A5324 and A5339;
A5339 <= (not A5315) or (not A5316);
A5338 <= A5316 and A5328;
A5337 <= A5317 or A5324;
A5336 <= A5317 or A5318;
A5335 <= (not A5345) or (not A5344);
A5334 <= A5343 and A5336;
A5333 <= ((not A5317) and A5324) or (A5317 and (not A5324));
A5332 <= (not A5341) or (not A5342);
A5331 <= (A5316 and A5328) or ((not A5316) and (not A5328));
A5330 <= A5338 or A5315;
A5329 <= A5335 and A5316;
A5328 <= A5337 and A5336;
A5327 <= A5332 and A5316;
A5326 <= A5334 and A5333;
A5325 <= ((not A5326) and A5316) or (A5326 and (not A5316));
A5324 <= ((not A5314) and A5315) or (A5314 and (not A5315));
A5323 <= A5324 and A5331;
A5322 <= A5324 and A5330;
A5321 <= A5329 or A5328;
A5320 <= A5327 or A5326;
A5319 <= A5325 and A5324;
A5318 <= A7236;
A5317 <= A7203;
A5316 <= A7170;
A5315 <= A7137;
A5314 <= A7104;
A5313 <= A5291 and A5306;
A5312 <= (not A5291) and (not A5313);
A5311 <= A5291 or A5306;
A5310 <= (not A5284) or (not A5285);
A5309 <= A5291 or A5306;
A5308 <= (not A5307) and (not A5291);
A5307 <= A5291 and A5306;
A5306 <= (not A5282) or (not A5283);
A5305 <= A5283 and A5295;
A5304 <= A5284 or A5291;
A5303 <= A5284 or A5285;
A5302 <= (not A5312) or (not A5311);
A5301 <= A5310 and A5303;
A5300 <= ((not A5284) and A5291) or (A5284 and (not A5291));
A5299 <= (not A5308) or (not A5309);
A5298 <= (A5283 and A5295) or ((not A5283) and (not A5295));
A5297 <= A5305 or A5282;
A5296 <= A5302 and A5283;
A5295 <= A5304 and A5303;
A5294 <= A5299 and A5283;
A5293 <= A5301 and A5300;
A5292 <= ((not A5293) and A5283) or (A5293 and (not A5283));
A5291 <= ((not A5281) and A5282) or (A5281 and (not A5282));
A5290 <= A5291 and A5298;
A5289 <= A5291 and A5297;
A5288 <= A5296 or A5295;
A5287 <= A5294 or A5293;
A5286 <= A5292 and A5291;
A5285 <= A7071;
A5284 <= A7038;
A5283 <= A7005;
A5282 <= A6972;
A5281 <= A6937;
A5280 <= A5258 and A5273;
A5279 <= (not A5258) and (not A5280);
A5278 <= A5258 or A5273;
A5277 <= (not A5251) or (not A5252);
A5276 <= A5258 or A5273;
A5275 <= (not A5274) and (not A5258);
A5274 <= A5258 and A5273;
A5273 <= (not A5249) or (not A5250);
A5272 <= A5250 and A5262;
A5271 <= A5251 or A5258;
A5270 <= A5251 or A5252;
A5269 <= (not A5279) or (not A5278);
A5268 <= A5277 and A5270;
A5267 <= ((not A5251) and A5258) or (A5251 and (not A5258));
A5266 <= (not A5275) or (not A5276);
A5265 <= (A5250 and A5262) or ((not A5250) and (not A5262));
A5264 <= A5272 or A5249;
A5263 <= A5269 and A5250;
A5262 <= A5271 and A5270;
A5261 <= A5266 and A5250;
A5260 <= A5268 and A5267;
A5259 <= ((not A5260) and A5250) or (A5260 and (not A5250));
A5258 <= ((not A5248) and A5249) or (A5248 and (not A5249));
A5257 <= A5258 and A5265;
A5256 <= A5258 and A5264;
A5255 <= A5263 or A5262;
A5254 <= A5261 or A5260;
A5253 <= A5259 and A5258;
A5252 <= B1031;
A5251 <= B998;
A5250 <= B965;
A5249 <= B932;
A5248 <= B899;
A5247 <= A5225 and A5240;
A5246 <= (not A5225) and (not A5247);
A5245 <= A5225 or A5240;
A5244 <= (not A5218) or (not A5219);
A5243 <= A5225 or A5240;
A5242 <= (not A5241) and (not A5225);
A5241 <= A5225 and A5240;
A5240 <= (not A5216) or (not A5217);
A5239 <= A5217 and A5229;
A5238 <= A5218 or A5225;
A5237 <= A5218 or A5219;
A5236 <= (not A5246) or (not A5245);
A5235 <= A5244 and A5237;
A5234 <= ((not A5218) and A5225) or (A5218 and (not A5225));
A5233 <= (not A5242) or (not A5243);
A5232 <= (A5217 and A5229) or ((not A5217) and (not A5229));
A5231 <= A5239 or A5216;
A5230 <= A5236 and A5217;
A5229 <= A5238 and A5237;
A5228 <= A5233 and A5217;
A5227 <= A5235 and A5234;
A5226 <= ((not A5227) and A5217) or (A5227 and (not A5217));
A5225 <= ((not A5215) and A5216) or (A5215 and (not A5216));
A5224 <= A5225 and A5232;
A5223 <= A5225 and A5231;
A5222 <= A5230 or A5229;
A5221 <= A5228 or A5227;
A5220 <= A5226 and A5225;
A5219 <= B866;
A5218 <= B833;
A5217 <= B800;
A5216 <= B767;
A5215 <= B734;
A5214 <= A5192 and A5207;
A5213 <= (not A5192) and (not A5214);
A5212 <= A5192 or A5207;
A5211 <= (not A5185) or (not A5186);
A5210 <= A5192 or A5207;
A5209 <= (not A5208) and (not A5192);
A5208 <= A5192 and A5207;
A5207 <= (not A5183) or (not A5184);
A5206 <= A5184 and A5196;
A5205 <= A5185 or A5192;
A5204 <= A5185 or A5186;
A5203 <= (not A5213) or (not A5212);
A5202 <= A5211 and A5204;
A5201 <= ((not A5185) and A5192) or (A5185 and (not A5192));
A5200 <= (not A5209) or (not A5210);
A5199 <= (A5184 and A5196) or ((not A5184) and (not A5196));
A5198 <= A5206 or A5183;
A5197 <= A5203 and A5184;
A5196 <= A5205 and A5204;
A5195 <= A5200 and A5184;
A5194 <= A5202 and A5201;
A5193 <= ((not A5194) and A5184) or (A5194 and (not A5184));
A5192 <= ((not A5182) and A5183) or (A5182 and (not A5183));
A5191 <= A5192 and A5199;
A5190 <= A5192 and A5198;
A5189 <= A5197 or A5196;
A5188 <= A5195 or A5194;
A5187 <= A5193 and A5192;
A5186 <= B701;
A5185 <= B668;
A5184 <= B635;
A5183 <= B602;
A5182 <= B569;
A5181 <= A5159 and A5174;
A5180 <= (not A5159) and (not A5181);
A5179 <= A5159 or A5174;
A5178 <= (not A5152) or (not A5153);
A5177 <= A5159 or A5174;
A5176 <= (not A5175) and (not A5159);
A5175 <= A5159 and A5174;
A5174 <= (not A5150) or (not A5151);
A5173 <= A5151 and A5163;
A5172 <= A5152 or A5159;
A5171 <= A5152 or A5153;
A5170 <= (not A5180) or (not A5179);
A5169 <= A5178 and A5171;
A5168 <= ((not A5152) and A5159) or (A5152 and (not A5159));
A5167 <= (not A5176) or (not A5177);
A5166 <= (A5151 and A5163) or ((not A5151) and (not A5163));
A5165 <= A5173 or A5150;
A5164 <= A5170 and A5151;
A5163 <= A5172 and A5171;
A5162 <= A5167 and A5151;
A5161 <= A5169 and A5168;
A5160 <= ((not A5161) and A5151) or (A5161 and (not A5151));
A5159 <= ((not A5149) and A5150) or (A5149 and (not A5150));
A5158 <= A5159 and A5166;
A5157 <= A5159 and A5165;
A5156 <= A5164 or A5163;
A5155 <= A5162 or A5161;
A5154 <= A5160 and A5159;
A5153 <= B536;
A5152 <= B503;
A5151 <= B470;
A5150 <= B437;
A5149 <= B404;
A5148 <= A5126 and A5141;
A5147 <= (not A5126) and (not A5148);
A5146 <= A5126 or A5141;
A5145 <= (not A5119) or (not A5120);
A5144 <= A5126 or A5141;
A5143 <= (not A5142) and (not A5126);
A5142 <= A5126 and A5141;
A5141 <= (not A5117) or (not A5118);
A5140 <= A5118 and A5130;
A5139 <= A5119 or A5126;
A5138 <= A5119 or A5120;
A5137 <= (not A5147) or (not A5146);
A5136 <= A5145 and A5138;
A5135 <= ((not A5119) and A5126) or (A5119 and (not A5126));
A5134 <= (not A5143) or (not A5144);
A5133 <= (A5118 and A5130) or ((not A5118) and (not A5130));
A5132 <= A5140 or A5117;
A5131 <= A5137 and A5118;
A5130 <= A5139 and A5138;
A5129 <= A5134 and A5118;
A5128 <= A5136 and A5135;
A5127 <= ((not A5128) and A5118) or (A5128 and (not A5118));
A5126 <= ((not A5116) and A5117) or (A5116 and (not A5117));
A5125 <= A5126 and A5133;
A5124 <= A5126 and A5132;
A5123 <= A5131 or A5130;
A5122 <= A5129 or A5128;
A5121 <= A5127 and A5126;
A5120 <= B371;
A5119 <= B338;
A5118 <= B305;
A5117 <= B272;
A5116 <= B239;
A5115 <= A5093 and A5108;
A5114 <= (not A5093) and (not A5115);
A5113 <= A5093 or A5108;
A5112 <= (not A5086) or (not A5087);
A5111 <= A5093 or A5108;
A5110 <= (not A5109) and (not A5093);
A5109 <= A5093 and A5108;
A5108 <= (not A5084) or (not A5085);
A5107 <= A5085 and A5097;
A5106 <= A5086 or A5093;
A5105 <= A5086 or A5087;
A5104 <= (not A5114) or (not A5113);
A5103 <= A5112 and A5105;
A5102 <= ((not A5086) and A5093) or (A5086 and (not A5093));
A5101 <= (not A5110) or (not A5111);
A5100 <= (A5085 and A5097) or ((not A5085) and (not A5097));
A5099 <= A5107 or A5084;
A5098 <= A5104 and A5085;
A5097 <= A5106 and A5105;
A5096 <= A5101 and A5085;
A5095 <= A5103 and A5102;
A5094 <= ((not A5095) and A5085) or (A5095 and (not A5085));
A5093 <= ((not A5083) and A5084) or (A5083 and (not A5084));
A5092 <= A5093 and A5100;
A5091 <= A5093 and A5099;
A5090 <= A5098 or A5097;
A5089 <= A5096 or A5095;
A5088 <= A5094 and A5093;
A5087 <= B206;
A5086 <= B173;
A5085 <= B140;
A5084 <= B107;
A5083 <= B74;
A5082 <= A5060 and A5075;
A5081 <= (not A5060) and (not A5082);
A5080 <= A5060 or A5075;
A5079 <= (not A5053) or (not A5054);
A5078 <= A5060 or A5075;
A5077 <= (not A5076) and (not A5060);
A5076 <= A5060 and A5075;
A5075 <= (not A5051) or (not A5052);
A5074 <= A5052 and A5064;
A5073 <= A5053 or A5060;
A5072 <= A5053 or A5054;
A5071 <= (not A5081) or (not A5080);
A5070 <= A5079 and A5072;
A5069 <= ((not A5053) and A5060) or (A5053 and (not A5060));
A5068 <= (not A5077) or (not A5078);
A5067 <= (A5052 and A5064) or ((not A5052) and (not A5064));
A5066 <= A5074 or A5051;
A5065 <= A5071 and A5052;
A5064 <= A5073 and A5072;
A5063 <= A5068 and A5052;
A5062 <= A5070 and A5069;
A5061 <= ((not A5062) and A5052) or (A5062 and (not A5052));
A5060 <= ((not A5050) and A5051) or (A5050 and (not A5051));
A5059 <= A5060 and A5067;
A5058 <= A5060 and A5066;
A5057 <= A5065 or A5064;
A5056 <= A5063 or A5062;
A5055 <= A5061 and A5060;
A5054 <= B41;
A5053 <= B8;
A5052 <= A9974;
A5051 <= A9941;
A5050 <= A9908;
A5049 <= A5027 and A5042;
A5048 <= (not A5027) and (not A5049);
A5047 <= A5027 or A5042;
A5046 <= (not A5020) or (not A5021);
A5045 <= A5027 or A5042;
A5044 <= (not A5043) and (not A5027);
A5043 <= A5027 and A5042;
A5042 <= (not A5018) or (not A5019);
A5041 <= A5019 and A5031;
A5040 <= A5020 or A5027;
A5039 <= A5020 or A5021;
A5038 <= (not A5048) or (not A5047);
A5037 <= A5046 and A5039;
A5036 <= ((not A5020) and A5027) or (A5020 and (not A5027));
A5035 <= (not A5044) or (not A5045);
A5034 <= (A5019 and A5031) or ((not A5019) and (not A5031));
A5033 <= A5041 or A5018;
A5032 <= A5038 and A5019;
A5031 <= A5040 and A5039;
A5030 <= A5035 and A5019;
A5029 <= A5037 and A5036;
A5028 <= ((not A5029) and A5019) or (A5029 and (not A5019));
A5027 <= ((not A5017) and A5018) or (A5017 and (not A5018));
A5026 <= A5027 and A5034;
A5025 <= A5027 and A5033;
A5024 <= A5032 or A5031;
A5023 <= A5030 or A5029;
A5022 <= A5028 and A5027;
A5021 <= A9875;
A5020 <= A9842;
A5019 <= A9809;
A5018 <= A9776;
A5017 <= A9743;
A5016 <= A4994 and A5009;
A5015 <= (not A4994) and (not A5016);
A5014 <= A4994 or A5009;
A5013 <= (not A4987) or (not A4988);
A5012 <= A4994 or A5009;
A5011 <= (not A5010) and (not A4994);
A5010 <= A4994 and A5009;
A5009 <= (not A4985) or (not A4986);
A5008 <= A4986 and A4998;
A5007 <= A4987 or A4994;
A5006 <= A4987 or A4988;
A5005 <= (not A5015) or (not A5014);
A5004 <= A5013 and A5006;
A5003 <= ((not A4987) and A4994) or (A4987 and (not A4994));
A5002 <= (not A5011) or (not A5012);
A5001 <= (A4986 and A4998) or ((not A4986) and (not A4998));
A5000 <= A5008 or A4985;
A4999 <= A5005 and A4986;
A4998 <= A5007 and A5006;
A4997 <= A5002 and A4986;
A4996 <= A5004 and A5003;
A4995 <= ((not A4996) and A4986) or (A4996 and (not A4986));
A4994 <= ((not A4984) and A4985) or (A4984 and (not A4985));
A4993 <= A4994 and A5001;
A4992 <= A4994 and A5000;
A4991 <= A4999 or A4998;
A4990 <= A4997 or A4996;
A4989 <= A4995 and A4994;
A4988 <= A9710;
A4987 <= A9677;
A4986 <= A9644;
A4985 <= A9611;
A4984 <= A9578;
A4983 <= A4961 and A4976;
A4982 <= (not A4961) and (not A4983);
A4981 <= A4961 or A4976;
A4980 <= (not A4954) or (not A4955);
A4979 <= A4961 or A4976;
A4978 <= (not A4977) and (not A4961);
A4977 <= A4961 and A4976;
A4976 <= (not A4952) or (not A4953);
A4975 <= A4953 and A4965;
A4974 <= A4954 or A4961;
A4973 <= A4954 or A4955;
A4972 <= (not A4982) or (not A4981);
A4971 <= A4980 and A4973;
A4970 <= ((not A4954) and A4961) or (A4954 and (not A4961));
A4969 <= (not A4978) or (not A4979);
A4968 <= (A4953 and A4965) or ((not A4953) and (not A4965));
A4967 <= A4975 or A4952;
A4966 <= A4972 and A4953;
A4965 <= A4974 and A4973;
A4964 <= A4969 and A4953;
A4963 <= A4971 and A4970;
A4962 <= ((not A4963) and A4953) or (A4963 and (not A4953));
A4961 <= ((not A4951) and A4952) or (A4951 and (not A4952));
A4960 <= A4961 and A4968;
A4959 <= A4961 and A4967;
A4958 <= A4966 or A4965;
A4957 <= A4964 or A4963;
A4956 <= A4962 and A4961;
A4955 <= A9545;
A4954 <= A9512;
A4953 <= A9479;
A4952 <= A9446;
A4951 <= A9413;
A4950 <= A4928 and A4943;
A4949 <= (not A4928) and (not A4950);
A4948 <= A4928 or A4943;
A4947 <= (not A4921) or (not A4922);
A4946 <= A4928 or A4943;
A4945 <= (not A4944) and (not A4928);
A4944 <= A4928 and A4943;
A4943 <= (not A4919) or (not A4920);
A4942 <= A4920 and A4932;
A4941 <= A4921 or A4928;
A4940 <= A4921 or A4922;
A4939 <= (not A4949) or (not A4948);
A4938 <= A4947 and A4940;
A4937 <= ((not A4921) and A4928) or (A4921 and (not A4928));
A4936 <= (not A4945) or (not A4946);
A4935 <= (A4920 and A4932) or ((not A4920) and (not A4932));
A4934 <= A4942 or A4919;
A4933 <= A4939 and A4920;
A4932 <= A4941 and A4940;
A4931 <= A4936 and A4920;
A4930 <= A4938 and A4937;
A4929 <= ((not A4930) and A4920) or (A4930 and (not A4920));
A4928 <= ((not A4918) and A4919) or (A4918 and (not A4919));
A4927 <= A4928 and A4935;
A4926 <= A4928 and A4934;
A4925 <= A4933 or A4932;
A4924 <= A4931 or A4930;
A4923 <= A4929 and A4928;
A4922 <= A9380;
A4921 <= A9347;
A4920 <= A9314;
A4919 <= A9281;
A4918 <= A9248;
A4917 <= A4895 and A4910;
A4916 <= (not A4895) and (not A4917);
A4915 <= A4895 or A4910;
A4914 <= (not A4888) or (not A4889);
A4913 <= A4895 or A4910;
A4912 <= (not A4911) and (not A4895);
A4911 <= A4895 and A4910;
A4910 <= (not A4886) or (not A4887);
A4909 <= A4887 and A4899;
A4908 <= A4888 or A4895;
A4907 <= A4888 or A4889;
A4906 <= (not A4916) or (not A4915);
A4905 <= A4914 and A4907;
A4904 <= ((not A4888) and A4895) or (A4888 and (not A4895));
A4903 <= (not A4912) or (not A4913);
A4902 <= (A4887 and A4899) or ((not A4887) and (not A4899));
A4901 <= A4909 or A4886;
A4900 <= A4906 and A4887;
A4899 <= A4908 and A4907;
A4898 <= A4903 and A4887;
A4897 <= A4905 and A4904;
A4896 <= ((not A4897) and A4887) or (A4897 and (not A4887));
A4895 <= ((not A4885) and A4886) or (A4885 and (not A4886));
A4894 <= A4895 and A4902;
A4893 <= A4895 and A4901;
A4892 <= A4900 or A4899;
A4891 <= A4898 or A4897;
A4890 <= A4896 and A4895;
A4889 <= A9215;
A4888 <= A9182;
A4887 <= A9149;
A4886 <= A9116;
A4885 <= A9083;
A4884 <= A4862 and A4877;
A4883 <= (not A4862) and (not A4884);
A4882 <= A4862 or A4877;
A4881 <= (not A4855) or (not A4856);
A4880 <= A4862 or A4877;
A4879 <= (not A4878) and (not A4862);
A4878 <= A4862 and A4877;
A4877 <= (not A4853) or (not A4854);
A4876 <= A4854 and A4866;
A4875 <= A4855 or A4862;
A4874 <= A4855 or A4856;
A4873 <= (not A4883) or (not A4882);
A4872 <= A4881 and A4874;
A4871 <= ((not A4855) and A4862) or (A4855 and (not A4862));
A4870 <= (not A4879) or (not A4880);
A4869 <= (A4854 and A4866) or ((not A4854) and (not A4866));
A4868 <= A4876 or A4853;
A4867 <= A4873 and A4854;
A4866 <= A4875 and A4874;
A4865 <= A4870 and A4854;
A4864 <= A4872 and A4871;
A4863 <= ((not A4864) and A4854) or (A4864 and (not A4854));
A4862 <= ((not A4852) and A4853) or (A4852 and (not A4853));
A4861 <= A4862 and A4869;
A4860 <= A4862 and A4868;
A4859 <= A4867 or A4866;
A4858 <= A4865 or A4864;
A4857 <= A4863 and A4862;
A4856 <= A9050;
A4855 <= A9017;
A4854 <= A8984;
A4853 <= A8951;
A4852 <= A8918;
A4851 <= A4829 and A4844;
A4850 <= (not A4829) and (not A4851);
A4849 <= A4829 or A4844;
A4848 <= (not A4822) or (not A4823);
A4847 <= A4829 or A4844;
A4846 <= (not A4845) and (not A4829);
A4845 <= A4829 and A4844;
A4844 <= (not A4820) or (not A4821);
A4843 <= A4821 and A4833;
A4842 <= A4822 or A4829;
A4841 <= A4822 or A4823;
A4840 <= (not A4850) or (not A4849);
A4839 <= A4848 and A4841;
A4838 <= ((not A4822) and A4829) or (A4822 and (not A4829));
A4837 <= (not A4846) or (not A4847);
A4836 <= (A4821 and A4833) or ((not A4821) and (not A4833));
A4835 <= A4843 or A4820;
A4834 <= A4840 and A4821;
A4833 <= A4842 and A4841;
A4832 <= A4837 and A4821;
A4831 <= A4839 and A4838;
A4830 <= ((not A4831) and A4821) or (A4831 and (not A4821));
A4829 <= ((not A4819) and A4820) or (A4819 and (not A4820));
A4828 <= A4829 and A4836;
A4827 <= A4829 and A4835;
A4826 <= A4834 or A4833;
A4825 <= A4832 or A4831;
A4824 <= A4830 and A4829;
A4823 <= A8885;
A4822 <= A8852;
A4821 <= A8819;
A4820 <= A8786;
A4819 <= A8753;
A4818 <= A4796 and A4811;
A4817 <= (not A4796) and (not A4818);
A4816 <= A4796 or A4811;
A4815 <= (not A4789) or (not A4790);
A4814 <= A4796 or A4811;
A4813 <= (not A4812) and (not A4796);
A4812 <= A4796 and A4811;
A4811 <= (not A4787) or (not A4788);
A4810 <= A4788 and A4800;
A4809 <= A4789 or A4796;
A4808 <= A4789 or A4790;
A4807 <= (not A4817) or (not A4816);
A4806 <= A4815 and A4808;
A4805 <= ((not A4789) and A4796) or (A4789 and (not A4796));
A4804 <= (not A4813) or (not A4814);
A4803 <= (A4788 and A4800) or ((not A4788) and (not A4800));
A4802 <= A4810 or A4787;
A4801 <= A4807 and A4788;
A4800 <= A4809 and A4808;
A4799 <= A4804 and A4788;
A4798 <= A4806 and A4805;
A4797 <= ((not A4798) and A4788) or (A4798 and (not A4788));
A4796 <= ((not A4786) and A4787) or (A4786 and (not A4787));
A4795 <= A4796 and A4803;
A4794 <= A4796 and A4802;
A4793 <= A4801 or A4800;
A4792 <= A4799 or A4798;
A4791 <= A4797 and A4796;
A4790 <= A8720;
A4789 <= A8687;
A4788 <= A8654;
A4787 <= A8621;
A4786 <= A8588;
A4785 <= A4763 and A4778;
A4784 <= (not A4763) and (not A4785);
A4783 <= A4763 or A4778;
A4782 <= (not A4756) or (not A4757);
A4781 <= A4763 or A4778;
A4780 <= (not A4779) and (not A4763);
A4779 <= A4763 and A4778;
A4778 <= (not A4754) or (not A4755);
A4777 <= A4755 and A4767;
A4776 <= A4756 or A4763;
A4775 <= A4756 or A4757;
A4774 <= (not A4784) or (not A4783);
A4773 <= A4782 and A4775;
A4772 <= ((not A4756) and A4763) or (A4756 and (not A4763));
A4771 <= (not A4780) or (not A4781);
A4770 <= (A4755 and A4767) or ((not A4755) and (not A4767));
A4769 <= A4777 or A4754;
A4768 <= A4774 and A4755;
A4767 <= A4776 and A4775;
A4766 <= A4771 and A4755;
A4765 <= A4773 and A4772;
A4764 <= ((not A4765) and A4755) or (A4765 and (not A4755));
A4763 <= ((not A4753) and A4754) or (A4753 and (not A4754));
A4762 <= A4763 and A4770;
A4761 <= A4763 and A4769;
A4760 <= A4768 or A4767;
A4759 <= A4766 or A4765;
A4758 <= A4764 and A4763;
A4757 <= A8555;
A4756 <= A8522;
A4755 <= A8489;
A4754 <= A8456;
A4753 <= A8423;
A4752 <= A4730 and A4745;
A4751 <= (not A4730) and (not A4752);
A4750 <= A4730 or A4745;
A4749 <= (not A4723) or (not A4724);
A4748 <= A4730 or A4745;
A4747 <= (not A4746) and (not A4730);
A4746 <= A4730 and A4745;
A4745 <= (not A4721) or (not A4722);
A4744 <= A4722 and A4734;
A4743 <= A4723 or A4730;
A4742 <= A4723 or A4724;
A4741 <= (not A4751) or (not A4750);
A4740 <= A4749 and A4742;
A4739 <= ((not A4723) and A4730) or (A4723 and (not A4730));
A4738 <= (not A4747) or (not A4748);
A4737 <= (A4722 and A4734) or ((not A4722) and (not A4734));
A4736 <= A4744 or A4721;
A4735 <= A4741 and A4722;
A4734 <= A4743 and A4742;
A4733 <= A4738 and A4722;
A4732 <= A4740 and A4739;
A4731 <= ((not A4732) and A4722) or (A4732 and (not A4722));
A4730 <= ((not A4720) and A4721) or (A4720 and (not A4721));
A4729 <= A4730 and A4737;
A4728 <= A4730 and A4736;
A4727 <= A4735 or A4734;
A4726 <= A4733 or A4732;
A4725 <= A4731 and A4730;
A4724 <= A8390;
A4723 <= A8357;
A4722 <= A8324;
A4721 <= A8291;
A4720 <= A8258;
A4719 <= A4697 and A4712;
A4718 <= (not A4697) and (not A4719);
A4717 <= A4697 or A4712;
A4716 <= (not A4690) or (not A4691);
A4715 <= A4697 or A4712;
A4714 <= (not A4713) and (not A4697);
A4713 <= A4697 and A4712;
A4712 <= (not A4688) or (not A4689);
A4711 <= A4689 and A4701;
A4710 <= A4690 or A4697;
A4709 <= A4690 or A4691;
A4708 <= (not A4718) or (not A4717);
A4707 <= A4716 and A4709;
A4706 <= ((not A4690) and A4697) or (A4690 and (not A4697));
A4705 <= (not A4714) or (not A4715);
A4704 <= (A4689 and A4701) or ((not A4689) and (not A4701));
A4703 <= A4711 or A4688;
A4702 <= A4708 and A4689;
A4701 <= A4710 and A4709;
A4700 <= A4705 and A4689;
A4699 <= A4707 and A4706;
A4698 <= ((not A4699) and A4689) or (A4699 and (not A4689));
A4697 <= ((not A4687) and A4688) or (A4687 and (not A4688));
A4696 <= A4697 and A4704;
A4695 <= A4697 and A4703;
A4694 <= A4702 or A4701;
A4693 <= A4700 or A4699;
A4692 <= A4698 and A4697;
A4691 <= A8225;
A4690 <= A8192;
A4689 <= A8159;
A4688 <= A8126;
A4687 <= A8093;
A4686 <= A4664 and A4679;
A4685 <= (not A4664) and (not A4686);
A4684 <= A4664 or A4679;
A4683 <= (not A4657) or (not A4658);
A4682 <= A4664 or A4679;
A4681 <= (not A4680) and (not A4664);
A4680 <= A4664 and A4679;
A4679 <= (not A4655) or (not A4656);
A4678 <= A4656 and A4668;
A4677 <= A4657 or A4664;
A4676 <= A4657 or A4658;
A4675 <= (not A4685) or (not A4684);
A4674 <= A4683 and A4676;
A4673 <= ((not A4657) and A4664) or (A4657 and (not A4664));
A4672 <= (not A4681) or (not A4682);
A4671 <= (A4656 and A4668) or ((not A4656) and (not A4668));
A4670 <= A4678 or A4655;
A4669 <= A4675 and A4656;
A4668 <= A4677 and A4676;
A4667 <= A4672 and A4656;
A4666 <= A4674 and A4673;
A4665 <= ((not A4666) and A4656) or (A4666 and (not A4656));
A4664 <= ((not A4654) and A4655) or (A4654 and (not A4655));
A4663 <= A4664 and A4671;
A4662 <= A4664 and A4670;
A4661 <= A4669 or A4668;
A4660 <= A4667 or A4666;
A4659 <= A4665 and A4664;
A4658 <= A8060;
A4657 <= A8027;
A4656 <= A7994;
A4655 <= A7961;
A4654 <= A7928;
A4653 <= A4631 and A4646;
A4652 <= (not A4631) and (not A4653);
A4651 <= A4631 or A4646;
A4650 <= (not A4624) or (not A4625);
A4649 <= A4631 or A4646;
A4648 <= (not A4647) and (not A4631);
A4647 <= A4631 and A4646;
A4646 <= (not A4622) or (not A4623);
A4645 <= A4623 and A4635;
A4644 <= A4624 or A4631;
A4643 <= A4624 or A4625;
A4642 <= (not A4652) or (not A4651);
A4641 <= A4650 and A4643;
A4640 <= ((not A4624) and A4631) or (A4624 and (not A4631));
A4639 <= (not A4648) or (not A4649);
A4638 <= (A4623 and A4635) or ((not A4623) and (not A4635));
A4637 <= A4645 or A4622;
A4636 <= A4642 and A4623;
A4635 <= A4644 and A4643;
A4634 <= A4639 and A4623;
A4633 <= A4641 and A4640;
A4632 <= ((not A4633) and A4623) or (A4633 and (not A4623));
A4631 <= ((not A4621) and A4622) or (A4621 and (not A4622));
A4630 <= A4631 and A4638;
A4629 <= A4631 and A4637;
A4628 <= A4636 or A4635;
A4627 <= A4634 or A4633;
A4626 <= A4632 and A4631;
A4625 <= A7895;
A4624 <= A7862;
A4623 <= A7829;
A4622 <= A7796;
A4621 <= A7763;
A4620 <= A4598 and A4613;
A4619 <= (not A4598) and (not A4620);
A4618 <= A4598 or A4613;
A4617 <= (not A4591) or (not A4592);
A4616 <= A4598 or A4613;
A4615 <= (not A4614) and (not A4598);
A4614 <= A4598 and A4613;
A4613 <= (not A4589) or (not A4590);
A4612 <= A4590 and A4602;
A4611 <= A4591 or A4598;
A4610 <= A4591 or A4592;
A4609 <= (not A4619) or (not A4618);
A4608 <= A4617 and A4610;
A4607 <= ((not A4591) and A4598) or (A4591 and (not A4598));
A4606 <= (not A4615) or (not A4616);
A4605 <= (A4590 and A4602) or ((not A4590) and (not A4602));
A4604 <= A4612 or A4589;
A4603 <= A4609 and A4590;
A4602 <= A4611 and A4610;
A4601 <= A4606 and A4590;
A4600 <= A4608 and A4607;
A4599 <= ((not A4600) and A4590) or (A4600 and (not A4590));
A4598 <= ((not A4588) and A4589) or (A4588 and (not A4589));
A4597 <= A4598 and A4605;
A4596 <= A4598 and A4604;
A4595 <= A4603 or A4602;
A4594 <= A4601 or A4600;
A4593 <= A4599 and A4598;
A4592 <= A7730;
A4591 <= A7697;
A4590 <= A7664;
A4589 <= A7631;
A4588 <= A7598;
A4587 <= A4565 and A4580;
A4586 <= (not A4565) and (not A4587);
A4585 <= A4565 or A4580;
A4584 <= (not A4558) or (not A4559);
A4583 <= A4565 or A4580;
A4582 <= (not A4581) and (not A4565);
A4581 <= A4565 and A4580;
A4580 <= (not A4556) or (not A4557);
A4579 <= A4557 and A4569;
A4578 <= A4558 or A4565;
A4577 <= A4558 or A4559;
A4576 <= (not A4586) or (not A4585);
A4575 <= A4584 and A4577;
A4574 <= ((not A4558) and A4565) or (A4558 and (not A4565));
A4573 <= (not A4582) or (not A4583);
A4572 <= (A4557 and A4569) or ((not A4557) and (not A4569));
A4571 <= A4579 or A4556;
A4570 <= A4576 and A4557;
A4569 <= A4578 and A4577;
A4568 <= A4573 and A4557;
A4567 <= A4575 and A4574;
A4566 <= ((not A4567) and A4557) or (A4567 and (not A4557));
A4565 <= ((not A4555) and A4556) or (A4555 and (not A4556));
A4564 <= A4565 and A4572;
A4563 <= A4565 and A4571;
A4562 <= A4570 or A4569;
A4561 <= A4568 or A4567;
A4560 <= A4566 and A4565;
A4559 <= A7565;
A4558 <= A7532;
A4557 <= A7499;
A4556 <= A7466;
A4555 <= A7433;
A4554 <= A4532 and A4547;
A4553 <= (not A4532) and (not A4554);
A4552 <= A4532 or A4547;
A4551 <= (not A4525) or (not A4526);
A4550 <= A4532 or A4547;
A4549 <= (not A4548) and (not A4532);
A4548 <= A4532 and A4547;
A4547 <= (not A4523) or (not A4524);
A4546 <= A4524 and A4536;
A4545 <= A4525 or A4532;
A4544 <= A4525 or A4526;
A4543 <= (not A4553) or (not A4552);
A4542 <= A4551 and A4544;
A4541 <= ((not A4525) and A4532) or (A4525 and (not A4532));
A4540 <= (not A4549) or (not A4550);
A4539 <= (A4524 and A4536) or ((not A4524) and (not A4536));
A4538 <= A4546 or A4523;
A4537 <= A4543 and A4524;
A4536 <= A4545 and A4544;
A4535 <= A4540 and A4524;
A4534 <= A4542 and A4541;
A4533 <= ((not A4534) and A4524) or (A4534 and (not A4524));
A4532 <= ((not A4522) and A4523) or (A4522 and (not A4523));
A4531 <= A4532 and A4539;
A4530 <= A4532 and A4538;
A4529 <= A4537 or A4536;
A4528 <= A4535 or A4534;
A4527 <= A4533 and A4532;
A4526 <= A7400;
A4525 <= A7367;
A4524 <= A7334;
A4523 <= A7301;
A4522 <= A7268;
A4521 <= A4499 and A4514;
A4520 <= (not A4499) and (not A4521);
A4519 <= A4499 or A4514;
A4518 <= (not A4492) or (not A4493);
A4517 <= A4499 or A4514;
A4516 <= (not A4515) and (not A4499);
A4515 <= A4499 and A4514;
A4514 <= (not A4490) or (not A4491);
A4513 <= A4491 and A4503;
A4512 <= A4492 or A4499;
A4511 <= A4492 or A4493;
A4510 <= (not A4520) or (not A4519);
A4509 <= A4518 and A4511;
A4508 <= ((not A4492) and A4499) or (A4492 and (not A4499));
A4507 <= (not A4516) or (not A4517);
A4506 <= (A4491 and A4503) or ((not A4491) and (not A4503));
A4505 <= A4513 or A4490;
A4504 <= A4510 and A4491;
A4503 <= A4512 and A4511;
A4502 <= A4507 and A4491;
A4501 <= A4509 and A4508;
A4500 <= ((not A4501) and A4491) or (A4501 and (not A4491));
A4499 <= ((not A4489) and A4490) or (A4489 and (not A4490));
A4498 <= A4499 and A4506;
A4497 <= A4499 and A4505;
A4496 <= A4504 or A4503;
A4495 <= A4502 or A4501;
A4494 <= A4500 and A4499;
A4493 <= A7235;
A4492 <= A7202;
A4491 <= A7169;
A4490 <= A7136;
A4489 <= A7103;
A4488 <= A4466 and A4481;
A4487 <= (not A4466) and (not A4488);
A4486 <= A4466 or A4481;
A4485 <= (not A4459) or (not A4460);
A4484 <= A4466 or A4481;
A4483 <= (not A4482) and (not A4466);
A4482 <= A4466 and A4481;
A4481 <= (not A4457) or (not A4458);
A4480 <= A4458 and A4470;
A4479 <= A4459 or A4466;
A4478 <= A4459 or A4460;
A4477 <= (not A4487) or (not A4486);
A4476 <= A4485 and A4478;
A4475 <= ((not A4459) and A4466) or (A4459 and (not A4466));
A4474 <= (not A4483) or (not A4484);
A4473 <= (A4458 and A4470) or ((not A4458) and (not A4470));
A4472 <= A4480 or A4457;
A4471 <= A4477 and A4458;
A4470 <= A4479 and A4478;
A4469 <= A4474 and A4458;
A4468 <= A4476 and A4475;
A4467 <= ((not A4468) and A4458) or (A4468 and (not A4458));
A4466 <= ((not A4456) and A4457) or (A4456 and (not A4457));
A4465 <= A4466 and A4473;
A4464 <= A4466 and A4472;
A4463 <= A4471 or A4470;
A4462 <= A4469 or A4468;
A4461 <= A4467 and A4466;
A4460 <= A7070;
A4459 <= A7037;
A4458 <= A7004;
A4457 <= A6971;
A4456 <= A6938;
A4455 <= A4433 and A4448;
A4454 <= (not A4433) and (not A4455);
A4453 <= A4433 or A4448;
A4452 <= (not A4426) or (not A4427);
A4451 <= A4433 or A4448;
A4450 <= (not A4449) and (not A4433);
A4449 <= A4433 and A4448;
A4448 <= (not A4424) or (not A4425);
A4447 <= A4425 and A4437;
A4446 <= A4426 or A4433;
A4445 <= A4426 or A4427;
A4444 <= (not A4454) or (not A4453);
A4443 <= A4452 and A4445;
A4442 <= ((not A4426) and A4433) or (A4426 and (not A4433));
A4441 <= (not A4450) or (not A4451);
A4440 <= (A4425 and A4437) or ((not A4425) and (not A4437));
A4439 <= A4447 or A4424;
A4438 <= A4444 and A4425;
A4437 <= A4446 and A4445;
A4436 <= A4441 and A4425;
A4435 <= A4443 and A4442;
A4434 <= ((not A4435) and A4425) or (A4435 and (not A4425));
A4433 <= ((not A4423) and A4424) or (A4423 and (not A4424));
A4432 <= A4433 and A4440;
A4431 <= A4433 and A4439;
A4430 <= A4438 or A4437;
A4429 <= A4436 or A4435;
A4428 <= A4434 and A4433;
A4427 <= B1030;
A4426 <= B997;
A4425 <= B964;
A4424 <= B931;
A4423 <= B898;
A4422 <= A4400 and A4415;
A4421 <= (not A4400) and (not A4422);
A4420 <= A4400 or A4415;
A4419 <= (not A4393) or (not A4394);
A4418 <= A4400 or A4415;
A4417 <= (not A4416) and (not A4400);
A4416 <= A4400 and A4415;
A4415 <= (not A4391) or (not A4392);
A4414 <= A4392 and A4404;
A4413 <= A4393 or A4400;
A4412 <= A4393 or A4394;
A4411 <= (not A4421) or (not A4420);
A4410 <= A4419 and A4412;
A4409 <= ((not A4393) and A4400) or (A4393 and (not A4400));
A4408 <= (not A4417) or (not A4418);
A4407 <= (A4392 and A4404) or ((not A4392) and (not A4404));
A4406 <= A4414 or A4391;
A4405 <= A4411 and A4392;
A4404 <= A4413 and A4412;
A4403 <= A4408 and A4392;
A4402 <= A4410 and A4409;
A4401 <= ((not A4402) and A4392) or (A4402 and (not A4392));
A4400 <= ((not A4390) and A4391) or (A4390 and (not A4391));
A4399 <= A4400 and A4407;
A4398 <= A4400 and A4406;
A4397 <= A4405 or A4404;
A4396 <= A4403 or A4402;
A4395 <= A4401 and A4400;
A4394 <= B865;
A4393 <= B832;
A4392 <= B799;
A4391 <= B766;
A4390 <= B733;
A4389 <= A4367 and A4382;
A4388 <= (not A4367) and (not A4389);
A4387 <= A4367 or A4382;
A4386 <= (not A4360) or (not A4361);
A4385 <= A4367 or A4382;
A4384 <= (not A4383) and (not A4367);
A4383 <= A4367 and A4382;
A4382 <= (not A4358) or (not A4359);
A4381 <= A4359 and A4371;
A4380 <= A4360 or A4367;
A4379 <= A4360 or A4361;
A4378 <= (not A4388) or (not A4387);
A4377 <= A4386 and A4379;
A4376 <= ((not A4360) and A4367) or (A4360 and (not A4367));
A4375 <= (not A4384) or (not A4385);
A4374 <= (A4359 and A4371) or ((not A4359) and (not A4371));
A4373 <= A4381 or A4358;
A4372 <= A4378 and A4359;
A4371 <= A4380 and A4379;
A4370 <= A4375 and A4359;
A4369 <= A4377 and A4376;
A4368 <= ((not A4369) and A4359) or (A4369 and (not A4359));
A4367 <= ((not A4357) and A4358) or (A4357 and (not A4358));
A4366 <= A4367 and A4374;
A4365 <= A4367 and A4373;
A4364 <= A4372 or A4371;
A4363 <= A4370 or A4369;
A4362 <= A4368 and A4367;
A4361 <= B700;
A4360 <= B667;
A4359 <= B634;
A4358 <= B601;
A4357 <= B568;
A4356 <= A4334 and A4349;
A4355 <= (not A4334) and (not A4356);
A4354 <= A4334 or A4349;
A4353 <= (not A4327) or (not A4328);
A4352 <= A4334 or A4349;
A4351 <= (not A4350) and (not A4334);
A4350 <= A4334 and A4349;
A4349 <= (not A4325) or (not A4326);
A4348 <= A4326 and A4338;
A4347 <= A4327 or A4334;
A4346 <= A4327 or A4328;
A4345 <= (not A4355) or (not A4354);
A4344 <= A4353 and A4346;
A4343 <= ((not A4327) and A4334) or (A4327 and (not A4334));
A4342 <= (not A4351) or (not A4352);
A4341 <= (A4326 and A4338) or ((not A4326) and (not A4338));
A4340 <= A4348 or A4325;
A4339 <= A4345 and A4326;
A4338 <= A4347 and A4346;
A4337 <= A4342 and A4326;
A4336 <= A4344 and A4343;
A4335 <= ((not A4336) and A4326) or (A4336 and (not A4326));
A4334 <= ((not A4324) and A4325) or (A4324 and (not A4325));
A4333 <= A4334 and A4341;
A4332 <= A4334 and A4340;
A4331 <= A4339 or A4338;
A4330 <= A4337 or A4336;
A4329 <= A4335 and A4334;
A4328 <= B535;
A4327 <= B502;
A4326 <= B469;
A4325 <= B436;
A4324 <= B403;
A4323 <= A4301 and A4316;
A4322 <= (not A4301) and (not A4323);
A4321 <= A4301 or A4316;
A4320 <= (not A4294) or (not A4295);
A4319 <= A4301 or A4316;
A4318 <= (not A4317) and (not A4301);
A4317 <= A4301 and A4316;
A4316 <= (not A4292) or (not A4293);
A4315 <= A4293 and A4305;
A4314 <= A4294 or A4301;
A4313 <= A4294 or A4295;
A4312 <= (not A4322) or (not A4321);
A4311 <= A4320 and A4313;
A4310 <= ((not A4294) and A4301) or (A4294 and (not A4301));
A4309 <= (not A4318) or (not A4319);
A4308 <= (A4293 and A4305) or ((not A4293) and (not A4305));
A4307 <= A4315 or A4292;
A4306 <= A4312 and A4293;
A4305 <= A4314 and A4313;
A4304 <= A4309 and A4293;
A4303 <= A4311 and A4310;
A4302 <= ((not A4303) and A4293) or (A4303 and (not A4293));
A4301 <= ((not A4291) and A4292) or (A4291 and (not A4292));
A4300 <= A4301 and A4308;
A4299 <= A4301 and A4307;
A4298 <= A4306 or A4305;
A4297 <= A4304 or A4303;
A4296 <= A4302 and A4301;
A4295 <= B370;
A4294 <= B337;
A4293 <= B304;
A4292 <= B271;
A4291 <= B238;
A4290 <= A4268 and A4283;
A4289 <= (not A4268) and (not A4290);
A4288 <= A4268 or A4283;
A4287 <= (not A4261) or (not A4262);
A4286 <= A4268 or A4283;
A4285 <= (not A4284) and (not A4268);
A4284 <= A4268 and A4283;
A4283 <= (not A4259) or (not A4260);
A4282 <= A4260 and A4272;
A4281 <= A4261 or A4268;
A4280 <= A4261 or A4262;
A4279 <= (not A4289) or (not A4288);
A4278 <= A4287 and A4280;
A4277 <= ((not A4261) and A4268) or (A4261 and (not A4268));
A4276 <= (not A4285) or (not A4286);
A4275 <= (A4260 and A4272) or ((not A4260) and (not A4272));
A4274 <= A4282 or A4259;
A4273 <= A4279 and A4260;
A4272 <= A4281 and A4280;
A4271 <= A4276 and A4260;
A4270 <= A4278 and A4277;
A4269 <= ((not A4270) and A4260) or (A4270 and (not A4260));
A4268 <= ((not A4258) and A4259) or (A4258 and (not A4259));
A4267 <= A4268 and A4275;
A4266 <= A4268 and A4274;
A4265 <= A4273 or A4272;
A4264 <= A4271 or A4270;
A4263 <= A4269 and A4268;
A4262 <= B205;
A4261 <= B172;
A4260 <= B139;
A4259 <= B106;
A4258 <= B73;
A4257 <= A4235 and A4250;
A4256 <= (not A4235) and (not A4257);
A4255 <= A4235 or A4250;
A4254 <= (not A4228) or (not A4229);
A4253 <= A4235 or A4250;
A4252 <= (not A4251) and (not A4235);
A4251 <= A4235 and A4250;
A4250 <= (not A4226) or (not A4227);
A4249 <= A4227 and A4239;
A4248 <= A4228 or A4235;
A4247 <= A4228 or A4229;
A4246 <= (not A4256) or (not A4255);
A4245 <= A4254 and A4247;
A4244 <= ((not A4228) and A4235) or (A4228 and (not A4235));
A4243 <= (not A4252) or (not A4253);
A4242 <= (A4227 and A4239) or ((not A4227) and (not A4239));
A4241 <= A4249 or A4226;
A4240 <= A4246 and A4227;
A4239 <= A4248 and A4247;
A4238 <= A4243 and A4227;
A4237 <= A4245 and A4244;
A4236 <= ((not A4237) and A4227) or (A4237 and (not A4227));
A4235 <= ((not A4225) and A4226) or (A4225 and (not A4226));
A4234 <= A4235 and A4242;
A4233 <= A4235 and A4241;
A4232 <= A4240 or A4239;
A4231 <= A4238 or A4237;
A4230 <= A4236 and A4235;
A4229 <= B40;
A4228 <= B7;
A4227 <= A9973;
A4226 <= A9940;
A4225 <= A9907;
A4224 <= A4202 and A4217;
A4223 <= (not A4202) and (not A4224);
A4222 <= A4202 or A4217;
A4221 <= (not A4195) or (not A4196);
A4220 <= A4202 or A4217;
A4219 <= (not A4218) and (not A4202);
A4218 <= A4202 and A4217;
A4217 <= (not A4193) or (not A4194);
A4216 <= A4194 and A4206;
A4215 <= A4195 or A4202;
A4214 <= A4195 or A4196;
A4213 <= (not A4223) or (not A4222);
A4212 <= A4221 and A4214;
A4211 <= ((not A4195) and A4202) or (A4195 and (not A4202));
A4210 <= (not A4219) or (not A4220);
A4209 <= (A4194 and A4206) or ((not A4194) and (not A4206));
A4208 <= A4216 or A4193;
A4207 <= A4213 and A4194;
A4206 <= A4215 and A4214;
A4205 <= A4210 and A4194;
A4204 <= A4212 and A4211;
A4203 <= ((not A4204) and A4194) or (A4204 and (not A4194));
A4202 <= ((not A4192) and A4193) or (A4192 and (not A4193));
A4201 <= A4202 and A4209;
A4200 <= A4202 and A4208;
A4199 <= A4207 or A4206;
A4198 <= A4205 or A4204;
A4197 <= A4203 and A4202;
A4196 <= A9874;
A4195 <= A9841;
A4194 <= A9808;
A4193 <= A9775;
A4192 <= A9742;
A4191 <= A4169 and A4184;
A4190 <= (not A4169) and (not A4191);
A4189 <= A4169 or A4184;
A4188 <= (not A4162) or (not A4163);
A4187 <= A4169 or A4184;
A4186 <= (not A4185) and (not A4169);
A4185 <= A4169 and A4184;
A4184 <= (not A4160) or (not A4161);
A4183 <= A4161 and A4173;
A4182 <= A4162 or A4169;
A4181 <= A4162 or A4163;
A4180 <= (not A4190) or (not A4189);
A4179 <= A4188 and A4181;
A4178 <= ((not A4162) and A4169) or (A4162 and (not A4169));
A4177 <= (not A4186) or (not A4187);
A4176 <= (A4161 and A4173) or ((not A4161) and (not A4173));
A4175 <= A4183 or A4160;
A4174 <= A4180 and A4161;
A4173 <= A4182 and A4181;
A4172 <= A4177 and A4161;
A4171 <= A4179 and A4178;
A4170 <= ((not A4171) and A4161) or (A4171 and (not A4161));
A4169 <= ((not A4159) and A4160) or (A4159 and (not A4160));
A4168 <= A4169 and A4176;
A4167 <= A4169 and A4175;
A4166 <= A4174 or A4173;
A4165 <= A4172 or A4171;
A4164 <= A4170 and A4169;
A4163 <= A9709;
A4162 <= A9676;
A4161 <= A9643;
A4160 <= A9610;
A4159 <= A9577;
A4158 <= A4136 and A4151;
A4157 <= (not A4136) and (not A4158);
A4156 <= A4136 or A4151;
A4155 <= (not A4129) or (not A4130);
A4154 <= A4136 or A4151;
A4153 <= (not A4152) and (not A4136);
A4152 <= A4136 and A4151;
A4151 <= (not A4127) or (not A4128);
A4150 <= A4128 and A4140;
A4149 <= A4129 or A4136;
A4148 <= A4129 or A4130;
A4147 <= (not A4157) or (not A4156);
A4146 <= A4155 and A4148;
A4145 <= ((not A4129) and A4136) or (A4129 and (not A4136));
A4144 <= (not A4153) or (not A4154);
A4143 <= (A4128 and A4140) or ((not A4128) and (not A4140));
A4142 <= A4150 or A4127;
A4141 <= A4147 and A4128;
A4140 <= A4149 and A4148;
A4139 <= A4144 and A4128;
A4138 <= A4146 and A4145;
A4137 <= ((not A4138) and A4128) or (A4138 and (not A4128));
A4136 <= ((not A4126) and A4127) or (A4126 and (not A4127));
A4135 <= A4136 and A4143;
A4134 <= A4136 and A4142;
A4133 <= A4141 or A4140;
A4132 <= A4139 or A4138;
A4131 <= A4137 and A4136;
A4130 <= A9544;
A4129 <= A9511;
A4128 <= A9478;
A4127 <= A9445;
A4126 <= A9412;
A4125 <= A4103 and A4118;
A4124 <= (not A4103) and (not A4125);
A4123 <= A4103 or A4118;
A4122 <= (not A4096) or (not A4097);
A4121 <= A4103 or A4118;
A4120 <= (not A4119) and (not A4103);
A4119 <= A4103 and A4118;
A4118 <= (not A4094) or (not A4095);
A4117 <= A4095 and A4107;
A4116 <= A4096 or A4103;
A4115 <= A4096 or A4097;
A4114 <= (not A4124) or (not A4123);
A4113 <= A4122 and A4115;
A4112 <= ((not A4096) and A4103) or (A4096 and (not A4103));
A4111 <= (not A4120) or (not A4121);
A4110 <= (A4095 and A4107) or ((not A4095) and (not A4107));
A4109 <= A4117 or A4094;
A4108 <= A4114 and A4095;
A4107 <= A4116 and A4115;
A4106 <= A4111 and A4095;
A4105 <= A4113 and A4112;
A4104 <= ((not A4105) and A4095) or (A4105 and (not A4095));
A4103 <= ((not A4093) and A4094) or (A4093 and (not A4094));
A4102 <= A4103 and A4110;
A4101 <= A4103 and A4109;
A4100 <= A4108 or A4107;
A4099 <= A4106 or A4105;
A4098 <= A4104 and A4103;
A4097 <= A9379;
A4096 <= A9346;
A4095 <= A9313;
A4094 <= A9280;
A4093 <= A9247;
A4092 <= A4070 and A4085;
A4091 <= (not A4070) and (not A4092);
A4090 <= A4070 or A4085;
A4089 <= (not A4063) or (not A4064);
A4088 <= A4070 or A4085;
A4087 <= (not A4086) and (not A4070);
A4086 <= A4070 and A4085;
A4085 <= (not A4061) or (not A4062);
A4084 <= A4062 and A4074;
A4083 <= A4063 or A4070;
A4082 <= A4063 or A4064;
A4081 <= (not A4091) or (not A4090);
A4080 <= A4089 and A4082;
A4079 <= ((not A4063) and A4070) or (A4063 and (not A4070));
A4078 <= (not A4087) or (not A4088);
A4077 <= (A4062 and A4074) or ((not A4062) and (not A4074));
A4076 <= A4084 or A4061;
A4075 <= A4081 and A4062;
A4074 <= A4083 and A4082;
A4073 <= A4078 and A4062;
A4072 <= A4080 and A4079;
A4071 <= ((not A4072) and A4062) or (A4072 and (not A4062));
A4070 <= ((not A4060) and A4061) or (A4060 and (not A4061));
A4069 <= A4070 and A4077;
A4068 <= A4070 and A4076;
A4067 <= A4075 or A4074;
A4066 <= A4073 or A4072;
A4065 <= A4071 and A4070;
A4064 <= A9214;
A4063 <= A9181;
A4062 <= A9148;
A4061 <= A9115;
A4060 <= A9082;
A4059 <= A4037 and A4052;
A4058 <= (not A4037) and (not A4059);
A4057 <= A4037 or A4052;
A4056 <= (not A4030) or (not A4031);
A4055 <= A4037 or A4052;
A4054 <= (not A4053) and (not A4037);
A4053 <= A4037 and A4052;
A4052 <= (not A4028) or (not A4029);
A4051 <= A4029 and A4041;
A4050 <= A4030 or A4037;
A4049 <= A4030 or A4031;
A4048 <= (not A4058) or (not A4057);
A4047 <= A4056 and A4049;
A4046 <= ((not A4030) and A4037) or (A4030 and (not A4037));
A4045 <= (not A4054) or (not A4055);
A4044 <= (A4029 and A4041) or ((not A4029) and (not A4041));
A4043 <= A4051 or A4028;
A4042 <= A4048 and A4029;
A4041 <= A4050 and A4049;
A4040 <= A4045 and A4029;
A4039 <= A4047 and A4046;
A4038 <= ((not A4039) and A4029) or (A4039 and (not A4029));
A4037 <= ((not A4027) and A4028) or (A4027 and (not A4028));
A4036 <= A4037 and A4044;
A4035 <= A4037 and A4043;
A4034 <= A4042 or A4041;
A4033 <= A4040 or A4039;
A4032 <= A4038 and A4037;
A4031 <= A9049;
A4030 <= A9016;
A4029 <= A8983;
A4028 <= A8950;
A4027 <= A8917;
A4026 <= A4004 and A4019;
A4025 <= (not A4004) and (not A4026);
A4024 <= A4004 or A4019;
A4023 <= (not A3997) or (not A3998);
A4022 <= A4004 or A4019;
A4021 <= (not A4020) and (not A4004);
A4020 <= A4004 and A4019;
A4019 <= (not A3995) or (not A3996);
A4018 <= A3996 and A4008;
A4017 <= A3997 or A4004;
A4016 <= A3997 or A3998;
A4015 <= (not A4025) or (not A4024);
A4014 <= A4023 and A4016;
A4013 <= ((not A3997) and A4004) or (A3997 and (not A4004));
A4012 <= (not A4021) or (not A4022);
A4011 <= (A3996 and A4008) or ((not A3996) and (not A4008));
A4010 <= A4018 or A3995;
A4009 <= A4015 and A3996;
A4008 <= A4017 and A4016;
A4007 <= A4012 and A3996;
A4006 <= A4014 and A4013;
A4005 <= ((not A4006) and A3996) or (A4006 and (not A3996));
A4004 <= ((not A3994) and A3995) or (A3994 and (not A3995));
A4003 <= A4004 and A4011;
A4002 <= A4004 and A4010;
A4001 <= A4009 or A4008;
A4000 <= A4007 or A4006;
A3999 <= A4005 and A4004;
A3998 <= A8884;
A3997 <= A8851;
A3996 <= A8818;
A3995 <= A8785;
A3994 <= A8752;
A3993 <= A3971 and A3986;
A3992 <= (not A3971) and (not A3993);
A3991 <= A3971 or A3986;
A3990 <= (not A3964) or (not A3965);
A3989 <= A3971 or A3986;
A3988 <= (not A3987) and (not A3971);
A3987 <= A3971 and A3986;
A3986 <= (not A3962) or (not A3963);
A3985 <= A3963 and A3975;
A3984 <= A3964 or A3971;
A3983 <= A3964 or A3965;
A3982 <= (not A3992) or (not A3991);
A3981 <= A3990 and A3983;
A3980 <= ((not A3964) and A3971) or (A3964 and (not A3971));
A3979 <= (not A3988) or (not A3989);
A3978 <= (A3963 and A3975) or ((not A3963) and (not A3975));
A3977 <= A3985 or A3962;
A3976 <= A3982 and A3963;
A3975 <= A3984 and A3983;
A3974 <= A3979 and A3963;
A3973 <= A3981 and A3980;
A3972 <= ((not A3973) and A3963) or (A3973 and (not A3963));
A3971 <= ((not A3961) and A3962) or (A3961 and (not A3962));
A3970 <= A3971 and A3978;
A3969 <= A3971 and A3977;
A3968 <= A3976 or A3975;
A3967 <= A3974 or A3973;
A3966 <= A3972 and A3971;
A3965 <= A8719;
A3964 <= A8686;
A3963 <= A8653;
A3962 <= A8620;
A3961 <= A8587;
A3960 <= A3938 and A3953;
A3959 <= (not A3938) and (not A3960);
A3958 <= A3938 or A3953;
A3957 <= (not A3931) or (not A3932);
A3956 <= A3938 or A3953;
A3955 <= (not A3954) and (not A3938);
A3954 <= A3938 and A3953;
A3953 <= (not A3929) or (not A3930);
A3952 <= A3930 and A3942;
A3951 <= A3931 or A3938;
A3950 <= A3931 or A3932;
A3949 <= (not A3959) or (not A3958);
A3948 <= A3957 and A3950;
A3947 <= ((not A3931) and A3938) or (A3931 and (not A3938));
A3946 <= (not A3955) or (not A3956);
A3945 <= (A3930 and A3942) or ((not A3930) and (not A3942));
A3944 <= A3952 or A3929;
A3943 <= A3949 and A3930;
A3942 <= A3951 and A3950;
A3941 <= A3946 and A3930;
A3940 <= A3948 and A3947;
A3939 <= ((not A3940) and A3930) or (A3940 and (not A3930));
A3938 <= ((not A3928) and A3929) or (A3928 and (not A3929));
A3937 <= A3938 and A3945;
A3936 <= A3938 and A3944;
A3935 <= A3943 or A3942;
A3934 <= A3941 or A3940;
A3933 <= A3939 and A3938;
A3932 <= A8554;
A3931 <= A8521;
A3930 <= A8488;
A3929 <= A8455;
A3928 <= A8422;
A3927 <= A3905 and A3920;
A3926 <= (not A3905) and (not A3927);
A3925 <= A3905 or A3920;
A3924 <= (not A3898) or (not A3899);
A3923 <= A3905 or A3920;
A3922 <= (not A3921) and (not A3905);
A3921 <= A3905 and A3920;
A3920 <= (not A3896) or (not A3897);
A3919 <= A3897 and A3909;
A3918 <= A3898 or A3905;
A3917 <= A3898 or A3899;
A3916 <= (not A3926) or (not A3925);
A3915 <= A3924 and A3917;
A3914 <= ((not A3898) and A3905) or (A3898 and (not A3905));
A3913 <= (not A3922) or (not A3923);
A3912 <= (A3897 and A3909) or ((not A3897) and (not A3909));
A3911 <= A3919 or A3896;
A3910 <= A3916 and A3897;
A3909 <= A3918 and A3917;
A3908 <= A3913 and A3897;
A3907 <= A3915 and A3914;
A3906 <= ((not A3907) and A3897) or (A3907 and (not A3897));
A3905 <= ((not A3895) and A3896) or (A3895 and (not A3896));
A3904 <= A3905 and A3912;
A3903 <= A3905 and A3911;
A3902 <= A3910 or A3909;
A3901 <= A3908 or A3907;
A3900 <= A3906 and A3905;
A3899 <= A8389;
A3898 <= A8356;
A3897 <= A8323;
A3896 <= A8290;
A3895 <= A8257;
A3894 <= A3872 and A3887;
A3893 <= (not A3872) and (not A3894);
A3892 <= A3872 or A3887;
A3891 <= (not A3865) or (not A3866);
A3890 <= A3872 or A3887;
A3889 <= (not A3888) and (not A3872);
A3888 <= A3872 and A3887;
A3887 <= (not A3863) or (not A3864);
A3886 <= A3864 and A3876;
A3885 <= A3865 or A3872;
A3884 <= A3865 or A3866;
A3883 <= (not A3893) or (not A3892);
A3882 <= A3891 and A3884;
A3881 <= ((not A3865) and A3872) or (A3865 and (not A3872));
A3880 <= (not A3889) or (not A3890);
A3879 <= (A3864 and A3876) or ((not A3864) and (not A3876));
A3878 <= A3886 or A3863;
A3877 <= A3883 and A3864;
A3876 <= A3885 and A3884;
A3875 <= A3880 and A3864;
A3874 <= A3882 and A3881;
A3873 <= ((not A3874) and A3864) or (A3874 and (not A3864));
A3872 <= ((not A3862) and A3863) or (A3862 and (not A3863));
A3871 <= A3872 and A3879;
A3870 <= A3872 and A3878;
A3869 <= A3877 or A3876;
A3868 <= A3875 or A3874;
A3867 <= A3873 and A3872;
A3866 <= A8224;
A3865 <= A8191;
A3864 <= A8158;
A3863 <= A8125;
A3862 <= A8092;
A3861 <= A3839 and A3854;
A3860 <= (not A3839) and (not A3861);
A3859 <= A3839 or A3854;
A3858 <= (not A3832) or (not A3833);
A3857 <= A3839 or A3854;
A3856 <= (not A3855) and (not A3839);
A3855 <= A3839 and A3854;
A3854 <= (not A3830) or (not A3831);
A3853 <= A3831 and A3843;
A3852 <= A3832 or A3839;
A3851 <= A3832 or A3833;
A3850 <= (not A3860) or (not A3859);
A3849 <= A3858 and A3851;
A3848 <= ((not A3832) and A3839) or (A3832 and (not A3839));
A3847 <= (not A3856) or (not A3857);
A3846 <= (A3831 and A3843) or ((not A3831) and (not A3843));
A3845 <= A3853 or A3830;
A3844 <= A3850 and A3831;
A3843 <= A3852 and A3851;
A3842 <= A3847 and A3831;
A3841 <= A3849 and A3848;
A3840 <= ((not A3841) and A3831) or (A3841 and (not A3831));
A3839 <= ((not A3829) and A3830) or (A3829 and (not A3830));
A3838 <= A3839 and A3846;
A3837 <= A3839 and A3845;
A3836 <= A3844 or A3843;
A3835 <= A3842 or A3841;
A3834 <= A3840 and A3839;
A3833 <= A8059;
A3832 <= A8026;
A3831 <= A7993;
A3830 <= A7960;
A3829 <= A7927;
A3828 <= A3806 and A3821;
A3827 <= (not A3806) and (not A3828);
A3826 <= A3806 or A3821;
A3825 <= (not A3799) or (not A3800);
A3824 <= A3806 or A3821;
A3823 <= (not A3822) and (not A3806);
A3822 <= A3806 and A3821;
A3821 <= (not A3797) or (not A3798);
A3820 <= A3798 and A3810;
A3819 <= A3799 or A3806;
A3818 <= A3799 or A3800;
A3817 <= (not A3827) or (not A3826);
A3816 <= A3825 and A3818;
A3815 <= ((not A3799) and A3806) or (A3799 and (not A3806));
A3814 <= (not A3823) or (not A3824);
A3813 <= (A3798 and A3810) or ((not A3798) and (not A3810));
A3812 <= A3820 or A3797;
A3811 <= A3817 and A3798;
A3810 <= A3819 and A3818;
A3809 <= A3814 and A3798;
A3808 <= A3816 and A3815;
A3807 <= ((not A3808) and A3798) or (A3808 and (not A3798));
A3806 <= ((not A3796) and A3797) or (A3796 and (not A3797));
A3805 <= A3806 and A3813;
A3804 <= A3806 and A3812;
A3803 <= A3811 or A3810;
A3802 <= A3809 or A3808;
A3801 <= A3807 and A3806;
A3800 <= A7894;
A3799 <= A7861;
A3798 <= A7828;
A3797 <= A7795;
A3796 <= A7762;
A3795 <= A3773 and A3788;
A3794 <= (not A3773) and (not A3795);
A3793 <= A3773 or A3788;
A3792 <= (not A3766) or (not A3767);
A3791 <= A3773 or A3788;
A3790 <= (not A3789) and (not A3773);
A3789 <= A3773 and A3788;
A3788 <= (not A3764) or (not A3765);
A3787 <= A3765 and A3777;
A3786 <= A3766 or A3773;
A3785 <= A3766 or A3767;
A3784 <= (not A3794) or (not A3793);
A3783 <= A3792 and A3785;
A3782 <= ((not A3766) and A3773) or (A3766 and (not A3773));
A3781 <= (not A3790) or (not A3791);
A3780 <= (A3765 and A3777) or ((not A3765) and (not A3777));
A3779 <= A3787 or A3764;
A3778 <= A3784 and A3765;
A3777 <= A3786 and A3785;
A3776 <= A3781 and A3765;
A3775 <= A3783 and A3782;
A3774 <= ((not A3775) and A3765) or (A3775 and (not A3765));
A3773 <= ((not A3763) and A3764) or (A3763 and (not A3764));
A3772 <= A3773 and A3780;
A3771 <= A3773 and A3779;
A3770 <= A3778 or A3777;
A3769 <= A3776 or A3775;
A3768 <= A3774 and A3773;
A3767 <= A7729;
A3766 <= A7696;
A3765 <= A7663;
A3764 <= A7630;
A3763 <= A7597;
A3762 <= A3740 and A3755;
A3761 <= (not A3740) and (not A3762);
A3760 <= A3740 or A3755;
A3759 <= (not A3733) or (not A3734);
A3758 <= A3740 or A3755;
A3757 <= (not A3756) and (not A3740);
A3756 <= A3740 and A3755;
A3755 <= (not A3731) or (not A3732);
A3754 <= A3732 and A3744;
A3753 <= A3733 or A3740;
A3752 <= A3733 or A3734;
A3751 <= (not A3761) or (not A3760);
A3750 <= A3759 and A3752;
A3749 <= ((not A3733) and A3740) or (A3733 and (not A3740));
A3748 <= (not A3757) or (not A3758);
A3747 <= (A3732 and A3744) or ((not A3732) and (not A3744));
A3746 <= A3754 or A3731;
A3745 <= A3751 and A3732;
A3744 <= A3753 and A3752;
A3743 <= A3748 and A3732;
A3742 <= A3750 and A3749;
A3741 <= ((not A3742) and A3732) or (A3742 and (not A3732));
A3740 <= ((not A3730) and A3731) or (A3730 and (not A3731));
A3739 <= A3740 and A3747;
A3738 <= A3740 and A3746;
A3737 <= A3745 or A3744;
A3736 <= A3743 or A3742;
A3735 <= A3741 and A3740;
A3734 <= A7564;
A3733 <= A7531;
A3732 <= A7498;
A3731 <= A7465;
A3730 <= A7432;
A3729 <= A3707 and A3722;
A3728 <= (not A3707) and (not A3729);
A3727 <= A3707 or A3722;
A3726 <= (not A3700) or (not A3701);
A3725 <= A3707 or A3722;
A3724 <= (not A3723) and (not A3707);
A3723 <= A3707 and A3722;
A3722 <= (not A3698) or (not A3699);
A3721 <= A3699 and A3711;
A3720 <= A3700 or A3707;
A3719 <= A3700 or A3701;
A3718 <= (not A3728) or (not A3727);
A3717 <= A3726 and A3719;
A3716 <= ((not A3700) and A3707) or (A3700 and (not A3707));
A3715 <= (not A3724) or (not A3725);
A3714 <= (A3699 and A3711) or ((not A3699) and (not A3711));
A3713 <= A3721 or A3698;
A3712 <= A3718 and A3699;
A3711 <= A3720 and A3719;
A3710 <= A3715 and A3699;
A3709 <= A3717 and A3716;
A3708 <= ((not A3709) and A3699) or (A3709 and (not A3699));
A3707 <= ((not A3697) and A3698) or (A3697 and (not A3698));
A3706 <= A3707 and A3714;
A3705 <= A3707 and A3713;
A3704 <= A3712 or A3711;
A3703 <= A3710 or A3709;
A3702 <= A3708 and A3707;
A3701 <= A7399;
A3700 <= A7366;
A3699 <= A7333;
A3698 <= A7300;
A3697 <= A7267;
A3696 <= A3674 and A3689;
A3695 <= (not A3674) and (not A3696);
A3694 <= A3674 or A3689;
A3693 <= (not A3667) or (not A3668);
A3692 <= A3674 or A3689;
A3691 <= (not A3690) and (not A3674);
A3690 <= A3674 and A3689;
A3689 <= (not A3665) or (not A3666);
A3688 <= A3666 and A3678;
A3687 <= A3667 or A3674;
A3686 <= A3667 or A3668;
A3685 <= (not A3695) or (not A3694);
A3684 <= A3693 and A3686;
A3683 <= ((not A3667) and A3674) or (A3667 and (not A3674));
A3682 <= (not A3691) or (not A3692);
A3681 <= (A3666 and A3678) or ((not A3666) and (not A3678));
A3680 <= A3688 or A3665;
A3679 <= A3685 and A3666;
A3678 <= A3687 and A3686;
A3677 <= A3682 and A3666;
A3676 <= A3684 and A3683;
A3675 <= ((not A3676) and A3666) or (A3676 and (not A3666));
A3674 <= ((not A3664) and A3665) or (A3664 and (not A3665));
A3673 <= A3674 and A3681;
A3672 <= A3674 and A3680;
A3671 <= A3679 or A3678;
A3670 <= A3677 or A3676;
A3669 <= A3675 and A3674;
A3668 <= A7234;
A3667 <= A7201;
A3666 <= A7168;
A3665 <= A7135;
A3664 <= A7102;
A3663 <= A3641 and A3656;
A3662 <= (not A3641) and (not A3663);
A3661 <= A3641 or A3656;
A3660 <= (not A3634) or (not A3635);
A3659 <= A3641 or A3656;
A3658 <= (not A3657) and (not A3641);
A3657 <= A3641 and A3656;
A3656 <= (not A3632) or (not A3633);
A3655 <= A3633 and A3645;
A3654 <= A3634 or A3641;
A3653 <= A3634 or A3635;
A3652 <= (not A3662) or (not A3661);
A3651 <= A3660 and A3653;
A3650 <= ((not A3634) and A3641) or (A3634 and (not A3641));
A3649 <= (not A3658) or (not A3659);
A3648 <= (A3633 and A3645) or ((not A3633) and (not A3645));
A3647 <= A3655 or A3632;
A3646 <= A3652 and A3633;
A3645 <= A3654 and A3653;
A3644 <= A3649 and A3633;
A3643 <= A3651 and A3650;
A3642 <= ((not A3643) and A3633) or (A3643 and (not A3633));
A3641 <= ((not A3631) and A3632) or (A3631 and (not A3632));
A3640 <= A3641 and A3648;
A3639 <= A3641 and A3647;
A3638 <= A3646 or A3645;
A3637 <= A3644 or A3643;
A3636 <= A3642 and A3641;
A3635 <= A7069;
A3634 <= A7036;
A3633 <= A7003;
A3632 <= A6970;
A3631 <= A6939;
A3630 <= A3608 and A3623;
A3629 <= (not A3608) and (not A3630);
A3628 <= A3608 or A3623;
A3627 <= (not A3601) or (not A3602);
A3626 <= A3608 or A3623;
A3625 <= (not A3624) and (not A3608);
A3624 <= A3608 and A3623;
A3623 <= (not A3599) or (not A3600);
A3622 <= A3600 and A3612;
A3621 <= A3601 or A3608;
A3620 <= A3601 or A3602;
A3619 <= (not A3629) or (not A3628);
A3618 <= A3627 and A3620;
A3617 <= ((not A3601) and A3608) or (A3601 and (not A3608));
A3616 <= (not A3625) or (not A3626);
A3615 <= (A3600 and A3612) or ((not A3600) and (not A3612));
A3614 <= A3622 or A3599;
A3613 <= A3619 and A3600;
A3612 <= A3621 and A3620;
A3611 <= A3616 and A3600;
A3610 <= A3618 and A3617;
A3609 <= ((not A3610) and A3600) or (A3610 and (not A3600));
A3608 <= ((not A3598) and A3599) or (A3598 and (not A3599));
A3607 <= A3608 and A3615;
A3606 <= A3608 and A3614;
A3605 <= A3613 or A3612;
A3604 <= A3611 or A3610;
A3603 <= A3609 and A3608;
A3602 <= B1029;
A3601 <= B996;
A3600 <= B963;
A3599 <= B930;
A3598 <= B897;
A3597 <= A3575 and A3590;
A3596 <= (not A3575) and (not A3597);
A3595 <= A3575 or A3590;
A3594 <= (not A3568) or (not A3569);
A3593 <= A3575 or A3590;
A3592 <= (not A3591) and (not A3575);
A3591 <= A3575 and A3590;
A3590 <= (not A3566) or (not A3567);
A3589 <= A3567 and A3579;
A3588 <= A3568 or A3575;
A3587 <= A3568 or A3569;
A3586 <= (not A3596) or (not A3595);
A3585 <= A3594 and A3587;
A3584 <= ((not A3568) and A3575) or (A3568 and (not A3575));
A3583 <= (not A3592) or (not A3593);
A3582 <= (A3567 and A3579) or ((not A3567) and (not A3579));
A3581 <= A3589 or A3566;
A3580 <= A3586 and A3567;
A3579 <= A3588 and A3587;
A3578 <= A3583 and A3567;
A3577 <= A3585 and A3584;
A3576 <= ((not A3577) and A3567) or (A3577 and (not A3567));
A3575 <= ((not A3565) and A3566) or (A3565 and (not A3566));
A3574 <= A3575 and A3582;
A3573 <= A3575 and A3581;
A3572 <= A3580 or A3579;
A3571 <= A3578 or A3577;
A3570 <= A3576 and A3575;
A3569 <= B864;
A3568 <= B831;
A3567 <= B798;
A3566 <= B765;
A3565 <= B732;
A3564 <= A3542 and A3557;
A3563 <= (not A3542) and (not A3564);
A3562 <= A3542 or A3557;
A3561 <= (not A3535) or (not A3536);
A3560 <= A3542 or A3557;
A3559 <= (not A3558) and (not A3542);
A3558 <= A3542 and A3557;
A3557 <= (not A3533) or (not A3534);
A3556 <= A3534 and A3546;
A3555 <= A3535 or A3542;
A3554 <= A3535 or A3536;
A3553 <= (not A3563) or (not A3562);
A3552 <= A3561 and A3554;
A3551 <= ((not A3535) and A3542) or (A3535 and (not A3542));
A3550 <= (not A3559) or (not A3560);
A3549 <= (A3534 and A3546) or ((not A3534) and (not A3546));
A3548 <= A3556 or A3533;
A3547 <= A3553 and A3534;
A3546 <= A3555 and A3554;
A3545 <= A3550 and A3534;
A3544 <= A3552 and A3551;
A3543 <= ((not A3544) and A3534) or (A3544 and (not A3534));
A3542 <= ((not A3532) and A3533) or (A3532 and (not A3533));
A3541 <= A3542 and A3549;
A3540 <= A3542 and A3548;
A3539 <= A3547 or A3546;
A3538 <= A3545 or A3544;
A3537 <= A3543 and A3542;
A3536 <= B699;
A3535 <= B666;
A3534 <= B633;
A3533 <= B600;
A3532 <= B567;
A3531 <= A3509 and A3524;
A3530 <= (not A3509) and (not A3531);
A3529 <= A3509 or A3524;
A3528 <= (not A3502) or (not A3503);
A3527 <= A3509 or A3524;
A3526 <= (not A3525) and (not A3509);
A3525 <= A3509 and A3524;
A3524 <= (not A3500) or (not A3501);
A3523 <= A3501 and A3513;
A3522 <= A3502 or A3509;
A3521 <= A3502 or A3503;
A3520 <= (not A3530) or (not A3529);
A3519 <= A3528 and A3521;
A3518 <= ((not A3502) and A3509) or (A3502 and (not A3509));
A3517 <= (not A3526) or (not A3527);
A3516 <= (A3501 and A3513) or ((not A3501) and (not A3513));
A3515 <= A3523 or A3500;
A3514 <= A3520 and A3501;
A3513 <= A3522 and A3521;
A3512 <= A3517 and A3501;
A3511 <= A3519 and A3518;
A3510 <= ((not A3511) and A3501) or (A3511 and (not A3501));
A3509 <= ((not A3499) and A3500) or (A3499 and (not A3500));
A3508 <= A3509 and A3516;
A3507 <= A3509 and A3515;
A3506 <= A3514 or A3513;
A3505 <= A3512 or A3511;
A3504 <= A3510 and A3509;
A3503 <= B534;
A3502 <= B501;
A3501 <= B468;
A3500 <= B435;
A3499 <= B402;
A3498 <= A3476 and A3491;
A3497 <= (not A3476) and (not A3498);
A3496 <= A3476 or A3491;
A3495 <= (not A3469) or (not A3470);
A3494 <= A3476 or A3491;
A3493 <= (not A3492) and (not A3476);
A3492 <= A3476 and A3491;
A3491 <= (not A3467) or (not A3468);
A3490 <= A3468 and A3480;
A3489 <= A3469 or A3476;
A3488 <= A3469 or A3470;
A3487 <= (not A3497) or (not A3496);
A3486 <= A3495 and A3488;
A3485 <= ((not A3469) and A3476) or (A3469 and (not A3476));
A3484 <= (not A3493) or (not A3494);
A3483 <= (A3468 and A3480) or ((not A3468) and (not A3480));
A3482 <= A3490 or A3467;
A3481 <= A3487 and A3468;
A3480 <= A3489 and A3488;
A3479 <= A3484 and A3468;
A3478 <= A3486 and A3485;
A3477 <= ((not A3478) and A3468) or (A3478 and (not A3468));
A3476 <= ((not A3466) and A3467) or (A3466 and (not A3467));
A3475 <= A3476 and A3483;
A3474 <= A3476 and A3482;
A3473 <= A3481 or A3480;
A3472 <= A3479 or A3478;
A3471 <= A3477 and A3476;
A3470 <= B369;
A3469 <= B336;
A3468 <= B303;
A3467 <= B270;
A3466 <= B237;
A3465 <= A3443 and A3458;
A3464 <= (not A3443) and (not A3465);
A3463 <= A3443 or A3458;
A3462 <= (not A3436) or (not A3437);
A3461 <= A3443 or A3458;
A3460 <= (not A3459) and (not A3443);
A3459 <= A3443 and A3458;
A3458 <= (not A3434) or (not A3435);
A3457 <= A3435 and A3447;
A3456 <= A3436 or A3443;
A3455 <= A3436 or A3437;
A3454 <= (not A3464) or (not A3463);
A3453 <= A3462 and A3455;
A3452 <= ((not A3436) and A3443) or (A3436 and (not A3443));
A3451 <= (not A3460) or (not A3461);
A3450 <= (A3435 and A3447) or ((not A3435) and (not A3447));
A3449 <= A3457 or A3434;
A3448 <= A3454 and A3435;
A3447 <= A3456 and A3455;
A3446 <= A3451 and A3435;
A3445 <= A3453 and A3452;
A3444 <= ((not A3445) and A3435) or (A3445 and (not A3435));
A3443 <= ((not A3433) and A3434) or (A3433 and (not A3434));
A3442 <= A3443 and A3450;
A3441 <= A3443 and A3449;
A3440 <= A3448 or A3447;
A3439 <= A3446 or A3445;
A3438 <= A3444 and A3443;
A3437 <= B204;
A3436 <= B171;
A3435 <= B138;
A3434 <= B105;
A3433 <= B72;
A3432 <= A3410 and A3425;
A3431 <= (not A3410) and (not A3432);
A3430 <= A3410 or A3425;
A3429 <= (not A3403) or (not A3404);
A3428 <= A3410 or A3425;
A3427 <= (not A3426) and (not A3410);
A3426 <= A3410 and A3425;
A3425 <= (not A3401) or (not A3402);
A3424 <= A3402 and A3414;
A3423 <= A3403 or A3410;
A3422 <= A3403 or A3404;
A3421 <= (not A3431) or (not A3430);
A3420 <= A3429 and A3422;
A3419 <= ((not A3403) and A3410) or (A3403 and (not A3410));
A3418 <= (not A3427) or (not A3428);
A3417 <= (A3402 and A3414) or ((not A3402) and (not A3414));
A3416 <= A3424 or A3401;
A3415 <= A3421 and A3402;
A3414 <= A3423 and A3422;
A3413 <= A3418 and A3402;
A3412 <= A3420 and A3419;
A3411 <= ((not A3412) and A3402) or (A3412 and (not A3402));
A3410 <= ((not A3400) and A3401) or (A3400 and (not A3401));
A3409 <= A3410 and A3417;
A3408 <= A3410 and A3416;
A3407 <= A3415 or A3414;
A3406 <= A3413 or A3412;
A3405 <= A3411 and A3410;
A3404 <= B39;
A3403 <= B6;
A3402 <= A9972;
A3401 <= A9939;
A3400 <= A9906;
A3399 <= A3377 and A3392;
A3398 <= (not A3377) and (not A3399);
A3397 <= A3377 or A3392;
A3396 <= (not A3370) or (not A3371);
A3395 <= A3377 or A3392;
A3394 <= (not A3393) and (not A3377);
A3393 <= A3377 and A3392;
A3392 <= (not A3368) or (not A3369);
A3391 <= A3369 and A3381;
A3390 <= A3370 or A3377;
A3389 <= A3370 or A3371;
A3388 <= (not A3398) or (not A3397);
A3387 <= A3396 and A3389;
A3386 <= ((not A3370) and A3377) or (A3370 and (not A3377));
A3385 <= (not A3394) or (not A3395);
A3384 <= (A3369 and A3381) or ((not A3369) and (not A3381));
A3383 <= A3391 or A3368;
A3382 <= A3388 and A3369;
A3381 <= A3390 and A3389;
A3380 <= A3385 and A3369;
A3379 <= A3387 and A3386;
A3378 <= ((not A3379) and A3369) or (A3379 and (not A3369));
A3377 <= ((not A3367) and A3368) or (A3367 and (not A3368));
A3376 <= A3377 and A3384;
A3375 <= A3377 and A3383;
A3374 <= A3382 or A3381;
A3373 <= A3380 or A3379;
A3372 <= A3378 and A3377;
A3371 <= A9873;
A3370 <= A9840;
A3369 <= A9807;
A3368 <= A9774;
A3367 <= A9741;
A3366 <= A3344 and A3359;
A3365 <= (not A3344) and (not A3366);
A3364 <= A3344 or A3359;
A3363 <= (not A3337) or (not A3338);
A3362 <= A3344 or A3359;
A3361 <= (not A3360) and (not A3344);
A3360 <= A3344 and A3359;
A3359 <= (not A3335) or (not A3336);
A3358 <= A3336 and A3348;
A3357 <= A3337 or A3344;
A3356 <= A3337 or A3338;
A3355 <= (not A3365) or (not A3364);
A3354 <= A3363 and A3356;
A3353 <= ((not A3337) and A3344) or (A3337 and (not A3344));
A3352 <= (not A3361) or (not A3362);
A3351 <= (A3336 and A3348) or ((not A3336) and (not A3348));
A3350 <= A3358 or A3335;
A3349 <= A3355 and A3336;
A3348 <= A3357 and A3356;
A3347 <= A3352 and A3336;
A3346 <= A3354 and A3353;
A3345 <= ((not A3346) and A3336) or (A3346 and (not A3336));
A3344 <= ((not A3334) and A3335) or (A3334 and (not A3335));
A3343 <= A3344 and A3351;
A3342 <= A3344 and A3350;
A3341 <= A3349 or A3348;
A3340 <= A3347 or A3346;
A3339 <= A3345 and A3344;
A3338 <= A9708;
A3337 <= A9675;
A3336 <= A9642;
A3335 <= A9609;
A3334 <= A9576;
A3333 <= A3311 and A3326;
A3332 <= (not A3311) and (not A3333);
A3331 <= A3311 or A3326;
A3330 <= (not A3304) or (not A3305);
A3329 <= A3311 or A3326;
A3328 <= (not A3327) and (not A3311);
A3327 <= A3311 and A3326;
A3326 <= (not A3302) or (not A3303);
A3325 <= A3303 and A3315;
A3324 <= A3304 or A3311;
A3323 <= A3304 or A3305;
A3322 <= (not A3332) or (not A3331);
A3321 <= A3330 and A3323;
A3320 <= ((not A3304) and A3311) or (A3304 and (not A3311));
A3319 <= (not A3328) or (not A3329);
A3318 <= (A3303 and A3315) or ((not A3303) and (not A3315));
A3317 <= A3325 or A3302;
A3316 <= A3322 and A3303;
A3315 <= A3324 and A3323;
A3314 <= A3319 and A3303;
A3313 <= A3321 and A3320;
A3312 <= ((not A3313) and A3303) or (A3313 and (not A3303));
A3311 <= ((not A3301) and A3302) or (A3301 and (not A3302));
A3310 <= A3311 and A3318;
A3309 <= A3311 and A3317;
A3308 <= A3316 or A3315;
A3307 <= A3314 or A3313;
A3306 <= A3312 and A3311;
A3305 <= A9543;
A3304 <= A9510;
A3303 <= A9477;
A3302 <= A9444;
A3301 <= A9411;
A3300 <= A3278 and A3293;
A3299 <= (not A3278) and (not A3300);
A3298 <= A3278 or A3293;
A3297 <= (not A3271) or (not A3272);
A3296 <= A3278 or A3293;
A3295 <= (not A3294) and (not A3278);
A3294 <= A3278 and A3293;
A3293 <= (not A3269) or (not A3270);
A3292 <= A3270 and A3282;
A3291 <= A3271 or A3278;
A3290 <= A3271 or A3272;
A3289 <= (not A3299) or (not A3298);
A3288 <= A3297 and A3290;
A3287 <= ((not A3271) and A3278) or (A3271 and (not A3278));
A3286 <= (not A3295) or (not A3296);
A3285 <= (A3270 and A3282) or ((not A3270) and (not A3282));
A3284 <= A3292 or A3269;
A3283 <= A3289 and A3270;
A3282 <= A3291 and A3290;
A3281 <= A3286 and A3270;
A3280 <= A3288 and A3287;
A3279 <= ((not A3280) and A3270) or (A3280 and (not A3270));
A3278 <= ((not A3268) and A3269) or (A3268 and (not A3269));
A3277 <= A3278 and A3285;
A3276 <= A3278 and A3284;
A3275 <= A3283 or A3282;
A3274 <= A3281 or A3280;
A3273 <= A3279 and A3278;
A3272 <= A9378;
A3271 <= A9345;
A3270 <= A9312;
A3269 <= A9279;
A3268 <= A9246;
A3267 <= A3245 and A3260;
A3266 <= (not A3245) and (not A3267);
A3265 <= A3245 or A3260;
A3264 <= (not A3238) or (not A3239);
A3263 <= A3245 or A3260;
A3262 <= (not A3261) and (not A3245);
A3261 <= A3245 and A3260;
A3260 <= (not A3236) or (not A3237);
A3259 <= A3237 and A3249;
A3258 <= A3238 or A3245;
A3257 <= A3238 or A3239;
A3256 <= (not A3266) or (not A3265);
A3255 <= A3264 and A3257;
A3254 <= ((not A3238) and A3245) or (A3238 and (not A3245));
A3253 <= (not A3262) or (not A3263);
A3252 <= (A3237 and A3249) or ((not A3237) and (not A3249));
A3251 <= A3259 or A3236;
A3250 <= A3256 and A3237;
A3249 <= A3258 and A3257;
A3248 <= A3253 and A3237;
A3247 <= A3255 and A3254;
A3246 <= ((not A3247) and A3237) or (A3247 and (not A3237));
A3245 <= ((not A3235) and A3236) or (A3235 and (not A3236));
A3244 <= A3245 and A3252;
A3243 <= A3245 and A3251;
A3242 <= A3250 or A3249;
A3241 <= A3248 or A3247;
A3240 <= A3246 and A3245;
A3239 <= A9213;
A3238 <= A9180;
A3237 <= A9147;
A3236 <= A9114;
A3235 <= A9081;
A3234 <= A3212 and A3227;
A3233 <= (not A3212) and (not A3234);
A3232 <= A3212 or A3227;
A3231 <= (not A3205) or (not A3206);
A3230 <= A3212 or A3227;
A3229 <= (not A3228) and (not A3212);
A3228 <= A3212 and A3227;
A3227 <= (not A3203) or (not A3204);
A3226 <= A3204 and A3216;
A3225 <= A3205 or A3212;
A3224 <= A3205 or A3206;
A3223 <= (not A3233) or (not A3232);
A3222 <= A3231 and A3224;
A3221 <= ((not A3205) and A3212) or (A3205 and (not A3212));
A3220 <= (not A3229) or (not A3230);
A3219 <= (A3204 and A3216) or ((not A3204) and (not A3216));
A3218 <= A3226 or A3203;
A3217 <= A3223 and A3204;
A3216 <= A3225 and A3224;
A3215 <= A3220 and A3204;
A3214 <= A3222 and A3221;
A3213 <= ((not A3214) and A3204) or (A3214 and (not A3204));
A3212 <= ((not A3202) and A3203) or (A3202 and (not A3203));
A3211 <= A3212 and A3219;
A3210 <= A3212 and A3218;
A3209 <= A3217 or A3216;
A3208 <= A3215 or A3214;
A3207 <= A3213 and A3212;
A3206 <= A9048;
A3205 <= A9015;
A3204 <= A8982;
A3203 <= A8949;
A3202 <= A8916;
A3201 <= A3179 and A3194;
A3200 <= (not A3179) and (not A3201);
A3199 <= A3179 or A3194;
A3198 <= (not A3172) or (not A3173);
A3197 <= A3179 or A3194;
A3196 <= (not A3195) and (not A3179);
A3195 <= A3179 and A3194;
A3194 <= (not A3170) or (not A3171);
A3193 <= A3171 and A3183;
A3192 <= A3172 or A3179;
A3191 <= A3172 or A3173;
A3190 <= (not A3200) or (not A3199);
A3189 <= A3198 and A3191;
A3188 <= ((not A3172) and A3179) or (A3172 and (not A3179));
A3187 <= (not A3196) or (not A3197);
A3186 <= (A3171 and A3183) or ((not A3171) and (not A3183));
A3185 <= A3193 or A3170;
A3184 <= A3190 and A3171;
A3183 <= A3192 and A3191;
A3182 <= A3187 and A3171;
A3181 <= A3189 and A3188;
A3180 <= ((not A3181) and A3171) or (A3181 and (not A3171));
A3179 <= ((not A3169) and A3170) or (A3169 and (not A3170));
A3178 <= A3179 and A3186;
A3177 <= A3179 and A3185;
A3176 <= A3184 or A3183;
A3175 <= A3182 or A3181;
A3174 <= A3180 and A3179;
A3173 <= A8883;
A3172 <= A8850;
A3171 <= A8817;
A3170 <= A8784;
A3169 <= A8751;
A3168 <= A3146 and A3161;
A3167 <= (not A3146) and (not A3168);
A3166 <= A3146 or A3161;
A3165 <= (not A3139) or (not A3140);
A3164 <= A3146 or A3161;
A3163 <= (not A3162) and (not A3146);
A3162 <= A3146 and A3161;
A3161 <= (not A3137) or (not A3138);
A3160 <= A3138 and A3150;
A3159 <= A3139 or A3146;
A3158 <= A3139 or A3140;
A3157 <= (not A3167) or (not A3166);
A3156 <= A3165 and A3158;
A3155 <= ((not A3139) and A3146) or (A3139 and (not A3146));
A3154 <= (not A3163) or (not A3164);
A3153 <= (A3138 and A3150) or ((not A3138) and (not A3150));
A3152 <= A3160 or A3137;
A3151 <= A3157 and A3138;
A3150 <= A3159 and A3158;
A3149 <= A3154 and A3138;
A3148 <= A3156 and A3155;
A3147 <= ((not A3148) and A3138) or (A3148 and (not A3138));
A3146 <= ((not A3136) and A3137) or (A3136 and (not A3137));
A3145 <= A3146 and A3153;
A3144 <= A3146 and A3152;
A3143 <= A3151 or A3150;
A3142 <= A3149 or A3148;
A3141 <= A3147 and A3146;
A3140 <= A8718;
A3139 <= A8685;
A3138 <= A8652;
A3137 <= A8619;
A3136 <= A8586;
A3135 <= A3113 and A3128;
A3134 <= (not A3113) and (not A3135);
A3133 <= A3113 or A3128;
A3132 <= (not A3106) or (not A3107);
A3131 <= A3113 or A3128;
A3130 <= (not A3129) and (not A3113);
A3129 <= A3113 and A3128;
A3128 <= (not A3104) or (not A3105);
A3127 <= A3105 and A3117;
A3126 <= A3106 or A3113;
A3125 <= A3106 or A3107;
A3124 <= (not A3134) or (not A3133);
A3123 <= A3132 and A3125;
A3122 <= ((not A3106) and A3113) or (A3106 and (not A3113));
A3121 <= (not A3130) or (not A3131);
A3120 <= (A3105 and A3117) or ((not A3105) and (not A3117));
A3119 <= A3127 or A3104;
A3118 <= A3124 and A3105;
A3117 <= A3126 and A3125;
A3116 <= A3121 and A3105;
A3115 <= A3123 and A3122;
A3114 <= ((not A3115) and A3105) or (A3115 and (not A3105));
A3113 <= ((not A3103) and A3104) or (A3103 and (not A3104));
A3112 <= A3113 and A3120;
A3111 <= A3113 and A3119;
A3110 <= A3118 or A3117;
A3109 <= A3116 or A3115;
A3108 <= A3114 and A3113;
A3107 <= A8553;
A3106 <= A8520;
A3105 <= A8487;
A3104 <= A8454;
A3103 <= A8421;
A3102 <= A3080 and A3095;
A3101 <= (not A3080) and (not A3102);
A3100 <= A3080 or A3095;
A3099 <= (not A3073) or (not A3074);
A3098 <= A3080 or A3095;
A3097 <= (not A3096) and (not A3080);
A3096 <= A3080 and A3095;
A3095 <= (not A3071) or (not A3072);
A3094 <= A3072 and A3084;
A3093 <= A3073 or A3080;
A3092 <= A3073 or A3074;
A3091 <= (not A3101) or (not A3100);
A3090 <= A3099 and A3092;
A3089 <= ((not A3073) and A3080) or (A3073 and (not A3080));
A3088 <= (not A3097) or (not A3098);
A3087 <= (A3072 and A3084) or ((not A3072) and (not A3084));
A3086 <= A3094 or A3071;
A3085 <= A3091 and A3072;
A3084 <= A3093 and A3092;
A3083 <= A3088 and A3072;
A3082 <= A3090 and A3089;
A3081 <= ((not A3082) and A3072) or (A3082 and (not A3072));
A3080 <= ((not A3070) and A3071) or (A3070 and (not A3071));
A3079 <= A3080 and A3087;
A3078 <= A3080 and A3086;
A3077 <= A3085 or A3084;
A3076 <= A3083 or A3082;
A3075 <= A3081 and A3080;
A3074 <= A8388;
A3073 <= A8355;
A3072 <= A8322;
A3071 <= A8289;
A3070 <= A8256;
A3069 <= A3047 and A3062;
A3068 <= (not A3047) and (not A3069);
A3067 <= A3047 or A3062;
A3066 <= (not A3040) or (not A3041);
A3065 <= A3047 or A3062;
A3064 <= (not A3063) and (not A3047);
A3063 <= A3047 and A3062;
A3062 <= (not A3038) or (not A3039);
A3061 <= A3039 and A3051;
A3060 <= A3040 or A3047;
A3059 <= A3040 or A3041;
A3058 <= (not A3068) or (not A3067);
A3057 <= A3066 and A3059;
A3056 <= ((not A3040) and A3047) or (A3040 and (not A3047));
A3055 <= (not A3064) or (not A3065);
A3054 <= (A3039 and A3051) or ((not A3039) and (not A3051));
A3053 <= A3061 or A3038;
A3052 <= A3058 and A3039;
A3051 <= A3060 and A3059;
A3050 <= A3055 and A3039;
A3049 <= A3057 and A3056;
A3048 <= ((not A3049) and A3039) or (A3049 and (not A3039));
A3047 <= ((not A3037) and A3038) or (A3037 and (not A3038));
A3046 <= A3047 and A3054;
A3045 <= A3047 and A3053;
A3044 <= A3052 or A3051;
A3043 <= A3050 or A3049;
A3042 <= A3048 and A3047;
A3041 <= A8223;
A3040 <= A8190;
A3039 <= A8157;
A3038 <= A8124;
A3037 <= A8091;
A3036 <= A3014 and A3029;
A3035 <= (not A3014) and (not A3036);
A3034 <= A3014 or A3029;
A3033 <= (not A3007) or (not A3008);
A3032 <= A3014 or A3029;
A3031 <= (not A3030) and (not A3014);
A3030 <= A3014 and A3029;
A3029 <= (not A3005) or (not A3006);
A3028 <= A3006 and A3018;
A3027 <= A3007 or A3014;
A3026 <= A3007 or A3008;
A3025 <= (not A3035) or (not A3034);
A3024 <= A3033 and A3026;
A3023 <= ((not A3007) and A3014) or (A3007 and (not A3014));
A3022 <= (not A3031) or (not A3032);
A3021 <= (A3006 and A3018) or ((not A3006) and (not A3018));
A3020 <= A3028 or A3005;
A3019 <= A3025 and A3006;
A3018 <= A3027 and A3026;
A3017 <= A3022 and A3006;
A3016 <= A3024 and A3023;
A3015 <= ((not A3016) and A3006) or (A3016 and (not A3006));
A3014 <= ((not A3004) and A3005) or (A3004 and (not A3005));
A3013 <= A3014 and A3021;
A3012 <= A3014 and A3020;
A3011 <= A3019 or A3018;
A3010 <= A3017 or A3016;
A3009 <= A3015 and A3014;
A3008 <= A8058;
A3007 <= A8025;
A3006 <= A7992;
A3005 <= A7959;
A3004 <= A7926;
A3003 <= A2981 and A2996;
A3002 <= (not A2981) and (not A3003);
A3001 <= A2981 or A2996;
A3000 <= (not A2974) or (not A2975);
A2999 <= A2981 or A2996;
A2998 <= (not A2997) and (not A2981);
A2997 <= A2981 and A2996;
A2996 <= (not A2972) or (not A2973);
A2995 <= A2973 and A2985;
A2994 <= A2974 or A2981;
A2993 <= A2974 or A2975;
A2992 <= (not A3002) or (not A3001);
A2991 <= A3000 and A2993;
A2990 <= ((not A2974) and A2981) or (A2974 and (not A2981));
A2989 <= (not A2998) or (not A2999);
A2988 <= (A2973 and A2985) or ((not A2973) and (not A2985));
A2987 <= A2995 or A2972;
A2986 <= A2992 and A2973;
A2985 <= A2994 and A2993;
A2984 <= A2989 and A2973;
A2983 <= A2991 and A2990;
A2982 <= ((not A2983) and A2973) or (A2983 and (not A2973));
A2981 <= ((not A2971) and A2972) or (A2971 and (not A2972));
A2980 <= A2981 and A2988;
A2979 <= A2981 and A2987;
A2978 <= A2986 or A2985;
A2977 <= A2984 or A2983;
A2976 <= A2982 and A2981;
A2975 <= A7893;
A2974 <= A7860;
A2973 <= A7827;
A2972 <= A7794;
A2971 <= A7761;
A2970 <= A2948 and A2963;
A2969 <= (not A2948) and (not A2970);
A2968 <= A2948 or A2963;
A2967 <= (not A2941) or (not A2942);
A2966 <= A2948 or A2963;
A2965 <= (not A2964) and (not A2948);
A2964 <= A2948 and A2963;
A2963 <= (not A2939) or (not A2940);
A2962 <= A2940 and A2952;
A2961 <= A2941 or A2948;
A2960 <= A2941 or A2942;
A2959 <= (not A2969) or (not A2968);
A2958 <= A2967 and A2960;
A2957 <= ((not A2941) and A2948) or (A2941 and (not A2948));
A2956 <= (not A2965) or (not A2966);
A2955 <= (A2940 and A2952) or ((not A2940) and (not A2952));
A2954 <= A2962 or A2939;
A2953 <= A2959 and A2940;
A2952 <= A2961 and A2960;
A2951 <= A2956 and A2940;
A2950 <= A2958 and A2957;
A2949 <= ((not A2950) and A2940) or (A2950 and (not A2940));
A2948 <= ((not A2938) and A2939) or (A2938 and (not A2939));
A2947 <= A2948 and A2955;
A2946 <= A2948 and A2954;
A2945 <= A2953 or A2952;
A2944 <= A2951 or A2950;
A2943 <= A2949 and A2948;
A2942 <= A7728;
A2941 <= A7695;
A2940 <= A7662;
A2939 <= A7629;
A2938 <= A7596;
A2937 <= A2915 and A2930;
A2936 <= (not A2915) and (not A2937);
A2935 <= A2915 or A2930;
A2934 <= (not A2908) or (not A2909);
A2933 <= A2915 or A2930;
A2932 <= (not A2931) and (not A2915);
A2931 <= A2915 and A2930;
A2930 <= (not A2906) or (not A2907);
A2929 <= A2907 and A2919;
A2928 <= A2908 or A2915;
A2927 <= A2908 or A2909;
A2926 <= (not A2936) or (not A2935);
A2925 <= A2934 and A2927;
A2924 <= ((not A2908) and A2915) or (A2908 and (not A2915));
A2923 <= (not A2932) or (not A2933);
A2922 <= (A2907 and A2919) or ((not A2907) and (not A2919));
A2921 <= A2929 or A2906;
A2920 <= A2926 and A2907;
A2919 <= A2928 and A2927;
A2918 <= A2923 and A2907;
A2917 <= A2925 and A2924;
A2916 <= ((not A2917) and A2907) or (A2917 and (not A2907));
A2915 <= ((not A2905) and A2906) or (A2905 and (not A2906));
A2914 <= A2915 and A2922;
A2913 <= A2915 and A2921;
A2912 <= A2920 or A2919;
A2911 <= A2918 or A2917;
A2910 <= A2916 and A2915;
A2909 <= A7563;
A2908 <= A7530;
A2907 <= A7497;
A2906 <= A7464;
A2905 <= A7431;
A2904 <= A2882 and A2897;
A2903 <= (not A2882) and (not A2904);
A2902 <= A2882 or A2897;
A2901 <= (not A2875) or (not A2876);
A2900 <= A2882 or A2897;
A2899 <= (not A2898) and (not A2882);
A2898 <= A2882 and A2897;
A2897 <= (not A2873) or (not A2874);
A2896 <= A2874 and A2886;
A2895 <= A2875 or A2882;
A2894 <= A2875 or A2876;
A2893 <= (not A2903) or (not A2902);
A2892 <= A2901 and A2894;
A2891 <= ((not A2875) and A2882) or (A2875 and (not A2882));
A2890 <= (not A2899) or (not A2900);
A2889 <= (A2874 and A2886) or ((not A2874) and (not A2886));
A2888 <= A2896 or A2873;
A2887 <= A2893 and A2874;
A2886 <= A2895 and A2894;
A2885 <= A2890 and A2874;
A2884 <= A2892 and A2891;
A2883 <= ((not A2884) and A2874) or (A2884 and (not A2874));
A2882 <= ((not A2872) and A2873) or (A2872 and (not A2873));
A2881 <= A2882 and A2889;
A2880 <= A2882 and A2888;
A2879 <= A2887 or A2886;
A2878 <= A2885 or A2884;
A2877 <= A2883 and A2882;
A2876 <= A7398;
A2875 <= A7365;
A2874 <= A7332;
A2873 <= A7299;
A2872 <= A7266;
A2871 <= A2849 and A2864;
A2870 <= (not A2849) and (not A2871);
A2869 <= A2849 or A2864;
A2868 <= (not A2842) or (not A2843);
A2867 <= A2849 or A2864;
A2866 <= (not A2865) and (not A2849);
A2865 <= A2849 and A2864;
A2864 <= (not A2840) or (not A2841);
A2863 <= A2841 and A2853;
A2862 <= A2842 or A2849;
A2861 <= A2842 or A2843;
A2860 <= (not A2870) or (not A2869);
A2859 <= A2868 and A2861;
A2858 <= ((not A2842) and A2849) or (A2842 and (not A2849));
A2857 <= (not A2866) or (not A2867);
A2856 <= (A2841 and A2853) or ((not A2841) and (not A2853));
A2855 <= A2863 or A2840;
A2854 <= A2860 and A2841;
A2853 <= A2862 and A2861;
A2852 <= A2857 and A2841;
A2851 <= A2859 and A2858;
A2850 <= ((not A2851) and A2841) or (A2851 and (not A2841));
A2849 <= ((not A2839) and A2840) or (A2839 and (not A2840));
A2848 <= A2849 and A2856;
A2847 <= A2849 and A2855;
A2846 <= A2854 or A2853;
A2845 <= A2852 or A2851;
A2844 <= A2850 and A2849;
A2843 <= A7233;
A2842 <= A7200;
A2841 <= A7167;
A2840 <= A7134;
A2839 <= A7101;
A2806 <= A7068;
A2807 <= A7035;
A2808 <= A7002;
A2809 <= A6969;
A2810 <= A6940;
A2811 <= A2817 and A2816;
A2812 <= A2819 or A2818;
A2813 <= A2821 or A2820;
A2814 <= A2816 and A2822;
A2815 <= A2816 and A2823;
A2816 <= ((not A2806) and A2807) or (A2806 and (not A2807));
A2817 <= ((not A2818) and A2808) or (A2818 and (not A2808));
A2818 <= A2826 and A2825;
A2819 <= A2824 and A2808;
A2820 <= A2829 and A2828;
A2821 <= A2827 and A2808;
A2822 <= A2830 or A2807;
A2823 <= (A2808 and A2820) or ((not A2808) and (not A2820));
A2824 <= (not A2833) or (not A2834);
A2825 <= ((not A2809) and A2816) or (A2809 and (not A2816));
A2826 <= A2835 and A2828;
A2827 <= (not A2837) or (not A2836);
A2828 <= A2809 or A2810;
A2829 <= A2809 or A2816;
A2830 <= A2808 and A2820;
A2831 <= (not A2807) or (not A2808);
A2832 <= A2816 and A2831;
A2833 <= (not A2832) and (not A2816);
A2834 <= A2816 or A2831;
A2835 <= (not A2809) or (not A2810);
A2836 <= A2816 or A2831;
A2837 <= (not A2816) and (not A2838);
A2838 <= A2816 and A2831;
end testing_behav;
| gpl-3.0 | 4a284ab3e79e835161d22c47d3ae2e5f | 0.61318 | 2.574132 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/ramfifo/rd_logic.vhd | 5 | 55,089 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
KiGptJTgfqBYZS72wh69LJC9ftH0usQfbwCqWpq6rKTKyZSFHTqV9jYUREWmB723cGIc30akrb7R
rwk5hSsJOQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
oDh97TlkJefnKqv55omMQ/ZmMIg5SM6QuYpKgFYNODgbGF/5rc6rWbGwOe1hjIKPsO4/NT2klxXD
dt/hQZgrEafpc7fubpzvKuNtQF+0ilkrCJk7x82TwqQqlkD6KjaK+gGEmn3f6bTnG2oJhMHvCq4N
oHgqcLMkAtVCbl7CV20=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
UfZCiEyJnA/VEE1lagPKMLZO1eFTrp5Fl/4XJFOl/8RBa04oZceVStDRlIUZIPo+k64+DsBVE/Is
RDsD2clfc3tIUHljYua9C+fiefafd0S7sxl/KDIf/ckKq6+B9ZMhQn6IVYshE4nKILXVv5gMy8Ve
CWff7IRU8Em7/9UL0d1dfiXZ3Y8j82CjbhGHczhsjD6GJZ15wF8PKEpjOkb1P350SW3C0e9smHby
E7vXpaztRvdAJmoQpW1om8fK3yzc9y0v5IXkAmckmHIquyrKkUWmpXsVFiFKHz7Bo8l/MA7tUTme
WcxrSiFOlHJJJWKv1Zi+21XopBRiPWUYLfHCeA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
t7et/RrkK1Y6zv5kUSWgI+KUOfrQNKE1oxsTklop5j7rCvYvz/esR+1xd+zy2pURy+aItRfHFC12
1QexHPPIuxafV4o3ncaEzKeqXaXEcZ9fFhn12dGGYqDJIH3UU5oieiew7kPUloN9++bvo2pOWzBh
Qh1U8PoY9vRvl9BvsOA=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
YfY3lGfEL2wTVsCSvOs4aQEMyq5AjKxYTAmPhnUtuSw9Zfza9lSS4dUKme1tZMjup4f/4ZHcEEFf
5BDmD7MEClBNe5kobK4ccmcyDi4tOv9gXn5aulmst1MbI1xTX6AkMmg0FdCkxaA8sUIzO41p26SA
yiSDKgkccfxANLylEkrbFCz/kh87DkijKjEtWxZNYg/Uk744fJW+ABuy6iGIDL8oNdeM+Kun4ZvX
9CyHlgKbXc1IJXR/MfFXKhd+HXxrq6dA/mBxFLgexORkHopz6C0YN0o4VwiQPS3pMM62qYD/MAFi
TfU/KLPX2Tq6yP6vaF/wWpHUYnbmBrt+IxsBpw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 39040)
`protect data_block
PLwkw0PPpG8za61yFvf7uHCEIsn5JyR5eXWeh8UmEpQ90SjHbQCCdxbMxVFPgRsX6dzUvY/bwUKX
73cgWIL5Nx5Bd6NLtOMmM5+HVk46iRKt6Qh2zCiDKqA1rnT+TPHP+yBHVsCmLATtxB5i1eJGidg7
Zaj3TvQz8uF0Kmr4KP4eQbBCs8UInm3ZmhMiZHW/plAVheJUGzvIBcgNzNN/b69mtzKJUU0M1LxQ
QgE1JW/Z7pEOZnqko4NvGqGdES4QRjoGHVhsBMlwWGKLzAbcgT0iWxfmVdZ7pd1gCEMtwCHT8NDM
ijkbueYX79BLUtbmLxKYwpAkeNcjTkijtr7QL3j9y9e9Rzq1CBRvQSErNz2xKDqgdcs3KWwn5NGp
CwpJglDH7bGxMD6fhywtoakENUpoe3WScMiPBa1Wd5jd5MXNCfDpVNAWZjMY6Ftj+1ootv2EkYYM
mnOpB7vr3bg54MU2nrz7uumZ43gvBDabYzXtR3SuvGv4s0gBcKCxIa0s4ifzw9s8QEsmoIfy+5rU
YvN7RNfrctwwn+PXl/zCqae0ZJhEnPTg5gAwCVf4+o3yYgUYfMR+m1Msz6uDxSSTkVRQmGV6do/V
cwldBXBF6u7RSHOkjVeIXJ9Md+GQpKP7Z5Cdy/efxUHAhBstIwfoTWw3JDhxyt2w0ZeVPQ2yguJ5
glmuPI2k7d8WmmfSHuHsOX2kC5y5ndWVQ4Wu7UoEajkp+lIK5njj2KDYMi/EWnY1Hd010539yxH4
0rERIqxhfQ12U3Eq4RUDyjDDjlJFQg+4UJYBCBWD5v2ZhcNO1O7FWFpCrKhw+4KhEhc1K7pb8p6s
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`protect end_protected
| apache-2.0 | faec5354d623e137986310d9af33f269 | 0.94999 | 1.824804 | false | false | false | false |
Abeergit/UART | BAUD_GEN.vhd | 1 | 836 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity baud_gen is
generic(
M: integer := 16 -- Divisor for sample rate (clk/sample_rate)
);
port(
clk, reset: in std_logic;
max_tick: out std_logic
);
end baud_gen;
architecture main of baud_gen is
signal r_reg, r_next: integer range 0 to (M-1);
begin
-- register
process(clk,reset,r_reg, r_next)
begin
if (rising_edge(clk) and clk='1') then
if (reset='1') then
r_reg <= 0;
elsif (reset = '0') then
r_reg <= r_next;
end if;
end if;
end process;
-- next-state logic
r_next <= 0 when r_reg=(M-1) else r_reg + 1;
-- output logic
max_tick <= '1' when r_reg=(M-1) else '0';
end main;
| mit | 5813ff4a51b727af48ae7b71b7e87290 | 0.521531 | 3.203065 | false | false | false | false |
BBN-Q/APS2-Comms | test/com5402_wrapper_tb.vhd | 1 | 24,428 | -- Testbench for com5402_wrapper
--
-- * ARP requests
-- * broadcast udp rx
-- * unicast udp rx
-- * unicast udp rx filtering
-- * udp tx with NACK from ComBlock
-- * tcp conneciton establish
-- * tcp tx with tready deasserting
--
-- Original author: Colm Ryan
-- Copyright 2015,2016 Raytheon BBN Technologies
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ethernet_frame_pkg.all;
use work.IPv4_packet_pkg.all;
entity com5402_wrapper_tb is
end;
architecture bench of com5402_wrapper_tb is
constant APS2_UDP_PORT : std_logic_vector(15 downto 0) := x"bb4f";
constant UUT_MAC_ADDR : MACAddr_t := (x"46", x"1d", x"db", x"11", x"22", x"33");
constant UUT_IP_ADDR : IPv4_addr_t := (x"c0", x"a8", x"02", x"03");
constant HOST_MAC_ADDR : MACAddr_t := (x"ba", x"ad", x"0d", x"db", x"a1", x"11");
constant HOST_IP_ADDR : IPv4_addr_t := (x"c0", x"a8", x"02", x"01");
constant HOST2_MAC_ADDR : MACAddr_t := (x"ba", x"ad", x"0d", x"db", x"a1", x"12");
constant HOST2_IP_ADDR : IPv4_addr_t := (x"c0", x"a8", x"02", x"51");
constant BROADCAST_IP_ADDR : IPv4_addr_t := (x"c0", x"a8", x"02", x"ff");
constant WRONG_IP_ADDR : IPv4_addr_t := (x"c0", x"a8", x"02", x"04");
constant BROADCAST_MAC_ADDR : MACAddr_t := (x"ff", x"ff", x"ff", x"ff", x"ff", x"ff");
-- "I am an APS2"
constant ENUMERATE_RESPONSE : byte_array :=
(x"49", x"20", x"61", x"6d", x"20", x"61", x"6e", x"20", x"41", x"50", x"53", x"32");
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal mac_addr : std_logic_vector(47 downto 0) := UUT_MAC_ADDR(0) & UUT_MAC_ADDR(1) & UUT_MAC_ADDR(2) & UUT_MAC_ADDR(3) & UUT_MAC_ADDR(4) & UUT_MAC_ADDR(5);
signal IPv4_addr : std_logic_vector(31 downto 0) := UUT_IP_ADDR(0) & UUT_IP_ADDR(1) & UUT_IP_ADDR(2) & UUT_IP_ADDR(3);
signal subnet_mask : std_logic_vector(31 downto 0) := x"ffffff00";
signal gateway_ip_addr : std_logic_vector(31 downto 0) := x"c0a80201";
signal tcp_rst : std_logic := '0';
signal dhcp_enable : std_logic := '0';
signal mac_tx_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal mac_tx_tvalid : std_logic := '0';
signal mac_tx_tlast : std_logic := '0';
signal mac_tx_tuser : std_logic := '0';
signal mac_tx_tready : std_logic := '1';
signal mac_rx_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal mac_rx_tvalid : std_logic := '0';
signal mac_rx_tlast : std_logic := '0';
signal mac_rx_tuser : std_logic := '0';
signal mac_rx_tready : std_logic := '0';
signal udp_rx_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal udp_rx_tvalid : std_logic := '0';
signal udp_rx_tlast : std_logic := '0';
signal udp_rx_src_port : std_logic_vector(15 downto 0) := (others => '0');
signal rx_src_ip_addr : std_logic_vector(31 downto 0);
signal udp_tx_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal udp_tx_tvalid : std_logic := '0';
signal udp_tx_tlast : std_logic := '0';
signal udp_tx_tready : std_logic := '0';
signal udp_tx_src_port : std_logic_vector(15 downto 0) := APS2_UDP_PORT;
signal udp_tx_dest_port : std_logic_vector(15 downto 0) := APS2_UDP_PORT;
signal udp_tx_dest_ip_addr : std_logic_vector(31 downto 0) := HOST2_IP_ADDR(0) & HOST2_IP_ADDR(1) & HOST2_IP_ADDR(2) & HOST2_IP_ADDR(3);
signal udp_tx_ack : std_logic;
signal udp_tx_nack : std_logic;
signal tcp_port : std_logic_vector(15 downto 0) := x"bb4e";
signal tcp_rx_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal tcp_rx_tvalid : std_logic := '0';
signal tcp_rx_tready : std_logic := '1';
signal tcp_tx_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal tcp_tx_tvalid : std_logic := '0';
signal tcp_tx_tready : std_logic := '0';
constant clock_period: time := 8 ns;
signal stop_the_clock: boolean := false;
type TestBenchState_t is (RESET, ARP_REQUEST, UDP_BROADCAST_RX, UDP_UNICAST_RX,
NO_INTERFRAME_GAP, UDP_UNICAST_IP_FILTER, UDP_TX,
ARP_RESPONSE, UDP_TX_RETRY, TCP_ESTABLISH, TCP_RX, DHCP);
signal testBench_state : TestBenchState_t;
signal checking_finished : boolean := false;
shared variable tcp_test_payload : byte_array(0 to 1023);
begin
uut: entity work.com5402_wrapper
generic map ( SIMULATION => '1')
port map (
clk => clk,
rst => rst,
tcp_rst => tcp_rst,
mac_addr => mac_addr,
IPv4_addr => IPv4_addr,
subnet_mask => subnet_mask,
gateway_ip_addr => gateway_ip_addr,
dhcp_enable => dhcp_enable,
mac_tx_tdata => mac_tx_tdata,
mac_tx_tvalid => mac_tx_tvalid,
mac_tx_tlast => mac_tx_tlast,
mac_tx_tuser => mac_tx_tuser,
mac_tx_tready => mac_tx_tready,
mac_rx_tdata => mac_rx_tdata,
mac_rx_tvalid => mac_rx_tvalid,
mac_rx_tlast => mac_rx_tlast,
mac_rx_tuser => mac_rx_tuser,
mac_rx_tready => mac_rx_tready,
udp_rx_tdata => udp_rx_tdata,
udp_rx_tvalid => udp_rx_tvalid,
udp_rx_tlast => udp_rx_tlast,
udp_rx_dest_port => APS2_UDP_PORT,
udp_rx_src_port => udp_rx_src_port,
rx_src_ip_addr => rx_src_ip_addr,
udp_tx_tdata => udp_tx_tdata,
udp_tx_tvalid => udp_tx_tvalid,
udp_tx_tlast => udp_tx_tlast,
udp_tx_tready => udp_tx_tready,
udp_tx_src_port => udp_tx_src_port,
udp_tx_dest_port => udp_tx_dest_port,
udp_tx_dest_ip_addr => udp_tx_dest_ip_addr,
udp_tx_ack => udp_tx_ack,
udp_tx_nack => udp_tx_nack,
tcp_port => tcp_port,
tcp_rx_tdata => tcp_rx_tdata,
tcp_rx_tvalid => tcp_rx_tvalid,
tcp_rx_tready => tcp_rx_tready,
tcp_tx_tdata => tcp_tx_tdata,
tcp_tx_tvalid => tcp_tx_tvalid,
tcp_tx_tready => tcp_tx_tready
);
clk <= not clk after clock_period / 2 when not stop_the_clock;
stimulus: process
constant ARP_req : byte_array := (
x"00", x"01", -- hardware type
x"08", x"00", -- protocol type
x"06", --hardware length (MAC address is 6 bytes)
x"04", --protocol size
x"00", x"01", -- request operation
HOST_MAC_ADDR(0), HOST_MAC_ADDR(1), HOST_MAC_ADDR(2),
HOST_MAC_ADDR(3), HOST_MAC_ADDR(4), HOST_MAC_ADDR(5), --sender MAC address
HOST_IP_ADDR(0), HOST_IP_ADDR(1), HOST_IP_ADDR(2), HOST_IP_ADDR(3), --sender IPv4 address
x"00", x"00", x"00", x"00", x"00", x"00", --target MAC address; empty for request
UUT_IP_ADDR(0), UUT_IP_ADDR(1), UUT_IP_ADDR(2), UUT_IP_ADDR(3) -- target IP address
);
constant ARP_resp : byte_array := (
x"00", x"01", -- hardware type
x"08", x"00", -- protocol type
x"06", --hardware length (MAC address is 6 bytes)
x"04", --protocol size
x"00", x"02", -- response operation
HOST2_MAC_ADDR(0), HOST2_MAC_ADDR(1), HOST2_MAC_ADDR(2),
HOST2_MAC_ADDR(3), HOST2_MAC_ADDR(4), HOST2_MAC_ADDR(5), --sender MAC address
HOST2_IP_ADDR(0), HOST2_IP_ADDR(1), HOST2_IP_ADDR(2), HOST2_IP_ADDR(3), -- sender IP address
UUT_MAC_ADDR(0), UUT_MAC_ADDR(1), UUT_MAC_ADDR(2),
UUT_MAC_ADDR(3), UUT_MAC_ADDR(4), UUT_MAC_ADDR(5), --target MAC address
UUT_IP_ADDR(0), UUT_IP_ADDR(1), UUT_IP_ADDR(2), UUT_IP_ADDR(3) --target IPv4 address
);
constant empty_payload : byte_array(0 to -1) := (others => (others => '0'));
constant UDP_test_payload : byte_array := (x"01", x"02", x"03", x"04");
variable tcp_response_packet : byte_array(0 to 1521);
variable ct : natural;
variable seq_num, ack_num, recv_seq_num, recv_ack_num : natural;
variable tmp : std_logic_vector(31 downto 0);
variable src_MAC, dest_MAC : MACAddr_t := (others => (others => '0'));
variable timeout : time;
begin
wait until rising_edge(clk);
--------------------------------------------------------------------------------
testBench_state <= RESET;
rst <= '1';
wait for 100ns;
wait until rising_edge(clk);
rst <= '0';
wait for 100ns;
wait until rising_edge(clk);
--------------------------------------------------------------------------------
testBench_state <= ARP_REQUEST;
--ARP request who has 192.168.2.3? Tell 192.168.2.1";
src_MAC := (x"ba", x"ad", x"0d", x"db", x"a1", x"11");
dest_MAC := (x"FF", x"FF", x"FF", x"FF", x"FF", x"FF");
write_ethernet_frame(dest_MAC, src_MAC, x"0806", ARP_req, clk, mac_rx_tdata,
mac_rx_tvalid, mac_rx_tlast, mac_rx_tready);
mac_rx_tlast <= '1';
--wait for the response to come back
wait until rising_edge(clk) and mac_tx_tvalid = '1' and mac_tx_tlast = '1' for 1us;
--Make sure nothing else comes back
--coverage for issue #26
timeout := now + 5 us;
while now < timeout loop
wait until rising_edge(clk);
assert mac_tx_tvalid = '0' report "mac_tx traffic when there shouldn't be";
assert mac_tx_tlast = '0' report "mac_tx traffic when there shouldn't be";
end loop;
--------------------------------------------------------------------------------
--Clock in a broadcast UDP packet
testBench_state <= UDP_BROADCAST_RX;
dest_MAC := UUT_MAC_ADDR;
write_ethernet_frame(BROADCAST_MAC_ADDR, src_MAC, x"0800",
udp_packet(HOST_IP_ADDR, BROADCAST_IP_ADDR, x"abcd", APS2_UDP_PORT, UDP_test_payload),
clk, mac_rx_tdata, mac_rx_tvalid, mac_rx_tlast, mac_rx_tready);
--interframe gap
for ct in 1 to 12 loop
wait until rising_edge(clk);
end loop;
--Clock in an unicast UDP packet to the correct IP
testBench_state <= UDP_UNICAST_RX;
dest_MAC := UUT_MAC_ADDR;
write_ethernet_frame(dest_MAC, src_MAC, x"0800",
udp_packet(HOST_IP_ADDR, UUT_IP_ADDR, APS2_UDP_PORT, APS2_UDP_PORT, UDP_test_payload),
clk, mac_rx_tdata, mac_rx_tvalid, mac_rx_tlast, mac_rx_tready);
--repeat with no interframe gap to test gap adder
testBench_state <= NO_INTERFRAME_GAP;
dest_MAC := UUT_MAC_ADDR;
write_ethernet_frame(dest_MAC, src_MAC, x"0800",
udp_packet(HOST_IP_ADDR, UUT_IP_ADDR, APS2_UDP_PORT, APS2_UDP_PORT, UDP_test_payload),
clk, mac_rx_tdata, mac_rx_tvalid, mac_rx_tlast, mac_rx_tready);
--interframe gap
for ct in 1 to 12 loop
wait until rising_edge(clk);
end loop;
--Clock in a unicast UDP packet to the wrong IP
testBench_state <= UDP_UNICAST_IP_FILTER;
dest_MAC := UUT_MAC_ADDR;
write_ethernet_frame(dest_MAC, src_MAC, x"0800",
udp_packet(HOST_IP_ADDR, WRONG_IP_ADDR, APS2_UDP_PORT, APS2_UDP_PORT, UDP_test_payload),
clk, mac_rx_tdata, mac_rx_tvalid, mac_rx_tlast, mac_rx_tready);
--------------------------------------------------------------------------------
--Try to send a response to UDP
--Send to different host to trigger ARP request and NACK
testBench_state <= UDP_TX;
wait until rising_edge(clk);
for ct in 0 to ENUMERATE_RESPONSE'high loop
udp_tx_tdata <= ENUMERATE_RESPONSE(ct);
udp_tx_tvalid <= '1';
if ct = ENUMERATE_RESPONSE'high then
udp_tx_tlast <= '1';
else
udp_tx_tlast <= '0';
end if;
wait until rising_edge(clk) and udp_tx_tready = '1';
end loop;
udp_tx_tvalid <= '0';
udp_tx_tlast <= '0';
wait until mac_tx_tvalid = '1' and mac_tx_tlast = '1' for 5 us;
--Send back the ARP response
testBench_state <= ARP_RESPONSE;
src_MAC := (x"ba", x"ad", x"0d", x"db", x"a1", x"12");
write_ethernet_frame(dest_MAC, src_MAC, x"0806", ARP_resp, clk, mac_rx_tdata,
mac_rx_tvalid, mac_rx_tlast, mac_rx_tready);
wait for 5 us;
--Try again the UDP_TX
testBench_state <= UDP_TX_RETRY;
wait until rising_edge(clk);
for ct in 0 to ENUMERATE_RESPONSE'high loop
udp_tx_tdata <= ENUMERATE_RESPONSE(ct);
udp_tx_tvalid <= '1';
if ct = ENUMERATE_RESPONSE'high then
udp_tx_tlast <= '1';
else
udp_tx_tlast <= '0';
end if;
wait until rising_edge(clk) and udp_tx_tready = '1';
end loop;
udp_tx_tvalid <= '0';
udp_tx_tlast <= '0';
wait until mac_tx_tvalid = '1' and mac_tx_tlast = '1' for 5 us;
--------------------------------------------------------------------------------
--Try to establish TCP connection
seq_num := 0;
ack_num := 0;
testBench_state <= TCP_ESTABLISH;
wait until rising_edge(clk);
write_ethernet_frame(dest_MAC, src_MAC, x"0800",
tcp_packet(HOST_IP_ADDR, UUT_IP_ADDR, x"bb4f", x"bb4e", seq_num, ack_num, '1', '0', empty_payload),
clk, mac_rx_tdata, mac_rx_tvalid, mac_rx_tlast, mac_rx_tready);
--extract the sequence and ack number returned
ct := 0;
loop
wait until rising_edge(clk) and mac_tx_tvalid = '1';
tcp_response_packet(ct) := mac_tx_tdata;
ct := ct + 1;
exit when mac_tx_tlast = '1';
end loop;
--sequence number starts at byte 14 (ethernet frame header) + 20 (IPv4 header) + 4 (tcp src/dest port)= 38
--For some reason Vivado can't infer this as one line
-- recv_seq_num := to_integer(unsigned( tcp_response_packet(38) & tcp_response_packet(39) & tcp_response_packet(40) & tcp_response_packet(41) ) );
-- recv_ack_num := to_integer(unsigned( tcp_response_packet(42) & tcp_response_packet(43) & tcp_response_packet(44) & tcp_response_packet(45) ) );
tmp := tcp_response_packet(38) & tcp_response_packet(39) & tcp_response_packet(40) & tcp_response_packet(41);
recv_seq_num := to_integer(unsigned(tmp));
tmp := tcp_response_packet(42) & tcp_response_packet(43) & tcp_response_packet(44) & tcp_response_packet(45);
recv_ack_num := to_integer(unsigned(tmp));
ack_num := recv_seq_num + 1;
seq_num := recv_ack_num;
--send ack back to finish connection established
wait until rising_edge(clk);
write_ethernet_frame(dest_MAC, src_MAC, x"0800",
tcp_packet(HOST_IP_ADDR, UUT_IP_ADDR, x"bb4f", x"bb4e", seq_num, ack_num, '0', '1', empty_payload),
clk, mac_rx_tdata, mac_rx_tvalid, mac_rx_tlast, mac_rx_tready);
--interframe gap
for ct in 1 to 12 loop
wait until rising_edge(clk);
end loop;
--send data
testBench_state <= TCP_RX;
for k in 0 to 1023 loop
tcp_test_payload(k) := std_logic_vector(to_unsigned(k, 8));
end loop;
wait until rising_edge(clk);
write_ethernet_frame(dest_MAC, src_MAC, x"0800",
tcp_packet(HOST_IP_ADDR, UUT_IP_ADDR, x"bb4f", x"bb4e", seq_num, ack_num, '0', '1', tcp_test_payload),
clk, mac_rx_tdata, mac_rx_tvalid, mac_rx_tlast, mac_rx_tready);
ct := 0;
loop
wait until rising_edge(clk) and mac_tx_tvalid = '1';
tcp_response_packet(ct) := mac_tx_tdata;
ct := ct + 1;
exit when mac_tx_tlast = '1';
end loop;
--wait for the data to show up
wait until tcp_rx_tvalid = '1' for 100 ns;
-- let the first half go by then start dropping ready periodically
ct := 0;
loop
if ct < 512 then
tcp_rx_tready <= '1';
wait until rising_edge(clk);
else
if (ct mod 16) = 0 then
tcp_rx_tready <= '0';
wait until rising_edge(clk);
wait until rising_edge(clk);
else
tcp_rx_tready <= '1';
wait until rising_edge(clk);
end if;
end if;
ct := ct + 1;
exit when ct = 1024;
end loop;
tcp_rx_tready <= '1';
wait for 500 ns;
--------------------------------------------------------------------------------
testBench_state <= DHCP;
dhcp_enable <= '1';
wait until mac_tx_tvalid = '1' and mac_tx_tlast = '1' for 250us;
assert checking_finished report "Checking process failed to finish";
wait for 1 us;
stop_the_clock <= true;
end process;
checking : process
constant ARP_resp : byte_array := (
x"00", x"01", -- hardware type
x"08", x"00", -- protocol type
x"06", --hardware length (MAC address is 6 bytes)
x"04", --protocol size
x"00", x"02", -- response operation
UUT_MAC_ADDR(0), UUT_MAC_ADDR(1), UUT_MAC_ADDR(2),
UUT_MAC_ADDR(3), UUT_MAC_ADDR(4), UUT_MAC_ADDR(5), --sender MAC address
UUT_IP_ADDR(0), UUT_IP_ADDR(1), UUT_IP_ADDR(2), UUT_IP_ADDR(3), --sender IPv4 address
HOST_MAC_ADDR(0), HOST_MAC_ADDR(1), HOST_MAC_ADDR(2),
HOST_MAC_ADDR(3), HOST_MAC_ADDR(4), HOST_MAC_ADDR(5), --target MAC address
HOST_IP_ADDR(0), HOST_IP_ADDR(1), HOST_IP_ADDR(2), HOST_IP_ADDR(3) -- target IP address
);
constant ARP_req : byte_array := (
x"00", x"01", -- hardware type
x"08", x"00", -- protocol type
x"06", --hardware length (MAC address is 6 bytes)
x"04", --protocol size
x"00", x"01", -- request operation
UUT_MAC_ADDR(0), UUT_MAC_ADDR(1), UUT_MAC_ADDR(2),
UUT_MAC_ADDR(3), UUT_MAC_ADDR(4), UUT_MAC_ADDR(5), --sender MAC address
UUT_IP_ADDR(0), UUT_IP_ADDR(1), UUT_IP_ADDR(2), UUT_IP_ADDR(3), --sender IPv4 address
x"00", x"00", x"00", x"00", x"00", x"00", --target MAC address; empty for request
HOST2_IP_ADDR(0), HOST2_IP_ADDR(1), HOST2_IP_ADDR(2), HOST2_IP_ADDR(3) -- target IP address
);
begin
--------------------------------------------------------------------------------
--First thing back is the ARP response
--Ethernet frame header
for ct in 0 to 5 loop
wait until rising_edge(clk) and mac_tx_tvalid = '1';
assert mac_tx_tdata = HOST_MAC_ADDR(ct) report "ARP response ethernet frame MAC header incorrect";
end loop;
for ct in 0 to 5 loop
wait until rising_edge(clk) and mac_tx_tvalid = '1';
assert mac_tx_tdata = UUT_MAC_ADDR(ct) report "ARP response ethernet frame MAC header incorrect";
end loop;
--Ethernet type
wait until rising_edge(clk) and mac_tx_tvalid = '1';
assert mac_tx_tdata = x"08" report "ARP response ethernet frame MAC header incorrect";
wait until rising_edge(clk) and mac_tx_tvalid = '1';
assert mac_tx_tdata = x"06" report "ARP response ethernet frame MAC header incorrect";
for ct in 0 to ARP_resp'high loop
wait until rising_edge(clk) and mac_tx_tvalid = '1';
assert mac_tx_tdata = ARP_resp(ct) report "ARP response payload incorrect";
if ct = ARP_resp'high then
assert mac_tx_tlast = '1' report "tlast failed to assert end of ARP response";
else
assert mac_tx_tlast = '0' report "tlast asserted early in ARP response";
end if;
end loop;
--------------------------------------------------------------------------------
-- broadcast UDP packet at udp_rx should come through
wait until rising_edge(clk) and mac_rx_tvalid = '1';
-- wait for header (14 Ethernet + 20 IP + 8 UDP) and latency (4)
for ct in 1 to 46 loop
wait until rising_edge(clk);
end loop;
assert udp_rx_src_port = x"abcd" report "UDP source port incorrect";
assert rx_src_ip_addr = HOST_IP_ADDR(0) & HOST_IP_ADDR(1) & HOST_IP_ADDR(2) & HOST_IP_ADDR(3) report "RX source IP address incorrect";
for ct in 0 to 3 loop
assert udp_rx_tdata = std_logic_vector(to_unsigned(ct+1,8));
assert udp_rx_tvalid = '1' report "udp_rx_tvalid failed to assert";
if ct = 3 then
assert udp_rx_tlast = '1' report "udp_rx_tlast failed to assert";
else
assert udp_rx_tlast = '0' report "udp_rx_tlast asserted incorrectly";
wait until rising_edge(clk);
end if;
end loop;
--wait for end of packet
wait until rising_edge(clk) and mac_rx_tlast = '1' for 1 us;
---unicast UDP packet at udp_rx
wait until rising_edge(clk) and mac_rx_tvalid = '1';
-- wait for header (14 Ethernet + 20 IP + 8 UDP) and latency (4)
for ct in 1 to 46 loop
wait until rising_edge(clk);
end loop;
assert udp_rx_src_port = APS2_UDP_PORT report "UDP source port incorrect";
assert rx_src_ip_addr = HOST_IP_ADDR(0) & HOST_IP_ADDR(1) & HOST_IP_ADDR(2) & HOST_IP_ADDR(3) report "RX source IP address incorrect";
for ct in 0 to 3 loop
assert udp_rx_tdata = std_logic_vector(to_unsigned(ct+1,8));
assert udp_rx_tvalid = '1' report "udp_rx_tvalid failed to assert";
if ct = 3 then
assert udp_rx_tlast = '1' report "udp_rx_tlast failed to assert";
else
assert udp_rx_tlast = '0' report "udp_rx_tlast asserted incorrectly";
wait until rising_edge(clk);
end if;
end loop;
--wait for end of packet
wait until rising_edge(clk) and mac_rx_tlast = '1' for 1 us;
---second unicast UDP packet at udp_rx should be delayed by added interframe gap
wait until rising_edge(clk) and mac_rx_tvalid = '1';
for ct in 1 to 8 loop
assert mac_rx_tready = '0' report "mac_rx_tready failed to deassert for interframe gap";
wait until rising_edge(clk);
end loop;
-- wait for header (14 Ethernet + 20 IP + 8 UDP) and latency (4)
for ct in 1 to 46 loop
wait until rising_edge(clk);
end loop;
assert udp_rx_src_port = APS2_UDP_PORT report "UDP source port incorrect";
assert rx_src_ip_addr = HOST_IP_ADDR(0) & HOST_IP_ADDR(1) & HOST_IP_ADDR(2) & HOST_IP_ADDR(3) report "RX source IP address incorrect";
for ct in 0 to 3 loop
assert udp_rx_tdata = std_logic_vector(to_unsigned(ct+1,8));
assert udp_rx_tvalid = '1' report "udp_rx_tvalid failed to assert";
if ct = 3 then
assert udp_rx_tlast = '1' report "udp_rx_tlast failed to assert";
else
assert udp_rx_tlast = '0' report "udp_rx_tlast asserted incorrectly";
wait until rising_edge(clk);
end if;
end loop;
--wait for end of packet
wait until rising_edge(clk) and mac_rx_tlast = '1' for 1 us;
---unicast UDP packet to different IP address should not come through at udp_rx
wait until rising_edge(clk) and mac_rx_tvalid = '1';
-- wait for header (14 Ethernet + 20 IP + 8 UDP) and latency (4)
for ct in 1 to 46 loop
wait until rising_edge(clk);
end loop;
for ct in 0 to 3 loop
assert udp_rx_tvalid = '0' report "udp_rx_tvalid asserted incorrectly";
wait until rising_edge(clk);
end loop;
--wait for end of packet
wait until rising_edge(clk) and mac_rx_tlast = '1' for 1 us;
--------------------------------------------------------------------------------
--Next is a ARP request at mac_tx
--Ethernet frame header
for ct in 0 to 5 loop
wait until rising_edge(clk) and mac_tx_tvalid = '1';
assert mac_tx_tdata = x"ff" report "ARP request ethernet frame MAC header incorrect";
end loop;
for ct in 0 to 5 loop
wait until rising_edge(clk) and mac_tx_tvalid = '1';
assert mac_tx_tdata = UUT_MAC_ADDR(ct) report "ARP request ethernet frame MAC header incorrect";
end loop;
--Ethernet type
wait until rising_edge(clk) and mac_tx_tvalid = '1';
assert mac_tx_tdata = x"08" report "ARP request ethernet frame MAC header incorrect";
wait until rising_edge(clk) and mac_tx_tvalid = '1';
assert mac_tx_tdata = x"06" report "ARP request ethernet frame MAC header incorrect";
for ct in 0 to ARP_req'high loop
wait until rising_edge(clk) and mac_tx_tvalid = '1';
assert mac_tx_tdata = ARP_req(ct) report "ARP request payload incorrect";
if ct = ARP_resp'high then
assert mac_tx_tlast = '1' report "tlast failed to assert end of ARP request";
else
assert mac_tx_tlast = '0' report "tlast asserted early in ARP request";
end if;
end loop;
--Next is UDP tx appearing at mac_tx
--count off header (should be checking) 14 bytes ethernet frame header; 20 bytes IpV4 header; 8 byte UDP header
for ct in 1 to 42 loop
wait until rising_edge(clk) and mac_tx_tvalid = '1';
end loop;
--Now check ennumerate response
for ct in 0 to ENUMERATE_RESPONSE'high loop
wait until rising_edge(clk) and mac_tx_tvalid = '1';
assert mac_tx_tdata = ENUMERATE_RESPONSE(ct) report "udp_tx data incorrect";
end loop;
--Next is TCP stream at tcp_rx
for ct in 0 to 1023 loop
wait until rising_edge(clk) and tcp_rx_tvalid = '1' and tcp_rx_tready = '1';
assert tcp_rx_tdata = tcp_test_payload(ct) report "tcp data incorrect";
end loop;
--Next is DHCP request
--TODO: checking
checking_finished <= true;
wait;
end process;
end;
| mpl-2.0 | 05e3b2dd3fe5481941c4bc464cf3a192 | 0.595137 | 3.151187 | false | false | false | false |
rcls/sdr | vhdl/sampler.vhd | 1 | 1,361 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.defs.all;
use work.sincos.all;
entity sampler is
port (data : in signed14;
decay : in unsigned(15 downto 0);
rate : in unsigned8;
q : out signed15;
strobe : out std_logic;
clk : in std_logic);
end sampler;
architecture sampler of sampler is
signal low1, fb1, low2, decay2 : signed18;
signal prod3, acc : signed36;
signal data1, data2, data3, data4 : signed14;
signal decay_off : boolean;
signal divide : unsigned9;
begin
decay_off <= (decay = x"0000");
process
variable q_acc_addend : signed15;
begin
wait until rising_edge(clk);
if not decay_off then
low1 <= data(13) & data(13) & data & "00";
fb1 <= acc(33 downto 16);
low2 <= low1 - fb1;
decay2 <= '0' & signed(decay) & '0';
prod3 <= low2 * decay2;
acc <= acc + prod3;
end if;
data1 <= data;
data2 <= data1;
data3 <= data2;
data4 <= data3;
strobe <= divide(8);
if divide(8) = '1' then
divide <= ('0' & rate) - 1;
if decay_off then
q_acc_addend := (others => '0');
else
q_acc_addend := acc(32 downto 18);
end if;
q <= data4 + q_acc_addend;
else
divide <= divide - 1;
end if;
end process;
end sampler;
| gpl-3.0 | ef40939cc8920f0b8744d5f61c973474 | 0.569434 | 3.240476 | false | false | false | false |
CyAScott/CIS4930.DatapathSynthesisTool | src/components/c_bus.vhd | 1 | 807 | library ieee;
use ieee.std_logic_1164.all;
entity c_bus is
generic
(
width : integer;
no_of_inputs : integer
);
port
(
input : in Std_logic_vector (((width * no_of_inputs) - 1) downto 0);
BUS_SELECT : in Std_logic_vector ((no_of_inputs - 1) downto 0);
output : out Std_logic_vector ((width - 1) downto 0)
);
end c_bus;
architecture behavior of c_bus is
begin
P1 : process (bus_select, input)
variable control_val : integer := 0;
variable drive : boolean := FALSE;
begin
for i in 0 to (no_of_inputs - 1) loop
if (bus_select(i) = '1') then
output <= input(((i + 1) * width - 1) downto (i) * width);
drive := TRUE;
end if;
end loop;
if (drive = FALSE) then
for i in 0 to (width - 1) loop
output(i) <= 'Z';
end loop;
end if;
end process P1;
end behavior; | mit | abefdb12aebc8d2a35b63ae11a8e941d | 0.6171 | 2.708054 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/pc_module.vhd | 1 | 20,504 | `protect begin_protected
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`protect end_protected
| apache-2.0 | 40bc8e39e7e6efd566e4e7d6dc49fc70 | 0.94245 | 1.858762 | false | false | false | false |
CyAScott/CIS4930.DatapathSynthesisTool | src/components/ram.vhd | 1 | 1,081 | library ieee;
use ieee.std_logic_1164.all;
library WORK;
use WORK.all;
entity ram is
generic
(
width : integer;
ram_select : integer
);
port
(
input1 : in std_logic_vector((width - 1) downto 0);
input2 : in std_logic_vector((ram_select - 1) downto 0);
wr, rd, clock : in std_logic;
output : out std_logic_vector((width - 1) downto 0)
);
end ram;
architecture behavior of ram is
function bits_to_int (input : std_logic_vector)return integer is
variable ret_val : integer := 0;
begin
for i in input'range loop
if input(i) = '1' then
ret_val := 2 ** i + ret_val;
end if;
end loop; return ret_val;
end bits_to_int;
type mem_type is array(0 to (2 ** ram_select - 1)) of
std_logic_vector((width - 1) downto 0);
signal mem_storage : mem_type;
begin
P0 : process (rd, wr, input1, input2, clock)
begin
if (clock = '1' and clock'EVENT) then
if (rd = '1') then
output <= mem_storage(bits_to_int(input2));
end if;
if (wr = '1') then
mem_storage(bits_to_int(input2)) <= input1;
end if;
end if;
end process P0;
end behavior; | mit | ae755785a02204541723d27f43f64636 | 0.641998 | 2.675743 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/axi_uartlite_v2_0/6e58ba99/hdl/src/vhdl/uartlite_core.vhd | 1 | 22,195 | -------------------------------------------------------------------------------
-- uartlite_core - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2012] Xilinx, Inc. All rights reserved.*
-- -- ** *
-- -- ** This file contains confidential and proprietary information *
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
-- -- ** international copyright and other intellectual property *
-- -- ** laws. *
-- -- ** *
-- -- ** DISCLAIMER *
-- -- ** This disclaimer is not a license and does not grant any *
-- -- ** rights to the materials distributed herewith. Except as *
-- -- ** otherwise provided in a valid license issued to you by *
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- -- ** including negligence, or under any other theory of *
-- -- ** liability) for any loss or damage of any kind or nature *
-- -- ** related to, arising under or in connection with these *
-- -- ** materials, including for any direct, or any indirect, *
-- -- ** special, incidental, or consequential loss or damage *
-- -- ** (including loss of data, profits, goodwill, or any type of *
-- -- ** loss or damage suffered as a result of any action brought *
-- -- ** by a third party) even if such damage or loss was *
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
-- -- ** possibility of the same. *
-- -- ** *
-- -- ** CRITICAL APPLICATIONS *
-- -- ** Xilinx products are not designed or intended to be fail- *
-- -- ** safe, or for use in any application requiring fail-safe *
-- -- ** performance, such as life-support or safety devices or *
-- -- ** systems, Class III medical devices, nuclear facilities, *
-- -- ** applications related to the deployment of airbags, or any *
-- -- ** other applications that could lead to death, personal *
-- -- ** injury, or severe property or environmental damage *
-- -- ** (individually and collectively, "Critical *
-- -- ** Applications"). Customer assumes the sole risk and *
-- -- ** liability of any use of Xilinx products in Critical *
-- -- ** Applications, subject only to applicable laws and *
-- -- ** regulations governing limitations on product liability. *
-- -- ** *
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- -- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: uartlite_core.vhd
-- Version: v2.0
-- Description: UART Lite core for implementing UART logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_uartlite.
--
-- axi_uartlite.vhd
-- --axi_lite_ipif.vhd
-- --uartlite_core.vhd
-- --uartlite_tx.vhd
-- --uartlite_rx.vhd
-- --baudrate.vhd
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 07/22/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
-- ~~~~~~
-- 20/09/20 SK
-- - Updated the version as AXI Lite IPIF version is updated.
-- ^^^^^^
-- NLR 31/01/11
-- ^^^^^^
-- - 1.Updated the RX interrupt to a pulse CR#577542 is fixed.
-- 2.Updated the version from axi_uartlite_v1_01_a to axi_uartlite_v2_0.
-- ^^^^^^
-- NLR 10/01/12
-- ^^^^^^
-- - Fixed the CR#636523
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library axi_uartlite_v2_0;
-- baudrate refered from axi_uartlite_v2_0
use axi_uartlite_v2_0.baudrate;
-- uartlite_rx refered from axi_uartlite_v2_0
use axi_uartlite_v2_0.uartlite_rx;
-- uartlite_tx refered from axi_uartlite_v2_0
use axi_uartlite_v2_0.uartlite_tx;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- UART Lite generics
-- C_DATA_BITS -- The number of data bits in the serial frame
-- C_S_AXI_ACLK_FREQ_HZ -- System clock frequency driving UART lite
-- peripheral in Hz
-- C_BAUDRATE -- Baud rate of UART Lite in bits per second
-- C_USE_PARITY -- Determines whether parity is used or not
-- C_ODD_PARITY -- If parity is used determines whether parity
-- is even or odd
-- System generics
-- C_FAMILY -- Xilinx FPGA Family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
-- System Signals
-- Clk -- Clock signal
-- Rst -- Reset signal
-- Slave attachment interface
-- bus2ip_data -- bus2ip data signal
-- bus2ip_rdce -- bus2ip read CE
-- bus2ip_wrce -- bus2ip write CE
-- ip2bus_rdack -- ip2bus read acknowledgement
-- ip2bus_wrack -- ip2bus write acknowledgement
-- ip2bus_error -- ip2bus error
-- SIn_DBus -- ip2bus data
-- UART Lite interface
-- RX -- Receive Data
-- TX -- Transmit Data
-- Interrupt -- UART Interrupt
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity uartlite_core is
generic
(
C_FAMILY : string := "virtex7";
C_S_AXI_ACLK_FREQ_HZ: integer := 100_000_000;
C_BAUDRATE : integer := 9600;
C_DATA_BITS : integer range 5 to 8 := 8;
C_USE_PARITY : integer range 0 to 1 := 0;
C_ODD_PARITY : integer range 0 to 1 := 0
);
port
(
Clk : in std_logic;
Reset : in std_logic;
-- IPIF signals
bus2ip_data : in std_logic_vector(0 to 7);
bus2ip_rdce : in std_logic_vector(0 to 3);
bus2ip_wrce : in std_logic_vector(0 to 3);
bus2ip_cs : in std_logic;
ip2bus_rdack : out std_logic;
ip2bus_wrack : out std_logic;
ip2bus_error : out std_logic;
SIn_DBus : out std_logic_vector(0 to 7);
-- UART signals
RX : in std_logic;
TX : out std_logic;
Interrupt : out std_logic
);
end entity uartlite_core;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture RTL of uartlite_core is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
---------------------------------------------------------------------------
-- function declarations
---------------------------------------------------------------------------
function CALC_RATIO ( C_S_AXI_ACLK_FREQ_HZ : integer;
C_BAUDRATE : integer ) return Integer is
constant C_BAUDRATE_16_BY_2: integer := (16 * C_BAUDRATE) / 2;
constant REMAINDER : integer :=
C_S_AXI_ACLK_FREQ_HZ rem (16 * C_BAUDRATE);
constant RATIO : integer :=
C_S_AXI_ACLK_FREQ_HZ / (16 * C_BAUDRATE);
begin
if (C_BAUDRATE_16_BY_2 < REMAINDER) then
return (RATIO + 1);
else
return RATIO;
end if;
end function CALC_RATIO;
---------------------------------------------------------------------------
-- Constant declarations
---------------------------------------------------------------------------
constant RATIO : integer := CALC_RATIO( C_S_AXI_ACLK_FREQ_HZ, C_BAUDRATE);
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
-- Read Only
signal status_reg : std_logic_vector(0 to 7) := (others => '0');
-- bit 7 rx_Data_Present
-- bit 6 rx_Buffer_Full
-- bit 5 tx_Buffer_Empty
-- bit 4 tx_Buffer_Full
-- bit 3 enable_interrupts
-- bit 2 Overrun Error
-- bit 1 Frame Error
-- bit 0 Parity Error (If C_USE_PARITY is true, otherwise '0')
-- Write Only
-- Below mentioned bits belong to Control Register and are declared as
-- signals below
-- bit 0-2 Dont'Care
-- bit 3 enable_interrupts
-- bit 4-5 Dont'Care
-- bit 6 Reset_RX_FIFO
-- bit 7 Reset_TX_FIFO
signal en_16x_Baud : std_logic;
signal enable_interrupts : std_logic;
signal reset_RX_FIFO : std_logic;
signal rx_Data : std_logic_vector(0 to C_DATA_BITS-1);
signal rx_Data_Present : std_logic;
signal rx_Buffer_Full : std_logic;
signal rx_Frame_Error : std_logic;
signal rx_Overrun_Error : std_logic;
signal rx_Parity_Error : std_logic;
signal clr_Status : std_logic;
signal reset_TX_FIFO : std_logic;
signal tx_Buffer_Full : std_logic;
signal tx_Buffer_Empty : std_logic;
signal tx_Buffer_Empty_Pre : std_logic;
signal rx_Data_Present_Pre : std_logic;
begin -- architecture IMP
---------------------------------------------------------------------------
-- Generating the acknowledgement and error signals
---------------------------------------------------------------------------
ip2bus_rdack <= bus2ip_rdce(0) or bus2ip_rdce(2) or bus2ip_rdce(1)
or bus2ip_rdce(3);
ip2bus_wrack <= bus2ip_wrce(1) or bus2ip_wrce(3) or bus2ip_wrce(0)
or bus2ip_wrce(2);
ip2bus_error <= ((bus2ip_rdce(0) and not rx_Data_Present) or
(bus2ip_wrce(1) and tx_Buffer_Full) );
-------------------------------------------------------------------------
-- BAUD_RATE_I : Instansiating the baudrate module
-------------------------------------------------------------------------
BAUD_RATE_I : entity axi_uartlite_v2_0.baudrate
generic map
(
C_RATIO => RATIO
)
port map
(
Clk => Clk,
Reset => Reset,
EN_16x_Baud => en_16x_Baud
);
-------------------------------------------------------------------------
-- Status register handling
-------------------------------------------------------------------------
status_reg(7) <= rx_Data_Present;
status_reg(6) <= rx_Buffer_Full;
status_reg(5) <= tx_Buffer_Empty;
status_reg(4) <= tx_Buffer_Full;
status_reg(3) <= enable_interrupts;
-------------------------------------------------------------------------
-- CLEAR_STATUS_REG : Process to clear status register
-------------------------------------------------------------------------
CLEAR_STATUS_REG : process (Clk) is
begin -- process Ctrl_Reg_DFF
if Clk'event and Clk = '1' then
if Reset = '1' then
clr_Status <= '0';
else
clr_Status <= bus2ip_rdce(2);
end if;
end if;
end process CLEAR_STATUS_REG;
-------------------------------------------------------------------------
-- Process to register rx_Overrun_Error
-------------------------------------------------------------------------
RX_OVERRUN_ERROR_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if ((Reset = '1') or (clr_Status = '1')) then
status_reg(2) <= '0';
elsif (rx_Overrun_Error = '1') then
status_reg(2) <= '1';
end if;
end if;
end process RX_OVERRUN_ERROR_DFF;
-------------------------------------------------------------------------
-- Process to register rx_Frame_Error
-------------------------------------------------------------------------
RX_FRAME_ERROR_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Reset = '1') then
status_reg(1) <= '0';
else
if (clr_Status = '1') then
status_reg(1) <= '0';
elsif (rx_Frame_Error = '1') then
status_reg(1) <= '1';
end if;
end if;
end if;
end process RX_FRAME_ERROR_DFF;
-------------------------------------------------------------------------
-- If C_USE_PARITY = 1, register rx_Parity_Error
-------------------------------------------------------------------------
USING_PARITY : if (C_USE_PARITY = 1) generate
RX_PARITY_ERROR_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Reset = '1') then
status_reg(0) <= '0';
else
if (clr_Status = '1') then
status_reg(0) <= '0';
elsif (rx_Parity_Error = '1') then
status_reg(0) <= '1';
end if;
end if;
end if;
end process RX_PARITY_ERROR_DFF;
end generate USING_PARITY;
-------------------------------------------------------------------------
-- NO_PARITY : If C_USE_PARITY = 0, rx_Parity_Error bit is not present
-------------------------------------------------------------------------
NO_PARITY : if (C_USE_PARITY = 0) generate
status_reg(0) <= '0';
end generate NO_PARITY;
-------------------------------------------------------------------------
-- CTRL_REG_DFF : Control Register Handling
-------------------------------------------------------------------------
CTRL_REG_DFF : process (Clk) is
begin -- process Ctrl_Reg_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
reset_TX_FIFO <= '1';
reset_RX_FIFO <= '1';
enable_interrupts <= '0';
elsif (bus2ip_wrce(3) = '1') then
reset_RX_FIFO <= bus2ip_data(6);
reset_TX_FIFO <= bus2ip_data(7);
enable_interrupts <= bus2ip_data(3);
else
reset_TX_FIFO <= '0';
reset_RX_FIFO <= '0';
end if;
end if;
end process CTRL_REG_DFF;
-------------------------------------------------------------------------
-- Tx Fifo Interrupt handling
-------------------------------------------------------------------------
TX_BUFFER_EMPTY_DFF_I: Process (Clk) is
begin
if (Clk'event and Clk = '1') then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Buffer_Empty_Pre <= '0';
else
if (bus2ip_wrce(1) = '1') then
tx_Buffer_Empty_Pre <= '0';
else
tx_Buffer_Empty_Pre <= tx_Buffer_Empty;
end if;
end if;
end if;
end process TX_BUFFER_EMPTY_DFF_I;
-------------------------------------------------------------------------
-- Rx Fifo Interrupt handling
-------------------------------------------------------------------------
RX_BUFFER_DATA_DFF_I: Process (Clk) is
begin
if (Clk'event and Clk = '1') then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
rx_Data_Present_Pre <= '0';
else
if (bus2ip_rdce(0) = '1') then
rx_Data_Present_Pre <= '0';
else
rx_Data_Present_Pre <= rx_Data_Present;
end if;
end if;
end if;
end process RX_BUFFER_DATA_DFF_I;
-------------------------------------------------------------------------
-- Interrupt register handling
-------------------------------------------------------------------------
INTERRUPT_DFF: process (Clk) is
begin
if Clk'event and Clk = '1' then
if Reset = '1' then -- synchronous reset (active high)
Interrupt <= '0';
else
Interrupt <= enable_interrupts and
((rx_Data_Present and not rx_Data_Present_Pre) or
(tx_Buffer_Empty and not tx_Buffer_Empty_Pre));
end if;
end if;
end process INTERRUPT_DFF;
-------------------------------------------------------------------------
-- READ_MUX : Read bus interface handling
-------------------------------------------------------------------------
READ_MUX : process (status_reg, bus2ip_rdce(2), bus2ip_rdce(0), rx_Data) is
begin -- process Read_Mux
if (bus2ip_rdce(2) = '1') then
SIn_DBus <= status_reg;
elsif (bus2ip_rdce(0) = '1') then
SIn_DBus((8-C_DATA_BITS) to 7) <= rx_Data;
SIn_DBus(0 to (7-C_DATA_BITS)) <= (others => '0');
else
SIn_DBus <= (others => '0');
end if;
end process READ_MUX;
-------------------------------------------------------------------------
-- UARTLITE_RX_I : Instansiating the receive module
-------------------------------------------------------------------------
UARTLITE_RX_I : entity axi_uartlite_v2_0.uartlite_rx
generic map
(
C_FAMILY => C_FAMILY,
C_DATA_BITS => C_DATA_BITS,
C_USE_PARITY => C_USE_PARITY,
C_ODD_PARITY => C_ODD_PARITY
)
port map
(
Clk => Clk,
Reset => Reset,
EN_16x_Baud => en_16x_Baud,
RX => RX,
Read_RX_FIFO => bus2ip_rdce(0),
Reset_RX_FIFO => reset_RX_FIFO,
RX_Data => rx_Data,
RX_Data_Present => rx_Data_Present,
RX_Buffer_Full => rx_Buffer_Full,
RX_Frame_Error => rx_Frame_Error,
RX_Overrun_Error => rx_Overrun_Error,
RX_Parity_Error => rx_Parity_Error
);
-------------------------------------------------------------------------
-- UARTLITE_TX_I : Instansiating the transmit module
-------------------------------------------------------------------------
UARTLITE_TX_I : entity axi_uartlite_v2_0.uartlite_tx
generic map
(
C_FAMILY => C_FAMILY,
C_DATA_BITS => C_DATA_BITS,
C_USE_PARITY => C_USE_PARITY,
C_ODD_PARITY => C_ODD_PARITY
)
port map
(
Clk => Clk,
Reset => Reset,
EN_16x_Baud => en_16x_Baud,
TX => TX,
Write_TX_FIFO => bus2ip_wrce(1),
Reset_TX_FIFO => reset_TX_FIFO,
TX_Data => bus2ip_data(8-C_DATA_BITS to 7),
TX_Buffer_Full => tx_Buffer_Full,
TX_Buffer_Empty => tx_Buffer_Empty
);
end architecture RTL;
| apache-2.0 | 1a49f28203113756f6928fdc9481cfcc | 0.40383 | 4.789599 | false | false | false | false |
mbgh/aes128-hdl | src/vhdl/sboxCan.vhd | 1 | 7,148 | -------------------------------------------------------------------------------
--! @file sbox.vhd
--! @brief AES Canright S-box
--! @project VLSI Book - AES-128 Example
--! @author Michael Muehlberghuber ([email protected])
--! @company Integrated Systems Laboratory, ETH Zurich
--! @copyright Copyright (C) 2014 Integrated Systems Laboratory, ETH Zurich
--! @date 2014-06-05
--! @updated 2014-10-21
--! @platform Simulation: ModelSim; Synthesis: Synopsys
--! @standard VHDL'93/02
-------------------------------------------------------------------------------
-- Revision Control System Information:
-- File ID : $Id: sboxCan.vhd 30 2014-10-21 11:17:34Z u59323933 $
-- Revision : $Revision: 30 $
-- Local Date : $Date: 2014-10-21 13:17:34 +0200 (Tue, 21 Oct 2014) $
-- Modified By : $Author: u59323933 $
-------------------------------------------------------------------------------
-- Major Revisions:
-- Date Version Author Description
-- 2014-06-05 1.0 michmueh Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.aes128Pkg.all;
-------------------------------------------------------------------------------
--! @brief AES S-box implementation based on the approach by D. Canright [1].
--!
--! AES S-box implementation based on the approach by D. Canright, which uses
--! the subfields GF(2^2) and GF(2^4) in order to realize the field inversion
--! in GF(2^8). Thereby the area footprint of the resulting architecture should
--! be significantly smaller than the LUT-based approach using only a constant
--! array and shifting the effort of the actual implementation over to the
--! synthesizer.
--!
--! @reference{[1], D. Canright\, "A Very Compact S-Box for AES"\, CHES'05\,
--! http://dx.doi.org/10.1007/11545262_32}
-------------------------------------------------------------------------------
entity sbox is
port (
--! @brief Input to the S-box.
In_DI : in Byte;
--! @brief Substituted output of the S-box.
Out_DO : out Byte);
end entity sbox;
-------------------------------------------------------------------------------
--! @brief Behavioral architecture of the Canright AES S-box.
-------------------------------------------------------------------------------
architecture Canright of sbox is
-----------------------------------------------------------------------------
-- Type definitions
-----------------------------------------------------------------------------
-- Array of bytes for storing constants required during the base conversion.
type byteArrayType is array (0 to 7) of Byte;
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
constant A2X : byteArrayType := (x"98", x"F3", x"F2", x"48", x"09", x"81", x"A9", x"FF");
constant X2S : byteArrayType := (x"58", x"2D", x"9E", x"0B", x"DC", x"04", x"03", x"24");
-----------------------------------------------------------------------------
-- Functions
-----------------------------------------------------------------------------
-- Multiply in GF(2^2).
function mulG4 (
inpOne : std_logic_vector(1 downto 0);
inpTwo : std_logic_vector(1 downto 0))
return std_logic_vector is
variable a, b, c, d, e, p, q : std_logic;
begin
a := inpOne(1); b := inpOne(0);
c := inpTwo(1); d := inpTwo(0);
e := (a xor b) and (c xor d);
p := (a and c) xor e;
q := (b and d) xor e;
return p & q;
end function mulG4;
-- Scale by N in GF(2^2) using normal basis.
function sclNG4 (
input : std_logic_vector(1 downto 0))
return std_logic_vector is
begin
return (input(0) & (input(0) xor input(1)));
end function sclNG4;
-- Scale by N^2 in GF(2^2) using normal basis.
function sclN2G4 (
inp : std_logic_vector(1 downto 0))
return std_logic_vector is
begin
return ((inp(0) xor inp(1)) & inp(1));
end function sclN2G4;
-- Square in GF(2^2) using normal basis (identical to inverse).
function sqG4 (
inp : std_logic_vector(1 downto 0))
return std_logic_vector is
begin
return (inp(0) & inp(1));
end function sqG4;
-- Multiply in GF(2^4) using normal basis.
function mulG16 (
inpOne : std_logic_vector(3 downto 0);
inpTwo : std_logic_vector(3 downto 0))
return std_logic_vector is
variable a, b, c, d, e, p, q : std_logic_vector(1 downto 0);
begin
a := inpOne(3 downto 2); b := inpOne(1 downto 0);
c := inpTwo(3 downto 2); d := inpTwo(1 downto 0);
e := mulG4(a xor b, c xor d);
e := sclNG4(e);
p := (mulG4(a, c) xor e);
q := (mulG4(b, d) xor e);
return p & q;
end function mulG16;
-- Square and scale by \nu in GF(2^4)/GF(2^2) using normal basis.
function sqSclG16 (
inp : std_logic_vector(3 downto 0))
return std_logic_vector is
variable p, q : std_logic_vector(1 downto 0);
begin
p := sqG4(inp(3 downto 2) xor inp(1 downto 0));
q := sclN2G4(sqG4(inp(1 downto 0)));
return p & q;
end function sqSclG16;
-- Inverse in GF(2^4) using normal basis.
function invG16 (
inp : std_logic_vector(3 downto 0))
return std_logic_vector is
variable a,b,c,d,e,p,q : std_logic_vector(1 downto 0);
begin
a := inp(3 downto 2); b := inp(1 downto 0);
c := sclNG4(sqG4(a xor b));
d := mulG4(a, b);
e := sqG4(c xor d);
p := mulG4(e, b);
q := mulG4(e, a);
return p & q;
end function invG16;
-- Inversion in GF(2^8) using normal basis.
function invG256 (
inp : std_logic_vector(7 downto 0))
return std_logic_vector is
variable a,b,c,d,e,p,q : std_logic_vector(3 downto 0);
begin
a := inp(7 downto 4); b:= inp(3 downto 0);
c := sqSclG16(a xor b);
d := mulG16(a, b);
e := invG16(c xor d);
p := mulG16(e, b);
q := mulG16(e, a);
return p & q;
end function invG256;
-- Base conversion in GF(2^8).
function baseConv (
input : Byte;
baseConst : byteArrayType)
return Byte is
variable tmp : Byte;
begin
tmp := ZERO_BYTE;
for i in 0 to 7 loop
if input(i) = '1' then
tmp := tmp xor baseConst(7-i);
end if;
end loop; -- i
return tmp;
end function baseConv;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal NewBase_D : Byte; --! @brief Value after first base conversion.
signal Inverse_D : Byte; --! @brief Inverse of input in new base.
signal OldBase_D : Byte; --! @brief Value after second base conversion.
begin -- architecture Canright
-- Perform inverse calculation in different basis.
NewBase_D <= baseConv(In_DI, A2X);
Inverse_D <= invG256(NewBase_D);
OldBase_D <= baseConv(Inverse_D, X2S);
-- Output assignment.
Out_DO <= OldBase_D xor x"63";
end architecture Canright;
| gpl-2.0 | 4575f0b3273a0ab8c830c8f56dd5d624 | 0.507275 | 3.656266 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/axi_master_burst_v2_0/1af76933/hdl/src/vhdl/axi_master_burst_reset.vhd | 1 | 11,866 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- Filename: axi_master_burst_reset.vhd
--
-- Description:
--
-- This VHDL file implements the reset module for the AXI Master lite.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_master_burst_reset.vhd
--
-------------------------------------------------------------------------------
-- Author: DET
-- Revision: $Revision: 1.0 $
-- Date: $1/26/2011$
--
-- History:
--
-- DET 1/26/2011 Initial
-- ~~~~~~
-- - Adapted from AXI Master Lite reset module
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI MASTER BURST to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_master_burst_reset is
port (
-----------------------------------------------------------------------
-- Clock Input
-----------------------------------------------------------------------
axi_aclk : in std_logic ;
-----------------------------------------------------------------------
-- Reset Input (active low)
-----------------------------------------------------------------------
axi_aresetn : in std_logic ;
-----------------------------------------------------------------------
-- IPIC Reset Input
-----------------------------------------------------------------------
ip2bus_mst_reset : In std_logic ;
-----------------------------------------------------------------------
-- Command Status Module Reset Output
-----------------------------------------------------------------------
rst2cmd_reset_out : out std_logic ;
-----------------------------------------------------------------------
-- Read Write controller Module Reset Output
-----------------------------------------------------------------------
rst2rdwr_reset_out : out std_logic ;
-----------------------------------------------------------------------
-- LocalLink Modules Reset Output
-----------------------------------------------------------------------
rst2llink_reset_out : out std_logic
);
end entity axi_master_burst_reset;
architecture implementation of axi_master_burst_reset is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal sig_axi_por_reg1 : std_logic := '0';
signal sig_axi_por_reg2 : std_logic := '0';
signal sig_axi_por_reg3 : std_logic := '0';
signal sig_axi_por_reg4 : std_logic := '0';
signal sig_axi_por_reg5 : std_logic := '0';
signal sig_axi_por_reg6 : std_logic := '0';
signal sig_axi_por_reg7 : std_logic := '0';
signal sig_axi_por_reg8 : std_logic := '0';
signal sig_axi_por2rst : std_logic := '0';
signal sig_axi_por2rst_out : std_logic := '0';
signal sig_axi_reset : std_logic := '0';
signal sig_ipic_reset : std_logic := '0';
signal sig_combined_reset : std_logic := '0';
signal sig_cmd_reset_reg : std_logic := '0';
signal sig_rdwr_reset_reg : std_logic := '0';
signal sig_llink_reset_reg : std_logic := '0';
-------------------------------------------------------------------------------
-- Register duplication attribute assignments to control fanout
-- on reset signals
-------------------------------------------------------------------------------
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_cmd_reset_reg : signal is "TRUE";
Attribute KEEP of sig_rdwr_reset_reg : signal is "TRUE";
Attribute KEEP of sig_llink_reset_reg : signal is "TRUE";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_cmd_reset_reg : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_rdwr_reset_reg : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_llink_reset_reg : signal is "no";
begin --(architecture implementation)
-- Assign the output ports
rst2cmd_reset_out <= sig_cmd_reset_reg ;
rst2rdwr_reset_out <= sig_rdwr_reset_reg ;
rst2llink_reset_out <= sig_llink_reset_reg;
-- Generate an active high combined reset from the
-- axi reset input and the IPIC reset input
sig_axi_reset <= not(axi_aresetn);
sig_ipic_reset <= ip2bus_mst_reset;
sig_combined_reset <= sig_axi_reset or sig_ipic_reset;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_RST_REG
--
-- Process Description:
-- Implements the register for the command/status module
-- reset output.
--
-------------------------------------------------------------
IMP_CMD_RST_REG : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (sig_axi_por2rst_out = '1') then
sig_cmd_reset_reg <= '1';
else
sig_cmd_reset_reg <= sig_combined_reset;
end if;
end if;
end process IMP_CMD_RST_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RDWR_RST_REG
--
-- Process Description:
-- Implements the register for the read/write controller
-- module reset output.
--
-------------------------------------------------------------
IMP_RDWR_RST_REG : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (sig_axi_por2rst_out = '1') then
sig_rdwr_reset_reg <= '1';
else
sig_rdwr_reset_reg <= sig_combined_reset;
end if;
end if;
end process IMP_RDWR_RST_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LLINK_RST_REG
--
-- Process Description:
-- Implements the register for the LocalLink Modules
-- reset output.
--
-------------------------------------------------------------
IMP_LLINK_RST_REG : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (sig_axi_por2rst_out = '1') then
sig_llink_reset_reg <= '1';
else
sig_llink_reset_reg <= sig_combined_reset;
end if;
end if;
end process IMP_LLINK_RST_REG;
---------------------------------------------------------------
-- Start Power On Reset (POR) Logic
---------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: AXI_POR_REG
--
-- Process Description:
-- This process generates an 8-clock wide pulse that
-- only occurs immediately after FPGA initialization. This
-- pulse is used to initialize reset logic synchronous to
-- the Main axi_aclk Clock until the Bus Reset occurs.
--
-------------------------------------------------------------
AXI_POR_REG : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
sig_axi_por_reg1 <= '1';
sig_axi_por_reg2 <= sig_axi_por_reg1;
sig_axi_por_reg3 <= sig_axi_por_reg2;
sig_axi_por_reg4 <= sig_axi_por_reg3;
sig_axi_por_reg5 <= sig_axi_por_reg4;
sig_axi_por_reg6 <= sig_axi_por_reg5;
sig_axi_por_reg7 <= sig_axi_por_reg6;
sig_axi_por_reg8 <= sig_axi_por_reg7;
sig_axi_por2rst_out <= sig_axi_por2rst ;
end if;
end process AXI_POR_REG;
sig_axi_por2rst <= not(sig_axi_por_reg1 and
sig_axi_por_reg2 and
sig_axi_por_reg3 and
sig_axi_por_reg4 and
sig_axi_por_reg5 and
sig_axi_por_reg6 and
sig_axi_por_reg7 and
sig_axi_por_reg8 );
---------------------------------------------------------------
-- End of Power On Reset (POR) Logic
---------------------------------------------------------------
end implementation;
| apache-2.0 | 33eaefec2bd935c3abc0168ab2e471df | 0.46865 | 4.811841 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/dcache.vhd | 1 | 155,661 | `protect begin_protected
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 113488)
`protect data_block
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`protect end_protected
| apache-2.0 | f5192d622be98cb0a5682b93c4626224 | 0.954324 | 1.806315 | false | false | false | false |
sils1297/HWPrak14 | task_3/task_3.srcs/sources_1/new/i2c_master_bit_ctrl.vhd | 2 | 24,550 | ---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 I2C Master Core; bit-controller ----
---- ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2000 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- CVS Log
--
-- $Id: i2c_master_bit_ctrl.vhd,v 1.17 2009-02-04 20:17:34 rherveille Exp $
--
-- $Date: 2009-02-04 20:17:34 $
-- $Revision: 1.17 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: not supported by cvs2svn $
-- Revision 1.16 2009/01/20 20:40:36 rherveille
-- Fixed type iscl_oen instead of scl_oen
--
-- Revision 1.15 2009/01/20 10:34:51 rherveille
-- Added SCL clock synchronization logic
-- Fixed slave_wait signal generation
--
-- Revision 1.14 2006/10/11 12:10:13 rherveille
-- Added missing semicolons ';' on endif
--
-- Revision 1.13 2006/10/06 10:48:24 rherveille
-- fixed short scl high pulse after clock stretch
--
-- Revision 1.12 2004/05/07 11:53:31 rherveille
-- Fixed previous fix :) Made a variable vs signal mistake.
--
-- Revision 1.11 2004/05/07 11:04:00 rherveille
-- Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.
--
-- Revision 1.10 2004/02/27 07:49:43 rherveille
-- Fixed a bug in the arbitration-lost signal generation. VHDL version only.
--
-- Revision 1.9 2003/08/12 14:48:37 rherveille
-- Forgot an 'end if' :-/
--
-- Revision 1.8 2003/08/09 07:01:13 rherveille
-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
-- Fixed a potential bug in the byte controller's host-acknowledge generation.
--
-- Revision 1.7 2003/02/05 00:06:02 rherveille
-- Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.
--
-- Revision 1.6 2003/02/01 02:03:06 rherveille
-- Fixed a few 'arbitration lost' bugs. VHDL version only.
--
-- Revision 1.5 2002/12/26 16:05:47 rherveille
-- Core is now a Multimaster I2C controller.
--
-- Revision 1.4 2002/11/30 22:24:37 rherveille
-- Cleaned up code
--
-- Revision 1.3 2002/10/30 18:09:53 rherveille
-- Fixed some reported minor start/stop generation timing issuess.
--
-- Revision 1.2 2002/06/15 07:37:04 rherveille
-- Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
--
-- Revision 1.1 2001/11/05 12:02:33 rherveille
-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
-- Code updated, is now up-to-date to doc. rev.0.4.
-- Added headers.
--
--
-------------------------------------
-- Bit controller section
------------------------------------
--
-- Translate simple commands into SCL/SDA transitions
-- Each command has 5 states, A/B/C/D/idle
--
-- start: SCL ~~~~~~~~~~~~~~\____
-- SDA XX/~~~~~~~\______
-- x | A | B | C | D | i
--
-- repstart SCL ______/~~~~~~~\___
-- SDA __/~~~~~~~\______
-- x | A | B | C | D | i
--
-- stop SCL _______/~~~~~~~~~~~
-- SDA ==\___________/~~~~~
-- x | A | B | C | D | i
--
--- write SCL ______/~~~~~~~\____
-- SDA XXX===============XX
-- x | A | B | C | D | i
--
--- read SCL ______/~~~~~~~\____
-- SDA XXXXXXX=XXXXXXXXXXX
-- x | A | B | C | D | i
--
-- Timing: Normal mode Fast mode
-----------------------------------------------------------------
-- Fscl 100KHz 400KHz
-- Th_scl 4.0us 0.6us High period of SCL
-- Tl_scl 4.7us 1.3us Low period of SCL
-- Tsu:sta 4.7us 0.6us setup time for a repeated start condition
-- Tsu:sto 4.0us 0.6us setup time for a stop conditon
-- Tbuf 4.7us 1.3us Bus free time between a stop and start condition
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity i2c_master_bit_ctrl is
port (
clk : in std_logic;
rst : in std_logic;
nReset : in std_logic;
ena : in std_logic; -- core enable signal
clk_cnt : in unsigned(15 downto 0); -- clock prescale value
cmd : in std_logic_vector(3 downto 0);
cmd_ack : out std_logic; -- command completed
busy : out std_logic; -- i2c bus busy
al : out std_logic; -- arbitration lost
din : in std_logic;
dout : out std_logic;
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end entity i2c_master_bit_ctrl;
architecture structural of i2c_master_bit_ctrl is
constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";
constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";
constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";
constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100";
constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000";
type states is (idle, start_a, start_b, start_c, start_d, start_e,
stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);
signal c_state : states;
signal iscl_oen, isda_oen : std_logic; -- internal I2C lines
signal sda_chk : std_logic; -- check SDA status (multi-master arbitration)
signal dscl_oen : std_logic; -- delayed scl_oen signals
signal sSCL, sSDA : std_logic; -- synchronized SCL and SDA inputs
signal dSCL, dSDA : std_logic; -- delayed versions ofsSCL and sSDA
signal clk_en : std_logic; -- statemachine clock enable
signal scl_sync, slave_wait : std_logic; -- clock generation signals
signal ial : std_logic; -- internal arbitration lost signal
signal cnt : unsigned(15 downto 0); -- clock divider counter (synthesis)
begin
-- whenever the slave is not ready it can delay the cycle by pulling SCL low
-- delay scl_oen
process (clk, nReset)
begin
if (nReset = '0') then
dscl_oen <= '0';
elsif (clk'event and clk = '1') then
dscl_oen <= iscl_oen;
end if;
end process;
-- slave_wait is asserted when master wants to drive SCL high, but the slave pulls it low
-- slave_wait remains asserted until the slave releases SCL
process (clk, nReset)
begin
if (nReset = '0') then
slave_wait <= '0';
elsif (clk'event and clk = '1') then
slave_wait <= (iscl_oen and not dscl_oen and not sSCL) or (slave_wait and not sSCL);
end if;
end process;
-- master drives SCL high, but another master pulls it low
-- master start counting down its low cycle now (clock synchronization)
scl_sync <= dSCL and not sSCL and iscl_oen;
-- generate clk enable signal
gen_clken: process(clk, nReset)
begin
if (nReset = '0') then
cnt <= (others => '0');
clk_en <= '1';
elsif (clk'event and clk = '1') then
if ((rst = '1') or (cnt = 0) or (ena = '0') or (scl_sync = '1')) then
cnt <= clk_cnt;
clk_en <= '1';
elsif (slave_wait = '1') then
cnt <= cnt;
clk_en <= '0';
else
cnt <= cnt -1;
clk_en <= '0';
end if;
end if;
end process gen_clken;
-- generate bus status controller
bus_status_ctrl: block
signal cSCL, cSDA : std_logic_vector( 1 downto 0); -- capture SDA and SCL
signal fSCL, fSDA : std_logic_vector( 2 downto 0); -- filter inputs for SCL and SDA
signal filter_cnt : unsigned(13 downto 0); -- clock divider for filter
signal sta_condition : std_logic; -- start detected
signal sto_condition : std_logic; -- stop detected
signal cmd_stop : std_logic; -- STOP command
signal ibusy : std_logic; -- internal busy signal
begin
-- capture SCL and SDA
capture_scl_sda: process(clk, nReset)
begin
if (nReset = '0') then
cSCL <= "00";
cSDA <= "00";
elsif (clk'event and clk = '1') then
if (rst = '1') then
cSCL <= "00";
cSDA <= "00";
else
cSCL <= (cSCL(0) & scl_i);
cSDA <= (cSDA(0) & sda_i);
end if;
end if;
end process capture_scl_sda;
-- filter SCL and SDA; (attempt to) remove glitches
filter_divider: process(clk, nReset)
begin
if (nReset = '0') then
filter_cnt <= (others => '0');
elsif (clk'event and clk = '1') then
if ( (rst = '1') or (ena = '0') ) then
filter_cnt <= (others => '0');
elsif (filter_cnt = 0) then
filter_cnt <= clk_cnt(15 downto 2);
else
filter_cnt <= filter_cnt -1;
end if;
end if;
end process filter_divider;
filter_scl_sda: process(clk, nReset)
begin
if (nReset = '0') then
fSCL <= (others => '1');
fSDA <= (others => '1');
elsif (clk'event and clk = '1') then
if (rst = '1') then
fSCL <= (others => '1');
fSDA <= (others => '1');
elsif (filter_cnt = 0) then
fSCL <= (fSCL(1 downto 0) & cSCL(1));
fSDA <= (fSDA(1 downto 0) & cSDA(1));
end if;
end if;
end process filter_scl_sda;
-- generate filtered SCL and SDA signals
scl_sda: process(clk, nReset)
begin
if (nReset = '0') then
sSCL <= '1';
sSDA <= '1';
dSCL <= '1';
dSDA <= '1';
elsif (clk'event and clk = '1') then
if (rst = '1') then
sSCL <= '1';
sSDA <= '1';
dSCL <= '1';
dSDA <= '1';
else
sSCL <= (fSCL(2) and fSCL(1)) or
(fSCL(2) and fSCL(0)) or
(fSCL(1) and fSCL(0));
sSDA <= (fSDA(2) and fSDA(1)) or
(fSDA(2) and fSDA(0)) or
(fSDA(1) and fSDA(0));
dSCL <= sSCL;
dSDA <= sSDA;
end if;
end if;
end process scl_sda;
-- detect start condition => detect falling edge on SDA while SCL is high
-- detect stop condition => detect rising edge on SDA while SCL is high
detect_sta_sto: process(clk, nReset)
begin
if (nReset = '0') then
sta_condition <= '0';
sto_condition <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
sta_condition <= '0';
sto_condition <= '0';
else
sta_condition <= (not sSDA and dSDA) and sSCL;
sto_condition <= (sSDA and not dSDA) and sSCL;
end if;
end if;
end process detect_sta_sto;
-- generate i2c-bus busy signal
gen_busy: process(clk, nReset)
begin
if (nReset = '0') then
ibusy <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
ibusy <= '0';
else
ibusy <= (sta_condition or ibusy) and not sto_condition;
end if;
end if;
end process gen_busy;
busy <= ibusy;
-- generate arbitration lost signal
-- aribitration lost when:
-- 1) master drives SDA high, but the i2c bus is low
-- 2) stop detected while not requested (detect during 'idle' state)
gen_al: process(clk, nReset)
begin
if (nReset = '0') then
cmd_stop <= '0';
ial <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
cmd_stop <= '0';
ial <= '0';
else
if (clk_en = '1') then
if (cmd = I2C_CMD_STOP) then
cmd_stop <= '1';
else
cmd_stop <= '0';
end if;
end if;
if (c_state = idle) then
ial <= (sda_chk and not sSDA and isda_oen) or (sto_condition and not cmd_stop);
else
ial <= (sda_chk and not sSDA and isda_oen);
end if;
end if;
end if;
end process gen_al;
al <= ial;
-- generate dout signal, store dout on rising edge of SCL
gen_dout: process(clk, nReset)
begin
if (nReset = '0') then
dout <= '0';
elsif (clk'event and clk = '1') then
if (sSCL = '1' and dSCL = '0') then
dout <= sSDA;
end if;
end if;
end process gen_dout;
end block bus_status_ctrl;
-- generate statemachine
nxt_state_decoder : process (clk, nReset)
begin
if (nReset = '0') then
c_state <= idle;
cmd_ack <= '0';
iscl_oen <= '1';
isda_oen <= '1';
sda_chk <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1' or ial = '1') then
c_state <= idle;
cmd_ack <= '0';
iscl_oen <= '1';
isda_oen <= '1';
sda_chk <= '0';
else
cmd_ack <= '0'; -- default no acknowledge
if (clk_en = '1') then
case (c_state) is
-- idle
when idle =>
case cmd is
when I2C_CMD_START => c_state <= start_a;
when I2C_CMD_STOP => c_state <= stop_a;
when I2C_CMD_WRITE => c_state <= wr_a;
when I2C_CMD_READ => c_state <= rd_a;
when others => c_state <= idle; -- NOP command
end case;
iscl_oen <= iscl_oen; -- keep SCL in same state
isda_oen <= isda_oen; -- keep SDA in same state
sda_chk <= '0'; -- don't check SDA
-- start
when start_a =>
c_state <= start_b;
iscl_oen <= iscl_oen; -- keep SCL in same state (for repeated start)
isda_oen <= '1'; -- set SDA high
sda_chk <= '0'; -- don't check SDA
when start_b =>
c_state <= start_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- keep SDA high
sda_chk <= '0'; -- don't check SDA
when start_c =>
c_state <= start_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- set SDA low
sda_chk <= '0'; -- don't check SDA
when start_d =>
c_state <= start_e;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when start_e =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
-- stop
when stop_a =>
c_state <= stop_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= '0'; -- set SDA low
sda_chk <= '0'; -- don't check SDA
when stop_b =>
c_state <= stop_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when stop_c =>
c_state <= stop_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when stop_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '1'; -- set SDA high
sda_chk <= '0'; -- don't check SDA
-- read
when rd_a =>
c_state <= rd_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_b =>
c_state <= rd_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_c =>
c_state <= rd_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
-- write
when wr_a =>
c_state <= wr_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= din; -- set SDA
sda_chk <= '0'; -- don't check SDA (SCL low)
when wr_b =>
c_state <= wr_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= din; -- keep SDA
sda_chk <= '0'; -- don't check SDA yet
-- Allow some more time for SDA and SCL to settle
when wr_c =>
c_state <= wr_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= din; -- keep SDA
sda_chk <= '1'; -- check SDA
when wr_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= din; -- keep SDA
sda_chk <= '0'; -- don't check SDA (SCL low)
when others =>
end case;
end if;
end if;
end if;
end process nxt_state_decoder;
-- assign outputs
scl_o <= '0';
scl_oen <= iscl_oen;
sda_o <= '0';
sda_oen <= isda_oen;
end architecture structural; | agpl-3.0 | 4bbeaf79769fc62e6a80b5105965df4f | 0.398411 | 4.523678 | false | false | false | false |
freecores/twofish | vhdl/twofish_cbc_decryption_monte_carlo_testbench_256bits.vhd | 1 | 11,593 | -- Twofish_cbc_decryption_monte_carlo_testbench_256bits.vhd
-- Copyright (C) 2006 Spyros Ninos
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this library; see the file COPYING. If not, write to:
--
--
-- description : this file is the testbench for the Decryption Monte Carlo KAT of the twofish cipher with 256 bit key
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_arith.all;
use std.textio.all;
entity cbc_decryption_monte_carlo_testbench256 is
end cbc_decryption_monte_carlo_testbench256;
architecture cbc_decryption256_monte_carlo_testbench_arch of cbc_decryption_monte_carlo_testbench256 is
component reg128
port (
in_reg128 : in std_logic_vector(127 downto 0);
out_reg128 : out std_logic_vector(127 downto 0);
enable_reg128, reset_reg128, clk_reg128 : in std_logic
);
end component;
component twofish_keysched256
port (
odd_in_tk256,
even_in_tk256 : in std_logic_vector(7 downto 0);
in_key_tk256 : in std_logic_vector(255 downto 0);
out_key_up_tk256,
out_key_down_tk256 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_whit_keysched256
port (
in_key_twk256 : in std_logic_vector(255 downto 0);
out_K0_twk256,
out_K1_twk256,
out_K2_twk256,
out_K3_twk256,
out_K4_twk256,
out_K5_twk256,
out_K6_twk256,
out_K7_twk256 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_decryption_round256
port (
in1_tdr256,
in2_tdr256,
in3_tdr256,
in4_tdr256,
in_Sfirst_tdr256,
in_Ssecond_tdr256,
in_Sthird_tdr256,
in_Sfourth_tdr256,
in_key_up_tdr256,
in_key_down_tdr256 : in std_logic_vector(31 downto 0);
out1_tdr256,
out2_tdr256,
out3_tdr256,
out4_tdr256 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_data_input
port (
in_tdi : in std_logic_vector(127 downto 0);
out_tdi : out std_logic_vector(127 downto 0)
);
end component;
component twofish_data_output
port (
in_tdo : in std_logic_vector(127 downto 0);
out_tdo : out std_logic_vector(127 downto 0)
);
end component;
component demux128
port ( in_demux128 : in std_logic_vector(127 downto 0);
out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0);
selection_demux128 : in std_logic
);
end component;
component mux128
port ( in1_mux128, in2_mux128 : in std_logic_vector(127 downto 0);
selection_mux128 : in std_logic;
out_mux128 : out std_logic_vector(127 downto 0)
);
end component;
component twofish_S256
port (
in_key_ts256 : in std_logic_vector(255 downto 0);
out_Sfirst_ts256,
out_Ssecond_ts256,
out_Sthird_ts256,
out_Sfourth_ts256 : out std_logic_vector(31 downto 0)
);
end component;
FILE input_file : text is in "twofish_cbc_decryption_monte_carlo_testvalues_256bits.txt";
FILE output_file : text is out "twofish_cbc_decryption_monte_carlo_256bits_results.txt";
-- we create the functions that transform a number to text
-- transforming a signle digit to a character
function digit_to_char(number : integer range 0 to 9) return character is
begin
case number is
when 0 => return '0';
when 1 => return '1';
when 2 => return '2';
when 3 => return '3';
when 4 => return '4';
when 5 => return '5';
when 6 => return '6';
when 7 => return '7';
when 8 => return '8';
when 9 => return '9';
end case;
end;
-- transforming multi-digit number to text
function to_text(int_number : integer range 0 to 9999) return string is
variable our_text : string (1 to 4) := (others => ' ');
variable thousands,
hundreds,
tens,
ones : integer range 0 to 9;
begin
ones := int_number mod 10;
tens := ((int_number mod 100) - ones) / 10;
hundreds := ((int_number mod 1000) - (int_number mod 100)) / 100;
thousands := (int_number - (int_number mod 1000)) / 1000;
our_text(1) := digit_to_char(thousands);
our_text(2) := digit_to_char(hundreds);
our_text(3) := digit_to_char(tens);
our_text(4) := digit_to_char(ones);
return our_text;
end;
signal odd_number,
even_number : std_logic_vector(7 downto 0);
signal input_data,
output_data,
to_encr_reg128,
from_tdi_to_xors,
to_output_whit_xors,
from_xors_to_tdo,
to_mux, to_demux,
from_input_whit_xors,
to_round,
to_input_mux : std_logic_vector(127 downto 0) ;
signal twofish_key : std_logic_vector(255 downto 0);
signal key_up,
key_down,
Sfirst,
Ssecond,
Sthird,
Sfourth,
from_xor0,
from_xor1,
from_xor2,
from_xor3,
K0,K1,K2,K3,
K4,K5,K6,K7 : std_logic_vector(31 downto 0);
signal clk : std_logic := '0';
signal mux_selection : std_logic := '0';
signal demux_selection: std_logic := '0';
signal enable_encr_reg : std_logic := '0';
signal reset : std_logic := '0';
signal enable_round_reg : std_logic := '0';
-- begin the testbench arch description
begin
-- getting data to encrypt
data_input: twofish_data_input
port map (
in_tdi => input_data,
out_tdi => from_tdi_to_xors
);
-- producing whitening keys K0..7
the_whitening_step: twofish_whit_keysched256
port map (
in_key_twk256 => twofish_key,
out_K0_twk256 => K0,
out_K1_twk256 => K1,
out_K2_twk256 => K2,
out_K3_twk256 => K3,
out_K4_twk256 => K4,
out_K5_twk256 => K5,
out_K6_twk256 => K6,
out_K7_twk256 => K7
);
-- performing the input whitening XORs
from_xor0 <= K4 XOR from_tdi_to_xors(127 downto 96);
from_xor1 <= K5 XOR from_tdi_to_xors(95 downto 64);
from_xor2 <= K6 XOR from_tdi_to_xors(63 downto 32);
from_xor3 <= K7 XOR from_tdi_to_xors(31 downto 0);
from_input_whit_xors <= from_xor0 & from_xor1 & from_xor2 & from_xor3;
round_reg: reg128
port map ( in_reg128 => from_input_whit_xors,
out_reg128 => to_input_mux,
enable_reg128 => enable_round_reg,
reset_reg128 => reset,
clk_reg128 => clk );
input_mux: mux128
port map ( in1_mux128 => to_input_mux,
in2_mux128 => to_mux,
out_mux128 => to_round,
selection_mux128 => mux_selection
);
-- creating a round
the_keysched_of_the_round: twofish_keysched256
port map (
odd_in_tk256 => odd_number,
even_in_tk256 => even_number,
in_key_tk256 => twofish_key,
out_key_up_tk256 => key_up,
out_key_down_tk256 => key_down
);
producing_the_Skeys: twofish_S256
port map (
in_key_ts256 => twofish_key,
out_Sfirst_ts256 => Sfirst,
out_Ssecond_ts256 => Ssecond,
out_Sthird_ts256 => Sthird,
out_Sfourth_ts256 => Sfourth
);
the_decryption_circuit: twofish_decryption_round256
port map (
in1_tdr256 => to_round(127 downto 96),
in2_tdr256 => to_round(95 downto 64),
in3_tdr256 => to_round(63 downto 32),
in4_tdr256 => to_round(31 downto 0),
in_Sfirst_tdr256 => Sfirst,
in_Ssecond_tdr256 => Ssecond,
in_Sthird_tdr256 => Sthird,
in_Sfourth_tdr256 => Sfourth,
in_key_up_tdr256 => key_up,
in_key_down_tdr256 => key_down,
out1_tdr256 => to_encr_reg128(127 downto 96),
out2_tdr256 => to_encr_reg128(95 downto 64),
out3_tdr256 => to_encr_reg128(63 downto 32),
out4_tdr256 => to_encr_reg128(31 downto 0)
);
encr_reg: reg128
port map ( in_reg128 => to_encr_reg128,
out_reg128 => to_demux,
enable_reg128 => enable_encr_reg,
reset_reg128 => reset,
clk_reg128 => clk );
output_demux: demux128
port map ( in_demux128 => to_demux,
out1_demux128 => to_output_whit_xors,
out2_demux128 => to_mux,
selection_demux128 => demux_selection );
-- don't forget the last swap !!!
from_xors_to_tdo(127 downto 96) <= K0 XOR to_output_whit_xors(63 downto 32);
from_xors_to_tdo(95 downto 64) <= K1 XOR to_output_whit_xors(31 downto 0);
from_xors_to_tdo(63 downto 32) <= K2 XOR to_output_whit_xors(127 downto 96);
from_xors_to_tdo(31 downto 0) <= K3 XOR to_output_whit_xors(95 downto 64);
taking_the_output: twofish_data_output
port map (
in_tdo => from_xors_to_tdo,
out_tdo => output_data
);
-- we create the clock
clk <= not clk after 50 ns; -- period 100 ns
cbc_dmc_proc: process
variable key_f, -- key input from file
pt_f, -- plaintext from file
ct_f,
iv_f : line; -- ciphertext from file
variable key_v : std_logic_vector(255 downto 0); -- key vector input
variable pt_v , -- plaintext vector
ct_v,
iv_v : std_logic_vector(127 downto 0); -- ciphertext vector
variable counter_10000 : integer range 0 to 9999 := 0; -- counter for the 10.000 repeats in the 400 next ones
variable counter_400 : integer range 0 to 399 := 0; -- counter for the 400 repeats
variable round : integer range 0 to 16 := 0; -- holds the rounds
variable PT, CT, CV, CTj_1 : std_logic_vector(127 downto 0) := (others => '0');
begin
while not endfile(input_file) loop
readline(input_file, key_f);
readline(input_file, iv_f);
readline(input_file,ct_f);
readline(input_file, pt_f);
hread(key_f,key_v);
hread(iv_f, iv_v);
hread(ct_f,ct_v);
hread(pt_f,pt_v);
twofish_key <= key_v;
CV := iv_v;
CT := ct_v;
for counter_10000 in 0 to 9999 loop
input_data <= CT;
wait for 25 ns;
reset <= '1';
wait for 50 ns;
reset <= '0';
mux_selection <= '0';
demux_selection <= '1';
enable_encr_reg <= '0';
enable_round_reg <= '0';
wait for 50 ns;
enable_round_reg <= '1';
wait for 50 ns;
enable_round_reg <= '0';
-- the first round
even_number <= "00100110"; -- 38
odd_number <= "00100111"; -- 39
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
demux_selection <= '1';
mux_selection <= '1';
-- the rest 15 rounds
for round in 1 to 15 loop
even_number <= conv_std_logic_vector((((15-round)*2)+8), 8);
odd_number <= conv_std_logic_vector((((15-round)*2)+9), 8);
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
end loop;
-- taking final results
demux_selection <= '0';
wait for 25 ns;
PT := output_data XOR CV;
CV := CT;
CT := PT;
assert false report "I=" & to_text(counter_400) & " R=" & to_text(counter_10000) severity note;
end loop; -- counter_10000
hwrite(key_f, key_v);
hwrite(iv_f, iv_v);
hwrite(ct_f, ct_v);
hwrite(pt_f, PT);
writeline(output_file,key_f);
writeline(output_file, iv_f);
writeline(output_file,ct_f);
writeline(output_file,pt_f);
assert (pt_v = PT) report "file entry and decryption result DO NOT match!!! :( " severity failure;
assert (pt_v /= PT) report "Decryption I=" & to_text(counter_400) &" OK" severity note;
counter_400 := counter_400 + 1;
end loop;
assert false report "***** CBC Decryption Monte Carlo Test with 256 bits key size ended succesfully! :) *****" severity failure;
end process cbc_dmc_proc;
end cbc_decryption256_monte_carlo_testbench_arch;
| gpl-2.0 | cda6e191815607a24e88e780b851c61c | 0.645476 | 2.693541 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/carry_or.vhd | 1 | 9,893 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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N8VsHQ9K8g==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5584)
`protect data_block
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`protect end_protected
| apache-2.0 | da087a3ba98927d9e2beb795432774cb | 0.924492 | 1.92396 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/prefetch_buffer_gti.vhd | 1 | 34,470 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 23776)
`protect data_block
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`protect end_protected
| apache-2.0 | a4eb280d8947a50eaaf68e22044173fb | 0.945692 | 1.829132 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/builtin/builtin_top.vhd | 5 | 75,016 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 53792)
`protect data_block
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`protect end_protected
| apache-2.0 | e5488a7491ae297dabd6757bdab34b8d | 0.95197 | 1.818129 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/7-FIR1/asap-alap-random/fir1_alap.vhd | 1 | 3,408 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-26.15:19:36)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY fir1_alap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16, input17, input18, input19, input20, input21, input22: IN unsigned(0 TO 3);
output1: OUT unsigned(0 TO 4));
END fir1_alap_entity;
ARCHITECTURE fir1_alap_description OF fir1_alap_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 and input1;
register2 := input2 and input2;
register3 := input3 and input3;
register4 := input4 and input4;
register5 := input5 and input5;
register6 := input6 and input6;
WHEN "00000010" =>
register1 := register2 * register1;
register2 := register4 * register3;
register3 := register6 * register5;
WHEN "00000011" =>
register1 := register2 + register1;
register2 := input7 and input7;
register4 := input8 and input8;
register5 := input9 and input9;
register6 := input10 and input10;
register7 := input11 and input11;
register8 := input12 and input12;
WHEN "00000100" =>
register1 := register1 + register3;
register2 := register4 * register2;
register3 := register6 * register5;
register4 := register8 * register7;
register5 := input13 and input13;
register6 := input14 and input14;
WHEN "00000101" =>
register1 := register2 + register1;
register2 := register4 + register3;
register3 := input15 and input15;
register4 := input16 and input16;
register7 := input17 and input17;
register8 := input18 and input18;
register5 := register6 * register5;
WHEN "00000110" =>
register1 := register2 + register1;
register2 := register4 * register3;
register3 := register8 * register7;
register4 := input19 and input19;
register6 := input20 and input20;
WHEN "00000111" =>
register1 := register1 + register5;
register2 := register3 + register2;
register3 := register6 * register4;
WHEN "00001000" =>
register1 := register2 + register1;
register2 := input21 and input21;
register4 := input22 and input22;
WHEN "00001001" =>
register1 := register1 + register3;
register2 := register4 * register2;
WHEN "00001010" =>
register1 := register2 + register1;
WHEN "00001011" =>
output1 <= register1 and register1;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END fir1_alap_description; | gpl-3.0 | 59e330a4c6a963d09b21d047bbfe6e8e | 0.681338 | 3.236467 | false | false | false | false |
rhexsel/xinu-cMIPS | vhdl/packageMemory_simu.vhd | 1 | 17,588 | -- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
package p_MEMORY is
-- To simplify (and accelerate) the RAM address decoding,
-- the BASE of the RAM addresses MUST be allocated at an
-- address which is at a different power of two than the ROM base.
-- Otherwise, the base must be subtracted from the address on every
-- reference, which means having an adder in the critical path.
-- Not good at all.
-- The address ranges for ROM, RAM and I/O must be distinct in the
-- uppermost 16 bits of the address (bits 31..16).
constant HI_SEL_BITS : integer := 31;
constant LO_SEL_BITS : integer := 16;
-- x_IO_ADDR_RANGE can have only ONE bit set, thus being a power of 2.
-- ACHTUNG: changing that definition may break some of the test programs.
-- begin DO NOT change these names as several scripts depend on them --
-- you may change the values, not names neither formatting --
constant x_INST_BASE_ADDR : reg32 := x"00000000";
constant x_INST_MEM_SZ : reg32 := x"00020000";
constant x_DATA_BASE_ADDR : reg32 := x"00080000";
constant x_DATA_MEM_SZ : reg32 := x"00080000";
constant x_IO_BASE_ADDR : reg32 := x"3c000000";
constant x_IO_MEM_SZ : reg32 := x"00002000";
constant x_IO_ADDR_RANGE : reg32 := x"00000020";
constant x_SDRAM_BASE_ADDR : reg32 := x"04000000";
constant x_SDRAM_MEM_SZ : reg32 := x"02000000";
constant x_EXCEPTION_0000 : reg32 := x"00000130"; -- TLBrefill
constant x_EXCEPTION_0100 : reg32 := x"00000200"; -- CacheError
constant x_EXCEPTION_0180 : reg32 := x"00000280"; -- generalExcpHandler
constant x_EXCEPTION_0200 : reg32 := x"00000400"; -- separInterrHandler
constant x_EXCEPTION_BFC0 : reg32 := x"00000680"; -- NMI, soft-reset
constant x_ENTRY_POINT : reg32 := x"00000700"; -- main()
-- end DO NOT change these names --
constant INST_BASE_ADDR : integer := to_integer(signed(x_INST_BASE_ADDR));
constant INST_MEM_SZ : integer := to_integer(signed(x_INST_MEM_SZ));
constant INST_ADDRS_BITS : natural := log2_ceil(INST_MEM_SZ);
constant DATA_BASE_ADDR : integer := to_integer(signed(x_DATA_BASE_ADDR));
constant DATA_MEM_SZ : integer := to_integer(signed(x_DATA_MEM_SZ));
constant SDRAM_BASE_ADDR : integer := to_integer(signed(x_SDRAM_BASE_ADDR));
constant SDRAM_MEM_SZ : integer := to_integer(signed(x_SDRAM_MEM_SZ));
constant IO_BASE_ADDR : integer := to_integer(signed(x_IO_BASE_ADDR));
constant IO_MEM_SZ : integer := to_integer(signed(x_IO_MEM_SZ));
constant IO_ADDR_RANGE : integer := to_integer(signed(x_IO_ADDR_RANGE));
-- maximum number of IO devices, must be a power of two.
constant IO_MAX_NUM_DEVS : integer := 16;
constant IO_ADDR_BITS : integer := log2_ceil(IO_MAX_NUM_DEVS * IO_ADDR_RANGE);
-- I/O addresses are IO_ADDR_RANGE apart
constant IO_PRINT_ADDR : integer := IO_BASE_ADDR;
constant IO_STDOUT_ADDR : integer := IO_BASE_ADDR + 1*IO_ADDR_RANGE;
constant IO_STDIN_ADDR : integer := IO_BASE_ADDR + 2*IO_ADDR_RANGE;
constant IO_READ_ADDR : integer := IO_BASE_ADDR + 3*IO_ADDR_RANGE;
constant IO_WRITE_ADDR : integer := IO_BASE_ADDR + 4*IO_ADDR_RANGE;
constant IO_COUNT_ADDR : integer := IO_BASE_ADDR + 5*IO_ADDR_RANGE;
constant IO_FPU_ADDR : integer := IO_BASE_ADDR + 6*IO_ADDR_RANGE;
constant IO_UART_ADDR : integer := IO_BASE_ADDR + 7*IO_ADDR_RANGE;
constant IO_STATS_ADDR : integer := IO_BASE_ADDR + 8*IO_ADDR_RANGE;
constant IO_DSP7SEG_ADDR : integer := IO_BASE_ADDR + 9*IO_ADDR_RANGE;
constant IO_KEYBD_ADDR : integer := IO_BASE_ADDR + 10*IO_ADDR_RANGE;
constant IO_LCD_ADDR : integer := IO_BASE_ADDR + 11*IO_ADDR_RANGE;
constant IO_SDC_ADDR : integer := IO_BASE_ADDR + 12*IO_ADDR_RANGE;
constant IO_DMA_ADDR : integer := IO_BASE_ADDR + 13*IO_ADDR_RANGE;
constant IO_HIGHEST_ADDR : integer :=
IO_BASE_ADDR + (IO_MAX_NUM_DEVS - 1)*IO_ADDR_RANGE;
-- DATA CACHE parameters ================================================
-- The combination of capacity, associativity and block/line size
-- MUST be such that DC_INDEX_BITS >= 6 (64 sets/way)
constant DC_TOTAL_CAPACITY : natural := 2*1024;
constant DC_NUM_WAYS : natural := 1; -- direct mapped
constant DC_VIA_CAPACITY : natural := DC_TOTAL_CAPACITY / DC_NUM_WAYS;
constant DC_BTS_PER_WORD : natural := 32;
constant DC_BYTES_PER_WORD : natural := 4;
constant DC_WORDS_PER_BLOCK : natural := 4;
constant DC_NUM_WORDS : natural := DC_VIA_CAPACITY / DC_BYTES_PER_WORD;
constant DC_NUM_BLOCKS : natural := DC_NUM_WORDS / DC_WORDS_PER_BLOCK;
constant DC_INDEX_BITS : natural := log2_ceil( DC_NUM_BLOCKS );
constant DC_WORD_SEL_BITS : natural := log2_ceil( DC_WORDS_PER_BLOCK );
constant DC_BYTE_SEL_BITS : natural := log2_ceil( DC_BYTES_PER_WORD );
-- constants for CONFIG1 cop0 register (Table 8-24 pg 103)
constant DC_SETS_PER_WAY: reg3 :=
std_logic_vector(to_signed(DC_INDEX_BITS - 6, 3));
constant DC_LINE_SIZE: reg3 :=
std_logic_vector(to_signed(DC_WORD_SEL_BITS + 1, 3));
constant DC_ASSOCIATIVITY: reg3 :=
std_logic_vector(to_signed(DC_NUM_WAYS - 1, 3));
-- INSTRUCTION CACHE parameters =========================================
-- The combination of capacity, associativity and block/line size
-- MUST be such that IC_INDEX_BITS >= 6 (64 sets/via)
constant IC_TOTAL_CAPACITY : natural := 1024; -- 2*1024;
constant IC_NUM_WAYS : natural := 1; -- direct mapped
constant IC_VIA_CAPACITY : natural := IC_TOTAL_CAPACITY / IC_NUM_WAYS;
constant IC_BTS_PER_WORD : natural := 32;
constant IC_BYTES_PER_WORD : natural := 4;
constant IC_WORDS_PER_BLOCK : natural := 4;
constant IC_NUM_WORDS : natural := IC_VIA_CAPACITY / IC_BYTES_PER_WORD;
constant IC_NUM_BLOCKS : natural := IC_NUM_WORDS / IC_WORDS_PER_BLOCK;
constant IC_INDEX_BITS : natural := log2_ceil( IC_NUM_BLOCKS );
constant IC_WORD_SEL_BITS : natural := log2_ceil( IC_WORDS_PER_BLOCK );
constant IC_BYTE_SEL_BITS : natural := log2_ceil( IC_BYTES_PER_WORD );
-- constants for CONFIG1 cop0 register (Table 8-24 pg 103)
constant IC_SETS_PER_WAY: reg3 :=
std_logic_vector(to_signed(IC_INDEX_BITS - 6, 3));
constant IC_LINE_SIZE: reg3 :=
std_logic_vector(to_signed(IC_WORD_SEL_BITS + 1, 3));
constant IC_ASSOCIATIVITY: reg3 :=
std_logic_vector(to_signed(IC_NUM_WAYS - 1, 3));
-- constants to access the cache statistics counters
constant dcache_Stats_ref : reg3 := "000";
constant dcache_Stats_rdhit : reg3 := "001";
constant dcache_Stats_wrhit : reg3 := "010";
constant dcache_Stats_flush : reg3 := "011";
constant icache_Stats_ref : reg3 := "100";
constant icache_Stats_hit : reg3 := "101";
-- MMU parameters ========================================================
-- constants for CONFIG1 cop0 register (Table 8-24 pg 103)
constant MMU_CAPACITY : natural := 8;
constant MMU_CAPACITY_BITS : natural := log2_ceil( MMU_CAPACITY );
constant MMU_SIZE: reg6 :=
std_logic_vector(to_signed( (MMU_CAPACITY-1), 6) );
constant MMU_WIRED_INIT : reg32 := x"00000000";
constant VABITS : natural := 32;
constant PABITS : natural := 32;
constant PAGE_SZ : natural := 4096; -- 4k pages
constant PAGE_SZ_BITS : natural := log2_ceil( PAGE_SZ );
constant PPN_BITS : natural := PABITS - PAGE_SZ_BITS;
constant VA_HI_BIT : natural := 31; -- VAaddr in EntryHi 31..PG_size
constant VA_LO_BIT : natural := PAGE_SZ_BITS + 1; -- maps 2 phy-pages
constant ASID_HI_BIT : natural := 7; -- ASID in EntryHi 7..0
constant ASID_LO_BIT : natural := 0;
constant EHI_ASIDLO_BIT : natural := 0;
constant EHI_ASIDHI_BIT : natural := 7;
constant EHI_G_BIT : natural := 8;
constant EHI_ALO_BIT : natural := PAGE_SZ_BITS + 1; -- maps 2 phy-pages
constant EHI_AHI_BIT : natural := 31;
constant EHI_ZEROS : std_logic_vector(PAGE_SZ_BITS-EHI_G_BIT-1 downto 0) := (others => '0');
constant TAG_ASIDLO_BIT : natural := 0;
constant TAG_ASIDHI_BIT : natural := 7;
constant TAG_G_BIT : natural := 8;
constant TAG_Z_BIT : natural := 9;
constant TAG_ALO_BIT : natural := PAGE_SZ_BITS + 1; -- maps 2 phy-pages
constant TAG_AHI_BIT : natural := 31;
constant ELO_G_BIT : natural := 0;
constant ELO_V_BIT : natural := 1;
constant ELO_D_BIT : natural := 2;
constant ELO_CLO_BIT : natural := 3;
constant ELO_CHI_BIT : natural := 5;
constant ELO_ALO_BIT : natural := 6;
constant ELO_AHI_BIT : natural := ELO_ALO_BIT + PPN_BITS - 1;
constant DAT_G_BIT : natural := 0;
constant DAT_V_BIT : natural := 1;
constant DAT_D_BIT : natural := 2;
constant DAT_CLO_BIT : natural := 3;
constant DAT_CHI_BIT : natural := 5;
constant DAT_ALO_BIT : natural := 6;
constant DAT_AHI_BIT : natural := DAT_ALO_BIT + PPN_BITS - 1;
constant DAT_REG_BITS : natural := DAT_ALO_BIT + PPN_BITS;
constant ContextPTE_init : reg9 := b"000000000";
constant mmu_PageMask : reg32 := x"00001800"; -- pg 68, 4k pages only
subtype mmu_dat_reg is std_logic_vector (DAT_AHI_BIT downto 0);
subtype MMU_idx_bits is std_logic_vector(MMU_CAPACITY_BITS-1 downto 0);
constant MMU_idx_0s : std_logic_vector(30 downto MMU_CAPACITY_BITS) :=
(others => '0');
constant MMU_IDX_BIT : natural := 31; -- probe hit=1, miss=0
-- VA tags map a pair of PHY pages, thus VAddr is 1 bit less than (VABITS-1..PAGE_SZ_BITS)
constant tag_zeros : std_logic_vector(PAGE_SZ_BITS downto 0) := (others => '0');
constant tag_ones : std_logic_vector(VABITS-1 downto PAGE_SZ_BITS+1) := (others => '1');
constant tag_mask : reg32 := tag_ones & tag_zeros;
constant tag_g : reg32 := x"00000100";
-- physical addresses for 8 ROM pages
constant x_ROM_PPN_0 : reg32 := std_logic_vector(to_signed(INST_BASE_ADDR + 0*PAGE_SZ, 32));
constant x_ROM_PPN_1 : reg32 := std_logic_vector(to_signed(INST_BASE_ADDR + 1*PAGE_SZ, 32));
constant x_ROM_PPN_2 : reg32 := std_logic_vector(to_signed(INST_BASE_ADDR + 2*PAGE_SZ, 32));
constant x_ROM_PPN_3 : reg32 := std_logic_vector(to_signed(INST_BASE_ADDR + 3*PAGE_SZ, 32));
constant x_ROM_PPN_4 : reg32 := std_logic_vector(to_signed(INST_BASE_ADDR + 4*PAGE_SZ, 32));
constant x_ROM_PPN_5 : reg32 := std_logic_vector(to_signed(INST_BASE_ADDR + 5*PAGE_SZ, 32));
constant x_ROM_PPN_6 : reg32 := std_logic_vector(to_signed(INST_BASE_ADDR + 6*PAGE_SZ, 32));
constant x_ROM_PPN_7 : reg32 := std_logic_vector(to_signed(INST_BASE_ADDR + 7*PAGE_SZ, 32));
constant MMU_ini_tag_ROM0 : reg32 := (x_ROM_PPN_0 and tag_mask) or tag_g;
constant MMU_ini_dat_ROM0 : mmu_dat_reg :=
x_ROM_PPN_0(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_ROM1 : mmu_dat_reg :=
x_ROM_PPN_1(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_ROM2 : reg32 := (x_ROM_PPN_2 and tag_mask) or tag_g;
constant MMU_ini_dat_ROM2 : mmu_dat_reg :=
x_ROM_PPN_2(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_ROM3 : mmu_dat_reg :=
x_ROM_PPN_3(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_ROM4 : reg32 := (x_ROM_PPN_4 and tag_mask) or tag_g;
constant MMU_ini_dat_ROM4 : mmu_dat_reg :=
x_ROM_PPN_4(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_ROM5 : mmu_dat_reg :=
x_ROM_PPN_5(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_ROM6 : reg32 := (x_ROM_PPN_6 and tag_mask) or tag_g;
constant MMU_ini_dat_ROM6 : mmu_dat_reg :=
x_ROM_PPN_6(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_ROM7 : mmu_dat_reg :=
x_ROM_PPN_7(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
-- physical addresses for 8 RAM pages
constant x_RAM_PPN_0 : reg32 := std_logic_vector(to_signed(DATA_BASE_ADDR + 0*PAGE_SZ, 32));
constant x_RAM_PPN_1 : reg32 := std_logic_vector(to_signed(DATA_BASE_ADDR + 1*PAGE_SZ, 32));
constant x_RAM_PPN_2 : reg32 := std_logic_vector(to_signed(DATA_BASE_ADDR + 2*PAGE_SZ, 32));
constant x_RAM_PPN_3 : reg32 := std_logic_vector(to_signed(DATA_BASE_ADDR + 3*PAGE_SZ, 32));
constant x_RAM_PPN_4 : reg32 := std_logic_vector(to_signed(DATA_BASE_ADDR + 4*PAGE_SZ, 32));
constant x_RAM_PPN_5 : reg32 := std_logic_vector(to_signed(DATA_BASE_ADDR + 5*PAGE_SZ, 32));
constant x_RAM_PPN_6 : reg32 := std_logic_vector(to_signed(DATA_BASE_ADDR + 6*PAGE_SZ, 32));
constant x_RAM_PPN_7 : reg32 := std_logic_vector(to_signed(DATA_BASE_ADDR + 7*PAGE_SZ, 32));
constant MMU_ini_tag_RAM0 : reg32 := (x_RAM_PPN_0 and tag_mask) or tag_g;
constant MMU_ini_dat_RAM0 : mmu_dat_reg :=
x_RAM_PPN_0(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_RAM1 : mmu_dat_reg :=
x_RAM_PPN_1(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_RAM2 : reg32 := (x_RAM_PPN_2 and tag_mask) or tag_g;
constant MMU_ini_dat_RAM2 : mmu_dat_reg :=
x_RAM_PPN_2(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_RAM3 : mmu_dat_reg :=
x_RAM_PPN_3(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_RAM4 : reg32 := (x_RAM_PPN_4 and tag_mask) or tag_g;
constant MMU_ini_dat_RAM4 : mmu_dat_reg :=
x_RAM_PPN_4(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_RAM5 : mmu_dat_reg :=
x_RAM_PPN_5(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_RAM6 : reg32 := (x_RAM_PPN_6 and tag_mask) or tag_g;
constant MMU_ini_dat_RAM6 : mmu_dat_reg :=
x_RAM_PPN_6(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_RAM7 : mmu_dat_reg :=
x_RAM_PPN_7(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
-- physical addresses for 2 pages reserved for I/O devices
constant x_IO_PPN_0 : reg32 := std_logic_vector(to_signed(IO_BASE_ADDR + 0*PAGE_SZ, 32));
constant x_IO_PPN_1 : reg32 := std_logic_vector(to_signed(IO_BASE_ADDR + 1*PAGE_SZ, 32));
constant MMU_ini_tag_IO : reg32 := (x_IO_BASE_ADDR and tag_mask) or tag_g;
constant MMU_ini_dat_IO0 : mmu_dat_reg :=
x_IO_PPN_0(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_IO1 : mmu_dat_reg :=
x_IO_PPN_1(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
-- physical addresses for 8 SDRAM pages
constant x_SDRAM_PPN_0 : reg32 := std_logic_vector(to_signed(SDRAM_BASE_ADDR + 0*PAGE_SZ, 32));
constant x_SDRAM_PPN_1 : reg32 := std_logic_vector(to_signed(SDRAM_BASE_ADDR + 1*PAGE_SZ, 32));
constant x_SDRAM_PPN_2 : reg32 := std_logic_vector(to_signed(SDRAM_BASE_ADDR + 2*PAGE_SZ, 32));
constant x_SDRAM_PPN_3 : reg32 := std_logic_vector(to_signed(SDRAM_BASE_ADDR + 3*PAGE_SZ, 32));
constant x_SDRAM_PPN_4 : reg32 := std_logic_vector(to_signed(SDRAM_BASE_ADDR + 4*PAGE_SZ, 32));
constant x_SDRAM_PPN_5 : reg32 := std_logic_vector(to_signed(SDRAM_BASE_ADDR + 5*PAGE_SZ, 32));
constant x_SDRAM_PPN_6 : reg32 := std_logic_vector(to_signed(SDRAM_BASE_ADDR + 6*PAGE_SZ, 32));
constant x_SDRAM_PPN_7 : reg32 := std_logic_vector(to_signed(SDRAM_BASE_ADDR + 7*PAGE_SZ, 32));
constant MMU_ini_tag_SDR0 : reg32 := (x_SDRAM_PPN_0 and tag_mask) or tag_g;
constant MMU_ini_dat_SDR0 : mmu_dat_reg :=
x_SDRAM_PPN_0(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_SDR1 : mmu_dat_reg :=
x_SDRAM_PPN_1(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_SDR2 : reg32 := (x_SDRAM_PPN_2 and tag_mask) or tag_g;
constant MMU_ini_dat_SDR2 : mmu_dat_reg :=
x_SDRAM_PPN_2(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_SDR3 : mmu_dat_reg :=
x_SDRAM_PPN_3(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_SDR4 : reg32 := (x_SDRAM_PPN_4 and tag_mask) or tag_g;
constant MMU_ini_dat_SDR4 : mmu_dat_reg :=
x_SDRAM_PPN_4(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_SDR5 : mmu_dat_reg :=
x_SDRAM_PPN_5(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_SDR6 : reg32 := (x_SDRAM_PPN_6 and tag_mask) or tag_g;
constant MMU_ini_dat_SDR6 : mmu_dat_reg :=
x_SDRAM_PPN_6(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_SDR7 : mmu_dat_reg :=
x_SDRAM_PPN_7(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
end p_MEMORY;
-- package body p_MEMORY is
-- end p_MEMORY;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| gpl-3.0 | b33dc7366d4d22d2d32b3b669e31be09 | 0.641062 | 2.954973 | false | false | false | false |
sandrosalvato94/System-Design-Project | src/polito/sdp2017/Tests/Encoder.vhd | 1 | 609 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Encoder is
port (A : in std_logic_vector(2 downto 0);
O : out std_logic_vector(2 downto 0)
);
end Encoder;
architecture Behavioral of Encoder is
begin
process(A)
begin
case A is
when "000" =>
O <= "000";
when "001" =>
O <= "001";
when "010" =>
O <= "001";
when "011" =>
O <= "011";
when "100" =>
O <= "100";
when "101" =>
O <= "010";
when "110" =>
O <= "010";
when "111" =>
O <= "000";
when others =>
end case;
end process;
end Behavioral;
| lgpl-3.0 | 9867b1588554adfd23afe03c84621467 | 0.490969 | 2.793578 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/or_gate.vhd | 15 | 9,199 | -------------------------------------------------------------------------------
-- $Id: or_gate.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- or_gate.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_gate.vhd
-- Version: v1.00a
-- Description: OR gate implementation
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- or_gate.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- History:
-- BLT 2001-05-23 First Version
-- ^^^^^^
-- First version of OPB Bus.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library proc_common_v4_0;
use proc_common_v4_0.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_OR_WIDTH -- Which Xilinx FPGA family to target when
-- syntesizing, affect the RLOC string values
-- C_BUS_WIDTH -- Which Y position the RLOC should start from
--
-- Definition of Ports:
-- A -- Input. Input buses are concatenated together to
-- form input A. Example: to OR buses R, S, and T,
-- assign A <= R & S & T;
-- Y -- Output. Same width as input buses.
--
-------------------------------------------------------------------------------
entity or_gate is
generic (
C_OR_WIDTH : natural range 1 to 32 := 17;
C_BUS_WIDTH : natural range 1 to 64 := 1;
C_USE_LUT_OR : boolean := TRUE
);
port (
A : in std_logic_vector(0 to C_OR_WIDTH*C_BUS_WIDTH-1);
Y : out std_logic_vector(0 to C_BUS_WIDTH-1)
);
end entity or_gate;
architecture imp of or_gate is
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component or_muxcy
generic (
C_NUM_BITS : integer := 8
);
port (
In_bus : in std_logic_vector(0 to C_NUM_BITS-1);
Or_out : out std_logic
);
end component or_muxcy;
signal test : std_logic_vector(0 to C_BUS_WIDTH-1);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
USE_LUT_OR_GEN: if C_USE_LUT_OR generate
OR_PROCESS: process( A ) is
variable yi : std_logic_vector(0 to (C_OR_WIDTH));
begin
for j in 0 to C_BUS_WIDTH-1 loop
yi(0) := '0';
for i in 0 to C_OR_WIDTH-1 loop
yi(i+1) := yi(i) or A(i*C_BUS_WIDTH+j);
end loop;
Y(j) <= yi(C_OR_WIDTH);
end loop;
end process OR_PROCESS;
end generate USE_LUT_OR_GEN;
USE_MUXCY_OR_GEN: if not C_USE_LUT_OR generate
BUS_WIDTH_FOR_GEN: for i in 0 to C_BUS_WIDTH-1 generate
signal in_Bus : std_logic_vector(0 to C_OR_WIDTH-1);
begin
ORDER_INPUT_BUS_PROCESS: process( A ) is
begin
for k in 0 to C_OR_WIDTH-1 loop
in_Bus(k) <= A(k*C_BUS_WIDTH+i);
end loop;
end process ORDER_INPUT_BUS_PROCESS;
OR_BITS_I: or_muxcy
generic map (
C_NUM_BITS => C_OR_WIDTH
)
port map (
In_bus => in_Bus, --[in]
Or_out => Y(i) --[out]
);
end generate BUS_WIDTH_FOR_GEN;
end generate USE_MUXCY_OR_GEN;
end architecture imp;
| apache-2.0 | 40e0e972bf769122d9d5ec0b15451064 | 0.41298 | 4.985908 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/operand_select_gti.vhd | 1 | 26,449 | `protect begin_protected
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`protect end_protected
| apache-2.0 | 949796f1c73d46e38bfc319c4d74ac8b | 0.944005 | 1.844035 | false | false | false | false |
witoldo7/puc-2 | PUC/PUC_567/PUC_2/foo.vhd | 1 | 272 | library ieee;
use ieee.std_logic_1164.all;
entity foo is
Port ( clk1 : out std_logic := '0');
end;
architecture behave of foo is
signal clk: std_logic := '0';
begin
clk <= '1' after 0.5 ns when clk = '0' else
'0' after 0.5 ns when clk = '1';
clk1<=clk;
end; | gpl-3.0 | 7a740bc9de67b6f97a69c17eff81d478 | 0.617647 | 2.72 | false | false | false | false |
sils1297/HWPrak14 | task_3/task_3.srcs/sim_1/new/ads7830.vhd | 1 | 3,435 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ADS7830 is
generic (I2C_ADR : std_logic_vector(6 downto 0) := "1001000"
);
port (
SDA : inout std_logic;
SCL : in std_logic
);
end ADS7830;
architecture RTL of ADS7830 is
constant CMD_WORD : std_logic_vector(7 downto 0) := x"8C";
constant MEM_WORD : std_logic_vector(7 downto 0) := x"9A"; --x"9A";
signal SDA_latched : std_logic := '1';
signal start_or_stop : std_logic;
signal bitcnt : unsigned(3 downto 0) := "1111"; -- counts the I2C bits from 7 downto 0, plus an ACK bit
signal bit_DATA : std_logic;
signal bit_ACK : std_logic;
signal data_phase : std_logic := '0';
signal adr_phase : std_logic;
signal adr_match : std_logic := '0';
signal op_read : std_logic := '0';
signal mem : std_logic_vector(7 downto 0) := MEM_WORD;
signal op_write : std_logic;
signal mem_bit_low : std_logic;
signal SDA_assert_low : std_logic;
signal SDA_assert_ACK : std_logic;
signal SDA_low : std_logic;
signal adr_reg : std_logic_vector(6 downto 0) := "0000000";
signal SDA_int : std_logic;
signal SCL_int : std_logic;
signal initialized : std_logic := '0';
signal SDA_edge : std_logic;
begin
-- for simulation only
SDA_int <= '0' when SDA = '0' else '1';
SCL_int <= '0' when SCL = '0' else '1';
-- We use two wires with a combinatorial loop to detect the start and stop conditions
-- making sure these two wires don't get optimized away
SDA_latched <= SDA_int when (SCL_int = '0') else --((SCL_int = '0') or (start_or_stop = '1')) else
SDA_latched;
SDA_edge <= SDA_int xor SDA_latched;
start_or_stop <= '0' when (SCL_int = '0') else
SDA_edge;
bit_ACK <= bitcnt(3); -- the ACK bit is the 9th bit sent
bit_DATA <= not bit_ACK;
bitcounter: process (SCL_int, start_or_stop)
begin
if (start_or_stop = '1') then
bitcnt <= x"7"; -- the bit 7 is received first
data_phase <= '0';
elsif (SCL_int'event and SCL_int = '0') then
if (bit_ACK = '1') then
bitcnt <= x"7";
data_phase <= '1';
else
bitcnt <= bitcnt - 1;
end if;
end if;
end process;
adr_phase <= not data_phase;
op_write <= not op_read;
regs: process (SCL_int, start_or_stop)
variable cmd_reg : std_logic_vector(7 downto 0) := x"00";
begin
if (start_or_stop = '1') then
adr_match <= '0';
op_read <= '0';
elsif (SCL_int'event and SCL_int = '1') then
if (adr_phase = '1') then
if (bitcnt > "000") then
adr_reg <= adr_reg(5 downto 0) & SDA_int;
else
op_read <= SDA_int;
if (adr_reg = I2C_ADR(6 downto 0)) then
adr_match <= '1';
end if;
end if;
end if;
if (data_phase='1' and adr_match = '1') then
if (op_write='1' and initialized='0') then
if (bitcnt >= "000") then
cmd_reg := cmd_reg(6 downto 0) & SDA_int;
end if;
if (bitcnt = "000" and cmd_reg = CMD_WORD) then
initialized <= '1';
end if;
end if;
end if;
end if;
end process;
mem_bit_low <= not mem(to_integer(bitcnt(2 downto 0)));
SDA_assert_low <= adr_match and bit_DATA and data_phase and op_read and mem_bit_low and initialized;
SDA_assert_ACK <= adr_match and bit_ACK and (adr_phase or op_write);
SDA_low <= SDA_assert_low or SDA_assert_ACK;
SDA <= '0' when (SDA_low = '1') else 'Z';
end RTL;
| agpl-3.0 | 5b71fbd3f54ef186826641df4e76bfbb | 0.592722 | 2.664856 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/axi_master_burst_v2_0/1af76933/hdl/src/vhdl/axi_master_burst_rd_wr_cntlr.vhd | 1 | 66,396 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- Filename: axi_master_burst_rd_wr_cntlr.vhd
--
-- Description:
-- This file implements the DataMover MM2S Full Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_master_burst.vhd
-- |
-- |-- proc_common_v4_0 (helper library)
-- |
-- |-- axi_master_burst_reset.vhd
-- |
-- |-- axi_master_rd_llink.vhd
-- |
-- |-- axi_master_wr_llink.vhd
-- |
-- |
-- |-- axi_master_burst_cmd_status.vhd
-- | |-- axi_master_burst_first_stb_offset.vhd
-- | |-- axi_master_burst_stbs_set.vhd
-- |
-- |-- axi_master_burst_rd_wr_cntlr.vhd
-- |-- axi_master_burst_pcc.vhd
-- | |-- axi_master_burst_strb_gen.vhd
-- |-- axi_master_burst_addr_cntl.vhd
-- |-- axi_master_burst_rddata_cntl.vhd
-- |-- axi_master_burst_wrdata_cntl.vhd
-- |-- axi_master_burst_rd_status_cntl.vhd
-- |-- axi_master_burst_wr_status_cntl.vhd
-- |-- axi_master_burst_skid_buf.vhd
-- |-- axi_master_burst_skid2mm_buf.vhd
--
--
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.0 $
-- Date: $01/18/2011$
--
-- History:
-- DET 01/18/2011 Initial Version
--
-- DET 2/10/2011 Initial for EDk 13.2
-- ~~~~~~
-- -- Per CR593239
-- - Added Min BTT width correction logic (adapted from Datamover)
-- ^^^^^^
-- DET 2/10/2011 Initial for EDK 13.2
-- ~~~~~~
-- - Updated the Addr Cntlr Instance with new ports for avalid
-- registering. Cleaned up a*valid signal generation.
-- - Added missing port mstr2dre_cmd_cmplt to the PCC instance
-- ^^^^^^
--
-- DET 2/15/2011 Initial for EDk 13.2
-- ~~~~~~
-- -- Per CR593812
-- - Modifications to remove unused features to improve Code coverage.
-- Used "-- coverage off" and "-- coverage on" strings.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI MASTER BURST to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- axi_master_burst Library Modules
library axi_master_burst_v2_0 ;
use axi_master_burst_v2_0.axi_master_burst_pcc ;
use axi_master_burst_v2_0.axi_master_burst_addr_cntl ;
use axi_master_burst_v2_0.axi_master_burst_rddata_cntl ;
use axi_master_burst_v2_0.axi_master_burst_wrdata_cntl ;
use axi_master_burst_v2_0.axi_master_burst_rd_status_cntl;
use axi_master_burst_v2_0.axi_master_burst_wr_status_cntl;
use axi_master_burst_v2_0.axi_master_burst_skid_buf ;
use axi_master_burst_v2_0.axi_master_burst_skid2mm_buf ;
-------------------------------------------------------------------------------
entity axi_master_burst_rd_wr_cntlr is
generic (
C_RDWR_ARID : Integer range 0 to 255 := 0;
-- Specifies the constant value to output on
-- the ARID output port
C_RDWR_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_RDWR_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_RDWR_MDATA_WIDTH : Integer range 32 to 256 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_RDWR_SDATA_WIDTH : Integer range 8 to 256 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_RDWR_MAX_BURST_LEN : Integer range 16 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_RDWR_BTT_USED : Integer range 8 to 23 := 12;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_RDWR_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 2;
-- This parameter specifies the depth of the RDWR internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_RDWR_PCC_CMD_WIDTH : Integer range 68 to 68 := 68;
-- Specifies the width of the PCC Command input
C_RDWR_STATUS_WIDTH : Integer range 8 to 8 := 8;
-- Specifies the width of the Status Output bus
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-------------------------------------------------------------------------
-- RDWR Primary Clock input
-------------------------------------------------------------------------
rdwr_aclk : in std_logic;
-- Primary synchronization clock for the Master side
-- interface and internal logic. It is also used
-- for the User interface synchronization when
-- C_STSCMD_IS_ASYNC = 0.
-------------------------------------------------------------------------
-- RDWR Primary Reset input
-------------------------------------------------------------------------
rdwr_areset : in std_logic;
-- Reset used for the internal master logic
-------------------------------------------------------------------------
-- RDWR Master detected Error Output Discrete
-------------------------------------------------------------------------
rdwr_md_error : out std_logic;
-- Master detected error output (acive high)
-------------------------------------------------------------------------
-- Command/Status Module PCC Command Interface (AXI Stream Like)
-------------------------------------------------------------------------
cmd2rdwr_cmd_valid : in std_logic; -- Command IF
rdwr2cmd_cmd_ready : out std_logic; -- Command IF
cmd2rdwr_cmd_data : in std_logic_vector(C_RDWR_PCC_CMD_WIDTH-1 downto 0); -- Command IF
-------------------------------------------------------------------------
-- Command/Status Module Type Interface
-------------------------------------------------------------------------
cmd2rdwr_doing_read : in std_logic; -- Read Active Discrete
cmd2rdwr_doing_write : in std_logic; -- Write Active Discrete
-------------------------------------------------------------------------
-- Command/Status Module Read Status Ports (AXI Stream Like)
-------------------------------------------------------------------------
stat2rsc_status_ready : in std_logic; -- Read Status
rsc2stat_status_valid : out std_logic; -- Read Status
rsc2stat_status : out std_logic_vector(C_RDWR_STATUS_WIDTH-1 downto 0); -- Read Status
-------------------------------------------------------------------------
-- Command/Status Module Write Status Ports (AXI Stream Like)
-------------------------------------------------------------------------
stat2wsc_status_ready : in std_logic; -- Write Status
wsc2stat_status_valid : out std_logic; -- Write Status
wsc2stat_status : out std_logic_vector(C_RDWR_STATUS_WIDTH-1 downto 0); -- Write Status
-------------------------------------------------------------------------
-- LocalLink Enable Outputs (1 clock pulse)
-------------------------------------------------------------------------
rd_llink_enable : out std_logic; -- Read LLink Enable
wr_llink_enable : out std_logic; -- Write LLink Enable
-------------------------------------------------------------------------
-- Read Address Posting Contols/Status
-------------------------------------------------------------------------
rd_allow_addr_req : in std_logic; -- Read Address Posting
rd_addr_req_posted : out std_logic; -- Read Address Posting
rd_xfer_cmplt : out std_logic; -- Read Address Posting
-------------------------------------------------------------------------
-- Write Address Posting Contols/Status
-------------------------------------------------------------------------
wr_allow_addr_req : in std_logic; -- Write Address Posting
wr_addr_req_posted : out std_logic; -- Write Address Posting
wr_xfer_cmplt : out std_logic; -- Write Address Posting
-------------------------------------------------------------------------
-- AXI Read Address Channel I/O
-------------------------------------------------------------------------
rd_arid : out std_logic_vector(C_RDWR_ID_WIDTH-1 downto 0); -- AXI4
rd_araddr : out std_logic_vector(C_RDWR_ADDR_WIDTH-1 downto 0); -- AXI4
rd_arlen : out std_logic_vector(7 downto 0); -- AXI4
rd_arsize : out std_logic_vector(2 downto 0); -- AXI4
rd_arburst : out std_logic_vector(1 downto 0); -- AXI4
rd_arprot : out std_logic_vector(2 downto 0); -- AXI4
rd_arcache : out std_logic_vector(3 downto 0); -- AXI4
rd_arvalid : out std_logic; -- AXI4
rd_arready : in std_logic; -- AXI4
-------------------------------------------------------------------------
-- AXI Read Data Channel I/O
-------------------------------------------------------------------------
rd_rdata : In std_logic_vector(C_RDWR_MDATA_WIDTH-1 downto 0); -- AXI4
rd_rresp : In std_logic_vector(1 downto 0); -- AXI4
rd_rlast : In std_logic; -- AXI4
rd_rvalid : In std_logic; -- AXI4
rd_rready : Out std_logic; -- AXI4
-------------------------------------------------------------------------
-- AXI Read Master Stream Channel I/O
------------------------------------------------------------------------- -- AXI4 Stream
rd_strm_tdata : Out std_logic_vector(C_RDWR_SDATA_WIDTH-1 downto 0); -- AXI4 Stream
rd_strm_tstrb : Out std_logic_vector((C_RDWR_SDATA_WIDTH/8)-1 downto 0);-- AXI4 Stream
rd_strm_tlast : Out std_logic; -- AXI4 Stream
rd_strm_tvalid : Out std_logic; -- AXI4 Stream
rd_strm_tready : In std_logic; -- AXI4 Stream
-------------------------------------------------------------------------
-- AXI Write Address Channel I/O
-------------------------------------------------------------------------
wr_awid : out std_logic_vector(C_RDWR_ID_WIDTH-1 downto 0); -- AXI4
wr_awaddr : out std_logic_vector(C_RDWR_ADDR_WIDTH-1 downto 0); -- AXI4
wr_awlen : out std_logic_vector(7 downto 0); -- AXI4
wr_awsize : out std_logic_vector(2 downto 0); -- AXI4
wr_awburst : out std_logic_vector(1 downto 0); -- AXI4
wr_awprot : out std_logic_vector(2 downto 0); -- AXI4
wr_awcache : out std_logic_vector(3 downto 0); -- AXI4
wr_awvalid : out std_logic; -- AXI4
wr_awready : in std_logic; -- AXI4
-------------------------------------------------------------------------
-- RDWR AXI Write Data Channel I/O
-------------------------------------------------------------------------
wr_wdata : Out std_logic_vector(C_RDWR_MDATA_WIDTH-1 downto 0); -- AXI4
wr_wstrb : Out std_logic_vector((C_RDWR_MDATA_WIDTH/8)-1 downto 0); -- AXI4
wr_wlast : Out std_logic; -- AXI4
wr_wvalid : Out std_logic; -- AXI4
wr_wready : In std_logic; -- AXI4
-------------------------------------------------------------------------
-- RDWR AXI Write response Channel I/O
-------------------------------------------------------------------------
wr_bresp : In std_logic_vector(1 downto 0); -- AXI4
wr_bvalid : In std_logic; -- AXI4
wr_bready : Out std_logic; -- AXI4
-------------------------------------------------------------------------
-- RDWR AXI Slave Stream Channel I/O
-------------------------------------------------------------------------
wr_strm_tdata : In std_logic_vector(C_RDWR_SDATA_WIDTH-1 downto 0); -- AXI4 Stream
wr_strm_tstrb : In std_logic_vector((C_RDWR_SDATA_WIDTH/8)-1 downto 0); -- AXI4 Stream
wr_strm_tlast : In std_logic; -- AXI4 Stream
wr_strm_tvalid : In std_logic; -- AXI4 Stream
wr_strm_tready : Out std_logic -- AXI4 Stream
);
end entity axi_master_burst_rd_wr_cntlr;
architecture implementation of axi_master_burst_rd_wr_cntlr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_rdmux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Read data mux select control.
--
-------------------------------------------------------------------
function func_calc_rdmux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 5 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when others => -- 256 bits
num_addr_bits_needed := 5;
end case;
Return (num_addr_bits_needed);
end function func_calc_rdmux_sel_bits;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_min_btt_width
--
-- Function Description:
-- This function calculates the minimum required value
-- for the used width of the command BTT field.
--
-------------------------------------------------------------------
function funct_get_min_btt_width (max_burst_beats : integer;
bytes_per_beat : integer ) return integer is
Variable var_min_btt_needed : Integer;
Variable var_max_bytes_per_burst : Integer;
begin
var_max_bytes_per_burst := max_burst_beats*bytes_per_beat;
-- coverage off
if (var_max_bytes_per_burst <= 16) then
var_min_btt_needed := 5;
elsif (var_max_bytes_per_burst <= 32) then
var_min_btt_needed := 6;
-- coverage on
elsif (var_max_bytes_per_burst <= 64) then
var_min_btt_needed := 7;
elsif (var_max_bytes_per_burst <= 128) then
var_min_btt_needed := 8;
elsif (var_max_bytes_per_burst <= 256) then
var_min_btt_needed := 9;
elsif (var_max_bytes_per_burst <= 512) then
var_min_btt_needed := 10;
elsif (var_max_bytes_per_burst <= 1024) then
var_min_btt_needed := 11;
elsif (var_max_bytes_per_burst <= 2048) then
var_min_btt_needed := 12;
elsif (var_max_bytes_per_burst <= 4096) then
var_min_btt_needed := 13;
-- coverage off
else -- 8K byte range
var_min_btt_needed := 14;
-- coverage on
end if;
Return (var_min_btt_needed);
end function funct_get_min_btt_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_fix_btt_used
--
-- Function Description:
-- THis function makes sure the BTT width used is at least the
-- minimum needed.
--
-------------------------------------------------------------------
function funct_fix_btt_used (requested_btt_width : integer;
min_btt_width : integer) return integer is
Variable var_corrected_btt_width : Integer;
begin
If (requested_btt_width < min_btt_width) Then
var_corrected_btt_width := min_btt_width;
else
var_corrected_btt_width := requested_btt_width;
End if;
Return (var_corrected_btt_width);
end function funct_fix_btt_used;
-- Constant Declarations ----------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant RDWR_ARID_VALUE : integer range 0 to 255 := C_RDWR_ARID;
Constant RDWR_ARID_WIDTH : integer range 1 to 8 := C_RDWR_ID_WIDTH;
Constant RDWR_ADDR_WIDTH : integer range 32 to 64 := C_RDWR_ADDR_WIDTH;
Constant RDWR_MDATA_WIDTH : integer range 32 to 256 := C_RDWR_MDATA_WIDTH;
Constant RDWR_SDATA_WIDTH : integer range 8 to 256 := C_RDWR_SDATA_WIDTH;
Constant BASE_PCC_CMD_WIDTH : integer := 64;
Constant RDWR_TAG_WIDTH : integer range 1 to 8 := C_RDWR_PCC_CMD_WIDTH-BASE_PCC_CMD_WIDTH;
Constant RDWR_CMD_WIDTH : integer := C_RDWR_PCC_CMD_WIDTH;
Constant RDWR_STS_WIDTH : integer := C_RDWR_STATUS_WIDTH;
Constant INCLUDE_RDWR_STSFIFO : integer range 0 to 1 := 1;
Constant RDWR_STSCMD_FIFO_DEPTH : integer range 1 to 16 := 1;
Constant RDWR_STSCMD_IS_ASYNC : integer range 0 to 1 := 0;
Constant ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_RDWR_ADDR_PIPE_DEPTH;
Constant RD_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_RDWR_ADDR_PIPE_DEPTH;
Constant WR_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_RDWR_ADDR_PIPE_DEPTH;
Constant SEL_ADDR_WIDTH : integer range 2 to 5 := func_calc_rdmux_sel_bits(RDWR_MDATA_WIDTH);
Constant RDWR_BTT_USED : integer range 8 to 23 := C_RDWR_BTT_USED;
Constant RDWR_MAX_BURST_LEN : integer range 16 to 256 := C_RDWR_MAX_BURST_LEN;
Constant RDWR_BYTES_PER_BEAT : integer range 4 to 16 := RDWR_SDATA_WIDTH/8;
Constant RDWR_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(RDWR_MAX_BURST_LEN,
RDWR_BYTES_PER_BEAT);
Constant RDWR_CORRECTED_BTT_USED : integer := funct_fix_btt_used(RDWR_BTT_USED,
RDWR_MIN_BTT_NEEDED);
Constant OMIT_INDET_BTT : integer range 0 to 1 := 0;
Constant OMIT_DRE : integer range 0 to 1 := 0;
Constant DRE_ALIGN_WIDTH : integer range 1 to 3 := 1;
Constant WR_STATUS_CNTL_FIFO_DEPTH : integer range 1 to 32 := WR_DATA_CNTL_FIFO_DEPTH+2; -- 2 added for going
-- full thresholding
-- in WSC
Constant WSC_BYTES_RCVD_WIDTH : integer range 8 to 32 := RDWR_CORRECTED_BTT_USED;
Constant OMIT_STORE_FORWARD : integer range 0 to 1 := 0;
-- Signal Declarations ------------------------------------------
signal sig_md_error_reg : std_logic := '0';
signal sig_doing_read : std_logic := '0';
signal sig_doing_write : std_logic := '0';
signal sig_axi2addr_aready : std_logic := '0';
signal sig_addr2axi_arvalid : std_logic := '0';
signal sig_addr2axi_awvalid : std_logic := '0';
signal sig_addr2axi_aid : std_logic_vector(RDWR_ARID_WIDTH-1 downto 0) := (others => '0');
signal sig_addr2axi_aaddr : std_logic_vector(RDWR_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr2axi_alen : std_logic_vector(7 downto 0) := (others => '0');
signal sig_addr2axi_asize : std_logic_vector(2 downto 0) := (others => '0');
signal sig_addr2axi_aburst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_addr2axi_aprot : std_logic_vector(2 downto 0) := (others => '0');
signal sig_rdc2axi_rready : std_logic := '0';
signal sig_axi2rdc_rvalid : std_logic := '0';
signal sig_axi2rdc_rdata : std_logic_vector(RDWR_MDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_axi2rdc_rresp : std_logic_vector(1 downto 0) := (others => '0');
signal sig_axi2rdc_rlast : std_logic := '0';
signal sig_wdc2wrskid_addr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_wrskid2wdc_wready : std_logic := '0';
signal sig_wdc2wrskid_wvalid : std_logic := '0';
signal sig_wdc2wrskid_wdata : std_logic_vector(RDWR_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_wdc2wrskid_wstrb : std_logic_vector((RDWR_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_wdc2wrskid_wlast : std_logic := '0';
signal sig_axi2wrskid_wready : std_logic := '0';
signal sig_wrskid2axi_wvalid : std_logic := '0';
signal sig_wrskid2axi_wdata : std_logic_vector(RDWR_MDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_wrskid2axi_wstrb : std_logic_vector((RDWR_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_wrskid2axi_wlast : std_logic := '0';
signal sig_wsc2axi_bready : std_logic := '0';
signal sig_axi2wsc_bvalid : std_logic := '0';
signal sig_axi2wsc_bresp : std_logic_vector(1 downto 0) := (others => '0');
signal sig_rdskid2rdc_tready : std_logic := '0';
signal sig_rdc2rdskid_tvalid : std_logic := '0';
signal sig_rdc2rdskid_tdata : std_logic_vector(RDWR_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_rdc2rdskid_tstrb : std_logic_vector((RDWR_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_rdc2rdskid_tlast : std_logic := '0';
signal sig_strm2rdskid_tready : std_logic := '0';
signal sig_rdskid2strm_tvalid : std_logic := '0';
signal sig_rdskid2strm_tdata : std_logic_vector(RDWR_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_rdskid2strm_tstrb : std_logic_vector((RDWR_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_rdskid2strm_tlast : std_logic := '0';
signal sig_wrskid2strm_tready : std_logic := '0';
signal sig_strm2wrskid_tvalid : std_logic := '0';
signal sig_strm2wrskid_tdata : std_logic_vector(RDWR_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strm2wrskid_tstrb : std_logic_vector((RDWR_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_strm2wrskid_tlast : std_logic := '0';
signal sig_wdc2wrskid_tready : std_logic := '0';
signal sig_wrskid2wdc_tvalid : std_logic := '0';
signal sig_wrskid2wdc_tdata : std_logic_vector(RDWR_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_wrskid2wdc_tstrb : std_logic_vector((RDWR_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_wrskid2wdc_tlast : std_logic := '0';
signal sig_cmd2pcc_command : std_logic_vector(RDWR_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2pcc_cmd_valid : std_logic := '0';
signal sig_pcc2cmd_cmd_ready : std_logic := '0';
signal sig_pcc2addr_tag : std_logic_vector(RDWR_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pcc2addr_addr : std_logic_vector(RDWR_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_pcc2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_pcc2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_pcc2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_pcc2addr_cmd_cmplt : std_logic := '0';
signal sig_pcc2addr_calc_error : std_logic := '0';
signal sig_pcc2addr_cmd_valid : std_logic := '0';
signal sig_addr2pcc_cmd_ready : std_logic := '0';
signal sig_pcc2data_tag : std_logic_vector(RDWR_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pcc2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_pcc2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_pcc2data_strt_strb : std_logic_vector((RDWR_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_pcc2data_last_strb : std_logic_vector((RDWR_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_pcc2data_drr : std_logic := '0';
signal sig_pcc2data_eof : std_logic := '0';
signal sig_pcc2data_sequential : std_logic := '0';
signal sig_pcc2data_calc_error : std_logic := '0';
signal sig_pcc2data_cmd_cmplt : std_logic := '0';
signal sig_pcc2data_dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_pcc2data_dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_pcc2all_calc_err : std_logic := '0';
signal sig_pcc2data_cmd_valid : std_logic := '0';
signal sig_pcc2rdc_cmd_valid : std_logic := '0';
signal sig_pcc2wdc_cmd_valid : std_logic := '0';
signal sig_data2pcc_cmd_ready : std_logic := '0';
signal sig_rdc2pcc_cmd_ready : std_logic := '0';
signal sig_wdc2pcc_cmd_ready : std_logic := '0';
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_addr2wdc_addr_posted : std_logic := '0';
signal sig_addr2rdc_addr_posted : std_logic := '0';
signal sig_rdc2skid_halt : std_logic := '0';
signal sig_wdc2skid_halt : std_logic := '0';
signal sig_rd_xfer_cmplt : std_logic := '0';
signal sig_wr_xfer_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_rdc2addr_stop_req : std_logic := '0';
signal sig_wdc2addr_stop_req : std_logic := '0';
signal sig_wsc2wdc_halt_pipe : std_logic := '0';
signal sig_addr2stat_calc_error : std_logic := '0';
signal sig_addr2rsc_calc_error : std_logic := '0';
signal sig_addr2wsc_calc_error : std_logic := '0';
signal sig_addr2stat_cmd_fifo_empty : std_logic := '0';
signal sig_addr2rsc_cmd_fifo_empty : std_logic := '0';
signal sig_addr2wsc_cmd_fifo_empty : std_logic := '0';
signal sig_rdc2rsc_tag : std_logic_vector(RDWR_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_rdc2rsc_calc_err : std_logic := '0';
signal sig_rdc2rsc_okay : std_logic := '0';
signal sig_rdc2rsc_decerr : std_logic := '0';
signal sig_rdc2rsc_slverr : std_logic := '0';
signal sig_rdc2rsc_cmd_cmplt : std_logic := '0';
signal sig_rsc2rdc_ready : std_logic := '0';
signal sig_rdc2rsc_valid : std_logic := '0';
signal sig_rsc2rdc_halt_pipe : std_logic := '0';
signal sig_allow_addr_req : std_logic := '0';
signal sig_addr_req_posted : std_logic := '0';
signal sig_stat2rsc_status_ready : std_logic := '0';
signal sig_rsc2stat_status_valid : std_logic := '0';
signal sig_rsc2stat_status : std_logic_vector(RDWR_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_stat2wsc_status_ready : std_logic := '0';
signal sig_wsc2stat_status_valid : std_logic := '0';
signal sig_wsc2stat_status : std_logic_vector(RDWR_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_wdc_stbs_asserted : std_logic_vector(7 downto 0) := (others => '0');
signal sig_wdc2wsc_tag : std_logic_vector(RDWR_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_wdc2wsc_calc_err : std_logic := '0';
signal sig_wdc2wsc_last_err : std_logic := '0';
signal sig_wdc2wsc_cmd_cmplt : std_logic := '0';
signal sig_wsc2wdc_ready : std_logic := '0';
signal sig_wdc2wsc_valid : std_logic := '0';
signal sig_wdc2wsc_eop : std_logic := '0';
signal sig_wdc2wsc_bytes_rcvd : std_logic_vector(WSC_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_enable_rd_llink : std_logic := '0';
signal sig_enable_wr_llink : std_logic := '0';
signal sig_doing_read_reg : std_logic := '0';
signal sig_doing_write_reg : std_logic := '0';
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_realign2wdc_eop_error : std_logic := '0';
begin --(architecture implementation)
---------------------------------------------------------------
-- Command Type Discrete Assignements
---------------------------------------------------------------
sig_doing_read <= cmd2rdwr_doing_read;
sig_doing_write <= cmd2rdwr_doing_write;
---------------------------------------------------------------
-- Read Address Pipelining Assignements
---------------------------------------------------------------
rd_addr_req_posted <= sig_addr_req_posted
When (sig_doing_read = '1')
Else '0';
rd_xfer_cmplt <= sig_rd_xfer_cmplt ;
---------------------------------------------------------------
-- Write Address Pipelining Assignements
---------------------------------------------------------------
wr_addr_req_posted <= sig_addr_req_posted
When (sig_doing_write = '1')
Else '0';
wr_xfer_cmplt <= sig_wr_xfer_cmplt;
---------------------------------------------------------------
-- AXI Read Addess Channel AREADY Port Assignments
-- This is a composite of the Read and Write Address ready
-- inputs.
---------------------------------------------------------------
sig_axi2addr_aready <= rd_arready
when (sig_doing_read = '1')
Else wr_awready
when (sig_doing_write = '1')
else '0' ;
---------------------------------------------------------------
-- AXI Read Addess Channel Port Assignments
---------------------------------------------------------------
rd_arvalid <= sig_addr2axi_arvalid;
rd_arid <= sig_addr2axi_aid ;
rd_araddr <= sig_addr2axi_aaddr ;
rd_arlen <= sig_addr2axi_alen ;
rd_arsize <= sig_addr2axi_asize ;
rd_arburst <= sig_addr2axi_aburst ;
rd_arprot <= sig_addr2axi_aprot ;
rd_arcache <= "0011" ; -- Per Interface-X guidelines for Masters ;
---------------------------------------------------------------
-- AXI Read Data Channel Port Assignments
---------------------------------------------------------------
rd_rready <= sig_rdc2axi_rready ;
sig_axi2rdc_rvalid <= rd_rvalid ;
sig_axi2rdc_rdata <= rd_rdata ;
sig_axi2rdc_rresp <= rd_rresp ;
sig_axi2rdc_rlast <= rd_rlast ;
---------------------------------------------------------------
-- AXI Write Addess Channel Port Assignments
---------------------------------------------------------------
wr_awvalid <= sig_addr2axi_awvalid;
wr_awid <= sig_addr2axi_aid ;
wr_awaddr <= sig_addr2axi_aaddr ;
wr_awlen <= sig_addr2axi_alen ;
wr_awsize <= sig_addr2axi_asize ;
wr_awburst <= sig_addr2axi_aburst ;
wr_awprot <= sig_addr2axi_aprot ;
wr_awcache <= "0011" ; -- Per Interface-X guidelines for Masters ;
-------------------------------------------------------------------------
-- AXI Write Data Channel Port Assignments
-------------------------------------------------------------------------
sig_axi2wrskid_wready <= wr_wready ;
wr_wvalid <= sig_wrskid2axi_wvalid ;
wr_wdata <= sig_wrskid2axi_wdata ;
wr_wstrb <= sig_wrskid2axi_wstrb ;
wr_wlast <= sig_wrskid2axi_wlast ;
-------------------------------------------------------------------------
-- AXI Write Response Channel Port Assignments
-------------------------------------------------------------------------
wr_bready <= sig_wsc2axi_bready ;
sig_axi2wsc_bvalid <= wr_bvalid ;
sig_axi2wsc_bresp <= wr_bresp ;
-------------------------------------------------------------------------
-- AXI Read Master Stream Channel Port Assignments
-------------------------------------------------------------------------
sig_strm2rdskid_tready <= rd_strm_tready ;
rd_strm_tvalid <= sig_rdskid2strm_tvalid ;
rd_strm_tdata <= sig_rdskid2strm_tdata ;
rd_strm_tstrb <= sig_rdskid2strm_tstrb ;
rd_strm_tlast <= sig_rdskid2strm_tlast ;
-------------------------------------------------------------------------
-- AXI Write Stream Channel Port Assignments
-------------------------------------------------------------------------
wr_strm_tready <= sig_wrskid2strm_tready ;
sig_strm2wrskid_tvalid <= wr_strm_tvalid ;
sig_strm2wrskid_tdata <= wr_strm_tdata ;
sig_strm2wrskid_tstrb <= wr_strm_tstrb ;
sig_strm2wrskid_tlast <= wr_strm_tlast ;
-------------------------------------------------------------------------
-- Read Status I/O Port Assignments
-------------------------------------------------------------------------
sig_stat2rsc_status_ready <= stat2rsc_status_ready ;
rsc2stat_status_valid <= sig_rsc2stat_status_valid ;
rsc2stat_status <= sig_rsc2stat_status ;
-------------------------------------------------------------------------
-- Write Status I/O Port Assignments
-------------------------------------------------------------------------
sig_stat2wsc_status_ready <= stat2wsc_status_ready ;
wsc2stat_status_valid <= sig_wsc2stat_status_valid ;
wsc2stat_status <= sig_wsc2stat_status ;
-------------------------------------------------------------------------
-- Internal error output discrete
-------------------------------------------------------------------------
rdwr_md_error <= sig_md_error_reg;
-------------------------------------------------------------------------
-- Assign the PCC Command Interface Ports
-------------------------------------------------------------------------
sig_cmd2pcc_command <= cmd2rdwr_cmd_data ;
sig_cmd2pcc_cmd_valid <= cmd2rdwr_cmd_valid ;
rdwr2cmd_cmd_ready <= sig_pcc2cmd_cmd_ready ;
-------------------------------------------------------------------------
-- Misc. Logic
-------------------------------------------------------------------------
sig_rst2all_stop_request <= '0';
-------------------------------------------------------------------------
-- LocalLink Enables Logic
-------------------------------------------------------------------------
rd_llink_enable <= sig_enable_rd_llink;
wr_llink_enable <= sig_enable_wr_llink;
-- create a 1 clock pulse for enabling the Read LocalLink on
-- the rising edge of the sig_doing_read signal.
sig_enable_rd_llink <= not(sig_doing_read_reg) and
sig_doing_read ;
-- create a 1 clock pulse for enabling the write LocalLink on
-- the rising edge of the sig_doing_write signal.
sig_enable_wr_llink <= not(sig_doing_write_reg) and
sig_doing_write ;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DOING_RD_FLOP
--
-- Process Description:
-- Registers the Doing Read input signal
--
-------------------------------------------------------------
IMP_DOING_RD_FLOP : process (rdwr_aclk)
begin
if (rdwr_aclk'event and rdwr_aclk = '1') then
if (rdwr_areset = '1') then
sig_doing_read_reg <= '0';
else
sig_doing_read_reg <= sig_doing_read;
end if;
end if;
end process IMP_DOING_RD_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DOING_WR_FLOP
--
-- Process Description:
-- Registers the Doing Write input signal
--
-------------------------------------------------------------
IMP_DOING_WR_FLOP : process (rdwr_aclk)
begin
if (rdwr_aclk'event and rdwr_aclk = '1') then
if (rdwr_areset = '1') then
sig_doing_write_reg <= '0';
else
sig_doing_write_reg <= sig_doing_write;
end if;
end if;
end process IMP_DOING_WR_FLOP;
-------------------------------------------------------------------------
-- Predictive Command Calculator Logic
-------------------------------------------------------------------------
sig_data2pcc_cmd_ready <= sig_rdc2pcc_cmd_ready
When (sig_doing_read = '1')
Else sig_wdc2pcc_cmd_ready
When (sig_doing_write = '1')
Else '0';
sig_pcc2rdc_cmd_valid <= sig_pcc2data_cmd_valid
when (sig_doing_read = '1')
Else '0';
sig_pcc2wdc_cmd_valid <= sig_pcc2data_cmd_valid
when (sig_doing_write = '1')
Else '0';
------------------------------------------------------------
-- Instance: I_MSTR_PCC
--
-- Description:
-- Predictive Command Calculator Block
--
------------------------------------------------------------
I_MSTR_PCC : entity axi_master_burst_v2_0.axi_master_burst_pcc
generic map (
C_DRE_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => RDWR_ADDR_WIDTH ,
C_STREAM_DWIDTH => RDWR_SDATA_WIDTH ,
C_MAX_BURST_LEN => RDWR_MAX_BURST_LEN ,
C_CMD_WIDTH => RDWR_CMD_WIDTH ,
C_TAG_WIDTH => RDWR_TAG_WIDTH ,
C_BTT_USED => RDWR_CORRECTED_BTT_USED ,
C_SUPPORT_INDET_BTT => OMIT_INDET_BTT
)
port map (
-- Clock input
primary_aclk => rdwr_aclk ,
mmap_reset => rdwr_areset ,
cmd2mstr_command => sig_cmd2pcc_command ,
cmd2mstr_cmd_valid => sig_cmd2pcc_cmd_valid ,
mst2cmd_cmd_ready => sig_pcc2cmd_cmd_ready ,
mstr2addr_tag => sig_pcc2addr_tag ,
mstr2addr_addr => sig_pcc2addr_addr ,
mstr2addr_len => sig_pcc2addr_len ,
mstr2addr_size => sig_pcc2addr_size ,
mstr2addr_burst => sig_pcc2addr_burst ,
mstr2addr_cmd_cmplt => sig_pcc2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_pcc2addr_calc_error ,
mstr2addr_cmd_valid => sig_pcc2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2pcc_cmd_ready ,
mstr2data_tag => sig_pcc2data_tag ,
mstr2data_saddr_lsb => sig_pcc2data_saddr_lsb ,
mstr2data_len => sig_pcc2data_len ,
mstr2data_strt_strb => sig_pcc2data_strt_strb ,
mstr2data_last_strb => sig_pcc2data_last_strb ,
mstr2data_drr => sig_pcc2data_drr ,
mstr2data_eof => sig_pcc2data_eof ,
mstr2data_sequential => sig_pcc2data_sequential ,
mstr2data_calc_error => sig_pcc2data_calc_error ,
mstr2data_cmd_cmplt => sig_pcc2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_pcc2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2pcc_cmd_ready ,
mstr2data_dre_src_align => sig_pcc2data_dre_src_align ,
mstr2data_dre_dest_align => sig_pcc2data_dre_dest_align ,
calc_error => sig_pcc2all_calc_err ,
dre2mstr_cmd_ready => LOGIC_HIGH ,
mstr2dre_cmd_valid => open ,
mstr2dre_tag => open ,
mstr2dre_dre_src_align => open ,
mstr2dre_dre_dest_align => open ,
mstr2dre_btt => open ,
mstr2dre_drr => open ,
mstr2dre_eof => open ,
mstr2dre_cmd_cmplt => open ,
mstr2dre_calc_error => open
);
-------------------------------------------------------------------------
-- Address Controller Logic
-------------------------------------------------------------------------
sig_allow_addr_req <= rd_allow_addr_req
when (sig_doing_read = '1')
Else wr_allow_addr_req
When (sig_doing_write = '1')
Else '0';
sig_addr2rdc_addr_posted <= sig_addr2data_addr_posted
When (sig_doing_read = '1')
Else '0';
sig_addr2wdc_addr_posted <= sig_addr2data_addr_posted
When (sig_doing_write = '1')
Else '0';
sig_data2addr_stop_req <= sig_rdc2addr_stop_req or
sig_wdc2addr_stop_req ;
sig_addr2rsc_calc_error <= sig_addr2stat_calc_error
when (sig_doing_read = '1')
Else '0';
sig_addr2wsc_calc_error <= sig_addr2stat_calc_error
when (sig_doing_write = '1')
Else '0';
sig_addr2rsc_cmd_fifo_empty <= sig_addr2stat_cmd_fifo_empty
when (sig_doing_read = '1')
Else '0';
sig_addr2wsc_cmd_fifo_empty <= sig_addr2stat_cmd_fifo_empty
when (sig_doing_write = '1')
Else '0';
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_master_burst_v2_0.axi_master_burst_addr_cntl
generic map (
C_ADDR_FIFO_DEPTH => ADDR_CNTL_FIFO_DEPTH ,
C_ADDR_WIDTH => RDWR_ADDR_WIDTH ,
C_ADDR_ID => RDWR_ARID_VALUE ,
C_ADDR_ID_WIDTH => RDWR_ARID_WIDTH ,
C_TAG_WIDTH => RDWR_TAG_WIDTH
)
port map (
primary_aclk => rdwr_aclk ,
mmap_reset => rdwr_areset ,
doing_read => sig_doing_read ,
doing_write => sig_doing_write ,
addr2axi_aid => sig_addr2axi_aid ,
addr2axi_aaddr => sig_addr2axi_aaddr ,
addr2axi_alen => sig_addr2axi_alen ,
addr2axi_asize => sig_addr2axi_asize ,
addr2axi_aburst => sig_addr2axi_aburst ,
addr2axi_aprot => sig_addr2axi_aprot ,
addr2axi_arvalid => sig_addr2axi_arvalid ,
addr2axi_awvalid => sig_addr2axi_awvalid ,
axi2addr_aready => sig_axi2addr_aready ,
mstr2addr_tag => sig_pcc2addr_tag ,
mstr2addr_addr => sig_pcc2addr_addr ,
mstr2addr_len => sig_pcc2addr_len ,
mstr2addr_size => sig_pcc2addr_size ,
mstr2addr_burst => sig_pcc2addr_burst ,
mstr2addr_cmd_cmplt => sig_pcc2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_pcc2addr_calc_error ,
mstr2addr_cmd_valid => sig_pcc2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2pcc_cmd_ready ,
addr2rst_stop_cmplt => open ,
allow_addr_req => sig_allow_addr_req ,
addr_req_posted => sig_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => LOGIC_LOW ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2stat_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2stat_cmd_fifo_empty
);
-------------------------------------------------------------------------
-- Read Data Controller Logic
-------------------------------------------------------------------------
------------------------------------------------------------
-- Instance: I_RD_DATA_CNTL
--
-- Description:
-- Read Data Controller Block
--
------------------------------------------------------------
I_RD_DATA_CNTL : entity axi_master_burst_v2_0.axi_master_burst_rddata_cntl
generic map (
C_INCLUDE_DRE => OMIT_DRE ,
C_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => RDWR_MDATA_WIDTH ,
C_STREAM_DWIDTH => RDWR_SDATA_WIDTH ,
C_TAG_WIDTH => RDWR_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset -----------------------------------
primary_aclk => rdwr_aclk ,
mmap_reset => rdwr_areset ,
-- Soft Shutdown Interface -----------------------------
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_rdc2addr_stop_req ,
data2rst_stop_cmplt => open ,
-- External Address Pipelining Contol support
mm2s_rd_xfer_cmplt => sig_rd_xfer_cmplt ,
-- AXI Read Data Channel I/O -------------------------------
mm2s_rdata => sig_axi2rdc_rdata ,
mm2s_rresp => sig_axi2rdc_rresp ,
mm2s_rlast => sig_axi2rdc_rlast ,
mm2s_rvalid => sig_axi2rdc_rvalid ,
mm2s_rready => sig_rdc2axi_rready ,
-- MM2S DRE Control -----------------------------------
mm2s_dre_new_align => open ,
mm2s_dre_use_autodest => open ,
mm2s_dre_src_align => open ,
mm2s_dre_dest_align => open ,
mm2s_dre_flush => open ,
-- AXI Master Stream -----------------------------------
mm2s_strm_wvalid => sig_rdc2rdskid_tvalid ,
mm2s_strm_wready => sig_rdskid2rdc_tready ,
mm2s_strm_wdata => sig_rdc2rdskid_tdata ,
mm2s_strm_wstrb => sig_rdc2rdskid_tstrb ,
mm2s_strm_wlast => sig_rdc2rdskid_tlast ,
-- Command Calculator Interface --------------------------
mstr2data_tag => sig_pcc2data_tag ,
mstr2data_saddr_lsb => sig_pcc2data_saddr_lsb ,
mstr2data_len => sig_pcc2data_len ,
mstr2data_strt_strb => sig_pcc2data_strt_strb ,
mstr2data_last_strb => sig_pcc2data_last_strb ,
mstr2data_drr => sig_pcc2data_drr ,
mstr2data_eof => sig_pcc2data_eof ,
mstr2data_sequential => sig_pcc2data_sequential ,
mstr2data_calc_error => sig_pcc2data_calc_error ,
mstr2data_cmd_cmplt => sig_pcc2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_pcc2rdc_cmd_valid ,
data2mstr_cmd_ready => sig_rdc2pcc_cmd_ready ,
mstr2data_dre_src_align => sig_pcc2data_dre_src_align ,
mstr2data_dre_dest_align => sig_pcc2data_dre_dest_align ,
-- Address Controller Interface --------------------------
addr2data_addr_posted => sig_addr2rdc_addr_posted ,
-- Data Controller Halted Status
data2all_dcntlr_halted => open ,
-- Output Stream Skid Buffer Halt control
data2skid_halt => sig_rdc2skid_halt ,
-- Read Status Controller Interface --------------------------
data2rsc_tag => sig_rdc2rsc_tag ,
data2rsc_calc_err => sig_rdc2rsc_calc_err ,
data2rsc_okay => sig_rdc2rsc_okay ,
data2rsc_decerr => sig_rdc2rsc_decerr ,
data2rsc_slverr => sig_rdc2rsc_slverr ,
data2rsc_cmd_cmplt => sig_rdc2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2rdc_ready ,
data2rsc_valid => sig_rdc2rsc_valid ,
rsc2mstr_halt_pipe => sig_rsc2rdc_halt_pipe
);
------------------------------------------------------------
-- Instance: I_RD_STATUS_CNTLR
--
-- Description:
-- Read Status Controller Block
--
------------------------------------------------------------
I_RD_STATUS_CNTLR : entity axi_master_burst_v2_0.axi_master_burst_rd_status_cntl
generic map (
C_STS_WIDTH => RDWR_STS_WIDTH ,
C_TAG_WIDTH => RDWR_TAG_WIDTH
)
port map (
primary_aclk => rdwr_aclk ,
mmap_reset => rdwr_areset ,
calc2rsc_calc_error => sig_pcc2all_calc_err ,
addr2rsc_calc_error => sig_addr2rsc_calc_error ,
addr2rsc_fifo_empty => sig_addr2rsc_cmd_fifo_empty ,
data2rsc_tag => sig_rdc2rsc_tag ,
data2rsc_calc_error => sig_rdc2rsc_calc_err ,
data2rsc_okay => sig_rdc2rsc_okay ,
data2rsc_decerr => sig_rdc2rsc_decerr ,
data2rsc_slverr => sig_rdc2rsc_slverr ,
data2rsc_cmd_cmplt => sig_rdc2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2rdc_ready ,
data2rsc_valid => sig_rdc2rsc_valid ,
rsc2stat_status => sig_rsc2stat_status ,
stat2rsc_status_ready => sig_stat2rsc_status_ready ,
rsc2stat_status_valid => sig_rsc2stat_status_valid ,
rsc2mstr_halt_pipe => sig_rsc2rdc_halt_pipe
);
------------------------------------------------------------
-- Instance: I_READ_STREAM_SKID_BUF
--
-- Description:
-- Instance for the Read side Skid Buffer which provides
-- for registerd Master Stream outputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
I_READ_STREAM_SKID_BUF : entity axi_master_burst_v2_0.axi_master_burst_skid_buf
generic map (
C_WDATA_WIDTH => RDWR_SDATA_WIDTH
)
port map (
-- System Ports
aclk => rdwr_aclk ,
arst => rdwr_areset ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => sig_rdc2skid_halt ,
-- Slave Side (Stream Data Input)
s_valid => sig_rdc2rdskid_tvalid ,
s_ready => sig_rdskid2rdc_tready ,
s_data => sig_rdc2rdskid_tdata ,
s_strb => sig_rdc2rdskid_tstrb ,
s_last => sig_rdc2rdskid_tlast ,
-- Master Side (Stream Data Output
m_valid => sig_rdskid2strm_tvalid ,
m_ready => sig_strm2rdskid_tready ,
m_data => sig_rdskid2strm_tdata ,
m_strb => sig_rdskid2strm_tstrb ,
m_last => sig_rdskid2strm_tlast
);
-------------------------------------------------------------------------
-- Write Data Controller Logic
-------------------------------------------------------------------------
sig_wdc_stbs_asserted <= (others => '0');
sig_realign2wdc_eop_error <= '0';
------------------------------------------------------------
-- Instance: I_WR_DATA_CNTL
--
-- Description:
-- Write Data Controller Block
--
------------------------------------------------------------
I_WR_DATA_CNTL : entity axi_master_burst_v2_0.axi_master_burst_wrdata_cntl
generic map (
C_REALIGNER_INCLUDED => OMIT_DRE ,
C_ENABLE_STORE_FORWARD => OMIT_STORE_FORWARD ,
C_SF_BYTES_RCVD_WIDTH => WSC_BYTES_RCVD_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => WR_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => RDWR_MDATA_WIDTH ,
C_STREAM_DWIDTH => RDWR_SDATA_WIDTH ,
C_TAG_WIDTH => RDWR_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => rdwr_aclk ,
mmap_reset => rdwr_areset ,
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_wdc2addr_stop_req ,
data2rst_stop_cmplt => open ,
wr_xfer_cmplt => sig_wr_xfer_cmplt ,
s2mm_ld_nxt_len => open ,
s2mm_wr_len => open ,
data2skid_saddr_lsb => sig_wdc2wrskid_addr_lsb ,
data2skid_wdata => sig_wdc2wrskid_wdata ,
data2skid_wstrb => sig_wdc2wrskid_wstrb ,
data2skid_wlast => sig_wdc2wrskid_wlast ,
data2skid_wvalid => sig_wdc2wrskid_wvalid ,
skid2data_wready => sig_wrskid2wdc_wready ,
s2mm_strm_wvalid => sig_wrskid2wdc_tvalid ,
s2mm_strm_wready => sig_wdc2wrskid_tready ,
s2mm_strm_wdata => sig_wrskid2wdc_tdata ,
s2mm_strm_wstrb => sig_wrskid2wdc_tstrb ,
s2mm_strm_wlast => sig_wrskid2wdc_tlast ,
s2mm_strm_eop => sig_wrskid2wdc_tlast ,
s2mm_stbs_asserted => sig_wdc_stbs_asserted ,
realign2wdc_eop_error => sig_realign2wdc_eop_error ,
mstr2data_tag => sig_pcc2data_tag ,
mstr2data_saddr_lsb => sig_pcc2data_saddr_lsb ,
mstr2data_len => sig_pcc2data_len ,
mstr2data_strt_strb => sig_pcc2data_strt_strb ,
mstr2data_last_strb => sig_pcc2data_last_strb ,
mstr2data_drr => sig_pcc2data_drr ,
mstr2data_eof => sig_pcc2data_eof ,
mstr2data_sequential => sig_pcc2data_sequential ,
mstr2data_calc_error => sig_pcc2data_calc_error ,
mstr2data_cmd_cmplt => sig_pcc2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_pcc2wdc_cmd_valid ,
data2mstr_cmd_ready => sig_wdc2pcc_cmd_ready ,
addr2data_addr_posted => sig_addr2wdc_addr_posted ,
data2addr_data_rdy => open ,
data2all_tlast_error => open ,
data2all_dcntlr_halted => open ,
data2skid_halt => sig_wdc2skid_halt ,
data2wsc_tag => sig_wdc2wsc_tag ,
data2wsc_calc_err => sig_wdc2wsc_calc_err ,
data2wsc_last_err => sig_wdc2wsc_last_err ,
data2wsc_cmd_cmplt => sig_wdc2wsc_cmd_cmplt ,
wsc2data_ready => sig_wsc2wdc_ready ,
data2wsc_valid => sig_wdc2wsc_valid ,
data2wsc_eop => sig_wdc2wsc_eop ,
data2wsc_bytes_rcvd => sig_wdc2wsc_bytes_rcvd ,
wsc2mstr_halt_pipe => sig_wsc2wdc_halt_pipe
);
------------------------------------------------------------
-- Instance: I_WR_STATUS_CNTLR
--
-- Description:
-- Write Status Controller Block
--
------------------------------------------------------------
I_WR_STATUS_CNTLR : entity axi_master_burst_v2_0.axi_master_burst_wr_status_cntl
generic map (
C_ENABLE_STORE_FORWARD => OMIT_STORE_FORWARD ,
C_SF_BYTES_RCVD_WIDTH => WSC_BYTES_RCVD_WIDTH ,
C_STS_FIFO_DEPTH => WR_STATUS_CNTL_FIFO_DEPTH ,
C_STS_WIDTH => RDWR_STS_WIDTH ,
C_TAG_WIDTH => RDWR_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => rdwr_aclk ,
mmap_reset => rdwr_areset ,
rst2wsc_stop_request => sig_rst2all_stop_request ,
wsc2rst_stop_cmplt => open ,
addr2wsc_addr_posted => sig_addr2wdc_addr_posted,
s2mm_bresp => sig_axi2wsc_bresp ,
s2mm_bvalid => sig_axi2wsc_bvalid ,
s2mm_bready => sig_wsc2axi_bready ,
calc2wsc_calc_error => sig_pcc2all_calc_err ,
addr2wsc_calc_error => sig_addr2wsc_calc_error ,
addr2wsc_fifo_empty => sig_addr2wsc_cmd_fifo_empty ,
data2wsc_tag => sig_wdc2wsc_tag ,
data2wsc_calc_error => sig_wdc2wsc_calc_err ,
data2wsc_last_error => sig_wdc2wsc_last_err ,
data2wsc_cmd_cmplt => sig_wdc2wsc_cmd_cmplt ,
data2wsc_valid => sig_wdc2wsc_valid ,
wsc2data_ready => sig_wsc2wdc_ready ,
data2wsc_eop => sig_wdc2wsc_eop ,
data2wsc_bytes_rcvd => sig_wdc2wsc_bytes_rcvd ,
wsc2stat_status => sig_wsc2stat_status ,
stat2wsc_status_ready => sig_stat2wsc_status_ready ,
wsc2stat_status_valid => sig_wsc2stat_status_valid ,
wsc2mstr_halt_pipe => sig_wsc2wdc_halt_pipe
);
------------------------------------------------------------
-- Instance: I_WRITE_MMAP_SKID_BUF
--
-- Description:
-- Instance for the S2MM Skid Buffer which provides for
-- registered outputs and supports bi-dir throttling.
--
-- This Module also provides Write Data Bus Mirroring and WSTRB
-- Demuxing to match a narrow Stream to a wider MMap Write
-- Channel. By doing this in the skid buffer, the resource
-- utilization of the skid buffer can be minimized by only
-- having to buffer/mux the Stream data width, not the MMap
-- Data width.
--
------------------------------------------------------------
I_WRITE_MMAP_SKID_BUF : entity axi_master_burst_v2_0.axi_master_burst_skid2mm_buf
generic map (
C_MDATA_WIDTH => RDWR_MDATA_WIDTH ,
C_SDATA_WIDTH => RDWR_SDATA_WIDTH ,
C_ADDR_LSB_WIDTH => SEL_ADDR_WIDTH
)
port map (
-- System Ports
ACLK => rdwr_aclk ,
ARST => rdwr_areset ,
-- Slave Side (Wr Data Controller Input Side )
S_ADDR_LSB => sig_wdc2wrskid_addr_lsb,
S_VALID => sig_wdc2wrskid_wvalid ,
S_READY => sig_wrskid2wdc_wready ,
S_Data => sig_wdc2wrskid_wdata ,
S_STRB => sig_wdc2wrskid_wstrb ,
S_Last => sig_wdc2wrskid_wlast ,
-- Master Side (MMap Write Data Output Side)
M_VALID => sig_wrskid2axi_wvalid ,
M_READY => sig_axi2wrskid_wready ,
M_Data => sig_wrskid2axi_wdata ,
M_STRB => sig_wrskid2axi_wstrb ,
M_Last => sig_wrskid2axi_wlast
);
------------------------------------------------------------
-- Instance: I_WRITE_STRM_SKID_BUF
--
-- Description:
-- Instance for the Write Stream Input Skid Buffer which
-- provides for registerd Slave Stream inputs and supports
-- bi-dir throttling.
--
------------------------------------------------------------
I_WRITE_STRM_SKID_BUF : entity axi_master_burst_v2_0.axi_master_burst_skid_buf
generic map (
C_WDATA_WIDTH => RDWR_SDATA_WIDTH
)
port map (
-- System Ports
aclk => rdwr_aclk ,
arst => rdwr_areset ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => sig_wdc2skid_halt ,
-- Slave Side (Stream Data Input)
s_valid => sig_strm2wrskid_tvalid ,
s_ready => sig_wrskid2strm_tready ,
s_data => sig_strm2wrskid_tdata ,
s_strb => sig_strm2wrskid_tstrb ,
s_last => sig_strm2wrskid_tlast ,
-- Master Side (Stream Data Output)
m_valid => sig_wrskid2wdc_tvalid ,
m_ready => sig_wdc2wrskid_tready ,
m_data => sig_wrskid2wdc_tdata ,
m_strb => sig_wrskid2wdc_tstrb ,
m_last => sig_wrskid2wdc_tlast
);
end implementation;
| apache-2.0 | a134ab67fa47114730c633b66042ece0 | 0.467603 | 3.979383 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/axi_master_burst_v2_0/1af76933/hdl/src/vhdl/axi_master_burst_rddata_cntl.vhd | 1 | 60,335 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- Filename: axi_master_burst_rddata_cntl.vhd
--
-- Description:
-- This file implements the AXI Master Burst Read Data Controller module.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_master_burst_rddata_cntl.vhd
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.0$
-- Date: $1/19/2011$
--
-- History:
--
-- DET 1/19/2011 Initial
-- ~~~~~~
-- - Adapted from DataMover v2_00_a axi_datamover_rddata_cntl.vhd
-- ^^^^^^
--
-- DET 1/19/2011 Initial
-- ~~~~~~
-- -- See CR590244 for DataMover
-- - Added additional check on the pop of the status coelscing register.
-- THis is needed to handle the case of a simultaneous push and pop of
-- the coelescing register.
-- ^^^^^^
--
-- DET 2/15/2011 Initial for EDk 13.2
-- ~~~~~~
-- -- Per CR593812
-- - Modifications to remove unused features to improve Code coverage.
-- Used "-- coverage off" and "-- coverage on" strings.
-- ^^^^^^
-- ~~~~~~
-- Fixed CR #688186
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI MASTER BURST to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_master_burst_v2_0;
use axi_master_burst_v2_0.axi_master_burst_rdmux;
use axi_master_burst_v2_0.axi_master_burst_fifo;
-------------------------------------------------------------------------------
entity axi_master_burst_rddata_cntl is
generic (
C_INCLUDE_DRE : Integer range 0 to 1 := 0;
C_ALIGN_WIDTH : Integer range 1 to 3 := 3;
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
C_DATA_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 4;
C_MMAP_DWIDTH : Integer range 32 to 256 := 32;
C_STREAM_DWIDTH : Integer range 8 to 256 := 32;
C_TAG_WIDTH : Integer range 1 to 8 := 4;
C_FAMILY : String := "virtex7"
);
port (
-- Clock input
primary_aclk : in std_logic;
-- Primary synchronization clock for the Master side
-- interface and internal logic. It is also used
-- for the User interface synchronization when
-- C_STSCMD_IS_ASYNC = 0.
-- Reset input
mmap_reset : in std_logic;
-- Reset used for the internal master logic
-- Soft Shutdown internal interface ---------------------------
rst2data_stop_request : in std_logic;
-- Active high soft stop request to modules
data2addr_stop_req : Out std_logic;
-- Active high signal requesting the Address Controller
-- to stop posting commands to the AXI Read Address Channel
data2rst_stop_cmplt : Out std_logic;
-- Active high indication that the Data Controller has completed
-- any pending transfers committed by the Address Controller
-- after a stop has been requested by the Reset module.
-- External Address Pipelining Contol support
mm2s_rd_xfer_cmplt : out std_logic;
-- Active high indication that the Data Controller has completed
-- a single read data transfer on the AXI4 Read Data Channel.
-- This signal escentially echos the assertion of rlast received
-- from the AXI4.
-- AXI Read Data Channel I/O ----------------------------------
mm2s_rdata : In std_logic_vector(C_MMAP_DWIDTH-1 downto 0);
-- AXI Read data input
mm2s_rresp : In std_logic_vector(1 downto 0);
-- AXI Read response input
mm2s_rlast : In std_logic;
-- AXI Read LAST input
mm2s_rvalid : In std_logic;
-- AXI Read VALID input
mm2s_rready : Out std_logic;
-- AXI Read data READY output
-- MM2S DRE Control -------------------------------------------
mm2s_dre_new_align : Out std_logic;
-- Active high signal indicating new DRE aligment required
mm2s_dre_use_autodest : Out std_logic;
-- Active high signal indicating to the DRE to use an auto-
-- calculated desination alignment based on the last transfer
mm2s_dre_src_align : Out std_logic_vector(C_ALIGN_WIDTH-1 downto 0);
-- Bit field indicating the byte lane of the first valid data byte
-- being sent to the DRE
mm2s_dre_dest_align : Out std_logic_vector(C_ALIGN_WIDTH-1 downto 0);
-- Bit field indicating the desired byte lane of the first valid data byte
-- to be output by the DRE
mm2s_dre_flush : Out std_logic;
-- Active high signal indicating to the DRE to flush the current
-- contents to the output register in preparation of a new alignment
-- that will be comming on the next transfer input
-- AXI Master Stream ------------------------------------------
mm2s_strm_wvalid : Out std_logic;
-- AXI Stream VALID Output
mm2s_strm_wready : In Std_logic;
-- AXI Stream READY input
mm2s_strm_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0);
-- AXI Stream data output
mm2s_strm_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0);
-- AXI Stream STRB output
mm2s_strm_wlast : Out std_logic;
-- AXI Stream LAST output
-- Command Calculator Interface --------------------------
mstr2data_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- The next command tag
mstr2data_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0);
-- The next command start address LSbs to use for the read data
-- mux (only used if Stream data width is 8 or 16 bits).
mstr2data_len : In std_logic_vector(7 downto 0);
-- The LEN value output to the Address Channel
mstr2data_strt_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0);
-- The starting strobe value to use for the first stream data beat
mstr2data_last_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0);
-- The endiing (LAST) strobe value to use for the last stream
-- data beat
mstr2data_drr : In std_logic;
-- The starting tranfer of a sequence of transfers
mstr2data_eof : In std_logic;
-- The endiing tranfer of a sequence of transfers
mstr2data_sequential : In std_logic;
-- The next sequential tranfer of a sequence of transfers
-- spawned from a single parent command
mstr2data_calc_error : In std_logic;
-- Indication if the next command in the calculation pipe
-- has a calculation error
mstr2data_cmd_cmplt : In std_logic;
-- The indication to the Data Channel that the current
-- sub-command output is the last one compiled from the
-- parent command pulled from the Command FIFO
mstr2data_cmd_valid : In std_logic;
-- The next command valid indication to the Data Channel
-- Controller for the AXI MMap
data2mstr_cmd_ready : Out std_logic ;
-- Indication from the Data Channel Controller that the
-- command is being accepted on the AXI Address Channel
mstr2data_dre_src_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0);
-- The source (input) alignment for the DRE
mstr2data_dre_dest_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0);
-- The destinstion (output) alignment for the DRE
-- Address Controller Interface --------------------------
addr2data_addr_posted : In std_logic ;
-- Indication from the Address Channel Controller to the
-- Data Controller that an address has been posted to the
-- AXI Address Channel
-- Data Controller General Halted Status
data2all_dcntlr_halted : Out std_logic;
-- When asserted, this indicates the data controller has satisfied
-- all pending transfers queued by the Address Controller and is halted.
-- Output Stream Skid Buffer Halt control
data2skid_halt : Out std_logic;
-- The data controller asserts this output for 1 primary clock period
-- The pulse commands the MM2S Stream skid buffer to tun off outputs
-- at the next tlast transmission.
-- Read Status Controller Interface --------------------------
data2rsc_tag : Out std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- The propagated command tag from the Command Calculator
data2rsc_calc_err : Out std_logic ;
-- Indication that the current command out from the Cntl FIFO
-- has a propagated calculation error from the Command Calculator
data2rsc_okay : Out std_logic ;
-- Indication that the AXI Read transfer completed with OK status
data2rsc_decerr : Out std_logic ;
-- Indication that the AXI Read transfer completed with decode error status
data2rsc_slverr : Out std_logic ;
-- Indication that the AXI Read transfer completed with slave error status
data2rsc_cmd_cmplt : Out std_logic ;
-- Indication by the Data Channel Controller that the
-- corresponding status is the last status for a parent command
-- pulled from the command FIFO
rsc2data_ready : in std_logic;
-- Handshake bit from the Read Status Controller Module indicating
-- that the it is ready to accept a new Read status transfer
data2rsc_valid : Out std_logic ;
-- Handshake bit output to the Read Status Controller Module
-- indicating that the Data Controller has valid tag and status
-- indicators to transfer
rsc2mstr_halt_pipe : In std_logic
-- Status Flag indicating the Status Controller needs to stall the command
-- execution pipe due to a Status flow issue or internal error. Generally
-- this will occur if the Status FIFO is not being serviced fast enough to
-- keep ahead of the command execution.
);
end entity axi_master_burst_rddata_cntl;
architecture implementation of axi_master_burst_rddata_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
-- coverage off
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
-- coverage on
end if;
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant OKAY : std_logic_vector(1 downto 0) := "00";
Constant EXOKAY : std_logic_vector(1 downto 0) := "01";
Constant SLVERR : std_logic_vector(1 downto 0) := "10";
Constant DECERR : std_logic_vector(1 downto 0) := "11";
Constant STRM_STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant LEN_OF_ZERO : std_logic_vector(7 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SADDR_LSB_WIDTH : integer := C_SEL_ADDR_WIDTH;
Constant LEN_WIDTH : integer := 8;
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant SOF_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant DRE_ALIGN_WIDTH : integer := C_ALIGN_WIDTH;
Constant DCTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SADDR_LSB_WIDTH + -- LS Address field width
LEN_WIDTH + -- LEN field
STRB_WIDTH + -- Starting Strobe field
STRB_WIDTH + -- Ending Strobe field
SOF_WIDTH + -- SOF Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Calc error flag
CMD_CMPLT_WIDTH + -- Sequential command flag
CALC_ERR_WIDTH + -- Command Complete Flag
DRE_ALIGN_WIDTH + -- DRE Source Align width
DRE_ALIGN_WIDTH ; -- DRE Dest Align width
-- Caution, the INDEX calculations are order dependent so don't rearrange
Constant TAG_STRT_INDEX : integer := 0;
Constant SADDR_LSB_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant LEN_STRT_INDEX : integer := SADDR_LSB_STRT_INDEX + SADDR_LSB_WIDTH;
Constant STRT_STRB_STRT_INDEX : integer := LEN_STRT_INDEX + LEN_WIDTH;
Constant LAST_STRB_STRT_INDEX : integer := STRT_STRB_STRT_INDEX + STRB_WIDTH;
Constant SOF_STRT_INDEX : integer := LAST_STRB_STRT_INDEX + STRB_WIDTH;
Constant EOF_STRT_INDEX : integer := SOF_STRT_INDEX + SOF_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CMD_CMPLT_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX + SEQUENTIAL_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := CMD_CMPLT_STRT_INDEX + CMD_CMPLT_WIDTH;
Constant DRE_SRC_STRT_INDEX : integer := CALC_ERR_STRT_INDEX + CALC_ERR_WIDTH;
Constant DRE_DEST_STRT_INDEX : integer := DRE_SRC_STRT_INDEX + DRE_ALIGN_WIDTH;
Constant ADDR_INCR_VALUE : integer := C_STREAM_DWIDTH/8;
--Constant ADDR_POSTED_CNTR_WIDTH : integer := 5; -- allows up to 32 entry address queue
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_DATA_CNTL_FIFO_DEPTH);
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_good_dbeat : std_logic := '0';
signal sig_get_next_dqual : std_logic := '0';
signal sig_last_mmap_dbeat : std_logic := '0';
signal sig_last_mmap_dbeat_reg : std_logic := '0';
signal sig_data2mmap_ready : std_logic := '0';
signal sig_mmap2data_valid : std_logic := '0';
signal sig_mmap2data_last : std_logic := '0';
signal sig_aposted_cntr_ready : std_logic := '0';
signal sig_ld_new_cmd : std_logic := '0';
signal sig_ld_new_cmd_reg : std_logic := '0';
signal sig_cmd_cmplt_reg : std_logic := '0';
signal sig_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsb_reg : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted : std_logic := '0';
signal sig_addr_chan_rdy : std_logic := '0';
signal sig_dqual_rdy : std_logic := '0';
signal sig_good_mmap_dbeat : std_logic := '0';
signal sig_first_dbeat : std_logic := '0';
signal sig_last_dbeat : std_logic := '0';
signal sig_new_len_eq_0 : std_logic := '0';
signal sig_dbeat_cntr : unsigned(7 downto 0) := (others => '0');
Signal sig_dbeat_cntr_int : Integer range 0 to 255 := 0;
signal sig_dbeat_cntr_eq_0 : std_logic := '0';
signal sig_dbeat_cntr_eq_1 : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_decerr : std_logic := '0';
signal sig_slverr : std_logic := '0';
signal sig_coelsc_okay_reg : std_logic := '0';
signal sig_coelsc_interr_reg : std_logic := '0';
signal sig_coelsc_decerr_reg : std_logic := '0';
signal sig_coelsc_slverr_reg : std_logic := '0';
signal sig_coelsc_cmd_cmplt_reg : std_logic := '0';
signal sig_coelsc_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_coelsc_reg : std_logic := '0';
signal sig_push_coelsc_reg : std_logic := '0';
signal sig_coelsc_reg_empty : std_logic := '0';
signal sig_coelsc_reg_full : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_cmd_cmplt_last_dbeat : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_eof_reg : std_logic := '0';
signal sig_next_sequential_reg : std_logic := '0';
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_next_calc_error_reg : std_logic := '0';
signal sig_next_dre_src_align_reg : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_next_dre_dest_align_reg : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_dqual_reg : std_logic := '0';
signal sig_push_dqual_reg : std_logic := '0';
signal sig_dqual_reg_empty : std_logic := '0';
signal sig_dqual_reg_full : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_ls_addr_cntr : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_ls_addr_cntr : std_logic := '0';
signal sig_addr_incr_unsgnd : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_no_posted_cmds : std_logic := '0';
Signal sig_cmd_fifo_data_in : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0);
Signal sig_cmd_fifo_data_out : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0);
signal sig_fifo_next_tag : std_logic_vector(TAG_WIDTH-1 downto 0);
signal sig_fifo_next_sadddr_lsb : std_logic_vector(SADDR_LSB_WIDTH-1 downto 0);
signal sig_fifo_next_len : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_fifo_next_strt_strb : std_logic_vector(STRB_WIDTH-1 downto 0);
signal sig_fifo_next_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0);
signal sig_fifo_next_drr : std_logic := '0';
signal sig_fifo_next_eof : std_logic := '0';
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_next_calc_error : std_logic := '0';
signal sig_fifo_next_sequential : std_logic := '0';
signal sig_fifo_next_dre_src_align : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_dre_dest_align : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_fifo_empty : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_sequential_push : std_logic := '0';
signal sig_clr_dqual_reg : std_logic := '0';
signal sig_advance_pipe : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_rd_xfer_cmplt : std_logic := '0';
begin --(architecture implementation)
-- AXI MMap Data Channel Port assignments
mm2s_rready <= sig_data2mmap_ready;
sig_mmap2data_valid <= mm2s_rvalid ;
sig_mmap2data_last <= mm2s_rlast and
mm2s_rvalid ;--Added to FIX CR#688186 -- 19-11-2012
-- Read Status Block interface
data2rsc_valid <= sig_coelsc_reg_full ;
sig_rsc2data_ready <= rsc2data_ready ;
data2rsc_tag <= sig_coelsc_tag_reg ;
data2rsc_calc_err <= sig_coelsc_interr_reg ;
data2rsc_okay <= sig_coelsc_okay_reg ;
data2rsc_decerr <= sig_coelsc_decerr_reg ;
data2rsc_slverr <= sig_coelsc_slverr_reg ;
data2rsc_cmd_cmplt <= sig_coelsc_cmd_cmplt_reg ;
-- AXI MM2S Stream Channel Port assignments
mm2s_strm_wvalid <= (mm2s_rvalid and
sig_advance_pipe) or
(sig_halt_reg and -- Force tvalid high on a Halt and
sig_dqual_reg_full and -- a transfer is scheduled and
not(sig_no_posted_cmds) and -- there are cmds posted to AXi and
not(sig_calc_error_reg)); -- not a calc error
mm2s_strm_wlast <= (mm2s_rlast and
mm2s_rvalid and --Added to FIX CR#688186 -- 19-11-2012
sig_next_eof_reg) or
(sig_halt_reg and -- Force tvalid high on a Halt and
sig_dqual_reg_full and -- a transfer is scheduled and
not(sig_no_posted_cmds) and -- there are cmds posted to AXi and
not(sig_calc_error_reg)); -- not a calc error;
-- Generate the Write Strobes for the Stream interface
mm2s_strm_wstrb <= (others => '1')
When (sig_halt_reg = '1') -- Force tstrb high on a Halt
else sig_strt_strb_reg
When (sig_first_dbeat = '1')
Else sig_last_strb_reg
When (sig_last_dbeat = '1')
Else (others => '1');
-- Address Channel Controller synchro pulse input
sig_addr_posted <= addr2data_addr_posted;
-- Request to halt the Address Channel Controller
data2addr_stop_req <= sig_halt_reg;
-- Halted flag to the reset module
data2rst_stop_cmplt <= (sig_halt_reg_dly3 and -- Normal Mode shutdown
sig_no_posted_cmds and
not(sig_calc_error_reg)) or
(sig_halt_reg_dly3 and -- Shutdown after error trap
sig_calc_error_reg);
-- Read Transfer Completed Status output
mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt;
-- Internal logic ------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RD_CMPLT_FLAG
--
-- Process Description:
-- Implements the status flag indicating that a read data
-- transfer has completed. This is an echo of a rlast assertion
-- and a qualified data beat on the AXI4 Read Data Channel
-- inputs.
--
-------------------------------------------------------------
IMP_RD_CMPLT_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_rd_xfer_cmplt <= '0';
else
sig_rd_xfer_cmplt <= sig_mmap2data_last and
sig_good_mmap_dbeat;
end if;
end if;
end process IMP_RD_CMPLT_FLAG;
-- General flag for advancing the MMap Read and the Stream
-- data pipelines
sig_advance_pipe <= sig_addr_chan_rdy and
sig_dqual_rdy and
not(sig_coelsc_reg_full) and -- new status back-pressure term
not(sig_calc_error_reg);
-- test for Kevin's status throttle case
sig_data2mmap_ready <= (mm2s_strm_wready or
sig_halt_reg) and -- Ignore the Stream ready on a Halt request
sig_advance_pipe;
sig_good_mmap_dbeat <= sig_data2mmap_ready and
sig_mmap2data_valid;
sig_last_mmap_dbeat <= sig_good_mmap_dbeat and
sig_mmap2data_last;
sig_get_next_dqual <= sig_last_mmap_dbeat;
------------------------------------------------------------
-- Instance: I_READ_MUX
--
-- Description:
-- Instance of the MM2S Read Data Channel Read Mux
--
------------------------------------------------------------
I_READ_MUX : entity axi_master_burst_v2_0.axi_master_burst_rdmux
generic map (
C_SEL_ADDR_WIDTH => C_SEL_ADDR_WIDTH, -- : Integer range 1 to 32 := 5;
C_MMAP_DWIDTH => C_MMAP_DWIDTH , -- : Integer range 32 to 256 := 32;
C_STREAM_DWIDTH => C_STREAM_DWIDTH -- : Integer range 8 to 256 := 32
)
port map (
mmap_read_data_in => mm2s_rdata , -- : In std_logic_vector(C_MMAP_DWIDTH-1 downto 0);
mux_data_out => mm2s_strm_wdata , -- : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0);
mstr2data_saddr_lsb => sig_addr_lsb_reg -- : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0)
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_LAST_DBEAT
--
-- Process Description:
-- This implements a FLOP that creates a pulse
-- indicating the LAST signal for an incoming read data channel
-- has been received. Note that it is possible to have back to
-- back LAST databeats.
--
-------------------------------------------------------------
REG_LAST_DBEAT : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_last_mmap_dbeat_reg <= '0';
else
sig_last_mmap_dbeat_reg <= sig_last_mmap_dbeat;
end if;
end if;
end process REG_LAST_DBEAT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Omits the input data control FIFO if the requested FIFO
-- depth is 1. The Data Qualifier Register serves as a
-- 1 deep FIFO by itself.
--
------------------------------------------------------------
GEN_NO_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH = 1) generate
begin
-- Command Calculator Handshake output
data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_rd_cmd_valid <= mstr2data_cmd_valid ;
-- pre 13.1 sig_fifo_wr_cmd_ready <= sig_dqual_reg_empty and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(rsc2mstr_halt_pipe) and -- The Rd Status Controller is not stalling
-- pre 13.1 not(sig_calc_error_reg); -- the command execution pipe and there is
-- pre 13.1 -- no calculation error being propagated
sig_fifo_wr_cmd_ready <= sig_push_dqual_reg;
sig_fifo_next_tag <= mstr2data_tag ;
sig_fifo_next_sadddr_lsb <= mstr2data_saddr_lsb ;
sig_fifo_next_len <= mstr2data_len ;
sig_fifo_next_strt_strb <= mstr2data_strt_strb ;
sig_fifo_next_last_strb <= mstr2data_last_strb ;
sig_fifo_next_drr <= mstr2data_drr ;
sig_fifo_next_eof <= mstr2data_eof ;
sig_fifo_next_sequential <= mstr2data_sequential ;
sig_fifo_next_cmd_cmplt <= mstr2data_cmd_cmplt ;
sig_fifo_next_calc_error <= mstr2data_calc_error ;
sig_fifo_next_dre_src_align <= mstr2data_dre_src_align ;
sig_fifo_next_dre_dest_align <= mstr2data_dre_dest_align ;
end generate GEN_NO_DATA_CNTL_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Includes the input data control FIFO if the requested
-- FIFO depth is more than 1.
--
------------------------------------------------------------
GEN_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH > 1) generate
begin
-- Command Calculator Handshake output
data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_wr_cmd_valid <= mstr2data_cmd_valid ;
sig_fifo_rd_cmd_ready <= sig_push_dqual_reg; -- pop the fifo when dqual reg is pushed
-- Format the input fifo data word
sig_cmd_fifo_data_in <= mstr2data_dre_dest_align &
mstr2data_dre_src_align &
mstr2data_calc_error &
mstr2data_cmd_cmplt &
mstr2data_sequential &
mstr2data_eof &
mstr2data_drr &
mstr2data_last_strb &
mstr2data_strt_strb &
mstr2data_len &
mstr2data_saddr_lsb &
mstr2data_tag ;
-- Rip the output fifo data word
sig_fifo_next_tag <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto
TAG_STRT_INDEX);
sig_fifo_next_sadddr_lsb <= sig_cmd_fifo_data_out((SADDR_LSB_STRT_INDEX+SADDR_LSB_WIDTH)-1 downto
SADDR_LSB_STRT_INDEX);
sig_fifo_next_len <= sig_cmd_fifo_data_out((LEN_STRT_INDEX+LEN_WIDTH)-1 downto
LEN_STRT_INDEX);
sig_fifo_next_strt_strb <= sig_cmd_fifo_data_out((STRT_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
STRT_STRB_STRT_INDEX);
sig_fifo_next_last_strb <= sig_cmd_fifo_data_out((LAST_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
LAST_STRB_STRT_INDEX);
sig_fifo_next_drr <= sig_cmd_fifo_data_out(SOF_STRT_INDEX);
sig_fifo_next_eof <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
sig_fifo_next_sequential <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
sig_fifo_next_cmd_cmplt <= sig_cmd_fifo_data_out(CMD_CMPLT_STRT_INDEX);
sig_fifo_next_calc_error <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
sig_fifo_next_dre_src_align <= sig_cmd_fifo_data_out((DRE_SRC_STRT_INDEX+DRE_ALIGN_WIDTH)-1 downto
DRE_SRC_STRT_INDEX);
sig_fifo_next_dre_dest_align <= sig_cmd_fifo_data_out((DRE_DEST_STRT_INDEX+DRE_ALIGN_WIDTH)-1 downto
DRE_DEST_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DATA_CNTL_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_FIFO : entity axi_master_burst_v2_0.axi_master_burst_fifo
generic map (
C_DWIDTH => DCTL_FIFO_WIDTH ,
C_DEPTH => C_DATA_CNTL_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_cmd_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_fifo_rd_cmd_ready ,
fifo_rd_tdata => sig_cmd_fifo_data_out ,
fifo_rd_empty => sig_cmd_fifo_empty
);
end generate GEN_DATA_CNTL_FIFO;
-- Data Qualifier Register ------------------------------------
sig_ld_new_cmd <= sig_push_dqual_reg ;
sig_addr_chan_rdy <= not(sig_addr_posted_cntr_eq_0);
sig_dqual_rdy <= sig_dqual_reg_full ;
sig_strt_strb_reg <= sig_next_strt_strb_reg ;
sig_last_strb_reg <= sig_next_last_strb_reg ;
sig_tag_reg <= sig_next_tag_reg ;
sig_cmd_cmplt_reg <= sig_next_cmd_cmplt_reg ;
sig_calc_error_reg <= sig_next_calc_error_reg ;
-- Flag indicating that there are no posted commands to AXI
sig_no_posted_cmds <= sig_addr_posted_cntr_eq_0;
-- new for no bubbles between child requests
sig_sequential_push <= sig_good_mmap_dbeat and -- MMap handshake qualified
sig_last_dbeat and -- last data beat of transfer
sig_next_sequential_reg;-- next queued command is sequential
-- to the current command
-- pre 13.1 sig_push_dqual_reg <= (sig_sequential_push or
-- pre 13.1 sig_dqual_reg_empty) and
-- pre 13.1 sig_fifo_rd_cmd_valid and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(rsc2mstr_halt_pipe); -- The Rd Status Controller is not
-- stalling the command execution pipe
sig_push_dqual_reg <= (sig_sequential_push or
sig_dqual_reg_empty) and
sig_fifo_rd_cmd_valid and
sig_aposted_cntr_ready and
not(sig_calc_error_reg) and -- 13.1 addition => An error has not been propagated
not(rsc2mstr_halt_pipe); -- The Rd Status Controller is not
-- stalling the command execution pipe
sig_pop_dqual_reg <= not(sig_next_calc_error_reg) and
sig_get_next_dqual and
sig_dqual_reg_full ;
-- new for no bubbles between child requests
sig_clr_dqual_reg <= mmap_reset or
(sig_pop_dqual_reg and
not(sig_push_dqual_reg));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DQUAL_REG
--
-- Process Description:
-- This process implements a register for the Data
-- Control and qualifiers. It operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_DQUAL_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_clr_dqual_reg = '1') then
sig_next_tag_reg <= (others => '0');
sig_next_strt_strb_reg <= (others => '0');
sig_next_last_strb_reg <= (others => '0');
sig_next_eof_reg <= '0';
sig_next_cmd_cmplt_reg <= '0';
sig_next_sequential_reg <= '0';
sig_next_calc_error_reg <= '0';
sig_next_dre_src_align_reg <= (others => '0');
sig_next_dre_dest_align_reg <= (others => '0');
sig_dqual_reg_empty <= '1';
sig_dqual_reg_full <= '0';
elsif (sig_push_dqual_reg = '1') then
sig_next_tag_reg <= sig_fifo_next_tag ;
sig_next_strt_strb_reg <= sig_fifo_next_strt_strb ;
sig_next_last_strb_reg <= sig_fifo_next_last_strb ;
sig_next_eof_reg <= sig_fifo_next_eof ;
sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
sig_next_sequential_reg <= sig_fifo_next_sequential ;
sig_next_calc_error_reg <= sig_fifo_next_calc_error ;
sig_next_dre_src_align_reg <= sig_fifo_next_dre_src_align ;
sig_next_dre_dest_align_reg <= sig_fifo_next_dre_dest_align ;
sig_dqual_reg_empty <= '0';
sig_dqual_reg_full <= '1';
else
null; -- don't change state
end if;
end if;
end process IMP_DQUAL_REG;
-- Address LS Cntr logic --------------------------
sig_addr_lsb_reg <= STD_LOGIC_VECTOR(sig_ls_addr_cntr);
sig_addr_incr_unsgnd <= TO_UNSIGNED(ADDR_INCR_VALUE, C_SEL_ADDR_WIDTH);
sig_incr_ls_addr_cntr <= sig_good_mmap_dbeat;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_ADDR_LSB_CNTR
--
-- Process Description:
-- Implements the LS Address Counter used for controlling
-- the Read Data Mux during Burst transfers
--
-------------------------------------------------------------
DO_ADDR_LSB_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_pop_dqual_reg = '1' and
sig_push_dqual_reg = '0')) then -- Clear the Counter
sig_ls_addr_cntr <= (others => '0');
elsif (sig_push_dqual_reg = '1') then -- Load the Counter
sig_ls_addr_cntr <= unsigned(sig_fifo_next_sadddr_lsb);
elsif (sig_incr_ls_addr_cntr = '1') then -- Increment the Counter
sig_ls_addr_cntr <= sig_ls_addr_cntr + sig_addr_incr_unsgnd;
else
null; -- Hold Current value
end if;
end if;
end process DO_ADDR_LSB_CNTR;
----- Address posted Counter logic --------------------------------
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_last_mmap_dbeat_reg ;
sig_aposted_cntr_ready <= not(sig_addr_posted_cntr_max);
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a register for the Address
-- Posted FIFO that operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
------- First/Middle/Last Dbeat detirmination -------------------
sig_new_len_eq_0 <= '1'
When (sig_fifo_next_len = LEN_OF_ZERO)
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_FIRST_MID_LAST
--
-- Process Description:
-- Implements the detection of the First/Mid/Last databeat of
-- a transfer.
--
-------------------------------------------------------------
DO_FIRST_MID_LAST : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
elsif (sig_ld_new_cmd = '1') then
sig_first_dbeat <= not(sig_new_len_eq_0);
sig_last_dbeat <= sig_new_len_eq_0;
Elsif (sig_dbeat_cntr_eq_1 = '1' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '1';
Elsif (sig_dbeat_cntr_eq_0 = '0' and
sig_dbeat_cntr_eq_1 = '0' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
else
null; -- hols current state
end if;
end if;
end process DO_FIRST_MID_LAST;
------- Data Controller Halted Indication -------------------------------
data2all_dcntlr_halted <= sig_no_posted_cmds and
(sig_calc_error_reg or
rst2data_stop_request);
------- Data Beat counter logic -------------------------------
sig_dbeat_cntr_int <= TO_INTEGER(sig_dbeat_cntr);
sig_dbeat_cntr_eq_0 <= '1'
when (sig_dbeat_cntr_int = 0)
Else '0';
sig_dbeat_cntr_eq_1 <= '1'
when (sig_dbeat_cntr_int = 1)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_DBEAT_CNTR
--
-- Process Description:
--
--
-------------------------------------------------------------
DO_DBEAT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_dbeat_cntr <= (others => '0');
elsif (sig_ld_new_cmd = '1') then
sig_dbeat_cntr <= unsigned(sig_fifo_next_len);
Elsif (sig_good_mmap_dbeat = '1' and
sig_dbeat_cntr_eq_0 = '0') Then
sig_dbeat_cntr <= sig_dbeat_cntr-1;
else
null; -- Hold current state
end if;
end if;
end process DO_DBEAT_CNTR;
------ Read Response Status Logic ------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: LD_NEW_CMD_PULSE
--
-- Process Description:
-- Generate a 1 Clock wide pulse when a new command has been
-- loaded into the Command Register
--
-------------------------------------------------------------
LD_NEW_CMD_PULSE : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_ld_new_cmd_reg = '1') then
sig_ld_new_cmd_reg <= '0';
elsif (sig_ld_new_cmd = '1') then
sig_ld_new_cmd_reg <= '1';
else
null; -- hold State
end if;
end if;
end process LD_NEW_CMD_PULSE;
sig_pop_coelsc_reg <= sig_coelsc_reg_full and
sig_rsc2data_ready ;
sig_push_coelsc_reg <= (sig_good_mmap_dbeat and
not(sig_coelsc_reg_full)) or
(sig_ld_new_cmd_reg and
sig_calc_error_reg) ;
sig_cmd_cmplt_last_dbeat <= (sig_cmd_cmplt_reg and sig_mmap2data_last) or
sig_calc_error_reg;
------- Read Response Decode
-- Decode the AXI MMap Read Response
sig_decerr <= '1'
When mm2s_rresp = DECERR
Else '0';
sig_slverr <= '1'
When mm2s_rresp = SLVERR
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: RD_RESP_COELESC_REG
--
-- Process Description:
-- Implement the Read error/status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status Controller.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_pop_coelsc_reg = '1' and -- Added more qualification here for simultaneus
sig_push_coelsc_reg = '0')) then -- push and pop condition per CR590244
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_cmd_cmplt_reg <= '0';
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_tag_reg;
sig_coelsc_cmd_cmplt_reg <= sig_cmd_cmplt_last_dbeat;
sig_coelsc_interr_reg <= sig_calc_error_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= sig_decerr or sig_coelsc_decerr_reg;
sig_coelsc_slverr_reg <= sig_slverr or sig_coelsc_slverr_reg;
sig_coelsc_okay_reg <= not(sig_decerr or
sig_slverr or
sig_calc_error_reg );
sig_coelsc_reg_full <= sig_cmd_cmplt_last_dbeat;
sig_coelsc_reg_empty <= not(sig_cmd_cmplt_last_dbeat);
else
null; -- hold current state
end if;
end if;
end process STATUS_COELESC_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_DRE
--
-- If Generate Description:
-- Ties off DRE Control signals to logic low when DRE is
-- omitted from the MM2S functionality.
--
--
------------------------------------------------------------
GEN_NO_DRE : if (C_INCLUDE_DRE = 0) generate
begin
mm2s_dre_new_align <= '0';
mm2s_dre_use_autodest <= '0';
mm2s_dre_src_align <= (others => '0');
mm2s_dre_dest_align <= (others => '0');
mm2s_dre_flush <= '0';
end generate GEN_NO_DRE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_DRE_CNTLS
--
-- If Generate Description:
-- Implements the DRE Control logic when MM2S DRE is enabled.
--
-- - The DRE needs to have forced alignment at a SOF assertion
--
--
------------------------------------------------------------
GEN_INCLUDE_DRE_CNTLS : if (C_INCLUDE_DRE = 1) generate
-- local signals
signal lsig_s_h_dre_autodest : std_logic := '0';
signal lsig_s_h_dre_new_align : std_logic := '0';
begin
mm2s_dre_new_align <= lsig_s_h_dre_new_align;
-- Autodest is asserted on a new parent command and the
-- previous parent command was not delimited with a EOF
mm2s_dre_use_autodest <= lsig_s_h_dre_autodest;
-- Assign the DRE Source and Destination Alignments
-- Only used when mm2s_dre_new_align is asserted
mm2s_dre_src_align <= sig_next_dre_src_align_reg ;
mm2s_dre_dest_align <= sig_next_dre_dest_align_reg;
-- Assert the Flush flag when the MMap Tlast input of the current transfer is
-- asserted and the next transfer is not sequential and not the last
-- transfer of a packet.
mm2s_dre_flush <= mm2s_rlast and
mm2s_rvalid and --Added to FIX CR#688186 -- 19-11-2012
not(sig_next_sequential_reg) and
not(sig_next_eof_reg);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_S_H_NEW_ALIGN
--
-- Process Description:
-- Generates the new alignment command flag to the DRE.
--
-------------------------------------------------------------
IMP_S_H_NEW_ALIGN : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_s_h_dre_new_align <= '0';
Elsif (sig_push_dqual_reg = '1' and
sig_fifo_next_drr = '1') Then
lsig_s_h_dre_new_align <= '1';
elsif (sig_pop_dqual_reg = '1') then
lsig_s_h_dre_new_align <= sig_next_cmd_cmplt_reg and
not(sig_next_sequential_reg) and
not(sig_next_eof_reg);
Elsif (sig_good_mmap_dbeat = '1') Then
lsig_s_h_dre_new_align <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_S_H_NEW_ALIGN;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_S_H_AUTODEST
--
-- Process Description:
-- Generates the control for the DRE indicating whether the
-- DRE destination alignment should be derived from the write
-- strobe stat of the last completed data-beat to the AXI
-- stream output.
--
-------------------------------------------------------------
IMP_S_H_AUTODEST : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_s_h_dre_autodest <= '0';
Elsif (sig_push_dqual_reg = '1' and
sig_fifo_next_drr = '1') Then
lsig_s_h_dre_autodest <= '0';
elsif (sig_pop_dqual_reg = '1') then
lsig_s_h_dre_autodest <= sig_next_cmd_cmplt_reg and
not(sig_next_sequential_reg) and
not(sig_next_eof_reg);
Elsif (lsig_s_h_dre_new_align = '1' and
sig_good_mmap_dbeat = '1') Then
lsig_s_h_dre_autodest <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_S_H_AUTODEST;
end generate GEN_INCLUDE_DRE_CNTLS;
------- Soft Shutdown Logic -------------------------------
-- Assign the output port skid buf control
data2skid_halt <= sig_data2skid_halt;
-- Create a 1 clock wide pulse to tell the output
-- stream skid buffer to shut down its outputs
sig_data2skid_halt <= sig_halt_reg_dly2 and
not(sig_halt_reg_dly3);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
-- coverage off
elsif (rst2data_stop_request = '1') then
sig_halt_reg <= '1';
-- coverage on
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
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`protect end_protected
| apache-2.0 | 42c1ccda432bf0f787450969fefb3586 | 0.950924 | 1.828716 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/6-FIR2/metaheurísticas/fir2_femo.vhd | 1 | 3,225 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-26.14:51:43)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY fir2_femo_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16: IN unsigned(0 TO 3);
output1: OUT unsigned(0 TO 4));
END fir2_femo_entity;
ARCHITECTURE fir2_femo_description OF fir2_femo_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := not input1 or input1;
register2 := not input2 or input2;
WHEN "00000010" =>
register1 := register2 + register1;
register2 := not input3 or input3;
register3 := not input4 or input4;
register4 := not input5 or input5;
WHEN "00000011" =>
register2 := register2 + register3;
register3 := not input6 or input6;
WHEN "00000100" =>
register2 := register2 * 8;
register1 := register1 * 10;
register5 := not input7 or input7;
register3 := register4 + register3;
register4 := not input8 or input8;
WHEN "00000101" =>
register4 := register4 + register5;
register5 := not input9 or input9;
register6 := not input10 or input10;
WHEN "00000110" =>
register5 := register6 + register5;
register6 := not input11 or input11;
register4 := register4 * 17;
WHEN "00000111" =>
register1 := register1 + register4;
register4 := not input12 or input12;
register5 := register5 * 20;
register3 := register3 * 22;
WHEN "00001000" =>
register4 := register4 + register6;
register6 := not input13 or input13;
register7 := not input14 or input14;
register1 := register3 + register1;
WHEN "00001001" =>
register1 := register2 + register1;
register2 := not input15 or input15;
register3 := register7 + register6;
register6 := not input16 or input16;
register4 := register4 * 28;
WHEN "00001010" =>
register1 := register4 + register1;
WHEN "00001011" =>
register1 := register5 + register1;
register3 := register3 * 30;
register2 := register6 + register2;
WHEN "00001100" =>
register2 := register2 * 32;
register1 := register3 + register1;
WHEN "00001101" =>
register1 := register2 + register1;
WHEN "00001110" =>
output1 <= to_unsigned(2 ** to_integer(register1), 4);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END fir2_femo_description; | gpl-3.0 | 9efe9ee8f46b175e8b3d7542bbee788b | 0.669147 | 3.186759 | false | false | false | false |
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