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witoldo7/puc-2 | PUC/PUC_567/PUC_2/decod.vhd | 2 | 971 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decod is
port (
--wejscie BCD.
bcd : in std_logic_vector(3 downto 0);
-- wyjscie dekodera 8 bit.
segment7 : out std_logic_vector(7 downto 0)
);
end decod;
architecture Behavioral of decod is
begin
process (bcd)
BEGIN
case bcd is
when "0000"=> segment7 <="00000011"; -- '0'
when "0001"=> segment7 <="10011111"; -- '1'
when "0010"=> segment7 <="00100101"; -- '2'
when "0011"=> segment7 <="00001101"; -- '3'
when "0100"=> segment7 <="10011001"; -- '4'
when "0101"=> segment7 <="01001001"; -- '5'
when "0110"=> segment7 <="01000001"; -- '6'
when "0111"=> segment7 <="00011111"; -- '7'
when "1000"=> segment7 <="00000001"; -- '8'
when "1001"=> segment7 <="00001001"; -- '9'
-- stany wyzsze od 9 wygaczaja segement
when others=> segment7 <="11111111";
end case;
end process;
end Behavioral; | gpl-3.0 | f8c6f0bebf3add8187e3919521ff4e0e | 0.610711 | 2.872781 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/prefetch_buffer.vhd | 1 | 18,235 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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| apache-2.0 | 0e45a4d57f8aa3199e7e1169d4888509 | 0.93836 | 1.869106 | false | false | false | false |
freecores/twofish | vhdl/twofish_ecb_vt_testbench_128bits.vhd | 1 | 10,286 | -- Twofish_ecb_vt_testbench_128bits.vhd
-- Copyright (C) 2006 Spyros Ninos
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this library; see the file COPYING. If not, write to:
--
-- Free Software Foundation
-- 59 Temple Place - Suite 330
-- Boston, MA 02111-1307, USA.
--
-- description : this file is the testbench for the VARIABLE TEXT KAT of the twofish cipher with 128 bit key
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_arith.all;
use std.textio.all;
entity vt_testbench128 is
end vt_testbench128;
architecture vt_encryption128_testbench_arch of vt_testbench128 is
component reg128
port (
in_reg128 : in std_logic_vector(127 downto 0);
out_reg128 : out std_logic_vector(127 downto 0);
enable_reg128, reset_reg128, clk_reg128 : in std_logic
);
end component;
component twofish_keysched128
port (
odd_in_tk128,
even_in_tk128 : in std_logic_vector(7 downto 0);
in_key_tk128 : in std_logic_vector(127 downto 0);
out_key_up_tk128,
out_key_down_tk128 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_whit_keysched128
port (
in_key_twk128 : in std_logic_vector(127 downto 0);
out_K0_twk128,
out_K1_twk128,
out_K2_twk128,
out_K3_twk128,
out_K4_twk128,
out_K5_twk128,
out_K6_twk128,
out_K7_twk128 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_encryption_round128
port (
in1_ter128,
in2_ter128,
in3_ter128,
in4_ter128,
in_Sfirst_ter128,
in_Ssecond_ter128,
in_key_up_ter128,
in_key_down_ter128 : in std_logic_vector(31 downto 0);
out1_ter128,
out2_ter128,
out3_ter128,
out4_ter128 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_data_input
port (
in_tdi : in std_logic_vector(127 downto 0);
out_tdi : out std_logic_vector(127 downto 0)
);
end component;
component twofish_data_output
port (
in_tdo : in std_logic_vector(127 downto 0);
out_tdo : out std_logic_vector(127 downto 0)
);
end component;
component demux128
port ( in_demux128 : in std_logic_vector(127 downto 0);
out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0);
selection_demux128 : in std_logic
);
end component;
component mux128
port ( in1_mux128, in2_mux128 : in std_logic_vector(127 downto 0);
selection_mux128 : in std_logic;
out_mux128 : out std_logic_vector(127 downto 0)
);
end component;
component twofish_S128
port (
in_key_ts128 : in std_logic_vector(127 downto 0);
out_Sfirst_ts128,
out_Ssecond_ts128 : out std_logic_vector(31 downto 0)
);
end component;
FILE input_file : text is in "twofish_ecb_vt_testvalues_128bits.txt";
FILE output_file : text is out "twofish_ecb_vt_128bits_results.txt";
-- we create the functions that transform a number to text
-- transforming a signle digit to a character
function digit_to_char(number : integer range 0 to 9) return character is
begin
case number is
when 0 => return '0';
when 1 => return '1';
when 2 => return '2';
when 3 => return '3';
when 4 => return '4';
when 5 => return '5';
when 6 => return '6';
when 7 => return '7';
when 8 => return '8';
when 9 => return '9';
end case;
end;
-- transforming multi-digit number to text
function to_text(int_number : integer range 1 to 129) return string is
variable our_text : string (1 to 3) := (others => ' ');
variable hundreds,
tens,
ones : integer range 0 to 9;
begin
ones := int_number mod 10;
tens := ((int_number mod 100) - ones) / 10;
hundreds := (int_number - (int_number mod 100)) / 100;
our_text(1) := digit_to_char(hundreds);
our_text(2) := digit_to_char(tens);
our_text(3) := digit_to_char(ones);
return our_text;
end;
signal odd_number,
even_number : std_logic_vector(7 downto 0);
signal input_data,
output_data,
twofish_key,
to_encr_reg128,
from_tdi_to_xors,
to_output_whit_xors,
from_xors_to_tdo,
to_mux, to_demux,
from_input_whit_xors,
to_round,
to_input_mux : std_logic_vector(127 downto 0) ;
signal key_up,
key_down,
Sfirst,
Ssecond,
from_xor0,
from_xor1,
from_xor2,
from_xor3,
K0,K1,K2,K3,
K4,K5,K6,K7 : std_logic_vector(31 downto 0);
signal clk : std_logic := '0';
signal mux_selection : std_logic := '0';
signal demux_selection: std_logic := '0';
signal enable_encr_reg : std_logic := '0';
signal reset : std_logic := '0';
signal enable_round_reg : std_logic := '0';
-- begin the testbench arch description
begin
-- getting data to encrypt
data_input: twofish_data_input
port map (
in_tdi => input_data,
out_tdi => from_tdi_to_xors
);
-- producing whitening keys K0..7
the_whitening_step: twofish_whit_keysched128
port map (
in_key_twk128 => twofish_key,
out_K0_twk128 => K0,
out_K1_twk128 => K1,
out_K2_twk128 => K2,
out_K3_twk128 => K3,
out_K4_twk128 => K4,
out_K5_twk128 => K5,
out_K6_twk128 => K6,
out_K7_twk128 => K7
);
-- performing the input whitening XORs
from_xor0 <= K0 XOR from_tdi_to_xors(127 downto 96);
from_xor1 <= K1 XOR from_tdi_to_xors(95 downto 64);
from_xor2 <= K2 XOR from_tdi_to_xors(63 downto 32);
from_xor3 <= K3 XOR from_tdi_to_xors(31 downto 0);
from_input_whit_xors <= from_xor0 & from_xor1 & from_xor2 & from_xor3;
round_reg: reg128
port map ( in_reg128 => from_input_whit_xors,
out_reg128 => to_input_mux,
enable_reg128 => enable_round_reg,
reset_reg128 => reset,
clk_reg128 => clk );
input_mux: mux128
port map ( in1_mux128 => to_input_mux,
in2_mux128 => to_mux,
out_mux128 => to_round,
selection_mux128 => mux_selection
);
-- creating a round
the_keysched_of_the_round: twofish_keysched128
port map (
odd_in_tk128 => odd_number,
even_in_tk128 => even_number,
in_key_tk128 => twofish_key,
out_key_up_tk128 => key_up,
out_key_down_tk128 => key_down
);
producing_the_Skeys: twofish_S128
port map (
in_key_ts128 => twofish_key,
out_Sfirst_ts128 => Sfirst,
out_Ssecond_ts128 => Ssecond
);
the_encryption_circuit: twofish_encryption_round128
port map (
in1_ter128 => to_round(127 downto 96),
in2_ter128 => to_round(95 downto 64),
in3_ter128 => to_round(63 downto 32),
in4_ter128 => to_round(31 downto 0),
in_Sfirst_ter128 => Sfirst,
in_Ssecond_ter128 => Ssecond,
in_key_up_ter128 => key_up,
in_key_down_ter128 => key_down,
out1_ter128 => to_encr_reg128(127 downto 96),
out2_ter128 => to_encr_reg128(95 downto 64),
out3_ter128 => to_encr_reg128(63 downto 32),
out4_ter128 => to_encr_reg128(31 downto 0)
);
encr_reg: reg128
port map ( in_reg128 => to_encr_reg128,
out_reg128 => to_demux,
enable_reg128 => enable_encr_reg,
reset_reg128 => reset,
clk_reg128 => clk );
output_demux: demux128
port map ( in_demux128 => to_demux,
out1_demux128 => to_output_whit_xors,
out2_demux128 => to_mux,
selection_demux128 => demux_selection );
-- don't forget the last swap !!!
from_xors_to_tdo(127 downto 96) <= K4 XOR to_output_whit_xors(63 downto 32);
from_xors_to_tdo(95 downto 64) <= K5 XOR to_output_whit_xors(31 downto 0);
from_xors_to_tdo(63 downto 32) <= K6 XOR to_output_whit_xors(127 downto 96);
from_xors_to_tdo(31 downto 0) <= K7 XOR to_output_whit_xors(95 downto 64);
taking_the_output: twofish_data_output
port map (
in_tdo => from_xors_to_tdo,
out_tdo => output_data
);
-- we create the clock
clk <= not clk after 50 ns; -- period 100 ns
vt_proc: process
variable pt_f, -- plaintext input from file
ct_f : line; -- ciphertext from file
variable pt_v, -- plaintext vector input
ct_v : std_logic_vector(127 downto 0); -- ciphertext vector
variable counter : integer range 1 to 129 := 1; -- counts the encryptions
variable round : integer range 1 to 16 := 1; -- holds the rounds of encryption
begin
-- key stays fixed to zero
twofish_key <= (others => '0');
while not endfile(input_file) loop
readline(input_file, pt_f);
readline(input_file,ct_f);
hread(pt_f,pt_v);
hread(ct_f,ct_v);
input_data <= pt_v;
wait for 25 ns;
reset <= '1';
wait for 50 ns;
reset <= '0';
mux_selection <= '0';
demux_selection <= '1';
enable_encr_reg <= '0';
enable_round_reg <= '0';
wait for 50 ns;
enable_round_reg <= '1';
wait for 50 ns;
enable_round_reg <= '0';
-- the first round
even_number <= "00001000"; -- 8
odd_number <= "00001001"; -- 9
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
demux_selection <= '1';
mux_selection <= '1';
-- the rest 15 rounds
for round in 1 to 15 loop
even_number <= conv_std_logic_vector(((round*2)+8), 8);
odd_number <= conv_std_logic_vector(((round*2)+9), 8);
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
end loop;
-- taking final results
demux_selection <= '0';
wait for 25 ns;
assert (ct_v = output_data) report "file entry and encryption result DO NOT match!!! :( " severity failure;
assert (ct_v /= output_data) report "Encryption I=" & to_text(counter) &" OK" severity note;
counter := counter+1;
hwrite(ct_f,output_data);
hwrite(pt_f,pt_v);
writeline(output_file,pt_f);
writeline(output_file,ct_f);
end loop;
assert false report "***** Variable Text Known Answer Test with 128 bits key size ended succesfully! :) *****" severity failure;
end process vt_proc;
end vt_encryption128_testbench_arch;
| gpl-2.0 | e3af92890ac259f007d96f717ad11c1e | 0.649621 | 2.696906 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/7-FIR1/metaheurísticas/fir1_spea2.vhd | 1 | 3,638 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-26.15:30:48)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY fir1_spea2_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16, input17, input18, input19, input20, input21, input22: IN unsigned(0 TO 3);
output1: OUT unsigned(0 TO 4));
END fir1_spea2_entity;
ARCHITECTURE fir1_spea2_description OF fir1_spea2_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register9: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register10: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register11: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 and input1;
register2 := input2 and input2;
register3 := input3 and input3;
register4 := input4 and input4;
register5 := input5 and input5;
WHEN "00000010" =>
register6 := input6 and input6;
register2 := register3 * register2;
register3 := input7 and input7;
register7 := input8 and input8;
register8 := input9 and input9;
register9 := input10 and input10;
WHEN "00000011" =>
register10 := input11 and input11;
register11 := input12 and input12;
register6 := register7 * register6;
register3 := register3 * register5;
register4 := register4 * register9;
register1 := register8 * register1;
WHEN "00000100" =>
register5 := register10 * register11;
register7 := input13 and input13;
register8 := input14 and input14;
register9 := input15 and input15;
register10 := input16 and input16;
WHEN "00000101" =>
register8 := register8 * register9;
register4 := register6 + register4;
register6 := register10 * register7;
register7 := input17 and input17;
register9 := input18 and input18;
register1 := register1 + register2;
WHEN "00000110" =>
register1 := register1 + register5;
register2 := input19 and input19;
register5 := input20 and input20;
register10 := input21 and input21;
register7 := register7 * register9;
register9 := input22 and input22;
WHEN "00000111" =>
register1 := register8 + register1;
register2 := register10 * register2;
register3 := register3 + register7;
WHEN "00001000" =>
register1 := register3 + register1;
WHEN "00001001" =>
register1 := register1 + register6;
WHEN "00001010" =>
register1 := register4 + register1;
WHEN "00001011" =>
register1 := register1 + register2;
register2 := register9 * register5;
WHEN "00001100" =>
register1 := register2 + register1;
WHEN "00001101" =>
output1 <= register1 and register1;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END fir1_spea2_description; | gpl-3.0 | 5f646d405190a5193caa73cc1e4268fb | 0.681968 | 3.239537 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/mux4.vhd | 1 | 10,822 | `protect begin_protected
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`protect end_protected
| apache-2.0 | 04d97893b4a3e711ccd6b711bace7a6f | 0.925245 | 1.885366 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/axi_master_burst_v2_0/1af76933/hdl/src/vhdl/axi_master_burst_rd_llink.vhd | 1 | 17,302 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- Filename: axi_master_burst_rd_llink.vhd
--
-- Description:
-- THis file implements the Read LocalLink to AXI Stream adapter for the
-- AXI Master burst core.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_master_burst_rd_llink.vhd
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.1 $
-- Date: $1/29/2011$
--
-- History:
-- DET 1/29/2011 Initial Version
--
-- DET 2/11/2011 Initial for EDK 13.2
-- ~~~~~~
-- -- Per CR593485
-- - Modified the Error logic to clear the rdllink_llink_busy assertion
-- when the localLink discontinue completes.
-- - Added logic to complete a Read Discontinue per LocalLink spec after a
-- rdllink_rd_error assertion.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI MASTER BURST to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_master_burst_rd_llink is
generic (
C_NATIVE_DWIDTH : INTEGER range 32 to 128 := 32
-- Set this equal to desred data bus width needed by IPIC
-- LocalLink Data Channels.
);
port (
-------------------------------------------------------------------------
-- Read LocalLink Clock input
-------------------------------------------------------------------------
rdllink_aclk : in std_logic;
-------------------------------------------------------------------------
-- Read LocalLink Reset input
-------------------------------------------------------------------------
rdllink_areset : in std_logic;
-------------------------------------------------------------------------
-- RDWR Cntlr Internal Error Indication
-------------------------------------------------------------------------
rdllink_rd_error : In std_logic;
-------------------------------------------------------------------------
-- LocalLink Enable Control (1 Clock wide pulse)
-------------------------------------------------------------------------
rdllink_llink_enable : In std_logic;
-------------------------------------------------------------------------
-- IPIC LocalLink Busy Flag
-------------------------------------------------------------------------
rdllink_llink_busy : Out std_logic;
-------------------------------------------------------------------------
-- Read Address Posting Contols/Status
-------------------------------------------------------------------------
rdllink_allow_addr_req : Out std_logic; -- Active High enable (1-clk pulse wide)
rdllink_addr_req_posted : In std_logic; -- ignored
rdllink_xfer_cmplt : In std_logic; -- ignored
-------------------------------------------------------------------------
-- Read AXI Master Stream Channel
-------------------------------------------------------------------------
rdllink_strm_tdata : In std_logic_vector(C_NATIVE_DWIDTH-1 downto 0); -- Read AXI Stream
rdllink_strm_tstrb : In std_logic_vector((C_NATIVE_DWIDTH/8)-1 downto 0);-- Read AXI Stream
rdllink_strm_tlast : In std_logic; -- Read AXI Stream
rdllink_strm_tvalid : In std_logic; -- Read AXI Stream
rdllink_strm_tready : Out std_logic; -- Read AXI Stream
-----------------------------------------------------------------------------
-- IPIC Read LocalLink Channel
-----------------------------------------------------------------------------
bus2ip_mstrd_d : out std_logic_vector(0 to C_NATIVE_DWIDTH-1); -- IPIC Read LocalLink
bus2ip_mstrd_rem : out std_logic_vector(0 to (C_NATIVE_DWIDTH/8)-1); -- IPIC Read LocalLink
bus2ip_mstrd_sof_n : Out std_logic; -- IPIC Read LocalLink
bus2ip_mstrd_eof_n : Out std_logic; -- IPIC Read LocalLink
bus2ip_mstrd_src_rdy_n : Out std_logic; -- IPIC Read LocalLink
bus2ip_mstrd_src_dsc_n : Out std_logic; -- IPIC Read LocalLink
ip2bus_mstrd_dst_rdy_n : In std_logic; -- IPIC Read LocalLink
ip2bus_mstrd_dst_dsc_n : In std_logic -- ignored -- IPIC Read LocalLink
);
end entity axi_master_burst_rd_llink;
architecture implementation of axi_master_burst_rd_llink is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Constants
Constant STRB_WIDTH : integer := C_NATIVE_DWIDTH/8;
-- Signals
signal sig_inverted_strbs : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_llink_busy : std_logic := '0';
signal sig_last_debeat_xfered : std_logic := '0';
signal sig_allow_rd_requests : std_logic := '0';
signal sig_debeat_xfered : std_logic := '0';
signal sig_stream_sof : std_logic := '0';
signal sig_set_discontinue : std_logic := '0';
signal sig_rd_error_reg : std_logic := '0';
signal sig_rd_discontinue : std_logic := '0';
signal sig_discontinue_src_rdy : std_logic := '0';
signal sig_discontinue_eof : std_logic := '0';
signal sig_discontinue_cmplt : std_logic := '0';
begin --(architecture implementation)
-------------------------------------------------------------------------
-- LocalLink Port Assignments
-------------------------------------------------------------------------
bus2ip_mstrd_d <= rdllink_strm_tdata ;
bus2ip_mstrd_rem <= sig_inverted_strbs ;
bus2ip_mstrd_sof_n <= not(sig_stream_sof) ;
bus2ip_mstrd_eof_n <= not(rdllink_strm_tlast or
sig_discontinue_eof) ;
bus2ip_mstrd_src_rdy_n <= not(rdllink_strm_tvalid or
sig_discontinue_src_rdy) ;
bus2ip_mstrd_src_dsc_n <= not(sig_discontinue_src_rdy) ;
-------------------------------------------------------------------------
-- Stream Port Assignments
-------------------------------------------------------------------------
rdllink_strm_tready <= Not(ip2bus_mstrd_dst_rdy_n) and
sig_llink_busy;
-------------------------------------------------------------------------
-- Stream Strobes to LLink REM Conversion
-------------------------------------------------------------------------
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_STRBS_INVERT
--
-- Process Description:
-- Inverts the Input Stream Strobe polarity
--
-------------------------------------------------------------
IMP_STRBS_INVERT : process (rdllink_strm_tstrb)
begin
for bit_index in 0 to STRB_WIDTH-1 loop
sig_inverted_strbs(bit_index) <= not(rdllink_strm_tstrb(bit_index));
end loop;
end process IMP_STRBS_INVERT;
-------------------------------------------------------------------------
-- LocalLink Busy Flag logic
-------------------------------------------------------------------------
rdllink_llink_busy <= sig_llink_busy ;
-- Detect the last data beat of the Stream to LocalLink transfer
sig_last_debeat_xfered <= rdllink_strm_tlast and
rdllink_strm_tvalid and
not(ip2bus_mstrd_dst_rdy_n) and
sig_llink_busy ;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LLINK_BUSY_FLOP
--
-- Process Description:
-- Implements the LocalLink Busy Flop
--
-------------------------------------------------------------
IMP_LLINK_BUSY_FLOP : process (rdllink_aclk)
begin
if (rdllink_aclk'event and rdllink_aclk = '1') then
if (rdllink_areset = '1' or
sig_discontinue_cmplt = '1') then
sig_llink_busy <= '0';
elsif (rdllink_llink_enable = '1') then
sig_llink_busy <= '1';
elsif (sig_last_debeat_xfered = '1') then
sig_llink_busy <= '0';
else
null; -- Hold Current State
end if;
end if;
end process IMP_LLINK_BUSY_FLOP;
-------------------------------------------------------------------------
-- LocalLink SOF Flag logic
--
-- Since the input AXI Stream does not have a Start of Frame analog,
-- one must be generated here and inserted in the LocalLink output on
-- the first data beat of the Stream to LocalLink transfer,
-------------------------------------------------------------------------
-- Detect a data beat tranfer between the LocalLink and Stream
sig_debeat_xfered <= rdllink_strm_tvalid and
not(ip2bus_mstrd_dst_rdy_n) and
sig_llink_busy ;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LLINK_SOF_FLOP
--
-- Process Description:
-- Implements the LocalLink SOF Flop. There is no SOF Flag
-- that can be derived from the Stream Input.
--
-------------------------------------------------------------
IMP_LLINK_SOF_FLOP : process (rdllink_aclk)
begin
if (rdllink_aclk'event and rdllink_aclk = '1') then
if (rdllink_areset = '1' or
sig_last_debeat_xfered = '1' or
sig_discontinue_cmplt = '1') then
sig_stream_sof <= '0';
elsif (rdllink_llink_enable = '1') then
sig_stream_sof <= '1';
elsif (sig_debeat_xfered = '1') then
sig_stream_sof <= '0';
else
null; -- Hold Current State
end if;
end if;
end process IMP_LLINK_SOF_FLOP;
-------------------------------------------------------------------------
-- AXI Read Address Posting Control logic
-------------------------------------------------------------------------
rdllink_allow_addr_req <= sig_allow_rd_requests;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ALLOW_RD_REQ_FLOP
--
-- Process Description:
-- Implements the AXI Read Address Request control flop.
-- AXI Read Requests will be withheld from the AXI Read Address
-- Channel until the LocalLink Destination is ready to receive
-- read data.
--
-------------------------------------------------------------
IMP_ALLOW_RD_REQ_FLOP : process (rdllink_aclk)
begin
if (rdllink_aclk'event and rdllink_aclk = '1') then
if (rdllink_areset = '1' or
rdllink_llink_enable = '1') then
sig_allow_rd_requests <= '0';
elsif (ip2bus_mstrd_dst_rdy_n = '0' and
sig_llink_busy = '1') then
sig_allow_rd_requests <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_ALLOW_RD_REQ_FLOP;
-------------------------------------------------------------------------
-- Read Error LLink discontinue logic
-------------------------------------------------------------------------
-- Detect rising edge of the Read Error assertion
sig_set_discontinue <= rdllink_rd_error and
not(sig_rd_error_reg) and
sig_llink_busy ;
-- Force the assertion of the Source ready at Discontinue
sig_discontinue_src_rdy <= sig_rd_discontinue and
sig_llink_busy;
-- Detect Completion of the Read Discontinue
sig_discontinue_cmplt <= sig_rd_discontinue and
sig_discontinue_src_rdy and
Not(ip2bus_mstrd_dst_rdy_n);
-- Must also assert the EOF on a discontinue
sig_discontinue_eof <= sig_discontinue_src_rdy;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RD_ERROR_FLOP
--
-- Process Description:
-- Implements the register for the read discontinue flag.
--
-------------------------------------------------------------
IMP_RD_ERROR_FLOP : process (rdllink_aclk)
begin
if (rdllink_aclk'event and rdllink_aclk = '1') then
if (rdllink_areset = '1') then
sig_rd_error_reg <= '0';
else
sig_rd_error_reg <= rdllink_rd_error;
end if;
end if;
end process IMP_RD_ERROR_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RD_DSC_FLOP
--
-- Process Description:
-- Implements the register for the read discontinue flag.
--
-------------------------------------------------------------
IMP_RD_DSC_FLOP : process (rdllink_aclk)
begin
if (rdllink_aclk'event and rdllink_aclk = '1') then
if (rdllink_areset = '1' or
sig_discontinue_cmplt = '1') then
sig_rd_discontinue <= '0';
elsif (sig_set_discontinue = '1') then
sig_rd_discontinue <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_RD_DSC_FLOP;
end implementation;
| apache-2.0 | e889472c2e191605d031a7d5a87355cd | 0.455265 | 4.974698 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/mdm_v3_1/0d9386c2/hdl/vhdl/bus_master.vhd | 1 | 22,788 | -------------------------------------------------------------------------------
-- $Id$
-------------------------------------------------------------------------------
-- bus_master.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: bus_master.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:
-- bus_master.vhd
-- - srl_fifo
-- - srl_fifo
--
-------------------------------------------------------------------------------
-- Author: stefana
-- Revision: $Revision$
-- Date: $Date$
--
-- History:
-- stefana 2013-11-01 First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity bus_master is
generic (
C_M_AXI_DATA_WIDTH : natural := 32;
C_M_AXI_THREAD_ID_WIDTH : natural := 4;
C_M_AXI_ADDR_WIDTH : natural := 32;
C_DATA_SIZE : natural := 32
);
port (
-- Bus read and write transaction
Rd_Start : in std_logic;
Rd_Addr : in std_logic_vector(31 downto 0);
Rd_Len : in std_logic_vector(4 downto 0);
Rd_Size : in std_logic_vector(1 downto 0);
Rd_Exclusive : in std_logic;
Rd_Idle : out std_logic;
Rd_Response : out std_logic_vector(1 downto 0);
Wr_Start : in std_logic;
Wr_Addr : in std_logic_vector(31 downto 0);
Wr_Len : in std_logic_vector(4 downto 0);
Wr_Size : in std_logic_vector(1 downto 0);
Wr_Exclusive : in std_logic;
Wr_Idle : out std_logic;
Wr_Response : out std_logic_vector(1 downto 0);
-- Bus read and write data
Data_Rd : in std_logic;
Data_Out : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Data_Exists : out std_logic;
Data_Wr : in std_logic;
Data_In : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Data_Empty : out std_logic;
-- LMB bus
LMB_Data_Addr : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe : out std_logic;
LMB_Read_Strobe : out std_logic;
LMB_Write_Strobe : out std_logic;
LMB_Ready : in std_logic;
LMB_Wait : in std_logic;
LMB_UE : in std_logic;
LMB_Byte_Enable : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
-- AXI bus
M_AXI_ACLK : in std_logic;
M_AXI_ARESETn : in std_logic;
M_AXI_AWID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_AWLOCK : out std_logic;
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_AWVALID : out std_logic;
M_AXI_AWREADY : in std_logic;
M_AXI_WLAST : out std_logic;
M_AXI_WDATA : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_WSTRB : out std_logic_vector(C_M_AXI_DATA_WIDTH/8-1 downto 0);
M_AXI_WVALID : out std_logic;
M_AXI_WREADY : in std_logic;
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_BVALID : in std_logic;
M_AXI_BREADY : out std_logic;
M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_ARID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_ARLOCK : out std_logic;
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_ARVALID : out std_logic;
M_AXI_ARREADY : in std_logic;
M_AXI_RLAST : in std_logic;
M_AXI_RID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_RDATA : in std_logic_vector(31 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RVALID : in std_logic;
M_AXI_RREADY : out std_logic
);
end entity bus_master;
library IEEE;
use ieee.numeric_std.all;
library mdm_v3_1;
use mdm_v3_1.all;
architecture IMP of bus_master is
component SRL_FIFO is
generic (
C_DATA_BITS : natural;
C_DEPTH : natural
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Full : out std_logic;
Data_Exists : out std_logic
);
end component SRL_FIFO;
-- Calculate WSTRB given size and low address bits
function Calc_WSTRB (Wr_Size : std_logic_vector(1 downto 0);
Wr_Addr : std_logic_vector(1 downto 0)) return std_logic_vector is
begin
if Wr_Size = "00" then -- Byte
case Wr_Addr is
when "00" => return "0001";
when "01" => return "0010";
when "10" => return "0100";
when "11" => return "1000";
when others => null;
end case;
end if;
if Wr_Size = "01" then -- Halfword
if Wr_Size(1) = '0' then
return "0011";
else
return "1100";
end if;
end if;
return "1111"; -- Word
end function Calc_WSTRB;
type lmb_state_type is (idle, start_rd, wait_rd, start_wr, wait_wr, sample_rd, sample_wr);
type rd_state_type is (idle, start, wait_on_ready, wait_on_data);
type wr_state_type is (idle, start, wait_on_ready, wait_on_bchan);
signal lmb_state : lmb_state_type;
signal rd_state : rd_state_type;
signal wr_state : wr_state_type;
signal reset : std_logic;
signal rdata : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
signal wdata : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
signal wstrb : std_logic_vector(C_M_AXI_DATA_WIDTH/8-1 downto 0);
signal do_read : std_logic;
signal do_write : std_logic;
signal lmb_addr : std_logic_vector(4 downto 0); -- LMB word address
signal lmb_addr_next : std_logic_vector(4 downto 0); -- LMB word address incremented
signal lmb_len : std_logic_vector(4 downto 0); -- LMB length
signal lmb_len_next : std_logic_vector(4 downto 0); -- LMB length decremented
signal lmb_rd_idle : std_logic; -- LMB read is idle
signal lmb_wr_idle : std_logic; -- LMB write is idle
signal lmb_rd_resp : std_logic_vector(1 downto 0); -- LMB read response
signal lmb_wr_resp : std_logic_vector(1 downto 0); -- LMB write response
signal axi_wvalid : std_logic; -- internal M_AXI_WVALID
signal axi_rready : std_logic; -- internal M_AXI_RREADY
signal axi_do_read : std_logic; -- read word from write FIFO for AXI
signal axi_do_write : std_logic; -- write word to read FIFO for AXI
signal axi_rd_start : std_logic; -- LMB did not respond, start AXI read
signal axi_wr_start : std_logic; -- LMB did not respond, start AXI write
signal axi_rd_idle : std_logic; -- AXI read is idle
signal axi_wr_idle : std_logic; -- AXI write is idle
signal axi_rd_resp : std_logic_vector(1 downto 0); -- AXI read response
signal axi_wr_resp : std_logic_vector(1 downto 0); -- AXI write response
signal wdata_exists : std_logic; -- write FIFO has data
begin -- architecture IMP
assert (C_DATA_SIZE = C_M_AXI_DATA_WIDTH)
report "LMB and AXI data widths must be the same" severity FAILURE;
reset <= not M_AXI_ARESETn;
-- Read FIFO instantiation
Read_FIFO : SRL_FIFO
generic map (
C_DATA_BITS => 32,
C_DEPTH => 32
)
port map (
Clk => M_AXI_ACLK,
Reset => reset,
FIFO_Write => do_write,
Data_In => rdata,
FIFO_Read => Data_Rd,
Data_Out => Data_Out,
FIFO_Full => open,
Data_Exists => Data_Exists
);
-- Write FIFO instantiation
Write_FIFO : SRL_FIFO
generic map (
C_DATA_BITS => 32,
C_DEPTH => 32
)
port map (
Clk => M_AXI_ACLK,
Reset => reset,
FIFO_Write => Data_Wr,
Data_In => Data_In,
FIFO_Read => do_read,
Data_Out => wdata,
FIFO_Full => open,
Data_Exists => wdata_exists
);
-- Common signals
Data_Empty <= not wdata_exists;
Rd_Idle <= lmb_rd_idle and axi_rd_idle;
Rd_Response <= lmb_rd_resp or axi_rd_resp;
Wr_Idle <= lmb_wr_idle and axi_wr_idle;
Wr_Response <= lmb_wr_resp or axi_wr_resp;
wstrb <= Calc_WSTRB(Wr_Size, Wr_Addr(1 downto 0));
rdata <= LMB_Data_Read when (LMB_Ready = '1' and lmb_rd_idle = '0') else M_AXI_RDATA;
do_write <= (LMB_Ready and not lmb_rd_idle) or axi_do_write;
do_read <= (LMB_Ready and not lmb_wr_idle) or axi_do_read;
-- LMB implementation
LMB_Data_Addr <= Wr_Addr(C_M_AXI_ADDR_WIDTH-1 downto 7) & lmb_addr & Wr_Addr(1 downto 0);
LMB_Data_Write <= wdata;
LMB_Byte_Enable <= wstrb;
lmb_addr_next <= std_logic_vector(unsigned(lmb_addr) + 1);
lmb_len_next <= std_logic_vector(unsigned(lmb_len) - 1);
LMB_Executing : process (M_AXI_ACLK) is
variable ue : std_logic;
begin -- process LMB_Executing
if (M_AXI_ACLK'event and M_AXI_ACLK = '1') then
if (M_AXI_ARESETn = '0') then
lmb_state <= idle;
axi_rd_start <= '0';
axi_wr_start <= '0';
lmb_addr <= (others => '0');
lmb_rd_idle <= '1';
lmb_wr_idle <= '1';
lmb_len <= (others => '0');
lmb_rd_resp <= "00";
lmb_wr_resp <= "00";
ue := '0';
LMB_Addr_Strobe <= '0';
LMB_Read_Strobe <= '0';
LMB_Write_Strobe <= '0';
else
axi_rd_start <= '0';
axi_wr_start <= '0';
case lmb_state is
when idle =>
lmb_addr <= Wr_Addr(6 downto 2);
lmb_len <= Wr_Len;
lmb_rd_idle <= '1';
lmb_wr_idle <= '1';
ue := '0';
if (Rd_Start = '1') then
lmb_state <= start_rd;
lmb_rd_idle <= '0';
lmb_rd_resp <= "00";
LMB_Addr_Strobe <= '1';
LMB_Read_Strobe <= '1';
end if;
if (Wr_Start = '1') then
lmb_state <= start_wr;
lmb_wr_idle <= '0';
lmb_wr_resp <= "00";
LMB_Addr_Strobe <= '1';
LMB_Write_Strobe <= '1';
end if;
when start_rd =>
lmb_state <= wait_rd;
LMB_Addr_Strobe <= '0';
LMB_Read_Strobe <= '0';
when wait_rd =>
lmb_state <= sample_rd;
when sample_rd =>
if (LMB_Ready = '1') then
if (lmb_len = (lmb_len'range => '0')) then
lmb_state <= idle;
else
lmb_state <= start_rd;
LMB_Addr_Strobe <= '1';
LMB_Read_Strobe <= '1';
end if;
lmb_addr <= lmb_addr_next;
lmb_len <= lmb_len_next;
ue := LMB_UE or ue;
lmb_rd_resp <= ue & '0';
elsif (LMB_Wait = '0') then
lmb_state <= idle;
axi_rd_start <= '1';
end if;
when start_wr =>
lmb_state <= wait_wr;
LMB_Addr_Strobe <= '0';
LMB_Write_Strobe <= '0';
when wait_wr =>
lmb_state <= sample_wr;
when sample_wr =>
if (LMB_Ready = '1') then
if (lmb_len = (lmb_len'range => '0')) then
lmb_state <= idle;
else
lmb_state <= start_wr;
LMB_Addr_Strobe <= '1';
LMB_Write_Strobe <= '1';
end if;
lmb_addr <= lmb_addr_next;
lmb_len <= lmb_len_next;
ue := LMB_UE or ue;
lmb_wr_resp <= ue & '0';
elsif (LMB_Wait = '0') then
lmb_state <= idle;
axi_wr_start <= '1';
end if;
-- coverage off
when others =>
null;
-- coverage on
end case;
end if;
end if;
end process LMB_Executing;
-- AW signals constant values
M_AXI_AWPROT <= "010"; -- Non-secure data accesses only
M_AXI_AWQOS <= "0000"; -- Don't participate in QoS handling
M_AXI_AWID <= (others => '0'); -- ID fixed to zero
M_AXI_AWBURST <= "01"; -- Only INCR bursts
M_AXI_AWCACHE <= "0011"; -- Set "Modifiable" and "Bufferable" bit
-- AR signals constant values
M_AXI_ARPROT <= "010"; -- Normal and non-secure Data access only
M_AXI_ARQOS <= "0000"; -- Don't participate in QoS handling
M_AXI_ARID <= (others => '0'); -- ID fixed to zero
M_AXI_ARBURST <= "01"; -- Only INCR bursts
M_AXI_ARCACHE <= "0011"; -- Set "Modifiable" and "Bufferable" bit
-- R signals constant values
M_AXI_RREADY <= '1'; -- Always accepting read data
-- B signals value
M_AXI_BREADY <= '1' when wr_state = wait_on_bchan else '0';
-- AXI Read FSM
Rd_Executing : process (M_AXI_ACLK) is
variable rd_resp : std_logic_vector(1 downto 0);
begin -- process Rd_Executing
if (M_AXI_ACLK'event and M_AXI_ACLK = '1') then -- rising clock edge
if (M_AXI_ARESETn = '0') then -- synchronous reset (active low)
rd_resp := "00";
axi_rready <= '0';
axi_rd_idle <= '1';
axi_rd_resp <= "00";
M_AXI_ARADDR <= (others => '0');
M_AXI_ARLEN <= (others => '0');
M_AXI_ARSIZE <= "010"; -- 32-bit accesses
M_AXI_ARLOCK <= '0'; -- No locking
M_AXI_ARVALID <= '0';
rd_state <= idle;
else
case rd_state is
when idle =>
rd_resp := "00";
axi_rd_idle <= '1';
if axi_rd_start = '1' then
rd_state <= start;
axi_rd_idle <= '0';
axi_rd_resp <= "00";
end if;
when start =>
M_AXI_ARVALID <= '1';
M_AXI_ARADDR <= Rd_Addr;
M_AXI_ARLEN <= "000" & Rd_Len;
M_AXI_ARSIZE <= "0" & Rd_Size;
M_AXI_ARLOCK <= Rd_Exclusive;
rd_state <= wait_on_ready;
when wait_on_ready =>
if (M_AXI_ARREADY = '1') then
M_AXI_ARVALID <= '0';
axi_rready <= '1';
rd_state <= wait_on_data;
end if;
when wait_on_data =>
if (M_AXI_RVALID = '1') then
if rd_resp = "00" and M_AXI_RRESP /= "00" then
rd_resp := M_AXI_RRESP; -- Sticky error response
end if;
if (M_AXI_RLAST = '1') then
rd_state <= idle;
axi_rd_resp <= rd_resp;
axi_rready <= '0';
end if;
end if;
-- coverage off
when others =>
null;
-- coverage on
end case;
end if;
end if;
end process Rd_Executing;
axi_do_write <= axi_rready and M_AXI_RVALID;
-- AXI Write FSM
Wr_Executing : process (M_AXI_ACLK) is
variable address_done : boolean;
variable data_done : boolean;
variable len : std_logic_vector(4 downto 0);
begin -- process Wr_Executing
if (M_AXI_ACLK'event and M_AXI_ACLK = '1') then -- rising clock edge
if (M_AXI_ARESETn = '0') then -- synchronous reset (active low)
axi_wr_idle <= '1';
axi_wr_resp <= "00";
axi_wvalid <= '0';
M_AXI_WVALID <= '0';
M_AXI_WLAST <= '0';
M_AXI_WSTRB <= (others => '0');
M_AXI_AWADDR <= (others => '0');
M_AXI_AWLEN <= (others => '0');
M_AXI_AWSIZE <= "010"; -- 32-bit accesses
M_AXI_AWLOCK <= '0'; -- No locking
M_AXI_AWVALID <= '0';
address_done := false;
data_done := false;
len := (others => '0');
wr_state <= idle;
else
case wr_state is
when idle =>
axi_wr_idle <= '1';
address_done := false;
data_done := false;
len := (others => '0');
if axi_wr_start = '1' then
wr_state <= start;
axi_wr_idle <= '0';
axi_wr_resp <= "00";
end if;
when start =>
M_AXI_WLAST <= '0';
M_AXI_AWVALID <= '1';
M_AXI_AWADDR <= Wr_Addr;
M_AXI_AWLEN <= "000" & Wr_Len;
M_AXI_AWSIZE <= "0" & Wr_Size;
M_AXI_AWLOCK <= Wr_Exclusive;
axi_wvalid <= '1';
M_AXI_WVALID <= '1';
if Wr_Len = "00000" then
M_AXI_WLAST <= '1';
end if;
M_AXI_WSTRB <= wstrb;
len := Wr_Len;
wr_state <= wait_on_ready;
when wait_on_ready =>
if M_AXI_AWREADY = '1' then
M_AXI_AWVALID <= '0';
address_done := true;
end if;
if M_AXI_WREADY = '1' then
if len = "00000" then
axi_wvalid <= '0';
M_AXI_WVALID <= '0';
data_done := true;
else
if len = "00001" then
M_AXI_WLAST <= '1';
end if;
len := std_logic_vector(unsigned(len) - 1);
end if;
end if;
if (address_done and data_done) then
wr_state <= wait_on_bchan;
end if;
when wait_on_bchan =>
if (M_AXI_BVALID = '1') then
wr_state <= idle;
axi_wr_resp <= M_AXI_BRESP;
end if;
-- coverage off
when others =>
null;
-- coverage on
end case;
end if;
end if;
end process Wr_Executing;
M_AXI_WDATA <= wdata;
axi_do_read <= axi_wvalid and M_AXI_WREADY;
end architecture IMP;
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| apache-2.0 | b84e97dcbfe9eae17b029329de546b08 | 0.942153 | 1.866141 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-30bits_outputs31bits/2-MESA-HB/metaheurísticas/mesahb_hype.vhd | 1 | 2,077 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.10:16:56)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mesahb_hype_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5: IN unsigned(0 TO 30);
output1, output2: OUT unsigned(0 TO 31));
END mesahb_hype_entity;
ARCHITECTURE mesahb_hype_description OF mesahb_hype_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "0000000000000000000000000000000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "0000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
output1 <= input1 + 1;
register1 := input2 * 2;
WHEN "00000010" =>
register2 := input3 * 3;
register1 := register1 + 5;
WHEN "00000011" =>
register1 := ((NOT register1) + 1) XOR register1;
register2 := register2 + 9;
WHEN "00000100" =>
register2 := register2 * 11;
WHEN "00000101" =>
register3 := input4 * 12;
register2 := register2 + 14;
WHEN "00000110" =>
register2 := ((NOT register2) + 1) XOR register2;
register1 := register3 * register1;
WHEN "00000111" =>
register2 := register2 * 18;
WHEN "00001000" =>
register1 := register2 + register1;
register2 := input5 * 19;
WHEN "00001001" =>
register2 := register2 + 21;
WHEN "00001010" =>
register2 := register2 * 23;
WHEN "00001011" =>
register2 := register2 + 25;
WHEN "00001100" =>
output2 <= register1(0 TO 14) & register2(0 TO 15);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mesahb_hype_description; | gpl-3.0 | 162cf56a33ad3a0a0e4578984b0947c4 | 0.669716 | 3.200308 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/address_hit.vhd | 1 | 16,249 | `protect begin_protected
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`protect end_protected
| apache-2.0 | 83d80bbd95376cabb8d01dbf59f5309d | 0.936427 | 1.860431 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-30bits_outputs31bits/1-HAL/asap-alap-random/hal_alap.vhd | 1 | 1,749 | t-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.08:58:01)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY hal_alap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5: IN unsigned(0 TO 30);
output1, output2, output3: OUT unsigned(0 TO 31));
END hal_alap_entity;
ARCHITECTURE hal_alap_description OF hal_alap_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register4: unsigned(0 TO 31) := "0000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
register2 := input2 * 2;
WHEN "00000010" =>
register3 := input3 * 3;
register1 := register2 * register1;
WHEN "00000011" =>
register2 := input4 * 4;
register3 := register3 * 6;
register1 := register1 - 8;
register4 := input5 + 9;
WHEN "00000100" =>
output1 <= register2 + 10;
output2 <= register1 - register3;
IF (register4 < 12) THEN
output3 <= register4;
ELSE
output3 <= "0000000000000000000000000001100";
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END hal_alap_description; | gpl-3.0 | 1716d2c0a560073bf0530c44ba6020e4 | 0.68725 | 3.238889 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/ramfifo/bram_fifo_rstlogic.vhd | 5 | 21,262 | `protect begin_protected
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`protect end_protected
| apache-2.0 | c46659f7ea6d8acf8d2f4003cb5a9277 | 0.941727 | 1.838796 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/ramfifo/rd_bin_cntr.vhd | 5 | 13,156 | `protect begin_protected
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`protect end_protected
| apache-2.0 | 25fab46bb63a69529f5dc8a8eddac7a7 | 0.931818 | 1.87648 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/msr_reg_bit.vhd | 1 | 9,914 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5600)
`protect data_block
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`protect end_protected
| apache-2.0 | 9ff16e9ff03edb329c8eb3885ac0a7de | 0.923643 | 1.906538 | false | false | false | false |
rcls/sdr | test/test_go.vhd | 1 | 1,519 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.all;
entity test_go is
end test_go;
architecture test_go of test_go is
signal usb_c : std_logic_vector(7 downto 0) := "111ZZZ11";
signal reclk_p : std_logic := '0';
signal reclk_n : std_logic;
signal adc_p : std_logic_vector(6 downto 0) := "1000000";
signal adc_n : std_logic_vector(6 downto 0) := "0111111";
begin
reclk_n <= not reclk_p;
adc_n <= not adc_p;
g : entity work.go port map (
adc_p => "0000000",
adc_n => "0000000",
adc_clk_p => open,
adc_clk_n => open,
adc_reclk_p => reclk_p,
adc_reclk_n => reclk_n,
adc_sen => open,
adc_sdata => open,
adc_sclk => open,
adc_reset => open,
audio_scki => open,
audio_lrck => open,
audio_data => open,
audio_bck => open,
audio_pd_inv => open,
audio_demp => open,
usb_d => open,
usb_c => usb_c,
flash_cs_inv => open,
flash_sclk => open,
flash_si => open,
flash_so => '1',
cpu_ssifss => '1',
cpu_ssiclk => '1',
cpu_ssirx => open,
cpu_ssitx => '1',
spartan_m0 => '1',
spartan_m1 => '1',
led => open,
clkin125 => '1',
clkin125_en => open);
process
variable seed1, seed2 : positive := 1;
variable rand : real;
begin
wait for 2ns;
reclk_p <= not reclk_p;
uniform(seed1, seed2, rand);
adc_p <= std_logic_vector(to_unsigned(integer(trunc(rand * 128.0)), 7));
end process;
end;
| gpl-3.0 | fb9713dd70b6c5ae1bc512423aa702a5 | 0.570112 | 2.849906 | false | true | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/ramfifo/rd_handshaking_flags.vhd | 5 | 13,954 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8592)
`protect data_block
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| apache-2.0 | c1baeaaf04cac66f82581dcac141cdf6 | 0.933567 | 1.881861 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/5-EWF/metaheurísticas/ewf_wsga.vhd | 1 | 2,862 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-17.11:31:50)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY ewf_wsga_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2: IN unsigned(0 TO 3);
output1, output2, output3, output4, output5: OUT unsigned(0 TO 4));
END ewf_wsga_entity;
ARCHITECTURE ewf_wsga_description OF ewf_wsga_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
WHEN "00000010" =>
register2 := register1 + 3;
register3 := input2 + 4;
WHEN "00000011" =>
register4 := register2 + 6;
WHEN "00000100" =>
register4 := register3 + register4;
WHEN "00000101" =>
register5 := register4 * 8;
WHEN "00000110" =>
register5 := register2 + register5;
register6 := register4 * 10;
WHEN "00000111" =>
register4 := register4 + register5;
register6 := register3 + register6;
register2 := register2 + register5;
WHEN "00001000" =>
output1 <= register6 + register4;
register3 := register3 + register6;
register2 := register2 * 13;
WHEN "00001001" =>
register3 := register3 * 15;
register2 := register1 + register2;
WHEN "00001010" =>
register3 := register3 + 17;
register1 := register1 + register2;
register4 := register5 + register2;
WHEN "00001011" =>
register4 := register4 + 19;
register5 := register6 + register3;
register1 := register1 * 21;
register6 := register3 + 23;
WHEN "00001100" =>
register6 := register6 * 25;
register5 := register5 + 27;
register1 := register1 + 29;
register7 := register4 * 31;
WHEN "00001101" =>
register8 := register5 * 33;
register7 := register7 + 35;
output2 <= register3 + register6;
output3 <= register2 + register1;
WHEN "00001110" =>
register1 := register8 + 39;
output4 <= register4 + register7;
WHEN "00001111" =>
output5 <= register5 + register1;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END ewf_wsga_description; | gpl-3.0 | 4d1781c07a35d3099ae1e58b461e37c3 | 0.655136 | 3.165929 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/interrupt_mode_converter.vhd | 1 | 10,757 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6224)
`protect data_block
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`protect end_protected
| apache-2.0 | bafcad7d5a8a15237f5b0403cc137792 | 0.924886 | 1.885209 | false | false | false | false |
CyAScott/CIS4930.DatapathSynthesisTool | src/components/gen_AND_bit.vhd | 1 | 506 | library ieee;
use ieee.std_logic_1164.all;
entity gen_AND_bit is
generic
(
width : integer := 4
);
port
(
input : std_logic_vector(width - 1 downto 0);
output : out std_logic
);
end gen_AND_bit;
architecture Behavior of gen_AND_bit is
begin
P0 : process (input)
variable result : std_logic;
begin
result := '1';
L1 : for n in width - 1 downto 0 loop
if input(n) = '0' then
result := '0';
exit L1;
end if;
end loop L1;
output <= result;
end process P0;
end Behavior; | mit | 2c2e578cdac6c8e4f651c563c92c4e54 | 0.634387 | 2.663158 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/byte_doublet_handle_gti.vhd | 1 | 32,370 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 22224)
`protect data_block
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`protect end_protected
| apache-2.0 | ae4537163f9136778b3e10fe5c169c83 | 0.946277 | 1.839414 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/14-MESA-IA/asap-alap-random/mesaia_alap.vhd | 1 | 6,651 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.13:54:59)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mesaia_alap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16, input17, input18, input19, input20, input21, input22, input23, input24, input25, input26, input27, input28, input29, input30, input31, input32, input33, input34, input35, input36, input37, input38, input39, input40, input41, input42, input43, input44, input45, input46, input47, input48: IN unsigned(0 TO 3);
output1, output2, output3, output4: OUT unsigned(0 TO 4));
END mesaia_alap_entity;
ARCHITECTURE mesaia_alap_description OF mesaia_alap_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register9: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register10: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register11: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register12: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register13: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register14: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register15: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register16: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register17: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register18: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
register2 := input2 * 2;
register3 := input3 + 3;
register4 := input4 * 4;
register5 := input5 + 5;
register6 := input6 * 6;
register7 := input7 + 7;
register8 := input8 * 8;
register9 := input9 + 9;
register10 := input10 * 10;
register11 := input11 + 11;
register12 := input12 * 12;
register13 := input13 + 13;
register14 := input14 * 14;
register15 := input15 + 15;
register16 := input16 * 16;
WHEN "00000010" =>
register1 := register2 + register1;
register2 := input17 * 17;
register3 := register4 + register3;
register4 := input18 * 18;
register5 := register6 + register5;
register6 := input19 * 19;
register7 := register8 + register7;
register8 := input20 * 20;
register9 := register10 + register9;
register10 := input21 * 21;
register11 := register12 + register11;
register12 := input22 * 22;
register13 := register14 + register13;
register14 := input23 * 23;
register15 := register16 + register15;
register16 := input24 * 24;
WHEN "00000011" =>
register1 := register2 + register1;
register2 := register4 + register3;
register3 := input25 + 25;
register4 := input26 * 26;
register5 := register6 + register5;
register6 := register8 + register7;
register7 := input27 + 27;
register8 := input28 * 28;
register9 := register10 + register9;
register10 := register12 + register11;
register11 := input29 + 29;
register12 := input30 * 30;
register13 := register14 + register13;
register14 := register16 + register15;
register15 := input31 + 31;
register16 := input32 * 32;
WHEN "00000100" =>
register1 := ((NOT register1) + 1) XOR register1;
register2 := ((NOT register2) + 1) XOR register2;
register3 := register4 + register3;
register4 := input33 * 37;
register5 := ((NOT register5) + 1) XOR register5;
register6 := ((NOT register6) + 1) XOR register6;
register7 := register8 + register7;
register8 := input34 * 42;
register9 := ((NOT register9) + 1) XOR register9;
register10 := ((NOT register10) + 1) XOR register10;
register11 := register12 + register11;
register12 := input35 * 47;
register13 := ((NOT register13) + 1) XOR register13;
register14 := ((NOT register14) + 1) XOR register14;
register15 := register16 + register15;
register16 := input36 * 52;
register17 := input37 + 53;
register18 := input38 * 54;
WHEN "00000101" =>
register1 := register2 - register1;
register2 := register4 + register3;
register3 := input39 + 55;
register4 := input40 * 56;
register5 := register6 - register5;
register6 := register8 + register7;
register7 := input41 + 57;
register8 := input42 * 58;
register9 := register10 - register9;
register10 := register12 + register11;
register11 := input43 + 59;
register12 := input44 * 60;
register13 := register14 - register13;
register14 := register16 + register15;
register15 := register18 + register17;
register16 := input45 * 61;
WHEN "00000110" =>
register1 := register1 * 63;
register2 := ((NOT register2) + 1) XOR register2;
register3 := register4 + register3;
register4 := input46 * 66;
register5 := register5 * 68;
register6 := ((NOT register6) + 1) XOR register6;
register7 := register8 + register7;
register8 := input47 * 71;
register9 := register9 * 73;
register10 := ((NOT register10) + 1) XOR register10;
register11 := register12 + register11;
register12 := input48 * 76;
register13 := register13 * 78;
register14 := ((NOT register14) + 1) XOR register14;
register15 := register16 + register15;
WHEN "00000111" =>
register1 := register2 + register1;
register2 := register4 + register3;
register3 := register6 + register5;
register4 := register8 + register7;
register5 := register10 + register9;
register6 := register12 + register11;
register7 := register14 + register13;
WHEN "00001000" =>
output1 <= register1(0 TO 1) & register15(0 TO 2);
output2 <= register3(0 TO 1) & register2(0 TO 2);
output3 <= register5(0 TO 1) & register4(0 TO 2);
output4 <= register7(0 TO 1) & register6(0 TO 2);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mesaia_alap_description; | gpl-3.0 | 61feb06886156fcee143aacec9940140 | 0.660953 | 3.238072 | false | false | false | false |
scriptum/geany | data/filetypes.vhdl | 22 | 3,042 | # For complete documentation of this file, please see Geany's main documentation
[styling]
# Edit these in the colorscheme .conf file instead
default=default
comment=comment
comment_line_bang=comment_line
block_comment=comment
number=number_1
string=string_1
operator=operator
identifier=identifier_1
stringeol=string_eol
keyword=keyword_1
stdoperator=operator
attribute=attribute
stdfunction=function
stdpackage=preprocessor
stdtype=type
userword=keyword_2
[keywords]
# all items must be in one line
keywords=access after alias all architecture array assert attribute begin block body buffer bus case component configuration constant disconnect downto else elsif end entity exit file for function generate generic group guarded if impure in inertial inout is label library linkage literal loop map new next null of on open others out package port postponed procedure process pure range record register reject report return select severity shared signal subtype then to transport type unaffected units until use variable wait when while with
operators=abs and mod nand nor not or rem rol ror sla sll sra srl xnor xor
attributes=left right low high ascending image value pos val succ pred leftof rightof base range reverse_range length delayed stable quiet transaction event active last_event last_active last_value driving driving_value simple_name path_name instance_name
std_functions=now readline read writeline write endfile resolved to_bit to_bitvector to_stdulogic to_stdlogicvector to_stdulogicvector to_x01 to_x01z to_UX01 rising_edge falling_edge is_x shift_left shift_right rotate_left rotate_right resize to_integer to_unsigned to_signed std_match to_01
std_packages=std ieee work standard textio std_logic_1164 std_logic_arith std_logic_misc std_logic_signed std_logic_textio std_logic_unsigned numeric_bit numeric_std math_complex math_real vital_primitives vital_timing
std_types=boolean bit character severity_level integer real time delay_length natural positive string bit_vector file_open_kind file_open_status line text side width std_ulogic std_ulogic_vector std_logic std_logic_vector X01 X01Z UX01 UX01Z unsigned signed
userwords=
[settings]
# default extension used when saving files
extension=vhd
# MIME type
mime_type=text/x-vhdl
# the following characters are these which a "word" can contains, see documentation
#wordchars=_abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789
# single comments, like # in this file
comment_single=--
# multiline comments
#comment_open=
#comment_close=
# set to false if a comment character/string should start at column 0 of a line, true uses any
# indentation of the line, e.g. setting to true causes the following on pressing CTRL+d
#command_example();
# setting to false would generate this
# command_example();
# This setting works only for single line comments
comment_use_indent=true
# context action command (please see Geany's main documentation for details)
context_action_cmd=
[indentation]
#width=4
# 0 is spaces, 1 is tabs, 2 is tab & spaces
#type=1
| gpl-2.0 | 6f6c3b6f8568a3815b1677d29be69f33 | 0.817554 | 4.105263 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/6-FIR2/metaheurísticas/fir2_wsga.vhd | 1 | 3,226 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-26.14:52:22)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY fir2_wsga_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16: IN unsigned(0 TO 3);
output1: OUT unsigned(0 TO 4));
END fir2_wsga_entity;
ARCHITECTURE fir2_wsga_description OF fir2_wsga_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := not input1 or input1;
register2 := not input2 or input2;
register3 := not input3 or input3;
WHEN "00000010" =>
register2 := register2 + register3;
register3 := not input4 or input4;
register4 := not input5 or input5;
register5 := not input6 or input6;
WHEN "00000011" =>
register3 := register3 + register5;
register5 := not input7 or input7;
register6 := not input8 or input8;
register2 := register2 * 10;
WHEN "00000100" =>
register5 := register5 + register6;
register6 := not input9 or input9;
WHEN "00000101" =>
register4 := register4 + register6;
register6 := not input10 or input10;
WHEN "00000110" =>
register1 := register6 + register1;
register6 := not input11 or input11;
register7 := not input12 or input12;
register4 := register4 * 16;
WHEN "00000111" =>
register6 := register7 + register6;
register7 := not input13 or input13;
register5 := register5 * 19;
register2 := register2 + register4;
register1 := register1 * 21;
WHEN "00001000" =>
register4 := register6 * 23;
register6 := not input14 or input14;
register1 := register1 + register2;
register2 := not input15 or input15;
register3 := register3 * 27;
WHEN "00001001" =>
register1 := register3 + register1;
register3 := not input16 or input16;
register2 := register7 + register2;
WHEN "00001010" =>
register3 := register6 + register3;
register2 := register2 * 30;
register1 := register5 + register1;
WHEN "00001011" =>
register3 := register3 * 32;
register1 := register2 + register1;
WHEN "00001100" =>
register1 := register4 + register1;
WHEN "00001101" =>
register1 := register3 + register1;
WHEN "00001110" =>
output1 <= to_unsigned(2 ** to_integer(register1), 4);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END fir2_wsga_description; | gpl-3.0 | a6576abe2c4a0882f2e6eec2ff4e8b5b | 0.66925 | 3.187747 | false | false | false | false |
witoldo7/puc-2 | PUC/PUC_567/PUC_2/mod10.vhd | 1 | 888 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity mod10 is
Port ( outp : out std_logic_vector(3 downto 0);
dir : in std_logic;
carry: out std_logic;
clr : in std_logic;
clk : in std_logic);
end mod10;
architecture Behavioral of mod10 is
signal temp : std_logic_vector(3 downto 0);
begin
process(clk,clr, dir)
begin
if clr = '1' then
temp<="0000";
carry <= '0';
elsif rising_edge(clk) then
if dir = '1' then
if temp <= "1000" then
temp <= temp+1;
carry <='0';
else
temp <= "0000";
carry <= '1';
end if;
elsif dir = '0' then
if temp >= "0001" then
temp <= temp - 1;
carry <='0';
else
temp <= "1001";
carry <= '1';
end if;
end if;
end if;
outp<=temp;
end process;
end Behavioral; | gpl-3.0 | 9ec1cf6b837a7d9d118f2bbb2474f386 | 0.556306 | 2.837061 | false | false | false | false |
sandrosalvato94/System-Design-Project | src/polito/sdp2017/Tests/CONSTANTS_TEMPLATE.vhd | 2 | 576 | library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package CONSTANTS is
--IMPORTANT: Choose the number of IP cores
constant DATA_WIDTH : integer := 16;
constant ADD_WIDTH : integer := 6;
type data_array is array (0 to NUM_IPS - 1) of std_logic_vector(DATA_WIDTH-1 downto 0);
type add_array is array (0 to NUM_IPS - 1) of std_logic_vector(ADD_WIDTH-1 downto 0);
constant INT_POS : integer := 13;
constant BE_POS : integer := 12;
constant IPADD_POS : integer := 11; -- downto 0
end package CONSTANTS;
--END HERE--
| lgpl-3.0 | 2da98711b56c607f0f5b4dd193c0323d | 0.661458 | 3.113514 | false | false | false | false |
sandrosalvato94/System-Design-Project | src/polito/sdp2017/Tests/profiler.vhd | 1 | 5,146 | ----------------------------------------------------------------------------------
-- Company: Politecnico di Torino
-- Engineer: Alessandro Salvato
--
-- Create Date: 14:32:23 12/06/2016
-- Design Name:
-- Module Name: profiler - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_unsigned.all;
entity profiler is
port ( instruction_code : in STD_LOGIC_VECTOR (5 downto 0); --from execution_logic
count_max : in STD_LOGIC_VECTOR (9 downto 0); --from control logic
target_instr : in STD_LOGIC_VECTOR (5 downto 0); --from control logic
Reset : in STD_LOGIC; --from control logic, it works in asyncronous way
EnableRF : in STD_LOGIC; --from control logic
WriteRF : in STD_LOGIC; --from control logic
Read16RF : in STD_LOGIC; --from control logic
Read32RF : in STD_LOGIC; --from control logic
EnableDump : in STD_LOGIC; --from control logic
clk : in STD_LOGIC; --from the environment
carry_detection : out STD_LOGIC; --to control logic
dump_detection: out std_logic; --to control logic
dump_end: out std_logic; --to control logic
data_out : out STD_LOGIC_VECTOR (31 downto 0)); --to multiplexer
end profiler;
--each control signal is considered active when is high
architecture Behavioral of profiler is
TYPE regfile_type IS ARRAY (0 TO 51) OF std_logic_vector(15 DOWNTO 0);
SIGNAL regfile : regfile_type;
signal count_state: std_logic_vector(9 downto 0); --in place of register
signal target_instr_state: std_logic_vector(5 downto 0); --in place of register
shared variable indice: integer := 0;
--signal RAM_out: std_logic_vector(15 downto 0);
--signal count_out_RAM: std_logic_vector(9 downto 0);
--signal target_instr_out_RAM: std_logic_vector(5 downto 0);
begin
WriteProcess: process(Clk)
variable tmp: std_logic_vector(15 downto 0);
begin
if (clk = '1' and clk'EVENT) then
if(Reset = '1') then
for index in 0 to 51 loop
regfile(index) <= std_logic_vector(to_unsigned(index, 16));
end loop;
dump_detection <= '0';
carry_detection <= '0';
elsif (WriteRF = '1' and EnableRF = '1' and instruction_code /= "ZZZZZZ") then
tmp := regfile(to_integer(unsigned(instruction_code)));
tmp := tmp + std_logic_vector(to_unsigned(64, 16)); -- 10000000
if((tmp(15 downto 6) >= count_state) and (tmp(5 downto 0) = target_instr_state)) then
if(EnableDump = '1') then
dump_detection <= '1';
else
dump_detection <= '0';
end if;
else
if(tmp(15 downto 6) = "0000000000") then -- se dopo la somma il contatore è uguale a zero, allora c'è stato carry
carry_detection <= '1'; -- è indipendente da target_instr, qualsiasi istruzione può esssere soggetta al carry detection
--buffer_out <= "1111111111111111" & tmp;
else
carry_detection <= '0';
end if;
dump_detection <= '0';
--carry_detection <= '0';
end if;
regfile(to_integer(unsigned(instruction_code))) <= tmp;
end if;
end if;
end process;
init: process(reset)
begin
if(reset = '1' and reset'event) then
count_state <= (others => 'Z');
target_instr_state <= (others => 'Z');
--indice := 0;
-- dump_detection <= '0';
-- carry_detection <= '0';
-- dump_end <= '0';
end if;
end process;
write_register: process(count_max, target_instr, reset)
begin
if(reset = '0' and count_max /= "ZZZZZZZZZZ" and target_instr /="ZZZZZZ") then --when reset is deactivated control logic writes the correct values
count_state <= count_max;
target_instr_state <= target_instr;
-- dump_detection <= '0';
-- carry_detection <= '0';
-- dump_end <= '0';
end if;
end process;
--
dump_mode: process(clk, Read32RF)
variable tmp: std_logic_vector(31 downto 0);
begin
if(Read32RF = '1' and EnableRF = '1' and EnableDump = '1' and Reset = '0') then
if(clk = '1' and clk'event) then
if(indice <51) then
tmp(15 downto 0) := regfile(indice);
tmp(31 downto 16) := regfile(indice+1);
data_out <= tmp;
dump_end <= '0';
indice := indice + 2;
else
indice := 0;
tmp(15 downto 0) := regfile(51);
tmp(31 downto 16) := (others => '1');
dump_end <= '1';
end if;
end if;
elsif(reset = '1') then
indice := 0;
end if;
end process;
-- writing_out: process(buffer_out)
-- begin
-- data_out <= buffer_out;
-- end process;
end Behavioral;
| lgpl-3.0 | 10c68a9158b5a94aa160042d9be7f406 | 0.56335 | 3.385526 | false | false | false | false |
sils1297/HWPrak14 | task_2/project_2/project_2.srcs/sources_1/new/LEDPWM.vhd | 1 | 749 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity LEDPWM is
generic (
WIDTH : integer := 7 -- that makes 256 bit combinations
);
Port (
CLK_66MHZ : in std_ulogic;
LED : out std_ulogic_vector(3 downto 0);
duty_cycle : in unsigned(7 downto 0)
);
end LEDPWM;
architecture Behavioral of LEDPWM is
signal counter : unsigned(WIDTH downto 0) := (others => '0');
signal ledstate : std_ulogic := '0';
begin
ledstate <= '1' when duty_cycle > counter else '0';
LED(0) <= ledstate;
LED(1) <= ledstate;
LED(2) <= ledstate;
LED(3) <= ledstate;
counterProcess : process(CLK_66MHZ)
begin
if(rising_edge(CLK_66MHZ)) then
counter <= counter + 1;
end if;
end process;
end Behavioral;
| agpl-3.0 | 3a784feffac2bbaac45605fbe9084878 | 0.648865 | 3.120833 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-30bits_outputs31bits/1-HAL/metaheurísticas/hal_hype.vhd | 1 | 1,623 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.09:05:29)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY hal_hype_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5: IN unsigned(0 TO 30);
output1, output2, output3: OUT unsigned(0 TO 31));
END hal_hype_entity;
ARCHITECTURE hal_hype_description OF hal_hype_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "0000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
register2 := input2 * 2;
WHEN "00000010" =>
output1 <= register2 + 3;
register2 := input3 * 4;
IF (register1 < 5) THEN
output2 <= register1;
ELSE
output2 <= "0000000000000000000000000000101";
END IF;
register1 := input4 * 6;
WHEN "00000011" =>
register1 := register2 * register1;
WHEN "00000100" =>
register1 := register1 - 8;
register2 := input5 * 9;
WHEN "00000101" =>
register2 := register2 * 11;
WHEN "00000110" =>
output3 <= register1 - register2;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END hal_hype_description; | gpl-3.0 | 7dc9f251fad1bc47d49f65997bb82ddd | 0.671596 | 3.127168 | false | false | false | false |
marceloboeira/vhdl-examples | 008-state-machine-calculator/_example/calc_avancada.vhd | 1 | 4,444 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:01:32 06/10/2013
-- Design Name:
-- Module Name: teste_display_e_botao - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
entity calc_avancada is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
bot0 : in STD_LOGIC;
bot1 : in STD_LOGIC;
sw7 : in STD_LOGIC;
sw6 : in STD_LOGIC;
sw5 : in STD_LOGIC;
saida_display : out STD_LOGIC_VECTOR (15 downto 0));
end calc_avancada;
architecture Behavioral of calc_avancada is
type fsm_botao is (inicial, polling, ret_b0, ret_b1, operacao);
signal estado_atual : fsm_botao;
signal num0, num1, resulti: integer range 0 to 255;
signal oper : integer range 0 to 9;
signal result_raiz, resultb, num_raiz : std_logic_vector (7 downto 0);
signal p : std_logic;
begin
fsm_p : process (reset, clock)
begin
if clock'event and clock = '1' then -- Se houve borda de subida do clock então
if reset = '1' then -- se houve reset
estado_atual <= inicial;
else
case estado_atual is
when inicial =>
num0 <= 0;
num1 <= 0;
oper <= 0;
estado_atual <= polling;
when polling =>
if sw5 = '1' then
estado_atual <= operacao;
elsif bot0 = '1' then
estado_atual <= ret_b0;
elsif bot1 = '1' then
estado_atual <= ret_b1;
else
estado_atual <= polling;
end if;
when ret_b0 =>
if bot0 = '1' then
estado_atual <= ret_b0;
else
if sw6 = '0' then
if sw7 = '1' then
num1 <= num1 + 1;
else
num0 <= num0 + 1;
end if;
else
oper <= oper + 1;
end if;
estado_atual <= polling;
end if;
when ret_b1 =>
if bot1 = '1' then
estado_atual <= ret_b1;
else
if sw6 = '0' then
if sw7 = '1' then
num1 <= num1 - 1;
else
num0 <= num0 - 1;
end if;
else
oper <= oper - 1;
end if;
estado_atual <= polling;
end if;
when operacao =>
case oper is
when 1 =>
resultb <= conv_std_logic_vector((num0 + num1), 8);
when 2 =>
resultb <= conv_std_logic_vector((num0 - num1), 8);
when 3 =>
resultb <= conv_std_logic_vector((num0 - num1), 8);
when 4 =>
resultb <= conv_std_logic_vector((num0 * num1), 8);
when 5 =>
resultb <= conv_std_logic_vector(num0, 8) and conv_std_logic_vector(num1, 8);
when 6 =>
resultb <= conv_std_logic_vector(num0, 8) or conv_std_logic_vector(num1, 8);
when 7 =>
resultb <= conv_std_logic_vector(num0, 8) xor conv_std_logic_vector(num1, 8);
when 8 =>
resultb <= not conv_std_logic_vector(num0, 8);
when 9 =>
resultb <= result_raiz;
when others =>
resultb <= (others => 'Z'); -- coloca a saida em alta impedancia
end case;
when others =>
estado_atual <= inicial;
end case;
end if;
end if;
end process;
disp_out_p : process (sw5, sw6, sw7, resultb, num0, num1, oper)
begin
if reset = '1' then
saida_display <= (others => '0');
elsif sw5 = '1' then
saida_display(7 downto 0) <= resultb;
saida_display(15 downto 8) <= (others => '0');
elsif sw6 = '1' then
saida_display(7 downto 0) <= conv_std_logic_vector(oper,8);
saida_display(15 downto 8) <= (others => '0');
elsif sw7 = '1' then
saida_display(7 downto 0) <= conv_std_logic_vector(num1,8);
saida_display(15 downto 8) <= (others => '0');
else
saida_display(7 downto 0) <= conv_std_logic_vector(num0,8);
saida_display(15 downto 8) <= (others => '0');
end if;
end process;
num_raiz <= conv_std_logic_vector(num0,8);
raiz_q : entity work.raiz_quad
port map ( numero => num_raiz,
clock => clock,
reset => reset,
saida => result_raiz,
pronto => p);
end Behavioral;
| mit | e21fa8e990af1fa1c0aef1b056ed2838 | 0.519802 | 3.125176 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/axi_master_burst_v2_0/1af76933/hdl/src/vhdl/axi_master_burst_strb_gen.vhd | 1 | 12,943 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- Filename: axi_master_burst_strb_gen.vhd
--
-- Description:
-- AXI Strobe Generator module.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_master_burst_strb_gen.vhd
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.0 $
-- Date: $1/19/2011$
--
-- History:
-- DET 1/19/2011 Initial
-- ~~~~~~
-- - Adapted from AXI DataMover V2_00_a axi_datamover_strb_gen.vhd
-- ^^^^^^
--
-- DET 2/15/2011 Initial for EDk 13.2
-- ~~~~~~
-- -- Per CR593812
-- - Modifications to remove unused features to improve Code coverage.
-- Used "-- coverage off" and "-- coverage on" strings.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI MASTER BURST to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_master_burst_strb_gen is
generic (
C_ADDR_MODE : Integer := 0; -- 0 = normal, 1 = Address only
C_STRB_WIDTH : Integer := 8; -- number of addr bits needed
C_OFFSET_WIDTH : Integer := 3; -- log2(C_STRB_WIDTH)
C_NUM_BYTES_WIDTH : Integer := 3 -- log2(C_STRB_WIDTH)+1 in normal mode
-- log2(C_STRB_WIDTH) in addr mode
);
port (
start_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); -- Starting address byte offset
num_valid_bytes : In std_logic_vector(C_NUM_BYTES_WIDTH-1 downto 0);-- Number of valid bytes from offset
strb_out : out std_logic_vector(C_STRB_WIDTH-1 downto 0) -- Strobes generated from the inputs
);
end entity axi_master_burst_strb_gen;
architecture implementation of axi_master_burst_strb_gen is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OFFSET_MODE
--
-- If Generate Description:
-- Normal mode strobe generation where a starting address
-- offset is provided and a number of bytes beyond that
-- address that remain.
--
--
------------------------------------------------------------
GEN_OFFSET_MODE : if (C_ADDR_MODE = 0) generate
-- Constants Declarations
Constant INTERNAL_CALC_WIDTH : integer := C_NUM_BYTES_WIDTH+2; -- 2 bits of math headroom
Constant ONE : unsigned := TO_UNSIGNED(1, INTERNAL_CALC_WIDTH);
-- local signals
signal sig_addr_offset_us : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal sig_num_valid_bytes_us : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_offset_bytes_us : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal sig_end_addr_us : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal sig_end_addr_int : integer := 0;
signal sig_strt_addr_int : integer := 0;
signal sig_strb_value : std_logic_vector(C_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_select_value : std_logic_vector(C_STRB_WIDTH-1 downto 0) := (others => '0');
begin
-- assign output
strb_out <= sig_strb_value;
sig_addr_offset_us <= RESIZE(UNSIGNED(start_addr_offset), INTERNAL_CALC_WIDTH);
sig_num_valid_bytes_us <= RESIZE(UNSIGNED(num_valid_bytes) , INTERNAL_CALC_WIDTH);
sig_incr_offset_bytes_us <= sig_num_valid_bytes_us - ONE;
sig_end_addr_us <= sig_addr_offset_us + sig_incr_offset_bytes_us;
sig_strt_addr_int <= TO_INTEGER(sig_addr_offset_us);
sig_end_addr_int <= TO_INTEGER(sig_end_addr_us);
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_STRB_FILL
--
-- Process Description:
-- Fills in the strobes between the start index and end index.
--
-------------------------------------------------------------
IMP_STRB_FILL : process (sig_strt_addr_int,
sig_end_addr_int)
Variable temp_strb : std_logic_vector(C_STRB_WIDTH-1 downto 0) := (others => '0');
Variable strt_offset : Integer := 0;
Variable end_offset : Integer := 0;
begin
-- Establish the Start offset with clipping
-- coverage off
If (sig_strt_addr_int > C_STRB_WIDTH-1) Then
strt_offset := C_STRB_WIDTH-1;
-- coverage on
else
strt_offset := sig_strt_addr_int;
End if;
-- Establish the end offset with clipping
If (sig_end_addr_int > C_STRB_WIDTH-1) Then
end_offset := C_STRB_WIDTH-1;
else
end_offset := sig_end_addr_int;
End if;
-- Set the appropriate strobe bits
for loop_index in 0 to C_STRB_WIDTH-1 loop
If (loop_index >= strt_offset and
loop_index <= end_offset) Then
temp_strb(loop_index) := '1';
Else
temp_strb(loop_index) := '0';
End if;
end loop;
sig_strb_value <= temp_strb;
end process IMP_STRB_FILL;
end generate GEN_OFFSET_MODE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_MODE
--
-- If Generate Description:
-- Address mode strobe generation where a starting address
-- offset is provided and a ending address offset is provided.
--
--
------------------------------------------------------------
GEN_ADDR_MODE : if (C_ADDR_MODE = 1) generate
-- Local Constants Declarations
Constant INTERNAL_CALC_WIDTH : integer := C_NUM_BYTES_WIDTH; -- use math clipping
Constant ONE : unsigned := TO_UNSIGNED(1, INTERNAL_CALC_WIDTH);
-- local signals
signal sig_addr_offset_us : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal sig_num_valid_bytes_us : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_offset_bytes_us : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal sig_end_addr_us : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal sig_end_addr_int : integer := 0;
signal sig_strt_addr_int : integer := 0;
signal sig_strb_value : std_logic_vector(C_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_select_value : std_logic_vector(C_STRB_WIDTH-1 downto 0) := (others => '0');
begin
-- assign output
strb_out <= sig_strb_value;
sig_addr_offset_us <= RESIZE(UNSIGNED(start_addr_offset), INTERNAL_CALC_WIDTH);
sig_num_valid_bytes_us <= RESIZE(UNSIGNED(num_valid_bytes) , INTERNAL_CALC_WIDTH);
sig_incr_offset_bytes_us <= sig_num_valid_bytes_us - ONE;
sig_end_addr_us <= sig_addr_offset_us + sig_incr_offset_bytes_us;
sig_strt_addr_int <= TO_INTEGER(sig_addr_offset_us);
sig_end_addr_int <= TO_INTEGER(sig_end_addr_us);
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_STRB_FILL
--
-- Process Description:
-- Fills in the strobes between the start index and end index.
--
-------------------------------------------------------------
IMP_STRB_FILL : process (sig_strt_addr_int,
sig_end_addr_int)
Variable temp_strb : std_logic_vector(C_STRB_WIDTH-1 downto 0) := (others => '0');
Variable strt_offset : Integer := 0;
Variable end_offset : Integer := 0;
begin
-- Establish the Start offset with clipping
-- coverage off
If (sig_strt_addr_int > C_STRB_WIDTH-1) Then
strt_offset := C_STRB_WIDTH-1;
-- coverage on
else
strt_offset := sig_strt_addr_int;
End if;
-- Establish the end offset with clipping
-- coverage off
If (sig_end_addr_int > C_STRB_WIDTH-1) Then
end_offset := C_STRB_WIDTH-1;
-- coverage on
else
end_offset := sig_end_addr_int;
End if;
-- Set the appropriate strobe bits
for loop_index in 0 to C_STRB_WIDTH-1 loop
If (loop_index >= strt_offset and
loop_index <= end_offset) Then
temp_strb(loop_index) := '1';
Else
temp_strb(loop_index) := '0';
End if;
end loop;
sig_strb_value <= temp_strb;
end process IMP_STRB_FILL;
end generate GEN_ADDR_MODE;
end implementation;
| apache-2.0 | fb40771d002ab25a4bdce655c5a8b8e8 | 0.510624 | 4.452356 | false | false | false | false |
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`protect end_protected
| apache-2.0 | c388d4e450a0165fa4bf1affea57246f | 0.955656 | 1.807634 | false | false | false | false |
BBN-Q/APS2-Comms | src/ip/cpld_bridge/ApsMsgProc_wrapper.vhd | 1 | 10,021 | -- Wrapper around ZRL ApsMsgProc
-- * Prepends rx packets with a fake Ethernet frame header_ct
-- * strips header of tx packets
--
-- Original author: Colm Ryan
-- Copyright 2015,2016 Raytheon BBN Technologies
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.cpld_bridge_pkg.all;
entity ApsMsgProc_wrapper is
generic (
BOARD_TYPE : std_logic_vector(7 downto 0) := x"00" -- x"00" for APS; x"01" for TDM
);
port (
clk : in std_logic;
rst : in std_logic;
--RX and TX to TCP comms.
rx_tdata : in std_logic_vector(7 downto 0);
rx_tvalid : in std_logic;
rx_tready : out std_logic;
rx_tlast : in std_logic;
tx_tdata : out std_logic_vector(7 downto 0);
tx_tvalid : out std_logic;
tx_tready : in std_logic;
tx_tlast : out std_logic;
-- Config Bus Connections
cfg_clk : in std_logic; -- 100 MHZ clock from the Config CPLD
cfgd : inout std_logic_vector(15 downto 0); -- Config Data bus from CPLD
fpga_cmdl : out std_logic; -- Command strobe from FPGA
fpga_rdyl : out std_logic; -- Ready Strobe from FPGA
cfg_rdy : in std_logic; -- Ready to complete current transfer. Connected to CFG_RDWR_B
cfg_err : in std_logic; -- Error during current command. Connecte to CFG_CSI_B
cfg_act : in std_logic; -- Current transaction is complete
stat_oel : out std_logic -- Enable CPLD to drive status onto CFGD
);
end entity;
architecture arch of ApsMsgProc_wrapper is
signal rx_framed_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal rx_framed_tvalid, rx_framed_tready, rx_framed_tlast : std_logic := '0';
signal rx_frame_status_tvalid, rx_frame_padded, rx_frame_truncated : std_logic;
signal rx_frame_length, rx_frame_original_length : unsigned(15 downto 0);
signal rx_msgproc_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal rx_msgproc_tvalid, rx_msgproc_tready, rx_msgproc_tlast : std_logic := '0';
signal tx_msgproc_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal tx_msgproc_tvalid, tx_msgproc_tready, tx_msgproc_tlast : std_logic := '0';
type ethernet_frame_header_t is array(0 to 15) of std_logic_vector(7 downto 0);
constant ethernet_frame_header : ethernet_frame_header_t := (
x"ff", x"ff", x"ff", x"ff", x"ff", x"ff", -- destination MAC address
x"ba", x"ad", x"0d", x"db", x"a1", x"11", -- source MAC address
x"bb", x"4e", --frame type
x"00", x"00" --sequence number
);
type rx_framer_state_t is (IDLE, WRITE_HEADER, WAIT_FOR_LAST, INTERFRAME_GAP);
signal rx_framer_state : rx_framer_state_t;
signal header_tdata : std_logic_vector(7 downto 0);
type tx_deframer_state_t is (IDLE, STRIP_HEADER, WAIT_FOR_LAST);
signal tx_deframer_state : tx_deframer_state_t;
signal nv_data : std_logic_vector(63 downto 0);
signal mac_addr : std_logic_vector(47 downto 0);
signal good_toggle, bad_toggle : std_logic;
begin
--Frame incoming packets with a fake Ethernet frame header
rx_framer : process(clk)
variable header_ct : integer range 0 to ethernet_frame_header'length;
variable ifg_ct : integer range 1 to 12;
begin
if rising_edge(clk) then
if rst = '1' then
rx_framer_state <= IDLE;
header_ct := 0;
ifg_ct := 1;
else
case( rx_framer_state ) is
when IDLE =>
header_ct := 0;
ifg_ct := 1;
--wait for valid to signal start of packet
if rx_tvalid = '1' then
rx_framer_state <= WRITE_HEADER;
end if;
when WRITE_HEADER =>
if rx_framed_tready = '1' then
if header_ct = ethernet_frame_header'length-1 then
rx_framer_state <= WAIT_FOR_LAST;
else
header_ct := header_ct + 1;
end if;
end if;
when WAIT_FOR_LAST =>
--wait for tlast
if rx_tvalid = '1' and rx_tlast = '1' then
rx_framer_state <= INTERFRAME_GAP;
end if;
--Not actually sure what the ApsMsgProc demands but might as well be compliant with convention
when INTERFRAME_GAP =>
if ifg_ct = 12 then
rx_framer_state <= IDLE;
end if;
ifg_ct := ifg_ct + 1;
end case;
end if;
header_tdata <= ethernet_frame_header(header_ct);
end if;
end process;
--combinational AXIS signals
--hold back data until frame is applied
rx_tready <= rx_framed_tready when rx_framer_state = WAIT_FOR_LAST else '0';
rx_framed_tlast <= rx_tlast when rx_framer_state = WAIT_FOR_LAST else '0';
with rx_framer_state select rx_framed_tvalid <=
'1' when WRITE_HEADER,
rx_tvalid when WAIT_FOR_LAST,
'0' when others;
with rx_framer_state select rx_framed_tdata <=
header_tdata when WRITE_HEADER,
rx_tdata when others;
--Make sure we have a valid ethernet frame size
--Instantiate axis_frame_length_adjust
rx_frame_adjuster_inst : axis_frame_length_adjust
generic map (
DATA_WIDTH => 8
)
port map (
clk => clk,
rst => rst,
--AXIS input
input_axis_tdata => rx_framed_tdata,
input_axis_tkeep => "1",
input_axis_tvalid => rx_framed_tvalid,
input_axis_tready => rx_framed_tready,
input_axis_tlast => rx_framed_tlast,
input_axis_tuser => '0',
--AXIS output
output_axis_tdata => rx_msgproc_tdata,
output_axis_tkeep => open,
output_axis_tvalid => rx_msgproc_tvalid,
output_axis_tready => rx_msgproc_tready,
output_axis_tlast => rx_msgproc_tlast,
output_axis_tuser => open,
--status
status_valid => rx_frame_status_tvalid,
status_ready => '1',
status_frame_pad => rx_frame_padded,
status_frame_truncate => rx_frame_truncated,
unsigned(status_frame_length) => rx_frame_length,
unsigned(status_frame_original_length) => rx_frame_original_length,
--control
length_min => x"0040", --64
length_max => x"05f2" --1522
);
--Questionable assumption ApsMsgProc can always take data
rx_msgproc_tready <= '1';
--strip Ethernet frame header from tx packets
tx_deframer : process(clk)
variable header_ct : integer range 0 to ethernet_frame_header'length;
begin
if rising_edge(clk) then
if rst = '1' then
tx_deframer_state <= IDLE;
header_ct := 0;
else
case( tx_deframer_state ) is
when IDLE =>
header_ct := 0;
--wait for valid to assert to indicate start of packet
if tx_msgproc_tvalid = '1' then
tx_deframer_state <= STRIP_HEADER;
end if;
when STRIP_HEADER =>
if header_ct = ethernet_frame_header'length-2 then
tx_deframer_state <= WAIT_FOR_LAST;
end if;
header_ct := header_ct + 1;
when WAIT_FOR_LAST =>
if tx_msgproc_tvalid = '1' and tx_msgproc_tlast = '1' and tx_tready = '1' then
tx_deframer_state <= IDLE;
end if;
end case;
end if;
end if;
end process;
--combinational AXIS signals
tx_tdata <= tx_msgproc_tdata;
tx_tvalid <= tx_msgproc_tvalid when tx_deframer_state = WAIT_FOR_LAST else '0';
tx_tlast <= tx_msgproc_tlast when tx_deframer_state = WAIT_FOR_LAST else '0';
tx_msgproc_tready <= tx_tready when tx_deframer_state = WAIT_FOR_LAST else '1';
--Intantiate ZRL message processor
--Because the only working simulation model we have is old have to if generate block
-- msgproc_sim : if in_simulation generate
-- AMP1 : entity work.ApsMsgProc
-- port map
-- (
-- -- Interface to MAC to get Ethernet packets
-- MAC_CLK => clk,
-- RESET => rst,
--
-- MAC_RXD => rx_msgproc_tdata,
-- MAC_RX_VALID => rx_msgproc_tvalid,
-- MAC_RX_EOP => rx_msgproc_tlast,
-- MAC_BAD_FCS => '0',
--
-- MAC_TXD => tx_msgproc_tdata,
-- MAC_TX_RDY => tx_msgproc_tready,
-- MAC_TX_VALID => tx_msgproc_tvalid,
-- MAC_TX_EOP => tx_msgproc_tlast,
--
-- -- User Logic Connections
-- USER_CLK => clk,
-- USER_RST => open,
-- USER_VERSION => x"badda555",
-- USER_STATUS => x"0ddba111",
--
-- USER_DIF => open,
-- USER_DIF_RD => '0',
--
-- USER_CIF_EMPTY => open,
-- USER_CIF_RD => '0',
-- USER_CIF_RW => open,
-- USER_CIF_MODE => open,
-- USER_CIF_CNT => open,
-- USER_CIF_ADDR => open,
--
-- USER_DOF => (others => '0'),
-- USER_DOF_WR => '0',
--
-- USER_COF_STAT => (others => '0'),
-- USER_COF_CNT => (others => '0'),
-- USER_COF_AFULL => open,
-- USER_COF_WR => '0',
--
-- -- Config Bus Connections
-- CFG_CLK => cfg_clk,
--
-- -- ApsMsgProc OlderVersion
-- CFGD_IN => x"AAAA",
-- CFGD_OUT => open,
-- CFGD_OE => open,
-- STAT_OE => open,
--
-- -- Status to top level
-- GOOD_TOGGLE => good_toggle,
-- BAD_TOGGLE => bad_toggle
-- );
-- end generate;
msgproc_impl : if in_synthesis generate
-- This encapsulates all of the packet and message processing
AMP1 : ApsMsgProc
port map (
-- Interface to MAC to get Ethernet packets
MAC_CLK => clk,
RESET => rst,
MAC_RXD => rx_msgproc_tdata,
MAC_RX_VALID => rx_msgproc_tvalid,
MAC_RX_EOP => rx_msgproc_tlast,
MAC_BAD_FCS => '0',
MAC_TXD => tx_msgproc_tdata,
MAC_TX_RDY => tx_msgproc_tready,
MAC_TX_VALID => tx_msgproc_tvalid,
MAC_TX_EOP => tx_msgproc_tlast,
NV_DATA => open,
MAC_ADDRESS => open,
BOARD_TYPE => BOARD_TYPE,
-- User Logic Connections
USER_CLK => clk,
USER_RST => open,
USER_VERSION => x"badda555",
USER_STATUS => x"0ddba111",
USER_DIF => open,
USER_DIF_RD => '0',
USER_CIF_EMPTY => open,
USER_CIF_RD => '0',
USER_CIF_RW => open,
USER_CIF_MODE => open,
USER_CIF_CNT => open,
USER_CIF_ADDR => open,
USER_DOF => (others => '0'),
USER_DOF_WR => '0',
USER_COF_STAT => (others => '0'),
USER_COF_CNT => (others => '0'),
USER_COF_AFULL => open,
USER_COF_WR => '0',
-- Config Bus Connections
CFG_CLK => cfg_clk,
CFGD => cfgd,
FPGA_CMDL => fpga_cmdl,
FPGA_RDYL => fpga_rdyl,
CFG_RDY => cfg_rdy,
CFG_ERR => cfg_err,
CFG_ACT => cfg_act,
STAT_OEL => stat_oel,
-- Status to top level
GOOD_TOGGLE => good_toggle,
BAD_TOGGLE => bad_toggle
);
end generate;
end architecture;
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`protect end_protected
| apache-2.0 | 7f8335f8a0a5882ed71d892ad4b4906c | 0.949657 | 1.823406 | false | false | false | false |
freecores/twofish | vhdl/twofish_ecb_decryption_monte_carlo_testbench_192bits.vhd | 1 | 11,520 | -- Twofish_ecb_decryption_monte_carlo_testbench_192bits.vhd
-- Copyright (C) 2006 Spyros Ninos
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this library; see the file COPYING. If not, write to:
--
-- Free Software Foundation
-- 59 Temple Place - Suite 330
-- Boston, MA 02111-1307, USA.
--
-- description : this file is the testbench for the Decryption Monte Carlo KAT of the twofish cipher with 192 bit key
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_arith.all;
use std.textio.all;
entity ecb_decryption_monte_carlo_testbench192 is
end ecb_decryption_monte_carlo_testbench192;
architecture ecb_decryption192_monte_carlo_testbench_arch of ecb_decryption_monte_carlo_testbench192 is
component reg128
port (
in_reg128 : in std_logic_vector(127 downto 0);
out_reg128 : out std_logic_vector(127 downto 0);
enable_reg128, reset_reg128, clk_reg128 : in std_logic
);
end component;
component twofish_keysched192
port (
odd_in_tk192,
even_in_tk192 : in std_logic_vector(7 downto 0);
in_key_tk192 : in std_logic_vector(191 downto 0);
out_key_up_tk192,
out_key_down_tk192 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_whit_keysched192
port (
in_key_twk192 : in std_logic_vector(191 downto 0);
out_K0_twk192,
out_K1_twk192,
out_K2_twk192,
out_K3_twk192,
out_K4_twk192,
out_K5_twk192,
out_K6_twk192,
out_K7_twk192 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_decryption_round192
port (
in1_tdr192,
in2_tdr192,
in3_tdr192,
in4_tdr192,
in_Sfirst_tdr192,
in_Ssecond_tdr192,
in_Sthird_tdr192,
in_key_up_tdr192,
in_key_down_tdr192 : in std_logic_vector(31 downto 0);
out1_tdr192,
out2_tdr192,
out3_tdr192,
out4_tdr192 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_data_input
port (
in_tdi : in std_logic_vector(127 downto 0);
out_tdi : out std_logic_vector(127 downto 0)
);
end component;
component twofish_data_output
port (
in_tdo : in std_logic_vector(127 downto 0);
out_tdo : out std_logic_vector(127 downto 0)
);
end component;
component demux128
port ( in_demux128 : in std_logic_vector(127 downto 0);
out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0);
selection_demux128 : in std_logic
);
end component;
component mux128
port ( in1_mux128, in2_mux128 : in std_logic_vector(127 downto 0);
selection_mux128 : in std_logic;
out_mux128 : out std_logic_vector(127 downto 0)
);
end component;
component twofish_S192
port (
in_key_ts192 : in std_logic_vector(191 downto 0);
out_Sfirst_ts192,
out_Ssecond_ts192,
out_Sthird_ts192 : out std_logic_vector(31 downto 0)
);
end component;
FILE input_file : text is in "twofish_ecb_decryption_monte_carlo_testvalues_192bits.txt";
FILE output_file : text is out "twofish_ecb_decryption_monte_carlo_192bits_results.txt";
-- we create the functions that transform a number to text
-- transforming a signle digit to a character
function digit_to_char(number : integer range 0 to 9) return character is
begin
case number is
when 0 => return '0';
when 1 => return '1';
when 2 => return '2';
when 3 => return '3';
when 4 => return '4';
when 5 => return '5';
when 6 => return '6';
when 7 => return '7';
when 8 => return '8';
when 9 => return '9';
end case;
end;
-- transforming multi-digit number to text
function to_text(int_number : integer range 0 to 9999) return string is
variable our_text : string (1 to 4) := (others => ' ');
variable thousands,
hundreds,
tens,
ones : integer range 0 to 9;
begin
ones := int_number mod 10;
tens := ((int_number mod 100) - ones) / 10;
hundreds := ((int_number mod 1000) - (int_number mod 100)) / 100;
thousands := (int_number - (int_number mod 1000)) / 1000;
our_text(1) := digit_to_char(thousands);
our_text(2) := digit_to_char(hundreds);
our_text(3) := digit_to_char(tens);
our_text(4) := digit_to_char(ones);
return our_text;
end;
signal odd_number,
even_number : std_logic_vector(7 downto 0);
signal input_data,
output_data,
to_encr_reg128,
from_tdi_to_xors,
to_output_whit_xors,
from_xors_to_tdo,
to_mux, to_demux,
from_input_whit_xors,
to_round,
to_input_mux : std_logic_vector(127 downto 0) ;
signal twofish_key : std_logic_vector(191 downto 0);
signal key_up,
key_down,
Sfirst,
Ssecond,
Sthird,
from_xor0,
from_xor1,
from_xor2,
from_xor3,
K0,K1,K2,K3,
K4,K5,K6,K7 : std_logic_vector(31 downto 0);
signal clk : std_logic := '0';
signal mux_selection : std_logic := '0';
signal demux_selection: std_logic := '0';
signal enable_encr_reg : std_logic := '0';
signal reset : std_logic := '0';
signal enable_round_reg : std_logic := '0';
-- begin the testbench arch description
begin
-- getting data to encrypt
data_input: twofish_data_input
port map (
in_tdi => input_data,
out_tdi => from_tdi_to_xors
);
-- producing whitening keys K0..7
the_whitening_step: twofish_whit_keysched192
port map (
in_key_twk192 => twofish_key,
out_K0_twk192 => K0,
out_K1_twk192 => K1,
out_K2_twk192 => K2,
out_K3_twk192 => K3,
out_K4_twk192 => K4,
out_K5_twk192 => K5,
out_K6_twk192 => K6,
out_K7_twk192 => K7
);
-- performing the input whitening XORs
from_xor0 <= K4 XOR from_tdi_to_xors(127 downto 96);
from_xor1 <= K5 XOR from_tdi_to_xors(95 downto 64);
from_xor2 <= K6 XOR from_tdi_to_xors(63 downto 32);
from_xor3 <= K7 XOR from_tdi_to_xors(31 downto 0);
from_input_whit_xors <= from_xor0 & from_xor1 & from_xor2 & from_xor3;
round_reg: reg128
port map ( in_reg128 => from_input_whit_xors,
out_reg128 => to_input_mux,
enable_reg128 => enable_round_reg,
reset_reg128 => reset,
clk_reg128 => clk );
input_mux: mux128
port map ( in1_mux128 => to_input_mux,
in2_mux128 => to_mux,
out_mux128 => to_round,
selection_mux128 => mux_selection
);
-- creating a round
the_keysched_of_the_round: twofish_keysched192
port map (
odd_in_tk192 => odd_number,
even_in_tk192 => even_number,
in_key_tk192 => twofish_key,
out_key_up_tk192 => key_up,
out_key_down_tk192 => key_down
);
producing_the_Skeys: twofish_S192
port map (
in_key_ts192 => twofish_key,
out_Sfirst_ts192 => Sfirst,
out_Ssecond_ts192 => Ssecond,
out_Sthird_ts192 => Sthird
);
the_decryption_circuit: twofish_decryption_round192
port map (
in1_tdr192 => to_round(127 downto 96),
in2_tdr192 => to_round(95 downto 64),
in3_tdr192 => to_round(63 downto 32),
in4_tdr192 => to_round(31 downto 0),
in_Sfirst_tdr192 => Sfirst,
in_Ssecond_tdr192 => Ssecond,
in_Sthird_tdr192 => Sthird,
in_key_up_tdr192 => key_up,
in_key_down_tdr192 => key_down,
out1_tdr192 => to_encr_reg128(127 downto 96),
out2_tdr192 => to_encr_reg128(95 downto 64),
out3_tdr192 => to_encr_reg128(63 downto 32),
out4_tdr192 => to_encr_reg128(31 downto 0)
);
encr_reg: reg128
port map ( in_reg128 => to_encr_reg128,
out_reg128 => to_demux,
enable_reg128 => enable_encr_reg,
reset_reg128 => reset,
clk_reg128 => clk );
output_demux: demux128
port map ( in_demux128 => to_demux,
out1_demux128 => to_output_whit_xors,
out2_demux128 => to_mux,
selection_demux128 => demux_selection );
-- don't forget the last swap !!!
from_xors_to_tdo(127 downto 96) <= K0 XOR to_output_whit_xors(63 downto 32);
from_xors_to_tdo(95 downto 64) <= K1 XOR to_output_whit_xors(31 downto 0);
from_xors_to_tdo(63 downto 32) <= K2 XOR to_output_whit_xors(127 downto 96);
from_xors_to_tdo(31 downto 0) <= K3 XOR to_output_whit_xors(95 downto 64);
taking_the_output: twofish_data_output
port map (
in_tdo => from_xors_to_tdo,
out_tdo => output_data
);
-- we create the clock
clk <= not clk after 50 ns; -- period 100 ns
ecb_dmc_proc: process
variable key_f, -- key input from file
pt_f, -- plaintext from file
ct_f : line; -- ciphertext from file
variable key_v : std_logic_vector(191 downto 0); -- key vector input
variable pt_v , -- plaintext vector
ct_v : std_logic_vector(127 downto 0); -- ciphertext vector
variable counter_10000 : integer range 0 to 9999 := 0; -- counter for the 10.000 repeats in the 400 next ones
variable counter_400 : integer range 0 to 399 := 0; -- counter for the 400 repeats
variable round : integer range 0 to 16 := 0; -- holds the rounds
variable intermediate_decryption_result : std_logic_vector(127 downto 0); -- holds the intermediate decryption result
begin
while not endfile(input_file) loop
readline(input_file, key_f);
readline(input_file, pt_f);
readline(input_file,ct_f);
hread(key_f,key_v);
hread(pt_f,pt_v);
hread(ct_f,ct_v);
twofish_key <= key_v;
intermediate_decryption_result := pt_v;
for counter_10000 in 0 to 9999 loop
input_data <= intermediate_decryption_result;
wait for 25 ns;
reset <= '1';
wait for 50 ns;
reset <= '0';
mux_selection <= '0';
demux_selection <= '1';
enable_encr_reg <= '0';
enable_round_reg <= '0';
wait for 50 ns;
enable_round_reg <= '1';
wait for 50 ns;
enable_round_reg <= '0';
-- the first round
even_number <= "00100110"; -- 38
odd_number <= "00100111"; -- 39
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
demux_selection <= '1';
mux_selection <= '1';
-- the rest 15 rounds
for round in 1 to 15 loop
even_number <= conv_std_logic_vector((((15-round)*2)+8), 8);
odd_number <= conv_std_logic_vector((((15-round)*2)+9), 8);
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
end loop;
-- taking final results
demux_selection <= '0';
wait for 25 ns;
intermediate_decryption_result := output_data;
assert false report "I=" & to_text(counter_400) & " R=" & to_text(counter_10000) severity note;
end loop; -- counter_10000
hwrite(key_f, key_v);
hwrite(pt_f, pt_v);
hwrite(ct_f,output_data);
writeline(output_file,key_f);
writeline(output_file,pt_f);
writeline(output_file,ct_f);
assert (ct_v = output_data) report "file entry and decryption result DO NOT match!!! :( " severity failure;
assert (ct_v /= output_data) report "Decryption I=" & to_text(counter_400) &" OK" severity note;
counter_400 := counter_400 + 1;
end loop;
assert false report "***** ECB Decryption Monte Carlo Test with 192 bits key size ended succesfully! :) *****" severity failure;
end process ecb_dmc_proc;
end ecb_decryption192_monte_carlo_testbench_arch;
| gpl-2.0 | b5bb76460ffa4ace90842596f20241d5 | 0.653212 | 2.735692 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/fpu_div.vhd | 1 | 23,013 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15296)
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| apache-2.0 | dfa12c9e699b8acebb7a858ad2dd43f2 | 0.940729 | 1.842809 | false | false | false | false |
mbgh/aes128-hdl | src/vhdl/keyExpansion.vhd | 1 | 12,251 | -------------------------------------------------------------------------------
--! @file keyExpansion.vhd
--! @brief AES-128 key expansion
--! @project VLSI Book - AES-128 Example
--! @author Michael Muehlberghuber ([email protected])
--! @company Integrated Systems Laboratory, ETH Zurich
--! @copyright Copyright (C) 2014 Integrated Systems Laboratory, ETH Zurich
--! @date 2014-06-05
--! @updated 2014-10-30
--! @platform Simulation: ModelSim; Synthesis: Synopsys
--! @standard VHDL'93/02
-------------------------------------------------------------------------------
-- Revision Control System Information:
-- File ID : $Id: keyExpansion.vhd 43 2014-10-30 12:22:52Z u59323933 $
-- Revision : $Revision: 43 $
-- Local Date : $Date: 2014-10-30 13:22:52 +0100 (Thu, 30 Oct 2014) $
-- Modified By : $Author: u59323933 $
-------------------------------------------------------------------------------
-- Major Revisions:
-- Date Version Author Description
-- 2014-06-05 1.0 michmueh Created
-- 2014-06-10 1.1 michmueh Removed controlling FSM an replaced the
-- roundkey enables with a simple shift
-- register.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.aes128Pkg.all;
-------------------------------------------------------------------------------
--! @brief AES-128 key expansion
--!
--! The present design implements the key expansion for the 128-bit version of
--! the Advanced Encryption Standard (AES). Since the design targets a
--! high-throughput implementation, the key expansion is implemented using
--! pipeline register between each roundkey calculation.
-------------------------------------------------------------------------------
entity keyExpansion is
port (
--! @brief System clock.
Clk_CI : in std_logic;
--! @brief Asynchronous, active-high reset.
Reset_RBI : in std_logic;
--! @brief Determines whether a new cipherkey has been applied or not.
--! <TABLE BORDER="0">
--! <TR><TD>0</TD><TD>...</TD><TD>No new cipherkey has been applied.</TD></TR>
--! <TR><TD>1</TD><TD>...</TD><TD>New cipherkey has been applied.</TD></TR>
--! </TABLE>
Start_SI : in std_logic;
--! @brief The cipher key (master key) for the encryption/decryption.
Cipherkey_DI : in std_logic_vector(127 downto 0);
--! @brief The generated round keys.
Roundkeys_DO : out roundkeyArrayType);
end entity keyExpansion;
-------------------------------------------------------------------------------
--! @brief Behavioral architecture description of AES-128 key expansion.
-------------------------------------------------------------------------------
architecture Behavioral of keyExpansion is
-----------------------------------------------------------------------------
-- Type definitions
-----------------------------------------------------------------------------
type byteArrayType is array (0 to 9) of std_logic_vector(7 downto 0);
type subWordArrayType is array (0 to 9) of Word;
type expkeyArrayType is array (0 to 43) of Word;
type rconArrayType is array (0 to 9) of Word;
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
constant RCON : byteArrayType := (
x"01", x"02", x"04", x"08", x"10", x"20", x"40", x"80", x"1B", x"36");
-----------------------------------------------------------------------------
-- Function declarations
-----------------------------------------------------------------------------
-- purpose: Provides an exclusive-or (XOR) operation for words.
function "xor" (
left : Word;
right : Word) return Word is
variable Result : Word;
begin
Result(0) := left(0) xor right(0);
Result(1) := left(1) xor right(1);
Result(2) := left(2) xor right(2);
Result(3) := left(3) xor right(3);
return Result;
end "xor";
-- purpose: Converts a word to a std_logic_vector. The 0-th byte of the word
-- becomes the most significant byte of the std_logic_vector.
function conv_std_logic_vector (
input : Word)
return std_logic_vector is
begin -- function conv_std_logic_vector
return input(0) & input(1) & input(2) & input(3);
end function conv_std_logic_vector;
-- purpose: Converts four words (i.e., a matrix) to a std_logic_vector.
function conv_std_logic_vector (
column0 : Word;
column1 : Word;
column2 : Word;
column3 : Word)
return std_logic_vector is
begin -- function conv_std_logic_vector
return
column0(0) & column0(1) & column0(2) & column0(3) &
column1(0) & column1(1) & column1(2) & column1(3) &
column2(0) & column2(1) & column2(2) & column2(3) &
column3(0) & column3(1) & column3(2) & column3(3);
end function conv_std_logic_vector;
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
component subWord is
port (
In_DI : in Word;
Out_DO : out Word);
end component subWord;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
-- ExpKey_D: Array of 32-bit words (each made up of four bytes) holding the
-- expanded key.
signal ExpKey_DN, ExpKey_DP : expkeyArrayType;
-- SubWordIn_D: Array holding the ten inputs, each of them one 32-word wide,
-- connected to the input of the AES S-box.
signal SubWordIn_D : subWordArrayType;
-- SubWordOut_D: Array holding the ten outputs, each of them one 32-word wide,
-- connected to the output of the AES S-box.
signal SubWordOut_D : subWordArrayType;
-- Rcon_D: Array holding the ten signals after the XOR operation with the
-- round constants.
signal Rcon_D : rconArrayType;
-- Roundkeys_D: Array holding all the roundkeys produced by the key epansion.
signal Roundkeys_D : roundkeyArrayType;
-- Shift register holding the enables for the roundkey registers.
signal EnRndKeys_SN, EnRndKeys_SP : std_logic_vector(0 to 9);
-- Indicates that all roundkey registers currently hold their correct value
-- and must not be enabled (e.g., no new cipherkey is provided to the design
-- and the corresponding roundkeys have already been derived).
signal AllRndKeysDisabled_S : std_logic;
begin -- architecture rtl
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
-- Generate the ten SubWord instances.
gen_subWords : for i in 0 to 9 generate
subWords : subWord
port map (
In_DI => SubWordIn_D(i),
Out_DO => SubWordOut_D(i));
end generate gen_subWords;
-----------------------------------------------------------------------------
-- Output assignments
-----------------------------------------------------------------------------
-- Connect the columns of the expanded key to the round key outputs.
gen_outputKeys : for i in 0 to 10 generate
Roundkeys_DO(i) <= conv_std_logic_vector(
ExpKey_DP(4*i), ExpKey_DP(4*i+1), ExpKey_DP(4*i+2), ExpKey_DP(4*i+3));
end generate gen_outputKeys;
-----------------------------------------------------------------------------
-- Connect the cipherkey to the first four columns (i.e., words) of the
-- expanded key.
-----------------------------------------------------------------------------
-- Use the first roundkey (i.e., the actual cipherkey) as the first four
-- 32-bit words of the expanded key.
ExpKey_DN(0) <= conv_word(Cipherkey_DI(127 downto 96)) when Start_SI = '1' else ExpKey_DP(0);
ExpKey_DN(1) <= conv_word(Cipherkey_DI(95 downto 64)) when Start_SI = '1' else ExpKey_DP(1);
ExpKey_DN(2) <= conv_word(Cipherkey_DI(63 downto 32)) when Start_SI = '1' else ExpKey_DP(2);
ExpKey_DN(3) <= conv_word(Cipherkey_DI(31 downto 0)) when Start_SI = '1' else ExpKey_DP(3);
-----------------------------------------------------------------------------
-- Calculation of further round key words.
-----------------------------------------------------------------------------
-- Since the "RotWord" function only performs a byte-wise rotation of a word,
-- we can perform it either before or after the "SubWord" substitution.
gen_roundKeys : for i in 0 to 9 generate
SubWordIn_D(i) <= ExpKey_DP(4*i+3);
Rcon_D(i)(0) <= SubWordOut_D(i)(1) xor RCON(i);
Rcon_D(i)(1) <= SubWordOut_D(i)(2);
Rcon_D(i)(2) <= SubWordOut_D(i)(3);
Rcon_D(i)(3) <= SubWordOut_D(i)(0);
-- Calculate the next expanded key only when the respective enable signal
-- is set.
ExpKey_DN(4*(i+1)+0) <= Rcon_D(i) xor ExpKey_DP(4*i) when EnRndKeys_SP(i) = '1' else ExpKey_DP(4*(i+1)+0);
ExpKey_DN(4*(i+1)+1) <= Rcon_D(i) xor ExpKey_DP(4*i) xor ExpKey_DP(4*i+1) when EnRndKeys_SP(i) = '1' else ExpKey_DP(4*(i+1)+1);
ExpKey_DN(4*(i+1)+2) <= Rcon_D(i) xor ExpKey_DP(4*i) xor ExpKey_DP(4*i+1) xor ExpKey_DP(4*i+2) when EnRndKeys_SP(i) = '1' else ExpKey_DP(4*(i+1)+2);
ExpKey_DN(4*(i+1)+3) <= Rcon_D(i) xor ExpKey_DP(4*i) xor ExpKey_DP(4*i+1) xor ExpKey_DP(4*i+2) xor ExpKey_DP(4*i+3) when EnRndKeys_SP(i) = '1' else ExpKey_DP(4*(i+1)+3);
end generate gen_roundKeys;
-----------------------------------------------------------------------------
-- Compute the next state logic for the shift register holding the enables for
-- the roundkeys.
-----------------------------------------------------------------------------
-- The enables for the roundkeys are generated by a one-hot encoded shift
-- register, which gets the start signal as an input.
EnRndKeys_SN <=
-- Start signal is set, so shift in a '1'.
'1' & EnRndKeys_SP(0 to 8) when Start_SI = '1' else
-- Since none of the roundkeys currently holds a substantial value, we do
-- not even have to shift in the zeros, but just hold the current state
-- (this might be the case when, the encryption pipeline has been emptied
-- and no encryption is going on anymore, i.e., no other plaintext blocks
-- have been provided).
EnRndKeys_SP when AllRndKeysDisabled_S = '1' else
-- Otherwise shift the enables such that they are proceeded correctly
-- together with their current pipeline stage (this enables-holding shift
-- register serves as kind of a shimming register).
'0' & EnRndKeys_SP(0 to 8);
-----------------------------------------------------------------------------
-- Compute the signal indicating that none of the roundkey registers has to
-- be updated, i.e., no new cipherkey has to be propagated through the key
-- expansion pipeline registers.
-----------------------------------------------------------------------------
pComb_CalcAllRndKeysDisabled : process (EnRndKeys_SP) is
variable tmp : std_logic;
begin -- process pComb_CalcAllRndKeysDisabled
tmp := EnRndKeys_SP(0);
for i in 1 to 9 loop
tmp := tmp or EnRndKeys_SP(i);
end loop; -- i
AllRndKeysDisabled_S <= not tmp;
end process pComb_CalcAllRndKeysDisabled;
-----------------------------------------------------------------------------
-- Flip Flops
-----------------------------------------------------------------------------
pSequ_FlipFlops : process (Clk_CI, Reset_RBI) is
begin -- process p_FlipFlops
if Reset_RBI = '0' then -- asynchronous reset (active low)
ExpKey_DP <= (others => ZERO_WORD);
EnRndKeys_SP <= (others => '0');
elsif Clk_CI'event and Clk_CI = '1' then -- rising clock edge
ExpKey_DP <= ExpKey_DN;
EnRndKeys_SP <= EnRndKeys_SN;
end if;
end process pSequ_FlipFlops;
end architecture Behavioral;
| gpl-2.0 | 15e92b1b5f141ced7925ec7a71e7eb8d | 0.515386 | 4.071452 | false | false | false | false |
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`protect end_protected
| apache-2.0 | 86bbd2f79c4c1d048eabf18a9250d647 | 0.935362 | 1.854881 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/fifo_generator_v12_0_defaults.vhd | 5 | 30,145 | `protect begin_protected
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect key_block
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`protect end_protected
| apache-2.0 | b04f6f2b3a96d0674b140c0683b40c8d | 0.944601 | 1.833526 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/ramfifo/wr_status_flags_as.vhd | 5 | 20,484 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13424)
`protect data_block
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| apache-2.0 | 25227966129d07a9fef53614a0a1d32a | 0.94132 | 1.858465 | false | false | false | false |
freecores/twofish | vhdl/twofish_cbc_encryption_monte_carlo_testbench_256bits.vhd | 1 | 11,814 | -- Twofish_cbc_encryption_monte_carlo_testbench_256bits.vhd
-- Copyright (C) 2006 Spyros Ninos
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this library; see the file COPYING. If not, write to:
--
-- Free Software Foundation
-- 59 Temple Place - Suite 330
-- Boston, MA 02111-1307, USA.
--
-- description : this file is the testbench for the Encryption Monte Carlo KAT of the twofish cipher with 256 bit key
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_arith.all;
use std.textio.all;
entity cbc_encryption_monte_carlo_testbench256 is
end cbc_encryption_monte_carlo_testbench256;
architecture cbc_encryption256_monte_carlo_testbench_arch of cbc_encryption_monte_carlo_testbench256 is
component reg128
port (
in_reg128 : in std_logic_vector(127 downto 0);
out_reg128 : out std_logic_vector(127 downto 0);
enable_reg128, reset_reg128, clk_reg128 : in std_logic
);
end component;
component twofish_keysched256
port (
odd_in_tk256,
even_in_tk256 : in std_logic_vector(7 downto 0);
in_key_tk256 : in std_logic_vector(255 downto 0);
out_key_up_tk256,
out_key_down_tk256 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_whit_keysched256
port (
in_key_twk256 : in std_logic_vector(255 downto 0);
out_K0_twk256,
out_K1_twk256,
out_K2_twk256,
out_K3_twk256,
out_K4_twk256,
out_K5_twk256,
out_K6_twk256,
out_K7_twk256 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_encryption_round256
port (
in1_ter256,
in2_ter256,
in3_ter256,
in4_ter256,
in_Sfirst_ter256,
in_Ssecond_ter256,
in_Sthird_ter256,
in_Sfourth_ter256,
in_key_up_ter256,
in_key_down_ter256 : in std_logic_vector(31 downto 0);
out1_ter256,
out2_ter256,
out3_ter256,
out4_ter256 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_data_input
port (
in_tdi : in std_logic_vector(127 downto 0);
out_tdi : out std_logic_vector(127 downto 0)
);
end component;
component twofish_data_output
port (
in_tdo : in std_logic_vector(127 downto 0);
out_tdo : out std_logic_vector(127 downto 0)
);
end component;
component demux128
port ( in_demux128 : in std_logic_vector(127 downto 0);
out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0);
selection_demux128 : in std_logic
);
end component;
component mux128
port ( in1_mux128, in2_mux128 : in std_logic_vector(127 downto 0);
selection_mux128 : in std_logic;
out_mux128 : out std_logic_vector(127 downto 0)
);
end component;
component twofish_S256
port (
in_key_ts256 : in std_logic_vector(255 downto 0);
out_Sfirst_ts256,
out_Ssecond_ts256,
out_Sthird_ts256,
out_Sfourth_ts256 : out std_logic_vector(31 downto 0)
);
end component;
FILE input_file : text is in "twofish_cbc_encryption_monte_carlo_testvalues_256bits.txt";
FILE output_file : text is out "twofish_cbc_encryption_monte_carlo_256bits_results.txt";
-- we create the functions that transform a number to text
-- transforming a signle digit to a character
function digit_to_char(number : integer range 0 to 9) return character is
begin
case number is
when 0 => return '0';
when 1 => return '1';
when 2 => return '2';
when 3 => return '3';
when 4 => return '4';
when 5 => return '5';
when 6 => return '6';
when 7 => return '7';
when 8 => return '8';
when 9 => return '9';
end case;
end;
-- transforming multi-digit number to text
function to_text(int_number : integer range 0 to 9999) return string is
variable our_text : string (1 to 4) := (others => ' ');
variable thousands,
hundreds,
tens,
ones : integer range 0 to 9;
begin
ones := int_number mod 10;
tens := ((int_number mod 100) - ones) / 10;
hundreds := ((int_number mod 1000) - (int_number mod 100)) / 100;
thousands := (int_number - (int_number mod 1000)) / 1000;
our_text(1) := digit_to_char(thousands);
our_text(2) := digit_to_char(hundreds);
our_text(3) := digit_to_char(tens);
our_text(4) := digit_to_char(ones);
return our_text;
end;
signal odd_number,
even_number : std_logic_vector(7 downto 0);
signal input_data,
output_data,
to_encr_reg128,
from_tdi_to_xors,
to_output_whit_xors,
from_xors_to_tdo,
to_mux, to_demux,
from_input_whit_xors,
to_round,
to_input_mux : std_logic_vector(127 downto 0) ;
signal twofish_key : std_logic_vector(255 downto 0);
signal key_up,
key_down,
Sfirst,
Ssecond,
Sthird,
Sfourth,
from_xor0,
from_xor1,
from_xor2,
from_xor3,
K0,K1,K2,K3,
K4,K5,K6,K7 : std_logic_vector(31 downto 0);
signal clk : std_logic := '0';
signal mux_selection : std_logic := '0';
signal demux_selection: std_logic := '0';
signal enable_encr_reg : std_logic := '0';
signal reset : std_logic := '0';
signal enable_round_reg : std_logic := '0';
-- begin the testbench arch description
begin
-- getting data to encrypt
data_input: twofish_data_input
port map (
in_tdi => input_data,
out_tdi => from_tdi_to_xors
);
-- producing whitening keys K0..7
the_whitening_step: twofish_whit_keysched256
port map (
in_key_twk256 => twofish_key,
out_K0_twk256 => K0,
out_K1_twk256 => K1,
out_K2_twk256 => K2,
out_K3_twk256 => K3,
out_K4_twk256 => K4,
out_K5_twk256 => K5,
out_K6_twk256 => K6,
out_K7_twk256 => K7
);
-- performing the input whitening XORs
from_xor0 <= K0 XOR from_tdi_to_xors(127 downto 96);
from_xor1 <= K1 XOR from_tdi_to_xors(95 downto 64);
from_xor2 <= K2 XOR from_tdi_to_xors(63 downto 32);
from_xor3 <= K3 XOR from_tdi_to_xors(31 downto 0);
from_input_whit_xors <= from_xor0 & from_xor1 & from_xor2 & from_xor3;
round_reg: reg128
port map ( in_reg128 => from_input_whit_xors,
out_reg128 => to_input_mux,
enable_reg128 => enable_round_reg,
reset_reg128 => reset,
clk_reg128 => clk );
input_mux: mux128
port map ( in1_mux128 => to_input_mux,
in2_mux128 => to_mux,
out_mux128 => to_round,
selection_mux128 => mux_selection
);
-- creating a round
the_keysched_of_the_round: twofish_keysched256
port map (
odd_in_tk256 => odd_number,
even_in_tk256 => even_number,
in_key_tk256 => twofish_key,
out_key_up_tk256 => key_up,
out_key_down_tk256 => key_down
);
producing_the_Skeys: twofish_S256
port map (
in_key_ts256 => twofish_key,
out_Sfirst_ts256 => Sfirst,
out_Ssecond_ts256 => Ssecond,
out_Sthird_ts256 => Sthird,
out_Sfourth_ts256 => Sfourth
);
the_encryption_circuit: twofish_encryption_round256
port map (
in1_ter256 => to_round(127 downto 96),
in2_ter256 => to_round(95 downto 64),
in3_ter256 => to_round(63 downto 32),
in4_ter256 => to_round(31 downto 0),
in_Sfirst_ter256 => Sfirst,
in_Ssecond_ter256 => Ssecond,
in_Sthird_ter256 => Sthird,
in_Sfourth_ter256 => Sfourth,
in_key_up_ter256 => key_up,
in_key_down_ter256 => key_down,
out1_ter256 => to_encr_reg128(127 downto 96),
out2_ter256 => to_encr_reg128(95 downto 64),
out3_ter256 => to_encr_reg128(63 downto 32),
out4_ter256 => to_encr_reg128(31 downto 0)
);
encr_reg: reg128
port map ( in_reg128 => to_encr_reg128,
out_reg128 => to_demux,
enable_reg128 => enable_encr_reg,
reset_reg128 => reset,
clk_reg128 => clk );
output_demux: demux128
port map ( in_demux128 => to_demux,
out1_demux128 => to_output_whit_xors,
out2_demux128 => to_mux,
selection_demux128 => demux_selection );
-- don't forget the last swap !!!
from_xors_to_tdo(127 downto 96) <= K4 XOR to_output_whit_xors(63 downto 32);
from_xors_to_tdo(95 downto 64) <= K5 XOR to_output_whit_xors(31 downto 0);
from_xors_to_tdo(63 downto 32) <= K6 XOR to_output_whit_xors(127 downto 96);
from_xors_to_tdo(31 downto 0) <= K7 XOR to_output_whit_xors(95 downto 64);
taking_the_output: twofish_data_output
port map (
in_tdo => from_xors_to_tdo,
out_tdo => output_data
);
-- we create the clock
clk <= not clk after 50 ns; -- period 100 ns
cbc_emc_proc: process
variable key_f, -- key input from file
pt_f, -- plaintext from file
ct_f,
iv_f : line; -- ciphertext from file
variable key_v : std_logic_vector(255 downto 0); -- key vector input
variable pt_v , -- plaintext vector
ct_v,
iv_v : std_logic_vector(127 downto 0); -- ciphertext vector
variable counter_10000 : integer range 0 to 9999 := 0; -- counter for the 10.000 repeats in the 400 next ones
variable counter_400 : integer range 0 to 399 := 0; -- counter for the 400 repeats
variable round : integer range 0 to 16 := 0; -- holds the rounds
variable PT, CT, CV, CTj_1 : std_logic_vector(127 downto 0) := (others => '0');
begin
while not endfile(input_file) loop
readline(input_file, key_f);
readline(input_file, iv_f);
readline(input_file, pt_f);
readline(input_file,ct_f);
hread(key_f,key_v);
hread(iv_f, iv_v);
hread(pt_f,pt_v);
hread(ct_f,ct_v);
twofish_key <= key_v;
PT := pt_v;
CV := iv_v;
for counter_10000 in 0 to 9999 loop
input_data <= PT xor CV;
wait for 25 ns;
reset <= '1';
wait for 50 ns;
reset <= '0';
mux_selection <= '0';
demux_selection <= '1';
enable_encr_reg <= '0';
enable_round_reg <= '0';
wait for 50 ns;
enable_round_reg <= '1';
wait for 50 ns;
enable_round_reg <= '0';
-- the first round
even_number <= "00001000"; -- 8
odd_number <= "00001001"; -- 9
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
demux_selection <= '1';
mux_selection <= '1';
-- the rest 15 rounds
for round in 1 to 15 loop
even_number <= conv_std_logic_vector(((round*2)+8), 8);
odd_number <= conv_std_logic_vector(((round*2)+9), 8);
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
end loop;
-- taking final results
demux_selection <= '0';
wait for 25 ns;
CTj_1 := CT;
CT := output_data;
if ( counter_10000 = 0 ) then
PT := CV;
else
PT := CTj_1;
end if; -- counter_10000 = 0
CV := CT;
assert false report "I=" & to_text(counter_400) & " R=" & to_text(counter_10000) severity note;
end loop; -- counter_10000
hwrite(key_f, key_v);
hwrite(iv_f, iv_v);
hwrite(pt_f, pt_v);
hwrite(ct_f,output_data);
writeline(output_file,key_f);
writeline(output_file, iv_f);
writeline(output_file,pt_f);
writeline(output_file,ct_f);
assert (ct_v = output_data) report "file entry and encryption result DO NOT match!!! :( " severity failure;
assert (ct_v /= output_data) report "Encryption I=" & to_text(counter_400) &" OK" severity note;
counter_400 := counter_400 + 1;
end loop;
assert false report "***** CBC Encryption Monte Carlo Test with 256 bits key size ended succesfully! :) *****" severity failure;
end process cbc_emc_proc;
end cbc_encryption256_monte_carlo_testbench_arch;
| gpl-2.0 | e6ca6218c1b0be73a193ed40d554b872 | 0.644744 | 2.701578 | false | false | false | false |
witoldo7/puc-2 | PUC/PUC_567/PUC_2/mod10_1.vhd | 1 | 1,280 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity mod10_1 is
Port ( outp : out std_logic_vector(3 downto 0);
UP : in std_logic;
clk : in std_logic;
carry: out std_logic;
clr : in std_logic;
dir : out std_logic;
DOWN : in std_logic);
end mod10_1;
architecture Behavioral of mod10_1 is
signal temp : std_logic_vector(3 downto 0);
-- pomocnicze zmienne zabezpieczja wy przed inkrementowaniem z kazdym
-- narastajacym zboczem zegara
signal up1, dw1 : std_logic;
begin
process(clk,clr)
begin
if clr = '1' then
temp<="0000";
carry <= '0';
elsif rising_edge(clk) then
-- licz w gore jesli narastajace zbocze zegara, na sygnale UP "1"
-- poprzednia wartosc UP "0" patrz komentarz wyzej oraz DOWN "0"
if (UP='1' and up1='0' and DOWN='0') then
dir <= '1';
if temp <= "1000" then
temp <= temp+1;
carry <='0';
else
temp <= "0000";
carry <= '1';
end if;
elsif (DOWN='1' and dw1='0' and UP='0') then
dir <= '0';
if temp >= "0001" then
temp <= temp - 1;
carry <='0';
else
temp <= "1001";
carry <= '1';
end if;
end if;
up1 <= UP;
dw1 <= DOWN;
end if;
outp<=temp;
end process;
end Behavioral;
| gpl-3.0 | 856739d1d9aa0dd8a2e98461353c64ae | 0.601563 | 2.514735 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/ramfifo/fifo_generator_ramfifo.vhd | 5 | 80,159 | `protect begin_protected
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`protect end_protected
| apache-2.0 | ece3fa811b78c1c28f7f1718dfb1ea18 | 0.952993 | 1.818902 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/3-ARF/asap-alap-random/arf_random.vhd | 1 | 2,566 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.14:37:51)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY arf_random_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8: IN unsigned(0 TO 3);
output1, output2: OUT unsigned(0 TO 4));
END arf_random_entity;
ARCHITECTURE arf_random_description OF arf_random_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
register2 := input2 * 2;
register3 := input3 * 3;
register4 := input4 * 4;
register5 := input5 * 5;
WHEN "00000010" =>
register1 := register4 + register1;
register4 := input6 * 6;
WHEN "00000011" =>
register2 := register4 + register2;
register4 := input7 * 7;
register6 := input8 * 8;
WHEN "00000100" =>
register5 := register6 + register5;
WHEN "00000101" =>
register5 := register5 + 10;
WHEN "00000110" =>
register6 := register5 * 12;
register2 := register2 + 14;
register5 := register5 * 16;
WHEN "00000111" =>
register7 := register2 * 18;
WHEN "00001000" =>
register5 := register7 + register5;
register3 := register3 + register4;
WHEN "00001001" =>
register4 := register5 * 20;
register5 := register5 * 22;
register2 := register2 * 24;
WHEN "00001010" =>
register2 := register2 + register6;
WHEN "00001011" =>
register6 := register2 * 26;
WHEN "00001100" =>
register4 := register6 + register4;
register2 := register2 * 28;
WHEN "00001101" =>
register2 := register2 + register5;
WHEN "00001110" =>
output1 <= register1 + register2;
output2 <= register3 + register4;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END arf_random_description; | gpl-3.0 | 751a08899e233fce95aa199a828d23a3 | 0.653936 | 3.133089 | false | false | false | false |
CyAScott/CIS4930.DatapathSynthesisTool | src/components/c_latch.vhd | 1 | 730 | library ieee;
use ieee.std_logic_1164.all;
library WORK;
use WORK.all;
entity c_latch is
generic
(
width : integer := 4
);
port
(
input : in std_logic_vector((width - 1) downto 0);
enable : in std_logic;
clear : in std_logic;
clock : in std_logic;
output : out std_logic_vector((width - 1) downto 0)
);
end c_latch;
architecture behavior of c_latch is
begin
P0 : process (clock, clear, input, enable)
variable out_var : std_logic_vector((width - 1) downto 0);
begin
for I in width - 1 downto 0 loop
out_var(I) := '0';
end loop;
if (clear = '1') then
output <= out_var;
elsif (clock = '1' and not clock'STABLE and enable = '1') then
output <= input;
end if;
end process P0;
end behavior; | mit | 2e75264fd320ad667ff7e9d5106cac16 | 0.645205 | 2.765152 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/ramfifo/dc_ss.vhd | 5 | 12,203 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
| apache-2.0 | 79a69dc2c3eabc20ebd96b40ed66a87c | 0.931574 | 1.904041 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/basic_sfifo_fg.vhd | 1 | 55,489 | -------------------------------------------------------------------------------
-- basic_sfifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: basic_sfifo_fg.vhd
--
-- Description:
-- This HDL file implements a basic synchronous (single clock) fifo using the
-- FIFO Generator tool. It is intended to offer a simple interface to the user
-- with the complexity of the FIFO Generator interface hidden from the user.
--
-- Note that in normal op mode (not First Word Fall Through FWFT) the data count
-- output goes to zero when the FIFO goes full. This the way FIFO Generator works.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- basic_sfifo_fg.vhd
-- |
-- |-- fifo_generator_v8_2
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.0 $
-- Date: $3/07/2011$
--
-- History:
-- DET 3/07/2011 Initial Version
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library fifo_generator_v12_0;
use fifo_generator_v12_0.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.all;
use proc_common_v4_0.proc_common_pkg.log2;
--use proc_common_v4_0.coregen_comp_defs.all;
-- synopsys translate_off
--library XilinxCoreLib;
--use XilinxCoreLib.all;
-- synopsys translate_on
-------------------------------------------------------------------------------
entity basic_sfifo_fg is
generic (
C_DWIDTH : Integer := 32 ;
-- FIFO data Width (Read and write data ports are symetric)
C_DEPTH : Integer := 512 ;
-- FIFO Depth (set to power of 2)
C_HAS_DATA_COUNT : integer := 1 ;
-- 0 = Data Count output not needed
-- 1 = Data Count output needed
C_DATA_COUNT_WIDTH : integer := 10 ;
-- Data Count bit width (Max value is log2(C_DEPTH))
C_IMPLEMENTATION_TYPE : integer range 0 to 1 := 0;
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
C_MEMORY_TYPE : integer := 1;
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
C_PRELOAD_REGS : integer := 1;
-- 0 = normal
-- 1 = FWFT
C_PRELOAD_LATENCY : integer := 0;
-- 0 = FWFT
-- 1 = normal
C_USE_FWFT_DATA_COUNT : integer := 0;
-- 0 = normal
-- 1 for FWFT
C_SYNCHRONIZER_STAGE : integer := 2; -- valid values are 0 to 8;
C_FAMILY : string := "virtex6"
);
port (
CLK : IN std_logic := '0';
DIN : IN std_logic_vector(C_DWIDTH-1 DOWNTO 0) := (OTHERS => '0');
RD_EN : IN std_logic := '0';
SRST : IN std_logic := '0';
WR_EN : IN std_logic := '0';
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
DOUT : OUT std_logic_vector(C_DWIDTH-1 DOWNTO 0);
EMPTY : OUT std_logic;
FULL : OUT std_logic
);
end entity basic_sfifo_fg;
architecture implementation of basic_sfifo_fg is
-- Constant Declarations ----------------------------------------------
Constant POINTER_WIDTH : integer := log2(C_DEPTH);
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(POINTER_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(POINTER_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal ALMOST_FULL : std_logic;
signal WR_ACK : std_logic;
signal OVERFLOW : std_logic;
signal VALID : std_logic;
signal UNDERFLOW : std_logic;
signal ALMOST_EMPTY : std_logic;
signal RD_DATA_COUNT : std_logic_vector(C_DATA_COUNT_WIDTH-1 downto 0);
signal WR_DATA_COUNT : std_logic_vector(C_DATA_COUNT_WIDTH-1 downto 0);
signal PROG_FULL : std_logic;
signal PROG_EMPTY : std_logic;
signal SBITERR : std_logic;
signal DBITERR : std_logic;
signal WR_RST_BUSY : std_logic;
signal RD_RST_BUSY : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_BUSER : std_logic_vector(0 downto 0);
signal S_AXI_BVALID : std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWUSER : std_logic_vector(0 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_WID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_WUSER : std_logic_vector(0 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_BREADY : std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0);
signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_RLAST : std_logic;
signal S_AXI_RUSER : std_logic_vector(0 downto 0);
signal S_AXI_RVALID : std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARUSER : std_logic_vector(0 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_RREADY : std_logic;
-- AXI Streaming Slave Signals (Write side)
signal S_AXIS_TREADY : std_logic;
-- AXI Streaming Master Signals (Read side)
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TLAST : std_logic;
signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0);
signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_SBITERR : std_logic;
signal AXI_AW_DBITERR : std_logic;
signal AXI_AW_OVERFLOW : std_logic;
signal AXI_AW_UNDERFLOW : std_logic;
signal AXI_AW_PROG_FULL : STD_LOGIC;
signal AXI_AW_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Data Channel Signals
signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_SBITERR : std_logic;
signal AXI_W_DBITERR : std_logic;
signal AXI_W_OVERFLOW : std_logic;
signal AXI_W_UNDERFLOW : std_logic;
signal AXI_W_PROG_FULL : STD_LOGIC;
signal AXI_W_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Response Channel Signals
signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_SBITERR : std_logic;
signal AXI_B_DBITERR : std_logic;
signal AXI_B_OVERFLOW : std_logic;
signal AXI_B_UNDERFLOW : std_logic;
signal AXI_B_PROG_FULL : STD_LOGIC;
signal AXI_B_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Address Channel Signals
signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_SBITERR : std_logic;
signal AXI_AR_DBITERR : std_logic;
signal AXI_AR_OVERFLOW : std_logic;
signal AXI_AR_UNDERFLOW : std_logic;
signal AXI_AR_PROG_FULL : STD_LOGIC;
signal AXI_AR_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Data Channel Signals
signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_SBITERR : std_logic;
signal AXI_R_DBITERR : std_logic;
signal AXI_R_OVERFLOW : std_logic;
signal AXI_R_UNDERFLOW : std_logic;
signal AXI_R_PROG_FULL : STD_LOGIC;
signal AXI_R_PROG_EMPTY : STD_LOGIC;
-- AXI Streaming FIFO Related Signals
signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_SBITERR : std_logic;
signal AXIS_DBITERR : std_logic;
signal AXIS_OVERFLOW : std_logic;
signal AXIS_UNDERFLOW : std_logic;
signal AXIS_PROG_FULL : STD_LOGIC;
signal AXIS_PROG_EMPTY : STD_LOGIC;
begin --(architecture implementation)
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- BRAM implementations of a basic Sync FIFO
--
-------------------------------------------------------------------------------
I_BASIC_SFIFO : entity fifo_generator_v12_0.fifo_generator_v12_0
generic map(
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => C_DATA_COUNT_WIDTH,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => C_DWIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_DWIDTH,
C_ENABLE_RLOCS => 0, -- n0
C_FAMILY => C_FAMILY,
C_HAS_ALMOST_EMPTY => 0, -- n0
C_HAS_ALMOST_FULL => 0, -- n0
C_HAS_BACKUP => 0, -- n0
C_HAS_DATA_COUNT => C_HAS_DATA_COUNT,
C_HAS_MEMINIT_FILE => 0, -- n0
C_HAS_OVERFLOW => 0, -- n0
C_HAS_RD_DATA_COUNT => 0, -- n0
C_HAS_RD_RST => 0, -- n0
C_HAS_RST => 0, -- n0
C_HAS_SRST => 1, -- yes
C_HAS_UNDERFLOW => 0, -- n0
C_HAS_VALID => 0, -- n0
C_HAS_WR_ACK => 0, -- n0
C_HAS_WR_DATA_COUNT => 0, -- n0
C_HAS_WR_RST => 0, -- n0
C_IMPLEMENTATION_TYPE => 0, -- Common clock BRAM
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => C_MEMORY_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY,
C_PRELOAD_REGS => C_PRELOAD_REGS,
C_PRIM_FIFO_TYPE => "512x36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 0,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 0,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 0,
C_PROG_FULL_THRESH_NEGATE_VAL => 0,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => C_DATA_COUNT_WIDTH,
C_RD_DEPTH => C_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => POINTER_WIDTH,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_EMBEDDED_REG => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => C_USE_FWFT_DATA_COUNT,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => C_DATA_COUNT_WIDTH,
C_WR_DEPTH => C_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => POINTER_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_USE_ECC => 0,
C_FULL_FLAGS_RST_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
C_HAS_INT_CLK => 0,
C_MSGON_VAL => 1,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_AXI_LEN_WIDTH => 8, -- : integer := 8;
C_AXI_LOCK_WIDTH => 2, -- : integer := 2;
C_HAS_AXI_ID => 0, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map(
backup => '0',
backup_marker => '0',
clk => CLK,
rst => '0',
srst => SRST,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => DIN, -- uses this one
wr_en => WR_EN, -- uses this one
rd_en => RD_EN, -- uses this one
prog_empty_thresh => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS,
prog_full_thresh => PROG_WRTHRESH_ZEROS,
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS,
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS,
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => DOUT, -- uses this one
full => FULL, -- uses this one
almost_full => ALMOST_FULL,
wr_ack => WR_ACK,
overflow => OVERFLOW,
empty => EMPTY, -- uses this one
almost_empty => ALMOST_EMPTY,
valid => VALID,
underflow => UNDERFLOW,
data_count => DATA_COUNT, -- uses this one
rd_data_count => RD_DATA_COUNT,
wr_data_count => WR_DATA_COUNT,
prog_full => PROG_FULL,
prog_empty => PROG_EMPTY,
sbiterr => SBITERR,
dbiterr => DBITERR,
wr_rst_busy => WR_RST_BUSY,
rd_rst_busy => RD_RST_BUSY,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end implementation;
| apache-2.0 | 8f15c6c078efc43f32ef16cd3eb69a86 | 0.436177 | 3.637192 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-30bits_outputs31bits/3-ARF/metaheurísticas/arf_hype.vhd | 1 | 2,603 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-13.07:34:57)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY arf_hype_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8: IN unsigned(0 TO 30);
output1, output2: OUT unsigned(0 TO 31));
END arf_hype_entity;
ARCHITECTURE arf_hype_description OF arf_hype_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register4: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register5: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register6: unsigned(0 TO 31) := "00000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
register2 := input2 * 2;
WHEN "00000010" =>
register1 := register1 + register2;
register2 := input3 * 3;
register3 := input4 * 4;
WHEN "00000011" =>
register4 := input5 * 5;
register1 := register1 + 7;
register5 := input6 * 8;
register2 := register3 + register2;
WHEN "00000100" =>
register3 := input7 * 9;
register6 := input8 * 10;
register4 := register5 + register4;
WHEN "00000101" =>
register5 := register1 * 12;
register1 := register1 * 14;
register3 := register3 + register6;
register4 := register4 + 16;
WHEN "00000110" =>
register6 := register4 * 18;
register4 := register4 * 20;
WHEN "00000111" =>
register1 := register1 + register4;
register4 := register5 + register6;
WHEN "00001000" =>
register5 := register4 * 22;
register6 := register1 * 24;
WHEN "00001001" =>
register1 := register1 * 26;
register4 := register4 * 28;
register5 := register5 + register6;
WHEN "00001010" =>
register1 := register4 + register1;
output1 <= register3 + register5;
WHEN "00001011" =>
output2 <= register2 + register1;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END arf_hype_description; | gpl-3.0 | 5d4f566d6dae5c351eb30f4a3a40f5ea | 0.676911 | 3.311705 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/builtin/builtin_prim_v6.vhd | 5 | 37,128 | `protect begin_protected
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`protect end_protected
| apache-2.0 | e45afcdefd0d93307155d1d0141faba2 | 0.948368 | 1.827165 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/5-EWF/metaheurísticas/ewf_hype.vhd | 1 | 2,968 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-17.11:31:21)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY ewf_hype_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2: IN unsigned(0 TO 3);
output1, output2, output3, output4, output5: OUT unsigned(0 TO 4));
END ewf_hype_entity;
ARCHITECTURE ewf_hype_description OF ewf_hype_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
WHEN "00000010" =>
register2 := register1 + 3;
register3 := input2 + 4;
WHEN "00000011" =>
register4 := register2 + 6;
WHEN "00000100" =>
register4 := register3 + register4;
WHEN "00000101" =>
register5 := register4 * 8;
register6 := register4 * 10;
WHEN "00000110" =>
register5 := register2 + register5;
WHEN "00000111" =>
register2 := register2 + register5;
WHEN "00001000" =>
register2 := register2 * 12;
WHEN "00001001" =>
register2 := register1 + register2;
WHEN "00001010" =>
register1 := register1 + register2;
WHEN "00001011" =>
register1 := register1 * 14;
WHEN "00001100" =>
register1 := register1 + 16;
WHEN "00001101" =>
output1 <= register2 + register1;
register1 := register5 + register2;
register2 := register4 + register5;
WHEN "00001110" =>
register4 := register3 + register6;
WHEN "00001111" =>
register3 := register3 + register4;
output2 <= register4 + register2;
register1 := register1 + 20;
WHEN "00010000" =>
register2 := register1 * 22;
WHEN "00010001" =>
register2 := register2 + 24;
WHEN "00010010" =>
output3 <= register1 + register2;
register1 := register3 * 27;
WHEN "00010011" =>
register1 := register1 + 29;
WHEN "00010100" =>
register2 := register4 + register1;
register3 := register1 + 31;
WHEN "00010101" =>
register3 := register3 * 33;
WHEN "00010110" =>
output4 <= register1 + register3;
register1 := register2 + 36;
WHEN "00010111" =>
register2 := register1 * 38;
WHEN "00011000" =>
register2 := register2 + 40;
WHEN "00011001" =>
output5 <= register1 + register2;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END ewf_hype_description; | gpl-3.0 | 9c41cf2e3cdfe9c78bcc8e2ba9bd67b2 | 0.645216 | 3.157447 | false | false | false | false |
CyAScott/CIS4930.DatapathSynthesisTool | src/components/c_adder.vhd | 1 | 1,914 | library ieee;
use ieee.std_logic_1164.all;
library WORK;
use WORK.all;
entity c_adder is
generic
(
width : integer := 4
);
port
(
input1, input2 : in std_logic_vector((width - 1) downto 0);
output : out std_logic_vector(width downto 0)
);
end c_adder;
architecture behavior of c_adder is
begin
P0 : process (input1, input2)
variable carry : std_logic := '0';
variable overflow : std_logic := '0';
variable temp : std_logic_vector(width downto 0);
begin
for i in 0 to width - 1 loop
if input1(i) = '0' and input2(i) = '0' and carry = '0' then
temp(i) := '0';
carry := '0';
elsif input1(i) = '0' and input2(i) = '0' and carry = '1' then
temp(i) := '1';
carry := '0';
elsif input1(i) = '0' and input2(i) = '1' and carry = '0' then
temp(i) := '1';
carry := '0';
elsif input1(i) = '0' and input2(i) = '1' and carry = '1' then
temp(i) := '0';
carry := '1';
elsif input1(i) = '1' and input2(i) = '0' and carry = '0' then
temp(i) := '1';
carry := '0';
elsif input1(i) = '1' and input2(i) = '0' and carry = '1' then
temp(i) := '0';
carry := '1';
elsif input1(i) = '1' and input2(i) = '1' and carry = '0' then
temp(i) := '0';
carry := '1';
elsif input1(i) = '1' and input2(i) = '1' and carry = '1' then
temp(i) := '1';
carry := '1';
end if;
end loop;
temp(width) := carry;
carry := '0';
output <= temp;
if ((input1(width - 1) = '0') and (input2(width - 1) = '0') and (temp(width) = '1')) then
overflow := '1';
elsif ((input1(width - 1) = '1') and (input2(width - 1) = '1') and (temp(width) = '0')) then
overflow := '1';
elsif ((input1(width - 1) = '0') and (input2(width - 1) = '1') and (temp(width) = '1')) then
overflow := '1';
elsif ((input1(width - 1) = '1') and (input2(width - 1) = '0') and (temp(width) = '0')) then
overflow := '1';
end if;
end process;
end behavior; | mit | 7a5634411e1cf54f9cdcf83695ef5a60 | 0.541275 | 2.469677 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/builtin/reset_builtin.vhd | 5 | 19,078 | `protect begin_protected
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`protect end_protected
| apache-2.0 | 20d693ea6579343ed5b2706d59f22acf | 0.939249 | 1.86254 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/6-FIR2/metaheurísticas/fir2_ibea.vhd | 1 | 3,283 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-26.14:51:59)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY fir2_ibea_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16: IN unsigned(0 TO 3);
output1: OUT unsigned(0 TO 4));
END fir2_ibea_entity;
ARCHITECTURE fir2_ibea_description OF fir2_ibea_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := not input1 or input1;
register2 := not input2 or input2;
WHEN "00000010" =>
register1 := register1 + register2;
register2 := not input3 or input3;
register3 := not input4 or input4;
register4 := not input5 or input5;
register5 := not input6 or input6;
WHEN "00000011" =>
register6 := not input7 or input7;
register4 := register4 + register5;
register5 := not input8 or input8;
register1 := register1 * 10;
WHEN "00000100" =>
register5 := register5 + register6;
register6 := not input9 or input9;
WHEN "00000101" =>
register2 := register2 + register6;
register5 := register5 * 13;
register6 := not input10 or input10;
register4 := register4 * 16;
register7 := not input11 or input11;
WHEN "00000110" =>
register4 := register4 + register5;
register2 := register2 * 19;
register5 := not input12 or input12;
register8 := not input13 or input13;
register6 := register6 + register7;
WHEN "00000111" =>
register3 := register5 + register3;
register5 := register6 * 23;
register6 := not input14 or input14;
WHEN "00001000" =>
register3 := register3 * 26;
register4 := register5 + register4;
register5 := register8 + register6;
WHEN "00001001" =>
register5 := register5 * 28;
register2 := register2 + register4;
register4 := not input15 or input15;
WHEN "00001010" =>
register2 := register5 + register2;
register5 := not input16 or input16;
WHEN "00001011" =>
register2 := register3 + register2;
register3 := register5 + register4;
WHEN "00001100" =>
register1 := register1 + register2;
register2 := register3 * 32;
WHEN "00001101" =>
register1 := register2 + register1;
WHEN "00001110" =>
output1 <= to_unsigned(2 ** to_integer(register1), 4);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END fir2_ibea_description; | gpl-3.0 | 02309123d6c92dd49836df3067f90b0c | 0.669814 | 3.190476 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/conv_funs_pkg.vhd | 15 | 15,316 | -------------------------------------------------------------------------------
-- $Id: conv_funs_pkg.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
----------------------------------------------------------------------------
-- conv_funs_pkg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
----------------------------------------------------------------------------
-- Filename: conv_funs_pkg.vhd
--
-- Description:
-- Various string conversion functions.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- conv_funs_pkg.vhd
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: unknown
-- Revision: $Revision: 1.1.4.1 $
-- Date: $1/1/2002$
--
-- History:
-- XXX 1/1/2002 Initial Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package conv_funs_pkg is
-- hex string to std_logic_vector
function hex_string_to_slv (instring : STRING;
return_length : POSITIVE range 1 to 64 := 32)
return STD_LOGIC_VECTOR;
-- octal string to std_logic_vector
function oct_string_to_slv (instring : STRING;
return_length : POSITIVE range 1 to 64 := 32)
return STD_LOGIC_VECTOR;
-- binary string to std_logic_vector
function bin_string_to_slv (instring : STRING;
return_length : POSITIVE range 1 to 64 := 32)
return STD_LOGIC_VECTOR;
-- string to std_logic_vector
function string_to_std_logic_vector (instring : STRING;
return_length : POSITIVE range 1 to 64 := 32)
return STD_LOGIC_VECTOR;
end conv_funs_pkg;
--
--------------------------------------------------------------------------------
--
package body conv_funs_pkg is
type basetype is (binary, octal, decimal, hex);
function max(x, y : INTEGER) return INTEGER is
begin
if x > y then return x; else return y; end if;
end max;
function MIN(x, y : INTEGER) return INTEGER is
begin
if x < y then return x; else return y; end if;
end MIN;
function hex_string_to_slv (instring : STRING;
return_length : POSITIVE range 1 to 64 := 32)
return STD_LOGIC_VECTOR is
-- if return_length is < than instring'length*4, result will be truncated on the left
-- if instring is other than characters 0 to 9 or a,A to f,F or
-- x,X,z,Z,u,U,-,w,W,
-- those result bits will be set to 0
variable temp_string : STRING(1 to instring'LENGTH) := instring;
variable vector_size : POSITIVE := max(instring'LENGTH*4, return_length);
variable char_ptr : INTEGER range -3 to max(instring'LENGTH*4, return_length) := max(instring'LENGTH*4, return_length);
variable return_vector : STD_LOGIC_VECTOR(1 to max(instring'LENGTH*4, return_length)) := (others => '0');
begin
for i in temp_string'REVERSE_RANGE loop
case temp_string(i) is
when '0' => return_vector(char_ptr-3 to char_ptr) := "0000";
when '1' => return_vector(char_ptr-3 to char_ptr) := "0001";
when '2' => return_vector(char_ptr-3 to char_ptr) := "0010";
when '3' => return_vector(char_ptr-3 to char_ptr) := "0011";
when '4' => return_vector(char_ptr-3 to char_ptr) := "0100";
when '5' => return_vector(char_ptr-3 to char_ptr) := "0101";
when '6' => return_vector(char_ptr-3 to char_ptr) := "0110";
when '7' => return_vector(char_ptr-3 to char_ptr) := "0111";
when '8' => return_vector(char_ptr-3 to char_ptr) := "1000";
when '9' => return_vector(char_ptr-3 to char_ptr) := "1001";
when 'a'|'A' => return_vector(char_ptr-3 to char_ptr) := "1010";
when 'b'|'B' => return_vector(char_ptr-3 to char_ptr) := "1011";
when 'c'|'C' => return_vector(char_ptr-3 to char_ptr) := "1100";
when 'd'|'D' => return_vector(char_ptr-3 to char_ptr) := "1101";
when 'e'|'E' => return_vector(char_ptr-3 to char_ptr) := "1110";
when 'f'|'F' => return_vector(char_ptr-3 to char_ptr) := "1111";
-- xst doesn't handle these
-- when 'U' => return_vector(char_ptr-3 to char_ptr) := "UUUU";
-- when 'X' => return_vector(char_ptr-3 to char_ptr) := "XXXX";
-- when 'Z' => return_vector(char_ptr-3 to char_ptr) := "ZZZZ";
-- when 'W' => return_vector(char_ptr-3 to char_ptr) := "WWWW";
-- when 'H' => return_vector(char_ptr-3 to char_ptr) := "HHHH";
-- when 'L' => return_vector(char_ptr-3 to char_ptr) := "LLLL";
-- when '-' => return_vector(char_ptr-3 to char_ptr) := "----";
-- but synplicity does
when '_' => char_ptr := char_ptr + 4;
when others =>
assert FALSE
report lf &
"hex_string_to_slv conversion found illegal input character: " &
temp_string(i) & lf & "converting character to '----'"
severity WARNING;
return_vector(char_ptr-3 to char_ptr) := "----";
end case;
char_ptr := char_ptr - 4;
end loop;
return return_vector(vector_size-return_length+1 to vector_size);
end hex_string_to_slv;
function oct_string_to_slv (instring : STRING;
return_length : POSITIVE range 1 to 64 := 32)
return STD_LOGIC_VECTOR is
-- if return_length is < than instring'length*3, result will be truncated on the left
-- if instring is other than characters 0 to 7 or or x,X,z,Z,u,U,-,w,W,
-- those result bits will be set to 0
variable temp_string : STRING(1 to instring'LENGTH) := instring;
variable vector_size : POSITIVE := max(instring'LENGTH*3, return_length);
variable char_ptr : INTEGER range -2 to max(instring'LENGTH*3, return_length) := max(instring'LENGTH*3, return_length);
variable return_vector : STD_LOGIC_VECTOR(1 to max(instring'LENGTH*3, return_length)) := (others => '0');
begin
for i in temp_string'REVERSE_RANGE loop
case temp_string(i) is
when '0' => return_vector(char_ptr-2 to char_ptr) := "000";
when '1' => return_vector(char_ptr-2 to char_ptr) := "001";
when '2' => return_vector(char_ptr-2 to char_ptr) := "010";
when '3' => return_vector(char_ptr-2 to char_ptr) := "011";
when '4' => return_vector(char_ptr-2 to char_ptr) := "100";
when '5' => return_vector(char_ptr-2 to char_ptr) := "101";
when '6' => return_vector(char_ptr-2 to char_ptr) := "110";
when '7' => return_vector(char_ptr-2 to char_ptr) := "111";
-- xst doesn't handle these
-- when 'U' => return_vector(char_ptr-2 to char_ptr) := "UUU";
-- when 'X' => return_vector(char_ptr-2 to char_ptr) := "XXX";
-- when 'Z' => return_vector(char_ptr-2 to char_ptr) := "ZZZ";
-- when 'W' => return_vector(char_ptr-2 to char_ptr) := "WWW";
-- when 'H' => return_vector(char_ptr-2 to char_ptr) := "HHH";
-- when 'L' => return_vector(char_ptr-2 to char_ptr) := "LLL";
-- when '-' => return_vector(char_ptr-2 to char_ptr) := "---";
-- but synplicity does
when '_' => char_ptr := char_ptr + 3;
when others =>
assert FALSE
report lf &
"oct_string_to_slv conversion found illegal input character: " &
temp_string(i) & lf & "converting character to '---'"
severity WARNING;
return_vector(char_ptr-2 to char_ptr) := "---";
end case;
char_ptr := char_ptr - 3;
end loop;
return return_vector(vector_size-return_length+1 to vector_size);
end oct_string_to_slv;
function bin_string_to_slv (instring : STRING;
return_length : POSITIVE range 1 to 64 := 32)
return STD_LOGIC_VECTOR is
-- if return_length is < than instring'length, result will be truncated on the left
-- if instring is other than characters 0 to 1 or x,X,z,Z,u,U,-,w,W,
-- those result bits will be set to 0
variable temp_string : STRING(1 to instring'LENGTH) := instring;
variable vector_size : POSITIVE := max(instring'LENGTH, return_length);
variable char_ptr : INTEGER range 0 to max(instring'LENGTH, return_length)+1 := max(instring'LENGTH, return_length);
variable return_vector : STD_LOGIC_VECTOR(1 to max(instring'LENGTH, return_length)) := (others => '0');
begin
for i in temp_string'REVERSE_RANGE loop
case temp_string(i) is
when '0' => return_vector(char_ptr) := '0';
when '1' => return_vector(char_ptr) := '1';
-- xst doesn't handle these
-- when 'U' => return_vector(char_ptr) := 'U';
-- when 'X' => return_vector(char_ptr) := 'X';
-- when 'Z' => return_vector(char_ptr) := 'Z';
-- when 'W' => return_vector(char_ptr) := 'W';
-- when 'H' => return_vector(char_ptr) := 'H';
-- when 'L' => return_vector(char_ptr) := 'L';
-- when '-' => return_vector(char_ptr) := '-';
-- but synplicity does
when '_' => char_ptr := char_ptr + 1;
when others =>
assert FALSE
report lf &
"bin_string_to_slv conversion found illegal input character: " &
temp_string(i) & lf & "converting character to '-'"
severity WARNING;
return_vector(char_ptr) := '-';
end case;
char_ptr := char_ptr - 1;
end loop;
return return_vector(vector_size-return_length+1 to vector_size);
end bin_string_to_slv;
function string_to_std_logic_vector (instring : STRING;
return_length : POSITIVE range 1 to 64 := 32)
return STD_LOGIC_VECTOR is
variable instring_length : POSITIVE := instring'LENGTH;
variable temp_string : STRING(1 to instring'LENGTH-2);
begin -- function string_to_std_logic_vector
if instring(1) = '0' and (instring(2) = 'x' or instring(2) = 'X') then
temp_string := instring(3 to instring_length);
return hex_string_to_slv(temp_string, return_length);
elsif instring(1) = '0' and (instring(2) = 'o' or instring(2) = 'O') then
temp_string := instring(3 to instring_length);
return oct_string_to_slv(temp_string, return_length);
elsif instring(1) = '0' and (instring(2) = 'b' or instring(2) = 'B') then
temp_string := instring(3 to instring_length);
return bin_string_to_slv(temp_string, return_length);
else
return bin_string_to_slv(instring, return_length);
end if;
end function string_to_std_logic_vector;
end conv_funs_pkg;
| apache-2.0 | 2c428c1574c757e7bd0b99b64a97300c | 0.501828 | 4.08209 | false | false | false | false |
rcls/sdr | vhdl/phasedetect.vhd | 1 | 7,140 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.defs.all;
entity phasedetect is
port(xx_in : in signed36; -- overkill, could have reduced to 18 bits by now.
yy_in : in signed36;
in_last : in std_logic;
phase : out unsigned18;
out_strobe : out std_logic;
out_last : out std_logic;
phasor_last : in unsigned18;
clk : in std_logic);
end phasedetect;
-- The main phase detect uses a pipeline, 16 iterations, main usage is
-- (iterations 1 to 15):
-- stage1: yy_div = yy right-shifted (by 2n).
-- stage2: trial xx' = xx + yy_div, yy' = yy - xx
-- stage3: commit, if yy' has not underflown, update angle.
-- We want to reuse the first time through the pipeline:
-- shift=0. If no underflow, then swap xx and yy.
-- We load every 20 (?) cycles,
-- and ship out 60 cycles later.
-- The phase detection is bypassed when out_last is asserted; we take
-- phasor_last instead.
architecture behavioural of phasedetect is
constant width : integer := 20;
subtype xunsigned is unsigned(width - 1 downto 0);
subtype yunsigned is unsigned(width downto 0);
signal shift : boolean;
signal x_shift, y_shift : unsigned36;
signal shift_last : std_logic;
signal xx1 : xunsigned; -- Real component.
signal yy1 : yunsigned; -- Imaginary component.
signal last1 : std_logic;
signal angle1 : unsigned18; -- Accumulated angle.
signal positive1 : boolean; -- Positive adjustments to angle.
signal xx2 : xunsigned;
signal yy2 : yunsigned;
signal yy2_shifted : yunsigned;
signal angle2 : unsigned18;
signal positive2 : boolean;
signal load2 : boolean;
signal last2 : std_logic;
signal xx3 : xunsigned;
signal yy3 : yunsigned;
signal xx3_trial : xunsigned;
signal yy3_trial : yunsigned;
signal angle3 : unsigned18;
signal angle3_update : unsigned16;
signal positive3 : boolean;
signal start3 : boolean;
signal last3 : std_logic;
signal count : integer range 0 to 19;
type stage_t is array(0 to 19) of integer range 0 to 19;
-- For pipeline stage 1, map the cycle counter to the iteration of the
-- calculation.
constant iteration1 : stage_t :=
(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19);
-- Iteration number for pipeline stage 2.
constant iteration2 : stage_t :=
(13, 14, 15, 16, 17, 18, 19, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12);
-- Iteration number for pipeline stage 3.
constant iteration3 : stage_t :=
(6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 0, 1, 2, 3, 4, 5);
-- Angle updates. Exhaustive testing indicates that the odd first value is
-- best.
type angles_t is array(0 to 19) of unsigned16;
constant angle_update : angles_t :=
(x"fffe", x"4b90", x"27ed", x"1444",
x"0a2c", x"0517", x"028c", x"0146",
x"00a3", x"0051", x"0029", x"0014",
x"000a", x"0005", x"0003", x"0001",
x"0000", x"0000", x"0000", x"0000");
begin
process
begin
wait until rising_edge(clk);
-- Preprocess each sample for 20 cycles, left shifting as much as possible.
-- This reduces the precision required in the main calculations.
if shift then
if load2 then
x_shift <= unsigned(xx_in);
y_shift <= unsigned(yy_in);
shift_last <= in_last;
else
x_shift <= x_shift sll 1;
y_shift <= y_shift sll 1;
end if;
end if;
if count = 19 then
shift <= true; -- Same cycle as load2.
elsif load2 then
shift <= xx_in(35) = xx_in(34) and yy_in(35) = yy_in(34);
else
shift <= shift and
x_shift(34) = x_shift(33) and y_shift(34) = y_shift(33);
end if;
if count >= 13 then
count <= count - 13;
else
count <= count + 7;
end if;
start3 <= (count = 7);
-- The default flow is just to cycle things around; override later if
-- need be.
xx2 <= xx1;
yy2 <= yy1;
angle2 <= angle1;
positive2 <= positive1;
last2 <= last1;
xx3 <= xx2;
-- Include left shift. If this loses a bit, then the trial will succeed
-- anyway, and get us back.
yy3 <= yy2 sll 1;
angle3 <= angle2;
positive3 <= positive2;
last3 <= last2;
xx1 <= xx3;
yy1 <= yy3;
angle1 <= angle3;
positive1 <= positive3;
last1 <= last3;
-- First pipeline stage is the right shift. Note that for the start
-- iteration, the high bit of yy is still zero, so the high bit of
-- yy_shifted will always be zero.
yy2_shifted <= yy1 srl (2 * (count mod 16));
load2 <= (count = 19);
-- Second pipeline stage is the trial operation. It also handles the
-- loading of data into the pipeline.
xx3_trial <= xx2 + yy2_shifted(width - 1 downto 0);
-- Note that yy is at most twice the 36 bit xx, so if the arithmetic does
-- not overflow, then the result of the subtract will fit in 36 bits.
-- Except for round-0 (where we normalise to the first octant). In that
-- case everything is 36 bits.
yy3_trial <= yy2 - ('0' & xx2);
angle3_update <= angle_update(iteration2(count));
if load2 then
last3 <= shift_last;
yy3_trial(width) <= '1'; -- Make sure we don't adjust on next cycle.
-- 'not' is cheaper than proper true negation. And given our
-- round-towards-negative behaviour, more accurate.
if x_shift(35) = '0' then
xx3 <= x_shift(35 downto 36 - width);
else
xx3 <= not x_shift(35 downto 36 - width);
end if;
if y_shift(35) = '0' then
yy3 <= '0' & y_shift(35 downto 36 - width);
else
yy3 <= '0' & not y_shift(35 downto 36 - width);
end if;
positive3 <= (x_shift(35) xor y_shift(35)) = '1';
-- Our convention is that angle zero covers the first sliver of the
-- first quadrant etc., so bias the start angle just into the
-- appropriate quadrant. Yes the 0=>1 looks like a step too far,
-- but after exhaustive testing, it gives better results, presumably
-- because of the granularity of the result.
angle3 <= (17 => y_shift(35), 0 => '1',
others => x_shift(35) xor y_shift(35));
if last2 = '1' then
phase <= phasor_last;
else
phase <= angle2; -- ship out previous result.
end if;
out_last <= last2;
end if;
out_strobe <= b2s(load2);
-- Third pipeline stage is commitment.
if yy3_trial(width) = '0' then
if not start3 then
xx1 <= xx3_trial;
-- yy got left shifted at the previous stage, but yy_trial did not.
-- so take that into account.
yy1 <= yy3_trial sll 1;
else
-- No overflow, yy is bigger than xx, so swap things over. Remember
-- that yy got left shifted, so take that into account in the swap.
xx1 <= yy3(width downto 1);
yy1 <= xx3 & '0';
positive1 <= not positive3;
end if;
if positive3 then
angle1 <= angle3 + ("00" & angle3_update);
else
angle1 <= angle3 - ("00" & angle3_update);
end if;
end if;
end process;
end behavioural;
| gpl-3.0 | fb32a8164a83c411501d8b2ab6d1d8e5 | 0.609664 | 3.4 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/daxi_interface.vhd | 1 | 27,637 | `protect begin_protected
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4RY6vqnYpulG+sxmK6jwV9ZhBGU0HU2eU+FwUQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 18720)
`protect data_block
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| apache-2.0 | eb5dbd2113e30124c7af3e951fd4eee6 | 0.94511 | 1.841485 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/byte_doublet_handle.vhd | 1 | 57,553 | `protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 40864)
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`protect end_protected
| apache-2.0 | f4524bbe3696ee0d544e8fc565f3b6dc | 0.95121 | 1.822162 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/cachehit_detect.vhd | 1 | 30,555 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
| apache-2.0 | 369a351b49c15964bb16aae13dc864e6 | 0.944919 | 1.829422 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/microblaze_primitives.vhd | 1 | 13,415 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8192)
`protect data_block
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`protect end_protected
| apache-2.0 | 0976abc38440e0d8f91fdff9b45f24b6 | 0.933805 | 1.886779 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/builtin/clk_x_pntrs_builtin.vhd | 5 | 43,418 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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c5AWr6la2WH4+kGWfZg=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 30400)
`protect data_block
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| apache-2.0 | 9041a3bc9b7cc10892b1cf0e40c3a4b8 | 0.948708 | 1.822677 | false | false | false | false |
marceloboeira/vhdl-examples | 008-state-machine-calculator/_example/hex2bcd.vhd | 1 | 2,692 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
entity hex2bcd is
port ( CLK : in std_logic;
--PUSH BUTTONS PIN ASSIGNMENT
--SWITCH PIN ASSIGNMENT
sw0 :in std_logic_vector(3 downto 0);
sw1 :in std_logic_vector(3 downto 0);
sw2 :in std_logic_vector(3 downto 0);
sw3 :in std_logic_vector(3 downto 0);
--YOU COULD HAVE ALSO WRITTEN
-- sw: in std_logic_vector(17 downto 0);
-- that would have worked too. But I did another project, SO I just kept it like that. Quartus is a pain in the butt when assigning pin. Its so time consuming and stupid :P
bcd0:out std_logic_vector(3 downto 0);
bcd1:out std_logic_vector(3 downto 0);
bcd2:out std_logic_vector(3 downto 0);
bcd3:out std_logic_vector(3 downto 0));
end hex2bcd;
architecture behavior of hex2bcd is
begin
--You cannot have variables here
my_proc: process (CLK)
--Variable assignment
variable random: std_logic_vector(15 downto 0) := "0000000000000000"; --16 BITS
variable one: std_logic_vector(3 downto 0) := "0000";
variable ten: std_logic_vector(3 downto 0) := "0000";
variable hund: std_logic_vector(3 downto 0) := "0000";
variable thou: std_logic_vector(3 downto 0) := "0000";
variable tthou: std_logic_vector(3 downto 0) := "0000";
variable hthou: std_logic_vector(3 downto 0) := "0000";
begin
--ON RISING EDGE OF CLOCK, DO THIS FUNCTION
if (rising_edge(CLK)) then
random := sw3 & sw2 & sw1 & sw0;
for i in 0 to 15 loop
--CHECKING IF THE NUMBER IS GREATER OR EQUAL TO 5
-- IF YES, THEN ADD 3
-- NOTE: THIS IS NOT THE MOST EFFICIENT WAY TO DO IT. But who cares :P!
if (hthou >= "0101") then
hthou := std_logic_vector (unsigned(hthou) +3);
end if;
if (tthou >= "0101") then
tthou := std_logic_vector (unsigned(tthou) +3);
end if;
if (thou >= "0101") then
thou := std_logic_vector (unsigned(thou) +3);
end if;
if (hund >= "0101") then
hund := std_logic_vector (unsigned(hund) +3);
end if;
if (ten >= "0101") then
ten := std_logic_vector (unsigned(ten) +3);
end if;
if (one >= "0101") then
one := std_logic_vector (unsigned(one) +3);
end if;
-- HERE I AM DOING THE SHIFTING WORK
hthou := hthou(2 downto 0) & tthou(3);
tthou := tthou(2 downto 0) & thou(3);
thou := thou(2 downto 0)& hund(3);
hund := hund(2 downto 0)& ten(3);
ten := ten(2 downto 0)& one(3);
one := one(2 downto 0)& random(15);
random := std_logic_vector(unsigned(random) sll 1);
end loop;
bcd0 <= one;
bcd1 <= ten;
bcd2 <= hund;
bcd3 <= thou;
one := "0000";
ten:= "0000";
hund := "0000";
thou := "0000";
tthou:= "0000";
hthou:= "0000";
end if;
end process ;
end behavior;
| mit | 9c6fff009452af333a86dfa306de398d | 0.639302 | 2.842661 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/srl_fifo2.vhd | 15 | 14,428 | -------------------------------------------------------------------------------
-- $Id: srl_fifo2.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo2 - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo2.vhd
--
-- Description: same as srl_fifo except the Addr port has the correct bit
-- ordering, there is a true FIFO_Empty port, and the C_DEPTH
-- generic actually controlls how many elements the fifo will
-- hold (up to 16). includes an assertion statement to check
-- that C_DEPTH is less than or equal to 16. changed
-- C_DATA_BITS to C_DWIDTH and changed it from natural to
-- positive (the width should be 1 or greater, zero width
-- didn't make sense to me!). Changed C_DEPTH from natural
-- to positive (zero elements doesn't make sense).
-- The Addr port in srl_fifo has the bits reversed which
-- made it more difficult to use. C_DEPTH was not used in
-- srl_fifo. Data_Exists is delayed by one clock so it is
-- not usefull for generating an empty flag. FIFO_Empty is
-- generated directly from the address, the same way that
-- FIFO_Full is generated.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo2.vhd
--
-------------------------------------------------------------------------------
-- Author: jam
--
-- History:
-- jam 02/20/02 First Version - modified from original srl_fifo
--
-- DCW 2002-03-12 Structural implementation of synchronous reset for
-- Data_Exists DFF (using FDR)
-- jam 04/12/02 Added C_XON generic for mixed vhdl/verilog sims
--
-- als 2002-04-18 added default for XON generic in SRL16E, FDRE, and FDR
-- component declarations
-- jam 2002-05-01 changed FIFO_Empty output from buffer_Empty, which had a
-- clock delay, to the not of data_Exists_I, which doesn't
-- have any delay
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
library unisim;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; -- conv_std_logic_vector
use unisim.all;
entity srl_fifo2 is
generic (
C_DWIDTH : positive := 8; -- changed to positive
C_DEPTH : positive := 16; -- changed to positive
C_XON : boolean := false -- added for mixed mode sims
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic; -- new port
Data_Exists : out std_logic;
Addr : out std_logic_vector(0 to 3)
);
end entity srl_fifo2;
architecture imp of srl_fifo2 is
-- convert C_DEPTH to a std_logic_vector so FIFO_Full can be generated
-- based on the selected depth rather than fixed at 16
constant DEPTH : std_logic_vector(0 to 3) :=
conv_std_logic_vector(C_DEPTH-1,4);
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16E;
-- component LUT4
-- generic(
-- INIT : bit_vector := X"0000"
-- );
-- port (
-- O : out std_logic;
-- I0 : in std_logic;
-- I1 : in std_logic;
-- I2 : in std_logic;
-- I3 : in std_logic);
-- end component;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDRE;
component FDR is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDR;
signal addr_i : std_logic_vector(0 to 3);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic;
signal data_Exists_I : std_logic;
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to 3);
signal sum_A : std_logic_vector(0 to 3);
signal addr_cy : std_logic_vector(0 to 4);
begin -- architecture IMP
-- C_DEPTH is positive so that ensures the fifo is at least 1 element deep
-- make sure it is not greater than 16 locations deep
-- pragma translate_off
assert C_DEPTH <= 16
report "SRL Fifo's must be 16 or less elements deep"
severity FAILURE;
-- pragma translate_on
-- since srl16 address is 3 downto 0 need to compare individual bits
-- didn't muck with addr_i since the basic addressing works - Addr output
-- is generated correctly below
buffer_Full <= '1' when (addr_i(0) = DEPTH(3) and
addr_i(1) = DEPTH(2) and
addr_i(2) = DEPTH(1) and
addr_i(3) = DEPTH(0)
) else '0';
FIFO_Full <= buffer_Full;
buffer_Empty <= '1' when (addr_i = "0000") else '0';
FIFO_Empty <= not data_Exists_I; -- generate a true empty flag with no delay
-- was buffer_Empty, which had a clock dly
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
Data_Exists_DFF : FDR
port map (
Q => data_Exists_I, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists, -- [in std_logic]
R => Reset); -- [in std_logic]
Data_Exists <= data_Exists_I;
valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
addr_cy(0) <= valid_Write;
Addr_Counters : for I in 0 to 3 generate
hsum_A(I) <= (FIFO_Read xor addr_i(I)) and (FIFO_Write or not buffer_Empty);
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => sum_A(I)); -- [out std_logic]
FDRE_I : FDRE
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_I, -- [in std_logic]
D => sum_A(I), -- [in std_logic]
R => Reset); -- [in std_logic]
end generate Addr_Counters;
FIFO_RAM : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i(0), -- [in std_logic]
A1 => addr_i(1), -- [in std_logic]
A2 => addr_i(2), -- [in std_logic]
A3 => addr_i(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
-------------------------------------------------------------------------------
-- INT_ADDR_PROCESS
-------------------------------------------------------------------------------
-- This process assigns the internal address to the output port
-------------------------------------------------------------------------------
-- modified the process to flip the bits since the address bits from the
-- srl16 are 3 downto 0 and Addr needs to be 0 to 3
INT_ADDR_PROCESS:process (addr_i)
begin -- process
for i in Addr'range
loop
Addr(i) <= addr_i(3 - i); -- flip the bits to account for srl16 addr
end loop;
end process;
end architecture imp;
| apache-2.0 | 622ca906899a9ec6718df3b2bfef51fd | 0.461949 | 4.340554 | false | false | false | false |
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`protect end_protected
| apache-2.0 | 358e8bc992d305e1469b64253d06ccdd | 0.942106 | 1.835239 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/ramfifo/rd_fwft.vhd | 5 | 38,466 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 26736)
`protect data_block
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| apache-2.0 | 0ee1b7bea19d107204301bc1a1fbf957 | 0.949696 | 1.83032 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/7-FIR1/asap-alap-random/fir1_random.vhd | 1 | 4,073 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-26.15:19:46)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY fir1_random_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16, input17, input18, input19, input20, input21, input22: IN unsigned(0 TO 3);
output1: OUT unsigned(0 TO 4));
END fir1_random_entity;
ARCHITECTURE fir1_random_description OF fir1_random_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register9: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register10: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register11: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register12: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register13: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register14: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register15: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register16: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register17: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 and input1;
register2 := input2 and input2;
register3 := input3 and input3;
register4 := input4 and input4;
register5 := input5 and input5;
register6 := input6 and input6;
register7 := input7 and input7;
register8 := input8 and input8;
register9 := input9 and input9;
register10 := input10 and input10;
WHEN "00000010" =>
register11 := input11 and input11;
register12 := input12 and input12;
register13 := input13 and input13;
register14 := input14 and input14;
register6 := register6 * register10;
register10 := input15 and input15;
register15 := input16 and input16;
register8 := register9 * register8;
register9 := input17 and input17;
register16 := input18 and input18;
register17 := input19 and input19;
WHEN "00000011" =>
register14 := register14 * register17;
register1 := register1 * register2;
register2 := register4 * register13;
register4 := input20 and input20;
register13 := input21 and input21;
register7 := register7 * register16;
WHEN "00000100" =>
register13 := register15 * register13;
register4 := register10 * register4;
WHEN "00000101" =>
register1 := register1 + register13;
register3 := register3 * register9;
WHEN "00000110" =>
register3 := register4 + register3;
register4 := register5 * register12;
WHEN "00000111" =>
register3 := register3 + register4;
WHEN "00001000" =>
register3 := register6 + register3;
WHEN "00001001" =>
register1 := register1 + register3;
register3 := input22 and input22;
WHEN "00001010" =>
register3 := register11 * register3;
WHEN "00001011" =>
register3 := register3 + register7;
WHEN "00001100" =>
register1 := register1 + register2;
WHEN "00001101" =>
register1 := register3 + register1;
WHEN "00001110" =>
register1 := register1 + register14;
WHEN "00001111" =>
register1 := register8 + register1;
WHEN "00010000" =>
output1 <= register1 and register1;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END fir1_random_description; | gpl-3.0 | 455d7e0e73e23cf141d09c7d51801738 | 0.683526 | 3.295307 | false | false | false | false |
jdryg/tis100cpu | node_port.vhd | 1 | 3,168 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity node_port is
generic (WIDTH: integer := 8);
port ( I_clk : in STD_LOGIC;
I_reset : in STD_LOGIC;
I_writeEnable: in STD_LOGIC;
I_readEnable: in STD_LOGIC;
I_dataIn : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
O_dataOut : out STD_LOGIC_VECTOR (WIDTH-1 downto 0);
O_dataOutValid : out STD_LOGIC); -- TODO: Check if this is actually needed. We can reset the O_dataOut(0) to Z or U instead.
end node_port;
architecture Behavioral of node_port is
type state_type is (S_EMPTY, S_WAITING_READ, S_WAITING_WRITE);
signal state: state_type;
signal data: STD_LOGIC_VECTOR (WIDTH - 1 downto 0);
begin
state_proc: process (I_clk, I_reset) begin
if (I_reset = '1') then
state <= S_EMPTY;
O_dataOut <= (others => '0');
O_dataOutValid <= '0';
elsif (rising_edge(I_clk)) then
-- Always reset the O_dataOutValid output. The reading node had its chance for a whole clock cycle.
-- Hope it's enough :)
O_dataOutValid <= '0';
case state is
when S_EMPTY =>
report "PORT is EMPTY " & std_logic'image(I_writeEnable) & " " & std_logic'image(I_readEnable);
-- Port is EMPTY. The worst case scenario at this point is one node to write
-- and the other to read, at the same time. Favor writes over reads (1 cycle less to complete the transaction).
if (I_writeEnable = '1') then
data <= I_dataIn;
state <= S_WAITING_READ;
elsif (I_readEnable = '1') then
state <= S_WAITING_WRITE;
end if;
when S_WAITING_READ =>
-- There are 2 ways to end up here.
-- 1) The port was EMPTY and the first request was for a write.
-- In this case the data is valid (already stored in the EMPTY state) so if there's a pending read
-- we can safely output the data (and set the valid bit to 1).
-- 2) The port was EMPTY and the first request was for a read.
-- In this case the port already got through S_WAITING_WRITE, the data is valid, so if there's still
-- a pending read request, we can output the data and set the valid bit to 1).
if (I_readEnable = '1') then
O_dataOut <= data;
O_dataOutValid <= '1';
state <= S_EMPTY;
end if;
when S_WAITING_WRITE =>
-- The only way to end up here is if a port was empty, and a node tried to read from it.
-- It might be possible to do everything in one cycle, but in order to keep things simple
-- I decided to delegate (is this the right word?) the read request to the corresponding state.
-- There's a chance the reader lowered the I_readEnable bit in the meantime (it's not correct
-- behaviour but it might happen).
if (I_writeEnable = '1') then
data <= I_dataIn;
state <= S_WAITING_READ;
end if;
end case;
end if;
end process;
end Behavioral;
| mit | 91d1ba844ca310bc9f12c5ce3af8aa60 | 0.588068 | 3.920792 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/data_read_steering.vhd | 1 | 13,825 | `protect begin_protected
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8496)
`protect data_block
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vbwTtpeoVZDqbsPFPLrSBRJ68W1bpIXAK3hSCec1fYhE/Xn7ZQhWXBW/O+7MNlU+fkuH/FJLtr9o
hYksJhhd4z4yF6Eznw1STMBavvDlbk9pQRg6Fx0wraOLrKGevzZ6E4Nz732fCPC52/r4Tiu1OB/d
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pl1dzj7MPNwQHVIkkKggIzhicmmc2gSM405e5kjcObiaQgJU+ROQ6DSTyqiCFjcXoLvlrmiEEetB
sX2gaBWE4j6QZUqdPN4D83zOaWAc9xp39mVbctqt8lbuaU23W/B6LD86nEaeSTHmOXTXfft0t1Qe
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Hcx2tOO+FrcJnJOEO3fwB5k8NBoqoitsVaysRf+tEua1wTtJ7JIifyS/UbSX/USfhsN+K1Oe+cki
XJZU9v5FlHgYR8Q3ncQRGHiFX9wg7DZ6QVULGR7QwHngSm5VQjIPRGtUPZXCAdxDFLR1pAy/0TN8
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tNs31anyXpJihl/F1z6SQFHEZkw2YZyzrul8Dh4fgrHqc739B8llSJds8FMKupYsh75z9gXWNV1s
b0TkLwb55tFeBgYlO/se8aqpZZmoEoO7wDye6HyhHmqr3NOe/djXdx0Mi+Iz0lSr3pBbeicVgJRx
0lvy
`protect end_protected
| apache-2.0 | 1d15a375d8d32cd79d8fe4cd77702523 | 0.933743 | 1.874576 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/lmb_bram_if_cntlr_v4_0/816dc01c/hdl/vhdl/parity.vhd | 1 | 9,600 | -------------------------------------------------------------------------------
-- $Id: parity.vhd,v 1.1.2.2 2010/09/06 09:01:24 rolandp Exp $
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
------------------------------------------------------------------------------
-- Filename: parity.vhd
--
-- Description: Generate parity optimally for all target architectures
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- parity.vhd
-- xor18.vhd
-- parity_recursive_LUT6.vhd
--
-------------------------------------------------------------------------------
-- Author: stefana
-- Revision: $Revision: 1.1.2.2 $
-- Date: $Date: 2010/09/06 09:01:24 $
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity Parity is
generic (
C_USE_LUT6 : boolean := true;
C_SIZE : integer := 6
);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Res : out std_logic
);
end entity Parity;
library unisim;
use unisim.vcomponents.all;
architecture IMP of Parity is
-- Non-recursive loop implementation
function ParityGen (InA : std_logic_vector) return std_logic is
variable result : std_logic;
begin
result := '0';
for I in InA'range loop
result := result xor InA(I);
end loop;
return result;
end function ParityGen;
begin -- architecture IMP
Using_LUT6 : if (C_USE_LUT6) generate
--------------------------------------------------------------------------------------------------
-- Single LUT6
--------------------------------------------------------------------------------------------------
Single_LUT6 : if C_SIZE > 1 and C_SIZE <= 6 generate
signal inA6 : std_logic_vector(0 to 5);
begin
Assign_InA : process (InA) is
begin
inA6 <= (others => '0');
inA6(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => Res,
I0 => inA6(5),
I1 => inA6(4),
I2 => inA6(3),
I3 => inA6(2),
I4 => inA6(1),
I5 => inA6(0));
end generate Single_LUT6;
--------------------------------------------------------------------------------------------------
-- Two LUT6 and one MUXF7
--------------------------------------------------------------------------------------------------
Use_MUXF7 : if C_SIZE = 7 generate
signal inA7 : std_logic_vector(0 to 6);
signal result6 : std_logic;
signal result6n : std_logic;
begin
Assign_InA : process (InA) is
begin
inA7 <= (others => '0');
inA7(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => result6,
I0 => inA7(5),
I1 => inA7(4),
I2 => inA7(3),
I3 => inA7(2),
I4 => inA7(1),
I5 => inA7(0));
XOR6_LUT_N : LUT6
generic map(
INIT => X"9669699669969669")
port map(
O => result6n,
I0 => inA7(5),
I1 => inA7(4),
I2 => inA7(3),
I3 => inA7(2),
I4 => inA7(1),
I5 => inA7(0));
MUXF7_LUT : MUXF7
port map (
O => Res,
I0 => result6,
I1 => result6n,
S => inA7(6));
end generate Use_MUXF7;
--------------------------------------------------------------------------------------------------
-- Four LUT6, two MUXF7 and one MUXF8
--------------------------------------------------------------------------------------------------
Use_MUXF8 : if C_SIZE = 8 generate
signal inA8 : std_logic_vector(0 to 7);
signal result6_1 : std_logic;
signal result6_1n : std_logic;
signal result6_2 : std_logic;
signal result6_2n : std_logic;
signal result7_1 : std_logic;
signal result7_1n : std_logic;
begin
Assign_InA : process (InA) is
begin
inA8 <= (others => '0');
inA8(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT1 : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => result6_1,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
XOR6_LUT2_N : LUT6
generic map(
INIT => X"9669699669969669")
port map(
O => result6_1n,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
MUXF7_LUT1 : MUXF7
port map (
O => result7_1,
I0 => result6_1,
I1 => result6_1n,
S => inA8(6));
XOR6_LUT3 : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => result6_2,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
XOR6_LUT4_N : LUT6
generic map(
INIT => X"9669699669969669")
port map(
O => result6_2n,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
MUXF7_LUT2 : MUXF7
port map (
O => result7_1n,
I0 => result6_2n,
I1 => result6_2,
S => inA8(6));
MUXF8_LUT : MUXF8
port map (
O => res,
I0 => result7_1,
I1 => result7_1n,
S => inA8(7));
end generate Use_MUXF8;
end generate Using_LUT6;
-- Fall-back implementation without LUT6
Not_Using_LUT6 : if not C_USE_LUT6 or C_SIZE > 8 generate
begin
Res <= ParityGen(InA);
end generate Not_Using_LUT6;
end architecture IMP;
| apache-2.0 | f60f8fbaad1b8d20dc87f99a61a5be1b | 0.470417 | 4.20868 | false | false | false | false |
rhexsel/xinu-cMIPS | vhdl/io.vhd | 1 | 41,531 | -- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- peripheral: from_stdin
-- read a signle character from stdout
-- returns LF ('\n'=0x0a) if there are no charachters on input
-- on the first ever read, returna LF on the empty line read
--+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.p_wires.all;
entity from_stdin is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
data : out reg32);
end from_stdin;
architecture simulation of from_stdin is
begin
U_READ_IN: process(clk,sel)
variable L : line;
variable this : character;
variable good : boolean := FALSE;
begin
if falling_edge(clk) and sel = '0' then
read(L, this, good);
if not(good) then
readline(input, L);
this := LF;
end if;
data <= x"000000" & std_logic_vector(to_signed(character'pos(this),8));
assert TRUE report "STD_IOrd= " & this;
end if;
end process U_READ_IN;
end architecture simulation;
-- ++ from_stdin +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
architecture fake of from_stdin is
begin
data <= (others => 'X');
end architecture fake;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- peripheral: print_data
-- print an integer to stdout, 32bit hexadecimal
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.p_wires.all;
entity print_data is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
data : in reg32);
end print_data;
architecture simulation of print_data is
file output : text open write_mode is "STD_OUTPUT";
begin
U_WRITE_OUT: process(sel,clk)
variable msg : line;
begin
if falling_edge(clk) and sel = '0' then
write ( msg, string'(SLV32HEX(data)) );
writeline( output, msg );
end if;
end process U_WRITE_OUT;
end architecture simulation;
-- ++ print_data +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
architecture fake of print_data is
begin
end architecture fake;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- peripheral: to_stdout
-- print a signle character to stdout
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.p_wires.all;
entity to_stdout is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
data : in std_logic_vector);
end to_stdout;
architecture simulation of to_stdout is
file output : text open write_mode is "STD_OUTPUT";
begin
U_WRITE_OUT: process(clk,sel)
variable msg : line;
begin
if falling_edge(clk) and sel = '0' then
if (data(7 downto 0) = x"00") or (data(7 downto 0) = x"0a") then
writeline( output, msg );
else
write(msg, character'val(to_integer( unsigned(data(7 downto 0)))));
end if;
end if;
end process U_WRITE_OUT;
end architecture simulation;
-- ++ to_stdout +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
architecture fake of to_stdout is
begin
end architecture fake;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- peripheral: write_data_to_file
-- write one 32bit integer to file "output.data"
-- if( addr(3 downto 0) ) = "0000" then write to file
-- if( addr(3 downto 0) ) = "0100" then close file
-- if( addr(3 downto 0) ) = "0111" then assert dump_ram
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.p_wires.all;
entity write_data_file is
generic (OUTPUT_FILE_NAME : string := "output.data");
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
addr : in reg32;
data : in reg32;
byte_sel : in reg4;
dump_ram : out std_logic);
end write_data_file;
architecture simulation of write_data_file is
type uint_file_type is file of integer;
file output_file: uint_file_type open write_mode is OUTPUT_FILE_NAME;
begin
U_write_uint: process (clk,sel)
begin
dump_ram <= '0';
if falling_edge(clk) and sel = '0' then
if addr(3 downto 0) = b"0000" then -- data write
if wr = '0' then
write( output_file, to_integer(signed(data)) );
assert TRUE report "IOwr[" & SLV32HEX(addr) &"]:" & SLV32HEX(data);
end if;
elsif addr(3 downto 0) = b"0100" then -- close output file
file_close(output_file);
elsif addr(3 downto 0) = b"0111" then -- dump RAM
dump_ram <= '1';
end if;
end if;
end process U_write_uint;
end architecture simulation; -- write_file_data
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
architecture fake of write_data_file is
begin
dump_ram <= 'X';
end architecture fake;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- peripheral: read_data_file
-- read one 32bit integer from file "input.data"
-- if not EOF then write data to file
-- else status <= 1
-- on a read, return last status (EOF=1 or otherwise=0)
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.p_wires.all;
entity read_data_file is
generic (INPUT_FILE_NAME : string := "input.data");
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
addr : in reg32;
data : out reg32;
byte_sel : in reg4);
end read_data_file;
architecture simulation of read_data_file is
type uint_file_type is file of integer;
file input_file: uint_file_type open read_mode is INPUT_FILE_NAME;
signal status : reg32 := (others => '0');
begin
U_read_uint: process(clk,sel)
variable datum : integer := 0;
variable value : reg32; -- for debugging only
begin
data <= (others => 'X');
if falling_edge(clk) and sel = '0' then
if addr(3 downto 0) = b"0000" then -- data read
if wr = '1' then
if not endfile(input_file) then
read( input_file, datum );
data <= std_logic_vector(to_signed(datum, 32));
status <= x"00000000"; -- NOT_EndOfFile
value := std_logic_vector(to_signed(datum, 32)); -- DEBUG
assert TRUE report "IOrd[" & SLV32HEX(addr) &"]:"& SLV32HEX(value);
else
status <= x"00000001"; -- EndOfFile
end if;
else
data <= (others => 'X');
end if;
else -- status read
if wr = '1' then
data <= status;
else
data <= (others => 'X');
end if;
end if;
end if;
end process U_read_uint;
end architecture simulation;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
architecture fake of read_data_file is
begin
data <= (others => 'X');
end architecture fake;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- peripheral: generate interrupt after N clock cycles
-- Generates an interrupt after N cycles, N <= 2**30
-- Counting stops on reaching limit stored to counter.
-- data(31) = 1 enables interrupt on reaching limit;
-- data(31) = 0 disables interrupts
-- data(30) = 1 enables counting
-- data(30) = 0 stops counter and delays interrupt (forever?)
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
entity do_interrupt is
port (rst : in std_logic;
clk : in std_logic; -- clock pulses counted
sel : in std_logic;
wr : in std_logic;
data_inp : in std_logic_vector;
data_out : out std_logic_vector;
irq : out std_logic);
constant NUM_BITS : integer := 30;
subtype c_width is std_logic_vector(NUM_BITS - 1 downto 0);
constant START_COUNT : c_width := (others => '0');
end do_interrupt;
architecture behavioral of do_interrupt is
component registerN is
generic (NUM_BITS: integer; INIT_VAL: std_logic_vector);
port(clk, rst, ld: in std_logic;
D: in std_logic_vector;
Q: out std_logic_vector);
end component registerN;
component countNup is
generic (NUM_BITS: integer);
port(clk, rst, ld, en: in std_logic;
D: in std_logic_vector;
Q: out std_logic_vector;
co: out std_logic);
end component countNup;
component FFDsimple is
port(clk, rst : in std_logic;
D : in std_logic;
Q : out std_logic);
end component FFDsimple;
signal Dlimit, Qlimit, Q: c_width;
signal ld_cnt, ld_reg, en, cnt_en, int_en, equals : std_logic;
signal i_ena, c_ena : std_logic;
begin
ld_reg <= wr when sel = '0' else '1';
ld_cnt <= not ld_reg;
Dlimit <= data_inp(NUM_BITS-1 downto 0);
U_LIMIT: registerN generic map (NUM_BITS, START_COUNT)
port map (clk, rst, ld_reg, Dlimit, Qlimit);
en <= cnt_en and (not equals);
U_COUNTER: countNup generic map (NUM_BITS)
port map (clk, rst, ld_cnt, en, START_COUNT, Q, open);
c_ena <= data_inp(30) when (sel='0' and wr='0') else cnt_en;
U_COUNT_EN: FFDsimple port map (clk, rst, c_ena, cnt_en);
i_ena <= data_inp(31) when (sel='0' and wr='0') else int_en;
U_INTERR_EN: FFDsimple port map (clk, rst, i_ena, int_en);
equals <= '1' when (Q = Qlimit(NUM_BITS-1 downto 0) ) else '0';
irq <= '1' when (equals = '1' and int_en = '1') else '0';
data_out <= int_en & cnt_en & Q;
end behavioral;
-- ++ do_interrupt +++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- peripheral: simple UART bus interface (a wrapper to the real UART)
-- 8 data bits, no parity, 1 stop bit (8N1), catches: framing, overrun
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use work.p_wires.all;
entity simple_uart is
port (rst : in std_logic;
clk : in std_logic; -- processor clock
sel : in std_logic;
wr : in std_logic;
addr : in std_logic_vector(1 downto 0);
data_inp : in std_logic_vector;
data_out : out std_logic_vector;
txdat : out std_logic; -- serial transmission (output)
rxdat : in std_logic; -- serial reception (input)
rts : out std_logic;
cts : in std_logic;
irq : out std_logic; -- interrupt request
bit_rt : out std_logic_vector); -- communication speed; for TB only
end simple_uart;
architecture behavioral of simple_uart is
component uart_int is
port(clk, rst: in std_logic;
s_ctrlwr, s_stat : in std_logic; -- select registers
s_tx, s_rx : in std_logic; -- select registers
s_intwr, s_intrd : in std_logic; -- select interrupt register
d_inp: in std_logic_vector; -- 32 bit input
d_out: out std_logic_vector; -- 32 bit output
txdat: out std_logic; -- serial transmission (output)
rxdat: in std_logic; -- serial reception (input)
rts: out std_logic;
cts: in std_logic;
irq_all: out std_logic; -- interrupt request
bit_rt: out std_logic_vector); -- communication speed - for TB only
end component uart_int;
signal s_ctrlwr, s_stat, s_tx, s_rx, s_intwr, s_intrd : std_logic;
signal d_inp, d_out : reg32;
begin
U_UART: uart_int port map (clk, rst, s_ctrlwr, s_stat, s_tx, s_rx,
s_intwr, s_intrd,
d_inp,d_out, txdat,rxdat, rts,cts, irq, bit_rt);
-- a3a2 wr register (aligned to word addresses)
-- 00 0 control, W+r IO_UART_ADDR +0
-- 01 x status, R IO_UART_ADDR +4
-- 10 0 interrupt conmtrol W IO_UART_ADDR +8
-- 10 1 interrupt conmtrol R IO_UART_ADDR +8
-- 11 0 transmission W IO_UART_ADDR +12
-- 11 1 reception R IO_UART_ADDR +12
s_ctrlwr <= '1' when sel = '0' and addr = b"00" and wr = '0' else '0'; -- W
s_stat <= '1' when sel = '0' and addr = b"01" else '0'; -- R+W
s_intwr <= '1' when sel = '0' and addr = b"10" and wr = '0' else '0'; -- W
s_intrd <= '1' when sel = '0' and addr = b"10" and wr = '1' else '0'; -- R
s_tx <= '1' when sel = '0' and addr = b"11" and wr = '0' else '0'; -- W-O
s_rx <= '1' when sel = '0' and addr = b"11" and wr = '1' else '0'; -- R-O
data_out <= d_out;
d_inp <= data_inp;
end behavioral;
-- ++ simple uart +++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- peripheral: system statistics: gather statistics in one place
-- processor reads performance counters, on word boundaries, adressed as
-- cnt_dc_ref when "00000", 0
-- cnt_dc_rd_hit when "00100", 4
-- cnt_dc_wr_hit when "01000", 8
-- cnt_dc_flush when "01100", 12
-- cnt_ic_ref when "10000", 16
-- cnt_ic_hit when "10100", 20
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
entity sys_stats is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
addr : in reg32;
data : out reg32;
cnt_dc_ref : in integer;
cnt_dc_rd_hit : in integer;
cnt_dc_wr_hit : in integer;
cnt_dc_flush : in integer;
cnt_ic_ref : in integer;
cnt_ic_hit : in integer);
end sys_stats;
architecture simulation of sys_stats is
begin
U_SYNC_OUTPUT: process(clk,sel)
variable i_c : integer := 0;
begin
data <= (others => '0');
if falling_edge(clk) and sel = '0' then
case addr(4 downto 2) is
when "000" => i_c := cnt_dc_ref;
when "001" => i_c := cnt_dc_rd_hit;
when "010" => i_c := cnt_dc_wr_hit;
when "011" => i_c := cnt_dc_flush;
when "100" => i_c := cnt_ic_ref;
when "101" => i_c := cnt_ic_hit;
when others => i_c := 0;
end case;
end if;
data <= std_logic_vector(to_signed(i_c,32));
end process U_SYNC_OUTPUT;
end architecture simulation;
-- ++ system statistics ++++++++++++++++++++++++++++++++++++++++++++++++++
architecture fake of sys_stats is
begin
data <= (others => 'X');
end architecture fake;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- peripheral: to_7seg
-- input format:
-- b14 b13 b12 b09 b08 b07..b04 b03..b02
-- red gre blu MSdot msdot MSdigit msdigit
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.p_wires.all;
entity to_7seg is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
data : in std_logic_vector;
display0 : out reg8;
display1 : out reg8;
red : out std_logic;
green : out std_logic;
blue : out std_logic);
-- 2 decimal points, 2 hex digits, 3 leds
constant NUM_BITS : integer := 15;
subtype c_width is std_logic_vector(NUM_BITS - 1 downto 0);
constant INIT_VALUE : c_width := (others => '0');
end to_7seg;
architecture behavioral of to_7seg is
component registerN is
generic (NUM_BITS: integer; INIT_VAL: std_logic_vector);
port(clk, rst, ld: in std_logic;
D: in std_logic_vector;
Q: out std_logic_vector);
end component registerN;
component display_7seg is
port(data_i : in std_logic_vector(3 downto 0);
decimal_i : in std_logic;
disp_7seg_o : out std_logic_vector(7 downto 0));
end component display_7seg;
signal value : std_logic_vector(NUM_BITS-1 downto 0);
signal middle : std_logic;
begin
U_HOLD_data: registerN generic map (NUM_BITS, INIT_VALUE)
port map (clk, rst, sel, data(NUM_BITS-1 downto 0), value);
red <= value(14);
green <= value(13);
blue <= value(12);
U_DSP1: display_7seg port map (value(7 downto 4), value(9), display1);
U_DSP0: display_7seg port map (value(3 downto 0), value(8), display0);
U_sim: process(sel,rst,clk)
begin
middle <= not(sel) and not(clk); -- to remove spurious reports
if rst = '1' then
assert not(rising_edge(middle))
report "dsp7seg: "& SLV32HEX(data) severity NOTE;
end if;
end process;
end behavioral;
-- ++ to_7seg +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- peripheral: read_keys
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
entity read_keys is
generic (DEB_CYCLES: natural); -- debouncing interval
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
data : out reg32;
kbd : in std_logic_vector (11 downto 0);
sw : in std_logic_vector (3 downto 0));
constant DEB_BITS : integer := 16; -- debounce counter width
constant CNT_MAX : integer := (2**DEB_BITS - 1);
constant x_DEB_CYCLES : std_logic_vector(DEB_BITS-1 downto 0)
:= std_logic_vector(to_signed((CNT_MAX - DEB_CYCLES),DEB_BITS));
constant NUM_BITS : integer := 4; -- four bits to hold key number
subtype c_width is std_logic_vector(NUM_BITS - 1 downto 0);
constant NO_KEY : c_width := (others => '0');
end read_keys;
architecture behavioral of read_keys is
component FFD is
port(clk, rst, set : in std_logic;
D : in std_logic; Q : out std_logic);
end component FFD;
component registerN is
generic (NUM_BITS: integer; INIT_VAL: std_logic_vector);
port(clk, rst, ld: in std_logic;
D: in std_logic_vector(NUM_BITS-1 downto 0);
Q: out std_logic_vector(NUM_BITS-1 downto 0));
end component registerN;
component countNup is
generic (NUM_BITS: integer := 16);
port(clk, rst, ld, en: in std_logic;
D: in std_logic_vector((NUM_BITS - 1) downto 0);
Q: out std_logic_vector((NUM_BITS - 1) downto 0);
co: out std_logic);
end component countNup;
type kbd_state is (st_idle, st_start, st_wait, st_load, st_release);
signal kbd_current_st, kbd_next_st : kbd_state;
attribute SYN_ENCODING of kbd_state : type is "safe";
-- signal kbd_dbg_st : integer; -- debugging only
signal cnt_ld, cnt_en, new_ld : std_logic;
signal press, debounced, rdy_clr, ready : std_logic;
signal keys_data, cpu_data : reg4;
signal d : reg2;
-- signal count : std_logic_vector(DEB_BITS-1 downto 0); -- debugging only
begin
data(31) <= ready;
data(30 downto 8) <= (others => '0');
data(7) <= sw(3);
data(6) <= sw(2);
data(5) <= sw(1);
data(4) <= sw(0);
data(3 downto 0) <= cpu_data(3 downto 0);
U_DEBOUNCER: countNup generic map (DEB_BITS)
port map (clk=>clk, rst=>rst, ld=>cnt_ld, en=>cnt_en,
D=>x_DEB_CYCLES, Q=>open, co=>debounced);
U_NEW_DATA: registerN generic map (4, NO_KEY)
port map (clk, rst, new_ld, keys_data, cpu_data);
d <= new_ld & sel; -- new_ld, sel active in '0'
with d select
rdy_clr <= '1' when "00",
'1' when "01",
'0' when "10",
ready when others;
U_READY: FFD port map (clk, rst, '1', rdy_clr, ready);
press <= BOOL2SL(keys_data /= b"0000");
-- translate key position to key code
-- code for key 0 cannot be zero; value-holding register is reset to "0000"
with kbd select
keys_data <= "0001" when "000000000001", -- 1
"0010" when "000000000010", -- 2
"0011" when "000000000100", -- 3
"0100" when "000000001000", -- 4
"0101" when "000000010000", -- 5
"0110" when "000000100000", -- 6
"0111" when "000001000000", -- 7
"1000" when "000010000000", -- 8
"1001" when "000100000000", -- 9
"1010" when "001000000000", -- *
"1111" when "010000000000", -- 0, cannot be "0000"
"1011" when "100000000000", -- #
"0000" when others; -- no key depressed
-- ---------------------------------------------------------------------
U_KBD_st_reg: process(rst,clk)
begin
if rst = '0' then
kbd_current_st <= st_idle;
elsif rising_edge(clk) then
kbd_current_st <= kbd_next_st;
end if;
end process U_KBD_st_reg; ----------------------------------------------
-- kbd_dbg_st <= integer(kbd_state'pos(kbd_current_st)); -- for debugging
U_KBD_st_transitions: process(kbd_current_st, press, debounced) --------
begin
case kbd_current_st is
when st_idle => -- 0
if press = '1' then
kbd_next_st <= st_start;
else
kbd_next_st <= st_idle;
end if;
when st_start => -- 1
kbd_next_st <= st_wait;
when st_wait => -- 2
if debounced = '1' then
kbd_next_st <= st_load;
else
kbd_next_st <= st_wait;
end if;
when st_load => -- 3
kbd_next_st <= st_release;
when st_release => -- 4
if press = '1' then
kbd_next_st <= st_release;
else
kbd_next_st <= st_idle;
end if;
end case;
end process U_KBD_st_transitions; ------------------------------------
U_KBD_outputs: process(kbd_current_st) ------------------------------
begin
case kbd_current_st is
when st_idle |st_release => -- 0,4
new_ld <= '1';
cnt_ld <= '0';
cnt_en <= '0';
when st_start => -- 1
new_ld <= '1';
cnt_ld <= '1';
cnt_en <= '0';
when st_wait => -- 2
new_ld <= '1';
cnt_ld <= '0';
cnt_en <= '1';
when st_load => -- 3
new_ld <= '0';
cnt_ld <= '1';
cnt_en <= '0';
end case;
end process U_KBD_outputs; -------------------------------------------
end behavioral;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- peripheral: LCD display controller
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use work.p_wires.all;
entity LCD_display is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
rdy : out std_logic;
wr : in std_logic;
addr : in std_logic; -- 0=constrol, 1=data
data_inp : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0);
LCD_DATA : inout std_logic_vector(7 downto 0); -- bidirectional bus
LCD_RS : out std_logic; -- LCD register select 0=ctrl, 1=data
LCD_RW : out std_logic; -- LCD read=1, 0=write
LCD_EN : out std_logic; -- LCD enable=1
LCD_BLON : out std_logic); -- LCD backlight on=1
constant NUM_BITS : integer := 8;
subtype c_width is std_logic_vector(NUM_BITS - 1 downto 0);
constant INIT_VALUE : c_width := (others => '0');
end LCD_display;
architecture rtl of LCD_display is
component wait_states is
generic (NUM_WAIT_STATES :integer);
port(rst : in std_logic;
clk : in std_logic;
sel : in std_logic; -- active in '0'
waiting : out std_logic); -- active in '1'
end component wait_states;
component registerN is
generic (NUM_BITS: integer; INIT_VAL: std_logic_vector);
port(clk, rst, ld: in std_logic;
D: in std_logic_vector;
Q: out std_logic_vector);
end component registerN;
component FFD is
port(clk, rst, set, D : in std_logic; Q : out std_logic);
end component FFD;
component FFDsimple is
port(clk, rst, D : in std_logic; Q : out std_logic);
end component FFDsimple;
type lcd_state is (st_init, st_idle, st_n, st_n1, st_n2, st_n3,
st_n4, st_n5, st_n6, st_n7, st_n8, st_n9, st_na, st_nb);
attribute SYN_ENCODING of lcd_state : type is "safe";
signal lcd_current_st, lcd_next_st : lcd_state;
signal lcd_current : integer; -- debugging only
signal waiting, wait1, wait2, n_sel: std_logic;
signal sel_rs, RS, sel_rw, RW,lcd_enable,lcd_read : std_logic;
signal inp_data, out_data : reg8;
begin
n_sel <= not(sel);
U_WAIT_ON_READS: component wait_states generic map (1)
port map (rst, clk, sel, wait1);
U_WAIT2: FFDsimple port map (clk, rst, wait1, wait2);
rdy <= not(wait1 or wait2 or waiting); -- wait for 260ns
sel_rs <= addr when sel = '0' else RS;
U_INPUT_RS: FFDsimple port map (clk, rst, sel_rs, RS);
U_INPUT: registerN generic map (NUM_BITS, INIT_VALUE)
port map (clk, rst, sel, data_inp(NUM_BITS-1 downto 0), inp_data);
U_OUTPUT: registerN generic map (NUM_BITS, INIT_VALUE)
port map (clk, rst, lcd_read, out_data, data_out(NUM_BITS-1 downto 0));
data_out(31 downto NUM_BITS) <= (others => 'X');
-- TESTING ONLY
-- out_data <= b"00000000" when RW = '1' else (others => 'X');
out_data <= LCD_DATA when RW = '1' else (others => 'Z');
LCD_DATA <= inp_data when RW = '0' else (others => 'Z');
LCD_RS <= RS; -- LCD register select 0=ctrl, 1=data
sel_rw <= wr when sel = '0' else RW;
U_INPUT_RW: FFD port map (clk, '1', rst, sel_rw, RW);
LCD_RW <= RW; -- LCD read=1, 0=write
LCD_EN <= lcd_enable; -- LCD enable=1
LCD_BLON <= '1'; -- LCD backlight
-- state register----------------------------------------------------
U_st_reg: process(rst,clk)
begin
if rst = '0' then
lcd_current_st <= st_init;
elsif rising_edge(clk) then
lcd_current_st <= lcd_next_st;
end if;
end process U_st_reg;
lcd_current <= lcd_state'pos(lcd_current_st); -- debugging only
U_st_transitions: process(lcd_current_st, RW, sel)
begin
case lcd_current_st is
when st_init => -- 0
lcd_next_st <= st_idle;
when st_idle => -- 1
if sel = '0' then
lcd_next_st <= st_n;
else
lcd_next_st <= st_idle;
end if;
when st_n => -- 2
lcd_next_st <= st_n1;
when st_n1 => -- 3, setup for Enable is 20ns
lcd_next_st <= st_n2;
when st_n2 => -- 4, keep Enable=1 for 200ns
lcd_next_st <= st_n3;
when st_n3 => -- 5, data setup is 100ns
lcd_next_st <= st_n4;
when st_n4 => -- 6
lcd_next_st <= st_n5;
when st_n5 => -- 7
lcd_next_st <= st_n6;
when st_n6 => -- 8
lcd_next_st <= st_n7;
when st_n7 => -- 9
lcd_next_st <= st_n8;
when st_n8 => -- 10, can read now
lcd_next_st <= st_n9;
when st_n9 => -- 11, data hold for Enable is >40ns
lcd_next_st <= st_na;
when st_na => -- 12
lcd_next_st <= st_nb;
when st_nb => -- 13
lcd_next_st <= st_idle;
when others => -- ??
lcd_next_st <= st_idle; -- Enable cycle >500ns
end case;
end process U_st_transitions;
U_st_outputs: process(lcd_current_st)
begin
case lcd_current_st is
when st_init =>
lcd_enable <= '0'; -- disable
lcd_read <= '1';
waiting <= '0';
when st_idle =>
lcd_enable <= '0'; -- disable
lcd_read <= '1';
waiting <= '0';
when st_n | st_n1 =>
lcd_enable <= '0'; -- disable, waiting for setup
lcd_read <= '1';
waiting <= '1';
when st_n2 | st_n3 | st_n4 | st_n5 | st_n6 | st_n7 =>
lcd_enable <= '1'; -- enable, waiting
lcd_read <= '1';
waiting <= '1';
when st_n8 =>
lcd_enable <= '1'; -- enable, still waiting
lcd_read <= '0';
waiting <= '1';
when st_n9 =>
lcd_enable <= '1'; -- enable, still waiting
lcd_read <= '1';
waiting <= '1';
when st_na =>
lcd_enable <= '0'; -- disable, still waiting
lcd_read <= '1';
waiting <= '1';
when st_nb =>
lcd_enable <= '0'; -- disable, stop waiting
lcd_read <= '1'; -- held inp data for 40ns
waiting <= '0';
when others =>
lcd_enable <= '0'; -- disable
lcd_read <= '1';
waiting <= '0';
end case;
end process U_st_outputs;
end architecture rtl;
-- -----------------------------------------------------------------------
-- -----------------------------------------------------------------------
architecture fake of LCD_display is
begin
rdy <= HI;
data_out <= (others => 'X');
LCD_RS <= LO; -- LCD register select 0=ctrl, 1=data
LCD_RW <= HI; -- LCD read=1, 0=write
LCD_EN <= LO; -- LCD enable=1
LCD_BLON <= LO; -- LCD backlight on=1
end architecture fake;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- peripheral: SDcard bus interface (a wrapper to the SDcard controller)
-- base + b"0000" -> address register
-- base + b"0100" -> data registers (RD/WR)
-- base + b"1000" -> control register
-- base + b"1100" -> status register
--
-- Software must ALWAYS check status(31) = busy before reading/writing
-- to controller. If controller is not busy, check for errors.
-- In case of errors, reset controller by writing 0x10 to control register.
-- Wait states (rdy=0) are inserted as needed by the bus interface.
--
-- Control register: bit(4)=1 reset the controller (because of error)
-- bit(1)=1 perform a sector READ
-- bit(0)=1 perform a sector WRITE
-- bit(0) and bit(1) shall not be both set
--
-- Status register: bit(31)=1 controller is busy (busy_o=1)
-- bit(30)=1 simultaneous read and write commands
-- bit(15..0) controller error bits (see SDcard.vhd)
--
-- Address register: 32 bits, can be written to, and read from
--
-- Data register: data write (sw by CPU), data read (lw by CPU)
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use work.SdCardPckg.all;
use work.p_wires.all;
entity SDcard is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
rdy : out std_logic;
wr : in std_logic;
addr : in reg2; -- a03, a02
data_inp : in reg32;
data_out : out reg32;
sdc_cs : out std_logic; -- SDcard chip-select
sdc_clk : out std_logic; -- SDcard serial clock
sdc_mosi_o : out std_logic; -- SDcard serial data out (to card)
sdc_miso_i : in std_logic; -- SDcard serial data inp (fro card)
irq : out std_logic); -- interrupt request (not yet used)
end SDCard;
architecture rtl of SDcard is
component wait_states is
generic (NUM_WAIT_STATES :integer);
port(rst : in std_logic;
clk : in std_logic;
sel : in std_logic; -- active in '0'
waiting : out std_logic); -- active in '1'
end component wait_states;
component registerN is
generic (NUM_BITS: integer; INIT_VAL: std_logic_vector);
port(clk, rst, ld: in std_logic;
D: in std_logic_vector;
Q: out std_logic_vector);
end component registerN;
component FFDsimple is
port(clk, rst, D : in std_logic; Q : out std_logic);
end component FFDsimple;
component SdCardCtrl is
generic (
FREQ_G : real; -- Master clock frequency (MHz).
INIT_SPI_FREQ_G : real; -- Slow SPI clock freq during init (MHz).
SPI_FREQ_G : real; -- Operational SPI freq. to the SD card (MHz).
BLOCK_SIZE_G : natural; -- Num bytes in an SD card block or sector.
CARD_TYPE_G : CardType_t); -- Type of SD card connected.
port (
-- Host-side interface signals.
clk_i : in std_logic; -- Master clock.
reset_i : in std_logic; -- active-high, synchronous reset.
rd_i : in std_logic; -- active-high read block request.
wr_i : in std_logic; -- active-high write block request.
continue_i : in std_logic; -- If true, inc address and continue R/W.
addr_i : in std_logic_vector; -- Block address.
data_i : in std_logic_vector; -- Data to write to block.
data_o : out std_logic_vector; -- Data read from block.
busy_o : out std_logic; -- High when controller is busy.
hndShk_i : in std_logic; -- High when host has new or has taken data.
hndShk_o : out std_logic; -- High when cntlr has taken or new data.
error_o : out std_logic_vector;
-- I/O signals to the external SD card.
cs_bo : out std_logic; -- Active-low chip-select.
sclk_o : out std_logic; -- Serial clock to SD card.
mosi_o : out std_logic; -- Serial data output to SD card.
miso_i : in std_logic; -- Serial data input from SD card.
state : out std_logic_vector); -- state, debugging only
end component SdCardCtrl;
-- use fake / rtl
for U_SDcard : SdCardCtrl use entity work.SdCardCtrl(fake);
signal s_addr, s_stat, s_ctrl, s_read, s_write : std_logic;
signal continue, busy, hndShk_i, hndShk_o, wr_i, rd_i : std_logic;
signal wait1, waiting, new_trans, new_data_rd, sdc_rst : std_logic;
signal ctrl_err, set_wr_i, set_rd_i : std_logic;
signal do_reset, do_reset1 : std_logic;
signal data_rd, data_rd_reg, data_wr_reg : reg8;
signal error_o : reg16;
signal addr_reg : reg32;
signal sel_data_out : reg3;
signal state : reg5;
signal w : reg5;
begin
U_SDcard: SdCardCtrl
-- generic map (50.0, 0.400, 12.5, 512, SD_CARD_E)
generic map (50.0, 25.0, 25.0, 512, SD_CARD_E)
port map (clk, sdc_rst, rd_i, wr_i, '0', addr_reg,
data_wr_reg, data_rd, busy, hndshk_i, open, error_o,
-- data_wr_reg, data_rd, busy, hndshk_i, hndshk_o, error_o,
sdc_cs, sdc_clk, sdc_mosi_o, sdc_miso_i, state);
hndshk_i <= waiting;
U_WAIT1: component wait_states generic map (1)
port map (rst, clk, new_trans, wait1);
U_WAIT: process(rst, clk, wait1, hndshk_o)
variable w : std_logic;
begin
if rst = '0' then
w := '0';
elsif rising_edge(clk) then
if wait1 = '1' then -- new transaction started
w := '1';
end if;
if hndshk_o = '1' then -- transaction ended
w := '0';
end if;
end if;
waiting <= w;
end process U_WAIT;
rdy <= not(wait1 or waiting); -- wait for controller
new_data_rd <= not(hndshk_o);
U_W1: FFDsimple port map (clk, rst, wait1, w(0));
U_W2: FFDsimple port map (clk, rst, w(0), w(1));
U_W3: FFDsimple port map (clk, rst, w(1), w(2));
U_W4: FFDsimple port map (clk, rst, w(2), w(3));
U_W5: FFDsimple port map (clk, rst, w(3), w(4));
U_W6: FFDsimple port map (clk, rst, w(4), hndshk_o);
-- a3a2 wr register (aligned to word addresses: a1a0=00)
-- 00 0 write to ADDR register (32 bits)
-- 00 1 returns current value of ADDR
-- 01 1 read from data register (8 bits, least significant byte)
-- 01 0 write to data register (8 bits, least significant byte)
-- 10 0 write to control register
-- 10 1 read from control register
-- 11 0 no effect (not possible to write to status register)
-- 11 1 read status register
new_trans <= '0' when addr = b"01" and sel = '0' else '1';
s_addr <= '0' when sel = '0' and addr = b"00" and wr = '0' else '1';
s_write <= '0' when sel = '0' and addr = b"01" and wr = '0' else '1';
s_read <= '0' when sel = '0' and addr = b"01" and wr = '1' else '1';
s_ctrl <= '1' when sel = '0' and addr = b"10" and wr = '0' else '0';
s_stat <= '1' when sel = '0' and addr = b"11" and wr = '1' else '0';
do_reset <= '1' when s_ctrl = '1' and data_inp(4) = '1' else '0';
U_RESET1: FFDsimple port map (clk, rst, do_reset, do_reset1);
sdc_rst <= not(rst) or do_reset or do_reset1; -- held HI for 2 cycles
-- hold wr_i active until first access to WR-register
set_wr_i <= ((s_ctrl and data_inp(0)) or (wr_i and s_write)) and s_write;
U_WR_STROBE: FFDsimple port map (clk, rst, set_wr_i, wr_i);
-- hold rd_i active until first access to RD-register
set_rd_i <= ((s_ctrl and data_inp(1)) or (rd_i and s_read)) and s_read;
U_RD_STROBE: FFDsimple port map (clk, rst, set_rd_i, rd_i);
ctrl_err <= wr_i and rd_i; -- cannot both read AND write
U_ADDR_REG: registerN generic map (32, x"00000000")
port map (clk, rst, s_addr, data_inp, addr_reg);
U_WRITE_REG: registerN generic map (8, x"00")
port map (clk, rst, s_write, data_inp(7 downto 0), data_wr_reg);
U_READ_REG: registerN generic map (8, x"00")
port map (clk, rst, new_data_rd, data_rd, data_rd_reg);
sel_data_out <= sel & addr;
with sel_data_out select
data_out <= addr_reg when "000",
x"000000" & data_rd_reg when "001",
x"000000" & b"000" & ctrl_err & b"00" & rd_i & wr_i when "010",
busy & ctrl_err & b"00" & b"000" & state & x"0" & error_o when "011",
(others => 'X') when others;
end architecture rtl;
-- ++ SDcard ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ++ SDcard ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
architecture fake of SDcard is
begin
rdy <= HI;
data_out <= (others => 'X');
sdc_cs <= HI;
sdc_clk <= LO; -- SDcard serial clock
sdc_mosi_o <= LO; -- SDcard serial data out (to card)
irq <= LO; -- interrupt request (not yet used)
end architecture fake;
-- ++ SDcard ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| gpl-3.0 | 6c401fe98ddaed15ea23333bc26e8d2c | 0.508849 | 3.543601 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-30bits_outputs31bits/3-ARF/asap-alap-random/arf_asap.vhd | 1 | 2,699 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.14:37:21)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY arf_asap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8: IN unsigned(0 TO 30);
output1, output2: OUT unsigned(0 TO 31));
END arf_asap_entity;
ARCHITECTURE arf_asap_description OF arf_asap_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register4: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register5: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register6: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register7: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register8: unsigned(0 TO 31) := "0000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
register2 := input2 * 2;
register3 := input3 * 3;
register4 := input4 * 4;
register5 := input5 * 5;
register6 := input6 * 6;
register7 := input7 * 7;
register8 := input8 * 8;
WHEN "00000010" =>
register1 := register4 + register1;
register2 := register2 + register8;
register3 := register6 + register3;
register4 := register7 + register5;
WHEN "00000011" =>
register1 := register1 + 10;
register3 := register3 + 12;
WHEN "00000100" =>
register5 := register1 * 14;
register1 := register1 * 16;
register6 := register3 * 18;
register3 := register3 * 20;
WHEN "00000101" =>
register5 := register6 + register5;
register1 := register3 + register1;
WHEN "00000110" =>
register3 := register5 * 22;
register5 := register5 * 24;
register6 := register1 * 26;
register1 := register1 * 28;
WHEN "00000111" =>
register3 := register3 + register6;
register1 := register5 + register1;
WHEN "00001000" =>
output1 <= register4 + register3;
output2 <= register2 + register1;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END arf_asap_description; | gpl-3.0 | 653b8a784b1f8ae05fc1ee4e67bf771e | 0.686921 | 3.377972 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-30bits_outputs31bits/5-EWF/asap-alap-random/ewf_alap.vhd | 1 | 3,329 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-16.08:47:35)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY ewf_alap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2: IN unsigned(0 TO 30);
output1, output2, output3, output4, output5: OUT unsigned(0 TO 31));
END ewf_alap_entity;
ARCHITECTURE ewf_alap_description OF ewf_alap_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register4: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register5: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register6: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register7: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register8: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register9: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register10: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register11: unsigned(0 TO 31) := "00000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
WHEN "00000010" =>
register2 := register1 + 3;
WHEN "00000011" =>
register3 := register2 + 5;
register4 := input2 + 6;
WHEN "00000100" =>
register3 := register4 + register3;
WHEN "00000101" =>
register5 := register3 * 8;
register6 := register3 * 10;
WHEN "00000110" =>
register5 := register4 + register5;
register6 := register2 + register6;
WHEN "00000111" =>
register4 := register4 + register5;
register2 := register2 + register6;
WHEN "00001000" =>
register4 := register4 * 12;
register2 := register2 * 14;
WHEN "00001001" =>
register4 := register4 + 16;
register2 := register1 + register2;
WHEN "00001010" =>
register7 := register5 + register4;
register8 := register6 + register2;
WHEN "00001011" =>
register7 := register7 + 18;
register1 := register1 + register2;
register8 := register8 + 20;
register9 := register4 + 22;
WHEN "00001100" =>
register10 := register7 * 24;
register1 := register1 * 26;
register11 := register8 * 28;
WHEN "00001101" =>
register9 := register9 * 30;
register3 := register3 + register6;
register6 := register10 + 32;
register1 := register1 + 34;
register10 := register11 + 36;
WHEN "00001110" =>
output1 <= register4 + register9;
output2 <= register5 + register3;
output3 <= register7 + register6;
output4 <= register2 + register1;
output5 <= register8 + register10;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END ewf_alap_description; | gpl-3.0 | 9208f90526718579d8df56b605285b38 | 0.691199 | 3.511603 | false | false | false | false |
marceloboeira/vhdl-examples | 005-button-ledbar/source.vhd | 1 | 1,166 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity btn_ledbar is
Port (
btn : in STD_LOGIC;
reset : in STD_LOGIC;
ledA : out STD_LOGIC_VECTOR (7 downto 0)
);
end btn_ledbar;
architecture Behavioral of btn_ledbar is
-- Signals
signal amount: integer range 0 to 80;
begin
p1: process (btn, reset)
-- variable ...
begin
if reset='1' then
amount <= 0;
elsif (btn'event and btn='1') then
amount <= amount + 1;
end if;
end process;
p2: process (amount)
begin
if amount >=10 then
ledA(0) <= '1';
if amount >=20 then
ledA(1) <= '1';
if amount >=30 then
ledA(2) <= '1';
if amount >=40 then
ledA(3) <= '1';
if amount >=50 then
ledA(4) <= '1';
if amount >=60 then
ledA(5) <= '1';
if amount >=70 then
ledA(6) <= '1';
if amount >=80 then
ledA(7) <= '1';
end if;
end if;
end if;
end if;
end if;
end if;
end if;
else
LEDS <= "00000000";
end if;
end process;
end Behavioral;
| mit | b013936315e61d5b632bf7aca54bce6d | 0.479417 | 3.449704 | false | false | false | false |
rhexsel/xinu-cMIPS | vhdl/instrcache.vhd | 2 | 17,020 | -- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- instruction cache, word-indexed, FPGA version, with early restart
-- TODO: associativity
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
entity I_CACHE_fpga is
port (rst : in std_logic;
clk4x : in std_logic;
ic_reset : out std_logic; -- active in '0'
cpu_sel : in std_logic; -- active in '0'
cpu_rdy : out std_logic; -- active in '0'
cpu_addr : in reg32;
cpu_data : out reg32;
mem_sel : out std_logic; -- active in '0'
mem_rdy : in std_logic; -- active in '0'
mem_addr : out reg32;
mem_data : in reg32;
ref_cnt : out integer;
hit_cnt : out integer);
constant IC_TAG_BITS : natural :=
IC_BTS_PER_WORD - (IC_INDEX_BITS + IC_WORD_SEL_BITS + IC_BYTE_SEL_BITS);
constant IC_TOP_TAG : natural := 31;
constant IC_BOT_TAG : natural := 32 - IC_TAG_BITS;
constant IC_TOP_INDEX : natural := 32 - (IC_TAG_BITS + 1);
constant IC_BOT_INDEX : natural := 32 - (IC_TAG_BITS + IC_INDEX_BITS);
constant IC_TOP_W_SEL : natural := 32 - (IC_TAG_BITS + IC_INDEX_BITS + 1);
constant IC_BOT_W_SEL : natural :=
32 - (IC_TAG_BITS + IC_INDEX_BITS + IC_WORD_SEL_BITS);
constant TAG_IDX_REG_INI: std_logic_vector(IC_TAG_BITS + IC_INDEX_BITS - 1 downto 0) :=
(others => '0');
subtype tag_address is integer range 0 to (IC_NUM_BLOCKS - 1);
subtype ram_address is integer range 0 to (IC_NUM_WORDS - 1);
subtype tag_sel_width is std_logic_vector((IC_TAG_BITS - 1) downto 0);
subtype index_width is std_logic_vector((IC_INDEX_BITS - 1) downto 0);
subtype word_sel_width is std_logic_vector((IC_WORD_SEL_BITS - 1) downto 0);
subtype tag_d_width is std_logic_vector(IC_TAG_BITS - 1 downto 0);
subtype v_tag_d_width is std_logic_vector(IC_TAG_BITS downto 0);
subtype tag_index_width is
std_logic_vector((IC_TAG_BITS+IC_INDEX_BITS - 1) downto 0);
end entity I_CACHE_fpga;
architecture structural of I_CACHE_fpga is
component sr_latch is
port(set,clr : in std_logic;
q : out std_logic);
end component sr_latch;
component sr_latch_rst is
port(rst,set,clr : in std_logic;
q : out std_logic);
end component sr_latch_rst;
component register32 is
generic (INITIAL_VALUE: std_logic_vector);
port(clk, rst, ld: in std_logic;
D: in std_logic_vector;
Q: out std_logic_vector);
end component register32;
component registerN is
generic (NUM_BITS: integer; INIT_VAL: std_logic_vector);
port(clk, rst, ld: in std_logic;
D: in std_logic_vector(NUM_BITS-1 downto 0);
Q: out std_logic_vector(NUM_BITS-1 downto 0));
end component registerN;
component countNup is
generic (NUM_BITS: integer);
port(clk, rst, ld, en: in std_logic;
D: in std_logic_vector(NUM_BITS-1 downto 0);
Q: out std_logic_vector(NUM_BITS-1 downto 0);
co: out std_logic);
end component countNup;
component ram_dual is
generic (N_WORDS : integer;
WIDTH : integer);
port (data : in std_logic_vector;
raddr : in natural range 0 to N_WORDS - 1;
waddr : in natural range 0 to N_WORDS - 1;
we : in std_logic;
rclk : in std_logic;
wclk : in std_logic;
q : out std_logic_vector);
end component ram_dual;
signal fetch, found, update_tags, hit, d_str_rd : std_logic;
signal t_str_rd, t_str_wr, t_we, d_str_wr, d_we : std_logic := '0';
signal full, filled, ld_addr, ld_cnt, en_cnt, check_addr : std_logic := '0';
signal fetching, s_fetching, r_fetching, en_wd_incr : std_logic;
signal reseting, s_reseting, r_reseting : std_logic;
signal init_done, init_incr, init_ld : std_logic;
signal tag_update, tag_invalidate, valid, miss_under_miss : std_logic := '0';
type cpu_ic_state is (st_idle, st_check, st_waiting, st_done, st_sync);
attribute SYN_ENCODING of cpu_ic_state : type is "safe";
signal cpu_ic_curr_st,cpu_ic_next_st : cpu_ic_state;
signal cpu_ic_curr : integer; -- DEBUGging only
type ic_ram_state is (st_idle, st_start1, st_wait1, st_found,
st_startn, st_waitn, st_done,
st_istart, st_iload, st_idelay1, st_idelay2,
st_inext, st_istop);
attribute SYN_ENCODING of ic_ram_state : type is "safe";
signal ic_ram_curr_st,ic_ram_next_st : ic_ram_state;
signal ic_ram_curr : integer; -- DEBUGging only
signal cached_data, hold_data : reg32;
signal t_rd_addr, t_wr_addr : tag_address;
signal d_rd_addr, d_wr_addr : ram_address;
signal cpu_tag, old_tag, tag : tag_d_width;
signal v_tag, old_v_tag, new_v_tag : v_tag_d_width;
signal cpu_index, old_index, init_index, wr_index : index_width;
signal cpu_word, old_word : word_sel_width;
signal cpu_tag_index, tag_index : tag_index_width;
constant word_sel_zero : word_sel_width := (others => '0');
constant index_sel_zero : index_width := (others => '0');
constant v_tag_zero : v_tag_d_width := (others => '0');
begin
cpu_tag <= cpu_addr(IC_TOP_TAG downto IC_BOT_TAG) when cpu_sel = '0'
else (others => 'X');
cpu_index <= cpu_addr(IC_TOP_INDEX downto IC_BOT_INDEX) when cpu_sel = '0'
else (others => 'X');
cpu_word <= cpu_addr(IC_TOP_W_SEL downto IC_BOT_W_SEL) when cpu_sel = '0'
else (others => 'X');
t_rd_addr <= to_integer(unsigned(cpu_index));
t_str_rd <= not(cpu_sel);
t_wr_addr <= to_integer(unsigned(wr_index));
-- t_we <= '1'; -- fetching,
t_we <= (tag_update or tag_invalidate) when reseting = '0' else
init_incr;
tag_update <= CONVERT_BOOLEAN( ic_ram_curr_st = st_done );
tag_invalidate <= CONVERT_BOOLEAN( ic_ram_curr_st = st_found ) ;
-- tag memory: valid (MS) & IC_TAG_BITS (ms)
U_TAGS: ram_dual generic map (IC_NUM_BLOCKS, IC_TAG_BITS+1)
port map (new_v_tag, t_rd_addr, t_wr_addr, t_we,
clk4x, clk4x, v_tag);
new_v_tag <= old_v_tag when (reseting = '0' and tag_update = '1') else
v_tag_zero;
valid <= v_tag(IC_TAG_BITS);
tag <= v_tag(IC_TAG_BITS-1 downto 0);
hit <= not(cpu_sel) and valid and CONVERT_BOOLEAN( tag = cpu_tag );
old_v_tag <= full & old_tag;
d_rd_addr <= to_integer(unsigned( cpu_index & cpu_word ) );
d_str_rd <= hit and not(cpu_sel);
wr_index <= old_index when reseting = '0' else init_index;
d_wr_addr <= to_integer(unsigned( wr_index & old_word ) );
-- instruction memory: physically organized as words, not blocks
U_RAM: ram_dual generic map (IC_NUM_WORDS, IC_BTS_PER_WORD)
port map (mem_data, d_rd_addr, d_wr_addr, fetching,
d_str_rd, mem_rdy, cached_data);
cpu_data <= hold_data when ( hit = '0' ) else cached_data;
U_HOLD_INSTR: registerN generic map ( 32, x"00000000" )
port map (mem_rdy, rst, '0', mem_data, hold_data);
en_wd_incr <= CONVERT_BOOLEAN( ic_ram_curr_st = st_startn );
-- block-fill circuitry for early restart: fill from address of miss
U_FILL_ADDR: countNup generic map (IC_WORD_SEL_BITS) -- clk,rst,ld,en
port map (clk4x, rst, s_fetching, en_wd_incr, cpu_word, old_word, open);
-- count number of words fetched from memory
U_FILL_COUNTER: countNup generic map (IC_WORD_SEL_BITS)
port map (clk4x, rst, s_fetching, en_wd_incr, word_sel_zero,
open, full);
old_tag <= tag_index((IC_TAG_BITS+IC_INDEX_BITS - 1) downto IC_INDEX_BITS);
old_index <= tag_index((IC_INDEX_BITS - 1) downto 0);
mem_addr <= old_tag & old_index & old_word & b"00";
cpu_tag_index <= cpu_tag & cpu_index;
ld_addr <= not(fetching);
U_TAG_INDEX_REGISTER: registerN -- clk,rst,ld=0
generic map ( IC_TAG_BITS + IC_INDEX_BITS, TAG_IDX_REG_INI)
port map (fetching, rst, '0', cpu_tag_index, tag_index);
miss_under_miss <= '1' when ( cpu_tag_index /= tag_index ) else '0';
update_tags <= '1' when ic_ram_curr_st = st_done else '0';
s_fetching <= CONVERT_BOOLEAN( ic_ram_curr_st = st_start1 );
r_fetching <= CONVERT_BOOLEAN( ic_ram_curr_st = st_done );
U_FETCHING: sr_latch_rst port map (rst, s_fetching, r_fetching, fetching);
-- scan I_cache during reset and clear valid bit in all blocks
U_RESET_COUNTER: countNup generic map (IC_INDEX_BITS) -- clk,rst,ld,en
port map (clk4x, rst, init_ld, init_incr,
index_sel_zero, init_index, init_done);
init_ld <= ( CONVERT_BOOLEAN( ic_ram_curr_st = st_iload ) );
init_incr <= ( CONVERT_BOOLEAN( ic_ram_curr_st = st_idelay2 ) );
s_reseting <= not( CONVERT_BOOLEAN( ic_ram_curr_st = st_istart ) );
r_reseting <= not( CONVERT_BOOLEAN( ic_ram_curr_st = st_istop ) );
U_RESSETING: sr_latch port map (s_reseting, r_reseting, reseting);
ic_reset <= not(reseting);
-- CPU-IC interface --------------------------------------------------
U_cpu_st_reg: process(rst,clk4x)
begin
if rst = '0' then
cpu_ic_curr_st <= st_idle;
elsif rising_edge(clk4x) then
cpu_ic_curr_st <= cpu_ic_next_st;
end if;
end process U_cpu_st_reg;
cpu_ic_curr <= cpu_ic_state'pos(cpu_ic_curr_st); -- debugging only
U_cpu_st_transitions: process(cpu_ic_curr_st, cpu_sel,hit,found,
miss_under_miss,fetching)
begin
case cpu_ic_curr_st is
when st_idle => -- 0
cpu_rdy <= '1';
fetch <= '0';
if cpu_sel = '0' then
cpu_ic_next_st <= st_check;
else
cpu_ic_next_st <= st_idle;
end if;
when st_check => -- 1
cpu_rdy <= '0';
fetch <= '0';
if hit = '1' then
cpu_ic_next_st <= st_done;
else
cpu_ic_next_st <= st_waiting;
end if;
when st_waiting => -- 2
cpu_rdy <= '0';
fetch <= '1';
if found = '0' then
cpu_ic_next_st <= st_waiting;
else
if miss_under_miss = '1' then
cpu_ic_next_st <= st_sync;
else
cpu_ic_next_st <= st_done;
end if;
end if;
when st_sync => -- 4
cpu_rdy <= '0';
fetch <= '1';
if fetching = '1' then
cpu_ic_next_st <= st_sync;
else
cpu_ic_next_st <= st_check;
end if;
when st_done => -- 3
cpu_rdy <= '1';
fetch <= '0';
if cpu_sel = '0' then -- MEM stalled, wait
cpu_ic_next_st <= st_done;
else
cpu_ic_next_st <= st_idle;
end if;
when others =>
cpu_rdy <= 'X';
fetch <= 'X';
assert false report "I_CACHE_CPU stateMachine broken" &
integer'image(cpu_ic_state'pos(cpu_ic_curr_st)) severity failure;
end case;
end process U_cpu_st_transitions; -- CPU-IC interface ---------------
-- IC-RAM interface -------------------------------------------------
U_ram_st_reg: process(rst,clk4x)
begin
if rst = '0' then
ic_ram_curr_st <= st_istart; -- initizlize cache tags
elsif falling_edge(clk4x) then
ic_ram_curr_st <= ic_ram_next_st;
end if;
end process U_ram_st_reg;
ic_ram_curr <= ic_ram_state'pos(ic_ram_curr_st); -- debugging only
U_ram_st_transitions: process(ic_ram_curr_st,check_addr,fetch,full,
mem_rdy,cpu_sel,init_done)
begin
case ic_ram_curr_st is
when st_idle => -- 0
mem_sel <= '1';
found <= '0';
if fetch = '1' then
ic_ram_next_st <= st_start1;
else
ic_ram_next_st <= st_idle;
end if;
when st_start1 => -- 1
mem_sel <= '0';
found <= '0';
ic_ram_next_st <= st_wait1;
when st_wait1 => -- 2
mem_sel <= '0';
found <= '0';
if mem_rdy = '0' then
ic_ram_next_st <= st_wait1;
else
ic_ram_next_st <= st_found;
end if;
when st_found => -- 3
found <= '1';
mem_sel <= '1';
if cpu_sel = '0' then
ic_ram_next_st <= st_found;
else
ic_ram_next_st <= st_startn;
end if;
when st_startn => -- 4 invalidate tag to avoid false-hit
mem_sel <= '1';
found <= '0';
if full = '1' then
ic_ram_next_st <= st_done;
else
ic_ram_next_st <= st_waitn;
end if;
when st_waitn => -- 5
mem_sel <= '0';
found <= '0';
if mem_rdy = '0' then
ic_ram_next_st <= st_waitn;
else
ic_ram_next_st <= st_startn;
end if;
when st_done => -- 6 mark tag as valid
mem_sel <= '1';
found <= '1';
ic_ram_next_st <= st_idle;
when st_istart => -- 7 initialize cache tags
mem_sel <= '1';
found <= '0';
ic_ram_next_st <= st_iload;
when st_iload => -- 8
mem_sel <= '1';
found <= '0';
ic_ram_next_st <= st_idelay1;
when st_idelay1 => -- 9 give some time to SRAM
mem_sel <= '1';
found <= '0';
ic_ram_next_st <= st_idelay2;
when st_idelay2 => -- 10
mem_sel <= '1';
found <= '0';
ic_ram_next_st <= st_inext;
when st_inext => -- 11
mem_sel <= '1';
found <= '0';
if init_done = '1' then
ic_ram_next_st <= st_istop;
else
ic_ram_next_st <= st_idelay1;
end if;
when st_istop => -- 12 initialization done
mem_sel <= '1';
found <= '0';
ic_ram_next_st <= st_idle; -- go to normal operation
when others =>
mem_sel <= 'X';
found <= 'X';
assert false report "I_CACHE_RAM stateMachine broken" &
integer'image(ic_ram_state'pos(ic_ram_curr_st)) severity failure;
end case;
end process U_ram_st_transitions; -- IC-RAM interface ---------------
ref_cnt <= 0;
hit_cnt <= 0;
end structural;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--c -- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--c -- Altera's design for a dual-port RAM that can be synthesized
--c -- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--c library ieee;
--c use ieee.std_logic_1164.all;
--c
--c entity ram_dual is
--c generic (N_WORDS : integer := 64;
--c WIDTH : integer := 8);
--c port (data : in std_logic_vector(WIDTH - 1 downto 0);
--c raddr : in natural range 0 to N_WORDS - 1;
--c waddr : in natural range 0 to N_WORDS - 1;
--c we : in std_logic;
--c rclk : in std_logic;
--c wclk : in std_logic;
--c q : out std_logic_vector(WIDTH - 1 downto 0));
--c end ram_dual;
--c
--c architecture rtl of ram_dual is
--c
--c -- Build a 2-D array type for the RAM
--c subtype word_t is std_logic_vector(WIDTH - 1 downto 0);
--c type memory_t is array(N_WORDS - 1 downto 0) of word_t;
--c
--c -- Declare the RAM signal.
--c signal ram : memory_t; -- := (others => (others => '0'));
--c
--c begin
--c
--c process(wclk)
--c begin
--c if(rising_edge(wclk)) then
--c if(we = '1') then
--c ram(waddr) <= data;
--c end if;
--c end if;
--c end process;
--c
--c process(rclk)
--c begin
--c if(rising_edge(rclk)) then
--c q <= ram(raddr);
--c end if;
--c end process;
--c
--c end rtl;
--c -- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| gpl-3.0 | a7fa5739d39929f17c5d98ef52242dd8 | 0.530082 | 3.257416 | false | false | false | false |
sils1297/HWPrak14 | task_3/task_3.srcs/sim_1/new/test.vhd | 1 | 3,435 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ADS7830 is
generic (I2C_ADR : std_logic_vector(6 downto 0) := "1001000"
);
port (
SDA : inout std_logic;
SCL : in std_logic
);
end ADS7830;
architecture RTL of ADS7830 is
constant CMD_WORD : std_logic_vector(7 downto 0) := x"8C";
constant MEM_WORD : std_logic_vector(7 downto 0) := x"55"; --x"9A";
signal SDA_latched : std_logic := '1';
signal start_or_stop : std_logic;
signal bitcnt : unsigned(3 downto 0) := "1111"; -- counts the I2C bits from 7 downto 0, plus an ACK bit
signal bit_DATA : std_logic;
signal bit_ACK : std_logic;
signal data_phase : std_logic := '0';
signal adr_phase : std_logic;
signal adr_match : std_logic := '0';
signal op_read : std_logic := '0';
signal mem : std_logic_vector(7 downto 0) := MEM_WORD;
signal op_write : std_logic;
signal mem_bit_low : std_logic;
signal SDA_assert_low : std_logic;
signal SDA_assert_ACK : std_logic;
signal SDA_low : std_logic;
signal adr_reg : std_logic_vector(6 downto 0) := "0000000";
signal SDA_int : std_logic;
signal SCL_int : std_logic;
signal initialized : std_logic := '0';
signal SDA_edge : std_logic;
begin
-- for simulation only
SDA_int <= '0' when SDA = '0' else '1';
SCL_int <= '0' when SCL = '0' else '1';
-- We use two wires with a combinatorial loop to detect the start and stop conditions
-- making sure these two wires don't get optimized away
SDA_latched <= SDA_int when (SCL_int = '0') else --((SCL_int = '0') or (start_or_stop = '1')) else
SDA_latched;
SDA_edge <= SDA_int xor SDA_latched;
start_or_stop <= '0' when (SCL_int = '0') else
SDA_edge;
bit_ACK <= bitcnt(3); -- the ACK bit is the 9th bit sent
bit_DATA <= not bit_ACK;
bitcounter: process (SCL_int, start_or_stop)
begin
if (start_or_stop = '1') then
bitcnt <= x"7"; -- the bit 7 is received first
data_phase <= '0';
elsif (SCL_int'event and SCL_int = '0') then
if (bit_ACK = '1') then
bitcnt <= x"7";
data_phase <= '1';
else
bitcnt <= bitcnt - 1;
end if;
end if;
end process;
adr_phase <= not data_phase;
op_write <= not op_read;
regs: process (SCL_int, start_or_stop)
variable cmd_reg : std_logic_vector(7 downto 0) := x"00";
begin
if (start_or_stop = '1') then
adr_match <= '0';
op_read <= '0';
elsif (SCL_int'event and SCL_int = '1') then
if (adr_phase = '1') then
if (bitcnt > "000") then
adr_reg <= adr_reg(5 downto 0) & SDA_int;
else
op_read <= SDA_int;
if (adr_reg = I2C_ADR(6 downto 0)) then
adr_match <= '1';
end if;
end if;
end if;
if (data_phase='1' and adr_match = '1') then
if (op_write='1' and initialized='0') then
if (bitcnt >= "000") then
cmd_reg := cmd_reg(6 downto 0) & SDA_int;
end if;
if (bitcnt = "000" and cmd_reg = CMD_WORD) then
initialized <= '1';
end if;
end if;
end if;
end if;
end process;
mem_bit_low <= not mem(to_integer(bitcnt(2 downto 0)));
SDA_assert_low <= adr_match and bit_DATA and data_phase and op_read and mem_bit_low and initialized;
SDA_assert_ACK <= adr_match and bit_ACK and (adr_phase or op_write);
SDA_low <= SDA_assert_low or SDA_assert_ACK;
SDA <= '0' when (SDA_low = '1') else 'Z';
end RTL;
| agpl-3.0 | 31b831ca43bd6b2d21fb1b0d16fc8052 | 0.592722 | 2.666925 | false | false | false | false |
jdryg/tis100cpu | cpu_1x3.vhd | 1 | 6,784 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity cpu_1x3 is
generic (
PROGRAM_00 : string := "input.prg";
PROGRAM_01 : string := "passthrough.prg";
PROGRAM_02 : string := "output.prg");
port (
I_clk : in std_logic;
I_reset : in std_logic);
end cpu_1x3;
architecture Behavioral of cpu_1x3 is
component ben is
Generic (PROGRAM_FILENAME : string);
Port ( I_clk, I_reset : in STD_LOGIC;
I_puw_dataValid : in STD_LOGIC;
I_pdw_dataValid : in STD_LOGIC;
I_plw_dataValid : in STD_LOGIC;
I_prw_dataValid : in STD_LOGIC;
I_pur_dataValid : in STD_LOGIC;
I_pdr_dataValid : in STD_LOGIC;
I_plr_dataValid : in STD_LOGIC;
I_prr_dataValid : in STD_LOGIC;
I_pur_data : in STD_LOGIC_VECTOR (15 downto 0);
I_pdr_data : in STD_LOGIC_VECTOR (15 downto 0);
I_plr_data : in STD_LOGIC_VECTOR (15 downto 0);
I_prr_data : in STD_LOGIC_VECTOR (15 downto 0);
O_puw_writeEnable : out STD_LOGIC;
O_pdw_writeEnable : out STD_LOGIC;
O_plw_writeEnable : out STD_LOGIC;
O_prw_writeEnable : out STD_LOGIC;
O_puw_data : out STD_LOGIC_VECTOR (15 downto 0);
O_pdw_data : out STD_LOGIC_VECTOR (15 downto 0);
O_plw_data : out STD_LOGIC_VECTOR (15 downto 0);
O_prw_data : out STD_LOGIC_VECTOR (15 downto 0);
O_pur_readEnable : out STD_LOGIC;
O_pdr_readEnable : out STD_LOGIC;
O_plr_readEnable : out STD_LOGIC;
O_prr_readEnable : out STD_LOGIC);
end component;
component node_port is
generic (WIDTH: integer := 8);
port ( I_clk : in STD_LOGIC;
I_reset : in STD_LOGIC;
I_writeEnable: in STD_LOGIC;
I_readEnable: in STD_LOGIC;
I_dataIn : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
O_dataOut : out STD_LOGIC_VECTOR (WIDTH-1 downto 0);
O_dataOutValid : out STD_LOGIC); -- TODO: Check if this is actually needed. We can reset the O_dataOut(0) to Z or U instead.
end component;
signal inputWriteMainRead_writeEnable : STD_LOGIC := '0';
signal inputWriteMainRead_readEnable : STD_LOGIC := '0';
signal input_dataOut : STD_LOGIC_VECTOR (15 downto 0) := X"0000";
signal main_dataIn : STD_LOGIC_VECTOR (15 downto 0) := X"0000";
signal main_dataInValid : STD_LOGIC := '0';
signal mainWriteOutputRead_writeEnable : STD_LOGIC := '0';
signal mainWriteOutputRead_readEnable : STD_LOGIC := '0';
signal main_dataOut : STD_LOGIC_VECTOR (15 downto 0) := X"0000";
signal output_dataIn : STD_LOGIC_VECTOR (15 downto 0) := X"0000";
signal output_dataInValid : STD_LOGIC := '0';
begin
inputWriteMainRead : node_port
generic map(WIDTH => 16)
port map(
I_clk => I_clk,
I_reset => I_reset,
I_writeEnable => inputWriteMainRead_writeEnable,
I_readEnable => inputWriteMainRead_readEnable,
I_dataIn => input_dataOut,
O_dataOut => main_dataIn,
O_dataOutValid => main_dataInValid);
mainWriteOutputRead: node_port
generic map(WIDTH => 16)
port map(
I_clk => I_clk,
I_reset => I_reset,
I_writeEnable => mainWriteOutputRead_writeEnable,
I_readEnable => mainWriteOutputRead_readEnable,
I_dataIn => main_dataOut,
O_dataOut => output_dataIn,
O_dataOutValid => output_dataInValid);
-- Input BEN
inputBEN: ben
generic map(PROGRAM_FILENAME => PROGRAM_00)
port map(
I_clk => I_clk,
I_reset => I_reset,
-- Read
-- Input BENs should not read anything
I_pur_dataValid => '0',
I_pdr_dataValid => '0',
I_plr_dataValid => '0',
I_prr_dataValid => '0',
I_pur_data => X"0000",
I_pdr_data => X"0000",
I_plr_data => X"0000",
I_prr_data => X"0000",
O_pur_readEnable => open,
O_pdr_readEnable => open,
O_plr_readEnable => open,
O_prr_readEnable => open,
-- Write
I_puw_dataValid => '0',
I_pdw_dataValid => main_dataInValid,
I_plw_dataValid => '0',
I_prw_dataValid => '0',
O_puw_writeEnable => open,
O_pdw_writeEnable => inputWriteMainRead_writeEnable,
O_plw_writeEnable => open,
O_prw_writeEnable => open,
O_puw_data => open,
O_pdw_data => input_dataOut,
O_plw_data => open,
O_prw_data => open);
-- Main BEN
mainBEN: ben
generic map(PROGRAM_FILENAME => PROGRAM_01)
port map(
I_clk => I_clk,
I_reset => I_reset,
-- Read
I_pur_dataValid => main_dataInValid,
I_pdr_dataValid => '0',
I_plr_dataValid => '0',
I_prr_dataValid => '0',
I_pur_data => main_dataIn,
I_pdr_data => X"0000",
I_plr_data => X"0000",
I_prr_data => X"0000",
O_pur_readEnable => inputWriteMainRead_readEnable,
O_pdr_readEnable => open,
O_plr_readEnable => open,
O_prr_readEnable => open,
-- Write
I_puw_dataValid => '0', -- Don't write to input BENs
I_pdw_dataValid => output_dataInValid,
I_plw_dataValid => '0', -- No left BEN
I_prw_dataValid => '0', -- No right BEN
O_puw_writeEnable => open, -- Don't write to input BENs
O_pdw_writeEnable => mainWriteOutputRead_writeEnable,
O_plw_writeEnable => open, -- No left BEN
O_prw_writeEnable => open, -- No right BEN
O_puw_data => open, -- Don't write to input BENs
O_pdw_data => main_dataOut,
O_plw_data => open, -- No left BEN
O_prw_data => open); -- No right BEN
-- Output BEN
outputBEN: ben
generic map(PROGRAM_FILENAME => PROGRAM_02)
port map(
I_clk => I_clk,
I_reset => I_reset,
-- Read
I_pur_dataValid => output_dataInValid,
I_pdr_dataValid => '0',
I_plr_dataValid => '0',
I_prr_dataValid => '0',
I_pur_data => output_dataIn,
I_pdr_data => X"0000",
I_plr_data => X"0000",
I_prr_data => X"0000",
O_pur_readEnable => mainWriteOutputRead_readEnable,
O_pdr_readEnable => open,
O_plr_readEnable => open,
O_prr_readEnable => open,
-- Write
-- Output BENs should not write anything
I_puw_dataValid => '0',
I_pdw_dataValid => '0',
I_plw_dataValid => '0',
I_prw_dataValid => '0',
O_puw_writeEnable => open,
O_pdw_writeEnable => open,
O_plw_writeEnable => open,
O_prw_writeEnable => open,
O_puw_data => open,
O_pdw_data => open,
O_plw_data => open,
O_prw_data => open);
end Behavioral;
| mit | e1a03499f253b68cb0e1003d4ef7387f | 0.562647 | 3.441908 | false | false | false | false |
BBN-Q/APS2-Comms | src/ip/cpld_bridge/cpld_bridge.vhd | 1 | 4,033 | -- Bridge to the CPLD-FPGA Interface
-- For now just wraps the ZRL ApsMsgProc but in the future will be our own solution
--
-- Original author: Colm Ryan
-- Copyright 2015,2016 Raytheon BBN Technologies
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.cpld_bridge_pkg.all;
entity CPLD_bridge is
generic (
BOARD_TYPE : std_logic_vector(7 downto 0) := x"00" -- x"00" for APS; x"01" for TDM
);
port (
clk : in std_logic;
rst : in std_logic;
--RX and TX to TCP comms.
rx_tdata : in std_logic_vector(31 downto 0);
rx_tvalid : in std_logic;
rx_tready : out std_logic;
rx_tlast : in std_logic;
tx_tdata : out std_logic_vector(31 downto 0);
tx_tvalid : out std_logic;
tx_tready : in std_logic;
tx_tlast : out std_logic;
-- Config Bus Connections
cfg_clk : in std_logic; -- 100 MHZ clock from the Config CPLD
cfgd : inout std_logic_vector(15 downto 0); -- Config Data bus from CPLD
fpga_cmdl : out std_logic; -- Command strobe from FPGA
fpga_rdyl : out std_logic; -- Ready Strobe from FPGA
cfg_rdy : in std_logic; -- Ready to complete current transfer. Connected to CFG_RDWR_B
cfg_err : in std_logic; -- Error during current command. Connecte to CFG_CSI_B
cfg_act : in std_logic; -- Current transaction is complete
stat_oel : out std_logic -- Enable CPLD to drive status onto CFGD
);
end entity;
architecture arch of CPLD_bridge is
--ApsMsgProc signals
signal msgproc_rx_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal msgproc_rx_tvalid, msgproc_rx_tready, msgproc_rx_tlast : std_logic := '0';
signal msgproc_tx_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal msgproc_tx_tvalid, msgproc_tx_tready, msgproc_tx_tlast : std_logic := '0';
--internal signal to work around Vivado not allowing functions on the left hand-side of a port-map
signal tx_tdata_int : std_logic_vector(31 downto 0);
begin
--Adapt rx and tx streams from 32 to 8 bits for MsgProc with byte swapping
rx_axis_adapter_inst : axis_adapter
generic map (
INPUT_DATA_WIDTH => 32,
INPUT_KEEP_WIDTH => 4,
OUTPUT_DATA_WIDTH => 8,
OUTPUT_KEEP_WIDTH => 1
)
port map (
clk => clk,
rst => rst,
input_axis_tdata => byte_swap(rx_tdata),
input_axis_tkeep => (others => '1'),
input_axis_tvalid => rx_tvalid,
input_axis_tready => rx_tready,
input_axis_tlast => rx_tlast,
input_axis_tuser => '0',
output_axis_tdata => msgproc_rx_tdata,
output_axis_tkeep => open,
output_axis_tvalid => msgproc_rx_tvalid,
output_axis_tready => msgproc_rx_tready,
output_axis_tlast => msgproc_rx_tlast,
output_axis_tuser => open
);
tx_axis_adapter_inst : axis_adapter
generic map (
INPUT_DATA_WIDTH => 8,
INPUT_KEEP_WIDTH => 1,
OUTPUT_DATA_WIDTH => 32,
OUTPUT_KEEP_WIDTH => 4
)
port map (
clk => clk,
rst => rst,
input_axis_tdata => msgproc_tx_tdata,
input_axis_tkeep(0) => msgproc_tx_tvalid,
input_axis_tvalid => msgproc_tx_tvalid,
input_axis_tready => msgproc_tx_tready,
input_axis_tlast => msgproc_tx_tlast,
input_axis_tuser => '0',
output_axis_tdata => tx_tdata_int,
output_axis_tkeep => open,
output_axis_tvalid => tx_tvalid,
output_axis_tready => tx_tready,
output_axis_tlast => tx_tlast,
output_axis_tuser => open
);
tx_tdata <= byte_swap(tx_tdata_int);
--Instantiate wrapper around ZRL ApsMsgProc
apsmsgproc_wrapper_inst : entity work.ApsMsgProc_wrapper
generic map( BOARD_TYPE => BOARD_TYPE )
port map (
clk => clk,
rst => rst,
--RX and TX to TCP comms.
rx_tdata => msgproc_rx_tdata,
rx_tvalid => msgproc_rx_tvalid,
rx_tready => msgproc_rx_tready,
rx_tlast => msgproc_rx_tlast,
tx_tdata => msgproc_tx_tdata,
tx_tvalid => msgproc_tx_tvalid,
tx_tready => msgproc_tx_tready,
tx_tlast => msgproc_tx_tlast,
-- Config Bus Connections
cfg_clk => cfg_clk,
cfgd => cfgd,
fpga_cmdl => fpga_cmdl,
fpga_rdyl => fpga_rdyl,
cfg_rdy => cfg_rdy,
cfg_err => cfg_err,
cfg_act => cfg_act,
stat_oel => stat_oel
);
end architecture;
| mpl-2.0 | 3c17f359b4844d35132eeea33e79073b | 0.670469 | 2.90562 | false | false | false | false |
rcls/sdr | test/test_phasedetect.vhd | 1 | 2,258 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.defs.all;
use work.phasedetect;
entity test_phasedetect is
port (qq_d : out signed(3 downto 0);
ii_d : out signed(3 downto 0);
phase : out unsigned18);
end test_phasedetect;
architecture behavioural of test_phasedetect is
signal qq_in : signed36 := (others => '0');
signal ii_in : signed36 := (others => '0');
signal clk : std_logic := '0';
subtype nibble is signed(3 downto 0);
subtype nibble_pair is signed(7 downto 0);
type test_nibbles is array(integer range <>) of nibble_pair;
signal nibbles : test_nibbles(0 to 59) := (
x"07", x"17", x"27", x"37", x"47", x"57", x"67", x"77",
x"76", x"75", x"74", x"73", x"72", x"71", x"70",
x"7f", x"7e", x"7d", x"7c", x"7b", x"7a", x"79", x"78",
x"68", x"58", x"48", x"38", x"28", x"18", x"08",
x"f8", x"e8", x"d8", x"c8", x"b8", x"a8", x"98", x"88",
x"89", x"8a", x"8b", x"8c", x"8d", x"8e", x"8f",
x"80", x"81", x"82", x"83", x"84", x"85", x"86", x"87",
x"97", x"a7", x"b7", x"c7", x"d7", x"e7", x"f7");
signal qq1 : nibble;
signal ii1 : nibble;
signal qq2 : nibble;
signal ii2 : nibble;
signal qq3 : nibble;
signal ii3 : nibble;
signal div20 : integer := 0;
begin
uut: entity phasedetect port map (qq_in => qq_in, ii_in => ii_in,
phase => phase, clk => clk);
process
begin
-- hold reset state for 100 ns.
clk <= '0';
wait for 100 ns;
for i in 0 to 59 loop
qq_in <= nibbles(i)(7 downto 4) & x"00000000";
ii_in <= nibbles(i)(3 downto 0) & x"00000000";
for j in 0 to 19 loop
wait for 2 ns;
clk <= '1';
wait for 2 ns;
clk <= '0';
end loop;
end loop;
for j in 0 to 99 loop
wait for 2 ns;
clk <= '1';
wait for 2 ns;
clk <= '0';
end loop;
wait;
end process;
process
begin
wait until rising_edge(clk);
div20 <= (div20 + 1) mod 20;
if div20 = 19 then
qq1 <= qq_in(35 downto 32);
qq2 <= qq1;
qq3 <= qq2;
qq_d <= qq3;
ii1 <= ii_in(35 downto 32);
ii2 <= ii1;
ii3 <= ii2;
ii_d <= ii3;
end if;
end process;
end;
| gpl-3.0 | 3bc9400370488cce97f9db99e2bbf9ef | 0.523915 | 2.76377 | false | true | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/wb_mux_gti.vhd | 1 | 34,470 | `protect begin_protected
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 23776)
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`protect end_protected
| apache-2.0 | 32f8a9abb9e1dceaaf4f831425823daf | 0.947955 | 1.832146 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/builtin/builtin_extdepth.vhd | 5 | 92,803 | `protect begin_protected
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`protect end_protected
| apache-2.0 | 657a23502b93c37c84c13a074f36d97a | 0.952071 | 1.815147 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/mdm_v3_1/0d9386c2/hdl/vhdl/jtag_control.vhd | 1 | 75,400 | -------------------------------------------------------------------------------
-- $Id$
-------------------------------------------------------------------------------
-- jtag_control.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2003,2012,2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
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--
-- DISCLAIMER
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-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: jtag_control.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- jtag_control.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision$
-- Date: $Date$
--
-- History:
-- goran 2003-02-13 First Version
-- stefana 2012-03-16 Added support for 32 processors and external BSCAN
-- stefana 2013-11-01 Added extended debug: debug register access, debug
-- memory access, cross trigger support
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity JTAG_CONTROL is
generic (
C_MB_DBG_PORTS : integer;
C_USE_CONFIG_RESET : integer;
C_DBG_REG_ACCESS : integer;
C_DBG_MEM_ACCESS : integer;
C_M_AXI_ADDR_WIDTH : integer;
C_M_AXI_DATA_WIDTH : integer;
C_USE_CROSS_TRIGGER : integer;
C_USE_UART : integer;
C_UART_WIDTH : integer := 8;
C_EN_WIDTH : integer := 1
);
port (
-- Global signals
Config_Reset : in std_logic;
Clk : in std_logic;
Rst : in std_logic;
Clear_Ext_BRK : in std_logic;
Ext_BRK : out std_logic;
Ext_NM_BRK : out std_logic := '0';
Debug_SYS_Rst : out std_logic := '0';
Debug_Rst : out std_logic := '0';
Read_RX_FIFO : in std_logic;
Reset_RX_FIFO : in std_logic;
RX_Data : out std_logic_vector(0 to C_UART_WIDTH-1);
RX_Data_Present : out std_logic;
RX_BUFFER_FULL : out std_logic;
Write_TX_FIFO : in std_logic;
Reset_TX_FIFO : in std_logic;
TX_Data : in std_logic_vector(0 to C_UART_WIDTH-1);
TX_Buffer_Full : out std_logic;
TX_Buffer_Empty : out std_logic;
-- Debug Register Access signals
DbgReg_Access_Lock : in std_logic;
DbgReg_Force_Lock : in std_logic;
DbgReg_Unlocked : in std_logic;
JTAG_Access_Lock : out std_logic;
JTAG_Force_Lock : out std_logic;
JTAG_AXIS_Overrun : in std_logic;
JTAG_Clear_Overrun : out std_logic;
-- MDM signals
TDI : in std_logic;
RESET : in std_logic;
UPDATE : in std_logic;
SHIFT : in std_logic;
CAPTURE : in std_logic;
SEL : in std_logic;
DRCK : in std_logic;
TDO : out std_logic;
-- Bus Master signals
M_AXI_ACLK : in std_logic;
M_AXI_ARESETn : in std_logic;
Master_rd_start : out std_logic;
Master_rd_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_rd_len : out std_logic_vector(4 downto 0);
Master_rd_size : out std_logic_vector(1 downto 0);
Master_rd_excl : out std_logic;
Master_rd_idle : in std_logic;
Master_rd_resp : in std_logic_vector(1 downto 0);
Master_wr_start : out std_logic;
Master_wr_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_wr_len : out std_logic_vector(4 downto 0);
Master_wr_size : out std_logic_vector(1 downto 0);
Master_wr_excl : out std_logic;
Master_wr_idle : in std_logic;
Master_wr_resp : in std_logic_vector(1 downto 0);
Master_data_rd : out std_logic;
Master_data_out : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_data_exists : in std_logic;
Master_data_wr : out std_logic;
Master_data_in : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_data_empty : in std_logic;
-- MicroBlaze Debug Signals
MB_Debug_Enabled : out std_logic_vector(C_EN_WIDTH-1 downto 0);
Dbg_Clk : out std_logic;
Dbg_TDI : out std_logic;
Dbg_TDO : in std_logic;
Dbg_Reg_En : out std_logic_vector(0 to 7);
Dbg_Capture : out std_logic;
Dbg_Shift : out std_logic;
Dbg_Update : out std_logic;
-- MicroBlaze Cross Trigger Signals
Dbg_Trig_In_0 : in std_logic_vector(0 to 7);
Dbg_Trig_In_1 : in std_logic_vector(0 to 7);
Dbg_Trig_In_2 : in std_logic_vector(0 to 7);
Dbg_Trig_In_3 : in std_logic_vector(0 to 7);
Dbg_Trig_In_4 : in std_logic_vector(0 to 7);
Dbg_Trig_In_5 : in std_logic_vector(0 to 7);
Dbg_Trig_In_6 : in std_logic_vector(0 to 7);
Dbg_Trig_In_7 : in std_logic_vector(0 to 7);
Dbg_Trig_In_8 : in std_logic_vector(0 to 7);
Dbg_Trig_In_9 : in std_logic_vector(0 to 7);
Dbg_Trig_In_10 : in std_logic_vector(0 to 7);
Dbg_Trig_In_11 : in std_logic_vector(0 to 7);
Dbg_Trig_In_12 : in std_logic_vector(0 to 7);
Dbg_Trig_In_13 : in std_logic_vector(0 to 7);
Dbg_Trig_In_14 : in std_logic_vector(0 to 7);
Dbg_Trig_In_15 : in std_logic_vector(0 to 7);
Dbg_Trig_In_16 : in std_logic_vector(0 to 7);
Dbg_Trig_In_17 : in std_logic_vector(0 to 7);
Dbg_Trig_In_18 : in std_logic_vector(0 to 7);
Dbg_Trig_In_19 : in std_logic_vector(0 to 7);
Dbg_Trig_In_20 : in std_logic_vector(0 to 7);
Dbg_Trig_In_21 : in std_logic_vector(0 to 7);
Dbg_Trig_In_22 : in std_logic_vector(0 to 7);
Dbg_Trig_In_23 : in std_logic_vector(0 to 7);
Dbg_Trig_In_24 : in std_logic_vector(0 to 7);
Dbg_Trig_In_25 : in std_logic_vector(0 to 7);
Dbg_Trig_In_26 : in std_logic_vector(0 to 7);
Dbg_Trig_In_27 : in std_logic_vector(0 to 7);
Dbg_Trig_In_28 : in std_logic_vector(0 to 7);
Dbg_Trig_In_29 : in std_logic_vector(0 to 7);
Dbg_Trig_In_30 : in std_logic_vector(0 to 7);
Dbg_Trig_In_31 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_0 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_1 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_2 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_3 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_4 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_5 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_6 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_7 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_8 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_9 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_10 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_11 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_12 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_13 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_14 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_15 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_16 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_17 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_18 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_19 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_20 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_21 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_22 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_23 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_24 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_25 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_26 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_27 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_28 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_29 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_30 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_31 : in std_logic_vector(0 to 7);
Ext_Trig_In : in std_logic_vector(0 to 3);
Ext_Trig_Ack_In : out std_logic_vector(0 to 3);
Ext_Trig_Out : out std_logic_vector(0 to 3);
Ext_Trig_Ack_Out : in std_logic_vector(0 to 3)
);
end entity JTAG_CONTROL;
library unisim;
use unisim.vcomponents.all;
library mdm_v3_1;
use mdm_v3_1.SRL_FIFO;
architecture IMP of JTAG_CONTROL is
component SRL_FIFO
generic (
C_DATA_BITS : natural;
C_DEPTH : natural
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Full : out std_logic;
Data_Exists : out std_logic
);
end component SRL_FIFO;
--
-- Old Config Word in previous versions
--
-- Magic String + Has FSL + 0 + Has UART + UART Width + Num MB + Num hw ports + Debug Version
-- 8 bits + 1 bit + 1 bit + 1 bit + 5 bits + 8 bits + 4 bits + 4 bits
--
-- New Config Word in mdm v2
--
-- Magic String + 00 + Has UART + UART Width + Num MB + UART version + Debug Version
-- 8 bits + 2 bits + 1 bit + 5 bits + 8 bits + 4 bits + 4 bits
--
-- New Config Word in mdm v2 with extended debug
--
-- Extended Config + Magic String + 1 + Extended + Has UART + UART Width + Num MB + UART version + Debug Version
-- 3 bits + 8 bits + 1 bit + 1 bit + 1 bit + 5 bits + 8 bits + 4 bits + 4 bits
--
-- Debug Version Table
-- 0,1,2: Obsolete
-- 3,4: Watchpoint support
-- 5: Remove sync
-- 6: Change command and Reg_En signals to 8 bits
-- 7: Change MB_Debug_Enabled to 32 bits
--
-- UART Version Table
-- 0: Get version from Debug Version Table
-- 6: Non-buffered mode support
--
function TDI_Shifter_Size return integer is
begin
if C_DBG_MEM_ACCESS = 1 then
return 32;
elsif C_USE_CROSS_TRIGGER = 1 then
if C_MB_DBG_PORTS < 16 then
return 16;
else
return C_MB_DBG_PORTS;
end if;
elsif C_MB_DBG_PORTS > 8 then
return C_MB_DBG_PORTS;
end if;
return 8;
end function TDI_Shifter_Size;
function Which_MB_Reg_Size return integer is
begin
if C_MB_DBG_PORTS > 8 then
return C_MB_DBG_PORTS;
end if;
return 8;
end function Which_MB_Reg_Size;
constant No_MicroBlazes : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(C_MB_DBG_PORTS, 8));
constant UART_VERSION : std_logic_vector(3 downto 0) := "0110";
constant DEBUG_VERSION : std_logic_vector(3 downto 0) := "0111";
constant Config_Init_Word_S : std_logic_vector(15 downto 0) :=
(No_MicroBlazes & UART_VERSION & DEBUG_VERSION);
constant Config_Init_Word : bit_vector(15 downto 0) :=
to_bitvector(Config_Init_Word_S);
constant C_EXT_CONFIG : integer :=
Boolean'Pos(C_DBG_MEM_ACCESS > 0 or C_DBG_REG_ACCESS > 0 or C_USE_CROSS_TRIGGER > 0);
constant HAVE_EXTENDED : std_logic_vector(0 to 0) :=
std_logic_vector(to_unsigned(C_EXT_CONFIG, 1));
constant HAVE_UART : std_logic_vector(0 to 0) :=
std_logic_vector(to_unsigned(C_USE_UART, 1));
constant UART_WIDTH : std_logic_vector(0 to 4) :=
std_logic_vector(to_unsigned(C_UART_WIDTH-1, 5));
constant MAGIC_STRING : std_logic_vector(0 to 7) := "01000010";
constant Config_Init_Word2_S : std_logic_vector(15 downto 0) :=
(MAGIC_STRING & '1' & HAVE_EXTENDED & HAVE_UART & UART_WIDTH);
constant Config_Init_Word2 : bit_vector(15 downto 0) :=
to_bitvector(Config_Init_Word2_S);
constant Config_Init_Word3_S : std_logic_vector(15 downto 0) :=
std_logic_vector(to_unsigned(C_DBG_MEM_ACCESS, 1) &
to_unsigned(C_DBG_REG_ACCESS, 1) &
to_unsigned(C_USE_CROSS_TRIGGER, 1) &
to_unsigned(0, 13));
constant Config_Init_Word3 : bit_vector(15 downto 0) :=
to_bitvector(Config_Init_Word3_S);
signal config_TDO_1 : std_logic;
signal config_TDO_2 : std_logic;
signal config_TDO_3 : std_logic;
signal config_TDO : std_logic;
signal ID_TDO : std_logic;
signal ID_TDO_1 : std_logic;
signal ID_TDO_2 : std_logic;
signal uart_TDO : std_logic;
signal compl_TDO : std_logic;
signal master_TDO : std_logic;
signal axis_TDO : std_logic;
signal ct_TDO : std_logic;
-----------------------------------------------------------------------------
-- JTAG signals
-----------------------------------------------------------------------------
signal data_cmd : std_logic;
signal data_cmd_n : std_logic;
signal data_cmd_noblock : std_logic;
signal sel_n : std_logic;
signal sel_n_delay : std_logic_vector(0 to 5);
signal command : std_logic_vector(0 to 7) := (others => '0');
signal command_1 : std_logic_vector(0 to 7) := (others => '0');
signal tdi_shifter : std_logic_vector(0 to TDI_Shifter_Size - 1) := (others => '0');
signal shifting_Data : std_logic;
signal sync_detected : std_logic;
signal sync : std_logic;
constant SYNC_CONST : std_logic_vector(1 to 8) := "01101001";
signal shift_Count : std_logic_vector(4 + C_EXT_CONFIG downto 0) := (others => '0');
signal mb_debug_enabled_i : std_logic_vector(C_EN_WIDTH-1 downto 0);
constant C_NUM_DBG_CT : integer := 8;
constant C_NUM_EXT_CT : integer := 4;
type dbg_trig_type is array (0 to 31) of std_logic_vector(0 to C_NUM_DBG_CT - 1);
signal dbg_trig_ack_in_i : dbg_trig_type;
signal dbg_trig_out_i : dbg_trig_type;
signal ext_trig_ack_in_i : std_logic_vector(0 to C_NUM_EXT_CT - 1);
signal ext_trig_out_i : std_logic_vector(0 to C_NUM_EXT_CT - 1);
signal completion_ctrl : std_logic_vector(0 downto 0) := (others => '0');
signal completion_status : std_logic_vector(15 downto 0) := (others => '0');
signal completion_block : std_logic := '0';
signal clear_overrun : std_logic := '0';
signal mb_instr_overrun : std_logic := '0';
signal mb_instr_error : std_logic := '0';
signal mb_data_overrun : std_logic := '0';
signal master_overrun : std_logic;
signal master_error : std_logic;
-----------------------------------------------------------------------------
-- Register handling
-----------------------------------------------------------------------------
constant MDM_DEBUG_ID : std_logic_vector(0 to 7) := "00000000";
constant MB_WRITE_CONTROL : std_logic_vector(0 to 7) := "00000001";
constant MB_WRITE_COMMAND : std_logic_vector(0 to 7) := "00000010";
constant MB_READ_STATUS : std_logic_vector(0 to 7) := "00000011";
constant MB_WRITE_INSTR : std_logic_vector(0 to 7) := "00000100";
--constant MB_WRITE_DATA : std_logic_vector(0 to 7) := "00000101";
constant MB_READ_DATA : std_logic_vector(0 to 7) := "00000110";
constant MB_READ_CONFIG : std_logic_vector(0 to 7) := "00000111";
constant MB_WRITE_BRK_RST_CTRL : std_logic_vector(0 to 7) := "00001000";
constant UART_WRITE_BYTE : std_logic_vector(0 to 7) := "00001001";
constant UART_READ_STATUS : std_logic_vector(0 to 7) := "00001010";
constant UART_READ_BYTE : std_logic_vector(0 to 7) := "00001011";
constant MDM_READ_CONFIG : std_logic_vector(0 to 7) := "00001100";
constant MDM_WRITE_WHICH_MB : std_logic_vector(0 to 7) := "00001101";
constant UART_WRITE_CONTROL : std_logic_vector(0 to 7) := "00001110";
--constant MDM_WRITE_TO_FSL : std_logic_vector(0 to 7) := "00001111";
-- registers "00010000" to "00011111" are pc breakpoints 1-16
constant BUSM_WRITE_DATA : std_logic_vector(0 to 7) := "00100001";
constant BUSM_READ_STATUS : std_logic_vector(0 to 7) := "00100010";
constant BUSM_READ_DATA : std_logic_vector(0 to 7) := "00100011";
constant BUSM_WRITE_COMMAND : std_logic_vector(0 to 7) := "00100101";
constant BUSM_WRITE_CONTROL : std_logic_vector(0 to 7) := "00100110";
constant MDM_READ_COMPL_STATUS : std_logic_vector(0 to 7) := "00101010";
constant MDM_WRITE_COMPL_CTRL : std_logic_vector(0 to 7) := "00101101";
constant AXIS_READ_STATUS : std_logic_vector(0 to 7) := "00110010";
constant AXIS_WRITE_COMMAND : std_logic_vector(0 to 7) := "00110110";
constant CT_WRITE_EXT_CTRL : std_logic_vector(0 to 7) := "01000000";
constant CT_READ_STATUS : std_logic_vector(0 to 7) := "01000010";
constant CT_WRITE_CTRL : std_logic_vector(0 to 7) := "01000110";
-- registers "01010000" to "11111111" are reserved
-----------------------------------------------------------------------------
-- Internal signals for debugging
-----------------------------------------------------------------------------
signal set_Ext_BRK : std_logic := '0';
signal ext_BRK_i : std_logic := '0';
signal Ext_NM_BRK_i : std_logic := '0';
signal Debug_SYS_Rst_i : std_logic := '0';
signal Debug_Rst_i : std_logic := '0';
constant ID_Init_Word1 : bit_vector(15 downto 0) := x"4443"; -- Ascii
constant ID_Init_Word2 : bit_vector(15 downto 0) := x"584D"; -- "XMDC"
attribute KEEP : string;
begin -- architecture IMP
-----------------------------------------------------------------------------
-- Control logic
-----------------------------------------------------------------------------
-- data_cmd | meaning
-- ======================
-- 0 | Command phase
-- 1 | Data phase
FDC_I : FDC_1
port map (
Q => data_cmd_noblock, -- [out std_logic]
C => Update, -- [in std_logic]
D => data_cmd_n, -- [in std_logic]
CLR => sel_n); -- [in std_logic]
data_cmd_n <= not data_cmd_noblock;
data_cmd <= data_cmd_noblock and not completion_block;
-- sel_n <= not SEL;
-- Need to delay sel_n to make sure that it arrives at the FDC_I after the
-- falling edge of Update. Update can get a long skew so extra LUTS are
-- inserted as delay elements
sel_n_delay(0) <= not SEL;
Insert_Delays : for I in sel_n_delay'left to sel_n_delay'right-1 generate
signal local_sel_n : std_logic;
attribute KEEP of local_sel_n : signal is "TRUE";
begin
LUT_Delay : LUT4
generic map(
INIT => X"0002"
)
port map (
O => local_sel_n, -- [out]
I0 => sel_n_delay(I), -- [in]
I1 => '0', -- [in]
I2 => '0', -- [in]
I3 => '0'); -- [in]
sel_n_delay(I+1) <= local_sel_n;
end generate Insert_Delays;
sel_n <= sel_n_delay(sel_n_delay'right) or Config_Reset;
Input_shifter : process (DRCK, Config_Reset)
begin
if Config_Reset = '1' then
tdi_shifter <= (others => '0');
elsif DRCK'event and DRCK = '1' then
if SEL = '1' and SHIFT = '1' then
tdi_shifter <= TDI & tdi_shifter(0 to tdi_shifter'right - 1);
end if;
end if;
end process Input_shifter;
Command_update : process (UPDATE, Config_Reset)
begin
if Config_Reset = '1' then
command <= (others => '0');
elsif UPDATE'event and UPDATE = '0' then
if SEL = '1' then
command <= command_1;
end if;
end if;
end process Command_update;
Command_update_1 : process (UPDATE, Config_Reset)
begin
if Config_Reset = '1' then
command_1 <= (others => '0');
elsif UPDATE'event and UPDATE = '1' then
if SEL = '1' and data_cmd = '0' then
command_1 <= tdi_shifter (0 to 7);
end if;
end if;
end process Command_update_1;
Dbg_Clk <= DRCK;
Dbg_Reg_En <= command when data_cmd = '1' else (others => '0');
Dbg_TDI <= TDI;
Dbg_Capture <= CAPTURE;
Dbg_Update <= UPDATE;
-- No sync word requirement for commands other than "Write Instruction"
shifting_Data <= (SHIFT and sync)
when (command = MB_WRITE_INSTR) and (data_cmd = '1')
else SHIFT;
Dbg_Shift <= shifting_Data;
sync_detected <= '1' when tdi_shifter(0 to 7) = SYNC_CONST and data_cmd = '1'
else '0';
SYNC_FDRE : FDRE_1
port map (
Q => sync,
C => DRCK,
CE => sync_detected,
D => '1',
R => data_cmd_n);
-----------------------------------------------------------------------------
-- Shift Counter
-----------------------------------------------------------------------------
-- Keep a counter on the number of bits in the data phase after a sync has
-- been detected
Shift_Counter : process (DRCK, Config_Reset) is
begin -- process Shift_Counter
if Config_Reset = '1' then
shift_Count <= (others => '0');
elsif DRCK'event and DRCK = '1' then -- rising clock edge
if SHIFT = '0' then
shift_Count <= (others => '0');
else
shift_Count <= std_logic_vector(unsigned(Shift_Count) + 1);
end if;
end if;
end process Shift_Counter;
-----------------------------------------------------------------------------
-- Config Register
-----------------------------------------------------------------------------
Use_Config_SRL16E : if (C_USE_CONFIG_RESET = 0) generate
begin
SRL16E_1 : SRL16E
generic map (
INIT => Config_Init_Word
)
port map (
CE => '0', -- [in std_logic]
D => '0', -- [in std_logic]
Clk => DRCK, -- [in std_logic]
A0 => shift_Count(0), -- [in std_logic]
A1 => shift_Count(1), -- [in std_logic]
A2 => shift_Count(2), -- [in std_logic]
A3 => shift_Count(3), -- [in std_logic]
Q => config_TDO_1); -- [out std_logic]
SRL16E_2 : SRL16E
generic map (
INIT => Config_Init_Word2
)
port map (
CE => '0', -- [in std_logic]
D => '0', -- [in std_logic]
Clk => DRCK, -- [in std_logic]
A0 => shift_Count(0), -- [in std_logic]
A1 => shift_Count(1), -- [in std_logic]
A2 => shift_Count(2), -- [in std_logic]
A3 => shift_Count(3), -- [in std_logic]
Q => config_TDO_2); -- [out std_logic]
Use_Ext_Config: if (C_EXT_CONFIG > 0) generate
begin
SRL16E_3 : SRL16E
generic map (
INIT => Config_Init_Word3
)
port map (
CE => '0', -- [in std_logic]
D => '0', -- [in std_logic]
Clk => DRCK, -- [in std_logic]
A0 => shift_Count(0), -- [in std_logic]
A1 => shift_Count(1), -- [in std_logic]
A2 => shift_Count(2), -- [in std_logic]
A3 => shift_Count(3), -- [in std_logic]
Q => config_TDO_3); -- [out std_logic]
end generate Use_Ext_Config;
end generate Use_Config_SRL16E;
No_Config_SRL16E : if (C_USE_CONFIG_RESET = 1) generate
begin
config_TDO_1 <= Config_Init_Word_S(to_integer(unsigned(shift_Count(3 downto 0))));
config_TDO_2 <= Config_Init_Word2_S(to_integer(unsigned(shift_Count(3 downto 0))));
Use_Ext_Config: if (C_EXT_CONFIG > 0) generate
begin
config_TDO_3 <= Config_Init_Word3_S(to_integer(unsigned(shift_Count(3 downto 0))));
end generate Use_Ext_Config;
end generate No_Config_SRL16E;
Use_Ext_Config: if (C_EXT_CONFIG > 0) generate
begin
config_TDO <= config_TDO_1 when shift_Count(5 downto 4) = "00" else
config_TDO_2 when shift_Count(5 downto 4) = "01" else
config_TDO_3;
end generate Use_Ext_Config;
No_Ext_Config: if (C_EXT_CONFIG = 0) generate
begin
config_TDO_3 <= '0'; -- Unused
config_TDO <= config_TDO_1 when shift_Count(4) = '0' else config_TDO_2;
end generate No_Ext_Config;
-----------------------------------------------------------------------------
-- ID Register
-----------------------------------------------------------------------------
Use_ID_SRL16E : if (C_USE_CONFIG_RESET = 0) generate
begin
SRL16E_ID_1 : SRL16E
generic map (
INIT => ID_Init_Word1
)
port map (
CE => '0',
D => '0',
Clk => DRCK,
A0 => shift_Count(0),
A1 => shift_Count(1),
A2 => shift_Count(2),
A3 => shift_Count(3),
Q => ID_TDO_1);
SRL16E_ID_2 : SRL16E
generic map (
INIT => ID_Init_Word2
)
port map (
CE => '0',
D => '0',
Clk => DRCK,
A0 => shift_Count(0),
A1 => shift_Count(1),
A2 => shift_Count(2),
A3 => shift_Count(3),
Q => ID_TDO_2);
end generate Use_ID_SRL16E;
No_ID_SRL16E : if (C_USE_CONFIG_RESET = 1) generate
begin
ID_TDO_1 <= To_X01(ID_Init_Word1(to_integer(unsigned(shift_Count(3 downto 0)))));
ID_TDO_2 <= To_X01(ID_Init_Word2(to_integer(unsigned(shift_Count(3 downto 0)))));
end generate No_ID_SRL16E;
ID_TDO <= ID_TDO_1 when shift_Count(4) = '0' else ID_TDO_2;
-----------------------------------------------------------------------------
-- Handling the Which_MB register
-----------------------------------------------------------------------------
More_Than_One_MB : if (C_MB_DBG_PORTS > 1) generate
signal Which_MB_Reg : std_logic_vector(Which_MB_Reg_Size - 1 downto 0) := (others => '0');
begin
Which_MB_Reg_Handle : process (UPDATE, Config_Reset)
begin
if Config_Reset = '1' then
Which_MB_Reg <= (others => '0');
elsif UPDATE'event and UPDATE = '0' then
if SEL = '1' and data_cmd = '1' and command = MDM_WRITE_WHICH_MB then
Which_MB_Reg <= tdi_shifter(0 to Which_MB_Reg_Size - 1);
end if;
end if;
end process Which_MB_Reg_Handle;
mb_debug_enabled_i(C_MB_DBG_PORTS-1 downto 0) <=
Which_MB_Reg(C_MB_DBG_PORTS-1 downto 0);
end generate More_Than_One_MB;
Only_One_MB : if (C_MB_DBG_PORTS = 1) generate
mb_debug_enabled_i(0) <= '1';
end generate Only_One_MB;
No_MB : if (C_MB_DBG_PORTS = 0) generate
mb_debug_enabled_i(0) <= '0';
end generate No_MB;
MB_Debug_Enabled <= mb_debug_enabled_i;
-----------------------------------------------------------------------------
-- Reset Control
-----------------------------------------------------------------------------
Reset_Control : process (UPDATE, Config_Reset)
begin -- process Reset_Control
if Config_Reset = '1' then
Debug_Rst_i <= '0';
Debug_SYS_Rst_i <= '0';
set_Ext_BRK <= '0';
Ext_NM_BRK_i <= '0';
elsif UPDATE'event and UPDATE = '1' then
if command = MB_WRITE_BRK_RST_CTRL and data_cmd = '1' then
Debug_Rst_i <= tdi_shifter(0);
Debug_SYS_Rst_i <= tdi_shifter(1);
set_Ext_BRK <= tdi_shifter(2);
Ext_NM_BRK_i <= tdi_shifter(3);
end if;
end if;
end process Reset_Control;
-----------------------------------------------------------------------------
-- Execute Commands
-----------------------------------------------------------------------------
Debug_SYS_Rst <= Debug_SYS_Rst_i;
Debug_Rst <= Debug_Rst_i;
Ext_NM_BRK <= Ext_NM_BRK_i;
Ext_BRK <= ext_BRK_i;
-----------------------------------------------------------------------------
-- TDO Mux
-----------------------------------------------------------------------------
with command select
TDO <=
ID_TDO when MDM_DEBUG_ID,
uart_TDO when UART_READ_BYTE,
uart_TDO when UART_READ_STATUS,
config_TDO when MDM_READ_CONFIG,
master_TDO when BUSM_READ_DATA,
master_TDO when BUSM_READ_STATUS,
compl_TDO when MDM_READ_COMPL_STATUS,
axis_TDO when AXIS_READ_STATUS,
ct_TDO when CT_READ_STATUS,
Dbg_TDO when others;
-----------------------------------------------------------------------------
-- Unified Overrun and Error Detection section
-----------------------------------------------------------------------------
-- Completion Control (clears completion count and block):
-- 0 Enable completion block
Completion_Control_Register : process (UPDATE, Config_Reset)
begin
if Config_Reset = '1' then
completion_ctrl <= (others => '0');
elsif UPDATE'event and UPDATE = '1' then
if command = MDM_WRITE_COMPL_CTRL and data_cmd_noblock = '1' then
completion_ctrl <= tdi_shifter(0 to 0);
end if;
end if;
end process Completion_Control_Register;
-- Completion Status:
-- 0-9 Command count
-- 10 MicroBlaze instruction insert overrun
-- 11 MicroBlaze instruction insert exception occurred
-- 12 MicroBlaze data read overrun
-- 13 Bus Master interface overrun
-- 14 Bus Master interface error occurred
-- 15 AXI Slave interface access locked
Completion_Status_Register : process (DRCK, Config_Reset) is
variable sample : std_logic_vector(15 downto 13);
variable sample_1 : std_logic_vector(15 downto 10);
attribute ASYNC_REG : string;
attribute ASYNC_REG of sample : variable is "TRUE";
begin -- process Completion_Status_Register
if Config_Reset = '1' then
completion_status <= (others => '0');
completion_block <= '0';
clear_overrun <= '0';
sample := (others => '0');
sample_1 := (others => '0');
elsif DRCK'event and DRCK = '1' then -- rising clock edge
if command = MDM_READ_COMPL_STATUS and data_cmd_noblock = '1' then
if CAPTURE = '1' then
completion_status(sample_1'range) <= sample_1;
elsif SHIFT = '1' then
completion_status <= '0' & completion_status(completion_status'left downto completion_status'right + 1);
end if;
elsif command = MDM_WRITE_COMPL_CTRL and data_cmd_noblock = '1' then
if CAPTURE = '1' then
completion_status(9 downto 0) <= (others => '0');
completion_block <= '0';
clear_overrun <= '1';
end if;
else
-- Sample and detect status change
if completion_ctrl(0) = '1' then
if (sample_1(10) = '0' and mb_instr_overrun = '1') or
(sample_1(11) = '0' and mb_instr_error = '1') or
(sample_1(12) = '0' and mb_data_overrun = '1') or
(sample_1(13) = '0' and sample(13) = '1') or
(sample_1(14) = '0' and sample(14) = '1') or
(sample_1(15) = '0' and sample(15) = '1') then
completion_block <= '1';
end if;
end if;
sample_1(15 downto 13) := sample;
sample_1(10) := mb_instr_overrun;
sample_1(11) := mb_instr_error;
sample_1(12) := mb_data_overrun;
sample(13) := master_overrun;
sample(14) := master_error;
sample(15) := JTAG_AXIS_Overrun;
-- Increment command count
if CAPTURE = '1' then
if data_cmd = '0' and completion_block = '0' then
completion_status(9 downto 0) <= std_logic_vector(unsigned(completion_status(9 downto 0)) + 1);
end if;
clear_overrun <= '0';
end if;
end if;
end if;
end process Completion_Status_Register;
compl_TDO <= completion_status(completion_status'right);
Write_Instr_Status : process (DRCK, Config_Reset) is
variable count : std_logic_vector(0 to 1) := "00";
begin -- process Write_Instr_Status
if Config_Reset = '1' then
mb_instr_overrun <= '0';
mb_instr_error <= '0';
count := "00";
elsif DRCK'event and DRCK = '1' then -- rising clock edge
if command = MB_WRITE_INSTR and data_cmd = '1' then
if CAPTURE = '1' then
mb_instr_overrun <= '0';
mb_instr_error <= '0';
count := "00";
elsif shifting_Data = '1' and count(0) = '0' then
if count(1) = '0' then
mb_instr_overrun <= Dbg_TDO;
end if;
if count(1) = '1' then
mb_instr_error <= Dbg_TDO;
end if;
count := std_logic_vector(unsigned(count) + 1);
end if;
end if;
end if;
end process Write_Instr_Status;
Data_Read_Status : process (DRCK, Config_Reset) is
variable count : std_logic_vector(0 to 5) := "000000";
begin -- process Data_Read_Status
if Config_Reset = '1' then
mb_data_overrun <= '0';
count := "000000";
elsif DRCK'event and DRCK = '1' then -- rising clock edge
if command = MB_READ_DATA and data_cmd = '1' then
if CAPTURE = '1' then
mb_data_overrun <= '0';
count := "000000";
elsif SHIFT = '1' then
if count(0) = '1' then
mb_data_overrun <= not Dbg_TDO;
end if;
count := std_logic_vector(unsigned(count) + 1);
end if;
end if;
end if;
end process Data_Read_Status;
-----------------------------------------------------------------------------
-- UART section
-----------------------------------------------------------------------------
Use_UART : if (C_USE_UART = 1) generate
signal execute : std_logic := '0';
signal execute_1 : std_logic := '0';
signal execute_2 : std_logic := '0';
signal execute_3 : std_logic := '0';
signal fifo_DOut : std_logic_vector(0 to C_UART_WIDTH-1);
signal fifo_Data_Present : std_logic := '0';
signal fifo_Din : std_logic_vector(0 to C_UART_WIDTH-1);
signal fifo_Read : std_logic := '0';
signal fifo_Write : std_logic := '0';
signal rx_Buffer_Full_I : std_logic := '0';
signal rx_Data_Present_I : std_logic := '0';
signal status_reg : std_logic_vector(0 to 7) := (others => '0');
signal tdo_reg : std_logic_vector(0 to C_UART_WIDTH-1) := (others => '0');
signal tx_Buffer_Full_I : std_logic := '0';
signal tx_buffered : std_logic := '0'; -- Non-buffered mode on startup
signal tx_buffered_1 : std_logic := '0';
signal tx_buffered_2 : std_logic := '0';
signal tx_fifo_wen : std_logic;
attribute ASYNC_REG : string;
attribute ASYNC_REG of execute_1 : signal is "TRUE";
attribute ASYNC_REG of execute_2 : signal is "TRUE";
attribute ASYNC_REG of tx_buffered_1 : signal is "TRUE";
attribute ASYNC_REG of tx_buffered_2 : signal is "TRUE";
begin
Ext_BRK_FDRSE : FDRSE
port map (
Q => ext_BRK_i, -- [out std_logic]
C => Clk, -- [in std_logic]
CE => '0', -- [in std_logic]
D => '0', -- [in std_logic]
R => Clear_Ext_BRK, -- [in std_logic]
S => set_Ext_BRK); -- [in std_logic]
-----------------------------------------------------------------------------
-- Control Register
-----------------------------------------------------------------------------
-- Register accessible on the JTAG interface only
Control_Register : process (UPDATE, Config_Reset)
begin
if Config_Reset = '1' then
tx_buffered <= '0';
elsif UPDATE'event and UPDATE = '1' then
if command = UART_WRITE_CONTROL and data_cmd = '1' then
tx_buffered <= tdi_shifter(0);
end if;
end if;
end process Control_Register;
Tx_Buffered_DFF: process (Clk)
begin -- process Tx_Buffered_DFF
if Clk'event and Clk = '1' then
tx_buffered_2 <= tx_buffered_1;
tx_buffered_1 <= tx_buffered;
end if;
end process Tx_Buffered_DFF;
Execute_UART_Command : process (UPDATE, data_cmd)
begin -- process Execute_UART_Command
if data_cmd = '0' then
execute <= '0';
elsif UPDATE'event and UPDATE = '1' then
if (command = UART_READ_BYTE) or
(command = UART_WRITE_BYTE) then
execute <= '1';
else
execute <= '0';
end if;
end if;
end process Execute_UART_Command;
Execute_FIFO_Command : process (Clk)
begin -- process Execute_FIFO_Command
if Clk'event and Clk = '1' then
fifo_Write <= '0';
fifo_Read <= '0';
if (execute_3 = '0') and (execute_2 = '1') then
if (command = UART_WRITE_BYTE) then
fifo_Write <= '1';
end if;
if (command = UART_READ_BYTE) then
fifo_Read <= '1';
end if;
end if;
execute_3 <= execute_2;
execute_2 <= execute_1;
execute_1 <= execute;
end if;
end process Execute_FIFO_Command;
-- Since only one bit can change in the status register at time
-- we don't need to synchronize them with the DRCK clock
status_reg(7) <= fifo_Data_Present;
status_reg(6) <= tx_Buffer_Full_I;
status_reg(5) <= not rx_Data_Present_I;
status_reg(4) <= rx_Buffer_Full_I;
status_reg(3) <= '0'; -- FSL0_S_Exists;
status_reg(2) <= '0'; -- FSL0_M_Full;
status_reg(1) <= '0'; -- FSL_Read_UnderRun;
status_reg(0) <= '0'; -- FSL_Write_OverRun;
-- Read UART registers
TDO_Register : process (DRCK, Config_Reset) is
begin -- process TDO_Register
if Config_Reset = '1' then
tdo_reg <= (others => '0');
elsif DRCK'event and DRCK = '1' then -- rising clock edge
if (CAPTURE = '1') then
case Command is
when UART_READ_STATUS =>
tdo_reg <= (others => '0');
tdo_reg(tdo_reg'right-status_reg'length+1 to tdo_reg'right) <= status_reg;
when others =>
tdo_reg <= fifo_DOut;
end case;
elsif SHIFT = '1' then
tdo_reg <= '0' & tdo_reg(tdo_reg'left to tdo_reg'right-1);
end if;
end if;
end process TDO_Register;
uart_TDO <= tdo_reg(tdo_reg'right);
-----------------------------------------------------------------------------
-- TDI Register
-----------------------------------------------------------------------------
TDI_Register : process (DRCK, Config_Reset) is
begin -- process TDI_Register
if Config_Reset = '1' then
fifo_Din <= (others => '0');
elsif DRCK'event and DRCK = '1' then -- rising clock edge
if shifting_Data = '1' then
fifo_Din(fifo_Din'left+1 to fifo_Din'right) <=
fifo_Din(fifo_Din'left to fifo_Din'right-1);
fifo_Din(0) <= TDI;
end if;
end if;
end process TDI_Register;
---------------------------------------------------------------------------
-- FIFO
---------------------------------------------------------------------------
RX_FIFO_I : SRL_FIFO
generic map (
C_DATA_BITS => C_UART_WIDTH, -- [natural]
C_DEPTH => 16) -- [natural]
port map (
Clk => Clk, -- [in std_logic]
Reset => Reset_RX_FIFO, -- [in std_logic]
FIFO_Write => fifo_Write, -- [in std_logic]
Data_In => fifo_Din(0 to C_UART_WIDTH-1), -- [in std_logic_vector(0 to C_DATA_BITS-1)]
FIFO_Read => Read_RX_FIFO, -- [in std_logic]
Data_Out => RX_Data, -- [out std_logic_vector(0 to C_DATA_BITS-1)]
FIFO_Full => rx_Buffer_Full_I, -- [out std_logic]
Data_Exists => rx_Data_Present_I); -- [out std_logic]
RX_Data_Present <= rx_Data_Present_I;
RX_Buffer_Full <= rx_Buffer_Full_I;
-- Discard transmit data until XMD enables buffered mode.
tx_fifo_wen <= Write_TX_FIFO and tx_buffered_2;
TX_FIFO_I : SRL_FIFO
generic map (
C_DATA_BITS => C_UART_WIDTH, -- [natural]
C_DEPTH => 16) -- [natural]
port map (
Clk => Clk, -- [in std_logic]
Reset => Reset_TX_FIFO, -- [in std_logic]
FIFO_Write => tx_fifo_wen, -- [in std_logic]
Data_In => TX_Data, -- [in std_logic_vector(0 to C_DATA_BITS-1)]
FIFO_Read => fifo_Read, -- [in std_logic]
Data_Out => fifo_DOut, -- [out std_logic_vector(0 to C_DATA_BITS-1)]
FIFO_Full => TX_Buffer_Full_I, -- [out std_logic]
Data_Exists => fifo_Data_Present); -- [out std_logic]
TX_Buffer_Full <= TX_Buffer_Full_I;
TX_Buffer_Empty <= not fifo_Data_Present;
end generate Use_UART;
No_UART : if (C_USE_UART = 0) generate
begin
ext_BRK_i <= '0';
uart_TDO <= '0';
RX_Data <= (others => '0');
RX_Data_Present <= '0';
RX_BUFFER_FULL <= '0';
TX_Buffer_Full <= '0';
TX_Buffer_Empty <= '1';
end generate No_UART;
-----------------------------------------------------------------------------
-- Bus Master Debug Memory Access section
-----------------------------------------------------------------------------
Use_Dbg_Mem_Access : if (C_DBG_MEM_ACCESS = 1) generate
signal input : std_logic_vector(0 to C_M_AXI_DATA_WIDTH-1);
signal output : std_logic_vector(0 to C_M_AXI_DATA_WIDTH-1);
signal status : std_logic_vector(0 to 7);
signal execute : std_logic := '0';
signal execute_1 : std_logic := '0';
signal execute_2 : std_logic := '0';
signal execute_3 : std_logic := '0';
signal rd_wr_len : std_logic_vector(0 to 4) := (others => '0');
signal rd_wr_size : std_logic_vector(0 to 1) := (others => '0');
signal rd_wr_excl : std_logic := '0';
attribute ASYNC_REG : string;
attribute ASYNC_REG of execute_1 : signal is "TRUE";
attribute ASYNC_REG of execute_2 : signal is "TRUE";
begin
-----------------------------------------------------------------------------
-- Control Register
-----------------------------------------------------------------------------
Control_Register : process (UPDATE, Config_Reset)
begin
if Config_Reset = '1' then
rd_wr_excl <= '0'; -- no exclusive
rd_wr_size <= "10"; -- word size
rd_wr_len <= (others => '0'); -- single word burst
elsif UPDATE'event and UPDATE = '1' then
if command = BUSM_WRITE_CONTROL and data_cmd = '1' then
rd_wr_excl <= tdi_shifter(0);
rd_wr_size <= tdi_shifter(1 to 2);
rd_wr_len <= tdi_shifter(3 to 7);
end if;
end if;
end process Control_Register;
Master_rd_len <= rd_wr_len;
Master_wr_len <= rd_wr_len;
Master_rd_size <= rd_wr_size;
Master_wr_size <= rd_wr_size;
Master_rd_excl <= rd_wr_excl;
Master_wr_excl <= rd_wr_excl;
-----------------------------------------------------------------------------
-- Command Registers
-----------------------------------------------------------------------------
Execute_Bus_Command : process (UPDATE, data_cmd)
begin -- process Execute_Bus_Command
if data_cmd = '0' then
execute <= '0';
elsif UPDATE'event and UPDATE = '1' then
if (command = BUSM_WRITE_COMMAND) or
(command = BUSM_READ_DATA) or
(command = BUSM_WRITE_DATA) then
execute <= '1';
else
execute <= '0';
end if;
end if;
end process Execute_Bus_Command;
Execute_Data_Command : process (M_AXI_ACLK)
begin -- process Execute_Data_Command
if M_AXI_ACLK'event and M_AXI_ACLK = '1' then
if M_AXI_ARESETn = '0' then
execute_3 <= '0';
execute_2 <= '0';
execute_1 <= '0';
Master_data_wr <= '0';
Master_data_rd <= '0';
Master_rd_start <= '0';
Master_wr_start <= '0';
master_overrun <= '0';
else
Master_data_wr <= '0';
Master_data_rd <= '0';
Master_rd_start <= '0';
Master_wr_start <= '0';
if (execute_3 = '0') and (execute_2 = '1') then
if (Master_rd_idle = '1') and (Master_wr_idle = '1') then
if (command = BUSM_WRITE_DATA) then
Master_data_wr <= '1';
end if;
if (command = BUSM_READ_DATA) then
Master_data_rd <= '1';
end if;
if (command = BUSM_WRITE_COMMAND) then
Master_rd_start <= Master_data_empty;
Master_wr_start <= not Master_data_empty;
end if;
master_overrun <= '0';
else
master_overrun <= '1';
end if;
end if;
execute_3 <= execute_2;
execute_2 <= execute_1;
execute_1 <= execute;
end if;
end if;
end process Execute_Data_Command;
master_error <= '1' when Master_rd_resp /= "00" or Master_wr_resp /= "00" else '0';
-----------------------------------------------------------------------------
-- Status Register and Data Read Register
-----------------------------------------------------------------------------
-- We don't need to synchronize status with DRCK clock
status(7) <= '0';
status(6) <= '0';
status(4 to 5) <= Master_rd_resp;
status(2 to 3) <= Master_wr_resp;
status(1) <= Master_rd_idle;
status(0) <= Master_wr_idle;
Output_Register : process (DRCK, Config_Reset) is
begin -- process Output_Register
if Config_Reset = '1' then
output <= (others => '0');
elsif DRCK'event and DRCK = '1' then -- rising clock edge
if (CAPTURE = '1') then
case Command is
when BUSM_READ_STATUS =>
output <= (others => '0');
output(output'right-status'length+1 to output'right) <= status;
when others =>
output <= Master_data_out;
end case;
elsif SHIFT = '1' then
output <= '0' & output(output'left to output'right-1);
end if;
end if;
end process Output_Register;
master_TDO <= output(output'right);
-----------------------------------------------------------------------------
-- Write Data and Read/Write Address Register
-----------------------------------------------------------------------------
Input_Register : process (DRCK, Config_Reset) is
begin -- process In_Register
if Config_Reset = '1' then
input <= (others => '0');
elsif DRCK'event and DRCK = '1' then -- rising clock edge
if shifting_Data = '1' then
input(input'left+1 to input'right) <= input(input'left to input'right-1);
input(0) <= TDI;
end if;
end if;
end process Input_Register;
Master_rd_addr <= input;
Master_wr_addr <= input;
Master_data_in <= input;
end generate Use_Dbg_Mem_Access;
No_Dbg_Mem_Access : if (C_DBG_MEM_ACCESS = 0) generate
begin
master_TDO <= '0';
master_overrun <= '0';
master_error <= '0';
Master_rd_start <= '0';
Master_rd_addr <= (others => '0');
Master_rd_len <= (others => '0');
Master_rd_size <= (others => '0');
Master_rd_excl <= '0';
Master_wr_start <= '0';
Master_wr_addr <= (others => '0');
Master_wr_len <= (others => '0');
Master_wr_size <= (others => '0');
Master_wr_excl <= '0';
Master_data_rd <= '0';
Master_data_wr <= '0';
Master_data_in <= (others => '0');
end generate No_Dbg_Mem_Access;
-----------------------------------------------------------------------------
-- AXI Slave Debug Register Access section
-----------------------------------------------------------------------------
Use_Dbg_Reg_Access : if (C_DBG_REG_ACCESS = 1) generate
signal access_lock : std_logic := '0';
signal access_lock_cmd_rst : std_logic;
signal dbgreg_access_lock_1 : std_logic := '0';
signal force_lock : std_logic := '0';
signal force_lock_cmd_rst : std_logic;
signal status_reg : std_logic_vector(0 to 1);
signal tdo_reg : std_logic_vector(0 to 1) := (others => '0');
begin
-----------------------------------------------------------------------------
-- Handle force lock command: first set it on update and then remove after
-- it has been detected in the other clock region
-----------------------------------------------------------------------------
force_lock_cmd_rst <= Config_Reset or dbgreg_unlocked;
Force_Lock_Command_Handle : process (UPDATE, force_lock_cmd_rst)
begin -- process Force_Lock_Command_Handle
if force_lock_cmd_rst = '1' then
force_lock <= '0';
elsif UPDATE'event and UPDATE = '1' then
if command = AXIS_WRITE_COMMAND and data_cmd = '1' then
force_lock <= tdi_shifter(0);
end if;
end if;
end process Force_Lock_Command_Handle;
JTAG_Force_Lock <= force_lock;
-----------------------------------------------------------------------------
-- Handle normal lock command: set it on update if not locked by other clock
-- region and remove if force lock by other clock region
-----------------------------------------------------------------------------
access_lock_cmd_rst <= Config_Reset or DbgReg_Force_Lock;
Access_Lock_Command_Handle : process (UPDATE, access_lock_cmd_rst)
begin -- process Access_Lock_Command_Handle
if access_lock_cmd_rst = '1' then
access_lock <= '0';
elsif UPDATE'event and UPDATE = '1' then
if command = AXIS_WRITE_COMMAND and data_cmd = '1' then
access_lock <= tdi_shifter(1) and not dbgreg_access_lock_1;
end if;
end if;
end process Access_Lock_Command_Handle;
Sync_Access_Lock : process (DRCK, Config_Reset) is
begin -- process Sync_Access_Lock
if Config_Reset = '1' then
dbgreg_access_lock_1 <= '0';
elsif DRCK'event and DRCK = '1' then -- rising clock edge
dbgreg_access_lock_1 <= DbgReg_Access_Lock;
end if;
end process Sync_Access_Lock;
JTAG_Access_Lock <= access_lock;
-----------------------------------------------------------------------------
-- Read AXI Slave status register
-----------------------------------------------------------------------------
status_reg(1) <= access_lock;
status_reg(0) <= dbgreg_access_lock_1;
TDO_Register : process (DRCK, Config_Reset) is
begin -- process TDO_Register
if Config_Reset = '1' then
tdo_reg <= (others => '0');
elsif DRCK'event and DRCK = '1' then -- rising clock edge
if CAPTURE = '1' then
-- AXIS_READ_STATUS
tdo_reg <= status_reg;
elsif SHIFT = '1' then
tdo_reg <= '0' & tdo_reg(tdo_reg'left to tdo_reg'right-1);
end if;
end if;
end process TDO_Register;
axis_TDO <= tdo_reg(tdo_reg'right);
JTAG_Clear_Overrun <= clear_overrun;
end generate Use_Dbg_Reg_Access;
No_Dbg_Reg_Acess : if (C_DBG_REG_ACCESS = 0) generate
begin
axis_TDO <= '0';
JTAG_Access_Lock <= '0';
JTAG_Force_Lock <= '0';
JTAG_Clear_Overrun <= '0';
end generate No_Dbg_Reg_Acess;
-----------------------------------------------------------------------------
-- Cross trigger section
-----------------------------------------------------------------------------
Use_Cross_Trigger : if (C_USE_CROSS_TRIGGER = 1) generate
constant C_NUM_CT : integer := C_NUM_DBG_CT + C_NUM_EXT_CT;
type dbg_in_all_type is array(0 to C_EN_WIDTH - 1) of std_logic_vector(0 to C_NUM_DBG_CT - 1);
type in_all_type is array(0 to C_EN_WIDTH - 1) of std_logic_vector(0 to C_NUM_CT - 1);
type dbg_out_type is array(0 to C_NUM_DBG_CT - 1) of std_logic_vector(0 to 3);
type dbg_out_all_type is array(0 to C_EN_WIDTH - 1) of dbg_out_type;
type ext_out_type is array(0 to C_NUM_EXT_CT - 1) of std_logic_vector(0 to 3);
constant C_DBG_IN_CTRL : std_logic_vector(0 to C_NUM_DBG_CT - 1) := (0 to C_NUM_EXT_CT - 1 => '1', others => '0');
constant C_DBG_OUT_CTRL : dbg_out_type := ("1001", "1010", "1011", "1100", "1101", "1101", "1101", "1101");
constant C_EXT_IN_CTRL : std_logic_vector(0 to C_NUM_EXT_CT - 1) := (others => '1');
constant C_EXT_OUT_CTRL : ext_out_type := ("0001", "0010", "0011", "0100");
signal dbg_trig_in_i : dbg_trig_type;
signal dbg_trig_Ack_Out_i : dbg_trig_type;
signal in_andor_ctrl : std_logic := '0';
signal in_ctrl : dbg_in_all_type := (others => C_DBG_IN_CTRL);
signal out_ctrl : dbg_out_all_type := (others => C_DBG_OUT_CTRL);
signal ext_in_ctrl : std_logic_vector(0 to C_NUM_EXT_CT - 1) := C_EXT_IN_CTRL;
signal ext_out_ctrl : ext_out_type := C_EXT_OUT_CTRL;
signal status_reg : std_logic_vector(0 to C_NUM_CT * 2 - 1) := (others => '0');
signal tdo_reg : std_logic_vector(0 to C_NUM_CT * 2 - 1) := (others => '0');
begin
-----------------------------------------------------------------------------
-- Assign trigger outputs
-----------------------------------------------------------------------------
Assign_Outputs: process (in_ctrl, in_andor_ctrl, ext_in_ctrl,
out_ctrl, ext_out_ctrl, dbg_trig_in_i, Ext_Trig_In,
dbg_trig_ack_out_i, Ext_Trig_Ack_Out) is
variable in_value_or : dbg_in_all_type;
variable in_value_and : dbg_in_all_type;
variable in_value : in_all_type;
variable in_value_ext_or : std_logic_vector(0 to C_NUM_DBG_CT - 1);
variable in_value_ext_and : std_logic_vector(0 to C_NUM_DBG_CT - 1);
variable in_value_ext : std_logic_vector(0 to C_NUM_CT - 1);
variable out_value : std_logic_vector(0 to 15);
variable out_ack_value : std_logic_vector(0 to 15);
variable dbg_ack_value : dbg_in_all_type;
variable ext_ack_value : std_logic_vector(0 to C_NUM_EXT_CT - 1);
variable index : integer range 0 to 15;
begin -- process Assign_Outputs
-- Determine in_value per processor from inputs and input select control registers
for N in 0 to C_EN_WIDTH - 1 loop
for K in 0 to C_NUM_DBG_CT - 1 loop
in_value_or(N)(K) := '0';
in_value_and(N)(K) := '1';
for I in 0 to C_EN_WIDTH - 1 loop
if N /= I then -- exclude own processor input
in_value_or(N)(K) := in_value_or(N)(K) or (dbg_trig_in_i(I)(K) and in_ctrl(I)(K));
in_value_and(N)(K) := in_value_and(N)(K) and (dbg_trig_in_i(I)(K) and in_ctrl(I)(K));
end if;
end loop;
end loop;
if in_andor_ctrl = '1' then
in_value(N)(0 to C_NUM_DBG_CT - 1) := in_value_and(N);
else
in_value(N)(0 to C_NUM_DBG_CT - 1) := in_value_or(N);
end if;
for K in 0 to C_NUM_EXT_CT - 1 loop
in_value(N)(K + C_NUM_DBG_CT) := Ext_Trig_In(K) and ext_in_ctrl(K);
end loop;
end loop;
-- Determine in_value_ext from inputs and input select control registers
for K in 0 to C_NUM_DBG_CT - 1 loop
in_value_ext_or(K) := '0';
in_value_ext_and(K) := '1';
for I in 0 to C_EN_WIDTH - 1 loop
in_value_ext_or(K) := in_value_ext_or(K) or (dbg_trig_in_i(I)(K) and in_ctrl(I)(K));
in_value_ext_and(K) := in_value_ext_and(K) and (dbg_trig_in_i(I)(K) and in_ctrl(I)(K));
end loop;
if in_andor_ctrl = '1' then
in_value_ext(0 to C_NUM_DBG_CT - 1) := in_value_ext_and;
else
in_value_ext(0 to C_NUM_DBG_CT - 1) := in_value_ext_or;
end if;
for K in 0 to C_NUM_EXT_CT - 1 loop
in_value_ext(K + C_NUM_DBG_CT) := Ext_Trig_In(K) and ext_in_ctrl(K);
end loop;
end loop;
-- Assign outputs from out_value based on out_ctrl control register
dbg_trig_out_i <= (others => (others => '0'));
for N in 0 to C_EN_WIDTH - 1 loop
out_value := '1' & in_value(N) & "000"; -- 0000: constant 1, N=K: constant 0
for K in 0 to C_NUM_DBG_CT - 1 loop
index := to_integer(unsigned(out_ctrl(N)(K)));
dbg_trig_out_i(N)(K) <= out_value(index);
end loop;
end loop;
-- Assign external outputs from in_value based on ext_out_ctrl control register
ext_trig_out_i <= (others => '0');
out_value := '1' & in_value_ext & "000"; -- 0000: constant 1, 1101: constant 0
for K in 0 to C_NUM_EXT_CT - 1 loop
index := to_integer(unsigned(ext_out_ctrl(K)));
ext_trig_out_i(K) <= out_value(index);
end loop;
-- Assign dbg_trig_ack_in_i from dbg_ack_value and Ext_Trig_Ack_Out
-- Create combined acknowledge from all processors and external trig
dbg_ack_value := (others => (others => '0'));
dbg_trig_ack_in_i <= (others => (others => '0'));
for K in 0 to C_NUM_DBG_CT - 1 loop
for N in 0 to C_EN_WIDTH - 1 loop
index := to_integer(unsigned(out_ctrl(N)(K)));
out_ack_value := '0' & dbg_trig_ack_out_i(N) & Ext_Trig_Ack_Out & "000";
dbg_ack_value(N)(K) := dbg_ack_value(N)(K) or out_ack_value(index);
end loop;
end loop;
for K in 0 to C_NUM_DBG_CT - 1 loop
for N in 0 to C_EN_WIDTH - 1 loop
dbg_trig_ack_in_i(N)(K) <= dbg_ack_value(N)(K) and in_ctrl(N)(K);
end loop;
end loop;
-- Assign ext_trig_ack_in_i from dbg_ack_value and Ext_Trig_Ack_Out
-- Create combined acknowledge from all processors and external trig
ext_ack_value := (others => '0');
ext_trig_ack_in_i <= (others => '0');
for K in 0 to C_NUM_EXT_CT - 1 loop
index := to_integer(unsigned(ext_out_ctrl(K)));
for N in 0 to C_EN_WIDTH - 1 loop
out_ack_value := '0' & dbg_trig_ack_out_i(N) & Ext_Trig_Ack_Out & "000";
ext_ack_value(K) := ext_ack_value(K) or out_ack_value(index);
end loop;
end loop;
for K in 0 to C_NUM_EXT_CT - 1 loop
ext_trig_ack_in_i(K) <= ext_ack_value(K) and ext_in_ctrl(K);
end loop;
end process Assign_Outputs;
-----------------------------------------------------------------------------
-- Control Registers:
-- 4 output select + 8 input mask + and/or + 3 (index 0-7) = 16
-- 4 output select + 4 input mask + 2 (index 0-3) = 10
-----------------------------------------------------------------------------
Control_Registers : process (UPDATE, Config_Reset)
variable dbg_index : std_logic_vector(0 to 2);
variable ext_index : std_logic_vector(0 to 1);
variable K : integer;
begin
if Config_Reset = '1' then
in_andor_ctrl <= '0';
in_ctrl <= (others => C_DBG_IN_CTRL);
out_ctrl <= (others => C_DBG_OUT_CTRL);
ext_in_ctrl <= C_EXT_IN_CTRL;
ext_out_ctrl <= C_EXT_OUT_CTRL;
elsif UPDATE'event and UPDATE = '1' then
if data_cmd = '1' then
if command = CT_WRITE_CTRL and data_cmd = '1' then
dbg_index := tdi_shifter(4 + C_NUM_DBG_CT + 1 to 4 + C_NUM_DBG_CT + 1 + 2);
K := to_integer(unsigned(dbg_index));
for I in 0 to C_EN_WIDTH - 1 loop
if mb_debug_enabled_i(I) = '1' then
out_ctrl(I)(K) <= tdi_shifter(0 to 3);
in_ctrl(I) <= tdi_shifter(4 to 4 + C_NUM_DBG_CT - 1);
end if;
end loop;
in_andor_ctrl <= tdi_shifter(4 + C_NUM_DBG_CT);
end if;
if command = CT_WRITE_EXT_CTRL and data_cmd = '1' then
ext_index := tdi_shifter(4 + C_NUM_EXT_CT to 4 + C_NUM_EXT_CT + 1);
K := to_integer(unsigned(ext_index));
ext_out_ctrl(K) <= tdi_shifter(0 to 3);
ext_in_ctrl <= tdi_shifter(4 to 4 + C_NUM_EXT_CT - 1);
end if;
end if;
end if;
end process Control_Registers;
-----------------------------------------------------------------------------
-- Status Register
-----------------------------------------------------------------------------
Assign_Status: process (dbg_trig_out_i, ext_trig_out_i, dbg_trig_in_i, Ext_Trig_In, mb_debug_enabled_i) is
begin -- process Assign_Status
status_reg <= (others => '0');
for I in 0 to C_EN_WIDTH - 1 loop
if mb_debug_enabled_i(I) = '1' then
status_reg(0 to C_NUM_DBG_CT * 2 - 1) <= dbg_trig_out_i(I) & dbg_trig_in_i(I);
end if;
end loop;
status_reg(C_NUM_DBG_CT * 2 to C_NUM_CT * 2 - 1) <= ext_trig_out_i & Ext_Trig_In;
end process Assign_Status;
TDO_Register : process (DRCK, Config_Reset) is
begin -- process TDO_Register
if Config_Reset = '1' then
tdo_reg <= (others => '0');
elsif DRCK'event and DRCK = '1' then -- rising clock edge
if (CAPTURE = '1') then
-- CT_READ_STATUS
tdo_reg <= status_reg;
elsif SHIFT = '1' then
tdo_reg <= '0' & tdo_reg(tdo_reg'left to tdo_reg'right-1);
end if;
end if;
end process TDO_Register;
ct_TDO <= tdo_reg(tdo_reg'right);
dbg_trig_in_i(0) <= Dbg_Trig_In_0;
dbg_trig_in_i(1) <= Dbg_Trig_In_1;
dbg_trig_in_i(2) <= Dbg_Trig_In_2;
dbg_trig_in_i(3) <= Dbg_Trig_In_3;
dbg_trig_in_i(4) <= Dbg_Trig_In_4;
dbg_trig_in_i(5) <= Dbg_Trig_In_5;
dbg_trig_in_i(6) <= Dbg_Trig_In_6;
dbg_trig_in_i(7) <= Dbg_Trig_In_7;
dbg_trig_in_i(8) <= Dbg_Trig_In_8;
dbg_trig_in_i(9) <= Dbg_Trig_In_9;
dbg_trig_in_i(10) <= Dbg_Trig_In_10;
dbg_trig_in_i(11) <= Dbg_Trig_In_11;
dbg_trig_in_i(12) <= Dbg_Trig_In_12;
dbg_trig_in_i(13) <= Dbg_Trig_In_13;
dbg_trig_in_i(14) <= Dbg_Trig_In_14;
dbg_trig_in_i(15) <= Dbg_Trig_In_15;
dbg_trig_in_i(16) <= Dbg_Trig_In_16;
dbg_trig_in_i(17) <= Dbg_Trig_In_17;
dbg_trig_in_i(18) <= Dbg_Trig_In_18;
dbg_trig_in_i(19) <= Dbg_Trig_In_19;
dbg_trig_in_i(20) <= Dbg_Trig_In_20;
dbg_trig_in_i(21) <= Dbg_Trig_In_21;
dbg_trig_in_i(22) <= Dbg_Trig_In_22;
dbg_trig_in_i(23) <= Dbg_Trig_In_23;
dbg_trig_in_i(24) <= Dbg_Trig_In_24;
dbg_trig_in_i(25) <= Dbg_Trig_In_25;
dbg_trig_in_i(26) <= Dbg_Trig_In_26;
dbg_trig_in_i(27) <= Dbg_Trig_In_27;
dbg_trig_in_i(28) <= Dbg_Trig_In_28;
dbg_trig_in_i(29) <= Dbg_Trig_In_29;
dbg_trig_in_i(30) <= Dbg_Trig_In_30;
dbg_trig_in_i(31) <= Dbg_Trig_In_31;
dbg_trig_ack_out_i(0) <= Dbg_Trig_Ack_Out_0;
dbg_trig_ack_out_i(1) <= Dbg_Trig_Ack_Out_1;
dbg_trig_ack_out_i(2) <= Dbg_Trig_Ack_Out_2;
dbg_trig_ack_out_i(3) <= Dbg_Trig_Ack_Out_3;
dbg_trig_ack_out_i(4) <= Dbg_Trig_Ack_Out_4;
dbg_trig_ack_out_i(5) <= Dbg_Trig_Ack_Out_5;
dbg_trig_ack_out_i(6) <= Dbg_Trig_Ack_Out_6;
dbg_trig_ack_out_i(7) <= Dbg_Trig_Ack_Out_7;
dbg_trig_ack_out_i(8) <= Dbg_Trig_Ack_Out_8;
dbg_trig_ack_out_i(9) <= Dbg_Trig_Ack_Out_9;
dbg_trig_ack_out_i(10) <= Dbg_Trig_Ack_Out_10;
dbg_trig_ack_out_i(11) <= Dbg_Trig_Ack_Out_11;
dbg_trig_ack_out_i(12) <= Dbg_Trig_Ack_Out_12;
dbg_trig_ack_out_i(13) <= Dbg_Trig_Ack_Out_13;
dbg_trig_ack_out_i(14) <= Dbg_Trig_Ack_Out_14;
dbg_trig_ack_out_i(15) <= Dbg_Trig_Ack_Out_15;
dbg_trig_ack_out_i(16) <= Dbg_Trig_Ack_Out_16;
dbg_trig_ack_out_i(17) <= Dbg_Trig_Ack_Out_17;
dbg_trig_ack_out_i(18) <= Dbg_Trig_Ack_Out_18;
dbg_trig_ack_out_i(19) <= Dbg_Trig_Ack_Out_19;
dbg_trig_ack_out_i(20) <= Dbg_Trig_Ack_Out_20;
dbg_trig_ack_out_i(21) <= Dbg_Trig_Ack_Out_21;
dbg_trig_ack_out_i(22) <= Dbg_Trig_Ack_Out_22;
dbg_trig_ack_out_i(23) <= Dbg_Trig_Ack_Out_23;
dbg_trig_ack_out_i(24) <= Dbg_Trig_Ack_Out_24;
dbg_trig_ack_out_i(25) <= Dbg_Trig_Ack_Out_25;
dbg_trig_ack_out_i(26) <= Dbg_Trig_Ack_Out_26;
dbg_trig_ack_out_i(27) <= Dbg_Trig_Ack_Out_27;
dbg_trig_ack_out_i(28) <= Dbg_Trig_Ack_Out_28;
dbg_trig_ack_out_i(29) <= Dbg_Trig_Ack_Out_29;
dbg_trig_ack_out_i(30) <= Dbg_Trig_Ack_Out_30;
dbg_trig_ack_out_i(31) <= Dbg_Trig_Ack_Out_31;
end generate Use_Cross_Trigger;
No_Cross_Trigger : if (C_USE_CROSS_TRIGGER = 0) generate
begin
dbg_trig_ack_in_i <= (others => (others => '0'));
dbg_trig_out_i <= (others => (others => '0'));
ext_trig_ack_in_i <= (others => '0');
ext_trig_out_i <= (others => '0');
ct_TDO <= '0';
end generate No_Cross_Trigger;
Dbg_Trig_Ack_In_0 <= dbg_trig_ack_in_i(0);
Dbg_Trig_Ack_In_1 <= dbg_trig_ack_in_i(1);
Dbg_Trig_Ack_In_2 <= dbg_trig_ack_in_i(2);
Dbg_Trig_Ack_In_3 <= dbg_trig_ack_in_i(3);
Dbg_Trig_Ack_In_4 <= dbg_trig_ack_in_i(4);
Dbg_Trig_Ack_In_5 <= dbg_trig_ack_in_i(5);
Dbg_Trig_Ack_In_6 <= dbg_trig_ack_in_i(6);
Dbg_Trig_Ack_In_7 <= dbg_trig_ack_in_i(7);
Dbg_Trig_Ack_In_8 <= dbg_trig_ack_in_i(8);
Dbg_Trig_Ack_In_9 <= dbg_trig_ack_in_i(9);
Dbg_Trig_Ack_In_10 <= dbg_trig_ack_in_i(10);
Dbg_Trig_Ack_In_11 <= dbg_trig_ack_in_i(11);
Dbg_Trig_Ack_In_12 <= dbg_trig_ack_in_i(12);
Dbg_Trig_Ack_In_13 <= dbg_trig_ack_in_i(13);
Dbg_Trig_Ack_In_14 <= dbg_trig_ack_in_i(14);
Dbg_Trig_Ack_In_15 <= dbg_trig_ack_in_i(15);
Dbg_Trig_Ack_In_16 <= dbg_trig_ack_in_i(16);
Dbg_Trig_Ack_In_17 <= dbg_trig_ack_in_i(17);
Dbg_Trig_Ack_In_18 <= dbg_trig_ack_in_i(18);
Dbg_Trig_Ack_In_19 <= dbg_trig_ack_in_i(19);
Dbg_Trig_Ack_In_20 <= dbg_trig_ack_in_i(20);
Dbg_Trig_Ack_In_21 <= dbg_trig_ack_in_i(21);
Dbg_Trig_Ack_In_22 <= dbg_trig_ack_in_i(22);
Dbg_Trig_Ack_In_23 <= dbg_trig_ack_in_i(23);
Dbg_Trig_Ack_In_24 <= dbg_trig_ack_in_i(24);
Dbg_Trig_Ack_In_25 <= dbg_trig_ack_in_i(25);
Dbg_Trig_Ack_In_26 <= dbg_trig_ack_in_i(26);
Dbg_Trig_Ack_In_27 <= dbg_trig_ack_in_i(27);
Dbg_Trig_Ack_In_28 <= dbg_trig_ack_in_i(28);
Dbg_Trig_Ack_In_29 <= dbg_trig_ack_in_i(29);
Dbg_Trig_Ack_In_30 <= dbg_trig_ack_in_i(30);
Dbg_Trig_Ack_In_31 <= dbg_trig_ack_in_i(31);
Dbg_Trig_Out_0 <= dbg_trig_out_i(0);
Dbg_Trig_Out_1 <= dbg_trig_out_i(1);
Dbg_Trig_Out_2 <= dbg_trig_out_i(2);
Dbg_Trig_Out_3 <= dbg_trig_out_i(3);
Dbg_Trig_Out_4 <= dbg_trig_out_i(4);
Dbg_Trig_Out_5 <= dbg_trig_out_i(5);
Dbg_Trig_Out_6 <= dbg_trig_out_i(6);
Dbg_Trig_Out_7 <= dbg_trig_out_i(7);
Dbg_Trig_Out_8 <= dbg_trig_out_i(8);
Dbg_Trig_Out_9 <= dbg_trig_out_i(9);
Dbg_Trig_Out_10 <= dbg_trig_out_i(10);
Dbg_Trig_Out_11 <= dbg_trig_out_i(11);
Dbg_Trig_Out_12 <= dbg_trig_out_i(12);
Dbg_Trig_Out_13 <= dbg_trig_out_i(13);
Dbg_Trig_Out_14 <= dbg_trig_out_i(14);
Dbg_Trig_Out_15 <= dbg_trig_out_i(15);
Dbg_Trig_Out_16 <= dbg_trig_out_i(16);
Dbg_Trig_Out_17 <= dbg_trig_out_i(17);
Dbg_Trig_Out_18 <= dbg_trig_out_i(18);
Dbg_Trig_Out_19 <= dbg_trig_out_i(19);
Dbg_Trig_Out_20 <= dbg_trig_out_i(20);
Dbg_Trig_Out_21 <= dbg_trig_out_i(21);
Dbg_Trig_Out_22 <= dbg_trig_out_i(22);
Dbg_Trig_Out_23 <= dbg_trig_out_i(23);
Dbg_Trig_Out_24 <= dbg_trig_out_i(24);
Dbg_Trig_Out_25 <= dbg_trig_out_i(25);
Dbg_Trig_Out_26 <= dbg_trig_out_i(26);
Dbg_Trig_Out_27 <= dbg_trig_out_i(27);
Dbg_Trig_Out_28 <= dbg_trig_out_i(28);
Dbg_Trig_Out_29 <= dbg_trig_out_i(29);
Dbg_Trig_Out_30 <= dbg_trig_out_i(30);
Dbg_Trig_Out_31 <= dbg_trig_out_i(31);
Ext_Trig_Ack_In <= ext_trig_ack_in_i;
Ext_Trig_Out <= ext_trig_out_i;
end architecture IMP;
| apache-2.0 | c10bf954dfd7da51357be7a881164ec3 | 0.52122 | 3.274701 | false | true | false | false |
sandrosalvato94/System-Design-Project | src/polito/sdp2017/Tests/b14BCD.vhd | 1 | 874 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY b14BCD IS
PORT ( in_bin: IN STD_LOGIC_VECTOR(13 downto 0);
out_migl: OUT STD_LOGIC_VECTOR (3 downto 0);
out_cent: OUT STD_LOGIC_VECTOR (3 downto 0);
out_dec : OUT STD_LOGIC_VECTOR (3 downto 0);
out_unit: OUT STD_LOGIC_VECTOR (3 downto 0));
END b14BCD;
ARCHITECTURE behavior OF b14BCD IS
SIGNAL in_int, migl, cent, dec, unit: integer;
BEGIN
in_int<=TO_INTEGER(UNSIGNED(in_bin));
migl<=in_int/1000;
out_migl<=STD_LOGIC_VECTOR(TO_UNSIGNED((migl), 4));
cent<=(in_int-migl*1000)/100;
out_cent<=STD_LOGIC_VECTOR(TO_UNSIGNED((cent), 4));
dec<=(in_int-migl*1000-cent*100)/10;
out_dec<=STD_LOGIC_VECTOR(TO_UNSIGNED((dec), 4));
unit<=(in_int-migl*1000-cent*100-dec*10);
out_unit<=STD_LOGIC_VECTOR(TO_UNSIGNED((unit), 4));
END behavior; | lgpl-3.0 | a84f12ed4dfc8a53e46ea2527b5e9c4c | 0.654462 | 2.689231 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/family.vhd | 15 | 23,047 | -- $Header: /devl/xcs/repo/env/Databases/ip2/processor/hardware/proc_common/proc_common_v4_0/hdl/src/vhdl/family.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- family.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: family.vhd
--
-- Description:
-- This HDL file provides various functions for determining features (such
-- as BRAM types) in the various device families in Xilinx products.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- family.vhd
--
-------------------------------------------------------------------------------
-- Revision history
--
-- ??? ?????????? Initial version
-- jam 03/31/2003 added spartan3 to constants and derived function. Added
-- comments to try and explain how the function is used
-- jam 04/01/2003 removed VIRTEX from the derived list for BYZANTIUM,
-- VIRTEX2P, and SPARTAN3. This changes VIRTEX2 to be a
-- base family type, similar to X4K and VIRTEX
-- jam 04/02/2003 add VIRTEX back into the hierarchy of VIRTEX2P, BYZANTIUM
-- and SPARTAN3; add additional comments showing use in
-- VHDL
-- lss 03/24/2004 Added QVIRTEX2, QRVIRTEX2, VIRTEX4
-- flo 03/22/2005 Added SPARTAN3E
-- als 02/23/2006 Added VIRTEX5
-- flo 09/13/2006 Added SPARTAN3A and SPARTAN3A. This may allow
-- legacy designs to support spartan3a and spartan3an in
-- terms of BRAMs. For new work (and maintenence where
-- possible) this package, family, should be dropped in favor
-- of the package, family_support.
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
--------------------------------------------------------------------------------
-- @BEGIN_CHANGELOG EDK_H_SP1
-- Added spartan3e
-- @END_CHANGELOG
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
package family is
-- constant declarations
constant ANY : string := "any";
constant X4K : string := "x4k";
constant X4KE : string := "x4ke";
constant X4KL : string := "x4kl";
constant X4KEX : string := "x4kex";
constant X4KXL : string := "x4kxl";
constant X4KXV : string := "x4kxv";
constant X4KXLA : string := "x4kxla";
constant SPARTAN : string := "spartan";
constant SPARTANXL : string := "spartanxl";
constant SPARTAN2 : string := "spartan2";
constant SPARTAN2E : string := "spartan2e";
constant VIRTEX : string := "virtex";
constant VIRTEXE : string := "virtexe";
constant VIRTEX2 : string := "virtex2";
constant VIRTEX2P : string := "virtex2p";
constant BYZANTIUM : string := "byzantium";
constant SPARTAN3 : string := "spartan3";
constant QRVIRTEX2 : string := "qrvirtex2";
constant QVIRTEX2 : string := "qvirtex2";
constant VIRTEX4 : string := "virtex4";
constant VIRTEX5 : string := "virtex5";
constant SPARTAN3E : string := "spartan3e";
constant SPARTAN3A : string := "spartan3a";
constant SPARTAN3AN: string := "spartan3an";
-- function declarations
-- derived - provides a means to determine if a family specified in child is
-- the same as, or is a super set of, the family specified in
-- ancestor.
--
-- Typically, child is set to the generic specifying the family type
-- the user wishes to implement the design into (C_FAMILY), and the
-- designer hard codes ancestor to the family type supported by the
-- design. If the design supports multiple family types, then each
-- of those family types would need to be tested against C_FAMILY
-- using this function. An example for the VIRTEX2P hierarchy
-- is shown below:
--
-- VIRTEX2P_SPECIFIC_LOGIC_GEN:
-- if derived(C_FAMILY,VIRTEX2P)
-- generate
-- -- logic specific to Virtex2P family
-- end generate VIRTEX2P_SPECIFIC_LOGIC_GEN;
--
-- NON_VIRTEX2P_SPECIFIC_LOGIC_GEN:
-- if not derived(C_FAMILY,VIRTEX2P)
-- generate
--
-- VIRTEX2_SPECIFIC_LOGIC_GEN:
-- if derived(C_FAMILY,VIRTEX2)
-- generate
-- -- logic specific to Virtex2 family
-- end generate VIRTEX2_SPECIFIC_LOGIC_GEN;
--
-- NON_VIRTEX2_SPECIFIC_LOGIC_GEN
-- if not derived(C_FAMILY,VIRTEX2)
-- generate
--
-- VIRTEX_SPECIFIC_LOGIC_GEN:
-- if derived(C_FAMILY,VIRTEX)
-- generate
-- -- logic specific to Virtex family
-- end generate VIRTEX_SPECIFIC_LOGIC_GEN;
--
-- NON_VIRTEX_SPECIFIC_LOGIC_GEN;
-- if not derived(C_FAMILY,VIRTEX)
-- generate
--
-- ANY_FAMILY_TYPE_LOGIC_GEN:
-- if derived(C_FAMILY,ANY)
-- generate
-- -- logic not specific to any family
-- end generate ANY_FAMILY_TYPE_LOGIC_GEN;
--
-- end generate NON_VIRTEX_SPECIFIC_LOGIC_GEN;
--
-- end generate NON_VIRTEX2_SPECIFIC_LOGIC_GEN;
--
-- end generate NON_VIRTEX2P_SPECIFIC_LOGIC_GEN;
--
-- This function will return TRUE if the family type specified in
-- child is equal to, or a super set of, the family type specified in
-- ancestor, otherwise it returns FALSE.
--
-- The current super sets are defined by the following list, where
-- all family types listed to the right of an item are contained in
-- the super set of that item, for all lines containing that item.
--
-- ANY, X4K, SPARTAN, SPARTANXL
-- ANY, X4K, X4KE, X4KL
-- ANY, X4K, X4KEX, X4KXL, X4KXV, X4KXLA
-- ANY, VIRTEX, SPARTAN2, SPARTAN2E
-- ANY, VIRTEX, VIRTEXE
-- ANY, VIRTEX, VIRTEX2, BYZANTIUM
-- ANY, VIRTEX, VIRTEX2, VIRTEX2P
-- ANY, VIRTEX, VIRTEX2, SPARTAN3
--
-- For exampel, all other family types are contained in the super set
-- for ANY. Stated another way, if the designer specifies ANY
-- for the family type the design supports, then the function will
-- return TRUE for any family type the user wishes to implement the
-- design into.
--
-- if derived(C_FAMILY,ANY) generate ... end generate;
--
-- If the designer specifies VIRTEX2 as the family type supported by
-- the design, then the function will only return TRUE if the user
-- intends to implement the design in VIRTEX2, VIRTEX2P, BYZANTIUM,
-- or SPARTAN3.
--
-- if derived(C_FAMILY,VIRTEX2) generate
-- -- logic that uses VIRTEX2 BRAMs
-- end generate;
--
-- if not derived(C_FAMILY,VIRTEX2) generate
-- -- logic that uses non VIRTEX2 BRAMs
-- end generate;
--
-- Note:
-- The last three lines of the list above were modified from the
-- original to remove VIRTEX from those lines because, from our point
-- of view, VIRTEX2 is different enough from VIRTEX to conclude that
-- it should be its own base family type.
--
-- **************************************************************************
-- WARNING
-- **************************************************************************
-- DO NOT RELY ON THE DERIVED FUNCTION TO PROVIDE DIFFERENTIATION BETWEEN
-- FAMILY TYPES FOR ANYTHING OTHER THAN BRAMS
--
-- Use of the derived function assumes that the designer is not using
-- RLOCs (RLOC'd FIFO's from Coregen, etc.) and that the BRAMs in the
-- derived families are similar. If the designer is using specific
-- elements of a family type, they are responsible for ensuring that
-- those same elements are available in all family types supported by
-- their design, and that the elements function exactly the same in all
-- "similar" families.
--
-- **************************************************************************
--
function derived ( child, ancestor : string ) return boolean;
-- equalIgnoreCase - Returns TRUE if case insensitive string comparison
-- determines that str1 and str2 are equal, otherwise FALSE
function equalIgnoreCase( str1, str2 : string ) return boolean;
-- toLowerCaseChar - Returns the lower case form of char if char is an upper
-- case letter. Otherwise char is returned.
function toLowerCaseChar( char : character ) return character;
end family;
package body family is
-- True if architecture "child" is derived from, or equal to,
-- the architecture "ancestor".
-- ANY, X4K, SPARTAN, SPARTANXL
-- ANY, X4K, X4KE, X4KL
-- ANY, X4K, X4KEX, X4KXL, X4KXV, X4KXLA
-- ANY, VIRTEX, SPARTAN2, SPARTAN2E
-- ANY, VIRTEX, VIRTEXE
-- ANY, VIRTEX, VIRTEX2, BYZANTIUM
-- ANY, VIRTEX, VIRTEX2, VIRTEX2P
-- ANY, VIRTEX, VIRTEX2, SPARTAN3
function derived ( child, ancestor : string ) return boolean is
variable is_derived : boolean := FALSE;
begin
if equalIgnoreCase( child, VIRTEX ) then -- base family type
if ( equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEX2 ) then
if ( equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, QRVIRTEX2 ) then
if ( equalIgnoreCase(ancestor,QRVIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, QVIRTEX2 ) then
if ( equalIgnoreCase(ancestor,QVIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEX5 ) then
if ( equalIgnoreCase(ancestor,VIRTEX5) OR
equalIgnoreCase(ancestor,VIRTEX4) OR
equalIgnoreCase(ancestor,VIRTEX2P) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEX4 ) then
if ( equalIgnoreCase(ancestor,VIRTEX4) OR
equalIgnoreCase(ancestor,VIRTEX2P) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEX2P ) then
if ( equalIgnoreCase(ancestor,VIRTEX2P) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, BYZANTIUM ) then
if ( equalIgnoreCase(ancestor,BYZANTIUM) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEXE ) then
if ( equalIgnoreCase(ancestor,VIRTEXE) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN2 ) then
if ( equalIgnoreCase(ancestor,SPARTAN2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN2E ) then
if ( equalIgnoreCase(ancestor,SPARTAN2E) OR
equalIgnoreCase(ancestor,SPARTAN2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN3 ) then
if ( equalIgnoreCase(ancestor,SPARTAN3) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN3E ) then
if ( equalIgnoreCase(ancestor,SPARTAN3E) OR
equalIgnoreCase(ancestor,SPARTAN3) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN3A ) then
if ( equalIgnoreCase(ancestor,SPARTAN3A) OR
equalIgnoreCase(ancestor,SPARTAN3E) OR
equalIgnoreCase(ancestor,SPARTAN3) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN3AN ) then
if ( equalIgnoreCase(ancestor,SPARTAN3AN) OR
equalIgnoreCase(ancestor,SPARTAN3E) OR
equalIgnoreCase(ancestor,SPARTAN3) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4K ) then -- base family type
if ( equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KEX ) then
if ( equalIgnoreCase(ancestor,X4KEX) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KXL ) then
if ( equalIgnoreCase(ancestor,X4KXL) OR
equalIgnoreCase(ancestor,X4KEX) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KXV ) then
if ( equalIgnoreCase(ancestor,X4KXV) OR
equalIgnoreCase(ancestor,X4KXL) OR
equalIgnoreCase(ancestor,X4KEX) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KXLA ) then
if ( equalIgnoreCase(ancestor,X4KXLA) OR
equalIgnoreCase(ancestor,X4KXV) OR
equalIgnoreCase(ancestor,X4KXL) OR
equalIgnoreCase(ancestor,X4KEX) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KE ) then
if ( equalIgnoreCase(ancestor,X4KE) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KL ) then
if ( equalIgnoreCase(ancestor,X4KL) OR
equalIgnoreCase(ancestor,X4KE) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN ) then
if ( equalIgnoreCase(ancestor,SPARTAN) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTANXL ) then
if ( equalIgnoreCase(ancestor,SPARTANXL) OR
equalIgnoreCase(ancestor,SPARTAN) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, ANY ) then
if equalIgnoreCase( ancestor, any ) then is_derived := TRUE;
end if;
end if;
return is_derived;
end derived;
-- Returns the lower case form of char if char is an upper case letter.
-- Otherwise char is returned.
function toLowerCaseChar( char : character ) return character is
begin
-- If char is not an upper case letter then return char
if char < 'A' OR char > 'Z' then
return char;
end if;
-- Otherwise map char to its corresponding lower case character and
-- return that
case char is
when 'A' => return 'a';
when 'B' => return 'b';
when 'C' => return 'c';
when 'D' => return 'd';
when 'E' => return 'e';
when 'F' => return 'f';
when 'G' => return 'g';
when 'H' => return 'h';
when 'I' => return 'i';
when 'J' => return 'j';
when 'K' => return 'k';
when 'L' => return 'l';
when 'M' => return 'm';
when 'N' => return 'n';
when 'O' => return 'o';
when 'P' => return 'p';
when 'Q' => return 'q';
when 'R' => return 'r';
when 'S' => return 's';
when 'T' => return 't';
when 'U' => return 'u';
when 'V' => return 'v';
when 'W' => return 'w';
when 'X' => return 'x';
when 'Y' => return 'y';
when 'Z' => return 'z';
when others => return char;
end case;
end toLowerCaseChar;
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
function equalIgnoreCase( str1, str2 : string ) return boolean is
constant LEN1 : integer := str1'length;
constant LEN2 : integer := str2'length;
variable equal : boolean := TRUE;
begin
if not (LEN1 = LEN2) then
equal := FALSE;
else
for i in str1'range loop
if not (toLowerCaseChar(str1(i)) = toLowerCaseChar(str2(i))) then
equal := FALSE;
end if;
end loop;
end if;
return equal;
end equalIgnoreCase;
end family;
| apache-2.0 | 3077b07f3f01f8a9ccde1bcfa12d9df4 | 0.548575 | 4.69389 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/2-MESA-HB/metaheurísticas/mesahb_ibea.vhd | 1 | 1,943 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.10:17:04)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mesahb_ibea_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5: IN unsigned(0 TO 3);
output1, output2: OUT unsigned(0 TO 4));
END mesahb_ibea_entity;
ARCHITECTURE mesahb_ibea_description OF mesahb_ibea_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
output1 <= input2 + 2;
WHEN "00000010" =>
register1 := register1 + 4;
register2 := input3 * 5;
WHEN "00000011" =>
register1 := register1 * 7;
register2 := register2 + 9;
WHEN "00000100" =>
register1 := register1 + 11;
register2 := ((NOT register2) + 1) XOR register2;
register3 := input4 * 14;
WHEN "00000101" =>
register2 := register3 * register2;
register1 := ((NOT register1) + 1) XOR register1;
WHEN "00000110" =>
register1 := register1 * 18;
WHEN "00000111" =>
register3 := input5 * 19;
register1 := register1 + register2;
WHEN "00001000" =>
register2 := register3 + 21;
WHEN "00001001" =>
register2 := register2 * 23;
WHEN "00001010" =>
register2 := register2 + 25;
WHEN "00001011" =>
output2 <= register1(0 TO 1) & register2(0 TO 2);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mesahb_ibea_description; | gpl-3.0 | 0e1581d2ae9e44f98048b45feadd1306 | 0.652084 | 3.02648 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/6-FIR2/metaheurísticas/fir2_spea2.vhd | 1 | 3,332 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-26.14:52:11)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY fir2_spea2_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16: IN unsigned(0 TO 3);
output1: OUT unsigned(0 TO 4));
END fir2_spea2_entity;
ARCHITECTURE fir2_spea2_description OF fir2_spea2_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := not input1 or input1;
register2 := not input2 or input2;
register3 := not input3 or input3;
register4 := not input4 or input4;
WHEN "00000010" =>
register1 := register1 + register2;
register2 := not input5 or input5;
register5 := not input6 or input6;
register6 := not input7 or input7;
register3 := register3 + register4;
WHEN "00000011" =>
register2 := register2 + register5;
register4 := not input8 or input8;
register5 := not input9 or input9;
WHEN "00000100" =>
register2 := register2 * 11;
register5 := register6 + register5;
register6 := not input10 or input10;
WHEN "00000101" =>
register5 := register5 * 14;
register1 := register1 * 16;
register7 := not input11 or input11;
WHEN "00000110" =>
register4 := register4 + register7;
register7 := not input12 or input12;
WHEN "00000111" =>
register6 := register7 + register6;
register1 := register5 + register1;
register5 := not input13 or input13;
register7 := not input14 or input14;
register4 := register4 * 22;
register8 := not input15 or input15;
register3 := register3 * 25;
WHEN "00001000" =>
register6 := register6 * 27;
WHEN "00001001" =>
register1 := register6 + register1;
register5 := register8 + register5;
WHEN "00001010" =>
register5 := register5 * 29;
register1 := register4 + register1;
register4 := not input16 or input16;
WHEN "00001011" =>
register1 := register5 + register1;
register4 := register4 + register7;
WHEN "00001100" =>
register4 := register4 * 32;
WHEN "00001101" =>
register1 := register4 + register1;
WHEN "00001110" =>
register1 := register3 + register1;
WHEN "00001111" =>
register1 := register2 + register1;
WHEN "00010000" =>
output1 <= to_unsigned(2 ** to_integer(register1), 4);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END fir2_spea2_description; | gpl-3.0 | 938b9c88b17f115377b463f0b42c5138 | 0.668667 | 3.179389 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-30bits_outputs31bits/1-HAL/metaheurísticas/hal_femo.vhd | 1 | 1,623 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.09:05:18)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY hal_femo_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5: IN unsigned(0 TO 30);
output1, output2, output3: OUT unsigned(0 TO 31));
END hal_femo_entity;
ARCHITECTURE hal_femo_description OF hal_femo_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "0000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
register2 := input2 * 2;
WHEN "00000010" =>
output1 <= register2 + 3;
register2 := input3 * 4;
IF (register1 < 5) THEN
output2 <= register1;
ELSE
output2 <= "0000000000000000000000000000101";
END IF;
register1 := input4 * 6;
WHEN "00000011" =>
register1 := register2 * register1;
WHEN "00000100" =>
register1 := register1 - 8;
register2 := input5 * 9;
WHEN "00000101" =>
register2 := register2 * 11;
WHEN "00000110" =>
output3 <= register1 - register2;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END hal_femo_description; | gpl-3.0 | 37f82c4c12c49ef0ea2f635d0b0046a1 | 0.671596 | 3.127168 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/ramfifo/wr_handshaking_flags.vhd | 5 | 12,657 | `protect begin_protected
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| apache-2.0 | d1263744264ca1de8e15dc61f7effaad | 0.93071 | 1.891928 | false | false | false | false |
CyAScott/CIS4930.DatapathSynthesisTool | src/Synthesize/DataPath/Vhdl/c_adder.vhd | 1 | 952 | library ieee;
use ieee.std_logic_1164.all;
library WORK;
use WORK.all;
entity c_adder is
generic
(
width : integer := 4
);
port
(
input1, input2 : in std_logic_vector((width - 1) downto 0);
output : out std_logic_vector((width - 1) downto 0)
);
end c_adder;
architecture behavior of c_adder is
function bits_to_int (input : std_logic_vector)return integer is
variable ret_val : integer := 0;
begin
for i in input'range loop
if input(i) = '1' then
ret_val := 2 ** i + ret_val;
end if;
end loop;
return ret_val;
end bits_to_int;
begin
process (input1, input2)
variable value : integer;
variable result : std_logic_vector((width - 1) downto 0);
begin
value := bits_to_int(input1) + bits_to_int(input2);
for i in 0 to width - 1 loop
if (value rem 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
value := value / 2;
end loop;
output <= result;
end process;
end behavior; | mit | a3f7c839da5354e543730766598e2923 | 0.635504 | 2.735632 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/debug_profile.vhd | 1 | 43,288 | `protect begin_protected
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`protect end_protected
| apache-2.0 | 94e99bf2f21f9152acbd229a141a257a | 0.947953 | 1.827038 | false | false | false | false |
rhexsel/xinu-cMIPS | vhdl/pipestages.vhd | 2 | 8,283 | -- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-------------------------------------------------------------------------
-- Processor core pipeline registers
-------------------------------------------------------------------------
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- IF-RF
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use work.p_WIRES.all;
entity reg_IF_RF is
port(clk, rst, ld: in std_logic;
PCincd_d: in reg32;
PCincd_q: out reg32;
instr: in reg32;
RF_instr: out reg32);
end reg_IF_RF;
architecture funcional of reg_IF_RF is
begin
process(clk, rst)
begin
if rst = '0' then
PCincd_q <= x"00000000";
RF_instr <= x"00000000";
elsif rising_edge(clk) then
if ld = '0' then
PCincd_q <= PCincd_d ;
RF_instr <= instr ;
end if;
end if;
end process;
end funcional;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- RF-EX
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use work.p_WIRES.all;
entity reg_RF_EX is
port(clk, rst, ld: in std_logic;
selB: in std_logic;
EX_selB: out std_logic;
oper: in t_alu_fun;
EX_oper: out t_alu_fun;
a_rs: in reg5;
EX_a_rs: out reg5;
a_rt: in reg5;
EX_a_rt: out reg5;
a_c: in reg5;
EX_a_c: out reg5;
wreg: in std_logic;
EX_wreg: out std_logic;
muxC: in reg3;
EX_muxC: out reg3;
move: in std_logic;
EX_move: out std_logic;
postn: in reg5;
EX_postn: out reg5;
shamt: in reg5;
EX_shamt: out reg5;
aVal: in std_logic;
EX_aVal: out std_logic;
wrmem: in std_logic;
EX_wrmem: out std_logic;
mem_t: in reg4;
EX_mem_t: out reg4;
is_load: in boolean;
EX_is_load: out boolean;
A: in reg32;
EX_A: out reg32;
B: in reg32;
EX_B: out reg32;
displ32: in reg32;
EX_displ32: out reg32;
pc_p8: in reg32;
EX_pc_p8: out reg32);
end reg_RF_EX;
architecture funcional of reg_RF_EX is
begin
process(clk, rst)
begin
if rst = '0' then
EX_wreg <= '1';
EX_wrmem <= '1';
EX_aVal <= '1';
elsif rising_edge(clk) then
if ld = '0' then
EX_selB <= selB ;
EX_oper <= oper ;
EX_a_rs <= a_rs ;
EX_a_rt <= a_rt ;
EX_a_c <= a_c ;
EX_wreg <= wreg ;
EX_muxC <= muxC ;
EX_move <= move ;
EX_postn <= postn ;
EX_shamt <= shamt ;
EX_aVal <= aVal ;
EX_wrmem <= wrmem ;
EX_mem_t <= mem_t ;
EX_is_load <= is_load ;
EX_A <= A ;
EX_B <= B ;
EX_displ32 <= displ32 ;
EX_pc_p8 <= pc_p8 ;
end if;
end if;
end process;
end funcional;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- EX-MEM
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use work.p_WIRES.all;
entity reg_EX_MM is
port(clk, rst, ld: in std_logic;
EX_a_rt: in reg5;
MM_a_rt: out reg5;
EX_a_c: in reg5;
MM_a_c: out reg5;
EX_wreg: in std_logic;
MM_wreg: out std_logic;
EX_muxC: in reg3;
MM_muxC: out reg3;
EX_aVal: in std_logic;
MM_aVal: out std_logic;
EX_wrmem: in std_logic;
MM_wrmem: out std_logic;
EX_mem_t: in reg4;
MM_mem_t: out reg4;
EX_is_load: in boolean;
MM_is_load: out boolean;
EX_A: in reg32;
MM_A: out reg32;
EX_B: in reg32;
MM_B: out reg32;
EX_result: in reg32;
MM_result: out reg32;
EX_addr: in reg32;
MM_addr: out reg32;
HI: in reg32;
MM_HI: out reg32;
LO: in reg32;
MM_LO: out reg32;
EX_alu_move_ok: in std_logic;
MM_alu_move_ok: out std_logic;
EX_move: in std_logic;
MM_move: out std_logic;
EX_pc_p8: in reg32;
MM_pc_p8: out reg32);
end reg_EX_MM;
architecture funcional of reg_EX_MM is
begin
process(clk, rst)
begin
if rst = '0' then
MM_wreg <= '1';
MM_wrmem <= '1';
MM_aVal <= '1';
elsif rising_edge(clk) then
if ld = '0' then
MM_a_rt <= EX_a_rt ;
MM_a_c <= EX_a_c ;
MM_wreg <= EX_wreg ;
MM_muxC <= EX_muxC ;
MM_aVal <= EX_aVal ;
MM_wrmem <= EX_wrmem ;
MM_mem_t <= EX_mem_t ;
MM_is_load <= EX_is_load ;
MM_A <= EX_A ;
MM_B <= EX_B ;
MM_result <= EX_result ;
MM_addr <= EX_addr ;
MM_HI <= HI ;
MM_LO <= LO ;
MM_alu_move_ok <= EX_alu_move_ok ;
MM_move <= EX_move ;
MM_pc_p8 <= EX_pc_p8 ;
end if;
end if;
end process;
end funcional;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- MEM-WB
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use work.p_WIRES.all;
entity reg_MM_WB is
port(clk, rst, ld: in std_logic;
MM_a_c: in reg5;
WB_a_c: out reg5;
MM_wreg: in std_logic;
WB_wreg: out std_logic;
MM_muxC: in reg3;
WB_muxC: out reg3;
MM_A: in reg32;
WB_A: out reg32;
MM_result: in reg32;
WB_result: out reg32;
MM_HI: in reg32;
WB_HI: out reg32;
MM_LO: in reg32;
WB_LO: out reg32;
rd_data: in reg32;
WB_rd_data: out reg32;
MM_B_data: in reg32;
WB_B_data: out reg32;
MM_addr2: in reg2;
WB_addr2: out reg2;
MM_oper: in reg2;
WB_oper: out reg2;
MM_pc_p8: in reg32;
WB_pc_p8: out reg32);
end reg_MM_WB;
architecture funcional of reg_MM_WB is
begin
process(clk, rst)
begin
if rst = '0' then
WB_wreg <= '1';
elsif rising_edge(clk) then
if ld = '0' then
WB_a_c <= MM_a_c ;
WB_wreg <= MM_wreg ;
WB_muxC <= MM_muxC ;
WB_A <= MM_A ;
WB_result <= MM_result ;
WB_HI <= MM_HI ;
WB_LO <= MM_LO ;
WB_rd_data <= rd_data ;
WB_B_data <= MM_B_data ;
WB_addr2 <= MM_addr2 ;
WB_oper <= MM_oper ;
WB_pc_p8 <= MM_pc_p8 ;
end if;
end if;
end process;
end funcional;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| gpl-3.0 | 95376c9ccb0984970c9fc0333b34e7ea | 0.409876 | 3.3548 | false | false | false | false |
marceloboeira/vhdl-examples | 003-state-machine-square/source.vhd | 1 | 1,123 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity square is
Port ( number : in STD_LOGIC_VECTOR (15 downto 0);
clock : in STD_LOGIC;
output : out STD_LOGIC_VECTOR (15 downto 0);
done : out STD_LOGIC);
end square;
architecture Behavioral of square is
type FSM is (INITIAL, OPERATION, FINAL);
signal state : FSM;
signal n, d, r : STD_LOGIC_VECTOR (15 downto 0);
begin
main_process : process (clock)
begin
if clock'event and clock = '1' then
case state is
when INITIAL =>
n <= number;
d <= "000000000000001";
r <= "000000000000000";
done <= '0';
state <= OPERATION;
when OPERATION =>
if (n > 0) then
n <= n - d;
d <= d + 2;
r <= r + 1;
done <= '0';
state <= OPERATION;
else
state <= FINAL;
end if;
when FINAL =>
output <= r;
done <= '1';
state <= INITIAL;
when others =>
done <= '0';
state <= INITIAL;
end case;
end if;
end process;
end Behavioral;
| mit | 3c64d33bd0e3dfdd81c2a63b3cc232a3 | 0.500445 | 3.899306 | false | false | false | false |
KANGKANGABC/ArmRobot | MotorCtl.vhd | 1 | 17,432 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: ZhaoKang
--
-- Create Date: 2017/05/31 21:54:01
-- Design Name:
-- Module Name: MotorCtl - beh
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functns with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MotorCtl is
Port (
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
UART_TX : out STD_LOGIC;
M1_degree : in STD_LOGIC_VECTOR (15 downto 0);
M2_degree : in STD_LOGIC_VECTOR (15 downto 0);
M3_degree : in STD_LOGIC_VECTOR (15 downto 0);
M4_degree : in STD_LOGIC_VECTOR (15 downto 0);
M5_degree : in STD_LOGIC_VECTOR (15 downto 0);
M6_degree : in STD_LOGIC_VECTOR (15 downto 0)
--TMP : buffer STD_LOGIC_VECTOR (15 downto 0)
);
end entity;
architecture beh of MotorCtl is
component crc is
port (
clk: in std_logic;
data_in: in std_logic_vector(7 downto 0);
crc_in: in std_logic_vector(15 downto 0);
crc_out: out std_logic_vector(15 downto 0)
);
end component;
component UART_TX_CTRL is
port (
SEND : in STD_LOGIC;
DATA : in STD_LOGIC_VECTOR (7 downto 0);
CLK : in STD_LOGIC;
READY : out STD_LOGIC;
UART_TX : out STD_LOGIC
);
end component;
--component InstructionRam is
--PORT (
-- clka : IN STD_LOGIC;
-- wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
-- addra : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
-- dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-- douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
-- clkb : IN STD_LOGIC;
-- web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
-- addrb : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
-- dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-- doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
-- );
--end component;
SIGNAL clk_1 : std_logic;
SIGNAL crc_ret : std_logic_vector (15 downto 0);
SIGNAL crc_int : std_logic_vector (15 downto 0);
SIGNAL crc_data : std_logic_vector (7 downto 0);
--SIGNAL wea : std_logic_vector (0 downto 0);
--SIGNAL addra : std_logic_vector (6 downto 0);
--SIGNAL addrb : std_logic_vector (6 downto 0);
--SIGNAL dina : std_logic_vector (7 downto 0);
--SIGNAL douta : std_logic_vector (7 downto 0);
--SIGNAL dinb : std_logic_vector (7 downto 0);
--SIGNAL doutb : std_logic_vector (7 downto 0);
TYPE matrix_index is array (13 downto 0) of std_logic_vector(7 downto 0);
TYPE StateType is (S000,S00, S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14,
S15, S16, S17, S18, S19, S20, S21, S22, S23);
SIGNAL m1, m2, m3, m4, m5, m6 : matrix_index;
SIGNAL m1a, m2a, m3a, m4a, m5a, m6a : matrix_index;
signal UartBusy : std_logic;
signal UartCtl : std_logic;
signal UartData : std_logic_vector(7 DOWNTO 0);
begin
crc_ins : crc
port map(
clk => clk_1,
data_in => crc_data,
crc_in => crc_int,
crc_out => crc_ret
);
UART_TX_CTRL_ins : UART_TX_CTRL
port map(
READY => UartBusy,
UART_TX => UART_TX,
CLK => clk_1,
DATA => UartData,
SEND => UartCtl
);
-- InstructionRam_ins : InstructionRam
-- port map(
-- clka => clk_1,
-- clkb => clk_1,
-- wea => wea,
-- web => wea,
-- addra => addra,
-- addrb => addrb,
-- dina => dina,
-- douta => douta,
-- dinb => dinb,
-- doutb => doutb
-- );
process(CLK)
variable state : StateType := S000;
variable count1 : integer range 0 to 13;
variable TMP : std_logic_vector (15 downto 0);
begin
-- m1(12) <= x"FF";m2(12) <= x"FF";m3(12) <= x"FF";m4(12) <= x"FF";m5(12) <= x"FF";m6(12) <= x"FF";
-- m1(13) <= x"FF";m2(13) <= x"FF";m3(13) <= x"FF";m4(13) <= x"FF";m5(13) <= x"FF";m6(13) <= x"FF";
clk_1 <= CLK;
if RESET = '0' then
count1 := 0;
state := S000;
elsif falling_edge(CLK) then
case state is
when S000 =>
m1(0) <= x"FF";m2(0) <= x"FF";m3(0) <= x"FF";m4(0) <= x"FF";m5(0) <= x"FF";m6(0) <= x"FF";
m1(1) <= x"FF";m2(1) <= x"FF";m3(1) <= x"FF";m4(1) <= x"FF";m5(1) <= x"FF";m6(1) <= x"FF";
m1(2) <= x"FD";m2(2) <= x"FD";m3(2) <= x"FD";m4(2) <= x"FD";m5(2) <= x"FD";m6(2) <= x"FD";
m1(3) <= x"00";m2(3) <= x"00";m3(3) <= x"00";m4(3) <= x"00";m5(3) <= x"00";m6(3) <= x"00";
m1(4) <= x"01";m2(4) <= x"02";m3(4) <= x"03";m4(4) <= x"04";m5(4) <= x"05";m6(4) <= x"06";
m1(5) <= x"07";m2(5) <= x"07";m3(5) <= x"07";m4(5) <= x"07";m5(5) <= x"07";m6(5) <= x"07";
m1(6) <= x"00";m2(6) <= x"00";m3(6) <= x"00";m4(6) <= x"00";m5(6) <= x"00";m6(6) <= x"00";
m1(7) <= x"03";m2(7) <= x"03";m3(7) <= x"03";m4(7) <= x"03";m5(7) <= x"03";m6(7) <= x"03";
m1(8) <= x"1E";m2(8) <= x"1E";m3(8) <= x"1E";m4(8) <= x"1E";m5(8) <= x"1E";m6(8) <= x"1E";
m1(9) <= x"00";m2(9) <= x"00";m3(9) <= x"00";m4(9) <= x"00";m5(9) <= x"00";m6(9) <= x"00";
m1(10) <= M1_degree(7 DOWNTO 0);m2(10) <= M2_degree(7 DOWNTO 0);m3(10) <= M3_degree(7 DOWNTO 0);
m4(10) <= M4_degree(7 DOWNTO 0);m5(10) <= M5_degree(7 DOWNTO 0);m6(10) <= M6_degree(7 DOWNTO 0);
m1(11) <= M1_degree(15 DOWNTO 8);m2(11) <= M2_degree(15 DOWNTO 8);m3(11) <= M3_degree(15 DOWNTO 8);
m4(11) <= M4_degree(15 DOWNTO 8);m5(11) <= M5_degree(15 DOWNTO 8);m6(11) <= M6_degree(15 DOWNTO 8);
state := S00;
when S00 =>
crc_int <= x"0000";
crc_data <= m1(count1);
state := S0;
when S0 =>
crc_int <= crc_ret;
count1 := count1 + 1;
crc_data<= m1(count1);
state := S1;
when S1 =>
if count1 < 11 then
state := S0;
else
state := S2;
count1 := 0;
TMP := crc_ret;
end if;
when S2 =>
m1(12) <= crc_ret(7 downto 0);
m1(13) <= crc_ret(15 downto 8);
crc_int <= x"0000";
crc_data <= m2(count1);
state := S3;
when S3 =>
crc_int <= crc_ret;
count1 := count1 + 1;
crc_data<= m2(count1);
state := S4;
when S4 =>
if count1 < 11 then
state := S3;
else
state := S5;
count1 := 0;
TMP := crc_ret;
end if;
when S5 =>
m2(12) <= crc_ret(7 downto 0);
m2(13) <= crc_ret(15 downto 8);
crc_int <= x"0000";
crc_data <= m3(count1);
state := S6;
when S6 =>
crc_int <= crc_ret;
count1 := count1 + 1;
crc_data<= m3(count1);
state := S7;
when S7 =>
if count1 < 11 then
state := S6;
else
state := S8;
count1 := 0;
TMP := crc_ret;
end if;
when S8 =>
m3(12) <= crc_ret(7 downto 0);
m3(13) <= crc_ret(15 downto 8);
crc_int <= x"0000";
crc_data <= m4(count1);
state := S9;
when S9 =>
crc_int <= crc_ret;
count1 := count1 + 1;
crc_data<= m4(count1);
state := S10;
when S10 =>
if count1 < 11 then
state := S9;
else
state := S11;
count1 := 0;
TMP := crc_ret;
end if;
when S11 =>
m4(12) <= crc_ret(7 downto 0);
m4(13) <= crc_ret(15 downto 8);
crc_int <= x"0000";
crc_data <= m5(count1);
state := S12;
when S12 =>
crc_int <= crc_ret;
count1 := count1 + 1;
crc_data<= m5(count1);
state := S13;
when S13 =>
if count1 < 11 then
state := S12;
else
state := S14;
count1 := 0;
TMP := crc_ret;
end if;
when S14 =>
m5(12) <= crc_ret(7 downto 0);
m5(13) <= crc_ret(15 downto 8);
crc_int <= x"0000";
crc_data <= m6(count1);
state := S15;
when S15 =>
crc_int <= crc_ret;
count1 := count1 + 1;
crc_data<= m6(count1);
state := S16;
when S16 =>
if count1 < 11 then
state := S15;
else
state := S17;
count1 := 0;
TMP := crc_ret;
end if;
when S17 =>
m6(12) <= crc_ret(7 downto 0);
m6(13) <= crc_ret(15 downto 8);
m1a <= m1;
m2a <= m2;
m3a <= m3;
m4a <= m4;
m5a <= m5;
m6a <= m6;
state := S000;
when others =>
state := S000;
end case;
end if;
end process;
process(CLK)
variable state1 : StateType := S000;
variable count2 : integer range 0 to 14;
begin
if RESET = '0' then
state1 := S000;
count2 := 0;
elsif falling_edge(CLK) then
case state1 is
when S000 =>
UartCtl <= '0';
UartData <= x"00";
state1 := S00;
count2 := 0;
---------------------------motor1--------------------------------
when S00 =>
UartData <= m1a(count2);
state1 := S0;
when S0 =>
UartCtl <= '1';
count2 := count2 + 1;
state1 := S1;
when S1 =>
if UartBusy = '1' then
UartCtl <= '0';
state1 := S2;
end if;
when S2 =>
if count2 < 14 then
state1 := S00;
else
state1 := S3;
count2 := 0;
end if;
---------------------------motor2--------------------------------
when S3 =>
UartData <= m2a(count2);
state1 := S4;
when S4 =>
UartCtl <= '1';
count2 := count2 + 1;
state1 := S5;
when S5 =>
if UartBusy = '1' then
UartCtl <= '0';
state1 := S6;
end if;
when S6 =>
if count2 < 14 then
state1 := S3;
else
state1 := S7;
count2 := 0;
end if;
---------------------------motor3--------------------------------
when S7 =>
UartData <= m3a(count2);
state1 := S8;
when S8 =>
UartCtl <= '1';
count2 := count2 + 1;
state1 := S9;
when S9 =>
if UartBusy = '1' then
UartCtl <= '0';
state1 := S10;
end if;
when S10 =>
if count2 < 14 then
state1 := S7;
else
state1 := S11;
count2 := 0;
end if;
---------------------------motor4--------------------------------
when S11 =>
UartData <= m4a(count2);
state1 := S12;
when S12 =>
UartCtl <= '1';
count2 := count2 + 1;
state1 := S13;
when S13 =>
if UartBusy = '1' then
UartCtl <= '0';
state1 := S14;
end if;
when S14 =>
if count2 < 14 then
state1 := S11;
else
state1 := S15;
count2 := 0;
end if;
---------------------------motor5--------------------------------
when S15 =>
UartData <= m5a(count2);
state1 := S16;
when S16 =>
UartCtl <= '1';
count2 := count2 + 1;
state1 := S17;
when S17 =>
if UartBusy = '1' then
UartCtl <= '0';
state1 := S18;
end if;
when S18 =>
if count2 < 14 then
state1 := S15;
else
state1 := S19;
count2 := 0;
end if;
---------------------------motor6--------------------------------
when S19 =>
UartData <= m6a(count2);
state1 := S20;
when S20 =>
UartCtl <= '1';
count2 := count2 + 1;
state1 := S21;
when S21 =>
if UartBusy = '1' then
UartCtl <= '0';
state1 := S22;
end if;
when S22 =>
if count2 < 14 then
state1 := S19;
else
state1 := S23;
count2 := 0;
end if;
when S23 =>
state1 := S000;
when others =>
state1 := S000;
end case;
end if;
end process;
end architecture;
| gpl-3.0 | 7aa9e83fcf20d0a3308bb4d803d5fd96 | 0.323084 | 4.245494 | false | false | false | false |
mbgh/aes128-hdl | src/vhdl/mixColumn.vhd | 1 | 4,555 | -------------------------------------------------------------------------------
--! @file mixColumn.vhd
--! @brief AES MixColumn operation (single column)
--! @project VLSI Book - AES-128 Example
--! @author Michael Muehlberghuber ([email protected])
--! @company Integrated Systems Laboratory, ETH Zurich
--! @copyright Copyright (C) 2014 Integrated Systems Laboratory, ETH Zurich
--! @date 2014-06-05
--! @updated 2014-06-05
--! @platform Simulation: ModelSim; Synthesis: Synopsys
--! @standard VHDL'93/02
-------------------------------------------------------------------------------
-- Revision Control System Information:
-- File ID : $Id: mixColumn.vhd 6 2014-06-12 12:49:55Z u59323933 $
-- Revision : $Revision: 6 $
-- Local Date : $Date: 2014-06-12 14:49:55 +0200 (Thu, 12 Jun 2014) $
-- Modified By : $Author: u59323933 $
-------------------------------------------------------------------------------
-- Major Revisions:
-- Date Version Author Description
-- 2014-06-05 1.0 michmueh Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.aes128Pkg.all;
-------------------------------------------------------------------------------
--! @brief AES MixColumn operation (single column)
--!
--! The present design implements the MixColumn operation of the Advanced
--! Encryption Standard (AES).
-------------------------------------------------------------------------------
entity mixColumn is
port (
--! @brief Input to the "MixColumn" function.
In_DI : in Word;
--! @brief Output of the "MixColumn" function.
Out_DO : out Word);
end entity mixColumn;
-------------------------------------------------------------------------------
--! @brief Behavioral architecture of the "MixColumn" function.
-------------------------------------------------------------------------------
architecture Behavioral of mixColumn is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal Byte0_D, Byte0Doubled_D, Byte0Tripled_D : Byte;
signal Byte1_D, Byte1Doubled_D, Byte1Tripled_D : Byte;
signal Byte2_D, Byte2Doubled_D, Byte2Tripled_D : Byte;
signal Byte3_D, Byte3Doubled_D, Byte3Tripled_D : Byte;
begin -- architecture Behavioral
-----------------------------------------------------------------------------
-- First Byte
-----------------------------------------------------------------------------
Byte0_D <= In_DI(0);
Byte0Doubled_D <= ((In_DI(0)(6 downto 0) & '0') xor x"1B") when In_DI(0)(7) = '1'
else (In_DI(0)(6 downto 0) & '0');
Byte0Tripled_D <= Byte0Doubled_D xor Byte0_D;
-----------------------------------------------------------------------------
-- Second Byte
-----------------------------------------------------------------------------
Byte1_D <= In_DI(1);
Byte1Doubled_D <= ((In_DI(1)(6 downto 0) & '0') xor x"1B") when In_DI(1)(7) = '1'
else (In_DI(1)(6 downto 0) & '0');
Byte1Tripled_D <= Byte1Doubled_D xor Byte1_D;
-----------------------------------------------------------------------------
-- Third Byte
-----------------------------------------------------------------------------
Byte2_D <= In_DI(2);
Byte2Doubled_D <= ((In_DI(2)(6 downto 0) & '0') xor x"1B") when In_DI(2)(7) = '1'
else (In_DI(2)(6 downto 0) & '0');
Byte2Tripled_D <= Byte2Doubled_D xor Byte2_D;
-----------------------------------------------------------------------------
-- Fourth Byte
-----------------------------------------------------------------------------
Byte3_D <= In_DI(3);
Byte3Doubled_D <= ((In_DI(3)(6 downto 0) & '0') xor x"1B") when In_DI(3)(7) = '1'
else (In_DI(3)(6 downto 0) & '0');
Byte3Tripled_D <= Byte3Doubled_D xor Byte3_D;
-----------------------------------------------------------------------------
-- Output Assignment
-----------------------------------------------------------------------------
Out_DO(0) <= Byte0Doubled_D xor Byte1Tripled_D xor Byte2_D xor Byte3_D;
Out_DO(1) <= Byte0_D xor Byte1Doubled_D xor Byte2Tripled_D xor Byte3_D;
Out_DO(2) <= Byte0_D xor Byte1_D xor Byte2Doubled_D xor Byte3Tripled_D;
Out_DO(3) <= Byte0Tripled_D xor Byte1_D xor Byte2_D xor Byte3Doubled_D;
end architecture Behavioral;
| gpl-2.0 | 67bb203a203bf172ba9b778500e819d2 | 0.407903 | 4.221501 | false | false | false | false |
rhexsel/xinu-cMIPS | vhdl/tb_cMIPS.vhd | 1 | 48,115 | -- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- testbench for classicalMIPS
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
entity tb_cMIPS is
end tb_cMIPS;
architecture TB of tb_cMIPS is
component FFD is
port(clk, rst, set, D : in std_logic; Q : out std_logic);
end component FFD;
component SDcard is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
rdy : out std_logic;
wr : in std_logic;
addr : in std_logic_vector; -- a03, a02
data_inp : in std_logic_vector;
data_out : out std_logic_vector;
sdc_cs : out std_logic; -- SDcard chip-select
sdc_clk : out std_logic; -- SDcard serial clock
sdc_mosi_o : out std_logic; -- SDcard serial data out (to card)
sdc_miso_i : in std_logic; -- SDcard serial data inp (fro card)
irq : out std_logic); -- interrupt request (not yet used)
end component SDCard;
component DISK is
port (rst : in std_logic;
clk : in std_logic;
strobe : in std_logic; -- strobe for file reads/writes
sel : in std_logic;
rdy : out std_logic;
wr : in std_logic;
busFree : in std_logic; -- '1' = bus will be free next cycle
busReq : out std_logic; -- '1' = bus will be used next cycle
busGrant : in std_logic; -- '1' = bus is free in this cycle
addr : in reg3;
data_inp : in reg32;
data_out : out reg32;
irq : out std_logic;
dma_addr : out reg32;
dma_dinp : in reg32;
dma_dout : out reg32;
dma_wr : out std_logic;
dma_aval : out std_logic;
dma_type : out reg4);
end component DISK;
component LCD_display is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
rdy : out std_logic;
wr : in std_logic;
addr : in std_logic; -- 0=constrol, 1=data
data_inp : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0);
LCD_DATA : inout std_logic_vector(7 downto 0); -- bidirectional bus
LCD_RS : out std_logic; -- LCD register select 0=ctrl, 1=data
LCD_RW : out std_logic; -- LCD read=1, 0=write
LCD_EN : out std_logic; -- LCD enable=1
LCD_BLON : out std_logic);
end component LCD_display;
component to_7seg is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
data : in std_logic_vector;
display0 : out std_logic_vector;
display1 : out std_logic_vector;
red : out std_logic;
green : out std_logic;
blue : out std_logic);
end component to_7seg;
component read_keys is
generic (DEB_CYCLES : natural);
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
data : out reg32;
kbd : in std_logic_vector (11 downto 0);
sw : in std_logic_vector (3 downto 0));
end component read_keys;
component to_stdout is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
data : in std_logic_vector);
end component to_stdout;
component from_stdin is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
data : out std_logic_vector);
end component from_stdin;
component print_data is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
data : in std_logic_vector);
end component print_data;
component write_data_file is
generic (OUTPUT_FILE_NAME : string);
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
addr : in std_logic_vector;
data : in std_logic_vector;
byte_sel : in std_logic_vector;
dump_ram : out std_logic);
end component write_data_file;
component read_data_file is
generic (INPUT_FILE_NAME : string);
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
addr : in std_logic_vector;
data : out std_logic_vector;
byte_sel: in std_logic_vector);
end component read_data_file;
component do_interrupt is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
data_inp : in std_logic_vector;
data_out : out std_logic_vector;
irq : out std_logic);
end component do_interrupt;
component simple_uart is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
addr : in std_logic_vector;
data_inp : in std_logic_vector;
data_out : out std_logic_vector;
txdat : out std_logic;
rxdat : in std_logic;
rts : out std_logic;
cts : in std_logic;
irq : out std_logic;
bit_rt : out std_logic_vector);-- communication speed - TB only
end component simple_uart;
component FPU is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
rdy : out std_logic;
wr : in std_logic;
addr : in std_logic_vector;
data_inp : in std_logic_vector;
data_out : out std_logic_vector);
end component FPU;
component remota is
generic(OUTPUT_FILE_NAME : string; INPUT_FILE_NAME : string);
port(rst, clk : in std_logic;
start : in std_logic;
inpDat : in std_logic; -- serial input
outDat : out std_logic; -- serial output
bit_rt : in std_logic_vector);
end component remota;
component sys_stats is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
addr : in std_logic_vector;
data : out std_logic_vector;
cnt_dc_ref : in integer;
cnt_dc_rd_hit : in integer;
cnt_dc_wr_hit : in integer;
cnt_dc_flush : in integer;
cnt_ic_ref : in integer;
cnt_ic_hit : in integer);
end component sys_stats;
component ram_addr_decode is
port (rst : in std_logic;
cpu_d_aVal : in std_logic;
addr : in std_logic_vector;
aVal : out std_logic;
dev_select : out std_logic_vector);
end component ram_addr_decode;
component sdram_addr_decode is
port (rst : in std_logic;
cpu_d_aVal : in std_logic;
addr : in std_logic_vector;
aVal : out std_logic;
dev_select : out std_logic_vector);
end component sdram_addr_decode;
component io_addr_decode is
port (rst : in std_logic;
clk : in std_logic;
cpu_d_aVal : in std_logic;
addr : in std_logic_vector;
dev_select : out std_logic_vector;
print_sel : out std_logic;
stdout_sel : out std_logic;
stdin_sel : out std_logic;
read_sel : out std_logic;
write_sel : out std_logic;
counter_sel : out std_logic;
FPU_sel : out std_logic;
uart_sel : out std_logic;
sstats_sel : out std_logic;
dsp7seg_sel : out std_logic;
keybd_sel : out std_logic;
lcd_sel : out std_logic;
sdc_sel : out std_logic;
dma_sel : out std_logic;
not_waiting : in std_logic);
end component io_addr_decode;
component busError_addr_decode is
port (rst : in std_logic;
cpu_d_aVal : in std_logic;
addr : in reg32;
d_busError : out std_logic); -- decoded address not in range (act=0)
end component busError_addr_decode;
component inst_addr_decode is
port (rst : in std_logic;
cpu_i_aVal : in std_logic;
addr : in std_logic_vector;
aVal : out std_logic;
i_busError : out std_logic);
end component inst_addr_decode;
component ROM is
generic (LOAD_FILE_NAME : string);
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
rdy : out std_logic;
strobe : in std_logic;
addr : in std_logic_vector;
data : out std_logic_vector);
end component ROM;
component RAM is
generic (LOAD_FILE_NAME : string; DUMP_FILE_NAME : string);
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
rdy : out std_logic;
wr : in std_logic;
strobe : in std_logic;
addr : in std_logic_vector;
data_inp : in std_logic_vector;
data_out : out std_logic_vector;
byte_sel : in std_logic_vector;
dump_ram : in std_logic);
end component RAM;
component SDRAM_controller is
port (rst : in std_logic; -- FPGA reset (=0)
clk : in std_logic; -- CPU clock
clk2x : in std_logic; -- 100MHz clock
sel : in std_logic; -- host side chip select (=0)
rdy : out std_logic; -- tell CPU to wait (=0)
wr : in std_logic; -- host side write enable (=0)
bsel : in reg4; -- byte select
haddr : in reg26; -- host side address
hDinp : in reg32; -- host side data input
hDout : out reg32; -- host side data output
cke : out std_logic; -- ram side clock enable
scs : out std_logic; -- ram side chip select
ras : out std_logic; -- ram side RAS
cas : out std_logic; -- ram side CAS
we : out std_logic; -- ram side write enable
dqm0 : out std_logic; -- ram side byte0 output enable
dqm1 : out std_logic; -- ram side byte0 output enable
ba0 : out std_logic; -- ram side bank select 0
ba1 : out std_logic; -- ram side bank select 1
saddr : out reg12; -- ram side address
sdata : inout reg16); -- ram side data
end component SDRAM_controller;
component I_CACHE is
port (rst : in std_logic;
clk4x : in std_logic;
ic_reset : out std_logic;
cpu_sel : in std_logic;
cpu_rdy : out std_logic;
cpu_addr : in std_logic_vector;
cpu_data : out std_logic_vector;
mem_sel : out std_logic;
mem_rdy : in std_logic;
mem_addr : out std_logic_vector;
mem_data : in std_logic_vector;
ref_cnt : out integer;
hit_cnt : out integer);
end component I_CACHE;
component I_CACHE_fpga is
port (rst : in std_logic;
clk4x : in std_logic;
ic_reset : out std_logic;
cpu_sel : in std_logic;
cpu_rdy : out std_logic;
cpu_addr : in std_logic_vector;
cpu_data : out std_logic_vector;
mem_sel : out std_logic;
mem_rdy : in std_logic;
mem_addr : out std_logic_vector;
mem_data : in std_logic_vector;
ref_cnt : out integer;
hit_cnt : out integer);
end component I_CACHE_fpga;
component D_CACHE is
port (rst : in std_logic;
clk4x : in std_logic;
cpu_sel : in std_logic;
cpu_rdy : out std_logic;
cpu_wr : in std_logic;
cpu_addr : in std_logic_vector;
cpu_data_inp : in std_logic_vector;
cpu_data_out : out std_logic_vector;
cpu_xfer : in std_logic_vector;
mem_sel : out std_logic;
mem_rdy : in std_logic;
mem_wr : out std_logic;
mem_addr : out std_logic_vector;
mem_data_inp : in std_logic_vector;
mem_data_out : out std_logic_vector;
mem_xfer : out std_logic_vector;
ref_cnt : out integer;
rd_hit_cnt : out integer;
wr_hit_cnt : out integer;
flush_cnt : out integer);
end component D_CACHE;
component core is
port (rst : in std_logic;
clk : in std_logic;
phi1 : in std_logic;
phi2 : in std_logic;
phi3 : in std_logic;
i_aVal : out std_logic;
i_wait : in std_logic;
i_addr : out std_logic_vector;
instr : in std_logic_vector;
d_aVal : out std_logic;
d_wait : in std_logic;
d_addr : out std_logic_vector;
data_inp : in std_logic_vector;
data_out : out std_logic_vector;
wr : out std_logic;
b_sel : out std_logic_vector;
busFree : out std_logic;
nmi : in std_logic;
irq : in std_logic_vector;
i_busErr : in std_logic;
d_busErr : in std_logic);
end component core;
component mf_altpll port (
areset : IN STD_LOGIC;
inclk0 : IN STD_LOGIC;
c0 : OUT STD_LOGIC;
c1 : OUT STD_LOGIC;
c2 : OUT STD_LOGIC;
c3 : OUT STD_LOGIC;
c4 : OUT STD_LOGIC);
end component mf_altpll;
component mf_altpll_io port (
areset : IN STD_LOGIC;
inclk0 : IN STD_LOGIC;
c0 : OUT STD_LOGIC;
c1 : OUT STD_LOGIC;
c2 : OUT STD_LOGIC);
end component mf_altpll_io;
component mf_altclkctrl port (
inclk : IN STD_LOGIC;
outclk : OUT STD_LOGIC);
end component mf_altclkctrl;
-- use simulation / fake
for U_from_stdin : from_stdin use entity work.from_stdin(simulation);
-- use simulation / fake
for U_print_data : print_data use entity work.print_data(simulation);
-- use simulation / fake
for U_to_stdout : to_stdout use entity work.to_stdout(simulation);
-- use simulation / fake
for U_write_out : write_data_file
use entity work.write_data_file(simulation);
-- use simulation / fake
for U_read_inp : read_data_file
use entity work.read_data_file(simulation);
-- use fake / behavioral
for U_I_CACHE : I_cache use entity work.I_cache(fake);
-- use simulation / rtl
for U_ROM : ROM use entity work.ROM(simulation);
-- use simulation / rtl
for U_RAM : RAM use entity work.RAM(simulation);
-- use fake / behavioral
for U_D_CACHE : D_cache use entity work.D_cache(fake);
-- use fake / rtl
for U_FPU: FPU use entity work.FPU(rtl);
-- use fake / simple
for U_SDRAMc : SDRAM_controller
use entity work.SDRAM_controller(simple);
-- use simulation / fake
for U_DISK : DISK use entity work.DISK(simulation);
-- use fake / rtl
for U_SDcard : SDcard use entity work.SDcard(fake);
-- use fake / rtl
for U_LCD_display : LCD_display use entity work.LCD_display(fake);
-- use simulation / fake
for U_uart_remota: remota use entity work.remota(simulation);
signal clock_50mhz, clk,clkin : std_logic;
signal clk4x,clk4x0, clk4x180, clk2x : std_logic;
signal phi0,phi1,phi2,phi3,phi0in,phi1in,phi2in,phi3in, phi2_dlyd : std_logic;
signal rst,ic_reset,a_rst1,a_rst2,a_rst3, cpu_reset : std_logic;
signal a_reset, async_reset : std_logic;
signal cpu_i_aVal, cpu_i_wait, wr, cpu_d_aVal, cpu_d_wait : std_logic;
signal busFree, nmi, i_busError, d_busError : std_logic;
signal irq : reg6;
signal inst_aVal, inst_wait, rom_rdy : std_logic;
signal data_aVal, data_wait, ram_rdy, mem_wr : std_logic;
signal sdram_aVal, sdram_wait, sdram_wr : std_logic;
signal cpu_xfer, mem_xfer : reg4;
signal dev_select, dev_select_ram, dev_select_io, dev_select_sdram : reg4;
signal io_print_sel : std_logic := '1';
signal io_stdout_sel : std_logic := '1';
signal io_stdin_sel : std_logic := '1';
signal io_write_sel : std_logic := '1';
signal io_read_sel : std_logic := '1';
signal io_counter_sel : std_logic := '1';
signal io_uart_sel : std_logic := '1';
signal io_sstats_sel : std_logic := '1';
signal io_7seg_sel : std_logic := '1';
signal io_keys_sel : std_logic := '1';
signal io_fpu_sel, io_fpu_wait : std_logic := '1';
signal io_lcd_sel, io_lcd_wait : std_logic := '1';
signal io_sdc_sel, io_sdc_wait : std_logic := '1';
signal io_dma_sel : std_logic := '1';
signal d_cache_d_out, stdin_d_out, read_d_out, counter_d_out : reg32;
signal fpu_d_out, uart_d_out, sstats_d_out, keybd_d_out : reg32;
signal lcd_d_out, sdc_d_out, sdram_d_out, dma_d_out : reg32;
signal counter_irq : std_logic;
signal io_wait, not_waiting : std_logic;
signal i_addr,d_addr,p_addr : reg32;
signal datrom, datram_inp,datram_out, cpu_instr : reg32;
signal cpu_data_inp, cpu_data_out, cpu_data : reg32;
signal mem_i_sel, mem_d_sel: std_logic;
signal mem_i_addr, mem_addr, mem_d_addr: reg32;
signal cnt_i_ref,cnt_i_hit : integer;
signal cnt_d_ref,cnt_d_rd_hit,cnt_d_wr_hit,cnt_d_flush : integer;
signal dump_ram : std_logic;
signal bit_rt : reg3;
-- Macnica development board's peripherals
signal disp0,disp1 : reg8; -- 7 segment displays
signal key : reg12; -- 12 key telephone keyboard
signal sw : reg4; -- 4 slide switches
signal led_r, led_g, led_b : std_logic; -- RGB leds (on board signals)
signal LCD_D : std_logic_vector(7 downto 0); -- LCD data bus
signal LCD_RS, LCD_RW, LCD_EN, LCD_BACKLIGHT : std_logic; -- LCD control
signal uart_txd, uart_rxd, uart_rts, uart_cts, uart_irq : std_logic;
signal sdc_cs, sdc_clk, sdc_mosi_o, sdc_miso_i : std_logic;
signal sdcke, sdscs, sdras, sdcas, sdwe : std_logic; -- SDRAM
signal sddqm0, sddqm1, sdba0, sdba1 : std_logic;
signal sdaddr : reg12;
signal sddata : reg16;
signal hDinp, hDout : reg32;
-- disk device, simulation only
signal dma_addr, dma_dinp, dma_dout, ram_addr, ram_inp : reg32;
signal dma_wr, ram_wr, dma_aval, dma_irq, ram_sel : std_logic;
signal dma_type, ram_xfer : reg4;
signal busReq, busFree_dly, dma_grant : std_logic;
begin -- TB
pll : mf_altpll port map (areset => a_reset, inclk0 => clock_50mhz,
c0 => phi0in, c1 => phi1in, c2 => phi2in, c3 => phi3in, c4 => clkin);
-- pll_io : mf_altpll_io port map (areset => a_reset, inclk0 => clock_50mhz,
-- c0 => clk2x, c1 => clk4x0, c2 => clk4x180);
clk4x0 <= '0';
clk4x180 <= '0';
mf_altclkctrl_inst_clk : mf_altclkctrl port map (
inclk => clkin, outclk => clk);
mf_altclkctrl_inst_clk4x : mf_altclkctrl port map (
inclk => clk4x180, outclk => clk4x);
mf_altclkctrl_inst_phi0 : mf_altclkctrl port map (
inclk => phi0in, outclk => phi0);
mf_altclkctrl_inst_phi1 : mf_altclkctrl port map (
inclk => phi1in, outclk => phi1);
mf_altclkctrl_inst_phi2 : mf_altclkctrl port map (
inclk => phi2in, outclk => phi2);
mf_altclkctrl_inst_phi3 : mf_altclkctrl port map (
inclk => phi3in, outclk => phi3);
-- synchronize reset
a_rst1 <= a_reset or rst;
U_SYNC_RESET1: FFD port map (clk, a_rst2, '1', a_rst1, rst);
U_SYNC_RESET2: FFD port map (clk, a_reset, '1', '1', a_rst2);
async_reset <= rst and ic_reset;
U_SYNC_RESET3: FFD port map (clk, rst, '1', async_reset, a_rst3);
U_SYNC_RESET4: FFD port map (clk, rst, '1', a_rst3, cpu_reset);
cpu_i_wait <= inst_wait;
cpu_d_wait <= data_wait and io_wait and sdram_wait;
io_wait <= io_lcd_wait and io_fpu_wait and io_sdc_wait;
not_waiting <= (inst_wait and data_wait and sdram_wait); -- and io_wait);
-- Count=Compare at IRQ7, UART at IRQ6, DMA at IRQ5, extCounter at IRQ4,
-- C=C U D E 0 0 sw1 sw0
-- uart+dma_disk+counter interrupts
irq <= ZERO & uart_irq & dma_irq & counter_irq & ZERO & ZERO;
-- irq <= b"000000"; -- NO interrupt requests
nmi <= NO; -- input port to TB
U_CORE: core
port map (cpu_reset, clk, phi1,phi2,phi3,
cpu_i_aVal, cpu_i_wait, i_addr, cpu_instr,
cpu_d_aVal, cpu_d_wait, d_addr, cpu_data_inp, cpu_data,
wr, cpu_xfer, busFree, nmi, irq, i_busError, d_busError);
U_INST_ADDR_DEC: inst_addr_decode
port map (rst, cpu_i_aVal, i_addr, inst_aVal, i_busError);
U_I_CACHE: i_cache
port map (rst, clk4x, ic_reset,
inst_aVal, inst_wait, i_addr, cpu_instr,
mem_i_sel, rom_rdy, mem_i_addr, datrom, cnt_i_ref,cnt_i_hit);
U_ROM: ROM generic map ("prog.bin")
port map (rst, clk, mem_i_sel,rom_rdy, phi3, mem_i_addr,datrom);
U_DATA_BUS_ERROR_DEC: busError_addr_decode
port map (rst, cpu_d_aVal, d_addr, d_busError);
-- d_busError <= '1'; -- only while testing the SDRAM
U_IO_ADDR_DEC: io_addr_decode
port map (rst, phi0, cpu_d_aVal, d_addr, dev_select_io,
io_print_sel, io_stdout_sel, io_stdin_sel, io_read_sel,
io_write_sel, io_counter_sel, io_fpu_sel, io_uart_sel,
io_sstats_sel, io_7seg_sel, io_keys_sel, io_lcd_sel,
io_sdc_sel, io_dma_sel, not_waiting);
U_DATA_ADDR_DEC: ram_addr_decode
port map (rst, cpu_d_aVal, d_addr,data_aVal, dev_select_ram);
U_SDRAM_ADDR_DEC: sdram_addr_decode
port map (rst, cpu_d_aVal, d_addr,sdram_aVal, dev_select_sdram);
dev_select <= dev_select_io or dev_select_ram; -- or dev_select_sdram;
with dev_select select
cpu_data_inp <= d_cache_d_out when b"0001",
stdin_d_out when b"0100",
read_d_out when b"0101",
counter_d_out when b"0111",
fpu_d_out when b"1000",
uart_d_out when b"1001",
-- sstats_d_out when b"1010",
keybd_d_out when b"1100",
lcd_d_out when b"1101",
sdc_d_out when b"1110",
-- sdram_d_out when b"1110",
dma_d_out when b"1111",
(others => 'X') when others;
U_D_CACHE: d_cache
port map (rst, clk4x,
data_aVal, data_wait, wr,
d_addr, cpu_data, d_cache_d_out, cpu_xfer,
mem_d_sel, ram_rdy, mem_wr,
mem_addr, datram_inp, datram_out, mem_xfer,
cnt_d_ref, cnt_d_rd_hit, cnt_d_wr_hit, cnt_d_flush);
U_BUSFREE_DLY: FFD port map (clk, rst, '1', busFree, busFree_dly);
dma_grant <= busFree_dly and busReq;
ram_xfer <= dma_type when dma_grant = YES else mem_xfer;
ram_addr <= dma_addr when dma_grant = YES else mem_addr;
ram_wr <= dma_wr when dma_grant = YES else mem_wr;
ram_sel <= '0' when dma_grant = YES else mem_d_sel;
ram_inp <= dma_dout when dma_grant = YES else datram_out;
U_RAM: RAM generic map ("data.bin", "dump.data")
port map (rst, clk, ram_sel, ram_rdy, ram_wr, phi3,
ram_addr, ram_inp, datram_inp, ram_xfer, dump_ram);
-- U_RAM: RAM generic map ("data.bin", "dump.data")
-- port map (rst, clk, mem_d_sel, ram_rdy, mem_wr, phi2,
-- mem_addr, datram_out, datram_inp, mem_xfer, dump_ram);
-- busReq <= '0';
U_DISK: DISK
port map (rst,clk, phi1, io_dma_sel, open, wr, -- '1', open,
busFree, busReq, dma_grant,
d_addr(4 downto 2), cpu_data, dma_d_out, dma_irq,
dma_addr, datram_inp, dma_dout, dma_wr, dma_aval, dma_type);
U_SDRAMc: SDRAM_controller port map
(rst, clk, clk2x, sdram_aVal, sdram_wait, wr,
cpu_xfer, d_addr(25 downto 0), hDinp,hDout,
sdcke,sdscs,sdras,sdcas,sdwe,sddqm0,sddqm1,sdba0,sdba1,sdaddr,sddata);
sdcke <= '1';
U_to_stdout: to_stdout
port map (rst,clk, io_stdout_sel, wr, cpu_data);
U_from_stdin: from_stdin
port map (rst,clk, io_stdin_sel, wr, stdin_d_out);
U_read_inp: read_data_file generic map ("input.data")
port map (rst,clk, io_read_sel, wr, d_addr,read_d_out, cpu_xfer);
U_write_out: write_data_file generic map ("output.data")
port map (rst,clk, io_write_sel, wr, d_addr,cpu_data, cpu_xfer, dump_ram);
U_print_data: print_data
port map (rst,clk, io_print_sel, wr, cpu_data);
U_interrupt_counter: do_interrupt -- external counter+interrupt
port map (rst,clk, io_counter_sel, wr, cpu_data,
counter_d_out, counter_irq);
U_to_7seg: to_7seg
port map (rst,clk,io_7seg_sel, wr, cpu_data, disp0, disp1,
led_r, led_g, led_b);
key <= b"000000000000", b"000000000100" after 1 us, b"000000000000" after 2 us, b"001000000000" after 3 us, b"000000000000" after 4 us, b"000001000000" after 5 us, b"000000000000" after 6 us;
sw <= b"0000";
U_read_keys: read_keys
generic map (6) -- debouncing interval, in clock cycles
port map (rst,clk, io_keys_sel, keybd_d_out, key, sw);
U_LCD_display: LCD_display
port map (rst, clk, io_lcd_sel, io_lcd_wait,
wr, d_addr(2), cpu_data, lcd_d_out,
lcd_d, lcd_rs, lcd_rw, lcd_en, lcd_backlight);
U_simple_uart: simple_uart
port map (rst,clk, io_uart_sel, wr, d_addr(3 downto 2),
cpu_data, uart_d_out,
uart_txd, uart_rxd, uart_rts, uart_cts, uart_irq, bit_rt);
-- uncoment next line for loop back, comment out previous line
-- uart_txd, uart_txd, uart_rts, uart_cts, uart_irq, bit_rt);
uart_cts <= uart_rts;
U_uart_remota: remota generic map ("serial.out","serial.inp")
port map (rst, clk, uart_rts, uart_txd, uart_rxd, bit_rt);
U_sdcard: SDcard
port map (rst, clk, io_sdc_sel, io_sdc_wait,
wr, d_addr(3 downto 2), cpu_data, sdc_d_out,
sdc_cs, sdc_clk, sdc_mosi_o, sdc_miso_i, open);
U_FPU: FPU
port map (rst,clk, io_FPU_sel, io_FPU_wait, wr, d_addr(5 downto 2),
cpu_data, fpu_d_out);
-- U_sys_stats: sys_stats -- CPU reads system counters
-- port map (cpu_reset,clk, io_sstats_sel, wr, d_addr, sstats_d_out,
-- cnt_d_ref,cnt_d_rd_hit,cnt_d_wr_hit,cnt_d_flush,
-- cnt_i_ref,cnt_i_hit);
U_clock: process -- simulate external clock
begin
clock_50mhz <= '1';
clk2x <= '1';
wait for CLOCK_PER / 4;
clk2x <= '0';
wait for CLOCK_PER / 4;
clock_50mhz <= '0';
clk2x <= '1';
wait for CLOCK_PER / 4;
clk2x <= '0';
wait for CLOCK_PER / 4;
end process; -- -------------------------------------------------------
-- simulate reset switch bounces
a_reset <= '1', '0' after 5 ns, '1' after 8 ns, '0' after 12 ns, '1' after 14 ns, '0' after 18 ns, '1' after 25 ns;
end architecture TB;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- instruction address decoding
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
entity inst_addr_decode is -- CPU side triggers access
port (rst : in std_logic;
cpu_i_aVal : in std_logic; -- CPU instr addr valid (act=0)
addr : in reg32; -- CPU address
aVal : out std_logic; -- decoded address in range (act=0)
i_busError : out std_logic); -- decoded address not in range (act=0)
end entity inst_addr_decode;
architecture behavioral of inst_addr_decode is
constant HI_ADDR : integer := HI_SEL_BITS;
constant LO_ADDR : integer := log2_ceil(INST_BASE_ADDR + INST_MEM_SZ);
constant PREFIX : std_logic_vector(HI_ADDR downto LO_ADDR) := (others=>'0');
signal in_range : boolean;
begin
in_range <= (addr(HI_ADDR downto LO_ADDR) = PREFIX);
aVal <= '0' when ( cpu_i_aVal = '0' and in_range ) else
'1';
i_busError <= '0' when ( cpu_i_aVal = '0' and not(in_range) ) else
'1';
end architecture behavioral;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- RAM address decoding
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
entity ram_addr_decode is -- CPU side triggers access
port (rst : in std_logic;
cpu_d_aVal : in std_logic; -- CPU data addr valid (active=0)
addr : in reg32; -- CPU address
aVal : out std_logic; -- data address (act=0)
dev_select : out reg4); -- select input to CPU
constant LO_ADDR : integer := log2_ceil(DATA_BASE_ADDR);
constant HI_ADDR : integer := log2_ceil(DATA_BASE_ADDR + DATA_MEM_SZ - 1);
constant in_r : std_logic_vector(HI_ADDR downto LO_ADDR) := (others => '1');
constant ng_r : std_logic_vector(HI_ADDR downto LO_ADDR) := (others => '0');
constant oth : std_logic_vector(HI_SEL_BITS downto HI_ADDR+1):=(others=>'1');
constant ng_o : std_logic_vector(HI_SEL_BITS downto HI_ADDR+1):=(others=>'0');
end entity ram_addr_decode;
architecture behavioral of ram_addr_decode is
-- constant LO_ADDR : natural := log2_ceil(DATA_BASE_ADDR);
-- constant HI_ADDR : natural := log2_ceil(DATA_BASE_ADDR + DATA_MEM_SZ - 1);
constant all_0 : std_logic_vector(31 downto 0) := (others=>'0');
constant a_hi : std_logic_vector(31 downto HI_ADDR+1) := (others=>'0');
constant a_lo : std_logic_vector(LO_ADDR-1 downto 0) := (others=>'0');
constant a_bits : std_logic_vector(HI_ADDR downto LO_ADDR) := (others=>'1');
constant a_mask : std_logic_vector := a_hi & a_bits & a_lo;
constant LO_RAM : natural := 0;
constant HI_RAM : natural := log2_ceil(DATA_MEM_SZ-1);
constant r_hi : std_logic_vector(31 downto HI_RAM+1) := (others=>'1');
constant r_lo : std_logic_vector(HI_RAM downto LO_RAM) := (others=>'0');
constant r_mask : std_logic_vector := r_hi & r_lo;
signal in_range : boolean;
constant RAM_ADDR_BOTTOM : natural :=
to_integer(signed(x_DATA_BASE_ADDR(HI_SEL_BITS downto LO_SEL_BITS)));
constant RAM_ADDR_RANGE : natural :=
(to_integer(signed(x_DATA_BASE_ADDR(HI_SEL_BITS downto LO_SEL_BITS)))
+
to_integer(signed(x_DATA_MEM_SZ(HI_SEL_BITS downto LO_SEL_BITS))));
constant RAM_ADDR_TOP : natural := RAM_ADDR_BOTTOM + RAM_ADDR_RANGE;
begin
-- in_range <= ( rst = '1'
-- and ((addr and a_mask) = x_DATA_BASE_ADDR)
-- and ((addr and r_mask) = x_DATA_BASE_ADDR) );
-- this works only for small RAMS
-- in_range <= ( addr(HI_SEL_BITS downto LO_SEL_BITS)
-- =
-- x_DATA_BASE_ADDR(HI_SEL_BITS downto LO_SEL_BITS) );
-- this is ONLY acceptable for simulations;
-- computing these differences is TOO expensive for synthesis
in_range <= ( (to_integer(signed(addr(HI_SEL_BITS downto LO_SEL_BITS)))
>=
RAM_ADDR_BOTTOM)
and
(to_integer(signed(addr(HI_SEL_BITS downto LO_SEL_BITS)))
<
RAM_ADDR_TOP)
);
aVal <= '0' when (cpu_d_aVal = '0' and in_range) else '1';
dev_select <= b"0001" when (cpu_d_aVal = '0' and in_range) else b"0000";
assert TRUE -- cpu_d_aVal = '1'
report LF & "e " & SLV32HEX(addr) &
" addr " & SLV2str(addr(15 downto 0)) & LF &
" LO_AD " & integer'image(LO_ADDR) &
" HI_AD " & integer'image(HI_ADDR) &
" a_hi " & SLV2STR(a_hi) &
" a_lo " & SLV2STR(a_lo) &
" a_bits " & SLV2STR(a_bits) &
" a_mask " & SLV32HEX(a_mask) & LF &
" LO_RAM " & integer'image(LO_RAM) &
" HI_RAM " & integer'image(HI_RAM) &
" r_hi " & SLV2STR(r_hi) &
" r_lo " & SLV2STR(r_lo) &
" r_mask " & SLV32HEX(r_mask)
severity NOTE;
end architecture behavioral;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- busError address decoding
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
entity busError_addr_decode is -- CPU side triggers access
port (rst : in std_logic;
cpu_d_aVal : in std_logic; -- CPU data addr valid (active=0)
addr : in reg32; -- CPU address
d_busError : out std_logic); -- decoded address not in range (act=0)
end entity busError_addr_decode;
architecture behavioral of busError_addr_decode is
constant all_0 : std_logic_vector(31 downto 0) := (others=>'0');
-- I/O constants
constant IO_RANGE : integer := IO_ADDR_RANGE * IO_MAX_NUM_DEVS;
constant LO_DEV : natural := 0;
constant HI_DEV : natural := log2_ceil(IO_RANGE);
constant x_hi : std_logic_vector(31 downto HI_DEV) := (others=>'1');
constant x_lo : std_logic_vector(HI_DEV-1 downto 0) := (others=>'0');
constant x_mask : std_logic_vector := x_hi & x_lo; -- 1..10..0
-- RAM constants
constant LO_ADDR : natural := log2_ceil(DATA_BASE_ADDR);
constant HI_ADDR : natural := log2_ceil(DATA_BASE_ADDR + DATA_MEM_SZ - 1);
constant a_hi : std_logic_vector(31 downto HI_ADDR+1) := (others=>'0');
constant a_lo : std_logic_vector(LO_ADDR-1 downto 0) := (others=>'0');
constant a_bits : std_logic_vector(HI_ADDR downto LO_ADDR) := (others=>'1');
constant a_mask : std_logic_vector := a_hi & a_bits & a_lo; -- 0..0110..0
constant LO_RAM : natural := 0;
constant HI_RAM : natural := log2_ceil(DATA_MEM_SZ-1);
constant r_hi : std_logic_vector(31 downto HI_RAM) := (others=>'1');
constant r_lo : std_logic_vector(HI_RAM-1 downto LO_RAM) := (others=>'0');
constant r_mask : std_logic_vector := r_hi & r_lo; -- 1..10..0
signal in_range, io_in_range : boolean;
begin
in_range <= ( rst = '1' and
((addr and a_mask) = x_DATA_BASE_ADDR) and
((addr and r_mask) = x_DATA_BASE_ADDR) );
io_in_range <= ( (addr and x_mask) = x_IO_BASE_ADDR );
d_busError <= '0' when ( (cpu_d_aVal = '0') and
(not(in_range) and not(io_in_range)) ) else '1';
assert TRUE -- cpu_d_aVal = '1'
report LF & LF &
" e " & SLV32HEX(addr) &
" addr " & SLV2str(addr(HI_ADDR downto 0)) & LF &
" LO_AD " & integer'image(LO_ADDR) &
" HI_AD " & integer'image(HI_ADDR) &
" a_hi " & SLV2STR(a_hi) &
" a_lo " & SLV2STR(a_lo) &
" a_bits " & SLV2STR(a_bits) &
" a_mask " & SLV32HEX(a_mask) & LF &
" LO_RAM " & integer'image(LO_RAM) &
" HI_RAM " & integer'image(HI_RAM) &
" r_hi " & SLV2STR(r_hi) &
" r_lo " & SLV2STR(r_lo) &
" r_mask " & SLV32HEX(r_mask) & LF
severity NOTE;
assert TRUE -- cpu_d_aVal = '1' and io_busError
report LF &
" e " & SLV32HEX(addr) &
" addr " & SLV2str(addr(15 downto 0)) & LF &
" x_hi " & SLV2STR(x_hi) &
" x_lo " & SLV2STR(x_lo) &
" x_mask " & SLV32HEX(x_mask) & LF &
" LO_DEV " & integer'image(LO_DEV) &
" HI_DEV " & integer'image(HI_DEV)
severity NOTE;
end architecture behavioral;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- I/O address decoding
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
entity io_addr_decode is -- CPU side triggers access
port (rst : in std_logic;
clk : in std_logic; -- clk sparates back-to-back refs
cpu_d_aVal : in std_logic; -- CPU data addr valid (active=0)
addr : in reg32; -- CPU address
dev_select : out reg4; -- select input to CPU
print_sel : out std_logic; -- std_out (integer) (act=0)
stdout_sel : out std_logic; -- std_out (character) (act=0)
stdin_sel : out std_logic; -- std_inp (character) (act=0)
read_sel : out std_logic; -- file read (act=0)
write_sel : out std_logic; -- file write (act=0)
counter_sel : out std_logic; -- interrupt counter (act=0)
FPU_sel : out std_logic; -- floating point unit (act=0)
UART_sel : out std_logic; -- floating point unit (act=0)
SSTATS_sel : out std_logic; -- system statistics (act=0)
dsp7seg_sel : out std_logic; -- 7 segments display (act=0)
keybd_sel : out std_logic; -- telephone keyboard (act=0)
lcd_sel : out std_logic; -- LCD 2x16 char display (act=0)
sdc_sel : out std_logic; -- SDcard reader/writer (act=0)
dma_sel : out std_logic; -- DMA/disk controller (act=0)
not_waiting : in std_logic); -- no other device is waiting
end entity io_addr_decode;
architecture behavioral of io_addr_decode is
constant LO_SEL_ADDR : integer := log2_ceil(IO_ADDR_RANGE);
constant HI_SEL_ADDR : integer := LO_SEL_ADDR + log2_ceil(IO_ADDR_BITS);
constant IO_RANGE : integer := IO_ADDR_RANGE * IO_MAX_NUM_DEVS;
constant LO_ADDR : integer := log2_ceil(IO_BASE_ADDR);
constant HI_ADDR : integer := log2_ceil(IO_BASE_ADDR + IO_RANGE - 1);
constant in_r : std_logic_vector(HI_ADDR downto LO_ADDR) := (others => '1');
constant ng_r : std_logic_vector(HI_ADDR downto LO_ADDR) := (others => '0');
constant oth : std_logic_vector(HI_SEL_BITS downto HI_ADDR+1):=(others=>'1');
constant ng_o : std_logic_vector(HI_SEL_BITS downto HI_ADDR+1):=(others=>'0');
constant all_0 : std_logic_vector(31 downto 0) := (others=>'0');
-- I/O constants
constant LO_DEV : natural := 0;
constant HI_DEV : natural := log2_ceil(IO_RANGE-1);
constant x_hi : std_logic_vector(31 downto HI_DEV) := (others=>'1');
constant x_lo : std_logic_vector(HI_DEV-1 downto 0) := (others=>'0');
constant x_mask : std_logic_vector := x_hi & x_lo; -- 1..10..0
signal in_range : boolean;
signal aVal : std_logic;
signal dev : integer; -- DEBUGGING only
begin
-- in_range <= ((addr and x_mask) = x_IO_BASE_ADDR);
in_range <= ((addr(HI_ADDR downto LO_ADDR) and in_r) /= ng_r) and
((addr(HI_SEL_BITS downto HI_ADDR+1) and oth) = ng_o);
dev <= to_integer(signed(addr(IO_ADDR_BITS downto LO_SEL_ADDR)));
aVal <= '0' when ( cpu_d_aVal = '0' and not_waiting = '1' and
in_range ) else '1';
U_decode: process(clk, aVal, addr, dev)
variable dev_sel : reg4;
constant is_noise : integer := 0;
constant is_print : integer := 2;
constant is_stdout : integer := 3;
constant is_stdin : integer := 4;
constant is_read : integer := 5;
constant is_write : integer := 6;
constant is_count : integer := 7;
constant is_FPU : integer := 8;
constant is_UART : integer := 9;
constant is_SSTATS : integer := 10;
constant is_dsp7seg : integer := 11;
constant is_keybd : integer := 12;
constant is_lcd : integer := 13;
constant is_sdc : integer := 14;
constant is_dma : integer := 15;
begin
print_sel <= '1';
stdout_sel <= '1';
stdin_sel <= '1';
read_sel <= '1';
write_sel <= '1';
counter_sel <= '1';
FPU_sel <= '1';
UART_sel <= '1';
SSTATS_sel <= '1';
dsp7seg_sel <= '1';
keybd_sel <= '1';
lcd_sel <= '1';
sdc_sel <= '1';
dma_sel <= '1';
case dev is -- to_integer(signed(addr(HI_ADDR downto LO_ADDR))) is
when 0 => dev_sel := std_logic_vector(to_signed(is_print, 4));
print_sel <= aVal or clk;
when 1 => dev_sel := std_logic_vector(to_signed(is_stdout, 4));
stdout_sel <= aVal or clk;
when 2 => dev_sel := std_logic_vector(to_signed(is_stdin, 4));
stdin_sel <= aVal or clk;
when 3 => dev_sel := std_logic_vector(to_signed(is_read, 4));
read_sel <= aVal or clk;
when 4 => dev_sel := std_logic_vector(to_signed(is_write, 4));
write_sel <= aVal or clk;
when 5 => dev_sel := std_logic_vector(to_signed(is_count, 4));
counter_sel <= aVal or clk;
when 6 => dev_sel := std_logic_vector(to_signed(is_FPU, 4));
FPU_sel <= aVal;
when 7 => dev_sel := std_logic_vector(to_signed(is_UART, 4));
UART_sel <= aVal;
when 8 => dev_sel := std_logic_vector(to_signed(is_SSTATS, 4));
SSTATS_sel <= aVal;
when 9 => dev_sel := std_logic_vector(to_signed(is_dsp7seg, 4));
dsp7seg_sel <= aVal;
when 10 => dev_sel := std_logic_vector(to_signed(is_keybd, 4));
keybd_sel <= aVal;
when 11 => dev_sel := std_logic_vector(to_signed(is_lcd, 4));
lcd_sel <= aVal;
when 12 => dev_sel := std_logic_vector(to_signed(is_sdc, 4));
sdc_sel <= aVal;
when 13 => dev_sel := std_logic_vector(to_signed(is_dma, 4));
dma_sel <= aVal or clk;
when others => dev_sel := std_logic_vector(to_signed(is_noise, 4));
end case;
assert TRUE report "IO_addr "& SLV32HEX(addr); -- DEBUG
if aVal = '0' then
dev_select <= dev_sel;
else
dev_select <= std_logic_vector(to_signed(is_noise, 4));
end if;
end process U_decode;
end architecture behavioral;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- SDRAM address decoding
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
entity sdram_addr_decode is -- CPU side triggers access
port (rst : in std_logic;
cpu_d_aVal : in std_logic; -- CPU data addr valid (active=0)
addr : in reg32; -- CPU address
aVal : out std_logic; -- data address (act=0)
dev_select : out reg4); -- select input to CPU
constant LO_ADDR : integer := log2_ceil(SDRAM_BASE_ADDR);
constant HI_ADDR : integer := log2_ceil(SDRAM_BASE_ADDR + SDRAM_MEM_SZ - 1);
constant in_r : std_logic_vector(HI_ADDR downto LO_ADDR) := (others => '1');
constant ng_r : std_logic_vector(HI_ADDR downto LO_ADDR) := (others => '0');
constant oth : std_logic_vector(HI_SEL_BITS downto HI_ADDR+1):=(others=>'1');
constant ng_o : std_logic_vector(HI_SEL_BITS downto HI_ADDR+1):=(others=>'0');
end entity sdram_addr_decode;
architecture behavioral of sdram_addr_decode is
constant all_0 : std_logic_vector(31 downto 0) := (others=>'0');
constant a_hi : std_logic_vector(31 downto HI_ADDR+1) := (others=>'0');
constant a_lo : std_logic_vector(LO_ADDR-1 downto 0) := (others=>'0');
constant a_bits : std_logic_vector(HI_ADDR downto LO_ADDR) := (others=>'1');
constant a_mask : std_logic_vector := a_hi & a_bits & a_lo;
constant LO_RAM : natural := 0;
constant HI_RAM : natural := log2_ceil(SDRAM_MEM_SZ-1);
constant r_hi : std_logic_vector(31 downto HI_RAM+1) := (others=>'1');
constant r_lo : std_logic_vector(HI_RAM downto LO_RAM) := (others=>'0');
constant r_mask : std_logic_vector := r_hi & r_lo;
signal in_range : boolean;
constant SDRAM_ADDR_BOTTOM : natural :=
to_integer(signed(x_SDRAM_BASE_ADDR(HI_SEL_BITS downto LO_SEL_BITS)));
constant SDRAM_ADDR_RANGE : natural :=
(to_integer(signed(x_SDRAM_BASE_ADDR(HI_SEL_BITS downto LO_SEL_BITS)))
+
to_integer(signed(x_SDRAM_MEM_SZ(HI_SEL_BITS downto LO_SEL_BITS))));
constant SDRAM_ADDR_TOP : natural := SDRAM_ADDR_BOTTOM + SDRAM_ADDR_RANGE;
begin
-- this is ONLY acceptable for simulations;
-- computing these differences is TOO expensive for synthesis
in_range <= ( (to_integer(signed(addr(HI_SEL_BITS downto LO_SEL_BITS)))
>=
SDRAM_ADDR_BOTTOM)
and
(to_integer(signed(addr(HI_SEL_BITS downto LO_SEL_BITS)))
<
SDRAM_ADDR_TOP)
);
aVal <= '0' when (cpu_d_aVal = '0' and in_range) else '1';
dev_select <= b"1110" when (cpu_d_aVal = '0' and in_range) else b"0000";
assert TRUE -- cpu_d_aVal = '1'
report "e " & SLV32HEX(addr) &
" addr " & SLV2str(addr(15 downto 0)) & LF &
" LO_AD " & integer'image(LO_ADDR) &
" HI_AD " & integer'image(HI_ADDR) &
" a_hi " & SLV2STR(a_hi) &
" a_lo " & SLV2STR(a_lo) &
" a_bits " & SLV2STR(a_bits) &
" a_mask " & SLV32HEX(a_mask) & LF &
" LO_RAM " & integer'image(LO_RAM) &
" HI_RAM " & integer'image(HI_RAM) &
" r_hi " & SLV2STR(r_hi) &
" r_lo " & SLV2STR(r_lo) &
" r_mask " & SLV32HEX(r_mask)
severity NOTE;
end architecture behavioral;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
use work.all;
configuration CFG_TB of TB_CMIPS is
for TB
end for;
end configuration CFG_TB;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| gpl-3.0 | ed61966159616355a9d79a31c30619d5 | 0.5358 | 3.273129 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/6-FIR2/metaheurísticas/fir2_nsga2.vhd | 1 | 3,331 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-26.14:51:31)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY fir2_nsga2_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16: IN unsigned(0 TO 3);
output1: OUT unsigned(0 TO 4));
END fir2_nsga2_entity;
ARCHITECTURE fir2_nsga2_description OF fir2_nsga2_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := not input1 or input1;
register2 := not input2 or input2;
WHEN "00000010" =>
register1 := register2 + register1;
register2 := not input3 or input3;
WHEN "00000011" =>
register1 := register1 * 5;
register3 := not input4 or input4;
WHEN "00000100" =>
register2 := register2 + register3;
register3 := not input5 or input5;
register4 := not input6 or input6;
register5 := not input7 or input7;
WHEN "00000101" =>
register6 := not input8 or input8;
register3 := register5 + register3;
WHEN "00000110" =>
register4 := register6 + register4;
register5 := not input9 or input9;
register6 := not input10 or input10;
register7 := not input11 or input11;
register2 := register2 * 15;
WHEN "00000111" =>
register5 := register7 + register5;
register3 := register3 * 17;
WHEN "00001000" =>
register5 := register5 * 19;
register7 := not input12 or input12;
register8 := not input13 or input13;
register2 := register3 + register2;
WHEN "00001001" =>
register3 := register6 + register7;
register1 := register1 + register2;
register2 := not input14 or input14;
register4 := register4 * 24;
register6 := not input15 or input15;
WHEN "00001010" =>
register6 := register6 + register8;
register7 := not input16 or input16;
WHEN "00001011" =>
register2 := register2 + register7;
register3 := register3 * 28;
register6 := register6 * 30;
register1 := register5 + register1;
WHEN "00001100" =>
register2 := register2 * 32;
register1 := register6 + register1;
WHEN "00001101" =>
register1 := register3 + register1;
WHEN "00001110" =>
register1 := register2 + register1;
WHEN "00001111" =>
register1 := register4 + register1;
WHEN "00010000" =>
output1 <= to_unsigned(2 ** to_integer(register1), 4);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END fir2_nsga2_description; | gpl-3.0 | 8e2d5ff6023bbbe6209a8e17012eb5d9 | 0.668568 | 3.178435 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/msr_reg_gti.vhd | 1 | 32,545 | `protect begin_protected
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`protect end_protected
| apache-2.0 | 42b87f483e2060dae3170757f5f7fb9c | 0.945552 | 1.82909 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/carry_compare_mask.vhd | 1 | 11,644 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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`protect end_protected
| apache-2.0 | 717fa3d64aae2cb2e3cc6d8bff035d22 | 0.927173 | 1.881402 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/comparator.vhd | 1 | 12,832 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7760)
`protect data_block
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| apache-2.0 | fd9a745bbb21707c8d27a56c92d47c66 | 0.934383 | 1.888725 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/pselect.vhd | 15 | 12,532 | -------------------------------------------------------------------------------
-- $Id: pselect.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pselect.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pselect.vhd
--
-- Description: Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain. For version with AValid at top of
-- carry chain, see pselect_top.vhd.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pselect.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- BLT 2001-04-10 First Version
-- BLT 2001-04-23 Moved function to this file
-- BLT 2001-05-21 Changed library to MicroBlaze
-- BLT 2001-08-13 Changed pragma to synthesis
-- ALS 2001-10-15 C_BAR is now padded to nearest multiple of 4
-- to handle lut equations
-- FLO 2002-03-26 Corrected implementation for case where C_AB
-- is not a multiple of 4 and the C_BAR values
-- at the pad bits are not '0'.
-- Removed implementation restriction that
-- required C_AW = C_BAR'length.
-- Added assertion to flag invalid generic
-- combinations.
-- ALS, FLO 2002-04-09 -Implemented XST workaround for the case
-- that C_AB = 0.
-- -Removed remnants of earlier
-- "instantiated-lut" implementation.
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library unisim;
use unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect is
component MUXCY is
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MUXCY;
attribute INIT : string;
-----------------------------------------------------------------------------
-- Constant Declarations
-----------------------------------------------------------------------------
constant NUM_LUTS : integer := (C_AB+3)/4;
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
-----------------------------------------------------------------------------
-- Signal Declarations
-----------------------------------------------------------------------------
--signal lut_out : std_logic_vector(0 to NUM_LUTS-1);
signal lut_out : std_logic_vector(0 to NUM_LUTS); -- XST workaround
signal carry_chain : std_logic_vector(0 to NUM_LUTS);
-------------------------------------------------------------------------------
-- Begin architecture section
-------------------------------------------------------------------------------
begin
--------------------------------------------------------------------------------
-- Check that the passed generics allow for correct implementation.
--------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
--------------------------------------------------------------------------------
-- Build the decoder using the fast carry chain.
--------------------------------------------------------------------------------
carry_chain(0) <= AValid;
XST_WA: if NUM_LUTS > 0 generate -- workaround for XST; remove this
-- enclosing generate when fixed
GEN_DECODE: for i in 0 to NUM_LUTS-1 generate
signal lut_in : std_logic_vector(3 downto 0);
signal invert : std_logic_vector(3 downto 0);
begin
GEN_LUT_INPUTS: for j in 0 to 3 generate
-- Generate to assign address bits to LUT4 inputs
GEN_INPUT: if i < NUM_LUTS-1 or j <= ((C_AB-1) mod 4) generate
lut_in(j) <= A(i*4+j);
invert(j) <= not BAR(i*4+j);
end generate;
-- Generate to assign one to remaining LUT4, pad, inputs
GEN_ZEROS: if not(i < NUM_LUTS-1 or j <= ((C_AB-1) mod 4)) generate
lut_in(j) <= '1';
invert(j) <= '0';
end generate;
end generate;
---------------------------------------------------------------------------
-- RTL LUT instantiation
---------------------------------------------------------------------------
lut_out(i) <= (lut_in(0) xor invert(0)) and
(lut_in(1) xor invert(1)) and
(lut_in(2) xor invert(2)) and
(lut_in(3) xor invert(3));
MUXCY_I: MUXCY
port map (
O => carry_chain(i+1), --[out]
CI => carry_chain(i), --[in]
DI => '0', --[in]
S => lut_out(i) --[in]
);
end generate GEN_DECODE;
end generate XST_WA;
CS <= carry_chain(NUM_LUTS); -- assign end of carry chain to output;
-- if NUM_LUTS=0, then
-- CS <= carry_chain(0) <= AValid
end imp;
| apache-2.0 | e56357fd6d38b35018e2a0289361e631 | 0.399058 | 5.330498 | false | false | false | false |
sandrosalvato94/System-Design-Project | src/polito/sdp2017/Tests/IP_Adder.vhd | 2 | 4,116 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.CONSTANTS.all;
--&&&&&&&&&&&&&&&&&&&&&&&&& Behaviour of the IP ADDER &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
--Initialized to read row1 (where the CPU writes the first operand)
--One clock cylce after the enable is 1, we ask to read row2 (where the CPU writes the second operand)
--1 cc after, we receive the first operand that is stored
--1 cc after, we receive the second operand that can be added to the first one and sent to the IP manager
--1 cc after, the IP ADDER stops and the result is written in row3
entity IP_ADDER is
port (
clk : in std_logic;
rst : in std_logic;
data_in : out std_logic_vector(DATA_WIDTH-1 downto 0);
data_out : in std_logic_vector(DATA_WIDTH-1 downto 0);
address : out std_logic_vector(ADD_WIDTH-1 downto 0);
W_enable : out std_logic;
R_enable : out std_logic;
generic_en : out std_logic;
enable : in std_logic;
ack : in std_logic;
interrupt : out std_logic
);
end IP_ADDER;
architecture BEHAVIOURAL of IP_ADDER is
signal OP1 : std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
type state_type is (READ_OPERAND2, WRITE_OPERAND1, WRITE_RESULT, IDLE );
signal fsm_state: state_type;
begin
proc_fsm : process(clk,rst,enable)
begin
if rst = '1' then
-- asynchronous reset.
--In idle always ask to read the first operand
OP1 <= (others => '0');
data_in <= (others => '0');
address <= conv_std_logic_vector(1, ADD_WIDTH);
R_enable <= '1';
W_enable <= '0';
generic_en <= '1';
interrupt <= '0';
fsm_state <= READ_OPERAND2;
elsif (clk'event and clk = '0') then -- Working on falling edge
if enable = '1' then
case fsm_state is
when READ_OPERAND2 =>
-- Asking for the second operand, present in row 2 and
address <= conv_std_logic_vector(2, ADD_WIDTH); --address of the second operand
R_enable <= '1';
W_enable <= '0';
generic_en <= '1';
interrupt <= '0';
fsm_state <= WRITE_OPERAND1;
when WRITE_OPERAND1 =>
--Since there is a latency of 1 clock cycle from the read request now we can write OP1 the first operand.
--The reading of the row 1 is done in the reset/init states so that when the IP ADDER is enabled immediately asks for the first operand
OP1 <= data_out;
address <= (others => '0');
R_enable <= '0';
W_enable <= '0';
generic_en <= '0';
interrupt <= '0';
fsm_state <= WRITE_RESULT;
when WRITE_RESULT =>
-- Store the result in row 3. The second operand is in data_out
data_in <= OP1 + data_out; --ADDER
address <= conv_std_logic_vector(3, ADD_WIDTH);
R_enable <= '0';
W_enable <= '1';
generic_en <= '1';
interrupt <= '0';
fsm_state <= IDLE;
when IDLE =>
--In idle always ask to read the first operand
OP1 <= (others => '0');
data_in <= (others => '0');
address <= (others => '0');
R_enable <= '0';
W_enable <= '0';
generic_en <= '0';
interrupt <= '0';
fsm_state <= READ_OPERAND2;
when OTHERS =>
--In idle always ask to read the first operand
OP1 <= (others => '0');
data_in <= (others => '0');
address <= conv_std_logic_vector(1, ADD_WIDTH);
R_enable <= '1';
W_enable <= '0';
generic_en <= '1';
interrupt <= '0';
fsm_state <= READ_OPERAND2;
end case;
elsif enable = '0' then
--In idle always ask to read the first operand
OP1 <= (others => '0');
data_in <= (others => '0');
address <= conv_std_logic_vector(1, ADD_WIDTH);
R_enable <= '1';
W_enable <= '0';
generic_en <= '1';
interrupt <= '0';
fsm_state <= READ_OPERAND2;
end if;
end if;
end process;
end architecture BEHAVIOURAL; | lgpl-3.0 | 65920641bbb65e5f99d506d6c3ebd954 | 0.555637 | 3.037638 | false | false | false | false |
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`protect end_protected
| apache-2.0 | cdd21795488b0140ae4bbfad277d0eaf | 0.936119 | 1.886146 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/ipif_pkg.vhd | 15 | 53,612 | -------------------------------------------------------------------------------
-- $Id: ipif_pkg.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- IPIF Common Library Package
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
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-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ipif_pkg.vhd
-- Version: Intital
-- Description: This file contains the constants and functions used in the
-- ipif common library components.
--
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: DET
-- History:
-- DET 02/21/02 -- Created from proc_common_pkg.vhd
--
-- DET 03/13/02 -- PLB IPIF development updates
-- ^^^^^^
-- - Commented out string types and string functions due to an XST
-- problem with string arrays and functions. THe string array
-- processing functions were replaced with comperable functions
-- operating on integer arrays.
-- ~~~~~~
--
--
-- DET 4/30/2002 Initial
-- ~~~~~~
-- - Added three functions: rebuild_slv32_array, rebuild_slv64_array, and
-- rebuild_int_array to support removal of unused elements from the
-- ARD arrays.
-- ^^^^^^ --
--
-- FLO 8/12/2002
-- ~~~~~~
-- - Added three functions: bits_needed_for_vac, bits_needed_for_occ,
-- and get_id_index_iboe.
-- (Removed provisional functions bits_needed_for_vacancy,
-- bits needed_for_occupancy, and bits_needed_for.)
-- ^^^^^^
--
-- FLO 3/24/2003
-- ~~~~~~
-- - Added dependent property paramters for channelized DMA.
-- - Added common property parameter array type.
-- - Definded the KEYHOLD_BURST common-property parameter.
-- ^^^^^^
--
-- FLO 10/22/2003
-- ~~~~~~
-- - Some adjustment to CHDMA parameterization.
-- - Cleanup of obsolete code and comments. (The former "XST workaround"
-- has become the officially deployed method.)
-- ^^^^^^
--
-- LSS 03/24/2004
-- ~~~~~~
-- - Added 5 functions
-- ^^^^^^
--
-- ALS 09/03/04
-- ^^^^^^
-- -- Added constants to describe the channel protocols used in MCH_OPB_IPIF
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- need conversion function to convert reals/integers to std logic vectors
use ieee.std_logic_arith.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package ipif_pkg is
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
type SLV32_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 31);
subtype SLV64_TYPE is std_logic_vector(0 to 63);
type SLV64_ARRAY_TYPE is array (natural range <>) of SLV64_TYPE;
type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
-------------------------------------------------------------------------------
-- Function and Procedure Declarations
-------------------------------------------------------------------------------
function "=" (s1: in string; s2: in string) return boolean;
function equaluseCase( str1, str2 : STRING ) RETURN BOOLEAN;
function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer;
function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
index : integer) return integer;
function get_min_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer;
function get_max_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer;
function S32 (in_string : string) return string;
--------------------------------------------------------------------------------
-- ARD support functions.
-- These function can be useful when operating with the ARD parameterization.
--------------------------------------------------------------------------------
function get_id_index (id_array :INTEGER_ARRAY_TYPE;
id : integer)
return integer;
function get_id_index_iboe (id_array :INTEGER_ARRAY_TYPE;
id : integer)
return integer;
function find_ard_id (id_array : INTEGER_ARRAY_TYPE;
id : integer) return boolean;
function find_id_dwidth (id_array : INTEGER_ARRAY_TYPE;
dwidth_array: INTEGER_ARRAY_TYPE;
id : integer;
default : integer)
return integer;
function cnt_ipif_id_blks (id_array : INTEGER_ARRAY_TYPE) return integer;
function get_ipif_id_dbus_index (id_array : INTEGER_ARRAY_TYPE;
id : integer)
return integer ;
function rebuild_slv32_array (slv32_array : SLV32_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV32_ARRAY_TYPE;
function rebuild_slv64_array (slv64_array : SLV64_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV64_ARRAY_TYPE;
function rebuild_int_array (int_array : INTEGER_ARRAY_TYPE;
num_valid_entry : integer)
return INTEGER_ARRAY_TYPE;
-- 5 Functions Added 3/24/04
function populate_intr_mode_array (num_user_intr : integer;
intr_capture_mode : integer)
return INTEGER_ARRAY_TYPE ;
function add_intr_ard_id_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE;
function add_intr_ard_addr_range_array(include_intr : boolean;
ZERO_ADDR_PAD : std_logic_vector;
intr_baseaddr : std_logic_vector;
intr_highaddr : std_logic_vector;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_addr_range_array : SLV64_ARRAY_TYPE)
return SLV64_ARRAY_TYPE;
function add_intr_ard_num_ce_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_num_ce_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE;
function add_intr_ard_dwidth_array(include_intr : boolean;
intr_dwidth : integer;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_dwidth_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Channel Protocols
-- The constant declarations below give symbolic-name aliases for values that
-- can be used in the C_MCH_PROTOCOL_ARRAY generic of the MCH_OPB_IPIF.
-------------------------------------------------------------------------------
constant XCL : integer := 0;
constant DAG : integer := 1;
--------------------------------------------------------------------------------
-- Address range types.
-- The constant declarations, below, give symbolic-name aliases for values
-- that can be used in the C_ARD_ID_ARRAY generic of IPIFs. The first set
-- gives aliases that are used to include IPIF services.
--------------------------------------------------------------------------------
-- IPIF module aliases
Constant IPIF_INTR : integer := 1;
Constant IPIF_RST : integer := 2;
Constant IPIF_SESR_SEAR : integer := 3;
Constant IPIF_DMA_SG : integer := 4;
Constant IPIF_WRFIFO_REG : integer := 5;
Constant IPIF_WRFIFO_DATA : integer := 6;
Constant IPIF_RDFIFO_REG : integer := 7;
Constant IPIF_RDFIFO_DATA : integer := 8;
Constant IPIF_CHDMA_CHANNELS : integer := 9;
Constant IPIF_CHDMA_GLOBAL_REGS : integer := 10;
Constant CHDMA_STATUS_FIFO : integer := 90;
-- Some predefined user module aliases
Constant USER_00 : integer := 100;
Constant USER_01 : integer := 101;
Constant USER_02 : integer := 102;
Constant USER_03 : integer := 103;
Constant USER_04 : integer := 104;
Constant USER_05 : integer := 105;
Constant USER_06 : integer := 106;
Constant USER_07 : integer := 107;
Constant USER_08 : integer := 108;
Constant USER_09 : integer := 109;
Constant USER_10 : integer := 110;
Constant USER_11 : integer := 111;
Constant USER_12 : integer := 112;
Constant USER_13 : integer := 113;
Constant USER_14 : integer := 114;
Constant USER_15 : integer := 115;
Constant USER_16 : integer := 116;
---( Start of Dependent Properties declarations
--------------------------------------------------------------------------------
-- Declarations for Dependent Properties (properties that depend on the type of
-- the address range, or in other words, address-range-specific parameters).
-- There is one property, i.e. one parameter, encoded as an integer at
-- each index of the properties array. There is one properties array for
-- each address range.
--
-- The C_ARD_DEPENDENT_PROPS_ARRAY generic parameter in (most) IPIFs is such
-- a properties array and it is usually giving its (static) value using a
-- VHDL aggregate construct. (--ToDo, give an example of this.)
--
-- The the "assigned" default value of a dependent property is zero. This value
-- is usually specified the aggregate by leaving its (index) name out so that
-- it is covered by an "others => 0" choice in the aggregate. Some parameters,
-- as noted in the definitions, below, have an "effective" default value that is
-- different from the assigned default value of zero. In such cases, the
-- function, eff_dp, given below, can be used to get the effective value of
-- the dependent property.
--------------------------------------------------------------------------------
constant DEPENDENT_PROPS_SIZE : integer := 32;
subtype DEPENDENT_PROPS_TYPE
is INTEGER_ARRAY_TYPE(0 to DEPENDENT_PROPS_SIZE-1);
type DEPENDENT_PROPS_ARRAY_TYPE
is array (natural range <>) of DEPENDENT_PROPS_TYPE;
--------------------------------------------------------------------------------
-- Below are the indices of dependent properties for the different types of
-- address ranges.
--
-- Example: Let C_ARD_DEPENDENT_PROPS_ARRAY hold the dependent properites
-- for a set of address ranges. Then, e.g.,
--
-- C_ARD_DEPENDENT_PROPS_ARRAY(i)(FIFO_CAPACITY_BITS)
--
-- gives the fifo capacity in bits, provided that the i'th address range
-- is of type IPIF_WRFIFO_DATA or IPIF_RDFIFO_DATA.
--
-- These indices should be referenced only by the names below and never
-- by numerical literals. (The right to change numerical index assignments
-- is reserved; applications using the names will not be affected by such
-- reassignments.)
--------------------------------------------------------------------------------
--
--ToDo, if the interrupt controller parameterization is ever moved to
-- C_ARD_DEPENDENT_PROPS_ARRAY, then the following declarations
-- could be uncommented and used.
---- IPIF_INTR IDX
---------------------------------------------------------------------------- ---
constant EXCLUDE_DEV_ISC : integer := 0;
-- 1 specifies that only the global interrupt
-- enable is present in the device interrupt source
-- controller and that the only source of interrupts
-- in the device is the IP interrupt source controller.
-- 0 specifies that the full device interrupt
-- source controller structure will be included.
constant INCLUDE_DEV_PENCODER : integer := 1;
-- 1 will include the Device IID in the device interrupt
-- source controller, 0 will exclude it.
--
-- IPIF_WRFIFO_DATA or IPIF_RDFIFO_DATA IDX
---------------------------------------------------------------------------- ---
constant FIFO_CAPACITY_BITS : integer := 0;
constant WR_WIDTH_BITS : integer := 1;
constant RD_WIDTH_BITS : integer := 2;
constant EXCLUDE_PACKET_MODE : integer := 3;
-- 1 Don't include packet mode features
-- 0 Include packet mode features
constant EXCLUDE_VACANCY : integer := 4;
-- 1 Don't include vacancy calculation
-- 0 Include vacancy calculation
-- See also the functions
-- bits_needed_for_vac and
-- bits_needed_for_occ that are declared below.
constant INCLUDE_DRE : integer := 5;
constant INCLUDE_AUTOPUSH_POP : integer := 6;
constant AUTOPUSH_POP_CE : integer := 7;
constant INCLUDE_CSUM : integer := 8;
--------------------------------------------------------------------------------
--
-- DMA_SG IDX
---------------------------------------------------------------------------- ---
--------------------------------------------------------------------------------
-- IPIF_CHDMA_CHANNELS IDX
---------------------------------------------------------------------------- ---
constant NUM_SUBS_FOR_PHYS_0 : integer :=0;
constant NUM_SUBS_FOR_PHYS_1 : integer :=1;
constant NUM_SUBS_FOR_PHYS_2 : integer :=2;
constant NUM_SUBS_FOR_PHYS_3 : integer :=3;
constant NUM_SUBS_FOR_PHYS_4 : integer :=4;
constant NUM_SUBS_FOR_PHYS_5 : integer :=5;
constant NUM_SUBS_FOR_PHYS_6 : integer :=6;
constant NUM_SUBS_FOR_PHYS_7 : integer :=7;
constant NUM_SUBS_FOR_PHYS_8 : integer :=8;
constant NUM_SUBS_FOR_PHYS_9 : integer :=9;
constant NUM_SUBS_FOR_PHYS_10 : integer :=10;
constant NUM_SUBS_FOR_PHYS_11 : integer :=11;
constant NUM_SUBS_FOR_PHYS_12 : integer :=12;
constant NUM_SUBS_FOR_PHYS_13 : integer :=13;
constant NUM_SUBS_FOR_PHYS_14 : integer :=14;
constant NUM_SUBS_FOR_PHYS_15 : integer :=15;
-- Gives the number of sub-channels for physical channel i.
--
-- These constants, which will be MAX_NUM_PHYS_CHANNELS in number (see
-- below), have consecutive values starting with 0 for
-- NUM_SUBS_FOR_PHYS_0. (The constants serve the purpose of giving symbolic
-- names for use in the dependent-properties aggregates that parameterize
-- an IPIF_CHDMA_CHANNELS address range.)
--
-- [Users can ignore this note for developers
-- If the number of physical channels changes, both the
-- IPIF_CHDMA_CHANNELS constants and MAX_NUM_PHYS_CHANNELS,
-- below, must be adjusted.
-- (Use of an array constant or a function of the form
-- NUM_SUBS_FOR_PHYS(i) to define the indices
-- runs afoul of LRM restrictions on non-locally static aggregate
-- choices. (Further, the LRM imposes perhaps unnecessarily
-- strict limits on what qualifies as a locally static primary.)
-- Note: This information is supplied for the benefit of anyone seeking
-- to improve the way that these NUM_SUBS_FOR_PHYS parameter
-- indices are defined.)
-- End of note for developers ]
--
-- The value associated with any index NUM_SUBS_FOR_PHYS_i in the
-- dependent-properties array must be even since TX and RX channels
-- come in pairs with the TX followed immediately by
-- the corresponding RX.
--
constant NUM_SIMPLE_DMA_CHANS : integer :=16;
-- The number of simple DMA channels.
constant NUM_SIMPLE_SG_CHANS : integer :=17;
-- The number of simple SG channels.
constant INTR_COALESCE : integer :=18;
-- 0 Interrupt coalescing is disabled
-- 1 Interrupt coalescing is enabled
constant CLK_PERIOD_PS : integer :=19;
-- The period of the OPB Bus clock in ps.
-- The default value of 0 is a special value that
-- is synonymous with 10000 ps (10 ns).
-- The value for CLK_PERIOD_PS is relevant only if (INTR_COALESCE = 1).
constant PACKET_WAIT_UNIT_NS : integer :=20;
-- Gives the unit for used for timing of pack-wait bounds.
-- The default value of 0 is a special value that
-- is synonymous with 1,000,000 ns (1 ms) and a non-default
-- value is typically only used for testing.
-- Relevant only if (INTR_COALESCE = 1).
constant BURST_SIZE : integer :=21;
-- 1, 2, 4, 8 or 16
-- The default value of 0 is a special value that
-- is synonymous with a burst size of 16.
-- Setting the BURST_SIZE to 1 effectively disables
-- bursts.
constant REMAINDER_AS_SINGLES : integer :=22;
-- 0 Remainder handled as a short burst
-- 1 Remainder handled as a series of singles
--------------------------------------------------------------------------------
-- The constant below is not the index of a dependent-properties
-- parameter (and, as such, would never appear as a choice in a
-- dependent-properties aggregate). Rather, it is fixed to the maximum
-- number of physical channels that an Address Range of type
-- IPIF_CHDMA_CHANNELS supports. It must be maintained in conjuction with
-- the constants named, e.g., NUM_SUBS_FOR_PHYS_15, above.
--------------------------------------------------------------------------------
constant MAX_NUM_PHYS_CHANNELS : natural := 16;
--------------------------------------------------------------------------
-- EXAMPLE: Here is an example dependent-properties aggregate for an
-- address range of type IPIF_CHDMA_CHANNELS.
-- To have a compact list of all of the CHDMA parameters, all are
-- shown, however three are commented out and the unneeded
-- MUM_SUBS_FOR_PHYS_x are excluded. The "OTHERS => 0" association
-- gives these parameters their default values, such that, for the example
--
-- - All physical channels above 2 have zero subchannels (effectively,
-- these physical channels are not used)
-- - There are no simple SG channels
-- - The packet-wait time unit is 1 ms
-- - Burst size is 16
--------------------------------------------------------------------------
-- (
-- NUM_SUBS_FOR_PHYS_0 => 8,
-- NUM_SUBS_FOR_PHYS_1 => 4,
-- NUM_SUBS_FOR_PHYS_2 => 14,
-- NUM_SIMPLE_DMA_CHANS => 1,
-- --NUM_SIMPLE_SG_CHANS => 5,
-- INTR_COALESCE => 1,
-- CLK_PERIOD_PS => 20000,
-- --PACKET_WAIT_UNIT_NS => 50000,
-- --BURST_SIZE => 1,
-- REMAINDER_AS_SINGLES => 1,
-- OTHERS => 0
-- )
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Calculates the number of bits needed to convey the vacancy (emptiness) of
-- the fifo described by dependent_props, if fifo_present. If not fifo_present,
-- returns 0 (or the smallest value allowed by tool limitations on null arrays)
-- without making reference to dependent_props.
--------------------------------------------------------------------------------
function bits_needed_for_vac(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer;
--------------------------------------------------------------------------------
-- Calculates the number of bits needed to convey the occupancy (fullness) of
-- the fifo described by dependent_props, if fifo_present. If not fifo_present,
-- returns 0 (or the smallest value allowed by tool limitations on null arrays)
-- without making reference to dependent_props.
--------------------------------------------------------------------------------
function bits_needed_for_occ(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer;
--------------------------------------------------------------------------------
-- Function eff_dp.
--
-- For some of the dependent properties, the default value of zero is meant
-- to imply an effective default value of other than zero (see e.g.
-- PKT_WAIT_UNIT_NS for the IPIF_CHDMA_CHANNELS address-range type). The
-- following function is used to get the (possibly default-adjusted)
-- value for a dependent property.
--
-- Example call:
--
-- eff_value_of_param :=
-- eff_dp(
-- C_IPIF_CHDMA_CHANNELS,
-- PACKET_WAIT_UNIT_NS,
-- C_ARD_DEPENDENT_PROPS_ARRAY(i)(PACKET_WAIT_UNIT_NS)
-- );
--
-- where C_ARD_DEPENDENT_PROPS_ARRAY(i) is an object of type
-- DEPENDENT_PROPS_ARRAY_TYPE, that was parameterized for an address range of
-- type C_IPIF_CHDMA_CHANNELS.
--------------------------------------------------------------------------------
function eff_dp(id : integer; -- The type of address range.
dep_prop : integer; -- The index of the dependent prop.
value : integer -- The value at that index.
) return integer; -- The effective value, possibly adjusted
-- if value has the default value of 0.
---) End of Dependent Properties declarations
--------------------------------------------------------------------------------
-- Declarations for Common Properties (properties that apply regardless of the
-- type of the address range). Structurally, these work the same as
-- the dependent properties.
--------------------------------------------------------------------------------
constant COMMON_PROPS_SIZE : integer := 2;
subtype COMMON_PROPS_TYPE
is INTEGER_ARRAY_TYPE(0 to COMMON_PROPS_SIZE-1);
type COMMON_PROPS_ARRAY_TYPE
is array (natural range <>) of COMMON_PROPS_TYPE;
--------------------------------------------------------------------------------
-- Below are the indices of the common properties.
--
-- These indices should be referenced only by the names below and never
-- by numerical literals.
-- IDX
---------------------------------------------------------------------------- ---
constant KEYHOLE_BURST : integer := 0;
-- 1 All addresses of a burst are forced to the initial
-- address of the burst.
-- 0 Burst addresses follow the bus protocol.
-- IP interrupt mode array constants
Constant INTR_PASS_THRU : integer := 1;
Constant INTR_PASS_THRU_INV : integer := 2;
Constant INTR_REG_EVENT : integer := 3;
Constant INTR_REG_EVENT_INV : integer := 4;
Constant INTR_POS_EDGE_DETECT : integer := 5;
Constant INTR_NEG_EDGE_DETECT : integer := 6;
end ipif_pkg;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.log2;
package body ipif_pkg is
-------------------------------------------------------------------------------
-- Function Definitions
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Function "="
--
-- This function can be used to overload the "=" operator when comparing
-- strings.
-----------------------------------------------------------------------------
function "=" (s1: in string; s2: in string) return boolean is
constant tc: character := ' '; -- string termination character
variable i: integer := 1;
variable v1 : string(1 to s1'length) := s1;
variable v2 : string(1 to s2'length) := s2;
begin
while (i <= v1'length) and (v1(i) /= tc) and
(i <= v2'length) and (v2(i) /= tc) and
(v1(i) = v2(i))
loop
i := i+1;
end loop;
return ((i > v1'length) or (v1(i) = tc)) and
((i > v2'length) or (v2(i) = tc));
end;
----------------------------------------------------------------------------
-- Function equaluseCase
--
-- This function returns true if case sensitive string comparison determines
-- that str1 and str2 are the same.
-----------------------------------------------------------------------------
FUNCTION equaluseCase( str1, str2 : STRING ) RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str1'range LOOP
IF NOT (str1(i) = str2(i)) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
RETURN equal;
END equaluseCase;
-----------------------------------------------------------------------------
-- Function calc_num_ce
--
-- This function is used to process the array specifying the number of Chip
-- Enables required for a Base Address specification. The array is input to
-- the function and an integer is returned reflecting the total number of
-- Chip Enables required for the CE, RdCE, and WrCE Buses
-----------------------------------------------------------------------------
function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer is
Variable ce_num_sum : integer := 0;
begin
for i in 0 to (ce_num_array'length)-1 loop
ce_num_sum := ce_num_sum + ce_num_array(i);
End loop;
return(ce_num_sum);
end function calc_num_ce;
-----------------------------------------------------------------------------
-- Function calc_start_ce_index
--
-- This function is used to process the array specifying the number of Chip
-- Enables required for a Base Address specification. The CE Size array is
-- input to the function and an integer index representing the index of the
-- target module in the ce_num_array. An integer is returned reflecting the
-- starting index of the assigned Chip Enables within the CE, RdCE, and
-- WrCE Buses.
-----------------------------------------------------------------------------
function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
index : integer) return integer is
Variable ce_num_sum : integer := 0;
begin
If (index = 0) Then
ce_num_sum := 0;
else
for i in 0 to index-1 loop
ce_num_sum := ce_num_sum + ce_num_array(i);
End loop;
End if;
return(ce_num_sum);
end function calc_start_ce_index;
-----------------------------------------------------------------------------
-- Function get_min_dwidth
--
-- This function is used to process the array specifying the data bus width
-- for each of the target modules. The dwidth_array is input to the function
-- and an integer is returned that is the smallest value found of all the
-- entries in the array.
-----------------------------------------------------------------------------
function get_min_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer is
Variable temp_min : Integer := 1024;
begin
for i in 0 to dwidth_array'length-1 loop
If (dwidth_array(i) < temp_min) Then
temp_min := dwidth_array(i);
else
null;
End if;
End loop;
return(temp_min);
end function get_min_dwidth;
-----------------------------------------------------------------------------
-- Function get_max_dwidth
--
-- This function is used to process the array specifying the data bus width
-- for each of the target modules. The dwidth_array is input to the function
-- and an integer is returned that is the largest value found of all the
-- entries in the array.
-----------------------------------------------------------------------------
function get_max_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer is
Variable temp_max : Integer := 0;
begin
for i in 0 to dwidth_array'length-1 loop
If (dwidth_array(i) > temp_max) Then
temp_max := dwidth_array(i);
else
null;
End if;
End loop;
return(temp_max);
end function get_max_dwidth;
-----------------------------------------------------------------------------
-- Function S32
--
-- This function is used to expand an input string to 32 characters by
-- padding with spaces. If the input string is larger than 32 characters,
-- it will truncate to 32 characters.
-----------------------------------------------------------------------------
function S32 (in_string : string) return string is
constant OUTPUT_STRING_LENGTH : integer := 32;
Constant space : character := ' ';
variable new_string : string(1 to 32);
Variable start_index : Integer := in_string'length+1;
begin
If (in_string'length < OUTPUT_STRING_LENGTH) Then
for i in 1 to in_string'length loop
new_string(i) := in_string(i);
End loop;
for j in start_index to OUTPUT_STRING_LENGTH loop
new_string(j) := space;
End loop;
else -- use first 32 chars of in_string (truncate the rest)
for k in 1 to OUTPUT_STRING_LENGTH loop
new_string(k) := in_string(k);
End loop;
End if;
return(new_string);
end function S32;
-----------------------------------------------------------------------------
-- Function get_id_index
--
-- This function is used to process the array specifying the target function
-- assigned to a Base Address pair address range. The id_array and a
-- id number is input to the function. A integer is returned reflecting the
-- array index of the id matching the id input number. This function
-- should only be called if the id number is known to exist in the
-- name_array input. This can be detirmined by using the find_ard_id
-- function.
-----------------------------------------------------------------------------
function get_id_index (id_array :INTEGER_ARRAY_TYPE;
id : integer) return integer is
Variable match : Boolean := false;
Variable match_index : Integer := 10000; -- a really big number!
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
If (match) Then
match_index := array_index;
else
null;
End if;
End if;
End loop;
return(match_index);
end function get_id_index;
--------------------------------------------------------------------------------
-- get_id_index but return a value in bounds on error (iboe).
--
-- This function is the same as get_id_index, except that when id does
-- not exist in id_array, the value returned is any index that is
-- within the index range of id_array.
--
-- This function would normally only be used where function find_ard_id
-- is used to establish the existence of id but, even when non-existent,
-- an element of one of the ARD arrays will be computed from the
-- returned get_id_index_iboe value. See, e.g., function bits_needed_for_vac
-- and the example call, below
--
-- bits_needed_for_vac(
-- find_ard_id(C_ARD_ID_ARRAY, IPIF_RDFIFO_DATA),
-- C_ARD_DEPENDENT_PROPS_ARRAY(get_id_index_iboe(C_ARD_ID_ARRAY,
-- IPIF_RDFIFO_DATA))
-- )
--------------------------------------------------------------------------------
function get_id_index_iboe (id_array :INTEGER_ARRAY_TYPE;
id : integer) return integer is
Variable match : Boolean := false;
Variable match_index : Integer := id_array'left; -- any valid array index
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
If (match) Then match_index := array_index;
else null;
End if;
End if;
End loop;
return(match_index);
end function get_id_index_iboe;
-----------------------------------------------------------------------------
-- Function find_ard_id
--
-- This function is used to process the array specifying the target function
-- assigned to a Base Address pair address range. The id_array and a
-- integer id is input to the function. A boolean is returned reflecting the
-- presence (or not) of a number in the array matching the id input number.
-----------------------------------------------------------------------------
function find_ard_id (id_array : INTEGER_ARRAY_TYPE;
id : integer) return boolean is
Variable match : Boolean := false;
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
End if;
End loop;
return(match);
end function find_ard_id;
-----------------------------------------------------------------------------
-- Function find_id_dwidth
--
-- This function is used to find the data width of a target module. If the
-- target module exists, the data width is extracted from the input dwidth
-- array. If the module is not in the ID array, the default input is
-- returned. This function is needed to assign data port size constraints on
-- unconstrained port widths.
-----------------------------------------------------------------------------
function find_id_dwidth (id_array : INTEGER_ARRAY_TYPE;
dwidth_array: INTEGER_ARRAY_TYPE;
id : integer;
default : integer) return integer is
Variable id_present : Boolean := false;
Variable array_index : Integer := 0;
Variable dwidth : Integer := default;
begin
id_present := find_ard_id(id_array, id);
If (id_present) Then
array_index := get_id_index (id_array, id);
dwidth := dwidth_array(array_index);
else
null; -- use default input
End if;
Return (dwidth);
end function find_id_dwidth;
-----------------------------------------------------------------------------
-- Function cnt_ipif_id_blks
--
-- This function is used to detirmine the number of IPIF components specified
-- in the ARD ID Array. An integer is returned representing the number
-- of elements counted. User IDs are ignored in the counting process.
-----------------------------------------------------------------------------
function cnt_ipif_id_blks (id_array : INTEGER_ARRAY_TYPE)
return integer is
Variable blk_count : integer := 0;
Variable temp_id : integer;
begin
for array_index in 0 to id_array'length-1 loop
temp_id := id_array(array_index);
If (temp_id = IPIF_WRFIFO_DATA or
temp_id = IPIF_RDFIFO_DATA or
temp_id = IPIF_RST or
temp_id = IPIF_INTR or
temp_id = IPIF_DMA_SG or
temp_id = IPIF_SESR_SEAR
) Then -- IPIF block found
blk_count := blk_count+1;
else -- go to next loop iteration
null;
End if;
End loop;
return(blk_count);
end function cnt_ipif_id_blks;
-----------------------------------------------------------------------------
-- Function get_ipif_id_dbus_index
--
-- This function is used to detirmine the IPIF relative index of a given
-- ID value. User IDs are ignored in the index detirmination.
-----------------------------------------------------------------------------
function get_ipif_id_dbus_index (id_array : INTEGER_ARRAY_TYPE;
id : integer)
return integer is
Variable blk_index : integer := 0;
Variable temp_id : integer;
Variable id_found : Boolean := false;
begin
for array_index in 0 to id_array'length-1 loop
temp_id := id_array(array_index);
If (id_found) then
null;
elsif (temp_id = id) then
id_found := true;
elsif (temp_id = IPIF_WRFIFO_DATA or
temp_id = IPIF_RDFIFO_DATA or
temp_id = IPIF_RST or
temp_id = IPIF_INTR or
temp_id = IPIF_DMA_SG or
temp_id = IPIF_SESR_SEAR
) Then -- IPIF block found
blk_index := blk_index+1;
else -- user block so do nothing
null;
End if;
End loop;
return(blk_index);
end function get_ipif_id_dbus_index;
------------------------------------------------------------------------------
-- Function: rebuild_slv32_array
--
-- Description:
-- This function takes an input slv32 array and rebuilds an output slv32
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_slv32_array (slv32_array : SLV32_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV32_ARRAY_TYPE is
--Constants
constant num_elements : Integer := num_valid_pairs * 2;
-- Variables
variable temp_baseaddr32_array : SLV32_ARRAY_TYPE( 0 to num_elements-1);
begin
for array_index in 0 to num_elements-1 loop
temp_baseaddr32_array(array_index) := slv32_array(array_index);
end loop;
return(temp_baseaddr32_array);
end function rebuild_slv32_array;
------------------------------------------------------------------------------
-- Function: rebuild_slv64_array
--
-- Description:
-- This function takes an input slv64 array and rebuilds an output slv64
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_slv64_array (slv64_array : SLV64_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV64_ARRAY_TYPE is
--Constants
constant num_elements : Integer := num_valid_pairs * 2;
-- Variables
variable temp_baseaddr64_array : SLV64_ARRAY_TYPE( 0 to num_elements-1);
begin
for array_index in 0 to num_elements-1 loop
temp_baseaddr64_array(array_index) := slv64_array(array_index);
end loop;
return(temp_baseaddr64_array);
end function rebuild_slv64_array;
------------------------------------------------------------------------------
-- Function: rebuild_int_array
--
-- Description:
-- This function takes an input integer array and rebuilds an output integer
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_int_array (int_array : INTEGER_ARRAY_TYPE;
num_valid_entry : integer)
return INTEGER_ARRAY_TYPE is
-- Variables
variable temp_int_array : INTEGER_ARRAY_TYPE( 0 to num_valid_entry-1);
begin
for array_index in 0 to num_valid_entry-1 loop
temp_int_array(array_index) := int_array(array_index);
end loop;
return(temp_int_array);
end function rebuild_int_array;
function bits_needed_for_vac(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer is
begin
if not fifo_present then
return 1; -- Zero would be better but leads to "0 to -1" null
-- ranges that are not handled by XST Flint or earlier
-- because of the negative index.
else
return
log2(1 + dependent_props(FIFO_CAPACITY_BITS) /
dependent_props(RD_WIDTH_BITS)
);
end if;
end function bits_needed_for_vac;
function bits_needed_for_occ(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer is
begin
if not fifo_present then
return 1; -- Zero would be better but leads to "0 to -1" null
-- ranges that are not handled by XST Flint or earlier
-- because of the negative index.
else
return
log2(1 + dependent_props(FIFO_CAPACITY_BITS) /
dependent_props(WR_WIDTH_BITS)
);
end if;
end function bits_needed_for_occ;
function eff_dp(id : integer;
dep_prop : integer;
value : integer) return integer is
variable dp : integer := dep_prop;
type bo2na_type is array (boolean) of natural;
constant bo2na : bo2na_type := (0, 1);
begin
if value /= 0 then return value; end if; -- Not default
case id is
when IPIF_CHDMA_CHANNELS =>
-------------------
return( bo2na(dp = CLK_PERIOD_PS ) * 10000
+ bo2na(dp = PACKET_WAIT_UNIT_NS ) * 1000000
+ bo2na(dp = BURST_SIZE ) * 16
);
when others => return 0;
end case;
end eff_dp;
function populate_intr_mode_array (num_user_intr : integer;
intr_capture_mode : integer)
return INTEGER_ARRAY_TYPE is
variable intr_mode_array : INTEGER_ARRAY_TYPE(0 to num_user_intr-1);
begin
for i in 0 to num_user_intr-1 loop
intr_mode_array(i) := intr_capture_mode;
end loop;
return intr_mode_array;
end function populate_intr_mode_array;
function add_intr_ard_id_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE is
variable intr_ard_id_array : INTEGER_ARRAY_TYPE(0 to ard_id_array'length);
begin
intr_ard_id_array(0 to ard_id_array'length-1) := ard_id_array;
if include_intr then
intr_ard_id_array(ard_id_array'length) := IPIF_INTR;
return intr_ard_id_array;
else
return ard_id_array;
end if;
end function add_intr_ard_id_array;
function add_intr_ard_addr_range_array(include_intr : boolean;
ZERO_ADDR_PAD : std_logic_vector;
intr_baseaddr : std_logic_vector;
intr_highaddr : std_logic_vector;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_addr_range_array : SLV64_ARRAY_TYPE)
return SLV64_ARRAY_TYPE is
variable intr_ard_addr_range_array : SLV64_ARRAY_TYPE(0 to ard_addr_range_array'length+1);
begin
intr_ard_addr_range_array(0 to ard_addr_range_array'length-1) := ard_addr_range_array;
if include_intr then
intr_ard_addr_range_array(2*get_id_index(ard_id_array,IPIF_INTR))
:= ZERO_ADDR_PAD & intr_baseaddr;
intr_ard_addr_range_array(2*get_id_index(ard_id_array,IPIF_INTR)+1)
:= ZERO_ADDR_PAD & intr_highaddr;
return intr_ard_addr_range_array;
else
return ard_addr_range_array;
end if;
end function add_intr_ard_addr_range_array;
function add_intr_ard_dwidth_array(include_intr : boolean;
intr_dwidth : integer;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_dwidth_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE is
variable intr_ard_dwidth_array : INTEGER_ARRAY_TYPE(0 to ard_dwidth_array'length);
begin
intr_ard_dwidth_array(0 to ard_dwidth_array'length-1) := ard_dwidth_array;
if include_intr then
intr_ard_dwidth_array(get_id_index(ard_id_array, IPIF_INTR)) := intr_dwidth;
return intr_ard_dwidth_array;
else
return ard_dwidth_array;
end if;
end function add_intr_ard_dwidth_array;
function add_intr_ard_num_ce_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_num_ce_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE is
variable intr_ard_num_ce_array : INTEGER_ARRAY_TYPE(0 to ard_num_ce_array'length);
begin
intr_ard_num_ce_array(0 to ard_num_ce_array'length-1) := ard_num_ce_array;
if include_intr then
intr_ard_num_ce_array(get_id_index(ard_id_array, IPIF_INTR)) := 16;
return intr_ard_num_ce_array;
else
return ard_num_ce_array;
end if;
end function add_intr_ard_num_ce_array;
end package body ipif_pkg;
| apache-2.0 | 343699ca3f84f94161df2cb15fb438a6 | 0.489909 | 4.85572 | false | false | false | false |
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