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sandrosalvato94/System-Design-Project | VHDLs/constants.vhd | 1 | 568 | library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package CONSTANTS is
constant NUM_IPS : integer := 1;
constant DATA_WIDTH : integer := 16;
constant ADD_WIDTH : integer := 6;
type data_array is array (0 to NUM_IPS - 1) of std_logic_vector(DATA_WIDTH-1 downto 0);
type add_array is array (0 to NUM_IPS - 1) of std_logic_vector(ADD_WIDTH-1 downto 0);
constant INT_POS : integer := 13;
constant BE_POS : integer := 12;
constant IPADD_POS : integer := 11; -- downto 0
end package CONSTANTS;
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mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/fpu_conv.vhd | 1 | 33,432 | `protect begin_protected
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`protect end_protected
| apache-2.0 | abb11f807349f452fc5a63b373da5200 | 0.947296 | 1.834907 | false | false | false | false |
CyAScott/CIS4930.DatapathSynthesisTool | src/components/c_subtractor.vhd | 1 | 1,065 | library ieee;
use ieee.std_logic_1164.all;
library WORK;
use WORK.all;
entity c_subtractor is
generic
(
width : integer := 4
);
port
(
input1, input2 : in std_logic_vector((width - 1) downto 0);
output : out std_logic_vector(width downto 0)
);
end c_subtractor;
architecture behavior of c_subtractor is
function bits_to_int (input : std_logic_vector) return integer is
variable ret_val : integer := 0;
begin
for i in input'range loop
if input(i) = '1' then
ret_val := 2 ** i + ret_val;
end if;
end loop; return ret_val;
end bits_to_int;
begin
P0 : process (input1, input2)
variable difference : integer := 0;
variable temp : std_logic_vector(width downto 0);
begin
difference := bits_to_int(input1) - bits_to_int(input2);
if (difference < 0) then
difference := (2 ** (width + 1)) + difference;
end if;
for i in 0 to width loop
if (difference rem 2) = 1 then
temp(i) := '1';
else
temp(i) := '0';
end if;
difference := difference/2;
end loop;
output <= temp;
end process;
end behavior; | mit | 49a0922995136330240f38140b89572f | 0.644131 | 2.862903 | false | false | false | false |
marceloboeira/vhdl-examples | 008-state-machine-calculator/hex_to_bcd.vhd | 1 | 2,303 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity HexToBCD is
port (CLK: in STD_LOGIC;
sw0: in STD_LOGIC_VECTOR(3 downto 0);
sw1: in STD_LOGIC_VECTOR(3 downto 0);
sw2: in STD_LOGIC_VECTOR(3 downto 0);
sw3: in STD_LOGIC_VECTOR(3 downto 0);
bcd0: out STD_LOGIC_VECTOR(3 downto 0);
bcd1: out STD_LOGIC_VECTOR(3 downto 0);
bcd2: out STD_LOGIC_VECTOR(3 downto 0);
bcd3: out STD_LOGIC_VECTOR(3 downto 0));
end HexToBCD;
architecture behavior of HexToBCD is
begin
my_proc: process (CLK)
variable random: STD_LOGIC_VECTOR(15 downto 0) := "0000000000000000";
variable one: STD_LOGIC_VECTOR(3 downto 0) := "0000";
variable ten: STD_LOGIC_VECTOR(3 downto 0) := "0000";
variable hund: STD_LOGIC_VECTOR(3 downto 0) := "0000";
variable thou: STD_LOGIC_VECTOR(3 downto 0) := "0000";
variable tthou: STD_LOGIC_VECTOR(3 downto 0) := "0000";
variable hthou: STD_LOGIC_VECTOR(3 downto 0) := "0000";
begin
if (rising_edge(CLK)) then
random := sw3 & sw2 & sw1 & sw0;
for i in 0 to 15 loop
if (hthou >= "0101") then
hthou := STD_LOGIC_VECTOR (unsigned(hthou) +3);
end if;
if (tthou >= "0101") then
tthou := STD_LOGIC_VECTOR (unsigned(tthou) +3);
end if;
if (thou >= "0101") then
thou := STD_LOGIC_VECTOR (unsigned(thou) +3);
end if;
if (hund >= "0101") then
hund := STD_LOGIC_VECTOR (unsigned(hund) +3);
end if;
if (ten >= "0101") then
ten := STD_LOGIC_VECTOR (unsigned(ten) +3);
end if;
if (one >= "0101") then
one := STD_LOGIC_VECTOR (unsigned(one) +3);
end if;
hthou := hthou(2 downto 0) & tthou(3);
tthou := tthou(2 downto 0) & thou(3);
thou := thou(2 downto 0)& hund(3);
hund := hund(2 downto 0)& ten(3);
ten := ten(2 downto 0)& one(3);
one := one(2 downto 0)& random(15);
random := STD_LOGIC_VECTOR(unsigned(random) sll 1);
end loop;
bcd0 <= one;
bcd1 <= ten;
bcd2 <= hund;
bcd3 <= thou;
one := "0000";
ten:= "0000";
hund := "0000";
thou := "0000";
tthou:= "0000";
hthou:= "0000";
end if;
end process ;
end behavior;
| mit | 4ae941c22d9e3943ea4ae275339882a0 | 0.559705 | 3.09543 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-30bits_outputs31bits/2-MESA-HB/metaheurísticas/mesahb_spea2.vhd | 1 | 2,033 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.10:17:13)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mesahb_spea2_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5: IN unsigned(0 TO 30);
output1, output2: OUT unsigned(0 TO 31));
END mesahb_spea2_entity;
ARCHITECTURE mesahb_spea2_description OF mesahb_spea2_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "0000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
output1 <= input2 + 2;
WHEN "00000010" =>
register1 := register1 + 4;
register2 := input3 * 5;
WHEN "00000011" =>
register1 := register1 * 7;
register2 := register2 + 9;
WHEN "00000100" =>
register1 := register1 + 11;
register2 := ((NOT register2) + 1) XOR register2;
register3 := input4 * 14;
WHEN "00000101" =>
register2 := register3 * register2;
register1 := ((NOT register1) + 1) XOR register1;
WHEN "00000110" =>
register1 := register1 * 18;
WHEN "00000111" =>
register3 := input5 * 19;
register1 := register1 + register2;
WHEN "00001000" =>
register2 := register3 + 21;
WHEN "00001001" =>
register2 := register2 * 23;
WHEN "00001010" =>
register2 := register2 + 25;
WHEN "00001011" =>
output2 <= register1(0 TO 14) & register2(0 TO 15);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mesahb_spea2_description; | gpl-3.0 | 3034f5b4184b1ece8a0ab1fcf0b5aced | 0.667486 | 3.142195 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/axi_master_burst_v2_0/1af76933/hdl/src/vhdl/axi_master_burst_first_stb_offset.vhd | 1 | 17,703 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- Filename: axi_master_burst_first_stb_offset.vhd
--
-- Description:
-- This file implements a module to find the address offset of the first
-- strobe bit asserted active high on the input strobe bus. This module
-- does not support sparse strobe assertions (asserted strobes must be
-- contiguous with each other).
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_master_burst_first_stb_offset.vhd
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.0 $
-- Date: $1/19/2011$
--
-- History:
-- DET 1/19/2011 Initial
-- ~~~~~~
-- - Adapted from AXI DataMover v2_00_a axi_datamvore_stbs_set.vhd
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI MASTER BURST to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_master_burst_first_stb_offset is
generic (
C_STROBE_WIDTH : Integer range 1 to 32 := 8;
-- Specifies the width (in bits) ob the input strobe bus.
C_OFFSET_WIDTH : Integer range 1 to 16 := 8
-- Indicates the bit width of the offset output port
);
port (
tstrb_in : in std_logic_vector(C_STROBE_WIDTH-1 downto 0);
-- Input Strobe bus
first_offset : Out unsigned(C_OFFSET_WIDTH-1 downto 0)
-- Offset output port
);
end entity axi_master_burst_first_stb_offset;
architecture implementation of axi_master_burst_first_stb_offset is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_4bit_first_be_set
--
-- Function Description:
-- Implements an 4-bit lookup table for calculating the index
-- of the first BE asserted within an 4-bit BE vector.
--
-- Note that this function assumes that asserted strobes are
-- contiguous with each other (no sparse strobe assertions).
--
-------------------------------------------------------------------
function funct_4bit_first_be_set (be_4bit : std_logic_vector(3 downto 0)) return Integer is
Variable lvar_first_be_set : Integer range 0 to 3 := 0;
begin
case be_4bit is
-- ------- 0 bit --------------------------
-- when "0001" | "0011" | "0111" | "1111" =>
--
-- lvar_first_be_set := 0;
------- 1 bit --------------------------
when "0010" | "0110" | "1110" =>
lvar_first_be_set := 1;
------- 2 bit --------------------------
when "0100" | "1100" =>
lvar_first_be_set := 2;
------- 3 bit --------------------------
when "1000" =>
lvar_first_be_set := 3;
------- bit 0, or all zeros, or sparse strobes ------
When others =>
lvar_first_be_set := 0;
end case;
Return (lvar_first_be_set);
end function funct_4bit_first_be_set;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_8bit_first_be_set
--
-- Function Description:
-- Implements an 8-bit lookup table for calculating the index
-- of the first BE asserted within an 8-bit BE vector.
--
-- Note that this function assumes that asserted strobes are
-- contiguous with each other (no sparse strobe assertions).
--
-------------------------------------------------------------------
function funct_8bit_first_be_set(be_8bit : std_logic_vector(7 downto 0)) return integer is
Variable lvar_first_be_set : Integer range 0 to 7 := 0;
begin
case be_8bit is
-- ------- 0 bit --------------------------
-- when "00000001" | "00000011" | "00000111" | "00001111" |
-- "00011111" | "00111111" | "01111111" | "11111111" =>
--
-- lvar_first_be_set := 0;
------- 1 bit --------------------------
when "00000010" | "00000110" | "00001110" | "00011110" |
"00111110" | "01111110" | "11111110" =>
lvar_first_be_set := 1;
------- 2 bit --------------------------
when "00000100" | "00001100" | "00011100" | "00111100" |
"01111100" | "11111100" =>
lvar_first_be_set := 2;
------- 3 bit --------------------------
when "00001000" | "00011000" | "00111000" | "01111000" |
"11111000" =>
lvar_first_be_set := 3;
------- 4 bit --------------------------
when "00010000" | "00110000" | "01110000" | "11110000" =>
lvar_first_be_set := 4;
------- 5 bit --------------------------
when "00100000" | "01100000" | "11100000" =>
lvar_first_be_set := 5;
------- 6 bit --------------------------
when "01000000" | "11000000" =>
lvar_first_be_set := 6;
------- 7 bit --------------------------
when "10000000" =>
lvar_first_be_set := 7;
------- bit 0, or all zeros, or sparse strobes ------
When others =>
lvar_first_be_set := 0;
end case;
Return (lvar_first_be_set);
end function funct_8bit_first_be_set;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_16bit_first_be_set
--
-- Function Description:
-- Implements an 16-bit lookup table for calculating the index
-- of the first BE asserted within an 16-bit BE vector.
--
-- Note that this function assumes that asserted strobes are
-- contiguous with each other (no sparse strobe assertions).
--
-------------------------------------------------------------------
function funct_16bit_first_be_set(be_16bit : std_logic_vector(15 downto 0)) return integer is
Variable lvar_first_be_set : Integer range 0 to 15 := 0;
begin
case be_16bit is
--------- 0 bit --------------------------
--when "0000000000000001" | "0000000000000011" | "0000000000000111" | "0000000000001111" |
-- "0000000000011111" | "0000000000111111" | "0000000001111111" | "0000000011111111" |
-- "0000000111111111" | "0000001111111111" | "0000011111111111" | "0000111111111111" |
-- "0001111111111111" | "0011111111111111" | "0111111111111111" | "1111111111111111" =>
--
-- lvar_first_be_set := 0;
------- 1 bit --------------------------
when "0000000000000010" | "0000000000000110" | "0000000000001110" | "0000000000011110" |
"0000000000111110" | "0000000001111110" | "0000000011111110" | "0000000111111110" |
"0000001111111110" | "0000011111111110" | "0000111111111110" | "0001111111111110" |
"0011111111111110" | "0111111111111110" | "1111111111111110" =>
lvar_first_be_set := 1;
------- 2 bit --------------------------
when "0000000000000100" | "0000000000001100" | "0000000000011100" | "0000000000111100" |
"0000000001111100" | "0000000011111100" | "0000000111111100" | "0000001111111100" |
"0000011111111100" | "0000111111111100" | "0001111111111100" | "0011111111111100" |
"0111111111111100" | "1111111111111100" =>
lvar_first_be_set := 2;
------- 3 bit --------------------------
when "0000000000001000" | "0000000000011000" | "0000000000111000" | "0000000001111000" |
"0000000011111000" | "0000000111111000" | "0000001111111000" | "0000011111111000" |
"0000111111111000" | "0001111111111000" | "0011111111111000" | "0111111111111000" |
"1111111111111000" =>
lvar_first_be_set := 3;
------- 4 bit --------------------------
when "0000000000010000" | "0000000000110000" | "0000000001110000" | "0000000011110000" |
"0000000111110000" | "0000001111110000" | "0000011111110000" | "0000111111110000" |
"0001111111110000" | "0011111111110000" | "0111111111110000" | "1111111111110000" =>
lvar_first_be_set := 4;
------- 5 bit --------------------------
when "0000000000100000" | "0000000001100000" | "0000000011100000" | "0000000111100000" |
"0000001111100000" | "0000011111100000" | "0000111111100000" | "0001111111100000" |
"0011111111100000" | "0111111111100000" | "1111111111100000" =>
lvar_first_be_set := 5;
------- 6 bit --------------------------
when "0000000001000000" | "0000000011000000" | "0000000111000000" | "0000001111000000" |
"0000011111000000" | "0000111111000000" | "0001111111000000" | "0011111111000000" |
"0111111111000000" | "1111111111000000" =>
lvar_first_be_set := 6;
------- 7 bit --------------------------
when "0000000010000000" | "0000000110000000" | "0000001110000000" | "0000011110000000" |
"0000111110000000" | "0001111110000000" | "0011111110000000" | "0111111110000000" |
"1111111110000000" =>
lvar_first_be_set := 7;
------- 8 bit --------------------------
when "0000000100000000" | "0000001100000000" | "0000011100000000" | "0000111100000000" |
"0001111100000000" | "0011111100000000" | "0111111100000000" | "1111111100000000" =>
lvar_first_be_set := 8;
------- 9 bit --------------------------
when "0000001000000000" | "0000011000000000" | "0000111000000000" | "0001111000000000" |
"0011111000000000" | "0111111000000000" | "1111111000000000" =>
lvar_first_be_set := 9;
------- 10 bit --------------------------
when "0000010000000000" | "0000110000000000" | "0001110000000000" | "0011110000000000" |
"0111110000000000" | "1111110000000000" =>
lvar_first_be_set := 10;
------- 11 bit --------------------------
when "0000100000000000" | "0001100000000000" | "0011100000000000" | "0111100000000000" |
"1111100000000000" =>
lvar_first_be_set := 11;
------- 12 bit --------------------------
when "0001000000000000" | "0011000000000000" | "0111000000000000" | "1111000000000000" =>
lvar_first_be_set := 12;
------- 13 bit --------------------------
when "0010000000000000" | "0110000000000000" | "1110000000000000" =>
lvar_first_be_set := 13;
------- 14 bit --------------------------
when "0100000000000000" | "1100000000000000" =>
lvar_first_be_set := 14;
------- 15 bit --------------------------
when "1000000000000000" =>
lvar_first_be_set := 15;
------- Bit 0, or all zeros, or sparse strobes ------
When others =>
lvar_first_be_set := 0;
end case;
Return (lvar_first_be_set);
end function funct_16bit_first_be_set;
-- Signals
signal sig_strb_input : std_logic_vector(C_STROBE_WIDTH-1 downto 0) := (others => '0');
signal sig_first_offset_unsgnd : unsigned(C_OFFSET_WIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-- Assign the input port value
sig_strb_input <= tstrb_in;
-- Assign the output port value
first_offset <= sig_first_offset_unsgnd;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4BIT_CASE
--
-- If Generate Description:
-- Implement the 4-bit strobe width case
--
--
------------------------------------------------------------
GEN_4BIT_CASE : if (C_STROBE_WIDTH = 4) generate
signal sig_first_offset : integer range 0 to 15 := 0;
begin
sig_first_offset <= funct_4bit_first_be_set(sig_strb_input);
sig_first_offset_unsgnd <= TO_UNSIGNED(sig_first_offset, C_OFFSET_WIDTH);
end generate GEN_4BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8BIT_CASE
--
-- If Generate Description:
-- Implement the 8-bit strobe width case
--
--
------------------------------------------------------------
GEN_8BIT_CASE : if (C_STROBE_WIDTH = 8) generate
signal sig_first_offset : integer range 0 to 15 := 0;
begin
sig_first_offset <= funct_8bit_first_be_set(sig_strb_input);
sig_first_offset_unsgnd <= TO_UNSIGNED(sig_first_offset, C_OFFSET_WIDTH);
end generate GEN_8BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16BIT_CASE
--
-- If Generate Description:
-- Implement the 16-bit strobe width case
--
--
------------------------------------------------------------
GEN_16BIT_CASE : if (C_STROBE_WIDTH = 16) generate
signal sig_first_offset : integer range 0 to 15 := 0;
begin
sig_first_offset <= funct_16bit_first_be_set(sig_strb_input);
sig_first_offset_unsgnd <= TO_UNSIGNED(sig_first_offset, C_OFFSET_WIDTH);
end generate GEN_16BIT_CASE;
end implementation;
| apache-2.0 | ab6e9125beaccba1667bc611a10e9ef5 | 0.486019 | 4.981148 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/carry_compare_const.vhd | 1 | 11,125 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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`protect end_protected
| apache-2.0 | c2a18c0f93a19c09abf41d1c8809a6c0 | 0.927101 | 1.918434 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/common/input_blk.vhd | 5 | 28,006 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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`protect end_protected
| apache-2.0 | efcedbdf0b7c87bb52aa6b85e9b47253 | 0.944833 | 1.844563 | false | false | false | false |
KANGKANGABC/ArmRobot | pl_console.vhd | 1 | 6,892 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity pl_console is
port(
RESET : In std_logic;
user_clk : In std_logic;
user_wren : In std_logic;
user_rden : In std_logic;
UART_CTL : Out std_logic;
UART_BUSY : In std_logic;
UART_DATA : Out std_logic_vector(7 DOWNTO 0);
MOTOR_1 : Out std_logic_vector(15 DOWNTO 0);
MOTOR_2 : Out std_logic_vector(15 DOWNTO 0);
MOTOR_3 : Out std_logic_vector(15 DOWNTO 0);
MOTOR_4 : Out std_logic_vector(15 DOWNTO 0);
MOTOR_5 : Out std_logic_vector(15 DOWNTO 0);
MOTOR_6 : Out std_logic_vector(15 DOWNTO 0);
user_wstrb : In std_logic_vector(3 DOWNTO 0);
user_wr_data : In std_logic_vector(31 DOWNTO 0);
user_addr : In std_logic_vector(31 DOWNTO 0);
user_rd_data : Out std_logic_vector(31 DOWNTO 0);
GPIO_LED : OUT std_logic_vector(3 DOWNTO 0)
);
end entity;
architecture beh of pl_console is
type demo_mem is array(0 TO 31) of std_logic_vector(7 DOWNTO 0);
signal lite_addr : integer range 0 to 31;
signal motor1 : std_logic_vector(15 DOWNTO 0);
signal motor2 : std_logic_vector(15 DOWNTO 0);
signal motor3 : std_logic_vector(15 DOWNTO 0);
signal motor4 : std_logic_vector(15 DOWNTO 0);
signal motor5 : std_logic_vector(15 DOWNTO 0);
signal motor6 : std_logic_vector(15 DOWNTO 0);
signal litearray0 : demo_mem;
signal litearray1 : demo_mem;
signal litearray2 : demo_mem;
signal litearray3 : demo_mem;
begin
lite_addr <= conv_integer(user_addr(6 DOWNTO 2));
process(RESET,user_clk,UART_BUSY)
type StateType is(S0,S1,S2,S3,S4,S5,S6,S7,S8,S9,S10,S11,S12,S13,S14,S15,S16);
variable state : StateType := S0;
begin
if RESET = '0' then
state:= S0;
UART_CTL <= '0';
elsif rising_edge(user_clk) then
case state is
when S0 =>
UART_CTL <= '0';
UART_DATA <= x"00";
state := S1;
when S1 =>
UART_DATA <= motor1(15 DOWNTO 8);
state := S2;
when S2 =>
UART_CTL <= '1';
state := S3;
when S3 =>
UART_CTL <= '1';
state := S4;
when S4 =>
if UART_BUSY = '1' then
UART_CTL <= '0';
state := S5;
end if;
when S5 =>
UART_DATA <= motor1(7 DOWNTO 0);
state := S6;
when S6 =>
UART_CTL <= '1';
state := S7;
when S7 =>
UART_CTL <= '1';
state := S8;
when S8=>
if UART_BUSY = '1' then
UART_CTL <= '0';
state := S9;
end if;
when S9 =>
UART_DATA <= motor6(15 DOWNTO 8);
state := S10;
when S10 =>
UART_CTL <= '1';
state := S11;
when S11 =>
UART_CTL <= '1';
state := S12;
when S12 =>
if UART_BUSY = '1' then
UART_CTL <= '0';
state := S13;
end if;
when S13 =>
UART_DATA <= motor6(7 DOWNTO 0);
state := S14;
when S14 =>
UART_CTL <= '1';
state := S15;
when S15 =>
UART_CTL <= '1';
state := S16;
when S16 =>
if UART_BUSY = '1' then
UART_CTL <= '0';
state := S0;
end if;
when others =>
state := S0;
end case;
end if;
end process;
process (user_clk)
variable sys_status : std_logic_vector(31 DOWNTO 0);
begin
if (user_clk'event and user_clk = '1') then
if (user_wstrb(0) = '1') then
litearray0(lite_addr) <= user_wr_data(7 DOWNTO 0);
end if;
if (user_wstrb(1) = '1') then
litearray1(lite_addr) <= user_wr_data(15 DOWNTO 8);
end if;
if (user_wstrb(2) = '1') then
litearray2(lite_addr) <= user_wr_data(23 DOWNTO 16);
end if;
if (user_wstrb(3) = '1') then
litearray3(lite_addr) <= user_wr_data(31 DOWNTO 24);
end if;
if (user_rden = '1') then
user_rd_data <= litearray3(lite_addr) & litearray2(lite_addr) &
litearray1(lite_addr) & litearray0(lite_addr);
end if;
if (lite_addr = 1) then
GPIO_LED <= user_wr_data(31 DOWNTO 28);
motor1 <= litearray3(lite_addr) & litearray2(lite_addr);
end if;
if (lite_addr = 2) then
motor2 <= litearray3(lite_addr) & litearray2(lite_addr);
end if;
if (lite_addr = 3) then
motor3 <= litearray3(lite_addr) & litearray2(lite_addr);
end if;
if (lite_addr = 4) then
motor4 <= litearray3(lite_addr) & litearray2(lite_addr);
end if;
if (lite_addr = 5) then
motor5 <= litearray3(lite_addr) & litearray2(lite_addr);
end if;
if (lite_addr = 6) then
motor6 <= litearray3(lite_addr) & litearray2(lite_addr);
end if;
MOTOR_1 <= motor1;
MOTOR_2 <= motor2;
MOTOR_3 <= motor3;
MOTOR_4 <= motor4;
MOTOR_5 <= motor5;
MOTOR_6 <= motor6;
-- GPIO_LED <= "0101";
-- if (user_clk'event and user_clk = '1') then
-- if (user_wren = '1') then
---- litearray(lite_addr) <= user_wr_data;
-- sys_status := user_wr_data;
-- end if;
-- if (user_rden = '1') then
---- user_rd_data <= litearray(lite_addr);
-- user_rd_data <= sys_status;
-- end if;
-- end if;
end if;
end process;
end architecture;
| gpl-3.0 | 489ffc3cb7f8298d8284cca99860cff2 | 0.420052 | 4.07088 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/proc_common_pkg.vhd | 15 | 18,735 | -------------------------------------------------------------------------------
-- $Id: proc_common_pkg.vhd,v 1.1.4.46 2010/10/28 01:14:32 ostlerf Exp $
-------------------------------------------------------------------------------
-- Processor Common Library Package
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_common_pkg.vhd
-- Version: v1.21b
-- Description: This file contains the constants and functions used in the
-- processor common library components.
--
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 09/12/01 -- Created from opb_arb_pkg.vhd
--
-- ALS 09/21/01
-- ^^^^^^
-- Added pwr function. Replaced log2 function with one that works for XST.
-- ~~~~~~
--
-- ALS 12/07/01
-- ^^^^^^
-- Added Addr_bits function.
-- ~~~~~~
-- ALS 01/31/02
-- ^^^^^^
-- Added max2 function.
-- ~~~~~~
-- FLO 02/22/02
-- ^^^^^^
-- Extended input argument range of log2 function to 2^30. Also, added
-- a check that the argument does not exceed this value; a failure
-- assertion violation is generated if it does not.
-- ~~~~~~
-- FLO 08/31/06
-- ^^^^^^
-- Removed type TARGET_FAMILY_TYPE and functions Get_Reg_File_Area and
-- Get_RLOC_Name. These objects are not used. Further, the functions
-- produced misleading warnings (CR419886, CR419898).
-- ~~~~~~
-- FLO 05/25/07
-- ^^^^^^
-- -Reimplemented function pad_power2 to correct error when the input
-- argument is 1. (fixes CR 303469)
-- -Added function clog2(x), which returns the integer ceiling of the
-- base 2 logarithm of x. This function can be used in place of log2
-- when wishing to avoid the XST warning, "VHDL Assertion Statement
-- with non constant condition is ignored".
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-- DET 5/8/2009 v4_0 for EDK L.SP2
-- ~~~~~~
-- - Per CR520627
-- - Added synthesis translate_off/on constructs to the log2 function
-- around the assertion statement. This removes a repetative XST Warning
-- in SRP files about a non-constant assertion check.
-- ^^^^^^
-- FL0 20/27/2010
-- ^^^^^^
-- Removed 42 TBD comment, again. (CR 568493)
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- need conversion function to convert reals/integers to std logic vectors
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package proc_common_pkg is
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
type CHAR_TO_INT_TYPE is array (character) of integer;
-- type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
-- Type SLV64_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 63);
-------------------------------------------------------------------------------
-- Function and Procedure Declarations
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer;
function min2 (num1, num2 : integer) return integer;
function Addr_Bits(x,y : std_logic_vector) return integer;
function clog2(x : positive) return natural;
function pad_power2 ( in_num : integer ) return integer;
function pad_4 ( in_num : integer ) return integer;
function log2(x : natural) return integer;
function pwr(x: integer; y: integer) return integer;
function String_To_Int(S : string) return integer;
function itoa (int : integer) return string;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- the RESET_ACTIVE constant should denote the logic level of an active reset
constant RESET_ACTIVE : std_logic := '1';
-- table containing strings representing hex characters for conversion to
-- integers
constant STRHEX_TO_INT_TABLE : CHAR_TO_INT_TYPE :=
('0' => 0,
'1' => 1,
'2' => 2,
'3' => 3,
'4' => 4,
'5' => 5,
'6' => 6,
'7' => 7,
'8' => 8,
'9' => 9,
'A'|'a' => 10,
'B'|'b' => 11,
'C'|'c' => 12,
'D'|'d' => 13,
'E'|'e' => 14,
'F'|'f' => 15,
others => -1);
end proc_common_pkg;
package body proc_common_pkg is
-------------------------------------------------------------------------------
-- Function Definitions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Function max2
--
-- This function returns the greater of two numbers.
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer is
begin
if num1 >= num2 then
return num1;
else
return num2;
end if;
end function max2;
-------------------------------------------------------------------------------
-- Function min2
--
-- This function returns the lesser of two numbers.
-------------------------------------------------------------------------------
function min2 (num1, num2 : integer) return integer is
begin
if num1 <= num2 then
return num1;
else
return num2;
end if;
end function min2;
-------------------------------------------------------------------------------
-- Function Addr_bits
--
-- function to convert an address range (base address and an upper address)
-- into the number of upper address bits needed for decoding a device
-- select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits(x,y : std_logic_vector) return integer is
variable addr_xor : std_logic_vector(x'range);
variable count : integer := 0;
begin
assert x'length = y'length and (x'ascending xnor y'ascending)
report "Addr_Bits: arguments are not the same type"
severity ERROR;
addr_xor := x xor y;
for i in x'range
loop
if addr_xor(i) = '1' then return count;
end if;
count := count + 1;
end loop;
return x'length;
end Addr_Bits;
--------------------------------------------------------------------------------
-- Function clog2 - returns the integer ceiling of the base 2 logarithm of x,
-- i.e., the least integer greater than or equal to log2(x).
--------------------------------------------------------------------------------
function clog2(x : positive) return natural is
variable r : natural := 0;
variable rp : natural := 1; -- rp tracks the value 2**r
begin
while rp < x loop -- Termination condition T: x <= 2**r
-- Loop invariant L: 2**(r-1) < x
r := r + 1;
if rp > integer'high - rp then exit; end if; -- If doubling rp overflows
-- the integer range, the doubled value would exceed x, so safe to exit.
rp := rp + rp;
end loop;
-- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r
return r; --
end clog2;
-------------------------------------------------------------------------------
-- Function pad_power2
--
-- This function returns the next power of 2 from the input number. If the
-- input number is a power of 2, this function returns the input number.
--
-- This function is used to round up the number of masters to the next power
-- of 2 if the number of masters is not already a power of 2.
--
-- Input argument 0, which is not a power of two, is accepted and returns 0.
-- Input arguments less than 0 are not allowed.
-------------------------------------------------------------------------------
--
function pad_power2 (in_num : integer ) return integer is
begin
if in_num = 0 then
return 0;
else
return 2**(clog2(in_num));
end if;
end pad_power2;
-------------------------------------------------------------------------------
-- Function pad_4
--
-- This function returns the next multiple of 4 from the input number. If the
-- input number is a multiple of 4, this function returns the input number.
--
-------------------------------------------------------------------------------
--
function pad_4 (in_num : integer ) return integer is
variable out_num : integer;
begin
out_num := (((in_num-1)/4) + 1)*4;
return out_num;
end pad_4;
-------------------------------------------------------------------------------
-- Function log2 -- returns number of bits needed to encode x choices
-- x = 0 returns 0
-- x = 1 returns 0
-- x = 2 returns 1
-- x = 4 returns 2, etc.
-------------------------------------------------------------------------------
--
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-------------------------------------------------------------------------------
-- Function pwr -- x**y
-- negative numbers not allowed for y
-------------------------------------------------------------------------------
function pwr(x: integer; y: integer) return integer is
variable z : integer := 1;
begin
if y = 0 then return 1;
else
for i in 1 to y loop
z := z * x;
end loop;
return z;
end if;
end function pwr;
-------------------------------------------------------------------------------
-- Function itoa
--
-- The itoa function converts an integer to a text string.
-- This function is required since `image doesn't work in Synplicity
-- Valid input range is -9999 to 9999
-------------------------------------------------------------------------------
--
function itoa (int : integer) return string is
type table is array (0 to 9) of string (1 to 1);
constant LUT : table :=
("0", "1", "2", "3", "4", "5", "6", "7", "8", "9");
variable str1 : string(1 to 1);
variable str2 : string(1 to 2);
variable str3 : string(1 to 3);
variable str4 : string(1 to 4);
variable str5 : string(1 to 5);
variable abs_int : natural;
variable thousands_place : natural;
variable hundreds_place : natural;
variable tens_place : natural;
variable ones_place : natural;
variable sign : integer;
begin
abs_int := abs(int);
if abs_int > int then sign := -1;
else sign := 1;
end if;
thousands_place := abs_int/1000;
hundreds_place := (abs_int-thousands_place*1000)/100;
tens_place := (abs_int-thousands_place*1000-hundreds_place*100)/10;
ones_place :=
(abs_int-thousands_place*1000-hundreds_place*100-tens_place*10);
if sign>0 then
if thousands_place>0 then
str4 := LUT(thousands_place) & LUT(hundreds_place) & LUT(tens_place) &
LUT(ones_place);
return str4;
elsif hundreds_place>0 then
str3 := LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str3;
elsif tens_place>0 then
str2 := LUT(tens_place) & LUT(ones_place);
return str2;
else
str1 := LUT(ones_place);
return str1;
end if;
else
if thousands_place>0 then
str5 := "-" & LUT(thousands_place) & LUT(hundreds_place) &
LUT(tens_place) & LUT(ones_place);
return str5;
elsif hundreds_place>0 then
str4 := "-" & LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str4;
elsif tens_place>0 then
str3 := "-" & LUT(tens_place) & LUT(ones_place);
return str3;
else
str2 := "-" & LUT(ones_place);
return str2;
end if;
end if;
end itoa;
-----------------------------------------------------------------------------
-- Function String_To_Int
--
-- Converts a string of hex character to an integer
-- accept negative numbers
-----------------------------------------------------------------------------
function String_To_Int(S : String) return Integer is
variable Result : integer := 0;
variable Temp : integer := S'Left;
variable Negative : integer := 1;
begin
for I in S'Left to S'Right loop
if (S(I) = '-') then
Temp := 0;
Negative := -1;
else
Temp := STRHEX_TO_INT_TABLE(S(I));
if (Temp = -1) then
assert false
report "Wrong value in String_To_Int conversion " & S(I)
severity error;
end if;
end if;
Result := Result * 16 + Temp;
end loop;
return (Negative * Result);
end String_To_Int;
end package body proc_common_pkg;
| apache-2.0 | c6377cd7c53541865c37b5257829919c | 0.466773 | 4.644274 | false | false | false | false |
rcls/sdr | vhdl/clockgen.vhd | 1 | 2,144 | -- This generates the cpu clock @50 MHz.
-- It is carefully phased to get the 25Mbps SPI working.
-- It can be rephased via jtag user2.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library unisim;
use unisim.vcomponents.all;
library work;
use work.all;
use work.defs.all;
entity clockgen is
port (cpu_clk : out std_logic; wform : out unsigned(9 downto 0);
clk_main, clk_main_neg, clk_50m : in std_logic);
end clockgen;
architecture clockgen of clockgen is
signal update2, update3 : std_logic := '0';
signal drck, tdi, tdi2, sel, sel2, update : std_logic;
signal drck2, drck3 : std_logic := '1';
signal init, bits, shift : unsigned(9 downto 0) := "0111110000";
signal updated : boolean := true;
signal count : integer range 0 to 4;
signal first, second : std_logic;
signal div50by2, div50by2prev, edge50 : std_logic;
begin
occ : oddr2 generic map(ddr_alignment=>"C0", srtype=>"async")
port map (c0 => clk_main, c1 => clk_main_neg, q => cpu_clk,
d0 => first, d1 => second);
jtg : bscan_spartan6 generic map (jtag_chain => 2)
port map (drck => drck, tdi => tdi, update => update, tdo => shift(0),
sel => sel);
wform <= init;
process
begin
wait until rising_edge(clk_50m);
div50by2 <= not div50by2;
end process;
process
begin
wait until rising_edge(clk_main);
div50by2prev <= div50by2;
edge50 <= div50by2prev xor div50by2;
count <= count + 1;
if edge50 = '1' then
count <= 0;
if updated then
bits(4 downto 0) <= (others => bits(9));
bits(9 downto 5) <= (others => init(0));
updated <= false;
else
bits <= init;
end if;
end if;
first <= bits(count * 2);
second <= bits(count * 2 + 1);
drck2 <= drck;
drck3 <= drck2;
update2 <= update;
update3 <= update2;
sel2 <= sel;
tdi2 <= tdi;
if drck2 = '1' and drck3 = '0' and sel2 = '1' then
shift <= tdi2 & shift(9 downto 1);
end if;
if update2 = '1' and update3 = '0' then
init <= shift;
updated <= true;
end if;
end process;
end clockgen;
| gpl-3.0 | 5f0c658cee4f95244a1908946931eb14 | 0.605877 | 3.22406 | false | false | false | false |
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`protect end_protected
| apache-2.0 | 90cf056ffd9092fd36442f8071f93756 | 0.951313 | 1.83081 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/3-ARF/metaheurísticas/arf_femo.vhd | 1 | 2,433 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-13.07:34:46)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY arf_femo_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8: IN unsigned(0 TO 3);
output1, output2: OUT unsigned(0 TO 4));
END arf_femo_entity;
ARCHITECTURE arf_femo_description OF arf_femo_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
register2 := input2 * 2;
WHEN "00000010" =>
register1 := register1 + register2;
register2 := input3 * 3;
register3 := input4 * 4;
WHEN "00000011" =>
register2 := register3 + register2;
register3 := input5 * 5;
register4 := input6 * 6;
WHEN "00000100" =>
register3 := register4 + register3;
register2 := register2 + 8;
register4 := input7 * 9;
register1 := register1 + 11;
register5 := input8 * 12;
WHEN "00000101" =>
register4 := register4 + register5;
register5 := register2 * 14;
register6 := register1 * 16;
WHEN "00000110" =>
register1 := register1 * 18;
register2 := register2 * 20;
register5 := register5 + register6;
WHEN "00000111" =>
register1 := register2 + register1;
WHEN "00001000" =>
register2 := register1 * 22;
register6 := register5 * 24;
WHEN "00001001" =>
register2 := register2 + register6;
register5 := register5 * 26;
register1 := register1 * 28;
WHEN "00001010" =>
register1 := register1 + register5;
output1 <= register4 + register2;
WHEN "00001011" =>
output2 <= register3 + register1;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END arf_femo_description; | gpl-3.0 | e07f470c7b1f087abd681e1f69909d21 | 0.654336 | 3.09542 | false | false | false | false |
marceloboeira/vhdl-examples | 004-clock-divider/source.vhd | 1 | 704 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clock_div is
Port ( clock_50m : in STD_LOGIC;
reset : in STD_LOGIC;
led : out STD_LOGIC);
end clock_div;
architecture Behavioral of clock_div is
signal counter : integer range 0 to 25000 := 0;
signal led_tmp : STD_LOGIC := '0';
begin
process (clock_50m, reset)
begin
if reset='1' then
led <= '0'; -- '0' -> Binary
counter <= 0; -- 0 -> Decimal
elsif (clock_50m'event and clock_50m='1') then
if (counter < 25000) then
counter <= counter + 1;
else
counter <= 0;
led_tmp <= not led_tmp;
end if;
end if;
end process;
led <= led_tmp;
end Behavioral;
| mit | 9cd213459652f6e7b21bde727d76c074 | 0.575284 | 3.28972 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/5-EWF/asap-alap-random/ewf_alap.vhd | 1 | 3,019 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-16.08:47:35)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY ewf_alap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2: IN unsigned(0 TO 3);
output1, output2, output3, output4, output5: OUT unsigned(0 TO 4));
END ewf_alap_entity;
ARCHITECTURE ewf_alap_description OF ewf_alap_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register9: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register10: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register11: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
WHEN "00000010" =>
register2 := register1 + 3;
WHEN "00000011" =>
register3 := register2 + 5;
register4 := input2 + 6;
WHEN "00000100" =>
register3 := register4 + register3;
WHEN "00000101" =>
register5 := register3 * 8;
register6 := register3 * 10;
WHEN "00000110" =>
register5 := register4 + register5;
register6 := register2 + register6;
WHEN "00000111" =>
register4 := register4 + register5;
register2 := register2 + register6;
WHEN "00001000" =>
register4 := register4 * 12;
register2 := register2 * 14;
WHEN "00001001" =>
register4 := register4 + 16;
register2 := register1 + register2;
WHEN "00001010" =>
register7 := register5 + register4;
register8 := register6 + register2;
WHEN "00001011" =>
register7 := register7 + 18;
register1 := register1 + register2;
register8 := register8 + 20;
register9 := register4 + 22;
WHEN "00001100" =>
register10 := register7 * 24;
register1 := register1 * 26;
register11 := register8 * 28;
WHEN "00001101" =>
register9 := register9 * 30;
register3 := register3 + register6;
register6 := register10 + 32;
register1 := register1 + 34;
register10 := register11 + 36;
WHEN "00001110" =>
output1 <= register4 + register9;
output2 <= register5 + register3;
output3 <= register7 + register6;
output4 <= register2 + register1;
output5 <= register8 + register10;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END ewf_alap_description; | gpl-3.0 | 7d96ee715813b46573d08851c7236989 | 0.65949 | 3.184599 | false | false | false | false |
marceloboeira/vhdl-examples | 008-state-machine-calculator/calculator.vhd | 1 | 3,426 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity Calculator is
port (clock : in STD_LOGIC;
btn_reset : in STD_LOGIC;
btn_inc : in STD_LOGIC;
btn_dec : in STD_LOGIC;
switch_input : in STD_LOGIC;
switch_operation : in STD_LOGIC;
switch_done : in STD_LOGIC;
display_out : out STD_LOGIC_VECTOR (15 downto 0));
end Calculator;
architecture Behavioral of Calculator is
type STATE is (BOOT,
POLLING,
INPUT_DATA,
RELEASE_BTN_INC,
RELEASE_BTN_DEC,
CALCULATE,
SHOW_RESULTS);
signal current_state : STATE;
signal input_a, input_b : INTEGER range 0 to 255;
signal result : STD_LOGIC_VECTOR (7 downto 0);
signal operation : INTEGER range 0 to 9;
begin
core : process (clock, btn_reset, btn_inc, btn_dec)
begin
if clock'event and clock = '1' then
if btn_reset = '1' then
current_state <= BOOT;
end if;
case current_state is
when BOOT =>
input_a <= 0;
input_b <= 0;
operation <= 0;
current_state <= POLLING;
when POLLING =>
if switch_done = '1' then
current_state <= CALCULATE;
elsif btn_inc = '1' then
current_state <= RELEASE_BTN_INC;
elsif btn_dec = '1' then
current_state <= RELEASE_BTN_DEC;
else
current_state <= POLLING;
end if;
when RELEASE_BTN_INC =>
if btn_inc = '0' then
if switch_operation = '0' then
if switch_input = '0' then
input_a <= input_a + 1;
else
input_b <= input_b + 1;
end if;
else
operation <= operation + 1;
end if;
current_state <= POLLING;
end if;
when RELEASE_BTN_DEC =>
if btn_dec = '0' then
if switch_operation = '0' then
if switch_input = '0' then
input_a <= input_a - 1;
else
input_b <= input_b - 1;
end if;
else
operation <= operation - 1;
end if;
current_state <= POLLING;
end if;
when CALCULATE =>
case operation is
when 1 =>
result <= conv_std_logic_vector((input_a + input_b), 8);
when 2 =>
result <= conv_std_logic_vector((input_a - input_b), 8);
when 3 =>
result <= conv_std_logic_vector((input_a - input_b), 8);
when 4 =>
result <= conv_std_logic_vector((input_a * input_b), 8);
when 5 =>
result <= conv_std_logic_vector(input_a, 8) and conv_std_logic_vector(input_b, 8);
when 6 =>
result <= conv_std_logic_vector(input_a, 8) or conv_std_logic_vector(input_b, 8);
when 7 =>
result <= conv_std_logic_vector(input_a, 8) xor conv_std_logic_vector(input_b, 8);
when 8 =>
result <= not conv_std_logic_vector(input_a, 8);
when 9 =>
result <= conv_std_logic_vector(0, 8);
when others =>
result <= conv_std_logic_vector(0, 8);
end case;
current_state <= BOOT;
when others =>
current_state <= BOOT;
end case;
end if;
end process;
end Behavioral ;
| mit | 2a116d88b946372f1eaa2a9d14ea2820 | 0.502335 | 3.853768 | false | false | false | false |
rhexsel/xinu-cMIPS | vhdl/disk.vhd | 2 | 18,008 | -- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- disk(0): ctrl(31)=oper[1=rd, 0=wr], (30)=doInterrupt,
-- (11..0)=transferSize in words, aligned, <= 1024
-- disk(1): stat(31)=oper[1rd, 0wr], (30)=doInterrupt, (29)=busy,
-- (28)=interrupt pending, (27)=0,
-- (26)=errSize [transfer larger than 1024 words],
-- (25,24)=file error [00=ok, 01=status, 10=name, 11=mode].
-- (23..0)=last address referenced
-- disk(2): src [rd=disk file {0,1,2,3}, wr=memory address]
-- disk(3): dst [rd=memory address, wr=disk file {0,1,2,3}]
-- disk(4): interr, (1)=setIRQ, (0)=clrIRQ
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- simulates a disk controller with DMA transfers, word only transfers
-- transfers AT MOST 4Kbytes or 1024 memory cycles
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
entity DISK is
port (rst : in std_logic;
clk : in std_logic;
strobe : in std_logic; -- strobe for file reads/writes
sel : in std_logic; -- active in '0'
rdy : out std_logic; -- active in '0'
wr : in std_logic; -- active in '0'
busFree : in std_logic; -- '1' = bus will be free next cycle
busReq : out std_logic; -- '1' = bus will be used next cycle
busGrant : in std_logic; -- '1' = bus is free in this cycle
addr : in reg3;
data_inp : in reg32;
data_out : out reg32;
irq : out std_logic;
dma_addr : out reg32;
dma_dinp : in reg32;
dma_dout : out reg32;
dma_wr : out std_logic; -- active in '0'
dma_aval : out std_logic; -- active in '0'
dma_type : out reg4);
constant NUM_BITS : integer := 32;
constant START_VALUE : reg32 := (others => '0');
end entity DISK;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- simulation version -- logic too complex for synthesis,
-- as there is no hw disk, model is for simulation
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
architecture simulation of DISK is
component registerN is
generic (NUM_BITS: integer; INIT_VAL: std_logic_vector);
port(clk, rst, ld: in std_logic;
D: in std_logic_vector;
Q: out std_logic_vector);
end component registerN;
component countNup is
generic (NUM_BITS: integer := 16);
port(clk, rst, ld, en: in std_logic;
D: in std_logic_vector((NUM_BITS - 1) downto 0);
Q: out std_logic_vector((NUM_BITS - 1) downto 0);
co: out std_logic);
end component countNup;
component FFDsimple is
port(clk, rst, D : in std_logic; Q : out std_logic);
end component FFDsimple;
constant C_OPER : integer := 31; -- operation 1=rd, 0=wr
constant C_OPER_RD : std_logic := '1';
constant C_OPER_WR : std_logic := '0';
constant C_INT : integer := 30; -- interrupt when finished=1
constant S_BUSY : integer := 29; -- controller busy=1
constant I_SET : integer := 1; -- set IRQ
constant I_CLR : integer := 0; -- clear IRQ
constant DSK_OK : std_logic_vector(1 downto 0) := b"00";
constant DSK_STATUS : std_logic_vector(1 downto 0) := b"01";
constant DSK_NAME : std_logic_vector(1 downto 0) := b"10";
constant DSK_MODE : std_logic_vector(1 downto 0) := b"11";
type int_file is file of integer;
file my_file : int_file;
type dma_state is (st_init, st_idle, st_src, st_dst, st_check,
st_bus, st_xfer, st_int, st_assert, st_wait, st_err);
attribute SYN_ENCODING of dma_state : type is "safe";
signal dma_current_st, dma_next_st : dma_state;
signal dma_curr_dbg, current_int, ctrl_int, addr_int : integer;
signal ld_ctrl, s_ctrl, s_stat, ld_src, s_src, ld_dst, s_dst : std_logic;
signal busy, take_bus, ld_curr, rst_curr, en_curr : std_logic;
signal ctrl, src, dst, stat, datum : reg32 := (others => '0');
signal current, xfer_sz : reg10;
signal last_addr : reg24;
signal base_addr, curr_addr, address : reg32;
signal s_intw, s_intr, set_irq, clear_irq, s_dat, err_sz : std_logic;
signal d_set_interrupt, interrupt, do_interr, ld_last : std_logic;
signal done, last_one : boolean;
signal err_dsk : reg2 := b"00";
signal clear_hold_done, set_hold_done, d_set_hold_done, hold_done : std_logic;
begin -- functional
rdy <= ZERO; -- simulation only, never waits
s_ctrl <= '1' when sel = '0' and addr = b"000" else '0'; -- R+W
s_stat <= '1' when sel = '0' and addr = b"001" else '0'; -- R+W
s_src <= '1' when sel = '0' and addr = b"010" else '0'; -- W
s_dst <= '1' when sel = '0' and addr = b"011" else '0'; -- W
s_intw <= '1' when sel = '0' and addr = b"100" and wr = '0' else '0'; -- W
s_intr <= '1' when sel = '0' and addr = b"100" and wr = '1' else '0'; -- R
s_dat <= '1' when sel = '0' and addr = b"111" else '0'; -- W, DEBUG
ld_ctrl <= '0' when s_ctrl = '1' and wr = '0' else '1';
U_CTRL: registerN generic map (NUM_BITS, START_VALUE)
port map (clk, rst, ld_ctrl, data_inp, ctrl);
ld_src <= '0' when s_src = '1' and wr = '0' else '1';
U_SRC: registerN generic map (NUM_BITS, START_VALUE)
port map (clk, rst, ld_src, data_inp, src);
ld_dst <= '0' when s_dst = '1' and wr = '0' else '1';
U_DST: registerN generic map (NUM_BITS, START_VALUE)
port map (clk, rst, ld_dst, data_inp, dst);
stat <= ctrl(C_OPER) & ctrl(C_INT) & busy & interrupt &
'0' & err_sz & err_dsk & last_addr;
with addr select
data_out <= ctrl when "000",
stat when "001",
src when "010",
dst when "011",
x"00000000" when others; -- interrupts, does RD-mod-WR
irq <= interrupt;
busReq <= take_bus;
dma_type <= b"1111"; -- always transfers words
dma_wr <= not(ctrl(C_OPER)) or not(take_bus); -- write to RAM
dma_aVal <= not(take_bus);
base_addr <= dst when ctrl(C_OPER) = C_OPER_RD else src;
curr_addr <= x"0000" & b"0000" & current & b"00"; -- word aligned
address <= std_logic_vector( signed(base_addr) + signed(curr_addr) );
dma_addr <= address;
dma_dout <= datum when ctrl(C_OPER) = C_OPER_RD else (others => 'X');
xfer_sz <= ctrl(9 downto 0) when ctrl_int <= 1024 else (others => '0');
addr_int <= to_integer(unsigned( ctrl(10 downto 0)));
err_sz <= YES when addr_int > 1024 else NO; -- check if size > 1024
rst_curr <= not(ld_curr) and rst;
U_CURRENT: countNup generic map (10) -- current DMA reference
port map (clk, rst_curr, '0', en_curr, xfer_sz, current);
last_one <= (current_int = (ctrl_int - 1));
ld_last <= BOOL2SL(not(last_one));
U_LAST_ADDR: registerN generic map (24, x"000000") -- for status
port map (clk, rst, ld_last, address(23 downto 0), last_addr);
current_int <= to_integer(unsigned(current));
ctrl_int <= to_integer(unsigned(ctrl(9 downto 0))); -- check == 1024
done <= ( (current = (ctrl(9 downto 0))) and (hold_done = NO) );
clear_hold_done <= en_curr; -- first increment, makes current /= 0
set_hold_done <= s_ctrl; -- wait 1 DMA access to check for done
d_set_hold_done <= (set_hold_done or hold_done) and not(clear_hold_done);
U_HOLD_DONE: FFDsimple port map (clk, rst, d_set_hold_done, hold_done);
-- file operations -----------------------------------------------------
U_FILE_CTRL: process(rst, clk, s_ctrl, s_src, s_dst, data_inp, ctrl)
variable status : file_open_status := open_ok;
variable i_status : integer := 0;
begin
if rst = '1' then
if (s_src = YES) and falling_edge(clk) and (ctrl(C_OPER) = C_OPER_RD)
then -- read file
case data_inp(1 downto 0) is
when b"00" => file_open(status, my_file, "DMA_0.src", read_mode);
when b"01" => file_open(status, my_file, "DMA_1.src", read_mode);
when b"10" => file_open(status, my_file, "DMA_2.src", read_mode);
when b"11" => file_open(status, my_file, "DMA_3.src", read_mode);
when others => status := name_error;
end case;
i_status := file_open_status'pos(status);
assert status = open_ok
report "fileRDopen["&SLV32HEX(ctrl)&"]."&SLV32HEX(data_inp)&" "&
natural'image(i_status);
case status is
when open_ok => err_dsk <= DSK_OK;
when status_error => err_dsk <= DSK_STATUS;
when name_error => err_dsk <= DSK_NAME;
when mode_error => err_dsk <= DSK_MODE;
when others => null;
end case;
end if;
if (s_dst = YES) and falling_edge(clk) and (ctrl(C_OPER) = C_OPER_WR)
then
case data_inp(1 downto 0) is
when b"00" => file_open(status, my_file, "DMA_0.dst", write_mode);
when b"01" => file_open(status, my_file, "DMA_1.dst", write_mode);
when b"10" => file_open(status, my_file, "DMA_2.dst", write_mode);
when b"11" => file_open(status, my_file, "DMA_3.dst", write_mode);
when others => status := name_error;
end case;
i_status := file_open_status'pos(status);
assert status = open_ok
report "fileWRopen["&SLV32HEX(ctrl)&"]."&SLV32HEX(data_inp)&" "&
natural'image(i_status);
case status is
when open_ok => err_dsk <= DSK_OK;
when status_error => err_dsk <= DSK_STATUS;
when name_error => err_dsk <= DSK_NAME;
when mode_error => err_dsk <= DSK_MODE;
when others => null;
end case;
end if; -- end write file
end if; -- reset
end process U_FILE_CTRL; -----------------------------------------------
clear_irq <= s_intw and data_inp(I_CLR);
set_irq <= ( (ctrl(C_INT) and do_interr) or (s_intw and data_inp(I_SET)) );
d_set_interrupt <= set_irq or (interrupt and not(clear_irq));
U_tx_int: FFDsimple port map (clk, rst, d_set_interrupt, interrupt);
-- state register-------------------------------------------------------
U_st_reg: process(rst,clk)
begin
if rst = ZERO then
dma_current_st <= st_init;
elsif rising_edge(clk) then
dma_current_st <= dma_next_st;
end if;
end process U_st_reg;
dma_curr_dbg <= dma_state'pos(dma_current_st); -- debugging only
U_st_transitions: process(dma_current_st, strobe, done,
s_ctrl, s_src, s_dst, s_stat,
busFree, busGrant, current, ctrl, interrupt,
dma_dinp, err_sz, err_dsk)
variable i_datum : integer;
variable i_addr, i_val : reg32;
begin
case dma_current_st is
when st_init => -- 0
dma_next_st <= st_idle;
when st_idle => -- 1
if s_ctrl = YES then
dma_next_st <= st_src;
else
dma_next_st <= st_idle;
end if;
when st_src => -- 2
if s_src = YES then
dma_next_st <= st_dst;
else
dma_next_st <= st_src;
end if;
when st_dst => -- 3
if s_dst = YES then
dma_next_st <= st_check;
else
dma_next_st <= st_dst;
end if;
when st_check => -- 4 are there any errors?
if err_sz = NO and err_dsk = b"00" then
dma_next_st <= st_bus;
else
dma_next_st <= st_err; -- YES, wait for status to be read
end if;
when st_bus => -- 5
if busFree = NO then
dma_next_st <= st_bus;
else
dma_next_st <= st_xfer;
end if;
when st_xfer => -- 6
if not(done) then -- not done
i_addr := x"00000" & current & b"00";
if ( rising_edge(strobe) and (busGrant = YES) )then
if ctrl(C_OPER) = C_OPER_RD then -- read
if not(endfile(my_file)) then
read( my_file, i_datum );
datum <= std_logic_vector(to_signed(i_datum, 32));
i_val := std_logic_vector(to_signed(i_datum, 32));
assert TRUE
report "DISKrd["&SLV32HEX(i_addr)&"]="&SLV32HEX(i_val);
else
datum <= (others => 'X');
end if;
else -- write = ctrl(C_OPER) = C_OPER_WR
write( my_file, to_integer(signed(dma_dinp)) );
assert TRUE
report "DISKwr["&SLV32HEX(i_addr)&"]="&SLV32HEX(dma_dinp);
end if;
end if;
if busFree = NO then
dma_next_st <= st_bus;
else
dma_next_st <= st_xfer;
end if;
else -- done
dma_next_st <= st_int;
end if;
when st_int => -- 7
if ctrl(C_INT) = YES then -- shall we raise an interrupt?
dma_next_st <= st_assert;
else
dma_next_st <= st_idle;
end if;
file_close(my_file);
when st_assert => -- 8
dma_next_st <= st_wait;
when st_wait => -- 9
if interrupt = YES then -- wait for IRQ to be cleared
dma_next_st <= st_wait;
else
dma_next_st <= st_idle;
end if;
when st_err => -- 10
if s_stat = NO then
dma_next_st <= st_err;
else
dma_next_st <= st_idle;
end if;
when others => -- ??
dma_next_st <= st_idle;
end case;
end process U_st_transitions; -- -----------------------------------
U_st_outputs: process(dma_current_st, done)
begin
case dma_current_st is
when st_init | st_idle | st_src =>
busy <= NO; -- free
en_curr <= NO; -- do not increment address
ld_curr <= NO; -- do not load address
take_bus <= NO; -- leave the bus alone
do_interr <= NO;
when st_dst =>
busy <= YES; -- busy
en_curr <= NO; -- do not increment address
ld_curr <= YES; -- load address
take_bus <= NO; -- leave the bus alone
do_interr <= NO;
when st_bus | st_check | st_wait =>
busy <= YES; -- busy
en_curr <= NO; -- do not increment address
ld_curr <= NO; -- do not load address
take_bus <= NO; -- leave the bus alone
do_interr <= NO;
when st_xfer =>
busy <= YES; -- busy
en_curr <= YES; -- increment address
if not(done) then
take_bus <= YES; -- request bus
else
take_bus <= NO;
end if;
ld_curr <= NO; -- do not load address
do_interr <= NO;
when st_int =>
busy <= NO; -- free
en_curr <= NO; -- do not increment address
ld_curr <= NO; -- do not load address
take_bus <= NO; -- leave the bus alone
do_interr <= NO;
when st_assert =>
busy <= NO; -- free
en_curr <= NO; -- increment address
ld_curr <= NO; -- do not load address
take_bus <= NO; -- leave the bus alone
do_interr <= YES; -- raise interrupt request
when others =>
busy <= NO; -- free
en_curr <= NO; -- do not increment address
ld_curr <= NO; -- do not load address
take_bus <= NO; -- leave the bus alone
do_interr <= NO;
end case;
end process U_st_outputs; -- -----------------------------------
end architecture simulation;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- synthesis version - compiler will optimize all away (one hopes)
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
architecture fake of DISK is
begin
rdy <= 'X';
busReq <= NO;
irq <= NO;
data_out <= (others => 'X');
dma_addr <= (others => 'X');
dma_dout <= (others => 'X');
dma_wr <= 'X';
dma_aval <= 'X';
dma_type <= (others => 'X');
end architecture fake;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| gpl-3.0 | 9b8740bf03cf20e3723d4ae2e47bc592 | 0.488561 | 3.585109 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/counter_f.vhd | 15 | 13,734 |
-------------------------------------------------------------------------------
-- counter_f - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter_f.vhd
--
-- Description: Implements a parameterizable N-bit counter_f
-- Up/Down Counter
-- Count Enable
-- Parallel Load
-- Synchronous Reset
-- The structural implementation has incremental cost
-- of one LUT per bit.
-- Precedence of operations when simultaneous:
-- reset, load, count
--
-- A default inferred-RTL implementation is provided and
-- is used if the user explicitly specifies C_FAMILY=nofamily
-- or ommits C_FAMILY (allowing it to default to nofamily).
-- The default implementation is also used
-- if needed primitives are not available in FPGAs of the
-- type given by C_FAMILY.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- counter_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- Author: FLO & Nitin 06/06/2006 First Version, functional equivalent
-- of counter.vhd.
-- History:
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.unsigned;
use IEEE.numeric_std."+";
use IEEE.numeric_std."-";
library unisim;
use unisim.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity counter_f is
generic(
C_NUM_BITS : integer := 9;
C_FAMILY : string := "nofamily"
);
port(
Clk : in std_logic;
Rst : in std_logic;
Load_In : in std_logic_vector(C_NUM_BITS - 1 downto 0);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Count_Out : out std_logic_vector(C_NUM_BITS - 1 downto 0);
Carry_Out : out std_logic
);
end entity counter_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of counter_f is
---------------------------------------------------------------------
-- Component declarations
---------------------------------------------------------------------
component MUXCY_L is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component MUXCY_L;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
---------------------------------------------------------------------
-- Constant declarations
---------------------------------------------------------------------
constant USE_STRUCTURAL_A : boolean :=
supported(C_FAMILY, (u_MUXCY_L, u_XORCY, u_FDRE));
constant USE_INFERRED : boolean := not USE_STRUCTURAL_A;
---------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Generate structural code
---------------------------------------------------------------------
STRUCTURAL_A_GEN : if USE_STRUCTURAL_A generate
signal alu_cy : std_logic_vector(C_NUM_BITS+1 downto 0);
signal alu_cy_init : std_logic;
signal icount_out : std_logic_vector(C_NUM_BITS downto 0);
signal icount_out_x : std_logic_vector(C_NUM_BITS downto 0);
signal load_in_x : std_logic_vector(C_NUM_BITS downto 0);
signal count_AddSub : std_logic_vector(C_NUM_BITS downto 0);
signal count_Result : std_logic_vector(C_NUM_BITS downto 0);
signal count_clock_en : std_logic;
begin
alu_cy_init <= (Count_Down and Count_Load) or
(not Count_Down and not Count_load);
I_MUXCY_I : component MUXCY_L
port map (
DI => '0',
CI => '1',
S => alu_cy_init,
LO => alu_cy(0));
count_clock_en <= Count_Enable or Count_Load;
load_in_x <= ('0' & Load_In);
-- Mask out carry position to retain legacy self-clear on next enable.
icount_out_x <= ('0' & icount_out(C_NUM_BITS-1 downto 0));
-----------------------------------------------------------------
-- Generate counter using MUXCY_L, XORCY and FDRE
-----------------------------------------------------------------
I_ADDSUB_GEN : for i in 0 to C_NUM_BITS generate
count_AddSub(i) <= load_in_x(i) xor Count_Down
when Count_Load ='1' else
icount_out_x(i) xor Count_Down ; -- LUT
MUXCY_I : component MUXCY_L
port map (
DI => Count_Down,
CI => alu_cy(i),
S => count_AddSub(i),
LO => alu_cy(i+1));
XOR_I : component XORCY
port map (
LI => count_AddSub(i),
CI => alu_cy(i),
O => count_Result(i));
FDRE_I: component FDRE
port map (
Q => iCount_Out(i),
C => Clk,
CE => count_clock_en,
D => count_Result(i),
R => Rst);
end generate I_ADDSUB_GEN;
Carry_Out <= icount_out(C_NUM_BITS);
Count_Out <= icount_out(C_NUM_BITS-1 downto 0);
end generate STRUCTURAL_A_GEN;
---------------------------------------------------------------------
-- Generate Inferred code
---------------------------------------------------------------------
--INFERRED_GEN : if USE_INFERRED generate
INFERRED_GEN : if (not USE_STRUCTURAL_A) generate
signal icount_out : unsigned(C_NUM_BITS downto 0);
signal icount_out_x : unsigned(C_NUM_BITS downto 0);
signal load_in_x : unsigned(C_NUM_BITS downto 0);
begin
load_in_x <= unsigned('0' & Load_In);
-- Mask out carry position to retain legacy self-clear on next enable.
-- icount_out_x <= ('0' & icount_out(C_NUM_BITS-1 downto 0)); -- Echeck WA
icount_out_x <= unsigned('0' & std_logic_vector(icount_out(C_NUM_BITS-1 downto 0)));
-----------------------------------------------------------------
-- Process to generate counter with - synchronous reset, load,
-- counter enable, count down / up features.
-----------------------------------------------------------------
CNTR_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
icount_out <= (others => '0');
elsif Count_Load = '1' then
icount_out <= load_in_x;
elsif Count_Down = '1' and Count_Enable = '1' then
icount_out <= icount_out_x - 1;
elsif Count_Enable = '1' then
icount_out <= icount_out_x + 1;
end if;
end if;
end process CNTR_PROC;
Carry_Out <= icount_out(C_NUM_BITS);
Count_Out <= std_logic_vector(icount_out(C_NUM_BITS-1 downto 0));
end generate INFERRED_GEN;
end architecture imp;
---------------------------------------------------------------
-- End of file counter_f.vhd
---------------------------------------------------------------
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`protect end_protected
| apache-2.0 | 98bfb15a4f5764bcc59df274bacf5104 | 0.953526 | 1.811142 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-30bits_outputs31bits/3-ARF/metaheurísticas/arf_femo.vhd | 1 | 2,603 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-13.07:34:46)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY arf_femo_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8: IN unsigned(0 TO 30);
output1, output2: OUT unsigned(0 TO 31));
END arf_femo_entity;
ARCHITECTURE arf_femo_description OF arf_femo_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register4: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register5: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register6: unsigned(0 TO 31) := "00000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
register2 := input2 * 2;
WHEN "00000010" =>
register1 := register1 + register2;
register2 := input3 * 3;
register3 := input4 * 4;
WHEN "00000011" =>
register2 := register3 + register2;
register3 := input5 * 5;
register4 := input6 * 6;
WHEN "00000100" =>
register3 := register4 + register3;
register2 := register2 + 8;
register4 := input7 * 9;
register1 := register1 + 11;
register5 := input8 * 12;
WHEN "00000101" =>
register4 := register4 + register5;
register5 := register2 * 14;
register6 := register1 * 16;
WHEN "00000110" =>
register1 := register1 * 18;
register2 := register2 * 20;
register5 := register5 + register6;
WHEN "00000111" =>
register1 := register2 + register1;
WHEN "00001000" =>
register2 := register1 * 22;
register6 := register5 * 24;
WHEN "00001001" =>
register2 := register2 + register6;
register5 := register5 * 26;
register1 := register1 * 28;
WHEN "00001010" =>
register1 := register1 + register5;
output1 <= register4 + register2;
WHEN "00001011" =>
output2 <= register3 + register1;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END arf_femo_description; | gpl-3.0 | e799888f6e211e6d46da35f33bb4bead | 0.676911 | 3.311705 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/8-JPEG-SD/asap-alap-random/jpegsd_alap.vhd | 1 | 3,907 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-26.15:39:39)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY jpegsd_alap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16, input17, input18: IN unsigned(0 TO 3);
output1, output2, output3: OUT unsigned(0 TO 4));
END jpegsd_alap_entity;
ARCHITECTURE jpegsd_alap_description OF jpegsd_alap_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
WHEN "00000010" =>
register1 := ((NOT register1) + 1) XOR register1;
register2 := ((NOT input2) + 1) XOR input2;
register3 := input3 + 5;
register4 := ((NOT input4) + 1) XOR input4;
WHEN "00000011" =>
register1 := register2 + register1;
register2 := input5 + 7;
register3 := ((NOT register3) + 1) XOR register3;
WHEN "00000100" =>
register1 := register1 + register4;
register4 := input6 + 10;
register2 := ((NOT register2) + 1) XOR register2;
WHEN "00000101" =>
register1 := register1 + register3;
register3 := input7 + 13;
register5 := input8 + 14;
register6 := input9 + 15;
register4 := ((NOT register4) + 1) XOR register4;
WHEN "00000110" =>
register1 := register1 + register2;
register2 := input10 + 18;
register3 := ((NOT register3) + 1) XOR register3;
register5 := ((NOT register5) + 1) XOR register5;
register7 := input11 + 23;
register6 := ((NOT register6) + 1) XOR register6;
WHEN "00000111" =>
register1 := register1 + register4;
register4 := input12 + 26;
register8 := input13 + 27;
register2 := ((NOT register2) + 1) XOR register2;
register3 := register5 + register3;
register5 := ((NOT register7) + 1) XOR register7;
WHEN "00001000" =>
register1 := register1 + register6;
register4 := ((NOT register4) + 1) XOR register4;
register6 := ((NOT input14) + 1) XOR input14;
register7 := ((NOT register8) + 1) XOR register8;
register2 := register3 + register2;
WHEN "00001001" =>
register1 := register1 + register5;
register3 := input15 + 37;
register5 := ((NOT input16) + 1) XOR input16;
register4 := register6 + register4;
register2 := register2 + register7;
WHEN "00001010" =>
register6 := register1 + 40;
register3 := ((NOT register3) + 1) XOR register3;
register4 := register4 + register5;
WHEN "00001011" =>
register2 := register1 + register6 + register2;
register3 := register4 + register3;
WHEN "00001100" =>
register1 := register1 * register6 * register2;
register2 := register3 * 44;
WHEN "00001101" =>
register1 := register2 + register1;
WHEN "00001110" =>
register1 := register3 + register1;
WHEN "00001111" =>
register1 := register1 srl 46;
output1 <= input17 + 47;
output2 <= input18 + 48;
WHEN "00010000" =>
output3 <= register1;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END jpegsd_alap_description; | gpl-3.0 | ce115e92378843d0673eb37b38ee319d | 0.651907 | 3.148268 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/axi_lite_ipif_v2_0/82c7a66d/hdl/src/vhdl/address_decoder.vhd | 7 | 22,380 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: address_decoder.vhd
-- Version: v2.0
-- Description: Address decoder utilizing unconstrained arrays for Base
-- Address specification and ce number.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 08/09/2010 --
-- - updated the core with optimziation. Closed CR 574507
-- - combined the CE generation logic to further optimize the code.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.all;
use proc_common_v4_0.pselect_f;
use proc_common_v4_0.ipif_pkg.all;
use proc_common_v4_0.family_support.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_BUS_AWIDTH -- Address bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Bus_clk -- Clock
-- Bus_rst -- Reset
-- Address_In_Erly -- Adddress in
-- Address_Valid_Erly -- Address is valid
-- Bus_RNW -- Read or write registered
-- Bus_RNW_Erly -- Read or Write
-- CS_CE_ld_enable -- chip select and chip enable registered
-- Clear_CS_CE_Reg -- Clear_CS_CE_Reg clear
-- RW_CE_ld_enable -- Read or Write Chip Enable
-- CS_for_gaps -- CS generation for the gaps between address ranges
-- CS_Out -- Chip select
-- RdCE_Out -- Read Chip enable
-- WrCE_Out -- Write chip enable
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity address_decoder is
generic (
C_BUS_AWIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(0 to 31) := X"000001FF";
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_1000_0000", -- IP user0 base address
X"0000_0000_1000_01FF", -- IP user0 high address
X"0000_0000_1000_0200", -- IP user1 base address
X"0000_0000_1000_02FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
8, -- User0 CE Number
1 -- User1 CE Number
);
C_FAMILY : string := "virtex6"
);
port (
Bus_clk : in std_logic;
Bus_rst : in std_logic;
-- PLB Interface signals
Address_In_Erly : in std_logic_vector(0 to C_BUS_AWIDTH-1);
Address_Valid_Erly : in std_logic;
Bus_RNW : in std_logic;
Bus_RNW_Erly : in std_logic;
-- Registering control signals
CS_CE_ld_enable : in std_logic;
Clear_CS_CE_Reg : in std_logic;
RW_CE_ld_enable : in std_logic;
CS_for_gaps : out std_logic;
-- Decode output signals
CS_Out : out std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
RdCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
WrCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1)
);
end entity address_decoder;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of address_decoder is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- local type declarations ----------------------------------------------------
type decode_bit_array_type is Array(natural range 0 to (
(C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of
integer;
type short_addr_array_type is Array(natural range 0 to
C_ARD_ADDR_RANGE_ARRAY'LENGTH-1) of
std_logic_vector(0 to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This function converts a 64 bit address range array to a AWIDTH bit
-- address range array.
-------------------------------------------------------------------------------
function slv64_2_slv_awidth(slv64_addr_array : SLV64_ARRAY_TYPE;
awidth : integer)
return short_addr_array_type is
variable temp_addr : std_logic_vector(0 to 63);
variable slv_array : short_addr_array_type;
begin
for array_index in 0 to slv64_addr_array'length-1 loop
temp_addr := slv64_addr_array(array_index);
slv_array(array_index) := temp_addr((64-awidth) to 63);
end loop;
return(slv_array);
end function slv64_2_slv_awidth;
-------------------------------------------------------------------------------
--Function Addr_bits
--function to convert an address range (base address and an upper address)
--into the number of upper address bits needed for decoding a device
--select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits (x,y : std_logic_vector(0 to C_BUS_AWIDTH-1))
return integer is
variable addr_nor : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
addr_nor := x xor y;
for i in 0 to C_BUS_AWIDTH-1 loop
if addr_nor(i)='1' then
return i;
end if;
end loop;
--coverage off
return(C_BUS_AWIDTH);
--coverage on
end function Addr_Bits;
-------------------------------------------------------------------------------
--Function Get_Addr_Bits
--function calculates the array which has the decode bits for the each address
--range.
-------------------------------------------------------------------------------
function Get_Addr_Bits (baseaddrs : short_addr_array_type)
return decode_bit_array_type is
variable num_bits : decode_bit_array_type;
begin
for i in 0 to ((baseaddrs'length)/2)-1 loop
num_bits(i) := Addr_Bits (baseaddrs(i*2),
baseaddrs(i*2+1));
end loop;
return(num_bits);
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- NEEDED_ADDR_BITS
--
-- Function Description:
-- This function calculates the number of address bits required
-- to support the CE generation logic. This is determined by
-- multiplying the number of CEs for an address space by the
-- data width of the address space (in bytes). Each address
-- space entry is processed and the biggest of the spaces is
-- used to set the number of address bits required to be latched
-- and used for CE decoding. A minimum value of 1 is returned by
-- this function.
--
-------------------------------------------------------------------------------
function needed_addr_bits (ce_array : INTEGER_ARRAY_TYPE)
return integer is
constant NUM_CE_ENTRIES : integer := CE_ARRAY'length;
variable biggest : integer := 2;
variable req_ce_addr_size : integer := 0;
variable num_addr_bits : integer := 0;
begin
for i in 0 to NUM_CE_ENTRIES-1 loop
req_ce_addr_size := ce_array(i) * 4;
if (req_ce_addr_size > biggest) Then
biggest := req_ce_addr_size;
end if;
end loop;
num_addr_bits := clog2(biggest);
return(num_addr_bits);
end function NEEDED_ADDR_BITS;
-----------------------------------------------------------------------------
-- Function calc_high_address
--
-- This function is used to calculate the high address of the each address
-- range
-----------------------------------------------------------------------------
function calc_high_address (high_address : short_addr_array_type;
index : integer) return std_logic_vector is
variable calc_high_addr : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
If (index = (C_ARD_ADDR_RANGE_ARRAY'length/2-1)) Then
calc_high_addr := C_S_AXI_MIN_SIZE(32-C_BUS_AWIDTH to 31);
else
calc_high_addr := high_address(index*2+2);
end if;
return(calc_high_addr);
end function calc_high_address;
----------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant ARD_ADDR_RANGE_ARRAY : short_addr_array_type :=
slv64_2_slv_awidth(C_ARD_ADDR_RANGE_ARRAY,
C_BUS_AWIDTH);
constant NUM_BASE_ADDRS : integer := (C_ARD_ADDR_RANGE_ARRAY'length)/2;
constant DECODE_BITS : decode_bit_array_type :=
Get_Addr_Bits(ARD_ADDR_RANGE_ARRAY);
constant NUM_CE_SIGNALS : integer :=
calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant NUM_S_H_ADDR_BITS : integer :=
needed_addr_bits(C_ARD_NUM_CE_ARRAY);
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal pselect_hit_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal cs_out_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal ce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal rdce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal ce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); --
signal cs_ce_clr : std_logic;
signal addr_out_s_h : std_logic_vector(0 to NUM_S_H_ADDR_BITS-1);
signal Bus_RNW_reg : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-- Register clears
cs_ce_clr <= not Bus_rst or Clear_CS_CE_Reg;
addr_out_s_h <= Address_In_Erly(C_BUS_AWIDTH-NUM_S_H_ADDR_BITS
to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- MEM_DECODE_GEN: Universal Address Decode Block
-------------------------------------------------------------------------------
MEM_DECODE_GEN: for bar_index in 0 to NUM_BASE_ADDRS-1 generate
---------------
constant CE_INDEX_START : integer
:= calc_start_ce_index(C_ARD_NUM_CE_ARRAY,bar_index);
constant CE_ADDR_SIZE : Integer range 0 to 15
:= clog2(C_ARD_NUM_CE_ARRAY(bar_index));
constant OFFSET : integer := 2;
constant BASE_ADDR_x : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= ARD_ADDR_RANGE_ARRAY(bar_index*2+1);
constant HIGH_ADDR_X : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= calc_high_address(ARD_ADDR_RANGE_ARRAY,bar_index);
--constant DECODE_BITS_0 : integer:= DECODE_BITS(0);
---------
begin
---------
-- GEN_FOR_MULTI_CS: Below logic generates the CS for decoded address
-- -----------------
GEN_FOR_MULTI_CS : if C_ARD_ADDR_RANGE_ARRAY'length > 2 generate
-- Instantiate the basic Base Address Decoders
MEM_SELECT_I: entity proc_common_v4_0.pselect_f
generic map
(
C_AB => DECODE_BITS(bar_index),
C_AW => C_BUS_AWIDTH,
C_BAR => ARD_ADDR_RANGE_ARRAY(bar_index*2),
C_FAMILY => C_FAMILY
)
port map
(
A => Address_In_Erly, -- [in]
AValid => Address_Valid_Erly, -- [in]
CS => pselect_hit_i(bar_index) -- [out]
);
end generate GEN_FOR_MULTI_CS;
-- GEN_FOR_ONE_CS: below logic decodes the CS for single address range
-- ---------------
GEN_FOR_ONE_CS : if C_ARD_ADDR_RANGE_ARRAY'length = 2 generate
pselect_hit_i(bar_index) <= Address_Valid_Erly;
end generate GEN_FOR_ONE_CS;
-- Instantate backend registers for the Chip Selects
BKEND_CS_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(Bus_Rst='0' or Clear_CS_CE_Reg = '1')then
cs_out_i(bar_index) <= '0';
elsif(CS_CE_ld_enable='1')then
cs_out_i(bar_index) <= pselect_hit_i(bar_index);
end if;
end if;
end process BKEND_CS_REG;
-------------------------------------------------------------------------
-- PER_CE_GEN: Now expand the individual CEs for each base address.
-------------------------------------------------------------------------
PER_CE_GEN: for j in 0 to C_ARD_NUM_CE_ARRAY(bar_index) - 1 generate
-----------
begin
-----------
----------------------------------------------------------------------
-- CE decoders for multiple CE's
----------------------------------------------------------------------
MULTIPLE_CES_THIS_CS_GEN : if CE_ADDR_SIZE > 0 generate
constant BAR : std_logic_vector(0 to CE_ADDR_SIZE-1) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
CE_I : entity proc_common_v4_0.pselect_f
generic map (
C_AB => CE_ADDR_SIZE ,
C_AW => CE_ADDR_SIZE ,
C_BAR => BAR ,
C_FAMILY => C_FAMILY
)
port map (
A => addr_out_s_h
(NUM_S_H_ADDR_BITS-OFFSET-CE_ADDR_SIZE
to NUM_S_H_ADDR_BITS - OFFSET - 1) ,
AValid => pselect_hit_i(bar_index) ,
CS => ce_expnd_i(CE_INDEX_START+j)
);
end generate MULTIPLE_CES_THIS_CS_GEN;
--------------------------------------
----------------------------------------------------------------------
-- SINGLE_CE_THIS_CS_GEN: CE decoders for single CE
----------------------------------------------------------------------
SINGLE_CE_THIS_CS_GEN : if CE_ADDR_SIZE = 0 generate
ce_expnd_i(CE_INDEX_START+j) <= pselect_hit_i(bar_index);
end generate;
-------------
end generate PER_CE_GEN;
------------------------
end generate MEM_DECODE_GEN;
-- RNW_REG_P: Register the incoming RNW signal at the time of registering the
-- address. This is need to generate the CE's separately.
RNW_REG_P:process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(RW_CE_ld_enable='1')then
Bus_RNW_reg <= Bus_RNW_Erly;
end if;
end if;
end process RNW_REG_P;
---------------------------------------------------------------------------
-- GEN_BKEND_CE_REGISTERS
-- This ForGen implements the backend registering for
-- the CE, RdCE, and WrCE output buses.
---------------------------------------------------------------------------
GEN_BKEND_CE_REGISTERS : for ce_index in 0 to NUM_CE_SIGNALS-1 generate
signal rdce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
------
begin
------
BKEND_RDCE_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(cs_ce_clr='1')then
ce_out_i(ce_index) <= '0';
elsif(RW_CE_ld_enable='1')then
ce_out_i(ce_index) <= ce_expnd_i(ce_index);
end if;
end if;
end process BKEND_RDCE_REG;
rdce_out_i(ce_index) <= ce_out_i(ce_index) and Bus_RNW_reg;
wrce_out_i(ce_index) <= ce_out_i(ce_index) and not Bus_RNW_reg;
-------------------------------
end generate GEN_BKEND_CE_REGISTERS;
-------------------------------------------------------------------------------
CS_for_gaps <= '0'; -- Removed the GAP adecoder logic
---------------------------------
CS_Out <= cs_out_i ;
RdCE_Out <= rdce_out_i ;
WrCE_Out <= wrce_out_i ;
end architecture IMP;
| apache-2.0 | 2ed350694abf450f968a5e8d5d4f2a79 | 0.465818 | 4.507553 | false | false | false | false |
marceloboeira/vhdl-examples | 006-ULA/lib/mux.vhd | 1 | 668 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MUX_PROCESS is
Port (A : in STD_LOGIC_VECTOR (7 downto 0);
B : in STD_LOGIC_VECTOR (7 downto 0);
C : in STD_LOGIC_VECTOR (7 downto 0);
D : in STD_LOGIC_VECTOR (7 downto 0);
S : in STD_LOGIC_VECTOR (1 downto 0);
O : out STD_LOGIC_VECTOR (7 downto 0));
end MUX_PROCESS;
architecture Behavioral of MUX_PROCESS is
begin
process (A, B, C, D, S)
begin
case S is
when "00" => O <= A;
when "01" => O <= B;
when "10" => O <= C;
when "11" => O <= D;
when others=> O <= "00000000";
end case;
end process;
end Behavioral;
| mit | b10285dd40543de65fa559dfb96b6958 | 0.546407 | 3.13615 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-30bits_outputs31bits/5-EWF/metaheurísticas/ewf_spea2.vhd | 1 | 3,121 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-17.11:31:40)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY ewf_spea2_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2: IN unsigned(0 TO 30);
output1, output2, output3, output4, output5: OUT unsigned(0 TO 31));
END ewf_spea2_entity;
ARCHITECTURE ewf_spea2_description OF ewf_spea2_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register4: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register5: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register6: unsigned(0 TO 31) := "00000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
register2 := input2 + 2;
WHEN "00000010" =>
register3 := register1 + 4;
WHEN "00000011" =>
register4 := register3 + 6;
WHEN "00000100" =>
register4 := register2 + register4;
WHEN "00000101" =>
register5 := register4 * 8;
WHEN "00000110" =>
register5 := register3 + register5;
WHEN "00000111" =>
register3 := register3 + register5;
register6 := register4 * 10;
WHEN "00001000" =>
register3 := register3 * 12;
register6 := register2 + register6;
register4 := register4 + register5;
WHEN "00001001" =>
output1 <= register6 + register4;
register2 := register2 + register6;
WHEN "00001010" =>
register2 := register2 * 15;
register3 := register1 + register3;
WHEN "00001011" =>
register1 := register1 + register3;
WHEN "00001100" =>
register1 := register1 * 17;
WHEN "00001101" =>
register1 := register1 + 19;
register4 := register5 + register3;
WHEN "00001110" =>
output2 <= register3 + register1;
register1 := register4 + 22;
WHEN "00001111" =>
register3 := register1 * 24;
WHEN "00010000" =>
register3 := register3 + 26;
WHEN "00010001" =>
output3 <= register1 + register3;
register1 := register2 + 29;
WHEN "00010010" =>
register2 := register1 + 31;
WHEN "00010011" =>
register2 := register2 * 33;
WHEN "00010100" =>
output4 <= register1 + register2;
register1 := register6 + register1;
WHEN "00010101" =>
register1 := register1 + 36;
WHEN "00010110" =>
register2 := register1 * 38;
WHEN "00010111" =>
register2 := register2 + 40;
WHEN "00011000" =>
output5 <= register1 + register2;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END ewf_spea2_description; | gpl-3.0 | 84ce986840fca6b46f80e8d2a959b4ca | 0.665812 | 3.327292 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/axi_intc_v4_1/28e93d3e/hdl/src/vhdl/intc_core.vhd | 1 | 135,910 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: intc_core.vhd
-- Version: v3.1
-- Description: Interrupt controller without a bus interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- axi_intc.vhd (wrapper for top level)
-- -- axi_lite_ipif.vhd
-- -- intc_core.vhd
--
-------------------------------------------------------------------------------
-- Author: PB
-- History:
-- PB 07/29/09
-- ^^^^^^^
-- - Initial release of v1.00.a
-- PB 03/26/10
--
-- - updated based on the xps_intc_v2_01_a
-- ~~~~~~
-- - Initial release of v2.00.a
-- - Updated by pkaruna
-- ^^^^^^^
-- SK 10/10/12
--
-- 1. Added cascade mode support in v1.03.a version of the core
-- 2. Updated major version of the core
-- ~~~~~~
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-- ^^^^^^^
-- SA 03/25/13
--
-- 1. Added software interrupt support in v3.1 version of the core
-- ~~~~~~
-- SA 09/05/13
--
-- 1. Added support for nested interrupts using ILR register in v4.1
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.log2;
use ieee.math_real.ceil;
use ieee.std_logic_misc.all;
library axi_intc_v4_1;
use axi_intc_v4_1.all;
library proc_common_v4_0;
use proc_common_v4_0.all;
use proc_common_v4_0.proc_common_pkg.all;
use proc_common_v4_0.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- -- Intc Parameters
-- C_DWIDTH -- Data bus width
-- C_NUM_INTR_INPUTS -- Number of interrupt inputs
-- C_NUM_SW_INTR -- Number of software interrupts
-- C_KIND_OF_INTR -- Kind of interrupt (0-Level/1-Edge)
-- C_KIND_OF_EDGE -- Kind of edge (0-falling/1-rising)
-- C_KIND_OF_LVL -- Kind of level (0-low/1-high)
-- C_ASYNC_INTR -- Interrupt is asynchronous (0-sync/1-async)
-- C_NUM_SYNC_FF -- Number of synchronization flip-flops for async interrupts
-- C_HAS_IPR -- Set to 1 if has Interrupt Pending Register
-- C_HAS_SIE -- Set to 1 if has Set Interrupt Enable Bits
-- Register
-- C_HAS_CIE -- Set to 1 if has Clear Interrupt Enable Bits
-- Register
-- C_HAS_IVR -- Set to 1 if has Interrupt Vector Register
-- C_HAS_ILR -- Set to 1 if has Interrupt Level Register for nested interupt support
-- C_IRQ_IS_LEVEL -- If set to 0 generates edge interrupt
-- -- If set to 1 generates level interrupt
-- C_IRQ_ACTIVE -- Defines the edge for output interrupt if
-- -- C_IRQ_IS_LEVEL=0 (0-FALLING/1-RISING)
-- -- Defines the level for output interrupt if
-- -- C_IRQ_IS_LEVEL=1 (0-LOW/1-HIGH)
-- C_IVR_RESET_VALUE -- Reset value for the vectroed interrupt registers in RAM
-- C_DISABLE_SYNCHRONIZERS -- If the processor clock and axi clock are of same
-- value then user can decide to disable this
-- C_MB_CLK_NOT_CONNECTED -- If the processor clock is not connected or used in design
-- C_HAS_FAST -- If user wants to choose the fast interrupt mode of the core
-- -- then it is needed to have this paraemter set. Default is Standard Mode interrupt
-- C_ENABLE_ASYNC -- This parameter is used only for Vivado standalone mode of the core, not used in RTL
-- C_EN_CASCADE_MODE -- If no. of interrupts goes beyond 32, then this parameter need to set
-- C_CASCADE_MASTER -- If cascade mode is set, then this parameter should be set to the first instance
-- -- of the core which is connected to the processor
-------------------------------------------------------------------------------
-- Definition of Ports:
-- Clocks and reset
-- Clk -- Clock
-- Rst -- Reset
-- Intc Interface Signals
-- Intr -- Input Interruput request
-- Reg_addr -- Address bus
-- Bus2ip_rdce -- Read
-- Bus2ip_wrce -- Write
-- Wr_data -- Write data bus
-- Rd_data -- Read data bus
-- Irq -- Output Interruput request
-- Processor_clk -- in put same as processor clock
-- Processor_rst -- in put same as processor reset
-- Processor_ack -- input Connected to processor ACK
-- Interrupt_address -- output Connected to processor interrupt address pins
-- Interrupt_address_in-- Input this is coming from lower level module in case
-- -- the cascade mode is set and all AXI INTC instances are marked
-- -- as C_HAS_FAST = 1
-- Processor_ack_out -- Output this is going to lower level module in case
-- -- the cascade mode is set and all AXI INTC instances are marked
-- -- as C_HAS_FAST = 1
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Entity
------------------------------------------------------------------------------
entity intc_core is
generic
(
C_FAMILY : string := "virtex6";
C_DWIDTH : integer := 32;
C_NUM_INTR_INPUTS : integer range 1 to 32 := 2;
C_NUM_SW_INTR : integer range 0 to 31 := 0;
C_KIND_OF_INTR : std_logic_vector(31 downto 0)
:= "11111111111111111111111111111111";
C_KIND_OF_EDGE : std_logic_vector(31 downto 0)
:= "11111111111111111111111111111111";
C_KIND_OF_LVL : std_logic_vector(31 downto 0)
:= "11111111111111111111111111111111";
C_ASYNC_INTR : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
C_NUM_SYNC_FF : integer range 0 to 7 := 2;
C_HAS_IPR : integer range 0 to 1 := 1;
C_HAS_SIE : integer range 0 to 1 := 1;
C_HAS_CIE : integer range 0 to 1 := 1;
C_HAS_IVR : integer range 0 to 1 := 1;
C_HAS_ILR : integer range 0 to 1 := 0;
C_IRQ_IS_LEVEL : integer range 0 to 1 := 1;
C_IRQ_ACTIVE : std_logic := '1';
C_DISABLE_SYNCHRONIZERS : integer range 0 to 1 := 0;
C_MB_CLK_NOT_CONNECTED : integer range 0 to 1 := 0;
C_HAS_FAST : integer range 0 to 1 := 0;
C_IVAR_RESET_VALUE : std_logic_vector(31 downto 0) :=
"00000000000000000000000000010000";
C_EN_CASCADE_MODE : integer range 0 to 1 := 0; -- default no cascade mode, if set enable cascade mode
C_CASCADE_MASTER : integer range 0 to 1 := 0 -- default slave, if set become cascade master and connects ports to Processor
);
port
(
-- Inputs
Clk : in std_logic; --- AXI Clock
Rst_n : in std_logic; --- active low AXI Reset
Intr : in std_logic_vector(C_NUM_INTR_INPUTS - 1 downto 0);
Reg_addr : in std_logic_vector(6 downto 0);
Bus2ip_rdce : in std_logic_vector(0 to 16);
Bus2ip_wrce : in std_logic_vector(0 to 16);
Wr_data : in std_logic_vector(C_DWIDTH - 1 downto 0);
-- Outputs
Rd_data : out std_logic_vector(C_DWIDTH - 1 downto 0);
Processor_clk : in std_logic; --- MB Clk, clock from MicroBlaze
processor_rst : in std_logic; --- active high MB rst, reset from MicroBlaze
Irq : out std_logic;
Processor_ack : in std_logic_vector(1 downto 0); --- added for fast interrupt mode
Interrupt_address : out std_logic_vector(31 downto 0); --- added for fast interrupt mode
--
Interrupt_address_in : in std_logic_vector(31 downto 0);
Processor_ack_out : out std_logic_vector(1 downto 0)
--
);
-------------------------------------------------------------------------------
-- Attributes
-------------------------------------------------------------------------------
attribute buffer_type: string;
attribute buffer_type of Intr: signal is "none";
end intc_core;
------------------------------------------------------------------------------
-- Architecture
------------------------------------------------------------------------------
architecture imp of intc_core is
-- Component Declarations
-- ======================
constant C_NUM_INTR : integer := C_NUM_INTR_INPUTS + C_NUM_SW_INTR;
constant RESET_ACTIVE : std_logic := '0';
CONSTANT INDEX_BIT : INTEGER := INTEGER(CEIL(LOG2(REAL(C_NUM_INTR+1))));
constant MICROBLAZE_FIXED_ADDRESS : std_logic_vector := X"00000010";
CONSTANT IVR_ALL_ONES : std_logic_vector(INDEX_BIT-1 downto 0) := (others => '1');
--- *** --- Decision is pending for logic used - mail sent to Bsb on 3rd Oct, 2012
CONSTANT C_USE_METHOD : integer := 1;
--- *** ---
-- Signal declaration
-- ==================
signal processor_rst_n : std_logic;
signal ack_b01 : std_logic;
signal first_ack : std_logic;
signal first_ack_active : std_logic;
signal second_ack : std_logic;
signal first_ack_sync : std_logic;
signal second_ack_sync : std_logic;
signal second_ack_sync_d1 : std_logic;
signal second_ack_sync_d2 : std_logic;
signal second_ack_sync_d3 : std_logic;
signal second_ack_sync_mb_clk : std_logic;
signal Irq_i : std_logic;
signal ivr_data_in : std_logic_vector(INDEX_BIT - 1 downto 0);
signal wr_data_int : std_logic_vector(C_NUM_INTR - 1 downto 0);
signal mer_int : std_logic_vector(1 downto 0);
signal mer : std_logic_vector(C_DWIDTH - 1 downto 0);
signal sie : std_logic_vector(C_NUM_INTR - 1 downto 0);
signal cie : std_logic_vector(C_NUM_INTR - 1 downto 0);
signal iar : std_logic_vector(C_NUM_INTR - 1 downto 0);
signal ier : std_logic_vector(C_NUM_INTR - 1 downto 0);
signal isr_en : std_logic;
signal hw_intr : std_logic_vector(C_NUM_INTR_INPUTS - 1 downto 0);
signal isr_data_in : std_logic_vector(C_NUM_INTR_INPUTS - 1 downto 0);
signal isr : std_logic_vector(C_NUM_INTR - 1 downto 0);
signal ivr : std_logic_vector(INDEX_BIT - 1 downto 0);
signal ivr_out : std_logic_vector(C_DWIDTH - 1 downto 0);
signal ilr : std_logic_vector(INDEX_BIT downto 0);
signal ilr_out : std_logic_vector(C_DWIDTH - 1 downto 0);
signal imr : std_logic_vector(C_NUM_INTR - 1 downto 0);
signal imr_out : std_logic_vector(C_DWIDTH - 1 downto 0);
signal ipr : std_logic_vector(C_DWIDTH - 1 downto 0);
signal irq_gen_i : std_logic;
signal irq_gen : std_logic;
signal irq_gen_sync : std_logic;
signal read : std_logic;
signal ier_out : std_logic_vector(C_DWIDTH - 1 downto 0);
signal isr_out : std_logic_vector(C_DWIDTH - 1 downto 0);
signal ack_or_i : std_logic;
signal ack_or : std_logic;
signal ack_or_sync : std_logic;
signal read_ivar : std_logic;
signal write_ivar : std_logic;
signal isr_or : std_logic;
signal ivar_index_mb_clk : std_logic_vector(INDEX_BIT-1 downto 0);
signal ivar_index_axi_clk : std_logic_vector(INDEX_BIT-1 downto 0);
signal in_idle : std_logic;
signal in_idle_axi_clk : std_logic;
signal idle_and_irq : std_logic;
signal idle_and_irq_d1 : std_logic;
signal ivar_index_sample_en_i : std_logic;
signal ivar_index_sample_en : std_logic;
signal ivar_index_sample_en_mb_clk : std_logic;
signal irq_dis_sample_mb_clk : std_logic;
signal ivar_rd_addr_mb_clk : std_logic_vector(4 downto 0);
signal mer_0_sync : std_logic;
--signal bus2ip_rdce_fast : std_logic_vector(0 to 31);
--signal bus2ip_wrce_fast : std_logic_vector(0 to 31);
signal bus2ip_rdce_fast : std_logic;
signal bus2ip_wrce_fast : std_logic;
signal ivar_rd_data_axi_clk : std_logic_vector(C_DWIDTH - 1 downto 0);
signal ivar_rd_data_mb_clk : std_logic_vector(C_DWIDTH - 1 downto 0);
signal isr_ored_30_0_bits : std_logic;
signal Interrupt_address_in_reg_int : std_logic_vector(31 downto 0);
signal intr_31_deassert_info : std_logic;
signal intr_31_deasserted_d1 : std_logic;
signal intr_31_deasserted : std_logic;
-- --------------------------------------------------------------------------------------
-- -- Function to find logic OR of 32 bit width vector
-- --------------------------------------------------------------------------------------
-- Function OR32_VEC2STDLOGIC (vec_in : std_logic_vector) return std_logic is
-- variable or_out : std_logic := '0';
-- begin
-- for i in 0 to 31 loop
-- or_out := vec_in(i) or or_out;
-- end loop;
-- return or_out;
-- end function Or32_vec2stdlogic;
-- --------------------------------------------------------------------------------------
FUNCTION calc_ivar_ram_addr_bits (
constant C_NUM_INTR : integer)
RETURN integer is
begin
if (C_NUM_INTR > 16) then
RETURN 5;
else
RETURN 4;
end if;
end FUNCTION calc_ivar_ram_addr_bits;
-------------------------------------
FUNCTION calc_ivar_ram_depth (
constant C_NUM_INTR : integer)
RETURN integer is
begin
if (C_NUM_INTR > 16) then
RETURN 32;
else
RETURN 16;
end if;
end FUNCTION calc_ivar_ram_depth;
---------------------------------
CONSTANT IVAR_MEM_ADDR_LINES : INTEGER := calc_ivar_ram_addr_bits (C_NUM_INTR);
CONSTANT IVAR_MEM_DEPTH : INTEGER := calc_ivar_ram_depth (C_NUM_INTR);
--------------------------------------------------------------------------------------
-- Function to convert std_logic to std_logic_vector
--------------------------------------------------------------------------------------
Function scalar_to_vector (scalar_in : std_logic) return std_logic_vector is
variable vec_out : std_logic_vector(0 downto 0) := "0";
begin
vec_out(0) := scalar_in;
return vec_out;
end function scalar_to_vector;
--------------------------------------------------------------------------------------
-- Function to convert std_logic_vector to std_logic
--------------------------------------------------------------------------------------
Function vector_to_scalar (vec_in : std_logic_vector) return std_logic is
variable scalar_out : std_logic := '0';
begin
scalar_out := vec_in(0);
return scalar_out;
end function vector_to_scalar;
-- Begin of architecture
begin
-----
-- active low reset
processor_rst_n <= not Processor_rst;
read <= bus2ip_rdce(0) or -- for ISR
bus2ip_rdce(1) or -- for IPR
bus2ip_rdce(2) or -- for IER
bus2ip_rdce(6) or -- for IVR
bus2ip_rdce(7) or -- for MER
bus2ip_rdce(8) or -- for IMR
bus2ip_rdce(9); -- for ILR
--------------------------------------------------------------------------
-- GENERATING ALL REGISTERS
--------------------------------------------------------------------------
wr_data_int <= Wr_data(C_NUM_INTR - 1 downto 0);
-------------------------------------------------------------------------
-- GENERATING IVAR READ ENABLES
-------------------------------------------------------------------------
bus2ip_rdce_fast <= bus2ip_rdce(16);
bus2ip_wrce_fast <= bus2ip_wrce(16);
write_ivar <= bus2ip_wrce_fast;
read_ivar <= bus2ip_rdce_fast;
--------------------------------------------------------------------------
-- Process for generating ACK enable and type and syncing them to ACLK
--------------------------------------------------------------------------
ACK_EN_SYNC_ON_MB_CLK_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
--------------------------
NO_CASCADE_MASTER_MODE : if (C_EN_CASCADE_MODE = 0) and (C_CASCADE_MASTER = 0) generate
-----
begin
-----
-- dont bypass the processor ack to output
Processor_ack_out <= (others => '0');
-----------------------------------------
Processor_ack_EN_REG_P: process (Processor_ack) is
-----
begin
-----
ack_b01 <= (not Processor_ack(1)) and Processor_ack(0); -- ack = b01
end process Processor_ack_EN_REG_P;
-----------------------------------------
first_ack_active_REG_P: process (Processor_clk) is
-----
begin
-----
if (Processor_clk'event and Processor_clk = '1') then
if (processor_rst_n = RESET_ACTIVE) then
first_ack_active <= '0';
else
if (ack_b01 = '1') then
first_ack_active <= '1';
elsif (Processor_ack(1) = '1') then
first_ack_active <= '0';
else
first_ack_active <= first_ack_active;
end if;
end if;
end if;
end process first_ack_active_REG_P;
-----------------------------------------
first_second_ack_REG_P: process (Processor_clk) is
-----
begin
-----
if (Processor_clk'event and Processor_clk = '1') then
if (processor_rst_n = RESET_ACTIVE) then
first_ack <= '0';
second_ack <= '0';
else
first_ack <= ack_b01;
second_ack <= first_ack_active and Processor_ack(1);
end if;
end if;
end process first_second_ack_REG_P;
-----------------------------------------
ACK_EN_SYNC_EN_GEN: if ((C_DISABLE_SYNCHRONIZERS = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
--Synchronize first_ack to AXI clock domain
Processor_first_ack_EN_PULSE_SYNC_I: entity axi_intc_v4_1.pulse_synchronizer
port map (
CLK_1 => Processor_clk,
RESET_1_n => processor_rst_n,
DATA_IN => first_ack,
CLK_2 => Clk,
RESET_2_n => Rst_n,
SYNC_DATA_OUT => first_ack_sync
);
--------------------------------------------
--Synchronize second_ack to AXI clock domain
Processor_second_ack_EN_PULSE_SYNC_I: entity axi_intc_v4_1.pulse_synchronizer
port map (
CLK_1 => Processor_clk,
RESET_1_n => processor_rst_n,
DATA_IN => second_ack,
CLK_2 => Clk,
RESET_2_n => Rst_n,
SYNC_DATA_OUT => second_ack_sync
);
end generate ACK_EN_SYNC_EN_GEN;
-----------------------------------------
ACK_EN_SYNC_DISABLE_GEN: if ((C_DISABLE_SYNCHRONIZERS = 1) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
first_ack_sync <= first_ack;
second_ack_sync <= second_ack;
end generate ACK_EN_SYNC_DISABLE_GEN;
-----------------------------------------
second_ack_d2_reg_p: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
second_ack_sync_d1 <= '0';
second_ack_sync_d2 <= '0';
second_ack_sync_d3 <= '0';
else
second_ack_sync_d1 <= second_ack_sync;
second_ack_sync_d2 <= second_ack_sync_d1;
second_ack_sync_d3 <= second_ack_sync_d2;
end if;
end if;
end process second_ack_d2_reg_p;
-----------------------------------------
SECOND_ACK_SYNC_EN_GEN: if ((C_DISABLE_SYNCHRONIZERS = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
--Synchronize Second_ack_sync_d2 back to processor clock domain
Second_ack_EN_PULSE_SYNC_I: entity axi_intc_v4_1.pulse_synchronizer
port map (
CLK_1 => Clk,
RESET_1_n => Rst_n,
DATA_IN => second_ack_sync_d2,
CLK_2 => Processor_clk,
RESET_2_n => processor_rst_n,
SYNC_DATA_OUT => second_ack_sync_mb_clk
);
end generate SECOND_ACK_SYNC_EN_GEN;
-----------------------------------------
SECOND_ACK_SYNC_DISABLE_GEN: if ((C_DISABLE_SYNCHRONIZERS = 1) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
second_ack_sync_mb_clk <= second_ack_sync_d2;
--second_ack_sync_mb_clk <= second_ack_sync;
end generate SECOND_ACK_SYNC_DISABLE_GEN;
-----------------------------------------
end generate NO_CASCADE_MASTER_MODE;
-----------------------------
CASCADE_MASTER_MODE_10 : if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 0) generate
------------------------
-----
begin
-----
--------------------------------------------------
Processor_ack_out <= (Processor_ack(1) and (not isr_ored_30_0_bits)) & -- to avoide any delay the processor is
(Processor_ack(0) and (not isr_ored_30_0_bits)) ; -- simply passed to below modules
ack_b01 <= (not Processor_ack(1)) and Processor_ack(0); -- ack = b01
--------------------------------------------------
first_ack_active_REG_P: process (Processor_clk) is
-----
begin
-----
if (Processor_clk'event and Processor_clk = '1') then
if (processor_rst_n = RESET_ACTIVE) then
first_ack_active <= '0';
else
if (ack_b01 = '1')then
first_ack_active <= '1';
elsif((Processor_ack(1) = '1')
) then
first_ack_active <= '0';
else
first_ack_active <= first_ack_active;
end if;
end if;
end if;
end process first_ack_active_REG_P;
---------------------------
first_second_ack_REG_P: process (Processor_clk) is
-----
begin
-----
if (Processor_clk'event and Processor_clk = '1') then
if (processor_rst_n = RESET_ACTIVE) then
first_ack <= '0';
second_ack <= '0';
else
first_ack <= ack_b01;
second_ack <= first_ack_active and Processor_ack(1);
end if;
end if;
end process first_second_ack_REG_P;
-----------------------------------
ACK_EN_SYNC_EN_GEN: if ((C_DISABLE_SYNCHRONIZERS = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
--Synchronize first_ack to AXI clock domain
Processor_first_ack_EN_PULSE_SYNC_I: entity axi_intc_v4_1.pulse_synchronizer
port map (
CLK_1 => Processor_clk,
RESET_1_n => processor_rst_n,
DATA_IN => first_ack,
CLK_2 => Clk,
RESET_2_n => Rst_n,
SYNC_DATA_OUT => first_ack_sync
);
--------------------------------------------
--Synchronize second_ack to AXI clock domain
Processor_second_ack_EN_PULSE_SYNC_I: entity axi_intc_v4_1.pulse_synchronizer
port map (
CLK_1 => Processor_clk,
RESET_1_n => processor_rst_n,
DATA_IN => second_ack,
CLK_2 => Clk,
RESET_2_n => Rst_n,
SYNC_DATA_OUT => second_ack_sync
);
--------------------------------------------
end generate ACK_EN_SYNC_EN_GEN;
--------------------------------------------
ACK_EN_SYNC_DISABLE_GEN: if ((C_DISABLE_SYNCHRONIZERS = 1) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
first_ack_sync <= first_ack;
second_ack_sync <= second_ack;
end generate ACK_EN_SYNC_DISABLE_GEN;
--------------------------------------------
second_ack_d2_reg_p: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
second_ack_sync_d1 <= '0';
second_ack_sync_d2 <= '0';
second_ack_sync_d3 <= '0';
else
second_ack_sync_d1 <= second_ack_sync;
second_ack_sync_d2 <= second_ack_sync_d1;
second_ack_sync_d3 <= second_ack_sync_d2;
end if;
end if;
end process second_ack_d2_reg_p;
--------------------------------------------
SECOND_ACK_SYNC_EN_GEN: if ((C_DISABLE_SYNCHRONIZERS = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
--Synchronize Second_ack_sync_d2 back to processor clock domain
Second_ack_EN_PULSE_SYNC_I: entity axi_intc_v4_1.pulse_synchronizer
port map (
CLK_1 => Clk,
RESET_1_n => Rst_n,
DATA_IN => second_ack_sync_d2,
CLK_2 => Processor_clk,
RESET_2_n => processor_rst_n,
SYNC_DATA_OUT => second_ack_sync_mb_clk
);
end generate SECOND_ACK_SYNC_EN_GEN;
--------------------------------------------
SECOND_ACK_SYNC_DISABLE_GEN: if ((C_DISABLE_SYNCHRONIZERS = 1) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
-----
begin
-----
second_ack_sync_mb_clk <= second_ack_sync_d2;
--second_ack_sync_mb_clk <= second_ack_sync;
end generate SECOND_ACK_SYNC_DISABLE_GEN;
--------------------------------------------
end generate CASCADE_MASTER_MODE_10;
-----------------------------
CASCADE_MASTER_MODE_11 : if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 1) generate
------------------------
-----
begin
-----
--------------------------------------------------
Processor_ack_out <= (Processor_ack(1) and (not isr_ored_30_0_bits)) &
(Processor_ack(0) and (not isr_ored_30_0_bits)) ;
ack_b01 <= (not Processor_ack(1)) and Processor_ack(0); -- ack = b01
--------------------------------------------------
first_ack_active_REG_P: process (Processor_clk) is
-----
begin
-----
if (Processor_clk'event and Processor_clk = '1') then
if (processor_rst_n = RESET_ACTIVE) then
first_ack_active <= '0';
else
if (ack_b01 = '1')then
first_ack_active <= '1';
elsif((Processor_ack(1) = '1')
) then
first_ack_active <= '0';
else
first_ack_active <= first_ack_active;
end if;
end if;
end if;
end process first_ack_active_REG_P;
---------------------------
first_second_ack_REG_P: process (Processor_clk) is
-----
begin
-----
if (Processor_clk'event and Processor_clk = '1') then
if (processor_rst_n = RESET_ACTIVE) then
first_ack <= '0';
second_ack <= '0';
else
first_ack <= ack_b01;
second_ack <= first_ack_active and Processor_ack(1);
end if;
end if;
end process first_second_ack_REG_P;
-----------------------------------
ACK_EN_SYNC_EN_GEN: if ((C_DISABLE_SYNCHRONIZERS = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
--Synchronize first_ack to AXI clock domain
Processor_first_ack_EN_PULSE_SYNC_I: entity axi_intc_v4_1.pulse_synchronizer
port map (
CLK_1 => Processor_clk,
RESET_1_n => processor_rst_n,
DATA_IN => first_ack,
CLK_2 => Clk,
RESET_2_n => Rst_n,
SYNC_DATA_OUT => first_ack_sync
);
--Synchronize second_ack to AXI clock domain
Processor_second_ack_EN_PULSE_SYNC_I: entity axi_intc_v4_1.pulse_synchronizer
port map (
CLK_1 => Processor_clk,
RESET_1_n => processor_rst_n,
DATA_IN => second_ack,
CLK_2 => Clk,
RESET_2_n => Rst_n,
SYNC_DATA_OUT => second_ack_sync
);
end generate ACK_EN_SYNC_EN_GEN;
------------------------------------
ACK_EN_SYNC_DISABLE_GEN: if ((C_DISABLE_SYNCHRONIZERS = 1) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
-----
begin
-----
first_ack_sync <= first_ack;
second_ack_sync <= second_ack;
end generate ACK_EN_SYNC_DISABLE_GEN;
------------------------------------
second_ack_d2_reg_p: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
second_ack_sync_d1 <= '0';
second_ack_sync_d2 <= '0';
second_ack_sync_d3 <= '0';
else
second_ack_sync_d1 <= second_ack_sync;
second_ack_sync_d2 <= second_ack_sync_d1;
second_ack_sync_d3 <= second_ack_sync_d2;
end if;
end if;
end process second_ack_d2_reg_p;
------------------------------------
SECOND_ACK_SYNC_EN_GEN: if ((C_DISABLE_SYNCHRONIZERS = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
--Synchronize Second_ack_sync_d2 back to processor clock domain
Second_ack_EN_PULSE_SYNC_I: entity axi_intc_v4_1.pulse_synchronizer
port map (
CLK_1 => Clk,
RESET_1_n => Rst_n,
DATA_IN => second_ack_sync_d2,
CLK_2 => Processor_clk,
RESET_2_n => processor_rst_n,
SYNC_DATA_OUT => second_ack_sync_mb_clk
);
end generate SECOND_ACK_SYNC_EN_GEN;
------------------------------------
SECOND_ACK_SYNC_DISABLE_GEN: if ((C_DISABLE_SYNCHRONIZERS = 1) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
second_ack_sync_mb_clk <= second_ack_sync_d2;
--second_ack_sync_mb_clk <= second_ack_sync;
end generate SECOND_ACK_SYNC_DISABLE_GEN;
------------------------------------
end generate CASCADE_MASTER_MODE_11;
-----------------------------
end generate ACK_EN_SYNC_ON_MB_CLK_GEN;
--------------------------------------------------------------------------
-- Process for generating ACK enable and type and syncing them to ACLK
--------------------------------------------------------------------------
ACK_EN_SYNC_ON_AXI_CLK_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 1)) generate
NO_CASCADE_MASTER : if (C_EN_CASCADE_MODE = 0) and (C_CASCADE_MASTER = 0) generate
-----
begin
-----
-- dont bypass the processor ack to output
Processor_ack_out <= (others => '0');
-----------------
Processor_ack_EN_REG_P: process (Processor_ack) is
-----
begin
-----
ack_b01 <= (not Processor_ack(1)) and Processor_ack(0); -- ack = b01
end process Processor_ack_EN_REG_P;
-----------------------------------
first_ack_active_REG_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
first_ack_active <= '0';
else
if (ack_b01 = '1') then
first_ack_active <= '1';
elsif (Processor_ack(1) = '1') then
first_ack_active <= '0';
else
first_ack_active <= first_ack_active;
end if;
end if;
end if;
end process first_ack_active_REG_P;
-----------------------------------
first_second_ack_REG_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
first_ack <= '0';
second_ack <= '0';
else
first_ack <= ack_b01;
second_ack <= first_ack_active and Processor_ack(1);
end if;
end if;
end process first_second_ack_REG_P;
-----------------------------------
first_ack_sync <= first_ack;
second_ack_sync <= second_ack;
-----------------------------------
second_ack_d2_reg_p: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
second_ack_sync_d1 <= '0';
second_ack_sync_d2 <= '0';
second_ack_sync_d3 <= '0';
else
second_ack_sync_d1 <= second_ack_sync;
second_ack_sync_d2 <= second_ack_sync_d1;
second_ack_sync_d3 <= second_ack_sync_d2;
end if;
end if;
end process second_ack_d2_reg_p;
-----------------------------------
second_ack_sync_mb_clk <= second_ack_sync_d2;
end generate NO_CASCADE_MASTER;
-------------------------------
CASCADE_MASTER_MODE_10 : if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 0) generate
------------------------
-----
begin
-----
--------------------------------------------------
Processor_ack_out <= (Processor_ack(1) and (not isr_ored_30_0_bits)) &
(Processor_ack(0) and (not isr_ored_30_0_bits)) ;
ack_b01 <= (not Processor_ack(1)) and Processor_ack(0); -- ack = b01
--------------------------------------------------
first_ack_active_REG_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
first_ack_active <= '0';
else
if (ack_b01 = '1') then
first_ack_active <= '1';
elsif((Processor_ack(1) = '1')
)then
first_ack_active <= '0';
else
first_ack_active <= first_ack_active;
end if;
end if;
end if;
end process first_ack_active_REG_P;
-----------------------------------
first_second_ack_REG_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
first_ack <= '0';
second_ack <= '0';
else
first_ack <= ack_b01;
second_ack <= first_ack_active and Processor_ack(1);
end if;
end if;
end process first_second_ack_REG_P;
-----------------------------------
first_ack_sync <= first_ack;
second_ack_sync <= second_ack;
-----------------------------------
second_ack_d2_reg_p: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
second_ack_sync_d1 <= '0';
second_ack_sync_d2 <= '0';
second_ack_sync_d3 <= '0';
else
second_ack_sync_d1 <= second_ack_sync;
second_ack_sync_d2 <= second_ack_sync_d1;
second_ack_sync_d3 <= second_ack_sync_d2;
end if;
end if;
end process second_ack_d2_reg_p;
-----------------------------------
second_ack_sync_mb_clk <= second_ack_sync_d2;
end generate CASCADE_MASTER_MODE_10;
-------------------------------
CASCADE_MASTER_MODE_11 : if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 1) generate
-----
begin
-----
--------------------------------------------------
Processor_ack_out <= (Processor_ack(1) and (not isr_ored_30_0_bits)) &
(Processor_ack(0) and (not isr_ored_30_0_bits)) ;
ack_b01 <= (not Processor_ack(1)) and Processor_ack(0); -- ack = b01
--------------------------------------------------
first_ack_active_REG_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
first_ack_active <= '0';
else
if (ack_b01 = '1') then
first_ack_active <= '1';
elsif((Processor_ack(1) = '1')-- and
--(isr(31) = '0') and
--(ier(31) = '0') -- and
-- (isr_ored_30_0_bits = '1')
)then
first_ack_active <= '0';
else
first_ack_active <= first_ack_active;
end if;
end if;
end if;
end process first_ack_active_REG_P;
first_second_ack_REG_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
first_ack <= '0';
second_ack <= '0';
else
first_ack <= ack_b01;
second_ack <= first_ack_active and Processor_ack(1);
end if;
end if;
end process first_second_ack_REG_P;
-----------------------------------
first_ack_sync <= first_ack;
second_ack_sync <= second_ack;
-----------------------------------
second_ack_d2_reg_p: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
second_ack_sync_d1 <= '0';
second_ack_sync_d2 <= '0';
second_ack_sync_d3 <= '0';
else
second_ack_sync_d1 <= second_ack_sync;
second_ack_sync_d2 <= second_ack_sync_d1;
second_ack_sync_d3 <= second_ack_sync_d2;
end if;
end if;
end process second_ack_d2_reg_p;
-----------------------------------
second_ack_sync_mb_clk <= second_ack_sync_d2;
--second_ack_sync_mb_clk <= second_ack_sync;
-----------------------------------
end generate CASCADE_MASTER_MODE_11;
-------------------------------
----------------------------------------
end generate ACK_EN_SYNC_ON_AXI_CLK_GEN;
SECOND_ACK_FAST_0_GEN: if (C_HAS_FAST = 0) generate
-----
begin
-----
second_ack_sync_mb_clk <= ack_or_sync;
end generate SECOND_ACK_FAST_0_GEN;
--------------------------------------------------------------------------
-- Process MER_ME_P for MER ME bit generation
--------------------------------------------------------------------------
MER_ME_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
mer_int(0) <= '0';
elsif (bus2ip_wrce(7) = '1') then
mer_int(0) <= Wr_data(0);
end if;
end if;
end process MER_ME_P;
--------------------------------------------------------------------------
-- Process MER_HIE_P for generating MER HIE bit
--------------------------------------------------------------------------
MER_HIE_P: process (Clk)is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
mer_int(1) <= '0';
elsif ((bus2ip_wrce(7) = '1') and (mer_int(1) = '0')) then
mer_int(1) <= Wr_data(1);
end if;
end if;
end process MER_HIE_P;
-----------------------------------
mer(1 downto 0) <= mer_int;
mer(C_DWIDTH - 1 downto 2) <= (others => '0');
-----------------------------------
----------------------------------------------------------------------
-- Generate SIE if (C_HAS_SIE = 1)
----------------------------------------------------------------------
SIE_GEN: if (C_HAS_SIE = 1) generate
-----
begin
-----
SIE_BIT_GEN : for i in 0 to (C_NUM_INTR - 1) generate
--------------------------------------------------------------
-- Process SIE_P for generating SIE register
--------------------------------------------------------------
SIE_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if ((Rst_n = RESET_ACTIVE) or (sie(i) = '1')) then
sie(i) <= '0';
elsif (bus2ip_wrce(4) = '1') then
sie(i) <= wr_data_int(i);
end if;
end if;
end process SIE_P;
end generate SIE_BIT_GEN;
end generate SIE_GEN;
----------------------------------------------------------------------
-- Assign sie_out ALL ZEROS if (C_HAS_SIE = 0)
----------------------------------------------------------------------
SIE_NO_GEN: if (C_HAS_SIE = 0) generate
-----
begin
-----
sie <= (others => '0');
end generate SIE_NO_GEN;
----------------------------------------------------------------------
-- Generate CIE if (C_HAS_CIE = 1)
----------------------------------------------------------------------
CIE_GEN: if (C_HAS_CIE = 1) generate
-----
begin
-----
CIE_BIT_GEN : for i in 0 to (C_NUM_INTR - 1) generate
------------------------------------------------------------------
-- Process CIE_P for generating CIE register
------------------------------------------------------------------
CIE_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if ((Rst_n = RESET_ACTIVE) or (cie(i) = '1')) then
cie(i) <= '0';
elsif (bus2ip_wrce(5) = '1') then
cie(i) <= wr_data_int(i);
end if;
end if;
end process CIE_P;
end generate CIE_BIT_GEN;
end generate CIE_GEN;
----------------------------------------------------------------------
-- Assign cie_out ALL ZEROS if (C_HAS_CIE = 0)
----------------------------------------------------------------------
CIE_NO_GEN: if (C_HAS_CIE = 0) generate
cie <= (others => '0');
end generate CIE_NO_GEN;
-- Generating write enable & data input for ISR
isr_en <= mer(1) or bus2ip_wrce(0);
isr_data_in <= hw_intr when mer(1) = '1' else
Wr_data(C_NUM_INTR_INPUTS - 1 downto 0);
--------------------------------------------------------------------------
-- Generate Registers of width equal C_NUM_INTR
--------------------------------------------------------------------------
REG_GEN : for i in 0 to (C_NUM_INTR - 1) generate
-----
begin
-----
--IAR_NORMAL_MODE_GEN: if ((C_HAS_FAST = 0) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
IAR_NORMAL_MODE_GEN: if (C_HAS_FAST = 0) generate
-----
begin
-----
----------------------------------------------------------------------
-- Process FAST_IAR_BIT_P for generating IAR register
----------------------------------------------------------------------
IAR_NORMAL_BIT_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) or (iar(i) = '1') then
iar(i) <= '0';
elsif ((bus2ip_wrce(3) = '1')) then
iar(i) <= wr_data_int(i);
else
iar(i) <= '0';
end if;
end if;
end process IAR_NORMAL_BIT_P;
-----------------------------------
end generate IAR_NORMAL_MODE_GEN;
---------------------------------
IAR_FAST_MODE_GEN: if (C_HAS_FAST = 1) generate
-----
begin
-----
----------------------------------------------------------------------
-- Process FAST_IAR_BIT_P for generating IAR register
----------------------------------------------------------------------
IAR_FAST_BIT_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) or (iar(i) = '1') then
iar(i) <= '0';
elsif ((bus2ip_wrce(3) = '1') and (imr(i) = '0')) then
iar(i) <= wr_data_int(i);
elsif (imr(i) = '1') then
if (((C_KIND_OF_INTR(i) = '1') and (first_ack_sync = '1')) or
((C_KIND_OF_INTR(i) = '0') and (second_ack_sync = '1'))) then
if (i = TO_INTEGER(unsigned(ivar_index_axi_clk))) then -- -- clearing IAR based on Processor_ack in FAST_INTERRUPT mode
iar(i) <= '1';
else
iar(i) <= iar(i);
end if;
else
iar(i) <= iar(i);
end if;
else
iar(i) <= iar(i);
end if;
end if;
end process IAR_FAST_BIT_P;
-----------------------------------
end generate IAR_FAST_MODE_GEN;
-------------------------------
----------------------------------------------------------------------
-- Process IER_BIT_P for generating IER register
----------------------------------------------------------------------
IER_BIT_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if ((Rst_n = RESET_ACTIVE) or (cie(i) = '1')) then
ier(i) <= '0';
elsif (sie(i) = '1') then
ier(i) <= '1';
elsif (bus2ip_wrce(2) = '1') then
ier(i) <= wr_data_int(i);
end if;
end if;
end process IER_BIT_P;
----------------------------------------------------------------------
-- Process ISR_P for generating ISR register
----------------------------------------------------------------------
ISR_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if ((Rst_n = RESET_ACTIVE) or (iar(i) = '1')) then
isr(i) <= '0';
elsif (i < C_NUM_INTR_INPUTS) then
if (isr_en = '1') then
isr(i) <= isr_data_in(i);
end if;
elsif (i >= C_NUM_INTR_INPUTS) then
if (bus2ip_wrce(0) = '1') then
isr(i) <= Wr_data(i);
end if;
end if;
end if;
end process ISR_P;
----------------------------------------------------------------------
-- Process IMR_P for generating IMR(Interrrupt Mode Register) Register
----------------------------------------------------------------------
IMR_FAST_MODE_GEN: if (C_HAS_FAST = 1) generate
-----
begin
-----
IMR_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
imr(i) <= '0';
elsif bus2ip_wrce(8) = '1' then
imr(i) <= wr_data_int(i);
end if;
end if;
end process IMR_P;
end generate IMR_FAST_MODE_GEN;
-----------------------------------
end generate REG_GEN;
---------------------
---------------------------------------------------------------------------
-- Proces IVAR_REG_P for generating IVAR Registers
---------------------------------------------------------------------------
IVAR_FAST_MODE_GEN: if (C_HAS_FAST = 1) generate
-----
begin
-----
IVAR_REG_MEM_MB_CLK_GEN: if (C_MB_CLK_NOT_CONNECTED = 0) generate
IVAR_REG_MEM_I: entity axi_intc_v4_1.shared_ram_ivar
generic map (
C_WIDTH => C_DWIDTH,
C_DPRAM_DEPTH => IVAR_MEM_DEPTH,
C_ADDR_LINES => IVAR_MEM_ADDR_LINES,
C_IVAR_RESET_VALUE => C_IVAR_RESET_VALUE
)
port map (
Addra => Reg_addr(IVAR_MEM_ADDR_LINES-1 downto 0),
Addrb => ivar_rd_addr_mb_clk(IVAR_MEM_ADDR_LINES-1 downto 0),
Clka => Clk,
Clkb => Processor_clk,
Dina => wr_data,
--Dinb => (others => '0'),
--Ena => '1',
--Enb => '1',
Wea => write_ivar,
--Web => '0',
Douta => ivar_rd_data_axi_clk,
Doutb => ivar_rd_data_mb_clk
);
end generate IVAR_REG_MEM_MB_CLK_GEN;
IVAR_REG_MEM_AXI_CLK_GEN: if (C_MB_CLK_NOT_CONNECTED = 1) generate
IVAR_REG_MEM_I: entity axi_intc_v4_1.shared_ram_ivar
generic map (
C_WIDTH => C_DWIDTH,
C_DPRAM_DEPTH => IVAR_MEM_DEPTH,
C_ADDR_LINES => IVAR_MEM_ADDR_LINES,
C_IVAR_RESET_VALUE => C_IVAR_RESET_VALUE
)
port map (
Addra => Reg_addr(IVAR_MEM_ADDR_LINES-1 downto 0),
Addrb => ivar_rd_addr_mb_clk(IVAR_MEM_ADDR_LINES-1 downto 0),
Clka => Clk,
Clkb => Clk,
Dina => wr_data,
--Dinb => (others => '0'),
--Ena => '1',
--Enb => '1',
Wea => write_ivar,
--Web => '0',
Douta => ivar_rd_data_axi_clk,
Doutb => ivar_rd_data_mb_clk
);
end generate IVAR_REG_MEM_AXI_CLK_GEN;
end generate IVAR_FAST_MODE_GEN;
-----------------------------------------------------------------------
-- Generating ier_out & isr_out if C_NUM_INTR /= C_DWIDTH
-----------------------------------------------------------------------
REG_OUT_GEN_DWIDTH_NOT_EQ_NUM_INTR: if (C_NUM_INTR /= C_DWIDTH) generate
-----
begin
-----
ier_out(C_NUM_INTR - 1 downto 0) <= ier;
ier_out(C_DWIDTH - 1 downto C_NUM_INTR) <= (others => '0');
isr_out(C_NUM_INTR - 1 downto 0) <= isr;
isr_out(C_DWIDTH - 1 downto C_NUM_INTR) <= (others => '0');
imr_out(C_NUM_INTR - 1 downto 0) <= imr;
imr_out(C_DWIDTH - 1 downto C_NUM_INTR) <= (others => '0');
isr_ored_30_0_bits <= or_reduce(isr(C_NUM_INTR-1 downto 0));
end generate REG_OUT_GEN_DWIDTH_NOT_EQ_NUM_INTR;
------------------------------------------------------------------------
-- Generating ier_out & isr_out if C_NUM_INTR = C_DWIDTH
------------------------------------------------------------------------
REG_OUT_GEN_DWIDTH_EQ_NUM_INTR: if (C_NUM_INTR = C_DWIDTH) generate
-----
begin
-----
ier_out <= ier;
isr_out <= isr;
imr_out <= imr;
isr_ored_30_0_bits <= or_reduce(isr(C_NUM_INTR-2 downto 0));
end generate REG_OUT_GEN_DWIDTH_EQ_NUM_INTR;
ilr_out (INDEX_BIT-1 downto 0) <= ilr(INDEX_BIT - 1 downto 0);
ilr_out (C_DWIDTH-1 downto INDEX_BIT) <= (others => '1') when ilr(INDEX_BIT) = '1' else
(others => '0');
ivr_out (INDEX_BIT-1 downto 0) <= ivr;
ivr_out (C_DWIDTH-1 downto INDEX_BIT) <= (others => '1') when ((ivr = IVR_ALL_ONES)) else
(others => '0');
--------------------------------------------------------------------------
-- Generate IPR if (C_HAS_IPR = 1)
--------------------------------------------------------------------------
IPR_GEN: if (C_HAS_IPR = 1) generate
----------------------------------------------------------------------
-- Process IPR_P for generating IPR register
----------------------------------------------------------------------
IPR_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
ipr <= (others => '0');
else
ipr <= isr_out and ier_out;
end if;
end if;
end process IPR_P;
------------------
end generate IPR_GEN;
---------------------
--------------------------------------------------------------------------
-- Assign IPR ALL ZEROS if (C_HAS_IPR = 0)
--------------------------------------------------------------------------
IPR_NO_GEN: if (C_HAS_IPR = 0) generate
ipr <= (others => '0');
end generate IPR_NO_GEN;
--------------------------------------------------------------------------
-- Generate IVR if (C_HAS_IVR = 1 or C_HAS_FAST = 1)
--------------------------------------------------------------------------
IVR_GEN: if ((C_HAS_IVR = 1) or (C_HAS_FAST = 1)) generate
begin
----------------------------------------------------------------------
-- Process IVR_DATA_GEN_P for generating interrupt vector address
----------------------------------------------------------------------
IVR_DATA_GEN_P: process (isr, ier) is
variable ivr_in : std_logic_vector(INDEX_BIT - 1 downto 0)
:= (others => '1');
-----
begin
-----
for i in 0 to (C_NUM_INTR - 1) loop
if ((isr(i) = '1') and (ier(i) = '1')) then
--ivr_in := CONV_STD_LOGIC_VECTOR(i, INDEX_BIT);
ivr_in := std_logic_vector(to_unsigned(i, INDEX_BIT));
exit;
else
ivr_in := (others => '1');
end if;
end loop;
ivr_data_in <= ivr_in;
end process IVR_DATA_GEN_P;
----------------------------------------------------------------------
-- Process IVR_P for generating IVR register
----------------------------------------------------------------------
IVR_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
ivr <= (others => '1');
else
ivr <= ivr_data_in;
end if;
end if;
end process IVR_P;
end generate IVR_GEN;
--------------------------------------------------------------------------
-- Assign IVR ALL ONES if (C_HAS_IVR = 0) and (C_HAS_FAST = 0)
--------------------------------------------------------------------------
IVR_NO_GEN: if ((C_HAS_IVR = 0) and (C_HAS_FAST = 0)) generate
ivr <= (others => '1');
end generate IVR_NO_GEN;
--------------------------------------------------------------------------
-- Generate ILR if (C_HAS_ILR = 1)
--------------------------------------------------------------------------
ILR_GEN: if (C_HAS_ILR = 1) generate
begin
----------------------------------------------------------------------
-- Process ILR_P for generating ILR register
----------------------------------------------------------------------
ILR_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
ilr <= (others => '1');
elsif (bus2ip_wrce(9) = '1') then
ilr <= Wr_data(INDEX_BIT downto 0);
end if;
end if;
end process ILR_P;
end generate ILR_GEN;
--------------------------------------------------------------------------
-- Assign ILR ALL ONES if (C_HAS_ILR = 0)
--------------------------------------------------------------------------
ILR_NO_GEN: if (C_HAS_ILR = 0) generate
begin
ilr <= (others => '1');
end generate ILR_NO_GEN;
--------------------------------------------------------------------------
-- DETECTING HW INTERRUPT
--------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Detecting the interrupts
---------------------------------------------------------------------------
INTR_DETECT_GEN: for i in 0 to C_NUM_INTR_INPUTS - 1 generate
signal synced_intr : std_logic := '0';
begin
-----------------------------------------------------------------------
-- Generating the synchronization flip-flops if C_ASYNC_INTR(i) = 1
-----------------------------------------------------------------------
ASYNC_GEN: if C_ASYNC_INTR(i) = '1' and C_NUM_SYNC_FF > 0 generate
signal intr_ff : std_logic_vector(0 to C_NUM_SYNC_FF - 1) := (others => '0');
attribute ASYNC_REG : string;
attribute ASYNC_REG of intr_ff : signal is "TRUE";
begin
--------------------------------------------
-- Process SYNC_P to synchronize hw_intr
--------------------------------------------
SYNC_P : process (Clk) is
begin
if Clk'event and Clk = '1' then
intr_ff(0) <= Intr(i);
for k in intr_ff'left to intr_ff'right - 1 loop
intr_ff(k + 1) <= intr_ff(k);
end loop;
end if;
end process SYNC_P;
synced_intr <= intr_ff(intr_ff'right);
------------------------------
end generate ASYNC_GEN;
-----------------------------------------------------------------------
-- No synchronization flip-flops if C_ASYNC_INTR(i) = 0
-----------------------------------------------------------------------
SYNC_GEN: if C_ASYNC_INTR(i) = '0' or C_NUM_SYNC_FF = 0 generate
begin
synced_intr <= Intr(i);
end generate SYNC_GEN;
-----------------------------------------------------------------------
-- Generating the edge triggered interrupts if C_KIND_OF_INTR(i) = 1
-----------------------------------------------------------------------
EDGE_DETECT_GEN: if C_KIND_OF_INTR(i) = '1' generate
signal intr_d1 : std_logic;
signal intr_edge : std_logic;
begin
----------------------------------------------------------------
-- Process REG_INTR_EDGE_P to register the interrupt signal edge
----------------------------------------------------------------
REG_INTR_EDGE_P : process (Clk) is
begin
if(Clk'event and Clk='1') then
if Rst_n = RESET_ACTIVE then
intr_d1 <= not C_KIND_OF_EDGE(i);
else
intr_d1 <= synced_intr;
end if;
end if;
end process REG_INTR_EDGE_P;
-- Creating one-shot edge triggered interrupt
intr_edge <= '1' when (synced_intr = C_KIND_OF_EDGE(i)) and
(intr_d1 = not C_KIND_OF_EDGE(i)) else
'0';
-----------------------------------------------------------------
-- Process DETECT_INTR_P to generate the edge triggered interrupt
-----------------------------------------------------------------
DETECT_INTR_P : process (Clk) is
begin
if Clk'event and Clk='1' then
if (Rst_n = RESET_ACTIVE) or (iar(i) = '1') then
hw_intr(i) <= '0';
elsif (intr_edge = '1') then
hw_intr(i) <= '1';
end if;
end if;
end process DETECT_INTR_P;
--------------------------
end generate EDGE_DETECT_GEN;
----------------------------------------------------------------------
-- Generating the Level trigeered interrupts if C_KIND_OF_INTR(i) = 0
----------------------------------------------------------------------
LVL_DETECT_GEN: if C_KIND_OF_INTR(i) = '0' generate
begin
------------------------------------------------------------------
-- Process LVL_P to generate hw_intr (active high or low)
------------------------------------------------------------------
LVL_P : process (Clk) is
begin
if Clk'event and Clk = '1' then
if (Rst_n = RESET_ACTIVE) or (iar(i) = '1') then
hw_intr(i) <= '0';
elsif synced_intr = C_KIND_OF_LVL(i) then
hw_intr(i) <= '1';
end if;
end if;
end process LVL_P;
------------------
end generate LVL_DETECT_GEN;
end generate INTR_DETECT_GEN;
--------------------------------------------------------------------------
-- Checking Active Interrupt/Interrupts
--------------------------------------------------------------------------
IRQ_ONE_INTR_GEN: if (C_NUM_INTR = 1) generate
-----
begin
-----
irq_gen_i<= isr(0) and ier(0) and ilr(0);
end generate IRQ_ONE_INTR_GEN;
IRQ_MULTI_INTR_GEN: if (C_NUM_INTR > 1) generate
-----
begin
-----
--------------------------------------------------------------
-- Process IRQ_GEN_P to generate irq_gen
--------------------------------------------------------------
IRQ_GEN_P: process (isr, ier, ilr) is
variable ilr_value : integer;
variable irq_gen_int : std_logic;
-----
begin
-----
ilr_value := TO_INTEGER(unsigned( ilr(INDEX_BIT - 1 downto 0) ));
irq_gen_int := '0';
for i in 0 to (isr'length - 1) loop
if (C_HAS_ILR = 1) then
exit when (i = ilr_value) and (ilr(INDEX_BIT) = '0');
end if;
irq_gen_int := irq_gen_int or (isr(i) and ier(i));
end loop;
irq_gen_i <= irq_gen_int;
end process IRQ_GEN_P;
----------------------
end generate IRQ_MULTI_INTR_GEN;
--------------------------------
-- Registering irq_gen_i as it will be going through double synchronizer
IRQ_GEN_REG_P : Process(Clk)is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
irq_gen <= '0';
else
irq_gen <= irq_gen_i;
end if;
end if;
end process IRQ_GEN_REG_P;
--------------------------
--------------------------------------------------------------
-- Synchronizing irq_gen
--------------------------------------------------------------
IRQ_GEN_SYNC_GEN: if ((C_DISABLE_SYNCHRONIZERS = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
-----
begin
-----
-- Synchronize irq_gen to Processor clock domain
IRQ_GEN_DOUBLE_SYNC_I: entity axi_intc_v4_1.double_synchronizer
generic map (
C_DWIDTH => 1
)
port map (
CLK_2 => Processor_clk,
RESET_2_n => processor_rst_n,
DATA_IN => scalar_to_vector(irq_gen),
vector_to_scalar(SYNC_DATA_OUT) => irq_gen_sync
);
end generate IRQ_GEN_SYNC_GEN;
IRQ_GEN_SYNC_DISABLE_GEN: if ((C_DISABLE_SYNCHRONIZERS = 1) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
irq_gen_sync <= irq_gen;
end generate IRQ_GEN_SYNC_DISABLE_GEN;
---------------------------------------------------------------
-- Process to synchronize irq_gen and "ivar" to Processor Clock
---------------------------------------------------------------
IVAR_INDEX_SYNC_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
-----
begin
-----
IN_IDLE_SYNC_EN_GEN: if (C_DISABLE_SYNCHRONIZERS = 0) generate
IN_IDLE_DOUBLE_SYNC_I: entity axi_intc_v4_1.double_synchronizer
generic map (
C_DWIDTH => 1
)
port map (
CLK_2 => Clk,
RESET_2_n => Rst_n,
DATA_IN => scalar_to_vector(in_idle),
vector_to_scalar(SYNC_DATA_OUT) => in_idle_axi_clk
);
end generate IN_IDLE_SYNC_EN_GEN;
---------------------------------
IN_IDLE_SYNC_DISABLE_GEN: if (C_DISABLE_SYNCHRONIZERS = 1) generate
in_idle_axi_clk <= in_idle;
end generate IN_IDLE_SYNC_DISABLE_GEN;
--------------------------------------
idle_and_irq <= in_idle_axi_clk and irq_gen_i and mer(0);
------------------------------------
IDLE_IRQ_DELAY_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
idle_and_irq_d1 <= '0';
else
idle_and_irq_d1 <= idle_and_irq;
end if;
end if;
end process IDLE_IRQ_DELAY_P;
------------------------------------
ivar_index_sample_en_i <= idle_and_irq and (not idle_and_irq_d1);
------------------------------------
SAMPLE_REG_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
ivar_index_sample_en <= '0';
else
ivar_index_sample_en <= ivar_index_sample_en_i;
end if;
end if;
end process SAMPLE_REG_P;
------------------------------------
IVAR_INDEX_SYNC_EN_GEN: if (C_DISABLE_SYNCHRONIZERS = 0) generate
IRQ_GEN_EDGE_PULSE_SYNC_I: entity axi_intc_v4_1.pulse_synchronizer
port map (
CLK_1 => Clk,
RESET_1_n => Rst_n,
DATA_IN => ivar_index_sample_en,
CLK_2 => Processor_clk,
RESET_2_n => processor_rst_n,
SYNC_DATA_OUT => ivar_index_sample_en_mb_clk
);
end generate IVAR_INDEX_SYNC_EN_GEN;
------------------------------------
IVAR_INDEX_SYNC_DISABLE_GEN: if (C_DISABLE_SYNCHRONIZERS = 1) generate
ivar_index_sample_en_mb_clk <= ivar_index_sample_en;
end generate IVAR_INDEX_SYNC_DISABLE_GEN;
------------------------------------
IVAR_INDEX_AXI_REG_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
ivar_index_axi_clk <= (others => '0');
else
if (ivar_index_sample_en_i = '1') then
ivar_index_axi_clk <= ivr_data_in;
else
ivar_index_axi_clk <= ivar_index_axi_clk;
end if;
end if;
end if;
end process IVAR_INDEX_AXI_REG_P;
------------------------------------
IVAR_INDEX_MB_REG_P : Process(Processor_clk)
begin
if (Processor_clk'event and Processor_clk = '1') then
if (processor_rst_n = RESET_ACTIVE) then
ivar_index_mb_clk <= (others => '0');
else
if (ivar_index_sample_en_mb_clk = '1') then
ivar_index_mb_clk <= ivar_index_axi_clk;
else
ivar_index_mb_clk <= ivar_index_mb_clk;
end if;
end if;
end if;
end process IVAR_INDEX_MB_REG_P;
------------------------------------
ivar_rd_addr_mb_clk <= std_logic_vector(to_unsigned(TO_INTEGER(unsigned(ivar_index_mb_clk)), 5));
------------------------------------
end generate IVAR_INDEX_SYNC_GEN;
---------------------------------------------------------------------
-- Process to synchronize irq_gen disable to Processor Clock with ILR
---------------------------------------------------------------------
IRQ_DIS_SYNC_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 0) and (C_HAS_ILR = 1)) generate
signal irq_dis : std_logic;
signal irq_dis_d1 : std_logic;
signal irq_dis_sample_i : std_logic;
signal irq_dis_sample : std_logic;
begin
irq_dis <= not irq_gen_i;
IDLE_NOT_IRQ_DELAY_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
irq_dis_d1 <= '0';
else
irq_dis_d1 <= irq_dis;
end if;
end if;
end process IDLE_NOT_IRQ_DELAY_P;
irq_dis_sample_i <= irq_dis and (not irq_dis_d1);
SAMPLE_REG_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
irq_dis_sample <= '0';
else
irq_dis_sample <= irq_dis_sample_i;
end if;
end if;
end process SAMPLE_REG_P;
IRQ_DIS_SYNC_EN_GEN: if (C_DISABLE_SYNCHRONIZERS = 0) generate
IRQ_GEN_EDGE_PULSE_SYNC_I: entity axi_intc_v4_1.pulse_synchronizer
port map (
CLK_1 => Clk,
RESET_1_n => Rst_n,
DATA_IN => irq_dis_sample,
CLK_2 => Processor_clk,
RESET_2_n => processor_rst_n,
SYNC_DATA_OUT => irq_dis_sample_mb_clk
);
end generate IRQ_DIS_SYNC_EN_GEN;
IRQ_DIS_SYNC_DISABLE_GEN: if (C_DISABLE_SYNCHRONIZERS = 1) generate
irq_dis_sample_mb_clk <= irq_dis_sample;
end generate IRQ_DIS_SYNC_DISABLE_GEN;
end generate IRQ_DIS_SYNC_GEN;
---------------------------------------------------------------
-- Process to synchronize irq_gen and "ivar" to Processor Clock
---------------------------------------------------------------
IVAR_INDEX_SYNC_ON_AXI_CLK_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 1)) generate
-----
begin
-----
in_idle_axi_clk <= in_idle;
------------------------------------
idle_and_irq <= in_idle_axi_clk and irq_gen and mer(0);
------------------------------------
IDLE_IRQ_DELAY_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
idle_and_irq_d1 <= '0';
else
idle_and_irq_d1 <= idle_and_irq;
end if;
end if;
end process IDLE_IRQ_DELAY_P;
--------------------------------
ivar_index_sample_en_i <= idle_and_irq and (not idle_and_irq_d1);
--------------------------------
SAMPLE_REG_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
ivar_index_sample_en <= '0';
else
ivar_index_sample_en <= ivar_index_sample_en_i;
end if;
end if;
end process SAMPLE_REG_P;
--------------------------------
ivar_index_sample_en_mb_clk <= ivar_index_sample_en;
--------------------------------
IVAR_INDEX_AXI_REG_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
ivar_index_axi_clk <= (others => '0');
else
if (ivar_index_sample_en_i = '1') then
ivar_index_axi_clk <= ivr;
else
ivar_index_axi_clk <= ivar_index_axi_clk;
end if;
end if;
end if;
end process IVAR_INDEX_AXI_REG_P;
--------------------------------
ivar_index_mb_clk <= ivar_index_axi_clk;
--------------------------------
ivar_rd_addr_mb_clk <= std_logic_vector(to_unsigned(TO_INTEGER(unsigned(ivar_index_mb_clk)), 5));
end generate IVAR_INDEX_SYNC_ON_AXI_CLK_GEN;
---------------------------------------------------------------------
-- Process to synchronize irq_gen disable to Processor Clock with ILR
---------------------------------------------------------------------
IRQ_DIS_SYNC_ON_AXI_CLK_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 1) and (C_HAS_ILR = 1)) generate
signal irq_dis : std_logic;
signal irq_dis_d1 : std_logic;
signal irq_dis_sample_i : std_logic;
signal irq_dis_sample : std_logic;
begin
irq_dis <= not irq_gen;
IDLE_IRQ_DELAY_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
irq_dis_d1 <= '0';
else
irq_dis_d1 <= irq_dis;
end if;
end if;
end process IDLE_IRQ_DELAY_P;
irq_dis_sample_i <= irq_dis and (not irq_dis_d1);
SAMPLE_REG_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
irq_dis_sample <= '0';
else
irq_dis_sample <= irq_dis_sample_i;
end if;
end if;
end process SAMPLE_REG_P;
irq_dis_sample_mb_clk <= irq_dis_sample;
end generate IRQ_DIS_SYNC_ON_AXI_CLK_GEN;
NO_IRQ_DIS_SYNC: if (C_HAS_FAST = 0) or (C_HAS_ILR = 0) generate
begin
irq_dis_sample_mb_clk <= '0';
end generate NO_IRQ_DIS_SYNC;
----------------------------------------------------------------------
-- MER_0_DOUBLE_SYNC_I to synchronize MER(0) with Processor_clk
----------------------------------------------------------------------
MER_SYNC_EN_GEN: if ((C_DISABLE_SYNCHRONIZERS = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
--Synchronize mer(0) to Processor clock domain
MER_0_DOUBLE_SYNC_I: entity axi_intc_v4_1.double_synchronizer
generic map (
C_DWIDTH => 1
)
port map (
CLK_2 => Processor_clk,
RESET_2_n => processor_rst_n,
DATA_IN => scalar_to_vector(mer(0)),
vector_to_scalar(SYNC_DATA_OUT) => mer_0_sync
);
end generate MER_SYNC_EN_GEN;
------------------------------
MER_SYNC_DISABLE_GEN: if ((C_DISABLE_SYNCHRONIZERS = 1) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
mer_0_sync <= mer(0);
end generate MER_SYNC_DISABLE_GEN;
--------------------------------------------------------------------------
-- Generating LEVEL interrupt if C_IRQ_IS_LEVEL = 1
--------------------------------------------------------------------------
IRQ_LEVEL_GEN: if (C_IRQ_IS_LEVEL = 1) generate
-- Level IRQ generation if C_HAS_FAST is 1
IRQ_LEVEL_FAST_ON_MB_CLK_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
-- Type declaration
type STATE_TYPE is (IDLE, GEN_LEVEL_IRQ, WAIT_ACK);
-- Signal declaration
signal current_state : STATE_TYPE;
begin
-- generate in_idle signal
GEN_IN_IDLE_P : process (Processor_clk)
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
in_idle <= '0';
else
if (current_state = IDLE) then
in_idle <= '1';
else
in_idle <= '0';
end if;
end if;
end if;
end process GEN_IN_IDLE_P;
--------------------------------------------------------------
--The sequential process below maintains the current_state
--------------------------------------------------------------
GEN_CS_P : process (Processor_clk)
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
current_state <= IDLE;
else
case current_state is
when IDLE => if ((ivar_index_sample_en_mb_clk = '1')) then
current_state <= GEN_LEVEL_IRQ;
else
current_state <= IDLE;
end if;
when GEN_LEVEL_IRQ =>
if (imr(TO_INTEGER(unsigned(ivar_index_mb_clk))) = '1') then
if (first_ack = '1') then
current_state <= WAIT_ACK;
else
current_state <= GEN_LEVEL_IRQ;
end if;
else
if (ack_or_sync = '1') or (irq_dis_sample_mb_clk = '1') then
current_state <= IDLE;
else
current_state <= GEN_LEVEL_IRQ;
end if;
end if;
when WAIT_ACK => if (second_ack_sync_mb_clk = '1') then
current_state <= IDLE;
else
current_state <= WAIT_ACK;
end if;
-- coverage off
when others => current_state <= IDLE;
-- coverage on
end case;
end if;
end if;
end process GEN_CS_P;
--------------------------------------------------------------------
-- Process IRQ_LEVEL_P for generating LEVEL interrupt
--------------------------------------------------------------------
Irq_i <= C_IRQ_ACTIVE when (current_state = GEN_LEVEL_IRQ) else
not C_IRQ_ACTIVE;
-----------------------------
GEN_LEVEL_IRQ_P : process (Processor_clk)
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
Irq <= (not C_IRQ_ACTIVE);
else
Irq <= Irq_i;
end if;
end if;
end process GEN_LEVEL_IRQ_P;
-----------------------------
NO_CASCADE_IVAR_ADDRESS: -- if (C_CASCADE_MASTER = 0) generate
if (C_EN_CASCADE_MODE = 0) and (C_CASCADE_MASTER = 0) generate
begin
-----
Interrupt_address <= ivar_rd_data_mb_clk;
end generate NO_CASCADE_IVAR_ADDRESS;
-------------------------------------
CASCADE_IVAR_ADDRESS: if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 0) generate
signal Interrupt_address_in_reg : std_logic_vector(31 downto 0);
-----
begin
-----
REG_IP_INTR_ADDR_IN: process(Processor_clk)is
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
Interrupt_address_in_reg <= (others => '0');
else
Interrupt_address_in_reg <= Interrupt_address_in;
end if;
end if;
end process REG_IP_INTR_ADDR_IN;
--------------------------------
Interrupt_address_in_reg_int <= Interrupt_address_in_reg;
--------------------------------
Interrupt_address <= Interrupt_address_in_reg when ((isr(31) = '1') and
(ier(31) = '1') and
(isr_ored_30_0_bits = '0')
)
else
ivar_rd_data_mb_clk;
end generate CASCADE_IVAR_ADDRESS;
----------------------------------
CASCADE_IVAR_ADDRESS_MST_MD: if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 1) generate
-- local signal declaration
signal Interrupt_address_in_reg : std_logic_vector(31 downto 0);
-----
begin
-----
REG_IP_INTR_ADDR_IN: process(Processor_clk)is
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
Interrupt_address_in_reg <= (others => '0');
else
Interrupt_address_in_reg <= Interrupt_address_in;
end if;
end if;
end process REG_IP_INTR_ADDR_IN;
--------------------------------
Interrupt_address_in_reg_int <= Interrupt_address_in_reg;
--------------------------------
Interrupt_address <= Interrupt_address_in_reg when ((isr(31) = '1') and
(ier(31) = '1') and
(isr_ored_30_0_bits = '0')
)
else
ivar_rd_data_mb_clk;
end generate CASCADE_IVAR_ADDRESS_MST_MD;
end generate IRQ_LEVEL_FAST_ON_MB_CLK_GEN;
------------------------------------------------------------------
IRQ_LEVEL_FAST_ON_AXI_CLK_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 1)) generate
-- Type declaration
type STATE_TYPE is (IDLE, GEN_LEVEL_IRQ, WAIT_ACK);
-- Signal declaration
signal current_state : STATE_TYPE;
begin
-- generate in_idle signal
GEN_IN_IDLE_P : process (Clk)
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
in_idle <= '0';
else
if (current_state = IDLE) then
in_idle <= '1';
else
in_idle <= '0';
end if;
end if;
end if;
end process GEN_IN_IDLE_P;
--------------------------------------------------------------
--The sequential process below maintains the current_state
--------------------------------------------------------------
GEN_CS_P : process (Clk)
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
current_state <= IDLE;
else
case current_state is
when IDLE => if (ivar_index_sample_en_mb_clk = '1') then
current_state <= GEN_LEVEL_IRQ;
else
current_state <= IDLE;
end if;
when GEN_LEVEL_IRQ =>
if (imr(TO_INTEGER(unsigned(ivar_index_mb_clk))) = '1') then
if (first_ack = '1') then
current_state <= WAIT_ACK;
else
current_state <= GEN_LEVEL_IRQ;
end if;
else
if (ack_or_sync = '1') or (irq_dis_sample_mb_clk = '1') then
current_state <= IDLE;
else
current_state <= GEN_LEVEL_IRQ;
end if;
end if;
when WAIT_ACK => if (second_ack_sync_mb_clk = '1') then
current_state <= IDLE;
else
current_state <= WAIT_ACK;
end if;
-- coverage off
when others => current_state <= IDLE;
-- coverage on
end case;
end if;
end if;
end process GEN_CS_P;
--------------------------------------------------------------------
-- Process IRQ_LEVEL_P for generating LEVEL interrupt
--------------------------------------------------------------------
Irq_i <= C_IRQ_ACTIVE when (current_state = GEN_LEVEL_IRQ) else
not C_IRQ_ACTIVE;
-------------------------------
GEN_LEVEL_IRQ_P : process (Clk)
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
Irq <= (not C_IRQ_ACTIVE);
else
Irq <= Irq_i;
end if;
end if;
end process GEN_LEVEL_IRQ_P;
----------------------------
-- Interrupt_address <= ivar_rd_data_mb_clk;
NO_CASCADE_IVAR_ADDRESS: -- if (C_CASCADE_MASTER = 0) generate
if (C_EN_CASCADE_MODE = 0) and (C_CASCADE_MASTER = 0) generate
begin
-----
Interrupt_address <= ivar_rd_data_mb_clk;
end generate NO_CASCADE_IVAR_ADDRESS;
CASCADE_IVAR_ADDRESS: if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 0) generate
signal Interrupt_address_in_reg : std_logic_vector(31 downto 0);
-----
begin
-----
REG_IP_INTR_ADDR_IN: process(Clk)is
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
Interrupt_address_in_reg <= (others => '0');
else
Interrupt_address_in_reg <= Interrupt_address_in;
end if;
end if;
end process REG_IP_INTR_ADDR_IN;
--------------------------------
Interrupt_address_in_reg_int <= Interrupt_address_in_reg;
--------------------------------
Interrupt_address <= Interrupt_address_in_reg when ((isr(31) = '1') and
(ier(31) = '1') and
(isr_ored_30_0_bits = '0')
)
else
ivar_rd_data_mb_clk;
end generate CASCADE_IVAR_ADDRESS;
----------------------------------
CASCADE_IVAR_ADDRESS_MST_MD: if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 1) generate
signal Interrupt_address_in_reg : std_logic_vector(31 downto 0);
-----
begin
-----
REG_IP_INTR_ADDR_IN: process(Clk)is
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
Interrupt_address_in_reg <= (others => '0');
else
Interrupt_address_in_reg <= Interrupt_address_in;
end if;
end if;
end process REG_IP_INTR_ADDR_IN;
--------------------------------
Interrupt_address_in_reg_int <= Interrupt_address_in_reg;
--------------------------------
Interrupt_address <= Interrupt_address_in_reg when ((isr(31) = '1') and
(ier(31) = '1') and
(isr_ored_30_0_bits = '0')
)
else
ivar_rd_data_mb_clk;
end generate CASCADE_IVAR_ADDRESS_MST_MD;
-------------------------------------------
end generate IRQ_LEVEL_FAST_ON_AXI_CLK_GEN;
-- Level IRQ generation if C_HAS_FAST is 0
IRQ_LEVEL_NORMAL_ON_MB_CLK_GEN: if ((C_HAS_FAST = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
--------------------------------------------------------------------
-- Process IRQ_LEVEL_P for generating LEVEL interrupt
--------------------------------------------------------------------
IRQ_LEVEL_P: process (Processor_clk) is
begin
if(Processor_clk'event and Processor_clk = '1') then
if ((processor_rst_n = RESET_ACTIVE) or (irq_gen_sync = '0')) then
Irq <= not C_IRQ_ACTIVE;
elsif ((irq_gen_sync = '1') and (mer_0_sync = '1')) then
Irq <= C_IRQ_ACTIVE;
end if;
end if;
end process IRQ_LEVEL_P;
-------------------------------------
Interrupt_address <= (others => '0');
-------------------------------------
end generate IRQ_LEVEL_NORMAL_ON_MB_CLK_GEN;
IRQ_LEVEL_NORMAL_ON_AXI_CLK_GEN: if ((C_HAS_FAST = 0) and (C_MB_CLK_NOT_CONNECTED = 1)) generate
--------------------------------------------------------------------
-- Process IRQ_LEVEL_P for generating LEVEL interrupt
--------------------------------------------------------------------
IRQ_LEVEL_ON_AXI_P: process (Clk) is
begin
if(Clk'event and Clk = '1') then
if ((Rst_n = RESET_ACTIVE) or (irq_gen_sync = '0')) then
Irq <= not C_IRQ_ACTIVE;
elsif ((irq_gen_sync = '1') and (mer_0_sync = '1')) then
Irq <= C_IRQ_ACTIVE;
end if;
end if;
end process IRQ_LEVEL_ON_AXI_P;
Interrupt_address <= (others => '0');
end generate IRQ_LEVEL_NORMAL_ON_AXI_CLK_GEN;
end generate IRQ_LEVEL_GEN;
----------------------------------------------------------------------
-- Generating ack_or for C_NUM_INTR = 1
----------------------------------------------------------------------
ACK_OR_ONE_INTR_GEN: if (C_NUM_INTR = 1) generate
ack_or_i <= iar(0);
end generate ACK_OR_ONE_INTR_GEN;
----------------------------------------------------------------------
-- Generating ack_or for C_NUM_INTR > 1
----------------------------------------------------------------------
ACK_OR_MULTI_INTR_GEN: if (C_NUM_INTR > 1) generate
-----
begin
-----
--------------------------------------------------------------
-- Process ACK_OR_GEN_P to generate ack_or (ORed Acks)
--------------------------------------------------------------
ACK_OR_GEN_P: process (iar)
variable ack_or_int : std_logic := '0';
begin
ack_or_int := iar(0);
for i in 1 to (iar'length - 1) loop
ack_or_int := ack_or_int or (iar(i));
end loop;
ack_or_i <= ack_or_int;
end process ACK_OR_GEN_P;
end generate ACK_OR_MULTI_INTR_GEN;
----------------------------------
ACK_OR_REG_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
ack_or <= '0';
else
ack_or <= ack_or_i;
end if;
end if;
end process ACK_OR_REG_P;
-------------------------
ACK_OR_SYNC_EN_GEN: if ((C_DISABLE_SYNCHRONIZERS = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
ACK_OR_PULSE_SYNC_I: entity axi_intc_v4_1.pulse_synchronizer
port map (
CLK_1 => Clk,
RESET_1_n => Rst_n,
DATA_IN => ack_or,
CLK_2 => Processor_clk,
RESET_2_n => processor_rst_n,
SYNC_DATA_OUT => ack_or_sync
);
end generate ACK_OR_SYNC_EN_GEN;
ACK_OR_SYNC_DISABLE_GEN: if ((C_DISABLE_SYNCHRONIZERS = 1) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
ack_or_sync <= ack_or;
end generate ACK_OR_SYNC_DISABLE_GEN;
--------------------------------------------------------------------------
-- Generating EDGE interrupt if C_IRQ_IS_LEVEL = 0
--------------------------------------------------------------------------
IRQ_EDGE_GEN: if (C_IRQ_IS_LEVEL = 0) generate
IRQ_EDGE_FAST_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
-- Type declaration
type STATE_TYPE is (IDLE, GEN_PULSE, WAIT_ACK);
-- Signal declaration
signal current_state : STATE_TYPE;
begin
-- generate in_idle signal
GEN_IN_IDLE_P : process (Processor_clk)
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
in_idle <= '0';
else
if (current_state = IDLE) then
in_idle <= '1';
else
in_idle <= '0';
end if;
end if;
end if;
end process GEN_IN_IDLE_P;
--------------------------------------------------------------
--The sequential process below maintains the current_state
--------------------------------------------------------------
GEN_CS_P : process (Processor_clk)
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
current_state <= IDLE;
else
case current_state is
when IDLE => if (ivar_index_sample_en_mb_clk = '1') then
current_state <= GEN_PULSE;
else
current_state <= IDLE;
end if;
when GEN_PULSE =>
if (imr(TO_INTEGER(unsigned(ivar_index_mb_clk))) = '1') then
if (first_ack = '1') then
current_state <= WAIT_ACK;
else
current_state <= GEN_PULSE;
end if;
else
if (ack_or_sync = '1') or (irq_dis_sample_mb_clk = '1') then
current_state <= IDLE;
else
current_state <= GEN_PULSE;
end if;
end if;
when WAIT_ACK => if (second_ack_sync_mb_clk = '1') then
current_state <= IDLE;
else
current_state <= WAIT_ACK;
end if;
-- coverage off
when others => current_state <= IDLE;
-- coverage on
end case;
end if;
end if;
end process GEN_CS_P;
Irq_i <= C_IRQ_ACTIVE when (current_state = GEN_PULSE) else
(not C_IRQ_ACTIVE);
GEN_IRQ_P : process (Processor_clk)
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
Irq <= (not C_IRQ_ACTIVE);
else
Irq <= Irq_i;
end if;
end if;
end process GEN_IRQ_P;
-- Interrupt_address <= ivar_rd_data_mb_clk; -- 09-09-2012
NO_CASCADE_IVAR_ADDRESS: -- if (C_CASCADE_MASTER = 0) generate
if (C_EN_CASCADE_MODE = 0) and (C_CASCADE_MASTER = 0) generate
begin
-----
Interrupt_address <= ivar_rd_data_mb_clk;
end generate NO_CASCADE_IVAR_ADDRESS;
CASCADE_IVAR_ADDRESS: if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 0) generate
signal Interrupt_address_in_reg : std_logic_vector(31 downto 0);
-----
begin
-----
REG_IP_INTR_ADDR_IN: process(Processor_clk)is
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
Interrupt_address_in_reg <= (others => '0');
else
Interrupt_address_in_reg <= Interrupt_address_in;
end if;
end if;
end process REG_IP_INTR_ADDR_IN;
--------------------------------
Interrupt_address_in_reg_int <= Interrupt_address_in_reg;
--------------------------------
Interrupt_address <= Interrupt_address_in_reg when ((isr(31) = '1') and
(ier(31) = '1') and
(isr_ored_30_0_bits = '0')
)
else
ivar_rd_data_mb_clk;
end generate CASCADE_IVAR_ADDRESS;
---------------------------------------------------
CASCADE_IVAR_ADDRESS_MST_MD: if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 1) generate
signal Interrupt_address_in_reg : std_logic_vector(31 downto 0);
-----
begin
-----
REG_IP_INTR_ADDR_IN: process(Processor_clk)is
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
Interrupt_address_in_reg <= (others => '0');
else
Interrupt_address_in_reg <= Interrupt_address_in;
end if;
end if;
end process REG_IP_INTR_ADDR_IN;
--------------------------------
Interrupt_address_in_reg_int <= Interrupt_address_in_reg;
--------------------------------
Interrupt_address <= Interrupt_address_in_reg when ((isr(31) = '1') and
(ier(31) = '1') and
(isr_ored_30_0_bits = '0')
)
else
ivar_rd_data_mb_clk;
end generate CASCADE_IVAR_ADDRESS_MST_MD;
---------------------------------------------------
end generate IRQ_EDGE_FAST_GEN;
IRQ_EDGE_FAST_ON_AXI_CLK_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 1)) generate
-- Type declaration
type STATE_TYPE is (IDLE, GEN_PULSE, WAIT_ACK);
-- Signal declaration
signal current_state : STATE_TYPE;
begin
-- generate in_idle signal
GEN_IN_IDLE_P : process (Clk)
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
in_idle <= '0';
else
if (current_state = IDLE) then
in_idle <= '1';
else
in_idle <= '0';
end if;
end if;
end if;
end process GEN_IN_IDLE_P;
--------------------------------------------------------------
--The sequential process below maintains the current_state
--------------------------------------------------------------
GEN_CS_P : process (Clk)
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
current_state <= IDLE;
else
case current_state is
when IDLE => if (ivar_index_sample_en_mb_clk = '1') then
current_state <= GEN_PULSE;
else
current_state <= IDLE;
end if;
when GEN_PULSE =>
if (imr(TO_INTEGER(unsigned(ivar_index_mb_clk))) = '1') then
if (first_ack = '1') then
current_state <= WAIT_ACK;
else
current_state <= GEN_PULSE;
end if;
else
if (ack_or_sync = '1') or (irq_dis_sample_mb_clk = '1') then
current_state <= IDLE;
else
current_state <= GEN_PULSE;
end if;
end if;
when WAIT_ACK => if (second_ack_sync_mb_clk = '1') then
current_state <= IDLE;
else
current_state <= WAIT_ACK;
end if;
-- coverage off
when others => current_state <= IDLE;
-- coverage on
end case;
end if;
end if;
end process GEN_CS_P;
---------------------------
Irq_i <= C_IRQ_ACTIVE when (current_state = GEN_PULSE) else
(not C_IRQ_ACTIVE);
---------------------------
GEN_IRQ_P : process (Clk)
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
Irq <= (not C_IRQ_ACTIVE);
else
Irq <= Irq_i;
end if;
end if;
end process GEN_IRQ_P;
-----------------------
-- Interrupt_address <= ivar_rd_data_mb_clk; -- 09-09-2012
NO_CASCADE_IVAR_ADDRESS: -- if (C_CASCADE_MASTER = 0) generate
if (C_EN_CASCADE_MODE = 0) and (C_CASCADE_MASTER = 0) generate
begin
-----
Interrupt_address <= ivar_rd_data_mb_clk;
end generate NO_CASCADE_IVAR_ADDRESS;
-------------------------------------
CASCADE_IVAR_ADDRESS: if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 0) generate
signal Interrupt_address_in_reg : std_logic_vector(31 downto 0);
-----
begin
-----
REG_IP_INTR_ADDR_IN: process(Clk)is
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
Interrupt_address_in_reg <= (others => '0');
else
Interrupt_address_in_reg <= Interrupt_address_in;
end if;
end if;
end process REG_IP_INTR_ADDR_IN;
--------------------------------
Interrupt_address_in_reg_int <= Interrupt_address_in_reg;
--------------------------------
Interrupt_address <= Interrupt_address_in_reg when ((isr(31) = '1') and
(ier(31) = '1') and
(isr_ored_30_0_bits = '0')
)
else
ivar_rd_data_mb_clk;
end generate CASCADE_IVAR_ADDRESS;
---------------------------------------------------------------
CASCADE_IVAR_ADDRESS_MST_MD: if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 1) generate
signal Interrupt_address_in_reg : std_logic_vector(31 downto 0);
-----
begin
-----
REG_IP_INTR_ADDR_IN: process(Clk)is
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
Interrupt_address_in_reg <= (others => '0');
else
Interrupt_address_in_reg <= Interrupt_address_in;
end if;
end if;
end process REG_IP_INTR_ADDR_IN;
--------------------------------
Interrupt_address_in_reg_int <= Interrupt_address_in_reg;
--------------------------------
Interrupt_address <= Interrupt_address_in_reg when ((isr(31) = '1') and
(ier(31) = '1') and
(isr_ored_30_0_bits = '0')
)
else
ivar_rd_data_mb_clk;
end generate CASCADE_IVAR_ADDRESS_MST_MD;
---------------------------------------------------------------
end generate IRQ_EDGE_FAST_ON_AXI_CLK_GEN;
--IRQ_EDGE_NORMAL_GEN: if (C_HAS_FAST = 0) generate
IRQ_EDGE_NO_MB_CLK_GEN: if ((C_HAS_FAST = 0) and (C_MB_CLK_NOT_CONNECTED = 1)) generate
-- Type declaration
type STATE_TYPE is (IDLE, GEN_PULSE, WAIT_ACK);
-- Signal declaration
signal current_state : STATE_TYPE;
begin
--------------------------------------------------------------
--The sequential process below maintains the current_state
--------------------------------------------------------------
GEN_CS_P : process (Clk)
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
current_state <= IDLE;
else
case current_state is
when IDLE => if ((irq_gen_sync = '1') and (mer_0_sync = '1')) then
current_state <= GEN_PULSE;
else
current_state <= IDLE;
end if;
when GEN_PULSE =>
current_state <= WAIT_ACK;
when WAIT_ACK => if (ack_or_sync = '1') then
current_state <= IDLE;
else
current_state <= WAIT_ACK;
end if;
end case;
end if;
end if;
end process GEN_CS_P;
GEN_IRQ_AND_ADDR_P : process (Clk)
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
Irq <= (not C_IRQ_ACTIVE);
else
if (current_state = GEN_PULSE) then
Irq <= C_IRQ_ACTIVE;
else
Irq <= not C_IRQ_ACTIVE;
end if;
end if;
end if;
end process GEN_IRQ_AND_ADDR_P;
Interrupt_address <= (others => '0');
end generate IRQ_EDGE_NO_MB_CLK_GEN;
IRQ_EDGE_MB_CLK_GEN: if ((C_HAS_FAST = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
-- Type declaration
type STATE_TYPE is (IDLE, GEN_PULSE, WAIT_ACK, WAIT_SYNC);
-- Signal declaration
signal current_state : STATE_TYPE;
begin
--------------------------------------------------------------
--The sequential process below maintains the current_state
--------------------------------------------------------------
GEN_CS_P : process (Processor_clk)
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
current_state <= IDLE;
else
case current_state is
when IDLE => if ((irq_gen_sync = '1') and (mer_0_sync = '1')) then
current_state <= GEN_PULSE;
else
current_state <= IDLE;
end if;
when GEN_PULSE =>
current_state <= WAIT_ACK;
when WAIT_ACK => if (ack_or_sync = '1') then
if (C_DISABLE_SYNCHRONIZERS = 1) then
current_state <= IDLE;
else
current_state <= WAIT_SYNC;
end if;
else
current_state <= WAIT_ACK;
end if;
when WAIT_SYNC => current_state <= IDLE;
-- coverage off
when others => current_state <= IDLE;
-- coverage on
end case;
end if;
end if;
end process GEN_CS_P;
GEN_IRQ_AND_ADDR_P : process (Processor_clk)
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
Irq <= (not C_IRQ_ACTIVE);
else
if (current_state = GEN_PULSE) then
Irq <= C_IRQ_ACTIVE;
else
Irq <= not C_IRQ_ACTIVE;
end if;
end if;
end if;
end process GEN_IRQ_AND_ADDR_P;
Interrupt_address <= (others => '0');
end generate IRQ_EDGE_MB_CLK_GEN;
--end generate IRQ_EDGE_NORMAL_GEN;
end generate IRQ_EDGE_GEN;
--Read data in Normal mode (C_HAS_FAST = 0)
OUTPUT_DATA_NORMAL_GEN: if (C_HAS_FAST = 0) generate
-----
begin
-----
------------------------------------------------------------------------
-- Process OUTPUT_DATA_GEN_P for generating Rd_data
------------------------------------------------------------------------
OUTPUT_DATA_GEN_P: process (read, Reg_addr, isr_out, ipr, ier_out,
ilr_out, ivr_out, mer) is
-----
begin
-----
if (read = '1') then
case Reg_addr(6 downto 0) is
when "0000000" => Rd_data <= isr_out; -- ISR (R/W)
when "0000001" => Rd_data <= ipr; -- IPR (Read only)
when "0000010" => Rd_data <= ier_out; -- IER (R/W)
when "0000110" => Rd_data <= ivr_out; -- IVR (Read only)
when "0000111" => Rd_data <= mer; -- MER (R/W)
when "0001001" => Rd_data <= ilr_out; -- ILR (R(W)
-- IAR, SIE, CIE (Write only)
-- coverage off
when others => Rd_data <= (others => '0');
-- coverage on
end case;
else
Rd_data <= (others => '0');
end if;
end process OUTPUT_DATA_GEN_P;
end generate OUTPUT_DATA_NORMAL_GEN;
--Read data in mixed mode (C_HAS_FAST = 1) and C_EN_CASCADE_MODE = 1 and C_CASCADE_MASTER = 1
CASCADE_OP_DATA_FAST_GEN: if ((C_HAS_FAST = 1) and
(C_EN_CASCADE_MODE = 1)
) generate
-----
begin
-----
------------------------------------------------------------------------
-- Process OUTPUT_DATA_GEN_P for generating Rd_data
------------------------------------------------------------------------
OUTPUT_DATA_GEN_P: process (read ,
read_ivar ,
Reg_addr ,
isr_out ,
ipr ,
ier_out ,
ilr_out ,
ivr_out ,
mer ,
imr_out ,
ivar_rd_data_axi_clk,
Interrupt_address_in_reg_int,
ier ,
isr ,
isr_ored_30_0_bits) is
begin
-----
if (read = '1') then
case Reg_addr(6 downto 0) is
when "0000000" => Rd_data <= isr_out; -- ISR (R/W)
when "0000001" => Rd_data <= ipr; -- IPR (Read only)
when "0000010" => Rd_data <= ier_out; -- IER (R/W)
when "0000110" => Rd_data <= ivr_out; -- IVR (Read only)
when "0000111" => Rd_data <= mer; -- MER (R/W)
when "0001000" => Rd_data <= imr_out; -- IMR (R/W)
when "0001001" => Rd_data <= ilr_out; -- ILR (R(W)
-- IAR, SIE, CIE (Write only)
-- coverage off
when others => Rd_data <= (others => '0');
-- coverage on
end case;
elsif (read_ivar = '1') then -- read IVAR of 31st bit in case the interrupt is present
if((isr(31) = '1') and -- else to read IVAR of lower modules the processor has to
(ier(31) = '1') and -- initiate the transaction for lower module separately
(isr_ored_30_0_bits = '0')
)then
Rd_data <= Interrupt_address_in_reg_int;
else
Rd_data <= ivar_rd_data_axi_clk;
end if;
else
Rd_data <= (others => '0');
end if;
end process OUTPUT_DATA_GEN_P;
end generate CASCADE_OP_DATA_FAST_GEN;
--------------------------------------------------------------------------
NO_CASCADE_OP_DATA_FAST_GEN: if (C_HAS_FAST = 1) and
(C_CASCADE_MASTER = 0) and
(C_EN_CASCADE_MODE = 0)
generate
-----
begin
-----
------------------------------------------------------------------------
-- Process OUTPUT_DATA_GEN_P for generating Rd_data
------------------------------------------------------------------------
OUTPUT_DATA_GEN_P: process (read ,
read_ivar ,
Reg_addr ,
isr_out ,
ipr ,
ier_out ,
ilr_out ,
ivr_out ,
mer ,
imr_out ,
ivar_rd_data_axi_clk) is
begin
if (read = '1') then
case Reg_addr(6 downto 0) is
when "0000000" => Rd_data <= isr_out; -- ISR (R/W)
when "0000001" => Rd_data <= ipr; -- IPR (Read only)
when "0000010" => Rd_data <= ier_out; -- IER (R/W)
when "0000110" => Rd_data <= ivr_out; -- IVR (Read only)
when "0000111" => Rd_data <= mer; -- MER (R/W)
when "0001000" => Rd_data <= imr_out; -- IMR (R/W)
when "0001001" => Rd_data <= ilr_out; -- ILR (R(W)
-- IAR, SIE, CIE (Write only)
-- coverage off
when others => Rd_data <= (others => '0');
-- coverage on
end case;
elsif (read_ivar = '1') then
Rd_data <= ivar_rd_data_axi_clk;
else
Rd_data <= (others => '0');
end if;
end process OUTPUT_DATA_GEN_P;
end generate NO_CASCADE_OP_DATA_FAST_GEN;
--------------------------------------------------------------------------
end imp;
| apache-2.0 | 1d4b0193e931f475b27b1836b22eb07a | 0.359179 | 4.99761 | false | false | false | false |
sils1297/HWPrak14 | task_4/project_1.srcs/sources_1/new/Register.vhd | 1 | 607 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity SimpleRegister is
generic(
WIDTH : integer := 16
);
Port(
inval : in std_ulogic_vector(WIDTH - 1 downto 0);
outval : out std_ulogic_vector(WIDTH - 1 downto 0);
set : in std_ulogic;
reset : in std_ulogic;
clock : in std_ulogic
);
end SimpleRegister;
architecture Behavioral of SimpleRegister is
begin
process(clock, set)
begin
if reset = '1' then
outval <= (others => '0');
else
if set = '1' and rising_edge(clock) then
outval <= inval;
end if;
end if;
end process;
end Behavioral;
| agpl-3.0 | 0f659d4f2f91c363adf56b55fcad7132 | 0.660626 | 2.836449 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-30bits_outputs31bits/1-HAL/metaheurísticas/hal_wsga.vhd | 1 | 1,748 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.09:06:03)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY hal_wsga_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5: IN unsigned(0 TO 30);
output1, output2, output3: OUT unsigned(0 TO 31));
END hal_wsga_entity;
ARCHITECTURE hal_wsga_description OF hal_wsga_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register4: unsigned(0 TO 31) := "0000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
register2 := input2 * 2;
WHEN "00000010" =>
register1 := register1 * register2;
register2 := input3 * 3;
register3 := input4 + 4;
WHEN "00000011" =>
register2 := register2 * 6;
register1 := register1 - 8;
register4 := input5 * 9;
IF (register3 < 10) THEN
output1 <= register3;
ELSE
output1 <= "0000000000000000000000000001010";
END IF;
WHEN "00000100" =>
output2 <= register4 + 11;
output3 <= register1 - register2;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END hal_wsga_description; | gpl-3.0 | 74c65b75629d80ed2f58241342760738 | 0.687071 | 3.243043 | false | false | false | false |
BBN-Q/APS2-Comms | src/tcp_bridge.vhd | 1 | 6,751 | -- Top-level entity for the bridge to the TCP stream
-- Contains:
-- 1. tcp_demux to send data to either memory or CPLD
-- 2. tcp_axi_dma to issue read/write DMA commands to memory
-- 3. tcp_mux to combine return streams
--
-- Original author: Colm Ryan
-- Copyright 2015, Raytheon BBN Technologies
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tcp_bridge is
port (
clk : in std_logic;
rst : in std_logic;
clk_tcp : in std_logic;
rst_tcp : in std_logic;
--TCP streams
tcp_rx_tdata : in std_logic_vector(7 downto 0);
tcp_rx_tvalid : in std_logic;
tcp_rx_tready : out std_logic;
tcp_tx_tdata : out std_logic_vector(7 downto 0);
tcp_tx_tvalid : out std_logic;
tcp_tx_tready : in std_logic;
comms_active : out std_logic;
--CPLD streams
cpld_rx_tdata : out std_logic_vector(31 downto 0);
cpld_rx_tvalid : out std_logic;
cpld_rx_tready : in std_logic := '1';
cpld_rx_tlast : out std_logic;
cpld_tx_tdata : in std_logic_vector(31 downto 0) := (others => '0');
cpld_tx_tvalid : in std_logic := '0';
cpld_tx_tready : out std_logic;
cpld_tx_tlast : in std_logic := '0';
--AXI DataMover streams
MM2S_CMD_tdata : out std_logic_vector( 71 downto 0 );
MM2S_CMD_tready : in std_logic;
MM2S_CMD_tvalid : out std_logic;
MM2S_tdata : in std_logic_vector( 31 downto 0 );
MM2S_tkeep : in std_logic_vector( 3 downto 0 );
MM2S_tlast : in std_logic;
MM2S_tready : out std_logic;
MM2S_tvalid : in std_logic;
MM2S_STS_tdata : in std_logic_vector( 7 downto 0 );
MM2S_STS_tkeep : in std_logic_vector( 0 to 0 );
MM2S_STS_tlast : in std_logic;
MM2S_STS_tready : out std_logic;
MM2S_STS_tvalid : in std_logic;
S2MM_CMD_tdata : out std_logic_vector( 71 downto 0 );
S2MM_CMD_tready : in std_logic;
S2MM_CMD_tvalid : out std_logic;
S2MM_tdata : out std_logic_vector( 31 downto 0 );
S2MM_tkeep : out std_logic_vector( 3 downto 0 );
S2MM_tlast : out std_logic;
S2MM_tready : in std_logic;
S2MM_tvalid : out std_logic;
S2MM_STS_tdata : in std_logic_vector( 7 downto 0 );
S2MM_STS_tkeep : in std_logic_vector( 0 to 0 );
S2MM_STS_tlast : in std_logic;
S2MM_STS_tready : out std_logic;
S2MM_STS_tvalid : in std_logic
);
end entity;
architecture arch of tcp_bridge is
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of clk_tcp : signal is "xilinx.com:signal:clock:1.0 clk_tcp CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of clk_tcp : signal is
"ASSOCIATED_BUSIF tcp_rx:tcp_tx, ASSOCIATED_RESET rst_tcp, FREQ_HZ 125000000";
attribute X_INTERFACE_INFO of rst_tcp : signal is "xilinx.com:signal:reset:1.0 rst_tcp RST";
attribute X_INTERFACE_PARAMETER of rst_tcp : signal is "POLARITY ACTIVE_HIGH";
signal memory_rx_tdata : std_logic_vector(31 downto 0) := (others => '0');
signal memory_rx_tvalid, memory_rx_tready, memory_rx_tlast : std_logic := '0';
signal memory_tx_write_resp_tdata : std_logic_vector(31 downto 0);
signal memory_tx_write_resp_tvalid, memory_tx_write_resp_tready, memory_tx_write_resp_tlast : std_logic;
signal memory_tx_read_resp_tdata : std_logic_vector(31 downto 0);
signal memory_tx_read_resp_tvalid, memory_tx_read_resp_tready, memory_tx_read_resp_tlast : std_logic;
signal tcp_tx_tvalid_int : std_logic;
begin
tcp_tx_tvalid <= tcp_tx_tvalid_int;
--Clock out valids as indicators of comms_active
comms_active_reg : process( clk_tcp )
begin
if rising_edge( clk_tcp) then
if rst_tcp = '1' then
comms_active <= '0';
else
comms_active <= tcp_rx_tvalid or tcp_tx_tvalid_int;
end if;
end if;
end process;
--TCP Demux
tcp_demux_inst : entity work.tcp_demux
port map (
clk => clk,
rst => rst,
clk_tcp => clk_tcp,
rst_tcp => rst_tcp,
--TCP stream receive
tcp_rx_tdata => tcp_rx_tdata,
tcp_rx_tvalid => tcp_rx_tvalid,
tcp_rx_tready => tcp_rx_tready,
--rx stream passed to memory
memory_rx_tdata => memory_rx_tdata,
memory_rx_tvalid => memory_rx_tvalid,
memory_rx_tready => memory_rx_tready,
memory_rx_tlast => memory_rx_tlast,
--rx stream passed to CPLD bridge
cpld_rx_tdata => cpld_rx_tdata,
cpld_rx_tvalid => cpld_rx_tvalid,
cpld_rx_tready => cpld_rx_tready,
cpld_rx_tlast => cpld_rx_tlast
);
--TCP DMA
tcp_axi_dma_inst : entity work.tcp_axi_dma
port map (
clk => clk,
rst => rst,
---TCP receive
rx_tdata => memory_rx_tdata,
rx_tvalid => memory_rx_tvalid,
rx_tready => memory_rx_tready,
rx_tlast => memory_rx_tlast,
--TCP send channels
tx_write_resp_tdata => memory_tx_write_resp_tdata,
tx_write_resp_tvalid => memory_tx_write_resp_tvalid,
tx_write_resp_tlast => memory_tx_write_resp_tlast,
tx_write_resp_tready => memory_tx_write_resp_tready,
tx_read_resp_tdata => memory_tx_read_resp_tdata,
tx_read_resp_tvalid => memory_tx_read_resp_tvalid,
tx_read_resp_tlast => memory_tx_read_resp_tlast,
tx_read_resp_tready => memory_tx_read_resp_tready,
--DataMover interfaces
MM2S_CMD_tdata => MM2S_CMD_tdata,
MM2S_CMD_tready => MM2S_CMD_tready,
MM2S_CMD_tvalid => MM2S_CMD_tvalid,
MM2S_tdata => MM2S_tdata,
MM2S_tkeep => MM2S_tkeep,
MM2S_tlast => MM2S_tlast,
MM2S_tready => MM2S_tready,
MM2S_tvalid => MM2S_tvalid,
MM2S_STS_tdata => MM2S_STS_tdata,
MM2S_STS_tkeep => MM2S_STS_tkeep,
MM2S_STS_tlast => MM2S_STS_tlast,
MM2S_STS_tready => MM2S_STS_tready,
MM2S_STS_tvalid => MM2S_STS_tvalid,
S2MM_CMD_tdata => S2MM_CMD_tdata,
S2MM_CMD_tready => S2MM_CMD_tready,
S2MM_CMD_tvalid => S2MM_CMD_tvalid,
S2MM_tdata => S2MM_tdata,
S2MM_tkeep => S2MM_tkeep,
S2MM_tlast => S2MM_tlast,
S2MM_tready => S2MM_tready,
S2MM_tvalid => S2MM_tvalid,
S2MM_STS_tdata => S2MM_STS_tdata,
S2MM_STS_tkeep => S2MM_STS_tkeep,
S2MM_STS_tlast => S2MM_STS_tlast,
S2MM_STS_tready => S2MM_STS_tready,
S2MM_STS_tvalid => S2MM_STS_tvalid
);
tcp_mux_inst : entity work.tcp_mux
port map (
clk => clk,
rst => rst,
clk_tcp => clk_tcp,
rst_tcp => rst_tcp,
--memory write/read streams
memory_tx_write_resp_tdata => memory_tx_write_resp_tdata,
memory_tx_write_resp_tvalid => memory_tx_write_resp_tvalid,
memory_tx_write_resp_tlast => memory_tx_write_resp_tlast,
memory_tx_write_resp_tready => memory_tx_write_resp_tready,
memory_tx_read_resp_tdata => memory_tx_read_resp_tdata,
memory_tx_read_resp_tvalid => memory_tx_read_resp_tvalid,
memory_tx_read_resp_tlast => memory_tx_read_resp_tlast,
memory_tx_read_resp_tready => memory_tx_read_resp_tready,
--CPLD tx stream
cpld_tx_tdata => cpld_tx_tdata,
cpld_tx_tvalid => cpld_tx_tvalid,
cpld_tx_tready => cpld_tx_tready,
cpld_tx_tlast => cpld_tx_tlast,
--TCP tx stream
tcp_tx_tdata => tcp_tx_tdata,
tcp_tx_tvalid => tcp_tx_tvalid_int,
tcp_tx_tready => tcp_tx_tready
);
end architecture;
| mpl-2.0 | e2136e2a8deba920a0e236b2d8da9e69 | 0.684936 | 2.57083 | false | false | false | false |
CyAScott/CIS4930.DatapathSynthesisTool | src/components/c_multiplexer.vhd | 1 | 898 | library ieee;
use ieee.std_logic_1164.all;
library WORK;
use WORK.all;
entity c_multiplexer is
generic
(
width : integer := 4;
no_of_inputs : integer := 2;
select_size : integer := 1
);
port
(
input : in std_logic_vector(((width * no_of_inputs) - 1) downto 0);
mux_select : in std_logic_vector ((select_size - 1) downto 0);
output : out std_logic_vector ((width - 1) downto 0)
);
end c_multiplexer;
architecture behavior of c_multiplexer is
begin
P1 : process (mux_select, input)
variable control_val : integer := 0;
variable base_val : integer := 1;
begin
base_val := 1;
control_val := 0;
for i in 0 to (select_size - 1) loop
if (mux_select(i) = '1') then
control_val := control_val + base_val;
end if;
base_val := base_val * 2;
end loop;
output <= input(((control_val + 1) * width - 1) downto (control_val) * width);
end process P1;
end behavior; | mit | 5a46923f4fbbceb323bbe977edfe9b71 | 0.641425 | 2.823899 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/ld_arith_reg2.vhd | 15 | 17,134 | -------------------------------------------------------------------------------
-- $Id: ld_arith_reg2.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- Loadable arithmetic register.
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ld_arith_reg2.vhd
-- Version:
--------------------------------------------------------------------------------
-- Description: A register that can be loaded and added to or subtracted from
-- (but not both). The width of the register is specified
-- with a generic. The load value and the arith
-- value, i.e. the value to be added (subtracted), may be of
-- lesser width than the register and may be
-- offset from the LSB position. (Uncovered positions
-- load or add (subtract) zero.) The register can be
-- reset, via the RST signal, to a freely selectable value.
-- The register is defined in terms of big-endian bit ordering.
--
-- ld_arith_reg2 is derived from ld_arith_reg. There are a few
-- changes:
-- - The control signal for load is active-low, LOAD_n.
-- - Boolean generic C_LOAD_OVERRIDES reverses the default that
-- OP overrides LOAD_n when both are asserted on the
-- same cycle.
-- - The default width is 32.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ld_arith_reg2.vhd
-------------------------------------------------------------------------------
-- Author: FO
--
-- History:
--
-- FO 09/01/03 -- First version, derived from ld_arith_reg
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ld_arith_reg2 is
generic (
------------------------------------------------------------------------
-- True if the arithmetic operation is add, false if subtract.
C_ADD_SUB_NOT : boolean := false;
------------------------------------------------------------------------
-- Width of the register.
C_REG_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Reset value. (No default, must be specified in the instantiation.)
C_RESET_VALUE : std_logic_vector;
------------------------------------------------------------------------
-- Width of the load data.
C_LD_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Offset from the LSB (toward more significant) of the load data.
C_LD_OFFSET : natural := 0;
------------------------------------------------------------------------
-- Width of the arithmetic data.
C_AD_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Offset from the LSB of the arithmetic data.
C_AD_OFFSET : natural := 0;
------------------------------------------------------------------------
C_LOAD_OVERRIDES : boolean := false
------------------------------------------------------------------------
-- Dependencies: (1) C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
-- (2) C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
------------------------------------------------------------------------
);
port (
CK : in std_logic;
RST : in std_logic; -- Reset to C_RESET_VALUE. (Overrides OP,LOAD_n)
Q : out std_logic_vector(0 to C_REG_WIDTH-1);
LD : in std_logic_vector(0 to C_LD_WIDTH-1); -- Load data.
AD : in std_logic_vector(0 to C_AD_WIDTH-1); -- Arith data.
LOAD_n : in std_logic; -- Active-low enable for the load op, Q <= LD.
OP : in std_logic -- Enable for the arith op, Q <= Q + AD.
-- (Q <= Q - AD if C_ADD_SUB_NOT = false.)
-- (Overrrides LOAD_n
-- unless C_LOAD_OVERRIDES = true)
);
end ld_arith_reg2;
library unisim;
use unisim.all;
library ieee;
use ieee.numeric_std.all;
architecture imp of ld_arith_reg2 is
component MULT_AND
port(
LO : out std_ulogic;
I1 : in std_ulogic;
I0 : in std_ulogic);
end component;
component MUXCY is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
O : out std_logic);
end component MUXCY;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
component FDSE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
S : in std_logic
);
end component FDSE;
signal q_i,
q_i_ns,
xorcy_out,
gen_cry_kill_n : std_logic_vector(0 to C_REG_WIDTH-1);
signal cry : std_logic_vector(0 to C_REG_WIDTH);
begin
-- synthesis translate_off
assert C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg2, constraint does not hold: " &
"C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH"
severity error;
assert C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg2, constraint does not hold: " &
"C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH"
severity error;
-- synthesis translate_on
Q <= q_i;
cry(C_REG_WIDTH) <=
'0' when C_ADD_SUB_NOT else
LOAD_n when not C_ADD_SUB_NOT and C_LOAD_OVERRIDES else
OP; -- when not C_ADD_SUB_NOT and not C_LOAD_OVERRIDES
PERBIT_GEN: for j in C_REG_WIDTH-1 downto 0 generate
signal load_bit, arith_bit, CE : std_logic;
begin
------------------------------------------------------------------------
-- Assign to load_bit either zero or the bit from input port LD.
------------------------------------------------------------------------
D_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_LD_OFFSET
or j < C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET generate
load_bit <= '0';
end generate;
D_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_LD_OFFSET
and j >= C_REG_WIDTH - C_LD_OFFSET - C_LD_WIDTH
generate
load_bit <= LD(j - (C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET));
end generate;
------------------------------------------------------------------------
-- Assign to arith_bit either zero or the bit from input port AD.
------------------------------------------------------------------------
AD_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_AD_OFFSET
or j < C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET
generate
arith_bit <= '0';
end generate;
AD_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_AD_OFFSET
and j >= C_REG_WIDTH - C_AD_OFFSET - C_AD_WIDTH
generate
arith_bit <= AD(j - (C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET));
end generate;
------------------------------------------------------------------------
-- LUT output generation.
------------------------------------------------------------------------
------------------------------------------------------------------------
-- Adder case, OP overrides LOAD_n
------------------------------------------------------------------------
Q_I_GEN_ADD_OO: if C_ADD_SUB_NOT and not C_LOAD_OVERRIDES generate
q_i_ns(j) <= q_i(j) xor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Adder case, LOAD_n overrides OP
------------------------------------------------------------------------
Q_I_GEN_ADD_LO: if C_ADD_SUB_NOT and C_LOAD_OVERRIDES generate
q_i_ns(j) <= load_bit when LOAD_n = '0' else q_i(j) xor arith_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case, OP overrides LOAD_n
------------------------------------------------------------------------
Q_I_GEN_SUB_OO: if not C_ADD_SUB_NOT and not C_LOAD_OVERRIDES generate
q_i_ns(j) <= q_i(j) xnor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case, LOAD_n overrides OP
------------------------------------------------------------------------
Q_I_GEN_SUB_LO: if not C_ADD_SUB_NOT and C_LOAD_OVERRIDES generate
q_i_ns(j) <= load_bit when LOAD_n = '0' else q_i(j) xnor arith_bit;
end generate;
------------------------------------------------------------------------
-- Kill carries (borrows) for loads but
-- generate or kill carries (borrows) for add (sub).
------------------------------------------------------------------------
MULT_AND_OO_GEN : if not C_LOAD_OVERRIDES generate
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => OP,
I0 => Q_i(j)
);
end generate;
MULT_AND_LO_GEN : if C_LOAD_OVERRIDES generate
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => LOAD_n,
I0 => Q_i(j)
);
end generate;
------------------------------------------------------------------------
-- Propagate the carry (borrow) out.
------------------------------------------------------------------------
MUXCY_i1: MUXCY
port map (
DI => gen_cry_kill_n(j),
CI => cry(j+1),
S => q_i_ns(j),
O => cry(j)
);
------------------------------------------------------------------------
-- Apply the effect of carry (borrow) in.
------------------------------------------------------------------------
XORCY_i1: XORCY
port map (
LI => q_i_ns(j),
CI => cry(j+1),
O => xorcy_out(j)
);
CE <= not LOAD_n or OP;
------------------------------------------------------------------------
-- Generate either a resettable or setable FF for bit j, depending
-- on C_RESET_VALUE at bit j.
------------------------------------------------------------------------
FF_RST0_GEN: if C_RESET_VALUE(j) = '0' generate
FDRE_i1: FDRE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
R => RST
);
end generate;
FF_RST1_GEN: if C_RESET_VALUE(j) = '1' generate
FDSE_i1: FDSE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
S => RST
);
end generate;
end generate;
end imp;
| apache-2.0 | 90eba7786932026b96ce945938b1a2ec | 0.381989 | 4.943451 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/LEKO_LEKU/leku/LEKU-CD'/25_18.vhd | 1 | 133,508 | Library IEEE;
use IEEE.std_logic_1164.all;
entity x25_18x is
Port (
A302,A301,A300,A299,A298,A269,A268,A267,A266,A265,A236,A235,A234,A233,A232,A203,A202,A201,A200,A199,A166,A167,A168,A169,A170: in std_logic;
A41: buffer std_logic
);
end x25_18x;
architecture x25_18x_behav of x25_18x is
signal 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50a,a6254a,a6255a,a6256a,a6260a,a6261a,a6265a,a6266a,a6267a,a6271a,a6272a,a6276a,a6277a,a6278a,a6282a,a6283a,a6287a,a6288a,a6289a,a6293a,a6294a,a6298a,a6299a,a6300a,a6304a,a6305a,a6309a,a6310a,a6311a,a6315a,a6316a,a6320a,a6321a,a6322a,a6326a,a6327a,a6331a,a6332a,a6333a,a6337a,a6338a,a6342a,a6343a,a6344a,a6348a,a6349a,a6353a,a6354a,a6355a,a6359a,a6360a,a6364a,a6365a,a6366a,a6370a,a6371a,a6375a,a6376a,a6377a,a6381a,a6382a,a6386a,a6387a,a6388a,a6392a,a6393a,a6397a,a6398a,a6399a,a6403a,a6404a,a6408a,a6409a,a6410a,a6414a,a6415a,a6419a,a6420a,a6421a,a6425a,a6426a,a6430a,a6431a,a6432a,a6436a,a6437a,a6441a,a6442a,a6443a,a6447a,a6448a,a6452a,a6453a,a6454a,a6458a,a6459a,a6463a,a6464a,a6465a,a6469a,a6470a,a6474a,a6475a,a6476a,a6480a,a6481a,a6485a,a6486a,a6487a,a6491a,a6492a,a6496a,a6497a,a6498a,a6502a,a6503a,a6507a,a6508a,a6509a,a6513a,a6514a,a6518a,a6519a,a6520a,a6524a,a6525a,a6529a,a6530a,a6531a,a6535a,a6536a,a6540a,a6541a,a6542a,a6546a,a6547a,a6551a,a6552a,a6553a,a6557a,a6558a,a6562a,a6563a,a6564a,a6568a,a6569a,a6573a,a6574a,a6575a,a6579a,a6580a,a6584a,a6585a,a6586a,a6590a,a6591a,a6595a,a6596a,a6597a,a6601a,a6602a,a6606a,a6607a,a6608a,a6612a,a6613a,a6617a,a6618a,a6619a,a6623a,a6624a,a6628a,a6629a,a6630a,a6634a,a6635a,a6639a,a6640a,a6641a,a6645a,a6646a,a6650a,a6651a,a6652a,a6656a,a6657a,a6661a,a6662a,a6663a,a6667a,a6668a,a6672a,a6673a,a6674a: std_logic;
begin
A41 <=( a1042a ) or ( a695a );
a1a <=( a6674a and a6663a );
a2a <=( a6652a and a6641a );
a3a <=( a6630a and a6619a );
a4a <=( a6608a and a6597a );
a5a <=( a6586a and a6575a );
a6a <=( a6564a and a6553a );
a7a <=( a6542a and a6531a );
a8a <=( a6520a and a6509a );
a9a <=( a6498a and a6487a );
a10a <=( a6476a and a6465a );
a11a <=( a6454a and a6443a );
a12a <=( a6432a and a6421a );
a13a <=( a6410a and a6399a );
a14a <=( a6388a and a6377a );
a15a <=( a6366a and a6355a );
a16a <=( a6344a and a6333a );
a17a <=( a6322a and a6311a );
a18a <=( a6300a and a6289a );
a19a <=( a6278a and a6267a );
a20a <=( a6256a and a6245a );
a21a <=( a6234a and a6223a );
a22a <=( a6212a and a6201a );
a23a <=( a6190a and a6179a );
a24a <=( a6168a and a6157a );
a25a <=( a6146a and a6135a );
a26a <=( a6124a and a6113a );
a27a <=( a6102a and a6091a );
a28a <=( a6080a and a6069a );
a29a <=( a6058a and a6047a );
a30a <=( a6036a and a6025a );
a31a <=( a6014a and a6003a );
a32a <=( a5992a and a5981a );
a33a <=( a5970a and a5959a );
a34a <=( a5948a and a5937a );
a35a <=( a5926a and a5915a );
a36a <=( a5904a and a5893a );
a37a <=( a5882a and a5871a );
a38a <=( a5860a and a5849a );
a39a <=( a5838a and a5827a );
a40a <=( a5816a and a5805a );
a41a <=( a5794a and a5783a );
a42a <=( a5772a and a5761a );
a43a <=( a5750a and a5739a );
a44a <=( a5728a and a5717a );
a45a <=( a5706a and a5695a );
a46a <=( a5684a and a5673a );
a47a <=( a5662a and a5651a );
a48a <=( a5640a and a5629a );
a49a <=( a5618a and a5607a );
a50a <=( a5598a and a5587a );
a51a <=( a5578a and a5567a );
a52a <=( a5558a and a5547a );
a53a <=( a5538a and a5527a );
a54a <=( a5518a and a5507a );
a55a <=( a5498a and a5487a );
a56a <=( a5478a and a5467a );
a57a <=( a5458a and a5447a );
a58a <=( a5438a and a5427a );
a59a <=( a5418a and a5407a );
a60a <=( a5398a and a5387a );
a61a <=( a5378a and a5367a );
a62a <=( a5358a and a5347a );
a63a <=( a5338a and a5327a );
a64a <=( a5318a and a5307a );
a65a <=( a5298a and a5287a );
a66a <=( a5278a and a5267a );
a67a <=( a5258a and a5247a );
a68a <=( a5238a and a5227a );
a69a <=( a5218a and a5207a );
a70a <=( a5198a and a5187a );
a71a <=( a5178a and a5167a );
a72a <=( a5158a and a5147a );
a73a <=( a5138a and a5127a );
a74a <=( a5118a and a5107a );
a75a <=( a5098a and a5087a );
a76a <=( a5078a and a5067a );
a77a <=( a5058a and a5047a );
a78a <=( a5038a and a5027a );
a79a <=( a5018a and a5007a );
a80a <=( a4998a and a4987a );
a81a <=( a4978a and a4969a );
a82a <=( a4960a and a4951a );
a83a <=( a4942a and a4933a );
a84a <=( a4924a and a4915a );
a85a <=( a4906a and a4897a );
a86a <=( a4888a and a4879a );
a87a <=( a4870a and a4861a );
a88a <=( a4852a and a4843a );
a89a <=( a4834a and a4825a );
a90a <=( a4816a and a4807a );
a91a <=( a4798a and a4789a );
a92a <=( a4780a and a4771a );
a93a <=( a4762a and a4753a );
a94a <=( a4744a and a4735a );
a95a <=( a4726a and a4717a );
a96a <=( a4708a and a4699a );
a97a <=( a4690a and a4681a );
a98a <=( a4672a and a4663a );
a99a <=( a4654a and a4645a );
a100a <=( a4636a and a4627a );
a101a <=( a4618a and a4609a );
a102a <=( a4600a and a4591a );
a103a <=( a4582a and a4573a );
a104a <=( a4564a and a4555a );
a105a <=( a4546a and a4537a );
a106a <=( a4528a and a4519a );
a107a <=( a4510a and a4501a );
a108a <=( a4492a and a4483a );
a109a <=( a4474a and a4465a );
a110a <=( a4456a and a4447a );
a111a <=( a4438a and a4429a );
a112a <=( a4420a and a4411a );
a113a <=( a4402a and a4393a );
a114a <=( a4384a and a4375a );
a115a <=( a4366a and a4357a );
a116a <=( a4348a and a4339a );
a117a <=( a4330a and a4321a );
a118a <=( a4312a and a4303a );
a119a <=( a4294a and a4285a );
a120a <=( a4276a and a4267a );
a121a <=( a4258a and a4249a );
a122a <=( a4240a and a4231a );
a123a <=( a4222a and a4213a );
a124a <=( a4204a and a4195a );
a125a <=( a4186a and a4177a );
a126a <=( a4168a and a4159a );
a127a <=( a4150a and a4141a );
a128a <=( a4132a and a4123a );
a129a <=( a4114a and a4105a );
a130a <=( a4096a and a4087a );
a131a <=( a4078a and a4069a );
a132a <=( a4060a and a4051a );
a133a <=( a4042a and a4033a );
a134a <=( a4024a and a4015a );
a135a <=( a4006a and a3997a );
a136a <=( a3988a and a3979a );
a137a <=( a3970a and a3961a );
a138a <=( a3952a and a3943a );
a139a <=( a3934a and a3925a );
a140a <=( a3916a and a3907a );
a141a <=( a3898a and a3889a );
a142a <=( a3880a and a3871a );
a143a <=( a3862a and a3853a );
a144a <=( a3844a and a3835a );
a145a <=( a3826a and a3817a );
a146a <=( a3808a and a3799a );
a147a <=( a3790a and a3781a );
a148a <=( a3772a and a3763a );
a149a <=( a3754a and a3745a );
a150a <=( a3736a and a3727a );
a151a <=( a3718a and a3709a );
a152a <=( a3700a and a3691a );
a153a <=( a3682a and a3673a );
a154a <=( a3664a and a3655a );
a155a <=( a3646a and a3637a );
a156a <=( a3628a and a3619a );
a157a <=( a3610a and a3601a );
a158a <=( a3592a and a3583a );
a159a <=( a3574a and a3565a );
a160a <=( a3556a and a3547a );
a161a <=( a3538a and a3529a );
a162a <=( a3520a and a3511a );
a163a <=( a3502a and a3493a );
a164a <=( a3484a and a3475a );
a165a <=( a3466a and a3457a );
a166a <=( a3448a and a3439a );
a167a <=( a3430a and a3421a );
a168a <=( a3412a and a3403a );
a169a <=( a3394a and a3385a );
a170a <=( a3376a and a3367a );
a171a <=( a3358a and a3349a );
a172a <=( a3340a and a3331a );
a173a <=( a3322a and a3313a );
a174a <=( a3304a and a3295a );
a175a <=( a3286a and a3277a );
a176a <=( a3268a and a3259a );
a177a <=( a3250a and a3241a );
a178a <=( a3234a and a3225a );
a179a <=( a3218a and a3209a );
a180a <=( a3202a and a3193a );
a181a <=( a3186a and a3177a );
a182a <=( a3170a and a3161a );
a183a <=( a3154a and a3145a );
a184a <=( a3138a and a3129a );
a185a <=( a3122a and a3113a );
a186a <=( a3106a and a3097a );
a187a <=( a3090a and a3081a );
a188a <=( a3074a and a3065a );
a189a <=( a3058a and a3049a );
a190a <=( a3042a and a3033a );
a191a <=( a3026a and a3017a );
a192a <=( a3010a and a3001a );
a193a <=( a2994a and a2985a );
a194a <=( a2978a and a2969a );
a195a <=( a2962a and a2953a );
a196a <=( a2946a and a2937a );
a197a <=( a2930a and a2921a );
a198a <=( a2914a and a2905a );
a199a <=( a2898a and a2889a );
a200a <=( a2882a and a2873a );
a201a <=( a2866a and a2857a );
a202a <=( a2850a and a2841a );
a203a <=( a2834a and a2825a );
a204a <=( a2818a and a2809a );
a205a <=( a2802a and a2793a );
a206a <=( a2786a and a2777a );
a207a <=( a2770a and a2761a );
a208a <=( a2754a and a2745a );
a209a <=( a2738a and a2731a );
a210a <=( a2724a and a2717a );
a211a <=( a2710a and a2703a );
a212a <=( a2696a and a2689a );
a213a <=( a2682a and a2675a );
a214a <=( a2668a and a2661a );
a215a <=( a2654a and a2647a );
a216a <=( a2640a and a2633a );
a217a <=( a2626a and a2619a );
a218a <=( a2612a and a2605a );
a219a <=( a2598a and a2591a );
a220a <=( a2584a and a2577a );
a221a <=( a2570a and a2563a );
a222a <=( a2556a and a2549a );
a223a <=( a2542a and a2535a );
a224a <=( a2528a and a2521a );
a225a <=( a2514a and a2507a );
a226a <=( a2500a and a2493a );
a227a <=( a2486a and a2479a );
a228a <=( a2472a and a2465a );
a229a <=( a2458a and a2451a );
a230a <=( a2444a and a2437a );
a231a <=( a2430a and a2423a );
a232a <=( a2416a and a2409a );
a233a <=( a2402a and a2395a );
a234a <=( a2388a and a2381a );
a235a <=( a2374a and a2367a );
a236a <=( a2360a and a2353a );
a237a <=( a2346a and a2339a );
a238a <=( a2332a and a2325a );
a239a <=( a2318a and a2311a );
a240a <=( a2304a and a2297a );
a241a <=( a2290a and a2283a );
a242a <=( a2276a and a2269a );
a243a <=( a2262a and a2255a );
a244a <=( a2248a and a2241a );
a245a <=( a2234a and a2227a );
a246a <=( a2220a and a2213a );
a247a <=( a2206a and a2199a );
a248a <=( a2192a and a2185a );
a249a <=( a2178a and a2171a );
a250a <=( a2164a and a2157a );
a251a <=( a2150a and a2143a );
a252a <=( a2136a and a2129a );
a253a <=( a2122a and a2115a );
a254a <=( a2108a and a2101a );
a255a <=( a2094a and a2087a );
a256a <=( a2080a and a2073a );
a257a <=( a2066a and a2059a );
a258a <=( a2052a and a2045a );
a259a <=( a2038a and a2031a );
a260a <=( a2024a and a2017a );
a261a <=( a2010a and a2003a );
a262a <=( a1996a and a1989a );
a263a <=( a1982a and a1975a );
a264a <=( a1968a and a1961a );
a265a <=( a1954a and a1947a );
a266a <=( a1940a and a1933a );
a267a <=( a1926a and a1919a );
a268a <=( a1912a and a1905a );
a269a <=( a1898a and a1891a );
a270a <=( a1884a and a1877a );
a271a <=( a1870a and a1863a );
a272a <=( a1856a and a1849a );
a273a <=( a1842a and a1835a );
a274a <=( a1828a and a1821a );
a275a <=( a1814a and a1807a );
a276a <=( a1800a and a1793a );
a277a <=( a1786a and a1779a );
a278a <=( a1772a and a1765a );
a279a <=( a1758a and a1751a );
a280a <=( a1744a and a1737a );
a281a <=( a1730a and a1723a );
a282a <=( a1716a and a1709a );
a283a <=( a1702a and a1695a );
a284a <=( a1688a and a1681a );
a285a <=( a1674a and a1667a );
a286a <=( a1660a and a1653a );
a287a <=( a1646a and a1639a );
a288a <=( a1632a and a1625a );
a289a <=( a1618a and a1611a );
a290a <=( a1604a and a1597a );
a291a <=( a1590a and a1583a );
a292a <=( a1576a and a1569a );
a293a <=( a1562a and a1555a );
a294a <=( a1550a and a1543a );
a295a <=( a1538a and a1531a );
a296a <=( a1526a and a1519a );
a297a <=( a1514a and a1507a );
a298a <=( a1502a and a1495a );
a299a <=( a1490a and a1483a );
a300a <=( a1478a and a1471a );
a301a <=( a1466a and a1461a );
a302a <=( a1456a and a1451a );
a303a <=( a1446a and a1441a );
a304a <=( a1436a and a1431a );
a305a <=( a1426a and a1421a );
a306a <=( a1416a and a1411a );
a307a <=( a1406a and a1401a );
a308a <=( a1396a and a1391a );
a309a <=( a1386a and a1381a );
a310a <=( a1376a and a1371a );
a311a <=( a1366a and a1361a );
a312a <=( a1356a and a1351a );
a313a <=( a1346a and a1341a );
a314a <=( a1336a and a1331a );
a315a <=( a1326a and a1321a );
a316a <=( a1316a and a1311a );
a317a <=( a1306a and a1301a );
a318a <=( a1296a and a1291a );
a319a <=( a1286a and a1281a );
a320a <=( a1276a and a1271a );
a321a <=( a1266a and a1261a );
a322a <=( a1256a and a1251a );
a323a <=( a1246a and a1241a );
a324a <=( a1236a and a1231a );
a325a <=( a1226a and a1221a );
a326a <=( a1216a and a1211a );
a327a <=( a1206a and a1201a );
a328a <=( a1196a and a1191a );
a329a <=( a1186a and a1181a );
a330a <=( a1176a and a1171a );
a331a <=( a1166a and a1161a );
a332a <=( a1156a and a1151a );
a333a <=( a1146a and a1141a );
a334a <=( a1136a and a1131a );
a335a <=( a1126a and a1121a );
a336a <=( a1116a and a1111a );
a337a <=( a1106a and a1103a );
a338a <=( a1100a and a1097a );
a339a <=( a1094a and a1091a );
a340a <=( a1088a and a1085a );
a341a <=( a1082a and a1079a );
a342a <=( a1076a and a1073a );
a343a <=( a1070a and a1067a );
a344a <=( a1064a and a1061a );
a345a <=( a1058a and a1055a );
a346a <=( a1052a and a1049a );
a347a <=( A267 and A266 );
a348a <=( A267 and A265 );
a351a <=( a347a ) or ( a348a );
a355a <=( a344a ) or ( a345a );
a356a <=( a346a ) or ( a355a );
a357a <=( a356a ) or ( a351a );
a360a <=( a342a ) or ( a343a );
a364a <=( a339a ) or ( a340a );
a365a <=( a341a ) or ( a364a );
a366a <=( a365a ) or ( a360a );
a367a <=( a366a ) or ( a357a );
a370a <=( a337a ) or ( a338a );
a374a <=( a334a ) or ( a335a );
a375a <=( a336a ) or ( a374a );
a376a <=( a375a ) or ( a370a );
a380a <=( a331a ) or ( a332a );
a381a <=( a333a ) or ( a380a );
a385a <=( a328a ) or ( a329a );
a386a <=( a330a ) or ( a385a );
a387a <=( a386a ) or ( a381a );
a388a <=( a387a ) or ( a376a );
a389a <=( a388a ) or ( a367a );
a392a <=( a326a ) or ( a327a );
a396a <=( a323a ) or ( a324a );
a397a <=( a325a ) or ( a396a );
a398a <=( a397a ) or ( a392a );
a402a <=( a320a ) or ( a321a );
a403a <=( a322a ) or ( a402a );
a407a <=( a317a ) or ( a318a );
a408a <=( a319a ) or ( a407a );
a409a <=( a408a ) or ( a403a );
a410a <=( a409a ) or ( a398a );
a413a <=( a315a ) or ( a316a );
a417a <=( a312a ) or ( a313a );
a418a <=( a314a ) or ( a417a );
a419a <=( a418a ) or ( a413a );
a423a <=( a309a ) or ( a310a );
a424a <=( a311a ) or ( a423a );
a428a <=( a306a ) or ( a307a );
a429a <=( a308a ) or ( a428a );
a430a <=( a429a ) or ( a424a );
a431a <=( a430a ) or ( a419a );
a432a <=( a431a ) or ( a410a );
a433a <=( a432a ) or ( a389a );
a436a <=( a304a ) or ( a305a );
a440a <=( a301a ) or ( a302a );
a441a <=( a303a ) or ( a440a );
a442a <=( a441a ) or ( a436a );
a446a <=( a298a ) or ( a299a );
a447a <=( a300a ) or ( a446a );
a451a <=( a295a ) or ( a296a );
a452a <=( a297a ) or ( a451a );
a453a <=( a452a ) or ( a447a );
a454a <=( a453a ) or ( a442a );
a457a <=( a293a ) or ( a294a );
a461a <=( a290a ) or ( a291a );
a462a <=( a292a ) or ( a461a );
a463a <=( a462a ) or ( a457a );
a467a <=( a287a ) or ( a288a );
a468a <=( a289a ) or ( a467a );
a472a <=( a284a ) or ( a285a );
a473a <=( a286a ) or ( a472a );
a474a <=( a473a ) or ( a468a );
a475a <=( a474a ) or ( a463a );
a476a <=( a475a ) or ( a454a );
a479a <=( a282a ) or ( a283a );
a483a <=( a279a ) or ( a280a );
a484a <=( a281a ) or ( a483a );
a485a <=( a484a ) or ( a479a );
a489a <=( a276a ) or ( a277a );
a490a <=( a278a ) or ( a489a );
a494a <=( a273a ) or ( a274a );
a495a <=( a275a ) or ( a494a );
a496a <=( a495a ) or ( a490a );
a497a <=( a496a ) or ( a485a );
a500a <=( a271a ) or ( a272a );
a504a <=( a268a ) or ( a269a );
a505a <=( a270a ) or ( a504a );
a506a <=( a505a ) or ( a500a );
a510a <=( a265a ) or ( a266a );
a511a <=( a267a ) or ( a510a );
a515a <=( a262a ) or ( a263a );
a516a <=( a264a ) or ( a515a );
a517a <=( a516a ) or ( a511a );
a518a <=( a517a ) or ( a506a );
a519a <=( a518a ) or ( a497a );
a520a <=( a519a ) or ( a476a );
a521a <=( a520a ) or ( a433a );
a524a <=( a260a ) or ( a261a );
a528a <=( a257a ) or ( a258a );
a529a <=( a259a ) or ( a528a );
a530a <=( a529a ) or ( a524a );
a533a <=( a255a ) or ( a256a );
a537a <=( a252a ) or ( a253a );
a538a <=( a254a ) or ( a537a );
a539a <=( a538a ) or ( a533a );
a540a <=( a539a ) or ( a530a );
a543a <=( a250a ) or ( a251a );
a547a <=( a247a ) or ( a248a );
a548a <=( a249a ) or ( a547a );
a549a <=( a548a ) or ( a543a );
a553a <=( a244a ) or ( a245a );
a554a <=( a246a ) or ( a553a );
a558a <=( a241a ) or ( a242a );
a559a <=( a243a ) or ( a558a );
a560a <=( a559a ) or ( a554a );
a561a <=( a560a ) or ( a549a );
a562a <=( a561a ) or ( a540a );
a565a <=( a239a ) or ( a240a );
a569a <=( a236a ) or ( a237a );
a570a <=( a238a ) or ( a569a );
a571a <=( a570a ) or ( a565a );
a575a <=( a233a ) or ( a234a );
a576a <=( a235a ) or ( a575a );
a580a <=( a230a ) or ( a231a );
a581a <=( a232a ) or ( a580a );
a582a <=( a581a ) or ( a576a );
a583a <=( a582a ) or ( a571a );
a586a <=( a228a ) or ( a229a );
a590a <=( a225a ) or ( a226a );
a591a <=( a227a ) or ( a590a );
a592a <=( a591a ) or ( a586a );
a596a <=( a222a ) or ( a223a );
a597a <=( a224a ) or ( a596a );
a601a <=( a219a ) or ( a220a );
a602a <=( a221a ) or ( a601a );
a603a <=( a602a ) or ( a597a );
a604a <=( a603a ) or ( a592a );
a605a <=( a604a ) or ( a583a );
a606a <=( a605a ) or ( a562a );
a609a <=( a217a ) or ( a218a );
a613a <=( a214a ) or ( a215a );
a614a <=( a216a ) or ( a613a );
a615a <=( a614a ) or ( a609a );
a619a <=( a211a ) or ( a212a );
a620a <=( a213a ) or ( a619a );
a624a <=( a208a ) or ( a209a );
a625a <=( a210a ) or ( a624a );
a626a <=( a625a ) or ( a620a );
a627a <=( a626a ) or ( a615a );
a630a <=( a206a ) or ( a207a );
a634a <=( a203a ) or ( a204a );
a635a <=( a205a ) or ( a634a );
a636a <=( a635a ) or ( a630a );
a640a <=( a200a ) or ( a201a );
a641a <=( a202a ) or ( a640a );
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a646a <=( a199a ) or ( a645a );
a647a <=( a646a ) or ( a641a );
a648a <=( a647a ) or ( a636a );
a649a <=( a648a ) or ( a627a );
a652a <=( a195a ) or ( a196a );
a656a <=( a192a ) or ( a193a );
a657a <=( a194a ) or ( a656a );
a658a <=( a657a ) or ( a652a );
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a663a <=( a191a ) or ( a662a );
a667a <=( a186a ) or ( a187a );
a668a <=( a188a ) or ( a667a );
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a670a <=( a669a ) or ( a658a );
a673a <=( a184a ) or ( a185a );
a677a <=( a181a ) or ( a182a );
a678a <=( a183a ) or ( a677a );
a679a <=( a678a ) or ( a673a );
a683a <=( a178a ) or ( a179a );
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a688a <=( a175a ) or ( a176a );
a689a <=( a177a ) or ( a688a );
a690a <=( a689a ) or ( a684a );
a691a <=( a690a ) or ( a679a );
a692a <=( a691a ) or ( a670a );
a693a <=( a692a ) or ( a649a );
a694a <=( a693a ) or ( a606a );
a695a <=( a694a ) or ( a521a );
a698a <=( a173a ) or ( a174a );
a702a <=( a170a ) or ( a171a );
a703a <=( a172a ) or ( a702a );
a704a <=( a703a ) or ( a698a );
a707a <=( a168a ) or ( a169a );
a711a <=( a165a ) or ( a166a );
a712a <=( a167a ) or ( a711a );
a713a <=( a712a ) or ( a707a );
a714a <=( a713a ) or ( a704a );
a717a <=( a163a ) or ( a164a );
a721a <=( a160a ) or ( a161a );
a722a <=( a162a ) or ( a721a );
a723a <=( a722a ) or ( a717a );
a727a <=( a157a ) or ( a158a );
a728a <=( a159a ) or ( a727a );
a732a <=( a154a ) or ( a155a );
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a734a <=( a733a ) or ( a728a );
a735a <=( a734a ) or ( a723a );
a736a <=( a735a ) or ( a714a );
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a743a <=( a149a ) or ( a150a );
a744a <=( a151a ) or ( a743a );
a745a <=( a744a ) or ( a739a );
a749a <=( a146a ) or ( a147a );
a750a <=( a148a ) or ( a749a );
a754a <=( a143a ) or ( a144a );
a755a <=( a145a ) or ( a754a );
a756a <=( a755a ) or ( a750a );
a757a <=( a756a ) or ( a745a );
a760a <=( a141a ) or ( a142a );
a764a <=( a138a ) or ( a139a );
a765a <=( a140a ) or ( a764a );
a766a <=( a765a ) or ( a760a );
a770a <=( a135a ) or ( a136a );
a771a <=( a137a ) or ( a770a );
a775a <=( a132a ) or ( a133a );
a776a <=( a134a ) or ( a775a );
a777a <=( a776a ) or ( a771a );
a778a <=( a777a ) or ( a766a );
a779a <=( a778a ) or ( a757a );
a780a <=( a779a ) or ( a736a );
a783a <=( a130a ) or ( a131a );
a787a <=( a127a ) or ( a128a );
a788a <=( a129a ) or ( a787a );
a789a <=( a788a ) or ( a783a );
a793a <=( a124a ) or ( a125a );
a794a <=( a126a ) or ( a793a );
a798a <=( a121a ) or ( a122a );
a799a <=( a123a ) or ( a798a );
a800a <=( a799a ) or ( a794a );
a801a <=( a800a ) or ( a789a );
a804a <=( a119a ) or ( a120a );
a808a <=( a116a ) or ( a117a );
a809a <=( a118a ) or ( a808a );
a810a <=( a809a ) or ( a804a );
a814a <=( a113a ) or ( a114a );
a815a <=( a115a ) or ( a814a );
a819a <=( a110a ) or ( a111a );
a820a <=( a112a ) or ( a819a );
a821a <=( a820a ) or ( a815a );
a822a <=( a821a ) or ( a810a );
a823a <=( a822a ) or ( a801a );
a826a <=( a108a ) or ( a109a );
a830a <=( a105a ) or ( a106a );
a831a <=( a107a ) or ( a830a );
a832a <=( a831a ) or ( a826a );
a836a <=( a102a ) or ( a103a );
a837a <=( a104a ) or ( a836a );
a841a <=( a99a ) or ( a100a );
a842a <=( a101a ) or ( a841a );
a843a <=( a842a ) or ( a837a );
a844a <=( a843a ) or ( a832a );
a847a <=( a97a ) or ( a98a );
a851a <=( a94a ) or ( a95a );
a852a <=( a96a ) or ( a851a );
a853a <=( a852a ) or ( a847a );
a857a <=( a91a ) or ( a92a );
a858a <=( a93a ) or ( a857a );
a862a <=( a88a ) or ( a89a );
a863a <=( a90a ) or ( a862a );
a864a <=( a863a ) or ( a858a );
a865a <=( a864a ) or ( a853a );
a866a <=( a865a ) or ( a844a );
a867a <=( a866a ) or ( a823a );
a868a <=( a867a ) or ( a780a );
a871a <=( a86a ) or ( a87a );
a875a <=( a83a ) or ( a84a );
a876a <=( a85a ) or ( a875a );
a877a <=( a876a ) or ( a871a );
a880a <=( a81a ) or ( a82a );
a884a <=( a78a ) or ( a79a );
a885a <=( a80a ) or ( a884a );
a886a <=( a885a ) or ( a880a );
a887a <=( a886a ) or ( a877a );
a890a <=( a76a ) or ( a77a );
a894a <=( a73a ) or ( a74a );
a895a <=( a75a ) or ( a894a );
a896a <=( a895a ) or ( a890a );
a900a <=( a70a ) or ( a71a );
a901a <=( a72a ) or ( a900a );
a905a <=( a67a ) or ( a68a );
a906a <=( a69a ) or ( a905a );
a907a <=( a906a ) or ( a901a );
a908a <=( a907a ) or ( a896a );
a909a <=( a908a ) or ( a887a );
a912a <=( a65a ) or ( a66a );
a916a <=( a62a ) or ( a63a );
a917a <=( a64a ) or ( a916a );
a918a <=( a917a ) or ( a912a );
a922a <=( a59a ) or ( a60a );
a923a <=( a61a ) or ( a922a );
a927a <=( a56a ) or ( a57a );
a928a <=( a58a ) or ( a927a );
a929a <=( a928a ) or ( a923a );
a930a <=( a929a ) or ( a918a );
a933a <=( a54a ) or ( a55a );
a937a <=( a51a ) or ( a52a );
a938a <=( a53a ) or ( a937a );
a939a <=( a938a ) or ( a933a );
a943a <=( a48a ) or ( a49a );
a944a <=( a50a ) or ( a943a );
a948a <=( a45a ) or ( a46a );
a949a <=( a47a ) or ( a948a );
a950a <=( a949a ) or ( a944a );
a951a <=( a950a ) or ( a939a );
a952a <=( a951a ) or ( a930a );
a953a <=( a952a ) or ( a909a );
a956a <=( a43a ) or ( a44a );
a960a <=( a40a ) or ( a41a );
a961a <=( a42a ) or ( a960a );
a962a <=( a961a ) or ( a956a );
a966a <=( a37a ) or ( a38a );
a967a <=( a39a ) or ( a966a );
a971a <=( a34a ) or ( a35a );
a972a <=( a36a ) or ( a971a );
a973a <=( a972a ) or ( a967a );
a974a <=( a973a ) or ( a962a );
a977a <=( a32a ) or ( a33a );
a981a <=( a29a ) or ( a30a );
a982a <=( a31a ) or ( a981a );
a983a <=( a982a ) or ( a977a );
a987a <=( a26a ) or ( a27a );
a988a <=( a28a ) or ( a987a );
a992a <=( a23a ) or ( a24a );
a993a <=( a25a ) or ( a992a );
a994a <=( a993a ) or ( a988a );
a995a <=( a994a ) or ( a983a );
a996a <=( a995a ) or ( a974a );
a999a <=( a21a ) or ( a22a );
a1003a <=( a18a ) or ( a19a );
a1004a <=( a20a ) or ( a1003a );
a1005a <=( a1004a ) or ( a999a );
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a1010a <=( a17a ) or ( a1009a );
a1014a <=( a12a ) or ( a13a );
a1015a <=( a14a ) or ( a1014a );
a1016a <=( a1015a ) or ( a1010a );
a1017a <=( a1016a ) or ( a1005a );
a1020a <=( a10a ) or ( a11a );
a1024a <=( a7a ) or ( a8a );
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a1031a <=( a6a ) or ( a1030a );
a1035a <=( a1a ) or ( a2a );
a1036a <=( a3a ) or ( a1035a );
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a1038a <=( a1037a ) or ( a1026a );
a1039a <=( a1038a ) or ( a1017a );
a1040a <=( a1039a ) or ( a996a );
a1041a <=( a1040a ) or ( a953a );
a1042a <=( a1041a ) or ( a868a );
a1049a <=( A266 and A265 );
a1052a <=( (not A269) and A268 );
a1055a <=( A266 and (not A265) );
a1058a <=( A269 and (not A268) );
a1061a <=( (not A266) and A265 );
a1064a <=( A269 and (not A268) );
a1067a <=( (not A266) and (not A265) );
a1070a <=( (not A269) and A268 );
a1073a <=( A201 and A199 );
a1076a <=( A234 and A232 );
a1079a <=( A201 and A199 );
a1082a <=( A234 and A233 );
a1085a <=( A201 and A200 );
a1088a <=( A234 and A232 );
a1091a <=( A201 and A200 );
a1094a <=( A234 and A233 );
a1097a <=( (not A166) and A167 );
a1100a <=( A234 and A232 );
a1103a <=( (not A166) and A167 );
a1106a <=( A234 and A233 );
a1110a <=( A232 and A201 );
a1111a <=( A199 and a1110a );
a1115a <=( (not A236) and A235 );
a1116a <=( A233 and a1115a );
a1120a <=( (not A232) and A201 );
a1121a <=( A199 and a1120a );
a1125a <=( A236 and (not A235) );
a1126a <=( A233 and a1125a );
a1130a <=( A232 and A201 );
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a1135a <=( A236 and (not A235) );
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a1140a <=( (not A232) and A201 );
a1141a <=( A199 and a1140a );
a1145a <=( (not A236) and A235 );
a1146a <=( (not A233) and a1145a );
a1150a <=( A232 and A201 );
a1151a <=( A200 and a1150a );
a1155a <=( (not A236) and A235 );
a1156a <=( A233 and a1155a );
a1160a <=( (not A232) and A201 );
a1161a <=( A200 and a1160a );
a1165a <=( A236 and (not A235) );
a1166a <=( A233 and a1165a );
a1170a <=( A232 and A201 );
a1171a <=( A200 and a1170a );
a1175a <=( A236 and (not A235) );
a1176a <=( (not A233) and a1175a );
a1180a <=( (not A232) and A201 );
a1181a <=( A200 and a1180a );
a1185a <=( (not A236) and A235 );
a1186a <=( (not A233) and a1185a );
a1190a <=( A202 and A200 );
a1191a <=( A199 and a1190a );
a1195a <=( A234 and A232 );
a1196a <=( (not A203) and a1195a );
a1200a <=( A202 and A200 );
a1201a <=( A199 and a1200a );
a1205a <=( A234 and A233 );
a1206a <=( (not A203) and a1205a );
a1210a <=( (not A202) and A200 );
a1211a <=( (not A199) and a1210a );
a1215a <=( A234 and A232 );
a1216a <=( A203 and a1215a );
a1220a <=( (not A202) and A200 );
a1221a <=( (not A199) and a1220a );
a1225a <=( A234 and A233 );
a1226a <=( A203 and a1225a );
a1230a <=( (not A202) and (not A200) );
a1231a <=( A199 and a1230a );
a1235a <=( A234 and A232 );
a1236a <=( A203 and a1235a );
a1240a <=( (not A202) and (not A200) );
a1241a <=( A199 and a1240a );
a1245a <=( A234 and A233 );
a1246a <=( A203 and a1245a );
a1250a <=( A202 and (not A200) );
a1251a <=( (not A199) and a1250a );
a1255a <=( A234 and A232 );
a1256a <=( (not A203) and a1255a );
a1260a <=( A202 and (not A200) );
a1261a <=( (not A199) and a1260a );
a1265a <=( A234 and A233 );
a1266a <=( (not A203) and a1265a );
a1270a <=( A199 and A166 );
a1271a <=( A167 and a1270a );
a1275a <=( A300 and A299 );
a1276a <=( A201 and a1275a );
a1280a <=( A199 and A166 );
a1281a <=( A167 and a1280a );
a1285a <=( A300 and A298 );
a1286a <=( A201 and a1285a );
a1290a <=( A200 and A166 );
a1291a <=( A167 and a1290a );
a1295a <=( A300 and A299 );
a1296a <=( A201 and a1295a );
a1300a <=( A200 and A166 );
a1301a <=( A167 and a1300a );
a1305a <=( A300 and A298 );
a1306a <=( A201 and a1305a );
a1310a <=( A232 and (not A166) );
a1311a <=( A167 and a1310a );
a1315a <=( (not A236) and A235 );
a1316a <=( A233 and a1315a );
a1320a <=( (not A232) and (not A166) );
a1321a <=( A167 and a1320a );
a1325a <=( A236 and (not A235) );
a1326a <=( A233 and a1325a );
a1330a <=( A232 and (not A166) );
a1331a <=( A167 and a1330a );
a1335a <=( A236 and (not A235) );
a1336a <=( (not A233) and a1335a );
a1340a <=( (not A232) and (not A166) );
a1341a <=( A167 and a1340a );
a1345a <=( (not A236) and A235 );
a1346a <=( (not A233) and a1345a );
a1350a <=( A199 and (not A166) );
a1351a <=( (not A167) and a1350a );
a1355a <=( A300 and A299 );
a1356a <=( A201 and a1355a );
a1360a <=( A199 and (not A166) );
a1361a <=( (not A167) and a1360a );
a1365a <=( A300 and A298 );
a1366a <=( A201 and a1365a );
a1370a <=( A200 and (not A166) );
a1371a <=( (not A167) and a1370a );
a1375a <=( A300 and A299 );
a1376a <=( A201 and a1375a );
a1380a <=( A200 and (not A166) );
a1381a <=( (not A167) and a1380a );
a1385a <=( A300 and A298 );
a1386a <=( A201 and a1385a );
a1390a <=( A199 and (not A167) );
a1391a <=( (not A168) and a1390a );
a1395a <=( A300 and A299 );
a1396a <=( A201 and a1395a );
a1400a <=( A199 and (not A167) );
a1401a <=( (not A168) and a1400a );
a1405a <=( A300 and A298 );
a1406a <=( A201 and a1405a );
a1410a <=( A200 and (not A167) );
a1411a <=( (not A168) and a1410a );
a1415a <=( A300 and A299 );
a1416a <=( A201 and a1415a );
a1420a <=( A200 and (not A167) );
a1421a <=( (not A168) and a1420a );
a1425a <=( A300 and A298 );
a1426a <=( A201 and a1425a );
a1430a <=( (not A167) and A168 );
a1431a <=( A170 and a1430a );
a1435a <=( A234 and A232 );
a1436a <=( A166 and a1435a );
a1440a <=( (not A167) and A168 );
a1441a <=( A170 and a1440a );
a1445a <=( A234 and A233 );
a1446a <=( A166 and a1445a );
a1450a <=( (not A167) and A168 );
a1451a <=( A169 and a1450a );
a1455a <=( A234 and A232 );
a1456a <=( A166 and a1455a );
a1460a <=( (not A167) and A168 );
a1461a <=( A169 and a1460a );
a1465a <=( A234 and A233 );
a1466a <=( A166 and a1465a );
a1470a <=( (not A199) and (not A166) );
a1471a <=( A167 and a1470a );
a1474a <=( (not A202) and (not A200) );
a1477a <=( A300 and A299 );
a1478a <=( a1477a and a1474a );
a1482a <=( (not A199) and (not A166) );
a1483a <=( A167 and a1482a );
a1486a <=( (not A202) and (not A200) );
a1489a <=( A300 and A298 );
a1490a <=( a1489a and a1486a );
a1494a <=( (not A199) and (not A166) );
a1495a <=( A167 and a1494a );
a1498a <=( A203 and (not A200) );
a1501a <=( A300 and A299 );
a1502a <=( a1501a and a1498a );
a1506a <=( (not A199) and (not A166) );
a1507a <=( A167 and a1506a );
a1510a <=( A203 and (not A200) );
a1513a <=( A300 and A298 );
a1514a <=( a1513a and a1510a );
a1518a <=( (not A167) and (not A169) );
a1519a <=( (not A170) and a1518a );
a1522a <=( A201 and A199 );
a1525a <=( A300 and A299 );
a1526a <=( a1525a and a1522a );
a1530a <=( (not A167) and (not A169) );
a1531a <=( (not A170) and a1530a );
a1534a <=( A201 and A199 );
a1537a <=( A300 and A298 );
a1538a <=( a1537a and a1534a );
a1542a <=( (not A167) and (not A169) );
a1543a <=( (not A170) and a1542a );
a1546a <=( A201 and A200 );
a1549a <=( A300 and A299 );
a1550a <=( a1549a and a1546a );
a1554a <=( (not A167) and (not A169) );
a1555a <=( (not A170) and a1554a );
a1558a <=( A201 and A200 );
a1561a <=( A300 and A298 );
a1562a <=( a1561a and a1558a );
a1565a <=( A200 and A199 );
a1568a <=( (not A203) and A202 );
a1569a <=( a1568a and a1565a );
a1572a <=( A233 and A232 );
a1575a <=( (not A236) and A235 );
a1576a <=( a1575a and a1572a );
a1579a <=( A200 and A199 );
a1582a <=( (not A203) and A202 );
a1583a <=( a1582a and a1579a );
a1586a <=( A233 and (not A232) );
a1589a <=( A236 and (not A235) );
a1590a <=( a1589a and a1586a );
a1593a <=( A200 and A199 );
a1596a <=( (not A203) and A202 );
a1597a <=( a1596a and a1593a );
a1600a <=( (not A233) and A232 );
a1603a <=( A236 and (not A235) );
a1604a <=( a1603a and a1600a );
a1607a <=( A200 and A199 );
a1610a <=( (not A203) and A202 );
a1611a <=( a1610a and a1607a );
a1614a <=( (not A233) and (not A232) );
a1617a <=( (not A236) and A235 );
a1618a <=( a1617a and a1614a );
a1621a <=( A200 and (not A199) );
a1624a <=( A203 and (not A202) );
a1625a <=( a1624a and a1621a );
a1628a <=( A233 and A232 );
a1631a <=( (not A236) and A235 );
a1632a <=( a1631a and a1628a );
a1635a <=( A200 and (not A199) );
a1638a <=( A203 and (not A202) );
a1639a <=( a1638a and a1635a );
a1642a <=( A233 and (not A232) );
a1645a <=( A236 and (not A235) );
a1646a <=( a1645a and a1642a );
a1649a <=( A200 and (not A199) );
a1652a <=( A203 and (not A202) );
a1653a <=( a1652a and a1649a );
a1656a <=( (not A233) and A232 );
a1659a <=( A236 and (not A235) );
a1660a <=( a1659a and a1656a );
a1663a <=( A200 and (not A199) );
a1666a <=( A203 and (not A202) );
a1667a <=( a1666a and a1663a );
a1670a <=( (not A233) and (not A232) );
a1673a <=( (not A236) and A235 );
a1674a <=( a1673a and a1670a );
a1677a <=( (not A200) and A199 );
a1680a <=( A203 and (not A202) );
a1681a <=( a1680a and a1677a );
a1684a <=( A233 and A232 );
a1687a <=( (not A236) and A235 );
a1688a <=( a1687a and a1684a );
a1691a <=( (not A200) and A199 );
a1694a <=( A203 and (not A202) );
a1695a <=( a1694a and a1691a );
a1698a <=( A233 and (not A232) );
a1701a <=( A236 and (not A235) );
a1702a <=( a1701a and a1698a );
a1705a <=( (not A200) and A199 );
a1708a <=( A203 and (not A202) );
a1709a <=( a1708a and a1705a );
a1712a <=( (not A233) and A232 );
a1715a <=( A236 and (not A235) );
a1716a <=( a1715a and a1712a );
a1719a <=( (not A200) and A199 );
a1722a <=( A203 and (not A202) );
a1723a <=( a1722a and a1719a );
a1726a <=( (not A233) and (not A232) );
a1729a <=( (not A236) and A235 );
a1730a <=( a1729a and a1726a );
a1733a <=( (not A200) and (not A199) );
a1736a <=( (not A203) and A202 );
a1737a <=( a1736a and a1733a );
a1740a <=( A233 and A232 );
a1743a <=( (not A236) and A235 );
a1744a <=( a1743a and a1740a );
a1747a <=( (not A200) and (not A199) );
a1750a <=( (not A203) and A202 );
a1751a <=( a1750a and a1747a );
a1754a <=( A233 and (not A232) );
a1757a <=( A236 and (not A235) );
a1758a <=( a1757a and a1754a );
a1761a <=( (not A200) and (not A199) );
a1764a <=( (not A203) and A202 );
a1765a <=( a1764a and a1761a );
a1768a <=( (not A233) and A232 );
a1771a <=( A236 and (not A235) );
a1772a <=( a1771a and a1768a );
a1775a <=( (not A200) and (not A199) );
a1778a <=( (not A203) and A202 );
a1779a <=( a1778a and a1775a );
a1782a <=( (not A233) and (not A232) );
a1785a <=( (not A236) and A235 );
a1786a <=( a1785a and a1782a );
a1789a <=( A166 and A167 );
a1792a <=( A201 and A199 );
a1793a <=( a1792a and a1789a );
a1796a <=( A299 and A298 );
a1799a <=( (not A302) and A301 );
a1800a <=( a1799a and a1796a );
a1803a <=( A166 and A167 );
a1806a <=( A201 and A199 );
a1807a <=( a1806a and a1803a );
a1810a <=( (not A299) and A298 );
a1813a <=( A302 and (not A301) );
a1814a <=( a1813a and a1810a );
a1817a <=( A166 and A167 );
a1820a <=( A201 and A199 );
a1821a <=( a1820a and a1817a );
a1824a <=( A299 and (not A298) );
a1827a <=( A302 and (not A301) );
a1828a <=( a1827a and a1824a );
a1831a <=( A166 and A167 );
a1834a <=( A201 and A199 );
a1835a <=( a1834a and a1831a );
a1838a <=( (not A299) and (not A298) );
a1841a <=( (not A302) and A301 );
a1842a <=( a1841a and a1838a );
a1845a <=( A166 and A167 );
a1848a <=( A201 and A200 );
a1849a <=( a1848a and a1845a );
a1852a <=( A299 and A298 );
a1855a <=( (not A302) and A301 );
a1856a <=( a1855a and a1852a );
a1859a <=( A166 and A167 );
a1862a <=( A201 and A200 );
a1863a <=( a1862a and a1859a );
a1866a <=( (not A299) and A298 );
a1869a <=( A302 and (not A301) );
a1870a <=( a1869a and a1866a );
a1873a <=( A166 and A167 );
a1876a <=( A201 and A200 );
a1877a <=( a1876a and a1873a );
a1880a <=( A299 and (not A298) );
a1883a <=( A302 and (not A301) );
a1884a <=( a1883a and a1880a );
a1887a <=( A166 and A167 );
a1890a <=( A201 and A200 );
a1891a <=( a1890a and a1887a );
a1894a <=( (not A299) and (not A298) );
a1897a <=( (not A302) and A301 );
a1898a <=( a1897a and a1894a );
a1901a <=( A166 and A167 );
a1904a <=( A200 and A199 );
a1905a <=( a1904a and a1901a );
a1908a <=( (not A203) and A202 );
a1911a <=( A300 and A299 );
a1912a <=( a1911a and a1908a );
a1915a <=( A166 and A167 );
a1918a <=( A200 and A199 );
a1919a <=( a1918a and a1915a );
a1922a <=( (not A203) and A202 );
a1925a <=( A300 and A298 );
a1926a <=( a1925a and a1922a );
a1929a <=( A166 and A167 );
a1932a <=( A200 and (not A199) );
a1933a <=( a1932a and a1929a );
a1936a <=( A203 and (not A202) );
a1939a <=( A300 and A299 );
a1940a <=( a1939a and a1936a );
a1943a <=( A166 and A167 );
a1946a <=( A200 and (not A199) );
a1947a <=( a1946a and a1943a );
a1950a <=( A203 and (not A202) );
a1953a <=( A300 and A298 );
a1954a <=( a1953a and a1950a );
a1957a <=( A166 and A167 );
a1960a <=( (not A200) and A199 );
a1961a <=( a1960a and a1957a );
a1964a <=( A203 and (not A202) );
a1967a <=( A300 and A299 );
a1968a <=( a1967a and a1964a );
a1971a <=( A166 and A167 );
a1974a <=( (not A200) and A199 );
a1975a <=( a1974a and a1971a );
a1978a <=( A203 and (not A202) );
a1981a <=( A300 and A298 );
a1982a <=( a1981a and a1978a );
a1985a <=( A166 and A167 );
a1988a <=( (not A200) and (not A199) );
a1989a <=( a1988a and a1985a );
a1992a <=( (not A203) and A202 );
a1995a <=( A300 and A299 );
a1996a <=( a1995a and a1992a );
a1999a <=( A166 and A167 );
a2002a <=( (not A200) and (not A199) );
a2003a <=( a2002a and a1999a );
a2006a <=( (not A203) and A202 );
a2009a <=( A300 and A298 );
a2010a <=( a2009a and a2006a );
a2013a <=( (not A166) and A167 );
a2016a <=( A200 and A199 );
a2017a <=( a2016a and a2013a );
a2020a <=( (not A202) and (not A201) );
a2023a <=( A300 and A299 );
a2024a <=( a2023a and a2020a );
a2027a <=( (not A166) and A167 );
a2030a <=( A200 and A199 );
a2031a <=( a2030a and a2027a );
a2034a <=( (not A202) and (not A201) );
a2037a <=( A300 and A298 );
a2038a <=( a2037a and a2034a );
a2041a <=( (not A166) and A167 );
a2044a <=( A200 and A199 );
a2045a <=( a2044a and a2041a );
a2048a <=( A203 and (not A201) );
a2051a <=( A300 and A299 );
a2052a <=( a2051a and a2048a );
a2055a <=( (not A166) and A167 );
a2058a <=( A200 and A199 );
a2059a <=( a2058a and a2055a );
a2062a <=( A203 and (not A201) );
a2065a <=( A300 and A298 );
a2066a <=( a2065a and a2062a );
a2069a <=( (not A166) and A167 );
a2072a <=( A200 and (not A199) );
a2073a <=( a2072a and a2069a );
a2076a <=( A202 and (not A201) );
a2079a <=( A300 and A299 );
a2080a <=( a2079a and a2076a );
a2083a <=( (not A166) and A167 );
a2086a <=( A200 and (not A199) );
a2087a <=( a2086a and a2083a );
a2090a <=( A202 and (not A201) );
a2093a <=( A300 and A298 );
a2094a <=( a2093a and a2090a );
a2097a <=( (not A166) and A167 );
a2100a <=( A200 and (not A199) );
a2101a <=( a2100a and a2097a );
a2104a <=( (not A203) and (not A201) );
a2107a <=( A300 and A299 );
a2108a <=( a2107a and a2104a );
a2111a <=( (not A166) and A167 );
a2114a <=( A200 and (not A199) );
a2115a <=( a2114a and a2111a );
a2118a <=( (not A203) and (not A201) );
a2121a <=( A300 and A298 );
a2122a <=( a2121a and a2118a );
a2125a <=( (not A166) and A167 );
a2128a <=( (not A200) and A199 );
a2129a <=( a2128a and a2125a );
a2132a <=( A202 and (not A201) );
a2135a <=( A300 and A299 );
a2136a <=( a2135a and a2132a );
a2139a <=( (not A166) and A167 );
a2142a <=( (not A200) and A199 );
a2143a <=( a2142a and a2139a );
a2146a <=( A202 and (not A201) );
a2149a <=( A300 and A298 );
a2150a <=( a2149a and a2146a );
a2153a <=( (not A166) and A167 );
a2156a <=( (not A200) and A199 );
a2157a <=( a2156a and a2153a );
a2160a <=( (not A203) and (not A201) );
a2163a <=( A300 and A299 );
a2164a <=( a2163a and a2160a );
a2167a <=( (not A166) and A167 );
a2170a <=( (not A200) and A199 );
a2171a <=( a2170a and a2167a );
a2174a <=( (not A203) and (not A201) );
a2177a <=( A300 and A298 );
a2178a <=( a2177a and a2174a );
a2181a <=( (not A166) and (not A167) );
a2184a <=( A201 and A199 );
a2185a <=( a2184a and a2181a );
a2188a <=( A299 and A298 );
a2191a <=( (not A302) and A301 );
a2192a <=( a2191a and a2188a );
a2195a <=( (not A166) and (not A167) );
a2198a <=( A201 and A199 );
a2199a <=( a2198a and a2195a );
a2202a <=( (not A299) and A298 );
a2205a <=( A302 and (not A301) );
a2206a <=( a2205a and a2202a );
a2209a <=( (not A166) and (not A167) );
a2212a <=( A201 and A199 );
a2213a <=( a2212a and a2209a );
a2216a <=( A299 and (not A298) );
a2219a <=( A302 and (not A301) );
a2220a <=( a2219a and a2216a );
a2223a <=( (not A166) and (not A167) );
a2226a <=( A201 and A199 );
a2227a <=( a2226a and a2223a );
a2230a <=( (not A299) and (not A298) );
a2233a <=( (not A302) and A301 );
a2234a <=( a2233a and a2230a );
a2237a <=( (not A166) and (not A167) );
a2240a <=( A201 and A200 );
a2241a <=( a2240a and a2237a );
a2244a <=( A299 and A298 );
a2247a <=( (not A302) and A301 );
a2248a <=( a2247a and a2244a );
a2251a <=( (not A166) and (not A167) );
a2254a <=( A201 and A200 );
a2255a <=( a2254a and a2251a );
a2258a <=( (not A299) and A298 );
a2261a <=( A302 and (not A301) );
a2262a <=( a2261a and a2258a );
a2265a <=( (not A166) and (not A167) );
a2268a <=( A201 and A200 );
a2269a <=( a2268a and a2265a );
a2272a <=( A299 and (not A298) );
a2275a <=( A302 and (not A301) );
a2276a <=( a2275a and a2272a );
a2279a <=( (not A166) and (not A167) );
a2282a <=( A201 and A200 );
a2283a <=( a2282a and a2279a );
a2286a <=( (not A299) and (not A298) );
a2289a <=( (not A302) and A301 );
a2290a <=( a2289a and a2286a );
a2293a <=( (not A166) and (not A167) );
a2296a <=( A200 and A199 );
a2297a <=( a2296a and a2293a );
a2300a <=( (not A203) and A202 );
a2303a <=( A300 and A299 );
a2304a <=( a2303a and a2300a );
a2307a <=( (not A166) and (not A167) );
a2310a <=( A200 and A199 );
a2311a <=( a2310a and a2307a );
a2314a <=( (not A203) and A202 );
a2317a <=( A300 and A298 );
a2318a <=( a2317a and a2314a );
a2321a <=( (not A166) and (not A167) );
a2324a <=( A200 and (not A199) );
a2325a <=( a2324a and a2321a );
a2328a <=( A203 and (not A202) );
a2331a <=( A300 and A299 );
a2332a <=( a2331a and a2328a );
a2335a <=( (not A166) and (not A167) );
a2338a <=( A200 and (not A199) );
a2339a <=( a2338a and a2335a );
a2342a <=( A203 and (not A202) );
a2345a <=( A300 and A298 );
a2346a <=( a2345a and a2342a );
a2349a <=( (not A166) and (not A167) );
a2352a <=( (not A200) and A199 );
a2353a <=( a2352a and a2349a );
a2356a <=( A203 and (not A202) );
a2359a <=( A300 and A299 );
a2360a <=( a2359a and a2356a );
a2363a <=( (not A166) and (not A167) );
a2366a <=( (not A200) and A199 );
a2367a <=( a2366a and a2363a );
a2370a <=( A203 and (not A202) );
a2373a <=( A300 and A298 );
a2374a <=( a2373a and a2370a );
a2377a <=( (not A166) and (not A167) );
a2380a <=( (not A200) and (not A199) );
a2381a <=( a2380a and a2377a );
a2384a <=( (not A203) and A202 );
a2387a <=( A300 and A299 );
a2388a <=( a2387a and a2384a );
a2391a <=( (not A166) and (not A167) );
a2394a <=( (not A200) and (not A199) );
a2395a <=( a2394a and a2391a );
a2398a <=( (not A203) and A202 );
a2401a <=( A300 and A298 );
a2402a <=( a2401a and a2398a );
a2405a <=( (not A167) and (not A168) );
a2408a <=( A201 and A199 );
a2409a <=( a2408a and a2405a );
a2412a <=( A299 and A298 );
a2415a <=( (not A302) and A301 );
a2416a <=( a2415a and a2412a );
a2419a <=( (not A167) and (not A168) );
a2422a <=( A201 and A199 );
a2423a <=( a2422a and a2419a );
a2426a <=( (not A299) and A298 );
a2429a <=( A302 and (not A301) );
a2430a <=( a2429a and a2426a );
a2433a <=( (not A167) and (not A168) );
a2436a <=( A201 and A199 );
a2437a <=( a2436a and a2433a );
a2440a <=( A299 and (not A298) );
a2443a <=( A302 and (not A301) );
a2444a <=( a2443a and a2440a );
a2447a <=( (not A167) and (not A168) );
a2450a <=( A201 and A199 );
a2451a <=( a2450a and a2447a );
a2454a <=( (not A299) and (not A298) );
a2457a <=( (not A302) and A301 );
a2458a <=( a2457a and a2454a );
a2461a <=( (not A167) and (not A168) );
a2464a <=( A201 and A200 );
a2465a <=( a2464a and a2461a );
a2468a <=( A299 and A298 );
a2471a <=( (not A302) and A301 );
a2472a <=( a2471a and a2468a );
a2475a <=( (not A167) and (not A168) );
a2478a <=( A201 and A200 );
a2479a <=( a2478a and a2475a );
a2482a <=( (not A299) and A298 );
a2485a <=( A302 and (not A301) );
a2486a <=( a2485a and a2482a );
a2489a <=( (not A167) and (not A168) );
a2492a <=( A201 and A200 );
a2493a <=( a2492a and a2489a );
a2496a <=( A299 and (not A298) );
a2499a <=( A302 and (not A301) );
a2500a <=( a2499a and a2496a );
a2503a <=( (not A167) and (not A168) );
a2506a <=( A201 and A200 );
a2507a <=( a2506a and a2503a );
a2510a <=( (not A299) and (not A298) );
a2513a <=( (not A302) and A301 );
a2514a <=( a2513a and a2510a );
a2517a <=( (not A167) and (not A168) );
a2520a <=( A200 and A199 );
a2521a <=( a2520a and a2517a );
a2524a <=( (not A203) and A202 );
a2527a <=( A300 and A299 );
a2528a <=( a2527a and a2524a );
a2531a <=( (not A167) and (not A168) );
a2534a <=( A200 and A199 );
a2535a <=( a2534a and a2531a );
a2538a <=( (not A203) and A202 );
a2541a <=( A300 and A298 );
a2542a <=( a2541a and a2538a );
a2545a <=( (not A167) and (not A168) );
a2548a <=( A200 and (not A199) );
a2549a <=( a2548a and a2545a );
a2552a <=( A203 and (not A202) );
a2555a <=( A300 and A299 );
a2556a <=( a2555a and a2552a );
a2559a <=( (not A167) and (not A168) );
a2562a <=( A200 and (not A199) );
a2563a <=( a2562a and a2559a );
a2566a <=( A203 and (not A202) );
a2569a <=( A300 and A298 );
a2570a <=( a2569a and a2566a );
a2573a <=( (not A167) and (not A168) );
a2576a <=( (not A200) and A199 );
a2577a <=( a2576a and a2573a );
a2580a <=( A203 and (not A202) );
a2583a <=( A300 and A299 );
a2584a <=( a2583a and a2580a );
a2587a <=( (not A167) and (not A168) );
a2590a <=( (not A200) and A199 );
a2591a <=( a2590a and a2587a );
a2594a <=( A203 and (not A202) );
a2597a <=( A300 and A298 );
a2598a <=( a2597a and a2594a );
a2601a <=( (not A167) and (not A168) );
a2604a <=( (not A200) and (not A199) );
a2605a <=( a2604a and a2601a );
a2608a <=( (not A203) and A202 );
a2611a <=( A300 and A299 );
a2612a <=( a2611a and a2608a );
a2615a <=( (not A167) and (not A168) );
a2618a <=( (not A200) and (not A199) );
a2619a <=( a2618a and a2615a );
a2622a <=( (not A203) and A202 );
a2625a <=( A300 and A298 );
a2626a <=( a2625a and a2622a );
a2629a <=( A168 and A170 );
a2632a <=( A166 and (not A167) );
a2633a <=( a2632a and a2629a );
a2636a <=( A233 and A232 );
a2639a <=( (not A236) and A235 );
a2640a <=( a2639a and a2636a );
a2643a <=( A168 and A170 );
a2646a <=( A166 and (not A167) );
a2647a <=( a2646a and a2643a );
a2650a <=( A233 and (not A232) );
a2653a <=( A236 and (not A235) );
a2654a <=( a2653a and a2650a );
a2657a <=( A168 and A170 );
a2660a <=( A166 and (not A167) );
a2661a <=( a2660a and a2657a );
a2664a <=( (not A233) and A232 );
a2667a <=( A236 and (not A235) );
a2668a <=( a2667a and a2664a );
a2671a <=( A168 and A170 );
a2674a <=( A166 and (not A167) );
a2675a <=( a2674a and a2671a );
a2678a <=( (not A233) and (not A232) );
a2681a <=( (not A236) and A235 );
a2682a <=( a2681a and a2678a );
a2685a <=( A168 and A169 );
a2688a <=( A166 and (not A167) );
a2689a <=( a2688a and a2685a );
a2692a <=( A233 and A232 );
a2695a <=( (not A236) and A235 );
a2696a <=( a2695a and a2692a );
a2699a <=( A168 and A169 );
a2702a <=( A166 and (not A167) );
a2703a <=( a2702a and a2699a );
a2706a <=( A233 and (not A232) );
a2709a <=( A236 and (not A235) );
a2710a <=( a2709a and a2706a );
a2713a <=( A168 and A169 );
a2716a <=( A166 and (not A167) );
a2717a <=( a2716a and a2713a );
a2720a <=( (not A233) and A232 );
a2723a <=( A236 and (not A235) );
a2724a <=( a2723a and a2720a );
a2727a <=( A168 and A169 );
a2730a <=( A166 and (not A167) );
a2731a <=( a2730a and a2727a );
a2734a <=( (not A233) and (not A232) );
a2737a <=( (not A236) and A235 );
a2738a <=( a2737a and a2734a );
a2741a <=( (not A166) and A167 );
a2744a <=( (not A200) and (not A199) );
a2745a <=( a2744a and a2741a );
a2748a <=( A298 and (not A202) );
a2752a <=( (not A302) and A301 );
a2753a <=( A299 and a2752a );
a2754a <=( a2753a and a2748a );
a2757a <=( (not A166) and A167 );
a2760a <=( (not A200) and (not A199) );
a2761a <=( a2760a and a2757a );
a2764a <=( A298 and (not A202) );
a2768a <=( A302 and (not A301) );
a2769a <=( (not A299) and a2768a );
a2770a <=( a2769a and a2764a );
a2773a <=( (not A166) and A167 );
a2776a <=( (not A200) and (not A199) );
a2777a <=( a2776a and a2773a );
a2780a <=( (not A298) and (not A202) );
a2784a <=( A302 and (not A301) );
a2785a <=( A299 and a2784a );
a2786a <=( a2785a and a2780a );
a2789a <=( (not A166) and A167 );
a2792a <=( (not A200) and (not A199) );
a2793a <=( a2792a and a2789a );
a2796a <=( (not A298) and (not A202) );
a2800a <=( (not A302) and A301 );
a2801a <=( (not A299) and a2800a );
a2802a <=( a2801a and a2796a );
a2805a <=( (not A166) and A167 );
a2808a <=( (not A200) and (not A199) );
a2809a <=( a2808a and a2805a );
a2812a <=( A298 and A203 );
a2816a <=( (not A302) and A301 );
a2817a <=( A299 and a2816a );
a2818a <=( a2817a and a2812a );
a2821a <=( (not A166) and A167 );
a2824a <=( (not A200) and (not A199) );
a2825a <=( a2824a and a2821a );
a2828a <=( A298 and A203 );
a2832a <=( A302 and (not A301) );
a2833a <=( (not A299) and a2832a );
a2834a <=( a2833a and a2828a );
a2837a <=( (not A166) and A167 );
a2840a <=( (not A200) and (not A199) );
a2841a <=( a2840a and a2837a );
a2844a <=( (not A298) and A203 );
a2848a <=( A302 and (not A301) );
a2849a <=( A299 and a2848a );
a2850a <=( a2849a and a2844a );
a2853a <=( (not A166) and A167 );
a2856a <=( (not A200) and (not A199) );
a2857a <=( a2856a and a2853a );
a2860a <=( (not A298) and A203 );
a2864a <=( (not A302) and A301 );
a2865a <=( (not A299) and a2864a );
a2866a <=( a2865a and a2860a );
a2869a <=( A168 and A170 );
a2872a <=( A166 and (not A167) );
a2873a <=( a2872a and a2869a );
a2876a <=( (not A200) and (not A199) );
a2880a <=( A300 and A299 );
a2881a <=( (not A202) and a2880a );
a2882a <=( a2881a and a2876a );
a2885a <=( A168 and A170 );
a2888a <=( A166 and (not A167) );
a2889a <=( a2888a and a2885a );
a2892a <=( (not A200) and (not A199) );
a2896a <=( A300 and A298 );
a2897a <=( (not A202) and a2896a );
a2898a <=( a2897a and a2892a );
a2901a <=( A168 and A170 );
a2904a <=( A166 and (not A167) );
a2905a <=( a2904a and a2901a );
a2908a <=( (not A200) and (not A199) );
a2912a <=( A300 and A299 );
a2913a <=( A203 and a2912a );
a2914a <=( a2913a and a2908a );
a2917a <=( A168 and A170 );
a2920a <=( A166 and (not A167) );
a2921a <=( a2920a and a2917a );
a2924a <=( (not A200) and (not A199) );
a2928a <=( A300 and A298 );
a2929a <=( A203 and a2928a );
a2930a <=( a2929a and a2924a );
a2933a <=( A168 and A169 );
a2936a <=( A166 and (not A167) );
a2937a <=( a2936a and a2933a );
a2940a <=( (not A200) and (not A199) );
a2944a <=( A300 and A299 );
a2945a <=( (not A202) and a2944a );
a2946a <=( a2945a and a2940a );
a2949a <=( A168 and A169 );
a2952a <=( A166 and (not A167) );
a2953a <=( a2952a and a2949a );
a2956a <=( (not A200) and (not A199) );
a2960a <=( A300 and A298 );
a2961a <=( (not A202) and a2960a );
a2962a <=( a2961a and a2956a );
a2965a <=( A168 and A169 );
a2968a <=( A166 and (not A167) );
a2969a <=( a2968a and a2965a );
a2972a <=( (not A200) and (not A199) );
a2976a <=( A300 and A299 );
a2977a <=( A203 and a2976a );
a2978a <=( a2977a and a2972a );
a2981a <=( A168 and A169 );
a2984a <=( A166 and (not A167) );
a2985a <=( a2984a and a2981a );
a2988a <=( (not A200) and (not A199) );
a2992a <=( A300 and A298 );
a2993a <=( A203 and a2992a );
a2994a <=( a2993a and a2988a );
a2997a <=( (not A169) and (not A170) );
a3000a <=( A199 and (not A167) );
a3001a <=( a3000a and a2997a );
a3004a <=( A298 and A201 );
a3008a <=( (not A302) and A301 );
a3009a <=( A299 and a3008a );
a3010a <=( a3009a and a3004a );
a3013a <=( (not A169) and (not A170) );
a3016a <=( A199 and (not A167) );
a3017a <=( a3016a and a3013a );
a3020a <=( A298 and A201 );
a3024a <=( A302 and (not A301) );
a3025a <=( (not A299) and a3024a );
a3026a <=( a3025a and a3020a );
a3029a <=( (not A169) and (not A170) );
a3032a <=( A199 and (not A167) );
a3033a <=( a3032a and a3029a );
a3036a <=( (not A298) and A201 );
a3040a <=( A302 and (not A301) );
a3041a <=( A299 and a3040a );
a3042a <=( a3041a and a3036a );
a3045a <=( (not A169) and (not A170) );
a3048a <=( A199 and (not A167) );
a3049a <=( a3048a and a3045a );
a3052a <=( (not A298) and A201 );
a3056a <=( (not A302) and A301 );
a3057a <=( (not A299) and a3056a );
a3058a <=( a3057a and a3052a );
a3061a <=( (not A169) and (not A170) );
a3064a <=( A200 and (not A167) );
a3065a <=( a3064a and a3061a );
a3068a <=( A298 and A201 );
a3072a <=( (not A302) and A301 );
a3073a <=( A299 and a3072a );
a3074a <=( a3073a and a3068a );
a3077a <=( (not A169) and (not A170) );
a3080a <=( A200 and (not A167) );
a3081a <=( a3080a and a3077a );
a3084a <=( A298 and A201 );
a3088a <=( A302 and (not A301) );
a3089a <=( (not A299) and a3088a );
a3090a <=( a3089a and a3084a );
a3093a <=( (not A169) and (not A170) );
a3096a <=( A200 and (not A167) );
a3097a <=( a3096a and a3093a );
a3100a <=( (not A298) and A201 );
a3104a <=( A302 and (not A301) );
a3105a <=( A299 and a3104a );
a3106a <=( a3105a and a3100a );
a3109a <=( (not A169) and (not A170) );
a3112a <=( A200 and (not A167) );
a3113a <=( a3112a and a3109a );
a3116a <=( (not A298) and A201 );
a3120a <=( (not A302) and A301 );
a3121a <=( (not A299) and a3120a );
a3122a <=( a3121a and a3116a );
a3125a <=( (not A169) and (not A170) );
a3128a <=( A199 and (not A167) );
a3129a <=( a3128a and a3125a );
a3132a <=( A202 and A200 );
a3136a <=( A300 and A299 );
a3137a <=( (not A203) and a3136a );
a3138a <=( a3137a and a3132a );
a3141a <=( (not A169) and (not A170) );
a3144a <=( A199 and (not A167) );
a3145a <=( a3144a and a3141a );
a3148a <=( A202 and A200 );
a3152a <=( A300 and A298 );
a3153a <=( (not A203) and a3152a );
a3154a <=( a3153a and a3148a );
a3157a <=( (not A169) and (not A170) );
a3160a <=( (not A199) and (not A167) );
a3161a <=( a3160a and a3157a );
a3164a <=( (not A202) and A200 );
a3168a <=( A300 and A299 );
a3169a <=( A203 and a3168a );
a3170a <=( a3169a and a3164a );
a3173a <=( (not A169) and (not A170) );
a3176a <=( (not A199) and (not A167) );
a3177a <=( a3176a and a3173a );
a3180a <=( (not A202) and A200 );
a3184a <=( A300 and A298 );
a3185a <=( A203 and a3184a );
a3186a <=( a3185a and a3180a );
a3189a <=( (not A169) and (not A170) );
a3192a <=( A199 and (not A167) );
a3193a <=( a3192a and a3189a );
a3196a <=( (not A202) and (not A200) );
a3200a <=( A300 and A299 );
a3201a <=( A203 and a3200a );
a3202a <=( a3201a and a3196a );
a3205a <=( (not A169) and (not A170) );
a3208a <=( A199 and (not A167) );
a3209a <=( a3208a and a3205a );
a3212a <=( (not A202) and (not A200) );
a3216a <=( A300 and A298 );
a3217a <=( A203 and a3216a );
a3218a <=( a3217a and a3212a );
a3221a <=( (not A169) and (not A170) );
a3224a <=( (not A199) and (not A167) );
a3225a <=( a3224a and a3221a );
a3228a <=( A202 and (not A200) );
a3232a <=( A300 and A299 );
a3233a <=( (not A203) and a3232a );
a3234a <=( a3233a and a3228a );
a3237a <=( (not A169) and (not A170) );
a3240a <=( (not A199) and (not A167) );
a3241a <=( a3240a and a3237a );
a3244a <=( A202 and (not A200) );
a3248a <=( A300 and A298 );
a3249a <=( (not A203) and a3248a );
a3250a <=( a3249a and a3244a );
a3253a <=( A166 and A167 );
a3257a <=( A202 and A200 );
a3258a <=( A199 and a3257a );
a3259a <=( a3258a and a3253a );
a3262a <=( A298 and (not A203) );
a3266a <=( (not A302) and A301 );
a3267a <=( A299 and a3266a );
a3268a <=( a3267a and a3262a );
a3271a <=( A166 and A167 );
a3275a <=( A202 and A200 );
a3276a <=( A199 and a3275a );
a3277a <=( a3276a and a3271a );
a3280a <=( A298 and (not A203) );
a3284a <=( A302 and (not A301) );
a3285a <=( (not A299) and a3284a );
a3286a <=( a3285a and a3280a );
a3289a <=( A166 and A167 );
a3293a <=( A202 and A200 );
a3294a <=( A199 and a3293a );
a3295a <=( a3294a and a3289a );
a3298a <=( (not A298) and (not A203) );
a3302a <=( A302 and (not A301) );
a3303a <=( A299 and a3302a );
a3304a <=( a3303a and a3298a );
a3307a <=( A166 and A167 );
a3311a <=( A202 and A200 );
a3312a <=( A199 and a3311a );
a3313a <=( a3312a and a3307a );
a3316a <=( (not A298) and (not A203) );
a3320a <=( (not A302) and A301 );
a3321a <=( (not A299) and a3320a );
a3322a <=( a3321a and a3316a );
a3325a <=( A166 and A167 );
a3329a <=( (not A202) and A200 );
a3330a <=( (not A199) and a3329a );
a3331a <=( a3330a and a3325a );
a3334a <=( A298 and A203 );
a3338a <=( (not A302) and A301 );
a3339a <=( A299 and a3338a );
a3340a <=( a3339a and a3334a );
a3343a <=( A166 and A167 );
a3347a <=( (not A202) and A200 );
a3348a <=( (not A199) and a3347a );
a3349a <=( a3348a and a3343a );
a3352a <=( A298 and A203 );
a3356a <=( A302 and (not A301) );
a3357a <=( (not A299) and a3356a );
a3358a <=( a3357a and a3352a );
a3361a <=( A166 and A167 );
a3365a <=( (not A202) and A200 );
a3366a <=( (not A199) and a3365a );
a3367a <=( a3366a and a3361a );
a3370a <=( (not A298) and A203 );
a3374a <=( A302 and (not A301) );
a3375a <=( A299 and a3374a );
a3376a <=( a3375a and a3370a );
a3379a <=( A166 and A167 );
a3383a <=( (not A202) and A200 );
a3384a <=( (not A199) and a3383a );
a3385a <=( a3384a and a3379a );
a3388a <=( (not A298) and A203 );
a3392a <=( (not A302) and A301 );
a3393a <=( (not A299) and a3392a );
a3394a <=( a3393a and a3388a );
a3397a <=( A166 and A167 );
a3401a <=( (not A202) and (not A200) );
a3402a <=( A199 and a3401a );
a3403a <=( a3402a and a3397a );
a3406a <=( A298 and A203 );
a3410a <=( (not A302) and A301 );
a3411a <=( A299 and a3410a );
a3412a <=( a3411a and a3406a );
a3415a <=( A166 and A167 );
a3419a <=( (not A202) and (not A200) );
a3420a <=( A199 and a3419a );
a3421a <=( a3420a and a3415a );
a3424a <=( A298 and A203 );
a3428a <=( A302 and (not A301) );
a3429a <=( (not A299) and a3428a );
a3430a <=( a3429a and a3424a );
a3433a <=( A166 and A167 );
a3437a <=( (not A202) and (not A200) );
a3438a <=( A199 and a3437a );
a3439a <=( a3438a and a3433a );
a3442a <=( (not A298) and A203 );
a3446a <=( A302 and (not A301) );
a3447a <=( A299 and a3446a );
a3448a <=( a3447a and a3442a );
a3451a <=( A166 and A167 );
a3455a <=( (not A202) and (not A200) );
a3456a <=( A199 and a3455a );
a3457a <=( a3456a and a3451a );
a3460a <=( (not A298) and A203 );
a3464a <=( (not A302) and A301 );
a3465a <=( (not A299) and a3464a );
a3466a <=( a3465a and a3460a );
a3469a <=( A166 and A167 );
a3473a <=( A202 and (not A200) );
a3474a <=( (not A199) and a3473a );
a3475a <=( a3474a and a3469a );
a3478a <=( A298 and (not A203) );
a3482a <=( (not A302) and A301 );
a3483a <=( A299 and a3482a );
a3484a <=( a3483a and a3478a );
a3487a <=( A166 and A167 );
a3491a <=( A202 and (not A200) );
a3492a <=( (not A199) and a3491a );
a3493a <=( a3492a and a3487a );
a3496a <=( A298 and (not A203) );
a3500a <=( A302 and (not A301) );
a3501a <=( (not A299) and a3500a );
a3502a <=( a3501a and a3496a );
a3505a <=( A166 and A167 );
a3509a <=( A202 and (not A200) );
a3510a <=( (not A199) and a3509a );
a3511a <=( a3510a and a3505a );
a3514a <=( (not A298) and (not A203) );
a3518a <=( A302 and (not A301) );
a3519a <=( A299 and a3518a );
a3520a <=( a3519a and a3514a );
a3523a <=( A166 and A167 );
a3527a <=( A202 and (not A200) );
a3528a <=( (not A199) and a3527a );
a3529a <=( a3528a and a3523a );
a3532a <=( (not A298) and (not A203) );
a3536a <=( (not A302) and A301 );
a3537a <=( (not A299) and a3536a );
a3538a <=( a3537a and a3532a );
a3541a <=( (not A166) and A167 );
a3545a <=( (not A201) and A200 );
a3546a <=( A199 and a3545a );
a3547a <=( a3546a and a3541a );
a3550a <=( A298 and (not A202) );
a3554a <=( (not A302) and A301 );
a3555a <=( A299 and a3554a );
a3556a <=( a3555a and a3550a );
a3559a <=( (not A166) and A167 );
a3563a <=( (not A201) and A200 );
a3564a <=( A199 and a3563a );
a3565a <=( a3564a and a3559a );
a3568a <=( A298 and (not A202) );
a3572a <=( A302 and (not A301) );
a3573a <=( (not A299) and a3572a );
a3574a <=( a3573a and a3568a );
a3577a <=( (not A166) and A167 );
a3581a <=( (not A201) and A200 );
a3582a <=( A199 and a3581a );
a3583a <=( a3582a and a3577a );
a3586a <=( (not A298) and (not A202) );
a3590a <=( A302 and (not A301) );
a3591a <=( A299 and a3590a );
a3592a <=( a3591a and a3586a );
a3595a <=( (not A166) and A167 );
a3599a <=( (not A201) and A200 );
a3600a <=( A199 and a3599a );
a3601a <=( a3600a and a3595a );
a3604a <=( (not A298) and (not A202) );
a3608a <=( (not A302) and A301 );
a3609a <=( (not A299) and a3608a );
a3610a <=( a3609a and a3604a );
a3613a <=( (not A166) and A167 );
a3617a <=( (not A201) and A200 );
a3618a <=( A199 and a3617a );
a3619a <=( a3618a and a3613a );
a3622a <=( A298 and A203 );
a3626a <=( (not A302) and A301 );
a3627a <=( A299 and a3626a );
a3628a <=( a3627a and a3622a );
a3631a <=( (not A166) and A167 );
a3635a <=( (not A201) and A200 );
a3636a <=( A199 and a3635a );
a3637a <=( a3636a and a3631a );
a3640a <=( A298 and A203 );
a3644a <=( A302 and (not A301) );
a3645a <=( (not A299) and a3644a );
a3646a <=( a3645a and a3640a );
a3649a <=( (not A166) and A167 );
a3653a <=( (not A201) and A200 );
a3654a <=( A199 and a3653a );
a3655a <=( a3654a and a3649a );
a3658a <=( (not A298) and A203 );
a3662a <=( A302 and (not A301) );
a3663a <=( A299 and a3662a );
a3664a <=( a3663a and a3658a );
a3667a <=( (not A166) and A167 );
a3671a <=( (not A201) and A200 );
a3672a <=( A199 and a3671a );
a3673a <=( a3672a and a3667a );
a3676a <=( (not A298) and A203 );
a3680a <=( (not A302) and A301 );
a3681a <=( (not A299) and a3680a );
a3682a <=( a3681a and a3676a );
a3685a <=( (not A166) and A167 );
a3689a <=( (not A201) and A200 );
a3690a <=( (not A199) and a3689a );
a3691a <=( a3690a and a3685a );
a3694a <=( A298 and A202 );
a3698a <=( (not A302) and A301 );
a3699a <=( A299 and a3698a );
a3700a <=( a3699a and a3694a );
a3703a <=( (not A166) and A167 );
a3707a <=( (not A201) and A200 );
a3708a <=( (not A199) and a3707a );
a3709a <=( a3708a and a3703a );
a3712a <=( A298 and A202 );
a3716a <=( A302 and (not A301) );
a3717a <=( (not A299) and a3716a );
a3718a <=( a3717a and a3712a );
a3721a <=( (not A166) and A167 );
a3725a <=( (not A201) and A200 );
a3726a <=( (not A199) and a3725a );
a3727a <=( a3726a and a3721a );
a3730a <=( (not A298) and A202 );
a3734a <=( A302 and (not A301) );
a3735a <=( A299 and a3734a );
a3736a <=( a3735a and a3730a );
a3739a <=( (not A166) and A167 );
a3743a <=( (not A201) and A200 );
a3744a <=( (not A199) and a3743a );
a3745a <=( a3744a and a3739a );
a3748a <=( (not A298) and A202 );
a3752a <=( (not A302) and A301 );
a3753a <=( (not A299) and a3752a );
a3754a <=( a3753a and a3748a );
a3757a <=( (not A166) and A167 );
a3761a <=( (not A201) and A200 );
a3762a <=( (not A199) and a3761a );
a3763a <=( a3762a and a3757a );
a3766a <=( A298 and (not A203) );
a3770a <=( (not A302) and A301 );
a3771a <=( A299 and a3770a );
a3772a <=( a3771a and a3766a );
a3775a <=( (not A166) and A167 );
a3779a <=( (not A201) and A200 );
a3780a <=( (not A199) and a3779a );
a3781a <=( a3780a and a3775a );
a3784a <=( A298 and (not A203) );
a3788a <=( A302 and (not A301) );
a3789a <=( (not A299) and a3788a );
a3790a <=( a3789a and a3784a );
a3793a <=( (not A166) and A167 );
a3797a <=( (not A201) and A200 );
a3798a <=( (not A199) and a3797a );
a3799a <=( a3798a and a3793a );
a3802a <=( (not A298) and (not A203) );
a3806a <=( A302 and (not A301) );
a3807a <=( A299 and a3806a );
a3808a <=( a3807a and a3802a );
a3811a <=( (not A166) and A167 );
a3815a <=( (not A201) and A200 );
a3816a <=( (not A199) and a3815a );
a3817a <=( a3816a and a3811a );
a3820a <=( (not A298) and (not A203) );
a3824a <=( (not A302) and A301 );
a3825a <=( (not A299) and a3824a );
a3826a <=( a3825a and a3820a );
a3829a <=( (not A166) and A167 );
a3833a <=( (not A201) and (not A200) );
a3834a <=( A199 and a3833a );
a3835a <=( a3834a and a3829a );
a3838a <=( A298 and A202 );
a3842a <=( (not A302) and A301 );
a3843a <=( A299 and a3842a );
a3844a <=( a3843a and a3838a );
a3847a <=( (not A166) and A167 );
a3851a <=( (not A201) and (not A200) );
a3852a <=( A199 and a3851a );
a3853a <=( a3852a and a3847a );
a3856a <=( A298 and A202 );
a3860a <=( A302 and (not A301) );
a3861a <=( (not A299) and a3860a );
a3862a <=( a3861a and a3856a );
a3865a <=( (not A166) and A167 );
a3869a <=( (not A201) and (not A200) );
a3870a <=( A199 and a3869a );
a3871a <=( a3870a and a3865a );
a3874a <=( (not A298) and A202 );
a3878a <=( A302 and (not A301) );
a3879a <=( A299 and a3878a );
a3880a <=( a3879a and a3874a );
a3883a <=( (not A166) and A167 );
a3887a <=( (not A201) and (not A200) );
a3888a <=( A199 and a3887a );
a3889a <=( a3888a and a3883a );
a3892a <=( (not A298) and A202 );
a3896a <=( (not A302) and A301 );
a3897a <=( (not A299) and a3896a );
a3898a <=( a3897a and a3892a );
a3901a <=( (not A166) and A167 );
a3905a <=( (not A201) and (not A200) );
a3906a <=( A199 and a3905a );
a3907a <=( a3906a and a3901a );
a3910a <=( A298 and (not A203) );
a3914a <=( (not A302) and A301 );
a3915a <=( A299 and a3914a );
a3916a <=( a3915a and a3910a );
a3919a <=( (not A166) and A167 );
a3923a <=( (not A201) and (not A200) );
a3924a <=( A199 and a3923a );
a3925a <=( a3924a and a3919a );
a3928a <=( A298 and (not A203) );
a3932a <=( A302 and (not A301) );
a3933a <=( (not A299) and a3932a );
a3934a <=( a3933a and a3928a );
a3937a <=( (not A166) and A167 );
a3941a <=( (not A201) and (not A200) );
a3942a <=( A199 and a3941a );
a3943a <=( a3942a and a3937a );
a3946a <=( (not A298) and (not A203) );
a3950a <=( A302 and (not A301) );
a3951a <=( A299 and a3950a );
a3952a <=( a3951a and a3946a );
a3955a <=( (not A166) and A167 );
a3959a <=( (not A201) and (not A200) );
a3960a <=( A199 and a3959a );
a3961a <=( a3960a and a3955a );
a3964a <=( (not A298) and (not A203) );
a3968a <=( (not A302) and A301 );
a3969a <=( (not A299) and a3968a );
a3970a <=( a3969a and a3964a );
a3973a <=( (not A166) and (not A167) );
a3977a <=( A202 and A200 );
a3978a <=( A199 and a3977a );
a3979a <=( a3978a and a3973a );
a3982a <=( A298 and (not A203) );
a3986a <=( (not A302) and A301 );
a3987a <=( A299 and a3986a );
a3988a <=( a3987a and a3982a );
a3991a <=( (not A166) and (not A167) );
a3995a <=( A202 and A200 );
a3996a <=( A199 and a3995a );
a3997a <=( a3996a and a3991a );
a4000a <=( A298 and (not A203) );
a4004a <=( A302 and (not A301) );
a4005a <=( (not A299) and a4004a );
a4006a <=( a4005a and a4000a );
a4009a <=( (not A166) and (not A167) );
a4013a <=( A202 and A200 );
a4014a <=( A199 and a4013a );
a4015a <=( a4014a and a4009a );
a4018a <=( (not A298) and (not A203) );
a4022a <=( A302 and (not A301) );
a4023a <=( A299 and a4022a );
a4024a <=( a4023a and a4018a );
a4027a <=( (not A166) and (not A167) );
a4031a <=( A202 and A200 );
a4032a <=( A199 and a4031a );
a4033a <=( a4032a and a4027a );
a4036a <=( (not A298) and (not A203) );
a4040a <=( (not A302) and A301 );
a4041a <=( (not A299) and a4040a );
a4042a <=( a4041a and a4036a );
a4045a <=( (not A166) and (not A167) );
a4049a <=( (not A202) and A200 );
a4050a <=( (not A199) and a4049a );
a4051a <=( a4050a and a4045a );
a4054a <=( A298 and A203 );
a4058a <=( (not A302) and A301 );
a4059a <=( A299 and a4058a );
a4060a <=( a4059a and a4054a );
a4063a <=( (not A166) and (not A167) );
a4067a <=( (not A202) and A200 );
a4068a <=( (not A199) and a4067a );
a4069a <=( a4068a and a4063a );
a4072a <=( A298 and A203 );
a4076a <=( A302 and (not A301) );
a4077a <=( (not A299) and a4076a );
a4078a <=( a4077a and a4072a );
a4081a <=( (not A166) and (not A167) );
a4085a <=( (not A202) and A200 );
a4086a <=( (not A199) and a4085a );
a4087a <=( a4086a and a4081a );
a4090a <=( (not A298) and A203 );
a4094a <=( A302 and (not A301) );
a4095a <=( A299 and a4094a );
a4096a <=( a4095a and a4090a );
a4099a <=( (not A166) and (not A167) );
a4103a <=( (not A202) and A200 );
a4104a <=( (not A199) and a4103a );
a4105a <=( a4104a and a4099a );
a4108a <=( (not A298) and A203 );
a4112a <=( (not A302) and A301 );
a4113a <=( (not A299) and a4112a );
a4114a <=( a4113a and a4108a );
a4117a <=( (not A166) and (not A167) );
a4121a <=( (not A202) and (not A200) );
a4122a <=( A199 and a4121a );
a4123a <=( a4122a and a4117a );
a4126a <=( A298 and A203 );
a4130a <=( (not A302) and A301 );
a4131a <=( A299 and a4130a );
a4132a <=( a4131a and a4126a );
a4135a <=( (not A166) and (not A167) );
a4139a <=( (not A202) and (not A200) );
a4140a <=( A199 and a4139a );
a4141a <=( a4140a and a4135a );
a4144a <=( A298 and A203 );
a4148a <=( A302 and (not A301) );
a4149a <=( (not A299) and a4148a );
a4150a <=( a4149a and a4144a );
a4153a <=( (not A166) and (not A167) );
a4157a <=( (not A202) and (not A200) );
a4158a <=( A199 and a4157a );
a4159a <=( a4158a and a4153a );
a4162a <=( (not A298) and A203 );
a4166a <=( A302 and (not A301) );
a4167a <=( A299 and a4166a );
a4168a <=( a4167a and a4162a );
a4171a <=( (not A166) and (not A167) );
a4175a <=( (not A202) and (not A200) );
a4176a <=( A199 and a4175a );
a4177a <=( a4176a and a4171a );
a4180a <=( (not A298) and A203 );
a4184a <=( (not A302) and A301 );
a4185a <=( (not A299) and a4184a );
a4186a <=( a4185a and a4180a );
a4189a <=( (not A166) and (not A167) );
a4193a <=( A202 and (not A200) );
a4194a <=( (not A199) and a4193a );
a4195a <=( a4194a and a4189a );
a4198a <=( A298 and (not A203) );
a4202a <=( (not A302) and A301 );
a4203a <=( A299 and a4202a );
a4204a <=( a4203a and a4198a );
a4207a <=( (not A166) and (not A167) );
a4211a <=( A202 and (not A200) );
a4212a <=( (not A199) and a4211a );
a4213a <=( a4212a and a4207a );
a4216a <=( A298 and (not A203) );
a4220a <=( A302 and (not A301) );
a4221a <=( (not A299) and a4220a );
a4222a <=( a4221a and a4216a );
a4225a <=( (not A166) and (not A167) );
a4229a <=( A202 and (not A200) );
a4230a <=( (not A199) and a4229a );
a4231a <=( a4230a and a4225a );
a4234a <=( (not A298) and (not A203) );
a4238a <=( A302 and (not A301) );
a4239a <=( A299 and a4238a );
a4240a <=( a4239a and a4234a );
a4243a <=( (not A166) and (not A167) );
a4247a <=( A202 and (not A200) );
a4248a <=( (not A199) and a4247a );
a4249a <=( a4248a and a4243a );
a4252a <=( (not A298) and (not A203) );
a4256a <=( (not A302) and A301 );
a4257a <=( (not A299) and a4256a );
a4258a <=( a4257a and a4252a );
a4261a <=( (not A167) and (not A168) );
a4265a <=( A202 and A200 );
a4266a <=( A199 and a4265a );
a4267a <=( a4266a and a4261a );
a4270a <=( A298 and (not A203) );
a4274a <=( (not A302) and A301 );
a4275a <=( A299 and a4274a );
a4276a <=( a4275a and a4270a );
a4279a <=( (not A167) and (not A168) );
a4283a <=( A202 and A200 );
a4284a <=( A199 and a4283a );
a4285a <=( a4284a and a4279a );
a4288a <=( A298 and (not A203) );
a4292a <=( A302 and (not A301) );
a4293a <=( (not A299) and a4292a );
a4294a <=( a4293a and a4288a );
a4297a <=( (not A167) and (not A168) );
a4301a <=( A202 and A200 );
a4302a <=( A199 and a4301a );
a4303a <=( a4302a and a4297a );
a4306a <=( (not A298) and (not A203) );
a4310a <=( A302 and (not A301) );
a4311a <=( A299 and a4310a );
a4312a <=( a4311a and a4306a );
a4315a <=( (not A167) and (not A168) );
a4319a <=( A202 and A200 );
a4320a <=( A199 and a4319a );
a4321a <=( a4320a and a4315a );
a4324a <=( (not A298) and (not A203) );
a4328a <=( (not A302) and A301 );
a4329a <=( (not A299) and a4328a );
a4330a <=( a4329a and a4324a );
a4333a <=( (not A167) and (not A168) );
a4337a <=( (not A202) and A200 );
a4338a <=( (not A199) and a4337a );
a4339a <=( a4338a and a4333a );
a4342a <=( A298 and A203 );
a4346a <=( (not A302) and A301 );
a4347a <=( A299 and a4346a );
a4348a <=( a4347a and a4342a );
a4351a <=( (not A167) and (not A168) );
a4355a <=( (not A202) and A200 );
a4356a <=( (not A199) and a4355a );
a4357a <=( a4356a and a4351a );
a4360a <=( A298 and A203 );
a4364a <=( A302 and (not A301) );
a4365a <=( (not A299) and a4364a );
a4366a <=( a4365a and a4360a );
a4369a <=( (not A167) and (not A168) );
a4373a <=( (not A202) and A200 );
a4374a <=( (not A199) and a4373a );
a4375a <=( a4374a and a4369a );
a4378a <=( (not A298) and A203 );
a4382a <=( A302 and (not A301) );
a4383a <=( A299 and a4382a );
a4384a <=( a4383a and a4378a );
a4387a <=( (not A167) and (not A168) );
a4391a <=( (not A202) and A200 );
a4392a <=( (not A199) and a4391a );
a4393a <=( a4392a and a4387a );
a4396a <=( (not A298) and A203 );
a4400a <=( (not A302) and A301 );
a4401a <=( (not A299) and a4400a );
a4402a <=( a4401a and a4396a );
a4405a <=( (not A167) and (not A168) );
a4409a <=( (not A202) and (not A200) );
a4410a <=( A199 and a4409a );
a4411a <=( a4410a and a4405a );
a4414a <=( A298 and A203 );
a4418a <=( (not A302) and A301 );
a4419a <=( A299 and a4418a );
a4420a <=( a4419a and a4414a );
a4423a <=( (not A167) and (not A168) );
a4427a <=( (not A202) and (not A200) );
a4428a <=( A199 and a4427a );
a4429a <=( a4428a and a4423a );
a4432a <=( A298 and A203 );
a4436a <=( A302 and (not A301) );
a4437a <=( (not A299) and a4436a );
a4438a <=( a4437a and a4432a );
a4441a <=( (not A167) and (not A168) );
a4445a <=( (not A202) and (not A200) );
a4446a <=( A199 and a4445a );
a4447a <=( a4446a and a4441a );
a4450a <=( (not A298) and A203 );
a4454a <=( A302 and (not A301) );
a4455a <=( A299 and a4454a );
a4456a <=( a4455a and a4450a );
a4459a <=( (not A167) and (not A168) );
a4463a <=( (not A202) and (not A200) );
a4464a <=( A199 and a4463a );
a4465a <=( a4464a and a4459a );
a4468a <=( (not A298) and A203 );
a4472a <=( (not A302) and A301 );
a4473a <=( (not A299) and a4472a );
a4474a <=( a4473a and a4468a );
a4477a <=( (not A167) and (not A168) );
a4481a <=( A202 and (not A200) );
a4482a <=( (not A199) and a4481a );
a4483a <=( a4482a and a4477a );
a4486a <=( A298 and (not A203) );
a4490a <=( (not A302) and A301 );
a4491a <=( A299 and a4490a );
a4492a <=( a4491a and a4486a );
a4495a <=( (not A167) and (not A168) );
a4499a <=( A202 and (not A200) );
a4500a <=( (not A199) and a4499a );
a4501a <=( a4500a and a4495a );
a4504a <=( A298 and (not A203) );
a4508a <=( A302 and (not A301) );
a4509a <=( (not A299) and a4508a );
a4510a <=( a4509a and a4504a );
a4513a <=( (not A167) and (not A168) );
a4517a <=( A202 and (not A200) );
a4518a <=( (not A199) and a4517a );
a4519a <=( a4518a and a4513a );
a4522a <=( (not A298) and (not A203) );
a4526a <=( A302 and (not A301) );
a4527a <=( A299 and a4526a );
a4528a <=( a4527a and a4522a );
a4531a <=( (not A167) and (not A168) );
a4535a <=( A202 and (not A200) );
a4536a <=( (not A199) and a4535a );
a4537a <=( a4536a and a4531a );
a4540a <=( (not A298) and (not A203) );
a4544a <=( (not A302) and A301 );
a4545a <=( (not A299) and a4544a );
a4546a <=( a4545a and a4540a );
a4549a <=( A168 and A170 );
a4553a <=( A199 and A166 );
a4554a <=( (not A167) and a4553a );
a4555a <=( a4554a and a4549a );
a4558a <=( (not A201) and A200 );
a4562a <=( A300 and A299 );
a4563a <=( (not A202) and a4562a );
a4564a <=( a4563a and a4558a );
a4567a <=( A168 and A170 );
a4571a <=( A199 and A166 );
a4572a <=( (not A167) and a4571a );
a4573a <=( a4572a and a4567a );
a4576a <=( (not A201) and A200 );
a4580a <=( A300 and A298 );
a4581a <=( (not A202) and a4580a );
a4582a <=( a4581a and a4576a );
a4585a <=( A168 and A170 );
a4589a <=( A199 and A166 );
a4590a <=( (not A167) and a4589a );
a4591a <=( a4590a and a4585a );
a4594a <=( (not A201) and A200 );
a4598a <=( A300 and A299 );
a4599a <=( A203 and a4598a );
a4600a <=( a4599a and a4594a );
a4603a <=( A168 and A170 );
a4607a <=( A199 and A166 );
a4608a <=( (not A167) and a4607a );
a4609a <=( a4608a and a4603a );
a4612a <=( (not A201) and A200 );
a4616a <=( A300 and A298 );
a4617a <=( A203 and a4616a );
a4618a <=( a4617a and a4612a );
a4621a <=( A168 and A170 );
a4625a <=( (not A199) and A166 );
a4626a <=( (not A167) and a4625a );
a4627a <=( a4626a and a4621a );
a4630a <=( (not A201) and A200 );
a4634a <=( A300 and A299 );
a4635a <=( A202 and a4634a );
a4636a <=( a4635a and a4630a );
a4639a <=( A168 and A170 );
a4643a <=( (not A199) and A166 );
a4644a <=( (not A167) and a4643a );
a4645a <=( a4644a and a4639a );
a4648a <=( (not A201) and A200 );
a4652a <=( A300 and A298 );
a4653a <=( A202 and a4652a );
a4654a <=( a4653a and a4648a );
a4657a <=( A168 and A170 );
a4661a <=( (not A199) and A166 );
a4662a <=( (not A167) and a4661a );
a4663a <=( a4662a and a4657a );
a4666a <=( (not A201) and A200 );
a4670a <=( A300 and A299 );
a4671a <=( (not A203) and a4670a );
a4672a <=( a4671a and a4666a );
a4675a <=( A168 and A170 );
a4679a <=( (not A199) and A166 );
a4680a <=( (not A167) and a4679a );
a4681a <=( a4680a and a4675a );
a4684a <=( (not A201) and A200 );
a4688a <=( A300 and A298 );
a4689a <=( (not A203) and a4688a );
a4690a <=( a4689a and a4684a );
a4693a <=( A168 and A170 );
a4697a <=( A199 and A166 );
a4698a <=( (not A167) and a4697a );
a4699a <=( a4698a and a4693a );
a4702a <=( (not A201) and (not A200) );
a4706a <=( A300 and A299 );
a4707a <=( A202 and a4706a );
a4708a <=( a4707a and a4702a );
a4711a <=( A168 and A170 );
a4715a <=( A199 and A166 );
a4716a <=( (not A167) and a4715a );
a4717a <=( a4716a and a4711a );
a4720a <=( (not A201) and (not A200) );
a4724a <=( A300 and A298 );
a4725a <=( A202 and a4724a );
a4726a <=( a4725a and a4720a );
a4729a <=( A168 and A170 );
a4733a <=( A199 and A166 );
a4734a <=( (not A167) and a4733a );
a4735a <=( a4734a and a4729a );
a4738a <=( (not A201) and (not A200) );
a4742a <=( A300 and A299 );
a4743a <=( (not A203) and a4742a );
a4744a <=( a4743a and a4738a );
a4747a <=( A168 and A170 );
a4751a <=( A199 and A166 );
a4752a <=( (not A167) and a4751a );
a4753a <=( a4752a and a4747a );
a4756a <=( (not A201) and (not A200) );
a4760a <=( A300 and A298 );
a4761a <=( (not A203) and a4760a );
a4762a <=( a4761a and a4756a );
a4765a <=( A168 and A169 );
a4769a <=( A199 and A166 );
a4770a <=( (not A167) and a4769a );
a4771a <=( a4770a and a4765a );
a4774a <=( (not A201) and A200 );
a4778a <=( A300 and A299 );
a4779a <=( (not A202) and a4778a );
a4780a <=( a4779a and a4774a );
a4783a <=( A168 and A169 );
a4787a <=( A199 and A166 );
a4788a <=( (not A167) and a4787a );
a4789a <=( a4788a and a4783a );
a4792a <=( (not A201) and A200 );
a4796a <=( A300 and A298 );
a4797a <=( (not A202) and a4796a );
a4798a <=( a4797a and a4792a );
a4801a <=( A168 and A169 );
a4805a <=( A199 and A166 );
a4806a <=( (not A167) and a4805a );
a4807a <=( a4806a and a4801a );
a4810a <=( (not A201) and A200 );
a4814a <=( A300 and A299 );
a4815a <=( A203 and a4814a );
a4816a <=( a4815a and a4810a );
a4819a <=( A168 and A169 );
a4823a <=( A199 and A166 );
a4824a <=( (not A167) and a4823a );
a4825a <=( a4824a and a4819a );
a4828a <=( (not A201) and A200 );
a4832a <=( A300 and A298 );
a4833a <=( A203 and a4832a );
a4834a <=( a4833a and a4828a );
a4837a <=( A168 and A169 );
a4841a <=( (not A199) and A166 );
a4842a <=( (not A167) and a4841a );
a4843a <=( a4842a and a4837a );
a4846a <=( (not A201) and A200 );
a4850a <=( A300 and A299 );
a4851a <=( A202 and a4850a );
a4852a <=( a4851a and a4846a );
a4855a <=( A168 and A169 );
a4859a <=( (not A199) and A166 );
a4860a <=( (not A167) and a4859a );
a4861a <=( a4860a and a4855a );
a4864a <=( (not A201) and A200 );
a4868a <=( A300 and A298 );
a4869a <=( A202 and a4868a );
a4870a <=( a4869a and a4864a );
a4873a <=( A168 and A169 );
a4877a <=( (not A199) and A166 );
a4878a <=( (not A167) and a4877a );
a4879a <=( a4878a and a4873a );
a4882a <=( (not A201) and A200 );
a4886a <=( A300 and A299 );
a4887a <=( (not A203) and a4886a );
a4888a <=( a4887a and a4882a );
a4891a <=( A168 and A169 );
a4895a <=( (not A199) and A166 );
a4896a <=( (not A167) and a4895a );
a4897a <=( a4896a and a4891a );
a4900a <=( (not A201) and A200 );
a4904a <=( A300 and A298 );
a4905a <=( (not A203) and a4904a );
a4906a <=( a4905a and a4900a );
a4909a <=( A168 and A169 );
a4913a <=( A199 and A166 );
a4914a <=( (not A167) and a4913a );
a4915a <=( a4914a and a4909a );
a4918a <=( (not A201) and (not A200) );
a4922a <=( A300 and A299 );
a4923a <=( A202 and a4922a );
a4924a <=( a4923a and a4918a );
a4927a <=( A168 and A169 );
a4931a <=( A199 and A166 );
a4932a <=( (not A167) and a4931a );
a4933a <=( a4932a and a4927a );
a4936a <=( (not A201) and (not A200) );
a4940a <=( A300 and A298 );
a4941a <=( A202 and a4940a );
a4942a <=( a4941a and a4936a );
a4945a <=( A168 and A169 );
a4949a <=( A199 and A166 );
a4950a <=( (not A167) and a4949a );
a4951a <=( a4950a and a4945a );
a4954a <=( (not A201) and (not A200) );
a4958a <=( A300 and A299 );
a4959a <=( (not A203) and a4958a );
a4960a <=( a4959a and a4954a );
a4963a <=( A168 and A169 );
a4967a <=( A199 and A166 );
a4968a <=( (not A167) and a4967a );
a4969a <=( a4968a and a4963a );
a4972a <=( (not A201) and (not A200) );
a4976a <=( A300 and A298 );
a4977a <=( (not A203) and a4976a );
a4978a <=( a4977a and a4972a );
a4981a <=( A168 and A170 );
a4985a <=( (not A199) and A166 );
a4986a <=( (not A167) and a4985a );
a4987a <=( a4986a and a4981a );
a4991a <=( A298 and (not A202) );
a4992a <=( (not A200) and a4991a );
a4996a <=( (not A302) and A301 );
a4997a <=( A299 and a4996a );
a4998a <=( a4997a and a4992a );
a5001a <=( A168 and A170 );
a5005a <=( (not A199) and A166 );
a5006a <=( (not A167) and a5005a );
a5007a <=( a5006a and a5001a );
a5011a <=( A298 and (not A202) );
a5012a <=( (not A200) and a5011a );
a5016a <=( A302 and (not A301) );
a5017a <=( (not A299) and a5016a );
a5018a <=( a5017a and a5012a );
a5021a <=( A168 and A170 );
a5025a <=( (not A199) and A166 );
a5026a <=( (not A167) and a5025a );
a5027a <=( a5026a and a5021a );
a5031a <=( (not A298) and (not A202) );
a5032a <=( (not A200) and a5031a );
a5036a <=( A302 and (not A301) );
a5037a <=( A299 and a5036a );
a5038a <=( a5037a and a5032a );
a5041a <=( A168 and A170 );
a5045a <=( (not A199) and A166 );
a5046a <=( (not A167) and a5045a );
a5047a <=( a5046a and a5041a );
a5051a <=( (not A298) and (not A202) );
a5052a <=( (not A200) and a5051a );
a5056a <=( (not A302) and A301 );
a5057a <=( (not A299) and a5056a );
a5058a <=( a5057a and a5052a );
a5061a <=( A168 and A170 );
a5065a <=( (not A199) and A166 );
a5066a <=( (not A167) and a5065a );
a5067a <=( a5066a and a5061a );
a5071a <=( A298 and A203 );
a5072a <=( (not A200) and a5071a );
a5076a <=( (not A302) and A301 );
a5077a <=( A299 and a5076a );
a5078a <=( a5077a and a5072a );
a5081a <=( A168 and A170 );
a5085a <=( (not A199) and A166 );
a5086a <=( (not A167) and a5085a );
a5087a <=( a5086a and a5081a );
a5091a <=( A298 and A203 );
a5092a <=( (not A200) and a5091a );
a5096a <=( A302 and (not A301) );
a5097a <=( (not A299) and a5096a );
a5098a <=( a5097a and a5092a );
a5101a <=( A168 and A170 );
a5105a <=( (not A199) and A166 );
a5106a <=( (not A167) and a5105a );
a5107a <=( a5106a and a5101a );
a5111a <=( (not A298) and A203 );
a5112a <=( (not A200) and a5111a );
a5116a <=( A302 and (not A301) );
a5117a <=( A299 and a5116a );
a5118a <=( a5117a and a5112a );
a5121a <=( A168 and A170 );
a5125a <=( (not A199) and A166 );
a5126a <=( (not A167) and a5125a );
a5127a <=( a5126a and a5121a );
a5131a <=( (not A298) and A203 );
a5132a <=( (not A200) and a5131a );
a5136a <=( (not A302) and A301 );
a5137a <=( (not A299) and a5136a );
a5138a <=( a5137a and a5132a );
a5141a <=( A168 and A169 );
a5145a <=( (not A199) and A166 );
a5146a <=( (not A167) and a5145a );
a5147a <=( a5146a and a5141a );
a5151a <=( A298 and (not A202) );
a5152a <=( (not A200) and a5151a );
a5156a <=( (not A302) and A301 );
a5157a <=( A299 and a5156a );
a5158a <=( a5157a and a5152a );
a5161a <=( A168 and A169 );
a5165a <=( (not A199) and A166 );
a5166a <=( (not A167) and a5165a );
a5167a <=( a5166a and a5161a );
a5171a <=( A298 and (not A202) );
a5172a <=( (not A200) and a5171a );
a5176a <=( A302 and (not A301) );
a5177a <=( (not A299) and a5176a );
a5178a <=( a5177a and a5172a );
a5181a <=( A168 and A169 );
a5185a <=( (not A199) and A166 );
a5186a <=( (not A167) and a5185a );
a5187a <=( a5186a and a5181a );
a5191a <=( (not A298) and (not A202) );
a5192a <=( (not A200) and a5191a );
a5196a <=( A302 and (not A301) );
a5197a <=( A299 and a5196a );
a5198a <=( a5197a and a5192a );
a5201a <=( A168 and A169 );
a5205a <=( (not A199) and A166 );
a5206a <=( (not A167) and a5205a );
a5207a <=( a5206a and a5201a );
a5211a <=( (not A298) and (not A202) );
a5212a <=( (not A200) and a5211a );
a5216a <=( (not A302) and A301 );
a5217a <=( (not A299) and a5216a );
a5218a <=( a5217a and a5212a );
a5221a <=( A168 and A169 );
a5225a <=( (not A199) and A166 );
a5226a <=( (not A167) and a5225a );
a5227a <=( a5226a and a5221a );
a5231a <=( A298 and A203 );
a5232a <=( (not A200) and a5231a );
a5236a <=( (not A302) and A301 );
a5237a <=( A299 and a5236a );
a5238a <=( a5237a and a5232a );
a5241a <=( A168 and A169 );
a5245a <=( (not A199) and A166 );
a5246a <=( (not A167) and a5245a );
a5247a <=( a5246a and a5241a );
a5251a <=( A298 and A203 );
a5252a <=( (not A200) and a5251a );
a5256a <=( A302 and (not A301) );
a5257a <=( (not A299) and a5256a );
a5258a <=( a5257a and a5252a );
a5261a <=( A168 and A169 );
a5265a <=( (not A199) and A166 );
a5266a <=( (not A167) and a5265a );
a5267a <=( a5266a and a5261a );
a5271a <=( (not A298) and A203 );
a5272a <=( (not A200) and a5271a );
a5276a <=( A302 and (not A301) );
a5277a <=( A299 and a5276a );
a5278a <=( a5277a and a5272a );
a5281a <=( A168 and A169 );
a5285a <=( (not A199) and A166 );
a5286a <=( (not A167) and a5285a );
a5287a <=( a5286a and a5281a );
a5291a <=( (not A298) and A203 );
a5292a <=( (not A200) and a5291a );
a5296a <=( (not A302) and A301 );
a5297a <=( (not A299) and a5296a );
a5298a <=( a5297a and a5292a );
a5301a <=( (not A169) and (not A170) );
a5305a <=( A200 and A199 );
a5306a <=( (not A167) and a5305a );
a5307a <=( a5306a and a5301a );
a5311a <=( A298 and (not A203) );
a5312a <=( A202 and a5311a );
a5316a <=( (not A302) and A301 );
a5317a <=( A299 and a5316a );
a5318a <=( a5317a and a5312a );
a5321a <=( (not A169) and (not A170) );
a5325a <=( A200 and A199 );
a5326a <=( (not A167) and a5325a );
a5327a <=( a5326a and a5321a );
a5331a <=( A298 and (not A203) );
a5332a <=( A202 and a5331a );
a5336a <=( A302 and (not A301) );
a5337a <=( (not A299) and a5336a );
a5338a <=( a5337a and a5332a );
a5341a <=( (not A169) and (not A170) );
a5345a <=( A200 and A199 );
a5346a <=( (not A167) and a5345a );
a5347a <=( a5346a and a5341a );
a5351a <=( (not A298) and (not A203) );
a5352a <=( A202 and a5351a );
a5356a <=( A302 and (not A301) );
a5357a <=( A299 and a5356a );
a5358a <=( a5357a and a5352a );
a5361a <=( (not A169) and (not A170) );
a5365a <=( A200 and A199 );
a5366a <=( (not A167) and a5365a );
a5367a <=( a5366a and a5361a );
a5371a <=( (not A298) and (not A203) );
a5372a <=( A202 and a5371a );
a5376a <=( (not A302) and A301 );
a5377a <=( (not A299) and a5376a );
a5378a <=( a5377a and a5372a );
a5381a <=( (not A169) and (not A170) );
a5385a <=( A200 and (not A199) );
a5386a <=( (not A167) and a5385a );
a5387a <=( a5386a and a5381a );
a5391a <=( A298 and A203 );
a5392a <=( (not A202) and a5391a );
a5396a <=( (not A302) and A301 );
a5397a <=( A299 and a5396a );
a5398a <=( a5397a and a5392a );
a5401a <=( (not A169) and (not A170) );
a5405a <=( A200 and (not A199) );
a5406a <=( (not A167) and a5405a );
a5407a <=( a5406a and a5401a );
a5411a <=( A298 and A203 );
a5412a <=( (not A202) and a5411a );
a5416a <=( A302 and (not A301) );
a5417a <=( (not A299) and a5416a );
a5418a <=( a5417a and a5412a );
a5421a <=( (not A169) and (not A170) );
a5425a <=( A200 and (not A199) );
a5426a <=( (not A167) and a5425a );
a5427a <=( a5426a and a5421a );
a5431a <=( (not A298) and A203 );
a5432a <=( (not A202) and a5431a );
a5436a <=( A302 and (not A301) );
a5437a <=( A299 and a5436a );
a5438a <=( a5437a and a5432a );
a5441a <=( (not A169) and (not A170) );
a5445a <=( A200 and (not A199) );
a5446a <=( (not A167) and a5445a );
a5447a <=( a5446a and a5441a );
a5451a <=( (not A298) and A203 );
a5452a <=( (not A202) and a5451a );
a5456a <=( (not A302) and A301 );
a5457a <=( (not A299) and a5456a );
a5458a <=( a5457a and a5452a );
a5461a <=( (not A169) and (not A170) );
a5465a <=( (not A200) and A199 );
a5466a <=( (not A167) and a5465a );
a5467a <=( a5466a and a5461a );
a5471a <=( A298 and A203 );
a5472a <=( (not A202) and a5471a );
a5476a <=( (not A302) and A301 );
a5477a <=( A299 and a5476a );
a5478a <=( a5477a and a5472a );
a5481a <=( (not A169) and (not A170) );
a5485a <=( (not A200) and A199 );
a5486a <=( (not A167) and a5485a );
a5487a <=( a5486a and a5481a );
a5491a <=( A298 and A203 );
a5492a <=( (not A202) and a5491a );
a5496a <=( A302 and (not A301) );
a5497a <=( (not A299) and a5496a );
a5498a <=( a5497a and a5492a );
a5501a <=( (not A169) and (not A170) );
a5505a <=( (not A200) and A199 );
a5506a <=( (not A167) and a5505a );
a5507a <=( a5506a and a5501a );
a5511a <=( (not A298) and A203 );
a5512a <=( (not A202) and a5511a );
a5516a <=( A302 and (not A301) );
a5517a <=( A299 and a5516a );
a5518a <=( a5517a and a5512a );
a5521a <=( (not A169) and (not A170) );
a5525a <=( (not A200) and A199 );
a5526a <=( (not A167) and a5525a );
a5527a <=( a5526a and a5521a );
a5531a <=( (not A298) and A203 );
a5532a <=( (not A202) and a5531a );
a5536a <=( (not A302) and A301 );
a5537a <=( (not A299) and a5536a );
a5538a <=( a5537a and a5532a );
a5541a <=( (not A169) and (not A170) );
a5545a <=( (not A200) and (not A199) );
a5546a <=( (not A167) and a5545a );
a5547a <=( a5546a and a5541a );
a5551a <=( A298 and (not A203) );
a5552a <=( A202 and a5551a );
a5556a <=( (not A302) and A301 );
a5557a <=( A299 and a5556a );
a5558a <=( a5557a and a5552a );
a5561a <=( (not A169) and (not A170) );
a5565a <=( (not A200) and (not A199) );
a5566a <=( (not A167) and a5565a );
a5567a <=( a5566a and a5561a );
a5571a <=( A298 and (not A203) );
a5572a <=( A202 and a5571a );
a5576a <=( A302 and (not A301) );
a5577a <=( (not A299) and a5576a );
a5578a <=( a5577a and a5572a );
a5581a <=( (not A169) and (not A170) );
a5585a <=( (not A200) and (not A199) );
a5586a <=( (not A167) and a5585a );
a5587a <=( a5586a and a5581a );
a5591a <=( (not A298) and (not A203) );
a5592a <=( A202 and a5591a );
a5596a <=( A302 and (not A301) );
a5597a <=( A299 and a5596a );
a5598a <=( a5597a and a5592a );
a5601a <=( (not A169) and (not A170) );
a5605a <=( (not A200) and (not A199) );
a5606a <=( (not A167) and a5605a );
a5607a <=( a5606a and a5601a );
a5611a <=( (not A298) and (not A203) );
a5612a <=( A202 and a5611a );
a5616a <=( (not A302) and A301 );
a5617a <=( (not A299) and a5616a );
a5618a <=( a5617a and a5612a );
a5622a <=( (not A167) and A168 );
a5623a <=( A170 and a5622a );
a5627a <=( A200 and A199 );
a5628a <=( A166 and a5627a );
a5629a <=( a5628a and a5623a );
a5633a <=( A298 and (not A202) );
a5634a <=( (not A201) and a5633a );
a5638a <=( (not A302) and A301 );
a5639a <=( A299 and a5638a );
a5640a <=( a5639a and a5634a );
a5644a <=( (not A167) and A168 );
a5645a <=( A170 and a5644a );
a5649a <=( A200 and A199 );
a5650a <=( A166 and a5649a );
a5651a <=( a5650a and a5645a );
a5655a <=( A298 and (not A202) );
a5656a <=( (not A201) and a5655a );
a5660a <=( A302 and (not A301) );
a5661a <=( (not A299) and a5660a );
a5662a <=( a5661a and a5656a );
a5666a <=( (not A167) and A168 );
a5667a <=( A170 and a5666a );
a5671a <=( A200 and A199 );
a5672a <=( A166 and a5671a );
a5673a <=( a5672a and a5667a );
a5677a <=( (not A298) and (not A202) );
a5678a <=( (not A201) and a5677a );
a5682a <=( A302 and (not A301) );
a5683a <=( A299 and a5682a );
a5684a <=( a5683a and a5678a );
a5688a <=( (not A167) and A168 );
a5689a <=( A170 and a5688a );
a5693a <=( A200 and A199 );
a5694a <=( A166 and a5693a );
a5695a <=( a5694a and a5689a );
a5699a <=( (not A298) and (not A202) );
a5700a <=( (not A201) and a5699a );
a5704a <=( (not A302) and A301 );
a5705a <=( (not A299) and a5704a );
a5706a <=( a5705a and a5700a );
a5710a <=( (not A167) and A168 );
a5711a <=( A170 and a5710a );
a5715a <=( A200 and A199 );
a5716a <=( A166 and a5715a );
a5717a <=( a5716a and a5711a );
a5721a <=( A298 and A203 );
a5722a <=( (not A201) and a5721a );
a5726a <=( (not A302) and A301 );
a5727a <=( A299 and a5726a );
a5728a <=( a5727a and a5722a );
a5732a <=( (not A167) and A168 );
a5733a <=( A170 and a5732a );
a5737a <=( A200 and A199 );
a5738a <=( A166 and a5737a );
a5739a <=( a5738a and a5733a );
a5743a <=( A298 and A203 );
a5744a <=( (not A201) and a5743a );
a5748a <=( A302 and (not A301) );
a5749a <=( (not A299) and a5748a );
a5750a <=( a5749a and a5744a );
a5754a <=( (not A167) and A168 );
a5755a <=( A170 and a5754a );
a5759a <=( A200 and A199 );
a5760a <=( A166 and a5759a );
a5761a <=( a5760a and a5755a );
a5765a <=( (not A298) and A203 );
a5766a <=( (not A201) and a5765a );
a5770a <=( A302 and (not A301) );
a5771a <=( A299 and a5770a );
a5772a <=( a5771a and a5766a );
a5776a <=( (not A167) and A168 );
a5777a <=( A170 and a5776a );
a5781a <=( A200 and A199 );
a5782a <=( A166 and a5781a );
a5783a <=( a5782a and a5777a );
a5787a <=( (not A298) and A203 );
a5788a <=( (not A201) and a5787a );
a5792a <=( (not A302) and A301 );
a5793a <=( (not A299) and a5792a );
a5794a <=( a5793a and a5788a );
a5798a <=( (not A167) and A168 );
a5799a <=( A170 and a5798a );
a5803a <=( A200 and (not A199) );
a5804a <=( A166 and a5803a );
a5805a <=( a5804a and a5799a );
a5809a <=( A298 and A202 );
a5810a <=( (not A201) and a5809a );
a5814a <=( (not A302) and A301 );
a5815a <=( A299 and a5814a );
a5816a <=( a5815a and a5810a );
a5820a <=( (not A167) and A168 );
a5821a <=( A170 and a5820a );
a5825a <=( A200 and (not A199) );
a5826a <=( A166 and a5825a );
a5827a <=( a5826a and a5821a );
a5831a <=( A298 and A202 );
a5832a <=( (not A201) and a5831a );
a5836a <=( A302 and (not A301) );
a5837a <=( (not A299) and a5836a );
a5838a <=( a5837a and a5832a );
a5842a <=( (not A167) and A168 );
a5843a <=( A170 and a5842a );
a5847a <=( A200 and (not A199) );
a5848a <=( A166 and a5847a );
a5849a <=( a5848a and a5843a );
a5853a <=( (not A298) and A202 );
a5854a <=( (not A201) and a5853a );
a5858a <=( A302 and (not A301) );
a5859a <=( A299 and a5858a );
a5860a <=( a5859a and a5854a );
a5864a <=( (not A167) and A168 );
a5865a <=( A170 and a5864a );
a5869a <=( A200 and (not A199) );
a5870a <=( A166 and a5869a );
a5871a <=( a5870a and a5865a );
a5875a <=( (not A298) and A202 );
a5876a <=( (not A201) and a5875a );
a5880a <=( (not A302) and A301 );
a5881a <=( (not A299) and a5880a );
a5882a <=( a5881a and a5876a );
a5886a <=( (not A167) and A168 );
a5887a <=( A170 and a5886a );
a5891a <=( A200 and (not A199) );
a5892a <=( A166 and a5891a );
a5893a <=( a5892a and a5887a );
a5897a <=( A298 and (not A203) );
a5898a <=( (not A201) and a5897a );
a5902a <=( (not A302) and A301 );
a5903a <=( A299 and a5902a );
a5904a <=( a5903a and a5898a );
a5908a <=( (not A167) and A168 );
a5909a <=( A170 and a5908a );
a5913a <=( A200 and (not A199) );
a5914a <=( A166 and a5913a );
a5915a <=( a5914a and a5909a );
a5919a <=( A298 and (not A203) );
a5920a <=( (not A201) and a5919a );
a5924a <=( A302 and (not A301) );
a5925a <=( (not A299) and a5924a );
a5926a <=( a5925a and a5920a );
a5930a <=( (not A167) and A168 );
a5931a <=( A170 and a5930a );
a5935a <=( A200 and (not A199) );
a5936a <=( A166 and a5935a );
a5937a <=( a5936a and a5931a );
a5941a <=( (not A298) and (not A203) );
a5942a <=( (not A201) and a5941a );
a5946a <=( A302 and (not A301) );
a5947a <=( A299 and a5946a );
a5948a <=( a5947a and a5942a );
a5952a <=( (not A167) and A168 );
a5953a <=( A170 and a5952a );
a5957a <=( A200 and (not A199) );
a5958a <=( A166 and a5957a );
a5959a <=( a5958a and a5953a );
a5963a <=( (not A298) and (not A203) );
a5964a <=( (not A201) and a5963a );
a5968a <=( (not A302) and A301 );
a5969a <=( (not A299) and a5968a );
a5970a <=( a5969a and a5964a );
a5974a <=( (not A167) and A168 );
a5975a <=( A170 and a5974a );
a5979a <=( (not A200) and A199 );
a5980a <=( A166 and a5979a );
a5981a <=( a5980a and a5975a );
a5985a <=( A298 and A202 );
a5986a <=( (not A201) and a5985a );
a5990a <=( (not A302) and A301 );
a5991a <=( A299 and a5990a );
a5992a <=( a5991a and a5986a );
a5996a <=( (not A167) and A168 );
a5997a <=( A170 and a5996a );
a6001a <=( (not A200) and A199 );
a6002a <=( A166 and a6001a );
a6003a <=( a6002a and a5997a );
a6007a <=( A298 and A202 );
a6008a <=( (not A201) and a6007a );
a6012a <=( A302 and (not A301) );
a6013a <=( (not A299) and a6012a );
a6014a <=( a6013a and a6008a );
a6018a <=( (not A167) and A168 );
a6019a <=( A170 and a6018a );
a6023a <=( (not A200) and A199 );
a6024a <=( A166 and a6023a );
a6025a <=( a6024a and a6019a );
a6029a <=( (not A298) and A202 );
a6030a <=( (not A201) and a6029a );
a6034a <=( A302 and (not A301) );
a6035a <=( A299 and a6034a );
a6036a <=( a6035a and a6030a );
a6040a <=( (not A167) and A168 );
a6041a <=( A170 and a6040a );
a6045a <=( (not A200) and A199 );
a6046a <=( A166 and a6045a );
a6047a <=( a6046a and a6041a );
a6051a <=( (not A298) and A202 );
a6052a <=( (not A201) and a6051a );
a6056a <=( (not A302) and A301 );
a6057a <=( (not A299) and a6056a );
a6058a <=( a6057a and a6052a );
a6062a <=( (not A167) and A168 );
a6063a <=( A170 and a6062a );
a6067a <=( (not A200) and A199 );
a6068a <=( A166 and a6067a );
a6069a <=( a6068a and a6063a );
a6073a <=( A298 and (not A203) );
a6074a <=( (not A201) and a6073a );
a6078a <=( (not A302) and A301 );
a6079a <=( A299 and a6078a );
a6080a <=( a6079a and a6074a );
a6084a <=( (not A167) and A168 );
a6085a <=( A170 and a6084a );
a6089a <=( (not A200) and A199 );
a6090a <=( A166 and a6089a );
a6091a <=( a6090a and a6085a );
a6095a <=( A298 and (not A203) );
a6096a <=( (not A201) and a6095a );
a6100a <=( A302 and (not A301) );
a6101a <=( (not A299) and a6100a );
a6102a <=( a6101a and a6096a );
a6106a <=( (not A167) and A168 );
a6107a <=( A170 and a6106a );
a6111a <=( (not A200) and A199 );
a6112a <=( A166 and a6111a );
a6113a <=( a6112a and a6107a );
a6117a <=( (not A298) and (not A203) );
a6118a <=( (not A201) and a6117a );
a6122a <=( A302 and (not A301) );
a6123a <=( A299 and a6122a );
a6124a <=( a6123a and a6118a );
a6128a <=( (not A167) and A168 );
a6129a <=( A170 and a6128a );
a6133a <=( (not A200) and A199 );
a6134a <=( A166 and a6133a );
a6135a <=( a6134a and a6129a );
a6139a <=( (not A298) and (not A203) );
a6140a <=( (not A201) and a6139a );
a6144a <=( (not A302) and A301 );
a6145a <=( (not A299) and a6144a );
a6146a <=( a6145a and a6140a );
a6150a <=( (not A167) and A168 );
a6151a <=( A169 and a6150a );
a6155a <=( A200 and A199 );
a6156a <=( A166 and a6155a );
a6157a <=( a6156a and a6151a );
a6161a <=( A298 and (not A202) );
a6162a <=( (not A201) and a6161a );
a6166a <=( (not A302) and A301 );
a6167a <=( A299 and a6166a );
a6168a <=( a6167a and a6162a );
a6172a <=( (not A167) and A168 );
a6173a <=( A169 and a6172a );
a6177a <=( A200 and A199 );
a6178a <=( A166 and a6177a );
a6179a <=( a6178a and a6173a );
a6183a <=( A298 and (not A202) );
a6184a <=( (not A201) and a6183a );
a6188a <=( A302 and (not A301) );
a6189a <=( (not A299) and a6188a );
a6190a <=( a6189a and a6184a );
a6194a <=( (not A167) and A168 );
a6195a <=( A169 and a6194a );
a6199a <=( A200 and A199 );
a6200a <=( A166 and a6199a );
a6201a <=( a6200a and a6195a );
a6205a <=( (not A298) and (not A202) );
a6206a <=( (not A201) and a6205a );
a6210a <=( A302 and (not A301) );
a6211a <=( A299 and a6210a );
a6212a <=( a6211a and a6206a );
a6216a <=( (not A167) and A168 );
a6217a <=( A169 and a6216a );
a6221a <=( A200 and A199 );
a6222a <=( A166 and a6221a );
a6223a <=( a6222a and a6217a );
a6227a <=( (not A298) and (not A202) );
a6228a <=( (not A201) and a6227a );
a6232a <=( (not A302) and A301 );
a6233a <=( (not A299) and a6232a );
a6234a <=( a6233a and a6228a );
a6238a <=( (not A167) and A168 );
a6239a <=( A169 and a6238a );
a6243a <=( A200 and A199 );
a6244a <=( A166 and a6243a );
a6245a <=( a6244a and a6239a );
a6249a <=( A298 and A203 );
a6250a <=( (not A201) and a6249a );
a6254a <=( (not A302) and A301 );
a6255a <=( A299 and a6254a );
a6256a <=( a6255a and a6250a );
a6260a <=( (not A167) and A168 );
a6261a <=( A169 and a6260a );
a6265a <=( A200 and A199 );
a6266a <=( A166 and a6265a );
a6267a <=( a6266a and a6261a );
a6271a <=( A298 and A203 );
a6272a <=( (not A201) and a6271a );
a6276a <=( A302 and (not A301) );
a6277a <=( (not A299) and a6276a );
a6278a <=( a6277a and a6272a );
a6282a <=( (not A167) and A168 );
a6283a <=( A169 and a6282a );
a6287a <=( A200 and A199 );
a6288a <=( A166 and a6287a );
a6289a <=( a6288a and a6283a );
a6293a <=( (not A298) and A203 );
a6294a <=( (not A201) and a6293a );
a6298a <=( A302 and (not A301) );
a6299a <=( A299 and a6298a );
a6300a <=( a6299a and a6294a );
a6304a <=( (not A167) and A168 );
a6305a <=( A169 and a6304a );
a6309a <=( A200 and A199 );
a6310a <=( A166 and a6309a );
a6311a <=( a6310a and a6305a );
a6315a <=( (not A298) and A203 );
a6316a <=( (not A201) and a6315a );
a6320a <=( (not A302) and A301 );
a6321a <=( (not A299) and a6320a );
a6322a <=( a6321a and a6316a );
a6326a <=( (not A167) and A168 );
a6327a <=( A169 and a6326a );
a6331a <=( A200 and (not A199) );
a6332a <=( A166 and a6331a );
a6333a <=( a6332a and a6327a );
a6337a <=( A298 and A202 );
a6338a <=( (not A201) and a6337a );
a6342a <=( (not A302) and A301 );
a6343a <=( A299 and a6342a );
a6344a <=( a6343a and a6338a );
a6348a <=( (not A167) and A168 );
a6349a <=( A169 and a6348a );
a6353a <=( A200 and (not A199) );
a6354a <=( A166 and a6353a );
a6355a <=( a6354a and a6349a );
a6359a <=( A298 and A202 );
a6360a <=( (not A201) and a6359a );
a6364a <=( A302 and (not A301) );
a6365a <=( (not A299) and a6364a );
a6366a <=( a6365a and a6360a );
a6370a <=( (not A167) and A168 );
a6371a <=( A169 and a6370a );
a6375a <=( A200 and (not A199) );
a6376a <=( A166 and a6375a );
a6377a <=( a6376a and a6371a );
a6381a <=( (not A298) and A202 );
a6382a <=( (not A201) and a6381a );
a6386a <=( A302 and (not A301) );
a6387a <=( A299 and a6386a );
a6388a <=( a6387a and a6382a );
a6392a <=( (not A167) and A168 );
a6393a <=( A169 and a6392a );
a6397a <=( A200 and (not A199) );
a6398a <=( A166 and a6397a );
a6399a <=( a6398a and a6393a );
a6403a <=( (not A298) and A202 );
a6404a <=( (not A201) and a6403a );
a6408a <=( (not A302) and A301 );
a6409a <=( (not A299) and a6408a );
a6410a <=( a6409a and a6404a );
a6414a <=( (not A167) and A168 );
a6415a <=( A169 and a6414a );
a6419a <=( A200 and (not A199) );
a6420a <=( A166 and a6419a );
a6421a <=( a6420a and a6415a );
a6425a <=( A298 and (not A203) );
a6426a <=( (not A201) and a6425a );
a6430a <=( (not A302) and A301 );
a6431a <=( A299 and a6430a );
a6432a <=( a6431a and a6426a );
a6436a <=( (not A167) and A168 );
a6437a <=( A169 and a6436a );
a6441a <=( A200 and (not A199) );
a6442a <=( A166 and a6441a );
a6443a <=( a6442a and a6437a );
a6447a <=( A298 and (not A203) );
a6448a <=( (not A201) and a6447a );
a6452a <=( A302 and (not A301) );
a6453a <=( (not A299) and a6452a );
a6454a <=( a6453a and a6448a );
a6458a <=( (not A167) and A168 );
a6459a <=( A169 and a6458a );
a6463a <=( A200 and (not A199) );
a6464a <=( A166 and a6463a );
a6465a <=( a6464a and a6459a );
a6469a <=( (not A298) and (not A203) );
a6470a <=( (not A201) and a6469a );
a6474a <=( A302 and (not A301) );
a6475a <=( A299 and a6474a );
a6476a <=( a6475a and a6470a );
a6480a <=( (not A167) and A168 );
a6481a <=( A169 and a6480a );
a6485a <=( A200 and (not A199) );
a6486a <=( A166 and a6485a );
a6487a <=( a6486a and a6481a );
a6491a <=( (not A298) and (not A203) );
a6492a <=( (not A201) and a6491a );
a6496a <=( (not A302) and A301 );
a6497a <=( (not A299) and a6496a );
a6498a <=( a6497a and a6492a );
a6502a <=( (not A167) and A168 );
a6503a <=( A169 and a6502a );
a6507a <=( (not A200) and A199 );
a6508a <=( A166 and a6507a );
a6509a <=( a6508a and a6503a );
a6513a <=( A298 and A202 );
a6514a <=( (not A201) and a6513a );
a6518a <=( (not A302) and A301 );
a6519a <=( A299 and a6518a );
a6520a <=( a6519a and a6514a );
a6524a <=( (not A167) and A168 );
a6525a <=( A169 and a6524a );
a6529a <=( (not A200) and A199 );
a6530a <=( A166 and a6529a );
a6531a <=( a6530a and a6525a );
a6535a <=( A298 and A202 );
a6536a <=( (not A201) and a6535a );
a6540a <=( A302 and (not A301) );
a6541a <=( (not A299) and a6540a );
a6542a <=( a6541a and a6536a );
a6546a <=( (not A167) and A168 );
a6547a <=( A169 and a6546a );
a6551a <=( (not A200) and A199 );
a6552a <=( A166 and a6551a );
a6553a <=( a6552a and a6547a );
a6557a <=( (not A298) and A202 );
a6558a <=( (not A201) and a6557a );
a6562a <=( A302 and (not A301) );
a6563a <=( A299 and a6562a );
a6564a <=( a6563a and a6558a );
a6568a <=( (not A167) and A168 );
a6569a <=( A169 and a6568a );
a6573a <=( (not A200) and A199 );
a6574a <=( A166 and a6573a );
a6575a <=( a6574a and a6569a );
a6579a <=( (not A298) and A202 );
a6580a <=( (not A201) and a6579a );
a6584a <=( (not A302) and A301 );
a6585a <=( (not A299) and a6584a );
a6586a <=( a6585a and a6580a );
a6590a <=( (not A167) and A168 );
a6591a <=( A169 and a6590a );
a6595a <=( (not A200) and A199 );
a6596a <=( A166 and a6595a );
a6597a <=( a6596a and a6591a );
a6601a <=( A298 and (not A203) );
a6602a <=( (not A201) and a6601a );
a6606a <=( (not A302) and A301 );
a6607a <=( A299 and a6606a );
a6608a <=( a6607a and a6602a );
a6612a <=( (not A167) and A168 );
a6613a <=( A169 and a6612a );
a6617a <=( (not A200) and A199 );
a6618a <=( A166 and a6617a );
a6619a <=( a6618a and a6613a );
a6623a <=( A298 and (not A203) );
a6624a <=( (not A201) and a6623a );
a6628a <=( A302 and (not A301) );
a6629a <=( (not A299) and a6628a );
a6630a <=( a6629a and a6624a );
a6634a <=( (not A167) and A168 );
a6635a <=( A169 and a6634a );
a6639a <=( (not A200) and A199 );
a6640a <=( A166 and a6639a );
a6641a <=( a6640a and a6635a );
a6645a <=( (not A298) and (not A203) );
a6646a <=( (not A201) and a6645a );
a6650a <=( A302 and (not A301) );
a6651a <=( A299 and a6650a );
a6652a <=( a6651a and a6646a );
a6656a <=( (not A167) and A168 );
a6657a <=( A169 and a6656a );
a6661a <=( (not A200) and A199 );
a6662a <=( A166 and a6661a );
a6663a <=( a6662a and a6657a );
a6667a <=( (not A298) and (not A203) );
a6668a <=( (not A201) and a6667a );
a6672a <=( (not A302) and A301 );
a6673a <=( (not A299) and a6672a );
a6674a <=( a6673a and a6668a );
end x25_18x_behav;
| gpl-3.0 | 3dd5f2678d52402e3470ade877948245 | 0.606398 | 2.162668 | false | false | false | false |
sils1297/HWPrak14 | task_4/project_1.srcs/sources_1/new/ProgramCounter.vhd | 1 | 802 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ProgramCounter is
generic(
WIDTH : integer := 16
);
Port(
inval : in std_ulogic_vector(WIDTH - 1 downto 0);
comp : in std_ulogic_vector(WIDTH - 1 downto 0);
jump : in std_ulogic_vector(2 downto 0);
reset : in std_ulogic;
clock : in std_ulogic;
outval : out std_ulogic_vector(WIDTH - 1 downto 0)
);
end ProgramCounter;
architecture Behavioral of ProgramCounter is
begin
process(clock, set)
begin
if reset = '1' then
outval <= (others => '0');
else
if (j(0) = '1' and signed(comp) < 0) or
(j(1) = '1' and signed(comp) = 0) or
(j(2) = '1' and signed(comp) > 0) then
outval <= inval;
else
outval <= outval + 1;
end if;
end if;
end process;
end Behavioral;
| agpl-3.0 | b7502e3a4264da40e6b1d99f645bfb34 | 0.623441 | 2.746575 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/pselect_mask.vhd | 15 | 13,363 | -------------------------------------------------------------------------------
-- $Id: pselect_mask.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pselect_mask.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pselect_mask.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pselect_mask.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- goran 2002-02-06 First Version
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library Unisim;
use Unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- PS -- peripheral select
-------------------------------------------------------------------------------
entity pselect_mask is
generic (
C_AW : integer := 32;
C_BAR : std_logic_vector(0 to 31) := "00000000000000100000000000000000";
C_MASK : std_logic_vector(0 to 31) := "00000000000001111100000000000000"
);
port (
A : in std_logic_vector(0 to C_AW-1);
Valid : in std_logic;
CS : out std_logic
);
end entity pselect_mask;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
library unisim;
use unisim.all;
architecture imp of pselect_mask is
-- component LUT4
-- generic(
-- INIT : bit_vector := X"0000"
-- );
-- port (
-- O : out std_logic;
-- I0 : in std_logic := '0';
-- I1 : in std_logic := '0';
-- I2 : in std_logic := '0';
-- I3 : in std_logic := '0');
-- end component;
-- component MUXCY is
-- port (
-- O : out std_logic;
-- CI : in std_logic;
-- DI : in std_logic;
-- S : in std_logic
-- );
-- end component MUXCY;
function Nr_Of_Ones (S : std_logic_vector) return natural is
variable tmp : natural := 0;
begin -- function Nr_Of_Ones
for I in S'range loop
if (S(I) = '1') then
tmp := tmp + 1;
end if;
end loop; -- I
return tmp;
end function Nr_Of_Ones;
function fix_AB (B : boolean; I : integer) return integer is
begin -- function fix_AB
if (not B) then
return I + 1;
else
return I;
end if;
end function fix_AB;
constant Nr : integer := Nr_Of_Ones(C_MASK);
constant Use_CIN : boolean := ((Nr mod 4) = 0);
constant AB : integer := fix_AB(Use_CIN, Nr);
attribute INIT : string;
constant NUM_LUTS : integer := (AB-1)/4+1;
-- signal lut_out : std_logic_vector(0 to NUM_LUTS-1);
-- signal carry_chain : std_logic_vector(0 to NUM_LUTS);
-- function to initialize LUT within pselect
type int4 is array (3 downto 0) of integer;
function pselect_init_lut(i : integer;
AB : integer;
NUM_LUTS : integer;
C_AW : integer;
C_BAR : std_logic_vector(0 to 31))
return bit_vector is
variable init_vector : bit_vector(15 downto 0) := X"0001";
variable j : integer := 0;
variable val_in : int4;
begin
for j in 0 to 3 loop
if i < NUM_LUTS-1 or j <= ((AB-1) mod 4) then
val_in(j) := conv_integer(C_BAR(i*4+j));
else val_in(j) := 0;
end if;
end loop;
init_vector := To_bitvector(conv_std_logic_vector(2**(val_in(3)*8+
val_in(2)*4+val_in(1)*2+val_in(0)*1),16));
return init_vector;
end pselect_init_lut;
signal A_Bus : std_logic_vector(0 to AB);
signal BAR : std_logic_vector(0 to AB);
-------------------------------------------------------------------------------
-- Begin architecture section
-------------------------------------------------------------------------------
begin -- VHDL_RTL
Make_Busses : process (A,Valid) is
variable tmp : natural;
begin -- process Make_Busses
tmp := 0;
A_Bus <= (others => '0');
BAR <= (others => '0');
for I in C_MASK'range loop
if (C_MASK(I) = '1') then
A_Bus(tmp) <= A(I);
BAR(tmp) <= C_BAR(I);
tmp := tmp + 1;
end if;
end loop; -- I
if (not Use_CIN) then
BAR(tmp) <= '1';
A_Bus(tmp) <= Valid;
end if;
end process Make_Busses;
-- More_Than_3_Bits : if (AB > 3) generate
-- Using_CIn: if (Use_CIN) generate
-- carry_chain(0) <= Valid;
-- end generate Using_CIn;
-- No_CIn: if (not Use_CIN) generate
-- carry_chain(0) <= '1';
-- end generate No_CIn;
-- GEN_DECODE : for i in 0 to NUM_LUTS-1 generate
-- signal lut_in : std_logic_vector(3 downto 0);
-- begin
-- GEN_LUT_INPUTS : for j in 0 to 3 generate
-- -- Generate to assign address bits to LUT4 inputs
-- GEN_INPUT : if i < NUM_LUTS-1 or j <= ((AB-1) mod 4) generate
-- lut_in(j) <= A_Bus(i*4+j);
-- end generate;
-- -- Generate to assign zeros to remaining LUT4 inputs
-- GEN_ZEROS : if not(i < NUM_LUTS-1 or j <= ((AB-1) mod 4)) generate
-- lut_in(j) <= '0';
-- end generate;
-- end generate;
---------------------------------------------------------------------------------
---- RTL version without LUT instantiation for XST
---------------------------------------------------------------------------------
-- lut_out(i) <= (lut_in(0) xnor BAR(i*4+0)) and
-- (lut_in(1) xnor BAR(i*4+1)) and
-- (lut_in(2) xnor BAR(i*4+2)) and
-- (lut_in(3) xnor BAR(i*4+3));
---------------------------------------------------------------------------------
---- Structural version with LUT instantiation for Synplicity (when RLOC is
---- desired for placing LUT
---------------------------------------------------------------------------------
---- LUT4_I : LUT4
---- generic map(
---- -- Function init_lut is used to generate INIT value for LUT4
---- INIT => pselect_init_lut(i,C_AB,NUM_LUTS,C_AW,C_BAR)
---- )
---- port map (
---- O => lut_out(i), -- [out]
---- I0 => lut_in(0), -- [in]
---- I1 => lut_in(1), -- [in]
---- I2 => lut_in(2), -- [in]
---- I3 => lut_in(3)); -- [in]
---------------------------------------------------------------------------------
-- MUXCY_I : MUXCY
-- port map (
-- O => carry_chain(i+1), --[out]
-- CI => carry_chain(i), --[in]
-- DI => '0', --[in]
-- S => lut_out(i) --[in]
-- );
-- end generate;
-- CS <= carry_chain(NUM_LUTS); -- assign end of carry chain to output
-- end generate More_Than_3_Bits;
-- Less_than_4_bits: if (AB < 4) generate
CS <= Valid when A_Bus=BAR else '0';
-- end generate Less_than_4_bits;
end imp;
| apache-2.0 | 4cec9d550a4568a35afba5eeb69b066b | 0.41353 | 4.46028 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/axi_intc_v4_1/28e93d3e/hdl/src/vhdl/double_synchronizer.vhd | 5 | 6,181 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename : double_synchronizer.vhd
-- Version : v3.0
-- Description: The double_synchronizer is having the double flop synchronization logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-------------------------------------------------------------------------------
-- Author: NLR
-- History:
-- NLR 3/21/2011 Initial version
-- ^^^^^^^
-- ^^^^^^^
-- SK 10/10/12
--
-- 1. Added cascade mode support in v1.03.a version of the core
-- 2. Updated major version of the core
-- ~~~~~~
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*N"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- RESET_2 signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- counter signals: "*cntr*", "*count*"
-- ports: - Names in Uppercase
-- processes: "*_REG", "*_CMB"
-- component instantiations: "<ENTITY_>MODULE<#|_FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library axi_intc_v4_1;
use axi_intc_v4_1.all;
library unisim;
use unisim.vcomponents.FDR;
-------------------------------------------------------------------------------
entity double_synchronizer is
generic (
C_DWIDTH : integer range 1 to 32 := 1
);
port (
CLK_2 : in std_logic;
RESET_2_n : in std_logic; -- active_low
DATA_IN : in std_logic_vector(C_DWIDTH-1 downto 0);
SYNC_DATA_OUT : out std_logic_vector(C_DWIDTH-1 downto 0)
);
end entity;
-------------------------------------------------------------------------------
architecture RTL of double_synchronizer is
signal RESET_2_p : std_logic;
signal data_in_d1 : std_logic_vector(C_DWIDTH-1 downto 0);
-----
begin
-----
-- active high Reset
RESET_2_p <= not RESET_2_n;
REG_GEN : for i in 0 to (C_DWIDTH - 1) generate
BLOCK_GEN: block
attribute ASYNC_REG : string;
attribute ASYNC_REG of FIRST_FLOP_i : label is "TRUE";
begin
FIRST_FLOP_i: component FDR
port map (
Q => data_in_d1(i),
C => CLK_2,
D => DATA_IN(i),
R => RESET_2_p
);
SECOND_FLOP_i: component FDR
port map (
Q => SYNC_DATA_OUT(i),
C => CLK_2,
D => data_in_d1(i),
R => RESET_2_p
);
end block BLOCK_GEN;
end generate REG_GEN;
-------------------------------------------------------------------------------
end RTL;
-------------------------------------------------------------------------------
| apache-2.0 | 883f839074504977d2b14efc19d8e6d8 | 0.504126 | 4.772973 | false | false | false | false |
rhexsel/xinu-cMIPS | vhdl/rom.vhd | 1 | 8,638 | -- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- syncronous ROM; FPGA version, word-indexed
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
entity ROM is
generic (LOAD_FILE_NAME : string := "prog.bin"); -- not used with FPGA
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic; -- active in '0'
rdy : out std_logic; -- active in '0'
strobe : in std_logic;
addr : in reg32;
data : out reg32);
-- FPGA version
constant INST_ADDRS_BITS : natural := log2_ceil(INST_MEM_SZ);
subtype rom_address is natural range 0 to ((INST_MEM_SZ / 4) - 1);
end entity ROM;
architecture rtl of ROM is
component wait_states is
generic (NUM_WAIT_STATES :integer := 0);
port(rst : in std_logic;
clk : in std_logic;
sel : in std_logic; -- active in '0'
waiting : out std_logic); -- active in '1'
end component wait_states;
component single_port_rom is
generic (N_WORDS : integer);
port (address : in rom_address;
clken : in std_logic;
clock : in std_logic;
q : out std_logic_vector);
end component single_port_rom;
component alt_mf_rom
port (address : IN STD_LOGIC_VECTOR ((INST_ADDRS_BITS-1) DOWNTO 0);
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0));
end component alt_mf_rom;
signal instrn : reg32;
signal index : rom_address := 0;
signal waiting, clken : std_logic;
signal raw_addr : std_logic_vector((INST_ADDRS_BITS-1) downto 0);
begin -- rtl
U_BUS_WAIT: wait_states generic map (ROM_WAIT_STATES)
port map (rst, clk, sel, waiting);
rdy <= not(waiting);
clken <= not(sel);
-- >>2 = /4: byte addressed but word indexed
index <= to_integer(unsigned(addr((INST_ADDRS_BITS-1)+2 downto 2)));
-- U_ROM: single_port_rom generic map (INST_MEM_SZ / 4)
-- port map (index, clken, strobe, instrn);
raw_addr <= addr((INST_ADDRS_BITS-1)+2 downto 2);
U_RTL_ROM: alt_mf_rom port map (raw_addr, clken, strobe, instrn);
U_ROM_ACCESS: process (instrn, sel, index)
begin
if sel = '0' then
data <= instrn;
assert (index >= 0) and (index < INST_MEM_SZ/4)
report "rom index out of bounds: " & natural'image(index)
severity failure;
assert TRUE -- DEBUG
report "romRD["& natural'image(index) &"]="& SLV32HEX(instrn);
else
data <= (others => 'X');
end if;
end process U_ROM_ACCESS;
end architecture rtl;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Adapted from Altera's design for a ROM that may be synthesized
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.p_wires.all;
entity single_port_rom is
generic (N_WORDS : integer := 32);
port (address : in natural range 0 to (N_WORDS - 1);
clken : in std_logic;
clock : in std_logic;
q : out reg32);
end entity;
architecture rtl of single_port_rom is
-- Build a 2-D array type for the RoM
subtype word_t is std_logic_vector(31 downto 0);
type memory_t is array(0 to (N_WORDS-1)) of word_t;
-- assemble.sh -v mac_lcd.s |\
-- sed -e '1,6d' -e '/^$/d' -e '/^ /!d' -e 's:\t: :g' \
-- -e 's#\(^ *[a-f0-9]*:\) *\(........\) *\(.*\)$#x"\2", -- \1 \3#' \
-- -e '$s:,: :'
constant test_prog : memory_t := (others => (others => '0'));
function init_rom
return memory_t is
variable tmp : memory_t := (others => (others => '0'));
variable i_addr : integer;
begin
for addr_pos in test_prog'range loop
tmp(addr_pos) := test_prog(addr_pos);
-- i_addr := addr_pos;
end loop;
for addr_pos in test_prog'high to (N_WORDS - 1) loop
tmp(addr_pos) := x"00000000"; -- nop
end loop;
return tmp;
end init_rom;
-- Declare the ROM signal and specify a default value. Quartus II
-- will create a memory initialization file (ROM.mif) based on the
-- default value.
signal rom : memory_t := init_rom;
begin
process(clock,clken)
begin
if(clken = '1' and rising_edge(clock)) then
q <= rom(address);
end if;
end process;
end architecture rtl;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- syncronous ROM; MIPS executable loaded into ROM at CPU reset, wd-indexed
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
architecture simulation of ROM is
component wait_states is
generic (NUM_WAIT_STATES :integer := 0);
port(rst : in std_logic;
clk : in std_logic;
sel : in std_logic; -- active in '0'
waiting : out std_logic); -- active in '1'
end component wait_states;
component FFT is
port(clk, rst, T : in std_logic; Q : out std_logic);
end component FFT;
constant WAIT_COUNT : max_wait_states := (NUM_MAX_W_STS - ROM_WAIT_STATES);
constant WAIT_FOR : reg10 := std_logic_vector(to_signed(WAIT_COUNT, 10));
signal waiting, do_wait : std_logic;
begin -- behavioral
U_BUS_WAIT: wait_states generic map (ROM_WAIT_STATES)
port map (rst, clk, sel, waiting);
rdy <= not(waiting);
U_ROM: process (rst, sel, strobe, addr)
subtype t_address is unsigned((INST_ADDRS_BITS - 1) downto 0);
variable u_addr : t_address;
subtype word is std_logic_vector(data'length - 1 downto 0);
type storage_array is
array( natural range 0 to (INST_MEM_SZ - 1) ) of word;
variable storage : storage_array;
variable index, latched : natural;
type binary_file is file of integer;
file load_file: binary_file open read_mode is LOAD_FILE_NAME;
variable instr: integer; -- := to_integer(unsigned(NULL_INSTRUCTION));
variable s_instr : signed(31 downto 0);
begin
if rst = '0' then -- reset, read binary executable
index := 0; -- indexed by word
for i in 0 to (INST_MEM_SZ - 1) loop
if not endfile(load_file) then
read(load_file, instr);
s_instr := to_signed(instr, 32);
assert TRUE report "romINIT["& natural'image(index*4) &"]= " &
SLV32HEX(std_logic_vector(s_instr)); -- DEBUG
storage(index) := std_logic_vector(s_instr);
index := index + 1;
end if;
end loop; -- i
else -- normal operation
u_addr := unsigned(addr((2+(INST_ADDRS_BITS-1)) downto 2)); -- >>2 = /4
index := to_integer(u_addr); -- indexed by word, not by byte
assert (index >= 0) and (index < INST_MEM_SZ/4)
report "romRDindex out of bounds: " & SLV32HEX(addr) & " = " &
natural'image(index) severity warning; -- failure;
if sel = '0' and rising_edge(strobe) then
latched := index;
end if;
if sel = '0' then
data <= storage(latched);
assert TRUE -- DEBUG
report "romRD["& natural'image(index) &"]="& SLV32HEX(storage(index));
else
data <= (others => 'X');
end if;
end if;
end process;
end architecture simulation;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| gpl-3.0 | a41a2ba63021144b769ef514030900b3 | 0.534962 | 3.757286 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/3-ARF/metaheurísticas/arf_spea2.vhd | 1 | 2,416 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-13.07:35:18)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY arf_spea2_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8: IN unsigned(0 TO 3);
output1, output2: OUT unsigned(0 TO 4));
END arf_spea2_entity;
ARCHITECTURE arf_spea2_description OF arf_spea2_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
register2 := input2 * 2;
WHEN "00000010" =>
register3 := input3 * 3;
register4 := input4 * 4;
register1 := register2 + register1;
WHEN "00000011" =>
register2 := register3 + register4;
register1 := register1 + 6;
register3 := input5 * 7;
register4 := input6 * 8;
WHEN "00000100" =>
register3 := register3 + register4;
register4 := input7 * 9;
register5 := input8 * 10;
register2 := register2 + 12;
WHEN "00000101" =>
register6 := register1 * 14;
register4 := register5 + register4;
register5 := register2 * 16;
WHEN "00000110" =>
register2 := register2 * 18;
register1 := register1 * 20;
register5 := register5 + register6;
WHEN "00000111" =>
register1 := register2 + register1;
register2 := register5 * 22;
register5 := register5 * 24;
WHEN "00001000" =>
register6 := register1 * 26;
register1 := register1 * 28;
WHEN "00001001" =>
register1 := register1 + register2;
register2 := register6 + register5;
WHEN "00001010" =>
output1 <= register4 + register2;
output2 <= register3 + register1;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END arf_spea2_description; | gpl-3.0 | 469f6f13af6db49ac35bf6d7e6e49f2c | 0.656043 | 3.081633 | false | false | false | false |
marceloboeira/vhdl-examples | 008-state-machine-calculator/_example/vetor_de_debounce.vhd | 1 | 1,937 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:20:49 09/25/2012
-- Design Name:
-- Module Name: vetor_de_debounce - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
entity debounce is
Port ( clock : in std_logic;
entrada : in STD_LOGIC;
entrada_tmp1_o : out STD_LOGIC;
entrada_tmp2_o : out STD_LOGIC;
contagem_o : out std_logic_vector(19 downto 0);
saida_DB : out STD_LOGIC);
end debounce;
architecture Behavioral of debounce is
constant atraso : integer := 500000; -- alterado p/ 500 p/ simular. Valor p/ sintese ingual a 500000
signal contagem : integer := 0;
signal entrada_tmp1, entrada_tmp2 : std_logic:='0';
signal saida_tmp : std_logic;
begin
contar: process (entrada, clock, entrada_tmp1)
begin
if entrada /= entrada_tmp1 then
contagem <= 0;
entrada_tmp1 <= entrada;
elsif clock'event and clock = '1' then
entrada_tmp1 <= entrada;
entrada_tmp2 <= entrada_tmp1;
contagem <= contagem +1;
else
contagem <= contagem;
end if;
end process;
avaliar: process (clock, entrada_tmp1, entrada_tmp2, contagem)
begin
if clock'event and clock='1' then
if contagem >= atraso and entrada_tmp1 = entrada_tmp2 then
saida_tmp <= entrada;
else
saida_tmp <= saida_tmp;
end if;
else
saida_tmp <= saida_tmp;
end if;
end process;
saida_DB <= saida_tmp;
contagem_o <= conv_std_logic_vector(contagem, 20);
entrada_tmp1_o <= entrada_tmp1;
entrada_tmp2_o <= entrada_tmp2;
end Behavioral;
| mit | b02d616ae02c40f8f72c83627a0daf42 | 0.580279 | 3.316781 | false | false | false | false |
freecores/twofish | vhdl/twofish_ecb_vt_testbench_192bits.vhd | 1 | 10,445 | -- Twofish_ecb_vt_testbench_192bits.vhd
-- Copyright (C) 2006 Spyros Ninos
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this library; see the file COPYING. If not, write to:
--
-- Free Software Foundation
-- 59 Temple Place - Suite 330
-- Boston, MA 02111-1307, USA.
--
-- description : this file is the testbench for the VARIABLE TEXT KAT of the twofish cipher with 192 bit key
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_arith.all;
use std.textio.all;
entity vt_testbench192 is
end vt_testbench192;
architecture vt_encryption192_testbench_arch of vt_testbench192 is
component reg128
port (
in_reg128 : in std_logic_vector(127 downto 0);
out_reg128 : out std_logic_vector(127 downto 0);
enable_reg128, reset_reg128, clk_reg128 : in std_logic
);
end component;
component twofish_keysched192
port (
odd_in_tk192,
even_in_tk192 : in std_logic_vector(7 downto 0);
in_key_tk192 : in std_logic_vector(191 downto 0);
out_key_up_tk192,
out_key_down_tk192 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_whit_keysched192
port (
in_key_twk192 : in std_logic_vector(191 downto 0);
out_K0_twk192,
out_K1_twk192,
out_K2_twk192,
out_K3_twk192,
out_K4_twk192,
out_K5_twk192,
out_K6_twk192,
out_K7_twk192 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_encryption_round192
port (
in1_ter192,
in2_ter192,
in3_ter192,
in4_ter192,
in_Sfirst_ter192,
in_Ssecond_ter192,
in_Sthird_ter192,
in_key_up_ter192,
in_key_down_ter192 : in std_logic_vector(31 downto 0);
out1_ter192,
out2_ter192,
out3_ter192,
out4_ter192 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_data_input
port (
in_tdi : in std_logic_vector(127 downto 0);
out_tdi : out std_logic_vector(127 downto 0)
);
end component;
component twofish_data_output
port (
in_tdo : in std_logic_vector(127 downto 0);
out_tdo : out std_logic_vector(127 downto 0)
);
end component;
component demux128
port ( in_demux128 : in std_logic_vector(127 downto 0);
out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0);
selection_demux128 : in std_logic
);
end component;
component mux128
port ( in1_mux128, in2_mux128 : in std_logic_vector(127 downto 0);
selection_mux128 : in std_logic;
out_mux128 : out std_logic_vector(127 downto 0)
);
end component;
component twofish_S192
port (
in_key_ts192 : in std_logic_vector(191 downto 0);
out_Sfirst_ts192,
out_Ssecond_ts192,
out_Sthird_ts192 : out std_logic_vector(31 downto 0)
);
end component;
FILE input_file : text is in "twofish_ecb_vt_testvalues_192bits.txt";
FILE output_file : text is out "twofish_ecb_vt_192bits_results.txt";
-- we create the functions that transform a number to text
-- transforming a signle digit to a character
function digit_to_char(number : integer range 0 to 9) return character is
begin
case number is
when 0 => return '0';
when 1 => return '1';
when 2 => return '2';
when 3 => return '3';
when 4 => return '4';
when 5 => return '5';
when 6 => return '6';
when 7 => return '7';
when 8 => return '8';
when 9 => return '9';
end case;
end;
-- transforming multi-digit number to text
function to_text(int_number : integer range 1 to 129) return string is
variable our_text : string (1 to 3) := (others => ' ');
variable hundreds,
tens,
ones : integer range 0 to 9;
begin
ones := int_number mod 10;
tens := ((int_number mod 100) - ones) / 10;
hundreds := (int_number - (int_number mod 100)) / 100;
our_text(1) := digit_to_char(hundreds);
our_text(2) := digit_to_char(tens);
our_text(3) := digit_to_char(ones);
return our_text;
end;
signal odd_number,
even_number : std_logic_vector(7 downto 0);
signal input_data,
output_data,
to_encr_reg128,
from_tdi_to_xors,
to_output_whit_xors,
from_xors_to_tdo,
to_mux, to_demux,
from_input_whit_xors,
to_round,
to_input_mux : std_logic_vector(127 downto 0) ;
signal twofish_key : std_logic_vector(191 downto 0);
signal key_up,
key_down,
Sfirst,
Ssecond,
Sthird,
from_xor0,
from_xor1,
from_xor2,
from_xor3,
K0,K1,K2,K3,
K4,K5,K6,K7 : std_logic_vector(31 downto 0);
signal clk : std_logic := '0';
signal mux_selection : std_logic := '0';
signal demux_selection: std_logic := '0';
signal enable_encr_reg : std_logic := '0';
signal reset : std_logic := '0';
signal enable_round_reg : std_logic := '0';
-- begin the testbench arch description
begin
-- getting data to encrypt
data_input: twofish_data_input
port map (
in_tdi => input_data,
out_tdi => from_tdi_to_xors
);
-- producing whitening keys K0..7
the_whitening_step: twofish_whit_keysched192
port map (
in_key_twk192 => twofish_key,
out_K0_twk192 => K0,
out_K1_twk192 => K1,
out_K2_twk192 => K2,
out_K3_twk192 => K3,
out_K4_twk192 => K4,
out_K5_twk192 => K5,
out_K6_twk192 => K6,
out_K7_twk192 => K7
);
-- performing the input whitening XORs
from_xor0 <= K0 XOR from_tdi_to_xors(127 downto 96);
from_xor1 <= K1 XOR from_tdi_to_xors(95 downto 64);
from_xor2 <= K2 XOR from_tdi_to_xors(63 downto 32);
from_xor3 <= K3 XOR from_tdi_to_xors(31 downto 0);
from_input_whit_xors <= from_xor0 & from_xor1 & from_xor2 & from_xor3;
round_reg: reg128
port map ( in_reg128 => from_input_whit_xors,
out_reg128 => to_input_mux,
enable_reg128 => enable_round_reg,
reset_reg128 => reset,
clk_reg128 => clk );
input_mux: mux128
port map ( in1_mux128 => to_input_mux,
in2_mux128 => to_mux,
out_mux128 => to_round,
selection_mux128 => mux_selection
);
-- creating a round
the_keysched_of_the_round: twofish_keysched192
port map (
odd_in_tk192 => odd_number,
even_in_tk192 => even_number,
in_key_tk192 => twofish_key,
out_key_up_tk192 => key_up,
out_key_down_tk192 => key_down
);
producing_the_Skeys: twofish_S192
port map (
in_key_ts192 => twofish_key,
out_Sfirst_ts192 => Sfirst,
out_Ssecond_ts192 => Ssecond,
out_Sthird_ts192 => Sthird
);
the_encryption_circuit: twofish_encryption_round192
port map (
in1_ter192 => to_round(127 downto 96),
in2_ter192 => to_round(95 downto 64),
in3_ter192 => to_round(63 downto 32),
in4_ter192 => to_round(31 downto 0),
in_Sfirst_ter192 => Sfirst,
in_Ssecond_ter192 => Ssecond,
in_Sthird_ter192 => Sthird,
in_key_up_ter192 => key_up,
in_key_down_ter192 => key_down,
out1_ter192 => to_encr_reg128(127 downto 96),
out2_ter192 => to_encr_reg128(95 downto 64),
out3_ter192 => to_encr_reg128(63 downto 32),
out4_ter192 => to_encr_reg128(31 downto 0)
);
encr_reg: reg128
port map ( in_reg128 => to_encr_reg128,
out_reg128 => to_demux,
enable_reg128 => enable_encr_reg,
reset_reg128 => reset,
clk_reg128 => clk );
output_demux: demux128
port map ( in_demux128 => to_demux,
out1_demux128 => to_output_whit_xors,
out2_demux128 => to_mux,
selection_demux128 => demux_selection );
-- don't forget the last swap !!!
from_xors_to_tdo(127 downto 96) <= K4 XOR to_output_whit_xors(63 downto 32);
from_xors_to_tdo(95 downto 64) <= K5 XOR to_output_whit_xors(31 downto 0);
from_xors_to_tdo(63 downto 32) <= K6 XOR to_output_whit_xors(127 downto 96);
from_xors_to_tdo(31 downto 0) <= K7 XOR to_output_whit_xors(95 downto 64);
taking_the_output: twofish_data_output
port map (
in_tdo => from_xors_to_tdo,
out_tdo => output_data
);
-- we create the clock
clk <= not clk after 50 ns; -- period 100 ns
vt_proc: process
variable pt_f, -- plaintext input from file
ct_f : line; -- ciphertext from file
variable pt_v, -- plaintext vector input
ct_v : std_logic_vector(127 downto 0); -- ciphertext vector
variable counter : integer range 1 to 129 := 1; -- counts the encryptions
variable round : integer range 1 to 16 := 1; -- holds the rounds of encryption
begin
-- key stays fixed to zero
twofish_key <= (others => '0');
while not endfile(input_file) loop
readline(input_file, pt_f);
readline(input_file,ct_f);
hread(pt_f,pt_v);
hread(ct_f,ct_v);
input_data <= pt_v;
wait for 25 ns;
reset <= '1';
wait for 50 ns;
reset <= '0';
mux_selection <= '0';
demux_selection <= '1';
enable_encr_reg <= '0';
enable_round_reg <= '0';
wait for 50 ns;
enable_round_reg <= '1';
wait for 50 ns;
enable_round_reg <= '0';
-- the first round
even_number <= "00001000"; -- 8
odd_number <= "00001001"; -- 9
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
demux_selection <= '1';
mux_selection <= '1';
-- the rest 15 rounds
for round in 1 to 15 loop
even_number <= conv_std_logic_vector(((round*2)+8), 8);
odd_number <= conv_std_logic_vector(((round*2)+9), 8);
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
end loop;
-- taking final results
demux_selection <= '0';
wait for 25 ns;
assert (ct_v = output_data) report "file entry and encryption result DO NOT match!!! :( " severity failure;
assert (ct_v /= output_data) report "Encryption I=" & to_text(counter) &" OK" severity note;
counter := counter+1;
hwrite(ct_f,output_data);
hwrite(pt_f,pt_v);
writeline(output_file,pt_f);
writeline(output_file,ct_f);
end loop;
assert false report "***** Variable Text Known Answer Test with 192 bits key size ended succesfully! :) *****" severity failure;
end process vt_proc;
end vt_encryption192_testbench_arch;
| gpl-2.0 | 4cfd3c586a559dcf715a03befe610258 | 0.649689 | 2.69201 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/builtin/builtin_extdepth_low_latency.vhd | 5 | 43,742 | `protect begin_protected
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| apache-2.0 | 52cdcd25a5ed8814f7f804c52fccef5c | 0.949819 | 1.825702 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/srl_fifo3.vhd | 15 | 67,496 | -------------------------------------------------------------------------------
-- $Id: srl_fifo3.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo3 - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
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-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
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-- ** purpose. **
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-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo3.vhd
--
-- Description: same as srl_fifo except the Addr port has the correct bit
-- ordering, there is a true FIFO_Empty port, and the C_DEPTH
-- generic actually controlls how many elements the fifo will
-- hold (up to 16). includes an assertion statement to check
-- that C_DEPTH is less than or equal to 16. changed
-- C_DATA_BITS to C_DWIDTH and changed it from natural to
-- positive (the width should be 1 or greater, zero width
-- didn't make sense to me!). Changed C_DEPTH from natural
-- to positive (zero elements doesn't make sense).
-- The Addr port in srl_fifo has the bits reversed which
-- made it more difficult to use. C_DEPTH was not used in
-- srl_fifo. Data_Exists is delayed by one clock so it is
-- not usefull for generating an empty flag. FIFO_Empty is
-- generated directly from the address, the same way that
-- FIFO_Full is generated.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo3.vhd
--
-------------------------------------------------------------------------------
-- Author: jam
--
-- History:
-- JAM 2002-02-02 First Version - modified from original srl_fifo
--
-- DCW 2002-03-12 Structural implementation of synchronous reset for
-- Data_Exists DFF (using FDR)
--
-- JAM 2002-04-12 Added C_XON generic for mixed vhdl/verilog sims
--
-- als 2002-04-18 Added default for XON generic in SRL16E, FDRE, and FDR
-- component declarations
--
-- JAM 2002-05-01 Changed FIFO_Empty output from buffer_Empty, which had
-- a clock delay, to the not of data_Exists_I, which
-- doesn't have any delay
--
-- DCW 2004-10-15 Changed unisim.all to unisim.vcomponents.
-- Added C_FAMILY generic.
-- Added C_AWIDTH generic.
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library proc_common_v4_0;
use proc_common_v4_0.all;
use proc_common_v4_0.family.all;
library unisim;
use unisim.vcomponents.all;
entity srl_fifo3 is
generic (
C_FAMILY : string := "virtex4"; -- latest and greatest
C_DWIDTH : positive := 8; -- changed to positive
C_AWIDTH : positive := 4; -- changed to positive
C_DEPTH : positive := 16 -- changed to positive
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
Data_Exists : out std_logic;
Addr : out std_logic_vector(0 to C_AWIDTH-1)
);
end entity srl_fifo3;
architecture imp of srl_fifo3 is
------------------------------------------------------------------------------
-- Architecture BEGIN
------------------------------------------------------------------------------
begin
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- GENERATE FOR C_DEPTH LESS THAN 17
------------------------------------------------------------------------------
------------------------------------------------------------------------------
C_DEPTH_LT_17 : if (C_DEPTH < 17) generate
--------------------------------------------------------------------------
-- Constant Declarations
--------------------------------------------------------------------------
-- convert C_DEPTH to a std_logic_vector so FIFO_Full can be generated
-- based on the selected depth rather than fixed at 16
constant DEPTH : std_logic_vector(0 to 3) :=
conv_std_logic_vector(C_DEPTH-1,4);
--------------------------------------------------------------------------
-- Signal Declarations
--------------------------------------------------------------------------
signal addr_i : std_logic_vector(0 to 3);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic;
signal data_Exists_I : std_logic;
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to 3);
signal sum_A : std_logic_vector(0 to 3);
signal addr_cy : std_logic_vector(0 to 4);
--------------------------------------------------------------------------
-- Component Declarations
--------------------------------------------------------------------------
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic
);
end component SRL16E;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic
);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic
);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic
);
end component;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
component FDR is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDR;
--------------------------------------------------------------------------
-- Begin for Generate
--------------------------------------------------------------------------
begin
--------------------------------------------------------------------------
-- Depth check and assertion
--------------------------------------------------------------------------
-- C_DEPTH is positive so that ensures the fifo is at least 1 element deep
-- make sure it is not greater than 16 locations deep
-- pragma translate_off
assert C_DEPTH <= 16
report "SRL Fifo's must be 16 or less elements deep"
severity FAILURE;
-- pragma translate_on
--------------------------------------------------------------------------
-- Concurrent Signal Assignments
--------------------------------------------------------------------------
-- since srl16 address is 3 downto 0 need to compare individual bits
-- didn't muck with addr_i since the basic addressing works - Addr output
-- is generated correctly below
buffer_Full <= '1' when (addr_i(0) = DEPTH(3) and
addr_i(1) = DEPTH(2) and
addr_i(2) = DEPTH(1) and
addr_i(3) = DEPTH(0) ) else '0';
FIFO_Full <= buffer_Full;
buffer_Empty <= '1' when (addr_i = "0000") else '0';
FIFO_Empty <= not data_Exists_I; -- generate a true empty flag with no delay
-- was buffer_Empty, which had a clock dly
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
Data_Exists <= data_Exists_I;
valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
addr_cy(0) <= valid_Write;
--------------------------------------------------------------------------
-- Data Exists DFF Instance
--------------------------------------------------------------------------
DATA_EXISTS_DFF : FDR
port map (
Q => data_Exists_I, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists, -- [in std_logic]
R => Reset -- [in std_logic]
);
--------------------------------------------------------------------------
-- GENERATE ADDRESS COUNTERS
--------------------------------------------------------------------------
Addr_Counters : for i in 0 to 3 generate
hsum_A(i) <= (FIFO_Read xor addr_i(i)) and
(FIFO_Write or not buffer_Empty);
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(i), -- [in std_logic]
CI => addr_cy(i), -- [in std_logic]
S => hsum_A(i), -- [in std_logic]
LO => addr_cy(i+1) -- [out std_logic]
);
XORCY_I : XORCY
port map (
LI => hsum_A(i), -- [in std_logic]
CI => addr_cy(i), -- [in std_logic]
O => sum_A(i) -- [out std_logic]
);
FDRE_I : FDRE
port map (
Q => addr_i(i), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_i, -- [in std_logic]
D => sum_A(i), -- [in std_logic]
R => Reset -- [in std_logic]
);
end generate Addr_Counters;
--------------------------------------------------------------------------
-- GENERATE FIFO RAM
--------------------------------------------------------------------------
FIFO_RAM : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map ( INIT => x"0000" )
-- pragma translate_on
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i(0), -- [in std_logic]
A1 => addr_i(1), -- [in std_logic]
A2 => addr_i(2), -- [in std_logic]
A3 => addr_i(3), -- [in std_logic]
Q => Data_Out(I) -- [out std_logic]
);
end generate FIFO_RAM;
--------------------------------------------------------------------------
-- INT_ADDR_PROCESS
--------------------------------------------------------------------------
-- This process assigns the internal address to the output port
--------------------------------------------------------------------------
-- modified the process to flip the bits since the address bits from
-- the srl16 are 3 downto 0 and Addr needs to be 0 to 3
INT_ADDR_PROCESS:process (addr_i)
begin
for i in Addr'range
loop
Addr(i) <= addr_i(3 - i); -- flip the bits to account
end loop; -- for srl16 addr
end process;
end generate;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- GENERATE FOR C_DEPTH GREATER THAN 16, LESS THAN 32,
-- AND VIRTEX-E AND OLDER FAMILIES
------------------------------------------------------------------------------
------------------------------------------------------------------------------
C_DEPTH_16_32_VE : if ( ( (C_DEPTH > 16) and (C_DEPTH < 33) ) and
( equalIgnoreCase(C_FAMILY,"virtex") or
equalIgnoreCase(C_FAMILY,"virtexe") or
equalIgnoreCase(C_FAMILY,"spartan3e") or
equalIgnoreCase(C_FAMILY,"spartan3") ) )
generate
--------------------------------------------------------------------------
-- Constant Declarations
--------------------------------------------------------------------------
--------------------------------------------------------------------------
-- Signal Declarations
--------------------------------------------------------------------------
signal addr_i : std_logic_vector(0 to 4);
signal addr_i_1 : std_logic_vector(3 downto 0);
signal buffer_Full_1 : std_logic;
signal next_buffer_Full_1 : std_logic;
signal next_Data_Exists_1 : std_logic;
signal data_Exists_I_1 : std_logic;
signal FIFO_Write_1 : std_logic;
signal Data_In_1 : std_logic_vector(0 to C_DWIDTH-1);
signal FIFO_Read_1 : std_logic;
signal Data_Out_1 : std_logic_vector(0 to C_DWIDTH-1);
signal addr_i_2 : std_logic_vector(3 downto 0);
signal buffer_Full_2 : std_logic;
signal next_buffer_Full_2 : std_logic;
signal next_Data_Exists_2 : std_logic;
signal data_Exists_I_2 : std_logic;
signal FIFO_Write_2 : std_logic;
signal Data_In_2 : std_logic_vector(0 to C_DWIDTH-1);
signal FIFO_Read_2 : std_logic;
signal Data_Out_2 : std_logic_vector(0 to C_DWIDTH-1);
--------------------------------------------------------------------------
-- Component Declarations
--------------------------------------------------------------------------
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic
);
end component SRL16E;
component FDR is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDR;
--------------------------------------------------------------------------
-- Begin for Generate
--------------------------------------------------------------------------
begin
--------------------------------------------------------------------------
-- Concurrent Signal Assignments
--------------------------------------------------------------------------
next_Data_Exists_1 <= ((FIFO_Write and not(FIFO_Read) and not(addr_i_1(0))
and not(addr_i_1(1)) and not(addr_i_1(2))
and not(addr_i_1(3))) or data_Exists_I_1) and not
(FIFO_Read and not(FIFO_Write) and not(addr_i_1(0))
and not(addr_i_1(1)) and not(addr_i_1(2))
and not(addr_i_1(3)));
FIFO_Write_1 <= FIFO_Write;
FIFO_Write_2 <= FIFO_Write;
FIFO_Read_1 <= FIFO_Read;
FIFO_Read_2 <= FIFO_Read;
data_Exists <= data_Exists_I_1;
Data_Out <= Data_Out_2 when (data_Exists_I_2 = '1') else Data_Out_1;
Data_In_2 <= Data_Out_1;
Data_In_1 <= Data_In;
FIFO_Full <= buffer_Full_2;
next_buffer_Full_1 <= '1' when (addr_i_1 = "1111") else '0';
next_Data_Exists_2 <= ((FIFO_Write and not(FIFO_Read) and not(addr_i_2(0))
and not(addr_i_2(1)) and not(addr_i_2(2)) and not
(addr_i_2(3)) and (buffer_Full_1)) or data_Exists_I_2)
and not(FIFO_Read and not(FIFO_Write) and
not(addr_i_2(0)) and not(addr_i_2(1)) and
not(addr_i_2(2)) and not(addr_i_2(3)));
next_buffer_Full_2 <= '1' when (addr_i_2 = "1111") else '0';
FIFO_Empty <= not next_Data_Exists_1 and not next_Data_Exists_2;
-- generate a true empty flag with no delay
-- was buffer_Empty, which had a clock dly
--------------------------------------------------------------------------
-- Address Processes
--------------------------------------------------------------------------
ADDRS_1 : process (Clk)
begin
if (clk'event and clk = '1') then
if (Reset = '1') then
addr_i_1 <= "0000";
elsif ((buffer_Full_1='0') and (FIFO_Write='1') and
(FIFO_Read='0') and (data_Exists_I_1='1')) then
addr_i_1 <= addr_i_1 + 1;
elsif (not(addr_i_1 = "0000") and (FIFO_Read='1') and
(FIFO_Write='0') and (data_Exists_I_2='0')) then
addr_i_1 <= addr_i_1 - 1;
else
null;
end if;
end if;
end process;
ADDRS_2 : process (Clk)
begin
if (clk'event and clk = '1') then
if (Reset = '1') then
addr_i_2 <= "0000";
elsif ((buffer_Full_2='0') and (FIFO_Write = '1') and
(FIFO_Read = '0') and (buffer_Full_1 = '1') and
(data_Exists_I_2='1')) then
addr_i_2 <= addr_i_2 + 1;
elsif (not(addr_i_2 = "0000") and (FIFO_Read = '1') and
(FIFO_Write = '0')) then
addr_i_2 <= addr_i_2 - 1;
else
null;
end if;
end if;
end process;
ADDR_OUT : process (addr_i_1, addr_i_2, data_Exists_I_2)
begin
if (data_Exists_I_2 = '0') then
Addr <= '0' & addr_i_1;
else
Addr <= '1' & addr_i_2;
end if;
end process;
--------------------------------------------------------------------------
-- Data Exists Instances
--------------------------------------------------------------------------
DATA_EXISTS_1_DFF : FDR
port map (
Q => data_Exists_I_1, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists_1, -- [in std_logic]
R => Reset -- [in std_logic]
);
DATA_EXISTS_2_DFF : FDR
port map (
Q => data_Exists_I_2, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists_2, -- [in std_logic]
R => Reset -- [in std_logic]
);
--------------------------------------------------------------------------
-- Buffer Full Instances
--------------------------------------------------------------------------
BUFFER_FULL_1_DFF : FDR
port map (
Q => buffer_Full_1, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_buffer_Full_1, -- [in std_logic]
R => Reset -- [in std_logic]
);
BUFFER_FULL_2_DFF : FDR
port map (
Q => buffer_Full_2, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_buffer_Full_2, -- [in std_logic]
R => Reset -- [in std_logic]
);
--------------------------------------------------------------------------
-- GENERATE FIFO RAMS
--------------------------------------------------------------------------
FIFO_RAM_1 : for i in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map ( INIT => x"0000" )
-- pragma translate_on
port map (
CE => FIFO_Write_1, -- [in std_logic]
D => Data_In_1(i), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i_1(0), -- [in std_logic]
A1 => addr_i_1(1), -- [in std_logic]
A2 => addr_i_1(2), -- [in std_logic]
A3 => addr_i_1(3), -- [in std_logic]
Q => Data_Out_1(i) -- [out std_logic]
);
end generate FIFO_RAM_1;
FIFO_RAM_2 : for i in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map ( INIT => x"0000" )
-- pragma translate_on
port map (
CE => FIFO_Write_2, -- [in std_logic]
D => Data_In_2(i), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i_2(0), -- [in std_logic]
A1 => addr_i_2(1), -- [in std_logic]
A2 => addr_i_2(2), -- [in std_logic]
A3 => addr_i_2(3), -- [in std_logic]
Q => Data_Out_2(i) -- [out std_logic]
);
end generate FIFO_RAM_2;
end generate;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- GENERATE FOR C_DEPTH GREATER THAN 16, LESS THAN 32,
-- AND VIRTEX-2 AND NEWER FAMILIES
------------------------------------------------------------------------------
------------------------------------------------------------------------------
C_DEPTH_16_32_V2 : if ( ( (C_DEPTH > 16) and (C_DEPTH < 33) ) and
( equalIgnoreCase(C_FAMILY,"virtex2") or
equalIgnoreCase(C_FAMILY,"virtex2p") or
equalIgnoreCase(C_FAMILY,"virtex4") ) )
generate
--------------------------------------------------------------------------
-- Constant Declarations
--------------------------------------------------------------------------
constant DEPTH : std_logic_vector(0 to 4) :=
conv_std_logic_vector(C_DEPTH-1,5);
--------------------------------------------------------------------------
-- Signal Declarations
--------------------------------------------------------------------------
signal addr_i : std_logic_vector(0 to 4);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic;
signal data_Exists_I : std_logic;
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to 4);
signal sum_A : std_logic_vector(0 to 4);
signal addr_cy : std_logic_vector(0 to 5);
signal D_Out_ls : std_logic_vector(0 to C_DWIDTH-1);
signal D_Out_ms : std_logic_vector(0 to C_DWIDTH-1);
signal q15 : std_logic_vector(0 to C_DWIDTH-1);
--------------------------------------------------------------------------
-- Component Declarations
--------------------------------------------------------------------------
component SRL16E is
-- pragma translate_off
generic ( INIT : bit_vector := X"0000" );
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic
);
end component SRL16E;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic
);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic
);
end component;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
component FDR is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDR;
component MUXF5
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component;
component SRLC16E
-- pragma translate_off
generic ( INIT : bit_vector := X"0000" );
-- pragma translate_on
port (
Q : out std_logic;
Q15 : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
CE : in std_logic;
CLK : in std_logic;
D : in std_logic
);
end component;
component LUT3
generic( INIT : bit_vector := X"0" );
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic
);
end component;
--------------------------------------------------------------------------
-- Begin for Generate
--------------------------------------------------------------------------
begin
--------------------------------------------------------------------------
-- Concurrent Signal Assignments
--------------------------------------------------------------------------
--buffer_Full <= '1' when (addr_i = "11111") else '0';
buffer_Full <= '1' when (addr_i(0) = DEPTH(4) and
addr_i(1) = DEPTH(3) and
addr_i(2) = DEPTH(2) and
addr_i(3) = DEPTH(1) and
addr_i(4) = DEPTH(0) ) else '0';
FIFO_Full <= buffer_Full;
buffer_Empty <= '1' when (addr_i = "00000") else '0';
FIFO_Empty <= not data_Exists_I; -- generate a true empty flag with no delay
-- was buffer_Empty, which had a clock dly
Data_Exists <= data_Exists_I;
addr_cy(0) <= valid_Write;
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
--------------------------------------------------------------------------
-- Data Exists DFF Instance
--------------------------------------------------------------------------
DATA_EXISTS_DFF : FDR
port map (
Q => data_Exists_i, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists, -- [in std_logic]
R => Reset -- [in std_logic]
);
--------------------------------------------------------------------------
-- Valid Write LUT Instance
--------------------------------------------------------------------------
-- XST CR183399 WA
-- valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
VALID_WRITE_I : LUT3
generic map ( INIT => X"8A" )
port map (
O => valid_Write,
I0 => FIFO_Write,
I1 => FIFO_Read,
I2 => buffer_Full
);
--END XST WA for CR183399
--------------------------------------------------------------------------
-- GENERATE ADDRESS COUNTERS
--------------------------------------------------------------------------
ADDR_COUNTERS : for i in 0 to 4 generate
hsum_A(I) <= (FIFO_Read xor addr_i(i)) and
(FIFO_Write or not buffer_Empty);
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(i), -- [in std_logic]
CI => addr_cy(i), -- [in std_logic]
S => hsum_A(i), -- [in std_logic]
LO => addr_cy(i+1) -- [out std_logic]
);
XORCY_I : XORCY
port map (
LI => hsum_A(i), -- [in std_logic]
CI => addr_cy(i), -- [in std_logic]
O => sum_A(i) -- [out std_logic]
);
FDRE_I : FDRE
port map (
Q => addr_i(i), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_i, -- [in std_logic]
D => sum_A(i), -- [in std_logic]
R => Reset -- [in std_logic]
);
end generate Addr_Counters;
--------------------------------------------------------------------------
-- GENERATE FIFO RAMS
--------------------------------------------------------------------------
FIFO_RAM : for i in 0 to C_DWIDTH-1 generate
SRLC16E_LS : SRLC16E
-- pragma translate_off
generic map ( INIT => x"0000" )
-- pragma translate_on
port map (
Q => D_Out_ls(i),
Q15 => q15(i),
A0 => addr_i(0),
A1 => addr_i(1),
A2 => addr_i(2),
A3 => addr_i(3),
CE => valid_Write,
CLK => Clk,
D => Data_In(i)
);
SRL16E_MS : SRL16E
-- pragma translate_off
generic map ( INIT => x"0000" )
-- pragma translate_on
port map (
CE => valid_Write,
D => q15(i),
Clk => Clk,
A0 => addr_i(0),
A1 => addr_i(1),
A2 => addr_i(2),
A3 => addr_i(3),
Q => D_Out_ms(i)
);
MUXF5_I: MUXF5
port map (
O => Data_Out(i), --[out]
I0 => D_Out_ls(i), --[in]
I1 => D_Out_ms(i), --[in]
S => addr_i(4) --[in]
);
end generate FIFO_RAM;
--------------------------------------------------------------------------
-- INT_ADDR_PROCESS
--------------------------------------------------------------------------
-- This process assigns the internal address to the output port
--------------------------------------------------------------------------
INT_ADDR_PROCESS:process (addr_i)
begin -- process
for i in Addr'range
loop
Addr(i) <= addr_i(4 - i); --flip the bits to account for srl16 addr
end loop;
end process;
end generate;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- GENERATE FOR C_DEPTH GREATER THAN 32, LESS THAN 65,
-- AND VIRTEX-E AND OLDER FAMILIES
------------------------------------------------------------------------------
------------------------------------------------------------------------------
C_DEPTH_32_64_VE : if ( (C_DEPTH > 32) and (C_DEPTH < 65) and
( equalIgnoreCase(C_FAMILY,"virtex") or
equalIgnoreCase(C_FAMILY,"virtexe") or
equalIgnoreCase(C_FAMILY,"spartan3e") or
equalIgnoreCase(C_FAMILY,"spartan3") ) )
generate
--------------------------------------------------------------------------
-- Constant Declarations
--------------------------------------------------------------------------
--------------------------------------------------------------------------
-- Signal Declarations
--------------------------------------------------------------------------
signal addr_i_1 : std_logic_vector(3 downto 0);
signal buffer_Full_1 : std_logic;
signal next_buffer_Full_1 : std_logic;
signal next_Data_Exists_1 : std_logic;
signal data_Exists_I_1 : std_logic;
signal FIFO_Write_1 : std_logic;
signal Data_In_1 : std_logic_vector(0 to C_DWIDTH-1);
signal FIFO_Read_1 : std_logic;
signal Data_Out_1 : std_logic_vector(0 to C_DWIDTH-1);
signal addr_i_2 : std_logic_vector(3 downto 0);
signal buffer_Full_2 : std_logic;
signal next_buffer_Full_2 : std_logic;
signal next_Data_Exists_2 : std_logic;
signal data_Exists_I_2 : std_logic;
signal FIFO_Write_2 : std_logic;
signal Data_In_2 : std_logic_vector(0 to C_DWIDTH-1);
signal FIFO_Read_2 : std_logic;
signal Data_Out_2 : std_logic_vector(0 to C_DWIDTH-1);
signal addr_i_3 : std_logic_vector(3 downto 0);
signal buffer_Full_3 : std_logic;
signal next_buffer_Full_3 : std_logic;
signal next_Data_Exists_3 : std_logic;
signal data_Exists_I_3 : std_logic;
signal FIFO_Write_3 : std_logic;
signal Data_In_3 : std_logic_vector(0 to C_DWIDTH-1);
signal FIFO_Read_3 : std_logic;
signal Data_Out_3 : std_logic_vector(0 to C_DWIDTH-1);
signal addr_i_4 : std_logic_vector(3 downto 0);
signal buffer_Full_4 : std_logic;
signal next_buffer_Full_4 : std_logic;
signal next_Data_Exists_4 : std_logic;
signal data_Exists_I_4 : std_logic;
signal FIFO_Write_4 : std_logic;
signal Data_In_4 : std_logic_vector(0 to C_DWIDTH-1);
signal FIFO_Read_4 : std_logic;
signal Data_Out_4 : std_logic_vector(0 to C_DWIDTH-1);
--------------------------------------------------------------------------
-- Component Declarations
--------------------------------------------------------------------------
component SRL16E is
-- pragma translate_off
generic ( INIT : bit_vector := X"0000" );
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic
);
end component SRL16E;
component FDR is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDR;
--------------------------------------------------------------------------
-- Begin for Generate
--------------------------------------------------------------------------
begin
--------------------------------------------------------------------------
-- Concurrent Signal Assignments
--------------------------------------------------------------------------
FIFO_Write_1 <= FIFO_Write;
FIFO_Read_1 <= FIFO_Read;
FIFO_Write_2 <= FIFO_Write and buffer_Full_1;
FIFO_Read_2 <= FIFO_Read;
FIFO_Write_3 <= FIFO_Write and buffer_Full_2;
FIFO_Read_3 <= FIFO_Read;
FIFO_Write_4 <= FIFO_Write and buffer_Full_3;
FIFO_Read_4 <= FIFO_Read;
Data_In_1 <= Data_In;
Data_In_2 <= Data_Out_1;
Data_In_3 <= Data_Out_2;
Data_In_4 <= Data_Out_3;
FIFO_Full <= buffer_Full_4;
next_buffer_Full_1 <= '1' when (addr_i_1 = "1111") else '0';
next_buffer_Full_2 <= '1' when (addr_i_2 = "1111") else '0';
next_buffer_Full_3 <= '1' when (addr_i_3 = "1111") else '0';
next_buffer_Full_4 <= '1' when (addr_i_4 = "1111") else '0';
next_Data_Exists_1 <= ((FIFO_Write and not(FIFO_Read) and not(addr_i_1(0))
and not(addr_i_1(1)) and not(addr_i_1(2))
and not(addr_i_1(3))) or data_Exists_I_1) and
not(FIFO_Read and not(FIFO_Write)
and not(addr_i_1(0)) and not(addr_i_1(1)) and not
(addr_i_1(2)) and not(addr_i_1(3)));
next_Data_Exists_2 <= ((FIFO_Write and not(FIFO_Read) and not(addr_i_2(0))
and not(addr_i_2(1)) and not(addr_i_2(2))
and not(addr_i_2(3)) and (buffer_Full_1)) or
data_Exists_I_2) and not(FIFO_Read and not(FIFO_Write)
and not(addr_i_2(0)) and not(addr_i_2(1)) and not
(addr_i_2(2)) and not(addr_i_2(3)));
next_Data_Exists_3 <= ((FIFO_Write and not(FIFO_Read) and not(addr_i_3(0))
and not(addr_i_3(1)) and not(addr_i_3(2)) and not
(addr_i_3(3)) and (buffer_Full_2)) or data_Exists_I_3)
and not(FIFO_Read and not(FIFO_Write) and not
(addr_i_3(0)) and not(addr_i_3(1)) and not
(addr_i_3(2)) and not(addr_i_3(3)));
next_Data_Exists_4 <= ((FIFO_Write and not(FIFO_Read) and not(addr_i_4(0))
and not(addr_i_4(1)) and not(addr_i_4(2)) and not
(addr_i_4(3)) and (buffer_Full_3)) or data_Exists_I_4)
and not(FIFO_Read and not(FIFO_Write) and
not(addr_i_4(0)) and not(addr_i_4(1)) and
not(addr_i_4(2)) and not(addr_i_4(3)));
data_Exists <= data_Exists_I_1;
Data_Out <= Data_Out_4 when (data_Exists_I_4 = '1') else
Data_Out_3 when (data_Exists_I_3 = '1') else
Data_Out_2 when (data_Exists_I_2 = '1') else
Data_Out_1;
FIFO_Empty <= not data_Exists_I_1;
--------------------------------------------------------------------------
-- Address Processes
--------------------------------------------------------------------------
ADDRS_1 : process (Clk)
begin
if (clk'event and clk = '1') then
if (Reset = '1') then
addr_i_1 <= "0000";
elsif ((buffer_Full_1='0') and (FIFO_Write='1') and
(FIFO_Read='0') and (data_Exists_I_1='1')) then
addr_i_1 <= addr_i_1 + 1;
elsif (not(addr_i_1 = "0000") and (FIFO_Read='1') and
(FIFO_Write='0') and (data_Exists_I_2='0')) then
addr_i_1 <= addr_i_1 - 1;
else
null;
end if;
end if;
end process;
ADDRS_2 : process (Clk)
begin
if (clk'event and clk = '1') then
if (Reset = '1') then
addr_i_2 <= "0000";
elsif ((buffer_Full_2='0') and (FIFO_Write = '1') and
(FIFO_Read = '0') and (buffer_Full_1 = '1') and
(data_Exists_I_2='1')) then
addr_i_2 <= addr_i_2 + 1;
elsif (not(addr_i_2 = "0000") and (FIFO_Read = '1') and
(FIFO_Write = '0') and (data_Exists_I_3='0')) then
addr_i_2 <= addr_i_2 - 1;
else
null;
end if;
end if;
end process;
ADDRS_3 : process (Clk)
begin
if (clk'event and clk = '1') then
if (Reset = '1') then
addr_i_3 <= "0000";
elsif ((buffer_Full_3='0') and (FIFO_Write = '1') and
(FIFO_Read = '0') and (buffer_Full_2 = '1') and
(data_Exists_I_3='1')) then
addr_i_3 <= addr_i_3 + 1;
elsif (not(addr_i_3 = "0000") and (FIFO_Read = '1') and
(FIFO_Write = '0') and (data_Exists_I_4='0')) then
addr_i_3 <= addr_i_3 - 1;
else
null;
end if;
end if;
end process;
ADDRS_4 : process (Clk)
begin
if (clk'event and clk = '1') then
if (Reset = '1') then
addr_i_4 <= "0000";
elsif ((buffer_Full_4='0') and (FIFO_Write = '1') and
(FIFO_Read = '0') and (buffer_Full_3 = '1') and
(data_Exists_I_4='1')) then
addr_i_4 <= addr_i_4 + 1;
elsif (not(addr_i_4 = "0000") and (FIFO_Read = '1') and
(FIFO_Write = '0')) then
addr_i_4 <= addr_i_4 - 1;
else
null;
end if;
end if;
end process;
ADDR_OUT : process (addr_i_1, addr_i_2, addr_i_3, addr_i_4,
data_Exists_I_2, data_Exists_I_3, data_Exists_I_4)
begin
if ( (data_Exists_I_2 = '0') and
(data_Exists_I_3 = '0') and
(data_Exists_I_4 = '0') )
then
Addr <= "00" & addr_i_1;
elsif ( (data_Exists_I_3 = '0') and
(data_Exists_I_4 = '0') )
then
Addr <= "01" & addr_i_2;
elsif ( (data_Exists_I_4 = '0') )
then
Addr <= "10" & addr_i_3;
else
Addr <= "11" & addr_i_4;
end if;
end process;
--------------------------------------------------------------------------
-- Data Exists Instances
--------------------------------------------------------------------------
DATA_EXISTS_1_DFF : FDR
port map (
Q => data_Exists_I_1, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists_1, -- [in std_logic]
R => Reset -- [in std_logic]
);
DATA_EXISTS_2_DFF : FDR
port map (
Q => data_Exists_I_2, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists_2, -- [in std_logic]
R => Reset -- [in std_logic]
);
DATA_EXISTS_3_DFF : FDR
port map (
Q => data_Exists_I_3, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists_3, -- [in std_logic]
R => Reset -- [in std_logic]
);
DATA_EXISTS_4_DFF : FDR
port map (
Q => data_Exists_I_4, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists_4, -- [in std_logic]
R => Reset -- [in std_logic]
);
--------------------------------------------------------------------------
-- Buffer Full Instances
--------------------------------------------------------------------------
BUFFER_FULL_1_DFF : FDR
port map (
Q => buffer_Full_1, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_buffer_Full_1, -- [in std_logic]
R => Reset -- [in std_logic]
);
BUFFER_FULL_2_DFF : FDR
port map (
Q => buffer_Full_2, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_buffer_Full_2, -- [in std_logic]
R => Reset -- [in std_logic]
);
BUFFER_FULL_3_DFF : FDR
port map (
Q => buffer_Full_3, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_buffer_Full_3, -- [in std_logic]
R => Reset -- [in std_logic]
);
BUFFER_FULL_4_DFF : FDR
port map (
Q => buffer_Full_4, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_buffer_Full_4, -- [in std_logic]
R => Reset -- [in std_logic]
);
--------------------------------------------------------------------------
-- GENERATE FIFO RAMS
--------------------------------------------------------------------------
FIFO_RAM_1 : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map ( INIT => x"0000" )
-- pragma translate_on
port map (
CE => FIFO_Write_1, -- [in std_logic]
D => Data_In_1(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i_1(0), -- [in std_logic]
A1 => addr_i_1(1), -- [in std_logic]
A2 => addr_i_1(2), -- [in std_logic]
A3 => addr_i_1(3), -- [in std_logic]
Q => Data_Out_1(I) -- [out std_logic]
);
end generate FIFO_RAM_1;
FIFO_RAM_2 : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map ( INIT => x"0000" )
-- pragma translate_on
port map (
CE => FIFO_Write_2, -- [in std_logic]
D => Data_In_2(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i_2(0), -- [in std_logic]
A1 => addr_i_2(1), -- [in std_logic]
A2 => addr_i_2(2), -- [in std_logic]
A3 => addr_i_2(3), -- [in std_logic]
Q => Data_Out_2(I) -- [out std_logic]
);
end generate FIFO_RAM_2;
FIFO_RAM_3 : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map ( INIT => x"0000" )
-- pragma translate_on
port map (
CE => FIFO_Write_3, -- [in std_logic]
D => Data_In_3(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i_3(0), -- [in std_logic]
A1 => addr_i_3(1), -- [in std_logic]
A2 => addr_i_3(2), -- [in std_logic]
A3 => addr_i_3(3), -- [in std_logic]
Q => Data_Out_3(I) -- [out std_logic]
);
end generate FIFO_RAM_3;
FIFO_RAM_4 : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map ( INIT => x"0000" )
-- pragma translate_on
port map (
CE => FIFO_Write_4, -- [in std_logic]
D => Data_In_4(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i_4(0), -- [in std_logic]
A1 => addr_i_4(1), -- [in std_logic]
A2 => addr_i_4(2), -- [in std_logic]
A3 => addr_i_4(3), -- [in std_logic]
Q => Data_Out_4(I) -- [out std_logic]
);
end generate FIFO_RAM_4;
end generate;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- GENERATE FOR C_DEPTH GREATER THAN 32, LESS THAN 65,
-- AND VIRTEX-2 AND NEWER FAMILIES
------------------------------------------------------------------------------
------------------------------------------------------------------------------
C_DEPTH_32_64_V2 : if ( (C_DEPTH > 32) and (C_DEPTH < 65) and
( equalIgnoreCase(C_FAMILY,"virtex2") or
equalIgnoreCase(C_FAMILY,"virtex2p") or
equalIgnoreCase(C_FAMILY,"virtex4") ) )
generate
--------------------------------------------------------------------------
-- Constant Declarations
--------------------------------------------------------------------------
constant DEPTH : std_logic_vector(0 to 5) :=
conv_std_logic_vector(C_DEPTH-1,6);
--------------------------------------------------------------------------
-- Signal Declarations
--------------------------------------------------------------------------
signal addr_i : std_logic_vector(0 to 5);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic;
signal data_Exists_I : std_logic;
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to 5);
signal sum_A : std_logic_vector(0 to 5);
signal addr_cy : std_logic_vector(0 to 6);
signal D_Out_ls_1 : std_logic_vector(0 to C_DWIDTH-1);
signal D_Out_ls_2 : std_logic_vector(0 to C_DWIDTH-1);
signal D_Out_ls_3 : std_logic_vector(0 to C_DWIDTH-1);
signal D_Out_ms : std_logic_vector(0 to C_DWIDTH-1);
signal Data_O_ls : std_logic_vector(0 to C_DWIDTH-1);
signal Data_O_ms : std_logic_vector(0 to C_DWIDTH-1);
signal q15_1 : std_logic_vector(0 to C_DWIDTH-1);
signal q15_2 : std_logic_vector(0 to C_DWIDTH-1);
signal q15_3 : std_logic_vector(0 to C_DWIDTH-1);
--------------------------------------------------------------------------
-- Component Declarations
--------------------------------------------------------------------------
component SRL16E is
-- pragma translate_off
generic ( INIT : bit_vector := X"0000" );
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic
);
end component SRL16E;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic
);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic
);
end component;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
component FDR is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDR;
component MUXF5
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component;
component MUXF6
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component;
component SRLC16E
-- pragma translate_off
generic ( INIT : bit_vector := X"0000" );
-- pragma translate_on
port (
Q : out std_logic;
Q15 : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
CE : in std_logic;
CLK : in std_logic;
D : in std_logic
);
end component;
-- XST WA for CR183399
component LUT3
generic( INIT : bit_vector := X"0" );
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic
);
end component;
--------------------------------------------------------------------------
-- Begin for Generate
--------------------------------------------------------------------------
begin
--------------------------------------------------------------------------
-- Concurrent Signal Assignments
--------------------------------------------------------------------------
-- buffer_Full <= '1' when (addr_i = "11111") else '0';
buffer_Full <= '1' when (addr_i(0) = DEPTH(5) and
addr_i(1) = DEPTH(4) and
addr_i(2) = DEPTH(3) and
addr_i(3) = DEPTH(2) and
addr_i(4) = DEPTH(1) and
addr_i(5) = DEPTH(0)
) else '0';
FIFO_Full <= buffer_Full;
buffer_Empty <= '1' when (addr_i = "000000") else '0';
FIFO_Empty <= not data_Exists_I; -- generate a true empty flag with no delay
-- was buffer_Empty, which had a clock dly
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
Data_Exists <= data_Exists_I;
addr_cy(0) <= valid_Write;
--------------------------------------------------------------------------
-- Data Exists DFF Instance
--------------------------------------------------------------------------
Data_Exists_DFF : FDR
port map (
Q => data_Exists_I, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists, -- [in std_logic]
R => Reset -- [in std_logic]
);
--------------------------------------------------------------------------
-- Valid Write LUT Instance
--------------------------------------------------------------------------
-- XST CR183399 WA
-- valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
VALID_WRITE_I : LUT3
generic map ( INIT => X"8A" )
port map (
O => valid_Write, -- [out std_logic]
I0 => FIFO_Write, -- [in std_logic]
I1 => FIFO_Read, -- [in std_logic]
I2 => buffer_Full -- [in std_logic]
);
--END XST WA for CR183399
--------------------------------------------------------------------------
-- GENERATE ADDRESS COUNTERS
--------------------------------------------------------------------------
ADDR_COUNTERS : for i in 0 to 5 generate
hsum_A(I) <= (FIFO_Read xor addr_i(I)) and
(FIFO_Write or not buffer_Empty);
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(i), -- [in std_logic]
CI => addr_cy(i), -- [in std_logic]
S => hsum_A(i), -- [in std_logic]
LO => addr_cy(i+1) -- [out std_logic]
);
XORCY_I : XORCY
port map (
LI => hsum_A(i), -- [in std_logic]
CI => addr_cy(i), -- [in std_logic]
O => sum_A(i) -- [out std_logic]
);
FDRE_I : FDRE
port map (
Q => addr_i(i), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_i, -- [in std_logic]
D => sum_A(i), -- [in std_logic]
R => Reset -- [in std_logic]
);
end generate ADDR_COUNTERS;
--------------------------------------------------------------------------
-- GENERATE FIFO RAMS
--------------------------------------------------------------------------
FIFO_RAM : for i in 0 to C_DWIDTH-1 generate
SRLC16E_LS1 : SRLC16E
-- pragma translate_off
generic map ( INIT => x"0000" )
-- pragma translate_on
port map (
Q => D_Out_ls_1(i), --[out]
Q15 => q15_1(i), --[out]
A0 => addr_i(0), --[in]
A1 => addr_i(1), --[in]
A2 => addr_i(2), --[in]
A3 => addr_i(3), --[in]
CE => valid_Write, --[in]
CLK => Clk, --[in]
D => Data_In(i) --[in]
);
SRLC16E_LS2 : SRLC16E
-- pragma translate_off
generic map ( INIT => x"0000" )
-- pragma translate_on
port map (
Q => D_Out_ls_2(i), --[out]
Q15 => q15_2(i), --[out]
A0 => addr_i(0), --[in]
A1 => addr_i(1), --[in]
A2 => addr_i(2), --[in]
A3 => addr_i(3), --[in]
CE => valid_Write, --[in]
CLK => Clk, --[in]
D => q15_1(i) --[in]
);
MUXF5_LS: MUXF5
port map (
O => Data_O_LS(i), --[out]
I0 => D_Out_ls_1(I), --[in]
I1 => D_Out_ls_2(I), --[in]
S => addr_i(4) --[in]
);
SRLC16E_LS3 : SRLC16E
-- pragma translate_off
generic map ( INIT => x"0000" )
-- pragma translate_on
port map (
Q => D_Out_ls_3(i), --[out]
Q15 => q15_3(i), --[out]
A0 => addr_i(0), --[in]
A1 => addr_i(1), --[in]
A2 => addr_i(2), --[in]
A3 => addr_i(3), --[in]
CE => valid_Write, --[in]
CLK => Clk, --[in]
D => q15_2(i) --[in]
);
SRL16E_MS : SRL16E
-- pragma translate_off
generic map ( INIT => x"0000" )
-- pragma translate_on
port map (
CE => valid_Write, --[in]
D => q15_3(i), --[in]
Clk => Clk, --[in]
A0 => addr_i(0), --[in]
A1 => addr_i(1), --[in]
A2 => addr_i(2), --[in]
A3 => addr_i(3), --[in]
Q => D_Out_ms(I) --[out]
);
MUXF5_MS: MUXF5
port map (
O => Data_O_MS(i), --[out]
I0 => D_Out_ls_3(i), --[in]
I1 => D_Out_ms(i), --[in]
S => addr_i(4) --[in]
);
MUXF6_I: MUXF6
port map (
O => Data_out(i), --[out]
I0 => Data_O_ls(i), --[in]
I1 => Data_O_ms(i), --[in]
S => addr_i(5) --[in]
);
end generate FIFO_RAM;
--------------------------------------------------------------------------
-- INT_ADDR_PROCESS
--------------------------------------------------------------------------
-- This process assigns the internal address to the output port
--------------------------------------------------------------------------
INT_ADDR_PROCESS:process (addr_i)
begin
for i in Addr'range
loop
Addr(i) <= addr_i(5 - i); -- flip the bits to account for srl16 addr
end loop;
end process;
end generate;
end architecture imp;
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`protect end_protected
| apache-2.0 | 96c18f3ca9fe9a2fde5f4b344a90cf39 | 0.93997 | 1.849913 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-30bits_outputs31bits/4-MPEG-MV/metaheurísticas/mpegmv_femo.vhd | 1 | 2,927 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-13.07:45:36)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mpegmv_femo_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14: IN unsigned(0 TO 30);
output1, output2, output3: OUT unsigned(0 TO 31));
END mpegmv_femo_entity;
ARCHITECTURE mpegmv_femo_description OF mpegmv_femo_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register4: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register5: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register6: unsigned(0 TO 31) := "00000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
register2 := input2 * 2;
register3 := input3 * 3;
WHEN "00000010" =>
register1 := register1 + 5;
WHEN "00000011" =>
register1 := register2 + register1;
register2 := input4 * 6;
register3 := register3 + 8;
WHEN "00000100" =>
register1 := register2 + register1;
register2 := input5 * 9;
register4 := input6 * 10;
WHEN "00000101" =>
register1 := ((NOT register1) + 1) XOR register1;
register5 := input7 * 13;
output1 <= register2 + register3;
register2 := input8 * 15;
register3 := register4 + 17;
WHEN "00000110" =>
register3 := register5 + register3;
register2 := register2 + 19;
register4 := input9 * 20;
register5 := input10 * 21;
register6 := input11 * 22;
WHEN "00000111" =>
register3 := register5 + register3;
register5 := input12 * 23;
register2 := register6 + register2;
WHEN "00001000" =>
register2 := register5 + register2;
register5 := input13 * 24;
output2 <= register1(0 TO 15) & register3(0 TO 15);
WHEN "00001001" =>
register1 := register5 + 27;
WHEN "00001010" =>
register1 := register4 + register1;
register3 := input14 * 28;
WHEN "00001011" =>
register1 := register3 + register1;
WHEN "00001100" =>
register1 := ((NOT register1) + 1) XOR register1;
WHEN "00001101" =>
output3 <= register1(0 TO 15) & register2(0 TO 15);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mpegmv_femo_description; | gpl-3.0 | d430a69edc4504b008b462867eaf0f37 | 0.673044 | 3.25584 | false | false | false | false |
BBN-Q/APS2-Comms | src/tcp_demux.vhd | 1 | 5,203 | -- Cross from tcp clock domain
-- Demux tcp stream between AXI memory and CPLD
-- Packetize by adding tlast to stream
-- Adapt to 32bit wide data path
--
-- Original author: Colm Ryan
-- Copyright 2015, Raytheon BBN Technologies
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.tcp_bridge_pkg.all;
entity tcp_demux is
port (
clk : in std_logic;
rst : in std_logic;
clk_tcp : in std_logic;
rst_tcp : in std_logic;
--TCP stream receive
tcp_rx_tdata : in std_logic_vector(7 downto 0);
tcp_rx_tvalid : in std_logic;
tcp_rx_tready : out std_logic;
--rx stream passed to memory
memory_rx_tdata : out std_logic_vector(31 downto 0);
memory_rx_tvalid : out std_logic;
memory_rx_tready : in std_logic;
memory_rx_tlast : out std_logic;
--rx stream passed to CPLD bridge
cpld_rx_tdata : out std_logic_vector(31 downto 0);
cpld_rx_tvalid : out std_logic;
cpld_rx_tready : in std_logic;
cpld_rx_tlast : out std_logic
);
end entity;
architecture arch of tcp_demux is
signal tcp_rx_long_tdata : std_logic_vector(31 downto 0) := (others => '0');
signal tcp_rx_long_tvalid, tcp_rx_long_tready : std_logic := '0';
signal tcp_rx_long_cc_tdata : std_logic_vector(31 downto 0) := (others => '0');
signal tcp_rx_long_cc_tvalid, tcp_rx_long_cc_tready : std_logic := '0';
signal demux_tdata : std_logic_vector(31 downto 0) := (others => '0');
signal demux_tvalid, demux_tlast, demux_tready : std_logic := '0';
type main_state_t is (IDLE, LATCH_COMMAND, COUNT_PACKET);
signal main_state : main_state_t := IDLE;
signal cmd : std_logic_vector(31 downto 0);
alias cmd_rw_bit : std_logic is cmd(28);
alias cmd_cpld_bit : std_logic is cmd(29);
alias cmd_length : std_logic_vector(15 downto 0) is cmd(15 downto 0);
signal word_ct : unsigned(16 downto 0);
begin
--Adapt up to 32 bit wide data path
axis_adapter_inst : axis_adapter
generic map (
INPUT_DATA_WIDTH => 8,
INPUT_KEEP_WIDTH => 1,
OUTPUT_DATA_WIDTH => 32,
OUTPUT_KEEP_WIDTH => 4
)
port map (
clk => clk_tcp,
rst => rst_tcp,
input_axis_tdata => tcp_rx_tdata,
input_axis_tkeep(0) => '1',
input_axis_tvalid => tcp_rx_tvalid,
input_axis_tready => tcp_rx_tready,
input_axis_tlast => '0',
input_axis_tuser => '0',
output_axis_tdata => tcp_rx_long_tdata,
output_axis_tkeep => open,
output_axis_tvalid => tcp_rx_long_tvalid,
output_axis_tready => tcp_rx_long_tready,
output_axis_tlast => open,
output_axis_tuser => open
);
--Cross from the tcp clock domain
tcp2axi_fifo_inst : axis_async_fifo
generic map (
ADDR_WIDTH => 5,
DATA_WIDTH => 32
)
port map (
async_rst => rst,
input_clk => clk_tcp,
input_axis_tdata => byte_swap(tcp_rx_long_tdata),
input_axis_tvalid => tcp_rx_long_tvalid,
input_axis_tready => tcp_rx_long_tready,
input_axis_tlast => '0',
input_axis_tuser => '0',
output_clk => clk,
output_axis_tdata => tcp_rx_long_cc_tdata,
output_axis_tvalid => tcp_rx_long_cc_tvalid,
output_axis_tready => tcp_rx_long_cc_tready,
output_axis_tlast => open,
output_axis_tuser => open
);
--Main decision loop
main : process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
main_state <= IDLE;
word_ct <= (others => '0');
cmd <= (others => '0');
else
case( main_state ) is
when IDLE =>
cmd <= tcp_rx_long_cc_tdata;
--Wait for valid to announce start of packet
if tcp_rx_long_cc_tvalid = '1' then
main_state <= LATCH_COMMAND;
end if;
when LATCH_COMMAND =>
main_state <= COUNT_PACKET;
--For reads only have command and address so mask out word_ct
--normally - 2 for zero indexed and roll-over but count cmd and address
--TODO: change to when/else when I get VHDL 2008 working
if cmd_rw_bit = '0' then
word_ct <= resize(unsigned(cmd_length),17);
else
word_ct <= (others => '0');
end if;
when COUNT_PACKET =>
if demux_tvalid = '1' and demux_tready = '1' then
if word_ct(word_ct'high) = '1' then
main_state <= IDLE;
end if;
word_ct <= word_ct - 1;
end if;
end case;
end if;
end if;
end process;
--Combinational AXI stream signals
demux_tdata <= tcp_rx_long_cc_tdata;
demux_tvalid <= tcp_rx_long_cc_tvalid when main_state = COUNT_PACKET else '0';
tcp_rx_long_cc_tready <= demux_tready when main_state = COUNT_PACKET else '0';
demux_tlast <= demux_tvalid when main_state = COUNT_PACKET and word_ct(word_ct'high) = '1' else '0';
--Demux between memory and CPLD
memory_cpld_demux : axis_demux_2
generic map ( DATA_WIDTH => 32)
port map (
clk => clk,
rst => rst,
input_axis_tdata => demux_tdata,
input_axis_tvalid => demux_tvalid,
input_axis_tready => demux_tready,
input_axis_tlast => demux_tlast,
input_axis_tuser => '0',
output_0_axis_tdata => memory_rx_tdata,
output_0_axis_tvalid => memory_rx_tvalid,
output_0_axis_tready => memory_rx_tready,
output_0_axis_tlast => memory_rx_tlast,
output_0_axis_tuser => open,
output_1_axis_tdata => cpld_rx_tdata,
output_1_axis_tvalid => cpld_rx_tvalid,
output_1_axis_tready => cpld_rx_tready,
output_1_axis_tlast => cpld_rx_tlast,
output_1_axis_tuser => open,
enable => '1',
control(0) => cmd_cpld_bit
);
end architecture;
| mpl-2.0 | aa1902f0fcc48fbe96f5ef8267fec2d0 | 0.660388 | 2.815476 | false | false | false | false |
BBN-Q/APS2-Comms | src/com5402_wrapper.vhd | 1 | 8,739 | -- Wraps ComBlock 5402 server into something more AXI compatible
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.com5402pkg.all; -- defines global types, number of TCP streams, etc
use work.com5402_wrapper_pkg.all;
entity com5402_wrapper is
generic (
SIMULATION : std_logic := '0';
FIXED_IP : boolean := false);
port (
clk : in std_logic;
rst : in std_logic;
tcp_rst : in std_logic;
mac_addr : in std_logic_vector(47 downto 0) := (others => '0');
IPv4_addr : in std_logic_vector(31 downto 0) := (others => '0');
subnet_mask : in std_logic_vector(31 downto 0) := (others => '0');
gateway_ip_addr : in std_logic_vector(31 downto 0) := (others => '0');
dhcp_enable : in std_logic := '0';
mac_tx_tdata : out std_logic_vector(7 downto 0);
mac_tx_tvalid : out std_logic;
mac_tx_tlast : out std_logic;
mac_tx_tuser : out std_logic;
mac_tx_tready : in std_logic;
mac_rx_tdata : in std_logic_vector(7 downto 0);
mac_rx_tvalid : in std_logic;
mac_rx_tlast : in std_logic;
mac_rx_tuser : in std_logic;
mac_rx_tready : out std_logic;
udp_rx_tdata : out std_logic_vector(7 downto 0);
udp_rx_tvalid : out std_logic;
udp_rx_tlast : out std_logic;
udp_rx_dest_port : in std_logic_vector(15 downto 0) := (others => '0');
udp_rx_src_port : out std_logic_vector(15 downto 0);
rx_src_ip_addr : out std_logic_vector(31 downto 0);
udp_tx_tdata : in std_logic_vector(7 downto 0) := (others => '0');
udp_tx_tvalid : in std_logic := '0';
udp_tx_tlast : in std_logic := '0';
udp_tx_tready : out std_logic;
udp_tx_src_port : in std_logic_vector(15 downto 0) := (others => '0');
udp_tx_dest_port : in std_logic_vector(15 downto 0) := (others => '0');
udp_tx_dest_ip_addr : in std_logic_vector(31 downto 0) := (others => '0');
udp_tx_ack : out std_logic;
udp_tx_nack : out std_logic;
tcp_port : in std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_tdata : out std_logic_vector(7 downto 0);
tcp_rx_tvalid : out std_logic;
tcp_rx_tready : in std_logic := '1';
tcp_tx_tdata : in std_logic_vector(7 downto 0) := (others => '0');
tcp_tx_tvalid : in std_logic := '0';
tcp_tx_tready : out std_logic
);
end entity;
architecture arch of com5402_wrapper is
signal tcp_rx_data, tcp_tx_data : SLV8xNTCPSTREAMStype;
--sof/eof signal generation
type SOF_STATE_TYPE is (IDLE, WAIT_FOR_LAST);
signal mac_rx_sof_state : SOF_STATE_TYPE;
signal mac_rx_sof : std_logic;
signal udp_tx_sof_state : SOF_STATE_TYPE;
signal udp_tx_sof : std_logic;
signal udp_tx_cts : std_logic;
signal udp_tx_data_valid : std_logic;
signal udp_tx_eof : std_logic;
--Vivado doesn't properly support reading from out in simulation
signal mac_tx_tlast_int : std_logic;
signal mac_rx_tready_int : std_logic;
--CTS / tready handshakes
signal tcp_rx_tvalid_int : std_logic;
signal tcp_tx_cts : std_logic;
signal tcp_tx_tvalid_int : std_logic;
--AXIS to Comblock tlast conversion
signal mac_rx_tlast_int : std_logic;
type rx_ifg_state_t is (IDLE, GAP);
signal rx_ifg_state : rx_ifg_state_t := IDLE;
begin
--don't leave mac_rx_tlast hanging asserted otherwise Comblock gets messed up
mac_rx_tlast_int <= mac_rx_tlast and mac_rx_tvalid;
mac_tx_tuser <= '0';
mac_tx_tlast <= mac_tx_tlast_int;
-- seems to be no signal from ComBlock to apply back pressure
-- generate one to ensure an interframe gap
mac_rx_ifg : process(clk)
constant RX_IFG_DELAY : natural := 7;
variable ifg_counter : natural range 0 to RX_IFG_DELAY := 0;
begin
if rising_edge(clk) then
if rst = '1' then
rx_ifg_state <= IDLE;
else
case (rx_ifg_state) is
when IDLE =>
ifg_counter := RX_IFG_DELAY;
if mac_rx_tlast_int = '1' then
rx_ifg_state <= GAP;
end if;
when GAP =>
if ifg_counter = 0 then
rx_ifg_state <= IDLE;
else
ifg_counter := ifg_counter - 1;
end if;
end case;
end if;
end if;
end process ; -- mac_rx_ifg
mac_rx_tready_int <= '0' when rx_ifg_state = GAP else '1';
mac_rx_tready <= mac_rx_tready_int;
--Create start-of-frame signals
--TODO turn into procedure
mac_rx_sof_creator : process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
mac_rx_sof_state <= IDLE;
else
case( mac_rx_sof_state ) is
when IDLE =>
if mac_rx_tvalid = '1' and mac_rx_tready_int = '1' then
mac_rx_sof_state <= WAIT_FOR_LAST;
end if;
when WAIT_FOR_LAST =>
if mac_rx_tlast = '1' and mac_rx_tvalid = '1' and mac_rx_tready_int = '1' then
mac_rx_sof_state <= IDLE;
end if;
end case;
end if;
end if;
end process;
mac_rx_sof <= mac_rx_tvalid and mac_rx_tready_int when mac_rx_sof_state = IDLE else '0';
udp_tx_sof_creator : process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
udp_tx_sof_state <= IDLE;
udp_tx_sof <= '0';
else
case( udp_tx_sof_state ) is
when IDLE =>
udp_tx_sof <= '0';
if udp_tx_tvalid = '1' and udp_tx_cts = '1' then
udp_tx_sof_state <= WAIT_FOR_LAST;
udp_tx_sof <= '1';
end if;
when WAIT_FOR_LAST =>
udp_tx_sof <= '0';
if udp_tx_tvalid = '1' and udp_tx_tlast = '1' then
udp_tx_sof_state <= IDLE;
end if;
end case;
end if;
end if;
end process;
udp_tx_data_valid <= udp_tx_tvalid when udp_tx_sof_state = WAIT_FOR_LAST else '0';
udp_tx_eof <= udp_tx_tlast when udp_tx_sof_state = WAIT_FOR_LAST else '0';
--the ComBlock UDP_TX module can take a full packet when CTS is asserted.
--we could add a frame length check to make sure we don't try and send more than one frame
udp_tx_tready <= '1' when udp_tx_sof_state = WAIT_FOR_LAST else '0';
--TCP stream interface between Comblock CTS and AXIS tready For rx CTS is more
--like a read enable so use a small FIFO as an elastic buffer and short-circuit
--the ready signal. When ready deasserts the Comblock stream will continue to
--flow for two clock cycles which can be soaked up by the FIFO. When ready
--asserts then Comblock stream will take two clocks to get going again giving us time to catch up.
tcp_rx_handshake: axis_srl_fifo
generic map (
DATA_WIDTH => 8,
DEPTH => 32
)
port map (
clk => clk,
rst => rst,
input_axis_tdata => tcp_rx_data(0),
input_axis_tvalid => tcp_rx_tvalid_int,
input_axis_tready => open,
input_axis_tlast => '0',
input_axis_tuser => '0',
output_axis_tdata => tcp_rx_tdata,
output_axis_tvalid => tcp_rx_tvalid,
output_axis_tready => tcp_rx_tready,
output_axis_tlast => open,
output_axis_tuser => open,
count => open
);
--Digging into the Comblock it appears tcp_tx_cts asserts when the buffer can
--take up to 128 bytes. Need to mask out valid though when CTS is low because
--AXIS thinks data is not accepted
tcp_tx_tready <= tcp_tx_cts;
tcp_tx_tvalid_int <= tcp_tx_tvalid when tcp_tx_cts = '1' else '0';
com5402_inst : entity work.COM5402_DHCP
generic map (
NUDPTX => 1,
NUDPRX => 1,
IGMP_EN => '0',
NTCPSTREAMS => 1,
CLK_FREQUENCY => 125,
SIMULATION => SIMULATION,
WITH_DHCP_CLIENT => true,
FIXED_IP => FIXED_IP
)
port map (
CLK => clk,
SYNC_RESET => rst,
MAC_ADDR => mac_addr,
REQUESTED_IPv4_ADDR => IPv4_addr,
IPv6_ADDR => (others => '0'),
MULTICAST_IP_ADDR => (others => '0'),
SUBNET_MASK => subnet_mask,
GATEWAY_IP_ADDR => gateway_ip_addr,
DYNAMIC_IP => dhcp_enable,
CONNECTION_RESET(0) => tcp_rst,
MAC_TX_DATA => mac_tx_tdata,
MAC_TX_DATA_VALID => mac_tx_tvalid,
MAC_TX_SOF => open,
MAC_TX_EOF => mac_tx_tlast_int,
MAC_TX_CTS => mac_tx_tready,
MAC_RX_DATA => mac_rx_tdata,
MAC_RX_DATA_VALID => mac_rx_tvalid,
MAC_RX_SOF => mac_rx_sof,
MAC_RX_EOF => mac_rx_tlast_int,
UDP_RX_DATA => udp_rx_tdata,
UDP_RX_DATA_VALID => udp_rx_tvalid,
UDP_RX_EOF => udp_rx_tlast,
UDP_RX_DEST_PORT_NO_IN => udp_rx_dest_port,
CHECK_UDP_RX_DEST_PORT_NO => '1',
UDP_RX_DEST_PORT_NO_OUT => open,
UDP_RX_SRC_PORT_NO => udp_rx_src_port,
RX_SRC_IP_ADDR => rx_src_ip_addr,
UDP_TX_DATA => udp_tx_tdata,
UDP_TX_DATA_VALID => udp_tx_data_valid,
UDP_TX_SOF => udp_tx_sof,
UDP_TX_EOF => udp_tx_eof,
UDP_TX_CTS => udp_tx_cts,
UDP_TX_ACK => udp_tx_ack,
UDP_TX_NAK => udp_tx_nack,
UDP_TX_DEST_IP_ADDR(127 downto 32) => (others => '0'), --ignore IPv6 for now
UDP_TX_DEST_IP_ADDR(31 downto 0) => udp_tx_dest_ip_addr,
UDP_TX_DEST_PORT_NO => udp_tx_dest_port,
UDP_TX_SOURCE_PORT_NO => udp_tx_src_port,
TCP_PORT_NO => tcp_port,
TCP_RX_DATA => tcp_rx_data,
TCP_RX_DATA_VALID(0) => tcp_rx_tvalid_int,
TCP_RX_RTS => open,
TCP_RX_CTS(0) => tcp_rx_tready,
TCP_TX_DATA => tcp_tx_data,
TCP_TX_DATA_VALID(0) => tcp_tx_tvalid_int,
TCP_TX_CTS(0) => tcp_tx_cts
);
--std_logic_vector
tcp_tx_data(0) <= tcp_tx_tdata;
end architecture;
| mpl-2.0 | e5d42616c82b6b8bbaca5c6df583275c | 0.644238 | 2.660274 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/4-MPEG-MV/metaheurísticas/mpegmv_spea2.vhd | 1 | 2,727 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-16.09:04:20)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mpegmv_spea2_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14: IN unsigned(0 TO 3);
output1, output2, output3: OUT unsigned(0 TO 4));
END mpegmv_spea2_entity;
ARCHITECTURE mpegmv_spea2_description OF mpegmv_spea2_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
WHEN "00000010" =>
register1 := register1 + 3;
register2 := input2 * 4;
register3 := input3 * 5;
WHEN "00000011" =>
output1 <= register2 + register1;
register1 := input4 * 7;
register2 := input5 * 8;
register4 := input6 * 9;
register3 := register3 + 11;
register5 := input7 * 12;
WHEN "00000100" =>
register2 := register2 + register3;
register3 := input8 * 13;
register4 := register4 + 15;
register6 := input9 * 16;
register5 := register5 + 18;
WHEN "00000101" =>
register2 := register3 + register2;
register1 := register1 + register4;
register3 := register6 + register5;
register4 := input10 * 19;
register5 := input11 * 20;
WHEN "00000110" =>
register5 := register5 + 22;
register6 := input12 * 23;
register7 := input13 * 24;
register2 := ((NOT register2) + 1) XOR register2;
WHEN "00000111" =>
register5 := register6 + register5;
register6 := input14 * 27;
register1 := register7 + register1;
WHEN "00001000" =>
register3 := register6 + register3;
register4 := register4 + register5;
register1 := ((NOT register1) + 1) XOR register1;
WHEN "00001001" =>
output2 <= register2(0 TO 1) & register4(0 TO 2);
output3 <= register1(0 TO 1) & register3(0 TO 2);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mpegmv_spea2_description; | gpl-3.0 | b8ef4664597bf3493538acbbb29b0a65 | 0.657499 | 3.053751 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/4-MPEG-MV/asap-alap-random/mpegmv_random.vhd | 1 | 3,134 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-13.07:37:23)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mpegmv_random_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14: IN unsigned(0 TO 3);
output1, output2, output3: OUT unsigned(0 TO 4));
END mpegmv_random_entity;
ARCHITECTURE mpegmv_random_description OF mpegmv_random_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register9: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register10: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register11: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register12: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register13: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
register2 := input2 * 2;
register3 := input3 * 3;
register4 := input4 * 4;
register5 := input5 * 5;
register6 := input6 * 6;
register7 := input7 * 7;
register8 := input8 * 8;
register9 := input9 * 9;
WHEN "00000010" =>
register10 := input10 * 10;
WHEN "00000011" =>
register10 := register10 + 12;
WHEN "00000100" =>
register9 := register9 + register10;
register10 := input11 * 13;
register11 := input12 * 14;
register12 := input13 * 15;
WHEN "00000101" =>
register11 := register11 + 17;
register3 := register3 + 19;
register4 := register4 + 21;
register13 := input14 * 22;
register6 := register6 + register9;
WHEN "00000110" =>
register2 := register2 + register11;
register4 := register10 + register4;
WHEN "00000111" =>
register2 := register5 + register2;
register5 := register12 + 24;
register1 := register1 + register4;
register3 := register7 + register3;
WHEN "00001000" =>
output1 <= register13 + register5;
register1 := ((NOT register1) + 1) XOR register1;
WHEN "00001001" =>
output2 <= register1(0 TO 1) & register6(0 TO 2);
register1 := register8 + register3;
WHEN "00001010" =>
register1 := ((NOT register1) + 1) XOR register1;
WHEN "00001011" =>
output3 <= register1(0 TO 1) & register2(0 TO 2);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mpegmv_random_description; | gpl-3.0 | 1d818316eb730a511f6d89c0715e6f0c | 0.66305 | 3.137137 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/8-JPEG-SD/asap-alap-random/jpegsd_random.vhd | 1 | 4,746 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-26.15:39:49)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY jpegsd_random_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16, input17, input18: IN unsigned(0 TO 3);
output1, output2, output3: OUT unsigned(0 TO 4));
END jpegsd_random_entity;
ARCHITECTURE jpegsd_random_description OF jpegsd_random_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register9: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register10: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register11: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register12: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register13: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register14: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register15: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
WHEN "00000010" =>
register2 := input2 + 2;
WHEN "00000011" =>
register3 := input3 + 3;
register4 := ((NOT input4) + 1) XOR input4;
WHEN "00000100" =>
register5 := input5 + 5;
register2 := ((NOT register2) + 1) XOR register2;
register6 := ((NOT input6) + 1) XOR input6;
register3 := ((NOT register3) + 1) XOR register3;
WHEN "00000101" =>
output1 <= input7 + 11;
WHEN "00000110" =>
register7 := input8 + 12;
WHEN "00000111" =>
register8 := input9 + 13;
WHEN "00001000" =>
register9 := input10 + 14;
WHEN "00001001" =>
register10 := input11 + 15;
WHEN "00001010" =>
register11 := input12 + 16;
WHEN "00001011" =>
register12 := input13 + 17;
register10 := ((NOT register10) + 1) XOR register10;
register1 := ((NOT register1) + 1) XOR register1;
WHEN "00001100" =>
register13 := input14 + 22;
register11 := ((NOT register11) + 1) XOR register11;
register8 := ((NOT register8) + 1) XOR register8;
WHEN "00001101" =>
output2 <= input15 + 27;
register5 := ((NOT register5) + 1) XOR register5;
register9 := ((NOT register9) + 1) XOR register9;
register14 := ((NOT input16) + 1) XOR input16;
register12 := ((NOT register12) + 1) XOR register12;
WHEN "00001110" =>
register15 := input17 + 35;
WHEN "00001111" =>
register15 := ((NOT register15) + 1) XOR register15;
register11 := register11 + register12;
register12 := ((NOT input18) + 1) XOR input18;
register7 := ((NOT register7) + 1) XOR register7;
WHEN "00010000" =>
register7 := register11 + register7;
WHEN "00010001" =>
register7 := register7 + register9;
WHEN "00010010" =>
register5 := register12 + register5;
register9 := ((NOT register13) + 1) XOR register13;
WHEN "00010011" =>
register4 := register5 + register4;
WHEN "00010100" =>
register4 := register4 + register10;
WHEN "00010101" =>
register5 := register4 * 44;
register6 := register6 + register9;
WHEN "00010110" =>
register6 := register6 + register14;
WHEN "00010111" =>
register6 := register6 + register8;
WHEN "00011000" =>
register1 := register6 + register1;
WHEN "00011001" =>
register1 := register1 + register2;
WHEN "00011010" =>
register1 := register1 + register3;
WHEN "00011011" =>
register1 := register1 + register15;
WHEN "00011100" =>
register2 := register1 + 46;
WHEN "00011101" =>
register3 := register1 + register2 + register7;
WHEN "00011110" =>
register1 := register1 * register2 * register3;
WHEN "00011111" =>
register1 := register5 + register1;
WHEN "00100000" =>
register1 := register4 + register1;
WHEN "00100001" =>
register1 := register1 srl 48;
WHEN "00100010" =>
output3 <= register1;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END jpegsd_random_description; | gpl-3.0 | a229ffcf5c68b51efdbc6531c804410e | 0.650442 | 3.204591 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/LEKO_LEKU/leku/LEKU-CD'/25_16.vhd | 1 | 9,656 | Library IEEE;
use IEEE.std_logic_1164.all;
entity testing is
Port (
A302,A301,A300,A299,A298,A269,A268,A267,A266,A265,A236,A235,A234,A233,A232,A203,A202,A201,A200,A199,A166,A167,A168,A169,A170: in std_logic;
A43: buffer std_logic
);
end testing;
architecture testing_behav of testing is
signal n_32,n_33,n_37,n_38,n_39,n_40,n_46,n_47,n_48,n_49,n_55,n_56,n_57,n_58,n_59,n_60,n_66,n_67,n_68,n_69,n_72,n_73,n_74,n_81,n_82,n_83,n_84,n_87,n_88,n_91,n_94,n_97,n_98,n_99,n_104,n_105,n_106,n_107,n_108,n_109,n_114,n_120,n_121,n_122,n_123,n_126,n_127,n_128,n_129,n_130,n_135,n_136,n_140,n_141,n_142,n_143,n_149,n_150,n_151,n_152,n_158,n_159,n_160,n_161,n_166,n_167,n_171,n_172,n_173,n_174,n_180,n_181,n_182,n_183,n_189,n_190,n_191,n_192,n_193,n_194,n_195,n_196,n_197,n_201,n_204,n_207,n_208,n_209,n_214,n_215,n_216,n_217,n_218,n_223,n_224,n_225,n_226,n_227,n_234,n_235,n_239,n_240,n_241,n_242,n_248,n_249,n_250,n_251,n_257,n_258,n_259,n_260,n_261,n_262,n_265,n_268,n_271,n_272,n_275,n_278,n_281,n_282,n_283,n_288,n_289,n_290,n_291,n_292,n_293,n_298,n_301,n_304,n_307,n_308,n_309,n_314,n_315,n_316,n_317,n_318,n_319,n_320,n_321,n_322,n_323,n_328,n_333,n_334,n_338,n_339,n_340,n_341,n_347,n_348,n_349,n_350,n_356,n_357,n_358,n_359,n_360,n_361,n_364,n_367,n_370,n_371,n_372,n_377,n_378,n_379,n_380,n_381,n_382,n_383,n_384,n_385,n_386,n_391,n_397,n_398,n_402,n_403,n_404,n_405,n_411,n_412,n_413,n_414,n_420,n_421,n_422,n_423,n_424,n_425,n_428,n_431,n_434,n_435,n_436,n_441,n_442,n_443,n_444,n_445,n_446,n_451,n_456,n_457,n_461,n_462,n_463,n_464,n_470,n_471,n_472,n_473,n_479,n_480,n_481,n_482,n_483,n_484,n_485,n_486,n_487,n_488,n_489,n_490,n_491,n_492,n_493,n_494,n_495,n_496: std_logic;
begin
A43 <=( (not n_496) );
n_32 <=( (not A202) and A203 );
n_33 <=( A200 and n_32 );
n_37 <=( A202 and (not A203) );
n_38 <=( (not A200) and n_37 );
n_39 <=( n_38 ) or ( n_33 );
n_40 <=( (not A199) and n_39 );
n_46 <=( A202 and (not A203) );
n_47 <=( A199 and n_46 );
n_48 <=( n_47 ) or ( A201 );
n_49 <=( A200 and n_48 );
n_55 <=( (not A202) and A203 );
n_56 <=( (not A200) and n_55 );
n_57 <=( n_56 ) or ( A201 );
n_58 <=( A199 and n_57 );
n_59 <=( n_58 ) or ( n_49 );
n_60 <=( n_59 ) or ( n_40 );
n_66 <=( A170 ) or ( A169 );
n_67 <=( A168 and n_66 );
n_68 <=( (not A167) and n_67 );
n_69 <=( A166 and n_68 );
n_72 <=( (not A166) and A167 );
n_73 <=( n_72 ) or ( n_69 );
n_74 <=( n_60 and n_73 );
n_81 <=( (not A169) and (not A170) );
n_82 <=( n_81 ) or ( (not A168) );
n_83 <=( n_82 ) or ( (not A166) );
n_84 <=( (not A167) and n_83 );
n_87 <=( A166 and A167 );
n_88 <=( n_87 ) or ( n_84 );
n_91 <=( (not A203) ) or ( A202 );
n_94 <=( (not A199) and A200 );
n_97 <=( A199 and (not A200) );
n_98 <=( n_97 ) or ( n_94 );
n_99 <=( n_91 and n_98 );
n_104 <=( A203 ) or ( (not A202) );
n_105 <=( A200 and n_104 );
n_106 <=( A199 and n_105 );
n_107 <=( n_106 ) or ( n_99 );
n_108 <=( n_88 and n_107 );
n_109 <=( (not A201) and n_108 );
n_114 <=( A203 ) or ( (not A202) );
n_120 <=( (not A169) and (not A170) );
n_121 <=( n_120 ) or ( (not A168) );
n_122 <=( n_121 ) or ( (not A166) );
n_123 <=( (not A167) and n_122 );
n_126 <=( A166 and A167 );
n_127 <=( n_126 ) or ( n_123 );
n_128 <=( n_114 and n_127 );
n_129 <=( (not A200) and n_128 );
n_130 <=( (not A199) and n_129 );
n_135 <=( (not A268) and A269 );
n_136 <=( A266 and n_135 );
n_140 <=( A268 and (not A269) );
n_141 <=( (not A266) and n_140 );
n_142 <=( n_141 ) or ( n_136 );
n_143 <=( (not A265) and n_142 );
n_149 <=( A268 and (not A269) );
n_150 <=( A265 and n_149 );
n_151 <=( n_150 ) or ( A267 );
n_152 <=( A266 and n_151 );
n_158 <=( (not A268) and A269 );
n_159 <=( (not A266) and n_158 );
n_160 <=( n_159 ) or ( A267 );
n_161 <=( A265 and n_160 );
n_166 <=( (not A301) and A302 );
n_167 <=( A299 and n_166 );
n_171 <=( A301 and (not A302) );
n_172 <=( (not A299) and n_171 );
n_173 <=( n_172 ) or ( n_167 );
n_174 <=( (not A298) and n_173 );
n_180 <=( A301 and (not A302) );
n_181 <=( A298 and n_180 );
n_182 <=( n_181 ) or ( A300 );
n_183 <=( A299 and n_182 );
n_189 <=( (not A301) and A302 );
n_190 <=( (not A299) and n_189 );
n_191 <=( n_190 ) or ( A300 );
n_192 <=( A298 and n_191 );
n_193 <=( n_192 ) or ( n_183 );
n_194 <=( n_193 ) or ( n_174 );
n_195 <=( n_194 ) or ( n_161 );
n_196 <=( n_195 ) or ( n_152 );
n_197 <=( n_196 ) or ( n_143 );
n_201 <=( (not A236) ) or ( A235 );
n_204 <=( (not A232) and A233 );
n_207 <=( A232 and (not A233) );
n_208 <=( n_207 ) or ( n_204 );
n_209 <=( n_201 and n_208 );
n_214 <=( A236 ) or ( (not A235) );
n_215 <=( A233 and n_214 );
n_216 <=( A232 and n_215 );
n_217 <=( n_216 ) or ( n_209 );
n_218 <=( (not A234) and n_217 );
n_223 <=( A236 ) or ( (not A235) );
n_224 <=( (not A233) and n_223 );
n_225 <=( (not A232) and n_224 );
n_226 <=( n_225 ) or ( n_218 );
n_227 <=( n_197 and n_226 );
n_234 <=( (not A235) and A236 );
n_235 <=( A233 and n_234 );
n_239 <=( A235 and (not A236) );
n_240 <=( (not A233) and n_239 );
n_241 <=( n_240 ) or ( n_235 );
n_242 <=( (not A232) and n_241 );
n_248 <=( A235 and (not A236) );
n_249 <=( A232 and n_248 );
n_250 <=( n_249 ) or ( A234 );
n_251 <=( A233 and n_250 );
n_257 <=( (not A235) and A236 );
n_258 <=( (not A233) and n_257 );
n_259 <=( n_258 ) or ( A234 );
n_260 <=( A232 and n_259 );
n_261 <=( n_260 ) or ( n_251 );
n_262 <=( n_261 ) or ( n_242 );
n_265 <=( (not A302) ) or ( A301 );
n_268 <=( (not A298) and A299 );
n_271 <=( A298 and (not A299) );
n_272 <=( n_271 ) or ( n_268 );
n_275 <=( (not A269) ) or ( A268 );
n_278 <=( (not A265) and A266 );
n_281 <=( A265 and (not A266) );
n_282 <=( n_281 ) or ( n_278 );
n_283 <=( n_275 and n_282 );
n_288 <=( A269 ) or ( (not A268) );
n_289 <=( A266 and n_288 );
n_290 <=( A265 and n_289 );
n_291 <=( n_290 ) or ( n_283 );
n_292 <=( n_272 and n_291 );
n_293 <=( n_265 and n_292 );
n_298 <=( A302 ) or ( (not A301) );
n_301 <=( (not A269) ) or ( A268 );
n_304 <=( (not A265) and A266 );
n_307 <=( A265 and (not A266) );
n_308 <=( n_307 ) or ( n_304 );
n_309 <=( n_301 and n_308 );
n_314 <=( A269 ) or ( (not A268) );
n_315 <=( A266 and n_314 );
n_316 <=( A265 and n_315 );
n_317 <=( n_316 ) or ( n_309 );
n_318 <=( n_298 and n_317 );
n_319 <=( A299 and n_318 );
n_320 <=( A298 and n_319 );
n_321 <=( n_320 ) or ( n_293 );
n_322 <=( n_262 and n_321 );
n_323 <=( (not A267) and n_322 );
n_328 <=( A269 ) or ( (not A268) );
n_333 <=( (not A235) and A236 );
n_334 <=( A233 and n_333 );
n_338 <=( A235 and (not A236) );
n_339 <=( (not A233) and n_338 );
n_340 <=( n_339 ) or ( n_334 );
n_341 <=( (not A232) and n_340 );
n_347 <=( A235 and (not A236) );
n_348 <=( A232 and n_347 );
n_349 <=( n_348 ) or ( A234 );
n_350 <=( A233 and n_349 );
n_356 <=( (not A235) and A236 );
n_357 <=( (not A233) and n_356 );
n_358 <=( n_357 ) or ( A234 );
n_359 <=( A232 and n_358 );
n_360 <=( n_359 ) or ( n_350 );
n_361 <=( n_360 ) or ( n_341 );
n_364 <=( (not A302) ) or ( A301 );
n_367 <=( (not A298) and A299 );
n_370 <=( A298 and (not A299) );
n_371 <=( n_370 ) or ( n_367 );
n_372 <=( n_364 and n_371 );
n_377 <=( A302 ) or ( (not A301) );
n_378 <=( A299 and n_377 );
n_379 <=( A298 and n_378 );
n_380 <=( n_379 ) or ( n_372 );
n_381 <=( n_361 and n_380 );
n_382 <=( n_328 and n_381 );
n_383 <=( (not A266) and n_382 );
n_384 <=( (not A265) and n_383 );
n_385 <=( n_384 ) or ( n_323 );
n_386 <=( (not A300) and n_385 );
n_391 <=( A302 ) or ( (not A301) );
n_397 <=( (not A235) and A236 );
n_398 <=( A233 and n_397 );
n_402 <=( A235 and (not A236) );
n_403 <=( (not A233) and n_402 );
n_404 <=( n_403 ) or ( n_398 );
n_405 <=( (not A232) and n_404 );
n_411 <=( A235 and (not A236) );
n_412 <=( A232 and n_411 );
n_413 <=( n_412 ) or ( A234 );
n_414 <=( A233 and n_413 );
n_420 <=( (not A235) and A236 );
n_421 <=( (not A233) and n_420 );
n_422 <=( n_421 ) or ( A234 );
n_423 <=( A232 and n_422 );
n_424 <=( n_423 ) or ( n_414 );
n_425 <=( n_424 ) or ( n_405 );
n_428 <=( (not A269) ) or ( A268 );
n_431 <=( (not A265) and A266 );
n_434 <=( A265 and (not A266) );
n_435 <=( n_434 ) or ( n_431 );
n_436 <=( n_428 and n_435 );
n_441 <=( A269 ) or ( (not A268) );
n_442 <=( A266 and n_441 );
n_443 <=( A265 and n_442 );
n_444 <=( n_443 ) or ( n_436 );
n_445 <=( n_425 and n_444 );
n_446 <=( (not A267) and n_445 );
n_451 <=( A269 ) or ( (not A268) );
n_456 <=( (not A235) and A236 );
n_457 <=( A233 and n_456 );
n_461 <=( A235 and (not A236) );
n_462 <=( (not A233) and n_461 );
n_463 <=( n_462 ) or ( n_457 );
n_464 <=( (not A232) and n_463 );
n_470 <=( A235 and (not A236) );
n_471 <=( A232 and n_470 );
n_472 <=( n_471 ) or ( A234 );
n_473 <=( A233 and n_472 );
n_479 <=( (not A235) and A236 );
n_480 <=( (not A233) and n_479 );
n_481 <=( n_480 ) or ( A234 );
n_482 <=( A232 and n_481 );
n_483 <=( n_482 ) or ( n_473 );
n_484 <=( n_483 ) or ( n_464 );
n_485 <=( n_451 and n_484 );
n_486 <=( (not A266) and n_485 );
n_487 <=( (not A265) and n_486 );
n_488 <=( n_487 ) or ( n_446 );
n_489 <=( n_391 and n_488 );
n_490 <=( (not A299) and n_489 );
n_491 <=( (not A298) and n_490 );
n_492 <=( n_491 ) or ( n_386 );
n_493 <=( n_492 ) or ( n_227 );
n_494 <=( n_493 ) or ( n_130 );
n_495 <=( n_494 ) or ( n_109 );
n_496 <=( n_495 ) or ( n_74 );
end testing_behav;
| gpl-3.0 | 83eb54d049c6e6fdf41764c37d51710e | 0.502693 | 2.056218 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/6-FIR2/metaheurísticas/fir2_hype.vhd | 1 | 3,427 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-26.14:51:52)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY fir2_hype_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16: IN unsigned(0 TO 3);
output1: OUT unsigned(0 TO 4));
END fir2_hype_entity;
ARCHITECTURE fir2_hype_description OF fir2_hype_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register9: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := not input1 or input1;
register2 := not input2 or input2;
WHEN "00000010" =>
register3 := not input3 or input3;
WHEN "00000011" =>
register1 := register3 + register1;
register3 := not input4 or input4;
register4 := not input5 or input5;
WHEN "00000100" =>
register2 := register3 + register2;
register3 := not input6 or input6;
register1 := register1 * 8;
WHEN "00000101" =>
register3 := register4 + register3;
register4 := not input7 or input7;
register2 := register2 * 11;
register5 := not input8 or input8;
WHEN "00000110" =>
register6 := not input9 or input9;
register7 := not input10 or input10;
register4 := register5 + register4;
WHEN "00000111" =>
register5 := not input11 or input11;
register8 := not input12 or input12;
register6 := register7 + register6;
register4 := register4 * 18;
WHEN "00001000" =>
register7 := not input13 or input13;
register5 := register8 + register5;
register8 := not input14 or input14;
WHEN "00001001" =>
register5 := register5 * 22;
register9 := not input15 or input15;
register7 := register7 + register8;
WHEN "00001010" =>
register7 := register7 * 25;
WHEN "00001011" =>
register5 := register7 + register5;
register6 := register6 * 27;
WHEN "00001100" =>
register2 := register2 + register5;
register3 := register3 * 29;
register5 := not input16 or input16;
WHEN "00001101" =>
register2 := register4 + register2;
WHEN "00001110" =>
register2 := register6 + register2;
register4 := register9 + register5;
WHEN "00001111" =>
register1 := register1 + register2;
register2 := register4 * 32;
WHEN "00010000" =>
register1 := register2 + register1;
WHEN "00010001" =>
register1 := register3 + register1;
WHEN "00010010" =>
output1 <= to_unsigned(2 ** to_integer(register1), 4);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END fir2_hype_description; | gpl-3.0 | ef744c38e90273b4f8f754022103b4cd | 0.667056 | 3.190875 | false | false | false | false |
witoldo7/puc-2 | PUC/PUC_34/demux1_4.vhd | 1 | 905 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity demux1_4 is
port (
-- wejscia
we : in std_logic_vector(3 downto 0);
adr : in std_logic_vector(1 downto 0);
oe : in std_logic ;
-- wyjscia
Y0,Y1,Y2,Y3 : out std_logic_vector (3 downto 0)
);
end demux1_4;
architecture Behavioral of demux1_4 is
begin
process(oe,adr) is
begin
--gdy '1' na wejsciu oe, demltiplexera
-- we zostaje przepisane na Yx w zaleznosci
-- od wejscia adresowego
-- '0' wygasza w 4 segmenty
if oe = '1' then
if adr="00" then
Y0<=we; Y1<="1111"; Y2<="1111"; Y3<="1111";
elsif adr="01" then
Y0<="1111"; Y1<=we; Y2<="1111"; Y3<="1111";
elsif adr="10" then
Y0<="1111"; Y1<="1111"; Y2<=we; Y3<="1111";
elsif adr="11" then
Y0<="1111"; Y1<="1111"; Y2<="1111"; Y3<=we;
end if;
elsif oe='0' then
Y0<="1111"; Y1<="1111"; Y2<="1111"; Y3<="1111";
end if;
end process;
end Behavioral;
| gpl-3.0 | 696615e1f0a0e060aefc94bac9e0ca3c | 0.60663 | 2.350649 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/ramfifo/wr_dc_fwft_ext_as.vhd | 5 | 13,630 | `protect begin_protected
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`protect end_protected
| apache-2.0 | 16170060455c25595719341c3bf1b583 | 0.933749 | 1.872767 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/addsub.vhd | 15 | 10,861 | -------------------------------------------------------------------------------
-- $Id: addsub.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- Either add an ArgA or subtract an ArgS from an ArgD.
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
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-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
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-- ** Xilinx products are not intended for use in life support **
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-- ** **
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-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: addsub.vhd
-- Version:
--------------------------------------------------------------------------------
-- Description:
-- Either add an ArgA or subtract an ArgS from an ArgD. The
-- output, Result, can be optionally combinatorial or registered.
--
-- When C_REGISTERED is false, Result will take on one of
-- two values:
--
-- ArgD - ArgS, when Sub is asserted, or
-- ArgD + ArgA, when Sub is not asserted.
--
-- Cry_BrwN will be '1' if ArgD + ArgA produces a carry
-- and it will be '0' if ArgD - ArgS produces a borrow.
--
-- The signals Clk, Rst and CE are meaningful and used only
-- if C_REGISTERED is true. These may be "tied off" to any
-- std_logic value in combinatorial instantiations (e.g.
-- connected to '0').
--
-- This table details the operation in registered mode:
--
-- Clk Rst CE Sub <Cry_BrwN, Result>
-- --- --- -- --- ------------------
-- _
-- _| 1 x x 0
--
-- _
-- _| 0 1 0 ArgD + ArgA
--
-- _
-- _| 0 1 1 ArgD - ArgS
--
-- _
-- _| 0 0 x No change
--
-- _
-- not _| x x x No change
--
-------------------------------------------------------------------------------
-- Structure:
--
-- addsub.vhd
-------------------------------------------------------------------------------
-- Author: FO
--
-- History:
--
-- FO 08/14/2003 -- First version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity addsub is
generic (
C_WIDTH : natural := 8;
C_REGISTERED : boolean := false
);
port (
Clk : in std_logic;
Rst : in std_logic; -- Reset Result and Cry_BrwN to zero
CE : in std_logic;
ArgD : in std_logic_vector(0 to C_WIDTH-1);
ArgA : in std_logic_vector(0 to C_WIDTH-1);
ArgS : in std_logic_vector(0 to C_WIDTH-1);
Sub : in std_logic;
Cry_BrwN : out std_logic;
Result : out std_logic_vector(0 to C_WIDTH-1)
);
end addsub;
library unisim;
use unisim.VCOMPONENTS.FDRE;
use unisim.VCOMPONENTS.MUXCY;
use unisim.VCOMPONENTS.XORCY;
library ieee;
use ieee.numeric_std.all;
architecture imp of addsub is
signal lutout,
xorcy_out : std_logic_vector(0 to C_WIDTH-1);
signal cry : std_logic_vector(0 to C_WIDTH);
begin
cry(C_WIDTH) <= Sub;
PERBIT_GEN: for j in C_WIDTH-1 downto 0 generate
begin
------------------------------------------------------------------------
-- LUT output generation.
------------------------------------------------------------------------
lutout(j) <= ArgD(j) xor ArgA(j) when Sub = '0' else
ArgD(j) xnor ArgS(j);
------------------------------------------------------------------------
-- Propagate the carry (borrow) out.
------------------------------------------------------------------------
MUXCY_i1: MUXCY
port map (
DI => ArgD(j),
CI => cry(j+1),
S => lutout(j),
O => cry(j)
);
------------------------------------------------------------------------
-- Apply the effect of carry (borrow) in.
------------------------------------------------------------------------
XORCY_i1: XORCY
port map (
LI => lutout(j),
CI => cry(j+1),
O => xorcy_out(j)
);
------------------------------------------------------------------------
-- Result, combinatorial or registered.
------------------------------------------------------------------------
COM_GEN : if not C_REGISTERED generate
Result(j) <= xorcy_out(j);
end generate;
-- else
REG_GEN : if C_REGISTERED generate
FDRE_I1: FDRE
port map (
Q => Result(j),
C => Clk,
CE => CE,
D => xorcy_out(j),
R => Rst
);
end generate;
end generate;
----------------------------------------------------------------------------
-- Cry_BrwN, combinatorial or registered.
----------------------------------------------------------------------------
COM_GEN : if not C_REGISTERED generate
Cry_BrwN <= cry(0);
end generate;
-- else
REG_GEN : if C_REGISTERED generate
FDRE_I1: FDRE
port map (
Q => Cry_BrwN,
C => Clk,
CE => CE,
D => cry(0),
R => Rst
);
end generate;
end imp;
| apache-2.0 | 2ddd4618b8e456eb7792250cffe028b7 | 0.371605 | 5.366107 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/5-EWF/metaheurísticas/ewf_femo.vhd | 1 | 2,924 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-17.11:31:09)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY ewf_femo_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2: IN unsigned(0 TO 3);
output1, output2, output3, output4, output5: OUT unsigned(0 TO 4));
END ewf_femo_entity;
ARCHITECTURE ewf_femo_description OF ewf_femo_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
register2 := input2 + 2;
WHEN "00000010" =>
register3 := register2 + 4;
WHEN "00000011" =>
register4 := register3 + 6;
WHEN "00000100" =>
register4 := register1 + register4;
WHEN "00000101" =>
register5 := register4 * 8;
WHEN "00000110" =>
register5 := register3 + register5;
register6 := register4 * 10;
WHEN "00000111" =>
register3 := register3 + register5;
register4 := register4 + register5;
WHEN "00001000" =>
register6 := register1 + register6;
register3 := register3 * 12;
WHEN "00001001" =>
output1 <= register6 + register4;
register1 := register1 + register6;
WHEN "00001010" =>
register3 := register2 + register3;
register1 := register1 * 15;
WHEN "00001011" =>
register2 := register2 + register3;
WHEN "00001100" =>
register2 := register2 * 17;
WHEN "00001101" =>
register2 := register2 + 19;
register4 := register5 + register3;
WHEN "00001110" =>
output2 <= register3 + register2;
register2 := register4 + 22;
WHEN "00001111" =>
register3 := register2 * 24;
WHEN "00010000" =>
register3 := register3 + 26;
WHEN "00010001" =>
output3 <= register2 + register3;
register1 := register1 + 29;
WHEN "00010010" =>
register2 := register1 + 31;
WHEN "00010011" =>
register2 := register2 * 33;
register3 := register6 + register1;
WHEN "00010100" =>
register3 := register3 + 35;
output4 <= register1 + register2;
WHEN "00010101" =>
register1 := register3 * 38;
WHEN "00010110" =>
register1 := register1 + 40;
WHEN "00010111" =>
output5 <= register3 + register1;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END ewf_femo_description; | gpl-3.0 | 6be3a4a786643b53d26f56548ae84f5d | 0.646717 | 3.157667 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/direct_path_cntr_ai.vhd | 15 | 11,358 |
--ENTITY_TAG
-------------------------------------------------------------------------------
-- $Id: direct_path_cntr_ai.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- direct_path_cntr_ai.vhd - entity/arch
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: direct_path_cntr_ai.vhd
--
-- Description: Direct-path counter with arbitrary increment.
--
-- This is an up counter with a combinatorial direct pass-
-- through mode. The passed-through value also serves as
-- the initial "loaded" value when the counter switches to
-- count mode. In pass-though mode, Dout <= Din.
--
-- The mode is controlled by two signals, Load_n and Cnt_en.
-- The counter is in direct pass-through mode any time Load_n
-- is true (low) and up to the first cycle where Cnt_en is
-- true after Load_n goes false. When Load_n = '1' (load
-- disabled) Dout increments by Delta each time Cnt_en is
-- true at the positive edge of Clk.
--
-- The implementation has a one-LUT delay from Din to Dout
-- (via the XORCY) in direct pass-through mode and the same
-- delay plus carry-chain propogation in count mode. There
-- is an additional LUT delay (added to the Din to Dout
-- delay) from the Load_n input or from the clock edge that
-- puts the counter into count mode.
-------------------------------------------------------------------------------
-- Structure: direct_path_cntr_ai.vhd
-------------------------------------------------------------------------------
-- Author: FLO
-- History:
-- FLO 12/02/2003 -- First version derived from
-- direct_path_cntr.vhd
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity direct_path_cntr_ai is
generic (
C_WIDTH : natural := 8
);
port (
Clk : in std_logic;
Din : in std_logic_vector(0 to C_WIDTH-1);
Dout : out std_logic_vector(0 to C_WIDTH-1);
Load_n : in std_logic;
Cnt_en : in std_logic;
Delta : in std_logic_vector(0 to C_WIDTH-1)
);
end direct_path_cntr_ai;
library unisim;
use unisim.vcomponents.all;
architecture imp of direct_path_cntr_ai is
signal q_i,
lut_out,
q_i_ns : std_logic_vector(0 to C_WIDTH-1);
signal cry : std_logic_vector(0 to C_WIDTH);
signal sel_cntr : std_logic;
signal sel_cntr_and_Load_n : std_logic; -- AND of sel_cntr and Load_n
signal mdelta : std_logic_vector(0 to Delta'length-1); -- "My delta"
-- Delta, adjusted to assure ascending range referenced from zero.
begin
mdelta <= Delta;
----------------------------------------------------------------------------
-- Load_n takes effect combinatorially, causing Dout to be directly driven
-- from Din when Load_n is asserted. When Load_n is not asserted, then the
-- first clocking of asserted Cnt_en switches modes so that Dout is driven
-- by the register value plus one. The value of Dout is clocked into the
-- register with each Cnt_en, thus realizing the counting behavior.
-- The combinatorial override of Load_n takes place in the LUT and covers
-- the cycle that it takes for the mode to recover (since the mode FF has a
-- synchronous reset). Use of an asynchronous reset is rejected as an
-- option to avoid the requirement that Load_n be generated glitch free.
----------------------------------------------------------------------------
I_MODE_SELECTION : process(Clk)
begin
if Clk'event and Clk='1' then
if Load_n = '0' then
sel_cntr <= '0';
elsif Cnt_en = '1' then
sel_cntr <= '1';
end if;
end if;
end process;
sel_cntr_and_Load_n <= sel_cntr and Load_n;
Dout <= q_i_ns;
cry(C_WIDTH) <= '0';
PERBIT_GEN: for j in C_WIDTH-1 downto 0 generate
begin
------------------------------------------------------------------------
-- LUT output generation and MUXCY carry handling.
------------------------------------------------------------------------
DELTA_LUT_GEN: if j >= C_WIDTH-mdelta'length generate
signal gen_cry: std_logic;
begin
lut_out(j) <= q_i(j) xor mdelta(mdelta'length + j - C_WIDTH)
when (sel_cntr_and_Load_n)='1'
else
Din(j);
I_MULT_AND : MULT_AND
port map (
LO => gen_cry,
I1 => sel_cntr_and_Load_n,
I0 => q_i(j)
);
MUXCY_i1: MUXCY
port map (
DI => gen_cry,
CI => cry(j+1),
S => lut_out(j),
O => cry(j)
);
end generate;
--
--
NON_DELTA_LUT_GEN : if j < C_WIDTH-mdelta'length generate
begin
lut_out(j) <= q_i(j) when (sel_cntr_and_Load_n)='1' else Din(j);
MUXCY_i1: MUXCY
port map (
DI => '0',
CI => cry(j+1),
S => lut_out(j),
O => cry(j)
);
end generate;
------------------------------------------------------------------------
-- Apply the effect of carry in.
------------------------------------------------------------------------
XORCY_i1: XORCY
port map (
LI => lut_out(j),
CI => cry(j+1),
O => q_i_ns(j)
);
FDE_i1: FDE
port map (
Q => q_i(j),
C => Clk,
CE => Cnt_en,
D => q_i_ns(j)
);
end generate;
end imp;
| apache-2.0 | b633d1e3b56f36fb9004fc029b11c6d4 | 0.429477 | 4.953336 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/builtin/builtin_extdepth_v6.vhd | 5 | 50,137 | `protect begin_protected
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| apache-2.0 | 812486192d55bd4950b54015ca0d15e6 | 0.949678 | 1.82895 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-30bits_outputs31bits/1-HAL/metaheurísticas/hal_ibea.vhd | 1 | 1,623 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.09:05:41)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY hal_ibea_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5: IN unsigned(0 TO 30);
output1, output2, output3: OUT unsigned(0 TO 31));
END hal_ibea_entity;
ARCHITECTURE hal_ibea_description OF hal_ibea_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "0000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
register2 := input2 * 2;
WHEN "00000010" =>
output1 <= register2 + 3;
register2 := input3 * 4;
IF (register1 < 5) THEN
output2 <= register1;
ELSE
output2 <= "0000000000000000000000000000101";
END IF;
register1 := input4 * 6;
WHEN "00000011" =>
register1 := register2 * register1;
WHEN "00000100" =>
register1 := register1 - 8;
register2 := input5 * 9;
WHEN "00000101" =>
register2 := register2 * 11;
WHEN "00000110" =>
output3 <= register1 - register2;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END hal_ibea_description; | gpl-3.0 | 29d7ca6e4ded3d0b13ca30463cc7fe9b | 0.671596 | 3.127168 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-30bits_outputs31bits/2-MESA-HB/asap-alap-random/mesahb_alap.vhd | 1 | 2,046 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.10:15:30)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mesahb_alap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5: IN unsigned(0 TO 30);
output1, output2: OUT unsigned(0 TO 31));
END mesahb_alap_entity;
ARCHITECTURE mesahb_alap_description OF mesahb_alap_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register4: unsigned(0 TO 31) := "0000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
WHEN "00000010" =>
register1 := register1 + 3;
register2 := input2 * 4;
WHEN "00000011" =>
register1 := register1 * 6;
register3 := input3 * 7;
register2 := register2 + 9;
WHEN "00000100" =>
register1 := register1 + 11;
register3 := register3 + 13;
register2 := ((NOT register2) + 1) XOR register2;
register4 := input4 * 16;
WHEN "00000101" =>
register1 := ((NOT register1) + 1) XOR register1;
register3 := register3 * 20;
register2 := register4 * register2;
WHEN "00000110" =>
register1 := register1 * 22;
register3 := register3 + 24;
WHEN "00000111" =>
register1 := register1 + register2;
output1 <= input5 + 25;
WHEN "00001000" =>
output2 <= register1(0 TO 14) & register3(0 TO 15);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mesahb_alap_description; | gpl-3.0 | 41e73de6e35ad38cf93bd694f2ccbcc8 | 0.675953 | 3.206897 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/debug.vhd | 1 | 188,082 | `protect begin_protected
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`protect end_protected
| apache-2.0 | 8c53b39a977d941326985a52e8927753 | 0.955216 | 1.812943 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/14-MESA-IA/asap-alap-random/mesaia_random.vhd | 1 | 7,988 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.13:55:20)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mesaia_random_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16, input17, input18, input19, input20, input21, input22, input23, input24, input25, input26, input27, input28, input29, input30, input31, input32, input33, input34, input35, input36, input37, input38, input39, input40, input41, input42, input43, input44, input45, input46, input47, input48: IN unsigned(0 TO 3);
output1, output2, output3, output4: OUT unsigned(0 TO 4));
END mesaia_random_entity;
ARCHITECTURE mesaia_random_description OF mesaia_random_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register9: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register10: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register11: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register12: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register13: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register14: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register15: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register16: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register17: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register18: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register19: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register20: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register21: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register22: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register23: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register24: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register25: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register26: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register27: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register28: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register29: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register30: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register31: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register32: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register33: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register34: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register35: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register36: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
register2 := input2 * 2;
register3 := input3 * 3;
register4 := input4 * 4;
register5 := input5 * 5;
register6 := input6 * 6;
register7 := input7 + 7;
register8 := input8 * 8;
register9 := input9 * 9;
register10 := input10 * 10;
register11 := input11 * 11;
register12 := input12 + 12;
register13 := input13 * 13;
register14 := input14 + 14;
register15 := input15 * 15;
register16 := input16 + 16;
register17 := input17 * 17;
register18 := input18 * 18;
register19 := input19 + 19;
register20 := input20 * 20;
register21 := input21 * 21;
register22 := input22 * 22;
register23 := input23 + 23;
register24 := input24 * 24;
WHEN "00000010" =>
register19 := register20 + register19;
register20 := input25 * 25;
register25 := input26 + 26;
register8 := register8 + register16;
register16 := input27 * 27;
register26 := input28 + 28;
register27 := input29 + 29;
register28 := input30 * 30;
register29 := input31 + 31;
register30 := input32 + 32;
register31 := input33 + 33;
register32 := input34 * 34;
WHEN "00000011" =>
register18 := register18 + register27;
register27 := input35 * 35;
register33 := input36 + 36;
register34 := input37 * 37;
register35 := input38 + 38;
WHEN "00000100" =>
register4 := register4 + register35;
register18 := register28 + register18;
register28 := input39 + 39;
register35 := input40 * 40;
register14 := register32 + register14;
register32 := input41 * 41;
register36 := input42 * 42;
WHEN "00000101" =>
register4 := register6 + register4;
register6 := register36 + register25;
register18 := ((NOT register18) + 1) XOR register18;
register7 := register15 + register7;
register13 := register13 + register23;
WHEN "00000110" =>
register4 := ((NOT register4) + 1) XOR register4;
register14 := register17 + register14;
WHEN "00000111" =>
register14 := ((NOT register14) + 1) XOR register14;
register12 := register34 + register12;
register8 := register35 + register8;
register15 := input43 * 49;
register17 := input44 * 50;
register5 := register5 + register26;
register21 := register21 + register30;
register23 := register27 + register29;
register25 := input45 * 51;
register26 := input46 * 52;
WHEN "00001000" =>
register19 := register26 + register19;
register13 := register15 + register13;
register15 := register32 + register33;
register26 := input47 * 53;
WHEN "00001001" =>
register5 := register26 + register5;
register6 := register22 + register6;
register22 := input48 * 54;
register17 := register17 + register31;
WHEN "00001010" =>
register1 := register22 + register1;
register7 := register25 + register7;
register11 := register11 + register21;
register5 := ((NOT register5) + 1) XOR register5;
register17 := register20 + register17;
WHEN "00001011" =>
register7 := ((NOT register7) + 1) XOR register7;
register3 := register3 + register28;
register13 := ((NOT register13) + 1) XOR register13;
WHEN "00001100" =>
register11 := ((NOT register11) + 1) XOR register11;
register10 := register10 + register12;
register7 := register13 - register7;
WHEN "00001101" =>
register11 := register11 - register14;
register7 := register7 * 64;
register10 := ((NOT register10) + 1) XOR register10;
register2 := register2 + register15;
register1 := register24 + register1;
WHEN "00001110" =>
register11 := register11 * 68;
register9 := register9 + register23;
register3 := register16 + register3;
register6 := ((NOT register6) + 1) XOR register6;
register12 := ((NOT register19) + 1) XOR register19;
register4 := register4 - register10;
WHEN "00001111" =>
register3 := ((NOT register3) + 1) XOR register3;
register7 := register12 + register7;
register1 := ((NOT register1) + 1) XOR register1;
WHEN "00010000" =>
register1 := register1 - register5;
register4 := register4 * 78;
WHEN "00010001" =>
register4 := register18 + register4;
register1 := register1 * 80;
register3 := register3 + register11;
output1 <= register7(0 TO 1) & register2(0 TO 2);
WHEN "00010010" =>
output2 <= register3(0 TO 1) & register9(0 TO 2);
output3 <= register4(0 TO 1) & register17(0 TO 2);
register1 := register6 + register1;
WHEN "00010011" =>
output4 <= register1(0 TO 1) & register8(0 TO 2);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mesaia_random_description; | gpl-3.0 | 4de6ef32d3e296e58774970dd9fdfeeb | 0.665623 | 3.284539 | false | false | false | false |
sandrosalvato94/System-Design-Project | src/polito/sdp2017/Tests/IP_Dummy.vhd | 2 | 896 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.CONSTANTS.all;
entity IP_DUMMY is
port (
clk : in std_logic;
rst : in std_logic;
data_in : out std_logic_vector(DATA_WIDTH-1 downto 0);
data_out : in std_logic_vector(DATA_WIDTH-1 downto 0);
address : out std_logic_vector(ADD_WIDTH-1 downto 0);
W_enable : out std_logic;
R_enable : out std_logic;
generic_en : out std_logic;
enable : in std_logic;
ack : in std_logic;
interrupt : out std_logic
);
end IP_DUMMY;
architecture BEHAVIOURAL of IP_DUMMY is
begin
address <= conv_std_logic_vector(4, ADD_WIDTH);
data_in <= conv_std_logic_vector(666, DATA_WIDTH);
W_enable <= '1';
R_enable <= '0';
generic_en <= '1';
interrupt <= '0';
end architecture BEHAVIOURAL; | lgpl-3.0 | e0ab0ee5ea3b29865c3e8cdd19992f3d | 0.616071 | 2.538244 | false | false | false | false |
jdryg/tis100cpu | register_file_tb.vhd | 1 | 3,972 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY register_file_tb IS
END register_file_tb;
ARCHITECTURE behavior OF register_file_tb IS
constant REG_SIZE : integer := 16;
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT register_file
GENERIC (WIDTH : integer := REG_SIZE);
PORT(
I_clk : IN std_logic;
I_swp : IN std_logic;
I_enableWrite : IN std_logic;
I_srcAID : IN std_logic_vector(1 downto 0);
I_srcBID : IN std_logic_vector(1 downto 0);
I_dstID : IN std_logic_vector(1 downto 0);
I_dstData : IN std_logic_vector(WIDTH-1 downto 0);
O_srcAData : OUT std_logic_vector(WIDTH-1 downto 0);
O_srcBData : OUT std_logic_vector(WIDTH-1 downto 0)
);
END COMPONENT;
--Inputs
signal I_clk : std_logic := '0';
signal I_swp : std_logic := '0';
signal I_enableWrite : std_logic := '0';
signal I_srcAID : std_logic_vector(1 downto 0) := (others => '0');
signal I_srcBID : std_logic_vector(1 downto 0) := (others => '0');
signal I_dstID : std_logic_vector(1 downto 0) := (others => '0');
signal I_dstData : std_logic_vector(REG_SIZE-1 downto 0) := (others => '0');
--Outputs
signal O_srcAData : std_logic_vector(REG_SIZE-1 downto 0);
signal O_srcBData : std_logic_vector(REG_SIZE-1 downto 0);
-- Clock period definitions
constant I_clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: register_file
GENERIC MAP (WIDTH => REG_SIZE)
PORT MAP (
I_clk => I_clk,
I_swp => I_swp,
I_enableWrite => I_enableWrite,
I_srcAID => I_srcAID,
I_srcBID => I_srcBID,
I_dstID => I_dstID,
I_dstData => I_dstData,
O_srcAData => O_srcAData,
O_srcBData => O_srcBData
);
-- Clock process definitions
I_clk_process :process
begin
I_clk <= '0';
wait for I_clk_period/2;
I_clk <= '1';
wait for I_clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- Write the NIL register
I_enableWrite <= '1';
I_dstData <= X"0001";
I_dstID <= "00";
wait for I_clk_period;
-- Verify that reading the NIL register always returns 0
I_srcAID <= "00";
wait for I_clk_period;
assert O_srcAData = X"0000" report "Error, NIL register != 0" severity ERROR;
-- Write the ACC register and verify it was written correctly.
I_enableWrite <= '1';
I_dstData <= X"0acc";
I_dstID <= "01";
wait for I_clk_period;
I_srcAID <= "01";
wait for I_clk_period;
assert O_srcAData = X"0acc" report "Error, ACC register not written correctly" severity ERROR;
-- Write the BAK register and read both ACC and back at the same time.
I_enableWrite <= '1';
I_dstData <= X"bacc";
I_dstID <= "10";
wait for I_clk_period;
I_srcAID <= "10";
I_srcBID <= "01";
wait for I_clk_period;
assert O_srcAData = X"bacc" report "Error, BAK register not written correctly" severity ERROR;
assert O_srcBData = X"0acc" report "Error, ACC register not read correctly. Should have the last value." severity ERROR;
-- Write the TMP register and verify it was written correctly.
I_enableWrite <= '1';
I_dstData <= X"1234";
I_dstID <= "11";
wait for I_clk_period;
I_srcAID <= "11";
wait for I_clk_period;
assert O_srcAData = X"1234" report "Error, TMP register not written correctly" severity ERROR;
-- SWP
I_swp <= '1';
wait for I_clk_period;
-- Read ACC (should have the last value of BAK)
I_swp <= '0';
I_srcAID <= "01";
I_srcBID <= "10";
wait for I_clk_period;
assert O_srcAData = X"bacc" report "Error, SWP didn't work correctly" severity ERROR;
-- SWP regs in every clock cycle, till the end of times!
I_swp <= '1';
wait;
end process;
END;
| mit | 89b25fd61394f0196390258074e698ce | 0.594914 | 3.239804 | false | false | false | false |
rcls/sdr | vhdl/burst.vhd | 1 | 1,587 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.defs.all;
entity burst is
port(adc_data : in signed14;
trigger : in std_logic;
data : out signed15;
strobe : out std_logic;
clk : in std_logic);
end burst;
architecture burst of burst is
constant bits : integer := 11;
constant ram_size : integer := 2048;
signal in_count : unsigned(bits downto 0) := (others => '0');
signal out_count : unsigned(bits + 8 downto 0) := (others => '0');
constant zero : unsigned(bits + 8 downto 0) := (others => '0');
type ram_t is array(0 to ram_size) of signed14;
signal ram : ram_t;
signal data_1, data_2 : signed14;
signal zero_1, zero_2 : std_logic;
signal strobe_1, strobe_2 : std_logic;
signal trigger_last : std_logic := '0';
begin
process
begin
wait until rising_edge(clk);
trigger_last <= trigger;
if trigger_last /= trigger then
in_count <= (bits => '1', others => '0');
elsif in_count(bits) = '1' then
in_count <= in_count + 1;
end if;
if in_count(bits) = '1' then
ram(to_integer(in_count(bits - 1 downto 0))) <= adc_data;
end if;
end process;
process
begin
wait until rising_edge(clk);
out_count <= out_count + 1;
zero_1 <= b2s(out_count(bits + 8 downto 9) = zero(bits + 8 downto 9));
data_1 <= ram(to_integer(out_count(bits + 8 downto 9)));
strobe_1 <= out_count(9);
zero_2 <= zero_1;
data_2 <= data_1;
strobe_2 <= strobe_1;
data <= zero_2 & data_2;
strobe <= strobe_2;
end process;
end burst;
| gpl-3.0 | 36ed08477802b0045f9668fae5476745 | 0.606805 | 3.124016 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/LEKO_LEKU/leku/LEKU-CD'/25_20.vhd | 1 | 6,899 | Library IEEE;
use IEEE.std_logic_1164.all;
entity x25_16x is
Port (
A302,A301,A300,A299,A298,A269,A268,A267,A266,A265,A236,A235,A234,A233,A232,A203,A202,A201,A200,A199,A166,A167,A168,A169,A170: in std_logic;
A39: buffer std_logic
);
end x25_16x;
architecture x25_16x_behav of x25_16x is
signal n_32,n_33,n_37,n_38,n_39,n_40,n_46,n_47,n_48,n_49,n_55,n_56,n_57,n_58,n_59,n_60,n_66,n_67,n_68,n_69,n_72,n_73,n_74,n_81,n_82,n_83,n_84,n_87,n_88,n_91,n_94,n_97,n_98,n_99,n_104,n_105,n_106,n_107,n_108,n_109,n_114,n_120,n_121,n_122,n_123,n_126,n_127,n_128,n_129,n_130,n_135,n_136,n_140,n_141,n_142,n_143,n_149,n_150,n_151,n_152,n_158,n_159,n_160,n_161,n_165,n_168,n_171,n_172,n_173,n_178,n_179,n_180,n_181,n_182,n_187,n_188,n_189,n_190,n_191,n_192,n_193,n_197,n_200,n_203,n_204,n_205,n_210,n_211,n_212,n_213,n_214,n_219,n_220,n_221,n_222,n_223,n_228,n_229,n_233,n_234,n_235,n_236,n_242,n_243,n_244,n_245,n_251,n_252,n_253,n_254,n_255,n_256,n_262,n_263,n_267,n_268,n_269,n_270,n_276,n_277,n_278,n_279,n_285,n_286,n_287,n_288,n_289,n_290,n_293,n_296,n_299,n_300,n_301,n_306,n_307,n_308,n_309,n_310,n_311,n_316,n_321,n_322,n_326,n_327,n_328,n_329,n_335,n_336,n_337,n_338,n_344,n_345,n_346,n_347,n_348,n_349,n_350,n_351,n_352,n_353,n_354,n_355,n_356,n_357,n_358: std_logic;
begin
A39 <=( (not n_358) );
n_32 <=( (not A202) and A203 );
n_33 <=( A200 and n_32 );
n_37 <=( A202 and (not A203) );
n_38 <=( (not A200) and n_37 );
n_39 <=( n_38 ) or ( n_33 );
n_40 <=( (not A199) and n_39 );
n_46 <=( A202 and (not A203) );
n_47 <=( A199 and n_46 );
n_48 <=( n_47 ) or ( A201 );
n_49 <=( A200 and n_48 );
n_55 <=( (not A202) and A203 );
n_56 <=( (not A200) and n_55 );
n_57 <=( n_56 ) or ( A201 );
n_58 <=( A199 and n_57 );
n_59 <=( n_58 ) or ( n_49 );
n_60 <=( n_59 ) or ( n_40 );
n_66 <=( A170 ) or ( A169 );
n_67 <=( A168 and n_66 );
n_68 <=( (not A167) and n_67 );
n_69 <=( A166 and n_68 );
n_72 <=( (not A166) and A167 );
n_73 <=( n_72 ) or ( n_69 );
n_74 <=( n_60 and n_73 );
n_81 <=( (not A169) and (not A170) );
n_82 <=( n_81 ) or ( (not A168) );
n_83 <=( n_82 ) or ( (not A166) );
n_84 <=( (not A167) and n_83 );
n_87 <=( A166 and A167 );
n_88 <=( n_87 ) or ( n_84 );
n_91 <=( (not A203) ) or ( A202 );
n_94 <=( (not A199) and A200 );
n_97 <=( A199 and (not A200) );
n_98 <=( n_97 ) or ( n_94 );
n_99 <=( n_91 and n_98 );
n_104 <=( A203 ) or ( (not A202) );
n_105 <=( A200 and n_104 );
n_106 <=( A199 and n_105 );
n_107 <=( n_106 ) or ( n_99 );
n_108 <=( n_88 and n_107 );
n_109 <=( (not A201) and n_108 );
n_114 <=( A203 ) or ( (not A202) );
n_120 <=( (not A169) and (not A170) );
n_121 <=( n_120 ) or ( (not A168) );
n_122 <=( n_121 ) or ( (not A166) );
n_123 <=( (not A167) and n_122 );
n_126 <=( A166 and A167 );
n_127 <=( n_126 ) or ( n_123 );
n_128 <=( n_114 and n_127 );
n_129 <=( (not A200) and n_128 );
n_130 <=( (not A199) and n_129 );
n_135 <=( (not A268) and A269 );
n_136 <=( A266 and n_135 );
n_140 <=( A268 and (not A269) );
n_141 <=( (not A266) and n_140 );
n_142 <=( n_141 ) or ( n_136 );
n_143 <=( (not A265) and n_142 );
n_149 <=( A268 and (not A269) );
n_150 <=( A265 and n_149 );
n_151 <=( n_150 ) or ( A267 );
n_152 <=( A266 and n_151 );
n_158 <=( (not A268) and A269 );
n_159 <=( (not A266) and n_158 );
n_160 <=( n_159 ) or ( A267 );
n_161 <=( A265 and n_160 );
n_165 <=( (not A302) ) or ( A301 );
n_168 <=( (not A298) and A299 );
n_171 <=( A298 and (not A299) );
n_172 <=( n_171 ) or ( n_168 );
n_173 <=( n_165 and n_172 );
n_178 <=( A302 ) or ( (not A301) );
n_179 <=( A299 and n_178 );
n_180 <=( A298 and n_179 );
n_181 <=( n_180 ) or ( n_173 );
n_182 <=( (not A300) and n_181 );
n_187 <=( A302 ) or ( (not A301) );
n_188 <=( (not A299) and n_187 );
n_189 <=( (not A298) and n_188 );
n_190 <=( n_189 ) or ( n_182 );
n_191 <=( n_190 ) or ( n_161 );
n_192 <=( n_191 ) or ( n_152 );
n_193 <=( n_192 ) or ( n_143 );
n_197 <=( (not A236) ) or ( A235 );
n_200 <=( (not A232) and A233 );
n_203 <=( A232 and (not A233) );
n_204 <=( n_203 ) or ( n_200 );
n_205 <=( n_197 and n_204 );
n_210 <=( A236 ) or ( (not A235) );
n_211 <=( A233 and n_210 );
n_212 <=( A232 and n_211 );
n_213 <=( n_212 ) or ( n_205 );
n_214 <=( (not A234) and n_213 );
n_219 <=( A236 ) or ( (not A235) );
n_220 <=( (not A233) and n_219 );
n_221 <=( (not A232) and n_220 );
n_222 <=( n_221 ) or ( n_214 );
n_223 <=( n_193 and n_222 );
n_228 <=( (not A301) and A302 );
n_229 <=( A299 and n_228 );
n_233 <=( A301 and (not A302) );
n_234 <=( (not A299) and n_233 );
n_235 <=( n_234 ) or ( n_229 );
n_236 <=( (not A298) and n_235 );
n_242 <=( A301 and (not A302) );
n_243 <=( A298 and n_242 );
n_244 <=( n_243 ) or ( A300 );
n_245 <=( A299 and n_244 );
n_251 <=( (not A301) and A302 );
n_252 <=( (not A299) and n_251 );
n_253 <=( n_252 ) or ( A300 );
n_254 <=( A298 and n_253 );
n_255 <=( n_254 ) or ( n_245 );
n_256 <=( n_255 ) or ( n_236 );
n_262 <=( (not A235) and A236 );
n_263 <=( A233 and n_262 );
n_267 <=( A235 and (not A236) );
n_268 <=( (not A233) and n_267 );
n_269 <=( n_268 ) or ( n_263 );
n_270 <=( (not A232) and n_269 );
n_276 <=( A235 and (not A236) );
n_277 <=( A232 and n_276 );
n_278 <=( n_277 ) or ( A234 );
n_279 <=( A233 and n_278 );
n_285 <=( (not A235) and A236 );
n_286 <=( (not A233) and n_285 );
n_287 <=( n_286 ) or ( A234 );
n_288 <=( A232 and n_287 );
n_289 <=( n_288 ) or ( n_279 );
n_290 <=( n_289 ) or ( n_270 );
n_293 <=( (not A269) ) or ( A268 );
n_296 <=( (not A265) and A266 );
n_299 <=( A265 and (not A266) );
n_300 <=( n_299 ) or ( n_296 );
n_301 <=( n_293 and n_300 );
n_306 <=( A269 ) or ( (not A268) );
n_307 <=( A266 and n_306 );
n_308 <=( A265 and n_307 );
n_309 <=( n_308 ) or ( n_301 );
n_310 <=( n_290 and n_309 );
n_311 <=( (not A267) and n_310 );
n_316 <=( A269 ) or ( (not A268) );
n_321 <=( (not A235) and A236 );
n_322 <=( A233 and n_321 );
n_326 <=( A235 and (not A236) );
n_327 <=( (not A233) and n_326 );
n_328 <=( n_327 ) or ( n_322 );
n_329 <=( (not A232) and n_328 );
n_335 <=( A235 and (not A236) );
n_336 <=( A232 and n_335 );
n_337 <=( n_336 ) or ( A234 );
n_338 <=( A233 and n_337 );
n_344 <=( (not A235) and A236 );
n_345 <=( (not A233) and n_344 );
n_346 <=( n_345 ) or ( A234 );
n_347 <=( A232 and n_346 );
n_348 <=( n_347 ) or ( n_338 );
n_349 <=( n_348 ) or ( n_329 );
n_350 <=( n_316 and n_349 );
n_351 <=( (not A266) and n_350 );
n_352 <=( (not A265) and n_351 );
n_353 <=( n_352 ) or ( n_311 );
n_354 <=( n_256 and n_353 );
n_355 <=( n_354 ) or ( n_223 );
n_356 <=( n_355 ) or ( n_130 );
n_357 <=( n_356 ) or ( n_109 );
n_358 <=( n_357 ) or ( n_74 );
end x25_16x_behav;
| gpl-3.0 | eb2715c4db0d47d353db3f14829c80c8 | 0.503261 | 2.038712 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/lmb_bram_if_cntlr_v4_0/816dc01c/hdl/vhdl/parityenable.vhd | 1 | 6,023 | -------------------------------------------------------------------------------
-- $Id: parityenable.vhd,v 1.1.2.3 2010/10/04 06:07:06 stefana Exp $
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
------------------------------------------------------------------------------
-- Filename: parity.vhd
--
-- Description: Generate parity optimally for all target architectures
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- parity.vhd
-- xor18.vhd
-- parity_recursive_LUT6.vhd
--
-------------------------------------------------------------------------------
-- Author: stefana
-- Revision: $Revision: 1.1.2.3 $
-- Date: $Date: 2010/10/04 06:07:06 $
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ParityEnable is
generic (
C_USE_LUT6 : boolean := true;
C_SIZE : integer := 4
);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Enable : in std_logic;
Res : out std_logic
);
end entity ParityEnable;
library unisim;
use unisim.vcomponents.all;
architecture IMP of ParityEnable is
-- Non-recursive loop implementation
function ParityGen (InA : std_logic_vector) return std_logic is
variable result : std_logic;
begin
result := '0';
for I in InA'range loop
result := result xor InA(I);
end loop;
return result;
end function ParityGen;
begin -- architecture IMP
Using_LUT6 : if (C_USE_LUT6) generate
--------------------------------------------------------------------------------------------------
-- Single LUT6
--------------------------------------------------------------------------------------------------
Single_LUT6 : if C_SIZE > 1 and C_SIZE <= 5 generate
signal inA5 : std_logic_vector(0 to 4);
begin
Assign_InA : process (InA) is
begin
inA5 <= (others => '0');
inA5(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : LUT6
generic map(
INIT => X"9669699600000000")
port map(
O => Res,
I0 => InA5(4),
I1 => inA5(3),
I2 => inA5(2),
I3 => inA5(1),
I4 => inA5(0),
I5 => Enable);
end generate Single_LUT6;
end generate Using_LUT6;
-- Fall-back implementation without LUT6
Not_Using_LUT6 : if not C_USE_LUT6 or C_SIZE > 8 generate
begin
Res <= Enable and ParityGen(InA);
end generate Not_Using_LUT6;
end architecture IMP;
| apache-2.0 | 6eb9579121ea6e8b5539e59ae54ba268 | 0.533953 | 4.661765 | false | false | false | false |
CyAScott/CIS4930.DatapathSynthesisTool | docs/sample/input_dp.vhd | 1 | 14,195 | ---------------------------------------------------------------------
-- --
-- This file is generated automatically by AUDI (AUtomatic --
-- Design Instantiation) system, a behavioral synthesis system, --
-- developed at the University of South Florida. This project --
-- is supported by the National Science Foundation (NSF) under --
-- the project number XYZ. If you have any questions, contact --
-- Dr. Srinivas Katkoori ([email protected]), Computer --
-- Science & Engineering Department, University of South Florida, --
-- Tampa, FL 33647. --
-- --
---------------------------------------------------------------------
--
-- Date & Time:
-- User login id/name:
--
-- File name:
-- Type:
--
-- Input aif file name:
--
-- CDFG statistics:
-- * Number of PI's:
-- * Number of PO's:
-- * Number of internal edges:
-- * Number of Operations:
-- * Conditionals:
-- * Loops:
-- * Types of Operations:
--
-- Design Flow/Algorithm Information:
-- * Scheduling Algorithm:
-- * Allocation:
-- * Binding:
-- Interconnect style: Multiplexor-Based or Bus-based
--
-- Design Information:
--
-- Datapath:
-- * Registers:
-- * Functional units:
-- * Number of Multiplexors:
-- * Number of Buses:
--
-- * Operator Binding Information:
--
-- * Register Optimization Information:
--
-- * Register Binding Information:
--
--
-- Controller:
-- * Type: Moore/Mealy
-- * Number of states:
-- * Number of control bits:
--
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library Beh_Lib;
use Beh_Lib.all;
entity input_dp is
port( a : IN std_logic_vector(3 downto 0);
b : IN std_logic_vector(3 downto 0);
c : IN std_logic_vector(3 downto 0);
d : IN std_logic_vector(3 downto 0);
e : IN std_logic_vector(3 downto 0);
f : IN std_logic_vector(3 downto 0);
g : IN std_logic_vector(3 downto 0);
h : IN std_logic_vector(3 downto 0);
i : OUT std_logic_vector(3 downto 0);
ctrl: IN std_logic_vector(14 downto 0);
clear: IN std_logic;
clock: IN std_logic
);
end input_dp;
architecture RTL of input_dp is
component c_register
generic (width : integer := 4);
port (input : in std_logic_vector((width-1) downto 0);
WR: in std_logic;
clear : in std_logic;
clock : in std_logic;
output : out std_logic_vector((width -1) downto 0));
end component;
-- for all : c_register use entity Beh_Lib.c_register(behavior);
component C_Latch
generic (width : integer);
port( input : in Std_logic_vector ((width - 1) downto 0);
ENABLE : in Std_logic;
CLEAR : in Std_logic;
CLOCK : in Std_logic;
output : out Std_logic_vector ((width - 1) downto 0));
end component;
-- for all : C_Latch use entity Beh_Lib.C_Latch(Behavior);
component Constant_Reg
generic (width : integer;
const : integer);
port( output : out Std_logic_vector ((width - 1) downto 0));
end component;
-- for all : Constant_Reg use entity Beh_Lib.Constant_Reg(Behavior);
component Shift_Reg
generic (width : integer);
port( input : in Std_logic_vector ((width - 1) downto 0);
CONTROL : in Std_logic_vector (1 downto 0);
CLEAR : in Std_logic;
CLOCK : in Std_logic;
output : out Std_logic_vector ((width - 1) downto 0));
end component;
-- for all : Shift_Reg use entity Beh_Lib.Shift_Reg(Behavior);
component C_Signal
generic (width : integer);
port( input : in Std_logic_vector ((width - 1) downto 0);
STORE : in Std_logic;
UPDATE : in Std_logic;
CLEAR : in Std_logic;
CLOCK : in Std_logic;
output : out Std_logic_vector ((width + 1) downto 0));
end component;
-- for all : C_Signal use entity Beh_Lib.C_Signal(Behavior);
component Ram
generic (width : integer;
ram_select : integer);
port( input1 : in Std_logic_vector ((width - 1) downto 0);
input2 : in Std_logic_vector ((ram_select - 1) downto 0);
WR : in Std_logic;
RD : in Std_logic;
CLOCK : in Std_logic;
output : out Std_logic_vector ((width - 1) downto 0));
end component;
-- for all : Ram use entity Beh_Lib.Ram(Behavior);
component C_Adder
generic (width : integer);
port( input1 : in Std_logic_vector ((width - 1) downto 0);
input2 : in Std_logic_vector ((width - 1) downto 0);
output : out Std_logic_vector (width downto 0));
end component;
-- for all : C_Adder use entity Beh_Lib.C_Adder(Behavior);
component C_subtractor
generic (width : integer);
port( input1 : in Std_logic_vector ((width - 1) downto 0);
input2 : in Std_logic_vector ((width - 1) downto 0);
output : out Std_logic_vector (width downto 0));
end component;
-- for all : C_Subtractor use entity Beh_Lib.C_Subtractor(Behavior);
component C_Comparator
generic (width : integer);
port( input1 : in Std_logic_vector ((width - 1) downto 0);
input2 : in Std_logic_vector ((width - 1) downto 0);
output : out Std_logic_vector (2 downto 0));
end component;
-- for all : C_Comparator use entity Beh_Lib.C_Comparator(Behavior);
component C_multiplier
generic (width : integer);
port( input1 : in Std_logic_vector ((width - 1) downto 0);
input2 : in Std_logic_vector ((width - 1) downto 0);
output : out Std_logic_vector (((width * 2) - 2) downto 0));
end component;
-- for all : C_Multiplier use entity Beh_Lib.C_Multiplier(Behavior);
component C_Divider
generic (width : integer;
const : integer);
port( input : in Std_logic_vector ((width - 1) downto 0);
output : out Std_logic_vector ((width - 1) downto 0));
end component;
-- for all : C_Divider use entity Beh_Lib.C_Divider(Behavior);
component C_Concat
generic (width1: integer;
width2 : integer);
port( input1 : in Std_logic_vector ((width1 - 1) downto 0);
input2 : in Std_logic_vector ((width2 - 1) downto 0);
output : out Std_logic_vector (((width1 + width2) - 1) downto 0));
end component;
-- for all : C_Concat use entity Beh_Lib.C_Concat(Behavior);
component C_Multiplexer
generic (width : integer;
no_of_inputs : integer;
select_size : integer);
port( input : in Std_logic_vector (((width*no_of_inputs) - 1) downto 0);
MUX_SELECT : in Std_logic_vector ((select_size - 1) downto 0);
output : out Std_logic_vector ((width - 1) downto 0));
end component;
-- for all : C_Multiplexer use entity Beh_Lib.C_Multiplexer(Behavior);
component C_Bus
generic (width : integer;
no_of_inputs : integer);
port( input : in Std_logic_vector (((width*no_of_inputs) - 1) downto 0);
BUS_SELECT : in Std_logic_vector ((no_of_inputs - 1) downto 0);
output : out Std_logic_vector ((width - 1) downto 0));
end component;
-- for all : C_Bus use entity Beh_Lib.C_Bus(Behavior);
component C_And
generic (width : integer);
port( input1 : in Std_logic_vector ((width - 1) downto 0);
input2 : in Std_logic_vector ((width - 1) downto 0);
output : out Std_logic_vector ((width - 1) downto 0));
end component;
-- for all : C_And use entity Beh_Lib.C_And(Behavior);
component C_Or
generic (width : integer);
port( input1 : in Std_logic_vector ((width - 1) downto 0);
input2 : in Std_logic_vector ((width - 1) downto 0);
output : out Std_logic_vector ((width - 1) downto 0));
end component;
-- for all : C_Or use entity Beh_Lib.C_Or(Behavior);
component C_Nand
generic (width : integer);
port( input1 : in Std_logic_vector ((width - 1) downto 0);
input2 : in Std_logic_vector ((width - 1) downto 0);
output : out Std_logic_vector ((width - 1) downto 0));
end component;
-- for all : C_Nand use entity Beh_Lib.C_Nand(Behavior);
component C_Nor
generic (width : integer);
port( input1 : in Std_logic_vector ((width - 1) downto 0);
input2 : in Std_logic_vector ((width - 1) downto 0);
output : out Std_logic_vector ((width - 1) downto 0));
end component;
-- for all : C_Nor use entity Beh_Lib.C_Nor(Behavior);
component C_XNor
generic (width : integer);
port( input1 : in Std_logic_vector ((width - 1) downto 0);
input2 : in Std_logic_vector ((width - 1) downto 0);
output : out Std_logic_vector ((width - 1) downto 0));
end component;
-- for all : C_XNor use entity Beh_Lib.C_XNor(Behavior);
component C_Xor
generic (width : integer);
port( input1 : in Std_logic_vector ((width - 1) downto 0);
input2 : in Std_logic_vector ((width - 1) downto 0);
output : out Std_logic_vector ((width - 1) downto 0));
end component;
-- for all : C_Xor use entity Beh_Lib.C_Xor(Behavior);
component C_Not
generic (width : integer);
port( input : in Std_logic_vector ((width - 1) downto 0);
output : out Std_logic_vector ((width - 1) downto 0));
end component;
-- for all : C_Not use entity Beh_Lib.C_Not(Behavior);
component Tri_State_Buf
generic (width : integer);
port (input : in Std_logic_vector ((width - 1) downto 0);
enable : in Std_logic;
output : out Std_logic_vector ((width - 1) downto 0));
end component;
-- for all : Tri_State_Buf use entity Beh_Lib.Tri_State_Buf(Behavior);
-- Outputs of registers
signal R0_out : Std_logic_vector(3 downto 0);
signal R1_out : Std_logic_vector(3 downto 0);
signal R2_out : Std_logic_vector(3 downto 0);
signal R3_out : Std_logic_vector(3 downto 0);
signal R4_out : Std_logic_vector(3 downto 0);
signal R5_out : Std_logic_vector(3 downto 0);
signal R6_out : Std_logic_vector(3 downto 0);
signal R7_out : Std_logic_vector(3 downto 0);
signal R8_out : Std_logic_vector(3 downto 0);
signal R9_out : Std_logic_vector(3 downto 0);
-- Outputs of FUs
signal FU0_0_out : Std_logic_vector(4 downto 0);
signal FU0_1_out : Std_logic_vector(4 downto 0);
signal FU0_2_out : Std_logic_vector(4 downto 0);
signal FU0_3_out : Std_logic_vector(4 downto 0);
signal FU0_4_out : Std_logic_vector(4 downto 0);
signal FU1_0_out : Std_logic_vector(4 downto 0);
signal FU1_1_out : Std_logic_vector(4 downto 0);
-- Outputs of Interconnect Units
signal Mux0_out : Std_logic_vector(3 downto 0);
signal Mux1_out : Std_logic_vector(3 downto 0);
signal Mux2_out : Std_logic_vector(3 downto 0);
begin
R0 : C_Register
generic map(4)
port map (
input(3 downto 0) => Mux0_out(3 downto 0),
WR => ctrl(0),
CLEAR => clear,
CLOCK => clock,
output => R0_out);
R1 : C_Register
generic map(4)
port map (
input(3 downto 0) => Mux1_out(3 downto 0),
WR => ctrl(1),
CLEAR => clear,
CLOCK => clock,
output => R1_out);
R2 : C_Register
generic map(4)
port map (
input(3 downto 0) => h(3 downto 0),
WR => ctrl(2),
CLEAR => clear,
CLOCK => clock,
output => R2_out);
R3 : C_Register
generic map(4)
port map (
input(3 downto 0) => g(3 downto 0),
WR => ctrl(3),
CLEAR => clear,
CLOCK => clock,
output => R3_out);
R4 : C_Register
generic map(4)
port map (
input(3 downto 0) => f(3 downto 0),
WR => ctrl(4),
CLEAR => clear,
CLOCK => clock,
output => R4_out);
R5 : C_Register
generic map(4)
port map (
input(3 downto 0) => e(3 downto 0),
WR => ctrl(5),
CLEAR => clear,
CLOCK => clock,
output => R5_out);
R6 : C_Register
generic map(4)
port map (
input(3 downto 0) => d(3 downto 0),
WR => ctrl(6),
CLEAR => clear,
CLOCK => clock,
output => R6_out);
R7 : C_Register
generic map(4)
port map (
input(3 downto 0) => c(3 downto 0),
WR => ctrl(7),
CLEAR => clear,
CLOCK => clock,
output => R7_out);
R8 : C_Register
generic map(4)
port map (
input(3 downto 0) => Mux2_out(3 downto 0),
WR => ctrl(8),
CLEAR => clear,
CLOCK => clock,
output => R8_out);
R9 : C_Register
generic map(4)
port map (
input(3 downto 0) => b(3 downto 0),
WR => ctrl(9),
CLEAR => clear,
CLOCK => clock,
output => R9_out);
MULT0_0 : C_Multiplier
generic map(4)
port map (
input1(3 downto 0) => R0_out(3 downto 0),
input2(3 downto 0) => R9_out(3 downto 0),
output(4 downto 0) => FU0_0_out(4 downto 0));
MULT0_1 : C_Multiplier
generic map(4)
port map (
input1(3 downto 0) => R7_out(3 downto 0),
input2(3 downto 0) => R6_out(3 downto 0),
output(4 downto 0) => FU0_1_out(4 downto 0));
MULT0_2 : C_Multiplier
generic map(4)
port map (
input1(3 downto 0) => R5_out(3 downto 0),
input2(3 downto 0) => R4_out(3 downto 0),
output(4 downto 0) => FU0_2_out(4 downto 0));
MULT0_3 : C_Multiplier
generic map(4)
port map (
input1(3 downto 0) => R8_out(3 downto 0),
input2(3 downto 0) => R1_out(3 downto 0),
output(4 downto 0) => FU0_3_out(4 downto 0));
MULT0_4 : C_Multiplier
generic map(4)
port map (
input1(3 downto 0) => R3_out(3 downto 0),
input2(3 downto 0) => R8_out(3 downto 0),
output(4 downto 0) => FU0_4_out(4 downto 0));
SUB1_0 : C_Subtractor
generic map(4)
port map (
input1(3 downto 0) => R1_out(3 downto 0),
input2(3 downto 0) => R2_out(3 downto 0),
output(4 downto 0) => FU1_0_out(4 downto 0));
SUB1_1 : C_Subtractor
generic map(4)
port map (
input1(3 downto 0) => R1_out(3 downto 0),
input2(3 downto 0) => R8_out(3 downto 0),
output(4 downto 0) => FU1_1_out(4 downto 0));
Mux0 : C_Multiplexer
generic map(4, 2, 1)
port map(
input(3 downto 0) => FU1_1_out(3 downto 0),
input(7 downto 4) => a(3 downto 0),
MUX_SELECT(0 downto 0) => ctrl(10 downto 10),
output => Mux0_out);
Mux1 : C_Multiplexer
generic map(4, 3, 2)
port map(
input(3 downto 0) => FU1_0_out(3 downto 0),
input(7 downto 4) => FU0_1_out(3 downto 0),
input(11 downto 8) => FU0_3_out(3 downto 0),
MUX_SELECT(1 downto 0) => ctrl(12 downto 11),
output => Mux1_out);
Mux2 : C_Multiplexer
generic map(4, 3, 2)
port map(
input(3 downto 0) => FU0_0_out(3 downto 0),
input(7 downto 4) => FU0_2_out(3 downto 0),
input(11 downto 8) => FU0_4_out(3 downto 0),
MUX_SELECT(1 downto 0) => ctrl(14 downto 13),
output => Mux2_out);
-- Primary outputs
i(3 downto 0) <= R0_out(3 downto 0);
end RTL;
| mit | 5968a15d96b58d0c63f4111ed9f64c26 | 0.613244 | 3.031824 | false | false | false | false |
jdryg/tis100cpu | alu_tb.vhd | 1 | 5,733 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY alu_tb IS
END alu_tb;
ARCHITECTURE behavior OF alu_tb IS
constant ALU_SIZE : integer := 16;
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT alu
GENERIC (WIDTH : integer := ALU_SIZE);
PORT(I_a, I_b : IN std_logic_vector(WIDTH-1 downto 0);
I_op : IN std_logic_vector(2 downto 0);
O_isZero : OUT std_logic;
O_y : BUFFER std_logic_vector(WIDTH-1 downto 0));
END COMPONENT;
--Inputs
signal I_a : std_logic_vector(ALU_SIZE-1 downto 0) := (others => '0');
signal I_b : std_logic_vector(ALU_SIZE-1 downto 0) := (others => '0');
signal I_op : std_logic_vector(2 downto 0) := (others => '0');
--Outputs
signal O_isZero : std_logic;
signal O_y : std_logic_vector(ALU_SIZE-1 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: alu
GENERIC MAP (WIDTH => ALU_SIZE)
PORT MAP (
I_a => I_a,
I_b => I_b,
I_op => I_op,
O_isZero => O_isZero,
O_y => O_y
);
-- Stimulus process
stim_proc: process
begin
-- Addition
I_op <= "000";
-- Test addition of positive numbers (op = 00)
I_a <= X"0001";
I_b <= X"0002";
wait for 10 ns;
assert O_y = X"0003" report "Addition of positive numbers failed" severity error;
assert O_isZero = '0' report "Invalid zero flag" severity error;
report "Addition of positive numbers completed";
-- Test addition of 1 positive and 1 negative number (op = 00)
I_a <= X"FFF7";
I_b <= X"0009";
wait for 10 ns;
assert O_y = X"0000" report "Addition of 1 positive and 1 negative number failed" severity error;
assert O_isZero = '1' report "Invalid zero flag" severity error;
report "Addition of mixed numbers completed";
-- Test addition of 2 negative numbers
I_a <= X"FFFF";
I_b <= X"FFFE";
wait for 10 ns;
assert O_y = X"FFFD" report "Addition of negative numbers failed" severity error;
assert O_isZero = '0' report "Invalid zero flag" severity error;
report "Addition of negative numbers completed";
-- Subtraction
I_op <= "001";
-- Test subtraction of positive numbers
I_a <= X"0001";
I_b <= X"0002";
wait for 10 ns;
assert O_y = X"FFFF" report "Subtraction of positive numbers failed" severity error;
assert O_isZero = '0' report "Invalid zero flag" severity error;
report "Subtraction of positive numbers completed";
-- Test subtraction of 1 positive and 1 negative number (op = 00)
I_a <= X"FFF7";
I_b <= X"0009";
wait for 10 ns;
assert O_y = X"FFEE" report "Subtraction of 1 positive and 1 negative number failed" severity error;
assert O_isZero = '0' report "Invalid zero flag" severity error;
report "Subtraction of mixed numbers completed";
-- Test subtraction of 2 negative numbers
I_a <= X"FFFF";
I_b <= X"FFFE";
wait for 10 ns;
assert O_y = X"0001" report "Subtraction of negative numbers failed" severity error;
assert O_isZero = '0' report "Invalid zero flag" severity error;
report "Subtraction of negative numbers completed";
-- Negation
I_op <= "010";
I_b <= X"0001";
-- Test negation of positive number
I_a <= X"0001";
wait for 10 ns;
assert O_y = X"FFFF" report "Negation of positive number failed" severity error;
assert O_isZero = '0' report "Invalid zero flag" severity error;
report "Negation of positive number completed";
I_a <= X"FFFE";
wait for 10 ns;
assert O_y = X"0002" report "Negation of negative number failed" severity error;
assert O_isZero = '0' report "Invalid zero flag" severity error;
report "Negation of negative number completed";
-- Set Less Than
I_op <= "011";
I_b <= X"0000";
-- -1 < 0
I_a <= X"FFFF";
wait for 10 ns;
assert O_y = X"0001" report "-1 < 0 failed" severity error;
assert O_isZero = '0' report "Invalid zero flag" severity error;
I_a <= X"0001";
wait for 10 ns;
assert O_y = X"0000" report "1 < 0 failed" severity error;
assert O_isZero = '0' report "Invalid zero flag" severity error;
I_a <= X"0000";
wait for 10 ns;
assert O_y = X"0000" report "0 < 0 failed" severity error;
assert O_isZero = '1' report "Invalid zero flag" severity error;
report "SLT tests completed";
-- Inverse Subtraction
I_op <= "100";
-- Test inverse subtraction of positive numbers
I_a <= X"0001";
I_b <= X"0002";
wait for 10 ns;
assert O_y = X"0001" report "Inverse subtraction of positive numbers failed" severity error;
assert O_isZero = '0' report "Invalid zero flag" severity error;
report "Inverse subtraction of positive numbers completed";
-- Test inverse subtraction of 1 positive and 1 negative number (op = 00)
I_a <= X"FFF7";
I_b <= X"0009";
wait for 10 ns;
assert O_y = X"0012" report "Inverse subtraction of 1 positive and 1 negative number failed" severity error;
assert O_isZero = '0' report "Invalid zero flag" severity error;
report "Inverse subtraction of mixed numbers completed";
-- Test inverse subtraction of 2 negative numbers
I_a <= X"FFFF";
I_b <= X"FFFE";
wait for 10 ns;
assert O_y = X"FFFF" report "Inverse subtraction of negative numbers failed" severity error;
assert O_isZero = '0' report "Invalid zero flag" severity error;
report "Inverse subtraction of negative numbers completed";
wait;
end process;
END;
| mit | 33f6e1f3bf63f63204d97365339684a5 | 0.613291 | 3.69871 | false | true | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/carry_equal.vhd | 1 | 11,904 | `protect begin_protected
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`protect end_protected
| apache-2.0 | 4f790bfabd5549c13e728ab0934a713f | 0.926831 | 1.882353 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/ramfifo/wr_logic.vhd | 5 | 41,428 | `protect begin_protected
`protect version = 1
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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`protect end_protected
| apache-2.0 | 8cfcdb67b51f9fde6ad981b4861609cf | 0.948465 | 1.830991 | false | false | false | false |
CyAScott/CIS4930.DatapathSynthesisTool | src/components/c_comparator.vhd | 2 | 658 | library ieee;
use ieee.std_logic_1164.all;
entity c_comparator is
generic
(
width : integer := 16
);
port
(
input1 : in std_logic_vector((width - 1) downto 0);
input2 : in std_logic_vector((width - 1) downto 0);
output : out std_logic_vector(2 downto 0)
);
end c_comparator;
architecture behavior of c_comparator is
begin
P0 : process (input1, input2)
variable result : std_logic_vector(2 downto 0);
begin
result := "000";
if (input1 = input2) then
result(0) := '1';
elsif (input1 > input2) then
result(1) := '1';
elsif (input1 < input2) then
result(2) := '1';
end if;
output <= result;
end process P0;
end behavior; | mit | e4fdca7346dbcfc16f6e69661d32fadd | 0.648936 | 2.741667 | false | false | false | false |
jdryg/tis100cpu | ben_tb.vhd | 1 | 5,679 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY ben_tb IS
END ben_tb;
ARCHITECTURE behavior OF ben_tb IS
-- constant PROGRAM_FILENAME : string := "F:\Projects\MyStuff\TIS100\Assembler\input.prg";
-- constant PROGRAM_FILENAME : string := "F:\Projects\MyStuff\TIS100\Assembler\output.prg";
constant PROGRAM_FILENAME : string := "F:\Projects\MyStuff\TIS100\Assembler\sample3.prg";
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ben
GENERIC(PROGRAM_FILENAME : string := PROGRAM_FILENAME);
PORT(
I_clk : IN std_logic;
I_reset : IN std_logic;
I_puw_dataValid : IN std_logic;
I_pdw_dataValid : IN std_logic;
I_plw_dataValid : IN std_logic;
I_prw_dataValid : IN std_logic;
I_pur_dataValid : IN std_logic;
I_pdr_dataValid : IN std_logic;
I_plr_dataValid : IN std_logic;
I_prr_dataValid : IN std_logic;
I_pur_data : IN std_logic_vector(15 downto 0);
I_pdr_data : IN std_logic_vector(15 downto 0);
I_plr_data : IN std_logic_vector(15 downto 0);
I_prr_data : IN std_logic_vector(15 downto 0);
O_puw_writeEnable : OUT std_logic;
O_pdw_writeEnable : OUT std_logic;
O_plw_writeEnable : OUT std_logic;
O_prw_writeEnable : OUT std_logic;
O_puw_data : OUT std_logic_vector(15 downto 0);
O_pdw_data : OUT std_logic_vector(15 downto 0);
O_plw_data : OUT std_logic_vector(15 downto 0);
O_prw_data : OUT std_logic_vector(15 downto 0);
O_pur_readEnable : OUT std_logic;
O_pdr_readEnable : OUT std_logic;
O_plr_readEnable : OUT std_logic;
O_prr_readEnable : OUT std_logic
);
END COMPONENT;
--Inputs
signal I_clk : std_logic := '0';
signal I_reset : std_logic := '0';
signal I_puw_dataValid : std_logic := '0';
signal I_pdw_dataValid : std_logic := '0';
signal I_plw_dataValid : std_logic := '0';
signal I_prw_dataValid : std_logic := '0';
signal I_pur_dataValid : std_logic := '0';
signal I_pdr_dataValid : std_logic := '0';
signal I_plr_dataValid : std_logic := '0';
signal I_prr_dataValid : std_logic := '0';
signal I_pur_data : std_logic_vector(15 downto 0) := (others => '0');
signal I_pdr_data : std_logic_vector(15 downto 0) := (others => '0');
signal I_plr_data : std_logic_vector(15 downto 0) := (others => '0');
signal I_prr_data : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal O_puw_writeEnable : std_logic;
signal O_pdw_writeEnable : std_logic;
signal O_plw_writeEnable : std_logic;
signal O_prw_writeEnable : std_logic;
signal O_puw_data : std_logic_vector(15 downto 0);
signal O_pdw_data : std_logic_vector(15 downto 0);
signal O_plw_data : std_logic_vector(15 downto 0);
signal O_prw_data : std_logic_vector(15 downto 0);
signal O_pur_readEnable : std_logic;
signal O_pdr_readEnable : std_logic;
signal O_plr_readEnable : std_logic;
signal O_prr_readEnable : std_logic;
-- Clock period definitions
constant I_clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ben
GENERIC MAP (PROGRAM_FILENAME => PROGRAM_FILENAME)
PORT MAP (
I_clk => I_clk,
I_reset => I_reset,
I_puw_dataValid => I_puw_dataValid,
I_pdw_dataValid => I_pdw_dataValid,
I_plw_dataValid => I_plw_dataValid,
I_prw_dataValid => I_prw_dataValid,
I_pur_dataValid => I_pur_dataValid,
I_pdr_dataValid => I_pdr_dataValid,
I_plr_dataValid => I_plr_dataValid,
I_prr_dataValid => I_prr_dataValid,
I_pur_data => I_pur_data,
I_pdr_data => I_pdr_data,
I_plr_data => I_plr_data,
I_prr_data => I_prr_data,
O_puw_writeEnable => O_puw_writeEnable,
O_pdw_writeEnable => O_pdw_writeEnable,
O_plw_writeEnable => O_plw_writeEnable,
O_prw_writeEnable => O_prw_writeEnable,
O_puw_data => O_puw_data,
O_pdw_data => O_pdw_data,
O_plw_data => O_plw_data,
O_prw_data => O_prw_data,
O_pur_readEnable => O_pur_readEnable,
O_pdr_readEnable => O_pdr_readEnable,
O_plr_readEnable => O_plr_readEnable,
O_prr_readEnable => O_prr_readEnable
);
-- Clock process definitions
I_clk_process :process
begin
I_clk <= '0';
wait for I_clk_period/2;
I_clk <= '1';
wait for I_clk_period/2;
end process;
-- DOWN node for input.prg and sample3.prg
down_proc: process
begin
wait until I_reset <= '0';
loop
I_pdw_dataValid <= '1';
-- Wait until the data from the UP port is valid
wait until O_pdw_writeEnable = '1';
-- Report the value read
report "Value written to the DOWN port is " & integer'image(to_integer(signed(O_pdw_data)));
wait for I_clk_period;
I_pdw_dataValid <= '0';
end loop;
end process;
-- UP node for output.prg and sample3.prg
up_proc: process
variable a : integer := 0;
begin
wait until I_reset = '0';
wait for I_clk_period / 2;
loop
a := a + 1;
I_pur_data <= std_logic_vector(to_signed(a, 16));
I_pur_dataValid <= '1';
wait until O_pur_readEnable = '1';
report "Value read from UP port is " & integer'image(a);
wait for I_clk_period;
I_pur_dataValid <= '0';
end loop;
end process;
-- Stimulus process
stim_proc: process
begin
I_reset <= '1';
wait for I_clk_period;
I_reset <= '0';
wait;
end process;
END;
| mit | c073f077c15a4e6f2da8491e0d53b496 | 0.59764 | 3.234055 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-30bits_outputs31bits/4-MPEG-MV/metaheurísticas/mpegmv_hype.vhd | 1 | 2,905 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-16.09:03:50)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mpegmv_hype_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14: IN unsigned(0 TO 30);
output1, output2, output3: OUT unsigned(0 TO 31));
END mpegmv_hype_entity;
ARCHITECTURE mpegmv_hype_description OF mpegmv_hype_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register4: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register5: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register6: unsigned(0 TO 31) := "00000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
WHEN "00000010" =>
register1 := register1 + 3;
register2 := input2 * 4;
register3 := input3 * 5;
WHEN "00000011" =>
register4 := input4 * 6;
register5 := input5 * 7;
register1 := register3 + register1;
register2 := register2 + 9;
WHEN "00000100" =>
register3 := input6 * 10;
register6 := input7 * 11;
register5 := register5 + 13;
output1 <= register4 + register2;
WHEN "00000101" =>
register2 := input8 * 15;
register4 := input9 * 16;
register3 := register3 + register5;
register1 := register6 + register1;
WHEN "00000110" =>
register4 := register4 + 18;
register5 := input10 * 19;
WHEN "00000111" =>
register2 := register2 + register4;
register4 := input11 * 20;
register1 := ((NOT register1) + 1) XOR register1;
register6 := input12 * 23;
register3 := register5 + register3;
WHEN "00001000" =>
register2 := register4 + register2;
register4 := input13 * 24;
register5 := input14 * 25;
register6 := register6 + 27;
output2 <= register1(0 TO 15) & register3(0 TO 15);
WHEN "00001001" =>
register1 := register5 + register6;
WHEN "00001010" =>
register1 := register4 + register1;
WHEN "00001011" =>
register1 := ((NOT register1) + 1) XOR register1;
WHEN "00001100" =>
output3 <= register1(0 TO 15) & register2(0 TO 15);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mpegmv_hype_description; | gpl-3.0 | 422be6658d9f4331aa6c79a8d52014e8 | 0.67401 | 3.256726 | false | false | false | false |
witoldo7/puc-2 | PUC/PUC_567/PUC_2/demux1_4.vhd | 2 | 839 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity demux1_4 is
port (
-- wejscia
we : in std_logic_vector(3 downto 0);
adr : in std_logic_vector(1 downto 0);
oe : in std_logic ;
-- wyjscia
Y0,Y1,Y2,Y3 : out std_logic_vector (3 downto 0)
);
end demux1_4;
architecture Behavioral of demux1_4 is
begin
process(oe,adr) is
begin
--gdy '1' na wejsciu oe, demltiplexer wlaczony
-- '0' wygasza w 3 segmenty
if oe = '1' then
if adr="00" then
Y0<=we; Y1<="1111"; Y2<="1111"; Y3<="1111";
elsif adr="01" then
Y0<="1111"; Y1<=we; Y2<="1111"; Y3<="1111";
elsif adr="10" then
Y0<="1111"; Y1<="1111"; Y2<=we; Y3<="1111";
elsif adr="11" then
Y0<="1111"; Y1<="1111"; Y2<="1111"; Y3<=we;
end if;
elsif oe='0' then
Y0<="1111"; Y1<="1111"; Y2<="1111"; Y3<="1111";
end if;
end process;
end Behavioral; | gpl-3.0 | 1a2983adbb0815e308ecb89206dbd003 | 0.599523 | 2.35014 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/result_mux_bit.vhd | 1 | 13,849 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
F8CStg3yDBVDIAnLskSv/VsEFA/nnWyMFaJpZHzdrZqyrHW+Odbk84wDZj3KbDpLowiTDmlYukMh
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8512)
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`protect end_protected
| apache-2.0 | a16d6e6c69e7fb2e67cbe7ea162608ce | 0.933641 | 1.879615 | false | false | false | false |
jdryg/tis100cpu | instruction_memory.vhd | 1 | 1,723 | library IEEE;
use STD.TEXTIO.all;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity instruction_memory is
generic (filename : string := "unknown.prg");
port ( I_addr : in STD_LOGIC_VECTOR (5 downto 0);
O_instr : out STD_LOGIC_VECTOR (31 downto 0));
end instruction_memory;
architecture Behavioral of instruction_memory is
begin
process is
file progFile: TEXT;
variable l: line;
variable ch: character;
variable i, index, result: integer;
type memtype is array (0 to 15) of STD_LOGIC_VECTOR (31 downto 0);
variable ROM: memtype;
begin
-- Set all instructions to NOP
for i in 0 to 15 loop
ROM(i) := X"0000";
end loop;
index := 0;
FILE_OPEN(progFile, filename, READ_MODE);
while (not endfile(progFile)) loop
-- Read a single line (1 instruction)
readline(progFile, l);
-- Build the instruction code from the individual characters.
result := 0;
-- Translate each character to its value
for i in 1 to 8 loop
read(L, ch);
if '0' <= ch and ch <= '9' then
result := character'pos(ch) - character'pos('0');
elsif 'A' <= ch and ch <= 'F' then
result := character'pos(ch) - character'pos('A') + 10;
else
report "Format error on line " & integer'image(index) severity error;
end if;
ROM(index)(35 - i*4 downto 32-i*4) := std_logic_vector(to_unsigned(result, 4));
end loop;
index := index + 1;
end loop;
-- Read memory
loop
O_instr <= ROM(to_integer(unsigned(I_addr)));
wait on I_addr;
end loop;
end process;
end Behavioral;
| mit | 3ebded22a0463e2f2da658458df45dea | 0.587348 | 3.689507 | false | false | false | false |
sils1297/HWPrak14 | task_3/task_3.srcs/sources_1/new/tri-state.vhd | 1 | 737 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tristate is
Port (
-- Interface to byte_ctrl
scl_i : out std_logic; -- i2c clock line input
scl_o : in std_logic; -- i2c clock line output
scl_oen : in std_logic; -- i2c clock line output enable, active low
sda_i : out std_logic; -- i2c data line input
sda_o : in std_logic; -- i2c data line output
sda_oen : in std_logic; -- i2c data line output enable, active low
-- Interface to the outside world
scl : inout std_logic;
sda : inout std_logic
);
end tristate;
architecture Behavioral of tristate is
begin
scl_i <= scl;
scl <= scl_o when scl_oen = '0' else 'Z';
sda_i <= sda;
sda <= sda_o when sda_oen = '0' else 'Z';
end Behavioral;
| agpl-3.0 | 0c3f78280b059d90adadf6fe19073a85 | 0.645862 | 2.901575 | false | false | false | false |
rcls/sdr | vhdl/quadcheby.vhd | 1 | 5,391 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.defs.all;
use work.sincos.all;
entity quadcheby is
port (D : in mf_signed;
Q : out signed36;
last_in : in std_logic;
last_out : out std_logic;
clk : in std_logic);
end quadcheby;
architecture quadcheby of quadcheby is
-- We implement:
-- d/dt U = - D - alpha U - beta I
-- d/dt I = U + V
-- d/dt V = - alpha V - beta I
-- Q = 2 alpha V
-- Letting A = U+V, we have
-- d/dt I = A,
-- d/dt A = -D - alpha A - 2 beta I
-- (d/dt)^2 A + alpha d/dt A + 2 beta A + d/dt D = 0.
-- Letting B = U - V, we have
-- d/dt B = -D - alpha B
-- In s-domain,
-- A = -s / (s^2 + alpha s + 2 beta) D
-- B = -1 / (s + alpha) D
-- Q = alpha(A - B) = alpha [ 1/(s+alpha) - s/(s^2 + alpha s + 2beta)] D
-- = 2 alpha beta / (s + alpha)(s^2 + alpha s + 2 beta) D
-- For reference:
-- V = beta / (s + alpha)(s^2 + alpha s + 2 beta) D
-- U = (A + B)/2 = [ 1/(s + alpha) + s/(s^2 + alpha s + 2beta ] D / 2
-- = D (s^2 + alpha s + beta) / (s+alpha)(s^2 + alpha s + 2 beta)
-- = D [1 - beta / (s + alpha s + 2 beta)] / (s + alpha)
-- I = -1 / (s^2 + alpha s + 2 beta) D
-- We have 4 channels TDMd over 16 cycles.
-- We want an overall bandwidth of around 200kHz = 1/1250 f_clk.
-- With beta=4alpha^2, the bandwidth is about pi*alpha rads/clk
-- = alpha/2 f_clk.
-- Remembering that f_clk is 250MHz / 16, take alpha = 1/32.
constant alpha_b : integer := 5;
-- Split beta into two parts; one applied going into I, one coming out.
constant beta1_b : integer := alpha_b;
constant beta2_b : integer := alpha_b - 1;
constant iwidth : integer := maximum(37, mf_width + alpha_b);
constant itop : integer := iwidth - alpha_b;
subtype acc_t is signed(iwidth - 1 downto 0);
signal U, U_a, U_b, U_c, U_d : acc_t := (others => '0');
signal V, V_a, V_b, V_c, V_d : acc_t := (others => '0');
signal I, I_a, I_b, I_c, I_d : acc_t := (others => '0');
signal Uaddend : acc_t := (others => '0');
signal Uc, Vc, Ic : std_logic := '0';
signal phase : unsigned2 := "00";
signal strobe0 : std_logic := '1';
signal strobe1 : std_logic := '0';
attribute keep_hierarchy : string;
attribute keep_hierarchy of quadcheby : architecture is "soft";
begin
process
variable U1, U2, V2, I2 : acc_t;
begin
wait until rising_edge(clk);
strobe0 <= phase(0) and phase(1);
strobe1 <= strobe0;
if strobe0 = '1' then
V_a <= V;
V_b <= V_a;
V_c <= V_b;
V_d <= V_c;
I_a <= I;
I_b <= I_a;
I_c <= I_b;
I_d <= I_c;
U_a <= U;
U_b <= U_a;
U_c <= U_b;
U_d <= U_c;
end if;
case phase is
when "01" =>
Uaddend <= resize(U_d(iwidth - 1 downto alpha_b), iwidth);
Uc <= not U_d(alpha_b - 1);
when "10" =>
Uaddend <= resize(I_d(iwidth - 1 downto beta2_b), iwidth);
Uc <= not I_d(beta2_b - 1);
when others =>
Uaddend <= (others => 'X');
Uc <= '1';
end case;
if strobe1 = '1' then
U1 := U_d;
U2 := resize(D, iwidth) sll (itop - mf_width);
last_out <= last_in;
Q <= V_d(itop + alpha_b - 2 downto itop + alpha_b - 37);
else
U1 := U;
U2 := Uaddend;
end if;
U <= U1 + (not U2) + ("0" & Uc);
if phase = "01" then
Vc <= not V_d(alpha_b - 1);
Ic <= U_d(beta1_b - 1);
elsif phase = "10" then
Vc <= not I_d(beta2_b - 1);
Ic <= V_d(beta1_b - 1);
else
Vc <= '0';
Ic <= '0';
end if;
case phase is
when "10" =>
V2 := not resize(V_d(iwidth - 1 downto alpha_b), iwidth);
I2 := resize(U_d(iwidth - 1 downto beta1_b), iwidth);
when "11" =>
V2 := not resize(I_d(iwidth - 1 downto beta2_b), iwidth);
I2 := resize(V_d(iwidth - 1 downto beta1_b), iwidth);
when others =>
V2 := V_d;
I2 := I_d;
end case;
V <= V + V2 + ("0" & Vc);
I <= I + I2 + ("0" & Ic);
if strobe0 = '1' then
V <= (others => '0');
I <= (others => '0');
end if;
phase <= phase + 1;
end process;
end quadcheby;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.defs.all;
entity test_quadcheby is
port (clk : out std_logic;
Q : out signed(35 downto 0);
last_out : out std_logic);
end test_quadcheby;
architecture test_quadcheby of test_quadcheby is
signal clk_main : std_logic := '0';
signal count : unsigned(10 downto 0) := (others => '0');
signal D : mf_signed := (others => '0');
signal last_in : std_logic := '0';
begin
uut : entity work.quadcheby port map(D, Q, last_in, last_out, clk_main);
clk <= clk_main;
process
begin
wait for 2ns;
clk_main <= not clk_main;
end process;
process(clk_main)
begin
if clk_main'event and clk_main = '1' then
count <= count + 1;
if count(1 downto 0) = "00" then
last_in <= '0';
--D <= (others => '0');
end if;
if count(3 downto 0) = "1100" then
last_in <= '1';
end if;
if count(3 downto 0) = "0000" then
if count(10) = '1' then
D <= to_signed(262144, mf_width);
else
D <= to_signed(-262144, mf_width);
end if;
end if;
end if;
end process;
end test_quadcheby;
| gpl-3.0 | 49caa9262dfd50525df5c06715455b5e | 0.519384 | 2.804891 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/mdm_v3_1/0d9386c2/hdl/vhdl/mdm_core.vhd | 1 | 92,795 | -------------------------------------------------------------------------------
-- $Id: mdm_core.vhd,v 1.1.2.2 2010/11/30 08:14:03 stefana Exp $
-------------------------------------------------------------------------------
-- mdm_core.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2003-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: mdm_core.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- mdm_core.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision$
-- Date: $Date$
--
-- History:
-- goran 2003-02-13 First Version
-- stefana 2012-03-16 Added support for 32 processors and external BSCAN
-- stefana 2012-12-14 Removed legacy interfaces
-- stefana 2013-11-01 Added extended debug: debug register access, debug
-- memory access, cross trigger support
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity MDM_Core is
generic (
C_USE_CONFIG_RESET : integer := 0;
C_BASEADDR : std_logic_vector(0 to 31);
C_HIGHADDR : std_logic_vector(0 to 31);
C_MB_DBG_PORTS : integer;
C_EN_WIDTH : integer;
C_DBG_REG_ACCESS : integer;
C_REG_NUM_CE : integer;
C_REG_DATA_WIDTH : integer;
C_DBG_MEM_ACCESS : integer;
C_S_AXI_ACLK_FREQ_HZ : integer;
C_M_AXI_ADDR_WIDTH : integer;
C_M_AXI_DATA_WIDTH : integer;
C_USE_CROSS_TRIGGER : integer;
C_USE_UART : integer;
C_UART_WIDTH : integer := 8
);
port (
-- Global signals
Config_Reset : in std_logic;
Interrupt : out std_logic;
Ext_BRK : out std_logic;
Ext_NM_BRK : out std_logic;
Debug_SYS_Rst : out std_logic;
-- Debug Register Access signals
DbgReg_DRCK : out std_logic;
DbgReg_UPDATE : out std_logic;
DbgReg_Select : out std_logic;
JTAG_Busy : in std_logic;
-- IPIC signals
bus2ip_clk : in std_logic;
bus2ip_resetn : in std_logic;
bus2ip_data : in std_logic_vector(C_REG_DATA_WIDTH-1 downto 0);
bus2ip_rdce : in std_logic_vector(0 to C_REG_NUM_CE-1);
bus2ip_wrce : in std_logic_vector(0 to C_REG_NUM_CE-1);
bus2ip_cs : in std_logic;
ip2bus_rdack : out std_logic;
ip2bus_wrack : out std_logic;
ip2bus_error : out std_logic;
ip2bus_data : out std_logic_vector(C_REG_DATA_WIDTH-1 downto 0);
-- Bus Master signals
MB_Debug_Enabled : out std_logic_vector(C_EN_WIDTH-1 downto 0);
M_AXI_ACLK : in std_logic;
M_AXI_ARESETn : in std_logic;
Master_rd_start : out std_logic;
Master_rd_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_rd_len : out std_logic_vector(4 downto 0);
Master_rd_size : out std_logic_vector(1 downto 0);
Master_rd_excl : out std_logic;
Master_rd_idle : in std_logic;
Master_rd_resp : in std_logic_vector(1 downto 0);
Master_wr_start : out std_logic;
Master_wr_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_wr_len : out std_logic_vector(4 downto 0);
Master_wr_size : out std_logic_vector(1 downto 0);
Master_wr_excl : out std_logic;
Master_wr_idle : in std_logic;
Master_wr_resp : in std_logic_vector(1 downto 0);
Master_data_rd : out std_logic;
Master_data_out : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_data_exists : in std_logic;
Master_data_wr : out std_logic;
Master_data_in : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_data_empty : in std_logic;
-- JTAG signals
JTAG_TDI : in std_logic;
JTAG_RESET : in std_logic;
UPDATE : in std_logic;
JTAG_SHIFT : in std_logic;
JTAG_CAPTURE : in std_logic;
SEL : in std_logic;
DRCK : in std_logic;
JTAG_TDO : out std_logic;
-- MicroBlaze Debug Signals
Dbg_Clk_0 : out std_logic;
Dbg_TDI_0 : out std_logic;
Dbg_TDO_0 : in std_logic;
Dbg_Reg_En_0 : out std_logic_vector(0 to 7);
Dbg_Capture_0 : out std_logic;
Dbg_Shift_0 : out std_logic;
Dbg_Update_0 : out std_logic;
Dbg_Rst_0 : out std_logic;
Dbg_Trig_In_0 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_0 : in std_logic_vector(0 to 7);
Dbg_Clk_1 : out std_logic;
Dbg_TDI_1 : out std_logic;
Dbg_TDO_1 : in std_logic;
Dbg_Reg_En_1 : out std_logic_vector(0 to 7);
Dbg_Capture_1 : out std_logic;
Dbg_Shift_1 : out std_logic;
Dbg_Update_1 : out std_logic;
Dbg_Rst_1 : out std_logic;
Dbg_Trig_In_1 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_1 : in std_logic_vector(0 to 7);
Dbg_Clk_2 : out std_logic;
Dbg_TDI_2 : out std_logic;
Dbg_TDO_2 : in std_logic;
Dbg_Reg_En_2 : out std_logic_vector(0 to 7);
Dbg_Capture_2 : out std_logic;
Dbg_Shift_2 : out std_logic;
Dbg_Update_2 : out std_logic;
Dbg_Rst_2 : out std_logic;
Dbg_Trig_In_2 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_2 : in std_logic_vector(0 to 7);
Dbg_Clk_3 : out std_logic;
Dbg_TDI_3 : out std_logic;
Dbg_TDO_3 : in std_logic;
Dbg_Reg_En_3 : out std_logic_vector(0 to 7);
Dbg_Capture_3 : out std_logic;
Dbg_Shift_3 : out std_logic;
Dbg_Update_3 : out std_logic;
Dbg_Rst_3 : out std_logic;
Dbg_Trig_In_3 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_3 : in std_logic_vector(0 to 7);
Dbg_Clk_4 : out std_logic;
Dbg_TDI_4 : out std_logic;
Dbg_TDO_4 : in std_logic;
Dbg_Reg_En_4 : out std_logic_vector(0 to 7);
Dbg_Capture_4 : out std_logic;
Dbg_Shift_4 : out std_logic;
Dbg_Update_4 : out std_logic;
Dbg_Rst_4 : out std_logic;
Dbg_Trig_In_4 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_4 : in std_logic_vector(0 to 7);
Dbg_Clk_5 : out std_logic;
Dbg_TDI_5 : out std_logic;
Dbg_TDO_5 : in std_logic;
Dbg_Reg_En_5 : out std_logic_vector(0 to 7);
Dbg_Capture_5 : out std_logic;
Dbg_Shift_5 : out std_logic;
Dbg_Update_5 : out std_logic;
Dbg_Rst_5 : out std_logic;
Dbg_Trig_In_5 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_5 : in std_logic_vector(0 to 7);
Dbg_Clk_6 : out std_logic;
Dbg_TDI_6 : out std_logic;
Dbg_TDO_6 : in std_logic;
Dbg_Reg_En_6 : out std_logic_vector(0 to 7);
Dbg_Capture_6 : out std_logic;
Dbg_Shift_6 : out std_logic;
Dbg_Update_6 : out std_logic;
Dbg_Rst_6 : out std_logic;
Dbg_Trig_In_6 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_6 : in std_logic_vector(0 to 7);
Dbg_Clk_7 : out std_logic;
Dbg_TDI_7 : out std_logic;
Dbg_TDO_7 : in std_logic;
Dbg_Reg_En_7 : out std_logic_vector(0 to 7);
Dbg_Capture_7 : out std_logic;
Dbg_Shift_7 : out std_logic;
Dbg_Update_7 : out std_logic;
Dbg_Rst_7 : out std_logic;
Dbg_Trig_In_7 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_7 : in std_logic_vector(0 to 7);
Dbg_Clk_8 : out std_logic;
Dbg_TDI_8 : out std_logic;
Dbg_TDO_8 : in std_logic;
Dbg_Reg_En_8 : out std_logic_vector(0 to 7);
Dbg_Capture_8 : out std_logic;
Dbg_Shift_8 : out std_logic;
Dbg_Update_8 : out std_logic;
Dbg_Rst_8 : out std_logic;
Dbg_Trig_In_8 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_8 : in std_logic_vector(0 to 7);
Dbg_Clk_9 : out std_logic;
Dbg_TDI_9 : out std_logic;
Dbg_TDO_9 : in std_logic;
Dbg_Reg_En_9 : out std_logic_vector(0 to 7);
Dbg_Capture_9 : out std_logic;
Dbg_Shift_9 : out std_logic;
Dbg_Update_9 : out std_logic;
Dbg_Rst_9 : out std_logic;
Dbg_Trig_In_9 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_9 : in std_logic_vector(0 to 7);
Dbg_Clk_10 : out std_logic;
Dbg_TDI_10 : out std_logic;
Dbg_TDO_10 : in std_logic;
Dbg_Reg_En_10 : out std_logic_vector(0 to 7);
Dbg_Capture_10 : out std_logic;
Dbg_Shift_10 : out std_logic;
Dbg_Update_10 : out std_logic;
Dbg_Rst_10 : out std_logic;
Dbg_Trig_In_10 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_10 : in std_logic_vector(0 to 7);
Dbg_Clk_11 : out std_logic;
Dbg_TDI_11 : out std_logic;
Dbg_TDO_11 : in std_logic;
Dbg_Reg_En_11 : out std_logic_vector(0 to 7);
Dbg_Capture_11 : out std_logic;
Dbg_Shift_11 : out std_logic;
Dbg_Update_11 : out std_logic;
Dbg_Rst_11 : out std_logic;
Dbg_Trig_In_11 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_11 : in std_logic_vector(0 to 7);
Dbg_Clk_12 : out std_logic;
Dbg_TDI_12 : out std_logic;
Dbg_TDO_12 : in std_logic;
Dbg_Reg_En_12 : out std_logic_vector(0 to 7);
Dbg_Capture_12 : out std_logic;
Dbg_Shift_12 : out std_logic;
Dbg_Update_12 : out std_logic;
Dbg_Rst_12 : out std_logic;
Dbg_Trig_In_12 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_12 : in std_logic_vector(0 to 7);
Dbg_Clk_13 : out std_logic;
Dbg_TDI_13 : out std_logic;
Dbg_TDO_13 : in std_logic;
Dbg_Reg_En_13 : out std_logic_vector(0 to 7);
Dbg_Capture_13 : out std_logic;
Dbg_Shift_13 : out std_logic;
Dbg_Update_13 : out std_logic;
Dbg_Rst_13 : out std_logic;
Dbg_Trig_In_13 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_13 : in std_logic_vector(0 to 7);
Dbg_Clk_14 : out std_logic;
Dbg_TDI_14 : out std_logic;
Dbg_TDO_14 : in std_logic;
Dbg_Reg_En_14 : out std_logic_vector(0 to 7);
Dbg_Capture_14 : out std_logic;
Dbg_Shift_14 : out std_logic;
Dbg_Update_14 : out std_logic;
Dbg_Rst_14 : out std_logic;
Dbg_Trig_In_14 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_14 : in std_logic_vector(0 to 7);
Dbg_Clk_15 : out std_logic;
Dbg_TDI_15 : out std_logic;
Dbg_TDO_15 : in std_logic;
Dbg_Reg_En_15 : out std_logic_vector(0 to 7);
Dbg_Capture_15 : out std_logic;
Dbg_Shift_15 : out std_logic;
Dbg_Update_15 : out std_logic;
Dbg_Rst_15 : out std_logic;
Dbg_Trig_In_15 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_15 : in std_logic_vector(0 to 7);
Dbg_Clk_16 : out std_logic;
Dbg_TDI_16 : out std_logic;
Dbg_TDO_16 : in std_logic;
Dbg_Reg_En_16 : out std_logic_vector(0 to 7);
Dbg_Capture_16 : out std_logic;
Dbg_Shift_16 : out std_logic;
Dbg_Update_16 : out std_logic;
Dbg_Rst_16 : out std_logic;
Dbg_Trig_In_16 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_16 : in std_logic_vector(0 to 7);
Dbg_Clk_17 : out std_logic;
Dbg_TDI_17 : out std_logic;
Dbg_TDO_17 : in std_logic;
Dbg_Reg_En_17 : out std_logic_vector(0 to 7);
Dbg_Capture_17 : out std_logic;
Dbg_Shift_17 : out std_logic;
Dbg_Update_17 : out std_logic;
Dbg_Rst_17 : out std_logic;
Dbg_Trig_In_17 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_17 : in std_logic_vector(0 to 7);
Dbg_Clk_18 : out std_logic;
Dbg_TDI_18 : out std_logic;
Dbg_TDO_18 : in std_logic;
Dbg_Reg_En_18 : out std_logic_vector(0 to 7);
Dbg_Capture_18 : out std_logic;
Dbg_Shift_18 : out std_logic;
Dbg_Update_18 : out std_logic;
Dbg_Rst_18 : out std_logic;
Dbg_Trig_In_18 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_18 : in std_logic_vector(0 to 7);
Dbg_Clk_19 : out std_logic;
Dbg_TDI_19 : out std_logic;
Dbg_TDO_19 : in std_logic;
Dbg_Reg_En_19 : out std_logic_vector(0 to 7);
Dbg_Capture_19 : out std_logic;
Dbg_Shift_19 : out std_logic;
Dbg_Update_19 : out std_logic;
Dbg_Rst_19 : out std_logic;
Dbg_Trig_In_19 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_19 : in std_logic_vector(0 to 7);
Dbg_Clk_20 : out std_logic;
Dbg_TDI_20 : out std_logic;
Dbg_TDO_20 : in std_logic;
Dbg_Reg_En_20 : out std_logic_vector(0 to 7);
Dbg_Capture_20 : out std_logic;
Dbg_Shift_20 : out std_logic;
Dbg_Update_20 : out std_logic;
Dbg_Rst_20 : out std_logic;
Dbg_Trig_In_20 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_20 : in std_logic_vector(0 to 7);
Dbg_Clk_21 : out std_logic;
Dbg_TDI_21 : out std_logic;
Dbg_TDO_21 : in std_logic;
Dbg_Reg_En_21 : out std_logic_vector(0 to 7);
Dbg_Capture_21 : out std_logic;
Dbg_Shift_21 : out std_logic;
Dbg_Update_21 : out std_logic;
Dbg_Rst_21 : out std_logic;
Dbg_Trig_In_21 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_21 : in std_logic_vector(0 to 7);
Dbg_Clk_22 : out std_logic;
Dbg_TDI_22 : out std_logic;
Dbg_TDO_22 : in std_logic;
Dbg_Reg_En_22 : out std_logic_vector(0 to 7);
Dbg_Capture_22 : out std_logic;
Dbg_Shift_22 : out std_logic;
Dbg_Update_22 : out std_logic;
Dbg_Rst_22 : out std_logic;
Dbg_Trig_In_22 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_22 : in std_logic_vector(0 to 7);
Dbg_Clk_23 : out std_logic;
Dbg_TDI_23 : out std_logic;
Dbg_TDO_23 : in std_logic;
Dbg_Reg_En_23 : out std_logic_vector(0 to 7);
Dbg_Capture_23 : out std_logic;
Dbg_Shift_23 : out std_logic;
Dbg_Update_23 : out std_logic;
Dbg_Rst_23 : out std_logic;
Dbg_Trig_In_23 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_23 : in std_logic_vector(0 to 7);
Dbg_Clk_24 : out std_logic;
Dbg_TDI_24 : out std_logic;
Dbg_TDO_24 : in std_logic;
Dbg_Reg_En_24 : out std_logic_vector(0 to 7);
Dbg_Capture_24 : out std_logic;
Dbg_Shift_24 : out std_logic;
Dbg_Update_24 : out std_logic;
Dbg_Rst_24 : out std_logic;
Dbg_Trig_In_24 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_24 : in std_logic_vector(0 to 7);
Dbg_Clk_25 : out std_logic;
Dbg_TDI_25 : out std_logic;
Dbg_TDO_25 : in std_logic;
Dbg_Reg_En_25 : out std_logic_vector(0 to 7);
Dbg_Capture_25 : out std_logic;
Dbg_Shift_25 : out std_logic;
Dbg_Update_25 : out std_logic;
Dbg_Rst_25 : out std_logic;
Dbg_Trig_In_25 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_25 : in std_logic_vector(0 to 7);
Dbg_Clk_26 : out std_logic;
Dbg_TDI_26 : out std_logic;
Dbg_TDO_26 : in std_logic;
Dbg_Reg_En_26 : out std_logic_vector(0 to 7);
Dbg_Capture_26 : out std_logic;
Dbg_Shift_26 : out std_logic;
Dbg_Update_26 : out std_logic;
Dbg_Rst_26 : out std_logic;
Dbg_Trig_In_26 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_26 : in std_logic_vector(0 to 7);
Dbg_Clk_27 : out std_logic;
Dbg_TDI_27 : out std_logic;
Dbg_TDO_27 : in std_logic;
Dbg_Reg_En_27 : out std_logic_vector(0 to 7);
Dbg_Capture_27 : out std_logic;
Dbg_Shift_27 : out std_logic;
Dbg_Update_27 : out std_logic;
Dbg_Rst_27 : out std_logic;
Dbg_Trig_In_27 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_27 : in std_logic_vector(0 to 7);
Dbg_Clk_28 : out std_logic;
Dbg_TDI_28 : out std_logic;
Dbg_TDO_28 : in std_logic;
Dbg_Reg_En_28 : out std_logic_vector(0 to 7);
Dbg_Capture_28 : out std_logic;
Dbg_Shift_28 : out std_logic;
Dbg_Update_28 : out std_logic;
Dbg_Rst_28 : out std_logic;
Dbg_Trig_In_28 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_28 : in std_logic_vector(0 to 7);
Dbg_Clk_29 : out std_logic;
Dbg_TDI_29 : out std_logic;
Dbg_TDO_29 : in std_logic;
Dbg_Reg_En_29 : out std_logic_vector(0 to 7);
Dbg_Capture_29 : out std_logic;
Dbg_Shift_29 : out std_logic;
Dbg_Update_29 : out std_logic;
Dbg_Rst_29 : out std_logic;
Dbg_Trig_In_29 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_29 : in std_logic_vector(0 to 7);
Dbg_Clk_30 : out std_logic;
Dbg_TDI_30 : out std_logic;
Dbg_TDO_30 : in std_logic;
Dbg_Reg_En_30 : out std_logic_vector(0 to 7);
Dbg_Capture_30 : out std_logic;
Dbg_Shift_30 : out std_logic;
Dbg_Update_30 : out std_logic;
Dbg_Rst_30 : out std_logic;
Dbg_Trig_In_30 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_30 : in std_logic_vector(0 to 7);
Dbg_Clk_31 : out std_logic;
Dbg_TDI_31 : out std_logic;
Dbg_TDO_31 : in std_logic;
Dbg_Reg_En_31 : out std_logic_vector(0 to 7);
Dbg_Capture_31 : out std_logic;
Dbg_Shift_31 : out std_logic;
Dbg_Update_31 : out std_logic;
Dbg_Rst_31 : out std_logic;
Dbg_Trig_In_31 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_31 : in std_logic_vector(0 to 7);
-- External Trace Signals
Ext_Trig_In : in std_logic_vector(0 to 3);
Ext_Trig_Ack_In : out std_logic_vector(0 to 3);
Ext_Trig_Out : out std_logic_vector(0 to 3);
Ext_Trig_Ack_Out : in std_logic_vector(0 to 3);
-- External JTAG Signals
Ext_JTAG_DRCK : out std_logic;
Ext_JTAG_RESET : out std_logic;
Ext_JTAG_SEL : out std_logic;
Ext_JTAG_CAPTURE : out std_logic;
Ext_JTAG_SHIFT : out std_logic;
Ext_JTAG_UPDATE : out std_logic;
Ext_JTAG_TDI : out std_logic;
Ext_JTAG_TDO : in std_logic
);
end entity MDM_Core;
library IEEE;
use IEEE.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library mdm_v3_1;
use mdm_v3_1.all;
architecture IMP of MDM_CORE is
function log2(x : natural) return integer is
variable i : integer := 0;
begin
if x = 0 then return 0;
else
while 2**i < x loop
i := i+1;
end loop;
return i;
end if;
end function log2;
constant C_DRCK_FREQ_HZ : integer := 30000000;
constant C_CLOCK_BITS : integer := log2(C_S_AXI_ACLK_FREQ_HZ / C_DRCK_FREQ_HZ);
component JTAG_CONTROL
generic (
C_MB_DBG_PORTS : integer;
C_USE_CONFIG_RESET : integer;
C_DBG_REG_ACCESS : integer;
C_DBG_MEM_ACCESS : integer;
C_M_AXI_ADDR_WIDTH : integer;
C_M_AXI_DATA_WIDTH : integer;
C_USE_CROSS_TRIGGER : integer;
C_USE_UART : integer;
C_UART_WIDTH : integer;
C_EN_WIDTH : integer := 1
);
port (
-- Global signals
Config_Reset : in std_logic;
Clk : in std_logic;
Rst : in std_logic;
Clear_Ext_BRK : in std_logic;
Ext_BRK : out std_logic;
Ext_NM_BRK : out std_logic;
Debug_SYS_Rst : out std_logic;
Debug_Rst : out std_logic;
Read_RX_FIFO : in std_logic;
Reset_RX_FIFO : in std_logic;
RX_Data : out std_logic_vector(0 to C_UART_WIDTH-1);
RX_Data_Present : out std_logic;
RX_Buffer_Full : out std_logic;
Write_TX_FIFO : in std_logic;
Reset_TX_FIFO : in std_logic;
TX_Data : in std_logic_vector(0 to C_UART_WIDTH-1);
TX_Buffer_Full : out std_logic;
TX_Buffer_Empty : out std_logic;
-- Debug Register Access signals
DbgReg_Access_Lock : in std_logic;
DbgReg_Force_Lock : in std_logic;
DbgReg_Unlocked : in std_logic;
JTAG_Access_Lock : out std_logic;
JTAG_Force_Lock : out std_logic;
JTAG_AXIS_Overrun : in std_logic;
JTAG_Clear_Overrun : out std_logic;
-- MDM signals
TDI : in std_logic;
RESET : in std_logic;
UPDATE : in std_logic;
SHIFT : in std_logic;
CAPTURE : in std_logic;
SEL : in std_logic;
DRCK : in std_logic;
TDO : out std_logic;
-- Bus Master signals
M_AXI_ACLK : in std_logic;
M_AXI_ARESETn : in std_logic;
Master_rd_start : out std_logic;
Master_rd_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_rd_len : out std_logic_vector(4 downto 0);
Master_rd_size : out std_logic_vector(1 downto 0);
Master_rd_excl : out std_logic;
Master_rd_idle : in std_logic;
Master_rd_resp : in std_logic_vector(1 downto 0);
Master_wr_start : out std_logic;
Master_wr_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_wr_len : out std_logic_vector(4 downto 0);
Master_wr_size : out std_logic_vector(1 downto 0);
Master_wr_excl : out std_logic;
Master_wr_idle : in std_logic;
Master_wr_resp : in std_logic_vector(1 downto 0);
Master_data_rd : out std_logic;
Master_data_out : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_data_exists : in std_logic;
Master_data_wr : out std_logic;
Master_data_in : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_data_empty : in std_logic;
-- MicroBlaze Debug Signals
MB_Debug_Enabled : out std_logic_vector(C_EN_WIDTH-1 downto 0);
Dbg_Clk : out std_logic;
Dbg_TDI : out std_logic;
Dbg_TDO : in std_logic;
Dbg_Reg_En : out std_logic_vector(0 to 7);
Dbg_Capture : out std_logic;
Dbg_Shift : out std_logic;
Dbg_Update : out std_logic;
-- MicroBlaze Cross Trigger Signals
Dbg_Trig_In_0 : in std_logic_vector(0 to 7);
Dbg_Trig_In_1 : in std_logic_vector(0 to 7);
Dbg_Trig_In_2 : in std_logic_vector(0 to 7);
Dbg_Trig_In_3 : in std_logic_vector(0 to 7);
Dbg_Trig_In_4 : in std_logic_vector(0 to 7);
Dbg_Trig_In_5 : in std_logic_vector(0 to 7);
Dbg_Trig_In_6 : in std_logic_vector(0 to 7);
Dbg_Trig_In_7 : in std_logic_vector(0 to 7);
Dbg_Trig_In_8 : in std_logic_vector(0 to 7);
Dbg_Trig_In_9 : in std_logic_vector(0 to 7);
Dbg_Trig_In_10 : in std_logic_vector(0 to 7);
Dbg_Trig_In_11 : in std_logic_vector(0 to 7);
Dbg_Trig_In_12 : in std_logic_vector(0 to 7);
Dbg_Trig_In_13 : in std_logic_vector(0 to 7);
Dbg_Trig_In_14 : in std_logic_vector(0 to 7);
Dbg_Trig_In_15 : in std_logic_vector(0 to 7);
Dbg_Trig_In_16 : in std_logic_vector(0 to 7);
Dbg_Trig_In_17 : in std_logic_vector(0 to 7);
Dbg_Trig_In_18 : in std_logic_vector(0 to 7);
Dbg_Trig_In_19 : in std_logic_vector(0 to 7);
Dbg_Trig_In_20 : in std_logic_vector(0 to 7);
Dbg_Trig_In_21 : in std_logic_vector(0 to 7);
Dbg_Trig_In_22 : in std_logic_vector(0 to 7);
Dbg_Trig_In_23 : in std_logic_vector(0 to 7);
Dbg_Trig_In_24 : in std_logic_vector(0 to 7);
Dbg_Trig_In_25 : in std_logic_vector(0 to 7);
Dbg_Trig_In_26 : in std_logic_vector(0 to 7);
Dbg_Trig_In_27 : in std_logic_vector(0 to 7);
Dbg_Trig_In_28 : in std_logic_vector(0 to 7);
Dbg_Trig_In_29 : in std_logic_vector(0 to 7);
Dbg_Trig_In_30 : in std_logic_vector(0 to 7);
Dbg_Trig_In_31 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_0 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_1 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_2 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_3 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_4 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_5 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_6 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_7 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_8 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_9 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_10 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_11 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_12 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_13 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_14 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_15 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_16 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_17 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_18 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_19 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_20 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_21 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_22 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_23 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_24 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_25 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_26 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_27 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_28 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_29 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_30 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_31 : in std_logic_vector(0 to 7);
Ext_Trig_In : in std_logic_vector(0 to 3);
Ext_Trig_Ack_In : out std_logic_vector(0 to 3);
Ext_Trig_Out : out std_logic_vector(0 to 3);
Ext_Trig_Ack_Out : in std_logic_vector(0 to 3)
);
end component JTAG_CONTROL;
-- Returns the minimum value of the two parameters
function IntMin (a, b : integer) return integer is
begin
if a < b then
return a;
else
return b;
end if;
end function IntMin;
signal config_reset_i : std_logic;
signal clear_Ext_BRK : std_logic;
signal enable_interrupts : std_logic;
signal read_RX_FIFO : std_logic;
signal reset_RX_FIFO : std_logic;
signal rx_Data : std_logic_vector(0 to C_UART_WIDTH-1);
signal rx_Data_Present : std_logic;
signal rx_Buffer_Full : std_logic;
signal tx_Data : std_logic_vector(0 to C_UART_WIDTH-1);
signal write_TX_FIFO : std_logic;
signal reset_TX_FIFO : std_logic;
signal tx_Buffer_Full : std_logic;
signal tx_Buffer_Empty : std_logic;
signal xfer_Ack : std_logic;
signal mdm_Dbus_i : std_logic_vector(0 to 31); -- Check!
signal mdm_CS : std_logic; -- Valid address in a address phase
signal mdm_CS_1 : std_logic; -- Active as long as mdm_CS is active
signal mdm_CS_2 : std_logic;
signal mdm_CS_3 : std_logic;
signal valid_access : std_logic; -- Active during the address phase (2 clock cycles)
signal valid_access_1 : std_logic; -- Will be a 1 clock delayed valid_access signal
signal valid_access_2 : std_logic; -- Active only 1 clock cycle
signal reading : std_logic; -- Valid reading access
signal valid_access_2_reading : std_logic; -- signal to drive out data bus on a read access
signal sl_rdDAck_i : std_logic;
signal sl_wrDAck_i : std_logic;
signal TDI : std_logic;
signal RESET : std_logic;
signal SHIFT : std_logic;
signal CAPTURE : std_logic;
signal TDO : std_logic;
signal mb_debug_enabled_i : std_logic_vector(C_EN_WIDTH-1 downto 0);
signal Dbg_Clk : std_logic;
signal Dbg_TDI : std_logic;
signal Dbg_TDO : std_logic;
signal Dbg_Reg_En : std_logic_vector(0 to 7);
signal Dbg_Capture : std_logic;
signal Dbg_Shift : std_logic;
signal Dbg_Update : std_logic;
signal Debug_Rst_i : std_logic;
subtype Reg_En_TYPE is std_logic_vector(0 to 7);
type Reg_EN_ARRAY is array(0 to 31) of Reg_En_TYPE;
signal Dbg_TDO_I : std_logic_vector(0 to 31);
signal Dbg_Reg_En_I : Reg_EN_ARRAY;
signal Dbg_Rst_I : std_logic_vector(0 to 31);
signal PORT_Selector : std_logic_vector(3 downto 0) := (others => '0');
signal PORT_Selector_1 : std_logic_vector(3 downto 0) := (others => '0');
signal TDI_Shifter : std_logic_vector(3 downto 0) := (others => '0');
signal Sl_rdDBus_int : std_logic_vector(0 to 31);
signal bus_clk : std_logic;
signal bus_rst : std_logic;
signal uart_ip2bus_rdack : std_logic;
signal uart_ip2bus_wrack : std_logic;
signal uart_ip2bus_error : std_logic;
signal uart_ip2bus_data : std_logic_vector(C_REG_DATA_WIDTH-1 downto 0);
signal dbgreg_ip2bus_rdack : std_logic;
signal dbgreg_ip2bus_wrack : std_logic;
signal dbgreg_ip2bus_error : std_logic;
signal dbgreg_ip2bus_data : std_logic_vector(C_REG_DATA_WIDTH-1 downto 0);
signal dbgreg_access_lock : std_logic;
signal dbgreg_force_lock : std_logic;
signal dbgreg_unlocked : std_logic;
signal jtag_access_lock : std_logic;
signal jtag_force_lock : std_logic;
signal jtag_axis_overrun : std_logic;
signal jtag_clear_overrun : std_logic;
-----------------------------------------------------------------------------
-- Register mapping
-----------------------------------------------------------------------------
-- Magic string "01000010" + "00000000" + No of Jtag peripheral units "0010"
-- + MDM Version no "00000110"
--
-- MDM Versions table:
-- 0,1,2,3: Not used
-- 4: opb_mdm v3
-- 5: mdm v1
-- 6: mdm v2
constant New_MDM_Config_Word : std_logic_vector(31 downto 0) :=
"01000010000000000000001000000110";
signal Config_Reg : std_logic_vector(31 downto 0) := New_MDM_Config_Word;
signal MDM_SEL : std_logic;
signal Old_MDM_DRCK : std_logic;
signal Old_MDM_TDI : std_logic;
signal Old_MDM_TDO : std_logic;
signal Old_MDM_SEL : std_logic;
signal Old_MDM_SEL_Mux : std_logic;
signal Old_MDM_SHIFT : std_logic;
signal Old_MDM_UPDATE : std_logic;
signal Old_MDM_RESET : std_logic;
signal Old_MDM_CAPTURE : std_logic;
signal JTAG_Dec_Sel : std_logic_vector(15 downto 0);
begin -- architecture IMP
config_reset_i <= Config_Reset when C_USE_CONFIG_RESET /= 0 else '0';
-----------------------------------------------------------------------------
-- TDI Shift Register
-----------------------------------------------------------------------------
-- Shifts data in when PORT 0 is selected. PORT 0 does not actually
-- exist externaly, but gets selected after asserting the SELECT signal.
-- The first value shifted in after SELECT goes high will select the new
-- PORT.
JTAG_Mux_Shifting : process (DRCK, SEL, config_reset_i)
begin
if SEL = '0' or config_reset_i = '1' then
TDI_Shifter <= (others => '0');
elsif DRCK'event and DRCK = '1' then
if MDM_SEL = '1' and SHIFT = '1' then
TDI_Shifter <= TDI & TDI_Shifter(3 downto 1);
end if;
end if;
end process JTAG_Mux_Shifting;
-----------------------------------------------------------------------------
-- PORT Selector Register
-----------------------------------------------------------------------------
-- Captures the shifted data when PORT 0 is selected. The data is captured at
-- the end of the BSCAN transaction (i.e. when the update signal goes low) to
-- prevent any other BSCAN signals to assert incorrectly.
-- Reference : XAPP 139
PORT_Selector_Updating : process (UPDATE, SEL, config_reset_i)
begin
if SEL = '0' or config_reset_i = '1' then
PORT_Selector <= (others => '0');
elsif Update'event and Update = '0' then
PORT_Selector <= Port_Selector_1;
end if;
end process PORT_Selector_Updating;
PORT_Selector_Updating_1 : process (UPDATE, SEL, config_reset_i)
begin
if SEL = '0' or config_reset_i = '1' then
PORT_Selector_1 <= (others => '0');
elsif Update'event and Update = '1' then
if MDM_SEL = '1' then
PORT_Selector_1 <= TDI_Shifter;
end if;
end if;
end process PORT_Selector_Updating_1;
-----------------------------------------------------------------------------
-- Configuration register
-----------------------------------------------------------------------------
-- TODO Can be replaced by SRLs
Config_Shifting : process (DRCK, SHIFT, config_reset_i)
begin
if SHIFT = '0' or config_reset_i = '1' then
Config_Reg <= New_MDM_Config_Word;
elsif DRCK'event and DRCK = '1' then -- rising clock edge
Config_Reg <= '0' & Config_Reg(31 downto 1);
end if;
end process Config_Shifting;
-----------------------------------------------------------------------------
-- Muxing and demuxing of JTAG Bscan User 1/2/3/4 signals
--
-- This block enables the older MDM/JTAG to co-exist with the newer
-- JTAG multiplexer block
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- TDO Mux
-----------------------------------------------------------------------------
with PORT_Selector select
TDO <=
Config_Reg(0) when "0000",
Old_MDM_TDO when "0001",
Ext_JTAG_TDO when "0010",
'1' when others;
-----------------------------------------------------------------------------
-- SELECT Decoder
-----------------------------------------------------------------------------
MDM_SEL <= SEL when PORT_Selector = "0000" else '0';
Old_MDM_SEL_Mux <= SEL when PORT_Selector = "0001" else '0';
Ext_JTAG_SEL <= SEL when PORT_Selector = "0010" else '0';
-----------------------------------------------------------------------------
-- Old MDM signals
-----------------------------------------------------------------------------
Old_MDM_DRCK <= DRCK;
Old_MDM_TDI <= TDI;
Old_MDM_CAPTURE <= CAPTURE;
Old_MDM_SHIFT <= SHIFT;
Old_MDM_UPDATE <= UPDATE;
Old_MDM_RESET <= RESET;
-----------------------------------------------------------------------------
-- External JTAG signals
-----------------------------------------------------------------------------
Ext_JTAG_DRCK <= DRCK;
Ext_JTAG_TDI <= TDI;
Ext_JTAG_CAPTURE <= CAPTURE;
Ext_JTAG_SHIFT <= SHIFT;
Ext_JTAG_UPDATE <= UPDATE;
Ext_JTAG_RESET <= RESET;
-----------------------------------------------------------------------------
-- AXI bus interface
-----------------------------------------------------------------------------
ip2bus_rdack <= uart_ip2bus_rdack or dbgreg_ip2bus_rdack;
ip2bus_wrack <= uart_ip2bus_wrack or dbgreg_ip2bus_wrack;
ip2bus_error <= uart_ip2bus_error or dbgreg_ip2bus_error;
ip2bus_data <= uart_ip2bus_data or dbgreg_ip2bus_data;
Use_AXI_IPIF : if (C_USE_UART = 1) or (C_DBG_REG_ACCESS = 1) generate
begin
bus_clk <= bus2ip_clk;
bus_rst <= not bus2ip_resetn;
end generate Use_AXI_IPIF;
No_AXI_IPIF : if (C_USE_UART = 0) and (C_DBG_REG_ACCESS = 0) generate
begin
bus_clk <= '0';
bus_rst <= '0';
end generate No_AXI_IPIF;
-----------------------------------------------------------------------------
-- UART
-----------------------------------------------------------------------------
Use_Uart : if (C_USE_UART = 1) generate
-- Read Only
signal status_Reg : std_logic_vector(7 downto 0);
-- bit 4 enable_interrupts
-- bit 3 tx_Buffer_Full
-- bit 2 tx_Buffer_Empty
-- bit 1 rx_Buffer_Full
-- bit 0 rx_Data_Present
-- Write Only
-- Control Register
-- bit 7-5 Dont'Care
-- bit 4 enable_interrupts
-- bit 3 Dont'Care
-- bit 2 Clear Ext BRK signal
-- bit 1 Reset_RX_FIFO
-- bit 0 Reset_TX_FIFO
signal tx_Buffer_Empty_Pre : std_logic;
begin
---------------------------------------------------------------------------
-- Acknowledgement and error signals
---------------------------------------------------------------------------
uart_ip2bus_rdack <= bus2ip_rdce(0) or bus2ip_rdce(2) or bus2ip_rdce(1)
or bus2ip_rdce(3);
uart_ip2bus_wrack <= bus2ip_wrce(1) or bus2ip_wrce(3) or bus2ip_wrce(0)
or bus2ip_wrce(2);
uart_ip2bus_error <= ((bus2ip_rdce(0) and not rx_Data_Present) or
(bus2ip_wrce(1) and tx_Buffer_Full) );
---------------------------------------------------------------------------
-- Status register
---------------------------------------------------------------------------
status_Reg(0) <= rx_Data_Present;
status_Reg(1) <= rx_Buffer_Full;
status_Reg(2) <= tx_Buffer_Empty;
status_Reg(3) <= tx_Buffer_Full;
status_Reg(4) <= enable_interrupts;
status_Reg(7 downto 5) <= "000";
---------------------------------------------------------------------------
-- Control Register
---------------------------------------------------------------------------
CTRL_REG_DFF : process (bus2ip_clk) is
begin
if bus2ip_clk'event and bus2ip_clk = '1' then -- rising clock edge
if bus2ip_resetn = '0' then -- synchronous reset (active low)
enable_interrupts <= '0';
clear_Ext_BRK <= '0';
reset_RX_FIFO <= '1';
reset_TX_FIFO <= '1';
elsif (bus2ip_wrce(3) = '1') then -- Control Register is reg 3
enable_interrupts <= bus2ip_data(4); -- Bit 4 in control reg
clear_Ext_BRK <= bus2ip_data(2); -- Bit 2 in control reg
reset_RX_FIFO <= bus2ip_data(1); -- Bit 1 in control reg
reset_TX_FIFO <= bus2ip_data(0); -- Bit 0 in control reg
else
clear_Ext_BRK <= '0';
reset_RX_FIFO <= '0';
reset_TX_FIFO <= '0';
end if;
end if;
end process CTRL_REG_DFF;
---------------------------------------------------------------------------
-- Read bus interface
---------------------------------------------------------------------------
READ_MUX : process (status_reg, bus2ip_rdce(2), bus2ip_rdce(0), rx_Data) is
begin
uart_ip2bus_data <= (others => '0');
if (bus2ip_rdce(2) = '1') then -- Status register is reg 2
uart_ip2bus_data(status_reg'length-1 downto 0) <= status_reg;
elsif (bus2ip_rdce(0) = '1') then -- RX FIFO is reg 0
uart_ip2bus_data(C_UART_WIDTH-1 downto 0) <= rx_Data;
end if;
end process READ_MUX;
---------------------------------------------------------------------------
-- Write bus interface
---------------------------------------------------------------------------
tx_Data <= bus2ip_data(C_UART_WIDTH-1 downto 0);
---------------------------------------------------------------------------
-- Read and write pulses to the FIFOs
---------------------------------------------------------------------------
write_TX_FIFO <= bus2ip_wrce(1); -- TX FIFO is reg 1
read_RX_FIFO <= bus2ip_rdce(0); -- RX FIFO is reg 0
-- Sample the tx_Buffer_Empty signal in order to detect a rising edge
TX_Buffer_Empty_FDRE : FDRE
port map (
Q => tx_Buffer_Empty_Pre,
C => bus_clk,
CE => '1',
D => tx_Buffer_Empty,
R => write_TX_FIFO);
---------------------------------------------------------------------------
-- Interrupt handling
---------------------------------------------------------------------------
Interrupt <= enable_interrupts and ( rx_Data_Present or
( tx_Buffer_Empty and
not tx_Buffer_Empty_Pre ) );
end generate Use_UART;
No_UART : if (C_USE_UART = 0) generate
begin
uart_ip2bus_rdack <= '0';
uart_ip2bus_wrack <= '0';
uart_ip2bus_error <= '0';
uart_ip2bus_data <= (others => '0');
Interrupt <= '0';
reset_TX_FIFO <= '1';
reset_RX_FIFO <= '1';
enable_interrupts <= '0';
clear_Ext_BRK <= '0';
tx_Data <= (others => '0');
write_TX_FIFO <= '0';
read_RX_FIFO <= '0';
end generate No_UART;
-----------------------------------------------------------------------------
-- Debug Register Access
-----------------------------------------------------------------------------
Use_Dbg_Reg_Access : if (C_DBG_REG_ACCESS = 1) generate
type state_type is
(idle, select_dr, capture_dr, shift_dr, exit1, pause, exit2, update_dr, cmd_done, data_done);
signal bit_size : std_logic_vector(8 downto 0);
signal cmd_val : std_logic_vector(7 downto 0);
signal type_lock : std_logic_vector(1 downto 0);
signal use_mdm : std_logic;
signal reg_data : std_logic_vector(31 downto 0);
signal bit_cnt : std_logic_vector(0 to 8);
signal clk_cnt : std_logic_vector(0 to C_CLOCK_BITS / 2);
signal clk_fall : boolean;
signal clk_rise : boolean;
signal shifting : boolean;
signal data_shift : boolean;
signal direction : std_logic;
signal rd_wr_n : boolean;
signal rdack_data : std_logic;
signal selected : std_logic := '0';
signal shift_index : std_logic_vector(0 to 4);
signal state : state_type;
signal unlocked : boolean;
signal wrack_data : std_logic;
signal dbgreg_TDI : std_logic;
signal dbgreg_RESET : std_logic;
signal dbgreg_SHIFT : std_logic;
signal dbgreg_CAPTURE : std_logic;
signal dbgreg_SEL : std_logic;
begin
---------------------------------------------------------------------------
-- Acknowledgement and error signals
---------------------------------------------------------------------------
dbgreg_ip2bus_rdack <= bus2ip_rdce(4) or rdack_data;
dbgreg_ip2bus_wrack <= bus2ip_wrce(4) or bus2ip_wrce(6) or wrack_data;
dbgreg_ip2bus_error <= (bus2ip_rdce(5) or bus2ip_wrce(5)) and not dbgreg_access_lock;
---------------------------------------------------------------------------
-- Control register
---------------------------------------------------------------------------
CTRL_REG_DFF : process (bus2ip_clk) is
begin
if bus2ip_clk'event and bus2ip_clk = '1' then -- rising clock edge
if bus2ip_resetn = '0' then -- synchronous reset (active low)
use_mdm <= '0';
type_lock <= (others => '0');
cmd_val <= (others => '0');
bit_size <= (others => '0');
elsif (bus2ip_wrce(4) = '1') and unlocked then -- Control Register is reg 4
type_lock <= bus2ip_data(19 downto 18);
use_mdm <= bus2ip_data(17);
cmd_val <= bus2ip_data(16 downto 9);
bit_size <= bus2ip_data(8 downto 0);
end if;
end if;
end process CTRL_REG_DFF;
---------------------------------------------------------------------------
-- Data register and TAP state machine
---------------------------------------------------------------------------
DATA_REG_DFF : process (bus2ip_clk) is
begin
if bus2ip_clk'event and bus2ip_clk = '1' then -- rising clock edge
if bus2ip_resetn = '0' then -- synchronous reset (active low)
reg_data <= (others => '0');
rdack_data <= '0';
wrack_data <= '0';
state <= idle;
shifting <= false;
data_shift <= false;
direction <= '1';
rd_wr_n <= false;
clk_rise <= false;
clk_fall <= false;
clk_cnt <= (others => '0');
bit_cnt <= "000000111";
shift_index <= "00000";
dbgreg_TDI <= '0';
dbgreg_RESET <= '0';
dbgreg_SHIFT <= '0';
dbgreg_CAPTURE <= '0';
dbgreg_SEL <= '0';
DbgReg_DRCK <= '0';
DbgReg_UPDATE <= '0';
selected <= '0';
else
rdack_data <= '0';
wrack_data <= '0';
if unlocked and dbgreg_access_lock = '1' and not shifting then
if bus2ip_wrce(5) = '1' then
reg_data <= bus2ip_data;
shifting <= true;
rd_wr_n <= false;
end if;
if bus2ip_rdce(5) = '1' then
shifting <= true;
rd_wr_n <= true;
end if;
end if;
if clk_rise then
case state is
when idle =>
-- Idle - Start when data access occurs
if shifting then
state <= select_dr;
end if;
bit_cnt <= "000000111";
shift_index <= "00000";
selected <= '0';
when select_dr =>
-- TAP state Select DR - Set SEL
state <= capture_dr;
dbgreg_SEL <= '1';
selected <= '1';
when capture_dr =>
-- TAP state Capture DR - Set CAPTURE and pulse DRCK
state <= shift_dr;
dbgreg_CAPTURE <= '1';
DbgReg_DRCK <= '1';
when shift_dr =>
-- TAP state Shift DR - Set SHIFT and pulse DRCK until done or pause
if bit_cnt = (bit_cnt'range => '0') then
state <= exit2; -- Shift done
elsif shift_index = (shift_index'range => direction) then
state <= exit1; -- Acknowledge and pause until next word
if rd_wr_n then
rdack_data <= '1';
else
wrack_data <= '1';
end if;
end if;
if data_shift then
dbgreg_TDI <= reg_data(to_integer(unsigned(shift_index)));
reg_data(to_integer(unsigned(shift_index))) <= Old_MDM_TDO;
else
dbgreg_TDI <= cmd_val(to_integer(unsigned(shift_index)));
end if;
dbgreg_CAPTURE <= '0';
dbgreg_SHIFT <= '1';
DbgReg_DRCK <= '1';
bit_cnt <= std_logic_vector(unsigned(bit_cnt) - 1);
if direction = '1' then
shift_index <= std_logic_vector(unsigned(shift_index) + 1);
else
shift_index <= std_logic_vector(unsigned(shift_index) - 1);
end if;
when exit1 =>
-- TAP state Exit1 DR - End shift and go to pause
state <= pause;
shifting <= false;
dbgreg_SHIFT <= '0';
DbgReg_DRCK <= '0';
when pause =>
-- TAP state Pause DR - Pause until new data access or abort
if dbgreg_access_lock = '0' then
state <= exit2; -- Abort shift
elsif shifting then
state <= shift_dr; -- Continue with next word
end if;
DbgReg_DRCK <= '0';
when exit2 =>
-- TAP state Exit2 DR - Delay before update
state <= update_dr;
dbgreg_SHIFT <= '0';
DbgReg_DRCK <= '0';
when update_dr =>
-- TAP state Update DR - Pulse UPDATE and acknowledge data access
if data_shift then
state <= data_done;
if rd_wr_n then
rdack_data <= '1';
else
wrack_data <= '1';
end if;
else
state <= cmd_done;
end if;
DbgReg_UPDATE <= '1';
when cmd_done =>
-- Command phase done - Continue with data phase
state <= select_dr;
data_shift <= true;
bit_cnt <= bit_size;
if use_mdm = '1' then
shift_index <= (others => '0');
else
shift_index <= bit_size(shift_index'length - 1 downto 0);
end if;
direction <= use_mdm;
DbgReg_UPDATE <= '0';
when data_done =>
-- Data phase done - End shifting and go back to idle
state <= idle;
data_shift <= false;
shifting <= false;
direction <= '1';
DbgReg_UPDATE <= '0';
end case;
elsif clk_fall then
DbgReg_DRCK <= '0';
end if;
if clk_cnt(clk_cnt'left + 1 to clk_cnt'right) = (clk_cnt'left + 1 to clk_cnt'right => '0') then
clk_rise <= (clk_cnt(clk_cnt'left) = '0');
clk_fall <= (clk_cnt(clk_cnt'left) = '1');
else
clk_rise <= false;
clk_fall <= false;
end if;
clk_cnt <= std_logic_vector(unsigned(clk_cnt) - 1);
end if;
end if;
end process DATA_REG_DFF;
---------------------------------------------------------------------------
-- Lock register
---------------------------------------------------------------------------
LOCK_REG_DFF : process (bus2ip_clk) is
begin
if bus2ip_clk'event and bus2ip_clk = '1' then -- rising clock edge
if bus2ip_resetn = '0' then -- synchronous reset (active low)
unlocked <= false;
elsif (bus2ip_wrce(6) = '1') then -- Lock Register is reg 6
unlocked <= (bus2ip_data(15 downto 0) = X"EBAB") and (not unlocked);
end if;
end if;
end process LOCK_REG_DFF;
---------------------------------------------------------------------------
-- Read bus interface
---------------------------------------------------------------------------
READ_MUX : process (bus2ip_rdce(4), rdack_data, dbgreg_access_lock, reg_data) is
begin
dbgreg_ip2bus_data <= (others => '0');
if (bus2ip_rdce(4) = '1') then -- Status register is reg 4
dbgreg_ip2bus_data(0) <= dbgreg_access_lock;
elsif rdack_data = '1' then -- Data register is reg 5
dbgreg_ip2bus_data <= reg_data;
end if;
end process READ_MUX;
---------------------------------------------------------------------------
-- Access lock handling
---------------------------------------------------------------------------
Handle_Access_Lock : process (bus2ip_clk) is
variable jtag_access_lock_1 : std_logic;
variable jtag_force_lock_1 : std_logic;
variable jtag_clear_overrun_1 : std_logic;
variable jtag_busy_1 : std_logic;
attribute ASYNC_REG : string;
attribute ASYNC_REG of jtag_access_lock_1 : variable is "TRUE";
attribute ASYNC_REG of jtag_force_lock_1 : variable is "TRUE";
attribute ASYNC_REG of jtag_clear_overrun_1 : variable is "TRUE";
attribute ASYNC_REG of jtag_busy_1 : variable is "TRUE";
begin
if bus2ip_clk'event and bus2ip_clk = '1' then -- rising clock edge
if bus2ip_resetn = '0' then -- synchronous reset (active low)
dbgreg_access_lock <= '0';
dbgreg_force_lock <= '0';
dbgreg_unlocked <= '0';
jtag_axis_overrun <= '0';
jtag_access_lock_1 := '0';
jtag_force_lock_1 := '0';
jtag_clear_overrun_1 := '0';
jtag_busy_1 := '0';
else
-- Unlock after last access for type "01"
if state = data_done and type_lock = "01" then
dbgreg_access_lock <= '0';
end if;
-- Write to Debug Access Control Register
if bus2ip_wrce(4) = '1' then
case bus2ip_data(19 downto 18) is
when "00" => -- Release lock to abort atomic sequence
dbgreg_access_lock <= '0';
when "01" | "10" => -- Lock before first access
if dbgreg_access_lock = '0' and jtag_busy_1 = '0' and jtag_access_lock_1 = '0' then
dbgreg_access_lock <= '1';
end if;
when "11" => -- Force access lock
dbgreg_access_lock <= '1';
dbgreg_force_lock <= '1';
-- coverage off
when others =>
null;
-- coverage on
end case;
else
dbgreg_force_lock <= '0';
end if;
jtag_access_lock_1 := JTAG_Access_Lock;
-- JTAG force lock
if jtag_force_lock_1 = '1' then
dbgreg_access_lock <= '0';
dbgreg_unlocked <= '1';
else
dbgreg_unlocked <= '0';
end if;
jtag_force_lock_1 := jtag_force_lock;
-- JTAG overrun detection
if selected = '1' and jtag_busy_1 = '1' then
jtag_axis_overrun <= '1';
elsif jtag_clear_overrun_1 = '1' then
jtag_axis_overrun <= '0';
end if;
jtag_clear_overrun_1 := jtag_clear_overrun;
jtag_busy_1 := jtag_busy;
end if;
end if;
end process;
DbgReg_Select <= selected;
Old_MDM_SEL <= dbgreg_SEL when selected = '1' else Old_MDM_SEL_Mux;
TDI <= dbgreg_TDI when selected = '1' else JTAG_TDI;
RESET <= dbgreg_RESET when selected = '1' else JTAG_RESET;
SHIFT <= dbgreg_SHIFT when selected = '1' else JTAG_SHIFT;
CAPTURE <= dbgreg_CAPTURE when selected = '1' else JTAG_CAPTURE;
JTAG_TDO <= '0' when selected = '1' else TDO;
end generate Use_Dbg_Reg_Access;
No_Dbg_Reg_Access : if (C_DBG_REG_ACCESS = 0) generate
begin
DbgReg_DRCK <= '0';
DbgReg_UPDATE <= '0';
DbgReg_Select <= '0';
dbgreg_ip2bus_rdack <= '0';
dbgreg_ip2bus_wrack <= '0';
dbgreg_ip2bus_error <= '0';
dbgreg_ip2bus_data <= (others => '0');
dbgreg_access_lock <= '0';
dbgreg_force_lock <= '0';
dbgreg_unlocked <= '0';
jtag_axis_overrun <= '0';
Old_MDM_SEL <= Old_MDM_SEL_Mux;
TDI <= JTAG_TDI;
RESET <= JTAG_RESET;
SHIFT <= JTAG_SHIFT;
CAPTURE <= JTAG_CAPTURE;
JTAG_TDO <= TDO;
end generate No_Dbg_Reg_Access;
---------------------------------------------------------------------------
-- Instantiating the receive and transmit modules
---------------------------------------------------------------------------
JTAG_CONTROL_I : JTAG_CONTROL
generic map (
C_MB_DBG_PORTS => C_MB_DBG_PORTS,
C_USE_CONFIG_RESET => C_USE_CONFIG_RESET,
C_DBG_REG_ACCESS => C_DBG_REG_ACCESS,
C_DBG_MEM_ACCESS => C_DBG_MEM_ACCESS,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_USE_CROSS_TRIGGER => C_USE_CROSS_TRIGGER,
C_USE_UART => C_USE_UART,
C_UART_WIDTH => C_UART_WIDTH,
C_EN_WIDTH => C_EN_WIDTH
)
port map (
Config_Reset => config_reset_i, -- [in std_logic]
Clk => bus_clk, -- [in std_logic]
Rst => bus_rst, -- [in std_logic]
Clear_Ext_BRK => clear_Ext_BRK, -- [in std_logic]
Ext_BRK => Ext_BRK, -- [out std_logic]
Ext_NM_BRK => Ext_NM_BRK, -- [out std_logic]
Debug_SYS_Rst => Debug_SYS_Rst, -- [out std_logic]
Debug_Rst => Debug_Rst_i, -- [out std_logic]
Read_RX_FIFO => read_RX_FIFO, -- [in std_logic]
Reset_RX_FIFO => reset_RX_FIFO, -- [in std_logic]
RX_Data => rx_Data, -- [out std_logic_vector(0 to 7)]
RX_Data_Present => rx_Data_Present, -- [out std_logic]
RX_Buffer_Full => rx_Buffer_Full, -- [out std_logic]
Write_TX_FIFO => write_TX_FIFO, -- [in std_logic]
Reset_TX_FIFO => reset_TX_FIFO, -- [in std_logic]
TX_Data => tx_Data, -- [in std_logic_vector(0 to 7)]
TX_Buffer_Full => tx_Buffer_Full, -- [out std_logic]
TX_Buffer_Empty => tx_Buffer_Empty, -- [out std_logic]
-- Debug Register Access signals
DbgReg_Access_Lock => dbgreg_access_lock, -- [in std_logic]
DbgReg_Force_Lock => dbgreg_force_lock, -- [in std_logic]
DbgReg_Unlocked => dbgreg_unlocked, -- [in std_logic]
JTAG_Access_Lock => jtag_access_lock, -- [out std_logic]
JTAG_Force_Lock => jtag_force_lock, -- [out std_logic]
JTAG_AXIS_Overrun => jtag_axis_overrun, -- [in std_logic]
JTAG_Clear_Overrun => jtag_clear_overrun, -- [out std_logic]
-- MDM signals
TDI => Old_MDM_TDI, -- [in std_logic]
RESET => Old_MDM_RESET, -- [in std_logic]
UPDATE => Old_MDM_UPDATE, -- [in std_logic]
SHIFT => Old_MDM_SHIFT, -- [in std_logic]
CAPTURE => Old_MDM_CAPTURE, -- [in std_logic]
SEL => Old_MDM_SEL, -- [in std_logic]
DRCK => Old_MDM_DRCK, -- [in std_logic]
TDO => Old_MDM_TDO, -- [out std_logic]
-- AXI Master signals
M_AXI_ACLK => M_AXI_ACLK, -- [in std_logic]
M_AXI_ARESETn => M_AXI_ARESETn, -- [in std_logic]
Master_rd_start => Master_rd_start, -- [out std_logic]
Master_rd_addr => Master_rd_addr, -- [out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0)]
Master_rd_len => Master_rd_len, -- [out std_logic_vector(4 downto 0)]
Master_rd_size => Master_rd_size, -- [out std_logic_vector(1 downto 0)]
Master_rd_excl => Master_rd_excl, -- [out std_logic]
Master_rd_idle => Master_rd_idle, -- [out std_logic]
Master_rd_resp => Master_rd_resp, -- [out std_logic_vector(1 downto 0)]
Master_wr_start => Master_wr_start, -- [out std_logic]
Master_wr_addr => Master_wr_addr, -- [out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0)]
Master_wr_len => Master_wr_len, -- [out std_logic_vector(4 downto 0)]
Master_wr_size => Master_wr_size, -- [out std_logic_vector(1 downto 0)]
Master_wr_excl => Master_wr_excl, -- [out std_logic]
Master_wr_idle => Master_wr_idle, -- [out std_logic]
Master_wr_resp => Master_wr_resp, -- [out std_logic_vector(1 downto 0)]
Master_data_rd => Master_data_rd, -- [out std_logic]
Master_data_out => Master_data_out, -- [in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0)]
Master_data_exists => Master_data_exists, -- [in std_logic]
Master_data_wr => Master_data_wr, -- [out std_logic]
Master_data_in => Master_data_in, -- [out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0)]
Master_data_empty => Master_data_empty, -- [in std_logic]
-- MicroBlaze Debug Signals
MB_Debug_Enabled => mb_debug_enabled_i, -- [out std_logic_vector(7 downto 0)]
Dbg_Clk => Dbg_Clk, -- [out std_logic]
Dbg_TDI => Dbg_TDI, -- [in std_logic]
Dbg_TDO => Dbg_TDO, -- [out std_logic]
Dbg_Reg_En => Dbg_Reg_En, -- [out std_logic_vector(0 to 7)]
Dbg_Capture => Dbg_Capture, -- [out std_logic]
Dbg_Shift => Dbg_Shift, -- [out std_logic]
Dbg_Update => Dbg_Update, -- [out std_logic]
-- MicroBlaze Cross Trigger Signals
Dbg_Trig_In_0 => Dbg_Trig_In_0, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_1 => Dbg_Trig_In_1, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_2 => Dbg_Trig_In_2, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_3 => Dbg_Trig_In_3, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_4 => Dbg_Trig_In_4, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_5 => Dbg_Trig_In_5, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_6 => Dbg_Trig_In_6, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_7 => Dbg_Trig_In_7, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_8 => Dbg_Trig_In_8, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_9 => Dbg_Trig_In_9, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_10 => Dbg_Trig_In_10, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_11 => Dbg_Trig_In_11, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_12 => Dbg_Trig_In_12, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_13 => Dbg_Trig_In_13, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_14 => Dbg_Trig_In_14, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_15 => Dbg_Trig_In_15, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_16 => Dbg_Trig_In_16, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_17 => Dbg_Trig_In_17, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_18 => Dbg_Trig_In_18, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_19 => Dbg_Trig_In_19, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_20 => Dbg_Trig_In_20, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_21 => Dbg_Trig_In_21, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_22 => Dbg_Trig_In_22, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_23 => Dbg_Trig_In_23, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_24 => Dbg_Trig_In_24, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_25 => Dbg_Trig_In_25, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_26 => Dbg_Trig_In_26, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_27 => Dbg_Trig_In_27, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_28 => Dbg_Trig_In_28, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_29 => Dbg_Trig_In_29, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_30 => Dbg_Trig_In_30, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_31 => Dbg_Trig_In_31, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_0 => Dbg_Trig_Ack_In_0, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_1 => Dbg_Trig_Ack_In_1, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_2 => Dbg_Trig_Ack_In_2, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_3 => Dbg_Trig_Ack_In_3, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_4 => Dbg_Trig_Ack_In_4, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_5 => Dbg_Trig_Ack_In_5, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_6 => Dbg_Trig_Ack_In_6, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_7 => Dbg_Trig_Ack_In_7, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_8 => Dbg_Trig_Ack_In_8, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_9 => Dbg_Trig_Ack_In_9, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_10 => Dbg_Trig_Ack_In_10, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_11 => Dbg_Trig_Ack_In_11, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_12 => Dbg_Trig_Ack_In_12, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_13 => Dbg_Trig_Ack_In_13, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_14 => Dbg_Trig_Ack_In_14, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_15 => Dbg_Trig_Ack_In_15, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_16 => Dbg_Trig_Ack_In_16, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_17 => Dbg_Trig_Ack_In_17, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_18 => Dbg_Trig_Ack_In_18, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_19 => Dbg_Trig_Ack_In_19, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_20 => Dbg_Trig_Ack_In_20, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_21 => Dbg_Trig_Ack_In_21, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_22 => Dbg_Trig_Ack_In_22, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_23 => Dbg_Trig_Ack_In_23, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_24 => Dbg_Trig_Ack_In_24, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_25 => Dbg_Trig_Ack_In_25, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_26 => Dbg_Trig_Ack_In_26, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_27 => Dbg_Trig_Ack_In_27, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_28 => Dbg_Trig_Ack_In_28, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_29 => Dbg_Trig_Ack_In_29, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_30 => Dbg_Trig_Ack_In_30, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_31 => Dbg_Trig_Ack_In_31, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_0 => Dbg_Trig_Out_0, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_1 => Dbg_Trig_Out_1, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_2 => Dbg_Trig_Out_2, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_3 => Dbg_Trig_Out_3, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_4 => Dbg_Trig_Out_4, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_5 => Dbg_Trig_Out_5, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_6 => Dbg_Trig_Out_6, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_7 => Dbg_Trig_Out_7, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_8 => Dbg_Trig_Out_8, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_9 => Dbg_Trig_Out_9, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_10 => Dbg_Trig_Out_10, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_11 => Dbg_Trig_Out_11, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_12 => Dbg_Trig_Out_12, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_13 => Dbg_Trig_Out_13, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_14 => Dbg_Trig_Out_14, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_15 => Dbg_Trig_Out_15, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_16 => Dbg_Trig_Out_16, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_17 => Dbg_Trig_Out_17, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_18 => Dbg_Trig_Out_18, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_19 => Dbg_Trig_Out_19, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_20 => Dbg_Trig_Out_20, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_21 => Dbg_Trig_Out_21, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_22 => Dbg_Trig_Out_22, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_23 => Dbg_Trig_Out_23, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_24 => Dbg_Trig_Out_24, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_25 => Dbg_Trig_Out_25, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_26 => Dbg_Trig_Out_26, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_27 => Dbg_Trig_Out_27, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_28 => Dbg_Trig_Out_28, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_29 => Dbg_Trig_Out_29, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_30 => Dbg_Trig_Out_30, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_31 => Dbg_Trig_Out_31, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_0 => Dbg_Trig_Ack_Out_0, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_1 => Dbg_Trig_Ack_Out_1, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_2 => Dbg_Trig_Ack_Out_2, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_3 => Dbg_Trig_Ack_Out_3, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_4 => Dbg_Trig_Ack_Out_4, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_5 => Dbg_Trig_Ack_Out_5, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_6 => Dbg_Trig_Ack_Out_6, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_7 => Dbg_Trig_Ack_Out_7, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_8 => Dbg_Trig_Ack_Out_8, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_9 => Dbg_Trig_Ack_Out_9, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_10 => Dbg_Trig_Ack_Out_10, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_11 => Dbg_Trig_Ack_Out_11, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_12 => Dbg_Trig_Ack_Out_12, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_13 => Dbg_Trig_Ack_Out_13, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_14 => Dbg_Trig_Ack_Out_14, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_15 => Dbg_Trig_Ack_Out_15, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_16 => Dbg_Trig_Ack_Out_16, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_17 => Dbg_Trig_Ack_Out_17, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_18 => Dbg_Trig_Ack_Out_18, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_19 => Dbg_Trig_Ack_Out_19, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_20 => Dbg_Trig_Ack_Out_20, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_21 => Dbg_Trig_Ack_Out_21, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_22 => Dbg_Trig_Ack_Out_22, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_23 => Dbg_Trig_Ack_Out_23, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_24 => Dbg_Trig_Ack_Out_24, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_25 => Dbg_Trig_Ack_Out_25, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_26 => Dbg_Trig_Ack_Out_26, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_27 => Dbg_Trig_Ack_Out_27, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_28 => Dbg_Trig_Ack_Out_28, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_29 => Dbg_Trig_Ack_Out_29, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_30 => Dbg_Trig_Ack_Out_30, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_31 => Dbg_Trig_Ack_Out_31, -- [in std_logic_vector(0 to 7)]
Ext_Trig_In => Ext_Trig_In, -- [in std_logic_vector(0 to 3)]
Ext_Trig_Ack_In => Ext_Trig_Ack_In, -- [out std_logic_vector(0 to 3)]
Ext_Trig_Out => Ext_Trig_Out, -- [out std_logic_vector(0 to 3)]
Ext_Trig_Ack_Out => Ext_Trig_Ack_Out -- [in std_logic_vector(0 to 3)]
);
-----------------------------------------------------------------------------
-- Enables for each debug port
-----------------------------------------------------------------------------
Generate_Dbg_Port_Signals : process (mb_debug_enabled_i, Dbg_Reg_En,
Dbg_TDO_I, Debug_Rst_I)
variable dbg_tdo_or : std_logic;
begin -- process Generate_Dbg_Port_Signals
dbg_tdo_or := '0';
for I in 0 to C_EN_WIDTH-1 loop
if (mb_debug_enabled_i(I) = '1') then
Dbg_Reg_En_I(I) <= Dbg_Reg_En;
Dbg_Rst_I(I) <= Debug_Rst_i;
else
Dbg_Reg_En_I(I) <= (others => '0');
Dbg_Rst_I(I) <= '0';
end if;
dbg_tdo_or := dbg_tdo_or or Dbg_TDO_I(I);
end loop; -- I
for I in C_EN_WIDTH to 31 loop
Dbg_Reg_En_I(I) <= (others => '0');
Dbg_Rst_I(I) <= '0';
end loop; -- I
Dbg_TDO <= dbg_tdo_or;
end process Generate_Dbg_Port_Signals;
MB_Debug_Enabled <= mb_debug_enabled_i;
Dbg_Clk_0 <= Dbg_Clk;
Dbg_TDI_0 <= Dbg_TDI;
Dbg_Reg_En_0 <= Dbg_Reg_En_I(0);
Dbg_Capture_0 <= Dbg_Capture;
Dbg_Shift_0 <= Dbg_Shift;
Dbg_Update_0 <= Dbg_Update;
Dbg_Rst_0 <= Dbg_Rst_I(0);
Dbg_TDO_I(0) <= Dbg_TDO_0;
Dbg_Clk_1 <= Dbg_Clk;
Dbg_TDI_1 <= Dbg_TDI;
Dbg_Reg_En_1 <= Dbg_Reg_En_I(1);
Dbg_Capture_1 <= Dbg_Capture;
Dbg_Shift_1 <= Dbg_Shift;
Dbg_Update_1 <= Dbg_Update;
Dbg_Rst_1 <= Dbg_Rst_I(1);
Dbg_TDO_I(1) <= Dbg_TDO_1;
Dbg_Clk_2 <= Dbg_Clk;
Dbg_TDI_2 <= Dbg_TDI;
Dbg_Reg_En_2 <= Dbg_Reg_En_I(2);
Dbg_Capture_2 <= Dbg_Capture;
Dbg_Shift_2 <= Dbg_Shift;
Dbg_Update_2 <= Dbg_Update;
Dbg_Rst_2 <= Dbg_Rst_I(2);
Dbg_TDO_I(2) <= Dbg_TDO_2;
Dbg_Clk_3 <= Dbg_Clk;
Dbg_TDI_3 <= Dbg_TDI;
Dbg_Reg_En_3 <= Dbg_Reg_En_I(3);
Dbg_Capture_3 <= Dbg_Capture;
Dbg_Shift_3 <= Dbg_Shift;
Dbg_Update_3 <= Dbg_Update;
Dbg_Rst_3 <= Dbg_Rst_I(3);
Dbg_TDO_I(3) <= Dbg_TDO_3;
Dbg_Clk_4 <= Dbg_Clk;
Dbg_TDI_4 <= Dbg_TDI;
Dbg_Reg_En_4 <= Dbg_Reg_En_I(4);
Dbg_Capture_4 <= Dbg_Capture;
Dbg_Shift_4 <= Dbg_Shift;
Dbg_Update_4 <= Dbg_Update;
Dbg_Rst_4 <= Dbg_Rst_I(4);
Dbg_TDO_I(4) <= Dbg_TDO_4;
Dbg_Clk_5 <= Dbg_Clk;
Dbg_TDI_5 <= Dbg_TDI;
Dbg_Reg_En_5 <= Dbg_Reg_En_I(5);
Dbg_Capture_5 <= Dbg_Capture;
Dbg_Shift_5 <= Dbg_Shift;
Dbg_Update_5 <= Dbg_Update;
Dbg_Rst_5 <= Dbg_Rst_I(5);
Dbg_TDO_I(5) <= Dbg_TDO_5;
Dbg_Clk_6 <= Dbg_Clk;
Dbg_TDI_6 <= Dbg_TDI;
Dbg_Reg_En_6 <= Dbg_Reg_En_I(6);
Dbg_Capture_6 <= Dbg_Capture;
Dbg_Shift_6 <= Dbg_Shift;
Dbg_Update_6 <= Dbg_Update;
Dbg_Rst_6 <= Dbg_Rst_I(6);
Dbg_TDO_I(6) <= Dbg_TDO_6;
Dbg_Clk_7 <= Dbg_Clk;
Dbg_TDI_7 <= Dbg_TDI;
Dbg_Reg_En_7 <= Dbg_Reg_En_I(7);
Dbg_Capture_7 <= Dbg_Capture;
Dbg_Shift_7 <= Dbg_Shift;
Dbg_Update_7 <= Dbg_Update;
Dbg_Rst_7 <= Dbg_Rst_I(7);
Dbg_TDO_I(7) <= Dbg_TDO_7;
Dbg_Clk_8 <= Dbg_Clk;
Dbg_TDI_8 <= Dbg_TDI;
Dbg_Reg_En_8 <= Dbg_Reg_En_I(8);
Dbg_Capture_8 <= Dbg_Capture;
Dbg_Shift_8 <= Dbg_Shift;
Dbg_Update_8 <= Dbg_Update;
Dbg_Rst_8 <= Dbg_Rst_I(8);
Dbg_TDO_I(8) <= Dbg_TDO_8;
Dbg_Clk_9 <= Dbg_Clk;
Dbg_TDI_9 <= Dbg_TDI;
Dbg_Reg_En_9 <= Dbg_Reg_En_I(9);
Dbg_Capture_9 <= Dbg_Capture;
Dbg_Shift_9 <= Dbg_Shift;
Dbg_Update_9 <= Dbg_Update;
Dbg_Rst_9 <= Dbg_Rst_I(9);
Dbg_TDO_I(9) <= Dbg_TDO_9;
Dbg_Clk_10 <= Dbg_Clk;
Dbg_TDI_10 <= Dbg_TDI;
Dbg_Reg_En_10 <= Dbg_Reg_En_I(10);
Dbg_Capture_10 <= Dbg_Capture;
Dbg_Shift_10 <= Dbg_Shift;
Dbg_Update_10 <= Dbg_Update;
Dbg_Rst_10 <= Dbg_Rst_I(10);
Dbg_TDO_I(10) <= Dbg_TDO_10;
Dbg_Clk_11 <= Dbg_Clk;
Dbg_TDI_11 <= Dbg_TDI;
Dbg_Reg_En_11 <= Dbg_Reg_En_I(11);
Dbg_Capture_11 <= Dbg_Capture;
Dbg_Shift_11 <= Dbg_Shift;
Dbg_Update_11 <= Dbg_Update;
Dbg_Rst_11 <= Dbg_Rst_I(11);
Dbg_TDO_I(11) <= Dbg_TDO_11;
Dbg_Clk_12 <= Dbg_Clk;
Dbg_TDI_12 <= Dbg_TDI;
Dbg_Reg_En_12 <= Dbg_Reg_En_I(12);
Dbg_Capture_12 <= Dbg_Capture;
Dbg_Shift_12 <= Dbg_Shift;
Dbg_Update_12 <= Dbg_Update;
Dbg_Rst_12 <= Dbg_Rst_I(12);
Dbg_TDO_I(12) <= Dbg_TDO_12;
Dbg_Clk_13 <= Dbg_Clk;
Dbg_TDI_13 <= Dbg_TDI;
Dbg_Reg_En_13 <= Dbg_Reg_En_I(13);
Dbg_Capture_13 <= Dbg_Capture;
Dbg_Shift_13 <= Dbg_Shift;
Dbg_Update_13 <= Dbg_Update;
Dbg_Rst_13 <= Dbg_Rst_I(13);
Dbg_TDO_I(13) <= Dbg_TDO_13;
Dbg_Clk_14 <= Dbg_Clk;
Dbg_TDI_14 <= Dbg_TDI;
Dbg_Reg_En_14 <= Dbg_Reg_En_I(14);
Dbg_Capture_14 <= Dbg_Capture;
Dbg_Shift_14 <= Dbg_Shift;
Dbg_Update_14 <= Dbg_Update;
Dbg_Rst_14 <= Dbg_Rst_I(14);
Dbg_TDO_I(14) <= Dbg_TDO_14;
Dbg_Clk_15 <= Dbg_Clk;
Dbg_TDI_15 <= Dbg_TDI;
Dbg_Reg_En_15 <= Dbg_Reg_En_I(15);
Dbg_Capture_15 <= Dbg_Capture;
Dbg_Shift_15 <= Dbg_Shift;
Dbg_Update_15 <= Dbg_Update;
Dbg_Rst_15 <= Dbg_Rst_I(15);
Dbg_TDO_I(15) <= Dbg_TDO_15;
Dbg_Clk_16 <= Dbg_Clk;
Dbg_TDI_16 <= Dbg_TDI;
Dbg_Reg_En_16 <= Dbg_Reg_En_I(16);
Dbg_Capture_16 <= Dbg_Capture;
Dbg_Shift_16 <= Dbg_Shift;
Dbg_Update_16 <= Dbg_Update;
Dbg_Rst_16 <= Dbg_Rst_I(16);
Dbg_TDO_I(16) <= Dbg_TDO_16;
Dbg_Clk_17 <= Dbg_Clk;
Dbg_TDI_17 <= Dbg_TDI;
Dbg_Reg_En_17 <= Dbg_Reg_En_I(17);
Dbg_Capture_17 <= Dbg_Capture;
Dbg_Shift_17 <= Dbg_Shift;
Dbg_Update_17 <= Dbg_Update;
Dbg_Rst_17 <= Dbg_Rst_I(17);
Dbg_TDO_I(17) <= Dbg_TDO_17;
Dbg_Clk_18 <= Dbg_Clk;
Dbg_TDI_18 <= Dbg_TDI;
Dbg_Reg_En_18 <= Dbg_Reg_En_I(18);
Dbg_Capture_18 <= Dbg_Capture;
Dbg_Shift_18 <= Dbg_Shift;
Dbg_Update_18 <= Dbg_Update;
Dbg_Rst_18 <= Dbg_Rst_I(18);
Dbg_TDO_I(18) <= Dbg_TDO_18;
Dbg_Clk_19 <= Dbg_Clk;
Dbg_TDI_19 <= Dbg_TDI;
Dbg_Reg_En_19 <= Dbg_Reg_En_I(19);
Dbg_Capture_19 <= Dbg_Capture;
Dbg_Shift_19 <= Dbg_Shift;
Dbg_Update_19 <= Dbg_Update;
Dbg_Rst_19 <= Dbg_Rst_I(19);
Dbg_TDO_I(19) <= Dbg_TDO_19;
Dbg_Clk_20 <= Dbg_Clk;
Dbg_TDI_20 <= Dbg_TDI;
Dbg_Reg_En_20 <= Dbg_Reg_En_I(20);
Dbg_Capture_20 <= Dbg_Capture;
Dbg_Shift_20 <= Dbg_Shift;
Dbg_Update_20 <= Dbg_Update;
Dbg_Rst_20 <= Dbg_Rst_I(20);
Dbg_TDO_I(20) <= Dbg_TDO_20;
Dbg_Clk_21 <= Dbg_Clk;
Dbg_TDI_21 <= Dbg_TDI;
Dbg_Reg_En_21 <= Dbg_Reg_En_I(21);
Dbg_Capture_21 <= Dbg_Capture;
Dbg_Shift_21 <= Dbg_Shift;
Dbg_Update_21 <= Dbg_Update;
Dbg_Rst_21 <= Dbg_Rst_I(21);
Dbg_TDO_I(21) <= Dbg_TDO_21;
Dbg_Clk_22 <= Dbg_Clk;
Dbg_TDI_22 <= Dbg_TDI;
Dbg_Reg_En_22 <= Dbg_Reg_En_I(22);
Dbg_Capture_22 <= Dbg_Capture;
Dbg_Shift_22 <= Dbg_Shift;
Dbg_Update_22 <= Dbg_Update;
Dbg_Rst_22 <= Dbg_Rst_I(22);
Dbg_TDO_I(22) <= Dbg_TDO_22;
Dbg_Clk_23 <= Dbg_Clk;
Dbg_TDI_23 <= Dbg_TDI;
Dbg_Reg_En_23 <= Dbg_Reg_En_I(23);
Dbg_Capture_23 <= Dbg_Capture;
Dbg_Shift_23 <= Dbg_Shift;
Dbg_Update_23 <= Dbg_Update;
Dbg_Rst_23 <= Dbg_Rst_I(23);
Dbg_TDO_I(23) <= Dbg_TDO_23;
Dbg_Clk_24 <= Dbg_Clk;
Dbg_TDI_24 <= Dbg_TDI;
Dbg_Reg_En_24 <= Dbg_Reg_En_I(24);
Dbg_Capture_24 <= Dbg_Capture;
Dbg_Shift_24 <= Dbg_Shift;
Dbg_Update_24 <= Dbg_Update;
Dbg_Rst_24 <= Dbg_Rst_I(24);
Dbg_TDO_I(24) <= Dbg_TDO_24;
Dbg_Clk_25 <= Dbg_Clk;
Dbg_TDI_25 <= Dbg_TDI;
Dbg_Reg_En_25 <= Dbg_Reg_En_I(25);
Dbg_Capture_25 <= Dbg_Capture;
Dbg_Shift_25 <= Dbg_Shift;
Dbg_Update_25 <= Dbg_Update;
Dbg_Rst_25 <= Dbg_Rst_I(25);
Dbg_TDO_I(25) <= Dbg_TDO_25;
Dbg_Clk_26 <= Dbg_Clk;
Dbg_TDI_26 <= Dbg_TDI;
Dbg_Reg_En_26 <= Dbg_Reg_En_I(26);
Dbg_Capture_26 <= Dbg_Capture;
Dbg_Shift_26 <= Dbg_Shift;
Dbg_Update_26 <= Dbg_Update;
Dbg_Rst_26 <= Dbg_Rst_I(26);
Dbg_TDO_I(26) <= Dbg_TDO_26;
Dbg_Clk_27 <= Dbg_Clk;
Dbg_TDI_27 <= Dbg_TDI;
Dbg_Reg_En_27 <= Dbg_Reg_En_I(27);
Dbg_Capture_27 <= Dbg_Capture;
Dbg_Shift_27 <= Dbg_Shift;
Dbg_Update_27 <= Dbg_Update;
Dbg_Rst_27 <= Dbg_Rst_I(27);
Dbg_TDO_I(27) <= Dbg_TDO_27;
Dbg_Clk_28 <= Dbg_Clk;
Dbg_TDI_28 <= Dbg_TDI;
Dbg_Reg_En_28 <= Dbg_Reg_En_I(28);
Dbg_Capture_28 <= Dbg_Capture;
Dbg_Shift_28 <= Dbg_Shift;
Dbg_Update_28 <= Dbg_Update;
Dbg_Rst_28 <= Dbg_Rst_I(28);
Dbg_TDO_I(28) <= Dbg_TDO_28;
Dbg_Clk_29 <= Dbg_Clk;
Dbg_TDI_29 <= Dbg_TDI;
Dbg_Reg_En_29 <= Dbg_Reg_En_I(29);
Dbg_Capture_29 <= Dbg_Capture;
Dbg_Shift_29 <= Dbg_Shift;
Dbg_Update_29 <= Dbg_Update;
Dbg_Rst_29 <= Dbg_Rst_I(29);
Dbg_TDO_I(29) <= Dbg_TDO_29;
Dbg_Clk_30 <= Dbg_Clk;
Dbg_TDI_30 <= Dbg_TDI;
Dbg_Reg_En_30 <= Dbg_Reg_En_I(30);
Dbg_Capture_30 <= Dbg_Capture;
Dbg_Shift_30 <= Dbg_Shift;
Dbg_Update_30 <= Dbg_Update;
Dbg_Rst_30 <= Dbg_Rst_I(30);
Dbg_TDO_I(30) <= Dbg_TDO_30;
Dbg_Clk_31 <= Dbg_Clk;
Dbg_TDI_31 <= Dbg_TDI;
Dbg_Reg_En_31 <= Dbg_Reg_En_I(31);
Dbg_Capture_31 <= Dbg_Capture;
Dbg_Shift_31 <= Dbg_Shift;
Dbg_Update_31 <= Dbg_Update;
Dbg_Rst_31 <= Dbg_Rst_I(31);
Dbg_TDO_I(31) <= Dbg_TDO_31;
end architecture IMP;
| apache-2.0 | 591bdce46c5d8beba6444f66689a5d3f | 0.516763 | 3.098537 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/dcache_gti.vhd | 1 | 208,572 | `protect begin_protected
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| apache-2.0 | 95da0710f07d5aea7879df8234f0d63c | 0.954337 | 1.809641 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/pf_occ_counter_top.vhd | 15 | 12,619 | -------------------------------------------------------------------------------
-- $Id: pf_occ_counter_top.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_occ_counter_top - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_occ_counter_top.vhd
--
-- Description: Implements parameterized up/down counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_occ_counter_top.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- DET 2001-08-30 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--Use IEEE.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.pf_occ_counter;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_occ_counter_top is
generic (
C_COUNT_WIDTH : integer := 10
);
port (
Clk : in std_logic;
Rst : in std_logic;
Load_Enable : in std_logic;
Load_value : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Down : in std_logic;
Count_Up : in std_logic;
By_2 : In std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1);
almost_full : Out std_logic;
full : Out std_logic;
almost_empty : Out std_logic;
empty : Out std_logic
);
end entity pf_occ_counter_top;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_occ_counter_top is
Signal sig_cnt_enable : std_logic;
Signal sig_cnt_up_n_dwn : std_logic;
Signal sig_carry_out : std_logic;
Signal sig_count_out : std_logic_vector(0 to C_COUNT_WIDTH-1);
Signal upper_cleared : std_logic;
Signal lower_set : std_logic;
Signal lower_cleared : std_logic;
Signal empty_state : std_logic_vector(0 to 2);
Signal full_state : std_logic_vector(0 to 3);
Signal sig_full : std_logic;
Signal sig_almost_full : std_logic;
Signal sig_going_full : std_logic;
Signal sig_empty : std_logic;
Signal sig_almost_empty : std_logic;
begin -- VHDL_RTL
full <= sig_full;
almost_full <= sig_almost_full;
empty <= sig_empty;
almost_empty <= sig_almost_empty;
-- Misc signal assignments
Count_Out <= sig_count_out;
sig_cnt_enable <= (Count_Up and not(sig_full))
xor (Count_Down and not(sig_empty));
sig_cnt_up_n_dwn <= not(Count_Up);
I_UP_DWN_COUNTER : entity proc_common_v4_0.pf_occ_counter
generic map (
C_COUNT_WIDTH
)
port map(
Clk => Clk,
Rst => Rst,
Carry_Out => sig_carry_out,
Load_In => Load_value,
Count_Enable => sig_cnt_enable,
Count_Load => Load_Enable,
Count_Down => sig_cnt_up_n_dwn,
Cnt_by_2 => By_2,
Count_Out => sig_count_out
);
TEST_UPPER_BITS : process (sig_count_out)
Variable all_cleared : boolean;
Variable loop_count : integer;
Begin
--loop_count := 0;
all_cleared := True;
for loop_count in 0 to C_COUNT_WIDTH-2 loop
If (sig_count_out(loop_count) = '1') Then
all_cleared := False;
else
null;
End if;
End loop;
-- -- Search through the upper counter bits starting with the MSB
-- while (loop_count < C_COUNT_WIDTH-2) loop
--
-- If (sig_count_out(loop_count) = '1') Then
-- all_cleared := False;
-- else
-- null;
-- End if;
--
-- loop_count := loop_count + 1;
--
-- End loop;
-- now assign the outputs
If (all_cleared) then
upper_cleared <= '1';
else
upper_cleared <= '0';
End if;
End process TEST_UPPER_BITS;
empty_state <= upper_cleared & sig_count_out(C_COUNT_WIDTH-2) &
sig_count_out(C_COUNT_WIDTH-1);
STATIC_EMPTY_DETECT : process (empty_state)
Begin
Case empty_state Is
When "100" =>
sig_empty <= '1';
sig_almost_empty <= '0';
When "101" =>
sig_empty <= '0';
sig_almost_empty <= '1';
When "110" =>
sig_empty <= '0';
sig_almost_empty <= '0';
When others =>
sig_empty <= '0';
sig_almost_empty <= '0';
End case;
End process STATIC_EMPTY_DETECT;
TEST_LOWER_BITS : process (sig_count_out)
Variable all_cleared : boolean;
Variable all_set : boolean;
Variable loop_count : integer;
Begin
--loop_count := 1;
all_set := True;
all_cleared := True;
for loop_count in 1 to C_COUNT_WIDTH-1 loop
If (sig_count_out(loop_count) = '0') Then
all_set := False;
else
all_cleared := False;
End if;
End loop;
-- -- Search through the lower counter bits starting with the MSB+1
-- while (loop_count < C_COUNT_WIDTH-1) loop
--
-- If (sig_count_out(loop_count) = '0') Then
-- all_set := False;
-- else
-- all_cleared := False;
-- End if;
--
-- loop_count := loop_count + 1;
--
-- End loop;
-- now assign the outputs
If (all_cleared) then
lower_cleared <= '1';
lower_set <= '0';
elsif (all_set) Then
lower_cleared <= '0';
lower_set <= '1';
else
lower_cleared <= '0';
lower_set <= '0';
End if;
End process TEST_LOWER_BITS;
full_state <= sig_count_out(0)
& lower_set
& lower_cleared
& sig_count_out(C_COUNT_WIDTH-1);
STATIC_FULL_DETECT : process (full_state, sig_count_out)
Begin
sig_full <= sig_count_out(0); -- MSB set implies full
Case full_state Is
When "0100" =>
sig_almost_full <= '0';
sig_going_full <= '1';
When "0101" =>
sig_almost_full <= '1';
sig_going_full <= '0';
When others =>
sig_almost_full <= '0';
sig_going_full <= '0';
End case;
End process STATIC_FULL_DETECT;
end architecture implementation;
| apache-2.0 | c6b3cfb0eb0a5bf22179de5aec3b4558 | 0.432047 | 4.570445 | false | false | false | false |
jdryg/tis100cpu | mux2_tb.vhd | 1 | 1,630 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY mux2_tb IS
END mux2_tb;
ARCHITECTURE behavior OF mux2_tb IS
constant MUX_SIZE: integer := 16;
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT mux2
GENERIC (WIDTH: integer := MUX_SIZE);
PORT(
I_A : IN std_logic_vector(WIDTH-1 downto 0);
I_B : IN std_logic_vector(WIDTH-1 downto 0);
I_Sel : IN std_logic;
O_Y : OUT std_logic_vector(WIDTH-1 downto 0)
);
END COMPONENT;
--Inputs
signal I_A : std_logic_vector(MUX_SIZE-1 downto 0) := (others => '0');
signal I_B : std_logic_vector(MUX_SIZE-1 downto 0) := (others => '0');
signal I_Sel : std_logic := '0';
--Outputs
signal O_Y : std_logic_vector(MUX_SIZE-1 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: mux2
GENERIC MAP (WIDTH => MUX_SIZE)
PORT MAP (
I_A => I_A,
I_B => I_B,
I_Sel => I_Sel,
O_Y => O_Y
);
-- Stimulus process
stim_proc: process
begin
I_A <= X"aaaa";
I_B <= X"bbbb";
I_Sel <= '0';
-- If we don't wait for some time at this point, O_Y doesn't have the correct value even though the waves are correct.
wait for 10 ns; -- JD: Why is this needed? This isn't a clocked unit. What am I missing?
assert O_Y = X"aaaa" report "Expected 'AAAA', got wrong value!" severity ERROR;
wait for 100 ns;
I_Sel <= '1';
wait for 10 ns; -- JD: Again, why?
assert O_Y = X"bbbb" report "Expected 'BBBB', got wrong value!" severity ERROR;
wait;
end process;
END;
| mit | 964d69f73e3866edf4e63bf01b5114ce | 0.574847 | 3.26 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/debug_trace.vhd | 1 | 65,160 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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| apache-2.0 | 620c4b450fd20c5cce96932e40b89d7d | 0.952348 | 1.81808 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/microblaze.vhd | 1 | 223,895 | `protect begin_protected
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect end_protected
| apache-2.0 | 6ae99db711ed39a73135191b6e1827e3 | 0.9553 | 1.809969 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/soft_reset.vhd | 15 | 13,928 | -------------------------------------------------------------------------------
-- $Id: soft_reset.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
--soft_reset.vhd v1.01a
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: soft_reset.vhd
-- Version: v1_00_a
-- Description: This VHDL design file is the Soft Reset Service
--
-------------------------------------------------------------------------------
-- Structure:
--
-- soft_reset.vhd
--
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
--
-- History:
-- GAB Aug 2, 2006 v1.00a (initial release)
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
entity soft_reset is
generic (
C_SIPIF_DWIDTH : integer := 32;
-- Width of the write data bus
C_RESET_WIDTH : integer := 4
-- Width of triggered reset in Bus Clocks
);
port (
-- Inputs From the IPIF Bus
Bus2IP_Reset : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_WrCE : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SIPIF_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to (C_SIPIF_DWIDTH/8)-1);
-- Final Device Reset Output
Reset2IP_Reset : out std_logic;
-- Status Reply Outputs to the Bus
Reset2Bus_WrAck : out std_logic;
Reset2Bus_Error : out std_logic;
Reset2Bus_ToutSup : out std_logic
);
end soft_reset ;
-------------------------------------------------------------------------------
architecture implementation of soft_reset is
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Module Software Reset screen value for write data
-- This requires a Hex 'A' to be written to ativate the S/W reset port
constant RESET_MATCH : std_logic_vector(0 to 3) := "1010";
-- Required BE index to be active during Reset activation
constant BE_MATCH : integer := 3;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal sm_reset : std_logic;
signal error_reply : std_logic;
signal reset_wrack : std_logic;
signal reset_error : std_logic;
signal reset_trig : std_logic;
signal wrack : std_logic;
signal wrack_ff_chain : std_logic;
signal flop_q_chain : std_logic_vector(0 to C_RESET_WIDTH);
--signal bus2ip_wrce_d1 : std_logic;
signal data_is_non_reset_match : std_logic;
signal sw_rst_cond : std_logic;
signal sw_rst_cond_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- Misc assignments
Reset2Bus_WrAck <= reset_wrack;
Reset2Bus_Error <= reset_error;
Reset2Bus_ToutSup <= sm_reset; -- Suppress a data phase timeout when
-- a commanded reset is active.
reset_wrack <= (reset_error or wrack);-- and Bus2IP_WrCE;
reset_error <= data_is_non_reset_match and Bus2IP_WrCE;
Reset2IP_Reset <= Bus2IP_Reset or sm_reset;
---------------------------------------------------------------------------------
---- Register WRCE for use in creating a strobe pulse
---------------------------------------------------------------------------------
--REG_WRCE : process(Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
-- if(Bus2IP_Reset = '1')then
-- bus2ip_wrce_d1 <= '0';
-- else
-- bus2ip_wrce_d1 <= Bus2IP_WrCE;
-- end if;
-- end if;
-- end process REG_WRCE;
--
-------------------------------------------------------------------------------
-- Start the S/W reset state machine as a result of an IPIF Bus write to
-- the Reset port and the data on the DBus inputs matching the Reset
-- match value. If the value on the data bus input does not match the
-- designated reset key, an error acknowledge is generated.
-------------------------------------------------------------------------------
--DETECT_SW_RESET : process (Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') then
-- if (Bus2IP_Reset = '1') then
-- error_reply <= '0';
-- reset_trig <= '0';
-- elsif (Bus2IP_WrCE = '1'
-- and Bus2IP_BE(BE_MATCH) = '1'
-- and Bus2IP_Data(28 to 31) = RESET_MATCH) then
-- error_reply <= '0';
-- reset_trig <= Bus2IP_WrCE and not bus2ip_wrce_d1;
-- elsif (Bus2IP_WrCE = '1') then
-- error_reply <= '1';
-- reset_trig <= '0';
-- else
-- error_reply <= '0';
-- reset_trig <= '0';
-- end if;
-- end if;
-- end process DETECT_SW_RESET;
data_is_non_reset_match <=
'0' when (Bus2IP_Data(C_SIPIF_DWIDTH-4 to C_SIPIF_DWIDTH-1) = RESET_MATCH
and Bus2IP_BE(BE_MATCH) = '1')
else '1';
--------------------------------------------------------------------------------
-- SW Reset
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
sw_rst_cond <= Bus2IP_WrCE and not data_is_non_reset_match;
--
RST_PULSE_PROC : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
if (Bus2IP_Reset = '1') Then
sw_rst_cond_d1 <= '0';
reset_trig <= '0';
else
sw_rst_cond_d1 <= sw_rst_cond;
reset_trig <= sw_rst_cond and not sw_rst_cond_d1;
end if;
end if;
End process;
-------------------------------------------------------------------------------
-- RESET_FLOPS:
-- This FORGEN implements the register chain used to create
-- the parameterizable reset pulse width.
-------------------------------------------------------------------------------
RESET_FLOPS : for index in 0 to C_RESET_WIDTH-1 generate
flop_q_chain(0) <= '0';
RST_FLOPS : FDRSE
port map(
Q => flop_q_chain(index+1), -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => flop_q_chain(index), -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => reset_trig -- : in std_logic
);
end generate RESET_FLOPS;
-- Use the last flop output for the commanded reset pulse
sm_reset <= flop_q_chain(C_RESET_WIDTH);
wrack_ff_chain <= flop_q_chain(C_RESET_WIDTH) and
not(flop_q_chain(C_RESET_WIDTH-1));
-- Register the Write Acknowledge for the Reset write
-- This is generated at the end of the reset pulse. This
-- keeps the Slave busy until the commanded reset completes.
FF_WRACK : FDRSE
port map(
Q => wrack, -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => wrack_ff_chain, -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => '0' -- : in std_logic
);
end implementation;
| apache-2.0 | e08a702e7043acac3c06cf2a95f1c107 | 0.401134 | 4.881879 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/axi_master_burst_v2_0/1af76933/hdl/src/vhdl/axi_master_burst_fifo.vhd | 1 | 30,607 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- Filename: axi_master_burst_fifo.vhd
-- Version: initial
-- Description:
-- This file is a wrapper file for the Synchronous FIFO used by the
-- AXI Master burst.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_master_burst_fifo.vhd
-- |
-- |-- proc_common_v4_0.srl_fifo_f
--
-------------------------------------------------------------------------------
-- Author: DET
--
-- History:
-- DET 1/19/2011 Initial
-- ~~~~~~
-- - Adapted from AXI DataMover v2_00_a axi_datamover_fifo.vhd
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI MASTER BURST to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.all;
use proc_common_v4_0.proc_common_pkg.clog2;
use proc_common_v4_0.srl_fifo_f;
-- library axi_master_burst_v2_0;
-- use axi_master_burst_v2_0.axi_master_burst_sfifo_autord;
-- use axi_master_burst_v2_0.axi_master_burst_afifo_autord;
-------------------------------------------------------------------------------
entity axi_master_burst_fifo is
generic (
C_DWIDTH : integer := 32 ;
-- Bit width of the FIFO
C_DEPTH : integer := 4 ;
-- Depth of the fifo in fifo width words
C_IS_ASYNC : Integer range 0 to 1 := 0 ;
-- 0 = Syncronous FIFO
-- 1 = Asynchronous (2 clock) FIFO
C_PRIM_TYPE : Integer range 0 to 2 := 2 ;
-- 0 = Register
-- 1 = Block Memory
-- 2 = SRL
C_FAMILY : String := "virtex7"
-- The target FPGA device familiy
);
port (
-----------------------------------------------------------------------------
-- Write Side Clock and Reset
-----------------------------------------------------------------------------
fifo_wr_clk : In std_logic; -- main clock input
fifo_wr_reset : In std_logic; -- main reset input
-----------------------------------------------------------------------------
-- Write Side Interface (AXI Stream Like)
-----------------------------------------------------------------------------
fifo_wr_tvalid : In std_logic; -- Write Side IF
fifo_wr_tready : Out std_logic; -- Write Side IF
fifo_wr_tdata : In std_logic_vector(C_DWIDTH-1 downto 0); -- Write Side IF
fifo_wr_full : Out std_logic; -- Write Side IF
-----------------------------------------------------------------------------
-- Read Side Clock and reset
-----------------------------------------------------------------------------
fifo_async_rd_reset : In std_logic; -- Read reset => only used if C_IS_ASYNC = 1
fifo_async_rd_clk : In std_logic; -- Read Clock => only used if C_IS_ASYNC = 1
-----------------------------------------------------------------------------
-- Read Side Interface (AXI Stream Like)
-----------------------------------------------------------------------------
fifo_rd_tvalid : Out std_logic; -- Read Side IF
fifo_rd_tready : In std_logic; -- Read Side IF
fifo_rd_tdata : Out std_logic_vector(C_DWIDTH-1 downto 0); -- Read Side IF
fifo_rd_empty : Out std_logic -- Read Side IF
);
end entity axi_master_burst_fifo;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_master_burst_fifo is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- function Declarations
-- Not used by AMB -------------------------------------------------------------------
-- Not used by AMB -- Function
-- Not used by AMB --
-- Not used by AMB -- Function Name: funct_get_prim_type
-- Not used by AMB --
-- Not used by AMB -- Function Description:
-- Not used by AMB -- Sorts out the FIFO Primitive type selection based on fifo
-- Not used by AMB -- depth and original primitive choice.
-- Not used by AMB --
-- Not used by AMB -------------------------------------------------------------------
-- Not used by AMB function funct_get_prim_type (depth : integer;
-- Not used by AMB input_prim_type : integer) return integer is
-- Not used by AMB
-- Not used by AMB Variable temp_prim_type : Integer := 0;
-- Not used by AMB
-- Not used by AMB begin
-- Not used by AMB
-- Not used by AMB If (depth > 64) Then
-- Not used by AMB
-- Not used by AMB temp_prim_type := 1; -- use BRAM
-- Not used by AMB
-- Not used by AMB Elsif (depth <= 64 and
-- Not used by AMB input_prim_type = 0) Then
-- Not used by AMB
-- Not used by AMB temp_prim_type := 0; -- use regiaters
-- Not used by AMB
-- Not used by AMB else
-- Not used by AMB
-- Not used by AMB temp_prim_type := 1; -- use BRAM
-- Not used by AMB
-- Not used by AMB End if;
-- Not used by AMB
-- Not used by AMB
-- Not used by AMB Return (temp_prim_type);
-- Not used by AMB
-- Not used by AMB end function funct_get_prim_type;
-- Signal declarations
Signal sig_init_reg : std_logic := '0';
Signal sig_init_reg2 : std_logic := '0';
Signal sig_init_done : std_logic := '0';
signal sig_inhibit_rdy_n : std_logic := '0';
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_INIT_REG
--
-- Process Description:
-- Registers the reset signal input.
--
-------------------------------------------------------------
IMP_INIT_REG : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_init_reg <= '1';
sig_init_reg2 <= '1';
else
sig_init_reg <= '0';
sig_init_reg2 <= sig_init_reg;
end if;
end if;
end process IMP_INIT_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_INIT_DONE_REG
--
-- Process Description:
-- Create a 1 clock wide init done pulse.
--
-------------------------------------------------------------
IMP_INIT_DONE_REG : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1' or
sig_init_done = '1') then
sig_init_done <= '0';
Elsif (sig_init_reg = '1' and
sig_init_reg2 = '1') Then
sig_init_done <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_INIT_DONE_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RDY_INHIBIT_REG
--
-- Process Description:
-- Implements a ready inhibit flop.
--
-------------------------------------------------------------
IMP_RDY_INHIBIT_REG : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_inhibit_rdy_n <= '0';
Elsif (sig_init_done = '1') Then
sig_inhibit_rdy_n <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_RDY_INHIBIT_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_SINGLE_REG
--
-- If Generate Description:
-- Implements a 1 deep register FIFO (synchronous mode only)
--
--
------------------------------------------------------------
USE_SINGLE_REG : if (C_IS_ASYNC = 0 and
C_DEPTH <= 1) generate
-- Local Constants
-- local signals
signal sig_data_in : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_regfifo_dout_reg : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_regfifo_full_reg : std_logic := '0';
signal sig_regfifo_empty_reg : std_logic := '0';
signal sig_push_regfifo : std_logic := '0';
signal sig_pop_regfifo : std_logic := '0';
begin
-- Internal signals
-- Write signals
fifo_wr_tready <= sig_regfifo_empty_reg;
fifo_wr_full <= sig_regfifo_full_reg ;
sig_push_regfifo <= fifo_wr_tvalid and
sig_regfifo_empty_reg;
sig_data_in <= fifo_wr_tdata ;
-- Read signals
fifo_rd_tdata <= sig_regfifo_dout_reg ;
fifo_rd_tvalid <= sig_regfifo_full_reg ;
fifo_rd_empty <= sig_regfifo_empty_reg;
sig_pop_regfifo <= sig_regfifo_full_reg and
fifo_rd_tready;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_REG_FIFO
--
-- Process Description:
-- This process implements the data and full flag for the
-- register fifo.
--
-------------------------------------------------------------
IMP_REG_FIFO : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1' or
sig_pop_regfifo = '1') then
sig_regfifo_dout_reg <= (others => '0');
sig_regfifo_full_reg <= '0';
elsif (sig_push_regfifo = '1') then
sig_regfifo_dout_reg <= sig_data_in;
sig_regfifo_full_reg <= '1';
else
null; -- don't change state
end if;
end if;
end process IMP_REG_FIFO;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_REG_EMPTY_FLOP
--
-- Process Description:
-- This process implements the empty flag for the
-- register fifo.
--
-------------------------------------------------------------
IMP_REG_EMPTY_FLOP : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_regfifo_empty_reg <= '0'; -- since this is used for the ready (invertd)
-- it can't be asserted during reset
elsif (sig_pop_regfifo = '1' or
sig_init_done = '1') then
sig_regfifo_empty_reg <= '1';
elsif (sig_push_regfifo = '1') then
sig_regfifo_empty_reg <= '0';
else
null; -- don't change state
end if;
end if;
end process IMP_REG_EMPTY_FLOP;
end generate USE_SINGLE_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_SRL_FIFO
--
-- If Generate Description:
-- Generates a fifo implementation usinf SRL based FIFOa
--
--
------------------------------------------------------------
USE_SRL_FIFO : if (C_IS_ASYNC = 0 and
C_DEPTH <= 64 and
C_DEPTH > 1 and
C_PRIM_TYPE = 2 ) generate
-- Local Constants
Constant LOGIC_LOW : std_logic := '0';
Constant NEED_ALMOST_EMPTY : Integer := 0;
Constant NEED_ALMOST_FULL : Integer := 0;
-- local signals
signal sig_wr_full : std_logic := '0';
signal sig_wr_fifo : std_logic := '0';
signal sig_wr_ready : std_logic := '0';
signal sig_rd_fifo : std_logic := '0';
signal sig_rd_empty : std_logic := '0';
signal sig_rd_valid : std_logic := '0';
signal sig_fifo_rd_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
begin
-- Write side signals
fifo_wr_tready <= sig_wr_ready;
fifo_wr_full <= sig_wr_full;
sig_wr_ready <= not(sig_wr_full) and
sig_inhibit_rdy_n;
sig_wr_fifo <= fifo_wr_tvalid and
sig_wr_ready;
sig_fifo_wr_data <= fifo_wr_tdata;
-- Read Side Signals
fifo_rd_tvalid <= sig_rd_valid;
sig_rd_valid <= not(sig_rd_empty);
fifo_rd_tdata <= sig_fifo_rd_data ;
fifo_rd_empty <= not(sig_rd_valid);
sig_rd_fifo <= sig_rd_valid and
fifo_rd_tready;
------------------------------------------------------------
-- Instance: I_SYNC_FIFO
--
-- Description:
-- Implement the synchronous FIFO using SRL FIFO elements
--
------------------------------------------------------------
I_SYNC_FIFO : entity proc_common_v4_0.srl_fifo_f
generic map (
C_DWIDTH => C_DWIDTH ,
C_DEPTH => C_DEPTH ,
C_FAMILY => C_FAMILY
)
port map (
Clk => fifo_wr_clk ,
Reset => fifo_wr_reset ,
FIFO_Write => sig_wr_fifo ,
Data_In => sig_fifo_wr_data ,
FIFO_Read => sig_rd_fifo ,
Data_Out => sig_fifo_rd_data ,
FIFO_Empty => sig_rd_empty ,
FIFO_Full => sig_wr_full ,
Addr => open
);
end generate USE_SRL_FIFO;
-- Not used by AMB ------------------------------------------------------------
-- Not used by AMB -- If Generate
-- Not used by AMB --
-- Not used by AMB -- Label: USE_SYNC_FIFO
-- Not used by AMB --
-- Not used by AMB -- If Generate Description:
-- Not used by AMB -- Instantiates a synchronous FIFO design for use in the
-- Not used by AMB -- synchronous operating mode.
-- Not used by AMB --
-- Not used by AMB ------------------------------------------------------------
-- Not used by AMB USE_SYNC_FIFO : if (C_IS_ASYNC = 0 and
-- Not used by AMB (C_DEPTH > 64 or
-- Not used by AMB (C_DEPTH > 1 and C_PRIM_TYPE < 2 ))) generate
-- Not used by AMB
-- Not used by AMB -- Local Constants
-- Not used by AMB Constant LOGIC_LOW : std_logic := '0';
-- Not used by AMB Constant NEED_ALMOST_EMPTY : Integer := 0;
-- Not used by AMB Constant NEED_ALMOST_FULL : Integer := 0;
-- Not used by AMB Constant DATA_CNT_WIDTH : Integer := clog2(C_DEPTH)+1;
-- Not used by AMB Constant PRIM_TYPE : Integer := funct_get_prim_type(C_DEPTH, C_PRIM_TYPE);
-- Not used by AMB
-- Not used by AMB
-- Not used by AMB -- local signals
-- Not used by AMB signal sig_wr_full : std_logic := '0';
-- Not used by AMB signal sig_wr_fifo : std_logic := '0';
-- Not used by AMB signal sig_wr_ready : std_logic := '0';
-- Not used by AMB signal sig_rd_fifo : std_logic := '0';
-- Not used by AMB signal sig_rd_valid : std_logic := '0';
-- Not used by AMB signal sig_fifo_rd_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
-- Not used by AMB signal sig_fifo_wr_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
-- Not used by AMB
-- Not used by AMB begin
-- Not used by AMB
-- Not used by AMB -- Write side signals
-- Not used by AMB fifo_wr_tready <= sig_wr_ready;
-- Not used by AMB
-- Not used by AMB fifo_wr_full <= sig_wr_full;
-- Not used by AMB
-- Not used by AMB sig_wr_ready <= not(sig_wr_full) and
-- Not used by AMB sig_inhibit_rdy_n;
-- Not used by AMB
-- Not used by AMB sig_wr_fifo <= fifo_wr_tvalid and
-- Not used by AMB sig_wr_ready;
-- Not used by AMB
-- Not used by AMB sig_fifo_wr_data <= fifo_wr_tdata;
-- Not used by AMB
-- Not used by AMB
-- Not used by AMB
-- Not used by AMB
-- Not used by AMB -- Read Side Signals
-- Not used by AMB fifo_rd_tvalid <= sig_rd_valid;
-- Not used by AMB
-- Not used by AMB fifo_rd_tdata <= sig_fifo_rd_data ;
-- Not used by AMB
-- Not used by AMB fifo_rd_empty <= not(sig_rd_valid);
-- Not used by AMB
-- Not used by AMB sig_rd_fifo <= sig_rd_valid and
-- Not used by AMB fifo_rd_tready;
-- Not used by AMB
-- Not used by AMB
-- Not used by AMB
-- Not used by AMB
-- Not used by AMB ------------------------------------------------------------
-- Not used by AMB -- Instance: I_SYNC_FIFO
-- Not used by AMB --
-- Not used by AMB -- Description:
-- Not used by AMB -- Implement the synchronous FIFO
-- Not used by AMB --
-- Not used by AMB ------------------------------------------------------------
-- Not used by AMB I_SYNC_FIFO : entity axi_master_burst_v2_0.axi_master_burst_sfifo_autord
-- Not used by AMB generic map (
-- Not used by AMB
-- Not used by AMB C_DWIDTH => C_DWIDTH ,
-- Not used by AMB C_DEPTH => C_DEPTH ,
-- Not used by AMB C_DATA_CNT_WIDTH => DATA_CNT_WIDTH ,
-- Not used by AMB C_NEED_ALMOST_EMPTY => NEED_ALMOST_EMPTY ,
-- Not used by AMB C_NEED_ALMOST_FULL => NEED_ALMOST_FULL ,
-- Not used by AMB C_USE_BLKMEM => PRIM_TYPE ,
-- Not used by AMB C_FAMILY => C_FAMILY
-- Not used by AMB
-- Not used by AMB )
-- Not used by AMB port map (
-- Not used by AMB
-- Not used by AMB -- Inputs
-- Not used by AMB SFIFO_Sinit => fifo_wr_reset ,
-- Not used by AMB SFIFO_Clk => fifo_wr_clk ,
-- Not used by AMB SFIFO_Wr_en => sig_wr_fifo ,
-- Not used by AMB SFIFO_Din => fifo_wr_tdata ,
-- Not used by AMB SFIFO_Rd_en => sig_rd_fifo ,
-- Not used by AMB SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Not used by AMB
-- Not used by AMB -- Outputs
-- Not used by AMB SFIFO_DValid => sig_rd_valid ,
-- Not used by AMB SFIFO_Dout => sig_fifo_rd_data ,
-- Not used by AMB SFIFO_Full => sig_wr_full ,
-- Not used by AMB SFIFO_Empty => open ,
-- Not used by AMB SFIFO_Almost_full => open ,
-- Not used by AMB SFIFO_Almost_empty => open ,
-- Not used by AMB SFIFO_Rd_count => open ,
-- Not used by AMB SFIFO_Rd_count_minus1 => open ,
-- Not used by AMB SFIFO_Wr_count => open ,
-- Not used by AMB SFIFO_Rd_ack => open
-- Not used by AMB
-- Not used by AMB );
-- Not used by AMB
-- Not used by AMB
-- Not used by AMB
-- Not used by AMB
-- Not used by AMB end generate USE_SYNC_FIFO;
-- Not used by AMB ------------------------------------------------------------
-- Not used by AMB -- If Generate
-- Not used by AMB --
-- Not used by AMB -- Label: USE_ASYNC_FIFO
-- Not used by AMB --
-- Not used by AMB -- If Generate Description:
-- Not used by AMB -- Instantiates an asynchronous FIFO design for use in the
-- Not used by AMB -- asynchronous operating mode.
-- Not used by AMB --
-- Not used by AMB ------------------------------------------------------------
-- Not used by AMB USE_ASYNC_FIFO : if (C_IS_ASYNC = 1) generate
-- Not used by AMB
-- Not used by AMB -- Local Constants
-- Not used by AMB Constant LOGIC_LOW : std_logic := '0';
-- Not used by AMB Constant CNT_WIDTH : Integer := clog2(C_DEPTH);
-- Not used by AMB
-- Not used by AMB
-- Not used by AMB -- local signals
-- Not used by AMB
-- Not used by AMB signal sig_async_wr_full : std_logic := '0';
-- Not used by AMB signal sig_async_wr_fifo : std_logic := '0';
-- Not used by AMB signal sig_async_wr_ready : std_logic := '0';
-- Not used by AMB signal sig_async_rd_fifo : std_logic := '0';
-- Not used by AMB signal sig_async_rd_valid : std_logic := '0';
-- Not used by AMB signal sig_afifo_rd_data : std_logic_vector(C_DWIDTH-1 downto 0);
-- Not used by AMB signal sig_afifo_wr_data : std_logic_vector(C_DWIDTH-1 downto 0);
-- Not used by AMB signal sig_fifo_ainit : std_logic := '0';
-- Not used by AMB Signal sig_init_reg : std_logic := '0';
-- Not used by AMB
-- Not used by AMB
-- Not used by AMB begin
-- Not used by AMB
-- Not used by AMB sig_fifo_ainit <= fifo_async_rd_reset or fifo_wr_reset;
-- Not used by AMB
-- Not used by AMB
-- Not used by AMB
-- Not used by AMB -- Write side signals
-- Not used by AMB fifo_wr_tready <= sig_async_wr_ready;
-- Not used by AMB
-- Not used by AMB fifo_wr_full <= sig_async_wr_full;
-- Not used by AMB
-- Not used by AMB sig_async_wr_ready <= not(sig_async_wr_full) and
-- Not used by AMB sig_inhibit_rdy_n;
-- Not used by AMB
-- Not used by AMB sig_async_wr_fifo <= fifo_wr_tvalid and
-- Not used by AMB sig_async_wr_ready;
-- Not used by AMB
-- Not used by AMB sig_afifo_wr_data <= fifo_wr_tdata;
-- Not used by AMB
-- Not used by AMB
-- Not used by AMB
-- Not used by AMB
-- Not used by AMB -- Read Side Signals
-- Not used by AMB fifo_rd_tvalid <= sig_async_rd_valid;
-- Not used by AMB
-- Not used by AMB fifo_rd_tdata <= sig_afifo_rd_data ;
-- Not used by AMB
-- Not used by AMB fifo_rd_empty <= not(sig_async_rd_valid);
-- Not used by AMB
-- Not used by AMB sig_async_rd_fifo <= sig_async_rd_valid and
-- Not used by AMB fifo_rd_tready;
-- Not used by AMB
-- Not used by AMB
-- Not used by AMB
-- Not used by AMB
-- Not used by AMB
-- Not used by AMB
-- Not used by AMB ------------------------------------------------------------
-- Not used by AMB -- Instance: I_ASYNC_FIFO
-- Not used by AMB --
-- Not used by AMB -- Description:
-- Not used by AMB -- Implement the asynchronous FIFO
-- Not used by AMB --
-- Not used by AMB ------------------------------------------------------------
-- Not used by AMB I_ASYNC_FIFO : entity axi_master_burst_v2_0.axi_master_burst_afifo_autord
-- Not used by AMB generic map (
-- Not used by AMB
-- Not used by AMB C_DWIDTH => C_DWIDTH ,
-- Not used by AMB C_DEPTH => C_DEPTH ,
-- Not used by AMB C_CNT_WIDTH => CNT_WIDTH ,
-- Not used by AMB C_USE_BLKMEM => C_PRIM_TYPE ,
-- Not used by AMB C_FAMILY => C_FAMILY
-- Not used by AMB
-- Not used by AMB )
-- Not used by AMB port map (
-- Not used by AMB
-- Not used by AMB -- Inputs
-- Not used by AMB AFIFO_Ainit => sig_fifo_ainit ,
-- Not used by AMB AFIFO_Wr_clk => fifo_wr_clk ,
-- Not used by AMB AFIFO_Wr_en => sig_async_wr_fifo ,
-- Not used by AMB AFIFO_Din => sig_afifo_wr_data ,
-- Not used by AMB AFIFO_Rd_clk => fifo_async_rd_clk ,
-- Not used by AMB AFIFO_Rd_en => sig_async_rd_fifo ,
-- Not used by AMB AFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Not used by AMB
-- Not used by AMB -- Outputs
-- Not used by AMB AFIFO_DValid => sig_async_rd_valid,
-- Not used by AMB AFIFO_Dout => sig_afifo_rd_data ,
-- Not used by AMB AFIFO_Full => sig_async_wr_full ,
-- Not used by AMB AFIFO_Empty => open ,
-- Not used by AMB AFIFO_Almost_full => open ,
-- Not used by AMB AFIFO_Almost_empty => open ,
-- Not used by AMB AFIFO_Wr_count => open ,
-- Not used by AMB AFIFO_Rd_count => open ,
-- Not used by AMB AFIFO_Corr_Rd_count => open ,
-- Not used by AMB AFIFO_Corr_Rd_count_minus1 => open ,
-- Not used by AMB AFIFO_Rd_ack => open
-- Not used by AMB
-- Not used by AMB );
-- Not used by AMB
-- Not used by AMB
-- Not used by AMB
-- Not used by AMB
-- Not used by AMB end generate USE_ASYNC_FIFO;
-- Not used by AMB
end imp;
| apache-2.0 | aa11e8965da4838d9a543ea45e70b782 | 0.450224 | 4.280101 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/lmb_bram_if_cntlr_v4_0/816dc01c/hdl/vhdl/pselect.vhd | 1 | 9,476 | -------------------------------------------------------------------------------
-- $Id: pselect.vhd,v 1.1.2.2 2010/09/06 09:01:24 rolandp Exp $
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
-------------------------------------------------------------------------------
-- Filename: pselect.vhd
--
-- Description: Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain. For version with AValid at top of
-- carry chain, see pselect_top.vhd.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pselect.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.1.2.2 $
-- Date: $Date: 2010/09/06 09:01:24 $
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library unisim;
use unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect is
component MUXCY is
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MUXCY;
attribute INIT : string;
-----------------------------------------------------------------------------
-- Constant Declarations
-----------------------------------------------------------------------------
constant NUM_LUTS : integer := (C_AB+3)/4;
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
-----------------------------------------------------------------------------
-- Signal Declarations
-----------------------------------------------------------------------------
--signal lut_out : std_logic_vector(0 to NUM_LUTS-1);
signal lut_out : std_logic_vector(0 to NUM_LUTS); -- XST workaround
signal carry_chain : std_logic_vector(0 to NUM_LUTS);
-------------------------------------------------------------------------------
-- Begin architecture section
-------------------------------------------------------------------------------
begin
--------------------------------------------------------------------------------
-- Check that the passed generics allow for correct implementation.
--------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
--------------------------------------------------------------------------------
-- Build the decoder using the fast carry chain.
--------------------------------------------------------------------------------
carry_chain(0) <= AValid;
XST_WA: if NUM_LUTS > 0 generate -- workaround for XST; remove this
-- enclosing generate when fixed
GEN_DECODE: for i in 0 to NUM_LUTS-1 generate
signal lut_in : std_logic_vector(3 downto 0);
signal invert : std_logic_vector(3 downto 0);
begin
GEN_LUT_INPUTS: for j in 0 to 3 generate
-- Generate to assign address bits to LUT4 inputs
GEN_INPUT: if i < NUM_LUTS-1 or j <= ((C_AB-1) mod 4) generate
lut_in(j) <= A(i*4+j);
invert(j) <= not BAR(i*4+j);
end generate;
-- Generate to assign one to remaining LUT4, pad, inputs
GEN_ZEROS: if not(i < NUM_LUTS-1 or j <= ((C_AB-1) mod 4)) generate
lut_in(j) <= '1';
invert(j) <= '0';
end generate;
end generate;
---------------------------------------------------------------------------
-- RTL LUT instantiation
---------------------------------------------------------------------------
lut_out(i) <= (lut_in(0) xor invert(0)) and
(lut_in(1) xor invert(1)) and
(lut_in(2) xor invert(2)) and
(lut_in(3) xor invert(3));
MUXCY_I: MUXCY
port map (
O => carry_chain(i+1), --[out]
CI => carry_chain(i), --[in]
DI => '0', --[in]
S => lut_out(i) --[in]
);
end generate GEN_DECODE;
end generate XST_WA;
CS <= carry_chain(NUM_LUTS); -- assign end of carry chain to output;
-- if NUM_LUTS=0, then
-- CS <= carry_chain(0) <= AValid
end imp;
| apache-2.0 | 92b905d02532fce8f4203a2dfd0846a2 | 0.46011 | 4.904762 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/decode_gti.vhd | 1 | 353,125 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 259664)
`protect data_block
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`protect end_protected
| apache-2.0 | 32709e6ccdecbaa111479a9a3b051a10 | 0.955679 | 1.810099 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/ramfifo/reset_blk_ramfifo.vhd | 5 | 38,790 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 26976)
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`protect end_protected
| apache-2.0 | b97cd254da764da48cad91095d944d61 | 0.947718 | 1.827045 | false | false | false | false |
sandrosalvato94/System-Design-Project | src/polito/sdp2017/Tests/Tmp/TopLevelEntity.vhd | 1 | 5,787 | library ieee;
use ieee.std_logic_1164.all;
use work.CONSTANTS.all;
entity TOP_ENTITY is
port(
clock : in std_logic;
reset : in std_logic;
data : inout std_logic_vector (DATA_WIDTH-1 downto 0);
address : in std_logic_vector(ADD_WIDTH-1 downto 0);
W_enable : in std_logic;
R_enable : in std_logic;
generic_enable : in std_logic;
interrupt : out std_logic
);
end TOP_ENTITY;
architecture STRUCTURAL of TOP_ENTITY is
component DATA_BUFFER is
port(
rst : in std_logic;
row_0 : out std_logic_vector (DATA_WIDTH-1 downto 0); -- First line of the buffer. Must be read constantly by the ip manager
--PORT_0
data_cpu : inout std_logic_vector (DATA_WIDTH-1 downto 0);
address_cpu : in std_logic_vector(ADD_WIDTH-1 downto 0);
WE_CPU : in std_logic;
RE_CPU : in std_logic;
GE_CPU : in std_logic;
--PORT_1
data_in_ip : in std_logic_vector (DATA_WIDTH-1 downto 0);
data_out_ip : out std_logic_vector (DATA_WIDTH-1 downto 0);
address_ip : in std_logic_vector(ADD_WIDTH-1 downto 0);
WE_IP : in std_logic;
RE_IP : in std_logic;
GE_IP : in std_logic
);
end component DATA_BUFFER;
component ip_manager is
port (
clk : in std_logic;
rst : in std_logic;
data_in : out std_logic_vector(data_width-1 downto 0);
data_out : in std_logic_vector(data_width-1 downto 0);
add : out std_logic_vector(add_width-1 downto 0);
w_enable : out std_logic;
r_enable : out std_logic;
generic_en : out std_logic;
interrupt : out std_logic;
row_0 : in std_logic_vector(data_width-1 downto 0);
data_in_ips : in data_array;
data_out_ips : out data_array;
add_ips : in add_array;
w_enable_ips : in std_logic_vector(0 to num_ips-1);
r_enable_ips : in std_logic_vector(0 to num_ips-1);
generic_en_ips : in std_logic_vector(0 to num_ips-1);
enable_ips : out std_logic_vector(0 to num_ips-1);
ack_ips : out std_logic_vector(0 to num_ips-1);
interrupt_ips : in std_logic_vector(0 to num_ips-1));
end component ip_manager;
component ip_dummy is
port (
clk : in std_logic;
rst : in std_logic;
data_in : out std_logic_vector(data_width-1 downto 0);
data_out : in std_logic_vector(data_width-1 downto 0);
address : out std_logic_vector(add_width-1 downto 0);
w_enable : out std_logic;
r_enable : out std_logic;
generic_en : out std_logic;
enable : in std_logic;
ack : in std_logic;
interrupt : out std_logic);
end component ip_dummy;
signal row_0 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal data_in_ip : std_logic_vector (DATA_WIDTH-1 downto 0);
signal data_out_ip : std_logic_vector (DATA_WIDTH-1 downto 0);
signal address_ip : std_logic_vector (ADD_WIDTH-1 downto 0);
signal WE_IP : std_logic;
signal RE_IP : std_logic;
signal GE_IP : std_logic;
signal data_in_IPs : data_array;
signal data_out_IPs : data_array;
signal add_IPs : add_array;
signal W_enable_IPs : std_logic_vector(0 to NUM_IPS-1);
signal R_enable_IPs : std_logic_vector(0 to NUM_IPS-1);
signal generic_en_IPs : std_logic_vector(0 to NUM_IPS-1);
signal enable_IPs : std_logic_vector(0 to NUM_IPS-1);
signal ack_IPs : std_logic_vector(0 to NUM_IPS-1);
signal interrupt_IPs : std_logic_vector(0 to NUM_IPS-1);
begin
data_buff: DATA_BUFFER
port map( rst => reset,
row_0 => row_0,
--PORT_0
data_cpu => data,
address_cpu => address,
WE_CPU => W_enable,
RE_CPU => R_enable,
GE_CPU => generic_enable,
--PORT_1
data_in_ip => data_in_ip,
data_out_ip => data_out_ip,
address_ip => address_ip,
WE_IP => WE_IP,
RE_IP => RE_IP,
GE_IP => GE_IP);
ip_man: ip_manager
port map( clk => clock,
rst => reset,
data_in => data_in_ip,
data_out => data_out_ip,
add => address_ip,
W_enable => WE_IP,
R_enable => RE_IP,
generic_en => GE_IP,
interrupt => interrupt,
row_0 => row_0,
data_in_IPs => data_in_IPs,
data_out_IPs => data_out_IPs,
add_IPs => add_IPs,
W_enable_IPs => W_enable_IPs,
R_enable_IPs => R_enable_IPs,
generic_en_IPs => generic_en_IPs,
enable_IPs => enable_IPs,
ack_IPs => ack_IPs,
interrupt_IPs => interrupt_IPs);
mapIP_0: IP_Dummy
PORT MAP(
clk => clock,
rst => reset,
data_in => data_in_IPs(0),
data_out => data_out_IPs(0),
address => add_IPs(0),
W_enable => W_enable_IPs(0),
R_enable => R_enable_IPs(0),
generic_en => generic_en_IPs(0),
enable => enable_IPs(0),
ack => ack_IPs(0),
interrupt => interrupt_IPs(0));
mapIP_15: IP_Dummy
PORT MAP(
clk => clock,
rst => reset,
data_in => data_in_IPs(1),
data_out => data_out_IPs(1),
address => add_IPs(1),
W_enable => W_enable_IPs(1),
R_enable => R_enable_IPs(1),
generic_en => generic_en_IPs(1),
enable => enable_IPs(1),
ack => ack_IPs(1),
interrupt => interrupt_IPs(1));
mapIP_3: IP_Dummy
PORT MAP(
clk => clock,
rst => reset,
data_in => data_in_IPs(2),
data_out => data_out_IPs(2),
address => add_IPs(2),
W_enable => W_enable_IPs(2),
R_enable => R_enable_IPs(2),
generic_en => generic_en_IPs(2),
enable => enable_IPs(2),
ack => ack_IPs(2),
interrupt => interrupt_IPs(2));
mapIP_17: IP_Dummy
PORT MAP(
clk => clock,
rst => reset,
data_in => data_in_IPs(3),
data_out => data_out_IPs(3),
address => add_IPs(3),
W_enable => W_enable_IPs(3),
R_enable => R_enable_IPs(3),
generic_en => generic_en_IPs(3),
enable => enable_IPs(3),
ack => ack_IPs(3),
interrupt => interrupt_IPs(3));
end architecture; | lgpl-3.0 | de052399d81d580624e6ff493f16999a | 0.597546 | 2.495472 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/carry_compare.vhd | 1 | 11,255 | `protect begin_protected
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| apache-2.0 | c1359950ff5601bffa4b0efab530cf0d | 0.9259 | 1.900861 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/down_counter.vhd | 15 | 8,398 | -------------------------------------------------------------------------------
-- $Id: down_counter.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
------------------------------------------------------------------------------
-- PLB Arbiter
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
------------------------------------------------------------------------------
-- Filename: down_counter.vhd
--
-- Description: Parameterizable down counter with synchronous load and
-- reset.
--
-------------------------------------------------------------------------------
-- Structure:
-- Multi-use module
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 04/10/01 -- First version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.STD_LOGIC_ARITH.all;
-- PROC_COMMON_PKG contains the RESET_ACTIVE constant
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_CNT_WIDTH -- counter width
--
-- Definition of Ports:
-- input Din -- data to be loaded into counter
-- input Load -- load control signal
-- input Cnt_en -- count enable signal
-- input Clk
-- input Rst
--
-- output Cnt_out -- counter output
-------------------------------------------------------------------------------
entity down_counter is
generic (
-- Select width of counter
C_CNT_WIDTH : INTEGER := 4
);
port (
Din : in std_logic_vector(0 to C_CNT_WIDTH-1);
Load : in std_logic;
Cnt_en : in std_logic;
Cnt_out : out std_logic_vector(0 to C_CNT_WIDTH - 1 );
Clk : in std_logic;
Rst : in std_logic
);
end down_counter;
architecture simulation of down_counter is
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
-- internal count
signal cnt : unsigned(0 to C_CNT_WIDTH - 1 );
begin
-------------------------------------------------------------------------------
-- COUNTER_PROCESS process
-------------------------------------------------------------------------------
COUNTER_PROCESS:process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = RESET_ACTIVE then
cnt <= (others => '0');
elsif Load = '1' then
cnt <= unsigned(Din);
elsif Cnt_en = '1' then
cnt <= cnt - 1;
else
cnt <= cnt;
end if;
end if;
end process COUNTER_PROCESS;
CNTOUT_PROCESS:process (cnt)
begin
Cnt_out <= conv_std_logic_vector(cnt, C_CNT_WIDTH);
end process CNTOUT_PROCESS;
end simulation;
| apache-2.0 | e8e7ef99f2306b13a423086dc4007381 | 0.397952 | 5.624916 | false | false | false | false |
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| apache-2.0 | 57951e71b2fbc4fe8c8b139531ce91d2 | 0.937702 | 1.87058 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/common_types_pkg.vhd | 15 | 12,094 | -------------------------------------------------------------------------------
-- $Id: common_types_pkg.vhd,v 1.1.4.4 2010/10/28 01:14:32 ostlerf Exp $
-------------------------------------------------------------------------------
-- Common_Types - package and package body
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: common_types_pkg.vhd
-- Version: v1.00a
-- Description: A package with common type definition and help functions
--
--
-------------------------------------------------------------------------------
-- Structure:
-- common_types_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: BLT (from goran's microblaze_types_pkg.vhd)
-- History:
-- BLT 6-29-2001 -- First version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
-- FLO 10/7/2010 v3_0_a
-- ~~~~~~
-- - Changed Get_RLOC_Name function implementation to an equivalent version
-- that addresses CR 574505.
-- ^^^^^^
-- Removed 42 TBD comment, again. (CR 568493)
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package Common_Types is
type RLOC_POS_TYPE is
record
X : natural;
Y : natural;
end record RLOC_POS_TYPE;
type TARGET_FAMILY_TYPE is (VIRTEX, VIRTEX2);
function log2(x : natural) return integer;
function String_To_Int(S : string) return integer;
function Get_RLOC_Name (Target : TARGET_FAMILY_TYPE;
Y : integer;
X : integer) return string;
end package Common_Types;
-------------------------------------------------------------------------------
-- Package Body section
-------------------------------------------------------------------------------
package body Common_Types is
-- log2 function returns the number of bits required to encode x choices
function log2(x : natural) return integer is
variable i : integer := 0;
begin
if x = 0 then return 0;
else
while 2**i < x loop
i := i+1;
end loop;
return i;
end if;
end function log2;
--itoa function converts integer to a text string
--this function is required since 'image doesn't work
--in synplicity
-- valid range for input to the function is -9999 to 9999
function itoa (int : integer) return string is
type table is array (0 to 9) of string (1 to 1);
constant LUT : table :=
("0", "1", "2", "3", "4", "5", "6", "7", "8", "9");
variable str1 : string(1 to 1);
variable str2 : string(1 to 2);
variable str3 : string(1 to 3);
variable str4 : string(1 to 4);
variable str5 : string(1 to 5);
variable abs_int : natural;
variable thousands_place : natural;
variable hundreds_place : natural;
variable tens_place : natural;
variable ones_place : natural;
variable sign : integer;
begin
abs_int := abs(int);
if abs_int > int then sign := -1;
else sign := 1;
end if;
thousands_place := abs_int/1000;
hundreds_place := (abs_int-thousands_place*1000)/100;
tens_place := (abs_int-thousands_place*1000-hundreds_place*100)/10;
ones_place :=
(abs_int-thousands_place*1000-hundreds_place*100-tens_place*10);
if sign>0 then
if thousands_place>0 then
str4 := LUT(thousands_place) & LUT(hundreds_place) & LUT(tens_place) &
LUT(ones_place);
return str4;
elsif hundreds_place>0 then
str3 := LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str3;
elsif tens_place>0 then
str2 := LUT(tens_place) & LUT(ones_place);
return str2;
else
str1 := LUT(ones_place);
return str1;
end if;
else
if thousands_place>0 then
str5 := "-" & LUT(thousands_place) & LUT(hundreds_place) &
LUT(tens_place) & LUT(ones_place);
return str5;
elsif hundreds_place>0 then
str4 := "-" & LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str4;
elsif tens_place>0 then
str3 := "-" & LUT(tens_place) & LUT(ones_place);
return str3;
else
str2 := "-" & LUT(ones_place);
return str2;
end if;
end if;
end function itoa;
function Get_RLOC_Name (Target : TARGET_FAMILY_TYPE;
Y : integer;
X : integer) return string is
variable Col : integer;
variable Row : integer;
variable S : integer;
begin
if Target = VIRTEX then
Row := -Y;
Col := X/2;
S := 1 - (X mod 2);
return 'R' & itoa(Row) &
'C' & itoa(Col) &
".S" & itoa(S);
else -- Target = VIRTEX2
return 'X' & itoa(X) & 'Y' & itoa(Y);
end if;
end function Get_RLOC_Name;
type POS_RECORD is
record
X : natural;
Y : natural;
end record POS_RECORD;
-----------------------------------------------------------------------------
--
-----------------------------------------------------------------------------
type CHAR_TO_INT_TYPE is array (character) of integer;
constant STRHEX_TO_INT_TABLE : CHAR_TO_INT_TYPE :=
('0' => 0,
'1' => 1,
'2' => 2,
'3' => 3,
'4' => 4,
'5' => 5,
'6' => 6,
'7' => 7,
'8' => 8,
'9' => 9,
'A'|'a' => 10,
'B'|'b' => 11,
'C'|'c' => 12,
'D'|'d' => 13,
'E'|'e' => 14,
'F'|'f' => 15,
others => -1);
-----------------------------------------------------------------------------
-- Converts a string of hex character to an integer
-- accept negative numbers
-----------------------------------------------------------------------------
function String_To_Int(S : String) return Integer is
variable Result : integer := 0;
variable Temp : integer := S'Left;
variable Negative : integer := 1;
begin
for I in S'Left to S'Right loop
if (S(I) = '-') then
Temp := 0;
Negative := -1;
else
Temp := STRHEX_TO_INT_TABLE(S(I));
if (Temp = -1) then
assert false
report "Wrong value in String_To_Int conversion " & S(I)
severity error;
end if;
end if;
Result := Result * 16 + Temp;
end loop;
return (Negative * Result);
end function String_To_Int;
-- function Get_RLOC ( Target : TARGET_FAMILY_TYPE;
-- Module : MODULE_TYPE;
-- Index : natural) return string is
-- begin -- function Get_RLOC
-- end function Get_RLOC;
end package body Common_Types;
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| apache-2.0 | fe0dcbdd505279263eab2529262edf93 | 0.947478 | 1.826191 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/axi_intc_v4_1/28e93d3e/hdl/src/vhdl/pulse_synchronizer.vhd | 1 | 6,838 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename : pulse_synchronizer.vhd
-- Version : v3.0
-- Description: The pulse_synchronizer is having the double flop synchronization logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-------------------------------------------------------------------------------
-- Author: NLR
-- History:
-- NLR 3/21/2011 Initial version
-- ^^^^^^^
-- ^^^^^^^
-- SK 10/10/12
--
-- 1. Added cascade mode support in v1.03.a version of the core
-- 2. Updated major version of the core
-- ~~~~~~
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*N"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- counter signals: "*cntr*", "*count*"
-- ports: - Names in Uppercase
-- processes: "*_REG", "*_CMB"
-- component instantiations: "<ENTITY_>MODULE<#|_FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library axi_intc_v4_1;
use axi_intc_v4_1.all;
entity pulse_synchronizer is
port (
CLK_1 : in std_logic;
RESET_1_n : in std_logic; -- active low reset
DATA_IN : in std_logic;
CLK_2 : in std_logic;
RESET_2_n : in std_logic; -- active low reset
SYNC_DATA_OUT : out std_logic
);
end entity;
architecture RTL of pulse_synchronizer is
signal data_in_toggle : std_logic;
signal data_in_toggle_sync : std_logic;
signal data_in_toggle_sync_d1 : std_logic;
--------------------------------------------------------------------------------------
-- Function to convert std_logic to std_logic_vector
--------------------------------------------------------------------------------------
Function scalar_to_vector (scalar_in : std_logic) return std_logic_vector is
variable vec_out : std_logic_vector(0 downto 0) := "0";
begin
vec_out(0) := scalar_in;
return vec_out;
end function scalar_to_vector;
--------------------------------------------------------------------------------------
-- Function to convert std_logic_vector to std_logic
--------------------------------------------------------------------------------------
Function vector_to_scalar (vec_in : std_logic_vector) return std_logic is
variable scalar_out : std_logic := '0';
begin
scalar_out := vec_in(0);
return scalar_out;
end function vector_to_scalar;
begin
TOGGLE_DATA_IN_REG:process(CLK_1)
begin
if(CLK_1'event and CLK_1 = '1') then
if(RESET_1_n = '0') then
data_in_toggle <= '0';
else
data_in_toggle <= DATA_IN xor data_in_toggle;
end if;
end if;
end process TOGGLE_DATA_IN_REG;
DOUBLE_SYNC_I : entity axi_intc_v4_1.double_synchronizer
generic map (
C_DWIDTH => 1
)
port map (
CLK_2 => CLK_2,
RESET_2_n => RESET_2_n,
DATA_IN => scalar_to_vector(data_in_toggle),
vector_to_scalar(SYNC_DATA_OUT) => data_in_toggle_sync
);
SYNC_DATA_REG:process(CLK_2)
begin
if(CLK_2'event and CLK_2 = '1') then
if(RESET_2_n = '0') then
data_in_toggle_sync_d1 <= '0';
else
data_in_toggle_sync_d1 <= data_in_toggle_sync;
end if;
end if;
end process SYNC_DATA_REG;
SYNC_DATA_OUT <= data_in_toggle_sync xor data_in_toggle_sync_d1;
end RTL;
| apache-2.0 | ab9e2b06a60e4d7746b60f7a48a2b6cc | 0.53656 | 4.355414 | false | false | false | false |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-30bits_outputs31bits/5-EWF/metaheurísticas/ewf_femo.vhd | 1 | 3,094 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-17.11:31:09)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY ewf_femo_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2: IN unsigned(0 TO 30);
output1, output2, output3, output4, output5: OUT unsigned(0 TO 31));
END ewf_femo_entity;
ARCHITECTURE ewf_femo_description OF ewf_femo_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register4: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register5: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register6: unsigned(0 TO 31) := "00000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
register2 := input2 + 2;
WHEN "00000010" =>
register3 := register2 + 4;
WHEN "00000011" =>
register4 := register3 + 6;
WHEN "00000100" =>
register4 := register1 + register4;
WHEN "00000101" =>
register5 := register4 * 8;
WHEN "00000110" =>
register5 := register3 + register5;
register6 := register4 * 10;
WHEN "00000111" =>
register3 := register3 + register5;
register4 := register4 + register5;
WHEN "00001000" =>
register6 := register1 + register6;
register3 := register3 * 12;
WHEN "00001001" =>
output1 <= register6 + register4;
register1 := register1 + register6;
WHEN "00001010" =>
register3 := register2 + register3;
register1 := register1 * 15;
WHEN "00001011" =>
register2 := register2 + register3;
WHEN "00001100" =>
register2 := register2 * 17;
WHEN "00001101" =>
register2 := register2 + 19;
register4 := register5 + register3;
WHEN "00001110" =>
output2 <= register3 + register2;
register2 := register4 + 22;
WHEN "00001111" =>
register3 := register2 * 24;
WHEN "00010000" =>
register3 := register3 + 26;
WHEN "00010001" =>
output3 <= register2 + register3;
register1 := register1 + 29;
WHEN "00010010" =>
register2 := register1 + 31;
WHEN "00010011" =>
register2 := register2 * 33;
register3 := register6 + register1;
WHEN "00010100" =>
register3 := register3 + 35;
output4 <= register1 + register2;
WHEN "00010101" =>
register1 := register3 * 38;
WHEN "00010110" =>
register1 := register1 + 40;
WHEN "00010111" =>
output5 <= register3 + register1;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END ewf_femo_description; | gpl-3.0 | 37ceb7bb1f5fe7bf02af4798ef726723 | 0.666128 | 3.341253 | false | false | false | false |
sils1297/HWPrak14 | task_4/project_1.srcs/sources_1/new/Hack.vhd | 1 | 1,330 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- The Hack CPU as described in
-- http://www.tuhh.de/t3resources/ict/dateien/Lehre/Hardware-Praktikum/Hack.pdf
--
-- Note that we only use 10 bits for memory addressing since we only have 1K
-- memory blocks.
entity Hack is
Port(
reset : in std_ulogic;
clock : in std_ulogic
);
end Hack;
architecture Behavioral of Hack is
signal inM : std_ulogic_vector(15 downto 0);
signal instruction : std_ulogic_vector(15 downto 0);
signal outM : std_ulogic_vector(15 downto 0);
signal writeM : std_ulogic;
signal addressM : std_ulogic_vector(9 downto 0);
signal pc : std_ulogic_vector(9 downto 0);
begin
CPU_inst : entity work.CPU(Behavioral)
port map(
inM => inM,
instruction => instruction,
reset => reset,
outM => outM,
writeM => writeM,
addressM => addressM,
pc => pc,
clock => clock
);
DataMemory_inst : entity work.DataMemory(Behavioral)
port map(
outM => outM,
writeM => writeM,
addressM => addressM,
inM => inM,
clock => clock
);
InstructionMemory_inst : entity work.InstructionMemory(Behavioral)
port map(
pc => pc,
instruction => instruction,
clock => clock
);
end Behavioral;
| agpl-3.0 | c2518ea8eaa1cccda02ea3353ba9da1d | 0.630827 | 3.174224 | false | false | false | false |
sils1297/HWPrak14 | task_3/task_3.srcs/sources_1/new/PWM.vhd | 1 | 745 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity LEDPWM is
generic (
WIDTH : integer := 7 -- that makes 256 bit combinations
);
Port (
CLK_66MHZ : in std_ulogic;
LED : out std_ulogic_vector(3 downto 0);
duty_cycle : in unsigned(7 downto 0)
);
end LEDPWM;
architecture Behavioral of LEDPWM is
signal counter : unsigned(7 downto 0) := (others => '0');
signal ledstate : std_ulogic := '0';
begin
ledstate <= '1' when duty_cycle > counter else '0';
LED(0) <= ledstate;
LED(1) <= ledstate;
LED(2) <= ledstate;
LED(3) <= ledstate;
counterProcess : process(CLK_66MHZ)
begin
if(rising_edge(CLK_66MHZ)) then
counter <= counter + 1;
end if;
end process;
end Behavioral;
| agpl-3.0 | 3a49c6768afc77b8d76a7e2bbf1a7a14 | 0.64698 | 3.104167 | false | false | false | false |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/ramfifo/bram_sync_reg.vhd | 5 | 7,904 | `protect begin_protected
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| apache-2.0 | 09a62dda11ec28dbadb361e222513f97 | 0.917763 | 1.93678 | false | false | false | false |
Abeergit/UART | UART_RX.vhd | 1 | 3,595 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uart_rx is
generic ( DBIT : integer := 8; --Anzahl Datenbits
SB_TICK : integer := 16; --Anzahl ticks für Stopbit
PARITY_EN: std_logic := '1' );
port (clk : in std_logic; --clock
reset : in std_logic; --reset
rx : in std_logic; --empfangenes bit
s_tick : in std_logic; --sample tick, für (16x baudrate)
rx_done_tick : out std_logic; --tick welches angibt, dass die Uebertragung abgeschlossen ist
framing_error_tick: out std_logic;
dout : out std_logic_vector (7 downto 0); --die aufgenommenen Bits in paralleler Form
parity_error : out std_logic);
end uart_rx;
architecture main of uart_rx is
type state_type is (idle, start, data, parity, stop);
signal parity_bit, parity_rx : std_logic;
signal state_reg, state_next : state_type; --Status Register
signal s_reg, s_next : unsigned (3 downto 0); --sample register
signal n_reg, n_next : unsigned (3 downto 0); --Anzahl empfangener Datenbits
signal b_reg, b_next : std_logic_vector (7 downto 0); --Datenwort
begin
process(clk,reset)
begin
if (rising_edge(clk) and clk='1') then
if reset = '1' then
state_reg <= idle;
s_reg <= (others=>'0');
n_reg <= (others=>'0');
b_reg <= (others=>'0');
elsif reset = '0' then
state_reg <= state_next;
s_reg <= s_next;
n_reg <= n_next;
b_reg <= b_next;
end if;
end if;
end process;
process(state_reg, s_reg, n_reg, b_reg, s_tick, rx)
begin
state_next <= state_reg;
s_next <= s_reg;
n_next <= n_reg;
b_next <= b_reg;
rx_done_tick <= '0';
framing_error_tick <= '0';
case state_reg is
when idle =>
if (rx='0') then
state_next <= start;
s_next <= (others => '0');
end if;
when start =>
if (s_tick = '1') then
if (s_reg = 7) then
state_next <= data;
s_next <= (others => '0');
n_next <= (others => '0');
else
s_next <= s_reg + 1;
end if;
end if;
when data =>
if (s_tick = '1') then
if (s_reg = 15) then
s_next <= (others => '0');
b_next <= rx & b_reg(7 downto 1);
if n_reg=(DBIT-1) then
if PARITY_EN = '1' then
state_next <= parity;
elsif PARITY_EN = '0' then
state_next <= stop;
end if;
else
n_next <= n_reg + 1;
end if;
else
s_next <= s_reg + 1;
end if;
end if;
when parity =>
parity_bit <= (b_reg(0) xor b_reg(1)) xor (b_reg(2) xor b_reg(3)) xor (b_reg(4) xor b_reg(5)) xor (b_reg(6) xor b_reg(7)); --even parity
if (s_tick = '1') then
if s_reg = 15 then
s_next <= (others => '0');
parity_rx <= rx;
parity_error <= rx xor parity_bit;
state_next <= stop;
else
s_next <= s_reg + 1;
end if;
end if;
when stop =>
if (s_tick = '1') then
if (s_reg = SB_TICK - 1) then
rx_done_tick <= '1';
if (rx = '1') then
state_next <= idle;
else
framing_error_tick <= '1';
if (rx = '1') then
state_next <= idle;
end if;
end if;
else
s_next <= s_reg + 1;
if (rx = '0') then
framing_error_tick <= '1';
end if;
end if;
end if;
end case;
end process;
dout <= b_reg;
end main;
| mit | 68a8e84ca2927222d3d6a67a155c127b | 0.499304 | 2.974338 | false | false | false | false |
rcls/sdr | vhdl/usbio.vhd | 1 | 4,666 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.defs.all;
-- We run off a 50mhz clock, transferring 1 byte every 4 cycles. This gives
-- up to 12.5MB/s transfer rate, to achieve the maximum rate we need to use
-- 'turbo' mode that ignores the FT2232H async strobes.
-- xmit strobes data in [subject to dead time] on clocks that are a multiple
-- of 4.
-- tx_overrun is asserted if xmit does not write a block. It is cleared on the
-- next successful xmit. In turbo mode, we have no idea if the write succeeds.
-- Instead tx_overrun outputs a LFSR which may be used to synchronise streams.
entity usbio is
generic (packet_bytes : integer);
port (usbd_in : in unsigned8;
usbd_out : out unsigned8;
usb_oe_n : out std_logic := '1';
usb_nRXF : in std_logic;
usb_nTXE : in std_logic;
usb_nRD : out std_logic := '1';
usb_nWR : out std_logic := '1';
usb_SIWU : out std_logic := '1';
read_ok : in std_logic := '1';
byte_in : out unsigned8;
byte_in_strobe : out std_logic;
packet : in unsigned(packet_bytes * 8 - 1 downto 0);
xmit : in std_logic; -- toggle to xmit.
last : in std_logic; -- strobe for highest number channel.
xmit_channel : in unsigned2;
xmit_length : in integer range 0 to packet_bytes;
low_latency, turbo : in std_logic;
tx_overrun : out std_logic;
clk : in std_logic);
end usbio;
architecture usbio of usbio is
type state_t is (state_idle, state_write, state_write2, state_read,
state_read2, state_pause);
signal state : state_t := state_idle;
signal xmit_prev : std_logic;
signal xmit_buffer : unsigned(packet_bytes * 8 - 1 downto 0);
signal xmit_buffered : std_logic := '0';
signal xmit_buffer_length : integer range 0 to packet_bytes;
signal xmit_queue : unsigned(packet_bytes * 8 - 1 downto 0);
signal xmit_channel_counter : unsigned2 := "00";
signal to_xmit : integer range 0 to packet_bytes := 0;
-- In turbo mode the overrun flags get replaced by an LFSR generated
-- pattern. Poly is 0x100802041.
signal lfsr : std_logic_vector(31 downto 0) := x"00000001";
begin
usbd_out <= xmit_queue(7 downto 0);
process
variable rx_available : boolean;
variable tx_available : boolean;
begin
wait until rising_edge(clk);
usb_nRD <= '1';
usb_nWR <= '1';
usb_oe_n <= '1';
state <= state_idle;
byte_in_strobe <= '0';
if state /= state_pause then
usb_SIWU <= '1';
end if;
-- If we're in state idle, decide what to do next. Prefer reads over
-- writes. The read handshake ensures that a write will get out
-- anyway.
rx_available := usb_nRXF = '0' and read_ok = '1';
tx_available := (usb_nTXE = '0' or turbo = '1') and to_xmit /= 0;
if state = state_idle then
if rx_available then
state <= state_read;
usb_nRD <= '0';
elsif tx_available then
state <= state_write;
usb_oe_n <= '0';
end if;
end if;
if state = state_write then
usb_oe_n <= '0';
usb_nWR <= '0';
state <= state_write2;
to_xmit <= to_xmit - 1;
end if;
if state = state_write2 then
usb_nWR <= '0';
state <= state_pause;
xmit_queue(packet_bytes * 8 - 9 downto 0)
<= xmit_queue(packet_bytes * 8 - 1 downto 8);
xmit_queue(packet_bytes * 8 - 1 downto packet_bytes * 8 - 8)
<= "XXXXXXXX";
if to_xmit = 0 and xmit_buffered = '0' and low_latency = '1' then
usb_SIWU <= '0';
end if;
end if;
if state = state_read then
usb_nRD <= '0';
state <= state_read2;
end if;
if state = state_read2 then
byte_in <= usbd_in;
byte_in_strobe <= '1';
state <= state_pause;
end if;
if xmit_buffered = '1' and to_xmit = 0 then
to_xmit <= xmit_buffer_length;
xmit_buffered <= '0';
xmit_queue <= xmit_buffer;
end if;
xmit_prev <= xmit;
if xmit /= xmit_prev and xmit_channel = xmit_channel_counter
then
xmit_buffered <= '1';
xmit_buffer <= packet;
xmit_buffer_length <= xmit_length;
lfsr <= lfsr(30 downto 0) & (
lfsr(31) xor lfsr(22) xor lfsr(12) xor lfsr(5));
if turbo = '1' then
tx_overrun <= lfsr(0);
else
tx_overrun <= xmit_buffered and b2s(to_xmit /= 0);
end if;
end if;
if xmit /= xmit_prev then
if last = '1' then
xmit_channel_counter <= "00";
else
xmit_channel_counter <= xmit_channel_counter + 1;
end if;
end if;
end process;
end usbio;
| gpl-3.0 | dbe87c5d3986b6b3164e95f1bf742384 | 0.593013 | 3.410819 | false | false | false | false |
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