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grwlf/vsim | vhdl_ct/pro000020.vhd | 1 | 4,013 | -- Prosoft VHDL tests.
--
-- Copyright (C) 2011 Prosoft.
--
-- Author: Zefirov, Karavaev.
--
-- This is a set of simplest tests for isolated tests of VHDL features.
--
-- Nothing more than standard package should be required.
--
-- Categories: entity, architecture, process, after, if-then-else, enumerations, array, record, case, for-loop, signals-attributes.
use work.std_logic_1164_for_tst.all;
entity ENT00017_Test_Bench is
end ENT00017_Test_Bench;
architecture ARCH00017_Test_Bench of ENT00017_Test_Bench is
type std_array_array is array (0 to 3, 1 to 4) of std_ulogic;
signal I_saa : std_array_array := (others => x"B");
subtype byte is bit_vector(7 downto 0);
subtype byte2 is bit_vector(0 to 7);
signal b1 : byte := x"00";
signal b2 : byte2 := x"00";
type bit_array_array is array (0 to 3, 4 downto 1) of bit;
signal I_baa : bit_array_array := (others => x"A");
type NatArray is array (natural range <>) of natural;
type std_array is array (0 to 7) of std_logic;
signal I_sa : std_array := "10101010";
type enum is (a_v, b_v, c_v, d_v, e_v, f_v);
type enum_array is array (integer range <>) of enum;
type rec is record
f1 : integer;
f2 : boolean;
f3 : bit;
f4 : enum;
f5 : enum_array(0 to 3);
f6 : NatArray(7 downto 0);
f7 : bit_vector(7 downto 0);
end record;
type rec_array is array (integer range <>) of rec;
signal e : enum := a_v;
signal ea : enum_array(0 to 3) := (others => a_v);
signal r : rec := (
f1 => 10
, f2 => true
, f3 => '1'
, f4 => a_v
, f5 => (others => a_v)
, f6 => (0 => 10, 7 => 3, others => 0)
, f7 => x"33"
);
signal ra : rec_array(0 to 3) := (others => (
f1 => 10
, f2 => true
, f3 => '1'
, f4 => a_v
, f5 => (others => a_v)
, f6 => (0 => 10, 7 => 3, others => 0)
, f7 => x"33"
)
);
signal bv : bit_vector(15 downto 0) := x"CCCC";
signal clk : std_logic := '0';
signal clk2 : std_logic := '0';
type BoolVector is array (integer range <>) of boolean;
signal bool : BoolVector(1 to 60);
begin
bool(13) <= bv'Quiet(40 ns);
bool(14) <= ra'Quiet(40 ns);
bool(15) <= r'Quiet(40 ns);
bool(16) <= ea'Quiet(40 ns);
bool(17) <= e'Quiet(40 ns);
bool(18) <= I_sa'Quiet(40 ns);
bool(19) <= I_baa'Quiet(40 ns);
bool(20) <= I_saa'Quiet(40 ns);
bool(21) <= b1'Quiet(40 ns);
bool(22) <= b2'Quiet(40 ns);
bool(23) <= clk'Quiet(40 ns);
bool(24) <= clk2'Quiet(40 ns);
clk <= not clk after 1 us;
clk2 <= not clk2 after 3 us;
process (clk)
begin
if clk'event and clk = '1' then
b1 <= b1(6 downto 0) & not b1(7);
case e is
when a_v => e <= b_v;
when b_v => e <= c_v;
when c_v => e <= d_v;
when d_v => e <= e_v;
when e_v => e <= f_v;
when f_v => e <= a_v;
end case;
ea(0) <= e;
ea_loop: for i in 1 to ea'length-1 loop
ea(i) <= ea(i-1);
end loop ea_loop;
elsif falling_edge(clk) then
bv <= bv(bv'left-1 downto bv'low) & bv(bv'high);
r.f1 <= r.f1 + 1;
r.f2 <= not r.f2;
r.f3 <= not r.f3;
r.f4 <= e;
r.f5 <= ea;
r_f6_loop: for i in r.f6'low to r.f6'high loop
r.f6(i) <= r.f6(i) + 1;
end loop r_f6_loop;
r.f7 <= r.f7(6 downto 0) & r.f7(7);
ra(ra'high) <= r;
ra_loop: for i in ra'high-1 downto 0 loop
ra(i) <= ra(i+1);
end loop;
end if;
end process;
process (clk2)
begin
if rising_edge(clk2) then
I_sa <= I_sa(I_sa'length-1) & I_sa(0 to I_sa'length-2);
elsif clk2'event and clk2 = '0' then
I_saa_loop_1: for i in 0 to 3 loop
I_saa_loop_2: for j in 1 to 4 loop
I_saa(i,j) <= I_sa(i+j);
end loop I_saa_loop_2;
end loop I_saa_loop_1;
I_baa_loop_1: for i in 0 to 3 loop
I_baa_loop_2: for j in 1 to 4 loop
I_baa(i,j) <= bv(i*j);
end loop I_baa_loop_2;
end loop I_baa_loop_1;
end if;
end process;
end ARCH00017_Test_Bench ; | gpl-3.0 | 0e402b2ab7996615d66d7a0a0c9164ed | 0.543733 | 2.463475 | false | false | false | false |
grwlf/vsim | vhdl_ct/pro000011.vhd | 1 | 2,453 | -- Prosoft VHDL tests.
--
-- Copyright (C) 2011 Prosoft.
--
-- Author: Zefirov, Karavaev.
--
-- This is a set of simplest tests for isolated tests of VHDL features.
--
-- Nothing more than standard package should be required.
--
-- Categories: entity, architecture, process, after, if-then-else, procedure, function.
entity ENT00008_Test_Bench is
end ENT00008_Test_Bench;
architecture ARCH00008_Test_Bench of ENT00008_Test_Bench is
procedure Comp_3(In1,R:in real; Step :in integer; W1,W2:out real) is
variable counter: Integer;
variable W2_t, W1_t : real;
begin
W1_t := 1.43 * In1;
W1 := 1.43 * In1;
W2_t := 1.0;
W2 := 1.0;
L1: for counter in 1 to Step loop
W2_t := W2_t * W1_t;
exit L1 when W2_t > R;
end loop L1;
W2 := W2_t;
W1 := W1_t;
assert ( W2_t < R )
report "Out of range"
severity Error;
end procedure Comp_3;
procedure Transcoder_1 (variable Value: inout bit_vector (0 to 7)) is
begin
case Value is
when "00000000" => Value:="01010101";
when "01010101" => Value:="00000000";
when others => Value:="11111111";
end case;
end procedure Transcoder_1;
procedure Proc_3 (X,Y : inout Integer) is
subtype Word_16 is integer range 0 to 65536;
variable Vb1,Vb2,Vb3,Vb4 : Real;
constant Pi : Real :=3.14;
function convToInt16 (r: real) return integer is
variable w16 : Word_16;
begin
if integer(r) > 65536 then
w16 := 65536;
elsif integer(r) < 0 then
w16 := 0;
else
w16 := integer(r);
end if;
return w16;
end;
procedure Compute (variable V1, V2: Real) is
begin
Vb3 := V1 * V2;
end procedure Compute;
variable Vb3_int : integer;
begin
Vb1 := real(X)*Pi;
Vb2 := real(Y)*Pi;
Vb3 := real(X*Y)*Pi;
Vb4 := 0.1;
Compute(Vb3,Vb4);
Vb3_int := convToInt16(Vb3);
X := integer(Vb1) + Vb3_int;
Y := integer(Vb2) - Vb3_int;
end procedure Proc_3;
signal p1o, p2o : real;
signal do_comp : boolean := false;
begin
do_comp <= not do_comp after 1 us;
process(do_comp)
variable v1, v2 : real;
variable vbv : bit_vector(0 to 7) := "01010101";
variable x : integer := 1;
variable y : integer := 2;
begin
if do_comp then
Comp_3(30.0,11.0,1,v1,v2);
p1o <= v1;
p2o <= v2;
Transcoder_1(vbv);
Proc_3(x,y);
end if;
end process;
end ARCH00008_Test_Bench ; | gpl-3.0 | a1040288b328f101ffdd859eb8c7c75f | 0.59519 | 2.829296 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00460.vhd | 1 | 4,807 | -------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00460
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.2.5 (2)
-- 7.2.5 (5)
-- 7.2.5 (6)
-- 7.2.5 (7)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00460
-- ENT00460(ARCH00460)
-- ENT00460_Test_Bench(ARCH00460_Test_Bench)
--
-- REVISION HISTORY:
--
-- 29-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
package PKG00460 is
-- integer definitions
subtype st_integer is integer range -2 ** 15 to 2 ** 20 ;
constant c_integer_1 : integer := 10 ;
constant c_integer_2 : integer := 7 ;
constant c_st_integer_1 : st_integer := 5 ;
constant c_st_integer_2 : st_integer := -4 ;
-- integer
type t_int is range -2 ** 20 to 2 ** 20 ;
subtype st_int is t_int range -2 ** 15 to 2 ** 20 ;
constant c_int_1 : integer := 2 ;
constant c_int_2 : integer := 1 ;
constant c_t_int_1 : t_int := -3 ;
constant c_t_int_2 : t_int := 4 ;
constant c_st_int_1 : st_int := 7 ;
constant c_st_int_2 : st_int := -1 ;
end PKG00460 ;
use WORK.STANDARD_TYPES ;
use WORK.PKG00460.ALL ;
entity ENT00460 is
generic (
i_integer_1 : integer := c_integer_1 ;
i_integer_2 : integer := c_integer_2 ;
i_st_integer_1 : st_integer := c_st_integer_1 ;
i_st_integer_2 : st_integer := c_st_integer_2 ;
i_int_1 : integer := c_int_1 ;
i_int_2 : integer := c_int_2 ;
i_t_int_1 : t_int := c_t_int_1 ;
i_t_int_2 : t_int := c_t_int_2 ;
i_st_int_1 : st_int := c_st_int_1 ;
i_st_int_2 : st_int := c_st_int_2
) ;
constant c2_integer_1 : integer :=
i_int_1 ** i_st_integer_1 ;
constant c2_integer_2 : integer :=
i_int_2 ** i_integer_1 ;
constant c2_t_int_1 : t_int :=
i_t_int_1 ** i_integer_2 ;
constant c2_t_int_2 : t_int :=
i_t_int_2 ** i_integer_1 ;
constant c2_st_int_1 : st_int :=
i_st_int_1 ** i_st_integer_1 ;
constant c2_st_int_2 : st_int :=
i_st_int_2 ** i_integer_1 ;
end ENT00460 ;
architecture ARCH00460 of ENT00460 is
begin
process
variable bool : boolean := true ;
variable cons_correct, gen_correct, dyn_correct : boolean := true ;
--
variable v_int_1, v2_int_1 : integer := i_int_1 ;
variable v_int_2, v2_int_2 : integer := i_int_2 ;
variable v_t_int_1, v2_t_int_1 : t_int := i_t_int_1 ;
variable v_t_int_2, v2_t_int_2 : t_int := i_t_int_2 ;
variable v_st_int_1, v2_st_int_1 : st_int := i_st_int_1 ;
variable v_st_int_2, v2_st_int_2 : st_int := i_st_int_2 ;
variable v_integer_1 : integer := i_integer_1 ;
variable v_integer_2 : integer := i_integer_2 ;
variable v_st_integer_1 : st_integer := i_st_integer_1 ;
variable v_st_integer_2 : st_integer := i_st_integer_2 ;
--
begin
-- static expression
case bool is
when (
c_int_1 ** c_st_integer_1 = 32 and
c_int_2 ** c_integer_1 = 1 and
c_t_int_1 ** c_integer_2 = (-2187) and
c_t_int_2 ** c_integer_1 = 1048576 and
c_st_int_1 ** c_st_integer_1 = 16807 and
c_st_int_2 ** c_integer_1 = 1
) =>
null ;
when others =>
cons_correct := false ;
end case ;
-- generic expression
gen_correct :=
c2_integer_1 = 32 and
c2_integer_2 = 1 and
c2_t_int_1 = (-2187) and
c2_t_int_2 = 1048576 and
c2_st_int_1 = 16807 and
c2_st_int_2 = 1 ;
-- dynamic expression
v2_int_1 :=
v_int_1 ** v_st_integer_1 ;
v2_int_2 :=
v_int_2 ** v_integer_1 ;
v2_t_int_1 :=
v_t_int_1 ** v_integer_2 ;
v2_t_int_2 :=
v_t_int_2 ** v_integer_1 ;
v2_st_int_1 :=
v_st_int_1 ** v_st_integer_1 ;
v2_st_int_2 :=
v_st_int_2 ** v_integer_1 ;
dyn_correct :=
v2_int_1 = 32 and
v2_int_2 = 1 and
v2_t_int_1 = (-2187) and
v2_t_int_2 = 1048576 and
v2_st_int_1 = 16807 and
v2_st_int_2 = 1 ;
STANDARD_TYPES.test_report ( "ARCH00460" ,
"** predefined for integer base and integer exponent" ,
dyn_correct and cons_correct and gen_correct ) ;
wait ;
end process ;
end ARCH00460 ;
entity ENT00460_Test_Bench is
end ENT00460_Test_Bench ;
architecture ARCH00460_Test_Bench of ENT00460_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00460 ( ARCH00460 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00460_Test_Bench ;
| gpl-3.0 | 2ba61a3c6b2732500ae510b50f9ad48b | 0.517787 | 2.819355 | false | true | false | false |
TWW12/lzw | ip_repo/axi_compression_1.0/src/bram_2048_1/synth/bram_2048_1.vhd | 4 | 14,460 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY bram_2048_1 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0)
);
END bram_2048_1;
ARCHITECTURE bram_2048_1_arch OF bram_2048_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bram_2048_1_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF bram_2048_1_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF bram_2048_1_arch : ARCHITECTURE IS "bram_2048_1,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF bram_2048_1_arch: ARCHITECTURE IS "bram_2048_1,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=bram_2048_1.mi" &
"f,C_INIT_FILE=bram_2048_1.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=20,C_READ_WIDTH_A=20,C_WRITE_DEPTH_A=2048,C_READ_DEPTH_A=2048,C_ADDRA_WIDTH=11,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=20,C_READ_WIDTH_B=20,C_WRITE_DE" &
"PTH_B=2048,C_READ_DEPTH_B=2048,C_ADDRB_WIDTH=11,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE" &
"_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 3.9373 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "bram_2048_1.mif",
C_INIT_FILE => "bram_2048_1.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 20,
C_READ_WIDTH_A => 20,
C_WRITE_DEPTH_A => 2048,
C_READ_DEPTH_A => 2048,
C_ADDRA_WIDTH => 11,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 20,
C_READ_WIDTH_B => 20,
C_WRITE_DEPTH_B => 2048,
C_READ_DEPTH_B => 2048,
C_ADDRB_WIDTH => 11,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 3.9373 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 11)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END bram_2048_1_arch;
| unlicense | b5213d10424c411599b00499509b5e7c | 0.62545 | 3.003115 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00615.vhd | 1 | 47,437 | -- NEED RESULT: ARCH00615: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00615: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00615: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00615: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00615: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00615: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00615: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00615: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00615: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00615.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00615.P2: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00615.P3: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00615.P4: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00615.P5: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00615.P6: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00615.P7: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00615.P8: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00615.P9: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00615: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00615: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00615: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00615: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00615: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00615: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00615: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00615: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00615: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00615: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00615: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00615: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00615: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00615: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00615: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00615: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00615: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00615: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00615: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00615: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00615: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00615: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00615: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00615: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00615: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00615: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00615: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: P9: Transport transactions completed entirely passed
-- NEED RESULT: P8: Transport transactions completed entirely passed
-- NEED RESULT: P7: Transport transactions completed entirely passed
-- NEED RESULT: P6: Transport transactions completed entirely passed
-- NEED RESULT: P5: Transport transactions completed entirely passed
-- NEED RESULT: P4: Transport transactions completed entirely passed
-- NEED RESULT: P3: Transport transactions completed entirely passed
-- NEED RESULT: P2: Transport transactions completed entirely passed
-- NEED RESULT: P1: Transport transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00615
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.3 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00615(ARCH00615)
-- ENT00615_Test_Bench(ARCH00615_Test_Bench)
--
-- REVISION HISTORY:
--
-- 24-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00615 is
end ENT00615 ;
--
--
architecture ARCH00615 of ENT00615 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_boolean_vector : chk_sig_type := -1 ;
signal chk_st_severity_level_vector : chk_sig_type := -1 ;
signal chk_st_string : chk_sig_type := -1 ;
signal chk_st_enum1_vector : chk_sig_type := -1 ;
signal chk_st_integer_vector : chk_sig_type := -1 ;
signal chk_st_time_vector : chk_sig_type := -1 ;
signal chk_st_real_vector : chk_sig_type := -1 ;
signal chk_st_rec1_vector : chk_sig_type := -1 ;
signal chk_st_arr2_vector : chk_sig_type := -1 ;
--
subtype chk_time_type is Time ;
signal s_st_boolean_vector_savt : chk_time_type := 0 ns ;
signal s_st_severity_level_vector_savt : chk_time_type := 0 ns ;
signal s_st_string_savt : chk_time_type := 0 ns ;
signal s_st_enum1_vector_savt : chk_time_type := 0 ns ;
signal s_st_integer_vector_savt : chk_time_type := 0 ns ;
signal s_st_time_vector_savt : chk_time_type := 0 ns ;
signal s_st_real_vector_savt : chk_time_type := 0 ns ;
signal s_st_rec1_vector_savt : chk_time_type := 0 ns ;
signal s_st_arr2_vector_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_boolean_vector_cnt : chk_cnt_type := 0 ;
signal s_st_severity_level_vector_cnt : chk_cnt_type := 0 ;
signal s_st_string_cnt : chk_cnt_type := 0 ;
signal s_st_enum1_vector_cnt : chk_cnt_type := 0 ;
signal s_st_integer_vector_cnt : chk_cnt_type := 0 ;
signal s_st_time_vector_cnt : chk_cnt_type := 0 ;
signal s_st_real_vector_cnt : chk_cnt_type := 0 ;
signal s_st_rec1_vector_cnt : chk_cnt_type := 0 ;
signal s_st_arr2_vector_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 3 ;
signal st_boolean_vector_select : select_type := 1 ;
signal st_severity_level_vector_select : select_type := 1 ;
signal st_string_select : select_type := 1 ;
signal st_enum1_vector_select : select_type := 1 ;
signal st_integer_vector_select : select_type := 1 ;
signal st_time_vector_select : select_type := 1 ;
signal st_real_vector_select : select_type := 1 ;
signal st_rec1_vector_select : select_type := 1 ;
signal st_arr2_vector_select : select_type := 1 ;
--
signal s_st_boolean_vector : st_boolean_vector
:= c_st_boolean_vector_1 ;
signal s_st_severity_level_vector : st_severity_level_vector
:= c_st_severity_level_vector_1 ;
signal s_st_string : st_string
:= c_st_string_1 ;
signal s_st_enum1_vector : st_enum1_vector
:= c_st_enum1_vector_1 ;
signal s_st_integer_vector : st_integer_vector
:= c_st_integer_vector_1 ;
signal s_st_time_vector : st_time_vector
:= c_st_time_vector_1 ;
signal s_st_real_vector : st_real_vector
:= c_st_real_vector_1 ;
signal s_st_rec1_vector : st_rec1_vector
:= c_st_rec1_vector_1 ;
signal s_st_arr2_vector : st_arr2_vector
:= c_st_arr2_vector_1 ;
--
procedure P1
(signal s_st_boolean_vector : in st_boolean_vector ;
signal select_sig : out Select_Type ;
signal savtime : out Chk_Time_Type ;
signal chk_sig : out Chk_Sig_Type ;
signal count : out Integer)
is
variable correct : boolean ;
begin
case s_st_boolean_vector_cnt is
when 0
=> null ;
-- s_st_boolean_vector(lowb to highb-1) <= transport
-- c_st_boolean_vector_2(lowb to highb-1) after 10 ns,
-- c_st_boolean_vector_1(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_boolean_vector(lowb to highb-1) =
c_st_boolean_vector_2(lowb to highb-1) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"Concurrent proc call 1",
correct ) ;
--
when 2
=> correct :=
s_st_boolean_vector(lowb to highb-1) =
c_st_boolean_vector_1(lowb to highb-1) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615.P1" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
select_sig <= transport 2 ;
-- s_st_boolean_vector(lowb to highb-1) <= transport
-- c_st_boolean_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_boolean_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_boolean_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_boolean_vector_1(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_boolean_vector(lowb to highb-1) =
c_st_boolean_vector_2(lowb to highb-1) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"Concurrent proc call 2",
correct ) ;
select_sig <= transport 3 ;
-- s_st_boolean_vector(lowb to highb-1) <= transport
-- c_st_boolean_vector_1(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
s_st_boolean_vector(lowb to highb-1) =
c_st_boolean_vector_1(lowb to highb-1) and
(s_st_boolean_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00615" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00615" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
savtime <= transport Std.Standard.Now ;
chk_sig <= transport s_st_boolean_vector_cnt
after (1 us - Std.Standard.Now) ;
count <= transport s_st_boolean_vector_cnt + 1 ;
--
end ;
--
procedure P2
(signal s_st_severity_level_vector : in st_severity_level_vector ;
signal select_sig : out Select_Type ;
signal savtime : out Chk_Time_Type ;
signal chk_sig : out Chk_Sig_Type ;
signal count : out Integer)
is
variable correct : boolean ;
begin
case s_st_severity_level_vector_cnt is
when 0
=> null ;
-- s_st_severity_level_vector(lowb to highb-1) <= transport
-- c_st_severity_level_vector_2(lowb to highb-1) after 10 ns,
-- c_st_severity_level_vector_1(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_severity_level_vector(lowb to highb-1) =
c_st_severity_level_vector_2(lowb to highb-1) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"Concurrent proc call 1",
correct ) ;
--
when 2
=> correct :=
s_st_severity_level_vector(lowb to highb-1) =
c_st_severity_level_vector_1(lowb to highb-1) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615.P2" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
select_sig <= transport 2 ;
-- s_st_severity_level_vector(lowb to highb-1) <= transport
-- c_st_severity_level_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_severity_level_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_severity_level_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_severity_level_vector_1(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_severity_level_vector(lowb to highb-1) =
c_st_severity_level_vector_2(lowb to highb-1) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"Concurrent proc call 2",
correct ) ;
select_sig <= transport 3 ;
-- s_st_severity_level_vector(lowb to highb-1) <= transport
-- c_st_severity_level_vector_1(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
s_st_severity_level_vector(lowb to highb-1) =
c_st_severity_level_vector_1(lowb to highb-1) and
(s_st_severity_level_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00615" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00615" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
savtime <= transport Std.Standard.Now ;
chk_sig <= transport s_st_severity_level_vector_cnt
after (1 us - Std.Standard.Now) ;
count <= transport s_st_severity_level_vector_cnt + 1 ;
--
end ;
--
procedure P3
(signal s_st_string : in st_string ;
signal select_sig : out Select_Type ;
signal savtime : out Chk_Time_Type ;
signal chk_sig : out Chk_Sig_Type ;
signal count : out Integer)
is
variable correct : boolean ;
begin
case s_st_string_cnt is
when 0
=> null ;
-- s_st_string(highb-1 to highb-1) <= transport
-- c_st_string_2(highb-1 to highb-1) after 10 ns,
-- c_st_string_1(highb-1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_string(highb-1 to highb-1) =
c_st_string_2(highb-1 to highb-1) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"Concurrent proc call 1",
correct ) ;
--
when 2
=> correct :=
s_st_string(highb-1 to highb-1) =
c_st_string_1(highb-1 to highb-1) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615.P3" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
select_sig <= transport 2 ;
-- s_st_string(highb-1 to highb-1) <= transport
-- c_st_string_2(highb-1 to highb-1) after 10 ns ,
-- c_st_string_1(highb-1 to highb-1) after 20 ns ,
-- c_st_string_2(highb-1 to highb-1) after 30 ns ,
-- c_st_string_1(highb-1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_string(highb-1 to highb-1) =
c_st_string_2(highb-1 to highb-1) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"Concurrent proc call 2",
correct ) ;
select_sig <= transport 3 ;
-- s_st_string(highb-1 to highb-1) <= transport
-- c_st_string_1(highb-1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
s_st_string(highb-1 to highb-1) =
c_st_string_1(highb-1 to highb-1) and
(s_st_string_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00615" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00615" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
savtime <= transport Std.Standard.Now ;
chk_sig <= transport s_st_string_cnt
after (1 us - Std.Standard.Now) ;
count <= transport s_st_string_cnt + 1 ;
--
end ;
--
procedure P4
(signal s_st_enum1_vector : in st_enum1_vector ;
signal select_sig : out Select_Type ;
signal savtime : out Chk_Time_Type ;
signal chk_sig : out Chk_Sig_Type ;
signal count : out Integer)
is
variable correct : boolean ;
begin
case s_st_enum1_vector_cnt is
when 0
=> null ;
-- s_st_enum1_vector(highb-1 to highb-1) <= transport
-- c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns,
-- c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_enum1_vector(highb-1 to highb-1) =
c_st_enum1_vector_2(highb-1 to highb-1) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"Concurrent proc call 1",
correct ) ;
--
when 2
=> correct :=
s_st_enum1_vector(highb-1 to highb-1) =
c_st_enum1_vector_1(highb-1 to highb-1) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615.P4" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
select_sig <= transport 2 ;
-- s_st_enum1_vector(highb-1 to highb-1) <= transport
-- c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns ,
-- c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns ,
-- c_st_enum1_vector_2(highb-1 to highb-1) after 30 ns ,
-- c_st_enum1_vector_1(highb-1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_enum1_vector(highb-1 to highb-1) =
c_st_enum1_vector_2(highb-1 to highb-1) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"Concurrent proc call 2",
correct ) ;
select_sig <= transport 3 ;
-- s_st_enum1_vector(highb-1 to highb-1) <= transport
-- c_st_enum1_vector_1(highb-1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
s_st_enum1_vector(highb-1 to highb-1) =
c_st_enum1_vector_1(highb-1 to highb-1) and
(s_st_enum1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00615" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00615" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
savtime <= transport Std.Standard.Now ;
chk_sig <= transport s_st_enum1_vector_cnt
after (1 us - Std.Standard.Now) ;
count <= transport s_st_enum1_vector_cnt + 1 ;
--
end ;
--
procedure P5
(signal s_st_integer_vector : in st_integer_vector ;
signal select_sig : out Select_Type ;
signal savtime : out Chk_Time_Type ;
signal chk_sig : out Chk_Sig_Type ;
signal count : out Integer)
is
variable correct : boolean ;
begin
case s_st_integer_vector_cnt is
when 0
=> null ;
-- s_st_integer_vector(lowb to highb-1) <= transport
-- c_st_integer_vector_2(lowb to highb-1) after 10 ns,
-- c_st_integer_vector_1(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_integer_vector(lowb to highb-1) =
c_st_integer_vector_2(lowb to highb-1) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"Concurrent proc call 1",
correct ) ;
--
when 2
=> correct :=
s_st_integer_vector(lowb to highb-1) =
c_st_integer_vector_1(lowb to highb-1) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615.P5" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
select_sig <= transport 2 ;
-- s_st_integer_vector(lowb to highb-1) <= transport
-- c_st_integer_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_integer_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_integer_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_integer_vector_1(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_integer_vector(lowb to highb-1) =
c_st_integer_vector_2(lowb to highb-1) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"Concurrent proc call 2",
correct ) ;
select_sig <= transport 3 ;
-- s_st_integer_vector(lowb to highb-1) <= transport
-- c_st_integer_vector_1(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
s_st_integer_vector(lowb to highb-1) =
c_st_integer_vector_1(lowb to highb-1) and
(s_st_integer_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00615" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00615" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
savtime <= transport Std.Standard.Now ;
chk_sig <= transport s_st_integer_vector_cnt
after (1 us - Std.Standard.Now) ;
count <= transport s_st_integer_vector_cnt + 1 ;
--
end ;
--
procedure P6
(signal s_st_time_vector : in st_time_vector ;
signal select_sig : out Select_Type ;
signal savtime : out Chk_Time_Type ;
signal chk_sig : out Chk_Sig_Type ;
signal count : out Integer)
is
variable correct : boolean ;
begin
case s_st_time_vector_cnt is
when 0
=> null ;
-- s_st_time_vector(lowb to highb-1) <= transport
-- c_st_time_vector_2(lowb to highb-1) after 10 ns,
-- c_st_time_vector_1(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_time_vector(lowb to highb-1) =
c_st_time_vector_2(lowb to highb-1) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"Concurrent proc call 1",
correct ) ;
--
when 2
=> correct :=
s_st_time_vector(lowb to highb-1) =
c_st_time_vector_1(lowb to highb-1) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615.P6" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
select_sig <= transport 2 ;
-- s_st_time_vector(lowb to highb-1) <= transport
-- c_st_time_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_time_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_time_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_time_vector_1(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_time_vector(lowb to highb-1) =
c_st_time_vector_2(lowb to highb-1) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"Concurrent proc call 2",
correct ) ;
select_sig <= transport 3 ;
-- s_st_time_vector(lowb to highb-1) <= transport
-- c_st_time_vector_1(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
s_st_time_vector(lowb to highb-1) =
c_st_time_vector_1(lowb to highb-1) and
(s_st_time_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00615" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00615" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
savtime <= transport Std.Standard.Now ;
chk_sig <= transport s_st_time_vector_cnt
after (1 us - Std.Standard.Now) ;
count <= transport s_st_time_vector_cnt + 1 ;
--
end ;
--
procedure P7
(signal s_st_real_vector : in st_real_vector ;
signal select_sig : out Select_Type ;
signal savtime : out Chk_Time_Type ;
signal chk_sig : out Chk_Sig_Type ;
signal count : out Integer)
is
variable correct : boolean ;
begin
case s_st_real_vector_cnt is
when 0
=> null ;
-- s_st_real_vector(highb-1 to highb-1) <= transport
-- c_st_real_vector_2(highb-1 to highb-1) after 10 ns,
-- c_st_real_vector_1(highb-1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_real_vector(highb-1 to highb-1) =
c_st_real_vector_2(highb-1 to highb-1) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"Concurrent proc call 1",
correct ) ;
--
when 2
=> correct :=
s_st_real_vector(highb-1 to highb-1) =
c_st_real_vector_1(highb-1 to highb-1) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615.P7" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
select_sig <= transport 2 ;
-- s_st_real_vector(highb-1 to highb-1) <= transport
-- c_st_real_vector_2(highb-1 to highb-1) after 10 ns ,
-- c_st_real_vector_1(highb-1 to highb-1) after 20 ns ,
-- c_st_real_vector_2(highb-1 to highb-1) after 30 ns ,
-- c_st_real_vector_1(highb-1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_real_vector(highb-1 to highb-1) =
c_st_real_vector_2(highb-1 to highb-1) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"Concurrent proc call 2",
correct ) ;
select_sig <= transport 3 ;
-- s_st_real_vector(highb-1 to highb-1) <= transport
-- c_st_real_vector_1(highb-1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
s_st_real_vector(highb-1 to highb-1) =
c_st_real_vector_1(highb-1 to highb-1) and
(s_st_real_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00615" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00615" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
savtime <= transport Std.Standard.Now ;
chk_sig <= transport s_st_real_vector_cnt
after (1 us - Std.Standard.Now) ;
count <= transport s_st_real_vector_cnt + 1 ;
--
end ;
--
procedure P8
(signal s_st_rec1_vector : in st_rec1_vector ;
signal select_sig : out Select_Type ;
signal savtime : out Chk_Time_Type ;
signal chk_sig : out Chk_Sig_Type ;
signal count : out Integer)
is
variable correct : boolean ;
begin
case s_st_rec1_vector_cnt is
when 0
=> null ;
-- s_st_rec1_vector(highb-1 to highb-1) <= transport
-- c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns,
-- c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_vector(highb-1 to highb-1) =
c_st_rec1_vector_2(highb-1 to highb-1) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"Concurrent proc call 1",
correct ) ;
--
when 2
=> correct :=
s_st_rec1_vector(highb-1 to highb-1) =
c_st_rec1_vector_1(highb-1 to highb-1) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615.P8" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
select_sig <= transport 2 ;
-- s_st_rec1_vector(highb-1 to highb-1) <= transport
-- c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns ,
-- c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns ,
-- c_st_rec1_vector_2(highb-1 to highb-1) after 30 ns ,
-- c_st_rec1_vector_1(highb-1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_vector(highb-1 to highb-1) =
c_st_rec1_vector_2(highb-1 to highb-1) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"Concurrent proc call 2",
correct ) ;
select_sig <= transport 3 ;
-- s_st_rec1_vector(highb-1 to highb-1) <= transport
-- c_st_rec1_vector_1(highb-1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
s_st_rec1_vector(highb-1 to highb-1) =
c_st_rec1_vector_1(highb-1 to highb-1) and
(s_st_rec1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00615" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00615" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
savtime <= transport Std.Standard.Now ;
chk_sig <= transport s_st_rec1_vector_cnt
after (1 us - Std.Standard.Now) ;
count <= transport s_st_rec1_vector_cnt + 1 ;
--
end ;
--
procedure P9
(signal s_st_arr2_vector : in st_arr2_vector ;
signal select_sig : out Select_Type ;
signal savtime : out Chk_Time_Type ;
signal chk_sig : out Chk_Sig_Type ;
signal count : out Integer)
is
variable correct : boolean ;
begin
case s_st_arr2_vector_cnt is
when 0
=> null ;
-- s_st_arr2_vector(lowb to highb-1) <= transport
-- c_st_arr2_vector_2(lowb to highb-1) after 10 ns,
-- c_st_arr2_vector_1(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2_vector(lowb to highb-1) =
c_st_arr2_vector_2(lowb to highb-1) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"Concurrent proc call 1",
correct ) ;
--
when 2
=> correct :=
s_st_arr2_vector(lowb to highb-1) =
c_st_arr2_vector_1(lowb to highb-1) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615.P9" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
select_sig <= transport 2 ;
-- s_st_arr2_vector(lowb to highb-1) <= transport
-- c_st_arr2_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_arr2_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_arr2_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_arr2_vector_1(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2_vector(lowb to highb-1) =
c_st_arr2_vector_2(lowb to highb-1) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"Concurrent proc call 2",
correct ) ;
select_sig <= transport 3 ;
-- s_st_arr2_vector(lowb to highb-1) <= transport
-- c_st_arr2_vector_1(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
s_st_arr2_vector(lowb to highb-1) =
c_st_arr2_vector_1(lowb to highb-1) and
(s_st_arr2_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00615" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00615" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
savtime <= transport Std.Standard.Now ;
chk_sig <= transport s_st_arr2_vector_cnt
after (1 us - Std.Standard.Now) ;
count <= transport s_st_arr2_vector_cnt + 1 ;
--
end ;
--
begin
CHG1 :
P1(
s_st_boolean_vector ,
st_boolean_vector_select ,
s_st_boolean_vector_savt ,
chk_st_boolean_vector ,
s_st_boolean_vector_cnt ) ;
--
PGEN_CHKP_1 :
process ( chk_st_boolean_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions completed entirely",
chk_st_boolean_vector = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
with st_boolean_vector_select select
s_st_boolean_vector(lowb to highb-1) <= transport
c_st_boolean_vector_2(lowb to highb-1) after 10 ns,
c_st_boolean_vector_1(lowb to highb-1) after 20 ns
when 1,
--
c_st_boolean_vector_2(lowb to highb-1) after 10 ns ,
c_st_boolean_vector_1(lowb to highb-1) after 20 ns ,
c_st_boolean_vector_2(lowb to highb-1) after 30 ns ,
c_st_boolean_vector_1(lowb to highb-1) after 40 ns
when 2,
--
c_st_boolean_vector_1(lowb to highb-1) after 5 ns when 3 ;
--
CHG2 :
P2(
s_st_severity_level_vector ,
st_severity_level_vector_select ,
s_st_severity_level_vector_savt ,
chk_st_severity_level_vector ,
s_st_severity_level_vector_cnt ) ;
--
PGEN_CHKP_2 :
process ( chk_st_severity_level_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions completed entirely",
chk_st_severity_level_vector = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
with st_severity_level_vector_select select
s_st_severity_level_vector(lowb to highb-1) <= transport
c_st_severity_level_vector_2(lowb to highb-1) after 10 ns,
c_st_severity_level_vector_1(lowb to highb-1) after 20 ns
when 1,
--
c_st_severity_level_vector_2(lowb to highb-1) after 10 ns ,
c_st_severity_level_vector_1(lowb to highb-1) after 20 ns ,
c_st_severity_level_vector_2(lowb to highb-1) after 30 ns ,
c_st_severity_level_vector_1(lowb to highb-1) after 40 ns
when 2,
--
c_st_severity_level_vector_1(lowb to highb-1) after 5 ns when 3 ;
--
CHG3 :
P3(
s_st_string ,
st_string_select ,
s_st_string_savt ,
chk_st_string ,
s_st_string_cnt ) ;
--
PGEN_CHKP_3 :
process ( chk_st_string )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions completed entirely",
chk_st_string = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
with st_string_select select
s_st_string(highb-1 to highb-1) <= transport
c_st_string_2(highb-1 to highb-1) after 10 ns,
c_st_string_1(highb-1 to highb-1) after 20 ns
when 1,
--
c_st_string_2(highb-1 to highb-1) after 10 ns ,
c_st_string_1(highb-1 to highb-1) after 20 ns ,
c_st_string_2(highb-1 to highb-1) after 30 ns ,
c_st_string_1(highb-1 to highb-1) after 40 ns
when 2,
--
c_st_string_1(highb-1 to highb-1) after 5 ns when 3 ;
--
CHG4 :
P4(
s_st_enum1_vector ,
st_enum1_vector_select ,
s_st_enum1_vector_savt ,
chk_st_enum1_vector ,
s_st_enum1_vector_cnt ) ;
--
PGEN_CHKP_4 :
process ( chk_st_enum1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Transport transactions completed entirely",
chk_st_enum1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
--
with st_enum1_vector_select select
s_st_enum1_vector(highb-1 to highb-1) <= transport
c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns,
c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns
when 1,
--
c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns ,
c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns ,
c_st_enum1_vector_2(highb-1 to highb-1) after 30 ns ,
c_st_enum1_vector_1(highb-1 to highb-1) after 40 ns
when 2,
--
c_st_enum1_vector_1(highb-1 to highb-1) after 5 ns when 3 ;
--
CHG5 :
P5(
s_st_integer_vector ,
st_integer_vector_select ,
s_st_integer_vector_savt ,
chk_st_integer_vector ,
s_st_integer_vector_cnt ) ;
--
PGEN_CHKP_5 :
process ( chk_st_integer_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Transport transactions completed entirely",
chk_st_integer_vector = 4 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
--
with st_integer_vector_select select
s_st_integer_vector(lowb to highb-1) <= transport
c_st_integer_vector_2(lowb to highb-1) after 10 ns,
c_st_integer_vector_1(lowb to highb-1) after 20 ns
when 1,
--
c_st_integer_vector_2(lowb to highb-1) after 10 ns ,
c_st_integer_vector_1(lowb to highb-1) after 20 ns ,
c_st_integer_vector_2(lowb to highb-1) after 30 ns ,
c_st_integer_vector_1(lowb to highb-1) after 40 ns
when 2,
--
c_st_integer_vector_1(lowb to highb-1) after 5 ns when 3 ;
--
CHG6 :
P6(
s_st_time_vector ,
st_time_vector_select ,
s_st_time_vector_savt ,
chk_st_time_vector ,
s_st_time_vector_cnt ) ;
--
PGEN_CHKP_6 :
process ( chk_st_time_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Transport transactions completed entirely",
chk_st_time_vector = 4 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
--
with st_time_vector_select select
s_st_time_vector(lowb to highb-1) <= transport
c_st_time_vector_2(lowb to highb-1) after 10 ns,
c_st_time_vector_1(lowb to highb-1) after 20 ns
when 1,
--
c_st_time_vector_2(lowb to highb-1) after 10 ns ,
c_st_time_vector_1(lowb to highb-1) after 20 ns ,
c_st_time_vector_2(lowb to highb-1) after 30 ns ,
c_st_time_vector_1(lowb to highb-1) after 40 ns
when 2,
--
c_st_time_vector_1(lowb to highb-1) after 5 ns when 3 ;
--
CHG7 :
P7(
s_st_real_vector ,
st_real_vector_select ,
s_st_real_vector_savt ,
chk_st_real_vector ,
s_st_real_vector_cnt ) ;
--
PGEN_CHKP_7 :
process ( chk_st_real_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Transport transactions completed entirely",
chk_st_real_vector = 4 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
--
with st_real_vector_select select
s_st_real_vector(highb-1 to highb-1) <= transport
c_st_real_vector_2(highb-1 to highb-1) after 10 ns,
c_st_real_vector_1(highb-1 to highb-1) after 20 ns
when 1,
--
c_st_real_vector_2(highb-1 to highb-1) after 10 ns ,
c_st_real_vector_1(highb-1 to highb-1) after 20 ns ,
c_st_real_vector_2(highb-1 to highb-1) after 30 ns ,
c_st_real_vector_1(highb-1 to highb-1) after 40 ns
when 2,
--
c_st_real_vector_1(highb-1 to highb-1) after 5 ns when 3 ;
--
CHG8 :
P8(
s_st_rec1_vector ,
st_rec1_vector_select ,
s_st_rec1_vector_savt ,
chk_st_rec1_vector ,
s_st_rec1_vector_cnt ) ;
--
PGEN_CHKP_8 :
process ( chk_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Transport transactions completed entirely",
chk_st_rec1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
--
with st_rec1_vector_select select
s_st_rec1_vector(highb-1 to highb-1) <= transport
c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns,
c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns
when 1,
--
c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns ,
c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns ,
c_st_rec1_vector_2(highb-1 to highb-1) after 30 ns ,
c_st_rec1_vector_1(highb-1 to highb-1) after 40 ns
when 2,
--
c_st_rec1_vector_1(highb-1 to highb-1) after 5 ns when 3 ;
--
CHG9 :
P9(
s_st_arr2_vector ,
st_arr2_vector_select ,
s_st_arr2_vector_savt ,
chk_st_arr2_vector ,
s_st_arr2_vector_cnt ) ;
--
PGEN_CHKP_9 :
process ( chk_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Transport transactions completed entirely",
chk_st_arr2_vector = 4 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
--
with st_arr2_vector_select select
s_st_arr2_vector(lowb to highb-1) <= transport
c_st_arr2_vector_2(lowb to highb-1) after 10 ns,
c_st_arr2_vector_1(lowb to highb-1) after 20 ns
when 1,
--
c_st_arr2_vector_2(lowb to highb-1) after 10 ns ,
c_st_arr2_vector_1(lowb to highb-1) after 20 ns ,
c_st_arr2_vector_2(lowb to highb-1) after 30 ns ,
c_st_arr2_vector_1(lowb to highb-1) after 40 ns
when 2,
--
c_st_arr2_vector_1(lowb to highb-1) after 5 ns when 3 ;
--
end ARCH00615 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00615_Test_Bench is
end ENT00615_Test_Bench ;
--
--
architecture ARCH00615_Test_Bench of ENT00615_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00615 ( ARCH00615 ) ;
begin
CIS1 : UUT
;
end block L1 ;
end ARCH00615_Test_Bench ;
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`protect end_protected
| gpl-3.0 | d62e31ff0aa6c5065751e50be92cd8c3 | 0.941869 | 1.863267 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00635.vhd | 1 | 129,785 | -- NEED RESULT: ARCH00635.P1: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635.P2: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635.P3: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635.P4: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635.P5: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635.P6: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635.P7: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635.P8: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635.P9: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635.P10: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635.P11: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635.P12: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635.P13: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635.P14: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635.P15: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635.P16: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635.P17: Multi inertial transactions occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Old transactions were removed on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: One inertial transaction occurred on signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00635: Inertial semantics check on a signal asg with an aggregate of simple names on LHS passed
-- NEED RESULT: P17: Inertial transactions entirely completed passed
-- NEED RESULT: P16: Inertial transactions entirely completed passed
-- NEED RESULT: P15: Inertial transactions entirely completed passed
-- NEED RESULT: P14: Inertial transactions entirely completed passed
-- NEED RESULT: P13: Inertial transactions entirely completed passed
-- NEED RESULT: P12: Inertial transactions entirely completed passed
-- NEED RESULT: P11: Inertial transactions entirely completed passed
-- NEED RESULT: P10: Inertial transactions entirely completed passed
-- NEED RESULT: P9: Inertial transactions entirely completed passed
-- NEED RESULT: P8: Inertial transactions entirely completed passed
-- NEED RESULT: P7: Inertial transactions entirely completed passed
-- NEED RESULT: P6: Inertial transactions entirely completed passed
-- NEED RESULT: P5: Inertial transactions entirely completed passed
-- NEED RESULT: P4: Inertial transactions entirely completed passed
-- NEED RESULT: P3: Inertial transactions entirely completed passed
-- NEED RESULT: P2: Inertial transactions entirely completed passed
-- NEED RESULT: P1: Inertial transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00635
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (6)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00635)
-- ENT00635_Test_Bench(ARCH00635_Test_Bench)
--
-- REVISION HISTORY:
--
-- 25-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00635 of E00000 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_boolean : chk_sig_type := -1 ;
signal chk_bit : chk_sig_type := -1 ;
signal chk_severity_level : chk_sig_type := -1 ;
signal chk_character : chk_sig_type := -1 ;
signal chk_st_enum1 : chk_sig_type := -1 ;
signal chk_integer : chk_sig_type := -1 ;
signal chk_st_int1 : chk_sig_type := -1 ;
signal chk_time : chk_sig_type := -1 ;
signal chk_st_phys1 : chk_sig_type := -1 ;
signal chk_real : chk_sig_type := -1 ;
signal chk_st_real1 : chk_sig_type := -1 ;
signal chk_st_rec1 : chk_sig_type := -1 ;
signal chk_st_rec2 : chk_sig_type := -1 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
signal chk_st_arr1 : chk_sig_type := -1 ;
signal chk_st_arr2 : chk_sig_type := -1 ;
signal chk_st_arr3 : chk_sig_type := -1 ;
--
type arr_boolean is
array (integer range -1 downto - 3 ) of
boolean ;
type arr_bit is
array (integer range -1 downto - 3 ) of
bit ;
type arr_severity_level is
array (integer range -1 downto - 3 ) of
severity_level ;
type arr_character is
array (integer range -1 downto - 3 ) of
character ;
type arr_st_enum1 is
array (integer range -1 downto - 3 ) of
st_enum1 ;
type arr_integer is
array (integer range -1 downto - 3 ) of
integer ;
type arr_st_int1 is
array (integer range -1 downto - 3 ) of
st_int1 ;
type arr_time is
array (integer range -1 downto - 3 ) of
time ;
type arr_st_phys1 is
array (integer range -1 downto - 3 ) of
st_phys1 ;
type arr_real is
array (integer range -1 downto - 3 ) of
real ;
type arr_st_real1 is
array (integer range -1 downto - 3 ) of
st_real1 ;
type arr_st_rec1 is
array (integer range -1 downto - 3 ) of
st_rec1 ;
type arr_st_rec2 is
array (integer range -1 downto - 3 ) of
st_rec2 ;
type arr_st_rec3 is
array (integer range -1 downto - 3 ) of
st_rec3 ;
type arr_st_arr1 is
array (integer range -1 downto - 3 ) of
st_arr1 ;
type arr_st_arr2 is
array (integer range -1 downto - 3 ) of
st_arr2 ;
type arr_st_arr3 is
array (integer range -1 downto - 3 ) of
st_arr3 ;
--
signal s_boolean_1 : boolean
:= c_boolean_1 ;
signal s_bit_1 : bit
:= c_bit_1 ;
signal s_severity_level_1 : severity_level
:= c_severity_level_1 ;
signal s_character_1 : character
:= c_character_1 ;
signal s_st_enum1_1 : st_enum1
:= c_st_enum1_1 ;
signal s_integer_1 : integer
:= c_integer_1 ;
signal s_st_int1_1 : st_int1
:= c_st_int1_1 ;
signal s_time_1 : time
:= c_time_1 ;
signal s_st_phys1_1 : st_phys1
:= c_st_phys1_1 ;
signal s_real_1 : real
:= c_real_1 ;
signal s_st_real1_1 : st_real1
:= c_st_real1_1 ;
signal s_st_rec1_1 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2_1 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3_1 : st_rec3
:= c_st_rec3_1 ;
signal s_st_arr1_1 : st_arr1
:= c_st_arr1_1 ;
signal s_st_arr2_1 : st_arr2
:= c_st_arr2_1 ;
signal s_st_arr3_1 : st_arr3
:= c_st_arr3_1 ;
--
signal s_boolean_2 : boolean
:= c_boolean_1 ;
signal s_bit_2 : bit
:= c_bit_1 ;
signal s_severity_level_2 : severity_level
:= c_severity_level_1 ;
signal s_character_2 : character
:= c_character_1 ;
signal s_st_enum1_2 : st_enum1
:= c_st_enum1_1 ;
signal s_integer_2 : integer
:= c_integer_1 ;
signal s_st_int1_2 : st_int1
:= c_st_int1_1 ;
signal s_time_2 : time
:= c_time_1 ;
signal s_st_phys1_2 : st_phys1
:= c_st_phys1_1 ;
signal s_real_2 : real
:= c_real_1 ;
signal s_st_real1_2 : st_real1
:= c_st_real1_1 ;
signal s_st_rec1_2 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2_2 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3_2 : st_rec3
:= c_st_rec3_1 ;
signal s_st_arr1_2 : st_arr1
:= c_st_arr1_1 ;
signal s_st_arr2_2 : st_arr2
:= c_st_arr2_1 ;
signal s_st_arr3_2 : st_arr3
:= c_st_arr3_1 ;
--
signal s_boolean_3 : boolean
:= c_boolean_1 ;
signal s_bit_3 : bit
:= c_bit_1 ;
signal s_severity_level_3 : severity_level
:= c_severity_level_1 ;
signal s_character_3 : character
:= c_character_1 ;
signal s_st_enum1_3 : st_enum1
:= c_st_enum1_1 ;
signal s_integer_3 : integer
:= c_integer_1 ;
signal s_st_int1_3 : st_int1
:= c_st_int1_1 ;
signal s_time_3 : time
:= c_time_1 ;
signal s_st_phys1_3 : st_phys1
:= c_st_phys1_1 ;
signal s_real_3 : real
:= c_real_1 ;
signal s_st_real1_3 : st_real1
:= c_st_real1_1 ;
signal s_st_rec1_3 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2_3 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3_3 : st_rec3
:= c_st_rec3_1 ;
signal s_st_arr1_3 : st_arr1
:= c_st_arr1_1 ;
signal s_st_arr2_3 : st_arr2
:= c_st_arr2_1 ;
signal s_st_arr3_3 : st_arr3
:= c_st_arr3_1 ;
--
begin
P1 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_boolean_1,
s_boolean_2,
s_boolean_3) <=
arr_boolean ' (
(c_boolean_2,
c_boolean_2,
c_boolean_2) ) after 10 ns,
arr_boolean ' (
(c_boolean_1,
c_boolean_1,
c_boolean_1) ) after 20 ns ;
--
when 1
=> correct :=
s_boolean_1 = c_boolean_2 and
s_boolean_2 = c_boolean_2 and
s_boolean_3 = c_boolean_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_boolean_1 = c_boolean_1 and
s_boolean_2 = c_boolean_1 and
s_boolean_3 = c_boolean_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_boolean_1,
s_boolean_2,
s_boolean_3) <=
arr_boolean ' (
(c_boolean_2,
c_boolean_2,
c_boolean_2) ) after 10 ns,
arr_boolean ' (
(c_boolean_1,
c_boolean_1,
c_boolean_1) ) after 20 ns ,
arr_boolean ' (
(c_boolean_2,
c_boolean_2,
c_boolean_2) ) after 30 ns,
arr_boolean ' (
(c_boolean_1,
c_boolean_1,
c_boolean_1) ) after 40 ns ;
--
when 3
=> correct :=
s_boolean_1 = c_boolean_2 and
s_boolean_2 = c_boolean_2 and
s_boolean_3 = c_boolean_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_boolean_1,
s_boolean_2,
s_boolean_3) <=
arr_boolean ' (
(c_boolean_1,
c_boolean_1,
c_boolean_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_boolean_1 = c_boolean_1 and
s_boolean_2 = c_boolean_1 and
s_boolean_3 = c_boolean_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_boolean_1,
s_boolean_2,
s_boolean_3) <= transport
arr_boolean ' (
(c_boolean_2,
c_boolean_2,
c_boolean_2) ) after 100 ns ;
--
when 5
=> correct :=
s_boolean_1 = c_boolean_2 and
s_boolean_2 = c_boolean_2 and
s_boolean_3 = c_boolean_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_boolean_1,
s_boolean_2,
s_boolean_3) <=
arr_boolean ' (
(c_boolean_1,
c_boolean_1,
c_boolean_1) ) after 10 ns ,
arr_boolean ' (
(c_boolean_2,
c_boolean_2,
c_boolean_2) ) after 20 ns ,
arr_boolean ' (
(c_boolean_1,
c_boolean_1,
c_boolean_1) ) after 30 ns ,
arr_boolean ' (
(c_boolean_2,
c_boolean_2,
c_boolean_2) ) after 40 ns ;
--
when 6
=> correct :=
s_boolean_1 = c_boolean_1 and
s_boolean_2 = c_boolean_1 and
s_boolean_3 = c_boolean_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_boolean_1,
s_boolean_2,
s_boolean_3) <=
arr_boolean ' (
(c_boolean_2,
c_boolean_2,
c_boolean_2) ) after 40 ns ;
--
when 7
=> correct :=
s_boolean_1 = c_boolean_2 and
s_boolean_2 = c_boolean_2 and
s_boolean_3 = c_boolean_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_boolean_1,
s_boolean_2,
s_boolean_3) <=
arr_boolean ' (
(c_boolean_1,
c_boolean_1,
c_boolean_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_boolean_1 = c_boolean_1 and
s_boolean_2 = c_boolean_1 and
s_boolean_3 = c_boolean_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_boolean <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_boolean_1'ACTIVE and
s_boolean_2'ACTIVE and
s_boolean_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_boolean )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_boolean = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P2 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_bit_1,
s_bit_2,
s_bit_3) <=
arr_bit ' (
(c_bit_2,
c_bit_2,
c_bit_2) ) after 10 ns,
arr_bit ' (
(c_bit_1,
c_bit_1,
c_bit_1) ) after 20 ns ;
--
when 1
=> correct :=
s_bit_1 = c_bit_2 and
s_bit_2 = c_bit_2 and
s_bit_3 = c_bit_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_bit_1 = c_bit_1 and
s_bit_2 = c_bit_1 and
s_bit_3 = c_bit_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635.P2" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_bit_1,
s_bit_2,
s_bit_3) <=
arr_bit ' (
(c_bit_2,
c_bit_2,
c_bit_2) ) after 10 ns,
arr_bit ' (
(c_bit_1,
c_bit_1,
c_bit_1) ) after 20 ns ,
arr_bit ' (
(c_bit_2,
c_bit_2,
c_bit_2) ) after 30 ns,
arr_bit ' (
(c_bit_1,
c_bit_1,
c_bit_1) ) after 40 ns ;
--
when 3
=> correct :=
s_bit_1 = c_bit_2 and
s_bit_2 = c_bit_2 and
s_bit_3 = c_bit_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_bit_1,
s_bit_2,
s_bit_3) <=
arr_bit ' (
(c_bit_1,
c_bit_1,
c_bit_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_bit_1 = c_bit_1 and
s_bit_2 = c_bit_1 and
s_bit_3 = c_bit_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_bit_1,
s_bit_2,
s_bit_3) <= transport
arr_bit ' (
(c_bit_2,
c_bit_2,
c_bit_2) ) after 100 ns ;
--
when 5
=> correct :=
s_bit_1 = c_bit_2 and
s_bit_2 = c_bit_2 and
s_bit_3 = c_bit_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_bit_1,
s_bit_2,
s_bit_3) <=
arr_bit ' (
(c_bit_1,
c_bit_1,
c_bit_1) ) after 10 ns ,
arr_bit ' (
(c_bit_2,
c_bit_2,
c_bit_2) ) after 20 ns ,
arr_bit ' (
(c_bit_1,
c_bit_1,
c_bit_1) ) after 30 ns ,
arr_bit ' (
(c_bit_2,
c_bit_2,
c_bit_2) ) after 40 ns ;
--
when 6
=> correct :=
s_bit_1 = c_bit_1 and
s_bit_2 = c_bit_1 and
s_bit_3 = c_bit_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_bit_1,
s_bit_2,
s_bit_3) <=
arr_bit ' (
(c_bit_2,
c_bit_2,
c_bit_2) ) after 40 ns ;
--
when 7
=> correct :=
s_bit_1 = c_bit_2 and
s_bit_2 = c_bit_2 and
s_bit_3 = c_bit_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_bit_1,
s_bit_2,
s_bit_3) <=
arr_bit ' (
(c_bit_1,
c_bit_1,
c_bit_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_bit_1 = c_bit_1 and
s_bit_2 = c_bit_1 and
s_bit_3 = c_bit_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_bit <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_bit_1'ACTIVE and
s_bit_2'ACTIVE and
s_bit_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P2 ;
--
PGEN_CHKP_2 :
process ( chk_bit )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions entirely completed",
chk_bit = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P3 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_severity_level_1,
s_severity_level_2,
s_severity_level_3) <=
arr_severity_level ' (
(c_severity_level_2,
c_severity_level_2,
c_severity_level_2) ) after 10 ns,
arr_severity_level ' (
(c_severity_level_1,
c_severity_level_1,
c_severity_level_1) ) after 20 ns ;
--
when 1
=> correct :=
s_severity_level_1 = c_severity_level_2 and
s_severity_level_2 = c_severity_level_2 and
s_severity_level_3 = c_severity_level_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_severity_level_1 = c_severity_level_1 and
s_severity_level_2 = c_severity_level_1 and
s_severity_level_3 = c_severity_level_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635.P3" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_severity_level_1,
s_severity_level_2,
s_severity_level_3) <=
arr_severity_level ' (
(c_severity_level_2,
c_severity_level_2,
c_severity_level_2) ) after 10 ns,
arr_severity_level ' (
(c_severity_level_1,
c_severity_level_1,
c_severity_level_1) ) after 20 ns ,
arr_severity_level ' (
(c_severity_level_2,
c_severity_level_2,
c_severity_level_2) ) after 30 ns,
arr_severity_level ' (
(c_severity_level_1,
c_severity_level_1,
c_severity_level_1) ) after 40 ns ;
--
when 3
=> correct :=
s_severity_level_1 = c_severity_level_2 and
s_severity_level_2 = c_severity_level_2 and
s_severity_level_3 = c_severity_level_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_severity_level_1,
s_severity_level_2,
s_severity_level_3) <=
arr_severity_level ' (
(c_severity_level_1,
c_severity_level_1,
c_severity_level_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_severity_level_1 = c_severity_level_1 and
s_severity_level_2 = c_severity_level_1 and
s_severity_level_3 = c_severity_level_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_severity_level_1,
s_severity_level_2,
s_severity_level_3) <= transport
arr_severity_level ' (
(c_severity_level_2,
c_severity_level_2,
c_severity_level_2) ) after 100 ns ;
--
when 5
=> correct :=
s_severity_level_1 = c_severity_level_2 and
s_severity_level_2 = c_severity_level_2 and
s_severity_level_3 = c_severity_level_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_severity_level_1,
s_severity_level_2,
s_severity_level_3) <=
arr_severity_level ' (
(c_severity_level_1,
c_severity_level_1,
c_severity_level_1) ) after 10 ns ,
arr_severity_level ' (
(c_severity_level_2,
c_severity_level_2,
c_severity_level_2) ) after 20 ns ,
arr_severity_level ' (
(c_severity_level_1,
c_severity_level_1,
c_severity_level_1) ) after 30 ns ,
arr_severity_level ' (
(c_severity_level_2,
c_severity_level_2,
c_severity_level_2) ) after 40 ns ;
--
when 6
=> correct :=
s_severity_level_1 = c_severity_level_1 and
s_severity_level_2 = c_severity_level_1 and
s_severity_level_3 = c_severity_level_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_severity_level_1,
s_severity_level_2,
s_severity_level_3) <=
arr_severity_level ' (
(c_severity_level_2,
c_severity_level_2,
c_severity_level_2) ) after 40 ns ;
--
when 7
=> correct :=
s_severity_level_1 = c_severity_level_2 and
s_severity_level_2 = c_severity_level_2 and
s_severity_level_3 = c_severity_level_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_severity_level_1,
s_severity_level_2,
s_severity_level_3) <=
arr_severity_level ' (
(c_severity_level_1,
c_severity_level_1,
c_severity_level_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_severity_level_1 = c_severity_level_1 and
s_severity_level_2 = c_severity_level_1 and
s_severity_level_3 = c_severity_level_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_severity_level <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_severity_level_1'ACTIVE and
s_severity_level_2'ACTIVE and
s_severity_level_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P3 ;
--
PGEN_CHKP_3 :
process ( chk_severity_level )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions entirely completed",
chk_severity_level = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P4 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_character_1,
s_character_2,
s_character_3) <=
arr_character ' (
(c_character_2,
c_character_2,
c_character_2) ) after 10 ns,
arr_character ' (
(c_character_1,
c_character_1,
c_character_1) ) after 20 ns ;
--
when 1
=> correct :=
s_character_1 = c_character_2 and
s_character_2 = c_character_2 and
s_character_3 = c_character_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_character_1 = c_character_1 and
s_character_2 = c_character_1 and
s_character_3 = c_character_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635.P4" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_character_1,
s_character_2,
s_character_3) <=
arr_character ' (
(c_character_2,
c_character_2,
c_character_2) ) after 10 ns,
arr_character ' (
(c_character_1,
c_character_1,
c_character_1) ) after 20 ns ,
arr_character ' (
(c_character_2,
c_character_2,
c_character_2) ) after 30 ns,
arr_character ' (
(c_character_1,
c_character_1,
c_character_1) ) after 40 ns ;
--
when 3
=> correct :=
s_character_1 = c_character_2 and
s_character_2 = c_character_2 and
s_character_3 = c_character_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_character_1,
s_character_2,
s_character_3) <=
arr_character ' (
(c_character_1,
c_character_1,
c_character_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_character_1 = c_character_1 and
s_character_2 = c_character_1 and
s_character_3 = c_character_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_character_1,
s_character_2,
s_character_3) <= transport
arr_character ' (
(c_character_2,
c_character_2,
c_character_2) ) after 100 ns ;
--
when 5
=> correct :=
s_character_1 = c_character_2 and
s_character_2 = c_character_2 and
s_character_3 = c_character_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_character_1,
s_character_2,
s_character_3) <=
arr_character ' (
(c_character_1,
c_character_1,
c_character_1) ) after 10 ns ,
arr_character ' (
(c_character_2,
c_character_2,
c_character_2) ) after 20 ns ,
arr_character ' (
(c_character_1,
c_character_1,
c_character_1) ) after 30 ns ,
arr_character ' (
(c_character_2,
c_character_2,
c_character_2) ) after 40 ns ;
--
when 6
=> correct :=
s_character_1 = c_character_1 and
s_character_2 = c_character_1 and
s_character_3 = c_character_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_character_1,
s_character_2,
s_character_3) <=
arr_character ' (
(c_character_2,
c_character_2,
c_character_2) ) after 40 ns ;
--
when 7
=> correct :=
s_character_1 = c_character_2 and
s_character_2 = c_character_2 and
s_character_3 = c_character_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_character_1,
s_character_2,
s_character_3) <=
arr_character ' (
(c_character_1,
c_character_1,
c_character_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_character_1 = c_character_1 and
s_character_2 = c_character_1 and
s_character_3 = c_character_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_character <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_character_1'ACTIVE and
s_character_2'ACTIVE and
s_character_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P4 ;
--
PGEN_CHKP_4 :
process ( chk_character )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Inertial transactions entirely completed",
chk_character = 8 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
P5 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_enum1_1,
s_st_enum1_2,
s_st_enum1_3) <=
arr_st_enum1 ' (
(c_st_enum1_2,
c_st_enum1_2,
c_st_enum1_2) ) after 10 ns,
arr_st_enum1 ' (
(c_st_enum1_1,
c_st_enum1_1,
c_st_enum1_1) ) after 20 ns ;
--
when 1
=> correct :=
s_st_enum1_1 = c_st_enum1_2 and
s_st_enum1_2 = c_st_enum1_2 and
s_st_enum1_3 = c_st_enum1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1_1 = c_st_enum1_1 and
s_st_enum1_2 = c_st_enum1_1 and
s_st_enum1_3 = c_st_enum1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635.P5" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_enum1_1,
s_st_enum1_2,
s_st_enum1_3) <=
arr_st_enum1 ' (
(c_st_enum1_2,
c_st_enum1_2,
c_st_enum1_2) ) after 10 ns,
arr_st_enum1 ' (
(c_st_enum1_1,
c_st_enum1_1,
c_st_enum1_1) ) after 20 ns ,
arr_st_enum1 ' (
(c_st_enum1_2,
c_st_enum1_2,
c_st_enum1_2) ) after 30 ns,
arr_st_enum1 ' (
(c_st_enum1_1,
c_st_enum1_1,
c_st_enum1_1) ) after 40 ns ;
--
when 3
=> correct :=
s_st_enum1_1 = c_st_enum1_2 and
s_st_enum1_2 = c_st_enum1_2 and
s_st_enum1_3 = c_st_enum1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_enum1_1,
s_st_enum1_2,
s_st_enum1_3) <=
arr_st_enum1 ' (
(c_st_enum1_1,
c_st_enum1_1,
c_st_enum1_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1_1 = c_st_enum1_1 and
s_st_enum1_2 = c_st_enum1_1 and
s_st_enum1_3 = c_st_enum1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_enum1_1,
s_st_enum1_2,
s_st_enum1_3) <= transport
arr_st_enum1 ' (
(c_st_enum1_2,
c_st_enum1_2,
c_st_enum1_2) ) after 100 ns ;
--
when 5
=> correct :=
s_st_enum1_1 = c_st_enum1_2 and
s_st_enum1_2 = c_st_enum1_2 and
s_st_enum1_3 = c_st_enum1_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_enum1_1,
s_st_enum1_2,
s_st_enum1_3) <=
arr_st_enum1 ' (
(c_st_enum1_1,
c_st_enum1_1,
c_st_enum1_1) ) after 10 ns ,
arr_st_enum1 ' (
(c_st_enum1_2,
c_st_enum1_2,
c_st_enum1_2) ) after 20 ns ,
arr_st_enum1 ' (
(c_st_enum1_1,
c_st_enum1_1,
c_st_enum1_1) ) after 30 ns ,
arr_st_enum1 ' (
(c_st_enum1_2,
c_st_enum1_2,
c_st_enum1_2) ) after 40 ns ;
--
when 6
=> correct :=
s_st_enum1_1 = c_st_enum1_1 and
s_st_enum1_2 = c_st_enum1_1 and
s_st_enum1_3 = c_st_enum1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_st_enum1_1,
s_st_enum1_2,
s_st_enum1_3) <=
arr_st_enum1 ' (
(c_st_enum1_2,
c_st_enum1_2,
c_st_enum1_2) ) after 40 ns ;
--
when 7
=> correct :=
s_st_enum1_1 = c_st_enum1_2 and
s_st_enum1_2 = c_st_enum1_2 and
s_st_enum1_3 = c_st_enum1_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_st_enum1_1,
s_st_enum1_2,
s_st_enum1_3) <=
arr_st_enum1 ' (
(c_st_enum1_1,
c_st_enum1_1,
c_st_enum1_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_st_enum1_1 = c_st_enum1_1 and
s_st_enum1_2 = c_st_enum1_1 and
s_st_enum1_3 = c_st_enum1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_enum1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_st_enum1_1'ACTIVE and
s_st_enum1_2'ACTIVE and
s_st_enum1_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P5 ;
--
PGEN_CHKP_5 :
process ( chk_st_enum1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Inertial transactions entirely completed",
chk_st_enum1 = 8 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
P6 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_integer_1,
s_integer_2,
s_integer_3) <=
arr_integer ' (
(c_integer_2,
c_integer_2,
c_integer_2) ) after 10 ns,
arr_integer ' (
(c_integer_1,
c_integer_1,
c_integer_1) ) after 20 ns ;
--
when 1
=> correct :=
s_integer_1 = c_integer_2 and
s_integer_2 = c_integer_2 and
s_integer_3 = c_integer_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_integer_1 = c_integer_1 and
s_integer_2 = c_integer_1 and
s_integer_3 = c_integer_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635.P6" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_integer_1,
s_integer_2,
s_integer_3) <=
arr_integer ' (
(c_integer_2,
c_integer_2,
c_integer_2) ) after 10 ns,
arr_integer ' (
(c_integer_1,
c_integer_1,
c_integer_1) ) after 20 ns ,
arr_integer ' (
(c_integer_2,
c_integer_2,
c_integer_2) ) after 30 ns,
arr_integer ' (
(c_integer_1,
c_integer_1,
c_integer_1) ) after 40 ns ;
--
when 3
=> correct :=
s_integer_1 = c_integer_2 and
s_integer_2 = c_integer_2 and
s_integer_3 = c_integer_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_integer_1,
s_integer_2,
s_integer_3) <=
arr_integer ' (
(c_integer_1,
c_integer_1,
c_integer_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_integer_1 = c_integer_1 and
s_integer_2 = c_integer_1 and
s_integer_3 = c_integer_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_integer_1,
s_integer_2,
s_integer_3) <= transport
arr_integer ' (
(c_integer_2,
c_integer_2,
c_integer_2) ) after 100 ns ;
--
when 5
=> correct :=
s_integer_1 = c_integer_2 and
s_integer_2 = c_integer_2 and
s_integer_3 = c_integer_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_integer_1,
s_integer_2,
s_integer_3) <=
arr_integer ' (
(c_integer_1,
c_integer_1,
c_integer_1) ) after 10 ns ,
arr_integer ' (
(c_integer_2,
c_integer_2,
c_integer_2) ) after 20 ns ,
arr_integer ' (
(c_integer_1,
c_integer_1,
c_integer_1) ) after 30 ns ,
arr_integer ' (
(c_integer_2,
c_integer_2,
c_integer_2) ) after 40 ns ;
--
when 6
=> correct :=
s_integer_1 = c_integer_1 and
s_integer_2 = c_integer_1 and
s_integer_3 = c_integer_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_integer_1,
s_integer_2,
s_integer_3) <=
arr_integer ' (
(c_integer_2,
c_integer_2,
c_integer_2) ) after 40 ns ;
--
when 7
=> correct :=
s_integer_1 = c_integer_2 and
s_integer_2 = c_integer_2 and
s_integer_3 = c_integer_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_integer_1,
s_integer_2,
s_integer_3) <=
arr_integer ' (
(c_integer_1,
c_integer_1,
c_integer_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_integer_1 = c_integer_1 and
s_integer_2 = c_integer_1 and
s_integer_3 = c_integer_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_integer <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_integer_1'ACTIVE and
s_integer_2'ACTIVE and
s_integer_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P6 ;
--
PGEN_CHKP_6 :
process ( chk_integer )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Inertial transactions entirely completed",
chk_integer = 8 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
P7 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_int1_1,
s_st_int1_2,
s_st_int1_3) <=
arr_st_int1 ' (
(c_st_int1_2,
c_st_int1_2,
c_st_int1_2) ) after 10 ns,
arr_st_int1 ' (
(c_st_int1_1,
c_st_int1_1,
c_st_int1_1) ) after 20 ns ;
--
when 1
=> correct :=
s_st_int1_1 = c_st_int1_2 and
s_st_int1_2 = c_st_int1_2 and
s_st_int1_3 = c_st_int1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_int1_1 = c_st_int1_1 and
s_st_int1_2 = c_st_int1_1 and
s_st_int1_3 = c_st_int1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635.P7" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_int1_1,
s_st_int1_2,
s_st_int1_3) <=
arr_st_int1 ' (
(c_st_int1_2,
c_st_int1_2,
c_st_int1_2) ) after 10 ns,
arr_st_int1 ' (
(c_st_int1_1,
c_st_int1_1,
c_st_int1_1) ) after 20 ns ,
arr_st_int1 ' (
(c_st_int1_2,
c_st_int1_2,
c_st_int1_2) ) after 30 ns,
arr_st_int1 ' (
(c_st_int1_1,
c_st_int1_1,
c_st_int1_1) ) after 40 ns ;
--
when 3
=> correct :=
s_st_int1_1 = c_st_int1_2 and
s_st_int1_2 = c_st_int1_2 and
s_st_int1_3 = c_st_int1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_int1_1,
s_st_int1_2,
s_st_int1_3) <=
arr_st_int1 ' (
(c_st_int1_1,
c_st_int1_1,
c_st_int1_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_int1_1 = c_st_int1_1 and
s_st_int1_2 = c_st_int1_1 and
s_st_int1_3 = c_st_int1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_int1_1,
s_st_int1_2,
s_st_int1_3) <= transport
arr_st_int1 ' (
(c_st_int1_2,
c_st_int1_2,
c_st_int1_2) ) after 100 ns ;
--
when 5
=> correct :=
s_st_int1_1 = c_st_int1_2 and
s_st_int1_2 = c_st_int1_2 and
s_st_int1_3 = c_st_int1_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_int1_1,
s_st_int1_2,
s_st_int1_3) <=
arr_st_int1 ' (
(c_st_int1_1,
c_st_int1_1,
c_st_int1_1) ) after 10 ns ,
arr_st_int1 ' (
(c_st_int1_2,
c_st_int1_2,
c_st_int1_2) ) after 20 ns ,
arr_st_int1 ' (
(c_st_int1_1,
c_st_int1_1,
c_st_int1_1) ) after 30 ns ,
arr_st_int1 ' (
(c_st_int1_2,
c_st_int1_2,
c_st_int1_2) ) after 40 ns ;
--
when 6
=> correct :=
s_st_int1_1 = c_st_int1_1 and
s_st_int1_2 = c_st_int1_1 and
s_st_int1_3 = c_st_int1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_st_int1_1,
s_st_int1_2,
s_st_int1_3) <=
arr_st_int1 ' (
(c_st_int1_2,
c_st_int1_2,
c_st_int1_2) ) after 40 ns ;
--
when 7
=> correct :=
s_st_int1_1 = c_st_int1_2 and
s_st_int1_2 = c_st_int1_2 and
s_st_int1_3 = c_st_int1_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_st_int1_1,
s_st_int1_2,
s_st_int1_3) <=
arr_st_int1 ' (
(c_st_int1_1,
c_st_int1_1,
c_st_int1_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_st_int1_1 = c_st_int1_1 and
s_st_int1_2 = c_st_int1_1 and
s_st_int1_3 = c_st_int1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_int1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_st_int1_1'ACTIVE and
s_st_int1_2'ACTIVE and
s_st_int1_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P7 ;
--
PGEN_CHKP_7 :
process ( chk_st_int1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Inertial transactions entirely completed",
chk_st_int1 = 8 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
P8 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_time_1,
s_time_2,
s_time_3) <=
arr_time ' (
(c_time_2,
c_time_2,
c_time_2) ) after 10 ns,
arr_time ' (
(c_time_1,
c_time_1,
c_time_1) ) after 20 ns ;
--
when 1
=> correct :=
s_time_1 = c_time_2 and
s_time_2 = c_time_2 and
s_time_3 = c_time_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_time_1 = c_time_1 and
s_time_2 = c_time_1 and
s_time_3 = c_time_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635.P8" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_time_1,
s_time_2,
s_time_3) <=
arr_time ' (
(c_time_2,
c_time_2,
c_time_2) ) after 10 ns,
arr_time ' (
(c_time_1,
c_time_1,
c_time_1) ) after 20 ns ,
arr_time ' (
(c_time_2,
c_time_2,
c_time_2) ) after 30 ns,
arr_time ' (
(c_time_1,
c_time_1,
c_time_1) ) after 40 ns ;
--
when 3
=> correct :=
s_time_1 = c_time_2 and
s_time_2 = c_time_2 and
s_time_3 = c_time_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_time_1,
s_time_2,
s_time_3) <=
arr_time ' (
(c_time_1,
c_time_1,
c_time_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_time_1 = c_time_1 and
s_time_2 = c_time_1 and
s_time_3 = c_time_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_time_1,
s_time_2,
s_time_3) <= transport
arr_time ' (
(c_time_2,
c_time_2,
c_time_2) ) after 100 ns ;
--
when 5
=> correct :=
s_time_1 = c_time_2 and
s_time_2 = c_time_2 and
s_time_3 = c_time_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_time_1,
s_time_2,
s_time_3) <=
arr_time ' (
(c_time_1,
c_time_1,
c_time_1) ) after 10 ns ,
arr_time ' (
(c_time_2,
c_time_2,
c_time_2) ) after 20 ns ,
arr_time ' (
(c_time_1,
c_time_1,
c_time_1) ) after 30 ns ,
arr_time ' (
(c_time_2,
c_time_2,
c_time_2) ) after 40 ns ;
--
when 6
=> correct :=
s_time_1 = c_time_1 and
s_time_2 = c_time_1 and
s_time_3 = c_time_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_time_1,
s_time_2,
s_time_3) <=
arr_time ' (
(c_time_2,
c_time_2,
c_time_2) ) after 40 ns ;
--
when 7
=> correct :=
s_time_1 = c_time_2 and
s_time_2 = c_time_2 and
s_time_3 = c_time_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_time_1,
s_time_2,
s_time_3) <=
arr_time ' (
(c_time_1,
c_time_1,
c_time_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_time_1 = c_time_1 and
s_time_2 = c_time_1 and
s_time_3 = c_time_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_time <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_time_1'ACTIVE and
s_time_2'ACTIVE and
s_time_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P8 ;
--
PGEN_CHKP_8 :
process ( chk_time )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Inertial transactions entirely completed",
chk_time = 8 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
P9 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_phys1_1,
s_st_phys1_2,
s_st_phys1_3) <=
arr_st_phys1 ' (
(c_st_phys1_2,
c_st_phys1_2,
c_st_phys1_2) ) after 10 ns,
arr_st_phys1 ' (
(c_st_phys1_1,
c_st_phys1_1,
c_st_phys1_1) ) after 20 ns ;
--
when 1
=> correct :=
s_st_phys1_1 = c_st_phys1_2 and
s_st_phys1_2 = c_st_phys1_2 and
s_st_phys1_3 = c_st_phys1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_phys1_1 = c_st_phys1_1 and
s_st_phys1_2 = c_st_phys1_1 and
s_st_phys1_3 = c_st_phys1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635.P9" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_phys1_1,
s_st_phys1_2,
s_st_phys1_3) <=
arr_st_phys1 ' (
(c_st_phys1_2,
c_st_phys1_2,
c_st_phys1_2) ) after 10 ns,
arr_st_phys1 ' (
(c_st_phys1_1,
c_st_phys1_1,
c_st_phys1_1) ) after 20 ns ,
arr_st_phys1 ' (
(c_st_phys1_2,
c_st_phys1_2,
c_st_phys1_2) ) after 30 ns,
arr_st_phys1 ' (
(c_st_phys1_1,
c_st_phys1_1,
c_st_phys1_1) ) after 40 ns ;
--
when 3
=> correct :=
s_st_phys1_1 = c_st_phys1_2 and
s_st_phys1_2 = c_st_phys1_2 and
s_st_phys1_3 = c_st_phys1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_phys1_1,
s_st_phys1_2,
s_st_phys1_3) <=
arr_st_phys1 ' (
(c_st_phys1_1,
c_st_phys1_1,
c_st_phys1_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_phys1_1 = c_st_phys1_1 and
s_st_phys1_2 = c_st_phys1_1 and
s_st_phys1_3 = c_st_phys1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_phys1_1,
s_st_phys1_2,
s_st_phys1_3) <= transport
arr_st_phys1 ' (
(c_st_phys1_2,
c_st_phys1_2,
c_st_phys1_2) ) after 100 ns ;
--
when 5
=> correct :=
s_st_phys1_1 = c_st_phys1_2 and
s_st_phys1_2 = c_st_phys1_2 and
s_st_phys1_3 = c_st_phys1_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_phys1_1,
s_st_phys1_2,
s_st_phys1_3) <=
arr_st_phys1 ' (
(c_st_phys1_1,
c_st_phys1_1,
c_st_phys1_1) ) after 10 ns ,
arr_st_phys1 ' (
(c_st_phys1_2,
c_st_phys1_2,
c_st_phys1_2) ) after 20 ns ,
arr_st_phys1 ' (
(c_st_phys1_1,
c_st_phys1_1,
c_st_phys1_1) ) after 30 ns ,
arr_st_phys1 ' (
(c_st_phys1_2,
c_st_phys1_2,
c_st_phys1_2) ) after 40 ns ;
--
when 6
=> correct :=
s_st_phys1_1 = c_st_phys1_1 and
s_st_phys1_2 = c_st_phys1_1 and
s_st_phys1_3 = c_st_phys1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_st_phys1_1,
s_st_phys1_2,
s_st_phys1_3) <=
arr_st_phys1 ' (
(c_st_phys1_2,
c_st_phys1_2,
c_st_phys1_2) ) after 40 ns ;
--
when 7
=> correct :=
s_st_phys1_1 = c_st_phys1_2 and
s_st_phys1_2 = c_st_phys1_2 and
s_st_phys1_3 = c_st_phys1_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_st_phys1_1,
s_st_phys1_2,
s_st_phys1_3) <=
arr_st_phys1 ' (
(c_st_phys1_1,
c_st_phys1_1,
c_st_phys1_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_st_phys1_1 = c_st_phys1_1 and
s_st_phys1_2 = c_st_phys1_1 and
s_st_phys1_3 = c_st_phys1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_phys1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_st_phys1_1'ACTIVE and
s_st_phys1_2'ACTIVE and
s_st_phys1_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P9 ;
--
PGEN_CHKP_9 :
process ( chk_st_phys1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Inertial transactions entirely completed",
chk_st_phys1 = 8 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
P10 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_real_1,
s_real_2,
s_real_3) <=
arr_real ' (
(c_real_2,
c_real_2,
c_real_2) ) after 10 ns,
arr_real ' (
(c_real_1,
c_real_1,
c_real_1) ) after 20 ns ;
--
when 1
=> correct :=
s_real_1 = c_real_2 and
s_real_2 = c_real_2 and
s_real_3 = c_real_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_real_1 = c_real_1 and
s_real_2 = c_real_1 and
s_real_3 = c_real_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635.P10" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_real_1,
s_real_2,
s_real_3) <=
arr_real ' (
(c_real_2,
c_real_2,
c_real_2) ) after 10 ns,
arr_real ' (
(c_real_1,
c_real_1,
c_real_1) ) after 20 ns ,
arr_real ' (
(c_real_2,
c_real_2,
c_real_2) ) after 30 ns,
arr_real ' (
(c_real_1,
c_real_1,
c_real_1) ) after 40 ns ;
--
when 3
=> correct :=
s_real_1 = c_real_2 and
s_real_2 = c_real_2 and
s_real_3 = c_real_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_real_1,
s_real_2,
s_real_3) <=
arr_real ' (
(c_real_1,
c_real_1,
c_real_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_real_1 = c_real_1 and
s_real_2 = c_real_1 and
s_real_3 = c_real_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_real_1,
s_real_2,
s_real_3) <= transport
arr_real ' (
(c_real_2,
c_real_2,
c_real_2) ) after 100 ns ;
--
when 5
=> correct :=
s_real_1 = c_real_2 and
s_real_2 = c_real_2 and
s_real_3 = c_real_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_real_1,
s_real_2,
s_real_3) <=
arr_real ' (
(c_real_1,
c_real_1,
c_real_1) ) after 10 ns ,
arr_real ' (
(c_real_2,
c_real_2,
c_real_2) ) after 20 ns ,
arr_real ' (
(c_real_1,
c_real_1,
c_real_1) ) after 30 ns ,
arr_real ' (
(c_real_2,
c_real_2,
c_real_2) ) after 40 ns ;
--
when 6
=> correct :=
s_real_1 = c_real_1 and
s_real_2 = c_real_1 and
s_real_3 = c_real_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_real_1,
s_real_2,
s_real_3) <=
arr_real ' (
(c_real_2,
c_real_2,
c_real_2) ) after 40 ns ;
--
when 7
=> correct :=
s_real_1 = c_real_2 and
s_real_2 = c_real_2 and
s_real_3 = c_real_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_real_1,
s_real_2,
s_real_3) <=
arr_real ' (
(c_real_1,
c_real_1,
c_real_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_real_1 = c_real_1 and
s_real_2 = c_real_1 and
s_real_3 = c_real_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_real <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_real_1'ACTIVE and
s_real_2'ACTIVE and
s_real_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P10 ;
--
PGEN_CHKP_10 :
process ( chk_real )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Inertial transactions entirely completed",
chk_real = 8 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
P11 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_real1_1,
s_st_real1_2,
s_st_real1_3) <=
arr_st_real1 ' (
(c_st_real1_2,
c_st_real1_2,
c_st_real1_2) ) after 10 ns,
arr_st_real1 ' (
(c_st_real1_1,
c_st_real1_1,
c_st_real1_1) ) after 20 ns ;
--
when 1
=> correct :=
s_st_real1_1 = c_st_real1_2 and
s_st_real1_2 = c_st_real1_2 and
s_st_real1_3 = c_st_real1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real1_1 = c_st_real1_1 and
s_st_real1_2 = c_st_real1_1 and
s_st_real1_3 = c_st_real1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635.P11" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_real1_1,
s_st_real1_2,
s_st_real1_3) <=
arr_st_real1 ' (
(c_st_real1_2,
c_st_real1_2,
c_st_real1_2) ) after 10 ns,
arr_st_real1 ' (
(c_st_real1_1,
c_st_real1_1,
c_st_real1_1) ) after 20 ns ,
arr_st_real1 ' (
(c_st_real1_2,
c_st_real1_2,
c_st_real1_2) ) after 30 ns,
arr_st_real1 ' (
(c_st_real1_1,
c_st_real1_1,
c_st_real1_1) ) after 40 ns ;
--
when 3
=> correct :=
s_st_real1_1 = c_st_real1_2 and
s_st_real1_2 = c_st_real1_2 and
s_st_real1_3 = c_st_real1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_real1_1,
s_st_real1_2,
s_st_real1_3) <=
arr_st_real1 ' (
(c_st_real1_1,
c_st_real1_1,
c_st_real1_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real1_1 = c_st_real1_1 and
s_st_real1_2 = c_st_real1_1 and
s_st_real1_3 = c_st_real1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_real1_1,
s_st_real1_2,
s_st_real1_3) <= transport
arr_st_real1 ' (
(c_st_real1_2,
c_st_real1_2,
c_st_real1_2) ) after 100 ns ;
--
when 5
=> correct :=
s_st_real1_1 = c_st_real1_2 and
s_st_real1_2 = c_st_real1_2 and
s_st_real1_3 = c_st_real1_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_real1_1,
s_st_real1_2,
s_st_real1_3) <=
arr_st_real1 ' (
(c_st_real1_1,
c_st_real1_1,
c_st_real1_1) ) after 10 ns ,
arr_st_real1 ' (
(c_st_real1_2,
c_st_real1_2,
c_st_real1_2) ) after 20 ns ,
arr_st_real1 ' (
(c_st_real1_1,
c_st_real1_1,
c_st_real1_1) ) after 30 ns ,
arr_st_real1 ' (
(c_st_real1_2,
c_st_real1_2,
c_st_real1_2) ) after 40 ns ;
--
when 6
=> correct :=
s_st_real1_1 = c_st_real1_1 and
s_st_real1_2 = c_st_real1_1 and
s_st_real1_3 = c_st_real1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_st_real1_1,
s_st_real1_2,
s_st_real1_3) <=
arr_st_real1 ' (
(c_st_real1_2,
c_st_real1_2,
c_st_real1_2) ) after 40 ns ;
--
when 7
=> correct :=
s_st_real1_1 = c_st_real1_2 and
s_st_real1_2 = c_st_real1_2 and
s_st_real1_3 = c_st_real1_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_st_real1_1,
s_st_real1_2,
s_st_real1_3) <=
arr_st_real1 ' (
(c_st_real1_1,
c_st_real1_1,
c_st_real1_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_st_real1_1 = c_st_real1_1 and
s_st_real1_2 = c_st_real1_1 and
s_st_real1_3 = c_st_real1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_real1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_st_real1_1'ACTIVE and
s_st_real1_2'ACTIVE and
s_st_real1_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P11 ;
--
PGEN_CHKP_11 :
process ( chk_st_real1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P11" ,
"Inertial transactions entirely completed",
chk_st_real1 = 8 ) ;
end if ;
end process PGEN_CHKP_11 ;
--
P12 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_rec1_1,
s_st_rec1_2,
s_st_rec1_3) <=
arr_st_rec1 ' (
(c_st_rec1_2,
c_st_rec1_2,
c_st_rec1_2) ) after 10 ns,
arr_st_rec1 ' (
(c_st_rec1_1,
c_st_rec1_1,
c_st_rec1_1) ) after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_1 = c_st_rec1_2 and
s_st_rec1_2 = c_st_rec1_2 and
s_st_rec1_3 = c_st_rec1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_1 = c_st_rec1_1 and
s_st_rec1_2 = c_st_rec1_1 and
s_st_rec1_3 = c_st_rec1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635.P12" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_rec1_1,
s_st_rec1_2,
s_st_rec1_3) <=
arr_st_rec1 ' (
(c_st_rec1_2,
c_st_rec1_2,
c_st_rec1_2) ) after 10 ns,
arr_st_rec1 ' (
(c_st_rec1_1,
c_st_rec1_1,
c_st_rec1_1) ) after 20 ns ,
arr_st_rec1 ' (
(c_st_rec1_2,
c_st_rec1_2,
c_st_rec1_2) ) after 30 ns,
arr_st_rec1 ' (
(c_st_rec1_1,
c_st_rec1_1,
c_st_rec1_1) ) after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_1 = c_st_rec1_2 and
s_st_rec1_2 = c_st_rec1_2 and
s_st_rec1_3 = c_st_rec1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_rec1_1,
s_st_rec1_2,
s_st_rec1_3) <=
arr_st_rec1 ' (
(c_st_rec1_1,
c_st_rec1_1,
c_st_rec1_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_1 = c_st_rec1_1 and
s_st_rec1_2 = c_st_rec1_1 and
s_st_rec1_3 = c_st_rec1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_rec1_1,
s_st_rec1_2,
s_st_rec1_3) <= transport
arr_st_rec1 ' (
(c_st_rec1_2,
c_st_rec1_2,
c_st_rec1_2) ) after 100 ns ;
--
when 5
=> correct :=
s_st_rec1_1 = c_st_rec1_2 and
s_st_rec1_2 = c_st_rec1_2 and
s_st_rec1_3 = c_st_rec1_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_rec1_1,
s_st_rec1_2,
s_st_rec1_3) <=
arr_st_rec1 ' (
(c_st_rec1_1,
c_st_rec1_1,
c_st_rec1_1) ) after 10 ns ,
arr_st_rec1 ' (
(c_st_rec1_2,
c_st_rec1_2,
c_st_rec1_2) ) after 20 ns ,
arr_st_rec1 ' (
(c_st_rec1_1,
c_st_rec1_1,
c_st_rec1_1) ) after 30 ns ,
arr_st_rec1 ' (
(c_st_rec1_2,
c_st_rec1_2,
c_st_rec1_2) ) after 40 ns ;
--
when 6
=> correct :=
s_st_rec1_1 = c_st_rec1_1 and
s_st_rec1_2 = c_st_rec1_1 and
s_st_rec1_3 = c_st_rec1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_st_rec1_1,
s_st_rec1_2,
s_st_rec1_3) <=
arr_st_rec1 ' (
(c_st_rec1_2,
c_st_rec1_2,
c_st_rec1_2) ) after 40 ns ;
--
when 7
=> correct :=
s_st_rec1_1 = c_st_rec1_2 and
s_st_rec1_2 = c_st_rec1_2 and
s_st_rec1_3 = c_st_rec1_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_st_rec1_1,
s_st_rec1_2,
s_st_rec1_3) <=
arr_st_rec1 ' (
(c_st_rec1_1,
c_st_rec1_1,
c_st_rec1_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_st_rec1_1 = c_st_rec1_1 and
s_st_rec1_2 = c_st_rec1_1 and
s_st_rec1_3 = c_st_rec1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_st_rec1_1'ACTIVE and
s_st_rec1_2'ACTIVE and
s_st_rec1_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P12 ;
--
PGEN_CHKP_12 :
process ( chk_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P12" ,
"Inertial transactions entirely completed",
chk_st_rec1 = 8 ) ;
end if ;
end process PGEN_CHKP_12 ;
--
P13 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_rec2_1,
s_st_rec2_2,
s_st_rec2_3) <=
arr_st_rec2 ' (
(c_st_rec2_2,
c_st_rec2_2,
c_st_rec2_2) ) after 10 ns,
arr_st_rec2 ' (
(c_st_rec2_1,
c_st_rec2_1,
c_st_rec2_1) ) after 20 ns ;
--
when 1
=> correct :=
s_st_rec2_1 = c_st_rec2_2 and
s_st_rec2_2 = c_st_rec2_2 and
s_st_rec2_3 = c_st_rec2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2_1 = c_st_rec2_1 and
s_st_rec2_2 = c_st_rec2_1 and
s_st_rec2_3 = c_st_rec2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635.P13" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_rec2_1,
s_st_rec2_2,
s_st_rec2_3) <=
arr_st_rec2 ' (
(c_st_rec2_2,
c_st_rec2_2,
c_st_rec2_2) ) after 10 ns,
arr_st_rec2 ' (
(c_st_rec2_1,
c_st_rec2_1,
c_st_rec2_1) ) after 20 ns ,
arr_st_rec2 ' (
(c_st_rec2_2,
c_st_rec2_2,
c_st_rec2_2) ) after 30 ns,
arr_st_rec2 ' (
(c_st_rec2_1,
c_st_rec2_1,
c_st_rec2_1) ) after 40 ns ;
--
when 3
=> correct :=
s_st_rec2_1 = c_st_rec2_2 and
s_st_rec2_2 = c_st_rec2_2 and
s_st_rec2_3 = c_st_rec2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_rec2_1,
s_st_rec2_2,
s_st_rec2_3) <=
arr_st_rec2 ' (
(c_st_rec2_1,
c_st_rec2_1,
c_st_rec2_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2_1 = c_st_rec2_1 and
s_st_rec2_2 = c_st_rec2_1 and
s_st_rec2_3 = c_st_rec2_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_rec2_1,
s_st_rec2_2,
s_st_rec2_3) <= transport
arr_st_rec2 ' (
(c_st_rec2_2,
c_st_rec2_2,
c_st_rec2_2) ) after 100 ns ;
--
when 5
=> correct :=
s_st_rec2_1 = c_st_rec2_2 and
s_st_rec2_2 = c_st_rec2_2 and
s_st_rec2_3 = c_st_rec2_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_rec2_1,
s_st_rec2_2,
s_st_rec2_3) <=
arr_st_rec2 ' (
(c_st_rec2_1,
c_st_rec2_1,
c_st_rec2_1) ) after 10 ns ,
arr_st_rec2 ' (
(c_st_rec2_2,
c_st_rec2_2,
c_st_rec2_2) ) after 20 ns ,
arr_st_rec2 ' (
(c_st_rec2_1,
c_st_rec2_1,
c_st_rec2_1) ) after 30 ns ,
arr_st_rec2 ' (
(c_st_rec2_2,
c_st_rec2_2,
c_st_rec2_2) ) after 40 ns ;
--
when 6
=> correct :=
s_st_rec2_1 = c_st_rec2_1 and
s_st_rec2_2 = c_st_rec2_1 and
s_st_rec2_3 = c_st_rec2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_st_rec2_1,
s_st_rec2_2,
s_st_rec2_3) <=
arr_st_rec2 ' (
(c_st_rec2_2,
c_st_rec2_2,
c_st_rec2_2) ) after 40 ns ;
--
when 7
=> correct :=
s_st_rec2_1 = c_st_rec2_2 and
s_st_rec2_2 = c_st_rec2_2 and
s_st_rec2_3 = c_st_rec2_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_st_rec2_1,
s_st_rec2_2,
s_st_rec2_3) <=
arr_st_rec2 ' (
(c_st_rec2_1,
c_st_rec2_1,
c_st_rec2_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_st_rec2_1 = c_st_rec2_1 and
s_st_rec2_2 = c_st_rec2_1 and
s_st_rec2_3 = c_st_rec2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_st_rec2_1'ACTIVE and
s_st_rec2_2'ACTIVE and
s_st_rec2_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P13 ;
--
PGEN_CHKP_13 :
process ( chk_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P13" ,
"Inertial transactions entirely completed",
chk_st_rec2 = 8 ) ;
end if ;
end process PGEN_CHKP_13 ;
--
P14 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_rec3_1,
s_st_rec3_2,
s_st_rec3_3) <=
arr_st_rec3 ' (
(c_st_rec3_2,
c_st_rec3_2,
c_st_rec3_2) ) after 10 ns,
arr_st_rec3 ' (
(c_st_rec3_1,
c_st_rec3_1,
c_st_rec3_1) ) after 20 ns ;
--
when 1
=> correct :=
s_st_rec3_1 = c_st_rec3_2 and
s_st_rec3_2 = c_st_rec3_2 and
s_st_rec3_3 = c_st_rec3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3_1 = c_st_rec3_1 and
s_st_rec3_2 = c_st_rec3_1 and
s_st_rec3_3 = c_st_rec3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635.P14" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_rec3_1,
s_st_rec3_2,
s_st_rec3_3) <=
arr_st_rec3 ' (
(c_st_rec3_2,
c_st_rec3_2,
c_st_rec3_2) ) after 10 ns,
arr_st_rec3 ' (
(c_st_rec3_1,
c_st_rec3_1,
c_st_rec3_1) ) after 20 ns ,
arr_st_rec3 ' (
(c_st_rec3_2,
c_st_rec3_2,
c_st_rec3_2) ) after 30 ns,
arr_st_rec3 ' (
(c_st_rec3_1,
c_st_rec3_1,
c_st_rec3_1) ) after 40 ns ;
--
when 3
=> correct :=
s_st_rec3_1 = c_st_rec3_2 and
s_st_rec3_2 = c_st_rec3_2 and
s_st_rec3_3 = c_st_rec3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_rec3_1,
s_st_rec3_2,
s_st_rec3_3) <=
arr_st_rec3 ' (
(c_st_rec3_1,
c_st_rec3_1,
c_st_rec3_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3_1 = c_st_rec3_1 and
s_st_rec3_2 = c_st_rec3_1 and
s_st_rec3_3 = c_st_rec3_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_rec3_1,
s_st_rec3_2,
s_st_rec3_3) <= transport
arr_st_rec3 ' (
(c_st_rec3_2,
c_st_rec3_2,
c_st_rec3_2) ) after 100 ns ;
--
when 5
=> correct :=
s_st_rec3_1 = c_st_rec3_2 and
s_st_rec3_2 = c_st_rec3_2 and
s_st_rec3_3 = c_st_rec3_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_rec3_1,
s_st_rec3_2,
s_st_rec3_3) <=
arr_st_rec3 ' (
(c_st_rec3_1,
c_st_rec3_1,
c_st_rec3_1) ) after 10 ns ,
arr_st_rec3 ' (
(c_st_rec3_2,
c_st_rec3_2,
c_st_rec3_2) ) after 20 ns ,
arr_st_rec3 ' (
(c_st_rec3_1,
c_st_rec3_1,
c_st_rec3_1) ) after 30 ns ,
arr_st_rec3 ' (
(c_st_rec3_2,
c_st_rec3_2,
c_st_rec3_2) ) after 40 ns ;
--
when 6
=> correct :=
s_st_rec3_1 = c_st_rec3_1 and
s_st_rec3_2 = c_st_rec3_1 and
s_st_rec3_3 = c_st_rec3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_st_rec3_1,
s_st_rec3_2,
s_st_rec3_3) <=
arr_st_rec3 ' (
(c_st_rec3_2,
c_st_rec3_2,
c_st_rec3_2) ) after 40 ns ;
--
when 7
=> correct :=
s_st_rec3_1 = c_st_rec3_2 and
s_st_rec3_2 = c_st_rec3_2 and
s_st_rec3_3 = c_st_rec3_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_st_rec3_1,
s_st_rec3_2,
s_st_rec3_3) <=
arr_st_rec3 ' (
(c_st_rec3_1,
c_st_rec3_1,
c_st_rec3_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_st_rec3_1 = c_st_rec3_1 and
s_st_rec3_2 = c_st_rec3_1 and
s_st_rec3_3 = c_st_rec3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_st_rec3_1'ACTIVE and
s_st_rec3_2'ACTIVE and
s_st_rec3_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P14 ;
--
PGEN_CHKP_14 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P14" ,
"Inertial transactions entirely completed",
chk_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_14 ;
--
P15 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_arr1_1,
s_st_arr1_2,
s_st_arr1_3) <=
arr_st_arr1 ' (
(c_st_arr1_2,
c_st_arr1_2,
c_st_arr1_2) ) after 10 ns,
arr_st_arr1 ' (
(c_st_arr1_1,
c_st_arr1_1,
c_st_arr1_1) ) after 20 ns ;
--
when 1
=> correct :=
s_st_arr1_1 = c_st_arr1_2 and
s_st_arr1_2 = c_st_arr1_2 and
s_st_arr1_3 = c_st_arr1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1_1 = c_st_arr1_1 and
s_st_arr1_2 = c_st_arr1_1 and
s_st_arr1_3 = c_st_arr1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635.P15" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_arr1_1,
s_st_arr1_2,
s_st_arr1_3) <=
arr_st_arr1 ' (
(c_st_arr1_2,
c_st_arr1_2,
c_st_arr1_2) ) after 10 ns,
arr_st_arr1 ' (
(c_st_arr1_1,
c_st_arr1_1,
c_st_arr1_1) ) after 20 ns ,
arr_st_arr1 ' (
(c_st_arr1_2,
c_st_arr1_2,
c_st_arr1_2) ) after 30 ns,
arr_st_arr1 ' (
(c_st_arr1_1,
c_st_arr1_1,
c_st_arr1_1) ) after 40 ns ;
--
when 3
=> correct :=
s_st_arr1_1 = c_st_arr1_2 and
s_st_arr1_2 = c_st_arr1_2 and
s_st_arr1_3 = c_st_arr1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_arr1_1,
s_st_arr1_2,
s_st_arr1_3) <=
arr_st_arr1 ' (
(c_st_arr1_1,
c_st_arr1_1,
c_st_arr1_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1_1 = c_st_arr1_1 and
s_st_arr1_2 = c_st_arr1_1 and
s_st_arr1_3 = c_st_arr1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_arr1_1,
s_st_arr1_2,
s_st_arr1_3) <= transport
arr_st_arr1 ' (
(c_st_arr1_2,
c_st_arr1_2,
c_st_arr1_2) ) after 100 ns ;
--
when 5
=> correct :=
s_st_arr1_1 = c_st_arr1_2 and
s_st_arr1_2 = c_st_arr1_2 and
s_st_arr1_3 = c_st_arr1_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_arr1_1,
s_st_arr1_2,
s_st_arr1_3) <=
arr_st_arr1 ' (
(c_st_arr1_1,
c_st_arr1_1,
c_st_arr1_1) ) after 10 ns ,
arr_st_arr1 ' (
(c_st_arr1_2,
c_st_arr1_2,
c_st_arr1_2) ) after 20 ns ,
arr_st_arr1 ' (
(c_st_arr1_1,
c_st_arr1_1,
c_st_arr1_1) ) after 30 ns ,
arr_st_arr1 ' (
(c_st_arr1_2,
c_st_arr1_2,
c_st_arr1_2) ) after 40 ns ;
--
when 6
=> correct :=
s_st_arr1_1 = c_st_arr1_1 and
s_st_arr1_2 = c_st_arr1_1 and
s_st_arr1_3 = c_st_arr1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_st_arr1_1,
s_st_arr1_2,
s_st_arr1_3) <=
arr_st_arr1 ' (
(c_st_arr1_2,
c_st_arr1_2,
c_st_arr1_2) ) after 40 ns ;
--
when 7
=> correct :=
s_st_arr1_1 = c_st_arr1_2 and
s_st_arr1_2 = c_st_arr1_2 and
s_st_arr1_3 = c_st_arr1_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_st_arr1_1,
s_st_arr1_2,
s_st_arr1_3) <=
arr_st_arr1 ' (
(c_st_arr1_1,
c_st_arr1_1,
c_st_arr1_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_st_arr1_1 = c_st_arr1_1 and
s_st_arr1_2 = c_st_arr1_1 and
s_st_arr1_3 = c_st_arr1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_st_arr1_1'ACTIVE and
s_st_arr1_2'ACTIVE and
s_st_arr1_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P15 ;
--
PGEN_CHKP_15 :
process ( chk_st_arr1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P15" ,
"Inertial transactions entirely completed",
chk_st_arr1 = 8 ) ;
end if ;
end process PGEN_CHKP_15 ;
--
P16 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_arr2_1,
s_st_arr2_2,
s_st_arr2_3) <=
arr_st_arr2 ' (
(c_st_arr2_2,
c_st_arr2_2,
c_st_arr2_2) ) after 10 ns,
arr_st_arr2 ' (
(c_st_arr2_1,
c_st_arr2_1,
c_st_arr2_1) ) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2_1 = c_st_arr2_2 and
s_st_arr2_2 = c_st_arr2_2 and
s_st_arr2_3 = c_st_arr2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2_1 = c_st_arr2_1 and
s_st_arr2_2 = c_st_arr2_1 and
s_st_arr2_3 = c_st_arr2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635.P16" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_arr2_1,
s_st_arr2_2,
s_st_arr2_3) <=
arr_st_arr2 ' (
(c_st_arr2_2,
c_st_arr2_2,
c_st_arr2_2) ) after 10 ns,
arr_st_arr2 ' (
(c_st_arr2_1,
c_st_arr2_1,
c_st_arr2_1) ) after 20 ns ,
arr_st_arr2 ' (
(c_st_arr2_2,
c_st_arr2_2,
c_st_arr2_2) ) after 30 ns,
arr_st_arr2 ' (
(c_st_arr2_1,
c_st_arr2_1,
c_st_arr2_1) ) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2_1 = c_st_arr2_2 and
s_st_arr2_2 = c_st_arr2_2 and
s_st_arr2_3 = c_st_arr2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_arr2_1,
s_st_arr2_2,
s_st_arr2_3) <=
arr_st_arr2 ' (
(c_st_arr2_1,
c_st_arr2_1,
c_st_arr2_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2_1 = c_st_arr2_1 and
s_st_arr2_2 = c_st_arr2_1 and
s_st_arr2_3 = c_st_arr2_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_arr2_1,
s_st_arr2_2,
s_st_arr2_3) <= transport
arr_st_arr2 ' (
(c_st_arr2_2,
c_st_arr2_2,
c_st_arr2_2) ) after 100 ns ;
--
when 5
=> correct :=
s_st_arr2_1 = c_st_arr2_2 and
s_st_arr2_2 = c_st_arr2_2 and
s_st_arr2_3 = c_st_arr2_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_arr2_1,
s_st_arr2_2,
s_st_arr2_3) <=
arr_st_arr2 ' (
(c_st_arr2_1,
c_st_arr2_1,
c_st_arr2_1) ) after 10 ns ,
arr_st_arr2 ' (
(c_st_arr2_2,
c_st_arr2_2,
c_st_arr2_2) ) after 20 ns ,
arr_st_arr2 ' (
(c_st_arr2_1,
c_st_arr2_1,
c_st_arr2_1) ) after 30 ns ,
arr_st_arr2 ' (
(c_st_arr2_2,
c_st_arr2_2,
c_st_arr2_2) ) after 40 ns ;
--
when 6
=> correct :=
s_st_arr2_1 = c_st_arr2_1 and
s_st_arr2_2 = c_st_arr2_1 and
s_st_arr2_3 = c_st_arr2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_st_arr2_1,
s_st_arr2_2,
s_st_arr2_3) <=
arr_st_arr2 ' (
(c_st_arr2_2,
c_st_arr2_2,
c_st_arr2_2) ) after 40 ns ;
--
when 7
=> correct :=
s_st_arr2_1 = c_st_arr2_2 and
s_st_arr2_2 = c_st_arr2_2 and
s_st_arr2_3 = c_st_arr2_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_st_arr2_1,
s_st_arr2_2,
s_st_arr2_3) <=
arr_st_arr2 ' (
(c_st_arr2_1,
c_st_arr2_1,
c_st_arr2_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_st_arr2_1 = c_st_arr2_1 and
s_st_arr2_2 = c_st_arr2_1 and
s_st_arr2_3 = c_st_arr2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_st_arr2_1'ACTIVE and
s_st_arr2_2'ACTIVE and
s_st_arr2_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P16 ;
--
PGEN_CHKP_16 :
process ( chk_st_arr2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P16" ,
"Inertial transactions entirely completed",
chk_st_arr2 = 8 ) ;
end if ;
end process PGEN_CHKP_16 ;
--
P17 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_arr3_1,
s_st_arr3_2,
s_st_arr3_3) <=
arr_st_arr3 ' (
(c_st_arr3_2,
c_st_arr3_2,
c_st_arr3_2) ) after 10 ns,
arr_st_arr3 ' (
(c_st_arr3_1,
c_st_arr3_1,
c_st_arr3_1) ) after 20 ns ;
--
when 1
=> correct :=
s_st_arr3_1 = c_st_arr3_2 and
s_st_arr3_2 = c_st_arr3_2 and
s_st_arr3_3 = c_st_arr3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr3_1 = c_st_arr3_1 and
s_st_arr3_2 = c_st_arr3_1 and
s_st_arr3_3 = c_st_arr3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635.P17" ,
"Multi inertial transactions occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_arr3_1,
s_st_arr3_2,
s_st_arr3_3) <=
arr_st_arr3 ' (
(c_st_arr3_2,
c_st_arr3_2,
c_st_arr3_2) ) after 10 ns,
arr_st_arr3 ' (
(c_st_arr3_1,
c_st_arr3_1,
c_st_arr3_1) ) after 20 ns ,
arr_st_arr3 ' (
(c_st_arr3_2,
c_st_arr3_2,
c_st_arr3_2) ) after 30 ns,
arr_st_arr3 ' (
(c_st_arr3_1,
c_st_arr3_1,
c_st_arr3_1) ) after 40 ns ;
--
when 3
=> correct :=
s_st_arr3_1 = c_st_arr3_2 and
s_st_arr3_2 = c_st_arr3_2 and
s_st_arr3_3 = c_st_arr3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_arr3_1,
s_st_arr3_2,
s_st_arr3_3) <=
arr_st_arr3 ' (
(c_st_arr3_1,
c_st_arr3_1,
c_st_arr3_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr3_1 = c_st_arr3_1 and
s_st_arr3_2 = c_st_arr3_1 and
s_st_arr3_3 = c_st_arr3_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_arr3_1,
s_st_arr3_2,
s_st_arr3_3) <= transport
arr_st_arr3 ' (
(c_st_arr3_2,
c_st_arr3_2,
c_st_arr3_2) ) after 100 ns ;
--
when 5
=> correct :=
s_st_arr3_1 = c_st_arr3_2 and
s_st_arr3_2 = c_st_arr3_2 and
s_st_arr3_3 = c_st_arr3_2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Old transactions were removed on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
(s_st_arr3_1,
s_st_arr3_2,
s_st_arr3_3) <=
arr_st_arr3 ' (
(c_st_arr3_1,
c_st_arr3_1,
c_st_arr3_1) ) after 10 ns ,
arr_st_arr3 ' (
(c_st_arr3_2,
c_st_arr3_2,
c_st_arr3_2) ) after 20 ns ,
arr_st_arr3 ' (
(c_st_arr3_1,
c_st_arr3_1,
c_st_arr3_1) ) after 30 ns ,
arr_st_arr3 ' (
(c_st_arr3_2,
c_st_arr3_2,
c_st_arr3_2) ) after 40 ns ;
--
when 6
=> correct :=
s_st_arr3_1 = c_st_arr3_1 and
s_st_arr3_2 = c_st_arr3_1 and
s_st_arr3_3 = c_st_arr3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"One inertial transaction occurred on signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
-- Last transaction above is marked
(s_st_arr3_1,
s_st_arr3_2,
s_st_arr3_3) <=
arr_st_arr3 ' (
(c_st_arr3_2,
c_st_arr3_2,
c_st_arr3_2) ) after 40 ns ;
--
when 7
=> correct :=
s_st_arr3_1 = c_st_arr3_2 and
s_st_arr3_2 = c_st_arr3_2 and
s_st_arr3_3 = c_st_arr3_2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
(s_st_arr3_1,
s_st_arr3_2,
s_st_arr3_3) <=
arr_st_arr3 ' (
(c_st_arr3_1,
c_st_arr3_1,
c_st_arr3_1) ) after 10 ns ;
--
when 8
=> correct := correct and
s_st_arr3_1 = c_st_arr3_1 and
s_st_arr3_2 = c_st_arr3_1 and
s_st_arr3_3 = c_st_arr3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00635" ,
"Inertial semantics check on a signal " &
"asg with an aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_st_arr3_1'ACTIVE and
s_st_arr3_2'ACTIVE and
s_st_arr3_3'ACTIVE and
(savtime /= Std.Standard.Now) ;
--
end process P17 ;
--
PGEN_CHKP_17 :
process ( chk_st_arr3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P17" ,
"Inertial transactions entirely completed",
chk_st_arr3 = 8 ) ;
end if ;
end process PGEN_CHKP_17 ;
--
--
end ARCH00635 ;
--
entity ENT00635_Test_Bench is
end ENT00635_Test_Bench ;
--
architecture ARCH00635_Test_Bench of ENT00635_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00635 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00635_Test_Bench ;
| gpl-3.0 | 717cc6d7407d028cb895e30be2040920 | 0.443387 | 3.581066 | false | false | false | false |
jairov4/accel-oil | solution_spartan6/syn/vhdl/nfa_accept_samples_generic_hw.vhd | 1 | 81,873 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_initials_buckets_req_din : OUT STD_LOGIC;
nfa_initials_buckets_req_full_n : IN STD_LOGIC;
nfa_initials_buckets_req_write : OUT STD_LOGIC;
nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_initials_buckets_rsp_read : OUT STD_LOGIC;
nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_req_din : OUT STD_LOGIC;
nfa_finals_buckets_req_full_n : IN STD_LOGIC;
nfa_finals_buckets_req_write : OUT STD_LOGIC;
nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_finals_buckets_rsp_read : OUT STD_LOGIC;
nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_req_din : OUT STD_LOGIC;
nfa_forward_buckets_req_full_n : IN STD_LOGIC;
nfa_forward_buckets_req_write : OUT STD_LOGIC;
nfa_forward_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_forward_buckets_rsp_read : OUT STD_LOGIC;
nfa_forward_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_symbols : IN STD_LOGIC_VECTOR (7 downto 0);
sample_buffer_req_din : OUT STD_LOGIC;
sample_buffer_req_full_n : IN STD_LOGIC;
sample_buffer_req_write : OUT STD_LOGIC;
sample_buffer_rsp_empty_n : IN STD_LOGIC;
sample_buffer_rsp_read : OUT STD_LOGIC;
sample_buffer_address : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_buffer_datain : IN STD_LOGIC_VECTOR (7 downto 0);
sample_buffer_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
sample_buffer_size : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_buffer_length : IN STD_LOGIC_VECTOR (31 downto 0);
sample_length : IN STD_LOGIC_VECTOR (15 downto 0);
indices_begin_req_din : OUT STD_LOGIC;
indices_begin_req_full_n : IN STD_LOGIC;
indices_begin_req_write : OUT STD_LOGIC;
indices_begin_rsp_empty_n : IN STD_LOGIC;
indices_begin_rsp_read : OUT STD_LOGIC;
indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0);
indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_samples_req_din : OUT STD_LOGIC;
indices_samples_req_full_n : IN STD_LOGIC;
indices_samples_req_write : OUT STD_LOGIC;
indices_samples_rsp_empty_n : IN STD_LOGIC;
indices_samples_rsp_read : OUT STD_LOGIC;
indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0);
indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0);
indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_req_din : OUT STD_LOGIC;
indices_stride_req_full_n : IN STD_LOGIC;
indices_stride_req_write : OUT STD_LOGIC;
indices_stride_rsp_empty_n : IN STD_LOGIC;
indices_stride_rsp_read : OUT STD_LOGIC;
indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0);
indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0);
i_size : IN STD_LOGIC_VECTOR (15 downto 0);
begin_index : IN STD_LOGIC_VECTOR (15 downto 0);
begin_sample : IN STD_LOGIC_VECTOR (15 downto 0);
end_index : IN STD_LOGIC_VECTOR (15 downto 0);
end_sample : IN STD_LOGIC_VECTOR (15 downto 0);
stop_on_first : IN STD_LOGIC_VECTOR (0 downto 0);
accept : IN STD_LOGIC_VECTOR (0 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of nfa_accept_samples_generic_hw is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"nfa_accept_samples_generic_hw,hls_ip_2013_4,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc6slx9ftg256-3,HLS_INPUT_CLOCK=1.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=3.000000,HLS_SYN_LAT=92264012,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=0,HLS_SYN_LUT=0}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (5 downto 0) := "000000";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (5 downto 0) := "000001";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (5 downto 0) := "000010";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (5 downto 0) := "000011";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (5 downto 0) := "000100";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (5 downto 0) := "000101";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (5 downto 0) := "000110";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (5 downto 0) := "000111";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (5 downto 0) := "001000";
constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (5 downto 0) := "001001";
constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (5 downto 0) := "001010";
constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (5 downto 0) := "001011";
constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (5 downto 0) := "001100";
constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (5 downto 0) := "001101";
constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (5 downto 0) := "001110";
constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (5 downto 0) := "001111";
constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (5 downto 0) := "010000";
constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (5 downto 0) := "010001";
constant ap_ST_st19_fsm_18 : STD_LOGIC_VECTOR (5 downto 0) := "010010";
constant ap_ST_st20_fsm_19 : STD_LOGIC_VECTOR (5 downto 0) := "010011";
constant ap_ST_st21_fsm_20 : STD_LOGIC_VECTOR (5 downto 0) := "010100";
constant ap_ST_st22_fsm_21 : STD_LOGIC_VECTOR (5 downto 0) := "010101";
constant ap_ST_st23_fsm_22 : STD_LOGIC_VECTOR (5 downto 0) := "010110";
constant ap_ST_st24_fsm_23 : STD_LOGIC_VECTOR (5 downto 0) := "010111";
constant ap_ST_st25_fsm_24 : STD_LOGIC_VECTOR (5 downto 0) := "011000";
constant ap_ST_st26_fsm_25 : STD_LOGIC_VECTOR (5 downto 0) := "011001";
constant ap_ST_st27_fsm_26 : STD_LOGIC_VECTOR (5 downto 0) := "011010";
constant ap_ST_st28_fsm_27 : STD_LOGIC_VECTOR (5 downto 0) := "011011";
constant ap_ST_st29_fsm_28 : STD_LOGIC_VECTOR (5 downto 0) := "011100";
constant ap_ST_st30_fsm_29 : STD_LOGIC_VECTOR (5 downto 0) := "011101";
constant ap_ST_st31_fsm_30 : STD_LOGIC_VECTOR (5 downto 0) := "011110";
constant ap_ST_st32_fsm_31 : STD_LOGIC_VECTOR (5 downto 0) := "011111";
constant ap_ST_st33_fsm_32 : STD_LOGIC_VECTOR (5 downto 0) := "100000";
constant ap_ST_st34_fsm_33 : STD_LOGIC_VECTOR (5 downto 0) := "100001";
constant ap_ST_st35_fsm_34 : STD_LOGIC_VECTOR (5 downto 0) := "100010";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ap_CS_fsm : STD_LOGIC_VECTOR (5 downto 0) := "000000";
signal stop_on_first_read_read_fu_102_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_fu_228_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_reg_313 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_10_fu_233_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_10_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_11_fu_238_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_11_reg_323 : STD_LOGIC_VECTOR (0 downto 0);
signal c_load_reg_327 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_192_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal offset_reg_333 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_ap_return : STD_LOGIC_VECTOR (0 downto 0);
signal r_reg_338 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_nfa_accept_sample_fu_176_ap_done : STD_LOGIC;
signal or_cond_fu_245_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond_reg_343 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_249_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal c_1_reg_347 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_ap_start : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_ap_idle : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_ap_ready : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_din : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_full_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_write : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_rsp_empty_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_rsp_read : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_din : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_full_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_write : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_rsp_empty_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_rsp_read : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_din : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_full_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_write : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_rsp_empty_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_rsp_read : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_symbols : STD_LOGIC_VECTOR (7 downto 0);
signal grp_nfa_accept_sample_fu_176_sample_req_din : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_sample_req_full_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_sample_req_write : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_sample_rsp_empty_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_sample_rsp_read : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_sample_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_sample_datain : STD_LOGIC_VECTOR (7 downto 0);
signal grp_nfa_accept_sample_fu_176_sample_dataout : STD_LOGIC_VECTOR (7 downto 0);
signal grp_nfa_accept_sample_fu_176_sample_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_empty : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_length_r : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_get_offset_fu_192_ap_start : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_ap_done : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_ap_idle : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_ap_ready : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_stride_req_din : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_stride_req_full_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_stride_req_write : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_stride_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_stride_rsp_read : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_stride_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_192_indices_stride_datain : STD_LOGIC_VECTOR (7 downto 0);
signal grp_sample_iterator_get_offset_fu_192_indices_stride_dataout : STD_LOGIC_VECTOR (7 downto 0);
signal grp_sample_iterator_get_offset_fu_192_indices_stride_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_192_indices_begin_req_din : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_begin_req_full_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_begin_req_write : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_begin_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_begin_rsp_read : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_begin_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_192_indices_begin_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_192_indices_begin_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_192_indices_begin_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_192_ap_ce : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_i_index : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_get_offset_fu_192_i_sample : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_get_offset_fu_192_indices_samples_req_din : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_samples_req_full_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_samples_req_write : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_samples_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_samples_rsp_read : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_samples_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_192_indices_samples_datain : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_get_offset_fu_192_indices_samples_dataout : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_get_offset_fu_192_indices_samples_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_192_sample_buffer_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_192_sample_length : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_209_ap_start : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_ap_done : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_ap_idle : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_ap_ready : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_samples_req_din : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_samples_req_full_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_samples_req_write : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_samples_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_samples_rsp_read : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_samples_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_209_indices_samples_datain : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_209_indices_samples_dataout : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_209_indices_samples_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_209_ap_ce : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_begin_req_din : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_begin_req_full_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_begin_req_write : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_begin_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_begin_rsp_read : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_begin_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_209_indices_begin_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_209_indices_begin_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_209_indices_begin_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_209_indices_stride_req_din : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_stride_req_full_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_stride_req_write : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_stride_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_stride_rsp_read : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_stride_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_209_indices_stride_datain : STD_LOGIC_VECTOR (7 downto 0);
signal grp_sample_iterator_next_fu_209_indices_stride_dataout : STD_LOGIC_VECTOR (7 downto 0);
signal grp_sample_iterator_next_fu_209_indices_stride_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_209_i_index : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_209_i_sample : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_209_ap_return_0 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_209_ap_return_1 : STD_LOGIC_VECTOR (15 downto 0);
signal i_index_reg_144 : STD_LOGIC_VECTOR (15 downto 0);
signal i_sample_reg_154 : STD_LOGIC_VECTOR (15 downto 0);
signal p_0_reg_164 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_ap_start_ap_start_reg : STD_LOGIC := '0';
signal grp_sample_iterator_get_offset_fu_192_ap_start_ap_start_reg : STD_LOGIC := '0';
signal ap_NS_fsm : STD_LOGIC_VECTOR (5 downto 0);
signal grp_sample_iterator_next_fu_209_ap_start_ap_start_reg : STD_LOGIC := '0';
signal c_fu_92 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_249_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_249_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_249_ce : STD_LOGIC;
component nfa_accept_sample IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_initials_buckets_req_din : OUT STD_LOGIC;
nfa_initials_buckets_req_full_n : IN STD_LOGIC;
nfa_initials_buckets_req_write : OUT STD_LOGIC;
nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_initials_buckets_rsp_read : OUT STD_LOGIC;
nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_req_din : OUT STD_LOGIC;
nfa_finals_buckets_req_full_n : IN STD_LOGIC;
nfa_finals_buckets_req_write : OUT STD_LOGIC;
nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_finals_buckets_rsp_read : OUT STD_LOGIC;
nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_req_din : OUT STD_LOGIC;
nfa_forward_buckets_req_full_n : IN STD_LOGIC;
nfa_forward_buckets_req_write : OUT STD_LOGIC;
nfa_forward_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_forward_buckets_rsp_read : OUT STD_LOGIC;
nfa_forward_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_symbols : IN STD_LOGIC_VECTOR (7 downto 0);
sample_req_din : OUT STD_LOGIC;
sample_req_full_n : IN STD_LOGIC;
sample_req_write : OUT STD_LOGIC;
sample_rsp_empty_n : IN STD_LOGIC;
sample_rsp_read : OUT STD_LOGIC;
sample_address : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_datain : IN STD_LOGIC_VECTOR (7 downto 0);
sample_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
sample_size : OUT STD_LOGIC_VECTOR (31 downto 0);
empty : IN STD_LOGIC_VECTOR (31 downto 0);
length_r : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (0 downto 0) );
end component;
component sample_iterator_get_offset IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
indices_stride_req_din : OUT STD_LOGIC;
indices_stride_req_full_n : IN STD_LOGIC;
indices_stride_req_write : OUT STD_LOGIC;
indices_stride_rsp_empty_n : IN STD_LOGIC;
indices_stride_rsp_read : OUT STD_LOGIC;
indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0);
indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_req_din : OUT STD_LOGIC;
indices_begin_req_full_n : IN STD_LOGIC;
indices_begin_req_write : OUT STD_LOGIC;
indices_begin_rsp_empty_n : IN STD_LOGIC;
indices_begin_rsp_read : OUT STD_LOGIC;
indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0);
indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
i_index : IN STD_LOGIC_VECTOR (15 downto 0);
i_sample : IN STD_LOGIC_VECTOR (15 downto 0);
indices_samples_req_din : OUT STD_LOGIC;
indices_samples_req_full_n : IN STD_LOGIC;
indices_samples_req_write : OUT STD_LOGIC;
indices_samples_rsp_empty_n : IN STD_LOGIC;
indices_samples_rsp_read : OUT STD_LOGIC;
indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0);
indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0);
indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_buffer_size : IN STD_LOGIC_VECTOR (31 downto 0);
sample_length : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component sample_iterator_next IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
indices_samples_req_din : OUT STD_LOGIC;
indices_samples_req_full_n : IN STD_LOGIC;
indices_samples_req_write : OUT STD_LOGIC;
indices_samples_rsp_empty_n : IN STD_LOGIC;
indices_samples_rsp_read : OUT STD_LOGIC;
indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0);
indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0);
indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
indices_begin_req_din : OUT STD_LOGIC;
indices_begin_req_full_n : IN STD_LOGIC;
indices_begin_req_write : OUT STD_LOGIC;
indices_begin_rsp_empty_n : IN STD_LOGIC;
indices_begin_rsp_read : OUT STD_LOGIC;
indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0);
indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_req_din : OUT STD_LOGIC;
indices_stride_req_full_n : IN STD_LOGIC;
indices_stride_req_write : OUT STD_LOGIC;
indices_stride_rsp_empty_n : IN STD_LOGIC;
indices_stride_rsp_read : OUT STD_LOGIC;
indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0);
indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0);
i_index : IN STD_LOGIC_VECTOR (15 downto 0);
i_sample : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (15 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (15 downto 0) );
end component;
component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
grp_nfa_accept_sample_fu_176 : component nfa_accept_sample
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_nfa_accept_sample_fu_176_ap_start,
ap_done => grp_nfa_accept_sample_fu_176_ap_done,
ap_idle => grp_nfa_accept_sample_fu_176_ap_idle,
ap_ready => grp_nfa_accept_sample_fu_176_ap_ready,
nfa_initials_buckets_req_din => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_din,
nfa_initials_buckets_req_full_n => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_full_n,
nfa_initials_buckets_req_write => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_write,
nfa_initials_buckets_rsp_empty_n => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_rsp_empty_n,
nfa_initials_buckets_rsp_read => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_rsp_read,
nfa_initials_buckets_address => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_address,
nfa_initials_buckets_datain => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_datain,
nfa_initials_buckets_dataout => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_dataout,
nfa_initials_buckets_size => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_size,
nfa_finals_buckets_req_din => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_din,
nfa_finals_buckets_req_full_n => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_full_n,
nfa_finals_buckets_req_write => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_write,
nfa_finals_buckets_rsp_empty_n => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_rsp_empty_n,
nfa_finals_buckets_rsp_read => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_rsp_read,
nfa_finals_buckets_address => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_address,
nfa_finals_buckets_datain => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_datain,
nfa_finals_buckets_dataout => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_dataout,
nfa_finals_buckets_size => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_size,
nfa_forward_buckets_req_din => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_din,
nfa_forward_buckets_req_full_n => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_full_n,
nfa_forward_buckets_req_write => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_write,
nfa_forward_buckets_rsp_empty_n => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_rsp_empty_n,
nfa_forward_buckets_rsp_read => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_rsp_read,
nfa_forward_buckets_address => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_address,
nfa_forward_buckets_datain => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_datain,
nfa_forward_buckets_dataout => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_dataout,
nfa_forward_buckets_size => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_size,
nfa_symbols => grp_nfa_accept_sample_fu_176_nfa_symbols,
sample_req_din => grp_nfa_accept_sample_fu_176_sample_req_din,
sample_req_full_n => grp_nfa_accept_sample_fu_176_sample_req_full_n,
sample_req_write => grp_nfa_accept_sample_fu_176_sample_req_write,
sample_rsp_empty_n => grp_nfa_accept_sample_fu_176_sample_rsp_empty_n,
sample_rsp_read => grp_nfa_accept_sample_fu_176_sample_rsp_read,
sample_address => grp_nfa_accept_sample_fu_176_sample_address,
sample_datain => grp_nfa_accept_sample_fu_176_sample_datain,
sample_dataout => grp_nfa_accept_sample_fu_176_sample_dataout,
sample_size => grp_nfa_accept_sample_fu_176_sample_size,
empty => grp_nfa_accept_sample_fu_176_empty,
length_r => grp_nfa_accept_sample_fu_176_length_r,
ap_return => grp_nfa_accept_sample_fu_176_ap_return);
grp_sample_iterator_get_offset_fu_192 : component sample_iterator_get_offset
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_sample_iterator_get_offset_fu_192_ap_start,
ap_done => grp_sample_iterator_get_offset_fu_192_ap_done,
ap_idle => grp_sample_iterator_get_offset_fu_192_ap_idle,
ap_ready => grp_sample_iterator_get_offset_fu_192_ap_ready,
indices_stride_req_din => grp_sample_iterator_get_offset_fu_192_indices_stride_req_din,
indices_stride_req_full_n => grp_sample_iterator_get_offset_fu_192_indices_stride_req_full_n,
indices_stride_req_write => grp_sample_iterator_get_offset_fu_192_indices_stride_req_write,
indices_stride_rsp_empty_n => grp_sample_iterator_get_offset_fu_192_indices_stride_rsp_empty_n,
indices_stride_rsp_read => grp_sample_iterator_get_offset_fu_192_indices_stride_rsp_read,
indices_stride_address => grp_sample_iterator_get_offset_fu_192_indices_stride_address,
indices_stride_datain => grp_sample_iterator_get_offset_fu_192_indices_stride_datain,
indices_stride_dataout => grp_sample_iterator_get_offset_fu_192_indices_stride_dataout,
indices_stride_size => grp_sample_iterator_get_offset_fu_192_indices_stride_size,
indices_begin_req_din => grp_sample_iterator_get_offset_fu_192_indices_begin_req_din,
indices_begin_req_full_n => grp_sample_iterator_get_offset_fu_192_indices_begin_req_full_n,
indices_begin_req_write => grp_sample_iterator_get_offset_fu_192_indices_begin_req_write,
indices_begin_rsp_empty_n => grp_sample_iterator_get_offset_fu_192_indices_begin_rsp_empty_n,
indices_begin_rsp_read => grp_sample_iterator_get_offset_fu_192_indices_begin_rsp_read,
indices_begin_address => grp_sample_iterator_get_offset_fu_192_indices_begin_address,
indices_begin_datain => grp_sample_iterator_get_offset_fu_192_indices_begin_datain,
indices_begin_dataout => grp_sample_iterator_get_offset_fu_192_indices_begin_dataout,
indices_begin_size => grp_sample_iterator_get_offset_fu_192_indices_begin_size,
ap_ce => grp_sample_iterator_get_offset_fu_192_ap_ce,
i_index => grp_sample_iterator_get_offset_fu_192_i_index,
i_sample => grp_sample_iterator_get_offset_fu_192_i_sample,
indices_samples_req_din => grp_sample_iterator_get_offset_fu_192_indices_samples_req_din,
indices_samples_req_full_n => grp_sample_iterator_get_offset_fu_192_indices_samples_req_full_n,
indices_samples_req_write => grp_sample_iterator_get_offset_fu_192_indices_samples_req_write,
indices_samples_rsp_empty_n => grp_sample_iterator_get_offset_fu_192_indices_samples_rsp_empty_n,
indices_samples_rsp_read => grp_sample_iterator_get_offset_fu_192_indices_samples_rsp_read,
indices_samples_address => grp_sample_iterator_get_offset_fu_192_indices_samples_address,
indices_samples_datain => grp_sample_iterator_get_offset_fu_192_indices_samples_datain,
indices_samples_dataout => grp_sample_iterator_get_offset_fu_192_indices_samples_dataout,
indices_samples_size => grp_sample_iterator_get_offset_fu_192_indices_samples_size,
sample_buffer_size => grp_sample_iterator_get_offset_fu_192_sample_buffer_size,
sample_length => grp_sample_iterator_get_offset_fu_192_sample_length,
ap_return => grp_sample_iterator_get_offset_fu_192_ap_return);
grp_sample_iterator_next_fu_209 : component sample_iterator_next
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_sample_iterator_next_fu_209_ap_start,
ap_done => grp_sample_iterator_next_fu_209_ap_done,
ap_idle => grp_sample_iterator_next_fu_209_ap_idle,
ap_ready => grp_sample_iterator_next_fu_209_ap_ready,
indices_samples_req_din => grp_sample_iterator_next_fu_209_indices_samples_req_din,
indices_samples_req_full_n => grp_sample_iterator_next_fu_209_indices_samples_req_full_n,
indices_samples_req_write => grp_sample_iterator_next_fu_209_indices_samples_req_write,
indices_samples_rsp_empty_n => grp_sample_iterator_next_fu_209_indices_samples_rsp_empty_n,
indices_samples_rsp_read => grp_sample_iterator_next_fu_209_indices_samples_rsp_read,
indices_samples_address => grp_sample_iterator_next_fu_209_indices_samples_address,
indices_samples_datain => grp_sample_iterator_next_fu_209_indices_samples_datain,
indices_samples_dataout => grp_sample_iterator_next_fu_209_indices_samples_dataout,
indices_samples_size => grp_sample_iterator_next_fu_209_indices_samples_size,
ap_ce => grp_sample_iterator_next_fu_209_ap_ce,
indices_begin_req_din => grp_sample_iterator_next_fu_209_indices_begin_req_din,
indices_begin_req_full_n => grp_sample_iterator_next_fu_209_indices_begin_req_full_n,
indices_begin_req_write => grp_sample_iterator_next_fu_209_indices_begin_req_write,
indices_begin_rsp_empty_n => grp_sample_iterator_next_fu_209_indices_begin_rsp_empty_n,
indices_begin_rsp_read => grp_sample_iterator_next_fu_209_indices_begin_rsp_read,
indices_begin_address => grp_sample_iterator_next_fu_209_indices_begin_address,
indices_begin_datain => grp_sample_iterator_next_fu_209_indices_begin_datain,
indices_begin_dataout => grp_sample_iterator_next_fu_209_indices_begin_dataout,
indices_begin_size => grp_sample_iterator_next_fu_209_indices_begin_size,
indices_stride_req_din => grp_sample_iterator_next_fu_209_indices_stride_req_din,
indices_stride_req_full_n => grp_sample_iterator_next_fu_209_indices_stride_req_full_n,
indices_stride_req_write => grp_sample_iterator_next_fu_209_indices_stride_req_write,
indices_stride_rsp_empty_n => grp_sample_iterator_next_fu_209_indices_stride_rsp_empty_n,
indices_stride_rsp_read => grp_sample_iterator_next_fu_209_indices_stride_rsp_read,
indices_stride_address => grp_sample_iterator_next_fu_209_indices_stride_address,
indices_stride_datain => grp_sample_iterator_next_fu_209_indices_stride_datain,
indices_stride_dataout => grp_sample_iterator_next_fu_209_indices_stride_dataout,
indices_stride_size => grp_sample_iterator_next_fu_209_indices_stride_size,
i_index => grp_sample_iterator_next_fu_209_i_index,
i_sample => grp_sample_iterator_next_fu_209_i_sample,
ap_return_0 => grp_sample_iterator_next_fu_209_ap_return_0,
ap_return_1 => grp_sample_iterator_next_fu_209_ap_return_1);
nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_U38 : component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8
generic map (
ID => 38,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_249_p0,
din1 => grp_fu_249_p1,
ce => grp_fu_249_ce,
dout => grp_fu_249_p2);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- grp_nfa_accept_sample_fu_176_ap_start_ap_start_reg assign process. --
grp_nfa_accept_sample_fu_176_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_nfa_accept_sample_fu_176_ap_start_ap_start_reg <= ap_const_logic_0;
else
if ((ap_ST_st17_fsm_16 = ap_CS_fsm)) then
grp_nfa_accept_sample_fu_176_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_nfa_accept_sample_fu_176_ap_ready)) then
grp_nfa_accept_sample_fu_176_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- grp_sample_iterator_get_offset_fu_192_ap_start_ap_start_reg assign process. --
grp_sample_iterator_get_offset_fu_192_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_sample_iterator_get_offset_fu_192_ap_start_ap_start_reg <= ap_const_logic_0;
else
if (((ap_ST_st3_fsm_2 = ap_CS_fsm) and (ap_ST_st4_fsm_3 = ap_NS_fsm) and (tmp_i_11_fu_238_p2 = ap_const_lv1_0))) then
grp_sample_iterator_get_offset_fu_192_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_sample_iterator_get_offset_fu_192_ap_ready)) then
grp_sample_iterator_get_offset_fu_192_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- grp_sample_iterator_next_fu_209_ap_start_ap_start_reg assign process. --
grp_sample_iterator_next_fu_209_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_sample_iterator_next_fu_209_ap_start_ap_start_reg <= ap_const_logic_0;
else
if (((ap_ST_st27_fsm_26 = ap_NS_fsm) and ((ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm)))) then
grp_sample_iterator_next_fu_209_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_sample_iterator_next_fu_209_ap_ready)) then
grp_sample_iterator_next_fu_209_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- c_fu_92 assign process. --
c_fu_92_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st27_fsm_26 = ap_CS_fsm) and (or_cond_reg_343 = ap_const_lv1_0))) then
c_fu_92 <= c_1_reg_347;
elsif (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then
c_fu_92 <= ap_const_lv32_0;
end if;
end if;
end process;
-- i_index_reg_144 assign process. --
i_index_reg_144_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st34_fsm_33 = ap_CS_fsm)) then
i_index_reg_144 <= grp_sample_iterator_next_fu_209_ap_return_0;
elsif (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then
i_index_reg_144 <= begin_index;
end if;
end if;
end process;
-- i_sample_reg_154 assign process. --
i_sample_reg_154_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st34_fsm_33 = ap_CS_fsm)) then
i_sample_reg_154 <= grp_sample_iterator_next_fu_209_ap_return_1;
elsif (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then
i_sample_reg_154 <= begin_sample;
end if;
end if;
end process;
-- p_0_reg_164 assign process. --
p_0_reg_164_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((stop_on_first_read_read_fu_102_p2 = ap_const_lv1_0)) and (or_cond_fu_245_p2 = ap_const_lv1_0))) then
p_0_reg_164 <= ap_const_lv32_1;
elsif (((ap_ST_st4_fsm_3 = ap_CS_fsm) and not((tmp_i_11_reg_323 = ap_const_lv1_0)))) then
p_0_reg_164 <= c_fu_92;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st26_fsm_25 = ap_CS_fsm)) then
c_1_reg_347 <= grp_fu_249_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st4_fsm_3 = ap_CS_fsm)) then
c_load_reg_327 <= c_fu_92;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st17_fsm_16 = ap_CS_fsm)) then
offset_reg_333 <= grp_sample_iterator_get_offset_fu_192_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st19_fsm_18 = ap_CS_fsm)) then
or_cond_reg_343 <= or_cond_fu_245_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st18_fsm_17 = ap_CS_fsm) and not((ap_const_logic_0 = grp_nfa_accept_sample_fu_176_ap_done)))) then
r_reg_338 <= grp_nfa_accept_sample_fu_176_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st2_fsm_1 = ap_CS_fsm)) then
tmp_i_10_reg_318 <= tmp_i_10_fu_233_p2;
tmp_i_reg_313 <= tmp_i_fu_228_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st3_fsm_2 = ap_CS_fsm)) then
tmp_i_11_reg_323 <= tmp_i_11_fu_238_p2;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , stop_on_first_read_read_fu_102_p2 , tmp_i_11_reg_323 , grp_nfa_accept_sample_fu_176_ap_done , or_cond_fu_245_p2)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
ap_NS_fsm <= ap_ST_st3_fsm_2;
when ap_ST_st3_fsm_2 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when ap_ST_st4_fsm_3 =>
if (not((tmp_i_11_reg_323 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_st35_fsm_34;
else
ap_NS_fsm <= ap_ST_st5_fsm_4;
end if;
when ap_ST_st5_fsm_4 =>
ap_NS_fsm <= ap_ST_st6_fsm_5;
when ap_ST_st6_fsm_5 =>
ap_NS_fsm <= ap_ST_st7_fsm_6;
when ap_ST_st7_fsm_6 =>
ap_NS_fsm <= ap_ST_st8_fsm_7;
when ap_ST_st8_fsm_7 =>
ap_NS_fsm <= ap_ST_st9_fsm_8;
when ap_ST_st9_fsm_8 =>
ap_NS_fsm <= ap_ST_st10_fsm_9;
when ap_ST_st10_fsm_9 =>
ap_NS_fsm <= ap_ST_st11_fsm_10;
when ap_ST_st11_fsm_10 =>
ap_NS_fsm <= ap_ST_st12_fsm_11;
when ap_ST_st12_fsm_11 =>
ap_NS_fsm <= ap_ST_st13_fsm_12;
when ap_ST_st13_fsm_12 =>
ap_NS_fsm <= ap_ST_st14_fsm_13;
when ap_ST_st14_fsm_13 =>
ap_NS_fsm <= ap_ST_st15_fsm_14;
when ap_ST_st15_fsm_14 =>
ap_NS_fsm <= ap_ST_st16_fsm_15;
when ap_ST_st16_fsm_15 =>
ap_NS_fsm <= ap_ST_st17_fsm_16;
when ap_ST_st17_fsm_16 =>
ap_NS_fsm <= ap_ST_st18_fsm_17;
when ap_ST_st18_fsm_17 =>
if (not((ap_const_logic_0 = grp_nfa_accept_sample_fu_176_ap_done))) then
ap_NS_fsm <= ap_ST_st19_fsm_18;
else
ap_NS_fsm <= ap_ST_st18_fsm_17;
end if;
when ap_ST_st19_fsm_18 =>
if ((not((stop_on_first_read_read_fu_102_p2 = ap_const_lv1_0)) and (or_cond_fu_245_p2 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_st35_fsm_34;
elsif (((stop_on_first_read_read_fu_102_p2 = ap_const_lv1_0) and (or_cond_fu_245_p2 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_st20_fsm_19;
else
ap_NS_fsm <= ap_ST_st27_fsm_26;
end if;
when ap_ST_st20_fsm_19 =>
ap_NS_fsm <= ap_ST_st21_fsm_20;
when ap_ST_st21_fsm_20 =>
ap_NS_fsm <= ap_ST_st22_fsm_21;
when ap_ST_st22_fsm_21 =>
ap_NS_fsm <= ap_ST_st23_fsm_22;
when ap_ST_st23_fsm_22 =>
ap_NS_fsm <= ap_ST_st24_fsm_23;
when ap_ST_st24_fsm_23 =>
ap_NS_fsm <= ap_ST_st25_fsm_24;
when ap_ST_st25_fsm_24 =>
ap_NS_fsm <= ap_ST_st26_fsm_25;
when ap_ST_st26_fsm_25 =>
ap_NS_fsm <= ap_ST_st27_fsm_26;
when ap_ST_st27_fsm_26 =>
ap_NS_fsm <= ap_ST_st28_fsm_27;
when ap_ST_st28_fsm_27 =>
ap_NS_fsm <= ap_ST_st29_fsm_28;
when ap_ST_st29_fsm_28 =>
ap_NS_fsm <= ap_ST_st30_fsm_29;
when ap_ST_st30_fsm_29 =>
ap_NS_fsm <= ap_ST_st31_fsm_30;
when ap_ST_st31_fsm_30 =>
ap_NS_fsm <= ap_ST_st32_fsm_31;
when ap_ST_st32_fsm_31 =>
ap_NS_fsm <= ap_ST_st33_fsm_32;
when ap_ST_st33_fsm_32 =>
ap_NS_fsm <= ap_ST_st34_fsm_33;
when ap_ST_st34_fsm_33 =>
ap_NS_fsm <= ap_ST_st2_fsm_1;
when ap_ST_st35_fsm_34 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "XXXXXX";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_CS_fsm)
begin
if ((ap_ST_st35_fsm_34 = ap_CS_fsm)) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_st1_fsm_0 = ap_CS_fsm))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_CS_fsm)
begin
if ((ap_ST_st35_fsm_34 = ap_CS_fsm)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_return <= p_0_reg_164;
grp_fu_249_ce <= ap_const_logic_1;
grp_fu_249_p0 <= c_load_reg_327;
grp_fu_249_p1 <= ap_const_lv32_1;
grp_nfa_accept_sample_fu_176_ap_start <= grp_nfa_accept_sample_fu_176_ap_start_ap_start_reg;
grp_nfa_accept_sample_fu_176_empty <= offset_reg_333;
grp_nfa_accept_sample_fu_176_length_r <= sample_length;
grp_nfa_accept_sample_fu_176_nfa_finals_buckets_datain <= nfa_finals_buckets_datain;
grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_full_n <= nfa_finals_buckets_req_full_n;
grp_nfa_accept_sample_fu_176_nfa_finals_buckets_rsp_empty_n <= nfa_finals_buckets_rsp_empty_n;
grp_nfa_accept_sample_fu_176_nfa_forward_buckets_datain <= nfa_forward_buckets_datain;
grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_full_n <= nfa_forward_buckets_req_full_n;
grp_nfa_accept_sample_fu_176_nfa_forward_buckets_rsp_empty_n <= nfa_forward_buckets_rsp_empty_n;
grp_nfa_accept_sample_fu_176_nfa_initials_buckets_datain <= nfa_initials_buckets_datain;
grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_full_n <= nfa_initials_buckets_req_full_n;
grp_nfa_accept_sample_fu_176_nfa_initials_buckets_rsp_empty_n <= nfa_initials_buckets_rsp_empty_n;
grp_nfa_accept_sample_fu_176_nfa_symbols <= nfa_symbols;
grp_nfa_accept_sample_fu_176_sample_datain <= sample_buffer_datain;
grp_nfa_accept_sample_fu_176_sample_req_full_n <= sample_buffer_req_full_n;
grp_nfa_accept_sample_fu_176_sample_rsp_empty_n <= sample_buffer_rsp_empty_n;
grp_sample_iterator_get_offset_fu_192_ap_ce <= ap_const_logic_1;
grp_sample_iterator_get_offset_fu_192_ap_start <= grp_sample_iterator_get_offset_fu_192_ap_start_ap_start_reg;
grp_sample_iterator_get_offset_fu_192_i_index <= i_index_reg_144;
grp_sample_iterator_get_offset_fu_192_i_sample <= i_sample_reg_154;
grp_sample_iterator_get_offset_fu_192_indices_begin_datain <= indices_begin_datain;
grp_sample_iterator_get_offset_fu_192_indices_begin_req_full_n <= indices_begin_req_full_n;
grp_sample_iterator_get_offset_fu_192_indices_begin_rsp_empty_n <= indices_begin_rsp_empty_n;
grp_sample_iterator_get_offset_fu_192_indices_samples_datain <= indices_samples_datain;
grp_sample_iterator_get_offset_fu_192_indices_samples_req_full_n <= indices_samples_req_full_n;
grp_sample_iterator_get_offset_fu_192_indices_samples_rsp_empty_n <= indices_samples_rsp_empty_n;
grp_sample_iterator_get_offset_fu_192_indices_stride_datain <= indices_stride_datain;
grp_sample_iterator_get_offset_fu_192_indices_stride_req_full_n <= indices_stride_req_full_n;
grp_sample_iterator_get_offset_fu_192_indices_stride_rsp_empty_n <= indices_stride_rsp_empty_n;
grp_sample_iterator_get_offset_fu_192_sample_buffer_size <= sample_buffer_length;
grp_sample_iterator_get_offset_fu_192_sample_length <= sample_length;
grp_sample_iterator_next_fu_209_ap_ce <= ap_const_logic_1;
grp_sample_iterator_next_fu_209_ap_start <= grp_sample_iterator_next_fu_209_ap_start_ap_start_reg;
grp_sample_iterator_next_fu_209_i_index <= i_index_reg_144;
grp_sample_iterator_next_fu_209_i_sample <= i_sample_reg_154;
grp_sample_iterator_next_fu_209_indices_begin_datain <= indices_begin_datain;
grp_sample_iterator_next_fu_209_indices_begin_req_full_n <= indices_begin_req_full_n;
grp_sample_iterator_next_fu_209_indices_begin_rsp_empty_n <= indices_begin_rsp_empty_n;
grp_sample_iterator_next_fu_209_indices_samples_datain <= indices_samples_datain;
grp_sample_iterator_next_fu_209_indices_samples_req_full_n <= indices_samples_req_full_n;
grp_sample_iterator_next_fu_209_indices_samples_rsp_empty_n <= indices_samples_rsp_empty_n;
grp_sample_iterator_next_fu_209_indices_stride_datain <= indices_stride_datain;
grp_sample_iterator_next_fu_209_indices_stride_req_full_n <= indices_stride_req_full_n;
grp_sample_iterator_next_fu_209_indices_stride_rsp_empty_n <= indices_stride_rsp_empty_n;
-- indices_begin_address assign process. --
indices_begin_address_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_begin_address, grp_sample_iterator_next_fu_209_indices_begin_address)
begin
if (((ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm))) then
indices_begin_address <= grp_sample_iterator_next_fu_209_indices_begin_address;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_begin_address <= grp_sample_iterator_get_offset_fu_192_indices_begin_address;
else
indices_begin_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_begin_dataout assign process. --
indices_begin_dataout_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_begin_dataout, grp_sample_iterator_next_fu_209_indices_begin_dataout)
begin
if (((ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm))) then
indices_begin_dataout <= grp_sample_iterator_next_fu_209_indices_begin_dataout;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_begin_dataout <= grp_sample_iterator_get_offset_fu_192_indices_begin_dataout;
else
indices_begin_dataout <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_begin_req_din assign process. --
indices_begin_req_din_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_begin_req_din, grp_sample_iterator_next_fu_209_indices_begin_req_din)
begin
if (((ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm))) then
indices_begin_req_din <= grp_sample_iterator_next_fu_209_indices_begin_req_din;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_begin_req_din <= grp_sample_iterator_get_offset_fu_192_indices_begin_req_din;
else
indices_begin_req_din <= 'X';
end if;
end process;
-- indices_begin_req_write assign process. --
indices_begin_req_write_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_begin_req_write, grp_sample_iterator_next_fu_209_indices_begin_req_write)
begin
if (((ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm))) then
indices_begin_req_write <= grp_sample_iterator_next_fu_209_indices_begin_req_write;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_begin_req_write <= grp_sample_iterator_get_offset_fu_192_indices_begin_req_write;
else
indices_begin_req_write <= 'X';
end if;
end process;
-- indices_begin_rsp_read assign process. --
indices_begin_rsp_read_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_begin_rsp_read, grp_sample_iterator_next_fu_209_indices_begin_rsp_read)
begin
if (((ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm))) then
indices_begin_rsp_read <= grp_sample_iterator_next_fu_209_indices_begin_rsp_read;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_begin_rsp_read <= grp_sample_iterator_get_offset_fu_192_indices_begin_rsp_read;
else
indices_begin_rsp_read <= 'X';
end if;
end process;
-- indices_begin_size assign process. --
indices_begin_size_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_begin_size, grp_sample_iterator_next_fu_209_indices_begin_size)
begin
if (((ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm))) then
indices_begin_size <= grp_sample_iterator_next_fu_209_indices_begin_size;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_begin_size <= grp_sample_iterator_get_offset_fu_192_indices_begin_size;
else
indices_begin_size <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_samples_address assign process. --
indices_samples_address_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_samples_address, grp_sample_iterator_next_fu_209_indices_samples_address)
begin
if (((ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm))) then
indices_samples_address <= grp_sample_iterator_next_fu_209_indices_samples_address;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_samples_address <= grp_sample_iterator_get_offset_fu_192_indices_samples_address;
else
indices_samples_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_samples_dataout assign process. --
indices_samples_dataout_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_samples_dataout, grp_sample_iterator_next_fu_209_indices_samples_dataout)
begin
if (((ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm))) then
indices_samples_dataout <= grp_sample_iterator_next_fu_209_indices_samples_dataout;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_samples_dataout <= grp_sample_iterator_get_offset_fu_192_indices_samples_dataout;
else
indices_samples_dataout <= "XXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_samples_req_din assign process. --
indices_samples_req_din_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_samples_req_din, grp_sample_iterator_next_fu_209_indices_samples_req_din)
begin
if (((ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm))) then
indices_samples_req_din <= grp_sample_iterator_next_fu_209_indices_samples_req_din;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_samples_req_din <= grp_sample_iterator_get_offset_fu_192_indices_samples_req_din;
else
indices_samples_req_din <= 'X';
end if;
end process;
-- indices_samples_req_write assign process. --
indices_samples_req_write_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_samples_req_write, grp_sample_iterator_next_fu_209_indices_samples_req_write)
begin
if (((ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm))) then
indices_samples_req_write <= grp_sample_iterator_next_fu_209_indices_samples_req_write;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_samples_req_write <= grp_sample_iterator_get_offset_fu_192_indices_samples_req_write;
else
indices_samples_req_write <= 'X';
end if;
end process;
-- indices_samples_rsp_read assign process. --
indices_samples_rsp_read_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_samples_rsp_read, grp_sample_iterator_next_fu_209_indices_samples_rsp_read)
begin
if (((ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm))) then
indices_samples_rsp_read <= grp_sample_iterator_next_fu_209_indices_samples_rsp_read;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_samples_rsp_read <= grp_sample_iterator_get_offset_fu_192_indices_samples_rsp_read;
else
indices_samples_rsp_read <= 'X';
end if;
end process;
-- indices_samples_size assign process. --
indices_samples_size_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_samples_size, grp_sample_iterator_next_fu_209_indices_samples_size)
begin
if (((ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm))) then
indices_samples_size <= grp_sample_iterator_next_fu_209_indices_samples_size;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_samples_size <= grp_sample_iterator_get_offset_fu_192_indices_samples_size;
else
indices_samples_size <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_stride_address assign process. --
indices_stride_address_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_stride_address, grp_sample_iterator_next_fu_209_indices_stride_address)
begin
if (((ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm))) then
indices_stride_address <= grp_sample_iterator_next_fu_209_indices_stride_address;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_stride_address <= grp_sample_iterator_get_offset_fu_192_indices_stride_address;
else
indices_stride_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_stride_dataout assign process. --
indices_stride_dataout_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_stride_dataout, grp_sample_iterator_next_fu_209_indices_stride_dataout)
begin
if (((ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm))) then
indices_stride_dataout <= grp_sample_iterator_next_fu_209_indices_stride_dataout;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_stride_dataout <= grp_sample_iterator_get_offset_fu_192_indices_stride_dataout;
else
indices_stride_dataout <= "XXXXXXXX";
end if;
end process;
-- indices_stride_req_din assign process. --
indices_stride_req_din_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_stride_req_din, grp_sample_iterator_next_fu_209_indices_stride_req_din)
begin
if (((ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm))) then
indices_stride_req_din <= grp_sample_iterator_next_fu_209_indices_stride_req_din;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_stride_req_din <= grp_sample_iterator_get_offset_fu_192_indices_stride_req_din;
else
indices_stride_req_din <= 'X';
end if;
end process;
-- indices_stride_req_write assign process. --
indices_stride_req_write_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_stride_req_write, grp_sample_iterator_next_fu_209_indices_stride_req_write)
begin
if (((ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm))) then
indices_stride_req_write <= grp_sample_iterator_next_fu_209_indices_stride_req_write;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_stride_req_write <= grp_sample_iterator_get_offset_fu_192_indices_stride_req_write;
else
indices_stride_req_write <= 'X';
end if;
end process;
-- indices_stride_rsp_read assign process. --
indices_stride_rsp_read_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_stride_rsp_read, grp_sample_iterator_next_fu_209_indices_stride_rsp_read)
begin
if (((ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm))) then
indices_stride_rsp_read <= grp_sample_iterator_next_fu_209_indices_stride_rsp_read;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_stride_rsp_read <= grp_sample_iterator_get_offset_fu_192_indices_stride_rsp_read;
else
indices_stride_rsp_read <= 'X';
end if;
end process;
-- indices_stride_size assign process. --
indices_stride_size_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_stride_size, grp_sample_iterator_next_fu_209_indices_stride_size)
begin
if (((ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm))) then
indices_stride_size <= grp_sample_iterator_next_fu_209_indices_stride_size;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_stride_size <= grp_sample_iterator_get_offset_fu_192_indices_stride_size;
else
indices_stride_size <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
nfa_finals_buckets_address <= grp_nfa_accept_sample_fu_176_nfa_finals_buckets_address;
nfa_finals_buckets_dataout <= grp_nfa_accept_sample_fu_176_nfa_finals_buckets_dataout;
nfa_finals_buckets_req_din <= grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_din;
nfa_finals_buckets_req_write <= grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_write;
nfa_finals_buckets_rsp_read <= grp_nfa_accept_sample_fu_176_nfa_finals_buckets_rsp_read;
nfa_finals_buckets_size <= grp_nfa_accept_sample_fu_176_nfa_finals_buckets_size;
nfa_forward_buckets_address <= grp_nfa_accept_sample_fu_176_nfa_forward_buckets_address;
nfa_forward_buckets_dataout <= grp_nfa_accept_sample_fu_176_nfa_forward_buckets_dataout;
nfa_forward_buckets_req_din <= grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_din;
nfa_forward_buckets_req_write <= grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_write;
nfa_forward_buckets_rsp_read <= grp_nfa_accept_sample_fu_176_nfa_forward_buckets_rsp_read;
nfa_forward_buckets_size <= grp_nfa_accept_sample_fu_176_nfa_forward_buckets_size;
nfa_initials_buckets_address <= grp_nfa_accept_sample_fu_176_nfa_initials_buckets_address;
nfa_initials_buckets_dataout <= grp_nfa_accept_sample_fu_176_nfa_initials_buckets_dataout;
nfa_initials_buckets_req_din <= grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_din;
nfa_initials_buckets_req_write <= grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_write;
nfa_initials_buckets_rsp_read <= grp_nfa_accept_sample_fu_176_nfa_initials_buckets_rsp_read;
nfa_initials_buckets_size <= grp_nfa_accept_sample_fu_176_nfa_initials_buckets_size;
or_cond_fu_245_p2 <= (r_reg_338 xor accept);
sample_buffer_address <= grp_nfa_accept_sample_fu_176_sample_address;
sample_buffer_dataout <= grp_nfa_accept_sample_fu_176_sample_dataout;
sample_buffer_req_din <= grp_nfa_accept_sample_fu_176_sample_req_din;
sample_buffer_req_write <= grp_nfa_accept_sample_fu_176_sample_req_write;
sample_buffer_rsp_read <= grp_nfa_accept_sample_fu_176_sample_rsp_read;
sample_buffer_size <= grp_nfa_accept_sample_fu_176_sample_size;
stop_on_first_read_read_fu_102_p2 <= stop_on_first;
tmp_i_10_fu_233_p2 <= "1" when (i_index_reg_144 = end_index) else "0";
tmp_i_11_fu_238_p2 <= (tmp_i_reg_313 and tmp_i_10_reg_318);
tmp_i_fu_228_p2 <= "1" when (i_sample_reg_154 = end_sample) else "0";
end behav;
| lgpl-3.0 | e9269e73047eed067038cfbec2f13b49 | 0.64451 | 2.699051 | false | false | false | false |
wsoltys/AtomFpga | src/AVR8/Memory/XPM16Kx16.vhd | 1 | 2,778 | --************************************************************************************************
-- 16Kx16(32 KB) PM RAM for AVR Core(Xilinx)
-- Version 0.2
-- Designed by Ruslan Lepetenok
-- Modified 30.07.2005
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
-- For Synplicity Synplify
--library virtexe;
--use virtexe.components.all;
-- Aldec
library unisim;
use unisim.vcomponents.all;
entity XPM16Kx16 is port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(13 downto 0);
din : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(15 downto 0);
weh : in std_logic;
wel : in std_logic
);
end XPM16Kx16;
architecture RTL of XPM16Kx16 is
type RAMBlDOut_Type is array(2**(address'length-9)-1 downto 0) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
signal WEBL : std_logic_vector(2**(address'length-9)-1 downto 0);
signal WEBH : std_logic_vector(2**(address'length-9)-1 downto 0);
signal gnd : std_logic;
begin
gnd <= '0';
WEBH_Dcd:for i in WEBL'range generate
WEBL(i) <= '1' when (wel='1' and address(address'high downto 9)=i) else '0';
end generate ;
WEBL_Dcd:for i in WEBH'range generate
WEBH(i) <= '1' when (weh='1' and address(address'high downto 9)=i) else '0';
end generate ;
RAM_Inst:for i in 0 to 2**(address'length-9)-1 generate
RAM_ByteLow:component RAMB4_S8 port map(
DO => RAMBlDOut(i)(7 downto 0),
ADDR => address(8 downto 0),
DI => din(7 downto 0),
EN => ce,
CLK => cp2,
WE => WEBL(i),
RST => gnd
);
RAM_ByteHigh:component RAMB4_S8 port map(
DO => RAMBlDOut(i)(15 downto 8),
ADDR => address(8 downto 0),
DI => din(15 downto 8),
EN => ce,
CLK => cp2,
WE => WEBH(i),
RST => gnd
);
end generate;
-- Output data mux
dout <= RAMBlDOut(CONV_INTEGER(address(address'high downto 9)));
end RTL;
| apache-2.0 | f83b3d6e54b550872cc0526019870d57 | 0.423686 | 4.061404 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00495.vhd | 1 | 7,759 | -- NEED RESULT: ARCH00495: Aggregates with others choice in signal assignment (locally static) passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00495
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.3.2.2 (6)
-- 7.3.2.2 (11)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00495(ARCH00495)
-- ENT00495_Test_Bench(ARCH00495_Test_Bench)
--
-- REVISION HISTORY:
--
-- 10-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00495 is
generic (
constant g_a11 : boolean := false ;
constant g_a12 : boolean := true ;
constant g_a21 : integer := 1 ;
constant g_a22 : integer := 5 ;
constant g_b11 : integer := 0 ;
constant g_b12 : integer := 0 ;
constant g_b21 : integer := -5 ;
constant g_b22 : integer := -3 ;
constant g_c1 : integer := 0 ;
constant g_c2 : integer := 4 ;
constant g_d1 : integer := 3 ;
constant g_d2 : integer := 5 ;
constant g_r1 : integer := 1
) ;
constant r1 : integer := 1 ;
constant a11 : boolean := false ;
constant a12 : boolean := true ;
constant a21 : integer := 1 ;
constant a22 : integer := 5 ;
constant b11 : integer := 0 ;
constant b12 : integer := 0 ;
constant b21 : integer := -5 ;
constant b22 : integer := -3 ;
constant c1 : integer := 0 ;
constant c2 : integer := 4 ;
constant d1 : integer := 3 ;
constant d2 : integer := 5 ;
--
type rec_arr is array ( integer range <> ) of boolean ;
type rec_1 is record
f1 : integer range - r1 to r1 ;
-- f2 : rec_arr (-r1 to r1) ;
f3, f4 : integer ;
end record ;
-- constant c_rec_arr : rec_arr (-r1 to r1) :=
-- (true, false, false) ;
-- constant c_rec_1_1 : rec_1 := (1, (true, false, false), 1, 0) ;
-- constant c_rec_1_2 : rec_1 := (0, (true, false, false), 0, 1) ;
constant c_rec_1_1 : rec_1 := (1, 1, 0) ;
constant c_rec_1_2 : rec_1 := (0, 0, 1) ;
--
type arr_1 is array ( boolean range <> , integer range <> )
of rec_1 ;
type time_matrix is array ( integer range <> , integer range <> )
of time ;
--
--
subtype arange1 is boolean range a11 to a12 ;
subtype arange2 is integer range a21 to a22 ;
subtype brange1 is integer range b11 to b12 ;
subtype brange2 is integer range b21 to b22 ;
subtype crange is integer range c1 to c2 ;
subtype drange is integer range d1 to d2 ;
--
subtype st_arr_1 is arr_1 ( arange1 , arange2 ) ;
subtype st_time_matrix is time_matrix ( brange1 , brange2 ) ;
subtype st_bit_vector is bit_vector ( crange ) ;
subtype st_string is string ( drange ) ;
--
--
end ENT00495 ;
--
architecture ARCH00495 of ENT00495 is
begin
B1 :
block
signal s_arr_1 : st_arr_1 ;
signal s_time_matrix : st_time_matrix ;
signal s_bit_vector : st_bit_vector ;
signal s_string : st_string ;
signal s_rec_1 : rec_1 ;
signal toggle : boolean := false ;
--
begin
process
variable v_arr_1 : st_arr_1 ;
variable v_time_matrix : st_time_matrix ;
variable v_bit_vector : st_bit_vector ;
variable v_string : st_string ;
variable v_rec_1 : rec_1 ;
variable bool : boolean := true ;
--
begin
s_arr_1 <=
( ( c_rec_1_1, others => c_rec_1_2 ),
others => (others => c_rec_1_1) ) ;
s_time_matrix <=
( st_time_matrix'right(1) =>
( st_time_matrix'right(2) => 10 ns, others => 5 fs),
others => (brange2'left => 10 ps, others => 15ms) ) ;
s_bit_vector <=
( 0 => '1', 2 => '1', others => '0' ) ;
s_string <=
( 3 => 'a', 4 => 'b', others => '0' ) ;
s_rec_1 <=
-- ( f2 => (r1 => true, others => false), f3 => 1, others => 0) ;
( f3 => 1, others => 0) ;
v_arr_1 :=
( ( c_rec_1_1, others => c_rec_1_2 ),
others => (others => c_rec_1_1) ) ;
v_time_matrix :=
( st_time_matrix'right(1) =>
( st_time_matrix'right(2) => 10 ns, others => 5 fs),
others => (brange2'left => 10 ps, others => 15ms) ) ;
v_bit_vector :=
( 0 => '1', 2 => '1', others => '0' ) ;
v_string :=
( 3 => 'a', 4 => 'b', others => '0' ) ;
v_rec_1 :=
-- ( f2 => (r1 => true, others => false), f3 => 1, others => 0) ;
( f3 => 1, others => 0) ;
bool := bool and v_arr_1(false, 1) = c_rec_1_1 ;
for i in 2 to 5 loop
bool := bool and v_arr_1(false, i) = c_rec_1_2 ;
end loop ;
for i in 1 to 5 loop
bool := bool and v_arr_1(true, i) = c_rec_1_1 ;
end loop ;
--
bool := bool and v_time_matrix(0, -3) = 10 ns ;
for i in integer'(-5) to -4 loop
bool := bool and v_time_matrix(0, i) = 5 fs ;
end loop ;
--
bool := bool and v_bit_vector = B"10100" ;
--
bool := bool and v_string = "ab0" ;
--
bool := bool and v_rec_1.f1 = 0 and v_rec_1.f4 = 0
and v_rec_1.f3 = 1 ;
-- bool := bool and v_rec_1.f2(1) = true
-- and v_rec_1.f2(0) = false and
-- v_rec_1.f2(-1) = false ;
--
--
test_report ( "ARCH00495" ,
"Aggregates with others choice in signal assignment"
& " (locally static)" ,
bool ) ;
wait ;
end process ;
process ( toggle )
variable bool : boolean := true ;
begin
if toggle then
bool := bool and s_arr_1(false, 1) = c_rec_1_1 ;
for i in 2 to 5 loop
bool := bool and s_arr_1(false, i) = c_rec_1_2 ;
end loop ;
for i in 1 to 5 loop
bool := bool and s_arr_1(true, i) = c_rec_1_1 ;
end loop ;
--
bool := bool and s_time_matrix(0, -3) = 10 ns ;
for i in integer'(-5) to -4 loop
bool := bool and s_time_matrix(0, i) = 5 fs ;
end loop ;
--
bool := bool and s_bit_vector = B"10100" ;
--
bool := bool and s_string = "ab0" ;
--
bool := bool and s_rec_1.f1 = 0 and s_rec_1.f4 = 0
and s_rec_1.f3 = 1 ;
-- bool := bool and s_rec_1.f2(1) = true
-- and s_rec_1.f2(0) = false and
-- s_rec_1.f2(-1) = false ;
--
--
test_report ( "ARCH00495" ,
"Aggregates with others choice in variable assignment"
& " (locally static)" ,
bool ) ;
end if ;
end process ;
end block B1 ;
end ARCH00495 ;
--
entity ENT00495_Test_Bench is
end ENT00495_Test_Bench ;
--
architecture ARCH00495_Test_Bench of ENT00495_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00495 ( ARCH00495 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00495_Test_Bench ;
| gpl-3.0 | fd51eb2fbd3786a49c8d0b12cac8be1b | 0.458822 | 3.328614 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00384.vhd | 1 | 104,055 | -- NEED RESULT: ARCH00384.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P2: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P3: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P4: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P5: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P6: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P7: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P8: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P9: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P10: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P11: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P12: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P13: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P14: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P15: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P16: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P17: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: P17: Inertial transactions completed entirely passed
-- NEED RESULT: P16: Inertial transactions completed entirely passed
-- NEED RESULT: P15: Inertial transactions completed entirely passed
-- NEED RESULT: P14: Inertial transactions completed entirely passed
-- NEED RESULT: P13: Inertial transactions completed entirely passed
-- NEED RESULT: P12: Inertial transactions completed entirely passed
-- NEED RESULT: P11: Inertial transactions completed entirely passed
-- NEED RESULT: P10: Inertial transactions completed entirely passed
-- NEED RESULT: P9: Inertial transactions completed entirely passed
-- NEED RESULT: P8: Inertial transactions completed entirely passed
-- NEED RESULT: P7: Inertial transactions completed entirely passed
-- NEED RESULT: P6: Inertial transactions completed entirely passed
-- NEED RESULT: P5: Inertial transactions completed entirely passed
-- NEED RESULT: P4: Inertial transactions completed entirely passed
-- NEED RESULT: P3: Inertial transactions completed entirely passed
-- NEED RESULT: P2: Inertial transactions completed entirely passed
-- NEED RESULT: P1: Inertial transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00384
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (3)
-- 9.5.1 (1)
-- 9.5.1 (2)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00384(ARCH00384)
-- ENT00384_Test_Bench(ARCH00384_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00384 is
port (
s_boolean : inout boolean
; s_bit : inout bit
; s_severity_level : inout severity_level
; s_character : inout character
; s_st_enum1 : inout st_enum1
; s_integer : inout integer
; s_st_int1 : inout st_int1
; s_time : inout time
; s_st_phys1 : inout st_phys1
; s_real : inout real
; s_st_real1 : inout st_real1
; s_st_rec1 : inout st_rec1
; s_st_rec2 : inout st_rec2
; s_st_rec3 : inout st_rec3
; s_st_arr1 : inout st_arr1
; s_st_arr2 : inout st_arr2
; s_st_arr3 : inout st_arr3
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_boolean : chk_sig_type := -1 ;
signal chk_bit : chk_sig_type := -1 ;
signal chk_severity_level : chk_sig_type := -1 ;
signal chk_character : chk_sig_type := -1 ;
signal chk_st_enum1 : chk_sig_type := -1 ;
signal chk_integer : chk_sig_type := -1 ;
signal chk_st_int1 : chk_sig_type := -1 ;
signal chk_time : chk_sig_type := -1 ;
signal chk_st_phys1 : chk_sig_type := -1 ;
signal chk_real : chk_sig_type := -1 ;
signal chk_st_real1 : chk_sig_type := -1 ;
signal chk_st_rec1 : chk_sig_type := -1 ;
signal chk_st_rec2 : chk_sig_type := -1 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
signal chk_st_arr1 : chk_sig_type := -1 ;
signal chk_st_arr2 : chk_sig_type := -1 ;
signal chk_st_arr3 : chk_sig_type := -1 ;
--
end ENT00384 ;
--
--
architecture ARCH00384 of ENT00384 is
subtype chk_time_type is Time ;
signal s_boolean_savt : chk_time_type := 0 ns ;
signal s_bit_savt : chk_time_type := 0 ns ;
signal s_severity_level_savt : chk_time_type := 0 ns ;
signal s_character_savt : chk_time_type := 0 ns ;
signal s_st_enum1_savt : chk_time_type := 0 ns ;
signal s_integer_savt : chk_time_type := 0 ns ;
signal s_st_int1_savt : chk_time_type := 0 ns ;
signal s_time_savt : chk_time_type := 0 ns ;
signal s_st_phys1_savt : chk_time_type := 0 ns ;
signal s_real_savt : chk_time_type := 0 ns ;
signal s_st_real1_savt : chk_time_type := 0 ns ;
signal s_st_rec1_savt : chk_time_type := 0 ns ;
signal s_st_rec2_savt : chk_time_type := 0 ns ;
signal s_st_rec3_savt : chk_time_type := 0 ns ;
signal s_st_arr1_savt : chk_time_type := 0 ns ;
signal s_st_arr2_savt : chk_time_type := 0 ns ;
signal s_st_arr3_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_boolean_cnt : chk_cnt_type := 0 ;
signal s_bit_cnt : chk_cnt_type := 0 ;
signal s_severity_level_cnt : chk_cnt_type := 0 ;
signal s_character_cnt : chk_cnt_type := 0 ;
signal s_st_enum1_cnt : chk_cnt_type := 0 ;
signal s_integer_cnt : chk_cnt_type := 0 ;
signal s_st_int1_cnt : chk_cnt_type := 0 ;
signal s_time_cnt : chk_cnt_type := 0 ;
signal s_st_phys1_cnt : chk_cnt_type := 0 ;
signal s_real_cnt : chk_cnt_type := 0 ;
signal s_st_real1_cnt : chk_cnt_type := 0 ;
signal s_st_rec1_cnt : chk_cnt_type := 0 ;
signal s_st_rec2_cnt : chk_cnt_type := 0 ;
signal s_st_rec3_cnt : chk_cnt_type := 0 ;
signal s_st_arr1_cnt : chk_cnt_type := 0 ;
signal s_st_arr2_cnt : chk_cnt_type := 0 ;
signal s_st_arr3_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 6 ;
signal boolean_select : select_type := 1 ;
signal bit_select : select_type := 1 ;
signal severity_level_select : select_type := 1 ;
signal character_select : select_type := 1 ;
signal st_enum1_select : select_type := 1 ;
signal integer_select : select_type := 1 ;
signal st_int1_select : select_type := 1 ;
signal time_select : select_type := 1 ;
signal st_phys1_select : select_type := 1 ;
signal real_select : select_type := 1 ;
signal st_real1_select : select_type := 1 ;
signal st_rec1_select : select_type := 1 ;
signal st_rec2_select : select_type := 1 ;
signal st_rec3_select : select_type := 1 ;
signal st_arr1_select : select_type := 1 ;
signal st_arr2_select : select_type := 1 ;
signal st_arr3_select : select_type := 1 ;
--
begin
CHG1 :
process
variable correct : boolean ;
begin
case s_boolean_cnt is
when 0
=> null ;
-- s_boolean <=
-- c_boolean_2 after 10 ns,
-- c_boolean_1 after 20 ns ;
--
when 1
=> correct :=
s_boolean =
c_boolean_2 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P1" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
boolean_select <= transport 2 ;
-- s_boolean <=
-- c_boolean_2 after 10 ns ,
-- c_boolean_1 after 20 ns ,
-- c_boolean_2 after 30 ns ,
-- c_boolean_1 after 40 ns ;
--
when 3
=> correct :=
s_boolean =
c_boolean_2 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
boolean_select <= transport 3 ;
-- s_boolean <=
-- c_boolean_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
boolean_select <= transport 4 ;
-- s_boolean <=
-- c_boolean_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
boolean_select <= transport 5 ;
-- s_boolean <=
-- c_boolean_2 after 10 ns ,
-- c_boolean_1 after 20 ns ,
-- c_boolean_2 after 30 ns ,
-- c_boolean_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_boolean =
c_boolean_2 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
boolean_select <= transport 6 ;
-- Last transaction above is marked
-- s_boolean <=
-- c_boolean_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_boolean_savt <= transport Std.Standard.Now ;
chk_boolean <= transport s_boolean_cnt
after (1 us - Std.Standard.Now) ;
s_boolean_cnt <= transport s_boolean_cnt + 1 ;
wait until (not s_boolean'Quiet) and
(s_boolean_savt /= Std.Standard.Now) ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_boolean )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions completed entirely",
chk_boolean = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
s_boolean <=
c_boolean_2 after 10 ns,
c_boolean_1 after 20 ns
when boolean_select = 1 else
--
c_boolean_2 after 10 ns ,
c_boolean_1 after 20 ns ,
c_boolean_2 after 30 ns ,
c_boolean_1 after 40 ns
when boolean_select = 2 else
--
c_boolean_1 after 5 ns
when boolean_select = 3 else
--
c_boolean_1 after 100 ns
when boolean_select = 4 else
--
c_boolean_2 after 10 ns ,
c_boolean_1 after 20 ns ,
c_boolean_2 after 30 ns ,
c_boolean_1 after 40 ns
when boolean_select = 5 else
--
-- Last transaction above is marked
c_boolean_1 after 40 ns ;
--
CHG2 :
process
variable correct : boolean ;
begin
case s_bit_cnt is
when 0
=> null ;
-- s_bit <=
-- c_bit_2 after 10 ns,
-- c_bit_1 after 20 ns ;
--
when 1
=> correct :=
s_bit =
c_bit_2 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P2" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
bit_select <= transport 2 ;
-- s_bit <=
-- c_bit_2 after 10 ns ,
-- c_bit_1 after 20 ns ,
-- c_bit_2 after 30 ns ,
-- c_bit_1 after 40 ns ;
--
when 3
=> correct :=
s_bit =
c_bit_2 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
bit_select <= transport 3 ;
-- s_bit <=
-- c_bit_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
bit_select <= transport 4 ;
-- s_bit <=
-- c_bit_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
bit_select <= transport 5 ;
-- s_bit <=
-- c_bit_2 after 10 ns ,
-- c_bit_1 after 20 ns ,
-- c_bit_2 after 30 ns ,
-- c_bit_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_bit =
c_bit_2 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
bit_select <= transport 6 ;
-- Last transaction above is marked
-- s_bit <=
-- c_bit_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_bit_savt <= transport Std.Standard.Now ;
chk_bit <= transport s_bit_cnt
after (1 us - Std.Standard.Now) ;
s_bit_cnt <= transport s_bit_cnt + 1 ;
wait until (not s_bit'Quiet) and
(s_bit_savt /= Std.Standard.Now) ;
--
end process CHG2 ;
--
PGEN_CHKP_2 :
process ( chk_bit )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions completed entirely",
chk_bit = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
s_bit <=
c_bit_2 after 10 ns,
c_bit_1 after 20 ns
when bit_select = 1 else
--
c_bit_2 after 10 ns ,
c_bit_1 after 20 ns ,
c_bit_2 after 30 ns ,
c_bit_1 after 40 ns
when bit_select = 2 else
--
c_bit_1 after 5 ns
when bit_select = 3 else
--
c_bit_1 after 100 ns
when bit_select = 4 else
--
c_bit_2 after 10 ns ,
c_bit_1 after 20 ns ,
c_bit_2 after 30 ns ,
c_bit_1 after 40 ns
when bit_select = 5 else
--
-- Last transaction above is marked
c_bit_1 after 40 ns ;
--
CHG3 :
process
variable correct : boolean ;
begin
case s_severity_level_cnt is
when 0
=> null ;
-- s_severity_level <=
-- c_severity_level_2 after 10 ns,
-- c_severity_level_1 after 20 ns ;
--
when 1
=> correct :=
s_severity_level =
c_severity_level_2 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P3" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
severity_level_select <= transport 2 ;
-- s_severity_level <=
-- c_severity_level_2 after 10 ns ,
-- c_severity_level_1 after 20 ns ,
-- c_severity_level_2 after 30 ns ,
-- c_severity_level_1 after 40 ns ;
--
when 3
=> correct :=
s_severity_level =
c_severity_level_2 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
severity_level_select <= transport 3 ;
-- s_severity_level <=
-- c_severity_level_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
severity_level_select <= transport 4 ;
-- s_severity_level <=
-- c_severity_level_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
severity_level_select <= transport 5 ;
-- s_severity_level <=
-- c_severity_level_2 after 10 ns ,
-- c_severity_level_1 after 20 ns ,
-- c_severity_level_2 after 30 ns ,
-- c_severity_level_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_severity_level =
c_severity_level_2 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
severity_level_select <= transport 6 ;
-- Last transaction above is marked
-- s_severity_level <=
-- c_severity_level_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_severity_level_savt <= transport Std.Standard.Now ;
chk_severity_level <= transport s_severity_level_cnt
after (1 us - Std.Standard.Now) ;
s_severity_level_cnt <= transport s_severity_level_cnt + 1 ;
wait until (not s_severity_level'Quiet) and
(s_severity_level_savt /= Std.Standard.Now) ;
--
end process CHG3 ;
--
PGEN_CHKP_3 :
process ( chk_severity_level )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions completed entirely",
chk_severity_level = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
s_severity_level <=
c_severity_level_2 after 10 ns,
c_severity_level_1 after 20 ns
when severity_level_select = 1 else
--
c_severity_level_2 after 10 ns ,
c_severity_level_1 after 20 ns ,
c_severity_level_2 after 30 ns ,
c_severity_level_1 after 40 ns
when severity_level_select = 2 else
--
c_severity_level_1 after 5 ns
when severity_level_select = 3 else
--
c_severity_level_1 after 100 ns
when severity_level_select = 4 else
--
c_severity_level_2 after 10 ns ,
c_severity_level_1 after 20 ns ,
c_severity_level_2 after 30 ns ,
c_severity_level_1 after 40 ns
when severity_level_select = 5 else
--
-- Last transaction above is marked
c_severity_level_1 after 40 ns ;
--
CHG4 :
process
variable correct : boolean ;
begin
case s_character_cnt is
when 0
=> null ;
-- s_character <=
-- c_character_2 after 10 ns,
-- c_character_1 after 20 ns ;
--
when 1
=> correct :=
s_character =
c_character_2 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P4" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
character_select <= transport 2 ;
-- s_character <=
-- c_character_2 after 10 ns ,
-- c_character_1 after 20 ns ,
-- c_character_2 after 30 ns ,
-- c_character_1 after 40 ns ;
--
when 3
=> correct :=
s_character =
c_character_2 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
character_select <= transport 3 ;
-- s_character <=
-- c_character_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
character_select <= transport 4 ;
-- s_character <=
-- c_character_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
character_select <= transport 5 ;
-- s_character <=
-- c_character_2 after 10 ns ,
-- c_character_1 after 20 ns ,
-- c_character_2 after 30 ns ,
-- c_character_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_character =
c_character_2 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
character_select <= transport 6 ;
-- Last transaction above is marked
-- s_character <=
-- c_character_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_character_savt <= transport Std.Standard.Now ;
chk_character <= transport s_character_cnt
after (1 us - Std.Standard.Now) ;
s_character_cnt <= transport s_character_cnt + 1 ;
wait until (not s_character'Quiet) and
(s_character_savt /= Std.Standard.Now) ;
--
end process CHG4 ;
--
PGEN_CHKP_4 :
process ( chk_character )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Inertial transactions completed entirely",
chk_character = 8 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
--
s_character <=
c_character_2 after 10 ns,
c_character_1 after 20 ns
when character_select = 1 else
--
c_character_2 after 10 ns ,
c_character_1 after 20 ns ,
c_character_2 after 30 ns ,
c_character_1 after 40 ns
when character_select = 2 else
--
c_character_1 after 5 ns
when character_select = 3 else
--
c_character_1 after 100 ns
when character_select = 4 else
--
c_character_2 after 10 ns ,
c_character_1 after 20 ns ,
c_character_2 after 30 ns ,
c_character_1 after 40 ns
when character_select = 5 else
--
-- Last transaction above is marked
c_character_1 after 40 ns ;
--
CHG5 :
process
variable correct : boolean ;
begin
case s_st_enum1_cnt is
when 0
=> null ;
-- s_st_enum1 <=
-- c_st_enum1_2 after 10 ns,
-- c_st_enum1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_enum1 =
c_st_enum1_2 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P5" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_enum1_select <= transport 2 ;
-- s_st_enum1 <=
-- c_st_enum1_2 after 10 ns ,
-- c_st_enum1_1 after 20 ns ,
-- c_st_enum1_2 after 30 ns ,
-- c_st_enum1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_enum1 =
c_st_enum1_2 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
st_enum1_select <= transport 3 ;
-- s_st_enum1 <=
-- c_st_enum1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_enum1_select <= transport 4 ;
-- s_st_enum1 <=
-- c_st_enum1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_enum1_select <= transport 5 ;
-- s_st_enum1 <=
-- c_st_enum1_2 after 10 ns ,
-- c_st_enum1_1 after 20 ns ,
-- c_st_enum1_2 after 30 ns ,
-- c_st_enum1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_2 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_enum1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_enum1 <=
-- c_st_enum1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_enum1_savt <= transport Std.Standard.Now ;
chk_st_enum1 <= transport s_st_enum1_cnt
after (1 us - Std.Standard.Now) ;
s_st_enum1_cnt <= transport s_st_enum1_cnt + 1 ;
wait until (not s_st_enum1'Quiet) and
(s_st_enum1_savt /= Std.Standard.Now) ;
--
end process CHG5 ;
--
PGEN_CHKP_5 :
process ( chk_st_enum1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Inertial transactions completed entirely",
chk_st_enum1 = 8 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
--
s_st_enum1 <=
c_st_enum1_2 after 10 ns,
c_st_enum1_1 after 20 ns
when st_enum1_select = 1 else
--
c_st_enum1_2 after 10 ns ,
c_st_enum1_1 after 20 ns ,
c_st_enum1_2 after 30 ns ,
c_st_enum1_1 after 40 ns
when st_enum1_select = 2 else
--
c_st_enum1_1 after 5 ns
when st_enum1_select = 3 else
--
c_st_enum1_1 after 100 ns
when st_enum1_select = 4 else
--
c_st_enum1_2 after 10 ns ,
c_st_enum1_1 after 20 ns ,
c_st_enum1_2 after 30 ns ,
c_st_enum1_1 after 40 ns
when st_enum1_select = 5 else
--
-- Last transaction above is marked
c_st_enum1_1 after 40 ns ;
--
CHG6 :
process
variable correct : boolean ;
begin
case s_integer_cnt is
when 0
=> null ;
-- s_integer <=
-- c_integer_2 after 10 ns,
-- c_integer_1 after 20 ns ;
--
when 1
=> correct :=
s_integer =
c_integer_2 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P6" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
integer_select <= transport 2 ;
-- s_integer <=
-- c_integer_2 after 10 ns ,
-- c_integer_1 after 20 ns ,
-- c_integer_2 after 30 ns ,
-- c_integer_1 after 40 ns ;
--
when 3
=> correct :=
s_integer =
c_integer_2 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
integer_select <= transport 3 ;
-- s_integer <=
-- c_integer_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
integer_select <= transport 4 ;
-- s_integer <=
-- c_integer_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
integer_select <= transport 5 ;
-- s_integer <=
-- c_integer_2 after 10 ns ,
-- c_integer_1 after 20 ns ,
-- c_integer_2 after 30 ns ,
-- c_integer_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_integer =
c_integer_2 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
integer_select <= transport 6 ;
-- Last transaction above is marked
-- s_integer <=
-- c_integer_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_integer_savt <= transport Std.Standard.Now ;
chk_integer <= transport s_integer_cnt
after (1 us - Std.Standard.Now) ;
s_integer_cnt <= transport s_integer_cnt + 1 ;
wait until (not s_integer'Quiet) and
(s_integer_savt /= Std.Standard.Now) ;
--
end process CHG6 ;
--
PGEN_CHKP_6 :
process ( chk_integer )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Inertial transactions completed entirely",
chk_integer = 8 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
--
s_integer <=
c_integer_2 after 10 ns,
c_integer_1 after 20 ns
when integer_select = 1 else
--
c_integer_2 after 10 ns ,
c_integer_1 after 20 ns ,
c_integer_2 after 30 ns ,
c_integer_1 after 40 ns
when integer_select = 2 else
--
c_integer_1 after 5 ns
when integer_select = 3 else
--
c_integer_1 after 100 ns
when integer_select = 4 else
--
c_integer_2 after 10 ns ,
c_integer_1 after 20 ns ,
c_integer_2 after 30 ns ,
c_integer_1 after 40 ns
when integer_select = 5 else
--
-- Last transaction above is marked
c_integer_1 after 40 ns ;
--
CHG7 :
process
variable correct : boolean ;
begin
case s_st_int1_cnt is
when 0
=> null ;
-- s_st_int1 <=
-- c_st_int1_2 after 10 ns,
-- c_st_int1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_int1 =
c_st_int1_2 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P7" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_int1_select <= transport 2 ;
-- s_st_int1 <=
-- c_st_int1_2 after 10 ns ,
-- c_st_int1_1 after 20 ns ,
-- c_st_int1_2 after 30 ns ,
-- c_st_int1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_int1 =
c_st_int1_2 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
st_int1_select <= transport 3 ;
-- s_st_int1 <=
-- c_st_int1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_int1_select <= transport 4 ;
-- s_st_int1 <=
-- c_st_int1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_int1_select <= transport 5 ;
-- s_st_int1 <=
-- c_st_int1_2 after 10 ns ,
-- c_st_int1_1 after 20 ns ,
-- c_st_int1_2 after 30 ns ,
-- c_st_int1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_int1 =
c_st_int1_2 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_int1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_int1 <=
-- c_st_int1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_int1_savt <= transport Std.Standard.Now ;
chk_st_int1 <= transport s_st_int1_cnt
after (1 us - Std.Standard.Now) ;
s_st_int1_cnt <= transport s_st_int1_cnt + 1 ;
wait until (not s_st_int1'Quiet) and
(s_st_int1_savt /= Std.Standard.Now) ;
--
end process CHG7 ;
--
PGEN_CHKP_7 :
process ( chk_st_int1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Inertial transactions completed entirely",
chk_st_int1 = 8 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
--
s_st_int1 <=
c_st_int1_2 after 10 ns,
c_st_int1_1 after 20 ns
when st_int1_select = 1 else
--
c_st_int1_2 after 10 ns ,
c_st_int1_1 after 20 ns ,
c_st_int1_2 after 30 ns ,
c_st_int1_1 after 40 ns
when st_int1_select = 2 else
--
c_st_int1_1 after 5 ns
when st_int1_select = 3 else
--
c_st_int1_1 after 100 ns
when st_int1_select = 4 else
--
c_st_int1_2 after 10 ns ,
c_st_int1_1 after 20 ns ,
c_st_int1_2 after 30 ns ,
c_st_int1_1 after 40 ns
when st_int1_select = 5 else
--
-- Last transaction above is marked
c_st_int1_1 after 40 ns ;
--
CHG8 :
process
variable correct : boolean ;
begin
case s_time_cnt is
when 0
=> null ;
-- s_time <=
-- c_time_2 after 10 ns,
-- c_time_1 after 20 ns ;
--
when 1
=> correct :=
s_time =
c_time_2 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P8" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
time_select <= transport 2 ;
-- s_time <=
-- c_time_2 after 10 ns ,
-- c_time_1 after 20 ns ,
-- c_time_2 after 30 ns ,
-- c_time_1 after 40 ns ;
--
when 3
=> correct :=
s_time =
c_time_2 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
time_select <= transport 3 ;
-- s_time <=
-- c_time_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
time_select <= transport 4 ;
-- s_time <=
-- c_time_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
time_select <= transport 5 ;
-- s_time <=
-- c_time_2 after 10 ns ,
-- c_time_1 after 20 ns ,
-- c_time_2 after 30 ns ,
-- c_time_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_time =
c_time_2 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
time_select <= transport 6 ;
-- Last transaction above is marked
-- s_time <=
-- c_time_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_time_savt <= transport Std.Standard.Now ;
chk_time <= transport s_time_cnt
after (1 us - Std.Standard.Now) ;
s_time_cnt <= transport s_time_cnt + 1 ;
wait until (not s_time'Quiet) and
(s_time_savt /= Std.Standard.Now) ;
--
end process CHG8 ;
--
PGEN_CHKP_8 :
process ( chk_time )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Inertial transactions completed entirely",
chk_time = 8 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
--
s_time <=
c_time_2 after 10 ns,
c_time_1 after 20 ns
when time_select = 1 else
--
c_time_2 after 10 ns ,
c_time_1 after 20 ns ,
c_time_2 after 30 ns ,
c_time_1 after 40 ns
when time_select = 2 else
--
c_time_1 after 5 ns
when time_select = 3 else
--
c_time_1 after 100 ns
when time_select = 4 else
--
c_time_2 after 10 ns ,
c_time_1 after 20 ns ,
c_time_2 after 30 ns ,
c_time_1 after 40 ns
when time_select = 5 else
--
-- Last transaction above is marked
c_time_1 after 40 ns ;
--
CHG9 :
process
variable correct : boolean ;
begin
case s_st_phys1_cnt is
when 0
=> null ;
-- s_st_phys1 <=
-- c_st_phys1_2 after 10 ns,
-- c_st_phys1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_phys1 =
c_st_phys1_2 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P9" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_phys1_select <= transport 2 ;
-- s_st_phys1 <=
-- c_st_phys1_2 after 10 ns ,
-- c_st_phys1_1 after 20 ns ,
-- c_st_phys1_2 after 30 ns ,
-- c_st_phys1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_phys1 =
c_st_phys1_2 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
st_phys1_select <= transport 3 ;
-- s_st_phys1 <=
-- c_st_phys1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_phys1_select <= transport 4 ;
-- s_st_phys1 <=
-- c_st_phys1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_phys1_select <= transport 5 ;
-- s_st_phys1 <=
-- c_st_phys1_2 after 10 ns ,
-- c_st_phys1_1 after 20 ns ,
-- c_st_phys1_2 after 30 ns ,
-- c_st_phys1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_2 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_phys1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_phys1 <=
-- c_st_phys1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_phys1_savt <= transport Std.Standard.Now ;
chk_st_phys1 <= transport s_st_phys1_cnt
after (1 us - Std.Standard.Now) ;
s_st_phys1_cnt <= transport s_st_phys1_cnt + 1 ;
wait until (not s_st_phys1'Quiet) and
(s_st_phys1_savt /= Std.Standard.Now) ;
--
end process CHG9 ;
--
PGEN_CHKP_9 :
process ( chk_st_phys1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Inertial transactions completed entirely",
chk_st_phys1 = 8 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
--
s_st_phys1 <=
c_st_phys1_2 after 10 ns,
c_st_phys1_1 after 20 ns
when st_phys1_select = 1 else
--
c_st_phys1_2 after 10 ns ,
c_st_phys1_1 after 20 ns ,
c_st_phys1_2 after 30 ns ,
c_st_phys1_1 after 40 ns
when st_phys1_select = 2 else
--
c_st_phys1_1 after 5 ns
when st_phys1_select = 3 else
--
c_st_phys1_1 after 100 ns
when st_phys1_select = 4 else
--
c_st_phys1_2 after 10 ns ,
c_st_phys1_1 after 20 ns ,
c_st_phys1_2 after 30 ns ,
c_st_phys1_1 after 40 ns
when st_phys1_select = 5 else
--
-- Last transaction above is marked
c_st_phys1_1 after 40 ns ;
--
CHG10 :
process
variable correct : boolean ;
begin
case s_real_cnt is
when 0
=> null ;
-- s_real <=
-- c_real_2 after 10 ns,
-- c_real_1 after 20 ns ;
--
when 1
=> correct :=
s_real =
c_real_2 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P10" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
real_select <= transport 2 ;
-- s_real <=
-- c_real_2 after 10 ns ,
-- c_real_1 after 20 ns ,
-- c_real_2 after 30 ns ,
-- c_real_1 after 40 ns ;
--
when 3
=> correct :=
s_real =
c_real_2 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
real_select <= transport 3 ;
-- s_real <=
-- c_real_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
real_select <= transport 4 ;
-- s_real <=
-- c_real_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
real_select <= transport 5 ;
-- s_real <=
-- c_real_2 after 10 ns ,
-- c_real_1 after 20 ns ,
-- c_real_2 after 30 ns ,
-- c_real_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_real =
c_real_2 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
real_select <= transport 6 ;
-- Last transaction above is marked
-- s_real <=
-- c_real_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_real_savt <= transport Std.Standard.Now ;
chk_real <= transport s_real_cnt
after (1 us - Std.Standard.Now) ;
s_real_cnt <= transport s_real_cnt + 1 ;
wait until (not s_real'Quiet) and
(s_real_savt /= Std.Standard.Now) ;
--
end process CHG10 ;
--
PGEN_CHKP_10 :
process ( chk_real )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Inertial transactions completed entirely",
chk_real = 8 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
--
s_real <=
c_real_2 after 10 ns,
c_real_1 after 20 ns
when real_select = 1 else
--
c_real_2 after 10 ns ,
c_real_1 after 20 ns ,
c_real_2 after 30 ns ,
c_real_1 after 40 ns
when real_select = 2 else
--
c_real_1 after 5 ns
when real_select = 3 else
--
c_real_1 after 100 ns
when real_select = 4 else
--
c_real_2 after 10 ns ,
c_real_1 after 20 ns ,
c_real_2 after 30 ns ,
c_real_1 after 40 ns
when real_select = 5 else
--
-- Last transaction above is marked
c_real_1 after 40 ns ;
--
CHG11 :
process
variable correct : boolean ;
begin
case s_st_real1_cnt is
when 0
=> null ;
-- s_st_real1 <=
-- c_st_real1_2 after 10 ns,
-- c_st_real1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_real1 =
c_st_real1_2 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P11" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_real1_select <= transport 2 ;
-- s_st_real1 <=
-- c_st_real1_2 after 10 ns ,
-- c_st_real1_1 after 20 ns ,
-- c_st_real1_2 after 30 ns ,
-- c_st_real1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_real1 =
c_st_real1_2 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
st_real1_select <= transport 3 ;
-- s_st_real1 <=
-- c_st_real1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_real1_select <= transport 4 ;
-- s_st_real1 <=
-- c_st_real1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_real1_select <= transport 5 ;
-- s_st_real1 <=
-- c_st_real1_2 after 10 ns ,
-- c_st_real1_1 after 20 ns ,
-- c_st_real1_2 after 30 ns ,
-- c_st_real1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_real1 =
c_st_real1_2 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_real1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_real1 <=
-- c_st_real1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_real1_savt <= transport Std.Standard.Now ;
chk_st_real1 <= transport s_st_real1_cnt
after (1 us - Std.Standard.Now) ;
s_st_real1_cnt <= transport s_st_real1_cnt + 1 ;
wait until (not s_st_real1'Quiet) and
(s_st_real1_savt /= Std.Standard.Now) ;
--
end process CHG11 ;
--
PGEN_CHKP_11 :
process ( chk_st_real1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P11" ,
"Inertial transactions completed entirely",
chk_st_real1 = 8 ) ;
end if ;
end process PGEN_CHKP_11 ;
--
--
s_st_real1 <=
c_st_real1_2 after 10 ns,
c_st_real1_1 after 20 ns
when st_real1_select = 1 else
--
c_st_real1_2 after 10 ns ,
c_st_real1_1 after 20 ns ,
c_st_real1_2 after 30 ns ,
c_st_real1_1 after 40 ns
when st_real1_select = 2 else
--
c_st_real1_1 after 5 ns
when st_real1_select = 3 else
--
c_st_real1_1 after 100 ns
when st_real1_select = 4 else
--
c_st_real1_2 after 10 ns ,
c_st_real1_1 after 20 ns ,
c_st_real1_2 after 30 ns ,
c_st_real1_1 after 40 ns
when st_real1_select = 5 else
--
-- Last transaction above is marked
c_st_real1_1 after 40 ns ;
--
CHG12 :
process
variable correct : boolean ;
begin
case s_st_rec1_cnt is
when 0
=> null ;
-- s_st_rec1 <=
-- c_st_rec1_2 after 10 ns,
-- c_st_rec1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1 =
c_st_rec1_2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P12" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec1_select <= transport 2 ;
-- s_st_rec1 <=
-- c_st_rec1_2 after 10 ns ,
-- c_st_rec1_1 after 20 ns ,
-- c_st_rec1_2 after 30 ns ,
-- c_st_rec1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1 =
c_st_rec1_2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
st_rec1_select <= transport 3 ;
-- s_st_rec1 <=
-- c_st_rec1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_select <= transport 4 ;
-- s_st_rec1 <=
-- c_st_rec1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec1_select <= transport 5 ;
-- s_st_rec1 <=
-- c_st_rec1_2 after 10 ns ,
-- c_st_rec1_1 after 20 ns ,
-- c_st_rec1_2 after 30 ns ,
-- c_st_rec1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec1 <=
-- c_st_rec1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec1_savt <= transport Std.Standard.Now ;
chk_st_rec1 <= transport s_st_rec1_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec1_cnt <= transport s_st_rec1_cnt + 1 ;
wait until (not s_st_rec1'Quiet) and
(s_st_rec1_savt /= Std.Standard.Now) ;
--
end process CHG12 ;
--
PGEN_CHKP_12 :
process ( chk_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P12" ,
"Inertial transactions completed entirely",
chk_st_rec1 = 8 ) ;
end if ;
end process PGEN_CHKP_12 ;
--
--
s_st_rec1 <=
c_st_rec1_2 after 10 ns,
c_st_rec1_1 after 20 ns
when st_rec1_select = 1 else
--
c_st_rec1_2 after 10 ns ,
c_st_rec1_1 after 20 ns ,
c_st_rec1_2 after 30 ns ,
c_st_rec1_1 after 40 ns
when st_rec1_select = 2 else
--
c_st_rec1_1 after 5 ns
when st_rec1_select = 3 else
--
c_st_rec1_1 after 100 ns
when st_rec1_select = 4 else
--
c_st_rec1_2 after 10 ns ,
c_st_rec1_1 after 20 ns ,
c_st_rec1_2 after 30 ns ,
c_st_rec1_1 after 40 ns
when st_rec1_select = 5 else
--
-- Last transaction above is marked
c_st_rec1_1 after 40 ns ;
--
CHG13 :
process
variable correct : boolean ;
begin
case s_st_rec2_cnt is
when 0
=> null ;
-- s_st_rec2 <=
-- c_st_rec2_2 after 10 ns,
-- c_st_rec2_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2 =
c_st_rec2_2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P13" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec2_select <= transport 2 ;
-- s_st_rec2 <=
-- c_st_rec2_2 after 10 ns ,
-- c_st_rec2_1 after 20 ns ,
-- c_st_rec2_2 after 30 ns ,
-- c_st_rec2_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2 =
c_st_rec2_2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
st_rec2_select <= transport 3 ;
-- s_st_rec2 <=
-- c_st_rec2_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec2_select <= transport 4 ;
-- s_st_rec2 <=
-- c_st_rec2_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec2_select <= transport 5 ;
-- s_st_rec2 <=
-- c_st_rec2_2 after 10 ns ,
-- c_st_rec2_1 after 20 ns ,
-- c_st_rec2_2 after 30 ns ,
-- c_st_rec2_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec2_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec2 <=
-- c_st_rec2_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec2_savt <= transport Std.Standard.Now ;
chk_st_rec2 <= transport s_st_rec2_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec2_cnt <= transport s_st_rec2_cnt + 1 ;
wait until (not s_st_rec2'Quiet) and
(s_st_rec2_savt /= Std.Standard.Now) ;
--
end process CHG13 ;
--
PGEN_CHKP_13 :
process ( chk_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P13" ,
"Inertial transactions completed entirely",
chk_st_rec2 = 8 ) ;
end if ;
end process PGEN_CHKP_13 ;
--
--
s_st_rec2 <=
c_st_rec2_2 after 10 ns,
c_st_rec2_1 after 20 ns
when st_rec2_select = 1 else
--
c_st_rec2_2 after 10 ns ,
c_st_rec2_1 after 20 ns ,
c_st_rec2_2 after 30 ns ,
c_st_rec2_1 after 40 ns
when st_rec2_select = 2 else
--
c_st_rec2_1 after 5 ns
when st_rec2_select = 3 else
--
c_st_rec2_1 after 100 ns
when st_rec2_select = 4 else
--
c_st_rec2_2 after 10 ns ,
c_st_rec2_1 after 20 ns ,
c_st_rec2_2 after 30 ns ,
c_st_rec2_1 after 40 ns
when st_rec2_select = 5 else
--
-- Last transaction above is marked
c_st_rec2_1 after 40 ns ;
--
CHG14 :
process
variable correct : boolean ;
begin
case s_st_rec3_cnt is
when 0
=> null ;
-- s_st_rec3 <=
-- c_st_rec3_2 after 10 ns,
-- c_st_rec3_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3 =
c_st_rec3_2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P14" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec3_select <= transport 2 ;
-- s_st_rec3 <=
-- c_st_rec3_2 after 10 ns ,
-- c_st_rec3_1 after 20 ns ,
-- c_st_rec3_2 after 30 ns ,
-- c_st_rec3_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3 =
c_st_rec3_2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
st_rec3_select <= transport 3 ;
-- s_st_rec3 <=
-- c_st_rec3_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 4 ;
-- s_st_rec3 <=
-- c_st_rec3_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 5 ;
-- s_st_rec3 <=
-- c_st_rec3_2 after 10 ns ,
-- c_st_rec3_1 after 20 ns ,
-- c_st_rec3_2 after 30 ns ,
-- c_st_rec3_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec3 <=
-- c_st_rec3_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec3_savt <= transport Std.Standard.Now ;
chk_st_rec3 <= transport s_st_rec3_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec3_cnt <= transport s_st_rec3_cnt + 1 ;
wait until (not s_st_rec3'Quiet) and
(s_st_rec3_savt /= Std.Standard.Now) ;
--
end process CHG14 ;
--
PGEN_CHKP_14 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P14" ,
"Inertial transactions completed entirely",
chk_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_14 ;
--
--
s_st_rec3 <=
c_st_rec3_2 after 10 ns,
c_st_rec3_1 after 20 ns
when st_rec3_select = 1 else
--
c_st_rec3_2 after 10 ns ,
c_st_rec3_1 after 20 ns ,
c_st_rec3_2 after 30 ns ,
c_st_rec3_1 after 40 ns
when st_rec3_select = 2 else
--
c_st_rec3_1 after 5 ns
when st_rec3_select = 3 else
--
c_st_rec3_1 after 100 ns
when st_rec3_select = 4 else
--
c_st_rec3_2 after 10 ns ,
c_st_rec3_1 after 20 ns ,
c_st_rec3_2 after 30 ns ,
c_st_rec3_1 after 40 ns
when st_rec3_select = 5 else
--
-- Last transaction above is marked
c_st_rec3_1 after 40 ns ;
--
CHG15 :
process
variable correct : boolean ;
begin
case s_st_arr1_cnt is
when 0
=> null ;
-- s_st_arr1 <=
-- c_st_arr1_2 after 10 ns,
-- c_st_arr1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr1 =
c_st_arr1_2 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P15" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr1_select <= transport 2 ;
-- s_st_arr1 <=
-- c_st_arr1_2 after 10 ns ,
-- c_st_arr1_1 after 20 ns ,
-- c_st_arr1_2 after 30 ns ,
-- c_st_arr1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr1 =
c_st_arr1_2 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
st_arr1_select <= transport 3 ;
-- s_st_arr1 <=
-- c_st_arr1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr1_select <= transport 4 ;
-- s_st_arr1 <=
-- c_st_arr1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_arr1_select <= transport 5 ;
-- s_st_arr1 <=
-- c_st_arr1_2 after 10 ns ,
-- c_st_arr1_1 after 20 ns ,
-- c_st_arr1_2 after 30 ns ,
-- c_st_arr1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_2 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_arr1 <=
-- c_st_arr1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_arr1_savt <= transport Std.Standard.Now ;
chk_st_arr1 <= transport s_st_arr1_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr1_cnt <= transport s_st_arr1_cnt + 1 ;
wait until (not s_st_arr1'Quiet) and
(s_st_arr1_savt /= Std.Standard.Now) ;
--
end process CHG15 ;
--
PGEN_CHKP_15 :
process ( chk_st_arr1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P15" ,
"Inertial transactions completed entirely",
chk_st_arr1 = 8 ) ;
end if ;
end process PGEN_CHKP_15 ;
--
--
s_st_arr1 <=
c_st_arr1_2 after 10 ns,
c_st_arr1_1 after 20 ns
when st_arr1_select = 1 else
--
c_st_arr1_2 after 10 ns ,
c_st_arr1_1 after 20 ns ,
c_st_arr1_2 after 30 ns ,
c_st_arr1_1 after 40 ns
when st_arr1_select = 2 else
--
c_st_arr1_1 after 5 ns
when st_arr1_select = 3 else
--
c_st_arr1_1 after 100 ns
when st_arr1_select = 4 else
--
c_st_arr1_2 after 10 ns ,
c_st_arr1_1 after 20 ns ,
c_st_arr1_2 after 30 ns ,
c_st_arr1_1 after 40 ns
when st_arr1_select = 5 else
--
-- Last transaction above is marked
c_st_arr1_1 after 40 ns ;
--
CHG16 :
process
variable correct : boolean ;
begin
case s_st_arr2_cnt is
when 0
=> null ;
-- s_st_arr2 <=
-- c_st_arr2_2 after 10 ns,
-- c_st_arr2_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr2 =
c_st_arr2_2 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P16" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr2_select <= transport 2 ;
-- s_st_arr2 <=
-- c_st_arr2_2 after 10 ns ,
-- c_st_arr2_1 after 20 ns ,
-- c_st_arr2_2 after 30 ns ,
-- c_st_arr2_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr2 =
c_st_arr2_2 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
st_arr2_select <= transport 3 ;
-- s_st_arr2 <=
-- c_st_arr2_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_select <= transport 4 ;
-- s_st_arr2 <=
-- c_st_arr2_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_arr2_select <= transport 5 ;
-- s_st_arr2 <=
-- c_st_arr2_2 after 10 ns ,
-- c_st_arr2_1 after 20 ns ,
-- c_st_arr2_2 after 30 ns ,
-- c_st_arr2_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_2 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_arr2 <=
-- c_st_arr2_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_arr2_savt <= transport Std.Standard.Now ;
chk_st_arr2 <= transport s_st_arr2_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr2_cnt <= transport s_st_arr2_cnt + 1 ;
wait until (not s_st_arr2'Quiet) and
(s_st_arr2_savt /= Std.Standard.Now) ;
--
end process CHG16 ;
--
PGEN_CHKP_16 :
process ( chk_st_arr2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P16" ,
"Inertial transactions completed entirely",
chk_st_arr2 = 8 ) ;
end if ;
end process PGEN_CHKP_16 ;
--
--
s_st_arr2 <=
c_st_arr2_2 after 10 ns,
c_st_arr2_1 after 20 ns
when st_arr2_select = 1 else
--
c_st_arr2_2 after 10 ns ,
c_st_arr2_1 after 20 ns ,
c_st_arr2_2 after 30 ns ,
c_st_arr2_1 after 40 ns
when st_arr2_select = 2 else
--
c_st_arr2_1 after 5 ns
when st_arr2_select = 3 else
--
c_st_arr2_1 after 100 ns
when st_arr2_select = 4 else
--
c_st_arr2_2 after 10 ns ,
c_st_arr2_1 after 20 ns ,
c_st_arr2_2 after 30 ns ,
c_st_arr2_1 after 40 ns
when st_arr2_select = 5 else
--
-- Last transaction above is marked
c_st_arr2_1 after 40 ns ;
--
CHG17 :
process
variable correct : boolean ;
begin
case s_st_arr3_cnt is
when 0
=> null ;
-- s_st_arr3 <=
-- c_st_arr3_2 after 10 ns,
-- c_st_arr3_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr3 =
c_st_arr3_2 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P17" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr3_select <= transport 2 ;
-- s_st_arr3 <=
-- c_st_arr3_2 after 10 ns ,
-- c_st_arr3_1 after 20 ns ,
-- c_st_arr3_2 after 30 ns ,
-- c_st_arr3_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr3 =
c_st_arr3_2 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
st_arr3_select <= transport 3 ;
-- s_st_arr3 <=
-- c_st_arr3_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr3_select <= transport 4 ;
-- s_st_arr3 <=
-- c_st_arr3_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_arr3_select <= transport 5 ;
-- s_st_arr3 <=
-- c_st_arr3_2 after 10 ns ,
-- c_st_arr3_1 after 20 ns ,
-- c_st_arr3_2 after 30 ns ,
-- c_st_arr3_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_2 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr3_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_arr3 <=
-- c_st_arr3_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_arr3_savt <= transport Std.Standard.Now ;
chk_st_arr3 <= transport s_st_arr3_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr3_cnt <= transport s_st_arr3_cnt + 1 ;
wait until (not s_st_arr3'Quiet) and
(s_st_arr3_savt /= Std.Standard.Now) ;
--
end process CHG17 ;
--
PGEN_CHKP_17 :
process ( chk_st_arr3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P17" ,
"Inertial transactions completed entirely",
chk_st_arr3 = 8 ) ;
end if ;
end process PGEN_CHKP_17 ;
--
--
s_st_arr3 <=
c_st_arr3_2 after 10 ns,
c_st_arr3_1 after 20 ns
when st_arr3_select = 1 else
--
c_st_arr3_2 after 10 ns ,
c_st_arr3_1 after 20 ns ,
c_st_arr3_2 after 30 ns ,
c_st_arr3_1 after 40 ns
when st_arr3_select = 2 else
--
c_st_arr3_1 after 5 ns
when st_arr3_select = 3 else
--
c_st_arr3_1 after 100 ns
when st_arr3_select = 4 else
--
c_st_arr3_2 after 10 ns ,
c_st_arr3_1 after 20 ns ,
c_st_arr3_2 after 30 ns ,
c_st_arr3_1 after 40 ns
when st_arr3_select = 5 else
--
-- Last transaction above is marked
c_st_arr3_1 after 40 ns ;
--
end ARCH00384 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00384_Test_Bench is
signal s_boolean : boolean
:= c_boolean_1 ;
signal s_bit : bit
:= c_bit_1 ;
signal s_severity_level : severity_level
:= c_severity_level_1 ;
signal s_character : character
:= c_character_1 ;
signal s_st_enum1 : st_enum1
:= c_st_enum1_1 ;
signal s_integer : integer
:= c_integer_1 ;
signal s_st_int1 : st_int1
:= c_st_int1_1 ;
signal s_time : time
:= c_time_1 ;
signal s_st_phys1 : st_phys1
:= c_st_phys1_1 ;
signal s_real : real
:= c_real_1 ;
signal s_st_real1 : st_real1
:= c_st_real1_1 ;
signal s_st_rec1 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
signal s_st_arr1 : st_arr1
:= c_st_arr1_1 ;
signal s_st_arr2 : st_arr2
:= c_st_arr2_1 ;
signal s_st_arr3 : st_arr3
:= c_st_arr3_1 ;
--
end ENT00384_Test_Bench ;
--
--
architecture ARCH00384_Test_Bench of ENT00384_Test_Bench is
begin
L1:
block
component UUT
port (
s_boolean : inout boolean
; s_bit : inout bit
; s_severity_level : inout severity_level
; s_character : inout character
; s_st_enum1 : inout st_enum1
; s_integer : inout integer
; s_st_int1 : inout st_int1
; s_time : inout time
; s_st_phys1 : inout st_phys1
; s_real : inout real
; s_st_real1 : inout st_real1
; s_st_rec1 : inout st_rec1
; s_st_rec2 : inout st_rec2
; s_st_rec3 : inout st_rec3
; s_st_arr1 : inout st_arr1
; s_st_arr2 : inout st_arr2
; s_st_arr3 : inout st_arr3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00384 ( ARCH00384 ) ;
begin
CIS1 : UUT
port map (
s_boolean
, s_bit
, s_severity_level
, s_character
, s_st_enum1
, s_integer
, s_st_int1
, s_time
, s_st_phys1
, s_real
, s_st_real1
, s_st_rec1
, s_st_rec2
, s_st_rec3
, s_st_arr1
, s_st_arr2
, s_st_arr3
)
;
end block L1 ;
end ARCH00384_Test_Bench ;
| gpl-3.0 | 442d59870ce1754075a1e2eb7f6f86dc | 0.470338 | 3.810561 | false | false | false | false |
jairov4/accel-oil | impl/impl_test_single/simulation/behavioral/nfa_accept_samples_generic_hw_top_v1_01_a/nfa_accept_samples_generic_hw_top/_primary.vhd | 1 | 16,324 | library verilog;
use verilog.vl_types.all;
entity nfa_accept_samples_generic_hw_top is
generic(
C_nfa_initials_buckets_REMOTE_DESTINATION_ADDRESS: integer := 0;
C_nfa_initials_buckets_AWIDTH: integer := 32;
C_nfa_initials_buckets_DWIDTH: integer := 64;
C_nfa_initials_buckets_NATIVE_DWIDTH: integer := 64;
C_nfa_finals_buckets_REMOTE_DESTINATION_ADDRESS: integer := 0;
C_nfa_finals_buckets_AWIDTH: integer := 32;
C_nfa_finals_buckets_DWIDTH: integer := 64;
C_nfa_finals_buckets_NATIVE_DWIDTH: integer := 64;
C_nfa_forward_buckets_REMOTE_DESTINATION_ADDRESS: integer := 0;
C_nfa_forward_buckets_AWIDTH: integer := 32;
C_nfa_forward_buckets_DWIDTH: integer := 64;
C_nfa_forward_buckets_NATIVE_DWIDTH: integer := 64;
C_sample_buffer_REMOTE_DESTINATION_ADDRESS: integer := 0;
C_sample_buffer_AWIDTH: integer := 32;
C_sample_buffer_DWIDTH: integer := 64;
C_sample_buffer_NATIVE_DWIDTH: integer := 64;
C_indices_REMOTE_DESTINATION_ADDRESS: integer := 0;
C_indices_AWIDTH: integer := 32;
C_indices_DWIDTH: integer := 64;
C_indices_NATIVE_DWIDTH: integer := 64;
C_SPLB_SLV0_BASEADDR: integer := 0;
C_SPLB_SLV0_HIGHADDR: integer := 15;
C_SPLB_SLV0_AWIDTH: integer := 32;
C_SPLB_SLV0_DWIDTH: integer := 32;
C_SPLB_SLV0_NUM_MASTERS: integer := 8;
C_SPLB_SLV0_MID_WIDTH: integer := 3;
C_SPLB_SLV0_NATIVE_DWIDTH: integer := 32;
C_SPLB_SLV0_P2P : integer := 0;
C_SPLB_SLV0_SUPPORT_BURSTS: integer := 0;
C_SPLB_SLV0_SMALLEST_MASTER: integer := 32;
C_SPLB_SLV0_INCLUDE_DPHASE_TIMER: integer := 0;
RESET_ACTIVE_LOW: integer := 1
);
port(
nfa_initials_buckets_MPLB_Clk: in vl_logic;
nfa_initials_buckets_MPLB_Rst: in vl_logic;
nfa_initials_buckets_M_request: out vl_logic;
nfa_initials_buckets_M_priority: out vl_logic_vector(1 downto 0);
nfa_initials_buckets_M_busLock: out vl_logic;
nfa_initials_buckets_M_RNW: out vl_logic;
nfa_initials_buckets_M_BE: out vl_logic_vector;
nfa_initials_buckets_M_MSize: out vl_logic_vector(1 downto 0);
nfa_initials_buckets_M_size: out vl_logic_vector(3 downto 0);
nfa_initials_buckets_M_type: out vl_logic_vector(2 downto 0);
nfa_initials_buckets_M_TAttribute: out vl_logic_vector(15 downto 0);
nfa_initials_buckets_M_lockErr: out vl_logic;
nfa_initials_buckets_M_abort: out vl_logic;
nfa_initials_buckets_M_UABus: out vl_logic_vector(31 downto 0);
nfa_initials_buckets_M_ABus: out vl_logic_vector(31 downto 0);
nfa_initials_buckets_M_wrDBus: out vl_logic_vector;
nfa_initials_buckets_M_wrBurst: out vl_logic;
nfa_initials_buckets_M_rdBurst: out vl_logic;
nfa_initials_buckets_PLB_MAddrAck: in vl_logic;
nfa_initials_buckets_PLB_MSSize: in vl_logic_vector(1 downto 0);
nfa_initials_buckets_PLB_MRearbitrate: in vl_logic;
nfa_initials_buckets_PLB_MTimeout: in vl_logic;
nfa_initials_buckets_PLB_MBusy: in vl_logic;
nfa_initials_buckets_PLB_MRdErr: in vl_logic;
nfa_initials_buckets_PLB_MWrErr: in vl_logic;
nfa_initials_buckets_PLB_MIRQ: in vl_logic;
nfa_initials_buckets_PLB_MRdDBus: in vl_logic_vector;
nfa_initials_buckets_PLB_MRdWdAddr: in vl_logic_vector(3 downto 0);
nfa_initials_buckets_PLB_MRdDAck: in vl_logic;
nfa_initials_buckets_PLB_MRdBTerm: in vl_logic;
nfa_initials_buckets_PLB_MWrDAck: in vl_logic;
nfa_initials_buckets_PLB_MWrBTerm: in vl_logic;
nfa_finals_buckets_MPLB_Clk: in vl_logic;
nfa_finals_buckets_MPLB_Rst: in vl_logic;
nfa_finals_buckets_M_request: out vl_logic;
nfa_finals_buckets_M_priority: out vl_logic_vector(1 downto 0);
nfa_finals_buckets_M_busLock: out vl_logic;
nfa_finals_buckets_M_RNW: out vl_logic;
nfa_finals_buckets_M_BE: out vl_logic_vector;
nfa_finals_buckets_M_MSize: out vl_logic_vector(1 downto 0);
nfa_finals_buckets_M_size: out vl_logic_vector(3 downto 0);
nfa_finals_buckets_M_type: out vl_logic_vector(2 downto 0);
nfa_finals_buckets_M_TAttribute: out vl_logic_vector(15 downto 0);
nfa_finals_buckets_M_lockErr: out vl_logic;
nfa_finals_buckets_M_abort: out vl_logic;
nfa_finals_buckets_M_UABus: out vl_logic_vector(31 downto 0);
nfa_finals_buckets_M_ABus: out vl_logic_vector(31 downto 0);
nfa_finals_buckets_M_wrDBus: out vl_logic_vector;
nfa_finals_buckets_M_wrBurst: out vl_logic;
nfa_finals_buckets_M_rdBurst: out vl_logic;
nfa_finals_buckets_PLB_MAddrAck: in vl_logic;
nfa_finals_buckets_PLB_MSSize: in vl_logic_vector(1 downto 0);
nfa_finals_buckets_PLB_MRearbitrate: in vl_logic;
nfa_finals_buckets_PLB_MTimeout: in vl_logic;
nfa_finals_buckets_PLB_MBusy: in vl_logic;
nfa_finals_buckets_PLB_MRdErr: in vl_logic;
nfa_finals_buckets_PLB_MWrErr: in vl_logic;
nfa_finals_buckets_PLB_MIRQ: in vl_logic;
nfa_finals_buckets_PLB_MRdDBus: in vl_logic_vector;
nfa_finals_buckets_PLB_MRdWdAddr: in vl_logic_vector(3 downto 0);
nfa_finals_buckets_PLB_MRdDAck: in vl_logic;
nfa_finals_buckets_PLB_MRdBTerm: in vl_logic;
nfa_finals_buckets_PLB_MWrDAck: in vl_logic;
nfa_finals_buckets_PLB_MWrBTerm: in vl_logic;
nfa_forward_buckets_MPLB_Clk: in vl_logic;
nfa_forward_buckets_MPLB_Rst: in vl_logic;
nfa_forward_buckets_M_request: out vl_logic;
nfa_forward_buckets_M_priority: out vl_logic_vector(1 downto 0);
nfa_forward_buckets_M_busLock: out vl_logic;
nfa_forward_buckets_M_RNW: out vl_logic;
nfa_forward_buckets_M_BE: out vl_logic_vector;
nfa_forward_buckets_M_MSize: out vl_logic_vector(1 downto 0);
nfa_forward_buckets_M_size: out vl_logic_vector(3 downto 0);
nfa_forward_buckets_M_type: out vl_logic_vector(2 downto 0);
nfa_forward_buckets_M_TAttribute: out vl_logic_vector(15 downto 0);
nfa_forward_buckets_M_lockErr: out vl_logic;
nfa_forward_buckets_M_abort: out vl_logic;
nfa_forward_buckets_M_UABus: out vl_logic_vector(31 downto 0);
nfa_forward_buckets_M_ABus: out vl_logic_vector(31 downto 0);
nfa_forward_buckets_M_wrDBus: out vl_logic_vector;
nfa_forward_buckets_M_wrBurst: out vl_logic;
nfa_forward_buckets_M_rdBurst: out vl_logic;
nfa_forward_buckets_PLB_MAddrAck: in vl_logic;
nfa_forward_buckets_PLB_MSSize: in vl_logic_vector(1 downto 0);
nfa_forward_buckets_PLB_MRearbitrate: in vl_logic;
nfa_forward_buckets_PLB_MTimeout: in vl_logic;
nfa_forward_buckets_PLB_MBusy: in vl_logic;
nfa_forward_buckets_PLB_MRdErr: in vl_logic;
nfa_forward_buckets_PLB_MWrErr: in vl_logic;
nfa_forward_buckets_PLB_MIRQ: in vl_logic;
nfa_forward_buckets_PLB_MRdDBus: in vl_logic_vector;
nfa_forward_buckets_PLB_MRdWdAddr: in vl_logic_vector(3 downto 0);
nfa_forward_buckets_PLB_MRdDAck: in vl_logic;
nfa_forward_buckets_PLB_MRdBTerm: in vl_logic;
nfa_forward_buckets_PLB_MWrDAck: in vl_logic;
nfa_forward_buckets_PLB_MWrBTerm: in vl_logic;
sample_buffer_MPLB_Clk: in vl_logic;
sample_buffer_MPLB_Rst: in vl_logic;
sample_buffer_M_request: out vl_logic;
sample_buffer_M_priority: out vl_logic_vector(1 downto 0);
sample_buffer_M_busLock: out vl_logic;
sample_buffer_M_RNW: out vl_logic;
sample_buffer_M_BE: out vl_logic_vector;
sample_buffer_M_MSize: out vl_logic_vector(1 downto 0);
sample_buffer_M_size: out vl_logic_vector(3 downto 0);
sample_buffer_M_type: out vl_logic_vector(2 downto 0);
sample_buffer_M_TAttribute: out vl_logic_vector(15 downto 0);
sample_buffer_M_lockErr: out vl_logic;
sample_buffer_M_abort: out vl_logic;
sample_buffer_M_UABus: out vl_logic_vector(31 downto 0);
sample_buffer_M_ABus: out vl_logic_vector(31 downto 0);
sample_buffer_M_wrDBus: out vl_logic_vector;
sample_buffer_M_wrBurst: out vl_logic;
sample_buffer_M_rdBurst: out vl_logic;
sample_buffer_PLB_MAddrAck: in vl_logic;
sample_buffer_PLB_MSSize: in vl_logic_vector(1 downto 0);
sample_buffer_PLB_MRearbitrate: in vl_logic;
sample_buffer_PLB_MTimeout: in vl_logic;
sample_buffer_PLB_MBusy: in vl_logic;
sample_buffer_PLB_MRdErr: in vl_logic;
sample_buffer_PLB_MWrErr: in vl_logic;
sample_buffer_PLB_MIRQ: in vl_logic;
sample_buffer_PLB_MRdDBus: in vl_logic_vector;
sample_buffer_PLB_MRdWdAddr: in vl_logic_vector(3 downto 0);
sample_buffer_PLB_MRdDAck: in vl_logic;
sample_buffer_PLB_MRdBTerm: in vl_logic;
sample_buffer_PLB_MWrDAck: in vl_logic;
sample_buffer_PLB_MWrBTerm: in vl_logic;
indices_MPLB_Clk: in vl_logic;
indices_MPLB_Rst: in vl_logic;
indices_M_request: out vl_logic;
indices_M_priority: out vl_logic_vector(1 downto 0);
indices_M_busLock: out vl_logic;
indices_M_RNW : out vl_logic;
indices_M_BE : out vl_logic_vector;
indices_M_MSize : out vl_logic_vector(1 downto 0);
indices_M_size : out vl_logic_vector(3 downto 0);
indices_M_type : out vl_logic_vector(2 downto 0);
indices_M_TAttribute: out vl_logic_vector(15 downto 0);
indices_M_lockErr: out vl_logic;
indices_M_abort : out vl_logic;
indices_M_UABus : out vl_logic_vector(31 downto 0);
indices_M_ABus : out vl_logic_vector(31 downto 0);
indices_M_wrDBus: out vl_logic_vector;
indices_M_wrBurst: out vl_logic;
indices_M_rdBurst: out vl_logic;
indices_PLB_MAddrAck: in vl_logic;
indices_PLB_MSSize: in vl_logic_vector(1 downto 0);
indices_PLB_MRearbitrate: in vl_logic;
indices_PLB_MTimeout: in vl_logic;
indices_PLB_MBusy: in vl_logic;
indices_PLB_MRdErr: in vl_logic;
indices_PLB_MWrErr: in vl_logic;
indices_PLB_MIRQ: in vl_logic;
indices_PLB_MRdDBus: in vl_logic_vector;
indices_PLB_MRdWdAddr: in vl_logic_vector(3 downto 0);
indices_PLB_MRdDAck: in vl_logic;
indices_PLB_MRdBTerm: in vl_logic;
indices_PLB_MWrDAck: in vl_logic;
indices_PLB_MWrBTerm: in vl_logic;
splb_slv0_SPLB_Clk: in vl_logic;
splb_slv0_SPLB_Rst: in vl_logic;
splb_slv0_PLB_ABus: in vl_logic_vector(31 downto 0);
splb_slv0_PLB_UABus: in vl_logic_vector(31 downto 0);
splb_slv0_PLB_PAValid: in vl_logic;
splb_slv0_PLB_SAValid: in vl_logic;
splb_slv0_PLB_rdPrim: in vl_logic;
splb_slv0_PLB_wrPrim: in vl_logic;
splb_slv0_PLB_masterID: in vl_logic_vector;
splb_slv0_PLB_abort: in vl_logic;
splb_slv0_PLB_busLock: in vl_logic;
splb_slv0_PLB_RNW: in vl_logic;
splb_slv0_PLB_BE: in vl_logic_vector;
splb_slv0_PLB_MSize: in vl_logic_vector(1 downto 0);
splb_slv0_PLB_size: in vl_logic_vector(3 downto 0);
splb_slv0_PLB_type: in vl_logic_vector(2 downto 0);
splb_slv0_PLB_lockErr: in vl_logic;
splb_slv0_PLB_wrDBus: in vl_logic_vector;
splb_slv0_PLB_wrBurst: in vl_logic;
splb_slv0_PLB_rdBurst: in vl_logic;
splb_slv0_PLB_wrPendReq: in vl_logic;
splb_slv0_PLB_rdPendReq: in vl_logic;
splb_slv0_PLB_wrPendPri: in vl_logic_vector(1 downto 0);
splb_slv0_PLB_rdPendPri: in vl_logic_vector(1 downto 0);
splb_slv0_PLB_reqPri: in vl_logic_vector(1 downto 0);
splb_slv0_PLB_TAttribute: in vl_logic_vector(15 downto 0);
splb_slv0_Sl_addrAck: out vl_logic;
splb_slv0_Sl_SSize: out vl_logic_vector(1 downto 0);
splb_slv0_Sl_wait: out vl_logic;
splb_slv0_Sl_rearbitrate: out vl_logic;
splb_slv0_Sl_wrDAck: out vl_logic;
splb_slv0_Sl_wrComp: out vl_logic;
splb_slv0_Sl_wrBTerm: out vl_logic;
splb_slv0_Sl_rdDBus: out vl_logic_vector;
splb_slv0_Sl_rdWdAddr: out vl_logic_vector(3 downto 0);
splb_slv0_Sl_rdDAck: out vl_logic;
splb_slv0_Sl_rdComp: out vl_logic;
splb_slv0_Sl_rdBTerm: out vl_logic;
splb_slv0_Sl_MBusy: out vl_logic_vector;
splb_slv0_Sl_MWrErr: out vl_logic_vector;
splb_slv0_Sl_MRdErr: out vl_logic_vector;
splb_slv0_Sl_MIRQ: out vl_logic_vector;
aresetn : in vl_logic;
aclk : in vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of C_nfa_initials_buckets_REMOTE_DESTINATION_ADDRESS : constant is 1;
attribute mti_svvh_generic_type of C_nfa_initials_buckets_AWIDTH : constant is 1;
attribute mti_svvh_generic_type of C_nfa_initials_buckets_DWIDTH : constant is 1;
attribute mti_svvh_generic_type of C_nfa_initials_buckets_NATIVE_DWIDTH : constant is 1;
attribute mti_svvh_generic_type of C_nfa_finals_buckets_REMOTE_DESTINATION_ADDRESS : constant is 1;
attribute mti_svvh_generic_type of C_nfa_finals_buckets_AWIDTH : constant is 1;
attribute mti_svvh_generic_type of C_nfa_finals_buckets_DWIDTH : constant is 1;
attribute mti_svvh_generic_type of C_nfa_finals_buckets_NATIVE_DWIDTH : constant is 1;
attribute mti_svvh_generic_type of C_nfa_forward_buckets_REMOTE_DESTINATION_ADDRESS : constant is 1;
attribute mti_svvh_generic_type of C_nfa_forward_buckets_AWIDTH : constant is 1;
attribute mti_svvh_generic_type of C_nfa_forward_buckets_DWIDTH : constant is 1;
attribute mti_svvh_generic_type of C_nfa_forward_buckets_NATIVE_DWIDTH : constant is 1;
attribute mti_svvh_generic_type of C_sample_buffer_REMOTE_DESTINATION_ADDRESS : constant is 1;
attribute mti_svvh_generic_type of C_sample_buffer_AWIDTH : constant is 1;
attribute mti_svvh_generic_type of C_sample_buffer_DWIDTH : constant is 1;
attribute mti_svvh_generic_type of C_sample_buffer_NATIVE_DWIDTH : constant is 1;
attribute mti_svvh_generic_type of C_indices_REMOTE_DESTINATION_ADDRESS : constant is 1;
attribute mti_svvh_generic_type of C_indices_AWIDTH : constant is 1;
attribute mti_svvh_generic_type of C_indices_DWIDTH : constant is 1;
attribute mti_svvh_generic_type of C_indices_NATIVE_DWIDTH : constant is 1;
attribute mti_svvh_generic_type of C_SPLB_SLV0_BASEADDR : constant is 1;
attribute mti_svvh_generic_type of C_SPLB_SLV0_HIGHADDR : constant is 1;
attribute mti_svvh_generic_type of C_SPLB_SLV0_AWIDTH : constant is 1;
attribute mti_svvh_generic_type of C_SPLB_SLV0_DWIDTH : constant is 1;
attribute mti_svvh_generic_type of C_SPLB_SLV0_NUM_MASTERS : constant is 1;
attribute mti_svvh_generic_type of C_SPLB_SLV0_MID_WIDTH : constant is 1;
attribute mti_svvh_generic_type of C_SPLB_SLV0_NATIVE_DWIDTH : constant is 1;
attribute mti_svvh_generic_type of C_SPLB_SLV0_P2P : constant is 1;
attribute mti_svvh_generic_type of C_SPLB_SLV0_SUPPORT_BURSTS : constant is 1;
attribute mti_svvh_generic_type of C_SPLB_SLV0_SMALLEST_MASTER : constant is 1;
attribute mti_svvh_generic_type of C_SPLB_SLV0_INCLUDE_DPHASE_TIMER : constant is 1;
attribute mti_svvh_generic_type of RESET_ACTIVE_LOW : constant is 1;
end nfa_accept_samples_generic_hw_top;
| lgpl-3.0 | a2c8eb88f3a081ba71c7a158cd2d7bd5 | 0.6352 | 3.082908 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00267.vhd | 1 | 6,783 | -- NEED RESULT: ARCH00267: Parameters are initialized passed
-- NEED RESULT: ARCH00267: Parameters are initialized passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00267
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 2.1.1.1 (1)
-- 2.1.1.1 (2)
-- 2.1.1.1 (3)
-- 2.1.1.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00267)
-- ENT00267_Test_Bench(ARCH00267_Test_Bench)
--
-- REVISION HISTORY:
--
-- 17-JUL-1987 - initial revision
-- 08-JUN-1988 - EL - remove tests of out params being initialize
--
-- NOTES:
--
-- ACCESS TYPES ARE FIXED AT NULL VALUES
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00267 of E00000 is
procedure proc1( int_in : in integer ;
real_in : in real ;
bool_in : in boolean ;
bit_in : in bit ;
chr_in : in character ;
lev_in : in severity_level ;
time_in : in time ;
phys_in : in t_phys1 ;
int_inout : inout integer ;
real_inout : inout real ;
bool_inout : inout boolean ;
bit_inout : inout bit ;
chr_inout : inout character ;
lev_inout : inout severity_level ;
time_inout : inout time ;
phys_inout : inout t_phys1 ;
acc_inout : inout a_bit_vector ;
int_out : out integer ;
real_out : out real ;
bool_out : out boolean ;
bit_out : out bit ;
chr_out : out character ;
lev_out : out severity_level ;
time_out : out time ;
phys_out : out t_phys1 ;
acc_out : out a_bit_vector ) is
begin
-- this tests 2.1.1.1 (1) and 2.1.1.1 (2)
test_report ( "ARCH00267" ,
"Parameters are initialized " ,
(int_in = 5) and
(real_in = 3.14159) and
(bool_in = true) and -- note: bool covers enum types
(bit_in = '0') and
(chr_in = 'Z') and
(lev_in = WARNING) and
(time_in = 10ms) and
(phys_in = phys1_2) and
(int_inout = integer'right) and
(real_inout = real'right) and
(bool_inout = boolean'right) and
(bit_inout = bit'right) and
(chr_inout = character'right) and
(lev_inout = severity_level'right) and
(time_inout = time'right) and
(phys_inout = t_phys1'right) and
(acc_inout = null)
) ;
-- now set the inout & out parms
int_inout := 20 ;
real_inout := 25.5 ;
bool_inout := false ;
bit_inout := '0' ;
chr_inout := 'Y' ;
lev_inout := NOTE ;
time_inout := 2 ps;
phys_inout := phys1_3 ;
acc_inout := null ;
int_out := 20 ;
real_out := 25.5 ;
bool_out := true ;
bit_out := '1' ;
chr_out := 'Y' ;
lev_out := NOTE ;
time_out := 2 ps;
phys_out := phys1_3 ;
acc_out := null ;
end proc1 ;
begin
P :
process
variable int_inout : integer := integer'right ;
variable real_inout : real := real'right ;
variable bool_inout : boolean := boolean'right ;
variable bit_inout : bit := bit'right ;
variable chr_inout : character := character'right ;
variable lev_inout : severity_level := severity_level'right ;
variable time_inout : time := time'right ;
variable phys_inout : t_phys1 := t_phys1'right ;
variable acc_inout : a_bit_vector := null ;
variable int_out : integer := integer'right ;
variable real_out : real := real'right ;
variable bool_out : boolean := boolean'right ;
variable bit_out : bit := bit'right ;
variable chr_out : character := character'right ;
variable lev_out : severity_level := severity_level'right ;
variable time_out : time := time'right ;
variable phys_out : t_phys1 := t_phys1'right ;
variable acc_out : a_bit_vector := null ;
begin
proc1( int_in => 5,
real_in => 3.14159,
bool_in => true,
bit_in => '0',
chr_in => 'Z',
lev_in => WARNING,
time_in => 10ms,
phys_in => phys1_2,
int_inout => int_inout,
real_inout => real_inout,
bool_inout => bool_inout,
bit_inout => bit_inout,
chr_inout => chr_inout,
lev_inout => lev_inout,
time_inout => time_inout,
phys_inout => phys_inout,
acc_inout => acc_inout,
int_out => int_out,
real_out => real_out,
bool_out => bool_out,
bit_out => bit_out,
chr_out => chr_out,
lev_out => lev_out,
time_out => time_out,
phys_out => phys_out,
acc_out => acc_out
) ;
-- this tests 2.1.1.1 (3)
test_report ( "ARCH00267" ,
"Parameters are initialized " ,
(int_inout = 20) and
(real_inout = 25.5) and
(bool_inout = false) and
(bit_inout = '0') and
(chr_inout = 'Y') and
(lev_inout = NOTE) and
(time_inout = 2 ps) and
(phys_inout = phys1_3) and
(acc_inout = null) and
(int_out = 20) and
(real_out = 25.5) and
(bool_out = true) and
(bit_out = '1') and
(chr_out = 'Y') and
(lev_out = NOTE) and
(time_out = 2 ps) and
(phys_out = phys1_3) and
(acc_out = null)
) ;
wait ;
end process P ;
end ARCH00267 ;
entity ENT00267_Test_Bench is
end ENT00267_Test_Bench ;
architecture ARCH00267_Test_Bench of ENT00267_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00267 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00267_Test_Bench ;
| gpl-3.0 | 2118dd44b5a8466ca999d4bca89f16f6 | 0.44759 | 3.810674 | false | true | false | false |
jairov4/accel-oil | solution_kintex7/sim/vhdl/AESL_autobus_sample_buffer.vhd | 1 | 28,942 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
library work;
use work.all;
entity AESL_autobus_sample_buffer is
generic (
constant TV_IN : STRING (1 to 74) := "../tv/cdatafile/c.nfa_accept_samples_generic_hw.autotvin_sample_buffer.dat";
constant TV_OUT : STRING (1 to 79) := "../tv/rtldatafile/rtl.nfa_accept_samples_generic_hw.autotvout_sample_buffer.dat";
constant DATA_WIDTH : INTEGER := 8;
constant ADDR_WIDTH : INTEGER := 32;
constant DEPTH : INTEGER := 10;
constant FIFO_DEPTH : INTEGER := 32;
constant FIFO_DEPTH_ADDR_WIDTH : INTEGER := 32
);
port (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
bus_req_RW : IN STD_LOGIC;
bus_req_full_n : OUT STD_LOGIC;
bus_req_RW_en : IN STD_LOGIC;
bus_rsp_empty_n : OUT STD_LOGIC;
bus_rsp_read : IN STD_LOGIC;
bus_address : IN STD_LOGIC_VECTOR (ADDR_WIDTH - 1 downto 0);
bus_din : IN STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
bus_dout : OUT STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
bus_size : IN STD_LOGIC_VECTOR ( 31 downto 0);
ready : IN STD_LOGIC;
done : IN STD_LOGIC
);
end AESL_autobus_sample_buffer;
architecture behav of AESL_autobus_sample_buffer is
-- Inner signals
signal FIFO_req_ptr_r : STD_LOGIC_VECTOR (FIFO_DEPTH_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal FIFO_req_ptr_w : STD_LOGIC_VECTOR (FIFO_DEPTH_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal FIFO_req_flag : STD_LOGIC := '0'; -- 0: empty hint, 1: full hint
signal FIFO_req_empty : STD_LOGIC := '0';
signal FIFO_req_full : STD_LOGIC := '0';
signal FIFO_req_read : STD_LOGIC := '0';
signal FIFO_req_burst_flag:STD_LOGIC := '0';
signal FIFO_rsp_ptr_r : STD_LOGIC_VECTOR (ADDR_WIDTH - 1 downto 0) := (others => '0');
signal FIFO_rsp_ptr_w : STD_LOGIC_VECTOR (ADDR_WIDTH - 1 downto 0) := (others => '0');
signal FIFO_rsp_flag : STD_LOGIC := '0';
signal FIFO_rsp_empty : STD_LOGIC;
signal FIFO_rsp_full : STD_LOGIC;
signal FIFO_rsp_write : STD_LOGIC;
signal FIFO_req_temp_state : STD_LOGIC_VECTOR(1 downto 0) := "00";
type arr_fifo_req_RW is array(0 to FIFO_DEPTH - 1) of STD_LOGIC;
type arr_fifo_req_addr is array(0 to FIFO_DEPTH - 1) of STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
type arr_fifo_req_din is array(0 to FIFO_DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
type arr_fifo_req_size is array(0 to FIFO_DEPTH - 1) of STD_LOGIC_VECTOR(31 downto 0);
type arr_mem is array(0 to DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
shared variable FIFO_req_RW : arr_fifo_req_RW;
shared variable FIFO_req_address: arr_fifo_req_addr;
shared variable FIFO_req_din : arr_fifo_req_din;
shared variable FIFO_req_size : arr_fifo_req_size;
shared variable mem : arr_mem := (others => (others => '0'));
shared variable FIFO_rsp_mem : arr_mem := (others => (others => '0'));
procedure esl_read_token (file textfile: TEXT; textline: inout LINE; token: out STRING; token_len: out INTEGER) is
variable whitespace : CHARACTER;
variable i : INTEGER;
variable ok: BOOLEAN;
variable buff: STRING(1 to token'length);
begin
ok := false;
i := 1;
loop_main: while not endfile(textfile) loop
if textline = null or textline'length = 0 then
readline(textfile, textline);
end if;
loop_remove_whitespace: while textline'length > 0 loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
read(textline, whitespace);
else
exit loop_remove_whitespace;
end if;
end loop;
loop_aesl_read_token: while textline'length > 0 and i <= buff'length loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
exit loop_aesl_read_token;
else
read(textline, buff(i));
i := i + 1;
end if;
ok := true;
end loop;
if ok = true then
exit loop_main;
end if;
end loop;
buff(i) := ' ';
token := buff;
token_len:= i-1;
end procedure esl_read_token;
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING) is
variable i : INTEGER;
begin
esl_read_token (textfile, textline, token, i);
end procedure esl_read_token;
function esl_add(v1, v2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable res : unsigned(v1'length-1 downto 0);
begin
res := unsigned(v1) + unsigned(v2);
return std_logic_vector(res);
end function;
function esl_sub(v1, v2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable res : unsigned(v1'length-1 downto 0);
begin
res := unsigned(v1) - unsigned(v2);
return std_logic_vector(res);
end function;
function esl_str2lv_hex (RHS : STRING; data_width : INTEGER) return STD_LOGIC_VECTOR is
variable ret : STD_LOGIC_VECTOR(data_width - 1 downto 0);
variable idx : integer := 3;
begin
ret := (others => '0');
if(RHS(1) /= '0' and (RHS(2) /= 'x' or RHS(2) /= 'X')) then
report "Error! The format of hex number is not initialed by 0x";
end if;
while true loop
if (data_width > 4) then
case RHS(idx) is
when '0' => ret := ret(data_width - 5 downto 0) & "0000";
when '1' => ret := ret(data_width - 5 downto 0) & "0001";
when '2' => ret := ret(data_width - 5 downto 0) & "0010";
when '3' => ret := ret(data_width - 5 downto 0) & "0011";
when '4' => ret := ret(data_width - 5 downto 0) & "0100";
when '5' => ret := ret(data_width - 5 downto 0) & "0101";
when '6' => ret := ret(data_width - 5 downto 0) & "0110";
when '7' => ret := ret(data_width - 5 downto 0) & "0111";
when '8' => ret := ret(data_width - 5 downto 0) & "1000";
when '9' => ret := ret(data_width - 5 downto 0) & "1001";
when 'a' | 'A' => ret := ret(data_width - 5 downto 0) & "1010";
when 'b' | 'B' => ret := ret(data_width - 5 downto 0) & "1011";
when 'c' | 'C' => ret := ret(data_width - 5 downto 0) & "1100";
when 'd' | 'D' => ret := ret(data_width - 5 downto 0) & "1101";
when 'e' | 'E' => ret := ret(data_width - 5 downto 0) & "1110";
when 'f' | 'F' => ret := ret(data_width - 5 downto 0) & "1111";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 4) then
case RHS(idx) is
when '0' => ret := "0000";
when '1' => ret := "0001";
when '2' => ret := "0010";
when '3' => ret := "0011";
when '4' => ret := "0100";
when '5' => ret := "0101";
when '6' => ret := "0110";
when '7' => ret := "0111";
when '8' => ret := "1000";
when '9' => ret := "1001";
when 'a' | 'A' => ret := "1010";
when 'b' | 'B' => ret := "1011";
when 'c' | 'C' => ret := "1100";
when 'd' | 'D' => ret := "1101";
when 'e' | 'E' => ret := "1110";
when 'f' | 'F' => ret := "1111";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 3) then
case RHS(idx) is
when '0' => ret := "000";
when '1' => ret := "001";
when '2' => ret := "010";
when '3' => ret := "011";
when '4' => ret := "100";
when '5' => ret := "101";
when '6' => ret := "110";
when '7' => ret := "111";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 2) then
case RHS(idx) is
when '0' => ret := "00";
when '1' => ret := "01";
when '2' => ret := "10";
when '3' => ret := "11";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 1) then
case RHS(idx) is
when '0' => ret := "0";
when '1' => ret := "1";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
else
report string'("Wrong data_width.");
return ret;
end if;
idx := idx + 1;
end loop;
return ret;
end function;
function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING is
constant str_len : integer := (lv'length + 3)/4;
variable ret : STRING (1 to str_len);
variable i, tmp: INTEGER;
variable normal_lv : STD_LOGIC_VECTOR(lv'length - 1 downto 0);
variable tmp_lv : STD_LOGIC_VECTOR(3 downto 0);
begin
normal_lv := lv;
for i in 1 to str_len loop
if(i = 1) then
if((lv'length mod 4) = 3) then
tmp_lv(2 downto 0) := normal_lv(lv'length - 1 downto lv'length - 3);
case tmp_lv(2 downto 0) is
when "000" => ret(i) := '0';
when "001" => ret(i) := '1';
when "010" => ret(i) := '2';
when "011" => ret(i) := '3';
when "100" => ret(i) := '4';
when "101" => ret(i) := '5';
when "110" => ret(i) := '6';
when "111" => ret(i) := '7';
when others => ret(i) := '0';
end case;
elsif((lv'length mod 4) = 2) then
tmp_lv(1 downto 0) := normal_lv(lv'length - 1 downto lv'length - 2);
case tmp_lv(1 downto 0) is
when "00" => ret(i) := '0';
when "01" => ret(i) := '1';
when "10" => ret(i) := '2';
when "11" => ret(i) := '3';
when others => ret(i) := '0';
end case;
elsif((lv'length mod 4) = 1) then
tmp_lv(0 downto 0) := normal_lv(lv'length - 1 downto lv'length - 1);
case tmp_lv(0 downto 0) is
when "0" => ret(i) := '0';
when "1" => ret(i) := '1';
when others=> ret(i) := '0';
end case;
elsif((lv'length mod 4) = 0) then
tmp_lv(3 downto 0) := normal_lv(lv'length - 1 downto lv'length - 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := '0';
end case;
end if;
else
tmp_lv(3 downto 0) := normal_lv((str_len - i) * 4 + 3 downto (str_len - i) * 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := '0';
end case;
end if;
end loop;
return ret;
end function;
begin
-------------- Assignment for output port -------------------
assign_proc : process
begin
wait until (clk'event and clk = '1');
wait for 0.4 ns;
bus_dout <= FIFO_rsp_mem(CONV_INTEGER(FIFO_rsp_ptr_r));
end process;
bus_rsp_proc : process(FIFO_rsp_empty)
begin
bus_rsp_empty_n <= not FIFO_rsp_empty;
end process;
bus_req_full_n_proc : process(FIFO_req_full)
begin
bus_req_full_n <= not FIFO_req_full;
end process;
FIFO_req_empty_full_proc : process(FIFO_req_ptr_r, FIFO_req_ptr_w, FIFO_req_flag)
begin
if(FIFO_req_ptr_r = FIFO_req_ptr_w) then
if(FIFO_req_flag = '1') then
FIFO_req_full <= '1';
FIFO_req_empty <= '0';
else
FIFO_req_full <= '0';
FIFO_req_empty <= '1';
end if;
else
FIFO_req_full <= '0';
FIFO_req_empty <= '0';
end if;
end process;
FIFO_rsp_empty_full_proc : process(FIFO_rsp_ptr_r, FIFO_rsp_ptr_w, FIFO_rsp_flag)
begin
if(FIFO_rsp_ptr_r = FIFO_rsp_ptr_w) then
if(FIFO_rsp_flag = '1') then
FIFO_rsp_full <= '1';
FIFO_rsp_empty <= '0';
else
FIFO_rsp_full <= '0';
FIFO_rsp_empty <= '1';
end if;
else
FIFO_rsp_full <= '0';
FIFO_rsp_empty <= '0';
end if;
end process;
-- Push RTL's req into FIFO_req
FIFO_req_write_proc : process(clk, rst)
begin
if(rst = '1') then
FIFO_req_ptr_w <= (others => '0');
elsif (clk'event and clk = '1') then
if(bus_req_RW_en = '1' and FIFO_req_full = '0') then
FIFO_req_RW(CONV_INTEGER(FIFO_req_ptr_w)) := bus_req_RW;
FIFO_req_address(CONV_INTEGER(FIFO_req_ptr_w)) := bus_address;
FIFO_req_din(CONV_INTEGER(FIFO_req_ptr_w)) := bus_din;
FIFO_req_size(CONV_INTEGER(FIFO_req_ptr_w)) := bus_size;
if(CONV_INTEGER(FIFO_req_ptr_w) /= FIFO_DEPTH - 1) then
FIFO_req_ptr_w <= esl_add(FIFO_req_ptr_w,"1");
else
FIFO_req_ptr_w <= (others => '0');
end if;
end if;
end if;
end process;
FIFO_req_read_proc : process(clk, rst)
variable FIFO_req_RW_temp : STD_LOGIC;
variable FIFO_req_address_temp : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
variable FIFO_req_din_temp : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
variable FIFO_req_size_temp : STD_LOGIC_VECTOR(31 downto 0);
constant IDLE_STATE : STD_LOGIC_VECTOR(1 downto 0) := "00";
constant READ_BURST_STATE : STD_LOGIC_VECTOR(1 downto 0) := "01";
constant WRITE_BURST_STATE : STD_LOGIC_VECTOR(1 downto 0) := "10";
begin
if(rst = '1') then
FIFO_req_temp_state <= IDLE_STATE;
FIFO_req_read <= '0';
FIFO_rsp_write <= '0';
elsif (clk'event and clk = '1') then
case FIFO_req_temp_state is
when IDLE_STATE =>
if(FIFO_req_empty = '0' and FIFO_rsp_full = '0') then
FIFO_req_read <= '1';
if(CONV_INTEGER(FIFO_req_ptr_r) /= FIFO_DEPTH - 1) then
FIFO_req_ptr_r <= esl_add(FIFO_req_ptr_r, "1");
else
FIFO_req_ptr_r <= (others => '0');
end if;
FIFO_req_RW_temp:= FIFO_req_RW(CONV_INTEGER(FIFO_req_ptr_r));
FIFO_req_address_temp := FIFO_req_address(CONV_INTEGER(FIFO_req_ptr_r));
FIFO_req_din_temp := FIFO_req_din(CONV_INTEGER(FIFO_req_ptr_r));
FIFO_req_size_temp := FIFO_req_size(CONV_INTEGER(FIFO_req_ptr_r));
-- Read request
if(FIFO_req_RW_temp = '0') then
FIFO_rsp_write <= '1'; -- Indicate the output is valid
FIFO_rsp_mem(CONV_INTEGER(FIFO_rsp_ptr_w)) := mem(CONV_INTEGER(FIFO_req_address_temp));
if(FIFO_rsp_ptr_w /= DEPTH - 1) then
FIFO_rsp_ptr_w <= esl_add(FIFO_rsp_ptr_w,"1");
else
FIFO_rsp_ptr_w <= (others => '0');
end if;
if(CONV_INTEGER(FIFO_req_size_temp) /= 0 and CONV_INTEGER(FIFO_req_size_temp) /= 1) then -- Read burst request
FIFO_req_temp_state <= READ_BURST_STATE; -- To deal with the rest data
end if;
else
FIFO_rsp_write <= '0'; -- Indicate the output is not valid
if(CONV_INTEGER(FIFO_req_size_temp) = 0 or CONV_INTEGER(FIFO_req_size_temp) = 1) then -- Write single request
mem(CONV_INTEGER(FIFO_req_address_temp)) := FIFO_req_din_temp;
else -- Write burst request
mem(CONV_INTEGER(FIFO_req_address_temp)) := FIFO_req_din_temp; -- Input the first data
FIFO_req_temp_state <= WRITE_BURST_STATE; -- To deal with the rest data
end if;
end if;
else -- There is no request in the FIFO_req
FIFO_req_read <= '0';
FIFO_rsp_write <= '0';
end if;
when READ_BURST_STATE =>
FIFO_req_read <= '0'; -- Stop reading the next request
FIFO_req_size_temp := esl_sub(FIFO_req_size_temp, "1");
if(CONV_INTEGER(FIFO_req_address_temp) /= DEPTH - 1) then
FIFO_req_address_temp := esl_add(FIFO_req_address_temp, "1");
else
report "Burst read out of size!";
end if;
FIFO_rsp_mem(CONV_INTEGER(FIFO_rsp_ptr_w)) := mem(CONV_INTEGER(FIFO_req_address_temp));
if(CONV_INTEGER(FIFO_rsp_ptr_w) /= DEPTH - 1) then
FIFO_rsp_ptr_w <= esl_add(FIFO_rsp_ptr_w, "1");
else
FIFO_rsp_ptr_w <= (others => '0');
end if;
if(CONV_INTEGER(FIFO_req_size_temp) = 1) then -- The last one is done
FIFO_req_temp_state <= IDLE_STATE;
end if;
when WRITE_BURST_STATE =>
if(FIFO_req_empty = '0') then
FIFO_req_read <= '1'; -- Keep reading the next data(The data is storaged in FIFO_req but it is not a request)
if(CONV_INTEGER(FIFO_req_ptr_r) /= FIFO_DEPTH - 1) then
FIFO_req_ptr_r <= esl_add(FIFO_req_ptr_r, "1");
else
FIFO_req_ptr_r <= (others => '0');
end if;
FIFO_req_size_temp := esl_sub(FIFO_req_size_temp, "1");
if(CONV_INTEGER(FIFO_req_address_temp) /= DEPTH - 1) then
FIFO_req_address_temp := esl_add(FIFO_req_address_temp, "1");
else
report "Burst write out of size!";
end if;
mem(CONV_INTEGER(FIFO_req_address_temp)) := FIFO_req_din(CONV_INTEGER(FIFO_req_ptr_r));
if(CONV_INTEGER(FIFO_req_size_temp) = 1) then -- The last one is done
FIFO_req_temp_state <= IDLE_STATE;
end if;
end if;
when OTHERS =>
FIFO_req_temp_state <= IDLE_STATE;
end case;
end if;
end process;
-- Generate "FIFO_req_flag"
FIFO_req_flag_proc : process
begin
wait until clk'event and clk = '1';
if(rst = '1') then
FIFO_req_flag <= '0';
else
if((bus_req_RW_en = '1' and FIFO_req_full /= '1') and CONV_INTEGER(FIFO_req_ptr_w) = FIFO_DEPTH - 1) then
FIFO_req_flag <= '1';
end if;
wait for 0.4 ns;
if((FIFO_req_read = '1' and FIFO_req_empty /= '1') and CONV_INTEGER(FIFO_req_ptr_r) = 0) then
FIFO_req_flag <= '0';
end if;
end if;
end process;
-- Generate "FIFO_rsp_flag"
FIFO_rsp_flag_proc : process
begin
wait until clk'event and clk = '1';
if(rst = '1') then
FIFO_rsp_flag <= '0';
else
if((bus_rsp_read = '1' and FIFO_rsp_empty /= '1') and CONV_INTEGER(FIFO_rsp_ptr_r) = DEPTH - 1) then
FIFO_rsp_flag <= '0';
end if;
wait for 0.4 ns;
if((FIFO_rsp_write = '1' and FIFO_rsp_full /= '1') and CONV_INTEGER(FIFO_rsp_ptr_w) = 0) then
FIFO_rsp_flag <= '1';
end if;
end if;
end process;
-- Pop data from FIFO_rsp
FIFO_rsp_ptr_r_proc : process(clk, rst)
begin
if(rst = '1') then
FIFO_rsp_ptr_r <= (others => '0');
elsif (clk'event and clk = '1') then
if(bus_rsp_read = '1' and FIFO_rsp_empty /= '1') then
if(CONV_INTEGER(FIFO_rsp_ptr_r) /= DEPTH - 1) then
FIFO_rsp_ptr_r <= esl_add(FIFO_rsp_ptr_r, "1");
else
FIFO_rsp_ptr_r <= (others => '0');
end if;
end if;
end if;
end process;
----------------------------Read file-------------------
-- Read data from file
read_file_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 128 );
variable token_len : INTEGER;
variable token_int : INTEGER;
variable idx : INTEGER;
--variable mem_var : arr2D;
begin
file_open(fstatus, fp, TV_IN, READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & TV_IN & " failed!!!" severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
report "The token is " & token;
assert false report "Illegal format of [[[runtime]]] part in " & TV_IN severity failure;
end if;
esl_read_token(fp, token_line, token);
while(token(1 to 14) /= "[[[/runtime]]]") loop
if(token(1 to 15) /= "[[transaction]]") then
report "The token is " & token;
assert false report "Illegal format of [[transaction]] part in " & TV_IN severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
-- Start to read data for every transaction round
wait until clk'event and clk = '1';
wait for 0.2 ns;
while(ready /= '1') loop
wait until clk'event and clk = '1';
wait for 0.2 ns;
end loop;
for i in 0 to DEPTH - 1 loop
esl_read_token(fp, token_line, token);
mem(i) := esl_str2lv_hex(token, DATA_WIDTH);
end loop;
esl_read_token(fp, token_line, token);
if(token(1 to 16) /= "[[/transaction]]") then
report "The token is " & token;
assert false report "Illegal format of [[/transaction]] part in " & TV_IN severity failure;
end if;
esl_read_token(fp, token_line, token);
end loop;
file_close(fp);
wait;
end process;
----------------------------Write file-------------------
-- Write data to file
write_file_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 128 );
variable transaction_idx : INTEGER;
begin
wait until (rst = '0');
transaction_idx := 0;
while(true) loop
wait until clk'event and clk = '1';
while(done /= '1') loop
wait until clk'event and clk = '1';
end loop;
wait for 0.1 ns;
file_open(fstatus, fp, TV_OUT, APPEND_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & TV_OUT & " failed!!!" severity failure;
end if;
write(token_line, "[[transaction]] " & integer'image(transaction_idx));
writeline(fp, token_line);
for i in 0 to DEPTH - 1 loop
write(token_line, "0x" & esl_conv_string_hex(mem(i)));
writeline(fp, token_line);
end loop;
write(token_line, string'("[[/transaction]]"));
writeline(fp, token_line);
transaction_idx := transaction_idx + 1;
file_close(fp);
end loop;
wait;
end process;
end behav;
| lgpl-3.0 | f341296d9d613febb2563ed715be7b52 | 0.431311 | 3.803154 | false | false | false | false |
rauenzi/VHDL-Communications | i2c_controller.vhd | 1 | 3,958 | ----------------------------------------------------------------------------------
--Code by: Zachary Rauen
--Date: 1/8/15
--Last Modified: 1/15/15
--
--Description: This takes in 16 bit data and displays them on an external display
-- using GPIO and I2C communication.
--
--Version: 2.1
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity i2c_controller is
Generic (slave_addr : std_logic_vector(6 downto 0) := "1110001");
Port ( Clock : in STD_LOGIC;
dataIn : in STD_LOGIC_VECTOR (15 downto 0);
oSDA : inout STD_LOGIC;
oSCL : inout STD_LOGIC);
end i2c_controller;
architecture Behavioral of i2c_controller is
component i2c_master IS
GENERIC(
input_clk : INTEGER := 100_000_000; --input clock speed from user logic in Hz
bus_clk : INTEGER := 400_000); --speed the i2c bus (scl) will run at in Hz
PORT(
clk : IN STD_LOGIC; --system clock
reset_n : IN STD_LOGIC; --active low reset
ena : IN STD_LOGIC; --latch in command
addr : IN STD_LOGIC_VECTOR(6 DOWNTO 0); --address of target slave
rw : IN STD_LOGIC; --'0' is write, '1' is read
data_wr : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --data to write to slave
busy : OUT STD_LOGIC; --indicates transaction in progress
data_rd : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --data read from slave
ack_error : BUFFER STD_LOGIC; --flag if improper acknowledge from slave
sda : INOUT STD_LOGIC; --serial data output of i2c bus
scl : INOUT STD_LOGIC); --serial clock output of i2c bus
END component i2c_master;
signal regBusy,sigBusy,reset,enable,readwrite,nack : std_logic;
signal regData : std_logic_vector(15 downto 0);
signal dataOut : std_logic_vector(7 downto 0);
signal byteChoice : integer := 1;
signal byteChoiceMax : integer := 13;
signal initialCount : integer := 0;
type state_type is (start,write,stop);
signal State : state_type := start;
signal address : std_logic_vector(6 downto 0);
signal Cnt : integer := 16383;
begin
output: i2c_master
port map (
clk=>Clock,
reset_n=>reset,
ena=>enable,
addr=>address,
rw=>readwrite,
data_wr=>dataOut,
busy=>sigBusy,
data_rd=>OPEN,
ack_error=>nack,
sda=>oSDA,
scl=>oSCL);
StateChange: process (Clock)
begin
if rising_edge(Clock) then
case State is
when start =>
if Cnt /= 0 then
Cnt<=Cnt-1;
reset<='0';
State<=start;
enable<='0';
else
reset<='1';
enable<='1';
address<=slave_addr;
readwrite<='0';
State<=write;
end if;
when write=>
regBusy<=sigBusy;
regData<=dataIn;
if regBusy/=sigBusy and sigBusy='0' then
if byteChoice /= byteChoiceMax then
byteChoice<=byteChoice+1;
State<=write;
else
byteChoice<=8;
State<=stop;
end if;
end if;
when stop=>
enable<='0';
if regData/=dataIn then
State<=start;
else
State<=stop;
end if;
end case;
end if;
end process;
process(byteChoice,Clock)
begin
case byteChoice is
when 1 => dataOut <= x"76";
when 2 => dataOut <= x"76";
when 3 => dataOut <= x"76";
when 4 => dataOut <= x"7A";
when 5 => dataOut <= x"FF";
when 6 => dataOut <= x"77";
when 7 => dataOut <= x"00";
when 8 => dataOut <= x"79";
when 9 => dataOut <= x"00";
when 10 => dataOut <= x"0" & dataIn(15 downto 12);
when 11 => dataOut <= x"0" & dataIn(11 downto 8);
when 12 => dataOut <= x"0" & dataIn(7 downto 4);
when 13 => dataOut <= x"0" & dataIn(3 downto 0);
when others => dataOut <= x"76";
end case;
end process;
end Behavioral;
| apache-2.0 | 7d81fcfa4c731fe68bcbb83caf53e959 | 0.557605 | 3.524488 | false | false | false | false |
jairov4/accel-oil | impl/impl_test_pcie/hdl/system.vhd | 1 | 474,353 | -------------------------------------------------------------------------------
-- system.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system is
port (
fpga_0_DDR2_SDRAM_DDR2_Clk_pin : out std_logic_vector(1 downto 0);
fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin : out std_logic_vector(1 downto 0);
fpga_0_DDR2_SDRAM_DDR2_CE_pin : out std_logic_vector(1 downto 0);
fpga_0_DDR2_SDRAM_DDR2_CS_n_pin : out std_logic_vector(1 downto 0);
fpga_0_DDR2_SDRAM_DDR2_ODT_pin : out std_logic_vector(1 downto 0);
fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin : out std_logic;
fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin : out std_logic;
fpga_0_DDR2_SDRAM_DDR2_WE_n_pin : out std_logic;
fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin : out std_logic_vector(1 downto 0);
fpga_0_DDR2_SDRAM_DDR2_Addr_pin : out std_logic_vector(12 downto 0);
fpga_0_DDR2_SDRAM_DDR2_DQ_pin : inout std_logic_vector(63 downto 0);
fpga_0_DDR2_SDRAM_DDR2_DM_pin : out std_logic_vector(7 downto 0);
fpga_0_DDR2_SDRAM_DDR2_DQS_pin : inout std_logic_vector(7 downto 0);
fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin : inout std_logic_vector(7 downto 0);
fpga_0_SRAM_Mem_A_pin : out std_logic_vector(7 to 30);
fpga_0_SRAM_Mem_CEN_pin : out std_logic;
fpga_0_SRAM_Mem_OEN_pin : out std_logic;
fpga_0_SRAM_Mem_WEN_pin : out std_logic;
fpga_0_SRAM_Mem_BEN_pin : out std_logic_vector(0 to 3);
fpga_0_SRAM_Mem_ADV_LDN_pin : out std_logic;
fpga_0_SRAM_Mem_DQ_pin : inout std_logic_vector(0 to 31);
fpga_0_SRAM_ZBT_CLK_OUT_pin : out std_logic;
fpga_0_SRAM_ZBT_CLK_FB_pin : in std_logic;
fpga_0_PCIe_Bridge_RXN_pin : in std_logic;
fpga_0_PCIe_Bridge_RXP_pin : in std_logic;
fpga_0_PCIe_Bridge_TXN_pin : out std_logic;
fpga_0_PCIe_Bridge_TXP_pin : out std_logic;
fpga_0_clk_1_sys_clk_pin : in std_logic;
fpga_0_rst_1_sys_rst_pin : in std_logic;
fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin : in std_logic;
fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin : in std_logic
);
end system;
architecture STRUCTURE of system is
component system_microblaze_0_wrapper is
port (
CLK : in std_logic;
RESET : in std_logic;
MB_RESET : in std_logic;
INTERRUPT : in std_logic;
INTERRUPT_ADDRESS : in std_logic_vector(0 to 31);
INTERRUPT_ACK : out std_logic_vector(0 to 1);
EXT_BRK : in std_logic;
EXT_NM_BRK : in std_logic;
DBG_STOP : in std_logic;
MB_Halted : out std_logic;
MB_Error : out std_logic;
WAKEUP : in std_logic_vector(0 to 1);
SLEEP : out std_logic;
DBG_WAKEUP : out std_logic;
LOCKSTEP_MASTER_OUT : out std_logic_vector(0 to 4095);
LOCKSTEP_SLAVE_IN : in std_logic_vector(0 to 4095);
LOCKSTEP_OUT : out std_logic_vector(0 to 4095);
INSTR : in std_logic_vector(0 to 31);
IREADY : in std_logic;
IWAIT : in std_logic;
ICE : in std_logic;
IUE : in std_logic;
INSTR_ADDR : out std_logic_vector(0 to 31);
IFETCH : out std_logic;
I_AS : out std_logic;
IPLB_M_ABort : out std_logic;
IPLB_M_ABus : out std_logic_vector(0 to 31);
IPLB_M_UABus : out std_logic_vector(0 to 31);
IPLB_M_BE : out std_logic_vector(0 to 7);
IPLB_M_busLock : out std_logic;
IPLB_M_lockErr : out std_logic;
IPLB_M_MSize : out std_logic_vector(0 to 1);
IPLB_M_priority : out std_logic_vector(0 to 1);
IPLB_M_rdBurst : out std_logic;
IPLB_M_request : out std_logic;
IPLB_M_RNW : out std_logic;
IPLB_M_size : out std_logic_vector(0 to 3);
IPLB_M_TAttribute : out std_logic_vector(0 to 15);
IPLB_M_type : out std_logic_vector(0 to 2);
IPLB_M_wrBurst : out std_logic;
IPLB_M_wrDBus : out std_logic_vector(0 to 63);
IPLB_MBusy : in std_logic;
IPLB_MRdErr : in std_logic;
IPLB_MWrErr : in std_logic;
IPLB_MIRQ : in std_logic;
IPLB_MWrBTerm : in std_logic;
IPLB_MWrDAck : in std_logic;
IPLB_MAddrAck : in std_logic;
IPLB_MRdBTerm : in std_logic;
IPLB_MRdDAck : in std_logic;
IPLB_MRdDBus : in std_logic_vector(0 to 63);
IPLB_MRdWdAddr : in std_logic_vector(0 to 3);
IPLB_MRearbitrate : in std_logic;
IPLB_MSSize : in std_logic_vector(0 to 1);
IPLB_MTimeout : in std_logic;
DATA_READ : in std_logic_vector(0 to 31);
DREADY : in std_logic;
DWAIT : in std_logic;
DCE : in std_logic;
DUE : in std_logic;
DATA_WRITE : out std_logic_vector(0 to 31);
DATA_ADDR : out std_logic_vector(0 to 31);
D_AS : out std_logic;
READ_STROBE : out std_logic;
WRITE_STROBE : out std_logic;
BYTE_ENABLE : out std_logic_vector(0 to 3);
DPLB_M_ABort : out std_logic;
DPLB_M_ABus : out std_logic_vector(0 to 31);
DPLB_M_UABus : out std_logic_vector(0 to 31);
DPLB_M_BE : out std_logic_vector(0 to 7);
DPLB_M_busLock : out std_logic;
DPLB_M_lockErr : out std_logic;
DPLB_M_MSize : out std_logic_vector(0 to 1);
DPLB_M_priority : out std_logic_vector(0 to 1);
DPLB_M_rdBurst : out std_logic;
DPLB_M_request : out std_logic;
DPLB_M_RNW : out std_logic;
DPLB_M_size : out std_logic_vector(0 to 3);
DPLB_M_TAttribute : out std_logic_vector(0 to 15);
DPLB_M_type : out std_logic_vector(0 to 2);
DPLB_M_wrBurst : out std_logic;
DPLB_M_wrDBus : out std_logic_vector(0 to 63);
DPLB_MBusy : in std_logic;
DPLB_MRdErr : in std_logic;
DPLB_MWrErr : in std_logic;
DPLB_MIRQ : in std_logic;
DPLB_MWrBTerm : in std_logic;
DPLB_MWrDAck : in std_logic;
DPLB_MAddrAck : in std_logic;
DPLB_MRdBTerm : in std_logic;
DPLB_MRdDAck : in std_logic;
DPLB_MRdDBus : in std_logic_vector(0 to 63);
DPLB_MRdWdAddr : in std_logic_vector(0 to 3);
DPLB_MRearbitrate : in std_logic;
DPLB_MSSize : in std_logic_vector(0 to 1);
DPLB_MTimeout : in std_logic;
M_AXI_IP_AWID : out std_logic_vector(0 downto 0);
M_AXI_IP_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_IP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_AWLOCK : out std_logic;
M_AXI_IP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_AWVALID : out std_logic;
M_AXI_IP_AWREADY : in std_logic;
M_AXI_IP_WDATA : out std_logic_vector(31 downto 0);
M_AXI_IP_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_IP_WLAST : out std_logic;
M_AXI_IP_WVALID : out std_logic;
M_AXI_IP_WREADY : in std_logic;
M_AXI_IP_BID : in std_logic_vector(0 downto 0);
M_AXI_IP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_BVALID : in std_logic;
M_AXI_IP_BREADY : out std_logic;
M_AXI_IP_ARID : out std_logic_vector(0 downto 0);
M_AXI_IP_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_IP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_ARLOCK : out std_logic;
M_AXI_IP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_ARVALID : out std_logic;
M_AXI_IP_ARREADY : in std_logic;
M_AXI_IP_RID : in std_logic_vector(0 downto 0);
M_AXI_IP_RDATA : in std_logic_vector(31 downto 0);
M_AXI_IP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_RLAST : in std_logic;
M_AXI_IP_RVALID : in std_logic;
M_AXI_IP_RREADY : out std_logic;
M_AXI_DP_AWID : out std_logic_vector(0 downto 0);
M_AXI_DP_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_DP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_AWLOCK : out std_logic;
M_AXI_DP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_AWVALID : out std_logic;
M_AXI_DP_AWREADY : in std_logic;
M_AXI_DP_WDATA : out std_logic_vector(31 downto 0);
M_AXI_DP_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_DP_WLAST : out std_logic;
M_AXI_DP_WVALID : out std_logic;
M_AXI_DP_WREADY : in std_logic;
M_AXI_DP_BID : in std_logic_vector(0 downto 0);
M_AXI_DP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_BVALID : in std_logic;
M_AXI_DP_BREADY : out std_logic;
M_AXI_DP_ARID : out std_logic_vector(0 downto 0);
M_AXI_DP_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_DP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_ARLOCK : out std_logic;
M_AXI_DP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_ARVALID : out std_logic;
M_AXI_DP_ARREADY : in std_logic;
M_AXI_DP_RID : in std_logic_vector(0 downto 0);
M_AXI_DP_RDATA : in std_logic_vector(31 downto 0);
M_AXI_DP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_RLAST : in std_logic;
M_AXI_DP_RVALID : in std_logic;
M_AXI_DP_RREADY : out std_logic;
M_AXI_IC_AWID : out std_logic_vector(0 downto 0);
M_AXI_IC_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_IC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_AWLOCK : out std_logic;
M_AXI_IC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_AWVALID : out std_logic;
M_AXI_IC_AWREADY : in std_logic;
M_AXI_IC_AWUSER : out std_logic_vector(4 downto 0);
M_AXI_IC_AWDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_IC_AWSNOOP : out std_logic_vector(2 downto 0);
M_AXI_IC_AWBAR : out std_logic_vector(1 downto 0);
M_AXI_IC_WDATA : out std_logic_vector(31 downto 0);
M_AXI_IC_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_IC_WLAST : out std_logic;
M_AXI_IC_WVALID : out std_logic;
M_AXI_IC_WREADY : in std_logic;
M_AXI_IC_WUSER : out std_logic_vector(0 downto 0);
M_AXI_IC_BID : in std_logic_vector(0 downto 0);
M_AXI_IC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IC_BVALID : in std_logic;
M_AXI_IC_BREADY : out std_logic;
M_AXI_IC_BUSER : in std_logic_vector(0 downto 0);
M_AXI_IC_WACK : out std_logic;
M_AXI_IC_ARID : out std_logic_vector(0 downto 0);
M_AXI_IC_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_IC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_ARLOCK : out std_logic;
M_AXI_IC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_ARVALID : out std_logic;
M_AXI_IC_ARREADY : in std_logic;
M_AXI_IC_ARUSER : out std_logic_vector(4 downto 0);
M_AXI_IC_ARDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_IC_ARSNOOP : out std_logic_vector(3 downto 0);
M_AXI_IC_ARBAR : out std_logic_vector(1 downto 0);
M_AXI_IC_RID : in std_logic_vector(0 downto 0);
M_AXI_IC_RDATA : in std_logic_vector(31 downto 0);
M_AXI_IC_RRESP : in std_logic_vector(1 downto 0);
M_AXI_IC_RLAST : in std_logic;
M_AXI_IC_RVALID : in std_logic;
M_AXI_IC_RREADY : out std_logic;
M_AXI_IC_RUSER : in std_logic_vector(0 downto 0);
M_AXI_IC_RACK : out std_logic;
M_AXI_IC_ACVALID : in std_logic;
M_AXI_IC_ACADDR : in std_logic_vector(31 downto 0);
M_AXI_IC_ACSNOOP : in std_logic_vector(3 downto 0);
M_AXI_IC_ACPROT : in std_logic_vector(2 downto 0);
M_AXI_IC_ACREADY : out std_logic;
M_AXI_IC_CRREADY : in std_logic;
M_AXI_IC_CRVALID : out std_logic;
M_AXI_IC_CRRESP : out std_logic_vector(4 downto 0);
M_AXI_IC_CDVALID : out std_logic;
M_AXI_IC_CDREADY : in std_logic;
M_AXI_IC_CDDATA : out std_logic_vector(31 downto 0);
M_AXI_IC_CDLAST : out std_logic;
M_AXI_DC_AWID : out std_logic_vector(0 downto 0);
M_AXI_DC_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_DC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_AWLOCK : out std_logic;
M_AXI_DC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_AWVALID : out std_logic;
M_AXI_DC_AWREADY : in std_logic;
M_AXI_DC_AWUSER : out std_logic_vector(4 downto 0);
M_AXI_DC_AWDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_DC_AWSNOOP : out std_logic_vector(2 downto 0);
M_AXI_DC_AWBAR : out std_logic_vector(1 downto 0);
M_AXI_DC_WDATA : out std_logic_vector(31 downto 0);
M_AXI_DC_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_DC_WLAST : out std_logic;
M_AXI_DC_WVALID : out std_logic;
M_AXI_DC_WREADY : in std_logic;
M_AXI_DC_WUSER : out std_logic_vector(0 downto 0);
M_AXI_DC_BID : in std_logic_vector(0 downto 0);
M_AXI_DC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DC_BVALID : in std_logic;
M_AXI_DC_BREADY : out std_logic;
M_AXI_DC_BUSER : in std_logic_vector(0 downto 0);
M_AXI_DC_WACK : out std_logic;
M_AXI_DC_ARID : out std_logic_vector(0 downto 0);
M_AXI_DC_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_DC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_ARLOCK : out std_logic;
M_AXI_DC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_ARVALID : out std_logic;
M_AXI_DC_ARREADY : in std_logic;
M_AXI_DC_ARUSER : out std_logic_vector(4 downto 0);
M_AXI_DC_ARDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_DC_ARSNOOP : out std_logic_vector(3 downto 0);
M_AXI_DC_ARBAR : out std_logic_vector(1 downto 0);
M_AXI_DC_RID : in std_logic_vector(0 downto 0);
M_AXI_DC_RDATA : in std_logic_vector(31 downto 0);
M_AXI_DC_RRESP : in std_logic_vector(1 downto 0);
M_AXI_DC_RLAST : in std_logic;
M_AXI_DC_RVALID : in std_logic;
M_AXI_DC_RREADY : out std_logic;
M_AXI_DC_RUSER : in std_logic_vector(0 downto 0);
M_AXI_DC_RACK : out std_logic;
M_AXI_DC_ACVALID : in std_logic;
M_AXI_DC_ACADDR : in std_logic_vector(31 downto 0);
M_AXI_DC_ACSNOOP : in std_logic_vector(3 downto 0);
M_AXI_DC_ACPROT : in std_logic_vector(2 downto 0);
M_AXI_DC_ACREADY : out std_logic;
M_AXI_DC_CRREADY : in std_logic;
M_AXI_DC_CRVALID : out std_logic;
M_AXI_DC_CRRESP : out std_logic_vector(4 downto 0);
M_AXI_DC_CDVALID : out std_logic;
M_AXI_DC_CDREADY : in std_logic;
M_AXI_DC_CDDATA : out std_logic_vector(31 downto 0);
M_AXI_DC_CDLAST : out std_logic;
DBG_CLK : in std_logic;
DBG_TDI : in std_logic;
DBG_TDO : out std_logic;
DBG_REG_EN : in std_logic_vector(0 to 7);
DBG_SHIFT : in std_logic;
DBG_CAPTURE : in std_logic;
DBG_UPDATE : in std_logic;
DEBUG_RST : in std_logic;
Trace_Instruction : out std_logic_vector(0 to 31);
Trace_Valid_Instr : out std_logic;
Trace_PC : out std_logic_vector(0 to 31);
Trace_Reg_Write : out std_logic;
Trace_Reg_Addr : out std_logic_vector(0 to 4);
Trace_MSR_Reg : out std_logic_vector(0 to 14);
Trace_PID_Reg : out std_logic_vector(0 to 7);
Trace_New_Reg_Value : out std_logic_vector(0 to 31);
Trace_Exception_Taken : out std_logic;
Trace_Exception_Kind : out std_logic_vector(0 to 4);
Trace_Jump_Taken : out std_logic;
Trace_Delay_Slot : out std_logic;
Trace_Data_Address : out std_logic_vector(0 to 31);
Trace_Data_Access : out std_logic;
Trace_Data_Read : out std_logic;
Trace_Data_Write : out std_logic;
Trace_Data_Write_Value : out std_logic_vector(0 to 31);
Trace_Data_Byte_Enable : out std_logic_vector(0 to 3);
Trace_DCache_Req : out std_logic;
Trace_DCache_Hit : out std_logic;
Trace_DCache_Rdy : out std_logic;
Trace_DCache_Read : out std_logic;
Trace_ICache_Req : out std_logic;
Trace_ICache_Hit : out std_logic;
Trace_ICache_Rdy : out std_logic;
Trace_OF_PipeRun : out std_logic;
Trace_EX_PipeRun : out std_logic;
Trace_MEM_PipeRun : out std_logic;
Trace_MB_Halted : out std_logic;
Trace_Jump_Hit : out std_logic;
FSL0_S_CLK : out std_logic;
FSL0_S_READ : out std_logic;
FSL0_S_DATA : in std_logic_vector(0 to 31);
FSL0_S_CONTROL : in std_logic;
FSL0_S_EXISTS : in std_logic;
FSL0_M_CLK : out std_logic;
FSL0_M_WRITE : out std_logic;
FSL0_M_DATA : out std_logic_vector(0 to 31);
FSL0_M_CONTROL : out std_logic;
FSL0_M_FULL : in std_logic;
FSL1_S_CLK : out std_logic;
FSL1_S_READ : out std_logic;
FSL1_S_DATA : in std_logic_vector(0 to 31);
FSL1_S_CONTROL : in std_logic;
FSL1_S_EXISTS : in std_logic;
FSL1_M_CLK : out std_logic;
FSL1_M_WRITE : out std_logic;
FSL1_M_DATA : out std_logic_vector(0 to 31);
FSL1_M_CONTROL : out std_logic;
FSL1_M_FULL : in std_logic;
FSL2_S_CLK : out std_logic;
FSL2_S_READ : out std_logic;
FSL2_S_DATA : in std_logic_vector(0 to 31);
FSL2_S_CONTROL : in std_logic;
FSL2_S_EXISTS : in std_logic;
FSL2_M_CLK : out std_logic;
FSL2_M_WRITE : out std_logic;
FSL2_M_DATA : out std_logic_vector(0 to 31);
FSL2_M_CONTROL : out std_logic;
FSL2_M_FULL : in std_logic;
FSL3_S_CLK : out std_logic;
FSL3_S_READ : out std_logic;
FSL3_S_DATA : in std_logic_vector(0 to 31);
FSL3_S_CONTROL : in std_logic;
FSL3_S_EXISTS : in std_logic;
FSL3_M_CLK : out std_logic;
FSL3_M_WRITE : out std_logic;
FSL3_M_DATA : out std_logic_vector(0 to 31);
FSL3_M_CONTROL : out std_logic;
FSL3_M_FULL : in std_logic;
FSL4_S_CLK : out std_logic;
FSL4_S_READ : out std_logic;
FSL4_S_DATA : in std_logic_vector(0 to 31);
FSL4_S_CONTROL : in std_logic;
FSL4_S_EXISTS : in std_logic;
FSL4_M_CLK : out std_logic;
FSL4_M_WRITE : out std_logic;
FSL4_M_DATA : out std_logic_vector(0 to 31);
FSL4_M_CONTROL : out std_logic;
FSL4_M_FULL : in std_logic;
FSL5_S_CLK : out std_logic;
FSL5_S_READ : out std_logic;
FSL5_S_DATA : in std_logic_vector(0 to 31);
FSL5_S_CONTROL : in std_logic;
FSL5_S_EXISTS : in std_logic;
FSL5_M_CLK : out std_logic;
FSL5_M_WRITE : out std_logic;
FSL5_M_DATA : out std_logic_vector(0 to 31);
FSL5_M_CONTROL : out std_logic;
FSL5_M_FULL : in std_logic;
FSL6_S_CLK : out std_logic;
FSL6_S_READ : out std_logic;
FSL6_S_DATA : in std_logic_vector(0 to 31);
FSL6_S_CONTROL : in std_logic;
FSL6_S_EXISTS : in std_logic;
FSL6_M_CLK : out std_logic;
FSL6_M_WRITE : out std_logic;
FSL6_M_DATA : out std_logic_vector(0 to 31);
FSL6_M_CONTROL : out std_logic;
FSL6_M_FULL : in std_logic;
FSL7_S_CLK : out std_logic;
FSL7_S_READ : out std_logic;
FSL7_S_DATA : in std_logic_vector(0 to 31);
FSL7_S_CONTROL : in std_logic;
FSL7_S_EXISTS : in std_logic;
FSL7_M_CLK : out std_logic;
FSL7_M_WRITE : out std_logic;
FSL7_M_DATA : out std_logic_vector(0 to 31);
FSL7_M_CONTROL : out std_logic;
FSL7_M_FULL : in std_logic;
FSL8_S_CLK : out std_logic;
FSL8_S_READ : out std_logic;
FSL8_S_DATA : in std_logic_vector(0 to 31);
FSL8_S_CONTROL : in std_logic;
FSL8_S_EXISTS : in std_logic;
FSL8_M_CLK : out std_logic;
FSL8_M_WRITE : out std_logic;
FSL8_M_DATA : out std_logic_vector(0 to 31);
FSL8_M_CONTROL : out std_logic;
FSL8_M_FULL : in std_logic;
FSL9_S_CLK : out std_logic;
FSL9_S_READ : out std_logic;
FSL9_S_DATA : in std_logic_vector(0 to 31);
FSL9_S_CONTROL : in std_logic;
FSL9_S_EXISTS : in std_logic;
FSL9_M_CLK : out std_logic;
FSL9_M_WRITE : out std_logic;
FSL9_M_DATA : out std_logic_vector(0 to 31);
FSL9_M_CONTROL : out std_logic;
FSL9_M_FULL : in std_logic;
FSL10_S_CLK : out std_logic;
FSL10_S_READ : out std_logic;
FSL10_S_DATA : in std_logic_vector(0 to 31);
FSL10_S_CONTROL : in std_logic;
FSL10_S_EXISTS : in std_logic;
FSL10_M_CLK : out std_logic;
FSL10_M_WRITE : out std_logic;
FSL10_M_DATA : out std_logic_vector(0 to 31);
FSL10_M_CONTROL : out std_logic;
FSL10_M_FULL : in std_logic;
FSL11_S_CLK : out std_logic;
FSL11_S_READ : out std_logic;
FSL11_S_DATA : in std_logic_vector(0 to 31);
FSL11_S_CONTROL : in std_logic;
FSL11_S_EXISTS : in std_logic;
FSL11_M_CLK : out std_logic;
FSL11_M_WRITE : out std_logic;
FSL11_M_DATA : out std_logic_vector(0 to 31);
FSL11_M_CONTROL : out std_logic;
FSL11_M_FULL : in std_logic;
FSL12_S_CLK : out std_logic;
FSL12_S_READ : out std_logic;
FSL12_S_DATA : in std_logic_vector(0 to 31);
FSL12_S_CONTROL : in std_logic;
FSL12_S_EXISTS : in std_logic;
FSL12_M_CLK : out std_logic;
FSL12_M_WRITE : out std_logic;
FSL12_M_DATA : out std_logic_vector(0 to 31);
FSL12_M_CONTROL : out std_logic;
FSL12_M_FULL : in std_logic;
FSL13_S_CLK : out std_logic;
FSL13_S_READ : out std_logic;
FSL13_S_DATA : in std_logic_vector(0 to 31);
FSL13_S_CONTROL : in std_logic;
FSL13_S_EXISTS : in std_logic;
FSL13_M_CLK : out std_logic;
FSL13_M_WRITE : out std_logic;
FSL13_M_DATA : out std_logic_vector(0 to 31);
FSL13_M_CONTROL : out std_logic;
FSL13_M_FULL : in std_logic;
FSL14_S_CLK : out std_logic;
FSL14_S_READ : out std_logic;
FSL14_S_DATA : in std_logic_vector(0 to 31);
FSL14_S_CONTROL : in std_logic;
FSL14_S_EXISTS : in std_logic;
FSL14_M_CLK : out std_logic;
FSL14_M_WRITE : out std_logic;
FSL14_M_DATA : out std_logic_vector(0 to 31);
FSL14_M_CONTROL : out std_logic;
FSL14_M_FULL : in std_logic;
FSL15_S_CLK : out std_logic;
FSL15_S_READ : out std_logic;
FSL15_S_DATA : in std_logic_vector(0 to 31);
FSL15_S_CONTROL : in std_logic;
FSL15_S_EXISTS : in std_logic;
FSL15_M_CLK : out std_logic;
FSL15_M_WRITE : out std_logic;
FSL15_M_DATA : out std_logic_vector(0 to 31);
FSL15_M_CONTROL : out std_logic;
FSL15_M_FULL : in std_logic;
M0_AXIS_TLAST : out std_logic;
M0_AXIS_TDATA : out std_logic_vector(31 downto 0);
M0_AXIS_TVALID : out std_logic;
M0_AXIS_TREADY : in std_logic;
S0_AXIS_TLAST : in std_logic;
S0_AXIS_TDATA : in std_logic_vector(31 downto 0);
S0_AXIS_TVALID : in std_logic;
S0_AXIS_TREADY : out std_logic;
M1_AXIS_TLAST : out std_logic;
M1_AXIS_TDATA : out std_logic_vector(31 downto 0);
M1_AXIS_TVALID : out std_logic;
M1_AXIS_TREADY : in std_logic;
S1_AXIS_TLAST : in std_logic;
S1_AXIS_TDATA : in std_logic_vector(31 downto 0);
S1_AXIS_TVALID : in std_logic;
S1_AXIS_TREADY : out std_logic;
M2_AXIS_TLAST : out std_logic;
M2_AXIS_TDATA : out std_logic_vector(31 downto 0);
M2_AXIS_TVALID : out std_logic;
M2_AXIS_TREADY : in std_logic;
S2_AXIS_TLAST : in std_logic;
S2_AXIS_TDATA : in std_logic_vector(31 downto 0);
S2_AXIS_TVALID : in std_logic;
S2_AXIS_TREADY : out std_logic;
M3_AXIS_TLAST : out std_logic;
M3_AXIS_TDATA : out std_logic_vector(31 downto 0);
M3_AXIS_TVALID : out std_logic;
M3_AXIS_TREADY : in std_logic;
S3_AXIS_TLAST : in std_logic;
S3_AXIS_TDATA : in std_logic_vector(31 downto 0);
S3_AXIS_TVALID : in std_logic;
S3_AXIS_TREADY : out std_logic;
M4_AXIS_TLAST : out std_logic;
M4_AXIS_TDATA : out std_logic_vector(31 downto 0);
M4_AXIS_TVALID : out std_logic;
M4_AXIS_TREADY : in std_logic;
S4_AXIS_TLAST : in std_logic;
S4_AXIS_TDATA : in std_logic_vector(31 downto 0);
S4_AXIS_TVALID : in std_logic;
S4_AXIS_TREADY : out std_logic;
M5_AXIS_TLAST : out std_logic;
M5_AXIS_TDATA : out std_logic_vector(31 downto 0);
M5_AXIS_TVALID : out std_logic;
M5_AXIS_TREADY : in std_logic;
S5_AXIS_TLAST : in std_logic;
S5_AXIS_TDATA : in std_logic_vector(31 downto 0);
S5_AXIS_TVALID : in std_logic;
S5_AXIS_TREADY : out std_logic;
M6_AXIS_TLAST : out std_logic;
M6_AXIS_TDATA : out std_logic_vector(31 downto 0);
M6_AXIS_TVALID : out std_logic;
M6_AXIS_TREADY : in std_logic;
S6_AXIS_TLAST : in std_logic;
S6_AXIS_TDATA : in std_logic_vector(31 downto 0);
S6_AXIS_TVALID : in std_logic;
S6_AXIS_TREADY : out std_logic;
M7_AXIS_TLAST : out std_logic;
M7_AXIS_TDATA : out std_logic_vector(31 downto 0);
M7_AXIS_TVALID : out std_logic;
M7_AXIS_TREADY : in std_logic;
S7_AXIS_TLAST : in std_logic;
S7_AXIS_TDATA : in std_logic_vector(31 downto 0);
S7_AXIS_TVALID : in std_logic;
S7_AXIS_TREADY : out std_logic;
M8_AXIS_TLAST : out std_logic;
M8_AXIS_TDATA : out std_logic_vector(31 downto 0);
M8_AXIS_TVALID : out std_logic;
M8_AXIS_TREADY : in std_logic;
S8_AXIS_TLAST : in std_logic;
S8_AXIS_TDATA : in std_logic_vector(31 downto 0);
S8_AXIS_TVALID : in std_logic;
S8_AXIS_TREADY : out std_logic;
M9_AXIS_TLAST : out std_logic;
M9_AXIS_TDATA : out std_logic_vector(31 downto 0);
M9_AXIS_TVALID : out std_logic;
M9_AXIS_TREADY : in std_logic;
S9_AXIS_TLAST : in std_logic;
S9_AXIS_TDATA : in std_logic_vector(31 downto 0);
S9_AXIS_TVALID : in std_logic;
S9_AXIS_TREADY : out std_logic;
M10_AXIS_TLAST : out std_logic;
M10_AXIS_TDATA : out std_logic_vector(31 downto 0);
M10_AXIS_TVALID : out std_logic;
M10_AXIS_TREADY : in std_logic;
S10_AXIS_TLAST : in std_logic;
S10_AXIS_TDATA : in std_logic_vector(31 downto 0);
S10_AXIS_TVALID : in std_logic;
S10_AXIS_TREADY : out std_logic;
M11_AXIS_TLAST : out std_logic;
M11_AXIS_TDATA : out std_logic_vector(31 downto 0);
M11_AXIS_TVALID : out std_logic;
M11_AXIS_TREADY : in std_logic;
S11_AXIS_TLAST : in std_logic;
S11_AXIS_TDATA : in std_logic_vector(31 downto 0);
S11_AXIS_TVALID : in std_logic;
S11_AXIS_TREADY : out std_logic;
M12_AXIS_TLAST : out std_logic;
M12_AXIS_TDATA : out std_logic_vector(31 downto 0);
M12_AXIS_TVALID : out std_logic;
M12_AXIS_TREADY : in std_logic;
S12_AXIS_TLAST : in std_logic;
S12_AXIS_TDATA : in std_logic_vector(31 downto 0);
S12_AXIS_TVALID : in std_logic;
S12_AXIS_TREADY : out std_logic;
M13_AXIS_TLAST : out std_logic;
M13_AXIS_TDATA : out std_logic_vector(31 downto 0);
M13_AXIS_TVALID : out std_logic;
M13_AXIS_TREADY : in std_logic;
S13_AXIS_TLAST : in std_logic;
S13_AXIS_TDATA : in std_logic_vector(31 downto 0);
S13_AXIS_TVALID : in std_logic;
S13_AXIS_TREADY : out std_logic;
M14_AXIS_TLAST : out std_logic;
M14_AXIS_TDATA : out std_logic_vector(31 downto 0);
M14_AXIS_TVALID : out std_logic;
M14_AXIS_TREADY : in std_logic;
S14_AXIS_TLAST : in std_logic;
S14_AXIS_TDATA : in std_logic_vector(31 downto 0);
S14_AXIS_TVALID : in std_logic;
S14_AXIS_TREADY : out std_logic;
M15_AXIS_TLAST : out std_logic;
M15_AXIS_TDATA : out std_logic_vector(31 downto 0);
M15_AXIS_TVALID : out std_logic;
M15_AXIS_TREADY : in std_logic;
S15_AXIS_TLAST : in std_logic;
S15_AXIS_TDATA : in std_logic_vector(31 downto 0);
S15_AXIS_TVALID : in std_logic;
S15_AXIS_TREADY : out std_logic;
ICACHE_FSL_IN_CLK : out std_logic;
ICACHE_FSL_IN_READ : out std_logic;
ICACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
ICACHE_FSL_IN_CONTROL : in std_logic;
ICACHE_FSL_IN_EXISTS : in std_logic;
ICACHE_FSL_OUT_CLK : out std_logic;
ICACHE_FSL_OUT_WRITE : out std_logic;
ICACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
ICACHE_FSL_OUT_CONTROL : out std_logic;
ICACHE_FSL_OUT_FULL : in std_logic;
DCACHE_FSL_IN_CLK : out std_logic;
DCACHE_FSL_IN_READ : out std_logic;
DCACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
DCACHE_FSL_IN_CONTROL : in std_logic;
DCACHE_FSL_IN_EXISTS : in std_logic;
DCACHE_FSL_OUT_CLK : out std_logic;
DCACHE_FSL_OUT_WRITE : out std_logic;
DCACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
DCACHE_FSL_OUT_CONTROL : out std_logic;
DCACHE_FSL_OUT_FULL : in std_logic
);
end component;
component system_mb_plb_wrapper is
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to 11);
MPLB_Rst : out std_logic_vector(0 to 5);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to 31);
DCR_ABus : in std_logic_vector(0 to 9);
DCR_DBus : in std_logic_vector(0 to 31);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to 191);
M_UABus : in std_logic_vector(0 to 191);
M_BE : in std_logic_vector(0 to 47);
M_RNW : in std_logic_vector(0 to 5);
M_abort : in std_logic_vector(0 to 5);
M_busLock : in std_logic_vector(0 to 5);
M_TAttribute : in std_logic_vector(0 to 95);
M_lockErr : in std_logic_vector(0 to 5);
M_MSize : in std_logic_vector(0 to 11);
M_priority : in std_logic_vector(0 to 11);
M_rdBurst : in std_logic_vector(0 to 5);
M_request : in std_logic_vector(0 to 5);
M_size : in std_logic_vector(0 to 23);
M_type : in std_logic_vector(0 to 17);
M_wrBurst : in std_logic_vector(0 to 5);
M_wrDBus : in std_logic_vector(0 to 383);
Sl_addrAck : in std_logic_vector(0 to 11);
Sl_MRdErr : in std_logic_vector(0 to 71);
Sl_MWrErr : in std_logic_vector(0 to 71);
Sl_MBusy : in std_logic_vector(0 to 71);
Sl_rdBTerm : in std_logic_vector(0 to 11);
Sl_rdComp : in std_logic_vector(0 to 11);
Sl_rdDAck : in std_logic_vector(0 to 11);
Sl_rdDBus : in std_logic_vector(0 to 767);
Sl_rdWdAddr : in std_logic_vector(0 to 47);
Sl_rearbitrate : in std_logic_vector(0 to 11);
Sl_SSize : in std_logic_vector(0 to 23);
Sl_wait : in std_logic_vector(0 to 11);
Sl_wrBTerm : in std_logic_vector(0 to 11);
Sl_wrComp : in std_logic_vector(0 to 11);
Sl_wrDAck : in std_logic_vector(0 to 11);
Sl_MIRQ : in std_logic_vector(0 to 71);
PLB_MIRQ : out std_logic_vector(0 to 5);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to 7);
PLB_MAddrAck : out std_logic_vector(0 to 5);
PLB_MTimeout : out std_logic_vector(0 to 5);
PLB_MBusy : out std_logic_vector(0 to 5);
PLB_MRdErr : out std_logic_vector(0 to 5);
PLB_MWrErr : out std_logic_vector(0 to 5);
PLB_MRdBTerm : out std_logic_vector(0 to 5);
PLB_MRdDAck : out std_logic_vector(0 to 5);
PLB_MRdDBus : out std_logic_vector(0 to 383);
PLB_MRdWdAddr : out std_logic_vector(0 to 23);
PLB_MRearbitrate : out std_logic_vector(0 to 5);
PLB_MWrBTerm : out std_logic_vector(0 to 5);
PLB_MWrDAck : out std_logic_vector(0 to 5);
PLB_MSSize : out std_logic_vector(0 to 11);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to 2);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to 11);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to 63);
PLB_wrPrim : out std_logic_vector(0 to 11);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to 5);
PLB_SMWrErr : out std_logic_vector(0 to 5);
PLB_SMBusy : out std_logic_vector(0 to 5);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to 63);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
Bus_Error_Det : out std_logic
);
end component;
component system_ilmb_wrapper is
port (
LMB_Clk : in std_logic;
SYS_Rst : in std_logic;
LMB_Rst : out std_logic;
M_ABus : in std_logic_vector(0 to 31);
M_ReadStrobe : in std_logic;
M_WriteStrobe : in std_logic;
M_AddrStrobe : in std_logic;
M_DBus : in std_logic_vector(0 to 31);
M_BE : in std_logic_vector(0 to 3);
Sl_DBus : in std_logic_vector(0 to 31);
Sl_Ready : in std_logic_vector(0 to 0);
Sl_Wait : in std_logic_vector(0 to 0);
Sl_UE : in std_logic_vector(0 to 0);
Sl_CE : in std_logic_vector(0 to 0);
LMB_ABus : out std_logic_vector(0 to 31);
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_AddrStrobe : out std_logic;
LMB_ReadDBus : out std_logic_vector(0 to 31);
LMB_WriteDBus : out std_logic_vector(0 to 31);
LMB_Ready : out std_logic;
LMB_Wait : out std_logic;
LMB_UE : out std_logic;
LMB_CE : out std_logic;
LMB_BE : out std_logic_vector(0 to 3)
);
end component;
component system_dlmb_wrapper is
port (
LMB_Clk : in std_logic;
SYS_Rst : in std_logic;
LMB_Rst : out std_logic;
M_ABus : in std_logic_vector(0 to 31);
M_ReadStrobe : in std_logic;
M_WriteStrobe : in std_logic;
M_AddrStrobe : in std_logic;
M_DBus : in std_logic_vector(0 to 31);
M_BE : in std_logic_vector(0 to 3);
Sl_DBus : in std_logic_vector(0 to 31);
Sl_Ready : in std_logic_vector(0 to 0);
Sl_Wait : in std_logic_vector(0 to 0);
Sl_UE : in std_logic_vector(0 to 0);
Sl_CE : in std_logic_vector(0 to 0);
LMB_ABus : out std_logic_vector(0 to 31);
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_AddrStrobe : out std_logic;
LMB_ReadDBus : out std_logic_vector(0 to 31);
LMB_WriteDBus : out std_logic_vector(0 to 31);
LMB_Ready : out std_logic;
LMB_Wait : out std_logic;
LMB_UE : out std_logic;
LMB_CE : out std_logic;
LMB_BE : out std_logic_vector(0 to 3)
);
end component;
component system_dlmb_cntlr_wrapper is
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
LMB_ABus : in std_logic_vector(0 to 31);
LMB_WriteDBus : in std_logic_vector(0 to 31);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to 3);
Sl_DBus : out std_logic_vector(0 to 31);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
LMB1_ABus : in std_logic_vector(0 to 31);
LMB1_WriteDBus : in std_logic_vector(0 to 31);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to 3);
Sl1_DBus : out std_logic_vector(0 to 31);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
LMB2_ABus : in std_logic_vector(0 to 31);
LMB2_WriteDBus : in std_logic_vector(0 to 31);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to 3);
Sl2_DBus : out std_logic_vector(0 to 31);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
LMB3_ABus : in std_logic_vector(0 to 31);
LMB3_WriteDBus : in std_logic_vector(0 to 31);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to 3);
Sl3_DBus : out std_logic_vector(0 to 31);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to 3);
BRAM_Addr_A : out std_logic_vector(0 to 31);
BRAM_Din_A : in std_logic_vector(0 to 31);
BRAM_Dout_A : out std_logic_vector(0 to 31);
Interrupt : out std_logic;
UE : out std_logic;
CE : out std_logic;
SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_PAValid : in std_logic;
SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to 0);
SPLB_CTRL_PLB_RNW : in std_logic;
SPLB_CTRL_PLB_BE : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2);
SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to 31);
SPLB_CTRL_Sl_addrAck : out std_logic;
SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1);
SPLB_CTRL_Sl_wait : out std_logic;
SPLB_CTRL_Sl_rearbitrate : out std_logic;
SPLB_CTRL_Sl_wrDAck : out std_logic;
SPLB_CTRL_Sl_wrComp : out std_logic;
SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to 31);
SPLB_CTRL_Sl_rdDAck : out std_logic;
SPLB_CTRL_Sl_rdComp : out std_logic;
SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to 0);
SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_SAValid : in std_logic;
SPLB_CTRL_PLB_rdPrim : in std_logic;
SPLB_CTRL_PLB_wrPrim : in std_logic;
SPLB_CTRL_PLB_abort : in std_logic;
SPLB_CTRL_PLB_busLock : in std_logic;
SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_lockErr : in std_logic;
SPLB_CTRL_PLB_wrBurst : in std_logic;
SPLB_CTRL_PLB_rdBurst : in std_logic;
SPLB_CTRL_PLB_wrPendReq : in std_logic;
SPLB_CTRL_PLB_rdPendReq : in std_logic;
SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB_CTRL_Sl_wrBTerm : out std_logic;
SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB_CTRL_Sl_rdBTerm : out std_logic;
SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to 0);
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic
);
end component;
component system_ilmb_cntlr_wrapper is
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
LMB_ABus : in std_logic_vector(0 to 31);
LMB_WriteDBus : in std_logic_vector(0 to 31);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to 3);
Sl_DBus : out std_logic_vector(0 to 31);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
LMB1_ABus : in std_logic_vector(0 to 31);
LMB1_WriteDBus : in std_logic_vector(0 to 31);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to 3);
Sl1_DBus : out std_logic_vector(0 to 31);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
LMB2_ABus : in std_logic_vector(0 to 31);
LMB2_WriteDBus : in std_logic_vector(0 to 31);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to 3);
Sl2_DBus : out std_logic_vector(0 to 31);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
LMB3_ABus : in std_logic_vector(0 to 31);
LMB3_WriteDBus : in std_logic_vector(0 to 31);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to 3);
Sl3_DBus : out std_logic_vector(0 to 31);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to 3);
BRAM_Addr_A : out std_logic_vector(0 to 31);
BRAM_Din_A : in std_logic_vector(0 to 31);
BRAM_Dout_A : out std_logic_vector(0 to 31);
Interrupt : out std_logic;
UE : out std_logic;
CE : out std_logic;
SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_PAValid : in std_logic;
SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to 0);
SPLB_CTRL_PLB_RNW : in std_logic;
SPLB_CTRL_PLB_BE : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2);
SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to 31);
SPLB_CTRL_Sl_addrAck : out std_logic;
SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1);
SPLB_CTRL_Sl_wait : out std_logic;
SPLB_CTRL_Sl_rearbitrate : out std_logic;
SPLB_CTRL_Sl_wrDAck : out std_logic;
SPLB_CTRL_Sl_wrComp : out std_logic;
SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to 31);
SPLB_CTRL_Sl_rdDAck : out std_logic;
SPLB_CTRL_Sl_rdComp : out std_logic;
SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to 0);
SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_SAValid : in std_logic;
SPLB_CTRL_PLB_rdPrim : in std_logic;
SPLB_CTRL_PLB_wrPrim : in std_logic;
SPLB_CTRL_PLB_abort : in std_logic;
SPLB_CTRL_PLB_busLock : in std_logic;
SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_lockErr : in std_logic;
SPLB_CTRL_PLB_wrBurst : in std_logic;
SPLB_CTRL_PLB_rdBurst : in std_logic;
SPLB_CTRL_PLB_wrPendReq : in std_logic;
SPLB_CTRL_PLB_rdPendReq : in std_logic;
SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB_CTRL_Sl_wrBTerm : out std_logic;
SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB_CTRL_Sl_rdBTerm : out std_logic;
SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to 0);
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic
);
end component;
component system_lmb_bram_wrapper is
port (
BRAM_Rst_A : in std_logic;
BRAM_Clk_A : in std_logic;
BRAM_EN_A : in std_logic;
BRAM_WEN_A : in std_logic_vector(0 to 3);
BRAM_Addr_A : in std_logic_vector(0 to 31);
BRAM_Din_A : out std_logic_vector(0 to 31);
BRAM_Dout_A : in std_logic_vector(0 to 31);
BRAM_Rst_B : in std_logic;
BRAM_Clk_B : in std_logic;
BRAM_EN_B : in std_logic;
BRAM_WEN_B : in std_logic_vector(0 to 3);
BRAM_Addr_B : in std_logic_vector(0 to 31);
BRAM_Din_B : out std_logic_vector(0 to 31);
BRAM_Dout_B : in std_logic_vector(0 to 31)
);
end component;
component system_ddr2_sdram_wrapper is
port (
FSL0_M_Clk : in std_logic;
FSL0_M_Write : in std_logic;
FSL0_M_Data : in std_logic_vector(0 to 31);
FSL0_M_Control : in std_logic;
FSL0_M_Full : out std_logic;
FSL0_S_Clk : in std_logic;
FSL0_S_Read : in std_logic;
FSL0_S_Data : out std_logic_vector(0 to 31);
FSL0_S_Control : out std_logic;
FSL0_S_Exists : out std_logic;
FSL0_B_M_Clk : in std_logic;
FSL0_B_M_Write : in std_logic;
FSL0_B_M_Data : in std_logic_vector(0 to 31);
FSL0_B_M_Control : in std_logic;
FSL0_B_M_Full : out std_logic;
FSL0_B_S_Clk : in std_logic;
FSL0_B_S_Read : in std_logic;
FSL0_B_S_Data : out std_logic_vector(0 to 31);
FSL0_B_S_Control : out std_logic;
FSL0_B_S_Exists : out std_logic;
SPLB0_Clk : in std_logic;
SPLB0_Rst : in std_logic;
SPLB0_PLB_ABus : in std_logic_vector(0 to 31);
SPLB0_PLB_PAValid : in std_logic;
SPLB0_PLB_SAValid : in std_logic;
SPLB0_PLB_masterID : in std_logic_vector(0 to 2);
SPLB0_PLB_RNW : in std_logic;
SPLB0_PLB_BE : in std_logic_vector(0 to 7);
SPLB0_PLB_UABus : in std_logic_vector(0 to 31);
SPLB0_PLB_rdPrim : in std_logic;
SPLB0_PLB_wrPrim : in std_logic;
SPLB0_PLB_abort : in std_logic;
SPLB0_PLB_busLock : in std_logic;
SPLB0_PLB_MSize : in std_logic_vector(0 to 1);
SPLB0_PLB_size : in std_logic_vector(0 to 3);
SPLB0_PLB_type : in std_logic_vector(0 to 2);
SPLB0_PLB_lockErr : in std_logic;
SPLB0_PLB_wrPendReq : in std_logic;
SPLB0_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB0_PLB_rdPendReq : in std_logic;
SPLB0_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB0_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB0_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB0_PLB_rdBurst : in std_logic;
SPLB0_PLB_wrBurst : in std_logic;
SPLB0_PLB_wrDBus : in std_logic_vector(0 to 63);
SPLB0_Sl_addrAck : out std_logic;
SPLB0_Sl_SSize : out std_logic_vector(0 to 1);
SPLB0_Sl_wait : out std_logic;
SPLB0_Sl_rearbitrate : out std_logic;
SPLB0_Sl_wrDAck : out std_logic;
SPLB0_Sl_wrComp : out std_logic;
SPLB0_Sl_wrBTerm : out std_logic;
SPLB0_Sl_rdDBus : out std_logic_vector(0 to 63);
SPLB0_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB0_Sl_rdDAck : out std_logic;
SPLB0_Sl_rdComp : out std_logic;
SPLB0_Sl_rdBTerm : out std_logic;
SPLB0_Sl_MBusy : out std_logic_vector(0 to 5);
SPLB0_Sl_MRdErr : out std_logic_vector(0 to 5);
SPLB0_Sl_MWrErr : out std_logic_vector(0 to 5);
SPLB0_Sl_MIRQ : out std_logic_vector(0 to 5);
SDMA0_Clk : in std_logic;
SDMA0_Rx_IntOut : out std_logic;
SDMA0_Tx_IntOut : out std_logic;
SDMA0_RstOut : out std_logic;
SDMA0_TX_D : out std_logic_vector(0 to 31);
SDMA0_TX_Rem : out std_logic_vector(0 to 3);
SDMA0_TX_SOF : out std_logic;
SDMA0_TX_EOF : out std_logic;
SDMA0_TX_SOP : out std_logic;
SDMA0_TX_EOP : out std_logic;
SDMA0_TX_Src_Rdy : out std_logic;
SDMA0_TX_Dst_Rdy : in std_logic;
SDMA0_RX_D : in std_logic_vector(0 to 31);
SDMA0_RX_Rem : in std_logic_vector(0 to 3);
SDMA0_RX_SOF : in std_logic;
SDMA0_RX_EOF : in std_logic;
SDMA0_RX_SOP : in std_logic;
SDMA0_RX_EOP : in std_logic;
SDMA0_RX_Src_Rdy : in std_logic;
SDMA0_RX_Dst_Rdy : out std_logic;
SDMA_CTRL0_Clk : in std_logic;
SDMA_CTRL0_Rst : in std_logic;
SDMA_CTRL0_PLB_ABus : in std_logic_vector(0 to 31);
SDMA_CTRL0_PLB_PAValid : in std_logic;
SDMA_CTRL0_PLB_SAValid : in std_logic;
SDMA_CTRL0_PLB_masterID : in std_logic_vector(0 to 0);
SDMA_CTRL0_PLB_RNW : in std_logic;
SDMA_CTRL0_PLB_BE : in std_logic_vector(0 to 7);
SDMA_CTRL0_PLB_UABus : in std_logic_vector(0 to 31);
SDMA_CTRL0_PLB_rdPrim : in std_logic;
SDMA_CTRL0_PLB_wrPrim : in std_logic;
SDMA_CTRL0_PLB_abort : in std_logic;
SDMA_CTRL0_PLB_busLock : in std_logic;
SDMA_CTRL0_PLB_MSize : in std_logic_vector(0 to 1);
SDMA_CTRL0_PLB_size : in std_logic_vector(0 to 3);
SDMA_CTRL0_PLB_type : in std_logic_vector(0 to 2);
SDMA_CTRL0_PLB_lockErr : in std_logic;
SDMA_CTRL0_PLB_wrPendReq : in std_logic;
SDMA_CTRL0_PLB_wrPendPri : in std_logic_vector(0 to 1);
SDMA_CTRL0_PLB_rdPendReq : in std_logic;
SDMA_CTRL0_PLB_rdPendPri : in std_logic_vector(0 to 1);
SDMA_CTRL0_PLB_reqPri : in std_logic_vector(0 to 1);
SDMA_CTRL0_PLB_TAttribute : in std_logic_vector(0 to 15);
SDMA_CTRL0_PLB_rdBurst : in std_logic;
SDMA_CTRL0_PLB_wrBurst : in std_logic;
SDMA_CTRL0_PLB_wrDBus : in std_logic_vector(0 to 63);
SDMA_CTRL0_Sl_addrAck : out std_logic;
SDMA_CTRL0_Sl_SSize : out std_logic_vector(0 to 1);
SDMA_CTRL0_Sl_wait : out std_logic;
SDMA_CTRL0_Sl_rearbitrate : out std_logic;
SDMA_CTRL0_Sl_wrDAck : out std_logic;
SDMA_CTRL0_Sl_wrComp : out std_logic;
SDMA_CTRL0_Sl_wrBTerm : out std_logic;
SDMA_CTRL0_Sl_rdDBus : out std_logic_vector(0 to 63);
SDMA_CTRL0_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SDMA_CTRL0_Sl_rdDAck : out std_logic;
SDMA_CTRL0_Sl_rdComp : out std_logic;
SDMA_CTRL0_Sl_rdBTerm : out std_logic;
SDMA_CTRL0_Sl_MBusy : out std_logic_vector(0 to 0);
SDMA_CTRL0_Sl_MRdErr : out std_logic_vector(0 to 0);
SDMA_CTRL0_Sl_MWrErr : out std_logic_vector(0 to 0);
SDMA_CTRL0_Sl_MIRQ : out std_logic_vector(0 to 0);
PIM0_Addr : in std_logic_vector(31 downto 0);
PIM0_AddrReq : in std_logic;
PIM0_AddrAck : out std_logic;
PIM0_RNW : in std_logic;
PIM0_Size : in std_logic_vector(3 downto 0);
PIM0_RdModWr : in std_logic;
PIM0_WrFIFO_Data : in std_logic_vector(63 downto 0);
PIM0_WrFIFO_BE : in std_logic_vector(7 downto 0);
PIM0_WrFIFO_Push : in std_logic;
PIM0_RdFIFO_Data : out std_logic_vector(63 downto 0);
PIM0_RdFIFO_Pop : in std_logic;
PIM0_RdFIFO_RdWdAddr : out std_logic_vector(3 downto 0);
PIM0_WrFIFO_Empty : out std_logic;
PIM0_WrFIFO_AlmostFull : out std_logic;
PIM0_WrFIFO_Flush : in std_logic;
PIM0_RdFIFO_Empty : out std_logic;
PIM0_RdFIFO_Flush : in std_logic;
PIM0_RdFIFO_Latency : out std_logic_vector(1 downto 0);
PIM0_InitDone : out std_logic;
PPC440MC0_MIMCReadNotWrite : in std_logic;
PPC440MC0_MIMCAddress : in std_logic_vector(0 to 35);
PPC440MC0_MIMCAddressValid : in std_logic;
PPC440MC0_MIMCWriteData : in std_logic_vector(0 to 127);
PPC440MC0_MIMCWriteDataValid : in std_logic;
PPC440MC0_MIMCByteEnable : in std_logic_vector(0 to 15);
PPC440MC0_MIMCBankConflict : in std_logic;
PPC440MC0_MIMCRowConflict : in std_logic;
PPC440MC0_MCMIReadData : out std_logic_vector(0 to 127);
PPC440MC0_MCMIReadDataValid : out std_logic;
PPC440MC0_MCMIReadDataErr : out std_logic;
PPC440MC0_MCMIAddrReadyToAccept : out std_logic;
VFBC0_Cmd_Clk : in std_logic;
VFBC0_Cmd_Reset : in std_logic;
VFBC0_Cmd_Data : in std_logic_vector(31 downto 0);
VFBC0_Cmd_Write : in std_logic;
VFBC0_Cmd_End : in std_logic;
VFBC0_Cmd_Full : out std_logic;
VFBC0_Cmd_Almost_Full : out std_logic;
VFBC0_Cmd_Idle : out std_logic;
VFBC0_Wd_Clk : in std_logic;
VFBC0_Wd_Reset : in std_logic;
VFBC0_Wd_Write : in std_logic;
VFBC0_Wd_End_Burst : in std_logic;
VFBC0_Wd_Flush : in std_logic;
VFBC0_Wd_Data : in std_logic_vector(31 downto 0);
VFBC0_Wd_Data_BE : in std_logic_vector(3 downto 0);
VFBC0_Wd_Full : out std_logic;
VFBC0_Wd_Almost_Full : out std_logic;
VFBC0_Rd_Clk : in std_logic;
VFBC0_Rd_Reset : in std_logic;
VFBC0_Rd_Read : in std_logic;
VFBC0_Rd_End_Burst : in std_logic;
VFBC0_Rd_Flush : in std_logic;
VFBC0_Rd_Data : out std_logic_vector(31 downto 0);
VFBC0_Rd_Empty : out std_logic;
VFBC0_Rd_Almost_Empty : out std_logic;
MCB0_cmd_clk : in std_logic;
MCB0_cmd_en : in std_logic;
MCB0_cmd_instr : in std_logic_vector(2 downto 0);
MCB0_cmd_bl : in std_logic_vector(5 downto 0);
MCB0_cmd_byte_addr : in std_logic_vector(29 downto 0);
MCB0_cmd_empty : out std_logic;
MCB0_cmd_full : out std_logic;
MCB0_wr_clk : in std_logic;
MCB0_wr_en : in std_logic;
MCB0_wr_mask : in std_logic_vector(7 downto 0);
MCB0_wr_data : in std_logic_vector(63 downto 0);
MCB0_wr_full : out std_logic;
MCB0_wr_empty : out std_logic;
MCB0_wr_count : out std_logic_vector(6 downto 0);
MCB0_wr_underrun : out std_logic;
MCB0_wr_error : out std_logic;
MCB0_rd_clk : in std_logic;
MCB0_rd_en : in std_logic;
MCB0_rd_data : out std_logic_vector(63 downto 0);
MCB0_rd_full : out std_logic;
MCB0_rd_empty : out std_logic;
MCB0_rd_count : out std_logic_vector(6 downto 0);
MCB0_rd_overflow : out std_logic;
MCB0_rd_error : out std_logic;
FSL1_M_Clk : in std_logic;
FSL1_M_Write : in std_logic;
FSL1_M_Data : in std_logic_vector(0 to 31);
FSL1_M_Control : in std_logic;
FSL1_M_Full : out std_logic;
FSL1_S_Clk : in std_logic;
FSL1_S_Read : in std_logic;
FSL1_S_Data : out std_logic_vector(0 to 31);
FSL1_S_Control : out std_logic;
FSL1_S_Exists : out std_logic;
FSL1_B_M_Clk : in std_logic;
FSL1_B_M_Write : in std_logic;
FSL1_B_M_Data : in std_logic_vector(0 to 31);
FSL1_B_M_Control : in std_logic;
FSL1_B_M_Full : out std_logic;
FSL1_B_S_Clk : in std_logic;
FSL1_B_S_Read : in std_logic;
FSL1_B_S_Data : out std_logic_vector(0 to 31);
FSL1_B_S_Control : out std_logic;
FSL1_B_S_Exists : out std_logic;
SPLB1_Clk : in std_logic;
SPLB1_Rst : in std_logic;
SPLB1_PLB_ABus : in std_logic_vector(0 to 31);
SPLB1_PLB_PAValid : in std_logic;
SPLB1_PLB_SAValid : in std_logic;
SPLB1_PLB_masterID : in std_logic_vector(0 to 0);
SPLB1_PLB_RNW : in std_logic;
SPLB1_PLB_BE : in std_logic_vector(0 to 7);
SPLB1_PLB_UABus : in std_logic_vector(0 to 31);
SPLB1_PLB_rdPrim : in std_logic;
SPLB1_PLB_wrPrim : in std_logic;
SPLB1_PLB_abort : in std_logic;
SPLB1_PLB_busLock : in std_logic;
SPLB1_PLB_MSize : in std_logic_vector(0 to 1);
SPLB1_PLB_size : in std_logic_vector(0 to 3);
SPLB1_PLB_type : in std_logic_vector(0 to 2);
SPLB1_PLB_lockErr : in std_logic;
SPLB1_PLB_wrPendReq : in std_logic;
SPLB1_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB1_PLB_rdPendReq : in std_logic;
SPLB1_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB1_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB1_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB1_PLB_rdBurst : in std_logic;
SPLB1_PLB_wrBurst : in std_logic;
SPLB1_PLB_wrDBus : in std_logic_vector(0 to 63);
SPLB1_Sl_addrAck : out std_logic;
SPLB1_Sl_SSize : out std_logic_vector(0 to 1);
SPLB1_Sl_wait : out std_logic;
SPLB1_Sl_rearbitrate : out std_logic;
SPLB1_Sl_wrDAck : out std_logic;
SPLB1_Sl_wrComp : out std_logic;
SPLB1_Sl_wrBTerm : out std_logic;
SPLB1_Sl_rdDBus : out std_logic_vector(0 to 63);
SPLB1_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB1_Sl_rdDAck : out std_logic;
SPLB1_Sl_rdComp : out std_logic;
SPLB1_Sl_rdBTerm : out std_logic;
SPLB1_Sl_MBusy : out std_logic_vector(0 to 0);
SPLB1_Sl_MRdErr : out std_logic_vector(0 to 0);
SPLB1_Sl_MWrErr : out std_logic_vector(0 to 0);
SPLB1_Sl_MIRQ : out std_logic_vector(0 to 0);
SDMA1_Clk : in std_logic;
SDMA1_Rx_IntOut : out std_logic;
SDMA1_Tx_IntOut : out std_logic;
SDMA1_RstOut : out std_logic;
SDMA1_TX_D : out std_logic_vector(0 to 31);
SDMA1_TX_Rem : out std_logic_vector(0 to 3);
SDMA1_TX_SOF : out std_logic;
SDMA1_TX_EOF : out std_logic;
SDMA1_TX_SOP : out std_logic;
SDMA1_TX_EOP : out std_logic;
SDMA1_TX_Src_Rdy : out std_logic;
SDMA1_TX_Dst_Rdy : in std_logic;
SDMA1_RX_D : in std_logic_vector(0 to 31);
SDMA1_RX_Rem : in std_logic_vector(0 to 3);
SDMA1_RX_SOF : in std_logic;
SDMA1_RX_EOF : in std_logic;
SDMA1_RX_SOP : in std_logic;
SDMA1_RX_EOP : in std_logic;
SDMA1_RX_Src_Rdy : in std_logic;
SDMA1_RX_Dst_Rdy : out std_logic;
SDMA_CTRL1_Clk : in std_logic;
SDMA_CTRL1_Rst : in std_logic;
SDMA_CTRL1_PLB_ABus : in std_logic_vector(0 to 31);
SDMA_CTRL1_PLB_PAValid : in std_logic;
SDMA_CTRL1_PLB_SAValid : in std_logic;
SDMA_CTRL1_PLB_masterID : in std_logic_vector(0 to 0);
SDMA_CTRL1_PLB_RNW : in std_logic;
SDMA_CTRL1_PLB_BE : in std_logic_vector(0 to 7);
SDMA_CTRL1_PLB_UABus : in std_logic_vector(0 to 31);
SDMA_CTRL1_PLB_rdPrim : in std_logic;
SDMA_CTRL1_PLB_wrPrim : in std_logic;
SDMA_CTRL1_PLB_abort : in std_logic;
SDMA_CTRL1_PLB_busLock : in std_logic;
SDMA_CTRL1_PLB_MSize : in std_logic_vector(0 to 1);
SDMA_CTRL1_PLB_size : in std_logic_vector(0 to 3);
SDMA_CTRL1_PLB_type : in std_logic_vector(0 to 2);
SDMA_CTRL1_PLB_lockErr : in std_logic;
SDMA_CTRL1_PLB_wrPendReq : in std_logic;
SDMA_CTRL1_PLB_wrPendPri : in std_logic_vector(0 to 1);
SDMA_CTRL1_PLB_rdPendReq : in std_logic;
SDMA_CTRL1_PLB_rdPendPri : in std_logic_vector(0 to 1);
SDMA_CTRL1_PLB_reqPri : in std_logic_vector(0 to 1);
SDMA_CTRL1_PLB_TAttribute : in std_logic_vector(0 to 15);
SDMA_CTRL1_PLB_rdBurst : in std_logic;
SDMA_CTRL1_PLB_wrBurst : in std_logic;
SDMA_CTRL1_PLB_wrDBus : in std_logic_vector(0 to 63);
SDMA_CTRL1_Sl_addrAck : out std_logic;
SDMA_CTRL1_Sl_SSize : out std_logic_vector(0 to 1);
SDMA_CTRL1_Sl_wait : out std_logic;
SDMA_CTRL1_Sl_rearbitrate : out std_logic;
SDMA_CTRL1_Sl_wrDAck : out std_logic;
SDMA_CTRL1_Sl_wrComp : out std_logic;
SDMA_CTRL1_Sl_wrBTerm : out std_logic;
SDMA_CTRL1_Sl_rdDBus : out std_logic_vector(0 to 63);
SDMA_CTRL1_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SDMA_CTRL1_Sl_rdDAck : out std_logic;
SDMA_CTRL1_Sl_rdComp : out std_logic;
SDMA_CTRL1_Sl_rdBTerm : out std_logic;
SDMA_CTRL1_Sl_MBusy : out std_logic_vector(0 to 0);
SDMA_CTRL1_Sl_MRdErr : out std_logic_vector(0 to 0);
SDMA_CTRL1_Sl_MWrErr : out std_logic_vector(0 to 0);
SDMA_CTRL1_Sl_MIRQ : out std_logic_vector(0 to 0);
PIM1_Addr : in std_logic_vector(31 downto 0);
PIM1_AddrReq : in std_logic;
PIM1_AddrAck : out std_logic;
PIM1_RNW : in std_logic;
PIM1_Size : in std_logic_vector(3 downto 0);
PIM1_RdModWr : in std_logic;
PIM1_WrFIFO_Data : in std_logic_vector(63 downto 0);
PIM1_WrFIFO_BE : in std_logic_vector(7 downto 0);
PIM1_WrFIFO_Push : in std_logic;
PIM1_RdFIFO_Data : out std_logic_vector(63 downto 0);
PIM1_RdFIFO_Pop : in std_logic;
PIM1_RdFIFO_RdWdAddr : out std_logic_vector(3 downto 0);
PIM1_WrFIFO_Empty : out std_logic;
PIM1_WrFIFO_AlmostFull : out std_logic;
PIM1_WrFIFO_Flush : in std_logic;
PIM1_RdFIFO_Empty : out std_logic;
PIM1_RdFIFO_Flush : in std_logic;
PIM1_RdFIFO_Latency : out std_logic_vector(1 downto 0);
PIM1_InitDone : out std_logic;
PPC440MC1_MIMCReadNotWrite : in std_logic;
PPC440MC1_MIMCAddress : in std_logic_vector(0 to 35);
PPC440MC1_MIMCAddressValid : in std_logic;
PPC440MC1_MIMCWriteData : in std_logic_vector(0 to 127);
PPC440MC1_MIMCWriteDataValid : in std_logic;
PPC440MC1_MIMCByteEnable : in std_logic_vector(0 to 15);
PPC440MC1_MIMCBankConflict : in std_logic;
PPC440MC1_MIMCRowConflict : in std_logic;
PPC440MC1_MCMIReadData : out std_logic_vector(0 to 127);
PPC440MC1_MCMIReadDataValid : out std_logic;
PPC440MC1_MCMIReadDataErr : out std_logic;
PPC440MC1_MCMIAddrReadyToAccept : out std_logic;
VFBC1_Cmd_Clk : in std_logic;
VFBC1_Cmd_Reset : in std_logic;
VFBC1_Cmd_Data : in std_logic_vector(31 downto 0);
VFBC1_Cmd_Write : in std_logic;
VFBC1_Cmd_End : in std_logic;
VFBC1_Cmd_Full : out std_logic;
VFBC1_Cmd_Almost_Full : out std_logic;
VFBC1_Cmd_Idle : out std_logic;
VFBC1_Wd_Clk : in std_logic;
VFBC1_Wd_Reset : in std_logic;
VFBC1_Wd_Write : in std_logic;
VFBC1_Wd_End_Burst : in std_logic;
VFBC1_Wd_Flush : in std_logic;
VFBC1_Wd_Data : in std_logic_vector(31 downto 0);
VFBC1_Wd_Data_BE : in std_logic_vector(3 downto 0);
VFBC1_Wd_Full : out std_logic;
VFBC1_Wd_Almost_Full : out std_logic;
VFBC1_Rd_Clk : in std_logic;
VFBC1_Rd_Reset : in std_logic;
VFBC1_Rd_Read : in std_logic;
VFBC1_Rd_End_Burst : in std_logic;
VFBC1_Rd_Flush : in std_logic;
VFBC1_Rd_Data : out std_logic_vector(31 downto 0);
VFBC1_Rd_Empty : out std_logic;
VFBC1_Rd_Almost_Empty : out std_logic;
MCB1_cmd_clk : in std_logic;
MCB1_cmd_en : in std_logic;
MCB1_cmd_instr : in std_logic_vector(2 downto 0);
MCB1_cmd_bl : in std_logic_vector(5 downto 0);
MCB1_cmd_byte_addr : in std_logic_vector(29 downto 0);
MCB1_cmd_empty : out std_logic;
MCB1_cmd_full : out std_logic;
MCB1_wr_clk : in std_logic;
MCB1_wr_en : in std_logic;
MCB1_wr_mask : in std_logic_vector(7 downto 0);
MCB1_wr_data : in std_logic_vector(63 downto 0);
MCB1_wr_full : out std_logic;
MCB1_wr_empty : out std_logic;
MCB1_wr_count : out std_logic_vector(6 downto 0);
MCB1_wr_underrun : out std_logic;
MCB1_wr_error : out std_logic;
MCB1_rd_clk : in std_logic;
MCB1_rd_en : in std_logic;
MCB1_rd_data : out std_logic_vector(63 downto 0);
MCB1_rd_full : out std_logic;
MCB1_rd_empty : out std_logic;
MCB1_rd_count : out std_logic_vector(6 downto 0);
MCB1_rd_overflow : out std_logic;
MCB1_rd_error : out std_logic;
FSL2_M_Clk : in std_logic;
FSL2_M_Write : in std_logic;
FSL2_M_Data : in std_logic_vector(0 to 31);
FSL2_M_Control : in std_logic;
FSL2_M_Full : out std_logic;
FSL2_S_Clk : in std_logic;
FSL2_S_Read : in std_logic;
FSL2_S_Data : out std_logic_vector(0 to 31);
FSL2_S_Control : out std_logic;
FSL2_S_Exists : out std_logic;
FSL2_B_M_Clk : in std_logic;
FSL2_B_M_Write : in std_logic;
FSL2_B_M_Data : in std_logic_vector(0 to 31);
FSL2_B_M_Control : in std_logic;
FSL2_B_M_Full : out std_logic;
FSL2_B_S_Clk : in std_logic;
FSL2_B_S_Read : in std_logic;
FSL2_B_S_Data : out std_logic_vector(0 to 31);
FSL2_B_S_Control : out std_logic;
FSL2_B_S_Exists : out std_logic;
SPLB2_Clk : in std_logic;
SPLB2_Rst : in std_logic;
SPLB2_PLB_ABus : in std_logic_vector(0 to 31);
SPLB2_PLB_PAValid : in std_logic;
SPLB2_PLB_SAValid : in std_logic;
SPLB2_PLB_masterID : in std_logic_vector(0 to 0);
SPLB2_PLB_RNW : in std_logic;
SPLB2_PLB_BE : in std_logic_vector(0 to 7);
SPLB2_PLB_UABus : in std_logic_vector(0 to 31);
SPLB2_PLB_rdPrim : in std_logic;
SPLB2_PLB_wrPrim : in std_logic;
SPLB2_PLB_abort : in std_logic;
SPLB2_PLB_busLock : in std_logic;
SPLB2_PLB_MSize : in std_logic_vector(0 to 1);
SPLB2_PLB_size : in std_logic_vector(0 to 3);
SPLB2_PLB_type : in std_logic_vector(0 to 2);
SPLB2_PLB_lockErr : in std_logic;
SPLB2_PLB_wrPendReq : in std_logic;
SPLB2_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB2_PLB_rdPendReq : in std_logic;
SPLB2_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB2_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB2_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB2_PLB_rdBurst : in std_logic;
SPLB2_PLB_wrBurst : in std_logic;
SPLB2_PLB_wrDBus : in std_logic_vector(0 to 63);
SPLB2_Sl_addrAck : out std_logic;
SPLB2_Sl_SSize : out std_logic_vector(0 to 1);
SPLB2_Sl_wait : out std_logic;
SPLB2_Sl_rearbitrate : out std_logic;
SPLB2_Sl_wrDAck : out std_logic;
SPLB2_Sl_wrComp : out std_logic;
SPLB2_Sl_wrBTerm : out std_logic;
SPLB2_Sl_rdDBus : out std_logic_vector(0 to 63);
SPLB2_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB2_Sl_rdDAck : out std_logic;
SPLB2_Sl_rdComp : out std_logic;
SPLB2_Sl_rdBTerm : out std_logic;
SPLB2_Sl_MBusy : out std_logic_vector(0 to 0);
SPLB2_Sl_MRdErr : out std_logic_vector(0 to 0);
SPLB2_Sl_MWrErr : out std_logic_vector(0 to 0);
SPLB2_Sl_MIRQ : out std_logic_vector(0 to 0);
SDMA2_Clk : in std_logic;
SDMA2_Rx_IntOut : out std_logic;
SDMA2_Tx_IntOut : out std_logic;
SDMA2_RstOut : out std_logic;
SDMA2_TX_D : out std_logic_vector(0 to 31);
SDMA2_TX_Rem : out std_logic_vector(0 to 3);
SDMA2_TX_SOF : out std_logic;
SDMA2_TX_EOF : out std_logic;
SDMA2_TX_SOP : out std_logic;
SDMA2_TX_EOP : out std_logic;
SDMA2_TX_Src_Rdy : out std_logic;
SDMA2_TX_Dst_Rdy : in std_logic;
SDMA2_RX_D : in std_logic_vector(0 to 31);
SDMA2_RX_Rem : in std_logic_vector(0 to 3);
SDMA2_RX_SOF : in std_logic;
SDMA2_RX_EOF : in std_logic;
SDMA2_RX_SOP : in std_logic;
SDMA2_RX_EOP : in std_logic;
SDMA2_RX_Src_Rdy : in std_logic;
SDMA2_RX_Dst_Rdy : out std_logic;
SDMA_CTRL2_Clk : in std_logic;
SDMA_CTRL2_Rst : in std_logic;
SDMA_CTRL2_PLB_ABus : in std_logic_vector(0 to 31);
SDMA_CTRL2_PLB_PAValid : in std_logic;
SDMA_CTRL2_PLB_SAValid : in std_logic;
SDMA_CTRL2_PLB_masterID : in std_logic_vector(0 to 0);
SDMA_CTRL2_PLB_RNW : in std_logic;
SDMA_CTRL2_PLB_BE : in std_logic_vector(0 to 7);
SDMA_CTRL2_PLB_UABus : in std_logic_vector(0 to 31);
SDMA_CTRL2_PLB_rdPrim : in std_logic;
SDMA_CTRL2_PLB_wrPrim : in std_logic;
SDMA_CTRL2_PLB_abort : in std_logic;
SDMA_CTRL2_PLB_busLock : in std_logic;
SDMA_CTRL2_PLB_MSize : in std_logic_vector(0 to 1);
SDMA_CTRL2_PLB_size : in std_logic_vector(0 to 3);
SDMA_CTRL2_PLB_type : in std_logic_vector(0 to 2);
SDMA_CTRL2_PLB_lockErr : in std_logic;
SDMA_CTRL2_PLB_wrPendReq : in std_logic;
SDMA_CTRL2_PLB_wrPendPri : in std_logic_vector(0 to 1);
SDMA_CTRL2_PLB_rdPendReq : in std_logic;
SDMA_CTRL2_PLB_rdPendPri : in std_logic_vector(0 to 1);
SDMA_CTRL2_PLB_reqPri : in std_logic_vector(0 to 1);
SDMA_CTRL2_PLB_TAttribute : in std_logic_vector(0 to 15);
SDMA_CTRL2_PLB_rdBurst : in std_logic;
SDMA_CTRL2_PLB_wrBurst : in std_logic;
SDMA_CTRL2_PLB_wrDBus : in std_logic_vector(0 to 63);
SDMA_CTRL2_Sl_addrAck : out std_logic;
SDMA_CTRL2_Sl_SSize : out std_logic_vector(0 to 1);
SDMA_CTRL2_Sl_wait : out std_logic;
SDMA_CTRL2_Sl_rearbitrate : out std_logic;
SDMA_CTRL2_Sl_wrDAck : out std_logic;
SDMA_CTRL2_Sl_wrComp : out std_logic;
SDMA_CTRL2_Sl_wrBTerm : out std_logic;
SDMA_CTRL2_Sl_rdDBus : out std_logic_vector(0 to 63);
SDMA_CTRL2_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SDMA_CTRL2_Sl_rdDAck : out std_logic;
SDMA_CTRL2_Sl_rdComp : out std_logic;
SDMA_CTRL2_Sl_rdBTerm : out std_logic;
SDMA_CTRL2_Sl_MBusy : out std_logic_vector(0 to 0);
SDMA_CTRL2_Sl_MRdErr : out std_logic_vector(0 to 0);
SDMA_CTRL2_Sl_MWrErr : out std_logic_vector(0 to 0);
SDMA_CTRL2_Sl_MIRQ : out std_logic_vector(0 to 0);
PIM2_Addr : in std_logic_vector(31 downto 0);
PIM2_AddrReq : in std_logic;
PIM2_AddrAck : out std_logic;
PIM2_RNW : in std_logic;
PIM2_Size : in std_logic_vector(3 downto 0);
PIM2_RdModWr : in std_logic;
PIM2_WrFIFO_Data : in std_logic_vector(63 downto 0);
PIM2_WrFIFO_BE : in std_logic_vector(7 downto 0);
PIM2_WrFIFO_Push : in std_logic;
PIM2_RdFIFO_Data : out std_logic_vector(63 downto 0);
PIM2_RdFIFO_Pop : in std_logic;
PIM2_RdFIFO_RdWdAddr : out std_logic_vector(3 downto 0);
PIM2_WrFIFO_Empty : out std_logic;
PIM2_WrFIFO_AlmostFull : out std_logic;
PIM2_WrFIFO_Flush : in std_logic;
PIM2_RdFIFO_Empty : out std_logic;
PIM2_RdFIFO_Flush : in std_logic;
PIM2_RdFIFO_Latency : out std_logic_vector(1 downto 0);
PIM2_InitDone : out std_logic;
PPC440MC2_MIMCReadNotWrite : in std_logic;
PPC440MC2_MIMCAddress : in std_logic_vector(0 to 35);
PPC440MC2_MIMCAddressValid : in std_logic;
PPC440MC2_MIMCWriteData : in std_logic_vector(0 to 127);
PPC440MC2_MIMCWriteDataValid : in std_logic;
PPC440MC2_MIMCByteEnable : in std_logic_vector(0 to 15);
PPC440MC2_MIMCBankConflict : in std_logic;
PPC440MC2_MIMCRowConflict : in std_logic;
PPC440MC2_MCMIReadData : out std_logic_vector(0 to 127);
PPC440MC2_MCMIReadDataValid : out std_logic;
PPC440MC2_MCMIReadDataErr : out std_logic;
PPC440MC2_MCMIAddrReadyToAccept : out std_logic;
VFBC2_Cmd_Clk : in std_logic;
VFBC2_Cmd_Reset : in std_logic;
VFBC2_Cmd_Data : in std_logic_vector(31 downto 0);
VFBC2_Cmd_Write : in std_logic;
VFBC2_Cmd_End : in std_logic;
VFBC2_Cmd_Full : out std_logic;
VFBC2_Cmd_Almost_Full : out std_logic;
VFBC2_Cmd_Idle : out std_logic;
VFBC2_Wd_Clk : in std_logic;
VFBC2_Wd_Reset : in std_logic;
VFBC2_Wd_Write : in std_logic;
VFBC2_Wd_End_Burst : in std_logic;
VFBC2_Wd_Flush : in std_logic;
VFBC2_Wd_Data : in std_logic_vector(31 downto 0);
VFBC2_Wd_Data_BE : in std_logic_vector(3 downto 0);
VFBC2_Wd_Full : out std_logic;
VFBC2_Wd_Almost_Full : out std_logic;
VFBC2_Rd_Clk : in std_logic;
VFBC2_Rd_Reset : in std_logic;
VFBC2_Rd_Read : in std_logic;
VFBC2_Rd_End_Burst : in std_logic;
VFBC2_Rd_Flush : in std_logic;
VFBC2_Rd_Data : out std_logic_vector(31 downto 0);
VFBC2_Rd_Empty : out std_logic;
VFBC2_Rd_Almost_Empty : out std_logic;
MCB2_cmd_clk : in std_logic;
MCB2_cmd_en : in std_logic;
MCB2_cmd_instr : in std_logic_vector(2 downto 0);
MCB2_cmd_bl : in std_logic_vector(5 downto 0);
MCB2_cmd_byte_addr : in std_logic_vector(29 downto 0);
MCB2_cmd_empty : out std_logic;
MCB2_cmd_full : out std_logic;
MCB2_wr_clk : in std_logic;
MCB2_wr_en : in std_logic;
MCB2_wr_mask : in std_logic_vector(7 downto 0);
MCB2_wr_data : in std_logic_vector(63 downto 0);
MCB2_wr_full : out std_logic;
MCB2_wr_empty : out std_logic;
MCB2_wr_count : out std_logic_vector(6 downto 0);
MCB2_wr_underrun : out std_logic;
MCB2_wr_error : out std_logic;
MCB2_rd_clk : in std_logic;
MCB2_rd_en : in std_logic;
MCB2_rd_data : out std_logic_vector(63 downto 0);
MCB2_rd_full : out std_logic;
MCB2_rd_empty : out std_logic;
MCB2_rd_count : out std_logic_vector(6 downto 0);
MCB2_rd_overflow : out std_logic;
MCB2_rd_error : out std_logic;
FSL3_M_Clk : in std_logic;
FSL3_M_Write : in std_logic;
FSL3_M_Data : in std_logic_vector(0 to 31);
FSL3_M_Control : in std_logic;
FSL3_M_Full : out std_logic;
FSL3_S_Clk : in std_logic;
FSL3_S_Read : in std_logic;
FSL3_S_Data : out std_logic_vector(0 to 31);
FSL3_S_Control : out std_logic;
FSL3_S_Exists : out std_logic;
FSL3_B_M_Clk : in std_logic;
FSL3_B_M_Write : in std_logic;
FSL3_B_M_Data : in std_logic_vector(0 to 31);
FSL3_B_M_Control : in std_logic;
FSL3_B_M_Full : out std_logic;
FSL3_B_S_Clk : in std_logic;
FSL3_B_S_Read : in std_logic;
FSL3_B_S_Data : out std_logic_vector(0 to 31);
FSL3_B_S_Control : out std_logic;
FSL3_B_S_Exists : out std_logic;
SPLB3_Clk : in std_logic;
SPLB3_Rst : in std_logic;
SPLB3_PLB_ABus : in std_logic_vector(0 to 31);
SPLB3_PLB_PAValid : in std_logic;
SPLB3_PLB_SAValid : in std_logic;
SPLB3_PLB_masterID : in std_logic_vector(0 to 0);
SPLB3_PLB_RNW : in std_logic;
SPLB3_PLB_BE : in std_logic_vector(0 to 7);
SPLB3_PLB_UABus : in std_logic_vector(0 to 31);
SPLB3_PLB_rdPrim : in std_logic;
SPLB3_PLB_wrPrim : in std_logic;
SPLB3_PLB_abort : in std_logic;
SPLB3_PLB_busLock : in std_logic;
SPLB3_PLB_MSize : in std_logic_vector(0 to 1);
SPLB3_PLB_size : in std_logic_vector(0 to 3);
SPLB3_PLB_type : in std_logic_vector(0 to 2);
SPLB3_PLB_lockErr : in std_logic;
SPLB3_PLB_wrPendReq : in std_logic;
SPLB3_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB3_PLB_rdPendReq : in std_logic;
SPLB3_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB3_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB3_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB3_PLB_rdBurst : in std_logic;
SPLB3_PLB_wrBurst : in std_logic;
SPLB3_PLB_wrDBus : in std_logic_vector(0 to 63);
SPLB3_Sl_addrAck : out std_logic;
SPLB3_Sl_SSize : out std_logic_vector(0 to 1);
SPLB3_Sl_wait : out std_logic;
SPLB3_Sl_rearbitrate : out std_logic;
SPLB3_Sl_wrDAck : out std_logic;
SPLB3_Sl_wrComp : out std_logic;
SPLB3_Sl_wrBTerm : out std_logic;
SPLB3_Sl_rdDBus : out std_logic_vector(0 to 63);
SPLB3_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB3_Sl_rdDAck : out std_logic;
SPLB3_Sl_rdComp : out std_logic;
SPLB3_Sl_rdBTerm : out std_logic;
SPLB3_Sl_MBusy : out std_logic_vector(0 to 0);
SPLB3_Sl_MRdErr : out std_logic_vector(0 to 0);
SPLB3_Sl_MWrErr : out std_logic_vector(0 to 0);
SPLB3_Sl_MIRQ : out std_logic_vector(0 to 0);
SDMA3_Clk : in std_logic;
SDMA3_Rx_IntOut : out std_logic;
SDMA3_Tx_IntOut : out std_logic;
SDMA3_RstOut : out std_logic;
SDMA3_TX_D : out std_logic_vector(0 to 31);
SDMA3_TX_Rem : out std_logic_vector(0 to 3);
SDMA3_TX_SOF : out std_logic;
SDMA3_TX_EOF : out std_logic;
SDMA3_TX_SOP : out std_logic;
SDMA3_TX_EOP : out std_logic;
SDMA3_TX_Src_Rdy : out std_logic;
SDMA3_TX_Dst_Rdy : in std_logic;
SDMA3_RX_D : in std_logic_vector(0 to 31);
SDMA3_RX_Rem : in std_logic_vector(0 to 3);
SDMA3_RX_SOF : in std_logic;
SDMA3_RX_EOF : in std_logic;
SDMA3_RX_SOP : in std_logic;
SDMA3_RX_EOP : in std_logic;
SDMA3_RX_Src_Rdy : in std_logic;
SDMA3_RX_Dst_Rdy : out std_logic;
SDMA_CTRL3_Clk : in std_logic;
SDMA_CTRL3_Rst : in std_logic;
SDMA_CTRL3_PLB_ABus : in std_logic_vector(0 to 31);
SDMA_CTRL3_PLB_PAValid : in std_logic;
SDMA_CTRL3_PLB_SAValid : in std_logic;
SDMA_CTRL3_PLB_masterID : in std_logic_vector(0 to 0);
SDMA_CTRL3_PLB_RNW : in std_logic;
SDMA_CTRL3_PLB_BE : in std_logic_vector(0 to 7);
SDMA_CTRL3_PLB_UABus : in std_logic_vector(0 to 31);
SDMA_CTRL3_PLB_rdPrim : in std_logic;
SDMA_CTRL3_PLB_wrPrim : in std_logic;
SDMA_CTRL3_PLB_abort : in std_logic;
SDMA_CTRL3_PLB_busLock : in std_logic;
SDMA_CTRL3_PLB_MSize : in std_logic_vector(0 to 1);
SDMA_CTRL3_PLB_size : in std_logic_vector(0 to 3);
SDMA_CTRL3_PLB_type : in std_logic_vector(0 to 2);
SDMA_CTRL3_PLB_lockErr : in std_logic;
SDMA_CTRL3_PLB_wrPendReq : in std_logic;
SDMA_CTRL3_PLB_wrPendPri : in std_logic_vector(0 to 1);
SDMA_CTRL3_PLB_rdPendReq : in std_logic;
SDMA_CTRL3_PLB_rdPendPri : in std_logic_vector(0 to 1);
SDMA_CTRL3_PLB_reqPri : in std_logic_vector(0 to 1);
SDMA_CTRL3_PLB_TAttribute : in std_logic_vector(0 to 15);
SDMA_CTRL3_PLB_rdBurst : in std_logic;
SDMA_CTRL3_PLB_wrBurst : in std_logic;
SDMA_CTRL3_PLB_wrDBus : in std_logic_vector(0 to 63);
SDMA_CTRL3_Sl_addrAck : out std_logic;
SDMA_CTRL3_Sl_SSize : out std_logic_vector(0 to 1);
SDMA_CTRL3_Sl_wait : out std_logic;
SDMA_CTRL3_Sl_rearbitrate : out std_logic;
SDMA_CTRL3_Sl_wrDAck : out std_logic;
SDMA_CTRL3_Sl_wrComp : out std_logic;
SDMA_CTRL3_Sl_wrBTerm : out std_logic;
SDMA_CTRL3_Sl_rdDBus : out std_logic_vector(0 to 63);
SDMA_CTRL3_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SDMA_CTRL3_Sl_rdDAck : out std_logic;
SDMA_CTRL3_Sl_rdComp : out std_logic;
SDMA_CTRL3_Sl_rdBTerm : out std_logic;
SDMA_CTRL3_Sl_MBusy : out std_logic_vector(0 to 0);
SDMA_CTRL3_Sl_MRdErr : out std_logic_vector(0 to 0);
SDMA_CTRL3_Sl_MWrErr : out std_logic_vector(0 to 0);
SDMA_CTRL3_Sl_MIRQ : out std_logic_vector(0 to 0);
PIM3_Addr : in std_logic_vector(31 downto 0);
PIM3_AddrReq : in std_logic;
PIM3_AddrAck : out std_logic;
PIM3_RNW : in std_logic;
PIM3_Size : in std_logic_vector(3 downto 0);
PIM3_RdModWr : in std_logic;
PIM3_WrFIFO_Data : in std_logic_vector(63 downto 0);
PIM3_WrFIFO_BE : in std_logic_vector(7 downto 0);
PIM3_WrFIFO_Push : in std_logic;
PIM3_RdFIFO_Data : out std_logic_vector(63 downto 0);
PIM3_RdFIFO_Pop : in std_logic;
PIM3_RdFIFO_RdWdAddr : out std_logic_vector(3 downto 0);
PIM3_WrFIFO_Empty : out std_logic;
PIM3_WrFIFO_AlmostFull : out std_logic;
PIM3_WrFIFO_Flush : in std_logic;
PIM3_RdFIFO_Empty : out std_logic;
PIM3_RdFIFO_Flush : in std_logic;
PIM3_RdFIFO_Latency : out std_logic_vector(1 downto 0);
PIM3_InitDone : out std_logic;
PPC440MC3_MIMCReadNotWrite : in std_logic;
PPC440MC3_MIMCAddress : in std_logic_vector(0 to 35);
PPC440MC3_MIMCAddressValid : in std_logic;
PPC440MC3_MIMCWriteData : in std_logic_vector(0 to 127);
PPC440MC3_MIMCWriteDataValid : in std_logic;
PPC440MC3_MIMCByteEnable : in std_logic_vector(0 to 15);
PPC440MC3_MIMCBankConflict : in std_logic;
PPC440MC3_MIMCRowConflict : in std_logic;
PPC440MC3_MCMIReadData : out std_logic_vector(0 to 127);
PPC440MC3_MCMIReadDataValid : out std_logic;
PPC440MC3_MCMIReadDataErr : out std_logic;
PPC440MC3_MCMIAddrReadyToAccept : out std_logic;
VFBC3_Cmd_Clk : in std_logic;
VFBC3_Cmd_Reset : in std_logic;
VFBC3_Cmd_Data : in std_logic_vector(31 downto 0);
VFBC3_Cmd_Write : in std_logic;
VFBC3_Cmd_End : in std_logic;
VFBC3_Cmd_Full : out std_logic;
VFBC3_Cmd_Almost_Full : out std_logic;
VFBC3_Cmd_Idle : out std_logic;
VFBC3_Wd_Clk : in std_logic;
VFBC3_Wd_Reset : in std_logic;
VFBC3_Wd_Write : in std_logic;
VFBC3_Wd_End_Burst : in std_logic;
VFBC3_Wd_Flush : in std_logic;
VFBC3_Wd_Data : in std_logic_vector(31 downto 0);
VFBC3_Wd_Data_BE : in std_logic_vector(3 downto 0);
VFBC3_Wd_Full : out std_logic;
VFBC3_Wd_Almost_Full : out std_logic;
VFBC3_Rd_Clk : in std_logic;
VFBC3_Rd_Reset : in std_logic;
VFBC3_Rd_Read : in std_logic;
VFBC3_Rd_End_Burst : in std_logic;
VFBC3_Rd_Flush : in std_logic;
VFBC3_Rd_Data : out std_logic_vector(31 downto 0);
VFBC3_Rd_Empty : out std_logic;
VFBC3_Rd_Almost_Empty : out std_logic;
MCB3_cmd_clk : in std_logic;
MCB3_cmd_en : in std_logic;
MCB3_cmd_instr : in std_logic_vector(2 downto 0);
MCB3_cmd_bl : in std_logic_vector(5 downto 0);
MCB3_cmd_byte_addr : in std_logic_vector(29 downto 0);
MCB3_cmd_empty : out std_logic;
MCB3_cmd_full : out std_logic;
MCB3_wr_clk : in std_logic;
MCB3_wr_en : in std_logic;
MCB3_wr_mask : in std_logic_vector(7 downto 0);
MCB3_wr_data : in std_logic_vector(63 downto 0);
MCB3_wr_full : out std_logic;
MCB3_wr_empty : out std_logic;
MCB3_wr_count : out std_logic_vector(6 downto 0);
MCB3_wr_underrun : out std_logic;
MCB3_wr_error : out std_logic;
MCB3_rd_clk : in std_logic;
MCB3_rd_en : in std_logic;
MCB3_rd_data : out std_logic_vector(63 downto 0);
MCB3_rd_full : out std_logic;
MCB3_rd_empty : out std_logic;
MCB3_rd_count : out std_logic_vector(6 downto 0);
MCB3_rd_overflow : out std_logic;
MCB3_rd_error : out std_logic;
FSL4_M_Clk : in std_logic;
FSL4_M_Write : in std_logic;
FSL4_M_Data : in std_logic_vector(0 to 31);
FSL4_M_Control : in std_logic;
FSL4_M_Full : out std_logic;
FSL4_S_Clk : in std_logic;
FSL4_S_Read : in std_logic;
FSL4_S_Data : out std_logic_vector(0 to 31);
FSL4_S_Control : out std_logic;
FSL4_S_Exists : out std_logic;
FSL4_B_M_Clk : in std_logic;
FSL4_B_M_Write : in std_logic;
FSL4_B_M_Data : in std_logic_vector(0 to 31);
FSL4_B_M_Control : in std_logic;
FSL4_B_M_Full : out std_logic;
FSL4_B_S_Clk : in std_logic;
FSL4_B_S_Read : in std_logic;
FSL4_B_S_Data : out std_logic_vector(0 to 31);
FSL4_B_S_Control : out std_logic;
FSL4_B_S_Exists : out std_logic;
SPLB4_Clk : in std_logic;
SPLB4_Rst : in std_logic;
SPLB4_PLB_ABus : in std_logic_vector(0 to 31);
SPLB4_PLB_PAValid : in std_logic;
SPLB4_PLB_SAValid : in std_logic;
SPLB4_PLB_masterID : in std_logic_vector(0 to 0);
SPLB4_PLB_RNW : in std_logic;
SPLB4_PLB_BE : in std_logic_vector(0 to 7);
SPLB4_PLB_UABus : in std_logic_vector(0 to 31);
SPLB4_PLB_rdPrim : in std_logic;
SPLB4_PLB_wrPrim : in std_logic;
SPLB4_PLB_abort : in std_logic;
SPLB4_PLB_busLock : in std_logic;
SPLB4_PLB_MSize : in std_logic_vector(0 to 1);
SPLB4_PLB_size : in std_logic_vector(0 to 3);
SPLB4_PLB_type : in std_logic_vector(0 to 2);
SPLB4_PLB_lockErr : in std_logic;
SPLB4_PLB_wrPendReq : in std_logic;
SPLB4_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB4_PLB_rdPendReq : in std_logic;
SPLB4_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB4_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB4_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB4_PLB_rdBurst : in std_logic;
SPLB4_PLB_wrBurst : in std_logic;
SPLB4_PLB_wrDBus : in std_logic_vector(0 to 63);
SPLB4_Sl_addrAck : out std_logic;
SPLB4_Sl_SSize : out std_logic_vector(0 to 1);
SPLB4_Sl_wait : out std_logic;
SPLB4_Sl_rearbitrate : out std_logic;
SPLB4_Sl_wrDAck : out std_logic;
SPLB4_Sl_wrComp : out std_logic;
SPLB4_Sl_wrBTerm : out std_logic;
SPLB4_Sl_rdDBus : out std_logic_vector(0 to 63);
SPLB4_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB4_Sl_rdDAck : out std_logic;
SPLB4_Sl_rdComp : out std_logic;
SPLB4_Sl_rdBTerm : out std_logic;
SPLB4_Sl_MBusy : out std_logic_vector(0 to 0);
SPLB4_Sl_MRdErr : out std_logic_vector(0 to 0);
SPLB4_Sl_MWrErr : out std_logic_vector(0 to 0);
SPLB4_Sl_MIRQ : out std_logic_vector(0 to 0);
SDMA4_Clk : in std_logic;
SDMA4_Rx_IntOut : out std_logic;
SDMA4_Tx_IntOut : out std_logic;
SDMA4_RstOut : out std_logic;
SDMA4_TX_D : out std_logic_vector(0 to 31);
SDMA4_TX_Rem : out std_logic_vector(0 to 3);
SDMA4_TX_SOF : out std_logic;
SDMA4_TX_EOF : out std_logic;
SDMA4_TX_SOP : out std_logic;
SDMA4_TX_EOP : out std_logic;
SDMA4_TX_Src_Rdy : out std_logic;
SDMA4_TX_Dst_Rdy : in std_logic;
SDMA4_RX_D : in std_logic_vector(0 to 31);
SDMA4_RX_Rem : in std_logic_vector(0 to 3);
SDMA4_RX_SOF : in std_logic;
SDMA4_RX_EOF : in std_logic;
SDMA4_RX_SOP : in std_logic;
SDMA4_RX_EOP : in std_logic;
SDMA4_RX_Src_Rdy : in std_logic;
SDMA4_RX_Dst_Rdy : out std_logic;
SDMA_CTRL4_Clk : in std_logic;
SDMA_CTRL4_Rst : in std_logic;
SDMA_CTRL4_PLB_ABus : in std_logic_vector(0 to 31);
SDMA_CTRL4_PLB_PAValid : in std_logic;
SDMA_CTRL4_PLB_SAValid : in std_logic;
SDMA_CTRL4_PLB_masterID : in std_logic_vector(0 to 0);
SDMA_CTRL4_PLB_RNW : in std_logic;
SDMA_CTRL4_PLB_BE : in std_logic_vector(0 to 7);
SDMA_CTRL4_PLB_UABus : in std_logic_vector(0 to 31);
SDMA_CTRL4_PLB_rdPrim : in std_logic;
SDMA_CTRL4_PLB_wrPrim : in std_logic;
SDMA_CTRL4_PLB_abort : in std_logic;
SDMA_CTRL4_PLB_busLock : in std_logic;
SDMA_CTRL4_PLB_MSize : in std_logic_vector(0 to 1);
SDMA_CTRL4_PLB_size : in std_logic_vector(0 to 3);
SDMA_CTRL4_PLB_type : in std_logic_vector(0 to 2);
SDMA_CTRL4_PLB_lockErr : in std_logic;
SDMA_CTRL4_PLB_wrPendReq : in std_logic;
SDMA_CTRL4_PLB_wrPendPri : in std_logic_vector(0 to 1);
SDMA_CTRL4_PLB_rdPendReq : in std_logic;
SDMA_CTRL4_PLB_rdPendPri : in std_logic_vector(0 to 1);
SDMA_CTRL4_PLB_reqPri : in std_logic_vector(0 to 1);
SDMA_CTRL4_PLB_TAttribute : in std_logic_vector(0 to 15);
SDMA_CTRL4_PLB_rdBurst : in std_logic;
SDMA_CTRL4_PLB_wrBurst : in std_logic;
SDMA_CTRL4_PLB_wrDBus : in std_logic_vector(0 to 63);
SDMA_CTRL4_Sl_addrAck : out std_logic;
SDMA_CTRL4_Sl_SSize : out std_logic_vector(0 to 1);
SDMA_CTRL4_Sl_wait : out std_logic;
SDMA_CTRL4_Sl_rearbitrate : out std_logic;
SDMA_CTRL4_Sl_wrDAck : out std_logic;
SDMA_CTRL4_Sl_wrComp : out std_logic;
SDMA_CTRL4_Sl_wrBTerm : out std_logic;
SDMA_CTRL4_Sl_rdDBus : out std_logic_vector(0 to 63);
SDMA_CTRL4_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SDMA_CTRL4_Sl_rdDAck : out std_logic;
SDMA_CTRL4_Sl_rdComp : out std_logic;
SDMA_CTRL4_Sl_rdBTerm : out std_logic;
SDMA_CTRL4_Sl_MBusy : out std_logic_vector(0 to 0);
SDMA_CTRL4_Sl_MRdErr : out std_logic_vector(0 to 0);
SDMA_CTRL4_Sl_MWrErr : out std_logic_vector(0 to 0);
SDMA_CTRL4_Sl_MIRQ : out std_logic_vector(0 to 0);
PIM4_Addr : in std_logic_vector(31 downto 0);
PIM4_AddrReq : in std_logic;
PIM4_AddrAck : out std_logic;
PIM4_RNW : in std_logic;
PIM4_Size : in std_logic_vector(3 downto 0);
PIM4_RdModWr : in std_logic;
PIM4_WrFIFO_Data : in std_logic_vector(63 downto 0);
PIM4_WrFIFO_BE : in std_logic_vector(7 downto 0);
PIM4_WrFIFO_Push : in std_logic;
PIM4_RdFIFO_Data : out std_logic_vector(63 downto 0);
PIM4_RdFIFO_Pop : in std_logic;
PIM4_RdFIFO_RdWdAddr : out std_logic_vector(3 downto 0);
PIM4_WrFIFO_Empty : out std_logic;
PIM4_WrFIFO_AlmostFull : out std_logic;
PIM4_WrFIFO_Flush : in std_logic;
PIM4_RdFIFO_Empty : out std_logic;
PIM4_RdFIFO_Flush : in std_logic;
PIM4_RdFIFO_Latency : out std_logic_vector(1 downto 0);
PIM4_InitDone : out std_logic;
PPC440MC4_MIMCReadNotWrite : in std_logic;
PPC440MC4_MIMCAddress : in std_logic_vector(0 to 35);
PPC440MC4_MIMCAddressValid : in std_logic;
PPC440MC4_MIMCWriteData : in std_logic_vector(0 to 127);
PPC440MC4_MIMCWriteDataValid : in std_logic;
PPC440MC4_MIMCByteEnable : in std_logic_vector(0 to 15);
PPC440MC4_MIMCBankConflict : in std_logic;
PPC440MC4_MIMCRowConflict : in std_logic;
PPC440MC4_MCMIReadData : out std_logic_vector(0 to 127);
PPC440MC4_MCMIReadDataValid : out std_logic;
PPC440MC4_MCMIReadDataErr : out std_logic;
PPC440MC4_MCMIAddrReadyToAccept : out std_logic;
VFBC4_Cmd_Clk : in std_logic;
VFBC4_Cmd_Reset : in std_logic;
VFBC4_Cmd_Data : in std_logic_vector(31 downto 0);
VFBC4_Cmd_Write : in std_logic;
VFBC4_Cmd_End : in std_logic;
VFBC4_Cmd_Full : out std_logic;
VFBC4_Cmd_Almost_Full : out std_logic;
VFBC4_Cmd_Idle : out std_logic;
VFBC4_Wd_Clk : in std_logic;
VFBC4_Wd_Reset : in std_logic;
VFBC4_Wd_Write : in std_logic;
VFBC4_Wd_End_Burst : in std_logic;
VFBC4_Wd_Flush : in std_logic;
VFBC4_Wd_Data : in std_logic_vector(31 downto 0);
VFBC4_Wd_Data_BE : in std_logic_vector(3 downto 0);
VFBC4_Wd_Full : out std_logic;
VFBC4_Wd_Almost_Full : out std_logic;
VFBC4_Rd_Clk : in std_logic;
VFBC4_Rd_Reset : in std_logic;
VFBC4_Rd_Read : in std_logic;
VFBC4_Rd_End_Burst : in std_logic;
VFBC4_Rd_Flush : in std_logic;
VFBC4_Rd_Data : out std_logic_vector(31 downto 0);
VFBC4_Rd_Empty : out std_logic;
VFBC4_Rd_Almost_Empty : out std_logic;
MCB4_cmd_clk : in std_logic;
MCB4_cmd_en : in std_logic;
MCB4_cmd_instr : in std_logic_vector(2 downto 0);
MCB4_cmd_bl : in std_logic_vector(5 downto 0);
MCB4_cmd_byte_addr : in std_logic_vector(29 downto 0);
MCB4_cmd_empty : out std_logic;
MCB4_cmd_full : out std_logic;
MCB4_wr_clk : in std_logic;
MCB4_wr_en : in std_logic;
MCB4_wr_mask : in std_logic_vector(7 downto 0);
MCB4_wr_data : in std_logic_vector(63 downto 0);
MCB4_wr_full : out std_logic;
MCB4_wr_empty : out std_logic;
MCB4_wr_count : out std_logic_vector(6 downto 0);
MCB4_wr_underrun : out std_logic;
MCB4_wr_error : out std_logic;
MCB4_rd_clk : in std_logic;
MCB4_rd_en : in std_logic;
MCB4_rd_data : out std_logic_vector(63 downto 0);
MCB4_rd_full : out std_logic;
MCB4_rd_empty : out std_logic;
MCB4_rd_count : out std_logic_vector(6 downto 0);
MCB4_rd_overflow : out std_logic;
MCB4_rd_error : out std_logic;
FSL5_M_Clk : in std_logic;
FSL5_M_Write : in std_logic;
FSL5_M_Data : in std_logic_vector(0 to 31);
FSL5_M_Control : in std_logic;
FSL5_M_Full : out std_logic;
FSL5_S_Clk : in std_logic;
FSL5_S_Read : in std_logic;
FSL5_S_Data : out std_logic_vector(0 to 31);
FSL5_S_Control : out std_logic;
FSL5_S_Exists : out std_logic;
FSL5_B_M_Clk : in std_logic;
FSL5_B_M_Write : in std_logic;
FSL5_B_M_Data : in std_logic_vector(0 to 31);
FSL5_B_M_Control : in std_logic;
FSL5_B_M_Full : out std_logic;
FSL5_B_S_Clk : in std_logic;
FSL5_B_S_Read : in std_logic;
FSL5_B_S_Data : out std_logic_vector(0 to 31);
FSL5_B_S_Control : out std_logic;
FSL5_B_S_Exists : out std_logic;
SPLB5_Clk : in std_logic;
SPLB5_Rst : in std_logic;
SPLB5_PLB_ABus : in std_logic_vector(0 to 31);
SPLB5_PLB_PAValid : in std_logic;
SPLB5_PLB_SAValid : in std_logic;
SPLB5_PLB_masterID : in std_logic_vector(0 to 0);
SPLB5_PLB_RNW : in std_logic;
SPLB5_PLB_BE : in std_logic_vector(0 to 7);
SPLB5_PLB_UABus : in std_logic_vector(0 to 31);
SPLB5_PLB_rdPrim : in std_logic;
SPLB5_PLB_wrPrim : in std_logic;
SPLB5_PLB_abort : in std_logic;
SPLB5_PLB_busLock : in std_logic;
SPLB5_PLB_MSize : in std_logic_vector(0 to 1);
SPLB5_PLB_size : in std_logic_vector(0 to 3);
SPLB5_PLB_type : in std_logic_vector(0 to 2);
SPLB5_PLB_lockErr : in std_logic;
SPLB5_PLB_wrPendReq : in std_logic;
SPLB5_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB5_PLB_rdPendReq : in std_logic;
SPLB5_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB5_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB5_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB5_PLB_rdBurst : in std_logic;
SPLB5_PLB_wrBurst : in std_logic;
SPLB5_PLB_wrDBus : in std_logic_vector(0 to 63);
SPLB5_Sl_addrAck : out std_logic;
SPLB5_Sl_SSize : out std_logic_vector(0 to 1);
SPLB5_Sl_wait : out std_logic;
SPLB5_Sl_rearbitrate : out std_logic;
SPLB5_Sl_wrDAck : out std_logic;
SPLB5_Sl_wrComp : out std_logic;
SPLB5_Sl_wrBTerm : out std_logic;
SPLB5_Sl_rdDBus : out std_logic_vector(0 to 63);
SPLB5_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB5_Sl_rdDAck : out std_logic;
SPLB5_Sl_rdComp : out std_logic;
SPLB5_Sl_rdBTerm : out std_logic;
SPLB5_Sl_MBusy : out std_logic_vector(0 to 0);
SPLB5_Sl_MRdErr : out std_logic_vector(0 to 0);
SPLB5_Sl_MWrErr : out std_logic_vector(0 to 0);
SPLB5_Sl_MIRQ : out std_logic_vector(0 to 0);
SDMA5_Clk : in std_logic;
SDMA5_Rx_IntOut : out std_logic;
SDMA5_Tx_IntOut : out std_logic;
SDMA5_RstOut : out std_logic;
SDMA5_TX_D : out std_logic_vector(0 to 31);
SDMA5_TX_Rem : out std_logic_vector(0 to 3);
SDMA5_TX_SOF : out std_logic;
SDMA5_TX_EOF : out std_logic;
SDMA5_TX_SOP : out std_logic;
SDMA5_TX_EOP : out std_logic;
SDMA5_TX_Src_Rdy : out std_logic;
SDMA5_TX_Dst_Rdy : in std_logic;
SDMA5_RX_D : in std_logic_vector(0 to 31);
SDMA5_RX_Rem : in std_logic_vector(0 to 3);
SDMA5_RX_SOF : in std_logic;
SDMA5_RX_EOF : in std_logic;
SDMA5_RX_SOP : in std_logic;
SDMA5_RX_EOP : in std_logic;
SDMA5_RX_Src_Rdy : in std_logic;
SDMA5_RX_Dst_Rdy : out std_logic;
SDMA_CTRL5_Clk : in std_logic;
SDMA_CTRL5_Rst : in std_logic;
SDMA_CTRL5_PLB_ABus : in std_logic_vector(0 to 31);
SDMA_CTRL5_PLB_PAValid : in std_logic;
SDMA_CTRL5_PLB_SAValid : in std_logic;
SDMA_CTRL5_PLB_masterID : in std_logic_vector(0 to 0);
SDMA_CTRL5_PLB_RNW : in std_logic;
SDMA_CTRL5_PLB_BE : in std_logic_vector(0 to 7);
SDMA_CTRL5_PLB_UABus : in std_logic_vector(0 to 31);
SDMA_CTRL5_PLB_rdPrim : in std_logic;
SDMA_CTRL5_PLB_wrPrim : in std_logic;
SDMA_CTRL5_PLB_abort : in std_logic;
SDMA_CTRL5_PLB_busLock : in std_logic;
SDMA_CTRL5_PLB_MSize : in std_logic_vector(0 to 1);
SDMA_CTRL5_PLB_size : in std_logic_vector(0 to 3);
SDMA_CTRL5_PLB_type : in std_logic_vector(0 to 2);
SDMA_CTRL5_PLB_lockErr : in std_logic;
SDMA_CTRL5_PLB_wrPendReq : in std_logic;
SDMA_CTRL5_PLB_wrPendPri : in std_logic_vector(0 to 1);
SDMA_CTRL5_PLB_rdPendReq : in std_logic;
SDMA_CTRL5_PLB_rdPendPri : in std_logic_vector(0 to 1);
SDMA_CTRL5_PLB_reqPri : in std_logic_vector(0 to 1);
SDMA_CTRL5_PLB_TAttribute : in std_logic_vector(0 to 15);
SDMA_CTRL5_PLB_rdBurst : in std_logic;
SDMA_CTRL5_PLB_wrBurst : in std_logic;
SDMA_CTRL5_PLB_wrDBus : in std_logic_vector(0 to 63);
SDMA_CTRL5_Sl_addrAck : out std_logic;
SDMA_CTRL5_Sl_SSize : out std_logic_vector(0 to 1);
SDMA_CTRL5_Sl_wait : out std_logic;
SDMA_CTRL5_Sl_rearbitrate : out std_logic;
SDMA_CTRL5_Sl_wrDAck : out std_logic;
SDMA_CTRL5_Sl_wrComp : out std_logic;
SDMA_CTRL5_Sl_wrBTerm : out std_logic;
SDMA_CTRL5_Sl_rdDBus : out std_logic_vector(0 to 63);
SDMA_CTRL5_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SDMA_CTRL5_Sl_rdDAck : out std_logic;
SDMA_CTRL5_Sl_rdComp : out std_logic;
SDMA_CTRL5_Sl_rdBTerm : out std_logic;
SDMA_CTRL5_Sl_MBusy : out std_logic_vector(0 to 0);
SDMA_CTRL5_Sl_MRdErr : out std_logic_vector(0 to 0);
SDMA_CTRL5_Sl_MWrErr : out std_logic_vector(0 to 0);
SDMA_CTRL5_Sl_MIRQ : out std_logic_vector(0 to 0);
PIM5_Addr : in std_logic_vector(31 downto 0);
PIM5_AddrReq : in std_logic;
PIM5_AddrAck : out std_logic;
PIM5_RNW : in std_logic;
PIM5_Size : in std_logic_vector(3 downto 0);
PIM5_RdModWr : in std_logic;
PIM5_WrFIFO_Data : in std_logic_vector(63 downto 0);
PIM5_WrFIFO_BE : in std_logic_vector(7 downto 0);
PIM5_WrFIFO_Push : in std_logic;
PIM5_RdFIFO_Data : out std_logic_vector(63 downto 0);
PIM5_RdFIFO_Pop : in std_logic;
PIM5_RdFIFO_RdWdAddr : out std_logic_vector(3 downto 0);
PIM5_WrFIFO_Empty : out std_logic;
PIM5_WrFIFO_AlmostFull : out std_logic;
PIM5_WrFIFO_Flush : in std_logic;
PIM5_RdFIFO_Empty : out std_logic;
PIM5_RdFIFO_Flush : in std_logic;
PIM5_RdFIFO_Latency : out std_logic_vector(1 downto 0);
PIM5_InitDone : out std_logic;
PPC440MC5_MIMCReadNotWrite : in std_logic;
PPC440MC5_MIMCAddress : in std_logic_vector(0 to 35);
PPC440MC5_MIMCAddressValid : in std_logic;
PPC440MC5_MIMCWriteData : in std_logic_vector(0 to 127);
PPC440MC5_MIMCWriteDataValid : in std_logic;
PPC440MC5_MIMCByteEnable : in std_logic_vector(0 to 15);
PPC440MC5_MIMCBankConflict : in std_logic;
PPC440MC5_MIMCRowConflict : in std_logic;
PPC440MC5_MCMIReadData : out std_logic_vector(0 to 127);
PPC440MC5_MCMIReadDataValid : out std_logic;
PPC440MC5_MCMIReadDataErr : out std_logic;
PPC440MC5_MCMIAddrReadyToAccept : out std_logic;
VFBC5_Cmd_Clk : in std_logic;
VFBC5_Cmd_Reset : in std_logic;
VFBC5_Cmd_Data : in std_logic_vector(31 downto 0);
VFBC5_Cmd_Write : in std_logic;
VFBC5_Cmd_End : in std_logic;
VFBC5_Cmd_Full : out std_logic;
VFBC5_Cmd_Almost_Full : out std_logic;
VFBC5_Cmd_Idle : out std_logic;
VFBC5_Wd_Clk : in std_logic;
VFBC5_Wd_Reset : in std_logic;
VFBC5_Wd_Write : in std_logic;
VFBC5_Wd_End_Burst : in std_logic;
VFBC5_Wd_Flush : in std_logic;
VFBC5_Wd_Data : in std_logic_vector(31 downto 0);
VFBC5_Wd_Data_BE : in std_logic_vector(3 downto 0);
VFBC5_Wd_Full : out std_logic;
VFBC5_Wd_Almost_Full : out std_logic;
VFBC5_Rd_Clk : in std_logic;
VFBC5_Rd_Reset : in std_logic;
VFBC5_Rd_Read : in std_logic;
VFBC5_Rd_End_Burst : in std_logic;
VFBC5_Rd_Flush : in std_logic;
VFBC5_Rd_Data : out std_logic_vector(31 downto 0);
VFBC5_Rd_Empty : out std_logic;
VFBC5_Rd_Almost_Empty : out std_logic;
MCB5_cmd_clk : in std_logic;
MCB5_cmd_en : in std_logic;
MCB5_cmd_instr : in std_logic_vector(2 downto 0);
MCB5_cmd_bl : in std_logic_vector(5 downto 0);
MCB5_cmd_byte_addr : in std_logic_vector(29 downto 0);
MCB5_cmd_empty : out std_logic;
MCB5_cmd_full : out std_logic;
MCB5_wr_clk : in std_logic;
MCB5_wr_en : in std_logic;
MCB5_wr_mask : in std_logic_vector(7 downto 0);
MCB5_wr_data : in std_logic_vector(63 downto 0);
MCB5_wr_full : out std_logic;
MCB5_wr_empty : out std_logic;
MCB5_wr_count : out std_logic_vector(6 downto 0);
MCB5_wr_underrun : out std_logic;
MCB5_wr_error : out std_logic;
MCB5_rd_clk : in std_logic;
MCB5_rd_en : in std_logic;
MCB5_rd_data : out std_logic_vector(63 downto 0);
MCB5_rd_full : out std_logic;
MCB5_rd_empty : out std_logic;
MCB5_rd_count : out std_logic_vector(6 downto 0);
MCB5_rd_overflow : out std_logic;
MCB5_rd_error : out std_logic;
FSL6_M_Clk : in std_logic;
FSL6_M_Write : in std_logic;
FSL6_M_Data : in std_logic_vector(0 to 31);
FSL6_M_Control : in std_logic;
FSL6_M_Full : out std_logic;
FSL6_S_Clk : in std_logic;
FSL6_S_Read : in std_logic;
FSL6_S_Data : out std_logic_vector(0 to 31);
FSL6_S_Control : out std_logic;
FSL6_S_Exists : out std_logic;
FSL6_B_M_Clk : in std_logic;
FSL6_B_M_Write : in std_logic;
FSL6_B_M_Data : in std_logic_vector(0 to 31);
FSL6_B_M_Control : in std_logic;
FSL6_B_M_Full : out std_logic;
FSL6_B_S_Clk : in std_logic;
FSL6_B_S_Read : in std_logic;
FSL6_B_S_Data : out std_logic_vector(0 to 31);
FSL6_B_S_Control : out std_logic;
FSL6_B_S_Exists : out std_logic;
SPLB6_Clk : in std_logic;
SPLB6_Rst : in std_logic;
SPLB6_PLB_ABus : in std_logic_vector(0 to 31);
SPLB6_PLB_PAValid : in std_logic;
SPLB6_PLB_SAValid : in std_logic;
SPLB6_PLB_masterID : in std_logic_vector(0 to 0);
SPLB6_PLB_RNW : in std_logic;
SPLB6_PLB_BE : in std_logic_vector(0 to 7);
SPLB6_PLB_UABus : in std_logic_vector(0 to 31);
SPLB6_PLB_rdPrim : in std_logic;
SPLB6_PLB_wrPrim : in std_logic;
SPLB6_PLB_abort : in std_logic;
SPLB6_PLB_busLock : in std_logic;
SPLB6_PLB_MSize : in std_logic_vector(0 to 1);
SPLB6_PLB_size : in std_logic_vector(0 to 3);
SPLB6_PLB_type : in std_logic_vector(0 to 2);
SPLB6_PLB_lockErr : in std_logic;
SPLB6_PLB_wrPendReq : in std_logic;
SPLB6_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB6_PLB_rdPendReq : in std_logic;
SPLB6_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB6_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB6_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB6_PLB_rdBurst : in std_logic;
SPLB6_PLB_wrBurst : in std_logic;
SPLB6_PLB_wrDBus : in std_logic_vector(0 to 63);
SPLB6_Sl_addrAck : out std_logic;
SPLB6_Sl_SSize : out std_logic_vector(0 to 1);
SPLB6_Sl_wait : out std_logic;
SPLB6_Sl_rearbitrate : out std_logic;
SPLB6_Sl_wrDAck : out std_logic;
SPLB6_Sl_wrComp : out std_logic;
SPLB6_Sl_wrBTerm : out std_logic;
SPLB6_Sl_rdDBus : out std_logic_vector(0 to 63);
SPLB6_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB6_Sl_rdDAck : out std_logic;
SPLB6_Sl_rdComp : out std_logic;
SPLB6_Sl_rdBTerm : out std_logic;
SPLB6_Sl_MBusy : out std_logic_vector(0 to 0);
SPLB6_Sl_MRdErr : out std_logic_vector(0 to 0);
SPLB6_Sl_MWrErr : out std_logic_vector(0 to 0);
SPLB6_Sl_MIRQ : out std_logic_vector(0 to 0);
SDMA6_Clk : in std_logic;
SDMA6_Rx_IntOut : out std_logic;
SDMA6_Tx_IntOut : out std_logic;
SDMA6_RstOut : out std_logic;
SDMA6_TX_D : out std_logic_vector(0 to 31);
SDMA6_TX_Rem : out std_logic_vector(0 to 3);
SDMA6_TX_SOF : out std_logic;
SDMA6_TX_EOF : out std_logic;
SDMA6_TX_SOP : out std_logic;
SDMA6_TX_EOP : out std_logic;
SDMA6_TX_Src_Rdy : out std_logic;
SDMA6_TX_Dst_Rdy : in std_logic;
SDMA6_RX_D : in std_logic_vector(0 to 31);
SDMA6_RX_Rem : in std_logic_vector(0 to 3);
SDMA6_RX_SOF : in std_logic;
SDMA6_RX_EOF : in std_logic;
SDMA6_RX_SOP : in std_logic;
SDMA6_RX_EOP : in std_logic;
SDMA6_RX_Src_Rdy : in std_logic;
SDMA6_RX_Dst_Rdy : out std_logic;
SDMA_CTRL6_Clk : in std_logic;
SDMA_CTRL6_Rst : in std_logic;
SDMA_CTRL6_PLB_ABus : in std_logic_vector(0 to 31);
SDMA_CTRL6_PLB_PAValid : in std_logic;
SDMA_CTRL6_PLB_SAValid : in std_logic;
SDMA_CTRL6_PLB_masterID : in std_logic_vector(0 to 0);
SDMA_CTRL6_PLB_RNW : in std_logic;
SDMA_CTRL6_PLB_BE : in std_logic_vector(0 to 7);
SDMA_CTRL6_PLB_UABus : in std_logic_vector(0 to 31);
SDMA_CTRL6_PLB_rdPrim : in std_logic;
SDMA_CTRL6_PLB_wrPrim : in std_logic;
SDMA_CTRL6_PLB_abort : in std_logic;
SDMA_CTRL6_PLB_busLock : in std_logic;
SDMA_CTRL6_PLB_MSize : in std_logic_vector(0 to 1);
SDMA_CTRL6_PLB_size : in std_logic_vector(0 to 3);
SDMA_CTRL6_PLB_type : in std_logic_vector(0 to 2);
SDMA_CTRL6_PLB_lockErr : in std_logic;
SDMA_CTRL6_PLB_wrPendReq : in std_logic;
SDMA_CTRL6_PLB_wrPendPri : in std_logic_vector(0 to 1);
SDMA_CTRL6_PLB_rdPendReq : in std_logic;
SDMA_CTRL6_PLB_rdPendPri : in std_logic_vector(0 to 1);
SDMA_CTRL6_PLB_reqPri : in std_logic_vector(0 to 1);
SDMA_CTRL6_PLB_TAttribute : in std_logic_vector(0 to 15);
SDMA_CTRL6_PLB_rdBurst : in std_logic;
SDMA_CTRL6_PLB_wrBurst : in std_logic;
SDMA_CTRL6_PLB_wrDBus : in std_logic_vector(0 to 63);
SDMA_CTRL6_Sl_addrAck : out std_logic;
SDMA_CTRL6_Sl_SSize : out std_logic_vector(0 to 1);
SDMA_CTRL6_Sl_wait : out std_logic;
SDMA_CTRL6_Sl_rearbitrate : out std_logic;
SDMA_CTRL6_Sl_wrDAck : out std_logic;
SDMA_CTRL6_Sl_wrComp : out std_logic;
SDMA_CTRL6_Sl_wrBTerm : out std_logic;
SDMA_CTRL6_Sl_rdDBus : out std_logic_vector(0 to 63);
SDMA_CTRL6_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SDMA_CTRL6_Sl_rdDAck : out std_logic;
SDMA_CTRL6_Sl_rdComp : out std_logic;
SDMA_CTRL6_Sl_rdBTerm : out std_logic;
SDMA_CTRL6_Sl_MBusy : out std_logic_vector(0 to 0);
SDMA_CTRL6_Sl_MRdErr : out std_logic_vector(0 to 0);
SDMA_CTRL6_Sl_MWrErr : out std_logic_vector(0 to 0);
SDMA_CTRL6_Sl_MIRQ : out std_logic_vector(0 to 0);
PIM6_Addr : in std_logic_vector(31 downto 0);
PIM6_AddrReq : in std_logic;
PIM6_AddrAck : out std_logic;
PIM6_RNW : in std_logic;
PIM6_Size : in std_logic_vector(3 downto 0);
PIM6_RdModWr : in std_logic;
PIM6_WrFIFO_Data : in std_logic_vector(63 downto 0);
PIM6_WrFIFO_BE : in std_logic_vector(7 downto 0);
PIM6_WrFIFO_Push : in std_logic;
PIM6_RdFIFO_Data : out std_logic_vector(63 downto 0);
PIM6_RdFIFO_Pop : in std_logic;
PIM6_RdFIFO_RdWdAddr : out std_logic_vector(3 downto 0);
PIM6_WrFIFO_Empty : out std_logic;
PIM6_WrFIFO_AlmostFull : out std_logic;
PIM6_WrFIFO_Flush : in std_logic;
PIM6_RdFIFO_Empty : out std_logic;
PIM6_RdFIFO_Flush : in std_logic;
PIM6_RdFIFO_Latency : out std_logic_vector(1 downto 0);
PIM6_InitDone : out std_logic;
PPC440MC6_MIMCReadNotWrite : in std_logic;
PPC440MC6_MIMCAddress : in std_logic_vector(0 to 35);
PPC440MC6_MIMCAddressValid : in std_logic;
PPC440MC6_MIMCWriteData : in std_logic_vector(0 to 127);
PPC440MC6_MIMCWriteDataValid : in std_logic;
PPC440MC6_MIMCByteEnable : in std_logic_vector(0 to 15);
PPC440MC6_MIMCBankConflict : in std_logic;
PPC440MC6_MIMCRowConflict : in std_logic;
PPC440MC6_MCMIReadData : out std_logic_vector(0 to 127);
PPC440MC6_MCMIReadDataValid : out std_logic;
PPC440MC6_MCMIReadDataErr : out std_logic;
PPC440MC6_MCMIAddrReadyToAccept : out std_logic;
VFBC6_Cmd_Clk : in std_logic;
VFBC6_Cmd_Reset : in std_logic;
VFBC6_Cmd_Data : in std_logic_vector(31 downto 0);
VFBC6_Cmd_Write : in std_logic;
VFBC6_Cmd_End : in std_logic;
VFBC6_Cmd_Full : out std_logic;
VFBC6_Cmd_Almost_Full : out std_logic;
VFBC6_Cmd_Idle : out std_logic;
VFBC6_Wd_Clk : in std_logic;
VFBC6_Wd_Reset : in std_logic;
VFBC6_Wd_Write : in std_logic;
VFBC6_Wd_End_Burst : in std_logic;
VFBC6_Wd_Flush : in std_logic;
VFBC6_Wd_Data : in std_logic_vector(31 downto 0);
VFBC6_Wd_Data_BE : in std_logic_vector(3 downto 0);
VFBC6_Wd_Full : out std_logic;
VFBC6_Wd_Almost_Full : out std_logic;
VFBC6_Rd_Clk : in std_logic;
VFBC6_Rd_Reset : in std_logic;
VFBC6_Rd_Read : in std_logic;
VFBC6_Rd_End_Burst : in std_logic;
VFBC6_Rd_Flush : in std_logic;
VFBC6_Rd_Data : out std_logic_vector(31 downto 0);
VFBC6_Rd_Empty : out std_logic;
VFBC6_Rd_Almost_Empty : out std_logic;
MCB6_cmd_clk : in std_logic;
MCB6_cmd_en : in std_logic;
MCB6_cmd_instr : in std_logic_vector(2 downto 0);
MCB6_cmd_bl : in std_logic_vector(5 downto 0);
MCB6_cmd_byte_addr : in std_logic_vector(29 downto 0);
MCB6_cmd_empty : out std_logic;
MCB6_cmd_full : out std_logic;
MCB6_wr_clk : in std_logic;
MCB6_wr_en : in std_logic;
MCB6_wr_mask : in std_logic_vector(7 downto 0);
MCB6_wr_data : in std_logic_vector(63 downto 0);
MCB6_wr_full : out std_logic;
MCB6_wr_empty : out std_logic;
MCB6_wr_count : out std_logic_vector(6 downto 0);
MCB6_wr_underrun : out std_logic;
MCB6_wr_error : out std_logic;
MCB6_rd_clk : in std_logic;
MCB6_rd_en : in std_logic;
MCB6_rd_data : out std_logic_vector(63 downto 0);
MCB6_rd_full : out std_logic;
MCB6_rd_empty : out std_logic;
MCB6_rd_count : out std_logic_vector(6 downto 0);
MCB6_rd_overflow : out std_logic;
MCB6_rd_error : out std_logic;
FSL7_M_Clk : in std_logic;
FSL7_M_Write : in std_logic;
FSL7_M_Data : in std_logic_vector(0 to 31);
FSL7_M_Control : in std_logic;
FSL7_M_Full : out std_logic;
FSL7_S_Clk : in std_logic;
FSL7_S_Read : in std_logic;
FSL7_S_Data : out std_logic_vector(0 to 31);
FSL7_S_Control : out std_logic;
FSL7_S_Exists : out std_logic;
FSL7_B_M_Clk : in std_logic;
FSL7_B_M_Write : in std_logic;
FSL7_B_M_Data : in std_logic_vector(0 to 31);
FSL7_B_M_Control : in std_logic;
FSL7_B_M_Full : out std_logic;
FSL7_B_S_Clk : in std_logic;
FSL7_B_S_Read : in std_logic;
FSL7_B_S_Data : out std_logic_vector(0 to 31);
FSL7_B_S_Control : out std_logic;
FSL7_B_S_Exists : out std_logic;
SPLB7_Clk : in std_logic;
SPLB7_Rst : in std_logic;
SPLB7_PLB_ABus : in std_logic_vector(0 to 31);
SPLB7_PLB_PAValid : in std_logic;
SPLB7_PLB_SAValid : in std_logic;
SPLB7_PLB_masterID : in std_logic_vector(0 to 0);
SPLB7_PLB_RNW : in std_logic;
SPLB7_PLB_BE : in std_logic_vector(0 to 7);
SPLB7_PLB_UABus : in std_logic_vector(0 to 31);
SPLB7_PLB_rdPrim : in std_logic;
SPLB7_PLB_wrPrim : in std_logic;
SPLB7_PLB_abort : in std_logic;
SPLB7_PLB_busLock : in std_logic;
SPLB7_PLB_MSize : in std_logic_vector(0 to 1);
SPLB7_PLB_size : in std_logic_vector(0 to 3);
SPLB7_PLB_type : in std_logic_vector(0 to 2);
SPLB7_PLB_lockErr : in std_logic;
SPLB7_PLB_wrPendReq : in std_logic;
SPLB7_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB7_PLB_rdPendReq : in std_logic;
SPLB7_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB7_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB7_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB7_PLB_rdBurst : in std_logic;
SPLB7_PLB_wrBurst : in std_logic;
SPLB7_PLB_wrDBus : in std_logic_vector(0 to 63);
SPLB7_Sl_addrAck : out std_logic;
SPLB7_Sl_SSize : out std_logic_vector(0 to 1);
SPLB7_Sl_wait : out std_logic;
SPLB7_Sl_rearbitrate : out std_logic;
SPLB7_Sl_wrDAck : out std_logic;
SPLB7_Sl_wrComp : out std_logic;
SPLB7_Sl_wrBTerm : out std_logic;
SPLB7_Sl_rdDBus : out std_logic_vector(0 to 63);
SPLB7_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB7_Sl_rdDAck : out std_logic;
SPLB7_Sl_rdComp : out std_logic;
SPLB7_Sl_rdBTerm : out std_logic;
SPLB7_Sl_MBusy : out std_logic_vector(0 to 0);
SPLB7_Sl_MRdErr : out std_logic_vector(0 to 0);
SPLB7_Sl_MWrErr : out std_logic_vector(0 to 0);
SPLB7_Sl_MIRQ : out std_logic_vector(0 to 0);
SDMA7_Clk : in std_logic;
SDMA7_Rx_IntOut : out std_logic;
SDMA7_Tx_IntOut : out std_logic;
SDMA7_RstOut : out std_logic;
SDMA7_TX_D : out std_logic_vector(0 to 31);
SDMA7_TX_Rem : out std_logic_vector(0 to 3);
SDMA7_TX_SOF : out std_logic;
SDMA7_TX_EOF : out std_logic;
SDMA7_TX_SOP : out std_logic;
SDMA7_TX_EOP : out std_logic;
SDMA7_TX_Src_Rdy : out std_logic;
SDMA7_TX_Dst_Rdy : in std_logic;
SDMA7_RX_D : in std_logic_vector(0 to 31);
SDMA7_RX_Rem : in std_logic_vector(0 to 3);
SDMA7_RX_SOF : in std_logic;
SDMA7_RX_EOF : in std_logic;
SDMA7_RX_SOP : in std_logic;
SDMA7_RX_EOP : in std_logic;
SDMA7_RX_Src_Rdy : in std_logic;
SDMA7_RX_Dst_Rdy : out std_logic;
SDMA_CTRL7_Clk : in std_logic;
SDMA_CTRL7_Rst : in std_logic;
SDMA_CTRL7_PLB_ABus : in std_logic_vector(0 to 31);
SDMA_CTRL7_PLB_PAValid : in std_logic;
SDMA_CTRL7_PLB_SAValid : in std_logic;
SDMA_CTRL7_PLB_masterID : in std_logic_vector(0 to 0);
SDMA_CTRL7_PLB_RNW : in std_logic;
SDMA_CTRL7_PLB_BE : in std_logic_vector(0 to 7);
SDMA_CTRL7_PLB_UABus : in std_logic_vector(0 to 31);
SDMA_CTRL7_PLB_rdPrim : in std_logic;
SDMA_CTRL7_PLB_wrPrim : in std_logic;
SDMA_CTRL7_PLB_abort : in std_logic;
SDMA_CTRL7_PLB_busLock : in std_logic;
SDMA_CTRL7_PLB_MSize : in std_logic_vector(0 to 1);
SDMA_CTRL7_PLB_size : in std_logic_vector(0 to 3);
SDMA_CTRL7_PLB_type : in std_logic_vector(0 to 2);
SDMA_CTRL7_PLB_lockErr : in std_logic;
SDMA_CTRL7_PLB_wrPendReq : in std_logic;
SDMA_CTRL7_PLB_wrPendPri : in std_logic_vector(0 to 1);
SDMA_CTRL7_PLB_rdPendReq : in std_logic;
SDMA_CTRL7_PLB_rdPendPri : in std_logic_vector(0 to 1);
SDMA_CTRL7_PLB_reqPri : in std_logic_vector(0 to 1);
SDMA_CTRL7_PLB_TAttribute : in std_logic_vector(0 to 15);
SDMA_CTRL7_PLB_rdBurst : in std_logic;
SDMA_CTRL7_PLB_wrBurst : in std_logic;
SDMA_CTRL7_PLB_wrDBus : in std_logic_vector(0 to 63);
SDMA_CTRL7_Sl_addrAck : out std_logic;
SDMA_CTRL7_Sl_SSize : out std_logic_vector(0 to 1);
SDMA_CTRL7_Sl_wait : out std_logic;
SDMA_CTRL7_Sl_rearbitrate : out std_logic;
SDMA_CTRL7_Sl_wrDAck : out std_logic;
SDMA_CTRL7_Sl_wrComp : out std_logic;
SDMA_CTRL7_Sl_wrBTerm : out std_logic;
SDMA_CTRL7_Sl_rdDBus : out std_logic_vector(0 to 63);
SDMA_CTRL7_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SDMA_CTRL7_Sl_rdDAck : out std_logic;
SDMA_CTRL7_Sl_rdComp : out std_logic;
SDMA_CTRL7_Sl_rdBTerm : out std_logic;
SDMA_CTRL7_Sl_MBusy : out std_logic_vector(0 to 0);
SDMA_CTRL7_Sl_MRdErr : out std_logic_vector(0 to 0);
SDMA_CTRL7_Sl_MWrErr : out std_logic_vector(0 to 0);
SDMA_CTRL7_Sl_MIRQ : out std_logic_vector(0 to 0);
PIM7_Addr : in std_logic_vector(31 downto 0);
PIM7_AddrReq : in std_logic;
PIM7_AddrAck : out std_logic;
PIM7_RNW : in std_logic;
PIM7_Size : in std_logic_vector(3 downto 0);
PIM7_RdModWr : in std_logic;
PIM7_WrFIFO_Data : in std_logic_vector(63 downto 0);
PIM7_WrFIFO_BE : in std_logic_vector(7 downto 0);
PIM7_WrFIFO_Push : in std_logic;
PIM7_RdFIFO_Data : out std_logic_vector(63 downto 0);
PIM7_RdFIFO_Pop : in std_logic;
PIM7_RdFIFO_RdWdAddr : out std_logic_vector(3 downto 0);
PIM7_WrFIFO_Empty : out std_logic;
PIM7_WrFIFO_AlmostFull : out std_logic;
PIM7_WrFIFO_Flush : in std_logic;
PIM7_RdFIFO_Empty : out std_logic;
PIM7_RdFIFO_Flush : in std_logic;
PIM7_RdFIFO_Latency : out std_logic_vector(1 downto 0);
PIM7_InitDone : out std_logic;
PPC440MC7_MIMCReadNotWrite : in std_logic;
PPC440MC7_MIMCAddress : in std_logic_vector(0 to 35);
PPC440MC7_MIMCAddressValid : in std_logic;
PPC440MC7_MIMCWriteData : in std_logic_vector(0 to 127);
PPC440MC7_MIMCWriteDataValid : in std_logic;
PPC440MC7_MIMCByteEnable : in std_logic_vector(0 to 15);
PPC440MC7_MIMCBankConflict : in std_logic;
PPC440MC7_MIMCRowConflict : in std_logic;
PPC440MC7_MCMIReadData : out std_logic_vector(0 to 127);
PPC440MC7_MCMIReadDataValid : out std_logic;
PPC440MC7_MCMIReadDataErr : out std_logic;
PPC440MC7_MCMIAddrReadyToAccept : out std_logic;
VFBC7_Cmd_Clk : in std_logic;
VFBC7_Cmd_Reset : in std_logic;
VFBC7_Cmd_Data : in std_logic_vector(31 downto 0);
VFBC7_Cmd_Write : in std_logic;
VFBC7_Cmd_End : in std_logic;
VFBC7_Cmd_Full : out std_logic;
VFBC7_Cmd_Almost_Full : out std_logic;
VFBC7_Cmd_Idle : out std_logic;
VFBC7_Wd_Clk : in std_logic;
VFBC7_Wd_Reset : in std_logic;
VFBC7_Wd_Write : in std_logic;
VFBC7_Wd_End_Burst : in std_logic;
VFBC7_Wd_Flush : in std_logic;
VFBC7_Wd_Data : in std_logic_vector(31 downto 0);
VFBC7_Wd_Data_BE : in std_logic_vector(3 downto 0);
VFBC7_Wd_Full : out std_logic;
VFBC7_Wd_Almost_Full : out std_logic;
VFBC7_Rd_Clk : in std_logic;
VFBC7_Rd_Reset : in std_logic;
VFBC7_Rd_Read : in std_logic;
VFBC7_Rd_End_Burst : in std_logic;
VFBC7_Rd_Flush : in std_logic;
VFBC7_Rd_Data : out std_logic_vector(31 downto 0);
VFBC7_Rd_Empty : out std_logic;
VFBC7_Rd_Almost_Empty : out std_logic;
MCB7_cmd_clk : in std_logic;
MCB7_cmd_en : in std_logic;
MCB7_cmd_instr : in std_logic_vector(2 downto 0);
MCB7_cmd_bl : in std_logic_vector(5 downto 0);
MCB7_cmd_byte_addr : in std_logic_vector(29 downto 0);
MCB7_cmd_empty : out std_logic;
MCB7_cmd_full : out std_logic;
MCB7_wr_clk : in std_logic;
MCB7_wr_en : in std_logic;
MCB7_wr_mask : in std_logic_vector(7 downto 0);
MCB7_wr_data : in std_logic_vector(63 downto 0);
MCB7_wr_full : out std_logic;
MCB7_wr_empty : out std_logic;
MCB7_wr_count : out std_logic_vector(6 downto 0);
MCB7_wr_underrun : out std_logic;
MCB7_wr_error : out std_logic;
MCB7_rd_clk : in std_logic;
MCB7_rd_en : in std_logic;
MCB7_rd_data : out std_logic_vector(63 downto 0);
MCB7_rd_full : out std_logic;
MCB7_rd_empty : out std_logic;
MCB7_rd_count : out std_logic_vector(6 downto 0);
MCB7_rd_overflow : out std_logic;
MCB7_rd_error : out std_logic;
MPMC_CTRL_Clk : in std_logic;
MPMC_CTRL_Rst : in std_logic;
MPMC_CTRL_PLB_ABus : in std_logic_vector(0 to 31);
MPMC_CTRL_PLB_PAValid : in std_logic;
MPMC_CTRL_PLB_SAValid : in std_logic;
MPMC_CTRL_PLB_masterID : in std_logic_vector(0 to 0);
MPMC_CTRL_PLB_RNW : in std_logic;
MPMC_CTRL_PLB_BE : in std_logic_vector(0 to 7);
MPMC_CTRL_PLB_UABus : in std_logic_vector(0 to 31);
MPMC_CTRL_PLB_rdPrim : in std_logic;
MPMC_CTRL_PLB_wrPrim : in std_logic;
MPMC_CTRL_PLB_abort : in std_logic;
MPMC_CTRL_PLB_busLock : in std_logic;
MPMC_CTRL_PLB_MSize : in std_logic_vector(0 to 1);
MPMC_CTRL_PLB_size : in std_logic_vector(0 to 3);
MPMC_CTRL_PLB_type : in std_logic_vector(0 to 2);
MPMC_CTRL_PLB_lockErr : in std_logic;
MPMC_CTRL_PLB_wrPendReq : in std_logic;
MPMC_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1);
MPMC_CTRL_PLB_rdPendReq : in std_logic;
MPMC_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1);
MPMC_CTRL_PLB_reqPri : in std_logic_vector(0 to 1);
MPMC_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15);
MPMC_CTRL_PLB_rdBurst : in std_logic;
MPMC_CTRL_PLB_wrBurst : in std_logic;
MPMC_CTRL_PLB_wrDBus : in std_logic_vector(0 to 63);
MPMC_CTRL_Sl_addrAck : out std_logic;
MPMC_CTRL_Sl_SSize : out std_logic_vector(0 to 1);
MPMC_CTRL_Sl_wait : out std_logic;
MPMC_CTRL_Sl_rearbitrate : out std_logic;
MPMC_CTRL_Sl_wrDAck : out std_logic;
MPMC_CTRL_Sl_wrComp : out std_logic;
MPMC_CTRL_Sl_wrBTerm : out std_logic;
MPMC_CTRL_Sl_rdDBus : out std_logic_vector(0 to 63);
MPMC_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3);
MPMC_CTRL_Sl_rdDAck : out std_logic;
MPMC_CTRL_Sl_rdComp : out std_logic;
MPMC_CTRL_Sl_rdBTerm : out std_logic;
MPMC_CTRL_Sl_MBusy : out std_logic_vector(0 to 0);
MPMC_CTRL_Sl_MRdErr : out std_logic_vector(0 to 0);
MPMC_CTRL_Sl_MWrErr : out std_logic_vector(0 to 0);
MPMC_CTRL_Sl_MIRQ : out std_logic_vector(0 to 0);
MPMC_Clk0 : in std_logic;
MPMC_Clk0_DIV2 : in std_logic;
MPMC_Clk90 : in std_logic;
MPMC_Clk_200MHz : in std_logic;
MPMC_Rst : in std_logic;
MPMC_Clk_Mem : in std_logic;
MPMC_Clk_Mem_2x : in std_logic;
MPMC_Clk_Mem_2x_180 : in std_logic;
MPMC_Clk_Mem_2x_CE0 : in std_logic;
MPMC_Clk_Mem_2x_CE90 : in std_logic;
MPMC_Clk_Rd_Base : in std_logic;
MPMC_Clk_Mem_2x_bufpll_o : out std_logic;
MPMC_Clk_Mem_2x_180_bufpll_o : out std_logic;
MPMC_Clk_Mem_2x_CE0_bufpll_o : out std_logic;
MPMC_Clk_Mem_2x_CE90_bufpll_o : out std_logic;
MPMC_PLL_Lock_bufpll_o : out std_logic;
MPMC_PLL_Lock : in std_logic;
MPMC_Idelayctrl_Rdy_I : in std_logic;
MPMC_Idelayctrl_Rdy_O : out std_logic;
MPMC_InitDone : out std_logic;
MPMC_ECC_Intr : out std_logic;
MPMC_DCM_PSEN : out std_logic;
MPMC_DCM_PSINCDEC : out std_logic;
MPMC_DCM_PSDONE : in std_logic;
MPMC_MCB_DRP_Clk : in std_logic;
SDRAM_Clk : out std_logic_vector(1 downto 0);
SDRAM_CE : out std_logic_vector(1 downto 0);
SDRAM_CS_n : out std_logic_vector(1 downto 0);
SDRAM_RAS_n : out std_logic;
SDRAM_CAS_n : out std_logic;
SDRAM_WE_n : out std_logic;
SDRAM_BankAddr : out std_logic_vector(1 downto 0);
SDRAM_Addr : out std_logic_vector(12 downto 0);
SDRAM_DQ : inout std_logic_vector(63 downto 0);
SDRAM_DM : out std_logic_vector(7 downto 0);
DDR_Clk : out std_logic_vector(1 downto 0);
DDR_Clk_n : out std_logic_vector(1 downto 0);
DDR_CE : out std_logic_vector(1 downto 0);
DDR_CS_n : out std_logic_vector(1 downto 0);
DDR_RAS_n : out std_logic;
DDR_CAS_n : out std_logic;
DDR_WE_n : out std_logic;
DDR_BankAddr : out std_logic_vector(1 downto 0);
DDR_Addr : out std_logic_vector(12 downto 0);
DDR_DQ : inout std_logic_vector(63 downto 0);
DDR_DM : out std_logic_vector(7 downto 0);
DDR_DQS : inout std_logic_vector(7 downto 0);
DDR_DQS_Div_O : out std_logic;
DDR_DQS_Div_I : in std_logic;
DDR2_Clk : out std_logic_vector(1 downto 0);
DDR2_Clk_n : out std_logic_vector(1 downto 0);
DDR2_CE : out std_logic_vector(1 downto 0);
DDR2_CS_n : out std_logic_vector(1 downto 0);
DDR2_ODT : out std_logic_vector(1 downto 0);
DDR2_RAS_n : out std_logic;
DDR2_CAS_n : out std_logic;
DDR2_WE_n : out std_logic;
DDR2_BankAddr : out std_logic_vector(1 downto 0);
DDR2_Addr : out std_logic_vector(12 downto 0);
DDR2_DQ : inout std_logic_vector(63 downto 0);
DDR2_DM : out std_logic_vector(7 downto 0);
DDR2_DQS : inout std_logic_vector(7 downto 0);
DDR2_DQS_n : inout std_logic_vector(7 downto 0);
DDR2_DQS_Div_O : out std_logic;
DDR2_DQS_Div_I : in std_logic;
DDR3_Clk : out std_logic_vector(1 downto 0);
DDR3_Clk_n : out std_logic_vector(1 downto 0);
DDR3_CE : out std_logic_vector(1 downto 0);
DDR3_CS_n : out std_logic_vector(1 downto 0);
DDR3_ODT : out std_logic_vector(1 downto 0);
DDR3_RAS_n : out std_logic;
DDR3_CAS_n : out std_logic;
DDR3_WE_n : out std_logic;
DDR3_BankAddr : out std_logic_vector(1 downto 0);
DDR3_Addr : out std_logic_vector(12 downto 0);
DDR3_DQ : inout std_logic_vector(63 downto 0);
DDR3_DM : out std_logic_vector(7 downto 0);
DDR3_Reset_n : out std_logic;
DDR3_DQS : inout std_logic_vector(7 downto 0);
DDR3_DQS_n : inout std_logic_vector(7 downto 0);
mcbx_dram_addr : out std_logic_vector(12 downto 0);
mcbx_dram_ba : out std_logic_vector(1 downto 0);
mcbx_dram_ras_n : out std_logic;
mcbx_dram_cas_n : out std_logic;
mcbx_dram_we_n : out std_logic;
mcbx_dram_cke : out std_logic;
mcbx_dram_clk : out std_logic;
mcbx_dram_clk_n : out std_logic;
mcbx_dram_dq : inout std_logic_vector(63 downto 0);
mcbx_dram_dqs : inout std_logic;
mcbx_dram_dqs_n : inout std_logic;
mcbx_dram_udqs : inout std_logic;
mcbx_dram_udqs_n : inout std_logic;
mcbx_dram_udm : out std_logic;
mcbx_dram_ldm : out std_logic;
mcbx_dram_odt : out std_logic;
mcbx_dram_ddr3_rst : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic;
calib_recal : in std_logic;
rzq : inout std_logic;
zio : inout std_logic
);
end component;
component system_sram_wrapper is
port (
MCH_SPLB_Clk : in std_logic;
RdClk : in std_logic;
MCH_SPLB_Rst : in std_logic;
MCH0_Access_Control : in std_logic;
MCH0_Access_Data : in std_logic_vector(0 to 31);
MCH0_Access_Write : in std_logic;
MCH0_Access_Full : out std_logic;
MCH0_ReadData_Control : out std_logic;
MCH0_ReadData_Data : out std_logic_vector(0 to 31);
MCH0_ReadData_Read : in std_logic;
MCH0_ReadData_Exists : out std_logic;
MCH1_Access_Control : in std_logic;
MCH1_Access_Data : in std_logic_vector(0 to 31);
MCH1_Access_Write : in std_logic;
MCH1_Access_Full : out std_logic;
MCH1_ReadData_Control : out std_logic;
MCH1_ReadData_Data : out std_logic_vector(0 to 31);
MCH1_ReadData_Read : in std_logic;
MCH1_ReadData_Exists : out std_logic;
MCH2_Access_Control : in std_logic;
MCH2_Access_Data : in std_logic_vector(0 to 31);
MCH2_Access_Write : in std_logic;
MCH2_Access_Full : out std_logic;
MCH2_ReadData_Control : out std_logic;
MCH2_ReadData_Data : out std_logic_vector(0 to 31);
MCH2_ReadData_Read : in std_logic;
MCH2_ReadData_Exists : out std_logic;
MCH3_Access_Control : in std_logic;
MCH3_Access_Data : in std_logic_vector(0 to 31);
MCH3_Access_Write : in std_logic;
MCH3_Access_Full : out std_logic;
MCH3_ReadData_Control : out std_logic;
MCH3_ReadData_Data : out std_logic_vector(0 to 31);
MCH3_ReadData_Read : in std_logic;
MCH3_ReadData_Exists : out std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 2);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 7);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 63);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 63);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 5);
Sl_MWrErr : out std_logic_vector(0 to 5);
Sl_MRdErr : out std_logic_vector(0 to 5);
Sl_MIRQ : out std_logic_vector(0 to 5);
Mem_DQ_I : in std_logic_vector(0 to 31);
Mem_DQ_O : out std_logic_vector(0 to 31);
Mem_DQ_T : out std_logic_vector(0 to 31);
Mem_A : out std_logic_vector(0 to 31);
Mem_RPN : out std_logic;
Mem_CEN : out std_logic_vector(0 to 0);
Mem_OEN : out std_logic_vector(0 to 0);
Mem_WEN : out std_logic;
Mem_QWEN : out std_logic_vector(0 to 3);
Mem_BEN : out std_logic_vector(0 to 3);
Mem_CE : out std_logic_vector(0 to 0);
Mem_ADV_LDN : out std_logic;
Mem_LBON : out std_logic;
Mem_CKEN : out std_logic;
Mem_RNW : out std_logic
);
end component;
component system_pcie_bridge_wrapper is
port (
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to 63);
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrBTerm : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_buslock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to 7);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_TAttribute : out std_logic_vector(0 to 15);
M_UABus : out std_logic_vector(0 to 31);
M_ABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to 63);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 2);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 7);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 63);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 63);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 5);
Sl_MWrErr : out std_logic_vector(0 to 5);
Sl_MRdErr : out std_logic_vector(0 to 5);
Sl_MIRQ : out std_logic_vector(0 to 5);
REFCLK : in std_logic;
Bridge_Clk : out std_logic;
RXN : in std_logic_vector(0 to 0);
RXP : in std_logic_vector(0 to 0);
TXN : out std_logic_vector(0 to 0);
TXP : out std_logic_vector(0 to 0);
IP2INTC_Irpt : out std_logic;
MSI_request : in std_logic
);
end component;
component system_xps_central_dma_1_wrapper is
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
SPLB_ABus : in std_logic_vector(0 to 31);
SPLB_BE : in std_logic_vector(0 to 7);
SPLB_UABus : in std_logic_vector(0 to 31);
SPLB_PAValid : in std_logic;
SPLB_SAValid : in std_logic;
SPLB_rdPrim : in std_logic;
SPLB_wrPrim : in std_logic;
SPLB_masterID : in std_logic_vector(0 to 2);
SPLB_abort : in std_logic;
SPLB_busLock : in std_logic;
SPLB_RNW : in std_logic;
SPLB_MSize : in std_logic_vector(0 to 1);
SPLB_size : in std_logic_vector(0 to 3);
SPLB_type : in std_logic_vector(0 to 2);
SPLB_lockErr : in std_logic;
SPLB_wrDBus : in std_logic_vector(0 to 63);
SPLB_wrBurst : in std_logic;
SPLB_rdBurst : in std_logic;
SPLB_wrPendReq : in std_logic;
SPLB_rdPendReq : in std_logic;
SPLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_reqPri : in std_logic_vector(0 to 1);
SPLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 63);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 5);
Sl_MWrErr : out std_logic_vector(0 to 5);
Sl_MRdErr : out std_logic_vector(0 to 5);
Sl_MIRQ : out std_logic_vector(0 to 5);
IP2INTC_Irpt : out std_logic;
MPLB_MAddrAck : in std_logic;
MPLB_MSSize : in std_logic_vector(0 to 1);
MPLB_MRearbitrate : in std_logic;
MPLB_MTimeout : in std_logic;
MPLB_MBusy : in std_logic;
MPLB_MRdErr : in std_logic;
MPLB_MWrErr : in std_logic;
MPLB_MIRQ : in std_logic;
MPLB_MRdDBus : in std_logic_vector(0 to 63);
MPLB_MRdWdAddr : in std_logic_vector(0 to 3);
MPLB_MRdDAck : in std_logic;
MPLB_MRdBTerm : in std_logic;
MPLB_MWrDAck : in std_logic;
MPLB_MWrBTerm : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to 7);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
M_ABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to 63);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic
);
end component;
component system_clock_generator_0_wrapper is
port (
CLKIN : in std_logic;
CLKOUT0 : out std_logic;
CLKOUT1 : out std_logic;
CLKOUT2 : out std_logic;
CLKOUT3 : out std_logic;
CLKOUT4 : out std_logic;
CLKOUT5 : out std_logic;
CLKOUT6 : out std_logic;
CLKOUT7 : out std_logic;
CLKOUT8 : out std_logic;
CLKOUT9 : out std_logic;
CLKOUT10 : out std_logic;
CLKOUT11 : out std_logic;
CLKOUT12 : out std_logic;
CLKOUT13 : out std_logic;
CLKOUT14 : out std_logic;
CLKOUT15 : out std_logic;
CLKFBIN : in std_logic;
CLKFBOUT : out std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
PSDONE : out std_logic;
RST : in std_logic;
LOCKED : out std_logic
);
end component;
component system_mdm_0_wrapper is
port (
Interrupt : out std_logic;
Debug_SYS_Rst : out std_logic;
Ext_BRK : out std_logic;
Ext_NM_BRK : out std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 2);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 7);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 63);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 63);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 5);
Sl_MWrErr : out std_logic_vector(0 to 5);
Sl_MRdErr : out std_logic_vector(0 to 5);
Sl_MIRQ : out std_logic_vector(0 to 5);
Dbg_Clk_0 : out std_logic;
Dbg_TDI_0 : out std_logic;
Dbg_TDO_0 : in std_logic;
Dbg_Reg_En_0 : out std_logic_vector(0 to 7);
Dbg_Capture_0 : out std_logic;
Dbg_Shift_0 : out std_logic;
Dbg_Update_0 : out std_logic;
Dbg_Rst_0 : out std_logic;
Dbg_Clk_1 : out std_logic;
Dbg_TDI_1 : out std_logic;
Dbg_TDO_1 : in std_logic;
Dbg_Reg_En_1 : out std_logic_vector(0 to 7);
Dbg_Capture_1 : out std_logic;
Dbg_Shift_1 : out std_logic;
Dbg_Update_1 : out std_logic;
Dbg_Rst_1 : out std_logic;
Dbg_Clk_2 : out std_logic;
Dbg_TDI_2 : out std_logic;
Dbg_TDO_2 : in std_logic;
Dbg_Reg_En_2 : out std_logic_vector(0 to 7);
Dbg_Capture_2 : out std_logic;
Dbg_Shift_2 : out std_logic;
Dbg_Update_2 : out std_logic;
Dbg_Rst_2 : out std_logic;
Dbg_Clk_3 : out std_logic;
Dbg_TDI_3 : out std_logic;
Dbg_TDO_3 : in std_logic;
Dbg_Reg_En_3 : out std_logic_vector(0 to 7);
Dbg_Capture_3 : out std_logic;
Dbg_Shift_3 : out std_logic;
Dbg_Update_3 : out std_logic;
Dbg_Rst_3 : out std_logic;
Dbg_Clk_4 : out std_logic;
Dbg_TDI_4 : out std_logic;
Dbg_TDO_4 : in std_logic;
Dbg_Reg_En_4 : out std_logic_vector(0 to 7);
Dbg_Capture_4 : out std_logic;
Dbg_Shift_4 : out std_logic;
Dbg_Update_4 : out std_logic;
Dbg_Rst_4 : out std_logic;
Dbg_Clk_5 : out std_logic;
Dbg_TDI_5 : out std_logic;
Dbg_TDO_5 : in std_logic;
Dbg_Reg_En_5 : out std_logic_vector(0 to 7);
Dbg_Capture_5 : out std_logic;
Dbg_Shift_5 : out std_logic;
Dbg_Update_5 : out std_logic;
Dbg_Rst_5 : out std_logic;
Dbg_Clk_6 : out std_logic;
Dbg_TDI_6 : out std_logic;
Dbg_TDO_6 : in std_logic;
Dbg_Reg_En_6 : out std_logic_vector(0 to 7);
Dbg_Capture_6 : out std_logic;
Dbg_Shift_6 : out std_logic;
Dbg_Update_6 : out std_logic;
Dbg_Rst_6 : out std_logic;
Dbg_Clk_7 : out std_logic;
Dbg_TDI_7 : out std_logic;
Dbg_TDO_7 : in std_logic;
Dbg_Reg_En_7 : out std_logic_vector(0 to 7);
Dbg_Capture_7 : out std_logic;
Dbg_Shift_7 : out std_logic;
Dbg_Update_7 : out std_logic;
Dbg_Rst_7 : out std_logic;
Dbg_Clk_8 : out std_logic;
Dbg_TDI_8 : out std_logic;
Dbg_TDO_8 : in std_logic;
Dbg_Reg_En_8 : out std_logic_vector(0 to 7);
Dbg_Capture_8 : out std_logic;
Dbg_Shift_8 : out std_logic;
Dbg_Update_8 : out std_logic;
Dbg_Rst_8 : out std_logic;
Dbg_Clk_9 : out std_logic;
Dbg_TDI_9 : out std_logic;
Dbg_TDO_9 : in std_logic;
Dbg_Reg_En_9 : out std_logic_vector(0 to 7);
Dbg_Capture_9 : out std_logic;
Dbg_Shift_9 : out std_logic;
Dbg_Update_9 : out std_logic;
Dbg_Rst_9 : out std_logic;
Dbg_Clk_10 : out std_logic;
Dbg_TDI_10 : out std_logic;
Dbg_TDO_10 : in std_logic;
Dbg_Reg_En_10 : out std_logic_vector(0 to 7);
Dbg_Capture_10 : out std_logic;
Dbg_Shift_10 : out std_logic;
Dbg_Update_10 : out std_logic;
Dbg_Rst_10 : out std_logic;
Dbg_Clk_11 : out std_logic;
Dbg_TDI_11 : out std_logic;
Dbg_TDO_11 : in std_logic;
Dbg_Reg_En_11 : out std_logic_vector(0 to 7);
Dbg_Capture_11 : out std_logic;
Dbg_Shift_11 : out std_logic;
Dbg_Update_11 : out std_logic;
Dbg_Rst_11 : out std_logic;
Dbg_Clk_12 : out std_logic;
Dbg_TDI_12 : out std_logic;
Dbg_TDO_12 : in std_logic;
Dbg_Reg_En_12 : out std_logic_vector(0 to 7);
Dbg_Capture_12 : out std_logic;
Dbg_Shift_12 : out std_logic;
Dbg_Update_12 : out std_logic;
Dbg_Rst_12 : out std_logic;
Dbg_Clk_13 : out std_logic;
Dbg_TDI_13 : out std_logic;
Dbg_TDO_13 : in std_logic;
Dbg_Reg_En_13 : out std_logic_vector(0 to 7);
Dbg_Capture_13 : out std_logic;
Dbg_Shift_13 : out std_logic;
Dbg_Update_13 : out std_logic;
Dbg_Rst_13 : out std_logic;
Dbg_Clk_14 : out std_logic;
Dbg_TDI_14 : out std_logic;
Dbg_TDO_14 : in std_logic;
Dbg_Reg_En_14 : out std_logic_vector(0 to 7);
Dbg_Capture_14 : out std_logic;
Dbg_Shift_14 : out std_logic;
Dbg_Update_14 : out std_logic;
Dbg_Rst_14 : out std_logic;
Dbg_Clk_15 : out std_logic;
Dbg_TDI_15 : out std_logic;
Dbg_TDO_15 : in std_logic;
Dbg_Reg_En_15 : out std_logic_vector(0 to 7);
Dbg_Capture_15 : out std_logic;
Dbg_Shift_15 : out std_logic;
Dbg_Update_15 : out std_logic;
Dbg_Rst_15 : out std_logic;
Dbg_Clk_16 : out std_logic;
Dbg_TDI_16 : out std_logic;
Dbg_TDO_16 : in std_logic;
Dbg_Reg_En_16 : out std_logic_vector(0 to 7);
Dbg_Capture_16 : out std_logic;
Dbg_Shift_16 : out std_logic;
Dbg_Update_16 : out std_logic;
Dbg_Rst_16 : out std_logic;
Dbg_Clk_17 : out std_logic;
Dbg_TDI_17 : out std_logic;
Dbg_TDO_17 : in std_logic;
Dbg_Reg_En_17 : out std_logic_vector(0 to 7);
Dbg_Capture_17 : out std_logic;
Dbg_Shift_17 : out std_logic;
Dbg_Update_17 : out std_logic;
Dbg_Rst_17 : out std_logic;
Dbg_Clk_18 : out std_logic;
Dbg_TDI_18 : out std_logic;
Dbg_TDO_18 : in std_logic;
Dbg_Reg_En_18 : out std_logic_vector(0 to 7);
Dbg_Capture_18 : out std_logic;
Dbg_Shift_18 : out std_logic;
Dbg_Update_18 : out std_logic;
Dbg_Rst_18 : out std_logic;
Dbg_Clk_19 : out std_logic;
Dbg_TDI_19 : out std_logic;
Dbg_TDO_19 : in std_logic;
Dbg_Reg_En_19 : out std_logic_vector(0 to 7);
Dbg_Capture_19 : out std_logic;
Dbg_Shift_19 : out std_logic;
Dbg_Update_19 : out std_logic;
Dbg_Rst_19 : out std_logic;
Dbg_Clk_20 : out std_logic;
Dbg_TDI_20 : out std_logic;
Dbg_TDO_20 : in std_logic;
Dbg_Reg_En_20 : out std_logic_vector(0 to 7);
Dbg_Capture_20 : out std_logic;
Dbg_Shift_20 : out std_logic;
Dbg_Update_20 : out std_logic;
Dbg_Rst_20 : out std_logic;
Dbg_Clk_21 : out std_logic;
Dbg_TDI_21 : out std_logic;
Dbg_TDO_21 : in std_logic;
Dbg_Reg_En_21 : out std_logic_vector(0 to 7);
Dbg_Capture_21 : out std_logic;
Dbg_Shift_21 : out std_logic;
Dbg_Update_21 : out std_logic;
Dbg_Rst_21 : out std_logic;
Dbg_Clk_22 : out std_logic;
Dbg_TDI_22 : out std_logic;
Dbg_TDO_22 : in std_logic;
Dbg_Reg_En_22 : out std_logic_vector(0 to 7);
Dbg_Capture_22 : out std_logic;
Dbg_Shift_22 : out std_logic;
Dbg_Update_22 : out std_logic;
Dbg_Rst_22 : out std_logic;
Dbg_Clk_23 : out std_logic;
Dbg_TDI_23 : out std_logic;
Dbg_TDO_23 : in std_logic;
Dbg_Reg_En_23 : out std_logic_vector(0 to 7);
Dbg_Capture_23 : out std_logic;
Dbg_Shift_23 : out std_logic;
Dbg_Update_23 : out std_logic;
Dbg_Rst_23 : out std_logic;
Dbg_Clk_24 : out std_logic;
Dbg_TDI_24 : out std_logic;
Dbg_TDO_24 : in std_logic;
Dbg_Reg_En_24 : out std_logic_vector(0 to 7);
Dbg_Capture_24 : out std_logic;
Dbg_Shift_24 : out std_logic;
Dbg_Update_24 : out std_logic;
Dbg_Rst_24 : out std_logic;
Dbg_Clk_25 : out std_logic;
Dbg_TDI_25 : out std_logic;
Dbg_TDO_25 : in std_logic;
Dbg_Reg_En_25 : out std_logic_vector(0 to 7);
Dbg_Capture_25 : out std_logic;
Dbg_Shift_25 : out std_logic;
Dbg_Update_25 : out std_logic;
Dbg_Rst_25 : out std_logic;
Dbg_Clk_26 : out std_logic;
Dbg_TDI_26 : out std_logic;
Dbg_TDO_26 : in std_logic;
Dbg_Reg_En_26 : out std_logic_vector(0 to 7);
Dbg_Capture_26 : out std_logic;
Dbg_Shift_26 : out std_logic;
Dbg_Update_26 : out std_logic;
Dbg_Rst_26 : out std_logic;
Dbg_Clk_27 : out std_logic;
Dbg_TDI_27 : out std_logic;
Dbg_TDO_27 : in std_logic;
Dbg_Reg_En_27 : out std_logic_vector(0 to 7);
Dbg_Capture_27 : out std_logic;
Dbg_Shift_27 : out std_logic;
Dbg_Update_27 : out std_logic;
Dbg_Rst_27 : out std_logic;
Dbg_Clk_28 : out std_logic;
Dbg_TDI_28 : out std_logic;
Dbg_TDO_28 : in std_logic;
Dbg_Reg_En_28 : out std_logic_vector(0 to 7);
Dbg_Capture_28 : out std_logic;
Dbg_Shift_28 : out std_logic;
Dbg_Update_28 : out std_logic;
Dbg_Rst_28 : out std_logic;
Dbg_Clk_29 : out std_logic;
Dbg_TDI_29 : out std_logic;
Dbg_TDO_29 : in std_logic;
Dbg_Reg_En_29 : out std_logic_vector(0 to 7);
Dbg_Capture_29 : out std_logic;
Dbg_Shift_29 : out std_logic;
Dbg_Update_29 : out std_logic;
Dbg_Rst_29 : out std_logic;
Dbg_Clk_30 : out std_logic;
Dbg_TDI_30 : out std_logic;
Dbg_TDO_30 : in std_logic;
Dbg_Reg_En_30 : out std_logic_vector(0 to 7);
Dbg_Capture_30 : out std_logic;
Dbg_Shift_30 : out std_logic;
Dbg_Update_30 : out std_logic;
Dbg_Rst_30 : out std_logic;
Dbg_Clk_31 : out std_logic;
Dbg_TDI_31 : out std_logic;
Dbg_TDO_31 : in std_logic;
Dbg_Reg_En_31 : out std_logic_vector(0 to 7);
Dbg_Capture_31 : out std_logic;
Dbg_Shift_31 : out std_logic;
Dbg_Update_31 : out std_logic;
Dbg_Rst_31 : out std_logic;
bscan_tdi : out std_logic;
bscan_reset : out std_logic;
bscan_shift : out std_logic;
bscan_update : out std_logic;
bscan_capture : out std_logic;
bscan_sel1 : out std_logic;
bscan_drck1 : out std_logic;
bscan_tdo1 : in std_logic;
bscan_ext_tdi : in std_logic;
bscan_ext_reset : in std_logic;
bscan_ext_shift : in std_logic;
bscan_ext_update : in std_logic;
bscan_ext_capture : in std_logic;
bscan_ext_sel : in std_logic;
bscan_ext_drck : in std_logic;
bscan_ext_tdo : out std_logic;
Ext_JTAG_DRCK : out std_logic;
Ext_JTAG_RESET : out std_logic;
Ext_JTAG_SEL : out std_logic;
Ext_JTAG_CAPTURE : out std_logic;
Ext_JTAG_SHIFT : out std_logic;
Ext_JTAG_UPDATE : out std_logic;
Ext_JTAG_TDI : out std_logic;
Ext_JTAG_TDO : in std_logic
);
end component;
component system_proc_sys_reset_0_wrapper is
port (
Slowest_sync_clk : in std_logic;
Ext_Reset_In : in std_logic;
Aux_Reset_In : in std_logic;
MB_Debug_Sys_Rst : in std_logic;
Core_Reset_Req_0 : in std_logic;
Chip_Reset_Req_0 : in std_logic;
System_Reset_Req_0 : in std_logic;
Core_Reset_Req_1 : in std_logic;
Chip_Reset_Req_1 : in std_logic;
System_Reset_Req_1 : in std_logic;
Dcm_locked : in std_logic;
RstcPPCresetcore_0 : out std_logic;
RstcPPCresetchip_0 : out std_logic;
RstcPPCresetsys_0 : out std_logic;
RstcPPCresetcore_1 : out std_logic;
RstcPPCresetchip_1 : out std_logic;
RstcPPCresetsys_1 : out std_logic;
MB_Reset : out std_logic;
Bus_Struct_Reset : out std_logic_vector(0 to 0);
Peripheral_Reset : out std_logic_vector(0 to 0);
Interconnect_aresetn : out std_logic_vector(0 to 0);
Peripheral_aresetn : out std_logic_vector(0 to 0)
);
end component;
component system_xps_intc_0_wrapper is
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_masterID : in std_logic_vector(0 to 2);
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 7);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_wrDBus : in std_logic_vector(0 to 63);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_MSize : in std_logic_vector(0 to 1);
PLB_lockErr : in std_logic;
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 63);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 5);
Sl_MWrErr : out std_logic_vector(0 to 5);
Sl_MRdErr : out std_logic_vector(0 to 5);
Sl_wrBTerm : out std_logic;
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdBTerm : out std_logic;
Sl_MIRQ : out std_logic_vector(0 to 5);
Intr : in std_logic_vector(1 downto 0);
Irq : out std_logic
);
end component;
component system_nfa_accept_samples_generic_hw_top_0_wrapper is
port (
aclk : in std_logic;
aresetn : in std_logic;
indices_MPLB_Clk : in std_logic;
indices_MPLB_Rst : in std_logic;
indices_M_request : out std_logic;
indices_M_priority : out std_logic_vector(0 to 1);
indices_M_busLock : out std_logic;
indices_M_RNW : out std_logic;
indices_M_BE : out std_logic_vector(0 to 7);
indices_M_MSize : out std_logic_vector(0 to 1);
indices_M_size : out std_logic_vector(0 to 3);
indices_M_type : out std_logic_vector(0 to 2);
indices_M_TAttribute : out std_logic_vector(0 to 15);
indices_M_lockErr : out std_logic;
indices_M_abort : out std_logic;
indices_M_UABus : out std_logic_vector(0 to 31);
indices_M_ABus : out std_logic_vector(0 to 31);
indices_M_wrDBus : out std_logic_vector(0 to 63);
indices_M_wrBurst : out std_logic;
indices_M_rdBurst : out std_logic;
indices_PLB_MAddrAck : in std_logic;
indices_PLB_MSSize : in std_logic_vector(0 to 1);
indices_PLB_MRearbitrate : in std_logic;
indices_PLB_MTimeout : in std_logic;
indices_PLB_MBusy : in std_logic;
indices_PLB_MRdErr : in std_logic;
indices_PLB_MWrErr : in std_logic;
indices_PLB_MIRQ : in std_logic;
indices_PLB_MRdDBus : in std_logic_vector(0 to 63);
indices_PLB_MRdWdAddr : in std_logic_vector(0 to 3);
indices_PLB_MRdDAck : in std_logic;
indices_PLB_MRdBTerm : in std_logic;
indices_PLB_MWrDAck : in std_logic;
indices_PLB_MWrBTerm : in std_logic;
nfa_finals_buckets_MPLB_Clk : in std_logic;
nfa_finals_buckets_MPLB_Rst : in std_logic;
nfa_finals_buckets_M_request : out std_logic;
nfa_finals_buckets_M_priority : out std_logic_vector(0 to 1);
nfa_finals_buckets_M_busLock : out std_logic;
nfa_finals_buckets_M_RNW : out std_logic;
nfa_finals_buckets_M_BE : out std_logic_vector(0 to 7);
nfa_finals_buckets_M_MSize : out std_logic_vector(0 to 1);
nfa_finals_buckets_M_size : out std_logic_vector(0 to 3);
nfa_finals_buckets_M_type : out std_logic_vector(0 to 2);
nfa_finals_buckets_M_TAttribute : out std_logic_vector(0 to 15);
nfa_finals_buckets_M_lockErr : out std_logic;
nfa_finals_buckets_M_abort : out std_logic;
nfa_finals_buckets_M_UABus : out std_logic_vector(0 to 31);
nfa_finals_buckets_M_ABus : out std_logic_vector(0 to 31);
nfa_finals_buckets_M_wrDBus : out std_logic_vector(0 to 63);
nfa_finals_buckets_M_wrBurst : out std_logic;
nfa_finals_buckets_M_rdBurst : out std_logic;
nfa_finals_buckets_PLB_MAddrAck : in std_logic;
nfa_finals_buckets_PLB_MSSize : in std_logic_vector(0 to 1);
nfa_finals_buckets_PLB_MRearbitrate : in std_logic;
nfa_finals_buckets_PLB_MTimeout : in std_logic;
nfa_finals_buckets_PLB_MBusy : in std_logic;
nfa_finals_buckets_PLB_MRdErr : in std_logic;
nfa_finals_buckets_PLB_MWrErr : in std_logic;
nfa_finals_buckets_PLB_MIRQ : in std_logic;
nfa_finals_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63);
nfa_finals_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3);
nfa_finals_buckets_PLB_MRdDAck : in std_logic;
nfa_finals_buckets_PLB_MRdBTerm : in std_logic;
nfa_finals_buckets_PLB_MWrDAck : in std_logic;
nfa_finals_buckets_PLB_MWrBTerm : in std_logic;
nfa_forward_buckets_MPLB_Clk : in std_logic;
nfa_forward_buckets_MPLB_Rst : in std_logic;
nfa_forward_buckets_M_request : out std_logic;
nfa_forward_buckets_M_priority : out std_logic_vector(0 to 1);
nfa_forward_buckets_M_busLock : out std_logic;
nfa_forward_buckets_M_RNW : out std_logic;
nfa_forward_buckets_M_BE : out std_logic_vector(0 to 7);
nfa_forward_buckets_M_MSize : out std_logic_vector(0 to 1);
nfa_forward_buckets_M_size : out std_logic_vector(0 to 3);
nfa_forward_buckets_M_type : out std_logic_vector(0 to 2);
nfa_forward_buckets_M_TAttribute : out std_logic_vector(0 to 15);
nfa_forward_buckets_M_lockErr : out std_logic;
nfa_forward_buckets_M_abort : out std_logic;
nfa_forward_buckets_M_UABus : out std_logic_vector(0 to 31);
nfa_forward_buckets_M_ABus : out std_logic_vector(0 to 31);
nfa_forward_buckets_M_wrDBus : out std_logic_vector(0 to 63);
nfa_forward_buckets_M_wrBurst : out std_logic;
nfa_forward_buckets_M_rdBurst : out std_logic;
nfa_forward_buckets_PLB_MAddrAck : in std_logic;
nfa_forward_buckets_PLB_MSSize : in std_logic_vector(0 to 1);
nfa_forward_buckets_PLB_MRearbitrate : in std_logic;
nfa_forward_buckets_PLB_MTimeout : in std_logic;
nfa_forward_buckets_PLB_MBusy : in std_logic;
nfa_forward_buckets_PLB_MRdErr : in std_logic;
nfa_forward_buckets_PLB_MWrErr : in std_logic;
nfa_forward_buckets_PLB_MIRQ : in std_logic;
nfa_forward_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63);
nfa_forward_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3);
nfa_forward_buckets_PLB_MRdDAck : in std_logic;
nfa_forward_buckets_PLB_MRdBTerm : in std_logic;
nfa_forward_buckets_PLB_MWrDAck : in std_logic;
nfa_forward_buckets_PLB_MWrBTerm : in std_logic;
nfa_initials_buckets_MPLB_Clk : in std_logic;
nfa_initials_buckets_MPLB_Rst : in std_logic;
nfa_initials_buckets_M_request : out std_logic;
nfa_initials_buckets_M_priority : out std_logic_vector(0 to 1);
nfa_initials_buckets_M_busLock : out std_logic;
nfa_initials_buckets_M_RNW : out std_logic;
nfa_initials_buckets_M_BE : out std_logic_vector(0 to 7);
nfa_initials_buckets_M_MSize : out std_logic_vector(0 to 1);
nfa_initials_buckets_M_size : out std_logic_vector(0 to 3);
nfa_initials_buckets_M_type : out std_logic_vector(0 to 2);
nfa_initials_buckets_M_TAttribute : out std_logic_vector(0 to 15);
nfa_initials_buckets_M_lockErr : out std_logic;
nfa_initials_buckets_M_abort : out std_logic;
nfa_initials_buckets_M_UABus : out std_logic_vector(0 to 31);
nfa_initials_buckets_M_ABus : out std_logic_vector(0 to 31);
nfa_initials_buckets_M_wrDBus : out std_logic_vector(0 to 63);
nfa_initials_buckets_M_wrBurst : out std_logic;
nfa_initials_buckets_M_rdBurst : out std_logic;
nfa_initials_buckets_PLB_MAddrAck : in std_logic;
nfa_initials_buckets_PLB_MSSize : in std_logic_vector(0 to 1);
nfa_initials_buckets_PLB_MRearbitrate : in std_logic;
nfa_initials_buckets_PLB_MTimeout : in std_logic;
nfa_initials_buckets_PLB_MBusy : in std_logic;
nfa_initials_buckets_PLB_MRdErr : in std_logic;
nfa_initials_buckets_PLB_MWrErr : in std_logic;
nfa_initials_buckets_PLB_MIRQ : in std_logic;
nfa_initials_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63);
nfa_initials_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3);
nfa_initials_buckets_PLB_MRdDAck : in std_logic;
nfa_initials_buckets_PLB_MRdBTerm : in std_logic;
nfa_initials_buckets_PLB_MWrDAck : in std_logic;
nfa_initials_buckets_PLB_MWrBTerm : in std_logic;
sample_buffer_MPLB_Clk : in std_logic;
sample_buffer_MPLB_Rst : in std_logic;
sample_buffer_M_request : out std_logic;
sample_buffer_M_priority : out std_logic_vector(0 to 1);
sample_buffer_M_busLock : out std_logic;
sample_buffer_M_RNW : out std_logic;
sample_buffer_M_BE : out std_logic_vector(0 to 7);
sample_buffer_M_MSize : out std_logic_vector(0 to 1);
sample_buffer_M_size : out std_logic_vector(0 to 3);
sample_buffer_M_type : out std_logic_vector(0 to 2);
sample_buffer_M_TAttribute : out std_logic_vector(0 to 15);
sample_buffer_M_lockErr : out std_logic;
sample_buffer_M_abort : out std_logic;
sample_buffer_M_UABus : out std_logic_vector(0 to 31);
sample_buffer_M_ABus : out std_logic_vector(0 to 31);
sample_buffer_M_wrDBus : out std_logic_vector(0 to 63);
sample_buffer_M_wrBurst : out std_logic;
sample_buffer_M_rdBurst : out std_logic;
sample_buffer_PLB_MAddrAck : in std_logic;
sample_buffer_PLB_MSSize : in std_logic_vector(0 to 1);
sample_buffer_PLB_MRearbitrate : in std_logic;
sample_buffer_PLB_MTimeout : in std_logic;
sample_buffer_PLB_MBusy : in std_logic;
sample_buffer_PLB_MRdErr : in std_logic;
sample_buffer_PLB_MWrErr : in std_logic;
sample_buffer_PLB_MIRQ : in std_logic;
sample_buffer_PLB_MRdDBus : in std_logic_vector(0 to 63);
sample_buffer_PLB_MRdWdAddr : in std_logic_vector(0 to 3);
sample_buffer_PLB_MRdDAck : in std_logic;
sample_buffer_PLB_MRdBTerm : in std_logic;
sample_buffer_PLB_MWrDAck : in std_logic;
sample_buffer_PLB_MWrBTerm : in std_logic;
splb_slv0_SPLB_Clk : in std_logic;
splb_slv0_SPLB_Rst : in std_logic;
splb_slv0_PLB_ABus : in std_logic_vector(0 to 31);
splb_slv0_PLB_UABus : in std_logic_vector(0 to 31);
splb_slv0_PLB_PAValid : in std_logic;
splb_slv0_PLB_SAValid : in std_logic;
splb_slv0_PLB_rdPrim : in std_logic;
splb_slv0_PLB_wrPrim : in std_logic;
splb_slv0_PLB_masterID : in std_logic_vector(0 to 2);
splb_slv0_PLB_abort : in std_logic;
splb_slv0_PLB_busLock : in std_logic;
splb_slv0_PLB_RNW : in std_logic;
splb_slv0_PLB_BE : in std_logic_vector(0 to 7);
splb_slv0_PLB_MSize : in std_logic_vector(0 to 1);
splb_slv0_PLB_size : in std_logic_vector(0 to 3);
splb_slv0_PLB_type : in std_logic_vector(0 to 2);
splb_slv0_PLB_lockErr : in std_logic;
splb_slv0_PLB_wrDBus : in std_logic_vector(0 to 63);
splb_slv0_PLB_wrBurst : in std_logic;
splb_slv0_PLB_rdBurst : in std_logic;
splb_slv0_PLB_wrPendReq : in std_logic;
splb_slv0_PLB_rdPendReq : in std_logic;
splb_slv0_PLB_wrPendPri : in std_logic_vector(0 to 1);
splb_slv0_PLB_rdPendPri : in std_logic_vector(0 to 1);
splb_slv0_PLB_reqPri : in std_logic_vector(0 to 1);
splb_slv0_PLB_TAttribute : in std_logic_vector(0 to 15);
splb_slv0_Sl_addrAck : out std_logic;
splb_slv0_Sl_SSize : out std_logic_vector(0 to 1);
splb_slv0_Sl_wait : out std_logic;
splb_slv0_Sl_rearbitrate : out std_logic;
splb_slv0_Sl_wrDAck : out std_logic;
splb_slv0_Sl_wrComp : out std_logic;
splb_slv0_Sl_wrBTerm : out std_logic;
splb_slv0_Sl_rdDBus : out std_logic_vector(0 to 63);
splb_slv0_Sl_rdWdAddr : out std_logic_vector(0 to 3);
splb_slv0_Sl_rdDAck : out std_logic;
splb_slv0_Sl_rdComp : out std_logic;
splb_slv0_Sl_rdBTerm : out std_logic;
splb_slv0_Sl_MBusy : out std_logic_vector(0 to 5);
splb_slv0_Sl_MWrErr : out std_logic_vector(0 to 5);
splb_slv0_Sl_MRdErr : out std_logic_vector(0 to 5);
splb_slv0_Sl_MIRQ : out std_logic_vector(0 to 5)
);
end component;
component system_nfa_accept_samples_generic_hw_top_1_wrapper is
port (
aclk : in std_logic;
aresetn : in std_logic;
indices_MPLB_Clk : in std_logic;
indices_MPLB_Rst : in std_logic;
indices_M_request : out std_logic;
indices_M_priority : out std_logic_vector(0 to 1);
indices_M_busLock : out std_logic;
indices_M_RNW : out std_logic;
indices_M_BE : out std_logic_vector(0 to 7);
indices_M_MSize : out std_logic_vector(0 to 1);
indices_M_size : out std_logic_vector(0 to 3);
indices_M_type : out std_logic_vector(0 to 2);
indices_M_TAttribute : out std_logic_vector(0 to 15);
indices_M_lockErr : out std_logic;
indices_M_abort : out std_logic;
indices_M_UABus : out std_logic_vector(0 to 31);
indices_M_ABus : out std_logic_vector(0 to 31);
indices_M_wrDBus : out std_logic_vector(0 to 63);
indices_M_wrBurst : out std_logic;
indices_M_rdBurst : out std_logic;
indices_PLB_MAddrAck : in std_logic;
indices_PLB_MSSize : in std_logic_vector(0 to 1);
indices_PLB_MRearbitrate : in std_logic;
indices_PLB_MTimeout : in std_logic;
indices_PLB_MBusy : in std_logic;
indices_PLB_MRdErr : in std_logic;
indices_PLB_MWrErr : in std_logic;
indices_PLB_MIRQ : in std_logic;
indices_PLB_MRdDBus : in std_logic_vector(0 to 63);
indices_PLB_MRdWdAddr : in std_logic_vector(0 to 3);
indices_PLB_MRdDAck : in std_logic;
indices_PLB_MRdBTerm : in std_logic;
indices_PLB_MWrDAck : in std_logic;
indices_PLB_MWrBTerm : in std_logic;
nfa_finals_buckets_MPLB_Clk : in std_logic;
nfa_finals_buckets_MPLB_Rst : in std_logic;
nfa_finals_buckets_M_request : out std_logic;
nfa_finals_buckets_M_priority : out std_logic_vector(0 to 1);
nfa_finals_buckets_M_busLock : out std_logic;
nfa_finals_buckets_M_RNW : out std_logic;
nfa_finals_buckets_M_BE : out std_logic_vector(0 to 7);
nfa_finals_buckets_M_MSize : out std_logic_vector(0 to 1);
nfa_finals_buckets_M_size : out std_logic_vector(0 to 3);
nfa_finals_buckets_M_type : out std_logic_vector(0 to 2);
nfa_finals_buckets_M_TAttribute : out std_logic_vector(0 to 15);
nfa_finals_buckets_M_lockErr : out std_logic;
nfa_finals_buckets_M_abort : out std_logic;
nfa_finals_buckets_M_UABus : out std_logic_vector(0 to 31);
nfa_finals_buckets_M_ABus : out std_logic_vector(0 to 31);
nfa_finals_buckets_M_wrDBus : out std_logic_vector(0 to 63);
nfa_finals_buckets_M_wrBurst : out std_logic;
nfa_finals_buckets_M_rdBurst : out std_logic;
nfa_finals_buckets_PLB_MAddrAck : in std_logic;
nfa_finals_buckets_PLB_MSSize : in std_logic_vector(0 to 1);
nfa_finals_buckets_PLB_MRearbitrate : in std_logic;
nfa_finals_buckets_PLB_MTimeout : in std_logic;
nfa_finals_buckets_PLB_MBusy : in std_logic;
nfa_finals_buckets_PLB_MRdErr : in std_logic;
nfa_finals_buckets_PLB_MWrErr : in std_logic;
nfa_finals_buckets_PLB_MIRQ : in std_logic;
nfa_finals_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63);
nfa_finals_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3);
nfa_finals_buckets_PLB_MRdDAck : in std_logic;
nfa_finals_buckets_PLB_MRdBTerm : in std_logic;
nfa_finals_buckets_PLB_MWrDAck : in std_logic;
nfa_finals_buckets_PLB_MWrBTerm : in std_logic;
nfa_forward_buckets_MPLB_Clk : in std_logic;
nfa_forward_buckets_MPLB_Rst : in std_logic;
nfa_forward_buckets_M_request : out std_logic;
nfa_forward_buckets_M_priority : out std_logic_vector(0 to 1);
nfa_forward_buckets_M_busLock : out std_logic;
nfa_forward_buckets_M_RNW : out std_logic;
nfa_forward_buckets_M_BE : out std_logic_vector(0 to 7);
nfa_forward_buckets_M_MSize : out std_logic_vector(0 to 1);
nfa_forward_buckets_M_size : out std_logic_vector(0 to 3);
nfa_forward_buckets_M_type : out std_logic_vector(0 to 2);
nfa_forward_buckets_M_TAttribute : out std_logic_vector(0 to 15);
nfa_forward_buckets_M_lockErr : out std_logic;
nfa_forward_buckets_M_abort : out std_logic;
nfa_forward_buckets_M_UABus : out std_logic_vector(0 to 31);
nfa_forward_buckets_M_ABus : out std_logic_vector(0 to 31);
nfa_forward_buckets_M_wrDBus : out std_logic_vector(0 to 63);
nfa_forward_buckets_M_wrBurst : out std_logic;
nfa_forward_buckets_M_rdBurst : out std_logic;
nfa_forward_buckets_PLB_MAddrAck : in std_logic;
nfa_forward_buckets_PLB_MSSize : in std_logic_vector(0 to 1);
nfa_forward_buckets_PLB_MRearbitrate : in std_logic;
nfa_forward_buckets_PLB_MTimeout : in std_logic;
nfa_forward_buckets_PLB_MBusy : in std_logic;
nfa_forward_buckets_PLB_MRdErr : in std_logic;
nfa_forward_buckets_PLB_MWrErr : in std_logic;
nfa_forward_buckets_PLB_MIRQ : in std_logic;
nfa_forward_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63);
nfa_forward_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3);
nfa_forward_buckets_PLB_MRdDAck : in std_logic;
nfa_forward_buckets_PLB_MRdBTerm : in std_logic;
nfa_forward_buckets_PLB_MWrDAck : in std_logic;
nfa_forward_buckets_PLB_MWrBTerm : in std_logic;
nfa_initials_buckets_MPLB_Clk : in std_logic;
nfa_initials_buckets_MPLB_Rst : in std_logic;
nfa_initials_buckets_M_request : out std_logic;
nfa_initials_buckets_M_priority : out std_logic_vector(0 to 1);
nfa_initials_buckets_M_busLock : out std_logic;
nfa_initials_buckets_M_RNW : out std_logic;
nfa_initials_buckets_M_BE : out std_logic_vector(0 to 7);
nfa_initials_buckets_M_MSize : out std_logic_vector(0 to 1);
nfa_initials_buckets_M_size : out std_logic_vector(0 to 3);
nfa_initials_buckets_M_type : out std_logic_vector(0 to 2);
nfa_initials_buckets_M_TAttribute : out std_logic_vector(0 to 15);
nfa_initials_buckets_M_lockErr : out std_logic;
nfa_initials_buckets_M_abort : out std_logic;
nfa_initials_buckets_M_UABus : out std_logic_vector(0 to 31);
nfa_initials_buckets_M_ABus : out std_logic_vector(0 to 31);
nfa_initials_buckets_M_wrDBus : out std_logic_vector(0 to 63);
nfa_initials_buckets_M_wrBurst : out std_logic;
nfa_initials_buckets_M_rdBurst : out std_logic;
nfa_initials_buckets_PLB_MAddrAck : in std_logic;
nfa_initials_buckets_PLB_MSSize : in std_logic_vector(0 to 1);
nfa_initials_buckets_PLB_MRearbitrate : in std_logic;
nfa_initials_buckets_PLB_MTimeout : in std_logic;
nfa_initials_buckets_PLB_MBusy : in std_logic;
nfa_initials_buckets_PLB_MRdErr : in std_logic;
nfa_initials_buckets_PLB_MWrErr : in std_logic;
nfa_initials_buckets_PLB_MIRQ : in std_logic;
nfa_initials_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63);
nfa_initials_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3);
nfa_initials_buckets_PLB_MRdDAck : in std_logic;
nfa_initials_buckets_PLB_MRdBTerm : in std_logic;
nfa_initials_buckets_PLB_MWrDAck : in std_logic;
nfa_initials_buckets_PLB_MWrBTerm : in std_logic;
sample_buffer_MPLB_Clk : in std_logic;
sample_buffer_MPLB_Rst : in std_logic;
sample_buffer_M_request : out std_logic;
sample_buffer_M_priority : out std_logic_vector(0 to 1);
sample_buffer_M_busLock : out std_logic;
sample_buffer_M_RNW : out std_logic;
sample_buffer_M_BE : out std_logic_vector(0 to 7);
sample_buffer_M_MSize : out std_logic_vector(0 to 1);
sample_buffer_M_size : out std_logic_vector(0 to 3);
sample_buffer_M_type : out std_logic_vector(0 to 2);
sample_buffer_M_TAttribute : out std_logic_vector(0 to 15);
sample_buffer_M_lockErr : out std_logic;
sample_buffer_M_abort : out std_logic;
sample_buffer_M_UABus : out std_logic_vector(0 to 31);
sample_buffer_M_ABus : out std_logic_vector(0 to 31);
sample_buffer_M_wrDBus : out std_logic_vector(0 to 63);
sample_buffer_M_wrBurst : out std_logic;
sample_buffer_M_rdBurst : out std_logic;
sample_buffer_PLB_MAddrAck : in std_logic;
sample_buffer_PLB_MSSize : in std_logic_vector(0 to 1);
sample_buffer_PLB_MRearbitrate : in std_logic;
sample_buffer_PLB_MTimeout : in std_logic;
sample_buffer_PLB_MBusy : in std_logic;
sample_buffer_PLB_MRdErr : in std_logic;
sample_buffer_PLB_MWrErr : in std_logic;
sample_buffer_PLB_MIRQ : in std_logic;
sample_buffer_PLB_MRdDBus : in std_logic_vector(0 to 63);
sample_buffer_PLB_MRdWdAddr : in std_logic_vector(0 to 3);
sample_buffer_PLB_MRdDAck : in std_logic;
sample_buffer_PLB_MRdBTerm : in std_logic;
sample_buffer_PLB_MWrDAck : in std_logic;
sample_buffer_PLB_MWrBTerm : in std_logic;
splb_slv0_SPLB_Clk : in std_logic;
splb_slv0_SPLB_Rst : in std_logic;
splb_slv0_PLB_ABus : in std_logic_vector(0 to 31);
splb_slv0_PLB_UABus : in std_logic_vector(0 to 31);
splb_slv0_PLB_PAValid : in std_logic;
splb_slv0_PLB_SAValid : in std_logic;
splb_slv0_PLB_rdPrim : in std_logic;
splb_slv0_PLB_wrPrim : in std_logic;
splb_slv0_PLB_masterID : in std_logic_vector(0 to 2);
splb_slv0_PLB_abort : in std_logic;
splb_slv0_PLB_busLock : in std_logic;
splb_slv0_PLB_RNW : in std_logic;
splb_slv0_PLB_BE : in std_logic_vector(0 to 7);
splb_slv0_PLB_MSize : in std_logic_vector(0 to 1);
splb_slv0_PLB_size : in std_logic_vector(0 to 3);
splb_slv0_PLB_type : in std_logic_vector(0 to 2);
splb_slv0_PLB_lockErr : in std_logic;
splb_slv0_PLB_wrDBus : in std_logic_vector(0 to 63);
splb_slv0_PLB_wrBurst : in std_logic;
splb_slv0_PLB_rdBurst : in std_logic;
splb_slv0_PLB_wrPendReq : in std_logic;
splb_slv0_PLB_rdPendReq : in std_logic;
splb_slv0_PLB_wrPendPri : in std_logic_vector(0 to 1);
splb_slv0_PLB_rdPendPri : in std_logic_vector(0 to 1);
splb_slv0_PLB_reqPri : in std_logic_vector(0 to 1);
splb_slv0_PLB_TAttribute : in std_logic_vector(0 to 15);
splb_slv0_Sl_addrAck : out std_logic;
splb_slv0_Sl_SSize : out std_logic_vector(0 to 1);
splb_slv0_Sl_wait : out std_logic;
splb_slv0_Sl_rearbitrate : out std_logic;
splb_slv0_Sl_wrDAck : out std_logic;
splb_slv0_Sl_wrComp : out std_logic;
splb_slv0_Sl_wrBTerm : out std_logic;
splb_slv0_Sl_rdDBus : out std_logic_vector(0 to 63);
splb_slv0_Sl_rdWdAddr : out std_logic_vector(0 to 3);
splb_slv0_Sl_rdDAck : out std_logic;
splb_slv0_Sl_rdComp : out std_logic;
splb_slv0_Sl_rdBTerm : out std_logic;
splb_slv0_Sl_MBusy : out std_logic_vector(0 to 5);
splb_slv0_Sl_MWrErr : out std_logic_vector(0 to 5);
splb_slv0_Sl_MRdErr : out std_logic_vector(0 to 5);
splb_slv0_Sl_MIRQ : out std_logic_vector(0 to 5)
);
end component;
component system_nfa_accept_samples_generic_hw_top_2_wrapper is
port (
aclk : in std_logic;
aresetn : in std_logic;
indices_MPLB_Clk : in std_logic;
indices_MPLB_Rst : in std_logic;
indices_M_request : out std_logic;
indices_M_priority : out std_logic_vector(0 to 1);
indices_M_busLock : out std_logic;
indices_M_RNW : out std_logic;
indices_M_BE : out std_logic_vector(0 to 7);
indices_M_MSize : out std_logic_vector(0 to 1);
indices_M_size : out std_logic_vector(0 to 3);
indices_M_type : out std_logic_vector(0 to 2);
indices_M_TAttribute : out std_logic_vector(0 to 15);
indices_M_lockErr : out std_logic;
indices_M_abort : out std_logic;
indices_M_UABus : out std_logic_vector(0 to 31);
indices_M_ABus : out std_logic_vector(0 to 31);
indices_M_wrDBus : out std_logic_vector(0 to 63);
indices_M_wrBurst : out std_logic;
indices_M_rdBurst : out std_logic;
indices_PLB_MAddrAck : in std_logic;
indices_PLB_MSSize : in std_logic_vector(0 to 1);
indices_PLB_MRearbitrate : in std_logic;
indices_PLB_MTimeout : in std_logic;
indices_PLB_MBusy : in std_logic;
indices_PLB_MRdErr : in std_logic;
indices_PLB_MWrErr : in std_logic;
indices_PLB_MIRQ : in std_logic;
indices_PLB_MRdDBus : in std_logic_vector(0 to 63);
indices_PLB_MRdWdAddr : in std_logic_vector(0 to 3);
indices_PLB_MRdDAck : in std_logic;
indices_PLB_MRdBTerm : in std_logic;
indices_PLB_MWrDAck : in std_logic;
indices_PLB_MWrBTerm : in std_logic;
nfa_finals_buckets_MPLB_Clk : in std_logic;
nfa_finals_buckets_MPLB_Rst : in std_logic;
nfa_finals_buckets_M_request : out std_logic;
nfa_finals_buckets_M_priority : out std_logic_vector(0 to 1);
nfa_finals_buckets_M_busLock : out std_logic;
nfa_finals_buckets_M_RNW : out std_logic;
nfa_finals_buckets_M_BE : out std_logic_vector(0 to 7);
nfa_finals_buckets_M_MSize : out std_logic_vector(0 to 1);
nfa_finals_buckets_M_size : out std_logic_vector(0 to 3);
nfa_finals_buckets_M_type : out std_logic_vector(0 to 2);
nfa_finals_buckets_M_TAttribute : out std_logic_vector(0 to 15);
nfa_finals_buckets_M_lockErr : out std_logic;
nfa_finals_buckets_M_abort : out std_logic;
nfa_finals_buckets_M_UABus : out std_logic_vector(0 to 31);
nfa_finals_buckets_M_ABus : out std_logic_vector(0 to 31);
nfa_finals_buckets_M_wrDBus : out std_logic_vector(0 to 63);
nfa_finals_buckets_M_wrBurst : out std_logic;
nfa_finals_buckets_M_rdBurst : out std_logic;
nfa_finals_buckets_PLB_MAddrAck : in std_logic;
nfa_finals_buckets_PLB_MSSize : in std_logic_vector(0 to 1);
nfa_finals_buckets_PLB_MRearbitrate : in std_logic;
nfa_finals_buckets_PLB_MTimeout : in std_logic;
nfa_finals_buckets_PLB_MBusy : in std_logic;
nfa_finals_buckets_PLB_MRdErr : in std_logic;
nfa_finals_buckets_PLB_MWrErr : in std_logic;
nfa_finals_buckets_PLB_MIRQ : in std_logic;
nfa_finals_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63);
nfa_finals_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3);
nfa_finals_buckets_PLB_MRdDAck : in std_logic;
nfa_finals_buckets_PLB_MRdBTerm : in std_logic;
nfa_finals_buckets_PLB_MWrDAck : in std_logic;
nfa_finals_buckets_PLB_MWrBTerm : in std_logic;
nfa_forward_buckets_MPLB_Clk : in std_logic;
nfa_forward_buckets_MPLB_Rst : in std_logic;
nfa_forward_buckets_M_request : out std_logic;
nfa_forward_buckets_M_priority : out std_logic_vector(0 to 1);
nfa_forward_buckets_M_busLock : out std_logic;
nfa_forward_buckets_M_RNW : out std_logic;
nfa_forward_buckets_M_BE : out std_logic_vector(0 to 7);
nfa_forward_buckets_M_MSize : out std_logic_vector(0 to 1);
nfa_forward_buckets_M_size : out std_logic_vector(0 to 3);
nfa_forward_buckets_M_type : out std_logic_vector(0 to 2);
nfa_forward_buckets_M_TAttribute : out std_logic_vector(0 to 15);
nfa_forward_buckets_M_lockErr : out std_logic;
nfa_forward_buckets_M_abort : out std_logic;
nfa_forward_buckets_M_UABus : out std_logic_vector(0 to 31);
nfa_forward_buckets_M_ABus : out std_logic_vector(0 to 31);
nfa_forward_buckets_M_wrDBus : out std_logic_vector(0 to 63);
nfa_forward_buckets_M_wrBurst : out std_logic;
nfa_forward_buckets_M_rdBurst : out std_logic;
nfa_forward_buckets_PLB_MAddrAck : in std_logic;
nfa_forward_buckets_PLB_MSSize : in std_logic_vector(0 to 1);
nfa_forward_buckets_PLB_MRearbitrate : in std_logic;
nfa_forward_buckets_PLB_MTimeout : in std_logic;
nfa_forward_buckets_PLB_MBusy : in std_logic;
nfa_forward_buckets_PLB_MRdErr : in std_logic;
nfa_forward_buckets_PLB_MWrErr : in std_logic;
nfa_forward_buckets_PLB_MIRQ : in std_logic;
nfa_forward_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63);
nfa_forward_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3);
nfa_forward_buckets_PLB_MRdDAck : in std_logic;
nfa_forward_buckets_PLB_MRdBTerm : in std_logic;
nfa_forward_buckets_PLB_MWrDAck : in std_logic;
nfa_forward_buckets_PLB_MWrBTerm : in std_logic;
nfa_initials_buckets_MPLB_Clk : in std_logic;
nfa_initials_buckets_MPLB_Rst : in std_logic;
nfa_initials_buckets_M_request : out std_logic;
nfa_initials_buckets_M_priority : out std_logic_vector(0 to 1);
nfa_initials_buckets_M_busLock : out std_logic;
nfa_initials_buckets_M_RNW : out std_logic;
nfa_initials_buckets_M_BE : out std_logic_vector(0 to 7);
nfa_initials_buckets_M_MSize : out std_logic_vector(0 to 1);
nfa_initials_buckets_M_size : out std_logic_vector(0 to 3);
nfa_initials_buckets_M_type : out std_logic_vector(0 to 2);
nfa_initials_buckets_M_TAttribute : out std_logic_vector(0 to 15);
nfa_initials_buckets_M_lockErr : out std_logic;
nfa_initials_buckets_M_abort : out std_logic;
nfa_initials_buckets_M_UABus : out std_logic_vector(0 to 31);
nfa_initials_buckets_M_ABus : out std_logic_vector(0 to 31);
nfa_initials_buckets_M_wrDBus : out std_logic_vector(0 to 63);
nfa_initials_buckets_M_wrBurst : out std_logic;
nfa_initials_buckets_M_rdBurst : out std_logic;
nfa_initials_buckets_PLB_MAddrAck : in std_logic;
nfa_initials_buckets_PLB_MSSize : in std_logic_vector(0 to 1);
nfa_initials_buckets_PLB_MRearbitrate : in std_logic;
nfa_initials_buckets_PLB_MTimeout : in std_logic;
nfa_initials_buckets_PLB_MBusy : in std_logic;
nfa_initials_buckets_PLB_MRdErr : in std_logic;
nfa_initials_buckets_PLB_MWrErr : in std_logic;
nfa_initials_buckets_PLB_MIRQ : in std_logic;
nfa_initials_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63);
nfa_initials_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3);
nfa_initials_buckets_PLB_MRdDAck : in std_logic;
nfa_initials_buckets_PLB_MRdBTerm : in std_logic;
nfa_initials_buckets_PLB_MWrDAck : in std_logic;
nfa_initials_buckets_PLB_MWrBTerm : in std_logic;
sample_buffer_MPLB_Clk : in std_logic;
sample_buffer_MPLB_Rst : in std_logic;
sample_buffer_M_request : out std_logic;
sample_buffer_M_priority : out std_logic_vector(0 to 1);
sample_buffer_M_busLock : out std_logic;
sample_buffer_M_RNW : out std_logic;
sample_buffer_M_BE : out std_logic_vector(0 to 7);
sample_buffer_M_MSize : out std_logic_vector(0 to 1);
sample_buffer_M_size : out std_logic_vector(0 to 3);
sample_buffer_M_type : out std_logic_vector(0 to 2);
sample_buffer_M_TAttribute : out std_logic_vector(0 to 15);
sample_buffer_M_lockErr : out std_logic;
sample_buffer_M_abort : out std_logic;
sample_buffer_M_UABus : out std_logic_vector(0 to 31);
sample_buffer_M_ABus : out std_logic_vector(0 to 31);
sample_buffer_M_wrDBus : out std_logic_vector(0 to 63);
sample_buffer_M_wrBurst : out std_logic;
sample_buffer_M_rdBurst : out std_logic;
sample_buffer_PLB_MAddrAck : in std_logic;
sample_buffer_PLB_MSSize : in std_logic_vector(0 to 1);
sample_buffer_PLB_MRearbitrate : in std_logic;
sample_buffer_PLB_MTimeout : in std_logic;
sample_buffer_PLB_MBusy : in std_logic;
sample_buffer_PLB_MRdErr : in std_logic;
sample_buffer_PLB_MWrErr : in std_logic;
sample_buffer_PLB_MIRQ : in std_logic;
sample_buffer_PLB_MRdDBus : in std_logic_vector(0 to 63);
sample_buffer_PLB_MRdWdAddr : in std_logic_vector(0 to 3);
sample_buffer_PLB_MRdDAck : in std_logic;
sample_buffer_PLB_MRdBTerm : in std_logic;
sample_buffer_PLB_MWrDAck : in std_logic;
sample_buffer_PLB_MWrBTerm : in std_logic;
splb_slv0_SPLB_Clk : in std_logic;
splb_slv0_SPLB_Rst : in std_logic;
splb_slv0_PLB_ABus : in std_logic_vector(0 to 31);
splb_slv0_PLB_UABus : in std_logic_vector(0 to 31);
splb_slv0_PLB_PAValid : in std_logic;
splb_slv0_PLB_SAValid : in std_logic;
splb_slv0_PLB_rdPrim : in std_logic;
splb_slv0_PLB_wrPrim : in std_logic;
splb_slv0_PLB_masterID : in std_logic_vector(0 to 2);
splb_slv0_PLB_abort : in std_logic;
splb_slv0_PLB_busLock : in std_logic;
splb_slv0_PLB_RNW : in std_logic;
splb_slv0_PLB_BE : in std_logic_vector(0 to 7);
splb_slv0_PLB_MSize : in std_logic_vector(0 to 1);
splb_slv0_PLB_size : in std_logic_vector(0 to 3);
splb_slv0_PLB_type : in std_logic_vector(0 to 2);
splb_slv0_PLB_lockErr : in std_logic;
splb_slv0_PLB_wrDBus : in std_logic_vector(0 to 63);
splb_slv0_PLB_wrBurst : in std_logic;
splb_slv0_PLB_rdBurst : in std_logic;
splb_slv0_PLB_wrPendReq : in std_logic;
splb_slv0_PLB_rdPendReq : in std_logic;
splb_slv0_PLB_wrPendPri : in std_logic_vector(0 to 1);
splb_slv0_PLB_rdPendPri : in std_logic_vector(0 to 1);
splb_slv0_PLB_reqPri : in std_logic_vector(0 to 1);
splb_slv0_PLB_TAttribute : in std_logic_vector(0 to 15);
splb_slv0_Sl_addrAck : out std_logic;
splb_slv0_Sl_SSize : out std_logic_vector(0 to 1);
splb_slv0_Sl_wait : out std_logic;
splb_slv0_Sl_rearbitrate : out std_logic;
splb_slv0_Sl_wrDAck : out std_logic;
splb_slv0_Sl_wrComp : out std_logic;
splb_slv0_Sl_wrBTerm : out std_logic;
splb_slv0_Sl_rdDBus : out std_logic_vector(0 to 63);
splb_slv0_Sl_rdWdAddr : out std_logic_vector(0 to 3);
splb_slv0_Sl_rdDAck : out std_logic;
splb_slv0_Sl_rdComp : out std_logic;
splb_slv0_Sl_rdBTerm : out std_logic;
splb_slv0_Sl_MBusy : out std_logic_vector(0 to 5);
splb_slv0_Sl_MWrErr : out std_logic_vector(0 to 5);
splb_slv0_Sl_MRdErr : out std_logic_vector(0 to 5);
splb_slv0_Sl_MIRQ : out std_logic_vector(0 to 5)
);
end component;
component system_nfa_accept_samples_generic_hw_top_3_wrapper is
port (
aclk : in std_logic;
aresetn : in std_logic;
indices_MPLB_Clk : in std_logic;
indices_MPLB_Rst : in std_logic;
indices_M_request : out std_logic;
indices_M_priority : out std_logic_vector(0 to 1);
indices_M_busLock : out std_logic;
indices_M_RNW : out std_logic;
indices_M_BE : out std_logic_vector(0 to 7);
indices_M_MSize : out std_logic_vector(0 to 1);
indices_M_size : out std_logic_vector(0 to 3);
indices_M_type : out std_logic_vector(0 to 2);
indices_M_TAttribute : out std_logic_vector(0 to 15);
indices_M_lockErr : out std_logic;
indices_M_abort : out std_logic;
indices_M_UABus : out std_logic_vector(0 to 31);
indices_M_ABus : out std_logic_vector(0 to 31);
indices_M_wrDBus : out std_logic_vector(0 to 63);
indices_M_wrBurst : out std_logic;
indices_M_rdBurst : out std_logic;
indices_PLB_MAddrAck : in std_logic;
indices_PLB_MSSize : in std_logic_vector(0 to 1);
indices_PLB_MRearbitrate : in std_logic;
indices_PLB_MTimeout : in std_logic;
indices_PLB_MBusy : in std_logic;
indices_PLB_MRdErr : in std_logic;
indices_PLB_MWrErr : in std_logic;
indices_PLB_MIRQ : in std_logic;
indices_PLB_MRdDBus : in std_logic_vector(0 to 63);
indices_PLB_MRdWdAddr : in std_logic_vector(0 to 3);
indices_PLB_MRdDAck : in std_logic;
indices_PLB_MRdBTerm : in std_logic;
indices_PLB_MWrDAck : in std_logic;
indices_PLB_MWrBTerm : in std_logic;
nfa_finals_buckets_MPLB_Clk : in std_logic;
nfa_finals_buckets_MPLB_Rst : in std_logic;
nfa_finals_buckets_M_request : out std_logic;
nfa_finals_buckets_M_priority : out std_logic_vector(0 to 1);
nfa_finals_buckets_M_busLock : out std_logic;
nfa_finals_buckets_M_RNW : out std_logic;
nfa_finals_buckets_M_BE : out std_logic_vector(0 to 7);
nfa_finals_buckets_M_MSize : out std_logic_vector(0 to 1);
nfa_finals_buckets_M_size : out std_logic_vector(0 to 3);
nfa_finals_buckets_M_type : out std_logic_vector(0 to 2);
nfa_finals_buckets_M_TAttribute : out std_logic_vector(0 to 15);
nfa_finals_buckets_M_lockErr : out std_logic;
nfa_finals_buckets_M_abort : out std_logic;
nfa_finals_buckets_M_UABus : out std_logic_vector(0 to 31);
nfa_finals_buckets_M_ABus : out std_logic_vector(0 to 31);
nfa_finals_buckets_M_wrDBus : out std_logic_vector(0 to 63);
nfa_finals_buckets_M_wrBurst : out std_logic;
nfa_finals_buckets_M_rdBurst : out std_logic;
nfa_finals_buckets_PLB_MAddrAck : in std_logic;
nfa_finals_buckets_PLB_MSSize : in std_logic_vector(0 to 1);
nfa_finals_buckets_PLB_MRearbitrate : in std_logic;
nfa_finals_buckets_PLB_MTimeout : in std_logic;
nfa_finals_buckets_PLB_MBusy : in std_logic;
nfa_finals_buckets_PLB_MRdErr : in std_logic;
nfa_finals_buckets_PLB_MWrErr : in std_logic;
nfa_finals_buckets_PLB_MIRQ : in std_logic;
nfa_finals_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63);
nfa_finals_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3);
nfa_finals_buckets_PLB_MRdDAck : in std_logic;
nfa_finals_buckets_PLB_MRdBTerm : in std_logic;
nfa_finals_buckets_PLB_MWrDAck : in std_logic;
nfa_finals_buckets_PLB_MWrBTerm : in std_logic;
nfa_forward_buckets_MPLB_Clk : in std_logic;
nfa_forward_buckets_MPLB_Rst : in std_logic;
nfa_forward_buckets_M_request : out std_logic;
nfa_forward_buckets_M_priority : out std_logic_vector(0 to 1);
nfa_forward_buckets_M_busLock : out std_logic;
nfa_forward_buckets_M_RNW : out std_logic;
nfa_forward_buckets_M_BE : out std_logic_vector(0 to 7);
nfa_forward_buckets_M_MSize : out std_logic_vector(0 to 1);
nfa_forward_buckets_M_size : out std_logic_vector(0 to 3);
nfa_forward_buckets_M_type : out std_logic_vector(0 to 2);
nfa_forward_buckets_M_TAttribute : out std_logic_vector(0 to 15);
nfa_forward_buckets_M_lockErr : out std_logic;
nfa_forward_buckets_M_abort : out std_logic;
nfa_forward_buckets_M_UABus : out std_logic_vector(0 to 31);
nfa_forward_buckets_M_ABus : out std_logic_vector(0 to 31);
nfa_forward_buckets_M_wrDBus : out std_logic_vector(0 to 63);
nfa_forward_buckets_M_wrBurst : out std_logic;
nfa_forward_buckets_M_rdBurst : out std_logic;
nfa_forward_buckets_PLB_MAddrAck : in std_logic;
nfa_forward_buckets_PLB_MSSize : in std_logic_vector(0 to 1);
nfa_forward_buckets_PLB_MRearbitrate : in std_logic;
nfa_forward_buckets_PLB_MTimeout : in std_logic;
nfa_forward_buckets_PLB_MBusy : in std_logic;
nfa_forward_buckets_PLB_MRdErr : in std_logic;
nfa_forward_buckets_PLB_MWrErr : in std_logic;
nfa_forward_buckets_PLB_MIRQ : in std_logic;
nfa_forward_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63);
nfa_forward_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3);
nfa_forward_buckets_PLB_MRdDAck : in std_logic;
nfa_forward_buckets_PLB_MRdBTerm : in std_logic;
nfa_forward_buckets_PLB_MWrDAck : in std_logic;
nfa_forward_buckets_PLB_MWrBTerm : in std_logic;
nfa_initials_buckets_MPLB_Clk : in std_logic;
nfa_initials_buckets_MPLB_Rst : in std_logic;
nfa_initials_buckets_M_request : out std_logic;
nfa_initials_buckets_M_priority : out std_logic_vector(0 to 1);
nfa_initials_buckets_M_busLock : out std_logic;
nfa_initials_buckets_M_RNW : out std_logic;
nfa_initials_buckets_M_BE : out std_logic_vector(0 to 7);
nfa_initials_buckets_M_MSize : out std_logic_vector(0 to 1);
nfa_initials_buckets_M_size : out std_logic_vector(0 to 3);
nfa_initials_buckets_M_type : out std_logic_vector(0 to 2);
nfa_initials_buckets_M_TAttribute : out std_logic_vector(0 to 15);
nfa_initials_buckets_M_lockErr : out std_logic;
nfa_initials_buckets_M_abort : out std_logic;
nfa_initials_buckets_M_UABus : out std_logic_vector(0 to 31);
nfa_initials_buckets_M_ABus : out std_logic_vector(0 to 31);
nfa_initials_buckets_M_wrDBus : out std_logic_vector(0 to 63);
nfa_initials_buckets_M_wrBurst : out std_logic;
nfa_initials_buckets_M_rdBurst : out std_logic;
nfa_initials_buckets_PLB_MAddrAck : in std_logic;
nfa_initials_buckets_PLB_MSSize : in std_logic_vector(0 to 1);
nfa_initials_buckets_PLB_MRearbitrate : in std_logic;
nfa_initials_buckets_PLB_MTimeout : in std_logic;
nfa_initials_buckets_PLB_MBusy : in std_logic;
nfa_initials_buckets_PLB_MRdErr : in std_logic;
nfa_initials_buckets_PLB_MWrErr : in std_logic;
nfa_initials_buckets_PLB_MIRQ : in std_logic;
nfa_initials_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63);
nfa_initials_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3);
nfa_initials_buckets_PLB_MRdDAck : in std_logic;
nfa_initials_buckets_PLB_MRdBTerm : in std_logic;
nfa_initials_buckets_PLB_MWrDAck : in std_logic;
nfa_initials_buckets_PLB_MWrBTerm : in std_logic;
sample_buffer_MPLB_Clk : in std_logic;
sample_buffer_MPLB_Rst : in std_logic;
sample_buffer_M_request : out std_logic;
sample_buffer_M_priority : out std_logic_vector(0 to 1);
sample_buffer_M_busLock : out std_logic;
sample_buffer_M_RNW : out std_logic;
sample_buffer_M_BE : out std_logic_vector(0 to 7);
sample_buffer_M_MSize : out std_logic_vector(0 to 1);
sample_buffer_M_size : out std_logic_vector(0 to 3);
sample_buffer_M_type : out std_logic_vector(0 to 2);
sample_buffer_M_TAttribute : out std_logic_vector(0 to 15);
sample_buffer_M_lockErr : out std_logic;
sample_buffer_M_abort : out std_logic;
sample_buffer_M_UABus : out std_logic_vector(0 to 31);
sample_buffer_M_ABus : out std_logic_vector(0 to 31);
sample_buffer_M_wrDBus : out std_logic_vector(0 to 63);
sample_buffer_M_wrBurst : out std_logic;
sample_buffer_M_rdBurst : out std_logic;
sample_buffer_PLB_MAddrAck : in std_logic;
sample_buffer_PLB_MSSize : in std_logic_vector(0 to 1);
sample_buffer_PLB_MRearbitrate : in std_logic;
sample_buffer_PLB_MTimeout : in std_logic;
sample_buffer_PLB_MBusy : in std_logic;
sample_buffer_PLB_MRdErr : in std_logic;
sample_buffer_PLB_MWrErr : in std_logic;
sample_buffer_PLB_MIRQ : in std_logic;
sample_buffer_PLB_MRdDBus : in std_logic_vector(0 to 63);
sample_buffer_PLB_MRdWdAddr : in std_logic_vector(0 to 3);
sample_buffer_PLB_MRdDAck : in std_logic;
sample_buffer_PLB_MRdBTerm : in std_logic;
sample_buffer_PLB_MWrDAck : in std_logic;
sample_buffer_PLB_MWrBTerm : in std_logic;
splb_slv0_SPLB_Clk : in std_logic;
splb_slv0_SPLB_Rst : in std_logic;
splb_slv0_PLB_ABus : in std_logic_vector(0 to 31);
splb_slv0_PLB_UABus : in std_logic_vector(0 to 31);
splb_slv0_PLB_PAValid : in std_logic;
splb_slv0_PLB_SAValid : in std_logic;
splb_slv0_PLB_rdPrim : in std_logic;
splb_slv0_PLB_wrPrim : in std_logic;
splb_slv0_PLB_masterID : in std_logic_vector(0 to 2);
splb_slv0_PLB_abort : in std_logic;
splb_slv0_PLB_busLock : in std_logic;
splb_slv0_PLB_RNW : in std_logic;
splb_slv0_PLB_BE : in std_logic_vector(0 to 7);
splb_slv0_PLB_MSize : in std_logic_vector(0 to 1);
splb_slv0_PLB_size : in std_logic_vector(0 to 3);
splb_slv0_PLB_type : in std_logic_vector(0 to 2);
splb_slv0_PLB_lockErr : in std_logic;
splb_slv0_PLB_wrDBus : in std_logic_vector(0 to 63);
splb_slv0_PLB_wrBurst : in std_logic;
splb_slv0_PLB_rdBurst : in std_logic;
splb_slv0_PLB_wrPendReq : in std_logic;
splb_slv0_PLB_rdPendReq : in std_logic;
splb_slv0_PLB_wrPendPri : in std_logic_vector(0 to 1);
splb_slv0_PLB_rdPendPri : in std_logic_vector(0 to 1);
splb_slv0_PLB_reqPri : in std_logic_vector(0 to 1);
splb_slv0_PLB_TAttribute : in std_logic_vector(0 to 15);
splb_slv0_Sl_addrAck : out std_logic;
splb_slv0_Sl_SSize : out std_logic_vector(0 to 1);
splb_slv0_Sl_wait : out std_logic;
splb_slv0_Sl_rearbitrate : out std_logic;
splb_slv0_Sl_wrDAck : out std_logic;
splb_slv0_Sl_wrComp : out std_logic;
splb_slv0_Sl_wrBTerm : out std_logic;
splb_slv0_Sl_rdDBus : out std_logic_vector(0 to 63);
splb_slv0_Sl_rdWdAddr : out std_logic_vector(0 to 3);
splb_slv0_Sl_rdDAck : out std_logic;
splb_slv0_Sl_rdComp : out std_logic;
splb_slv0_Sl_rdBTerm : out std_logic;
splb_slv0_Sl_MBusy : out std_logic_vector(0 to 5);
splb_slv0_Sl_MWrErr : out std_logic_vector(0 to 5);
splb_slv0_Sl_MRdErr : out std_logic_vector(0 to 5);
splb_slv0_Sl_MIRQ : out std_logic_vector(0 to 5)
);
end component;
component system_nfa_accept_samples_generic_hw_top_4_wrapper is
port (
aclk : in std_logic;
aresetn : in std_logic;
indices_MPLB_Clk : in std_logic;
indices_MPLB_Rst : in std_logic;
indices_M_request : out std_logic;
indices_M_priority : out std_logic_vector(0 to 1);
indices_M_busLock : out std_logic;
indices_M_RNW : out std_logic;
indices_M_BE : out std_logic_vector(0 to 7);
indices_M_MSize : out std_logic_vector(0 to 1);
indices_M_size : out std_logic_vector(0 to 3);
indices_M_type : out std_logic_vector(0 to 2);
indices_M_TAttribute : out std_logic_vector(0 to 15);
indices_M_lockErr : out std_logic;
indices_M_abort : out std_logic;
indices_M_UABus : out std_logic_vector(0 to 31);
indices_M_ABus : out std_logic_vector(0 to 31);
indices_M_wrDBus : out std_logic_vector(0 to 63);
indices_M_wrBurst : out std_logic;
indices_M_rdBurst : out std_logic;
indices_PLB_MAddrAck : in std_logic;
indices_PLB_MSSize : in std_logic_vector(0 to 1);
indices_PLB_MRearbitrate : in std_logic;
indices_PLB_MTimeout : in std_logic;
indices_PLB_MBusy : in std_logic;
indices_PLB_MRdErr : in std_logic;
indices_PLB_MWrErr : in std_logic;
indices_PLB_MIRQ : in std_logic;
indices_PLB_MRdDBus : in std_logic_vector(0 to 63);
indices_PLB_MRdWdAddr : in std_logic_vector(0 to 3);
indices_PLB_MRdDAck : in std_logic;
indices_PLB_MRdBTerm : in std_logic;
indices_PLB_MWrDAck : in std_logic;
indices_PLB_MWrBTerm : in std_logic;
nfa_finals_buckets_MPLB_Clk : in std_logic;
nfa_finals_buckets_MPLB_Rst : in std_logic;
nfa_finals_buckets_M_request : out std_logic;
nfa_finals_buckets_M_priority : out std_logic_vector(0 to 1);
nfa_finals_buckets_M_busLock : out std_logic;
nfa_finals_buckets_M_RNW : out std_logic;
nfa_finals_buckets_M_BE : out std_logic_vector(0 to 7);
nfa_finals_buckets_M_MSize : out std_logic_vector(0 to 1);
nfa_finals_buckets_M_size : out std_logic_vector(0 to 3);
nfa_finals_buckets_M_type : out std_logic_vector(0 to 2);
nfa_finals_buckets_M_TAttribute : out std_logic_vector(0 to 15);
nfa_finals_buckets_M_lockErr : out std_logic;
nfa_finals_buckets_M_abort : out std_logic;
nfa_finals_buckets_M_UABus : out std_logic_vector(0 to 31);
nfa_finals_buckets_M_ABus : out std_logic_vector(0 to 31);
nfa_finals_buckets_M_wrDBus : out std_logic_vector(0 to 63);
nfa_finals_buckets_M_wrBurst : out std_logic;
nfa_finals_buckets_M_rdBurst : out std_logic;
nfa_finals_buckets_PLB_MAddrAck : in std_logic;
nfa_finals_buckets_PLB_MSSize : in std_logic_vector(0 to 1);
nfa_finals_buckets_PLB_MRearbitrate : in std_logic;
nfa_finals_buckets_PLB_MTimeout : in std_logic;
nfa_finals_buckets_PLB_MBusy : in std_logic;
nfa_finals_buckets_PLB_MRdErr : in std_logic;
nfa_finals_buckets_PLB_MWrErr : in std_logic;
nfa_finals_buckets_PLB_MIRQ : in std_logic;
nfa_finals_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63);
nfa_finals_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3);
nfa_finals_buckets_PLB_MRdDAck : in std_logic;
nfa_finals_buckets_PLB_MRdBTerm : in std_logic;
nfa_finals_buckets_PLB_MWrDAck : in std_logic;
nfa_finals_buckets_PLB_MWrBTerm : in std_logic;
nfa_forward_buckets_MPLB_Clk : in std_logic;
nfa_forward_buckets_MPLB_Rst : in std_logic;
nfa_forward_buckets_M_request : out std_logic;
nfa_forward_buckets_M_priority : out std_logic_vector(0 to 1);
nfa_forward_buckets_M_busLock : out std_logic;
nfa_forward_buckets_M_RNW : out std_logic;
nfa_forward_buckets_M_BE : out std_logic_vector(0 to 7);
nfa_forward_buckets_M_MSize : out std_logic_vector(0 to 1);
nfa_forward_buckets_M_size : out std_logic_vector(0 to 3);
nfa_forward_buckets_M_type : out std_logic_vector(0 to 2);
nfa_forward_buckets_M_TAttribute : out std_logic_vector(0 to 15);
nfa_forward_buckets_M_lockErr : out std_logic;
nfa_forward_buckets_M_abort : out std_logic;
nfa_forward_buckets_M_UABus : out std_logic_vector(0 to 31);
nfa_forward_buckets_M_ABus : out std_logic_vector(0 to 31);
nfa_forward_buckets_M_wrDBus : out std_logic_vector(0 to 63);
nfa_forward_buckets_M_wrBurst : out std_logic;
nfa_forward_buckets_M_rdBurst : out std_logic;
nfa_forward_buckets_PLB_MAddrAck : in std_logic;
nfa_forward_buckets_PLB_MSSize : in std_logic_vector(0 to 1);
nfa_forward_buckets_PLB_MRearbitrate : in std_logic;
nfa_forward_buckets_PLB_MTimeout : in std_logic;
nfa_forward_buckets_PLB_MBusy : in std_logic;
nfa_forward_buckets_PLB_MRdErr : in std_logic;
nfa_forward_buckets_PLB_MWrErr : in std_logic;
nfa_forward_buckets_PLB_MIRQ : in std_logic;
nfa_forward_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63);
nfa_forward_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3);
nfa_forward_buckets_PLB_MRdDAck : in std_logic;
nfa_forward_buckets_PLB_MRdBTerm : in std_logic;
nfa_forward_buckets_PLB_MWrDAck : in std_logic;
nfa_forward_buckets_PLB_MWrBTerm : in std_logic;
nfa_initials_buckets_MPLB_Clk : in std_logic;
nfa_initials_buckets_MPLB_Rst : in std_logic;
nfa_initials_buckets_M_request : out std_logic;
nfa_initials_buckets_M_priority : out std_logic_vector(0 to 1);
nfa_initials_buckets_M_busLock : out std_logic;
nfa_initials_buckets_M_RNW : out std_logic;
nfa_initials_buckets_M_BE : out std_logic_vector(0 to 7);
nfa_initials_buckets_M_MSize : out std_logic_vector(0 to 1);
nfa_initials_buckets_M_size : out std_logic_vector(0 to 3);
nfa_initials_buckets_M_type : out std_logic_vector(0 to 2);
nfa_initials_buckets_M_TAttribute : out std_logic_vector(0 to 15);
nfa_initials_buckets_M_lockErr : out std_logic;
nfa_initials_buckets_M_abort : out std_logic;
nfa_initials_buckets_M_UABus : out std_logic_vector(0 to 31);
nfa_initials_buckets_M_ABus : out std_logic_vector(0 to 31);
nfa_initials_buckets_M_wrDBus : out std_logic_vector(0 to 63);
nfa_initials_buckets_M_wrBurst : out std_logic;
nfa_initials_buckets_M_rdBurst : out std_logic;
nfa_initials_buckets_PLB_MAddrAck : in std_logic;
nfa_initials_buckets_PLB_MSSize : in std_logic_vector(0 to 1);
nfa_initials_buckets_PLB_MRearbitrate : in std_logic;
nfa_initials_buckets_PLB_MTimeout : in std_logic;
nfa_initials_buckets_PLB_MBusy : in std_logic;
nfa_initials_buckets_PLB_MRdErr : in std_logic;
nfa_initials_buckets_PLB_MWrErr : in std_logic;
nfa_initials_buckets_PLB_MIRQ : in std_logic;
nfa_initials_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63);
nfa_initials_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3);
nfa_initials_buckets_PLB_MRdDAck : in std_logic;
nfa_initials_buckets_PLB_MRdBTerm : in std_logic;
nfa_initials_buckets_PLB_MWrDAck : in std_logic;
nfa_initials_buckets_PLB_MWrBTerm : in std_logic;
sample_buffer_MPLB_Clk : in std_logic;
sample_buffer_MPLB_Rst : in std_logic;
sample_buffer_M_request : out std_logic;
sample_buffer_M_priority : out std_logic_vector(0 to 1);
sample_buffer_M_busLock : out std_logic;
sample_buffer_M_RNW : out std_logic;
sample_buffer_M_BE : out std_logic_vector(0 to 7);
sample_buffer_M_MSize : out std_logic_vector(0 to 1);
sample_buffer_M_size : out std_logic_vector(0 to 3);
sample_buffer_M_type : out std_logic_vector(0 to 2);
sample_buffer_M_TAttribute : out std_logic_vector(0 to 15);
sample_buffer_M_lockErr : out std_logic;
sample_buffer_M_abort : out std_logic;
sample_buffer_M_UABus : out std_logic_vector(0 to 31);
sample_buffer_M_ABus : out std_logic_vector(0 to 31);
sample_buffer_M_wrDBus : out std_logic_vector(0 to 63);
sample_buffer_M_wrBurst : out std_logic;
sample_buffer_M_rdBurst : out std_logic;
sample_buffer_PLB_MAddrAck : in std_logic;
sample_buffer_PLB_MSSize : in std_logic_vector(0 to 1);
sample_buffer_PLB_MRearbitrate : in std_logic;
sample_buffer_PLB_MTimeout : in std_logic;
sample_buffer_PLB_MBusy : in std_logic;
sample_buffer_PLB_MRdErr : in std_logic;
sample_buffer_PLB_MWrErr : in std_logic;
sample_buffer_PLB_MIRQ : in std_logic;
sample_buffer_PLB_MRdDBus : in std_logic_vector(0 to 63);
sample_buffer_PLB_MRdWdAddr : in std_logic_vector(0 to 3);
sample_buffer_PLB_MRdDAck : in std_logic;
sample_buffer_PLB_MRdBTerm : in std_logic;
sample_buffer_PLB_MWrDAck : in std_logic;
sample_buffer_PLB_MWrBTerm : in std_logic;
splb_slv0_SPLB_Clk : in std_logic;
splb_slv0_SPLB_Rst : in std_logic;
splb_slv0_PLB_ABus : in std_logic_vector(0 to 31);
splb_slv0_PLB_UABus : in std_logic_vector(0 to 31);
splb_slv0_PLB_PAValid : in std_logic;
splb_slv0_PLB_SAValid : in std_logic;
splb_slv0_PLB_rdPrim : in std_logic;
splb_slv0_PLB_wrPrim : in std_logic;
splb_slv0_PLB_masterID : in std_logic_vector(0 to 2);
splb_slv0_PLB_abort : in std_logic;
splb_slv0_PLB_busLock : in std_logic;
splb_slv0_PLB_RNW : in std_logic;
splb_slv0_PLB_BE : in std_logic_vector(0 to 7);
splb_slv0_PLB_MSize : in std_logic_vector(0 to 1);
splb_slv0_PLB_size : in std_logic_vector(0 to 3);
splb_slv0_PLB_type : in std_logic_vector(0 to 2);
splb_slv0_PLB_lockErr : in std_logic;
splb_slv0_PLB_wrDBus : in std_logic_vector(0 to 63);
splb_slv0_PLB_wrBurst : in std_logic;
splb_slv0_PLB_rdBurst : in std_logic;
splb_slv0_PLB_wrPendReq : in std_logic;
splb_slv0_PLB_rdPendReq : in std_logic;
splb_slv0_PLB_wrPendPri : in std_logic_vector(0 to 1);
splb_slv0_PLB_rdPendPri : in std_logic_vector(0 to 1);
splb_slv0_PLB_reqPri : in std_logic_vector(0 to 1);
splb_slv0_PLB_TAttribute : in std_logic_vector(0 to 15);
splb_slv0_Sl_addrAck : out std_logic;
splb_slv0_Sl_SSize : out std_logic_vector(0 to 1);
splb_slv0_Sl_wait : out std_logic;
splb_slv0_Sl_rearbitrate : out std_logic;
splb_slv0_Sl_wrDAck : out std_logic;
splb_slv0_Sl_wrComp : out std_logic;
splb_slv0_Sl_wrBTerm : out std_logic;
splb_slv0_Sl_rdDBus : out std_logic_vector(0 to 63);
splb_slv0_Sl_rdWdAddr : out std_logic_vector(0 to 3);
splb_slv0_Sl_rdDAck : out std_logic;
splb_slv0_Sl_rdComp : out std_logic;
splb_slv0_Sl_rdBTerm : out std_logic;
splb_slv0_Sl_MBusy : out std_logic_vector(0 to 5);
splb_slv0_Sl_MWrErr : out std_logic_vector(0 to 5);
splb_slv0_Sl_MRdErr : out std_logic_vector(0 to 5);
splb_slv0_Sl_MIRQ : out std_logic_vector(0 to 5)
);
end component;
component system_ac0_plb_wrapper is
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to 0);
MPLB_Rst : out std_logic_vector(0 to 14);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to 31);
DCR_ABus : in std_logic_vector(0 to 9);
DCR_DBus : in std_logic_vector(0 to 31);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to 479);
M_UABus : in std_logic_vector(0 to 479);
M_BE : in std_logic_vector(0 to 119);
M_RNW : in std_logic_vector(0 to 14);
M_abort : in std_logic_vector(0 to 14);
M_busLock : in std_logic_vector(0 to 14);
M_TAttribute : in std_logic_vector(0 to 239);
M_lockErr : in std_logic_vector(0 to 14);
M_MSize : in std_logic_vector(0 to 29);
M_priority : in std_logic_vector(0 to 29);
M_rdBurst : in std_logic_vector(0 to 14);
M_request : in std_logic_vector(0 to 14);
M_size : in std_logic_vector(0 to 59);
M_type : in std_logic_vector(0 to 44);
M_wrBurst : in std_logic_vector(0 to 14);
M_wrDBus : in std_logic_vector(0 to 959);
Sl_addrAck : in std_logic_vector(0 to 0);
Sl_MRdErr : in std_logic_vector(0 to 14);
Sl_MWrErr : in std_logic_vector(0 to 14);
Sl_MBusy : in std_logic_vector(0 to 14);
Sl_rdBTerm : in std_logic_vector(0 to 0);
Sl_rdComp : in std_logic_vector(0 to 0);
Sl_rdDAck : in std_logic_vector(0 to 0);
Sl_rdDBus : in std_logic_vector(0 to 63);
Sl_rdWdAddr : in std_logic_vector(0 to 3);
Sl_rearbitrate : in std_logic_vector(0 to 0);
Sl_SSize : in std_logic_vector(0 to 1);
Sl_wait : in std_logic_vector(0 to 0);
Sl_wrBTerm : in std_logic_vector(0 to 0);
Sl_wrComp : in std_logic_vector(0 to 0);
Sl_wrDAck : in std_logic_vector(0 to 0);
Sl_MIRQ : in std_logic_vector(0 to 14);
PLB_MIRQ : out std_logic_vector(0 to 14);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to 7);
PLB_MAddrAck : out std_logic_vector(0 to 14);
PLB_MTimeout : out std_logic_vector(0 to 14);
PLB_MBusy : out std_logic_vector(0 to 14);
PLB_MRdErr : out std_logic_vector(0 to 14);
PLB_MWrErr : out std_logic_vector(0 to 14);
PLB_MRdBTerm : out std_logic_vector(0 to 14);
PLB_MRdDAck : out std_logic_vector(0 to 14);
PLB_MRdDBus : out std_logic_vector(0 to 959);
PLB_MRdWdAddr : out std_logic_vector(0 to 59);
PLB_MRearbitrate : out std_logic_vector(0 to 14);
PLB_MWrBTerm : out std_logic_vector(0 to 14);
PLB_MWrDAck : out std_logic_vector(0 to 14);
PLB_MSSize : out std_logic_vector(0 to 29);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to 3);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to 0);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to 63);
PLB_wrPrim : out std_logic_vector(0 to 0);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to 14);
PLB_SMWrErr : out std_logic_vector(0 to 14);
PLB_SMBusy : out std_logic_vector(0 to 14);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to 63);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
Bus_Error_Det : out std_logic
);
end component;
component system_ac0_mb_bridge_wrapper is
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
IP2INTC_Irpt : out std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 3);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 7);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 63);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 63);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 14);
Sl_MWrErr : out std_logic_vector(0 to 14);
Sl_MRdErr : out std_logic_vector(0 to 14);
Sl_MIRQ : out std_logic_vector(0 to 14);
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to 7);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_ABus : out std_logic_vector(0 to 31);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to 63);
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to 63);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
PLB_MBusy : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdWdAddr : in std_logic_vector(0 to 3)
);
end component;
component system_ac1_plb_wrapper is
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to 0);
MPLB_Rst : out std_logic_vector(0 to 14);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to 31);
DCR_ABus : in std_logic_vector(0 to 9);
DCR_DBus : in std_logic_vector(0 to 31);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to 479);
M_UABus : in std_logic_vector(0 to 479);
M_BE : in std_logic_vector(0 to 119);
M_RNW : in std_logic_vector(0 to 14);
M_abort : in std_logic_vector(0 to 14);
M_busLock : in std_logic_vector(0 to 14);
M_TAttribute : in std_logic_vector(0 to 239);
M_lockErr : in std_logic_vector(0 to 14);
M_MSize : in std_logic_vector(0 to 29);
M_priority : in std_logic_vector(0 to 29);
M_rdBurst : in std_logic_vector(0 to 14);
M_request : in std_logic_vector(0 to 14);
M_size : in std_logic_vector(0 to 59);
M_type : in std_logic_vector(0 to 44);
M_wrBurst : in std_logic_vector(0 to 14);
M_wrDBus : in std_logic_vector(0 to 959);
Sl_addrAck : in std_logic_vector(0 to 0);
Sl_MRdErr : in std_logic_vector(0 to 14);
Sl_MWrErr : in std_logic_vector(0 to 14);
Sl_MBusy : in std_logic_vector(0 to 14);
Sl_rdBTerm : in std_logic_vector(0 to 0);
Sl_rdComp : in std_logic_vector(0 to 0);
Sl_rdDAck : in std_logic_vector(0 to 0);
Sl_rdDBus : in std_logic_vector(0 to 63);
Sl_rdWdAddr : in std_logic_vector(0 to 3);
Sl_rearbitrate : in std_logic_vector(0 to 0);
Sl_SSize : in std_logic_vector(0 to 1);
Sl_wait : in std_logic_vector(0 to 0);
Sl_wrBTerm : in std_logic_vector(0 to 0);
Sl_wrComp : in std_logic_vector(0 to 0);
Sl_wrDAck : in std_logic_vector(0 to 0);
Sl_MIRQ : in std_logic_vector(0 to 14);
PLB_MIRQ : out std_logic_vector(0 to 14);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to 7);
PLB_MAddrAck : out std_logic_vector(0 to 14);
PLB_MTimeout : out std_logic_vector(0 to 14);
PLB_MBusy : out std_logic_vector(0 to 14);
PLB_MRdErr : out std_logic_vector(0 to 14);
PLB_MWrErr : out std_logic_vector(0 to 14);
PLB_MRdBTerm : out std_logic_vector(0 to 14);
PLB_MRdDAck : out std_logic_vector(0 to 14);
PLB_MRdDBus : out std_logic_vector(0 to 959);
PLB_MRdWdAddr : out std_logic_vector(0 to 59);
PLB_MRearbitrate : out std_logic_vector(0 to 14);
PLB_MWrBTerm : out std_logic_vector(0 to 14);
PLB_MWrDAck : out std_logic_vector(0 to 14);
PLB_MSSize : out std_logic_vector(0 to 29);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to 3);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to 0);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to 63);
PLB_wrPrim : out std_logic_vector(0 to 0);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to 14);
PLB_SMWrErr : out std_logic_vector(0 to 14);
PLB_SMBusy : out std_logic_vector(0 to 14);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to 63);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
Bus_Error_Det : out std_logic
);
end component;
component system_ac1_mb_bridge_wrapper is
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
IP2INTC_Irpt : out std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 3);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 7);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 63);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 63);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 14);
Sl_MWrErr : out std_logic_vector(0 to 14);
Sl_MRdErr : out std_logic_vector(0 to 14);
Sl_MIRQ : out std_logic_vector(0 to 14);
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to 7);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_ABus : out std_logic_vector(0 to 31);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to 63);
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to 63);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
PLB_MBusy : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdWdAddr : in std_logic_vector(0 to 3)
);
end component;
component system_nfa_accept_samples_generic_hw_top_5_wrapper is
port (
aclk : in std_logic;
aresetn : in std_logic;
indices_MPLB_Clk : in std_logic;
indices_MPLB_Rst : in std_logic;
indices_M_request : out std_logic;
indices_M_priority : out std_logic_vector(0 to 1);
indices_M_busLock : out std_logic;
indices_M_RNW : out std_logic;
indices_M_BE : out std_logic_vector(0 to 7);
indices_M_MSize : out std_logic_vector(0 to 1);
indices_M_size : out std_logic_vector(0 to 3);
indices_M_type : out std_logic_vector(0 to 2);
indices_M_TAttribute : out std_logic_vector(0 to 15);
indices_M_lockErr : out std_logic;
indices_M_abort : out std_logic;
indices_M_UABus : out std_logic_vector(0 to 31);
indices_M_ABus : out std_logic_vector(0 to 31);
indices_M_wrDBus : out std_logic_vector(0 to 63);
indices_M_wrBurst : out std_logic;
indices_M_rdBurst : out std_logic;
indices_PLB_MAddrAck : in std_logic;
indices_PLB_MSSize : in std_logic_vector(0 to 1);
indices_PLB_MRearbitrate : in std_logic;
indices_PLB_MTimeout : in std_logic;
indices_PLB_MBusy : in std_logic;
indices_PLB_MRdErr : in std_logic;
indices_PLB_MWrErr : in std_logic;
indices_PLB_MIRQ : in std_logic;
indices_PLB_MRdDBus : in std_logic_vector(0 to 63);
indices_PLB_MRdWdAddr : in std_logic_vector(0 to 3);
indices_PLB_MRdDAck : in std_logic;
indices_PLB_MRdBTerm : in std_logic;
indices_PLB_MWrDAck : in std_logic;
indices_PLB_MWrBTerm : in std_logic;
nfa_finals_buckets_MPLB_Clk : in std_logic;
nfa_finals_buckets_MPLB_Rst : in std_logic;
nfa_finals_buckets_M_request : out std_logic;
nfa_finals_buckets_M_priority : out std_logic_vector(0 to 1);
nfa_finals_buckets_M_busLock : out std_logic;
nfa_finals_buckets_M_RNW : out std_logic;
nfa_finals_buckets_M_BE : out std_logic_vector(0 to 7);
nfa_finals_buckets_M_MSize : out std_logic_vector(0 to 1);
nfa_finals_buckets_M_size : out std_logic_vector(0 to 3);
nfa_finals_buckets_M_type : out std_logic_vector(0 to 2);
nfa_finals_buckets_M_TAttribute : out std_logic_vector(0 to 15);
nfa_finals_buckets_M_lockErr : out std_logic;
nfa_finals_buckets_M_abort : out std_logic;
nfa_finals_buckets_M_UABus : out std_logic_vector(0 to 31);
nfa_finals_buckets_M_ABus : out std_logic_vector(0 to 31);
nfa_finals_buckets_M_wrDBus : out std_logic_vector(0 to 63);
nfa_finals_buckets_M_wrBurst : out std_logic;
nfa_finals_buckets_M_rdBurst : out std_logic;
nfa_finals_buckets_PLB_MAddrAck : in std_logic;
nfa_finals_buckets_PLB_MSSize : in std_logic_vector(0 to 1);
nfa_finals_buckets_PLB_MRearbitrate : in std_logic;
nfa_finals_buckets_PLB_MTimeout : in std_logic;
nfa_finals_buckets_PLB_MBusy : in std_logic;
nfa_finals_buckets_PLB_MRdErr : in std_logic;
nfa_finals_buckets_PLB_MWrErr : in std_logic;
nfa_finals_buckets_PLB_MIRQ : in std_logic;
nfa_finals_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63);
nfa_finals_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3);
nfa_finals_buckets_PLB_MRdDAck : in std_logic;
nfa_finals_buckets_PLB_MRdBTerm : in std_logic;
nfa_finals_buckets_PLB_MWrDAck : in std_logic;
nfa_finals_buckets_PLB_MWrBTerm : in std_logic;
nfa_forward_buckets_MPLB_Clk : in std_logic;
nfa_forward_buckets_MPLB_Rst : in std_logic;
nfa_forward_buckets_M_request : out std_logic;
nfa_forward_buckets_M_priority : out std_logic_vector(0 to 1);
nfa_forward_buckets_M_busLock : out std_logic;
nfa_forward_buckets_M_RNW : out std_logic;
nfa_forward_buckets_M_BE : out std_logic_vector(0 to 7);
nfa_forward_buckets_M_MSize : out std_logic_vector(0 to 1);
nfa_forward_buckets_M_size : out std_logic_vector(0 to 3);
nfa_forward_buckets_M_type : out std_logic_vector(0 to 2);
nfa_forward_buckets_M_TAttribute : out std_logic_vector(0 to 15);
nfa_forward_buckets_M_lockErr : out std_logic;
nfa_forward_buckets_M_abort : out std_logic;
nfa_forward_buckets_M_UABus : out std_logic_vector(0 to 31);
nfa_forward_buckets_M_ABus : out std_logic_vector(0 to 31);
nfa_forward_buckets_M_wrDBus : out std_logic_vector(0 to 63);
nfa_forward_buckets_M_wrBurst : out std_logic;
nfa_forward_buckets_M_rdBurst : out std_logic;
nfa_forward_buckets_PLB_MAddrAck : in std_logic;
nfa_forward_buckets_PLB_MSSize : in std_logic_vector(0 to 1);
nfa_forward_buckets_PLB_MRearbitrate : in std_logic;
nfa_forward_buckets_PLB_MTimeout : in std_logic;
nfa_forward_buckets_PLB_MBusy : in std_logic;
nfa_forward_buckets_PLB_MRdErr : in std_logic;
nfa_forward_buckets_PLB_MWrErr : in std_logic;
nfa_forward_buckets_PLB_MIRQ : in std_logic;
nfa_forward_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63);
nfa_forward_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3);
nfa_forward_buckets_PLB_MRdDAck : in std_logic;
nfa_forward_buckets_PLB_MRdBTerm : in std_logic;
nfa_forward_buckets_PLB_MWrDAck : in std_logic;
nfa_forward_buckets_PLB_MWrBTerm : in std_logic;
nfa_initials_buckets_MPLB_Clk : in std_logic;
nfa_initials_buckets_MPLB_Rst : in std_logic;
nfa_initials_buckets_M_request : out std_logic;
nfa_initials_buckets_M_priority : out std_logic_vector(0 to 1);
nfa_initials_buckets_M_busLock : out std_logic;
nfa_initials_buckets_M_RNW : out std_logic;
nfa_initials_buckets_M_BE : out std_logic_vector(0 to 7);
nfa_initials_buckets_M_MSize : out std_logic_vector(0 to 1);
nfa_initials_buckets_M_size : out std_logic_vector(0 to 3);
nfa_initials_buckets_M_type : out std_logic_vector(0 to 2);
nfa_initials_buckets_M_TAttribute : out std_logic_vector(0 to 15);
nfa_initials_buckets_M_lockErr : out std_logic;
nfa_initials_buckets_M_abort : out std_logic;
nfa_initials_buckets_M_UABus : out std_logic_vector(0 to 31);
nfa_initials_buckets_M_ABus : out std_logic_vector(0 to 31);
nfa_initials_buckets_M_wrDBus : out std_logic_vector(0 to 63);
nfa_initials_buckets_M_wrBurst : out std_logic;
nfa_initials_buckets_M_rdBurst : out std_logic;
nfa_initials_buckets_PLB_MAddrAck : in std_logic;
nfa_initials_buckets_PLB_MSSize : in std_logic_vector(0 to 1);
nfa_initials_buckets_PLB_MRearbitrate : in std_logic;
nfa_initials_buckets_PLB_MTimeout : in std_logic;
nfa_initials_buckets_PLB_MBusy : in std_logic;
nfa_initials_buckets_PLB_MRdErr : in std_logic;
nfa_initials_buckets_PLB_MWrErr : in std_logic;
nfa_initials_buckets_PLB_MIRQ : in std_logic;
nfa_initials_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63);
nfa_initials_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3);
nfa_initials_buckets_PLB_MRdDAck : in std_logic;
nfa_initials_buckets_PLB_MRdBTerm : in std_logic;
nfa_initials_buckets_PLB_MWrDAck : in std_logic;
nfa_initials_buckets_PLB_MWrBTerm : in std_logic;
sample_buffer_MPLB_Clk : in std_logic;
sample_buffer_MPLB_Rst : in std_logic;
sample_buffer_M_request : out std_logic;
sample_buffer_M_priority : out std_logic_vector(0 to 1);
sample_buffer_M_busLock : out std_logic;
sample_buffer_M_RNW : out std_logic;
sample_buffer_M_BE : out std_logic_vector(0 to 7);
sample_buffer_M_MSize : out std_logic_vector(0 to 1);
sample_buffer_M_size : out std_logic_vector(0 to 3);
sample_buffer_M_type : out std_logic_vector(0 to 2);
sample_buffer_M_TAttribute : out std_logic_vector(0 to 15);
sample_buffer_M_lockErr : out std_logic;
sample_buffer_M_abort : out std_logic;
sample_buffer_M_UABus : out std_logic_vector(0 to 31);
sample_buffer_M_ABus : out std_logic_vector(0 to 31);
sample_buffer_M_wrDBus : out std_logic_vector(0 to 63);
sample_buffer_M_wrBurst : out std_logic;
sample_buffer_M_rdBurst : out std_logic;
sample_buffer_PLB_MAddrAck : in std_logic;
sample_buffer_PLB_MSSize : in std_logic_vector(0 to 1);
sample_buffer_PLB_MRearbitrate : in std_logic;
sample_buffer_PLB_MTimeout : in std_logic;
sample_buffer_PLB_MBusy : in std_logic;
sample_buffer_PLB_MRdErr : in std_logic;
sample_buffer_PLB_MWrErr : in std_logic;
sample_buffer_PLB_MIRQ : in std_logic;
sample_buffer_PLB_MRdDBus : in std_logic_vector(0 to 63);
sample_buffer_PLB_MRdWdAddr : in std_logic_vector(0 to 3);
sample_buffer_PLB_MRdDAck : in std_logic;
sample_buffer_PLB_MRdBTerm : in std_logic;
sample_buffer_PLB_MWrDAck : in std_logic;
sample_buffer_PLB_MWrBTerm : in std_logic;
splb_slv0_SPLB_Clk : in std_logic;
splb_slv0_SPLB_Rst : in std_logic;
splb_slv0_PLB_ABus : in std_logic_vector(0 to 31);
splb_slv0_PLB_UABus : in std_logic_vector(0 to 31);
splb_slv0_PLB_PAValid : in std_logic;
splb_slv0_PLB_SAValid : in std_logic;
splb_slv0_PLB_rdPrim : in std_logic;
splb_slv0_PLB_wrPrim : in std_logic;
splb_slv0_PLB_masterID : in std_logic_vector(0 to 2);
splb_slv0_PLB_abort : in std_logic;
splb_slv0_PLB_busLock : in std_logic;
splb_slv0_PLB_RNW : in std_logic;
splb_slv0_PLB_BE : in std_logic_vector(0 to 7);
splb_slv0_PLB_MSize : in std_logic_vector(0 to 1);
splb_slv0_PLB_size : in std_logic_vector(0 to 3);
splb_slv0_PLB_type : in std_logic_vector(0 to 2);
splb_slv0_PLB_lockErr : in std_logic;
splb_slv0_PLB_wrDBus : in std_logic_vector(0 to 63);
splb_slv0_PLB_wrBurst : in std_logic;
splb_slv0_PLB_rdBurst : in std_logic;
splb_slv0_PLB_wrPendReq : in std_logic;
splb_slv0_PLB_rdPendReq : in std_logic;
splb_slv0_PLB_wrPendPri : in std_logic_vector(0 to 1);
splb_slv0_PLB_rdPendPri : in std_logic_vector(0 to 1);
splb_slv0_PLB_reqPri : in std_logic_vector(0 to 1);
splb_slv0_PLB_TAttribute : in std_logic_vector(0 to 15);
splb_slv0_Sl_addrAck : out std_logic;
splb_slv0_Sl_SSize : out std_logic_vector(0 to 1);
splb_slv0_Sl_wait : out std_logic;
splb_slv0_Sl_rearbitrate : out std_logic;
splb_slv0_Sl_wrDAck : out std_logic;
splb_slv0_Sl_wrComp : out std_logic;
splb_slv0_Sl_wrBTerm : out std_logic;
splb_slv0_Sl_rdDBus : out std_logic_vector(0 to 63);
splb_slv0_Sl_rdWdAddr : out std_logic_vector(0 to 3);
splb_slv0_Sl_rdDAck : out std_logic;
splb_slv0_Sl_rdComp : out std_logic;
splb_slv0_Sl_rdBTerm : out std_logic;
splb_slv0_Sl_MBusy : out std_logic_vector(0 to 5);
splb_slv0_Sl_MWrErr : out std_logic_vector(0 to 5);
splb_slv0_Sl_MRdErr : out std_logic_vector(0 to 5);
splb_slv0_Sl_MIRQ : out std_logic_vector(0 to 5)
);
end component;
component IOBUF is
port (
I : in std_logic;
IO : inout std_logic;
O : out std_logic;
T : in std_logic
);
end component;
component IBUFGDS is
port (
I : in std_logic;
IB : in std_logic;
O : out std_logic
);
end component;
-- Internal signals
signal CLK_S : std_logic;
signal Dcm_all_locked : std_logic;
signal Debug_SYS_Rst : std_logic;
signal Ext_BRK : std_logic;
signal Ext_NM_BRK : std_logic;
signal PCIe_Bridge_IP2INTC_Irpt : std_logic;
signal PCIe_Diff_Clk : std_logic;
signal SRAM_CLK_FB_s : std_logic;
signal SRAM_CLK_OUT_s : std_logic;
signal ac0_plb_MPLB_Rst : std_logic_vector(0 to 14);
signal ac0_plb_M_ABus : std_logic_vector(0 to 479);
signal ac0_plb_M_BE : std_logic_vector(0 to 119);
signal ac0_plb_M_MSize : std_logic_vector(0 to 29);
signal ac0_plb_M_RNW : std_logic_vector(0 to 14);
signal ac0_plb_M_TAttribute : std_logic_vector(0 to 239);
signal ac0_plb_M_UABus : std_logic_vector(0 to 479);
signal ac0_plb_M_abort : std_logic_vector(0 to 14);
signal ac0_plb_M_busLock : std_logic_vector(0 to 14);
signal ac0_plb_M_lockErr : std_logic_vector(0 to 14);
signal ac0_plb_M_priority : std_logic_vector(0 to 29);
signal ac0_plb_M_rdBurst : std_logic_vector(0 to 14);
signal ac0_plb_M_request : std_logic_vector(0 to 14);
signal ac0_plb_M_size : std_logic_vector(0 to 59);
signal ac0_plb_M_type : std_logic_vector(0 to 44);
signal ac0_plb_M_wrBurst : std_logic_vector(0 to 14);
signal ac0_plb_M_wrDBus : std_logic_vector(0 to 959);
signal ac0_plb_PLB_ABus : std_logic_vector(0 to 31);
signal ac0_plb_PLB_BE : std_logic_vector(0 to 7);
signal ac0_plb_PLB_MAddrAck : std_logic_vector(0 to 14);
signal ac0_plb_PLB_MBusy : std_logic_vector(0 to 14);
signal ac0_plb_PLB_MIRQ : std_logic_vector(0 to 14);
signal ac0_plb_PLB_MRdBTerm : std_logic_vector(0 to 14);
signal ac0_plb_PLB_MRdDAck : std_logic_vector(0 to 14);
signal ac0_plb_PLB_MRdDBus : std_logic_vector(0 to 959);
signal ac0_plb_PLB_MRdErr : std_logic_vector(0 to 14);
signal ac0_plb_PLB_MRdWdAddr : std_logic_vector(0 to 59);
signal ac0_plb_PLB_MRearbitrate : std_logic_vector(0 to 14);
signal ac0_plb_PLB_MSSize : std_logic_vector(0 to 29);
signal ac0_plb_PLB_MSize : std_logic_vector(0 to 1);
signal ac0_plb_PLB_MTimeout : std_logic_vector(0 to 14);
signal ac0_plb_PLB_MWrBTerm : std_logic_vector(0 to 14);
signal ac0_plb_PLB_MWrDAck : std_logic_vector(0 to 14);
signal ac0_plb_PLB_MWrErr : std_logic_vector(0 to 14);
signal ac0_plb_PLB_PAValid : std_logic;
signal ac0_plb_PLB_RNW : std_logic;
signal ac0_plb_PLB_SAValid : std_logic;
signal ac0_plb_PLB_TAttribute : std_logic_vector(0 to 15);
signal ac0_plb_PLB_UABus : std_logic_vector(0 to 31);
signal ac0_plb_PLB_abort : std_logic;
signal ac0_plb_PLB_busLock : std_logic;
signal ac0_plb_PLB_lockErr : std_logic;
signal ac0_plb_PLB_masterID : std_logic_vector(0 to 3);
signal ac0_plb_PLB_rdBurst : std_logic;
signal ac0_plb_PLB_rdPendPri : std_logic_vector(0 to 1);
signal ac0_plb_PLB_rdPendReq : std_logic;
signal ac0_plb_PLB_rdPrim : std_logic_vector(0 to 0);
signal ac0_plb_PLB_reqPri : std_logic_vector(0 to 1);
signal ac0_plb_PLB_size : std_logic_vector(0 to 3);
signal ac0_plb_PLB_type : std_logic_vector(0 to 2);
signal ac0_plb_PLB_wrBurst : std_logic;
signal ac0_plb_PLB_wrDBus : std_logic_vector(0 to 63);
signal ac0_plb_PLB_wrPendPri : std_logic_vector(0 to 1);
signal ac0_plb_PLB_wrPendReq : std_logic;
signal ac0_plb_PLB_wrPrim : std_logic_vector(0 to 0);
signal ac0_plb_SPLB_Rst : std_logic_vector(0 to 0);
signal ac0_plb_Sl_MBusy : std_logic_vector(0 to 14);
signal ac0_plb_Sl_MIRQ : std_logic_vector(0 to 14);
signal ac0_plb_Sl_MRdErr : std_logic_vector(0 to 14);
signal ac0_plb_Sl_MWrErr : std_logic_vector(0 to 14);
signal ac0_plb_Sl_SSize : std_logic_vector(0 to 1);
signal ac0_plb_Sl_addrAck : std_logic_vector(0 to 0);
signal ac0_plb_Sl_rdBTerm : std_logic_vector(0 to 0);
signal ac0_plb_Sl_rdComp : std_logic_vector(0 to 0);
signal ac0_plb_Sl_rdDAck : std_logic_vector(0 to 0);
signal ac0_plb_Sl_rdDBus : std_logic_vector(0 to 63);
signal ac0_plb_Sl_rdWdAddr : std_logic_vector(0 to 3);
signal ac0_plb_Sl_rearbitrate : std_logic_vector(0 to 0);
signal ac0_plb_Sl_wait : std_logic_vector(0 to 0);
signal ac0_plb_Sl_wrBTerm : std_logic_vector(0 to 0);
signal ac0_plb_Sl_wrComp : std_logic_vector(0 to 0);
signal ac0_plb_Sl_wrDAck : std_logic_vector(0 to 0);
signal ac1_plb_MPLB_Rst : std_logic_vector(0 to 14);
signal ac1_plb_M_ABus : std_logic_vector(0 to 479);
signal ac1_plb_M_BE : std_logic_vector(0 to 119);
signal ac1_plb_M_MSize : std_logic_vector(0 to 29);
signal ac1_plb_M_RNW : std_logic_vector(0 to 14);
signal ac1_plb_M_TAttribute : std_logic_vector(0 to 239);
signal ac1_plb_M_UABus : std_logic_vector(0 to 479);
signal ac1_plb_M_abort : std_logic_vector(0 to 14);
signal ac1_plb_M_busLock : std_logic_vector(0 to 14);
signal ac1_plb_M_lockErr : std_logic_vector(0 to 14);
signal ac1_plb_M_priority : std_logic_vector(0 to 29);
signal ac1_plb_M_rdBurst : std_logic_vector(0 to 14);
signal ac1_plb_M_request : std_logic_vector(0 to 14);
signal ac1_plb_M_size : std_logic_vector(0 to 59);
signal ac1_plb_M_type : std_logic_vector(0 to 44);
signal ac1_plb_M_wrBurst : std_logic_vector(0 to 14);
signal ac1_plb_M_wrDBus : std_logic_vector(0 to 959);
signal ac1_plb_PLB_ABus : std_logic_vector(0 to 31);
signal ac1_plb_PLB_BE : std_logic_vector(0 to 7);
signal ac1_plb_PLB_MAddrAck : std_logic_vector(0 to 14);
signal ac1_plb_PLB_MBusy : std_logic_vector(0 to 14);
signal ac1_plb_PLB_MIRQ : std_logic_vector(0 to 14);
signal ac1_plb_PLB_MRdBTerm : std_logic_vector(0 to 14);
signal ac1_plb_PLB_MRdDAck : std_logic_vector(0 to 14);
signal ac1_plb_PLB_MRdDBus : std_logic_vector(0 to 959);
signal ac1_plb_PLB_MRdErr : std_logic_vector(0 to 14);
signal ac1_plb_PLB_MRdWdAddr : std_logic_vector(0 to 59);
signal ac1_plb_PLB_MRearbitrate : std_logic_vector(0 to 14);
signal ac1_plb_PLB_MSSize : std_logic_vector(0 to 29);
signal ac1_plb_PLB_MSize : std_logic_vector(0 to 1);
signal ac1_plb_PLB_MTimeout : std_logic_vector(0 to 14);
signal ac1_plb_PLB_MWrBTerm : std_logic_vector(0 to 14);
signal ac1_plb_PLB_MWrDAck : std_logic_vector(0 to 14);
signal ac1_plb_PLB_MWrErr : std_logic_vector(0 to 14);
signal ac1_plb_PLB_PAValid : std_logic;
signal ac1_plb_PLB_RNW : std_logic;
signal ac1_plb_PLB_SAValid : std_logic;
signal ac1_plb_PLB_TAttribute : std_logic_vector(0 to 15);
signal ac1_plb_PLB_UABus : std_logic_vector(0 to 31);
signal ac1_plb_PLB_abort : std_logic;
signal ac1_plb_PLB_busLock : std_logic;
signal ac1_plb_PLB_lockErr : std_logic;
signal ac1_plb_PLB_masterID : std_logic_vector(0 to 3);
signal ac1_plb_PLB_rdBurst : std_logic;
signal ac1_plb_PLB_rdPendPri : std_logic_vector(0 to 1);
signal ac1_plb_PLB_rdPendReq : std_logic;
signal ac1_plb_PLB_rdPrim : std_logic_vector(0 to 0);
signal ac1_plb_PLB_reqPri : std_logic_vector(0 to 1);
signal ac1_plb_PLB_size : std_logic_vector(0 to 3);
signal ac1_plb_PLB_type : std_logic_vector(0 to 2);
signal ac1_plb_PLB_wrBurst : std_logic;
signal ac1_plb_PLB_wrDBus : std_logic_vector(0 to 63);
signal ac1_plb_PLB_wrPendPri : std_logic_vector(0 to 1);
signal ac1_plb_PLB_wrPendReq : std_logic;
signal ac1_plb_PLB_wrPrim : std_logic_vector(0 to 0);
signal ac1_plb_SPLB_Rst : std_logic_vector(0 to 0);
signal ac1_plb_Sl_MBusy : std_logic_vector(0 to 14);
signal ac1_plb_Sl_MIRQ : std_logic_vector(0 to 14);
signal ac1_plb_Sl_MRdErr : std_logic_vector(0 to 14);
signal ac1_plb_Sl_MWrErr : std_logic_vector(0 to 14);
signal ac1_plb_Sl_SSize : std_logic_vector(0 to 1);
signal ac1_plb_Sl_addrAck : std_logic_vector(0 to 0);
signal ac1_plb_Sl_rdBTerm : std_logic_vector(0 to 0);
signal ac1_plb_Sl_rdComp : std_logic_vector(0 to 0);
signal ac1_plb_Sl_rdDAck : std_logic_vector(0 to 0);
signal ac1_plb_Sl_rdDBus : std_logic_vector(0 to 63);
signal ac1_plb_Sl_rdWdAddr : std_logic_vector(0 to 3);
signal ac1_plb_Sl_rearbitrate : std_logic_vector(0 to 0);
signal ac1_plb_Sl_wait : std_logic_vector(0 to 0);
signal ac1_plb_Sl_wrBTerm : std_logic_vector(0 to 0);
signal ac1_plb_Sl_wrComp : std_logic_vector(0 to 0);
signal ac1_plb_Sl_wrDAck : std_logic_vector(0 to 0);
signal clk_62_5000MHzPLL0 : std_logic;
signal clk_125_0000MHz90PLL0 : std_logic;
signal clk_125_0000MHzPLL0 : std_logic;
signal clk_200_0000MHz : std_logic;
signal dlmb_LMB_ABus : std_logic_vector(0 to 31);
signal dlmb_LMB_AddrStrobe : std_logic;
signal dlmb_LMB_BE : std_logic_vector(0 to 3);
signal dlmb_LMB_CE : std_logic;
signal dlmb_LMB_ReadDBus : std_logic_vector(0 to 31);
signal dlmb_LMB_ReadStrobe : std_logic;
signal dlmb_LMB_Ready : std_logic;
signal dlmb_LMB_Rst : std_logic;
signal dlmb_LMB_UE : std_logic;
signal dlmb_LMB_Wait : std_logic;
signal dlmb_LMB_WriteDBus : std_logic_vector(0 to 31);
signal dlmb_LMB_WriteStrobe : std_logic;
signal dlmb_M_ABus : std_logic_vector(0 to 31);
signal dlmb_M_AddrStrobe : std_logic;
signal dlmb_M_BE : std_logic_vector(0 to 3);
signal dlmb_M_DBus : std_logic_vector(0 to 31);
signal dlmb_M_ReadStrobe : std_logic;
signal dlmb_M_WriteStrobe : std_logic;
signal dlmb_Sl_CE : std_logic_vector(0 to 0);
signal dlmb_Sl_DBus : std_logic_vector(0 to 31);
signal dlmb_Sl_Ready : std_logic_vector(0 to 0);
signal dlmb_Sl_UE : std_logic_vector(0 to 0);
signal dlmb_Sl_Wait : std_logic_vector(0 to 0);
signal dlmb_port_BRAM_Addr : std_logic_vector(0 to 31);
signal dlmb_port_BRAM_Clk : std_logic;
signal dlmb_port_BRAM_Din : std_logic_vector(0 to 31);
signal dlmb_port_BRAM_Dout : std_logic_vector(0 to 31);
signal dlmb_port_BRAM_EN : std_logic;
signal dlmb_port_BRAM_Rst : std_logic;
signal dlmb_port_BRAM_WEN : std_logic_vector(0 to 3);
signal fpga_0_SRAM_Mem_A_pin_vslice_7_30_concat : std_logic_vector(7 to 30);
signal fpga_0_SRAM_Mem_DQ_pin_I : std_logic_vector(0 to 31);
signal fpga_0_SRAM_Mem_DQ_pin_O : std_logic_vector(0 to 31);
signal fpga_0_SRAM_Mem_DQ_pin_T : std_logic_vector(0 to 31);
signal ilmb_LMB_ABus : std_logic_vector(0 to 31);
signal ilmb_LMB_AddrStrobe : std_logic;
signal ilmb_LMB_BE : std_logic_vector(0 to 3);
signal ilmb_LMB_CE : std_logic;
signal ilmb_LMB_ReadDBus : std_logic_vector(0 to 31);
signal ilmb_LMB_ReadStrobe : std_logic;
signal ilmb_LMB_Ready : std_logic;
signal ilmb_LMB_Rst : std_logic;
signal ilmb_LMB_UE : std_logic;
signal ilmb_LMB_Wait : std_logic;
signal ilmb_LMB_WriteDBus : std_logic_vector(0 to 31);
signal ilmb_LMB_WriteStrobe : std_logic;
signal ilmb_M_ABus : std_logic_vector(0 to 31);
signal ilmb_M_AddrStrobe : std_logic;
signal ilmb_M_ReadStrobe : std_logic;
signal ilmb_Sl_CE : std_logic_vector(0 to 0);
signal ilmb_Sl_DBus : std_logic_vector(0 to 31);
signal ilmb_Sl_Ready : std_logic_vector(0 to 0);
signal ilmb_Sl_UE : std_logic_vector(0 to 0);
signal ilmb_Sl_Wait : std_logic_vector(0 to 0);
signal ilmb_port_BRAM_Addr : std_logic_vector(0 to 31);
signal ilmb_port_BRAM_Clk : std_logic;
signal ilmb_port_BRAM_Din : std_logic_vector(0 to 31);
signal ilmb_port_BRAM_Dout : std_logic_vector(0 to 31);
signal ilmb_port_BRAM_EN : std_logic;
signal ilmb_port_BRAM_Rst : std_logic;
signal ilmb_port_BRAM_WEN : std_logic_vector(0 to 3);
signal mb_plb_MPLB_Rst : std_logic_vector(0 to 5);
signal mb_plb_M_ABort : std_logic_vector(0 to 5);
signal mb_plb_M_ABus : std_logic_vector(0 to 191);
signal mb_plb_M_BE : std_logic_vector(0 to 47);
signal mb_plb_M_MSize : std_logic_vector(0 to 11);
signal mb_plb_M_RNW : std_logic_vector(0 to 5);
signal mb_plb_M_TAttribute : std_logic_vector(0 to 95);
signal mb_plb_M_UABus : std_logic_vector(0 to 191);
signal mb_plb_M_busLock : std_logic_vector(0 to 5);
signal mb_plb_M_lockErr : std_logic_vector(0 to 5);
signal mb_plb_M_priority : std_logic_vector(0 to 11);
signal mb_plb_M_rdBurst : std_logic_vector(0 to 5);
signal mb_plb_M_request : std_logic_vector(0 to 5);
signal mb_plb_M_size : std_logic_vector(0 to 23);
signal mb_plb_M_type : std_logic_vector(0 to 17);
signal mb_plb_M_wrBurst : std_logic_vector(0 to 5);
signal mb_plb_M_wrDBus : std_logic_vector(0 to 383);
signal mb_plb_PLB_ABus : std_logic_vector(0 to 31);
signal mb_plb_PLB_BE : std_logic_vector(0 to 7);
signal mb_plb_PLB_MAddrAck : std_logic_vector(0 to 5);
signal mb_plb_PLB_MBusy : std_logic_vector(0 to 5);
signal mb_plb_PLB_MIRQ : std_logic_vector(0 to 5);
signal mb_plb_PLB_MRdBTerm : std_logic_vector(0 to 5);
signal mb_plb_PLB_MRdDAck : std_logic_vector(0 to 5);
signal mb_plb_PLB_MRdDBus : std_logic_vector(0 to 383);
signal mb_plb_PLB_MRdErr : std_logic_vector(0 to 5);
signal mb_plb_PLB_MRdWdAddr : std_logic_vector(0 to 23);
signal mb_plb_PLB_MRearbitrate : std_logic_vector(0 to 5);
signal mb_plb_PLB_MSSize : std_logic_vector(0 to 11);
signal mb_plb_PLB_MSize : std_logic_vector(0 to 1);
signal mb_plb_PLB_MTimeout : std_logic_vector(0 to 5);
signal mb_plb_PLB_MWrBTerm : std_logic_vector(0 to 5);
signal mb_plb_PLB_MWrDAck : std_logic_vector(0 to 5);
signal mb_plb_PLB_MWrErr : std_logic_vector(0 to 5);
signal mb_plb_PLB_PAValid : std_logic;
signal mb_plb_PLB_RNW : std_logic;
signal mb_plb_PLB_SAValid : std_logic;
signal mb_plb_PLB_TAttribute : std_logic_vector(0 to 15);
signal mb_plb_PLB_UABus : std_logic_vector(0 to 31);
signal mb_plb_PLB_abort : std_logic;
signal mb_plb_PLB_busLock : std_logic;
signal mb_plb_PLB_lockErr : std_logic;
signal mb_plb_PLB_masterID : std_logic_vector(0 to 2);
signal mb_plb_PLB_rdBurst : std_logic;
signal mb_plb_PLB_rdPendPri : std_logic_vector(0 to 1);
signal mb_plb_PLB_rdPendReq : std_logic;
signal mb_plb_PLB_rdPrim : std_logic_vector(0 to 11);
signal mb_plb_PLB_reqPri : std_logic_vector(0 to 1);
signal mb_plb_PLB_size : std_logic_vector(0 to 3);
signal mb_plb_PLB_type : std_logic_vector(0 to 2);
signal mb_plb_PLB_wrBurst : std_logic;
signal mb_plb_PLB_wrDBus : std_logic_vector(0 to 63);
signal mb_plb_PLB_wrPendPri : std_logic_vector(0 to 1);
signal mb_plb_PLB_wrPendReq : std_logic;
signal mb_plb_PLB_wrPrim : std_logic_vector(0 to 11);
signal mb_plb_SPLB_Rst : std_logic_vector(0 to 11);
signal mb_plb_Sl_MBusy : std_logic_vector(0 to 71);
signal mb_plb_Sl_MIRQ : std_logic_vector(0 to 71);
signal mb_plb_Sl_MRdErr : std_logic_vector(0 to 71);
signal mb_plb_Sl_MWrErr : std_logic_vector(0 to 71);
signal mb_plb_Sl_SSize : std_logic_vector(0 to 23);
signal mb_plb_Sl_addrAck : std_logic_vector(0 to 11);
signal mb_plb_Sl_rdBTerm : std_logic_vector(0 to 11);
signal mb_plb_Sl_rdComp : std_logic_vector(0 to 11);
signal mb_plb_Sl_rdDAck : std_logic_vector(0 to 11);
signal mb_plb_Sl_rdDBus : std_logic_vector(0 to 767);
signal mb_plb_Sl_rdWdAddr : std_logic_vector(0 to 47);
signal mb_plb_Sl_rearbitrate : std_logic_vector(0 to 11);
signal mb_plb_Sl_wait : std_logic_vector(0 to 11);
signal mb_plb_Sl_wrBTerm : std_logic_vector(0 to 11);
signal mb_plb_Sl_wrComp : std_logic_vector(0 to 11);
signal mb_plb_Sl_wrDAck : std_logic_vector(0 to 11);
signal mb_reset : std_logic;
signal microblaze_0_Interrupt : std_logic;
signal microblaze_0_mdm_bus_Dbg_Capture : std_logic;
signal microblaze_0_mdm_bus_Dbg_Clk : std_logic;
signal microblaze_0_mdm_bus_Dbg_Reg_En : std_logic_vector(0 to 7);
signal microblaze_0_mdm_bus_Dbg_Shift : std_logic;
signal microblaze_0_mdm_bus_Dbg_TDI : std_logic;
signal microblaze_0_mdm_bus_Dbg_TDO : std_logic;
signal microblaze_0_mdm_bus_Dbg_Update : std_logic;
signal microblaze_0_mdm_bus_Debug_Rst : std_logic;
signal net_gnd0 : std_logic;
signal net_gnd1 : std_logic_vector(0 downto 0);
signal net_gnd2 : std_logic_vector(0 to 1);
signal net_gnd3 : std_logic_vector(2 downto 0);
signal net_gnd4 : std_logic_vector(0 to 3);
signal net_gnd6 : std_logic_vector(5 downto 0);
signal net_gnd8 : std_logic_vector(0 to 7);
signal net_gnd10 : std_logic_vector(0 to 9);
signal net_gnd16 : std_logic_vector(0 to 15);
signal net_gnd30 : std_logic_vector(29 downto 0);
signal net_gnd32 : std_logic_vector(0 to 31);
signal net_gnd36 : std_logic_vector(0 to 35);
signal net_gnd64 : std_logic_vector(0 to 63);
signal net_gnd128 : std_logic_vector(0 to 127);
signal net_gnd4096 : std_logic_vector(0 to 4095);
signal net_vcc0 : std_logic;
signal net_vcc4 : std_logic_vector(0 to 3);
signal pgassign1 : std_logic_vector(0 to 0);
signal pgassign2 : std_logic_vector(0 to 0);
signal pgassign3 : std_logic_vector(0 to 0);
signal pgassign4 : std_logic_vector(0 to 0);
signal pgassign5 : std_logic_vector(0 to 0);
signal pgassign6 : std_logic_vector(0 to 0);
signal pgassign7 : std_logic_vector(0 to 6);
signal pgassign8 : std_logic_vector(0 to 0);
signal pgassign9 : std_logic_vector(0 to 31);
signal pgassign10 : std_logic_vector(1 downto 0);
signal proc_sys_reset_0_Peripheral_aresetn : std_logic_vector(0 to 0);
signal sys_bus_reset : std_logic_vector(0 to 0);
signal sys_periph_reset : std_logic_vector(0 to 0);
signal sys_rst_s : std_logic;
signal xps_central_dma_1_IP2INTC_Irpt : std_logic;
attribute BOX_TYPE : STRING;
attribute BOX_TYPE of system_microblaze_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_mb_plb_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_ilmb_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_dlmb_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_dlmb_cntlr_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_ilmb_cntlr_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_lmb_bram_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_ddr2_sdram_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_sram_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_pcie_bridge_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_xps_central_dma_1_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_clock_generator_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_mdm_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_proc_sys_reset_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_xps_intc_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_nfa_accept_samples_generic_hw_top_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_nfa_accept_samples_generic_hw_top_1_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_nfa_accept_samples_generic_hw_top_2_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_nfa_accept_samples_generic_hw_top_3_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_nfa_accept_samples_generic_hw_top_4_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_ac0_plb_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_ac0_mb_bridge_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_ac1_plb_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_ac1_mb_bridge_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_nfa_accept_samples_generic_hw_top_5_wrapper : component is "user_black_box";
begin
-- Internal assignments
fpga_0_SRAM_Mem_A_pin <= fpga_0_SRAM_Mem_A_pin_vslice_7_30_concat;
fpga_0_SRAM_ZBT_CLK_OUT_pin <= SRAM_CLK_OUT_s;
SRAM_CLK_FB_s <= fpga_0_SRAM_ZBT_CLK_FB_pin;
CLK_S <= fpga_0_clk_1_sys_clk_pin;
sys_rst_s <= fpga_0_rst_1_sys_rst_pin;
pgassign7(0 to 6) <= B"0000000";
pgassign8(0 to 0) <= B"0";
fpga_0_SRAM_Mem_CEN_pin <= pgassign1(0);
fpga_0_SRAM_Mem_OEN_pin <= pgassign2(0);
pgassign3(0) <= fpga_0_PCIe_Bridge_RXN_pin;
pgassign4(0) <= fpga_0_PCIe_Bridge_RXP_pin;
fpga_0_PCIe_Bridge_TXN_pin <= pgassign5(0);
fpga_0_PCIe_Bridge_TXP_pin <= pgassign6(0);
fpga_0_SRAM_Mem_A_pin_vslice_7_30_concat(7 to 30) <= pgassign9(7 to 30);
pgassign10(1) <= PCIe_Bridge_IP2INTC_Irpt;
pgassign10(0) <= xps_central_dma_1_IP2INTC_Irpt;
net_gnd0 <= '0';
net_gnd1(0 downto 0) <= B"0";
net_gnd10(0 to 9) <= B"0000000000";
net_gnd128(0 to 127) <= B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
net_gnd16(0 to 15) <= B"0000000000000000";
net_gnd2(0 to 1) <= B"00";
net_gnd3(2 downto 0) <= B"000";
net_gnd30(29 downto 0) <= B"000000000000000000000000000000";
net_gnd32(0 to 31) <= B"00000000000000000000000000000000";
net_gnd36(0 to 35) <= B"000000000000000000000000000000000000";
net_gnd4(0 to 3) <= B"0000";
net_gnd4096(0 to 4095) <= X"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
net_gnd6(5 downto 0) <= B"000000";
net_gnd64(0 to 63) <= B"0000000000000000000000000000000000000000000000000000000000000000";
net_gnd8(0 to 7) <= B"00000000";
net_vcc0 <= '1';
net_vcc4(0 to 3) <= B"1111";
microblaze_0 : system_microblaze_0_wrapper
port map (
CLK => clk_125_0000MHzPLL0,
RESET => dlmb_LMB_Rst,
MB_RESET => mb_reset,
INTERRUPT => microblaze_0_Interrupt,
INTERRUPT_ADDRESS => net_gnd32,
INTERRUPT_ACK => open,
EXT_BRK => Ext_BRK,
EXT_NM_BRK => Ext_NM_BRK,
DBG_STOP => net_gnd0,
MB_Halted => open,
MB_Error => open,
WAKEUP => net_gnd2,
SLEEP => open,
DBG_WAKEUP => open,
LOCKSTEP_MASTER_OUT => open,
LOCKSTEP_SLAVE_IN => net_gnd4096,
LOCKSTEP_OUT => open,
INSTR => ilmb_LMB_ReadDBus,
IREADY => ilmb_LMB_Ready,
IWAIT => ilmb_LMB_Wait,
ICE => ilmb_LMB_CE,
IUE => ilmb_LMB_UE,
INSTR_ADDR => ilmb_M_ABus,
IFETCH => ilmb_M_ReadStrobe,
I_AS => ilmb_M_AddrStrobe,
IPLB_M_ABort => mb_plb_M_ABort(1),
IPLB_M_ABus => mb_plb_M_ABus(32 to 63),
IPLB_M_UABus => mb_plb_M_UABus(32 to 63),
IPLB_M_BE => mb_plb_M_BE(8 to 15),
IPLB_M_busLock => mb_plb_M_busLock(1),
IPLB_M_lockErr => mb_plb_M_lockErr(1),
IPLB_M_MSize => mb_plb_M_MSize(2 to 3),
IPLB_M_priority => mb_plb_M_priority(2 to 3),
IPLB_M_rdBurst => mb_plb_M_rdBurst(1),
IPLB_M_request => mb_plb_M_request(1),
IPLB_M_RNW => mb_plb_M_RNW(1),
IPLB_M_size => mb_plb_M_size(4 to 7),
IPLB_M_TAttribute => mb_plb_M_TAttribute(16 to 31),
IPLB_M_type => mb_plb_M_type(3 to 5),
IPLB_M_wrBurst => mb_plb_M_wrBurst(1),
IPLB_M_wrDBus => mb_plb_M_wrDBus(64 to 127),
IPLB_MBusy => mb_plb_PLB_MBusy(1),
IPLB_MRdErr => mb_plb_PLB_MRdErr(1),
IPLB_MWrErr => mb_plb_PLB_MWrErr(1),
IPLB_MIRQ => mb_plb_PLB_MIRQ(1),
IPLB_MWrBTerm => mb_plb_PLB_MWrBTerm(1),
IPLB_MWrDAck => mb_plb_PLB_MWrDAck(1),
IPLB_MAddrAck => mb_plb_PLB_MAddrAck(1),
IPLB_MRdBTerm => mb_plb_PLB_MRdBTerm(1),
IPLB_MRdDAck => mb_plb_PLB_MRdDAck(1),
IPLB_MRdDBus => mb_plb_PLB_MRdDBus(64 to 127),
IPLB_MRdWdAddr => mb_plb_PLB_MRdWdAddr(4 to 7),
IPLB_MRearbitrate => mb_plb_PLB_MRearbitrate(1),
IPLB_MSSize => mb_plb_PLB_MSSize(2 to 3),
IPLB_MTimeout => mb_plb_PLB_MTimeout(1),
DATA_READ => dlmb_LMB_ReadDBus,
DREADY => dlmb_LMB_Ready,
DWAIT => dlmb_LMB_Wait,
DCE => dlmb_LMB_CE,
DUE => dlmb_LMB_UE,
DATA_WRITE => dlmb_M_DBus,
DATA_ADDR => dlmb_M_ABus,
D_AS => dlmb_M_AddrStrobe,
READ_STROBE => dlmb_M_ReadStrobe,
WRITE_STROBE => dlmb_M_WriteStrobe,
BYTE_ENABLE => dlmb_M_BE,
DPLB_M_ABort => mb_plb_M_ABort(0),
DPLB_M_ABus => mb_plb_M_ABus(0 to 31),
DPLB_M_UABus => mb_plb_M_UABus(0 to 31),
DPLB_M_BE => mb_plb_M_BE(0 to 7),
DPLB_M_busLock => mb_plb_M_busLock(0),
DPLB_M_lockErr => mb_plb_M_lockErr(0),
DPLB_M_MSize => mb_plb_M_MSize(0 to 1),
DPLB_M_priority => mb_plb_M_priority(0 to 1),
DPLB_M_rdBurst => mb_plb_M_rdBurst(0),
DPLB_M_request => mb_plb_M_request(0),
DPLB_M_RNW => mb_plb_M_RNW(0),
DPLB_M_size => mb_plb_M_size(0 to 3),
DPLB_M_TAttribute => mb_plb_M_TAttribute(0 to 15),
DPLB_M_type => mb_plb_M_type(0 to 2),
DPLB_M_wrBurst => mb_plb_M_wrBurst(0),
DPLB_M_wrDBus => mb_plb_M_wrDBus(0 to 63),
DPLB_MBusy => mb_plb_PLB_MBusy(0),
DPLB_MRdErr => mb_plb_PLB_MRdErr(0),
DPLB_MWrErr => mb_plb_PLB_MWrErr(0),
DPLB_MIRQ => mb_plb_PLB_MIRQ(0),
DPLB_MWrBTerm => mb_plb_PLB_MWrBTerm(0),
DPLB_MWrDAck => mb_plb_PLB_MWrDAck(0),
DPLB_MAddrAck => mb_plb_PLB_MAddrAck(0),
DPLB_MRdBTerm => mb_plb_PLB_MRdBTerm(0),
DPLB_MRdDAck => mb_plb_PLB_MRdDAck(0),
DPLB_MRdDBus => mb_plb_PLB_MRdDBus(0 to 63),
DPLB_MRdWdAddr => mb_plb_PLB_MRdWdAddr(0 to 3),
DPLB_MRearbitrate => mb_plb_PLB_MRearbitrate(0),
DPLB_MSSize => mb_plb_PLB_MSSize(0 to 1),
DPLB_MTimeout => mb_plb_PLB_MTimeout(0),
M_AXI_IP_AWID => open,
M_AXI_IP_AWADDR => open,
M_AXI_IP_AWLEN => open,
M_AXI_IP_AWSIZE => open,
M_AXI_IP_AWBURST => open,
M_AXI_IP_AWLOCK => open,
M_AXI_IP_AWCACHE => open,
M_AXI_IP_AWPROT => open,
M_AXI_IP_AWQOS => open,
M_AXI_IP_AWVALID => open,
M_AXI_IP_AWREADY => net_gnd0,
M_AXI_IP_WDATA => open,
M_AXI_IP_WSTRB => open,
M_AXI_IP_WLAST => open,
M_AXI_IP_WVALID => open,
M_AXI_IP_WREADY => net_gnd0,
M_AXI_IP_BID => net_gnd1(0 downto 0),
M_AXI_IP_BRESP => net_gnd2(0 to 1),
M_AXI_IP_BVALID => net_gnd0,
M_AXI_IP_BREADY => open,
M_AXI_IP_ARID => open,
M_AXI_IP_ARADDR => open,
M_AXI_IP_ARLEN => open,
M_AXI_IP_ARSIZE => open,
M_AXI_IP_ARBURST => open,
M_AXI_IP_ARLOCK => open,
M_AXI_IP_ARCACHE => open,
M_AXI_IP_ARPROT => open,
M_AXI_IP_ARQOS => open,
M_AXI_IP_ARVALID => open,
M_AXI_IP_ARREADY => net_gnd0,
M_AXI_IP_RID => net_gnd1(0 downto 0),
M_AXI_IP_RDATA => net_gnd32(0 to 31),
M_AXI_IP_RRESP => net_gnd2(0 to 1),
M_AXI_IP_RLAST => net_gnd0,
M_AXI_IP_RVALID => net_gnd0,
M_AXI_IP_RREADY => open,
M_AXI_DP_AWID => open,
M_AXI_DP_AWADDR => open,
M_AXI_DP_AWLEN => open,
M_AXI_DP_AWSIZE => open,
M_AXI_DP_AWBURST => open,
M_AXI_DP_AWLOCK => open,
M_AXI_DP_AWCACHE => open,
M_AXI_DP_AWPROT => open,
M_AXI_DP_AWQOS => open,
M_AXI_DP_AWVALID => open,
M_AXI_DP_AWREADY => net_gnd0,
M_AXI_DP_WDATA => open,
M_AXI_DP_WSTRB => open,
M_AXI_DP_WLAST => open,
M_AXI_DP_WVALID => open,
M_AXI_DP_WREADY => net_gnd0,
M_AXI_DP_BID => net_gnd1(0 downto 0),
M_AXI_DP_BRESP => net_gnd2(0 to 1),
M_AXI_DP_BVALID => net_gnd0,
M_AXI_DP_BREADY => open,
M_AXI_DP_ARID => open,
M_AXI_DP_ARADDR => open,
M_AXI_DP_ARLEN => open,
M_AXI_DP_ARSIZE => open,
M_AXI_DP_ARBURST => open,
M_AXI_DP_ARLOCK => open,
M_AXI_DP_ARCACHE => open,
M_AXI_DP_ARPROT => open,
M_AXI_DP_ARQOS => open,
M_AXI_DP_ARVALID => open,
M_AXI_DP_ARREADY => net_gnd0,
M_AXI_DP_RID => net_gnd1(0 downto 0),
M_AXI_DP_RDATA => net_gnd32(0 to 31),
M_AXI_DP_RRESP => net_gnd2(0 to 1),
M_AXI_DP_RLAST => net_gnd0,
M_AXI_DP_RVALID => net_gnd0,
M_AXI_DP_RREADY => open,
M_AXI_IC_AWID => open,
M_AXI_IC_AWADDR => open,
M_AXI_IC_AWLEN => open,
M_AXI_IC_AWSIZE => open,
M_AXI_IC_AWBURST => open,
M_AXI_IC_AWLOCK => open,
M_AXI_IC_AWCACHE => open,
M_AXI_IC_AWPROT => open,
M_AXI_IC_AWQOS => open,
M_AXI_IC_AWVALID => open,
M_AXI_IC_AWREADY => net_gnd0,
M_AXI_IC_AWUSER => open,
M_AXI_IC_AWDOMAIN => open,
M_AXI_IC_AWSNOOP => open,
M_AXI_IC_AWBAR => open,
M_AXI_IC_WDATA => open,
M_AXI_IC_WSTRB => open,
M_AXI_IC_WLAST => open,
M_AXI_IC_WVALID => open,
M_AXI_IC_WREADY => net_gnd0,
M_AXI_IC_WUSER => open,
M_AXI_IC_BID => net_gnd1(0 downto 0),
M_AXI_IC_BRESP => net_gnd2(0 to 1),
M_AXI_IC_BVALID => net_gnd0,
M_AXI_IC_BREADY => open,
M_AXI_IC_BUSER => net_gnd1(0 downto 0),
M_AXI_IC_WACK => open,
M_AXI_IC_ARID => open,
M_AXI_IC_ARADDR => open,
M_AXI_IC_ARLEN => open,
M_AXI_IC_ARSIZE => open,
M_AXI_IC_ARBURST => open,
M_AXI_IC_ARLOCK => open,
M_AXI_IC_ARCACHE => open,
M_AXI_IC_ARPROT => open,
M_AXI_IC_ARQOS => open,
M_AXI_IC_ARVALID => open,
M_AXI_IC_ARREADY => net_gnd0,
M_AXI_IC_ARUSER => open,
M_AXI_IC_ARDOMAIN => open,
M_AXI_IC_ARSNOOP => open,
M_AXI_IC_ARBAR => open,
M_AXI_IC_RID => net_gnd1(0 downto 0),
M_AXI_IC_RDATA => net_gnd32(0 to 31),
M_AXI_IC_RRESP => net_gnd2(0 to 1),
M_AXI_IC_RLAST => net_gnd0,
M_AXI_IC_RVALID => net_gnd0,
M_AXI_IC_RREADY => open,
M_AXI_IC_RUSER => net_gnd1(0 downto 0),
M_AXI_IC_RACK => open,
M_AXI_IC_ACVALID => net_gnd0,
M_AXI_IC_ACADDR => net_gnd32(0 to 31),
M_AXI_IC_ACSNOOP => net_gnd4(0 to 3),
M_AXI_IC_ACPROT => net_gnd3,
M_AXI_IC_ACREADY => open,
M_AXI_IC_CRREADY => net_gnd0,
M_AXI_IC_CRVALID => open,
M_AXI_IC_CRRESP => open,
M_AXI_IC_CDVALID => open,
M_AXI_IC_CDREADY => net_gnd0,
M_AXI_IC_CDDATA => open,
M_AXI_IC_CDLAST => open,
M_AXI_DC_AWID => open,
M_AXI_DC_AWADDR => open,
M_AXI_DC_AWLEN => open,
M_AXI_DC_AWSIZE => open,
M_AXI_DC_AWBURST => open,
M_AXI_DC_AWLOCK => open,
M_AXI_DC_AWCACHE => open,
M_AXI_DC_AWPROT => open,
M_AXI_DC_AWQOS => open,
M_AXI_DC_AWVALID => open,
M_AXI_DC_AWREADY => net_gnd0,
M_AXI_DC_AWUSER => open,
M_AXI_DC_AWDOMAIN => open,
M_AXI_DC_AWSNOOP => open,
M_AXI_DC_AWBAR => open,
M_AXI_DC_WDATA => open,
M_AXI_DC_WSTRB => open,
M_AXI_DC_WLAST => open,
M_AXI_DC_WVALID => open,
M_AXI_DC_WREADY => net_gnd0,
M_AXI_DC_WUSER => open,
M_AXI_DC_BID => net_gnd1(0 downto 0),
M_AXI_DC_BRESP => net_gnd2(0 to 1),
M_AXI_DC_BVALID => net_gnd0,
M_AXI_DC_BREADY => open,
M_AXI_DC_BUSER => net_gnd1(0 downto 0),
M_AXI_DC_WACK => open,
M_AXI_DC_ARID => open,
M_AXI_DC_ARADDR => open,
M_AXI_DC_ARLEN => open,
M_AXI_DC_ARSIZE => open,
M_AXI_DC_ARBURST => open,
M_AXI_DC_ARLOCK => open,
M_AXI_DC_ARCACHE => open,
M_AXI_DC_ARPROT => open,
M_AXI_DC_ARQOS => open,
M_AXI_DC_ARVALID => open,
M_AXI_DC_ARREADY => net_gnd0,
M_AXI_DC_ARUSER => open,
M_AXI_DC_ARDOMAIN => open,
M_AXI_DC_ARSNOOP => open,
M_AXI_DC_ARBAR => open,
M_AXI_DC_RID => net_gnd1(0 downto 0),
M_AXI_DC_RDATA => net_gnd32(0 to 31),
M_AXI_DC_RRESP => net_gnd2(0 to 1),
M_AXI_DC_RLAST => net_gnd0,
M_AXI_DC_RVALID => net_gnd0,
M_AXI_DC_RREADY => open,
M_AXI_DC_RUSER => net_gnd1(0 downto 0),
M_AXI_DC_RACK => open,
M_AXI_DC_ACVALID => net_gnd0,
M_AXI_DC_ACADDR => net_gnd32(0 to 31),
M_AXI_DC_ACSNOOP => net_gnd4(0 to 3),
M_AXI_DC_ACPROT => net_gnd3,
M_AXI_DC_ACREADY => open,
M_AXI_DC_CRREADY => net_gnd0,
M_AXI_DC_CRVALID => open,
M_AXI_DC_CRRESP => open,
M_AXI_DC_CDVALID => open,
M_AXI_DC_CDREADY => net_gnd0,
M_AXI_DC_CDDATA => open,
M_AXI_DC_CDLAST => open,
DBG_CLK => microblaze_0_mdm_bus_Dbg_Clk,
DBG_TDI => microblaze_0_mdm_bus_Dbg_TDI,
DBG_TDO => microblaze_0_mdm_bus_Dbg_TDO,
DBG_REG_EN => microblaze_0_mdm_bus_Dbg_Reg_En,
DBG_SHIFT => microblaze_0_mdm_bus_Dbg_Shift,
DBG_CAPTURE => microblaze_0_mdm_bus_Dbg_Capture,
DBG_UPDATE => microblaze_0_mdm_bus_Dbg_Update,
DEBUG_RST => microblaze_0_mdm_bus_Debug_Rst,
Trace_Instruction => open,
Trace_Valid_Instr => open,
Trace_PC => open,
Trace_Reg_Write => open,
Trace_Reg_Addr => open,
Trace_MSR_Reg => open,
Trace_PID_Reg => open,
Trace_New_Reg_Value => open,
Trace_Exception_Taken => open,
Trace_Exception_Kind => open,
Trace_Jump_Taken => open,
Trace_Delay_Slot => open,
Trace_Data_Address => open,
Trace_Data_Access => open,
Trace_Data_Read => open,
Trace_Data_Write => open,
Trace_Data_Write_Value => open,
Trace_Data_Byte_Enable => open,
Trace_DCache_Req => open,
Trace_DCache_Hit => open,
Trace_DCache_Rdy => open,
Trace_DCache_Read => open,
Trace_ICache_Req => open,
Trace_ICache_Hit => open,
Trace_ICache_Rdy => open,
Trace_OF_PipeRun => open,
Trace_EX_PipeRun => open,
Trace_MEM_PipeRun => open,
Trace_MB_Halted => open,
Trace_Jump_Hit => open,
FSL0_S_CLK => open,
FSL0_S_READ => open,
FSL0_S_DATA => net_gnd32,
FSL0_S_CONTROL => net_gnd0,
FSL0_S_EXISTS => net_gnd0,
FSL0_M_CLK => open,
FSL0_M_WRITE => open,
FSL0_M_DATA => open,
FSL0_M_CONTROL => open,
FSL0_M_FULL => net_gnd0,
FSL1_S_CLK => open,
FSL1_S_READ => open,
FSL1_S_DATA => net_gnd32,
FSL1_S_CONTROL => net_gnd0,
FSL1_S_EXISTS => net_gnd0,
FSL1_M_CLK => open,
FSL1_M_WRITE => open,
FSL1_M_DATA => open,
FSL1_M_CONTROL => open,
FSL1_M_FULL => net_gnd0,
FSL2_S_CLK => open,
FSL2_S_READ => open,
FSL2_S_DATA => net_gnd32,
FSL2_S_CONTROL => net_gnd0,
FSL2_S_EXISTS => net_gnd0,
FSL2_M_CLK => open,
FSL2_M_WRITE => open,
FSL2_M_DATA => open,
FSL2_M_CONTROL => open,
FSL2_M_FULL => net_gnd0,
FSL3_S_CLK => open,
FSL3_S_READ => open,
FSL3_S_DATA => net_gnd32,
FSL3_S_CONTROL => net_gnd0,
FSL3_S_EXISTS => net_gnd0,
FSL3_M_CLK => open,
FSL3_M_WRITE => open,
FSL3_M_DATA => open,
FSL3_M_CONTROL => open,
FSL3_M_FULL => net_gnd0,
FSL4_S_CLK => open,
FSL4_S_READ => open,
FSL4_S_DATA => net_gnd32,
FSL4_S_CONTROL => net_gnd0,
FSL4_S_EXISTS => net_gnd0,
FSL4_M_CLK => open,
FSL4_M_WRITE => open,
FSL4_M_DATA => open,
FSL4_M_CONTROL => open,
FSL4_M_FULL => net_gnd0,
FSL5_S_CLK => open,
FSL5_S_READ => open,
FSL5_S_DATA => net_gnd32,
FSL5_S_CONTROL => net_gnd0,
FSL5_S_EXISTS => net_gnd0,
FSL5_M_CLK => open,
FSL5_M_WRITE => open,
FSL5_M_DATA => open,
FSL5_M_CONTROL => open,
FSL5_M_FULL => net_gnd0,
FSL6_S_CLK => open,
FSL6_S_READ => open,
FSL6_S_DATA => net_gnd32,
FSL6_S_CONTROL => net_gnd0,
FSL6_S_EXISTS => net_gnd0,
FSL6_M_CLK => open,
FSL6_M_WRITE => open,
FSL6_M_DATA => open,
FSL6_M_CONTROL => open,
FSL6_M_FULL => net_gnd0,
FSL7_S_CLK => open,
FSL7_S_READ => open,
FSL7_S_DATA => net_gnd32,
FSL7_S_CONTROL => net_gnd0,
FSL7_S_EXISTS => net_gnd0,
FSL7_M_CLK => open,
FSL7_M_WRITE => open,
FSL7_M_DATA => open,
FSL7_M_CONTROL => open,
FSL7_M_FULL => net_gnd0,
FSL8_S_CLK => open,
FSL8_S_READ => open,
FSL8_S_DATA => net_gnd32,
FSL8_S_CONTROL => net_gnd0,
FSL8_S_EXISTS => net_gnd0,
FSL8_M_CLK => open,
FSL8_M_WRITE => open,
FSL8_M_DATA => open,
FSL8_M_CONTROL => open,
FSL8_M_FULL => net_gnd0,
FSL9_S_CLK => open,
FSL9_S_READ => open,
FSL9_S_DATA => net_gnd32,
FSL9_S_CONTROL => net_gnd0,
FSL9_S_EXISTS => net_gnd0,
FSL9_M_CLK => open,
FSL9_M_WRITE => open,
FSL9_M_DATA => open,
FSL9_M_CONTROL => open,
FSL9_M_FULL => net_gnd0,
FSL10_S_CLK => open,
FSL10_S_READ => open,
FSL10_S_DATA => net_gnd32,
FSL10_S_CONTROL => net_gnd0,
FSL10_S_EXISTS => net_gnd0,
FSL10_M_CLK => open,
FSL10_M_WRITE => open,
FSL10_M_DATA => open,
FSL10_M_CONTROL => open,
FSL10_M_FULL => net_gnd0,
FSL11_S_CLK => open,
FSL11_S_READ => open,
FSL11_S_DATA => net_gnd32,
FSL11_S_CONTROL => net_gnd0,
FSL11_S_EXISTS => net_gnd0,
FSL11_M_CLK => open,
FSL11_M_WRITE => open,
FSL11_M_DATA => open,
FSL11_M_CONTROL => open,
FSL11_M_FULL => net_gnd0,
FSL12_S_CLK => open,
FSL12_S_READ => open,
FSL12_S_DATA => net_gnd32,
FSL12_S_CONTROL => net_gnd0,
FSL12_S_EXISTS => net_gnd0,
FSL12_M_CLK => open,
FSL12_M_WRITE => open,
FSL12_M_DATA => open,
FSL12_M_CONTROL => open,
FSL12_M_FULL => net_gnd0,
FSL13_S_CLK => open,
FSL13_S_READ => open,
FSL13_S_DATA => net_gnd32,
FSL13_S_CONTROL => net_gnd0,
FSL13_S_EXISTS => net_gnd0,
FSL13_M_CLK => open,
FSL13_M_WRITE => open,
FSL13_M_DATA => open,
FSL13_M_CONTROL => open,
FSL13_M_FULL => net_gnd0,
FSL14_S_CLK => open,
FSL14_S_READ => open,
FSL14_S_DATA => net_gnd32,
FSL14_S_CONTROL => net_gnd0,
FSL14_S_EXISTS => net_gnd0,
FSL14_M_CLK => open,
FSL14_M_WRITE => open,
FSL14_M_DATA => open,
FSL14_M_CONTROL => open,
FSL14_M_FULL => net_gnd0,
FSL15_S_CLK => open,
FSL15_S_READ => open,
FSL15_S_DATA => net_gnd32,
FSL15_S_CONTROL => net_gnd0,
FSL15_S_EXISTS => net_gnd0,
FSL15_M_CLK => open,
FSL15_M_WRITE => open,
FSL15_M_DATA => open,
FSL15_M_CONTROL => open,
FSL15_M_FULL => net_gnd0,
M0_AXIS_TLAST => open,
M0_AXIS_TDATA => open,
M0_AXIS_TVALID => open,
M0_AXIS_TREADY => net_gnd0,
S0_AXIS_TLAST => net_gnd0,
S0_AXIS_TDATA => net_gnd32(0 to 31),
S0_AXIS_TVALID => net_gnd0,
S0_AXIS_TREADY => open,
M1_AXIS_TLAST => open,
M1_AXIS_TDATA => open,
M1_AXIS_TVALID => open,
M1_AXIS_TREADY => net_gnd0,
S1_AXIS_TLAST => net_gnd0,
S1_AXIS_TDATA => net_gnd32(0 to 31),
S1_AXIS_TVALID => net_gnd0,
S1_AXIS_TREADY => open,
M2_AXIS_TLAST => open,
M2_AXIS_TDATA => open,
M2_AXIS_TVALID => open,
M2_AXIS_TREADY => net_gnd0,
S2_AXIS_TLAST => net_gnd0,
S2_AXIS_TDATA => net_gnd32(0 to 31),
S2_AXIS_TVALID => net_gnd0,
S2_AXIS_TREADY => open,
M3_AXIS_TLAST => open,
M3_AXIS_TDATA => open,
M3_AXIS_TVALID => open,
M3_AXIS_TREADY => net_gnd0,
S3_AXIS_TLAST => net_gnd0,
S3_AXIS_TDATA => net_gnd32(0 to 31),
S3_AXIS_TVALID => net_gnd0,
S3_AXIS_TREADY => open,
M4_AXIS_TLAST => open,
M4_AXIS_TDATA => open,
M4_AXIS_TVALID => open,
M4_AXIS_TREADY => net_gnd0,
S4_AXIS_TLAST => net_gnd0,
S4_AXIS_TDATA => net_gnd32(0 to 31),
S4_AXIS_TVALID => net_gnd0,
S4_AXIS_TREADY => open,
M5_AXIS_TLAST => open,
M5_AXIS_TDATA => open,
M5_AXIS_TVALID => open,
M5_AXIS_TREADY => net_gnd0,
S5_AXIS_TLAST => net_gnd0,
S5_AXIS_TDATA => net_gnd32(0 to 31),
S5_AXIS_TVALID => net_gnd0,
S5_AXIS_TREADY => open,
M6_AXIS_TLAST => open,
M6_AXIS_TDATA => open,
M6_AXIS_TVALID => open,
M6_AXIS_TREADY => net_gnd0,
S6_AXIS_TLAST => net_gnd0,
S6_AXIS_TDATA => net_gnd32(0 to 31),
S6_AXIS_TVALID => net_gnd0,
S6_AXIS_TREADY => open,
M7_AXIS_TLAST => open,
M7_AXIS_TDATA => open,
M7_AXIS_TVALID => open,
M7_AXIS_TREADY => net_gnd0,
S7_AXIS_TLAST => net_gnd0,
S7_AXIS_TDATA => net_gnd32(0 to 31),
S7_AXIS_TVALID => net_gnd0,
S7_AXIS_TREADY => open,
M8_AXIS_TLAST => open,
M8_AXIS_TDATA => open,
M8_AXIS_TVALID => open,
M8_AXIS_TREADY => net_gnd0,
S8_AXIS_TLAST => net_gnd0,
S8_AXIS_TDATA => net_gnd32(0 to 31),
S8_AXIS_TVALID => net_gnd0,
S8_AXIS_TREADY => open,
M9_AXIS_TLAST => open,
M9_AXIS_TDATA => open,
M9_AXIS_TVALID => open,
M9_AXIS_TREADY => net_gnd0,
S9_AXIS_TLAST => net_gnd0,
S9_AXIS_TDATA => net_gnd32(0 to 31),
S9_AXIS_TVALID => net_gnd0,
S9_AXIS_TREADY => open,
M10_AXIS_TLAST => open,
M10_AXIS_TDATA => open,
M10_AXIS_TVALID => open,
M10_AXIS_TREADY => net_gnd0,
S10_AXIS_TLAST => net_gnd0,
S10_AXIS_TDATA => net_gnd32(0 to 31),
S10_AXIS_TVALID => net_gnd0,
S10_AXIS_TREADY => open,
M11_AXIS_TLAST => open,
M11_AXIS_TDATA => open,
M11_AXIS_TVALID => open,
M11_AXIS_TREADY => net_gnd0,
S11_AXIS_TLAST => net_gnd0,
S11_AXIS_TDATA => net_gnd32(0 to 31),
S11_AXIS_TVALID => net_gnd0,
S11_AXIS_TREADY => open,
M12_AXIS_TLAST => open,
M12_AXIS_TDATA => open,
M12_AXIS_TVALID => open,
M12_AXIS_TREADY => net_gnd0,
S12_AXIS_TLAST => net_gnd0,
S12_AXIS_TDATA => net_gnd32(0 to 31),
S12_AXIS_TVALID => net_gnd0,
S12_AXIS_TREADY => open,
M13_AXIS_TLAST => open,
M13_AXIS_TDATA => open,
M13_AXIS_TVALID => open,
M13_AXIS_TREADY => net_gnd0,
S13_AXIS_TLAST => net_gnd0,
S13_AXIS_TDATA => net_gnd32(0 to 31),
S13_AXIS_TVALID => net_gnd0,
S13_AXIS_TREADY => open,
M14_AXIS_TLAST => open,
M14_AXIS_TDATA => open,
M14_AXIS_TVALID => open,
M14_AXIS_TREADY => net_gnd0,
S14_AXIS_TLAST => net_gnd0,
S14_AXIS_TDATA => net_gnd32(0 to 31),
S14_AXIS_TVALID => net_gnd0,
S14_AXIS_TREADY => open,
M15_AXIS_TLAST => open,
M15_AXIS_TDATA => open,
M15_AXIS_TVALID => open,
M15_AXIS_TREADY => net_gnd0,
S15_AXIS_TLAST => net_gnd0,
S15_AXIS_TDATA => net_gnd32(0 to 31),
S15_AXIS_TVALID => net_gnd0,
S15_AXIS_TREADY => open,
ICACHE_FSL_IN_CLK => open,
ICACHE_FSL_IN_READ => open,
ICACHE_FSL_IN_DATA => net_gnd32,
ICACHE_FSL_IN_CONTROL => net_gnd0,
ICACHE_FSL_IN_EXISTS => net_gnd0,
ICACHE_FSL_OUT_CLK => open,
ICACHE_FSL_OUT_WRITE => open,
ICACHE_FSL_OUT_DATA => open,
ICACHE_FSL_OUT_CONTROL => open,
ICACHE_FSL_OUT_FULL => net_gnd0,
DCACHE_FSL_IN_CLK => open,
DCACHE_FSL_IN_READ => open,
DCACHE_FSL_IN_DATA => net_gnd32,
DCACHE_FSL_IN_CONTROL => net_gnd0,
DCACHE_FSL_IN_EXISTS => net_gnd0,
DCACHE_FSL_OUT_CLK => open,
DCACHE_FSL_OUT_WRITE => open,
DCACHE_FSL_OUT_DATA => open,
DCACHE_FSL_OUT_CONTROL => open,
DCACHE_FSL_OUT_FULL => net_gnd0
);
mb_plb : system_mb_plb_wrapper
port map (
PLB_Clk => clk_125_0000MHzPLL0,
SYS_Rst => sys_bus_reset(0),
PLB_Rst => open,
SPLB_Rst => mb_plb_SPLB_Rst,
MPLB_Rst => mb_plb_MPLB_Rst,
PLB_dcrAck => open,
PLB_dcrDBus => open,
DCR_ABus => net_gnd10,
DCR_DBus => net_gnd32,
DCR_Read => net_gnd0,
DCR_Write => net_gnd0,
M_ABus => mb_plb_M_ABus,
M_UABus => mb_plb_M_UABus,
M_BE => mb_plb_M_BE,
M_RNW => mb_plb_M_RNW,
M_abort => mb_plb_M_ABort,
M_busLock => mb_plb_M_busLock,
M_TAttribute => mb_plb_M_TAttribute,
M_lockErr => mb_plb_M_lockErr,
M_MSize => mb_plb_M_MSize,
M_priority => mb_plb_M_priority,
M_rdBurst => mb_plb_M_rdBurst,
M_request => mb_plb_M_request,
M_size => mb_plb_M_size,
M_type => mb_plb_M_type,
M_wrBurst => mb_plb_M_wrBurst,
M_wrDBus => mb_plb_M_wrDBus,
Sl_addrAck => mb_plb_Sl_addrAck,
Sl_MRdErr => mb_plb_Sl_MRdErr,
Sl_MWrErr => mb_plb_Sl_MWrErr,
Sl_MBusy => mb_plb_Sl_MBusy,
Sl_rdBTerm => mb_plb_Sl_rdBTerm,
Sl_rdComp => mb_plb_Sl_rdComp,
Sl_rdDAck => mb_plb_Sl_rdDAck,
Sl_rdDBus => mb_plb_Sl_rdDBus,
Sl_rdWdAddr => mb_plb_Sl_rdWdAddr,
Sl_rearbitrate => mb_plb_Sl_rearbitrate,
Sl_SSize => mb_plb_Sl_SSize,
Sl_wait => mb_plb_Sl_wait,
Sl_wrBTerm => mb_plb_Sl_wrBTerm,
Sl_wrComp => mb_plb_Sl_wrComp,
Sl_wrDAck => mb_plb_Sl_wrDAck,
Sl_MIRQ => mb_plb_Sl_MIRQ,
PLB_MIRQ => mb_plb_PLB_MIRQ,
PLB_ABus => mb_plb_PLB_ABus,
PLB_UABus => mb_plb_PLB_UABus,
PLB_BE => mb_plb_PLB_BE,
PLB_MAddrAck => mb_plb_PLB_MAddrAck,
PLB_MTimeout => mb_plb_PLB_MTimeout,
PLB_MBusy => mb_plb_PLB_MBusy,
PLB_MRdErr => mb_plb_PLB_MRdErr,
PLB_MWrErr => mb_plb_PLB_MWrErr,
PLB_MRdBTerm => mb_plb_PLB_MRdBTerm,
PLB_MRdDAck => mb_plb_PLB_MRdDAck,
PLB_MRdDBus => mb_plb_PLB_MRdDBus,
PLB_MRdWdAddr => mb_plb_PLB_MRdWdAddr,
PLB_MRearbitrate => mb_plb_PLB_MRearbitrate,
PLB_MWrBTerm => mb_plb_PLB_MWrBTerm,
PLB_MWrDAck => mb_plb_PLB_MWrDAck,
PLB_MSSize => mb_plb_PLB_MSSize,
PLB_PAValid => mb_plb_PLB_PAValid,
PLB_RNW => mb_plb_PLB_RNW,
PLB_SAValid => mb_plb_PLB_SAValid,
PLB_abort => mb_plb_PLB_abort,
PLB_busLock => mb_plb_PLB_busLock,
PLB_TAttribute => mb_plb_PLB_TAttribute,
PLB_lockErr => mb_plb_PLB_lockErr,
PLB_masterID => mb_plb_PLB_masterID,
PLB_MSize => mb_plb_PLB_MSize,
PLB_rdPendPri => mb_plb_PLB_rdPendPri,
PLB_wrPendPri => mb_plb_PLB_wrPendPri,
PLB_rdPendReq => mb_plb_PLB_rdPendReq,
PLB_wrPendReq => mb_plb_PLB_wrPendReq,
PLB_rdBurst => mb_plb_PLB_rdBurst,
PLB_rdPrim => mb_plb_PLB_rdPrim,
PLB_reqPri => mb_plb_PLB_reqPri,
PLB_size => mb_plb_PLB_size,
PLB_type => mb_plb_PLB_type,
PLB_wrBurst => mb_plb_PLB_wrBurst,
PLB_wrDBus => mb_plb_PLB_wrDBus,
PLB_wrPrim => mb_plb_PLB_wrPrim,
PLB_SaddrAck => open,
PLB_SMRdErr => open,
PLB_SMWrErr => open,
PLB_SMBusy => open,
PLB_SrdBTerm => open,
PLB_SrdComp => open,
PLB_SrdDAck => open,
PLB_SrdDBus => open,
PLB_SrdWdAddr => open,
PLB_Srearbitrate => open,
PLB_Sssize => open,
PLB_Swait => open,
PLB_SwrBTerm => open,
PLB_SwrComp => open,
PLB_SwrDAck => open,
Bus_Error_Det => open
);
ilmb : system_ilmb_wrapper
port map (
LMB_Clk => clk_125_0000MHzPLL0,
SYS_Rst => sys_bus_reset(0),
LMB_Rst => ilmb_LMB_Rst,
M_ABus => ilmb_M_ABus,
M_ReadStrobe => ilmb_M_ReadStrobe,
M_WriteStrobe => net_gnd0,
M_AddrStrobe => ilmb_M_AddrStrobe,
M_DBus => net_gnd32,
M_BE => net_gnd4,
Sl_DBus => ilmb_Sl_DBus,
Sl_Ready => ilmb_Sl_Ready(0 to 0),
Sl_Wait => ilmb_Sl_Wait(0 to 0),
Sl_UE => ilmb_Sl_UE(0 to 0),
Sl_CE => ilmb_Sl_CE(0 to 0),
LMB_ABus => ilmb_LMB_ABus,
LMB_ReadStrobe => ilmb_LMB_ReadStrobe,
LMB_WriteStrobe => ilmb_LMB_WriteStrobe,
LMB_AddrStrobe => ilmb_LMB_AddrStrobe,
LMB_ReadDBus => ilmb_LMB_ReadDBus,
LMB_WriteDBus => ilmb_LMB_WriteDBus,
LMB_Ready => ilmb_LMB_Ready,
LMB_Wait => ilmb_LMB_Wait,
LMB_UE => ilmb_LMB_UE,
LMB_CE => ilmb_LMB_CE,
LMB_BE => ilmb_LMB_BE
);
dlmb : system_dlmb_wrapper
port map (
LMB_Clk => clk_125_0000MHzPLL0,
SYS_Rst => sys_bus_reset(0),
LMB_Rst => dlmb_LMB_Rst,
M_ABus => dlmb_M_ABus,
M_ReadStrobe => dlmb_M_ReadStrobe,
M_WriteStrobe => dlmb_M_WriteStrobe,
M_AddrStrobe => dlmb_M_AddrStrobe,
M_DBus => dlmb_M_DBus,
M_BE => dlmb_M_BE,
Sl_DBus => dlmb_Sl_DBus,
Sl_Ready => dlmb_Sl_Ready(0 to 0),
Sl_Wait => dlmb_Sl_Wait(0 to 0),
Sl_UE => dlmb_Sl_UE(0 to 0),
Sl_CE => dlmb_Sl_CE(0 to 0),
LMB_ABus => dlmb_LMB_ABus,
LMB_ReadStrobe => dlmb_LMB_ReadStrobe,
LMB_WriteStrobe => dlmb_LMB_WriteStrobe,
LMB_AddrStrobe => dlmb_LMB_AddrStrobe,
LMB_ReadDBus => dlmb_LMB_ReadDBus,
LMB_WriteDBus => dlmb_LMB_WriteDBus,
LMB_Ready => dlmb_LMB_Ready,
LMB_Wait => dlmb_LMB_Wait,
LMB_UE => dlmb_LMB_UE,
LMB_CE => dlmb_LMB_CE,
LMB_BE => dlmb_LMB_BE
);
dlmb_cntlr : system_dlmb_cntlr_wrapper
port map (
LMB_Clk => clk_125_0000MHzPLL0,
LMB_Rst => dlmb_LMB_Rst,
LMB_ABus => dlmb_LMB_ABus,
LMB_WriteDBus => dlmb_LMB_WriteDBus,
LMB_AddrStrobe => dlmb_LMB_AddrStrobe,
LMB_ReadStrobe => dlmb_LMB_ReadStrobe,
LMB_WriteStrobe => dlmb_LMB_WriteStrobe,
LMB_BE => dlmb_LMB_BE,
Sl_DBus => dlmb_Sl_DBus,
Sl_Ready => dlmb_Sl_Ready(0),
Sl_Wait => dlmb_Sl_Wait(0),
Sl_UE => dlmb_Sl_UE(0),
Sl_CE => dlmb_Sl_CE(0),
LMB1_ABus => net_gnd32,
LMB1_WriteDBus => net_gnd32,
LMB1_AddrStrobe => net_gnd0,
LMB1_ReadStrobe => net_gnd0,
LMB1_WriteStrobe => net_gnd0,
LMB1_BE => net_gnd4,
Sl1_DBus => open,
Sl1_Ready => open,
Sl1_Wait => open,
Sl1_UE => open,
Sl1_CE => open,
LMB2_ABus => net_gnd32,
LMB2_WriteDBus => net_gnd32,
LMB2_AddrStrobe => net_gnd0,
LMB2_ReadStrobe => net_gnd0,
LMB2_WriteStrobe => net_gnd0,
LMB2_BE => net_gnd4,
Sl2_DBus => open,
Sl2_Ready => open,
Sl2_Wait => open,
Sl2_UE => open,
Sl2_CE => open,
LMB3_ABus => net_gnd32,
LMB3_WriteDBus => net_gnd32,
LMB3_AddrStrobe => net_gnd0,
LMB3_ReadStrobe => net_gnd0,
LMB3_WriteStrobe => net_gnd0,
LMB3_BE => net_gnd4,
Sl3_DBus => open,
Sl3_Ready => open,
Sl3_Wait => open,
Sl3_UE => open,
Sl3_CE => open,
BRAM_Rst_A => dlmb_port_BRAM_Rst,
BRAM_Clk_A => dlmb_port_BRAM_Clk,
BRAM_EN_A => dlmb_port_BRAM_EN,
BRAM_WEN_A => dlmb_port_BRAM_WEN,
BRAM_Addr_A => dlmb_port_BRAM_Addr,
BRAM_Din_A => dlmb_port_BRAM_Din,
BRAM_Dout_A => dlmb_port_BRAM_Dout,
Interrupt => open,
UE => open,
CE => open,
SPLB_CTRL_PLB_ABus => net_gnd32,
SPLB_CTRL_PLB_PAValid => net_gnd0,
SPLB_CTRL_PLB_masterID => net_gnd1(0 downto 0),
SPLB_CTRL_PLB_RNW => net_gnd0,
SPLB_CTRL_PLB_BE => net_gnd4,
SPLB_CTRL_PLB_size => net_gnd4,
SPLB_CTRL_PLB_type => net_gnd3(2 downto 0),
SPLB_CTRL_PLB_wrDBus => net_gnd32,
SPLB_CTRL_Sl_addrAck => open,
SPLB_CTRL_Sl_SSize => open,
SPLB_CTRL_Sl_wait => open,
SPLB_CTRL_Sl_rearbitrate => open,
SPLB_CTRL_Sl_wrDAck => open,
SPLB_CTRL_Sl_wrComp => open,
SPLB_CTRL_Sl_rdDBus => open,
SPLB_CTRL_Sl_rdDAck => open,
SPLB_CTRL_Sl_rdComp => open,
SPLB_CTRL_Sl_MBusy => open,
SPLB_CTRL_Sl_MWrErr => open,
SPLB_CTRL_Sl_MRdErr => open,
SPLB_CTRL_PLB_UABus => net_gnd32,
SPLB_CTRL_PLB_SAValid => net_gnd0,
SPLB_CTRL_PLB_rdPrim => net_gnd0,
SPLB_CTRL_PLB_wrPrim => net_gnd0,
SPLB_CTRL_PLB_abort => net_gnd0,
SPLB_CTRL_PLB_busLock => net_gnd0,
SPLB_CTRL_PLB_MSize => net_gnd2,
SPLB_CTRL_PLB_lockErr => net_gnd0,
SPLB_CTRL_PLB_wrBurst => net_gnd0,
SPLB_CTRL_PLB_rdBurst => net_gnd0,
SPLB_CTRL_PLB_wrPendReq => net_gnd0,
SPLB_CTRL_PLB_rdPendReq => net_gnd0,
SPLB_CTRL_PLB_wrPendPri => net_gnd2,
SPLB_CTRL_PLB_rdPendPri => net_gnd2,
SPLB_CTRL_PLB_reqPri => net_gnd2,
SPLB_CTRL_PLB_TAttribute => net_gnd16,
SPLB_CTRL_Sl_wrBTerm => open,
SPLB_CTRL_Sl_rdWdAddr => open,
SPLB_CTRL_Sl_rdBTerm => open,
SPLB_CTRL_Sl_MIRQ => open,
S_AXI_CTRL_ACLK => net_vcc0,
S_AXI_CTRL_ARESETN => net_gnd0,
S_AXI_CTRL_AWADDR => net_gnd32(0 to 31),
S_AXI_CTRL_AWVALID => net_gnd0,
S_AXI_CTRL_AWREADY => open,
S_AXI_CTRL_WDATA => net_gnd32(0 to 31),
S_AXI_CTRL_WSTRB => net_gnd4(0 to 3),
S_AXI_CTRL_WVALID => net_gnd0,
S_AXI_CTRL_WREADY => open,
S_AXI_CTRL_BRESP => open,
S_AXI_CTRL_BVALID => open,
S_AXI_CTRL_BREADY => net_gnd0,
S_AXI_CTRL_ARADDR => net_gnd32(0 to 31),
S_AXI_CTRL_ARVALID => net_gnd0,
S_AXI_CTRL_ARREADY => open,
S_AXI_CTRL_RDATA => open,
S_AXI_CTRL_RRESP => open,
S_AXI_CTRL_RVALID => open,
S_AXI_CTRL_RREADY => net_gnd0
);
ilmb_cntlr : system_ilmb_cntlr_wrapper
port map (
LMB_Clk => clk_125_0000MHzPLL0,
LMB_Rst => ilmb_LMB_Rst,
LMB_ABus => ilmb_LMB_ABus,
LMB_WriteDBus => ilmb_LMB_WriteDBus,
LMB_AddrStrobe => ilmb_LMB_AddrStrobe,
LMB_ReadStrobe => ilmb_LMB_ReadStrobe,
LMB_WriteStrobe => ilmb_LMB_WriteStrobe,
LMB_BE => ilmb_LMB_BE,
Sl_DBus => ilmb_Sl_DBus,
Sl_Ready => ilmb_Sl_Ready(0),
Sl_Wait => ilmb_Sl_Wait(0),
Sl_UE => ilmb_Sl_UE(0),
Sl_CE => ilmb_Sl_CE(0),
LMB1_ABus => net_gnd32,
LMB1_WriteDBus => net_gnd32,
LMB1_AddrStrobe => net_gnd0,
LMB1_ReadStrobe => net_gnd0,
LMB1_WriteStrobe => net_gnd0,
LMB1_BE => net_gnd4,
Sl1_DBus => open,
Sl1_Ready => open,
Sl1_Wait => open,
Sl1_UE => open,
Sl1_CE => open,
LMB2_ABus => net_gnd32,
LMB2_WriteDBus => net_gnd32,
LMB2_AddrStrobe => net_gnd0,
LMB2_ReadStrobe => net_gnd0,
LMB2_WriteStrobe => net_gnd0,
LMB2_BE => net_gnd4,
Sl2_DBus => open,
Sl2_Ready => open,
Sl2_Wait => open,
Sl2_UE => open,
Sl2_CE => open,
LMB3_ABus => net_gnd32,
LMB3_WriteDBus => net_gnd32,
LMB3_AddrStrobe => net_gnd0,
LMB3_ReadStrobe => net_gnd0,
LMB3_WriteStrobe => net_gnd0,
LMB3_BE => net_gnd4,
Sl3_DBus => open,
Sl3_Ready => open,
Sl3_Wait => open,
Sl3_UE => open,
Sl3_CE => open,
BRAM_Rst_A => ilmb_port_BRAM_Rst,
BRAM_Clk_A => ilmb_port_BRAM_Clk,
BRAM_EN_A => ilmb_port_BRAM_EN,
BRAM_WEN_A => ilmb_port_BRAM_WEN,
BRAM_Addr_A => ilmb_port_BRAM_Addr,
BRAM_Din_A => ilmb_port_BRAM_Din,
BRAM_Dout_A => ilmb_port_BRAM_Dout,
Interrupt => open,
UE => open,
CE => open,
SPLB_CTRL_PLB_ABus => net_gnd32,
SPLB_CTRL_PLB_PAValid => net_gnd0,
SPLB_CTRL_PLB_masterID => net_gnd1(0 downto 0),
SPLB_CTRL_PLB_RNW => net_gnd0,
SPLB_CTRL_PLB_BE => net_gnd4,
SPLB_CTRL_PLB_size => net_gnd4,
SPLB_CTRL_PLB_type => net_gnd3(2 downto 0),
SPLB_CTRL_PLB_wrDBus => net_gnd32,
SPLB_CTRL_Sl_addrAck => open,
SPLB_CTRL_Sl_SSize => open,
SPLB_CTRL_Sl_wait => open,
SPLB_CTRL_Sl_rearbitrate => open,
SPLB_CTRL_Sl_wrDAck => open,
SPLB_CTRL_Sl_wrComp => open,
SPLB_CTRL_Sl_rdDBus => open,
SPLB_CTRL_Sl_rdDAck => open,
SPLB_CTRL_Sl_rdComp => open,
SPLB_CTRL_Sl_MBusy => open,
SPLB_CTRL_Sl_MWrErr => open,
SPLB_CTRL_Sl_MRdErr => open,
SPLB_CTRL_PLB_UABus => net_gnd32,
SPLB_CTRL_PLB_SAValid => net_gnd0,
SPLB_CTRL_PLB_rdPrim => net_gnd0,
SPLB_CTRL_PLB_wrPrim => net_gnd0,
SPLB_CTRL_PLB_abort => net_gnd0,
SPLB_CTRL_PLB_busLock => net_gnd0,
SPLB_CTRL_PLB_MSize => net_gnd2,
SPLB_CTRL_PLB_lockErr => net_gnd0,
SPLB_CTRL_PLB_wrBurst => net_gnd0,
SPLB_CTRL_PLB_rdBurst => net_gnd0,
SPLB_CTRL_PLB_wrPendReq => net_gnd0,
SPLB_CTRL_PLB_rdPendReq => net_gnd0,
SPLB_CTRL_PLB_wrPendPri => net_gnd2,
SPLB_CTRL_PLB_rdPendPri => net_gnd2,
SPLB_CTRL_PLB_reqPri => net_gnd2,
SPLB_CTRL_PLB_TAttribute => net_gnd16,
SPLB_CTRL_Sl_wrBTerm => open,
SPLB_CTRL_Sl_rdWdAddr => open,
SPLB_CTRL_Sl_rdBTerm => open,
SPLB_CTRL_Sl_MIRQ => open,
S_AXI_CTRL_ACLK => net_vcc0,
S_AXI_CTRL_ARESETN => net_gnd0,
S_AXI_CTRL_AWADDR => net_gnd32(0 to 31),
S_AXI_CTRL_AWVALID => net_gnd0,
S_AXI_CTRL_AWREADY => open,
S_AXI_CTRL_WDATA => net_gnd32(0 to 31),
S_AXI_CTRL_WSTRB => net_gnd4(0 to 3),
S_AXI_CTRL_WVALID => net_gnd0,
S_AXI_CTRL_WREADY => open,
S_AXI_CTRL_BRESP => open,
S_AXI_CTRL_BVALID => open,
S_AXI_CTRL_BREADY => net_gnd0,
S_AXI_CTRL_ARADDR => net_gnd32(0 to 31),
S_AXI_CTRL_ARVALID => net_gnd0,
S_AXI_CTRL_ARREADY => open,
S_AXI_CTRL_RDATA => open,
S_AXI_CTRL_RRESP => open,
S_AXI_CTRL_RVALID => open,
S_AXI_CTRL_RREADY => net_gnd0
);
lmb_bram : system_lmb_bram_wrapper
port map (
BRAM_Rst_A => ilmb_port_BRAM_Rst,
BRAM_Clk_A => ilmb_port_BRAM_Clk,
BRAM_EN_A => ilmb_port_BRAM_EN,
BRAM_WEN_A => ilmb_port_BRAM_WEN,
BRAM_Addr_A => ilmb_port_BRAM_Addr,
BRAM_Din_A => ilmb_port_BRAM_Din,
BRAM_Dout_A => ilmb_port_BRAM_Dout,
BRAM_Rst_B => dlmb_port_BRAM_Rst,
BRAM_Clk_B => dlmb_port_BRAM_Clk,
BRAM_EN_B => dlmb_port_BRAM_EN,
BRAM_WEN_B => dlmb_port_BRAM_WEN,
BRAM_Addr_B => dlmb_port_BRAM_Addr,
BRAM_Din_B => dlmb_port_BRAM_Din,
BRAM_Dout_B => dlmb_port_BRAM_Dout
);
DDR2_SDRAM : system_ddr2_sdram_wrapper
port map (
FSL0_M_Clk => net_vcc0,
FSL0_M_Write => net_gnd0,
FSL0_M_Data => net_gnd32,
FSL0_M_Control => net_gnd0,
FSL0_M_Full => open,
FSL0_S_Clk => net_gnd0,
FSL0_S_Read => net_gnd0,
FSL0_S_Data => open,
FSL0_S_Control => open,
FSL0_S_Exists => open,
FSL0_B_M_Clk => net_vcc0,
FSL0_B_M_Write => net_gnd0,
FSL0_B_M_Data => net_gnd32,
FSL0_B_M_Control => net_gnd0,
FSL0_B_M_Full => open,
FSL0_B_S_Clk => net_gnd0,
FSL0_B_S_Read => net_gnd0,
FSL0_B_S_Data => open,
FSL0_B_S_Control => open,
FSL0_B_S_Exists => open,
SPLB0_Clk => clk_125_0000MHzPLL0,
SPLB0_Rst => mb_plb_SPLB_Rst(0),
SPLB0_PLB_ABus => mb_plb_PLB_ABus,
SPLB0_PLB_PAValid => mb_plb_PLB_PAValid,
SPLB0_PLB_SAValid => mb_plb_PLB_SAValid,
SPLB0_PLB_masterID => mb_plb_PLB_masterID,
SPLB0_PLB_RNW => mb_plb_PLB_RNW,
SPLB0_PLB_BE => mb_plb_PLB_BE,
SPLB0_PLB_UABus => mb_plb_PLB_UABus,
SPLB0_PLB_rdPrim => mb_plb_PLB_rdPrim(0),
SPLB0_PLB_wrPrim => mb_plb_PLB_wrPrim(0),
SPLB0_PLB_abort => mb_plb_PLB_abort,
SPLB0_PLB_busLock => mb_plb_PLB_busLock,
SPLB0_PLB_MSize => mb_plb_PLB_MSize,
SPLB0_PLB_size => mb_plb_PLB_size,
SPLB0_PLB_type => mb_plb_PLB_type,
SPLB0_PLB_lockErr => mb_plb_PLB_lockErr,
SPLB0_PLB_wrPendReq => mb_plb_PLB_wrPendReq,
SPLB0_PLB_wrPendPri => mb_plb_PLB_wrPendPri,
SPLB0_PLB_rdPendReq => mb_plb_PLB_rdPendReq,
SPLB0_PLB_rdPendPri => mb_plb_PLB_rdPendPri,
SPLB0_PLB_reqPri => mb_plb_PLB_reqPri,
SPLB0_PLB_TAttribute => mb_plb_PLB_TAttribute,
SPLB0_PLB_rdBurst => mb_plb_PLB_rdBurst,
SPLB0_PLB_wrBurst => mb_plb_PLB_wrBurst,
SPLB0_PLB_wrDBus => mb_plb_PLB_wrDBus,
SPLB0_Sl_addrAck => mb_plb_Sl_addrAck(0),
SPLB0_Sl_SSize => mb_plb_Sl_SSize(0 to 1),
SPLB0_Sl_wait => mb_plb_Sl_wait(0),
SPLB0_Sl_rearbitrate => mb_plb_Sl_rearbitrate(0),
SPLB0_Sl_wrDAck => mb_plb_Sl_wrDAck(0),
SPLB0_Sl_wrComp => mb_plb_Sl_wrComp(0),
SPLB0_Sl_wrBTerm => mb_plb_Sl_wrBTerm(0),
SPLB0_Sl_rdDBus => mb_plb_Sl_rdDBus(0 to 63),
SPLB0_Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(0 to 3),
SPLB0_Sl_rdDAck => mb_plb_Sl_rdDAck(0),
SPLB0_Sl_rdComp => mb_plb_Sl_rdComp(0),
SPLB0_Sl_rdBTerm => mb_plb_Sl_rdBTerm(0),
SPLB0_Sl_MBusy => mb_plb_Sl_MBusy(0 to 5),
SPLB0_Sl_MRdErr => mb_plb_Sl_MRdErr(0 to 5),
SPLB0_Sl_MWrErr => mb_plb_Sl_MWrErr(0 to 5),
SPLB0_Sl_MIRQ => mb_plb_Sl_MIRQ(0 to 5),
SDMA0_Clk => net_gnd0,
SDMA0_Rx_IntOut => open,
SDMA0_Tx_IntOut => open,
SDMA0_RstOut => open,
SDMA0_TX_D => open,
SDMA0_TX_Rem => open,
SDMA0_TX_SOF => open,
SDMA0_TX_EOF => open,
SDMA0_TX_SOP => open,
SDMA0_TX_EOP => open,
SDMA0_TX_Src_Rdy => open,
SDMA0_TX_Dst_Rdy => net_vcc0,
SDMA0_RX_D => net_gnd32,
SDMA0_RX_Rem => net_vcc4,
SDMA0_RX_SOF => net_vcc0,
SDMA0_RX_EOF => net_vcc0,
SDMA0_RX_SOP => net_vcc0,
SDMA0_RX_EOP => net_vcc0,
SDMA0_RX_Src_Rdy => net_vcc0,
SDMA0_RX_Dst_Rdy => open,
SDMA_CTRL0_Clk => net_vcc0,
SDMA_CTRL0_Rst => net_gnd0,
SDMA_CTRL0_PLB_ABus => net_gnd32,
SDMA_CTRL0_PLB_PAValid => net_gnd0,
SDMA_CTRL0_PLB_SAValid => net_gnd0,
SDMA_CTRL0_PLB_masterID => net_gnd1(0 downto 0),
SDMA_CTRL0_PLB_RNW => net_gnd0,
SDMA_CTRL0_PLB_BE => net_gnd8,
SDMA_CTRL0_PLB_UABus => net_gnd32,
SDMA_CTRL0_PLB_rdPrim => net_gnd0,
SDMA_CTRL0_PLB_wrPrim => net_gnd0,
SDMA_CTRL0_PLB_abort => net_gnd0,
SDMA_CTRL0_PLB_busLock => net_gnd0,
SDMA_CTRL0_PLB_MSize => net_gnd2,
SDMA_CTRL0_PLB_size => net_gnd4,
SDMA_CTRL0_PLB_type => net_gnd3(2 downto 0),
SDMA_CTRL0_PLB_lockErr => net_gnd0,
SDMA_CTRL0_PLB_wrPendReq => net_gnd0,
SDMA_CTRL0_PLB_wrPendPri => net_gnd2,
SDMA_CTRL0_PLB_rdPendReq => net_gnd0,
SDMA_CTRL0_PLB_rdPendPri => net_gnd2,
SDMA_CTRL0_PLB_reqPri => net_gnd2,
SDMA_CTRL0_PLB_TAttribute => net_gnd16,
SDMA_CTRL0_PLB_rdBurst => net_gnd0,
SDMA_CTRL0_PLB_wrBurst => net_gnd0,
SDMA_CTRL0_PLB_wrDBus => net_gnd64,
SDMA_CTRL0_Sl_addrAck => open,
SDMA_CTRL0_Sl_SSize => open,
SDMA_CTRL0_Sl_wait => open,
SDMA_CTRL0_Sl_rearbitrate => open,
SDMA_CTRL0_Sl_wrDAck => open,
SDMA_CTRL0_Sl_wrComp => open,
SDMA_CTRL0_Sl_wrBTerm => open,
SDMA_CTRL0_Sl_rdDBus => open,
SDMA_CTRL0_Sl_rdWdAddr => open,
SDMA_CTRL0_Sl_rdDAck => open,
SDMA_CTRL0_Sl_rdComp => open,
SDMA_CTRL0_Sl_rdBTerm => open,
SDMA_CTRL0_Sl_MBusy => open,
SDMA_CTRL0_Sl_MRdErr => open,
SDMA_CTRL0_Sl_MWrErr => open,
SDMA_CTRL0_Sl_MIRQ => open,
PIM0_Addr => net_gnd32(0 to 31),
PIM0_AddrReq => net_gnd0,
PIM0_AddrAck => open,
PIM0_RNW => net_gnd0,
PIM0_Size => net_gnd4(0 to 3),
PIM0_RdModWr => net_gnd0,
PIM0_WrFIFO_Data => net_gnd64(0 to 63),
PIM0_WrFIFO_BE => net_gnd8(0 to 7),
PIM0_WrFIFO_Push => net_gnd0,
PIM0_RdFIFO_Data => open,
PIM0_RdFIFO_Pop => net_gnd0,
PIM0_RdFIFO_RdWdAddr => open,
PIM0_WrFIFO_Empty => open,
PIM0_WrFIFO_AlmostFull => open,
PIM0_WrFIFO_Flush => net_gnd0,
PIM0_RdFIFO_Empty => open,
PIM0_RdFIFO_Flush => net_gnd0,
PIM0_RdFIFO_Latency => open,
PIM0_InitDone => open,
PPC440MC0_MIMCReadNotWrite => net_gnd0,
PPC440MC0_MIMCAddress => net_gnd36,
PPC440MC0_MIMCAddressValid => net_gnd0,
PPC440MC0_MIMCWriteData => net_gnd128,
PPC440MC0_MIMCWriteDataValid => net_gnd0,
PPC440MC0_MIMCByteEnable => net_gnd16,
PPC440MC0_MIMCBankConflict => net_gnd0,
PPC440MC0_MIMCRowConflict => net_gnd0,
PPC440MC0_MCMIReadData => open,
PPC440MC0_MCMIReadDataValid => open,
PPC440MC0_MCMIReadDataErr => open,
PPC440MC0_MCMIAddrReadyToAccept => open,
VFBC0_Cmd_Clk => net_gnd0,
VFBC0_Cmd_Reset => net_gnd0,
VFBC0_Cmd_Data => net_gnd32(0 to 31),
VFBC0_Cmd_Write => net_gnd0,
VFBC0_Cmd_End => net_gnd0,
VFBC0_Cmd_Full => open,
VFBC0_Cmd_Almost_Full => open,
VFBC0_Cmd_Idle => open,
VFBC0_Wd_Clk => net_gnd0,
VFBC0_Wd_Reset => net_gnd0,
VFBC0_Wd_Write => net_gnd0,
VFBC0_Wd_End_Burst => net_gnd0,
VFBC0_Wd_Flush => net_gnd0,
VFBC0_Wd_Data => net_gnd32(0 to 31),
VFBC0_Wd_Data_BE => net_gnd4(0 to 3),
VFBC0_Wd_Full => open,
VFBC0_Wd_Almost_Full => open,
VFBC0_Rd_Clk => net_gnd0,
VFBC0_Rd_Reset => net_gnd0,
VFBC0_Rd_Read => net_gnd0,
VFBC0_Rd_End_Burst => net_gnd0,
VFBC0_Rd_Flush => net_gnd0,
VFBC0_Rd_Data => open,
VFBC0_Rd_Empty => open,
VFBC0_Rd_Almost_Empty => open,
MCB0_cmd_clk => net_gnd0,
MCB0_cmd_en => net_gnd0,
MCB0_cmd_instr => net_gnd3,
MCB0_cmd_bl => net_gnd6,
MCB0_cmd_byte_addr => net_gnd30,
MCB0_cmd_empty => open,
MCB0_cmd_full => open,
MCB0_wr_clk => net_gnd0,
MCB0_wr_en => net_gnd0,
MCB0_wr_mask => net_gnd8(0 to 7),
MCB0_wr_data => net_gnd64(0 to 63),
MCB0_wr_full => open,
MCB0_wr_empty => open,
MCB0_wr_count => open,
MCB0_wr_underrun => open,
MCB0_wr_error => open,
MCB0_rd_clk => net_gnd0,
MCB0_rd_en => net_gnd0,
MCB0_rd_data => open,
MCB0_rd_full => open,
MCB0_rd_empty => open,
MCB0_rd_count => open,
MCB0_rd_overflow => open,
MCB0_rd_error => open,
FSL1_M_Clk => net_vcc0,
FSL1_M_Write => net_gnd0,
FSL1_M_Data => net_gnd32,
FSL1_M_Control => net_gnd0,
FSL1_M_Full => open,
FSL1_S_Clk => net_gnd0,
FSL1_S_Read => net_gnd0,
FSL1_S_Data => open,
FSL1_S_Control => open,
FSL1_S_Exists => open,
FSL1_B_M_Clk => net_vcc0,
FSL1_B_M_Write => net_gnd0,
FSL1_B_M_Data => net_gnd32,
FSL1_B_M_Control => net_gnd0,
FSL1_B_M_Full => open,
FSL1_B_S_Clk => net_gnd0,
FSL1_B_S_Read => net_gnd0,
FSL1_B_S_Data => open,
FSL1_B_S_Control => open,
FSL1_B_S_Exists => open,
SPLB1_Clk => net_vcc0,
SPLB1_Rst => net_gnd0,
SPLB1_PLB_ABus => net_gnd32,
SPLB1_PLB_PAValid => net_gnd0,
SPLB1_PLB_SAValid => net_gnd0,
SPLB1_PLB_masterID => net_gnd1(0 downto 0),
SPLB1_PLB_RNW => net_gnd0,
SPLB1_PLB_BE => net_gnd8,
SPLB1_PLB_UABus => net_gnd32,
SPLB1_PLB_rdPrim => net_gnd0,
SPLB1_PLB_wrPrim => net_gnd0,
SPLB1_PLB_abort => net_gnd0,
SPLB1_PLB_busLock => net_gnd0,
SPLB1_PLB_MSize => net_gnd2,
SPLB1_PLB_size => net_gnd4,
SPLB1_PLB_type => net_gnd3(2 downto 0),
SPLB1_PLB_lockErr => net_gnd0,
SPLB1_PLB_wrPendReq => net_gnd0,
SPLB1_PLB_wrPendPri => net_gnd2,
SPLB1_PLB_rdPendReq => net_gnd0,
SPLB1_PLB_rdPendPri => net_gnd2,
SPLB1_PLB_reqPri => net_gnd2,
SPLB1_PLB_TAttribute => net_gnd16,
SPLB1_PLB_rdBurst => net_gnd0,
SPLB1_PLB_wrBurst => net_gnd0,
SPLB1_PLB_wrDBus => net_gnd64,
SPLB1_Sl_addrAck => open,
SPLB1_Sl_SSize => open,
SPLB1_Sl_wait => open,
SPLB1_Sl_rearbitrate => open,
SPLB1_Sl_wrDAck => open,
SPLB1_Sl_wrComp => open,
SPLB1_Sl_wrBTerm => open,
SPLB1_Sl_rdDBus => open,
SPLB1_Sl_rdWdAddr => open,
SPLB1_Sl_rdDAck => open,
SPLB1_Sl_rdComp => open,
SPLB1_Sl_rdBTerm => open,
SPLB1_Sl_MBusy => open,
SPLB1_Sl_MRdErr => open,
SPLB1_Sl_MWrErr => open,
SPLB1_Sl_MIRQ => open,
SDMA1_Clk => net_gnd0,
SDMA1_Rx_IntOut => open,
SDMA1_Tx_IntOut => open,
SDMA1_RstOut => open,
SDMA1_TX_D => open,
SDMA1_TX_Rem => open,
SDMA1_TX_SOF => open,
SDMA1_TX_EOF => open,
SDMA1_TX_SOP => open,
SDMA1_TX_EOP => open,
SDMA1_TX_Src_Rdy => open,
SDMA1_TX_Dst_Rdy => net_vcc0,
SDMA1_RX_D => net_gnd32,
SDMA1_RX_Rem => net_vcc4,
SDMA1_RX_SOF => net_vcc0,
SDMA1_RX_EOF => net_vcc0,
SDMA1_RX_SOP => net_vcc0,
SDMA1_RX_EOP => net_vcc0,
SDMA1_RX_Src_Rdy => net_vcc0,
SDMA1_RX_Dst_Rdy => open,
SDMA_CTRL1_Clk => net_vcc0,
SDMA_CTRL1_Rst => net_gnd0,
SDMA_CTRL1_PLB_ABus => net_gnd32,
SDMA_CTRL1_PLB_PAValid => net_gnd0,
SDMA_CTRL1_PLB_SAValid => net_gnd0,
SDMA_CTRL1_PLB_masterID => net_gnd1(0 downto 0),
SDMA_CTRL1_PLB_RNW => net_gnd0,
SDMA_CTRL1_PLB_BE => net_gnd8,
SDMA_CTRL1_PLB_UABus => net_gnd32,
SDMA_CTRL1_PLB_rdPrim => net_gnd0,
SDMA_CTRL1_PLB_wrPrim => net_gnd0,
SDMA_CTRL1_PLB_abort => net_gnd0,
SDMA_CTRL1_PLB_busLock => net_gnd0,
SDMA_CTRL1_PLB_MSize => net_gnd2,
SDMA_CTRL1_PLB_size => net_gnd4,
SDMA_CTRL1_PLB_type => net_gnd3(2 downto 0),
SDMA_CTRL1_PLB_lockErr => net_gnd0,
SDMA_CTRL1_PLB_wrPendReq => net_gnd0,
SDMA_CTRL1_PLB_wrPendPri => net_gnd2,
SDMA_CTRL1_PLB_rdPendReq => net_gnd0,
SDMA_CTRL1_PLB_rdPendPri => net_gnd2,
SDMA_CTRL1_PLB_reqPri => net_gnd2,
SDMA_CTRL1_PLB_TAttribute => net_gnd16,
SDMA_CTRL1_PLB_rdBurst => net_gnd0,
SDMA_CTRL1_PLB_wrBurst => net_gnd0,
SDMA_CTRL1_PLB_wrDBus => net_gnd64,
SDMA_CTRL1_Sl_addrAck => open,
SDMA_CTRL1_Sl_SSize => open,
SDMA_CTRL1_Sl_wait => open,
SDMA_CTRL1_Sl_rearbitrate => open,
SDMA_CTRL1_Sl_wrDAck => open,
SDMA_CTRL1_Sl_wrComp => open,
SDMA_CTRL1_Sl_wrBTerm => open,
SDMA_CTRL1_Sl_rdDBus => open,
SDMA_CTRL1_Sl_rdWdAddr => open,
SDMA_CTRL1_Sl_rdDAck => open,
SDMA_CTRL1_Sl_rdComp => open,
SDMA_CTRL1_Sl_rdBTerm => open,
SDMA_CTRL1_Sl_MBusy => open,
SDMA_CTRL1_Sl_MRdErr => open,
SDMA_CTRL1_Sl_MWrErr => open,
SDMA_CTRL1_Sl_MIRQ => open,
PIM1_Addr => net_gnd32(0 to 31),
PIM1_AddrReq => net_gnd0,
PIM1_AddrAck => open,
PIM1_RNW => net_gnd0,
PIM1_Size => net_gnd4(0 to 3),
PIM1_RdModWr => net_gnd0,
PIM1_WrFIFO_Data => net_gnd64(0 to 63),
PIM1_WrFIFO_BE => net_gnd8(0 to 7),
PIM1_WrFIFO_Push => net_gnd0,
PIM1_RdFIFO_Data => open,
PIM1_RdFIFO_Pop => net_gnd0,
PIM1_RdFIFO_RdWdAddr => open,
PIM1_WrFIFO_Empty => open,
PIM1_WrFIFO_AlmostFull => open,
PIM1_WrFIFO_Flush => net_gnd0,
PIM1_RdFIFO_Empty => open,
PIM1_RdFIFO_Flush => net_gnd0,
PIM1_RdFIFO_Latency => open,
PIM1_InitDone => open,
PPC440MC1_MIMCReadNotWrite => net_gnd0,
PPC440MC1_MIMCAddress => net_gnd36,
PPC440MC1_MIMCAddressValid => net_gnd0,
PPC440MC1_MIMCWriteData => net_gnd128,
PPC440MC1_MIMCWriteDataValid => net_gnd0,
PPC440MC1_MIMCByteEnable => net_gnd16,
PPC440MC1_MIMCBankConflict => net_gnd0,
PPC440MC1_MIMCRowConflict => net_gnd0,
PPC440MC1_MCMIReadData => open,
PPC440MC1_MCMIReadDataValid => open,
PPC440MC1_MCMIReadDataErr => open,
PPC440MC1_MCMIAddrReadyToAccept => open,
VFBC1_Cmd_Clk => net_gnd0,
VFBC1_Cmd_Reset => net_gnd0,
VFBC1_Cmd_Data => net_gnd32(0 to 31),
VFBC1_Cmd_Write => net_gnd0,
VFBC1_Cmd_End => net_gnd0,
VFBC1_Cmd_Full => open,
VFBC1_Cmd_Almost_Full => open,
VFBC1_Cmd_Idle => open,
VFBC1_Wd_Clk => net_gnd0,
VFBC1_Wd_Reset => net_gnd0,
VFBC1_Wd_Write => net_gnd0,
VFBC1_Wd_End_Burst => net_gnd0,
VFBC1_Wd_Flush => net_gnd0,
VFBC1_Wd_Data => net_gnd32(0 to 31),
VFBC1_Wd_Data_BE => net_gnd4(0 to 3),
VFBC1_Wd_Full => open,
VFBC1_Wd_Almost_Full => open,
VFBC1_Rd_Clk => net_gnd0,
VFBC1_Rd_Reset => net_gnd0,
VFBC1_Rd_Read => net_gnd0,
VFBC1_Rd_End_Burst => net_gnd0,
VFBC1_Rd_Flush => net_gnd0,
VFBC1_Rd_Data => open,
VFBC1_Rd_Empty => open,
VFBC1_Rd_Almost_Empty => open,
MCB1_cmd_clk => net_gnd0,
MCB1_cmd_en => net_gnd0,
MCB1_cmd_instr => net_gnd3,
MCB1_cmd_bl => net_gnd6,
MCB1_cmd_byte_addr => net_gnd30,
MCB1_cmd_empty => open,
MCB1_cmd_full => open,
MCB1_wr_clk => net_gnd0,
MCB1_wr_en => net_gnd0,
MCB1_wr_mask => net_gnd8(0 to 7),
MCB1_wr_data => net_gnd64(0 to 63),
MCB1_wr_full => open,
MCB1_wr_empty => open,
MCB1_wr_count => open,
MCB1_wr_underrun => open,
MCB1_wr_error => open,
MCB1_rd_clk => net_gnd0,
MCB1_rd_en => net_gnd0,
MCB1_rd_data => open,
MCB1_rd_full => open,
MCB1_rd_empty => open,
MCB1_rd_count => open,
MCB1_rd_overflow => open,
MCB1_rd_error => open,
FSL2_M_Clk => net_vcc0,
FSL2_M_Write => net_gnd0,
FSL2_M_Data => net_gnd32,
FSL2_M_Control => net_gnd0,
FSL2_M_Full => open,
FSL2_S_Clk => net_gnd0,
FSL2_S_Read => net_gnd0,
FSL2_S_Data => open,
FSL2_S_Control => open,
FSL2_S_Exists => open,
FSL2_B_M_Clk => net_vcc0,
FSL2_B_M_Write => net_gnd0,
FSL2_B_M_Data => net_gnd32,
FSL2_B_M_Control => net_gnd0,
FSL2_B_M_Full => open,
FSL2_B_S_Clk => net_gnd0,
FSL2_B_S_Read => net_gnd0,
FSL2_B_S_Data => open,
FSL2_B_S_Control => open,
FSL2_B_S_Exists => open,
SPLB2_Clk => net_vcc0,
SPLB2_Rst => net_gnd0,
SPLB2_PLB_ABus => net_gnd32,
SPLB2_PLB_PAValid => net_gnd0,
SPLB2_PLB_SAValid => net_gnd0,
SPLB2_PLB_masterID => net_gnd1(0 downto 0),
SPLB2_PLB_RNW => net_gnd0,
SPLB2_PLB_BE => net_gnd8,
SPLB2_PLB_UABus => net_gnd32,
SPLB2_PLB_rdPrim => net_gnd0,
SPLB2_PLB_wrPrim => net_gnd0,
SPLB2_PLB_abort => net_gnd0,
SPLB2_PLB_busLock => net_gnd0,
SPLB2_PLB_MSize => net_gnd2,
SPLB2_PLB_size => net_gnd4,
SPLB2_PLB_type => net_gnd3(2 downto 0),
SPLB2_PLB_lockErr => net_gnd0,
SPLB2_PLB_wrPendReq => net_gnd0,
SPLB2_PLB_wrPendPri => net_gnd2,
SPLB2_PLB_rdPendReq => net_gnd0,
SPLB2_PLB_rdPendPri => net_gnd2,
SPLB2_PLB_reqPri => net_gnd2,
SPLB2_PLB_TAttribute => net_gnd16,
SPLB2_PLB_rdBurst => net_gnd0,
SPLB2_PLB_wrBurst => net_gnd0,
SPLB2_PLB_wrDBus => net_gnd64,
SPLB2_Sl_addrAck => open,
SPLB2_Sl_SSize => open,
SPLB2_Sl_wait => open,
SPLB2_Sl_rearbitrate => open,
SPLB2_Sl_wrDAck => open,
SPLB2_Sl_wrComp => open,
SPLB2_Sl_wrBTerm => open,
SPLB2_Sl_rdDBus => open,
SPLB2_Sl_rdWdAddr => open,
SPLB2_Sl_rdDAck => open,
SPLB2_Sl_rdComp => open,
SPLB2_Sl_rdBTerm => open,
SPLB2_Sl_MBusy => open,
SPLB2_Sl_MRdErr => open,
SPLB2_Sl_MWrErr => open,
SPLB2_Sl_MIRQ => open,
SDMA2_Clk => net_gnd0,
SDMA2_Rx_IntOut => open,
SDMA2_Tx_IntOut => open,
SDMA2_RstOut => open,
SDMA2_TX_D => open,
SDMA2_TX_Rem => open,
SDMA2_TX_SOF => open,
SDMA2_TX_EOF => open,
SDMA2_TX_SOP => open,
SDMA2_TX_EOP => open,
SDMA2_TX_Src_Rdy => open,
SDMA2_TX_Dst_Rdy => net_vcc0,
SDMA2_RX_D => net_gnd32,
SDMA2_RX_Rem => net_vcc4,
SDMA2_RX_SOF => net_vcc0,
SDMA2_RX_EOF => net_vcc0,
SDMA2_RX_SOP => net_vcc0,
SDMA2_RX_EOP => net_vcc0,
SDMA2_RX_Src_Rdy => net_vcc0,
SDMA2_RX_Dst_Rdy => open,
SDMA_CTRL2_Clk => net_vcc0,
SDMA_CTRL2_Rst => net_gnd0,
SDMA_CTRL2_PLB_ABus => net_gnd32,
SDMA_CTRL2_PLB_PAValid => net_gnd0,
SDMA_CTRL2_PLB_SAValid => net_gnd0,
SDMA_CTRL2_PLB_masterID => net_gnd1(0 downto 0),
SDMA_CTRL2_PLB_RNW => net_gnd0,
SDMA_CTRL2_PLB_BE => net_gnd8,
SDMA_CTRL2_PLB_UABus => net_gnd32,
SDMA_CTRL2_PLB_rdPrim => net_gnd0,
SDMA_CTRL2_PLB_wrPrim => net_gnd0,
SDMA_CTRL2_PLB_abort => net_gnd0,
SDMA_CTRL2_PLB_busLock => net_gnd0,
SDMA_CTRL2_PLB_MSize => net_gnd2,
SDMA_CTRL2_PLB_size => net_gnd4,
SDMA_CTRL2_PLB_type => net_gnd3(2 downto 0),
SDMA_CTRL2_PLB_lockErr => net_gnd0,
SDMA_CTRL2_PLB_wrPendReq => net_gnd0,
SDMA_CTRL2_PLB_wrPendPri => net_gnd2,
SDMA_CTRL2_PLB_rdPendReq => net_gnd0,
SDMA_CTRL2_PLB_rdPendPri => net_gnd2,
SDMA_CTRL2_PLB_reqPri => net_gnd2,
SDMA_CTRL2_PLB_TAttribute => net_gnd16,
SDMA_CTRL2_PLB_rdBurst => net_gnd0,
SDMA_CTRL2_PLB_wrBurst => net_gnd0,
SDMA_CTRL2_PLB_wrDBus => net_gnd64,
SDMA_CTRL2_Sl_addrAck => open,
SDMA_CTRL2_Sl_SSize => open,
SDMA_CTRL2_Sl_wait => open,
SDMA_CTRL2_Sl_rearbitrate => open,
SDMA_CTRL2_Sl_wrDAck => open,
SDMA_CTRL2_Sl_wrComp => open,
SDMA_CTRL2_Sl_wrBTerm => open,
SDMA_CTRL2_Sl_rdDBus => open,
SDMA_CTRL2_Sl_rdWdAddr => open,
SDMA_CTRL2_Sl_rdDAck => open,
SDMA_CTRL2_Sl_rdComp => open,
SDMA_CTRL2_Sl_rdBTerm => open,
SDMA_CTRL2_Sl_MBusy => open,
SDMA_CTRL2_Sl_MRdErr => open,
SDMA_CTRL2_Sl_MWrErr => open,
SDMA_CTRL2_Sl_MIRQ => open,
PIM2_Addr => net_gnd32(0 to 31),
PIM2_AddrReq => net_gnd0,
PIM2_AddrAck => open,
PIM2_RNW => net_gnd0,
PIM2_Size => net_gnd4(0 to 3),
PIM2_RdModWr => net_gnd0,
PIM2_WrFIFO_Data => net_gnd64(0 to 63),
PIM2_WrFIFO_BE => net_gnd8(0 to 7),
PIM2_WrFIFO_Push => net_gnd0,
PIM2_RdFIFO_Data => open,
PIM2_RdFIFO_Pop => net_gnd0,
PIM2_RdFIFO_RdWdAddr => open,
PIM2_WrFIFO_Empty => open,
PIM2_WrFIFO_AlmostFull => open,
PIM2_WrFIFO_Flush => net_gnd0,
PIM2_RdFIFO_Empty => open,
PIM2_RdFIFO_Flush => net_gnd0,
PIM2_RdFIFO_Latency => open,
PIM2_InitDone => open,
PPC440MC2_MIMCReadNotWrite => net_gnd0,
PPC440MC2_MIMCAddress => net_gnd36,
PPC440MC2_MIMCAddressValid => net_gnd0,
PPC440MC2_MIMCWriteData => net_gnd128,
PPC440MC2_MIMCWriteDataValid => net_gnd0,
PPC440MC2_MIMCByteEnable => net_gnd16,
PPC440MC2_MIMCBankConflict => net_gnd0,
PPC440MC2_MIMCRowConflict => net_gnd0,
PPC440MC2_MCMIReadData => open,
PPC440MC2_MCMIReadDataValid => open,
PPC440MC2_MCMIReadDataErr => open,
PPC440MC2_MCMIAddrReadyToAccept => open,
VFBC2_Cmd_Clk => net_gnd0,
VFBC2_Cmd_Reset => net_gnd0,
VFBC2_Cmd_Data => net_gnd32(0 to 31),
VFBC2_Cmd_Write => net_gnd0,
VFBC2_Cmd_End => net_gnd0,
VFBC2_Cmd_Full => open,
VFBC2_Cmd_Almost_Full => open,
VFBC2_Cmd_Idle => open,
VFBC2_Wd_Clk => net_gnd0,
VFBC2_Wd_Reset => net_gnd0,
VFBC2_Wd_Write => net_gnd0,
VFBC2_Wd_End_Burst => net_gnd0,
VFBC2_Wd_Flush => net_gnd0,
VFBC2_Wd_Data => net_gnd32(0 to 31),
VFBC2_Wd_Data_BE => net_gnd4(0 to 3),
VFBC2_Wd_Full => open,
VFBC2_Wd_Almost_Full => open,
VFBC2_Rd_Clk => net_gnd0,
VFBC2_Rd_Reset => net_gnd0,
VFBC2_Rd_Read => net_gnd0,
VFBC2_Rd_End_Burst => net_gnd0,
VFBC2_Rd_Flush => net_gnd0,
VFBC2_Rd_Data => open,
VFBC2_Rd_Empty => open,
VFBC2_Rd_Almost_Empty => open,
MCB2_cmd_clk => net_gnd0,
MCB2_cmd_en => net_gnd0,
MCB2_cmd_instr => net_gnd3,
MCB2_cmd_bl => net_gnd6,
MCB2_cmd_byte_addr => net_gnd30,
MCB2_cmd_empty => open,
MCB2_cmd_full => open,
MCB2_wr_clk => net_gnd0,
MCB2_wr_en => net_gnd0,
MCB2_wr_mask => net_gnd8(0 to 7),
MCB2_wr_data => net_gnd64(0 to 63),
MCB2_wr_full => open,
MCB2_wr_empty => open,
MCB2_wr_count => open,
MCB2_wr_underrun => open,
MCB2_wr_error => open,
MCB2_rd_clk => net_gnd0,
MCB2_rd_en => net_gnd0,
MCB2_rd_data => open,
MCB2_rd_full => open,
MCB2_rd_empty => open,
MCB2_rd_count => open,
MCB2_rd_overflow => open,
MCB2_rd_error => open,
FSL3_M_Clk => net_vcc0,
FSL3_M_Write => net_gnd0,
FSL3_M_Data => net_gnd32,
FSL3_M_Control => net_gnd0,
FSL3_M_Full => open,
FSL3_S_Clk => net_gnd0,
FSL3_S_Read => net_gnd0,
FSL3_S_Data => open,
FSL3_S_Control => open,
FSL3_S_Exists => open,
FSL3_B_M_Clk => net_vcc0,
FSL3_B_M_Write => net_gnd0,
FSL3_B_M_Data => net_gnd32,
FSL3_B_M_Control => net_gnd0,
FSL3_B_M_Full => open,
FSL3_B_S_Clk => net_gnd0,
FSL3_B_S_Read => net_gnd0,
FSL3_B_S_Data => open,
FSL3_B_S_Control => open,
FSL3_B_S_Exists => open,
SPLB3_Clk => net_vcc0,
SPLB3_Rst => net_gnd0,
SPLB3_PLB_ABus => net_gnd32,
SPLB3_PLB_PAValid => net_gnd0,
SPLB3_PLB_SAValid => net_gnd0,
SPLB3_PLB_masterID => net_gnd1(0 downto 0),
SPLB3_PLB_RNW => net_gnd0,
SPLB3_PLB_BE => net_gnd8,
SPLB3_PLB_UABus => net_gnd32,
SPLB3_PLB_rdPrim => net_gnd0,
SPLB3_PLB_wrPrim => net_gnd0,
SPLB3_PLB_abort => net_gnd0,
SPLB3_PLB_busLock => net_gnd0,
SPLB3_PLB_MSize => net_gnd2,
SPLB3_PLB_size => net_gnd4,
SPLB3_PLB_type => net_gnd3(2 downto 0),
SPLB3_PLB_lockErr => net_gnd0,
SPLB3_PLB_wrPendReq => net_gnd0,
SPLB3_PLB_wrPendPri => net_gnd2,
SPLB3_PLB_rdPendReq => net_gnd0,
SPLB3_PLB_rdPendPri => net_gnd2,
SPLB3_PLB_reqPri => net_gnd2,
SPLB3_PLB_TAttribute => net_gnd16,
SPLB3_PLB_rdBurst => net_gnd0,
SPLB3_PLB_wrBurst => net_gnd0,
SPLB3_PLB_wrDBus => net_gnd64,
SPLB3_Sl_addrAck => open,
SPLB3_Sl_SSize => open,
SPLB3_Sl_wait => open,
SPLB3_Sl_rearbitrate => open,
SPLB3_Sl_wrDAck => open,
SPLB3_Sl_wrComp => open,
SPLB3_Sl_wrBTerm => open,
SPLB3_Sl_rdDBus => open,
SPLB3_Sl_rdWdAddr => open,
SPLB3_Sl_rdDAck => open,
SPLB3_Sl_rdComp => open,
SPLB3_Sl_rdBTerm => open,
SPLB3_Sl_MBusy => open,
SPLB3_Sl_MRdErr => open,
SPLB3_Sl_MWrErr => open,
SPLB3_Sl_MIRQ => open,
SDMA3_Clk => net_gnd0,
SDMA3_Rx_IntOut => open,
SDMA3_Tx_IntOut => open,
SDMA3_RstOut => open,
SDMA3_TX_D => open,
SDMA3_TX_Rem => open,
SDMA3_TX_SOF => open,
SDMA3_TX_EOF => open,
SDMA3_TX_SOP => open,
SDMA3_TX_EOP => open,
SDMA3_TX_Src_Rdy => open,
SDMA3_TX_Dst_Rdy => net_vcc0,
SDMA3_RX_D => net_gnd32,
SDMA3_RX_Rem => net_vcc4,
SDMA3_RX_SOF => net_vcc0,
SDMA3_RX_EOF => net_vcc0,
SDMA3_RX_SOP => net_vcc0,
SDMA3_RX_EOP => net_vcc0,
SDMA3_RX_Src_Rdy => net_vcc0,
SDMA3_RX_Dst_Rdy => open,
SDMA_CTRL3_Clk => net_vcc0,
SDMA_CTRL3_Rst => net_gnd0,
SDMA_CTRL3_PLB_ABus => net_gnd32,
SDMA_CTRL3_PLB_PAValid => net_gnd0,
SDMA_CTRL3_PLB_SAValid => net_gnd0,
SDMA_CTRL3_PLB_masterID => net_gnd1(0 downto 0),
SDMA_CTRL3_PLB_RNW => net_gnd0,
SDMA_CTRL3_PLB_BE => net_gnd8,
SDMA_CTRL3_PLB_UABus => net_gnd32,
SDMA_CTRL3_PLB_rdPrim => net_gnd0,
SDMA_CTRL3_PLB_wrPrim => net_gnd0,
SDMA_CTRL3_PLB_abort => net_gnd0,
SDMA_CTRL3_PLB_busLock => net_gnd0,
SDMA_CTRL3_PLB_MSize => net_gnd2,
SDMA_CTRL3_PLB_size => net_gnd4,
SDMA_CTRL3_PLB_type => net_gnd3(2 downto 0),
SDMA_CTRL3_PLB_lockErr => net_gnd0,
SDMA_CTRL3_PLB_wrPendReq => net_gnd0,
SDMA_CTRL3_PLB_wrPendPri => net_gnd2,
SDMA_CTRL3_PLB_rdPendReq => net_gnd0,
SDMA_CTRL3_PLB_rdPendPri => net_gnd2,
SDMA_CTRL3_PLB_reqPri => net_gnd2,
SDMA_CTRL3_PLB_TAttribute => net_gnd16,
SDMA_CTRL3_PLB_rdBurst => net_gnd0,
SDMA_CTRL3_PLB_wrBurst => net_gnd0,
SDMA_CTRL3_PLB_wrDBus => net_gnd64,
SDMA_CTRL3_Sl_addrAck => open,
SDMA_CTRL3_Sl_SSize => open,
SDMA_CTRL3_Sl_wait => open,
SDMA_CTRL3_Sl_rearbitrate => open,
SDMA_CTRL3_Sl_wrDAck => open,
SDMA_CTRL3_Sl_wrComp => open,
SDMA_CTRL3_Sl_wrBTerm => open,
SDMA_CTRL3_Sl_rdDBus => open,
SDMA_CTRL3_Sl_rdWdAddr => open,
SDMA_CTRL3_Sl_rdDAck => open,
SDMA_CTRL3_Sl_rdComp => open,
SDMA_CTRL3_Sl_rdBTerm => open,
SDMA_CTRL3_Sl_MBusy => open,
SDMA_CTRL3_Sl_MRdErr => open,
SDMA_CTRL3_Sl_MWrErr => open,
SDMA_CTRL3_Sl_MIRQ => open,
PIM3_Addr => net_gnd32(0 to 31),
PIM3_AddrReq => net_gnd0,
PIM3_AddrAck => open,
PIM3_RNW => net_gnd0,
PIM3_Size => net_gnd4(0 to 3),
PIM3_RdModWr => net_gnd0,
PIM3_WrFIFO_Data => net_gnd64(0 to 63),
PIM3_WrFIFO_BE => net_gnd8(0 to 7),
PIM3_WrFIFO_Push => net_gnd0,
PIM3_RdFIFO_Data => open,
PIM3_RdFIFO_Pop => net_gnd0,
PIM3_RdFIFO_RdWdAddr => open,
PIM3_WrFIFO_Empty => open,
PIM3_WrFIFO_AlmostFull => open,
PIM3_WrFIFO_Flush => net_gnd0,
PIM3_RdFIFO_Empty => open,
PIM3_RdFIFO_Flush => net_gnd0,
PIM3_RdFIFO_Latency => open,
PIM3_InitDone => open,
PPC440MC3_MIMCReadNotWrite => net_gnd0,
PPC440MC3_MIMCAddress => net_gnd36,
PPC440MC3_MIMCAddressValid => net_gnd0,
PPC440MC3_MIMCWriteData => net_gnd128,
PPC440MC3_MIMCWriteDataValid => net_gnd0,
PPC440MC3_MIMCByteEnable => net_gnd16,
PPC440MC3_MIMCBankConflict => net_gnd0,
PPC440MC3_MIMCRowConflict => net_gnd0,
PPC440MC3_MCMIReadData => open,
PPC440MC3_MCMIReadDataValid => open,
PPC440MC3_MCMIReadDataErr => open,
PPC440MC3_MCMIAddrReadyToAccept => open,
VFBC3_Cmd_Clk => net_gnd0,
VFBC3_Cmd_Reset => net_gnd0,
VFBC3_Cmd_Data => net_gnd32(0 to 31),
VFBC3_Cmd_Write => net_gnd0,
VFBC3_Cmd_End => net_gnd0,
VFBC3_Cmd_Full => open,
VFBC3_Cmd_Almost_Full => open,
VFBC3_Cmd_Idle => open,
VFBC3_Wd_Clk => net_gnd0,
VFBC3_Wd_Reset => net_gnd0,
VFBC3_Wd_Write => net_gnd0,
VFBC3_Wd_End_Burst => net_gnd0,
VFBC3_Wd_Flush => net_gnd0,
VFBC3_Wd_Data => net_gnd32(0 to 31),
VFBC3_Wd_Data_BE => net_gnd4(0 to 3),
VFBC3_Wd_Full => open,
VFBC3_Wd_Almost_Full => open,
VFBC3_Rd_Clk => net_gnd0,
VFBC3_Rd_Reset => net_gnd0,
VFBC3_Rd_Read => net_gnd0,
VFBC3_Rd_End_Burst => net_gnd0,
VFBC3_Rd_Flush => net_gnd0,
VFBC3_Rd_Data => open,
VFBC3_Rd_Empty => open,
VFBC3_Rd_Almost_Empty => open,
MCB3_cmd_clk => net_gnd0,
MCB3_cmd_en => net_gnd0,
MCB3_cmd_instr => net_gnd3,
MCB3_cmd_bl => net_gnd6,
MCB3_cmd_byte_addr => net_gnd30,
MCB3_cmd_empty => open,
MCB3_cmd_full => open,
MCB3_wr_clk => net_gnd0,
MCB3_wr_en => net_gnd0,
MCB3_wr_mask => net_gnd8(0 to 7),
MCB3_wr_data => net_gnd64(0 to 63),
MCB3_wr_full => open,
MCB3_wr_empty => open,
MCB3_wr_count => open,
MCB3_wr_underrun => open,
MCB3_wr_error => open,
MCB3_rd_clk => net_gnd0,
MCB3_rd_en => net_gnd0,
MCB3_rd_data => open,
MCB3_rd_full => open,
MCB3_rd_empty => open,
MCB3_rd_count => open,
MCB3_rd_overflow => open,
MCB3_rd_error => open,
FSL4_M_Clk => net_vcc0,
FSL4_M_Write => net_gnd0,
FSL4_M_Data => net_gnd32,
FSL4_M_Control => net_gnd0,
FSL4_M_Full => open,
FSL4_S_Clk => net_gnd0,
FSL4_S_Read => net_gnd0,
FSL4_S_Data => open,
FSL4_S_Control => open,
FSL4_S_Exists => open,
FSL4_B_M_Clk => net_vcc0,
FSL4_B_M_Write => net_gnd0,
FSL4_B_M_Data => net_gnd32,
FSL4_B_M_Control => net_gnd0,
FSL4_B_M_Full => open,
FSL4_B_S_Clk => net_gnd0,
FSL4_B_S_Read => net_gnd0,
FSL4_B_S_Data => open,
FSL4_B_S_Control => open,
FSL4_B_S_Exists => open,
SPLB4_Clk => net_vcc0,
SPLB4_Rst => net_gnd0,
SPLB4_PLB_ABus => net_gnd32,
SPLB4_PLB_PAValid => net_gnd0,
SPLB4_PLB_SAValid => net_gnd0,
SPLB4_PLB_masterID => net_gnd1(0 downto 0),
SPLB4_PLB_RNW => net_gnd0,
SPLB4_PLB_BE => net_gnd8,
SPLB4_PLB_UABus => net_gnd32,
SPLB4_PLB_rdPrim => net_gnd0,
SPLB4_PLB_wrPrim => net_gnd0,
SPLB4_PLB_abort => net_gnd0,
SPLB4_PLB_busLock => net_gnd0,
SPLB4_PLB_MSize => net_gnd2,
SPLB4_PLB_size => net_gnd4,
SPLB4_PLB_type => net_gnd3(2 downto 0),
SPLB4_PLB_lockErr => net_gnd0,
SPLB4_PLB_wrPendReq => net_gnd0,
SPLB4_PLB_wrPendPri => net_gnd2,
SPLB4_PLB_rdPendReq => net_gnd0,
SPLB4_PLB_rdPendPri => net_gnd2,
SPLB4_PLB_reqPri => net_gnd2,
SPLB4_PLB_TAttribute => net_gnd16,
SPLB4_PLB_rdBurst => net_gnd0,
SPLB4_PLB_wrBurst => net_gnd0,
SPLB4_PLB_wrDBus => net_gnd64,
SPLB4_Sl_addrAck => open,
SPLB4_Sl_SSize => open,
SPLB4_Sl_wait => open,
SPLB4_Sl_rearbitrate => open,
SPLB4_Sl_wrDAck => open,
SPLB4_Sl_wrComp => open,
SPLB4_Sl_wrBTerm => open,
SPLB4_Sl_rdDBus => open,
SPLB4_Sl_rdWdAddr => open,
SPLB4_Sl_rdDAck => open,
SPLB4_Sl_rdComp => open,
SPLB4_Sl_rdBTerm => open,
SPLB4_Sl_MBusy => open,
SPLB4_Sl_MRdErr => open,
SPLB4_Sl_MWrErr => open,
SPLB4_Sl_MIRQ => open,
SDMA4_Clk => net_gnd0,
SDMA4_Rx_IntOut => open,
SDMA4_Tx_IntOut => open,
SDMA4_RstOut => open,
SDMA4_TX_D => open,
SDMA4_TX_Rem => open,
SDMA4_TX_SOF => open,
SDMA4_TX_EOF => open,
SDMA4_TX_SOP => open,
SDMA4_TX_EOP => open,
SDMA4_TX_Src_Rdy => open,
SDMA4_TX_Dst_Rdy => net_vcc0,
SDMA4_RX_D => net_gnd32,
SDMA4_RX_Rem => net_vcc4,
SDMA4_RX_SOF => net_vcc0,
SDMA4_RX_EOF => net_vcc0,
SDMA4_RX_SOP => net_vcc0,
SDMA4_RX_EOP => net_vcc0,
SDMA4_RX_Src_Rdy => net_vcc0,
SDMA4_RX_Dst_Rdy => open,
SDMA_CTRL4_Clk => net_vcc0,
SDMA_CTRL4_Rst => net_gnd0,
SDMA_CTRL4_PLB_ABus => net_gnd32,
SDMA_CTRL4_PLB_PAValid => net_gnd0,
SDMA_CTRL4_PLB_SAValid => net_gnd0,
SDMA_CTRL4_PLB_masterID => net_gnd1(0 downto 0),
SDMA_CTRL4_PLB_RNW => net_gnd0,
SDMA_CTRL4_PLB_BE => net_gnd8,
SDMA_CTRL4_PLB_UABus => net_gnd32,
SDMA_CTRL4_PLB_rdPrim => net_gnd0,
SDMA_CTRL4_PLB_wrPrim => net_gnd0,
SDMA_CTRL4_PLB_abort => net_gnd0,
SDMA_CTRL4_PLB_busLock => net_gnd0,
SDMA_CTRL4_PLB_MSize => net_gnd2,
SDMA_CTRL4_PLB_size => net_gnd4,
SDMA_CTRL4_PLB_type => net_gnd3(2 downto 0),
SDMA_CTRL4_PLB_lockErr => net_gnd0,
SDMA_CTRL4_PLB_wrPendReq => net_gnd0,
SDMA_CTRL4_PLB_wrPendPri => net_gnd2,
SDMA_CTRL4_PLB_rdPendReq => net_gnd0,
SDMA_CTRL4_PLB_rdPendPri => net_gnd2,
SDMA_CTRL4_PLB_reqPri => net_gnd2,
SDMA_CTRL4_PLB_TAttribute => net_gnd16,
SDMA_CTRL4_PLB_rdBurst => net_gnd0,
SDMA_CTRL4_PLB_wrBurst => net_gnd0,
SDMA_CTRL4_PLB_wrDBus => net_gnd64,
SDMA_CTRL4_Sl_addrAck => open,
SDMA_CTRL4_Sl_SSize => open,
SDMA_CTRL4_Sl_wait => open,
SDMA_CTRL4_Sl_rearbitrate => open,
SDMA_CTRL4_Sl_wrDAck => open,
SDMA_CTRL4_Sl_wrComp => open,
SDMA_CTRL4_Sl_wrBTerm => open,
SDMA_CTRL4_Sl_rdDBus => open,
SDMA_CTRL4_Sl_rdWdAddr => open,
SDMA_CTRL4_Sl_rdDAck => open,
SDMA_CTRL4_Sl_rdComp => open,
SDMA_CTRL4_Sl_rdBTerm => open,
SDMA_CTRL4_Sl_MBusy => open,
SDMA_CTRL4_Sl_MRdErr => open,
SDMA_CTRL4_Sl_MWrErr => open,
SDMA_CTRL4_Sl_MIRQ => open,
PIM4_Addr => net_gnd32(0 to 31),
PIM4_AddrReq => net_gnd0,
PIM4_AddrAck => open,
PIM4_RNW => net_gnd0,
PIM4_Size => net_gnd4(0 to 3),
PIM4_RdModWr => net_gnd0,
PIM4_WrFIFO_Data => net_gnd64(0 to 63),
PIM4_WrFIFO_BE => net_gnd8(0 to 7),
PIM4_WrFIFO_Push => net_gnd0,
PIM4_RdFIFO_Data => open,
PIM4_RdFIFO_Pop => net_gnd0,
PIM4_RdFIFO_RdWdAddr => open,
PIM4_WrFIFO_Empty => open,
PIM4_WrFIFO_AlmostFull => open,
PIM4_WrFIFO_Flush => net_gnd0,
PIM4_RdFIFO_Empty => open,
PIM4_RdFIFO_Flush => net_gnd0,
PIM4_RdFIFO_Latency => open,
PIM4_InitDone => open,
PPC440MC4_MIMCReadNotWrite => net_gnd0,
PPC440MC4_MIMCAddress => net_gnd36,
PPC440MC4_MIMCAddressValid => net_gnd0,
PPC440MC4_MIMCWriteData => net_gnd128,
PPC440MC4_MIMCWriteDataValid => net_gnd0,
PPC440MC4_MIMCByteEnable => net_gnd16,
PPC440MC4_MIMCBankConflict => net_gnd0,
PPC440MC4_MIMCRowConflict => net_gnd0,
PPC440MC4_MCMIReadData => open,
PPC440MC4_MCMIReadDataValid => open,
PPC440MC4_MCMIReadDataErr => open,
PPC440MC4_MCMIAddrReadyToAccept => open,
VFBC4_Cmd_Clk => net_gnd0,
VFBC4_Cmd_Reset => net_gnd0,
VFBC4_Cmd_Data => net_gnd32(0 to 31),
VFBC4_Cmd_Write => net_gnd0,
VFBC4_Cmd_End => net_gnd0,
VFBC4_Cmd_Full => open,
VFBC4_Cmd_Almost_Full => open,
VFBC4_Cmd_Idle => open,
VFBC4_Wd_Clk => net_gnd0,
VFBC4_Wd_Reset => net_gnd0,
VFBC4_Wd_Write => net_gnd0,
VFBC4_Wd_End_Burst => net_gnd0,
VFBC4_Wd_Flush => net_gnd0,
VFBC4_Wd_Data => net_gnd32(0 to 31),
VFBC4_Wd_Data_BE => net_gnd4(0 to 3),
VFBC4_Wd_Full => open,
VFBC4_Wd_Almost_Full => open,
VFBC4_Rd_Clk => net_gnd0,
VFBC4_Rd_Reset => net_gnd0,
VFBC4_Rd_Read => net_gnd0,
VFBC4_Rd_End_Burst => net_gnd0,
VFBC4_Rd_Flush => net_gnd0,
VFBC4_Rd_Data => open,
VFBC4_Rd_Empty => open,
VFBC4_Rd_Almost_Empty => open,
MCB4_cmd_clk => net_gnd0,
MCB4_cmd_en => net_gnd0,
MCB4_cmd_instr => net_gnd3,
MCB4_cmd_bl => net_gnd6,
MCB4_cmd_byte_addr => net_gnd30,
MCB4_cmd_empty => open,
MCB4_cmd_full => open,
MCB4_wr_clk => net_gnd0,
MCB4_wr_en => net_gnd0,
MCB4_wr_mask => net_gnd8(0 to 7),
MCB4_wr_data => net_gnd64(0 to 63),
MCB4_wr_full => open,
MCB4_wr_empty => open,
MCB4_wr_count => open,
MCB4_wr_underrun => open,
MCB4_wr_error => open,
MCB4_rd_clk => net_gnd0,
MCB4_rd_en => net_gnd0,
MCB4_rd_data => open,
MCB4_rd_full => open,
MCB4_rd_empty => open,
MCB4_rd_count => open,
MCB4_rd_overflow => open,
MCB4_rd_error => open,
FSL5_M_Clk => net_vcc0,
FSL5_M_Write => net_gnd0,
FSL5_M_Data => net_gnd32,
FSL5_M_Control => net_gnd0,
FSL5_M_Full => open,
FSL5_S_Clk => net_gnd0,
FSL5_S_Read => net_gnd0,
FSL5_S_Data => open,
FSL5_S_Control => open,
FSL5_S_Exists => open,
FSL5_B_M_Clk => net_vcc0,
FSL5_B_M_Write => net_gnd0,
FSL5_B_M_Data => net_gnd32,
FSL5_B_M_Control => net_gnd0,
FSL5_B_M_Full => open,
FSL5_B_S_Clk => net_gnd0,
FSL5_B_S_Read => net_gnd0,
FSL5_B_S_Data => open,
FSL5_B_S_Control => open,
FSL5_B_S_Exists => open,
SPLB5_Clk => net_vcc0,
SPLB5_Rst => net_gnd0,
SPLB5_PLB_ABus => net_gnd32,
SPLB5_PLB_PAValid => net_gnd0,
SPLB5_PLB_SAValid => net_gnd0,
SPLB5_PLB_masterID => net_gnd1(0 downto 0),
SPLB5_PLB_RNW => net_gnd0,
SPLB5_PLB_BE => net_gnd8,
SPLB5_PLB_UABus => net_gnd32,
SPLB5_PLB_rdPrim => net_gnd0,
SPLB5_PLB_wrPrim => net_gnd0,
SPLB5_PLB_abort => net_gnd0,
SPLB5_PLB_busLock => net_gnd0,
SPLB5_PLB_MSize => net_gnd2,
SPLB5_PLB_size => net_gnd4,
SPLB5_PLB_type => net_gnd3(2 downto 0),
SPLB5_PLB_lockErr => net_gnd0,
SPLB5_PLB_wrPendReq => net_gnd0,
SPLB5_PLB_wrPendPri => net_gnd2,
SPLB5_PLB_rdPendReq => net_gnd0,
SPLB5_PLB_rdPendPri => net_gnd2,
SPLB5_PLB_reqPri => net_gnd2,
SPLB5_PLB_TAttribute => net_gnd16,
SPLB5_PLB_rdBurst => net_gnd0,
SPLB5_PLB_wrBurst => net_gnd0,
SPLB5_PLB_wrDBus => net_gnd64,
SPLB5_Sl_addrAck => open,
SPLB5_Sl_SSize => open,
SPLB5_Sl_wait => open,
SPLB5_Sl_rearbitrate => open,
SPLB5_Sl_wrDAck => open,
SPLB5_Sl_wrComp => open,
SPLB5_Sl_wrBTerm => open,
SPLB5_Sl_rdDBus => open,
SPLB5_Sl_rdWdAddr => open,
SPLB5_Sl_rdDAck => open,
SPLB5_Sl_rdComp => open,
SPLB5_Sl_rdBTerm => open,
SPLB5_Sl_MBusy => open,
SPLB5_Sl_MRdErr => open,
SPLB5_Sl_MWrErr => open,
SPLB5_Sl_MIRQ => open,
SDMA5_Clk => net_gnd0,
SDMA5_Rx_IntOut => open,
SDMA5_Tx_IntOut => open,
SDMA5_RstOut => open,
SDMA5_TX_D => open,
SDMA5_TX_Rem => open,
SDMA5_TX_SOF => open,
SDMA5_TX_EOF => open,
SDMA5_TX_SOP => open,
SDMA5_TX_EOP => open,
SDMA5_TX_Src_Rdy => open,
SDMA5_TX_Dst_Rdy => net_vcc0,
SDMA5_RX_D => net_gnd32,
SDMA5_RX_Rem => net_vcc4,
SDMA5_RX_SOF => net_vcc0,
SDMA5_RX_EOF => net_vcc0,
SDMA5_RX_SOP => net_vcc0,
SDMA5_RX_EOP => net_vcc0,
SDMA5_RX_Src_Rdy => net_vcc0,
SDMA5_RX_Dst_Rdy => open,
SDMA_CTRL5_Clk => net_vcc0,
SDMA_CTRL5_Rst => net_gnd0,
SDMA_CTRL5_PLB_ABus => net_gnd32,
SDMA_CTRL5_PLB_PAValid => net_gnd0,
SDMA_CTRL5_PLB_SAValid => net_gnd0,
SDMA_CTRL5_PLB_masterID => net_gnd1(0 downto 0),
SDMA_CTRL5_PLB_RNW => net_gnd0,
SDMA_CTRL5_PLB_BE => net_gnd8,
SDMA_CTRL5_PLB_UABus => net_gnd32,
SDMA_CTRL5_PLB_rdPrim => net_gnd0,
SDMA_CTRL5_PLB_wrPrim => net_gnd0,
SDMA_CTRL5_PLB_abort => net_gnd0,
SDMA_CTRL5_PLB_busLock => net_gnd0,
SDMA_CTRL5_PLB_MSize => net_gnd2,
SDMA_CTRL5_PLB_size => net_gnd4,
SDMA_CTRL5_PLB_type => net_gnd3(2 downto 0),
SDMA_CTRL5_PLB_lockErr => net_gnd0,
SDMA_CTRL5_PLB_wrPendReq => net_gnd0,
SDMA_CTRL5_PLB_wrPendPri => net_gnd2,
SDMA_CTRL5_PLB_rdPendReq => net_gnd0,
SDMA_CTRL5_PLB_rdPendPri => net_gnd2,
SDMA_CTRL5_PLB_reqPri => net_gnd2,
SDMA_CTRL5_PLB_TAttribute => net_gnd16,
SDMA_CTRL5_PLB_rdBurst => net_gnd0,
SDMA_CTRL5_PLB_wrBurst => net_gnd0,
SDMA_CTRL5_PLB_wrDBus => net_gnd64,
SDMA_CTRL5_Sl_addrAck => open,
SDMA_CTRL5_Sl_SSize => open,
SDMA_CTRL5_Sl_wait => open,
SDMA_CTRL5_Sl_rearbitrate => open,
SDMA_CTRL5_Sl_wrDAck => open,
SDMA_CTRL5_Sl_wrComp => open,
SDMA_CTRL5_Sl_wrBTerm => open,
SDMA_CTRL5_Sl_rdDBus => open,
SDMA_CTRL5_Sl_rdWdAddr => open,
SDMA_CTRL5_Sl_rdDAck => open,
SDMA_CTRL5_Sl_rdComp => open,
SDMA_CTRL5_Sl_rdBTerm => open,
SDMA_CTRL5_Sl_MBusy => open,
SDMA_CTRL5_Sl_MRdErr => open,
SDMA_CTRL5_Sl_MWrErr => open,
SDMA_CTRL5_Sl_MIRQ => open,
PIM5_Addr => net_gnd32(0 to 31),
PIM5_AddrReq => net_gnd0,
PIM5_AddrAck => open,
PIM5_RNW => net_gnd0,
PIM5_Size => net_gnd4(0 to 3),
PIM5_RdModWr => net_gnd0,
PIM5_WrFIFO_Data => net_gnd64(0 to 63),
PIM5_WrFIFO_BE => net_gnd8(0 to 7),
PIM5_WrFIFO_Push => net_gnd0,
PIM5_RdFIFO_Data => open,
PIM5_RdFIFO_Pop => net_gnd0,
PIM5_RdFIFO_RdWdAddr => open,
PIM5_WrFIFO_Empty => open,
PIM5_WrFIFO_AlmostFull => open,
PIM5_WrFIFO_Flush => net_gnd0,
PIM5_RdFIFO_Empty => open,
PIM5_RdFIFO_Flush => net_gnd0,
PIM5_RdFIFO_Latency => open,
PIM5_InitDone => open,
PPC440MC5_MIMCReadNotWrite => net_gnd0,
PPC440MC5_MIMCAddress => net_gnd36,
PPC440MC5_MIMCAddressValid => net_gnd0,
PPC440MC5_MIMCWriteData => net_gnd128,
PPC440MC5_MIMCWriteDataValid => net_gnd0,
PPC440MC5_MIMCByteEnable => net_gnd16,
PPC440MC5_MIMCBankConflict => net_gnd0,
PPC440MC5_MIMCRowConflict => net_gnd0,
PPC440MC5_MCMIReadData => open,
PPC440MC5_MCMIReadDataValid => open,
PPC440MC5_MCMIReadDataErr => open,
PPC440MC5_MCMIAddrReadyToAccept => open,
VFBC5_Cmd_Clk => net_gnd0,
VFBC5_Cmd_Reset => net_gnd0,
VFBC5_Cmd_Data => net_gnd32(0 to 31),
VFBC5_Cmd_Write => net_gnd0,
VFBC5_Cmd_End => net_gnd0,
VFBC5_Cmd_Full => open,
VFBC5_Cmd_Almost_Full => open,
VFBC5_Cmd_Idle => open,
VFBC5_Wd_Clk => net_gnd0,
VFBC5_Wd_Reset => net_gnd0,
VFBC5_Wd_Write => net_gnd0,
VFBC5_Wd_End_Burst => net_gnd0,
VFBC5_Wd_Flush => net_gnd0,
VFBC5_Wd_Data => net_gnd32(0 to 31),
VFBC5_Wd_Data_BE => net_gnd4(0 to 3),
VFBC5_Wd_Full => open,
VFBC5_Wd_Almost_Full => open,
VFBC5_Rd_Clk => net_gnd0,
VFBC5_Rd_Reset => net_gnd0,
VFBC5_Rd_Read => net_gnd0,
VFBC5_Rd_End_Burst => net_gnd0,
VFBC5_Rd_Flush => net_gnd0,
VFBC5_Rd_Data => open,
VFBC5_Rd_Empty => open,
VFBC5_Rd_Almost_Empty => open,
MCB5_cmd_clk => net_gnd0,
MCB5_cmd_en => net_gnd0,
MCB5_cmd_instr => net_gnd3,
MCB5_cmd_bl => net_gnd6,
MCB5_cmd_byte_addr => net_gnd30,
MCB5_cmd_empty => open,
MCB5_cmd_full => open,
MCB5_wr_clk => net_gnd0,
MCB5_wr_en => net_gnd0,
MCB5_wr_mask => net_gnd8(0 to 7),
MCB5_wr_data => net_gnd64(0 to 63),
MCB5_wr_full => open,
MCB5_wr_empty => open,
MCB5_wr_count => open,
MCB5_wr_underrun => open,
MCB5_wr_error => open,
MCB5_rd_clk => net_gnd0,
MCB5_rd_en => net_gnd0,
MCB5_rd_data => open,
MCB5_rd_full => open,
MCB5_rd_empty => open,
MCB5_rd_count => open,
MCB5_rd_overflow => open,
MCB5_rd_error => open,
FSL6_M_Clk => net_vcc0,
FSL6_M_Write => net_gnd0,
FSL6_M_Data => net_gnd32,
FSL6_M_Control => net_gnd0,
FSL6_M_Full => open,
FSL6_S_Clk => net_gnd0,
FSL6_S_Read => net_gnd0,
FSL6_S_Data => open,
FSL6_S_Control => open,
FSL6_S_Exists => open,
FSL6_B_M_Clk => net_vcc0,
FSL6_B_M_Write => net_gnd0,
FSL6_B_M_Data => net_gnd32,
FSL6_B_M_Control => net_gnd0,
FSL6_B_M_Full => open,
FSL6_B_S_Clk => net_gnd0,
FSL6_B_S_Read => net_gnd0,
FSL6_B_S_Data => open,
FSL6_B_S_Control => open,
FSL6_B_S_Exists => open,
SPLB6_Clk => net_vcc0,
SPLB6_Rst => net_gnd0,
SPLB6_PLB_ABus => net_gnd32,
SPLB6_PLB_PAValid => net_gnd0,
SPLB6_PLB_SAValid => net_gnd0,
SPLB6_PLB_masterID => net_gnd1(0 downto 0),
SPLB6_PLB_RNW => net_gnd0,
SPLB6_PLB_BE => net_gnd8,
SPLB6_PLB_UABus => net_gnd32,
SPLB6_PLB_rdPrim => net_gnd0,
SPLB6_PLB_wrPrim => net_gnd0,
SPLB6_PLB_abort => net_gnd0,
SPLB6_PLB_busLock => net_gnd0,
SPLB6_PLB_MSize => net_gnd2,
SPLB6_PLB_size => net_gnd4,
SPLB6_PLB_type => net_gnd3(2 downto 0),
SPLB6_PLB_lockErr => net_gnd0,
SPLB6_PLB_wrPendReq => net_gnd0,
SPLB6_PLB_wrPendPri => net_gnd2,
SPLB6_PLB_rdPendReq => net_gnd0,
SPLB6_PLB_rdPendPri => net_gnd2,
SPLB6_PLB_reqPri => net_gnd2,
SPLB6_PLB_TAttribute => net_gnd16,
SPLB6_PLB_rdBurst => net_gnd0,
SPLB6_PLB_wrBurst => net_gnd0,
SPLB6_PLB_wrDBus => net_gnd64,
SPLB6_Sl_addrAck => open,
SPLB6_Sl_SSize => open,
SPLB6_Sl_wait => open,
SPLB6_Sl_rearbitrate => open,
SPLB6_Sl_wrDAck => open,
SPLB6_Sl_wrComp => open,
SPLB6_Sl_wrBTerm => open,
SPLB6_Sl_rdDBus => open,
SPLB6_Sl_rdWdAddr => open,
SPLB6_Sl_rdDAck => open,
SPLB6_Sl_rdComp => open,
SPLB6_Sl_rdBTerm => open,
SPLB6_Sl_MBusy => open,
SPLB6_Sl_MRdErr => open,
SPLB6_Sl_MWrErr => open,
SPLB6_Sl_MIRQ => open,
SDMA6_Clk => net_gnd0,
SDMA6_Rx_IntOut => open,
SDMA6_Tx_IntOut => open,
SDMA6_RstOut => open,
SDMA6_TX_D => open,
SDMA6_TX_Rem => open,
SDMA6_TX_SOF => open,
SDMA6_TX_EOF => open,
SDMA6_TX_SOP => open,
SDMA6_TX_EOP => open,
SDMA6_TX_Src_Rdy => open,
SDMA6_TX_Dst_Rdy => net_vcc0,
SDMA6_RX_D => net_gnd32,
SDMA6_RX_Rem => net_vcc4,
SDMA6_RX_SOF => net_vcc0,
SDMA6_RX_EOF => net_vcc0,
SDMA6_RX_SOP => net_vcc0,
SDMA6_RX_EOP => net_vcc0,
SDMA6_RX_Src_Rdy => net_vcc0,
SDMA6_RX_Dst_Rdy => open,
SDMA_CTRL6_Clk => net_vcc0,
SDMA_CTRL6_Rst => net_gnd0,
SDMA_CTRL6_PLB_ABus => net_gnd32,
SDMA_CTRL6_PLB_PAValid => net_gnd0,
SDMA_CTRL6_PLB_SAValid => net_gnd0,
SDMA_CTRL6_PLB_masterID => net_gnd1(0 downto 0),
SDMA_CTRL6_PLB_RNW => net_gnd0,
SDMA_CTRL6_PLB_BE => net_gnd8,
SDMA_CTRL6_PLB_UABus => net_gnd32,
SDMA_CTRL6_PLB_rdPrim => net_gnd0,
SDMA_CTRL6_PLB_wrPrim => net_gnd0,
SDMA_CTRL6_PLB_abort => net_gnd0,
SDMA_CTRL6_PLB_busLock => net_gnd0,
SDMA_CTRL6_PLB_MSize => net_gnd2,
SDMA_CTRL6_PLB_size => net_gnd4,
SDMA_CTRL6_PLB_type => net_gnd3(2 downto 0),
SDMA_CTRL6_PLB_lockErr => net_gnd0,
SDMA_CTRL6_PLB_wrPendReq => net_gnd0,
SDMA_CTRL6_PLB_wrPendPri => net_gnd2,
SDMA_CTRL6_PLB_rdPendReq => net_gnd0,
SDMA_CTRL6_PLB_rdPendPri => net_gnd2,
SDMA_CTRL6_PLB_reqPri => net_gnd2,
SDMA_CTRL6_PLB_TAttribute => net_gnd16,
SDMA_CTRL6_PLB_rdBurst => net_gnd0,
SDMA_CTRL6_PLB_wrBurst => net_gnd0,
SDMA_CTRL6_PLB_wrDBus => net_gnd64,
SDMA_CTRL6_Sl_addrAck => open,
SDMA_CTRL6_Sl_SSize => open,
SDMA_CTRL6_Sl_wait => open,
SDMA_CTRL6_Sl_rearbitrate => open,
SDMA_CTRL6_Sl_wrDAck => open,
SDMA_CTRL6_Sl_wrComp => open,
SDMA_CTRL6_Sl_wrBTerm => open,
SDMA_CTRL6_Sl_rdDBus => open,
SDMA_CTRL6_Sl_rdWdAddr => open,
SDMA_CTRL6_Sl_rdDAck => open,
SDMA_CTRL6_Sl_rdComp => open,
SDMA_CTRL6_Sl_rdBTerm => open,
SDMA_CTRL6_Sl_MBusy => open,
SDMA_CTRL6_Sl_MRdErr => open,
SDMA_CTRL6_Sl_MWrErr => open,
SDMA_CTRL6_Sl_MIRQ => open,
PIM6_Addr => net_gnd32(0 to 31),
PIM6_AddrReq => net_gnd0,
PIM6_AddrAck => open,
PIM6_RNW => net_gnd0,
PIM6_Size => net_gnd4(0 to 3),
PIM6_RdModWr => net_gnd0,
PIM6_WrFIFO_Data => net_gnd64(0 to 63),
PIM6_WrFIFO_BE => net_gnd8(0 to 7),
PIM6_WrFIFO_Push => net_gnd0,
PIM6_RdFIFO_Data => open,
PIM6_RdFIFO_Pop => net_gnd0,
PIM6_RdFIFO_RdWdAddr => open,
PIM6_WrFIFO_Empty => open,
PIM6_WrFIFO_AlmostFull => open,
PIM6_WrFIFO_Flush => net_gnd0,
PIM6_RdFIFO_Empty => open,
PIM6_RdFIFO_Flush => net_gnd0,
PIM6_RdFIFO_Latency => open,
PIM6_InitDone => open,
PPC440MC6_MIMCReadNotWrite => net_gnd0,
PPC440MC6_MIMCAddress => net_gnd36,
PPC440MC6_MIMCAddressValid => net_gnd0,
PPC440MC6_MIMCWriteData => net_gnd128,
PPC440MC6_MIMCWriteDataValid => net_gnd0,
PPC440MC6_MIMCByteEnable => net_gnd16,
PPC440MC6_MIMCBankConflict => net_gnd0,
PPC440MC6_MIMCRowConflict => net_gnd0,
PPC440MC6_MCMIReadData => open,
PPC440MC6_MCMIReadDataValid => open,
PPC440MC6_MCMIReadDataErr => open,
PPC440MC6_MCMIAddrReadyToAccept => open,
VFBC6_Cmd_Clk => net_gnd0,
VFBC6_Cmd_Reset => net_gnd0,
VFBC6_Cmd_Data => net_gnd32(0 to 31),
VFBC6_Cmd_Write => net_gnd0,
VFBC6_Cmd_End => net_gnd0,
VFBC6_Cmd_Full => open,
VFBC6_Cmd_Almost_Full => open,
VFBC6_Cmd_Idle => open,
VFBC6_Wd_Clk => net_gnd0,
VFBC6_Wd_Reset => net_gnd0,
VFBC6_Wd_Write => net_gnd0,
VFBC6_Wd_End_Burst => net_gnd0,
VFBC6_Wd_Flush => net_gnd0,
VFBC6_Wd_Data => net_gnd32(0 to 31),
VFBC6_Wd_Data_BE => net_gnd4(0 to 3),
VFBC6_Wd_Full => open,
VFBC6_Wd_Almost_Full => open,
VFBC6_Rd_Clk => net_gnd0,
VFBC6_Rd_Reset => net_gnd0,
VFBC6_Rd_Read => net_gnd0,
VFBC6_Rd_End_Burst => net_gnd0,
VFBC6_Rd_Flush => net_gnd0,
VFBC6_Rd_Data => open,
VFBC6_Rd_Empty => open,
VFBC6_Rd_Almost_Empty => open,
MCB6_cmd_clk => net_gnd0,
MCB6_cmd_en => net_gnd0,
MCB6_cmd_instr => net_gnd3,
MCB6_cmd_bl => net_gnd6,
MCB6_cmd_byte_addr => net_gnd30,
MCB6_cmd_empty => open,
MCB6_cmd_full => open,
MCB6_wr_clk => net_gnd0,
MCB6_wr_en => net_gnd0,
MCB6_wr_mask => net_gnd8(0 to 7),
MCB6_wr_data => net_gnd64(0 to 63),
MCB6_wr_full => open,
MCB6_wr_empty => open,
MCB6_wr_count => open,
MCB6_wr_underrun => open,
MCB6_wr_error => open,
MCB6_rd_clk => net_gnd0,
MCB6_rd_en => net_gnd0,
MCB6_rd_data => open,
MCB6_rd_full => open,
MCB6_rd_empty => open,
MCB6_rd_count => open,
MCB6_rd_overflow => open,
MCB6_rd_error => open,
FSL7_M_Clk => net_vcc0,
FSL7_M_Write => net_gnd0,
FSL7_M_Data => net_gnd32,
FSL7_M_Control => net_gnd0,
FSL7_M_Full => open,
FSL7_S_Clk => net_gnd0,
FSL7_S_Read => net_gnd0,
FSL7_S_Data => open,
FSL7_S_Control => open,
FSL7_S_Exists => open,
FSL7_B_M_Clk => net_vcc0,
FSL7_B_M_Write => net_gnd0,
FSL7_B_M_Data => net_gnd32,
FSL7_B_M_Control => net_gnd0,
FSL7_B_M_Full => open,
FSL7_B_S_Clk => net_gnd0,
FSL7_B_S_Read => net_gnd0,
FSL7_B_S_Data => open,
FSL7_B_S_Control => open,
FSL7_B_S_Exists => open,
SPLB7_Clk => net_vcc0,
SPLB7_Rst => net_gnd0,
SPLB7_PLB_ABus => net_gnd32,
SPLB7_PLB_PAValid => net_gnd0,
SPLB7_PLB_SAValid => net_gnd0,
SPLB7_PLB_masterID => net_gnd1(0 downto 0),
SPLB7_PLB_RNW => net_gnd0,
SPLB7_PLB_BE => net_gnd8,
SPLB7_PLB_UABus => net_gnd32,
SPLB7_PLB_rdPrim => net_gnd0,
SPLB7_PLB_wrPrim => net_gnd0,
SPLB7_PLB_abort => net_gnd0,
SPLB7_PLB_busLock => net_gnd0,
SPLB7_PLB_MSize => net_gnd2,
SPLB7_PLB_size => net_gnd4,
SPLB7_PLB_type => net_gnd3(2 downto 0),
SPLB7_PLB_lockErr => net_gnd0,
SPLB7_PLB_wrPendReq => net_gnd0,
SPLB7_PLB_wrPendPri => net_gnd2,
SPLB7_PLB_rdPendReq => net_gnd0,
SPLB7_PLB_rdPendPri => net_gnd2,
SPLB7_PLB_reqPri => net_gnd2,
SPLB7_PLB_TAttribute => net_gnd16,
SPLB7_PLB_rdBurst => net_gnd0,
SPLB7_PLB_wrBurst => net_gnd0,
SPLB7_PLB_wrDBus => net_gnd64,
SPLB7_Sl_addrAck => open,
SPLB7_Sl_SSize => open,
SPLB7_Sl_wait => open,
SPLB7_Sl_rearbitrate => open,
SPLB7_Sl_wrDAck => open,
SPLB7_Sl_wrComp => open,
SPLB7_Sl_wrBTerm => open,
SPLB7_Sl_rdDBus => open,
SPLB7_Sl_rdWdAddr => open,
SPLB7_Sl_rdDAck => open,
SPLB7_Sl_rdComp => open,
SPLB7_Sl_rdBTerm => open,
SPLB7_Sl_MBusy => open,
SPLB7_Sl_MRdErr => open,
SPLB7_Sl_MWrErr => open,
SPLB7_Sl_MIRQ => open,
SDMA7_Clk => net_gnd0,
SDMA7_Rx_IntOut => open,
SDMA7_Tx_IntOut => open,
SDMA7_RstOut => open,
SDMA7_TX_D => open,
SDMA7_TX_Rem => open,
SDMA7_TX_SOF => open,
SDMA7_TX_EOF => open,
SDMA7_TX_SOP => open,
SDMA7_TX_EOP => open,
SDMA7_TX_Src_Rdy => open,
SDMA7_TX_Dst_Rdy => net_vcc0,
SDMA7_RX_D => net_gnd32,
SDMA7_RX_Rem => net_vcc4,
SDMA7_RX_SOF => net_vcc0,
SDMA7_RX_EOF => net_vcc0,
SDMA7_RX_SOP => net_vcc0,
SDMA7_RX_EOP => net_vcc0,
SDMA7_RX_Src_Rdy => net_vcc0,
SDMA7_RX_Dst_Rdy => open,
SDMA_CTRL7_Clk => net_vcc0,
SDMA_CTRL7_Rst => net_gnd0,
SDMA_CTRL7_PLB_ABus => net_gnd32,
SDMA_CTRL7_PLB_PAValid => net_gnd0,
SDMA_CTRL7_PLB_SAValid => net_gnd0,
SDMA_CTRL7_PLB_masterID => net_gnd1(0 downto 0),
SDMA_CTRL7_PLB_RNW => net_gnd0,
SDMA_CTRL7_PLB_BE => net_gnd8,
SDMA_CTRL7_PLB_UABus => net_gnd32,
SDMA_CTRL7_PLB_rdPrim => net_gnd0,
SDMA_CTRL7_PLB_wrPrim => net_gnd0,
SDMA_CTRL7_PLB_abort => net_gnd0,
SDMA_CTRL7_PLB_busLock => net_gnd0,
SDMA_CTRL7_PLB_MSize => net_gnd2,
SDMA_CTRL7_PLB_size => net_gnd4,
SDMA_CTRL7_PLB_type => net_gnd3(2 downto 0),
SDMA_CTRL7_PLB_lockErr => net_gnd0,
SDMA_CTRL7_PLB_wrPendReq => net_gnd0,
SDMA_CTRL7_PLB_wrPendPri => net_gnd2,
SDMA_CTRL7_PLB_rdPendReq => net_gnd0,
SDMA_CTRL7_PLB_rdPendPri => net_gnd2,
SDMA_CTRL7_PLB_reqPri => net_gnd2,
SDMA_CTRL7_PLB_TAttribute => net_gnd16,
SDMA_CTRL7_PLB_rdBurst => net_gnd0,
SDMA_CTRL7_PLB_wrBurst => net_gnd0,
SDMA_CTRL7_PLB_wrDBus => net_gnd64,
SDMA_CTRL7_Sl_addrAck => open,
SDMA_CTRL7_Sl_SSize => open,
SDMA_CTRL7_Sl_wait => open,
SDMA_CTRL7_Sl_rearbitrate => open,
SDMA_CTRL7_Sl_wrDAck => open,
SDMA_CTRL7_Sl_wrComp => open,
SDMA_CTRL7_Sl_wrBTerm => open,
SDMA_CTRL7_Sl_rdDBus => open,
SDMA_CTRL7_Sl_rdWdAddr => open,
SDMA_CTRL7_Sl_rdDAck => open,
SDMA_CTRL7_Sl_rdComp => open,
SDMA_CTRL7_Sl_rdBTerm => open,
SDMA_CTRL7_Sl_MBusy => open,
SDMA_CTRL7_Sl_MRdErr => open,
SDMA_CTRL7_Sl_MWrErr => open,
SDMA_CTRL7_Sl_MIRQ => open,
PIM7_Addr => net_gnd32(0 to 31),
PIM7_AddrReq => net_gnd0,
PIM7_AddrAck => open,
PIM7_RNW => net_gnd0,
PIM7_Size => net_gnd4(0 to 3),
PIM7_RdModWr => net_gnd0,
PIM7_WrFIFO_Data => net_gnd64(0 to 63),
PIM7_WrFIFO_BE => net_gnd8(0 to 7),
PIM7_WrFIFO_Push => net_gnd0,
PIM7_RdFIFO_Data => open,
PIM7_RdFIFO_Pop => net_gnd0,
PIM7_RdFIFO_RdWdAddr => open,
PIM7_WrFIFO_Empty => open,
PIM7_WrFIFO_AlmostFull => open,
PIM7_WrFIFO_Flush => net_gnd0,
PIM7_RdFIFO_Empty => open,
PIM7_RdFIFO_Flush => net_gnd0,
PIM7_RdFIFO_Latency => open,
PIM7_InitDone => open,
PPC440MC7_MIMCReadNotWrite => net_gnd0,
PPC440MC7_MIMCAddress => net_gnd36,
PPC440MC7_MIMCAddressValid => net_gnd0,
PPC440MC7_MIMCWriteData => net_gnd128,
PPC440MC7_MIMCWriteDataValid => net_gnd0,
PPC440MC7_MIMCByteEnable => net_gnd16,
PPC440MC7_MIMCBankConflict => net_gnd0,
PPC440MC7_MIMCRowConflict => net_gnd0,
PPC440MC7_MCMIReadData => open,
PPC440MC7_MCMIReadDataValid => open,
PPC440MC7_MCMIReadDataErr => open,
PPC440MC7_MCMIAddrReadyToAccept => open,
VFBC7_Cmd_Clk => net_gnd0,
VFBC7_Cmd_Reset => net_gnd0,
VFBC7_Cmd_Data => net_gnd32(0 to 31),
VFBC7_Cmd_Write => net_gnd0,
VFBC7_Cmd_End => net_gnd0,
VFBC7_Cmd_Full => open,
VFBC7_Cmd_Almost_Full => open,
VFBC7_Cmd_Idle => open,
VFBC7_Wd_Clk => net_gnd0,
VFBC7_Wd_Reset => net_gnd0,
VFBC7_Wd_Write => net_gnd0,
VFBC7_Wd_End_Burst => net_gnd0,
VFBC7_Wd_Flush => net_gnd0,
VFBC7_Wd_Data => net_gnd32(0 to 31),
VFBC7_Wd_Data_BE => net_gnd4(0 to 3),
VFBC7_Wd_Full => open,
VFBC7_Wd_Almost_Full => open,
VFBC7_Rd_Clk => net_gnd0,
VFBC7_Rd_Reset => net_gnd0,
VFBC7_Rd_Read => net_gnd0,
VFBC7_Rd_End_Burst => net_gnd0,
VFBC7_Rd_Flush => net_gnd0,
VFBC7_Rd_Data => open,
VFBC7_Rd_Empty => open,
VFBC7_Rd_Almost_Empty => open,
MCB7_cmd_clk => net_gnd0,
MCB7_cmd_en => net_gnd0,
MCB7_cmd_instr => net_gnd3,
MCB7_cmd_bl => net_gnd6,
MCB7_cmd_byte_addr => net_gnd30,
MCB7_cmd_empty => open,
MCB7_cmd_full => open,
MCB7_wr_clk => net_gnd0,
MCB7_wr_en => net_gnd0,
MCB7_wr_mask => net_gnd8(0 to 7),
MCB7_wr_data => net_gnd64(0 to 63),
MCB7_wr_full => open,
MCB7_wr_empty => open,
MCB7_wr_count => open,
MCB7_wr_underrun => open,
MCB7_wr_error => open,
MCB7_rd_clk => net_gnd0,
MCB7_rd_en => net_gnd0,
MCB7_rd_data => open,
MCB7_rd_full => open,
MCB7_rd_empty => open,
MCB7_rd_count => open,
MCB7_rd_overflow => open,
MCB7_rd_error => open,
MPMC_CTRL_Clk => net_vcc0,
MPMC_CTRL_Rst => net_gnd0,
MPMC_CTRL_PLB_ABus => net_gnd32,
MPMC_CTRL_PLB_PAValid => net_gnd0,
MPMC_CTRL_PLB_SAValid => net_gnd0,
MPMC_CTRL_PLB_masterID => net_gnd1(0 downto 0),
MPMC_CTRL_PLB_RNW => net_gnd0,
MPMC_CTRL_PLB_BE => net_gnd8,
MPMC_CTRL_PLB_UABus => net_gnd32,
MPMC_CTRL_PLB_rdPrim => net_gnd0,
MPMC_CTRL_PLB_wrPrim => net_gnd0,
MPMC_CTRL_PLB_abort => net_gnd0,
MPMC_CTRL_PLB_busLock => net_gnd0,
MPMC_CTRL_PLB_MSize => net_gnd2,
MPMC_CTRL_PLB_size => net_gnd4,
MPMC_CTRL_PLB_type => net_gnd3(2 downto 0),
MPMC_CTRL_PLB_lockErr => net_gnd0,
MPMC_CTRL_PLB_wrPendReq => net_gnd0,
MPMC_CTRL_PLB_wrPendPri => net_gnd2,
MPMC_CTRL_PLB_rdPendReq => net_gnd0,
MPMC_CTRL_PLB_rdPendPri => net_gnd2,
MPMC_CTRL_PLB_reqPri => net_gnd2,
MPMC_CTRL_PLB_TAttribute => net_gnd16,
MPMC_CTRL_PLB_rdBurst => net_gnd0,
MPMC_CTRL_PLB_wrBurst => net_gnd0,
MPMC_CTRL_PLB_wrDBus => net_gnd64,
MPMC_CTRL_Sl_addrAck => open,
MPMC_CTRL_Sl_SSize => open,
MPMC_CTRL_Sl_wait => open,
MPMC_CTRL_Sl_rearbitrate => open,
MPMC_CTRL_Sl_wrDAck => open,
MPMC_CTRL_Sl_wrComp => open,
MPMC_CTRL_Sl_wrBTerm => open,
MPMC_CTRL_Sl_rdDBus => open,
MPMC_CTRL_Sl_rdWdAddr => open,
MPMC_CTRL_Sl_rdDAck => open,
MPMC_CTRL_Sl_rdComp => open,
MPMC_CTRL_Sl_rdBTerm => open,
MPMC_CTRL_Sl_MBusy => open,
MPMC_CTRL_Sl_MRdErr => open,
MPMC_CTRL_Sl_MWrErr => open,
MPMC_CTRL_Sl_MIRQ => open,
MPMC_Clk0 => clk_125_0000MHzPLL0,
MPMC_Clk0_DIV2 => clk_62_5000MHzPLL0,
MPMC_Clk90 => clk_125_0000MHz90PLL0,
MPMC_Clk_200MHz => clk_200_0000MHz,
MPMC_Rst => sys_periph_reset(0),
MPMC_Clk_Mem => net_vcc0,
MPMC_Clk_Mem_2x => net_vcc0,
MPMC_Clk_Mem_2x_180 => net_vcc0,
MPMC_Clk_Mem_2x_CE0 => net_vcc0,
MPMC_Clk_Mem_2x_CE90 => net_vcc0,
MPMC_Clk_Rd_Base => net_vcc0,
MPMC_Clk_Mem_2x_bufpll_o => open,
MPMC_Clk_Mem_2x_180_bufpll_o => open,
MPMC_Clk_Mem_2x_CE0_bufpll_o => open,
MPMC_Clk_Mem_2x_CE90_bufpll_o => open,
MPMC_PLL_Lock_bufpll_o => open,
MPMC_PLL_Lock => net_gnd0,
MPMC_Idelayctrl_Rdy_I => net_vcc0,
MPMC_Idelayctrl_Rdy_O => open,
MPMC_InitDone => open,
MPMC_ECC_Intr => open,
MPMC_DCM_PSEN => open,
MPMC_DCM_PSINCDEC => open,
MPMC_DCM_PSDONE => net_gnd0,
MPMC_MCB_DRP_Clk => net_vcc0,
SDRAM_Clk => open,
SDRAM_CE => open,
SDRAM_CS_n => open,
SDRAM_RAS_n => open,
SDRAM_CAS_n => open,
SDRAM_WE_n => open,
SDRAM_BankAddr => open,
SDRAM_Addr => open,
SDRAM_DQ => open,
SDRAM_DM => open,
DDR_Clk => open,
DDR_Clk_n => open,
DDR_CE => open,
DDR_CS_n => open,
DDR_RAS_n => open,
DDR_CAS_n => open,
DDR_WE_n => open,
DDR_BankAddr => open,
DDR_Addr => open,
DDR_DQ => open,
DDR_DM => open,
DDR_DQS => open,
DDR_DQS_Div_O => open,
DDR_DQS_Div_I => net_gnd0,
DDR2_Clk => fpga_0_DDR2_SDRAM_DDR2_Clk_pin,
DDR2_Clk_n => fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin,
DDR2_CE => fpga_0_DDR2_SDRAM_DDR2_CE_pin,
DDR2_CS_n => fpga_0_DDR2_SDRAM_DDR2_CS_n_pin,
DDR2_ODT => fpga_0_DDR2_SDRAM_DDR2_ODT_pin,
DDR2_RAS_n => fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin,
DDR2_CAS_n => fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin,
DDR2_WE_n => fpga_0_DDR2_SDRAM_DDR2_WE_n_pin,
DDR2_BankAddr => fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin,
DDR2_Addr => fpga_0_DDR2_SDRAM_DDR2_Addr_pin,
DDR2_DQ => fpga_0_DDR2_SDRAM_DDR2_DQ_pin,
DDR2_DM => fpga_0_DDR2_SDRAM_DDR2_DM_pin,
DDR2_DQS => fpga_0_DDR2_SDRAM_DDR2_DQS_pin,
DDR2_DQS_n => fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin,
DDR2_DQS_Div_O => open,
DDR2_DQS_Div_I => net_gnd0,
DDR3_Clk => open,
DDR3_Clk_n => open,
DDR3_CE => open,
DDR3_CS_n => open,
DDR3_ODT => open,
DDR3_RAS_n => open,
DDR3_CAS_n => open,
DDR3_WE_n => open,
DDR3_BankAddr => open,
DDR3_Addr => open,
DDR3_DQ => open,
DDR3_DM => open,
DDR3_Reset_n => open,
DDR3_DQS => open,
DDR3_DQS_n => open,
mcbx_dram_addr => open,
mcbx_dram_ba => open,
mcbx_dram_ras_n => open,
mcbx_dram_cas_n => open,
mcbx_dram_we_n => open,
mcbx_dram_cke => open,
mcbx_dram_clk => open,
mcbx_dram_clk_n => open,
mcbx_dram_dq => open,
mcbx_dram_dqs => open,
mcbx_dram_dqs_n => open,
mcbx_dram_udqs => open,
mcbx_dram_udqs_n => open,
mcbx_dram_udm => open,
mcbx_dram_ldm => open,
mcbx_dram_odt => open,
mcbx_dram_ddr3_rst => open,
selfrefresh_enter => net_gnd0,
selfrefresh_mode => open,
calib_recal => net_gnd0,
rzq => open,
zio => open
);
SRAM : system_sram_wrapper
port map (
MCH_SPLB_Clk => clk_125_0000MHzPLL0,
RdClk => clk_125_0000MHzPLL0,
MCH_SPLB_Rst => mb_plb_SPLB_Rst(1),
MCH0_Access_Control => net_gnd0,
MCH0_Access_Data => net_gnd32,
MCH0_Access_Write => net_gnd0,
MCH0_Access_Full => open,
MCH0_ReadData_Control => open,
MCH0_ReadData_Data => open,
MCH0_ReadData_Read => net_gnd0,
MCH0_ReadData_Exists => open,
MCH1_Access_Control => net_gnd0,
MCH1_Access_Data => net_gnd32,
MCH1_Access_Write => net_gnd0,
MCH1_Access_Full => open,
MCH1_ReadData_Control => open,
MCH1_ReadData_Data => open,
MCH1_ReadData_Read => net_gnd0,
MCH1_ReadData_Exists => open,
MCH2_Access_Control => net_gnd0,
MCH2_Access_Data => net_gnd32,
MCH2_Access_Write => net_gnd0,
MCH2_Access_Full => open,
MCH2_ReadData_Control => open,
MCH2_ReadData_Data => open,
MCH2_ReadData_Read => net_gnd0,
MCH2_ReadData_Exists => open,
MCH3_Access_Control => net_gnd0,
MCH3_Access_Data => net_gnd32,
MCH3_Access_Write => net_gnd0,
MCH3_Access_Full => open,
MCH3_ReadData_Control => open,
MCH3_ReadData_Data => open,
MCH3_ReadData_Read => net_gnd0,
MCH3_ReadData_Exists => open,
PLB_ABus => mb_plb_PLB_ABus,
PLB_UABus => mb_plb_PLB_UABus,
PLB_PAValid => mb_plb_PLB_PAValid,
PLB_SAValid => mb_plb_PLB_SAValid,
PLB_rdPrim => mb_plb_PLB_rdPrim(1),
PLB_wrPrim => mb_plb_PLB_wrPrim(1),
PLB_masterID => mb_plb_PLB_masterID,
PLB_abort => mb_plb_PLB_abort,
PLB_busLock => mb_plb_PLB_busLock,
PLB_RNW => mb_plb_PLB_RNW,
PLB_BE => mb_plb_PLB_BE,
PLB_MSize => mb_plb_PLB_MSize,
PLB_size => mb_plb_PLB_size,
PLB_type => mb_plb_PLB_type,
PLB_lockErr => mb_plb_PLB_lockErr,
PLB_wrDBus => mb_plb_PLB_wrDBus,
PLB_wrBurst => mb_plb_PLB_wrBurst,
PLB_rdBurst => mb_plb_PLB_rdBurst,
PLB_wrPendReq => mb_plb_PLB_wrPendReq,
PLB_rdPendReq => mb_plb_PLB_rdPendReq,
PLB_wrPendPri => mb_plb_PLB_wrPendPri,
PLB_rdPendPri => mb_plb_PLB_rdPendPri,
PLB_reqPri => mb_plb_PLB_reqPri,
PLB_TAttribute => mb_plb_PLB_TAttribute,
Sl_addrAck => mb_plb_Sl_addrAck(1),
Sl_SSize => mb_plb_Sl_SSize(2 to 3),
Sl_wait => mb_plb_Sl_wait(1),
Sl_rearbitrate => mb_plb_Sl_rearbitrate(1),
Sl_wrDAck => mb_plb_Sl_wrDAck(1),
Sl_wrComp => mb_plb_Sl_wrComp(1),
Sl_wrBTerm => mb_plb_Sl_wrBTerm(1),
Sl_rdDBus => mb_plb_Sl_rdDBus(64 to 127),
Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(4 to 7),
Sl_rdDAck => mb_plb_Sl_rdDAck(1),
Sl_rdComp => mb_plb_Sl_rdComp(1),
Sl_rdBTerm => mb_plb_Sl_rdBTerm(1),
Sl_MBusy => mb_plb_Sl_MBusy(6 to 11),
Sl_MWrErr => mb_plb_Sl_MWrErr(6 to 11),
Sl_MRdErr => mb_plb_Sl_MRdErr(6 to 11),
Sl_MIRQ => mb_plb_Sl_MIRQ(6 to 11),
Mem_DQ_I => fpga_0_SRAM_Mem_DQ_pin_I,
Mem_DQ_O => fpga_0_SRAM_Mem_DQ_pin_O,
Mem_DQ_T => fpga_0_SRAM_Mem_DQ_pin_T,
Mem_A => pgassign9,
Mem_RPN => open,
Mem_CEN => pgassign1(0 to 0),
Mem_OEN => pgassign2(0 to 0),
Mem_WEN => fpga_0_SRAM_Mem_WEN_pin,
Mem_QWEN => open,
Mem_BEN => fpga_0_SRAM_Mem_BEN_pin,
Mem_CE => open,
Mem_ADV_LDN => fpga_0_SRAM_Mem_ADV_LDN_pin,
Mem_LBON => open,
Mem_CKEN => open,
Mem_RNW => open
);
PCIe_Bridge : system_pcie_bridge_wrapper
port map (
MPLB_Clk => clk_125_0000MHzPLL0,
MPLB_Rst => mb_plb_MPLB_Rst(2),
PLB_MTimeout => mb_plb_PLB_MTimeout(2),
PLB_MIRQ => mb_plb_PLB_MIRQ(2),
PLB_MAddrAck => mb_plb_PLB_MAddrAck(2),
PLB_MSSize => mb_plb_PLB_MSSize(4 to 5),
PLB_MRearbitrate => mb_plb_PLB_MRearbitrate(2),
PLB_MBusy => mb_plb_PLB_MBusy(2),
PLB_MRdErr => mb_plb_PLB_MRdErr(2),
PLB_MWrErr => mb_plb_PLB_MWrErr(2),
PLB_MWrDAck => mb_plb_PLB_MWrDAck(2),
PLB_MRdDBus => mb_plb_PLB_MRdDBus(128 to 191),
PLB_MRdWdAddr => mb_plb_PLB_MRdWdAddr(8 to 11),
PLB_MRdDAck => mb_plb_PLB_MRdDAck(2),
PLB_MRdBTerm => mb_plb_PLB_MRdBTerm(2),
PLB_MWrBTerm => mb_plb_PLB_MWrBTerm(2),
M_request => mb_plb_M_request(2),
M_priority => mb_plb_M_priority(4 to 5),
M_buslock => mb_plb_M_busLock(2),
M_RNW => mb_plb_M_RNW(2),
M_BE => mb_plb_M_BE(16 to 23),
M_MSize => mb_plb_M_MSize(4 to 5),
M_size => mb_plb_M_size(8 to 11),
M_type => mb_plb_M_type(6 to 8),
M_lockErr => mb_plb_M_lockErr(2),
M_abort => mb_plb_M_ABort(2),
M_TAttribute => mb_plb_M_TAttribute(32 to 47),
M_UABus => mb_plb_M_UABus(64 to 95),
M_ABus => mb_plb_M_ABus(64 to 95),
M_wrDBus => mb_plb_M_wrDBus(128 to 191),
M_wrBurst => mb_plb_M_wrBurst(2),
M_rdBurst => mb_plb_M_rdBurst(2),
SPLB_Clk => clk_125_0000MHzPLL0,
SPLB_Rst => mb_plb_SPLB_Rst(2),
PLB_ABus => mb_plb_PLB_ABus,
PLB_UABus => mb_plb_PLB_UABus,
PLB_PAValid => mb_plb_PLB_PAValid,
PLB_SAValid => mb_plb_PLB_SAValid,
PLB_rdPrim => mb_plb_PLB_rdPrim(2),
PLB_wrPrim => mb_plb_PLB_wrPrim(2),
PLB_masterID => mb_plb_PLB_masterID,
PLB_abort => mb_plb_PLB_abort,
PLB_busLock => mb_plb_PLB_busLock,
PLB_RNW => mb_plb_PLB_RNW,
PLB_BE => mb_plb_PLB_BE,
PLB_MSize => mb_plb_PLB_MSize,
PLB_size => mb_plb_PLB_size,
PLB_type => mb_plb_PLB_type,
PLB_lockErr => mb_plb_PLB_lockErr,
PLB_wrDBus => mb_plb_PLB_wrDBus,
PLB_wrBurst => mb_plb_PLB_wrBurst,
PLB_rdBurst => mb_plb_PLB_rdBurst,
PLB_wrPendReq => mb_plb_PLB_wrPendReq,
PLB_rdPendReq => mb_plb_PLB_rdPendReq,
PLB_wrPendPri => mb_plb_PLB_wrPendPri,
PLB_rdPendPri => mb_plb_PLB_rdPendPri,
PLB_reqPri => mb_plb_PLB_reqPri,
PLB_TAttribute => mb_plb_PLB_TAttribute,
Sl_addrAck => mb_plb_Sl_addrAck(2),
Sl_SSize => mb_plb_Sl_SSize(4 to 5),
Sl_wait => mb_plb_Sl_wait(2),
Sl_rearbitrate => mb_plb_Sl_rearbitrate(2),
Sl_wrDAck => mb_plb_Sl_wrDAck(2),
Sl_wrComp => mb_plb_Sl_wrComp(2),
Sl_wrBTerm => mb_plb_Sl_wrBTerm(2),
Sl_rdDBus => mb_plb_Sl_rdDBus(128 to 191),
Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(8 to 11),
Sl_rdDAck => mb_plb_Sl_rdDAck(2),
Sl_rdComp => mb_plb_Sl_rdComp(2),
Sl_rdBTerm => mb_plb_Sl_rdBTerm(2),
Sl_MBusy => mb_plb_Sl_MBusy(12 to 17),
Sl_MWrErr => mb_plb_Sl_MWrErr(12 to 17),
Sl_MRdErr => mb_plb_Sl_MRdErr(12 to 17),
Sl_MIRQ => mb_plb_Sl_MIRQ(12 to 17),
REFCLK => PCIe_Diff_Clk,
Bridge_Clk => open,
RXN => pgassign3(0 to 0),
RXP => pgassign4(0 to 0),
TXN => pgassign5(0 to 0),
TXP => pgassign6(0 to 0),
IP2INTC_Irpt => PCIe_Bridge_IP2INTC_Irpt,
MSI_request => net_gnd0
);
xps_central_dma_1 : system_xps_central_dma_1_wrapper
port map (
SPLB_Clk => clk_125_0000MHzPLL0,
SPLB_Rst => mb_plb_SPLB_Rst(3),
MPLB_Clk => clk_125_0000MHzPLL0,
MPLB_Rst => mb_plb_MPLB_Rst(3),
SPLB_ABus => mb_plb_PLB_ABus,
SPLB_BE => mb_plb_PLB_BE,
SPLB_UABus => mb_plb_PLB_UABus,
SPLB_PAValid => mb_plb_PLB_PAValid,
SPLB_SAValid => mb_plb_PLB_SAValid,
SPLB_rdPrim => mb_plb_PLB_rdPrim(3),
SPLB_wrPrim => mb_plb_PLB_wrPrim(3),
SPLB_masterID => mb_plb_PLB_masterID,
SPLB_abort => mb_plb_PLB_abort,
SPLB_busLock => mb_plb_PLB_busLock,
SPLB_RNW => mb_plb_PLB_RNW,
SPLB_MSize => mb_plb_PLB_MSize,
SPLB_size => mb_plb_PLB_size,
SPLB_type => mb_plb_PLB_type,
SPLB_lockErr => mb_plb_PLB_lockErr,
SPLB_wrDBus => mb_plb_PLB_wrDBus,
SPLB_wrBurst => mb_plb_PLB_wrBurst,
SPLB_rdBurst => mb_plb_PLB_rdBurst,
SPLB_wrPendReq => mb_plb_PLB_wrPendReq,
SPLB_rdPendReq => mb_plb_PLB_rdPendReq,
SPLB_wrPendPri => mb_plb_PLB_wrPendPri,
SPLB_rdPendPri => mb_plb_PLB_rdPendPri,
SPLB_reqPri => mb_plb_PLB_reqPri,
SPLB_TAttribute => mb_plb_PLB_TAttribute,
Sl_addrAck => mb_plb_Sl_addrAck(3),
Sl_SSize => mb_plb_Sl_SSize(6 to 7),
Sl_wait => mb_plb_Sl_wait(3),
Sl_rearbitrate => mb_plb_Sl_rearbitrate(3),
Sl_wrDAck => mb_plb_Sl_wrDAck(3),
Sl_wrComp => mb_plb_Sl_wrComp(3),
Sl_wrBTerm => mb_plb_Sl_wrBTerm(3),
Sl_rdDBus => mb_plb_Sl_rdDBus(192 to 255),
Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(12 to 15),
Sl_rdDAck => mb_plb_Sl_rdDAck(3),
Sl_rdComp => mb_plb_Sl_rdComp(3),
Sl_rdBTerm => mb_plb_Sl_rdBTerm(3),
Sl_MBusy => mb_plb_Sl_MBusy(18 to 23),
Sl_MWrErr => mb_plb_Sl_MWrErr(18 to 23),
Sl_MRdErr => mb_plb_Sl_MRdErr(18 to 23),
Sl_MIRQ => mb_plb_Sl_MIRQ(18 to 23),
IP2INTC_Irpt => xps_central_dma_1_IP2INTC_Irpt,
MPLB_MAddrAck => mb_plb_PLB_MAddrAck(3),
MPLB_MSSize => mb_plb_PLB_MSSize(6 to 7),
MPLB_MRearbitrate => mb_plb_PLB_MRearbitrate(3),
MPLB_MTimeout => mb_plb_PLB_MTimeout(3),
MPLB_MBusy => mb_plb_PLB_MBusy(3),
MPLB_MRdErr => mb_plb_PLB_MRdErr(3),
MPLB_MWrErr => mb_plb_PLB_MWrErr(3),
MPLB_MIRQ => mb_plb_PLB_MIRQ(3),
MPLB_MRdDBus => mb_plb_PLB_MRdDBus(192 to 255),
MPLB_MRdWdAddr => mb_plb_PLB_MRdWdAddr(12 to 15),
MPLB_MRdDAck => mb_plb_PLB_MRdDAck(3),
MPLB_MRdBTerm => mb_plb_PLB_MRdBTerm(3),
MPLB_MWrDAck => mb_plb_PLB_MWrDAck(3),
MPLB_MWrBTerm => mb_plb_PLB_MWrBTerm(3),
M_request => mb_plb_M_request(3),
M_priority => mb_plb_M_priority(6 to 7),
M_busLock => mb_plb_M_busLock(3),
M_RNW => mb_plb_M_RNW(3),
M_BE => mb_plb_M_BE(24 to 31),
M_MSize => mb_plb_M_MSize(6 to 7),
M_size => mb_plb_M_size(12 to 15),
M_type => mb_plb_M_type(9 to 11),
M_TAttribute => mb_plb_M_TAttribute(48 to 63),
M_lockErr => mb_plb_M_lockErr(3),
M_abort => mb_plb_M_ABort(3),
M_UABus => mb_plb_M_UABus(96 to 127),
M_ABus => mb_plb_M_ABus(96 to 127),
M_wrDBus => mb_plb_M_wrDBus(192 to 255),
M_wrBurst => mb_plb_M_wrBurst(3),
M_rdBurst => mb_plb_M_rdBurst(3)
);
clock_generator_0 : system_clock_generator_0_wrapper
port map (
CLKIN => CLK_S,
CLKOUT0 => clk_125_0000MHz90PLL0,
CLKOUT1 => clk_125_0000MHzPLL0,
CLKOUT2 => clk_200_0000MHz,
CLKOUT3 => clk_62_5000MHzPLL0,
CLKOUT4 => open,
CLKOUT5 => open,
CLKOUT6 => open,
CLKOUT7 => open,
CLKOUT8 => open,
CLKOUT9 => open,
CLKOUT10 => open,
CLKOUT11 => open,
CLKOUT12 => open,
CLKOUT13 => open,
CLKOUT14 => open,
CLKOUT15 => open,
CLKFBIN => SRAM_CLK_FB_s,
CLKFBOUT => SRAM_CLK_OUT_s,
PSCLK => net_gnd0,
PSEN => net_gnd0,
PSINCDEC => net_gnd0,
PSDONE => open,
RST => sys_rst_s,
LOCKED => Dcm_all_locked
);
mdm_0 : system_mdm_0_wrapper
port map (
Interrupt => open,
Debug_SYS_Rst => Debug_SYS_Rst,
Ext_BRK => Ext_BRK,
Ext_NM_BRK => Ext_NM_BRK,
S_AXI_ACLK => net_gnd0,
S_AXI_ARESETN => net_gnd0,
S_AXI_AWADDR => net_gnd32(0 to 31),
S_AXI_AWVALID => net_gnd0,
S_AXI_AWREADY => open,
S_AXI_WDATA => net_gnd32(0 to 31),
S_AXI_WSTRB => net_gnd4(0 to 3),
S_AXI_WVALID => net_gnd0,
S_AXI_WREADY => open,
S_AXI_BRESP => open,
S_AXI_BVALID => open,
S_AXI_BREADY => net_gnd0,
S_AXI_ARADDR => net_gnd32(0 to 31),
S_AXI_ARVALID => net_gnd0,
S_AXI_ARREADY => open,
S_AXI_RDATA => open,
S_AXI_RRESP => open,
S_AXI_RVALID => open,
S_AXI_RREADY => net_gnd0,
SPLB_Clk => clk_125_0000MHzPLL0,
SPLB_Rst => mb_plb_SPLB_Rst(4),
PLB_ABus => mb_plb_PLB_ABus,
PLB_UABus => mb_plb_PLB_UABus,
PLB_PAValid => mb_plb_PLB_PAValid,
PLB_SAValid => mb_plb_PLB_SAValid,
PLB_rdPrim => mb_plb_PLB_rdPrim(4),
PLB_wrPrim => mb_plb_PLB_wrPrim(4),
PLB_masterID => mb_plb_PLB_masterID,
PLB_abort => mb_plb_PLB_abort,
PLB_busLock => mb_plb_PLB_busLock,
PLB_RNW => mb_plb_PLB_RNW,
PLB_BE => mb_plb_PLB_BE,
PLB_MSize => mb_plb_PLB_MSize,
PLB_size => mb_plb_PLB_size,
PLB_type => mb_plb_PLB_type,
PLB_lockErr => mb_plb_PLB_lockErr,
PLB_wrDBus => mb_plb_PLB_wrDBus,
PLB_wrBurst => mb_plb_PLB_wrBurst,
PLB_rdBurst => mb_plb_PLB_rdBurst,
PLB_wrPendReq => mb_plb_PLB_wrPendReq,
PLB_rdPendReq => mb_plb_PLB_rdPendReq,
PLB_wrPendPri => mb_plb_PLB_wrPendPri,
PLB_rdPendPri => mb_plb_PLB_rdPendPri,
PLB_reqPri => mb_plb_PLB_reqPri,
PLB_TAttribute => mb_plb_PLB_TAttribute,
Sl_addrAck => mb_plb_Sl_addrAck(4),
Sl_SSize => mb_plb_Sl_SSize(8 to 9),
Sl_wait => mb_plb_Sl_wait(4),
Sl_rearbitrate => mb_plb_Sl_rearbitrate(4),
Sl_wrDAck => mb_plb_Sl_wrDAck(4),
Sl_wrComp => mb_plb_Sl_wrComp(4),
Sl_wrBTerm => mb_plb_Sl_wrBTerm(4),
Sl_rdDBus => mb_plb_Sl_rdDBus(256 to 319),
Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(16 to 19),
Sl_rdDAck => mb_plb_Sl_rdDAck(4),
Sl_rdComp => mb_plb_Sl_rdComp(4),
Sl_rdBTerm => mb_plb_Sl_rdBTerm(4),
Sl_MBusy => mb_plb_Sl_MBusy(24 to 29),
Sl_MWrErr => mb_plb_Sl_MWrErr(24 to 29),
Sl_MRdErr => mb_plb_Sl_MRdErr(24 to 29),
Sl_MIRQ => mb_plb_Sl_MIRQ(24 to 29),
Dbg_Clk_0 => microblaze_0_mdm_bus_Dbg_Clk,
Dbg_TDI_0 => microblaze_0_mdm_bus_Dbg_TDI,
Dbg_TDO_0 => microblaze_0_mdm_bus_Dbg_TDO,
Dbg_Reg_En_0 => microblaze_0_mdm_bus_Dbg_Reg_En,
Dbg_Capture_0 => microblaze_0_mdm_bus_Dbg_Capture,
Dbg_Shift_0 => microblaze_0_mdm_bus_Dbg_Shift,
Dbg_Update_0 => microblaze_0_mdm_bus_Dbg_Update,
Dbg_Rst_0 => microblaze_0_mdm_bus_Debug_Rst,
Dbg_Clk_1 => open,
Dbg_TDI_1 => open,
Dbg_TDO_1 => net_gnd0,
Dbg_Reg_En_1 => open,
Dbg_Capture_1 => open,
Dbg_Shift_1 => open,
Dbg_Update_1 => open,
Dbg_Rst_1 => open,
Dbg_Clk_2 => open,
Dbg_TDI_2 => open,
Dbg_TDO_2 => net_gnd0,
Dbg_Reg_En_2 => open,
Dbg_Capture_2 => open,
Dbg_Shift_2 => open,
Dbg_Update_2 => open,
Dbg_Rst_2 => open,
Dbg_Clk_3 => open,
Dbg_TDI_3 => open,
Dbg_TDO_3 => net_gnd0,
Dbg_Reg_En_3 => open,
Dbg_Capture_3 => open,
Dbg_Shift_3 => open,
Dbg_Update_3 => open,
Dbg_Rst_3 => open,
Dbg_Clk_4 => open,
Dbg_TDI_4 => open,
Dbg_TDO_4 => net_gnd0,
Dbg_Reg_En_4 => open,
Dbg_Capture_4 => open,
Dbg_Shift_4 => open,
Dbg_Update_4 => open,
Dbg_Rst_4 => open,
Dbg_Clk_5 => open,
Dbg_TDI_5 => open,
Dbg_TDO_5 => net_gnd0,
Dbg_Reg_En_5 => open,
Dbg_Capture_5 => open,
Dbg_Shift_5 => open,
Dbg_Update_5 => open,
Dbg_Rst_5 => open,
Dbg_Clk_6 => open,
Dbg_TDI_6 => open,
Dbg_TDO_6 => net_gnd0,
Dbg_Reg_En_6 => open,
Dbg_Capture_6 => open,
Dbg_Shift_6 => open,
Dbg_Update_6 => open,
Dbg_Rst_6 => open,
Dbg_Clk_7 => open,
Dbg_TDI_7 => open,
Dbg_TDO_7 => net_gnd0,
Dbg_Reg_En_7 => open,
Dbg_Capture_7 => open,
Dbg_Shift_7 => open,
Dbg_Update_7 => open,
Dbg_Rst_7 => open,
Dbg_Clk_8 => open,
Dbg_TDI_8 => open,
Dbg_TDO_8 => net_gnd0,
Dbg_Reg_En_8 => open,
Dbg_Capture_8 => open,
Dbg_Shift_8 => open,
Dbg_Update_8 => open,
Dbg_Rst_8 => open,
Dbg_Clk_9 => open,
Dbg_TDI_9 => open,
Dbg_TDO_9 => net_gnd0,
Dbg_Reg_En_9 => open,
Dbg_Capture_9 => open,
Dbg_Shift_9 => open,
Dbg_Update_9 => open,
Dbg_Rst_9 => open,
Dbg_Clk_10 => open,
Dbg_TDI_10 => open,
Dbg_TDO_10 => net_gnd0,
Dbg_Reg_En_10 => open,
Dbg_Capture_10 => open,
Dbg_Shift_10 => open,
Dbg_Update_10 => open,
Dbg_Rst_10 => open,
Dbg_Clk_11 => open,
Dbg_TDI_11 => open,
Dbg_TDO_11 => net_gnd0,
Dbg_Reg_En_11 => open,
Dbg_Capture_11 => open,
Dbg_Shift_11 => open,
Dbg_Update_11 => open,
Dbg_Rst_11 => open,
Dbg_Clk_12 => open,
Dbg_TDI_12 => open,
Dbg_TDO_12 => net_gnd0,
Dbg_Reg_En_12 => open,
Dbg_Capture_12 => open,
Dbg_Shift_12 => open,
Dbg_Update_12 => open,
Dbg_Rst_12 => open,
Dbg_Clk_13 => open,
Dbg_TDI_13 => open,
Dbg_TDO_13 => net_gnd0,
Dbg_Reg_En_13 => open,
Dbg_Capture_13 => open,
Dbg_Shift_13 => open,
Dbg_Update_13 => open,
Dbg_Rst_13 => open,
Dbg_Clk_14 => open,
Dbg_TDI_14 => open,
Dbg_TDO_14 => net_gnd0,
Dbg_Reg_En_14 => open,
Dbg_Capture_14 => open,
Dbg_Shift_14 => open,
Dbg_Update_14 => open,
Dbg_Rst_14 => open,
Dbg_Clk_15 => open,
Dbg_TDI_15 => open,
Dbg_TDO_15 => net_gnd0,
Dbg_Reg_En_15 => open,
Dbg_Capture_15 => open,
Dbg_Shift_15 => open,
Dbg_Update_15 => open,
Dbg_Rst_15 => open,
Dbg_Clk_16 => open,
Dbg_TDI_16 => open,
Dbg_TDO_16 => net_gnd0,
Dbg_Reg_En_16 => open,
Dbg_Capture_16 => open,
Dbg_Shift_16 => open,
Dbg_Update_16 => open,
Dbg_Rst_16 => open,
Dbg_Clk_17 => open,
Dbg_TDI_17 => open,
Dbg_TDO_17 => net_gnd0,
Dbg_Reg_En_17 => open,
Dbg_Capture_17 => open,
Dbg_Shift_17 => open,
Dbg_Update_17 => open,
Dbg_Rst_17 => open,
Dbg_Clk_18 => open,
Dbg_TDI_18 => open,
Dbg_TDO_18 => net_gnd0,
Dbg_Reg_En_18 => open,
Dbg_Capture_18 => open,
Dbg_Shift_18 => open,
Dbg_Update_18 => open,
Dbg_Rst_18 => open,
Dbg_Clk_19 => open,
Dbg_TDI_19 => open,
Dbg_TDO_19 => net_gnd0,
Dbg_Reg_En_19 => open,
Dbg_Capture_19 => open,
Dbg_Shift_19 => open,
Dbg_Update_19 => open,
Dbg_Rst_19 => open,
Dbg_Clk_20 => open,
Dbg_TDI_20 => open,
Dbg_TDO_20 => net_gnd0,
Dbg_Reg_En_20 => open,
Dbg_Capture_20 => open,
Dbg_Shift_20 => open,
Dbg_Update_20 => open,
Dbg_Rst_20 => open,
Dbg_Clk_21 => open,
Dbg_TDI_21 => open,
Dbg_TDO_21 => net_gnd0,
Dbg_Reg_En_21 => open,
Dbg_Capture_21 => open,
Dbg_Shift_21 => open,
Dbg_Update_21 => open,
Dbg_Rst_21 => open,
Dbg_Clk_22 => open,
Dbg_TDI_22 => open,
Dbg_TDO_22 => net_gnd0,
Dbg_Reg_En_22 => open,
Dbg_Capture_22 => open,
Dbg_Shift_22 => open,
Dbg_Update_22 => open,
Dbg_Rst_22 => open,
Dbg_Clk_23 => open,
Dbg_TDI_23 => open,
Dbg_TDO_23 => net_gnd0,
Dbg_Reg_En_23 => open,
Dbg_Capture_23 => open,
Dbg_Shift_23 => open,
Dbg_Update_23 => open,
Dbg_Rst_23 => open,
Dbg_Clk_24 => open,
Dbg_TDI_24 => open,
Dbg_TDO_24 => net_gnd0,
Dbg_Reg_En_24 => open,
Dbg_Capture_24 => open,
Dbg_Shift_24 => open,
Dbg_Update_24 => open,
Dbg_Rst_24 => open,
Dbg_Clk_25 => open,
Dbg_TDI_25 => open,
Dbg_TDO_25 => net_gnd0,
Dbg_Reg_En_25 => open,
Dbg_Capture_25 => open,
Dbg_Shift_25 => open,
Dbg_Update_25 => open,
Dbg_Rst_25 => open,
Dbg_Clk_26 => open,
Dbg_TDI_26 => open,
Dbg_TDO_26 => net_gnd0,
Dbg_Reg_En_26 => open,
Dbg_Capture_26 => open,
Dbg_Shift_26 => open,
Dbg_Update_26 => open,
Dbg_Rst_26 => open,
Dbg_Clk_27 => open,
Dbg_TDI_27 => open,
Dbg_TDO_27 => net_gnd0,
Dbg_Reg_En_27 => open,
Dbg_Capture_27 => open,
Dbg_Shift_27 => open,
Dbg_Update_27 => open,
Dbg_Rst_27 => open,
Dbg_Clk_28 => open,
Dbg_TDI_28 => open,
Dbg_TDO_28 => net_gnd0,
Dbg_Reg_En_28 => open,
Dbg_Capture_28 => open,
Dbg_Shift_28 => open,
Dbg_Update_28 => open,
Dbg_Rst_28 => open,
Dbg_Clk_29 => open,
Dbg_TDI_29 => open,
Dbg_TDO_29 => net_gnd0,
Dbg_Reg_En_29 => open,
Dbg_Capture_29 => open,
Dbg_Shift_29 => open,
Dbg_Update_29 => open,
Dbg_Rst_29 => open,
Dbg_Clk_30 => open,
Dbg_TDI_30 => open,
Dbg_TDO_30 => net_gnd0,
Dbg_Reg_En_30 => open,
Dbg_Capture_30 => open,
Dbg_Shift_30 => open,
Dbg_Update_30 => open,
Dbg_Rst_30 => open,
Dbg_Clk_31 => open,
Dbg_TDI_31 => open,
Dbg_TDO_31 => net_gnd0,
Dbg_Reg_En_31 => open,
Dbg_Capture_31 => open,
Dbg_Shift_31 => open,
Dbg_Update_31 => open,
Dbg_Rst_31 => open,
bscan_tdi => open,
bscan_reset => open,
bscan_shift => open,
bscan_update => open,
bscan_capture => open,
bscan_sel1 => open,
bscan_drck1 => open,
bscan_tdo1 => net_gnd0,
bscan_ext_tdi => net_gnd0,
bscan_ext_reset => net_gnd0,
bscan_ext_shift => net_gnd0,
bscan_ext_update => net_gnd0,
bscan_ext_capture => net_gnd0,
bscan_ext_sel => net_gnd0,
bscan_ext_drck => net_gnd0,
bscan_ext_tdo => open,
Ext_JTAG_DRCK => open,
Ext_JTAG_RESET => open,
Ext_JTAG_SEL => open,
Ext_JTAG_CAPTURE => open,
Ext_JTAG_SHIFT => open,
Ext_JTAG_UPDATE => open,
Ext_JTAG_TDI => open,
Ext_JTAG_TDO => net_gnd0
);
proc_sys_reset_0 : system_proc_sys_reset_0_wrapper
port map (
Slowest_sync_clk => clk_125_0000MHzPLL0,
Ext_Reset_In => sys_rst_s,
Aux_Reset_In => net_gnd0,
MB_Debug_Sys_Rst => Debug_SYS_Rst,
Core_Reset_Req_0 => net_gnd0,
Chip_Reset_Req_0 => net_gnd0,
System_Reset_Req_0 => net_gnd0,
Core_Reset_Req_1 => net_gnd0,
Chip_Reset_Req_1 => net_gnd0,
System_Reset_Req_1 => net_gnd0,
Dcm_locked => Dcm_all_locked,
RstcPPCresetcore_0 => open,
RstcPPCresetchip_0 => open,
RstcPPCresetsys_0 => open,
RstcPPCresetcore_1 => open,
RstcPPCresetchip_1 => open,
RstcPPCresetsys_1 => open,
MB_Reset => mb_reset,
Bus_Struct_Reset => sys_bus_reset(0 to 0),
Peripheral_Reset => sys_periph_reset(0 to 0),
Interconnect_aresetn => open,
Peripheral_aresetn => proc_sys_reset_0_Peripheral_aresetn(0 to 0)
);
xps_intc_0 : system_xps_intc_0_wrapper
port map (
SPLB_Clk => clk_125_0000MHzPLL0,
SPLB_Rst => mb_plb_SPLB_Rst(5),
PLB_ABus => mb_plb_PLB_ABus,
PLB_PAValid => mb_plb_PLB_PAValid,
PLB_masterID => mb_plb_PLB_masterID,
PLB_RNW => mb_plb_PLB_RNW,
PLB_BE => mb_plb_PLB_BE,
PLB_size => mb_plb_PLB_size,
PLB_type => mb_plb_PLB_type,
PLB_wrDBus => mb_plb_PLB_wrDBus,
PLB_UABus => mb_plb_PLB_UABus,
PLB_SAValid => mb_plb_PLB_SAValid,
PLB_rdPrim => mb_plb_PLB_rdPrim(5),
PLB_wrPrim => mb_plb_PLB_wrPrim(5),
PLB_abort => mb_plb_PLB_abort,
PLB_busLock => mb_plb_PLB_busLock,
PLB_MSize => mb_plb_PLB_MSize,
PLB_lockErr => mb_plb_PLB_lockErr,
PLB_wrBurst => mb_plb_PLB_wrBurst,
PLB_rdBurst => mb_plb_PLB_rdBurst,
PLB_wrPendReq => mb_plb_PLB_wrPendReq,
PLB_rdPendReq => mb_plb_PLB_rdPendReq,
PLB_wrPendPri => mb_plb_PLB_wrPendPri,
PLB_rdPendPri => mb_plb_PLB_rdPendPri,
PLB_reqPri => mb_plb_PLB_reqPri,
PLB_TAttribute => mb_plb_PLB_TAttribute,
Sl_addrAck => mb_plb_Sl_addrAck(5),
Sl_SSize => mb_plb_Sl_SSize(10 to 11),
Sl_wait => mb_plb_Sl_wait(5),
Sl_rearbitrate => mb_plb_Sl_rearbitrate(5),
Sl_wrDAck => mb_plb_Sl_wrDAck(5),
Sl_wrComp => mb_plb_Sl_wrComp(5),
Sl_rdDBus => mb_plb_Sl_rdDBus(320 to 383),
Sl_rdDAck => mb_plb_Sl_rdDAck(5),
Sl_rdComp => mb_plb_Sl_rdComp(5),
Sl_MBusy => mb_plb_Sl_MBusy(30 to 35),
Sl_MWrErr => mb_plb_Sl_MWrErr(30 to 35),
Sl_MRdErr => mb_plb_Sl_MRdErr(30 to 35),
Sl_wrBTerm => mb_plb_Sl_wrBTerm(5),
Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(20 to 23),
Sl_rdBTerm => mb_plb_Sl_rdBTerm(5),
Sl_MIRQ => mb_plb_Sl_MIRQ(30 to 35),
Intr => pgassign10,
Irq => microblaze_0_Interrupt
);
nfa_accept_samples_generic_hw_top_0 : system_nfa_accept_samples_generic_hw_top_0_wrapper
port map (
aclk => clk_125_0000MHzPLL0,
aresetn => proc_sys_reset_0_Peripheral_aresetn(0),
indices_MPLB_Clk => net_gnd0,
indices_MPLB_Rst => ac0_plb_MPLB_Rst(0),
indices_M_request => ac0_plb_M_request(0),
indices_M_priority => ac0_plb_M_priority(0 to 1),
indices_M_busLock => ac0_plb_M_busLock(0),
indices_M_RNW => ac0_plb_M_RNW(0),
indices_M_BE => ac0_plb_M_BE(0 to 7),
indices_M_MSize => ac0_plb_M_MSize(0 to 1),
indices_M_size => ac0_plb_M_size(0 to 3),
indices_M_type => ac0_plb_M_type(0 to 2),
indices_M_TAttribute => ac0_plb_M_TAttribute(0 to 15),
indices_M_lockErr => ac0_plb_M_lockErr(0),
indices_M_abort => ac0_plb_M_abort(0),
indices_M_UABus => ac0_plb_M_UABus(0 to 31),
indices_M_ABus => ac0_plb_M_ABus(0 to 31),
indices_M_wrDBus => ac0_plb_M_wrDBus(0 to 63),
indices_M_wrBurst => ac0_plb_M_wrBurst(0),
indices_M_rdBurst => ac0_plb_M_rdBurst(0),
indices_PLB_MAddrAck => ac0_plb_PLB_MAddrAck(0),
indices_PLB_MSSize => ac0_plb_PLB_MSSize(0 to 1),
indices_PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate(0),
indices_PLB_MTimeout => ac0_plb_PLB_MTimeout(0),
indices_PLB_MBusy => ac0_plb_PLB_MBusy(0),
indices_PLB_MRdErr => ac0_plb_PLB_MRdErr(0),
indices_PLB_MWrErr => ac0_plb_PLB_MWrErr(0),
indices_PLB_MIRQ => ac0_plb_PLB_MIRQ(0),
indices_PLB_MRdDBus => ac0_plb_PLB_MRdDBus(0 to 63),
indices_PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr(0 to 3),
indices_PLB_MRdDAck => ac0_plb_PLB_MRdDAck(0),
indices_PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm(0),
indices_PLB_MWrDAck => ac0_plb_PLB_MWrDAck(0),
indices_PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm(0),
nfa_finals_buckets_MPLB_Clk => net_gnd0,
nfa_finals_buckets_MPLB_Rst => ac0_plb_MPLB_Rst(1),
nfa_finals_buckets_M_request => ac0_plb_M_request(1),
nfa_finals_buckets_M_priority => ac0_plb_M_priority(2 to 3),
nfa_finals_buckets_M_busLock => ac0_plb_M_busLock(1),
nfa_finals_buckets_M_RNW => ac0_plb_M_RNW(1),
nfa_finals_buckets_M_BE => ac0_plb_M_BE(8 to 15),
nfa_finals_buckets_M_MSize => ac0_plb_M_MSize(2 to 3),
nfa_finals_buckets_M_size => ac0_plb_M_size(4 to 7),
nfa_finals_buckets_M_type => ac0_plb_M_type(3 to 5),
nfa_finals_buckets_M_TAttribute => ac0_plb_M_TAttribute(16 to 31),
nfa_finals_buckets_M_lockErr => ac0_plb_M_lockErr(1),
nfa_finals_buckets_M_abort => ac0_plb_M_abort(1),
nfa_finals_buckets_M_UABus => ac0_plb_M_UABus(32 to 63),
nfa_finals_buckets_M_ABus => ac0_plb_M_ABus(32 to 63),
nfa_finals_buckets_M_wrDBus => ac0_plb_M_wrDBus(64 to 127),
nfa_finals_buckets_M_wrBurst => ac0_plb_M_wrBurst(1),
nfa_finals_buckets_M_rdBurst => ac0_plb_M_rdBurst(1),
nfa_finals_buckets_PLB_MAddrAck => ac0_plb_PLB_MAddrAck(1),
nfa_finals_buckets_PLB_MSSize => ac0_plb_PLB_MSSize(2 to 3),
nfa_finals_buckets_PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate(1),
nfa_finals_buckets_PLB_MTimeout => ac0_plb_PLB_MTimeout(1),
nfa_finals_buckets_PLB_MBusy => ac0_plb_PLB_MBusy(1),
nfa_finals_buckets_PLB_MRdErr => ac0_plb_PLB_MRdErr(1),
nfa_finals_buckets_PLB_MWrErr => ac0_plb_PLB_MWrErr(1),
nfa_finals_buckets_PLB_MIRQ => ac0_plb_PLB_MIRQ(1),
nfa_finals_buckets_PLB_MRdDBus => ac0_plb_PLB_MRdDBus(64 to 127),
nfa_finals_buckets_PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr(4 to 7),
nfa_finals_buckets_PLB_MRdDAck => ac0_plb_PLB_MRdDAck(1),
nfa_finals_buckets_PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm(1),
nfa_finals_buckets_PLB_MWrDAck => ac0_plb_PLB_MWrDAck(1),
nfa_finals_buckets_PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm(1),
nfa_forward_buckets_MPLB_Clk => net_gnd0,
nfa_forward_buckets_MPLB_Rst => ac0_plb_MPLB_Rst(2),
nfa_forward_buckets_M_request => ac0_plb_M_request(2),
nfa_forward_buckets_M_priority => ac0_plb_M_priority(4 to 5),
nfa_forward_buckets_M_busLock => ac0_plb_M_busLock(2),
nfa_forward_buckets_M_RNW => ac0_plb_M_RNW(2),
nfa_forward_buckets_M_BE => ac0_plb_M_BE(16 to 23),
nfa_forward_buckets_M_MSize => ac0_plb_M_MSize(4 to 5),
nfa_forward_buckets_M_size => ac0_plb_M_size(8 to 11),
nfa_forward_buckets_M_type => ac0_plb_M_type(6 to 8),
nfa_forward_buckets_M_TAttribute => ac0_plb_M_TAttribute(32 to 47),
nfa_forward_buckets_M_lockErr => ac0_plb_M_lockErr(2),
nfa_forward_buckets_M_abort => ac0_plb_M_abort(2),
nfa_forward_buckets_M_UABus => ac0_plb_M_UABus(64 to 95),
nfa_forward_buckets_M_ABus => ac0_plb_M_ABus(64 to 95),
nfa_forward_buckets_M_wrDBus => ac0_plb_M_wrDBus(128 to 191),
nfa_forward_buckets_M_wrBurst => ac0_plb_M_wrBurst(2),
nfa_forward_buckets_M_rdBurst => ac0_plb_M_rdBurst(2),
nfa_forward_buckets_PLB_MAddrAck => ac0_plb_PLB_MAddrAck(2),
nfa_forward_buckets_PLB_MSSize => ac0_plb_PLB_MSSize(4 to 5),
nfa_forward_buckets_PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate(2),
nfa_forward_buckets_PLB_MTimeout => ac0_plb_PLB_MTimeout(2),
nfa_forward_buckets_PLB_MBusy => ac0_plb_PLB_MBusy(2),
nfa_forward_buckets_PLB_MRdErr => ac0_plb_PLB_MRdErr(2),
nfa_forward_buckets_PLB_MWrErr => ac0_plb_PLB_MWrErr(2),
nfa_forward_buckets_PLB_MIRQ => ac0_plb_PLB_MIRQ(2),
nfa_forward_buckets_PLB_MRdDBus => ac0_plb_PLB_MRdDBus(128 to 191),
nfa_forward_buckets_PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr(8 to 11),
nfa_forward_buckets_PLB_MRdDAck => ac0_plb_PLB_MRdDAck(2),
nfa_forward_buckets_PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm(2),
nfa_forward_buckets_PLB_MWrDAck => ac0_plb_PLB_MWrDAck(2),
nfa_forward_buckets_PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm(2),
nfa_initials_buckets_MPLB_Clk => net_gnd0,
nfa_initials_buckets_MPLB_Rst => ac0_plb_MPLB_Rst(3),
nfa_initials_buckets_M_request => ac0_plb_M_request(3),
nfa_initials_buckets_M_priority => ac0_plb_M_priority(6 to 7),
nfa_initials_buckets_M_busLock => ac0_plb_M_busLock(3),
nfa_initials_buckets_M_RNW => ac0_plb_M_RNW(3),
nfa_initials_buckets_M_BE => ac0_plb_M_BE(24 to 31),
nfa_initials_buckets_M_MSize => ac0_plb_M_MSize(6 to 7),
nfa_initials_buckets_M_size => ac0_plb_M_size(12 to 15),
nfa_initials_buckets_M_type => ac0_plb_M_type(9 to 11),
nfa_initials_buckets_M_TAttribute => ac0_plb_M_TAttribute(48 to 63),
nfa_initials_buckets_M_lockErr => ac0_plb_M_lockErr(3),
nfa_initials_buckets_M_abort => ac0_plb_M_abort(3),
nfa_initials_buckets_M_UABus => ac0_plb_M_UABus(96 to 127),
nfa_initials_buckets_M_ABus => ac0_plb_M_ABus(96 to 127),
nfa_initials_buckets_M_wrDBus => ac0_plb_M_wrDBus(192 to 255),
nfa_initials_buckets_M_wrBurst => ac0_plb_M_wrBurst(3),
nfa_initials_buckets_M_rdBurst => ac0_plb_M_rdBurst(3),
nfa_initials_buckets_PLB_MAddrAck => ac0_plb_PLB_MAddrAck(3),
nfa_initials_buckets_PLB_MSSize => ac0_plb_PLB_MSSize(6 to 7),
nfa_initials_buckets_PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate(3),
nfa_initials_buckets_PLB_MTimeout => ac0_plb_PLB_MTimeout(3),
nfa_initials_buckets_PLB_MBusy => ac0_plb_PLB_MBusy(3),
nfa_initials_buckets_PLB_MRdErr => ac0_plb_PLB_MRdErr(3),
nfa_initials_buckets_PLB_MWrErr => ac0_plb_PLB_MWrErr(3),
nfa_initials_buckets_PLB_MIRQ => ac0_plb_PLB_MIRQ(3),
nfa_initials_buckets_PLB_MRdDBus => ac0_plb_PLB_MRdDBus(192 to 255),
nfa_initials_buckets_PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr(12 to 15),
nfa_initials_buckets_PLB_MRdDAck => ac0_plb_PLB_MRdDAck(3),
nfa_initials_buckets_PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm(3),
nfa_initials_buckets_PLB_MWrDAck => ac0_plb_PLB_MWrDAck(3),
nfa_initials_buckets_PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm(3),
sample_buffer_MPLB_Clk => net_gnd0,
sample_buffer_MPLB_Rst => ac0_plb_MPLB_Rst(4),
sample_buffer_M_request => ac0_plb_M_request(4),
sample_buffer_M_priority => ac0_plb_M_priority(8 to 9),
sample_buffer_M_busLock => ac0_plb_M_busLock(4),
sample_buffer_M_RNW => ac0_plb_M_RNW(4),
sample_buffer_M_BE => ac0_plb_M_BE(32 to 39),
sample_buffer_M_MSize => ac0_plb_M_MSize(8 to 9),
sample_buffer_M_size => ac0_plb_M_size(16 to 19),
sample_buffer_M_type => ac0_plb_M_type(12 to 14),
sample_buffer_M_TAttribute => ac0_plb_M_TAttribute(64 to 79),
sample_buffer_M_lockErr => ac0_plb_M_lockErr(4),
sample_buffer_M_abort => ac0_plb_M_abort(4),
sample_buffer_M_UABus => ac0_plb_M_UABus(128 to 159),
sample_buffer_M_ABus => ac0_plb_M_ABus(128 to 159),
sample_buffer_M_wrDBus => ac0_plb_M_wrDBus(256 to 319),
sample_buffer_M_wrBurst => ac0_plb_M_wrBurst(4),
sample_buffer_M_rdBurst => ac0_plb_M_rdBurst(4),
sample_buffer_PLB_MAddrAck => ac0_plb_PLB_MAddrAck(4),
sample_buffer_PLB_MSSize => ac0_plb_PLB_MSSize(8 to 9),
sample_buffer_PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate(4),
sample_buffer_PLB_MTimeout => ac0_plb_PLB_MTimeout(4),
sample_buffer_PLB_MBusy => ac0_plb_PLB_MBusy(4),
sample_buffer_PLB_MRdErr => ac0_plb_PLB_MRdErr(4),
sample_buffer_PLB_MWrErr => ac0_plb_PLB_MWrErr(4),
sample_buffer_PLB_MIRQ => ac0_plb_PLB_MIRQ(4),
sample_buffer_PLB_MRdDBus => ac0_plb_PLB_MRdDBus(256 to 319),
sample_buffer_PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr(16 to 19),
sample_buffer_PLB_MRdDAck => ac0_plb_PLB_MRdDAck(4),
sample_buffer_PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm(4),
sample_buffer_PLB_MWrDAck => ac0_plb_PLB_MWrDAck(4),
sample_buffer_PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm(4),
splb_slv0_SPLB_Clk => clk_125_0000MHzPLL0,
splb_slv0_SPLB_Rst => mb_plb_SPLB_Rst(6),
splb_slv0_PLB_ABus => mb_plb_PLB_ABus,
splb_slv0_PLB_UABus => mb_plb_PLB_UABus,
splb_slv0_PLB_PAValid => mb_plb_PLB_PAValid,
splb_slv0_PLB_SAValid => mb_plb_PLB_SAValid,
splb_slv0_PLB_rdPrim => mb_plb_PLB_rdPrim(6),
splb_slv0_PLB_wrPrim => mb_plb_PLB_wrPrim(6),
splb_slv0_PLB_masterID => mb_plb_PLB_masterID,
splb_slv0_PLB_abort => mb_plb_PLB_abort,
splb_slv0_PLB_busLock => mb_plb_PLB_busLock,
splb_slv0_PLB_RNW => mb_plb_PLB_RNW,
splb_slv0_PLB_BE => mb_plb_PLB_BE,
splb_slv0_PLB_MSize => mb_plb_PLB_MSize,
splb_slv0_PLB_size => mb_plb_PLB_size,
splb_slv0_PLB_type => mb_plb_PLB_type,
splb_slv0_PLB_lockErr => mb_plb_PLB_lockErr,
splb_slv0_PLB_wrDBus => mb_plb_PLB_wrDBus,
splb_slv0_PLB_wrBurst => mb_plb_PLB_wrBurst,
splb_slv0_PLB_rdBurst => mb_plb_PLB_rdBurst,
splb_slv0_PLB_wrPendReq => mb_plb_PLB_wrPendReq,
splb_slv0_PLB_rdPendReq => mb_plb_PLB_rdPendReq,
splb_slv0_PLB_wrPendPri => mb_plb_PLB_wrPendPri,
splb_slv0_PLB_rdPendPri => mb_plb_PLB_rdPendPri,
splb_slv0_PLB_reqPri => mb_plb_PLB_reqPri,
splb_slv0_PLB_TAttribute => mb_plb_PLB_TAttribute,
splb_slv0_Sl_addrAck => mb_plb_Sl_addrAck(6),
splb_slv0_Sl_SSize => mb_plb_Sl_SSize(12 to 13),
splb_slv0_Sl_wait => mb_plb_Sl_wait(6),
splb_slv0_Sl_rearbitrate => mb_plb_Sl_rearbitrate(6),
splb_slv0_Sl_wrDAck => mb_plb_Sl_wrDAck(6),
splb_slv0_Sl_wrComp => mb_plb_Sl_wrComp(6),
splb_slv0_Sl_wrBTerm => mb_plb_Sl_wrBTerm(6),
splb_slv0_Sl_rdDBus => mb_plb_Sl_rdDBus(384 to 447),
splb_slv0_Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(24 to 27),
splb_slv0_Sl_rdDAck => mb_plb_Sl_rdDAck(6),
splb_slv0_Sl_rdComp => mb_plb_Sl_rdComp(6),
splb_slv0_Sl_rdBTerm => mb_plb_Sl_rdBTerm(6),
splb_slv0_Sl_MBusy => mb_plb_Sl_MBusy(36 to 41),
splb_slv0_Sl_MWrErr => mb_plb_Sl_MWrErr(36 to 41),
splb_slv0_Sl_MRdErr => mb_plb_Sl_MRdErr(36 to 41),
splb_slv0_Sl_MIRQ => mb_plb_Sl_MIRQ(36 to 41)
);
nfa_accept_samples_generic_hw_top_1 : system_nfa_accept_samples_generic_hw_top_1_wrapper
port map (
aclk => clk_125_0000MHzPLL0,
aresetn => proc_sys_reset_0_Peripheral_aresetn(0),
indices_MPLB_Clk => net_gnd0,
indices_MPLB_Rst => ac0_plb_MPLB_Rst(5),
indices_M_request => ac0_plb_M_request(5),
indices_M_priority => ac0_plb_M_priority(10 to 11),
indices_M_busLock => ac0_plb_M_busLock(5),
indices_M_RNW => ac0_plb_M_RNW(5),
indices_M_BE => ac0_plb_M_BE(40 to 47),
indices_M_MSize => ac0_plb_M_MSize(10 to 11),
indices_M_size => ac0_plb_M_size(20 to 23),
indices_M_type => ac0_plb_M_type(15 to 17),
indices_M_TAttribute => ac0_plb_M_TAttribute(80 to 95),
indices_M_lockErr => ac0_plb_M_lockErr(5),
indices_M_abort => ac0_plb_M_abort(5),
indices_M_UABus => ac0_plb_M_UABus(160 to 191),
indices_M_ABus => ac0_plb_M_ABus(160 to 191),
indices_M_wrDBus => ac0_plb_M_wrDBus(320 to 383),
indices_M_wrBurst => ac0_plb_M_wrBurst(5),
indices_M_rdBurst => ac0_plb_M_rdBurst(5),
indices_PLB_MAddrAck => ac0_plb_PLB_MAddrAck(5),
indices_PLB_MSSize => ac0_plb_PLB_MSSize(10 to 11),
indices_PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate(5),
indices_PLB_MTimeout => ac0_plb_PLB_MTimeout(5),
indices_PLB_MBusy => ac0_plb_PLB_MBusy(5),
indices_PLB_MRdErr => ac0_plb_PLB_MRdErr(5),
indices_PLB_MWrErr => ac0_plb_PLB_MWrErr(5),
indices_PLB_MIRQ => ac0_plb_PLB_MIRQ(5),
indices_PLB_MRdDBus => ac0_plb_PLB_MRdDBus(320 to 383),
indices_PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr(20 to 23),
indices_PLB_MRdDAck => ac0_plb_PLB_MRdDAck(5),
indices_PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm(5),
indices_PLB_MWrDAck => ac0_plb_PLB_MWrDAck(5),
indices_PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm(5),
nfa_finals_buckets_MPLB_Clk => net_gnd0,
nfa_finals_buckets_MPLB_Rst => ac0_plb_MPLB_Rst(6),
nfa_finals_buckets_M_request => ac0_plb_M_request(6),
nfa_finals_buckets_M_priority => ac0_plb_M_priority(12 to 13),
nfa_finals_buckets_M_busLock => ac0_plb_M_busLock(6),
nfa_finals_buckets_M_RNW => ac0_plb_M_RNW(6),
nfa_finals_buckets_M_BE => ac0_plb_M_BE(48 to 55),
nfa_finals_buckets_M_MSize => ac0_plb_M_MSize(12 to 13),
nfa_finals_buckets_M_size => ac0_plb_M_size(24 to 27),
nfa_finals_buckets_M_type => ac0_plb_M_type(18 to 20),
nfa_finals_buckets_M_TAttribute => ac0_plb_M_TAttribute(96 to 111),
nfa_finals_buckets_M_lockErr => ac0_plb_M_lockErr(6),
nfa_finals_buckets_M_abort => ac0_plb_M_abort(6),
nfa_finals_buckets_M_UABus => ac0_plb_M_UABus(192 to 223),
nfa_finals_buckets_M_ABus => ac0_plb_M_ABus(192 to 223),
nfa_finals_buckets_M_wrDBus => ac0_plb_M_wrDBus(384 to 447),
nfa_finals_buckets_M_wrBurst => ac0_plb_M_wrBurst(6),
nfa_finals_buckets_M_rdBurst => ac0_plb_M_rdBurst(6),
nfa_finals_buckets_PLB_MAddrAck => ac0_plb_PLB_MAddrAck(6),
nfa_finals_buckets_PLB_MSSize => ac0_plb_PLB_MSSize(12 to 13),
nfa_finals_buckets_PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate(6),
nfa_finals_buckets_PLB_MTimeout => ac0_plb_PLB_MTimeout(6),
nfa_finals_buckets_PLB_MBusy => ac0_plb_PLB_MBusy(6),
nfa_finals_buckets_PLB_MRdErr => ac0_plb_PLB_MRdErr(6),
nfa_finals_buckets_PLB_MWrErr => ac0_plb_PLB_MWrErr(6),
nfa_finals_buckets_PLB_MIRQ => ac0_plb_PLB_MIRQ(6),
nfa_finals_buckets_PLB_MRdDBus => ac0_plb_PLB_MRdDBus(384 to 447),
nfa_finals_buckets_PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr(24 to 27),
nfa_finals_buckets_PLB_MRdDAck => ac0_plb_PLB_MRdDAck(6),
nfa_finals_buckets_PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm(6),
nfa_finals_buckets_PLB_MWrDAck => ac0_plb_PLB_MWrDAck(6),
nfa_finals_buckets_PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm(6),
nfa_forward_buckets_MPLB_Clk => net_gnd0,
nfa_forward_buckets_MPLB_Rst => ac0_plb_MPLB_Rst(7),
nfa_forward_buckets_M_request => ac0_plb_M_request(7),
nfa_forward_buckets_M_priority => ac0_plb_M_priority(14 to 15),
nfa_forward_buckets_M_busLock => ac0_plb_M_busLock(7),
nfa_forward_buckets_M_RNW => ac0_plb_M_RNW(7),
nfa_forward_buckets_M_BE => ac0_plb_M_BE(56 to 63),
nfa_forward_buckets_M_MSize => ac0_plb_M_MSize(14 to 15),
nfa_forward_buckets_M_size => ac0_plb_M_size(28 to 31),
nfa_forward_buckets_M_type => ac0_plb_M_type(21 to 23),
nfa_forward_buckets_M_TAttribute => ac0_plb_M_TAttribute(112 to 127),
nfa_forward_buckets_M_lockErr => ac0_plb_M_lockErr(7),
nfa_forward_buckets_M_abort => ac0_plb_M_abort(7),
nfa_forward_buckets_M_UABus => ac0_plb_M_UABus(224 to 255),
nfa_forward_buckets_M_ABus => ac0_plb_M_ABus(224 to 255),
nfa_forward_buckets_M_wrDBus => ac0_plb_M_wrDBus(448 to 511),
nfa_forward_buckets_M_wrBurst => ac0_plb_M_wrBurst(7),
nfa_forward_buckets_M_rdBurst => ac0_plb_M_rdBurst(7),
nfa_forward_buckets_PLB_MAddrAck => ac0_plb_PLB_MAddrAck(7),
nfa_forward_buckets_PLB_MSSize => ac0_plb_PLB_MSSize(14 to 15),
nfa_forward_buckets_PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate(7),
nfa_forward_buckets_PLB_MTimeout => ac0_plb_PLB_MTimeout(7),
nfa_forward_buckets_PLB_MBusy => ac0_plb_PLB_MBusy(7),
nfa_forward_buckets_PLB_MRdErr => ac0_plb_PLB_MRdErr(7),
nfa_forward_buckets_PLB_MWrErr => ac0_plb_PLB_MWrErr(7),
nfa_forward_buckets_PLB_MIRQ => ac0_plb_PLB_MIRQ(7),
nfa_forward_buckets_PLB_MRdDBus => ac0_plb_PLB_MRdDBus(448 to 511),
nfa_forward_buckets_PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr(28 to 31),
nfa_forward_buckets_PLB_MRdDAck => ac0_plb_PLB_MRdDAck(7),
nfa_forward_buckets_PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm(7),
nfa_forward_buckets_PLB_MWrDAck => ac0_plb_PLB_MWrDAck(7),
nfa_forward_buckets_PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm(7),
nfa_initials_buckets_MPLB_Clk => net_gnd0,
nfa_initials_buckets_MPLB_Rst => ac0_plb_MPLB_Rst(8),
nfa_initials_buckets_M_request => ac0_plb_M_request(8),
nfa_initials_buckets_M_priority => ac0_plb_M_priority(16 to 17),
nfa_initials_buckets_M_busLock => ac0_plb_M_busLock(8),
nfa_initials_buckets_M_RNW => ac0_plb_M_RNW(8),
nfa_initials_buckets_M_BE => ac0_plb_M_BE(64 to 71),
nfa_initials_buckets_M_MSize => ac0_plb_M_MSize(16 to 17),
nfa_initials_buckets_M_size => ac0_plb_M_size(32 to 35),
nfa_initials_buckets_M_type => ac0_plb_M_type(24 to 26),
nfa_initials_buckets_M_TAttribute => ac0_plb_M_TAttribute(128 to 143),
nfa_initials_buckets_M_lockErr => ac0_plb_M_lockErr(8),
nfa_initials_buckets_M_abort => ac0_plb_M_abort(8),
nfa_initials_buckets_M_UABus => ac0_plb_M_UABus(256 to 287),
nfa_initials_buckets_M_ABus => ac0_plb_M_ABus(256 to 287),
nfa_initials_buckets_M_wrDBus => ac0_plb_M_wrDBus(512 to 575),
nfa_initials_buckets_M_wrBurst => ac0_plb_M_wrBurst(8),
nfa_initials_buckets_M_rdBurst => ac0_plb_M_rdBurst(8),
nfa_initials_buckets_PLB_MAddrAck => ac0_plb_PLB_MAddrAck(8),
nfa_initials_buckets_PLB_MSSize => ac0_plb_PLB_MSSize(16 to 17),
nfa_initials_buckets_PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate(8),
nfa_initials_buckets_PLB_MTimeout => ac0_plb_PLB_MTimeout(8),
nfa_initials_buckets_PLB_MBusy => ac0_plb_PLB_MBusy(8),
nfa_initials_buckets_PLB_MRdErr => ac0_plb_PLB_MRdErr(8),
nfa_initials_buckets_PLB_MWrErr => ac0_plb_PLB_MWrErr(8),
nfa_initials_buckets_PLB_MIRQ => ac0_plb_PLB_MIRQ(8),
nfa_initials_buckets_PLB_MRdDBus => ac0_plb_PLB_MRdDBus(512 to 575),
nfa_initials_buckets_PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr(32 to 35),
nfa_initials_buckets_PLB_MRdDAck => ac0_plb_PLB_MRdDAck(8),
nfa_initials_buckets_PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm(8),
nfa_initials_buckets_PLB_MWrDAck => ac0_plb_PLB_MWrDAck(8),
nfa_initials_buckets_PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm(8),
sample_buffer_MPLB_Clk => net_gnd0,
sample_buffer_MPLB_Rst => ac0_plb_MPLB_Rst(9),
sample_buffer_M_request => ac0_plb_M_request(9),
sample_buffer_M_priority => ac0_plb_M_priority(18 to 19),
sample_buffer_M_busLock => ac0_plb_M_busLock(9),
sample_buffer_M_RNW => ac0_plb_M_RNW(9),
sample_buffer_M_BE => ac0_plb_M_BE(72 to 79),
sample_buffer_M_MSize => ac0_plb_M_MSize(18 to 19),
sample_buffer_M_size => ac0_plb_M_size(36 to 39),
sample_buffer_M_type => ac0_plb_M_type(27 to 29),
sample_buffer_M_TAttribute => ac0_plb_M_TAttribute(144 to 159),
sample_buffer_M_lockErr => ac0_plb_M_lockErr(9),
sample_buffer_M_abort => ac0_plb_M_abort(9),
sample_buffer_M_UABus => ac0_plb_M_UABus(288 to 319),
sample_buffer_M_ABus => ac0_plb_M_ABus(288 to 319),
sample_buffer_M_wrDBus => ac0_plb_M_wrDBus(576 to 639),
sample_buffer_M_wrBurst => ac0_plb_M_wrBurst(9),
sample_buffer_M_rdBurst => ac0_plb_M_rdBurst(9),
sample_buffer_PLB_MAddrAck => ac0_plb_PLB_MAddrAck(9),
sample_buffer_PLB_MSSize => ac0_plb_PLB_MSSize(18 to 19),
sample_buffer_PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate(9),
sample_buffer_PLB_MTimeout => ac0_plb_PLB_MTimeout(9),
sample_buffer_PLB_MBusy => ac0_plb_PLB_MBusy(9),
sample_buffer_PLB_MRdErr => ac0_plb_PLB_MRdErr(9),
sample_buffer_PLB_MWrErr => ac0_plb_PLB_MWrErr(9),
sample_buffer_PLB_MIRQ => ac0_plb_PLB_MIRQ(9),
sample_buffer_PLB_MRdDBus => ac0_plb_PLB_MRdDBus(576 to 639),
sample_buffer_PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr(36 to 39),
sample_buffer_PLB_MRdDAck => ac0_plb_PLB_MRdDAck(9),
sample_buffer_PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm(9),
sample_buffer_PLB_MWrDAck => ac0_plb_PLB_MWrDAck(9),
sample_buffer_PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm(9),
splb_slv0_SPLB_Clk => clk_125_0000MHzPLL0,
splb_slv0_SPLB_Rst => mb_plb_SPLB_Rst(7),
splb_slv0_PLB_ABus => mb_plb_PLB_ABus,
splb_slv0_PLB_UABus => mb_plb_PLB_UABus,
splb_slv0_PLB_PAValid => mb_plb_PLB_PAValid,
splb_slv0_PLB_SAValid => mb_plb_PLB_SAValid,
splb_slv0_PLB_rdPrim => mb_plb_PLB_rdPrim(7),
splb_slv0_PLB_wrPrim => mb_plb_PLB_wrPrim(7),
splb_slv0_PLB_masterID => mb_plb_PLB_masterID,
splb_slv0_PLB_abort => mb_plb_PLB_abort,
splb_slv0_PLB_busLock => mb_plb_PLB_busLock,
splb_slv0_PLB_RNW => mb_plb_PLB_RNW,
splb_slv0_PLB_BE => mb_plb_PLB_BE,
splb_slv0_PLB_MSize => mb_plb_PLB_MSize,
splb_slv0_PLB_size => mb_plb_PLB_size,
splb_slv0_PLB_type => mb_plb_PLB_type,
splb_slv0_PLB_lockErr => mb_plb_PLB_lockErr,
splb_slv0_PLB_wrDBus => mb_plb_PLB_wrDBus,
splb_slv0_PLB_wrBurst => mb_plb_PLB_wrBurst,
splb_slv0_PLB_rdBurst => mb_plb_PLB_rdBurst,
splb_slv0_PLB_wrPendReq => mb_plb_PLB_wrPendReq,
splb_slv0_PLB_rdPendReq => mb_plb_PLB_rdPendReq,
splb_slv0_PLB_wrPendPri => mb_plb_PLB_wrPendPri,
splb_slv0_PLB_rdPendPri => mb_plb_PLB_rdPendPri,
splb_slv0_PLB_reqPri => mb_plb_PLB_reqPri,
splb_slv0_PLB_TAttribute => mb_plb_PLB_TAttribute,
splb_slv0_Sl_addrAck => mb_plb_Sl_addrAck(7),
splb_slv0_Sl_SSize => mb_plb_Sl_SSize(14 to 15),
splb_slv0_Sl_wait => mb_plb_Sl_wait(7),
splb_slv0_Sl_rearbitrate => mb_plb_Sl_rearbitrate(7),
splb_slv0_Sl_wrDAck => mb_plb_Sl_wrDAck(7),
splb_slv0_Sl_wrComp => mb_plb_Sl_wrComp(7),
splb_slv0_Sl_wrBTerm => mb_plb_Sl_wrBTerm(7),
splb_slv0_Sl_rdDBus => mb_plb_Sl_rdDBus(448 to 511),
splb_slv0_Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(28 to 31),
splb_slv0_Sl_rdDAck => mb_plb_Sl_rdDAck(7),
splb_slv0_Sl_rdComp => mb_plb_Sl_rdComp(7),
splb_slv0_Sl_rdBTerm => mb_plb_Sl_rdBTerm(7),
splb_slv0_Sl_MBusy => mb_plb_Sl_MBusy(42 to 47),
splb_slv0_Sl_MWrErr => mb_plb_Sl_MWrErr(42 to 47),
splb_slv0_Sl_MRdErr => mb_plb_Sl_MRdErr(42 to 47),
splb_slv0_Sl_MIRQ => mb_plb_Sl_MIRQ(42 to 47)
);
nfa_accept_samples_generic_hw_top_2 : system_nfa_accept_samples_generic_hw_top_2_wrapper
port map (
aclk => clk_125_0000MHzPLL0,
aresetn => proc_sys_reset_0_Peripheral_aresetn(0),
indices_MPLB_Clk => net_gnd0,
indices_MPLB_Rst => ac0_plb_MPLB_Rst(10),
indices_M_request => ac0_plb_M_request(10),
indices_M_priority => ac0_plb_M_priority(20 to 21),
indices_M_busLock => ac0_plb_M_busLock(10),
indices_M_RNW => ac0_plb_M_RNW(10),
indices_M_BE => ac0_plb_M_BE(80 to 87),
indices_M_MSize => ac0_plb_M_MSize(20 to 21),
indices_M_size => ac0_plb_M_size(40 to 43),
indices_M_type => ac0_plb_M_type(30 to 32),
indices_M_TAttribute => ac0_plb_M_TAttribute(160 to 175),
indices_M_lockErr => ac0_plb_M_lockErr(10),
indices_M_abort => ac0_plb_M_abort(10),
indices_M_UABus => ac0_plb_M_UABus(320 to 351),
indices_M_ABus => ac0_plb_M_ABus(320 to 351),
indices_M_wrDBus => ac0_plb_M_wrDBus(640 to 703),
indices_M_wrBurst => ac0_plb_M_wrBurst(10),
indices_M_rdBurst => ac0_plb_M_rdBurst(10),
indices_PLB_MAddrAck => ac0_plb_PLB_MAddrAck(10),
indices_PLB_MSSize => ac0_plb_PLB_MSSize(20 to 21),
indices_PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate(10),
indices_PLB_MTimeout => ac0_plb_PLB_MTimeout(10),
indices_PLB_MBusy => ac0_plb_PLB_MBusy(10),
indices_PLB_MRdErr => ac0_plb_PLB_MRdErr(10),
indices_PLB_MWrErr => ac0_plb_PLB_MWrErr(10),
indices_PLB_MIRQ => ac0_plb_PLB_MIRQ(10),
indices_PLB_MRdDBus => ac0_plb_PLB_MRdDBus(640 to 703),
indices_PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr(40 to 43),
indices_PLB_MRdDAck => ac0_plb_PLB_MRdDAck(10),
indices_PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm(10),
indices_PLB_MWrDAck => ac0_plb_PLB_MWrDAck(10),
indices_PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm(10),
nfa_finals_buckets_MPLB_Clk => net_gnd0,
nfa_finals_buckets_MPLB_Rst => ac0_plb_MPLB_Rst(11),
nfa_finals_buckets_M_request => ac0_plb_M_request(11),
nfa_finals_buckets_M_priority => ac0_plb_M_priority(22 to 23),
nfa_finals_buckets_M_busLock => ac0_plb_M_busLock(11),
nfa_finals_buckets_M_RNW => ac0_plb_M_RNW(11),
nfa_finals_buckets_M_BE => ac0_plb_M_BE(88 to 95),
nfa_finals_buckets_M_MSize => ac0_plb_M_MSize(22 to 23),
nfa_finals_buckets_M_size => ac0_plb_M_size(44 to 47),
nfa_finals_buckets_M_type => ac0_plb_M_type(33 to 35),
nfa_finals_buckets_M_TAttribute => ac0_plb_M_TAttribute(176 to 191),
nfa_finals_buckets_M_lockErr => ac0_plb_M_lockErr(11),
nfa_finals_buckets_M_abort => ac0_plb_M_abort(11),
nfa_finals_buckets_M_UABus => ac0_plb_M_UABus(352 to 383),
nfa_finals_buckets_M_ABus => ac0_plb_M_ABus(352 to 383),
nfa_finals_buckets_M_wrDBus => ac0_plb_M_wrDBus(704 to 767),
nfa_finals_buckets_M_wrBurst => ac0_plb_M_wrBurst(11),
nfa_finals_buckets_M_rdBurst => ac0_plb_M_rdBurst(11),
nfa_finals_buckets_PLB_MAddrAck => ac0_plb_PLB_MAddrAck(11),
nfa_finals_buckets_PLB_MSSize => ac0_plb_PLB_MSSize(22 to 23),
nfa_finals_buckets_PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate(11),
nfa_finals_buckets_PLB_MTimeout => ac0_plb_PLB_MTimeout(11),
nfa_finals_buckets_PLB_MBusy => ac0_plb_PLB_MBusy(11),
nfa_finals_buckets_PLB_MRdErr => ac0_plb_PLB_MRdErr(11),
nfa_finals_buckets_PLB_MWrErr => ac0_plb_PLB_MWrErr(11),
nfa_finals_buckets_PLB_MIRQ => ac0_plb_PLB_MIRQ(11),
nfa_finals_buckets_PLB_MRdDBus => ac0_plb_PLB_MRdDBus(704 to 767),
nfa_finals_buckets_PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr(44 to 47),
nfa_finals_buckets_PLB_MRdDAck => ac0_plb_PLB_MRdDAck(11),
nfa_finals_buckets_PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm(11),
nfa_finals_buckets_PLB_MWrDAck => ac0_plb_PLB_MWrDAck(11),
nfa_finals_buckets_PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm(11),
nfa_forward_buckets_MPLB_Clk => net_gnd0,
nfa_forward_buckets_MPLB_Rst => ac0_plb_MPLB_Rst(12),
nfa_forward_buckets_M_request => ac0_plb_M_request(12),
nfa_forward_buckets_M_priority => ac0_plb_M_priority(24 to 25),
nfa_forward_buckets_M_busLock => ac0_plb_M_busLock(12),
nfa_forward_buckets_M_RNW => ac0_plb_M_RNW(12),
nfa_forward_buckets_M_BE => ac0_plb_M_BE(96 to 103),
nfa_forward_buckets_M_MSize => ac0_plb_M_MSize(24 to 25),
nfa_forward_buckets_M_size => ac0_plb_M_size(48 to 51),
nfa_forward_buckets_M_type => ac0_plb_M_type(36 to 38),
nfa_forward_buckets_M_TAttribute => ac0_plb_M_TAttribute(192 to 207),
nfa_forward_buckets_M_lockErr => ac0_plb_M_lockErr(12),
nfa_forward_buckets_M_abort => ac0_plb_M_abort(12),
nfa_forward_buckets_M_UABus => ac0_plb_M_UABus(384 to 415),
nfa_forward_buckets_M_ABus => ac0_plb_M_ABus(384 to 415),
nfa_forward_buckets_M_wrDBus => ac0_plb_M_wrDBus(768 to 831),
nfa_forward_buckets_M_wrBurst => ac0_plb_M_wrBurst(12),
nfa_forward_buckets_M_rdBurst => ac0_plb_M_rdBurst(12),
nfa_forward_buckets_PLB_MAddrAck => ac0_plb_PLB_MAddrAck(12),
nfa_forward_buckets_PLB_MSSize => ac0_plb_PLB_MSSize(24 to 25),
nfa_forward_buckets_PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate(12),
nfa_forward_buckets_PLB_MTimeout => ac0_plb_PLB_MTimeout(12),
nfa_forward_buckets_PLB_MBusy => ac0_plb_PLB_MBusy(12),
nfa_forward_buckets_PLB_MRdErr => ac0_plb_PLB_MRdErr(12),
nfa_forward_buckets_PLB_MWrErr => ac0_plb_PLB_MWrErr(12),
nfa_forward_buckets_PLB_MIRQ => ac0_plb_PLB_MIRQ(12),
nfa_forward_buckets_PLB_MRdDBus => ac0_plb_PLB_MRdDBus(768 to 831),
nfa_forward_buckets_PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr(48 to 51),
nfa_forward_buckets_PLB_MRdDAck => ac0_plb_PLB_MRdDAck(12),
nfa_forward_buckets_PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm(12),
nfa_forward_buckets_PLB_MWrDAck => ac0_plb_PLB_MWrDAck(12),
nfa_forward_buckets_PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm(12),
nfa_initials_buckets_MPLB_Clk => net_gnd0,
nfa_initials_buckets_MPLB_Rst => ac0_plb_MPLB_Rst(13),
nfa_initials_buckets_M_request => ac0_plb_M_request(13),
nfa_initials_buckets_M_priority => ac0_plb_M_priority(26 to 27),
nfa_initials_buckets_M_busLock => ac0_plb_M_busLock(13),
nfa_initials_buckets_M_RNW => ac0_plb_M_RNW(13),
nfa_initials_buckets_M_BE => ac0_plb_M_BE(104 to 111),
nfa_initials_buckets_M_MSize => ac0_plb_M_MSize(26 to 27),
nfa_initials_buckets_M_size => ac0_plb_M_size(52 to 55),
nfa_initials_buckets_M_type => ac0_plb_M_type(39 to 41),
nfa_initials_buckets_M_TAttribute => ac0_plb_M_TAttribute(208 to 223),
nfa_initials_buckets_M_lockErr => ac0_plb_M_lockErr(13),
nfa_initials_buckets_M_abort => ac0_plb_M_abort(13),
nfa_initials_buckets_M_UABus => ac0_plb_M_UABus(416 to 447),
nfa_initials_buckets_M_ABus => ac0_plb_M_ABus(416 to 447),
nfa_initials_buckets_M_wrDBus => ac0_plb_M_wrDBus(832 to 895),
nfa_initials_buckets_M_wrBurst => ac0_plb_M_wrBurst(13),
nfa_initials_buckets_M_rdBurst => ac0_plb_M_rdBurst(13),
nfa_initials_buckets_PLB_MAddrAck => ac0_plb_PLB_MAddrAck(13),
nfa_initials_buckets_PLB_MSSize => ac0_plb_PLB_MSSize(26 to 27),
nfa_initials_buckets_PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate(13),
nfa_initials_buckets_PLB_MTimeout => ac0_plb_PLB_MTimeout(13),
nfa_initials_buckets_PLB_MBusy => ac0_plb_PLB_MBusy(13),
nfa_initials_buckets_PLB_MRdErr => ac0_plb_PLB_MRdErr(13),
nfa_initials_buckets_PLB_MWrErr => ac0_plb_PLB_MWrErr(13),
nfa_initials_buckets_PLB_MIRQ => ac0_plb_PLB_MIRQ(13),
nfa_initials_buckets_PLB_MRdDBus => ac0_plb_PLB_MRdDBus(832 to 895),
nfa_initials_buckets_PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr(52 to 55),
nfa_initials_buckets_PLB_MRdDAck => ac0_plb_PLB_MRdDAck(13),
nfa_initials_buckets_PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm(13),
nfa_initials_buckets_PLB_MWrDAck => ac0_plb_PLB_MWrDAck(13),
nfa_initials_buckets_PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm(13),
sample_buffer_MPLB_Clk => net_gnd0,
sample_buffer_MPLB_Rst => ac0_plb_MPLB_Rst(14),
sample_buffer_M_request => ac0_plb_M_request(14),
sample_buffer_M_priority => ac0_plb_M_priority(28 to 29),
sample_buffer_M_busLock => ac0_plb_M_busLock(14),
sample_buffer_M_RNW => ac0_plb_M_RNW(14),
sample_buffer_M_BE => ac0_plb_M_BE(112 to 119),
sample_buffer_M_MSize => ac0_plb_M_MSize(28 to 29),
sample_buffer_M_size => ac0_plb_M_size(56 to 59),
sample_buffer_M_type => ac0_plb_M_type(42 to 44),
sample_buffer_M_TAttribute => ac0_plb_M_TAttribute(224 to 239),
sample_buffer_M_lockErr => ac0_plb_M_lockErr(14),
sample_buffer_M_abort => ac0_plb_M_abort(14),
sample_buffer_M_UABus => ac0_plb_M_UABus(448 to 479),
sample_buffer_M_ABus => ac0_plb_M_ABus(448 to 479),
sample_buffer_M_wrDBus => ac0_plb_M_wrDBus(896 to 959),
sample_buffer_M_wrBurst => ac0_plb_M_wrBurst(14),
sample_buffer_M_rdBurst => ac0_plb_M_rdBurst(14),
sample_buffer_PLB_MAddrAck => ac0_plb_PLB_MAddrAck(14),
sample_buffer_PLB_MSSize => ac0_plb_PLB_MSSize(28 to 29),
sample_buffer_PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate(14),
sample_buffer_PLB_MTimeout => ac0_plb_PLB_MTimeout(14),
sample_buffer_PLB_MBusy => ac0_plb_PLB_MBusy(14),
sample_buffer_PLB_MRdErr => ac0_plb_PLB_MRdErr(14),
sample_buffer_PLB_MWrErr => ac0_plb_PLB_MWrErr(14),
sample_buffer_PLB_MIRQ => ac0_plb_PLB_MIRQ(14),
sample_buffer_PLB_MRdDBus => ac0_plb_PLB_MRdDBus(896 to 959),
sample_buffer_PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr(56 to 59),
sample_buffer_PLB_MRdDAck => ac0_plb_PLB_MRdDAck(14),
sample_buffer_PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm(14),
sample_buffer_PLB_MWrDAck => ac0_plb_PLB_MWrDAck(14),
sample_buffer_PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm(14),
splb_slv0_SPLB_Clk => clk_125_0000MHzPLL0,
splb_slv0_SPLB_Rst => mb_plb_SPLB_Rst(8),
splb_slv0_PLB_ABus => mb_plb_PLB_ABus,
splb_slv0_PLB_UABus => mb_plb_PLB_UABus,
splb_slv0_PLB_PAValid => mb_plb_PLB_PAValid,
splb_slv0_PLB_SAValid => mb_plb_PLB_SAValid,
splb_slv0_PLB_rdPrim => mb_plb_PLB_rdPrim(8),
splb_slv0_PLB_wrPrim => mb_plb_PLB_wrPrim(8),
splb_slv0_PLB_masterID => mb_plb_PLB_masterID,
splb_slv0_PLB_abort => mb_plb_PLB_abort,
splb_slv0_PLB_busLock => mb_plb_PLB_busLock,
splb_slv0_PLB_RNW => mb_plb_PLB_RNW,
splb_slv0_PLB_BE => mb_plb_PLB_BE,
splb_slv0_PLB_MSize => mb_plb_PLB_MSize,
splb_slv0_PLB_size => mb_plb_PLB_size,
splb_slv0_PLB_type => mb_plb_PLB_type,
splb_slv0_PLB_lockErr => mb_plb_PLB_lockErr,
splb_slv0_PLB_wrDBus => mb_plb_PLB_wrDBus,
splb_slv0_PLB_wrBurst => mb_plb_PLB_wrBurst,
splb_slv0_PLB_rdBurst => mb_plb_PLB_rdBurst,
splb_slv0_PLB_wrPendReq => mb_plb_PLB_wrPendReq,
splb_slv0_PLB_rdPendReq => mb_plb_PLB_rdPendReq,
splb_slv0_PLB_wrPendPri => mb_plb_PLB_wrPendPri,
splb_slv0_PLB_rdPendPri => mb_plb_PLB_rdPendPri,
splb_slv0_PLB_reqPri => mb_plb_PLB_reqPri,
splb_slv0_PLB_TAttribute => mb_plb_PLB_TAttribute,
splb_slv0_Sl_addrAck => mb_plb_Sl_addrAck(8),
splb_slv0_Sl_SSize => mb_plb_Sl_SSize(16 to 17),
splb_slv0_Sl_wait => mb_plb_Sl_wait(8),
splb_slv0_Sl_rearbitrate => mb_plb_Sl_rearbitrate(8),
splb_slv0_Sl_wrDAck => mb_plb_Sl_wrDAck(8),
splb_slv0_Sl_wrComp => mb_plb_Sl_wrComp(8),
splb_slv0_Sl_wrBTerm => mb_plb_Sl_wrBTerm(8),
splb_slv0_Sl_rdDBus => mb_plb_Sl_rdDBus(512 to 575),
splb_slv0_Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(32 to 35),
splb_slv0_Sl_rdDAck => mb_plb_Sl_rdDAck(8),
splb_slv0_Sl_rdComp => mb_plb_Sl_rdComp(8),
splb_slv0_Sl_rdBTerm => mb_plb_Sl_rdBTerm(8),
splb_slv0_Sl_MBusy => mb_plb_Sl_MBusy(48 to 53),
splb_slv0_Sl_MWrErr => mb_plb_Sl_MWrErr(48 to 53),
splb_slv0_Sl_MRdErr => mb_plb_Sl_MRdErr(48 to 53),
splb_slv0_Sl_MIRQ => mb_plb_Sl_MIRQ(48 to 53)
);
nfa_accept_samples_generic_hw_top_3 : system_nfa_accept_samples_generic_hw_top_3_wrapper
port map (
aclk => clk_125_0000MHzPLL0,
aresetn => proc_sys_reset_0_Peripheral_aresetn(0),
indices_MPLB_Clk => net_gnd0,
indices_MPLB_Rst => ac1_plb_MPLB_Rst(0),
indices_M_request => ac1_plb_M_request(0),
indices_M_priority => ac1_plb_M_priority(0 to 1),
indices_M_busLock => ac1_plb_M_busLock(0),
indices_M_RNW => ac1_plb_M_RNW(0),
indices_M_BE => ac1_plb_M_BE(0 to 7),
indices_M_MSize => ac1_plb_M_MSize(0 to 1),
indices_M_size => ac1_plb_M_size(0 to 3),
indices_M_type => ac1_plb_M_type(0 to 2),
indices_M_TAttribute => ac1_plb_M_TAttribute(0 to 15),
indices_M_lockErr => ac1_plb_M_lockErr(0),
indices_M_abort => ac1_plb_M_abort(0),
indices_M_UABus => ac1_plb_M_UABus(0 to 31),
indices_M_ABus => ac1_plb_M_ABus(0 to 31),
indices_M_wrDBus => ac1_plb_M_wrDBus(0 to 63),
indices_M_wrBurst => ac1_plb_M_wrBurst(0),
indices_M_rdBurst => ac1_plb_M_rdBurst(0),
indices_PLB_MAddrAck => ac1_plb_PLB_MAddrAck(0),
indices_PLB_MSSize => ac1_plb_PLB_MSSize(0 to 1),
indices_PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate(0),
indices_PLB_MTimeout => ac1_plb_PLB_MTimeout(0),
indices_PLB_MBusy => ac1_plb_PLB_MBusy(0),
indices_PLB_MRdErr => ac1_plb_PLB_MRdErr(0),
indices_PLB_MWrErr => ac1_plb_PLB_MWrErr(0),
indices_PLB_MIRQ => ac1_plb_PLB_MIRQ(0),
indices_PLB_MRdDBus => ac1_plb_PLB_MRdDBus(0 to 63),
indices_PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr(0 to 3),
indices_PLB_MRdDAck => ac1_plb_PLB_MRdDAck(0),
indices_PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm(0),
indices_PLB_MWrDAck => ac1_plb_PLB_MWrDAck(0),
indices_PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm(0),
nfa_finals_buckets_MPLB_Clk => net_gnd0,
nfa_finals_buckets_MPLB_Rst => ac1_plb_MPLB_Rst(1),
nfa_finals_buckets_M_request => ac1_plb_M_request(1),
nfa_finals_buckets_M_priority => ac1_plb_M_priority(2 to 3),
nfa_finals_buckets_M_busLock => ac1_plb_M_busLock(1),
nfa_finals_buckets_M_RNW => ac1_plb_M_RNW(1),
nfa_finals_buckets_M_BE => ac1_plb_M_BE(8 to 15),
nfa_finals_buckets_M_MSize => ac1_plb_M_MSize(2 to 3),
nfa_finals_buckets_M_size => ac1_plb_M_size(4 to 7),
nfa_finals_buckets_M_type => ac1_plb_M_type(3 to 5),
nfa_finals_buckets_M_TAttribute => ac1_plb_M_TAttribute(16 to 31),
nfa_finals_buckets_M_lockErr => ac1_plb_M_lockErr(1),
nfa_finals_buckets_M_abort => ac1_plb_M_abort(1),
nfa_finals_buckets_M_UABus => ac1_plb_M_UABus(32 to 63),
nfa_finals_buckets_M_ABus => ac1_plb_M_ABus(32 to 63),
nfa_finals_buckets_M_wrDBus => ac1_plb_M_wrDBus(64 to 127),
nfa_finals_buckets_M_wrBurst => ac1_plb_M_wrBurst(1),
nfa_finals_buckets_M_rdBurst => ac1_plb_M_rdBurst(1),
nfa_finals_buckets_PLB_MAddrAck => ac1_plb_PLB_MAddrAck(1),
nfa_finals_buckets_PLB_MSSize => ac1_plb_PLB_MSSize(2 to 3),
nfa_finals_buckets_PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate(1),
nfa_finals_buckets_PLB_MTimeout => ac1_plb_PLB_MTimeout(1),
nfa_finals_buckets_PLB_MBusy => ac1_plb_PLB_MBusy(1),
nfa_finals_buckets_PLB_MRdErr => ac1_plb_PLB_MRdErr(1),
nfa_finals_buckets_PLB_MWrErr => ac1_plb_PLB_MWrErr(1),
nfa_finals_buckets_PLB_MIRQ => ac1_plb_PLB_MIRQ(1),
nfa_finals_buckets_PLB_MRdDBus => ac1_plb_PLB_MRdDBus(64 to 127),
nfa_finals_buckets_PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr(4 to 7),
nfa_finals_buckets_PLB_MRdDAck => ac1_plb_PLB_MRdDAck(1),
nfa_finals_buckets_PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm(1),
nfa_finals_buckets_PLB_MWrDAck => ac1_plb_PLB_MWrDAck(1),
nfa_finals_buckets_PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm(1),
nfa_forward_buckets_MPLB_Clk => net_gnd0,
nfa_forward_buckets_MPLB_Rst => ac1_plb_MPLB_Rst(2),
nfa_forward_buckets_M_request => ac1_plb_M_request(2),
nfa_forward_buckets_M_priority => ac1_plb_M_priority(4 to 5),
nfa_forward_buckets_M_busLock => ac1_plb_M_busLock(2),
nfa_forward_buckets_M_RNW => ac1_plb_M_RNW(2),
nfa_forward_buckets_M_BE => ac1_plb_M_BE(16 to 23),
nfa_forward_buckets_M_MSize => ac1_plb_M_MSize(4 to 5),
nfa_forward_buckets_M_size => ac1_plb_M_size(8 to 11),
nfa_forward_buckets_M_type => ac1_plb_M_type(6 to 8),
nfa_forward_buckets_M_TAttribute => ac1_plb_M_TAttribute(32 to 47),
nfa_forward_buckets_M_lockErr => ac1_plb_M_lockErr(2),
nfa_forward_buckets_M_abort => ac1_plb_M_abort(2),
nfa_forward_buckets_M_UABus => ac1_plb_M_UABus(64 to 95),
nfa_forward_buckets_M_ABus => ac1_plb_M_ABus(64 to 95),
nfa_forward_buckets_M_wrDBus => ac1_plb_M_wrDBus(128 to 191),
nfa_forward_buckets_M_wrBurst => ac1_plb_M_wrBurst(2),
nfa_forward_buckets_M_rdBurst => ac1_plb_M_rdBurst(2),
nfa_forward_buckets_PLB_MAddrAck => ac1_plb_PLB_MAddrAck(2),
nfa_forward_buckets_PLB_MSSize => ac1_plb_PLB_MSSize(4 to 5),
nfa_forward_buckets_PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate(2),
nfa_forward_buckets_PLB_MTimeout => ac1_plb_PLB_MTimeout(2),
nfa_forward_buckets_PLB_MBusy => ac1_plb_PLB_MBusy(2),
nfa_forward_buckets_PLB_MRdErr => ac1_plb_PLB_MRdErr(2),
nfa_forward_buckets_PLB_MWrErr => ac1_plb_PLB_MWrErr(2),
nfa_forward_buckets_PLB_MIRQ => ac1_plb_PLB_MIRQ(2),
nfa_forward_buckets_PLB_MRdDBus => ac1_plb_PLB_MRdDBus(128 to 191),
nfa_forward_buckets_PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr(8 to 11),
nfa_forward_buckets_PLB_MRdDAck => ac1_plb_PLB_MRdDAck(2),
nfa_forward_buckets_PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm(2),
nfa_forward_buckets_PLB_MWrDAck => ac1_plb_PLB_MWrDAck(2),
nfa_forward_buckets_PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm(2),
nfa_initials_buckets_MPLB_Clk => net_gnd0,
nfa_initials_buckets_MPLB_Rst => ac1_plb_MPLB_Rst(3),
nfa_initials_buckets_M_request => ac1_plb_M_request(3),
nfa_initials_buckets_M_priority => ac1_plb_M_priority(6 to 7),
nfa_initials_buckets_M_busLock => ac1_plb_M_busLock(3),
nfa_initials_buckets_M_RNW => ac1_plb_M_RNW(3),
nfa_initials_buckets_M_BE => ac1_plb_M_BE(24 to 31),
nfa_initials_buckets_M_MSize => ac1_plb_M_MSize(6 to 7),
nfa_initials_buckets_M_size => ac1_plb_M_size(12 to 15),
nfa_initials_buckets_M_type => ac1_plb_M_type(9 to 11),
nfa_initials_buckets_M_TAttribute => ac1_plb_M_TAttribute(48 to 63),
nfa_initials_buckets_M_lockErr => ac1_plb_M_lockErr(3),
nfa_initials_buckets_M_abort => ac1_plb_M_abort(3),
nfa_initials_buckets_M_UABus => ac1_plb_M_UABus(96 to 127),
nfa_initials_buckets_M_ABus => ac1_plb_M_ABus(96 to 127),
nfa_initials_buckets_M_wrDBus => ac1_plb_M_wrDBus(192 to 255),
nfa_initials_buckets_M_wrBurst => ac1_plb_M_wrBurst(3),
nfa_initials_buckets_M_rdBurst => ac1_plb_M_rdBurst(3),
nfa_initials_buckets_PLB_MAddrAck => ac1_plb_PLB_MAddrAck(3),
nfa_initials_buckets_PLB_MSSize => ac1_plb_PLB_MSSize(6 to 7),
nfa_initials_buckets_PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate(3),
nfa_initials_buckets_PLB_MTimeout => ac1_plb_PLB_MTimeout(3),
nfa_initials_buckets_PLB_MBusy => ac1_plb_PLB_MBusy(3),
nfa_initials_buckets_PLB_MRdErr => ac1_plb_PLB_MRdErr(3),
nfa_initials_buckets_PLB_MWrErr => ac1_plb_PLB_MWrErr(3),
nfa_initials_buckets_PLB_MIRQ => ac1_plb_PLB_MIRQ(3),
nfa_initials_buckets_PLB_MRdDBus => ac1_plb_PLB_MRdDBus(192 to 255),
nfa_initials_buckets_PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr(12 to 15),
nfa_initials_buckets_PLB_MRdDAck => ac1_plb_PLB_MRdDAck(3),
nfa_initials_buckets_PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm(3),
nfa_initials_buckets_PLB_MWrDAck => ac1_plb_PLB_MWrDAck(3),
nfa_initials_buckets_PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm(3),
sample_buffer_MPLB_Clk => net_gnd0,
sample_buffer_MPLB_Rst => ac1_plb_MPLB_Rst(4),
sample_buffer_M_request => ac1_plb_M_request(4),
sample_buffer_M_priority => ac1_plb_M_priority(8 to 9),
sample_buffer_M_busLock => ac1_plb_M_busLock(4),
sample_buffer_M_RNW => ac1_plb_M_RNW(4),
sample_buffer_M_BE => ac1_plb_M_BE(32 to 39),
sample_buffer_M_MSize => ac1_plb_M_MSize(8 to 9),
sample_buffer_M_size => ac1_plb_M_size(16 to 19),
sample_buffer_M_type => ac1_plb_M_type(12 to 14),
sample_buffer_M_TAttribute => ac1_plb_M_TAttribute(64 to 79),
sample_buffer_M_lockErr => ac1_plb_M_lockErr(4),
sample_buffer_M_abort => ac1_plb_M_abort(4),
sample_buffer_M_UABus => ac1_plb_M_UABus(128 to 159),
sample_buffer_M_ABus => ac1_plb_M_ABus(128 to 159),
sample_buffer_M_wrDBus => ac1_plb_M_wrDBus(256 to 319),
sample_buffer_M_wrBurst => ac1_plb_M_wrBurst(4),
sample_buffer_M_rdBurst => ac1_plb_M_rdBurst(4),
sample_buffer_PLB_MAddrAck => ac1_plb_PLB_MAddrAck(4),
sample_buffer_PLB_MSSize => ac1_plb_PLB_MSSize(8 to 9),
sample_buffer_PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate(4),
sample_buffer_PLB_MTimeout => ac1_plb_PLB_MTimeout(4),
sample_buffer_PLB_MBusy => ac1_plb_PLB_MBusy(4),
sample_buffer_PLB_MRdErr => ac1_plb_PLB_MRdErr(4),
sample_buffer_PLB_MWrErr => ac1_plb_PLB_MWrErr(4),
sample_buffer_PLB_MIRQ => ac1_plb_PLB_MIRQ(4),
sample_buffer_PLB_MRdDBus => ac1_plb_PLB_MRdDBus(256 to 319),
sample_buffer_PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr(16 to 19),
sample_buffer_PLB_MRdDAck => ac1_plb_PLB_MRdDAck(4),
sample_buffer_PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm(4),
sample_buffer_PLB_MWrDAck => ac1_plb_PLB_MWrDAck(4),
sample_buffer_PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm(4),
splb_slv0_SPLB_Clk => clk_125_0000MHzPLL0,
splb_slv0_SPLB_Rst => mb_plb_SPLB_Rst(9),
splb_slv0_PLB_ABus => mb_plb_PLB_ABus,
splb_slv0_PLB_UABus => mb_plb_PLB_UABus,
splb_slv0_PLB_PAValid => mb_plb_PLB_PAValid,
splb_slv0_PLB_SAValid => mb_plb_PLB_SAValid,
splb_slv0_PLB_rdPrim => mb_plb_PLB_rdPrim(9),
splb_slv0_PLB_wrPrim => mb_plb_PLB_wrPrim(9),
splb_slv0_PLB_masterID => mb_plb_PLB_masterID,
splb_slv0_PLB_abort => mb_plb_PLB_abort,
splb_slv0_PLB_busLock => mb_plb_PLB_busLock,
splb_slv0_PLB_RNW => mb_plb_PLB_RNW,
splb_slv0_PLB_BE => mb_plb_PLB_BE,
splb_slv0_PLB_MSize => mb_plb_PLB_MSize,
splb_slv0_PLB_size => mb_plb_PLB_size,
splb_slv0_PLB_type => mb_plb_PLB_type,
splb_slv0_PLB_lockErr => mb_plb_PLB_lockErr,
splb_slv0_PLB_wrDBus => mb_plb_PLB_wrDBus,
splb_slv0_PLB_wrBurst => mb_plb_PLB_wrBurst,
splb_slv0_PLB_rdBurst => mb_plb_PLB_rdBurst,
splb_slv0_PLB_wrPendReq => mb_plb_PLB_wrPendReq,
splb_slv0_PLB_rdPendReq => mb_plb_PLB_rdPendReq,
splb_slv0_PLB_wrPendPri => mb_plb_PLB_wrPendPri,
splb_slv0_PLB_rdPendPri => mb_plb_PLB_rdPendPri,
splb_slv0_PLB_reqPri => mb_plb_PLB_reqPri,
splb_slv0_PLB_TAttribute => mb_plb_PLB_TAttribute,
splb_slv0_Sl_addrAck => mb_plb_Sl_addrAck(9),
splb_slv0_Sl_SSize => mb_plb_Sl_SSize(18 to 19),
splb_slv0_Sl_wait => mb_plb_Sl_wait(9),
splb_slv0_Sl_rearbitrate => mb_plb_Sl_rearbitrate(9),
splb_slv0_Sl_wrDAck => mb_plb_Sl_wrDAck(9),
splb_slv0_Sl_wrComp => mb_plb_Sl_wrComp(9),
splb_slv0_Sl_wrBTerm => mb_plb_Sl_wrBTerm(9),
splb_slv0_Sl_rdDBus => mb_plb_Sl_rdDBus(576 to 639),
splb_slv0_Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(36 to 39),
splb_slv0_Sl_rdDAck => mb_plb_Sl_rdDAck(9),
splb_slv0_Sl_rdComp => mb_plb_Sl_rdComp(9),
splb_slv0_Sl_rdBTerm => mb_plb_Sl_rdBTerm(9),
splb_slv0_Sl_MBusy => mb_plb_Sl_MBusy(54 to 59),
splb_slv0_Sl_MWrErr => mb_plb_Sl_MWrErr(54 to 59),
splb_slv0_Sl_MRdErr => mb_plb_Sl_MRdErr(54 to 59),
splb_slv0_Sl_MIRQ => mb_plb_Sl_MIRQ(54 to 59)
);
nfa_accept_samples_generic_hw_top_4 : system_nfa_accept_samples_generic_hw_top_4_wrapper
port map (
aclk => clk_125_0000MHzPLL0,
aresetn => proc_sys_reset_0_Peripheral_aresetn(0),
indices_MPLB_Clk => net_gnd0,
indices_MPLB_Rst => ac1_plb_MPLB_Rst(5),
indices_M_request => ac1_plb_M_request(5),
indices_M_priority => ac1_plb_M_priority(10 to 11),
indices_M_busLock => ac1_plb_M_busLock(5),
indices_M_RNW => ac1_plb_M_RNW(5),
indices_M_BE => ac1_plb_M_BE(40 to 47),
indices_M_MSize => ac1_plb_M_MSize(10 to 11),
indices_M_size => ac1_plb_M_size(20 to 23),
indices_M_type => ac1_plb_M_type(15 to 17),
indices_M_TAttribute => ac1_plb_M_TAttribute(80 to 95),
indices_M_lockErr => ac1_plb_M_lockErr(5),
indices_M_abort => ac1_plb_M_abort(5),
indices_M_UABus => ac1_plb_M_UABus(160 to 191),
indices_M_ABus => ac1_plb_M_ABus(160 to 191),
indices_M_wrDBus => ac1_plb_M_wrDBus(320 to 383),
indices_M_wrBurst => ac1_plb_M_wrBurst(5),
indices_M_rdBurst => ac1_plb_M_rdBurst(5),
indices_PLB_MAddrAck => ac1_plb_PLB_MAddrAck(5),
indices_PLB_MSSize => ac1_plb_PLB_MSSize(10 to 11),
indices_PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate(5),
indices_PLB_MTimeout => ac1_plb_PLB_MTimeout(5),
indices_PLB_MBusy => ac1_plb_PLB_MBusy(5),
indices_PLB_MRdErr => ac1_plb_PLB_MRdErr(5),
indices_PLB_MWrErr => ac1_plb_PLB_MWrErr(5),
indices_PLB_MIRQ => ac1_plb_PLB_MIRQ(5),
indices_PLB_MRdDBus => ac1_plb_PLB_MRdDBus(320 to 383),
indices_PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr(20 to 23),
indices_PLB_MRdDAck => ac1_plb_PLB_MRdDAck(5),
indices_PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm(5),
indices_PLB_MWrDAck => ac1_plb_PLB_MWrDAck(5),
indices_PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm(5),
nfa_finals_buckets_MPLB_Clk => net_gnd0,
nfa_finals_buckets_MPLB_Rst => ac1_plb_MPLB_Rst(6),
nfa_finals_buckets_M_request => ac1_plb_M_request(6),
nfa_finals_buckets_M_priority => ac1_plb_M_priority(12 to 13),
nfa_finals_buckets_M_busLock => ac1_plb_M_busLock(6),
nfa_finals_buckets_M_RNW => ac1_plb_M_RNW(6),
nfa_finals_buckets_M_BE => ac1_plb_M_BE(48 to 55),
nfa_finals_buckets_M_MSize => ac1_plb_M_MSize(12 to 13),
nfa_finals_buckets_M_size => ac1_plb_M_size(24 to 27),
nfa_finals_buckets_M_type => ac1_plb_M_type(18 to 20),
nfa_finals_buckets_M_TAttribute => ac1_plb_M_TAttribute(96 to 111),
nfa_finals_buckets_M_lockErr => ac1_plb_M_lockErr(6),
nfa_finals_buckets_M_abort => ac1_plb_M_abort(6),
nfa_finals_buckets_M_UABus => ac1_plb_M_UABus(192 to 223),
nfa_finals_buckets_M_ABus => ac1_plb_M_ABus(192 to 223),
nfa_finals_buckets_M_wrDBus => ac1_plb_M_wrDBus(384 to 447),
nfa_finals_buckets_M_wrBurst => ac1_plb_M_wrBurst(6),
nfa_finals_buckets_M_rdBurst => ac1_plb_M_rdBurst(6),
nfa_finals_buckets_PLB_MAddrAck => ac1_plb_PLB_MAddrAck(6),
nfa_finals_buckets_PLB_MSSize => ac1_plb_PLB_MSSize(12 to 13),
nfa_finals_buckets_PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate(6),
nfa_finals_buckets_PLB_MTimeout => ac1_plb_PLB_MTimeout(6),
nfa_finals_buckets_PLB_MBusy => ac1_plb_PLB_MBusy(6),
nfa_finals_buckets_PLB_MRdErr => ac1_plb_PLB_MRdErr(6),
nfa_finals_buckets_PLB_MWrErr => ac1_plb_PLB_MWrErr(6),
nfa_finals_buckets_PLB_MIRQ => ac1_plb_PLB_MIRQ(6),
nfa_finals_buckets_PLB_MRdDBus => ac1_plb_PLB_MRdDBus(384 to 447),
nfa_finals_buckets_PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr(24 to 27),
nfa_finals_buckets_PLB_MRdDAck => ac1_plb_PLB_MRdDAck(6),
nfa_finals_buckets_PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm(6),
nfa_finals_buckets_PLB_MWrDAck => ac1_plb_PLB_MWrDAck(6),
nfa_finals_buckets_PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm(6),
nfa_forward_buckets_MPLB_Clk => net_gnd0,
nfa_forward_buckets_MPLB_Rst => ac1_plb_MPLB_Rst(7),
nfa_forward_buckets_M_request => ac1_plb_M_request(7),
nfa_forward_buckets_M_priority => ac1_plb_M_priority(14 to 15),
nfa_forward_buckets_M_busLock => ac1_plb_M_busLock(7),
nfa_forward_buckets_M_RNW => ac1_plb_M_RNW(7),
nfa_forward_buckets_M_BE => ac1_plb_M_BE(56 to 63),
nfa_forward_buckets_M_MSize => ac1_plb_M_MSize(14 to 15),
nfa_forward_buckets_M_size => ac1_plb_M_size(28 to 31),
nfa_forward_buckets_M_type => ac1_plb_M_type(21 to 23),
nfa_forward_buckets_M_TAttribute => ac1_plb_M_TAttribute(112 to 127),
nfa_forward_buckets_M_lockErr => ac1_plb_M_lockErr(7),
nfa_forward_buckets_M_abort => ac1_plb_M_abort(7),
nfa_forward_buckets_M_UABus => ac1_plb_M_UABus(224 to 255),
nfa_forward_buckets_M_ABus => ac1_plb_M_ABus(224 to 255),
nfa_forward_buckets_M_wrDBus => ac1_plb_M_wrDBus(448 to 511),
nfa_forward_buckets_M_wrBurst => ac1_plb_M_wrBurst(7),
nfa_forward_buckets_M_rdBurst => ac1_plb_M_rdBurst(7),
nfa_forward_buckets_PLB_MAddrAck => ac1_plb_PLB_MAddrAck(7),
nfa_forward_buckets_PLB_MSSize => ac1_plb_PLB_MSSize(14 to 15),
nfa_forward_buckets_PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate(7),
nfa_forward_buckets_PLB_MTimeout => ac1_plb_PLB_MTimeout(7),
nfa_forward_buckets_PLB_MBusy => ac1_plb_PLB_MBusy(7),
nfa_forward_buckets_PLB_MRdErr => ac1_plb_PLB_MRdErr(7),
nfa_forward_buckets_PLB_MWrErr => ac1_plb_PLB_MWrErr(7),
nfa_forward_buckets_PLB_MIRQ => ac1_plb_PLB_MIRQ(7),
nfa_forward_buckets_PLB_MRdDBus => ac1_plb_PLB_MRdDBus(448 to 511),
nfa_forward_buckets_PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr(28 to 31),
nfa_forward_buckets_PLB_MRdDAck => ac1_plb_PLB_MRdDAck(7),
nfa_forward_buckets_PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm(7),
nfa_forward_buckets_PLB_MWrDAck => ac1_plb_PLB_MWrDAck(7),
nfa_forward_buckets_PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm(7),
nfa_initials_buckets_MPLB_Clk => net_gnd0,
nfa_initials_buckets_MPLB_Rst => ac1_plb_MPLB_Rst(8),
nfa_initials_buckets_M_request => ac1_plb_M_request(8),
nfa_initials_buckets_M_priority => ac1_plb_M_priority(16 to 17),
nfa_initials_buckets_M_busLock => ac1_plb_M_busLock(8),
nfa_initials_buckets_M_RNW => ac1_plb_M_RNW(8),
nfa_initials_buckets_M_BE => ac1_plb_M_BE(64 to 71),
nfa_initials_buckets_M_MSize => ac1_plb_M_MSize(16 to 17),
nfa_initials_buckets_M_size => ac1_plb_M_size(32 to 35),
nfa_initials_buckets_M_type => ac1_plb_M_type(24 to 26),
nfa_initials_buckets_M_TAttribute => ac1_plb_M_TAttribute(128 to 143),
nfa_initials_buckets_M_lockErr => ac1_plb_M_lockErr(8),
nfa_initials_buckets_M_abort => ac1_plb_M_abort(8),
nfa_initials_buckets_M_UABus => ac1_plb_M_UABus(256 to 287),
nfa_initials_buckets_M_ABus => ac1_plb_M_ABus(256 to 287),
nfa_initials_buckets_M_wrDBus => ac1_plb_M_wrDBus(512 to 575),
nfa_initials_buckets_M_wrBurst => ac1_plb_M_wrBurst(8),
nfa_initials_buckets_M_rdBurst => ac1_plb_M_rdBurst(8),
nfa_initials_buckets_PLB_MAddrAck => ac1_plb_PLB_MAddrAck(8),
nfa_initials_buckets_PLB_MSSize => ac1_plb_PLB_MSSize(16 to 17),
nfa_initials_buckets_PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate(8),
nfa_initials_buckets_PLB_MTimeout => ac1_plb_PLB_MTimeout(8),
nfa_initials_buckets_PLB_MBusy => ac1_plb_PLB_MBusy(8),
nfa_initials_buckets_PLB_MRdErr => ac1_plb_PLB_MRdErr(8),
nfa_initials_buckets_PLB_MWrErr => ac1_plb_PLB_MWrErr(8),
nfa_initials_buckets_PLB_MIRQ => ac1_plb_PLB_MIRQ(8),
nfa_initials_buckets_PLB_MRdDBus => ac1_plb_PLB_MRdDBus(512 to 575),
nfa_initials_buckets_PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr(32 to 35),
nfa_initials_buckets_PLB_MRdDAck => ac1_plb_PLB_MRdDAck(8),
nfa_initials_buckets_PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm(8),
nfa_initials_buckets_PLB_MWrDAck => ac1_plb_PLB_MWrDAck(8),
nfa_initials_buckets_PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm(8),
sample_buffer_MPLB_Clk => net_gnd0,
sample_buffer_MPLB_Rst => ac1_plb_MPLB_Rst(9),
sample_buffer_M_request => ac1_plb_M_request(9),
sample_buffer_M_priority => ac1_plb_M_priority(18 to 19),
sample_buffer_M_busLock => ac1_plb_M_busLock(9),
sample_buffer_M_RNW => ac1_plb_M_RNW(9),
sample_buffer_M_BE => ac1_plb_M_BE(72 to 79),
sample_buffer_M_MSize => ac1_plb_M_MSize(18 to 19),
sample_buffer_M_size => ac1_plb_M_size(36 to 39),
sample_buffer_M_type => ac1_plb_M_type(27 to 29),
sample_buffer_M_TAttribute => ac1_plb_M_TAttribute(144 to 159),
sample_buffer_M_lockErr => ac1_plb_M_lockErr(9),
sample_buffer_M_abort => ac1_plb_M_abort(9),
sample_buffer_M_UABus => ac1_plb_M_UABus(288 to 319),
sample_buffer_M_ABus => ac1_plb_M_ABus(288 to 319),
sample_buffer_M_wrDBus => ac1_plb_M_wrDBus(576 to 639),
sample_buffer_M_wrBurst => ac1_plb_M_wrBurst(9),
sample_buffer_M_rdBurst => ac1_plb_M_rdBurst(9),
sample_buffer_PLB_MAddrAck => ac1_plb_PLB_MAddrAck(9),
sample_buffer_PLB_MSSize => ac1_plb_PLB_MSSize(18 to 19),
sample_buffer_PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate(9),
sample_buffer_PLB_MTimeout => ac1_plb_PLB_MTimeout(9),
sample_buffer_PLB_MBusy => ac1_plb_PLB_MBusy(9),
sample_buffer_PLB_MRdErr => ac1_plb_PLB_MRdErr(9),
sample_buffer_PLB_MWrErr => ac1_plb_PLB_MWrErr(9),
sample_buffer_PLB_MIRQ => ac1_plb_PLB_MIRQ(9),
sample_buffer_PLB_MRdDBus => ac1_plb_PLB_MRdDBus(576 to 639),
sample_buffer_PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr(36 to 39),
sample_buffer_PLB_MRdDAck => ac1_plb_PLB_MRdDAck(9),
sample_buffer_PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm(9),
sample_buffer_PLB_MWrDAck => ac1_plb_PLB_MWrDAck(9),
sample_buffer_PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm(9),
splb_slv0_SPLB_Clk => clk_125_0000MHzPLL0,
splb_slv0_SPLB_Rst => mb_plb_SPLB_Rst(10),
splb_slv0_PLB_ABus => mb_plb_PLB_ABus,
splb_slv0_PLB_UABus => mb_plb_PLB_UABus,
splb_slv0_PLB_PAValid => mb_plb_PLB_PAValid,
splb_slv0_PLB_SAValid => mb_plb_PLB_SAValid,
splb_slv0_PLB_rdPrim => mb_plb_PLB_rdPrim(10),
splb_slv0_PLB_wrPrim => mb_plb_PLB_wrPrim(10),
splb_slv0_PLB_masterID => mb_plb_PLB_masterID,
splb_slv0_PLB_abort => mb_plb_PLB_abort,
splb_slv0_PLB_busLock => mb_plb_PLB_busLock,
splb_slv0_PLB_RNW => mb_plb_PLB_RNW,
splb_slv0_PLB_BE => mb_plb_PLB_BE,
splb_slv0_PLB_MSize => mb_plb_PLB_MSize,
splb_slv0_PLB_size => mb_plb_PLB_size,
splb_slv0_PLB_type => mb_plb_PLB_type,
splb_slv0_PLB_lockErr => mb_plb_PLB_lockErr,
splb_slv0_PLB_wrDBus => mb_plb_PLB_wrDBus,
splb_slv0_PLB_wrBurst => mb_plb_PLB_wrBurst,
splb_slv0_PLB_rdBurst => mb_plb_PLB_rdBurst,
splb_slv0_PLB_wrPendReq => mb_plb_PLB_wrPendReq,
splb_slv0_PLB_rdPendReq => mb_plb_PLB_rdPendReq,
splb_slv0_PLB_wrPendPri => mb_plb_PLB_wrPendPri,
splb_slv0_PLB_rdPendPri => mb_plb_PLB_rdPendPri,
splb_slv0_PLB_reqPri => mb_plb_PLB_reqPri,
splb_slv0_PLB_TAttribute => mb_plb_PLB_TAttribute,
splb_slv0_Sl_addrAck => mb_plb_Sl_addrAck(10),
splb_slv0_Sl_SSize => mb_plb_Sl_SSize(20 to 21),
splb_slv0_Sl_wait => mb_plb_Sl_wait(10),
splb_slv0_Sl_rearbitrate => mb_plb_Sl_rearbitrate(10),
splb_slv0_Sl_wrDAck => mb_plb_Sl_wrDAck(10),
splb_slv0_Sl_wrComp => mb_plb_Sl_wrComp(10),
splb_slv0_Sl_wrBTerm => mb_plb_Sl_wrBTerm(10),
splb_slv0_Sl_rdDBus => mb_plb_Sl_rdDBus(640 to 703),
splb_slv0_Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(40 to 43),
splb_slv0_Sl_rdDAck => mb_plb_Sl_rdDAck(10),
splb_slv0_Sl_rdComp => mb_plb_Sl_rdComp(10),
splb_slv0_Sl_rdBTerm => mb_plb_Sl_rdBTerm(10),
splb_slv0_Sl_MBusy => mb_plb_Sl_MBusy(60 to 65),
splb_slv0_Sl_MWrErr => mb_plb_Sl_MWrErr(60 to 65),
splb_slv0_Sl_MRdErr => mb_plb_Sl_MRdErr(60 to 65),
splb_slv0_Sl_MIRQ => mb_plb_Sl_MIRQ(60 to 65)
);
ac0_plb : system_ac0_plb_wrapper
port map (
PLB_Clk => net_gnd0,
SYS_Rst => net_gnd0,
PLB_Rst => open,
SPLB_Rst => ac0_plb_SPLB_Rst(0 to 0),
MPLB_Rst => ac0_plb_MPLB_Rst,
PLB_dcrAck => open,
PLB_dcrDBus => open,
DCR_ABus => net_gnd10,
DCR_DBus => net_gnd32,
DCR_Read => net_gnd0,
DCR_Write => net_gnd0,
M_ABus => ac0_plb_M_ABus,
M_UABus => ac0_plb_M_UABus,
M_BE => ac0_plb_M_BE,
M_RNW => ac0_plb_M_RNW,
M_abort => ac0_plb_M_abort,
M_busLock => ac0_plb_M_busLock,
M_TAttribute => ac0_plb_M_TAttribute,
M_lockErr => ac0_plb_M_lockErr,
M_MSize => ac0_plb_M_MSize,
M_priority => ac0_plb_M_priority,
M_rdBurst => ac0_plb_M_rdBurst,
M_request => ac0_plb_M_request,
M_size => ac0_plb_M_size,
M_type => ac0_plb_M_type,
M_wrBurst => ac0_plb_M_wrBurst,
M_wrDBus => ac0_plb_M_wrDBus,
Sl_addrAck => ac0_plb_Sl_addrAck(0 to 0),
Sl_MRdErr => ac0_plb_Sl_MRdErr,
Sl_MWrErr => ac0_plb_Sl_MWrErr,
Sl_MBusy => ac0_plb_Sl_MBusy,
Sl_rdBTerm => ac0_plb_Sl_rdBTerm(0 to 0),
Sl_rdComp => ac0_plb_Sl_rdComp(0 to 0),
Sl_rdDAck => ac0_plb_Sl_rdDAck(0 to 0),
Sl_rdDBus => ac0_plb_Sl_rdDBus,
Sl_rdWdAddr => ac0_plb_Sl_rdWdAddr,
Sl_rearbitrate => ac0_plb_Sl_rearbitrate(0 to 0),
Sl_SSize => ac0_plb_Sl_SSize,
Sl_wait => ac0_plb_Sl_wait(0 to 0),
Sl_wrBTerm => ac0_plb_Sl_wrBTerm(0 to 0),
Sl_wrComp => ac0_plb_Sl_wrComp(0 to 0),
Sl_wrDAck => ac0_plb_Sl_wrDAck(0 to 0),
Sl_MIRQ => ac0_plb_Sl_MIRQ,
PLB_MIRQ => ac0_plb_PLB_MIRQ,
PLB_ABus => ac0_plb_PLB_ABus,
PLB_UABus => ac0_plb_PLB_UABus,
PLB_BE => ac0_plb_PLB_BE,
PLB_MAddrAck => ac0_plb_PLB_MAddrAck,
PLB_MTimeout => ac0_plb_PLB_MTimeout,
PLB_MBusy => ac0_plb_PLB_MBusy,
PLB_MRdErr => ac0_plb_PLB_MRdErr,
PLB_MWrErr => ac0_plb_PLB_MWrErr,
PLB_MRdBTerm => ac0_plb_PLB_MRdBTerm,
PLB_MRdDAck => ac0_plb_PLB_MRdDAck,
PLB_MRdDBus => ac0_plb_PLB_MRdDBus,
PLB_MRdWdAddr => ac0_plb_PLB_MRdWdAddr,
PLB_MRearbitrate => ac0_plb_PLB_MRearbitrate,
PLB_MWrBTerm => ac0_plb_PLB_MWrBTerm,
PLB_MWrDAck => ac0_plb_PLB_MWrDAck,
PLB_MSSize => ac0_plb_PLB_MSSize,
PLB_PAValid => ac0_plb_PLB_PAValid,
PLB_RNW => ac0_plb_PLB_RNW,
PLB_SAValid => ac0_plb_PLB_SAValid,
PLB_abort => ac0_plb_PLB_abort,
PLB_busLock => ac0_plb_PLB_busLock,
PLB_TAttribute => ac0_plb_PLB_TAttribute,
PLB_lockErr => ac0_plb_PLB_lockErr,
PLB_masterID => ac0_plb_PLB_masterID,
PLB_MSize => ac0_plb_PLB_MSize,
PLB_rdPendPri => ac0_plb_PLB_rdPendPri,
PLB_wrPendPri => ac0_plb_PLB_wrPendPri,
PLB_rdPendReq => ac0_plb_PLB_rdPendReq,
PLB_wrPendReq => ac0_plb_PLB_wrPendReq,
PLB_rdBurst => ac0_plb_PLB_rdBurst,
PLB_rdPrim => ac0_plb_PLB_rdPrim(0 to 0),
PLB_reqPri => ac0_plb_PLB_reqPri,
PLB_size => ac0_plb_PLB_size,
PLB_type => ac0_plb_PLB_type,
PLB_wrBurst => ac0_plb_PLB_wrBurst,
PLB_wrDBus => ac0_plb_PLB_wrDBus,
PLB_wrPrim => ac0_plb_PLB_wrPrim(0 to 0),
PLB_SaddrAck => open,
PLB_SMRdErr => open,
PLB_SMWrErr => open,
PLB_SMBusy => open,
PLB_SrdBTerm => open,
PLB_SrdComp => open,
PLB_SrdDAck => open,
PLB_SrdDBus => open,
PLB_SrdWdAddr => open,
PLB_Srearbitrate => open,
PLB_Sssize => open,
PLB_Swait => open,
PLB_SwrBTerm => open,
PLB_SwrComp => open,
PLB_SwrDAck => open,
Bus_Error_Det => open
);
ac0_mb_bridge : system_ac0_mb_bridge_wrapper
port map (
SPLB_Clk => net_gnd0,
SPLB_Rst => ac0_plb_SPLB_Rst(0),
IP2INTC_Irpt => open,
PLB_ABus => ac0_plb_PLB_ABus,
PLB_UABus => ac0_plb_PLB_UABus,
PLB_PAValid => ac0_plb_PLB_PAValid,
PLB_SAValid => ac0_plb_PLB_SAValid,
PLB_rdPrim => ac0_plb_PLB_rdPrim(0),
PLB_wrPrim => ac0_plb_PLB_wrPrim(0),
PLB_masterID => ac0_plb_PLB_masterID,
PLB_abort => ac0_plb_PLB_abort,
PLB_busLock => ac0_plb_PLB_busLock,
PLB_RNW => ac0_plb_PLB_RNW,
PLB_BE => ac0_plb_PLB_BE,
PLB_MSize => ac0_plb_PLB_MSize,
PLB_size => ac0_plb_PLB_size,
PLB_type => ac0_plb_PLB_type,
PLB_lockErr => ac0_plb_PLB_lockErr,
PLB_wrDBus => ac0_plb_PLB_wrDBus,
PLB_wrBurst => ac0_plb_PLB_wrBurst,
PLB_rdBurst => ac0_plb_PLB_rdBurst,
PLB_wrPendReq => ac0_plb_PLB_wrPendReq,
PLB_rdPendReq => ac0_plb_PLB_rdPendReq,
PLB_wrPendPri => ac0_plb_PLB_wrPendPri,
PLB_rdPendPri => ac0_plb_PLB_rdPendPri,
PLB_reqPri => ac0_plb_PLB_reqPri,
PLB_TAttribute => ac0_plb_PLB_TAttribute,
Sl_addrAck => ac0_plb_Sl_addrAck(0),
Sl_SSize => ac0_plb_Sl_SSize,
Sl_wait => ac0_plb_Sl_wait(0),
Sl_rearbitrate => ac0_plb_Sl_rearbitrate(0),
Sl_wrDAck => ac0_plb_Sl_wrDAck(0),
Sl_wrComp => ac0_plb_Sl_wrComp(0),
Sl_wrBTerm => ac0_plb_Sl_wrBTerm(0),
Sl_rdDBus => ac0_plb_Sl_rdDBus,
Sl_rdWdAddr => ac0_plb_Sl_rdWdAddr,
Sl_rdDAck => ac0_plb_Sl_rdDAck(0),
Sl_rdComp => ac0_plb_Sl_rdComp(0),
Sl_rdBTerm => ac0_plb_Sl_rdBTerm(0),
Sl_MBusy => ac0_plb_Sl_MBusy,
Sl_MWrErr => ac0_plb_Sl_MWrErr,
Sl_MRdErr => ac0_plb_Sl_MRdErr,
Sl_MIRQ => ac0_plb_Sl_MIRQ,
MPLB_Clk => clk_125_0000MHzPLL0,
MPLB_Rst => mb_plb_MPLB_Rst(4),
M_request => mb_plb_M_request(4),
M_priority => mb_plb_M_priority(8 to 9),
M_busLock => mb_plb_M_busLock(4),
M_RNW => mb_plb_M_RNW(4),
M_BE => mb_plb_M_BE(32 to 39),
M_MSize => mb_plb_M_MSize(8 to 9),
M_size => mb_plb_M_size(16 to 19),
M_type => mb_plb_M_type(12 to 14),
M_ABus => mb_plb_M_ABus(128 to 159),
M_wrBurst => mb_plb_M_wrBurst(4),
M_rdBurst => mb_plb_M_rdBurst(4),
M_wrDBus => mb_plb_M_wrDBus(256 to 319),
PLB_MAddrAck => mb_plb_PLB_MAddrAck(4),
PLB_MSSize => mb_plb_PLB_MSSize(8 to 9),
PLB_MRearbitrate => mb_plb_PLB_MRearbitrate(4),
PLB_MTimeout => mb_plb_PLB_MTimeout(4),
PLB_MRdErr => mb_plb_PLB_MRdErr(4),
PLB_MWrErr => mb_plb_PLB_MWrErr(4),
PLB_MRdDBus => mb_plb_PLB_MRdDBus(256 to 319),
PLB_MRdDAck => mb_plb_PLB_MRdDAck(4),
PLB_MRdBTerm => mb_plb_PLB_MRdBTerm(4),
PLB_MWrDAck => mb_plb_PLB_MWrDAck(4),
PLB_MWrBTerm => mb_plb_PLB_MWrBTerm(4),
M_TAttribute => mb_plb_M_TAttribute(64 to 79),
M_lockErr => mb_plb_M_lockErr(4),
M_abort => mb_plb_M_ABort(4),
M_UABus => mb_plb_M_UABus(128 to 159),
PLB_MBusy => mb_plb_PLB_MBusy(4),
PLB_MIRQ => mb_plb_PLB_MIRQ(4),
PLB_MRdWdAddr => mb_plb_PLB_MRdWdAddr(16 to 19)
);
ac1_plb : system_ac1_plb_wrapper
port map (
PLB_Clk => net_gnd0,
SYS_Rst => net_gnd0,
PLB_Rst => open,
SPLB_Rst => ac1_plb_SPLB_Rst(0 to 0),
MPLB_Rst => ac1_plb_MPLB_Rst,
PLB_dcrAck => open,
PLB_dcrDBus => open,
DCR_ABus => net_gnd10,
DCR_DBus => net_gnd32,
DCR_Read => net_gnd0,
DCR_Write => net_gnd0,
M_ABus => ac1_plb_M_ABus,
M_UABus => ac1_plb_M_UABus,
M_BE => ac1_plb_M_BE,
M_RNW => ac1_plb_M_RNW,
M_abort => ac1_plb_M_abort,
M_busLock => ac1_plb_M_busLock,
M_TAttribute => ac1_plb_M_TAttribute,
M_lockErr => ac1_plb_M_lockErr,
M_MSize => ac1_plb_M_MSize,
M_priority => ac1_plb_M_priority,
M_rdBurst => ac1_plb_M_rdBurst,
M_request => ac1_plb_M_request,
M_size => ac1_plb_M_size,
M_type => ac1_plb_M_type,
M_wrBurst => ac1_plb_M_wrBurst,
M_wrDBus => ac1_plb_M_wrDBus,
Sl_addrAck => ac1_plb_Sl_addrAck(0 to 0),
Sl_MRdErr => ac1_plb_Sl_MRdErr,
Sl_MWrErr => ac1_plb_Sl_MWrErr,
Sl_MBusy => ac1_plb_Sl_MBusy,
Sl_rdBTerm => ac1_plb_Sl_rdBTerm(0 to 0),
Sl_rdComp => ac1_plb_Sl_rdComp(0 to 0),
Sl_rdDAck => ac1_plb_Sl_rdDAck(0 to 0),
Sl_rdDBus => ac1_plb_Sl_rdDBus,
Sl_rdWdAddr => ac1_plb_Sl_rdWdAddr,
Sl_rearbitrate => ac1_plb_Sl_rearbitrate(0 to 0),
Sl_SSize => ac1_plb_Sl_SSize,
Sl_wait => ac1_plb_Sl_wait(0 to 0),
Sl_wrBTerm => ac1_plb_Sl_wrBTerm(0 to 0),
Sl_wrComp => ac1_plb_Sl_wrComp(0 to 0),
Sl_wrDAck => ac1_plb_Sl_wrDAck(0 to 0),
Sl_MIRQ => ac1_plb_Sl_MIRQ,
PLB_MIRQ => ac1_plb_PLB_MIRQ,
PLB_ABus => ac1_plb_PLB_ABus,
PLB_UABus => ac1_plb_PLB_UABus,
PLB_BE => ac1_plb_PLB_BE,
PLB_MAddrAck => ac1_plb_PLB_MAddrAck,
PLB_MTimeout => ac1_plb_PLB_MTimeout,
PLB_MBusy => ac1_plb_PLB_MBusy,
PLB_MRdErr => ac1_plb_PLB_MRdErr,
PLB_MWrErr => ac1_plb_PLB_MWrErr,
PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm,
PLB_MRdDAck => ac1_plb_PLB_MRdDAck,
PLB_MRdDBus => ac1_plb_PLB_MRdDBus,
PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr,
PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate,
PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm,
PLB_MWrDAck => ac1_plb_PLB_MWrDAck,
PLB_MSSize => ac1_plb_PLB_MSSize,
PLB_PAValid => ac1_plb_PLB_PAValid,
PLB_RNW => ac1_plb_PLB_RNW,
PLB_SAValid => ac1_plb_PLB_SAValid,
PLB_abort => ac1_plb_PLB_abort,
PLB_busLock => ac1_plb_PLB_busLock,
PLB_TAttribute => ac1_plb_PLB_TAttribute,
PLB_lockErr => ac1_plb_PLB_lockErr,
PLB_masterID => ac1_plb_PLB_masterID,
PLB_MSize => ac1_plb_PLB_MSize,
PLB_rdPendPri => ac1_plb_PLB_rdPendPri,
PLB_wrPendPri => ac1_plb_PLB_wrPendPri,
PLB_rdPendReq => ac1_plb_PLB_rdPendReq,
PLB_wrPendReq => ac1_plb_PLB_wrPendReq,
PLB_rdBurst => ac1_plb_PLB_rdBurst,
PLB_rdPrim => ac1_plb_PLB_rdPrim(0 to 0),
PLB_reqPri => ac1_plb_PLB_reqPri,
PLB_size => ac1_plb_PLB_size,
PLB_type => ac1_plb_PLB_type,
PLB_wrBurst => ac1_plb_PLB_wrBurst,
PLB_wrDBus => ac1_plb_PLB_wrDBus,
PLB_wrPrim => ac1_plb_PLB_wrPrim(0 to 0),
PLB_SaddrAck => open,
PLB_SMRdErr => open,
PLB_SMWrErr => open,
PLB_SMBusy => open,
PLB_SrdBTerm => open,
PLB_SrdComp => open,
PLB_SrdDAck => open,
PLB_SrdDBus => open,
PLB_SrdWdAddr => open,
PLB_Srearbitrate => open,
PLB_Sssize => open,
PLB_Swait => open,
PLB_SwrBTerm => open,
PLB_SwrComp => open,
PLB_SwrDAck => open,
Bus_Error_Det => open
);
ac1_mb_bridge : system_ac1_mb_bridge_wrapper
port map (
SPLB_Clk => net_gnd0,
SPLB_Rst => ac1_plb_SPLB_Rst(0),
IP2INTC_Irpt => open,
PLB_ABus => ac1_plb_PLB_ABus,
PLB_UABus => ac1_plb_PLB_UABus,
PLB_PAValid => ac1_plb_PLB_PAValid,
PLB_SAValid => ac1_plb_PLB_SAValid,
PLB_rdPrim => ac1_plb_PLB_rdPrim(0),
PLB_wrPrim => ac1_plb_PLB_wrPrim(0),
PLB_masterID => ac1_plb_PLB_masterID,
PLB_abort => ac1_plb_PLB_abort,
PLB_busLock => ac1_plb_PLB_busLock,
PLB_RNW => ac1_plb_PLB_RNW,
PLB_BE => ac1_plb_PLB_BE,
PLB_MSize => ac1_plb_PLB_MSize,
PLB_size => ac1_plb_PLB_size,
PLB_type => ac1_plb_PLB_type,
PLB_lockErr => ac1_plb_PLB_lockErr,
PLB_wrDBus => ac1_plb_PLB_wrDBus,
PLB_wrBurst => ac1_plb_PLB_wrBurst,
PLB_rdBurst => ac1_plb_PLB_rdBurst,
PLB_wrPendReq => ac1_plb_PLB_wrPendReq,
PLB_rdPendReq => ac1_plb_PLB_rdPendReq,
PLB_wrPendPri => ac1_plb_PLB_wrPendPri,
PLB_rdPendPri => ac1_plb_PLB_rdPendPri,
PLB_reqPri => ac1_plb_PLB_reqPri,
PLB_TAttribute => ac1_plb_PLB_TAttribute,
Sl_addrAck => ac1_plb_Sl_addrAck(0),
Sl_SSize => ac1_plb_Sl_SSize,
Sl_wait => ac1_plb_Sl_wait(0),
Sl_rearbitrate => ac1_plb_Sl_rearbitrate(0),
Sl_wrDAck => ac1_plb_Sl_wrDAck(0),
Sl_wrComp => ac1_plb_Sl_wrComp(0),
Sl_wrBTerm => ac1_plb_Sl_wrBTerm(0),
Sl_rdDBus => ac1_plb_Sl_rdDBus,
Sl_rdWdAddr => ac1_plb_Sl_rdWdAddr,
Sl_rdDAck => ac1_plb_Sl_rdDAck(0),
Sl_rdComp => ac1_plb_Sl_rdComp(0),
Sl_rdBTerm => ac1_plb_Sl_rdBTerm(0),
Sl_MBusy => ac1_plb_Sl_MBusy,
Sl_MWrErr => ac1_plb_Sl_MWrErr,
Sl_MRdErr => ac1_plb_Sl_MRdErr,
Sl_MIRQ => ac1_plb_Sl_MIRQ,
MPLB_Clk => clk_125_0000MHzPLL0,
MPLB_Rst => mb_plb_MPLB_Rst(5),
M_request => mb_plb_M_request(5),
M_priority => mb_plb_M_priority(10 to 11),
M_busLock => mb_plb_M_busLock(5),
M_RNW => mb_plb_M_RNW(5),
M_BE => mb_plb_M_BE(40 to 47),
M_MSize => mb_plb_M_MSize(10 to 11),
M_size => mb_plb_M_size(20 to 23),
M_type => mb_plb_M_type(15 to 17),
M_ABus => mb_plb_M_ABus(160 to 191),
M_wrBurst => mb_plb_M_wrBurst(5),
M_rdBurst => mb_plb_M_rdBurst(5),
M_wrDBus => mb_plb_M_wrDBus(320 to 383),
PLB_MAddrAck => mb_plb_PLB_MAddrAck(5),
PLB_MSSize => mb_plb_PLB_MSSize(10 to 11),
PLB_MRearbitrate => mb_plb_PLB_MRearbitrate(5),
PLB_MTimeout => mb_plb_PLB_MTimeout(5),
PLB_MRdErr => mb_plb_PLB_MRdErr(5),
PLB_MWrErr => mb_plb_PLB_MWrErr(5),
PLB_MRdDBus => mb_plb_PLB_MRdDBus(320 to 383),
PLB_MRdDAck => mb_plb_PLB_MRdDAck(5),
PLB_MRdBTerm => mb_plb_PLB_MRdBTerm(5),
PLB_MWrDAck => mb_plb_PLB_MWrDAck(5),
PLB_MWrBTerm => mb_plb_PLB_MWrBTerm(5),
M_TAttribute => mb_plb_M_TAttribute(80 to 95),
M_lockErr => mb_plb_M_lockErr(5),
M_abort => mb_plb_M_ABort(5),
M_UABus => mb_plb_M_UABus(160 to 191),
PLB_MBusy => mb_plb_PLB_MBusy(5),
PLB_MIRQ => mb_plb_PLB_MIRQ(5),
PLB_MRdWdAddr => mb_plb_PLB_MRdWdAddr(20 to 23)
);
nfa_accept_samples_generic_hw_top_5 : system_nfa_accept_samples_generic_hw_top_5_wrapper
port map (
aclk => clk_125_0000MHzPLL0,
aresetn => proc_sys_reset_0_Peripheral_aresetn(0),
indices_MPLB_Clk => net_gnd0,
indices_MPLB_Rst => ac1_plb_MPLB_Rst(10),
indices_M_request => ac1_plb_M_request(10),
indices_M_priority => ac1_plb_M_priority(20 to 21),
indices_M_busLock => ac1_plb_M_busLock(10),
indices_M_RNW => ac1_plb_M_RNW(10),
indices_M_BE => ac1_plb_M_BE(80 to 87),
indices_M_MSize => ac1_plb_M_MSize(20 to 21),
indices_M_size => ac1_plb_M_size(40 to 43),
indices_M_type => ac1_plb_M_type(30 to 32),
indices_M_TAttribute => ac1_plb_M_TAttribute(160 to 175),
indices_M_lockErr => ac1_plb_M_lockErr(10),
indices_M_abort => ac1_plb_M_abort(10),
indices_M_UABus => ac1_plb_M_UABus(320 to 351),
indices_M_ABus => ac1_plb_M_ABus(320 to 351),
indices_M_wrDBus => ac1_plb_M_wrDBus(640 to 703),
indices_M_wrBurst => ac1_plb_M_wrBurst(10),
indices_M_rdBurst => ac1_plb_M_rdBurst(10),
indices_PLB_MAddrAck => ac1_plb_PLB_MAddrAck(10),
indices_PLB_MSSize => ac1_plb_PLB_MSSize(20 to 21),
indices_PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate(10),
indices_PLB_MTimeout => ac1_plb_PLB_MTimeout(10),
indices_PLB_MBusy => ac1_plb_PLB_MBusy(10),
indices_PLB_MRdErr => ac1_plb_PLB_MRdErr(10),
indices_PLB_MWrErr => ac1_plb_PLB_MWrErr(10),
indices_PLB_MIRQ => ac1_plb_PLB_MIRQ(10),
indices_PLB_MRdDBus => ac1_plb_PLB_MRdDBus(640 to 703),
indices_PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr(40 to 43),
indices_PLB_MRdDAck => ac1_plb_PLB_MRdDAck(10),
indices_PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm(10),
indices_PLB_MWrDAck => ac1_plb_PLB_MWrDAck(10),
indices_PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm(10),
nfa_finals_buckets_MPLB_Clk => net_gnd0,
nfa_finals_buckets_MPLB_Rst => ac1_plb_MPLB_Rst(11),
nfa_finals_buckets_M_request => ac1_plb_M_request(11),
nfa_finals_buckets_M_priority => ac1_plb_M_priority(22 to 23),
nfa_finals_buckets_M_busLock => ac1_plb_M_busLock(11),
nfa_finals_buckets_M_RNW => ac1_plb_M_RNW(11),
nfa_finals_buckets_M_BE => ac1_plb_M_BE(88 to 95),
nfa_finals_buckets_M_MSize => ac1_plb_M_MSize(22 to 23),
nfa_finals_buckets_M_size => ac1_plb_M_size(44 to 47),
nfa_finals_buckets_M_type => ac1_plb_M_type(33 to 35),
nfa_finals_buckets_M_TAttribute => ac1_plb_M_TAttribute(176 to 191),
nfa_finals_buckets_M_lockErr => ac1_plb_M_lockErr(11),
nfa_finals_buckets_M_abort => ac1_plb_M_abort(11),
nfa_finals_buckets_M_UABus => ac1_plb_M_UABus(352 to 383),
nfa_finals_buckets_M_ABus => ac1_plb_M_ABus(352 to 383),
nfa_finals_buckets_M_wrDBus => ac1_plb_M_wrDBus(704 to 767),
nfa_finals_buckets_M_wrBurst => ac1_plb_M_wrBurst(11),
nfa_finals_buckets_M_rdBurst => ac1_plb_M_rdBurst(11),
nfa_finals_buckets_PLB_MAddrAck => ac1_plb_PLB_MAddrAck(11),
nfa_finals_buckets_PLB_MSSize => ac1_plb_PLB_MSSize(22 to 23),
nfa_finals_buckets_PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate(11),
nfa_finals_buckets_PLB_MTimeout => ac1_plb_PLB_MTimeout(11),
nfa_finals_buckets_PLB_MBusy => ac1_plb_PLB_MBusy(11),
nfa_finals_buckets_PLB_MRdErr => ac1_plb_PLB_MRdErr(11),
nfa_finals_buckets_PLB_MWrErr => ac1_plb_PLB_MWrErr(11),
nfa_finals_buckets_PLB_MIRQ => ac1_plb_PLB_MIRQ(11),
nfa_finals_buckets_PLB_MRdDBus => ac1_plb_PLB_MRdDBus(704 to 767),
nfa_finals_buckets_PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr(44 to 47),
nfa_finals_buckets_PLB_MRdDAck => ac1_plb_PLB_MRdDAck(11),
nfa_finals_buckets_PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm(11),
nfa_finals_buckets_PLB_MWrDAck => ac1_plb_PLB_MWrDAck(11),
nfa_finals_buckets_PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm(11),
nfa_forward_buckets_MPLB_Clk => net_gnd0,
nfa_forward_buckets_MPLB_Rst => ac1_plb_MPLB_Rst(12),
nfa_forward_buckets_M_request => ac1_plb_M_request(12),
nfa_forward_buckets_M_priority => ac1_plb_M_priority(24 to 25),
nfa_forward_buckets_M_busLock => ac1_plb_M_busLock(12),
nfa_forward_buckets_M_RNW => ac1_plb_M_RNW(12),
nfa_forward_buckets_M_BE => ac1_plb_M_BE(96 to 103),
nfa_forward_buckets_M_MSize => ac1_plb_M_MSize(24 to 25),
nfa_forward_buckets_M_size => ac1_plb_M_size(48 to 51),
nfa_forward_buckets_M_type => ac1_plb_M_type(36 to 38),
nfa_forward_buckets_M_TAttribute => ac1_plb_M_TAttribute(192 to 207),
nfa_forward_buckets_M_lockErr => ac1_plb_M_lockErr(12),
nfa_forward_buckets_M_abort => ac1_plb_M_abort(12),
nfa_forward_buckets_M_UABus => ac1_plb_M_UABus(384 to 415),
nfa_forward_buckets_M_ABus => ac1_plb_M_ABus(384 to 415),
nfa_forward_buckets_M_wrDBus => ac1_plb_M_wrDBus(768 to 831),
nfa_forward_buckets_M_wrBurst => ac1_plb_M_wrBurst(12),
nfa_forward_buckets_M_rdBurst => ac1_plb_M_rdBurst(12),
nfa_forward_buckets_PLB_MAddrAck => ac1_plb_PLB_MAddrAck(12),
nfa_forward_buckets_PLB_MSSize => ac1_plb_PLB_MSSize(24 to 25),
nfa_forward_buckets_PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate(12),
nfa_forward_buckets_PLB_MTimeout => ac1_plb_PLB_MTimeout(12),
nfa_forward_buckets_PLB_MBusy => ac1_plb_PLB_MBusy(12),
nfa_forward_buckets_PLB_MRdErr => ac1_plb_PLB_MRdErr(12),
nfa_forward_buckets_PLB_MWrErr => ac1_plb_PLB_MWrErr(12),
nfa_forward_buckets_PLB_MIRQ => ac1_plb_PLB_MIRQ(12),
nfa_forward_buckets_PLB_MRdDBus => ac1_plb_PLB_MRdDBus(768 to 831),
nfa_forward_buckets_PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr(48 to 51),
nfa_forward_buckets_PLB_MRdDAck => ac1_plb_PLB_MRdDAck(12),
nfa_forward_buckets_PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm(12),
nfa_forward_buckets_PLB_MWrDAck => ac1_plb_PLB_MWrDAck(12),
nfa_forward_buckets_PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm(12),
nfa_initials_buckets_MPLB_Clk => net_gnd0,
nfa_initials_buckets_MPLB_Rst => ac1_plb_MPLB_Rst(13),
nfa_initials_buckets_M_request => ac1_plb_M_request(13),
nfa_initials_buckets_M_priority => ac1_plb_M_priority(26 to 27),
nfa_initials_buckets_M_busLock => ac1_plb_M_busLock(13),
nfa_initials_buckets_M_RNW => ac1_plb_M_RNW(13),
nfa_initials_buckets_M_BE => ac1_plb_M_BE(104 to 111),
nfa_initials_buckets_M_MSize => ac1_plb_M_MSize(26 to 27),
nfa_initials_buckets_M_size => ac1_plb_M_size(52 to 55),
nfa_initials_buckets_M_type => ac1_plb_M_type(39 to 41),
nfa_initials_buckets_M_TAttribute => ac1_plb_M_TAttribute(208 to 223),
nfa_initials_buckets_M_lockErr => ac1_plb_M_lockErr(13),
nfa_initials_buckets_M_abort => ac1_plb_M_abort(13),
nfa_initials_buckets_M_UABus => ac1_plb_M_UABus(416 to 447),
nfa_initials_buckets_M_ABus => ac1_plb_M_ABus(416 to 447),
nfa_initials_buckets_M_wrDBus => ac1_plb_M_wrDBus(832 to 895),
nfa_initials_buckets_M_wrBurst => ac1_plb_M_wrBurst(13),
nfa_initials_buckets_M_rdBurst => ac1_plb_M_rdBurst(13),
nfa_initials_buckets_PLB_MAddrAck => ac1_plb_PLB_MAddrAck(13),
nfa_initials_buckets_PLB_MSSize => ac1_plb_PLB_MSSize(26 to 27),
nfa_initials_buckets_PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate(13),
nfa_initials_buckets_PLB_MTimeout => ac1_plb_PLB_MTimeout(13),
nfa_initials_buckets_PLB_MBusy => ac1_plb_PLB_MBusy(13),
nfa_initials_buckets_PLB_MRdErr => ac1_plb_PLB_MRdErr(13),
nfa_initials_buckets_PLB_MWrErr => ac1_plb_PLB_MWrErr(13),
nfa_initials_buckets_PLB_MIRQ => ac1_plb_PLB_MIRQ(13),
nfa_initials_buckets_PLB_MRdDBus => ac1_plb_PLB_MRdDBus(832 to 895),
nfa_initials_buckets_PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr(52 to 55),
nfa_initials_buckets_PLB_MRdDAck => ac1_plb_PLB_MRdDAck(13),
nfa_initials_buckets_PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm(13),
nfa_initials_buckets_PLB_MWrDAck => ac1_plb_PLB_MWrDAck(13),
nfa_initials_buckets_PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm(13),
sample_buffer_MPLB_Clk => net_gnd0,
sample_buffer_MPLB_Rst => ac1_plb_MPLB_Rst(14),
sample_buffer_M_request => ac1_plb_M_request(14),
sample_buffer_M_priority => ac1_plb_M_priority(28 to 29),
sample_buffer_M_busLock => ac1_plb_M_busLock(14),
sample_buffer_M_RNW => ac1_plb_M_RNW(14),
sample_buffer_M_BE => ac1_plb_M_BE(112 to 119),
sample_buffer_M_MSize => ac1_plb_M_MSize(28 to 29),
sample_buffer_M_size => ac1_plb_M_size(56 to 59),
sample_buffer_M_type => ac1_plb_M_type(42 to 44),
sample_buffer_M_TAttribute => ac1_plb_M_TAttribute(224 to 239),
sample_buffer_M_lockErr => ac1_plb_M_lockErr(14),
sample_buffer_M_abort => ac1_plb_M_abort(14),
sample_buffer_M_UABus => ac1_plb_M_UABus(448 to 479),
sample_buffer_M_ABus => ac1_plb_M_ABus(448 to 479),
sample_buffer_M_wrDBus => ac1_plb_M_wrDBus(896 to 959),
sample_buffer_M_wrBurst => ac1_plb_M_wrBurst(14),
sample_buffer_M_rdBurst => ac1_plb_M_rdBurst(14),
sample_buffer_PLB_MAddrAck => ac1_plb_PLB_MAddrAck(14),
sample_buffer_PLB_MSSize => ac1_plb_PLB_MSSize(28 to 29),
sample_buffer_PLB_MRearbitrate => ac1_plb_PLB_MRearbitrate(14),
sample_buffer_PLB_MTimeout => ac1_plb_PLB_MTimeout(14),
sample_buffer_PLB_MBusy => ac1_plb_PLB_MBusy(14),
sample_buffer_PLB_MRdErr => ac1_plb_PLB_MRdErr(14),
sample_buffer_PLB_MWrErr => ac1_plb_PLB_MWrErr(14),
sample_buffer_PLB_MIRQ => ac1_plb_PLB_MIRQ(14),
sample_buffer_PLB_MRdDBus => ac1_plb_PLB_MRdDBus(896 to 959),
sample_buffer_PLB_MRdWdAddr => ac1_plb_PLB_MRdWdAddr(56 to 59),
sample_buffer_PLB_MRdDAck => ac1_plb_PLB_MRdDAck(14),
sample_buffer_PLB_MRdBTerm => ac1_plb_PLB_MRdBTerm(14),
sample_buffer_PLB_MWrDAck => ac1_plb_PLB_MWrDAck(14),
sample_buffer_PLB_MWrBTerm => ac1_plb_PLB_MWrBTerm(14),
splb_slv0_SPLB_Clk => clk_125_0000MHzPLL0,
splb_slv0_SPLB_Rst => mb_plb_SPLB_Rst(11),
splb_slv0_PLB_ABus => mb_plb_PLB_ABus,
splb_slv0_PLB_UABus => mb_plb_PLB_UABus,
splb_slv0_PLB_PAValid => mb_plb_PLB_PAValid,
splb_slv0_PLB_SAValid => mb_plb_PLB_SAValid,
splb_slv0_PLB_rdPrim => mb_plb_PLB_rdPrim(11),
splb_slv0_PLB_wrPrim => mb_plb_PLB_wrPrim(11),
splb_slv0_PLB_masterID => mb_plb_PLB_masterID,
splb_slv0_PLB_abort => mb_plb_PLB_abort,
splb_slv0_PLB_busLock => mb_plb_PLB_busLock,
splb_slv0_PLB_RNW => mb_plb_PLB_RNW,
splb_slv0_PLB_BE => mb_plb_PLB_BE,
splb_slv0_PLB_MSize => mb_plb_PLB_MSize,
splb_slv0_PLB_size => mb_plb_PLB_size,
splb_slv0_PLB_type => mb_plb_PLB_type,
splb_slv0_PLB_lockErr => mb_plb_PLB_lockErr,
splb_slv0_PLB_wrDBus => mb_plb_PLB_wrDBus,
splb_slv0_PLB_wrBurst => mb_plb_PLB_wrBurst,
splb_slv0_PLB_rdBurst => mb_plb_PLB_rdBurst,
splb_slv0_PLB_wrPendReq => mb_plb_PLB_wrPendReq,
splb_slv0_PLB_rdPendReq => mb_plb_PLB_rdPendReq,
splb_slv0_PLB_wrPendPri => mb_plb_PLB_wrPendPri,
splb_slv0_PLB_rdPendPri => mb_plb_PLB_rdPendPri,
splb_slv0_PLB_reqPri => mb_plb_PLB_reqPri,
splb_slv0_PLB_TAttribute => mb_plb_PLB_TAttribute,
splb_slv0_Sl_addrAck => mb_plb_Sl_addrAck(11),
splb_slv0_Sl_SSize => mb_plb_Sl_SSize(22 to 23),
splb_slv0_Sl_wait => mb_plb_Sl_wait(11),
splb_slv0_Sl_rearbitrate => mb_plb_Sl_rearbitrate(11),
splb_slv0_Sl_wrDAck => mb_plb_Sl_wrDAck(11),
splb_slv0_Sl_wrComp => mb_plb_Sl_wrComp(11),
splb_slv0_Sl_wrBTerm => mb_plb_Sl_wrBTerm(11),
splb_slv0_Sl_rdDBus => mb_plb_Sl_rdDBus(704 to 767),
splb_slv0_Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(44 to 47),
splb_slv0_Sl_rdDAck => mb_plb_Sl_rdDAck(11),
splb_slv0_Sl_rdComp => mb_plb_Sl_rdComp(11),
splb_slv0_Sl_rdBTerm => mb_plb_Sl_rdBTerm(11),
splb_slv0_Sl_MBusy => mb_plb_Sl_MBusy(66 to 71),
splb_slv0_Sl_MWrErr => mb_plb_Sl_MWrErr(66 to 71),
splb_slv0_Sl_MRdErr => mb_plb_Sl_MRdErr(66 to 71),
splb_slv0_Sl_MIRQ => mb_plb_Sl_MIRQ(66 to 71)
);
iobuf_0 : IOBUF
port map (
I => fpga_0_SRAM_Mem_DQ_pin_O(0),
IO => fpga_0_SRAM_Mem_DQ_pin(0),
O => fpga_0_SRAM_Mem_DQ_pin_I(0),
T => fpga_0_SRAM_Mem_DQ_pin_T(0)
);
iobuf_1 : IOBUF
port map (
I => fpga_0_SRAM_Mem_DQ_pin_O(1),
IO => fpga_0_SRAM_Mem_DQ_pin(1),
O => fpga_0_SRAM_Mem_DQ_pin_I(1),
T => fpga_0_SRAM_Mem_DQ_pin_T(1)
);
iobuf_2 : IOBUF
port map (
I => fpga_0_SRAM_Mem_DQ_pin_O(2),
IO => fpga_0_SRAM_Mem_DQ_pin(2),
O => fpga_0_SRAM_Mem_DQ_pin_I(2),
T => fpga_0_SRAM_Mem_DQ_pin_T(2)
);
iobuf_3 : IOBUF
port map (
I => fpga_0_SRAM_Mem_DQ_pin_O(3),
IO => fpga_0_SRAM_Mem_DQ_pin(3),
O => fpga_0_SRAM_Mem_DQ_pin_I(3),
T => fpga_0_SRAM_Mem_DQ_pin_T(3)
);
iobuf_4 : IOBUF
port map (
I => fpga_0_SRAM_Mem_DQ_pin_O(4),
IO => fpga_0_SRAM_Mem_DQ_pin(4),
O => fpga_0_SRAM_Mem_DQ_pin_I(4),
T => fpga_0_SRAM_Mem_DQ_pin_T(4)
);
iobuf_5 : IOBUF
port map (
I => fpga_0_SRAM_Mem_DQ_pin_O(5),
IO => fpga_0_SRAM_Mem_DQ_pin(5),
O => fpga_0_SRAM_Mem_DQ_pin_I(5),
T => fpga_0_SRAM_Mem_DQ_pin_T(5)
);
iobuf_6 : IOBUF
port map (
I => fpga_0_SRAM_Mem_DQ_pin_O(6),
IO => fpga_0_SRAM_Mem_DQ_pin(6),
O => fpga_0_SRAM_Mem_DQ_pin_I(6),
T => fpga_0_SRAM_Mem_DQ_pin_T(6)
);
iobuf_7 : IOBUF
port map (
I => fpga_0_SRAM_Mem_DQ_pin_O(7),
IO => fpga_0_SRAM_Mem_DQ_pin(7),
O => fpga_0_SRAM_Mem_DQ_pin_I(7),
T => fpga_0_SRAM_Mem_DQ_pin_T(7)
);
iobuf_8 : IOBUF
port map (
I => fpga_0_SRAM_Mem_DQ_pin_O(8),
IO => fpga_0_SRAM_Mem_DQ_pin(8),
O => fpga_0_SRAM_Mem_DQ_pin_I(8),
T => fpga_0_SRAM_Mem_DQ_pin_T(8)
);
iobuf_9 : IOBUF
port map (
I => fpga_0_SRAM_Mem_DQ_pin_O(9),
IO => fpga_0_SRAM_Mem_DQ_pin(9),
O => fpga_0_SRAM_Mem_DQ_pin_I(9),
T => fpga_0_SRAM_Mem_DQ_pin_T(9)
);
iobuf_10 : IOBUF
port map (
I => fpga_0_SRAM_Mem_DQ_pin_O(10),
IO => fpga_0_SRAM_Mem_DQ_pin(10),
O => fpga_0_SRAM_Mem_DQ_pin_I(10),
T => fpga_0_SRAM_Mem_DQ_pin_T(10)
);
iobuf_11 : IOBUF
port map (
I => fpga_0_SRAM_Mem_DQ_pin_O(11),
IO => fpga_0_SRAM_Mem_DQ_pin(11),
O => fpga_0_SRAM_Mem_DQ_pin_I(11),
T => fpga_0_SRAM_Mem_DQ_pin_T(11)
);
iobuf_12 : IOBUF
port map (
I => fpga_0_SRAM_Mem_DQ_pin_O(12),
IO => fpga_0_SRAM_Mem_DQ_pin(12),
O => fpga_0_SRAM_Mem_DQ_pin_I(12),
T => fpga_0_SRAM_Mem_DQ_pin_T(12)
);
iobuf_13 : IOBUF
port map (
I => fpga_0_SRAM_Mem_DQ_pin_O(13),
IO => fpga_0_SRAM_Mem_DQ_pin(13),
O => fpga_0_SRAM_Mem_DQ_pin_I(13),
T => fpga_0_SRAM_Mem_DQ_pin_T(13)
);
iobuf_14 : IOBUF
port map (
I => fpga_0_SRAM_Mem_DQ_pin_O(14),
IO => fpga_0_SRAM_Mem_DQ_pin(14),
O => fpga_0_SRAM_Mem_DQ_pin_I(14),
T => fpga_0_SRAM_Mem_DQ_pin_T(14)
);
iobuf_15 : IOBUF
port map (
I => fpga_0_SRAM_Mem_DQ_pin_O(15),
IO => fpga_0_SRAM_Mem_DQ_pin(15),
O => fpga_0_SRAM_Mem_DQ_pin_I(15),
T => fpga_0_SRAM_Mem_DQ_pin_T(15)
);
iobuf_16 : IOBUF
port map (
I => fpga_0_SRAM_Mem_DQ_pin_O(16),
IO => fpga_0_SRAM_Mem_DQ_pin(16),
O => fpga_0_SRAM_Mem_DQ_pin_I(16),
T => fpga_0_SRAM_Mem_DQ_pin_T(16)
);
iobuf_17 : IOBUF
port map (
I => fpga_0_SRAM_Mem_DQ_pin_O(17),
IO => fpga_0_SRAM_Mem_DQ_pin(17),
O => fpga_0_SRAM_Mem_DQ_pin_I(17),
T => fpga_0_SRAM_Mem_DQ_pin_T(17)
);
iobuf_18 : IOBUF
port map (
I => fpga_0_SRAM_Mem_DQ_pin_O(18),
IO => fpga_0_SRAM_Mem_DQ_pin(18),
O => fpga_0_SRAM_Mem_DQ_pin_I(18),
T => fpga_0_SRAM_Mem_DQ_pin_T(18)
);
iobuf_19 : IOBUF
port map (
I => fpga_0_SRAM_Mem_DQ_pin_O(19),
IO => fpga_0_SRAM_Mem_DQ_pin(19),
O => fpga_0_SRAM_Mem_DQ_pin_I(19),
T => fpga_0_SRAM_Mem_DQ_pin_T(19)
);
iobuf_20 : IOBUF
port map (
I => fpga_0_SRAM_Mem_DQ_pin_O(20),
IO => fpga_0_SRAM_Mem_DQ_pin(20),
O => fpga_0_SRAM_Mem_DQ_pin_I(20),
T => fpga_0_SRAM_Mem_DQ_pin_T(20)
);
iobuf_21 : IOBUF
port map (
I => fpga_0_SRAM_Mem_DQ_pin_O(21),
IO => fpga_0_SRAM_Mem_DQ_pin(21),
O => fpga_0_SRAM_Mem_DQ_pin_I(21),
T => fpga_0_SRAM_Mem_DQ_pin_T(21)
);
iobuf_22 : IOBUF
port map (
I => fpga_0_SRAM_Mem_DQ_pin_O(22),
IO => fpga_0_SRAM_Mem_DQ_pin(22),
O => fpga_0_SRAM_Mem_DQ_pin_I(22),
T => fpga_0_SRAM_Mem_DQ_pin_T(22)
);
iobuf_23 : IOBUF
port map (
I => fpga_0_SRAM_Mem_DQ_pin_O(23),
IO => fpga_0_SRAM_Mem_DQ_pin(23),
O => fpga_0_SRAM_Mem_DQ_pin_I(23),
T => fpga_0_SRAM_Mem_DQ_pin_T(23)
);
iobuf_24 : IOBUF
port map (
I => fpga_0_SRAM_Mem_DQ_pin_O(24),
IO => fpga_0_SRAM_Mem_DQ_pin(24),
O => fpga_0_SRAM_Mem_DQ_pin_I(24),
T => fpga_0_SRAM_Mem_DQ_pin_T(24)
);
iobuf_25 : IOBUF
port map (
I => fpga_0_SRAM_Mem_DQ_pin_O(25),
IO => fpga_0_SRAM_Mem_DQ_pin(25),
O => fpga_0_SRAM_Mem_DQ_pin_I(25),
T => fpga_0_SRAM_Mem_DQ_pin_T(25)
);
iobuf_26 : IOBUF
port map (
I => fpga_0_SRAM_Mem_DQ_pin_O(26),
IO => fpga_0_SRAM_Mem_DQ_pin(26),
O => fpga_0_SRAM_Mem_DQ_pin_I(26),
T => fpga_0_SRAM_Mem_DQ_pin_T(26)
);
iobuf_27 : IOBUF
port map (
I => fpga_0_SRAM_Mem_DQ_pin_O(27),
IO => fpga_0_SRAM_Mem_DQ_pin(27),
O => fpga_0_SRAM_Mem_DQ_pin_I(27),
T => fpga_0_SRAM_Mem_DQ_pin_T(27)
);
iobuf_28 : IOBUF
port map (
I => fpga_0_SRAM_Mem_DQ_pin_O(28),
IO => fpga_0_SRAM_Mem_DQ_pin(28),
O => fpga_0_SRAM_Mem_DQ_pin_I(28),
T => fpga_0_SRAM_Mem_DQ_pin_T(28)
);
iobuf_29 : IOBUF
port map (
I => fpga_0_SRAM_Mem_DQ_pin_O(29),
IO => fpga_0_SRAM_Mem_DQ_pin(29),
O => fpga_0_SRAM_Mem_DQ_pin_I(29),
T => fpga_0_SRAM_Mem_DQ_pin_T(29)
);
iobuf_30 : IOBUF
port map (
I => fpga_0_SRAM_Mem_DQ_pin_O(30),
IO => fpga_0_SRAM_Mem_DQ_pin(30),
O => fpga_0_SRAM_Mem_DQ_pin_I(30),
T => fpga_0_SRAM_Mem_DQ_pin_T(30)
);
iobuf_31 : IOBUF
port map (
I => fpga_0_SRAM_Mem_DQ_pin_O(31),
IO => fpga_0_SRAM_Mem_DQ_pin(31),
O => fpga_0_SRAM_Mem_DQ_pin_I(31),
T => fpga_0_SRAM_Mem_DQ_pin_T(31)
);
ibufgds_32 : IBUFGDS
port map (
I => fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin,
IB => fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin,
O => PCIe_Diff_Clk
);
end architecture STRUCTURE;
| lgpl-3.0 | 1986df1d1a1f1bf5a18b70a76a13d638 | 0.614329 | 2.851965 | false | false | false | false |
wsoltys/AtomFpga | src/AtomGodilVideo/src/MINIUART/Rxunit.vhd | 1 | 3,421 | -------------------------------------------------------------------------------
-- Title : UART
-- Project : UART
-------------------------------------------------------------------------------
-- File : Rxunit.vhd
-- Author : Philippe CARTON
-- ([email protected])
-- Organization:
-- Created : 15/12/2001
-- Last update : 8/1/2003
-- Platform : Foundation 3.1i
-- Simulators : ModelSim 5.5b
-- Synthesizers: Xilinx Synthesis
-- Targets : Xilinx Spartan
-- Dependency : IEEE std_logic_1164
-------------------------------------------------------------------------------
-- Description: RxUnit is a serial to parallel unit Receiver.
-------------------------------------------------------------------------------
-- Copyright (c) notice
-- This core adheres to the GNU public license
--
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number :
-- Version :
-- Date :
-- Modifier : name <email>
-- Description :
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity RxUnit is
port (
Clk : in std_logic; -- system clock signal
Reset : in std_logic; -- Reset input
Enable : in std_logic; -- Enable input
ReadA : in Std_logic; -- Async Read Received Byte
RxD : in std_logic; -- RS-232 data input
RxAv : out std_logic; -- Byte available
DataO : out std_logic_vector(7 downto 0)); -- Byte received
end RxUnit;
architecture Behaviour of RxUnit is
signal RReg : std_logic_vector(7 downto 0); -- receive register
signal RRegL : std_logic; -- Byte received
begin
-- RxAv process
RxAvProc : process(RRegL,Reset,ReadA)
begin
if ReadA = '1' or Reset = '1' then
RxAv <= '0'; -- Negate RxAv when RReg read
elsif Rising_Edge(RRegL) then
RxAv <= '1'; -- Assert RxAv when RReg written
end if;
end process;
-- Rx Process
RxProc : process(Clk,Reset,Enable,RxD,RReg)
variable BitPos : INTEGER range 0 to 10; -- Position of the bit in the frame
variable SampleCnt : INTEGER range 0 to 3; -- Count from 0 to 3 in each bit
begin
if Reset = '1' then -- Reset
RRegL <= '0';
BitPos := 0;
elsif Rising_Edge(Clk) then
if Enable = '1' then
case BitPos is
when 0 => -- idle
RRegL <= '0';
if RxD = '0' then -- Start Bit
SampleCnt := 0;
BitPos := 1;
end if;
when 10 => -- Stop Bit
BitPos := 0; -- next is idle
RRegL <= '1'; -- Indicate byte received
DataO <= RReg; -- Store received byte
when others =>
if (SampleCnt = 1 and BitPos >= 2) then -- Sample RxD on 1
RReg(BitPos-2) <= RxD; -- Deserialisation
end if;
if SampleCnt = 3 then -- Increment BitPos on 3
BitPos := BitPos + 1;
end if;
end case;
if SampleCnt = 3 then
SampleCnt := 0;
else
sampleCnt := SampleCnt + 1;
end if;
end if;
end if;
end process;
end Behaviour;
| apache-2.0 | a9ffd67ba3cdc0f4f5a378f9f37f2e3b | 0.453961 | 4.324905 | false | false | false | false |
grwlf/vsim | vhdl_ct/WORK/arithmetic.vhd | 1 | 2,572 | -------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
package ARITHMETIC is
-- integer definitions
type t_int is range -2 ** 20 to 2 ** 20 ;
subtype st_int is t_int range 2 ** 15 downto -2 ** 20 ;
subtype intt is integer range -2 ** 20 to 2 ** 20 ;
subtype intst is integer range 2 ** 15 downto -2 ** 20 ;
constant c_int_1 : integer := 10 ;
constant c_int_2 : integer := -7 ;
constant c_t_int_1 : t_int := 500 ;
constant c_intt_1 : intt := 500 ;
constant c_t_int_2 : t_int := -3 ;
constant c_intt_2 : intt := -3 ;
constant c_st_int_1 : st_int := 5 ;
constant c_intst_1 : intst := 5 ;
constant c_st_int_2 : st_int := -400 ;
constant c_intst_2 : intst := -400 ;
constant ans_int1 : integer := 0 ;
constant ans_int2 : t_int := 7 ;
constant ans_int3 : st_int := -5 ;
-- physical type definitions
type t_phys is range -2 ** 20 to 2 ** 20
units
ones ;
tens = 10 ones ;
hundreds = 10 tens ;
five_hundreds = 50 tens ;
end units ;
subtype st_phys is t_phys range 2 ** 15 * ones downto -2 ** 20 * ones ;
constant c_time_1 : time := 1 ns ;
constant c_time_2 : time := 10 fs ;
constant c_t_phys_1 : t_phys := 5 hundreds ;
constant c_t_phys_2 : t_phys := (-3) * ones ;
constant c_st_phys_1 : st_phys := 5 ones ;
constant c_st_phys_2 : st_phys := (-4) * 10 ones ;
constant ans_phys1 : time := 999990 fs ;
constant ans_phys2 : t_phys := 7 ones ;
constant ans_phys3 : t_phys := -5 * 1 ones ;
-- real
type t_real is range -2.0E20 to 2.0E20 ;
subtype st_real is t_real range 2.0E15 downto -2.0E20 ;
subtype realt is real range -2.0E20 to 2.0E20 ;
subtype realst is real range 2.0E15 downto -2.0E20 ;
constant c_real_1 : real := 10.5 ;
constant c_real_2 : real := -7.3 ;
constant c_t_real_1 : t_real := 500.0 ;
constant c_realt_1 : realt := 500.0 ;
constant c_t_real_2 : t_real := -3.5 ;
constant c_realt_2 : realt := -3.5 ;
constant c_st_real_1 : st_real := 5.9 ;
constant c_realst_1 : realst := 5.9 ;
constant c_st_real_2 : st_real := -400.1 ;
constant c_realst_2 : realst := -400.1 ;
constant ans_real1 : real := 0.0 ;
constant ans_real2 : t_real := 9.0 ;
constant ans_real3 : t_real := -6.8 ;
constant acceptable_error : real := 0.001 ;
constant t_acceptable_error : t_real := 0.001 ;
end ARITHMETIC ;
| gpl-3.0 | 7d171fa7dcc705d527142c7ce9ac5678 | 0.544323 | 3.054632 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00031.vhd | 1 | 50,570 | -- NEED RESULT: ARCH00031.P1: Target of a variable assignment may be a aggregate of simple names passed
-- NEED RESULT: ARCH00031.P2: Target of a variable assignment may be a aggregate of simple names passed
-- NEED RESULT: ARCH00031.P3: Target of a variable assignment may be a aggregate of simple names passed
-- NEED RESULT: ARCH00031.P4: Target of a variable assignment may be a aggregate of simple names passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00031
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.4 (1)
-- 8.4 (3)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00031)
-- ENT00031_Test_Bench(ARCH00031_Test_Bench)
--
-- REVISION HISTORY:
--
-- 29-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00031 of E00000 is
signal Dummy : Boolean := false ;
--
begin
P1 :
process ( Dummy )
type arr_boolean is
array (integer range -1 downto - 3 ) of
boolean ;
type arr_bit is
array (integer range -1 downto - 3 ) of
bit ;
type arr_severity_level is
array (integer range -1 downto - 3 ) of
severity_level ;
type arr_character is
array (integer range -1 downto - 3 ) of
character ;
type arr_st_enum1 is
array (integer range -1 downto - 3 ) of
st_enum1 ;
type arr_integer is
array (integer range -1 downto - 3 ) of
integer ;
type arr_st_int1 is
array (integer range -1 downto - 3 ) of
st_int1 ;
type arr_time is
array (integer range -1 downto - 3 ) of
time ;
type arr_st_phys1 is
array (integer range -1 downto - 3 ) of
st_phys1 ;
type arr_real is
array (integer range -1 downto - 3 ) of
real ;
type arr_st_real1 is
array (integer range -1 downto - 3 ) of
st_real1 ;
type arr_st_rec1 is
array (integer range -1 downto - 3 ) of
st_rec1 ;
type arr_st_rec2 is
array (integer range -1 downto - 3 ) of
st_rec2 ;
type arr_st_rec3 is
array (integer range -1 downto - 3 ) of
st_rec3 ;
type arr_st_arr1 is
array (integer range -1 downto - 3 ) of
st_arr1 ;
type arr_st_arr2 is
array (integer range -1 downto - 3 ) of
st_arr2 ;
type arr_st_arr3 is
array (integer range -1 downto - 3 ) of
st_arr3 ;
--
variable v_boolean_1 : boolean :=
c_boolean_1 ;
variable v_bit_1 : bit :=
c_bit_1 ;
variable v_severity_level_1 : severity_level :=
c_severity_level_1 ;
variable v_character_1 : character :=
c_character_1 ;
variable v_st_enum1_1 : st_enum1 :=
c_st_enum1_1 ;
variable v_integer_1 : integer :=
c_integer_1 ;
variable v_st_int1_1 : st_int1 :=
c_st_int1_1 ;
variable v_time_1 : time :=
c_time_1 ;
variable v_st_phys1_1 : st_phys1 :=
c_st_phys1_1 ;
variable v_real_1 : real :=
c_real_1 ;
variable v_st_real1_1 : st_real1 :=
c_st_real1_1 ;
variable v_st_rec1_1 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_1 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_1 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_1 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_1 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_1 : st_arr3 :=
c_st_arr3_1 ;
--
variable v_boolean_2 : boolean :=
c_boolean_1 ;
variable v_bit_2 : bit :=
c_bit_1 ;
variable v_severity_level_2 : severity_level :=
c_severity_level_1 ;
variable v_character_2 : character :=
c_character_1 ;
variable v_st_enum1_2 : st_enum1 :=
c_st_enum1_1 ;
variable v_integer_2 : integer :=
c_integer_1 ;
variable v_st_int1_2 : st_int1 :=
c_st_int1_1 ;
variable v_time_2 : time :=
c_time_1 ;
variable v_st_phys1_2 : st_phys1 :=
c_st_phys1_1 ;
variable v_real_2 : real :=
c_real_1 ;
variable v_st_real1_2 : st_real1 :=
c_st_real1_1 ;
variable v_st_rec1_2 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_2 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_2 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_2 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_2 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_2 : st_arr3 :=
c_st_arr3_1 ;
--
variable v_boolean_3 : boolean :=
c_boolean_1 ;
variable v_bit_3 : bit :=
c_bit_1 ;
variable v_severity_level_3 : severity_level :=
c_severity_level_1 ;
variable v_character_3 : character :=
c_character_1 ;
variable v_st_enum1_3 : st_enum1 :=
c_st_enum1_1 ;
variable v_integer_3 : integer :=
c_integer_1 ;
variable v_st_int1_3 : st_int1 :=
c_st_int1_1 ;
variable v_time_3 : time :=
c_time_1 ;
variable v_st_phys1_3 : st_phys1 :=
c_st_phys1_1 ;
variable v_real_3 : real :=
c_real_1 ;
variable v_st_real1_3 : st_real1 :=
c_st_real1_1 ;
variable v_st_rec1_3 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_3 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_3 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_3 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_3 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_3 : st_arr3 :=
c_st_arr3_1 ;
--
variable correct : boolean := true ;
begin
( v_boolean_1
, v_boolean_2
, v_boolean_3
) := arr_boolean ' (
(Others => c_boolean_2)) ;
--
( v_bit_1
, v_bit_2
, v_bit_3
) := arr_bit ' (
(Others => c_bit_2)) ;
--
( v_severity_level_1
, v_severity_level_2
, v_severity_level_3
) := arr_severity_level ' (
(Others => c_severity_level_2)) ;
--
( v_character_1
, v_character_2
, v_character_3
) := arr_character ' (
(Others => c_character_2)) ;
--
( v_st_enum1_1
, v_st_enum1_2
, v_st_enum1_3
) := arr_st_enum1 ' (
(Others => c_st_enum1_2)) ;
--
( v_integer_1
, v_integer_2
, v_integer_3
) := arr_integer ' (
(Others => c_integer_2)) ;
--
( v_st_int1_1
, v_st_int1_2
, v_st_int1_3
) := arr_st_int1 ' (
(Others => c_st_int1_2)) ;
--
( v_time_1
, v_time_2
, v_time_3
) := arr_time ' (
(Others => c_time_2)) ;
--
( v_st_phys1_1
, v_st_phys1_2
, v_st_phys1_3
) := arr_st_phys1 ' (
(Others => c_st_phys1_2)) ;
--
( v_real_1
, v_real_2
, v_real_3
) := arr_real ' (
(Others => c_real_2)) ;
--
( v_st_real1_1
, v_st_real1_2
, v_st_real1_3
) := arr_st_real1 ' (
(Others => c_st_real1_2)) ;
--
( v_st_rec1_1
, v_st_rec1_2
, v_st_rec1_3
) := arr_st_rec1 ' (
(Others => c_st_rec1_2)) ;
--
( v_st_rec2_1
, v_st_rec2_2
, v_st_rec2_3
) := arr_st_rec2 ' (
(Others => c_st_rec2_2)) ;
--
( v_st_rec3_1
, v_st_rec3_2
, v_st_rec3_3
) := arr_st_rec3 ' (
(Others => c_st_rec3_2)) ;
--
( v_st_arr1_1
, v_st_arr1_2
, v_st_arr1_3
) := arr_st_arr1 ' (
(Others => c_st_arr1_2)) ;
--
( v_st_arr2_1
, v_st_arr2_2
, v_st_arr2_3
) := arr_st_arr2 ' (
(Others => c_st_arr2_2)) ;
--
( v_st_arr3_1
, v_st_arr3_2
, v_st_arr3_3
) := arr_st_arr3 ' (
(Others => c_st_arr3_2)) ;
--
--
correct := correct and
v_boolean_1 = c_boolean_2 ;
correct := correct and
v_bit_1 = c_bit_2 ;
correct := correct and
v_severity_level_1 = c_severity_level_2 ;
correct := correct and
v_character_1 = c_character_2 ;
correct := correct and
v_st_enum1_1 = c_st_enum1_2 ;
correct := correct and
v_integer_1 = c_integer_2 ;
correct := correct and
v_st_int1_1 = c_st_int1_2 ;
correct := correct and
v_time_1 = c_time_2 ;
correct := correct and
v_st_phys1_1 = c_st_phys1_2 ;
correct := correct and
v_real_1 = c_real_2 ;
correct := correct and
v_st_real1_1 = c_st_real1_2 ;
correct := correct and
v_st_rec1_1 = c_st_rec1_2 ;
correct := correct and
v_st_rec2_1 = c_st_rec2_2 ;
correct := correct and
v_st_rec3_1 = c_st_rec3_2 ;
correct := correct and
v_st_arr1_1 = c_st_arr1_2 ;
correct := correct and
v_st_arr2_1 = c_st_arr2_2 ;
correct := correct and
v_st_arr3_1 = c_st_arr3_2 ;
--
correct := correct and
v_boolean_2 = c_boolean_2 ;
correct := correct and
v_bit_2 = c_bit_2 ;
correct := correct and
v_severity_level_2 = c_severity_level_2 ;
correct := correct and
v_character_2 = c_character_2 ;
correct := correct and
v_st_enum1_2 = c_st_enum1_2 ;
correct := correct and
v_integer_2 = c_integer_2 ;
correct := correct and
v_st_int1_2 = c_st_int1_2 ;
correct := correct and
v_time_2 = c_time_2 ;
correct := correct and
v_st_phys1_2 = c_st_phys1_2 ;
correct := correct and
v_real_2 = c_real_2 ;
correct := correct and
v_st_real1_2 = c_st_real1_2 ;
correct := correct and
v_st_rec1_2 = c_st_rec1_2 ;
correct := correct and
v_st_rec2_2 = c_st_rec2_2 ;
correct := correct and
v_st_rec3_2 = c_st_rec3_2 ;
correct := correct and
v_st_arr1_2 = c_st_arr1_2 ;
correct := correct and
v_st_arr2_2 = c_st_arr2_2 ;
correct := correct and
v_st_arr3_2 = c_st_arr3_2 ;
--
correct := correct and
v_boolean_3 = c_boolean_2 ;
correct := correct and
v_bit_3 = c_bit_2 ;
correct := correct and
v_severity_level_3 = c_severity_level_2 ;
correct := correct and
v_character_3 = c_character_2 ;
correct := correct and
v_st_enum1_3 = c_st_enum1_2 ;
correct := correct and
v_integer_3 = c_integer_2 ;
correct := correct and
v_st_int1_3 = c_st_int1_2 ;
correct := correct and
v_time_3 = c_time_2 ;
correct := correct and
v_st_phys1_3 = c_st_phys1_2 ;
correct := correct and
v_real_3 = c_real_2 ;
correct := correct and
v_st_real1_3 = c_st_real1_2 ;
correct := correct and
v_st_rec1_3 = c_st_rec1_2 ;
correct := correct and
v_st_rec2_3 = c_st_rec2_2 ;
correct := correct and
v_st_rec3_3 = c_st_rec3_2 ;
correct := correct and
v_st_arr1_3 = c_st_arr1_2 ;
correct := correct and
v_st_arr2_3 = c_st_arr2_2 ;
correct := correct and
v_st_arr3_3 = c_st_arr3_2 ;
--
test_report ( "ARCH00031.P1" ,
"Target of a variable assignment may be a " &
"aggregate of simple names" ,
correct) ;
end process P1 ;
--
P2 :
process ( Dummy )
variable correct : boolean := true ;
--
procedure Proc1 is
type arr_boolean is
array (integer range -1 downto - 3 ) of
boolean ;
type arr_bit is
array (integer range -1 downto - 3 ) of
bit ;
type arr_severity_level is
array (integer range -1 downto - 3 ) of
severity_level ;
type arr_character is
array (integer range -1 downto - 3 ) of
character ;
type arr_st_enum1 is
array (integer range -1 downto - 3 ) of
st_enum1 ;
type arr_integer is
array (integer range -1 downto - 3 ) of
integer ;
type arr_st_int1 is
array (integer range -1 downto - 3 ) of
st_int1 ;
type arr_time is
array (integer range -1 downto - 3 ) of
time ;
type arr_st_phys1 is
array (integer range -1 downto - 3 ) of
st_phys1 ;
type arr_real is
array (integer range -1 downto - 3 ) of
real ;
type arr_st_real1 is
array (integer range -1 downto - 3 ) of
st_real1 ;
type arr_st_rec1 is
array (integer range -1 downto - 3 ) of
st_rec1 ;
type arr_st_rec2 is
array (integer range -1 downto - 3 ) of
st_rec2 ;
type arr_st_rec3 is
array (integer range -1 downto - 3 ) of
st_rec3 ;
type arr_st_arr1 is
array (integer range -1 downto - 3 ) of
st_arr1 ;
type arr_st_arr2 is
array (integer range -1 downto - 3 ) of
st_arr2 ;
type arr_st_arr3 is
array (integer range -1 downto - 3 ) of
st_arr3 ;
--
variable v_boolean_1 : boolean :=
c_boolean_1 ;
variable v_bit_1 : bit :=
c_bit_1 ;
variable v_severity_level_1 : severity_level :=
c_severity_level_1 ;
variable v_character_1 : character :=
c_character_1 ;
variable v_st_enum1_1 : st_enum1 :=
c_st_enum1_1 ;
variable v_integer_1 : integer :=
c_integer_1 ;
variable v_st_int1_1 : st_int1 :=
c_st_int1_1 ;
variable v_time_1 : time :=
c_time_1 ;
variable v_st_phys1_1 : st_phys1 :=
c_st_phys1_1 ;
variable v_real_1 : real :=
c_real_1 ;
variable v_st_real1_1 : st_real1 :=
c_st_real1_1 ;
variable v_st_rec1_1 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_1 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_1 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_1 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_1 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_1 : st_arr3 :=
c_st_arr3_1 ;
--
variable v_boolean_2 : boolean :=
c_boolean_1 ;
variable v_bit_2 : bit :=
c_bit_1 ;
variable v_severity_level_2 : severity_level :=
c_severity_level_1 ;
variable v_character_2 : character :=
c_character_1 ;
variable v_st_enum1_2 : st_enum1 :=
c_st_enum1_1 ;
variable v_integer_2 : integer :=
c_integer_1 ;
variable v_st_int1_2 : st_int1 :=
c_st_int1_1 ;
variable v_time_2 : time :=
c_time_1 ;
variable v_st_phys1_2 : st_phys1 :=
c_st_phys1_1 ;
variable v_real_2 : real :=
c_real_1 ;
variable v_st_real1_2 : st_real1 :=
c_st_real1_1 ;
variable v_st_rec1_2 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_2 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_2 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_2 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_2 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_2 : st_arr3 :=
c_st_arr3_1 ;
--
variable v_boolean_3 : boolean :=
c_boolean_1 ;
variable v_bit_3 : bit :=
c_bit_1 ;
variable v_severity_level_3 : severity_level :=
c_severity_level_1 ;
variable v_character_3 : character :=
c_character_1 ;
variable v_st_enum1_3 : st_enum1 :=
c_st_enum1_1 ;
variable v_integer_3 : integer :=
c_integer_1 ;
variable v_st_int1_3 : st_int1 :=
c_st_int1_1 ;
variable v_time_3 : time :=
c_time_1 ;
variable v_st_phys1_3 : st_phys1 :=
c_st_phys1_1 ;
variable v_real_3 : real :=
c_real_1 ;
variable v_st_real1_3 : st_real1 :=
c_st_real1_1 ;
variable v_st_rec1_3 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_3 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_3 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_3 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_3 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_3 : st_arr3 :=
c_st_arr3_1 ;
--
begin
( v_boolean_1
, v_boolean_2
, v_boolean_3
) := arr_boolean ' (
(Others => c_boolean_2)) ;
--
( v_bit_1
, v_bit_2
, v_bit_3
) := arr_bit ' (
(Others => c_bit_2)) ;
--
( v_severity_level_1
, v_severity_level_2
, v_severity_level_3
) := arr_severity_level ' (
(Others => c_severity_level_2)) ;
--
( v_character_1
, v_character_2
, v_character_3
) := arr_character ' (
(Others => c_character_2)) ;
--
( v_st_enum1_1
, v_st_enum1_2
, v_st_enum1_3
) := arr_st_enum1 ' (
(Others => c_st_enum1_2)) ;
--
( v_integer_1
, v_integer_2
, v_integer_3
) := arr_integer ' (
(Others => c_integer_2)) ;
--
( v_st_int1_1
, v_st_int1_2
, v_st_int1_3
) := arr_st_int1 ' (
(Others => c_st_int1_2)) ;
--
( v_time_1
, v_time_2
, v_time_3
) := arr_time ' (
(Others => c_time_2)) ;
--
( v_st_phys1_1
, v_st_phys1_2
, v_st_phys1_3
) := arr_st_phys1 ' (
(Others => c_st_phys1_2)) ;
--
( v_real_1
, v_real_2
, v_real_3
) := arr_real ' (
(Others => c_real_2)) ;
--
( v_st_real1_1
, v_st_real1_2
, v_st_real1_3
) := arr_st_real1 ' (
(Others => c_st_real1_2)) ;
--
( v_st_rec1_1
, v_st_rec1_2
, v_st_rec1_3
) := arr_st_rec1 ' (
(Others => c_st_rec1_2)) ;
--
( v_st_rec2_1
, v_st_rec2_2
, v_st_rec2_3
) := arr_st_rec2 ' (
(Others => c_st_rec2_2)) ;
--
( v_st_rec3_1
, v_st_rec3_2
, v_st_rec3_3
) := arr_st_rec3 ' (
(Others => c_st_rec3_2)) ;
--
( v_st_arr1_1
, v_st_arr1_2
, v_st_arr1_3
) := arr_st_arr1 ' (
(Others => c_st_arr1_2)) ;
--
( v_st_arr2_1
, v_st_arr2_2
, v_st_arr2_3
) := arr_st_arr2 ' (
(Others => c_st_arr2_2)) ;
--
( v_st_arr3_1
, v_st_arr3_2
, v_st_arr3_3
) := arr_st_arr3 ' (
(Others => c_st_arr3_2)) ;
--
--
correct := correct and
v_boolean_1 = c_boolean_2 ;
correct := correct and
v_bit_1 = c_bit_2 ;
correct := correct and
v_severity_level_1 = c_severity_level_2 ;
correct := correct and
v_character_1 = c_character_2 ;
correct := correct and
v_st_enum1_1 = c_st_enum1_2 ;
correct := correct and
v_integer_1 = c_integer_2 ;
correct := correct and
v_st_int1_1 = c_st_int1_2 ;
correct := correct and
v_time_1 = c_time_2 ;
correct := correct and
v_st_phys1_1 = c_st_phys1_2 ;
correct := correct and
v_real_1 = c_real_2 ;
correct := correct and
v_st_real1_1 = c_st_real1_2 ;
correct := correct and
v_st_rec1_1 = c_st_rec1_2 ;
correct := correct and
v_st_rec2_1 = c_st_rec2_2 ;
correct := correct and
v_st_rec3_1 = c_st_rec3_2 ;
correct := correct and
v_st_arr1_1 = c_st_arr1_2 ;
correct := correct and
v_st_arr2_1 = c_st_arr2_2 ;
correct := correct and
v_st_arr3_1 = c_st_arr3_2 ;
--
correct := correct and
v_boolean_2 = c_boolean_2 ;
correct := correct and
v_bit_2 = c_bit_2 ;
correct := correct and
v_severity_level_2 = c_severity_level_2 ;
correct := correct and
v_character_2 = c_character_2 ;
correct := correct and
v_st_enum1_2 = c_st_enum1_2 ;
correct := correct and
v_integer_2 = c_integer_2 ;
correct := correct and
v_st_int1_2 = c_st_int1_2 ;
correct := correct and
v_time_2 = c_time_2 ;
correct := correct and
v_st_phys1_2 = c_st_phys1_2 ;
correct := correct and
v_real_2 = c_real_2 ;
correct := correct and
v_st_real1_2 = c_st_real1_2 ;
correct := correct and
v_st_rec1_2 = c_st_rec1_2 ;
correct := correct and
v_st_rec2_2 = c_st_rec2_2 ;
correct := correct and
v_st_rec3_2 = c_st_rec3_2 ;
correct := correct and
v_st_arr1_2 = c_st_arr1_2 ;
correct := correct and
v_st_arr2_2 = c_st_arr2_2 ;
correct := correct and
v_st_arr3_2 = c_st_arr3_2 ;
--
correct := correct and
v_boolean_3 = c_boolean_2 ;
correct := correct and
v_bit_3 = c_bit_2 ;
correct := correct and
v_severity_level_3 = c_severity_level_2 ;
correct := correct and
v_character_3 = c_character_2 ;
correct := correct and
v_st_enum1_3 = c_st_enum1_2 ;
correct := correct and
v_integer_3 = c_integer_2 ;
correct := correct and
v_st_int1_3 = c_st_int1_2 ;
correct := correct and
v_time_3 = c_time_2 ;
correct := correct and
v_st_phys1_3 = c_st_phys1_2 ;
correct := correct and
v_real_3 = c_real_2 ;
correct := correct and
v_st_real1_3 = c_st_real1_2 ;
correct := correct and
v_st_rec1_3 = c_st_rec1_2 ;
correct := correct and
v_st_rec2_3 = c_st_rec2_2 ;
correct := correct and
v_st_rec3_3 = c_st_rec3_2 ;
correct := correct and
v_st_arr1_3 = c_st_arr1_2 ;
correct := correct and
v_st_arr2_3 = c_st_arr2_2 ;
correct := correct and
v_st_arr3_3 = c_st_arr3_2 ;
--
end Proc1 ;
begin
Proc1 ;
test_report ( "ARCH00031.P2" ,
"Target of a variable assignment may be a " &
"aggregate of simple names" ,
correct) ;
end process P2 ;
--
P3 :
process ( Dummy )
type arr_boolean is
array (integer range -1 downto - 3 ) of
boolean ;
type arr_bit is
array (integer range -1 downto - 3 ) of
bit ;
type arr_severity_level is
array (integer range -1 downto - 3 ) of
severity_level ;
type arr_character is
array (integer range -1 downto - 3 ) of
character ;
type arr_st_enum1 is
array (integer range -1 downto - 3 ) of
st_enum1 ;
type arr_integer is
array (integer range -1 downto - 3 ) of
integer ;
type arr_st_int1 is
array (integer range -1 downto - 3 ) of
st_int1 ;
type arr_time is
array (integer range -1 downto - 3 ) of
time ;
type arr_st_phys1 is
array (integer range -1 downto - 3 ) of
st_phys1 ;
type arr_real is
array (integer range -1 downto - 3 ) of
real ;
type arr_st_real1 is
array (integer range -1 downto - 3 ) of
st_real1 ;
type arr_st_rec1 is
array (integer range -1 downto - 3 ) of
st_rec1 ;
type arr_st_rec2 is
array (integer range -1 downto - 3 ) of
st_rec2 ;
type arr_st_rec3 is
array (integer range -1 downto - 3 ) of
st_rec3 ;
type arr_st_arr1 is
array (integer range -1 downto - 3 ) of
st_arr1 ;
type arr_st_arr2 is
array (integer range -1 downto - 3 ) of
st_arr2 ;
type arr_st_arr3 is
array (integer range -1 downto - 3 ) of
st_arr3 ;
--
variable v_boolean_1 : boolean :=
c_boolean_1 ;
variable v_bit_1 : bit :=
c_bit_1 ;
variable v_severity_level_1 : severity_level :=
c_severity_level_1 ;
variable v_character_1 : character :=
c_character_1 ;
variable v_st_enum1_1 : st_enum1 :=
c_st_enum1_1 ;
variable v_integer_1 : integer :=
c_integer_1 ;
variable v_st_int1_1 : st_int1 :=
c_st_int1_1 ;
variable v_time_1 : time :=
c_time_1 ;
variable v_st_phys1_1 : st_phys1 :=
c_st_phys1_1 ;
variable v_real_1 : real :=
c_real_1 ;
variable v_st_real1_1 : st_real1 :=
c_st_real1_1 ;
variable v_st_rec1_1 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_1 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_1 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_1 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_1 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_1 : st_arr3 :=
c_st_arr3_1 ;
--
variable v_boolean_2 : boolean :=
c_boolean_1 ;
variable v_bit_2 : bit :=
c_bit_1 ;
variable v_severity_level_2 : severity_level :=
c_severity_level_1 ;
variable v_character_2 : character :=
c_character_1 ;
variable v_st_enum1_2 : st_enum1 :=
c_st_enum1_1 ;
variable v_integer_2 : integer :=
c_integer_1 ;
variable v_st_int1_2 : st_int1 :=
c_st_int1_1 ;
variable v_time_2 : time :=
c_time_1 ;
variable v_st_phys1_2 : st_phys1 :=
c_st_phys1_1 ;
variable v_real_2 : real :=
c_real_1 ;
variable v_st_real1_2 : st_real1 :=
c_st_real1_1 ;
variable v_st_rec1_2 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_2 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_2 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_2 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_2 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_2 : st_arr3 :=
c_st_arr3_1 ;
--
variable v_boolean_3 : boolean :=
c_boolean_1 ;
variable v_bit_3 : bit :=
c_bit_1 ;
variable v_severity_level_3 : severity_level :=
c_severity_level_1 ;
variable v_character_3 : character :=
c_character_1 ;
variable v_st_enum1_3 : st_enum1 :=
c_st_enum1_1 ;
variable v_integer_3 : integer :=
c_integer_1 ;
variable v_st_int1_3 : st_int1 :=
c_st_int1_1 ;
variable v_time_3 : time :=
c_time_1 ;
variable v_st_phys1_3 : st_phys1 :=
c_st_phys1_1 ;
variable v_real_3 : real :=
c_real_1 ;
variable v_st_real1_3 : st_real1 :=
c_st_real1_1 ;
variable v_st_rec1_3 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_3 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_3 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_3 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_3 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_3 : st_arr3 :=
c_st_arr3_1 ;
--
variable correct : boolean := true ;
--
procedure Proc1 is
begin
( v_boolean_1
, v_boolean_2
, v_boolean_3
) := arr_boolean ' (
(Others => c_boolean_2)) ;
--
( v_bit_1
, v_bit_2
, v_bit_3
) := arr_bit ' (
(Others => c_bit_2)) ;
--
( v_severity_level_1
, v_severity_level_2
, v_severity_level_3
) := arr_severity_level ' (
(Others => c_severity_level_2)) ;
--
( v_character_1
, v_character_2
, v_character_3
) := arr_character ' (
(Others => c_character_2)) ;
--
( v_st_enum1_1
, v_st_enum1_2
, v_st_enum1_3
) := arr_st_enum1 ' (
(Others => c_st_enum1_2)) ;
--
( v_integer_1
, v_integer_2
, v_integer_3
) := arr_integer ' (
(Others => c_integer_2)) ;
--
( v_st_int1_1
, v_st_int1_2
, v_st_int1_3
) := arr_st_int1 ' (
(Others => c_st_int1_2)) ;
--
( v_time_1
, v_time_2
, v_time_3
) := arr_time ' (
(Others => c_time_2)) ;
--
( v_st_phys1_1
, v_st_phys1_2
, v_st_phys1_3
) := arr_st_phys1 ' (
(Others => c_st_phys1_2)) ;
--
( v_real_1
, v_real_2
, v_real_3
) := arr_real ' (
(Others => c_real_2)) ;
--
( v_st_real1_1
, v_st_real1_2
, v_st_real1_3
) := arr_st_real1 ' (
(Others => c_st_real1_2)) ;
--
( v_st_rec1_1
, v_st_rec1_2
, v_st_rec1_3
) := arr_st_rec1 ' (
(Others => c_st_rec1_2)) ;
--
( v_st_rec2_1
, v_st_rec2_2
, v_st_rec2_3
) := arr_st_rec2 ' (
(Others => c_st_rec2_2)) ;
--
( v_st_rec3_1
, v_st_rec3_2
, v_st_rec3_3
) := arr_st_rec3 ' (
(Others => c_st_rec3_2)) ;
--
( v_st_arr1_1
, v_st_arr1_2
, v_st_arr1_3
) := arr_st_arr1 ' (
(Others => c_st_arr1_2)) ;
--
( v_st_arr2_1
, v_st_arr2_2
, v_st_arr2_3
) := arr_st_arr2 ' (
(Others => c_st_arr2_2)) ;
--
( v_st_arr3_1
, v_st_arr3_2
, v_st_arr3_3
) := arr_st_arr3 ' (
(Others => c_st_arr3_2)) ;
--
--
end Proc1 ;
begin
Proc1 ;
correct := correct and
v_boolean_1 = c_boolean_2 ;
correct := correct and
v_bit_1 = c_bit_2 ;
correct := correct and
v_severity_level_1 = c_severity_level_2 ;
correct := correct and
v_character_1 = c_character_2 ;
correct := correct and
v_st_enum1_1 = c_st_enum1_2 ;
correct := correct and
v_integer_1 = c_integer_2 ;
correct := correct and
v_st_int1_1 = c_st_int1_2 ;
correct := correct and
v_time_1 = c_time_2 ;
correct := correct and
v_st_phys1_1 = c_st_phys1_2 ;
correct := correct and
v_real_1 = c_real_2 ;
correct := correct and
v_st_real1_1 = c_st_real1_2 ;
correct := correct and
v_st_rec1_1 = c_st_rec1_2 ;
correct := correct and
v_st_rec2_1 = c_st_rec2_2 ;
correct := correct and
v_st_rec3_1 = c_st_rec3_2 ;
correct := correct and
v_st_arr1_1 = c_st_arr1_2 ;
correct := correct and
v_st_arr2_1 = c_st_arr2_2 ;
correct := correct and
v_st_arr3_1 = c_st_arr3_2 ;
--
correct := correct and
v_boolean_2 = c_boolean_2 ;
correct := correct and
v_bit_2 = c_bit_2 ;
correct := correct and
v_severity_level_2 = c_severity_level_2 ;
correct := correct and
v_character_2 = c_character_2 ;
correct := correct and
v_st_enum1_2 = c_st_enum1_2 ;
correct := correct and
v_integer_2 = c_integer_2 ;
correct := correct and
v_st_int1_2 = c_st_int1_2 ;
correct := correct and
v_time_2 = c_time_2 ;
correct := correct and
v_st_phys1_2 = c_st_phys1_2 ;
correct := correct and
v_real_2 = c_real_2 ;
correct := correct and
v_st_real1_2 = c_st_real1_2 ;
correct := correct and
v_st_rec1_2 = c_st_rec1_2 ;
correct := correct and
v_st_rec2_2 = c_st_rec2_2 ;
correct := correct and
v_st_rec3_2 = c_st_rec3_2 ;
correct := correct and
v_st_arr1_2 = c_st_arr1_2 ;
correct := correct and
v_st_arr2_2 = c_st_arr2_2 ;
correct := correct and
v_st_arr3_2 = c_st_arr3_2 ;
--
correct := correct and
v_boolean_3 = c_boolean_2 ;
correct := correct and
v_bit_3 = c_bit_2 ;
correct := correct and
v_severity_level_3 = c_severity_level_2 ;
correct := correct and
v_character_3 = c_character_2 ;
correct := correct and
v_st_enum1_3 = c_st_enum1_2 ;
correct := correct and
v_integer_3 = c_integer_2 ;
correct := correct and
v_st_int1_3 = c_st_int1_2 ;
correct := correct and
v_time_3 = c_time_2 ;
correct := correct and
v_st_phys1_3 = c_st_phys1_2 ;
correct := correct and
v_real_3 = c_real_2 ;
correct := correct and
v_st_real1_3 = c_st_real1_2 ;
correct := correct and
v_st_rec1_3 = c_st_rec1_2 ;
correct := correct and
v_st_rec2_3 = c_st_rec2_2 ;
correct := correct and
v_st_rec3_3 = c_st_rec3_2 ;
correct := correct and
v_st_arr1_3 = c_st_arr1_2 ;
correct := correct and
v_st_arr2_3 = c_st_arr2_2 ;
correct := correct and
v_st_arr3_3 = c_st_arr3_2 ;
--
test_report ( "ARCH00031.P3" ,
"Target of a variable assignment may be a " &
"aggregate of simple names" ,
correct) ;
end process P3 ;
--
P4 :
process ( Dummy )
type arr_boolean is
array (integer range -1 downto - 3 ) of
boolean ;
type arr_bit is
array (integer range -1 downto - 3 ) of
bit ;
type arr_severity_level is
array (integer range -1 downto - 3 ) of
severity_level ;
type arr_character is
array (integer range -1 downto - 3 ) of
character ;
type arr_st_enum1 is
array (integer range -1 downto - 3 ) of
st_enum1 ;
type arr_integer is
array (integer range -1 downto - 3 ) of
integer ;
type arr_st_int1 is
array (integer range -1 downto - 3 ) of
st_int1 ;
type arr_time is
array (integer range -1 downto - 3 ) of
time ;
type arr_st_phys1 is
array (integer range -1 downto - 3 ) of
st_phys1 ;
type arr_real is
array (integer range -1 downto - 3 ) of
real ;
type arr_st_real1 is
array (integer range -1 downto - 3 ) of
st_real1 ;
type arr_st_rec1 is
array (integer range -1 downto - 3 ) of
st_rec1 ;
type arr_st_rec2 is
array (integer range -1 downto - 3 ) of
st_rec2 ;
type arr_st_rec3 is
array (integer range -1 downto - 3 ) of
st_rec3 ;
type arr_st_arr1 is
array (integer range -1 downto - 3 ) of
st_arr1 ;
type arr_st_arr2 is
array (integer range -1 downto - 3 ) of
st_arr2 ;
type arr_st_arr3 is
array (integer range -1 downto - 3 ) of
st_arr3 ;
--
variable v_boolean_1 : boolean :=
c_boolean_1 ;
variable v_bit_1 : bit :=
c_bit_1 ;
variable v_severity_level_1 : severity_level :=
c_severity_level_1 ;
variable v_character_1 : character :=
c_character_1 ;
variable v_st_enum1_1 : st_enum1 :=
c_st_enum1_1 ;
variable v_integer_1 : integer :=
c_integer_1 ;
variable v_st_int1_1 : st_int1 :=
c_st_int1_1 ;
variable v_time_1 : time :=
c_time_1 ;
variable v_st_phys1_1 : st_phys1 :=
c_st_phys1_1 ;
variable v_real_1 : real :=
c_real_1 ;
variable v_st_real1_1 : st_real1 :=
c_st_real1_1 ;
variable v_st_rec1_1 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_1 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_1 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_1 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_1 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_1 : st_arr3 :=
c_st_arr3_1 ;
--
variable v_boolean_2 : boolean :=
c_boolean_1 ;
variable v_bit_2 : bit :=
c_bit_1 ;
variable v_severity_level_2 : severity_level :=
c_severity_level_1 ;
variable v_character_2 : character :=
c_character_1 ;
variable v_st_enum1_2 : st_enum1 :=
c_st_enum1_1 ;
variable v_integer_2 : integer :=
c_integer_1 ;
variable v_st_int1_2 : st_int1 :=
c_st_int1_1 ;
variable v_time_2 : time :=
c_time_1 ;
variable v_st_phys1_2 : st_phys1 :=
c_st_phys1_1 ;
variable v_real_2 : real :=
c_real_1 ;
variable v_st_real1_2 : st_real1 :=
c_st_real1_1 ;
variable v_st_rec1_2 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_2 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_2 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_2 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_2 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_2 : st_arr3 :=
c_st_arr3_1 ;
--
variable v_boolean_3 : boolean :=
c_boolean_1 ;
variable v_bit_3 : bit :=
c_bit_1 ;
variable v_severity_level_3 : severity_level :=
c_severity_level_1 ;
variable v_character_3 : character :=
c_character_1 ;
variable v_st_enum1_3 : st_enum1 :=
c_st_enum1_1 ;
variable v_integer_3 : integer :=
c_integer_1 ;
variable v_st_int1_3 : st_int1 :=
c_st_int1_1 ;
variable v_time_3 : time :=
c_time_1 ;
variable v_st_phys1_3 : st_phys1 :=
c_st_phys1_1 ;
variable v_real_3 : real :=
c_real_1 ;
variable v_st_real1_3 : st_real1 :=
c_st_real1_1 ;
variable v_st_rec1_3 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_3 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_3 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_3 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_3 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_3 : st_arr3 :=
c_st_arr3_1 ;
--
variable correct : boolean := true ;
--
procedure Proc1 (
v_boolean_2 : inout boolean
; v_bit_2 : inout bit
; v_severity_level_2 : inout severity_level
; v_character_2 : inout character
; v_st_enum1_2 : inout st_enum1
; v_integer_2 : inout integer
; v_st_int1_2 : inout st_int1
; v_time_2 : inout time
; v_st_phys1_2 : inout st_phys1
; v_real_2 : inout real
; v_st_real1_2 : inout st_real1
; v_st_rec1_2 : inout st_rec1
; v_st_rec2_2 : inout st_rec2
; v_st_rec3_2 : inout st_rec3
; v_st_arr1_2 : inout st_arr1
; v_st_arr2_2 : inout st_arr2
; v_st_arr3_2 : inout st_arr3
)
is
begin
( v_boolean_1
, v_boolean_2
, v_boolean_3
) := arr_boolean ' (
(Others => c_boolean_2)) ;
--
( v_bit_1
, v_bit_2
, v_bit_3
) := arr_bit ' (
(Others => c_bit_2)) ;
--
( v_severity_level_1
, v_severity_level_2
, v_severity_level_3
) := arr_severity_level ' (
(Others => c_severity_level_2)) ;
--
( v_character_1
, v_character_2
, v_character_3
) := arr_character ' (
(Others => c_character_2)) ;
--
( v_st_enum1_1
, v_st_enum1_2
, v_st_enum1_3
) := arr_st_enum1 ' (
(Others => c_st_enum1_2)) ;
--
( v_integer_1
, v_integer_2
, v_integer_3
) := arr_integer ' (
(Others => c_integer_2)) ;
--
( v_st_int1_1
, v_st_int1_2
, v_st_int1_3
) := arr_st_int1 ' (
(Others => c_st_int1_2)) ;
--
( v_time_1
, v_time_2
, v_time_3
) := arr_time ' (
(Others => c_time_2)) ;
--
( v_st_phys1_1
, v_st_phys1_2
, v_st_phys1_3
) := arr_st_phys1 ' (
(Others => c_st_phys1_2)) ;
--
( v_real_1
, v_real_2
, v_real_3
) := arr_real ' (
(Others => c_real_2)) ;
--
( v_st_real1_1
, v_st_real1_2
, v_st_real1_3
) := arr_st_real1 ' (
(Others => c_st_real1_2)) ;
--
( v_st_rec1_1
, v_st_rec1_2
, v_st_rec1_3
) := arr_st_rec1 ' (
(Others => c_st_rec1_2)) ;
--
( v_st_rec2_1
, v_st_rec2_2
, v_st_rec2_3
) := arr_st_rec2 ' (
(Others => c_st_rec2_2)) ;
--
( v_st_rec3_1
, v_st_rec3_2
, v_st_rec3_3
) := arr_st_rec3 ' (
(Others => c_st_rec3_2)) ;
--
( v_st_arr1_1
, v_st_arr1_2
, v_st_arr1_3
) := arr_st_arr1 ' (
(Others => c_st_arr1_2)) ;
--
( v_st_arr2_1
, v_st_arr2_2
, v_st_arr2_3
) := arr_st_arr2 ' (
(Others => c_st_arr2_2)) ;
--
( v_st_arr3_1
, v_st_arr3_2
, v_st_arr3_3
) := arr_st_arr3 ' (
(Others => c_st_arr3_2)) ;
--
--
end Proc1 ;
begin
Proc1 (
v_boolean_2
, v_bit_2
, v_severity_level_2
, v_character_2
, v_st_enum1_2
, v_integer_2
, v_st_int1_2
, v_time_2
, v_st_phys1_2
, v_real_2
, v_st_real1_2
, v_st_rec1_2
, v_st_rec2_2
, v_st_rec3_2
, v_st_arr1_2
, v_st_arr2_2
, v_st_arr3_2
) ;
correct := correct and
v_boolean_1 = c_boolean_2 ;
correct := correct and
v_bit_1 = c_bit_2 ;
correct := correct and
v_severity_level_1 = c_severity_level_2 ;
correct := correct and
v_character_1 = c_character_2 ;
correct := correct and
v_st_enum1_1 = c_st_enum1_2 ;
correct := correct and
v_integer_1 = c_integer_2 ;
correct := correct and
v_st_int1_1 = c_st_int1_2 ;
correct := correct and
v_time_1 = c_time_2 ;
correct := correct and
v_st_phys1_1 = c_st_phys1_2 ;
correct := correct and
v_real_1 = c_real_2 ;
correct := correct and
v_st_real1_1 = c_st_real1_2 ;
correct := correct and
v_st_rec1_1 = c_st_rec1_2 ;
correct := correct and
v_st_rec2_1 = c_st_rec2_2 ;
correct := correct and
v_st_rec3_1 = c_st_rec3_2 ;
correct := correct and
v_st_arr1_1 = c_st_arr1_2 ;
correct := correct and
v_st_arr2_1 = c_st_arr2_2 ;
correct := correct and
v_st_arr3_1 = c_st_arr3_2 ;
--
correct := correct and
v_boolean_2 = c_boolean_2 ;
correct := correct and
v_bit_2 = c_bit_2 ;
correct := correct and
v_severity_level_2 = c_severity_level_2 ;
correct := correct and
v_character_2 = c_character_2 ;
correct := correct and
v_st_enum1_2 = c_st_enum1_2 ;
correct := correct and
v_integer_2 = c_integer_2 ;
correct := correct and
v_st_int1_2 = c_st_int1_2 ;
correct := correct and
v_time_2 = c_time_2 ;
correct := correct and
v_st_phys1_2 = c_st_phys1_2 ;
correct := correct and
v_real_2 = c_real_2 ;
correct := correct and
v_st_real1_2 = c_st_real1_2 ;
correct := correct and
v_st_rec1_2 = c_st_rec1_2 ;
correct := correct and
v_st_rec2_2 = c_st_rec2_2 ;
correct := correct and
v_st_rec3_2 = c_st_rec3_2 ;
correct := correct and
v_st_arr1_2 = c_st_arr1_2 ;
correct := correct and
v_st_arr2_2 = c_st_arr2_2 ;
correct := correct and
v_st_arr3_2 = c_st_arr3_2 ;
--
correct := correct and
v_boolean_3 = c_boolean_2 ;
correct := correct and
v_bit_3 = c_bit_2 ;
correct := correct and
v_severity_level_3 = c_severity_level_2 ;
correct := correct and
v_character_3 = c_character_2 ;
correct := correct and
v_st_enum1_3 = c_st_enum1_2 ;
correct := correct and
v_integer_3 = c_integer_2 ;
correct := correct and
v_st_int1_3 = c_st_int1_2 ;
correct := correct and
v_time_3 = c_time_2 ;
correct := correct and
v_st_phys1_3 = c_st_phys1_2 ;
correct := correct and
v_real_3 = c_real_2 ;
correct := correct and
v_st_real1_3 = c_st_real1_2 ;
correct := correct and
v_st_rec1_3 = c_st_rec1_2 ;
correct := correct and
v_st_rec2_3 = c_st_rec2_2 ;
correct := correct and
v_st_rec3_3 = c_st_rec3_2 ;
correct := correct and
v_st_arr1_3 = c_st_arr1_2 ;
correct := correct and
v_st_arr2_3 = c_st_arr2_2 ;
correct := correct and
v_st_arr3_3 = c_st_arr3_2 ;
--
test_report ( "ARCH00031.P4" ,
"Target of a variable assignment may be a " &
"aggregate of simple names" ,
correct) ;
end process P4 ;
--
end ARCH00031 ;
--
entity ENT00031_Test_Bench is
end ENT00031_Test_Bench ;
--
architecture ARCH00031_Test_Bench of ENT00031_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00031 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00031_Test_Bench ;
| gpl-3.0 | eabb3807cf765892206ec8b4dec3106f | 0.435871 | 3.250836 | false | false | false | false |
grwlf/vsim | vhdl/IEEE/old/math_real.vhdl | 1 | 21,581 | ------------------------------------------------------------------------
--
-- Copyright 1996, 2006 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076-2006, IEEE Standard
-- VHDL Language Reference Manual. This source file may not be copied, sold, or
-- included with software that is sold without written permission from the IEEE
-- Standards Department. This source file may be used to implement this standard
-- and may be distributed in compiled form in any manner so long as the
-- compiled form does not allow direct decompilation of the original source file.
-- This source file may be copied for individual use between licensed users.
-- This source file is provided on an AS IS basis. The IEEE disclaims ANY
-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY
-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source
-- file shall indemnify and hold IEEE harmless from any damages or liability
-- arising out of the use thereof.
--
-- Title: Standard VHDL Mathematical Packages (IEEE Std 1076-2006,
-- MATH_REAL)
--
-- Library: This package shall be compiled into a library
-- symbolically named IEEE.
--
-- Developers: IEEE DASC VHDL Mathematical Packages Working Group
--
-- Purpose: This package defines a standard for designers to use in
-- describing VHDL models that make use of common REAL constants
-- and common REAL elementary mathematical functions.
--
-- Limitation: The values generated by the functions in this package may
-- vary from platform to platform, and the precision of results
-- is only guaranteed to be the minimum required by IEEE Std 1076-
-- 2006.
--
-- Notes:
-- No declarations or definitions shall be included in, or
-- excluded from, this package.
-- The "package declaration" defines the types, subtypes, and
-- declarations of MATH_REAL.
-- The standard mathematical definition and conventional meaning
-- of the mathematical functions that are part of this standard
-- represent the formal semantics of the implementation of the
-- MATH_REAL package declaration. The purpose of the MATH_REAL
-- package body is to provide a guideline for implementations to
-- verify their implementation of MATH_REAL. Tool developers may
-- choose to implement the package body in the most efficient
-- manner available to them.
--
-- -----------------------------------------------------------------------------
-- Version : $Revision: 1.1 $
-- Date : $Date: 2006-06-08 10:39:22-04 $
-- -----------------------------------------------------------------------------
package MATH_REAL is
constant CopyRightNotice : STRING
:= "Copyright 1996, 2006 IEEE. All rights reserved.";
--
-- Constant Definitions
--
constant MATH_E : REAL := 2.71828_18284_59045_23536;
-- Value of e
constant MATH_1_OVER_E : REAL := 0.36787_94411_71442_32160;
-- Value of 1/e
constant MATH_PI : REAL := 3.14159_26535_89793_23846;
-- Value of pi
constant MATH_2_PI : REAL := 6.28318_53071_79586_47693;
-- Value of 2*pi
constant MATH_1_OVER_PI : REAL := 0.31830_98861_83790_67154;
-- Value of 1/pi
constant MATH_PI_OVER_2 : REAL := 1.57079_63267_94896_61923;
-- Value of pi/2
constant MATH_PI_OVER_3 : REAL := 1.04719_75511_96597_74615;
-- Value of pi/3
constant MATH_PI_OVER_4 : REAL := 0.78539_81633_97448_30962;
-- Value of pi/4
constant MATH_3_PI_OVER_2 : REAL := 4.71238_89803_84689_85769;
-- Value 3*pi/2
constant MATH_LOG_OF_2 : REAL := 0.69314_71805_59945_30942;
-- Natural log of 2
constant MATH_LOG_OF_10 : REAL := 2.30258_50929_94045_68402;
-- Natural log of 10
constant MATH_LOG2_OF_E : REAL := 1.44269_50408_88963_4074;
-- Log base 2 of e
constant MATH_LOG10_OF_E : REAL := 0.43429_44819_03251_82765;
-- Log base 10 of e
constant MATH_SQRT_2 : REAL := 1.41421_35623_73095_04880;
-- square root of 2
constant MATH_1_OVER_SQRT_2 : REAL := 0.70710_67811_86547_52440;
-- square root of 1/2
constant MATH_SQRT_PI : REAL := 1.77245_38509_05516_02730;
-- square root of pi
constant MATH_DEG_TO_RAD : REAL := 0.01745_32925_19943_29577;
-- Conversion factor from degree to radian
constant MATH_RAD_TO_DEG : REAL := 57.29577_95130_82320_87680;
-- Conversion factor from radian to degree
--
-- Function Declarations
--
function SIGN (X : in REAL) return REAL;
-- Purpose:
-- Returns 1.0 if X > 0.0; 0.0 if X = 0.0; -1.0 if X < 0.0
-- Special values:
-- None
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(SIGN(X)) <= 1.0
-- Notes:
-- None
function CEIL (X : in REAL) return REAL;
-- Purpose:
-- Returns smallest INTEGER value (as REAL) not less than X
-- Special values:
-- None
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- CEIL(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function FLOOR (X : in REAL) return REAL;
-- Purpose:
-- Returns largest INTEGER value (as REAL) not greater than X
-- Special values:
-- FLOOR(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- FLOOR(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function ROUND (X : in REAL) return REAL;
-- Purpose:
-- Rounds X to the nearest integer value (as real). If X is
-- halfway between two integers, rounding is away from 0.0
-- Special values:
-- ROUND(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ROUND(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function TRUNC (X : in REAL) return REAL;
-- Purpose:
-- Truncates X towards 0.0 and returns truncated value
-- Special values:
-- TRUNC(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- TRUNC(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function "MOD" (X, Y : in REAL) return REAL;
-- Purpose:
-- Returns floating point modulus of X/Y, with the same sign as
-- Y, and absolute value less than the absolute value of Y, and
-- for some INTEGER value N the result satisfies the relation
-- X = Y*N + MOD(X,Y)
-- Special values:
-- None
-- Domain:
-- X in REAL; Y in REAL and Y /= 0.0
-- Error conditions:
-- Error if Y = 0.0
-- Range:
-- ABS(MOD(X,Y)) < ABS(Y)
-- Notes:
-- None
function REALMAX (X, Y : in REAL) return REAL;
-- Purpose:
-- Returns the algebraically larger of X and Y
-- Special values:
-- REALMAX(X,Y) = X when X = Y
-- Domain:
-- X in REAL; Y in REAL
-- Error conditions:
-- None
-- Range:
-- REALMAX(X,Y) is mathematically unbounded
-- Notes:
-- None
function REALMIN (X, Y : in REAL) return REAL;
-- Purpose:
-- Returns the algebraically smaller of X and Y
-- Special values:
-- REALMIN(X,Y) = X when X = Y
-- Domain:
-- X in REAL; Y in REAL
-- Error conditions:
-- None
-- Range:
-- REALMIN(X,Y) is mathematically unbounded
-- Notes:
-- None
procedure UNIFORM(variable SEED1, SEED2 : inout POSITIVE; variable X : out REAL);
-- Purpose:
-- Returns, in X, a pseudo-random number with uniform
-- distribution in the open interval (0.0, 1.0).
-- Special values:
-- None
-- Domain:
-- 1 <= SEED1 <= 2147483562; 1 <= SEED2 <= 2147483398
-- Error conditions:
-- Error if SEED1 or SEED2 outside of valid domain
-- Range:
-- 0.0 < X < 1.0
-- Notes:
-- a) The semantics for this function are described by the
-- algorithm published by Pierre L'Ecuyer in "Communications
-- of the ACM," vol. 31, no. 6, June 1988, pp. 742-774.
-- The algorithm is based on the combination of two
-- multiplicative linear congruential generators for 32-bit
-- platforms.
--
-- b) Before the first call to UNIFORM, the seed values
-- (SEED1, SEED2) have to be initialized to values in the range
-- [1, 2147483562] and [1, 2147483398] respectively. The
-- seed values are modified after each call to UNIFORM.
--
-- c) This random number generator is portable for 32-bit
-- computers, and it has a period of ~2.30584*(10**18) for each
-- set of seed values.
--
-- d) For information on spectral tests for the algorithm, refer
-- to the L'Ecuyer article.
function SQRT (X : in REAL) return REAL;
-- Purpose:
-- Returns square root of X
-- Special values:
-- SQRT(0.0) = 0.0
-- SQRT(1.0) = 1.0
-- Domain:
-- X >= 0.0
-- Error conditions:
-- Error if X < 0.0
-- Range:
-- SQRT(X) >= 0.0
-- Notes:
-- a) The upper bound of the reachable range of SQRT is
-- approximately given by:
-- SQRT(X) <= SQRT(REAL'HIGH)
function CBRT (X : in REAL) return REAL;
-- Purpose:
-- Returns cube root of X
-- Special values:
-- CBRT(0.0) = 0.0
-- CBRT(1.0) = 1.0
-- CBRT(-1.0) = -1.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- CBRT(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of CBRT is approximately given by:
-- ABS(CBRT(X)) <= CBRT(REAL'HIGH)
function "**" (X : in INTEGER; Y : in REAL) return REAL;
-- Purpose:
-- Returns Y power of X ==> X**Y
-- Special values:
-- X**0.0 = 1.0; X /= 0
-- 0**Y = 0.0; Y > 0.0
-- X**1.0 = REAL(X); X >= 0
-- 1**Y = 1.0
-- Domain:
-- X > 0
-- X = 0 for Y > 0.0
-- X < 0 for Y = 0.0
-- Error conditions:
-- Error if X < 0 and Y /= 0.0
-- Error if X = 0 and Y <= 0.0
-- Range:
-- X**Y >= 0.0
-- Notes:
-- a) The upper bound of the reachable range for "**" is
-- approximately given by:
-- X**Y <= REAL'HIGH
function "**" (X : in REAL; Y : in REAL) return REAL;
-- Purpose:
-- Returns Y power of X ==> X**Y
-- Special values:
-- X**0.0 = 1.0; X /= 0.0
-- 0.0**Y = 0.0; Y > 0.0
-- X**1.0 = X; X >= 0.0
-- 1.0**Y = 1.0
-- Domain:
-- X > 0.0
-- X = 0.0 for Y > 0.0
-- X < 0.0 for Y = 0.0
-- Error conditions:
-- Error if X < 0.0 and Y /= 0.0
-- Error if X = 0.0 and Y <= 0.0
-- Range:
-- X**Y >= 0.0
-- Notes:
-- a) The upper bound of the reachable range for "**" is
-- approximately given by:
-- X**Y <= REAL'HIGH
function EXP (X : in REAL) return REAL;
-- Purpose:
-- Returns e**X; where e = MATH_E
-- Special values:
-- EXP(0.0) = 1.0
-- EXP(1.0) = MATH_E
-- EXP(-1.0) = MATH_1_OVER_E
-- EXP(X) = 0.0 for X <= -LOG(REAL'HIGH)
-- Domain:
-- X in REAL such that EXP(X) <= REAL'HIGH
-- Error conditions:
-- Error if X > LOG(REAL'HIGH)
-- Range:
-- EXP(X) >= 0.0
-- Notes:
-- a) The usable domain of EXP is approximately given by:
-- X <= LOG(REAL'HIGH)
function LOG (X : in REAL) return REAL;
-- Purpose:
-- Returns natural logarithm of X
-- Special values:
-- LOG(1.0) = 0.0
-- LOG(MATH_E) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG is approximately given by:
-- LOG(0+) <= LOG(X) <= LOG(REAL'HIGH)
function LOG2 (X : in REAL) return REAL;
-- Purpose:
-- Returns logarithm base 2 of X
-- Special values:
-- LOG2(1.0) = 0.0
-- LOG2(2.0) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG2(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG2 is approximately given by:
-- LOG2(0+) <= LOG2(X) <= LOG2(REAL'HIGH)
function LOG10 (X : in REAL) return REAL;
-- Purpose:
-- Returns logarithm base 10 of X
-- Special values:
-- LOG10(1.0) = 0.0
-- LOG10(10.0) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG10(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG10 is approximately given by:
-- LOG10(0+) <= LOG10(X) <= LOG10(REAL'HIGH)
function LOG (X : in REAL; BASE : in REAL) return REAL;
-- Purpose:
-- Returns logarithm base BASE of X
-- Special values:
-- LOG(1.0, BASE) = 0.0
-- LOG(BASE, BASE) = 1.0
-- Domain:
-- X > 0.0
-- BASE > 0.0
-- BASE /= 1.0
-- Error conditions:
-- Error if X <= 0.0
-- Error if BASE <= 0.0
-- Error if BASE = 1.0
-- Range:
-- LOG(X, BASE) is mathematically unbounded
-- Notes:
-- a) When BASE > 1.0, the reachable range of LOG is
-- approximately given by:
-- LOG(0+, BASE) <= LOG(X, BASE) <= LOG(REAL'HIGH, BASE)
-- b) When 0.0 < BASE < 1.0, the reachable range of LOG is
-- approximately given by:
-- LOG(REAL'HIGH, BASE) <= LOG(X, BASE) <= LOG(0+, BASE)
function SIN (X : in REAL) return REAL;
-- Purpose:
-- Returns sine of X; X in radians
-- Special values:
-- SIN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER
-- SIN(X) = 1.0 for X = (4*k+1)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- SIN(X) = -1.0 for X = (4*k+3)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(SIN(X)) <= 1.0
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function COS (X : in REAL) return REAL;
-- Purpose:
-- Returns cosine of X; X in radians
-- Special values:
-- COS(X) = 0.0 for X = (2*k+1)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- COS(X) = 1.0 for X = (2*k)*MATH_PI, where k is an INTEGER
-- COS(X) = -1.0 for X = (2*k+1)*MATH_PI, where k is an INTEGER
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(COS(X)) <= 1.0
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function TAN (X : in REAL) return REAL;
-- Purpose:
-- Returns tangent of X; X in radians
-- Special values:
-- TAN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER
-- Domain:
-- X in REAL and
-- X /= (2*k+1)*MATH_PI_OVER_2, where k is an INTEGER
-- Error conditions:
-- Error if X = ((2*k+1) * MATH_PI_OVER_2), where k is an
-- INTEGER
-- Range:
-- TAN(X) is mathematically unbounded
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function ARCSIN (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse sine of X
-- Special values:
-- ARCSIN(0.0) = 0.0
-- ARCSIN(1.0) = MATH_PI_OVER_2
-- ARCSIN(-1.0) = -MATH_PI_OVER_2
-- Domain:
-- ABS(X) <= 1.0
-- Error conditions:
-- Error if ABS(X) > 1.0
-- Range:
-- ABS(ARCSIN(X) <= MATH_PI_OVER_2
-- Notes:
-- None
function ARCCOS (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse cosine of X
-- Special values:
-- ARCCOS(1.0) = 0.0
-- ARCCOS(0.0) = MATH_PI_OVER_2
-- ARCCOS(-1.0) = MATH_PI
-- Domain:
-- ABS(X) <= 1.0
-- Error conditions:
-- Error if ABS(X) > 1.0
-- Range:
-- 0.0 <= ARCCOS(X) <= MATH_PI
-- Notes:
-- None
function ARCTAN (Y : in REAL) return REAL;
-- Purpose:
-- Returns the value of the angle in radians of the point
-- (1.0, Y), which is in rectangular coordinates
-- Special values:
-- ARCTAN(0.0) = 0.0
-- Domain:
-- Y in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(ARCTAN(Y)) <= MATH_PI_OVER_2
-- Notes:
-- None
function ARCTAN (Y : in REAL; X : in REAL) return REAL;
-- Purpose:
-- Returns the principal value of the angle in radians of
-- the point (X, Y), which is in rectangular coordinates
-- Special values:
-- ARCTAN(0.0, X) = 0.0 if X > 0.0
-- ARCTAN(0.0, X) = MATH_PI if X < 0.0
-- ARCTAN(Y, 0.0) = MATH_PI_OVER_2 if Y > 0.0
-- ARCTAN(Y, 0.0) = -MATH_PI_OVER_2 if Y < 0.0
-- Domain:
-- Y in REAL
-- X in REAL, X /= 0.0 when Y = 0.0
-- Error conditions:
-- Error if X = 0.0 and Y = 0.0
-- Range:
-- -MATH_PI < ARCTAN(Y,X) <= MATH_PI
-- Notes:
-- None
function SINH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic sine of X
-- Special values:
-- SINH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- SINH(X) is mathematically unbounded
-- Notes:
-- a) The usable domain of SINH is approximately given by:
-- ABS(X) <= LOG(REAL'HIGH)
function COSH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic cosine of X
-- Special values:
-- COSH(0.0) = 1.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- COSH(X) >= 1.0
-- Notes:
-- a) The usable domain of COSH is approximately given by:
-- ABS(X) <= LOG(REAL'HIGH)
function TANH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic tangent of X
-- Special values:
-- TANH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(TANH(X)) <= 1.0
-- Notes:
-- None
function ARCSINH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic sine of X
-- Special values:
-- ARCSINH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ARCSINH(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of ARCSINH is approximately given by:
-- ABS(ARCSINH(X)) <= LOG(REAL'HIGH)
function ARCCOSH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic cosine of X
-- Special values:
-- ARCCOSH(1.0) = 0.0
-- Domain:
-- X >= 1.0
-- Error conditions:
-- Error if X < 1.0
-- Range:
-- ARCCOSH(X) >= 0.0
-- Notes:
-- a) The upper bound of the reachable range of ARCCOSH is
-- approximately given by: ARCCOSH(X) <= LOG(REAL'HIGH)
function ARCTANH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic tangent of X
-- Special values:
-- ARCTANH(0.0) = 0.0
-- Domain:
-- ABS(X) < 1.0
-- Error conditions:
-- Error if ABS(X) >= 1.0
-- Range:
-- ARCTANH(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of ARCTANH is approximately given by:
-- ABS(ARCTANH(X)) < LOG(REAL'HIGH)
end package MATH_REAL;
| gpl-3.0 | 9209a8f506d122c84306ae30446ceaab | 0.506974 | 3.708713 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00181.vhd | 1 | 47,936 | -- NEED RESULT: ARCH00181.P1: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00181.P2: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00181.P3: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00181.P4: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00181.P5: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00181.P6: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00181: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Old transactions were removed on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Old transactions were removed on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Old transactions were removed on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Old transactions were removed on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Old transactions were removed on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Old transactions were removed on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00181: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: P6: Inertial transactions entirely completed failed
-- NEED RESULT: P5: Inertial transactions entirely completed failed
-- NEED RESULT: P4: Inertial transactions entirely completed failed
-- NEED RESULT: P3: Inertial transactions entirely completed failed
-- NEED RESULT: P2: Inertial transactions entirely completed failed
-- NEED RESULT: P1: Inertial transactions entirely completed failed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00181
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00181
-- PKG00181/BODY
-- ENT00181(ARCH00181)
-- ENT00181_Test_Bench(ARCH00181_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
package PKG00181 is
type r_st_arr1_vector is record
f1 : integer ;
f2 : st_arr1_vector ;
end record ;
function c_r_st_arr1_vector_1 return r_st_arr1_vector ;
-- (c_integer_1, c_st_arr1_vector_1) ;
function c_r_st_arr1_vector_2 return r_st_arr1_vector ;
-- (c_integer_2, c_st_arr1_vector_2) ;
--
type r_st_arr2_vector is record
f1 : integer ;
f2 : st_arr2_vector ;
end record ;
function c_r_st_arr2_vector_1 return r_st_arr2_vector ;
-- (c_integer_1, c_st_arr2_vector_1) ;
function c_r_st_arr2_vector_2 return r_st_arr2_vector ;
-- (c_integer_2, c_st_arr2_vector_2) ;
--
type r_st_arr3_vector is record
f1 : integer ;
f2 : st_arr3_vector ;
end record ;
function c_r_st_arr3_vector_1 return r_st_arr3_vector ;
-- (c_integer_1, c_st_arr3_vector_1) ;
function c_r_st_arr3_vector_2 return r_st_arr3_vector ;
-- (c_integer_2, c_st_arr3_vector_2) ;
--
type r_st_rec1_vector is record
f1 : integer ;
f2 : st_rec1_vector ;
end record ;
function c_r_st_rec1_vector_1 return r_st_rec1_vector ;
-- (c_integer_1, c_st_rec1_vector_1) ;
function c_r_st_rec1_vector_2 return r_st_rec1_vector ;
-- (c_integer_2, c_st_rec1_vector_2) ;
--
type r_st_rec2_vector is record
f1 : integer ;
f2 : st_rec2_vector ;
end record ;
function c_r_st_rec2_vector_1 return r_st_rec2_vector ;
-- (c_integer_1, c_st_rec2_vector_1) ;
function c_r_st_rec2_vector_2 return r_st_rec2_vector ;
-- (c_integer_2, c_st_rec2_vector_2) ;
--
type r_st_rec3_vector is record
f1 : integer ;
f2 : st_rec3_vector ;
end record ;
function c_r_st_rec3_vector_1 return r_st_rec3_vector ;
-- (c_integer_1, c_st_rec3_vector_1) ;
function c_r_st_rec3_vector_2 return r_st_rec3_vector ;
-- (c_integer_2, c_st_rec3_vector_2) ;
--
--
end PKG00181 ;
--
package body PKG00181 is
function c_r_st_arr1_vector_1 return r_st_arr1_vector
is begin
return (c_integer_1, c_st_arr1_vector_1) ;
end c_r_st_arr1_vector_1 ;
--
function c_r_st_arr1_vector_2 return r_st_arr1_vector
is begin
return (c_integer_2, c_st_arr1_vector_2) ;
end c_r_st_arr1_vector_2 ;
--
--
function c_r_st_arr2_vector_1 return r_st_arr2_vector
is begin
return (c_integer_1, c_st_arr2_vector_1) ;
end c_r_st_arr2_vector_1 ;
--
function c_r_st_arr2_vector_2 return r_st_arr2_vector
is begin
return (c_integer_2, c_st_arr2_vector_2) ;
end c_r_st_arr2_vector_2 ;
--
--
function c_r_st_arr3_vector_1 return r_st_arr3_vector
is begin
return (c_integer_1, c_st_arr3_vector_1) ;
end c_r_st_arr3_vector_1 ;
--
function c_r_st_arr3_vector_2 return r_st_arr3_vector
is begin
return (c_integer_2, c_st_arr3_vector_2) ;
end c_r_st_arr3_vector_2 ;
--
--
function c_r_st_rec1_vector_1 return r_st_rec1_vector
is begin
return (c_integer_1, c_st_rec1_vector_1) ;
end c_r_st_rec1_vector_1 ;
--
function c_r_st_rec1_vector_2 return r_st_rec1_vector
is begin
return (c_integer_2, c_st_rec1_vector_2) ;
end c_r_st_rec1_vector_2 ;
--
--
function c_r_st_rec2_vector_1 return r_st_rec2_vector
is begin
return (c_integer_1, c_st_rec2_vector_1) ;
end c_r_st_rec2_vector_1 ;
--
function c_r_st_rec2_vector_2 return r_st_rec2_vector
is begin
return (c_integer_2, c_st_rec2_vector_2) ;
end c_r_st_rec2_vector_2 ;
--
--
function c_r_st_rec3_vector_1 return r_st_rec3_vector
is begin
return (c_integer_1, c_st_rec3_vector_1) ;
end c_r_st_rec3_vector_1 ;
--
function c_r_st_rec3_vector_2 return r_st_rec3_vector
is begin
return (c_integer_2, c_st_rec3_vector_2) ;
end c_r_st_rec3_vector_2 ;
--
--
--
end PKG00181 ;
--
use WORK.STANDARD_TYPES.all ;
use WORK.PKG00181.all ;
entity ENT00181 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_r_st_arr1_vector : chk_sig_type := -1 ;
signal chk_r_st_arr2_vector : chk_sig_type := -1 ;
signal chk_r_st_arr3_vector : chk_sig_type := -1 ;
signal chk_r_st_rec1_vector : chk_sig_type := -1 ;
signal chk_r_st_rec2_vector : chk_sig_type := -1 ;
signal chk_r_st_rec3_vector : chk_sig_type := -1 ;
--
procedure Proc1 (
signal s_r_st_arr1_vector : inout r_st_arr1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_r_st_arr1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00181" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_arr1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
procedure Proc2 (
signal s_r_st_arr2_vector : inout r_st_arr2_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_r_st_arr2_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181.P2" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00181" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_arr2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc2 ;
--
procedure Proc3 (
signal s_r_st_arr3_vector : inout r_st_arr3_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_r_st_arr3_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181.P3" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00181" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_arr3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc3 ;
--
procedure Proc4 (
signal s_r_st_rec1_vector : inout r_st_rec1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_r_st_rec1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181.P4" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00181" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc4 ;
--
procedure Proc5 (
signal s_r_st_rec2_vector : inout r_st_rec2_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_r_st_rec2_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181.P5" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00181" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc5 ;
--
procedure Proc6 (
signal s_r_st_rec3_vector : inout r_st_rec3_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_r_st_rec3_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181.P6" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00181" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00181" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc6 ;
--
--
end ENT00181 ;
--
architecture ARCH00181 of ENT00181 is
signal s_r_st_arr1_vector : r_st_arr1_vector
:= c_r_st_arr1_vector_1 ;
signal s_r_st_arr2_vector : r_st_arr2_vector
:= c_r_st_arr2_vector_1 ;
signal s_r_st_arr3_vector : r_st_arr3_vector
:= c_r_st_arr3_vector_1 ;
signal s_r_st_rec1_vector : r_st_rec1_vector
:= c_r_st_rec1_vector_1 ;
signal s_r_st_rec2_vector : r_st_rec2_vector
:= c_r_st_rec2_vector_1 ;
signal s_r_st_rec3_vector : r_st_rec3_vector
:= c_r_st_rec3_vector_1 ;
--
begin
P1 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc1 (
s_r_st_arr1_vector,
counter,
correct,
savtime,
chk_r_st_arr1_vector
) ;
wait until (not s_r_st_arr1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_r_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_r_st_arr1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
P2 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc2 (
s_r_st_arr2_vector,
counter,
correct,
savtime,
chk_r_st_arr2_vector
) ;
wait until (not s_r_st_arr2_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P2 ;
--
PGEN_CHKP_2 :
process ( chk_r_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions entirely completed",
chk_r_st_arr2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
P3 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc3 (
s_r_st_arr3_vector,
counter,
correct,
savtime,
chk_r_st_arr3_vector
) ;
wait until (not s_r_st_arr3_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P3 ;
--
PGEN_CHKP_3 :
process ( chk_r_st_arr3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions entirely completed",
chk_r_st_arr3_vector = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
P4 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc4 (
s_r_st_rec1_vector,
counter,
correct,
savtime,
chk_r_st_rec1_vector
) ;
wait until (not s_r_st_rec1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P4 ;
--
PGEN_CHKP_4 :
process ( chk_r_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Inertial transactions entirely completed",
chk_r_st_rec1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
--
P5 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc5 (
s_r_st_rec2_vector,
counter,
correct,
savtime,
chk_r_st_rec2_vector
) ;
wait until (not s_r_st_rec2_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P5 ;
--
PGEN_CHKP_5 :
process ( chk_r_st_rec2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Inertial transactions entirely completed",
chk_r_st_rec2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
--
P6 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc6 (
s_r_st_rec3_vector,
counter,
correct,
savtime,
chk_r_st_rec3_vector
) ;
wait until (not s_r_st_rec3_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P6 ;
--
PGEN_CHKP_6 :
process ( chk_r_st_rec3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Inertial transactions entirely completed",
chk_r_st_rec3_vector = 8 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
--
--
end ARCH00181 ;
--
entity ENT00181_Test_Bench is
end ENT00181_Test_Bench ;
--
architecture ARCH00181_Test_Bench of ENT00181_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00181 ( ARCH00181 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00181_Test_Bench ;
| gpl-3.0 | 509026c20eee777e5281004475f53b31 | 0.525555 | 3.347486 | false | false | false | false |
TWW12/lzw | ip_repo/axi_compression_1.0/src/dictionary_block_4.vhd | 4 | 7,917 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity dictionary_block_4 is
generic( block_num : integer := 0);
port (
clk : in std_logic;
rst : in std_logic;
start_search : in std_logic;
search_entry : in std_logic_vector(19 downto 0);
halt_search : in std_logic;
--Write enable & entries
wr_en : in std_logic;
wr_addr : in std_logic_vector(9 downto 0);
wr_entry : in std_logic_vector(19 downto 0);
--Outputs
prefix : out std_logic_vector(9 downto 0);
entry_found : out std_logic;
search_completed : out std_logic);
end dictionary_block_4;
architecture Behavioral of dictionary_block_4 is
component bram_1024_0 is
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0)
);
end component;
component bram_1024_1 is
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0)
);
end component;
component bram_1024_2 is
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0)
);
end component;
component bram_1024_3 is
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0)
);
end component;
type state_type is (S_RST,S_GO,S_WAIT,S_SEARCH);
signal state : state_type;
signal rd_addr : std_logic_vector(11 downto 0);
signal addr : std_logic_vector(9 downto 0);
signal bram_out : std_logic_vector(19 downto 0);
signal full : std_logic;
signal rd_addr_delay : std_logic_vector(11 downto 0);
signal wr_entry_delay : std_logic_vector(19 downto 0);
signal r_wr_addr : std_logic_vector(9 downto 0);
signal r_wr_en : std_logic;
signal r_wr_entry : std_logic_vector(19 downto 0);
signal r_wr_addr_sum : std_logic_vector(11 downto 0);
signal r_start_search : std_logic;
signal r_search_entry : std_logic_vector(19 downto 0);
signal rd_addr_counter : std_logic_vector(11 downto 0);
begin
--Registered signals used to meet timing
process(clk,rst)
begin
if rst = '1' then
r_wr_en <= '0';
r_wr_addr <= (others => '0');
r_wr_entry <= (others => '0');
r_wr_addr_sum <= (others => '0');
r_start_search <= '0';
r_search_entry <= (others => '0');
elsif rising_edge(clk) then
r_wr_en <= wr_en;
r_wr_addr <= wr_addr;
r_wr_entry <= wr_entry;
r_wr_addr_sum <= std_logic_vector(unsigned(r_wr_addr)+to_unsigned(3,12));
r_search_entry <= search_entry;
r_start_search <= start_search;
end if;
end process;
GEN_BLOCK_0: if block_num = 0 generate
U_BRAM : bram_1024_0
port map(
clka => clk,
ena => '1',
wea(0) => r_wr_en,
addra => addr,
dina => wr_entry_delay,
douta => bram_out);
end generate GEN_BLOCK_0;
GEN_BLOCK_1 : if block_num = 1 generate
U_BRAM : bram_1024_1
port map(
clka => clk,
ena => '1',
wea(0) => r_wr_en,
addra => addr,
dina => wr_entry_delay,
douta => bram_out);
end generate GEN_BLOCK_1;
GEN_BLOCK_2: if block_num = 2 generate
U_BRAM : bram_1024_2
port map(
clka => clk,
ena => '1',
wea(0) => r_wr_en,
addra => addr,
dina => wr_entry_delay,
douta => bram_out);
end generate GEN_BLOCK_2;
GEN_BLOCK_3 : if block_num = 3 generate
U_BRAM : bram_1024_3
port map(
clka => clk,
ena => '1',
wea(0) => r_wr_en,
addra => addr,
dina => wr_entry_delay,
douta => bram_out);
end generate GEN_BLOCK_3;
with r_wr_en select addr <=
r_wr_addr when '1',
rd_addr(9 downto 0) when others;
process(clk,rst)
begin
if rising_edge(clk) then
if rst = '1' then
state <= S_RST;
rd_addr_counter <= (others => '0');
rd_addr <= (rd_addr'range => '0');
entry_found <= '0';
search_completed <= '0';
prefix <= (prefix'range => '0');
wr_entry_delay <= (wr_entry_delay'range => '0');
rd_addr_delay <= (rd_addr_delay'range => '0');
else
rd_addr_delay <= rd_addr;
wr_entry_delay <= r_wr_entry;
case state is
when S_RST =>
state <= S_GO;
--idle until its time to search
when S_GO =>
rd_addr_counter <= (others => '0');
rd_addr <= (rd_addr'range => '0');
entry_found <= '0';
search_completed <= '0';
prefix <= (prefix'range => '0');
if r_start_search = '1' then
state <= S_WAIT;
end if;
when S_WAIT =>
state <= S_SEARCH;
when S_SEARCH =>
rd_addr_counter <= std_logic_vector(unsigned(rd_addr_counter)+to_unsigned(1,12));
rd_addr <= std_logic_vector(unsigned(rd_addr)+to_unsigned(1,12));
--Did we find the entry?
if r_search_entry = bram_out then
state <= S_GO;
entry_found <= '1';
search_completed <= '1';
prefix <= rd_addr_delay(9 downto 0);
rd_addr <= (others => '0');
rd_addr_counter <= (others => '0');
end if;
--Did we go through the whole dictionary?
if r_start_search = '1' then
state <= S_SEARCH;
rd_addr <= (others => '0');
rd_addr_counter <= (others => '0');
elsif halt_search = '1' then
state <= S_GO;
rd_addr <= (others => '0');
rd_addr_counter <= (others => '0');
elsif rd_addr_counter = r_wr_addr_sum then
state <= S_GO;
rd_addr <= (others => '0');
search_completed <= '1';
rd_addr_counter <= (others => '0');
end if;
end case;
end if;
end if;
end process;
end Behavioral;
| unlicense | 769528bfe7303085d06a088966c1697c | 0.444992 | 3.982394 | false | false | false | false |
wsoltys/AtomFpga | src/AtomGodilVideo/src/mouse/resolution_mouse_informer.vhd | 1 | 8,042 | ------------------------------------------------------------------------
-- resolution_mouse_informer.vhd
------------------------------------------------------------------------
-- Author : Ulrich Zoltn
-- Copyright 2006 Digilent, Inc.
------------------------------------------------------------------------
-- Software version : Xilinx ISE 7.1.04i
-- WebPack
-- Device : 3s200ft256-4
------------------------------------------------------------------------
-- This file contains the logic that send the mouse_controller new
-- position of the mouse and new maximum values for the position
-- when resolution changes, so that the mouse will be centered on the
-- screen and the bounds for the new resolution are properly set.
------------------------------------------------------------------------
-- Behavioral description
------------------------------------------------------------------------
-- This module implements the logic that sets the position of the mouse
-- when the fpga is powered-up and when the resolution changes. It
-- also sets the bounds of the mouse corresponding to the currently used
-- resolution.
-- The mouse is centered for the currently selected resolution and the
-- bounds are set appropriately. This way the mouse will first appear
-- in the center in the screen at start-up and when resolution is
-- changed and cannot leave the screen.
-- The position (and similarly the bounds) is set by placing and number
-- representing the middle of the screen dimension on the value output
-- and activation the corresponding set signal (setx for horizontal
-- position, sety for vertical position, setmax_x for horizontal
-- maximum value, setmax_y for the veritcal maximum value).
------------------------------------------------------------------------
-- Port definitions
------------------------------------------------------------------------
-- clk - global clock signal
-- rst - reset signal
-- resolution - input pin, from resolution_switcher
-- - 0 for 640x480 selected resolution
-- - 1 for 800x600 selected resolution
-- switch - input pin, from resolution_switcher
-- - active for one clock period when resolution changes
-- value - output pin, 10 bits, to mouse_controller
-- - position on x or y, max value for x or y
-- - that is sent to the mouse_controller
-- setx - output pin, to mouse_controller
-- - active for one clock period when the horizontal
-- - position of the mouse cursor is valid on value output
-- sety - output pin, to mouse_controller
-- - active for one clock period when the vertical
-- - position of the mouse cursor is valid on value output
-- setmax_x - output pin, to mouse_controller
-- - active for one clock period when the horizontal
-- - maximum position of the mouse cursor is valid on
-- - value output
-- setmax_y - output pin, to mouse_controller
-- - active for one clock period when the vertical
-- - maximum position of the mouse cursor is valid on
-- - value output
------------------------------------------------------------------------
-- Revision History:
-- 09/18/2006(UlrichZ): created
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- simulation library
library UNISIM;
--use UNISIM.VComponents.all;
-- the resolution_mouse_informer entity declaration
-- read above for behavioral description and port definitions.
entity resolution_mouse_informer is
port (
clk : in std_logic;
rst : in std_logic;
resolution : in std_logic;
switch : in std_logic;
value : out std_logic_vector(9 downto 0);
setx : out std_logic;
sety : out std_logic;
setmax_x : out std_logic;
setmax_y : out std_logic
);
end resolution_mouse_informer;
architecture Behavioral of resolution_mouse_informer is
------------------------------------------------------------------------
-- CONSTANTS
------------------------------------------------------------------------
-- center horizontal position of the mouse for 640x480 and 256x192
constant POS_X_640: std_logic_vector(9 downto 0) := "0101000000"; -- 320
constant POS_X_800: std_logic_vector(9 downto 0) := "0010000000"; -- 128
-- center vertical position of the mouse for 640x480 and 800x600
constant POS_Y_640: std_logic_vector(9 downto 0) := "0011110000"; -- 240
constant POS_Y_800: std_logic_vector(9 downto 0) := "0001100000"; -- 96
-- maximum horizontal position of the mouse for 640x480 and 800x600
constant MAX_X_640: std_logic_vector(9 downto 0) := "1001111111"; -- 639
constant MAX_X_800: std_logic_vector(9 downto 0) := "0011111111"; -- 255
-- maximum vertical position of the mouse for 640x480 and 800x600
constant MAX_Y_640: std_logic_vector(9 downto 0) := "0111011111"; -- 479
constant MAX_Y_800: std_logic_vector(9 downto 0) := "0010111111"; -- 191
constant RES_640 : std_logic := '0';
constant RES_800 : std_logic := '1';
------------------------------------------------------------------------
-- SIGNALS
------------------------------------------------------------------------
type fsm_state is (sReset,sIdle,sSetX,sSetY,sSetMaxX,sSetMaxY);
-- signal that holds the current state of the FSM
signal state: fsm_state := sIdle;
begin
-- value receives the horizontal position of the mouse, the vertical
-- position, the maximum horizontal value and maximum vertical
-- value for the active resolution when in the apropriate state
value <= POS_X_640 when state = sSetX and resolution = RES_640 else
POS_X_800 when state = sSetX and resolution = RES_800 else
POS_Y_640 when state = sSetY and resolution = RES_640 else
POS_Y_800 when state = sSetY and resolution = RES_800 else
MAX_X_640 when state = sSetMaxX and resolution = RES_640 else
MAX_X_800 when state = sSetMaxX and resolution = RES_800 else
MAX_Y_640 when state = sSetMaxY and resolution = RES_640 else
MAX_Y_800 when state = sSetMaxY and resolution = RES_800 else
(others => '0');
-- when in state sSetX, set the horizontal value for the mouse
setx <= '1' when state = sSetX else '0';
-- when in state sSetY, set the vertical value for the mouse
sety <= '1' when state = sSetY else '0';
-- when in state sSetMaxX, set the horizontal max value for the mouse
setmax_x <= '1' when state = sSetMaxX else '0';
-- when in state sSetMaxX, set the vertical max value for the mouse
setmax_y <= '1' when state = sSetMaxY else '0';
-- when a resolution switch occurs (even to the same resolution)
-- leave the idle state
-- if just powered up or reset occures go to reset state and
-- from there set the position and bounds for the mouse
manage_fsm: process(clk,rst)
begin
if(rst = '1') then
state <= sReset;
elsif(rising_edge(clk)) then
case state is
-- when reset occurs (or power-up) set the position
-- and bounds for the mouse.
when sReset =>
state <= sSetX;
-- remain in idle while switch is not active.
when sIdle =>
if(switch = '1') then
state <= sSetX;
else
state <= sIdle;
end if;
when sSetX =>
state <= sSetY;
when sSetY =>
state <= sSetMaxX;
when sSetMaxX =>
state <= sSetMaxY;
when sSetMaxY =>
state <= sIdle;
when others =>
state <= sIdle;
end case;
end if;
end process;
end Behavioral; | apache-2.0 | d5bdfd0aabf582a3a469e11cf0eacf84 | 0.557946 | 4.691949 | false | false | false | false |
jairov4/accel-oil | impl/impl_test_pcie/hdl/system_sram_wrapper.vhd | 1 | 18,426 | -------------------------------------------------------------------------------
-- system_sram_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library xps_mch_emc_v3_01_a;
use xps_mch_emc_v3_01_a.all;
entity system_sram_wrapper is
port (
MCH_SPLB_Clk : in std_logic;
RdClk : in std_logic;
MCH_SPLB_Rst : in std_logic;
MCH0_Access_Control : in std_logic;
MCH0_Access_Data : in std_logic_vector(0 to 31);
MCH0_Access_Write : in std_logic;
MCH0_Access_Full : out std_logic;
MCH0_ReadData_Control : out std_logic;
MCH0_ReadData_Data : out std_logic_vector(0 to 31);
MCH0_ReadData_Read : in std_logic;
MCH0_ReadData_Exists : out std_logic;
MCH1_Access_Control : in std_logic;
MCH1_Access_Data : in std_logic_vector(0 to 31);
MCH1_Access_Write : in std_logic;
MCH1_Access_Full : out std_logic;
MCH1_ReadData_Control : out std_logic;
MCH1_ReadData_Data : out std_logic_vector(0 to 31);
MCH1_ReadData_Read : in std_logic;
MCH1_ReadData_Exists : out std_logic;
MCH2_Access_Control : in std_logic;
MCH2_Access_Data : in std_logic_vector(0 to 31);
MCH2_Access_Write : in std_logic;
MCH2_Access_Full : out std_logic;
MCH2_ReadData_Control : out std_logic;
MCH2_ReadData_Data : out std_logic_vector(0 to 31);
MCH2_ReadData_Read : in std_logic;
MCH2_ReadData_Exists : out std_logic;
MCH3_Access_Control : in std_logic;
MCH3_Access_Data : in std_logic_vector(0 to 31);
MCH3_Access_Write : in std_logic;
MCH3_Access_Full : out std_logic;
MCH3_ReadData_Control : out std_logic;
MCH3_ReadData_Data : out std_logic_vector(0 to 31);
MCH3_ReadData_Read : in std_logic;
MCH3_ReadData_Exists : out std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 2);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 7);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 63);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 63);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 5);
Sl_MWrErr : out std_logic_vector(0 to 5);
Sl_MRdErr : out std_logic_vector(0 to 5);
Sl_MIRQ : out std_logic_vector(0 to 5);
Mem_DQ_I : in std_logic_vector(0 to 31);
Mem_DQ_O : out std_logic_vector(0 to 31);
Mem_DQ_T : out std_logic_vector(0 to 31);
Mem_A : out std_logic_vector(0 to 31);
Mem_RPN : out std_logic;
Mem_CEN : out std_logic_vector(0 to 0);
Mem_OEN : out std_logic_vector(0 to 0);
Mem_WEN : out std_logic;
Mem_QWEN : out std_logic_vector(0 to 3);
Mem_BEN : out std_logic_vector(0 to 3);
Mem_CE : out std_logic_vector(0 to 0);
Mem_ADV_LDN : out std_logic;
Mem_LBON : out std_logic;
Mem_CKEN : out std_logic;
Mem_RNW : out std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of system_sram_wrapper : entity is "xps_mch_emc_v3_01_a";
end system_sram_wrapper;
architecture STRUCTURE of system_sram_wrapper is
component xps_mch_emc is
generic (
C_FAMILY : STRING;
C_NUM_BANKS_MEM : INTEGER;
C_NUM_CHANNELS : INTEGER;
C_PRIORITY_MODE : INTEGER;
C_INCLUDE_PLB_IPIF : INTEGER;
C_INCLUDE_WRBUF : INTEGER;
C_SPLB_MID_WIDTH : INTEGER;
C_SPLB_NUM_MASTERS : INTEGER;
C_SPLB_P2P : INTEGER;
C_SPLB_DWIDTH : INTEGER;
C_MCH_SPLB_AWIDTH : INTEGER;
C_SPLB_SMALLEST_MASTER : INTEGER;
C_MCH_NATIVE_DWIDTH : INTEGER;
C_MCH_SPLB_CLK_PERIOD_PS : INTEGER;
C_MEM0_BASEADDR : std_logic_vector;
C_MEM0_HIGHADDR : std_logic_vector;
C_MEM1_BASEADDR : std_logic_vector;
C_MEM1_HIGHADDR : std_logic_vector;
C_MEM2_BASEADDR : std_logic_vector;
C_MEM2_HIGHADDR : std_logic_vector;
C_MEM3_BASEADDR : std_logic_vector;
C_MEM3_HIGHADDR : std_logic_vector;
C_PAGEMODE_FLASH_0 : INTEGER;
C_PAGEMODE_FLASH_1 : INTEGER;
C_PAGEMODE_FLASH_2 : INTEGER;
C_PAGEMODE_FLASH_3 : INTEGER;
C_INCLUDE_NEGEDGE_IOREGS : INTEGER;
C_MEM0_WIDTH : INTEGER;
C_MEM1_WIDTH : INTEGER;
C_MEM2_WIDTH : INTEGER;
C_MEM3_WIDTH : INTEGER;
C_MAX_MEM_WIDTH : INTEGER;
C_INCLUDE_DATAWIDTH_MATCHING_0 : INTEGER;
C_INCLUDE_DATAWIDTH_MATCHING_1 : INTEGER;
C_INCLUDE_DATAWIDTH_MATCHING_2 : INTEGER;
C_INCLUDE_DATAWIDTH_MATCHING_3 : INTEGER;
C_SYNCH_MEM_0 : INTEGER;
C_SYNCH_PIPEDELAY_0 : INTEGER;
C_TCEDV_PS_MEM_0 : INTEGER;
C_TAVDV_PS_MEM_0 : INTEGER;
C_TPACC_PS_FLASH_0 : INTEGER;
C_THZCE_PS_MEM_0 : INTEGER;
C_THZOE_PS_MEM_0 : INTEGER;
C_TWC_PS_MEM_0 : INTEGER;
C_TWP_PS_MEM_0 : INTEGER;
C_TLZWE_PS_MEM_0 : INTEGER;
C_SYNCH_MEM_1 : INTEGER;
C_SYNCH_PIPEDELAY_1 : INTEGER;
C_TCEDV_PS_MEM_1 : INTEGER;
C_TAVDV_PS_MEM_1 : INTEGER;
C_TPACC_PS_FLASH_1 : INTEGER;
C_THZCE_PS_MEM_1 : INTEGER;
C_THZOE_PS_MEM_1 : INTEGER;
C_TWC_PS_MEM_1 : INTEGER;
C_TWP_PS_MEM_1 : INTEGER;
C_TLZWE_PS_MEM_1 : INTEGER;
C_SYNCH_MEM_2 : INTEGER;
C_SYNCH_PIPEDELAY_2 : INTEGER;
C_TCEDV_PS_MEM_2 : INTEGER;
C_TAVDV_PS_MEM_2 : INTEGER;
C_TPACC_PS_FLASH_2 : INTEGER;
C_THZCE_PS_MEM_2 : INTEGER;
C_THZOE_PS_MEM_2 : INTEGER;
C_TWC_PS_MEM_2 : INTEGER;
C_TWP_PS_MEM_2 : INTEGER;
C_TLZWE_PS_MEM_2 : INTEGER;
C_SYNCH_MEM_3 : INTEGER;
C_SYNCH_PIPEDELAY_3 : INTEGER;
C_TCEDV_PS_MEM_3 : INTEGER;
C_TAVDV_PS_MEM_3 : INTEGER;
C_TPACC_PS_FLASH_3 : INTEGER;
C_THZCE_PS_MEM_3 : INTEGER;
C_THZOE_PS_MEM_3 : INTEGER;
C_TWC_PS_MEM_3 : INTEGER;
C_TWP_PS_MEM_3 : INTEGER;
C_TLZWE_PS_MEM_3 : INTEGER;
C_MCH0_PROTOCOL : INTEGER;
C_MCH0_ACCESSBUF_DEPTH : INTEGER;
C_MCH0_RDDATABUF_DEPTH : INTEGER;
C_MCH1_PROTOCOL : INTEGER;
C_MCH1_ACCESSBUF_DEPTH : INTEGER;
C_MCH1_RDDATABUF_DEPTH : INTEGER;
C_MCH2_PROTOCOL : INTEGER;
C_MCH2_ACCESSBUF_DEPTH : INTEGER;
C_MCH2_RDDATABUF_DEPTH : INTEGER;
C_MCH3_PROTOCOL : INTEGER;
C_MCH3_ACCESSBUF_DEPTH : INTEGER;
C_MCH3_RDDATABUF_DEPTH : INTEGER;
C_XCL0_LINESIZE : INTEGER;
C_XCL0_WRITEXFER : INTEGER;
C_XCL1_LINESIZE : INTEGER;
C_XCL1_WRITEXFER : INTEGER;
C_XCL2_LINESIZE : INTEGER;
C_XCL2_WRITEXFER : INTEGER;
C_XCL3_LINESIZE : INTEGER;
C_XCL3_WRITEXFER : INTEGER
);
port (
MCH_SPLB_Clk : in std_logic;
RdClk : in std_logic;
MCH_SPLB_Rst : in std_logic;
MCH0_Access_Control : in std_logic;
MCH0_Access_Data : in std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1));
MCH0_Access_Write : in std_logic;
MCH0_Access_Full : out std_logic;
MCH0_ReadData_Control : out std_logic;
MCH0_ReadData_Data : out std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1));
MCH0_ReadData_Read : in std_logic;
MCH0_ReadData_Exists : out std_logic;
MCH1_Access_Control : in std_logic;
MCH1_Access_Data : in std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1));
MCH1_Access_Write : in std_logic;
MCH1_Access_Full : out std_logic;
MCH1_ReadData_Control : out std_logic;
MCH1_ReadData_Data : out std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1));
MCH1_ReadData_Read : in std_logic;
MCH1_ReadData_Exists : out std_logic;
MCH2_Access_Control : in std_logic;
MCH2_Access_Data : in std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1));
MCH2_Access_Write : in std_logic;
MCH2_Access_Full : out std_logic;
MCH2_ReadData_Control : out std_logic;
MCH2_ReadData_Data : out std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1));
MCH2_ReadData_Read : in std_logic;
MCH2_ReadData_Exists : out std_logic;
MCH3_Access_Control : in std_logic;
MCH3_Access_Data : in std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1));
MCH3_Access_Write : in std_logic;
MCH3_Access_Full : out std_logic;
MCH3_ReadData_Control : out std_logic;
MCH3_ReadData_Data : out std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1));
MCH3_ReadData_Read : in std_logic;
MCH3_ReadData_Exists : out std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1));
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1));
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1));
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1));
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Mem_DQ_I : in std_logic_vector(0 to (C_MAX_MEM_WIDTH-1));
Mem_DQ_O : out std_logic_vector(0 to (C_MAX_MEM_WIDTH-1));
Mem_DQ_T : out std_logic_vector(0 to (C_MAX_MEM_WIDTH-1));
Mem_A : out std_logic_vector(0 to (C_MCH_SPLB_AWIDTH-1));
Mem_RPN : out std_logic;
Mem_CEN : out std_logic_vector(0 to (C_NUM_BANKS_MEM-1));
Mem_OEN : out std_logic_vector(0 to (C_NUM_BANKS_MEM-1));
Mem_WEN : out std_logic;
Mem_QWEN : out std_logic_vector(0 to ((C_MAX_MEM_WIDTH/8)-1));
Mem_BEN : out std_logic_vector(0 to ((C_MAX_MEM_WIDTH/8)-1));
Mem_CE : out std_logic_vector(0 to (C_NUM_BANKS_MEM-1));
Mem_ADV_LDN : out std_logic;
Mem_LBON : out std_logic;
Mem_CKEN : out std_logic;
Mem_RNW : out std_logic
);
end component;
begin
SRAM : xps_mch_emc
generic map (
C_FAMILY => "virtex5",
C_NUM_BANKS_MEM => 1,
C_NUM_CHANNELS => 0,
C_PRIORITY_MODE => 0,
C_INCLUDE_PLB_IPIF => 1,
C_INCLUDE_WRBUF => 1,
C_SPLB_MID_WIDTH => 3,
C_SPLB_NUM_MASTERS => 6,
C_SPLB_P2P => 0,
C_SPLB_DWIDTH => 64,
C_MCH_SPLB_AWIDTH => 32,
C_SPLB_SMALLEST_MASTER => 32,
C_MCH_NATIVE_DWIDTH => 32,
C_MCH_SPLB_CLK_PERIOD_PS => 8000,
C_MEM0_BASEADDR => X"9af00000",
C_MEM0_HIGHADDR => X"9affffff",
C_MEM1_BASEADDR => X"ffffffff",
C_MEM1_HIGHADDR => X"00000000",
C_MEM2_BASEADDR => X"ffffffff",
C_MEM2_HIGHADDR => X"00000000",
C_MEM3_BASEADDR => X"ffffffff",
C_MEM3_HIGHADDR => X"00000000",
C_PAGEMODE_FLASH_0 => 0,
C_PAGEMODE_FLASH_1 => 0,
C_PAGEMODE_FLASH_2 => 0,
C_PAGEMODE_FLASH_3 => 0,
C_INCLUDE_NEGEDGE_IOREGS => 0,
C_MEM0_WIDTH => 32,
C_MEM1_WIDTH => 32,
C_MEM2_WIDTH => 32,
C_MEM3_WIDTH => 32,
C_MAX_MEM_WIDTH => 32,
C_INCLUDE_DATAWIDTH_MATCHING_0 => 0,
C_INCLUDE_DATAWIDTH_MATCHING_1 => 0,
C_INCLUDE_DATAWIDTH_MATCHING_2 => 0,
C_INCLUDE_DATAWIDTH_MATCHING_3 => 0,
C_SYNCH_MEM_0 => 1,
C_SYNCH_PIPEDELAY_0 => 2,
C_TCEDV_PS_MEM_0 => 0,
C_TAVDV_PS_MEM_0 => 0,
C_TPACC_PS_FLASH_0 => 25000,
C_THZCE_PS_MEM_0 => 0,
C_THZOE_PS_MEM_0 => 0,
C_TWC_PS_MEM_0 => 0,
C_TWP_PS_MEM_0 => 0,
C_TLZWE_PS_MEM_0 => 0,
C_SYNCH_MEM_1 => 0,
C_SYNCH_PIPEDELAY_1 => 2,
C_TCEDV_PS_MEM_1 => 15000,
C_TAVDV_PS_MEM_1 => 15000,
C_TPACC_PS_FLASH_1 => 25000,
C_THZCE_PS_MEM_1 => 7000,
C_THZOE_PS_MEM_1 => 7000,
C_TWC_PS_MEM_1 => 15000,
C_TWP_PS_MEM_1 => 12000,
C_TLZWE_PS_MEM_1 => 0,
C_SYNCH_MEM_2 => 0,
C_SYNCH_PIPEDELAY_2 => 2,
C_TCEDV_PS_MEM_2 => 15000,
C_TAVDV_PS_MEM_2 => 15000,
C_TPACC_PS_FLASH_2 => 25000,
C_THZCE_PS_MEM_2 => 7000,
C_THZOE_PS_MEM_2 => 7000,
C_TWC_PS_MEM_2 => 15000,
C_TWP_PS_MEM_2 => 12000,
C_TLZWE_PS_MEM_2 => 0,
C_SYNCH_MEM_3 => 0,
C_SYNCH_PIPEDELAY_3 => 2,
C_TCEDV_PS_MEM_3 => 15000,
C_TAVDV_PS_MEM_3 => 15000,
C_TPACC_PS_FLASH_3 => 25000,
C_THZCE_PS_MEM_3 => 7000,
C_THZOE_PS_MEM_3 => 7000,
C_TWC_PS_MEM_3 => 15000,
C_TWP_PS_MEM_3 => 12000,
C_TLZWE_PS_MEM_3 => 0,
C_MCH0_PROTOCOL => 0,
C_MCH0_ACCESSBUF_DEPTH => 16,
C_MCH0_RDDATABUF_DEPTH => 16,
C_MCH1_PROTOCOL => 0,
C_MCH1_ACCESSBUF_DEPTH => 16,
C_MCH1_RDDATABUF_DEPTH => 16,
C_MCH2_PROTOCOL => 0,
C_MCH2_ACCESSBUF_DEPTH => 16,
C_MCH2_RDDATABUF_DEPTH => 16,
C_MCH3_PROTOCOL => 0,
C_MCH3_ACCESSBUF_DEPTH => 16,
C_MCH3_RDDATABUF_DEPTH => 16,
C_XCL0_LINESIZE => 4,
C_XCL0_WRITEXFER => 1,
C_XCL1_LINESIZE => 4,
C_XCL1_WRITEXFER => 1,
C_XCL2_LINESIZE => 4,
C_XCL2_WRITEXFER => 1,
C_XCL3_LINESIZE => 4,
C_XCL3_WRITEXFER => 1
)
port map (
MCH_SPLB_Clk => MCH_SPLB_Clk,
RdClk => RdClk,
MCH_SPLB_Rst => MCH_SPLB_Rst,
MCH0_Access_Control => MCH0_Access_Control,
MCH0_Access_Data => MCH0_Access_Data,
MCH0_Access_Write => MCH0_Access_Write,
MCH0_Access_Full => MCH0_Access_Full,
MCH0_ReadData_Control => MCH0_ReadData_Control,
MCH0_ReadData_Data => MCH0_ReadData_Data,
MCH0_ReadData_Read => MCH0_ReadData_Read,
MCH0_ReadData_Exists => MCH0_ReadData_Exists,
MCH1_Access_Control => MCH1_Access_Control,
MCH1_Access_Data => MCH1_Access_Data,
MCH1_Access_Write => MCH1_Access_Write,
MCH1_Access_Full => MCH1_Access_Full,
MCH1_ReadData_Control => MCH1_ReadData_Control,
MCH1_ReadData_Data => MCH1_ReadData_Data,
MCH1_ReadData_Read => MCH1_ReadData_Read,
MCH1_ReadData_Exists => MCH1_ReadData_Exists,
MCH2_Access_Control => MCH2_Access_Control,
MCH2_Access_Data => MCH2_Access_Data,
MCH2_Access_Write => MCH2_Access_Write,
MCH2_Access_Full => MCH2_Access_Full,
MCH2_ReadData_Control => MCH2_ReadData_Control,
MCH2_ReadData_Data => MCH2_ReadData_Data,
MCH2_ReadData_Read => MCH2_ReadData_Read,
MCH2_ReadData_Exists => MCH2_ReadData_Exists,
MCH3_Access_Control => MCH3_Access_Control,
MCH3_Access_Data => MCH3_Access_Data,
MCH3_Access_Write => MCH3_Access_Write,
MCH3_Access_Full => MCH3_Access_Full,
MCH3_ReadData_Control => MCH3_ReadData_Control,
MCH3_ReadData_Data => MCH3_ReadData_Data,
MCH3_ReadData_Read => MCH3_ReadData_Read,
MCH3_ReadData_Exists => MCH3_ReadData_Exists,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Mem_DQ_I => Mem_DQ_I,
Mem_DQ_O => Mem_DQ_O,
Mem_DQ_T => Mem_DQ_T,
Mem_A => Mem_A,
Mem_RPN => Mem_RPN,
Mem_CEN => Mem_CEN,
Mem_OEN => Mem_OEN,
Mem_WEN => Mem_WEN,
Mem_QWEN => Mem_QWEN,
Mem_BEN => Mem_BEN,
Mem_CE => Mem_CE,
Mem_ADV_LDN => Mem_ADV_LDN,
Mem_LBON => Mem_LBON,
Mem_CKEN => Mem_CKEN,
Mem_RNW => Mem_RNW
);
end architecture STRUCTURE;
| lgpl-3.0 | d60d8968f2b82c80f6919e61fb510554 | 0.595897 | 2.981553 | false | false | false | false |
TWW12/lzw | ip_repo/axi_compression_1.0/src/bram_1024_3/synth/bram_1024_3.vhd | 4 | 14,457 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY bram_1024_3 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0)
);
END bram_1024_3;
ARCHITECTURE bram_1024_3_arch OF bram_1024_3 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bram_1024_3_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF bram_1024_3_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF bram_1024_3_arch : ARCHITECTURE IS "bram_1024_3,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF bram_1024_3_arch: ARCHITECTURE IS "bram_1024_3,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=bram_1024_3.mi" &
"f,C_INIT_FILE=bram_1024_3.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=20,C_READ_WIDTH_A=20,C_WRITE_DEPTH_A=1024,C_READ_DEPTH_A=1024,C_ADDRA_WIDTH=10,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=20,C_READ_WIDTH_B=20,C_WRITE_DE" &
"PTH_B=1024,C_READ_DEPTH_B=1024,C_ADDRB_WIDTH=10,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE" &
"_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.74095 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "bram_1024_3.mif",
C_INIT_FILE => "bram_1024_3.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 20,
C_READ_WIDTH_A => 20,
C_WRITE_DEPTH_A => 1024,
C_READ_DEPTH_A => 1024,
C_ADDRA_WIDTH => 10,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 20,
C_READ_WIDTH_B => 20,
C_WRITE_DEPTH_B => 1024,
C_READ_DEPTH_B => 1024,
C_ADDRB_WIDTH => 10,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.74095 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END bram_1024_3_arch;
| unlicense | 057a6260b6309ee30e2a96f08afd09a6 | 0.625372 | 3.002492 | false | false | false | false |
jairov4/accel-oil | impl/impl_test_pcie/hdl/system_dlmb_cntlr_wrapper.vhd | 1 | 18,461 | -------------------------------------------------------------------------------
-- system_dlmb_cntlr_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library lmb_bram_if_cntlr_v3_10_c;
use lmb_bram_if_cntlr_v3_10_c.all;
entity system_dlmb_cntlr_wrapper is
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
LMB_ABus : in std_logic_vector(0 to 31);
LMB_WriteDBus : in std_logic_vector(0 to 31);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to 3);
Sl_DBus : out std_logic_vector(0 to 31);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
LMB1_ABus : in std_logic_vector(0 to 31);
LMB1_WriteDBus : in std_logic_vector(0 to 31);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to 3);
Sl1_DBus : out std_logic_vector(0 to 31);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
LMB2_ABus : in std_logic_vector(0 to 31);
LMB2_WriteDBus : in std_logic_vector(0 to 31);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to 3);
Sl2_DBus : out std_logic_vector(0 to 31);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
LMB3_ABus : in std_logic_vector(0 to 31);
LMB3_WriteDBus : in std_logic_vector(0 to 31);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to 3);
Sl3_DBus : out std_logic_vector(0 to 31);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to 3);
BRAM_Addr_A : out std_logic_vector(0 to 31);
BRAM_Din_A : in std_logic_vector(0 to 31);
BRAM_Dout_A : out std_logic_vector(0 to 31);
Interrupt : out std_logic;
UE : out std_logic;
CE : out std_logic;
SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_PAValid : in std_logic;
SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to 0);
SPLB_CTRL_PLB_RNW : in std_logic;
SPLB_CTRL_PLB_BE : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2);
SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to 31);
SPLB_CTRL_Sl_addrAck : out std_logic;
SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1);
SPLB_CTRL_Sl_wait : out std_logic;
SPLB_CTRL_Sl_rearbitrate : out std_logic;
SPLB_CTRL_Sl_wrDAck : out std_logic;
SPLB_CTRL_Sl_wrComp : out std_logic;
SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to 31);
SPLB_CTRL_Sl_rdDAck : out std_logic;
SPLB_CTRL_Sl_rdComp : out std_logic;
SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to 0);
SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_SAValid : in std_logic;
SPLB_CTRL_PLB_rdPrim : in std_logic;
SPLB_CTRL_PLB_wrPrim : in std_logic;
SPLB_CTRL_PLB_abort : in std_logic;
SPLB_CTRL_PLB_busLock : in std_logic;
SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_lockErr : in std_logic;
SPLB_CTRL_PLB_wrBurst : in std_logic;
SPLB_CTRL_PLB_rdBurst : in std_logic;
SPLB_CTRL_PLB_wrPendReq : in std_logic;
SPLB_CTRL_PLB_rdPendReq : in std_logic;
SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB_CTRL_Sl_wrBTerm : out std_logic;
SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB_CTRL_Sl_rdBTerm : out std_logic;
SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to 0);
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of system_dlmb_cntlr_wrapper : entity is "lmb_bram_if_cntlr_v3_10_c";
end system_dlmb_cntlr_wrapper;
architecture STRUCTURE of system_dlmb_cntlr_wrapper is
component lmb_bram_if_cntlr is
generic (
C_BASEADDR : std_logic_vector(0 to 31);
C_HIGHADDR : std_logic_vector(0 to 31);
C_FAMILY : string;
C_MASK : std_logic_vector(0 to 31);
C_MASK1 : std_logic_vector(0 to 31);
C_MASK2 : std_logic_vector(0 to 31);
C_MASK3 : std_logic_vector(0 to 31);
C_LMB_AWIDTH : integer;
C_LMB_DWIDTH : integer;
C_ECC : integer;
C_INTERCONNECT : integer;
C_FAULT_INJECT : integer;
C_CE_FAILING_REGISTERS : integer;
C_UE_FAILING_REGISTERS : integer;
C_ECC_STATUS_REGISTERS : integer;
C_ECC_ONOFF_REGISTER : integer;
C_ECC_ONOFF_RESET_VALUE : integer;
C_CE_COUNTER_WIDTH : integer;
C_WRITE_ACCESS : integer;
C_NUM_LMB : integer;
C_SPLB_CTRL_BASEADDR : std_logic_vector;
C_SPLB_CTRL_HIGHADDR : std_logic_vector;
C_SPLB_CTRL_AWIDTH : INTEGER;
C_SPLB_CTRL_DWIDTH : INTEGER;
C_SPLB_CTRL_P2P : INTEGER;
C_SPLB_CTRL_MID_WIDTH : INTEGER;
C_SPLB_CTRL_NUM_MASTERS : INTEGER;
C_SPLB_CTRL_SUPPORT_BURSTS : INTEGER;
C_SPLB_CTRL_NATIVE_DWIDTH : INTEGER;
C_S_AXI_CTRL_BASEADDR : std_logic_vector(31 downto 0);
C_S_AXI_CTRL_HIGHADDR : std_logic_vector(31 downto 0);
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER
);
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
LMB_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
LMB1_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB1_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl1_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
LMB2_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB2_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl2_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
LMB3_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB3_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl3_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to ((C_LMB_DWIDTH+8*C_ECC)/8)-1);
BRAM_Addr_A : out std_logic_vector(0 to C_LMB_AWIDTH-1);
BRAM_Din_A : in std_logic_vector(0 to C_LMB_DWIDTH-1+8*C_ECC);
BRAM_Dout_A : out std_logic_vector(0 to C_LMB_DWIDTH-1+8*C_ECC);
Interrupt : out std_logic;
UE : out std_logic;
CE : out std_logic;
SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_PAValid : in std_logic;
SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to (C_SPLB_CTRL_MID_WIDTH-1));
SPLB_CTRL_PLB_RNW : in std_logic;
SPLB_CTRL_PLB_BE : in std_logic_vector(0 to ((C_SPLB_CTRL_DWIDTH/8)-1));
SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2);
SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_CTRL_DWIDTH-1));
SPLB_CTRL_Sl_addrAck : out std_logic;
SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1);
SPLB_CTRL_Sl_wait : out std_logic;
SPLB_CTRL_Sl_rearbitrate : out std_logic;
SPLB_CTRL_Sl_wrDAck : out std_logic;
SPLB_CTRL_Sl_wrComp : out std_logic;
SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_CTRL_DWIDTH-1));
SPLB_CTRL_Sl_rdDAck : out std_logic;
SPLB_CTRL_Sl_rdComp : out std_logic;
SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_SAValid : in std_logic;
SPLB_CTRL_PLB_rdPrim : in std_logic;
SPLB_CTRL_PLB_wrPrim : in std_logic;
SPLB_CTRL_PLB_abort : in std_logic;
SPLB_CTRL_PLB_busLock : in std_logic;
SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_lockErr : in std_logic;
SPLB_CTRL_PLB_wrBurst : in std_logic;
SPLB_CTRL_PLB_rdBurst : in std_logic;
SPLB_CTRL_PLB_wrPendReq : in std_logic;
SPLB_CTRL_PLB_rdPendReq : in std_logic;
SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB_CTRL_Sl_wrBTerm : out std_logic;
SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB_CTRL_Sl_rdBTerm : out std_logic;
SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector((C_S_AXI_CTRL_ADDR_WIDTH-1) downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH-1) downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector(((C_S_AXI_CTRL_DATA_WIDTH/8)-1) downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector((C_S_AXI_CTRL_ADDR_WIDTH-1) downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH-1) downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic
);
end component;
begin
dlmb_cntlr : lmb_bram_if_cntlr
generic map (
C_BASEADDR => X"00000000",
C_HIGHADDR => X"00000fff",
C_FAMILY => "virtex5",
C_MASK => X"80000000",
C_MASK1 => X"00800000",
C_MASK2 => X"00800000",
C_MASK3 => X"00800000",
C_LMB_AWIDTH => 32,
C_LMB_DWIDTH => 32,
C_ECC => 0,
C_INTERCONNECT => 0,
C_FAULT_INJECT => 0,
C_CE_FAILING_REGISTERS => 0,
C_UE_FAILING_REGISTERS => 0,
C_ECC_STATUS_REGISTERS => 0,
C_ECC_ONOFF_REGISTER => 0,
C_ECC_ONOFF_RESET_VALUE => 1,
C_CE_COUNTER_WIDTH => 0,
C_WRITE_ACCESS => 2,
C_NUM_LMB => 1,
C_SPLB_CTRL_BASEADDR => X"FFFFFFFF",
C_SPLB_CTRL_HIGHADDR => X"00000000",
C_SPLB_CTRL_AWIDTH => 32,
C_SPLB_CTRL_DWIDTH => 32,
C_SPLB_CTRL_P2P => 0,
C_SPLB_CTRL_MID_WIDTH => 1,
C_SPLB_CTRL_NUM_MASTERS => 1,
C_SPLB_CTRL_SUPPORT_BURSTS => 0,
C_SPLB_CTRL_NATIVE_DWIDTH => 32,
C_S_AXI_CTRL_BASEADDR => X"FFFFFFFF",
C_S_AXI_CTRL_HIGHADDR => X"00000000",
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32
)
port map (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
LMB_ABus => LMB_ABus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_BE => LMB_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
Sl_Wait => Sl_Wait,
Sl_UE => Sl_UE,
Sl_CE => Sl_CE,
LMB1_ABus => LMB1_ABus,
LMB1_WriteDBus => LMB1_WriteDBus,
LMB1_AddrStrobe => LMB1_AddrStrobe,
LMB1_ReadStrobe => LMB1_ReadStrobe,
LMB1_WriteStrobe => LMB1_WriteStrobe,
LMB1_BE => LMB1_BE,
Sl1_DBus => Sl1_DBus,
Sl1_Ready => Sl1_Ready,
Sl1_Wait => Sl1_Wait,
Sl1_UE => Sl1_UE,
Sl1_CE => Sl1_CE,
LMB2_ABus => LMB2_ABus,
LMB2_WriteDBus => LMB2_WriteDBus,
LMB2_AddrStrobe => LMB2_AddrStrobe,
LMB2_ReadStrobe => LMB2_ReadStrobe,
LMB2_WriteStrobe => LMB2_WriteStrobe,
LMB2_BE => LMB2_BE,
Sl2_DBus => Sl2_DBus,
Sl2_Ready => Sl2_Ready,
Sl2_Wait => Sl2_Wait,
Sl2_UE => Sl2_UE,
Sl2_CE => Sl2_CE,
LMB3_ABus => LMB3_ABus,
LMB3_WriteDBus => LMB3_WriteDBus,
LMB3_AddrStrobe => LMB3_AddrStrobe,
LMB3_ReadStrobe => LMB3_ReadStrobe,
LMB3_WriteStrobe => LMB3_WriteStrobe,
LMB3_BE => LMB3_BE,
Sl3_DBus => Sl3_DBus,
Sl3_Ready => Sl3_Ready,
Sl3_Wait => Sl3_Wait,
Sl3_UE => Sl3_UE,
Sl3_CE => Sl3_CE,
BRAM_Rst_A => BRAM_Rst_A,
BRAM_Clk_A => BRAM_Clk_A,
BRAM_EN_A => BRAM_EN_A,
BRAM_WEN_A => BRAM_WEN_A,
BRAM_Addr_A => BRAM_Addr_A,
BRAM_Din_A => BRAM_Din_A,
BRAM_Dout_A => BRAM_Dout_A,
Interrupt => Interrupt,
UE => UE,
CE => CE,
SPLB_CTRL_PLB_ABus => SPLB_CTRL_PLB_ABus,
SPLB_CTRL_PLB_PAValid => SPLB_CTRL_PLB_PAValid,
SPLB_CTRL_PLB_masterID => SPLB_CTRL_PLB_masterID,
SPLB_CTRL_PLB_RNW => SPLB_CTRL_PLB_RNW,
SPLB_CTRL_PLB_BE => SPLB_CTRL_PLB_BE,
SPLB_CTRL_PLB_size => SPLB_CTRL_PLB_size,
SPLB_CTRL_PLB_type => SPLB_CTRL_PLB_type,
SPLB_CTRL_PLB_wrDBus => SPLB_CTRL_PLB_wrDBus,
SPLB_CTRL_Sl_addrAck => SPLB_CTRL_Sl_addrAck,
SPLB_CTRL_Sl_SSize => SPLB_CTRL_Sl_SSize,
SPLB_CTRL_Sl_wait => SPLB_CTRL_Sl_wait,
SPLB_CTRL_Sl_rearbitrate => SPLB_CTRL_Sl_rearbitrate,
SPLB_CTRL_Sl_wrDAck => SPLB_CTRL_Sl_wrDAck,
SPLB_CTRL_Sl_wrComp => SPLB_CTRL_Sl_wrComp,
SPLB_CTRL_Sl_rdDBus => SPLB_CTRL_Sl_rdDBus,
SPLB_CTRL_Sl_rdDAck => SPLB_CTRL_Sl_rdDAck,
SPLB_CTRL_Sl_rdComp => SPLB_CTRL_Sl_rdComp,
SPLB_CTRL_Sl_MBusy => SPLB_CTRL_Sl_MBusy,
SPLB_CTRL_Sl_MWrErr => SPLB_CTRL_Sl_MWrErr,
SPLB_CTRL_Sl_MRdErr => SPLB_CTRL_Sl_MRdErr,
SPLB_CTRL_PLB_UABus => SPLB_CTRL_PLB_UABus,
SPLB_CTRL_PLB_SAValid => SPLB_CTRL_PLB_SAValid,
SPLB_CTRL_PLB_rdPrim => SPLB_CTRL_PLB_rdPrim,
SPLB_CTRL_PLB_wrPrim => SPLB_CTRL_PLB_wrPrim,
SPLB_CTRL_PLB_abort => SPLB_CTRL_PLB_abort,
SPLB_CTRL_PLB_busLock => SPLB_CTRL_PLB_busLock,
SPLB_CTRL_PLB_MSize => SPLB_CTRL_PLB_MSize,
SPLB_CTRL_PLB_lockErr => SPLB_CTRL_PLB_lockErr,
SPLB_CTRL_PLB_wrBurst => SPLB_CTRL_PLB_wrBurst,
SPLB_CTRL_PLB_rdBurst => SPLB_CTRL_PLB_rdBurst,
SPLB_CTRL_PLB_wrPendReq => SPLB_CTRL_PLB_wrPendReq,
SPLB_CTRL_PLB_rdPendReq => SPLB_CTRL_PLB_rdPendReq,
SPLB_CTRL_PLB_wrPendPri => SPLB_CTRL_PLB_wrPendPri,
SPLB_CTRL_PLB_rdPendPri => SPLB_CTRL_PLB_rdPendPri,
SPLB_CTRL_PLB_reqPri => SPLB_CTRL_PLB_reqPri,
SPLB_CTRL_PLB_TAttribute => SPLB_CTRL_PLB_TAttribute,
SPLB_CTRL_Sl_wrBTerm => SPLB_CTRL_Sl_wrBTerm,
SPLB_CTRL_Sl_rdWdAddr => SPLB_CTRL_Sl_rdWdAddr,
SPLB_CTRL_Sl_rdBTerm => SPLB_CTRL_Sl_rdBTerm,
SPLB_CTRL_Sl_MIRQ => SPLB_CTRL_Sl_MIRQ,
S_AXI_CTRL_ACLK => S_AXI_CTRL_ACLK,
S_AXI_CTRL_ARESETN => S_AXI_CTRL_ARESETN,
S_AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR,
S_AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID,
S_AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY,
S_AXI_CTRL_WDATA => S_AXI_CTRL_WDATA,
S_AXI_CTRL_WSTRB => S_AXI_CTRL_WSTRB,
S_AXI_CTRL_WVALID => S_AXI_CTRL_WVALID,
S_AXI_CTRL_WREADY => S_AXI_CTRL_WREADY,
S_AXI_CTRL_BRESP => S_AXI_CTRL_BRESP,
S_AXI_CTRL_BVALID => S_AXI_CTRL_BVALID,
S_AXI_CTRL_BREADY => S_AXI_CTRL_BREADY,
S_AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR,
S_AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID,
S_AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY,
S_AXI_CTRL_RDATA => S_AXI_CTRL_RDATA,
S_AXI_CTRL_RRESP => S_AXI_CTRL_RRESP,
S_AXI_CTRL_RVALID => S_AXI_CTRL_RVALID,
S_AXI_CTRL_RREADY => S_AXI_CTRL_RREADY
);
end architecture STRUCTURE;
| lgpl-3.0 | e03659039692c7a434bc4184f5e5fc9b | 0.615785 | 2.932645 | false | false | false | false |
jairov4/accel-oil | impl/impl_test_pcie/hdl/system_ac0_plb_wrapper.vhd | 1 | 14,691 | -------------------------------------------------------------------------------
-- system_ac0_plb_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plb_v46_v1_05_a;
use plb_v46_v1_05_a.all;
entity system_ac0_plb_wrapper is
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to 0);
MPLB_Rst : out std_logic_vector(0 to 14);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to 31);
DCR_ABus : in std_logic_vector(0 to 9);
DCR_DBus : in std_logic_vector(0 to 31);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to 479);
M_UABus : in std_logic_vector(0 to 479);
M_BE : in std_logic_vector(0 to 119);
M_RNW : in std_logic_vector(0 to 14);
M_abort : in std_logic_vector(0 to 14);
M_busLock : in std_logic_vector(0 to 14);
M_TAttribute : in std_logic_vector(0 to 239);
M_lockErr : in std_logic_vector(0 to 14);
M_MSize : in std_logic_vector(0 to 29);
M_priority : in std_logic_vector(0 to 29);
M_rdBurst : in std_logic_vector(0 to 14);
M_request : in std_logic_vector(0 to 14);
M_size : in std_logic_vector(0 to 59);
M_type : in std_logic_vector(0 to 44);
M_wrBurst : in std_logic_vector(0 to 14);
M_wrDBus : in std_logic_vector(0 to 959);
Sl_addrAck : in std_logic_vector(0 to 0);
Sl_MRdErr : in std_logic_vector(0 to 14);
Sl_MWrErr : in std_logic_vector(0 to 14);
Sl_MBusy : in std_logic_vector(0 to 14);
Sl_rdBTerm : in std_logic_vector(0 to 0);
Sl_rdComp : in std_logic_vector(0 to 0);
Sl_rdDAck : in std_logic_vector(0 to 0);
Sl_rdDBus : in std_logic_vector(0 to 63);
Sl_rdWdAddr : in std_logic_vector(0 to 3);
Sl_rearbitrate : in std_logic_vector(0 to 0);
Sl_SSize : in std_logic_vector(0 to 1);
Sl_wait : in std_logic_vector(0 to 0);
Sl_wrBTerm : in std_logic_vector(0 to 0);
Sl_wrComp : in std_logic_vector(0 to 0);
Sl_wrDAck : in std_logic_vector(0 to 0);
Sl_MIRQ : in std_logic_vector(0 to 14);
PLB_MIRQ : out std_logic_vector(0 to 14);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to 7);
PLB_MAddrAck : out std_logic_vector(0 to 14);
PLB_MTimeout : out std_logic_vector(0 to 14);
PLB_MBusy : out std_logic_vector(0 to 14);
PLB_MRdErr : out std_logic_vector(0 to 14);
PLB_MWrErr : out std_logic_vector(0 to 14);
PLB_MRdBTerm : out std_logic_vector(0 to 14);
PLB_MRdDAck : out std_logic_vector(0 to 14);
PLB_MRdDBus : out std_logic_vector(0 to 959);
PLB_MRdWdAddr : out std_logic_vector(0 to 59);
PLB_MRearbitrate : out std_logic_vector(0 to 14);
PLB_MWrBTerm : out std_logic_vector(0 to 14);
PLB_MWrDAck : out std_logic_vector(0 to 14);
PLB_MSSize : out std_logic_vector(0 to 29);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to 3);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to 0);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to 63);
PLB_wrPrim : out std_logic_vector(0 to 0);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to 14);
PLB_SMWrErr : out std_logic_vector(0 to 14);
PLB_SMBusy : out std_logic_vector(0 to 14);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to 63);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
Bus_Error_Det : out std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of system_ac0_plb_wrapper : entity is "plb_v46_v1_05_a";
end system_ac0_plb_wrapper;
architecture STRUCTURE of system_ac0_plb_wrapper is
component plb_v46 is
generic (
C_PLBV46_NUM_MASTERS : integer;
C_PLBV46_NUM_SLAVES : integer;
C_PLBV46_MID_WIDTH : integer;
C_PLBV46_AWIDTH : integer;
C_PLBV46_DWIDTH : integer;
C_DCR_INTFCE : integer;
C_BASEADDR : std_logic_vector;
C_HIGHADDR : std_logic_vector;
C_DCR_AWIDTH : integer;
C_DCR_DWIDTH : integer;
C_EXT_RESET_HIGH : integer;
C_IRQ_ACTIVE : std_logic;
C_ADDR_PIPELINING_TYPE : integer;
C_FAMILY : string;
C_P2P : integer;
C_ARB_TYPE : integer
);
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
MPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_ABus : in std_logic_vector(0 to C_DCR_AWIDTH-1);
DCR_DBus : in std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*32)-1);
M_UABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*32)-1);
M_BE : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*(C_PLBV46_DWIDTH/8))-1);
M_RNW : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_abort : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_busLock : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_TAttribute : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*16)-1);
M_lockErr : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_MSize : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
M_priority : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
M_rdBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_request : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_size : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*4)-1);
M_type : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*3)-1);
M_wrBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_wrDBus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1);
Sl_addrAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_MRdErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1);
Sl_MWrErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1);
Sl_MBusy : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS - 1 );
Sl_rdBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdDBus : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_DWIDTH-1);
Sl_rdWdAddr : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*4-1);
Sl_rearbitrate : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_SSize : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*2-1);
Sl_wait : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_MIRQ : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS-1);
PLB_MIRQ : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to (C_PLBV46_DWIDTH/8)-1);
PLB_MAddrAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MTimeout : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdDBus : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1);
PLB_MRdWdAddr : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*4)-1);
PLB_MRearbitrate : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MSSize : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to C_PLBV46_MID_WIDTH-1);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1);
PLB_wrPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SMWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SMBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
Bus_Error_Det : out std_logic
);
end component;
begin
ac0_plb : plb_v46
generic map (
C_PLBV46_NUM_MASTERS => 15,
C_PLBV46_NUM_SLAVES => 1,
C_PLBV46_MID_WIDTH => 4,
C_PLBV46_AWIDTH => 32,
C_PLBV46_DWIDTH => 64,
C_DCR_INTFCE => 0,
C_BASEADDR => B"1111111111",
C_HIGHADDR => B"0000000000",
C_DCR_AWIDTH => 10,
C_DCR_DWIDTH => 32,
C_EXT_RESET_HIGH => 1,
C_IRQ_ACTIVE => '1',
C_ADDR_PIPELINING_TYPE => 1,
C_FAMILY => "virtex5",
C_P2P => 0,
C_ARB_TYPE => 0
)
port map (
PLB_Clk => PLB_Clk,
SYS_Rst => SYS_Rst,
PLB_Rst => PLB_Rst,
SPLB_Rst => SPLB_Rst,
MPLB_Rst => MPLB_Rst,
PLB_dcrAck => PLB_dcrAck,
PLB_dcrDBus => PLB_dcrDBus,
DCR_ABus => DCR_ABus,
DCR_DBus => DCR_DBus,
DCR_Read => DCR_Read,
DCR_Write => DCR_Write,
M_ABus => M_ABus,
M_UABus => M_UABus,
M_BE => M_BE,
M_RNW => M_RNW,
M_abort => M_abort,
M_busLock => M_busLock,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_MSize => M_MSize,
M_priority => M_priority,
M_rdBurst => M_rdBurst,
M_request => M_request,
M_size => M_size,
M_type => M_type,
M_wrBurst => M_wrBurst,
M_wrDBus => M_wrDBus,
Sl_addrAck => Sl_addrAck,
Sl_MRdErr => Sl_MRdErr,
Sl_MWrErr => Sl_MWrErr,
Sl_MBusy => Sl_MBusy,
Sl_rdBTerm => Sl_rdBTerm,
Sl_rdComp => Sl_rdComp,
Sl_rdDAck => Sl_rdDAck,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rearbitrate => Sl_rearbitrate,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_wrBTerm => Sl_wrBTerm,
Sl_wrComp => Sl_wrComp,
Sl_wrDAck => Sl_wrDAck,
Sl_MIRQ => Sl_MIRQ,
PLB_MIRQ => PLB_MIRQ,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_BE => PLB_BE,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MSSize => PLB_MSSize,
PLB_PAValid => PLB_PAValid,
PLB_RNW => PLB_RNW,
PLB_SAValid => PLB_SAValid,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_TAttribute => PLB_TAttribute,
PLB_lockErr => PLB_lockErr,
PLB_masterID => PLB_masterID,
PLB_MSize => PLB_MSize,
PLB_rdPendPri => PLB_rdPendPri,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdBurst => PLB_rdBurst,
PLB_rdPrim => PLB_rdPrim,
PLB_reqPri => PLB_reqPri,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_wrBurst => PLB_wrBurst,
PLB_wrDBus => PLB_wrDBus,
PLB_wrPrim => PLB_wrPrim,
PLB_SaddrAck => PLB_SaddrAck,
PLB_SMRdErr => PLB_SMRdErr,
PLB_SMWrErr => PLB_SMWrErr,
PLB_SMBusy => PLB_SMBusy,
PLB_SrdBTerm => PLB_SrdBTerm,
PLB_SrdComp => PLB_SrdComp,
PLB_SrdDAck => PLB_SrdDAck,
PLB_SrdDBus => PLB_SrdDBus,
PLB_SrdWdAddr => PLB_SrdWdAddr,
PLB_Srearbitrate => PLB_Srearbitrate,
PLB_Sssize => PLB_Sssize,
PLB_Swait => PLB_Swait,
PLB_SwrBTerm => PLB_SwrBTerm,
PLB_SwrComp => PLB_SwrComp,
PLB_SwrDAck => PLB_SwrDAck,
Bus_Error_Det => Bus_Error_Det
);
end architecture STRUCTURE;
| lgpl-3.0 | ccd6cdadbe6016a18428bde4632298bf | 0.611871 | 3.039098 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00242.vhd | 1 | 4,008 | -------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00242
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.1.1.2 (8)
--
-- DESIGN UNIT ORDERING:
--
-- GENERIC_STANDARD_TYPES(ARCH00242)
-- ENT00242_Test_Bench(ARCH00242_Test_Bench)
--
-- REVISION HISTORY:
--
-- 15-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES ;
use STANDARD_TYPES.test_report, STANDARD_TYPES.switch,
STANDARD_TYPES.up, STANDARD_TYPES.down, STANDARD_TYPES.toggle,
STANDARD_TYPES."=" ;
architecture ARCH00242 of GENERIC_STANDARD_TYPES is
signal i_bit_vector_1, i_bit_vector_2 : st_bit_vector
:= c_st_bit_vector_1 ;
signal i_string_1, i_string_2 : st_string
:= c_st_string_1 ;
signal i_t_rec1_1, i_t_rec1_2 : st_rec1
:= c_st_rec1_1 ;
signal i_st_rec1_1, i_st_rec1_2 : st_rec1
:= c_st_rec1_1 ;
signal i_t_rec2_1, i_t_rec2_2 : st_rec2
:= c_st_rec2_1 ;
signal i_st_rec2_1, i_st_rec2_2 : st_rec2
:= c_st_rec2_1 ;
signal i_t_rec3_1, i_t_rec3_2 : st_rec3
:= c_st_rec3_1 ;
signal i_st_rec3_1, i_st_rec3_2 : st_rec3
:= c_st_rec3_1 ;
signal i_t_arr1_1, i_t_arr1_2 : st_arr1
:= c_st_arr1_1 ;
signal i_st_arr1_1, i_st_arr1_2 : st_arr1
:= c_st_arr1_1 ;
signal i_t_arr2_1, i_t_arr2_2 : st_arr2
:= c_st_arr2_1 ;
signal i_st_arr2_1, i_st_arr2_2 : st_arr2
:= c_st_arr2_1 ;
signal i_t_arr3_1, i_t_arr3_2 : st_arr3
:= c_st_arr3_1 ;
signal i_st_arr3_1, i_st_arr3_2 : st_arr3
:= c_st_arr3_1 ;
--
begin
L1:
block
port (
i_bit_vector_1, i_bit_vector_2 : linkage bit_vector
;
i_string_1, i_string_2 : linkage string
;
i_t_rec1_1, i_t_rec1_2 : linkage t_rec1
;
i_st_rec1_1, i_st_rec1_2 : linkage st_rec1
;
i_t_rec2_1, i_t_rec2_2 : linkage t_rec2
;
i_st_rec2_1, i_st_rec2_2 : linkage st_rec2
;
i_t_rec3_1, i_t_rec3_2 : linkage t_rec3
;
i_st_rec3_1, i_st_rec3_2 : linkage st_rec3
;
i_t_arr1_1, i_t_arr1_2 : linkage t_arr1
;
i_st_arr1_1, i_st_arr1_2 : linkage st_arr1
;
i_t_arr2_1, i_t_arr2_2 : linkage t_arr2
;
i_st_arr2_1, i_st_arr2_2 : linkage st_arr2
;
i_t_arr3_1, i_t_arr3_2 : linkage t_arr3
;
i_st_arr3_1, i_st_arr3_2 : linkage st_arr3
) ;
port map (
i_bit_vector_1, i_bit_vector_2,
i_string_1, i_string_2,
i_t_rec1_1, i_t_rec1_2,
i_st_rec1_1, i_st_rec1_2,
i_t_rec2_1, i_t_rec2_2,
i_st_rec2_1, i_st_rec2_2,
i_t_rec3_1, i_t_rec3_2,
i_st_rec3_1, i_st_rec3_2,
i_t_arr1_1, i_t_arr1_2,
i_st_arr1_1, i_st_arr1_2,
i_t_arr2_1, i_t_arr2_2,
i_st_arr2_1, i_st_arr2_2,
i_t_arr3_1, i_t_arr3_2,
i_st_arr3_1, i_st_arr3_2
) ;
--
begin
process
variable correct : boolean := true ;
begin
test_report ( "ENT00242" ,
"Associated composite linkage ports with generic subtypes" ,
correct) ;
wait ;
end process ;
end block L1 ;
end ARCH00242 ;
--
entity ENT00242_Test_Bench is
end ENT00242_Test_Bench ;
--
architecture ARCH00242_Test_Bench of ENT00242_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00242 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00242_Test_Bench ;
| gpl-3.0 | c47fe3f284ded5469bf63b921fd88962 | 0.489022 | 2.657825 | false | true | false | false |
jairov4/accel-oil | solution_virtex5_plb/impl/pcores/nfa_accept_samples_generic_hw_top_v1_01_a/synhdl/vhdl/nfa_initials_buckets_if_ap_fifo.vhd | 3 | 2,831 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity nfa_initials_buckets_if_ap_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 16;
DEPTH : integer := 1);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of nfa_initials_buckets_if_ap_fifo is
type memtype is array (0 to DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal mStorage : memtype := (others => (others => '0'));
signal mInPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal mOutPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal internal_empty_n, internal_full_n : STD_LOGIC;
signal mFlag_nEF_hint : STD_LOGIC := '0'; -- 0: empty hint, 1: full hint
begin
if_dout <= mStorage(CONV_INTEGER(mOutPtr));
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
internal_empty_n <= '0' when mInPtr = mOutPtr and mFlag_nEF_hint = '0' else '1';
internal_full_n <= '0' when mInptr = mOutPtr and mFlag_nEF_hint = '1' else '1';
process (clk, reset)
begin
if reset = '1' then
mInPtr <= (others => '0');
mOutPtr <= (others => '0');
mFlag_nEF_hint <= '0'; -- empty hint
elsif clk'event and clk = '1' then
if if_read_ce = '1' and if_read = '1' and internal_empty_n = '1' then
if (mOutPtr = DEPTH -1) then
mOutPtr <= (others => '0');
mFlag_nEF_hint <= not mFlag_nEF_hint;
else
mOutPtr <= mOutPtr + 1;
end if;
end if;
if if_write_ce = '1' and if_write = '1' and internal_full_n = '1' then
mStorage(CONV_INTEGER(mInPtr)) <= if_din;
if (mInPtr = DEPTH -1) then
mInPtr <= (others => '0');
mFlag_nEF_hint <= not mFlag_nEF_hint;
else
mInPtr <= mInPtr + 1;
end if;
end if;
end if;
end process;
end architecture;
| lgpl-3.0 | a3e14e524a1da59f94a11832ff8744c4 | 0.497704 | 3.652903 | false | false | false | false |
MilosSubotic/huffman_coding | RTL/src/rtl/histogram.vhd | 1 | 1,139 | ------------------------------------------------------------------------------
-- @license MIT
-- @brief Histogram for Huffman encoding.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.global.all;
entity histogram is
port(
i_clk : in std_logic;
in_rst : in std_logic;
i_stage : in t_stage;
i_pipe_en : in std_logic;
i_sym : in t_sym;
o_hist : out t_freq_array(0 to 15)
);
end entity histogram;
architecture arch_histogram_v1 of histogram is
signal hist : t_freq_array(0 to 15);
begin
process(i_clk, in_rst)
begin
if in_rst = '0' then
hist <= (others => (others => '0'));
elsif rising_edge(i_clk) then
if i_pipe_en = '1' then
if i_stage /= 16 then
hist(conv_integer(i_sym)) <= hist(conv_integer(i_sym)) + 1;
else
hist <= (others => (others => '0'));
end if;
end if;
end if;
end process;
o_hist <= hist;
end architecture arch_histogram_v1;
| mit | d48ec460208dcabc10fe24cee36d5c8b | 0.497805 | 3.163889 | false | false | false | false |
jairov4/accel-oil | impl/impl_test_pcie/hdl/system_mb_plb_wrapper.vhd | 1 | 14,676 | -------------------------------------------------------------------------------
-- system_mb_plb_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plb_v46_v1_05_a;
use plb_v46_v1_05_a.all;
entity system_mb_plb_wrapper is
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to 11);
MPLB_Rst : out std_logic_vector(0 to 5);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to 31);
DCR_ABus : in std_logic_vector(0 to 9);
DCR_DBus : in std_logic_vector(0 to 31);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to 191);
M_UABus : in std_logic_vector(0 to 191);
M_BE : in std_logic_vector(0 to 47);
M_RNW : in std_logic_vector(0 to 5);
M_abort : in std_logic_vector(0 to 5);
M_busLock : in std_logic_vector(0 to 5);
M_TAttribute : in std_logic_vector(0 to 95);
M_lockErr : in std_logic_vector(0 to 5);
M_MSize : in std_logic_vector(0 to 11);
M_priority : in std_logic_vector(0 to 11);
M_rdBurst : in std_logic_vector(0 to 5);
M_request : in std_logic_vector(0 to 5);
M_size : in std_logic_vector(0 to 23);
M_type : in std_logic_vector(0 to 17);
M_wrBurst : in std_logic_vector(0 to 5);
M_wrDBus : in std_logic_vector(0 to 383);
Sl_addrAck : in std_logic_vector(0 to 11);
Sl_MRdErr : in std_logic_vector(0 to 71);
Sl_MWrErr : in std_logic_vector(0 to 71);
Sl_MBusy : in std_logic_vector(0 to 71);
Sl_rdBTerm : in std_logic_vector(0 to 11);
Sl_rdComp : in std_logic_vector(0 to 11);
Sl_rdDAck : in std_logic_vector(0 to 11);
Sl_rdDBus : in std_logic_vector(0 to 767);
Sl_rdWdAddr : in std_logic_vector(0 to 47);
Sl_rearbitrate : in std_logic_vector(0 to 11);
Sl_SSize : in std_logic_vector(0 to 23);
Sl_wait : in std_logic_vector(0 to 11);
Sl_wrBTerm : in std_logic_vector(0 to 11);
Sl_wrComp : in std_logic_vector(0 to 11);
Sl_wrDAck : in std_logic_vector(0 to 11);
Sl_MIRQ : in std_logic_vector(0 to 71);
PLB_MIRQ : out std_logic_vector(0 to 5);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to 7);
PLB_MAddrAck : out std_logic_vector(0 to 5);
PLB_MTimeout : out std_logic_vector(0 to 5);
PLB_MBusy : out std_logic_vector(0 to 5);
PLB_MRdErr : out std_logic_vector(0 to 5);
PLB_MWrErr : out std_logic_vector(0 to 5);
PLB_MRdBTerm : out std_logic_vector(0 to 5);
PLB_MRdDAck : out std_logic_vector(0 to 5);
PLB_MRdDBus : out std_logic_vector(0 to 383);
PLB_MRdWdAddr : out std_logic_vector(0 to 23);
PLB_MRearbitrate : out std_logic_vector(0 to 5);
PLB_MWrBTerm : out std_logic_vector(0 to 5);
PLB_MWrDAck : out std_logic_vector(0 to 5);
PLB_MSSize : out std_logic_vector(0 to 11);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to 2);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to 11);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to 63);
PLB_wrPrim : out std_logic_vector(0 to 11);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to 5);
PLB_SMWrErr : out std_logic_vector(0 to 5);
PLB_SMBusy : out std_logic_vector(0 to 5);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to 63);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
Bus_Error_Det : out std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of system_mb_plb_wrapper : entity is "plb_v46_v1_05_a";
end system_mb_plb_wrapper;
architecture STRUCTURE of system_mb_plb_wrapper is
component plb_v46 is
generic (
C_PLBV46_NUM_MASTERS : integer;
C_PLBV46_NUM_SLAVES : integer;
C_PLBV46_MID_WIDTH : integer;
C_PLBV46_AWIDTH : integer;
C_PLBV46_DWIDTH : integer;
C_DCR_INTFCE : integer;
C_BASEADDR : std_logic_vector;
C_HIGHADDR : std_logic_vector;
C_DCR_AWIDTH : integer;
C_DCR_DWIDTH : integer;
C_EXT_RESET_HIGH : integer;
C_IRQ_ACTIVE : std_logic;
C_ADDR_PIPELINING_TYPE : integer;
C_FAMILY : string;
C_P2P : integer;
C_ARB_TYPE : integer
);
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
MPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_ABus : in std_logic_vector(0 to C_DCR_AWIDTH-1);
DCR_DBus : in std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*32)-1);
M_UABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*32)-1);
M_BE : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*(C_PLBV46_DWIDTH/8))-1);
M_RNW : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_abort : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_busLock : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_TAttribute : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*16)-1);
M_lockErr : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_MSize : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
M_priority : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
M_rdBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_request : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_size : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*4)-1);
M_type : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*3)-1);
M_wrBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_wrDBus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1);
Sl_addrAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_MRdErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1);
Sl_MWrErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1);
Sl_MBusy : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS - 1 );
Sl_rdBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdDBus : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_DWIDTH-1);
Sl_rdWdAddr : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*4-1);
Sl_rearbitrate : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_SSize : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*2-1);
Sl_wait : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_MIRQ : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS-1);
PLB_MIRQ : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to (C_PLBV46_DWIDTH/8)-1);
PLB_MAddrAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MTimeout : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdDBus : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1);
PLB_MRdWdAddr : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*4)-1);
PLB_MRearbitrate : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MSSize : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to C_PLBV46_MID_WIDTH-1);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1);
PLB_wrPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SMWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SMBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
Bus_Error_Det : out std_logic
);
end component;
begin
mb_plb : plb_v46
generic map (
C_PLBV46_NUM_MASTERS => 6,
C_PLBV46_NUM_SLAVES => 12,
C_PLBV46_MID_WIDTH => 3,
C_PLBV46_AWIDTH => 32,
C_PLBV46_DWIDTH => 64,
C_DCR_INTFCE => 0,
C_BASEADDR => B"1111111111",
C_HIGHADDR => B"0000000000",
C_DCR_AWIDTH => 10,
C_DCR_DWIDTH => 32,
C_EXT_RESET_HIGH => 1,
C_IRQ_ACTIVE => '1',
C_ADDR_PIPELINING_TYPE => 1,
C_FAMILY => "virtex5",
C_P2P => 0,
C_ARB_TYPE => 0
)
port map (
PLB_Clk => PLB_Clk,
SYS_Rst => SYS_Rst,
PLB_Rst => PLB_Rst,
SPLB_Rst => SPLB_Rst,
MPLB_Rst => MPLB_Rst,
PLB_dcrAck => PLB_dcrAck,
PLB_dcrDBus => PLB_dcrDBus,
DCR_ABus => DCR_ABus,
DCR_DBus => DCR_DBus,
DCR_Read => DCR_Read,
DCR_Write => DCR_Write,
M_ABus => M_ABus,
M_UABus => M_UABus,
M_BE => M_BE,
M_RNW => M_RNW,
M_abort => M_abort,
M_busLock => M_busLock,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_MSize => M_MSize,
M_priority => M_priority,
M_rdBurst => M_rdBurst,
M_request => M_request,
M_size => M_size,
M_type => M_type,
M_wrBurst => M_wrBurst,
M_wrDBus => M_wrDBus,
Sl_addrAck => Sl_addrAck,
Sl_MRdErr => Sl_MRdErr,
Sl_MWrErr => Sl_MWrErr,
Sl_MBusy => Sl_MBusy,
Sl_rdBTerm => Sl_rdBTerm,
Sl_rdComp => Sl_rdComp,
Sl_rdDAck => Sl_rdDAck,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rearbitrate => Sl_rearbitrate,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_wrBTerm => Sl_wrBTerm,
Sl_wrComp => Sl_wrComp,
Sl_wrDAck => Sl_wrDAck,
Sl_MIRQ => Sl_MIRQ,
PLB_MIRQ => PLB_MIRQ,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_BE => PLB_BE,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MSSize => PLB_MSSize,
PLB_PAValid => PLB_PAValid,
PLB_RNW => PLB_RNW,
PLB_SAValid => PLB_SAValid,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_TAttribute => PLB_TAttribute,
PLB_lockErr => PLB_lockErr,
PLB_masterID => PLB_masterID,
PLB_MSize => PLB_MSize,
PLB_rdPendPri => PLB_rdPendPri,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdBurst => PLB_rdBurst,
PLB_rdPrim => PLB_rdPrim,
PLB_reqPri => PLB_reqPri,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_wrBurst => PLB_wrBurst,
PLB_wrDBus => PLB_wrDBus,
PLB_wrPrim => PLB_wrPrim,
PLB_SaddrAck => PLB_SaddrAck,
PLB_SMRdErr => PLB_SMRdErr,
PLB_SMWrErr => PLB_SMWrErr,
PLB_SMBusy => PLB_SMBusy,
PLB_SrdBTerm => PLB_SrdBTerm,
PLB_SrdComp => PLB_SrdComp,
PLB_SrdDAck => PLB_SrdDAck,
PLB_SrdDBus => PLB_SrdDBus,
PLB_SrdWdAddr => PLB_SrdWdAddr,
PLB_Srearbitrate => PLB_Srearbitrate,
PLB_Sssize => PLB_Sssize,
PLB_Swait => PLB_Swait,
PLB_SwrBTerm => PLB_SwrBTerm,
PLB_SwrComp => PLB_SwrComp,
PLB_SwrDAck => PLB_SwrDAck,
Bus_Error_Det => Bus_Error_Det
);
end architecture STRUCTURE;
| lgpl-3.0 | 9371ca29b97bf2ad0b0d80cbbbd0e623 | 0.611475 | 3.039768 | false | false | false | false |
jairov4/accel-oil | solution_spartan6/syn/vhdl/sample_iterator_next.vhd | 1 | 26,409 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sample_iterator_next is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
indices_samples_req_din : OUT STD_LOGIC;
indices_samples_req_full_n : IN STD_LOGIC;
indices_samples_req_write : OUT STD_LOGIC;
indices_samples_rsp_empty_n : IN STD_LOGIC;
indices_samples_rsp_read : OUT STD_LOGIC;
indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0);
indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0);
indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
indices_begin_req_din : OUT STD_LOGIC;
indices_begin_req_full_n : IN STD_LOGIC;
indices_begin_req_write : OUT STD_LOGIC;
indices_begin_rsp_empty_n : IN STD_LOGIC;
indices_begin_rsp_read : OUT STD_LOGIC;
indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0);
indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_req_din : OUT STD_LOGIC;
indices_stride_req_full_n : IN STD_LOGIC;
indices_stride_req_write : OUT STD_LOGIC;
indices_stride_rsp_empty_n : IN STD_LOGIC;
indices_stride_rsp_read : OUT STD_LOGIC;
indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0);
indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0);
i_index : IN STD_LOGIC_VECTOR (15 downto 0);
i_sample : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (15 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (15 downto 0) );
end;
architecture behav of sample_iterator_next is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv17_1FFFF : STD_LOGIC_VECTOR (16 downto 0) := "11111111111111111";
constant ap_const_lv16_1 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000001";
constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "0";
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it4 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it5 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it6 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it7 : STD_LOGIC := '0';
signal i_sample_read_reg_128 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it1 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it2 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it3 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it4 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it5 : STD_LOGIC_VECTOR (15 downto 0);
signal i_index_read_reg_134 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it1 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it2 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it3 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it4 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it5 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it6 : STD_LOGIC_VECTOR (15 downto 0);
signal indices_samples_addr_read_reg_145 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_77_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_5_reg_155 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_6_fu_99_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_6_reg_160 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_83_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_7_reg_166 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_88_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_8_reg_171 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_s_fu_63_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_77_p0 : STD_LOGIC_VECTOR (16 downto 0);
signal grp_fu_77_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal grp_fu_83_p0 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_83_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_88_p0 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_88_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_cast_fu_93_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_6_fu_99_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_5_reg_155_temp: signed (17-1 downto 0);
signal agg_result_index_write_assign_fu_111_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal agg_result_sample_write_assign_fu_105_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_77_ce : STD_LOGIC;
signal grp_fu_83_ce : STD_LOGIC;
signal grp_fu_88_ce : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_pprstidle_pp0 : STD_LOGIC;
component nfa_accept_samples_generic_hw_add_17ns_17s_17_4 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (16 downto 0);
din1 : IN STD_LOGIC_VECTOR (16 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (16 downto 0) );
end component;
component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (15 downto 0);
din1 : IN STD_LOGIC_VECTOR (15 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (15 downto 0) );
end component;
begin
nfa_accept_samples_generic_hw_add_17ns_17s_17_4_U30 : component nfa_accept_samples_generic_hw_add_17ns_17s_17_4
generic map (
ID => 30,
NUM_STAGE => 4,
din0_WIDTH => 17,
din1_WIDTH => 17,
dout_WIDTH => 17)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_77_p0,
din1 => grp_fu_77_p1,
ce => grp_fu_77_ce,
dout => grp_fu_77_p2);
nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_U31 : component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4
generic map (
ID => 31,
NUM_STAGE => 4,
din0_WIDTH => 16,
din1_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_83_p0,
din1 => grp_fu_83_p1,
ce => grp_fu_83_ce,
dout => grp_fu_83_p2);
nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_U32 : component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4
generic map (
ID => 32,
NUM_STAGE => 4,
din0_WIDTH => 16,
din1_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_88_p0,
din1 => grp_fu_88_p1,
ce => grp_fu_88_ce,
dout => grp_fu_88_p2);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it2 assign process. --
ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it3 assign process. --
ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it4 assign process. --
ap_reg_ppiten_pp0_it4_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it5 assign process. --
ap_reg_ppiten_pp0_it5_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it6 assign process. --
ap_reg_ppiten_pp0_it6_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it6 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it7 assign process. --
ap_reg_ppiten_pp0_it7_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it7 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
ap_reg_ppstg_i_index_read_reg_134_pp0_it1 <= i_index_read_reg_134;
ap_reg_ppstg_i_index_read_reg_134_pp0_it2 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it1;
ap_reg_ppstg_i_index_read_reg_134_pp0_it3 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it2;
ap_reg_ppstg_i_index_read_reg_134_pp0_it4 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it3;
ap_reg_ppstg_i_index_read_reg_134_pp0_it5 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it4;
ap_reg_ppstg_i_index_read_reg_134_pp0_it6 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it5;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it1 <= i_sample_read_reg_128;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it2 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it1;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it3 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it2;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it4 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it3;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it5 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it4;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
i_index_read_reg_134 <= i_index;
i_sample_read_reg_128 <= i_sample;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_samples_addr_read_reg_145 <= indices_samples_datain;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
tmp_5_reg_155 <= grp_fu_77_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it6) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
tmp_6_reg_160 <= tmp_6_fu_99_p2;
tmp_7_reg_166 <= grp_fu_83_p2;
tmp_8_reg_171 <= grp_fu_88_p2;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it1 , indices_samples_rsp_empty_n , ap_ce , ap_sig_pprstidle_pp0)
begin
case ap_CS_fsm is
when ap_ST_pp0_stg0_fsm_0 =>
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
agg_result_index_write_assign_fu_111_p3 <=
ap_reg_ppstg_i_index_read_reg_134_pp0_it6 when (tmp_6_reg_160(0) = '1') else
tmp_7_reg_166;
agg_result_sample_write_assign_fu_105_p3 <=
tmp_8_reg_171 when (tmp_6_reg_160(0) = '1') else
ap_const_lv16_0;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it7, indices_samples_rsp_empty_n, ap_ce)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it6, ap_reg_ppiten_pp0_it7)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it4) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it5) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it6) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it7))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, indices_samples_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_reg_ppiten_pp0_it0 <= ap_start;
ap_return_0 <= agg_result_index_write_assign_fu_111_p3;
ap_return_1 <= agg_result_sample_write_assign_fu_105_p3;
-- ap_sig_pprstidle_pp0 assign process. --
ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it6)
begin
if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it4) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it5) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it6) and (ap_const_logic_0 = ap_start))) then
ap_sig_pprstidle_pp0 <= ap_const_logic_1;
else
ap_sig_pprstidle_pp0 <= ap_const_logic_0;
end if;
end process;
-- grp_fu_77_ce assign process. --
grp_fu_77_ce_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, indices_samples_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
grp_fu_77_ce <= ap_const_logic_1;
else
grp_fu_77_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_77_p0 <= std_logic_vector(resize(unsigned(indices_samples_addr_read_reg_145),17));
grp_fu_77_p1 <= ap_const_lv17_1FFFF;
-- grp_fu_83_ce assign process. --
grp_fu_83_ce_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, indices_samples_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
grp_fu_83_ce <= ap_const_logic_1;
else
grp_fu_83_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_83_p0 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it2;
grp_fu_83_p1 <= ap_const_lv16_1;
-- grp_fu_88_ce assign process. --
grp_fu_88_ce_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, indices_samples_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
grp_fu_88_ce <= ap_const_logic_1;
else
grp_fu_88_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_88_p0 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it2;
grp_fu_88_p1 <= ap_const_lv16_1;
indices_begin_address <= ap_const_lv32_0;
indices_begin_dataout <= ap_const_lv32_0;
indices_begin_req_din <= ap_const_logic_0;
indices_begin_req_write <= ap_const_logic_0;
indices_begin_rsp_read <= ap_const_logic_0;
indices_begin_size <= ap_const_lv32_0;
indices_samples_address <= tmp_s_fu_63_p1;
indices_samples_dataout <= ap_const_lv16_0;
indices_samples_req_din <= ap_const_logic_0;
-- indices_samples_req_write assign process. --
indices_samples_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, indices_samples_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_samples_req_write <= ap_const_logic_1;
else
indices_samples_req_write <= ap_const_logic_0;
end if;
end process;
-- indices_samples_rsp_read assign process. --
indices_samples_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, indices_samples_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_samples_rsp_read <= ap_const_logic_1;
else
indices_samples_rsp_read <= ap_const_logic_0;
end if;
end process;
indices_samples_size <= ap_const_lv32_1;
indices_stride_address <= ap_const_lv32_0;
indices_stride_dataout <= ap_const_lv8_0;
indices_stride_req_din <= ap_const_logic_0;
indices_stride_req_write <= ap_const_logic_0;
indices_stride_rsp_read <= ap_const_logic_0;
indices_stride_size <= ap_const_lv32_0;
tmp_5_reg_155_temp <= signed(tmp_5_reg_155);
tmp_6_fu_99_p1 <= std_logic_vector(resize(tmp_5_reg_155_temp,18));
tmp_6_fu_99_p2 <= "1" when (signed(tmp_cast_fu_93_p1) < signed(tmp_6_fu_99_p1)) else "0";
tmp_cast_fu_93_p1 <= std_logic_vector(resize(unsigned(ap_reg_ppstg_i_sample_read_reg_128_pp0_it5),18));
tmp_s_fu_63_p1 <= std_logic_vector(resize(unsigned(i_index),32));
end behav;
| lgpl-3.0 | 7f42fcd8feebc5f2937a34cfe101c18f | 0.600439 | 2.741514 | false | false | false | false |
jairov4/accel-oil | impl/impl_test_pcie/hdl/system_microblaze_0_wrapper.vhd | 1 | 93,946 | -------------------------------------------------------------------------------
-- system_microblaze_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library microblaze_v8_50_c;
use microblaze_v8_50_c.all;
entity system_microblaze_0_wrapper is
port (
CLK : in std_logic;
RESET : in std_logic;
MB_RESET : in std_logic;
INTERRUPT : in std_logic;
INTERRUPT_ADDRESS : in std_logic_vector(0 to 31);
INTERRUPT_ACK : out std_logic_vector(0 to 1);
EXT_BRK : in std_logic;
EXT_NM_BRK : in std_logic;
DBG_STOP : in std_logic;
MB_Halted : out std_logic;
MB_Error : out std_logic;
WAKEUP : in std_logic_vector(0 to 1);
SLEEP : out std_logic;
DBG_WAKEUP : out std_logic;
LOCKSTEP_MASTER_OUT : out std_logic_vector(0 to 4095);
LOCKSTEP_SLAVE_IN : in std_logic_vector(0 to 4095);
LOCKSTEP_OUT : out std_logic_vector(0 to 4095);
INSTR : in std_logic_vector(0 to 31);
IREADY : in std_logic;
IWAIT : in std_logic;
ICE : in std_logic;
IUE : in std_logic;
INSTR_ADDR : out std_logic_vector(0 to 31);
IFETCH : out std_logic;
I_AS : out std_logic;
IPLB_M_ABort : out std_logic;
IPLB_M_ABus : out std_logic_vector(0 to 31);
IPLB_M_UABus : out std_logic_vector(0 to 31);
IPLB_M_BE : out std_logic_vector(0 to 7);
IPLB_M_busLock : out std_logic;
IPLB_M_lockErr : out std_logic;
IPLB_M_MSize : out std_logic_vector(0 to 1);
IPLB_M_priority : out std_logic_vector(0 to 1);
IPLB_M_rdBurst : out std_logic;
IPLB_M_request : out std_logic;
IPLB_M_RNW : out std_logic;
IPLB_M_size : out std_logic_vector(0 to 3);
IPLB_M_TAttribute : out std_logic_vector(0 to 15);
IPLB_M_type : out std_logic_vector(0 to 2);
IPLB_M_wrBurst : out std_logic;
IPLB_M_wrDBus : out std_logic_vector(0 to 63);
IPLB_MBusy : in std_logic;
IPLB_MRdErr : in std_logic;
IPLB_MWrErr : in std_logic;
IPLB_MIRQ : in std_logic;
IPLB_MWrBTerm : in std_logic;
IPLB_MWrDAck : in std_logic;
IPLB_MAddrAck : in std_logic;
IPLB_MRdBTerm : in std_logic;
IPLB_MRdDAck : in std_logic;
IPLB_MRdDBus : in std_logic_vector(0 to 63);
IPLB_MRdWdAddr : in std_logic_vector(0 to 3);
IPLB_MRearbitrate : in std_logic;
IPLB_MSSize : in std_logic_vector(0 to 1);
IPLB_MTimeout : in std_logic;
DATA_READ : in std_logic_vector(0 to 31);
DREADY : in std_logic;
DWAIT : in std_logic;
DCE : in std_logic;
DUE : in std_logic;
DATA_WRITE : out std_logic_vector(0 to 31);
DATA_ADDR : out std_logic_vector(0 to 31);
D_AS : out std_logic;
READ_STROBE : out std_logic;
WRITE_STROBE : out std_logic;
BYTE_ENABLE : out std_logic_vector(0 to 3);
DPLB_M_ABort : out std_logic;
DPLB_M_ABus : out std_logic_vector(0 to 31);
DPLB_M_UABus : out std_logic_vector(0 to 31);
DPLB_M_BE : out std_logic_vector(0 to 7);
DPLB_M_busLock : out std_logic;
DPLB_M_lockErr : out std_logic;
DPLB_M_MSize : out std_logic_vector(0 to 1);
DPLB_M_priority : out std_logic_vector(0 to 1);
DPLB_M_rdBurst : out std_logic;
DPLB_M_request : out std_logic;
DPLB_M_RNW : out std_logic;
DPLB_M_size : out std_logic_vector(0 to 3);
DPLB_M_TAttribute : out std_logic_vector(0 to 15);
DPLB_M_type : out std_logic_vector(0 to 2);
DPLB_M_wrBurst : out std_logic;
DPLB_M_wrDBus : out std_logic_vector(0 to 63);
DPLB_MBusy : in std_logic;
DPLB_MRdErr : in std_logic;
DPLB_MWrErr : in std_logic;
DPLB_MIRQ : in std_logic;
DPLB_MWrBTerm : in std_logic;
DPLB_MWrDAck : in std_logic;
DPLB_MAddrAck : in std_logic;
DPLB_MRdBTerm : in std_logic;
DPLB_MRdDAck : in std_logic;
DPLB_MRdDBus : in std_logic_vector(0 to 63);
DPLB_MRdWdAddr : in std_logic_vector(0 to 3);
DPLB_MRearbitrate : in std_logic;
DPLB_MSSize : in std_logic_vector(0 to 1);
DPLB_MTimeout : in std_logic;
M_AXI_IP_AWID : out std_logic_vector(0 downto 0);
M_AXI_IP_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_IP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_AWLOCK : out std_logic;
M_AXI_IP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_AWVALID : out std_logic;
M_AXI_IP_AWREADY : in std_logic;
M_AXI_IP_WDATA : out std_logic_vector(31 downto 0);
M_AXI_IP_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_IP_WLAST : out std_logic;
M_AXI_IP_WVALID : out std_logic;
M_AXI_IP_WREADY : in std_logic;
M_AXI_IP_BID : in std_logic_vector(0 downto 0);
M_AXI_IP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_BVALID : in std_logic;
M_AXI_IP_BREADY : out std_logic;
M_AXI_IP_ARID : out std_logic_vector(0 downto 0);
M_AXI_IP_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_IP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_ARLOCK : out std_logic;
M_AXI_IP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_ARVALID : out std_logic;
M_AXI_IP_ARREADY : in std_logic;
M_AXI_IP_RID : in std_logic_vector(0 downto 0);
M_AXI_IP_RDATA : in std_logic_vector(31 downto 0);
M_AXI_IP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_RLAST : in std_logic;
M_AXI_IP_RVALID : in std_logic;
M_AXI_IP_RREADY : out std_logic;
M_AXI_DP_AWID : out std_logic_vector(0 downto 0);
M_AXI_DP_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_DP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_AWLOCK : out std_logic;
M_AXI_DP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_AWVALID : out std_logic;
M_AXI_DP_AWREADY : in std_logic;
M_AXI_DP_WDATA : out std_logic_vector(31 downto 0);
M_AXI_DP_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_DP_WLAST : out std_logic;
M_AXI_DP_WVALID : out std_logic;
M_AXI_DP_WREADY : in std_logic;
M_AXI_DP_BID : in std_logic_vector(0 downto 0);
M_AXI_DP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_BVALID : in std_logic;
M_AXI_DP_BREADY : out std_logic;
M_AXI_DP_ARID : out std_logic_vector(0 downto 0);
M_AXI_DP_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_DP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_ARLOCK : out std_logic;
M_AXI_DP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_ARVALID : out std_logic;
M_AXI_DP_ARREADY : in std_logic;
M_AXI_DP_RID : in std_logic_vector(0 downto 0);
M_AXI_DP_RDATA : in std_logic_vector(31 downto 0);
M_AXI_DP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_RLAST : in std_logic;
M_AXI_DP_RVALID : in std_logic;
M_AXI_DP_RREADY : out std_logic;
M_AXI_IC_AWID : out std_logic_vector(0 downto 0);
M_AXI_IC_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_IC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_AWLOCK : out std_logic;
M_AXI_IC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_AWVALID : out std_logic;
M_AXI_IC_AWREADY : in std_logic;
M_AXI_IC_AWUSER : out std_logic_vector(4 downto 0);
M_AXI_IC_AWDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_IC_AWSNOOP : out std_logic_vector(2 downto 0);
M_AXI_IC_AWBAR : out std_logic_vector(1 downto 0);
M_AXI_IC_WDATA : out std_logic_vector(31 downto 0);
M_AXI_IC_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_IC_WLAST : out std_logic;
M_AXI_IC_WVALID : out std_logic;
M_AXI_IC_WREADY : in std_logic;
M_AXI_IC_WUSER : out std_logic_vector(0 downto 0);
M_AXI_IC_BID : in std_logic_vector(0 downto 0);
M_AXI_IC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IC_BVALID : in std_logic;
M_AXI_IC_BREADY : out std_logic;
M_AXI_IC_BUSER : in std_logic_vector(0 downto 0);
M_AXI_IC_WACK : out std_logic;
M_AXI_IC_ARID : out std_logic_vector(0 downto 0);
M_AXI_IC_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_IC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_ARLOCK : out std_logic;
M_AXI_IC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_ARVALID : out std_logic;
M_AXI_IC_ARREADY : in std_logic;
M_AXI_IC_ARUSER : out std_logic_vector(4 downto 0);
M_AXI_IC_ARDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_IC_ARSNOOP : out std_logic_vector(3 downto 0);
M_AXI_IC_ARBAR : out std_logic_vector(1 downto 0);
M_AXI_IC_RID : in std_logic_vector(0 downto 0);
M_AXI_IC_RDATA : in std_logic_vector(31 downto 0);
M_AXI_IC_RRESP : in std_logic_vector(1 downto 0);
M_AXI_IC_RLAST : in std_logic;
M_AXI_IC_RVALID : in std_logic;
M_AXI_IC_RREADY : out std_logic;
M_AXI_IC_RUSER : in std_logic_vector(0 downto 0);
M_AXI_IC_RACK : out std_logic;
M_AXI_IC_ACVALID : in std_logic;
M_AXI_IC_ACADDR : in std_logic_vector(31 downto 0);
M_AXI_IC_ACSNOOP : in std_logic_vector(3 downto 0);
M_AXI_IC_ACPROT : in std_logic_vector(2 downto 0);
M_AXI_IC_ACREADY : out std_logic;
M_AXI_IC_CRREADY : in std_logic;
M_AXI_IC_CRVALID : out std_logic;
M_AXI_IC_CRRESP : out std_logic_vector(4 downto 0);
M_AXI_IC_CDVALID : out std_logic;
M_AXI_IC_CDREADY : in std_logic;
M_AXI_IC_CDDATA : out std_logic_vector(31 downto 0);
M_AXI_IC_CDLAST : out std_logic;
M_AXI_DC_AWID : out std_logic_vector(0 downto 0);
M_AXI_DC_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_DC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_AWLOCK : out std_logic;
M_AXI_DC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_AWVALID : out std_logic;
M_AXI_DC_AWREADY : in std_logic;
M_AXI_DC_AWUSER : out std_logic_vector(4 downto 0);
M_AXI_DC_AWDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_DC_AWSNOOP : out std_logic_vector(2 downto 0);
M_AXI_DC_AWBAR : out std_logic_vector(1 downto 0);
M_AXI_DC_WDATA : out std_logic_vector(31 downto 0);
M_AXI_DC_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_DC_WLAST : out std_logic;
M_AXI_DC_WVALID : out std_logic;
M_AXI_DC_WREADY : in std_logic;
M_AXI_DC_WUSER : out std_logic_vector(0 downto 0);
M_AXI_DC_BID : in std_logic_vector(0 downto 0);
M_AXI_DC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DC_BVALID : in std_logic;
M_AXI_DC_BREADY : out std_logic;
M_AXI_DC_BUSER : in std_logic_vector(0 downto 0);
M_AXI_DC_WACK : out std_logic;
M_AXI_DC_ARID : out std_logic_vector(0 downto 0);
M_AXI_DC_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_DC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_ARLOCK : out std_logic;
M_AXI_DC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_ARVALID : out std_logic;
M_AXI_DC_ARREADY : in std_logic;
M_AXI_DC_ARUSER : out std_logic_vector(4 downto 0);
M_AXI_DC_ARDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_DC_ARSNOOP : out std_logic_vector(3 downto 0);
M_AXI_DC_ARBAR : out std_logic_vector(1 downto 0);
M_AXI_DC_RID : in std_logic_vector(0 downto 0);
M_AXI_DC_RDATA : in std_logic_vector(31 downto 0);
M_AXI_DC_RRESP : in std_logic_vector(1 downto 0);
M_AXI_DC_RLAST : in std_logic;
M_AXI_DC_RVALID : in std_logic;
M_AXI_DC_RREADY : out std_logic;
M_AXI_DC_RUSER : in std_logic_vector(0 downto 0);
M_AXI_DC_RACK : out std_logic;
M_AXI_DC_ACVALID : in std_logic;
M_AXI_DC_ACADDR : in std_logic_vector(31 downto 0);
M_AXI_DC_ACSNOOP : in std_logic_vector(3 downto 0);
M_AXI_DC_ACPROT : in std_logic_vector(2 downto 0);
M_AXI_DC_ACREADY : out std_logic;
M_AXI_DC_CRREADY : in std_logic;
M_AXI_DC_CRVALID : out std_logic;
M_AXI_DC_CRRESP : out std_logic_vector(4 downto 0);
M_AXI_DC_CDVALID : out std_logic;
M_AXI_DC_CDREADY : in std_logic;
M_AXI_DC_CDDATA : out std_logic_vector(31 downto 0);
M_AXI_DC_CDLAST : out std_logic;
DBG_CLK : in std_logic;
DBG_TDI : in std_logic;
DBG_TDO : out std_logic;
DBG_REG_EN : in std_logic_vector(0 to 7);
DBG_SHIFT : in std_logic;
DBG_CAPTURE : in std_logic;
DBG_UPDATE : in std_logic;
DEBUG_RST : in std_logic;
Trace_Instruction : out std_logic_vector(0 to 31);
Trace_Valid_Instr : out std_logic;
Trace_PC : out std_logic_vector(0 to 31);
Trace_Reg_Write : out std_logic;
Trace_Reg_Addr : out std_logic_vector(0 to 4);
Trace_MSR_Reg : out std_logic_vector(0 to 14);
Trace_PID_Reg : out std_logic_vector(0 to 7);
Trace_New_Reg_Value : out std_logic_vector(0 to 31);
Trace_Exception_Taken : out std_logic;
Trace_Exception_Kind : out std_logic_vector(0 to 4);
Trace_Jump_Taken : out std_logic;
Trace_Delay_Slot : out std_logic;
Trace_Data_Address : out std_logic_vector(0 to 31);
Trace_Data_Access : out std_logic;
Trace_Data_Read : out std_logic;
Trace_Data_Write : out std_logic;
Trace_Data_Write_Value : out std_logic_vector(0 to 31);
Trace_Data_Byte_Enable : out std_logic_vector(0 to 3);
Trace_DCache_Req : out std_logic;
Trace_DCache_Hit : out std_logic;
Trace_DCache_Rdy : out std_logic;
Trace_DCache_Read : out std_logic;
Trace_ICache_Req : out std_logic;
Trace_ICache_Hit : out std_logic;
Trace_ICache_Rdy : out std_logic;
Trace_OF_PipeRun : out std_logic;
Trace_EX_PipeRun : out std_logic;
Trace_MEM_PipeRun : out std_logic;
Trace_MB_Halted : out std_logic;
Trace_Jump_Hit : out std_logic;
FSL0_S_CLK : out std_logic;
FSL0_S_READ : out std_logic;
FSL0_S_DATA : in std_logic_vector(0 to 31);
FSL0_S_CONTROL : in std_logic;
FSL0_S_EXISTS : in std_logic;
FSL0_M_CLK : out std_logic;
FSL0_M_WRITE : out std_logic;
FSL0_M_DATA : out std_logic_vector(0 to 31);
FSL0_M_CONTROL : out std_logic;
FSL0_M_FULL : in std_logic;
FSL1_S_CLK : out std_logic;
FSL1_S_READ : out std_logic;
FSL1_S_DATA : in std_logic_vector(0 to 31);
FSL1_S_CONTROL : in std_logic;
FSL1_S_EXISTS : in std_logic;
FSL1_M_CLK : out std_logic;
FSL1_M_WRITE : out std_logic;
FSL1_M_DATA : out std_logic_vector(0 to 31);
FSL1_M_CONTROL : out std_logic;
FSL1_M_FULL : in std_logic;
FSL2_S_CLK : out std_logic;
FSL2_S_READ : out std_logic;
FSL2_S_DATA : in std_logic_vector(0 to 31);
FSL2_S_CONTROL : in std_logic;
FSL2_S_EXISTS : in std_logic;
FSL2_M_CLK : out std_logic;
FSL2_M_WRITE : out std_logic;
FSL2_M_DATA : out std_logic_vector(0 to 31);
FSL2_M_CONTROL : out std_logic;
FSL2_M_FULL : in std_logic;
FSL3_S_CLK : out std_logic;
FSL3_S_READ : out std_logic;
FSL3_S_DATA : in std_logic_vector(0 to 31);
FSL3_S_CONTROL : in std_logic;
FSL3_S_EXISTS : in std_logic;
FSL3_M_CLK : out std_logic;
FSL3_M_WRITE : out std_logic;
FSL3_M_DATA : out std_logic_vector(0 to 31);
FSL3_M_CONTROL : out std_logic;
FSL3_M_FULL : in std_logic;
FSL4_S_CLK : out std_logic;
FSL4_S_READ : out std_logic;
FSL4_S_DATA : in std_logic_vector(0 to 31);
FSL4_S_CONTROL : in std_logic;
FSL4_S_EXISTS : in std_logic;
FSL4_M_CLK : out std_logic;
FSL4_M_WRITE : out std_logic;
FSL4_M_DATA : out std_logic_vector(0 to 31);
FSL4_M_CONTROL : out std_logic;
FSL4_M_FULL : in std_logic;
FSL5_S_CLK : out std_logic;
FSL5_S_READ : out std_logic;
FSL5_S_DATA : in std_logic_vector(0 to 31);
FSL5_S_CONTROL : in std_logic;
FSL5_S_EXISTS : in std_logic;
FSL5_M_CLK : out std_logic;
FSL5_M_WRITE : out std_logic;
FSL5_M_DATA : out std_logic_vector(0 to 31);
FSL5_M_CONTROL : out std_logic;
FSL5_M_FULL : in std_logic;
FSL6_S_CLK : out std_logic;
FSL6_S_READ : out std_logic;
FSL6_S_DATA : in std_logic_vector(0 to 31);
FSL6_S_CONTROL : in std_logic;
FSL6_S_EXISTS : in std_logic;
FSL6_M_CLK : out std_logic;
FSL6_M_WRITE : out std_logic;
FSL6_M_DATA : out std_logic_vector(0 to 31);
FSL6_M_CONTROL : out std_logic;
FSL6_M_FULL : in std_logic;
FSL7_S_CLK : out std_logic;
FSL7_S_READ : out std_logic;
FSL7_S_DATA : in std_logic_vector(0 to 31);
FSL7_S_CONTROL : in std_logic;
FSL7_S_EXISTS : in std_logic;
FSL7_M_CLK : out std_logic;
FSL7_M_WRITE : out std_logic;
FSL7_M_DATA : out std_logic_vector(0 to 31);
FSL7_M_CONTROL : out std_logic;
FSL7_M_FULL : in std_logic;
FSL8_S_CLK : out std_logic;
FSL8_S_READ : out std_logic;
FSL8_S_DATA : in std_logic_vector(0 to 31);
FSL8_S_CONTROL : in std_logic;
FSL8_S_EXISTS : in std_logic;
FSL8_M_CLK : out std_logic;
FSL8_M_WRITE : out std_logic;
FSL8_M_DATA : out std_logic_vector(0 to 31);
FSL8_M_CONTROL : out std_logic;
FSL8_M_FULL : in std_logic;
FSL9_S_CLK : out std_logic;
FSL9_S_READ : out std_logic;
FSL9_S_DATA : in std_logic_vector(0 to 31);
FSL9_S_CONTROL : in std_logic;
FSL9_S_EXISTS : in std_logic;
FSL9_M_CLK : out std_logic;
FSL9_M_WRITE : out std_logic;
FSL9_M_DATA : out std_logic_vector(0 to 31);
FSL9_M_CONTROL : out std_logic;
FSL9_M_FULL : in std_logic;
FSL10_S_CLK : out std_logic;
FSL10_S_READ : out std_logic;
FSL10_S_DATA : in std_logic_vector(0 to 31);
FSL10_S_CONTROL : in std_logic;
FSL10_S_EXISTS : in std_logic;
FSL10_M_CLK : out std_logic;
FSL10_M_WRITE : out std_logic;
FSL10_M_DATA : out std_logic_vector(0 to 31);
FSL10_M_CONTROL : out std_logic;
FSL10_M_FULL : in std_logic;
FSL11_S_CLK : out std_logic;
FSL11_S_READ : out std_logic;
FSL11_S_DATA : in std_logic_vector(0 to 31);
FSL11_S_CONTROL : in std_logic;
FSL11_S_EXISTS : in std_logic;
FSL11_M_CLK : out std_logic;
FSL11_M_WRITE : out std_logic;
FSL11_M_DATA : out std_logic_vector(0 to 31);
FSL11_M_CONTROL : out std_logic;
FSL11_M_FULL : in std_logic;
FSL12_S_CLK : out std_logic;
FSL12_S_READ : out std_logic;
FSL12_S_DATA : in std_logic_vector(0 to 31);
FSL12_S_CONTROL : in std_logic;
FSL12_S_EXISTS : in std_logic;
FSL12_M_CLK : out std_logic;
FSL12_M_WRITE : out std_logic;
FSL12_M_DATA : out std_logic_vector(0 to 31);
FSL12_M_CONTROL : out std_logic;
FSL12_M_FULL : in std_logic;
FSL13_S_CLK : out std_logic;
FSL13_S_READ : out std_logic;
FSL13_S_DATA : in std_logic_vector(0 to 31);
FSL13_S_CONTROL : in std_logic;
FSL13_S_EXISTS : in std_logic;
FSL13_M_CLK : out std_logic;
FSL13_M_WRITE : out std_logic;
FSL13_M_DATA : out std_logic_vector(0 to 31);
FSL13_M_CONTROL : out std_logic;
FSL13_M_FULL : in std_logic;
FSL14_S_CLK : out std_logic;
FSL14_S_READ : out std_logic;
FSL14_S_DATA : in std_logic_vector(0 to 31);
FSL14_S_CONTROL : in std_logic;
FSL14_S_EXISTS : in std_logic;
FSL14_M_CLK : out std_logic;
FSL14_M_WRITE : out std_logic;
FSL14_M_DATA : out std_logic_vector(0 to 31);
FSL14_M_CONTROL : out std_logic;
FSL14_M_FULL : in std_logic;
FSL15_S_CLK : out std_logic;
FSL15_S_READ : out std_logic;
FSL15_S_DATA : in std_logic_vector(0 to 31);
FSL15_S_CONTROL : in std_logic;
FSL15_S_EXISTS : in std_logic;
FSL15_M_CLK : out std_logic;
FSL15_M_WRITE : out std_logic;
FSL15_M_DATA : out std_logic_vector(0 to 31);
FSL15_M_CONTROL : out std_logic;
FSL15_M_FULL : in std_logic;
M0_AXIS_TLAST : out std_logic;
M0_AXIS_TDATA : out std_logic_vector(31 downto 0);
M0_AXIS_TVALID : out std_logic;
M0_AXIS_TREADY : in std_logic;
S0_AXIS_TLAST : in std_logic;
S0_AXIS_TDATA : in std_logic_vector(31 downto 0);
S0_AXIS_TVALID : in std_logic;
S0_AXIS_TREADY : out std_logic;
M1_AXIS_TLAST : out std_logic;
M1_AXIS_TDATA : out std_logic_vector(31 downto 0);
M1_AXIS_TVALID : out std_logic;
M1_AXIS_TREADY : in std_logic;
S1_AXIS_TLAST : in std_logic;
S1_AXIS_TDATA : in std_logic_vector(31 downto 0);
S1_AXIS_TVALID : in std_logic;
S1_AXIS_TREADY : out std_logic;
M2_AXIS_TLAST : out std_logic;
M2_AXIS_TDATA : out std_logic_vector(31 downto 0);
M2_AXIS_TVALID : out std_logic;
M2_AXIS_TREADY : in std_logic;
S2_AXIS_TLAST : in std_logic;
S2_AXIS_TDATA : in std_logic_vector(31 downto 0);
S2_AXIS_TVALID : in std_logic;
S2_AXIS_TREADY : out std_logic;
M3_AXIS_TLAST : out std_logic;
M3_AXIS_TDATA : out std_logic_vector(31 downto 0);
M3_AXIS_TVALID : out std_logic;
M3_AXIS_TREADY : in std_logic;
S3_AXIS_TLAST : in std_logic;
S3_AXIS_TDATA : in std_logic_vector(31 downto 0);
S3_AXIS_TVALID : in std_logic;
S3_AXIS_TREADY : out std_logic;
M4_AXIS_TLAST : out std_logic;
M4_AXIS_TDATA : out std_logic_vector(31 downto 0);
M4_AXIS_TVALID : out std_logic;
M4_AXIS_TREADY : in std_logic;
S4_AXIS_TLAST : in std_logic;
S4_AXIS_TDATA : in std_logic_vector(31 downto 0);
S4_AXIS_TVALID : in std_logic;
S4_AXIS_TREADY : out std_logic;
M5_AXIS_TLAST : out std_logic;
M5_AXIS_TDATA : out std_logic_vector(31 downto 0);
M5_AXIS_TVALID : out std_logic;
M5_AXIS_TREADY : in std_logic;
S5_AXIS_TLAST : in std_logic;
S5_AXIS_TDATA : in std_logic_vector(31 downto 0);
S5_AXIS_TVALID : in std_logic;
S5_AXIS_TREADY : out std_logic;
M6_AXIS_TLAST : out std_logic;
M6_AXIS_TDATA : out std_logic_vector(31 downto 0);
M6_AXIS_TVALID : out std_logic;
M6_AXIS_TREADY : in std_logic;
S6_AXIS_TLAST : in std_logic;
S6_AXIS_TDATA : in std_logic_vector(31 downto 0);
S6_AXIS_TVALID : in std_logic;
S6_AXIS_TREADY : out std_logic;
M7_AXIS_TLAST : out std_logic;
M7_AXIS_TDATA : out std_logic_vector(31 downto 0);
M7_AXIS_TVALID : out std_logic;
M7_AXIS_TREADY : in std_logic;
S7_AXIS_TLAST : in std_logic;
S7_AXIS_TDATA : in std_logic_vector(31 downto 0);
S7_AXIS_TVALID : in std_logic;
S7_AXIS_TREADY : out std_logic;
M8_AXIS_TLAST : out std_logic;
M8_AXIS_TDATA : out std_logic_vector(31 downto 0);
M8_AXIS_TVALID : out std_logic;
M8_AXIS_TREADY : in std_logic;
S8_AXIS_TLAST : in std_logic;
S8_AXIS_TDATA : in std_logic_vector(31 downto 0);
S8_AXIS_TVALID : in std_logic;
S8_AXIS_TREADY : out std_logic;
M9_AXIS_TLAST : out std_logic;
M9_AXIS_TDATA : out std_logic_vector(31 downto 0);
M9_AXIS_TVALID : out std_logic;
M9_AXIS_TREADY : in std_logic;
S9_AXIS_TLAST : in std_logic;
S9_AXIS_TDATA : in std_logic_vector(31 downto 0);
S9_AXIS_TVALID : in std_logic;
S9_AXIS_TREADY : out std_logic;
M10_AXIS_TLAST : out std_logic;
M10_AXIS_TDATA : out std_logic_vector(31 downto 0);
M10_AXIS_TVALID : out std_logic;
M10_AXIS_TREADY : in std_logic;
S10_AXIS_TLAST : in std_logic;
S10_AXIS_TDATA : in std_logic_vector(31 downto 0);
S10_AXIS_TVALID : in std_logic;
S10_AXIS_TREADY : out std_logic;
M11_AXIS_TLAST : out std_logic;
M11_AXIS_TDATA : out std_logic_vector(31 downto 0);
M11_AXIS_TVALID : out std_logic;
M11_AXIS_TREADY : in std_logic;
S11_AXIS_TLAST : in std_logic;
S11_AXIS_TDATA : in std_logic_vector(31 downto 0);
S11_AXIS_TVALID : in std_logic;
S11_AXIS_TREADY : out std_logic;
M12_AXIS_TLAST : out std_logic;
M12_AXIS_TDATA : out std_logic_vector(31 downto 0);
M12_AXIS_TVALID : out std_logic;
M12_AXIS_TREADY : in std_logic;
S12_AXIS_TLAST : in std_logic;
S12_AXIS_TDATA : in std_logic_vector(31 downto 0);
S12_AXIS_TVALID : in std_logic;
S12_AXIS_TREADY : out std_logic;
M13_AXIS_TLAST : out std_logic;
M13_AXIS_TDATA : out std_logic_vector(31 downto 0);
M13_AXIS_TVALID : out std_logic;
M13_AXIS_TREADY : in std_logic;
S13_AXIS_TLAST : in std_logic;
S13_AXIS_TDATA : in std_logic_vector(31 downto 0);
S13_AXIS_TVALID : in std_logic;
S13_AXIS_TREADY : out std_logic;
M14_AXIS_TLAST : out std_logic;
M14_AXIS_TDATA : out std_logic_vector(31 downto 0);
M14_AXIS_TVALID : out std_logic;
M14_AXIS_TREADY : in std_logic;
S14_AXIS_TLAST : in std_logic;
S14_AXIS_TDATA : in std_logic_vector(31 downto 0);
S14_AXIS_TVALID : in std_logic;
S14_AXIS_TREADY : out std_logic;
M15_AXIS_TLAST : out std_logic;
M15_AXIS_TDATA : out std_logic_vector(31 downto 0);
M15_AXIS_TVALID : out std_logic;
M15_AXIS_TREADY : in std_logic;
S15_AXIS_TLAST : in std_logic;
S15_AXIS_TDATA : in std_logic_vector(31 downto 0);
S15_AXIS_TVALID : in std_logic;
S15_AXIS_TREADY : out std_logic;
ICACHE_FSL_IN_CLK : out std_logic;
ICACHE_FSL_IN_READ : out std_logic;
ICACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
ICACHE_FSL_IN_CONTROL : in std_logic;
ICACHE_FSL_IN_EXISTS : in std_logic;
ICACHE_FSL_OUT_CLK : out std_logic;
ICACHE_FSL_OUT_WRITE : out std_logic;
ICACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
ICACHE_FSL_OUT_CONTROL : out std_logic;
ICACHE_FSL_OUT_FULL : in std_logic;
DCACHE_FSL_IN_CLK : out std_logic;
DCACHE_FSL_IN_READ : out std_logic;
DCACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
DCACHE_FSL_IN_CONTROL : in std_logic;
DCACHE_FSL_IN_EXISTS : in std_logic;
DCACHE_FSL_OUT_CLK : out std_logic;
DCACHE_FSL_OUT_WRITE : out std_logic;
DCACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
DCACHE_FSL_OUT_CONTROL : out std_logic;
DCACHE_FSL_OUT_FULL : in std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of system_microblaze_0_wrapper : entity is "microblaze_v8_50_c";
end system_microblaze_0_wrapper;
architecture STRUCTURE of system_microblaze_0_wrapper is
component microblaze is
generic (
C_SCO : integer;
C_FREQ : integer;
C_DATA_SIZE : integer;
C_DYNAMIC_BUS_SIZING : integer;
C_FAMILY : string;
C_INSTANCE : string;
C_AVOID_PRIMITIVES : integer;
C_FAULT_TOLERANT : integer;
C_ECC_USE_CE_EXCEPTION : integer;
C_LOCKSTEP_SLAVE : integer;
C_ENDIANNESS : integer;
C_AREA_OPTIMIZED : integer;
C_OPTIMIZATION : integer;
C_INTERCONNECT : integer;
C_STREAM_INTERCONNECT : integer;
C_BASE_VECTORS : std_logic_vector;
C_DPLB_DWIDTH : integer;
C_DPLB_NATIVE_DWIDTH : integer;
C_DPLB_BURST_EN : integer;
C_DPLB_P2P : integer;
C_IPLB_DWIDTH : integer;
C_IPLB_NATIVE_DWIDTH : integer;
C_IPLB_BURST_EN : integer;
C_IPLB_P2P : integer;
C_M_AXI_DP_THREAD_ID_WIDTH : integer;
C_M_AXI_DP_DATA_WIDTH : integer;
C_M_AXI_DP_ADDR_WIDTH : integer;
C_M_AXI_DP_EXCLUSIVE_ACCESS : integer;
C_M_AXI_IP_THREAD_ID_WIDTH : integer;
C_M_AXI_IP_DATA_WIDTH : integer;
C_M_AXI_IP_ADDR_WIDTH : integer;
C_D_AXI : integer;
C_D_PLB : integer;
C_D_LMB : integer;
C_I_AXI : integer;
C_I_PLB : integer;
C_I_LMB : integer;
C_USE_MSR_INSTR : integer;
C_USE_PCMP_INSTR : integer;
C_USE_BARREL : integer;
C_USE_DIV : integer;
C_USE_HW_MUL : integer;
C_USE_FPU : integer;
C_USE_REORDER_INSTR : integer;
C_UNALIGNED_EXCEPTIONS : integer;
C_ILL_OPCODE_EXCEPTION : integer;
C_M_AXI_I_BUS_EXCEPTION : integer;
C_M_AXI_D_BUS_EXCEPTION : integer;
C_IPLB_BUS_EXCEPTION : integer;
C_DPLB_BUS_EXCEPTION : integer;
C_DIV_ZERO_EXCEPTION : integer;
C_FPU_EXCEPTION : integer;
C_FSL_EXCEPTION : integer;
C_USE_STACK_PROTECTION : integer;
C_PVR : integer;
C_PVR_USER1 : std_logic_vector(0 to 7);
C_PVR_USER2 : std_logic_vector(0 to 31);
C_DEBUG_ENABLED : integer;
C_NUMBER_OF_PC_BRK : integer;
C_NUMBER_OF_RD_ADDR_BRK : integer;
C_NUMBER_OF_WR_ADDR_BRK : integer;
C_INTERRUPT_IS_EDGE : integer;
C_EDGE_IS_POSITIVE : integer;
C_RESET_MSR : std_logic_vector;
C_OPCODE_0x0_ILLEGAL : integer;
C_FSL_LINKS : integer;
C_FSL_DATA_SIZE : integer;
C_USE_EXTENDED_FSL_INSTR : integer;
C_M0_AXIS_DATA_WIDTH : integer;
C_S0_AXIS_DATA_WIDTH : integer;
C_M1_AXIS_DATA_WIDTH : integer;
C_S1_AXIS_DATA_WIDTH : integer;
C_M2_AXIS_DATA_WIDTH : integer;
C_S2_AXIS_DATA_WIDTH : integer;
C_M3_AXIS_DATA_WIDTH : integer;
C_S3_AXIS_DATA_WIDTH : integer;
C_M4_AXIS_DATA_WIDTH : integer;
C_S4_AXIS_DATA_WIDTH : integer;
C_M5_AXIS_DATA_WIDTH : integer;
C_S5_AXIS_DATA_WIDTH : integer;
C_M6_AXIS_DATA_WIDTH : integer;
C_S6_AXIS_DATA_WIDTH : integer;
C_M7_AXIS_DATA_WIDTH : integer;
C_S7_AXIS_DATA_WIDTH : integer;
C_M8_AXIS_DATA_WIDTH : integer;
C_S8_AXIS_DATA_WIDTH : integer;
C_M9_AXIS_DATA_WIDTH : integer;
C_S9_AXIS_DATA_WIDTH : integer;
C_M10_AXIS_DATA_WIDTH : integer;
C_S10_AXIS_DATA_WIDTH : integer;
C_M11_AXIS_DATA_WIDTH : integer;
C_S11_AXIS_DATA_WIDTH : integer;
C_M12_AXIS_DATA_WIDTH : integer;
C_S12_AXIS_DATA_WIDTH : integer;
C_M13_AXIS_DATA_WIDTH : integer;
C_S13_AXIS_DATA_WIDTH : integer;
C_M14_AXIS_DATA_WIDTH : integer;
C_S14_AXIS_DATA_WIDTH : integer;
C_M15_AXIS_DATA_WIDTH : integer;
C_S15_AXIS_DATA_WIDTH : integer;
C_ICACHE_BASEADDR : std_logic_vector;
C_ICACHE_HIGHADDR : std_logic_vector;
C_USE_ICACHE : integer;
C_ALLOW_ICACHE_WR : integer;
C_ADDR_TAG_BITS : integer;
C_CACHE_BYTE_SIZE : integer;
C_ICACHE_USE_FSL : integer;
C_ICACHE_LINE_LEN : integer;
C_ICACHE_ALWAYS_USED : integer;
C_ICACHE_INTERFACE : integer;
C_ICACHE_VICTIMS : integer;
C_ICACHE_STREAMS : integer;
C_ICACHE_FORCE_TAG_LUTRAM : integer;
C_ICACHE_DATA_WIDTH : integer;
C_M_AXI_IC_THREAD_ID_WIDTH : integer;
C_M_AXI_IC_DATA_WIDTH : integer;
C_M_AXI_IC_ADDR_WIDTH : integer;
C_M_AXI_IC_USER_VALUE : integer;
C_M_AXI_IC_AWUSER_WIDTH : integer;
C_M_AXI_IC_ARUSER_WIDTH : integer;
C_M_AXI_IC_WUSER_WIDTH : integer;
C_M_AXI_IC_RUSER_WIDTH : integer;
C_M_AXI_IC_BUSER_WIDTH : integer;
C_DCACHE_BASEADDR : std_logic_vector;
C_DCACHE_HIGHADDR : std_logic_vector;
C_USE_DCACHE : integer;
C_ALLOW_DCACHE_WR : integer;
C_DCACHE_ADDR_TAG : integer;
C_DCACHE_BYTE_SIZE : integer;
C_DCACHE_USE_FSL : integer;
C_DCACHE_LINE_LEN : integer;
C_DCACHE_ALWAYS_USED : integer;
C_DCACHE_INTERFACE : integer;
C_DCACHE_USE_WRITEBACK : integer;
C_DCACHE_VICTIMS : integer;
C_DCACHE_FORCE_TAG_LUTRAM : integer;
C_DCACHE_DATA_WIDTH : integer;
C_M_AXI_DC_THREAD_ID_WIDTH : integer;
C_M_AXI_DC_DATA_WIDTH : integer;
C_M_AXI_DC_ADDR_WIDTH : integer;
C_M_AXI_DC_EXCLUSIVE_ACCESS : integer;
C_M_AXI_DC_USER_VALUE : integer;
C_M_AXI_DC_AWUSER_WIDTH : integer;
C_M_AXI_DC_ARUSER_WIDTH : integer;
C_M_AXI_DC_WUSER_WIDTH : integer;
C_M_AXI_DC_RUSER_WIDTH : integer;
C_M_AXI_DC_BUSER_WIDTH : integer;
C_USE_MMU : integer;
C_MMU_DTLB_SIZE : integer;
C_MMU_ITLB_SIZE : integer;
C_MMU_TLB_ACCESS : integer;
C_MMU_ZONES : integer;
C_MMU_PRIVILEGED_INSTR : integer;
C_USE_INTERRUPT : integer;
C_USE_EXT_BRK : integer;
C_USE_EXT_NM_BRK : integer;
C_USE_BRANCH_TARGET_CACHE : integer;
C_BRANCH_TARGET_CACHE_SIZE : integer;
C_PC_WIDTH : integer
);
port (
CLK : in std_logic;
RESET : in std_logic;
MB_RESET : in std_logic;
INTERRUPT : in std_logic;
INTERRUPT_ADDRESS : in std_logic_vector(0 to 31);
INTERRUPT_ACK : out std_logic_vector(0 to 1);
EXT_BRK : in std_logic;
EXT_NM_BRK : in std_logic;
DBG_STOP : in std_logic;
MB_Halted : out std_logic;
MB_Error : out std_logic;
WAKEUP : in std_logic_vector(0 to 1);
SLEEP : out std_logic;
DBG_WAKEUP : out std_logic;
LOCKSTEP_MASTER_OUT : out std_logic_vector(0 to 4095);
LOCKSTEP_SLAVE_IN : in std_logic_vector(0 to 4095);
LOCKSTEP_OUT : out std_logic_vector(0 to 4095);
INSTR : in std_logic_vector(0 to 31);
IREADY : in std_logic;
IWAIT : in std_logic;
ICE : in std_logic;
IUE : in std_logic;
INSTR_ADDR : out std_logic_vector(0 to 31);
IFETCH : out std_logic;
I_AS : out std_logic;
IPLB_M_ABort : out std_logic;
IPLB_M_ABus : out std_logic_vector(0 to 31);
IPLB_M_UABus : out std_logic_vector(0 to 31);
IPLB_M_BE : out std_logic_vector(0 to (C_IPLB_DWIDTH-1)/8);
IPLB_M_busLock : out std_logic;
IPLB_M_lockErr : out std_logic;
IPLB_M_MSize : out std_logic_vector(0 to 1);
IPLB_M_priority : out std_logic_vector(0 to 1);
IPLB_M_rdBurst : out std_logic;
IPLB_M_request : out std_logic;
IPLB_M_RNW : out std_logic;
IPLB_M_size : out std_logic_vector(0 to 3);
IPLB_M_TAttribute : out std_logic_vector(0 to 15);
IPLB_M_type : out std_logic_vector(0 to 2);
IPLB_M_wrBurst : out std_logic;
IPLB_M_wrDBus : out std_logic_vector(0 to C_IPLB_DWIDTH-1);
IPLB_MBusy : in std_logic;
IPLB_MRdErr : in std_logic;
IPLB_MWrErr : in std_logic;
IPLB_MIRQ : in std_logic;
IPLB_MWrBTerm : in std_logic;
IPLB_MWrDAck : in std_logic;
IPLB_MAddrAck : in std_logic;
IPLB_MRdBTerm : in std_logic;
IPLB_MRdDAck : in std_logic;
IPLB_MRdDBus : in std_logic_vector(0 to C_IPLB_DWIDTH-1);
IPLB_MRdWdAddr : in std_logic_vector(0 to 3);
IPLB_MRearbitrate : in std_logic;
IPLB_MSSize : in std_logic_vector(0 to 1);
IPLB_MTimeout : in std_logic;
DATA_READ : in std_logic_vector(0 to 31);
DREADY : in std_logic;
DWAIT : in std_logic;
DCE : in std_logic;
DUE : in std_logic;
DATA_WRITE : out std_logic_vector(0 to 31);
DATA_ADDR : out std_logic_vector(0 to 31);
D_AS : out std_logic;
READ_STROBE : out std_logic;
WRITE_STROBE : out std_logic;
BYTE_ENABLE : out std_logic_vector(0 to 3);
DPLB_M_ABort : out std_logic;
DPLB_M_ABus : out std_logic_vector(0 to 31);
DPLB_M_UABus : out std_logic_vector(0 to 31);
DPLB_M_BE : out std_logic_vector(0 to (C_DPLB_DWIDTH-1)/8);
DPLB_M_busLock : out std_logic;
DPLB_M_lockErr : out std_logic;
DPLB_M_MSize : out std_logic_vector(0 to 1);
DPLB_M_priority : out std_logic_vector(0 to 1);
DPLB_M_rdBurst : out std_logic;
DPLB_M_request : out std_logic;
DPLB_M_RNW : out std_logic;
DPLB_M_size : out std_logic_vector(0 to 3);
DPLB_M_TAttribute : out std_logic_vector(0 to 15);
DPLB_M_type : out std_logic_vector(0 to 2);
DPLB_M_wrBurst : out std_logic;
DPLB_M_wrDBus : out std_logic_vector(0 to C_DPLB_DWIDTH-1);
DPLB_MBusy : in std_logic;
DPLB_MRdErr : in std_logic;
DPLB_MWrErr : in std_logic;
DPLB_MIRQ : in std_logic;
DPLB_MWrBTerm : in std_logic;
DPLB_MWrDAck : in std_logic;
DPLB_MAddrAck : in std_logic;
DPLB_MRdBTerm : in std_logic;
DPLB_MRdDAck : in std_logic;
DPLB_MRdDBus : in std_logic_vector(0 to C_DPLB_DWIDTH-1);
DPLB_MRdWdAddr : in std_logic_vector(0 to 3);
DPLB_MRearbitrate : in std_logic;
DPLB_MSSize : in std_logic_vector(0 to 1);
DPLB_MTimeout : in std_logic;
M_AXI_IP_AWID : out std_logic_vector((C_M_AXI_IP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IP_AWADDR : out std_logic_vector((C_M_AXI_IP_ADDR_WIDTH-1) downto 0);
M_AXI_IP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_AWLOCK : out std_logic;
M_AXI_IP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_AWVALID : out std_logic;
M_AXI_IP_AWREADY : in std_logic;
M_AXI_IP_WDATA : out std_logic_vector((C_M_AXI_IP_DATA_WIDTH-1) downto 0);
M_AXI_IP_WSTRB : out std_logic_vector(((C_M_AXI_IP_DATA_WIDTH/8)-1) downto 0);
M_AXI_IP_WLAST : out std_logic;
M_AXI_IP_WVALID : out std_logic;
M_AXI_IP_WREADY : in std_logic;
M_AXI_IP_BID : in std_logic_vector((C_M_AXI_IP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_BVALID : in std_logic;
M_AXI_IP_BREADY : out std_logic;
M_AXI_IP_ARID : out std_logic_vector((C_M_AXI_IP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IP_ARADDR : out std_logic_vector((C_M_AXI_IP_ADDR_WIDTH-1) downto 0);
M_AXI_IP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_ARLOCK : out std_logic;
M_AXI_IP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_ARVALID : out std_logic;
M_AXI_IP_ARREADY : in std_logic;
M_AXI_IP_RID : in std_logic_vector((C_M_AXI_IP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IP_RDATA : in std_logic_vector((C_M_AXI_IP_DATA_WIDTH-1) downto 0);
M_AXI_IP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_RLAST : in std_logic;
M_AXI_IP_RVALID : in std_logic;
M_AXI_IP_RREADY : out std_logic;
M_AXI_DP_AWID : out std_logic_vector((C_M_AXI_DP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DP_AWADDR : out std_logic_vector((C_M_AXI_DP_ADDR_WIDTH-1) downto 0);
M_AXI_DP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_AWLOCK : out std_logic;
M_AXI_DP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_AWVALID : out std_logic;
M_AXI_DP_AWREADY : in std_logic;
M_AXI_DP_WDATA : out std_logic_vector((C_M_AXI_DP_DATA_WIDTH-1) downto 0);
M_AXI_DP_WSTRB : out std_logic_vector(((C_M_AXI_DP_DATA_WIDTH/8)-1) downto 0);
M_AXI_DP_WLAST : out std_logic;
M_AXI_DP_WVALID : out std_logic;
M_AXI_DP_WREADY : in std_logic;
M_AXI_DP_BID : in std_logic_vector((C_M_AXI_DP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_BVALID : in std_logic;
M_AXI_DP_BREADY : out std_logic;
M_AXI_DP_ARID : out std_logic_vector((C_M_AXI_DP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DP_ARADDR : out std_logic_vector((C_M_AXI_DP_ADDR_WIDTH-1) downto 0);
M_AXI_DP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_ARLOCK : out std_logic;
M_AXI_DP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_ARVALID : out std_logic;
M_AXI_DP_ARREADY : in std_logic;
M_AXI_DP_RID : in std_logic_vector((C_M_AXI_DP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DP_RDATA : in std_logic_vector((C_M_AXI_DP_DATA_WIDTH-1) downto 0);
M_AXI_DP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_RLAST : in std_logic;
M_AXI_DP_RVALID : in std_logic;
M_AXI_DP_RREADY : out std_logic;
M_AXI_IC_AWID : out std_logic_vector((C_M_AXI_IC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IC_AWADDR : out std_logic_vector((C_M_AXI_IC_ADDR_WIDTH-1) downto 0);
M_AXI_IC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_AWLOCK : out std_logic;
M_AXI_IC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_AWVALID : out std_logic;
M_AXI_IC_AWREADY : in std_logic;
M_AXI_IC_AWUSER : out std_logic_vector((C_M_AXI_IC_AWUSER_WIDTH-1) downto 0);
M_AXI_IC_AWDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_IC_AWSNOOP : out std_logic_vector(2 downto 0);
M_AXI_IC_AWBAR : out std_logic_vector(1 downto 0);
M_AXI_IC_WDATA : out std_logic_vector((C_M_AXI_IC_DATA_WIDTH-1) downto 0);
M_AXI_IC_WSTRB : out std_logic_vector(((C_M_AXI_IC_DATA_WIDTH/8)-1) downto 0);
M_AXI_IC_WLAST : out std_logic;
M_AXI_IC_WVALID : out std_logic;
M_AXI_IC_WREADY : in std_logic;
M_AXI_IC_WUSER : out std_logic_vector((C_M_AXI_IC_WUSER_WIDTH-1) downto 0);
M_AXI_IC_BID : in std_logic_vector((C_M_AXI_IC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IC_BVALID : in std_logic;
M_AXI_IC_BREADY : out std_logic;
M_AXI_IC_BUSER : in std_logic_vector((C_M_AXI_IC_BUSER_WIDTH-1) downto 0);
M_AXI_IC_WACK : out std_logic;
M_AXI_IC_ARID : out std_logic_vector((C_M_AXI_IC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IC_ARADDR : out std_logic_vector((C_M_AXI_IC_ADDR_WIDTH-1) downto 0);
M_AXI_IC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_ARLOCK : out std_logic;
M_AXI_IC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_ARVALID : out std_logic;
M_AXI_IC_ARREADY : in std_logic;
M_AXI_IC_ARUSER : out std_logic_vector((C_M_AXI_IC_ARUSER_WIDTH-1) downto 0);
M_AXI_IC_ARDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_IC_ARSNOOP : out std_logic_vector(3 downto 0);
M_AXI_IC_ARBAR : out std_logic_vector(1 downto 0);
M_AXI_IC_RID : in std_logic_vector((C_M_AXI_IC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IC_RDATA : in std_logic_vector((C_M_AXI_IC_DATA_WIDTH-1) downto 0);
M_AXI_IC_RRESP : in std_logic_vector(1+2*((C_INTERCONNECT-1)/2) downto 0);
M_AXI_IC_RLAST : in std_logic;
M_AXI_IC_RVALID : in std_logic;
M_AXI_IC_RREADY : out std_logic;
M_AXI_IC_RUSER : in std_logic_vector((C_M_AXI_IC_RUSER_WIDTH-1) downto 0);
M_AXI_IC_RACK : out std_logic;
M_AXI_IC_ACVALID : in std_logic;
M_AXI_IC_ACADDR : in std_logic_vector((C_M_AXI_IC_ADDR_WIDTH-1) downto 0);
M_AXI_IC_ACSNOOP : in std_logic_vector(3 downto 0);
M_AXI_IC_ACPROT : in std_logic_vector(2 downto 0);
M_AXI_IC_ACREADY : out std_logic;
M_AXI_IC_CRREADY : in std_logic;
M_AXI_IC_CRVALID : out std_logic;
M_AXI_IC_CRRESP : out std_logic_vector(4 downto 0);
M_AXI_IC_CDVALID : out std_logic;
M_AXI_IC_CDREADY : in std_logic;
M_AXI_IC_CDDATA : out std_logic_vector((C_M_AXI_IC_DATA_WIDTH-1) downto 0);
M_AXI_IC_CDLAST : out std_logic;
M_AXI_DC_AWID : out std_logic_vector((C_M_AXI_DC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DC_AWADDR : out std_logic_vector((C_M_AXI_DC_ADDR_WIDTH-1) downto 0);
M_AXI_DC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_AWLOCK : out std_logic;
M_AXI_DC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_AWVALID : out std_logic;
M_AXI_DC_AWREADY : in std_logic;
M_AXI_DC_AWUSER : out std_logic_vector((C_M_AXI_DC_AWUSER_WIDTH-1) downto 0);
M_AXI_DC_AWDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_DC_AWSNOOP : out std_logic_vector(2 downto 0);
M_AXI_DC_AWBAR : out std_logic_vector(1 downto 0);
M_AXI_DC_WDATA : out std_logic_vector((C_M_AXI_DC_DATA_WIDTH-1) downto 0);
M_AXI_DC_WSTRB : out std_logic_vector(((C_M_AXI_DC_DATA_WIDTH/8)-1) downto 0);
M_AXI_DC_WLAST : out std_logic;
M_AXI_DC_WVALID : out std_logic;
M_AXI_DC_WREADY : in std_logic;
M_AXI_DC_WUSER : out std_logic_vector((C_M_AXI_DC_WUSER_WIDTH-1) downto 0);
M_AXI_DC_BID : in std_logic_vector((C_M_AXI_DC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DC_BVALID : in std_logic;
M_AXI_DC_BREADY : out std_logic;
M_AXI_DC_BUSER : in std_logic_vector((C_M_AXI_DC_BUSER_WIDTH-1) downto 0);
M_AXI_DC_WACK : out std_logic;
M_AXI_DC_ARID : out std_logic_vector((C_M_AXI_DC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DC_ARADDR : out std_logic_vector((C_M_AXI_DC_ADDR_WIDTH-1) downto 0);
M_AXI_DC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_ARLOCK : out std_logic;
M_AXI_DC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_ARVALID : out std_logic;
M_AXI_DC_ARREADY : in std_logic;
M_AXI_DC_ARUSER : out std_logic_vector((C_M_AXI_DC_ARUSER_WIDTH-1) downto 0);
M_AXI_DC_ARDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_DC_ARSNOOP : out std_logic_vector(3 downto 0);
M_AXI_DC_ARBAR : out std_logic_vector(1 downto 0);
M_AXI_DC_RID : in std_logic_vector((C_M_AXI_DC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DC_RDATA : in std_logic_vector((C_M_AXI_DC_DATA_WIDTH-1) downto 0);
M_AXI_DC_RRESP : in std_logic_vector(1+2*((C_INTERCONNECT-1)/2) downto 0);
M_AXI_DC_RLAST : in std_logic;
M_AXI_DC_RVALID : in std_logic;
M_AXI_DC_RREADY : out std_logic;
M_AXI_DC_RUSER : in std_logic_vector((C_M_AXI_DC_RUSER_WIDTH-1) downto 0);
M_AXI_DC_RACK : out std_logic;
M_AXI_DC_ACVALID : in std_logic;
M_AXI_DC_ACADDR : in std_logic_vector((C_M_AXI_DC_ADDR_WIDTH-1) downto 0);
M_AXI_DC_ACSNOOP : in std_logic_vector(3 downto 0);
M_AXI_DC_ACPROT : in std_logic_vector(2 downto 0);
M_AXI_DC_ACREADY : out std_logic;
M_AXI_DC_CRREADY : in std_logic;
M_AXI_DC_CRVALID : out std_logic;
M_AXI_DC_CRRESP : out std_logic_vector(4 downto 0);
M_AXI_DC_CDVALID : out std_logic;
M_AXI_DC_CDREADY : in std_logic;
M_AXI_DC_CDDATA : out std_logic_vector((C_M_AXI_DC_DATA_WIDTH-1) downto 0);
M_AXI_DC_CDLAST : out std_logic;
DBG_CLK : in std_logic;
DBG_TDI : in std_logic;
DBG_TDO : out std_logic;
DBG_REG_EN : in std_logic_vector(0 to 7);
DBG_SHIFT : in std_logic;
DBG_CAPTURE : in std_logic;
DBG_UPDATE : in std_logic;
DEBUG_RST : in std_logic;
Trace_Instruction : out std_logic_vector(0 to 31);
Trace_Valid_Instr : out std_logic;
Trace_PC : out std_logic_vector(0 to 31);
Trace_Reg_Write : out std_logic;
Trace_Reg_Addr : out std_logic_vector(0 to 4);
Trace_MSR_Reg : out std_logic_vector(0 to 14);
Trace_PID_Reg : out std_logic_vector(0 to 7);
Trace_New_Reg_Value : out std_logic_vector(0 to 31);
Trace_Exception_Taken : out std_logic;
Trace_Exception_Kind : out std_logic_vector(0 to 4);
Trace_Jump_Taken : out std_logic;
Trace_Delay_Slot : out std_logic;
Trace_Data_Address : out std_logic_vector(0 to 31);
Trace_Data_Access : out std_logic;
Trace_Data_Read : out std_logic;
Trace_Data_Write : out std_logic;
Trace_Data_Write_Value : out std_logic_vector(0 to 31);
Trace_Data_Byte_Enable : out std_logic_vector(0 to 3);
Trace_DCache_Req : out std_logic;
Trace_DCache_Hit : out std_logic;
Trace_DCache_Rdy : out std_logic;
Trace_DCache_Read : out std_logic;
Trace_ICache_Req : out std_logic;
Trace_ICache_Hit : out std_logic;
Trace_ICache_Rdy : out std_logic;
Trace_OF_PipeRun : out std_logic;
Trace_EX_PipeRun : out std_logic;
Trace_MEM_PipeRun : out std_logic;
Trace_MB_Halted : out std_logic;
Trace_Jump_Hit : out std_logic;
FSL0_S_CLK : out std_logic;
FSL0_S_READ : out std_logic;
FSL0_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL0_S_CONTROL : in std_logic;
FSL0_S_EXISTS : in std_logic;
FSL0_M_CLK : out std_logic;
FSL0_M_WRITE : out std_logic;
FSL0_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL0_M_CONTROL : out std_logic;
FSL0_M_FULL : in std_logic;
FSL1_S_CLK : out std_logic;
FSL1_S_READ : out std_logic;
FSL1_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL1_S_CONTROL : in std_logic;
FSL1_S_EXISTS : in std_logic;
FSL1_M_CLK : out std_logic;
FSL1_M_WRITE : out std_logic;
FSL1_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL1_M_CONTROL : out std_logic;
FSL1_M_FULL : in std_logic;
FSL2_S_CLK : out std_logic;
FSL2_S_READ : out std_logic;
FSL2_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL2_S_CONTROL : in std_logic;
FSL2_S_EXISTS : in std_logic;
FSL2_M_CLK : out std_logic;
FSL2_M_WRITE : out std_logic;
FSL2_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL2_M_CONTROL : out std_logic;
FSL2_M_FULL : in std_logic;
FSL3_S_CLK : out std_logic;
FSL3_S_READ : out std_logic;
FSL3_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL3_S_CONTROL : in std_logic;
FSL3_S_EXISTS : in std_logic;
FSL3_M_CLK : out std_logic;
FSL3_M_WRITE : out std_logic;
FSL3_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL3_M_CONTROL : out std_logic;
FSL3_M_FULL : in std_logic;
FSL4_S_CLK : out std_logic;
FSL4_S_READ : out std_logic;
FSL4_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL4_S_CONTROL : in std_logic;
FSL4_S_EXISTS : in std_logic;
FSL4_M_CLK : out std_logic;
FSL4_M_WRITE : out std_logic;
FSL4_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL4_M_CONTROL : out std_logic;
FSL4_M_FULL : in std_logic;
FSL5_S_CLK : out std_logic;
FSL5_S_READ : out std_logic;
FSL5_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL5_S_CONTROL : in std_logic;
FSL5_S_EXISTS : in std_logic;
FSL5_M_CLK : out std_logic;
FSL5_M_WRITE : out std_logic;
FSL5_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL5_M_CONTROL : out std_logic;
FSL5_M_FULL : in std_logic;
FSL6_S_CLK : out std_logic;
FSL6_S_READ : out std_logic;
FSL6_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL6_S_CONTROL : in std_logic;
FSL6_S_EXISTS : in std_logic;
FSL6_M_CLK : out std_logic;
FSL6_M_WRITE : out std_logic;
FSL6_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL6_M_CONTROL : out std_logic;
FSL6_M_FULL : in std_logic;
FSL7_S_CLK : out std_logic;
FSL7_S_READ : out std_logic;
FSL7_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL7_S_CONTROL : in std_logic;
FSL7_S_EXISTS : in std_logic;
FSL7_M_CLK : out std_logic;
FSL7_M_WRITE : out std_logic;
FSL7_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL7_M_CONTROL : out std_logic;
FSL7_M_FULL : in std_logic;
FSL8_S_CLK : out std_logic;
FSL8_S_READ : out std_logic;
FSL8_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL8_S_CONTROL : in std_logic;
FSL8_S_EXISTS : in std_logic;
FSL8_M_CLK : out std_logic;
FSL8_M_WRITE : out std_logic;
FSL8_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL8_M_CONTROL : out std_logic;
FSL8_M_FULL : in std_logic;
FSL9_S_CLK : out std_logic;
FSL9_S_READ : out std_logic;
FSL9_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL9_S_CONTROL : in std_logic;
FSL9_S_EXISTS : in std_logic;
FSL9_M_CLK : out std_logic;
FSL9_M_WRITE : out std_logic;
FSL9_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL9_M_CONTROL : out std_logic;
FSL9_M_FULL : in std_logic;
FSL10_S_CLK : out std_logic;
FSL10_S_READ : out std_logic;
FSL10_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL10_S_CONTROL : in std_logic;
FSL10_S_EXISTS : in std_logic;
FSL10_M_CLK : out std_logic;
FSL10_M_WRITE : out std_logic;
FSL10_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL10_M_CONTROL : out std_logic;
FSL10_M_FULL : in std_logic;
FSL11_S_CLK : out std_logic;
FSL11_S_READ : out std_logic;
FSL11_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL11_S_CONTROL : in std_logic;
FSL11_S_EXISTS : in std_logic;
FSL11_M_CLK : out std_logic;
FSL11_M_WRITE : out std_logic;
FSL11_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL11_M_CONTROL : out std_logic;
FSL11_M_FULL : in std_logic;
FSL12_S_CLK : out std_logic;
FSL12_S_READ : out std_logic;
FSL12_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL12_S_CONTROL : in std_logic;
FSL12_S_EXISTS : in std_logic;
FSL12_M_CLK : out std_logic;
FSL12_M_WRITE : out std_logic;
FSL12_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL12_M_CONTROL : out std_logic;
FSL12_M_FULL : in std_logic;
FSL13_S_CLK : out std_logic;
FSL13_S_READ : out std_logic;
FSL13_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL13_S_CONTROL : in std_logic;
FSL13_S_EXISTS : in std_logic;
FSL13_M_CLK : out std_logic;
FSL13_M_WRITE : out std_logic;
FSL13_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL13_M_CONTROL : out std_logic;
FSL13_M_FULL : in std_logic;
FSL14_S_CLK : out std_logic;
FSL14_S_READ : out std_logic;
FSL14_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL14_S_CONTROL : in std_logic;
FSL14_S_EXISTS : in std_logic;
FSL14_M_CLK : out std_logic;
FSL14_M_WRITE : out std_logic;
FSL14_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL14_M_CONTROL : out std_logic;
FSL14_M_FULL : in std_logic;
FSL15_S_CLK : out std_logic;
FSL15_S_READ : out std_logic;
FSL15_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL15_S_CONTROL : in std_logic;
FSL15_S_EXISTS : in std_logic;
FSL15_M_CLK : out std_logic;
FSL15_M_WRITE : out std_logic;
FSL15_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL15_M_CONTROL : out std_logic;
FSL15_M_FULL : in std_logic;
M0_AXIS_TLAST : out std_logic;
M0_AXIS_TDATA : out std_logic_vector(C_M0_AXIS_DATA_WIDTH-1 downto 0);
M0_AXIS_TVALID : out std_logic;
M0_AXIS_TREADY : in std_logic;
S0_AXIS_TLAST : in std_logic;
S0_AXIS_TDATA : in std_logic_vector(C_S0_AXIS_DATA_WIDTH-1 downto 0);
S0_AXIS_TVALID : in std_logic;
S0_AXIS_TREADY : out std_logic;
M1_AXIS_TLAST : out std_logic;
M1_AXIS_TDATA : out std_logic_vector(C_M1_AXIS_DATA_WIDTH-1 downto 0);
M1_AXIS_TVALID : out std_logic;
M1_AXIS_TREADY : in std_logic;
S1_AXIS_TLAST : in std_logic;
S1_AXIS_TDATA : in std_logic_vector(C_S1_AXIS_DATA_WIDTH-1 downto 0);
S1_AXIS_TVALID : in std_logic;
S1_AXIS_TREADY : out std_logic;
M2_AXIS_TLAST : out std_logic;
M2_AXIS_TDATA : out std_logic_vector(C_M2_AXIS_DATA_WIDTH-1 downto 0);
M2_AXIS_TVALID : out std_logic;
M2_AXIS_TREADY : in std_logic;
S2_AXIS_TLAST : in std_logic;
S2_AXIS_TDATA : in std_logic_vector(C_S2_AXIS_DATA_WIDTH-1 downto 0);
S2_AXIS_TVALID : in std_logic;
S2_AXIS_TREADY : out std_logic;
M3_AXIS_TLAST : out std_logic;
M3_AXIS_TDATA : out std_logic_vector(C_M3_AXIS_DATA_WIDTH-1 downto 0);
M3_AXIS_TVALID : out std_logic;
M3_AXIS_TREADY : in std_logic;
S3_AXIS_TLAST : in std_logic;
S3_AXIS_TDATA : in std_logic_vector(C_S3_AXIS_DATA_WIDTH-1 downto 0);
S3_AXIS_TVALID : in std_logic;
S3_AXIS_TREADY : out std_logic;
M4_AXIS_TLAST : out std_logic;
M4_AXIS_TDATA : out std_logic_vector(C_M4_AXIS_DATA_WIDTH-1 downto 0);
M4_AXIS_TVALID : out std_logic;
M4_AXIS_TREADY : in std_logic;
S4_AXIS_TLAST : in std_logic;
S4_AXIS_TDATA : in std_logic_vector(C_S4_AXIS_DATA_WIDTH-1 downto 0);
S4_AXIS_TVALID : in std_logic;
S4_AXIS_TREADY : out std_logic;
M5_AXIS_TLAST : out std_logic;
M5_AXIS_TDATA : out std_logic_vector(C_M5_AXIS_DATA_WIDTH-1 downto 0);
M5_AXIS_TVALID : out std_logic;
M5_AXIS_TREADY : in std_logic;
S5_AXIS_TLAST : in std_logic;
S5_AXIS_TDATA : in std_logic_vector(C_S5_AXIS_DATA_WIDTH-1 downto 0);
S5_AXIS_TVALID : in std_logic;
S5_AXIS_TREADY : out std_logic;
M6_AXIS_TLAST : out std_logic;
M6_AXIS_TDATA : out std_logic_vector(C_M6_AXIS_DATA_WIDTH-1 downto 0);
M6_AXIS_TVALID : out std_logic;
M6_AXIS_TREADY : in std_logic;
S6_AXIS_TLAST : in std_logic;
S6_AXIS_TDATA : in std_logic_vector(C_S6_AXIS_DATA_WIDTH-1 downto 0);
S6_AXIS_TVALID : in std_logic;
S6_AXIS_TREADY : out std_logic;
M7_AXIS_TLAST : out std_logic;
M7_AXIS_TDATA : out std_logic_vector(C_M7_AXIS_DATA_WIDTH-1 downto 0);
M7_AXIS_TVALID : out std_logic;
M7_AXIS_TREADY : in std_logic;
S7_AXIS_TLAST : in std_logic;
S7_AXIS_TDATA : in std_logic_vector(C_S7_AXIS_DATA_WIDTH-1 downto 0);
S7_AXIS_TVALID : in std_logic;
S7_AXIS_TREADY : out std_logic;
M8_AXIS_TLAST : out std_logic;
M8_AXIS_TDATA : out std_logic_vector(C_M8_AXIS_DATA_WIDTH-1 downto 0);
M8_AXIS_TVALID : out std_logic;
M8_AXIS_TREADY : in std_logic;
S8_AXIS_TLAST : in std_logic;
S8_AXIS_TDATA : in std_logic_vector(C_S8_AXIS_DATA_WIDTH-1 downto 0);
S8_AXIS_TVALID : in std_logic;
S8_AXIS_TREADY : out std_logic;
M9_AXIS_TLAST : out std_logic;
M9_AXIS_TDATA : out std_logic_vector(C_M9_AXIS_DATA_WIDTH-1 downto 0);
M9_AXIS_TVALID : out std_logic;
M9_AXIS_TREADY : in std_logic;
S9_AXIS_TLAST : in std_logic;
S9_AXIS_TDATA : in std_logic_vector(C_S9_AXIS_DATA_WIDTH-1 downto 0);
S9_AXIS_TVALID : in std_logic;
S9_AXIS_TREADY : out std_logic;
M10_AXIS_TLAST : out std_logic;
M10_AXIS_TDATA : out std_logic_vector(C_M10_AXIS_DATA_WIDTH-1 downto 0);
M10_AXIS_TVALID : out std_logic;
M10_AXIS_TREADY : in std_logic;
S10_AXIS_TLAST : in std_logic;
S10_AXIS_TDATA : in std_logic_vector(C_S10_AXIS_DATA_WIDTH-1 downto 0);
S10_AXIS_TVALID : in std_logic;
S10_AXIS_TREADY : out std_logic;
M11_AXIS_TLAST : out std_logic;
M11_AXIS_TDATA : out std_logic_vector(C_M11_AXIS_DATA_WIDTH-1 downto 0);
M11_AXIS_TVALID : out std_logic;
M11_AXIS_TREADY : in std_logic;
S11_AXIS_TLAST : in std_logic;
S11_AXIS_TDATA : in std_logic_vector(C_S11_AXIS_DATA_WIDTH-1 downto 0);
S11_AXIS_TVALID : in std_logic;
S11_AXIS_TREADY : out std_logic;
M12_AXIS_TLAST : out std_logic;
M12_AXIS_TDATA : out std_logic_vector(C_M12_AXIS_DATA_WIDTH-1 downto 0);
M12_AXIS_TVALID : out std_logic;
M12_AXIS_TREADY : in std_logic;
S12_AXIS_TLAST : in std_logic;
S12_AXIS_TDATA : in std_logic_vector(C_S12_AXIS_DATA_WIDTH-1 downto 0);
S12_AXIS_TVALID : in std_logic;
S12_AXIS_TREADY : out std_logic;
M13_AXIS_TLAST : out std_logic;
M13_AXIS_TDATA : out std_logic_vector(C_M13_AXIS_DATA_WIDTH-1 downto 0);
M13_AXIS_TVALID : out std_logic;
M13_AXIS_TREADY : in std_logic;
S13_AXIS_TLAST : in std_logic;
S13_AXIS_TDATA : in std_logic_vector(C_S13_AXIS_DATA_WIDTH-1 downto 0);
S13_AXIS_TVALID : in std_logic;
S13_AXIS_TREADY : out std_logic;
M14_AXIS_TLAST : out std_logic;
M14_AXIS_TDATA : out std_logic_vector(C_M14_AXIS_DATA_WIDTH-1 downto 0);
M14_AXIS_TVALID : out std_logic;
M14_AXIS_TREADY : in std_logic;
S14_AXIS_TLAST : in std_logic;
S14_AXIS_TDATA : in std_logic_vector(C_S14_AXIS_DATA_WIDTH-1 downto 0);
S14_AXIS_TVALID : in std_logic;
S14_AXIS_TREADY : out std_logic;
M15_AXIS_TLAST : out std_logic;
M15_AXIS_TDATA : out std_logic_vector(C_M15_AXIS_DATA_WIDTH-1 downto 0);
M15_AXIS_TVALID : out std_logic;
M15_AXIS_TREADY : in std_logic;
S15_AXIS_TLAST : in std_logic;
S15_AXIS_TDATA : in std_logic_vector(C_S15_AXIS_DATA_WIDTH-1 downto 0);
S15_AXIS_TVALID : in std_logic;
S15_AXIS_TREADY : out std_logic;
ICACHE_FSL_IN_CLK : out std_logic;
ICACHE_FSL_IN_READ : out std_logic;
ICACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
ICACHE_FSL_IN_CONTROL : in std_logic;
ICACHE_FSL_IN_EXISTS : in std_logic;
ICACHE_FSL_OUT_CLK : out std_logic;
ICACHE_FSL_OUT_WRITE : out std_logic;
ICACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
ICACHE_FSL_OUT_CONTROL : out std_logic;
ICACHE_FSL_OUT_FULL : in std_logic;
DCACHE_FSL_IN_CLK : out std_logic;
DCACHE_FSL_IN_READ : out std_logic;
DCACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
DCACHE_FSL_IN_CONTROL : in std_logic;
DCACHE_FSL_IN_EXISTS : in std_logic;
DCACHE_FSL_OUT_CLK : out std_logic;
DCACHE_FSL_OUT_WRITE : out std_logic;
DCACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
DCACHE_FSL_OUT_CONTROL : out std_logic;
DCACHE_FSL_OUT_FULL : in std_logic
);
end component;
begin
microblaze_0 : microblaze
generic map (
C_SCO => 0,
C_FREQ => 125000000,
C_DATA_SIZE => 32,
C_DYNAMIC_BUS_SIZING => 1,
C_FAMILY => "virtex5",
C_INSTANCE => "microblaze_0",
C_AVOID_PRIMITIVES => 0,
C_FAULT_TOLERANT => 0,
C_ECC_USE_CE_EXCEPTION => 0,
C_LOCKSTEP_SLAVE => 0,
C_ENDIANNESS => 0,
C_AREA_OPTIMIZED => 0,
C_OPTIMIZATION => 0,
C_INTERCONNECT => 1,
C_STREAM_INTERCONNECT => 0,
C_BASE_VECTORS => X"00000000",
C_DPLB_DWIDTH => 64,
C_DPLB_NATIVE_DWIDTH => 32,
C_DPLB_BURST_EN => 0,
C_DPLB_P2P => 0,
C_IPLB_DWIDTH => 64,
C_IPLB_NATIVE_DWIDTH => 32,
C_IPLB_BURST_EN => 0,
C_IPLB_P2P => 0,
C_M_AXI_DP_THREAD_ID_WIDTH => 1,
C_M_AXI_DP_DATA_WIDTH => 32,
C_M_AXI_DP_ADDR_WIDTH => 32,
C_M_AXI_DP_EXCLUSIVE_ACCESS => 0,
C_M_AXI_IP_THREAD_ID_WIDTH => 1,
C_M_AXI_IP_DATA_WIDTH => 32,
C_M_AXI_IP_ADDR_WIDTH => 32,
C_D_AXI => 0,
C_D_PLB => 1,
C_D_LMB => 1,
C_I_AXI => 0,
C_I_PLB => 1,
C_I_LMB => 1,
C_USE_MSR_INSTR => 0,
C_USE_PCMP_INSTR => 0,
C_USE_BARREL => 0,
C_USE_DIV => 0,
C_USE_HW_MUL => 0,
C_USE_FPU => 0,
C_USE_REORDER_INSTR => 0,
C_UNALIGNED_EXCEPTIONS => 0,
C_ILL_OPCODE_EXCEPTION => 0,
C_M_AXI_I_BUS_EXCEPTION => 0,
C_M_AXI_D_BUS_EXCEPTION => 0,
C_IPLB_BUS_EXCEPTION => 0,
C_DPLB_BUS_EXCEPTION => 0,
C_DIV_ZERO_EXCEPTION => 0,
C_FPU_EXCEPTION => 0,
C_FSL_EXCEPTION => 0,
C_USE_STACK_PROTECTION => 0,
C_PVR => 0,
C_PVR_USER1 => X"00",
C_PVR_USER2 => X"00000000",
C_DEBUG_ENABLED => 1,
C_NUMBER_OF_PC_BRK => 1,
C_NUMBER_OF_RD_ADDR_BRK => 0,
C_NUMBER_OF_WR_ADDR_BRK => 0,
C_INTERRUPT_IS_EDGE => 0,
C_EDGE_IS_POSITIVE => 1,
C_RESET_MSR => X"00000000",
C_OPCODE_0x0_ILLEGAL => 0,
C_FSL_LINKS => 0,
C_FSL_DATA_SIZE => 32,
C_USE_EXTENDED_FSL_INSTR => 0,
C_M0_AXIS_DATA_WIDTH => 32,
C_S0_AXIS_DATA_WIDTH => 32,
C_M1_AXIS_DATA_WIDTH => 32,
C_S1_AXIS_DATA_WIDTH => 32,
C_M2_AXIS_DATA_WIDTH => 32,
C_S2_AXIS_DATA_WIDTH => 32,
C_M3_AXIS_DATA_WIDTH => 32,
C_S3_AXIS_DATA_WIDTH => 32,
C_M4_AXIS_DATA_WIDTH => 32,
C_S4_AXIS_DATA_WIDTH => 32,
C_M5_AXIS_DATA_WIDTH => 32,
C_S5_AXIS_DATA_WIDTH => 32,
C_M6_AXIS_DATA_WIDTH => 32,
C_S6_AXIS_DATA_WIDTH => 32,
C_M7_AXIS_DATA_WIDTH => 32,
C_S7_AXIS_DATA_WIDTH => 32,
C_M8_AXIS_DATA_WIDTH => 32,
C_S8_AXIS_DATA_WIDTH => 32,
C_M9_AXIS_DATA_WIDTH => 32,
C_S9_AXIS_DATA_WIDTH => 32,
C_M10_AXIS_DATA_WIDTH => 32,
C_S10_AXIS_DATA_WIDTH => 32,
C_M11_AXIS_DATA_WIDTH => 32,
C_S11_AXIS_DATA_WIDTH => 32,
C_M12_AXIS_DATA_WIDTH => 32,
C_S12_AXIS_DATA_WIDTH => 32,
C_M13_AXIS_DATA_WIDTH => 32,
C_S13_AXIS_DATA_WIDTH => 32,
C_M14_AXIS_DATA_WIDTH => 32,
C_S14_AXIS_DATA_WIDTH => 32,
C_M15_AXIS_DATA_WIDTH => 32,
C_S15_AXIS_DATA_WIDTH => 32,
C_ICACHE_BASEADDR => X"00000000",
C_ICACHE_HIGHADDR => X"3FFFFFFF",
C_USE_ICACHE => 0,
C_ALLOW_ICACHE_WR => 1,
C_ADDR_TAG_BITS => 0,
C_CACHE_BYTE_SIZE => 2048,
C_ICACHE_USE_FSL => 1,
C_ICACHE_LINE_LEN => 4,
C_ICACHE_ALWAYS_USED => 0,
C_ICACHE_INTERFACE => 0,
C_ICACHE_VICTIMS => 0,
C_ICACHE_STREAMS => 0,
C_ICACHE_FORCE_TAG_LUTRAM => 0,
C_ICACHE_DATA_WIDTH => 0,
C_M_AXI_IC_THREAD_ID_WIDTH => 1,
C_M_AXI_IC_DATA_WIDTH => 32,
C_M_AXI_IC_ADDR_WIDTH => 32,
C_M_AXI_IC_USER_VALUE => 2#11111#,
C_M_AXI_IC_AWUSER_WIDTH => 5,
C_M_AXI_IC_ARUSER_WIDTH => 5,
C_M_AXI_IC_WUSER_WIDTH => 1,
C_M_AXI_IC_RUSER_WIDTH => 1,
C_M_AXI_IC_BUSER_WIDTH => 1,
C_DCACHE_BASEADDR => X"00000000",
C_DCACHE_HIGHADDR => X"3FFFFFFF",
C_USE_DCACHE => 0,
C_ALLOW_DCACHE_WR => 1,
C_DCACHE_ADDR_TAG => 0,
C_DCACHE_BYTE_SIZE => 2048,
C_DCACHE_USE_FSL => 1,
C_DCACHE_LINE_LEN => 4,
C_DCACHE_ALWAYS_USED => 0,
C_DCACHE_INTERFACE => 0,
C_DCACHE_USE_WRITEBACK => 0,
C_DCACHE_VICTIMS => 0,
C_DCACHE_FORCE_TAG_LUTRAM => 0,
C_DCACHE_DATA_WIDTH => 0,
C_M_AXI_DC_THREAD_ID_WIDTH => 1,
C_M_AXI_DC_DATA_WIDTH => 32,
C_M_AXI_DC_ADDR_WIDTH => 32,
C_M_AXI_DC_EXCLUSIVE_ACCESS => 0,
C_M_AXI_DC_USER_VALUE => 2#11111#,
C_M_AXI_DC_AWUSER_WIDTH => 5,
C_M_AXI_DC_ARUSER_WIDTH => 5,
C_M_AXI_DC_WUSER_WIDTH => 1,
C_M_AXI_DC_RUSER_WIDTH => 1,
C_M_AXI_DC_BUSER_WIDTH => 1,
C_USE_MMU => 0,
C_MMU_DTLB_SIZE => 4,
C_MMU_ITLB_SIZE => 2,
C_MMU_TLB_ACCESS => 3,
C_MMU_ZONES => 16,
C_MMU_PRIVILEGED_INSTR => 0,
C_USE_INTERRUPT => 1,
C_USE_EXT_BRK => 1,
C_USE_EXT_NM_BRK => 1,
C_USE_BRANCH_TARGET_CACHE => 0,
C_BRANCH_TARGET_CACHE_SIZE => 0,
C_PC_WIDTH => 32
)
port map (
CLK => CLK,
RESET => RESET,
MB_RESET => MB_RESET,
INTERRUPT => INTERRUPT,
INTERRUPT_ADDRESS => INTERRUPT_ADDRESS,
INTERRUPT_ACK => INTERRUPT_ACK,
EXT_BRK => EXT_BRK,
EXT_NM_BRK => EXT_NM_BRK,
DBG_STOP => DBG_STOP,
MB_Halted => MB_Halted,
MB_Error => MB_Error,
WAKEUP => WAKEUP,
SLEEP => SLEEP,
DBG_WAKEUP => DBG_WAKEUP,
LOCKSTEP_MASTER_OUT => LOCKSTEP_MASTER_OUT,
LOCKSTEP_SLAVE_IN => LOCKSTEP_SLAVE_IN,
LOCKSTEP_OUT => LOCKSTEP_OUT,
INSTR => INSTR,
IREADY => IREADY,
IWAIT => IWAIT,
ICE => ICE,
IUE => IUE,
INSTR_ADDR => INSTR_ADDR,
IFETCH => IFETCH,
I_AS => I_AS,
IPLB_M_ABort => IPLB_M_ABort,
IPLB_M_ABus => IPLB_M_ABus,
IPLB_M_UABus => IPLB_M_UABus,
IPLB_M_BE => IPLB_M_BE,
IPLB_M_busLock => IPLB_M_busLock,
IPLB_M_lockErr => IPLB_M_lockErr,
IPLB_M_MSize => IPLB_M_MSize,
IPLB_M_priority => IPLB_M_priority,
IPLB_M_rdBurst => IPLB_M_rdBurst,
IPLB_M_request => IPLB_M_request,
IPLB_M_RNW => IPLB_M_RNW,
IPLB_M_size => IPLB_M_size,
IPLB_M_TAttribute => IPLB_M_TAttribute,
IPLB_M_type => IPLB_M_type,
IPLB_M_wrBurst => IPLB_M_wrBurst,
IPLB_M_wrDBus => IPLB_M_wrDBus,
IPLB_MBusy => IPLB_MBusy,
IPLB_MRdErr => IPLB_MRdErr,
IPLB_MWrErr => IPLB_MWrErr,
IPLB_MIRQ => IPLB_MIRQ,
IPLB_MWrBTerm => IPLB_MWrBTerm,
IPLB_MWrDAck => IPLB_MWrDAck,
IPLB_MAddrAck => IPLB_MAddrAck,
IPLB_MRdBTerm => IPLB_MRdBTerm,
IPLB_MRdDAck => IPLB_MRdDAck,
IPLB_MRdDBus => IPLB_MRdDBus,
IPLB_MRdWdAddr => IPLB_MRdWdAddr,
IPLB_MRearbitrate => IPLB_MRearbitrate,
IPLB_MSSize => IPLB_MSSize,
IPLB_MTimeout => IPLB_MTimeout,
DATA_READ => DATA_READ,
DREADY => DREADY,
DWAIT => DWAIT,
DCE => DCE,
DUE => DUE,
DATA_WRITE => DATA_WRITE,
DATA_ADDR => DATA_ADDR,
D_AS => D_AS,
READ_STROBE => READ_STROBE,
WRITE_STROBE => WRITE_STROBE,
BYTE_ENABLE => BYTE_ENABLE,
DPLB_M_ABort => DPLB_M_ABort,
DPLB_M_ABus => DPLB_M_ABus,
DPLB_M_UABus => DPLB_M_UABus,
DPLB_M_BE => DPLB_M_BE,
DPLB_M_busLock => DPLB_M_busLock,
DPLB_M_lockErr => DPLB_M_lockErr,
DPLB_M_MSize => DPLB_M_MSize,
DPLB_M_priority => DPLB_M_priority,
DPLB_M_rdBurst => DPLB_M_rdBurst,
DPLB_M_request => DPLB_M_request,
DPLB_M_RNW => DPLB_M_RNW,
DPLB_M_size => DPLB_M_size,
DPLB_M_TAttribute => DPLB_M_TAttribute,
DPLB_M_type => DPLB_M_type,
DPLB_M_wrBurst => DPLB_M_wrBurst,
DPLB_M_wrDBus => DPLB_M_wrDBus,
DPLB_MBusy => DPLB_MBusy,
DPLB_MRdErr => DPLB_MRdErr,
DPLB_MWrErr => DPLB_MWrErr,
DPLB_MIRQ => DPLB_MIRQ,
DPLB_MWrBTerm => DPLB_MWrBTerm,
DPLB_MWrDAck => DPLB_MWrDAck,
DPLB_MAddrAck => DPLB_MAddrAck,
DPLB_MRdBTerm => DPLB_MRdBTerm,
DPLB_MRdDAck => DPLB_MRdDAck,
DPLB_MRdDBus => DPLB_MRdDBus,
DPLB_MRdWdAddr => DPLB_MRdWdAddr,
DPLB_MRearbitrate => DPLB_MRearbitrate,
DPLB_MSSize => DPLB_MSSize,
DPLB_MTimeout => DPLB_MTimeout,
M_AXI_IP_AWID => M_AXI_IP_AWID,
M_AXI_IP_AWADDR => M_AXI_IP_AWADDR,
M_AXI_IP_AWLEN => M_AXI_IP_AWLEN,
M_AXI_IP_AWSIZE => M_AXI_IP_AWSIZE,
M_AXI_IP_AWBURST => M_AXI_IP_AWBURST,
M_AXI_IP_AWLOCK => M_AXI_IP_AWLOCK,
M_AXI_IP_AWCACHE => M_AXI_IP_AWCACHE,
M_AXI_IP_AWPROT => M_AXI_IP_AWPROT,
M_AXI_IP_AWQOS => M_AXI_IP_AWQOS,
M_AXI_IP_AWVALID => M_AXI_IP_AWVALID,
M_AXI_IP_AWREADY => M_AXI_IP_AWREADY,
M_AXI_IP_WDATA => M_AXI_IP_WDATA,
M_AXI_IP_WSTRB => M_AXI_IP_WSTRB,
M_AXI_IP_WLAST => M_AXI_IP_WLAST,
M_AXI_IP_WVALID => M_AXI_IP_WVALID,
M_AXI_IP_WREADY => M_AXI_IP_WREADY,
M_AXI_IP_BID => M_AXI_IP_BID,
M_AXI_IP_BRESP => M_AXI_IP_BRESP,
M_AXI_IP_BVALID => M_AXI_IP_BVALID,
M_AXI_IP_BREADY => M_AXI_IP_BREADY,
M_AXI_IP_ARID => M_AXI_IP_ARID,
M_AXI_IP_ARADDR => M_AXI_IP_ARADDR,
M_AXI_IP_ARLEN => M_AXI_IP_ARLEN,
M_AXI_IP_ARSIZE => M_AXI_IP_ARSIZE,
M_AXI_IP_ARBURST => M_AXI_IP_ARBURST,
M_AXI_IP_ARLOCK => M_AXI_IP_ARLOCK,
M_AXI_IP_ARCACHE => M_AXI_IP_ARCACHE,
M_AXI_IP_ARPROT => M_AXI_IP_ARPROT,
M_AXI_IP_ARQOS => M_AXI_IP_ARQOS,
M_AXI_IP_ARVALID => M_AXI_IP_ARVALID,
M_AXI_IP_ARREADY => M_AXI_IP_ARREADY,
M_AXI_IP_RID => M_AXI_IP_RID,
M_AXI_IP_RDATA => M_AXI_IP_RDATA,
M_AXI_IP_RRESP => M_AXI_IP_RRESP,
M_AXI_IP_RLAST => M_AXI_IP_RLAST,
M_AXI_IP_RVALID => M_AXI_IP_RVALID,
M_AXI_IP_RREADY => M_AXI_IP_RREADY,
M_AXI_DP_AWID => M_AXI_DP_AWID,
M_AXI_DP_AWADDR => M_AXI_DP_AWADDR,
M_AXI_DP_AWLEN => M_AXI_DP_AWLEN,
M_AXI_DP_AWSIZE => M_AXI_DP_AWSIZE,
M_AXI_DP_AWBURST => M_AXI_DP_AWBURST,
M_AXI_DP_AWLOCK => M_AXI_DP_AWLOCK,
M_AXI_DP_AWCACHE => M_AXI_DP_AWCACHE,
M_AXI_DP_AWPROT => M_AXI_DP_AWPROT,
M_AXI_DP_AWQOS => M_AXI_DP_AWQOS,
M_AXI_DP_AWVALID => M_AXI_DP_AWVALID,
M_AXI_DP_AWREADY => M_AXI_DP_AWREADY,
M_AXI_DP_WDATA => M_AXI_DP_WDATA,
M_AXI_DP_WSTRB => M_AXI_DP_WSTRB,
M_AXI_DP_WLAST => M_AXI_DP_WLAST,
M_AXI_DP_WVALID => M_AXI_DP_WVALID,
M_AXI_DP_WREADY => M_AXI_DP_WREADY,
M_AXI_DP_BID => M_AXI_DP_BID,
M_AXI_DP_BRESP => M_AXI_DP_BRESP,
M_AXI_DP_BVALID => M_AXI_DP_BVALID,
M_AXI_DP_BREADY => M_AXI_DP_BREADY,
M_AXI_DP_ARID => M_AXI_DP_ARID,
M_AXI_DP_ARADDR => M_AXI_DP_ARADDR,
M_AXI_DP_ARLEN => M_AXI_DP_ARLEN,
M_AXI_DP_ARSIZE => M_AXI_DP_ARSIZE,
M_AXI_DP_ARBURST => M_AXI_DP_ARBURST,
M_AXI_DP_ARLOCK => M_AXI_DP_ARLOCK,
M_AXI_DP_ARCACHE => M_AXI_DP_ARCACHE,
M_AXI_DP_ARPROT => M_AXI_DP_ARPROT,
M_AXI_DP_ARQOS => M_AXI_DP_ARQOS,
M_AXI_DP_ARVALID => M_AXI_DP_ARVALID,
M_AXI_DP_ARREADY => M_AXI_DP_ARREADY,
M_AXI_DP_RID => M_AXI_DP_RID,
M_AXI_DP_RDATA => M_AXI_DP_RDATA,
M_AXI_DP_RRESP => M_AXI_DP_RRESP,
M_AXI_DP_RLAST => M_AXI_DP_RLAST,
M_AXI_DP_RVALID => M_AXI_DP_RVALID,
M_AXI_DP_RREADY => M_AXI_DP_RREADY,
M_AXI_IC_AWID => M_AXI_IC_AWID,
M_AXI_IC_AWADDR => M_AXI_IC_AWADDR,
M_AXI_IC_AWLEN => M_AXI_IC_AWLEN,
M_AXI_IC_AWSIZE => M_AXI_IC_AWSIZE,
M_AXI_IC_AWBURST => M_AXI_IC_AWBURST,
M_AXI_IC_AWLOCK => M_AXI_IC_AWLOCK,
M_AXI_IC_AWCACHE => M_AXI_IC_AWCACHE,
M_AXI_IC_AWPROT => M_AXI_IC_AWPROT,
M_AXI_IC_AWQOS => M_AXI_IC_AWQOS,
M_AXI_IC_AWVALID => M_AXI_IC_AWVALID,
M_AXI_IC_AWREADY => M_AXI_IC_AWREADY,
M_AXI_IC_AWUSER => M_AXI_IC_AWUSER,
M_AXI_IC_AWDOMAIN => M_AXI_IC_AWDOMAIN,
M_AXI_IC_AWSNOOP => M_AXI_IC_AWSNOOP,
M_AXI_IC_AWBAR => M_AXI_IC_AWBAR,
M_AXI_IC_WDATA => M_AXI_IC_WDATA,
M_AXI_IC_WSTRB => M_AXI_IC_WSTRB,
M_AXI_IC_WLAST => M_AXI_IC_WLAST,
M_AXI_IC_WVALID => M_AXI_IC_WVALID,
M_AXI_IC_WREADY => M_AXI_IC_WREADY,
M_AXI_IC_WUSER => M_AXI_IC_WUSER,
M_AXI_IC_BID => M_AXI_IC_BID,
M_AXI_IC_BRESP => M_AXI_IC_BRESP,
M_AXI_IC_BVALID => M_AXI_IC_BVALID,
M_AXI_IC_BREADY => M_AXI_IC_BREADY,
M_AXI_IC_BUSER => M_AXI_IC_BUSER,
M_AXI_IC_WACK => M_AXI_IC_WACK,
M_AXI_IC_ARID => M_AXI_IC_ARID,
M_AXI_IC_ARADDR => M_AXI_IC_ARADDR,
M_AXI_IC_ARLEN => M_AXI_IC_ARLEN,
M_AXI_IC_ARSIZE => M_AXI_IC_ARSIZE,
M_AXI_IC_ARBURST => M_AXI_IC_ARBURST,
M_AXI_IC_ARLOCK => M_AXI_IC_ARLOCK,
M_AXI_IC_ARCACHE => M_AXI_IC_ARCACHE,
M_AXI_IC_ARPROT => M_AXI_IC_ARPROT,
M_AXI_IC_ARQOS => M_AXI_IC_ARQOS,
M_AXI_IC_ARVALID => M_AXI_IC_ARVALID,
M_AXI_IC_ARREADY => M_AXI_IC_ARREADY,
M_AXI_IC_ARUSER => M_AXI_IC_ARUSER,
M_AXI_IC_ARDOMAIN => M_AXI_IC_ARDOMAIN,
M_AXI_IC_ARSNOOP => M_AXI_IC_ARSNOOP,
M_AXI_IC_ARBAR => M_AXI_IC_ARBAR,
M_AXI_IC_RID => M_AXI_IC_RID,
M_AXI_IC_RDATA => M_AXI_IC_RDATA,
M_AXI_IC_RRESP => M_AXI_IC_RRESP,
M_AXI_IC_RLAST => M_AXI_IC_RLAST,
M_AXI_IC_RVALID => M_AXI_IC_RVALID,
M_AXI_IC_RREADY => M_AXI_IC_RREADY,
M_AXI_IC_RUSER => M_AXI_IC_RUSER,
M_AXI_IC_RACK => M_AXI_IC_RACK,
M_AXI_IC_ACVALID => M_AXI_IC_ACVALID,
M_AXI_IC_ACADDR => M_AXI_IC_ACADDR,
M_AXI_IC_ACSNOOP => M_AXI_IC_ACSNOOP,
M_AXI_IC_ACPROT => M_AXI_IC_ACPROT,
M_AXI_IC_ACREADY => M_AXI_IC_ACREADY,
M_AXI_IC_CRREADY => M_AXI_IC_CRREADY,
M_AXI_IC_CRVALID => M_AXI_IC_CRVALID,
M_AXI_IC_CRRESP => M_AXI_IC_CRRESP,
M_AXI_IC_CDVALID => M_AXI_IC_CDVALID,
M_AXI_IC_CDREADY => M_AXI_IC_CDREADY,
M_AXI_IC_CDDATA => M_AXI_IC_CDDATA,
M_AXI_IC_CDLAST => M_AXI_IC_CDLAST,
M_AXI_DC_AWID => M_AXI_DC_AWID,
M_AXI_DC_AWADDR => M_AXI_DC_AWADDR,
M_AXI_DC_AWLEN => M_AXI_DC_AWLEN,
M_AXI_DC_AWSIZE => M_AXI_DC_AWSIZE,
M_AXI_DC_AWBURST => M_AXI_DC_AWBURST,
M_AXI_DC_AWLOCK => M_AXI_DC_AWLOCK,
M_AXI_DC_AWCACHE => M_AXI_DC_AWCACHE,
M_AXI_DC_AWPROT => M_AXI_DC_AWPROT,
M_AXI_DC_AWQOS => M_AXI_DC_AWQOS,
M_AXI_DC_AWVALID => M_AXI_DC_AWVALID,
M_AXI_DC_AWREADY => M_AXI_DC_AWREADY,
M_AXI_DC_AWUSER => M_AXI_DC_AWUSER,
M_AXI_DC_AWDOMAIN => M_AXI_DC_AWDOMAIN,
M_AXI_DC_AWSNOOP => M_AXI_DC_AWSNOOP,
M_AXI_DC_AWBAR => M_AXI_DC_AWBAR,
M_AXI_DC_WDATA => M_AXI_DC_WDATA,
M_AXI_DC_WSTRB => M_AXI_DC_WSTRB,
M_AXI_DC_WLAST => M_AXI_DC_WLAST,
M_AXI_DC_WVALID => M_AXI_DC_WVALID,
M_AXI_DC_WREADY => M_AXI_DC_WREADY,
M_AXI_DC_WUSER => M_AXI_DC_WUSER,
M_AXI_DC_BID => M_AXI_DC_BID,
M_AXI_DC_BRESP => M_AXI_DC_BRESP,
M_AXI_DC_BVALID => M_AXI_DC_BVALID,
M_AXI_DC_BREADY => M_AXI_DC_BREADY,
M_AXI_DC_BUSER => M_AXI_DC_BUSER,
M_AXI_DC_WACK => M_AXI_DC_WACK,
M_AXI_DC_ARID => M_AXI_DC_ARID,
M_AXI_DC_ARADDR => M_AXI_DC_ARADDR,
M_AXI_DC_ARLEN => M_AXI_DC_ARLEN,
M_AXI_DC_ARSIZE => M_AXI_DC_ARSIZE,
M_AXI_DC_ARBURST => M_AXI_DC_ARBURST,
M_AXI_DC_ARLOCK => M_AXI_DC_ARLOCK,
M_AXI_DC_ARCACHE => M_AXI_DC_ARCACHE,
M_AXI_DC_ARPROT => M_AXI_DC_ARPROT,
M_AXI_DC_ARQOS => M_AXI_DC_ARQOS,
M_AXI_DC_ARVALID => M_AXI_DC_ARVALID,
M_AXI_DC_ARREADY => M_AXI_DC_ARREADY,
M_AXI_DC_ARUSER => M_AXI_DC_ARUSER,
M_AXI_DC_ARDOMAIN => M_AXI_DC_ARDOMAIN,
M_AXI_DC_ARSNOOP => M_AXI_DC_ARSNOOP,
M_AXI_DC_ARBAR => M_AXI_DC_ARBAR,
M_AXI_DC_RID => M_AXI_DC_RID,
M_AXI_DC_RDATA => M_AXI_DC_RDATA,
M_AXI_DC_RRESP => M_AXI_DC_RRESP,
M_AXI_DC_RLAST => M_AXI_DC_RLAST,
M_AXI_DC_RVALID => M_AXI_DC_RVALID,
M_AXI_DC_RREADY => M_AXI_DC_RREADY,
M_AXI_DC_RUSER => M_AXI_DC_RUSER,
M_AXI_DC_RACK => M_AXI_DC_RACK,
M_AXI_DC_ACVALID => M_AXI_DC_ACVALID,
M_AXI_DC_ACADDR => M_AXI_DC_ACADDR,
M_AXI_DC_ACSNOOP => M_AXI_DC_ACSNOOP,
M_AXI_DC_ACPROT => M_AXI_DC_ACPROT,
M_AXI_DC_ACREADY => M_AXI_DC_ACREADY,
M_AXI_DC_CRREADY => M_AXI_DC_CRREADY,
M_AXI_DC_CRVALID => M_AXI_DC_CRVALID,
M_AXI_DC_CRRESP => M_AXI_DC_CRRESP,
M_AXI_DC_CDVALID => M_AXI_DC_CDVALID,
M_AXI_DC_CDREADY => M_AXI_DC_CDREADY,
M_AXI_DC_CDDATA => M_AXI_DC_CDDATA,
M_AXI_DC_CDLAST => M_AXI_DC_CDLAST,
DBG_CLK => DBG_CLK,
DBG_TDI => DBG_TDI,
DBG_TDO => DBG_TDO,
DBG_REG_EN => DBG_REG_EN,
DBG_SHIFT => DBG_SHIFT,
DBG_CAPTURE => DBG_CAPTURE,
DBG_UPDATE => DBG_UPDATE,
DEBUG_RST => DEBUG_RST,
Trace_Instruction => Trace_Instruction,
Trace_Valid_Instr => Trace_Valid_Instr,
Trace_PC => Trace_PC,
Trace_Reg_Write => Trace_Reg_Write,
Trace_Reg_Addr => Trace_Reg_Addr,
Trace_MSR_Reg => Trace_MSR_Reg,
Trace_PID_Reg => Trace_PID_Reg,
Trace_New_Reg_Value => Trace_New_Reg_Value,
Trace_Exception_Taken => Trace_Exception_Taken,
Trace_Exception_Kind => Trace_Exception_Kind,
Trace_Jump_Taken => Trace_Jump_Taken,
Trace_Delay_Slot => Trace_Delay_Slot,
Trace_Data_Address => Trace_Data_Address,
Trace_Data_Access => Trace_Data_Access,
Trace_Data_Read => Trace_Data_Read,
Trace_Data_Write => Trace_Data_Write,
Trace_Data_Write_Value => Trace_Data_Write_Value,
Trace_Data_Byte_Enable => Trace_Data_Byte_Enable,
Trace_DCache_Req => Trace_DCache_Req,
Trace_DCache_Hit => Trace_DCache_Hit,
Trace_DCache_Rdy => Trace_DCache_Rdy,
Trace_DCache_Read => Trace_DCache_Read,
Trace_ICache_Req => Trace_ICache_Req,
Trace_ICache_Hit => Trace_ICache_Hit,
Trace_ICache_Rdy => Trace_ICache_Rdy,
Trace_OF_PipeRun => Trace_OF_PipeRun,
Trace_EX_PipeRun => Trace_EX_PipeRun,
Trace_MEM_PipeRun => Trace_MEM_PipeRun,
Trace_MB_Halted => Trace_MB_Halted,
Trace_Jump_Hit => Trace_Jump_Hit,
FSL0_S_CLK => FSL0_S_CLK,
FSL0_S_READ => FSL0_S_READ,
FSL0_S_DATA => FSL0_S_DATA,
FSL0_S_CONTROL => FSL0_S_CONTROL,
FSL0_S_EXISTS => FSL0_S_EXISTS,
FSL0_M_CLK => FSL0_M_CLK,
FSL0_M_WRITE => FSL0_M_WRITE,
FSL0_M_DATA => FSL0_M_DATA,
FSL0_M_CONTROL => FSL0_M_CONTROL,
FSL0_M_FULL => FSL0_M_FULL,
FSL1_S_CLK => FSL1_S_CLK,
FSL1_S_READ => FSL1_S_READ,
FSL1_S_DATA => FSL1_S_DATA,
FSL1_S_CONTROL => FSL1_S_CONTROL,
FSL1_S_EXISTS => FSL1_S_EXISTS,
FSL1_M_CLK => FSL1_M_CLK,
FSL1_M_WRITE => FSL1_M_WRITE,
FSL1_M_DATA => FSL1_M_DATA,
FSL1_M_CONTROL => FSL1_M_CONTROL,
FSL1_M_FULL => FSL1_M_FULL,
FSL2_S_CLK => FSL2_S_CLK,
FSL2_S_READ => FSL2_S_READ,
FSL2_S_DATA => FSL2_S_DATA,
FSL2_S_CONTROL => FSL2_S_CONTROL,
FSL2_S_EXISTS => FSL2_S_EXISTS,
FSL2_M_CLK => FSL2_M_CLK,
FSL2_M_WRITE => FSL2_M_WRITE,
FSL2_M_DATA => FSL2_M_DATA,
FSL2_M_CONTROL => FSL2_M_CONTROL,
FSL2_M_FULL => FSL2_M_FULL,
FSL3_S_CLK => FSL3_S_CLK,
FSL3_S_READ => FSL3_S_READ,
FSL3_S_DATA => FSL3_S_DATA,
FSL3_S_CONTROL => FSL3_S_CONTROL,
FSL3_S_EXISTS => FSL3_S_EXISTS,
FSL3_M_CLK => FSL3_M_CLK,
FSL3_M_WRITE => FSL3_M_WRITE,
FSL3_M_DATA => FSL3_M_DATA,
FSL3_M_CONTROL => FSL3_M_CONTROL,
FSL3_M_FULL => FSL3_M_FULL,
FSL4_S_CLK => FSL4_S_CLK,
FSL4_S_READ => FSL4_S_READ,
FSL4_S_DATA => FSL4_S_DATA,
FSL4_S_CONTROL => FSL4_S_CONTROL,
FSL4_S_EXISTS => FSL4_S_EXISTS,
FSL4_M_CLK => FSL4_M_CLK,
FSL4_M_WRITE => FSL4_M_WRITE,
FSL4_M_DATA => FSL4_M_DATA,
FSL4_M_CONTROL => FSL4_M_CONTROL,
FSL4_M_FULL => FSL4_M_FULL,
FSL5_S_CLK => FSL5_S_CLK,
FSL5_S_READ => FSL5_S_READ,
FSL5_S_DATA => FSL5_S_DATA,
FSL5_S_CONTROL => FSL5_S_CONTROL,
FSL5_S_EXISTS => FSL5_S_EXISTS,
FSL5_M_CLK => FSL5_M_CLK,
FSL5_M_WRITE => FSL5_M_WRITE,
FSL5_M_DATA => FSL5_M_DATA,
FSL5_M_CONTROL => FSL5_M_CONTROL,
FSL5_M_FULL => FSL5_M_FULL,
FSL6_S_CLK => FSL6_S_CLK,
FSL6_S_READ => FSL6_S_READ,
FSL6_S_DATA => FSL6_S_DATA,
FSL6_S_CONTROL => FSL6_S_CONTROL,
FSL6_S_EXISTS => FSL6_S_EXISTS,
FSL6_M_CLK => FSL6_M_CLK,
FSL6_M_WRITE => FSL6_M_WRITE,
FSL6_M_DATA => FSL6_M_DATA,
FSL6_M_CONTROL => FSL6_M_CONTROL,
FSL6_M_FULL => FSL6_M_FULL,
FSL7_S_CLK => FSL7_S_CLK,
FSL7_S_READ => FSL7_S_READ,
FSL7_S_DATA => FSL7_S_DATA,
FSL7_S_CONTROL => FSL7_S_CONTROL,
FSL7_S_EXISTS => FSL7_S_EXISTS,
FSL7_M_CLK => FSL7_M_CLK,
FSL7_M_WRITE => FSL7_M_WRITE,
FSL7_M_DATA => FSL7_M_DATA,
FSL7_M_CONTROL => FSL7_M_CONTROL,
FSL7_M_FULL => FSL7_M_FULL,
FSL8_S_CLK => FSL8_S_CLK,
FSL8_S_READ => FSL8_S_READ,
FSL8_S_DATA => FSL8_S_DATA,
FSL8_S_CONTROL => FSL8_S_CONTROL,
FSL8_S_EXISTS => FSL8_S_EXISTS,
FSL8_M_CLK => FSL8_M_CLK,
FSL8_M_WRITE => FSL8_M_WRITE,
FSL8_M_DATA => FSL8_M_DATA,
FSL8_M_CONTROL => FSL8_M_CONTROL,
FSL8_M_FULL => FSL8_M_FULL,
FSL9_S_CLK => FSL9_S_CLK,
FSL9_S_READ => FSL9_S_READ,
FSL9_S_DATA => FSL9_S_DATA,
FSL9_S_CONTROL => FSL9_S_CONTROL,
FSL9_S_EXISTS => FSL9_S_EXISTS,
FSL9_M_CLK => FSL9_M_CLK,
FSL9_M_WRITE => FSL9_M_WRITE,
FSL9_M_DATA => FSL9_M_DATA,
FSL9_M_CONTROL => FSL9_M_CONTROL,
FSL9_M_FULL => FSL9_M_FULL,
FSL10_S_CLK => FSL10_S_CLK,
FSL10_S_READ => FSL10_S_READ,
FSL10_S_DATA => FSL10_S_DATA,
FSL10_S_CONTROL => FSL10_S_CONTROL,
FSL10_S_EXISTS => FSL10_S_EXISTS,
FSL10_M_CLK => FSL10_M_CLK,
FSL10_M_WRITE => FSL10_M_WRITE,
FSL10_M_DATA => FSL10_M_DATA,
FSL10_M_CONTROL => FSL10_M_CONTROL,
FSL10_M_FULL => FSL10_M_FULL,
FSL11_S_CLK => FSL11_S_CLK,
FSL11_S_READ => FSL11_S_READ,
FSL11_S_DATA => FSL11_S_DATA,
FSL11_S_CONTROL => FSL11_S_CONTROL,
FSL11_S_EXISTS => FSL11_S_EXISTS,
FSL11_M_CLK => FSL11_M_CLK,
FSL11_M_WRITE => FSL11_M_WRITE,
FSL11_M_DATA => FSL11_M_DATA,
FSL11_M_CONTROL => FSL11_M_CONTROL,
FSL11_M_FULL => FSL11_M_FULL,
FSL12_S_CLK => FSL12_S_CLK,
FSL12_S_READ => FSL12_S_READ,
FSL12_S_DATA => FSL12_S_DATA,
FSL12_S_CONTROL => FSL12_S_CONTROL,
FSL12_S_EXISTS => FSL12_S_EXISTS,
FSL12_M_CLK => FSL12_M_CLK,
FSL12_M_WRITE => FSL12_M_WRITE,
FSL12_M_DATA => FSL12_M_DATA,
FSL12_M_CONTROL => FSL12_M_CONTROL,
FSL12_M_FULL => FSL12_M_FULL,
FSL13_S_CLK => FSL13_S_CLK,
FSL13_S_READ => FSL13_S_READ,
FSL13_S_DATA => FSL13_S_DATA,
FSL13_S_CONTROL => FSL13_S_CONTROL,
FSL13_S_EXISTS => FSL13_S_EXISTS,
FSL13_M_CLK => FSL13_M_CLK,
FSL13_M_WRITE => FSL13_M_WRITE,
FSL13_M_DATA => FSL13_M_DATA,
FSL13_M_CONTROL => FSL13_M_CONTROL,
FSL13_M_FULL => FSL13_M_FULL,
FSL14_S_CLK => FSL14_S_CLK,
FSL14_S_READ => FSL14_S_READ,
FSL14_S_DATA => FSL14_S_DATA,
FSL14_S_CONTROL => FSL14_S_CONTROL,
FSL14_S_EXISTS => FSL14_S_EXISTS,
FSL14_M_CLK => FSL14_M_CLK,
FSL14_M_WRITE => FSL14_M_WRITE,
FSL14_M_DATA => FSL14_M_DATA,
FSL14_M_CONTROL => FSL14_M_CONTROL,
FSL14_M_FULL => FSL14_M_FULL,
FSL15_S_CLK => FSL15_S_CLK,
FSL15_S_READ => FSL15_S_READ,
FSL15_S_DATA => FSL15_S_DATA,
FSL15_S_CONTROL => FSL15_S_CONTROL,
FSL15_S_EXISTS => FSL15_S_EXISTS,
FSL15_M_CLK => FSL15_M_CLK,
FSL15_M_WRITE => FSL15_M_WRITE,
FSL15_M_DATA => FSL15_M_DATA,
FSL15_M_CONTROL => FSL15_M_CONTROL,
FSL15_M_FULL => FSL15_M_FULL,
M0_AXIS_TLAST => M0_AXIS_TLAST,
M0_AXIS_TDATA => M0_AXIS_TDATA,
M0_AXIS_TVALID => M0_AXIS_TVALID,
M0_AXIS_TREADY => M0_AXIS_TREADY,
S0_AXIS_TLAST => S0_AXIS_TLAST,
S0_AXIS_TDATA => S0_AXIS_TDATA,
S0_AXIS_TVALID => S0_AXIS_TVALID,
S0_AXIS_TREADY => S0_AXIS_TREADY,
M1_AXIS_TLAST => M1_AXIS_TLAST,
M1_AXIS_TDATA => M1_AXIS_TDATA,
M1_AXIS_TVALID => M1_AXIS_TVALID,
M1_AXIS_TREADY => M1_AXIS_TREADY,
S1_AXIS_TLAST => S1_AXIS_TLAST,
S1_AXIS_TDATA => S1_AXIS_TDATA,
S1_AXIS_TVALID => S1_AXIS_TVALID,
S1_AXIS_TREADY => S1_AXIS_TREADY,
M2_AXIS_TLAST => M2_AXIS_TLAST,
M2_AXIS_TDATA => M2_AXIS_TDATA,
M2_AXIS_TVALID => M2_AXIS_TVALID,
M2_AXIS_TREADY => M2_AXIS_TREADY,
S2_AXIS_TLAST => S2_AXIS_TLAST,
S2_AXIS_TDATA => S2_AXIS_TDATA,
S2_AXIS_TVALID => S2_AXIS_TVALID,
S2_AXIS_TREADY => S2_AXIS_TREADY,
M3_AXIS_TLAST => M3_AXIS_TLAST,
M3_AXIS_TDATA => M3_AXIS_TDATA,
M3_AXIS_TVALID => M3_AXIS_TVALID,
M3_AXIS_TREADY => M3_AXIS_TREADY,
S3_AXIS_TLAST => S3_AXIS_TLAST,
S3_AXIS_TDATA => S3_AXIS_TDATA,
S3_AXIS_TVALID => S3_AXIS_TVALID,
S3_AXIS_TREADY => S3_AXIS_TREADY,
M4_AXIS_TLAST => M4_AXIS_TLAST,
M4_AXIS_TDATA => M4_AXIS_TDATA,
M4_AXIS_TVALID => M4_AXIS_TVALID,
M4_AXIS_TREADY => M4_AXIS_TREADY,
S4_AXIS_TLAST => S4_AXIS_TLAST,
S4_AXIS_TDATA => S4_AXIS_TDATA,
S4_AXIS_TVALID => S4_AXIS_TVALID,
S4_AXIS_TREADY => S4_AXIS_TREADY,
M5_AXIS_TLAST => M5_AXIS_TLAST,
M5_AXIS_TDATA => M5_AXIS_TDATA,
M5_AXIS_TVALID => M5_AXIS_TVALID,
M5_AXIS_TREADY => M5_AXIS_TREADY,
S5_AXIS_TLAST => S5_AXIS_TLAST,
S5_AXIS_TDATA => S5_AXIS_TDATA,
S5_AXIS_TVALID => S5_AXIS_TVALID,
S5_AXIS_TREADY => S5_AXIS_TREADY,
M6_AXIS_TLAST => M6_AXIS_TLAST,
M6_AXIS_TDATA => M6_AXIS_TDATA,
M6_AXIS_TVALID => M6_AXIS_TVALID,
M6_AXIS_TREADY => M6_AXIS_TREADY,
S6_AXIS_TLAST => S6_AXIS_TLAST,
S6_AXIS_TDATA => S6_AXIS_TDATA,
S6_AXIS_TVALID => S6_AXIS_TVALID,
S6_AXIS_TREADY => S6_AXIS_TREADY,
M7_AXIS_TLAST => M7_AXIS_TLAST,
M7_AXIS_TDATA => M7_AXIS_TDATA,
M7_AXIS_TVALID => M7_AXIS_TVALID,
M7_AXIS_TREADY => M7_AXIS_TREADY,
S7_AXIS_TLAST => S7_AXIS_TLAST,
S7_AXIS_TDATA => S7_AXIS_TDATA,
S7_AXIS_TVALID => S7_AXIS_TVALID,
S7_AXIS_TREADY => S7_AXIS_TREADY,
M8_AXIS_TLAST => M8_AXIS_TLAST,
M8_AXIS_TDATA => M8_AXIS_TDATA,
M8_AXIS_TVALID => M8_AXIS_TVALID,
M8_AXIS_TREADY => M8_AXIS_TREADY,
S8_AXIS_TLAST => S8_AXIS_TLAST,
S8_AXIS_TDATA => S8_AXIS_TDATA,
S8_AXIS_TVALID => S8_AXIS_TVALID,
S8_AXIS_TREADY => S8_AXIS_TREADY,
M9_AXIS_TLAST => M9_AXIS_TLAST,
M9_AXIS_TDATA => M9_AXIS_TDATA,
M9_AXIS_TVALID => M9_AXIS_TVALID,
M9_AXIS_TREADY => M9_AXIS_TREADY,
S9_AXIS_TLAST => S9_AXIS_TLAST,
S9_AXIS_TDATA => S9_AXIS_TDATA,
S9_AXIS_TVALID => S9_AXIS_TVALID,
S9_AXIS_TREADY => S9_AXIS_TREADY,
M10_AXIS_TLAST => M10_AXIS_TLAST,
M10_AXIS_TDATA => M10_AXIS_TDATA,
M10_AXIS_TVALID => M10_AXIS_TVALID,
M10_AXIS_TREADY => M10_AXIS_TREADY,
S10_AXIS_TLAST => S10_AXIS_TLAST,
S10_AXIS_TDATA => S10_AXIS_TDATA,
S10_AXIS_TVALID => S10_AXIS_TVALID,
S10_AXIS_TREADY => S10_AXIS_TREADY,
M11_AXIS_TLAST => M11_AXIS_TLAST,
M11_AXIS_TDATA => M11_AXIS_TDATA,
M11_AXIS_TVALID => M11_AXIS_TVALID,
M11_AXIS_TREADY => M11_AXIS_TREADY,
S11_AXIS_TLAST => S11_AXIS_TLAST,
S11_AXIS_TDATA => S11_AXIS_TDATA,
S11_AXIS_TVALID => S11_AXIS_TVALID,
S11_AXIS_TREADY => S11_AXIS_TREADY,
M12_AXIS_TLAST => M12_AXIS_TLAST,
M12_AXIS_TDATA => M12_AXIS_TDATA,
M12_AXIS_TVALID => M12_AXIS_TVALID,
M12_AXIS_TREADY => M12_AXIS_TREADY,
S12_AXIS_TLAST => S12_AXIS_TLAST,
S12_AXIS_TDATA => S12_AXIS_TDATA,
S12_AXIS_TVALID => S12_AXIS_TVALID,
S12_AXIS_TREADY => S12_AXIS_TREADY,
M13_AXIS_TLAST => M13_AXIS_TLAST,
M13_AXIS_TDATA => M13_AXIS_TDATA,
M13_AXIS_TVALID => M13_AXIS_TVALID,
M13_AXIS_TREADY => M13_AXIS_TREADY,
S13_AXIS_TLAST => S13_AXIS_TLAST,
S13_AXIS_TDATA => S13_AXIS_TDATA,
S13_AXIS_TVALID => S13_AXIS_TVALID,
S13_AXIS_TREADY => S13_AXIS_TREADY,
M14_AXIS_TLAST => M14_AXIS_TLAST,
M14_AXIS_TDATA => M14_AXIS_TDATA,
M14_AXIS_TVALID => M14_AXIS_TVALID,
M14_AXIS_TREADY => M14_AXIS_TREADY,
S14_AXIS_TLAST => S14_AXIS_TLAST,
S14_AXIS_TDATA => S14_AXIS_TDATA,
S14_AXIS_TVALID => S14_AXIS_TVALID,
S14_AXIS_TREADY => S14_AXIS_TREADY,
M15_AXIS_TLAST => M15_AXIS_TLAST,
M15_AXIS_TDATA => M15_AXIS_TDATA,
M15_AXIS_TVALID => M15_AXIS_TVALID,
M15_AXIS_TREADY => M15_AXIS_TREADY,
S15_AXIS_TLAST => S15_AXIS_TLAST,
S15_AXIS_TDATA => S15_AXIS_TDATA,
S15_AXIS_TVALID => S15_AXIS_TVALID,
S15_AXIS_TREADY => S15_AXIS_TREADY,
ICACHE_FSL_IN_CLK => ICACHE_FSL_IN_CLK,
ICACHE_FSL_IN_READ => ICACHE_FSL_IN_READ,
ICACHE_FSL_IN_DATA => ICACHE_FSL_IN_DATA,
ICACHE_FSL_IN_CONTROL => ICACHE_FSL_IN_CONTROL,
ICACHE_FSL_IN_EXISTS => ICACHE_FSL_IN_EXISTS,
ICACHE_FSL_OUT_CLK => ICACHE_FSL_OUT_CLK,
ICACHE_FSL_OUT_WRITE => ICACHE_FSL_OUT_WRITE,
ICACHE_FSL_OUT_DATA => ICACHE_FSL_OUT_DATA,
ICACHE_FSL_OUT_CONTROL => ICACHE_FSL_OUT_CONTROL,
ICACHE_FSL_OUT_FULL => ICACHE_FSL_OUT_FULL,
DCACHE_FSL_IN_CLK => DCACHE_FSL_IN_CLK,
DCACHE_FSL_IN_READ => DCACHE_FSL_IN_READ,
DCACHE_FSL_IN_DATA => DCACHE_FSL_IN_DATA,
DCACHE_FSL_IN_CONTROL => DCACHE_FSL_IN_CONTROL,
DCACHE_FSL_IN_EXISTS => DCACHE_FSL_IN_EXISTS,
DCACHE_FSL_OUT_CLK => DCACHE_FSL_OUT_CLK,
DCACHE_FSL_OUT_WRITE => DCACHE_FSL_OUT_WRITE,
DCACHE_FSL_OUT_DATA => DCACHE_FSL_OUT_DATA,
DCACHE_FSL_OUT_CONTROL => DCACHE_FSL_OUT_CONTROL,
DCACHE_FSL_OUT_FULL => DCACHE_FSL_OUT_FULL
);
end architecture STRUCTURE;
| lgpl-3.0 | d8530929cf4e104966dfed51c33c07a4 | 0.60671 | 2.748727 | false | false | false | false |
TWW12/lzw | ip_repo/axi_compression_1.0/src/input_fifo/synth/input_fifo.vhd | 2 | 38,764 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.1
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v13_1_3;
USE fifo_generator_v13_1_3.fifo_generator_v13_1_3;
ENTITY input_fifo IS
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END input_fifo;
ARCHITECTURE input_fifo_arch OF input_fifo IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF input_fifo_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v13_1_3 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_SELECT_XPM : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v13_1_3;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF input_fifo_arch: ARCHITECTURE IS "fifo_generator_v13_1_3,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF input_fifo_arch : ARCHITECTURE IS "input_fifo,fifo_generator_v13_1_3,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF input_fifo_arch: ARCHITECTURE IS "input_fifo,fifo_generator_v13_1_3,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.1,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_SELECT_XPM=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=11,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=8,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=8,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_" &
"FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=1,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=1kx18,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1023,C_PROG_FULL_THRESH_NE" &
"GATE_VAL=1022,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=11,C_RD_DEPTH=1024,C_RD_FREQ=1,C_RD_PNTR_WIDTH=10,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=1,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=11,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TY" &
"PE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C" &
"_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH" &
"=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_I" &
"NJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=1,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_" &
"PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_P" &
"ROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL" &
"_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 core_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v13_1_3
GENERIC MAP (
C_COMMON_CLOCK => 1,
C_SELECT_XPM => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 11,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 8,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 8,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 0,
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 0,
C_PRELOAD_REGS => 1,
C_PRIM_FIFO_TYPE => "1kx18",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 4,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 5,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 1023,
C_PROG_FULL_THRESH_NEGATE_VAL => 1022,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 11,
C_RD_DEPTH => 1024,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 10,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 1,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 11,
C_WR_DEPTH => 1024,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 10,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 1,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => clk,
rst => '0',
srst => srst,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END input_fifo_arch;
| unlicense | 00fd779a4395f5bb60cc13226d97edf2 | 0.627077 | 2.909992 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00385.vhd | 1 | 69,451 | -- NEED RESULT: ARCH00385.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00385.P2: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00385.P3: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00385.P4: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00385.P5: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00385.P6: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00385.P7: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00385.P8: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00385.P9: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00385.P10: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00385: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00385: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: P10: Inertial transactions completed entirely passed
-- NEED RESULT: P9: Inertial transactions completed entirely passed
-- NEED RESULT: P8: Inertial transactions completed entirely passed
-- NEED RESULT: P7: Inertial transactions completed entirely passed
-- NEED RESULT: P6: Inertial transactions completed entirely passed
-- NEED RESULT: P5: Inertial transactions completed entirely passed
-- NEED RESULT: P4: Inertial transactions completed entirely passed
-- NEED RESULT: P3: Inertial transactions completed entirely passed
-- NEED RESULT: P2: Inertial transactions completed entirely passed
-- NEED RESULT: P1: Inertial transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00385
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (3)
-- 9.5.2 (1)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00385(ARCH00385)
-- ENT00385_Test_Bench(ARCH00385_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00385 is
end ENT00385 ;
--
--
architecture ARCH00385 of ENT00385 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_boolean_vector : chk_sig_type := -1 ;
signal chk_st_severity_level_vector : chk_sig_type := -1 ;
signal chk_st_string : chk_sig_type := -1 ;
signal chk_st_enum1_vector : chk_sig_type := -1 ;
signal chk_st_integer_vector : chk_sig_type := -1 ;
signal chk_st_time_vector : chk_sig_type := -1 ;
signal chk_st_real_vector : chk_sig_type := -1 ;
signal chk_st_rec1_vector : chk_sig_type := -1 ;
signal chk_st_arr2_vector : chk_sig_type := -1 ;
signal chk_st_arr2 : chk_sig_type := -1 ;
--
subtype chk_time_type is Time ;
signal s_st_boolean_vector_savt : chk_time_type := 0 ns ;
signal s_st_severity_level_vector_savt : chk_time_type := 0 ns ;
signal s_st_string_savt : chk_time_type := 0 ns ;
signal s_st_enum1_vector_savt : chk_time_type := 0 ns ;
signal s_st_integer_vector_savt : chk_time_type := 0 ns ;
signal s_st_time_vector_savt : chk_time_type := 0 ns ;
signal s_st_real_vector_savt : chk_time_type := 0 ns ;
signal s_st_rec1_vector_savt : chk_time_type := 0 ns ;
signal s_st_arr2_vector_savt : chk_time_type := 0 ns ;
signal s_st_arr2_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_boolean_vector_cnt : chk_cnt_type := 0 ;
signal s_st_severity_level_vector_cnt : chk_cnt_type := 0 ;
signal s_st_string_cnt : chk_cnt_type := 0 ;
signal s_st_enum1_vector_cnt : chk_cnt_type := 0 ;
signal s_st_integer_vector_cnt : chk_cnt_type := 0 ;
signal s_st_time_vector_cnt : chk_cnt_type := 0 ;
signal s_st_real_vector_cnt : chk_cnt_type := 0 ;
signal s_st_rec1_vector_cnt : chk_cnt_type := 0 ;
signal s_st_arr2_vector_cnt : chk_cnt_type := 0 ;
signal s_st_arr2_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 6 ;
signal st_boolean_vector_select : select_type := 1 ;
signal st_severity_level_vector_select : select_type := 1 ;
signal st_string_select : select_type := 1 ;
signal st_enum1_vector_select : select_type := 1 ;
signal st_integer_vector_select : select_type := 1 ;
signal st_time_vector_select : select_type := 1 ;
signal st_real_vector_select : select_type := 1 ;
signal st_rec1_vector_select : select_type := 1 ;
signal st_arr2_vector_select : select_type := 1 ;
signal st_arr2_select : select_type := 1 ;
--
signal s_st_boolean_vector : st_boolean_vector
:= c_st_boolean_vector_1 ;
signal s_st_severity_level_vector : st_severity_level_vector
:= c_st_severity_level_vector_1 ;
signal s_st_string : st_string
:= c_st_string_1 ;
signal s_st_enum1_vector : st_enum1_vector
:= c_st_enum1_vector_1 ;
signal s_st_integer_vector : st_integer_vector
:= c_st_integer_vector_1 ;
signal s_st_time_vector : st_time_vector
:= c_st_time_vector_1 ;
signal s_st_real_vector : st_real_vector
:= c_st_real_vector_1 ;
signal s_st_rec1_vector : st_rec1_vector
:= c_st_rec1_vector_1 ;
signal s_st_arr2_vector : st_arr2_vector
:= c_st_arr2_vector_1 ;
signal s_st_arr2 : st_arr2
:= c_st_arr2_1 ;
--
begin
CHG1 :
process
variable correct : boolean ;
begin
case s_st_boolean_vector_cnt is
when 0
=> null ;
-- s_st_boolean_vector(lowb) <=
-- c_st_boolean_vector_2(lowb) after 10 ns,
-- c_st_boolean_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_boolean_vector(lowb) =
c_st_boolean_vector_2(lowb) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_1(lowb) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385.P1" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_boolean_vector_select <= transport 2 ;
-- s_st_boolean_vector(lowb) <=
-- c_st_boolean_vector_2(lowb) after 10 ns ,
-- c_st_boolean_vector_1(lowb) after 20 ns ,
-- c_st_boolean_vector_2(lowb) after 30 ns ,
-- c_st_boolean_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_boolean_vector(lowb) =
c_st_boolean_vector_2(lowb) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
st_boolean_vector_select <= transport 3 ;
-- s_st_boolean_vector(lowb) <=
-- c_st_boolean_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_1(lowb) and
(s_st_boolean_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_boolean_vector_select <= transport 4 ;
-- s_st_boolean_vector(lowb) <=
-- c_st_boolean_vector_1(lowb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_1(lowb) and
(s_st_boolean_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_boolean_vector_select <= transport 5 ;
-- s_st_boolean_vector(lowb) <=
-- c_st_boolean_vector_2(lowb) after 10 ns ,
-- c_st_boolean_vector_1(lowb) after 20 ns ,
-- c_st_boolean_vector_2(lowb) after 30 ns ,
-- c_st_boolean_vector_1(lowb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_2(lowb) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_boolean_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_boolean_vector(lowb) <=
-- c_st_boolean_vector_1(lowb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_1(lowb) and
(s_st_boolean_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_1(lowb) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00385" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_boolean_vector_savt <= transport Std.Standard.Now ;
chk_st_boolean_vector <= transport s_st_boolean_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_boolean_vector_cnt <= transport s_st_boolean_vector_cnt + 1 ;
wait until (not s_st_boolean_vector(lowb)'Quiet) and
(s_st_boolean_vector_savt /= Std.Standard.Now) ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_boolean_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions completed entirely",
chk_st_boolean_vector = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
with st_boolean_vector_select select
s_st_boolean_vector(lowb) <=
c_st_boolean_vector_2(lowb) after 10 ns,
c_st_boolean_vector_1(lowb) after 20 ns
when 1,
--
c_st_boolean_vector_2(lowb) after 10 ns ,
c_st_boolean_vector_1(lowb) after 20 ns ,
c_st_boolean_vector_2(lowb) after 30 ns ,
c_st_boolean_vector_1(lowb) after 40 ns
when 2,
--
c_st_boolean_vector_1(lowb) after 5 ns
when 3,
--
c_st_boolean_vector_1(lowb) after 100 ns
when 4,
--
c_st_boolean_vector_2(lowb) after 10 ns ,
c_st_boolean_vector_1(lowb) after 20 ns ,
c_st_boolean_vector_2(lowb) after 30 ns ,
c_st_boolean_vector_1(lowb) after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_boolean_vector_1(lowb) after 40 ns when 6 ;
--
CHG2 :
process
variable correct : boolean ;
begin
case s_st_severity_level_vector_cnt is
when 0
=> null ;
-- s_st_severity_level_vector(lowb) <=
-- c_st_severity_level_vector_2(lowb) after 10 ns,
-- c_st_severity_level_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_2(lowb) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_1(lowb) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385.P2" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_severity_level_vector_select <= transport 2 ;
-- s_st_severity_level_vector(lowb) <=
-- c_st_severity_level_vector_2(lowb) after 10 ns ,
-- c_st_severity_level_vector_1(lowb) after 20 ns ,
-- c_st_severity_level_vector_2(lowb) after 30 ns ,
-- c_st_severity_level_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_2(lowb) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
st_severity_level_vector_select <= transport 3 ;
-- s_st_severity_level_vector(lowb) <=
-- c_st_severity_level_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_1(lowb) and
(s_st_severity_level_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_severity_level_vector_select <= transport 4 ;
-- s_st_severity_level_vector(lowb) <=
-- c_st_severity_level_vector_1(lowb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_1(lowb) and
(s_st_severity_level_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_severity_level_vector_select <= transport 5 ;
-- s_st_severity_level_vector(lowb) <=
-- c_st_severity_level_vector_2(lowb) after 10 ns ,
-- c_st_severity_level_vector_1(lowb) after 20 ns ,
-- c_st_severity_level_vector_2(lowb) after 30 ns ,
-- c_st_severity_level_vector_1(lowb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_2(lowb) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_severity_level_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_severity_level_vector(lowb) <=
-- c_st_severity_level_vector_1(lowb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_1(lowb) and
(s_st_severity_level_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_1(lowb) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00385" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_severity_level_vector_savt <= transport Std.Standard.Now ;
chk_st_severity_level_vector <= transport s_st_severity_level_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_severity_level_vector_cnt <= transport s_st_severity_level_vector_cnt
+ 1 ;
wait until (not s_st_severity_level_vector(lowb)'Quiet) and
(s_st_severity_level_vector_savt /= Std.Standard.Now) ;
--
end process CHG2 ;
--
PGEN_CHKP_2 :
process ( chk_st_severity_level_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions completed entirely",
chk_st_severity_level_vector = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
with st_severity_level_vector_select select
s_st_severity_level_vector(lowb) <=
c_st_severity_level_vector_2(lowb) after 10 ns,
c_st_severity_level_vector_1(lowb) after 20 ns
when 1,
--
c_st_severity_level_vector_2(lowb) after 10 ns ,
c_st_severity_level_vector_1(lowb) after 20 ns ,
c_st_severity_level_vector_2(lowb) after 30 ns ,
c_st_severity_level_vector_1(lowb) after 40 ns
when 2,
--
c_st_severity_level_vector_1(lowb) after 5 ns
when 3,
--
c_st_severity_level_vector_1(lowb) after 100 ns
when 4,
--
c_st_severity_level_vector_2(lowb) after 10 ns ,
c_st_severity_level_vector_1(lowb) after 20 ns ,
c_st_severity_level_vector_2(lowb) after 30 ns ,
c_st_severity_level_vector_1(lowb) after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_severity_level_vector_1(lowb) after 40 ns when 6 ;
--
CHG3 :
process
variable correct : boolean ;
begin
case s_st_string_cnt is
when 0
=> null ;
-- s_st_string(highb) <=
-- c_st_string_2(highb) after 10 ns,
-- c_st_string_1(highb) after 20 ns ;
--
when 1
=> correct :=
s_st_string(highb) =
c_st_string_2(highb) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_string(highb) =
c_st_string_1(highb) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385.P3" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_string_select <= transport 2 ;
-- s_st_string(highb) <=
-- c_st_string_2(highb) after 10 ns ,
-- c_st_string_1(highb) after 20 ns ,
-- c_st_string_2(highb) after 30 ns ,
-- c_st_string_1(highb) after 40 ns ;
--
when 3
=> correct :=
s_st_string(highb) =
c_st_string_2(highb) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
st_string_select <= transport 3 ;
-- s_st_string(highb) <=
-- c_st_string_1(highb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_string(highb) =
c_st_string_1(highb) and
(s_st_string_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_string_select <= transport 4 ;
-- s_st_string(highb) <=
-- c_st_string_1(highb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_string(highb) =
c_st_string_1(highb) and
(s_st_string_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_string_select <= transport 5 ;
-- s_st_string(highb) <=
-- c_st_string_2(highb) after 10 ns ,
-- c_st_string_1(highb) after 20 ns ,
-- c_st_string_2(highb) after 30 ns ,
-- c_st_string_1(highb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_string(highb) =
c_st_string_2(highb) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_string_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_string(highb) <=
-- c_st_string_1(highb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_string(highb) =
c_st_string_1(highb) and
(s_st_string_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_string(highb) =
c_st_string_1(highb) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00385" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_string_savt <= transport Std.Standard.Now ;
chk_st_string <= transport s_st_string_cnt
after (1 us - Std.Standard.Now) ;
s_st_string_cnt <= transport s_st_string_cnt + 1 ;
wait until (not s_st_string(highb)'Quiet) and
(s_st_string_savt /= Std.Standard.Now) ;
--
end process CHG3 ;
--
PGEN_CHKP_3 :
process ( chk_st_string )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions completed entirely",
chk_st_string = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
with st_string_select select
s_st_string(highb) <=
c_st_string_2(highb) after 10 ns,
c_st_string_1(highb) after 20 ns
when 1,
--
c_st_string_2(highb) after 10 ns ,
c_st_string_1(highb) after 20 ns ,
c_st_string_2(highb) after 30 ns ,
c_st_string_1(highb) after 40 ns
when 2,
--
c_st_string_1(highb) after 5 ns
when 3,
--
c_st_string_1(highb) after 100 ns
when 4,
--
c_st_string_2(highb) after 10 ns ,
c_st_string_1(highb) after 20 ns ,
c_st_string_2(highb) after 30 ns ,
c_st_string_1(highb) after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_string_1(highb) after 40 ns when 6 ;
--
CHG4 :
process
variable correct : boolean ;
begin
case s_st_enum1_vector_cnt is
when 0
=> null ;
-- s_st_enum1_vector(highb) <=
-- c_st_enum1_vector_2(highb) after 10 ns,
-- c_st_enum1_vector_1(highb) after 20 ns ;
--
when 1
=> correct :=
s_st_enum1_vector(highb) =
c_st_enum1_vector_2(highb) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_1(highb) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385.P4" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_enum1_vector_select <= transport 2 ;
-- s_st_enum1_vector(highb) <=
-- c_st_enum1_vector_2(highb) after 10 ns ,
-- c_st_enum1_vector_1(highb) after 20 ns ,
-- c_st_enum1_vector_2(highb) after 30 ns ,
-- c_st_enum1_vector_1(highb) after 40 ns ;
--
when 3
=> correct :=
s_st_enum1_vector(highb) =
c_st_enum1_vector_2(highb) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
st_enum1_vector_select <= transport 3 ;
-- s_st_enum1_vector(highb) <=
-- c_st_enum1_vector_1(highb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_1(highb) and
(s_st_enum1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_enum1_vector_select <= transport 4 ;
-- s_st_enum1_vector(highb) <=
-- c_st_enum1_vector_1(highb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_1(highb) and
(s_st_enum1_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_enum1_vector_select <= transport 5 ;
-- s_st_enum1_vector(highb) <=
-- c_st_enum1_vector_2(highb) after 10 ns ,
-- c_st_enum1_vector_1(highb) after 20 ns ,
-- c_st_enum1_vector_2(highb) after 30 ns ,
-- c_st_enum1_vector_1(highb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_2(highb) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_enum1_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_enum1_vector(highb) <=
-- c_st_enum1_vector_1(highb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_1(highb) and
(s_st_enum1_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_1(highb) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00385" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_enum1_vector_savt <= transport Std.Standard.Now ;
chk_st_enum1_vector <= transport s_st_enum1_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_enum1_vector_cnt <= transport s_st_enum1_vector_cnt + 1 ;
wait until (not s_st_enum1_vector(highb)'Quiet) and
(s_st_enum1_vector_savt /= Std.Standard.Now) ;
--
end process CHG4 ;
--
PGEN_CHKP_4 :
process ( chk_st_enum1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Inertial transactions completed entirely",
chk_st_enum1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
--
with st_enum1_vector_select select
s_st_enum1_vector(highb) <=
c_st_enum1_vector_2(highb) after 10 ns,
c_st_enum1_vector_1(highb) after 20 ns
when 1,
--
c_st_enum1_vector_2(highb) after 10 ns ,
c_st_enum1_vector_1(highb) after 20 ns ,
c_st_enum1_vector_2(highb) after 30 ns ,
c_st_enum1_vector_1(highb) after 40 ns
when 2,
--
c_st_enum1_vector_1(highb) after 5 ns
when 3,
--
c_st_enum1_vector_1(highb) after 100 ns
when 4,
--
c_st_enum1_vector_2(highb) after 10 ns ,
c_st_enum1_vector_1(highb) after 20 ns ,
c_st_enum1_vector_2(highb) after 30 ns ,
c_st_enum1_vector_1(highb) after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_enum1_vector_1(highb) after 40 ns when 6 ;
--
CHG5 :
process
variable correct : boolean ;
begin
case s_st_integer_vector_cnt is
when 0
=> null ;
-- s_st_integer_vector(lowb) <=
-- c_st_integer_vector_2(lowb) after 10 ns,
-- c_st_integer_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_integer_vector(lowb) =
c_st_integer_vector_2(lowb) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_1(lowb) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385.P5" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_integer_vector_select <= transport 2 ;
-- s_st_integer_vector(lowb) <=
-- c_st_integer_vector_2(lowb) after 10 ns ,
-- c_st_integer_vector_1(lowb) after 20 ns ,
-- c_st_integer_vector_2(lowb) after 30 ns ,
-- c_st_integer_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_integer_vector(lowb) =
c_st_integer_vector_2(lowb) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
st_integer_vector_select <= transport 3 ;
-- s_st_integer_vector(lowb) <=
-- c_st_integer_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_1(lowb) and
(s_st_integer_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_integer_vector_select <= transport 4 ;
-- s_st_integer_vector(lowb) <=
-- c_st_integer_vector_1(lowb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_1(lowb) and
(s_st_integer_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_integer_vector_select <= transport 5 ;
-- s_st_integer_vector(lowb) <=
-- c_st_integer_vector_2(lowb) after 10 ns ,
-- c_st_integer_vector_1(lowb) after 20 ns ,
-- c_st_integer_vector_2(lowb) after 30 ns ,
-- c_st_integer_vector_1(lowb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_2(lowb) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_integer_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_integer_vector(lowb) <=
-- c_st_integer_vector_1(lowb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_1(lowb) and
(s_st_integer_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_1(lowb) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00385" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_integer_vector_savt <= transport Std.Standard.Now ;
chk_st_integer_vector <= transport s_st_integer_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_integer_vector_cnt <= transport s_st_integer_vector_cnt + 1 ;
wait until (not s_st_integer_vector(lowb)'Quiet) and
(s_st_integer_vector_savt /= Std.Standard.Now) ;
--
end process CHG5 ;
--
PGEN_CHKP_5 :
process ( chk_st_integer_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Inertial transactions completed entirely",
chk_st_integer_vector = 8 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
--
with st_integer_vector_select select
s_st_integer_vector(lowb) <=
c_st_integer_vector_2(lowb) after 10 ns,
c_st_integer_vector_1(lowb) after 20 ns
when 1,
--
c_st_integer_vector_2(lowb) after 10 ns ,
c_st_integer_vector_1(lowb) after 20 ns ,
c_st_integer_vector_2(lowb) after 30 ns ,
c_st_integer_vector_1(lowb) after 40 ns
when 2,
--
c_st_integer_vector_1(lowb) after 5 ns
when 3,
--
c_st_integer_vector_1(lowb) after 100 ns
when 4,
--
c_st_integer_vector_2(lowb) after 10 ns ,
c_st_integer_vector_1(lowb) after 20 ns ,
c_st_integer_vector_2(lowb) after 30 ns ,
c_st_integer_vector_1(lowb) after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_integer_vector_1(lowb) after 40 ns when 6 ;
--
CHG6 :
process
variable correct : boolean ;
begin
case s_st_time_vector_cnt is
when 0
=> null ;
-- s_st_time_vector(lowb) <=
-- c_st_time_vector_2(lowb) after 10 ns,
-- c_st_time_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_time_vector(lowb) =
c_st_time_vector_2(lowb) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_1(lowb) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385.P6" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_time_vector_select <= transport 2 ;
-- s_st_time_vector(lowb) <=
-- c_st_time_vector_2(lowb) after 10 ns ,
-- c_st_time_vector_1(lowb) after 20 ns ,
-- c_st_time_vector_2(lowb) after 30 ns ,
-- c_st_time_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_time_vector(lowb) =
c_st_time_vector_2(lowb) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
st_time_vector_select <= transport 3 ;
-- s_st_time_vector(lowb) <=
-- c_st_time_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_1(lowb) and
(s_st_time_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_time_vector_select <= transport 4 ;
-- s_st_time_vector(lowb) <=
-- c_st_time_vector_1(lowb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_1(lowb) and
(s_st_time_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_time_vector_select <= transport 5 ;
-- s_st_time_vector(lowb) <=
-- c_st_time_vector_2(lowb) after 10 ns ,
-- c_st_time_vector_1(lowb) after 20 ns ,
-- c_st_time_vector_2(lowb) after 30 ns ,
-- c_st_time_vector_1(lowb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_2(lowb) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_time_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_time_vector(lowb) <=
-- c_st_time_vector_1(lowb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_1(lowb) and
(s_st_time_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_1(lowb) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00385" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_time_vector_savt <= transport Std.Standard.Now ;
chk_st_time_vector <= transport s_st_time_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_time_vector_cnt <= transport s_st_time_vector_cnt + 1 ;
wait until (not s_st_time_vector(lowb)'Quiet) and
(s_st_time_vector_savt /= Std.Standard.Now) ;
--
end process CHG6 ;
--
PGEN_CHKP_6 :
process ( chk_st_time_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Inertial transactions completed entirely",
chk_st_time_vector = 8 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
--
with st_time_vector_select select
s_st_time_vector(lowb) <=
c_st_time_vector_2(lowb) after 10 ns,
c_st_time_vector_1(lowb) after 20 ns
when 1,
--
c_st_time_vector_2(lowb) after 10 ns ,
c_st_time_vector_1(lowb) after 20 ns ,
c_st_time_vector_2(lowb) after 30 ns ,
c_st_time_vector_1(lowb) after 40 ns
when 2,
--
c_st_time_vector_1(lowb) after 5 ns
when 3,
--
c_st_time_vector_1(lowb) after 100 ns
when 4,
--
c_st_time_vector_2(lowb) after 10 ns ,
c_st_time_vector_1(lowb) after 20 ns ,
c_st_time_vector_2(lowb) after 30 ns ,
c_st_time_vector_1(lowb) after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_time_vector_1(lowb) after 40 ns when 6 ;
--
CHG7 :
process
variable correct : boolean ;
begin
case s_st_real_vector_cnt is
when 0
=> null ;
-- s_st_real_vector(highb) <=
-- c_st_real_vector_2(highb) after 10 ns,
-- c_st_real_vector_1(highb) after 20 ns ;
--
when 1
=> correct :=
s_st_real_vector(highb) =
c_st_real_vector_2(highb) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_1(highb) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385.P7" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_real_vector_select <= transport 2 ;
-- s_st_real_vector(highb) <=
-- c_st_real_vector_2(highb) after 10 ns ,
-- c_st_real_vector_1(highb) after 20 ns ,
-- c_st_real_vector_2(highb) after 30 ns ,
-- c_st_real_vector_1(highb) after 40 ns ;
--
when 3
=> correct :=
s_st_real_vector(highb) =
c_st_real_vector_2(highb) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
st_real_vector_select <= transport 3 ;
-- s_st_real_vector(highb) <=
-- c_st_real_vector_1(highb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_1(highb) and
(s_st_real_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_real_vector_select <= transport 4 ;
-- s_st_real_vector(highb) <=
-- c_st_real_vector_1(highb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_1(highb) and
(s_st_real_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_real_vector_select <= transport 5 ;
-- s_st_real_vector(highb) <=
-- c_st_real_vector_2(highb) after 10 ns ,
-- c_st_real_vector_1(highb) after 20 ns ,
-- c_st_real_vector_2(highb) after 30 ns ,
-- c_st_real_vector_1(highb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_2(highb) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_real_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_real_vector(highb) <=
-- c_st_real_vector_1(highb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_1(highb) and
(s_st_real_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_1(highb) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00385" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_real_vector_savt <= transport Std.Standard.Now ;
chk_st_real_vector <= transport s_st_real_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_real_vector_cnt <= transport s_st_real_vector_cnt + 1 ;
wait until (not s_st_real_vector(highb)'Quiet) and
(s_st_real_vector_savt /= Std.Standard.Now) ;
--
end process CHG7 ;
--
PGEN_CHKP_7 :
process ( chk_st_real_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Inertial transactions completed entirely",
chk_st_real_vector = 8 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
--
with st_real_vector_select select
s_st_real_vector(highb) <=
c_st_real_vector_2(highb) after 10 ns,
c_st_real_vector_1(highb) after 20 ns
when 1,
--
c_st_real_vector_2(highb) after 10 ns ,
c_st_real_vector_1(highb) after 20 ns ,
c_st_real_vector_2(highb) after 30 ns ,
c_st_real_vector_1(highb) after 40 ns
when 2,
--
c_st_real_vector_1(highb) after 5 ns
when 3,
--
c_st_real_vector_1(highb) after 100 ns
when 4,
--
c_st_real_vector_2(highb) after 10 ns ,
c_st_real_vector_1(highb) after 20 ns ,
c_st_real_vector_2(highb) after 30 ns ,
c_st_real_vector_1(highb) after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_real_vector_1(highb) after 40 ns when 6 ;
--
CHG8 :
process
variable correct : boolean ;
begin
case s_st_rec1_vector_cnt is
when 0
=> null ;
-- s_st_rec1_vector(highb) <=
-- c_st_rec1_vector_2(highb) after 10 ns,
-- c_st_rec1_vector_1(highb) after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_vector(highb) =
c_st_rec1_vector_2(highb) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_1(highb) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385.P8" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec1_vector_select <= transport 2 ;
-- s_st_rec1_vector(highb) <=
-- c_st_rec1_vector_2(highb) after 10 ns ,
-- c_st_rec1_vector_1(highb) after 20 ns ,
-- c_st_rec1_vector_2(highb) after 30 ns ,
-- c_st_rec1_vector_1(highb) after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_vector(highb) =
c_st_rec1_vector_2(highb) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
st_rec1_vector_select <= transport 3 ;
-- s_st_rec1_vector(highb) <=
-- c_st_rec1_vector_1(highb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_1(highb) and
(s_st_rec1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_vector_select <= transport 4 ;
-- s_st_rec1_vector(highb) <=
-- c_st_rec1_vector_1(highb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_1(highb) and
(s_st_rec1_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec1_vector_select <= transport 5 ;
-- s_st_rec1_vector(highb) <=
-- c_st_rec1_vector_2(highb) after 10 ns ,
-- c_st_rec1_vector_1(highb) after 20 ns ,
-- c_st_rec1_vector_2(highb) after 30 ns ,
-- c_st_rec1_vector_1(highb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_2(highb) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec1_vector(highb) <=
-- c_st_rec1_vector_1(highb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_1(highb) and
(s_st_rec1_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_1(highb) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00385" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec1_vector_savt <= transport Std.Standard.Now ;
chk_st_rec1_vector <= transport s_st_rec1_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec1_vector_cnt <= transport s_st_rec1_vector_cnt + 1 ;
wait until (not s_st_rec1_vector(highb)'Quiet) and
(s_st_rec1_vector_savt /= Std.Standard.Now) ;
--
end process CHG8 ;
--
PGEN_CHKP_8 :
process ( chk_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Inertial transactions completed entirely",
chk_st_rec1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
--
with st_rec1_vector_select select
s_st_rec1_vector(highb) <=
c_st_rec1_vector_2(highb) after 10 ns,
c_st_rec1_vector_1(highb) after 20 ns
when 1,
--
c_st_rec1_vector_2(highb) after 10 ns ,
c_st_rec1_vector_1(highb) after 20 ns ,
c_st_rec1_vector_2(highb) after 30 ns ,
c_st_rec1_vector_1(highb) after 40 ns
when 2,
--
c_st_rec1_vector_1(highb) after 5 ns
when 3,
--
c_st_rec1_vector_1(highb) after 100 ns
when 4,
--
c_st_rec1_vector_2(highb) after 10 ns ,
c_st_rec1_vector_1(highb) after 20 ns ,
c_st_rec1_vector_2(highb) after 30 ns ,
c_st_rec1_vector_1(highb) after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_rec1_vector_1(highb) after 40 ns when 6 ;
--
CHG9 :
process
variable correct : boolean ;
begin
case s_st_arr2_vector_cnt is
when 0
=> null ;
-- s_st_arr2_vector(lowb) <=
-- c_st_arr2_vector_2(lowb) after 10 ns,
-- c_st_arr2_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2_vector(lowb) =
c_st_arr2_vector_2(lowb) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_1(lowb) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385.P9" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr2_vector_select <= transport 2 ;
-- s_st_arr2_vector(lowb) <=
-- c_st_arr2_vector_2(lowb) after 10 ns ,
-- c_st_arr2_vector_1(lowb) after 20 ns ,
-- c_st_arr2_vector_2(lowb) after 30 ns ,
-- c_st_arr2_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2_vector(lowb) =
c_st_arr2_vector_2(lowb) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
st_arr2_vector_select <= transport 3 ;
-- s_st_arr2_vector(lowb) <=
-- c_st_arr2_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_1(lowb) and
(s_st_arr2_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_vector_select <= transport 4 ;
-- s_st_arr2_vector(lowb) <=
-- c_st_arr2_vector_1(lowb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_1(lowb) and
(s_st_arr2_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_arr2_vector_select <= transport 5 ;
-- s_st_arr2_vector(lowb) <=
-- c_st_arr2_vector_2(lowb) after 10 ns ,
-- c_st_arr2_vector_1(lowb) after 20 ns ,
-- c_st_arr2_vector_2(lowb) after 30 ns ,
-- c_st_arr2_vector_1(lowb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_2(lowb) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_arr2_vector(lowb) <=
-- c_st_arr2_vector_1(lowb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_1(lowb) and
(s_st_arr2_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_1(lowb) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00385" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_arr2_vector_savt <= transport Std.Standard.Now ;
chk_st_arr2_vector <= transport s_st_arr2_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr2_vector_cnt <= transport s_st_arr2_vector_cnt + 1 ;
wait until (not s_st_arr2_vector(lowb)'Quiet) and
(s_st_arr2_vector_savt /= Std.Standard.Now) ;
--
end process CHG9 ;
--
PGEN_CHKP_9 :
process ( chk_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Inertial transactions completed entirely",
chk_st_arr2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
--
with st_arr2_vector_select select
s_st_arr2_vector(lowb) <=
c_st_arr2_vector_2(lowb) after 10 ns,
c_st_arr2_vector_1(lowb) after 20 ns
when 1,
--
c_st_arr2_vector_2(lowb) after 10 ns ,
c_st_arr2_vector_1(lowb) after 20 ns ,
c_st_arr2_vector_2(lowb) after 30 ns ,
c_st_arr2_vector_1(lowb) after 40 ns
when 2,
--
c_st_arr2_vector_1(lowb) after 5 ns
when 3,
--
c_st_arr2_vector_1(lowb) after 100 ns
when 4,
--
c_st_arr2_vector_2(lowb) after 10 ns ,
c_st_arr2_vector_1(lowb) after 20 ns ,
c_st_arr2_vector_2(lowb) after 30 ns ,
c_st_arr2_vector_1(lowb) after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_arr2_vector_1(lowb) after 40 ns when 6 ;
--
CHG10 :
process
variable correct : boolean ;
begin
case s_st_arr2_cnt is
when 0
=> null ;
-- s_st_arr2(highb,false) <=
-- c_st_arr2_2(highb,false) after 10 ns,
-- c_st_arr2_1(highb,false) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2(highb,false) =
c_st_arr2_2(highb,false) and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_1(highb,false) and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385.P10" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr2_select <= transport 2 ;
-- s_st_arr2(highb,false) <=
-- c_st_arr2_2(highb,false) after 10 ns ,
-- c_st_arr2_1(highb,false) after 20 ns ,
-- c_st_arr2_2(highb,false) after 30 ns ,
-- c_st_arr2_1(highb,false) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2(highb,false) =
c_st_arr2_2(highb,false) and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
st_arr2_select <= transport 3 ;
-- s_st_arr2(highb,false) <=
-- c_st_arr2_1(highb,false) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_1(highb,false) and
(s_st_arr2_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_select <= transport 4 ;
-- s_st_arr2(highb,false) <=
-- c_st_arr2_1(highb,false) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_1(highb,false) and
(s_st_arr2_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_arr2_select <= transport 5 ;
-- s_st_arr2(highb,false) <=
-- c_st_arr2_2(highb,false) after 10 ns ,
-- c_st_arr2_1(highb,false) after 20 ns ,
-- c_st_arr2_2(highb,false) after 30 ns ,
-- c_st_arr2_1(highb,false) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_2(highb,false) and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_arr2(highb,false) <=
-- c_st_arr2_1(highb,false) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_1(highb,false) and
(s_st_arr2_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_1(highb,false) and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00385" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00385" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_arr2_savt <= transport Std.Standard.Now ;
chk_st_arr2 <= transport s_st_arr2_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr2_cnt <= transport s_st_arr2_cnt + 1 ;
wait until (not s_st_arr2(highb,false)'Quiet) and
(s_st_arr2_savt /= Std.Standard.Now) ;
--
end process CHG10 ;
--
PGEN_CHKP_10 :
process ( chk_st_arr2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Inertial transactions completed entirely",
chk_st_arr2 = 8 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
--
with st_arr2_select select
s_st_arr2(highb,false) <=
c_st_arr2_2(highb,false) after 10 ns,
c_st_arr2_1(highb,false) after 20 ns
when 1,
--
c_st_arr2_2(highb,false) after 10 ns ,
c_st_arr2_1(highb,false) after 20 ns ,
c_st_arr2_2(highb,false) after 30 ns ,
c_st_arr2_1(highb,false) after 40 ns
when 2,
--
c_st_arr2_1(highb,false) after 5 ns
when 3,
--
c_st_arr2_1(highb,false) after 100 ns
when 4,
--
c_st_arr2_2(highb,false) after 10 ns ,
c_st_arr2_1(highb,false) after 20 ns ,
c_st_arr2_2(highb,false) after 30 ns ,
c_st_arr2_1(highb,false) after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_arr2_1(highb,false) after 40 ns when 6 ;
--
end ARCH00385 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00385_Test_Bench is
end ENT00385_Test_Bench ;
--
--
architecture ARCH00385_Test_Bench of ENT00385_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00385 ( ARCH00385 ) ;
begin
CIS1 : UUT
;
end block L1 ;
end ARCH00385_Test_Bench ;
| gpl-3.0 | f76c10155c9fbb2eef3e51a7bc67b3ee | 0.510245 | 3.506564 | false | false | false | false |
wsoltys/AtomFpga | src/T6502/T65_Pack.vhd | 1 | 4,662 | -- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 Bugfixes by ehenciak added
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- 65xx compatible microprocessor core
--
-- Version : 0246
--
-- Copyright (c) 2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t65/
--
-- Limitations :
--
-- File history :
--
library IEEE;
use IEEE.std_logic_1164.all;
package T65_Pack is
constant Flag_C : integer := 0;
constant Flag_Z : integer := 1;
constant Flag_I : integer := 2;
constant Flag_D : integer := 3;
constant Flag_B : integer := 4;
constant Flag_1 : integer := 5;
constant Flag_V : integer := 6;
constant Flag_N : integer := 7;
component T65_MCode
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816
IR : in std_logic_vector(7 downto 0);
MCycle : in std_logic_vector(2 downto 0);
P : in std_logic_vector(7 downto 0);
LCycle : out std_logic_vector(2 downto 0);
ALU_Op : out std_logic_vector(3 downto 0);
Set_BusA_To : out std_logic_vector(2 downto 0); -- DI,A,X,Y,S,P
Set_Addr_To : out std_logic_vector(1 downto 0); -- PC Adder,S,AD,BA
Write_Data : out std_logic_vector(2 downto 0); -- DL,A,X,Y,S,P,PCL,PCH
Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel
BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj
BreakAtNA : out std_logic;
ADAdd : out std_logic;
AddY : out std_logic;
PCAdd : out std_logic;
Inc_S : out std_logic;
Dec_S : out std_logic;
LDA : out std_logic;
LDP : out std_logic;
LDX : out std_logic;
LDY : out std_logic;
LDS : out std_logic;
LDDI : out std_logic;
LDALU : out std_logic;
LDAD : out std_logic;
LDBAL : out std_logic;
LDBAH : out std_logic;
SaveP : out std_logic;
Write : out std_logic
);
end component;
component T65_ALU
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816
Op : in std_logic_vector(3 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
P_In : in std_logic_vector(7 downto 0);
P_Out : out std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0)
);
end component;
end;
| apache-2.0 | 966f7ab28099b45894f592362fed1e41 | 0.60296 | 3.846535 | false | false | false | false |
jairov4/accel-oil | impl/impl_test_single/simulation/behavioral/nfa_accept_samples_generic_hw_top_v1_01_a/nfa_accept_samples_generic_hw_mul_16ns_8ns_24_2/_primary.vhd | 1 | 1,041 | library verilog;
use verilog.vl_types.all;
entity nfa_accept_samples_generic_hw_mul_16ns_8ns_24_2 is
generic(
ID : integer := 1;
NUM_STAGE : integer := 1;
din0_WIDTH : integer := 1;
din1_WIDTH : integer := 1;
dout_WIDTH : integer := 1
);
port(
clk : in vl_logic;
reset : in vl_logic;
ce : in vl_logic;
din0 : in vl_logic_vector;
din1 : in vl_logic_vector;
dout : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of ID : constant is 1;
attribute mti_svvh_generic_type of NUM_STAGE : constant is 1;
attribute mti_svvh_generic_type of din0_WIDTH : constant is 1;
attribute mti_svvh_generic_type of din1_WIDTH : constant is 1;
attribute mti_svvh_generic_type of dout_WIDTH : constant is 1;
end nfa_accept_samples_generic_hw_mul_16ns_8ns_24_2;
| lgpl-3.0 | 3728adbe6747743c34172431cc92d87d | 0.552354 | 3.565068 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00238.vhd | 1 | 8,937 | -------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00238
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.1.1.2 (8)
--
-- DESIGN UNIT ORDERING:
--
-- GENERIC_STANDARD_TYPES(ARCH00238)
-- ENT00238_Test_Bench(ARCH00238_Test_Bench)
--
-- REVISION HISTORY:
--
-- 15-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES ;
use STANDARD_TYPES.test_report, STANDARD_TYPES.switch,
STANDARD_TYPES.up, STANDARD_TYPES.down, STANDARD_TYPES.toggle,
STANDARD_TYPES."=" ;
architecture ARCH00238 of GENERIC_STANDARD_TYPES is
signal i_bit_vector_1, i_bit_vector_2 : st_bit_vector
:= c_st_bit_vector_1 ;
signal i_string_1, i_string_2 : st_string
:= c_st_string_1 ;
signal i_t_rec1_1, i_t_rec1_2 : st_rec1
:= c_st_rec1_1 ;
signal i_st_rec1_1, i_st_rec1_2 : st_rec1
:= c_st_rec1_1 ;
signal i_t_rec2_1, i_t_rec2_2 : st_rec2
:= c_st_rec2_1 ;
signal i_st_rec2_1, i_st_rec2_2 : st_rec2
:= c_st_rec2_1 ;
signal i_t_rec3_1, i_t_rec3_2 : st_rec3
:= c_st_rec3_1 ;
signal i_st_rec3_1, i_st_rec3_2 : st_rec3
:= c_st_rec3_1 ;
signal i_t_arr1_1, i_t_arr1_2 : st_arr1
:= c_st_arr1_1 ;
signal i_st_arr1_1, i_st_arr1_2 : st_arr1
:= c_st_arr1_1 ;
signal i_t_arr2_1, i_t_arr2_2 : st_arr2
:= c_st_arr2_1 ;
signal i_st_arr2_1, i_st_arr2_2 : st_arr2
:= c_st_arr2_1 ;
signal i_t_arr3_1, i_t_arr3_2 : st_arr3
:= c_st_arr3_1 ;
signal i_st_arr3_1, i_st_arr3_2 : st_arr3
:= c_st_arr3_1 ;
--
begin
L1:
block
port (
toggle : buffer switch := down;
i_bit_vector_1, i_bit_vector_2 : buffer bit_vector
:= c_st_bit_vector_1
;
i_string_1, i_string_2 : buffer string
:= c_st_string_1
;
i_t_rec1_1, i_t_rec1_2 : buffer t_rec1
:= c_st_rec1_1
;
i_st_rec1_1, i_st_rec1_2 : buffer st_rec1
:= c_st_rec1_1
;
i_t_rec2_1, i_t_rec2_2 : buffer t_rec2
:= c_st_rec2_1
;
i_st_rec2_1, i_st_rec2_2 : buffer st_rec2
:= c_st_rec2_1
;
i_t_rec3_1, i_t_rec3_2 : buffer t_rec3
:= c_st_rec3_1
;
i_st_rec3_1, i_st_rec3_2 : buffer st_rec3
:= c_st_rec3_1
;
i_t_arr1_1, i_t_arr1_2 : buffer t_arr1
:= c_st_arr1_1
;
i_st_arr1_1, i_st_arr1_2 : buffer st_arr1
:= c_st_arr1_1
;
i_t_arr2_1, i_t_arr2_2 : buffer t_arr2
:= c_st_arr2_1
;
i_st_arr2_1, i_st_arr2_2 : buffer st_arr2
:= c_st_arr2_1
;
i_t_arr3_1, i_t_arr3_2 : buffer t_arr3
:= c_st_arr3_1
;
i_st_arr3_1, i_st_arr3_2 : buffer st_arr3
:= c_st_arr3_1
) ;
port map (
toggle ,
i_bit_vector_1, i_bit_vector_2,
i_string_1, i_string_2,
i_t_rec1_1, i_t_rec1_2,
i_st_rec1_1, i_st_rec1_2,
i_t_rec2_1, i_t_rec2_2,
i_st_rec2_1, i_st_rec2_2,
i_t_rec3_1, i_t_rec3_2,
i_st_rec3_1, i_st_rec3_2,
i_t_arr1_1, i_t_arr1_2,
i_st_arr1_1, i_st_arr1_2,
i_t_arr2_1, i_t_arr2_2,
i_st_arr2_1, i_st_arr2_2,
i_t_arr3_1, i_t_arr3_2,
i_st_arr3_1, i_st_arr3_2
) ;
--
begin
process
variable correct : boolean := true ;
begin
correct := correct and i_bit_vector_1 = c_st_bit_vector_1
and i_bit_vector_2 = c_st_bit_vector_1 ;
correct := correct and i_string_1 = c_st_string_1
and i_string_2 = c_st_string_1 ;
correct := correct and i_t_rec1_1 = c_st_rec1_1
and i_t_rec1_2 = c_st_rec1_1 ;
correct := correct and i_st_rec1_1 = c_st_rec1_1
and i_st_rec1_2 = c_st_rec1_1 ;
correct := correct and i_t_rec2_1 = c_st_rec2_1
and i_t_rec2_2 = c_st_rec2_1 ;
correct := correct and i_st_rec2_1 = c_st_rec2_1
and i_st_rec2_2 = c_st_rec2_1 ;
correct := correct and i_t_rec3_1 = c_st_rec3_1
and i_t_rec3_2 = c_st_rec3_1 ;
correct := correct and i_st_rec3_1 = c_st_rec3_1
and i_st_rec3_2 = c_st_rec3_1 ;
correct := correct and i_t_arr1_1 = c_st_arr1_1
and i_t_arr1_2 = c_st_arr1_1 ;
correct := correct and i_st_arr1_1 = c_st_arr1_1
and i_st_arr1_2 = c_st_arr1_1 ;
correct := correct and i_t_arr2_1 = c_st_arr2_1
and i_t_arr2_2 = c_st_arr2_1 ;
correct := correct and i_st_arr2_1 = c_st_arr2_1
and i_st_arr2_2 = c_st_arr2_1 ;
correct := correct and i_t_arr3_1 = c_st_arr3_1
and i_t_arr3_2 = c_st_arr3_1 ;
correct := correct and i_st_arr3_1 = c_st_arr3_1
and i_st_arr3_2 = c_st_arr3_1 ;
--
test_report ( "ENT00238" ,
"Associated composite buffer ports with generic subtypes" ,
correct) ;
--
toggle <= up ;
i_bit_vector_1 <= c_st_bit_vector_2 ;
i_bit_vector_2 <= c_st_bit_vector_2 ;
i_string_1 <= c_st_string_2 ;
i_string_2 <= c_st_string_2 ;
i_t_rec1_1 <= c_st_rec1_2 ;
i_t_rec1_2 <= c_st_rec1_2 ;
i_st_rec1_1 <= c_st_rec1_2 ;
i_st_rec1_2 <= c_st_rec1_2 ;
i_t_rec2_1 <= c_st_rec2_2 ;
i_t_rec2_2 <= c_st_rec2_2 ;
i_st_rec2_1 <= c_st_rec2_2 ;
i_st_rec2_2 <= c_st_rec2_2 ;
i_t_rec3_1 <= c_st_rec3_2 ;
i_t_rec3_2 <= c_st_rec3_2 ;
i_st_rec3_1 <= c_st_rec3_2 ;
i_st_rec3_2 <= c_st_rec3_2 ;
i_t_arr1_1 <= c_st_arr1_2 ;
i_t_arr1_2 <= c_st_arr1_2 ;
i_st_arr1_1 <= c_st_arr1_2 ;
i_st_arr1_2 <= c_st_arr1_2 ;
i_t_arr2_1 <= c_st_arr2_2 ;
i_t_arr2_2 <= c_st_arr2_2 ;
i_st_arr2_1 <= c_st_arr2_2 ;
i_st_arr2_2 <= c_st_arr2_2 ;
i_t_arr3_1 <= c_st_arr3_2 ;
i_t_arr3_2 <= c_st_arr3_2 ;
i_st_arr3_1 <= c_st_arr3_2 ;
i_st_arr3_2 <= c_st_arr3_2 ;
wait ;
end process ;
end block L1 ;
P00238 :
process ( toggle )
variable correct : boolean := true ;
begin
if toggle = up then
correct := correct and i_bit_vector_1 = c_st_bit_vector_2
and i_bit_vector_2 = c_st_bit_vector_2 ;
correct := correct and i_string_1 = c_st_string_2
and i_string_2 = c_st_string_2 ;
correct := correct and i_t_rec1_1 = c_st_rec1_2
and i_t_rec1_2 = c_st_rec1_2 ;
correct := correct and i_st_rec1_1 = c_st_rec1_2
and i_st_rec1_2 = c_st_rec1_2 ;
correct := correct and i_t_rec2_1 = c_st_rec2_2
and i_t_rec2_2 = c_st_rec2_2 ;
correct := correct and i_st_rec2_1 = c_st_rec2_2
and i_st_rec2_2 = c_st_rec2_2 ;
correct := correct and i_t_rec3_1 = c_st_rec3_2
and i_t_rec3_2 = c_st_rec3_2 ;
correct := correct and i_st_rec3_1 = c_st_rec3_2
and i_st_rec3_2 = c_st_rec3_2 ;
correct := correct and i_t_arr1_1 = c_st_arr1_2
and i_t_arr1_2 = c_st_arr1_2 ;
correct := correct and i_st_arr1_1 = c_st_arr1_2
and i_st_arr1_2 = c_st_arr1_2 ;
correct := correct and i_t_arr2_1 = c_st_arr2_2
and i_t_arr2_2 = c_st_arr2_2 ;
correct := correct and i_st_arr2_1 = c_st_arr2_2
and i_st_arr2_2 = c_st_arr2_2 ;
correct := correct and i_t_arr3_1 = c_st_arr3_2
and i_t_arr3_2 = c_st_arr3_2 ;
correct := correct and i_st_arr3_1 = c_st_arr3_2
and i_st_arr3_2 = c_st_arr3_2 ;
end if ;
--
test_report ( "ENT00238.P00238" ,
"Associated composite buffer ports with generic subtypes",
correct) ;
end process P00238 ;
end ARCH00238 ;
--
entity ENT00238_Test_Bench is
end ENT00238_Test_Bench ;
--
architecture ARCH00238_Test_Bench of ENT00238_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00238 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00238_Test_Bench ;
| gpl-3.0 | f63cea4896427335f70cf481aeaa34af | 0.469173 | 2.612394 | false | false | false | false |
jairov4/accel-oil | solution_virtex5/syn/vhdl/nfa_accept_samples_generic_hw.vhd | 2 | 75,065 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_initials_buckets_req_din : OUT STD_LOGIC;
nfa_initials_buckets_req_full_n : IN STD_LOGIC;
nfa_initials_buckets_req_write : OUT STD_LOGIC;
nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_initials_buckets_rsp_read : OUT STD_LOGIC;
nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_req_din : OUT STD_LOGIC;
nfa_finals_buckets_req_full_n : IN STD_LOGIC;
nfa_finals_buckets_req_write : OUT STD_LOGIC;
nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_finals_buckets_rsp_read : OUT STD_LOGIC;
nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_req_din : OUT STD_LOGIC;
nfa_forward_buckets_req_full_n : IN STD_LOGIC;
nfa_forward_buckets_req_write : OUT STD_LOGIC;
nfa_forward_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_forward_buckets_rsp_read : OUT STD_LOGIC;
nfa_forward_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_symbols : IN STD_LOGIC_VECTOR (7 downto 0);
sample_buffer_req_din : OUT STD_LOGIC;
sample_buffer_req_full_n : IN STD_LOGIC;
sample_buffer_req_write : OUT STD_LOGIC;
sample_buffer_rsp_empty_n : IN STD_LOGIC;
sample_buffer_rsp_read : OUT STD_LOGIC;
sample_buffer_address : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_buffer_datain : IN STD_LOGIC_VECTOR (7 downto 0);
sample_buffer_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
sample_buffer_size : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_buffer_length : IN STD_LOGIC_VECTOR (31 downto 0);
sample_length : IN STD_LOGIC_VECTOR (15 downto 0);
indices_req_din : OUT STD_LOGIC;
indices_req_full_n : IN STD_LOGIC;
indices_req_write : OUT STD_LOGIC;
indices_rsp_empty_n : IN STD_LOGIC;
indices_rsp_read : OUT STD_LOGIC;
indices_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_datain : IN STD_LOGIC_VECTOR (55 downto 0);
indices_dataout : OUT STD_LOGIC_VECTOR (55 downto 0);
indices_size : OUT STD_LOGIC_VECTOR (31 downto 0);
i_size : IN STD_LOGIC_VECTOR (15 downto 0);
begin_index : IN STD_LOGIC_VECTOR (15 downto 0);
begin_sample : IN STD_LOGIC_VECTOR (15 downto 0);
end_index : IN STD_LOGIC_VECTOR (15 downto 0);
end_sample : IN STD_LOGIC_VECTOR (15 downto 0);
stop_on_first : IN STD_LOGIC_VECTOR (0 downto 0);
accept : IN STD_LOGIC_VECTOR (0 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of nfa_accept_samples_generic_hw is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"nfa_accept_samples_generic_hw,hls_ip_2014_1,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc5vlx50tff1136-3,HLS_INPUT_CLOCK=8.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=5.000000,HLS_SYN_LAT=53290010,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=0,HLS_SYN_LUT=0}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (5 downto 0) := "000000";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (5 downto 0) := "000001";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (5 downto 0) := "000010";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (5 downto 0) := "000011";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (5 downto 0) := "000100";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (5 downto 0) := "000101";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (5 downto 0) := "000110";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (5 downto 0) := "000111";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (5 downto 0) := "001000";
constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (5 downto 0) := "001001";
constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (5 downto 0) := "001010";
constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (5 downto 0) := "001011";
constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (5 downto 0) := "001100";
constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (5 downto 0) := "001101";
constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (5 downto 0) := "001110";
constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (5 downto 0) := "001111";
constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (5 downto 0) := "010000";
constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (5 downto 0) := "010001";
constant ap_ST_st19_fsm_18 : STD_LOGIC_VECTOR (5 downto 0) := "010010";
constant ap_ST_st20_fsm_19 : STD_LOGIC_VECTOR (5 downto 0) := "010011";
constant ap_ST_st21_fsm_20 : STD_LOGIC_VECTOR (5 downto 0) := "010100";
constant ap_ST_st22_fsm_21 : STD_LOGIC_VECTOR (5 downto 0) := "010101";
constant ap_ST_st23_fsm_22 : STD_LOGIC_VECTOR (5 downto 0) := "010110";
constant ap_ST_st24_fsm_23 : STD_LOGIC_VECTOR (5 downto 0) := "010111";
constant ap_ST_st25_fsm_24 : STD_LOGIC_VECTOR (5 downto 0) := "011000";
constant ap_ST_st26_fsm_25 : STD_LOGIC_VECTOR (5 downto 0) := "011001";
constant ap_ST_st27_fsm_26 : STD_LOGIC_VECTOR (5 downto 0) := "011010";
constant ap_ST_st28_fsm_27 : STD_LOGIC_VECTOR (5 downto 0) := "011011";
constant ap_ST_st29_fsm_28 : STD_LOGIC_VECTOR (5 downto 0) := "011100";
constant ap_ST_st30_fsm_29 : STD_LOGIC_VECTOR (5 downto 0) := "011101";
constant ap_ST_st31_fsm_30 : STD_LOGIC_VECTOR (5 downto 0) := "011110";
constant ap_ST_st32_fsm_31 : STD_LOGIC_VECTOR (5 downto 0) := "011111";
constant ap_ST_st33_fsm_32 : STD_LOGIC_VECTOR (5 downto 0) := "100000";
constant ap_ST_st34_fsm_33 : STD_LOGIC_VECTOR (5 downto 0) := "100001";
constant ap_ST_st35_fsm_34 : STD_LOGIC_VECTOR (5 downto 0) := "100010";
constant ap_ST_st36_fsm_35 : STD_LOGIC_VECTOR (5 downto 0) := "100011";
constant ap_ST_st37_fsm_36 : STD_LOGIC_VECTOR (5 downto 0) := "100100";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
constant ap_const_lv16_1 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000001";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
signal ap_CS_fsm : STD_LOGIC_VECTOR (5 downto 0) := "000000";
signal reg_515 : STD_LOGIC_VECTOR (31 downto 0);
signal stop_on_first_read_read_fu_152_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal c_load_reg_814 : STD_LOGIC_VECTOR (31 downto 0);
signal current_buckets_0_reg_823 : STD_LOGIC_VECTOR (31 downto 0);
signal current_buckets_1_reg_828 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_6_fu_551_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_6_reg_833 : STD_LOGIC_VECTOR (63 downto 0);
signal sample_buffer_addr_reg_838 : STD_LOGIC_VECTOR (31 downto 0);
signal i_fu_571_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal i_reg_847 : STD_LOGIC_VECTOR (15 downto 0);
signal p_rec_i_fu_577_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal p_rec_i_reg_852 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_7_fu_566_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sym_reg_857 : STD_LOGIC_VECTOR (7 downto 0);
signal agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_595_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal r_bit_p_bsf32_hw_fu_509_ap_return : STD_LOGIC_VECTOR (4 downto 0);
signal j_bucket_index1_ph_cast_fu_599_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bit1_ph_cast_fu_603_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_5_i_cast_fu_607_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_5_i_cast_reg_888 : STD_LOGIC_VECTOR (13 downto 0);
signal state_fu_626_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal state_reg_893 : STD_LOGIC_VECTOR (5 downto 0);
signal j_end_phi_fu_420_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_6_i_fu_645_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_6_i_reg_898 : STD_LOGIC_VECTOR (13 downto 0);
signal j_bit_reg_910 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bucket_index_reg_915 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bucket_reg_920 : STD_LOGIC_VECTOR (31 downto 0);
signal p_s_reg_925 : STD_LOGIC_VECTOR (0 downto 0);
signal next_buckets_0_1_fu_702_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal next_buckets_0_1_reg_936 : STD_LOGIC_VECTOR (31 downto 0);
signal next_buckets_1_1_fu_708_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_buckets_0_reg_946 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_buckets_1_reg_951 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_4_fu_738_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_sample_iterator_next_fu_463_ap_start : STD_LOGIC;
signal grp_sample_iterator_next_fu_463_ap_done : STD_LOGIC;
signal grp_sample_iterator_next_fu_463_ap_idle : STD_LOGIC;
signal grp_sample_iterator_next_fu_463_ap_ready : STD_LOGIC;
signal grp_sample_iterator_next_fu_463_indices_req_din : STD_LOGIC;
signal grp_sample_iterator_next_fu_463_indices_req_full_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_463_indices_req_write : STD_LOGIC;
signal grp_sample_iterator_next_fu_463_indices_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_463_indices_rsp_read : STD_LOGIC;
signal grp_sample_iterator_next_fu_463_indices_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_463_indices_datain : STD_LOGIC_VECTOR (55 downto 0);
signal grp_sample_iterator_next_fu_463_indices_dataout : STD_LOGIC_VECTOR (55 downto 0);
signal grp_sample_iterator_next_fu_463_indices_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_463_ap_ce : STD_LOGIC;
signal grp_sample_iterator_next_fu_463_i_index : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_463_i_sample : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_463_ap_return_0 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_463_ap_return_1 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_bitset_next_fu_473_ap_start : STD_LOGIC;
signal grp_bitset_next_fu_473_ap_done : STD_LOGIC;
signal grp_bitset_next_fu_473_ap_idle : STD_LOGIC;
signal grp_bitset_next_fu_473_ap_ready : STD_LOGIC;
signal grp_bitset_next_fu_473_ap_ce : STD_LOGIC;
signal grp_bitset_next_fu_473_p_read : STD_LOGIC_VECTOR (31 downto 0);
signal grp_bitset_next_fu_473_r_bit : STD_LOGIC_VECTOR (7 downto 0);
signal grp_bitset_next_fu_473_r_bucket_index : STD_LOGIC_VECTOR (7 downto 0);
signal grp_bitset_next_fu_473_r_bucket : STD_LOGIC_VECTOR (31 downto 0);
signal grp_bitset_next_fu_473_ap_return_0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_bitset_next_fu_473_ap_return_1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_bitset_next_fu_473_ap_return_2 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_bitset_next_fu_473_ap_return_3 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_sample_iterator_get_offset_fu_485_ap_start : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_485_ap_done : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_485_ap_idle : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_485_ap_ready : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_485_indices_req_din : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_485_indices_req_full_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_485_indices_req_write : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_485_indices_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_485_indices_rsp_read : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_485_indices_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_485_indices_datain : STD_LOGIC_VECTOR (55 downto 0);
signal grp_sample_iterator_get_offset_fu_485_indices_dataout : STD_LOGIC_VECTOR (55 downto 0);
signal grp_sample_iterator_get_offset_fu_485_indices_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_485_ap_ce : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_485_i_index : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_get_offset_fu_485_i_sample : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_get_offset_fu_485_sample_buffer_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_485_sample_length : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_get_offset_fu_485_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_initials_fu_497_ap_start : STD_LOGIC;
signal grp_nfa_get_initials_fu_497_ap_done : STD_LOGIC;
signal grp_nfa_get_initials_fu_497_ap_idle : STD_LOGIC;
signal grp_nfa_get_initials_fu_497_ap_ready : STD_LOGIC;
signal grp_nfa_get_initials_fu_497_ap_ce : STD_LOGIC;
signal grp_nfa_get_initials_fu_497_nfa_initials_buckets_req_din : STD_LOGIC;
signal grp_nfa_get_initials_fu_497_nfa_initials_buckets_req_full_n : STD_LOGIC;
signal grp_nfa_get_initials_fu_497_nfa_initials_buckets_req_write : STD_LOGIC;
signal grp_nfa_get_initials_fu_497_nfa_initials_buckets_rsp_empty_n : STD_LOGIC;
signal grp_nfa_get_initials_fu_497_nfa_initials_buckets_rsp_read : STD_LOGIC;
signal grp_nfa_get_initials_fu_497_nfa_initials_buckets_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_initials_fu_497_nfa_initials_buckets_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_initials_fu_497_nfa_initials_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_initials_fu_497_nfa_initials_buckets_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_initials_fu_497_ap_return_0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_initials_fu_497_ap_return_1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_finals_fu_503_ap_start : STD_LOGIC;
signal grp_nfa_get_finals_fu_503_ap_done : STD_LOGIC;
signal grp_nfa_get_finals_fu_503_ap_idle : STD_LOGIC;
signal grp_nfa_get_finals_fu_503_ap_ready : STD_LOGIC;
signal grp_nfa_get_finals_fu_503_ap_ce : STD_LOGIC;
signal grp_nfa_get_finals_fu_503_nfa_finals_buckets_req_din : STD_LOGIC;
signal grp_nfa_get_finals_fu_503_nfa_finals_buckets_req_full_n : STD_LOGIC;
signal grp_nfa_get_finals_fu_503_nfa_finals_buckets_req_write : STD_LOGIC;
signal grp_nfa_get_finals_fu_503_nfa_finals_buckets_rsp_empty_n : STD_LOGIC;
signal grp_nfa_get_finals_fu_503_nfa_finals_buckets_rsp_read : STD_LOGIC;
signal grp_nfa_get_finals_fu_503_nfa_finals_buckets_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_finals_fu_503_nfa_finals_buckets_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_finals_fu_503_nfa_finals_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_finals_fu_503_nfa_finals_buckets_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_finals_fu_503_ap_return_0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_finals_fu_503_ap_return_1 : STD_LOGIC_VECTOR (31 downto 0);
signal r_bit_p_bsf32_hw_fu_509_bus_r : STD_LOGIC_VECTOR (31 downto 0);
signal i_index_reg_224 : STD_LOGIC_VECTOR (15 downto 0);
signal i_sample_reg_234 : STD_LOGIC_VECTOR (15 downto 0);
signal next_buckets_1_reg_244 : STD_LOGIC_VECTOR (31 downto 0);
signal any_0_i_phi_fu_432_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal next_buckets_0_reg_254 : STD_LOGIC_VECTOR (31 downto 0);
signal i_0_i_reg_264 : STD_LOGIC_VECTOR (15 downto 0);
signal p_01_rec_i_reg_275 : STD_LOGIC_VECTOR (63 downto 0);
signal bus_assign_reg_286 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_18_i_fu_583_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_18_1_i_fu_589_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal agg_result_bucket_index_0_lcssa4_i_reg_298 : STD_LOGIC_VECTOR (0 downto 0);
signal j_bucket1_ph_reg_311 : STD_LOGIC_VECTOR (31 downto 0);
signal j_bucket_index1_ph_reg_324 : STD_LOGIC_VECTOR (1 downto 0);
signal j_bit1_ph_reg_335 : STD_LOGIC_VECTOR (4 downto 0);
signal j_end_ph_reg_346 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_buckets_1_3_reg_360 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_buckets_0_3_reg_373 : STD_LOGIC_VECTOR (31 downto 0);
signal j_bucket1_reg_386 : STD_LOGIC_VECTOR (31 downto 0);
signal j_bucket_index1_reg_397 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bit1_reg_407 : STD_LOGIC_VECTOR (7 downto 0);
signal j_end_reg_417 : STD_LOGIC_VECTOR (0 downto 0);
signal any_0_i_reg_427 : STD_LOGIC_VECTOR (0 downto 0);
signal r_reg_440 : STD_LOGIC_VECTOR (0 downto 0);
signal p_0_reg_451 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_i_13_fu_537_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond_fu_744_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_sample_iterator_next_fu_463_ap_start_ap_start_reg : STD_LOGIC := '0';
signal ap_NS_fsm : STD_LOGIC_VECTOR (5 downto 0);
signal grp_bitset_next_fu_473_ap_start_ap_start_reg : STD_LOGIC := '0';
signal grp_sample_iterator_get_offset_fu_485_ap_start_ap_start_reg : STD_LOGIC := '0';
signal grp_nfa_get_initials_fu_497_ap_start_ap_start_reg : STD_LOGIC := '0';
signal grp_nfa_get_finals_fu_503_ap_start_ap_start_reg : STD_LOGIC := '0';
signal sum_fu_555_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_7_i_cast_fu_657_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_8_i_cast_fu_691_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal c_fu_142 : STD_LOGIC_VECTOR (31 downto 0);
signal c_1_fu_749_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_i_fu_527_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_12_fu_532_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_fu_610_p1 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i1_fu_614_p3 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_8_fu_622_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_4_i_fu_639_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_4_i_fu_639_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_4_i_fu_639_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_7_i_fu_650_p3 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_8_i_fu_684_p3 : STD_LOGIC_VECTOR (14 downto 0);
signal current_buckets_1_1_fu_727_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal current_buckets_0_1_fu_722_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_1_fu_732_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_4_i_fu_639_p00 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_4_i_fu_639_p10 : STD_LOGIC_VECTOR (13 downto 0);
signal ap_sig_bdd_366 : BOOLEAN;
signal ap_sig_bdd_187 : BOOLEAN;
component sample_iterator_next IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
indices_req_din : OUT STD_LOGIC;
indices_req_full_n : IN STD_LOGIC;
indices_req_write : OUT STD_LOGIC;
indices_rsp_empty_n : IN STD_LOGIC;
indices_rsp_read : OUT STD_LOGIC;
indices_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_datain : IN STD_LOGIC_VECTOR (55 downto 0);
indices_dataout : OUT STD_LOGIC_VECTOR (55 downto 0);
indices_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
i_index : IN STD_LOGIC_VECTOR (15 downto 0);
i_sample : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (15 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (15 downto 0) );
end component;
component bitset_next IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
ap_ce : IN STD_LOGIC;
p_read : IN STD_LOGIC_VECTOR (31 downto 0);
r_bit : IN STD_LOGIC_VECTOR (7 downto 0);
r_bucket_index : IN STD_LOGIC_VECTOR (7 downto 0);
r_bucket : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (7 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (7 downto 0);
ap_return_2 : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_3 : OUT STD_LOGIC_VECTOR (0 downto 0) );
end component;
component sample_iterator_get_offset IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
indices_req_din : OUT STD_LOGIC;
indices_req_full_n : IN STD_LOGIC;
indices_req_write : OUT STD_LOGIC;
indices_rsp_empty_n : IN STD_LOGIC;
indices_rsp_read : OUT STD_LOGIC;
indices_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_datain : IN STD_LOGIC_VECTOR (55 downto 0);
indices_dataout : OUT STD_LOGIC_VECTOR (55 downto 0);
indices_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
i_index : IN STD_LOGIC_VECTOR (15 downto 0);
i_sample : IN STD_LOGIC_VECTOR (15 downto 0);
sample_buffer_size : IN STD_LOGIC_VECTOR (31 downto 0);
sample_length : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component nfa_get_initials IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
ap_ce : IN STD_LOGIC;
nfa_initials_buckets_req_din : OUT STD_LOGIC;
nfa_initials_buckets_req_full_n : IN STD_LOGIC;
nfa_initials_buckets_req_write : OUT STD_LOGIC;
nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_initials_buckets_rsp_read : OUT STD_LOGIC;
nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component nfa_get_finals IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
ap_ce : IN STD_LOGIC;
nfa_finals_buckets_req_din : OUT STD_LOGIC;
nfa_finals_buckets_req_full_n : IN STD_LOGIC;
nfa_finals_buckets_req_write : OUT STD_LOGIC;
nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_finals_buckets_rsp_read : OUT STD_LOGIC;
nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component p_bsf32_hw IS
port (
bus_r : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (4 downto 0) );
end component;
begin
grp_sample_iterator_next_fu_463 : component sample_iterator_next
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_sample_iterator_next_fu_463_ap_start,
ap_done => grp_sample_iterator_next_fu_463_ap_done,
ap_idle => grp_sample_iterator_next_fu_463_ap_idle,
ap_ready => grp_sample_iterator_next_fu_463_ap_ready,
indices_req_din => grp_sample_iterator_next_fu_463_indices_req_din,
indices_req_full_n => grp_sample_iterator_next_fu_463_indices_req_full_n,
indices_req_write => grp_sample_iterator_next_fu_463_indices_req_write,
indices_rsp_empty_n => grp_sample_iterator_next_fu_463_indices_rsp_empty_n,
indices_rsp_read => grp_sample_iterator_next_fu_463_indices_rsp_read,
indices_address => grp_sample_iterator_next_fu_463_indices_address,
indices_datain => grp_sample_iterator_next_fu_463_indices_datain,
indices_dataout => grp_sample_iterator_next_fu_463_indices_dataout,
indices_size => grp_sample_iterator_next_fu_463_indices_size,
ap_ce => grp_sample_iterator_next_fu_463_ap_ce,
i_index => grp_sample_iterator_next_fu_463_i_index,
i_sample => grp_sample_iterator_next_fu_463_i_sample,
ap_return_0 => grp_sample_iterator_next_fu_463_ap_return_0,
ap_return_1 => grp_sample_iterator_next_fu_463_ap_return_1);
grp_bitset_next_fu_473 : component bitset_next
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_bitset_next_fu_473_ap_start,
ap_done => grp_bitset_next_fu_473_ap_done,
ap_idle => grp_bitset_next_fu_473_ap_idle,
ap_ready => grp_bitset_next_fu_473_ap_ready,
ap_ce => grp_bitset_next_fu_473_ap_ce,
p_read => grp_bitset_next_fu_473_p_read,
r_bit => grp_bitset_next_fu_473_r_bit,
r_bucket_index => grp_bitset_next_fu_473_r_bucket_index,
r_bucket => grp_bitset_next_fu_473_r_bucket,
ap_return_0 => grp_bitset_next_fu_473_ap_return_0,
ap_return_1 => grp_bitset_next_fu_473_ap_return_1,
ap_return_2 => grp_bitset_next_fu_473_ap_return_2,
ap_return_3 => grp_bitset_next_fu_473_ap_return_3);
grp_sample_iterator_get_offset_fu_485 : component sample_iterator_get_offset
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_sample_iterator_get_offset_fu_485_ap_start,
ap_done => grp_sample_iterator_get_offset_fu_485_ap_done,
ap_idle => grp_sample_iterator_get_offset_fu_485_ap_idle,
ap_ready => grp_sample_iterator_get_offset_fu_485_ap_ready,
indices_req_din => grp_sample_iterator_get_offset_fu_485_indices_req_din,
indices_req_full_n => grp_sample_iterator_get_offset_fu_485_indices_req_full_n,
indices_req_write => grp_sample_iterator_get_offset_fu_485_indices_req_write,
indices_rsp_empty_n => grp_sample_iterator_get_offset_fu_485_indices_rsp_empty_n,
indices_rsp_read => grp_sample_iterator_get_offset_fu_485_indices_rsp_read,
indices_address => grp_sample_iterator_get_offset_fu_485_indices_address,
indices_datain => grp_sample_iterator_get_offset_fu_485_indices_datain,
indices_dataout => grp_sample_iterator_get_offset_fu_485_indices_dataout,
indices_size => grp_sample_iterator_get_offset_fu_485_indices_size,
ap_ce => grp_sample_iterator_get_offset_fu_485_ap_ce,
i_index => grp_sample_iterator_get_offset_fu_485_i_index,
i_sample => grp_sample_iterator_get_offset_fu_485_i_sample,
sample_buffer_size => grp_sample_iterator_get_offset_fu_485_sample_buffer_size,
sample_length => grp_sample_iterator_get_offset_fu_485_sample_length,
ap_return => grp_sample_iterator_get_offset_fu_485_ap_return);
grp_nfa_get_initials_fu_497 : component nfa_get_initials
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_nfa_get_initials_fu_497_ap_start,
ap_done => grp_nfa_get_initials_fu_497_ap_done,
ap_idle => grp_nfa_get_initials_fu_497_ap_idle,
ap_ready => grp_nfa_get_initials_fu_497_ap_ready,
ap_ce => grp_nfa_get_initials_fu_497_ap_ce,
nfa_initials_buckets_req_din => grp_nfa_get_initials_fu_497_nfa_initials_buckets_req_din,
nfa_initials_buckets_req_full_n => grp_nfa_get_initials_fu_497_nfa_initials_buckets_req_full_n,
nfa_initials_buckets_req_write => grp_nfa_get_initials_fu_497_nfa_initials_buckets_req_write,
nfa_initials_buckets_rsp_empty_n => grp_nfa_get_initials_fu_497_nfa_initials_buckets_rsp_empty_n,
nfa_initials_buckets_rsp_read => grp_nfa_get_initials_fu_497_nfa_initials_buckets_rsp_read,
nfa_initials_buckets_address => grp_nfa_get_initials_fu_497_nfa_initials_buckets_address,
nfa_initials_buckets_datain => grp_nfa_get_initials_fu_497_nfa_initials_buckets_datain,
nfa_initials_buckets_dataout => grp_nfa_get_initials_fu_497_nfa_initials_buckets_dataout,
nfa_initials_buckets_size => grp_nfa_get_initials_fu_497_nfa_initials_buckets_size,
ap_return_0 => grp_nfa_get_initials_fu_497_ap_return_0,
ap_return_1 => grp_nfa_get_initials_fu_497_ap_return_1);
grp_nfa_get_finals_fu_503 : component nfa_get_finals
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_nfa_get_finals_fu_503_ap_start,
ap_done => grp_nfa_get_finals_fu_503_ap_done,
ap_idle => grp_nfa_get_finals_fu_503_ap_idle,
ap_ready => grp_nfa_get_finals_fu_503_ap_ready,
ap_ce => grp_nfa_get_finals_fu_503_ap_ce,
nfa_finals_buckets_req_din => grp_nfa_get_finals_fu_503_nfa_finals_buckets_req_din,
nfa_finals_buckets_req_full_n => grp_nfa_get_finals_fu_503_nfa_finals_buckets_req_full_n,
nfa_finals_buckets_req_write => grp_nfa_get_finals_fu_503_nfa_finals_buckets_req_write,
nfa_finals_buckets_rsp_empty_n => grp_nfa_get_finals_fu_503_nfa_finals_buckets_rsp_empty_n,
nfa_finals_buckets_rsp_read => grp_nfa_get_finals_fu_503_nfa_finals_buckets_rsp_read,
nfa_finals_buckets_address => grp_nfa_get_finals_fu_503_nfa_finals_buckets_address,
nfa_finals_buckets_datain => grp_nfa_get_finals_fu_503_nfa_finals_buckets_datain,
nfa_finals_buckets_dataout => grp_nfa_get_finals_fu_503_nfa_finals_buckets_dataout,
nfa_finals_buckets_size => grp_nfa_get_finals_fu_503_nfa_finals_buckets_size,
ap_return_0 => grp_nfa_get_finals_fu_503_ap_return_0,
ap_return_1 => grp_nfa_get_finals_fu_503_ap_return_1);
r_bit_p_bsf32_hw_fu_509 : component p_bsf32_hw
port map (
bus_r => r_bit_p_bsf32_hw_fu_509_bus_r,
ap_return => r_bit_p_bsf32_hw_fu_509_ap_return);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- grp_bitset_next_fu_473_ap_start_ap_start_reg assign process. --
grp_bitset_next_fu_473_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_bitset_next_fu_473_ap_start_ap_start_reg <= ap_const_logic_0;
else
if (((ap_ST_st16_fsm_15 = ap_CS_fsm) and (ap_ST_st17_fsm_16 = ap_NS_fsm))) then
grp_bitset_next_fu_473_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_bitset_next_fu_473_ap_ready)) then
grp_bitset_next_fu_473_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- grp_nfa_get_finals_fu_503_ap_start_ap_start_reg assign process. --
grp_nfa_get_finals_fu_503_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_nfa_get_finals_fu_503_ap_start_ap_start_reg <= ap_const_logic_0;
else
if (((ap_ST_st10_fsm_9 = ap_CS_fsm) and (ap_ST_st25_fsm_24 = ap_NS_fsm))) then
grp_nfa_get_finals_fu_503_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_nfa_get_finals_fu_503_ap_ready)) then
grp_nfa_get_finals_fu_503_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- grp_nfa_get_initials_fu_497_ap_start_ap_start_reg assign process. --
grp_nfa_get_initials_fu_497_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_nfa_get_initials_fu_497_ap_start_ap_start_reg <= ap_const_logic_0;
else
if (((ap_ST_st2_fsm_1 = ap_CS_fsm) and (ap_ST_st3_fsm_2 = ap_NS_fsm))) then
grp_nfa_get_initials_fu_497_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_nfa_get_initials_fu_497_ap_ready)) then
grp_nfa_get_initials_fu_497_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- grp_sample_iterator_get_offset_fu_485_ap_start_ap_start_reg assign process. --
grp_sample_iterator_get_offset_fu_485_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_sample_iterator_get_offset_fu_485_ap_start_ap_start_reg <= ap_const_logic_0;
else
if (((ap_ST_st6_fsm_5 = ap_NS_fsm) and (ap_ST_st5_fsm_4 = ap_CS_fsm))) then
grp_sample_iterator_get_offset_fu_485_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_sample_iterator_get_offset_fu_485_ap_ready)) then
grp_sample_iterator_get_offset_fu_485_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- grp_sample_iterator_next_fu_463_ap_start_ap_start_reg assign process. --
grp_sample_iterator_next_fu_463_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_sample_iterator_next_fu_463_ap_start_ap_start_reg <= ap_const_logic_0;
else
if (((ap_ST_st32_fsm_31 = ap_CS_fsm) and (ap_ST_st33_fsm_32 = ap_NS_fsm))) then
grp_sample_iterator_next_fu_463_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_sample_iterator_next_fu_463_ap_ready)) then
grp_sample_iterator_next_fu_463_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- agg_result_bucket_index_0_lcssa4_i_reg_298 assign process. --
agg_result_bucket_index_0_lcssa4_i_reg_298_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_sig_bdd_187) then
if (ap_sig_bdd_366) then
agg_result_bucket_index_0_lcssa4_i_reg_298 <= ap_const_lv1_1;
elsif ((ap_const_lv1_0 = tmp_18_i_fu_583_p2)) then
agg_result_bucket_index_0_lcssa4_i_reg_298 <= ap_const_lv1_0;
end if;
end if;
end if;
end process;
-- any_0_i_reg_427 assign process. --
any_0_i_reg_427_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st15_fsm_14 = ap_CS_fsm)) then
any_0_i_reg_427 <= ap_const_lv1_0;
elsif ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then
any_0_i_reg_427 <= ap_const_lv1_1;
end if;
end if;
end process;
-- bus_assign_reg_286 assign process. --
bus_assign_reg_286_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_sig_bdd_187) then
if (ap_sig_bdd_366) then
bus_assign_reg_286 <= next_buckets_1_reg_244;
elsif ((ap_const_lv1_0 = tmp_18_i_fu_583_p2)) then
bus_assign_reg_286 <= next_buckets_0_reg_254;
end if;
end if;
end if;
end process;
-- c_fu_142 assign process. --
c_fu_142_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st32_fsm_31 = ap_CS_fsm) and (stop_on_first_read_read_fu_152_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = or_cond_fu_744_p2))) then
c_fu_142 <= c_1_fu_749_p2;
elsif (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then
c_fu_142 <= ap_const_lv32_0;
end if;
end if;
end process;
-- i_0_i_reg_264 assign process. --
i_0_i_reg_264_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st16_fsm_15 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_420_p4)) and not((ap_const_lv1_0 = any_0_i_phi_fu_432_p4)))) then
i_0_i_reg_264 <= i_reg_847;
elsif ((ap_ST_st9_fsm_8 = ap_CS_fsm)) then
i_0_i_reg_264 <= ap_const_lv16_0;
end if;
end if;
end process;
-- i_index_reg_224 assign process. --
i_index_reg_224_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st36_fsm_35 = ap_CS_fsm)) then
i_index_reg_224 <= grp_sample_iterator_next_fu_463_ap_return_0;
elsif (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then
i_index_reg_224 <= begin_index;
end if;
end if;
end process;
-- i_sample_reg_234 assign process. --
i_sample_reg_234_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st36_fsm_35 = ap_CS_fsm)) then
i_sample_reg_234 <= grp_sample_iterator_next_fu_463_ap_return_1;
elsif (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then
i_sample_reg_234 <= begin_sample;
end if;
end if;
end process;
-- j_bit1_reg_407 assign process. --
j_bit1_reg_407_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st15_fsm_14 = ap_CS_fsm)) then
j_bit1_reg_407 <= j_bit1_ph_cast_fu_603_p1;
elsif ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then
j_bit1_reg_407 <= j_bit_reg_910;
end if;
end if;
end process;
-- j_bucket1_ph_reg_311 assign process. --
j_bucket1_ph_reg_311_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st14_fsm_13 = ap_CS_fsm)) then
j_bucket1_ph_reg_311 <= bus_assign_reg_286;
elsif (((ap_ST_st13_fsm_12 = ap_CS_fsm) and not((sample_buffer_rsp_empty_n = ap_const_logic_0)) and not((ap_const_lv1_0 = tmp_18_i_fu_583_p2)) and not((ap_const_lv1_0 = tmp_18_1_i_fu_589_p2)))) then
j_bucket1_ph_reg_311 <= ap_const_lv32_0;
end if;
end if;
end process;
-- j_bucket1_reg_386 assign process. --
j_bucket1_reg_386_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st15_fsm_14 = ap_CS_fsm)) then
j_bucket1_reg_386 <= j_bucket1_ph_reg_311;
elsif ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then
j_bucket1_reg_386 <= j_bucket_reg_920;
end if;
end if;
end process;
-- j_bucket_index1_ph_reg_324 assign process. --
j_bucket_index1_ph_reg_324_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st14_fsm_13 = ap_CS_fsm)) then
j_bucket_index1_ph_reg_324 <= agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_595_p1;
elsif (((ap_ST_st13_fsm_12 = ap_CS_fsm) and not((sample_buffer_rsp_empty_n = ap_const_logic_0)) and not((ap_const_lv1_0 = tmp_18_i_fu_583_p2)) and not((ap_const_lv1_0 = tmp_18_1_i_fu_589_p2)))) then
j_bucket_index1_ph_reg_324 <= ap_const_lv2_2;
end if;
end if;
end process;
-- j_bucket_index1_reg_397 assign process. --
j_bucket_index1_reg_397_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st15_fsm_14 = ap_CS_fsm)) then
j_bucket_index1_reg_397 <= j_bucket_index1_ph_cast_fu_599_p1;
elsif ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then
j_bucket_index1_reg_397 <= j_bucket_index_reg_915;
end if;
end if;
end process;
-- j_end_ph_reg_346 assign process. --
j_end_ph_reg_346_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st14_fsm_13 = ap_CS_fsm)) then
j_end_ph_reg_346 <= ap_const_lv1_0;
elsif (((ap_ST_st13_fsm_12 = ap_CS_fsm) and not((sample_buffer_rsp_empty_n = ap_const_logic_0)) and not((ap_const_lv1_0 = tmp_18_i_fu_583_p2)) and not((ap_const_lv1_0 = tmp_18_1_i_fu_589_p2)))) then
j_end_ph_reg_346 <= ap_const_lv1_1;
end if;
end if;
end process;
-- j_end_reg_417 assign process. --
j_end_reg_417_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st15_fsm_14 = ap_CS_fsm)) then
j_end_reg_417 <= j_end_ph_reg_346;
elsif ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then
j_end_reg_417 <= p_s_reg_925;
end if;
end if;
end process;
-- next_buckets_0_reg_254 assign process. --
next_buckets_0_reg_254_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st16_fsm_15 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_420_p4)) and not((ap_const_lv1_0 = any_0_i_phi_fu_432_p4)))) then
next_buckets_0_reg_254 <= tmp_buckets_0_3_reg_373;
elsif ((ap_ST_st9_fsm_8 = ap_CS_fsm)) then
next_buckets_0_reg_254 <= current_buckets_0_reg_823;
end if;
end if;
end process;
-- next_buckets_1_reg_244 assign process. --
next_buckets_1_reg_244_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st16_fsm_15 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_420_p4)) and not((ap_const_lv1_0 = any_0_i_phi_fu_432_p4)))) then
next_buckets_1_reg_244 <= tmp_buckets_1_3_reg_360;
elsif ((ap_ST_st9_fsm_8 = ap_CS_fsm)) then
next_buckets_1_reg_244 <= current_buckets_1_reg_828;
end if;
end if;
end process;
-- p_01_rec_i_reg_275 assign process. --
p_01_rec_i_reg_275_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st16_fsm_15 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_420_p4)) and not((ap_const_lv1_0 = any_0_i_phi_fu_432_p4)))) then
p_01_rec_i_reg_275 <= p_rec_i_reg_852;
elsif ((ap_ST_st9_fsm_8 = ap_CS_fsm)) then
p_01_rec_i_reg_275 <= ap_const_lv64_0;
end if;
end if;
end process;
-- p_0_reg_451 assign process. --
p_0_reg_451_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st32_fsm_31 = ap_CS_fsm) and not((stop_on_first_read_read_fu_152_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = or_cond_fu_744_p2))) then
p_0_reg_451 <= ap_const_lv32_1;
elsif (((ap_ST_st2_fsm_1 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_i_13_fu_537_p2)))) then
p_0_reg_451 <= c_fu_142;
end if;
end if;
end process;
-- r_reg_440 assign process. --
r_reg_440_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st16_fsm_15 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_420_p4)) and (ap_const_lv1_0 = any_0_i_phi_fu_432_p4))) then
r_reg_440 <= ap_const_lv1_0;
elsif ((ap_ST_st31_fsm_30 = ap_CS_fsm)) then
r_reg_440 <= tmp_4_fu_738_p2;
end if;
end if;
end process;
-- tmp_buckets_0_3_reg_373 assign process. --
tmp_buckets_0_3_reg_373_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st15_fsm_14 = ap_CS_fsm)) then
tmp_buckets_0_3_reg_373 <= ap_const_lv32_0;
elsif ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then
tmp_buckets_0_3_reg_373 <= next_buckets_0_1_reg_936;
end if;
end if;
end process;
-- tmp_buckets_1_3_reg_360 assign process. --
tmp_buckets_1_3_reg_360_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st15_fsm_14 = ap_CS_fsm)) then
tmp_buckets_1_3_reg_360 <= ap_const_lv32_0;
elsif ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then
tmp_buckets_1_3_reg_360 <= next_buckets_1_1_fu_708_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st2_fsm_1 = ap_CS_fsm)) then
c_load_reg_814 <= c_fu_142;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st8_fsm_7 = ap_CS_fsm)) then
current_buckets_0_reg_823 <= grp_nfa_get_initials_fu_497_ap_return_0;
current_buckets_1_reg_828 <= grp_nfa_get_initials_fu_497_ap_return_1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st10_fsm_9 = ap_CS_fsm)) then
i_reg_847 <= i_fu_571_p2;
sample_buffer_addr_reg_838 <= sum_fu_555_p2(32 - 1 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st14_fsm_13 = ap_CS_fsm)) then
j_bit1_ph_reg_335 <= r_bit_p_bsf32_hw_fu_509_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
j_bit_reg_910 <= grp_bitset_next_fu_473_ap_return_0;
j_bucket_index_reg_915 <= grp_bitset_next_fu_473_ap_return_1;
j_bucket_reg_920 <= grp_bitset_next_fu_473_ap_return_2;
p_s_reg_925 <= grp_bitset_next_fu_473_ap_return_3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st21_fsm_20 = ap_CS_fsm)) then
next_buckets_0_1_reg_936 <= next_buckets_0_1_fu_702_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st10_fsm_9 = ap_CS_fsm) and not((tmp_7_fu_566_p2 = ap_const_lv1_0)))) then
p_rec_i_reg_852 <= p_rec_i_fu_577_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_ST_st20_fsm_19 = ap_CS_fsm) and not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) or (not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0)) and (ap_ST_st23_fsm_22 = ap_CS_fsm)))) then
reg_515 <= nfa_forward_buckets_datain;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st16_fsm_15 = ap_CS_fsm) and (ap_const_lv1_0 = j_end_phi_fu_420_p4))) then
state_reg_893 <= state_fu_626_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st13_fsm_12 = ap_CS_fsm) and not((sample_buffer_rsp_empty_n = ap_const_logic_0)))) then
sym_reg_857 <= sample_buffer_datain;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st15_fsm_14 = ap_CS_fsm)) then
tmp_5_i_cast_reg_888(0) <= tmp_5_i_cast_fu_607_p1(0);
tmp_5_i_cast_reg_888(1) <= tmp_5_i_cast_fu_607_p1(1);
tmp_5_i_cast_reg_888(2) <= tmp_5_i_cast_fu_607_p1(2);
tmp_5_i_cast_reg_888(3) <= tmp_5_i_cast_fu_607_p1(3);
tmp_5_i_cast_reg_888(4) <= tmp_5_i_cast_fu_607_p1(4);
tmp_5_i_cast_reg_888(5) <= tmp_5_i_cast_fu_607_p1(5);
tmp_5_i_cast_reg_888(6) <= tmp_5_i_cast_fu_607_p1(6);
tmp_5_i_cast_reg_888(7) <= tmp_5_i_cast_fu_607_p1(7);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st17_fsm_16 = ap_CS_fsm)) then
tmp_6_i_reg_898 <= tmp_6_i_fu_645_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st9_fsm_8 = ap_CS_fsm)) then
tmp_6_reg_833(0) <= tmp_6_fu_551_p1(0);
tmp_6_reg_833(1) <= tmp_6_fu_551_p1(1);
tmp_6_reg_833(2) <= tmp_6_fu_551_p1(2);
tmp_6_reg_833(3) <= tmp_6_fu_551_p1(3);
tmp_6_reg_833(4) <= tmp_6_fu_551_p1(4);
tmp_6_reg_833(5) <= tmp_6_fu_551_p1(5);
tmp_6_reg_833(6) <= tmp_6_fu_551_p1(6);
tmp_6_reg_833(7) <= tmp_6_fu_551_p1(7);
tmp_6_reg_833(8) <= tmp_6_fu_551_p1(8);
tmp_6_reg_833(9) <= tmp_6_fu_551_p1(9);
tmp_6_reg_833(10) <= tmp_6_fu_551_p1(10);
tmp_6_reg_833(11) <= tmp_6_fu_551_p1(11);
tmp_6_reg_833(12) <= tmp_6_fu_551_p1(12);
tmp_6_reg_833(13) <= tmp_6_fu_551_p1(13);
tmp_6_reg_833(14) <= tmp_6_fu_551_p1(14);
tmp_6_reg_833(15) <= tmp_6_fu_551_p1(15);
tmp_6_reg_833(16) <= tmp_6_fu_551_p1(16);
tmp_6_reg_833(17) <= tmp_6_fu_551_p1(17);
tmp_6_reg_833(18) <= tmp_6_fu_551_p1(18);
tmp_6_reg_833(19) <= tmp_6_fu_551_p1(19);
tmp_6_reg_833(20) <= tmp_6_fu_551_p1(20);
tmp_6_reg_833(21) <= tmp_6_fu_551_p1(21);
tmp_6_reg_833(22) <= tmp_6_fu_551_p1(22);
tmp_6_reg_833(23) <= tmp_6_fu_551_p1(23);
tmp_6_reg_833(24) <= tmp_6_fu_551_p1(24);
tmp_6_reg_833(25) <= tmp_6_fu_551_p1(25);
tmp_6_reg_833(26) <= tmp_6_fu_551_p1(26);
tmp_6_reg_833(27) <= tmp_6_fu_551_p1(27);
tmp_6_reg_833(28) <= tmp_6_fu_551_p1(28);
tmp_6_reg_833(29) <= tmp_6_fu_551_p1(29);
tmp_6_reg_833(30) <= tmp_6_fu_551_p1(30);
tmp_6_reg_833(31) <= tmp_6_fu_551_p1(31);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st30_fsm_29 = ap_CS_fsm)) then
tmp_buckets_0_reg_946 <= grp_nfa_get_finals_fu_503_ap_return_0;
tmp_buckets_1_reg_951 <= grp_nfa_get_finals_fu_503_ap_return_1;
end if;
end if;
end process;
tmp_6_reg_833(63 downto 32) <= "00000000000000000000000000000000";
tmp_5_i_cast_reg_888(13 downto 8) <= "000000";
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , nfa_forward_buckets_rsp_empty_n , sample_buffer_rsp_empty_n , stop_on_first_read_read_fu_152_p2 , tmp_7_fu_566_p2 , j_end_phi_fu_420_p4 , any_0_i_phi_fu_432_p4 , tmp_18_i_fu_583_p2 , tmp_18_1_i_fu_589_p2 , tmp_i_13_fu_537_p2 , or_cond_fu_744_p2)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if (not((ap_const_lv1_0 = tmp_i_13_fu_537_p2))) then
ap_NS_fsm <= ap_ST_st37_fsm_36;
else
ap_NS_fsm <= ap_ST_st3_fsm_2;
end if;
when ap_ST_st3_fsm_2 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when ap_ST_st4_fsm_3 =>
ap_NS_fsm <= ap_ST_st5_fsm_4;
when ap_ST_st5_fsm_4 =>
ap_NS_fsm <= ap_ST_st6_fsm_5;
when ap_ST_st6_fsm_5 =>
ap_NS_fsm <= ap_ST_st7_fsm_6;
when ap_ST_st7_fsm_6 =>
ap_NS_fsm <= ap_ST_st8_fsm_7;
when ap_ST_st8_fsm_7 =>
ap_NS_fsm <= ap_ST_st9_fsm_8;
when ap_ST_st9_fsm_8 =>
ap_NS_fsm <= ap_ST_st10_fsm_9;
when ap_ST_st10_fsm_9 =>
if ((tmp_7_fu_566_p2 = ap_const_lv1_0)) then
ap_NS_fsm <= ap_ST_st25_fsm_24;
else
ap_NS_fsm <= ap_ST_st11_fsm_10;
end if;
when ap_ST_st11_fsm_10 =>
ap_NS_fsm <= ap_ST_st12_fsm_11;
when ap_ST_st12_fsm_11 =>
ap_NS_fsm <= ap_ST_st13_fsm_12;
when ap_ST_st13_fsm_12 =>
if ((not((sample_buffer_rsp_empty_n = ap_const_logic_0)) and not((ap_const_lv1_0 = tmp_18_i_fu_583_p2)) and not((ap_const_lv1_0 = tmp_18_1_i_fu_589_p2)))) then
ap_NS_fsm <= ap_ST_st15_fsm_14;
elsif ((not((sample_buffer_rsp_empty_n = ap_const_logic_0)) and ((ap_const_lv1_0 = tmp_18_i_fu_583_p2) or (ap_const_lv1_0 = tmp_18_1_i_fu_589_p2)))) then
ap_NS_fsm <= ap_ST_st14_fsm_13;
else
ap_NS_fsm <= ap_ST_st13_fsm_12;
end if;
when ap_ST_st14_fsm_13 =>
ap_NS_fsm <= ap_ST_st15_fsm_14;
when ap_ST_st15_fsm_14 =>
ap_NS_fsm <= ap_ST_st16_fsm_15;
when ap_ST_st16_fsm_15 =>
if ((not((ap_const_lv1_0 = j_end_phi_fu_420_p4)) and not((ap_const_lv1_0 = any_0_i_phi_fu_432_p4)))) then
ap_NS_fsm <= ap_ST_st10_fsm_9;
elsif ((not((ap_const_lv1_0 = j_end_phi_fu_420_p4)) and (ap_const_lv1_0 = any_0_i_phi_fu_432_p4))) then
ap_NS_fsm <= ap_ST_st32_fsm_31;
else
ap_NS_fsm <= ap_ST_st17_fsm_16;
end if;
when ap_ST_st17_fsm_16 =>
ap_NS_fsm <= ap_ST_st18_fsm_17;
when ap_ST_st18_fsm_17 =>
ap_NS_fsm <= ap_ST_st19_fsm_18;
when ap_ST_st19_fsm_18 =>
ap_NS_fsm <= ap_ST_st20_fsm_19;
when ap_ST_st20_fsm_19 =>
if (not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st21_fsm_20;
else
ap_NS_fsm <= ap_ST_st20_fsm_19;
end if;
when ap_ST_st21_fsm_20 =>
ap_NS_fsm <= ap_ST_st22_fsm_21;
when ap_ST_st22_fsm_21 =>
ap_NS_fsm <= ap_ST_st23_fsm_22;
when ap_ST_st23_fsm_22 =>
if (not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st24_fsm_23;
else
ap_NS_fsm <= ap_ST_st23_fsm_22;
end if;
when ap_ST_st24_fsm_23 =>
ap_NS_fsm <= ap_ST_st16_fsm_15;
when ap_ST_st25_fsm_24 =>
ap_NS_fsm <= ap_ST_st26_fsm_25;
when ap_ST_st26_fsm_25 =>
ap_NS_fsm <= ap_ST_st27_fsm_26;
when ap_ST_st27_fsm_26 =>
ap_NS_fsm <= ap_ST_st28_fsm_27;
when ap_ST_st28_fsm_27 =>
ap_NS_fsm <= ap_ST_st29_fsm_28;
when ap_ST_st29_fsm_28 =>
ap_NS_fsm <= ap_ST_st30_fsm_29;
when ap_ST_st30_fsm_29 =>
ap_NS_fsm <= ap_ST_st31_fsm_30;
when ap_ST_st31_fsm_30 =>
ap_NS_fsm <= ap_ST_st32_fsm_31;
when ap_ST_st32_fsm_31 =>
if ((not((stop_on_first_read_read_fu_152_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = or_cond_fu_744_p2))) then
ap_NS_fsm <= ap_ST_st37_fsm_36;
else
ap_NS_fsm <= ap_ST_st33_fsm_32;
end if;
when ap_ST_st33_fsm_32 =>
ap_NS_fsm <= ap_ST_st34_fsm_33;
when ap_ST_st34_fsm_33 =>
ap_NS_fsm <= ap_ST_st35_fsm_34;
when ap_ST_st35_fsm_34 =>
ap_NS_fsm <= ap_ST_st36_fsm_35;
when ap_ST_st36_fsm_35 =>
ap_NS_fsm <= ap_ST_st2_fsm_1;
when ap_ST_st37_fsm_36 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "XXXXXX";
end case;
end process;
agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_595_p1 <= std_logic_vector(resize(unsigned(agg_result_bucket_index_0_lcssa4_i_reg_298),2));
any_0_i_phi_fu_432_p4 <= any_0_i_reg_427;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_CS_fsm)
begin
if ((ap_ST_st37_fsm_36 = ap_CS_fsm)) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_st1_fsm_0 = ap_CS_fsm))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_CS_fsm)
begin
if ((ap_ST_st37_fsm_36 = ap_CS_fsm)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_return <= p_0_reg_451;
-- ap_sig_bdd_187 assign process. --
ap_sig_bdd_187_assign_proc : process(ap_CS_fsm, sample_buffer_rsp_empty_n)
begin
ap_sig_bdd_187 <= ((ap_ST_st13_fsm_12 = ap_CS_fsm) and not((sample_buffer_rsp_empty_n = ap_const_logic_0)));
end process;
-- ap_sig_bdd_366 assign process. --
ap_sig_bdd_366_assign_proc : process(tmp_18_i_fu_583_p2, tmp_18_1_i_fu_589_p2)
begin
ap_sig_bdd_366 <= ((ap_const_lv1_0 = tmp_18_1_i_fu_589_p2) and not((ap_const_lv1_0 = tmp_18_i_fu_583_p2)));
end process;
c_1_fu_749_p2 <= std_logic_vector(unsigned(c_load_reg_814) + unsigned(ap_const_lv32_1));
current_buckets_0_1_fu_722_p2 <= (next_buckets_0_reg_254 and tmp_buckets_0_reg_946);
current_buckets_1_1_fu_727_p2 <= (next_buckets_1_reg_244 and tmp_buckets_1_reg_951);
grp_bitset_next_fu_473_ap_ce <= ap_const_logic_1;
grp_bitset_next_fu_473_ap_start <= grp_bitset_next_fu_473_ap_start_ap_start_reg;
grp_bitset_next_fu_473_p_read <= next_buckets_1_reg_244;
grp_bitset_next_fu_473_r_bit <= j_bit1_reg_407;
grp_bitset_next_fu_473_r_bucket <= j_bucket1_reg_386;
grp_bitset_next_fu_473_r_bucket_index <= j_bucket_index1_reg_397;
grp_nfa_get_finals_fu_503_ap_ce <= ap_const_logic_1;
grp_nfa_get_finals_fu_503_ap_start <= grp_nfa_get_finals_fu_503_ap_start_ap_start_reg;
grp_nfa_get_finals_fu_503_nfa_finals_buckets_datain <= nfa_finals_buckets_datain;
grp_nfa_get_finals_fu_503_nfa_finals_buckets_req_full_n <= nfa_finals_buckets_req_full_n;
grp_nfa_get_finals_fu_503_nfa_finals_buckets_rsp_empty_n <= nfa_finals_buckets_rsp_empty_n;
grp_nfa_get_initials_fu_497_ap_ce <= ap_const_logic_1;
grp_nfa_get_initials_fu_497_ap_start <= grp_nfa_get_initials_fu_497_ap_start_ap_start_reg;
grp_nfa_get_initials_fu_497_nfa_initials_buckets_datain <= nfa_initials_buckets_datain;
grp_nfa_get_initials_fu_497_nfa_initials_buckets_req_full_n <= nfa_initials_buckets_req_full_n;
grp_nfa_get_initials_fu_497_nfa_initials_buckets_rsp_empty_n <= nfa_initials_buckets_rsp_empty_n;
grp_sample_iterator_get_offset_fu_485_ap_ce <= ap_const_logic_1;
grp_sample_iterator_get_offset_fu_485_ap_start <= grp_sample_iterator_get_offset_fu_485_ap_start_ap_start_reg;
grp_sample_iterator_get_offset_fu_485_i_index <= i_index_reg_224;
grp_sample_iterator_get_offset_fu_485_i_sample <= i_sample_reg_234;
grp_sample_iterator_get_offset_fu_485_indices_datain <= indices_datain;
grp_sample_iterator_get_offset_fu_485_indices_req_full_n <= indices_req_full_n;
grp_sample_iterator_get_offset_fu_485_indices_rsp_empty_n <= indices_rsp_empty_n;
grp_sample_iterator_get_offset_fu_485_sample_buffer_size <= sample_buffer_length;
grp_sample_iterator_get_offset_fu_485_sample_length <= sample_length;
grp_sample_iterator_next_fu_463_ap_ce <= ap_const_logic_1;
grp_sample_iterator_next_fu_463_ap_start <= grp_sample_iterator_next_fu_463_ap_start_ap_start_reg;
grp_sample_iterator_next_fu_463_i_index <= i_index_reg_224;
grp_sample_iterator_next_fu_463_i_sample <= i_sample_reg_234;
grp_sample_iterator_next_fu_463_indices_datain <= indices_datain;
grp_sample_iterator_next_fu_463_indices_req_full_n <= indices_req_full_n;
grp_sample_iterator_next_fu_463_indices_rsp_empty_n <= indices_rsp_empty_n;
i_fu_571_p2 <= std_logic_vector(unsigned(i_0_i_reg_264) + unsigned(ap_const_lv16_1));
-- indices_address assign process. --
indices_address_assign_proc : process(ap_CS_fsm, grp_sample_iterator_next_fu_463_indices_address, grp_sample_iterator_get_offset_fu_485_indices_address)
begin
if (((ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm))) then
indices_address <= grp_sample_iterator_get_offset_fu_485_indices_address;
elsif (((ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm))) then
indices_address <= grp_sample_iterator_next_fu_463_indices_address;
else
indices_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_dataout assign process. --
indices_dataout_assign_proc : process(ap_CS_fsm, grp_sample_iterator_next_fu_463_indices_dataout, grp_sample_iterator_get_offset_fu_485_indices_dataout)
begin
if (((ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm))) then
indices_dataout <= grp_sample_iterator_get_offset_fu_485_indices_dataout;
elsif (((ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm))) then
indices_dataout <= grp_sample_iterator_next_fu_463_indices_dataout;
else
indices_dataout <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_req_din assign process. --
indices_req_din_assign_proc : process(ap_CS_fsm, grp_sample_iterator_next_fu_463_indices_req_din, grp_sample_iterator_get_offset_fu_485_indices_req_din)
begin
if (((ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm))) then
indices_req_din <= grp_sample_iterator_get_offset_fu_485_indices_req_din;
elsif (((ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm))) then
indices_req_din <= grp_sample_iterator_next_fu_463_indices_req_din;
else
indices_req_din <= 'X';
end if;
end process;
-- indices_req_write assign process. --
indices_req_write_assign_proc : process(ap_CS_fsm, grp_sample_iterator_next_fu_463_indices_req_write, grp_sample_iterator_get_offset_fu_485_indices_req_write)
begin
if (((ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm))) then
indices_req_write <= grp_sample_iterator_get_offset_fu_485_indices_req_write;
elsif (((ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm))) then
indices_req_write <= grp_sample_iterator_next_fu_463_indices_req_write;
else
indices_req_write <= 'X';
end if;
end process;
-- indices_rsp_read assign process. --
indices_rsp_read_assign_proc : process(ap_CS_fsm, grp_sample_iterator_next_fu_463_indices_rsp_read, grp_sample_iterator_get_offset_fu_485_indices_rsp_read)
begin
if (((ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm))) then
indices_rsp_read <= grp_sample_iterator_get_offset_fu_485_indices_rsp_read;
elsif (((ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm))) then
indices_rsp_read <= grp_sample_iterator_next_fu_463_indices_rsp_read;
else
indices_rsp_read <= 'X';
end if;
end process;
-- indices_size assign process. --
indices_size_assign_proc : process(ap_CS_fsm, grp_sample_iterator_next_fu_463_indices_size, grp_sample_iterator_get_offset_fu_485_indices_size)
begin
if (((ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm))) then
indices_size <= grp_sample_iterator_get_offset_fu_485_indices_size;
elsif (((ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm))) then
indices_size <= grp_sample_iterator_next_fu_463_indices_size;
else
indices_size <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
j_bit1_ph_cast_fu_603_p1 <= std_logic_vector(resize(unsigned(j_bit1_ph_reg_335),8));
j_bucket_index1_ph_cast_fu_599_p1 <= std_logic_vector(resize(unsigned(j_bucket_index1_ph_reg_324),8));
j_end_phi_fu_420_p4 <= j_end_reg_417;
next_buckets_0_1_fu_702_p2 <= (reg_515 or tmp_buckets_0_3_reg_373);
next_buckets_1_1_fu_708_p2 <= (reg_515 or tmp_buckets_1_3_reg_360);
nfa_finals_buckets_address <= grp_nfa_get_finals_fu_503_nfa_finals_buckets_address;
nfa_finals_buckets_dataout <= grp_nfa_get_finals_fu_503_nfa_finals_buckets_dataout;
nfa_finals_buckets_req_din <= grp_nfa_get_finals_fu_503_nfa_finals_buckets_req_din;
nfa_finals_buckets_req_write <= grp_nfa_get_finals_fu_503_nfa_finals_buckets_req_write;
nfa_finals_buckets_rsp_read <= grp_nfa_get_finals_fu_503_nfa_finals_buckets_rsp_read;
nfa_finals_buckets_size <= grp_nfa_get_finals_fu_503_nfa_finals_buckets_size;
-- nfa_forward_buckets_address assign process. --
nfa_forward_buckets_address_assign_proc : process(ap_CS_fsm, tmp_7_i_cast_fu_657_p1, tmp_8_i_cast_fu_691_p1)
begin
if ((ap_ST_st21_fsm_20 = ap_CS_fsm)) then
nfa_forward_buckets_address <= tmp_8_i_cast_fu_691_p1(32 - 1 downto 0);
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
nfa_forward_buckets_address <= tmp_7_i_cast_fu_657_p1(32 - 1 downto 0);
else
nfa_forward_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
nfa_forward_buckets_dataout <= ap_const_lv32_0;
nfa_forward_buckets_req_din <= ap_const_logic_0;
-- nfa_forward_buckets_req_write assign process. --
nfa_forward_buckets_req_write_assign_proc : process(ap_CS_fsm)
begin
if (((ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm))) then
nfa_forward_buckets_req_write <= ap_const_logic_1;
else
nfa_forward_buckets_req_write <= ap_const_logic_0;
end if;
end process;
-- nfa_forward_buckets_rsp_read assign process. --
nfa_forward_buckets_rsp_read_assign_proc : process(ap_CS_fsm, nfa_forward_buckets_rsp_empty_n)
begin
if ((((ap_ST_st20_fsm_19 = ap_CS_fsm) and not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) or (not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0)) and (ap_ST_st23_fsm_22 = ap_CS_fsm)))) then
nfa_forward_buckets_rsp_read <= ap_const_logic_1;
else
nfa_forward_buckets_rsp_read <= ap_const_logic_0;
end if;
end process;
nfa_forward_buckets_size <= ap_const_lv32_1;
nfa_initials_buckets_address <= grp_nfa_get_initials_fu_497_nfa_initials_buckets_address;
nfa_initials_buckets_dataout <= grp_nfa_get_initials_fu_497_nfa_initials_buckets_dataout;
nfa_initials_buckets_req_din <= grp_nfa_get_initials_fu_497_nfa_initials_buckets_req_din;
nfa_initials_buckets_req_write <= grp_nfa_get_initials_fu_497_nfa_initials_buckets_req_write;
nfa_initials_buckets_rsp_read <= grp_nfa_get_initials_fu_497_nfa_initials_buckets_rsp_read;
nfa_initials_buckets_size <= grp_nfa_get_initials_fu_497_nfa_initials_buckets_size;
or_cond_fu_744_p2 <= (r_reg_440 xor accept);
p_rec_i_fu_577_p2 <= std_logic_vector(unsigned(p_01_rec_i_reg_275) + unsigned(ap_const_lv64_1));
r_bit_p_bsf32_hw_fu_509_bus_r <= bus_assign_reg_286;
sample_buffer_address <= sample_buffer_addr_reg_838;
sample_buffer_dataout <= ap_const_lv8_0;
sample_buffer_req_din <= ap_const_logic_0;
-- sample_buffer_req_write assign process. --
sample_buffer_req_write_assign_proc : process(ap_CS_fsm)
begin
if ((ap_ST_st11_fsm_10 = ap_CS_fsm)) then
sample_buffer_req_write <= ap_const_logic_1;
else
sample_buffer_req_write <= ap_const_logic_0;
end if;
end process;
-- sample_buffer_rsp_read assign process. --
sample_buffer_rsp_read_assign_proc : process(ap_CS_fsm, sample_buffer_rsp_empty_n)
begin
if (((ap_ST_st13_fsm_12 = ap_CS_fsm) and not((sample_buffer_rsp_empty_n = ap_const_logic_0)))) then
sample_buffer_rsp_read <= ap_const_logic_1;
else
sample_buffer_rsp_read <= ap_const_logic_0;
end if;
end process;
sample_buffer_size <= ap_const_lv32_1;
state_fu_626_p2 <= std_logic_vector(unsigned(tmp_i1_fu_614_p3) + unsigned(tmp_8_fu_622_p1));
stop_on_first_read_read_fu_152_p2 <= stop_on_first;
sum_fu_555_p2 <= std_logic_vector(unsigned(p_01_rec_i_reg_275) + unsigned(tmp_6_reg_833));
tmp_18_1_i_fu_589_p2 <= "1" when (next_buckets_1_reg_244 = ap_const_lv32_0) else "0";
tmp_18_i_fu_583_p2 <= "1" when (next_buckets_0_reg_254 = ap_const_lv32_0) else "0";
tmp_1_fu_732_p2 <= (current_buckets_1_1_fu_727_p2 or current_buckets_0_1_fu_722_p2);
tmp_4_fu_738_p2 <= "0" when (tmp_1_fu_732_p2 = ap_const_lv32_0) else "1";
tmp_4_i_fu_639_p0 <= tmp_4_i_fu_639_p00(8 - 1 downto 0);
tmp_4_i_fu_639_p00 <= std_logic_vector(resize(unsigned(nfa_symbols),14));
tmp_4_i_fu_639_p1 <= tmp_4_i_fu_639_p10(6 - 1 downto 0);
tmp_4_i_fu_639_p10 <= std_logic_vector(resize(unsigned(state_reg_893),14));
tmp_4_i_fu_639_p2 <= std_logic_vector(resize(unsigned(tmp_4_i_fu_639_p0) * unsigned(tmp_4_i_fu_639_p1), 14));
tmp_5_fu_610_p1 <= j_bucket_index1_reg_397(1 - 1 downto 0);
tmp_5_i_cast_fu_607_p1 <= std_logic_vector(resize(unsigned(sym_reg_857),14));
tmp_6_fu_551_p1 <= std_logic_vector(resize(unsigned(grp_sample_iterator_get_offset_fu_485_ap_return),64));
tmp_6_i_fu_645_p2 <= std_logic_vector(unsigned(tmp_4_i_fu_639_p2) + unsigned(tmp_5_i_cast_reg_888));
tmp_7_fu_566_p2 <= "1" when (unsigned(i_0_i_reg_264) < unsigned(sample_length)) else "0";
tmp_7_i_cast_fu_657_p1 <= std_logic_vector(resize(unsigned(tmp_7_i_fu_650_p3),64));
tmp_7_i_fu_650_p3 <= (tmp_6_i_reg_898 & ap_const_lv1_0);
tmp_8_fu_622_p1 <= j_bit1_reg_407(6 - 1 downto 0);
tmp_8_i_cast_fu_691_p1 <= std_logic_vector(resize(unsigned(tmp_8_i_fu_684_p3),64));
tmp_8_i_fu_684_p3 <= (tmp_6_i_reg_898 & ap_const_lv1_1);
tmp_i1_fu_614_p3 <= (tmp_5_fu_610_p1 & ap_const_lv5_0);
tmp_i_12_fu_532_p2 <= "1" when (i_index_reg_224 = end_index) else "0";
tmp_i_13_fu_537_p2 <= (tmp_i_fu_527_p2 and tmp_i_12_fu_532_p2);
tmp_i_fu_527_p2 <= "1" when (i_sample_reg_234 = end_sample) else "0";
end behav;
| lgpl-3.0 | 3a7e5738237efeae11b0d7925ffee92e | 0.602997 | 2.739499 | false | false | false | false |
grwlf/vsim | vhdl/proc3.vhd | 1 | 634 | -- Subtypes
entity test is
end entity test;
architecture test_arch of test is
type vector is array (integer range <>) of integer;
subtype svec1 is vector (1 to 3);
subtype svec2 is vector (4 to 7);
procedure p1(variable v1 : inout svec2) is
begin
v1(4) := 4;
end procedure;
begin
main: process
variable v : svec1 := (0=>0, 1=>1, 2=>2, 3=>3);
begin
p1(v);
report integer'image(v(0));
report integer'image(v(1));
report integer'image(v(2));
report integer'image(v(3));
assert false report "end of simulation" severity failure;
end process;
end architecture test_arch;
| gpl-3.0 | d144ddc12b3f82bbaf75fafbec3dbf95 | 0.641956 | 3.019048 | false | true | false | false |
jairov4/accel-oil | impl/impl_test_single/hdl/system_microblaze_0_wrapper.vhd | 1 | 93,945 | -------------------------------------------------------------------------------
-- system_microblaze_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library microblaze_v8_50_c;
use microblaze_v8_50_c.all;
entity system_microblaze_0_wrapper is
port (
CLK : in std_logic;
RESET : in std_logic;
MB_RESET : in std_logic;
INTERRUPT : in std_logic;
INTERRUPT_ADDRESS : in std_logic_vector(0 to 31);
INTERRUPT_ACK : out std_logic_vector(0 to 1);
EXT_BRK : in std_logic;
EXT_NM_BRK : in std_logic;
DBG_STOP : in std_logic;
MB_Halted : out std_logic;
MB_Error : out std_logic;
WAKEUP : in std_logic_vector(0 to 1);
SLEEP : out std_logic;
DBG_WAKEUP : out std_logic;
LOCKSTEP_MASTER_OUT : out std_logic_vector(0 to 4095);
LOCKSTEP_SLAVE_IN : in std_logic_vector(0 to 4095);
LOCKSTEP_OUT : out std_logic_vector(0 to 4095);
INSTR : in std_logic_vector(0 to 31);
IREADY : in std_logic;
IWAIT : in std_logic;
ICE : in std_logic;
IUE : in std_logic;
INSTR_ADDR : out std_logic_vector(0 to 31);
IFETCH : out std_logic;
I_AS : out std_logic;
IPLB_M_ABort : out std_logic;
IPLB_M_ABus : out std_logic_vector(0 to 31);
IPLB_M_UABus : out std_logic_vector(0 to 31);
IPLB_M_BE : out std_logic_vector(0 to 7);
IPLB_M_busLock : out std_logic;
IPLB_M_lockErr : out std_logic;
IPLB_M_MSize : out std_logic_vector(0 to 1);
IPLB_M_priority : out std_logic_vector(0 to 1);
IPLB_M_rdBurst : out std_logic;
IPLB_M_request : out std_logic;
IPLB_M_RNW : out std_logic;
IPLB_M_size : out std_logic_vector(0 to 3);
IPLB_M_TAttribute : out std_logic_vector(0 to 15);
IPLB_M_type : out std_logic_vector(0 to 2);
IPLB_M_wrBurst : out std_logic;
IPLB_M_wrDBus : out std_logic_vector(0 to 63);
IPLB_MBusy : in std_logic;
IPLB_MRdErr : in std_logic;
IPLB_MWrErr : in std_logic;
IPLB_MIRQ : in std_logic;
IPLB_MWrBTerm : in std_logic;
IPLB_MWrDAck : in std_logic;
IPLB_MAddrAck : in std_logic;
IPLB_MRdBTerm : in std_logic;
IPLB_MRdDAck : in std_logic;
IPLB_MRdDBus : in std_logic_vector(0 to 63);
IPLB_MRdWdAddr : in std_logic_vector(0 to 3);
IPLB_MRearbitrate : in std_logic;
IPLB_MSSize : in std_logic_vector(0 to 1);
IPLB_MTimeout : in std_logic;
DATA_READ : in std_logic_vector(0 to 31);
DREADY : in std_logic;
DWAIT : in std_logic;
DCE : in std_logic;
DUE : in std_logic;
DATA_WRITE : out std_logic_vector(0 to 31);
DATA_ADDR : out std_logic_vector(0 to 31);
D_AS : out std_logic;
READ_STROBE : out std_logic;
WRITE_STROBE : out std_logic;
BYTE_ENABLE : out std_logic_vector(0 to 3);
DPLB_M_ABort : out std_logic;
DPLB_M_ABus : out std_logic_vector(0 to 31);
DPLB_M_UABus : out std_logic_vector(0 to 31);
DPLB_M_BE : out std_logic_vector(0 to 7);
DPLB_M_busLock : out std_logic;
DPLB_M_lockErr : out std_logic;
DPLB_M_MSize : out std_logic_vector(0 to 1);
DPLB_M_priority : out std_logic_vector(0 to 1);
DPLB_M_rdBurst : out std_logic;
DPLB_M_request : out std_logic;
DPLB_M_RNW : out std_logic;
DPLB_M_size : out std_logic_vector(0 to 3);
DPLB_M_TAttribute : out std_logic_vector(0 to 15);
DPLB_M_type : out std_logic_vector(0 to 2);
DPLB_M_wrBurst : out std_logic;
DPLB_M_wrDBus : out std_logic_vector(0 to 63);
DPLB_MBusy : in std_logic;
DPLB_MRdErr : in std_logic;
DPLB_MWrErr : in std_logic;
DPLB_MIRQ : in std_logic;
DPLB_MWrBTerm : in std_logic;
DPLB_MWrDAck : in std_logic;
DPLB_MAddrAck : in std_logic;
DPLB_MRdBTerm : in std_logic;
DPLB_MRdDAck : in std_logic;
DPLB_MRdDBus : in std_logic_vector(0 to 63);
DPLB_MRdWdAddr : in std_logic_vector(0 to 3);
DPLB_MRearbitrate : in std_logic;
DPLB_MSSize : in std_logic_vector(0 to 1);
DPLB_MTimeout : in std_logic;
M_AXI_IP_AWID : out std_logic_vector(0 downto 0);
M_AXI_IP_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_IP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_AWLOCK : out std_logic;
M_AXI_IP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_AWVALID : out std_logic;
M_AXI_IP_AWREADY : in std_logic;
M_AXI_IP_WDATA : out std_logic_vector(31 downto 0);
M_AXI_IP_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_IP_WLAST : out std_logic;
M_AXI_IP_WVALID : out std_logic;
M_AXI_IP_WREADY : in std_logic;
M_AXI_IP_BID : in std_logic_vector(0 downto 0);
M_AXI_IP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_BVALID : in std_logic;
M_AXI_IP_BREADY : out std_logic;
M_AXI_IP_ARID : out std_logic_vector(0 downto 0);
M_AXI_IP_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_IP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_ARLOCK : out std_logic;
M_AXI_IP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_ARVALID : out std_logic;
M_AXI_IP_ARREADY : in std_logic;
M_AXI_IP_RID : in std_logic_vector(0 downto 0);
M_AXI_IP_RDATA : in std_logic_vector(31 downto 0);
M_AXI_IP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_RLAST : in std_logic;
M_AXI_IP_RVALID : in std_logic;
M_AXI_IP_RREADY : out std_logic;
M_AXI_DP_AWID : out std_logic_vector(0 downto 0);
M_AXI_DP_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_DP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_AWLOCK : out std_logic;
M_AXI_DP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_AWVALID : out std_logic;
M_AXI_DP_AWREADY : in std_logic;
M_AXI_DP_WDATA : out std_logic_vector(31 downto 0);
M_AXI_DP_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_DP_WLAST : out std_logic;
M_AXI_DP_WVALID : out std_logic;
M_AXI_DP_WREADY : in std_logic;
M_AXI_DP_BID : in std_logic_vector(0 downto 0);
M_AXI_DP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_BVALID : in std_logic;
M_AXI_DP_BREADY : out std_logic;
M_AXI_DP_ARID : out std_logic_vector(0 downto 0);
M_AXI_DP_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_DP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_ARLOCK : out std_logic;
M_AXI_DP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_ARVALID : out std_logic;
M_AXI_DP_ARREADY : in std_logic;
M_AXI_DP_RID : in std_logic_vector(0 downto 0);
M_AXI_DP_RDATA : in std_logic_vector(31 downto 0);
M_AXI_DP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_RLAST : in std_logic;
M_AXI_DP_RVALID : in std_logic;
M_AXI_DP_RREADY : out std_logic;
M_AXI_IC_AWID : out std_logic_vector(0 downto 0);
M_AXI_IC_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_IC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_AWLOCK : out std_logic;
M_AXI_IC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_AWVALID : out std_logic;
M_AXI_IC_AWREADY : in std_logic;
M_AXI_IC_AWUSER : out std_logic_vector(4 downto 0);
M_AXI_IC_AWDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_IC_AWSNOOP : out std_logic_vector(2 downto 0);
M_AXI_IC_AWBAR : out std_logic_vector(1 downto 0);
M_AXI_IC_WDATA : out std_logic_vector(31 downto 0);
M_AXI_IC_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_IC_WLAST : out std_logic;
M_AXI_IC_WVALID : out std_logic;
M_AXI_IC_WREADY : in std_logic;
M_AXI_IC_WUSER : out std_logic_vector(0 downto 0);
M_AXI_IC_BID : in std_logic_vector(0 downto 0);
M_AXI_IC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IC_BVALID : in std_logic;
M_AXI_IC_BREADY : out std_logic;
M_AXI_IC_BUSER : in std_logic_vector(0 downto 0);
M_AXI_IC_WACK : out std_logic;
M_AXI_IC_ARID : out std_logic_vector(0 downto 0);
M_AXI_IC_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_IC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_ARLOCK : out std_logic;
M_AXI_IC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_ARVALID : out std_logic;
M_AXI_IC_ARREADY : in std_logic;
M_AXI_IC_ARUSER : out std_logic_vector(4 downto 0);
M_AXI_IC_ARDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_IC_ARSNOOP : out std_logic_vector(3 downto 0);
M_AXI_IC_ARBAR : out std_logic_vector(1 downto 0);
M_AXI_IC_RID : in std_logic_vector(0 downto 0);
M_AXI_IC_RDATA : in std_logic_vector(31 downto 0);
M_AXI_IC_RRESP : in std_logic_vector(1 downto 0);
M_AXI_IC_RLAST : in std_logic;
M_AXI_IC_RVALID : in std_logic;
M_AXI_IC_RREADY : out std_logic;
M_AXI_IC_RUSER : in std_logic_vector(0 downto 0);
M_AXI_IC_RACK : out std_logic;
M_AXI_IC_ACVALID : in std_logic;
M_AXI_IC_ACADDR : in std_logic_vector(31 downto 0);
M_AXI_IC_ACSNOOP : in std_logic_vector(3 downto 0);
M_AXI_IC_ACPROT : in std_logic_vector(2 downto 0);
M_AXI_IC_ACREADY : out std_logic;
M_AXI_IC_CRREADY : in std_logic;
M_AXI_IC_CRVALID : out std_logic;
M_AXI_IC_CRRESP : out std_logic_vector(4 downto 0);
M_AXI_IC_CDVALID : out std_logic;
M_AXI_IC_CDREADY : in std_logic;
M_AXI_IC_CDDATA : out std_logic_vector(31 downto 0);
M_AXI_IC_CDLAST : out std_logic;
M_AXI_DC_AWID : out std_logic_vector(0 downto 0);
M_AXI_DC_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_DC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_AWLOCK : out std_logic;
M_AXI_DC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_AWVALID : out std_logic;
M_AXI_DC_AWREADY : in std_logic;
M_AXI_DC_AWUSER : out std_logic_vector(4 downto 0);
M_AXI_DC_AWDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_DC_AWSNOOP : out std_logic_vector(2 downto 0);
M_AXI_DC_AWBAR : out std_logic_vector(1 downto 0);
M_AXI_DC_WDATA : out std_logic_vector(31 downto 0);
M_AXI_DC_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_DC_WLAST : out std_logic;
M_AXI_DC_WVALID : out std_logic;
M_AXI_DC_WREADY : in std_logic;
M_AXI_DC_WUSER : out std_logic_vector(0 downto 0);
M_AXI_DC_BID : in std_logic_vector(0 downto 0);
M_AXI_DC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DC_BVALID : in std_logic;
M_AXI_DC_BREADY : out std_logic;
M_AXI_DC_BUSER : in std_logic_vector(0 downto 0);
M_AXI_DC_WACK : out std_logic;
M_AXI_DC_ARID : out std_logic_vector(0 downto 0);
M_AXI_DC_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_DC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_ARLOCK : out std_logic;
M_AXI_DC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_ARVALID : out std_logic;
M_AXI_DC_ARREADY : in std_logic;
M_AXI_DC_ARUSER : out std_logic_vector(4 downto 0);
M_AXI_DC_ARDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_DC_ARSNOOP : out std_logic_vector(3 downto 0);
M_AXI_DC_ARBAR : out std_logic_vector(1 downto 0);
M_AXI_DC_RID : in std_logic_vector(0 downto 0);
M_AXI_DC_RDATA : in std_logic_vector(31 downto 0);
M_AXI_DC_RRESP : in std_logic_vector(1 downto 0);
M_AXI_DC_RLAST : in std_logic;
M_AXI_DC_RVALID : in std_logic;
M_AXI_DC_RREADY : out std_logic;
M_AXI_DC_RUSER : in std_logic_vector(0 downto 0);
M_AXI_DC_RACK : out std_logic;
M_AXI_DC_ACVALID : in std_logic;
M_AXI_DC_ACADDR : in std_logic_vector(31 downto 0);
M_AXI_DC_ACSNOOP : in std_logic_vector(3 downto 0);
M_AXI_DC_ACPROT : in std_logic_vector(2 downto 0);
M_AXI_DC_ACREADY : out std_logic;
M_AXI_DC_CRREADY : in std_logic;
M_AXI_DC_CRVALID : out std_logic;
M_AXI_DC_CRRESP : out std_logic_vector(4 downto 0);
M_AXI_DC_CDVALID : out std_logic;
M_AXI_DC_CDREADY : in std_logic;
M_AXI_DC_CDDATA : out std_logic_vector(31 downto 0);
M_AXI_DC_CDLAST : out std_logic;
DBG_CLK : in std_logic;
DBG_TDI : in std_logic;
DBG_TDO : out std_logic;
DBG_REG_EN : in std_logic_vector(0 to 7);
DBG_SHIFT : in std_logic;
DBG_CAPTURE : in std_logic;
DBG_UPDATE : in std_logic;
DEBUG_RST : in std_logic;
Trace_Instruction : out std_logic_vector(0 to 31);
Trace_Valid_Instr : out std_logic;
Trace_PC : out std_logic_vector(0 to 31);
Trace_Reg_Write : out std_logic;
Trace_Reg_Addr : out std_logic_vector(0 to 4);
Trace_MSR_Reg : out std_logic_vector(0 to 14);
Trace_PID_Reg : out std_logic_vector(0 to 7);
Trace_New_Reg_Value : out std_logic_vector(0 to 31);
Trace_Exception_Taken : out std_logic;
Trace_Exception_Kind : out std_logic_vector(0 to 4);
Trace_Jump_Taken : out std_logic;
Trace_Delay_Slot : out std_logic;
Trace_Data_Address : out std_logic_vector(0 to 31);
Trace_Data_Access : out std_logic;
Trace_Data_Read : out std_logic;
Trace_Data_Write : out std_logic;
Trace_Data_Write_Value : out std_logic_vector(0 to 31);
Trace_Data_Byte_Enable : out std_logic_vector(0 to 3);
Trace_DCache_Req : out std_logic;
Trace_DCache_Hit : out std_logic;
Trace_DCache_Rdy : out std_logic;
Trace_DCache_Read : out std_logic;
Trace_ICache_Req : out std_logic;
Trace_ICache_Hit : out std_logic;
Trace_ICache_Rdy : out std_logic;
Trace_OF_PipeRun : out std_logic;
Trace_EX_PipeRun : out std_logic;
Trace_MEM_PipeRun : out std_logic;
Trace_MB_Halted : out std_logic;
Trace_Jump_Hit : out std_logic;
FSL0_S_CLK : out std_logic;
FSL0_S_READ : out std_logic;
FSL0_S_DATA : in std_logic_vector(0 to 31);
FSL0_S_CONTROL : in std_logic;
FSL0_S_EXISTS : in std_logic;
FSL0_M_CLK : out std_logic;
FSL0_M_WRITE : out std_logic;
FSL0_M_DATA : out std_logic_vector(0 to 31);
FSL0_M_CONTROL : out std_logic;
FSL0_M_FULL : in std_logic;
FSL1_S_CLK : out std_logic;
FSL1_S_READ : out std_logic;
FSL1_S_DATA : in std_logic_vector(0 to 31);
FSL1_S_CONTROL : in std_logic;
FSL1_S_EXISTS : in std_logic;
FSL1_M_CLK : out std_logic;
FSL1_M_WRITE : out std_logic;
FSL1_M_DATA : out std_logic_vector(0 to 31);
FSL1_M_CONTROL : out std_logic;
FSL1_M_FULL : in std_logic;
FSL2_S_CLK : out std_logic;
FSL2_S_READ : out std_logic;
FSL2_S_DATA : in std_logic_vector(0 to 31);
FSL2_S_CONTROL : in std_logic;
FSL2_S_EXISTS : in std_logic;
FSL2_M_CLK : out std_logic;
FSL2_M_WRITE : out std_logic;
FSL2_M_DATA : out std_logic_vector(0 to 31);
FSL2_M_CONTROL : out std_logic;
FSL2_M_FULL : in std_logic;
FSL3_S_CLK : out std_logic;
FSL3_S_READ : out std_logic;
FSL3_S_DATA : in std_logic_vector(0 to 31);
FSL3_S_CONTROL : in std_logic;
FSL3_S_EXISTS : in std_logic;
FSL3_M_CLK : out std_logic;
FSL3_M_WRITE : out std_logic;
FSL3_M_DATA : out std_logic_vector(0 to 31);
FSL3_M_CONTROL : out std_logic;
FSL3_M_FULL : in std_logic;
FSL4_S_CLK : out std_logic;
FSL4_S_READ : out std_logic;
FSL4_S_DATA : in std_logic_vector(0 to 31);
FSL4_S_CONTROL : in std_logic;
FSL4_S_EXISTS : in std_logic;
FSL4_M_CLK : out std_logic;
FSL4_M_WRITE : out std_logic;
FSL4_M_DATA : out std_logic_vector(0 to 31);
FSL4_M_CONTROL : out std_logic;
FSL4_M_FULL : in std_logic;
FSL5_S_CLK : out std_logic;
FSL5_S_READ : out std_logic;
FSL5_S_DATA : in std_logic_vector(0 to 31);
FSL5_S_CONTROL : in std_logic;
FSL5_S_EXISTS : in std_logic;
FSL5_M_CLK : out std_logic;
FSL5_M_WRITE : out std_logic;
FSL5_M_DATA : out std_logic_vector(0 to 31);
FSL5_M_CONTROL : out std_logic;
FSL5_M_FULL : in std_logic;
FSL6_S_CLK : out std_logic;
FSL6_S_READ : out std_logic;
FSL6_S_DATA : in std_logic_vector(0 to 31);
FSL6_S_CONTROL : in std_logic;
FSL6_S_EXISTS : in std_logic;
FSL6_M_CLK : out std_logic;
FSL6_M_WRITE : out std_logic;
FSL6_M_DATA : out std_logic_vector(0 to 31);
FSL6_M_CONTROL : out std_logic;
FSL6_M_FULL : in std_logic;
FSL7_S_CLK : out std_logic;
FSL7_S_READ : out std_logic;
FSL7_S_DATA : in std_logic_vector(0 to 31);
FSL7_S_CONTROL : in std_logic;
FSL7_S_EXISTS : in std_logic;
FSL7_M_CLK : out std_logic;
FSL7_M_WRITE : out std_logic;
FSL7_M_DATA : out std_logic_vector(0 to 31);
FSL7_M_CONTROL : out std_logic;
FSL7_M_FULL : in std_logic;
FSL8_S_CLK : out std_logic;
FSL8_S_READ : out std_logic;
FSL8_S_DATA : in std_logic_vector(0 to 31);
FSL8_S_CONTROL : in std_logic;
FSL8_S_EXISTS : in std_logic;
FSL8_M_CLK : out std_logic;
FSL8_M_WRITE : out std_logic;
FSL8_M_DATA : out std_logic_vector(0 to 31);
FSL8_M_CONTROL : out std_logic;
FSL8_M_FULL : in std_logic;
FSL9_S_CLK : out std_logic;
FSL9_S_READ : out std_logic;
FSL9_S_DATA : in std_logic_vector(0 to 31);
FSL9_S_CONTROL : in std_logic;
FSL9_S_EXISTS : in std_logic;
FSL9_M_CLK : out std_logic;
FSL9_M_WRITE : out std_logic;
FSL9_M_DATA : out std_logic_vector(0 to 31);
FSL9_M_CONTROL : out std_logic;
FSL9_M_FULL : in std_logic;
FSL10_S_CLK : out std_logic;
FSL10_S_READ : out std_logic;
FSL10_S_DATA : in std_logic_vector(0 to 31);
FSL10_S_CONTROL : in std_logic;
FSL10_S_EXISTS : in std_logic;
FSL10_M_CLK : out std_logic;
FSL10_M_WRITE : out std_logic;
FSL10_M_DATA : out std_logic_vector(0 to 31);
FSL10_M_CONTROL : out std_logic;
FSL10_M_FULL : in std_logic;
FSL11_S_CLK : out std_logic;
FSL11_S_READ : out std_logic;
FSL11_S_DATA : in std_logic_vector(0 to 31);
FSL11_S_CONTROL : in std_logic;
FSL11_S_EXISTS : in std_logic;
FSL11_M_CLK : out std_logic;
FSL11_M_WRITE : out std_logic;
FSL11_M_DATA : out std_logic_vector(0 to 31);
FSL11_M_CONTROL : out std_logic;
FSL11_M_FULL : in std_logic;
FSL12_S_CLK : out std_logic;
FSL12_S_READ : out std_logic;
FSL12_S_DATA : in std_logic_vector(0 to 31);
FSL12_S_CONTROL : in std_logic;
FSL12_S_EXISTS : in std_logic;
FSL12_M_CLK : out std_logic;
FSL12_M_WRITE : out std_logic;
FSL12_M_DATA : out std_logic_vector(0 to 31);
FSL12_M_CONTROL : out std_logic;
FSL12_M_FULL : in std_logic;
FSL13_S_CLK : out std_logic;
FSL13_S_READ : out std_logic;
FSL13_S_DATA : in std_logic_vector(0 to 31);
FSL13_S_CONTROL : in std_logic;
FSL13_S_EXISTS : in std_logic;
FSL13_M_CLK : out std_logic;
FSL13_M_WRITE : out std_logic;
FSL13_M_DATA : out std_logic_vector(0 to 31);
FSL13_M_CONTROL : out std_logic;
FSL13_M_FULL : in std_logic;
FSL14_S_CLK : out std_logic;
FSL14_S_READ : out std_logic;
FSL14_S_DATA : in std_logic_vector(0 to 31);
FSL14_S_CONTROL : in std_logic;
FSL14_S_EXISTS : in std_logic;
FSL14_M_CLK : out std_logic;
FSL14_M_WRITE : out std_logic;
FSL14_M_DATA : out std_logic_vector(0 to 31);
FSL14_M_CONTROL : out std_logic;
FSL14_M_FULL : in std_logic;
FSL15_S_CLK : out std_logic;
FSL15_S_READ : out std_logic;
FSL15_S_DATA : in std_logic_vector(0 to 31);
FSL15_S_CONTROL : in std_logic;
FSL15_S_EXISTS : in std_logic;
FSL15_M_CLK : out std_logic;
FSL15_M_WRITE : out std_logic;
FSL15_M_DATA : out std_logic_vector(0 to 31);
FSL15_M_CONTROL : out std_logic;
FSL15_M_FULL : in std_logic;
M0_AXIS_TLAST : out std_logic;
M0_AXIS_TDATA : out std_logic_vector(31 downto 0);
M0_AXIS_TVALID : out std_logic;
M0_AXIS_TREADY : in std_logic;
S0_AXIS_TLAST : in std_logic;
S0_AXIS_TDATA : in std_logic_vector(31 downto 0);
S0_AXIS_TVALID : in std_logic;
S0_AXIS_TREADY : out std_logic;
M1_AXIS_TLAST : out std_logic;
M1_AXIS_TDATA : out std_logic_vector(31 downto 0);
M1_AXIS_TVALID : out std_logic;
M1_AXIS_TREADY : in std_logic;
S1_AXIS_TLAST : in std_logic;
S1_AXIS_TDATA : in std_logic_vector(31 downto 0);
S1_AXIS_TVALID : in std_logic;
S1_AXIS_TREADY : out std_logic;
M2_AXIS_TLAST : out std_logic;
M2_AXIS_TDATA : out std_logic_vector(31 downto 0);
M2_AXIS_TVALID : out std_logic;
M2_AXIS_TREADY : in std_logic;
S2_AXIS_TLAST : in std_logic;
S2_AXIS_TDATA : in std_logic_vector(31 downto 0);
S2_AXIS_TVALID : in std_logic;
S2_AXIS_TREADY : out std_logic;
M3_AXIS_TLAST : out std_logic;
M3_AXIS_TDATA : out std_logic_vector(31 downto 0);
M3_AXIS_TVALID : out std_logic;
M3_AXIS_TREADY : in std_logic;
S3_AXIS_TLAST : in std_logic;
S3_AXIS_TDATA : in std_logic_vector(31 downto 0);
S3_AXIS_TVALID : in std_logic;
S3_AXIS_TREADY : out std_logic;
M4_AXIS_TLAST : out std_logic;
M4_AXIS_TDATA : out std_logic_vector(31 downto 0);
M4_AXIS_TVALID : out std_logic;
M4_AXIS_TREADY : in std_logic;
S4_AXIS_TLAST : in std_logic;
S4_AXIS_TDATA : in std_logic_vector(31 downto 0);
S4_AXIS_TVALID : in std_logic;
S4_AXIS_TREADY : out std_logic;
M5_AXIS_TLAST : out std_logic;
M5_AXIS_TDATA : out std_logic_vector(31 downto 0);
M5_AXIS_TVALID : out std_logic;
M5_AXIS_TREADY : in std_logic;
S5_AXIS_TLAST : in std_logic;
S5_AXIS_TDATA : in std_logic_vector(31 downto 0);
S5_AXIS_TVALID : in std_logic;
S5_AXIS_TREADY : out std_logic;
M6_AXIS_TLAST : out std_logic;
M6_AXIS_TDATA : out std_logic_vector(31 downto 0);
M6_AXIS_TVALID : out std_logic;
M6_AXIS_TREADY : in std_logic;
S6_AXIS_TLAST : in std_logic;
S6_AXIS_TDATA : in std_logic_vector(31 downto 0);
S6_AXIS_TVALID : in std_logic;
S6_AXIS_TREADY : out std_logic;
M7_AXIS_TLAST : out std_logic;
M7_AXIS_TDATA : out std_logic_vector(31 downto 0);
M7_AXIS_TVALID : out std_logic;
M7_AXIS_TREADY : in std_logic;
S7_AXIS_TLAST : in std_logic;
S7_AXIS_TDATA : in std_logic_vector(31 downto 0);
S7_AXIS_TVALID : in std_logic;
S7_AXIS_TREADY : out std_logic;
M8_AXIS_TLAST : out std_logic;
M8_AXIS_TDATA : out std_logic_vector(31 downto 0);
M8_AXIS_TVALID : out std_logic;
M8_AXIS_TREADY : in std_logic;
S8_AXIS_TLAST : in std_logic;
S8_AXIS_TDATA : in std_logic_vector(31 downto 0);
S8_AXIS_TVALID : in std_logic;
S8_AXIS_TREADY : out std_logic;
M9_AXIS_TLAST : out std_logic;
M9_AXIS_TDATA : out std_logic_vector(31 downto 0);
M9_AXIS_TVALID : out std_logic;
M9_AXIS_TREADY : in std_logic;
S9_AXIS_TLAST : in std_logic;
S9_AXIS_TDATA : in std_logic_vector(31 downto 0);
S9_AXIS_TVALID : in std_logic;
S9_AXIS_TREADY : out std_logic;
M10_AXIS_TLAST : out std_logic;
M10_AXIS_TDATA : out std_logic_vector(31 downto 0);
M10_AXIS_TVALID : out std_logic;
M10_AXIS_TREADY : in std_logic;
S10_AXIS_TLAST : in std_logic;
S10_AXIS_TDATA : in std_logic_vector(31 downto 0);
S10_AXIS_TVALID : in std_logic;
S10_AXIS_TREADY : out std_logic;
M11_AXIS_TLAST : out std_logic;
M11_AXIS_TDATA : out std_logic_vector(31 downto 0);
M11_AXIS_TVALID : out std_logic;
M11_AXIS_TREADY : in std_logic;
S11_AXIS_TLAST : in std_logic;
S11_AXIS_TDATA : in std_logic_vector(31 downto 0);
S11_AXIS_TVALID : in std_logic;
S11_AXIS_TREADY : out std_logic;
M12_AXIS_TLAST : out std_logic;
M12_AXIS_TDATA : out std_logic_vector(31 downto 0);
M12_AXIS_TVALID : out std_logic;
M12_AXIS_TREADY : in std_logic;
S12_AXIS_TLAST : in std_logic;
S12_AXIS_TDATA : in std_logic_vector(31 downto 0);
S12_AXIS_TVALID : in std_logic;
S12_AXIS_TREADY : out std_logic;
M13_AXIS_TLAST : out std_logic;
M13_AXIS_TDATA : out std_logic_vector(31 downto 0);
M13_AXIS_TVALID : out std_logic;
M13_AXIS_TREADY : in std_logic;
S13_AXIS_TLAST : in std_logic;
S13_AXIS_TDATA : in std_logic_vector(31 downto 0);
S13_AXIS_TVALID : in std_logic;
S13_AXIS_TREADY : out std_logic;
M14_AXIS_TLAST : out std_logic;
M14_AXIS_TDATA : out std_logic_vector(31 downto 0);
M14_AXIS_TVALID : out std_logic;
M14_AXIS_TREADY : in std_logic;
S14_AXIS_TLAST : in std_logic;
S14_AXIS_TDATA : in std_logic_vector(31 downto 0);
S14_AXIS_TVALID : in std_logic;
S14_AXIS_TREADY : out std_logic;
M15_AXIS_TLAST : out std_logic;
M15_AXIS_TDATA : out std_logic_vector(31 downto 0);
M15_AXIS_TVALID : out std_logic;
M15_AXIS_TREADY : in std_logic;
S15_AXIS_TLAST : in std_logic;
S15_AXIS_TDATA : in std_logic_vector(31 downto 0);
S15_AXIS_TVALID : in std_logic;
S15_AXIS_TREADY : out std_logic;
ICACHE_FSL_IN_CLK : out std_logic;
ICACHE_FSL_IN_READ : out std_logic;
ICACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
ICACHE_FSL_IN_CONTROL : in std_logic;
ICACHE_FSL_IN_EXISTS : in std_logic;
ICACHE_FSL_OUT_CLK : out std_logic;
ICACHE_FSL_OUT_WRITE : out std_logic;
ICACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
ICACHE_FSL_OUT_CONTROL : out std_logic;
ICACHE_FSL_OUT_FULL : in std_logic;
DCACHE_FSL_IN_CLK : out std_logic;
DCACHE_FSL_IN_READ : out std_logic;
DCACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
DCACHE_FSL_IN_CONTROL : in std_logic;
DCACHE_FSL_IN_EXISTS : in std_logic;
DCACHE_FSL_OUT_CLK : out std_logic;
DCACHE_FSL_OUT_WRITE : out std_logic;
DCACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
DCACHE_FSL_OUT_CONTROL : out std_logic;
DCACHE_FSL_OUT_FULL : in std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of system_microblaze_0_wrapper : entity is "microblaze_v8_50_c";
end system_microblaze_0_wrapper;
architecture STRUCTURE of system_microblaze_0_wrapper is
component microblaze is
generic (
C_SCO : integer;
C_FREQ : integer;
C_DATA_SIZE : integer;
C_DYNAMIC_BUS_SIZING : integer;
C_FAMILY : string;
C_INSTANCE : string;
C_AVOID_PRIMITIVES : integer;
C_FAULT_TOLERANT : integer;
C_ECC_USE_CE_EXCEPTION : integer;
C_LOCKSTEP_SLAVE : integer;
C_ENDIANNESS : integer;
C_AREA_OPTIMIZED : integer;
C_OPTIMIZATION : integer;
C_INTERCONNECT : integer;
C_STREAM_INTERCONNECT : integer;
C_BASE_VECTORS : std_logic_vector;
C_DPLB_DWIDTH : integer;
C_DPLB_NATIVE_DWIDTH : integer;
C_DPLB_BURST_EN : integer;
C_DPLB_P2P : integer;
C_IPLB_DWIDTH : integer;
C_IPLB_NATIVE_DWIDTH : integer;
C_IPLB_BURST_EN : integer;
C_IPLB_P2P : integer;
C_M_AXI_DP_THREAD_ID_WIDTH : integer;
C_M_AXI_DP_DATA_WIDTH : integer;
C_M_AXI_DP_ADDR_WIDTH : integer;
C_M_AXI_DP_EXCLUSIVE_ACCESS : integer;
C_M_AXI_IP_THREAD_ID_WIDTH : integer;
C_M_AXI_IP_DATA_WIDTH : integer;
C_M_AXI_IP_ADDR_WIDTH : integer;
C_D_AXI : integer;
C_D_PLB : integer;
C_D_LMB : integer;
C_I_AXI : integer;
C_I_PLB : integer;
C_I_LMB : integer;
C_USE_MSR_INSTR : integer;
C_USE_PCMP_INSTR : integer;
C_USE_BARREL : integer;
C_USE_DIV : integer;
C_USE_HW_MUL : integer;
C_USE_FPU : integer;
C_USE_REORDER_INSTR : integer;
C_UNALIGNED_EXCEPTIONS : integer;
C_ILL_OPCODE_EXCEPTION : integer;
C_M_AXI_I_BUS_EXCEPTION : integer;
C_M_AXI_D_BUS_EXCEPTION : integer;
C_IPLB_BUS_EXCEPTION : integer;
C_DPLB_BUS_EXCEPTION : integer;
C_DIV_ZERO_EXCEPTION : integer;
C_FPU_EXCEPTION : integer;
C_FSL_EXCEPTION : integer;
C_USE_STACK_PROTECTION : integer;
C_PVR : integer;
C_PVR_USER1 : std_logic_vector(0 to 7);
C_PVR_USER2 : std_logic_vector(0 to 31);
C_DEBUG_ENABLED : integer;
C_NUMBER_OF_PC_BRK : integer;
C_NUMBER_OF_RD_ADDR_BRK : integer;
C_NUMBER_OF_WR_ADDR_BRK : integer;
C_INTERRUPT_IS_EDGE : integer;
C_EDGE_IS_POSITIVE : integer;
C_RESET_MSR : std_logic_vector;
C_OPCODE_0x0_ILLEGAL : integer;
C_FSL_LINKS : integer;
C_FSL_DATA_SIZE : integer;
C_USE_EXTENDED_FSL_INSTR : integer;
C_M0_AXIS_DATA_WIDTH : integer;
C_S0_AXIS_DATA_WIDTH : integer;
C_M1_AXIS_DATA_WIDTH : integer;
C_S1_AXIS_DATA_WIDTH : integer;
C_M2_AXIS_DATA_WIDTH : integer;
C_S2_AXIS_DATA_WIDTH : integer;
C_M3_AXIS_DATA_WIDTH : integer;
C_S3_AXIS_DATA_WIDTH : integer;
C_M4_AXIS_DATA_WIDTH : integer;
C_S4_AXIS_DATA_WIDTH : integer;
C_M5_AXIS_DATA_WIDTH : integer;
C_S5_AXIS_DATA_WIDTH : integer;
C_M6_AXIS_DATA_WIDTH : integer;
C_S6_AXIS_DATA_WIDTH : integer;
C_M7_AXIS_DATA_WIDTH : integer;
C_S7_AXIS_DATA_WIDTH : integer;
C_M8_AXIS_DATA_WIDTH : integer;
C_S8_AXIS_DATA_WIDTH : integer;
C_M9_AXIS_DATA_WIDTH : integer;
C_S9_AXIS_DATA_WIDTH : integer;
C_M10_AXIS_DATA_WIDTH : integer;
C_S10_AXIS_DATA_WIDTH : integer;
C_M11_AXIS_DATA_WIDTH : integer;
C_S11_AXIS_DATA_WIDTH : integer;
C_M12_AXIS_DATA_WIDTH : integer;
C_S12_AXIS_DATA_WIDTH : integer;
C_M13_AXIS_DATA_WIDTH : integer;
C_S13_AXIS_DATA_WIDTH : integer;
C_M14_AXIS_DATA_WIDTH : integer;
C_S14_AXIS_DATA_WIDTH : integer;
C_M15_AXIS_DATA_WIDTH : integer;
C_S15_AXIS_DATA_WIDTH : integer;
C_ICACHE_BASEADDR : std_logic_vector;
C_ICACHE_HIGHADDR : std_logic_vector;
C_USE_ICACHE : integer;
C_ALLOW_ICACHE_WR : integer;
C_ADDR_TAG_BITS : integer;
C_CACHE_BYTE_SIZE : integer;
C_ICACHE_USE_FSL : integer;
C_ICACHE_LINE_LEN : integer;
C_ICACHE_ALWAYS_USED : integer;
C_ICACHE_INTERFACE : integer;
C_ICACHE_VICTIMS : integer;
C_ICACHE_STREAMS : integer;
C_ICACHE_FORCE_TAG_LUTRAM : integer;
C_ICACHE_DATA_WIDTH : integer;
C_M_AXI_IC_THREAD_ID_WIDTH : integer;
C_M_AXI_IC_DATA_WIDTH : integer;
C_M_AXI_IC_ADDR_WIDTH : integer;
C_M_AXI_IC_USER_VALUE : integer;
C_M_AXI_IC_AWUSER_WIDTH : integer;
C_M_AXI_IC_ARUSER_WIDTH : integer;
C_M_AXI_IC_WUSER_WIDTH : integer;
C_M_AXI_IC_RUSER_WIDTH : integer;
C_M_AXI_IC_BUSER_WIDTH : integer;
C_DCACHE_BASEADDR : std_logic_vector;
C_DCACHE_HIGHADDR : std_logic_vector;
C_USE_DCACHE : integer;
C_ALLOW_DCACHE_WR : integer;
C_DCACHE_ADDR_TAG : integer;
C_DCACHE_BYTE_SIZE : integer;
C_DCACHE_USE_FSL : integer;
C_DCACHE_LINE_LEN : integer;
C_DCACHE_ALWAYS_USED : integer;
C_DCACHE_INTERFACE : integer;
C_DCACHE_USE_WRITEBACK : integer;
C_DCACHE_VICTIMS : integer;
C_DCACHE_FORCE_TAG_LUTRAM : integer;
C_DCACHE_DATA_WIDTH : integer;
C_M_AXI_DC_THREAD_ID_WIDTH : integer;
C_M_AXI_DC_DATA_WIDTH : integer;
C_M_AXI_DC_ADDR_WIDTH : integer;
C_M_AXI_DC_EXCLUSIVE_ACCESS : integer;
C_M_AXI_DC_USER_VALUE : integer;
C_M_AXI_DC_AWUSER_WIDTH : integer;
C_M_AXI_DC_ARUSER_WIDTH : integer;
C_M_AXI_DC_WUSER_WIDTH : integer;
C_M_AXI_DC_RUSER_WIDTH : integer;
C_M_AXI_DC_BUSER_WIDTH : integer;
C_USE_MMU : integer;
C_MMU_DTLB_SIZE : integer;
C_MMU_ITLB_SIZE : integer;
C_MMU_TLB_ACCESS : integer;
C_MMU_ZONES : integer;
C_MMU_PRIVILEGED_INSTR : integer;
C_USE_INTERRUPT : integer;
C_USE_EXT_BRK : integer;
C_USE_EXT_NM_BRK : integer;
C_USE_BRANCH_TARGET_CACHE : integer;
C_BRANCH_TARGET_CACHE_SIZE : integer;
C_PC_WIDTH : integer
);
port (
CLK : in std_logic;
RESET : in std_logic;
MB_RESET : in std_logic;
INTERRUPT : in std_logic;
INTERRUPT_ADDRESS : in std_logic_vector(0 to 31);
INTERRUPT_ACK : out std_logic_vector(0 to 1);
EXT_BRK : in std_logic;
EXT_NM_BRK : in std_logic;
DBG_STOP : in std_logic;
MB_Halted : out std_logic;
MB_Error : out std_logic;
WAKEUP : in std_logic_vector(0 to 1);
SLEEP : out std_logic;
DBG_WAKEUP : out std_logic;
LOCKSTEP_MASTER_OUT : out std_logic_vector(0 to 4095);
LOCKSTEP_SLAVE_IN : in std_logic_vector(0 to 4095);
LOCKSTEP_OUT : out std_logic_vector(0 to 4095);
INSTR : in std_logic_vector(0 to 31);
IREADY : in std_logic;
IWAIT : in std_logic;
ICE : in std_logic;
IUE : in std_logic;
INSTR_ADDR : out std_logic_vector(0 to 31);
IFETCH : out std_logic;
I_AS : out std_logic;
IPLB_M_ABort : out std_logic;
IPLB_M_ABus : out std_logic_vector(0 to 31);
IPLB_M_UABus : out std_logic_vector(0 to 31);
IPLB_M_BE : out std_logic_vector(0 to (C_IPLB_DWIDTH-1)/8);
IPLB_M_busLock : out std_logic;
IPLB_M_lockErr : out std_logic;
IPLB_M_MSize : out std_logic_vector(0 to 1);
IPLB_M_priority : out std_logic_vector(0 to 1);
IPLB_M_rdBurst : out std_logic;
IPLB_M_request : out std_logic;
IPLB_M_RNW : out std_logic;
IPLB_M_size : out std_logic_vector(0 to 3);
IPLB_M_TAttribute : out std_logic_vector(0 to 15);
IPLB_M_type : out std_logic_vector(0 to 2);
IPLB_M_wrBurst : out std_logic;
IPLB_M_wrDBus : out std_logic_vector(0 to C_IPLB_DWIDTH-1);
IPLB_MBusy : in std_logic;
IPLB_MRdErr : in std_logic;
IPLB_MWrErr : in std_logic;
IPLB_MIRQ : in std_logic;
IPLB_MWrBTerm : in std_logic;
IPLB_MWrDAck : in std_logic;
IPLB_MAddrAck : in std_logic;
IPLB_MRdBTerm : in std_logic;
IPLB_MRdDAck : in std_logic;
IPLB_MRdDBus : in std_logic_vector(0 to C_IPLB_DWIDTH-1);
IPLB_MRdWdAddr : in std_logic_vector(0 to 3);
IPLB_MRearbitrate : in std_logic;
IPLB_MSSize : in std_logic_vector(0 to 1);
IPLB_MTimeout : in std_logic;
DATA_READ : in std_logic_vector(0 to 31);
DREADY : in std_logic;
DWAIT : in std_logic;
DCE : in std_logic;
DUE : in std_logic;
DATA_WRITE : out std_logic_vector(0 to 31);
DATA_ADDR : out std_logic_vector(0 to 31);
D_AS : out std_logic;
READ_STROBE : out std_logic;
WRITE_STROBE : out std_logic;
BYTE_ENABLE : out std_logic_vector(0 to 3);
DPLB_M_ABort : out std_logic;
DPLB_M_ABus : out std_logic_vector(0 to 31);
DPLB_M_UABus : out std_logic_vector(0 to 31);
DPLB_M_BE : out std_logic_vector(0 to (C_DPLB_DWIDTH-1)/8);
DPLB_M_busLock : out std_logic;
DPLB_M_lockErr : out std_logic;
DPLB_M_MSize : out std_logic_vector(0 to 1);
DPLB_M_priority : out std_logic_vector(0 to 1);
DPLB_M_rdBurst : out std_logic;
DPLB_M_request : out std_logic;
DPLB_M_RNW : out std_logic;
DPLB_M_size : out std_logic_vector(0 to 3);
DPLB_M_TAttribute : out std_logic_vector(0 to 15);
DPLB_M_type : out std_logic_vector(0 to 2);
DPLB_M_wrBurst : out std_logic;
DPLB_M_wrDBus : out std_logic_vector(0 to C_DPLB_DWIDTH-1);
DPLB_MBusy : in std_logic;
DPLB_MRdErr : in std_logic;
DPLB_MWrErr : in std_logic;
DPLB_MIRQ : in std_logic;
DPLB_MWrBTerm : in std_logic;
DPLB_MWrDAck : in std_logic;
DPLB_MAddrAck : in std_logic;
DPLB_MRdBTerm : in std_logic;
DPLB_MRdDAck : in std_logic;
DPLB_MRdDBus : in std_logic_vector(0 to C_DPLB_DWIDTH-1);
DPLB_MRdWdAddr : in std_logic_vector(0 to 3);
DPLB_MRearbitrate : in std_logic;
DPLB_MSSize : in std_logic_vector(0 to 1);
DPLB_MTimeout : in std_logic;
M_AXI_IP_AWID : out std_logic_vector((C_M_AXI_IP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IP_AWADDR : out std_logic_vector((C_M_AXI_IP_ADDR_WIDTH-1) downto 0);
M_AXI_IP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_AWLOCK : out std_logic;
M_AXI_IP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_AWVALID : out std_logic;
M_AXI_IP_AWREADY : in std_logic;
M_AXI_IP_WDATA : out std_logic_vector((C_M_AXI_IP_DATA_WIDTH-1) downto 0);
M_AXI_IP_WSTRB : out std_logic_vector(((C_M_AXI_IP_DATA_WIDTH/8)-1) downto 0);
M_AXI_IP_WLAST : out std_logic;
M_AXI_IP_WVALID : out std_logic;
M_AXI_IP_WREADY : in std_logic;
M_AXI_IP_BID : in std_logic_vector((C_M_AXI_IP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_BVALID : in std_logic;
M_AXI_IP_BREADY : out std_logic;
M_AXI_IP_ARID : out std_logic_vector((C_M_AXI_IP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IP_ARADDR : out std_logic_vector((C_M_AXI_IP_ADDR_WIDTH-1) downto 0);
M_AXI_IP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_ARLOCK : out std_logic;
M_AXI_IP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_ARVALID : out std_logic;
M_AXI_IP_ARREADY : in std_logic;
M_AXI_IP_RID : in std_logic_vector((C_M_AXI_IP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IP_RDATA : in std_logic_vector((C_M_AXI_IP_DATA_WIDTH-1) downto 0);
M_AXI_IP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_RLAST : in std_logic;
M_AXI_IP_RVALID : in std_logic;
M_AXI_IP_RREADY : out std_logic;
M_AXI_DP_AWID : out std_logic_vector((C_M_AXI_DP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DP_AWADDR : out std_logic_vector((C_M_AXI_DP_ADDR_WIDTH-1) downto 0);
M_AXI_DP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_AWLOCK : out std_logic;
M_AXI_DP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_AWVALID : out std_logic;
M_AXI_DP_AWREADY : in std_logic;
M_AXI_DP_WDATA : out std_logic_vector((C_M_AXI_DP_DATA_WIDTH-1) downto 0);
M_AXI_DP_WSTRB : out std_logic_vector(((C_M_AXI_DP_DATA_WIDTH/8)-1) downto 0);
M_AXI_DP_WLAST : out std_logic;
M_AXI_DP_WVALID : out std_logic;
M_AXI_DP_WREADY : in std_logic;
M_AXI_DP_BID : in std_logic_vector((C_M_AXI_DP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_BVALID : in std_logic;
M_AXI_DP_BREADY : out std_logic;
M_AXI_DP_ARID : out std_logic_vector((C_M_AXI_DP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DP_ARADDR : out std_logic_vector((C_M_AXI_DP_ADDR_WIDTH-1) downto 0);
M_AXI_DP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_ARLOCK : out std_logic;
M_AXI_DP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_ARVALID : out std_logic;
M_AXI_DP_ARREADY : in std_logic;
M_AXI_DP_RID : in std_logic_vector((C_M_AXI_DP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DP_RDATA : in std_logic_vector((C_M_AXI_DP_DATA_WIDTH-1) downto 0);
M_AXI_DP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_RLAST : in std_logic;
M_AXI_DP_RVALID : in std_logic;
M_AXI_DP_RREADY : out std_logic;
M_AXI_IC_AWID : out std_logic_vector((C_M_AXI_IC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IC_AWADDR : out std_logic_vector((C_M_AXI_IC_ADDR_WIDTH-1) downto 0);
M_AXI_IC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_AWLOCK : out std_logic;
M_AXI_IC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_AWVALID : out std_logic;
M_AXI_IC_AWREADY : in std_logic;
M_AXI_IC_AWUSER : out std_logic_vector((C_M_AXI_IC_AWUSER_WIDTH-1) downto 0);
M_AXI_IC_AWDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_IC_AWSNOOP : out std_logic_vector(2 downto 0);
M_AXI_IC_AWBAR : out std_logic_vector(1 downto 0);
M_AXI_IC_WDATA : out std_logic_vector((C_M_AXI_IC_DATA_WIDTH-1) downto 0);
M_AXI_IC_WSTRB : out std_logic_vector(((C_M_AXI_IC_DATA_WIDTH/8)-1) downto 0);
M_AXI_IC_WLAST : out std_logic;
M_AXI_IC_WVALID : out std_logic;
M_AXI_IC_WREADY : in std_logic;
M_AXI_IC_WUSER : out std_logic_vector((C_M_AXI_IC_WUSER_WIDTH-1) downto 0);
M_AXI_IC_BID : in std_logic_vector((C_M_AXI_IC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IC_BVALID : in std_logic;
M_AXI_IC_BREADY : out std_logic;
M_AXI_IC_BUSER : in std_logic_vector((C_M_AXI_IC_BUSER_WIDTH-1) downto 0);
M_AXI_IC_WACK : out std_logic;
M_AXI_IC_ARID : out std_logic_vector((C_M_AXI_IC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IC_ARADDR : out std_logic_vector((C_M_AXI_IC_ADDR_WIDTH-1) downto 0);
M_AXI_IC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_ARLOCK : out std_logic;
M_AXI_IC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_ARVALID : out std_logic;
M_AXI_IC_ARREADY : in std_logic;
M_AXI_IC_ARUSER : out std_logic_vector((C_M_AXI_IC_ARUSER_WIDTH-1) downto 0);
M_AXI_IC_ARDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_IC_ARSNOOP : out std_logic_vector(3 downto 0);
M_AXI_IC_ARBAR : out std_logic_vector(1 downto 0);
M_AXI_IC_RID : in std_logic_vector((C_M_AXI_IC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IC_RDATA : in std_logic_vector((C_M_AXI_IC_DATA_WIDTH-1) downto 0);
M_AXI_IC_RRESP : in std_logic_vector(1+2*((C_INTERCONNECT-1)/2) downto 0);
M_AXI_IC_RLAST : in std_logic;
M_AXI_IC_RVALID : in std_logic;
M_AXI_IC_RREADY : out std_logic;
M_AXI_IC_RUSER : in std_logic_vector((C_M_AXI_IC_RUSER_WIDTH-1) downto 0);
M_AXI_IC_RACK : out std_logic;
M_AXI_IC_ACVALID : in std_logic;
M_AXI_IC_ACADDR : in std_logic_vector((C_M_AXI_IC_ADDR_WIDTH-1) downto 0);
M_AXI_IC_ACSNOOP : in std_logic_vector(3 downto 0);
M_AXI_IC_ACPROT : in std_logic_vector(2 downto 0);
M_AXI_IC_ACREADY : out std_logic;
M_AXI_IC_CRREADY : in std_logic;
M_AXI_IC_CRVALID : out std_logic;
M_AXI_IC_CRRESP : out std_logic_vector(4 downto 0);
M_AXI_IC_CDVALID : out std_logic;
M_AXI_IC_CDREADY : in std_logic;
M_AXI_IC_CDDATA : out std_logic_vector((C_M_AXI_IC_DATA_WIDTH-1) downto 0);
M_AXI_IC_CDLAST : out std_logic;
M_AXI_DC_AWID : out std_logic_vector((C_M_AXI_DC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DC_AWADDR : out std_logic_vector((C_M_AXI_DC_ADDR_WIDTH-1) downto 0);
M_AXI_DC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_AWLOCK : out std_logic;
M_AXI_DC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_AWVALID : out std_logic;
M_AXI_DC_AWREADY : in std_logic;
M_AXI_DC_AWUSER : out std_logic_vector((C_M_AXI_DC_AWUSER_WIDTH-1) downto 0);
M_AXI_DC_AWDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_DC_AWSNOOP : out std_logic_vector(2 downto 0);
M_AXI_DC_AWBAR : out std_logic_vector(1 downto 0);
M_AXI_DC_WDATA : out std_logic_vector((C_M_AXI_DC_DATA_WIDTH-1) downto 0);
M_AXI_DC_WSTRB : out std_logic_vector(((C_M_AXI_DC_DATA_WIDTH/8)-1) downto 0);
M_AXI_DC_WLAST : out std_logic;
M_AXI_DC_WVALID : out std_logic;
M_AXI_DC_WREADY : in std_logic;
M_AXI_DC_WUSER : out std_logic_vector((C_M_AXI_DC_WUSER_WIDTH-1) downto 0);
M_AXI_DC_BID : in std_logic_vector((C_M_AXI_DC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DC_BVALID : in std_logic;
M_AXI_DC_BREADY : out std_logic;
M_AXI_DC_BUSER : in std_logic_vector((C_M_AXI_DC_BUSER_WIDTH-1) downto 0);
M_AXI_DC_WACK : out std_logic;
M_AXI_DC_ARID : out std_logic_vector((C_M_AXI_DC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DC_ARADDR : out std_logic_vector((C_M_AXI_DC_ADDR_WIDTH-1) downto 0);
M_AXI_DC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_ARLOCK : out std_logic;
M_AXI_DC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_ARVALID : out std_logic;
M_AXI_DC_ARREADY : in std_logic;
M_AXI_DC_ARUSER : out std_logic_vector((C_M_AXI_DC_ARUSER_WIDTH-1) downto 0);
M_AXI_DC_ARDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_DC_ARSNOOP : out std_logic_vector(3 downto 0);
M_AXI_DC_ARBAR : out std_logic_vector(1 downto 0);
M_AXI_DC_RID : in std_logic_vector((C_M_AXI_DC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DC_RDATA : in std_logic_vector((C_M_AXI_DC_DATA_WIDTH-1) downto 0);
M_AXI_DC_RRESP : in std_logic_vector(1+2*((C_INTERCONNECT-1)/2) downto 0);
M_AXI_DC_RLAST : in std_logic;
M_AXI_DC_RVALID : in std_logic;
M_AXI_DC_RREADY : out std_logic;
M_AXI_DC_RUSER : in std_logic_vector((C_M_AXI_DC_RUSER_WIDTH-1) downto 0);
M_AXI_DC_RACK : out std_logic;
M_AXI_DC_ACVALID : in std_logic;
M_AXI_DC_ACADDR : in std_logic_vector((C_M_AXI_DC_ADDR_WIDTH-1) downto 0);
M_AXI_DC_ACSNOOP : in std_logic_vector(3 downto 0);
M_AXI_DC_ACPROT : in std_logic_vector(2 downto 0);
M_AXI_DC_ACREADY : out std_logic;
M_AXI_DC_CRREADY : in std_logic;
M_AXI_DC_CRVALID : out std_logic;
M_AXI_DC_CRRESP : out std_logic_vector(4 downto 0);
M_AXI_DC_CDVALID : out std_logic;
M_AXI_DC_CDREADY : in std_logic;
M_AXI_DC_CDDATA : out std_logic_vector((C_M_AXI_DC_DATA_WIDTH-1) downto 0);
M_AXI_DC_CDLAST : out std_logic;
DBG_CLK : in std_logic;
DBG_TDI : in std_logic;
DBG_TDO : out std_logic;
DBG_REG_EN : in std_logic_vector(0 to 7);
DBG_SHIFT : in std_logic;
DBG_CAPTURE : in std_logic;
DBG_UPDATE : in std_logic;
DEBUG_RST : in std_logic;
Trace_Instruction : out std_logic_vector(0 to 31);
Trace_Valid_Instr : out std_logic;
Trace_PC : out std_logic_vector(0 to 31);
Trace_Reg_Write : out std_logic;
Trace_Reg_Addr : out std_logic_vector(0 to 4);
Trace_MSR_Reg : out std_logic_vector(0 to 14);
Trace_PID_Reg : out std_logic_vector(0 to 7);
Trace_New_Reg_Value : out std_logic_vector(0 to 31);
Trace_Exception_Taken : out std_logic;
Trace_Exception_Kind : out std_logic_vector(0 to 4);
Trace_Jump_Taken : out std_logic;
Trace_Delay_Slot : out std_logic;
Trace_Data_Address : out std_logic_vector(0 to 31);
Trace_Data_Access : out std_logic;
Trace_Data_Read : out std_logic;
Trace_Data_Write : out std_logic;
Trace_Data_Write_Value : out std_logic_vector(0 to 31);
Trace_Data_Byte_Enable : out std_logic_vector(0 to 3);
Trace_DCache_Req : out std_logic;
Trace_DCache_Hit : out std_logic;
Trace_DCache_Rdy : out std_logic;
Trace_DCache_Read : out std_logic;
Trace_ICache_Req : out std_logic;
Trace_ICache_Hit : out std_logic;
Trace_ICache_Rdy : out std_logic;
Trace_OF_PipeRun : out std_logic;
Trace_EX_PipeRun : out std_logic;
Trace_MEM_PipeRun : out std_logic;
Trace_MB_Halted : out std_logic;
Trace_Jump_Hit : out std_logic;
FSL0_S_CLK : out std_logic;
FSL0_S_READ : out std_logic;
FSL0_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL0_S_CONTROL : in std_logic;
FSL0_S_EXISTS : in std_logic;
FSL0_M_CLK : out std_logic;
FSL0_M_WRITE : out std_logic;
FSL0_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL0_M_CONTROL : out std_logic;
FSL0_M_FULL : in std_logic;
FSL1_S_CLK : out std_logic;
FSL1_S_READ : out std_logic;
FSL1_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL1_S_CONTROL : in std_logic;
FSL1_S_EXISTS : in std_logic;
FSL1_M_CLK : out std_logic;
FSL1_M_WRITE : out std_logic;
FSL1_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL1_M_CONTROL : out std_logic;
FSL1_M_FULL : in std_logic;
FSL2_S_CLK : out std_logic;
FSL2_S_READ : out std_logic;
FSL2_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL2_S_CONTROL : in std_logic;
FSL2_S_EXISTS : in std_logic;
FSL2_M_CLK : out std_logic;
FSL2_M_WRITE : out std_logic;
FSL2_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL2_M_CONTROL : out std_logic;
FSL2_M_FULL : in std_logic;
FSL3_S_CLK : out std_logic;
FSL3_S_READ : out std_logic;
FSL3_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL3_S_CONTROL : in std_logic;
FSL3_S_EXISTS : in std_logic;
FSL3_M_CLK : out std_logic;
FSL3_M_WRITE : out std_logic;
FSL3_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL3_M_CONTROL : out std_logic;
FSL3_M_FULL : in std_logic;
FSL4_S_CLK : out std_logic;
FSL4_S_READ : out std_logic;
FSL4_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL4_S_CONTROL : in std_logic;
FSL4_S_EXISTS : in std_logic;
FSL4_M_CLK : out std_logic;
FSL4_M_WRITE : out std_logic;
FSL4_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL4_M_CONTROL : out std_logic;
FSL4_M_FULL : in std_logic;
FSL5_S_CLK : out std_logic;
FSL5_S_READ : out std_logic;
FSL5_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL5_S_CONTROL : in std_logic;
FSL5_S_EXISTS : in std_logic;
FSL5_M_CLK : out std_logic;
FSL5_M_WRITE : out std_logic;
FSL5_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL5_M_CONTROL : out std_logic;
FSL5_M_FULL : in std_logic;
FSL6_S_CLK : out std_logic;
FSL6_S_READ : out std_logic;
FSL6_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL6_S_CONTROL : in std_logic;
FSL6_S_EXISTS : in std_logic;
FSL6_M_CLK : out std_logic;
FSL6_M_WRITE : out std_logic;
FSL6_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL6_M_CONTROL : out std_logic;
FSL6_M_FULL : in std_logic;
FSL7_S_CLK : out std_logic;
FSL7_S_READ : out std_logic;
FSL7_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL7_S_CONTROL : in std_logic;
FSL7_S_EXISTS : in std_logic;
FSL7_M_CLK : out std_logic;
FSL7_M_WRITE : out std_logic;
FSL7_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL7_M_CONTROL : out std_logic;
FSL7_M_FULL : in std_logic;
FSL8_S_CLK : out std_logic;
FSL8_S_READ : out std_logic;
FSL8_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL8_S_CONTROL : in std_logic;
FSL8_S_EXISTS : in std_logic;
FSL8_M_CLK : out std_logic;
FSL8_M_WRITE : out std_logic;
FSL8_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL8_M_CONTROL : out std_logic;
FSL8_M_FULL : in std_logic;
FSL9_S_CLK : out std_logic;
FSL9_S_READ : out std_logic;
FSL9_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL9_S_CONTROL : in std_logic;
FSL9_S_EXISTS : in std_logic;
FSL9_M_CLK : out std_logic;
FSL9_M_WRITE : out std_logic;
FSL9_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL9_M_CONTROL : out std_logic;
FSL9_M_FULL : in std_logic;
FSL10_S_CLK : out std_logic;
FSL10_S_READ : out std_logic;
FSL10_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL10_S_CONTROL : in std_logic;
FSL10_S_EXISTS : in std_logic;
FSL10_M_CLK : out std_logic;
FSL10_M_WRITE : out std_logic;
FSL10_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL10_M_CONTROL : out std_logic;
FSL10_M_FULL : in std_logic;
FSL11_S_CLK : out std_logic;
FSL11_S_READ : out std_logic;
FSL11_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL11_S_CONTROL : in std_logic;
FSL11_S_EXISTS : in std_logic;
FSL11_M_CLK : out std_logic;
FSL11_M_WRITE : out std_logic;
FSL11_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL11_M_CONTROL : out std_logic;
FSL11_M_FULL : in std_logic;
FSL12_S_CLK : out std_logic;
FSL12_S_READ : out std_logic;
FSL12_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL12_S_CONTROL : in std_logic;
FSL12_S_EXISTS : in std_logic;
FSL12_M_CLK : out std_logic;
FSL12_M_WRITE : out std_logic;
FSL12_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL12_M_CONTROL : out std_logic;
FSL12_M_FULL : in std_logic;
FSL13_S_CLK : out std_logic;
FSL13_S_READ : out std_logic;
FSL13_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL13_S_CONTROL : in std_logic;
FSL13_S_EXISTS : in std_logic;
FSL13_M_CLK : out std_logic;
FSL13_M_WRITE : out std_logic;
FSL13_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL13_M_CONTROL : out std_logic;
FSL13_M_FULL : in std_logic;
FSL14_S_CLK : out std_logic;
FSL14_S_READ : out std_logic;
FSL14_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL14_S_CONTROL : in std_logic;
FSL14_S_EXISTS : in std_logic;
FSL14_M_CLK : out std_logic;
FSL14_M_WRITE : out std_logic;
FSL14_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL14_M_CONTROL : out std_logic;
FSL14_M_FULL : in std_logic;
FSL15_S_CLK : out std_logic;
FSL15_S_READ : out std_logic;
FSL15_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL15_S_CONTROL : in std_logic;
FSL15_S_EXISTS : in std_logic;
FSL15_M_CLK : out std_logic;
FSL15_M_WRITE : out std_logic;
FSL15_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL15_M_CONTROL : out std_logic;
FSL15_M_FULL : in std_logic;
M0_AXIS_TLAST : out std_logic;
M0_AXIS_TDATA : out std_logic_vector(C_M0_AXIS_DATA_WIDTH-1 downto 0);
M0_AXIS_TVALID : out std_logic;
M0_AXIS_TREADY : in std_logic;
S0_AXIS_TLAST : in std_logic;
S0_AXIS_TDATA : in std_logic_vector(C_S0_AXIS_DATA_WIDTH-1 downto 0);
S0_AXIS_TVALID : in std_logic;
S0_AXIS_TREADY : out std_logic;
M1_AXIS_TLAST : out std_logic;
M1_AXIS_TDATA : out std_logic_vector(C_M1_AXIS_DATA_WIDTH-1 downto 0);
M1_AXIS_TVALID : out std_logic;
M1_AXIS_TREADY : in std_logic;
S1_AXIS_TLAST : in std_logic;
S1_AXIS_TDATA : in std_logic_vector(C_S1_AXIS_DATA_WIDTH-1 downto 0);
S1_AXIS_TVALID : in std_logic;
S1_AXIS_TREADY : out std_logic;
M2_AXIS_TLAST : out std_logic;
M2_AXIS_TDATA : out std_logic_vector(C_M2_AXIS_DATA_WIDTH-1 downto 0);
M2_AXIS_TVALID : out std_logic;
M2_AXIS_TREADY : in std_logic;
S2_AXIS_TLAST : in std_logic;
S2_AXIS_TDATA : in std_logic_vector(C_S2_AXIS_DATA_WIDTH-1 downto 0);
S2_AXIS_TVALID : in std_logic;
S2_AXIS_TREADY : out std_logic;
M3_AXIS_TLAST : out std_logic;
M3_AXIS_TDATA : out std_logic_vector(C_M3_AXIS_DATA_WIDTH-1 downto 0);
M3_AXIS_TVALID : out std_logic;
M3_AXIS_TREADY : in std_logic;
S3_AXIS_TLAST : in std_logic;
S3_AXIS_TDATA : in std_logic_vector(C_S3_AXIS_DATA_WIDTH-1 downto 0);
S3_AXIS_TVALID : in std_logic;
S3_AXIS_TREADY : out std_logic;
M4_AXIS_TLAST : out std_logic;
M4_AXIS_TDATA : out std_logic_vector(C_M4_AXIS_DATA_WIDTH-1 downto 0);
M4_AXIS_TVALID : out std_logic;
M4_AXIS_TREADY : in std_logic;
S4_AXIS_TLAST : in std_logic;
S4_AXIS_TDATA : in std_logic_vector(C_S4_AXIS_DATA_WIDTH-1 downto 0);
S4_AXIS_TVALID : in std_logic;
S4_AXIS_TREADY : out std_logic;
M5_AXIS_TLAST : out std_logic;
M5_AXIS_TDATA : out std_logic_vector(C_M5_AXIS_DATA_WIDTH-1 downto 0);
M5_AXIS_TVALID : out std_logic;
M5_AXIS_TREADY : in std_logic;
S5_AXIS_TLAST : in std_logic;
S5_AXIS_TDATA : in std_logic_vector(C_S5_AXIS_DATA_WIDTH-1 downto 0);
S5_AXIS_TVALID : in std_logic;
S5_AXIS_TREADY : out std_logic;
M6_AXIS_TLAST : out std_logic;
M6_AXIS_TDATA : out std_logic_vector(C_M6_AXIS_DATA_WIDTH-1 downto 0);
M6_AXIS_TVALID : out std_logic;
M6_AXIS_TREADY : in std_logic;
S6_AXIS_TLAST : in std_logic;
S6_AXIS_TDATA : in std_logic_vector(C_S6_AXIS_DATA_WIDTH-1 downto 0);
S6_AXIS_TVALID : in std_logic;
S6_AXIS_TREADY : out std_logic;
M7_AXIS_TLAST : out std_logic;
M7_AXIS_TDATA : out std_logic_vector(C_M7_AXIS_DATA_WIDTH-1 downto 0);
M7_AXIS_TVALID : out std_logic;
M7_AXIS_TREADY : in std_logic;
S7_AXIS_TLAST : in std_logic;
S7_AXIS_TDATA : in std_logic_vector(C_S7_AXIS_DATA_WIDTH-1 downto 0);
S7_AXIS_TVALID : in std_logic;
S7_AXIS_TREADY : out std_logic;
M8_AXIS_TLAST : out std_logic;
M8_AXIS_TDATA : out std_logic_vector(C_M8_AXIS_DATA_WIDTH-1 downto 0);
M8_AXIS_TVALID : out std_logic;
M8_AXIS_TREADY : in std_logic;
S8_AXIS_TLAST : in std_logic;
S8_AXIS_TDATA : in std_logic_vector(C_S8_AXIS_DATA_WIDTH-1 downto 0);
S8_AXIS_TVALID : in std_logic;
S8_AXIS_TREADY : out std_logic;
M9_AXIS_TLAST : out std_logic;
M9_AXIS_TDATA : out std_logic_vector(C_M9_AXIS_DATA_WIDTH-1 downto 0);
M9_AXIS_TVALID : out std_logic;
M9_AXIS_TREADY : in std_logic;
S9_AXIS_TLAST : in std_logic;
S9_AXIS_TDATA : in std_logic_vector(C_S9_AXIS_DATA_WIDTH-1 downto 0);
S9_AXIS_TVALID : in std_logic;
S9_AXIS_TREADY : out std_logic;
M10_AXIS_TLAST : out std_logic;
M10_AXIS_TDATA : out std_logic_vector(C_M10_AXIS_DATA_WIDTH-1 downto 0);
M10_AXIS_TVALID : out std_logic;
M10_AXIS_TREADY : in std_logic;
S10_AXIS_TLAST : in std_logic;
S10_AXIS_TDATA : in std_logic_vector(C_S10_AXIS_DATA_WIDTH-1 downto 0);
S10_AXIS_TVALID : in std_logic;
S10_AXIS_TREADY : out std_logic;
M11_AXIS_TLAST : out std_logic;
M11_AXIS_TDATA : out std_logic_vector(C_M11_AXIS_DATA_WIDTH-1 downto 0);
M11_AXIS_TVALID : out std_logic;
M11_AXIS_TREADY : in std_logic;
S11_AXIS_TLAST : in std_logic;
S11_AXIS_TDATA : in std_logic_vector(C_S11_AXIS_DATA_WIDTH-1 downto 0);
S11_AXIS_TVALID : in std_logic;
S11_AXIS_TREADY : out std_logic;
M12_AXIS_TLAST : out std_logic;
M12_AXIS_TDATA : out std_logic_vector(C_M12_AXIS_DATA_WIDTH-1 downto 0);
M12_AXIS_TVALID : out std_logic;
M12_AXIS_TREADY : in std_logic;
S12_AXIS_TLAST : in std_logic;
S12_AXIS_TDATA : in std_logic_vector(C_S12_AXIS_DATA_WIDTH-1 downto 0);
S12_AXIS_TVALID : in std_logic;
S12_AXIS_TREADY : out std_logic;
M13_AXIS_TLAST : out std_logic;
M13_AXIS_TDATA : out std_logic_vector(C_M13_AXIS_DATA_WIDTH-1 downto 0);
M13_AXIS_TVALID : out std_logic;
M13_AXIS_TREADY : in std_logic;
S13_AXIS_TLAST : in std_logic;
S13_AXIS_TDATA : in std_logic_vector(C_S13_AXIS_DATA_WIDTH-1 downto 0);
S13_AXIS_TVALID : in std_logic;
S13_AXIS_TREADY : out std_logic;
M14_AXIS_TLAST : out std_logic;
M14_AXIS_TDATA : out std_logic_vector(C_M14_AXIS_DATA_WIDTH-1 downto 0);
M14_AXIS_TVALID : out std_logic;
M14_AXIS_TREADY : in std_logic;
S14_AXIS_TLAST : in std_logic;
S14_AXIS_TDATA : in std_logic_vector(C_S14_AXIS_DATA_WIDTH-1 downto 0);
S14_AXIS_TVALID : in std_logic;
S14_AXIS_TREADY : out std_logic;
M15_AXIS_TLAST : out std_logic;
M15_AXIS_TDATA : out std_logic_vector(C_M15_AXIS_DATA_WIDTH-1 downto 0);
M15_AXIS_TVALID : out std_logic;
M15_AXIS_TREADY : in std_logic;
S15_AXIS_TLAST : in std_logic;
S15_AXIS_TDATA : in std_logic_vector(C_S15_AXIS_DATA_WIDTH-1 downto 0);
S15_AXIS_TVALID : in std_logic;
S15_AXIS_TREADY : out std_logic;
ICACHE_FSL_IN_CLK : out std_logic;
ICACHE_FSL_IN_READ : out std_logic;
ICACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
ICACHE_FSL_IN_CONTROL : in std_logic;
ICACHE_FSL_IN_EXISTS : in std_logic;
ICACHE_FSL_OUT_CLK : out std_logic;
ICACHE_FSL_OUT_WRITE : out std_logic;
ICACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
ICACHE_FSL_OUT_CONTROL : out std_logic;
ICACHE_FSL_OUT_FULL : in std_logic;
DCACHE_FSL_IN_CLK : out std_logic;
DCACHE_FSL_IN_READ : out std_logic;
DCACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
DCACHE_FSL_IN_CONTROL : in std_logic;
DCACHE_FSL_IN_EXISTS : in std_logic;
DCACHE_FSL_OUT_CLK : out std_logic;
DCACHE_FSL_OUT_WRITE : out std_logic;
DCACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
DCACHE_FSL_OUT_CONTROL : out std_logic;
DCACHE_FSL_OUT_FULL : in std_logic
);
end component;
begin
microblaze_0 : microblaze
generic map (
C_SCO => 0,
C_FREQ => 50000000,
C_DATA_SIZE => 32,
C_DYNAMIC_BUS_SIZING => 1,
C_FAMILY => "virtex5",
C_INSTANCE => "microblaze_0",
C_AVOID_PRIMITIVES => 0,
C_FAULT_TOLERANT => 0,
C_ECC_USE_CE_EXCEPTION => 0,
C_LOCKSTEP_SLAVE => 0,
C_ENDIANNESS => 0,
C_AREA_OPTIMIZED => 0,
C_OPTIMIZATION => 0,
C_INTERCONNECT => 1,
C_STREAM_INTERCONNECT => 0,
C_BASE_VECTORS => X"00000000",
C_DPLB_DWIDTH => 64,
C_DPLB_NATIVE_DWIDTH => 32,
C_DPLB_BURST_EN => 0,
C_DPLB_P2P => 0,
C_IPLB_DWIDTH => 64,
C_IPLB_NATIVE_DWIDTH => 32,
C_IPLB_BURST_EN => 0,
C_IPLB_P2P => 0,
C_M_AXI_DP_THREAD_ID_WIDTH => 1,
C_M_AXI_DP_DATA_WIDTH => 32,
C_M_AXI_DP_ADDR_WIDTH => 32,
C_M_AXI_DP_EXCLUSIVE_ACCESS => 0,
C_M_AXI_IP_THREAD_ID_WIDTH => 1,
C_M_AXI_IP_DATA_WIDTH => 32,
C_M_AXI_IP_ADDR_WIDTH => 32,
C_D_AXI => 0,
C_D_PLB => 1,
C_D_LMB => 1,
C_I_AXI => 0,
C_I_PLB => 1,
C_I_LMB => 1,
C_USE_MSR_INSTR => 1,
C_USE_PCMP_INSTR => 1,
C_USE_BARREL => 1,
C_USE_DIV => 0,
C_USE_HW_MUL => 1,
C_USE_FPU => 0,
C_USE_REORDER_INSTR => 1,
C_UNALIGNED_EXCEPTIONS => 0,
C_ILL_OPCODE_EXCEPTION => 0,
C_M_AXI_I_BUS_EXCEPTION => 0,
C_M_AXI_D_BUS_EXCEPTION => 0,
C_IPLB_BUS_EXCEPTION => 0,
C_DPLB_BUS_EXCEPTION => 0,
C_DIV_ZERO_EXCEPTION => 0,
C_FPU_EXCEPTION => 0,
C_FSL_EXCEPTION => 0,
C_USE_STACK_PROTECTION => 0,
C_PVR => 0,
C_PVR_USER1 => X"00",
C_PVR_USER2 => X"00000000",
C_DEBUG_ENABLED => 1,
C_NUMBER_OF_PC_BRK => 1,
C_NUMBER_OF_RD_ADDR_BRK => 0,
C_NUMBER_OF_WR_ADDR_BRK => 0,
C_INTERRUPT_IS_EDGE => 0,
C_EDGE_IS_POSITIVE => 1,
C_RESET_MSR => X"00000000",
C_OPCODE_0x0_ILLEGAL => 0,
C_FSL_LINKS => 0,
C_FSL_DATA_SIZE => 32,
C_USE_EXTENDED_FSL_INSTR => 0,
C_M0_AXIS_DATA_WIDTH => 32,
C_S0_AXIS_DATA_WIDTH => 32,
C_M1_AXIS_DATA_WIDTH => 32,
C_S1_AXIS_DATA_WIDTH => 32,
C_M2_AXIS_DATA_WIDTH => 32,
C_S2_AXIS_DATA_WIDTH => 32,
C_M3_AXIS_DATA_WIDTH => 32,
C_S3_AXIS_DATA_WIDTH => 32,
C_M4_AXIS_DATA_WIDTH => 32,
C_S4_AXIS_DATA_WIDTH => 32,
C_M5_AXIS_DATA_WIDTH => 32,
C_S5_AXIS_DATA_WIDTH => 32,
C_M6_AXIS_DATA_WIDTH => 32,
C_S6_AXIS_DATA_WIDTH => 32,
C_M7_AXIS_DATA_WIDTH => 32,
C_S7_AXIS_DATA_WIDTH => 32,
C_M8_AXIS_DATA_WIDTH => 32,
C_S8_AXIS_DATA_WIDTH => 32,
C_M9_AXIS_DATA_WIDTH => 32,
C_S9_AXIS_DATA_WIDTH => 32,
C_M10_AXIS_DATA_WIDTH => 32,
C_S10_AXIS_DATA_WIDTH => 32,
C_M11_AXIS_DATA_WIDTH => 32,
C_S11_AXIS_DATA_WIDTH => 32,
C_M12_AXIS_DATA_WIDTH => 32,
C_S12_AXIS_DATA_WIDTH => 32,
C_M13_AXIS_DATA_WIDTH => 32,
C_S13_AXIS_DATA_WIDTH => 32,
C_M14_AXIS_DATA_WIDTH => 32,
C_S14_AXIS_DATA_WIDTH => 32,
C_M15_AXIS_DATA_WIDTH => 32,
C_S15_AXIS_DATA_WIDTH => 32,
C_ICACHE_BASEADDR => X"00000000",
C_ICACHE_HIGHADDR => X"3FFFFFFF",
C_USE_ICACHE => 0,
C_ALLOW_ICACHE_WR => 1,
C_ADDR_TAG_BITS => 0,
C_CACHE_BYTE_SIZE => 8192,
C_ICACHE_USE_FSL => 1,
C_ICACHE_LINE_LEN => 4,
C_ICACHE_ALWAYS_USED => 0,
C_ICACHE_INTERFACE => 0,
C_ICACHE_VICTIMS => 0,
C_ICACHE_STREAMS => 0,
C_ICACHE_FORCE_TAG_LUTRAM => 0,
C_ICACHE_DATA_WIDTH => 0,
C_M_AXI_IC_THREAD_ID_WIDTH => 1,
C_M_AXI_IC_DATA_WIDTH => 32,
C_M_AXI_IC_ADDR_WIDTH => 32,
C_M_AXI_IC_USER_VALUE => 2#11111#,
C_M_AXI_IC_AWUSER_WIDTH => 5,
C_M_AXI_IC_ARUSER_WIDTH => 5,
C_M_AXI_IC_WUSER_WIDTH => 1,
C_M_AXI_IC_RUSER_WIDTH => 1,
C_M_AXI_IC_BUSER_WIDTH => 1,
C_DCACHE_BASEADDR => X"00000000",
C_DCACHE_HIGHADDR => X"3FFFFFFF",
C_USE_DCACHE => 0,
C_ALLOW_DCACHE_WR => 1,
C_DCACHE_ADDR_TAG => 0,
C_DCACHE_BYTE_SIZE => 8192,
C_DCACHE_USE_FSL => 1,
C_DCACHE_LINE_LEN => 4,
C_DCACHE_ALWAYS_USED => 0,
C_DCACHE_INTERFACE => 0,
C_DCACHE_USE_WRITEBACK => 0,
C_DCACHE_VICTIMS => 0,
C_DCACHE_FORCE_TAG_LUTRAM => 0,
C_DCACHE_DATA_WIDTH => 0,
C_M_AXI_DC_THREAD_ID_WIDTH => 1,
C_M_AXI_DC_DATA_WIDTH => 32,
C_M_AXI_DC_ADDR_WIDTH => 32,
C_M_AXI_DC_EXCLUSIVE_ACCESS => 0,
C_M_AXI_DC_USER_VALUE => 2#11111#,
C_M_AXI_DC_AWUSER_WIDTH => 5,
C_M_AXI_DC_ARUSER_WIDTH => 5,
C_M_AXI_DC_WUSER_WIDTH => 1,
C_M_AXI_DC_RUSER_WIDTH => 1,
C_M_AXI_DC_BUSER_WIDTH => 1,
C_USE_MMU => 0,
C_MMU_DTLB_SIZE => 4,
C_MMU_ITLB_SIZE => 2,
C_MMU_TLB_ACCESS => 3,
C_MMU_ZONES => 16,
C_MMU_PRIVILEGED_INSTR => 0,
C_USE_INTERRUPT => 0,
C_USE_EXT_BRK => 1,
C_USE_EXT_NM_BRK => 1,
C_USE_BRANCH_TARGET_CACHE => 0,
C_BRANCH_TARGET_CACHE_SIZE => 0,
C_PC_WIDTH => 32
)
port map (
CLK => CLK,
RESET => RESET,
MB_RESET => MB_RESET,
INTERRUPT => INTERRUPT,
INTERRUPT_ADDRESS => INTERRUPT_ADDRESS,
INTERRUPT_ACK => INTERRUPT_ACK,
EXT_BRK => EXT_BRK,
EXT_NM_BRK => EXT_NM_BRK,
DBG_STOP => DBG_STOP,
MB_Halted => MB_Halted,
MB_Error => MB_Error,
WAKEUP => WAKEUP,
SLEEP => SLEEP,
DBG_WAKEUP => DBG_WAKEUP,
LOCKSTEP_MASTER_OUT => LOCKSTEP_MASTER_OUT,
LOCKSTEP_SLAVE_IN => LOCKSTEP_SLAVE_IN,
LOCKSTEP_OUT => LOCKSTEP_OUT,
INSTR => INSTR,
IREADY => IREADY,
IWAIT => IWAIT,
ICE => ICE,
IUE => IUE,
INSTR_ADDR => INSTR_ADDR,
IFETCH => IFETCH,
I_AS => I_AS,
IPLB_M_ABort => IPLB_M_ABort,
IPLB_M_ABus => IPLB_M_ABus,
IPLB_M_UABus => IPLB_M_UABus,
IPLB_M_BE => IPLB_M_BE,
IPLB_M_busLock => IPLB_M_busLock,
IPLB_M_lockErr => IPLB_M_lockErr,
IPLB_M_MSize => IPLB_M_MSize,
IPLB_M_priority => IPLB_M_priority,
IPLB_M_rdBurst => IPLB_M_rdBurst,
IPLB_M_request => IPLB_M_request,
IPLB_M_RNW => IPLB_M_RNW,
IPLB_M_size => IPLB_M_size,
IPLB_M_TAttribute => IPLB_M_TAttribute,
IPLB_M_type => IPLB_M_type,
IPLB_M_wrBurst => IPLB_M_wrBurst,
IPLB_M_wrDBus => IPLB_M_wrDBus,
IPLB_MBusy => IPLB_MBusy,
IPLB_MRdErr => IPLB_MRdErr,
IPLB_MWrErr => IPLB_MWrErr,
IPLB_MIRQ => IPLB_MIRQ,
IPLB_MWrBTerm => IPLB_MWrBTerm,
IPLB_MWrDAck => IPLB_MWrDAck,
IPLB_MAddrAck => IPLB_MAddrAck,
IPLB_MRdBTerm => IPLB_MRdBTerm,
IPLB_MRdDAck => IPLB_MRdDAck,
IPLB_MRdDBus => IPLB_MRdDBus,
IPLB_MRdWdAddr => IPLB_MRdWdAddr,
IPLB_MRearbitrate => IPLB_MRearbitrate,
IPLB_MSSize => IPLB_MSSize,
IPLB_MTimeout => IPLB_MTimeout,
DATA_READ => DATA_READ,
DREADY => DREADY,
DWAIT => DWAIT,
DCE => DCE,
DUE => DUE,
DATA_WRITE => DATA_WRITE,
DATA_ADDR => DATA_ADDR,
D_AS => D_AS,
READ_STROBE => READ_STROBE,
WRITE_STROBE => WRITE_STROBE,
BYTE_ENABLE => BYTE_ENABLE,
DPLB_M_ABort => DPLB_M_ABort,
DPLB_M_ABus => DPLB_M_ABus,
DPLB_M_UABus => DPLB_M_UABus,
DPLB_M_BE => DPLB_M_BE,
DPLB_M_busLock => DPLB_M_busLock,
DPLB_M_lockErr => DPLB_M_lockErr,
DPLB_M_MSize => DPLB_M_MSize,
DPLB_M_priority => DPLB_M_priority,
DPLB_M_rdBurst => DPLB_M_rdBurst,
DPLB_M_request => DPLB_M_request,
DPLB_M_RNW => DPLB_M_RNW,
DPLB_M_size => DPLB_M_size,
DPLB_M_TAttribute => DPLB_M_TAttribute,
DPLB_M_type => DPLB_M_type,
DPLB_M_wrBurst => DPLB_M_wrBurst,
DPLB_M_wrDBus => DPLB_M_wrDBus,
DPLB_MBusy => DPLB_MBusy,
DPLB_MRdErr => DPLB_MRdErr,
DPLB_MWrErr => DPLB_MWrErr,
DPLB_MIRQ => DPLB_MIRQ,
DPLB_MWrBTerm => DPLB_MWrBTerm,
DPLB_MWrDAck => DPLB_MWrDAck,
DPLB_MAddrAck => DPLB_MAddrAck,
DPLB_MRdBTerm => DPLB_MRdBTerm,
DPLB_MRdDAck => DPLB_MRdDAck,
DPLB_MRdDBus => DPLB_MRdDBus,
DPLB_MRdWdAddr => DPLB_MRdWdAddr,
DPLB_MRearbitrate => DPLB_MRearbitrate,
DPLB_MSSize => DPLB_MSSize,
DPLB_MTimeout => DPLB_MTimeout,
M_AXI_IP_AWID => M_AXI_IP_AWID,
M_AXI_IP_AWADDR => M_AXI_IP_AWADDR,
M_AXI_IP_AWLEN => M_AXI_IP_AWLEN,
M_AXI_IP_AWSIZE => M_AXI_IP_AWSIZE,
M_AXI_IP_AWBURST => M_AXI_IP_AWBURST,
M_AXI_IP_AWLOCK => M_AXI_IP_AWLOCK,
M_AXI_IP_AWCACHE => M_AXI_IP_AWCACHE,
M_AXI_IP_AWPROT => M_AXI_IP_AWPROT,
M_AXI_IP_AWQOS => M_AXI_IP_AWQOS,
M_AXI_IP_AWVALID => M_AXI_IP_AWVALID,
M_AXI_IP_AWREADY => M_AXI_IP_AWREADY,
M_AXI_IP_WDATA => M_AXI_IP_WDATA,
M_AXI_IP_WSTRB => M_AXI_IP_WSTRB,
M_AXI_IP_WLAST => M_AXI_IP_WLAST,
M_AXI_IP_WVALID => M_AXI_IP_WVALID,
M_AXI_IP_WREADY => M_AXI_IP_WREADY,
M_AXI_IP_BID => M_AXI_IP_BID,
M_AXI_IP_BRESP => M_AXI_IP_BRESP,
M_AXI_IP_BVALID => M_AXI_IP_BVALID,
M_AXI_IP_BREADY => M_AXI_IP_BREADY,
M_AXI_IP_ARID => M_AXI_IP_ARID,
M_AXI_IP_ARADDR => M_AXI_IP_ARADDR,
M_AXI_IP_ARLEN => M_AXI_IP_ARLEN,
M_AXI_IP_ARSIZE => M_AXI_IP_ARSIZE,
M_AXI_IP_ARBURST => M_AXI_IP_ARBURST,
M_AXI_IP_ARLOCK => M_AXI_IP_ARLOCK,
M_AXI_IP_ARCACHE => M_AXI_IP_ARCACHE,
M_AXI_IP_ARPROT => M_AXI_IP_ARPROT,
M_AXI_IP_ARQOS => M_AXI_IP_ARQOS,
M_AXI_IP_ARVALID => M_AXI_IP_ARVALID,
M_AXI_IP_ARREADY => M_AXI_IP_ARREADY,
M_AXI_IP_RID => M_AXI_IP_RID,
M_AXI_IP_RDATA => M_AXI_IP_RDATA,
M_AXI_IP_RRESP => M_AXI_IP_RRESP,
M_AXI_IP_RLAST => M_AXI_IP_RLAST,
M_AXI_IP_RVALID => M_AXI_IP_RVALID,
M_AXI_IP_RREADY => M_AXI_IP_RREADY,
M_AXI_DP_AWID => M_AXI_DP_AWID,
M_AXI_DP_AWADDR => M_AXI_DP_AWADDR,
M_AXI_DP_AWLEN => M_AXI_DP_AWLEN,
M_AXI_DP_AWSIZE => M_AXI_DP_AWSIZE,
M_AXI_DP_AWBURST => M_AXI_DP_AWBURST,
M_AXI_DP_AWLOCK => M_AXI_DP_AWLOCK,
M_AXI_DP_AWCACHE => M_AXI_DP_AWCACHE,
M_AXI_DP_AWPROT => M_AXI_DP_AWPROT,
M_AXI_DP_AWQOS => M_AXI_DP_AWQOS,
M_AXI_DP_AWVALID => M_AXI_DP_AWVALID,
M_AXI_DP_AWREADY => M_AXI_DP_AWREADY,
M_AXI_DP_WDATA => M_AXI_DP_WDATA,
M_AXI_DP_WSTRB => M_AXI_DP_WSTRB,
M_AXI_DP_WLAST => M_AXI_DP_WLAST,
M_AXI_DP_WVALID => M_AXI_DP_WVALID,
M_AXI_DP_WREADY => M_AXI_DP_WREADY,
M_AXI_DP_BID => M_AXI_DP_BID,
M_AXI_DP_BRESP => M_AXI_DP_BRESP,
M_AXI_DP_BVALID => M_AXI_DP_BVALID,
M_AXI_DP_BREADY => M_AXI_DP_BREADY,
M_AXI_DP_ARID => M_AXI_DP_ARID,
M_AXI_DP_ARADDR => M_AXI_DP_ARADDR,
M_AXI_DP_ARLEN => M_AXI_DP_ARLEN,
M_AXI_DP_ARSIZE => M_AXI_DP_ARSIZE,
M_AXI_DP_ARBURST => M_AXI_DP_ARBURST,
M_AXI_DP_ARLOCK => M_AXI_DP_ARLOCK,
M_AXI_DP_ARCACHE => M_AXI_DP_ARCACHE,
M_AXI_DP_ARPROT => M_AXI_DP_ARPROT,
M_AXI_DP_ARQOS => M_AXI_DP_ARQOS,
M_AXI_DP_ARVALID => M_AXI_DP_ARVALID,
M_AXI_DP_ARREADY => M_AXI_DP_ARREADY,
M_AXI_DP_RID => M_AXI_DP_RID,
M_AXI_DP_RDATA => M_AXI_DP_RDATA,
M_AXI_DP_RRESP => M_AXI_DP_RRESP,
M_AXI_DP_RLAST => M_AXI_DP_RLAST,
M_AXI_DP_RVALID => M_AXI_DP_RVALID,
M_AXI_DP_RREADY => M_AXI_DP_RREADY,
M_AXI_IC_AWID => M_AXI_IC_AWID,
M_AXI_IC_AWADDR => M_AXI_IC_AWADDR,
M_AXI_IC_AWLEN => M_AXI_IC_AWLEN,
M_AXI_IC_AWSIZE => M_AXI_IC_AWSIZE,
M_AXI_IC_AWBURST => M_AXI_IC_AWBURST,
M_AXI_IC_AWLOCK => M_AXI_IC_AWLOCK,
M_AXI_IC_AWCACHE => M_AXI_IC_AWCACHE,
M_AXI_IC_AWPROT => M_AXI_IC_AWPROT,
M_AXI_IC_AWQOS => M_AXI_IC_AWQOS,
M_AXI_IC_AWVALID => M_AXI_IC_AWVALID,
M_AXI_IC_AWREADY => M_AXI_IC_AWREADY,
M_AXI_IC_AWUSER => M_AXI_IC_AWUSER,
M_AXI_IC_AWDOMAIN => M_AXI_IC_AWDOMAIN,
M_AXI_IC_AWSNOOP => M_AXI_IC_AWSNOOP,
M_AXI_IC_AWBAR => M_AXI_IC_AWBAR,
M_AXI_IC_WDATA => M_AXI_IC_WDATA,
M_AXI_IC_WSTRB => M_AXI_IC_WSTRB,
M_AXI_IC_WLAST => M_AXI_IC_WLAST,
M_AXI_IC_WVALID => M_AXI_IC_WVALID,
M_AXI_IC_WREADY => M_AXI_IC_WREADY,
M_AXI_IC_WUSER => M_AXI_IC_WUSER,
M_AXI_IC_BID => M_AXI_IC_BID,
M_AXI_IC_BRESP => M_AXI_IC_BRESP,
M_AXI_IC_BVALID => M_AXI_IC_BVALID,
M_AXI_IC_BREADY => M_AXI_IC_BREADY,
M_AXI_IC_BUSER => M_AXI_IC_BUSER,
M_AXI_IC_WACK => M_AXI_IC_WACK,
M_AXI_IC_ARID => M_AXI_IC_ARID,
M_AXI_IC_ARADDR => M_AXI_IC_ARADDR,
M_AXI_IC_ARLEN => M_AXI_IC_ARLEN,
M_AXI_IC_ARSIZE => M_AXI_IC_ARSIZE,
M_AXI_IC_ARBURST => M_AXI_IC_ARBURST,
M_AXI_IC_ARLOCK => M_AXI_IC_ARLOCK,
M_AXI_IC_ARCACHE => M_AXI_IC_ARCACHE,
M_AXI_IC_ARPROT => M_AXI_IC_ARPROT,
M_AXI_IC_ARQOS => M_AXI_IC_ARQOS,
M_AXI_IC_ARVALID => M_AXI_IC_ARVALID,
M_AXI_IC_ARREADY => M_AXI_IC_ARREADY,
M_AXI_IC_ARUSER => M_AXI_IC_ARUSER,
M_AXI_IC_ARDOMAIN => M_AXI_IC_ARDOMAIN,
M_AXI_IC_ARSNOOP => M_AXI_IC_ARSNOOP,
M_AXI_IC_ARBAR => M_AXI_IC_ARBAR,
M_AXI_IC_RID => M_AXI_IC_RID,
M_AXI_IC_RDATA => M_AXI_IC_RDATA,
M_AXI_IC_RRESP => M_AXI_IC_RRESP,
M_AXI_IC_RLAST => M_AXI_IC_RLAST,
M_AXI_IC_RVALID => M_AXI_IC_RVALID,
M_AXI_IC_RREADY => M_AXI_IC_RREADY,
M_AXI_IC_RUSER => M_AXI_IC_RUSER,
M_AXI_IC_RACK => M_AXI_IC_RACK,
M_AXI_IC_ACVALID => M_AXI_IC_ACVALID,
M_AXI_IC_ACADDR => M_AXI_IC_ACADDR,
M_AXI_IC_ACSNOOP => M_AXI_IC_ACSNOOP,
M_AXI_IC_ACPROT => M_AXI_IC_ACPROT,
M_AXI_IC_ACREADY => M_AXI_IC_ACREADY,
M_AXI_IC_CRREADY => M_AXI_IC_CRREADY,
M_AXI_IC_CRVALID => M_AXI_IC_CRVALID,
M_AXI_IC_CRRESP => M_AXI_IC_CRRESP,
M_AXI_IC_CDVALID => M_AXI_IC_CDVALID,
M_AXI_IC_CDREADY => M_AXI_IC_CDREADY,
M_AXI_IC_CDDATA => M_AXI_IC_CDDATA,
M_AXI_IC_CDLAST => M_AXI_IC_CDLAST,
M_AXI_DC_AWID => M_AXI_DC_AWID,
M_AXI_DC_AWADDR => M_AXI_DC_AWADDR,
M_AXI_DC_AWLEN => M_AXI_DC_AWLEN,
M_AXI_DC_AWSIZE => M_AXI_DC_AWSIZE,
M_AXI_DC_AWBURST => M_AXI_DC_AWBURST,
M_AXI_DC_AWLOCK => M_AXI_DC_AWLOCK,
M_AXI_DC_AWCACHE => M_AXI_DC_AWCACHE,
M_AXI_DC_AWPROT => M_AXI_DC_AWPROT,
M_AXI_DC_AWQOS => M_AXI_DC_AWQOS,
M_AXI_DC_AWVALID => M_AXI_DC_AWVALID,
M_AXI_DC_AWREADY => M_AXI_DC_AWREADY,
M_AXI_DC_AWUSER => M_AXI_DC_AWUSER,
M_AXI_DC_AWDOMAIN => M_AXI_DC_AWDOMAIN,
M_AXI_DC_AWSNOOP => M_AXI_DC_AWSNOOP,
M_AXI_DC_AWBAR => M_AXI_DC_AWBAR,
M_AXI_DC_WDATA => M_AXI_DC_WDATA,
M_AXI_DC_WSTRB => M_AXI_DC_WSTRB,
M_AXI_DC_WLAST => M_AXI_DC_WLAST,
M_AXI_DC_WVALID => M_AXI_DC_WVALID,
M_AXI_DC_WREADY => M_AXI_DC_WREADY,
M_AXI_DC_WUSER => M_AXI_DC_WUSER,
M_AXI_DC_BID => M_AXI_DC_BID,
M_AXI_DC_BRESP => M_AXI_DC_BRESP,
M_AXI_DC_BVALID => M_AXI_DC_BVALID,
M_AXI_DC_BREADY => M_AXI_DC_BREADY,
M_AXI_DC_BUSER => M_AXI_DC_BUSER,
M_AXI_DC_WACK => M_AXI_DC_WACK,
M_AXI_DC_ARID => M_AXI_DC_ARID,
M_AXI_DC_ARADDR => M_AXI_DC_ARADDR,
M_AXI_DC_ARLEN => M_AXI_DC_ARLEN,
M_AXI_DC_ARSIZE => M_AXI_DC_ARSIZE,
M_AXI_DC_ARBURST => M_AXI_DC_ARBURST,
M_AXI_DC_ARLOCK => M_AXI_DC_ARLOCK,
M_AXI_DC_ARCACHE => M_AXI_DC_ARCACHE,
M_AXI_DC_ARPROT => M_AXI_DC_ARPROT,
M_AXI_DC_ARQOS => M_AXI_DC_ARQOS,
M_AXI_DC_ARVALID => M_AXI_DC_ARVALID,
M_AXI_DC_ARREADY => M_AXI_DC_ARREADY,
M_AXI_DC_ARUSER => M_AXI_DC_ARUSER,
M_AXI_DC_ARDOMAIN => M_AXI_DC_ARDOMAIN,
M_AXI_DC_ARSNOOP => M_AXI_DC_ARSNOOP,
M_AXI_DC_ARBAR => M_AXI_DC_ARBAR,
M_AXI_DC_RID => M_AXI_DC_RID,
M_AXI_DC_RDATA => M_AXI_DC_RDATA,
M_AXI_DC_RRESP => M_AXI_DC_RRESP,
M_AXI_DC_RLAST => M_AXI_DC_RLAST,
M_AXI_DC_RVALID => M_AXI_DC_RVALID,
M_AXI_DC_RREADY => M_AXI_DC_RREADY,
M_AXI_DC_RUSER => M_AXI_DC_RUSER,
M_AXI_DC_RACK => M_AXI_DC_RACK,
M_AXI_DC_ACVALID => M_AXI_DC_ACVALID,
M_AXI_DC_ACADDR => M_AXI_DC_ACADDR,
M_AXI_DC_ACSNOOP => M_AXI_DC_ACSNOOP,
M_AXI_DC_ACPROT => M_AXI_DC_ACPROT,
M_AXI_DC_ACREADY => M_AXI_DC_ACREADY,
M_AXI_DC_CRREADY => M_AXI_DC_CRREADY,
M_AXI_DC_CRVALID => M_AXI_DC_CRVALID,
M_AXI_DC_CRRESP => M_AXI_DC_CRRESP,
M_AXI_DC_CDVALID => M_AXI_DC_CDVALID,
M_AXI_DC_CDREADY => M_AXI_DC_CDREADY,
M_AXI_DC_CDDATA => M_AXI_DC_CDDATA,
M_AXI_DC_CDLAST => M_AXI_DC_CDLAST,
DBG_CLK => DBG_CLK,
DBG_TDI => DBG_TDI,
DBG_TDO => DBG_TDO,
DBG_REG_EN => DBG_REG_EN,
DBG_SHIFT => DBG_SHIFT,
DBG_CAPTURE => DBG_CAPTURE,
DBG_UPDATE => DBG_UPDATE,
DEBUG_RST => DEBUG_RST,
Trace_Instruction => Trace_Instruction,
Trace_Valid_Instr => Trace_Valid_Instr,
Trace_PC => Trace_PC,
Trace_Reg_Write => Trace_Reg_Write,
Trace_Reg_Addr => Trace_Reg_Addr,
Trace_MSR_Reg => Trace_MSR_Reg,
Trace_PID_Reg => Trace_PID_Reg,
Trace_New_Reg_Value => Trace_New_Reg_Value,
Trace_Exception_Taken => Trace_Exception_Taken,
Trace_Exception_Kind => Trace_Exception_Kind,
Trace_Jump_Taken => Trace_Jump_Taken,
Trace_Delay_Slot => Trace_Delay_Slot,
Trace_Data_Address => Trace_Data_Address,
Trace_Data_Access => Trace_Data_Access,
Trace_Data_Read => Trace_Data_Read,
Trace_Data_Write => Trace_Data_Write,
Trace_Data_Write_Value => Trace_Data_Write_Value,
Trace_Data_Byte_Enable => Trace_Data_Byte_Enable,
Trace_DCache_Req => Trace_DCache_Req,
Trace_DCache_Hit => Trace_DCache_Hit,
Trace_DCache_Rdy => Trace_DCache_Rdy,
Trace_DCache_Read => Trace_DCache_Read,
Trace_ICache_Req => Trace_ICache_Req,
Trace_ICache_Hit => Trace_ICache_Hit,
Trace_ICache_Rdy => Trace_ICache_Rdy,
Trace_OF_PipeRun => Trace_OF_PipeRun,
Trace_EX_PipeRun => Trace_EX_PipeRun,
Trace_MEM_PipeRun => Trace_MEM_PipeRun,
Trace_MB_Halted => Trace_MB_Halted,
Trace_Jump_Hit => Trace_Jump_Hit,
FSL0_S_CLK => FSL0_S_CLK,
FSL0_S_READ => FSL0_S_READ,
FSL0_S_DATA => FSL0_S_DATA,
FSL0_S_CONTROL => FSL0_S_CONTROL,
FSL0_S_EXISTS => FSL0_S_EXISTS,
FSL0_M_CLK => FSL0_M_CLK,
FSL0_M_WRITE => FSL0_M_WRITE,
FSL0_M_DATA => FSL0_M_DATA,
FSL0_M_CONTROL => FSL0_M_CONTROL,
FSL0_M_FULL => FSL0_M_FULL,
FSL1_S_CLK => FSL1_S_CLK,
FSL1_S_READ => FSL1_S_READ,
FSL1_S_DATA => FSL1_S_DATA,
FSL1_S_CONTROL => FSL1_S_CONTROL,
FSL1_S_EXISTS => FSL1_S_EXISTS,
FSL1_M_CLK => FSL1_M_CLK,
FSL1_M_WRITE => FSL1_M_WRITE,
FSL1_M_DATA => FSL1_M_DATA,
FSL1_M_CONTROL => FSL1_M_CONTROL,
FSL1_M_FULL => FSL1_M_FULL,
FSL2_S_CLK => FSL2_S_CLK,
FSL2_S_READ => FSL2_S_READ,
FSL2_S_DATA => FSL2_S_DATA,
FSL2_S_CONTROL => FSL2_S_CONTROL,
FSL2_S_EXISTS => FSL2_S_EXISTS,
FSL2_M_CLK => FSL2_M_CLK,
FSL2_M_WRITE => FSL2_M_WRITE,
FSL2_M_DATA => FSL2_M_DATA,
FSL2_M_CONTROL => FSL2_M_CONTROL,
FSL2_M_FULL => FSL2_M_FULL,
FSL3_S_CLK => FSL3_S_CLK,
FSL3_S_READ => FSL3_S_READ,
FSL3_S_DATA => FSL3_S_DATA,
FSL3_S_CONTROL => FSL3_S_CONTROL,
FSL3_S_EXISTS => FSL3_S_EXISTS,
FSL3_M_CLK => FSL3_M_CLK,
FSL3_M_WRITE => FSL3_M_WRITE,
FSL3_M_DATA => FSL3_M_DATA,
FSL3_M_CONTROL => FSL3_M_CONTROL,
FSL3_M_FULL => FSL3_M_FULL,
FSL4_S_CLK => FSL4_S_CLK,
FSL4_S_READ => FSL4_S_READ,
FSL4_S_DATA => FSL4_S_DATA,
FSL4_S_CONTROL => FSL4_S_CONTROL,
FSL4_S_EXISTS => FSL4_S_EXISTS,
FSL4_M_CLK => FSL4_M_CLK,
FSL4_M_WRITE => FSL4_M_WRITE,
FSL4_M_DATA => FSL4_M_DATA,
FSL4_M_CONTROL => FSL4_M_CONTROL,
FSL4_M_FULL => FSL4_M_FULL,
FSL5_S_CLK => FSL5_S_CLK,
FSL5_S_READ => FSL5_S_READ,
FSL5_S_DATA => FSL5_S_DATA,
FSL5_S_CONTROL => FSL5_S_CONTROL,
FSL5_S_EXISTS => FSL5_S_EXISTS,
FSL5_M_CLK => FSL5_M_CLK,
FSL5_M_WRITE => FSL5_M_WRITE,
FSL5_M_DATA => FSL5_M_DATA,
FSL5_M_CONTROL => FSL5_M_CONTROL,
FSL5_M_FULL => FSL5_M_FULL,
FSL6_S_CLK => FSL6_S_CLK,
FSL6_S_READ => FSL6_S_READ,
FSL6_S_DATA => FSL6_S_DATA,
FSL6_S_CONTROL => FSL6_S_CONTROL,
FSL6_S_EXISTS => FSL6_S_EXISTS,
FSL6_M_CLK => FSL6_M_CLK,
FSL6_M_WRITE => FSL6_M_WRITE,
FSL6_M_DATA => FSL6_M_DATA,
FSL6_M_CONTROL => FSL6_M_CONTROL,
FSL6_M_FULL => FSL6_M_FULL,
FSL7_S_CLK => FSL7_S_CLK,
FSL7_S_READ => FSL7_S_READ,
FSL7_S_DATA => FSL7_S_DATA,
FSL7_S_CONTROL => FSL7_S_CONTROL,
FSL7_S_EXISTS => FSL7_S_EXISTS,
FSL7_M_CLK => FSL7_M_CLK,
FSL7_M_WRITE => FSL7_M_WRITE,
FSL7_M_DATA => FSL7_M_DATA,
FSL7_M_CONTROL => FSL7_M_CONTROL,
FSL7_M_FULL => FSL7_M_FULL,
FSL8_S_CLK => FSL8_S_CLK,
FSL8_S_READ => FSL8_S_READ,
FSL8_S_DATA => FSL8_S_DATA,
FSL8_S_CONTROL => FSL8_S_CONTROL,
FSL8_S_EXISTS => FSL8_S_EXISTS,
FSL8_M_CLK => FSL8_M_CLK,
FSL8_M_WRITE => FSL8_M_WRITE,
FSL8_M_DATA => FSL8_M_DATA,
FSL8_M_CONTROL => FSL8_M_CONTROL,
FSL8_M_FULL => FSL8_M_FULL,
FSL9_S_CLK => FSL9_S_CLK,
FSL9_S_READ => FSL9_S_READ,
FSL9_S_DATA => FSL9_S_DATA,
FSL9_S_CONTROL => FSL9_S_CONTROL,
FSL9_S_EXISTS => FSL9_S_EXISTS,
FSL9_M_CLK => FSL9_M_CLK,
FSL9_M_WRITE => FSL9_M_WRITE,
FSL9_M_DATA => FSL9_M_DATA,
FSL9_M_CONTROL => FSL9_M_CONTROL,
FSL9_M_FULL => FSL9_M_FULL,
FSL10_S_CLK => FSL10_S_CLK,
FSL10_S_READ => FSL10_S_READ,
FSL10_S_DATA => FSL10_S_DATA,
FSL10_S_CONTROL => FSL10_S_CONTROL,
FSL10_S_EXISTS => FSL10_S_EXISTS,
FSL10_M_CLK => FSL10_M_CLK,
FSL10_M_WRITE => FSL10_M_WRITE,
FSL10_M_DATA => FSL10_M_DATA,
FSL10_M_CONTROL => FSL10_M_CONTROL,
FSL10_M_FULL => FSL10_M_FULL,
FSL11_S_CLK => FSL11_S_CLK,
FSL11_S_READ => FSL11_S_READ,
FSL11_S_DATA => FSL11_S_DATA,
FSL11_S_CONTROL => FSL11_S_CONTROL,
FSL11_S_EXISTS => FSL11_S_EXISTS,
FSL11_M_CLK => FSL11_M_CLK,
FSL11_M_WRITE => FSL11_M_WRITE,
FSL11_M_DATA => FSL11_M_DATA,
FSL11_M_CONTROL => FSL11_M_CONTROL,
FSL11_M_FULL => FSL11_M_FULL,
FSL12_S_CLK => FSL12_S_CLK,
FSL12_S_READ => FSL12_S_READ,
FSL12_S_DATA => FSL12_S_DATA,
FSL12_S_CONTROL => FSL12_S_CONTROL,
FSL12_S_EXISTS => FSL12_S_EXISTS,
FSL12_M_CLK => FSL12_M_CLK,
FSL12_M_WRITE => FSL12_M_WRITE,
FSL12_M_DATA => FSL12_M_DATA,
FSL12_M_CONTROL => FSL12_M_CONTROL,
FSL12_M_FULL => FSL12_M_FULL,
FSL13_S_CLK => FSL13_S_CLK,
FSL13_S_READ => FSL13_S_READ,
FSL13_S_DATA => FSL13_S_DATA,
FSL13_S_CONTROL => FSL13_S_CONTROL,
FSL13_S_EXISTS => FSL13_S_EXISTS,
FSL13_M_CLK => FSL13_M_CLK,
FSL13_M_WRITE => FSL13_M_WRITE,
FSL13_M_DATA => FSL13_M_DATA,
FSL13_M_CONTROL => FSL13_M_CONTROL,
FSL13_M_FULL => FSL13_M_FULL,
FSL14_S_CLK => FSL14_S_CLK,
FSL14_S_READ => FSL14_S_READ,
FSL14_S_DATA => FSL14_S_DATA,
FSL14_S_CONTROL => FSL14_S_CONTROL,
FSL14_S_EXISTS => FSL14_S_EXISTS,
FSL14_M_CLK => FSL14_M_CLK,
FSL14_M_WRITE => FSL14_M_WRITE,
FSL14_M_DATA => FSL14_M_DATA,
FSL14_M_CONTROL => FSL14_M_CONTROL,
FSL14_M_FULL => FSL14_M_FULL,
FSL15_S_CLK => FSL15_S_CLK,
FSL15_S_READ => FSL15_S_READ,
FSL15_S_DATA => FSL15_S_DATA,
FSL15_S_CONTROL => FSL15_S_CONTROL,
FSL15_S_EXISTS => FSL15_S_EXISTS,
FSL15_M_CLK => FSL15_M_CLK,
FSL15_M_WRITE => FSL15_M_WRITE,
FSL15_M_DATA => FSL15_M_DATA,
FSL15_M_CONTROL => FSL15_M_CONTROL,
FSL15_M_FULL => FSL15_M_FULL,
M0_AXIS_TLAST => M0_AXIS_TLAST,
M0_AXIS_TDATA => M0_AXIS_TDATA,
M0_AXIS_TVALID => M0_AXIS_TVALID,
M0_AXIS_TREADY => M0_AXIS_TREADY,
S0_AXIS_TLAST => S0_AXIS_TLAST,
S0_AXIS_TDATA => S0_AXIS_TDATA,
S0_AXIS_TVALID => S0_AXIS_TVALID,
S0_AXIS_TREADY => S0_AXIS_TREADY,
M1_AXIS_TLAST => M1_AXIS_TLAST,
M1_AXIS_TDATA => M1_AXIS_TDATA,
M1_AXIS_TVALID => M1_AXIS_TVALID,
M1_AXIS_TREADY => M1_AXIS_TREADY,
S1_AXIS_TLAST => S1_AXIS_TLAST,
S1_AXIS_TDATA => S1_AXIS_TDATA,
S1_AXIS_TVALID => S1_AXIS_TVALID,
S1_AXIS_TREADY => S1_AXIS_TREADY,
M2_AXIS_TLAST => M2_AXIS_TLAST,
M2_AXIS_TDATA => M2_AXIS_TDATA,
M2_AXIS_TVALID => M2_AXIS_TVALID,
M2_AXIS_TREADY => M2_AXIS_TREADY,
S2_AXIS_TLAST => S2_AXIS_TLAST,
S2_AXIS_TDATA => S2_AXIS_TDATA,
S2_AXIS_TVALID => S2_AXIS_TVALID,
S2_AXIS_TREADY => S2_AXIS_TREADY,
M3_AXIS_TLAST => M3_AXIS_TLAST,
M3_AXIS_TDATA => M3_AXIS_TDATA,
M3_AXIS_TVALID => M3_AXIS_TVALID,
M3_AXIS_TREADY => M3_AXIS_TREADY,
S3_AXIS_TLAST => S3_AXIS_TLAST,
S3_AXIS_TDATA => S3_AXIS_TDATA,
S3_AXIS_TVALID => S3_AXIS_TVALID,
S3_AXIS_TREADY => S3_AXIS_TREADY,
M4_AXIS_TLAST => M4_AXIS_TLAST,
M4_AXIS_TDATA => M4_AXIS_TDATA,
M4_AXIS_TVALID => M4_AXIS_TVALID,
M4_AXIS_TREADY => M4_AXIS_TREADY,
S4_AXIS_TLAST => S4_AXIS_TLAST,
S4_AXIS_TDATA => S4_AXIS_TDATA,
S4_AXIS_TVALID => S4_AXIS_TVALID,
S4_AXIS_TREADY => S4_AXIS_TREADY,
M5_AXIS_TLAST => M5_AXIS_TLAST,
M5_AXIS_TDATA => M5_AXIS_TDATA,
M5_AXIS_TVALID => M5_AXIS_TVALID,
M5_AXIS_TREADY => M5_AXIS_TREADY,
S5_AXIS_TLAST => S5_AXIS_TLAST,
S5_AXIS_TDATA => S5_AXIS_TDATA,
S5_AXIS_TVALID => S5_AXIS_TVALID,
S5_AXIS_TREADY => S5_AXIS_TREADY,
M6_AXIS_TLAST => M6_AXIS_TLAST,
M6_AXIS_TDATA => M6_AXIS_TDATA,
M6_AXIS_TVALID => M6_AXIS_TVALID,
M6_AXIS_TREADY => M6_AXIS_TREADY,
S6_AXIS_TLAST => S6_AXIS_TLAST,
S6_AXIS_TDATA => S6_AXIS_TDATA,
S6_AXIS_TVALID => S6_AXIS_TVALID,
S6_AXIS_TREADY => S6_AXIS_TREADY,
M7_AXIS_TLAST => M7_AXIS_TLAST,
M7_AXIS_TDATA => M7_AXIS_TDATA,
M7_AXIS_TVALID => M7_AXIS_TVALID,
M7_AXIS_TREADY => M7_AXIS_TREADY,
S7_AXIS_TLAST => S7_AXIS_TLAST,
S7_AXIS_TDATA => S7_AXIS_TDATA,
S7_AXIS_TVALID => S7_AXIS_TVALID,
S7_AXIS_TREADY => S7_AXIS_TREADY,
M8_AXIS_TLAST => M8_AXIS_TLAST,
M8_AXIS_TDATA => M8_AXIS_TDATA,
M8_AXIS_TVALID => M8_AXIS_TVALID,
M8_AXIS_TREADY => M8_AXIS_TREADY,
S8_AXIS_TLAST => S8_AXIS_TLAST,
S8_AXIS_TDATA => S8_AXIS_TDATA,
S8_AXIS_TVALID => S8_AXIS_TVALID,
S8_AXIS_TREADY => S8_AXIS_TREADY,
M9_AXIS_TLAST => M9_AXIS_TLAST,
M9_AXIS_TDATA => M9_AXIS_TDATA,
M9_AXIS_TVALID => M9_AXIS_TVALID,
M9_AXIS_TREADY => M9_AXIS_TREADY,
S9_AXIS_TLAST => S9_AXIS_TLAST,
S9_AXIS_TDATA => S9_AXIS_TDATA,
S9_AXIS_TVALID => S9_AXIS_TVALID,
S9_AXIS_TREADY => S9_AXIS_TREADY,
M10_AXIS_TLAST => M10_AXIS_TLAST,
M10_AXIS_TDATA => M10_AXIS_TDATA,
M10_AXIS_TVALID => M10_AXIS_TVALID,
M10_AXIS_TREADY => M10_AXIS_TREADY,
S10_AXIS_TLAST => S10_AXIS_TLAST,
S10_AXIS_TDATA => S10_AXIS_TDATA,
S10_AXIS_TVALID => S10_AXIS_TVALID,
S10_AXIS_TREADY => S10_AXIS_TREADY,
M11_AXIS_TLAST => M11_AXIS_TLAST,
M11_AXIS_TDATA => M11_AXIS_TDATA,
M11_AXIS_TVALID => M11_AXIS_TVALID,
M11_AXIS_TREADY => M11_AXIS_TREADY,
S11_AXIS_TLAST => S11_AXIS_TLAST,
S11_AXIS_TDATA => S11_AXIS_TDATA,
S11_AXIS_TVALID => S11_AXIS_TVALID,
S11_AXIS_TREADY => S11_AXIS_TREADY,
M12_AXIS_TLAST => M12_AXIS_TLAST,
M12_AXIS_TDATA => M12_AXIS_TDATA,
M12_AXIS_TVALID => M12_AXIS_TVALID,
M12_AXIS_TREADY => M12_AXIS_TREADY,
S12_AXIS_TLAST => S12_AXIS_TLAST,
S12_AXIS_TDATA => S12_AXIS_TDATA,
S12_AXIS_TVALID => S12_AXIS_TVALID,
S12_AXIS_TREADY => S12_AXIS_TREADY,
M13_AXIS_TLAST => M13_AXIS_TLAST,
M13_AXIS_TDATA => M13_AXIS_TDATA,
M13_AXIS_TVALID => M13_AXIS_TVALID,
M13_AXIS_TREADY => M13_AXIS_TREADY,
S13_AXIS_TLAST => S13_AXIS_TLAST,
S13_AXIS_TDATA => S13_AXIS_TDATA,
S13_AXIS_TVALID => S13_AXIS_TVALID,
S13_AXIS_TREADY => S13_AXIS_TREADY,
M14_AXIS_TLAST => M14_AXIS_TLAST,
M14_AXIS_TDATA => M14_AXIS_TDATA,
M14_AXIS_TVALID => M14_AXIS_TVALID,
M14_AXIS_TREADY => M14_AXIS_TREADY,
S14_AXIS_TLAST => S14_AXIS_TLAST,
S14_AXIS_TDATA => S14_AXIS_TDATA,
S14_AXIS_TVALID => S14_AXIS_TVALID,
S14_AXIS_TREADY => S14_AXIS_TREADY,
M15_AXIS_TLAST => M15_AXIS_TLAST,
M15_AXIS_TDATA => M15_AXIS_TDATA,
M15_AXIS_TVALID => M15_AXIS_TVALID,
M15_AXIS_TREADY => M15_AXIS_TREADY,
S15_AXIS_TLAST => S15_AXIS_TLAST,
S15_AXIS_TDATA => S15_AXIS_TDATA,
S15_AXIS_TVALID => S15_AXIS_TVALID,
S15_AXIS_TREADY => S15_AXIS_TREADY,
ICACHE_FSL_IN_CLK => ICACHE_FSL_IN_CLK,
ICACHE_FSL_IN_READ => ICACHE_FSL_IN_READ,
ICACHE_FSL_IN_DATA => ICACHE_FSL_IN_DATA,
ICACHE_FSL_IN_CONTROL => ICACHE_FSL_IN_CONTROL,
ICACHE_FSL_IN_EXISTS => ICACHE_FSL_IN_EXISTS,
ICACHE_FSL_OUT_CLK => ICACHE_FSL_OUT_CLK,
ICACHE_FSL_OUT_WRITE => ICACHE_FSL_OUT_WRITE,
ICACHE_FSL_OUT_DATA => ICACHE_FSL_OUT_DATA,
ICACHE_FSL_OUT_CONTROL => ICACHE_FSL_OUT_CONTROL,
ICACHE_FSL_OUT_FULL => ICACHE_FSL_OUT_FULL,
DCACHE_FSL_IN_CLK => DCACHE_FSL_IN_CLK,
DCACHE_FSL_IN_READ => DCACHE_FSL_IN_READ,
DCACHE_FSL_IN_DATA => DCACHE_FSL_IN_DATA,
DCACHE_FSL_IN_CONTROL => DCACHE_FSL_IN_CONTROL,
DCACHE_FSL_IN_EXISTS => DCACHE_FSL_IN_EXISTS,
DCACHE_FSL_OUT_CLK => DCACHE_FSL_OUT_CLK,
DCACHE_FSL_OUT_WRITE => DCACHE_FSL_OUT_WRITE,
DCACHE_FSL_OUT_DATA => DCACHE_FSL_OUT_DATA,
DCACHE_FSL_OUT_CONTROL => DCACHE_FSL_OUT_CONTROL,
DCACHE_FSL_OUT_FULL => DCACHE_FSL_OUT_FULL
);
end architecture STRUCTURE;
| lgpl-3.0 | 0d8efc0b3ef91e834b4902e104e2614d | 0.606706 | 2.748698 | false | false | false | false |
grwlf/vsim | vhdl/IEEE/mentor/std_logic_arith_body.vhdl | 7 | 103,728 | LIBRARY ieee;
-- LIBRARY arithmetic;
PACKAGE BODY std_logic_arith IS
USE ieee.std_logic_1164.ALL;
-- USE arithmetic.utils.all;
-------------------------------------------------------------------
-- Local Types
-------------------------------------------------------------------
TYPE stdlogic_1d IS ARRAY (std_ulogic) OF std_ulogic;
TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic;
TYPE stdlogic_boolean_table IS ARRAY(std_ulogic, std_ulogic) OF BOOLEAN;
--------------------------------------------------------------------
--------------------------------------------------------------------
-- FUNCTIONS DEFINED FOR SYNTHESIS
--------------------------------------------------------------------
--------------------------------------------------------------------
FUNCTION std_ulogic_wired_or ( input : std_ulogic_vector ) RETURN std_ulogic IS
VARIABLE result : std_ulogic := '-'; -- weakest state default
CONSTANT resolution_table : stdlogic_table := (
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ---------------------------------------------------------
( 'X', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | U |
( 'X', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | X |
( 'X', 'X', '0', '1', '0', 'X', '0', '1', '0' ), -- | 0 |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | 1 |
( 'X', 'X', '0', '1', 'Z', 'X', '0', '1', 'Z' ), -- | Z |
( 'X', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | W |
( 'X', 'X', '0', '1', '0', 'X', '0', '1', '0' ), -- | L |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | H |
( 'X', 'X', '0', '1', 'Z', 'X', '0', '1', 'Z' ) -- | D |
);
BEGIN
-- Iterate through all inputs
FOR i IN input'range LOOP
result := resolution_table(result, input(i));
END LOOP;
-- Return the resultant value
RETURN result;
END std_ulogic_wired_or;
FUNCTION std_ulogic_wired_and ( input : std_ulogic_vector ) RETURN std_ulogic IS
VARIABLE result : std_ulogic := '-'; -- weakest state default
CONSTANT resolution_table : stdlogic_table := (
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ---------------------------------------------------------
( 'X', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | U |
( 'X', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | 0 |
( 'X', 'X', '0', '1', '1', 'X', '0', '1', '1' ), -- | 1 |
( 'X', 'X', '0', '1', 'Z', 'X', '0', '1', 'Z' ), -- | Z |
( 'X', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | W |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L |
( 'X', 'X', '0', '1', '1', 'X', '0', '1', '1' ), -- | H |
( 'X', 'X', '0', '1', 'Z', 'X', '0', '1', 'Z' ) -- | D |
);
BEGIN
-- Iterate through all inputs
FOR i IN input'range LOOP
result := resolution_table(result, input(i));
END LOOP;
-- Return the resultant value
RETURN result;
END std_ulogic_wired_and;
--
-- MGC base level functions
--
--
-- Convert Base Type to Integer
--
FUNCTION to_integer (arg1 : STD_ULOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE tmp : SIGNED( arg1'length - 1 DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : INTEGER;
BEGIN
tmp := SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END to_integer;
FUNCTION to_integer (arg1 : STD_LOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE tmp : SIGNED( arg1'length - 1 DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : INTEGER;
BEGIN
tmp := SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END to_integer;
FUNCTION to_integer (arg1 : UNSIGNED; x : INTEGER := 0 ) RETURN NATURAL IS
VARIABLE tmp : SIGNED( arg1'length DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : NATURAL;
BEGIN
tmp := '0' & SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END to_integer;
FUNCTION TO_INTEGER (arg1 : SIGNED; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE return_int,x_tmp : INTEGER := 0;
BEGIN
ASSERT arg1'length > 0
REPORT "NULL vector, returning 0"
SEVERITY NOTE;
assert arg1'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
ASSERT arg1'length <= 32 -- implementation dependent limit
REPORT "vector too large, conversion may cause overflow"
SEVERITY WARNING;
IF x /= 0 THEN
x_tmp := 1;
END IF;
IF arg1(arg1'left) = '0' OR arg1(arg1'left) = 'L' OR -- positive value
( x_tmp = 0 AND arg1(arg1'left) /= '1' AND arg1(arg1'left) /= 'H') THEN
FOR i IN arg1'range LOOP
return_int := return_int * 2;
CASE arg1(i) IS
WHEN '0'|'L' => NULL;
WHEN '1'|'H' => return_int := return_int + 1;
WHEN OTHERS => return_int := return_int + x_tmp;
END CASE;
END LOOP;
ELSE -- negative value
IF (x_tmp = 0) THEN
x_tmp := 1;
ELSE
x_tmp := 0;
END IF;
FOR i IN arg1'range LOOP
return_int := return_int * 2;
CASE arg1(i) IS
WHEN '0'|'L' => return_int := return_int + 1;
WHEN '1'|'H' => NULL;
WHEN OTHERS => return_int := return_int + x_tmp;
END CASE;
END LOOP;
return_int := (-return_int) - 1;
END IF;
RETURN return_int;
END TO_INTEGER;
FUNCTION to_integer (arg1:STD_LOGIC; x : INTEGER := 0 ) RETURN NATURAL IS
BEGIN
IF(arg1 = '0' OR arg1 = 'L' OR (x = 0 AND arg1 /= '1' AND arg1 /= 'H')) THEN
RETURN(0);
ELSE
RETURN(1) ;
END IF ;
END ;
FUNCTION conv_integer (arg1 : STD_ULOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE tmp : SIGNED( arg1'length - 1 DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : INTEGER;
BEGIN
tmp := SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END ;
FUNCTION conv_integer (arg1 : STD_LOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE tmp : SIGNED( arg1'length -1 DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : INTEGER;
BEGIN
tmp := SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END ;
FUNCTION conv_integer (arg1 : UNSIGNED; x : INTEGER := 0 ) RETURN NATURAL IS
VARIABLE tmp : SIGNED( arg1'length DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : NATURAL;
BEGIN
tmp := '0' & SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END ;
FUNCTION conv_INTEGER (arg1 : SIGNED; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE return_int,x_tmp : INTEGER := 0;
BEGIN
ASSERT arg1'length > 0
REPORT "NULL vector, returning 0"
SEVERITY NOTE;
assert arg1'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
ASSERT arg1'length <= 32 -- implementation dependent limit
REPORT "vector too large, conversion may cause overflow"
SEVERITY WARNING;
IF x /= 0 THEN
x_tmp := 1;
END IF;
IF arg1(arg1'left) = '0' OR arg1(arg1'left) = 'L' OR -- positive value
( x_tmp = 0 AND arg1(arg1'left) /= '1' AND arg1(arg1'left) /= 'H') THEN
FOR i IN arg1'range LOOP
return_int := return_int * 2;
CASE arg1(i) IS
WHEN '0'|'L' => NULL;
WHEN '1'|'H' => return_int := return_int + 1;
WHEN OTHERS => return_int := return_int + x_tmp;
END CASE;
END LOOP;
ELSE -- negative value
IF (x_tmp = 0) THEN
x_tmp := 1;
ELSE
x_tmp := 0;
END IF;
FOR i IN arg1'range LOOP
return_int := return_int * 2;
CASE arg1(i) IS
WHEN '0'|'L' => return_int := return_int + 1;
WHEN '1'|'H' => NULL;
WHEN OTHERS => return_int := return_int + x_tmp;
END CASE;
END LOOP;
return_int := (-return_int) - 1;
END IF;
RETURN return_int;
END ;
FUNCTION conv_integer (arg1:STD_LOGIC; x : INTEGER := 0 ) RETURN NATURAL IS
BEGIN
IF(arg1 = '0' OR arg1 = 'L' OR (x = 0 AND arg1 /= '1' AND arg1 /= 'H')) THEN
RETURN(0);
ELSE
RETURN(1) ;
END IF ;
END ;
--
-- Convert Base Type to STD_LOGIC
--
FUNCTION to_stdlogic (arg1:BOOLEAN) RETURN STD_LOGIC IS
BEGIN
IF(arg1) THEN
RETURN('1') ;
ELSE
RETURN('0') ;
END IF ;
END ;
--
-- Convert Base Type to STD_LOGIC_VECTOR
--
FUNCTION To_StdlogicVector (arg1 : integer; size : NATURAL) RETURN std_logic_vector IS
VARIABLE vector : std_logic_vector(0 TO size-1);
VARIABLE tmp_int : integer := arg1;
VARIABLE carry : std_logic := '1'; -- setup to add 1 if needed
VARIABLE carry2 : std_logic;
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
IF arg1 < 0 THEN
FOR i IN size-1 DOWNTO 0 LOOP
carry2 := (NOT vector(i)) AND carry;
vector(i) := (NOT vector(i)) XOR carry;
carry := carry2;
END LOOP;
END IF;
RETURN vector;
END To_StdlogicVector;
FUNCTION To_StdUlogicVector (arg1 : integer; size : NATURAL) RETURN std_ulogic_vector IS
VARIABLE vector : std_ulogic_vector(0 TO size-1);
VARIABLE tmp_int : integer := arg1;
VARIABLE carry : std_ulogic := '1'; -- setup to add 1 if needed
VARIABLE carry2 : std_ulogic;
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
IF arg1 < 0 THEN
FOR i IN size-1 DOWNTO 0 LOOP
carry2 := (NOT vector(i)) AND carry;
vector(i) := (NOT vector(i)) XOR carry;
carry := carry2;
END LOOP;
END IF;
RETURN vector;
END To_StdUlogicVector;
--
-- Convert Base Type to UNSIGNED
--
FUNCTION to_unsigned (arg1:NATURAL ; size:NATURAL) RETURN UNSIGNED IS
VARIABLE vector : UNSIGNED(0 TO size-1) := (OTHERS => '0');
VARIABLE tmp_int : INTEGER := arg1;
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
RETURN vector;
END ;
FUNCTION conv_unsigned (arg1:NATURAL ; size:NATURAL) RETURN UNSIGNED IS
VARIABLE vector : UNSIGNED(0 TO size-1) := (OTHERS => '0');
VARIABLE tmp_int : INTEGER := arg1;
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
RETURN vector;
END ;
--
-- Convert Base Type to SIGNED
--
FUNCTION to_signed (arg1:INTEGER ; size : NATURAL) RETURN SIGNED IS
VARIABLE vector : SIGNED(0 TO size-1) := (OTHERS => '0');
VARIABLE tmp_int : INTEGER := arg1;
VARIABLE carry : STD_LOGIC := '1'; -- setup to add 1 if needed
VARIABLE carry2 : STD_LOGIC := '0';
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
IF arg1 < 0 THEN
FOR i IN size-1 DOWNTO 0 LOOP
carry2 := (NOT vector(i)) AND carry;
vector(i) := (NOT vector(i)) XOR carry;
carry := carry2;
END LOOP;
END IF;
RETURN vector;
END ;
FUNCTION conv_signed (arg1:INTEGER ; size : NATURAL) RETURN SIGNED IS
VARIABLE vector : SIGNED(0 TO size-1) := (OTHERS => '0');
VARIABLE tmp_int : INTEGER := arg1;
VARIABLE carry : STD_LOGIC := '1'; -- setup to add 1 if needed
VARIABLE carry2 : STD_LOGIC := '0';
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
IF arg1 < 0 THEN
FOR i IN size-1 DOWNTO 0 LOOP
carry2 := (NOT vector(i)) AND carry;
vector(i) := (NOT vector(i)) XOR carry;
carry := carry2;
END LOOP;
END IF;
RETURN vector;
END ;
-- sign/zero extend functions
--
FUNCTION zero_extend ( arg1 : STD_ULOGIC_VECTOR; size : NATURAL ) RETURN STD_ULOGIC_VECTOR
IS
VARIABLE answer : STD_ULOGIC_VECTOR(size-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
ASSERT arg1'length <= size
REPORT "Vector is already larger then size."
SEVERITY WARNING ;
answer := (OTHERS => '0') ;
answer(arg1'length-1 DOWNTO 0) := arg1;
RETURN(answer) ;
END ;
FUNCTION zero_extend ( arg1 : STD_LOGIC_VECTOR; size : NATURAL ) RETURN STD_LOGIC_VECTOR
IS
VARIABLE answer : STD_LOGIC_VECTOR(size-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
ASSERT arg1'length <= size
REPORT "Vector is already larger then size."
SEVERITY WARNING ;
answer := (OTHERS => '0') ;
answer(arg1'length-1 DOWNTO 0) := arg1;
RETURN(answer) ;
END ;
FUNCTION zero_extend ( arg1 : STD_LOGIC; size : NATURAL ) RETURN STD_LOGIC_VECTOR
IS
VARIABLE answer : STD_LOGIC_VECTOR(size-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
answer := (OTHERS => '0') ;
answer(0) := arg1;
RETURN(answer) ;
END ;
FUNCTION zero_extend ( arg1 : UNSIGNED; size : NATURAL ) RETURN UNSIGNED IS
VARIABLE answer : UNSIGNED(size-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
ASSERT arg1'length <= size
REPORT "Vector is already larger then size."
SEVERITY WARNING ;
answer := (OTHERS => '0') ;
answer(arg1'length - 1 DOWNTO 0) := arg1;
RETURN(answer) ;
END ;
FUNCTION sign_extend ( arg1 : SIGNED; size : NATURAL ) RETURN SIGNED IS
VARIABLE answer : SIGNED(size-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
ASSERT arg1'length <= size
REPORT "Vector is already larger then size."
SEVERITY WARNING ;
answer := (OTHERS => arg1(arg1'left)) ;
answer(arg1'length - 1 DOWNTO 0) := arg1;
RETURN(answer) ;
END ;
-- Some useful generic functions
--//// Zero Extend ////
--
-- Function zxt
--
FUNCTION zxt( q : STD_ULOGIC_VECTOR; i : INTEGER ) RETURN STD_ULOGIC_VECTOR IS
VARIABLE qs : STD_ULOGIC_VECTOR (1 TO i);
VARIABLE qt : STD_ULOGIC_VECTOR (1 TO q'length);
BEGIN
qt := q;
IF i < q'length THEN
qs := qt( (q'length-i+1) TO qt'right);
ELSIF i > q'length THEN
qs := (OTHERS=>'0');
qs := qs(1 TO (i-q'length)) & qt;
ELSE
qs := qt;
END IF;
RETURN qs;
END;
--//// Zero Extend ////
--
-- Function zxt
--
FUNCTION zxt( q : STD_LOGIC_VECTOR; i : INTEGER ) RETURN STD_LOGIC_VECTOR IS
VARIABLE qs : STD_LOGIC_VECTOR (1 TO i);
VARIABLE qt : STD_LOGIC_VECTOR (1 TO q'length);
BEGIN
qt := q;
IF i < q'length THEN
qs := qt( (q'length-i+1) TO qt'right);
ELSIF i > q'length THEN
qs := (OTHERS=>'0');
qs := qs(1 TO (i-q'length)) & qt;
ELSE
qs := qt;
END IF;
RETURN qs;
END;
--//// Zero Extend ////
--
-- Function zxt
--
FUNCTION zxt( q : UNSIGNED; i : INTEGER ) RETURN UNSIGNED IS
VARIABLE qs : UNSIGNED (1 TO i);
VARIABLE qt : UNSIGNED (1 TO q'length);
BEGIN
qt := q;
IF i < q'length THEN
qs := qt( (q'length-i+1) TO qt'right);
ELSIF i > q'length THEN
qs := (OTHERS=>'0');
qs := qs(1 TO (i-q'length)) & qt;
ELSE
qs := qt;
END IF;
RETURN qs;
END;
--------------------------------------
-- Synthesizable addition Functions --
--------------------------------------
FUNCTION "+" ( arg1, arg2 : STD_LOGIC ) RETURN STD_LOGIC IS
-- truth table for "xor" function
CONSTANT xor_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | D |
);
BEGIN
RETURN xor_table( arg1, arg2 );
END "+";
function maximum (arg1, arg2: integer) return integer is
begin
if arg1 > arg2 then
return arg1;
else
return arg2;
end if;
end;
FUNCTION "+" (arg1, arg2 :STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE res : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE carry : STD_ULOGIC := '0';
VARIABLE a,b,s1 : STD_ULOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := rt(i);
s1 := a + b;
res(i) := s1 + carry;
carry := (a AND b) OR (s1 AND carry);
END LOOP;
RETURN res;
END;
FUNCTION "+" (arg1, arg2 :STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE res : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE carry : STD_LOGIC := '0';
VARIABLE a,b,s1 : STD_LOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := rt(i);
s1 := a + b;
res(i) := s1 + carry;
carry := (a AND b) OR (s1 AND carry);
END LOOP;
RETURN res;
END;
FUNCTION "+" (arg1, arg2:UNSIGNED) RETURN UNSIGNED IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : UNSIGNED(1 TO ml);
VARIABLE rt : UNSIGNED(1 TO ml);
VARIABLE res : UNSIGNED(1 TO ml);
VARIABLE carry : STD_LOGIC := '0';
VARIABLE a,b,s1 : STD_LOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := rt(i);
s1 := a + b;
res(i) := s1 + carry;
carry := (a AND b) OR (s1 AND carry);
END LOOP;
RETURN res;
END;
FUNCTION "+" (arg1, arg2:SIGNED) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
assert arg1'length > 1 AND arg2'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a + b);
RETURN (answer);
END ;
-----------------------------------------
-- Synthesizable subtraction Functions --
-----------------------------------------
FUNCTION "-" ( arg1, arg2 : std_logic ) RETURN std_logic IS
-- truth table for "xor" function
CONSTANT xor_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | D |
);
BEGIN
RETURN xor_table( arg1, arg2 );
END "-";
FUNCTION "-" (arg1, arg2:STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE res : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE borrow : STD_ULOGIC := '1';
VARIABLE a,b,s1 : STD_ULOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := NOT rt(i);
s1 := a + b;
res(i) := s1 + borrow;
borrow := (a AND b) OR (s1 AND borrow);
END LOOP;
RETURN res;
END "-";
FUNCTION "-" (arg1, arg2:STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE res : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE borrow : STD_LOGIC := '1';
VARIABLE a,b,s1 : STD_LOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := NOT rt(i);
s1 := a + b;
res(i) := s1 + borrow;
borrow := (a AND b) OR (s1 AND borrow);
END LOOP;
RETURN res;
END "-";
FUNCTION "-" (arg1, arg2:UNSIGNED) RETURN UNSIGNED IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : UNSIGNED(1 TO ml);
VARIABLE rt : UNSIGNED(1 TO ml);
VARIABLE res : UNSIGNED(1 TO ml);
VARIABLE borrow : STD_LOGIC := '1';
VARIABLE a,b,s1 : STD_LOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := NOT rt(i);
s1 := a + b;
res(i) := s1 + borrow;
borrow := (a AND b) OR (s1 AND borrow);
END LOOP;
RETURN res;
END "-";
FUNCTION "-" (arg1, arg2:SIGNED) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
assert arg1'length > 1 AND arg2'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED( a - b );
RETURN (answer);
END ;
-----------------------------------------
-- Unary subtract and add Functions --
-----------------------------------------
FUNCTION "+" (arg1:STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
BEGIN
RETURN (arg1);
END;
FUNCTION "+" (arg1:STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
BEGIN
RETURN (arg1);
END;
FUNCTION "+" (arg1:UNSIGNED) RETURN UNSIGNED IS
BEGIN
RETURN (arg1);
END;
FUNCTION "+" (arg1:SIGNED) RETURN SIGNED IS
BEGIN
RETURN (arg1);
END;
FUNCTION hasx( v : SIGNED ) RETURN BOOLEAN IS
BEGIN
FOR i IN v'range LOOP
IF v(i) = '0' OR v(i) = '1' OR v(i) = 'L' OR v(i) = 'H'THEN
NULL;
ELSE
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END hasx;
FUNCTION "-" (arg1:SIGNED) RETURN SIGNED IS
constant len : integer := arg1'length;
VARIABLE answer, tmp : SIGNED( len-1 downto 0 ) := (others=>'0');
VARIABLE index : integer := len;
BEGIN
assert arg1'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
IF hasx(arg1) THEN
answer := (OTHERS => 'X');
ELSE
tmp := arg1;
lp1 : FOR i IN answer'REVERSE_RANGE LOOP
IF (tmp(i) = '1' OR tmp(i) = 'H') THEN
index := i+1;
answer(i downto 0) := tmp(i downto 0);
exit;
END IF;
END LOOP lp1;
answer(len-1 downto index) := NOT tmp(len-1 downto index);
end if;
RETURN (answer);
END ;
--------------------------------------------
-- Synthesizable multiplication Functions --
--------------------------------------------
FUNCTION shift( v : STD_ULOGIC_VECTOR ) RETURN STD_ULOGIC_VECTOR IS
VARIABLE v1 : STD_ULOGIC_VECTOR( v'range );
BEGIN
FOR i IN (v'left+1) TO v'right LOOP
v1(i-1) := v(i);
END LOOP;
v1(v1'right) := '0';
RETURN v1;
END shift;
PROCEDURE copy(a : IN STD_ULOGIC_VECTOR; b : OUT STD_ULOGIC_VECTOR) IS
VARIABLE bi : INTEGER := b'right;
BEGIN
FOR i IN a'reverse_range LOOP
b(bi) := a(i);
bi := bi - 1;
END LOOP;
END copy;
FUNCTION shift( v : STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR IS
VARIABLE v1 : STD_LOGIC_VECTOR( v'range );
BEGIN
FOR i IN (v'left+1) TO v'right LOOP
v1(i-1) := v(i);
END LOOP;
v1(v1'right) := '0';
RETURN v1;
END shift;
PROCEDURE copy(a : IN STD_LOGIC_VECTOR; b : OUT STD_LOGIC_VECTOR) IS
VARIABLE bi : INTEGER := b'right;
BEGIN
FOR i IN a'reverse_range LOOP
b(bi) := a(i);
bi := bi - 1;
END LOOP;
END copy;
FUNCTION shift( v : SIGNED ) RETURN SIGNED IS
VARIABLE v1 : SIGNED( v'range );
BEGIN
FOR i IN (v'left+1) TO v'right LOOP
v1(i-1) := v(i);
END LOOP;
v1(v1'right) := '0';
RETURN v1;
END shift;
PROCEDURE copy(a : IN SIGNED; b : OUT SIGNED) IS
VARIABLE bi : INTEGER := b'right;
BEGIN
FOR i IN a'reverse_range LOOP
b(bi) := a(i);
bi := bi - 1;
END LOOP;
END copy;
FUNCTION shift( v : UNSIGNED ) RETURN UNSIGNED IS
VARIABLE v1 : UNSIGNED( v'range );
BEGIN
FOR i IN (v'left+1) TO v'right LOOP
v1(i-1) := v(i);
END LOOP;
v1(v1'right) := '0';
RETURN v1;
END shift;
PROCEDURE copy(a : IN UNSIGNED; b : OUT UNSIGNED) IS
VARIABLE bi : INTEGER := b'right;
BEGIN
FOR i IN a'reverse_range LOOP
b(bi) := a(i);
bi := bi - 1;
END LOOP;
END copy;
FUNCTION "*" (arg1, arg2:STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
VARIABLE ml : INTEGER := arg1'length + arg2'length;
VARIABLE lt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE prod : STD_ULOGIC_VECTOR(1 TO ml) := (OTHERS=>'0');
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN rt'reverse_range LOOP
IF rt(i) = '1' THEN
prod := prod + lt;
END IF;
lt := shift(lt);
END LOOP;
RETURN prod;
END "*";
FUNCTION "*" (arg1, arg2:STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
VARIABLE ml : INTEGER := arg1'length + arg2'length;
VARIABLE lt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE prod : STD_LOGIC_VECTOR(1 TO ml) := (OTHERS=>'0');
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN rt'reverse_range LOOP
IF rt(i) = '1' THEN
prod := prod + lt;
END IF;
lt := shift(lt);
END LOOP;
RETURN prod;
END "*";
FUNCTION "*" (arg1, arg2:UNSIGNED) RETURN UNSIGNED IS
VARIABLE ml : INTEGER := arg1'length + arg2'length;
VARIABLE lt : UNSIGNED(1 TO ml);
VARIABLE rt : UNSIGNED(1 TO ml);
VARIABLE prod : UNSIGNED(1 TO ml) := (OTHERS=>'0');
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN rt'reverse_range LOOP
IF rt(i) = '1' THEN
prod := prod + lt;
END IF;
lt := shift(lt);
END LOOP;
RETURN prod;
END "*";
--//// Sign Extend ////
--
-- Function sxt
--
FUNCTION sxt( q : SIGNED; i : INTEGER ) RETURN SIGNED IS
VARIABLE qs : SIGNED (1 TO i);
VARIABLE qt : SIGNED (1 TO q'length);
BEGIN
qt := q;
IF i < q'length THEN
qs := qt( (q'length-i+1) TO qt'right);
ELSIF i > q'length THEN
qs := (OTHERS=>q(q'left));
qs := qs(1 TO (i-q'length)) & qt;
ELSE
qs := qt;
END IF;
RETURN qs;
END;
FUNCTION "*" (arg1, arg2:SIGNED) RETURN SIGNED IS
VARIABLE ml : INTEGER := arg1'length + arg2'length;
VARIABLE lt : SIGNED(1 TO ml);
VARIABLE rt : SIGNED(1 TO ml);
VARIABLE prod : SIGNED(1 TO ml) := (OTHERS=>'0');
BEGIN
assert arg1'length > 1 AND arg2'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := sxt( arg1, ml );
rt := sxt( arg2, ml );
FOR i IN rt'reverse_range LOOP
IF rt(i) = '1' THEN
prod := prod + lt;
END IF;
lt := shift(lt);
END LOOP;
RETURN prod;
END "*";
FUNCTION rshift( v : STD_ULOGIC_VECTOR ) RETURN STD_ULOGIC_VECTOR IS
VARIABLE v1 : STD_ULOGIC_VECTOR( v'range );
BEGIN
FOR i IN v'left TO v'right-1 LOOP
v1(i+1) := v(i);
END LOOP;
v1(v1'left) := '0';
RETURN v1;
END rshift;
FUNCTION hasx( v : STD_ULOGIC_VECTOR ) RETURN BOOLEAN IS
BEGIN
FOR i IN v'range LOOP
IF v(i) = '0' OR v(i) = '1' OR v(i) = 'L' OR v(i) = 'H'THEN
NULL;
ELSE
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END hasx;
FUNCTION rshift( v : STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR IS
VARIABLE v1 : STD_LOGIC_VECTOR( v'range );
BEGIN
FOR i IN v'left TO v'right-1 LOOP
v1(i+1) := v(i);
END LOOP;
v1(v1'left) := '0';
RETURN v1;
END rshift;
FUNCTION hasx( v : STD_LOGIC_VECTOR ) RETURN BOOLEAN IS
BEGIN
FOR i IN v'range LOOP
IF v(i) = '0' OR v(i) = '1' OR v(i) = 'L' OR v(i) = 'H'THEN
NULL;
ELSE
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END hasx;
FUNCTION rshift( v : UNSIGNED ) RETURN UNSIGNED IS
VARIABLE v1 : UNSIGNED( v'range );
BEGIN
FOR i IN v'left TO v'right-1 LOOP
v1(i+1) := v(i);
END LOOP;
v1(v1'left) := '0';
RETURN v1;
END rshift;
FUNCTION hasx( v : UNSIGNED ) RETURN BOOLEAN IS
BEGIN
FOR i IN v'range LOOP
IF v(i) = '0' OR v(i) = '1' OR v(i) = 'L' OR v(i) = 'H'THEN
NULL;
ELSE
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END hasx;
FUNCTION rshift( v : SIGNED ) RETURN SIGNED IS
VARIABLE v1 : SIGNED( v'range );
BEGIN
FOR i IN v'left TO v'right-1 LOOP
v1(i+1) := v(i);
END LOOP;
v1(v1'left) := '0';
RETURN v1;
END rshift;
FUNCTION "/" (l, r :STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_ULOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_ULOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN quote'range LOOP
quote(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
n := (OTHERS=>'0');
n(n'right) := '1';
WHILE rt <= lt LOOP
rt := shift(rt);
n := shift(n);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
n := rshift(n);
tmp := tmp + n;
END LOOP;
END IF;
quote := tmp(2 TO ml+1);
RETURN quote;
END "/";
FUNCTION "/" (l, r :STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_LOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_LOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN quote'range LOOP
quote(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
n := (OTHERS=>'0');
n(n'right) := '1';
WHILE rt <= lt LOOP
rt := shift(rt);
n := shift(n);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
n := rshift(n);
tmp := tmp + n;
END LOOP;
END IF;
quote := tmp(2 TO ml+1);
RETURN quote;
END "/";
FUNCTION "/" (l, r :UNSIGNED) RETURN UNSIGNED IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : UNSIGNED(0 TO ml+1);
VARIABLE rt : UNSIGNED(0 TO ml+1);
VARIABLE quote : UNSIGNED(1 TO ml);
VARIABLE tmp : UNSIGNED(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : UNSIGNED(0 TO ml+1) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN quote'range LOOP
quote(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
n := (OTHERS=>'0');
n(n'right) := '1';
WHILE rt <= lt LOOP
rt := shift(rt);
n := shift(n);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
n := rshift(n);
tmp := tmp + n;
END LOOP;
END IF;
quote := tmp(2 TO ml+1);
RETURN quote;
END "/";
FUNCTION "/" (l, r :SIGNED) RETURN SIGNED IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : SIGNED(0 TO ml+1);
VARIABLE rt : SIGNED(0 TO ml+1);
VARIABLE quote : SIGNED(1 TO ml);
VARIABLE tmp : SIGNED(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : SIGNED(0 TO ml+1) := (OTHERS=>'0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN quote'range LOOP
quote(i) := 'X';
END LOOP;
ELSE
lt := sxt( l, ml+2 );
WHILE lt >= r LOOP
rt := sxt( r, ml+2 );
n := (OTHERS=>'0');
n(n'right) := '1';
WHILE rt <= lt LOOP
rt := shift(rt);
n := shift(n);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
n := rshift(n);
tmp := tmp + n;
END LOOP;
END IF;
quote := tmp(2 TO ml+1);
RETURN quote;
END "/";
FUNCTION "MOD" (l, r :STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_ULOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_ULOGIC_VECTOR(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "MOD";
FUNCTION "MOD" (l, r :STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_LOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_LOGIC_VECTOR(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "MOD";
FUNCTION "MOD" (l, r :UNSIGNED) RETURN UNSIGNED IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : UNSIGNED(0 TO ml+1);
VARIABLE rt : UNSIGNED(0 TO ml+1);
VARIABLE quote : UNSIGNED(1 TO ml);
VARIABLE tmp : UNSIGNED(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : UNSIGNED(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "MOD";
FUNCTION "REM" (l, r :STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_ULOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_ULOGIC_VECTOR(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "REM";
FUNCTION "REM" (l, r :STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_LOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_LOGIC_VECTOR(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "REM";
FUNCTION "REM" (l, r :UNSIGNED) RETURN UNSIGNED IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : UNSIGNED(0 TO ml+1);
VARIABLE rt : UNSIGNED(0 TO ml+1);
VARIABLE quote : UNSIGNED(1 TO ml);
VARIABLE tmp : UNSIGNED(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : UNSIGNED(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "REM";
FUNCTION "**" (l, r :STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
VARIABLE return_vector : STD_ULOGIC_VECTOR(l'range) := (OTHERS=>'0');
VARIABLE tmp : STD_ULOGIC_VECTOR(1 TO (2 * l'length)) := (OTHERS=>'0');
CONSTANT lsh_l : INTEGER := l'length+1;
CONSTANT lsh_r : INTEGER := 2 * l'length;
VARIABLE pow : INTEGER;
BEGIN
IF (hasx(l) OR hasx(r)) THEN
FOR i IN return_vector'range LOOP
return_vector(i) := 'X';
END LOOP;
ELSE
pow := to_integer( r, 0 );
tmp( tmp'right ) := '1';
FOR i IN 1 TO pow LOOP
tmp := tmp(lsh_l TO lsh_r) * l;
END LOOP;
return_vector := tmp(lsh_l TO lsh_r);
END IF;
RETURN return_vector;
END "**";
FUNCTION "**" (l, r :STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
VARIABLE return_vector : STD_LOGIC_VECTOR(l'range) := (OTHERS=>'0');
VARIABLE tmp : STD_LOGIC_VECTOR(1 TO (2 * l'length)) := (OTHERS=>'0');
CONSTANT lsh_l : INTEGER := l'length+1;
CONSTANT lsh_r : INTEGER := 2 * l'length;
VARIABLE pow : INTEGER;
BEGIN
IF (hasx(l) OR hasx(r)) THEN
FOR i IN return_vector'range LOOP
return_vector(i) := 'X';
END LOOP;
ELSE
pow := to_integer( r, 0 );
tmp( tmp'right ) := '1';
FOR i IN 1 TO pow LOOP
tmp := tmp(lsh_l TO lsh_r) * l;
END LOOP;
return_vector := tmp(lsh_l TO lsh_r);
END IF;
RETURN return_vector;
END "**";
FUNCTION "**" (l, r :UNSIGNED) RETURN UNSIGNED IS
VARIABLE return_vector : UNSIGNED(l'range) := (OTHERS=>'0');
VARIABLE tmp : UNSIGNED(1 TO (2 * l'length)) := (OTHERS=>'0');
CONSTANT lsh_l : INTEGER := l'length+1;
CONSTANT lsh_r : INTEGER := 2 * l'length;
VARIABLE pow : INTEGER;
BEGIN
IF (hasx(l) OR hasx(r)) THEN
FOR i IN return_vector'range LOOP
return_vector(i) := 'X';
END LOOP;
ELSE
pow := to_integer( r, 0 );
tmp( tmp'right ) := '1';
FOR i IN 1 TO pow LOOP
tmp := tmp(lsh_l TO lsh_r) * l;
END LOOP;
return_vector := tmp(lsh_l TO lsh_r);
END IF;
RETURN return_vector;
END "**";
--
-- Absolute Value Functions
--
FUNCTION "abs" (arg1:SIGNED) RETURN SIGNED IS
constant len : integer := arg1'length;
VARIABLE answer, tmp : SIGNED( len-1 downto 0 ) := (others=>'0');
VARIABLE index : integer := len;
BEGIN
assert arg1'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
IF hasx(arg1) THEN
answer := (OTHERS => 'X');
ELSIF (arg1(arg1'left) = '0' OR arg1(arg1'left) = 'L') THEN
answer := arg1;
ELSE
tmp := arg1;
lp1 : FOR i IN answer'REVERSE_RANGE LOOP
IF (tmp(i) = '1' OR tmp(i) = 'H') THEN
index := i+1;
answer(i downto 0) := tmp(i downto 0);
exit;
END IF;
END LOOP lp1;
answer(len-1 downto index) := NOT tmp(len-1 downto index);
end if;
RETURN (answer);
END ;
--
-- Shift Left (arithmetic) Functions
--
FUNCTION "sla" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_ulogic_vector(1 to len) := (others => arg1(arg1'right));
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sla" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_logic_vector(1 to len) := (others => arg1(arg1'right));
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sla" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : UNSIGNED(1 to len) := (others => arg1(arg1'right));
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sla" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : SIGNED(1 to len) := (others => arg1(arg1'right));
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
--
-- Shift Right (arithmetics) Functions
--
FUNCTION "sra" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_ulogic_vector(1 to len) := (others => arg1(arg1'left));
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "sra" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_logic_vector(1 to len) := (others => arg1(arg1'left));
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "sra" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : UNSIGNED(1 to len) := (others => arg1(arg1'left));
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "sra" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : SIGNED(1 to len) := (others => arg1(arg1'left));
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
--
-- Shift Left (logical) Functions
--
FUNCTION "sll" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_ulogic_vector(1 to len) := (others =>'0');
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sll" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_logic_vector(1 to len) := (others =>'0');
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sll" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : UNSIGNED(1 to len) := (others =>'0');
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sll" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : SIGNED(1 to len) := (others =>'0');
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
--
-- Shift Right (logical) Functions
--
FUNCTION "srl" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_ulogic_vector(1 to len) := (others => '0');
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "srl" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_logic_vector(1 to len) := (others => '0');
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "srl" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : UNSIGNED(1 to len) := (others => '0');
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "srl" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : SIGNED(1 to len) := (others => '0');
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
--
-- Rotate Left (Logical) Functions
--
FUNCTION "rol" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(marg2+1 to len) & ans(1 to marg2));
END IF;
END ;
FUNCTION "rol" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(marg2+1 to len) & ans(1 to marg2));
END IF;
END ;
FUNCTION "rol" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(marg2+1 to len) & ans(1 to marg2));
END IF;
END ;
FUNCTION "rol" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(marg2+1 to len) & ans(1 to marg2));
END IF;
END ;
--
-- Rotate Right (Logical) Functions
--
FUNCTION "ror" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(len-marg2+1 to len) & ans(1 to len-marg2));
END IF;
END ;
FUNCTION "ror" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(len-marg2+1 to len) & ans(1 to len-marg2));
END IF;
END ;
FUNCTION "ror" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(len-marg2+1 to len) & ans(1 to len-marg2));
END IF;
END ;
FUNCTION "ror" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(len-marg2+1 to len) & ans(1 to len-marg2));
END IF;
END ;
--
-- Equal functions.
--
CONSTANT eq_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | 0 |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | L |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
FUNCTION eq ( l, r : STD_LOGIC ) RETURN BOOLEAN IS
BEGIN
RETURN eq_table( l, r );
END;
FUNCTION eq ( l,r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_ULOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_ULOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN FALSE;
END IF;
END LOOP;
RETURN TRUE;
END;
FUNCTION eq ( l,r : STD_LOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_LOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_LOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN FALSE;
END IF;
END LOOP;
RETURN TRUE;
END;
FUNCTION eq ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN FALSE;
END IF;
END LOOP;
RETURN TRUE;
END;
FUNCTION eq ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
RETURN (eq( lt, rt ));
END;
FUNCTION "=" ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN FALSE;
END IF;
END LOOP;
RETURN TRUE;
END;
FUNCTION "=" ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
RETURN (eq( lt, rt ));
END;
--
-- Not Equal function.
--
CONSTANT neq_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | 0 |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | L |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
FUNCTION ne ( l, r : STD_LOGIC ) RETURN BOOLEAN IS
BEGIN
RETURN neq_table( l, r );
END;
FUNCTION ne ( l,r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_ULOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_ULOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF ne( lt(i), rt(i) ) THEN
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION ne ( l,r : STD_LOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_LOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_LOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF ne( lt(i), rt(i) ) THEN
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION ne ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF ne( lt(i), rt(i) ) THEN
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION ne ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
RETURN (ne( lt, rt ));
END;
FUNCTION "/=" ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF ne( lt(i), rt(i) ) THEN
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION "/=" ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
RETURN (ne( lt, rt ));
END;
--
-- Less Than functions.
--
CONSTANT ltb_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | 0 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | L |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
FUNCTION lt ( l, r : STD_LOGIC ) RETURN BOOLEAN IS
BEGIN
RETURN ltb_table( l, r );
END;
FUNCTION lt ( l,r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE ltt : STD_ULOGIC_VECTOR ( 1 TO ml );
VARIABLE rtt : STD_ULOGIC_VECTOR ( 1 TO ml );
BEGIN
ltt := zxt( l, ml );
rtt := zxt( r, ml );
FOR i IN ltt'range LOOP
IF NOT eq( ltt(i), rtt(i) ) THEN
RETURN lt( ltt(i), rtt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION lt ( l,r : STD_LOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE ltt : STD_LOGIC_VECTOR ( 1 TO ml );
VARIABLE rtt : STD_LOGIC_VECTOR ( 1 TO ml );
BEGIN
ltt := zxt( l, ml );
rtt := zxt( r, ml );
FOR i IN ltt'range LOOP
IF NOT eq( ltt(i), rtt(i) ) THEN
RETURN lt( ltt(i), rtt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION lt ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE ltt : UNSIGNED ( 1 TO ml );
VARIABLE rtt : UNSIGNED ( 1 TO ml );
BEGIN
ltt := zxt( l, ml );
rtt := zxt( r, ml );
FOR i IN ltt'range LOOP
IF NOT eq( ltt(i), rtt(i) ) THEN
RETURN lt( ltt(i), rtt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION lt ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE ltt, rtt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
ltt := (OTHERS => l(l'left)) ;
ltt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rtt := (OTHERS => r(r'left)) ;
rtt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(ltt(ltt'left) = '1' AND rtt(rtt'left) = '0') THEN
RETURN(TRUE) ;
ELSIF(ltt(ltt'left) = '0' AND rtt(rtt'left) = '1') THEN
RETURN(FALSE) ;
ELSE
RETURN (lt( ltt, rtt ));
END IF ;
END;
FUNCTION "<" ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE ltt : UNSIGNED ( 1 TO ml );
VARIABLE rtt : UNSIGNED ( 1 TO ml );
BEGIN
ltt := zxt( l, ml );
rtt := zxt( r, ml );
FOR i IN ltt'range LOOP
IF NOT eq( ltt(i), rtt(i) ) THEN
RETURN lt( ltt(i), rtt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION "<" ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE ltt, rtt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
ltt := (OTHERS => l(l'left)) ;
ltt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rtt := (OTHERS => r(r'left)) ;
rtt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(ltt(ltt'left) = '1' AND rtt(rtt'left) = '0') THEN
RETURN(TRUE) ;
ELSIF(ltt(ltt'left) = '0' AND rtt(rtt'left) = '1') THEN
RETURN(FALSE) ;
ELSE
RETURN (lt( ltt, rtt ));
END IF ;
END;
--
-- Greater Than functions.
--
CONSTANT gtb_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | 0 |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | L |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
FUNCTION gt ( l, r : std_logic ) RETURN BOOLEAN IS
BEGIN
RETURN gtb_table( l, r );
END ;
FUNCTION gt ( l,r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_ULOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_ULOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN gt( lt(i), rt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION gt ( l,r : STD_LOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_LOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_LOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN gt( lt(i), rt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION gt ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN gt( lt(i), rt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION gt ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(FALSE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(TRUE) ;
ELSE
RETURN (gt( lt, rt ));
END IF ;
END;
FUNCTION ">" ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN gt( lt(i), rt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION ">" ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(FALSE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(TRUE) ;
ELSE
RETURN (gt( lt, rt ));
END IF ;
END;
--
-- Less Than or Equal to functions.
--
CONSTANT leb_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | X |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE ), -- | 0 |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | W |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE ), -- | L |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ) -- | D |
);
FUNCTION le ( l, r : std_logic ) RETURN BOOLEAN IS
BEGIN
RETURN leb_table( l, r );
END ;
TYPE std_ulogic_fuzzy_state IS ('U', 'X', 'T', 'F', 'N');
TYPE std_ulogic_fuzzy_state_table IS ARRAY ( std_ulogic, std_ulogic ) OF std_ulogic_fuzzy_state;
CONSTANT le_fuzzy_table : std_ulogic_fuzzy_state_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'N', 'U', 'U', 'U', 'N', 'U' ), -- | U |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | X |
( 'N', 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N' ), -- | 0 |
( 'U', 'X', 'F', 'N', 'X', 'X', 'F', 'N', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | Z |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | W |
( 'N', 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N' ), -- | L |
( 'U', 'X', 'F', 'N', 'X', 'X', 'F', 'N', 'X' ), -- | H |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ) -- | D |
);
FUNCTION le ( L,R : std_ulogic_vector ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : std_ulogic_vector ( 1 to ml );
VARIABLE rt : std_ulogic_vector ( 1 to ml );
VARIABLE res : std_ulogic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := le_fuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
TYPE std_logic_fuzzy_state IS ('U', 'X', 'T', 'F', 'N');
TYPE std_logic_fuzzy_state_table IS ARRAY ( std_logic, std_logic ) OF std_logic_fuzzy_state;
CONSTANT le_lfuzzy_table : std_logic_fuzzy_state_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'N', 'U', 'U', 'U', 'N', 'U' ), -- | U |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | X |
( 'N', 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N' ), -- | 0 |
( 'U', 'X', 'F', 'N', 'X', 'X', 'F', 'N', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | Z |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | W |
( 'N', 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N' ), -- | L |
( 'U', 'X', 'F', 'N', 'X', 'X', 'F', 'N', 'X' ), -- | H |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ) -- | D |
);
FUNCTION le ( L,R : std_logic_vector ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : std_logic_vector ( 1 to ml );
VARIABLE rt : std_logic_vector ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := le_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION le ( L,R : UNSIGNED ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := le_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION le (l, r:SIGNED) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(TRUE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(FALSE) ;
ELSE
RETURN (le( lt, rt ));
END IF ;
END;
FUNCTION "<=" ( L,R : UNSIGNED ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := le_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION "<=" (l, r:SIGNED) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(TRUE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(FALSE) ;
ELSE
RETURN (le( lt, rt ));
END IF ;
END;
--
-- Greater Than or Equal to functions.
--
CONSTANT geb_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | 0 |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE ), -- | 1 |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | L |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE ), -- | H |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ) -- | D |
);
FUNCTION ge ( l, r : std_logic ) RETURN BOOLEAN IS
BEGIN
RETURN geb_table( l, r );
END ;
CONSTANT ge_fuzzy_table : std_ulogic_fuzzy_state_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'N', 'U', 'U', 'U', 'N', 'U', 'U' ), -- | U |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | X |
( 'U', 'X', 'N', 'F', 'X', 'X', 'N', 'F', 'X' ), -- | 0 |
( 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N', 'N' ), -- | 1 |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | Z |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | W |
( 'U', 'X', 'N', 'F', 'X', 'X', 'N', 'F', 'X' ), -- | L |
( 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N', 'N' ), -- | H |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ) -- | D |
);
FUNCTION ge ( L,R : std_ulogic_vector ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : std_ulogic_vector ( 1 to ml );
VARIABLE rt : std_ulogic_vector ( 1 to ml );
VARIABLE res : std_ulogic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := ge_fuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
CONSTANT ge_lfuzzy_table : std_logic_fuzzy_state_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'N', 'U', 'U', 'U', 'N', 'U', 'U' ), -- | U |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | X |
( 'U', 'X', 'N', 'F', 'X', 'X', 'N', 'F', 'X' ), -- | 0 |
( 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N', 'N' ), -- | 1 |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | Z |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | W |
( 'U', 'X', 'N', 'F', 'X', 'X', 'N', 'F', 'X' ), -- | L |
( 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N', 'N' ), -- | H |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ) -- | D |
);
FUNCTION ge ( L,R : std_logic_vector ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : std_logic_vector ( 1 to ml );
VARIABLE rt : std_logic_vector ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := ge_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION ge ( L,R : UNSIGNED ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := ge_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION ge ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(FALSE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(TRUE) ;
ELSE
RETURN (ge( lt, rt ));
END IF ;
END;
FUNCTION ">=" ( L,R : UNSIGNED ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := ge_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION ">=" ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(FALSE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(TRUE) ;
ELSE
RETURN (ge( lt, rt ));
END IF ;
END;
-------------------------------------------------------------------------------
-- Logical Operations
-------------------------------------------------------------------------------
-- truth table for "and" function
CONSTANT and_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U' ), -- | U |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | 0 |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | Z |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | W |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | H |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ) -- | D |
);
-- truth table for "or" function
CONSTANT or_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', '1', 'U', 'U', 'U', '1', 'U' ), -- | U |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | 1 |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | Z |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | H |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ) -- | D |
);
-- truth table for "xor" function
CONSTANT xor_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | D |
);
-- truth table for "not" function
CONSTANT not_table: stdlogic_1D :=
-- -------------------------------------------------
-- | U X 0 1 Z W L H D |
-- -------------------------------------------------
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' );
FUNCTION "and" ( arg1,arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := and_table( lt(i), rt(i) );
END LOOP;
RETURN res;
end "and";
FUNCTION "nand" ( arg1,arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := not_table( and_table( lt(i), rt(i) ) );
END LOOP;
RETURN res;
end "nand";
FUNCTION "or" ( arg1,arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := or_table( lt(i), rt(i) );
END LOOP;
RETURN res;
end "or";
FUNCTION "nor" ( arg1,arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := not_table( or_table( lt(i), rt(i) ) );
END LOOP;
RETURN res;
end "nor";
FUNCTION "xor" ( arg1, arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := xor_table( lt(i), rt(i) );
END LOOP;
RETURN res;
end "xor";
FUNCTION "not" ( arg1 : UNSIGNED ) RETURN UNSIGNED IS
VARIABLE result : UNSIGNED ( arg1'RANGE ) := (Others => 'X');
begin
for i in result'range loop
result(i) := not_table( arg1(i) );
end loop;
return result;
end "not";
FUNCTION "and" ( arg1,arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a and b);
RETURN (answer);
end "and";
FUNCTION "nand" ( arg1,arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a nand b);
RETURN (answer);
end "nand";
FUNCTION "or" ( arg1,arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a or b);
RETURN (answer);
end "or";
FUNCTION "nor" ( arg1,arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a nor b);
RETURN (answer);
end "nor";
FUNCTION "xor" ( arg1, arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a xor b);
RETURN (answer);
end "xor";
FUNCTION "not" ( arg1 : SIGNED ) RETURN SIGNED IS
VARIABLE result : SIGNED ( arg1'RANGE ) := (Others => 'X');
begin
for i in result'range loop
result(i) := not_table( arg1(i) );
end loop;
return result;
end "not";
FUNCTION "xnor" ( arg1, arg2 : std_ulogic_vector ) RETURN std_ulogic_vector IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : std_ulogic_vector ( 1 to ml );
VARIABLE rt : std_ulogic_vector ( 1 to ml );
VARIABLE res : std_ulogic_vector ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := not_table( xor_table( lt(i), rt(i) ) );
END LOOP;
RETURN res;
end "xnor";
FUNCTION "xnor" ( arg1, arg2 : std_logic_vector ) RETURN std_logic_vector IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : std_logic_vector ( 1 to ml );
VARIABLE rt : std_logic_vector ( 1 to ml );
VARIABLE res : std_logic_vector ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := not_table( xor_table( lt(i), rt(i) ) );
END LOOP;
RETURN res;
end "xnor";
FUNCTION "xnor" ( arg1, arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := not_table( xor_table( lt(i), rt(i) ) );
END LOOP;
RETURN res;
end "xnor";
FUNCTION "xnor" ( arg1, arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a xnor b);
RETURN (answer);
end "xnor";
END ;
| gpl-3.0 | 07a3ec8faa9f17006fb8959c9f7e2545 | 0.452067 | 3.506812 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00184.vhd | 1 | 48,978 | -- NEED RESULT: ARCH00184.P1: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00184.P2: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00184.P3: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00184.P4: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00184.P5: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00184.P6: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00184: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Old transactions were removed on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Old transactions were removed on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Old transactions were removed on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Old transactions were removed on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Old transactions were removed on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Old transactions were removed on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: ARCH00184: Inertial semantics check on a signal asg with slice name prefixed by an selected name on LHS failed
-- NEED RESULT: P6: Inertial transactions entirely completed failed
-- NEED RESULT: P5: Inertial transactions entirely completed failed
-- NEED RESULT: P4: Inertial transactions entirely completed failed
-- NEED RESULT: P3: Inertial transactions entirely completed failed
-- NEED RESULT: P2: Inertial transactions entirely completed failed
-- NEED RESULT: P1: Inertial transactions entirely completed failed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00184
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00184
-- PKG00184/BODY
-- ENT00184(ARCH00184)
-- ENT00184_Test_Bench(ARCH00184_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
package PKG00184 is
type r_st_arr1_vector is record
f1 : integer ;
f2 : st_arr1_vector ;
end record ;
function c_r_st_arr1_vector_1 return r_st_arr1_vector ;
-- (c_integer_1, c_st_arr1_vector_1) ;
function c_r_st_arr1_vector_2 return r_st_arr1_vector ;
-- (c_integer_2, c_st_arr1_vector_2) ;
--
type r_st_arr2_vector is record
f1 : integer ;
f2 : st_arr2_vector ;
end record ;
function c_r_st_arr2_vector_1 return r_st_arr2_vector ;
-- (c_integer_1, c_st_arr2_vector_1) ;
function c_r_st_arr2_vector_2 return r_st_arr2_vector ;
-- (c_integer_2, c_st_arr2_vector_2) ;
--
type r_st_arr3_vector is record
f1 : integer ;
f2 : st_arr3_vector ;
end record ;
function c_r_st_arr3_vector_1 return r_st_arr3_vector ;
-- (c_integer_1, c_st_arr3_vector_1) ;
function c_r_st_arr3_vector_2 return r_st_arr3_vector ;
-- (c_integer_2, c_st_arr3_vector_2) ;
--
type r_st_rec1_vector is record
f1 : integer ;
f2 : st_rec1_vector ;
end record ;
function c_r_st_rec1_vector_1 return r_st_rec1_vector ;
-- (c_integer_1, c_st_rec1_vector_1) ;
function c_r_st_rec1_vector_2 return r_st_rec1_vector ;
-- (c_integer_2, c_st_rec1_vector_2) ;
--
type r_st_rec2_vector is record
f1 : integer ;
f2 : st_rec2_vector ;
end record ;
function c_r_st_rec2_vector_1 return r_st_rec2_vector ;
-- (c_integer_1, c_st_rec2_vector_1) ;
function c_r_st_rec2_vector_2 return r_st_rec2_vector ;
-- (c_integer_2, c_st_rec2_vector_2) ;
--
type r_st_rec3_vector is record
f1 : integer ;
f2 : st_rec3_vector ;
end record ;
function c_r_st_rec3_vector_1 return r_st_rec3_vector ;
-- (c_integer_1, c_st_rec3_vector_1) ;
function c_r_st_rec3_vector_2 return r_st_rec3_vector ;
-- (c_integer_2, c_st_rec3_vector_2) ;
--
--
end PKG00184 ;
--
package body PKG00184 is
function c_r_st_arr1_vector_1 return r_st_arr1_vector
is begin
return (c_integer_1, c_st_arr1_vector_1) ;
end c_r_st_arr1_vector_1 ;
--
function c_r_st_arr1_vector_2 return r_st_arr1_vector
is begin
return (c_integer_2, c_st_arr1_vector_2) ;
end c_r_st_arr1_vector_2 ;
--
--
function c_r_st_arr2_vector_1 return r_st_arr2_vector
is begin
return (c_integer_1, c_st_arr2_vector_1) ;
end c_r_st_arr2_vector_1 ;
--
function c_r_st_arr2_vector_2 return r_st_arr2_vector
is begin
return (c_integer_2, c_st_arr2_vector_2) ;
end c_r_st_arr2_vector_2 ;
--
--
function c_r_st_arr3_vector_1 return r_st_arr3_vector
is begin
return (c_integer_1, c_st_arr3_vector_1) ;
end c_r_st_arr3_vector_1 ;
--
function c_r_st_arr3_vector_2 return r_st_arr3_vector
is begin
return (c_integer_2, c_st_arr3_vector_2) ;
end c_r_st_arr3_vector_2 ;
--
--
function c_r_st_rec1_vector_1 return r_st_rec1_vector
is begin
return (c_integer_1, c_st_rec1_vector_1) ;
end c_r_st_rec1_vector_1 ;
--
function c_r_st_rec1_vector_2 return r_st_rec1_vector
is begin
return (c_integer_2, c_st_rec1_vector_2) ;
end c_r_st_rec1_vector_2 ;
--
--
function c_r_st_rec2_vector_1 return r_st_rec2_vector
is begin
return (c_integer_1, c_st_rec2_vector_1) ;
end c_r_st_rec2_vector_1 ;
--
function c_r_st_rec2_vector_2 return r_st_rec2_vector
is begin
return (c_integer_2, c_st_rec2_vector_2) ;
end c_r_st_rec2_vector_2 ;
--
--
function c_r_st_rec3_vector_1 return r_st_rec3_vector
is begin
return (c_integer_1, c_st_rec3_vector_1) ;
end c_r_st_rec3_vector_1 ;
--
function c_r_st_rec3_vector_2 return r_st_rec3_vector
is begin
return (c_integer_2, c_st_rec3_vector_2) ;
end c_r_st_rec3_vector_2 ;
--
--
--
end PKG00184 ;
--
use WORK.STANDARD_TYPES.all ;
use WORK.PKG00184.all ;
entity ENT00184 is
port (
s_r_st_arr1_vector : inout r_st_arr1_vector
; s_r_st_arr2_vector : inout r_st_arr2_vector
; s_r_st_arr3_vector : inout r_st_arr3_vector
; s_r_st_rec1_vector : inout r_st_rec1_vector
; s_r_st_rec2_vector : inout r_st_rec2_vector
; s_r_st_rec3_vector : inout r_st_rec3_vector
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_r_st_arr1_vector : chk_sig_type := -1 ;
signal chk_r_st_arr2_vector : chk_sig_type := -1 ;
signal chk_r_st_arr3_vector : chk_sig_type := -1 ;
signal chk_r_st_rec1_vector : chk_sig_type := -1 ;
signal chk_r_st_rec2_vector : chk_sig_type := -1 ;
signal chk_r_st_rec3_vector : chk_sig_type := -1 ;
--
--
procedure Proc1 (
signal s_r_st_arr1_vector : inout r_st_arr1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_r_st_arr1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00184.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00184" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_arr1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
procedure Proc2 (
signal s_r_st_arr2_vector : inout r_st_arr2_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_r_st_arr2_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00184.P2" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00184" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_arr2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc2 ;
--
procedure Proc3 (
signal s_r_st_arr3_vector : inout r_st_arr3_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_r_st_arr3_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00184.P3" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00184" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_arr3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc3 ;
--
procedure Proc4 (
signal s_r_st_rec1_vector : inout r_st_rec1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_r_st_rec1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00184.P4" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00184" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc4 ;
--
procedure Proc5 (
signal s_r_st_rec2_vector : inout r_st_rec2_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_r_st_rec2_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00184.P5" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00184" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc5 ;
--
procedure Proc6 (
signal s_r_st_rec3_vector : inout r_st_rec3_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_r_st_rec3_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00184.P6" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00184" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00184" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc6 ;
--
--
end ENT00184 ;
--
architecture ARCH00184 of ENT00184 is
begin
P1 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc1 (
s_r_st_arr1_vector,
counter,
correct,
savtime,
chk_r_st_arr1_vector
) ;
wait until (not s_r_st_arr1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_r_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_r_st_arr1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
P2 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc2 (
s_r_st_arr2_vector,
counter,
correct,
savtime,
chk_r_st_arr2_vector
) ;
wait until (not s_r_st_arr2_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P2 ;
--
PGEN_CHKP_2 :
process ( chk_r_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions entirely completed",
chk_r_st_arr2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
P3 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc3 (
s_r_st_arr3_vector,
counter,
correct,
savtime,
chk_r_st_arr3_vector
) ;
wait until (not s_r_st_arr3_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P3 ;
--
PGEN_CHKP_3 :
process ( chk_r_st_arr3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions entirely completed",
chk_r_st_arr3_vector = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
P4 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc4 (
s_r_st_rec1_vector,
counter,
correct,
savtime,
chk_r_st_rec1_vector
) ;
wait until (not s_r_st_rec1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P4 ;
--
PGEN_CHKP_4 :
process ( chk_r_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Inertial transactions entirely completed",
chk_r_st_rec1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
--
P5 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc5 (
s_r_st_rec2_vector,
counter,
correct,
savtime,
chk_r_st_rec2_vector
) ;
wait until (not s_r_st_rec2_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P5 ;
--
PGEN_CHKP_5 :
process ( chk_r_st_rec2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Inertial transactions entirely completed",
chk_r_st_rec2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
--
P6 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc6 (
s_r_st_rec3_vector,
counter,
correct,
savtime,
chk_r_st_rec3_vector
) ;
wait until (not s_r_st_rec3_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P6 ;
--
PGEN_CHKP_6 :
process ( chk_r_st_rec3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Inertial transactions entirely completed",
chk_r_st_rec3_vector = 8 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
--
--
end ARCH00184 ;
--
use WORK.STANDARD_TYPES.all ;
use WORK.PKG00184.all ;
entity ENT00184_Test_Bench is
signal s_r_st_arr1_vector : r_st_arr1_vector
:= c_r_st_arr1_vector_1 ;
signal s_r_st_arr2_vector : r_st_arr2_vector
:= c_r_st_arr2_vector_1 ;
signal s_r_st_arr3_vector : r_st_arr3_vector
:= c_r_st_arr3_vector_1 ;
signal s_r_st_rec1_vector : r_st_rec1_vector
:= c_r_st_rec1_vector_1 ;
signal s_r_st_rec2_vector : r_st_rec2_vector
:= c_r_st_rec2_vector_1 ;
signal s_r_st_rec3_vector : r_st_rec3_vector
:= c_r_st_rec3_vector_1 ;
--
end ENT00184_Test_Bench ;
--
architecture ARCH00184_Test_Bench of ENT00184_Test_Bench is
begin
L1:
block
component UUT
port (
s_r_st_arr1_vector : inout r_st_arr1_vector
; s_r_st_arr2_vector : inout r_st_arr2_vector
; s_r_st_arr3_vector : inout r_st_arr3_vector
; s_r_st_rec1_vector : inout r_st_rec1_vector
; s_r_st_rec2_vector : inout r_st_rec2_vector
; s_r_st_rec3_vector : inout r_st_rec3_vector
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00184 ( ARCH00184 ) ;
begin
CIS1 : UUT
port map (
s_r_st_arr1_vector
, s_r_st_arr2_vector
, s_r_st_arr3_vector
, s_r_st_rec1_vector
, s_r_st_rec2_vector
, s_r_st_rec3_vector
) ;
end block L1 ;
end ARCH00184_Test_Bench ;
| gpl-3.0 | 4b78bc5c8c6c1ac8cd7139ed296d9913 | 0.525072 | 3.33229 | false | false | false | false |
dcliche/mdsynth | rtl/test_benches/channel_tb/src/pitch_to_freq.vhd | 1 | 3,731 | -- MDSynth Sound Chip
--
-- Copyright (c) 2012, Meldora Inc.
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification, are permitted provided that the
-- following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice, this list of conditions and the
-- following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the
-- following disclaimer in the documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
-- USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- MIDI-compatible pitch to NCO-compatible frequency with phase delta and octave
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity pitch_to_freq is
port ( pitch: in unsigned(6 downto 0); -- 60 = C4
phase_delta: out unsigned(11 downto 0);
octave: out unsigned(3 downto 0));
end pitch_to_freq;
architecture pitch_to_freq_arch of pitch_to_freq is
component div_by_12 is
port ( numerator : in unsigned(6 downto 0);
quotient : out unsigned(3 downto 0);
remain : out unsigned(3 downto 0));
end component;
signal note: unsigned(3 downto 0);
signal toggle: std_logic := '0';
begin
div0: div_by_12 port map (numerator => pitch, quotient => octave, remain => note);
-- pitch 69 (A4) will give the following: octave=5, note=9
-- The desired frequencies for octave 5 are the following:
-- note freq (Hz)
-- 0 261.63 (C4)
-- 1 277.18
-- 2 293.66
-- 3 311.13
-- 4 329.63
-- 5 349.23
-- 6 369.99
-- 7 392.00
-- 8 415.30
-- 9 440.00 (A4)
-- 10 466.16
-- 11 493.88
-- The frequency given to NCO is the following:
-- freq = (50E6 * (phase_delta * 2^octave)) / 2^32
-- phase_delta = freq * 2^32 / (50E6 * 2^octave)
process (note)
begin
case note is
when "0000" => phase_delta <= to_unsigned(702, 12); -- C4
when "0001" => phase_delta <= to_unsigned(744, 12); -- C4#
when "0010" => phase_delta <= to_unsigned(788, 12); -- D4
when "0011" => phase_delta <= to_unsigned(835, 12); -- D4#
when "0100" => phase_delta <= to_unsigned(885, 12); -- E4
when "0101" => phase_delta <= to_unsigned(937, 12); -- F4
when "0110" => phase_delta <= to_unsigned(993, 12); -- F4#
when "0111" => phase_delta <= to_unsigned(1052, 12); -- G4
when "1000" => phase_delta <= to_unsigned(1115, 12); -- G4#
when "1001" => phase_delta <= to_unsigned(1181, 12); -- A4
when "1010" => phase_delta <= to_unsigned(1251, 12); -- A4#
when "1011" => phase_delta <= to_unsigned(1326, 12); -- B4
when others => phase_delta <= to_unsigned(0, 12); -- Should never happen
end case;
end process;
end pitch_to_freq_arch;
| gpl-3.0 | c6d49217284474bdc82edffb8e84eeb3 | 0.635486 | 3.457831 | false | false | false | false |
jairov4/accel-oil | impl/impl_test_pcie/simulation/behavioral/system_ac0_mb_bridge_wrapper.vhd | 1 | 10,910 | -------------------------------------------------------------------------------
-- system_ac0_mb_bridge_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plbv46_plbv46_bridge_v1_04_a;
use plbv46_plbv46_bridge_v1_04_a.all;
entity system_ac0_mb_bridge_wrapper is
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
IP2INTC_Irpt : out std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 3);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 7);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 63);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 63);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 14);
Sl_MWrErr : out std_logic_vector(0 to 14);
Sl_MRdErr : out std_logic_vector(0 to 14);
Sl_MIRQ : out std_logic_vector(0 to 14);
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to 7);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_ABus : out std_logic_vector(0 to 31);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to 63);
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to 63);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
PLB_MBusy : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdWdAddr : in std_logic_vector(0 to 3)
);
end system_ac0_mb_bridge_wrapper;
architecture STRUCTURE of system_ac0_mb_bridge_wrapper is
component plbv46_plbv46_bridge is
generic (
C_NUM_ADDR_RNG : INTEGER;
C_BRIDGE_BASEADDR : std_logic_vector;
C_BRIDGE_HIGHADDR : std_logic_vector;
C_RNG0_BASEADDR : std_logic_vector;
C_RNG0_HIGHADDR : std_logic_vector;
C_RNG1_BASEADDR : std_logic_vector;
C_RNG1_HIGHADDR : std_logic_vector;
C_RNG2_BASEADDR : std_logic_vector;
C_RNG2_HIGHADDR : std_logic_vector;
C_RNG3_BASEADDR : std_logic_vector;
C_RNG3_HIGHADDR : std_logic_vector;
C_SPLB_P2P : INTEGER;
C_SPLB_MID_WIDTH : INTEGER;
C_SPLB_NUM_MASTERS : INTEGER;
C_SPLB_SMALLEST_MASTER : INTEGER;
C_SPLB_BIGGEST_MASTER : INTEGER;
C_SPLB_AWIDTH : INTEGER;
C_SPLB_DWIDTH : INTEGER;
C_MPLB_AWIDTH : INTEGER;
C_MPLB_DWIDTH : INTEGER;
C_SPLB_NATIVE_DWIDTH : INTEGER;
C_MPLB_NATIVE_DWIDTH : INTEGER;
C_MPLB_SMALLEST_SLAVE : INTEGER;
C_BUS_CLOCK_RATIO : INTEGER;
C_PREFETCH_TIMEOUT : INTEGER;
C_FAMILY : STRING
);
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
IP2INTC_Irpt : out std_logic;
PLB_ABus : in std_logic_vector(0 to C_SPLB_AWIDTH-1);
PLB_UABus : in std_logic_vector(0 to C_SPLB_AWIDTH-1);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1));
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1));
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1));
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1));
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to ((C_MPLB_DWIDTH/8)-1));
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_ABus : out std_logic_vector(0 to C_MPLB_AWIDTH-1);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to (C_MPLB_DWIDTH-1));
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_MPLB_DWIDTH-1));
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to C_MPLB_AWIDTH-1);
PLB_MBusy : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdWdAddr : in std_logic_vector(0 to 3)
);
end component;
begin
ac0_mb_bridge : plbv46_plbv46_bridge
generic map (
C_NUM_ADDR_RNG => 1,
C_BRIDGE_BASEADDR => X"00000000",
C_BRIDGE_HIGHADDR => X"FFFFFFFF",
C_RNG0_BASEADDR => X"00000000",
C_RNG0_HIGHADDR => X"FFFFFFFF",
C_RNG1_BASEADDR => X"ffffffff",
C_RNG1_HIGHADDR => X"00000000",
C_RNG2_BASEADDR => X"ffffffff",
C_RNG2_HIGHADDR => X"00000000",
C_RNG3_BASEADDR => X"ffffffff",
C_RNG3_HIGHADDR => X"00000000",
C_SPLB_P2P => 0,
C_SPLB_MID_WIDTH => 4,
C_SPLB_NUM_MASTERS => 15,
C_SPLB_SMALLEST_MASTER => 64,
C_SPLB_BIGGEST_MASTER => 32,
C_SPLB_AWIDTH => 32,
C_SPLB_DWIDTH => 64,
C_MPLB_AWIDTH => 32,
C_MPLB_DWIDTH => 64,
C_SPLB_NATIVE_DWIDTH => 32,
C_MPLB_NATIVE_DWIDTH => 32,
C_MPLB_SMALLEST_SLAVE => 32,
C_BUS_CLOCK_RATIO => 1,
C_PREFETCH_TIMEOUT => 10,
C_FAMILY => "virtex5"
)
port map (
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
IP2INTC_Irpt => IP2INTC_Irpt,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
MPLB_Clk => MPLB_Clk,
MPLB_Rst => MPLB_Rst,
M_request => M_request,
M_priority => M_priority,
M_busLock => M_busLock,
M_RNW => M_RNW,
M_BE => M_BE,
M_MSize => M_MSize,
M_size => M_size,
M_type => M_type,
M_ABus => M_ABus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst,
M_wrDBus => M_wrDBus,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MSSize => PLB_MSSize,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MTimeout => PLB_MTimeout,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MWrBTerm => PLB_MWrBTerm,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_UABus => M_UABus,
PLB_MBusy => PLB_MBusy,
PLB_MIRQ => PLB_MIRQ,
PLB_MRdWdAddr => PLB_MRdWdAddr
);
end architecture STRUCTURE;
| lgpl-3.0 | b4fa72c42f9684a004b42e61c53cbede | 0.590009 | 3.16599 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00462.vhd | 1 | 3,077 | -------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00462
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.2.5 (1)
-- 7.2.5 (5)
-- 7.2.5 (6)
-- 7.2.5 (7)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00462(ARCH00462)
-- ENT00462_Test_Bench(ARCH00462_Test_Bench)
--
-- REVISION HISTORY:
--
-- 29-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES ;
use WORK.ARITHMETIC.ALL ;
entity ENT00462 is
generic (
i_int_1 : integer := c_int_1 ;
i_int_2 : integer := c_int_2 ;
i_t_int_1 : t_int := c_t_int_1 ;
i_t_int_2 : t_int := c_t_int_2 ;
i_st_int_1 : st_int := c_st_int_1 ;
i_st_int_2 : st_int := c_st_int_2
) ;
end ENT00462 ;
architecture ARCH00462 of ENT00462 is
constant c2_int_1 : integer :=
abs i_int_1 + abs i_int_2 ;
constant c2_t_int_1 : t_int :=
abs i_t_int_1 + abs i_t_int_2 ;
constant c2_st_int_1 : st_int :=
abs i_st_int_1 + abs i_st_int_2 + abs i_t_int_2 ;
begin
process
variable bool : boolean := true ;
variable cons_correct, gen_correct, dyn_correct : boolean := true ;
--
variable v_int_1, v2_int_1 : integer := i_int_1 ;
variable v_int_2, v2_int_2 : integer := i_int_2 ;
variable v_t_int_1, v2_t_int_1 : t_int := i_t_int_1 ;
variable v_t_int_2, v2_t_int_2 : t_int := i_t_int_2 ;
variable v_st_int_1, v2_st_int_1 : st_int := i_st_int_1 ;
variable v_st_int_2, v2_st_int_2 : st_int := i_st_int_2 ;
--
begin
-- static expression
case bool is
when (
abs c_int_1 + abs c_int_2 = 17 and
abs c_t_int_1 + abs c_t_int_2 = 503 and
abs c_st_int_1 + abs c_st_int_2 + abs c_t_int_2 = 408
) =>
null ;
when others =>
cons_correct := false ;
end case ;
-- generic expression
gen_correct := c2_int_1 = 17 and
c2_t_int_1 = 503 and
c2_st_int_1 = 408 ;
-- dynamic expression
v2_int_1 :=
abs v_int_1 + abs v_int_2 ;
v2_t_int_1 :=
abs v_t_int_1 + abs v_t_int_2 ;
v2_st_int_1 :=
abs v_st_int_1 + abs v_st_int_2 + abs v_t_int_2 ;
dyn_correct := v2_int_1 = 17 and
v2_t_int_1 = 503 and
v2_st_int_1 = 408 ;
STANDARD_TYPES.test_report ( "ARCH00462" ,
"abs predefined for integer types" ,
cons_correct and gen_correct and dyn_correct ) ;
wait ;
end process ;
end ARCH00462 ;
entity ENT00462_Test_Bench is
end ENT00462_Test_Bench ;
architecture ARCH00462_Test_Bench of ENT00462_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00462 ( ARCH00462 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00462_Test_Bench ;
| gpl-3.0 | ef6b5be312d407875ad8e95fa4233016 | 0.500812 | 2.828125 | false | true | false | false |
TWW12/lzw | ip_repo/axi_compression_1.0/src/output_fifo/output_fifo_sim_netlist.vhdl | 2 | 164,294 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Mar 31 09:06:21 2017
-- Host : Shaun running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/Shaun/Desktop/ip_repo/axi_compression_1.0/src/output_fifo/output_fifo_sim_netlist.vhdl
-- Design : output_fifo
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_blk_mem_gen_prim_wrapper is
port (
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 11 downto 0 );
ram_rd_en_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
end output_fifo_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of output_fifo_blk_mem_gen_prim_wrapper is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_16\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_17\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_24\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_25\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_34\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_35\ : STD_LOGIC;
signal tmp_ram_regce : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 18,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 18
)
port map (
ADDRARDADDR(13 downto 4) => Q(9 downto 0),
ADDRARDADDR(3 downto 0) => B"0000",
ADDRBWRADDR(13 downto 4) => \gc0.count_d1_reg[9]\(9 downto 0),
ADDRBWRADDR(3 downto 0) => B"0000",
CLKARDCLK => clk,
CLKBWRCLK => clk,
DIADI(15 downto 14) => B"00",
DIADI(13 downto 8) => din(11 downto 6),
DIADI(7 downto 6) => B"00",
DIADI(5 downto 0) => din(5 downto 0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 0),
DOBDO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_16\,
DOBDO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_17\,
DOBDO(13 downto 8) => dout(11 downto 6),
DOBDO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_24\,
DOBDO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_25\,
DOBDO(5 downto 0) => dout(5 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_34\,
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_35\,
ENARDEN => WEA(0),
ENBWREN => tmp_ram_rd_en,
REGCEAREGCE => '0',
REGCEB => tmp_ram_regce,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => srst,
WEA(1) => WEA(0),
WEA(0) => WEA(0),
WEBWE(3 downto 0) => B"0000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => srst,
I1 => ram_rd_en_d1,
O => tmp_ram_regce
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_compare is
port (
ram_full_fb_i_reg : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
wr_en : in STD_LOGIC;
comp1 : in STD_LOGIC;
\out\ : in STD_LOGIC;
rd_en : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_compare : entity is "compare";
end output_fifo_compare;
architecture STRUCTURE of output_fifo_compare is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal comp0 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp0,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg(4)
);
ram_full_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFC0FFC05500FFC0"
)
port map (
I0 => comp0,
I1 => wr_en,
I2 => comp1,
I3 => \out\,
I4 => rd_en,
I5 => ram_empty_fb_i_reg,
O => ram_full_fb_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_compare_0 is
port (
comp1 : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_compare_0 : entity is "compare";
end output_fifo_compare_0;
architecture STRUCTURE of output_fifo_compare_0 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_0(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg_0(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_compare_1 is
port (
ram_empty_i_reg : out STD_LOGIC;
\gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC;
rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC;
comp1 : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_compare_1 : entity is "compare";
end output_fifo_compare_1;
architecture STRUCTURE of output_fifo_compare_1 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal comp0 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3) => \gcc0.gc0.count_d1_reg[6]\,
S(2) => \gcc0.gc0.count_d1_reg[4]\,
S(1) => \gcc0.gc0.count_d1_reg[2]\,
S(0) => \gcc0.gc0.count_d1_reg[0]\
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp0,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => \gcc0.gc0.count_d1_reg[8]\
);
ram_empty_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FCF0FCF05050FCF0"
)
port map (
I0 => comp0,
I1 => rd_en,
I2 => \out\,
I3 => comp1,
I4 => wr_en,
I5 => ram_full_fb_i_reg,
O => ram_empty_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_compare_2 is
port (
comp1 : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_compare_2 : entity is "compare";
end output_fifo_compare_2;
architecture STRUCTURE of output_fifo_compare_2 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_rd_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
srst : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_rd_bin_cntr : entity is "rd_bin_cntr";
end output_fifo_rd_bin_cntr;
architecture STRUCTURE of output_fifo_rd_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \gc0.count[9]_i_2_n_0\ : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gc0.count[6]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gc0.count[7]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gc0.count[8]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gc0.count[9]_i_1\ : label is "soft_lutpair0";
begin
Q(9 downto 0) <= \^q\(9 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => plusOp(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => plusOp(4)
);
\gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => plusOp(5)
);
\gc0.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gc0.count[9]_i_2_n_0\,
I1 => \^q\(6),
O => plusOp(6)
);
\gc0.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \gc0.count[9]_i_2_n_0\,
I1 => \^q\(6),
I2 => \^q\(7),
O => plusOp(7)
);
\gc0.count[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count[9]_i_2_n_0\,
I2 => \^q\(7),
I3 => \^q\(8),
O => plusOp(8)
);
\gc0.count[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(7),
I1 => \gc0.count[9]_i_2_n_0\,
I2 => \^q\(6),
I3 => \^q\(8),
I4 => \^q\(9),
O => plusOp(9)
);
\gc0.count[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^q\(5),
I1 => \^q\(3),
I2 => \^q\(1),
I3 => \^q\(0),
I4 => \^q\(2),
I5 => \^q\(4),
O => \gc0.count[9]_i_2_n_0\
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(0),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(0),
R => srst
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(1),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(1),
R => srst
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(2),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(2),
R => srst
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(3),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(3),
R => srst
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(4),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(4),
R => srst
);
\gc0.count_d1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(5),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(5),
R => srst
);
\gc0.count_d1_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(6),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(6),
R => srst
);
\gc0.count_d1_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(7),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(7),
R => srst
);
\gc0.count_d1_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(8),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(8),
R => srst
);
\gc0.count_d1_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(9),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(9),
R => srst
);
\gc0.count_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => plusOp(0),
Q => \^q\(0),
S => srst
);
\gc0.count_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(1),
Q => \^q\(1),
R => srst
);
\gc0.count_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(2),
Q => \^q\(2),
R => srst
);
\gc0.count_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(3),
Q => \^q\(3),
R => srst
);
\gc0.count_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(4),
Q => \^q\(4),
R => srst
);
\gc0.count_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(5),
Q => \^q\(5),
R => srst
);
\gc0.count_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(6),
Q => \^q\(6),
R => srst
);
\gc0.count_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(7),
Q => \^q\(7),
R => srst
);
\gc0.count_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(8),
Q => \^q\(8),
R => srst
);
\gc0.count_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(9),
Q => \^q\(9),
R => srst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_wr_bin_cntr is
port (
v1_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_1 : out STD_LOGIC_VECTOR ( 4 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
ram_empty_i_reg_0 : out STD_LOGIC;
ram_empty_i_reg_1 : out STD_LOGIC;
ram_empty_i_reg_2 : out STD_LOGIC;
ram_empty_i_reg_3 : out STD_LOGIC;
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
srst : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_wr_bin_cntr : entity is "wr_bin_cntr";
end output_fifo_wr_bin_cntr;
architecture STRUCTURE of output_fifo_wr_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \gcc0.gc0.count[9]_i_2_n_0\ : STD_LOGIC;
signal p_12_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gcc0.gc0.count[1]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gcc0.gc0.count[2]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gcc0.gc0.count[3]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gcc0.gc0.count[4]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gcc0.gc0.count[6]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gcc0.gc0.count[7]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gcc0.gc0.count[8]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gcc0.gc0.count[9]_i_1\ : label is "soft_lutpair4";
begin
Q(9 downto 0) <= \^q\(9 downto 0);
\gcc0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => p_12_out(0),
O => \plusOp__0\(0)
);
\gcc0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_12_out(0),
I1 => p_12_out(1),
O => \plusOp__0\(1)
);
\gcc0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => p_12_out(0),
I1 => p_12_out(1),
I2 => p_12_out(2),
O => \plusOp__0\(2)
);
\gcc0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => p_12_out(1),
I1 => p_12_out(0),
I2 => p_12_out(2),
I3 => p_12_out(3),
O => \plusOp__0\(3)
);
\gcc0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => p_12_out(2),
I1 => p_12_out(0),
I2 => p_12_out(1),
I3 => p_12_out(3),
I4 => p_12_out(4),
O => \plusOp__0\(4)
);
\gcc0.gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => p_12_out(3),
I1 => p_12_out(1),
I2 => p_12_out(0),
I3 => p_12_out(2),
I4 => p_12_out(4),
I5 => p_12_out(5),
O => \plusOp__0\(5)
);
\gcc0.gc0.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gcc0.gc0.count[9]_i_2_n_0\,
I1 => p_12_out(6),
O => \plusOp__0\(6)
);
\gcc0.gc0.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \gcc0.gc0.count[9]_i_2_n_0\,
I1 => p_12_out(6),
I2 => p_12_out(7),
O => \plusOp__0\(7)
);
\gcc0.gc0.count[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => p_12_out(6),
I1 => \gcc0.gc0.count[9]_i_2_n_0\,
I2 => p_12_out(7),
I3 => p_12_out(8),
O => \plusOp__0\(8)
);
\gcc0.gc0.count[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => p_12_out(7),
I1 => \gcc0.gc0.count[9]_i_2_n_0\,
I2 => p_12_out(6),
I3 => p_12_out(8),
I4 => p_12_out(9),
O => \plusOp__0\(9)
);
\gcc0.gc0.count[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => p_12_out(5),
I1 => p_12_out(3),
I2 => p_12_out(1),
I3 => p_12_out(0),
I4 => p_12_out(2),
I5 => p_12_out(4),
O => \gcc0.gc0.count[9]_i_2_n_0\
);
\gcc0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(0),
Q => \^q\(0),
R => srst
);
\gcc0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(1),
Q => \^q\(1),
R => srst
);
\gcc0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(2),
Q => \^q\(2),
R => srst
);
\gcc0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(3),
Q => \^q\(3),
R => srst
);
\gcc0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(4),
Q => \^q\(4),
R => srst
);
\gcc0.gc0.count_d1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(5),
Q => \^q\(5),
R => srst
);
\gcc0.gc0.count_d1_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(6),
Q => \^q\(6),
R => srst
);
\gcc0.gc0.count_d1_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(7),
Q => \^q\(7),
R => srst
);
\gcc0.gc0.count_d1_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(8),
Q => \^q\(8),
R => srst
);
\gcc0.gc0.count_d1_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(9),
Q => \^q\(9),
R => srst
);
\gcc0.gc0.count_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(0),
Q => p_12_out(0),
S => srst
);
\gcc0.gc0.count_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(1),
Q => p_12_out(1),
R => srst
);
\gcc0.gc0.count_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(2),
Q => p_12_out(2),
R => srst
);
\gcc0.gc0.count_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(3),
Q => p_12_out(3),
R => srst
);
\gcc0.gc0.count_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(4),
Q => p_12_out(4),
R => srst
);
\gcc0.gc0.count_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(5),
Q => p_12_out(5),
R => srst
);
\gcc0.gc0.count_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(6),
Q => p_12_out(6),
R => srst
);
\gcc0.gc0.count_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(7),
Q => p_12_out(7),
R => srst
);
\gcc0.gc0.count_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(8),
Q => p_12_out(8),
R => srst
);
\gcc0.gc0.count_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(9),
Q => p_12_out(9),
R => srst
);
\gmux.gm[0].gm1.m1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(0),
I1 => \gc0.count_d1_reg[9]\(0),
I2 => \^q\(1),
I3 => \gc0.count_d1_reg[9]\(1),
O => v1_reg_0(0)
);
\gmux.gm[0].gm1.m1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(0),
I1 => \gc0.count_reg[9]\(0),
I2 => \^q\(1),
I3 => \gc0.count_reg[9]\(1),
O => v1_reg(0)
);
\gmux.gm[0].gm1.m1_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(0),
I1 => \gc0.count_d1_reg[9]\(0),
I2 => p_12_out(1),
I3 => \gc0.count_d1_reg[9]\(1),
O => v1_reg_1(0)
);
\gmux.gm[0].gm1.m1_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(0),
I1 => \gc0.count_d1_reg[9]\(0),
I2 => \^q\(1),
I3 => \gc0.count_d1_reg[9]\(1),
O => ram_empty_i_reg
);
\gmux.gm[1].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_d1_reg[9]\(2),
I2 => \^q\(3),
I3 => \gc0.count_d1_reg[9]\(3),
O => v1_reg_0(1)
);
\gmux.gm[1].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_reg[9]\(2),
I2 => \^q\(3),
I3 => \gc0.count_reg[9]\(3),
O => v1_reg(1)
);
\gmux.gm[1].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(2),
I1 => \gc0.count_d1_reg[9]\(2),
I2 => p_12_out(3),
I3 => \gc0.count_d1_reg[9]\(3),
O => v1_reg_1(1)
);
\gmux.gm[1].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_d1_reg[9]\(2),
I2 => \^q\(3),
I3 => \gc0.count_d1_reg[9]\(3),
O => ram_empty_i_reg_0
);
\gmux.gm[2].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(4),
I1 => \gc0.count_d1_reg[9]\(4),
I2 => \^q\(5),
I3 => \gc0.count_d1_reg[9]\(5),
O => v1_reg_0(2)
);
\gmux.gm[2].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(4),
I1 => \gc0.count_reg[9]\(4),
I2 => \^q\(5),
I3 => \gc0.count_reg[9]\(5),
O => v1_reg(2)
);
\gmux.gm[2].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(4),
I1 => \gc0.count_d1_reg[9]\(4),
I2 => p_12_out(5),
I3 => \gc0.count_d1_reg[9]\(5),
O => v1_reg_1(2)
);
\gmux.gm[2].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(4),
I1 => \gc0.count_d1_reg[9]\(4),
I2 => \^q\(5),
I3 => \gc0.count_d1_reg[9]\(5),
O => ram_empty_i_reg_1
);
\gmux.gm[3].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count_d1_reg[9]\(6),
I2 => \^q\(7),
I3 => \gc0.count_d1_reg[9]\(7),
O => v1_reg_0(3)
);
\gmux.gm[3].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count_reg[9]\(6),
I2 => \^q\(7),
I3 => \gc0.count_reg[9]\(7),
O => v1_reg(3)
);
\gmux.gm[3].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(6),
I1 => \gc0.count_d1_reg[9]\(6),
I2 => p_12_out(7),
I3 => \gc0.count_d1_reg[9]\(7),
O => v1_reg_1(3)
);
\gmux.gm[3].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count_d1_reg[9]\(6),
I2 => \^q\(7),
I3 => \gc0.count_d1_reg[9]\(7),
O => ram_empty_i_reg_2
);
\gmux.gm[4].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(8),
I1 => \gc0.count_d1_reg[9]\(8),
I2 => \^q\(9),
I3 => \gc0.count_d1_reg[9]\(9),
O => v1_reg_0(4)
);
\gmux.gm[4].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(8),
I1 => \gc0.count_reg[9]\(8),
I2 => \^q\(9),
I3 => \gc0.count_reg[9]\(9),
O => v1_reg(4)
);
\gmux.gm[4].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(8),
I1 => \gc0.count_d1_reg[9]\(8),
I2 => p_12_out(9),
I3 => \gc0.count_d1_reg[9]\(9),
O => v1_reg_1(4)
);
\gmux.gm[4].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(8),
I1 => \gc0.count_d1_reg[9]\(8),
I2 => \^q\(9),
I3 => \gc0.count_d1_reg[9]\(9),
O => ram_empty_i_reg_3
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_blk_mem_gen_prim_width is
port (
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 11 downto 0 );
ram_rd_en_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end output_fifo_blk_mem_gen_prim_width;
architecture STRUCTURE of output_fifo_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.output_fifo_blk_mem_gen_prim_wrapper
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
clk => clk,
din(11 downto 0) => din(11 downto 0),
dout(11 downto 0) => dout(11 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
ram_rd_en_d1 => ram_rd_en_d1,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_rd_status_flags_ss is
port (
\out\ : out STD_LOGIC;
empty : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : out STD_LOGIC;
\gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
srst : in STD_LOGIC;
clk : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_rd_status_flags_ss : entity is "rd_status_flags_ss";
end output_fifo_rd_status_flags_ss;
architecture STRUCTURE of output_fifo_rd_status_flags_ss is
signal c1_n_0 : STD_LOGIC;
signal comp1 : STD_LOGIC;
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
empty <= ram_empty_i;
\out\ <= ram_empty_fb_i;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => ram_empty_fb_i,
I1 => rd_en,
I2 => srst,
O => tmp_ram_rd_en
);
c1: entity work.output_fifo_compare_1
port map (
comp1 => comp1,
\gcc0.gc0.count_d1_reg[0]\ => \gcc0.gc0.count_d1_reg[0]\,
\gcc0.gc0.count_d1_reg[2]\ => \gcc0.gc0.count_d1_reg[2]\,
\gcc0.gc0.count_d1_reg[4]\ => \gcc0.gc0.count_d1_reg[4]\,
\gcc0.gc0.count_d1_reg[6]\ => \gcc0.gc0.count_d1_reg[6]\,
\gcc0.gc0.count_d1_reg[8]\ => \gcc0.gc0.count_d1_reg[8]\,
\out\ => ram_empty_fb_i,
ram_empty_i_reg => c1_n_0,
ram_full_fb_i_reg => ram_full_fb_i_reg,
rd_en => rd_en,
wr_en => wr_en
);
c2: entity work.output_fifo_compare_2
port map (
comp1 => comp1,
v1_reg(4 downto 0) => v1_reg(4 downto 0)
);
\gbm.gregce.ram_rd_en_d1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => ram_empty_fb_i,
O => E(0)
);
ram_empty_fb_i_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => c1_n_0,
Q => ram_empty_fb_i,
S => srst
);
ram_empty_i_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => c1_n_0,
Q => ram_empty_i,
S => srst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_wr_status_flags_ss is
port (
\out\ : out STD_LOGIC;
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
srst : in STD_LOGIC;
clk : in STD_LOGIC;
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_wr_status_flags_ss : entity is "wr_status_flags_ss";
end output_fifo_wr_status_flags_ss;
architecture STRUCTURE of output_fifo_wr_status_flags_ss is
signal c0_n_0 : STD_LOGIC;
signal comp1 : STD_LOGIC;
signal ram_afull_fb : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_afull_fb : signal is std.standard.true;
signal ram_afull_i : STD_LOGIC;
attribute DONT_TOUCH of ram_afull_i : signal is std.standard.true;
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
full <= ram_full_i;
\out\ <= ram_full_fb_i;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => ram_full_fb_i,
O => E(0)
);
c0: entity work.output_fifo_compare
port map (
comp1 => comp1,
\out\ => ram_full_fb_i,
ram_empty_fb_i_reg => ram_empty_fb_i_reg,
ram_full_fb_i_reg => c0_n_0,
rd_en => rd_en,
v1_reg(4 downto 0) => v1_reg(4 downto 0),
wr_en => wr_en
);
c1: entity work.output_fifo_compare_0
port map (
comp1 => comp1,
v1_reg_0(4 downto 0) => v1_reg_0(4 downto 0)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => ram_afull_i
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => ram_afull_fb
);
ram_full_fb_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => c0_n_0,
Q => ram_full_fb_i,
R => srst
);
ram_full_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => c0_n_0,
Q => ram_full_i,
R => srst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_blk_mem_gen_generic_cstr is
port (
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 11 downto 0 );
ram_rd_en_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end output_fifo_blk_mem_gen_generic_cstr;
architecture STRUCTURE of output_fifo_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.output_fifo_blk_mem_gen_prim_width
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
clk => clk,
din(11 downto 0) => din(11 downto 0),
dout(11 downto 0) => dout(11 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
ram_rd_en_d1 => ram_rd_en_d1,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_rd_logic is
port (
\out\ : out STD_LOGIC;
empty : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
\gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
srst : in STD_LOGIC;
clk : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_rd_logic : entity is "rd_logic";
end output_fifo_rd_logic;
architecture STRUCTURE of output_fifo_rd_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
E(0) <= \^e\(0);
\grss.rsts\: entity work.output_fifo_rd_status_flags_ss
port map (
E(0) => \^e\(0),
clk => clk,
empty => empty,
\gcc0.gc0.count_d1_reg[0]\ => \gcc0.gc0.count_d1_reg[0]\,
\gcc0.gc0.count_d1_reg[2]\ => \gcc0.gc0.count_d1_reg[2]\,
\gcc0.gc0.count_d1_reg[4]\ => \gcc0.gc0.count_d1_reg[4]\,
\gcc0.gc0.count_d1_reg[6]\ => \gcc0.gc0.count_d1_reg[6]\,
\gcc0.gc0.count_d1_reg[8]\ => \gcc0.gc0.count_d1_reg[8]\,
\out\ => \out\,
ram_full_fb_i_reg => ram_full_fb_i_reg,
rd_en => rd_en,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en,
v1_reg(4 downto 0) => v1_reg(4 downto 0),
wr_en => wr_en
);
rpntr: entity work.output_fifo_rd_bin_cntr
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(9 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(9 downto 0),
E(0) => \^e\(0),
Q(9 downto 0) => Q(9 downto 0),
clk => clk,
srst => srst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_wr_logic is
port (
\out\ : out STD_LOGIC;
full : out STD_LOGIC;
WEA : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
ram_empty_i_reg_0 : out STD_LOGIC;
ram_empty_i_reg_1 : out STD_LOGIC;
ram_empty_i_reg_2 : out STD_LOGIC;
ram_empty_i_reg_3 : out STD_LOGIC;
srst : in STD_LOGIC;
clk : in STD_LOGIC;
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_wr_logic : entity is "wr_logic";
end output_fifo_wr_logic;
architecture STRUCTURE of output_fifo_wr_logic is
signal \^wea\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \c0/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \c1/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
begin
WEA(0) <= \^wea\(0);
\gwss.wsts\: entity work.output_fifo_wr_status_flags_ss
port map (
E(0) => \^wea\(0),
clk => clk,
full => full,
\out\ => \out\,
ram_empty_fb_i_reg => ram_empty_fb_i_reg,
rd_en => rd_en,
srst => srst,
v1_reg(4 downto 0) => \c0/v1_reg\(4 downto 0),
v1_reg_0(4 downto 0) => \c1/v1_reg\(4 downto 0),
wr_en => wr_en
);
wpntr: entity work.output_fifo_wr_bin_cntr
port map (
E(0) => \^wea\(0),
Q(9 downto 0) => Q(9 downto 0),
clk => clk,
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\gc0.count_reg[9]\(9 downto 0) => \gc0.count_reg[9]\(9 downto 0),
ram_empty_i_reg => ram_empty_i_reg,
ram_empty_i_reg_0 => ram_empty_i_reg_0,
ram_empty_i_reg_1 => ram_empty_i_reg_1,
ram_empty_i_reg_2 => ram_empty_i_reg_2,
ram_empty_i_reg_3 => ram_empty_i_reg_3,
srst => srst,
v1_reg(4 downto 0) => v1_reg(4 downto 0),
v1_reg_0(4 downto 0) => \c0/v1_reg\(4 downto 0),
v1_reg_1(4 downto 0) => \c1/v1_reg\(4 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_blk_mem_gen_top is
port (
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 11 downto 0 );
ram_rd_en_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_blk_mem_gen_top : entity is "blk_mem_gen_top";
end output_fifo_blk_mem_gen_top;
architecture STRUCTURE of output_fifo_blk_mem_gen_top is
begin
\valid.cstr\: entity work.output_fifo_blk_mem_gen_generic_cstr
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
clk => clk,
din(11 downto 0) => din(11 downto 0),
dout(11 downto 0) => dout(11 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
ram_rd_en_d1 => ram_rd_en_d1,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_blk_mem_gen_v8_3_5_synth is
port (
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 11 downto 0 );
ram_rd_en_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth";
end output_fifo_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of output_fifo_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.output_fifo_blk_mem_gen_top
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
clk => clk,
din(11 downto 0) => din(11 downto 0),
dout(11 downto 0) => dout(11 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
ram_rd_en_d1 => ram_rd_en_d1,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_blk_mem_gen_v8_3_5 is
port (
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 11 downto 0 );
ram_rd_en_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5";
end output_fifo_blk_mem_gen_v8_3_5;
architecture STRUCTURE of output_fifo_blk_mem_gen_v8_3_5 is
begin
inst_blk_mem_gen: entity work.output_fifo_blk_mem_gen_v8_3_5_synth
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
clk => clk,
din(11 downto 0) => din(11 downto 0),
dout(11 downto 0) => dout(11 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
ram_rd_en_d1 => ram_rd_en_d1,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_memory is
port (
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 11 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_memory : entity is "memory";
end output_fifo_memory;
architecture STRUCTURE of output_fifo_memory is
signal ram_rd_en_d1 : STD_LOGIC;
begin
\gbm.gbmg.gbmgc.ngecc.bmg\: entity work.output_fifo_blk_mem_gen_v8_3_5
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
clk => clk,
din(11 downto 0) => din(11 downto 0),
dout(11 downto 0) => dout(11 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
ram_rd_en_d1 => ram_rd_en_d1,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
\gbm.gregce.ram_rd_en_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => E(0),
Q => ram_rd_en_d1,
R => srst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_fifo_generator_ramfifo is
port (
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
clk : in STD_LOGIC;
srst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_fifo_generator_ramfifo : entity is "fifo_generator_ramfifo";
end output_fifo_fifo_generator_ramfifo;
architecture STRUCTURE of output_fifo_fifo_generator_ramfifo is
signal \gntv_or_sync_fifo.gl0.rd_n_2\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_18\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_19\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_2\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_20\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_21\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_22\ : STD_LOGIC;
signal \grss.rsts/c2/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_0_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_11_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_2_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 9 downto 0 );
signal tmp_ram_rd_en : STD_LOGIC;
begin
\gntv_or_sync_fifo.gl0.rd\: entity work.output_fifo_rd_logic
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(9 downto 0) => p_0_out(9 downto 0),
E(0) => \gntv_or_sync_fifo.gl0.rd_n_2\,
Q(9 downto 0) => rd_pntr_plus1(9 downto 0),
clk => clk,
empty => empty,
\gcc0.gc0.count_d1_reg[0]\ => \gntv_or_sync_fifo.gl0.wr_n_18\,
\gcc0.gc0.count_d1_reg[2]\ => \gntv_or_sync_fifo.gl0.wr_n_19\,
\gcc0.gc0.count_d1_reg[4]\ => \gntv_or_sync_fifo.gl0.wr_n_20\,
\gcc0.gc0.count_d1_reg[6]\ => \gntv_or_sync_fifo.gl0.wr_n_21\,
\gcc0.gc0.count_d1_reg[8]\ => \gntv_or_sync_fifo.gl0.wr_n_22\,
\out\ => p_2_out,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_0\,
rd_en => rd_en,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en,
v1_reg(4 downto 0) => \grss.rsts/c2/v1_reg\(4 downto 0),
wr_en => wr_en
);
\gntv_or_sync_fifo.gl0.wr\: entity work.output_fifo_wr_logic
port map (
Q(9 downto 0) => p_11_out(9 downto 0),
WEA(0) => \gntv_or_sync_fifo.gl0.wr_n_2\,
clk => clk,
full => full,
\gc0.count_d1_reg[9]\(9 downto 0) => p_0_out(9 downto 0),
\gc0.count_reg[9]\(9 downto 0) => rd_pntr_plus1(9 downto 0),
\out\ => \gntv_or_sync_fifo.gl0.wr_n_0\,
ram_empty_fb_i_reg => p_2_out,
ram_empty_i_reg => \gntv_or_sync_fifo.gl0.wr_n_18\,
ram_empty_i_reg_0 => \gntv_or_sync_fifo.gl0.wr_n_19\,
ram_empty_i_reg_1 => \gntv_or_sync_fifo.gl0.wr_n_20\,
ram_empty_i_reg_2 => \gntv_or_sync_fifo.gl0.wr_n_21\,
ram_empty_i_reg_3 => \gntv_or_sync_fifo.gl0.wr_n_22\,
rd_en => rd_en,
srst => srst,
v1_reg(4 downto 0) => \grss.rsts/c2/v1_reg\(4 downto 0),
wr_en => wr_en
);
\gntv_or_sync_fifo.mem\: entity work.output_fifo_memory
port map (
E(0) => \gntv_or_sync_fifo.gl0.rd_n_2\,
Q(9 downto 0) => p_11_out(9 downto 0),
WEA(0) => \gntv_or_sync_fifo.gl0.wr_n_2\,
clk => clk,
din(11 downto 0) => din(11 downto 0),
dout(11 downto 0) => dout(11 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => p_0_out(9 downto 0),
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_fifo_generator_top is
port (
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
clk : in STD_LOGIC;
srst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_fifo_generator_top : entity is "fifo_generator_top";
end output_fifo_fifo_generator_top;
architecture STRUCTURE of output_fifo_fifo_generator_top is
begin
\grf.rf\: entity work.output_fifo_fifo_generator_ramfifo
port map (
clk => clk,
din(11 downto 0) => din(11 downto 0),
dout(11 downto 0) => dout(11 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
srst => srst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_fifo_generator_v13_1_3_synth is
port (
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
clk : in STD_LOGIC;
srst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_fifo_generator_v13_1_3_synth : entity is "fifo_generator_v13_1_3_synth";
end output_fifo_fifo_generator_v13_1_3_synth;
architecture STRUCTURE of output_fifo_fifo_generator_v13_1_3_synth is
begin
\gconvfifo.rf\: entity work.output_fifo_fifo_generator_top
port map (
clk => clk,
din(11 downto 0) => din(11 downto 0),
dout(11 downto 0) => dout(11 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
srst => srst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_fifo_generator_v13_1_3 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 11 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 9 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 10;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of output_fifo_fifo_generator_v13_1_3 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 12;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of output_fifo_fifo_generator_v13_1_3 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 12;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of output_fifo_fifo_generator_v13_1_3 : entity is "zynq";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of output_fifo_fifo_generator_v13_1_3 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of output_fifo_fifo_generator_v13_1_3 : entity is 2;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of output_fifo_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of output_fifo_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of output_fifo_fifo_generator_v13_1_3 : entity is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of output_fifo_fifo_generator_v13_1_3 : entity is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of output_fifo_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of output_fifo_fifo_generator_v13_1_3 : entity is 1021;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 10;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of output_fifo_fifo_generator_v13_1_3 : entity is 1024;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 10;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of output_fifo_fifo_generator_v13_1_3 : entity is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 10;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of output_fifo_fifo_generator_v13_1_3 : entity is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_fifo_generator_v13_1_3 : entity is "fifo_generator_v13_1_3";
end output_fifo_fifo_generator_v13_1_3;
architecture STRUCTURE of output_fifo_fifo_generator_v13_1_3 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(9) <= \<const0>\;
data_count(8) <= \<const0>\;
data_count(7) <= \<const0>\;
data_count(6) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(9) <= \<const0>\;
rd_data_count(8) <= \<const0>\;
rd_data_count(7) <= \<const0>\;
rd_data_count(6) <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(9) <= \<const0>\;
wr_data_count(8) <= \<const0>\;
wr_data_count(7) <= \<const0>\;
wr_data_count(6) <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.output_fifo_fifo_generator_v13_1_3_synth
port map (
clk => clk,
din(11 downto 0) => din(11 downto 0),
dout(11 downto 0) => dout(11 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
srst => srst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo is
port (
clk : in STD_LOGIC;
srst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 11 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of output_fifo : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of output_fifo : entity is "output_fifo,fifo_generator_v13_1_3,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of output_fifo : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of output_fifo : entity is "fifo_generator_v13_1_3,Vivado 2016.4";
end output_fifo;
architecture STRUCTURE of output_fifo is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 12;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 12;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 0;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 0;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 1;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 2;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 1022;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 1021;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 1024;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 10;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 1;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.output_fifo_fifo_generator_v13_1_3
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3 downto 0) => B"0000",
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3 downto 0) => B"0000",
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9 downto 0) => B"0000000000",
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9 downto 0) => B"0000000000",
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => clk,
data_count(9 downto 0) => NLW_U0_data_count_UNCONNECTED(9 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(11 downto 0) => din(11 downto 0),
dout(11 downto 0) => dout(11 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1 downto 0) => B"00",
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1 downto 0) => B"00",
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(9 downto 0) => B"0000000000",
prog_empty_thresh_assert(9 downto 0) => B"0000000000",
prog_empty_thresh_negate(9 downto 0) => B"0000000000",
prog_full => NLW_U0_prog_full_UNCONNECTED,
prog_full_thresh(9 downto 0) => B"0000000000",
prog_full_thresh_assert(9 downto 0) => B"0000000000",
prog_full_thresh_negate(9 downto 0) => B"0000000000",
rd_clk => '0',
rd_data_count(9 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(9 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => '0',
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => B"000",
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7 downto 0) => B"00000000",
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7 downto 0) => B"00000000",
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => srst,
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => '0',
wr_data_count(9 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(9 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
| unlicense | d59c72a9607e826ebec1fa7b019b379c | 0.630997 | 2.89847 | false | false | false | false |
jairov4/accel-oil | solution_virtex5/impl/pcores/nfa_accept_samples_generic_hw_top_v1_00_a/synhdl/vhdl/nfa_forward_buckets_if_ap_fifo_af.vhd | 2 | 6,299 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity nfa_forward_buckets_if_ap_fifo_af_ram is
generic(
mem_style : string := "block";
dwidth : integer := 64;
awidth : integer := 6;
mem_size : integer := 64
);
port (
clk : in std_logic;
din : in std_logic_vector(dwidth-1 downto 0);
w_addr : in std_logic_vector(awidth-1 downto 0);
we : in std_logic;
r_addr : in std_logic_vector(awidth-1 downto 0);
dout : out std_logic_vector(dwidth-1 downto 0)
);
end entity;
architecture rtl of nfa_forward_buckets_if_ap_fifo_af_ram is
type mem_array is array (mem_size-1 downto 0) of std_logic_vector (dwidth-1 downto 0);
signal mem : mem_array;
attribute ram_style : string;
attribute ram_style of mem : signal is mem_style;
begin
p_memory_read: process (clk)
begin
if (clk = '1' and clk'event) then
if (we = '1') then
mem(CONV_INTEGER(w_addr)) <= din;
end if;
dout <= mem(CONV_INTEGER(r_addr));
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity nfa_forward_buckets_if_ap_fifo_af is
generic (
MEM_STYLE : string := "block";
DATA_WIDTH : integer := 64;
ADDR_WIDTH : integer := 6;
DEPTH : integer := 64;
ALMOST_FULL_MARGIN : integer := 2);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of nfa_forward_buckets_if_ap_fifo_af is
component nfa_forward_buckets_if_ap_fifo_af_ram is
generic(
mem_style : string := "block";
dwidth : integer := 64;
awidth : integer := 6;
mem_size : integer := 64
);
port (
clk : in std_logic;
din : in std_logic_vector(dwidth-1 downto 0);
w_addr : in std_logic_vector(awidth-1 downto 0);
we : in std_logic;
r_addr : in std_logic_vector(awidth-1 downto 0);
dout : out std_logic_vector(dwidth-1 downto 0)
);
end component;
signal mInPtr, mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal mInPtr_next, mOutPtr_next : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal ram_raddr, ram_waddr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal ram_din, ram_dout : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal conflict_buff : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal conflict_buff_valid : STD_LOGIC;
signal ram_we : STD_LOGIC;
signal wordUsed : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0);
signal internal_empty_n, internal_full_n: STD_LOGIC;
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
ram_din <= if_din;
process (wordUsed, conflict_buff_valid, conflict_buff, ram_dout)
begin
if ( wordUsed = 1 and conflict_buff_valid = '1' ) then
if_dout <= conflict_buff;
else
if_dout <= ram_dout;
end if;
end process;
process (mOutPtr)
begin
if ( mOutPtr < DEPTH -1 ) then
mOutPtr_next <= mOutPtr + 1;
else
mOutPtr_next <= (others => '0');
end if;
end process;
process (mInPtr)
begin
if ( mInPtr < DEPTH -1 ) then
mInPtr_next <= mInPtr + 1;
else
mInPtr_next <= (others => '0');
end if;
end process;
process (clk, reset)
begin
if reset = '1' then
mInPtr <= (others => '0');
mOutPtr <= (others => '0');
wordUsed <= (others => '0');
internal_empty_n <= '0';
internal_full_n <= '1';
conflict_buff <= (others => '0');
conflict_buff_valid <= '0';
else
if clk'event and clk = '1' then
if if_read = '1' and internal_empty_n = '1' then
mOutPtr <= mOutPtr_next;
end if;
if (if_write = '1') then
mInPtr <= mInPtr_next;
end if;
if (if_read = '1' and internal_empty_n = '1' and if_write = '0') then
wordUsed <= wordUsed -1;
if (wordUsed = 1) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif (if_read = '0' or internal_empty_n = '0') and
(if_write = '1') then
wordUsed <= wordUsed +1;
internal_empty_n <= '1';
if (wordUsed + ALMOST_FULL_MARGIN = DEPTH -1) then
internal_full_n <= '0';
end if;
end if;
conflict_buff <= if_din;
conflict_buff_valid <= if_write and internal_full_n;
end if;
end if;
end process;
ram_waddr <= mInPtr;
ram_raddr <= mOutPtr_next when if_read = '1' and internal_empty_n = '1' else mOutPtr;
-- if a read occur on the following clock edge, prepare next read data in advance
ram_we <= if_write; -- caller should check almost_full signal
U_nfa_forward_buckets_if_ap_fifo_af_ram : nfa_forward_buckets_if_ap_fifo_af_ram
generic map (
mem_style => MEM_STYLE,
dwidth => DATA_WIDTH,
awidth => ADDR_WIDTH,
mem_size => DEPTH)
port map (
clk => clk,
din => ram_din,
w_addr => ram_waddr,
we => ram_we,
r_addr => ram_raddr,
dout => ram_dout);
end rtl;
| lgpl-3.0 | 600bd8b118d1c1df8919151010390624 | 0.516907 | 3.607675 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00388.vhd | 1 | 71,915 | -- NEED RESULT: ARCH00388.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00388.P2: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00388.P3: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00388.P4: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00388.P5: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00388.P6: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00388.P7: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00388.P8: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00388.P9: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00388.P10: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00388: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00388: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00388: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00388: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00388: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00388: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00388: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00388: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00388: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00388: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00388: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00388: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00388: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00388: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00388: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00388: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00388: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00388: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00388: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00388: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00388: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00388: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00388: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00388: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00388: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00388: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00388: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00388: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00388: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00388: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00388: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00388: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00388: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00388: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00388: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00388: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00388: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00388: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00388: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00388: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: P10: Inertial transactions completed entirely passed
-- NEED RESULT: P9: Inertial transactions completed entirely passed
-- NEED RESULT: P8: Inertial transactions completed entirely passed
-- NEED RESULT: P7: Inertial transactions completed entirely passed
-- NEED RESULT: P6: Inertial transactions completed entirely passed
-- NEED RESULT: P5: Inertial transactions completed entirely passed
-- NEED RESULT: P4: Inertial transactions completed entirely passed
-- NEED RESULT: P3: Inertial transactions completed entirely passed
-- NEED RESULT: P2: Inertial transactions completed entirely passed
-- NEED RESULT: P1: Inertial transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00388
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (3)
-- 9.5.1 (1)
-- 9.5.1 (2)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00388(ARCH00388)
-- ENT00388_Test_Bench(ARCH00388_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00388 is
port (
s_st_boolean_vector : inout st_boolean_vector
; s_st_severity_level_vector : inout st_severity_level_vector
; s_st_string : inout st_string
; s_st_enum1_vector : inout st_enum1_vector
; s_st_integer_vector : inout st_integer_vector
; s_st_time_vector : inout st_time_vector
; s_st_real_vector : inout st_real_vector
; s_st_rec1_vector : inout st_rec1_vector
; s_st_arr2_vector : inout st_arr2_vector
; s_st_arr2 : inout st_arr2
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_boolean_vector : chk_sig_type := -1 ;
signal chk_st_severity_level_vector : chk_sig_type := -1 ;
signal chk_st_string : chk_sig_type := -1 ;
signal chk_st_enum1_vector : chk_sig_type := -1 ;
signal chk_st_integer_vector : chk_sig_type := -1 ;
signal chk_st_time_vector : chk_sig_type := -1 ;
signal chk_st_real_vector : chk_sig_type := -1 ;
signal chk_st_rec1_vector : chk_sig_type := -1 ;
signal chk_st_arr2_vector : chk_sig_type := -1 ;
signal chk_st_arr2 : chk_sig_type := -1 ;
--
end ENT00388 ;
--
--
architecture ARCH00388 of ENT00388 is
subtype chk_time_type is Time ;
signal s_st_boolean_vector_savt : chk_time_type := 0 ns ;
signal s_st_severity_level_vector_savt : chk_time_type := 0 ns ;
signal s_st_string_savt : chk_time_type := 0 ns ;
signal s_st_enum1_vector_savt : chk_time_type := 0 ns ;
signal s_st_integer_vector_savt : chk_time_type := 0 ns ;
signal s_st_time_vector_savt : chk_time_type := 0 ns ;
signal s_st_real_vector_savt : chk_time_type := 0 ns ;
signal s_st_rec1_vector_savt : chk_time_type := 0 ns ;
signal s_st_arr2_vector_savt : chk_time_type := 0 ns ;
signal s_st_arr2_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_boolean_vector_cnt : chk_cnt_type := 0 ;
signal s_st_severity_level_vector_cnt : chk_cnt_type := 0 ;
signal s_st_string_cnt : chk_cnt_type := 0 ;
signal s_st_enum1_vector_cnt : chk_cnt_type := 0 ;
signal s_st_integer_vector_cnt : chk_cnt_type := 0 ;
signal s_st_time_vector_cnt : chk_cnt_type := 0 ;
signal s_st_real_vector_cnt : chk_cnt_type := 0 ;
signal s_st_rec1_vector_cnt : chk_cnt_type := 0 ;
signal s_st_arr2_vector_cnt : chk_cnt_type := 0 ;
signal s_st_arr2_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 6 ;
signal st_boolean_vector_select : select_type := 1 ;
signal st_severity_level_vector_select : select_type := 1 ;
signal st_string_select : select_type := 1 ;
signal st_enum1_vector_select : select_type := 1 ;
signal st_integer_vector_select : select_type := 1 ;
signal st_time_vector_select : select_type := 1 ;
signal st_real_vector_select : select_type := 1 ;
signal st_rec1_vector_select : select_type := 1 ;
signal st_arr2_vector_select : select_type := 1 ;
signal st_arr2_select : select_type := 1 ;
--
begin
CHG1 :
process
variable correct : boolean ;
begin
case s_st_boolean_vector_cnt is
when 0
=> null ;
-- s_st_boolean_vector(lowb) <=
-- c_st_boolean_vector_2(lowb) after 10 ns,
-- c_st_boolean_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_boolean_vector(lowb) =
c_st_boolean_vector_2(lowb) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_1(lowb) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00388.P1" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_boolean_vector_select <= transport 2 ;
-- s_st_boolean_vector(lowb) <=
-- c_st_boolean_vector_2(lowb) after 10 ns ,
-- c_st_boolean_vector_1(lowb) after 20 ns ,
-- c_st_boolean_vector_2(lowb) after 30 ns ,
-- c_st_boolean_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_boolean_vector(lowb) =
c_st_boolean_vector_2(lowb) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
st_boolean_vector_select <= transport 3 ;
-- s_st_boolean_vector(lowb) <=
-- c_st_boolean_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_1(lowb) and
(s_st_boolean_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00388" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_boolean_vector_select <= transport 4 ;
-- s_st_boolean_vector(lowb) <=
-- c_st_boolean_vector_1(lowb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_1(lowb) and
(s_st_boolean_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00388" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_boolean_vector_select <= transport 5 ;
-- s_st_boolean_vector(lowb) <=
-- c_st_boolean_vector_2(lowb) after 10 ns ,
-- c_st_boolean_vector_1(lowb) after 20 ns ,
-- c_st_boolean_vector_2(lowb) after 30 ns ,
-- c_st_boolean_vector_1(lowb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_2(lowb) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00388" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_boolean_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_boolean_vector(lowb) <=
-- c_st_boolean_vector_1(lowb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_1(lowb) and
(s_st_boolean_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_1(lowb) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00388" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00388" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_boolean_vector_savt <= transport Std.Standard.Now ;
chk_st_boolean_vector <= transport s_st_boolean_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_boolean_vector_cnt <= transport s_st_boolean_vector_cnt + 1 ;
wait until (not s_st_boolean_vector(lowb)'Quiet) and
(s_st_boolean_vector_savt /= Std.Standard.Now) ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_boolean_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions completed entirely",
chk_st_boolean_vector = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
s_st_boolean_vector(lowb) <=
c_st_boolean_vector_2(lowb) after 10 ns,
c_st_boolean_vector_1(lowb) after 20 ns
when st_boolean_vector_select = 1 else
--
c_st_boolean_vector_2(lowb) after 10 ns ,
c_st_boolean_vector_1(lowb) after 20 ns ,
c_st_boolean_vector_2(lowb) after 30 ns ,
c_st_boolean_vector_1(lowb) after 40 ns
when st_boolean_vector_select = 2 else
--
c_st_boolean_vector_1(lowb) after 5 ns
when st_boolean_vector_select = 3 else
--
c_st_boolean_vector_1(lowb) after 100 ns
when st_boolean_vector_select = 4 else
--
c_st_boolean_vector_2(lowb) after 10 ns ,
c_st_boolean_vector_1(lowb) after 20 ns ,
c_st_boolean_vector_2(lowb) after 30 ns ,
c_st_boolean_vector_1(lowb) after 40 ns
when st_boolean_vector_select = 5 else
--
-- Last transaction above is marked
c_st_boolean_vector_1(lowb) after 40 ns ;
--
CHG2 :
process
variable correct : boolean ;
begin
case s_st_severity_level_vector_cnt is
when 0
=> null ;
-- s_st_severity_level_vector(lowb) <=
-- c_st_severity_level_vector_2(lowb) after 10 ns,
-- c_st_severity_level_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_2(lowb) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_1(lowb) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00388.P2" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_severity_level_vector_select <= transport 2 ;
-- s_st_severity_level_vector(lowb) <=
-- c_st_severity_level_vector_2(lowb) after 10 ns ,
-- c_st_severity_level_vector_1(lowb) after 20 ns ,
-- c_st_severity_level_vector_2(lowb) after 30 ns ,
-- c_st_severity_level_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_2(lowb) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
st_severity_level_vector_select <= transport 3 ;
-- s_st_severity_level_vector(lowb) <=
-- c_st_severity_level_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_1(lowb) and
(s_st_severity_level_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00388" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_severity_level_vector_select <= transport 4 ;
-- s_st_severity_level_vector(lowb) <=
-- c_st_severity_level_vector_1(lowb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_1(lowb) and
(s_st_severity_level_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00388" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_severity_level_vector_select <= transport 5 ;
-- s_st_severity_level_vector(lowb) <=
-- c_st_severity_level_vector_2(lowb) after 10 ns ,
-- c_st_severity_level_vector_1(lowb) after 20 ns ,
-- c_st_severity_level_vector_2(lowb) after 30 ns ,
-- c_st_severity_level_vector_1(lowb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_2(lowb) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00388" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_severity_level_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_severity_level_vector(lowb) <=
-- c_st_severity_level_vector_1(lowb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_1(lowb) and
(s_st_severity_level_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_1(lowb) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00388" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00388" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_severity_level_vector_savt <= transport Std.Standard.Now ;
chk_st_severity_level_vector <= transport s_st_severity_level_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_severity_level_vector_cnt <= transport s_st_severity_level_vector_cnt
+ 1 ;
wait until (not s_st_severity_level_vector(lowb)'Quiet) and
(s_st_severity_level_vector_savt /= Std.Standard.Now) ;
--
end process CHG2 ;
--
PGEN_CHKP_2 :
process ( chk_st_severity_level_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions completed entirely",
chk_st_severity_level_vector = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
s_st_severity_level_vector(lowb) <=
c_st_severity_level_vector_2(lowb) after 10 ns,
c_st_severity_level_vector_1(lowb) after 20 ns
when st_severity_level_vector_select = 1 else
--
c_st_severity_level_vector_2(lowb) after 10 ns ,
c_st_severity_level_vector_1(lowb) after 20 ns ,
c_st_severity_level_vector_2(lowb) after 30 ns ,
c_st_severity_level_vector_1(lowb) after 40 ns
when st_severity_level_vector_select = 2 else
--
c_st_severity_level_vector_1(lowb) after 5 ns
when st_severity_level_vector_select = 3 else
--
c_st_severity_level_vector_1(lowb) after 100 ns
when st_severity_level_vector_select = 4 else
--
c_st_severity_level_vector_2(lowb) after 10 ns ,
c_st_severity_level_vector_1(lowb) after 20 ns ,
c_st_severity_level_vector_2(lowb) after 30 ns ,
c_st_severity_level_vector_1(lowb) after 40 ns
when st_severity_level_vector_select = 5 else
--
-- Last transaction above is marked
c_st_severity_level_vector_1(lowb) after 40 ns ;
--
CHG3 :
process
variable correct : boolean ;
begin
case s_st_string_cnt is
when 0
=> null ;
-- s_st_string(highb) <=
-- c_st_string_2(highb) after 10 ns,
-- c_st_string_1(highb) after 20 ns ;
--
when 1
=> correct :=
s_st_string(highb) =
c_st_string_2(highb) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_string(highb) =
c_st_string_1(highb) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00388.P3" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_string_select <= transport 2 ;
-- s_st_string(highb) <=
-- c_st_string_2(highb) after 10 ns ,
-- c_st_string_1(highb) after 20 ns ,
-- c_st_string_2(highb) after 30 ns ,
-- c_st_string_1(highb) after 40 ns ;
--
when 3
=> correct :=
s_st_string(highb) =
c_st_string_2(highb) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
st_string_select <= transport 3 ;
-- s_st_string(highb) <=
-- c_st_string_1(highb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_string(highb) =
c_st_string_1(highb) and
(s_st_string_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00388" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_string_select <= transport 4 ;
-- s_st_string(highb) <=
-- c_st_string_1(highb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_string(highb) =
c_st_string_1(highb) and
(s_st_string_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00388" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_string_select <= transport 5 ;
-- s_st_string(highb) <=
-- c_st_string_2(highb) after 10 ns ,
-- c_st_string_1(highb) after 20 ns ,
-- c_st_string_2(highb) after 30 ns ,
-- c_st_string_1(highb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_string(highb) =
c_st_string_2(highb) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00388" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_string_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_string(highb) <=
-- c_st_string_1(highb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_string(highb) =
c_st_string_1(highb) and
(s_st_string_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_string(highb) =
c_st_string_1(highb) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00388" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00388" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_string_savt <= transport Std.Standard.Now ;
chk_st_string <= transport s_st_string_cnt
after (1 us - Std.Standard.Now) ;
s_st_string_cnt <= transport s_st_string_cnt + 1 ;
wait until (not s_st_string(highb)'Quiet) and
(s_st_string_savt /= Std.Standard.Now) ;
--
end process CHG3 ;
--
PGEN_CHKP_3 :
process ( chk_st_string )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions completed entirely",
chk_st_string = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
s_st_string(highb) <=
c_st_string_2(highb) after 10 ns,
c_st_string_1(highb) after 20 ns
when st_string_select = 1 else
--
c_st_string_2(highb) after 10 ns ,
c_st_string_1(highb) after 20 ns ,
c_st_string_2(highb) after 30 ns ,
c_st_string_1(highb) after 40 ns
when st_string_select = 2 else
--
c_st_string_1(highb) after 5 ns
when st_string_select = 3 else
--
c_st_string_1(highb) after 100 ns
when st_string_select = 4 else
--
c_st_string_2(highb) after 10 ns ,
c_st_string_1(highb) after 20 ns ,
c_st_string_2(highb) after 30 ns ,
c_st_string_1(highb) after 40 ns
when st_string_select = 5 else
--
-- Last transaction above is marked
c_st_string_1(highb) after 40 ns ;
--
CHG4 :
process
variable correct : boolean ;
begin
case s_st_enum1_vector_cnt is
when 0
=> null ;
-- s_st_enum1_vector(highb) <=
-- c_st_enum1_vector_2(highb) after 10 ns,
-- c_st_enum1_vector_1(highb) after 20 ns ;
--
when 1
=> correct :=
s_st_enum1_vector(highb) =
c_st_enum1_vector_2(highb) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_1(highb) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00388.P4" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_enum1_vector_select <= transport 2 ;
-- s_st_enum1_vector(highb) <=
-- c_st_enum1_vector_2(highb) after 10 ns ,
-- c_st_enum1_vector_1(highb) after 20 ns ,
-- c_st_enum1_vector_2(highb) after 30 ns ,
-- c_st_enum1_vector_1(highb) after 40 ns ;
--
when 3
=> correct :=
s_st_enum1_vector(highb) =
c_st_enum1_vector_2(highb) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
st_enum1_vector_select <= transport 3 ;
-- s_st_enum1_vector(highb) <=
-- c_st_enum1_vector_1(highb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_1(highb) and
(s_st_enum1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00388" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_enum1_vector_select <= transport 4 ;
-- s_st_enum1_vector(highb) <=
-- c_st_enum1_vector_1(highb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_1(highb) and
(s_st_enum1_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00388" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_enum1_vector_select <= transport 5 ;
-- s_st_enum1_vector(highb) <=
-- c_st_enum1_vector_2(highb) after 10 ns ,
-- c_st_enum1_vector_1(highb) after 20 ns ,
-- c_st_enum1_vector_2(highb) after 30 ns ,
-- c_st_enum1_vector_1(highb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_2(highb) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00388" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_enum1_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_enum1_vector(highb) <=
-- c_st_enum1_vector_1(highb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_1(highb) and
(s_st_enum1_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_1(highb) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00388" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00388" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_enum1_vector_savt <= transport Std.Standard.Now ;
chk_st_enum1_vector <= transport s_st_enum1_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_enum1_vector_cnt <= transport s_st_enum1_vector_cnt + 1 ;
wait until (not s_st_enum1_vector(highb)'Quiet) and
(s_st_enum1_vector_savt /= Std.Standard.Now) ;
--
end process CHG4 ;
--
PGEN_CHKP_4 :
process ( chk_st_enum1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Inertial transactions completed entirely",
chk_st_enum1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
--
s_st_enum1_vector(highb) <=
c_st_enum1_vector_2(highb) after 10 ns,
c_st_enum1_vector_1(highb) after 20 ns
when st_enum1_vector_select = 1 else
--
c_st_enum1_vector_2(highb) after 10 ns ,
c_st_enum1_vector_1(highb) after 20 ns ,
c_st_enum1_vector_2(highb) after 30 ns ,
c_st_enum1_vector_1(highb) after 40 ns
when st_enum1_vector_select = 2 else
--
c_st_enum1_vector_1(highb) after 5 ns
when st_enum1_vector_select = 3 else
--
c_st_enum1_vector_1(highb) after 100 ns
when st_enum1_vector_select = 4 else
--
c_st_enum1_vector_2(highb) after 10 ns ,
c_st_enum1_vector_1(highb) after 20 ns ,
c_st_enum1_vector_2(highb) after 30 ns ,
c_st_enum1_vector_1(highb) after 40 ns
when st_enum1_vector_select = 5 else
--
-- Last transaction above is marked
c_st_enum1_vector_1(highb) after 40 ns ;
--
CHG5 :
process
variable correct : boolean ;
begin
case s_st_integer_vector_cnt is
when 0
=> null ;
-- s_st_integer_vector(lowb) <=
-- c_st_integer_vector_2(lowb) after 10 ns,
-- c_st_integer_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_integer_vector(lowb) =
c_st_integer_vector_2(lowb) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_1(lowb) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00388.P5" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_integer_vector_select <= transport 2 ;
-- s_st_integer_vector(lowb) <=
-- c_st_integer_vector_2(lowb) after 10 ns ,
-- c_st_integer_vector_1(lowb) after 20 ns ,
-- c_st_integer_vector_2(lowb) after 30 ns ,
-- c_st_integer_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_integer_vector(lowb) =
c_st_integer_vector_2(lowb) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
st_integer_vector_select <= transport 3 ;
-- s_st_integer_vector(lowb) <=
-- c_st_integer_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_1(lowb) and
(s_st_integer_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00388" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_integer_vector_select <= transport 4 ;
-- s_st_integer_vector(lowb) <=
-- c_st_integer_vector_1(lowb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_1(lowb) and
(s_st_integer_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00388" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_integer_vector_select <= transport 5 ;
-- s_st_integer_vector(lowb) <=
-- c_st_integer_vector_2(lowb) after 10 ns ,
-- c_st_integer_vector_1(lowb) after 20 ns ,
-- c_st_integer_vector_2(lowb) after 30 ns ,
-- c_st_integer_vector_1(lowb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_2(lowb) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00388" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_integer_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_integer_vector(lowb) <=
-- c_st_integer_vector_1(lowb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_1(lowb) and
(s_st_integer_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_1(lowb) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00388" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00388" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_integer_vector_savt <= transport Std.Standard.Now ;
chk_st_integer_vector <= transport s_st_integer_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_integer_vector_cnt <= transport s_st_integer_vector_cnt + 1 ;
wait until (not s_st_integer_vector(lowb)'Quiet) and
(s_st_integer_vector_savt /= Std.Standard.Now) ;
--
end process CHG5 ;
--
PGEN_CHKP_5 :
process ( chk_st_integer_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Inertial transactions completed entirely",
chk_st_integer_vector = 8 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
--
s_st_integer_vector(lowb) <=
c_st_integer_vector_2(lowb) after 10 ns,
c_st_integer_vector_1(lowb) after 20 ns
when st_integer_vector_select = 1 else
--
c_st_integer_vector_2(lowb) after 10 ns ,
c_st_integer_vector_1(lowb) after 20 ns ,
c_st_integer_vector_2(lowb) after 30 ns ,
c_st_integer_vector_1(lowb) after 40 ns
when st_integer_vector_select = 2 else
--
c_st_integer_vector_1(lowb) after 5 ns
when st_integer_vector_select = 3 else
--
c_st_integer_vector_1(lowb) after 100 ns
when st_integer_vector_select = 4 else
--
c_st_integer_vector_2(lowb) after 10 ns ,
c_st_integer_vector_1(lowb) after 20 ns ,
c_st_integer_vector_2(lowb) after 30 ns ,
c_st_integer_vector_1(lowb) after 40 ns
when st_integer_vector_select = 5 else
--
-- Last transaction above is marked
c_st_integer_vector_1(lowb) after 40 ns ;
--
CHG6 :
process
variable correct : boolean ;
begin
case s_st_time_vector_cnt is
when 0
=> null ;
-- s_st_time_vector(lowb) <=
-- c_st_time_vector_2(lowb) after 10 ns,
-- c_st_time_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_time_vector(lowb) =
c_st_time_vector_2(lowb) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_1(lowb) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00388.P6" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_time_vector_select <= transport 2 ;
-- s_st_time_vector(lowb) <=
-- c_st_time_vector_2(lowb) after 10 ns ,
-- c_st_time_vector_1(lowb) after 20 ns ,
-- c_st_time_vector_2(lowb) after 30 ns ,
-- c_st_time_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_time_vector(lowb) =
c_st_time_vector_2(lowb) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
st_time_vector_select <= transport 3 ;
-- s_st_time_vector(lowb) <=
-- c_st_time_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_1(lowb) and
(s_st_time_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00388" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_time_vector_select <= transport 4 ;
-- s_st_time_vector(lowb) <=
-- c_st_time_vector_1(lowb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_1(lowb) and
(s_st_time_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00388" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_time_vector_select <= transport 5 ;
-- s_st_time_vector(lowb) <=
-- c_st_time_vector_2(lowb) after 10 ns ,
-- c_st_time_vector_1(lowb) after 20 ns ,
-- c_st_time_vector_2(lowb) after 30 ns ,
-- c_st_time_vector_1(lowb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_2(lowb) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00388" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_time_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_time_vector(lowb) <=
-- c_st_time_vector_1(lowb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_1(lowb) and
(s_st_time_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_1(lowb) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00388" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00388" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_time_vector_savt <= transport Std.Standard.Now ;
chk_st_time_vector <= transport s_st_time_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_time_vector_cnt <= transport s_st_time_vector_cnt + 1 ;
wait until (not s_st_time_vector(lowb)'Quiet) and
(s_st_time_vector_savt /= Std.Standard.Now) ;
--
end process CHG6 ;
--
PGEN_CHKP_6 :
process ( chk_st_time_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Inertial transactions completed entirely",
chk_st_time_vector = 8 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
--
s_st_time_vector(lowb) <=
c_st_time_vector_2(lowb) after 10 ns,
c_st_time_vector_1(lowb) after 20 ns
when st_time_vector_select = 1 else
--
c_st_time_vector_2(lowb) after 10 ns ,
c_st_time_vector_1(lowb) after 20 ns ,
c_st_time_vector_2(lowb) after 30 ns ,
c_st_time_vector_1(lowb) after 40 ns
when st_time_vector_select = 2 else
--
c_st_time_vector_1(lowb) after 5 ns
when st_time_vector_select = 3 else
--
c_st_time_vector_1(lowb) after 100 ns
when st_time_vector_select = 4 else
--
c_st_time_vector_2(lowb) after 10 ns ,
c_st_time_vector_1(lowb) after 20 ns ,
c_st_time_vector_2(lowb) after 30 ns ,
c_st_time_vector_1(lowb) after 40 ns
when st_time_vector_select = 5 else
--
-- Last transaction above is marked
c_st_time_vector_1(lowb) after 40 ns ;
--
CHG7 :
process
variable correct : boolean ;
begin
case s_st_real_vector_cnt is
when 0
=> null ;
-- s_st_real_vector(highb) <=
-- c_st_real_vector_2(highb) after 10 ns,
-- c_st_real_vector_1(highb) after 20 ns ;
--
when 1
=> correct :=
s_st_real_vector(highb) =
c_st_real_vector_2(highb) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_1(highb) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00388.P7" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_real_vector_select <= transport 2 ;
-- s_st_real_vector(highb) <=
-- c_st_real_vector_2(highb) after 10 ns ,
-- c_st_real_vector_1(highb) after 20 ns ,
-- c_st_real_vector_2(highb) after 30 ns ,
-- c_st_real_vector_1(highb) after 40 ns ;
--
when 3
=> correct :=
s_st_real_vector(highb) =
c_st_real_vector_2(highb) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
st_real_vector_select <= transport 3 ;
-- s_st_real_vector(highb) <=
-- c_st_real_vector_1(highb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_1(highb) and
(s_st_real_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00388" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_real_vector_select <= transport 4 ;
-- s_st_real_vector(highb) <=
-- c_st_real_vector_1(highb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_1(highb) and
(s_st_real_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00388" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_real_vector_select <= transport 5 ;
-- s_st_real_vector(highb) <=
-- c_st_real_vector_2(highb) after 10 ns ,
-- c_st_real_vector_1(highb) after 20 ns ,
-- c_st_real_vector_2(highb) after 30 ns ,
-- c_st_real_vector_1(highb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_2(highb) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00388" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_real_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_real_vector(highb) <=
-- c_st_real_vector_1(highb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_1(highb) and
(s_st_real_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_1(highb) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00388" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00388" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_real_vector_savt <= transport Std.Standard.Now ;
chk_st_real_vector <= transport s_st_real_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_real_vector_cnt <= transport s_st_real_vector_cnt + 1 ;
wait until (not s_st_real_vector(highb)'Quiet) and
(s_st_real_vector_savt /= Std.Standard.Now) ;
--
end process CHG7 ;
--
PGEN_CHKP_7 :
process ( chk_st_real_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Inertial transactions completed entirely",
chk_st_real_vector = 8 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
--
s_st_real_vector(highb) <=
c_st_real_vector_2(highb) after 10 ns,
c_st_real_vector_1(highb) after 20 ns
when st_real_vector_select = 1 else
--
c_st_real_vector_2(highb) after 10 ns ,
c_st_real_vector_1(highb) after 20 ns ,
c_st_real_vector_2(highb) after 30 ns ,
c_st_real_vector_1(highb) after 40 ns
when st_real_vector_select = 2 else
--
c_st_real_vector_1(highb) after 5 ns
when st_real_vector_select = 3 else
--
c_st_real_vector_1(highb) after 100 ns
when st_real_vector_select = 4 else
--
c_st_real_vector_2(highb) after 10 ns ,
c_st_real_vector_1(highb) after 20 ns ,
c_st_real_vector_2(highb) after 30 ns ,
c_st_real_vector_1(highb) after 40 ns
when st_real_vector_select = 5 else
--
-- Last transaction above is marked
c_st_real_vector_1(highb) after 40 ns ;
--
CHG8 :
process
variable correct : boolean ;
begin
case s_st_rec1_vector_cnt is
when 0
=> null ;
-- s_st_rec1_vector(highb) <=
-- c_st_rec1_vector_2(highb) after 10 ns,
-- c_st_rec1_vector_1(highb) after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_vector(highb) =
c_st_rec1_vector_2(highb) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_1(highb) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00388.P8" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec1_vector_select <= transport 2 ;
-- s_st_rec1_vector(highb) <=
-- c_st_rec1_vector_2(highb) after 10 ns ,
-- c_st_rec1_vector_1(highb) after 20 ns ,
-- c_st_rec1_vector_2(highb) after 30 ns ,
-- c_st_rec1_vector_1(highb) after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_vector(highb) =
c_st_rec1_vector_2(highb) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
st_rec1_vector_select <= transport 3 ;
-- s_st_rec1_vector(highb) <=
-- c_st_rec1_vector_1(highb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_1(highb) and
(s_st_rec1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00388" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_vector_select <= transport 4 ;
-- s_st_rec1_vector(highb) <=
-- c_st_rec1_vector_1(highb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_1(highb) and
(s_st_rec1_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00388" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec1_vector_select <= transport 5 ;
-- s_st_rec1_vector(highb) <=
-- c_st_rec1_vector_2(highb) after 10 ns ,
-- c_st_rec1_vector_1(highb) after 20 ns ,
-- c_st_rec1_vector_2(highb) after 30 ns ,
-- c_st_rec1_vector_1(highb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_2(highb) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00388" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec1_vector(highb) <=
-- c_st_rec1_vector_1(highb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_1(highb) and
(s_st_rec1_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_1(highb) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00388" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00388" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec1_vector_savt <= transport Std.Standard.Now ;
chk_st_rec1_vector <= transport s_st_rec1_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec1_vector_cnt <= transport s_st_rec1_vector_cnt + 1 ;
wait until (not s_st_rec1_vector(highb)'Quiet) and
(s_st_rec1_vector_savt /= Std.Standard.Now) ;
--
end process CHG8 ;
--
PGEN_CHKP_8 :
process ( chk_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Inertial transactions completed entirely",
chk_st_rec1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
--
s_st_rec1_vector(highb) <=
c_st_rec1_vector_2(highb) after 10 ns,
c_st_rec1_vector_1(highb) after 20 ns
when st_rec1_vector_select = 1 else
--
c_st_rec1_vector_2(highb) after 10 ns ,
c_st_rec1_vector_1(highb) after 20 ns ,
c_st_rec1_vector_2(highb) after 30 ns ,
c_st_rec1_vector_1(highb) after 40 ns
when st_rec1_vector_select = 2 else
--
c_st_rec1_vector_1(highb) after 5 ns
when st_rec1_vector_select = 3 else
--
c_st_rec1_vector_1(highb) after 100 ns
when st_rec1_vector_select = 4 else
--
c_st_rec1_vector_2(highb) after 10 ns ,
c_st_rec1_vector_1(highb) after 20 ns ,
c_st_rec1_vector_2(highb) after 30 ns ,
c_st_rec1_vector_1(highb) after 40 ns
when st_rec1_vector_select = 5 else
--
-- Last transaction above is marked
c_st_rec1_vector_1(highb) after 40 ns ;
--
CHG9 :
process
variable correct : boolean ;
begin
case s_st_arr2_vector_cnt is
when 0
=> null ;
-- s_st_arr2_vector(lowb) <=
-- c_st_arr2_vector_2(lowb) after 10 ns,
-- c_st_arr2_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2_vector(lowb) =
c_st_arr2_vector_2(lowb) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_1(lowb) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00388.P9" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr2_vector_select <= transport 2 ;
-- s_st_arr2_vector(lowb) <=
-- c_st_arr2_vector_2(lowb) after 10 ns ,
-- c_st_arr2_vector_1(lowb) after 20 ns ,
-- c_st_arr2_vector_2(lowb) after 30 ns ,
-- c_st_arr2_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2_vector(lowb) =
c_st_arr2_vector_2(lowb) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
st_arr2_vector_select <= transport 3 ;
-- s_st_arr2_vector(lowb) <=
-- c_st_arr2_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_1(lowb) and
(s_st_arr2_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00388" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_vector_select <= transport 4 ;
-- s_st_arr2_vector(lowb) <=
-- c_st_arr2_vector_1(lowb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_1(lowb) and
(s_st_arr2_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00388" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_arr2_vector_select <= transport 5 ;
-- s_st_arr2_vector(lowb) <=
-- c_st_arr2_vector_2(lowb) after 10 ns ,
-- c_st_arr2_vector_1(lowb) after 20 ns ,
-- c_st_arr2_vector_2(lowb) after 30 ns ,
-- c_st_arr2_vector_1(lowb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_2(lowb) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00388" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_arr2_vector(lowb) <=
-- c_st_arr2_vector_1(lowb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_1(lowb) and
(s_st_arr2_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_1(lowb) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00388" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00388" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_arr2_vector_savt <= transport Std.Standard.Now ;
chk_st_arr2_vector <= transport s_st_arr2_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr2_vector_cnt <= transport s_st_arr2_vector_cnt + 1 ;
wait until (not s_st_arr2_vector(lowb)'Quiet) and
(s_st_arr2_vector_savt /= Std.Standard.Now) ;
--
end process CHG9 ;
--
PGEN_CHKP_9 :
process ( chk_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Inertial transactions completed entirely",
chk_st_arr2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
--
s_st_arr2_vector(lowb) <=
c_st_arr2_vector_2(lowb) after 10 ns,
c_st_arr2_vector_1(lowb) after 20 ns
when st_arr2_vector_select = 1 else
--
c_st_arr2_vector_2(lowb) after 10 ns ,
c_st_arr2_vector_1(lowb) after 20 ns ,
c_st_arr2_vector_2(lowb) after 30 ns ,
c_st_arr2_vector_1(lowb) after 40 ns
when st_arr2_vector_select = 2 else
--
c_st_arr2_vector_1(lowb) after 5 ns
when st_arr2_vector_select = 3 else
--
c_st_arr2_vector_1(lowb) after 100 ns
when st_arr2_vector_select = 4 else
--
c_st_arr2_vector_2(lowb) after 10 ns ,
c_st_arr2_vector_1(lowb) after 20 ns ,
c_st_arr2_vector_2(lowb) after 30 ns ,
c_st_arr2_vector_1(lowb) after 40 ns
when st_arr2_vector_select = 5 else
--
-- Last transaction above is marked
c_st_arr2_vector_1(lowb) after 40 ns ;
--
CHG10 :
process
variable correct : boolean ;
begin
case s_st_arr2_cnt is
when 0
=> null ;
-- s_st_arr2(highb,false) <=
-- c_st_arr2_2(highb,false) after 10 ns,
-- c_st_arr2_1(highb,false) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2(highb,false) =
c_st_arr2_2(highb,false) and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_1(highb,false) and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00388.P10" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr2_select <= transport 2 ;
-- s_st_arr2(highb,false) <=
-- c_st_arr2_2(highb,false) after 10 ns ,
-- c_st_arr2_1(highb,false) after 20 ns ,
-- c_st_arr2_2(highb,false) after 30 ns ,
-- c_st_arr2_1(highb,false) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2(highb,false) =
c_st_arr2_2(highb,false) and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
st_arr2_select <= transport 3 ;
-- s_st_arr2(highb,false) <=
-- c_st_arr2_1(highb,false) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_1(highb,false) and
(s_st_arr2_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00388" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_select <= transport 4 ;
-- s_st_arr2(highb,false) <=
-- c_st_arr2_1(highb,false) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_1(highb,false) and
(s_st_arr2_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00388" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_arr2_select <= transport 5 ;
-- s_st_arr2(highb,false) <=
-- c_st_arr2_2(highb,false) after 10 ns ,
-- c_st_arr2_1(highb,false) after 20 ns ,
-- c_st_arr2_2(highb,false) after 30 ns ,
-- c_st_arr2_1(highb,false) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_2(highb,false) and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00388" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_arr2(highb,false) <=
-- c_st_arr2_1(highb,false) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_1(highb,false) and
(s_st_arr2_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_1(highb,false) and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00388" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00388" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_arr2_savt <= transport Std.Standard.Now ;
chk_st_arr2 <= transport s_st_arr2_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr2_cnt <= transport s_st_arr2_cnt + 1 ;
wait until (not s_st_arr2(highb,false)'Quiet) and
(s_st_arr2_savt /= Std.Standard.Now) ;
--
end process CHG10 ;
--
PGEN_CHKP_10 :
process ( chk_st_arr2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Inertial transactions completed entirely",
chk_st_arr2 = 8 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
--
s_st_arr2(highb,false) <=
c_st_arr2_2(highb,false) after 10 ns,
c_st_arr2_1(highb,false) after 20 ns
when st_arr2_select = 1 else
--
c_st_arr2_2(highb,false) after 10 ns ,
c_st_arr2_1(highb,false) after 20 ns ,
c_st_arr2_2(highb,false) after 30 ns ,
c_st_arr2_1(highb,false) after 40 ns
when st_arr2_select = 2 else
--
c_st_arr2_1(highb,false) after 5 ns
when st_arr2_select = 3 else
--
c_st_arr2_1(highb,false) after 100 ns
when st_arr2_select = 4 else
--
c_st_arr2_2(highb,false) after 10 ns ,
c_st_arr2_1(highb,false) after 20 ns ,
c_st_arr2_2(highb,false) after 30 ns ,
c_st_arr2_1(highb,false) after 40 ns
when st_arr2_select = 5 else
--
-- Last transaction above is marked
c_st_arr2_1(highb,false) after 40 ns ;
--
end ARCH00388 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00388_Test_Bench is
signal s_st_boolean_vector : st_boolean_vector
:= c_st_boolean_vector_1 ;
signal s_st_severity_level_vector : st_severity_level_vector
:= c_st_severity_level_vector_1 ;
signal s_st_string : st_string
:= c_st_string_1 ;
signal s_st_enum1_vector : st_enum1_vector
:= c_st_enum1_vector_1 ;
signal s_st_integer_vector : st_integer_vector
:= c_st_integer_vector_1 ;
signal s_st_time_vector : st_time_vector
:= c_st_time_vector_1 ;
signal s_st_real_vector : st_real_vector
:= c_st_real_vector_1 ;
signal s_st_rec1_vector : st_rec1_vector
:= c_st_rec1_vector_1 ;
signal s_st_arr2_vector : st_arr2_vector
:= c_st_arr2_vector_1 ;
signal s_st_arr2 : st_arr2
:= c_st_arr2_1 ;
--
end ENT00388_Test_Bench ;
--
--
architecture ARCH00388_Test_Bench of ENT00388_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_boolean_vector : inout st_boolean_vector
; s_st_severity_level_vector : inout st_severity_level_vector
; s_st_string : inout st_string
; s_st_enum1_vector : inout st_enum1_vector
; s_st_integer_vector : inout st_integer_vector
; s_st_time_vector : inout st_time_vector
; s_st_real_vector : inout st_real_vector
; s_st_rec1_vector : inout st_rec1_vector
; s_st_arr2_vector : inout st_arr2_vector
; s_st_arr2 : inout st_arr2
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00388 ( ARCH00388 ) ;
begin
CIS1 : UUT
port map (
s_st_boolean_vector
, s_st_severity_level_vector
, s_st_string
, s_st_enum1_vector
, s_st_integer_vector
, s_st_time_vector
, s_st_real_vector
, s_st_rec1_vector
, s_st_arr2_vector
, s_st_arr2
)
;
end block L1 ;
end ARCH00388_Test_Bench ;
| gpl-3.0 | 150bdcf94b2f43544cfb64bad3b27c30 | 0.514635 | 3.502752 | false | false | false | false |
TWW12/lzw | final_project_sim/lzw/lzw.srcs/sim_1/imports/temp/dictionary_block_tb.vhd | 1 | 3,115 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity dictionary_block_tb is
end dictionary_block_tb;
architecture Behavioral of dictionary_block_tb is
signal clk : std_logic;
signal rst : std_logic;
signal start_search : std_logic := '0';
signal search_entry : std_logic_vector(19 downto 0);
signal wr_en : std_logic := '0';
signal wr_entry : std_logic_vector(19 downto 0) := x"00000";
signal prefix : std_logic_vector(11 downto 0);
signal entry_found : std_logic;
signal search_completed : std_logic;
signal search_prefix : std_logic_vector(11 downto 0) := x"000";
signal search_char : std_logic_vector(7 downto 0) := x"00";
begin
search_entry(19 downto 8) <= search_prefix;
search_entry(7 downto 0) <= search_char;
UUT : entity work.dictionary_4
port map(
clk => clk,
rst => rst,
start_search => start_search,
search_entry => search_entry,
wr_en => wr_en,
wr_entry => wr_entry,
prefix => prefix,
entry_found => entry_found,
search_completed => search_completed);
--Clock generation
process
begin
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
end process;
--Actual testing
process
begin
--hold reset for 3 cycles
rst <= '1';
wait for 30 ns;
rst <= '0';
wait for 10 ns;
--first search for an entry that shouldnt exist
search_prefix <= x"001";
search_char <= x"30";
start_search <= '1';
wait for 10 ns;
start_search <= '0';
--wait for search to complete
wait until search_completed = '1';
assert entry_found = '0' report "Entry found asserted for non-existant entry." severity failure;
wait for 10 ns;
--Check all dictionary entries
for i in 1 to 255 loop
search_prefix <= x"000";
search_char <= std_logic_vector(to_unsigned(i,8));
start_search <= '1';
wait for 10 ns;
start_search <= '0';
wait until search_completed = '1';
assert entry_found = '1' report "Entry not found." severity warning;
assert prefix = std_logic_vector(to_unsigned(i,12)) report "Incorrect resulting prefix." severity warning;
wait for 10 ns;
end loop;
--Write an entry to the dictionary
wr_entry <= x"00130"; --prefix = 0x001, char = 0x30
wr_en <= '1';
wait for 10 ns;
wr_en <= '0';
--Now try looking for it!
search_prefix <= x"001";
search_char <= x"30";
start_search <= '1';
wait for 10 ns;
start_search <= '0';
wait for 10 ns;
wait until search_completed = '1';
assert entry_found = '1' report "Newly written entry not found" severity failure;
report "Testbench completed." severity note;
wait;
end process;
end Behavioral;
| unlicense | 12efb4b8a622d1e04ac30c1e46b950ec | 0.551525 | 3.953046 | false | false | false | false |
grwlf/vsim | vhdl_ct/pro000024.vhd | 1 | 72,452 | -- Prosoft VHDL tests.
--
-- Copyright (C) 2011 Prosoft.
--
-- Author: Zefirov, Karavaev.
--
-- This is a set of simplest tests for isolated tests of VHDL features.
--
-- Nothing more than standard package should be required.
--
-- Categories: entity, architecture, process, type, subtype, case, enumerations, array, for-loop, function, Attributes-of-the-array-type-or-objects-of-the-array-type
use work.std_logic_1164_for_tst.all;
entity ENT00024_Test_Bench is
end ENT00024_Test_Bench;
architecture ARCH00024_Test_Bench of ENT00024_Test_Bench is
subtype byte is bit_vector(0 to 7);
type IntArray is array (integer range <>) of integer;
type ArrayOfIntArray is array (1 to 5) of IntArray(1 to 6);
type ArrayOfIntArray_ForRange is array (1 to 6) of IntArray(-3 to 20);
type ArrayOfArrayOfIntArray_ForRange is array (1 to 12) of ArrayOfIntArray_ForRange;
type ArrayOfArrayOfIntArray is array (1 to 12) of ArrayOfIntArray;
type std_array is array (0 to 3) of std_logic;
signal I_sa : std_array := "1010";
type enum is (a_v, b_v, c_v, d_v, e_v, f_v);
type rec is record
f1 : integer;
f2 : boolean;
f3 : bit;
end record;
type BooleanVector is array (integer range <>) of boolean;
type cond_type is array (1 to 12) of BooleanVector(1 to 8);
type ArrayOfBooleanVector is array (1 to 12) of BooleanVector(1 to 6);
type StateType is (init, assign, analize, waiting);
signal state : StateType := init;
type std_logic_array_dem_5 is array (integer range <>, integer range <>, integer range <>, integer range <>, integer range <>) of std_logic;
type bit_array_dem_5 is array (integer range <>, integer range <>, integer range <>, integer range <>, integer range <>) of bit;
type integer_array_dem_5 is array (integer range <>, integer range <>, integer range <>, integer range <>, integer range <>) of integer;
type boolean_array_dem_5 is array (integer range <>, integer range <>, integer range <>, integer range <>, integer range <>) of boolean;
type enum_array_dem_5 is array (integer range <>, integer range <>, integer range <>, integer range <>, integer range <>) of enum;
type rec_array_dem_5 is array (integer range <>, integer range <>, integer range <>, integer range <>, integer range <>) of rec;
subtype std_logic_array_dem_5_sub is std_logic_array_dem_5(1 to 3, 7 downto 0, 1 downto -1, 10 to 20, -3 to 3);
type bit_array_dem_5_boarded is array (1 to 3, 7 downto 0, 1 downto -1, 10 to 20, -3 to 3) of bit;
subtype integer_array_dem_5_sub is integer_array_dem_5 (1 to 3, 7 downto 0, 1 downto -1, 10 to 20, -3 to 3);
subtype boolean_array_dem_5_sub is boolean_array_dem_5 (1 to 3, 7 downto 0, 1 downto -1, 10 to 20, -3 to 3);
type enum_array_dem_5_boarded is array (1 to 3, 7 downto 0, 1 downto -1, 10 to 20, -3 to 3) of enum;
subtype rec_array_dem_5_sub is rec_array_dem_5 (1 to 3, 7 downto 0, 1 downto -1, 10 to 20, -3 to 3);
signal stdl_a_d5 : std_logic_array_dem_5(1 to 3, 7 downto 0, 1 downto -1, 10 to 20, -3 to 3);
signal bit_a_d5 : bit_array_dem_5 (1 to 3, 7 downto 0, 1 downto -1, 10 to 20, -3 to 3);
signal int_a_d5 : integer_array_dem_5 (1 to 3, 7 downto 0, 1 downto -1, 10 to 20, -3 to 3);
signal bool_a_d5 : boolean_array_dem_5 (1 to 3, 7 downto 0, 1 downto -1, 10 to 20, -3 to 3);
signal enum_a_d5 : enum_array_dem_5 (1 to 3, 7 downto 0, 1 downto -1, 10 to 20, -3 to 3);
signal rec_a_d5 : rec_array_dem_5 (1 to 3, 7 downto 0, 1 downto -1, 10 to 20, -3 to 3);
function all100 (i : IntArray) return boolean is
variable v : IntArray(i'range);
variable r : boolean;
begin
v := i;
r := true;
l1: for i in v'range loop
r := r and (v(i) = 100);
end loop;
return r;
end function;
begin
process (state)
variable vv : ArrayOfArrayOfIntArray_ForRange := (others => (others => (others => 100)));
variable vv_reverse : ArrayOfArrayOfIntArray_ForRange := (others => (others => (others => 100)));
variable int : ArrayOfArrayOfIntArray := (others => (others => (others => 0)));
variable bool : ArrayOfBooleanVector := (others => (others => false));
variable cond : cond_type := (others => (others => false));
begin
case state is
when init =>
state <= assign;
when assign =>
state <= analize;
-- std_logic_array
int(1)(1)(1) := stdl_a_d5'Low;
int(1)(1)(2) := stdl_a_d5'Low(1);
int(1)(1)(3) := stdl_a_d5'Low(2);
int(1)(1)(4) := stdl_a_d5'Low(3);
int(1)(1)(5) := stdl_a_d5'Low(4);
int(1)(1)(6) := stdl_a_d5'Low(5);
int(1)(2)(1) := stdl_a_d5'High;
int(1)(2)(2) := stdl_a_d5'High(1);
int(1)(2)(3) := stdl_a_d5'High(2);
int(1)(2)(4) := stdl_a_d5'High(3);
int(1)(2)(5) := stdl_a_d5'High(4);
int(1)(2)(6) := stdl_a_d5'High(5);
int(1)(3)(1) := stdl_a_d5'Left;
int(1)(3)(2) := stdl_a_d5'Left(1);
int(1)(3)(3) := stdl_a_d5'Left(2);
int(1)(3)(4) := stdl_a_d5'Left(3);
int(1)(3)(5) := stdl_a_d5'Left(4);
int(1)(3)(6) := stdl_a_d5'Left(5);
int(1)(4)(1) := stdl_a_d5'Right;
int(1)(4)(2) := stdl_a_d5'Right(1);
int(1)(4)(3) := stdl_a_d5'Right(2);
int(1)(4)(4) := stdl_a_d5'Right(3);
int(1)(4)(5) := stdl_a_d5'Right(4);
int(1)(4)(6) := stdl_a_d5'Right(5);
int(1)(5)(1) := stdl_a_d5'Length;
int(1)(5)(2) := stdl_a_d5'Length(1);
int(1)(5)(3) := stdl_a_d5'Length(2);
int(1)(5)(4) := stdl_a_d5'Length(3);
int(1)(5)(5) := stdl_a_d5'Length(4);
int(1)(5)(6) := stdl_a_d5'Length(5);
int(2)(1)(1) := std_logic_array_dem_5_sub'Low;
int(2)(1)(2) := std_logic_array_dem_5_sub'Low(1);
int(2)(1)(3) := std_logic_array_dem_5_sub'Low(2);
int(2)(1)(4) := std_logic_array_dem_5_sub'Low(3);
int(2)(1)(5) := std_logic_array_dem_5_sub'Low(4);
int(2)(1)(6) := std_logic_array_dem_5_sub'Low(5);
int(2)(2)(1) := std_logic_array_dem_5_sub'High;
int(2)(2)(2) := std_logic_array_dem_5_sub'High(1);
int(2)(2)(3) := std_logic_array_dem_5_sub'High(2);
int(2)(2)(4) := std_logic_array_dem_5_sub'High(3);
int(2)(2)(5) := std_logic_array_dem_5_sub'High(4);
int(2)(2)(6) := std_logic_array_dem_5_sub'High(5);
int(2)(3)(1) := std_logic_array_dem_5_sub'Left;
int(2)(3)(2) := std_logic_array_dem_5_sub'Left(1);
int(2)(3)(3) := std_logic_array_dem_5_sub'Left(2);
int(2)(3)(4) := std_logic_array_dem_5_sub'Left(3);
int(2)(3)(5) := std_logic_array_dem_5_sub'Left(4);
int(2)(3)(6) := std_logic_array_dem_5_sub'Left(5);
int(2)(4)(1) := std_logic_array_dem_5_sub'Right;
int(2)(4)(2) := std_logic_array_dem_5_sub'Right(1);
int(2)(4)(3) := std_logic_array_dem_5_sub'Right(2);
int(2)(4)(4) := std_logic_array_dem_5_sub'Right(3);
int(2)(4)(5) := std_logic_array_dem_5_sub'Right(4);
int(2)(4)(6) := std_logic_array_dem_5_sub'Right(5);
int(2)(5)(1) := std_logic_array_dem_5_sub'Length;
int(2)(5)(2) := std_logic_array_dem_5_sub'Length(1);
int(2)(5)(3) := std_logic_array_dem_5_sub'Length(2);
int(2)(5)(4) := std_logic_array_dem_5_sub'Length(3);
int(2)(5)(5) := std_logic_array_dem_5_sub'Length(4);
int(2)(5)(6) := std_logic_array_dem_5_sub'Length(5);
bool(1)(1) := stdl_a_d5'Ascending;
bool(1)(2) := stdl_a_d5'Ascending(1);
bool(1)(3) := stdl_a_d5'Ascending(2);
bool(1)(4) := stdl_a_d5'Ascending(3);
bool(1)(5) := stdl_a_d5'Ascending(4);
bool(1)(6) := stdl_a_d5'Ascending(5);
bool(2)(1) := std_logic_array_dem_5_sub'Ascending;
bool(2)(2) := std_logic_array_dem_5_sub'Ascending(1);
bool(2)(3) := std_logic_array_dem_5_sub'Ascending(2);
bool(2)(4) := std_logic_array_dem_5_sub'Ascending(3);
bool(2)(5) := std_logic_array_dem_5_sub'Ascending(4);
bool(2)(6) := std_logic_array_dem_5_sub'Ascending(5);
-- bit_array
int(3)(1)(1) := bit_a_d5'Low;
int(3)(1)(2) := bit_a_d5'Low(1);
int(3)(1)(3) := bit_a_d5'Low(2);
int(3)(1)(4) := bit_a_d5'Low(3);
int(3)(1)(5) := bit_a_d5'Low(4);
int(3)(1)(6) := bit_a_d5'Low(5);
int(3)(2)(1) := bit_a_d5'High;
int(3)(2)(2) := bit_a_d5'High(1);
int(3)(2)(3) := bit_a_d5'High(2);
int(3)(2)(4) := bit_a_d5'High(3);
int(3)(2)(5) := bit_a_d5'High(4);
int(3)(2)(6) := bit_a_d5'High(5);
int(3)(3)(1) := bit_a_d5'Left;
int(3)(3)(2) := bit_a_d5'Left(1);
int(3)(3)(3) := bit_a_d5'Left(2);
int(3)(3)(4) := bit_a_d5'Left(3);
int(3)(3)(5) := bit_a_d5'Left(4);
int(3)(3)(6) := bit_a_d5'Left(5);
int(3)(4)(1) := bit_a_d5'Right;
int(3)(4)(2) := bit_a_d5'Right(1);
int(3)(4)(3) := bit_a_d5'Right(2);
int(3)(4)(4) := bit_a_d5'Right(3);
int(3)(4)(5) := bit_a_d5'Right(4);
int(3)(4)(6) := bit_a_d5'Right(5);
int(3)(5)(1) := bit_a_d5'Length;
int(3)(5)(2) := bit_a_d5'Length(1);
int(3)(5)(3) := bit_a_d5'Length(2);
int(3)(5)(4) := bit_a_d5'Length(3);
int(3)(5)(5) := bit_a_d5'Length(4);
int(3)(5)(6) := bit_a_d5'Length(5);
int(4)(1)(1) := bit_array_dem_5_boarded'Low;
int(4)(1)(2) := bit_array_dem_5_boarded'Low(1);
int(4)(1)(3) := bit_array_dem_5_boarded'Low(2);
int(4)(1)(4) := bit_array_dem_5_boarded'Low(3);
int(4)(1)(5) := bit_array_dem_5_boarded'Low(4);
int(4)(1)(6) := bit_array_dem_5_boarded'Low(5);
int(4)(2)(1) := bit_array_dem_5_boarded'High;
int(4)(2)(2) := bit_array_dem_5_boarded'High(1);
int(4)(2)(3) := bit_array_dem_5_boarded'High(2);
int(4)(2)(4) := bit_array_dem_5_boarded'High(3);
int(4)(2)(5) := bit_array_dem_5_boarded'High(4);
int(4)(2)(6) := bit_array_dem_5_boarded'High(5);
int(4)(3)(1) := bit_array_dem_5_boarded'Left;
int(4)(3)(2) := bit_array_dem_5_boarded'Left(1);
int(4)(3)(3) := bit_array_dem_5_boarded'Left(2);
int(4)(3)(4) := bit_array_dem_5_boarded'Left(3);
int(4)(3)(5) := bit_array_dem_5_boarded'Left(4);
int(4)(3)(6) := bit_array_dem_5_boarded'Left(5);
int(4)(4)(1) := bit_array_dem_5_boarded'Right;
int(4)(4)(2) := bit_array_dem_5_boarded'Right(1);
int(4)(4)(3) := bit_array_dem_5_boarded'Right(2);
int(4)(4)(4) := bit_array_dem_5_boarded'Right(3);
int(4)(4)(5) := bit_array_dem_5_boarded'Right(4);
int(4)(4)(6) := bit_array_dem_5_boarded'Right(5);
int(4)(5)(1) := bit_array_dem_5_boarded'Length;
int(4)(5)(2) := bit_array_dem_5_boarded'Length(1);
int(4)(5)(3) := bit_array_dem_5_boarded'Length(2);
int(4)(5)(4) := bit_array_dem_5_boarded'Length(3);
int(4)(5)(5) := bit_array_dem_5_boarded'Length(4);
int(4)(5)(6) := bit_array_dem_5_boarded'Length(5);
bool(3)(1) := bit_a_d5'Ascending;
bool(3)(2) := bit_a_d5'Ascending(1);
bool(3)(3) := bit_a_d5'Ascending(2);
bool(3)(4) := bit_a_d5'Ascending(3);
bool(3)(5) := bit_a_d5'Ascending(4);
bool(3)(6) := bit_a_d5'Ascending(5);
bool(4)(1) := bit_array_dem_5_boarded'Ascending;
bool(4)(2) := bit_array_dem_5_boarded'Ascending(1);
bool(4)(3) := bit_array_dem_5_boarded'Ascending(2);
bool(4)(4) := bit_array_dem_5_boarded'Ascending(3);
bool(4)(5) := bit_array_dem_5_boarded'Ascending(4);
bool(4)(6) := bit_array_dem_5_boarded'Ascending(5);
-- integer_array
int(5)(1)(1) := int_a_d5'Low;
int(5)(1)(2) := int_a_d5'Low(1);
int(5)(1)(3) := int_a_d5'Low(2);
int(5)(1)(4) := int_a_d5'Low(3);
int(5)(1)(5) := int_a_d5'Low(4);
int(5)(1)(6) := int_a_d5'Low(5);
int(5)(2)(1) := int_a_d5'High;
int(5)(2)(2) := int_a_d5'High(1);
int(5)(2)(3) := int_a_d5'High(2);
int(5)(2)(4) := int_a_d5'High(3);
int(5)(2)(5) := int_a_d5'High(4);
int(5)(2)(6) := int_a_d5'High(5);
int(5)(3)(1) := int_a_d5'Left;
int(5)(3)(2) := int_a_d5'Left(1);
int(5)(3)(3) := int_a_d5'Left(2);
int(5)(3)(4) := int_a_d5'Left(3);
int(5)(3)(5) := int_a_d5'Left(4);
int(5)(3)(6) := int_a_d5'Left(5);
int(5)(4)(1) := int_a_d5'Right;
int(5)(4)(2) := int_a_d5'Right(1);
int(5)(4)(3) := int_a_d5'Right(2);
int(5)(4)(4) := int_a_d5'Right(3);
int(5)(4)(5) := int_a_d5'Right(4);
int(5)(4)(6) := int_a_d5'Right(5);
int(5)(5)(1) := int_a_d5'Length;
int(5)(5)(2) := int_a_d5'Length(1);
int(5)(5)(3) := int_a_d5'Length(2);
int(5)(5)(4) := int_a_d5'Length(3);
int(5)(5)(5) := int_a_d5'Length(4);
int(5)(5)(6) := int_a_d5'Length(5);
int(6)(1)(1) := integer_array_dem_5_sub'Low;
int(6)(1)(2) := integer_array_dem_5_sub'Low(1);
int(6)(1)(3) := integer_array_dem_5_sub'Low(2);
int(6)(1)(4) := integer_array_dem_5_sub'Low(3);
int(6)(1)(5) := integer_array_dem_5_sub'Low(4);
int(6)(1)(6) := integer_array_dem_5_sub'Low(5);
int(6)(2)(1) := integer_array_dem_5_sub'High;
int(6)(2)(2) := integer_array_dem_5_sub'High(1);
int(6)(2)(3) := integer_array_dem_5_sub'High(2);
int(6)(2)(4) := integer_array_dem_5_sub'High(3);
int(6)(2)(5) := integer_array_dem_5_sub'High(4);
int(6)(2)(6) := integer_array_dem_5_sub'High(5);
int(6)(3)(1) := integer_array_dem_5_sub'Left;
int(6)(3)(2) := integer_array_dem_5_sub'Left(1);
int(6)(3)(3) := integer_array_dem_5_sub'Left(2);
int(6)(3)(4) := integer_array_dem_5_sub'Left(3);
int(6)(3)(5) := integer_array_dem_5_sub'Left(4);
int(6)(3)(6) := integer_array_dem_5_sub'Left(5);
int(6)(4)(1) := integer_array_dem_5_sub'Right;
int(6)(4)(2) := integer_array_dem_5_sub'Right(1);
int(6)(4)(3) := integer_array_dem_5_sub'Right(2);
int(6)(4)(4) := integer_array_dem_5_sub'Right(3);
int(6)(4)(5) := integer_array_dem_5_sub'Right(4);
int(6)(4)(6) := integer_array_dem_5_sub'Right(5);
int(6)(5)(1) := integer_array_dem_5_sub'Length;
int(6)(5)(2) := integer_array_dem_5_sub'Length(1);
int(6)(5)(3) := integer_array_dem_5_sub'Length(2);
int(6)(5)(4) := integer_array_dem_5_sub'Length(3);
int(6)(5)(5) := integer_array_dem_5_sub'Length(4);
int(6)(5)(6) := integer_array_dem_5_sub'Length(5);
bool(5)(1) := int_a_d5'Ascending;
bool(5)(2) := int_a_d5'Ascending(1);
bool(5)(3) := int_a_d5'Ascending(2);
bool(5)(4) := int_a_d5'Ascending(3);
bool(5)(5) := int_a_d5'Ascending(4);
bool(5)(6) := int_a_d5'Ascending(5);
bool(6)(1) := integer_array_dem_5_sub'Ascending;
bool(6)(2) := integer_array_dem_5_sub'Ascending(1);
bool(6)(3) := integer_array_dem_5_sub'Ascending(2);
bool(6)(4) := integer_array_dem_5_sub'Ascending(3);
bool(6)(5) := integer_array_dem_5_sub'Ascending(4);
bool(6)(6) := integer_array_dem_5_sub'Ascending(5);
-- boolean_array
int(7)(1)(1) := bool_a_d5'Low;
int(7)(1)(2) := bool_a_d5'Low(1);
int(7)(1)(3) := bool_a_d5'Low(2);
int(7)(1)(4) := bool_a_d5'Low(3);
int(7)(1)(5) := bool_a_d5'Low(4);
int(7)(1)(6) := bool_a_d5'Low(5);
int(7)(2)(1) := bool_a_d5'High;
int(7)(2)(2) := bool_a_d5'High(1);
int(7)(2)(3) := bool_a_d5'High(2);
int(7)(2)(4) := bool_a_d5'High(3);
int(7)(2)(5) := bool_a_d5'High(4);
int(7)(2)(6) := bool_a_d5'High(5);
int(7)(3)(1) := bool_a_d5'Left;
int(7)(3)(2) := bool_a_d5'Left(1);
int(7)(3)(3) := bool_a_d5'Left(2);
int(7)(3)(4) := bool_a_d5'Left(3);
int(7)(3)(5) := bool_a_d5'Left(4);
int(7)(3)(6) := bool_a_d5'Left(5);
int(7)(4)(1) := bool_a_d5'Right;
int(7)(4)(2) := bool_a_d5'Right(1);
int(7)(4)(3) := bool_a_d5'Right(2);
int(7)(4)(4) := bool_a_d5'Right(3);
int(7)(4)(5) := bool_a_d5'Right(4);
int(7)(4)(6) := bool_a_d5'Right(5);
int(7)(5)(1) := bool_a_d5'Length;
int(7)(5)(2) := bool_a_d5'Length(1);
int(7)(5)(3) := bool_a_d5'Length(2);
int(7)(5)(4) := bool_a_d5'Length(3);
int(7)(5)(5) := bool_a_d5'Length(4);
int(7)(5)(6) := bool_a_d5'Length(5);
int(8)(1)(1) := boolean_array_dem_5_sub'Low;
int(8)(1)(2) := boolean_array_dem_5_sub'Low(1);
int(8)(1)(3) := boolean_array_dem_5_sub'Low(2);
int(8)(1)(4) := boolean_array_dem_5_sub'Low(3);
int(8)(1)(5) := boolean_array_dem_5_sub'Low(4);
int(8)(1)(6) := boolean_array_dem_5_sub'Low(5);
int(8)(2)(1) := boolean_array_dem_5_sub'High;
int(8)(2)(2) := boolean_array_dem_5_sub'High(1);
int(8)(2)(3) := boolean_array_dem_5_sub'High(2);
int(8)(2)(4) := boolean_array_dem_5_sub'High(3);
int(8)(2)(5) := boolean_array_dem_5_sub'High(4);
int(8)(2)(6) := boolean_array_dem_5_sub'High(5);
int(8)(3)(1) := boolean_array_dem_5_sub'Left;
int(8)(3)(2) := boolean_array_dem_5_sub'Left(1);
int(8)(3)(3) := boolean_array_dem_5_sub'Left(2);
int(8)(3)(4) := boolean_array_dem_5_sub'Left(3);
int(8)(3)(5) := boolean_array_dem_5_sub'Left(4);
int(8)(3)(6) := boolean_array_dem_5_sub'Left(5);
int(8)(4)(1) := boolean_array_dem_5_sub'Right;
int(8)(4)(2) := boolean_array_dem_5_sub'Right(1);
int(8)(4)(3) := boolean_array_dem_5_sub'Right(2);
int(8)(4)(4) := boolean_array_dem_5_sub'Right(3);
int(8)(4)(5) := boolean_array_dem_5_sub'Right(4);
int(8)(4)(6) := boolean_array_dem_5_sub'Right(5);
int(8)(5)(1) := boolean_array_dem_5_sub'Length;
int(8)(5)(2) := boolean_array_dem_5_sub'Length(1);
int(8)(5)(3) := boolean_array_dem_5_sub'Length(2);
int(8)(5)(4) := boolean_array_dem_5_sub'Length(3);
int(8)(5)(5) := boolean_array_dem_5_sub'Length(4);
int(8)(5)(6) := boolean_array_dem_5_sub'Length(5);
bool(7)(1) := bool_a_d5'Ascending;
bool(7)(2) := bool_a_d5'Ascending(1);
bool(7)(3) := bool_a_d5'Ascending(2);
bool(7)(4) := bool_a_d5'Ascending(3);
bool(7)(5) := bool_a_d5'Ascending(4);
bool(7)(6) := bool_a_d5'Ascending(5);
bool(8)(1) := boolean_array_dem_5_sub'Ascending;
bool(8)(2) := boolean_array_dem_5_sub'Ascending(1);
bool(8)(3) := boolean_array_dem_5_sub'Ascending(2);
bool(8)(4) := boolean_array_dem_5_sub'Ascending(3);
bool(8)(5) := boolean_array_dem_5_sub'Ascending(4);
bool(8)(6) := boolean_array_dem_5_sub'Ascending(5);
-- enum_array
int(9)(1)(1) := enum_a_d5'Low;
int(9)(1)(2) := enum_a_d5'Low(1);
int(9)(1)(3) := enum_a_d5'Low(2);
int(9)(1)(4) := enum_a_d5'Low(3);
int(9)(1)(5) := enum_a_d5'Low(4);
int(9)(1)(6) := enum_a_d5'Low(5);
int(9)(2)(1) := enum_a_d5'High;
int(9)(2)(2) := enum_a_d5'High(1);
int(9)(2)(3) := enum_a_d5'High(2);
int(9)(2)(4) := enum_a_d5'High(3);
int(9)(2)(5) := enum_a_d5'High(4);
int(9)(2)(6) := enum_a_d5'High(5);
int(9)(3)(1) := enum_a_d5'Left;
int(9)(3)(2) := enum_a_d5'Left(1);
int(9)(3)(3) := enum_a_d5'Left(2);
int(9)(3)(4) := enum_a_d5'Left(3);
int(9)(3)(5) := enum_a_d5'Left(4);
int(9)(3)(6) := enum_a_d5'Left(5);
int(9)(4)(1) := enum_a_d5'Right;
int(9)(4)(2) := enum_a_d5'Right(1);
int(9)(4)(3) := enum_a_d5'Right(2);
int(9)(4)(4) := enum_a_d5'Right(3);
int(9)(4)(5) := enum_a_d5'Right(4);
int(9)(4)(6) := enum_a_d5'Right(5);
int(9)(5)(1) := enum_a_d5'Length;
int(9)(5)(2) := enum_a_d5'Length(1);
int(9)(5)(3) := enum_a_d5'Length(2);
int(9)(5)(4) := enum_a_d5'Length(3);
int(9)(5)(5) := enum_a_d5'Length(4);
int(9)(5)(6) := enum_a_d5'Length(5);
int(10)(1)(1) := enum_array_dem_5_boarded'Low;
int(10)(1)(2) := enum_array_dem_5_boarded'Low(1);
int(10)(1)(3) := enum_array_dem_5_boarded'Low(2);
int(10)(1)(4) := enum_array_dem_5_boarded'Low(3);
int(10)(1)(5) := enum_array_dem_5_boarded'Low(4);
int(10)(1)(6) := enum_array_dem_5_boarded'Low(5);
int(10)(2)(1) := enum_array_dem_5_boarded'High;
int(10)(2)(2) := enum_array_dem_5_boarded'High(1);
int(10)(2)(3) := enum_array_dem_5_boarded'High(2);
int(10)(2)(4) := enum_array_dem_5_boarded'High(3);
int(10)(2)(5) := enum_array_dem_5_boarded'High(4);
int(10)(2)(6) := enum_array_dem_5_boarded'High(5);
int(10)(3)(1) := enum_array_dem_5_boarded'Left;
int(10)(3)(2) := enum_array_dem_5_boarded'Left(1);
int(10)(3)(3) := enum_array_dem_5_boarded'Left(2);
int(10)(3)(4) := enum_array_dem_5_boarded'Left(3);
int(10)(3)(5) := enum_array_dem_5_boarded'Left(4);
int(10)(3)(6) := enum_array_dem_5_boarded'Left(5);
int(10)(4)(1) := enum_array_dem_5_boarded'Right;
int(10)(4)(2) := enum_array_dem_5_boarded'Right(1);
int(10)(4)(3) := enum_array_dem_5_boarded'Right(2);
int(10)(4)(4) := enum_array_dem_5_boarded'Right(3);
int(10)(4)(5) := enum_array_dem_5_boarded'Right(4);
int(10)(4)(6) := enum_array_dem_5_boarded'Right(5);
int(10)(5)(1) := enum_array_dem_5_boarded'Length;
int(10)(5)(2) := enum_array_dem_5_boarded'Length(1);
int(10)(5)(3) := enum_array_dem_5_boarded'Length(2);
int(10)(5)(4) := enum_array_dem_5_boarded'Length(3);
int(10)(5)(5) := enum_array_dem_5_boarded'Length(4);
int(10)(5)(6) := enum_array_dem_5_boarded'Length(5);
bool(9)(1) := enum_a_d5'Ascending;
bool(9)(2) := enum_a_d5'Ascending(1);
bool(9)(3) := enum_a_d5'Ascending(2);
bool(9)(4) := enum_a_d5'Ascending(3);
bool(9)(5) := enum_a_d5'Ascending(4);
bool(9)(6) := enum_a_d5'Ascending(5);
bool(10)(1) := enum_array_dem_5_boarded'Ascending;
bool(10)(2) := enum_array_dem_5_boarded'Ascending(1);
bool(10)(3) := enum_array_dem_5_boarded'Ascending(2);
bool(10)(4) := enum_array_dem_5_boarded'Ascending(3);
bool(10)(5) := enum_array_dem_5_boarded'Ascending(4);
bool(10)(6) := enum_array_dem_5_boarded'Ascending(5);
-- rec_array
int(11)(1)(1) := rec_a_d5'Low;
int(11)(1)(2) := rec_a_d5'Low(1);
int(11)(1)(3) := rec_a_d5'Low(2);
int(11)(1)(4) := rec_a_d5'Low(3);
int(11)(1)(5) := rec_a_d5'Low(4);
int(11)(1)(6) := rec_a_d5'Low(5);
int(11)(2)(1) := rec_a_d5'High;
int(11)(2)(2) := rec_a_d5'High(1);
int(11)(2)(3) := rec_a_d5'High(2);
int(11)(2)(4) := rec_a_d5'High(3);
int(11)(2)(5) := rec_a_d5'High(4);
int(11)(2)(6) := rec_a_d5'High(5);
int(11)(3)(1) := rec_a_d5'Left;
int(11)(3)(2) := rec_a_d5'Left(1);
int(11)(3)(3) := rec_a_d5'Left(2);
int(11)(3)(4) := rec_a_d5'Left(3);
int(11)(3)(5) := rec_a_d5'Left(4);
int(11)(3)(6) := rec_a_d5'Left(5);
int(11)(4)(1) := rec_a_d5'Right;
int(11)(4)(2) := rec_a_d5'Right(1);
int(11)(4)(3) := rec_a_d5'Right(2);
int(11)(4)(4) := rec_a_d5'Right(3);
int(11)(4)(5) := rec_a_d5'Right(4);
int(11)(4)(6) := rec_a_d5'Right(5);
int(11)(5)(1) := rec_a_d5'Length;
int(11)(5)(2) := rec_a_d5'Length(1);
int(11)(5)(3) := rec_a_d5'Length(2);
int(11)(5)(4) := rec_a_d5'Length(3);
int(11)(5)(5) := rec_a_d5'Length(4);
int(11)(5)(6) := rec_a_d5'Length(5);
int(12)(1)(1) := rec_array_dem_5_sub'Low;
int(12)(1)(2) := rec_array_dem_5_sub'Low(1);
int(12)(1)(3) := rec_array_dem_5_sub'Low(2);
int(12)(1)(4) := rec_array_dem_5_sub'Low(3);
int(12)(1)(5) := rec_array_dem_5_sub'Low(4);
int(12)(1)(6) := rec_array_dem_5_sub'Low(5);
int(12)(2)(1) := rec_array_dem_5_sub'High;
int(12)(2)(2) := rec_array_dem_5_sub'High(1);
int(12)(2)(3) := rec_array_dem_5_sub'High(2);
int(12)(2)(4) := rec_array_dem_5_sub'High(3);
int(12)(2)(5) := rec_array_dem_5_sub'High(4);
int(12)(2)(6) := rec_array_dem_5_sub'High(5);
int(12)(3)(1) := rec_array_dem_5_sub'Left;
int(12)(3)(2) := rec_array_dem_5_sub'Left(1);
int(12)(3)(3) := rec_array_dem_5_sub'Left(2);
int(12)(3)(4) := rec_array_dem_5_sub'Left(3);
int(12)(3)(5) := rec_array_dem_5_sub'Left(4);
int(12)(3)(6) := rec_array_dem_5_sub'Left(5);
int(12)(4)(1) := rec_array_dem_5_sub'Right;
int(12)(4)(2) := rec_array_dem_5_sub'Right(1);
int(12)(4)(3) := rec_array_dem_5_sub'Right(2);
int(12)(4)(4) := rec_array_dem_5_sub'Right(3);
int(12)(4)(5) := rec_array_dem_5_sub'Right(4);
int(12)(4)(6) := rec_array_dem_5_sub'Right(5);
int(12)(5)(1) := rec_array_dem_5_sub'Length;
int(12)(5)(2) := rec_array_dem_5_sub'Length(1);
int(12)(5)(3) := rec_array_dem_5_sub'Length(2);
int(12)(5)(4) := rec_array_dem_5_sub'Length(3);
int(12)(5)(5) := rec_array_dem_5_sub'Length(4);
int(12)(5)(6) := rec_array_dem_5_sub'Length(5);
bool(11)(1) := rec_a_d5'Ascending;
bool(11)(2) := rec_a_d5'Ascending(1);
bool(11)(3) := rec_a_d5'Ascending(2);
bool(11)(4) := rec_a_d5'Ascending(3);
bool(11)(5) := rec_a_d5'Ascending(4);
bool(11)(6) := rec_a_d5'Ascending(5);
bool(12)(1) := rec_array_dem_5_sub'Ascending;
bool(12)(2) := rec_array_dem_5_sub'Ascending(1);
bool(12)(3) := rec_array_dem_5_sub'Ascending(2);
bool(12)(4) := rec_array_dem_5_sub'Ascending(3);
bool(12)(5) := rec_array_dem_5_sub'Ascending(4);
bool(12)(6) := rec_array_dem_5_sub'Ascending(5);
-- range
-- std_logic_array
l1_1: for i in stdl_a_d5'range loop vv(1)(1)(i) := i; end loop l1_1;
l1_2: for i in stdl_a_d5'range(1) loop vv(1)(2)(i) := i; end loop l1_2;
l1_3: for i in stdl_a_d5'range(2) loop vv(1)(3)(i) := i; end loop l1_3;
l1_4: for i in stdl_a_d5'range(3) loop vv(1)(4)(i) := i; end loop l1_4;
l1_5: for i in stdl_a_d5'range(4) loop vv(1)(5)(i) := i; end loop l1_5;
l1_6: for i in stdl_a_d5'range(5) loop vv(1)(6)(i) := i; end loop l1_6;
l2_1: for i in std_logic_array_dem_5_sub'range loop vv(2)(1)(i) := i; end loop l2_1;
l2_2: for i in std_logic_array_dem_5_sub'range(1) loop vv(2)(2)(i) := i; end loop l2_2;
l2_3: for i in std_logic_array_dem_5_sub'range(2) loop vv(2)(3)(i) := i; end loop l2_3;
l2_4: for i in std_logic_array_dem_5_sub'range(3) loop vv(2)(4)(i) := i; end loop l2_4;
l2_5: for i in std_logic_array_dem_5_sub'range(4) loop vv(2)(5)(i) := i; end loop l2_5;
l2_6: for i in std_logic_array_dem_5_sub'range(5) loop vv(2)(6)(i) := i; end loop l2_6;
lr1_1: for i in stdl_a_d5'Reverse_range loop vv_reverse(1)(1)(i) := i; end loop lr1_1;
lr1_2: for i in stdl_a_d5'Reverse_range(1) loop vv_reverse(1)(2)(i) := i; end loop lr1_2;
lr1_3: for i in stdl_a_d5'Reverse_range(2) loop vv_reverse(1)(3)(i) := i; end loop lr1_3;
lr1_4: for i in stdl_a_d5'Reverse_range(3) loop vv_reverse(1)(4)(i) := i; end loop lr1_4;
lr1_5: for i in stdl_a_d5'Reverse_range(4) loop vv_reverse(1)(5)(i) := i; end loop lr1_5;
lr1_6: for i in stdl_a_d5'Reverse_range(5) loop vv_reverse(1)(6)(i) := i; end loop lr1_6;
lr2_1: for i in std_logic_array_dem_5_sub'Reverse_range loop vv_reverse(2)(1)(i) := i; end loop lr2_1;
lr2_2: for i in std_logic_array_dem_5_sub'Reverse_range(1) loop vv_reverse(2)(2)(i) := i; end loop lr2_2;
lr2_3: for i in std_logic_array_dem_5_sub'Reverse_range(2) loop vv_reverse(2)(3)(i) := i; end loop lr2_3;
lr2_4: for i in std_logic_array_dem_5_sub'Reverse_range(3) loop vv_reverse(2)(4)(i) := i; end loop lr2_4;
lr2_5: for i in std_logic_array_dem_5_sub'Reverse_range(4) loop vv_reverse(2)(5)(i) := i; end loop lr2_5;
lr2_6: for i in std_logic_array_dem_5_sub'Reverse_range(5) loop vv_reverse(2)(6)(i) := i; end loop lr2_6;
-- bit array
l3_1: for i in bit_a_d5'range loop vv(3)(1)(i) := i; end loop l3_1;
l3_2: for i in bit_a_d5'range(1) loop vv(3)(2)(i) := i; end loop l3_2;
l3_3: for i in bit_a_d5'range(2) loop vv(3)(3)(i) := i; end loop l3_3;
l3_4: for i in bit_a_d5'range(3) loop vv(3)(4)(i) := i; end loop l3_4;
l3_5: for i in bit_a_d5'range(4) loop vv(3)(5)(i) := i; end loop l3_5;
l3_6: for i in bit_a_d5'range(5) loop vv(3)(6)(i) := i; end loop l3_6;
l4_1: for i in bit_array_dem_5_boarded'range loop vv(4)(1)(i) := i; end loop l4_1;
l4_2: for i in bit_array_dem_5_boarded'range(1) loop vv(4)(2)(i) := i; end loop l4_2;
l4_3: for i in bit_array_dem_5_boarded'range(2) loop vv(4)(3)(i) := i; end loop l4_3;
l4_4: for i in bit_array_dem_5_boarded'range(3) loop vv(4)(4)(i) := i; end loop l4_4;
l4_5: for i in bit_array_dem_5_boarded'range(4) loop vv(4)(5)(i) := i; end loop l4_5;
l4_6: for i in bit_array_dem_5_boarded'range(5) loop vv(4)(6)(i) := i; end loop l4_6;
lr3_1: for i in bit_a_d5'Reverse_range loop vv_reverse(3)(1)(i) := i; end loop lr3_1;
lr3_2: for i in bit_a_d5'Reverse_range(1) loop vv_reverse(3)(2)(i) := i; end loop lr3_2;
lr3_3: for i in bit_a_d5'Reverse_range(2) loop vv_reverse(3)(3)(i) := i; end loop lr3_3;
lr3_4: for i in bit_a_d5'Reverse_range(3) loop vv_reverse(3)(4)(i) := i; end loop lr3_4;
lr3_5: for i in bit_a_d5'Reverse_range(4) loop vv_reverse(3)(5)(i) := i; end loop lr3_5;
lr3_6: for i in bit_a_d5'Reverse_range(5) loop vv_reverse(3)(6)(i) := i; end loop lr3_6;
lr4_1: for i in bit_array_dem_5_boarded'Reverse_range loop vv_reverse(4)(1)(i) := i; end loop lr4_1;
lr4_2: for i in bit_array_dem_5_boarded'Reverse_range(1) loop vv_reverse(4)(2)(i) := i; end loop lr4_2;
lr4_3: for i in bit_array_dem_5_boarded'Reverse_range(2) loop vv_reverse(4)(3)(i) := i; end loop lr4_3;
lr4_4: for i in bit_array_dem_5_boarded'Reverse_range(3) loop vv_reverse(4)(4)(i) := i; end loop lr4_4;
lr4_5: for i in bit_array_dem_5_boarded'Reverse_range(4) loop vv_reverse(4)(5)(i) := i; end loop lr4_5;
lr4_6: for i in bit_array_dem_5_boarded'Reverse_range(5) loop vv_reverse(4)(6)(i) := i; end loop lr4_6;
-- integer array
l5_1: for i in int_a_d5'range loop vv(5)(1)(i) := i; end loop l5_1;
l5_2: for i in int_a_d5'range(1) loop vv(5)(2)(i) := i; end loop l5_2;
l5_3: for i in int_a_d5'range(2) loop vv(5)(3)(i) := i; end loop l5_3;
l5_4: for i in int_a_d5'range(3) loop vv(5)(4)(i) := i; end loop l5_4;
l5_5: for i in int_a_d5'range(4) loop vv(5)(5)(i) := i; end loop l5_5;
l5_6: for i in int_a_d5'range(5) loop vv(5)(6)(i) := i; end loop l5_6;
l6_1: for i in integer_array_dem_5_sub'range loop vv(6)(1)(i) := i; end loop l6_1;
l6_2: for i in integer_array_dem_5_sub'range(1) loop vv(6)(2)(i) := i; end loop l6_2;
l6_3: for i in integer_array_dem_5_sub'range(2) loop vv(6)(3)(i) := i; end loop l6_3;
l6_4: for i in integer_array_dem_5_sub'range(3) loop vv(6)(4)(i) := i; end loop l6_4;
l6_5: for i in integer_array_dem_5_sub'range(4) loop vv(6)(5)(i) := i; end loop l6_5;
l6_6: for i in integer_array_dem_5_sub'range(5) loop vv(6)(6)(i) := i; end loop l6_6;
lr5_1: for i in int_a_d5'Reverse_range loop vv_reverse(5)(1)(i) := i; end loop lr5_1;
lr5_2: for i in int_a_d5'Reverse_range(1) loop vv_reverse(5)(2)(i) := i; end loop lr5_2;
lr5_3: for i in int_a_d5'Reverse_range(2) loop vv_reverse(5)(3)(i) := i; end loop lr5_3;
lr5_4: for i in int_a_d5'Reverse_range(3) loop vv_reverse(5)(4)(i) := i; end loop lr5_4;
lr5_5: for i in int_a_d5'Reverse_range(4) loop vv_reverse(5)(5)(i) := i; end loop lr5_5;
lr5_6: for i in int_a_d5'Reverse_range(5) loop vv_reverse(5)(6)(i) := i; end loop lr5_6;
lr6_1: for i in integer_array_dem_5_sub'Reverse_range loop vv_reverse(6)(1)(i) := i; end loop lr6_1;
lr6_2: for i in integer_array_dem_5_sub'Reverse_range(1) loop vv_reverse(6)(2)(i) := i; end loop lr6_2;
lr6_3: for i in integer_array_dem_5_sub'Reverse_range(2) loop vv_reverse(6)(3)(i) := i; end loop lr6_3;
lr6_4: for i in integer_array_dem_5_sub'Reverse_range(3) loop vv_reverse(6)(4)(i) := i; end loop lr6_4;
lr6_5: for i in integer_array_dem_5_sub'Reverse_range(4) loop vv_reverse(6)(5)(i) := i; end loop lr6_5;
lr6_6: for i in integer_array_dem_5_sub'Reverse_range(5) loop vv_reverse(6)(6)(i) := i; end loop lr6_6;
-- boolean array
l7_1: for i in bool_a_d5'range loop vv(7)(1)(i) := i; end loop l7_1;
l7_2: for i in bool_a_d5'range(1) loop vv(7)(2)(i) := i; end loop l7_2;
l7_3: for i in bool_a_d5'range(2) loop vv(7)(3)(i) := i; end loop l7_3;
l7_4: for i in bool_a_d5'range(3) loop vv(7)(4)(i) := i; end loop l7_4;
l7_5: for i in bool_a_d5'range(4) loop vv(7)(5)(i) := i; end loop l7_5;
l7_6: for i in bool_a_d5'range(5) loop vv(7)(6)(i) := i; end loop l7_6;
l8_1: for i in boolean_array_dem_5_sub'range loop vv(8)(1)(i) := i; end loop l8_1;
l8_2: for i in boolean_array_dem_5_sub'range(1) loop vv(8)(2)(i) := i; end loop l8_2;
l8_3: for i in boolean_array_dem_5_sub'range(2) loop vv(8)(3)(i) := i; end loop l8_3;
l8_4: for i in boolean_array_dem_5_sub'range(3) loop vv(8)(4)(i) := i; end loop l8_4;
l8_5: for i in boolean_array_dem_5_sub'range(4) loop vv(8)(5)(i) := i; end loop l8_5;
l8_6: for i in boolean_array_dem_5_sub'range(5) loop vv(8)(6)(i) := i; end loop l8_6;
lr7_1: for i in bool_a_d5'Reverse_range loop vv_reverse(7)(1)(i) := i; end loop lr7_1;
lr7_2: for i in bool_a_d5'Reverse_range(1) loop vv_reverse(7)(2)(i) := i; end loop lr7_2;
lr7_3: for i in bool_a_d5'Reverse_range(2) loop vv_reverse(7)(3)(i) := i; end loop lr7_3;
lr7_4: for i in bool_a_d5'Reverse_range(3) loop vv_reverse(7)(4)(i) := i; end loop lr7_4;
lr7_5: for i in bool_a_d5'Reverse_range(4) loop vv_reverse(7)(5)(i) := i; end loop lr7_5;
lr7_6: for i in bool_a_d5'Reverse_range(5) loop vv_reverse(7)(6)(i) := i; end loop lr7_6;
lr8_1: for i in boolean_array_dem_5_sub'Reverse_range loop vv_reverse(8)(1)(i) := i; end loop lr8_1;
lr8_2: for i in boolean_array_dem_5_sub'Reverse_range(1) loop vv_reverse(8)(2)(i) := i; end loop lr8_2;
lr8_3: for i in boolean_array_dem_5_sub'Reverse_range(2) loop vv_reverse(8)(3)(i) := i; end loop lr8_3;
lr8_4: for i in boolean_array_dem_5_sub'Reverse_range(3) loop vv_reverse(8)(4)(i) := i; end loop lr8_4;
lr8_5: for i in boolean_array_dem_5_sub'Reverse_range(4) loop vv_reverse(8)(5)(i) := i; end loop lr8_5;
lr8_6: for i in boolean_array_dem_5_sub'Reverse_range(5) loop vv_reverse(8)(6)(i) := i; end loop lr8_6;
-- enum array
l9_1: for i in enum_a_d5'range loop vv(9)(1)(i) := i; end loop l9_1;
l9_2: for i in enum_a_d5'range(1) loop vv(9)(2)(i) := i; end loop l9_2;
l9_3: for i in enum_a_d5'range(2) loop vv(9)(3)(i) := i; end loop l9_3;
l9_4: for i in enum_a_d5'range(3) loop vv(9)(4)(i) := i; end loop l9_4;
l9_5: for i in enum_a_d5'range(4) loop vv(9)(5)(i) := i; end loop l9_5;
l9_6: for i in enum_a_d5'range(5) loop vv(9)(6)(i) := i; end loop l9_6;
l10_1: for i in enum_array_dem_5_boarded'range loop vv(10)(1)(i) := i; end loop l10_1;
l10_2: for i in enum_array_dem_5_boarded'range(1) loop vv(10)(2)(i) := i; end loop l10_2;
l10_3: for i in enum_array_dem_5_boarded'range(2) loop vv(10)(3)(i) := i; end loop l10_3;
l10_4: for i in enum_array_dem_5_boarded'range(3) loop vv(10)(4)(i) := i; end loop l10_4;
l10_5: for i in enum_array_dem_5_boarded'range(4) loop vv(10)(5)(i) := i; end loop l10_5;
l10_6: for i in enum_array_dem_5_boarded'range(5) loop vv(10)(6)(i) := i; end loop l10_6;
lr9_1: for i in enum_a_d5'Reverse_range loop vv_reverse(9)(1)(i) := i; end loop lr9_1;
lr9_2: for i in enum_a_d5'Reverse_range(1) loop vv_reverse(9)(2)(i) := i; end loop lr9_2;
lr9_3: for i in enum_a_d5'Reverse_range(2) loop vv_reverse(9)(3)(i) := i; end loop lr9_3;
lr9_4: for i in enum_a_d5'Reverse_range(3) loop vv_reverse(9)(4)(i) := i; end loop lr9_4;
lr9_5: for i in enum_a_d5'Reverse_range(4) loop vv_reverse(9)(5)(i) := i; end loop lr9_5;
lr9_6: for i in enum_a_d5'Reverse_range(5) loop vv_reverse(9)(6)(i) := i; end loop lr9_6;
lr10_1: for i in enum_array_dem_5_boarded'Reverse_range loop vv_reverse(10)(1)(i) := i; end loop lr10_1;
lr10_2: for i in enum_array_dem_5_boarded'Reverse_range(1) loop vv_reverse(10)(2)(i) := i; end loop lr10_2;
lr10_3: for i in enum_array_dem_5_boarded'Reverse_range(2) loop vv_reverse(10)(3)(i) := i; end loop lr10_3;
lr10_4: for i in enum_array_dem_5_boarded'Reverse_range(3) loop vv_reverse(10)(4)(i) := i; end loop lr10_4;
lr10_5: for i in enum_array_dem_5_boarded'Reverse_range(4) loop vv_reverse(10)(5)(i) := i; end loop lr10_5;
lr10_6: for i in enum_array_dem_5_boarded'Reverse_range(5) loop vv_reverse(10)(6)(i) := i; end loop lr10_6;
-- rec array
l11_1: for i in rec_a_d5'range loop vv(11)(1)(i) := i; end loop l11_1;
l11_2: for i in rec_a_d5'range(1) loop vv(11)(2)(i) := i; end loop l11_2;
l11_3: for i in rec_a_d5'range(2) loop vv(11)(3)(i) := i; end loop l11_3;
l11_4: for i in rec_a_d5'range(3) loop vv(11)(4)(i) := i; end loop l11_4;
l11_5: for i in rec_a_d5'range(4) loop vv(11)(5)(i) := i; end loop l11_5;
l11_6: for i in rec_a_d5'range(5) loop vv(11)(6)(i) := i; end loop l11_6;
l12_1: for i in rec_array_dem_5_sub'range loop vv(12)(1)(i) := i; end loop l12_1;
l12_2: for i in rec_array_dem_5_sub'range(1) loop vv(12)(2)(i) := i; end loop l12_2;
l12_3: for i in rec_array_dem_5_sub'range(2) loop vv(12)(3)(i) := i; end loop l12_3;
l12_4: for i in rec_array_dem_5_sub'range(3) loop vv(12)(4)(i) := i; end loop l12_4;
l12_5: for i in rec_array_dem_5_sub'range(4) loop vv(12)(5)(i) := i; end loop l12_5;
l12_6: for i in rec_array_dem_5_sub'range(5) loop vv(12)(6)(i) := i; end loop l12_6;
lr11_1: for i in rec_a_d5'Reverse_range loop vv_reverse(11)(1)(i) := i; end loop lr11_1;
lr11_2: for i in rec_a_d5'Reverse_range(1) loop vv_reverse(11)(2)(i) := i; end loop lr11_2;
lr11_3: for i in rec_a_d5'Reverse_range(2) loop vv_reverse(11)(3)(i) := i; end loop lr11_3;
lr11_4: for i in rec_a_d5'Reverse_range(3) loop vv_reverse(11)(4)(i) := i; end loop lr11_4;
lr11_5: for i in rec_a_d5'Reverse_range(4) loop vv_reverse(11)(5)(i) := i; end loop lr11_5;
lr11_6: for i in rec_a_d5'Reverse_range(5) loop vv_reverse(11)(6)(i) := i; end loop lr11_6;
lr12_1: for i in rec_array_dem_5_sub'Reverse_range loop vv_reverse(12)(1)(i) := i; end loop lr12_1;
lr12_2: for i in rec_array_dem_5_sub'Reverse_range(1) loop vv_reverse(12)(2)(i) := i; end loop lr12_2;
lr12_3: for i in rec_array_dem_5_sub'Reverse_range(2) loop vv_reverse(12)(3)(i) := i; end loop lr12_3;
lr12_4: for i in rec_array_dem_5_sub'Reverse_range(3) loop vv_reverse(12)(4)(i) := i; end loop lr12_4;
lr12_5: for i in rec_array_dem_5_sub'Reverse_range(4) loop vv_reverse(12)(5)(i) := i; end loop lr12_5;
lr12_6: for i in rec_array_dem_5_sub'Reverse_range(5) loop vv_reverse(12)(6)(i) := i; end loop lr12_6;
cond_loop: for i in 1 to 12 loop
-- low
cond(i)(1) := int(i)(1)(1) = 1 and int(i)(1)(2) = 1 and int(i)(1)(3) = 0 and int(i)(1)(4) = -1 and int(i)(1)(5) = 10 and int(i)(1)(6) = -3;
-- high
cond(i)(2) := int(i)(2)(1) = 3 and int(i)(2)(2) = 3 and int(i)(2)(3) = 7 and int(i)(2)(4) = 1 and int(i)(2)(5) = 20 and int(i)(2)(6) = 3;
-- left
cond(i)(3) := int(i)(3)(1) = 1 and int(i)(3)(2) = 1 and int(i)(3)(3) = 7 and int(i)(3)(4) = 1 and int(i)(3)(5) = 10 and int(i)(3)(6) = -3;
-- right
cond(i)(4) := int(i)(4)(1) = 3 and int(i)(4)(2) = 3 and int(i)(4)(3) = 0 and int(i)(4)(4) = -1 and int(i)(4)(5) = 20 and int(i)(4)(6) = 3;
-- length
cond(i)(5) := int(i)(5)(1) = 3 and int(i)(5)(2) = 3 and int(i)(5)(3) = 8 and int(i)(5)(4) = 3 and int(i)(5)(5) = 11 and int(i)(5)(6) = 7;
-- Ascending
cond(i)(6) := bool(i)(1) and bool(i)(2) and not(bool(i)(3)) and not(bool(i)(4)) and bool(i)(5) and bool(i)(6);
-- range
cond(i)(7) := all100(vv(i)(1)(-3 to 0)) and vv(i)(1)(1 to 3) = 1 & 2 & 3 and all100(vv(i)(1)(4 to 20)) and
all100(vv(i)(2)(-3 to 0)) and vv(i)(2)(1 to 3) = 1 & 2 & 3 and all100(vv(i)(2)(4 to 20)) and
all100(vv(i)(3)(-3 to -1)) and vv(i)(3)(0 to 7) = 0 & 1 & 2 & 3 & 4 & 5 & 6 & 7 and all100(vv(i)(3)(8 to 20)) and
all100(vv(i)(4)(-3 to -2)) and vv(i)(4)(-1 to 1) = -1 & 0 & 1 and all100(vv(i)(4)(2 to 20)) and
all100(vv(i)(5)(-3 to 9)) and vv(i)(5)(10 to 20) = 10 & 11 & 12 & 13 & 14 & 15 & 16 & 17 & 18 & 19 & 20 and
vv(i)(6)(-3 to 3) = (-3) & (-2) & (-1) & 0 & 1 & 2 & 3 and all100(vv(i)(6)(4 to 20));
-- reverse range
cond(i)(8) := all100(vv_reverse(i)(1)(-3 to 0)) and vv_reverse(i)(1)(1 to 3) = 1 & 2 & 3 and all100(vv_reverse(i)(1)(4 to 20)) and
all100(vv_reverse(i)(2)(-3 to 0)) and vv_reverse(i)(2)(1 to 3) = 1 & 2 & 3 and all100(vv_reverse(i)(2)(4 to 20)) and
all100(vv_reverse(i)(3)(-3 to -1)) and vv_reverse(i)(3)(0 to 7) = 0 & 1 & 2 & 3 & 4 & 5 & 6 & 7 and all100(vv_reverse(i)(3)(8 to 20)) and
all100(vv_reverse(i)(4)(-3 to -2)) and vv_reverse(i)(4)(-1 to 1) = -1 & 0 & 1 and all100(vv_reverse(i)(4)(2 to 20)) and
all100(vv_reverse(i)(5)(-3 to 9)) and vv_reverse(i)(5)(10 to 20) = 10 & 11 & 12 & 13 & 14 & 15 & 16 & 17 & 18 & 19 & 20 and
vv_reverse(i)(6)(-3 to 3) = (-3) & (-2) & (-1) & 0 & 1 & 2 & 3 and all100(vv_reverse(i)(6)(4 to 20));
end loop cond_loop;
-- std_logic_array
-- obj = 1
-- type = 2
-- bit array
-- obj = 3
-- type = 4
-- integer array
-- obj = 5
-- type = 6
-- boolean array
-- obj = 7
-- type = 8
-- enum array
-- obj = 9
-- type = 10
-- rec array
-- obj = 11
-- type = 12
when analize =>
state <= waiting;
-- std_logic array
-- Obj
assert not cond(1)(1)
report "Attribute A'Low(n) worked with the object of the type std_logic array of demention up to 5 correctly"
severity NOTE;
assert cond(1)(1)
report "Attribute A'Low(n) does not work with the object of the type std_logic array of demention up to 5"
severity NOTE;
assert not cond(1)(2)
report "Attribute A'High(n) worked with the object of the type std_logic array of demention up to 5 correctly"
severity NOTE;
assert cond(1)(2)
report "Attribute A'High(n) does not work with the object of the type std_logic array of demention up to 5"
severity NOTE;
assert not cond(1)(3)
report "Attribute A'Left(n) worked with the object of the type std_logic array of demention up to 5 correctly"
severity NOTE;
assert cond(1)(3)
report "Attribute A'Left(n) does not work with the object of the type std_logic array of demention up to 5"
severity NOTE;
assert not cond(1)(4)
report "Attribute A'Right(n) worked with the object of the type std_logic array of demention up to 5 correctly"
severity NOTE;
assert cond(1)(4)
report "Attribute A'Right(n) does not work with the object of the type std_logic array of demention up to 5"
severity NOTE;
assert not cond(1)(5)
report "Attribute A'Length(n) worked with the object of the type std_logic array of demention up to 5 correctly"
severity NOTE;
assert cond(1)(5)
report "Attribute A'Length(n) does not work with the object of the type std_logic array of demention up to 5"
severity NOTE;
assert not cond(1)(6)
report "Attribute A'Ascending(n) worked with the object of the type std_logic array of demention up to 5 correctly"
severity NOTE;
assert cond(1)(6)
report "Attribute A'Ascending(n) does not work with the object of the type std_logic array of demention up to 5"
severity NOTE;
assert not cond(1)(7)
report "Attribute A'Range(n) worked with the object of the type std_logic array of demention up to 5 correctly"
severity NOTE;
assert cond(1)(7)
report "Attribute A'Range(n) does not work with the object of the type std_logic array of demention up to 5"
severity NOTE;
assert not cond(1)(8)
report "Attribute A'Reverse_range(n) worked with the object of the type std_logic array of demention up to 5 correctly"
severity NOTE;
assert cond(1)(8)
report "Attribute A'Reverse_range(n) does not work with the object of the type std_logic array of demention up to 5"
severity NOTE;
-- subtype
assert not cond(2)(1)
report "Attribute A'Low(n) worked with the subtype std_logic array of demention up to 5 correctly"
severity NOTE;
assert cond(2)(1)
report "Attribute A'Low(n) does not work with the subtype std_logic array of demention up to 5"
severity NOTE;
assert not cond(2)(2)
report "Attribute A'High(n) worked with the subtype std_logic array of demention up to 5 correctly"
severity NOTE;
assert cond(2)(2)
report "Attribute A'High(n) does not work with the subtype std_logic array of demention up to 5"
severity NOTE;
assert not cond(2)(3)
report "Attribute A'Left(n) worked with the subtype std_logic array of demention up to 5 correctly"
severity NOTE;
assert cond(2)(3)
report "Attribute A'Left(n) does not work with the subtype std_logic array of demention up to 5"
severity NOTE;
assert not cond(2)(4)
report "Attribute A'Right(n) worked with the subtype std_logic array of demention up to 5 correctly"
severity NOTE;
assert cond(2)(4)
report "Attribute A'Right(n) does not work with the subtype std_logic array of demention up to 5"
severity NOTE;
assert not cond(2)(5)
report "Attribute A'Length(n) worked with the subtype std_logic array of demention up to 5 correctly"
severity NOTE;
assert cond(2)(5)
report "Attribute A'Length(n) does not work with the subtype std_logic array of demention up to 5"
severity NOTE;
assert not cond(2)(6)
report "Attribute A'Ascending(n) worked with the subtype std_logic array of demention up to 5 correctly"
severity NOTE;
assert cond(2)(6)
report "Attribute A'Ascending(n) does not work with the subtype std_logic array of demention up to 5"
severity NOTE;
assert not cond(2)(7)
report "Attribute A'Range(n) worked with the subtype std_logic array of demention up to 5 correctly"
severity NOTE;
assert cond(2)(7)
report "Attribute A'Range(n) does not work with the subtype std_logic array of demention up to 5"
severity NOTE;
assert not cond(2)(8)
report "Attribute A'Reverse_range(n) worked with the subtype std_logic array of demention up to 5 correctly"
severity NOTE;
assert cond(2)(8)
report "Attribute A'Reverse_range(n) does not work with the subtype std_logic array of demention up to 5"
severity NOTE;
-- bit array
-- Obj
assert not cond(3)(1)
report "Attribute A'Low(n) worked with the object of the type bit array of demention up to 5 correctly"
severity NOTE;
assert cond(3)(1)
report "Attribute A'Low(n) does not work with the object of the type bit array of demention up to 5"
severity NOTE;
assert not cond(3)(2)
report "Attribute A'High(n) worked with the object of the type bit array of demention up to 5 correctly"
severity NOTE;
assert cond(3)(2)
report "Attribute A'High(n) does not work with the object of the type bit array of demention up to 5"
severity NOTE;
assert not cond(3)(3)
report "Attribute A'Left(n) worked with the object of the type bit array of demention up to 5 correctly"
severity NOTE;
assert cond(3)(3)
report "Attribute A'Left(n) does not work with the object of the type bit array of demention up to 5"
severity NOTE;
assert not cond(3)(4)
report "Attribute A'Right(n) worked with the object of the type bit array of demention up to 5 correctly"
severity NOTE;
assert cond(3)(4)
report "Attribute A'Right(n) does not work with the object of the type bit array of demention up to 5"
severity NOTE;
assert not cond(3)(5)
report "Attribute A'Length(n) worked with the object of the type bit array of demention up to 5 correctly"
severity NOTE;
assert cond(3)(5)
report "Attribute A'Length(n) does not work with the object of the type bit array of demention up to 5"
severity NOTE;
assert not cond(3)(6)
report "Attribute A'Ascending(n) worked with the object of the type bit array of demention up to 5 correctly"
severity NOTE;
assert cond(3)(6)
report "Attribute A'Ascending(n) does not work with the object of the type bit array of demention up to 5"
severity NOTE;
assert not cond(3)(7)
report "Attribute A'Range(n) worked with the object of the type bit array of demention up to 5 correctly"
severity NOTE;
assert cond(3)(7)
report "Attribute A'Range(n) does not work with the object of the type bit array of demention up to 5"
severity NOTE;
assert not cond(3)(8)
report "Attribute A'Reverse_range(n) worked with the object of the type bit array of demention up to 5 correctly"
severity NOTE;
assert cond(3)(8)
report "Attribute A'Reverse_range(n) does not work with the object of the type bit array of demention up to 5"
severity NOTE;
-- subtype
assert not cond(4)(1)
report "Attribute A'Low(n) worked with the boarded type bit array of demention up to 5 correctly"
severity NOTE;
assert cond(4)(1)
report "Attribute A'Low(n) does not work with the boarded type bit array of demention up to 5"
severity NOTE;
assert not cond(4)(2)
report "Attribute A'High(n) worked with the boarded type bit array of demention up to 5 correctly"
severity NOTE;
assert cond(4)(2)
report "Attribute A'High(n) does not work with the boarded type bit array of demention up to 5"
severity NOTE;
assert not cond(4)(3)
report "Attribute A'Left(n) worked with the boarded type bit array of demention up to 5 correctly"
severity NOTE;
assert cond(4)(3)
report "Attribute A'Left(n) does not work with the boarded type bit array of demention up to 5"
severity NOTE;
assert not cond(4)(4)
report "Attribute A'Right(n) worked with the boarded type bit array of demention up to 5 correctly"
severity NOTE;
assert cond(4)(4)
report "Attribute A'Right(n) does not work with the boarded type bit array of demention up to 5"
severity NOTE;
assert not cond(4)(5)
report "Attribute A'Length(n) worked with the boarded type bit array of demention up to 5 correctly"
severity NOTE;
assert cond(4)(5)
report "Attribute A'Length(n) does not work with the boarded type bit array of demention up to 5"
severity NOTE;
assert not cond(4)(6)
report "Attribute A'Ascending(n) worked with the boarded type bit array of demention up to 5 correctly"
severity NOTE;
assert cond(4)(6)
report "Attribute A'Ascending(n) does not work with the boarded type bit array of demention up to 5"
severity NOTE;
assert not cond(4)(7)
report "Attribute A'Range(n) worked with the boarded type bit array of demention up to 5 correctly"
severity NOTE;
assert cond(4)(7)
report "Attribute A'Range(n) does not work with the boarded type bit array of demention up to 5"
severity NOTE;
assert not cond(4)(8)
report "Attribute A'Reverse_range(n) worked with the boarded type bit array of demention up to 5 correctly"
severity NOTE;
assert cond(4)(8)
report "Attribute A'Reverse_range(n) does not work with the boarded type bit array of demention up to 5"
severity NOTE;
-- integer array
-- Obj
assert not cond(5)(1)
report "Attribute A'Low(n) worked with the object of the type integer array of demention up to 5 correctly"
severity NOTE;
assert cond(5)(1)
report "Attribute A'Low(n) does not work with the object of the type integer array of demention up to 5"
severity NOTE;
assert not cond(5)(2)
report "Attribute A'High(n) worked with the object of the type integer array of demention up to 5 correctly"
severity NOTE;
assert cond(5)(2)
report "Attribute A'High(n) does not work with the object of the type integer array of demention up to 5"
severity NOTE;
assert not cond(5)(3)
report "Attribute A'Left(n) worked with the object of the type integer array of demention up to 5 correctly"
severity NOTE;
assert cond(5)(3)
report "Attribute A'Left(n) does not work with the object of the type integer array of demention up to 5"
severity NOTE;
assert not cond(5)(4)
report "Attribute A'Right(n) worked with the object of the type integer array of demention up to 5 correctly"
severity NOTE;
assert cond(5)(4)
report "Attribute A'Right(n) does not work with the object of the type integer array of demention up to 5"
severity NOTE;
assert not cond(5)(5)
report "Attribute A'Length(n) worked with the object of the type integer array of demention up to 5 correctly"
severity NOTE;
assert cond(5)(5)
report "Attribute A'Length(n) does not work with the object of the type integer array of demention up to 5"
severity NOTE;
assert not cond(5)(6)
report "Attribute A'Ascending(n) worked with the object of the type integer array of demention up to 5 correctly"
severity NOTE;
assert cond(5)(6)
report "Attribute A'Ascending(n) does not work with the object of the type integer array of demention up to 5"
severity NOTE;
assert not cond(5)(7)
report "Attribute A'Range(n) worked with the object of the type integer array of demention up to 5 correctly"
severity NOTE;
assert cond(5)(7)
report "Attribute A'Range(n) does not work with the object of the type integer array of demention up to 5"
severity NOTE;
assert not cond(5)(8)
report "Attribute A'Reverse_range(n) worked with the object of the type integer array of demention up to 5 correctly"
severity NOTE;
assert cond(5)(8)
report "Attribute A'Reverse_range(n) does not work with the object of the type integer array of demention up to 5"
severity NOTE;
-- subtype
assert not cond(6)(1)
report "Attribute A'Low(n) worked with the subtype integer array of demention up to 5 correctly"
severity NOTE;
assert cond(6)(1)
report "Attribute A'Low(n) does not work with the subtype integer array of demention up to 5"
severity NOTE;
assert not cond(6)(2)
report "Attribute A'High(n) worked with the subtype integer array of demention up to 5 correctly"
severity NOTE;
assert cond(6)(2)
report "Attribute A'High(n) does not work with the subtype integer array of demention up to 5"
severity NOTE;
assert not cond(6)(3)
report "Attribute A'Left(n) worked with the subtype integer array of demention up to 5 correctly"
severity NOTE;
assert cond(6)(3)
report "Attribute A'Left(n) does not work with the subtype integer array of demention up to 5"
severity NOTE;
assert not cond(6)(4)
report "Attribute A'Right(n) worked with the subtype integer array of demention up to 5 correctly"
severity NOTE;
assert cond(6)(4)
report "Attribute A'Right(n) does not work with the subtype integer array of demention up to 5"
severity NOTE;
assert not cond(6)(5)
report "Attribute A'Length(n) worked with the subtype integer array of demention up to 5 correctly"
severity NOTE;
assert cond(6)(5)
report "Attribute A'Length(n) does not work with the subtype integer array of demention up to 5"
severity NOTE;
assert not cond(6)(6)
report "Attribute A'Ascending(n) worked with the subtype integer array of demention up to 5 correctly"
severity NOTE;
assert cond(6)(6)
report "Attribute A'Ascending(n) does not work with the subtype integer array of demention up to 5"
severity NOTE;
assert not cond(6)(7)
report "Attribute A'Range(n) worked with the subtype integer array of demention up to 5 correctly"
severity NOTE;
assert cond(6)(7)
report "Attribute A'Range(n) does not work with the subtype integer array of demention up to 5"
severity NOTE;
assert not cond(6)(8)
report "Attribute A'Reverse_range(n) worked with the subtype integer array of demention up to 5 correctly"
severity NOTE;
assert cond(6)(8)
report "Attribute A'Reverse_range(n) does not work with the subtype integer array of demention up to 5"
severity NOTE;
-- boolean array
-- Obj
assert not cond(7)(1)
report "Attribute A'Low(n) worked with the object of the type boolean array of demention up to 5 correctly"
severity NOTE;
assert cond(7)(1)
report "Attribute A'Low(n) does not work with the object of the type boolean array of demention up to 5"
severity NOTE;
assert not cond(7)(2)
report "Attribute A'High(n) worked with the object of the type boolean array of demention up to 5 correctly"
severity NOTE;
assert cond(7)(2)
report "Attribute A'High(n) does not work with the object of the type boolean array of demention up to 5"
severity NOTE;
assert not cond(7)(3)
report "Attribute A'Left(n) worked with the object of the type boolean array of demention up to 5 correctly"
severity NOTE;
assert cond(7)(3)
report "Attribute A'Left(n) does not work with the object of the type boolean array of demention up to 5"
severity NOTE;
assert not cond(7)(4)
report "Attribute A'Right(n) worked with the object of the type boolean array of demention up to 5 correctly"
severity NOTE;
assert cond(7)(4)
report "Attribute A'Right(n) does not work with the object of the type boolean array of demention up to 5"
severity NOTE;
assert not cond(7)(5)
report "Attribute A'Length(n) worked with the object of the type boolean array of demention up to 5 correctly"
severity NOTE;
assert cond(7)(5)
report "Attribute A'Length(n) does not work with the object of the type boolean array of demention up to 5"
severity NOTE;
assert not cond(7)(6)
report "Attribute A'Ascending(n) worked with the object of the type boolean array of demention up to 5 correctly"
severity NOTE;
assert cond(7)(6)
report "Attribute A'Ascending(n) does not work with the object of the type boolean array of demention up to 5"
severity NOTE;
assert not cond(7)(7)
report "Attribute A'Range(n) worked with the object of the type boolean array of demention up to 5 correctly"
severity NOTE;
assert cond(7)(7)
report "Attribute A'Range(n) does not work with the object of the type boolean array of demention up to 5"
severity NOTE;
assert not cond(7)(8)
report "Attribute A'Reverse_range(n) worked with the object of the type boolean array of demention up to 5 correctly"
severity NOTE;
assert cond(7)(8)
report "Attribute A'Reverse_range(n) does not work with the object of the type boolean array of demention up to 5"
severity NOTE;
-- subtype
assert not cond(8)(1)
report "Attribute A'Low(n) worked with the subtype boolean array of demention up to 5 correctly"
severity NOTE;
assert cond(8)(1)
report "Attribute A'Low(n) does not work with the subtype boolean array of demention up to 5"
severity NOTE;
assert not cond(8)(2)
report "Attribute A'High(n) worked with the subtype boolean array of demention up to 5 correctly"
severity NOTE;
assert cond(8)(2)
report "Attribute A'High(n) does not work with the subtype boolean array of demention up to 5"
severity NOTE;
assert not cond(8)(3)
report "Attribute A'Left(n) worked with the subtype boolean array of demention up to 5 correctly"
severity NOTE;
assert cond(8)(3)
report "Attribute A'Left(n) does not work with the subtype boolean array of demention up to 5"
severity NOTE;
assert not cond(8)(4)
report "Attribute A'Right(n) worked with the subtype boolean array of demention up to 5 correctly"
severity NOTE;
assert cond(8)(4)
report "Attribute A'Right(n) does not work with the subtype boolean array of demention up to 5"
severity NOTE;
assert not cond(8)(5)
report "Attribute A'Length(n) worked with the subtype boolean array of demention up to 5 correctly"
severity NOTE;
assert cond(8)(5)
report "Attribute A'Length(n) does not work with the subtype boolean array of demention up to 5"
severity NOTE;
assert not cond(8)(6)
report "Attribute A'Ascending(n) worked with the subtype boolean array of demention up to 5 correctly"
severity NOTE;
assert cond(8)(6)
report "Attribute A'Ascending(n) does not work with the subtype boolean array of demention up to 5"
severity NOTE;
assert not cond(8)(7)
report "Attribute A'Range(n) worked with the subtype boolean array of demention up to 5 correctly"
severity NOTE;
assert cond(8)(7)
report "Attribute A'Range(n) does not work with the subtype boolean array of demention up to 5"
severity NOTE;
assert not cond(8)(8)
report "Attribute A'Reverse_range(n) worked with the subtype boolean array of demention up to 5 correctly"
severity NOTE;
assert cond(8)(8)
report "Attribute A'Reverse_range(n) does not work with the subtype boolean array of demention up to 5"
severity NOTE;
-- enum array
-- Obj
assert not cond(9)(1)
report "Attribute A'Low(n) worked with the object of the type enum array of demention up to 5 correctly"
severity NOTE;
assert cond(9)(1)
report "Attribute A'Low(n) does not work with the object of the type enum array of demention up to 5"
severity NOTE;
assert not cond(9)(2)
report "Attribute A'High(n) worked with the object of the type enum array of demention up to 5 correctly"
severity NOTE;
assert cond(9)(2)
report "Attribute A'High(n) does not work with the object of the type enum array of demention up to 5"
severity NOTE;
assert not cond(9)(3)
report "Attribute A'Left(n) worked with the object of the type enum array of demention up to 5 correctly"
severity NOTE;
assert cond(9)(3)
report "Attribute A'Left(n) does not work with the object of the type enum array of demention up to 5"
severity NOTE;
assert not cond(9)(4)
report "Attribute A'Right(n) worked with the object of the type enum array of demention up to 5 correctly"
severity NOTE;
assert cond(9)(4)
report "Attribute A'Right(n) does not work with the object of the type enum array of demention up to 5"
severity NOTE;
assert not cond(9)(5)
report "Attribute A'Length(n) worked with the object of the type enum array of demention up to 5 correctly"
severity NOTE;
assert cond(9)(5)
report "Attribute A'Length(n) does not work with the object of the type enum array of demention up to 5"
severity NOTE;
assert not cond(9)(6)
report "Attribute A'Ascending(n) worked with the object of the type enum array of demention up to 5 correctly"
severity NOTE;
assert cond(9)(6)
report "Attribute A'Ascending(n) does not work with the object of the type enum array of demention up to 5"
severity NOTE;
assert not cond(9)(7)
report "Attribute A'Range(n) worked with the object of the type enum array of demention up to 5 correctly"
severity NOTE;
assert cond(9)(7)
report "Attribute A'Range(n) does not work with the object of the type enum array of demention up to 5"
severity NOTE;
assert not cond(9)(8)
report "Attribute A'Reverse_range(n) worked with the object of the type enum array of demention up to 5 correctly"
severity NOTE;
assert cond(9)(8)
report "Attribute A'Reverse_range(n) does not work with the object of the type enum array of demention up to 5"
severity NOTE;
-- subtype
assert not cond(10)(1)
report "Attribute A'Low(n) worked with the boarded type enum array of demention up to 5 correctly"
severity NOTE;
assert cond(10)(1)
report "Attribute A'Low(n) does not work with the boarded type enum array of demention up to 5"
severity NOTE;
assert not cond(10)(2)
report "Attribute A'High(n) worked with the boarded type enum array of demention up to 5 correctly"
severity NOTE;
assert cond(10)(2)
report "Attribute A'High(n) does not work with the boarded type enum array of demention up to 5"
severity NOTE;
assert not cond(10)(3)
report "Attribute A'Left(n) worked with the boarded type enum array of demention up to 5 correctly"
severity NOTE;
assert cond(10)(3)
report "Attribute A'Left(n) does not work with the boarded type enum array of demention up to 5"
severity NOTE;
assert not cond(10)(4)
report "Attribute A'Right(n) worked with the boarded type enum array of demention up to 5 correctly"
severity NOTE;
assert cond(10)(4)
report "Attribute A'Right(n) does not work with the boarded type enum array of demention up to 5"
severity NOTE;
assert not cond(10)(5)
report "Attribute A'Length(n) worked with the boarded type enum array of demention up to 5 correctly"
severity NOTE;
assert cond(10)(5)
report "Attribute A'Length(n) does not work with the boarded type enum array of demention up to 5"
severity NOTE;
assert not cond(10)(6)
report "Attribute A'Ascending(n) worked with the boarded type enum array of demention up to 5 correctly"
severity NOTE;
assert cond(10)(6)
report "Attribute A'Ascending(n) does not work with the boarded type enum array of demention up to 5"
severity NOTE;
assert not cond(10)(7)
report "Attribute A'Range(n) worked with the boarded type enum array of demention up to 5 correctly"
severity NOTE;
assert cond(10)(7)
report "Attribute A'Range(n) does not work with the boarded type enum array of demention up to 5"
severity NOTE;
assert not cond(10)(8)
report "Attribute A'Reverse_range(n) worked with the boarded type enum array of demention up to 5 correctly"
severity NOTE;
assert cond(10)(8)
report "Attribute A'Reverse_range(n) does not work with the boarded type enum array of demention up to 5"
severity NOTE;
-- rec array
-- Obj
assert not cond(11)(1)
report "Attribute A'Low(n) worked with the object of the type record array of demention up to 5 correctly"
severity NOTE;
assert cond(11)(1)
report "Attribute A'Low(n) does not work with the object of the type record array of demention up to 5"
severity NOTE;
assert not cond(11)(2)
report "Attribute A'High(n) worked with the object of the type record array of demention up to 5 correctly"
severity NOTE;
assert cond(11)(2)
report "Attribute A'High(n) does not work with the object of the type record array of demention up to 5"
severity NOTE;
assert not cond(11)(3)
report "Attribute A'Left(n) worked with the object of the type record array of demention up to 5 correctly"
severity NOTE;
assert cond(11)(3)
report "Attribute A'Left(n) does not work with the object of the type record array of demention up to 5"
severity NOTE;
assert not cond(11)(4)
report "Attribute A'Right(n) worked with the object of the type record array of demention up to 5 correctly"
severity NOTE;
assert cond(11)(4)
report "Attribute A'Right(n) does not work with the object of the type record array of demention up to 5"
severity NOTE;
assert not cond(11)(5)
report "Attribute A'Length(n) worked with the object of the type record array of demention up to 5 correctly"
severity NOTE;
assert cond(11)(5)
report "Attribute A'Length(n) does not work with the object of the type record array of demention up to 5"
severity NOTE;
assert not cond(11)(6)
report "Attribute A'Ascending(n) worked with the object of the type record array of demention up to 5 correctly"
severity NOTE;
assert cond(11)(6)
report "Attribute A'Ascending(n) does not work with the object of the type record array of demention up to 5"
severity NOTE;
assert not cond(11)(7)
report "Attribute A'Range(n) worked with the object of the type record array of demention up to 5 correctly"
severity NOTE;
assert cond(11)(7)
report "Attribute A'Range(n) does not work with the object of the type record array of demention up to 5"
severity NOTE;
assert not cond(11)(8)
report "Attribute A'Reverse_range(n) worked with the object of the type record array of demention up to 5 correctly"
severity NOTE;
assert cond(11)(8)
report "Attribute A'Reverse_range(n) does not work with the object of the type record array of demention up to 5"
severity NOTE;
-- subtype
assert not cond(12)(1)
report "Attribute A'Low(n) worked with the subtype record array of demention up to 5 correctly"
severity NOTE;
assert cond(12)(1)
report "Attribute A'Low(n) does not work with the subtype record array of demention up to 5"
severity NOTE;
assert not cond(12)(2)
report "Attribute A'High(n) worked with the subtype record array of demention up to 5 correctly"
severity NOTE;
assert cond(12)(2)
report "Attribute A'High(n) does not work with the subtype record array of demention up to 5"
severity NOTE;
assert not cond(12)(3)
report "Attribute A'Left(n) worked with the subtype record array of demention up to 5 correctly"
severity NOTE;
assert cond(12)(3)
report "Attribute A'Left(n) does not work with the subtype record array of demention up to 5"
severity NOTE;
assert not cond(12)(4)
report "Attribute A'Right(n) worked with the subtype record array of demention up to 5 correctly"
severity NOTE;
assert cond(12)(4)
report "Attribute A'Right(n) does not work with the subtype record array of demention up to 5"
severity NOTE;
assert not cond(12)(5)
report "Attribute A'Length(n) worked with the subtype record array of demention up to 5 correctly"
severity NOTE;
assert cond(12)(5)
report "Attribute A'Length(n) does not work with the subtype record array of demention up to 5"
severity NOTE;
assert not cond(12)(6)
report "Attribute A'Ascending(n) worked with the subtype record array of demention up to 5 correctly"
severity NOTE;
assert cond(12)(6)
report "Attribute A'Ascending(n) does not work with the subtype record array of demention up to 5"
severity NOTE;
assert not cond(12)(7)
report "Attribute A'Range(n) worked with the subtype record array of demention up to 5 correctly"
severity NOTE;
assert cond(12)(7)
report "Attribute A'Range(n) does not work with the subtype record array of demention up to 5"
severity NOTE;
assert not cond(12)(8)
report "Attribute A'Reverse_range(n) worked with the subtype record array of demention up to 5 correctly"
severity NOTE;
assert cond(12)(8)
report "Attribute A'Reverse_range(n) does not work with the subtype record array of demention up to 5"
severity NOTE;
when waiting =>
null;
end case;
end process;
end ARCH00024_Test_Bench ; | gpl-3.0 | d7da1512b84eea2003336fcbb369cad1 | 0.605242 | 2.620705 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00383.vhd | 1 | 102,908 | -- NEED RESULT: ARCH00383.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00383.P2: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00383.P3: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00383.P4: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00383.P5: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00383.P6: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00383.P7: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00383.P8: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00383.P9: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00383.P10: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00383.P11: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00383.P12: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00383.P13: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00383.P14: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00383.P15: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00383.P16: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00383.P17: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00383: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: P17: Inertial transactions completed entirely passed
-- NEED RESULT: P16: Inertial transactions completed entirely passed
-- NEED RESULT: P15: Inertial transactions completed entirely passed
-- NEED RESULT: P14: Inertial transactions completed entirely passed
-- NEED RESULT: P13: Inertial transactions completed entirely passed
-- NEED RESULT: P12: Inertial transactions completed entirely passed
-- NEED RESULT: P11: Inertial transactions completed entirely passed
-- NEED RESULT: P10: Inertial transactions completed entirely passed
-- NEED RESULT: P9: Inertial transactions completed entirely passed
-- NEED RESULT: P8: Inertial transactions completed entirely passed
-- NEED RESULT: P7: Inertial transactions completed entirely passed
-- NEED RESULT: P6: Inertial transactions completed entirely passed
-- NEED RESULT: P5: Inertial transactions completed entirely passed
-- NEED RESULT: P4: Inertial transactions completed entirely passed
-- NEED RESULT: P3: Inertial transactions completed entirely passed
-- NEED RESULT: P2: Inertial transactions completed entirely passed
-- NEED RESULT: P1: Inertial transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00383
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (3)
-- 9.5.2 (1)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00383(ARCH00383)
-- ENT00383_Test_Bench(ARCH00383_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00383 is
port (
s_boolean : inout boolean
; s_bit : inout bit
; s_severity_level : inout severity_level
; s_character : inout character
; s_st_enum1 : inout st_enum1
; s_integer : inout integer
; s_st_int1 : inout st_int1
; s_time : inout time
; s_st_phys1 : inout st_phys1
; s_real : inout real
; s_st_real1 : inout st_real1
; s_st_rec1 : inout st_rec1
; s_st_rec2 : inout st_rec2
; s_st_rec3 : inout st_rec3
; s_st_arr1 : inout st_arr1
; s_st_arr2 : inout st_arr2
; s_st_arr3 : inout st_arr3
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_boolean : chk_sig_type := -1 ;
signal chk_bit : chk_sig_type := -1 ;
signal chk_severity_level : chk_sig_type := -1 ;
signal chk_character : chk_sig_type := -1 ;
signal chk_st_enum1 : chk_sig_type := -1 ;
signal chk_integer : chk_sig_type := -1 ;
signal chk_st_int1 : chk_sig_type := -1 ;
signal chk_time : chk_sig_type := -1 ;
signal chk_st_phys1 : chk_sig_type := -1 ;
signal chk_real : chk_sig_type := -1 ;
signal chk_st_real1 : chk_sig_type := -1 ;
signal chk_st_rec1 : chk_sig_type := -1 ;
signal chk_st_rec2 : chk_sig_type := -1 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
signal chk_st_arr1 : chk_sig_type := -1 ;
signal chk_st_arr2 : chk_sig_type := -1 ;
signal chk_st_arr3 : chk_sig_type := -1 ;
--
end ENT00383 ;
--
--
architecture ARCH00383 of ENT00383 is
subtype chk_time_type is Time ;
signal s_boolean_savt : chk_time_type := 0 ns ;
signal s_bit_savt : chk_time_type := 0 ns ;
signal s_severity_level_savt : chk_time_type := 0 ns ;
signal s_character_savt : chk_time_type := 0 ns ;
signal s_st_enum1_savt : chk_time_type := 0 ns ;
signal s_integer_savt : chk_time_type := 0 ns ;
signal s_st_int1_savt : chk_time_type := 0 ns ;
signal s_time_savt : chk_time_type := 0 ns ;
signal s_st_phys1_savt : chk_time_type := 0 ns ;
signal s_real_savt : chk_time_type := 0 ns ;
signal s_st_real1_savt : chk_time_type := 0 ns ;
signal s_st_rec1_savt : chk_time_type := 0 ns ;
signal s_st_rec2_savt : chk_time_type := 0 ns ;
signal s_st_rec3_savt : chk_time_type := 0 ns ;
signal s_st_arr1_savt : chk_time_type := 0 ns ;
signal s_st_arr2_savt : chk_time_type := 0 ns ;
signal s_st_arr3_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_boolean_cnt : chk_cnt_type := 0 ;
signal s_bit_cnt : chk_cnt_type := 0 ;
signal s_severity_level_cnt : chk_cnt_type := 0 ;
signal s_character_cnt : chk_cnt_type := 0 ;
signal s_st_enum1_cnt : chk_cnt_type := 0 ;
signal s_integer_cnt : chk_cnt_type := 0 ;
signal s_st_int1_cnt : chk_cnt_type := 0 ;
signal s_time_cnt : chk_cnt_type := 0 ;
signal s_st_phys1_cnt : chk_cnt_type := 0 ;
signal s_real_cnt : chk_cnt_type := 0 ;
signal s_st_real1_cnt : chk_cnt_type := 0 ;
signal s_st_rec1_cnt : chk_cnt_type := 0 ;
signal s_st_rec2_cnt : chk_cnt_type := 0 ;
signal s_st_rec3_cnt : chk_cnt_type := 0 ;
signal s_st_arr1_cnt : chk_cnt_type := 0 ;
signal s_st_arr2_cnt : chk_cnt_type := 0 ;
signal s_st_arr3_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 6 ;
signal boolean_select : select_type := 1 ;
signal bit_select : select_type := 1 ;
signal severity_level_select : select_type := 1 ;
signal character_select : select_type := 1 ;
signal st_enum1_select : select_type := 1 ;
signal integer_select : select_type := 1 ;
signal st_int1_select : select_type := 1 ;
signal time_select : select_type := 1 ;
signal st_phys1_select : select_type := 1 ;
signal real_select : select_type := 1 ;
signal st_real1_select : select_type := 1 ;
signal st_rec1_select : select_type := 1 ;
signal st_rec2_select : select_type := 1 ;
signal st_rec3_select : select_type := 1 ;
signal st_arr1_select : select_type := 1 ;
signal st_arr2_select : select_type := 1 ;
signal st_arr3_select : select_type := 1 ;
--
begin
CHG1 :
process
variable correct : boolean ;
begin
case s_boolean_cnt is
when 0
=> null ;
-- s_boolean <=
-- c_boolean_2 after 10 ns,
-- c_boolean_1 after 20 ns ;
--
when 1
=> correct :=
s_boolean =
c_boolean_2 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383.P1" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
boolean_select <= transport 2 ;
-- s_boolean <=
-- c_boolean_2 after 10 ns ,
-- c_boolean_1 after 20 ns ,
-- c_boolean_2 after 30 ns ,
-- c_boolean_1 after 40 ns ;
--
when 3
=> correct :=
s_boolean =
c_boolean_2 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
boolean_select <= transport 3 ;
-- s_boolean <=
-- c_boolean_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
boolean_select <= transport 4 ;
-- s_boolean <=
-- c_boolean_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
boolean_select <= transport 5 ;
-- s_boolean <=
-- c_boolean_2 after 10 ns ,
-- c_boolean_1 after 20 ns ,
-- c_boolean_2 after 30 ns ,
-- c_boolean_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_boolean =
c_boolean_2 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
boolean_select <= transport 6 ;
-- Last transaction above is marked
-- s_boolean <=
-- c_boolean_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_boolean_savt <= transport Std.Standard.Now ;
chk_boolean <= transport s_boolean_cnt
after (1 us - Std.Standard.Now) ;
s_boolean_cnt <= transport s_boolean_cnt + 1 ;
wait until (not s_boolean'Quiet) and
(s_boolean_savt /= Std.Standard.Now) ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_boolean )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions completed entirely",
chk_boolean = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
with boolean_select select
s_boolean <=
c_boolean_2 after 10 ns,
c_boolean_1 after 20 ns
when 1,
--
c_boolean_2 after 10 ns ,
c_boolean_1 after 20 ns ,
c_boolean_2 after 30 ns ,
c_boolean_1 after 40 ns
when 2,
--
c_boolean_1 after 5 ns
when 3,
--
c_boolean_1 after 100 ns
when 4,
--
c_boolean_2 after 10 ns ,
c_boolean_1 after 20 ns ,
c_boolean_2 after 30 ns ,
c_boolean_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_boolean_1 after 40 ns when 6 ;
--
CHG2 :
process
variable correct : boolean ;
begin
case s_bit_cnt is
when 0
=> null ;
-- s_bit <=
-- c_bit_2 after 10 ns,
-- c_bit_1 after 20 ns ;
--
when 1
=> correct :=
s_bit =
c_bit_2 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383.P2" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
bit_select <= transport 2 ;
-- s_bit <=
-- c_bit_2 after 10 ns ,
-- c_bit_1 after 20 ns ,
-- c_bit_2 after 30 ns ,
-- c_bit_1 after 40 ns ;
--
when 3
=> correct :=
s_bit =
c_bit_2 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
bit_select <= transport 3 ;
-- s_bit <=
-- c_bit_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
bit_select <= transport 4 ;
-- s_bit <=
-- c_bit_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
bit_select <= transport 5 ;
-- s_bit <=
-- c_bit_2 after 10 ns ,
-- c_bit_1 after 20 ns ,
-- c_bit_2 after 30 ns ,
-- c_bit_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_bit =
c_bit_2 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
bit_select <= transport 6 ;
-- Last transaction above is marked
-- s_bit <=
-- c_bit_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_bit_savt <= transport Std.Standard.Now ;
chk_bit <= transport s_bit_cnt
after (1 us - Std.Standard.Now) ;
s_bit_cnt <= transport s_bit_cnt + 1 ;
wait until (not s_bit'Quiet) and
(s_bit_savt /= Std.Standard.Now) ;
--
end process CHG2 ;
--
PGEN_CHKP_2 :
process ( chk_bit )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions completed entirely",
chk_bit = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
with bit_select select
s_bit <=
c_bit_2 after 10 ns,
c_bit_1 after 20 ns
when 1,
--
c_bit_2 after 10 ns ,
c_bit_1 after 20 ns ,
c_bit_2 after 30 ns ,
c_bit_1 after 40 ns
when 2,
--
c_bit_1 after 5 ns
when 3,
--
c_bit_1 after 100 ns
when 4,
--
c_bit_2 after 10 ns ,
c_bit_1 after 20 ns ,
c_bit_2 after 30 ns ,
c_bit_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_bit_1 after 40 ns when 6 ;
--
CHG3 :
process
variable correct : boolean ;
begin
case s_severity_level_cnt is
when 0
=> null ;
-- s_severity_level <=
-- c_severity_level_2 after 10 ns,
-- c_severity_level_1 after 20 ns ;
--
when 1
=> correct :=
s_severity_level =
c_severity_level_2 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383.P3" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
severity_level_select <= transport 2 ;
-- s_severity_level <=
-- c_severity_level_2 after 10 ns ,
-- c_severity_level_1 after 20 ns ,
-- c_severity_level_2 after 30 ns ,
-- c_severity_level_1 after 40 ns ;
--
when 3
=> correct :=
s_severity_level =
c_severity_level_2 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
severity_level_select <= transport 3 ;
-- s_severity_level <=
-- c_severity_level_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
severity_level_select <= transport 4 ;
-- s_severity_level <=
-- c_severity_level_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
severity_level_select <= transport 5 ;
-- s_severity_level <=
-- c_severity_level_2 after 10 ns ,
-- c_severity_level_1 after 20 ns ,
-- c_severity_level_2 after 30 ns ,
-- c_severity_level_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_severity_level =
c_severity_level_2 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
severity_level_select <= transport 6 ;
-- Last transaction above is marked
-- s_severity_level <=
-- c_severity_level_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_severity_level_savt <= transport Std.Standard.Now ;
chk_severity_level <= transport s_severity_level_cnt
after (1 us - Std.Standard.Now) ;
s_severity_level_cnt <= transport s_severity_level_cnt + 1 ;
wait until (not s_severity_level'Quiet) and
(s_severity_level_savt /= Std.Standard.Now) ;
--
end process CHG3 ;
--
PGEN_CHKP_3 :
process ( chk_severity_level )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions completed entirely",
chk_severity_level = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
with severity_level_select select
s_severity_level <=
c_severity_level_2 after 10 ns,
c_severity_level_1 after 20 ns
when 1,
--
c_severity_level_2 after 10 ns ,
c_severity_level_1 after 20 ns ,
c_severity_level_2 after 30 ns ,
c_severity_level_1 after 40 ns
when 2,
--
c_severity_level_1 after 5 ns
when 3,
--
c_severity_level_1 after 100 ns
when 4,
--
c_severity_level_2 after 10 ns ,
c_severity_level_1 after 20 ns ,
c_severity_level_2 after 30 ns ,
c_severity_level_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_severity_level_1 after 40 ns when 6 ;
--
CHG4 :
process
variable correct : boolean ;
begin
case s_character_cnt is
when 0
=> null ;
-- s_character <=
-- c_character_2 after 10 ns,
-- c_character_1 after 20 ns ;
--
when 1
=> correct :=
s_character =
c_character_2 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383.P4" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
character_select <= transport 2 ;
-- s_character <=
-- c_character_2 after 10 ns ,
-- c_character_1 after 20 ns ,
-- c_character_2 after 30 ns ,
-- c_character_1 after 40 ns ;
--
when 3
=> correct :=
s_character =
c_character_2 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
character_select <= transport 3 ;
-- s_character <=
-- c_character_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
character_select <= transport 4 ;
-- s_character <=
-- c_character_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
character_select <= transport 5 ;
-- s_character <=
-- c_character_2 after 10 ns ,
-- c_character_1 after 20 ns ,
-- c_character_2 after 30 ns ,
-- c_character_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_character =
c_character_2 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
character_select <= transport 6 ;
-- Last transaction above is marked
-- s_character <=
-- c_character_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_character_savt <= transport Std.Standard.Now ;
chk_character <= transport s_character_cnt
after (1 us - Std.Standard.Now) ;
s_character_cnt <= transport s_character_cnt + 1 ;
wait until (not s_character'Quiet) and
(s_character_savt /= Std.Standard.Now) ;
--
end process CHG4 ;
--
PGEN_CHKP_4 :
process ( chk_character )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Inertial transactions completed entirely",
chk_character = 8 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
--
with character_select select
s_character <=
c_character_2 after 10 ns,
c_character_1 after 20 ns
when 1,
--
c_character_2 after 10 ns ,
c_character_1 after 20 ns ,
c_character_2 after 30 ns ,
c_character_1 after 40 ns
when 2,
--
c_character_1 after 5 ns
when 3,
--
c_character_1 after 100 ns
when 4,
--
c_character_2 after 10 ns ,
c_character_1 after 20 ns ,
c_character_2 after 30 ns ,
c_character_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_character_1 after 40 ns when 6 ;
--
CHG5 :
process
variable correct : boolean ;
begin
case s_st_enum1_cnt is
when 0
=> null ;
-- s_st_enum1 <=
-- c_st_enum1_2 after 10 ns,
-- c_st_enum1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_enum1 =
c_st_enum1_2 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383.P5" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_enum1_select <= transport 2 ;
-- s_st_enum1 <=
-- c_st_enum1_2 after 10 ns ,
-- c_st_enum1_1 after 20 ns ,
-- c_st_enum1_2 after 30 ns ,
-- c_st_enum1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_enum1 =
c_st_enum1_2 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
st_enum1_select <= transport 3 ;
-- s_st_enum1 <=
-- c_st_enum1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_enum1_select <= transport 4 ;
-- s_st_enum1 <=
-- c_st_enum1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_enum1_select <= transport 5 ;
-- s_st_enum1 <=
-- c_st_enum1_2 after 10 ns ,
-- c_st_enum1_1 after 20 ns ,
-- c_st_enum1_2 after 30 ns ,
-- c_st_enum1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_2 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_enum1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_enum1 <=
-- c_st_enum1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_enum1_savt <= transport Std.Standard.Now ;
chk_st_enum1 <= transport s_st_enum1_cnt
after (1 us - Std.Standard.Now) ;
s_st_enum1_cnt <= transport s_st_enum1_cnt + 1 ;
wait until (not s_st_enum1'Quiet) and
(s_st_enum1_savt /= Std.Standard.Now) ;
--
end process CHG5 ;
--
PGEN_CHKP_5 :
process ( chk_st_enum1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Inertial transactions completed entirely",
chk_st_enum1 = 8 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
--
with st_enum1_select select
s_st_enum1 <=
c_st_enum1_2 after 10 ns,
c_st_enum1_1 after 20 ns
when 1,
--
c_st_enum1_2 after 10 ns ,
c_st_enum1_1 after 20 ns ,
c_st_enum1_2 after 30 ns ,
c_st_enum1_1 after 40 ns
when 2,
--
c_st_enum1_1 after 5 ns
when 3,
--
c_st_enum1_1 after 100 ns
when 4,
--
c_st_enum1_2 after 10 ns ,
c_st_enum1_1 after 20 ns ,
c_st_enum1_2 after 30 ns ,
c_st_enum1_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_enum1_1 after 40 ns when 6 ;
--
CHG6 :
process
variable correct : boolean ;
begin
case s_integer_cnt is
when 0
=> null ;
-- s_integer <=
-- c_integer_2 after 10 ns,
-- c_integer_1 after 20 ns ;
--
when 1
=> correct :=
s_integer =
c_integer_2 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383.P6" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
integer_select <= transport 2 ;
-- s_integer <=
-- c_integer_2 after 10 ns ,
-- c_integer_1 after 20 ns ,
-- c_integer_2 after 30 ns ,
-- c_integer_1 after 40 ns ;
--
when 3
=> correct :=
s_integer =
c_integer_2 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
integer_select <= transport 3 ;
-- s_integer <=
-- c_integer_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
integer_select <= transport 4 ;
-- s_integer <=
-- c_integer_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
integer_select <= transport 5 ;
-- s_integer <=
-- c_integer_2 after 10 ns ,
-- c_integer_1 after 20 ns ,
-- c_integer_2 after 30 ns ,
-- c_integer_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_integer =
c_integer_2 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
integer_select <= transport 6 ;
-- Last transaction above is marked
-- s_integer <=
-- c_integer_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_integer_savt <= transport Std.Standard.Now ;
chk_integer <= transport s_integer_cnt
after (1 us - Std.Standard.Now) ;
s_integer_cnt <= transport s_integer_cnt + 1 ;
wait until (not s_integer'Quiet) and
(s_integer_savt /= Std.Standard.Now) ;
--
end process CHG6 ;
--
PGEN_CHKP_6 :
process ( chk_integer )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Inertial transactions completed entirely",
chk_integer = 8 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
--
with integer_select select
s_integer <=
c_integer_2 after 10 ns,
c_integer_1 after 20 ns
when 1,
--
c_integer_2 after 10 ns ,
c_integer_1 after 20 ns ,
c_integer_2 after 30 ns ,
c_integer_1 after 40 ns
when 2,
--
c_integer_1 after 5 ns
when 3,
--
c_integer_1 after 100 ns
when 4,
--
c_integer_2 after 10 ns ,
c_integer_1 after 20 ns ,
c_integer_2 after 30 ns ,
c_integer_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_integer_1 after 40 ns when 6 ;
--
CHG7 :
process
variable correct : boolean ;
begin
case s_st_int1_cnt is
when 0
=> null ;
-- s_st_int1 <=
-- c_st_int1_2 after 10 ns,
-- c_st_int1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_int1 =
c_st_int1_2 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383.P7" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_int1_select <= transport 2 ;
-- s_st_int1 <=
-- c_st_int1_2 after 10 ns ,
-- c_st_int1_1 after 20 ns ,
-- c_st_int1_2 after 30 ns ,
-- c_st_int1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_int1 =
c_st_int1_2 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
st_int1_select <= transport 3 ;
-- s_st_int1 <=
-- c_st_int1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_int1_select <= transport 4 ;
-- s_st_int1 <=
-- c_st_int1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_int1_select <= transport 5 ;
-- s_st_int1 <=
-- c_st_int1_2 after 10 ns ,
-- c_st_int1_1 after 20 ns ,
-- c_st_int1_2 after 30 ns ,
-- c_st_int1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_int1 =
c_st_int1_2 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_int1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_int1 <=
-- c_st_int1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_int1_savt <= transport Std.Standard.Now ;
chk_st_int1 <= transport s_st_int1_cnt
after (1 us - Std.Standard.Now) ;
s_st_int1_cnt <= transport s_st_int1_cnt + 1 ;
wait until (not s_st_int1'Quiet) and
(s_st_int1_savt /= Std.Standard.Now) ;
--
end process CHG7 ;
--
PGEN_CHKP_7 :
process ( chk_st_int1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Inertial transactions completed entirely",
chk_st_int1 = 8 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
--
with st_int1_select select
s_st_int1 <=
c_st_int1_2 after 10 ns,
c_st_int1_1 after 20 ns
when 1,
--
c_st_int1_2 after 10 ns ,
c_st_int1_1 after 20 ns ,
c_st_int1_2 after 30 ns ,
c_st_int1_1 after 40 ns
when 2,
--
c_st_int1_1 after 5 ns
when 3,
--
c_st_int1_1 after 100 ns
when 4,
--
c_st_int1_2 after 10 ns ,
c_st_int1_1 after 20 ns ,
c_st_int1_2 after 30 ns ,
c_st_int1_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_int1_1 after 40 ns when 6 ;
--
CHG8 :
process
variable correct : boolean ;
begin
case s_time_cnt is
when 0
=> null ;
-- s_time <=
-- c_time_2 after 10 ns,
-- c_time_1 after 20 ns ;
--
when 1
=> correct :=
s_time =
c_time_2 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383.P8" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
time_select <= transport 2 ;
-- s_time <=
-- c_time_2 after 10 ns ,
-- c_time_1 after 20 ns ,
-- c_time_2 after 30 ns ,
-- c_time_1 after 40 ns ;
--
when 3
=> correct :=
s_time =
c_time_2 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
time_select <= transport 3 ;
-- s_time <=
-- c_time_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
time_select <= transport 4 ;
-- s_time <=
-- c_time_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
time_select <= transport 5 ;
-- s_time <=
-- c_time_2 after 10 ns ,
-- c_time_1 after 20 ns ,
-- c_time_2 after 30 ns ,
-- c_time_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_time =
c_time_2 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
time_select <= transport 6 ;
-- Last transaction above is marked
-- s_time <=
-- c_time_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_time_savt <= transport Std.Standard.Now ;
chk_time <= transport s_time_cnt
after (1 us - Std.Standard.Now) ;
s_time_cnt <= transport s_time_cnt + 1 ;
wait until (not s_time'Quiet) and
(s_time_savt /= Std.Standard.Now) ;
--
end process CHG8 ;
--
PGEN_CHKP_8 :
process ( chk_time )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Inertial transactions completed entirely",
chk_time = 8 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
--
with time_select select
s_time <=
c_time_2 after 10 ns,
c_time_1 after 20 ns
when 1,
--
c_time_2 after 10 ns ,
c_time_1 after 20 ns ,
c_time_2 after 30 ns ,
c_time_1 after 40 ns
when 2,
--
c_time_1 after 5 ns
when 3,
--
c_time_1 after 100 ns
when 4,
--
c_time_2 after 10 ns ,
c_time_1 after 20 ns ,
c_time_2 after 30 ns ,
c_time_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_time_1 after 40 ns when 6 ;
--
CHG9 :
process
variable correct : boolean ;
begin
case s_st_phys1_cnt is
when 0
=> null ;
-- s_st_phys1 <=
-- c_st_phys1_2 after 10 ns,
-- c_st_phys1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_phys1 =
c_st_phys1_2 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383.P9" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_phys1_select <= transport 2 ;
-- s_st_phys1 <=
-- c_st_phys1_2 after 10 ns ,
-- c_st_phys1_1 after 20 ns ,
-- c_st_phys1_2 after 30 ns ,
-- c_st_phys1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_phys1 =
c_st_phys1_2 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
st_phys1_select <= transport 3 ;
-- s_st_phys1 <=
-- c_st_phys1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_phys1_select <= transport 4 ;
-- s_st_phys1 <=
-- c_st_phys1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_phys1_select <= transport 5 ;
-- s_st_phys1 <=
-- c_st_phys1_2 after 10 ns ,
-- c_st_phys1_1 after 20 ns ,
-- c_st_phys1_2 after 30 ns ,
-- c_st_phys1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_2 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_phys1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_phys1 <=
-- c_st_phys1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_phys1_savt <= transport Std.Standard.Now ;
chk_st_phys1 <= transport s_st_phys1_cnt
after (1 us - Std.Standard.Now) ;
s_st_phys1_cnt <= transport s_st_phys1_cnt + 1 ;
wait until (not s_st_phys1'Quiet) and
(s_st_phys1_savt /= Std.Standard.Now) ;
--
end process CHG9 ;
--
PGEN_CHKP_9 :
process ( chk_st_phys1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Inertial transactions completed entirely",
chk_st_phys1 = 8 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
--
with st_phys1_select select
s_st_phys1 <=
c_st_phys1_2 after 10 ns,
c_st_phys1_1 after 20 ns
when 1,
--
c_st_phys1_2 after 10 ns ,
c_st_phys1_1 after 20 ns ,
c_st_phys1_2 after 30 ns ,
c_st_phys1_1 after 40 ns
when 2,
--
c_st_phys1_1 after 5 ns
when 3,
--
c_st_phys1_1 after 100 ns
when 4,
--
c_st_phys1_2 after 10 ns ,
c_st_phys1_1 after 20 ns ,
c_st_phys1_2 after 30 ns ,
c_st_phys1_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_phys1_1 after 40 ns when 6 ;
--
CHG10 :
process
variable correct : boolean ;
begin
case s_real_cnt is
when 0
=> null ;
-- s_real <=
-- c_real_2 after 10 ns,
-- c_real_1 after 20 ns ;
--
when 1
=> correct :=
s_real =
c_real_2 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383.P10" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
real_select <= transport 2 ;
-- s_real <=
-- c_real_2 after 10 ns ,
-- c_real_1 after 20 ns ,
-- c_real_2 after 30 ns ,
-- c_real_1 after 40 ns ;
--
when 3
=> correct :=
s_real =
c_real_2 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
real_select <= transport 3 ;
-- s_real <=
-- c_real_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
real_select <= transport 4 ;
-- s_real <=
-- c_real_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
real_select <= transport 5 ;
-- s_real <=
-- c_real_2 after 10 ns ,
-- c_real_1 after 20 ns ,
-- c_real_2 after 30 ns ,
-- c_real_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_real =
c_real_2 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
real_select <= transport 6 ;
-- Last transaction above is marked
-- s_real <=
-- c_real_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_real_savt <= transport Std.Standard.Now ;
chk_real <= transport s_real_cnt
after (1 us - Std.Standard.Now) ;
s_real_cnt <= transport s_real_cnt + 1 ;
wait until (not s_real'Quiet) and
(s_real_savt /= Std.Standard.Now) ;
--
end process CHG10 ;
--
PGEN_CHKP_10 :
process ( chk_real )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Inertial transactions completed entirely",
chk_real = 8 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
--
with real_select select
s_real <=
c_real_2 after 10 ns,
c_real_1 after 20 ns
when 1,
--
c_real_2 after 10 ns ,
c_real_1 after 20 ns ,
c_real_2 after 30 ns ,
c_real_1 after 40 ns
when 2,
--
c_real_1 after 5 ns
when 3,
--
c_real_1 after 100 ns
when 4,
--
c_real_2 after 10 ns ,
c_real_1 after 20 ns ,
c_real_2 after 30 ns ,
c_real_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_real_1 after 40 ns when 6 ;
--
CHG11 :
process
variable correct : boolean ;
begin
case s_st_real1_cnt is
when 0
=> null ;
-- s_st_real1 <=
-- c_st_real1_2 after 10 ns,
-- c_st_real1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_real1 =
c_st_real1_2 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383.P11" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_real1_select <= transport 2 ;
-- s_st_real1 <=
-- c_st_real1_2 after 10 ns ,
-- c_st_real1_1 after 20 ns ,
-- c_st_real1_2 after 30 ns ,
-- c_st_real1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_real1 =
c_st_real1_2 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
st_real1_select <= transport 3 ;
-- s_st_real1 <=
-- c_st_real1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_real1_select <= transport 4 ;
-- s_st_real1 <=
-- c_st_real1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_real1_select <= transport 5 ;
-- s_st_real1 <=
-- c_st_real1_2 after 10 ns ,
-- c_st_real1_1 after 20 ns ,
-- c_st_real1_2 after 30 ns ,
-- c_st_real1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_real1 =
c_st_real1_2 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_real1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_real1 <=
-- c_st_real1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_real1_savt <= transport Std.Standard.Now ;
chk_st_real1 <= transport s_st_real1_cnt
after (1 us - Std.Standard.Now) ;
s_st_real1_cnt <= transport s_st_real1_cnt + 1 ;
wait until (not s_st_real1'Quiet) and
(s_st_real1_savt /= Std.Standard.Now) ;
--
end process CHG11 ;
--
PGEN_CHKP_11 :
process ( chk_st_real1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P11" ,
"Inertial transactions completed entirely",
chk_st_real1 = 8 ) ;
end if ;
end process PGEN_CHKP_11 ;
--
--
with st_real1_select select
s_st_real1 <=
c_st_real1_2 after 10 ns,
c_st_real1_1 after 20 ns
when 1,
--
c_st_real1_2 after 10 ns ,
c_st_real1_1 after 20 ns ,
c_st_real1_2 after 30 ns ,
c_st_real1_1 after 40 ns
when 2,
--
c_st_real1_1 after 5 ns
when 3,
--
c_st_real1_1 after 100 ns
when 4,
--
c_st_real1_2 after 10 ns ,
c_st_real1_1 after 20 ns ,
c_st_real1_2 after 30 ns ,
c_st_real1_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_real1_1 after 40 ns when 6 ;
--
CHG12 :
process
variable correct : boolean ;
begin
case s_st_rec1_cnt is
when 0
=> null ;
-- s_st_rec1 <=
-- c_st_rec1_2 after 10 ns,
-- c_st_rec1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1 =
c_st_rec1_2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383.P12" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec1_select <= transport 2 ;
-- s_st_rec1 <=
-- c_st_rec1_2 after 10 ns ,
-- c_st_rec1_1 after 20 ns ,
-- c_st_rec1_2 after 30 ns ,
-- c_st_rec1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1 =
c_st_rec1_2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
st_rec1_select <= transport 3 ;
-- s_st_rec1 <=
-- c_st_rec1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_select <= transport 4 ;
-- s_st_rec1 <=
-- c_st_rec1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec1_select <= transport 5 ;
-- s_st_rec1 <=
-- c_st_rec1_2 after 10 ns ,
-- c_st_rec1_1 after 20 ns ,
-- c_st_rec1_2 after 30 ns ,
-- c_st_rec1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec1 <=
-- c_st_rec1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec1_savt <= transport Std.Standard.Now ;
chk_st_rec1 <= transport s_st_rec1_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec1_cnt <= transport s_st_rec1_cnt + 1 ;
wait until (not s_st_rec1'Quiet) and
(s_st_rec1_savt /= Std.Standard.Now) ;
--
end process CHG12 ;
--
PGEN_CHKP_12 :
process ( chk_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P12" ,
"Inertial transactions completed entirely",
chk_st_rec1 = 8 ) ;
end if ;
end process PGEN_CHKP_12 ;
--
--
with st_rec1_select select
s_st_rec1 <=
c_st_rec1_2 after 10 ns,
c_st_rec1_1 after 20 ns
when 1,
--
c_st_rec1_2 after 10 ns ,
c_st_rec1_1 after 20 ns ,
c_st_rec1_2 after 30 ns ,
c_st_rec1_1 after 40 ns
when 2,
--
c_st_rec1_1 after 5 ns
when 3,
--
c_st_rec1_1 after 100 ns
when 4,
--
c_st_rec1_2 after 10 ns ,
c_st_rec1_1 after 20 ns ,
c_st_rec1_2 after 30 ns ,
c_st_rec1_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_rec1_1 after 40 ns when 6 ;
--
CHG13 :
process
variable correct : boolean ;
begin
case s_st_rec2_cnt is
when 0
=> null ;
-- s_st_rec2 <=
-- c_st_rec2_2 after 10 ns,
-- c_st_rec2_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2 =
c_st_rec2_2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383.P13" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec2_select <= transport 2 ;
-- s_st_rec2 <=
-- c_st_rec2_2 after 10 ns ,
-- c_st_rec2_1 after 20 ns ,
-- c_st_rec2_2 after 30 ns ,
-- c_st_rec2_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2 =
c_st_rec2_2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
st_rec2_select <= transport 3 ;
-- s_st_rec2 <=
-- c_st_rec2_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec2_select <= transport 4 ;
-- s_st_rec2 <=
-- c_st_rec2_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec2_select <= transport 5 ;
-- s_st_rec2 <=
-- c_st_rec2_2 after 10 ns ,
-- c_st_rec2_1 after 20 ns ,
-- c_st_rec2_2 after 30 ns ,
-- c_st_rec2_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec2_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec2 <=
-- c_st_rec2_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec2_savt <= transport Std.Standard.Now ;
chk_st_rec2 <= transport s_st_rec2_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec2_cnt <= transport s_st_rec2_cnt + 1 ;
wait until (not s_st_rec2'Quiet) and
(s_st_rec2_savt /= Std.Standard.Now) ;
--
end process CHG13 ;
--
PGEN_CHKP_13 :
process ( chk_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P13" ,
"Inertial transactions completed entirely",
chk_st_rec2 = 8 ) ;
end if ;
end process PGEN_CHKP_13 ;
--
--
with st_rec2_select select
s_st_rec2 <=
c_st_rec2_2 after 10 ns,
c_st_rec2_1 after 20 ns
when 1,
--
c_st_rec2_2 after 10 ns ,
c_st_rec2_1 after 20 ns ,
c_st_rec2_2 after 30 ns ,
c_st_rec2_1 after 40 ns
when 2,
--
c_st_rec2_1 after 5 ns
when 3,
--
c_st_rec2_1 after 100 ns
when 4,
--
c_st_rec2_2 after 10 ns ,
c_st_rec2_1 after 20 ns ,
c_st_rec2_2 after 30 ns ,
c_st_rec2_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_rec2_1 after 40 ns when 6 ;
--
CHG14 :
process
variable correct : boolean ;
begin
case s_st_rec3_cnt is
when 0
=> null ;
-- s_st_rec3 <=
-- c_st_rec3_2 after 10 ns,
-- c_st_rec3_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3 =
c_st_rec3_2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383.P14" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec3_select <= transport 2 ;
-- s_st_rec3 <=
-- c_st_rec3_2 after 10 ns ,
-- c_st_rec3_1 after 20 ns ,
-- c_st_rec3_2 after 30 ns ,
-- c_st_rec3_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3 =
c_st_rec3_2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
st_rec3_select <= transport 3 ;
-- s_st_rec3 <=
-- c_st_rec3_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 4 ;
-- s_st_rec3 <=
-- c_st_rec3_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 5 ;
-- s_st_rec3 <=
-- c_st_rec3_2 after 10 ns ,
-- c_st_rec3_1 after 20 ns ,
-- c_st_rec3_2 after 30 ns ,
-- c_st_rec3_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec3 <=
-- c_st_rec3_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec3_savt <= transport Std.Standard.Now ;
chk_st_rec3 <= transport s_st_rec3_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec3_cnt <= transport s_st_rec3_cnt + 1 ;
wait until (not s_st_rec3'Quiet) and
(s_st_rec3_savt /= Std.Standard.Now) ;
--
end process CHG14 ;
--
PGEN_CHKP_14 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P14" ,
"Inertial transactions completed entirely",
chk_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_14 ;
--
--
with st_rec3_select select
s_st_rec3 <=
c_st_rec3_2 after 10 ns,
c_st_rec3_1 after 20 ns
when 1,
--
c_st_rec3_2 after 10 ns ,
c_st_rec3_1 after 20 ns ,
c_st_rec3_2 after 30 ns ,
c_st_rec3_1 after 40 ns
when 2,
--
c_st_rec3_1 after 5 ns
when 3,
--
c_st_rec3_1 after 100 ns
when 4,
--
c_st_rec3_2 after 10 ns ,
c_st_rec3_1 after 20 ns ,
c_st_rec3_2 after 30 ns ,
c_st_rec3_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_rec3_1 after 40 ns when 6 ;
--
CHG15 :
process
variable correct : boolean ;
begin
case s_st_arr1_cnt is
when 0
=> null ;
-- s_st_arr1 <=
-- c_st_arr1_2 after 10 ns,
-- c_st_arr1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr1 =
c_st_arr1_2 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383.P15" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr1_select <= transport 2 ;
-- s_st_arr1 <=
-- c_st_arr1_2 after 10 ns ,
-- c_st_arr1_1 after 20 ns ,
-- c_st_arr1_2 after 30 ns ,
-- c_st_arr1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr1 =
c_st_arr1_2 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
st_arr1_select <= transport 3 ;
-- s_st_arr1 <=
-- c_st_arr1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr1_select <= transport 4 ;
-- s_st_arr1 <=
-- c_st_arr1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_arr1_select <= transport 5 ;
-- s_st_arr1 <=
-- c_st_arr1_2 after 10 ns ,
-- c_st_arr1_1 after 20 ns ,
-- c_st_arr1_2 after 30 ns ,
-- c_st_arr1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_2 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_arr1 <=
-- c_st_arr1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_arr1_savt <= transport Std.Standard.Now ;
chk_st_arr1 <= transport s_st_arr1_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr1_cnt <= transport s_st_arr1_cnt + 1 ;
wait until (not s_st_arr1'Quiet) and
(s_st_arr1_savt /= Std.Standard.Now) ;
--
end process CHG15 ;
--
PGEN_CHKP_15 :
process ( chk_st_arr1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P15" ,
"Inertial transactions completed entirely",
chk_st_arr1 = 8 ) ;
end if ;
end process PGEN_CHKP_15 ;
--
--
with st_arr1_select select
s_st_arr1 <=
c_st_arr1_2 after 10 ns,
c_st_arr1_1 after 20 ns
when 1,
--
c_st_arr1_2 after 10 ns ,
c_st_arr1_1 after 20 ns ,
c_st_arr1_2 after 30 ns ,
c_st_arr1_1 after 40 ns
when 2,
--
c_st_arr1_1 after 5 ns
when 3,
--
c_st_arr1_1 after 100 ns
when 4,
--
c_st_arr1_2 after 10 ns ,
c_st_arr1_1 after 20 ns ,
c_st_arr1_2 after 30 ns ,
c_st_arr1_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_arr1_1 after 40 ns when 6 ;
--
CHG16 :
process
variable correct : boolean ;
begin
case s_st_arr2_cnt is
when 0
=> null ;
-- s_st_arr2 <=
-- c_st_arr2_2 after 10 ns,
-- c_st_arr2_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr2 =
c_st_arr2_2 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383.P16" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr2_select <= transport 2 ;
-- s_st_arr2 <=
-- c_st_arr2_2 after 10 ns ,
-- c_st_arr2_1 after 20 ns ,
-- c_st_arr2_2 after 30 ns ,
-- c_st_arr2_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr2 =
c_st_arr2_2 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
st_arr2_select <= transport 3 ;
-- s_st_arr2 <=
-- c_st_arr2_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_select <= transport 4 ;
-- s_st_arr2 <=
-- c_st_arr2_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_arr2_select <= transport 5 ;
-- s_st_arr2 <=
-- c_st_arr2_2 after 10 ns ,
-- c_st_arr2_1 after 20 ns ,
-- c_st_arr2_2 after 30 ns ,
-- c_st_arr2_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_2 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_arr2 <=
-- c_st_arr2_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_arr2_savt <= transport Std.Standard.Now ;
chk_st_arr2 <= transport s_st_arr2_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr2_cnt <= transport s_st_arr2_cnt + 1 ;
wait until (not s_st_arr2'Quiet) and
(s_st_arr2_savt /= Std.Standard.Now) ;
--
end process CHG16 ;
--
PGEN_CHKP_16 :
process ( chk_st_arr2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P16" ,
"Inertial transactions completed entirely",
chk_st_arr2 = 8 ) ;
end if ;
end process PGEN_CHKP_16 ;
--
--
with st_arr2_select select
s_st_arr2 <=
c_st_arr2_2 after 10 ns,
c_st_arr2_1 after 20 ns
when 1,
--
c_st_arr2_2 after 10 ns ,
c_st_arr2_1 after 20 ns ,
c_st_arr2_2 after 30 ns ,
c_st_arr2_1 after 40 ns
when 2,
--
c_st_arr2_1 after 5 ns
when 3,
--
c_st_arr2_1 after 100 ns
when 4,
--
c_st_arr2_2 after 10 ns ,
c_st_arr2_1 after 20 ns ,
c_st_arr2_2 after 30 ns ,
c_st_arr2_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_arr2_1 after 40 ns when 6 ;
--
CHG17 :
process
variable correct : boolean ;
begin
case s_st_arr3_cnt is
when 0
=> null ;
-- s_st_arr3 <=
-- c_st_arr3_2 after 10 ns,
-- c_st_arr3_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr3 =
c_st_arr3_2 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383.P17" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr3_select <= transport 2 ;
-- s_st_arr3 <=
-- c_st_arr3_2 after 10 ns ,
-- c_st_arr3_1 after 20 ns ,
-- c_st_arr3_2 after 30 ns ,
-- c_st_arr3_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr3 =
c_st_arr3_2 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
st_arr3_select <= transport 3 ;
-- s_st_arr3 <=
-- c_st_arr3_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr3_select <= transport 4 ;
-- s_st_arr3 <=
-- c_st_arr3_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_arr3_select <= transport 5 ;
-- s_st_arr3 <=
-- c_st_arr3_2 after 10 ns ,
-- c_st_arr3_1 after 20 ns ,
-- c_st_arr3_2 after 30 ns ,
-- c_st_arr3_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_2 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr3_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_arr3 <=
-- c_st_arr3_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00383" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_arr3_savt <= transport Std.Standard.Now ;
chk_st_arr3 <= transport s_st_arr3_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr3_cnt <= transport s_st_arr3_cnt + 1 ;
wait until (not s_st_arr3'Quiet) and
(s_st_arr3_savt /= Std.Standard.Now) ;
--
end process CHG17 ;
--
PGEN_CHKP_17 :
process ( chk_st_arr3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P17" ,
"Inertial transactions completed entirely",
chk_st_arr3 = 8 ) ;
end if ;
end process PGEN_CHKP_17 ;
--
--
with st_arr3_select select
s_st_arr3 <=
c_st_arr3_2 after 10 ns,
c_st_arr3_1 after 20 ns
when 1,
--
c_st_arr3_2 after 10 ns ,
c_st_arr3_1 after 20 ns ,
c_st_arr3_2 after 30 ns ,
c_st_arr3_1 after 40 ns
when 2,
--
c_st_arr3_1 after 5 ns
when 3,
--
c_st_arr3_1 after 100 ns
when 4,
--
c_st_arr3_2 after 10 ns ,
c_st_arr3_1 after 20 ns ,
c_st_arr3_2 after 30 ns ,
c_st_arr3_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_arr3_1 after 40 ns when 6 ;
--
end ARCH00383 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00383_Test_Bench is
signal s_boolean : boolean
:= c_boolean_1 ;
signal s_bit : bit
:= c_bit_1 ;
signal s_severity_level : severity_level
:= c_severity_level_1 ;
signal s_character : character
:= c_character_1 ;
signal s_st_enum1 : st_enum1
:= c_st_enum1_1 ;
signal s_integer : integer
:= c_integer_1 ;
signal s_st_int1 : st_int1
:= c_st_int1_1 ;
signal s_time : time
:= c_time_1 ;
signal s_st_phys1 : st_phys1
:= c_st_phys1_1 ;
signal s_real : real
:= c_real_1 ;
signal s_st_real1 : st_real1
:= c_st_real1_1 ;
signal s_st_rec1 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
signal s_st_arr1 : st_arr1
:= c_st_arr1_1 ;
signal s_st_arr2 : st_arr2
:= c_st_arr2_1 ;
signal s_st_arr3 : st_arr3
:= c_st_arr3_1 ;
--
end ENT00383_Test_Bench ;
--
--
architecture ARCH00383_Test_Bench of ENT00383_Test_Bench is
begin
L1:
block
component UUT
port (
s_boolean : inout boolean
; s_bit : inout bit
; s_severity_level : inout severity_level
; s_character : inout character
; s_st_enum1 : inout st_enum1
; s_integer : inout integer
; s_st_int1 : inout st_int1
; s_time : inout time
; s_st_phys1 : inout st_phys1
; s_real : inout real
; s_st_real1 : inout st_real1
; s_st_rec1 : inout st_rec1
; s_st_rec2 : inout st_rec2
; s_st_rec3 : inout st_rec3
; s_st_arr1 : inout st_arr1
; s_st_arr2 : inout st_arr2
; s_st_arr3 : inout st_arr3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00383 ( ARCH00383 ) ;
begin
CIS1 : UUT
port map (
s_boolean
, s_bit
, s_severity_level
, s_character
, s_st_enum1
, s_integer
, s_st_int1
, s_time
, s_st_phys1
, s_real
, s_st_real1
, s_st_rec1
, s_st_rec2
, s_st_rec3
, s_st_arr1
, s_st_arr2
, s_st_arr3
)
;
end block L1 ;
end ARCH00383_Test_Bench ;
| gpl-3.0 | 258cee082203bb5a0fbd71127058a3bb | 0.466475 | 3.785609 | false | false | false | false |
wsoltys/AtomFpga | src/AVR8/Memory/XPM10Kx16.vhd | 1 | 35,273 | --************************************************************************************************
-- 8Kx16(8 KB) PM RAM for AVR Core(Xilinx)
-- Version 0.1
-- Designed by Ruslan Lepetenok
-- Modified by Jack Gassett for use with Papilio
-- Modified 11.06.2009
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.SynthCtrlPack.all; -- Synthesis control
use WORK.prog_mem_init_pkg.all; -- Init file for program memory.
-- For Synplicity Synplify
--library virtexe;
--use virtexe.components.all;
-- Aldec
library unisim;
use unisim.vcomponents.all;
entity XPM10Kx16 is port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(13 downto 0);
din : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(15 downto 0);
we : in std_logic
);
end XPM10Kx16;
architecture RTL of XPM10Kx16 is
type RAMBlDOut_Type is array(2**(address'length-10)-1 downto 0) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
signal WEB : std_logic_vector(2**(address'length-10)-1 downto 0);
signal gnd : std_logic;
signal DIP : STD_LOGIC_VECTOR(1 downto 0) := "11";
signal SSR : STD_LOGIC := '0'; -- Don't use the output resets.
begin
gnd <= '0';
WEB_Dcd:for i in WEB'range generate
WEB(i) <= '1' when (we='1' and address(address'high downto 10)=i) else '0';
end generate ;
--RAM_Inst:for i in 0 to 2**(address'length-10)-1 generate
RAM_Word0:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word0_INIT_00,
INIT_01 => PM_Inst_RAM_Word0_INIT_01,
INIT_02 => PM_Inst_RAM_Word0_INIT_02,
INIT_03 => PM_Inst_RAM_Word0_INIT_03,
INIT_04 => PM_Inst_RAM_Word0_INIT_04,
INIT_05 => PM_Inst_RAM_Word0_INIT_05,
INIT_06 => PM_Inst_RAM_Word0_INIT_06,
INIT_07 => PM_Inst_RAM_Word0_INIT_07,
INIT_08 => PM_Inst_RAM_Word0_INIT_08,
INIT_09 => PM_Inst_RAM_Word0_INIT_09,
INIT_0A => PM_Inst_RAM_Word0_INIT_0A,
INIT_0B => PM_Inst_RAM_Word0_INIT_0B,
INIT_0C => PM_Inst_RAM_Word0_INIT_0C,
INIT_0D => PM_Inst_RAM_Word0_INIT_0D,
INIT_0E => PM_Inst_RAM_Word0_INIT_0E,
INIT_0F => PM_Inst_RAM_Word0_INIT_0F,
INIT_10 => PM_Inst_RAM_Word0_INIT_10,
INIT_11 => PM_Inst_RAM_Word0_INIT_11,
INIT_12 => PM_Inst_RAM_Word0_INIT_12,
INIT_13 => PM_Inst_RAM_Word0_INIT_13,
INIT_14 => PM_Inst_RAM_Word0_INIT_14,
INIT_15 => PM_Inst_RAM_Word0_INIT_15,
INIT_16 => PM_Inst_RAM_Word0_INIT_16,
INIT_17 => PM_Inst_RAM_Word0_INIT_17,
INIT_18 => PM_Inst_RAM_Word0_INIT_18,
INIT_19 => PM_Inst_RAM_Word0_INIT_19,
INIT_1A => PM_Inst_RAM_Word0_INIT_1A,
INIT_1B => PM_Inst_RAM_Word0_INIT_1B,
INIT_1C => PM_Inst_RAM_Word0_INIT_1C,
INIT_1D => PM_Inst_RAM_Word0_INIT_1D,
INIT_1E => PM_Inst_RAM_Word0_INIT_1E,
INIT_1F => PM_Inst_RAM_Word0_INIT_1F,
INIT_20 => PM_Inst_RAM_Word0_INIT_20,
INIT_21 => PM_Inst_RAM_Word0_INIT_21,
INIT_22 => PM_Inst_RAM_Word0_INIT_22,
INIT_23 => PM_Inst_RAM_Word0_INIT_23,
INIT_24 => PM_Inst_RAM_Word0_INIT_24,
INIT_25 => PM_Inst_RAM_Word0_INIT_25,
INIT_26 => PM_Inst_RAM_Word0_INIT_26,
INIT_27 => PM_Inst_RAM_Word0_INIT_27,
INIT_28 => PM_Inst_RAM_Word0_INIT_28,
INIT_29 => PM_Inst_RAM_Word0_INIT_29,
INIT_2A => PM_Inst_RAM_Word0_INIT_2A,
INIT_2B => PM_Inst_RAM_Word0_INIT_2B,
INIT_2C => PM_Inst_RAM_Word0_INIT_2C,
INIT_2D => PM_Inst_RAM_Word0_INIT_2D,
INIT_2E => PM_Inst_RAM_Word0_INIT_2E,
INIT_2F => PM_Inst_RAM_Word0_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word0_INIT_30,
INIT_31 => PM_Inst_RAM_Word0_INIT_31,
INIT_32 => PM_Inst_RAM_Word0_INIT_32,
INIT_33 => PM_Inst_RAM_Word0_INIT_33,
INIT_34 => PM_Inst_RAM_Word0_INIT_34,
INIT_35 => PM_Inst_RAM_Word0_INIT_35,
INIT_36 => PM_Inst_RAM_Word0_INIT_36,
INIT_37 => PM_Inst_RAM_Word0_INIT_37,
INIT_38 => PM_Inst_RAM_Word0_INIT_38,
INIT_39 => PM_Inst_RAM_Word0_INIT_39,
INIT_3A => PM_Inst_RAM_Word0_INIT_3A,
INIT_3B => PM_Inst_RAM_Word0_INIT_3B,
INIT_3C => PM_Inst_RAM_Word0_INIT_3C,
INIT_3D => PM_Inst_RAM_Word0_INIT_3D,
INIT_3E => PM_Inst_RAM_Word0_INIT_3E,
INIT_3F => PM_Inst_RAM_Word0_INIT_3F
)
port map(
DO => RAMBlDOut(0)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(0)
);
RAM_Word1:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word1_INIT_00,
INIT_01 => PM_Inst_RAM_Word1_INIT_01,
INIT_02 => PM_Inst_RAM_Word1_INIT_02,
INIT_03 => PM_Inst_RAM_Word1_INIT_03,
INIT_04 => PM_Inst_RAM_Word1_INIT_04,
INIT_05 => PM_Inst_RAM_Word1_INIT_05,
INIT_06 => PM_Inst_RAM_Word1_INIT_06,
INIT_07 => PM_Inst_RAM_Word1_INIT_07,
INIT_08 => PM_Inst_RAM_Word1_INIT_08,
INIT_09 => PM_Inst_RAM_Word1_INIT_09,
INIT_0A => PM_Inst_RAM_Word1_INIT_0A,
INIT_0B => PM_Inst_RAM_Word1_INIT_0B,
INIT_0C => PM_Inst_RAM_Word1_INIT_0C,
INIT_0D => PM_Inst_RAM_Word1_INIT_0D,
INIT_0E => PM_Inst_RAM_Word1_INIT_0E,
INIT_0F => PM_Inst_RAM_Word1_INIT_0F,
INIT_10 => PM_Inst_RAM_Word1_INIT_10,
INIT_11 => PM_Inst_RAM_Word1_INIT_11,
INIT_12 => PM_Inst_RAM_Word1_INIT_12,
INIT_13 => PM_Inst_RAM_Word1_INIT_13,
INIT_14 => PM_Inst_RAM_Word1_INIT_14,
INIT_15 => PM_Inst_RAM_Word1_INIT_15,
INIT_16 => PM_Inst_RAM_Word1_INIT_16,
INIT_17 => PM_Inst_RAM_Word1_INIT_17,
INIT_18 => PM_Inst_RAM_Word1_INIT_18,
INIT_19 => PM_Inst_RAM_Word1_INIT_19,
INIT_1A => PM_Inst_RAM_Word1_INIT_1A,
INIT_1B => PM_Inst_RAM_Word1_INIT_1B,
INIT_1C => PM_Inst_RAM_Word1_INIT_1C,
INIT_1D => PM_Inst_RAM_Word1_INIT_1D,
INIT_1E => PM_Inst_RAM_Word1_INIT_1E,
INIT_1F => PM_Inst_RAM_Word1_INIT_1F,
INIT_20 => PM_Inst_RAM_Word1_INIT_20,
INIT_21 => PM_Inst_RAM_Word1_INIT_21,
INIT_22 => PM_Inst_RAM_Word1_INIT_22,
INIT_23 => PM_Inst_RAM_Word1_INIT_23,
INIT_24 => PM_Inst_RAM_Word1_INIT_24,
INIT_25 => PM_Inst_RAM_Word1_INIT_25,
INIT_26 => PM_Inst_RAM_Word1_INIT_26,
INIT_27 => PM_Inst_RAM_Word1_INIT_27,
INIT_28 => PM_Inst_RAM_Word1_INIT_28,
INIT_29 => PM_Inst_RAM_Word1_INIT_29,
INIT_2A => PM_Inst_RAM_Word1_INIT_2A,
INIT_2B => PM_Inst_RAM_Word1_INIT_2B,
INIT_2C => PM_Inst_RAM_Word1_INIT_2C,
INIT_2D => PM_Inst_RAM_Word1_INIT_2D,
INIT_2E => PM_Inst_RAM_Word1_INIT_2E,
INIT_2F => PM_Inst_RAM_Word1_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word1_INIT_30,
INIT_31 => PM_Inst_RAM_Word1_INIT_31,
INIT_32 => PM_Inst_RAM_Word1_INIT_32,
INIT_33 => PM_Inst_RAM_Word1_INIT_33,
INIT_34 => PM_Inst_RAM_Word1_INIT_34,
INIT_35 => PM_Inst_RAM_Word1_INIT_35,
INIT_36 => PM_Inst_RAM_Word1_INIT_36,
INIT_37 => PM_Inst_RAM_Word1_INIT_37,
INIT_38 => PM_Inst_RAM_Word1_INIT_38,
INIT_39 => PM_Inst_RAM_Word1_INIT_39,
INIT_3A => PM_Inst_RAM_Word1_INIT_3A,
INIT_3B => PM_Inst_RAM_Word1_INIT_3B,
INIT_3C => PM_Inst_RAM_Word1_INIT_3C,
INIT_3D => PM_Inst_RAM_Word1_INIT_3D,
INIT_3E => PM_Inst_RAM_Word1_INIT_3E,
INIT_3F => PM_Inst_RAM_Word1_INIT_3F
)
port map(
DO => RAMBlDOut(1)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(1)
);
RAM_Word2:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word2_INIT_00,
INIT_01 => PM_Inst_RAM_Word2_INIT_01,
INIT_02 => PM_Inst_RAM_Word2_INIT_02,
INIT_03 => PM_Inst_RAM_Word2_INIT_03,
INIT_04 => PM_Inst_RAM_Word2_INIT_04,
INIT_05 => PM_Inst_RAM_Word2_INIT_05,
INIT_06 => PM_Inst_RAM_Word2_INIT_06,
INIT_07 => PM_Inst_RAM_Word2_INIT_07,
INIT_08 => PM_Inst_RAM_Word2_INIT_08,
INIT_09 => PM_Inst_RAM_Word2_INIT_09,
INIT_0A => PM_Inst_RAM_Word2_INIT_0A,
INIT_0B => PM_Inst_RAM_Word2_INIT_0B,
INIT_0C => PM_Inst_RAM_Word2_INIT_0C,
INIT_0D => PM_Inst_RAM_Word2_INIT_0D,
INIT_0E => PM_Inst_RAM_Word2_INIT_0E,
INIT_0F => PM_Inst_RAM_Word2_INIT_0F,
INIT_10 => PM_Inst_RAM_Word2_INIT_10,
INIT_11 => PM_Inst_RAM_Word2_INIT_11,
INIT_12 => PM_Inst_RAM_Word2_INIT_12,
INIT_13 => PM_Inst_RAM_Word2_INIT_13,
INIT_14 => PM_Inst_RAM_Word2_INIT_14,
INIT_15 => PM_Inst_RAM_Word2_INIT_15,
INIT_16 => PM_Inst_RAM_Word2_INIT_16,
INIT_17 => PM_Inst_RAM_Word2_INIT_17,
INIT_18 => PM_Inst_RAM_Word2_INIT_18,
INIT_19 => PM_Inst_RAM_Word2_INIT_19,
INIT_1A => PM_Inst_RAM_Word2_INIT_1A,
INIT_1B => PM_Inst_RAM_Word2_INIT_1B,
INIT_1C => PM_Inst_RAM_Word2_INIT_1C,
INIT_1D => PM_Inst_RAM_Word2_INIT_1D,
INIT_1E => PM_Inst_RAM_Word2_INIT_1E,
INIT_1F => PM_Inst_RAM_Word2_INIT_1F,
INIT_20 => PM_Inst_RAM_Word2_INIT_20,
INIT_21 => PM_Inst_RAM_Word2_INIT_21,
INIT_22 => PM_Inst_RAM_Word2_INIT_22,
INIT_23 => PM_Inst_RAM_Word2_INIT_23,
INIT_24 => PM_Inst_RAM_Word2_INIT_24,
INIT_25 => PM_Inst_RAM_Word2_INIT_25,
INIT_26 => PM_Inst_RAM_Word2_INIT_26,
INIT_27 => PM_Inst_RAM_Word2_INIT_27,
INIT_28 => PM_Inst_RAM_Word2_INIT_28,
INIT_29 => PM_Inst_RAM_Word2_INIT_29,
INIT_2A => PM_Inst_RAM_Word2_INIT_2A,
INIT_2B => PM_Inst_RAM_Word2_INIT_2B,
INIT_2C => PM_Inst_RAM_Word2_INIT_2C,
INIT_2D => PM_Inst_RAM_Word2_INIT_2D,
INIT_2E => PM_Inst_RAM_Word2_INIT_2E,
INIT_2F => PM_Inst_RAM_Word2_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word2_INIT_30,
INIT_31 => PM_Inst_RAM_Word2_INIT_31,
INIT_32 => PM_Inst_RAM_Word2_INIT_32,
INIT_33 => PM_Inst_RAM_Word2_INIT_33,
INIT_34 => PM_Inst_RAM_Word2_INIT_34,
INIT_35 => PM_Inst_RAM_Word2_INIT_35,
INIT_36 => PM_Inst_RAM_Word2_INIT_36,
INIT_37 => PM_Inst_RAM_Word2_INIT_37,
INIT_38 => PM_Inst_RAM_Word2_INIT_38,
INIT_39 => PM_Inst_RAM_Word2_INIT_39,
INIT_3A => PM_Inst_RAM_Word2_INIT_3A,
INIT_3B => PM_Inst_RAM_Word2_INIT_3B,
INIT_3C => PM_Inst_RAM_Word2_INIT_3C,
INIT_3D => PM_Inst_RAM_Word2_INIT_3D,
INIT_3E => PM_Inst_RAM_Word2_INIT_3E,
INIT_3F => PM_Inst_RAM_Word2_INIT_3F
)
port map(
DO => RAMBlDOut(2)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(2)
);
RAM_Word3:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word3_INIT_00,
INIT_01 => PM_Inst_RAM_Word3_INIT_01,
INIT_02 => PM_Inst_RAM_Word3_INIT_02,
INIT_03 => PM_Inst_RAM_Word3_INIT_03,
INIT_04 => PM_Inst_RAM_Word3_INIT_04,
INIT_05 => PM_Inst_RAM_Word3_INIT_05,
INIT_06 => PM_Inst_RAM_Word3_INIT_06,
INIT_07 => PM_Inst_RAM_Word3_INIT_07,
INIT_08 => PM_Inst_RAM_Word3_INIT_08,
INIT_09 => PM_Inst_RAM_Word3_INIT_09,
INIT_0A => PM_Inst_RAM_Word3_INIT_0A,
INIT_0B => PM_Inst_RAM_Word3_INIT_0B,
INIT_0C => PM_Inst_RAM_Word3_INIT_0C,
INIT_0D => PM_Inst_RAM_Word3_INIT_0D,
INIT_0E => PM_Inst_RAM_Word3_INIT_0E,
INIT_0F => PM_Inst_RAM_Word3_INIT_0F,
INIT_10 => PM_Inst_RAM_Word3_INIT_10,
INIT_11 => PM_Inst_RAM_Word3_INIT_11,
INIT_12 => PM_Inst_RAM_Word3_INIT_12,
INIT_13 => PM_Inst_RAM_Word3_INIT_13,
INIT_14 => PM_Inst_RAM_Word3_INIT_14,
INIT_15 => PM_Inst_RAM_Word3_INIT_15,
INIT_16 => PM_Inst_RAM_Word3_INIT_16,
INIT_17 => PM_Inst_RAM_Word3_INIT_17,
INIT_18 => PM_Inst_RAM_Word3_INIT_18,
INIT_19 => PM_Inst_RAM_Word3_INIT_19,
INIT_1A => PM_Inst_RAM_Word3_INIT_1A,
INIT_1B => PM_Inst_RAM_Word3_INIT_1B,
INIT_1C => PM_Inst_RAM_Word3_INIT_1C,
INIT_1D => PM_Inst_RAM_Word3_INIT_1D,
INIT_1E => PM_Inst_RAM_Word3_INIT_1E,
INIT_1F => PM_Inst_RAM_Word3_INIT_1F,
INIT_20 => PM_Inst_RAM_Word3_INIT_20,
INIT_21 => PM_Inst_RAM_Word3_INIT_21,
INIT_22 => PM_Inst_RAM_Word3_INIT_22,
INIT_23 => PM_Inst_RAM_Word3_INIT_23,
INIT_24 => PM_Inst_RAM_Word3_INIT_24,
INIT_25 => PM_Inst_RAM_Word3_INIT_25,
INIT_26 => PM_Inst_RAM_Word3_INIT_26,
INIT_27 => PM_Inst_RAM_Word3_INIT_27,
INIT_28 => PM_Inst_RAM_Word3_INIT_28,
INIT_29 => PM_Inst_RAM_Word3_INIT_29,
INIT_2A => PM_Inst_RAM_Word3_INIT_2A,
INIT_2B => PM_Inst_RAM_Word3_INIT_2B,
INIT_2C => PM_Inst_RAM_Word3_INIT_2C,
INIT_2D => PM_Inst_RAM_Word3_INIT_2D,
INIT_2E => PM_Inst_RAM_Word3_INIT_2E,
INIT_2F => PM_Inst_RAM_Word3_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word3_INIT_30,
INIT_31 => PM_Inst_RAM_Word3_INIT_31,
INIT_32 => PM_Inst_RAM_Word3_INIT_32,
INIT_33 => PM_Inst_RAM_Word3_INIT_33,
INIT_34 => PM_Inst_RAM_Word3_INIT_34,
INIT_35 => PM_Inst_RAM_Word3_INIT_35,
INIT_36 => PM_Inst_RAM_Word3_INIT_36,
INIT_37 => PM_Inst_RAM_Word3_INIT_37,
INIT_38 => PM_Inst_RAM_Word3_INIT_38,
INIT_39 => PM_Inst_RAM_Word3_INIT_39,
INIT_3A => PM_Inst_RAM_Word3_INIT_3A,
INIT_3B => PM_Inst_RAM_Word3_INIT_3B,
INIT_3C => PM_Inst_RAM_Word3_INIT_3C,
INIT_3D => PM_Inst_RAM_Word3_INIT_3D,
INIT_3E => PM_Inst_RAM_Word3_INIT_3E,
INIT_3F => PM_Inst_RAM_Word3_INIT_3F
)
port map(
DO => RAMBlDOut(3)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(3)
);
RAM_Word4:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word4_INIT_00,
INIT_01 => PM_Inst_RAM_Word4_INIT_01,
INIT_02 => PM_Inst_RAM_Word4_INIT_02,
INIT_03 => PM_Inst_RAM_Word4_INIT_03,
INIT_04 => PM_Inst_RAM_Word4_INIT_04,
INIT_05 => PM_Inst_RAM_Word4_INIT_05,
INIT_06 => PM_Inst_RAM_Word4_INIT_06,
INIT_07 => PM_Inst_RAM_Word4_INIT_07,
INIT_08 => PM_Inst_RAM_Word4_INIT_08,
INIT_09 => PM_Inst_RAM_Word4_INIT_09,
INIT_0A => PM_Inst_RAM_Word4_INIT_0A,
INIT_0B => PM_Inst_RAM_Word4_INIT_0B,
INIT_0C => PM_Inst_RAM_Word4_INIT_0C,
INIT_0D => PM_Inst_RAM_Word4_INIT_0D,
INIT_0E => PM_Inst_RAM_Word4_INIT_0E,
INIT_0F => PM_Inst_RAM_Word4_INIT_0F,
INIT_10 => PM_Inst_RAM_Word4_INIT_10,
INIT_11 => PM_Inst_RAM_Word4_INIT_11,
INIT_12 => PM_Inst_RAM_Word4_INIT_12,
INIT_13 => PM_Inst_RAM_Word4_INIT_13,
INIT_14 => PM_Inst_RAM_Word4_INIT_14,
INIT_15 => PM_Inst_RAM_Word4_INIT_15,
INIT_16 => PM_Inst_RAM_Word4_INIT_16,
INIT_17 => PM_Inst_RAM_Word4_INIT_17,
INIT_18 => PM_Inst_RAM_Word4_INIT_18,
INIT_19 => PM_Inst_RAM_Word4_INIT_19,
INIT_1A => PM_Inst_RAM_Word4_INIT_1A,
INIT_1B => PM_Inst_RAM_Word4_INIT_1B,
INIT_1C => PM_Inst_RAM_Word4_INIT_1C,
INIT_1D => PM_Inst_RAM_Word4_INIT_1D,
INIT_1E => PM_Inst_RAM_Word4_INIT_1E,
INIT_1F => PM_Inst_RAM_Word4_INIT_1F,
INIT_20 => PM_Inst_RAM_Word4_INIT_20,
INIT_21 => PM_Inst_RAM_Word4_INIT_21,
INIT_22 => PM_Inst_RAM_Word4_INIT_22,
INIT_23 => PM_Inst_RAM_Word4_INIT_23,
INIT_24 => PM_Inst_RAM_Word4_INIT_24,
INIT_25 => PM_Inst_RAM_Word4_INIT_25,
INIT_26 => PM_Inst_RAM_Word4_INIT_26,
INIT_27 => PM_Inst_RAM_Word4_INIT_27,
INIT_28 => PM_Inst_RAM_Word4_INIT_28,
INIT_29 => PM_Inst_RAM_Word4_INIT_29,
INIT_2A => PM_Inst_RAM_Word4_INIT_2A,
INIT_2B => PM_Inst_RAM_Word4_INIT_2B,
INIT_2C => PM_Inst_RAM_Word4_INIT_2C,
INIT_2D => PM_Inst_RAM_Word4_INIT_2D,
INIT_2E => PM_Inst_RAM_Word4_INIT_2E,
INIT_2F => PM_Inst_RAM_Word4_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word4_INIT_30,
INIT_31 => PM_Inst_RAM_Word4_INIT_31,
INIT_32 => PM_Inst_RAM_Word4_INIT_32,
INIT_33 => PM_Inst_RAM_Word4_INIT_33,
INIT_34 => PM_Inst_RAM_Word4_INIT_34,
INIT_35 => PM_Inst_RAM_Word4_INIT_35,
INIT_36 => PM_Inst_RAM_Word4_INIT_36,
INIT_37 => PM_Inst_RAM_Word4_INIT_37,
INIT_38 => PM_Inst_RAM_Word4_INIT_38,
INIT_39 => PM_Inst_RAM_Word4_INIT_39,
INIT_3A => PM_Inst_RAM_Word4_INIT_3A,
INIT_3B => PM_Inst_RAM_Word4_INIT_3B,
INIT_3C => PM_Inst_RAM_Word4_INIT_3C,
INIT_3D => PM_Inst_RAM_Word4_INIT_3D,
INIT_3E => PM_Inst_RAM_Word4_INIT_3E,
INIT_3F => PM_Inst_RAM_Word4_INIT_3F
)
port map(
DO => RAMBlDOut(4)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(4)
);
RAM_Word5:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word5_INIT_00,
INIT_01 => PM_Inst_RAM_Word5_INIT_01,
INIT_02 => PM_Inst_RAM_Word5_INIT_02,
INIT_03 => PM_Inst_RAM_Word5_INIT_03,
INIT_04 => PM_Inst_RAM_Word5_INIT_04,
INIT_05 => PM_Inst_RAM_Word5_INIT_05,
INIT_06 => PM_Inst_RAM_Word5_INIT_06,
INIT_07 => PM_Inst_RAM_Word5_INIT_07,
INIT_08 => PM_Inst_RAM_Word5_INIT_08,
INIT_09 => PM_Inst_RAM_Word5_INIT_09,
INIT_0A => PM_Inst_RAM_Word5_INIT_0A,
INIT_0B => PM_Inst_RAM_Word5_INIT_0B,
INIT_0C => PM_Inst_RAM_Word5_INIT_0C,
INIT_0D => PM_Inst_RAM_Word5_INIT_0D,
INIT_0E => PM_Inst_RAM_Word5_INIT_0E,
INIT_0F => PM_Inst_RAM_Word5_INIT_0F,
INIT_10 => PM_Inst_RAM_Word5_INIT_10,
INIT_11 => PM_Inst_RAM_Word5_INIT_11,
INIT_12 => PM_Inst_RAM_Word5_INIT_12,
INIT_13 => PM_Inst_RAM_Word5_INIT_13,
INIT_14 => PM_Inst_RAM_Word5_INIT_14,
INIT_15 => PM_Inst_RAM_Word5_INIT_15,
INIT_16 => PM_Inst_RAM_Word5_INIT_16,
INIT_17 => PM_Inst_RAM_Word5_INIT_17,
INIT_18 => PM_Inst_RAM_Word5_INIT_18,
INIT_19 => PM_Inst_RAM_Word5_INIT_19,
INIT_1A => PM_Inst_RAM_Word5_INIT_1A,
INIT_1B => PM_Inst_RAM_Word5_INIT_1B,
INIT_1C => PM_Inst_RAM_Word5_INIT_1C,
INIT_1D => PM_Inst_RAM_Word5_INIT_1D,
INIT_1E => PM_Inst_RAM_Word5_INIT_1E,
INIT_1F => PM_Inst_RAM_Word5_INIT_1F,
INIT_20 => PM_Inst_RAM_Word5_INIT_20,
INIT_21 => PM_Inst_RAM_Word5_INIT_21,
INIT_22 => PM_Inst_RAM_Word5_INIT_22,
INIT_23 => PM_Inst_RAM_Word5_INIT_23,
INIT_24 => PM_Inst_RAM_Word5_INIT_24,
INIT_25 => PM_Inst_RAM_Word5_INIT_25,
INIT_26 => PM_Inst_RAM_Word5_INIT_26,
INIT_27 => PM_Inst_RAM_Word5_INIT_27,
INIT_28 => PM_Inst_RAM_Word5_INIT_28,
INIT_29 => PM_Inst_RAM_Word5_INIT_29,
INIT_2A => PM_Inst_RAM_Word5_INIT_2A,
INIT_2B => PM_Inst_RAM_Word5_INIT_2B,
INIT_2C => PM_Inst_RAM_Word5_INIT_2C,
INIT_2D => PM_Inst_RAM_Word5_INIT_2D,
INIT_2E => PM_Inst_RAM_Word5_INIT_2E,
INIT_2F => PM_Inst_RAM_Word5_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word5_INIT_30,
INIT_31 => PM_Inst_RAM_Word5_INIT_31,
INIT_32 => PM_Inst_RAM_Word5_INIT_32,
INIT_33 => PM_Inst_RAM_Word5_INIT_33,
INIT_34 => PM_Inst_RAM_Word5_INIT_34,
INIT_35 => PM_Inst_RAM_Word5_INIT_35,
INIT_36 => PM_Inst_RAM_Word5_INIT_36,
INIT_37 => PM_Inst_RAM_Word5_INIT_37,
INIT_38 => PM_Inst_RAM_Word5_INIT_38,
INIT_39 => PM_Inst_RAM_Word5_INIT_39,
INIT_3A => PM_Inst_RAM_Word5_INIT_3A,
INIT_3B => PM_Inst_RAM_Word5_INIT_3B,
INIT_3C => PM_Inst_RAM_Word5_INIT_3C,
INIT_3D => PM_Inst_RAM_Word5_INIT_3D,
INIT_3E => PM_Inst_RAM_Word5_INIT_3E,
INIT_3F => PM_Inst_RAM_Word5_INIT_3F
)
port map(
DO => RAMBlDOut(5)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(5)
);
RAM_Word6:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word6_INIT_00,
INIT_01 => PM_Inst_RAM_Word6_INIT_01,
INIT_02 => PM_Inst_RAM_Word6_INIT_02,
INIT_03 => PM_Inst_RAM_Word6_INIT_03,
INIT_04 => PM_Inst_RAM_Word6_INIT_04,
INIT_05 => PM_Inst_RAM_Word6_INIT_05,
INIT_06 => PM_Inst_RAM_Word6_INIT_06,
INIT_07 => PM_Inst_RAM_Word6_INIT_07,
INIT_08 => PM_Inst_RAM_Word6_INIT_08,
INIT_09 => PM_Inst_RAM_Word6_INIT_09,
INIT_0A => PM_Inst_RAM_Word6_INIT_0A,
INIT_0B => PM_Inst_RAM_Word6_INIT_0B,
INIT_0C => PM_Inst_RAM_Word6_INIT_0C,
INIT_0D => PM_Inst_RAM_Word6_INIT_0D,
INIT_0E => PM_Inst_RAM_Word6_INIT_0E,
INIT_0F => PM_Inst_RAM_Word6_INIT_0F,
INIT_10 => PM_Inst_RAM_Word6_INIT_10,
INIT_11 => PM_Inst_RAM_Word6_INIT_11,
INIT_12 => PM_Inst_RAM_Word6_INIT_12,
INIT_13 => PM_Inst_RAM_Word6_INIT_13,
INIT_14 => PM_Inst_RAM_Word6_INIT_14,
INIT_15 => PM_Inst_RAM_Word6_INIT_15,
INIT_16 => PM_Inst_RAM_Word6_INIT_16,
INIT_17 => PM_Inst_RAM_Word6_INIT_17,
INIT_18 => PM_Inst_RAM_Word6_INIT_18,
INIT_19 => PM_Inst_RAM_Word6_INIT_19,
INIT_1A => PM_Inst_RAM_Word6_INIT_1A,
INIT_1B => PM_Inst_RAM_Word6_INIT_1B,
INIT_1C => PM_Inst_RAM_Word6_INIT_1C,
INIT_1D => PM_Inst_RAM_Word6_INIT_1D,
INIT_1E => PM_Inst_RAM_Word6_INIT_1E,
INIT_1F => PM_Inst_RAM_Word6_INIT_1F,
INIT_20 => PM_Inst_RAM_Word6_INIT_20,
INIT_21 => PM_Inst_RAM_Word6_INIT_21,
INIT_22 => PM_Inst_RAM_Word6_INIT_22,
INIT_23 => PM_Inst_RAM_Word6_INIT_23,
INIT_24 => PM_Inst_RAM_Word6_INIT_24,
INIT_25 => PM_Inst_RAM_Word6_INIT_25,
INIT_26 => PM_Inst_RAM_Word6_INIT_26,
INIT_27 => PM_Inst_RAM_Word6_INIT_27,
INIT_28 => PM_Inst_RAM_Word6_INIT_28,
INIT_29 => PM_Inst_RAM_Word6_INIT_29,
INIT_2A => PM_Inst_RAM_Word6_INIT_2A,
INIT_2B => PM_Inst_RAM_Word6_INIT_2B,
INIT_2C => PM_Inst_RAM_Word6_INIT_2C,
INIT_2D => PM_Inst_RAM_Word6_INIT_2D,
INIT_2E => PM_Inst_RAM_Word6_INIT_2E,
INIT_2F => PM_Inst_RAM_Word6_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word6_INIT_30,
INIT_31 => PM_Inst_RAM_Word6_INIT_31,
INIT_32 => PM_Inst_RAM_Word6_INIT_32,
INIT_33 => PM_Inst_RAM_Word6_INIT_33,
INIT_34 => PM_Inst_RAM_Word6_INIT_34,
INIT_35 => PM_Inst_RAM_Word6_INIT_35,
INIT_36 => PM_Inst_RAM_Word6_INIT_36,
INIT_37 => PM_Inst_RAM_Word6_INIT_37,
INIT_38 => PM_Inst_RAM_Word6_INIT_38,
INIT_39 => PM_Inst_RAM_Word6_INIT_39,
INIT_3A => PM_Inst_RAM_Word6_INIT_3A,
INIT_3B => PM_Inst_RAM_Word6_INIT_3B,
INIT_3C => PM_Inst_RAM_Word6_INIT_3C,
INIT_3D => PM_Inst_RAM_Word6_INIT_3D,
INIT_3E => PM_Inst_RAM_Word6_INIT_3E,
INIT_3F => PM_Inst_RAM_Word6_INIT_3F
)
port map(
DO => RAMBlDOut(6)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(6)
);
RAM_Word7:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word7_INIT_00,
INIT_01 => PM_Inst_RAM_Word7_INIT_01,
INIT_02 => PM_Inst_RAM_Word7_INIT_02,
INIT_03 => PM_Inst_RAM_Word7_INIT_03,
INIT_04 => PM_Inst_RAM_Word7_INIT_04,
INIT_05 => PM_Inst_RAM_Word7_INIT_05,
INIT_06 => PM_Inst_RAM_Word7_INIT_06,
INIT_07 => PM_Inst_RAM_Word7_INIT_07,
INIT_08 => PM_Inst_RAM_Word7_INIT_08,
INIT_09 => PM_Inst_RAM_Word7_INIT_09,
INIT_0A => PM_Inst_RAM_Word7_INIT_0A,
INIT_0B => PM_Inst_RAM_Word7_INIT_0B,
INIT_0C => PM_Inst_RAM_Word7_INIT_0C,
INIT_0D => PM_Inst_RAM_Word7_INIT_0D,
INIT_0E => PM_Inst_RAM_Word7_INIT_0E,
INIT_0F => PM_Inst_RAM_Word7_INIT_0F,
INIT_10 => PM_Inst_RAM_Word7_INIT_10,
INIT_11 => PM_Inst_RAM_Word7_INIT_11,
INIT_12 => PM_Inst_RAM_Word7_INIT_12,
INIT_13 => PM_Inst_RAM_Word7_INIT_13,
INIT_14 => PM_Inst_RAM_Word7_INIT_14,
INIT_15 => PM_Inst_RAM_Word7_INIT_15,
INIT_16 => PM_Inst_RAM_Word7_INIT_16,
INIT_17 => PM_Inst_RAM_Word7_INIT_17,
INIT_18 => PM_Inst_RAM_Word7_INIT_18,
INIT_19 => PM_Inst_RAM_Word7_INIT_19,
INIT_1A => PM_Inst_RAM_Word7_INIT_1A,
INIT_1B => PM_Inst_RAM_Word7_INIT_1B,
INIT_1C => PM_Inst_RAM_Word7_INIT_1C,
INIT_1D => PM_Inst_RAM_Word7_INIT_1D,
INIT_1E => PM_Inst_RAM_Word7_INIT_1E,
INIT_1F => PM_Inst_RAM_Word7_INIT_1F,
INIT_20 => PM_Inst_RAM_Word7_INIT_20,
INIT_21 => PM_Inst_RAM_Word7_INIT_21,
INIT_22 => PM_Inst_RAM_Word7_INIT_22,
INIT_23 => PM_Inst_RAM_Word7_INIT_23,
INIT_24 => PM_Inst_RAM_Word7_INIT_24,
INIT_25 => PM_Inst_RAM_Word7_INIT_25,
INIT_26 => PM_Inst_RAM_Word7_INIT_26,
INIT_27 => PM_Inst_RAM_Word7_INIT_27,
INIT_28 => PM_Inst_RAM_Word7_INIT_28,
INIT_29 => PM_Inst_RAM_Word7_INIT_29,
INIT_2A => PM_Inst_RAM_Word7_INIT_2A,
INIT_2B => PM_Inst_RAM_Word7_INIT_2B,
INIT_2C => PM_Inst_RAM_Word7_INIT_2C,
INIT_2D => PM_Inst_RAM_Word7_INIT_2D,
INIT_2E => PM_Inst_RAM_Word7_INIT_2E,
INIT_2F => PM_Inst_RAM_Word7_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word7_INIT_30,
INIT_31 => PM_Inst_RAM_Word7_INIT_31,
INIT_32 => PM_Inst_RAM_Word7_INIT_32,
INIT_33 => PM_Inst_RAM_Word7_INIT_33,
INIT_34 => PM_Inst_RAM_Word7_INIT_34,
INIT_35 => PM_Inst_RAM_Word7_INIT_35,
INIT_36 => PM_Inst_RAM_Word7_INIT_36,
INIT_37 => PM_Inst_RAM_Word7_INIT_37,
INIT_38 => PM_Inst_RAM_Word7_INIT_38,
INIT_39 => PM_Inst_RAM_Word7_INIT_39,
INIT_3A => PM_Inst_RAM_Word7_INIT_3A,
INIT_3B => PM_Inst_RAM_Word7_INIT_3B,
INIT_3C => PM_Inst_RAM_Word7_INIT_3C,
INIT_3D => PM_Inst_RAM_Word7_INIT_3D,
INIT_3E => PM_Inst_RAM_Word7_INIT_3E,
INIT_3F => PM_Inst_RAM_Word7_INIT_3F
)
port map(
DO => RAMBlDOut(7)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(7)
);
--end generate;
RAM_Word8:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word7_INIT_00,
INIT_01 => PM_Inst_RAM_Word7_INIT_01,
INIT_02 => PM_Inst_RAM_Word7_INIT_02,
INIT_03 => PM_Inst_RAM_Word7_INIT_03,
INIT_04 => PM_Inst_RAM_Word7_INIT_04,
INIT_05 => PM_Inst_RAM_Word7_INIT_05,
INIT_06 => PM_Inst_RAM_Word7_INIT_06,
INIT_07 => PM_Inst_RAM_Word7_INIT_07,
INIT_08 => PM_Inst_RAM_Word7_INIT_08,
INIT_09 => PM_Inst_RAM_Word7_INIT_09,
INIT_0A => PM_Inst_RAM_Word7_INIT_0A,
INIT_0B => PM_Inst_RAM_Word7_INIT_0B,
INIT_0C => PM_Inst_RAM_Word7_INIT_0C,
INIT_0D => PM_Inst_RAM_Word7_INIT_0D,
INIT_0E => PM_Inst_RAM_Word7_INIT_0E,
INIT_0F => PM_Inst_RAM_Word7_INIT_0F,
INIT_10 => PM_Inst_RAM_Word7_INIT_10,
INIT_11 => PM_Inst_RAM_Word7_INIT_11,
INIT_12 => PM_Inst_RAM_Word7_INIT_12,
INIT_13 => PM_Inst_RAM_Word7_INIT_13,
INIT_14 => PM_Inst_RAM_Word7_INIT_14,
INIT_15 => PM_Inst_RAM_Word7_INIT_15,
INIT_16 => PM_Inst_RAM_Word7_INIT_16,
INIT_17 => PM_Inst_RAM_Word7_INIT_17,
INIT_18 => PM_Inst_RAM_Word7_INIT_18,
INIT_19 => PM_Inst_RAM_Word7_INIT_19,
INIT_1A => PM_Inst_RAM_Word7_INIT_1A,
INIT_1B => PM_Inst_RAM_Word7_INIT_1B,
INIT_1C => PM_Inst_RAM_Word7_INIT_1C,
INIT_1D => PM_Inst_RAM_Word7_INIT_1D,
INIT_1E => PM_Inst_RAM_Word7_INIT_1E,
INIT_1F => PM_Inst_RAM_Word7_INIT_1F,
INIT_20 => PM_Inst_RAM_Word7_INIT_20,
INIT_21 => PM_Inst_RAM_Word7_INIT_21,
INIT_22 => PM_Inst_RAM_Word7_INIT_22,
INIT_23 => PM_Inst_RAM_Word7_INIT_23,
INIT_24 => PM_Inst_RAM_Word7_INIT_24,
INIT_25 => PM_Inst_RAM_Word7_INIT_25,
INIT_26 => PM_Inst_RAM_Word7_INIT_26,
INIT_27 => PM_Inst_RAM_Word7_INIT_27,
INIT_28 => PM_Inst_RAM_Word7_INIT_28,
INIT_29 => PM_Inst_RAM_Word7_INIT_29,
INIT_2A => PM_Inst_RAM_Word7_INIT_2A,
INIT_2B => PM_Inst_RAM_Word7_INIT_2B,
INIT_2C => PM_Inst_RAM_Word7_INIT_2C,
INIT_2D => PM_Inst_RAM_Word7_INIT_2D,
INIT_2E => PM_Inst_RAM_Word7_INIT_2E,
INIT_2F => PM_Inst_RAM_Word7_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word7_INIT_30,
INIT_31 => PM_Inst_RAM_Word7_INIT_31,
INIT_32 => PM_Inst_RAM_Word7_INIT_32,
INIT_33 => PM_Inst_RAM_Word7_INIT_33,
INIT_34 => PM_Inst_RAM_Word7_INIT_34,
INIT_35 => PM_Inst_RAM_Word7_INIT_35,
INIT_36 => PM_Inst_RAM_Word7_INIT_36,
INIT_37 => PM_Inst_RAM_Word7_INIT_37,
INIT_38 => PM_Inst_RAM_Word7_INIT_38,
INIT_39 => PM_Inst_RAM_Word7_INIT_39,
INIT_3A => PM_Inst_RAM_Word7_INIT_3A,
INIT_3B => PM_Inst_RAM_Word7_INIT_3B,
INIT_3C => PM_Inst_RAM_Word7_INIT_3C,
INIT_3D => PM_Inst_RAM_Word7_INIT_3D,
INIT_3E => PM_Inst_RAM_Word7_INIT_3E,
INIT_3F => PM_Inst_RAM_Word7_INIT_3F
)
port map(
DO => RAMBlDOut(8)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(8)
);
--end generate;
RAM_Word9:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word7_INIT_00,
INIT_01 => PM_Inst_RAM_Word7_INIT_01,
INIT_02 => PM_Inst_RAM_Word7_INIT_02,
INIT_03 => PM_Inst_RAM_Word7_INIT_03,
INIT_04 => PM_Inst_RAM_Word7_INIT_04,
INIT_05 => PM_Inst_RAM_Word7_INIT_05,
INIT_06 => PM_Inst_RAM_Word7_INIT_06,
INIT_07 => PM_Inst_RAM_Word7_INIT_07,
INIT_08 => PM_Inst_RAM_Word7_INIT_08,
INIT_09 => PM_Inst_RAM_Word7_INIT_09,
INIT_0A => PM_Inst_RAM_Word7_INIT_0A,
INIT_0B => PM_Inst_RAM_Word7_INIT_0B,
INIT_0C => PM_Inst_RAM_Word7_INIT_0C,
INIT_0D => PM_Inst_RAM_Word7_INIT_0D,
INIT_0E => PM_Inst_RAM_Word7_INIT_0E,
INIT_0F => PM_Inst_RAM_Word7_INIT_0F,
INIT_10 => PM_Inst_RAM_Word7_INIT_10,
INIT_11 => PM_Inst_RAM_Word7_INIT_11,
INIT_12 => PM_Inst_RAM_Word7_INIT_12,
INIT_13 => PM_Inst_RAM_Word7_INIT_13,
INIT_14 => PM_Inst_RAM_Word7_INIT_14,
INIT_15 => PM_Inst_RAM_Word7_INIT_15,
INIT_16 => PM_Inst_RAM_Word7_INIT_16,
INIT_17 => PM_Inst_RAM_Word7_INIT_17,
INIT_18 => PM_Inst_RAM_Word7_INIT_18,
INIT_19 => PM_Inst_RAM_Word7_INIT_19,
INIT_1A => PM_Inst_RAM_Word7_INIT_1A,
INIT_1B => PM_Inst_RAM_Word7_INIT_1B,
INIT_1C => PM_Inst_RAM_Word7_INIT_1C,
INIT_1D => PM_Inst_RAM_Word7_INIT_1D,
INIT_1E => PM_Inst_RAM_Word7_INIT_1E,
INIT_1F => PM_Inst_RAM_Word7_INIT_1F,
INIT_20 => PM_Inst_RAM_Word7_INIT_20,
INIT_21 => PM_Inst_RAM_Word7_INIT_21,
INIT_22 => PM_Inst_RAM_Word7_INIT_22,
INIT_23 => PM_Inst_RAM_Word7_INIT_23,
INIT_24 => PM_Inst_RAM_Word7_INIT_24,
INIT_25 => PM_Inst_RAM_Word7_INIT_25,
INIT_26 => PM_Inst_RAM_Word7_INIT_26,
INIT_27 => PM_Inst_RAM_Word7_INIT_27,
INIT_28 => PM_Inst_RAM_Word7_INIT_28,
INIT_29 => PM_Inst_RAM_Word7_INIT_29,
INIT_2A => PM_Inst_RAM_Word7_INIT_2A,
INIT_2B => PM_Inst_RAM_Word7_INIT_2B,
INIT_2C => PM_Inst_RAM_Word7_INIT_2C,
INIT_2D => PM_Inst_RAM_Word7_INIT_2D,
INIT_2E => PM_Inst_RAM_Word7_INIT_2E,
INIT_2F => PM_Inst_RAM_Word7_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word7_INIT_30,
INIT_31 => PM_Inst_RAM_Word7_INIT_31,
INIT_32 => PM_Inst_RAM_Word7_INIT_32,
INIT_33 => PM_Inst_RAM_Word7_INIT_33,
INIT_34 => PM_Inst_RAM_Word7_INIT_34,
INIT_35 => PM_Inst_RAM_Word7_INIT_35,
INIT_36 => PM_Inst_RAM_Word7_INIT_36,
INIT_37 => PM_Inst_RAM_Word7_INIT_37,
INIT_38 => PM_Inst_RAM_Word7_INIT_38,
INIT_39 => PM_Inst_RAM_Word7_INIT_39,
INIT_3A => PM_Inst_RAM_Word7_INIT_3A,
INIT_3B => PM_Inst_RAM_Word7_INIT_3B,
INIT_3C => PM_Inst_RAM_Word7_INIT_3C,
INIT_3D => PM_Inst_RAM_Word7_INIT_3D,
INIT_3E => PM_Inst_RAM_Word7_INIT_3E,
INIT_3F => PM_Inst_RAM_Word7_INIT_3F
)
port map(
DO => RAMBlDOut(9)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(9)
);
--end generate;
-- Output data mux
dout <= RAMBlDOut(CONV_INTEGER(address(address'high downto 10)));
end RTL;
| apache-2.0 | f363008227db6700067f94be98c11219 | 0.598645 | 2.359082 | false | false | false | false |
TWW12/lzw | ip_repo/axi_compression_1.0/hdl/axi_compression_v1_0.vhd | 3 | 3,848 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_compression_v1_0 is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S00_AXI
C_S00_AXI_DATA_WIDTH : integer := 32;
C_S00_AXI_ADDR_WIDTH : integer := 6
);
port (
-- Users to add ports here
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S00_AXI
s00_axi_aclk : in std_logic;
s00_axi_aresetn : in std_logic;
s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_awprot : in std_logic_vector(2 downto 0);
s00_axi_awvalid : in std_logic;
s00_axi_awready : out std_logic;
s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
s00_axi_wvalid : in std_logic;
s00_axi_wready : out std_logic;
s00_axi_bresp : out std_logic_vector(1 downto 0);
s00_axi_bvalid : out std_logic;
s00_axi_bready : in std_logic;
s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_arprot : in std_logic_vector(2 downto 0);
s00_axi_arvalid : in std_logic;
s00_axi_arready : out std_logic;
s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_rresp : out std_logic_vector(1 downto 0);
s00_axi_rvalid : out std_logic;
s00_axi_rready : in std_logic
);
end axi_compression_v1_0;
architecture arch_imp of axi_compression_v1_0 is
-- component declaration
component axi_compression_v1_0_S00_AXI is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 6
);
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component axi_compression_v1_0_S00_AXI;
begin
-- Instantiation of Axi Bus Interface S00_AXI
axi_compression_v1_0_S00_AXI_inst : axi_compression_v1_0_S00_AXI
generic map (
C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH
)
port map (
S_AXI_ACLK => s00_axi_aclk,
S_AXI_ARESETN => s00_axi_aresetn,
S_AXI_AWADDR => s00_axi_awaddr,
S_AXI_AWPROT => s00_axi_awprot,
S_AXI_AWVALID => s00_axi_awvalid,
S_AXI_AWREADY => s00_axi_awready,
S_AXI_WDATA => s00_axi_wdata,
S_AXI_WSTRB => s00_axi_wstrb,
S_AXI_WVALID => s00_axi_wvalid,
S_AXI_WREADY => s00_axi_wready,
S_AXI_BRESP => s00_axi_bresp,
S_AXI_BVALID => s00_axi_bvalid,
S_AXI_BREADY => s00_axi_bready,
S_AXI_ARADDR => s00_axi_araddr,
S_AXI_ARPROT => s00_axi_arprot,
S_AXI_ARVALID => s00_axi_arvalid,
S_AXI_ARREADY => s00_axi_arready,
S_AXI_RDATA => s00_axi_rdata,
S_AXI_RRESP => s00_axi_rresp,
S_AXI_RVALID => s00_axi_rvalid,
S_AXI_RREADY => s00_axi_rready
);
-- Add user logic here
-- User logic ends
end arch_imp;
| unlicense | 3f94bda1ba7095271fc84c0ca56fb801 | 0.655405 | 2.436985 | false | false | false | false |
jairov4/accel-oil | impl/impl_test_single/simulation/behavioral/system_microblaze_0_wrapper.vhd | 1 | 93,820 | -------------------------------------------------------------------------------
-- system_microblaze_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library microblaze_v8_50_c;
use microblaze_v8_50_c.all;
entity system_microblaze_0_wrapper is
port (
CLK : in std_logic;
RESET : in std_logic;
MB_RESET : in std_logic;
INTERRUPT : in std_logic;
INTERRUPT_ADDRESS : in std_logic_vector(0 to 31);
INTERRUPT_ACK : out std_logic_vector(0 to 1);
EXT_BRK : in std_logic;
EXT_NM_BRK : in std_logic;
DBG_STOP : in std_logic;
MB_Halted : out std_logic;
MB_Error : out std_logic;
WAKEUP : in std_logic_vector(0 to 1);
SLEEP : out std_logic;
DBG_WAKEUP : out std_logic;
LOCKSTEP_MASTER_OUT : out std_logic_vector(0 to 4095);
LOCKSTEP_SLAVE_IN : in std_logic_vector(0 to 4095);
LOCKSTEP_OUT : out std_logic_vector(0 to 4095);
INSTR : in std_logic_vector(0 to 31);
IREADY : in std_logic;
IWAIT : in std_logic;
ICE : in std_logic;
IUE : in std_logic;
INSTR_ADDR : out std_logic_vector(0 to 31);
IFETCH : out std_logic;
I_AS : out std_logic;
IPLB_M_ABort : out std_logic;
IPLB_M_ABus : out std_logic_vector(0 to 31);
IPLB_M_UABus : out std_logic_vector(0 to 31);
IPLB_M_BE : out std_logic_vector(0 to 7);
IPLB_M_busLock : out std_logic;
IPLB_M_lockErr : out std_logic;
IPLB_M_MSize : out std_logic_vector(0 to 1);
IPLB_M_priority : out std_logic_vector(0 to 1);
IPLB_M_rdBurst : out std_logic;
IPLB_M_request : out std_logic;
IPLB_M_RNW : out std_logic;
IPLB_M_size : out std_logic_vector(0 to 3);
IPLB_M_TAttribute : out std_logic_vector(0 to 15);
IPLB_M_type : out std_logic_vector(0 to 2);
IPLB_M_wrBurst : out std_logic;
IPLB_M_wrDBus : out std_logic_vector(0 to 63);
IPLB_MBusy : in std_logic;
IPLB_MRdErr : in std_logic;
IPLB_MWrErr : in std_logic;
IPLB_MIRQ : in std_logic;
IPLB_MWrBTerm : in std_logic;
IPLB_MWrDAck : in std_logic;
IPLB_MAddrAck : in std_logic;
IPLB_MRdBTerm : in std_logic;
IPLB_MRdDAck : in std_logic;
IPLB_MRdDBus : in std_logic_vector(0 to 63);
IPLB_MRdWdAddr : in std_logic_vector(0 to 3);
IPLB_MRearbitrate : in std_logic;
IPLB_MSSize : in std_logic_vector(0 to 1);
IPLB_MTimeout : in std_logic;
DATA_READ : in std_logic_vector(0 to 31);
DREADY : in std_logic;
DWAIT : in std_logic;
DCE : in std_logic;
DUE : in std_logic;
DATA_WRITE : out std_logic_vector(0 to 31);
DATA_ADDR : out std_logic_vector(0 to 31);
D_AS : out std_logic;
READ_STROBE : out std_logic;
WRITE_STROBE : out std_logic;
BYTE_ENABLE : out std_logic_vector(0 to 3);
DPLB_M_ABort : out std_logic;
DPLB_M_ABus : out std_logic_vector(0 to 31);
DPLB_M_UABus : out std_logic_vector(0 to 31);
DPLB_M_BE : out std_logic_vector(0 to 7);
DPLB_M_busLock : out std_logic;
DPLB_M_lockErr : out std_logic;
DPLB_M_MSize : out std_logic_vector(0 to 1);
DPLB_M_priority : out std_logic_vector(0 to 1);
DPLB_M_rdBurst : out std_logic;
DPLB_M_request : out std_logic;
DPLB_M_RNW : out std_logic;
DPLB_M_size : out std_logic_vector(0 to 3);
DPLB_M_TAttribute : out std_logic_vector(0 to 15);
DPLB_M_type : out std_logic_vector(0 to 2);
DPLB_M_wrBurst : out std_logic;
DPLB_M_wrDBus : out std_logic_vector(0 to 63);
DPLB_MBusy : in std_logic;
DPLB_MRdErr : in std_logic;
DPLB_MWrErr : in std_logic;
DPLB_MIRQ : in std_logic;
DPLB_MWrBTerm : in std_logic;
DPLB_MWrDAck : in std_logic;
DPLB_MAddrAck : in std_logic;
DPLB_MRdBTerm : in std_logic;
DPLB_MRdDAck : in std_logic;
DPLB_MRdDBus : in std_logic_vector(0 to 63);
DPLB_MRdWdAddr : in std_logic_vector(0 to 3);
DPLB_MRearbitrate : in std_logic;
DPLB_MSSize : in std_logic_vector(0 to 1);
DPLB_MTimeout : in std_logic;
M_AXI_IP_AWID : out std_logic_vector(0 downto 0);
M_AXI_IP_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_IP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_AWLOCK : out std_logic;
M_AXI_IP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_AWVALID : out std_logic;
M_AXI_IP_AWREADY : in std_logic;
M_AXI_IP_WDATA : out std_logic_vector(31 downto 0);
M_AXI_IP_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_IP_WLAST : out std_logic;
M_AXI_IP_WVALID : out std_logic;
M_AXI_IP_WREADY : in std_logic;
M_AXI_IP_BID : in std_logic_vector(0 downto 0);
M_AXI_IP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_BVALID : in std_logic;
M_AXI_IP_BREADY : out std_logic;
M_AXI_IP_ARID : out std_logic_vector(0 downto 0);
M_AXI_IP_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_IP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_ARLOCK : out std_logic;
M_AXI_IP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_ARVALID : out std_logic;
M_AXI_IP_ARREADY : in std_logic;
M_AXI_IP_RID : in std_logic_vector(0 downto 0);
M_AXI_IP_RDATA : in std_logic_vector(31 downto 0);
M_AXI_IP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_RLAST : in std_logic;
M_AXI_IP_RVALID : in std_logic;
M_AXI_IP_RREADY : out std_logic;
M_AXI_DP_AWID : out std_logic_vector(0 downto 0);
M_AXI_DP_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_DP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_AWLOCK : out std_logic;
M_AXI_DP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_AWVALID : out std_logic;
M_AXI_DP_AWREADY : in std_logic;
M_AXI_DP_WDATA : out std_logic_vector(31 downto 0);
M_AXI_DP_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_DP_WLAST : out std_logic;
M_AXI_DP_WVALID : out std_logic;
M_AXI_DP_WREADY : in std_logic;
M_AXI_DP_BID : in std_logic_vector(0 downto 0);
M_AXI_DP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_BVALID : in std_logic;
M_AXI_DP_BREADY : out std_logic;
M_AXI_DP_ARID : out std_logic_vector(0 downto 0);
M_AXI_DP_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_DP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_ARLOCK : out std_logic;
M_AXI_DP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_ARVALID : out std_logic;
M_AXI_DP_ARREADY : in std_logic;
M_AXI_DP_RID : in std_logic_vector(0 downto 0);
M_AXI_DP_RDATA : in std_logic_vector(31 downto 0);
M_AXI_DP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_RLAST : in std_logic;
M_AXI_DP_RVALID : in std_logic;
M_AXI_DP_RREADY : out std_logic;
M_AXI_IC_AWID : out std_logic_vector(0 downto 0);
M_AXI_IC_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_IC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_AWLOCK : out std_logic;
M_AXI_IC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_AWVALID : out std_logic;
M_AXI_IC_AWREADY : in std_logic;
M_AXI_IC_AWUSER : out std_logic_vector(4 downto 0);
M_AXI_IC_AWDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_IC_AWSNOOP : out std_logic_vector(2 downto 0);
M_AXI_IC_AWBAR : out std_logic_vector(1 downto 0);
M_AXI_IC_WDATA : out std_logic_vector(31 downto 0);
M_AXI_IC_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_IC_WLAST : out std_logic;
M_AXI_IC_WVALID : out std_logic;
M_AXI_IC_WREADY : in std_logic;
M_AXI_IC_WUSER : out std_logic_vector(0 downto 0);
M_AXI_IC_BID : in std_logic_vector(0 downto 0);
M_AXI_IC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IC_BVALID : in std_logic;
M_AXI_IC_BREADY : out std_logic;
M_AXI_IC_BUSER : in std_logic_vector(0 downto 0);
M_AXI_IC_WACK : out std_logic;
M_AXI_IC_ARID : out std_logic_vector(0 downto 0);
M_AXI_IC_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_IC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_ARLOCK : out std_logic;
M_AXI_IC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_ARVALID : out std_logic;
M_AXI_IC_ARREADY : in std_logic;
M_AXI_IC_ARUSER : out std_logic_vector(4 downto 0);
M_AXI_IC_ARDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_IC_ARSNOOP : out std_logic_vector(3 downto 0);
M_AXI_IC_ARBAR : out std_logic_vector(1 downto 0);
M_AXI_IC_RID : in std_logic_vector(0 downto 0);
M_AXI_IC_RDATA : in std_logic_vector(31 downto 0);
M_AXI_IC_RRESP : in std_logic_vector(1 downto 0);
M_AXI_IC_RLAST : in std_logic;
M_AXI_IC_RVALID : in std_logic;
M_AXI_IC_RREADY : out std_logic;
M_AXI_IC_RUSER : in std_logic_vector(0 downto 0);
M_AXI_IC_RACK : out std_logic;
M_AXI_IC_ACVALID : in std_logic;
M_AXI_IC_ACADDR : in std_logic_vector(31 downto 0);
M_AXI_IC_ACSNOOP : in std_logic_vector(3 downto 0);
M_AXI_IC_ACPROT : in std_logic_vector(2 downto 0);
M_AXI_IC_ACREADY : out std_logic;
M_AXI_IC_CRREADY : in std_logic;
M_AXI_IC_CRVALID : out std_logic;
M_AXI_IC_CRRESP : out std_logic_vector(4 downto 0);
M_AXI_IC_CDVALID : out std_logic;
M_AXI_IC_CDREADY : in std_logic;
M_AXI_IC_CDDATA : out std_logic_vector(31 downto 0);
M_AXI_IC_CDLAST : out std_logic;
M_AXI_DC_AWID : out std_logic_vector(0 downto 0);
M_AXI_DC_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_DC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_AWLOCK : out std_logic;
M_AXI_DC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_AWVALID : out std_logic;
M_AXI_DC_AWREADY : in std_logic;
M_AXI_DC_AWUSER : out std_logic_vector(4 downto 0);
M_AXI_DC_AWDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_DC_AWSNOOP : out std_logic_vector(2 downto 0);
M_AXI_DC_AWBAR : out std_logic_vector(1 downto 0);
M_AXI_DC_WDATA : out std_logic_vector(31 downto 0);
M_AXI_DC_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_DC_WLAST : out std_logic;
M_AXI_DC_WVALID : out std_logic;
M_AXI_DC_WREADY : in std_logic;
M_AXI_DC_WUSER : out std_logic_vector(0 downto 0);
M_AXI_DC_BID : in std_logic_vector(0 downto 0);
M_AXI_DC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DC_BVALID : in std_logic;
M_AXI_DC_BREADY : out std_logic;
M_AXI_DC_BUSER : in std_logic_vector(0 downto 0);
M_AXI_DC_WACK : out std_logic;
M_AXI_DC_ARID : out std_logic_vector(0 downto 0);
M_AXI_DC_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_DC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_ARLOCK : out std_logic;
M_AXI_DC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_ARVALID : out std_logic;
M_AXI_DC_ARREADY : in std_logic;
M_AXI_DC_ARUSER : out std_logic_vector(4 downto 0);
M_AXI_DC_ARDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_DC_ARSNOOP : out std_logic_vector(3 downto 0);
M_AXI_DC_ARBAR : out std_logic_vector(1 downto 0);
M_AXI_DC_RID : in std_logic_vector(0 downto 0);
M_AXI_DC_RDATA : in std_logic_vector(31 downto 0);
M_AXI_DC_RRESP : in std_logic_vector(1 downto 0);
M_AXI_DC_RLAST : in std_logic;
M_AXI_DC_RVALID : in std_logic;
M_AXI_DC_RREADY : out std_logic;
M_AXI_DC_RUSER : in std_logic_vector(0 downto 0);
M_AXI_DC_RACK : out std_logic;
M_AXI_DC_ACVALID : in std_logic;
M_AXI_DC_ACADDR : in std_logic_vector(31 downto 0);
M_AXI_DC_ACSNOOP : in std_logic_vector(3 downto 0);
M_AXI_DC_ACPROT : in std_logic_vector(2 downto 0);
M_AXI_DC_ACREADY : out std_logic;
M_AXI_DC_CRREADY : in std_logic;
M_AXI_DC_CRVALID : out std_logic;
M_AXI_DC_CRRESP : out std_logic_vector(4 downto 0);
M_AXI_DC_CDVALID : out std_logic;
M_AXI_DC_CDREADY : in std_logic;
M_AXI_DC_CDDATA : out std_logic_vector(31 downto 0);
M_AXI_DC_CDLAST : out std_logic;
DBG_CLK : in std_logic;
DBG_TDI : in std_logic;
DBG_TDO : out std_logic;
DBG_REG_EN : in std_logic_vector(0 to 7);
DBG_SHIFT : in std_logic;
DBG_CAPTURE : in std_logic;
DBG_UPDATE : in std_logic;
DEBUG_RST : in std_logic;
Trace_Instruction : out std_logic_vector(0 to 31);
Trace_Valid_Instr : out std_logic;
Trace_PC : out std_logic_vector(0 to 31);
Trace_Reg_Write : out std_logic;
Trace_Reg_Addr : out std_logic_vector(0 to 4);
Trace_MSR_Reg : out std_logic_vector(0 to 14);
Trace_PID_Reg : out std_logic_vector(0 to 7);
Trace_New_Reg_Value : out std_logic_vector(0 to 31);
Trace_Exception_Taken : out std_logic;
Trace_Exception_Kind : out std_logic_vector(0 to 4);
Trace_Jump_Taken : out std_logic;
Trace_Delay_Slot : out std_logic;
Trace_Data_Address : out std_logic_vector(0 to 31);
Trace_Data_Access : out std_logic;
Trace_Data_Read : out std_logic;
Trace_Data_Write : out std_logic;
Trace_Data_Write_Value : out std_logic_vector(0 to 31);
Trace_Data_Byte_Enable : out std_logic_vector(0 to 3);
Trace_DCache_Req : out std_logic;
Trace_DCache_Hit : out std_logic;
Trace_DCache_Rdy : out std_logic;
Trace_DCache_Read : out std_logic;
Trace_ICache_Req : out std_logic;
Trace_ICache_Hit : out std_logic;
Trace_ICache_Rdy : out std_logic;
Trace_OF_PipeRun : out std_logic;
Trace_EX_PipeRun : out std_logic;
Trace_MEM_PipeRun : out std_logic;
Trace_MB_Halted : out std_logic;
Trace_Jump_Hit : out std_logic;
FSL0_S_CLK : out std_logic;
FSL0_S_READ : out std_logic;
FSL0_S_DATA : in std_logic_vector(0 to 31);
FSL0_S_CONTROL : in std_logic;
FSL0_S_EXISTS : in std_logic;
FSL0_M_CLK : out std_logic;
FSL0_M_WRITE : out std_logic;
FSL0_M_DATA : out std_logic_vector(0 to 31);
FSL0_M_CONTROL : out std_logic;
FSL0_M_FULL : in std_logic;
FSL1_S_CLK : out std_logic;
FSL1_S_READ : out std_logic;
FSL1_S_DATA : in std_logic_vector(0 to 31);
FSL1_S_CONTROL : in std_logic;
FSL1_S_EXISTS : in std_logic;
FSL1_M_CLK : out std_logic;
FSL1_M_WRITE : out std_logic;
FSL1_M_DATA : out std_logic_vector(0 to 31);
FSL1_M_CONTROL : out std_logic;
FSL1_M_FULL : in std_logic;
FSL2_S_CLK : out std_logic;
FSL2_S_READ : out std_logic;
FSL2_S_DATA : in std_logic_vector(0 to 31);
FSL2_S_CONTROL : in std_logic;
FSL2_S_EXISTS : in std_logic;
FSL2_M_CLK : out std_logic;
FSL2_M_WRITE : out std_logic;
FSL2_M_DATA : out std_logic_vector(0 to 31);
FSL2_M_CONTROL : out std_logic;
FSL2_M_FULL : in std_logic;
FSL3_S_CLK : out std_logic;
FSL3_S_READ : out std_logic;
FSL3_S_DATA : in std_logic_vector(0 to 31);
FSL3_S_CONTROL : in std_logic;
FSL3_S_EXISTS : in std_logic;
FSL3_M_CLK : out std_logic;
FSL3_M_WRITE : out std_logic;
FSL3_M_DATA : out std_logic_vector(0 to 31);
FSL3_M_CONTROL : out std_logic;
FSL3_M_FULL : in std_logic;
FSL4_S_CLK : out std_logic;
FSL4_S_READ : out std_logic;
FSL4_S_DATA : in std_logic_vector(0 to 31);
FSL4_S_CONTROL : in std_logic;
FSL4_S_EXISTS : in std_logic;
FSL4_M_CLK : out std_logic;
FSL4_M_WRITE : out std_logic;
FSL4_M_DATA : out std_logic_vector(0 to 31);
FSL4_M_CONTROL : out std_logic;
FSL4_M_FULL : in std_logic;
FSL5_S_CLK : out std_logic;
FSL5_S_READ : out std_logic;
FSL5_S_DATA : in std_logic_vector(0 to 31);
FSL5_S_CONTROL : in std_logic;
FSL5_S_EXISTS : in std_logic;
FSL5_M_CLK : out std_logic;
FSL5_M_WRITE : out std_logic;
FSL5_M_DATA : out std_logic_vector(0 to 31);
FSL5_M_CONTROL : out std_logic;
FSL5_M_FULL : in std_logic;
FSL6_S_CLK : out std_logic;
FSL6_S_READ : out std_logic;
FSL6_S_DATA : in std_logic_vector(0 to 31);
FSL6_S_CONTROL : in std_logic;
FSL6_S_EXISTS : in std_logic;
FSL6_M_CLK : out std_logic;
FSL6_M_WRITE : out std_logic;
FSL6_M_DATA : out std_logic_vector(0 to 31);
FSL6_M_CONTROL : out std_logic;
FSL6_M_FULL : in std_logic;
FSL7_S_CLK : out std_logic;
FSL7_S_READ : out std_logic;
FSL7_S_DATA : in std_logic_vector(0 to 31);
FSL7_S_CONTROL : in std_logic;
FSL7_S_EXISTS : in std_logic;
FSL7_M_CLK : out std_logic;
FSL7_M_WRITE : out std_logic;
FSL7_M_DATA : out std_logic_vector(0 to 31);
FSL7_M_CONTROL : out std_logic;
FSL7_M_FULL : in std_logic;
FSL8_S_CLK : out std_logic;
FSL8_S_READ : out std_logic;
FSL8_S_DATA : in std_logic_vector(0 to 31);
FSL8_S_CONTROL : in std_logic;
FSL8_S_EXISTS : in std_logic;
FSL8_M_CLK : out std_logic;
FSL8_M_WRITE : out std_logic;
FSL8_M_DATA : out std_logic_vector(0 to 31);
FSL8_M_CONTROL : out std_logic;
FSL8_M_FULL : in std_logic;
FSL9_S_CLK : out std_logic;
FSL9_S_READ : out std_logic;
FSL9_S_DATA : in std_logic_vector(0 to 31);
FSL9_S_CONTROL : in std_logic;
FSL9_S_EXISTS : in std_logic;
FSL9_M_CLK : out std_logic;
FSL9_M_WRITE : out std_logic;
FSL9_M_DATA : out std_logic_vector(0 to 31);
FSL9_M_CONTROL : out std_logic;
FSL9_M_FULL : in std_logic;
FSL10_S_CLK : out std_logic;
FSL10_S_READ : out std_logic;
FSL10_S_DATA : in std_logic_vector(0 to 31);
FSL10_S_CONTROL : in std_logic;
FSL10_S_EXISTS : in std_logic;
FSL10_M_CLK : out std_logic;
FSL10_M_WRITE : out std_logic;
FSL10_M_DATA : out std_logic_vector(0 to 31);
FSL10_M_CONTROL : out std_logic;
FSL10_M_FULL : in std_logic;
FSL11_S_CLK : out std_logic;
FSL11_S_READ : out std_logic;
FSL11_S_DATA : in std_logic_vector(0 to 31);
FSL11_S_CONTROL : in std_logic;
FSL11_S_EXISTS : in std_logic;
FSL11_M_CLK : out std_logic;
FSL11_M_WRITE : out std_logic;
FSL11_M_DATA : out std_logic_vector(0 to 31);
FSL11_M_CONTROL : out std_logic;
FSL11_M_FULL : in std_logic;
FSL12_S_CLK : out std_logic;
FSL12_S_READ : out std_logic;
FSL12_S_DATA : in std_logic_vector(0 to 31);
FSL12_S_CONTROL : in std_logic;
FSL12_S_EXISTS : in std_logic;
FSL12_M_CLK : out std_logic;
FSL12_M_WRITE : out std_logic;
FSL12_M_DATA : out std_logic_vector(0 to 31);
FSL12_M_CONTROL : out std_logic;
FSL12_M_FULL : in std_logic;
FSL13_S_CLK : out std_logic;
FSL13_S_READ : out std_logic;
FSL13_S_DATA : in std_logic_vector(0 to 31);
FSL13_S_CONTROL : in std_logic;
FSL13_S_EXISTS : in std_logic;
FSL13_M_CLK : out std_logic;
FSL13_M_WRITE : out std_logic;
FSL13_M_DATA : out std_logic_vector(0 to 31);
FSL13_M_CONTROL : out std_logic;
FSL13_M_FULL : in std_logic;
FSL14_S_CLK : out std_logic;
FSL14_S_READ : out std_logic;
FSL14_S_DATA : in std_logic_vector(0 to 31);
FSL14_S_CONTROL : in std_logic;
FSL14_S_EXISTS : in std_logic;
FSL14_M_CLK : out std_logic;
FSL14_M_WRITE : out std_logic;
FSL14_M_DATA : out std_logic_vector(0 to 31);
FSL14_M_CONTROL : out std_logic;
FSL14_M_FULL : in std_logic;
FSL15_S_CLK : out std_logic;
FSL15_S_READ : out std_logic;
FSL15_S_DATA : in std_logic_vector(0 to 31);
FSL15_S_CONTROL : in std_logic;
FSL15_S_EXISTS : in std_logic;
FSL15_M_CLK : out std_logic;
FSL15_M_WRITE : out std_logic;
FSL15_M_DATA : out std_logic_vector(0 to 31);
FSL15_M_CONTROL : out std_logic;
FSL15_M_FULL : in std_logic;
M0_AXIS_TLAST : out std_logic;
M0_AXIS_TDATA : out std_logic_vector(31 downto 0);
M0_AXIS_TVALID : out std_logic;
M0_AXIS_TREADY : in std_logic;
S0_AXIS_TLAST : in std_logic;
S0_AXIS_TDATA : in std_logic_vector(31 downto 0);
S0_AXIS_TVALID : in std_logic;
S0_AXIS_TREADY : out std_logic;
M1_AXIS_TLAST : out std_logic;
M1_AXIS_TDATA : out std_logic_vector(31 downto 0);
M1_AXIS_TVALID : out std_logic;
M1_AXIS_TREADY : in std_logic;
S1_AXIS_TLAST : in std_logic;
S1_AXIS_TDATA : in std_logic_vector(31 downto 0);
S1_AXIS_TVALID : in std_logic;
S1_AXIS_TREADY : out std_logic;
M2_AXIS_TLAST : out std_logic;
M2_AXIS_TDATA : out std_logic_vector(31 downto 0);
M2_AXIS_TVALID : out std_logic;
M2_AXIS_TREADY : in std_logic;
S2_AXIS_TLAST : in std_logic;
S2_AXIS_TDATA : in std_logic_vector(31 downto 0);
S2_AXIS_TVALID : in std_logic;
S2_AXIS_TREADY : out std_logic;
M3_AXIS_TLAST : out std_logic;
M3_AXIS_TDATA : out std_logic_vector(31 downto 0);
M3_AXIS_TVALID : out std_logic;
M3_AXIS_TREADY : in std_logic;
S3_AXIS_TLAST : in std_logic;
S3_AXIS_TDATA : in std_logic_vector(31 downto 0);
S3_AXIS_TVALID : in std_logic;
S3_AXIS_TREADY : out std_logic;
M4_AXIS_TLAST : out std_logic;
M4_AXIS_TDATA : out std_logic_vector(31 downto 0);
M4_AXIS_TVALID : out std_logic;
M4_AXIS_TREADY : in std_logic;
S4_AXIS_TLAST : in std_logic;
S4_AXIS_TDATA : in std_logic_vector(31 downto 0);
S4_AXIS_TVALID : in std_logic;
S4_AXIS_TREADY : out std_logic;
M5_AXIS_TLAST : out std_logic;
M5_AXIS_TDATA : out std_logic_vector(31 downto 0);
M5_AXIS_TVALID : out std_logic;
M5_AXIS_TREADY : in std_logic;
S5_AXIS_TLAST : in std_logic;
S5_AXIS_TDATA : in std_logic_vector(31 downto 0);
S5_AXIS_TVALID : in std_logic;
S5_AXIS_TREADY : out std_logic;
M6_AXIS_TLAST : out std_logic;
M6_AXIS_TDATA : out std_logic_vector(31 downto 0);
M6_AXIS_TVALID : out std_logic;
M6_AXIS_TREADY : in std_logic;
S6_AXIS_TLAST : in std_logic;
S6_AXIS_TDATA : in std_logic_vector(31 downto 0);
S6_AXIS_TVALID : in std_logic;
S6_AXIS_TREADY : out std_logic;
M7_AXIS_TLAST : out std_logic;
M7_AXIS_TDATA : out std_logic_vector(31 downto 0);
M7_AXIS_TVALID : out std_logic;
M7_AXIS_TREADY : in std_logic;
S7_AXIS_TLAST : in std_logic;
S7_AXIS_TDATA : in std_logic_vector(31 downto 0);
S7_AXIS_TVALID : in std_logic;
S7_AXIS_TREADY : out std_logic;
M8_AXIS_TLAST : out std_logic;
M8_AXIS_TDATA : out std_logic_vector(31 downto 0);
M8_AXIS_TVALID : out std_logic;
M8_AXIS_TREADY : in std_logic;
S8_AXIS_TLAST : in std_logic;
S8_AXIS_TDATA : in std_logic_vector(31 downto 0);
S8_AXIS_TVALID : in std_logic;
S8_AXIS_TREADY : out std_logic;
M9_AXIS_TLAST : out std_logic;
M9_AXIS_TDATA : out std_logic_vector(31 downto 0);
M9_AXIS_TVALID : out std_logic;
M9_AXIS_TREADY : in std_logic;
S9_AXIS_TLAST : in std_logic;
S9_AXIS_TDATA : in std_logic_vector(31 downto 0);
S9_AXIS_TVALID : in std_logic;
S9_AXIS_TREADY : out std_logic;
M10_AXIS_TLAST : out std_logic;
M10_AXIS_TDATA : out std_logic_vector(31 downto 0);
M10_AXIS_TVALID : out std_logic;
M10_AXIS_TREADY : in std_logic;
S10_AXIS_TLAST : in std_logic;
S10_AXIS_TDATA : in std_logic_vector(31 downto 0);
S10_AXIS_TVALID : in std_logic;
S10_AXIS_TREADY : out std_logic;
M11_AXIS_TLAST : out std_logic;
M11_AXIS_TDATA : out std_logic_vector(31 downto 0);
M11_AXIS_TVALID : out std_logic;
M11_AXIS_TREADY : in std_logic;
S11_AXIS_TLAST : in std_logic;
S11_AXIS_TDATA : in std_logic_vector(31 downto 0);
S11_AXIS_TVALID : in std_logic;
S11_AXIS_TREADY : out std_logic;
M12_AXIS_TLAST : out std_logic;
M12_AXIS_TDATA : out std_logic_vector(31 downto 0);
M12_AXIS_TVALID : out std_logic;
M12_AXIS_TREADY : in std_logic;
S12_AXIS_TLAST : in std_logic;
S12_AXIS_TDATA : in std_logic_vector(31 downto 0);
S12_AXIS_TVALID : in std_logic;
S12_AXIS_TREADY : out std_logic;
M13_AXIS_TLAST : out std_logic;
M13_AXIS_TDATA : out std_logic_vector(31 downto 0);
M13_AXIS_TVALID : out std_logic;
M13_AXIS_TREADY : in std_logic;
S13_AXIS_TLAST : in std_logic;
S13_AXIS_TDATA : in std_logic_vector(31 downto 0);
S13_AXIS_TVALID : in std_logic;
S13_AXIS_TREADY : out std_logic;
M14_AXIS_TLAST : out std_logic;
M14_AXIS_TDATA : out std_logic_vector(31 downto 0);
M14_AXIS_TVALID : out std_logic;
M14_AXIS_TREADY : in std_logic;
S14_AXIS_TLAST : in std_logic;
S14_AXIS_TDATA : in std_logic_vector(31 downto 0);
S14_AXIS_TVALID : in std_logic;
S14_AXIS_TREADY : out std_logic;
M15_AXIS_TLAST : out std_logic;
M15_AXIS_TDATA : out std_logic_vector(31 downto 0);
M15_AXIS_TVALID : out std_logic;
M15_AXIS_TREADY : in std_logic;
S15_AXIS_TLAST : in std_logic;
S15_AXIS_TDATA : in std_logic_vector(31 downto 0);
S15_AXIS_TVALID : in std_logic;
S15_AXIS_TREADY : out std_logic;
ICACHE_FSL_IN_CLK : out std_logic;
ICACHE_FSL_IN_READ : out std_logic;
ICACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
ICACHE_FSL_IN_CONTROL : in std_logic;
ICACHE_FSL_IN_EXISTS : in std_logic;
ICACHE_FSL_OUT_CLK : out std_logic;
ICACHE_FSL_OUT_WRITE : out std_logic;
ICACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
ICACHE_FSL_OUT_CONTROL : out std_logic;
ICACHE_FSL_OUT_FULL : in std_logic;
DCACHE_FSL_IN_CLK : out std_logic;
DCACHE_FSL_IN_READ : out std_logic;
DCACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
DCACHE_FSL_IN_CONTROL : in std_logic;
DCACHE_FSL_IN_EXISTS : in std_logic;
DCACHE_FSL_OUT_CLK : out std_logic;
DCACHE_FSL_OUT_WRITE : out std_logic;
DCACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
DCACHE_FSL_OUT_CONTROL : out std_logic;
DCACHE_FSL_OUT_FULL : in std_logic
);
end system_microblaze_0_wrapper;
architecture STRUCTURE of system_microblaze_0_wrapper is
component microblaze is
generic (
C_SCO : integer;
C_FREQ : integer;
C_DATA_SIZE : integer;
C_DYNAMIC_BUS_SIZING : integer;
C_FAMILY : string;
C_INSTANCE : string;
C_AVOID_PRIMITIVES : integer;
C_FAULT_TOLERANT : integer;
C_ECC_USE_CE_EXCEPTION : integer;
C_LOCKSTEP_SLAVE : integer;
C_ENDIANNESS : integer;
C_AREA_OPTIMIZED : integer;
C_OPTIMIZATION : integer;
C_INTERCONNECT : integer;
C_STREAM_INTERCONNECT : integer;
C_BASE_VECTORS : std_logic_vector;
C_DPLB_DWIDTH : integer;
C_DPLB_NATIVE_DWIDTH : integer;
C_DPLB_BURST_EN : integer;
C_DPLB_P2P : integer;
C_IPLB_DWIDTH : integer;
C_IPLB_NATIVE_DWIDTH : integer;
C_IPLB_BURST_EN : integer;
C_IPLB_P2P : integer;
C_M_AXI_DP_THREAD_ID_WIDTH : integer;
C_M_AXI_DP_DATA_WIDTH : integer;
C_M_AXI_DP_ADDR_WIDTH : integer;
C_M_AXI_DP_EXCLUSIVE_ACCESS : integer;
C_M_AXI_IP_THREAD_ID_WIDTH : integer;
C_M_AXI_IP_DATA_WIDTH : integer;
C_M_AXI_IP_ADDR_WIDTH : integer;
C_D_AXI : integer;
C_D_PLB : integer;
C_D_LMB : integer;
C_I_AXI : integer;
C_I_PLB : integer;
C_I_LMB : integer;
C_USE_MSR_INSTR : integer;
C_USE_PCMP_INSTR : integer;
C_USE_BARREL : integer;
C_USE_DIV : integer;
C_USE_HW_MUL : integer;
C_USE_FPU : integer;
C_USE_REORDER_INSTR : integer;
C_UNALIGNED_EXCEPTIONS : integer;
C_ILL_OPCODE_EXCEPTION : integer;
C_M_AXI_I_BUS_EXCEPTION : integer;
C_M_AXI_D_BUS_EXCEPTION : integer;
C_IPLB_BUS_EXCEPTION : integer;
C_DPLB_BUS_EXCEPTION : integer;
C_DIV_ZERO_EXCEPTION : integer;
C_FPU_EXCEPTION : integer;
C_FSL_EXCEPTION : integer;
C_USE_STACK_PROTECTION : integer;
C_PVR : integer;
C_PVR_USER1 : std_logic_vector(0 to 7);
C_PVR_USER2 : std_logic_vector(0 to 31);
C_DEBUG_ENABLED : integer;
C_NUMBER_OF_PC_BRK : integer;
C_NUMBER_OF_RD_ADDR_BRK : integer;
C_NUMBER_OF_WR_ADDR_BRK : integer;
C_INTERRUPT_IS_EDGE : integer;
C_EDGE_IS_POSITIVE : integer;
C_RESET_MSR : std_logic_vector;
C_OPCODE_0x0_ILLEGAL : integer;
C_FSL_LINKS : integer;
C_FSL_DATA_SIZE : integer;
C_USE_EXTENDED_FSL_INSTR : integer;
C_M0_AXIS_DATA_WIDTH : integer;
C_S0_AXIS_DATA_WIDTH : integer;
C_M1_AXIS_DATA_WIDTH : integer;
C_S1_AXIS_DATA_WIDTH : integer;
C_M2_AXIS_DATA_WIDTH : integer;
C_S2_AXIS_DATA_WIDTH : integer;
C_M3_AXIS_DATA_WIDTH : integer;
C_S3_AXIS_DATA_WIDTH : integer;
C_M4_AXIS_DATA_WIDTH : integer;
C_S4_AXIS_DATA_WIDTH : integer;
C_M5_AXIS_DATA_WIDTH : integer;
C_S5_AXIS_DATA_WIDTH : integer;
C_M6_AXIS_DATA_WIDTH : integer;
C_S6_AXIS_DATA_WIDTH : integer;
C_M7_AXIS_DATA_WIDTH : integer;
C_S7_AXIS_DATA_WIDTH : integer;
C_M8_AXIS_DATA_WIDTH : integer;
C_S8_AXIS_DATA_WIDTH : integer;
C_M9_AXIS_DATA_WIDTH : integer;
C_S9_AXIS_DATA_WIDTH : integer;
C_M10_AXIS_DATA_WIDTH : integer;
C_S10_AXIS_DATA_WIDTH : integer;
C_M11_AXIS_DATA_WIDTH : integer;
C_S11_AXIS_DATA_WIDTH : integer;
C_M12_AXIS_DATA_WIDTH : integer;
C_S12_AXIS_DATA_WIDTH : integer;
C_M13_AXIS_DATA_WIDTH : integer;
C_S13_AXIS_DATA_WIDTH : integer;
C_M14_AXIS_DATA_WIDTH : integer;
C_S14_AXIS_DATA_WIDTH : integer;
C_M15_AXIS_DATA_WIDTH : integer;
C_S15_AXIS_DATA_WIDTH : integer;
C_ICACHE_BASEADDR : std_logic_vector;
C_ICACHE_HIGHADDR : std_logic_vector;
C_USE_ICACHE : integer;
C_ALLOW_ICACHE_WR : integer;
C_ADDR_TAG_BITS : integer;
C_CACHE_BYTE_SIZE : integer;
C_ICACHE_USE_FSL : integer;
C_ICACHE_LINE_LEN : integer;
C_ICACHE_ALWAYS_USED : integer;
C_ICACHE_INTERFACE : integer;
C_ICACHE_VICTIMS : integer;
C_ICACHE_STREAMS : integer;
C_ICACHE_FORCE_TAG_LUTRAM : integer;
C_ICACHE_DATA_WIDTH : integer;
C_M_AXI_IC_THREAD_ID_WIDTH : integer;
C_M_AXI_IC_DATA_WIDTH : integer;
C_M_AXI_IC_ADDR_WIDTH : integer;
C_M_AXI_IC_USER_VALUE : integer;
C_M_AXI_IC_AWUSER_WIDTH : integer;
C_M_AXI_IC_ARUSER_WIDTH : integer;
C_M_AXI_IC_WUSER_WIDTH : integer;
C_M_AXI_IC_RUSER_WIDTH : integer;
C_M_AXI_IC_BUSER_WIDTH : integer;
C_DCACHE_BASEADDR : std_logic_vector;
C_DCACHE_HIGHADDR : std_logic_vector;
C_USE_DCACHE : integer;
C_ALLOW_DCACHE_WR : integer;
C_DCACHE_ADDR_TAG : integer;
C_DCACHE_BYTE_SIZE : integer;
C_DCACHE_USE_FSL : integer;
C_DCACHE_LINE_LEN : integer;
C_DCACHE_ALWAYS_USED : integer;
C_DCACHE_INTERFACE : integer;
C_DCACHE_USE_WRITEBACK : integer;
C_DCACHE_VICTIMS : integer;
C_DCACHE_FORCE_TAG_LUTRAM : integer;
C_DCACHE_DATA_WIDTH : integer;
C_M_AXI_DC_THREAD_ID_WIDTH : integer;
C_M_AXI_DC_DATA_WIDTH : integer;
C_M_AXI_DC_ADDR_WIDTH : integer;
C_M_AXI_DC_EXCLUSIVE_ACCESS : integer;
C_M_AXI_DC_USER_VALUE : integer;
C_M_AXI_DC_AWUSER_WIDTH : integer;
C_M_AXI_DC_ARUSER_WIDTH : integer;
C_M_AXI_DC_WUSER_WIDTH : integer;
C_M_AXI_DC_RUSER_WIDTH : integer;
C_M_AXI_DC_BUSER_WIDTH : integer;
C_USE_MMU : integer;
C_MMU_DTLB_SIZE : integer;
C_MMU_ITLB_SIZE : integer;
C_MMU_TLB_ACCESS : integer;
C_MMU_ZONES : integer;
C_MMU_PRIVILEGED_INSTR : integer;
C_USE_INTERRUPT : integer;
C_USE_EXT_BRK : integer;
C_USE_EXT_NM_BRK : integer;
C_USE_BRANCH_TARGET_CACHE : integer;
C_BRANCH_TARGET_CACHE_SIZE : integer;
C_PC_WIDTH : integer
);
port (
CLK : in std_logic;
RESET : in std_logic;
MB_RESET : in std_logic;
INTERRUPT : in std_logic;
INTERRUPT_ADDRESS : in std_logic_vector(0 to 31);
INTERRUPT_ACK : out std_logic_vector(0 to 1);
EXT_BRK : in std_logic;
EXT_NM_BRK : in std_logic;
DBG_STOP : in std_logic;
MB_Halted : out std_logic;
MB_Error : out std_logic;
WAKEUP : in std_logic_vector(0 to 1);
SLEEP : out std_logic;
DBG_WAKEUP : out std_logic;
LOCKSTEP_MASTER_OUT : out std_logic_vector(0 to 4095);
LOCKSTEP_SLAVE_IN : in std_logic_vector(0 to 4095);
LOCKSTEP_OUT : out std_logic_vector(0 to 4095);
INSTR : in std_logic_vector(0 to 31);
IREADY : in std_logic;
IWAIT : in std_logic;
ICE : in std_logic;
IUE : in std_logic;
INSTR_ADDR : out std_logic_vector(0 to 31);
IFETCH : out std_logic;
I_AS : out std_logic;
IPLB_M_ABort : out std_logic;
IPLB_M_ABus : out std_logic_vector(0 to 31);
IPLB_M_UABus : out std_logic_vector(0 to 31);
IPLB_M_BE : out std_logic_vector(0 to (C_IPLB_DWIDTH-1)/8);
IPLB_M_busLock : out std_logic;
IPLB_M_lockErr : out std_logic;
IPLB_M_MSize : out std_logic_vector(0 to 1);
IPLB_M_priority : out std_logic_vector(0 to 1);
IPLB_M_rdBurst : out std_logic;
IPLB_M_request : out std_logic;
IPLB_M_RNW : out std_logic;
IPLB_M_size : out std_logic_vector(0 to 3);
IPLB_M_TAttribute : out std_logic_vector(0 to 15);
IPLB_M_type : out std_logic_vector(0 to 2);
IPLB_M_wrBurst : out std_logic;
IPLB_M_wrDBus : out std_logic_vector(0 to C_IPLB_DWIDTH-1);
IPLB_MBusy : in std_logic;
IPLB_MRdErr : in std_logic;
IPLB_MWrErr : in std_logic;
IPLB_MIRQ : in std_logic;
IPLB_MWrBTerm : in std_logic;
IPLB_MWrDAck : in std_logic;
IPLB_MAddrAck : in std_logic;
IPLB_MRdBTerm : in std_logic;
IPLB_MRdDAck : in std_logic;
IPLB_MRdDBus : in std_logic_vector(0 to C_IPLB_DWIDTH-1);
IPLB_MRdWdAddr : in std_logic_vector(0 to 3);
IPLB_MRearbitrate : in std_logic;
IPLB_MSSize : in std_logic_vector(0 to 1);
IPLB_MTimeout : in std_logic;
DATA_READ : in std_logic_vector(0 to 31);
DREADY : in std_logic;
DWAIT : in std_logic;
DCE : in std_logic;
DUE : in std_logic;
DATA_WRITE : out std_logic_vector(0 to 31);
DATA_ADDR : out std_logic_vector(0 to 31);
D_AS : out std_logic;
READ_STROBE : out std_logic;
WRITE_STROBE : out std_logic;
BYTE_ENABLE : out std_logic_vector(0 to 3);
DPLB_M_ABort : out std_logic;
DPLB_M_ABus : out std_logic_vector(0 to 31);
DPLB_M_UABus : out std_logic_vector(0 to 31);
DPLB_M_BE : out std_logic_vector(0 to (C_DPLB_DWIDTH-1)/8);
DPLB_M_busLock : out std_logic;
DPLB_M_lockErr : out std_logic;
DPLB_M_MSize : out std_logic_vector(0 to 1);
DPLB_M_priority : out std_logic_vector(0 to 1);
DPLB_M_rdBurst : out std_logic;
DPLB_M_request : out std_logic;
DPLB_M_RNW : out std_logic;
DPLB_M_size : out std_logic_vector(0 to 3);
DPLB_M_TAttribute : out std_logic_vector(0 to 15);
DPLB_M_type : out std_logic_vector(0 to 2);
DPLB_M_wrBurst : out std_logic;
DPLB_M_wrDBus : out std_logic_vector(0 to C_DPLB_DWIDTH-1);
DPLB_MBusy : in std_logic;
DPLB_MRdErr : in std_logic;
DPLB_MWrErr : in std_logic;
DPLB_MIRQ : in std_logic;
DPLB_MWrBTerm : in std_logic;
DPLB_MWrDAck : in std_logic;
DPLB_MAddrAck : in std_logic;
DPLB_MRdBTerm : in std_logic;
DPLB_MRdDAck : in std_logic;
DPLB_MRdDBus : in std_logic_vector(0 to C_DPLB_DWIDTH-1);
DPLB_MRdWdAddr : in std_logic_vector(0 to 3);
DPLB_MRearbitrate : in std_logic;
DPLB_MSSize : in std_logic_vector(0 to 1);
DPLB_MTimeout : in std_logic;
M_AXI_IP_AWID : out std_logic_vector((C_M_AXI_IP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IP_AWADDR : out std_logic_vector((C_M_AXI_IP_ADDR_WIDTH-1) downto 0);
M_AXI_IP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_AWLOCK : out std_logic;
M_AXI_IP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_AWVALID : out std_logic;
M_AXI_IP_AWREADY : in std_logic;
M_AXI_IP_WDATA : out std_logic_vector((C_M_AXI_IP_DATA_WIDTH-1) downto 0);
M_AXI_IP_WSTRB : out std_logic_vector(((C_M_AXI_IP_DATA_WIDTH/8)-1) downto 0);
M_AXI_IP_WLAST : out std_logic;
M_AXI_IP_WVALID : out std_logic;
M_AXI_IP_WREADY : in std_logic;
M_AXI_IP_BID : in std_logic_vector((C_M_AXI_IP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_BVALID : in std_logic;
M_AXI_IP_BREADY : out std_logic;
M_AXI_IP_ARID : out std_logic_vector((C_M_AXI_IP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IP_ARADDR : out std_logic_vector((C_M_AXI_IP_ADDR_WIDTH-1) downto 0);
M_AXI_IP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_ARLOCK : out std_logic;
M_AXI_IP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_ARVALID : out std_logic;
M_AXI_IP_ARREADY : in std_logic;
M_AXI_IP_RID : in std_logic_vector((C_M_AXI_IP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IP_RDATA : in std_logic_vector((C_M_AXI_IP_DATA_WIDTH-1) downto 0);
M_AXI_IP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_RLAST : in std_logic;
M_AXI_IP_RVALID : in std_logic;
M_AXI_IP_RREADY : out std_logic;
M_AXI_DP_AWID : out std_logic_vector((C_M_AXI_DP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DP_AWADDR : out std_logic_vector((C_M_AXI_DP_ADDR_WIDTH-1) downto 0);
M_AXI_DP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_AWLOCK : out std_logic;
M_AXI_DP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_AWVALID : out std_logic;
M_AXI_DP_AWREADY : in std_logic;
M_AXI_DP_WDATA : out std_logic_vector((C_M_AXI_DP_DATA_WIDTH-1) downto 0);
M_AXI_DP_WSTRB : out std_logic_vector(((C_M_AXI_DP_DATA_WIDTH/8)-1) downto 0);
M_AXI_DP_WLAST : out std_logic;
M_AXI_DP_WVALID : out std_logic;
M_AXI_DP_WREADY : in std_logic;
M_AXI_DP_BID : in std_logic_vector((C_M_AXI_DP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_BVALID : in std_logic;
M_AXI_DP_BREADY : out std_logic;
M_AXI_DP_ARID : out std_logic_vector((C_M_AXI_DP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DP_ARADDR : out std_logic_vector((C_M_AXI_DP_ADDR_WIDTH-1) downto 0);
M_AXI_DP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_ARLOCK : out std_logic;
M_AXI_DP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_ARVALID : out std_logic;
M_AXI_DP_ARREADY : in std_logic;
M_AXI_DP_RID : in std_logic_vector((C_M_AXI_DP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DP_RDATA : in std_logic_vector((C_M_AXI_DP_DATA_WIDTH-1) downto 0);
M_AXI_DP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_RLAST : in std_logic;
M_AXI_DP_RVALID : in std_logic;
M_AXI_DP_RREADY : out std_logic;
M_AXI_IC_AWID : out std_logic_vector((C_M_AXI_IC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IC_AWADDR : out std_logic_vector((C_M_AXI_IC_ADDR_WIDTH-1) downto 0);
M_AXI_IC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_AWLOCK : out std_logic;
M_AXI_IC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_AWVALID : out std_logic;
M_AXI_IC_AWREADY : in std_logic;
M_AXI_IC_AWUSER : out std_logic_vector((C_M_AXI_IC_AWUSER_WIDTH-1) downto 0);
M_AXI_IC_AWDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_IC_AWSNOOP : out std_logic_vector(2 downto 0);
M_AXI_IC_AWBAR : out std_logic_vector(1 downto 0);
M_AXI_IC_WDATA : out std_logic_vector((C_M_AXI_IC_DATA_WIDTH-1) downto 0);
M_AXI_IC_WSTRB : out std_logic_vector(((C_M_AXI_IC_DATA_WIDTH/8)-1) downto 0);
M_AXI_IC_WLAST : out std_logic;
M_AXI_IC_WVALID : out std_logic;
M_AXI_IC_WREADY : in std_logic;
M_AXI_IC_WUSER : out std_logic_vector((C_M_AXI_IC_WUSER_WIDTH-1) downto 0);
M_AXI_IC_BID : in std_logic_vector((C_M_AXI_IC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IC_BVALID : in std_logic;
M_AXI_IC_BREADY : out std_logic;
M_AXI_IC_BUSER : in std_logic_vector((C_M_AXI_IC_BUSER_WIDTH-1) downto 0);
M_AXI_IC_WACK : out std_logic;
M_AXI_IC_ARID : out std_logic_vector((C_M_AXI_IC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IC_ARADDR : out std_logic_vector((C_M_AXI_IC_ADDR_WIDTH-1) downto 0);
M_AXI_IC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_ARLOCK : out std_logic;
M_AXI_IC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_ARVALID : out std_logic;
M_AXI_IC_ARREADY : in std_logic;
M_AXI_IC_ARUSER : out std_logic_vector((C_M_AXI_IC_ARUSER_WIDTH-1) downto 0);
M_AXI_IC_ARDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_IC_ARSNOOP : out std_logic_vector(3 downto 0);
M_AXI_IC_ARBAR : out std_logic_vector(1 downto 0);
M_AXI_IC_RID : in std_logic_vector((C_M_AXI_IC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IC_RDATA : in std_logic_vector((C_M_AXI_IC_DATA_WIDTH-1) downto 0);
M_AXI_IC_RRESP : in std_logic_vector(1+2*((C_INTERCONNECT-1)/2) downto 0);
M_AXI_IC_RLAST : in std_logic;
M_AXI_IC_RVALID : in std_logic;
M_AXI_IC_RREADY : out std_logic;
M_AXI_IC_RUSER : in std_logic_vector((C_M_AXI_IC_RUSER_WIDTH-1) downto 0);
M_AXI_IC_RACK : out std_logic;
M_AXI_IC_ACVALID : in std_logic;
M_AXI_IC_ACADDR : in std_logic_vector((C_M_AXI_IC_ADDR_WIDTH-1) downto 0);
M_AXI_IC_ACSNOOP : in std_logic_vector(3 downto 0);
M_AXI_IC_ACPROT : in std_logic_vector(2 downto 0);
M_AXI_IC_ACREADY : out std_logic;
M_AXI_IC_CRREADY : in std_logic;
M_AXI_IC_CRVALID : out std_logic;
M_AXI_IC_CRRESP : out std_logic_vector(4 downto 0);
M_AXI_IC_CDVALID : out std_logic;
M_AXI_IC_CDREADY : in std_logic;
M_AXI_IC_CDDATA : out std_logic_vector((C_M_AXI_IC_DATA_WIDTH-1) downto 0);
M_AXI_IC_CDLAST : out std_logic;
M_AXI_DC_AWID : out std_logic_vector((C_M_AXI_DC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DC_AWADDR : out std_logic_vector((C_M_AXI_DC_ADDR_WIDTH-1) downto 0);
M_AXI_DC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_AWLOCK : out std_logic;
M_AXI_DC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_AWVALID : out std_logic;
M_AXI_DC_AWREADY : in std_logic;
M_AXI_DC_AWUSER : out std_logic_vector((C_M_AXI_DC_AWUSER_WIDTH-1) downto 0);
M_AXI_DC_AWDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_DC_AWSNOOP : out std_logic_vector(2 downto 0);
M_AXI_DC_AWBAR : out std_logic_vector(1 downto 0);
M_AXI_DC_WDATA : out std_logic_vector((C_M_AXI_DC_DATA_WIDTH-1) downto 0);
M_AXI_DC_WSTRB : out std_logic_vector(((C_M_AXI_DC_DATA_WIDTH/8)-1) downto 0);
M_AXI_DC_WLAST : out std_logic;
M_AXI_DC_WVALID : out std_logic;
M_AXI_DC_WREADY : in std_logic;
M_AXI_DC_WUSER : out std_logic_vector((C_M_AXI_DC_WUSER_WIDTH-1) downto 0);
M_AXI_DC_BID : in std_logic_vector((C_M_AXI_DC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DC_BVALID : in std_logic;
M_AXI_DC_BREADY : out std_logic;
M_AXI_DC_BUSER : in std_logic_vector((C_M_AXI_DC_BUSER_WIDTH-1) downto 0);
M_AXI_DC_WACK : out std_logic;
M_AXI_DC_ARID : out std_logic_vector((C_M_AXI_DC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DC_ARADDR : out std_logic_vector((C_M_AXI_DC_ADDR_WIDTH-1) downto 0);
M_AXI_DC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_ARLOCK : out std_logic;
M_AXI_DC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_ARVALID : out std_logic;
M_AXI_DC_ARREADY : in std_logic;
M_AXI_DC_ARUSER : out std_logic_vector((C_M_AXI_DC_ARUSER_WIDTH-1) downto 0);
M_AXI_DC_ARDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_DC_ARSNOOP : out std_logic_vector(3 downto 0);
M_AXI_DC_ARBAR : out std_logic_vector(1 downto 0);
M_AXI_DC_RID : in std_logic_vector((C_M_AXI_DC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DC_RDATA : in std_logic_vector((C_M_AXI_DC_DATA_WIDTH-1) downto 0);
M_AXI_DC_RRESP : in std_logic_vector(1+2*((C_INTERCONNECT-1)/2) downto 0);
M_AXI_DC_RLAST : in std_logic;
M_AXI_DC_RVALID : in std_logic;
M_AXI_DC_RREADY : out std_logic;
M_AXI_DC_RUSER : in std_logic_vector((C_M_AXI_DC_RUSER_WIDTH-1) downto 0);
M_AXI_DC_RACK : out std_logic;
M_AXI_DC_ACVALID : in std_logic;
M_AXI_DC_ACADDR : in std_logic_vector((C_M_AXI_DC_ADDR_WIDTH-1) downto 0);
M_AXI_DC_ACSNOOP : in std_logic_vector(3 downto 0);
M_AXI_DC_ACPROT : in std_logic_vector(2 downto 0);
M_AXI_DC_ACREADY : out std_logic;
M_AXI_DC_CRREADY : in std_logic;
M_AXI_DC_CRVALID : out std_logic;
M_AXI_DC_CRRESP : out std_logic_vector(4 downto 0);
M_AXI_DC_CDVALID : out std_logic;
M_AXI_DC_CDREADY : in std_logic;
M_AXI_DC_CDDATA : out std_logic_vector((C_M_AXI_DC_DATA_WIDTH-1) downto 0);
M_AXI_DC_CDLAST : out std_logic;
DBG_CLK : in std_logic;
DBG_TDI : in std_logic;
DBG_TDO : out std_logic;
DBG_REG_EN : in std_logic_vector(0 to 7);
DBG_SHIFT : in std_logic;
DBG_CAPTURE : in std_logic;
DBG_UPDATE : in std_logic;
DEBUG_RST : in std_logic;
Trace_Instruction : out std_logic_vector(0 to 31);
Trace_Valid_Instr : out std_logic;
Trace_PC : out std_logic_vector(0 to 31);
Trace_Reg_Write : out std_logic;
Trace_Reg_Addr : out std_logic_vector(0 to 4);
Trace_MSR_Reg : out std_logic_vector(0 to 14);
Trace_PID_Reg : out std_logic_vector(0 to 7);
Trace_New_Reg_Value : out std_logic_vector(0 to 31);
Trace_Exception_Taken : out std_logic;
Trace_Exception_Kind : out std_logic_vector(0 to 4);
Trace_Jump_Taken : out std_logic;
Trace_Delay_Slot : out std_logic;
Trace_Data_Address : out std_logic_vector(0 to 31);
Trace_Data_Access : out std_logic;
Trace_Data_Read : out std_logic;
Trace_Data_Write : out std_logic;
Trace_Data_Write_Value : out std_logic_vector(0 to 31);
Trace_Data_Byte_Enable : out std_logic_vector(0 to 3);
Trace_DCache_Req : out std_logic;
Trace_DCache_Hit : out std_logic;
Trace_DCache_Rdy : out std_logic;
Trace_DCache_Read : out std_logic;
Trace_ICache_Req : out std_logic;
Trace_ICache_Hit : out std_logic;
Trace_ICache_Rdy : out std_logic;
Trace_OF_PipeRun : out std_logic;
Trace_EX_PipeRun : out std_logic;
Trace_MEM_PipeRun : out std_logic;
Trace_MB_Halted : out std_logic;
Trace_Jump_Hit : out std_logic;
FSL0_S_CLK : out std_logic;
FSL0_S_READ : out std_logic;
FSL0_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL0_S_CONTROL : in std_logic;
FSL0_S_EXISTS : in std_logic;
FSL0_M_CLK : out std_logic;
FSL0_M_WRITE : out std_logic;
FSL0_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL0_M_CONTROL : out std_logic;
FSL0_M_FULL : in std_logic;
FSL1_S_CLK : out std_logic;
FSL1_S_READ : out std_logic;
FSL1_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL1_S_CONTROL : in std_logic;
FSL1_S_EXISTS : in std_logic;
FSL1_M_CLK : out std_logic;
FSL1_M_WRITE : out std_logic;
FSL1_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL1_M_CONTROL : out std_logic;
FSL1_M_FULL : in std_logic;
FSL2_S_CLK : out std_logic;
FSL2_S_READ : out std_logic;
FSL2_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL2_S_CONTROL : in std_logic;
FSL2_S_EXISTS : in std_logic;
FSL2_M_CLK : out std_logic;
FSL2_M_WRITE : out std_logic;
FSL2_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL2_M_CONTROL : out std_logic;
FSL2_M_FULL : in std_logic;
FSL3_S_CLK : out std_logic;
FSL3_S_READ : out std_logic;
FSL3_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL3_S_CONTROL : in std_logic;
FSL3_S_EXISTS : in std_logic;
FSL3_M_CLK : out std_logic;
FSL3_M_WRITE : out std_logic;
FSL3_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL3_M_CONTROL : out std_logic;
FSL3_M_FULL : in std_logic;
FSL4_S_CLK : out std_logic;
FSL4_S_READ : out std_logic;
FSL4_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL4_S_CONTROL : in std_logic;
FSL4_S_EXISTS : in std_logic;
FSL4_M_CLK : out std_logic;
FSL4_M_WRITE : out std_logic;
FSL4_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL4_M_CONTROL : out std_logic;
FSL4_M_FULL : in std_logic;
FSL5_S_CLK : out std_logic;
FSL5_S_READ : out std_logic;
FSL5_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL5_S_CONTROL : in std_logic;
FSL5_S_EXISTS : in std_logic;
FSL5_M_CLK : out std_logic;
FSL5_M_WRITE : out std_logic;
FSL5_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL5_M_CONTROL : out std_logic;
FSL5_M_FULL : in std_logic;
FSL6_S_CLK : out std_logic;
FSL6_S_READ : out std_logic;
FSL6_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL6_S_CONTROL : in std_logic;
FSL6_S_EXISTS : in std_logic;
FSL6_M_CLK : out std_logic;
FSL6_M_WRITE : out std_logic;
FSL6_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL6_M_CONTROL : out std_logic;
FSL6_M_FULL : in std_logic;
FSL7_S_CLK : out std_logic;
FSL7_S_READ : out std_logic;
FSL7_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL7_S_CONTROL : in std_logic;
FSL7_S_EXISTS : in std_logic;
FSL7_M_CLK : out std_logic;
FSL7_M_WRITE : out std_logic;
FSL7_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL7_M_CONTROL : out std_logic;
FSL7_M_FULL : in std_logic;
FSL8_S_CLK : out std_logic;
FSL8_S_READ : out std_logic;
FSL8_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL8_S_CONTROL : in std_logic;
FSL8_S_EXISTS : in std_logic;
FSL8_M_CLK : out std_logic;
FSL8_M_WRITE : out std_logic;
FSL8_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL8_M_CONTROL : out std_logic;
FSL8_M_FULL : in std_logic;
FSL9_S_CLK : out std_logic;
FSL9_S_READ : out std_logic;
FSL9_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL9_S_CONTROL : in std_logic;
FSL9_S_EXISTS : in std_logic;
FSL9_M_CLK : out std_logic;
FSL9_M_WRITE : out std_logic;
FSL9_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL9_M_CONTROL : out std_logic;
FSL9_M_FULL : in std_logic;
FSL10_S_CLK : out std_logic;
FSL10_S_READ : out std_logic;
FSL10_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL10_S_CONTROL : in std_logic;
FSL10_S_EXISTS : in std_logic;
FSL10_M_CLK : out std_logic;
FSL10_M_WRITE : out std_logic;
FSL10_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL10_M_CONTROL : out std_logic;
FSL10_M_FULL : in std_logic;
FSL11_S_CLK : out std_logic;
FSL11_S_READ : out std_logic;
FSL11_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL11_S_CONTROL : in std_logic;
FSL11_S_EXISTS : in std_logic;
FSL11_M_CLK : out std_logic;
FSL11_M_WRITE : out std_logic;
FSL11_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL11_M_CONTROL : out std_logic;
FSL11_M_FULL : in std_logic;
FSL12_S_CLK : out std_logic;
FSL12_S_READ : out std_logic;
FSL12_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL12_S_CONTROL : in std_logic;
FSL12_S_EXISTS : in std_logic;
FSL12_M_CLK : out std_logic;
FSL12_M_WRITE : out std_logic;
FSL12_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL12_M_CONTROL : out std_logic;
FSL12_M_FULL : in std_logic;
FSL13_S_CLK : out std_logic;
FSL13_S_READ : out std_logic;
FSL13_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL13_S_CONTROL : in std_logic;
FSL13_S_EXISTS : in std_logic;
FSL13_M_CLK : out std_logic;
FSL13_M_WRITE : out std_logic;
FSL13_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL13_M_CONTROL : out std_logic;
FSL13_M_FULL : in std_logic;
FSL14_S_CLK : out std_logic;
FSL14_S_READ : out std_logic;
FSL14_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL14_S_CONTROL : in std_logic;
FSL14_S_EXISTS : in std_logic;
FSL14_M_CLK : out std_logic;
FSL14_M_WRITE : out std_logic;
FSL14_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL14_M_CONTROL : out std_logic;
FSL14_M_FULL : in std_logic;
FSL15_S_CLK : out std_logic;
FSL15_S_READ : out std_logic;
FSL15_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL15_S_CONTROL : in std_logic;
FSL15_S_EXISTS : in std_logic;
FSL15_M_CLK : out std_logic;
FSL15_M_WRITE : out std_logic;
FSL15_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL15_M_CONTROL : out std_logic;
FSL15_M_FULL : in std_logic;
M0_AXIS_TLAST : out std_logic;
M0_AXIS_TDATA : out std_logic_vector(C_M0_AXIS_DATA_WIDTH-1 downto 0);
M0_AXIS_TVALID : out std_logic;
M0_AXIS_TREADY : in std_logic;
S0_AXIS_TLAST : in std_logic;
S0_AXIS_TDATA : in std_logic_vector(C_S0_AXIS_DATA_WIDTH-1 downto 0);
S0_AXIS_TVALID : in std_logic;
S0_AXIS_TREADY : out std_logic;
M1_AXIS_TLAST : out std_logic;
M1_AXIS_TDATA : out std_logic_vector(C_M1_AXIS_DATA_WIDTH-1 downto 0);
M1_AXIS_TVALID : out std_logic;
M1_AXIS_TREADY : in std_logic;
S1_AXIS_TLAST : in std_logic;
S1_AXIS_TDATA : in std_logic_vector(C_S1_AXIS_DATA_WIDTH-1 downto 0);
S1_AXIS_TVALID : in std_logic;
S1_AXIS_TREADY : out std_logic;
M2_AXIS_TLAST : out std_logic;
M2_AXIS_TDATA : out std_logic_vector(C_M2_AXIS_DATA_WIDTH-1 downto 0);
M2_AXIS_TVALID : out std_logic;
M2_AXIS_TREADY : in std_logic;
S2_AXIS_TLAST : in std_logic;
S2_AXIS_TDATA : in std_logic_vector(C_S2_AXIS_DATA_WIDTH-1 downto 0);
S2_AXIS_TVALID : in std_logic;
S2_AXIS_TREADY : out std_logic;
M3_AXIS_TLAST : out std_logic;
M3_AXIS_TDATA : out std_logic_vector(C_M3_AXIS_DATA_WIDTH-1 downto 0);
M3_AXIS_TVALID : out std_logic;
M3_AXIS_TREADY : in std_logic;
S3_AXIS_TLAST : in std_logic;
S3_AXIS_TDATA : in std_logic_vector(C_S3_AXIS_DATA_WIDTH-1 downto 0);
S3_AXIS_TVALID : in std_logic;
S3_AXIS_TREADY : out std_logic;
M4_AXIS_TLAST : out std_logic;
M4_AXIS_TDATA : out std_logic_vector(C_M4_AXIS_DATA_WIDTH-1 downto 0);
M4_AXIS_TVALID : out std_logic;
M4_AXIS_TREADY : in std_logic;
S4_AXIS_TLAST : in std_logic;
S4_AXIS_TDATA : in std_logic_vector(C_S4_AXIS_DATA_WIDTH-1 downto 0);
S4_AXIS_TVALID : in std_logic;
S4_AXIS_TREADY : out std_logic;
M5_AXIS_TLAST : out std_logic;
M5_AXIS_TDATA : out std_logic_vector(C_M5_AXIS_DATA_WIDTH-1 downto 0);
M5_AXIS_TVALID : out std_logic;
M5_AXIS_TREADY : in std_logic;
S5_AXIS_TLAST : in std_logic;
S5_AXIS_TDATA : in std_logic_vector(C_S5_AXIS_DATA_WIDTH-1 downto 0);
S5_AXIS_TVALID : in std_logic;
S5_AXIS_TREADY : out std_logic;
M6_AXIS_TLAST : out std_logic;
M6_AXIS_TDATA : out std_logic_vector(C_M6_AXIS_DATA_WIDTH-1 downto 0);
M6_AXIS_TVALID : out std_logic;
M6_AXIS_TREADY : in std_logic;
S6_AXIS_TLAST : in std_logic;
S6_AXIS_TDATA : in std_logic_vector(C_S6_AXIS_DATA_WIDTH-1 downto 0);
S6_AXIS_TVALID : in std_logic;
S6_AXIS_TREADY : out std_logic;
M7_AXIS_TLAST : out std_logic;
M7_AXIS_TDATA : out std_logic_vector(C_M7_AXIS_DATA_WIDTH-1 downto 0);
M7_AXIS_TVALID : out std_logic;
M7_AXIS_TREADY : in std_logic;
S7_AXIS_TLAST : in std_logic;
S7_AXIS_TDATA : in std_logic_vector(C_S7_AXIS_DATA_WIDTH-1 downto 0);
S7_AXIS_TVALID : in std_logic;
S7_AXIS_TREADY : out std_logic;
M8_AXIS_TLAST : out std_logic;
M8_AXIS_TDATA : out std_logic_vector(C_M8_AXIS_DATA_WIDTH-1 downto 0);
M8_AXIS_TVALID : out std_logic;
M8_AXIS_TREADY : in std_logic;
S8_AXIS_TLAST : in std_logic;
S8_AXIS_TDATA : in std_logic_vector(C_S8_AXIS_DATA_WIDTH-1 downto 0);
S8_AXIS_TVALID : in std_logic;
S8_AXIS_TREADY : out std_logic;
M9_AXIS_TLAST : out std_logic;
M9_AXIS_TDATA : out std_logic_vector(C_M9_AXIS_DATA_WIDTH-1 downto 0);
M9_AXIS_TVALID : out std_logic;
M9_AXIS_TREADY : in std_logic;
S9_AXIS_TLAST : in std_logic;
S9_AXIS_TDATA : in std_logic_vector(C_S9_AXIS_DATA_WIDTH-1 downto 0);
S9_AXIS_TVALID : in std_logic;
S9_AXIS_TREADY : out std_logic;
M10_AXIS_TLAST : out std_logic;
M10_AXIS_TDATA : out std_logic_vector(C_M10_AXIS_DATA_WIDTH-1 downto 0);
M10_AXIS_TVALID : out std_logic;
M10_AXIS_TREADY : in std_logic;
S10_AXIS_TLAST : in std_logic;
S10_AXIS_TDATA : in std_logic_vector(C_S10_AXIS_DATA_WIDTH-1 downto 0);
S10_AXIS_TVALID : in std_logic;
S10_AXIS_TREADY : out std_logic;
M11_AXIS_TLAST : out std_logic;
M11_AXIS_TDATA : out std_logic_vector(C_M11_AXIS_DATA_WIDTH-1 downto 0);
M11_AXIS_TVALID : out std_logic;
M11_AXIS_TREADY : in std_logic;
S11_AXIS_TLAST : in std_logic;
S11_AXIS_TDATA : in std_logic_vector(C_S11_AXIS_DATA_WIDTH-1 downto 0);
S11_AXIS_TVALID : in std_logic;
S11_AXIS_TREADY : out std_logic;
M12_AXIS_TLAST : out std_logic;
M12_AXIS_TDATA : out std_logic_vector(C_M12_AXIS_DATA_WIDTH-1 downto 0);
M12_AXIS_TVALID : out std_logic;
M12_AXIS_TREADY : in std_logic;
S12_AXIS_TLAST : in std_logic;
S12_AXIS_TDATA : in std_logic_vector(C_S12_AXIS_DATA_WIDTH-1 downto 0);
S12_AXIS_TVALID : in std_logic;
S12_AXIS_TREADY : out std_logic;
M13_AXIS_TLAST : out std_logic;
M13_AXIS_TDATA : out std_logic_vector(C_M13_AXIS_DATA_WIDTH-1 downto 0);
M13_AXIS_TVALID : out std_logic;
M13_AXIS_TREADY : in std_logic;
S13_AXIS_TLAST : in std_logic;
S13_AXIS_TDATA : in std_logic_vector(C_S13_AXIS_DATA_WIDTH-1 downto 0);
S13_AXIS_TVALID : in std_logic;
S13_AXIS_TREADY : out std_logic;
M14_AXIS_TLAST : out std_logic;
M14_AXIS_TDATA : out std_logic_vector(C_M14_AXIS_DATA_WIDTH-1 downto 0);
M14_AXIS_TVALID : out std_logic;
M14_AXIS_TREADY : in std_logic;
S14_AXIS_TLAST : in std_logic;
S14_AXIS_TDATA : in std_logic_vector(C_S14_AXIS_DATA_WIDTH-1 downto 0);
S14_AXIS_TVALID : in std_logic;
S14_AXIS_TREADY : out std_logic;
M15_AXIS_TLAST : out std_logic;
M15_AXIS_TDATA : out std_logic_vector(C_M15_AXIS_DATA_WIDTH-1 downto 0);
M15_AXIS_TVALID : out std_logic;
M15_AXIS_TREADY : in std_logic;
S15_AXIS_TLAST : in std_logic;
S15_AXIS_TDATA : in std_logic_vector(C_S15_AXIS_DATA_WIDTH-1 downto 0);
S15_AXIS_TVALID : in std_logic;
S15_AXIS_TREADY : out std_logic;
ICACHE_FSL_IN_CLK : out std_logic;
ICACHE_FSL_IN_READ : out std_logic;
ICACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
ICACHE_FSL_IN_CONTROL : in std_logic;
ICACHE_FSL_IN_EXISTS : in std_logic;
ICACHE_FSL_OUT_CLK : out std_logic;
ICACHE_FSL_OUT_WRITE : out std_logic;
ICACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
ICACHE_FSL_OUT_CONTROL : out std_logic;
ICACHE_FSL_OUT_FULL : in std_logic;
DCACHE_FSL_IN_CLK : out std_logic;
DCACHE_FSL_IN_READ : out std_logic;
DCACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
DCACHE_FSL_IN_CONTROL : in std_logic;
DCACHE_FSL_IN_EXISTS : in std_logic;
DCACHE_FSL_OUT_CLK : out std_logic;
DCACHE_FSL_OUT_WRITE : out std_logic;
DCACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
DCACHE_FSL_OUT_CONTROL : out std_logic;
DCACHE_FSL_OUT_FULL : in std_logic
);
end component;
begin
microblaze_0 : microblaze
generic map (
C_SCO => 0,
C_FREQ => 50000000,
C_DATA_SIZE => 32,
C_DYNAMIC_BUS_SIZING => 1,
C_FAMILY => "virtex5",
C_INSTANCE => "microblaze_0",
C_AVOID_PRIMITIVES => 0,
C_FAULT_TOLERANT => 0,
C_ECC_USE_CE_EXCEPTION => 0,
C_LOCKSTEP_SLAVE => 0,
C_ENDIANNESS => 0,
C_AREA_OPTIMIZED => 0,
C_OPTIMIZATION => 0,
C_INTERCONNECT => 1,
C_STREAM_INTERCONNECT => 0,
C_BASE_VECTORS => X"00000000",
C_DPLB_DWIDTH => 64,
C_DPLB_NATIVE_DWIDTH => 32,
C_DPLB_BURST_EN => 0,
C_DPLB_P2P => 0,
C_IPLB_DWIDTH => 64,
C_IPLB_NATIVE_DWIDTH => 32,
C_IPLB_BURST_EN => 0,
C_IPLB_P2P => 0,
C_M_AXI_DP_THREAD_ID_WIDTH => 1,
C_M_AXI_DP_DATA_WIDTH => 32,
C_M_AXI_DP_ADDR_WIDTH => 32,
C_M_AXI_DP_EXCLUSIVE_ACCESS => 0,
C_M_AXI_IP_THREAD_ID_WIDTH => 1,
C_M_AXI_IP_DATA_WIDTH => 32,
C_M_AXI_IP_ADDR_WIDTH => 32,
C_D_AXI => 0,
C_D_PLB => 1,
C_D_LMB => 1,
C_I_AXI => 0,
C_I_PLB => 1,
C_I_LMB => 1,
C_USE_MSR_INSTR => 1,
C_USE_PCMP_INSTR => 1,
C_USE_BARREL => 1,
C_USE_DIV => 0,
C_USE_HW_MUL => 1,
C_USE_FPU => 0,
C_USE_REORDER_INSTR => 1,
C_UNALIGNED_EXCEPTIONS => 0,
C_ILL_OPCODE_EXCEPTION => 0,
C_M_AXI_I_BUS_EXCEPTION => 0,
C_M_AXI_D_BUS_EXCEPTION => 0,
C_IPLB_BUS_EXCEPTION => 0,
C_DPLB_BUS_EXCEPTION => 0,
C_DIV_ZERO_EXCEPTION => 0,
C_FPU_EXCEPTION => 0,
C_FSL_EXCEPTION => 0,
C_USE_STACK_PROTECTION => 0,
C_PVR => 0,
C_PVR_USER1 => X"00",
C_PVR_USER2 => X"00000000",
C_DEBUG_ENABLED => 1,
C_NUMBER_OF_PC_BRK => 1,
C_NUMBER_OF_RD_ADDR_BRK => 0,
C_NUMBER_OF_WR_ADDR_BRK => 0,
C_INTERRUPT_IS_EDGE => 0,
C_EDGE_IS_POSITIVE => 1,
C_RESET_MSR => X"00000000",
C_OPCODE_0x0_ILLEGAL => 0,
C_FSL_LINKS => 0,
C_FSL_DATA_SIZE => 32,
C_USE_EXTENDED_FSL_INSTR => 0,
C_M0_AXIS_DATA_WIDTH => 32,
C_S0_AXIS_DATA_WIDTH => 32,
C_M1_AXIS_DATA_WIDTH => 32,
C_S1_AXIS_DATA_WIDTH => 32,
C_M2_AXIS_DATA_WIDTH => 32,
C_S2_AXIS_DATA_WIDTH => 32,
C_M3_AXIS_DATA_WIDTH => 32,
C_S3_AXIS_DATA_WIDTH => 32,
C_M4_AXIS_DATA_WIDTH => 32,
C_S4_AXIS_DATA_WIDTH => 32,
C_M5_AXIS_DATA_WIDTH => 32,
C_S5_AXIS_DATA_WIDTH => 32,
C_M6_AXIS_DATA_WIDTH => 32,
C_S6_AXIS_DATA_WIDTH => 32,
C_M7_AXIS_DATA_WIDTH => 32,
C_S7_AXIS_DATA_WIDTH => 32,
C_M8_AXIS_DATA_WIDTH => 32,
C_S8_AXIS_DATA_WIDTH => 32,
C_M9_AXIS_DATA_WIDTH => 32,
C_S9_AXIS_DATA_WIDTH => 32,
C_M10_AXIS_DATA_WIDTH => 32,
C_S10_AXIS_DATA_WIDTH => 32,
C_M11_AXIS_DATA_WIDTH => 32,
C_S11_AXIS_DATA_WIDTH => 32,
C_M12_AXIS_DATA_WIDTH => 32,
C_S12_AXIS_DATA_WIDTH => 32,
C_M13_AXIS_DATA_WIDTH => 32,
C_S13_AXIS_DATA_WIDTH => 32,
C_M14_AXIS_DATA_WIDTH => 32,
C_S14_AXIS_DATA_WIDTH => 32,
C_M15_AXIS_DATA_WIDTH => 32,
C_S15_AXIS_DATA_WIDTH => 32,
C_ICACHE_BASEADDR => X"00000000",
C_ICACHE_HIGHADDR => X"3FFFFFFF",
C_USE_ICACHE => 0,
C_ALLOW_ICACHE_WR => 1,
C_ADDR_TAG_BITS => 0,
C_CACHE_BYTE_SIZE => 8192,
C_ICACHE_USE_FSL => 1,
C_ICACHE_LINE_LEN => 4,
C_ICACHE_ALWAYS_USED => 0,
C_ICACHE_INTERFACE => 0,
C_ICACHE_VICTIMS => 0,
C_ICACHE_STREAMS => 0,
C_ICACHE_FORCE_TAG_LUTRAM => 0,
C_ICACHE_DATA_WIDTH => 0,
C_M_AXI_IC_THREAD_ID_WIDTH => 1,
C_M_AXI_IC_DATA_WIDTH => 32,
C_M_AXI_IC_ADDR_WIDTH => 32,
C_M_AXI_IC_USER_VALUE => 2#11111#,
C_M_AXI_IC_AWUSER_WIDTH => 5,
C_M_AXI_IC_ARUSER_WIDTH => 5,
C_M_AXI_IC_WUSER_WIDTH => 1,
C_M_AXI_IC_RUSER_WIDTH => 1,
C_M_AXI_IC_BUSER_WIDTH => 1,
C_DCACHE_BASEADDR => X"00000000",
C_DCACHE_HIGHADDR => X"3FFFFFFF",
C_USE_DCACHE => 0,
C_ALLOW_DCACHE_WR => 1,
C_DCACHE_ADDR_TAG => 0,
C_DCACHE_BYTE_SIZE => 8192,
C_DCACHE_USE_FSL => 1,
C_DCACHE_LINE_LEN => 4,
C_DCACHE_ALWAYS_USED => 0,
C_DCACHE_INTERFACE => 0,
C_DCACHE_USE_WRITEBACK => 0,
C_DCACHE_VICTIMS => 0,
C_DCACHE_FORCE_TAG_LUTRAM => 0,
C_DCACHE_DATA_WIDTH => 0,
C_M_AXI_DC_THREAD_ID_WIDTH => 1,
C_M_AXI_DC_DATA_WIDTH => 32,
C_M_AXI_DC_ADDR_WIDTH => 32,
C_M_AXI_DC_EXCLUSIVE_ACCESS => 0,
C_M_AXI_DC_USER_VALUE => 2#11111#,
C_M_AXI_DC_AWUSER_WIDTH => 5,
C_M_AXI_DC_ARUSER_WIDTH => 5,
C_M_AXI_DC_WUSER_WIDTH => 1,
C_M_AXI_DC_RUSER_WIDTH => 1,
C_M_AXI_DC_BUSER_WIDTH => 1,
C_USE_MMU => 0,
C_MMU_DTLB_SIZE => 4,
C_MMU_ITLB_SIZE => 2,
C_MMU_TLB_ACCESS => 3,
C_MMU_ZONES => 16,
C_MMU_PRIVILEGED_INSTR => 0,
C_USE_INTERRUPT => 0,
C_USE_EXT_BRK => 1,
C_USE_EXT_NM_BRK => 1,
C_USE_BRANCH_TARGET_CACHE => 0,
C_BRANCH_TARGET_CACHE_SIZE => 0,
C_PC_WIDTH => 32
)
port map (
CLK => CLK,
RESET => RESET,
MB_RESET => MB_RESET,
INTERRUPT => INTERRUPT,
INTERRUPT_ADDRESS => INTERRUPT_ADDRESS,
INTERRUPT_ACK => INTERRUPT_ACK,
EXT_BRK => EXT_BRK,
EXT_NM_BRK => EXT_NM_BRK,
DBG_STOP => DBG_STOP,
MB_Halted => MB_Halted,
MB_Error => MB_Error,
WAKEUP => WAKEUP,
SLEEP => SLEEP,
DBG_WAKEUP => DBG_WAKEUP,
LOCKSTEP_MASTER_OUT => LOCKSTEP_MASTER_OUT,
LOCKSTEP_SLAVE_IN => LOCKSTEP_SLAVE_IN,
LOCKSTEP_OUT => LOCKSTEP_OUT,
INSTR => INSTR,
IREADY => IREADY,
IWAIT => IWAIT,
ICE => ICE,
IUE => IUE,
INSTR_ADDR => INSTR_ADDR,
IFETCH => IFETCH,
I_AS => I_AS,
IPLB_M_ABort => IPLB_M_ABort,
IPLB_M_ABus => IPLB_M_ABus,
IPLB_M_UABus => IPLB_M_UABus,
IPLB_M_BE => IPLB_M_BE,
IPLB_M_busLock => IPLB_M_busLock,
IPLB_M_lockErr => IPLB_M_lockErr,
IPLB_M_MSize => IPLB_M_MSize,
IPLB_M_priority => IPLB_M_priority,
IPLB_M_rdBurst => IPLB_M_rdBurst,
IPLB_M_request => IPLB_M_request,
IPLB_M_RNW => IPLB_M_RNW,
IPLB_M_size => IPLB_M_size,
IPLB_M_TAttribute => IPLB_M_TAttribute,
IPLB_M_type => IPLB_M_type,
IPLB_M_wrBurst => IPLB_M_wrBurst,
IPLB_M_wrDBus => IPLB_M_wrDBus,
IPLB_MBusy => IPLB_MBusy,
IPLB_MRdErr => IPLB_MRdErr,
IPLB_MWrErr => IPLB_MWrErr,
IPLB_MIRQ => IPLB_MIRQ,
IPLB_MWrBTerm => IPLB_MWrBTerm,
IPLB_MWrDAck => IPLB_MWrDAck,
IPLB_MAddrAck => IPLB_MAddrAck,
IPLB_MRdBTerm => IPLB_MRdBTerm,
IPLB_MRdDAck => IPLB_MRdDAck,
IPLB_MRdDBus => IPLB_MRdDBus,
IPLB_MRdWdAddr => IPLB_MRdWdAddr,
IPLB_MRearbitrate => IPLB_MRearbitrate,
IPLB_MSSize => IPLB_MSSize,
IPLB_MTimeout => IPLB_MTimeout,
DATA_READ => DATA_READ,
DREADY => DREADY,
DWAIT => DWAIT,
DCE => DCE,
DUE => DUE,
DATA_WRITE => DATA_WRITE,
DATA_ADDR => DATA_ADDR,
D_AS => D_AS,
READ_STROBE => READ_STROBE,
WRITE_STROBE => WRITE_STROBE,
BYTE_ENABLE => BYTE_ENABLE,
DPLB_M_ABort => DPLB_M_ABort,
DPLB_M_ABus => DPLB_M_ABus,
DPLB_M_UABus => DPLB_M_UABus,
DPLB_M_BE => DPLB_M_BE,
DPLB_M_busLock => DPLB_M_busLock,
DPLB_M_lockErr => DPLB_M_lockErr,
DPLB_M_MSize => DPLB_M_MSize,
DPLB_M_priority => DPLB_M_priority,
DPLB_M_rdBurst => DPLB_M_rdBurst,
DPLB_M_request => DPLB_M_request,
DPLB_M_RNW => DPLB_M_RNW,
DPLB_M_size => DPLB_M_size,
DPLB_M_TAttribute => DPLB_M_TAttribute,
DPLB_M_type => DPLB_M_type,
DPLB_M_wrBurst => DPLB_M_wrBurst,
DPLB_M_wrDBus => DPLB_M_wrDBus,
DPLB_MBusy => DPLB_MBusy,
DPLB_MRdErr => DPLB_MRdErr,
DPLB_MWrErr => DPLB_MWrErr,
DPLB_MIRQ => DPLB_MIRQ,
DPLB_MWrBTerm => DPLB_MWrBTerm,
DPLB_MWrDAck => DPLB_MWrDAck,
DPLB_MAddrAck => DPLB_MAddrAck,
DPLB_MRdBTerm => DPLB_MRdBTerm,
DPLB_MRdDAck => DPLB_MRdDAck,
DPLB_MRdDBus => DPLB_MRdDBus,
DPLB_MRdWdAddr => DPLB_MRdWdAddr,
DPLB_MRearbitrate => DPLB_MRearbitrate,
DPLB_MSSize => DPLB_MSSize,
DPLB_MTimeout => DPLB_MTimeout,
M_AXI_IP_AWID => M_AXI_IP_AWID,
M_AXI_IP_AWADDR => M_AXI_IP_AWADDR,
M_AXI_IP_AWLEN => M_AXI_IP_AWLEN,
M_AXI_IP_AWSIZE => M_AXI_IP_AWSIZE,
M_AXI_IP_AWBURST => M_AXI_IP_AWBURST,
M_AXI_IP_AWLOCK => M_AXI_IP_AWLOCK,
M_AXI_IP_AWCACHE => M_AXI_IP_AWCACHE,
M_AXI_IP_AWPROT => M_AXI_IP_AWPROT,
M_AXI_IP_AWQOS => M_AXI_IP_AWQOS,
M_AXI_IP_AWVALID => M_AXI_IP_AWVALID,
M_AXI_IP_AWREADY => M_AXI_IP_AWREADY,
M_AXI_IP_WDATA => M_AXI_IP_WDATA,
M_AXI_IP_WSTRB => M_AXI_IP_WSTRB,
M_AXI_IP_WLAST => M_AXI_IP_WLAST,
M_AXI_IP_WVALID => M_AXI_IP_WVALID,
M_AXI_IP_WREADY => M_AXI_IP_WREADY,
M_AXI_IP_BID => M_AXI_IP_BID,
M_AXI_IP_BRESP => M_AXI_IP_BRESP,
M_AXI_IP_BVALID => M_AXI_IP_BVALID,
M_AXI_IP_BREADY => M_AXI_IP_BREADY,
M_AXI_IP_ARID => M_AXI_IP_ARID,
M_AXI_IP_ARADDR => M_AXI_IP_ARADDR,
M_AXI_IP_ARLEN => M_AXI_IP_ARLEN,
M_AXI_IP_ARSIZE => M_AXI_IP_ARSIZE,
M_AXI_IP_ARBURST => M_AXI_IP_ARBURST,
M_AXI_IP_ARLOCK => M_AXI_IP_ARLOCK,
M_AXI_IP_ARCACHE => M_AXI_IP_ARCACHE,
M_AXI_IP_ARPROT => M_AXI_IP_ARPROT,
M_AXI_IP_ARQOS => M_AXI_IP_ARQOS,
M_AXI_IP_ARVALID => M_AXI_IP_ARVALID,
M_AXI_IP_ARREADY => M_AXI_IP_ARREADY,
M_AXI_IP_RID => M_AXI_IP_RID,
M_AXI_IP_RDATA => M_AXI_IP_RDATA,
M_AXI_IP_RRESP => M_AXI_IP_RRESP,
M_AXI_IP_RLAST => M_AXI_IP_RLAST,
M_AXI_IP_RVALID => M_AXI_IP_RVALID,
M_AXI_IP_RREADY => M_AXI_IP_RREADY,
M_AXI_DP_AWID => M_AXI_DP_AWID,
M_AXI_DP_AWADDR => M_AXI_DP_AWADDR,
M_AXI_DP_AWLEN => M_AXI_DP_AWLEN,
M_AXI_DP_AWSIZE => M_AXI_DP_AWSIZE,
M_AXI_DP_AWBURST => M_AXI_DP_AWBURST,
M_AXI_DP_AWLOCK => M_AXI_DP_AWLOCK,
M_AXI_DP_AWCACHE => M_AXI_DP_AWCACHE,
M_AXI_DP_AWPROT => M_AXI_DP_AWPROT,
M_AXI_DP_AWQOS => M_AXI_DP_AWQOS,
M_AXI_DP_AWVALID => M_AXI_DP_AWVALID,
M_AXI_DP_AWREADY => M_AXI_DP_AWREADY,
M_AXI_DP_WDATA => M_AXI_DP_WDATA,
M_AXI_DP_WSTRB => M_AXI_DP_WSTRB,
M_AXI_DP_WLAST => M_AXI_DP_WLAST,
M_AXI_DP_WVALID => M_AXI_DP_WVALID,
M_AXI_DP_WREADY => M_AXI_DP_WREADY,
M_AXI_DP_BID => M_AXI_DP_BID,
M_AXI_DP_BRESP => M_AXI_DP_BRESP,
M_AXI_DP_BVALID => M_AXI_DP_BVALID,
M_AXI_DP_BREADY => M_AXI_DP_BREADY,
M_AXI_DP_ARID => M_AXI_DP_ARID,
M_AXI_DP_ARADDR => M_AXI_DP_ARADDR,
M_AXI_DP_ARLEN => M_AXI_DP_ARLEN,
M_AXI_DP_ARSIZE => M_AXI_DP_ARSIZE,
M_AXI_DP_ARBURST => M_AXI_DP_ARBURST,
M_AXI_DP_ARLOCK => M_AXI_DP_ARLOCK,
M_AXI_DP_ARCACHE => M_AXI_DP_ARCACHE,
M_AXI_DP_ARPROT => M_AXI_DP_ARPROT,
M_AXI_DP_ARQOS => M_AXI_DP_ARQOS,
M_AXI_DP_ARVALID => M_AXI_DP_ARVALID,
M_AXI_DP_ARREADY => M_AXI_DP_ARREADY,
M_AXI_DP_RID => M_AXI_DP_RID,
M_AXI_DP_RDATA => M_AXI_DP_RDATA,
M_AXI_DP_RRESP => M_AXI_DP_RRESP,
M_AXI_DP_RLAST => M_AXI_DP_RLAST,
M_AXI_DP_RVALID => M_AXI_DP_RVALID,
M_AXI_DP_RREADY => M_AXI_DP_RREADY,
M_AXI_IC_AWID => M_AXI_IC_AWID,
M_AXI_IC_AWADDR => M_AXI_IC_AWADDR,
M_AXI_IC_AWLEN => M_AXI_IC_AWLEN,
M_AXI_IC_AWSIZE => M_AXI_IC_AWSIZE,
M_AXI_IC_AWBURST => M_AXI_IC_AWBURST,
M_AXI_IC_AWLOCK => M_AXI_IC_AWLOCK,
M_AXI_IC_AWCACHE => M_AXI_IC_AWCACHE,
M_AXI_IC_AWPROT => M_AXI_IC_AWPROT,
M_AXI_IC_AWQOS => M_AXI_IC_AWQOS,
M_AXI_IC_AWVALID => M_AXI_IC_AWVALID,
M_AXI_IC_AWREADY => M_AXI_IC_AWREADY,
M_AXI_IC_AWUSER => M_AXI_IC_AWUSER,
M_AXI_IC_AWDOMAIN => M_AXI_IC_AWDOMAIN,
M_AXI_IC_AWSNOOP => M_AXI_IC_AWSNOOP,
M_AXI_IC_AWBAR => M_AXI_IC_AWBAR,
M_AXI_IC_WDATA => M_AXI_IC_WDATA,
M_AXI_IC_WSTRB => M_AXI_IC_WSTRB,
M_AXI_IC_WLAST => M_AXI_IC_WLAST,
M_AXI_IC_WVALID => M_AXI_IC_WVALID,
M_AXI_IC_WREADY => M_AXI_IC_WREADY,
M_AXI_IC_WUSER => M_AXI_IC_WUSER,
M_AXI_IC_BID => M_AXI_IC_BID,
M_AXI_IC_BRESP => M_AXI_IC_BRESP,
M_AXI_IC_BVALID => M_AXI_IC_BVALID,
M_AXI_IC_BREADY => M_AXI_IC_BREADY,
M_AXI_IC_BUSER => M_AXI_IC_BUSER,
M_AXI_IC_WACK => M_AXI_IC_WACK,
M_AXI_IC_ARID => M_AXI_IC_ARID,
M_AXI_IC_ARADDR => M_AXI_IC_ARADDR,
M_AXI_IC_ARLEN => M_AXI_IC_ARLEN,
M_AXI_IC_ARSIZE => M_AXI_IC_ARSIZE,
M_AXI_IC_ARBURST => M_AXI_IC_ARBURST,
M_AXI_IC_ARLOCK => M_AXI_IC_ARLOCK,
M_AXI_IC_ARCACHE => M_AXI_IC_ARCACHE,
M_AXI_IC_ARPROT => M_AXI_IC_ARPROT,
M_AXI_IC_ARQOS => M_AXI_IC_ARQOS,
M_AXI_IC_ARVALID => M_AXI_IC_ARVALID,
M_AXI_IC_ARREADY => M_AXI_IC_ARREADY,
M_AXI_IC_ARUSER => M_AXI_IC_ARUSER,
M_AXI_IC_ARDOMAIN => M_AXI_IC_ARDOMAIN,
M_AXI_IC_ARSNOOP => M_AXI_IC_ARSNOOP,
M_AXI_IC_ARBAR => M_AXI_IC_ARBAR,
M_AXI_IC_RID => M_AXI_IC_RID,
M_AXI_IC_RDATA => M_AXI_IC_RDATA,
M_AXI_IC_RRESP => M_AXI_IC_RRESP,
M_AXI_IC_RLAST => M_AXI_IC_RLAST,
M_AXI_IC_RVALID => M_AXI_IC_RVALID,
M_AXI_IC_RREADY => M_AXI_IC_RREADY,
M_AXI_IC_RUSER => M_AXI_IC_RUSER,
M_AXI_IC_RACK => M_AXI_IC_RACK,
M_AXI_IC_ACVALID => M_AXI_IC_ACVALID,
M_AXI_IC_ACADDR => M_AXI_IC_ACADDR,
M_AXI_IC_ACSNOOP => M_AXI_IC_ACSNOOP,
M_AXI_IC_ACPROT => M_AXI_IC_ACPROT,
M_AXI_IC_ACREADY => M_AXI_IC_ACREADY,
M_AXI_IC_CRREADY => M_AXI_IC_CRREADY,
M_AXI_IC_CRVALID => M_AXI_IC_CRVALID,
M_AXI_IC_CRRESP => M_AXI_IC_CRRESP,
M_AXI_IC_CDVALID => M_AXI_IC_CDVALID,
M_AXI_IC_CDREADY => M_AXI_IC_CDREADY,
M_AXI_IC_CDDATA => M_AXI_IC_CDDATA,
M_AXI_IC_CDLAST => M_AXI_IC_CDLAST,
M_AXI_DC_AWID => M_AXI_DC_AWID,
M_AXI_DC_AWADDR => M_AXI_DC_AWADDR,
M_AXI_DC_AWLEN => M_AXI_DC_AWLEN,
M_AXI_DC_AWSIZE => M_AXI_DC_AWSIZE,
M_AXI_DC_AWBURST => M_AXI_DC_AWBURST,
M_AXI_DC_AWLOCK => M_AXI_DC_AWLOCK,
M_AXI_DC_AWCACHE => M_AXI_DC_AWCACHE,
M_AXI_DC_AWPROT => M_AXI_DC_AWPROT,
M_AXI_DC_AWQOS => M_AXI_DC_AWQOS,
M_AXI_DC_AWVALID => M_AXI_DC_AWVALID,
M_AXI_DC_AWREADY => M_AXI_DC_AWREADY,
M_AXI_DC_AWUSER => M_AXI_DC_AWUSER,
M_AXI_DC_AWDOMAIN => M_AXI_DC_AWDOMAIN,
M_AXI_DC_AWSNOOP => M_AXI_DC_AWSNOOP,
M_AXI_DC_AWBAR => M_AXI_DC_AWBAR,
M_AXI_DC_WDATA => M_AXI_DC_WDATA,
M_AXI_DC_WSTRB => M_AXI_DC_WSTRB,
M_AXI_DC_WLAST => M_AXI_DC_WLAST,
M_AXI_DC_WVALID => M_AXI_DC_WVALID,
M_AXI_DC_WREADY => M_AXI_DC_WREADY,
M_AXI_DC_WUSER => M_AXI_DC_WUSER,
M_AXI_DC_BID => M_AXI_DC_BID,
M_AXI_DC_BRESP => M_AXI_DC_BRESP,
M_AXI_DC_BVALID => M_AXI_DC_BVALID,
M_AXI_DC_BREADY => M_AXI_DC_BREADY,
M_AXI_DC_BUSER => M_AXI_DC_BUSER,
M_AXI_DC_WACK => M_AXI_DC_WACK,
M_AXI_DC_ARID => M_AXI_DC_ARID,
M_AXI_DC_ARADDR => M_AXI_DC_ARADDR,
M_AXI_DC_ARLEN => M_AXI_DC_ARLEN,
M_AXI_DC_ARSIZE => M_AXI_DC_ARSIZE,
M_AXI_DC_ARBURST => M_AXI_DC_ARBURST,
M_AXI_DC_ARLOCK => M_AXI_DC_ARLOCK,
M_AXI_DC_ARCACHE => M_AXI_DC_ARCACHE,
M_AXI_DC_ARPROT => M_AXI_DC_ARPROT,
M_AXI_DC_ARQOS => M_AXI_DC_ARQOS,
M_AXI_DC_ARVALID => M_AXI_DC_ARVALID,
M_AXI_DC_ARREADY => M_AXI_DC_ARREADY,
M_AXI_DC_ARUSER => M_AXI_DC_ARUSER,
M_AXI_DC_ARDOMAIN => M_AXI_DC_ARDOMAIN,
M_AXI_DC_ARSNOOP => M_AXI_DC_ARSNOOP,
M_AXI_DC_ARBAR => M_AXI_DC_ARBAR,
M_AXI_DC_RID => M_AXI_DC_RID,
M_AXI_DC_RDATA => M_AXI_DC_RDATA,
M_AXI_DC_RRESP => M_AXI_DC_RRESP,
M_AXI_DC_RLAST => M_AXI_DC_RLAST,
M_AXI_DC_RVALID => M_AXI_DC_RVALID,
M_AXI_DC_RREADY => M_AXI_DC_RREADY,
M_AXI_DC_RUSER => M_AXI_DC_RUSER,
M_AXI_DC_RACK => M_AXI_DC_RACK,
M_AXI_DC_ACVALID => M_AXI_DC_ACVALID,
M_AXI_DC_ACADDR => M_AXI_DC_ACADDR,
M_AXI_DC_ACSNOOP => M_AXI_DC_ACSNOOP,
M_AXI_DC_ACPROT => M_AXI_DC_ACPROT,
M_AXI_DC_ACREADY => M_AXI_DC_ACREADY,
M_AXI_DC_CRREADY => M_AXI_DC_CRREADY,
M_AXI_DC_CRVALID => M_AXI_DC_CRVALID,
M_AXI_DC_CRRESP => M_AXI_DC_CRRESP,
M_AXI_DC_CDVALID => M_AXI_DC_CDVALID,
M_AXI_DC_CDREADY => M_AXI_DC_CDREADY,
M_AXI_DC_CDDATA => M_AXI_DC_CDDATA,
M_AXI_DC_CDLAST => M_AXI_DC_CDLAST,
DBG_CLK => DBG_CLK,
DBG_TDI => DBG_TDI,
DBG_TDO => DBG_TDO,
DBG_REG_EN => DBG_REG_EN,
DBG_SHIFT => DBG_SHIFT,
DBG_CAPTURE => DBG_CAPTURE,
DBG_UPDATE => DBG_UPDATE,
DEBUG_RST => DEBUG_RST,
Trace_Instruction => Trace_Instruction,
Trace_Valid_Instr => Trace_Valid_Instr,
Trace_PC => Trace_PC,
Trace_Reg_Write => Trace_Reg_Write,
Trace_Reg_Addr => Trace_Reg_Addr,
Trace_MSR_Reg => Trace_MSR_Reg,
Trace_PID_Reg => Trace_PID_Reg,
Trace_New_Reg_Value => Trace_New_Reg_Value,
Trace_Exception_Taken => Trace_Exception_Taken,
Trace_Exception_Kind => Trace_Exception_Kind,
Trace_Jump_Taken => Trace_Jump_Taken,
Trace_Delay_Slot => Trace_Delay_Slot,
Trace_Data_Address => Trace_Data_Address,
Trace_Data_Access => Trace_Data_Access,
Trace_Data_Read => Trace_Data_Read,
Trace_Data_Write => Trace_Data_Write,
Trace_Data_Write_Value => Trace_Data_Write_Value,
Trace_Data_Byte_Enable => Trace_Data_Byte_Enable,
Trace_DCache_Req => Trace_DCache_Req,
Trace_DCache_Hit => Trace_DCache_Hit,
Trace_DCache_Rdy => Trace_DCache_Rdy,
Trace_DCache_Read => Trace_DCache_Read,
Trace_ICache_Req => Trace_ICache_Req,
Trace_ICache_Hit => Trace_ICache_Hit,
Trace_ICache_Rdy => Trace_ICache_Rdy,
Trace_OF_PipeRun => Trace_OF_PipeRun,
Trace_EX_PipeRun => Trace_EX_PipeRun,
Trace_MEM_PipeRun => Trace_MEM_PipeRun,
Trace_MB_Halted => Trace_MB_Halted,
Trace_Jump_Hit => Trace_Jump_Hit,
FSL0_S_CLK => FSL0_S_CLK,
FSL0_S_READ => FSL0_S_READ,
FSL0_S_DATA => FSL0_S_DATA,
FSL0_S_CONTROL => FSL0_S_CONTROL,
FSL0_S_EXISTS => FSL0_S_EXISTS,
FSL0_M_CLK => FSL0_M_CLK,
FSL0_M_WRITE => FSL0_M_WRITE,
FSL0_M_DATA => FSL0_M_DATA,
FSL0_M_CONTROL => FSL0_M_CONTROL,
FSL0_M_FULL => FSL0_M_FULL,
FSL1_S_CLK => FSL1_S_CLK,
FSL1_S_READ => FSL1_S_READ,
FSL1_S_DATA => FSL1_S_DATA,
FSL1_S_CONTROL => FSL1_S_CONTROL,
FSL1_S_EXISTS => FSL1_S_EXISTS,
FSL1_M_CLK => FSL1_M_CLK,
FSL1_M_WRITE => FSL1_M_WRITE,
FSL1_M_DATA => FSL1_M_DATA,
FSL1_M_CONTROL => FSL1_M_CONTROL,
FSL1_M_FULL => FSL1_M_FULL,
FSL2_S_CLK => FSL2_S_CLK,
FSL2_S_READ => FSL2_S_READ,
FSL2_S_DATA => FSL2_S_DATA,
FSL2_S_CONTROL => FSL2_S_CONTROL,
FSL2_S_EXISTS => FSL2_S_EXISTS,
FSL2_M_CLK => FSL2_M_CLK,
FSL2_M_WRITE => FSL2_M_WRITE,
FSL2_M_DATA => FSL2_M_DATA,
FSL2_M_CONTROL => FSL2_M_CONTROL,
FSL2_M_FULL => FSL2_M_FULL,
FSL3_S_CLK => FSL3_S_CLK,
FSL3_S_READ => FSL3_S_READ,
FSL3_S_DATA => FSL3_S_DATA,
FSL3_S_CONTROL => FSL3_S_CONTROL,
FSL3_S_EXISTS => FSL3_S_EXISTS,
FSL3_M_CLK => FSL3_M_CLK,
FSL3_M_WRITE => FSL3_M_WRITE,
FSL3_M_DATA => FSL3_M_DATA,
FSL3_M_CONTROL => FSL3_M_CONTROL,
FSL3_M_FULL => FSL3_M_FULL,
FSL4_S_CLK => FSL4_S_CLK,
FSL4_S_READ => FSL4_S_READ,
FSL4_S_DATA => FSL4_S_DATA,
FSL4_S_CONTROL => FSL4_S_CONTROL,
FSL4_S_EXISTS => FSL4_S_EXISTS,
FSL4_M_CLK => FSL4_M_CLK,
FSL4_M_WRITE => FSL4_M_WRITE,
FSL4_M_DATA => FSL4_M_DATA,
FSL4_M_CONTROL => FSL4_M_CONTROL,
FSL4_M_FULL => FSL4_M_FULL,
FSL5_S_CLK => FSL5_S_CLK,
FSL5_S_READ => FSL5_S_READ,
FSL5_S_DATA => FSL5_S_DATA,
FSL5_S_CONTROL => FSL5_S_CONTROL,
FSL5_S_EXISTS => FSL5_S_EXISTS,
FSL5_M_CLK => FSL5_M_CLK,
FSL5_M_WRITE => FSL5_M_WRITE,
FSL5_M_DATA => FSL5_M_DATA,
FSL5_M_CONTROL => FSL5_M_CONTROL,
FSL5_M_FULL => FSL5_M_FULL,
FSL6_S_CLK => FSL6_S_CLK,
FSL6_S_READ => FSL6_S_READ,
FSL6_S_DATA => FSL6_S_DATA,
FSL6_S_CONTROL => FSL6_S_CONTROL,
FSL6_S_EXISTS => FSL6_S_EXISTS,
FSL6_M_CLK => FSL6_M_CLK,
FSL6_M_WRITE => FSL6_M_WRITE,
FSL6_M_DATA => FSL6_M_DATA,
FSL6_M_CONTROL => FSL6_M_CONTROL,
FSL6_M_FULL => FSL6_M_FULL,
FSL7_S_CLK => FSL7_S_CLK,
FSL7_S_READ => FSL7_S_READ,
FSL7_S_DATA => FSL7_S_DATA,
FSL7_S_CONTROL => FSL7_S_CONTROL,
FSL7_S_EXISTS => FSL7_S_EXISTS,
FSL7_M_CLK => FSL7_M_CLK,
FSL7_M_WRITE => FSL7_M_WRITE,
FSL7_M_DATA => FSL7_M_DATA,
FSL7_M_CONTROL => FSL7_M_CONTROL,
FSL7_M_FULL => FSL7_M_FULL,
FSL8_S_CLK => FSL8_S_CLK,
FSL8_S_READ => FSL8_S_READ,
FSL8_S_DATA => FSL8_S_DATA,
FSL8_S_CONTROL => FSL8_S_CONTROL,
FSL8_S_EXISTS => FSL8_S_EXISTS,
FSL8_M_CLK => FSL8_M_CLK,
FSL8_M_WRITE => FSL8_M_WRITE,
FSL8_M_DATA => FSL8_M_DATA,
FSL8_M_CONTROL => FSL8_M_CONTROL,
FSL8_M_FULL => FSL8_M_FULL,
FSL9_S_CLK => FSL9_S_CLK,
FSL9_S_READ => FSL9_S_READ,
FSL9_S_DATA => FSL9_S_DATA,
FSL9_S_CONTROL => FSL9_S_CONTROL,
FSL9_S_EXISTS => FSL9_S_EXISTS,
FSL9_M_CLK => FSL9_M_CLK,
FSL9_M_WRITE => FSL9_M_WRITE,
FSL9_M_DATA => FSL9_M_DATA,
FSL9_M_CONTROL => FSL9_M_CONTROL,
FSL9_M_FULL => FSL9_M_FULL,
FSL10_S_CLK => FSL10_S_CLK,
FSL10_S_READ => FSL10_S_READ,
FSL10_S_DATA => FSL10_S_DATA,
FSL10_S_CONTROL => FSL10_S_CONTROL,
FSL10_S_EXISTS => FSL10_S_EXISTS,
FSL10_M_CLK => FSL10_M_CLK,
FSL10_M_WRITE => FSL10_M_WRITE,
FSL10_M_DATA => FSL10_M_DATA,
FSL10_M_CONTROL => FSL10_M_CONTROL,
FSL10_M_FULL => FSL10_M_FULL,
FSL11_S_CLK => FSL11_S_CLK,
FSL11_S_READ => FSL11_S_READ,
FSL11_S_DATA => FSL11_S_DATA,
FSL11_S_CONTROL => FSL11_S_CONTROL,
FSL11_S_EXISTS => FSL11_S_EXISTS,
FSL11_M_CLK => FSL11_M_CLK,
FSL11_M_WRITE => FSL11_M_WRITE,
FSL11_M_DATA => FSL11_M_DATA,
FSL11_M_CONTROL => FSL11_M_CONTROL,
FSL11_M_FULL => FSL11_M_FULL,
FSL12_S_CLK => FSL12_S_CLK,
FSL12_S_READ => FSL12_S_READ,
FSL12_S_DATA => FSL12_S_DATA,
FSL12_S_CONTROL => FSL12_S_CONTROL,
FSL12_S_EXISTS => FSL12_S_EXISTS,
FSL12_M_CLK => FSL12_M_CLK,
FSL12_M_WRITE => FSL12_M_WRITE,
FSL12_M_DATA => FSL12_M_DATA,
FSL12_M_CONTROL => FSL12_M_CONTROL,
FSL12_M_FULL => FSL12_M_FULL,
FSL13_S_CLK => FSL13_S_CLK,
FSL13_S_READ => FSL13_S_READ,
FSL13_S_DATA => FSL13_S_DATA,
FSL13_S_CONTROL => FSL13_S_CONTROL,
FSL13_S_EXISTS => FSL13_S_EXISTS,
FSL13_M_CLK => FSL13_M_CLK,
FSL13_M_WRITE => FSL13_M_WRITE,
FSL13_M_DATA => FSL13_M_DATA,
FSL13_M_CONTROL => FSL13_M_CONTROL,
FSL13_M_FULL => FSL13_M_FULL,
FSL14_S_CLK => FSL14_S_CLK,
FSL14_S_READ => FSL14_S_READ,
FSL14_S_DATA => FSL14_S_DATA,
FSL14_S_CONTROL => FSL14_S_CONTROL,
FSL14_S_EXISTS => FSL14_S_EXISTS,
FSL14_M_CLK => FSL14_M_CLK,
FSL14_M_WRITE => FSL14_M_WRITE,
FSL14_M_DATA => FSL14_M_DATA,
FSL14_M_CONTROL => FSL14_M_CONTROL,
FSL14_M_FULL => FSL14_M_FULL,
FSL15_S_CLK => FSL15_S_CLK,
FSL15_S_READ => FSL15_S_READ,
FSL15_S_DATA => FSL15_S_DATA,
FSL15_S_CONTROL => FSL15_S_CONTROL,
FSL15_S_EXISTS => FSL15_S_EXISTS,
FSL15_M_CLK => FSL15_M_CLK,
FSL15_M_WRITE => FSL15_M_WRITE,
FSL15_M_DATA => FSL15_M_DATA,
FSL15_M_CONTROL => FSL15_M_CONTROL,
FSL15_M_FULL => FSL15_M_FULL,
M0_AXIS_TLAST => M0_AXIS_TLAST,
M0_AXIS_TDATA => M0_AXIS_TDATA,
M0_AXIS_TVALID => M0_AXIS_TVALID,
M0_AXIS_TREADY => M0_AXIS_TREADY,
S0_AXIS_TLAST => S0_AXIS_TLAST,
S0_AXIS_TDATA => S0_AXIS_TDATA,
S0_AXIS_TVALID => S0_AXIS_TVALID,
S0_AXIS_TREADY => S0_AXIS_TREADY,
M1_AXIS_TLAST => M1_AXIS_TLAST,
M1_AXIS_TDATA => M1_AXIS_TDATA,
M1_AXIS_TVALID => M1_AXIS_TVALID,
M1_AXIS_TREADY => M1_AXIS_TREADY,
S1_AXIS_TLAST => S1_AXIS_TLAST,
S1_AXIS_TDATA => S1_AXIS_TDATA,
S1_AXIS_TVALID => S1_AXIS_TVALID,
S1_AXIS_TREADY => S1_AXIS_TREADY,
M2_AXIS_TLAST => M2_AXIS_TLAST,
M2_AXIS_TDATA => M2_AXIS_TDATA,
M2_AXIS_TVALID => M2_AXIS_TVALID,
M2_AXIS_TREADY => M2_AXIS_TREADY,
S2_AXIS_TLAST => S2_AXIS_TLAST,
S2_AXIS_TDATA => S2_AXIS_TDATA,
S2_AXIS_TVALID => S2_AXIS_TVALID,
S2_AXIS_TREADY => S2_AXIS_TREADY,
M3_AXIS_TLAST => M3_AXIS_TLAST,
M3_AXIS_TDATA => M3_AXIS_TDATA,
M3_AXIS_TVALID => M3_AXIS_TVALID,
M3_AXIS_TREADY => M3_AXIS_TREADY,
S3_AXIS_TLAST => S3_AXIS_TLAST,
S3_AXIS_TDATA => S3_AXIS_TDATA,
S3_AXIS_TVALID => S3_AXIS_TVALID,
S3_AXIS_TREADY => S3_AXIS_TREADY,
M4_AXIS_TLAST => M4_AXIS_TLAST,
M4_AXIS_TDATA => M4_AXIS_TDATA,
M4_AXIS_TVALID => M4_AXIS_TVALID,
M4_AXIS_TREADY => M4_AXIS_TREADY,
S4_AXIS_TLAST => S4_AXIS_TLAST,
S4_AXIS_TDATA => S4_AXIS_TDATA,
S4_AXIS_TVALID => S4_AXIS_TVALID,
S4_AXIS_TREADY => S4_AXIS_TREADY,
M5_AXIS_TLAST => M5_AXIS_TLAST,
M5_AXIS_TDATA => M5_AXIS_TDATA,
M5_AXIS_TVALID => M5_AXIS_TVALID,
M5_AXIS_TREADY => M5_AXIS_TREADY,
S5_AXIS_TLAST => S5_AXIS_TLAST,
S5_AXIS_TDATA => S5_AXIS_TDATA,
S5_AXIS_TVALID => S5_AXIS_TVALID,
S5_AXIS_TREADY => S5_AXIS_TREADY,
M6_AXIS_TLAST => M6_AXIS_TLAST,
M6_AXIS_TDATA => M6_AXIS_TDATA,
M6_AXIS_TVALID => M6_AXIS_TVALID,
M6_AXIS_TREADY => M6_AXIS_TREADY,
S6_AXIS_TLAST => S6_AXIS_TLAST,
S6_AXIS_TDATA => S6_AXIS_TDATA,
S6_AXIS_TVALID => S6_AXIS_TVALID,
S6_AXIS_TREADY => S6_AXIS_TREADY,
M7_AXIS_TLAST => M7_AXIS_TLAST,
M7_AXIS_TDATA => M7_AXIS_TDATA,
M7_AXIS_TVALID => M7_AXIS_TVALID,
M7_AXIS_TREADY => M7_AXIS_TREADY,
S7_AXIS_TLAST => S7_AXIS_TLAST,
S7_AXIS_TDATA => S7_AXIS_TDATA,
S7_AXIS_TVALID => S7_AXIS_TVALID,
S7_AXIS_TREADY => S7_AXIS_TREADY,
M8_AXIS_TLAST => M8_AXIS_TLAST,
M8_AXIS_TDATA => M8_AXIS_TDATA,
M8_AXIS_TVALID => M8_AXIS_TVALID,
M8_AXIS_TREADY => M8_AXIS_TREADY,
S8_AXIS_TLAST => S8_AXIS_TLAST,
S8_AXIS_TDATA => S8_AXIS_TDATA,
S8_AXIS_TVALID => S8_AXIS_TVALID,
S8_AXIS_TREADY => S8_AXIS_TREADY,
M9_AXIS_TLAST => M9_AXIS_TLAST,
M9_AXIS_TDATA => M9_AXIS_TDATA,
M9_AXIS_TVALID => M9_AXIS_TVALID,
M9_AXIS_TREADY => M9_AXIS_TREADY,
S9_AXIS_TLAST => S9_AXIS_TLAST,
S9_AXIS_TDATA => S9_AXIS_TDATA,
S9_AXIS_TVALID => S9_AXIS_TVALID,
S9_AXIS_TREADY => S9_AXIS_TREADY,
M10_AXIS_TLAST => M10_AXIS_TLAST,
M10_AXIS_TDATA => M10_AXIS_TDATA,
M10_AXIS_TVALID => M10_AXIS_TVALID,
M10_AXIS_TREADY => M10_AXIS_TREADY,
S10_AXIS_TLAST => S10_AXIS_TLAST,
S10_AXIS_TDATA => S10_AXIS_TDATA,
S10_AXIS_TVALID => S10_AXIS_TVALID,
S10_AXIS_TREADY => S10_AXIS_TREADY,
M11_AXIS_TLAST => M11_AXIS_TLAST,
M11_AXIS_TDATA => M11_AXIS_TDATA,
M11_AXIS_TVALID => M11_AXIS_TVALID,
M11_AXIS_TREADY => M11_AXIS_TREADY,
S11_AXIS_TLAST => S11_AXIS_TLAST,
S11_AXIS_TDATA => S11_AXIS_TDATA,
S11_AXIS_TVALID => S11_AXIS_TVALID,
S11_AXIS_TREADY => S11_AXIS_TREADY,
M12_AXIS_TLAST => M12_AXIS_TLAST,
M12_AXIS_TDATA => M12_AXIS_TDATA,
M12_AXIS_TVALID => M12_AXIS_TVALID,
M12_AXIS_TREADY => M12_AXIS_TREADY,
S12_AXIS_TLAST => S12_AXIS_TLAST,
S12_AXIS_TDATA => S12_AXIS_TDATA,
S12_AXIS_TVALID => S12_AXIS_TVALID,
S12_AXIS_TREADY => S12_AXIS_TREADY,
M13_AXIS_TLAST => M13_AXIS_TLAST,
M13_AXIS_TDATA => M13_AXIS_TDATA,
M13_AXIS_TVALID => M13_AXIS_TVALID,
M13_AXIS_TREADY => M13_AXIS_TREADY,
S13_AXIS_TLAST => S13_AXIS_TLAST,
S13_AXIS_TDATA => S13_AXIS_TDATA,
S13_AXIS_TVALID => S13_AXIS_TVALID,
S13_AXIS_TREADY => S13_AXIS_TREADY,
M14_AXIS_TLAST => M14_AXIS_TLAST,
M14_AXIS_TDATA => M14_AXIS_TDATA,
M14_AXIS_TVALID => M14_AXIS_TVALID,
M14_AXIS_TREADY => M14_AXIS_TREADY,
S14_AXIS_TLAST => S14_AXIS_TLAST,
S14_AXIS_TDATA => S14_AXIS_TDATA,
S14_AXIS_TVALID => S14_AXIS_TVALID,
S14_AXIS_TREADY => S14_AXIS_TREADY,
M15_AXIS_TLAST => M15_AXIS_TLAST,
M15_AXIS_TDATA => M15_AXIS_TDATA,
M15_AXIS_TVALID => M15_AXIS_TVALID,
M15_AXIS_TREADY => M15_AXIS_TREADY,
S15_AXIS_TLAST => S15_AXIS_TLAST,
S15_AXIS_TDATA => S15_AXIS_TDATA,
S15_AXIS_TVALID => S15_AXIS_TVALID,
S15_AXIS_TREADY => S15_AXIS_TREADY,
ICACHE_FSL_IN_CLK => ICACHE_FSL_IN_CLK,
ICACHE_FSL_IN_READ => ICACHE_FSL_IN_READ,
ICACHE_FSL_IN_DATA => ICACHE_FSL_IN_DATA,
ICACHE_FSL_IN_CONTROL => ICACHE_FSL_IN_CONTROL,
ICACHE_FSL_IN_EXISTS => ICACHE_FSL_IN_EXISTS,
ICACHE_FSL_OUT_CLK => ICACHE_FSL_OUT_CLK,
ICACHE_FSL_OUT_WRITE => ICACHE_FSL_OUT_WRITE,
ICACHE_FSL_OUT_DATA => ICACHE_FSL_OUT_DATA,
ICACHE_FSL_OUT_CONTROL => ICACHE_FSL_OUT_CONTROL,
ICACHE_FSL_OUT_FULL => ICACHE_FSL_OUT_FULL,
DCACHE_FSL_IN_CLK => DCACHE_FSL_IN_CLK,
DCACHE_FSL_IN_READ => DCACHE_FSL_IN_READ,
DCACHE_FSL_IN_DATA => DCACHE_FSL_IN_DATA,
DCACHE_FSL_IN_CONTROL => DCACHE_FSL_IN_CONTROL,
DCACHE_FSL_IN_EXISTS => DCACHE_FSL_IN_EXISTS,
DCACHE_FSL_OUT_CLK => DCACHE_FSL_OUT_CLK,
DCACHE_FSL_OUT_WRITE => DCACHE_FSL_OUT_WRITE,
DCACHE_FSL_OUT_DATA => DCACHE_FSL_OUT_DATA,
DCACHE_FSL_OUT_CONTROL => DCACHE_FSL_OUT_CONTROL,
DCACHE_FSL_OUT_FULL => DCACHE_FSL_OUT_FULL
);
end architecture STRUCTURE;
| lgpl-3.0 | 06660cf34517eddf420df1862503101e | 0.606544 | 2.748177 | false | false | false | false |
TWW12/lzw | final_project/lzw_compression/lzw_compression.srcs/sources_1/bd/design_1/hdl/design_1.vhd | 1 | 58,855 | --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
--Date : Tue Apr 18 23:07:58 2017
--Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200)
--Command : generate_target design_1.bd
--Design : design_1
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_UYSKKA is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s00_couplers_imp_UYSKKA;
architecture STRUCTURE of s00_couplers_imp_UYSKKA is
component design_1_auto_pc_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component design_1_auto_pc_0;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC;
signal auto_pc_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= auto_pc_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= auto_pc_to_s00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= auto_pc_to_s00_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= auto_pc_to_s00_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_s00_couplers_BREADY;
M_AXI_rready <= auto_pc_to_s00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= auto_pc_to_s00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_pc_to_s00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1 <= S_ARESETN;
S_AXI_arready <= s00_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= s00_couplers_to_auto_pc_AWREADY;
S_AXI_bid(11 downto 0) <= s00_couplers_to_auto_pc_BID(11 downto 0);
S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= s00_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rid(11 downto 0) <= s00_couplers_to_auto_pc_RID(11 downto 0);
S_AXI_rlast <= s00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_auto_pc_RVALID;
S_AXI_wready <= s00_couplers_to_auto_pc_WREADY;
auto_pc_to_s00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_s00_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_s00_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_s00_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_s00_couplers_WREADY <= M_AXI_wready;
s00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_auto_pc_ARID(11 downto 0) <= S_AXI_arid(11 downto 0);
s00_couplers_to_auto_pc_ARLEN(3 downto 0) <= S_AXI_arlen(3 downto 0);
s00_couplers_to_auto_pc_ARLOCK(1 downto 0) <= S_AXI_arlock(1 downto 0);
s00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
s00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s00_couplers_to_auto_pc_AWID(11 downto 0) <= S_AXI_awid(11 downto 0);
s00_couplers_to_auto_pc_AWLEN(3 downto 0) <= S_AXI_awlen(3 downto 0);
s00_couplers_to_auto_pc_AWLOCK(1 downto 0) <= S_AXI_awlock(1 downto 0);
s00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
s00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
s00_couplers_to_auto_pc_BREADY <= S_AXI_bready;
s00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
s00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_auto_pc_WID(11 downto 0) <= S_AXI_wid(11 downto 0);
s00_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
s00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component design_1_auto_pc_0
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1,
m_axi_araddr(31 downto 0) => auto_pc_to_s00_couplers_ARADDR(31 downto 0),
m_axi_arprot(2 downto 0) => auto_pc_to_s00_couplers_ARPROT(2 downto 0),
m_axi_arready => auto_pc_to_s00_couplers_ARREADY,
m_axi_arvalid => auto_pc_to_s00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_s00_couplers_AWADDR(31 downto 0),
m_axi_awprot(2 downto 0) => auto_pc_to_s00_couplers_AWPROT(2 downto 0),
m_axi_awready => auto_pc_to_s00_couplers_AWREADY,
m_axi_awvalid => auto_pc_to_s00_couplers_AWVALID,
m_axi_bready => auto_pc_to_s00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_s00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_s00_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_s00_couplers_RDATA(31 downto 0),
m_axi_rready => auto_pc_to_s00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_s00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_s00_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_s00_couplers_WDATA(31 downto 0),
m_axi_wready => auto_pc_to_s00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_pc_to_s00_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_pc_to_s00_couplers_WVALID,
s_axi_araddr(31 downto 0) => s00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(11 downto 0) => s00_couplers_to_auto_pc_ARID(11 downto 0),
s_axi_arlen(3 downto 0) => s00_couplers_to_auto_pc_ARLEN(3 downto 0),
s_axi_arlock(1 downto 0) => s00_couplers_to_auto_pc_ARLOCK(1 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s00_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => s00_couplers_to_auto_pc_ARREADY,
s_axi_arsize(2 downto 0) => s00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => s00_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s00_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s00_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(11 downto 0) => s00_couplers_to_auto_pc_AWID(11 downto 0),
s_axi_awlen(3 downto 0) => s00_couplers_to_auto_pc_AWLEN(3 downto 0),
s_axi_awlock(1 downto 0) => s00_couplers_to_auto_pc_AWLOCK(1 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => s00_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => s00_couplers_to_auto_pc_AWREADY,
s_axi_awsize(2 downto 0) => s00_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => s00_couplers_to_auto_pc_AWVALID,
s_axi_bid(11 downto 0) => s00_couplers_to_auto_pc_BID(11 downto 0),
s_axi_bready => s00_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => s00_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => s00_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rid(11 downto 0) => s00_couplers_to_auto_pc_RID(11 downto 0),
s_axi_rlast => s00_couplers_to_auto_pc_RLAST,
s_axi_rready => s00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => s00_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => s00_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wid(11 downto 0) => s00_couplers_to_auto_pc_WID(11 downto 0),
s_axi_wlast => s00_couplers_to_auto_pc_WLAST,
s_axi_wready => s00_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => s00_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_ps7_0_axi_periph_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC;
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC;
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arready : in STD_LOGIC;
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awready : in STD_LOGIC;
M00_AXI_awvalid : out STD_LOGIC;
M00_AXI_bready : out STD_LOGIC;
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rready : out STD_LOGIC;
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC;
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wready : in STD_LOGIC;
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC;
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC
);
end design_1_ps7_0_axi_periph_0;
architecture STRUCTURE of design_1_ps7_0_axi_periph_0 is
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC;
signal ps7_0_axi_periph_ACLK_net : STD_LOGIC;
signal ps7_0_axi_periph_ARESETN_net : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_ARREADY : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_ARVALID : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_AWREADY : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_AWVALID : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_BREADY : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_BVALID : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_RLAST : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_RREADY : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_RVALID : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_WLAST : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_WREADY : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_ps7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_ps7_0_axi_periph_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_ps7_0_axi_periph_ARREADY : STD_LOGIC;
signal s00_couplers_to_ps7_0_axi_periph_ARVALID : STD_LOGIC;
signal s00_couplers_to_ps7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_ps7_0_axi_periph_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_ps7_0_axi_periph_AWREADY : STD_LOGIC;
signal s00_couplers_to_ps7_0_axi_periph_AWVALID : STD_LOGIC;
signal s00_couplers_to_ps7_0_axi_periph_BREADY : STD_LOGIC;
signal s00_couplers_to_ps7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_ps7_0_axi_periph_BVALID : STD_LOGIC;
signal s00_couplers_to_ps7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_ps7_0_axi_periph_RREADY : STD_LOGIC;
signal s00_couplers_to_ps7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_ps7_0_axi_periph_RVALID : STD_LOGIC;
signal s00_couplers_to_ps7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_ps7_0_axi_periph_WREADY : STD_LOGIC;
signal s00_couplers_to_ps7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_ps7_0_axi_periph_WVALID : STD_LOGIC;
begin
M00_AXI_araddr(31 downto 0) <= s00_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0);
M00_AXI_arprot(2 downto 0) <= s00_couplers_to_ps7_0_axi_periph_ARPROT(2 downto 0);
M00_AXI_arvalid <= s00_couplers_to_ps7_0_axi_periph_ARVALID;
M00_AXI_awaddr(31 downto 0) <= s00_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0);
M00_AXI_awprot(2 downto 0) <= s00_couplers_to_ps7_0_axi_periph_AWPROT(2 downto 0);
M00_AXI_awvalid <= s00_couplers_to_ps7_0_axi_periph_AWVALID;
M00_AXI_bready <= s00_couplers_to_ps7_0_axi_periph_BREADY;
M00_AXI_rready <= s00_couplers_to_ps7_0_axi_periph_RREADY;
M00_AXI_wdata(31 downto 0) <= s00_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0);
M00_AXI_wstrb(3 downto 0) <= s00_couplers_to_ps7_0_axi_periph_WSTRB(3 downto 0);
M00_AXI_wvalid <= s00_couplers_to_ps7_0_axi_periph_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1 <= S00_ARESETN;
S00_AXI_arready <= ps7_0_axi_periph_to_s00_couplers_ARREADY;
S00_AXI_awready <= ps7_0_axi_periph_to_s00_couplers_AWREADY;
S00_AXI_bid(11 downto 0) <= ps7_0_axi_periph_to_s00_couplers_BID(11 downto 0);
S00_AXI_bresp(1 downto 0) <= ps7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid <= ps7_0_axi_periph_to_s00_couplers_BVALID;
S00_AXI_rdata(31 downto 0) <= ps7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rid(11 downto 0) <= ps7_0_axi_periph_to_s00_couplers_RID(11 downto 0);
S00_AXI_rlast <= ps7_0_axi_periph_to_s00_couplers_RLAST;
S00_AXI_rresp(1 downto 0) <= ps7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= ps7_0_axi_periph_to_s00_couplers_RVALID;
S00_AXI_wready <= ps7_0_axi_periph_to_s00_couplers_WREADY;
ps7_0_axi_periph_ACLK_net <= M00_ACLK;
ps7_0_axi_periph_ARESETN_net <= M00_ARESETN;
ps7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
ps7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
ps7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
ps7_0_axi_periph_to_s00_couplers_ARID(11 downto 0) <= S00_AXI_arid(11 downto 0);
ps7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0);
ps7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0) <= S00_AXI_arlock(1 downto 0);
ps7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
ps7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0);
ps7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
ps7_0_axi_periph_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
ps7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
ps7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
ps7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
ps7_0_axi_periph_to_s00_couplers_AWID(11 downto 0) <= S00_AXI_awid(11 downto 0);
ps7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0);
ps7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0) <= S00_AXI_awlock(1 downto 0);
ps7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
ps7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0);
ps7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
ps7_0_axi_periph_to_s00_couplers_AWVALID <= S00_AXI_awvalid;
ps7_0_axi_periph_to_s00_couplers_BREADY <= S00_AXI_bready;
ps7_0_axi_periph_to_s00_couplers_RREADY <= S00_AXI_rready;
ps7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
ps7_0_axi_periph_to_s00_couplers_WID(11 downto 0) <= S00_AXI_wid(11 downto 0);
ps7_0_axi_periph_to_s00_couplers_WLAST <= S00_AXI_wlast;
ps7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
ps7_0_axi_periph_to_s00_couplers_WVALID <= S00_AXI_wvalid;
s00_couplers_to_ps7_0_axi_periph_ARREADY <= M00_AXI_arready;
s00_couplers_to_ps7_0_axi_periph_AWREADY <= M00_AXI_awready;
s00_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
s00_couplers_to_ps7_0_axi_periph_BVALID <= M00_AXI_bvalid;
s00_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
s00_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
s00_couplers_to_ps7_0_axi_periph_RVALID <= M00_AXI_rvalid;
s00_couplers_to_ps7_0_axi_periph_WREADY <= M00_AXI_wready;
s00_couplers: entity work.s00_couplers_imp_UYSKKA
port map (
M_ACLK => ps7_0_axi_periph_ACLK_net,
M_ARESETN => ps7_0_axi_periph_ARESETN_net,
M_AXI_araddr(31 downto 0) => s00_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_ps7_0_axi_periph_ARPROT(2 downto 0),
M_AXI_arready => s00_couplers_to_ps7_0_axi_periph_ARREADY,
M_AXI_arvalid => s00_couplers_to_ps7_0_axi_periph_ARVALID,
M_AXI_awaddr(31 downto 0) => s00_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => s00_couplers_to_ps7_0_axi_periph_AWPROT(2 downto 0),
M_AXI_awready => s00_couplers_to_ps7_0_axi_periph_AWREADY,
M_AXI_awvalid => s00_couplers_to_ps7_0_axi_periph_AWVALID,
M_AXI_bready => s00_couplers_to_ps7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => s00_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => s00_couplers_to_ps7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => s00_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => s00_couplers_to_ps7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_ps7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => s00_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => s00_couplers_to_ps7_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => s00_couplers_to_ps7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => s00_couplers_to_ps7_0_axi_periph_WVALID,
S_ACLK => S00_ACLK_1,
S_ARESETN => S00_ARESETN_1,
S_AXI_araddr(31 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(11 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARID(11 downto 0),
S_AXI_arlen(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0),
S_AXI_arlock(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0),
S_AXI_arprot(2 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0),
S_AXI_arready => ps7_0_axi_periph_to_s00_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => ps7_0_axi_periph_to_s00_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(11 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWID(11 downto 0),
S_AXI_awlen(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0),
S_AXI_awlock(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0),
S_AXI_awprot(2 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0),
S_AXI_awready => ps7_0_axi_periph_to_s00_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => ps7_0_axi_periph_to_s00_couplers_AWVALID,
S_AXI_bid(11 downto 0) => ps7_0_axi_periph_to_s00_couplers_BID(11 downto 0),
S_AXI_bready => ps7_0_axi_periph_to_s00_couplers_BREADY,
S_AXI_bresp(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => ps7_0_axi_periph_to_s00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => ps7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rid(11 downto 0) => ps7_0_axi_periph_to_s00_couplers_RID(11 downto 0),
S_AXI_rlast => ps7_0_axi_periph_to_s00_couplers_RLAST,
S_AXI_rready => ps7_0_axi_periph_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => ps7_0_axi_periph_to_s00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => ps7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wid(11 downto 0) => ps7_0_axi_periph_to_s00_couplers_WID(11 downto 0),
S_AXI_wlast => ps7_0_axi_periph_to_s00_couplers_WLAST,
S_AXI_wready => ps7_0_axi_periph_to_s00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => ps7_0_axi_periph_to_s00_couplers_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1 is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of design_1 : entity is "design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=6,numReposBlks=4,numNonXlnxBlks=0,numHierBlks=2,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_axi4_cnt=1,da_ps7_cnt=1,synth_mode=Global}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of design_1 : entity is "design_1.hwdef";
end design_1;
architecture STRUCTURE of design_1 is
component design_1_processing_system7_0_0 is
port (
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end component design_1_processing_system7_0_0;
component design_1_rst_ps7_0_100M_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component design_1_rst_ps7_0_100M_0;
component design_1_axi_compression_0_0 is
port (
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 5 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 5 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC
);
end component design_1_axi_compression_0_0;
signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_DDR_CAS_N : STD_LOGIC;
signal processing_system7_0_DDR_CKE : STD_LOGIC;
signal processing_system7_0_DDR_CK_N : STD_LOGIC;
signal processing_system7_0_DDR_CK_P : STD_LOGIC;
signal processing_system7_0_DDR_CS_N : STD_LOGIC;
signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_ODT : STD_LOGIC;
signal processing_system7_0_DDR_RAS_N : STD_LOGIC;
signal processing_system7_0_DDR_RESET_N : STD_LOGIC;
signal processing_system7_0_DDR_WE_N : STD_LOGIC;
signal processing_system7_0_FCLK_CLK0 : STD_LOGIC;
signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC;
signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_BREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_BVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_RLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_RVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_WLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_WVALID : STD_LOGIC;
signal ps7_0_axi_periph_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal ps7_0_axi_periph_M00_AXI_ARREADY : STD_LOGIC;
signal ps7_0_axi_periph_M00_AXI_ARVALID : STD_LOGIC;
signal ps7_0_axi_periph_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal ps7_0_axi_periph_M00_AXI_AWREADY : STD_LOGIC;
signal ps7_0_axi_periph_M00_AXI_AWVALID : STD_LOGIC;
signal ps7_0_axi_periph_M00_AXI_BREADY : STD_LOGIC;
signal ps7_0_axi_periph_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_M00_AXI_BVALID : STD_LOGIC;
signal ps7_0_axi_periph_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M00_AXI_RREADY : STD_LOGIC;
signal ps7_0_axi_periph_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_M00_AXI_RVALID : STD_LOGIC;
signal ps7_0_axi_periph_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M00_AXI_WREADY : STD_LOGIC;
signal ps7_0_axi_periph_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_M00_AXI_WVALID : STD_LOGIC;
signal rst_ps7_0_100M_interconnect_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_ps7_0_100M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_rst_ps7_0_100M_mb_reset_UNCONNECTED : STD_LOGIC;
signal NLW_rst_ps7_0_100M_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_rst_ps7_0_100M_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
begin
axi_compression_0: component design_1_axi_compression_0_0
port map (
s00_axi_aclk => processing_system7_0_FCLK_CLK0,
s00_axi_araddr(5 downto 0) => ps7_0_axi_periph_M00_AXI_ARADDR(5 downto 0),
s00_axi_aresetn => rst_ps7_0_100M_peripheral_aresetn(0),
s00_axi_arprot(2 downto 0) => ps7_0_axi_periph_M00_AXI_ARPROT(2 downto 0),
s00_axi_arready => ps7_0_axi_periph_M00_AXI_ARREADY,
s00_axi_arvalid => ps7_0_axi_periph_M00_AXI_ARVALID,
s00_axi_awaddr(5 downto 0) => ps7_0_axi_periph_M00_AXI_AWADDR(5 downto 0),
s00_axi_awprot(2 downto 0) => ps7_0_axi_periph_M00_AXI_AWPROT(2 downto 0),
s00_axi_awready => ps7_0_axi_periph_M00_AXI_AWREADY,
s00_axi_awvalid => ps7_0_axi_periph_M00_AXI_AWVALID,
s00_axi_bready => ps7_0_axi_periph_M00_AXI_BREADY,
s00_axi_bresp(1 downto 0) => ps7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
s00_axi_bvalid => ps7_0_axi_periph_M00_AXI_BVALID,
s00_axi_rdata(31 downto 0) => ps7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
s00_axi_rready => ps7_0_axi_periph_M00_AXI_RREADY,
s00_axi_rresp(1 downto 0) => ps7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
s00_axi_rvalid => ps7_0_axi_periph_M00_AXI_RVALID,
s00_axi_wdata(31 downto 0) => ps7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
s00_axi_wready => ps7_0_axi_periph_M00_AXI_WREADY,
s00_axi_wstrb(3 downto 0) => ps7_0_axi_periph_M00_AXI_WSTRB(3 downto 0),
s00_axi_wvalid => ps7_0_axi_periph_M00_AXI_WVALID
);
processing_system7_0: component design_1_processing_system7_0_0
port map (
DDR_Addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0),
DDR_CAS_n => DDR_cas_n,
DDR_CKE => DDR_cke,
DDR_CS_n => DDR_cs_n,
DDR_Clk => DDR_ck_p,
DDR_Clk_n => DDR_ck_n,
DDR_DM(3 downto 0) => DDR_dm(3 downto 0),
DDR_DQ(31 downto 0) => DDR_dq(31 downto 0),
DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_DRSTB => DDR_reset_n,
DDR_ODT => DDR_odt,
DDR_RAS_n => DDR_ras_n,
DDR_VRN => FIXED_IO_ddr_vrn,
DDR_VRP => FIXED_IO_ddr_vrp,
DDR_WEB => DDR_we_n,
FCLK_CLK0 => processing_system7_0_FCLK_CLK0,
FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
MIO(53 downto 0) => FIXED_IO_mio(53 downto 0),
M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0,
M_AXI_GP0_ARADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARID(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => processing_system7_0_M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => processing_system7_0_M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => processing_system7_0_M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => processing_system7_0_M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => processing_system7_0_M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => processing_system7_0_M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => processing_system7_0_M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => processing_system7_0_M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => processing_system7_0_M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => processing_system7_0_M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => processing_system7_0_M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => processing_system7_0_M_AXI_GP0_WVALID,
PS_CLK => FIXED_IO_ps_clk,
PS_PORB => FIXED_IO_ps_porb,
PS_SRSTB => FIXED_IO_ps_srstb,
TTC0_WAVE0_OUT => NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED,
TTC0_WAVE1_OUT => NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED,
TTC0_WAVE2_OUT => NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB0_VBUS_PWRFAULT => '0',
USB0_VBUS_PWRSELECT => NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED
);
ps7_0_axi_periph: entity work.design_1_ps7_0_axi_periph_0
port map (
ACLK => processing_system7_0_FCLK_CLK0,
ARESETN => rst_ps7_0_100M_interconnect_aresetn(0),
M00_ACLK => processing_system7_0_FCLK_CLK0,
M00_ARESETN => rst_ps7_0_100M_peripheral_aresetn(0),
M00_AXI_araddr(31 downto 0) => ps7_0_axi_periph_M00_AXI_ARADDR(31 downto 0),
M00_AXI_arprot(2 downto 0) => ps7_0_axi_periph_M00_AXI_ARPROT(2 downto 0),
M00_AXI_arready => ps7_0_axi_periph_M00_AXI_ARREADY,
M00_AXI_arvalid => ps7_0_axi_periph_M00_AXI_ARVALID,
M00_AXI_awaddr(31 downto 0) => ps7_0_axi_periph_M00_AXI_AWADDR(31 downto 0),
M00_AXI_awprot(2 downto 0) => ps7_0_axi_periph_M00_AXI_AWPROT(2 downto 0),
M00_AXI_awready => ps7_0_axi_periph_M00_AXI_AWREADY,
M00_AXI_awvalid => ps7_0_axi_periph_M00_AXI_AWVALID,
M00_AXI_bready => ps7_0_axi_periph_M00_AXI_BREADY,
M00_AXI_bresp(1 downto 0) => ps7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid => ps7_0_axi_periph_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => ps7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
M00_AXI_rready => ps7_0_axi_periph_M00_AXI_RREADY,
M00_AXI_rresp(1 downto 0) => ps7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid => ps7_0_axi_periph_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => ps7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
M00_AXI_wready => ps7_0_axi_periph_M00_AXI_WREADY,
M00_AXI_wstrb(3 downto 0) => ps7_0_axi_periph_M00_AXI_WSTRB(3 downto 0),
M00_AXI_wvalid => ps7_0_axi_periph_M00_AXI_WVALID,
S00_ACLK => processing_system7_0_FCLK_CLK0,
S00_ARESETN => rst_ps7_0_100M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
S00_AXI_arid(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
S00_AXI_arlen(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
S00_AXI_arlock(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
S00_AXI_arprot(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
S00_AXI_arqos(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
S00_AXI_arready => processing_system7_0_M_AXI_GP0_ARREADY,
S00_AXI_arsize(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
S00_AXI_arvalid => processing_system7_0_M_AXI_GP0_ARVALID,
S00_AXI_awaddr(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
S00_AXI_awburst(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
S00_AXI_awcache(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
S00_AXI_awid(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
S00_AXI_awlen(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
S00_AXI_awlock(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
S00_AXI_awprot(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
S00_AXI_awqos(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
S00_AXI_awready => processing_system7_0_M_AXI_GP0_AWREADY,
S00_AXI_awsize(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
S00_AXI_awvalid => processing_system7_0_M_AXI_GP0_AWVALID,
S00_AXI_bid(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
S00_AXI_bready => processing_system7_0_M_AXI_GP0_BREADY,
S00_AXI_bresp(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
S00_AXI_bvalid => processing_system7_0_M_AXI_GP0_BVALID,
S00_AXI_rdata(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
S00_AXI_rid(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
S00_AXI_rlast => processing_system7_0_M_AXI_GP0_RLAST,
S00_AXI_rready => processing_system7_0_M_AXI_GP0_RREADY,
S00_AXI_rresp(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
S00_AXI_rvalid => processing_system7_0_M_AXI_GP0_RVALID,
S00_AXI_wdata(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
S00_AXI_wid(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
S00_AXI_wlast => processing_system7_0_M_AXI_GP0_WLAST,
S00_AXI_wready => processing_system7_0_M_AXI_GP0_WREADY,
S00_AXI_wstrb(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
S00_AXI_wvalid => processing_system7_0_M_AXI_GP0_WVALID
);
rst_ps7_0_100M: component design_1_rst_ps7_0_100M_0
port map (
aux_reset_in => '1',
bus_struct_reset(0) => NLW_rst_ps7_0_100M_bus_struct_reset_UNCONNECTED(0),
dcm_locked => '1',
ext_reset_in => processing_system7_0_FCLK_RESET0_N,
interconnect_aresetn(0) => rst_ps7_0_100M_interconnect_aresetn(0),
mb_debug_sys_rst => '0',
mb_reset => NLW_rst_ps7_0_100M_mb_reset_UNCONNECTED,
peripheral_aresetn(0) => rst_ps7_0_100M_peripheral_aresetn(0),
peripheral_reset(0) => NLW_rst_ps7_0_100M_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => processing_system7_0_FCLK_CLK0
);
end STRUCTURE;
| unlicense | e471f0d1f1d3be5f64fd8a0df31ddd2c | 0.672738 | 2.721618 | false | false | false | false |
MrDoomBringer/DSD-Labs | Lab 7/BCD_to_sevenseg.vhd | 1 | 7,055 | -- BCD display for hex displays
-- (c) Cliff Chapman 2013
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_signed.ALL;
-- Seven segment display output
--
ENTITY sevenseg_bcd_display IS
port (
-- Input value to display
R : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-- Hex/Dec display select
S : IN STD_LOGIC;
-- sevenseg outputs
HEX0 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) := "1111111";
HEX1 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) := "1111111";
HEX2 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) := "1111111"
);
END sevenseg_bcd_display;
ARCHITECTURE display OF sevenseg_bcd_display IS
-- Hex output displays, customized for Altera DE2 board. May require
-- redefinition for different board setups.
CONSTANT hex_blk : STD_LOGIC_VECTOR (6 DOWNTO 0) := "1111111";
CONSTANT hex_neg : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0111111";
CONSTANT hex_zer : STD_LOGIC_VECTOR (6 DOWNTO 0) := "1000000";
CONSTANT hex_one : STD_LOGIC_VECTOR (6 DOWNTO 0) := "1111001";
CONSTANT hex_two : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0100100";
CONSTANT hex_thr : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0110000";
CONSTANT hex_fou : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0011001";
CONSTANT hex_fiv : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0010010";
CONSTANT hex_six : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0000010";
CONSTANT hex_sev : STD_LOGIC_VECTOR (6 DOWNTO 0) := "1111000";
CONSTANT hex_eig : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0000000";
CONSTANT hex_nin : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0011000";
CONSTANT hex_0xa : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0001000";
CONSTANT hex_0xb : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0000011";
CONSTANT hex_0xc : STD_LOGIC_VECTOR (6 DOWNTO 0) := "1000110";
CONSTANT hex_0xd : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0100001";
CONSTANT hex_0xe : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0000110";
CONSTANT hex_0xf : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0001110";
-- Internal buffer signals for display select
SIGNAL HEX0_buff_hex : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL HEX1_buff_hex : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL HEX2_buff_hex : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL HEX0_buff_dec : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL HEX1_buff_dec : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL HEX2_buff_dec : STD_LOGIC_VECTOR (6 DOWNTO 0);
BEGIN
-- Generate a hex display
display_hex : PROCESS (R)
ALIAS high_bit : STD_LOGIC_VECTOR (3 DOWNTO 0) IS R (7 DOWNTO 4);
ALIAS low_bit : STD_LOGIC_VECTOR (3 DOWNTO 0) IS R (3 DOWNTO 0);
BEGIN
CASE high_bit IS
WHEN "0000" => HEX1_buff_hex <= hex_zer;
WHEN "0001" => HEX1_buff_hex <= hex_one;
WHEN "0010" => HEX1_buff_hex <= hex_two;
WHEN "0011" => HEX1_buff_hex <= hex_thr;
WHEN "0100" => HEX1_buff_hex <= hex_fou;
WHEN "0101" => HEX1_buff_hex <= hex_fiv;
WHEN "0110" => HEX1_buff_hex <= hex_six;
WHEN "0111" => HEX1_buff_hex <= hex_sev;
WHEN "1000" => HEX1_buff_hex <= hex_eig;
WHEN "1001" => HEX1_buff_hex <= hex_nin;
WHEN "1010" => HEX1_buff_hex <= hex_0xa;
WHEN "1011" => HEX1_buff_hex <= hex_0xb;
WHEN "1100" => HEX1_buff_hex <= hex_0xc;
WHEN "1101" => HEX1_buff_hex <= hex_0xd;
WHEN "1110" => HEX1_buff_hex <= hex_0xe;
WHEN "1111" => HEX1_buff_hex <= hex_0xf;
WHEN OTHERS => HEX1_buff_hex <= hex_blk;
END CASE;
CASE low_bit IS
WHEN "0000" => HEX2_buff_hex <= hex_zer;
WHEN "0001" => HEX2_buff_hex <= hex_one;
WHEN "0010" => HEX2_buff_hex <= hex_two;
WHEN "0011" => HEX2_buff_hex <= hex_thr;
WHEN "0100" => HEX2_buff_hex <= hex_fou;
WHEN "0101" => HEX2_buff_hex <= hex_fiv;
WHEN "0110" => HEX2_buff_hex <= hex_six;
WHEN "0111" => HEX2_buff_hex <= hex_sev;
WHEN "1000" => HEX2_buff_hex <= hex_eig;
WHEN "1001" => HEX2_buff_hex <= hex_nin;
WHEN "1010" => HEX2_buff_hex <= hex_0xa;
WHEN "1011" => HEX2_buff_hex <= hex_0xb;
WHEN "1100" => HEX2_buff_hex <= hex_0xc;
WHEN "1101" => HEX2_buff_hex <= hex_0xd;
WHEN "1110" => HEX2_buff_hex <= hex_0xe;
WHEN "1111" => HEX2_buff_hex <= hex_0xf;
WHEN OTHERS => HEX2_buff_hex <= hex_blk;
END CASE;
END PROCESS display_hex;
-- Generate a decimal display
display_dec: PROCESS (R)
ALIAS sign_bit : STD_LOGIC IS R (7);
VARIABLE r_lower: STD_LOGIC_VECTOR (7 DOWNTO 0);
VARIABLE r_buff : STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
-- Select value to work off of
IF (sign_bit='1') THEN
HEX0_buff_dec <= hex_neg;
r_buff := (NOT(R) + "00000001");
ELSIF (sign_bit='0') THEN
HEX0_buff_dec <= hex_blk;
r_buff := R;
ELSE
HEX0_buff_dec <= hex_blk;
r_buff := "00000000";
END IF;
-- Display higher digit
IF (r_buff >= "00001010" AND r_buff < "00010100") THEN -- Within 10-19
HEX1_buff_dec <= hex_one;
r_lower := r_buff - "00001010";
ELSIF (r_buff >= "00010100" AND r_buff < "00011110") THEN -- Within 20-29
HEX1_buff_dec <= hex_two;
r_lower := r_buff - "00010100";
ELSIF (r_buff >= "00011110" AND r_buff < "00101000") THEN -- Within 30-39
HEX1_buff_dec <= hex_thr;
r_lower := r_buff - "00011110";
ELSIF (r_buff >= "00101000" AND r_buff < "00110010") THEN -- Within 40-49
HEX1_buff_dec <= hex_fou;
r_lower := r_buff - "00101000";
ELSIF (r_buff >= "00110010" AND r_buff < "00111100") THEN -- Within 50-59
HEX1_buff_dec <= hex_fiv;
r_lower := r_buff - "00110010";
ELSIF (r_buff >= "00111100" AND r_buff < "01000110") THEN -- Within 60-69
HEX1_buff_dec <= hex_six;
r_lower := r_buff - "00111100";
ELSIF (r_buff >= "01000110" AND r_buff < "01010000") THEN -- Within 70-79
HEX1_buff_dec <= hex_sev;
r_lower := r_buff - "01000110";
ELSIF (r_buff >= "01010000" AND r_buff < "01011010") THEN -- Within 80-89
HEX1_buff_dec <= hex_eig;
r_lower := r_buff - "01010000";
ELSIF (r_buff >= "01011010" AND r_buff < "01100100") THEN -- Within 90-99
HEX1_buff_dec <= hex_nin;
r_lower := r_buff - "01011010";
ELSE -- 99 is the highest value we can reliably display.
HEX1_buff_dec <= hex_zer;
r_lower := r_buff;
END IF;
-- Display lower digit
CASE r_lower IS
WHEN "00000000" => HEX2_buff_dec <= hex_zer;
WHEN "00000001" => HEX2_buff_dec <= hex_one;
WHEN "00000010" => HEX2_buff_dec <= hex_two;
WHEN "00000011" => HEX2_buff_dec <= hex_thr;
WHEN "00000100" => HEX2_buff_dec <= hex_fou;
WHEN "00000101" => HEX2_buff_dec <= hex_fiv;
WHEN "00000110" => HEX2_buff_dec <= hex_six;
WHEN "00000111" => HEX2_buff_dec <= hex_sev;
WHEN "00001000" => HEX2_buff_dec <= hex_eig;
WHEN "00001001" => HEX2_buff_dec <= hex_nin;
WHEN OTHERS => HEX2_buff_dec <= hex_zer;
END CASE;
END PROCESS display_dec;
-- Select display type for output
select_display : PROCESS (S, HEX0_buff_hex, HEX1_buff_hex, HEX2_buff_hex, HEX0_buff_dec, HEX1_buff_dec, HEX2_buff_dec)
BEGIN
IF (s = '0') THEN
HEX2 <= hex_blk;
HEX1 <= HEX1_buff_hex;
HEX0 <= HEX2_buff_hex;
ELSIF (s = '1') THEN
HEX2 <= HEX0_buff_dec;
HEX1 <= HEX1_buff_dec;
HEX0 <= HEX2_buff_dec;
ELSE
HEX2 <= hex_blk;
HEX1 <= hex_blk;
HEX0 <= hex_blk;
END IF;
END PROCESS select_display;
END display; | mit | 672455694af73c85e8c47dc6dccbc046 | 0.626364 | 2.700995 | false | false | false | false |
jairov4/accel-oil | impl/impl_test_single/hdl/system_mdm_0_wrapper.vhd | 1 | 39,103 | -------------------------------------------------------------------------------
-- system_mdm_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library mdm_v2_10_a;
use mdm_v2_10_a.all;
entity system_mdm_0_wrapper is
port (
Interrupt : out std_logic;
Debug_SYS_Rst : out std_logic;
Ext_BRK : out std_logic;
Ext_NM_BRK : out std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 2);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 7);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 63);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 63);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 6);
Sl_MWrErr : out std_logic_vector(0 to 6);
Sl_MRdErr : out std_logic_vector(0 to 6);
Sl_MIRQ : out std_logic_vector(0 to 6);
Dbg_Clk_0 : out std_logic;
Dbg_TDI_0 : out std_logic;
Dbg_TDO_0 : in std_logic;
Dbg_Reg_En_0 : out std_logic_vector(0 to 7);
Dbg_Capture_0 : out std_logic;
Dbg_Shift_0 : out std_logic;
Dbg_Update_0 : out std_logic;
Dbg_Rst_0 : out std_logic;
Dbg_Clk_1 : out std_logic;
Dbg_TDI_1 : out std_logic;
Dbg_TDO_1 : in std_logic;
Dbg_Reg_En_1 : out std_logic_vector(0 to 7);
Dbg_Capture_1 : out std_logic;
Dbg_Shift_1 : out std_logic;
Dbg_Update_1 : out std_logic;
Dbg_Rst_1 : out std_logic;
Dbg_Clk_2 : out std_logic;
Dbg_TDI_2 : out std_logic;
Dbg_TDO_2 : in std_logic;
Dbg_Reg_En_2 : out std_logic_vector(0 to 7);
Dbg_Capture_2 : out std_logic;
Dbg_Shift_2 : out std_logic;
Dbg_Update_2 : out std_logic;
Dbg_Rst_2 : out std_logic;
Dbg_Clk_3 : out std_logic;
Dbg_TDI_3 : out std_logic;
Dbg_TDO_3 : in std_logic;
Dbg_Reg_En_3 : out std_logic_vector(0 to 7);
Dbg_Capture_3 : out std_logic;
Dbg_Shift_3 : out std_logic;
Dbg_Update_3 : out std_logic;
Dbg_Rst_3 : out std_logic;
Dbg_Clk_4 : out std_logic;
Dbg_TDI_4 : out std_logic;
Dbg_TDO_4 : in std_logic;
Dbg_Reg_En_4 : out std_logic_vector(0 to 7);
Dbg_Capture_4 : out std_logic;
Dbg_Shift_4 : out std_logic;
Dbg_Update_4 : out std_logic;
Dbg_Rst_4 : out std_logic;
Dbg_Clk_5 : out std_logic;
Dbg_TDI_5 : out std_logic;
Dbg_TDO_5 : in std_logic;
Dbg_Reg_En_5 : out std_logic_vector(0 to 7);
Dbg_Capture_5 : out std_logic;
Dbg_Shift_5 : out std_logic;
Dbg_Update_5 : out std_logic;
Dbg_Rst_5 : out std_logic;
Dbg_Clk_6 : out std_logic;
Dbg_TDI_6 : out std_logic;
Dbg_TDO_6 : in std_logic;
Dbg_Reg_En_6 : out std_logic_vector(0 to 7);
Dbg_Capture_6 : out std_logic;
Dbg_Shift_6 : out std_logic;
Dbg_Update_6 : out std_logic;
Dbg_Rst_6 : out std_logic;
Dbg_Clk_7 : out std_logic;
Dbg_TDI_7 : out std_logic;
Dbg_TDO_7 : in std_logic;
Dbg_Reg_En_7 : out std_logic_vector(0 to 7);
Dbg_Capture_7 : out std_logic;
Dbg_Shift_7 : out std_logic;
Dbg_Update_7 : out std_logic;
Dbg_Rst_7 : out std_logic;
Dbg_Clk_8 : out std_logic;
Dbg_TDI_8 : out std_logic;
Dbg_TDO_8 : in std_logic;
Dbg_Reg_En_8 : out std_logic_vector(0 to 7);
Dbg_Capture_8 : out std_logic;
Dbg_Shift_8 : out std_logic;
Dbg_Update_8 : out std_logic;
Dbg_Rst_8 : out std_logic;
Dbg_Clk_9 : out std_logic;
Dbg_TDI_9 : out std_logic;
Dbg_TDO_9 : in std_logic;
Dbg_Reg_En_9 : out std_logic_vector(0 to 7);
Dbg_Capture_9 : out std_logic;
Dbg_Shift_9 : out std_logic;
Dbg_Update_9 : out std_logic;
Dbg_Rst_9 : out std_logic;
Dbg_Clk_10 : out std_logic;
Dbg_TDI_10 : out std_logic;
Dbg_TDO_10 : in std_logic;
Dbg_Reg_En_10 : out std_logic_vector(0 to 7);
Dbg_Capture_10 : out std_logic;
Dbg_Shift_10 : out std_logic;
Dbg_Update_10 : out std_logic;
Dbg_Rst_10 : out std_logic;
Dbg_Clk_11 : out std_logic;
Dbg_TDI_11 : out std_logic;
Dbg_TDO_11 : in std_logic;
Dbg_Reg_En_11 : out std_logic_vector(0 to 7);
Dbg_Capture_11 : out std_logic;
Dbg_Shift_11 : out std_logic;
Dbg_Update_11 : out std_logic;
Dbg_Rst_11 : out std_logic;
Dbg_Clk_12 : out std_logic;
Dbg_TDI_12 : out std_logic;
Dbg_TDO_12 : in std_logic;
Dbg_Reg_En_12 : out std_logic_vector(0 to 7);
Dbg_Capture_12 : out std_logic;
Dbg_Shift_12 : out std_logic;
Dbg_Update_12 : out std_logic;
Dbg_Rst_12 : out std_logic;
Dbg_Clk_13 : out std_logic;
Dbg_TDI_13 : out std_logic;
Dbg_TDO_13 : in std_logic;
Dbg_Reg_En_13 : out std_logic_vector(0 to 7);
Dbg_Capture_13 : out std_logic;
Dbg_Shift_13 : out std_logic;
Dbg_Update_13 : out std_logic;
Dbg_Rst_13 : out std_logic;
Dbg_Clk_14 : out std_logic;
Dbg_TDI_14 : out std_logic;
Dbg_TDO_14 : in std_logic;
Dbg_Reg_En_14 : out std_logic_vector(0 to 7);
Dbg_Capture_14 : out std_logic;
Dbg_Shift_14 : out std_logic;
Dbg_Update_14 : out std_logic;
Dbg_Rst_14 : out std_logic;
Dbg_Clk_15 : out std_logic;
Dbg_TDI_15 : out std_logic;
Dbg_TDO_15 : in std_logic;
Dbg_Reg_En_15 : out std_logic_vector(0 to 7);
Dbg_Capture_15 : out std_logic;
Dbg_Shift_15 : out std_logic;
Dbg_Update_15 : out std_logic;
Dbg_Rst_15 : out std_logic;
Dbg_Clk_16 : out std_logic;
Dbg_TDI_16 : out std_logic;
Dbg_TDO_16 : in std_logic;
Dbg_Reg_En_16 : out std_logic_vector(0 to 7);
Dbg_Capture_16 : out std_logic;
Dbg_Shift_16 : out std_logic;
Dbg_Update_16 : out std_logic;
Dbg_Rst_16 : out std_logic;
Dbg_Clk_17 : out std_logic;
Dbg_TDI_17 : out std_logic;
Dbg_TDO_17 : in std_logic;
Dbg_Reg_En_17 : out std_logic_vector(0 to 7);
Dbg_Capture_17 : out std_logic;
Dbg_Shift_17 : out std_logic;
Dbg_Update_17 : out std_logic;
Dbg_Rst_17 : out std_logic;
Dbg_Clk_18 : out std_logic;
Dbg_TDI_18 : out std_logic;
Dbg_TDO_18 : in std_logic;
Dbg_Reg_En_18 : out std_logic_vector(0 to 7);
Dbg_Capture_18 : out std_logic;
Dbg_Shift_18 : out std_logic;
Dbg_Update_18 : out std_logic;
Dbg_Rst_18 : out std_logic;
Dbg_Clk_19 : out std_logic;
Dbg_TDI_19 : out std_logic;
Dbg_TDO_19 : in std_logic;
Dbg_Reg_En_19 : out std_logic_vector(0 to 7);
Dbg_Capture_19 : out std_logic;
Dbg_Shift_19 : out std_logic;
Dbg_Update_19 : out std_logic;
Dbg_Rst_19 : out std_logic;
Dbg_Clk_20 : out std_logic;
Dbg_TDI_20 : out std_logic;
Dbg_TDO_20 : in std_logic;
Dbg_Reg_En_20 : out std_logic_vector(0 to 7);
Dbg_Capture_20 : out std_logic;
Dbg_Shift_20 : out std_logic;
Dbg_Update_20 : out std_logic;
Dbg_Rst_20 : out std_logic;
Dbg_Clk_21 : out std_logic;
Dbg_TDI_21 : out std_logic;
Dbg_TDO_21 : in std_logic;
Dbg_Reg_En_21 : out std_logic_vector(0 to 7);
Dbg_Capture_21 : out std_logic;
Dbg_Shift_21 : out std_logic;
Dbg_Update_21 : out std_logic;
Dbg_Rst_21 : out std_logic;
Dbg_Clk_22 : out std_logic;
Dbg_TDI_22 : out std_logic;
Dbg_TDO_22 : in std_logic;
Dbg_Reg_En_22 : out std_logic_vector(0 to 7);
Dbg_Capture_22 : out std_logic;
Dbg_Shift_22 : out std_logic;
Dbg_Update_22 : out std_logic;
Dbg_Rst_22 : out std_logic;
Dbg_Clk_23 : out std_logic;
Dbg_TDI_23 : out std_logic;
Dbg_TDO_23 : in std_logic;
Dbg_Reg_En_23 : out std_logic_vector(0 to 7);
Dbg_Capture_23 : out std_logic;
Dbg_Shift_23 : out std_logic;
Dbg_Update_23 : out std_logic;
Dbg_Rst_23 : out std_logic;
Dbg_Clk_24 : out std_logic;
Dbg_TDI_24 : out std_logic;
Dbg_TDO_24 : in std_logic;
Dbg_Reg_En_24 : out std_logic_vector(0 to 7);
Dbg_Capture_24 : out std_logic;
Dbg_Shift_24 : out std_logic;
Dbg_Update_24 : out std_logic;
Dbg_Rst_24 : out std_logic;
Dbg_Clk_25 : out std_logic;
Dbg_TDI_25 : out std_logic;
Dbg_TDO_25 : in std_logic;
Dbg_Reg_En_25 : out std_logic_vector(0 to 7);
Dbg_Capture_25 : out std_logic;
Dbg_Shift_25 : out std_logic;
Dbg_Update_25 : out std_logic;
Dbg_Rst_25 : out std_logic;
Dbg_Clk_26 : out std_logic;
Dbg_TDI_26 : out std_logic;
Dbg_TDO_26 : in std_logic;
Dbg_Reg_En_26 : out std_logic_vector(0 to 7);
Dbg_Capture_26 : out std_logic;
Dbg_Shift_26 : out std_logic;
Dbg_Update_26 : out std_logic;
Dbg_Rst_26 : out std_logic;
Dbg_Clk_27 : out std_logic;
Dbg_TDI_27 : out std_logic;
Dbg_TDO_27 : in std_logic;
Dbg_Reg_En_27 : out std_logic_vector(0 to 7);
Dbg_Capture_27 : out std_logic;
Dbg_Shift_27 : out std_logic;
Dbg_Update_27 : out std_logic;
Dbg_Rst_27 : out std_logic;
Dbg_Clk_28 : out std_logic;
Dbg_TDI_28 : out std_logic;
Dbg_TDO_28 : in std_logic;
Dbg_Reg_En_28 : out std_logic_vector(0 to 7);
Dbg_Capture_28 : out std_logic;
Dbg_Shift_28 : out std_logic;
Dbg_Update_28 : out std_logic;
Dbg_Rst_28 : out std_logic;
Dbg_Clk_29 : out std_logic;
Dbg_TDI_29 : out std_logic;
Dbg_TDO_29 : in std_logic;
Dbg_Reg_En_29 : out std_logic_vector(0 to 7);
Dbg_Capture_29 : out std_logic;
Dbg_Shift_29 : out std_logic;
Dbg_Update_29 : out std_logic;
Dbg_Rst_29 : out std_logic;
Dbg_Clk_30 : out std_logic;
Dbg_TDI_30 : out std_logic;
Dbg_TDO_30 : in std_logic;
Dbg_Reg_En_30 : out std_logic_vector(0 to 7);
Dbg_Capture_30 : out std_logic;
Dbg_Shift_30 : out std_logic;
Dbg_Update_30 : out std_logic;
Dbg_Rst_30 : out std_logic;
Dbg_Clk_31 : out std_logic;
Dbg_TDI_31 : out std_logic;
Dbg_TDO_31 : in std_logic;
Dbg_Reg_En_31 : out std_logic_vector(0 to 7);
Dbg_Capture_31 : out std_logic;
Dbg_Shift_31 : out std_logic;
Dbg_Update_31 : out std_logic;
Dbg_Rst_31 : out std_logic;
bscan_tdi : out std_logic;
bscan_reset : out std_logic;
bscan_shift : out std_logic;
bscan_update : out std_logic;
bscan_capture : out std_logic;
bscan_sel1 : out std_logic;
bscan_drck1 : out std_logic;
bscan_tdo1 : in std_logic;
bscan_ext_tdi : in std_logic;
bscan_ext_reset : in std_logic;
bscan_ext_shift : in std_logic;
bscan_ext_update : in std_logic;
bscan_ext_capture : in std_logic;
bscan_ext_sel : in std_logic;
bscan_ext_drck : in std_logic;
bscan_ext_tdo : out std_logic;
Ext_JTAG_DRCK : out std_logic;
Ext_JTAG_RESET : out std_logic;
Ext_JTAG_SEL : out std_logic;
Ext_JTAG_CAPTURE : out std_logic;
Ext_JTAG_SHIFT : out std_logic;
Ext_JTAG_UPDATE : out std_logic;
Ext_JTAG_TDI : out std_logic;
Ext_JTAG_TDO : in std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of system_mdm_0_wrapper : entity is "mdm_v2_10_a";
end system_mdm_0_wrapper;
architecture STRUCTURE of system_mdm_0_wrapper is
component mdm is
generic (
C_FAMILY : STRING;
C_JTAG_CHAIN : INTEGER;
C_INTERCONNECT : INTEGER;
C_BASEADDR : STD_LOGIC_VECTOR;
C_HIGHADDR : STD_LOGIC_VECTOR;
C_SPLB_AWIDTH : INTEGER;
C_SPLB_DWIDTH : INTEGER;
C_SPLB_P2P : INTEGER;
C_SPLB_MID_WIDTH : INTEGER;
C_SPLB_NUM_MASTERS : INTEGER;
C_SPLB_NATIVE_DWIDTH : INTEGER;
C_SPLB_SUPPORT_BURSTS : INTEGER;
C_MB_DBG_PORTS : INTEGER;
C_USE_UART : INTEGER;
C_USE_BSCAN : integer;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER
);
port (
Interrupt : out std_logic;
Debug_SYS_Rst : out std_logic;
Ext_BRK : out std_logic;
Ext_NM_BRK : out std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8-1) downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1));
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1));
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1));
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1));
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Dbg_Clk_0 : out std_logic;
Dbg_TDI_0 : out std_logic;
Dbg_TDO_0 : in std_logic;
Dbg_Reg_En_0 : out std_logic_vector(0 to 7);
Dbg_Capture_0 : out std_logic;
Dbg_Shift_0 : out std_logic;
Dbg_Update_0 : out std_logic;
Dbg_Rst_0 : out std_logic;
Dbg_Clk_1 : out std_logic;
Dbg_TDI_1 : out std_logic;
Dbg_TDO_1 : in std_logic;
Dbg_Reg_En_1 : out std_logic_vector(0 to 7);
Dbg_Capture_1 : out std_logic;
Dbg_Shift_1 : out std_logic;
Dbg_Update_1 : out std_logic;
Dbg_Rst_1 : out std_logic;
Dbg_Clk_2 : out std_logic;
Dbg_TDI_2 : out std_logic;
Dbg_TDO_2 : in std_logic;
Dbg_Reg_En_2 : out std_logic_vector(0 to 7);
Dbg_Capture_2 : out std_logic;
Dbg_Shift_2 : out std_logic;
Dbg_Update_2 : out std_logic;
Dbg_Rst_2 : out std_logic;
Dbg_Clk_3 : out std_logic;
Dbg_TDI_3 : out std_logic;
Dbg_TDO_3 : in std_logic;
Dbg_Reg_En_3 : out std_logic_vector(0 to 7);
Dbg_Capture_3 : out std_logic;
Dbg_Shift_3 : out std_logic;
Dbg_Update_3 : out std_logic;
Dbg_Rst_3 : out std_logic;
Dbg_Clk_4 : out std_logic;
Dbg_TDI_4 : out std_logic;
Dbg_TDO_4 : in std_logic;
Dbg_Reg_En_4 : out std_logic_vector(0 to 7);
Dbg_Capture_4 : out std_logic;
Dbg_Shift_4 : out std_logic;
Dbg_Update_4 : out std_logic;
Dbg_Rst_4 : out std_logic;
Dbg_Clk_5 : out std_logic;
Dbg_TDI_5 : out std_logic;
Dbg_TDO_5 : in std_logic;
Dbg_Reg_En_5 : out std_logic_vector(0 to 7);
Dbg_Capture_5 : out std_logic;
Dbg_Shift_5 : out std_logic;
Dbg_Update_5 : out std_logic;
Dbg_Rst_5 : out std_logic;
Dbg_Clk_6 : out std_logic;
Dbg_TDI_6 : out std_logic;
Dbg_TDO_6 : in std_logic;
Dbg_Reg_En_6 : out std_logic_vector(0 to 7);
Dbg_Capture_6 : out std_logic;
Dbg_Shift_6 : out std_logic;
Dbg_Update_6 : out std_logic;
Dbg_Rst_6 : out std_logic;
Dbg_Clk_7 : out std_logic;
Dbg_TDI_7 : out std_logic;
Dbg_TDO_7 : in std_logic;
Dbg_Reg_En_7 : out std_logic_vector(0 to 7);
Dbg_Capture_7 : out std_logic;
Dbg_Shift_7 : out std_logic;
Dbg_Update_7 : out std_logic;
Dbg_Rst_7 : out std_logic;
Dbg_Clk_8 : out std_logic;
Dbg_TDI_8 : out std_logic;
Dbg_TDO_8 : in std_logic;
Dbg_Reg_En_8 : out std_logic_vector(0 to 7);
Dbg_Capture_8 : out std_logic;
Dbg_Shift_8 : out std_logic;
Dbg_Update_8 : out std_logic;
Dbg_Rst_8 : out std_logic;
Dbg_Clk_9 : out std_logic;
Dbg_TDI_9 : out std_logic;
Dbg_TDO_9 : in std_logic;
Dbg_Reg_En_9 : out std_logic_vector(0 to 7);
Dbg_Capture_9 : out std_logic;
Dbg_Shift_9 : out std_logic;
Dbg_Update_9 : out std_logic;
Dbg_Rst_9 : out std_logic;
Dbg_Clk_10 : out std_logic;
Dbg_TDI_10 : out std_logic;
Dbg_TDO_10 : in std_logic;
Dbg_Reg_En_10 : out std_logic_vector(0 to 7);
Dbg_Capture_10 : out std_logic;
Dbg_Shift_10 : out std_logic;
Dbg_Update_10 : out std_logic;
Dbg_Rst_10 : out std_logic;
Dbg_Clk_11 : out std_logic;
Dbg_TDI_11 : out std_logic;
Dbg_TDO_11 : in std_logic;
Dbg_Reg_En_11 : out std_logic_vector(0 to 7);
Dbg_Capture_11 : out std_logic;
Dbg_Shift_11 : out std_logic;
Dbg_Update_11 : out std_logic;
Dbg_Rst_11 : out std_logic;
Dbg_Clk_12 : out std_logic;
Dbg_TDI_12 : out std_logic;
Dbg_TDO_12 : in std_logic;
Dbg_Reg_En_12 : out std_logic_vector(0 to 7);
Dbg_Capture_12 : out std_logic;
Dbg_Shift_12 : out std_logic;
Dbg_Update_12 : out std_logic;
Dbg_Rst_12 : out std_logic;
Dbg_Clk_13 : out std_logic;
Dbg_TDI_13 : out std_logic;
Dbg_TDO_13 : in std_logic;
Dbg_Reg_En_13 : out std_logic_vector(0 to 7);
Dbg_Capture_13 : out std_logic;
Dbg_Shift_13 : out std_logic;
Dbg_Update_13 : out std_logic;
Dbg_Rst_13 : out std_logic;
Dbg_Clk_14 : out std_logic;
Dbg_TDI_14 : out std_logic;
Dbg_TDO_14 : in std_logic;
Dbg_Reg_En_14 : out std_logic_vector(0 to 7);
Dbg_Capture_14 : out std_logic;
Dbg_Shift_14 : out std_logic;
Dbg_Update_14 : out std_logic;
Dbg_Rst_14 : out std_logic;
Dbg_Clk_15 : out std_logic;
Dbg_TDI_15 : out std_logic;
Dbg_TDO_15 : in std_logic;
Dbg_Reg_En_15 : out std_logic_vector(0 to 7);
Dbg_Capture_15 : out std_logic;
Dbg_Shift_15 : out std_logic;
Dbg_Update_15 : out std_logic;
Dbg_Rst_15 : out std_logic;
Dbg_Clk_16 : out std_logic;
Dbg_TDI_16 : out std_logic;
Dbg_TDO_16 : in std_logic;
Dbg_Reg_En_16 : out std_logic_vector(0 to 7);
Dbg_Capture_16 : out std_logic;
Dbg_Shift_16 : out std_logic;
Dbg_Update_16 : out std_logic;
Dbg_Rst_16 : out std_logic;
Dbg_Clk_17 : out std_logic;
Dbg_TDI_17 : out std_logic;
Dbg_TDO_17 : in std_logic;
Dbg_Reg_En_17 : out std_logic_vector(0 to 7);
Dbg_Capture_17 : out std_logic;
Dbg_Shift_17 : out std_logic;
Dbg_Update_17 : out std_logic;
Dbg_Rst_17 : out std_logic;
Dbg_Clk_18 : out std_logic;
Dbg_TDI_18 : out std_logic;
Dbg_TDO_18 : in std_logic;
Dbg_Reg_En_18 : out std_logic_vector(0 to 7);
Dbg_Capture_18 : out std_logic;
Dbg_Shift_18 : out std_logic;
Dbg_Update_18 : out std_logic;
Dbg_Rst_18 : out std_logic;
Dbg_Clk_19 : out std_logic;
Dbg_TDI_19 : out std_logic;
Dbg_TDO_19 : in std_logic;
Dbg_Reg_En_19 : out std_logic_vector(0 to 7);
Dbg_Capture_19 : out std_logic;
Dbg_Shift_19 : out std_logic;
Dbg_Update_19 : out std_logic;
Dbg_Rst_19 : out std_logic;
Dbg_Clk_20 : out std_logic;
Dbg_TDI_20 : out std_logic;
Dbg_TDO_20 : in std_logic;
Dbg_Reg_En_20 : out std_logic_vector(0 to 7);
Dbg_Capture_20 : out std_logic;
Dbg_Shift_20 : out std_logic;
Dbg_Update_20 : out std_logic;
Dbg_Rst_20 : out std_logic;
Dbg_Clk_21 : out std_logic;
Dbg_TDI_21 : out std_logic;
Dbg_TDO_21 : in std_logic;
Dbg_Reg_En_21 : out std_logic_vector(0 to 7);
Dbg_Capture_21 : out std_logic;
Dbg_Shift_21 : out std_logic;
Dbg_Update_21 : out std_logic;
Dbg_Rst_21 : out std_logic;
Dbg_Clk_22 : out std_logic;
Dbg_TDI_22 : out std_logic;
Dbg_TDO_22 : in std_logic;
Dbg_Reg_En_22 : out std_logic_vector(0 to 7);
Dbg_Capture_22 : out std_logic;
Dbg_Shift_22 : out std_logic;
Dbg_Update_22 : out std_logic;
Dbg_Rst_22 : out std_logic;
Dbg_Clk_23 : out std_logic;
Dbg_TDI_23 : out std_logic;
Dbg_TDO_23 : in std_logic;
Dbg_Reg_En_23 : out std_logic_vector(0 to 7);
Dbg_Capture_23 : out std_logic;
Dbg_Shift_23 : out std_logic;
Dbg_Update_23 : out std_logic;
Dbg_Rst_23 : out std_logic;
Dbg_Clk_24 : out std_logic;
Dbg_TDI_24 : out std_logic;
Dbg_TDO_24 : in std_logic;
Dbg_Reg_En_24 : out std_logic_vector(0 to 7);
Dbg_Capture_24 : out std_logic;
Dbg_Shift_24 : out std_logic;
Dbg_Update_24 : out std_logic;
Dbg_Rst_24 : out std_logic;
Dbg_Clk_25 : out std_logic;
Dbg_TDI_25 : out std_logic;
Dbg_TDO_25 : in std_logic;
Dbg_Reg_En_25 : out std_logic_vector(0 to 7);
Dbg_Capture_25 : out std_logic;
Dbg_Shift_25 : out std_logic;
Dbg_Update_25 : out std_logic;
Dbg_Rst_25 : out std_logic;
Dbg_Clk_26 : out std_logic;
Dbg_TDI_26 : out std_logic;
Dbg_TDO_26 : in std_logic;
Dbg_Reg_En_26 : out std_logic_vector(0 to 7);
Dbg_Capture_26 : out std_logic;
Dbg_Shift_26 : out std_logic;
Dbg_Update_26 : out std_logic;
Dbg_Rst_26 : out std_logic;
Dbg_Clk_27 : out std_logic;
Dbg_TDI_27 : out std_logic;
Dbg_TDO_27 : in std_logic;
Dbg_Reg_En_27 : out std_logic_vector(0 to 7);
Dbg_Capture_27 : out std_logic;
Dbg_Shift_27 : out std_logic;
Dbg_Update_27 : out std_logic;
Dbg_Rst_27 : out std_logic;
Dbg_Clk_28 : out std_logic;
Dbg_TDI_28 : out std_logic;
Dbg_TDO_28 : in std_logic;
Dbg_Reg_En_28 : out std_logic_vector(0 to 7);
Dbg_Capture_28 : out std_logic;
Dbg_Shift_28 : out std_logic;
Dbg_Update_28 : out std_logic;
Dbg_Rst_28 : out std_logic;
Dbg_Clk_29 : out std_logic;
Dbg_TDI_29 : out std_logic;
Dbg_TDO_29 : in std_logic;
Dbg_Reg_En_29 : out std_logic_vector(0 to 7);
Dbg_Capture_29 : out std_logic;
Dbg_Shift_29 : out std_logic;
Dbg_Update_29 : out std_logic;
Dbg_Rst_29 : out std_logic;
Dbg_Clk_30 : out std_logic;
Dbg_TDI_30 : out std_logic;
Dbg_TDO_30 : in std_logic;
Dbg_Reg_En_30 : out std_logic_vector(0 to 7);
Dbg_Capture_30 : out std_logic;
Dbg_Shift_30 : out std_logic;
Dbg_Update_30 : out std_logic;
Dbg_Rst_30 : out std_logic;
Dbg_Clk_31 : out std_logic;
Dbg_TDI_31 : out std_logic;
Dbg_TDO_31 : in std_logic;
Dbg_Reg_En_31 : out std_logic_vector(0 to 7);
Dbg_Capture_31 : out std_logic;
Dbg_Shift_31 : out std_logic;
Dbg_Update_31 : out std_logic;
Dbg_Rst_31 : out std_logic;
bscan_tdi : out std_logic;
bscan_reset : out std_logic;
bscan_shift : out std_logic;
bscan_update : out std_logic;
bscan_capture : out std_logic;
bscan_sel1 : out std_logic;
bscan_drck1 : out std_logic;
bscan_tdo1 : in std_logic;
bscan_ext_tdi : in std_logic;
bscan_ext_reset : in std_logic;
bscan_ext_shift : in std_logic;
bscan_ext_update : in std_logic;
bscan_ext_capture : in std_logic;
bscan_ext_sel : in std_logic;
bscan_ext_drck : in std_logic;
bscan_ext_tdo : out std_logic;
Ext_JTAG_DRCK : out std_logic;
Ext_JTAG_RESET : out std_logic;
Ext_JTAG_SEL : out std_logic;
Ext_JTAG_CAPTURE : out std_logic;
Ext_JTAG_SHIFT : out std_logic;
Ext_JTAG_UPDATE : out std_logic;
Ext_JTAG_TDI : out std_logic;
Ext_JTAG_TDO : in std_logic
);
end component;
begin
mdm_0 : mdm
generic map (
C_FAMILY => "virtex5",
C_JTAG_CHAIN => 2,
C_INTERCONNECT => 1,
C_BASEADDR => X"84400000",
C_HIGHADDR => X"8440ffff",
C_SPLB_AWIDTH => 32,
C_SPLB_DWIDTH => 64,
C_SPLB_P2P => 0,
C_SPLB_MID_WIDTH => 3,
C_SPLB_NUM_MASTERS => 7,
C_SPLB_NATIVE_DWIDTH => 32,
C_SPLB_SUPPORT_BURSTS => 1,
C_MB_DBG_PORTS => 1,
C_USE_UART => 1,
C_USE_BSCAN => 0,
C_S_AXI_ADDR_WIDTH => 32,
C_S_AXI_DATA_WIDTH => 32
)
port map (
Interrupt => Interrupt,
Debug_SYS_Rst => Debug_SYS_Rst,
Ext_BRK => Ext_BRK,
Ext_NM_BRK => Ext_NM_BRK,
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Dbg_Clk_0 => Dbg_Clk_0,
Dbg_TDI_0 => Dbg_TDI_0,
Dbg_TDO_0 => Dbg_TDO_0,
Dbg_Reg_En_0 => Dbg_Reg_En_0,
Dbg_Capture_0 => Dbg_Capture_0,
Dbg_Shift_0 => Dbg_Shift_0,
Dbg_Update_0 => Dbg_Update_0,
Dbg_Rst_0 => Dbg_Rst_0,
Dbg_Clk_1 => Dbg_Clk_1,
Dbg_TDI_1 => Dbg_TDI_1,
Dbg_TDO_1 => Dbg_TDO_1,
Dbg_Reg_En_1 => Dbg_Reg_En_1,
Dbg_Capture_1 => Dbg_Capture_1,
Dbg_Shift_1 => Dbg_Shift_1,
Dbg_Update_1 => Dbg_Update_1,
Dbg_Rst_1 => Dbg_Rst_1,
Dbg_Clk_2 => Dbg_Clk_2,
Dbg_TDI_2 => Dbg_TDI_2,
Dbg_TDO_2 => Dbg_TDO_2,
Dbg_Reg_En_2 => Dbg_Reg_En_2,
Dbg_Capture_2 => Dbg_Capture_2,
Dbg_Shift_2 => Dbg_Shift_2,
Dbg_Update_2 => Dbg_Update_2,
Dbg_Rst_2 => Dbg_Rst_2,
Dbg_Clk_3 => Dbg_Clk_3,
Dbg_TDI_3 => Dbg_TDI_3,
Dbg_TDO_3 => Dbg_TDO_3,
Dbg_Reg_En_3 => Dbg_Reg_En_3,
Dbg_Capture_3 => Dbg_Capture_3,
Dbg_Shift_3 => Dbg_Shift_3,
Dbg_Update_3 => Dbg_Update_3,
Dbg_Rst_3 => Dbg_Rst_3,
Dbg_Clk_4 => Dbg_Clk_4,
Dbg_TDI_4 => Dbg_TDI_4,
Dbg_TDO_4 => Dbg_TDO_4,
Dbg_Reg_En_4 => Dbg_Reg_En_4,
Dbg_Capture_4 => Dbg_Capture_4,
Dbg_Shift_4 => Dbg_Shift_4,
Dbg_Update_4 => Dbg_Update_4,
Dbg_Rst_4 => Dbg_Rst_4,
Dbg_Clk_5 => Dbg_Clk_5,
Dbg_TDI_5 => Dbg_TDI_5,
Dbg_TDO_5 => Dbg_TDO_5,
Dbg_Reg_En_5 => Dbg_Reg_En_5,
Dbg_Capture_5 => Dbg_Capture_5,
Dbg_Shift_5 => Dbg_Shift_5,
Dbg_Update_5 => Dbg_Update_5,
Dbg_Rst_5 => Dbg_Rst_5,
Dbg_Clk_6 => Dbg_Clk_6,
Dbg_TDI_6 => Dbg_TDI_6,
Dbg_TDO_6 => Dbg_TDO_6,
Dbg_Reg_En_6 => Dbg_Reg_En_6,
Dbg_Capture_6 => Dbg_Capture_6,
Dbg_Shift_6 => Dbg_Shift_6,
Dbg_Update_6 => Dbg_Update_6,
Dbg_Rst_6 => Dbg_Rst_6,
Dbg_Clk_7 => Dbg_Clk_7,
Dbg_TDI_7 => Dbg_TDI_7,
Dbg_TDO_7 => Dbg_TDO_7,
Dbg_Reg_En_7 => Dbg_Reg_En_7,
Dbg_Capture_7 => Dbg_Capture_7,
Dbg_Shift_7 => Dbg_Shift_7,
Dbg_Update_7 => Dbg_Update_7,
Dbg_Rst_7 => Dbg_Rst_7,
Dbg_Clk_8 => Dbg_Clk_8,
Dbg_TDI_8 => Dbg_TDI_8,
Dbg_TDO_8 => Dbg_TDO_8,
Dbg_Reg_En_8 => Dbg_Reg_En_8,
Dbg_Capture_8 => Dbg_Capture_8,
Dbg_Shift_8 => Dbg_Shift_8,
Dbg_Update_8 => Dbg_Update_8,
Dbg_Rst_8 => Dbg_Rst_8,
Dbg_Clk_9 => Dbg_Clk_9,
Dbg_TDI_9 => Dbg_TDI_9,
Dbg_TDO_9 => Dbg_TDO_9,
Dbg_Reg_En_9 => Dbg_Reg_En_9,
Dbg_Capture_9 => Dbg_Capture_9,
Dbg_Shift_9 => Dbg_Shift_9,
Dbg_Update_9 => Dbg_Update_9,
Dbg_Rst_9 => Dbg_Rst_9,
Dbg_Clk_10 => Dbg_Clk_10,
Dbg_TDI_10 => Dbg_TDI_10,
Dbg_TDO_10 => Dbg_TDO_10,
Dbg_Reg_En_10 => Dbg_Reg_En_10,
Dbg_Capture_10 => Dbg_Capture_10,
Dbg_Shift_10 => Dbg_Shift_10,
Dbg_Update_10 => Dbg_Update_10,
Dbg_Rst_10 => Dbg_Rst_10,
Dbg_Clk_11 => Dbg_Clk_11,
Dbg_TDI_11 => Dbg_TDI_11,
Dbg_TDO_11 => Dbg_TDO_11,
Dbg_Reg_En_11 => Dbg_Reg_En_11,
Dbg_Capture_11 => Dbg_Capture_11,
Dbg_Shift_11 => Dbg_Shift_11,
Dbg_Update_11 => Dbg_Update_11,
Dbg_Rst_11 => Dbg_Rst_11,
Dbg_Clk_12 => Dbg_Clk_12,
Dbg_TDI_12 => Dbg_TDI_12,
Dbg_TDO_12 => Dbg_TDO_12,
Dbg_Reg_En_12 => Dbg_Reg_En_12,
Dbg_Capture_12 => Dbg_Capture_12,
Dbg_Shift_12 => Dbg_Shift_12,
Dbg_Update_12 => Dbg_Update_12,
Dbg_Rst_12 => Dbg_Rst_12,
Dbg_Clk_13 => Dbg_Clk_13,
Dbg_TDI_13 => Dbg_TDI_13,
Dbg_TDO_13 => Dbg_TDO_13,
Dbg_Reg_En_13 => Dbg_Reg_En_13,
Dbg_Capture_13 => Dbg_Capture_13,
Dbg_Shift_13 => Dbg_Shift_13,
Dbg_Update_13 => Dbg_Update_13,
Dbg_Rst_13 => Dbg_Rst_13,
Dbg_Clk_14 => Dbg_Clk_14,
Dbg_TDI_14 => Dbg_TDI_14,
Dbg_TDO_14 => Dbg_TDO_14,
Dbg_Reg_En_14 => Dbg_Reg_En_14,
Dbg_Capture_14 => Dbg_Capture_14,
Dbg_Shift_14 => Dbg_Shift_14,
Dbg_Update_14 => Dbg_Update_14,
Dbg_Rst_14 => Dbg_Rst_14,
Dbg_Clk_15 => Dbg_Clk_15,
Dbg_TDI_15 => Dbg_TDI_15,
Dbg_TDO_15 => Dbg_TDO_15,
Dbg_Reg_En_15 => Dbg_Reg_En_15,
Dbg_Capture_15 => Dbg_Capture_15,
Dbg_Shift_15 => Dbg_Shift_15,
Dbg_Update_15 => Dbg_Update_15,
Dbg_Rst_15 => Dbg_Rst_15,
Dbg_Clk_16 => Dbg_Clk_16,
Dbg_TDI_16 => Dbg_TDI_16,
Dbg_TDO_16 => Dbg_TDO_16,
Dbg_Reg_En_16 => Dbg_Reg_En_16,
Dbg_Capture_16 => Dbg_Capture_16,
Dbg_Shift_16 => Dbg_Shift_16,
Dbg_Update_16 => Dbg_Update_16,
Dbg_Rst_16 => Dbg_Rst_16,
Dbg_Clk_17 => Dbg_Clk_17,
Dbg_TDI_17 => Dbg_TDI_17,
Dbg_TDO_17 => Dbg_TDO_17,
Dbg_Reg_En_17 => Dbg_Reg_En_17,
Dbg_Capture_17 => Dbg_Capture_17,
Dbg_Shift_17 => Dbg_Shift_17,
Dbg_Update_17 => Dbg_Update_17,
Dbg_Rst_17 => Dbg_Rst_17,
Dbg_Clk_18 => Dbg_Clk_18,
Dbg_TDI_18 => Dbg_TDI_18,
Dbg_TDO_18 => Dbg_TDO_18,
Dbg_Reg_En_18 => Dbg_Reg_En_18,
Dbg_Capture_18 => Dbg_Capture_18,
Dbg_Shift_18 => Dbg_Shift_18,
Dbg_Update_18 => Dbg_Update_18,
Dbg_Rst_18 => Dbg_Rst_18,
Dbg_Clk_19 => Dbg_Clk_19,
Dbg_TDI_19 => Dbg_TDI_19,
Dbg_TDO_19 => Dbg_TDO_19,
Dbg_Reg_En_19 => Dbg_Reg_En_19,
Dbg_Capture_19 => Dbg_Capture_19,
Dbg_Shift_19 => Dbg_Shift_19,
Dbg_Update_19 => Dbg_Update_19,
Dbg_Rst_19 => Dbg_Rst_19,
Dbg_Clk_20 => Dbg_Clk_20,
Dbg_TDI_20 => Dbg_TDI_20,
Dbg_TDO_20 => Dbg_TDO_20,
Dbg_Reg_En_20 => Dbg_Reg_En_20,
Dbg_Capture_20 => Dbg_Capture_20,
Dbg_Shift_20 => Dbg_Shift_20,
Dbg_Update_20 => Dbg_Update_20,
Dbg_Rst_20 => Dbg_Rst_20,
Dbg_Clk_21 => Dbg_Clk_21,
Dbg_TDI_21 => Dbg_TDI_21,
Dbg_TDO_21 => Dbg_TDO_21,
Dbg_Reg_En_21 => Dbg_Reg_En_21,
Dbg_Capture_21 => Dbg_Capture_21,
Dbg_Shift_21 => Dbg_Shift_21,
Dbg_Update_21 => Dbg_Update_21,
Dbg_Rst_21 => Dbg_Rst_21,
Dbg_Clk_22 => Dbg_Clk_22,
Dbg_TDI_22 => Dbg_TDI_22,
Dbg_TDO_22 => Dbg_TDO_22,
Dbg_Reg_En_22 => Dbg_Reg_En_22,
Dbg_Capture_22 => Dbg_Capture_22,
Dbg_Shift_22 => Dbg_Shift_22,
Dbg_Update_22 => Dbg_Update_22,
Dbg_Rst_22 => Dbg_Rst_22,
Dbg_Clk_23 => Dbg_Clk_23,
Dbg_TDI_23 => Dbg_TDI_23,
Dbg_TDO_23 => Dbg_TDO_23,
Dbg_Reg_En_23 => Dbg_Reg_En_23,
Dbg_Capture_23 => Dbg_Capture_23,
Dbg_Shift_23 => Dbg_Shift_23,
Dbg_Update_23 => Dbg_Update_23,
Dbg_Rst_23 => Dbg_Rst_23,
Dbg_Clk_24 => Dbg_Clk_24,
Dbg_TDI_24 => Dbg_TDI_24,
Dbg_TDO_24 => Dbg_TDO_24,
Dbg_Reg_En_24 => Dbg_Reg_En_24,
Dbg_Capture_24 => Dbg_Capture_24,
Dbg_Shift_24 => Dbg_Shift_24,
Dbg_Update_24 => Dbg_Update_24,
Dbg_Rst_24 => Dbg_Rst_24,
Dbg_Clk_25 => Dbg_Clk_25,
Dbg_TDI_25 => Dbg_TDI_25,
Dbg_TDO_25 => Dbg_TDO_25,
Dbg_Reg_En_25 => Dbg_Reg_En_25,
Dbg_Capture_25 => Dbg_Capture_25,
Dbg_Shift_25 => Dbg_Shift_25,
Dbg_Update_25 => Dbg_Update_25,
Dbg_Rst_25 => Dbg_Rst_25,
Dbg_Clk_26 => Dbg_Clk_26,
Dbg_TDI_26 => Dbg_TDI_26,
Dbg_TDO_26 => Dbg_TDO_26,
Dbg_Reg_En_26 => Dbg_Reg_En_26,
Dbg_Capture_26 => Dbg_Capture_26,
Dbg_Shift_26 => Dbg_Shift_26,
Dbg_Update_26 => Dbg_Update_26,
Dbg_Rst_26 => Dbg_Rst_26,
Dbg_Clk_27 => Dbg_Clk_27,
Dbg_TDI_27 => Dbg_TDI_27,
Dbg_TDO_27 => Dbg_TDO_27,
Dbg_Reg_En_27 => Dbg_Reg_En_27,
Dbg_Capture_27 => Dbg_Capture_27,
Dbg_Shift_27 => Dbg_Shift_27,
Dbg_Update_27 => Dbg_Update_27,
Dbg_Rst_27 => Dbg_Rst_27,
Dbg_Clk_28 => Dbg_Clk_28,
Dbg_TDI_28 => Dbg_TDI_28,
Dbg_TDO_28 => Dbg_TDO_28,
Dbg_Reg_En_28 => Dbg_Reg_En_28,
Dbg_Capture_28 => Dbg_Capture_28,
Dbg_Shift_28 => Dbg_Shift_28,
Dbg_Update_28 => Dbg_Update_28,
Dbg_Rst_28 => Dbg_Rst_28,
Dbg_Clk_29 => Dbg_Clk_29,
Dbg_TDI_29 => Dbg_TDI_29,
Dbg_TDO_29 => Dbg_TDO_29,
Dbg_Reg_En_29 => Dbg_Reg_En_29,
Dbg_Capture_29 => Dbg_Capture_29,
Dbg_Shift_29 => Dbg_Shift_29,
Dbg_Update_29 => Dbg_Update_29,
Dbg_Rst_29 => Dbg_Rst_29,
Dbg_Clk_30 => Dbg_Clk_30,
Dbg_TDI_30 => Dbg_TDI_30,
Dbg_TDO_30 => Dbg_TDO_30,
Dbg_Reg_En_30 => Dbg_Reg_En_30,
Dbg_Capture_30 => Dbg_Capture_30,
Dbg_Shift_30 => Dbg_Shift_30,
Dbg_Update_30 => Dbg_Update_30,
Dbg_Rst_30 => Dbg_Rst_30,
Dbg_Clk_31 => Dbg_Clk_31,
Dbg_TDI_31 => Dbg_TDI_31,
Dbg_TDO_31 => Dbg_TDO_31,
Dbg_Reg_En_31 => Dbg_Reg_En_31,
Dbg_Capture_31 => Dbg_Capture_31,
Dbg_Shift_31 => Dbg_Shift_31,
Dbg_Update_31 => Dbg_Update_31,
Dbg_Rst_31 => Dbg_Rst_31,
bscan_tdi => bscan_tdi,
bscan_reset => bscan_reset,
bscan_shift => bscan_shift,
bscan_update => bscan_update,
bscan_capture => bscan_capture,
bscan_sel1 => bscan_sel1,
bscan_drck1 => bscan_drck1,
bscan_tdo1 => bscan_tdo1,
bscan_ext_tdi => bscan_ext_tdi,
bscan_ext_reset => bscan_ext_reset,
bscan_ext_shift => bscan_ext_shift,
bscan_ext_update => bscan_ext_update,
bscan_ext_capture => bscan_ext_capture,
bscan_ext_sel => bscan_ext_sel,
bscan_ext_drck => bscan_ext_drck,
bscan_ext_tdo => bscan_ext_tdo,
Ext_JTAG_DRCK => Ext_JTAG_DRCK,
Ext_JTAG_RESET => Ext_JTAG_RESET,
Ext_JTAG_SEL => Ext_JTAG_SEL,
Ext_JTAG_CAPTURE => Ext_JTAG_CAPTURE,
Ext_JTAG_SHIFT => Ext_JTAG_SHIFT,
Ext_JTAG_UPDATE => Ext_JTAG_UPDATE,
Ext_JTAG_TDI => Ext_JTAG_TDI,
Ext_JTAG_TDO => Ext_JTAG_TDO
);
end architecture STRUCTURE;
| lgpl-3.0 | 727fd26a3f188fca9d6596d6914a2abb | 0.575864 | 2.800272 | false | false | false | false |
jairov4/accel-oil | impl/impl_test_pcie/hdl/system_xps_intc_0_wrapper.vhd | 1 | 7,118 | -------------------------------------------------------------------------------
-- system_xps_intc_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library xps_intc_v2_01_a;
use xps_intc_v2_01_a.all;
entity system_xps_intc_0_wrapper is
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_masterID : in std_logic_vector(0 to 2);
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 7);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_wrDBus : in std_logic_vector(0 to 63);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_MSize : in std_logic_vector(0 to 1);
PLB_lockErr : in std_logic;
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 63);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 5);
Sl_MWrErr : out std_logic_vector(0 to 5);
Sl_MRdErr : out std_logic_vector(0 to 5);
Sl_wrBTerm : out std_logic;
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdBTerm : out std_logic;
Sl_MIRQ : out std_logic_vector(0 to 5);
Intr : in std_logic_vector(1 downto 0);
Irq : out std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of system_xps_intc_0_wrapper : entity is "xps_intc_v2_01_a";
end system_xps_intc_0_wrapper;
architecture STRUCTURE of system_xps_intc_0_wrapper is
component xps_intc is
generic (
C_FAMILY : STRING;
C_BASEADDR : std_logic_vector(0 to 31);
C_HIGHADDR : std_logic_vector(0 to 31);
C_SPLB_AWIDTH : INTEGER;
C_SPLB_DWIDTH : INTEGER;
C_SPLB_P2P : INTEGER;
C_SPLB_NUM_MASTERS : INTEGER;
C_SPLB_MID_WIDTH : INTEGER;
C_SPLB_NATIVE_DWIDTH : INTEGER;
C_SPLB_SUPPORT_BURSTS : INTEGER;
C_NUM_INTR_INPUTS : INTEGER;
C_KIND_OF_INTR : std_logic_vector(31 downto 0);
C_KIND_OF_EDGE : std_logic_vector(31 downto 0);
C_KIND_OF_LVL : std_logic_vector(31 downto 0);
C_HAS_IPR : INTEGER;
C_HAS_SIE : INTEGER;
C_HAS_CIE : INTEGER;
C_HAS_IVR : INTEGER;
C_IRQ_IS_LEVEL : INTEGER;
C_IRQ_ACTIVE : std_logic
);
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1));
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1));
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1));
PLB_UABus : in std_logic_vector(0 to 31);
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_MSize : in std_logic_vector(0 to 1);
PLB_lockErr : in std_logic;
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1));
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_wrBTerm : out std_logic;
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdBTerm : out std_logic;
Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Intr : in std_logic_vector((C_NUM_INTR_INPUTS-1) downto 0);
Irq : out std_logic
);
end component;
begin
xps_intc_0 : xps_intc
generic map (
C_FAMILY => "virtex5",
C_BASEADDR => X"81800000",
C_HIGHADDR => X"8180ffff",
C_SPLB_AWIDTH => 32,
C_SPLB_DWIDTH => 64,
C_SPLB_P2P => 0,
C_SPLB_NUM_MASTERS => 6,
C_SPLB_MID_WIDTH => 3,
C_SPLB_NATIVE_DWIDTH => 32,
C_SPLB_SUPPORT_BURSTS => 0,
C_NUM_INTR_INPUTS => 2,
C_KIND_OF_INTR => B"11111111111111111111111111111100",
C_KIND_OF_EDGE => B"11111111111111111111111111111111",
C_KIND_OF_LVL => B"11111111111111111111111111111111",
C_HAS_IPR => 1,
C_HAS_SIE => 1,
C_HAS_CIE => 1,
C_HAS_IVR => 1,
C_IRQ_IS_LEVEL => 1,
C_IRQ_ACTIVE => '1'
)
port map (
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_PAValid => PLB_PAValid,
PLB_masterID => PLB_masterID,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_wrDBus => PLB_wrDBus,
PLB_UABus => PLB_UABus,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_MSize => PLB_MSize,
PLB_lockErr => PLB_lockErr,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_rdDBus => Sl_rdDBus,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MIRQ => Sl_MIRQ,
Intr => Intr,
Irq => Irq
);
end architecture STRUCTURE;
| lgpl-3.0 | c382613988660295b15f9b1659d1e106 | 0.584153 | 3.190498 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00633.vhd | 1 | 79,152 | -- NEED RESULT: ARCH00633.P1: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633.P2: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633.P3: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633.P4: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633.P5: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633.P6: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633.P7: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633.P8: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633.P9: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633.P10: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633.P11: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633.P12: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633.P13: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633.P14: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633.P15: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633.P16: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633.P17: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633: Old transactions were removed on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633: Old transactions were removed on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633: Old transactions were removed on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633: Old transactions were removed on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633: Old transactions were removed on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633: Old transactions were removed on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633: Old transactions were removed on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633: Old transactions were removed on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633: Old transactions were removed on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633: Old transactions were removed on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633: Old transactions were removed on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633: Old transactions were removed on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633: Old transactions were removed on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633: Old transactions were removed on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633: Old transactions were removed on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633: Old transactions were removed on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633: One transport transaction occurred on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00633: Old transactions were removed on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: P17: Transport transactions entirely completed passed
-- NEED RESULT: P16: Transport transactions entirely completed passed
-- NEED RESULT: P15: Transport transactions entirely completed passed
-- NEED RESULT: P14: Transport transactions entirely completed passed
-- NEED RESULT: P13: Transport transactions entirely completed passed
-- NEED RESULT: P12: Transport transactions entirely completed passed
-- NEED RESULT: P11: Transport transactions entirely completed passed
-- NEED RESULT: P10: Transport transactions entirely completed passed
-- NEED RESULT: P9: Transport transactions entirely completed passed
-- NEED RESULT: P8: Transport transactions entirely completed passed
-- NEED RESULT: P7: Transport transactions entirely completed passed
-- NEED RESULT: P6: Transport transactions entirely completed passed
-- NEED RESULT: P5: Transport transactions entirely completed passed
-- NEED RESULT: P4: Transport transactions entirely completed passed
-- NEED RESULT: P3: Transport transactions entirely completed passed
-- NEED RESULT: P2: Transport transactions entirely completed passed
-- NEED RESULT: P1: Transport transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00633
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (2)
-- 8.3 (3)
-- 8.3 (6)
-- 8.3.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00633)
-- ENT00633_Test_Bench(ARCH00633_Test_Bench)
--
-- REVISION HISTORY:
--
-- 25-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00633 of E00000 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_boolean : chk_sig_type := -1 ;
signal chk_bit : chk_sig_type := -1 ;
signal chk_severity_level : chk_sig_type := -1 ;
signal chk_character : chk_sig_type := -1 ;
signal chk_st_enum1 : chk_sig_type := -1 ;
signal chk_integer : chk_sig_type := -1 ;
signal chk_st_int1 : chk_sig_type := -1 ;
signal chk_time : chk_sig_type := -1 ;
signal chk_st_phys1 : chk_sig_type := -1 ;
signal chk_real : chk_sig_type := -1 ;
signal chk_st_real1 : chk_sig_type := -1 ;
signal chk_st_rec1 : chk_sig_type := -1 ;
signal chk_st_rec2 : chk_sig_type := -1 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
signal chk_st_arr1 : chk_sig_type := -1 ;
signal chk_st_arr2 : chk_sig_type := -1 ;
signal chk_st_arr3 : chk_sig_type := -1 ;
--
type arr_boolean is
array (integer range -1 downto - 3 ) of
boolean ;
type arr_bit is
array (integer range -1 downto - 3 ) of
bit ;
type arr_severity_level is
array (integer range -1 downto - 3 ) of
severity_level ;
type arr_character is
array (integer range -1 downto - 3 ) of
character ;
type arr_st_enum1 is
array (integer range -1 downto - 3 ) of
st_enum1 ;
type arr_integer is
array (integer range -1 downto - 3 ) of
integer ;
type arr_st_int1 is
array (integer range -1 downto - 3 ) of
st_int1 ;
type arr_time is
array (integer range -1 downto - 3 ) of
time ;
type arr_st_phys1 is
array (integer range -1 downto - 3 ) of
st_phys1 ;
type arr_real is
array (integer range -1 downto - 3 ) of
real ;
type arr_st_real1 is
array (integer range -1 downto - 3 ) of
st_real1 ;
type arr_st_rec1 is
array (integer range -1 downto - 3 ) of
st_rec1 ;
type arr_st_rec2 is
array (integer range -1 downto - 3 ) of
st_rec2 ;
type arr_st_rec3 is
array (integer range -1 downto - 3 ) of
st_rec3 ;
type arr_st_arr1 is
array (integer range -1 downto - 3 ) of
st_arr1 ;
type arr_st_arr2 is
array (integer range -1 downto - 3 ) of
st_arr2 ;
type arr_st_arr3 is
array (integer range -1 downto - 3 ) of
st_arr3 ;
--
signal s_boolean_1 : boolean
:= c_boolean_1 ;
signal s_bit_1 : bit
:= c_bit_1 ;
signal s_severity_level_1 : severity_level
:= c_severity_level_1 ;
signal s_character_1 : character
:= c_character_1 ;
signal s_st_enum1_1 : st_enum1
:= c_st_enum1_1 ;
signal s_integer_1 : integer
:= c_integer_1 ;
signal s_st_int1_1 : st_int1
:= c_st_int1_1 ;
signal s_time_1 : time
:= c_time_1 ;
signal s_st_phys1_1 : st_phys1
:= c_st_phys1_1 ;
signal s_real_1 : real
:= c_real_1 ;
signal s_st_real1_1 : st_real1
:= c_st_real1_1 ;
signal s_st_rec1_1 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2_1 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3_1 : st_rec3
:= c_st_rec3_1 ;
signal s_st_arr1_1 : st_arr1
:= c_st_arr1_1 ;
signal s_st_arr2_1 : st_arr2
:= c_st_arr2_1 ;
signal s_st_arr3_1 : st_arr3
:= c_st_arr3_1 ;
--
signal s_boolean_2 : boolean
:= c_boolean_1 ;
signal s_bit_2 : bit
:= c_bit_1 ;
signal s_severity_level_2 : severity_level
:= c_severity_level_1 ;
signal s_character_2 : character
:= c_character_1 ;
signal s_st_enum1_2 : st_enum1
:= c_st_enum1_1 ;
signal s_integer_2 : integer
:= c_integer_1 ;
signal s_st_int1_2 : st_int1
:= c_st_int1_1 ;
signal s_time_2 : time
:= c_time_1 ;
signal s_st_phys1_2 : st_phys1
:= c_st_phys1_1 ;
signal s_real_2 : real
:= c_real_1 ;
signal s_st_real1_2 : st_real1
:= c_st_real1_1 ;
signal s_st_rec1_2 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2_2 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3_2 : st_rec3
:= c_st_rec3_1 ;
signal s_st_arr1_2 : st_arr1
:= c_st_arr1_1 ;
signal s_st_arr2_2 : st_arr2
:= c_st_arr2_1 ;
signal s_st_arr3_2 : st_arr3
:= c_st_arr3_1 ;
--
signal s_boolean_3 : boolean
:= c_boolean_1 ;
signal s_bit_3 : bit
:= c_bit_1 ;
signal s_severity_level_3 : severity_level
:= c_severity_level_1 ;
signal s_character_3 : character
:= c_character_1 ;
signal s_st_enum1_3 : st_enum1
:= c_st_enum1_1 ;
signal s_integer_3 : integer
:= c_integer_1 ;
signal s_st_int1_3 : st_int1
:= c_st_int1_1 ;
signal s_time_3 : time
:= c_time_1 ;
signal s_st_phys1_3 : st_phys1
:= c_st_phys1_1 ;
signal s_real_3 : real
:= c_real_1 ;
signal s_st_real1_3 : st_real1
:= c_st_real1_1 ;
signal s_st_rec1_3 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2_3 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3_3 : st_rec3
:= c_st_rec3_1 ;
signal s_st_arr1_3 : st_arr1
:= c_st_arr1_1 ;
signal s_st_arr2_3 : st_arr2
:= c_st_arr2_1 ;
signal s_st_arr3_3 : st_arr3
:= c_st_arr3_1 ;
--
begin
PGEN_CHKP_1 :
process ( chk_boolean )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions entirely completed",
chk_boolean = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P1 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_boolean_1,
s_boolean_2,
s_boolean_3) <= transport
arr_boolean ' (
(c_boolean_2,
c_boolean_2,
c_boolean_2) ) after 10 ns,
arr_boolean ' (
(c_boolean_1,
c_boolean_1,
c_boolean_1) ) after 20 ns ;
--
when 1
=> correct :=
s_boolean_1 = c_boolean_2 and
s_boolean_2 = c_boolean_2 and
s_boolean_3 = c_boolean_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_boolean_1 = c_boolean_1 and
s_boolean_2 = c_boolean_1 and
s_boolean_3 = c_boolean_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00633.P1" ,
"Multi transport transactions occurred on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
(s_boolean_1,
s_boolean_2,
s_boolean_3) <= transport
arr_boolean ' (
(c_boolean_2,
c_boolean_2,
c_boolean_2) ) after 10 ns,
arr_boolean ' (
(c_boolean_1,
c_boolean_1,
c_boolean_1) ) after 20 ns,
arr_boolean ' (
(c_boolean_2,
c_boolean_2,
c_boolean_2) ) after 30 ns,
arr_boolean ' (
(c_boolean_1,
c_boolean_1,
c_boolean_1) ) after 40 ns ;
--
when 3
=> correct :=
s_boolean_1 = c_boolean_2 and
s_boolean_2 = c_boolean_2 and
s_boolean_3 = c_boolean_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_boolean_1,
s_boolean_2,
s_boolean_3) <= transport
arr_boolean ' (
(c_boolean_1,
c_boolean_1,
c_boolean_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_boolean_1 = c_boolean_1 and
s_boolean_2 = c_boolean_1 and
s_boolean_3 = c_boolean_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00633" ,
"One transport transaction occurred on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
test_report ( "ARCH00633" ,
"Old transactions were removed on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00633" ,
"Old transactions were removed on signal " &
"asg with aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_boolean <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_boolean_1'EVENT and
s_boolean_2'EVENT and
s_boolean_3'EVENT ;
end process P1 ;
--
PGEN_CHKP_2 :
process ( chk_bit )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions entirely completed",
chk_bit = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P2 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_bit_1,
s_bit_2,
s_bit_3) <= transport
arr_bit ' (
(c_bit_2,
c_bit_2,
c_bit_2) ) after 10 ns,
arr_bit ' (
(c_bit_1,
c_bit_1,
c_bit_1) ) after 20 ns ;
--
when 1
=> correct :=
s_bit_1 = c_bit_2 and
s_bit_2 = c_bit_2 and
s_bit_3 = c_bit_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_bit_1 = c_bit_1 and
s_bit_2 = c_bit_1 and
s_bit_3 = c_bit_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00633.P2" ,
"Multi transport transactions occurred on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
(s_bit_1,
s_bit_2,
s_bit_3) <= transport
arr_bit ' (
(c_bit_2,
c_bit_2,
c_bit_2) ) after 10 ns,
arr_bit ' (
(c_bit_1,
c_bit_1,
c_bit_1) ) after 20 ns,
arr_bit ' (
(c_bit_2,
c_bit_2,
c_bit_2) ) after 30 ns,
arr_bit ' (
(c_bit_1,
c_bit_1,
c_bit_1) ) after 40 ns ;
--
when 3
=> correct :=
s_bit_1 = c_bit_2 and
s_bit_2 = c_bit_2 and
s_bit_3 = c_bit_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_bit_1,
s_bit_2,
s_bit_3) <= transport
arr_bit ' (
(c_bit_1,
c_bit_1,
c_bit_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_bit_1 = c_bit_1 and
s_bit_2 = c_bit_1 and
s_bit_3 = c_bit_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00633" ,
"One transport transaction occurred on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
test_report ( "ARCH00633" ,
"Old transactions were removed on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00633" ,
"Old transactions were removed on signal " &
"asg with aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_bit <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_bit_1'EVENT and
s_bit_2'EVENT and
s_bit_3'EVENT ;
end process P2 ;
--
PGEN_CHKP_3 :
process ( chk_severity_level )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions entirely completed",
chk_severity_level = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P3 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_severity_level_1,
s_severity_level_2,
s_severity_level_3) <= transport
arr_severity_level ' (
(c_severity_level_2,
c_severity_level_2,
c_severity_level_2) ) after 10 ns,
arr_severity_level ' (
(c_severity_level_1,
c_severity_level_1,
c_severity_level_1) ) after 20 ns ;
--
when 1
=> correct :=
s_severity_level_1 = c_severity_level_2 and
s_severity_level_2 = c_severity_level_2 and
s_severity_level_3 = c_severity_level_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_severity_level_1 = c_severity_level_1 and
s_severity_level_2 = c_severity_level_1 and
s_severity_level_3 = c_severity_level_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00633.P3" ,
"Multi transport transactions occurred on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
(s_severity_level_1,
s_severity_level_2,
s_severity_level_3) <= transport
arr_severity_level ' (
(c_severity_level_2,
c_severity_level_2,
c_severity_level_2) ) after 10 ns,
arr_severity_level ' (
(c_severity_level_1,
c_severity_level_1,
c_severity_level_1) ) after 20 ns,
arr_severity_level ' (
(c_severity_level_2,
c_severity_level_2,
c_severity_level_2) ) after 30 ns,
arr_severity_level ' (
(c_severity_level_1,
c_severity_level_1,
c_severity_level_1) ) after 40 ns ;
--
when 3
=> correct :=
s_severity_level_1 = c_severity_level_2 and
s_severity_level_2 = c_severity_level_2 and
s_severity_level_3 = c_severity_level_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_severity_level_1,
s_severity_level_2,
s_severity_level_3) <= transport
arr_severity_level ' (
(c_severity_level_1,
c_severity_level_1,
c_severity_level_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_severity_level_1 = c_severity_level_1 and
s_severity_level_2 = c_severity_level_1 and
s_severity_level_3 = c_severity_level_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00633" ,
"One transport transaction occurred on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
test_report ( "ARCH00633" ,
"Old transactions were removed on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00633" ,
"Old transactions were removed on signal " &
"asg with aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_severity_level <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_severity_level_1'EVENT and
s_severity_level_2'EVENT and
s_severity_level_3'EVENT ;
end process P3 ;
--
PGEN_CHKP_4 :
process ( chk_character )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Transport transactions entirely completed",
chk_character = 4 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
P4 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_character_1,
s_character_2,
s_character_3) <= transport
arr_character ' (
(c_character_2,
c_character_2,
c_character_2) ) after 10 ns,
arr_character ' (
(c_character_1,
c_character_1,
c_character_1) ) after 20 ns ;
--
when 1
=> correct :=
s_character_1 = c_character_2 and
s_character_2 = c_character_2 and
s_character_3 = c_character_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_character_1 = c_character_1 and
s_character_2 = c_character_1 and
s_character_3 = c_character_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00633.P4" ,
"Multi transport transactions occurred on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
(s_character_1,
s_character_2,
s_character_3) <= transport
arr_character ' (
(c_character_2,
c_character_2,
c_character_2) ) after 10 ns,
arr_character ' (
(c_character_1,
c_character_1,
c_character_1) ) after 20 ns,
arr_character ' (
(c_character_2,
c_character_2,
c_character_2) ) after 30 ns,
arr_character ' (
(c_character_1,
c_character_1,
c_character_1) ) after 40 ns ;
--
when 3
=> correct :=
s_character_1 = c_character_2 and
s_character_2 = c_character_2 and
s_character_3 = c_character_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_character_1,
s_character_2,
s_character_3) <= transport
arr_character ' (
(c_character_1,
c_character_1,
c_character_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_character_1 = c_character_1 and
s_character_2 = c_character_1 and
s_character_3 = c_character_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00633" ,
"One transport transaction occurred on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
test_report ( "ARCH00633" ,
"Old transactions were removed on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00633" ,
"Old transactions were removed on signal " &
"asg with aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_character <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_character_1'EVENT and
s_character_2'EVENT and
s_character_3'EVENT ;
end process P4 ;
--
PGEN_CHKP_5 :
process ( chk_st_enum1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Transport transactions entirely completed",
chk_st_enum1 = 4 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
P5 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_enum1_1,
s_st_enum1_2,
s_st_enum1_3) <= transport
arr_st_enum1 ' (
(c_st_enum1_2,
c_st_enum1_2,
c_st_enum1_2) ) after 10 ns,
arr_st_enum1 ' (
(c_st_enum1_1,
c_st_enum1_1,
c_st_enum1_1) ) after 20 ns ;
--
when 1
=> correct :=
s_st_enum1_1 = c_st_enum1_2 and
s_st_enum1_2 = c_st_enum1_2 and
s_st_enum1_3 = c_st_enum1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1_1 = c_st_enum1_1 and
s_st_enum1_2 = c_st_enum1_1 and
s_st_enum1_3 = c_st_enum1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00633.P5" ,
"Multi transport transactions occurred on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
(s_st_enum1_1,
s_st_enum1_2,
s_st_enum1_3) <= transport
arr_st_enum1 ' (
(c_st_enum1_2,
c_st_enum1_2,
c_st_enum1_2) ) after 10 ns,
arr_st_enum1 ' (
(c_st_enum1_1,
c_st_enum1_1,
c_st_enum1_1) ) after 20 ns,
arr_st_enum1 ' (
(c_st_enum1_2,
c_st_enum1_2,
c_st_enum1_2) ) after 30 ns,
arr_st_enum1 ' (
(c_st_enum1_1,
c_st_enum1_1,
c_st_enum1_1) ) after 40 ns ;
--
when 3
=> correct :=
s_st_enum1_1 = c_st_enum1_2 and
s_st_enum1_2 = c_st_enum1_2 and
s_st_enum1_3 = c_st_enum1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_enum1_1,
s_st_enum1_2,
s_st_enum1_3) <= transport
arr_st_enum1 ' (
(c_st_enum1_1,
c_st_enum1_1,
c_st_enum1_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1_1 = c_st_enum1_1 and
s_st_enum1_2 = c_st_enum1_1 and
s_st_enum1_3 = c_st_enum1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00633" ,
"One transport transaction occurred on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
test_report ( "ARCH00633" ,
"Old transactions were removed on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00633" ,
"Old transactions were removed on signal " &
"asg with aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_enum1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_st_enum1_1'EVENT and
s_st_enum1_2'EVENT and
s_st_enum1_3'EVENT ;
end process P5 ;
--
PGEN_CHKP_6 :
process ( chk_integer )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Transport transactions entirely completed",
chk_integer = 4 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
P6 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_integer_1,
s_integer_2,
s_integer_3) <= transport
arr_integer ' (
(c_integer_2,
c_integer_2,
c_integer_2) ) after 10 ns,
arr_integer ' (
(c_integer_1,
c_integer_1,
c_integer_1) ) after 20 ns ;
--
when 1
=> correct :=
s_integer_1 = c_integer_2 and
s_integer_2 = c_integer_2 and
s_integer_3 = c_integer_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_integer_1 = c_integer_1 and
s_integer_2 = c_integer_1 and
s_integer_3 = c_integer_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00633.P6" ,
"Multi transport transactions occurred on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
(s_integer_1,
s_integer_2,
s_integer_3) <= transport
arr_integer ' (
(c_integer_2,
c_integer_2,
c_integer_2) ) after 10 ns,
arr_integer ' (
(c_integer_1,
c_integer_1,
c_integer_1) ) after 20 ns,
arr_integer ' (
(c_integer_2,
c_integer_2,
c_integer_2) ) after 30 ns,
arr_integer ' (
(c_integer_1,
c_integer_1,
c_integer_1) ) after 40 ns ;
--
when 3
=> correct :=
s_integer_1 = c_integer_2 and
s_integer_2 = c_integer_2 and
s_integer_3 = c_integer_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_integer_1,
s_integer_2,
s_integer_3) <= transport
arr_integer ' (
(c_integer_1,
c_integer_1,
c_integer_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_integer_1 = c_integer_1 and
s_integer_2 = c_integer_1 and
s_integer_3 = c_integer_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00633" ,
"One transport transaction occurred on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
test_report ( "ARCH00633" ,
"Old transactions were removed on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00633" ,
"Old transactions were removed on signal " &
"asg with aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_integer <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_integer_1'EVENT and
s_integer_2'EVENT and
s_integer_3'EVENT ;
end process P6 ;
--
PGEN_CHKP_7 :
process ( chk_st_int1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Transport transactions entirely completed",
chk_st_int1 = 4 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
P7 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_int1_1,
s_st_int1_2,
s_st_int1_3) <= transport
arr_st_int1 ' (
(c_st_int1_2,
c_st_int1_2,
c_st_int1_2) ) after 10 ns,
arr_st_int1 ' (
(c_st_int1_1,
c_st_int1_1,
c_st_int1_1) ) after 20 ns ;
--
when 1
=> correct :=
s_st_int1_1 = c_st_int1_2 and
s_st_int1_2 = c_st_int1_2 and
s_st_int1_3 = c_st_int1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_int1_1 = c_st_int1_1 and
s_st_int1_2 = c_st_int1_1 and
s_st_int1_3 = c_st_int1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00633.P7" ,
"Multi transport transactions occurred on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
(s_st_int1_1,
s_st_int1_2,
s_st_int1_3) <= transport
arr_st_int1 ' (
(c_st_int1_2,
c_st_int1_2,
c_st_int1_2) ) after 10 ns,
arr_st_int1 ' (
(c_st_int1_1,
c_st_int1_1,
c_st_int1_1) ) after 20 ns,
arr_st_int1 ' (
(c_st_int1_2,
c_st_int1_2,
c_st_int1_2) ) after 30 ns,
arr_st_int1 ' (
(c_st_int1_1,
c_st_int1_1,
c_st_int1_1) ) after 40 ns ;
--
when 3
=> correct :=
s_st_int1_1 = c_st_int1_2 and
s_st_int1_2 = c_st_int1_2 and
s_st_int1_3 = c_st_int1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_int1_1,
s_st_int1_2,
s_st_int1_3) <= transport
arr_st_int1 ' (
(c_st_int1_1,
c_st_int1_1,
c_st_int1_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_int1_1 = c_st_int1_1 and
s_st_int1_2 = c_st_int1_1 and
s_st_int1_3 = c_st_int1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00633" ,
"One transport transaction occurred on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
test_report ( "ARCH00633" ,
"Old transactions were removed on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00633" ,
"Old transactions were removed on signal " &
"asg with aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_int1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_st_int1_1'EVENT and
s_st_int1_2'EVENT and
s_st_int1_3'EVENT ;
end process P7 ;
--
PGEN_CHKP_8 :
process ( chk_time )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Transport transactions entirely completed",
chk_time = 4 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
P8 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_time_1,
s_time_2,
s_time_3) <= transport
arr_time ' (
(c_time_2,
c_time_2,
c_time_2) ) after 10 ns,
arr_time ' (
(c_time_1,
c_time_1,
c_time_1) ) after 20 ns ;
--
when 1
=> correct :=
s_time_1 = c_time_2 and
s_time_2 = c_time_2 and
s_time_3 = c_time_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_time_1 = c_time_1 and
s_time_2 = c_time_1 and
s_time_3 = c_time_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00633.P8" ,
"Multi transport transactions occurred on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
(s_time_1,
s_time_2,
s_time_3) <= transport
arr_time ' (
(c_time_2,
c_time_2,
c_time_2) ) after 10 ns,
arr_time ' (
(c_time_1,
c_time_1,
c_time_1) ) after 20 ns,
arr_time ' (
(c_time_2,
c_time_2,
c_time_2) ) after 30 ns,
arr_time ' (
(c_time_1,
c_time_1,
c_time_1) ) after 40 ns ;
--
when 3
=> correct :=
s_time_1 = c_time_2 and
s_time_2 = c_time_2 and
s_time_3 = c_time_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_time_1,
s_time_2,
s_time_3) <= transport
arr_time ' (
(c_time_1,
c_time_1,
c_time_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_time_1 = c_time_1 and
s_time_2 = c_time_1 and
s_time_3 = c_time_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00633" ,
"One transport transaction occurred on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
test_report ( "ARCH00633" ,
"Old transactions were removed on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00633" ,
"Old transactions were removed on signal " &
"asg with aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_time <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_time_1'EVENT and
s_time_2'EVENT and
s_time_3'EVENT ;
end process P8 ;
--
PGEN_CHKP_9 :
process ( chk_st_phys1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Transport transactions entirely completed",
chk_st_phys1 = 4 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
P9 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_phys1_1,
s_st_phys1_2,
s_st_phys1_3) <= transport
arr_st_phys1 ' (
(c_st_phys1_2,
c_st_phys1_2,
c_st_phys1_2) ) after 10 ns,
arr_st_phys1 ' (
(c_st_phys1_1,
c_st_phys1_1,
c_st_phys1_1) ) after 20 ns ;
--
when 1
=> correct :=
s_st_phys1_1 = c_st_phys1_2 and
s_st_phys1_2 = c_st_phys1_2 and
s_st_phys1_3 = c_st_phys1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_phys1_1 = c_st_phys1_1 and
s_st_phys1_2 = c_st_phys1_1 and
s_st_phys1_3 = c_st_phys1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00633.P9" ,
"Multi transport transactions occurred on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
(s_st_phys1_1,
s_st_phys1_2,
s_st_phys1_3) <= transport
arr_st_phys1 ' (
(c_st_phys1_2,
c_st_phys1_2,
c_st_phys1_2) ) after 10 ns,
arr_st_phys1 ' (
(c_st_phys1_1,
c_st_phys1_1,
c_st_phys1_1) ) after 20 ns,
arr_st_phys1 ' (
(c_st_phys1_2,
c_st_phys1_2,
c_st_phys1_2) ) after 30 ns,
arr_st_phys1 ' (
(c_st_phys1_1,
c_st_phys1_1,
c_st_phys1_1) ) after 40 ns ;
--
when 3
=> correct :=
s_st_phys1_1 = c_st_phys1_2 and
s_st_phys1_2 = c_st_phys1_2 and
s_st_phys1_3 = c_st_phys1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_phys1_1,
s_st_phys1_2,
s_st_phys1_3) <= transport
arr_st_phys1 ' (
(c_st_phys1_1,
c_st_phys1_1,
c_st_phys1_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_phys1_1 = c_st_phys1_1 and
s_st_phys1_2 = c_st_phys1_1 and
s_st_phys1_3 = c_st_phys1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00633" ,
"One transport transaction occurred on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
test_report ( "ARCH00633" ,
"Old transactions were removed on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00633" ,
"Old transactions were removed on signal " &
"asg with aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_phys1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_st_phys1_1'EVENT and
s_st_phys1_2'EVENT and
s_st_phys1_3'EVENT ;
end process P9 ;
--
PGEN_CHKP_10 :
process ( chk_real )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Transport transactions entirely completed",
chk_real = 4 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
P10 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_real_1,
s_real_2,
s_real_3) <= transport
arr_real ' (
(c_real_2,
c_real_2,
c_real_2) ) after 10 ns,
arr_real ' (
(c_real_1,
c_real_1,
c_real_1) ) after 20 ns ;
--
when 1
=> correct :=
s_real_1 = c_real_2 and
s_real_2 = c_real_2 and
s_real_3 = c_real_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_real_1 = c_real_1 and
s_real_2 = c_real_1 and
s_real_3 = c_real_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00633.P10" ,
"Multi transport transactions occurred on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
(s_real_1,
s_real_2,
s_real_3) <= transport
arr_real ' (
(c_real_2,
c_real_2,
c_real_2) ) after 10 ns,
arr_real ' (
(c_real_1,
c_real_1,
c_real_1) ) after 20 ns,
arr_real ' (
(c_real_2,
c_real_2,
c_real_2) ) after 30 ns,
arr_real ' (
(c_real_1,
c_real_1,
c_real_1) ) after 40 ns ;
--
when 3
=> correct :=
s_real_1 = c_real_2 and
s_real_2 = c_real_2 and
s_real_3 = c_real_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_real_1,
s_real_2,
s_real_3) <= transport
arr_real ' (
(c_real_1,
c_real_1,
c_real_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_real_1 = c_real_1 and
s_real_2 = c_real_1 and
s_real_3 = c_real_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00633" ,
"One transport transaction occurred on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
test_report ( "ARCH00633" ,
"Old transactions were removed on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00633" ,
"Old transactions were removed on signal " &
"asg with aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_real <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_real_1'EVENT and
s_real_2'EVENT and
s_real_3'EVENT ;
end process P10 ;
--
PGEN_CHKP_11 :
process ( chk_st_real1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P11" ,
"Transport transactions entirely completed",
chk_st_real1 = 4 ) ;
end if ;
end process PGEN_CHKP_11 ;
--
P11 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_real1_1,
s_st_real1_2,
s_st_real1_3) <= transport
arr_st_real1 ' (
(c_st_real1_2,
c_st_real1_2,
c_st_real1_2) ) after 10 ns,
arr_st_real1 ' (
(c_st_real1_1,
c_st_real1_1,
c_st_real1_1) ) after 20 ns ;
--
when 1
=> correct :=
s_st_real1_1 = c_st_real1_2 and
s_st_real1_2 = c_st_real1_2 and
s_st_real1_3 = c_st_real1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real1_1 = c_st_real1_1 and
s_st_real1_2 = c_st_real1_1 and
s_st_real1_3 = c_st_real1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00633.P11" ,
"Multi transport transactions occurred on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
(s_st_real1_1,
s_st_real1_2,
s_st_real1_3) <= transport
arr_st_real1 ' (
(c_st_real1_2,
c_st_real1_2,
c_st_real1_2) ) after 10 ns,
arr_st_real1 ' (
(c_st_real1_1,
c_st_real1_1,
c_st_real1_1) ) after 20 ns,
arr_st_real1 ' (
(c_st_real1_2,
c_st_real1_2,
c_st_real1_2) ) after 30 ns,
arr_st_real1 ' (
(c_st_real1_1,
c_st_real1_1,
c_st_real1_1) ) after 40 ns ;
--
when 3
=> correct :=
s_st_real1_1 = c_st_real1_2 and
s_st_real1_2 = c_st_real1_2 and
s_st_real1_3 = c_st_real1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_real1_1,
s_st_real1_2,
s_st_real1_3) <= transport
arr_st_real1 ' (
(c_st_real1_1,
c_st_real1_1,
c_st_real1_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real1_1 = c_st_real1_1 and
s_st_real1_2 = c_st_real1_1 and
s_st_real1_3 = c_st_real1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00633" ,
"One transport transaction occurred on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
test_report ( "ARCH00633" ,
"Old transactions were removed on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00633" ,
"Old transactions were removed on signal " &
"asg with aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_real1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_st_real1_1'EVENT and
s_st_real1_2'EVENT and
s_st_real1_3'EVENT ;
end process P11 ;
--
PGEN_CHKP_12 :
process ( chk_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P12" ,
"Transport transactions entirely completed",
chk_st_rec1 = 4 ) ;
end if ;
end process PGEN_CHKP_12 ;
--
P12 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_rec1_1,
s_st_rec1_2,
s_st_rec1_3) <= transport
arr_st_rec1 ' (
(c_st_rec1_2,
c_st_rec1_2,
c_st_rec1_2) ) after 10 ns,
arr_st_rec1 ' (
(c_st_rec1_1,
c_st_rec1_1,
c_st_rec1_1) ) after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_1 = c_st_rec1_2 and
s_st_rec1_2 = c_st_rec1_2 and
s_st_rec1_3 = c_st_rec1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_1 = c_st_rec1_1 and
s_st_rec1_2 = c_st_rec1_1 and
s_st_rec1_3 = c_st_rec1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00633.P12" ,
"Multi transport transactions occurred on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
(s_st_rec1_1,
s_st_rec1_2,
s_st_rec1_3) <= transport
arr_st_rec1 ' (
(c_st_rec1_2,
c_st_rec1_2,
c_st_rec1_2) ) after 10 ns,
arr_st_rec1 ' (
(c_st_rec1_1,
c_st_rec1_1,
c_st_rec1_1) ) after 20 ns,
arr_st_rec1 ' (
(c_st_rec1_2,
c_st_rec1_2,
c_st_rec1_2) ) after 30 ns,
arr_st_rec1 ' (
(c_st_rec1_1,
c_st_rec1_1,
c_st_rec1_1) ) after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_1 = c_st_rec1_2 and
s_st_rec1_2 = c_st_rec1_2 and
s_st_rec1_3 = c_st_rec1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_rec1_1,
s_st_rec1_2,
s_st_rec1_3) <= transport
arr_st_rec1 ' (
(c_st_rec1_1,
c_st_rec1_1,
c_st_rec1_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_1 = c_st_rec1_1 and
s_st_rec1_2 = c_st_rec1_1 and
s_st_rec1_3 = c_st_rec1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00633" ,
"One transport transaction occurred on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
test_report ( "ARCH00633" ,
"Old transactions were removed on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00633" ,
"Old transactions were removed on signal " &
"asg with aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_st_rec1_1'EVENT and
s_st_rec1_2'EVENT and
s_st_rec1_3'EVENT ;
end process P12 ;
--
PGEN_CHKP_13 :
process ( chk_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P13" ,
"Transport transactions entirely completed",
chk_st_rec2 = 4 ) ;
end if ;
end process PGEN_CHKP_13 ;
--
P13 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_rec2_1,
s_st_rec2_2,
s_st_rec2_3) <= transport
arr_st_rec2 ' (
(c_st_rec2_2,
c_st_rec2_2,
c_st_rec2_2) ) after 10 ns,
arr_st_rec2 ' (
(c_st_rec2_1,
c_st_rec2_1,
c_st_rec2_1) ) after 20 ns ;
--
when 1
=> correct :=
s_st_rec2_1 = c_st_rec2_2 and
s_st_rec2_2 = c_st_rec2_2 and
s_st_rec2_3 = c_st_rec2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2_1 = c_st_rec2_1 and
s_st_rec2_2 = c_st_rec2_1 and
s_st_rec2_3 = c_st_rec2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00633.P13" ,
"Multi transport transactions occurred on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
(s_st_rec2_1,
s_st_rec2_2,
s_st_rec2_3) <= transport
arr_st_rec2 ' (
(c_st_rec2_2,
c_st_rec2_2,
c_st_rec2_2) ) after 10 ns,
arr_st_rec2 ' (
(c_st_rec2_1,
c_st_rec2_1,
c_st_rec2_1) ) after 20 ns,
arr_st_rec2 ' (
(c_st_rec2_2,
c_st_rec2_2,
c_st_rec2_2) ) after 30 ns,
arr_st_rec2 ' (
(c_st_rec2_1,
c_st_rec2_1,
c_st_rec2_1) ) after 40 ns ;
--
when 3
=> correct :=
s_st_rec2_1 = c_st_rec2_2 and
s_st_rec2_2 = c_st_rec2_2 and
s_st_rec2_3 = c_st_rec2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_rec2_1,
s_st_rec2_2,
s_st_rec2_3) <= transport
arr_st_rec2 ' (
(c_st_rec2_1,
c_st_rec2_1,
c_st_rec2_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2_1 = c_st_rec2_1 and
s_st_rec2_2 = c_st_rec2_1 and
s_st_rec2_3 = c_st_rec2_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00633" ,
"One transport transaction occurred on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
test_report ( "ARCH00633" ,
"Old transactions were removed on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00633" ,
"Old transactions were removed on signal " &
"asg with aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_st_rec2_1'EVENT and
s_st_rec2_2'EVENT and
s_st_rec2_3'EVENT ;
end process P13 ;
--
PGEN_CHKP_14 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P14" ,
"Transport transactions entirely completed",
chk_st_rec3 = 4 ) ;
end if ;
end process PGEN_CHKP_14 ;
--
P14 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_rec3_1,
s_st_rec3_2,
s_st_rec3_3) <= transport
arr_st_rec3 ' (
(c_st_rec3_2,
c_st_rec3_2,
c_st_rec3_2) ) after 10 ns,
arr_st_rec3 ' (
(c_st_rec3_1,
c_st_rec3_1,
c_st_rec3_1) ) after 20 ns ;
--
when 1
=> correct :=
s_st_rec3_1 = c_st_rec3_2 and
s_st_rec3_2 = c_st_rec3_2 and
s_st_rec3_3 = c_st_rec3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3_1 = c_st_rec3_1 and
s_st_rec3_2 = c_st_rec3_1 and
s_st_rec3_3 = c_st_rec3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00633.P14" ,
"Multi transport transactions occurred on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
(s_st_rec3_1,
s_st_rec3_2,
s_st_rec3_3) <= transport
arr_st_rec3 ' (
(c_st_rec3_2,
c_st_rec3_2,
c_st_rec3_2) ) after 10 ns,
arr_st_rec3 ' (
(c_st_rec3_1,
c_st_rec3_1,
c_st_rec3_1) ) after 20 ns,
arr_st_rec3 ' (
(c_st_rec3_2,
c_st_rec3_2,
c_st_rec3_2) ) after 30 ns,
arr_st_rec3 ' (
(c_st_rec3_1,
c_st_rec3_1,
c_st_rec3_1) ) after 40 ns ;
--
when 3
=> correct :=
s_st_rec3_1 = c_st_rec3_2 and
s_st_rec3_2 = c_st_rec3_2 and
s_st_rec3_3 = c_st_rec3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_rec3_1,
s_st_rec3_2,
s_st_rec3_3) <= transport
arr_st_rec3 ' (
(c_st_rec3_1,
c_st_rec3_1,
c_st_rec3_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3_1 = c_st_rec3_1 and
s_st_rec3_2 = c_st_rec3_1 and
s_st_rec3_3 = c_st_rec3_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00633" ,
"One transport transaction occurred on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
test_report ( "ARCH00633" ,
"Old transactions were removed on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00633" ,
"Old transactions were removed on signal " &
"asg with aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_st_rec3_1'EVENT and
s_st_rec3_2'EVENT and
s_st_rec3_3'EVENT ;
end process P14 ;
--
PGEN_CHKP_15 :
process ( chk_st_arr1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P15" ,
"Transport transactions entirely completed",
chk_st_arr1 = 4 ) ;
end if ;
end process PGEN_CHKP_15 ;
--
P15 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_arr1_1,
s_st_arr1_2,
s_st_arr1_3) <= transport
arr_st_arr1 ' (
(c_st_arr1_2,
c_st_arr1_2,
c_st_arr1_2) ) after 10 ns,
arr_st_arr1 ' (
(c_st_arr1_1,
c_st_arr1_1,
c_st_arr1_1) ) after 20 ns ;
--
when 1
=> correct :=
s_st_arr1_1 = c_st_arr1_2 and
s_st_arr1_2 = c_st_arr1_2 and
s_st_arr1_3 = c_st_arr1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1_1 = c_st_arr1_1 and
s_st_arr1_2 = c_st_arr1_1 and
s_st_arr1_3 = c_st_arr1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00633.P15" ,
"Multi transport transactions occurred on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
(s_st_arr1_1,
s_st_arr1_2,
s_st_arr1_3) <= transport
arr_st_arr1 ' (
(c_st_arr1_2,
c_st_arr1_2,
c_st_arr1_2) ) after 10 ns,
arr_st_arr1 ' (
(c_st_arr1_1,
c_st_arr1_1,
c_st_arr1_1) ) after 20 ns,
arr_st_arr1 ' (
(c_st_arr1_2,
c_st_arr1_2,
c_st_arr1_2) ) after 30 ns,
arr_st_arr1 ' (
(c_st_arr1_1,
c_st_arr1_1,
c_st_arr1_1) ) after 40 ns ;
--
when 3
=> correct :=
s_st_arr1_1 = c_st_arr1_2 and
s_st_arr1_2 = c_st_arr1_2 and
s_st_arr1_3 = c_st_arr1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_arr1_1,
s_st_arr1_2,
s_st_arr1_3) <= transport
arr_st_arr1 ' (
(c_st_arr1_1,
c_st_arr1_1,
c_st_arr1_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1_1 = c_st_arr1_1 and
s_st_arr1_2 = c_st_arr1_1 and
s_st_arr1_3 = c_st_arr1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00633" ,
"One transport transaction occurred on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
test_report ( "ARCH00633" ,
"Old transactions were removed on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00633" ,
"Old transactions were removed on signal " &
"asg with aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_st_arr1_1'EVENT and
s_st_arr1_2'EVENT and
s_st_arr1_3'EVENT ;
end process P15 ;
--
PGEN_CHKP_16 :
process ( chk_st_arr2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P16" ,
"Transport transactions entirely completed",
chk_st_arr2 = 4 ) ;
end if ;
end process PGEN_CHKP_16 ;
--
P16 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_arr2_1,
s_st_arr2_2,
s_st_arr2_3) <= transport
arr_st_arr2 ' (
(c_st_arr2_2,
c_st_arr2_2,
c_st_arr2_2) ) after 10 ns,
arr_st_arr2 ' (
(c_st_arr2_1,
c_st_arr2_1,
c_st_arr2_1) ) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2_1 = c_st_arr2_2 and
s_st_arr2_2 = c_st_arr2_2 and
s_st_arr2_3 = c_st_arr2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2_1 = c_st_arr2_1 and
s_st_arr2_2 = c_st_arr2_1 and
s_st_arr2_3 = c_st_arr2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00633.P16" ,
"Multi transport transactions occurred on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
(s_st_arr2_1,
s_st_arr2_2,
s_st_arr2_3) <= transport
arr_st_arr2 ' (
(c_st_arr2_2,
c_st_arr2_2,
c_st_arr2_2) ) after 10 ns,
arr_st_arr2 ' (
(c_st_arr2_1,
c_st_arr2_1,
c_st_arr2_1) ) after 20 ns,
arr_st_arr2 ' (
(c_st_arr2_2,
c_st_arr2_2,
c_st_arr2_2) ) after 30 ns,
arr_st_arr2 ' (
(c_st_arr2_1,
c_st_arr2_1,
c_st_arr2_1) ) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2_1 = c_st_arr2_2 and
s_st_arr2_2 = c_st_arr2_2 and
s_st_arr2_3 = c_st_arr2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_arr2_1,
s_st_arr2_2,
s_st_arr2_3) <= transport
arr_st_arr2 ' (
(c_st_arr2_1,
c_st_arr2_1,
c_st_arr2_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2_1 = c_st_arr2_1 and
s_st_arr2_2 = c_st_arr2_1 and
s_st_arr2_3 = c_st_arr2_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00633" ,
"One transport transaction occurred on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
test_report ( "ARCH00633" ,
"Old transactions were removed on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00633" ,
"Old transactions were removed on signal " &
"asg with aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_st_arr2_1'EVENT and
s_st_arr2_2'EVENT and
s_st_arr2_3'EVENT ;
end process P16 ;
--
PGEN_CHKP_17 :
process ( chk_st_arr3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P17" ,
"Transport transactions entirely completed",
chk_st_arr3 = 4 ) ;
end if ;
end process PGEN_CHKP_17 ;
--
P17 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_arr3_1,
s_st_arr3_2,
s_st_arr3_3) <= transport
arr_st_arr3 ' (
(c_st_arr3_2,
c_st_arr3_2,
c_st_arr3_2) ) after 10 ns,
arr_st_arr3 ' (
(c_st_arr3_1,
c_st_arr3_1,
c_st_arr3_1) ) after 20 ns ;
--
when 1
=> correct :=
s_st_arr3_1 = c_st_arr3_2 and
s_st_arr3_2 = c_st_arr3_2 and
s_st_arr3_3 = c_st_arr3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr3_1 = c_st_arr3_1 and
s_st_arr3_2 = c_st_arr3_1 and
s_st_arr3_3 = c_st_arr3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00633.P17" ,
"Multi transport transactions occurred on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
(s_st_arr3_1,
s_st_arr3_2,
s_st_arr3_3) <= transport
arr_st_arr3 ' (
(c_st_arr3_2,
c_st_arr3_2,
c_st_arr3_2) ) after 10 ns,
arr_st_arr3 ' (
(c_st_arr3_1,
c_st_arr3_1,
c_st_arr3_1) ) after 20 ns,
arr_st_arr3 ' (
(c_st_arr3_2,
c_st_arr3_2,
c_st_arr3_2) ) after 30 ns,
arr_st_arr3 ' (
(c_st_arr3_1,
c_st_arr3_1,
c_st_arr3_1) ) after 40 ns ;
--
when 3
=> correct :=
s_st_arr3_1 = c_st_arr3_2 and
s_st_arr3_2 = c_st_arr3_2 and
s_st_arr3_3 = c_st_arr3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_arr3_1,
s_st_arr3_2,
s_st_arr3_3) <= transport
arr_st_arr3 ' (
(c_st_arr3_1,
c_st_arr3_1,
c_st_arr3_1) ) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr3_1 = c_st_arr3_1 and
s_st_arr3_2 = c_st_arr3_1 and
s_st_arr3_3 = c_st_arr3_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00633" ,
"One transport transaction occurred on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
test_report ( "ARCH00633" ,
"Old transactions were removed on signal " &
"asg with aggregate of simple names on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00633" ,
"Old transactions were removed on signal " &
"asg with aggregate of simple names on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until s_st_arr3_1'EVENT and
s_st_arr3_2'EVENT and
s_st_arr3_3'EVENT ;
end process P17 ;
--
--
end ARCH00633 ;
--
entity ENT00633_Test_Bench is
end ENT00633_Test_Bench ;
--
architecture ARCH00633_Test_Bench of ENT00633_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00633 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00633_Test_Bench ;
| gpl-3.0 | 7c77974c40ba129c202c15e9d7c1babf | 0.469653 | 3.65227 | false | false | false | false |
takeshineshiro/fpga_fibre_scan | HUCB2P0_150701/frontend/fir_band_pass.vhd | 1 | 11,585 | -- megafunction wizard: %FIR Compiler v12.1%
-- GENERATION: XML
-- ============================================================
-- Megafunction Name(s):
-- fir_band_pass_ast
-- ============================================================
-- Generated by FIR Compiler 12.1 [Altera, IP Toolbench 1.3.0 Build 243]
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2013 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY fir_band_pass IS
PORT (
clk : IN STD_LOGIC;
reset_n : IN STD_LOGIC;
ast_sink_data : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
ast_sink_valid : IN STD_LOGIC;
ast_source_ready : IN STD_LOGIC;
ast_sink_error : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ast_source_data : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
ast_sink_ready : OUT STD_LOGIC;
ast_source_valid : OUT STD_LOGIC;
ast_source_error : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END fir_band_pass;
ARCHITECTURE SYN OF fir_band_pass IS
COMPONENT fir_band_pass_ast
PORT (
clk : IN STD_LOGIC;
reset_n : IN STD_LOGIC;
ast_sink_data : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
ast_sink_valid : IN STD_LOGIC;
ast_source_ready : IN STD_LOGIC;
ast_sink_error : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ast_source_data : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
ast_sink_ready : OUT STD_LOGIC;
ast_source_valid : OUT STD_LOGIC;
ast_source_error : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
BEGIN
fir_band_pass_ast_inst : fir_band_pass_ast
PORT MAP (
clk => clk,
reset_n => reset_n,
ast_sink_data => ast_sink_data,
ast_source_data => ast_source_data,
ast_sink_valid => ast_sink_valid,
ast_sink_ready => ast_sink_ready,
ast_source_valid => ast_source_valid,
ast_source_ready => ast_source_ready,
ast_sink_error => ast_sink_error,
ast_source_error => ast_source_error
);
END SYN;
-- =========================================================
-- FIR Compiler Wizard Data
-- ===============================
-- DO NOT EDIT FOLLOWING DATA
-- @Altera, IP Toolbench@
-- Warning: If you modify this section, FIR Compiler Wizard may not be able to reproduce your chosen configuration.
--
-- Retrieval info: <?xml version="1.0"?>
-- Retrieval info: <MEGACORE title="FIR Compiler" version="12.1" build="243" iptb_version="1.3.0 Build 243" format_version="120" >
-- Retrieval info: <NETLIST_SECTION class="altera.ipbu.flowbase.netlist.model.FIRModelClass" active_core="fir_band_pass_ast" >
-- Retrieval info: <STATIC_SECTION>
-- Retrieval info: <PRIVATES>
-- Retrieval info: <NAMESPACE name = "parameterization">
-- Retrieval info: <PRIVATE name = "use_mem" value="1" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_type" value="M512" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "filter_rate" value="Single Rate" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "filter_factor" value="2" type="INTEGER" enable="0" />
-- Retrieval info: <PRIVATE name = "coefficient_scaling_type" value="Auto" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "coefficient_scaling_factor" value="2663.965303912064" type="STRING" enable="0" />
-- Retrieval info: <PRIVATE name = "coefficient_bit_width" value="11" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "coefficient_binary_point_position" value="0" type="INTEGER" enable="0" />
-- Retrieval info: <PRIVATE name = "number_of_input_channels" value="1" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "input_number_system" value="Signed Binary" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "input_bit_width" value="12" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "input_binary_point_position" value="0" type="INTEGER" enable="0" />
-- Retrieval info: <PRIVATE name = "output_bit_width_method" value="Actual Coefficients" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "output_number_system" value="Custom Resolution" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "output_bit_width" value="16" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "output_bits_right_of_binary_point" value="16" type="INTEGER" enable="0" />
-- Retrieval info: <PRIVATE name = "output_bits_removed_from_lsb" value="9" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "output_lsb_remove_type" value="Truncate" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "output_msb_remove_type" value="Truncate" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "flow_control" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "flow_control_input" value="Slave Sink" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "flow_control_output" value="Master Source" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "device_family" value="Cyclone III" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "structure" value="Distributed Arithmetic : Fully Parallel Filter" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "pipeline_level" value="3" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "clocks_to_compute" value="1" type="INTEGER" enable="0" />
-- Retrieval info: <PRIVATE name = "number_of_serial_units" value="2" type="INTEGER" enable="0" />
-- Retrieval info: <PRIVATE name = "data_storage" value="Logic Cells" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "coefficient_storage" value="Logic Cells" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "multiplier_storage" value="Logic Cells" type="STRING" enable="0" />
-- Retrieval info: <PRIVATE name = "force_non_symmetric_structure" value="0" type="BOOLEAN" enable="0" />
-- Retrieval info: <PRIVATE name = "coefficients_reload" value="0" type="BOOLEAN" enable="0" />
-- Retrieval info: <PRIVATE name = "coefficients_reload_sgl_clock" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "max_clocks_to_compute" value="1" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "set_1" value="Low Pass Set, Floating, Band Pass, Hanning, 32, 1.5E8, 1.5E7, 5.5E7, 0, -1.12474E-4, 4.74116E-4, -0.00209712, -0.00527236, 9.87553E-4, -0.00989875, 0.00532489, 0.0263621, 0.0, 0.0480273, 0.0178911, -0.0654593, 0.0137166, -0.180396, -0.232389, 0.384014, 0.384014, -0.232389, -0.180396, 0.0137166, -0.0654593, 0.0178911, 0.0480273, 0.0, 0.0263621, 0.00532489, -0.00989875, 9.87553E-4, -0.00527236, -0.00209712, 4.74116E-4, -1.12474E-4" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "number_of_sets" value="1" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "output_full_bit_width" value="25" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "output_full_bits_right_of_binary_point" value="21" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "coefficient_reload_bit_width" value="14" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "logic_cell" value="2584" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "m512" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "m4k" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "m144k" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "m9k" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "m20k" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "mlab" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "megaram" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "dsp_block" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "input_clock_period" value="1" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "output_clock_period" value="1" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "throughput" value="1" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "memory_units" value="0" type="INTEGER" enable="1" />
-- Retrieval info: </NAMESPACE>
-- Retrieval info: <NAMESPACE name = "simgen_enable">
-- Retrieval info: <PRIVATE name = "matlab_enable" value="1" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "testbench_enable" value="1" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "testbench_simulation_clock_period" value="10.0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "language" value="VHDL" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "enabled" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: </NAMESPACE>
-- Retrieval info: <NAMESPACE name = "simgen">
-- Retrieval info: <PRIVATE name = "filename" value="fir_band_pass.vho" type="STRING" enable="1" />
-- Retrieval info: </NAMESPACE>
-- Retrieval info: <NAMESPACE name = "quartus_settings">
-- Retrieval info: <PRIVATE name = "DEVICE" value="EP2S60F672I4" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "FAMILY" value="Stratix II" type="STRING" enable="1" />
-- Retrieval info: </NAMESPACE>
-- Retrieval info: <NAMESPACE name = "serializer"/>
-- Retrieval info: </PRIVATES>
-- Retrieval info: <FILES/>
-- Retrieval info: <PORTS/>
-- Retrieval info: <LIBRARIES/>
-- Retrieval info: </STATIC_SECTION>
-- Retrieval info: </NETLIST_SECTION>
-- Retrieval info: </MEGACORE>
-- =========================================================
| apache-2.0 | 82f1d4a175cc4de17437d18cb8acee80 | 0.632715 | 3.245098 | false | false | false | false |
MrDoomBringer/DSD-Labs | Lab 10/TLC.vhd | 1 | 6,250 | -- FPGA Traffic Light Controller for Altera DE-2 board
-- Cliff Chapman
-- 11/04/2013
--
-- Lab 9 - Digital Systems Design
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_signed.ALL;
ENTITY tlc IS
PORT(
-- 50 mhz clock signal
clk : IN STD_LOGIC;
-- Reset signal
rst : IN STD_LOGIC;
-- Car occupancy sensor for side road
s_car : IN STD_LOGIC;
-- Main road lights, RED YELLOW GREEN m to l
m_light : OUT STD_LOGIC_VECTOR (2 DOWNTO 0) := "100";
-- Side road lights, RED YELLOW GREEN m to l
s_light : OUT STD_LOGIC_VECTOR (2 DOWNTO 0) := "001";
-- Delay time display
d_hex0 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
d_hex1 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
);
END tlc;
ARCHITECTURE rtl OF tlc IS
COMPONENT sevenseg_bcd_display
PORT (
r : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
s : IN STD_LOGIC := '1'; -- Select tied to '1' by default to show numeric values
HEX0, HEX1, HEX2 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
);
END COMPONENT;
-- State for main light loops
TYPE state_type IS
(m_row_s, m_row_lock_s, s_row_s
, main2side_s, side2main_s
);
SIGNAL state: state_type;
-- State for light transition
TYPE light_state_type IS
(main_g_side_r_s, main_r_side_g_s
, main_r_side_ry_s, main_ry_side_r_s
, main_y_side_r_s, main_r_side_y_s
);
SIGNAL state_light: light_state_type;
-- Timer display output
SIGNAL d_timer : STD_LOGIC_VECTOR (7 DOWNTO 0);
-- Target for timeout
SIGNAL timeout_limit : STD_LOGIC_VECTOR (7 DOWNTO 0);
-- Count for the clock divider
SIGNAL cnt: STD_LOGIC_VECTOR (26 DOWNTO 0) := "000000000000000000000000000";
-- 1 second clock
SIGNAL clock_1 : STD_LOGIC;
-- Timeout state for count timers
SIGNAL timeout : STD_LOGIC;
BEGIN
disp : sevenseg_bcd_display PORT MAP (
r => d_timer,
s => '1',
HEX2 => OPEN,
HEX1 => d_hex1,
HEX0 => d_hex0
);
clock_div: PROCESS (clk, cnt)
BEGIN
IF (rising_edge(clk)) THEN
IF (cnt >= "001111110000011110101111101") THEN
cnt <= "000000000000000000000000000";
clock_1 <= NOT clock_1;
ELSE
cnt <= cnt + '1';
END IF;
END IF;
END PROCESS clock_div;
state_monitor : PROCESS (state, clk, rst)
BEGIN
IF (rst = '0') THEN
state <= m_row_s;
ELSIF (rising_edge(clk) AND rst = '1') THEN
CASE state IS
WHEN m_row_s =>
IF (s_car = '1') THEN
state <= main2side_s;
ELSE
state <= m_row_s;
END IF;
WHEN main2side_s =>
IF (state_light = main_r_side_g_s) THEN
state <= s_row_s;
ELSE
state <= main2side_s;
END IF;
WHEN s_row_s =>
IF (timeout = '1') THEN
state <= side2main_s;
ELSE
state <= s_row_s;
END IF;
WHEN side2main_s =>
IF (state_light = main_g_side_r_s) THEN
state <= m_row_lock_s;
ELSE
state <= side2main_s;
END IF;
WHEN m_row_lock_s =>
IF (timeout = '1') THEN
state <= m_row_s;
ELSE
state <= m_row_lock_s;
END IF;
WHEN OTHERS =>
state <= m_row_s;
END CASE;
END IF;
END PROCESS state_monitor;
light_state_monitor : PROCESS (state, state_light, timeout, rst, clk)
BEGIN
IF (rst = '0') THEN
state_light <= main_g_side_r_s;
timeout_limit <= "00000000";
ELSIF (rising_edge(clk) AND rst = '1') THEN
IF (state = main2side_s) THEN
CASE state_light IS
WHEN main_g_side_r_s =>
state_light <= main_y_side_r_s;
WHEN main_y_side_r_s =>
timeout_limit <= "00001000";
IF (timeout = '1') THEN
timeout_limit <= "00001010";
state_light <= main_r_side_ry_s;
ELSE
state_light <= main_y_side_r_s;
END IF;
WHEN main_r_side_ry_s =>
IF (timeout = '1') THEN
state_light <= main_r_side_g_s;
ELSE
state_light <= main_r_side_ry_s;
END IF;
WHEN OTHERS =>
timeout_limit <= "ZZZZZZZZ";
END CASE;
ELSIF (state = side2main_s) THEN
CASE state_light IS
WHEN main_r_side_g_s =>
state_light <= main_r_side_y_s;
timeout_limit <= "00100110";
WHEN main_r_side_y_s =>
IF (timeout = '1') THEN
timeout_limit <= "00101000";
state_light <= main_ry_side_r_s;
ELSE
state_light <= main_r_side_y_s;
END IF;
WHEN main_ry_side_r_s =>
IF (timeout = '1') THEN
state_light <= main_g_side_r_s;
ELSE
state_light <= main_ry_side_r_s;
END IF;
WHEN OTHERS =>
timeout_limit <= "ZZZZZZZZ";
END CASE;
END IF;
END IF;
END PROCESS light_state_monitor;
timeout_counter : PROCESS (timeout_limit, clk, clock_1, rst, d_timer)
BEGIN
IF (timeout_limit = "00000000" OR rst = '0') THEN
d_timer <= "00000000";
ELSIF (rst = '1' AND timeout_limit /= "00000000" AND rising_edge(clock_1)) THEN
d_timer <= d_timer + '1';
ELSE
d_timer <= d_timer;
END IF;
END PROCESS timeout_counter;
timeout_monitor : PROCESS (d_timer, timeout_limit, rst)
BEGIN
IF (timeout_limit /= "00000000" AND rst = '1' AND d_timer >= timeout_limit) THEN
timeout <= '1';
ELSE
timeout <= '0';
END IF;
END PROCESS timeout_monitor;
output_monitor : PROCESS (state, state_light, rst)
BEGIN
IF (rst = '0') THEN
timeout_limit <= "00000000";
m_light <= "100";
s_light <= "001";
ELSE
CASE state IS
WHEN m_row_s =>
timeout_limit <= "00000000";
WHEN main2side_s =>
timeout_limit <= "ZZZZZZZZ";
WHEN s_row_s =>
timeout_limit <= "00011110";
WHEN side2main_s =>
timeout_limit <= "ZZZZZZZZ";
WHEN m_row_lock_s =>
timeout_limit <= "01000110";
WHEN OTHERS =>
timeout_limit <= "ZZZZZZZZ";
END CASE;
CASE state_light IS
WHEN main_g_side_r_s =>
m_light <= "100";
s_light <= "001";
WHEN main_y_side_r_s =>
m_light <= "010";
s_light <= "001";
WHEN main_r_side_g_s =>
m_light <= "001";
s_light <= "100";
WHEN main_r_side_ry_s =>
m_light <= "001";
s_light <= "011";
WHEN main_r_side_y_s =>
m_light <= "001";
s_light <= "010";
WHEN main_ry_side_r_s =>
m_light <= "011";
s_light <= "001";
WHEN OTHERS =>
m_light <= "001";
s_light <= "001";
END CASE;
END IF;
END PROCESS output_monitor;
END ARCHITECTURE; | mit | 715e2b3c8ff9da5bdd1ded89e3051f93 | 0.58352 | 2.771619 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00687.vhd | 1 | 28,802 | -- NEED RESULT: ARCH00687: Allocators with dynamic composite subtype indication passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00687
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.3.6 (2)
-- 7.3.6 (9)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00687)
-- ENT00687_Test_Bench(ARCH00687_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-SEP-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.test_report ;
architecture ARCH00687 of E00000 is
procedure p1 (
constant lowb : integer := 1 ;
constant highb : integer := 10 ;
constant lowb_i2 : integer := 0 ;
constant highb_i2 : integer := 1000 ;
constant lowb_p : integer := -100 ;
constant highb_p : integer := 1000 ;
constant lowb_r : real := 0.0 ;
constant highb_r : real := 1000.0 ;
constant lowb_r2 : real := 8.0 ;
constant highb_r2 : real := 80.0
--
) is
--
-- assertion: c_xxxxx_2 >= c_xxxxx_1
-- enumeration types
-- predefined
-- boolean
constant c_boolean_1 : boolean := false ;
constant c_boolean_2 : boolean := true ;
--
type boolean_vector is array (integer range <>) of boolean ;
subtype boolean_vector_range1 is integer range lowb to highb ;
subtype st_boolean_vector is boolean_vector (boolean_vector_range1) ;
constant c_st_boolean_vector_1 : st_boolean_vector :=
(others => c_boolean_1) ;
constant c_st_boolean_vector_2 : st_boolean_vector :=
(others => c_boolean_2) ;
--
-- bit
constant c_bit_1 : bit := '0' ;
constant c_bit_2 : bit := '1' ;
--
constant c_bit_vector_1 : bit_vector := B"0000" ;
constant c_bit_vector_2 : bit_vector := B"1111" ;
subtype bit_vector_range1 is integer range lowb to highb ;
subtype st_bit_vector is bit_vector (bit_vector_range1) ;
constant c_st_bit_vector_1 : st_bit_vector :=
(others => c_bit_1) ;
constant c_st_bit_vector_2 : st_bit_vector :=
(others => c_bit_2) ;
-- severity_level
constant c_severity_level_1 : severity_level := NOTE ;
constant c_severity_level_2 : severity_level := WARNING ;
--
type severity_level_vector is array (integer range <>) of severity_level ;
subtype severity_level_vector_range1 is integer range lowb to highb ;
subtype st_severity_level_vector is
severity_level_vector (severity_level_vector_range1) ;
constant c_st_severity_level_vector_1 : st_severity_level_vector :=
(others => c_severity_level_1) ;
constant c_st_severity_level_vector_2 : st_severity_level_vector :=
(others => c_severity_level_2) ;
--
-- character
constant c_character_1 : character := 'A' ;
constant c_character_2 : character := 'a' ;
--
constant c_string_1 : string := "ABC0000" ;
constant c_string_2 : string := "ABC1111" ;
subtype string_range1 is integer range lowb to highb ;
subtype st_string is string (string_range1) ;
constant c_st_string_1 : st_string :=
(others => c_character_1) ;
constant c_st_string_2 : st_string :=
(others => c_character_2) ;
-- user defined enumeration
type t_enum1 is (en1, en2, en3, en4) ;
constant c_t_enum1_1 : t_enum1 := en1 ;
constant c_t_enum1_2 : t_enum1 := en2 ;
subtype st_enum1 is t_enum1 range en4 downto en1 ;
constant c_st_enum1_1 : st_enum1 := en1 ;
constant c_st_enum1_2 : st_enum1 := en2 ;
--
type enum1_vector is array (integer range <>) of st_enum1 ;
subtype enum1_vector_range1 is integer range lowb to highb ;
subtype st_enum1_vector is enum1_vector (enum1_vector_range1) ;
constant c_st_enum1_vector_1 : st_enum1_vector :=
(others => c_st_enum1_1) ;
constant c_st_enum1_vector_2 : st_enum1_vector :=
(others => c_st_enum1_2) ;
-- integer types
-- predefined
constant c_integer_1 : integer := lowb ;
constant c_integer_2 : integer := highb ;
--
type integer_vector is array (integer range <>) of integer ;
subtype integer_vector_range1 is integer range lowb to highb ;
subtype st_integer_vector is integer_vector (integer_vector_range1) ;
constant c_st_integer_vector_1 : st_integer_vector :=
(others => c_integer_1) ;
constant c_st_integer_vector_2 : st_integer_vector :=
(others => c_integer_2) ;
--
-- user defined integer type
type t_int1 is range 0 to 100 ;
constant c_t_int1_1 : t_int1 := 0 ;
constant c_t_int1_2 : t_int1 := 10 ;
subtype st_int1 is t_int1 range 8 to 60 ;
constant c_st_int1_1 : st_int1 := 8 ;
constant c_st_int1_2 : st_int1 := 9 ;
--
type int1_vector is array (integer range <>) of st_int1 ;
subtype int1_vector_range1 is integer range lowb to highb ;
subtype st_int1_vector is int1_vector (int1_vector_range1) ;
constant c_st_int1_vector_1 : st_int1_vector :=
(others => c_st_int1_1) ;
constant c_st_int1_vector_2 : st_int1_vector :=
(others => c_st_int1_2) ;
--
-- physical types
-- predefined
constant c_time_1 : time := 1 ns ;
constant c_time_2 : time := 2 ns ;
--
type time_vector is array (integer range <>) of time ;
subtype time_vector_range1 is integer range lowb to highb ;
subtype st_time_vector is time_vector (time_vector_range1) ;
constant c_st_time_vector_1 : st_time_vector :=
(others => c_time_1) ;
constant c_st_time_vector_2 : st_time_vector :=
(others => c_time_2) ;
--
-- user defined physical type
type t_phys1 is range -100 to 1000
units
phys1_1 ;
phys1_2 = 10 phys1_1 ;
phys1_3 = 10 phys1_2 ;
phys1_4 = 10 phys1_3 ;
phys1_5 = 10 phys1_4 ;
end units ;
--
constant c_t_phys1_1 : t_phys1 := phys1_1 ;
constant c_t_phys1_2 : t_phys1 := phys1_2 ;
subtype st_phys1 is t_phys1 range phys1_2 to phys1_4 ;
constant c_st_phys1_1 : st_phys1 := phys1_2 ;
constant c_st_phys1_2 : st_phys1 := phys1_3 ;
--
type phys1_vector is array (integer range <>) of st_phys1 ;
subtype phys1_vector_range1 is integer range lowb to highb ;
subtype st_phys1_vector is phys1_vector (phys1_vector_range1) ;
constant c_st_phys1_vector_1 : st_phys1_vector :=
(others => c_st_phys1_1) ;
constant c_st_phys1_vector_2 : st_phys1_vector :=
(others => c_st_phys1_2) ;
--
--
-- floating point types
-- predefined
constant c_real_1 : real := 0.0 ;
constant c_real_2 : real := 1.0 ;
--
type real_vector is array (integer range <>) of real ;
subtype real_vector_range1 is integer range lowb to highb ;
subtype st_real_vector is real_vector (real_vector_range1) ;
constant c_st_real_vector_1 : st_real_vector :=
(others => c_real_1) ;
constant c_st_real_vector_2 : st_real_vector :=
(others => c_real_2) ;
--
-- user defined floating type
type t_real1 is range 0.0 to 1000.0 ;
constant c_t_real1_1 : t_real1 := 0.0 ;
constant c_t_real1_2 : t_real1 := 1.0 ;
subtype st_real1 is t_real1 range 8.0 to 80.0 ;
constant c_st_real1_1 : st_real1 := 8.0 ;
constant c_st_real1_2 : st_real1 := 9.0 ;
--
type real1_vector is array (integer range <>) of st_real1 ;
subtype real1_vector_range1 is integer range lowb to highb ;
subtype st_real1_vector is real1_vector (real1_vector_range1) ;
constant c_st_real1_vector_1 : st_real1_vector :=
(others => c_st_real1_1) ;
constant c_st_real1_vector_2 : st_real1_vector :=
(others => c_st_real1_2) ;
-- composite types
--
-- simple record
type t_rec1 is record
f1 : integer range lowb_i2 to highb_i2 ;
f2 : time ;
f3 : boolean ;
f4 : real ;
end record ;
constant c_t_rec1_1 : t_rec1 :=
(c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
constant c_t_rec1_2 : t_rec1 :=
(c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
subtype st_rec1 is t_rec1 ;
constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
--
type rec1_vector is array (integer range <>) of st_rec1 ;
subtype rec1_vector_range1 is integer range lowb to highb ;
subtype st_rec1_vector is rec1_vector (rec1_vector_range1) ;
constant c_st_rec1_vector_1 : st_rec1_vector :=
(others => c_st_rec1_1) ;
constant c_st_rec1_vector_2 : st_rec1_vector :=
(others => c_st_rec1_2) ;
--
--
-- more complex record
type t_rec2 is record
f1 : boolean ;
f2 : st_rec1 ;
f3 : time ;
end record ;
constant c_t_rec2_1 : t_rec2 :=
(c_boolean_1, c_st_rec1_1, c_time_1) ;
constant c_t_rec2_2 : t_rec2 :=
(c_boolean_2, c_st_rec1_2, c_time_2) ;
subtype st_rec2 is t_rec2 ;
constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
--
type rec2_vector is array (integer range <>) of st_rec2 ;
subtype rec2_vector_range1 is integer range lowb to highb ;
subtype st_rec2_vector is rec2_vector (rec2_vector_range1) ;
constant c_st_rec2_vector_1 : st_rec2_vector :=
(others => c_st_rec2_1) ;
constant c_st_rec2_vector_2 : st_rec2_vector :=
(others => c_st_rec2_2) ;
--
-- simple array
type t_arr1 is array (integer range <>) of st_int1 ;
subtype t_arr1_range1 is integer range lowb to highb ;
subtype st_arr1 is t_arr1 (t_arr1_range1) ;
constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ;
constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ;
--
type arr1_vector is array (integer range <>) of st_arr1 ;
subtype arr1_vector_range1 is integer range lowb to highb ;
subtype st_arr1_vector is arr1_vector (arr1_vector_range1) ;
constant c_st_arr1_vector_1 : st_arr1_vector :=
(others => c_st_arr1_1) ;
constant c_st_arr1_vector_2 : st_arr1_vector :=
(others => c_st_arr1_2) ;
-- more complex array
type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
subtype t_arr2_range1 is integer range lowb to highb ;
subtype t_arr2_range2 is boolean range false to true ;
subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ;
constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ;
--
type arr2_vector is array (integer range <>) of st_arr2 ;
subtype arr2_vector_range1 is integer range lowb to highb ;
subtype st_arr2_vector is arr2_vector (arr2_vector_range1) ;
constant c_st_arr2_vector_1 : st_arr2_vector :=
(others => c_st_arr2_1) ;
constant c_st_arr2_vector_2 : st_arr2_vector :=
(others => c_st_arr2_2) ;
--
--
-- most complex record
type t_rec3 is record
f1 : boolean ;
f2 : st_rec2 ;
f3 : st_arr2 ;
end record ;
constant c_t_rec3_1 : t_rec3 :=
(c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
constant c_t_rec3_2 : t_rec3 :=
(c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
subtype st_rec3 is t_rec3 ;
constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
--
type rec3_vector is array (integer range <>) of st_rec3 ;
subtype rec3_vector_range1 is integer range lowb to highb ;
subtype st_rec3_vector is rec3_vector (rec3_vector_range1) ;
constant c_st_rec3_vector_1 : st_rec3_vector :=
(others => c_st_rec3_1) ;
constant c_st_rec3_vector_2 : st_rec3_vector :=
(others => c_st_rec3_2) ;
--
-- most complex array
type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
subtype t_arr3_range1 is integer range lowb to highb ;
subtype t_arr3_range2 is boolean range true downto false ;
subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ;
constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ;
--
type arr3_vector is array (integer range <>) of st_arr3 ;
subtype arr3_vector_range1 is integer range lowb to highb ;
subtype st_arr3_vector is arr3_vector (arr3_vector_range1) ;
constant c_st_arr3_vector_1 : st_arr3_vector :=
(others => c_st_arr3_1) ;
constant c_st_arr3_vector_2 : st_arr3_vector :=
(others => c_st_arr3_2) ;
--
constant d_boolean : boolean := boolean'left ;
constant d_bit : bit := bit'left ;
constant d_severity_level : severity_level := severity_level'left ;
constant d_character : character := character'left ;
constant d_t_enum1 : t_enum1 := t_enum1'left ;
constant d_st_enum1 : st_enum1 := st_enum1'left ;
constant d_integer : integer := integer'left ;
constant d_t_int1 : t_int1 := t_int1'left ;
constant d_st_int1 : st_int1 := st_int1'left ;
constant d_time : time := time'left ;
constant d_t_phys1 : t_phys1 := t_phys1'left ;
constant d_st_phys1 : st_phys1 := st_phys1'left ;
constant d_real : real := real'left ;
constant d_t_real1 : t_real1 := t_real1'left ;
constant d_st_real1 : st_real1 := st_real1'left ;
constant d_st_bit_vector : st_bit_vector :=
(others => bit'left) ;
constant d_st_string : st_string :=
(others => character'left) ;
constant d_t_rec1 : t_rec1 :=
(lowb_i2, time'left, boolean'left, real'left) ;
constant d_st_rec1 : st_rec1 :=
(lowb_i2, time'left, boolean'left, real'left) ;
constant d_t_rec2 : t_rec2 :=
(boolean'left, d_st_rec1, time'left) ;
constant d_st_rec2 : st_rec2 :=
(boolean'left, d_st_rec1, time'left) ;
constant d_st_arr1 : st_arr1 :=
(others => st_int1'left) ;
constant d_st_arr2 : st_arr2 :=
(others => (others => d_st_arr1) ) ;
constant d_t_rec3 : t_rec3 :=
(boolean'left, d_st_rec2, d_st_arr2) ;
constant d_st_rec3 : st_rec3 :=
(boolean'left, d_st_rec2, d_st_arr2) ;
constant d_st_arr3 : st_arr3 :=
(others => (others => d_st_rec3) ) ;
-- enumeration types
-- predefined
-- boolean
function bf_boolean(to_resolve : boolean_vector) return boolean is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return boolean'left ;
else
for i in to_resolve'range loop
sum := sum + boolean'pos(to_resolve(i)) ;
end loop ;
return boolean'val(integer'pos(sum) mod
(boolean'pos(boolean'high) + 1)) ;
end if ;
end bf_boolean ;
--
--
-- bit
function bf_bit(to_resolve : bit_vector) return bit is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return bit'left ;
else
for i in to_resolve'range loop
sum := sum + bit'pos(to_resolve(i)) ;
end loop ;
return bit'val(integer'pos(sum) mod
(bit'pos(bit'high) + 1)) ;
end if ;
end bf_bit ;
--
-- severity_level
function bf_severity_level(to_resolve : severity_level_vector)
return severity_level is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return severity_level'left ;
else
for i in to_resolve'range loop
sum := sum + severity_level'pos(to_resolve(i)) ;
end loop ;
return severity_level'val(integer'pos(sum) mod
(severity_level'pos(severity_level'high) + 1)) ;
end if ;
end bf_severity_level ;
--
-- character
function bf_character(to_resolve : string) return character is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return character'left ;
else
for i in to_resolve'range loop
sum := sum + character'pos(to_resolve(i)) ;
end loop ;
return character'val(integer'pos(sum) mod
(character'pos(character'high) + 1)) ;
end if ;
end bf_character ;
--
--
-- user defined enumeration
function bf_enum1(to_resolve : enum1_vector) return st_enum1 is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return st_enum1'left ;
else
for i in to_resolve'range loop
sum := sum + t_enum1'pos(to_resolve(i)) ;
end loop ;
return t_enum1'val(integer'pos(sum) mod
(t_enum1'pos(t_enum1'high) + 1)) ;
end if ;
end bf_enum1 ;
--
--
-- integer types
-- predefined
function bf_integer(to_resolve : integer_vector) return integer is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return integer'left ;
else
for i in to_resolve'range loop
sum := sum + integer'pos(to_resolve(i)) ;
end loop ;
return sum ;
end if ;
end bf_integer ;
--
--
-- user defined integer type
function bf_int1(to_resolve : int1_vector) return st_int1 is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return st_int1'left ;
else
for i in to_resolve'range loop
sum := sum + t_int1'pos(to_resolve(i)) ;
end loop ;
return t_int1'val(integer'pos(sum) mod
(t_int1'pos(t_int1'high) + 1)) ;
end if ;
end bf_int1 ;
--
--
-- physical types
-- predefined
function bf_time(to_resolve : time_vector) return time is
variable sum : time := 0 fs;
begin
if to_resolve'length = 0 then
return time'left ;
else
for i in to_resolve'range loop
sum := sum + to_resolve(i) ;
end loop ;
return sum ;
end if ;
end bf_time ;
--
--
-- user defined physical type
function bf_phys1(to_resolve : phys1_vector) return st_phys1 is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return c_st_phys1_1 ;
else
for i in to_resolve'range loop
sum := sum + t_phys1'pos(to_resolve(i)) ;
end loop ;
return t_phys1'val(integer'pos(sum) mod
(t_phys1'pos(t_phys1'high) + 1)) ;
end if ;
end bf_phys1 ;
--
--
-- floating point types
-- predefined
function bf_real(to_resolve : real_vector) return real is
variable sum : real := 0.0 ;
begin
if to_resolve'length = 0 then
return real'left ;
else
for i in to_resolve'range loop
sum := sum + to_resolve(i) ;
end loop ;
return sum ;
end if ;
end bf_real ;
--
--
-- user defined floating type
function bf_real1(to_resolve : real1_vector) return st_real1 is
variable sum : t_real1 := 0.0 ;
begin
if to_resolve'length = 0 then
return c_st_real1_1 ;
else
for i in to_resolve'range loop
sum := sum + to_resolve(i) ;
end loop ;
return sum ;
end if ;
end bf_real1 ;
--
--
-- composite types
--
-- simple record
function bf_rec1(to_resolve : rec1_vector) return st_rec1 is
variable f1array : integer_vector (to_resolve'range) ;
variable f2array : time_vector (to_resolve'range) ;
variable f3array : boolean_vector (to_resolve'range) ;
variable f4array : real_vector (to_resolve'range) ;
variable result : st_rec1 ;
begin
if to_resolve'length = 0 then
return c_st_rec1_1 ;
else
for i in to_resolve'range loop
f1array(i) := to_resolve(i).f1 ;
f2array(i) := to_resolve(i).f2 ;
f3array(i) := to_resolve(i).f3 ;
f4array(i) := to_resolve(i).f4 ;
end loop ;
result.f1 := bf_integer(f1array) ;
result.f2 := bf_time(f2array) ;
result.f3 := bf_boolean(f3array) ;
result.f4 := bf_real(f4array) ;
return result ;
end if ;
end bf_rec1 ;
--
--
-- more complex record
function bf_rec2(to_resolve : rec2_vector) return st_rec2 is
variable f1array : boolean_vector (to_resolve'range) ;
variable f2array : rec1_vector (to_resolve'range) ;
variable f3array : time_vector (to_resolve'range) ;
variable result : st_rec2 ;
begin
if to_resolve'length = 0 then
return c_st_rec2_1 ;
else
for i in to_resolve'range loop
f1array(i) := to_resolve(i).f1 ;
f2array(i) := to_resolve(i).f2 ;
f3array(i) := to_resolve(i).f3 ;
end loop ;
result.f1 := bf_boolean(f1array) ;
result.f2 := bf_rec1(f2array) ;
result.f3 := bf_time(f3array) ;
return result ;
end if ;
end bf_rec2 ;
--
--
-- simple array
function bf_arr1(to_resolve : arr1_vector) return st_arr1 is
variable temp : int1_vector (to_resolve'range) ;
variable result : st_arr1 ;
begin
if to_resolve'length = 0 then
return c_st_arr1_1 ;
else
for i in st_arr1'range loop
for j in to_resolve'range(1) loop
temp(j) := to_resolve(j)(i) ;
end loop;
result(i) := bf_int1(temp) ;
end loop ;
return result ;
end if ;
end bf_arr1 ;
--
--
-- more complex array
function bf_arr2(to_resolve : arr2_vector) return st_arr2 is
variable temp : arr1_vector (to_resolve'range) ;
variable result : st_arr2 ;
begin
if to_resolve'length = 0 then
return c_st_arr2_1 ;
else
for i in st_arr2'range(1) loop
for j in st_arr2'range(2) loop
for k in to_resolve'range loop
temp(k) := to_resolve(k)(i,j) ;
end loop ;
result(i, j) := bf_arr1(temp) ;
end loop ;
end loop ;
return result ;
end if ;
end bf_arr2 ;
--
--
-- most complex record
function bf_rec3(to_resolve : rec3_vector) return st_rec3 is
variable f1array : boolean_vector (to_resolve'range) ;
variable f2array : rec2_vector (to_resolve'range) ;
variable f3array : arr2_vector (to_resolve'range) ;
variable result : st_rec3 ;
begin
if to_resolve'length = 0 then
return c_st_rec3_1 ;
else
for i in to_resolve'range loop
f1array(i) := to_resolve(i).f1 ;
f2array(i) := to_resolve(i).f2 ;
f3array(i) := to_resolve(i).f3 ;
end loop ;
result.f1 := bf_boolean(f1array) ;
result.f2 := bf_rec2(f2array) ;
result.f3 := bf_arr2(f3array) ;
return result ;
end if ;
end bf_rec3 ;
--
--
-- most complex array
function bf_arr3(to_resolve : arr3_vector) return st_arr3 is
variable temp : rec3_vector (to_resolve'range) ;
variable result : st_arr3 ;
begin
if to_resolve'length = 0 then
return c_st_arr3_1 ;
else
for i in st_arr3'range(1) loop
for j in st_arr3'range(2) loop
for k in to_resolve'range loop
temp(k) := to_resolve(k)(i,j) ;
end loop ;
result(i, j) := bf_rec3(temp) ;
end loop ;
end loop ;
return result ;
end if ;
end bf_arr3 ;
--
variable correct : boolean := true ;
type a_bit_vector is access bit_vector ;
variable va_bit_vector_1, va_bit_vector_2 : a_bit_vector
:= new st_bit_vector ;
type a_string is access string ;
variable va_string_1, va_string_2 : a_string
:= new st_string ;
type a_t_rec1 is access t_rec1 ;
variable va_t_rec1_1, va_t_rec1_2 : a_t_rec1
:= new st_rec1 ;
type a_st_rec1 is access st_rec1 ;
variable va_st_rec1_1, va_st_rec1_2 : a_st_rec1
:= new st_rec1 ;
type a_t_rec2 is access t_rec2 ;
variable va_t_rec2_1, va_t_rec2_2 : a_t_rec2
:= new st_rec2 ;
type a_st_rec2 is access st_rec2 ;
variable va_st_rec2_1, va_st_rec2_2 : a_st_rec2
:= new st_rec2 ;
type a_t_rec3 is access t_rec3 ;
variable va_t_rec3_1, va_t_rec3_2 : a_t_rec3
:= new st_rec3 ;
type a_st_rec3 is access st_rec3 ;
variable va_st_rec3_1, va_st_rec3_2 : a_st_rec3
:= new st_rec3 ;
type a_t_arr1 is access t_arr1 ;
variable va_t_arr1_1, va_t_arr1_2 : a_t_arr1
:= new st_arr1 ;
type a_st_arr1 is access st_arr1 ;
variable va_st_arr1_1, va_st_arr1_2 : a_st_arr1
:= new st_arr1 ;
type a_t_arr2 is access t_arr2 ;
variable va_t_arr2_1, va_t_arr2_2 : a_t_arr2
:= new st_arr2 ;
type a_st_arr2 is access st_arr2 ;
variable va_st_arr2_1, va_st_arr2_2 : a_st_arr2
:= new st_arr2 ;
type a_t_arr3 is access t_arr3 ;
variable va_t_arr3_1, va_t_arr3_2 : a_t_arr3
:= new st_arr3 ;
type a_st_arr3 is access st_arr3 ;
variable va_st_arr3_1, va_st_arr3_2 : a_st_arr3
:= new st_arr3 ;
begin
correct := correct and
va_bit_vector_1.all = d_st_bit_vector ;
correct := correct and
va_string_1.all = d_st_string ;
correct := correct and
va_t_rec1_1.all = d_st_rec1 ;
correct := correct and
va_st_rec1_1.all = d_st_rec1 ;
correct := correct and
va_t_rec2_1.all = d_st_rec2 ;
correct := correct and
va_st_rec2_1.all = d_st_rec2 ;
correct := correct and
va_t_rec3_1.all = d_st_rec3 ;
correct := correct and
va_st_rec3_1.all = d_st_rec3 ;
correct := correct and
va_t_arr1_1.all = d_st_arr1 ;
correct := correct and
va_st_arr1_1.all = d_st_arr1 ;
correct := correct and
va_t_arr2_1.all = d_st_arr2 ;
correct := correct and
va_st_arr2_1.all = d_st_arr2 ;
correct := correct and
va_t_arr3_1.all = d_st_arr3 ;
correct := correct and
va_st_arr3_1.all = d_st_arr3 ;
test_report ( "ARCH00687" ,
"Allocators with dynamic composite subtype indication" ,
correct) ;
end p1 ;
begin
process
begin
p1 ;
wait ;
end process ;
end ARCH00687 ;
--
entity ENT00687_Test_Bench is
end ENT00687_Test_Bench ;
--
architecture ARCH00687_Test_Bench of ENT00687_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00687 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00687_Test_Bench ;
| gpl-3.0 | 911a9bbb6e3cd4f7860be74379e96b63 | 0.539199 | 3.202357 | false | false | false | false |
wsoltys/AtomFpga | src/AVR8/uC/AVR8.vhd | 1 | 33,368 | --************************************************************************************************
-- Top entity for AVR microcontroller (for synthesis) with JTAG OCD and DMAs
-- Version 0.5 (Version for Xilinx)
-- Designed by Ruslan Lepetenok
-- Modified 31.05.2006
--************************************************************************************************
--************************************************************************************************
-- Adapted for AtomFPGA
-- input clock is now 16MHz
--************************************************************************************************
--************************************************************************************************
--Adapted for the Papilio FPGA development board. To learn more visit http://papilio.cc
--Gadget Factory Note: This project is currently configured for the Papilio One board Version 2.03 or greater. It assumes a 32Mhz oscillator and a ucf with a period of 31.25.
--*************************************************************************************************
--*************************************************************************************************
--This is AVR8-based SoC for processing diode signals
--modifications by Zvonimir Bandic
--modified 01/05/2013
--*************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use WORK.AVRuCPackage.all;
use WORK.AVR_uC_CompPack.all;
use WORK.SynthCtrlPack.all; -- Synthesis control
use WORK.XMemCompPack.all; -- Xilinx RAM components
use WORK.spi_mod_comp_pack.all; --SPI
use WORK.spi_slv_sel_comp_pack.all;
use WORK.MemAccessCtrlPack.all;
use WORK.MemAccessCompPack.all;
entity AVR8 is port(
nrst : in std_logic; --Uncomment this to connect reset to an external pushbutton. Must be defined in ucf.
clk16M : in std_logic;
portaout : out std_logic_vector(7 downto 0);
portain : in std_logic_vector(7 downto 0);
portbout : out std_logic_vector(7 downto 0);
portbin : in std_logic_vector(7 downto 0);
portc : inout std_logic_vector(7 downto 0);
portdin : in std_logic_vector(7 downto 0);
portdout : out std_logic_vector(7 downto 0);
porte : inout std_logic_vector(7 downto 0);
portf : inout std_logic_vector(7 downto 0);
spi_mosio : out std_logic;
spi_scko : out std_logic;
spi_cs_n : out std_logic;
spi_misoi : in std_logic;
-- UART
rxd : in std_logic;
txd : out std_logic
);
end AVR8;
architecture Struct of AVR8 is
-- Use these setting to control which peripherals you want to include with your custom AVR8 implementation.
constant CImplPORTA : boolean := TRUE; -- set to false here for portA and portB, or DDRAreg and DDRBreg
constant CImplPORTB : boolean := TRUE;
constant CImplPORTC : boolean := FALSE;
constant CImplPORTD : boolean := TRUE;
constant CImplPORTE : boolean := FALSE;
constant CImplPORTF : boolean := FALSE;
constant CImplUART : boolean := TRUE; --AVR8 UART peripheral
constant CImplSPI : boolean := TRUE; -- adding SPI master
constant CImplTmrCnt : boolean := FALSE; --AVR8 Timer
constant CImplExtIRQ : boolean := TRUE; --AVR8 Interrupt Unit
component XDM4Kx8 port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(CDATAMEMSIZE downto 0);
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0);
we : in std_logic
);
end component;
component XPM10Kx16 port(
--component XPM8Kx16 port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(13 downto 0);
-- address : in std_logic_vector(CPROGMEMSIZE downto 0);
din : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(15 downto 0);
we : in std_logic
);
end component;
-- ############################## Define Components for User Cores ##################################################
-- ###############################################################################################################
-- ############################## Signals connected directly to the core ##########################################
signal core_cpuwait : std_logic;
-- Program memory
signal core_pc : std_logic_vector (15 downto 0); -- PROM address
signal core_inst : std_logic_vector (15 downto 0); -- PROM data
-- I/O registers
signal core_adr : std_logic_vector (15 downto 0);
signal core_iore : std_logic;
signal core_iowe : std_logic;
-- Data memery
signal core_ramadr : std_logic_vector (15 downto 0);
signal core_ramre : std_logic;
signal core_ramwe : std_logic;
signal core_dbusin : std_logic_vector (7 downto 0);
signal core_dbusout : std_logic_vector (7 downto 0);
-- Interrupts
signal core_irqlines : std_logic_vector(22 downto 0);
signal core_irqack : std_logic;
signal core_irqackad : std_logic_vector(4 downto 0);
-- ###############################################################################################################
-- ############################## Signals connected directly to the SRAM controller ###############################
signal ram_din : std_logic_vector(7 downto 0);
-- ###############################################################################################################
-- ####################### Signals connected directly to the external multiplexer ################################
signal io_port_out : ext_mux_din_type;
signal io_port_out_en : ext_mux_en_type;
signal ind_irq_ack : std_logic_vector(core_irqlines'range);
-- ###############################################################################################################
-- ################################## Reset signals #############################################
signal core_ireset : std_logic;
-- ##############################################################################################
-- Port signals
signal PortAReg : std_logic_vector(portain'range);
signal DDRAReg : std_logic_vector(portain'range);
signal PortBReg : std_logic_vector(portbin'range);
signal DDRBReg : std_logic_vector(portbin'range);
signal PortCReg : std_logic_vector(portc'range);
signal DDRCReg : std_logic_vector(portc'range);
signal PortDReg : std_logic_vector(portdin'range);
signal DDRDReg : std_logic_vector(portdin'range);
signal PortEReg : std_logic_vector(porte'range);
signal DDREReg : std_logic_vector(porte'range);
signal PortFReg : std_logic_vector(portf'range);
signal DDRFReg : std_logic_vector(portf'range);
-- Added for Synopsys compatibility
signal gnd : std_logic;
signal vcc : std_logic;
-- Sleep support
signal core_cp2 : std_logic; -- Global clock signal after gating(and global primitive)
signal sleep_en : std_logic;
signal sleepi : std_logic;
signal irqok : std_logic;
signal globint : std_logic;
signal nrst_clksw : std_logic; -- Separate reset for clock gating module
-- Watchdog related signals
signal wdtmout : std_logic; -- Watchdog overflow
signal core_wdri : std_logic; -- Watchdog clear
-- ********************** JTAG and memory **********************************************
-- PM address,data and control
signal pm_adr : std_logic_vector(core_pc'range);
signal pm_h_we : std_logic;
signal pm_l_we : std_logic;
signal pm_din : std_logic_vector(core_inst'range);
signal pm_dout : std_logic_vector(core_inst'range);
signal TDO_Out : std_logic;
signal TDO_OE : std_logic;
signal JTAG_Rst : std_logic;
-- ********************** JTAG and memory **********************************************
signal nrst_cp64m_tmp : std_logic;
signal ram_cp2_n : std_logic;
signal sleep_mode : std_logic;
-- "EEPROM" related signals
signal EEPrgSel : std_logic;
signal EEAdr : std_logic_vector(11 downto 0);
signal EEWrData : std_logic_vector(7 downto 0);
signal EERdData : std_logic_vector(7 downto 0);
signal EEWr : std_logic;
-- New
signal busmin : MastersOutBus_Type;
signal busmwait : std_logic_vector(CNumOfBusMasters-1 downto 0) := (others => '0');
signal slv_outs : SlavesOutBus_Type;
signal ram_sel : std_logic;
-- UART DMA
signal udma_mack : std_logic;
signal mem_mux_out : std_logic_vector (7 downto 0);
-- Place Holder Signals for JTAG instead of connecting them externally
signal TRSTn : std_logic;
signal TMS : std_logic;
signal TCK : std_logic;
signal TDI : std_logic;
signal TDO : std_logic;
-- AES
signal aes_mack : std_logic;
-- Address decoder
signal stb_IO : std_logic;
signal stb_IOmod : std_logic_vector (CNumOfSlaves-1 downto 0);
signal ram_ce : std_logic;
signal slv_cpuwait : std_logic;
-- Memory i/f
signal mem_ramadr : std_logic_vector (15 downto 0);
signal mem_ram_dbus_in : std_logic_vector (7 downto 0);
signal mem_ram_dbus_out : std_logic_vector (7 downto 0);
signal mem_ramwe : std_logic;
signal mem_ramre : std_logic;
-- RAM
signal ram_ramwe : std_logic;
-- nrst
--signal nrst : std_logic; --Comment this to connect reset to an external pushbutton.
-- ############################## Signals connected directly to the I/O registers ################################
-- PortA
signal porta_dbusout : std_logic_vector (7 downto 0);
signal porta_out_en : std_logic;
-- PortB
signal portb_dbusout : std_logic_vector (7 downto 0);
signal portb_out_en : std_logic;
-- PortC
signal portc_dbusout : std_logic_vector (7 downto 0);
signal portc_out_en : std_logic;
-- PortD
signal portd_dbusout : std_logic_vector (7 downto 0);
signal portd_out_en : std_logic;
-- PortE
signal porte_dbusout : std_logic_vector (7 downto 0);
signal porte_out_en : std_logic;
-- PortF
signal portf_dbusout : std_logic_vector (7 downto 0);
signal portf_out_en : std_logic;
-- Timer/Counter
signal tc_dbusout : std_logic_vector (7 downto 0);
signal tc_out_en : std_logic;
-- Ext IRQ Controller
signal extirq_dbusout : std_logic_vector (7 downto 0);
signal extirq_out_en : std_logic;
signal ext_irqlines : std_logic_vector(7 downto 0);
-- UART
signal uart_dbusout : std_logic_vector (7 downto 0);
signal uart_out_en : std_logic;
-- SPI
constant c_spi_slvs_num : integer := 1;
--signal spi_misoi : std_logic;
signal spi_mosii : std_logic;
signal spi_scki : std_logic;
signal spi_ss_b : std_logic;
signal spi_misoo : std_logic;
--signal spi_mosio : std_logic;
--signal spi_scko : std_logic;
signal spi_spe : std_logic;
signal spi_spimaster : std_logic;
signal spi_dbusout : std_logic_vector (7 downto 0);
signal spi_out_en : std_logic;
-- Slave selects
signal spi_slv_sel_n : std_logic_vector(c_spi_slvs_num-1 downto 0);
-- SPI
-- ###############################################################################################################
-- ############################## Define Signals for User Cores ##################################################
-- Example Core - - core9
--signal core9_input_sig : std_logic_vector(1 downto 0); --Define a signal for the inputs.
-- ###############################################################################################################
begin
-- Added for Synopsys compatibility
gnd <= '0';
vcc <= '1';
-- Added for Synopsys compatibility
--nrst <= '1'; --Comment this to connect reset to an external pushbutton.
core_inst <= pm_dout;
--Signals to connect peripherals controlled from Generics to the physical ports
-- ****************** User Cores - Instantiate User Cores Here **************************
-- ****************** END User Cores - Instantiate User Cores Here **************************
-- Unused IRQ lines
--core_irqlines(7 downto 4) <= ( others => '0');
--core_irqlines(3 downto 0) <= ( others => '0');
core_irqlines(13 downto 10) <= ( others => '0');
--core_irqlines(16) <= '0'; --now used by SPI
core_irqlines(22 downto 20) <= ( others => '0');
-- ************************
-- Unused out_en
io_port_out_en(11 to 15) <= (others => '0');
io_port_out(11 to 15) <= (others => (others => '0'));
AVR_Core_Inst:component AVR_Core port map(
--Clock and reset
cp2 => core_cp2,
cp2en => vcc,
ireset => core_ireset,
-- JTAG OCD support
valid_instr => open,
insert_nop => gnd,
block_irq => gnd,
change_flow => open,
-- Program Memory
pc => core_pc,
inst => core_inst,
-- I/O control
adr => core_adr,
iore => core_iore,
iowe => core_iowe,
-- Data memory control
ramadr => core_ramadr,
ramre => core_ramre,
ramwe => core_ramwe,
cpuwait => core_cpuwait,
-- Data paths
dbusin => core_dbusin,
dbusout => core_dbusout,
-- Interrupts
irqlines => core_irqlines,
irqack => core_irqack,
irqackad => core_irqackad,
--Sleep Control
sleepi => sleepi,
irqok => irqok,
globint => globint,
--Watchdog
wdri => core_wdri);
RAM_Data_Register:component RAMDataReg port map(
ireset => core_ireset,
cp2 => clk16M, -- clk,
cpuwait => core_cpuwait,
RAMDataIn => core_dbusout,
RAMDataOut => ram_din
);
EXT_MUX:component external_mux port map(
ramre => mem_ramre, -- ramre output of the arbiter and multiplexor
dbus_out => core_dbusin, -- Data input of the core
ram_data_out => mem_mux_out, -- Data output of the RAM mux(RAM or memory located I/O)
io_port_bus => io_port_out, -- Data outputs of the I/O
io_port_en_bus => io_port_out_en, -- Out enable outputs of I/O
irqack => core_irqack,
irqackad => core_irqackad,
ind_irq_ack => ind_irq_ack -- Individual interrupt acknolege for the peripheral
);
-- ****************** PORTA **************************
PORTA_Impl:if CImplPORTA generate
PORTA_COMP:component pport
generic map(PPortNum => 0)
port map(
-- AVR Control
ireset => core_ireset,
cp2 => clk16M, -- clk,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => porta_dbusout,
iore => core_iore,
iowe => core_iowe,
out_en => porta_out_en,
-- External connection
portx => PortAReg,
ddrx => DDRAReg,
pinx => portain,
irqlines => open);
-- PORTA connection to the external multiplexer
io_port_out(0) <= porta_dbusout;
io_port_out_en(0) <= porta_out_en;
---- Tri-state control for PORTA
--PortAZCtrl:for i in porta'range generate
--porta(i) <= PortAReg(i) when DDRAReg(i)='1' else 'Z';
--end generate;
-- Tri-state control for PORTA
PortAZCtrl:for i in portaout'range generate
portaout(i) <= PortAReg(i) when DDRAReg(i)='1' else '0';
end generate;
end generate;
PORTA_Not_Impl:if not CImplPORTA generate
portaout <= (others => '0');
end generate;
-- ****************** PORTB **************************
PORTB_Impl:if CImplPORTB generate
PORTB_COMP:component pport
generic map (PPortNum => 1)
port map(
-- AVR Control
ireset => core_ireset,
cp2 => clk16M, -- clk,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => portb_dbusout,
iore => core_iore,
iowe => core_iowe,
out_en => portb_out_en,
-- External connection
portx => PortBReg,
ddrx => DDRBReg,
pinx => portbin,
irqlines => ext_irqlines);
-- PORTB connection to the external multiplexer
io_port_out(1) <= portb_dbusout;
io_port_out_en(1) <= portb_out_en;
---- Tri-state control for PORTB
--PortBZCtrl:for i in portb'range generate
--portb(i) <= PortBReg(i) when DDRBReg(i)='1' else 'Z';
--end generate;
-- Tri-state control for PORTB
PortBZCtrl:for i in portbout'range generate
--portb(i) <= PortBReg(i) when DDRBReg(i)='1' else 'Z';
portbout(i) <= PortBReg(i) when DDRBReg(i)='1' else '0';
end generate;
end generate;
PORTB_Not_Impl:if not CImplPORTB generate
portbout <= (others => '0');
end generate;
-- ************************************************
-- ****************** PORTC **************************
PORTC_Impl:if CImplPORTC generate
PORTC_COMP:component pport
generic map(PPortNum => 2)
port map(
-- AVR Control
ireset => core_ireset,
cp2 => clk16M, -- clk,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => portc_dbusout,
iore => core_iore,
iowe => core_iowe,
out_en => portc_out_en,
-- External connection
portx => PortCReg,
ddrx => DDRCReg,
pinx => portc,
irqlines => open);
-- PORTC connection to the external multiplexer
io_port_out(5) <= portc_dbusout;
io_port_out_en(5) <= portc_out_en;
---- Tri-state control for PORTC
--PortCZCtrl:for i in portc'range generate
--portc(i) <= PortCReg(i) when DDRCReg(i)='1' else 'Z';
--end generate;
-- Tri-state control for PORTC
PortCZCtrl:for i in portc'range generate
portc(i) <= PortCReg(i) when DDRCReg(i)='1' else 'Z';
end generate;
end generate;
PORTC_Not_Impl:if not CImplPORTC generate
portc <= (others => 'Z');
end generate;
-- ****************** PORTD **************************
PORTD_Impl:if CImplPORTD generate
PORTD_COMP:component pport
generic map (PPortNum => 3)
port map(
-- AVR Control
ireset => core_ireset,
cp2 => clk16M, -- clk,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => portd_dbusout,
iore => core_iore,
iowe => core_iowe,
out_en => portd_out_en,
-- External connection
portx => PortDReg,
ddrx => DDRDReg,
pinx => portdin,
irqlines => open);
-- PORTD connection to the external multiplexer
io_port_out(6) <= portd_dbusout;
io_port_out_en(6) <= portd_out_en;
---- Tri-state control for PORTD
--PortDZCtrl:for i in portd'range generate
--portd(i) <= PortDReg(i) when DDRDReg(i)='1' else 'Z';
--end generate;
-- Tri-state control for PORTD
PortDZCtrl:for i in portdout'range generate
portdout(i) <= PortDReg(i) when DDRDReg(i)='1' else '0';
end generate;
end generate;
PORTD_Not_Impl:if not CImplPORTD generate
portdout <= (others => '0');
end generate;
-- ************************************************
-- ****************** PORTE **************************
PORTE_Impl:if CImplPORTE generate
PORTE_COMP:component pport
generic map(PPortNum => 4)
port map(
-- AVR Control
ireset => core_ireset,
cp2 => clk16M, -- clk,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => porte_dbusout,
iore => core_iore,
iowe => core_iowe,
out_en => porte_out_en,
-- External connection
portx => PortEReg,
ddrx => DDREReg,
pinx => porte,
irqlines => open);
-- PORTE connection to the external multiplexer
io_port_out(7) <= porte_dbusout;
io_port_out_en(7) <= porte_out_en;
---- Tri-state control for PORTE
--PortEZCtrl:for i in porte'range generate
--porte(i) <= PortEReg(i) when DDREReg(i)='1' else 'Z';
--end generate;
-- Tri-state control for PORTE
PortEZCtrl:for i in porte'range generate
porte(i) <= PortEReg(i) when DDREReg(i)='1' else 'Z';
end generate;
end generate;
PORTE_Not_Impl:if not CImplPORTE generate
porte <= (others => 'Z');
end generate;
-- ****************** PORTF **************************
PORTF_Impl:if CImplPORTF generate
PORTF_COMP:component pport
generic map (PPortNum => 5)
port map(
-- AVR Control
ireset => core_ireset,
cp2 => clk16M, -- clk,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => portf_dbusout,
iore => core_iore,
iowe => core_iowe,
out_en => portf_out_en,
-- External connection
portx => PortFReg,
ddrx => DDRFReg,
pinx => portf,
irqlines => open);
-- PORTF connection to the external multiplexer
io_port_out(8) <= portf_dbusout;
io_port_out_en(8) <= portf_out_en;
-- Tri-state control for PORTF
PortFZCtrl:for i in portf'range generate
portf(i) <= PortFReg(i) when DDRFReg(i)='1' else 'Z';
end generate;
end generate;
PORTF_Not_Impl:if not CImplPORTF generate
portf <= (others => 'Z');
end generate;
-- ************************************************
--****************** External IRQ Controller**************************
ExtIRQ_Impl:if CImplExtIRQ generate
ExtIRQ_Inst:component ExtIRQ_Controller port map(
-- AVR Control
nReset => core_ireset,
clk => clk16M, -- clk,
clken => vcc,
irq_clken => vcc,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => extirq_dbusout,
iore => core_iore,
iowe => core_iowe,
out_en => extirq_out_en,
------------------------------------------------
extpins => ext_irqlines,
INTx => core_irqlines(7 downto 0));
-- ExtIRQ connection to the external multiplexer
io_port_out(10) <= extirq_dbusout;
io_port_out_en(10) <= extirq_out_en;
end generate;
--****************** Timer/Counter **************************
TmrCnt_Impl:if CImplTmrCnt generate
TmrCnt_Inst:component Timer_Counter port map(
-- AVR Control
ireset => core_ireset,
cp2 => clk16M, -- clk,
cp2en => vcc,
tmr_cp2en => vcc,
stopped_mode => gnd,
tmr_running => gnd,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => tc_dbusout,
iore => core_iore,
iowe => core_iowe,
out_en => tc_out_en,
-- External inputs/outputs
EXT1 => gnd,
EXT2 => gnd,
OC0_PWM0 => open,
OC1A_PWM1A => open,
OC1B_PWM1B => open,
OC2_PWM2 => open,
-- Interrupt related signals
TC0OvfIRQ => core_irqlines(15), -- Timer/Counter0 overflow ($0020)
TC0OvfIRQ_Ack => ind_irq_ack(15),
TC0CmpIRQ => core_irqlines(14), -- Timer/Counter0 Compare Match ($001E)
TC0CmpIRQ_Ack => ind_irq_ack(14),
TC2OvfIRQ => core_irqlines(9), -- Timer/Counter2 overflow ($0014)
TC2OvfIRQ_Ack => ind_irq_ack(9),
TC2CmpIRQ => core_irqlines(8), -- Timer/Counter2 Compare Match ($0012)
TC2CmpIRQ_Ack => ind_irq_ack(8),
TC1OvfIRQ => open,
TC1OvfIRQ_Ack => gnd,
TC1CmpAIRQ => open,
TC1CmpAIRQ_Ack => gnd,
TC1CmpBIRQ => open,
TC1CmpBIRQ_Ack => gnd,
TC1ICIRQ => open,
TC1ICIRQ_Ack => gnd,
PWM0bit => open,
PWM10bit => open,
PWM11bit => open,
PWM2bit => open);
-- Timer/Counter connection to the external multiplexer
io_port_out(4) <= tc_dbusout;
io_port_out_en(4) <= tc_out_en;
end generate;
-- Watchdog is not implemented
wdtmout <= '0';
-- Reset generator
ResetGenerator_Inst:component ResetGenerator port map(
-- Clock inputs
cp2 => clk16M, -- clk,
cp64m => gnd,
-- Reset inputs
nrst => nrst,
npwrrst => vcc,
wdovf => wdtmout,
jtagrst => JTAG_Rst,
-- Reset outputs
nrst_cp2 => core_ireset,
nrst_cp64m => nrst_cp64m_tmp,
nrst_clksw => nrst_clksw
);
ClockGatingDis:if not CImplClockSw generate
core_cp2 <= clk16M;
end generate;
-- ********************** JTAG and memory **********************************************
ram_cp2_n <= not clk16M;
---- Data memory(8-bit)
DRAM_Inst:component XDM4Kx8
port map(
cp2 => ram_cp2_n,
ce => vcc,
address => mem_ramadr(CDATAMEMSIZE downto 0),
din => mem_ram_dbus_in,
dout => mem_ram_dbus_out,
we => ram_ramwe
);
-- Program memory
PM_Inst:component XPM10Kx16
--PM_Inst:component XPM8Kx16
port map(
cp2 => ram_cp2_n,
ce => vcc,
address => pm_adr(13 downto 0),
-- address => pm_adr(CPROGMEMSIZE downto 0),
din => pm_din,
dout => pm_dout,
we => pm_l_we
);
-- ********************** JTAG and memory **********************************************
-- Sleep mode is not implemented
sleep_mode <= '0';
JTAGOCDPrgTop_Inst:component JTAGOCDPrgTop port map(
-- AVR Control
ireset => core_ireset,
cp2 => core_cp2,
-- JTAG related inputs/outputs
TRSTn => TRSTn, -- Optional
TMS => TMS,
TCK => TCK,
TDI => TDI,
TDO => TDO_Out,
TDO_OE => TDO_OE,
-- From the core
PC => core_pc,
-- To the PM("Flash")
pm_adr => pm_adr,
pm_h_we => pm_h_we,
pm_l_we => pm_l_we,
pm_dout => pm_dout,
pm_din => pm_din,
-- To the "EEPROM"
EEPrgSel => EEPrgSel,
EEAdr => EEAdr,
EEWrData => EEWrData,
EERdData => EERdData,
EEWr => EEWr,
-- CPU reset
jtag_rst => JTAG_Rst
);
-- JTAG OCD module connection to the external multiplexer
io_port_out(3) <= (others => '0');
io_port_out_en(3) <= gnd;
TDO <= TDO_Out when TDO_OE='1' else 'Z';
-- *******************************************************************************************************
-- DMA, Memory decoder, ...
-- *******************************************************************************************************
-- ****************** SPI **************************
spi_is_used:if CImplSPI generate
spi_mod_inst:component spi_mod port map(
-- AVR Control
ireset => core_ireset,
cp2 => clk16M,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => spi_dbusout,
iore => core_iore,
iowe => core_iowe,
out_en => spi_out_en,
-- SPI i/f
misoi => spi_misoi,
mosii => spi_mosii,
scki => spi_scki,
ss_b => spi_ss_b,
misoo => spi_misoo,
mosio => spi_mosio,
scko => spi_scko,
spe => spi_spe,
spimaster => spi_spimaster,
-- IRQ
spiirq => core_irqlines(16),
spiack => ind_irq_ack(16),
-- Slave Programming Mode
por => gnd,
spiextload => gnd,
spidwrite => open,
spiload => open
);
-- SPI connection to the external multiplexer
io_port_out(9) <= spi_dbusout;
io_port_out_en(9) <= spi_out_en;
-- Pads
--mosi_SIG <= spi_mosio when (spi_spimaster='1') else 'Z';
--miso_SIG <= spi_misoo when (spi_spimaster='0') else 'Z';
--sck_SIG <= spi_scko when (spi_spimaster='1') else 'Z';
--
--spi_misoi <= miso_SIG;
--spi_mosii <= mosi_SIG;
--spi_scki <= sck_SIG;
spi_ss_b <= vcc;
-- Pads
spi_slv_sel_inst:component spi_slv_sel generic map(num_of_slvs => c_spi_slvs_num)
port map(
-- AVR Control
ireset => core_ireset,
cp2 => core_cp2,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => open,
iore => core_iore,
iowe => core_iowe,
out_en => open,
-- Output
slv_sel_n => spi_slv_sel_n
);
end generate;
spi_cs_n <= spi_slv_sel_n(0);
no_spi:if not CImplSPI generate
--mosi_SIG <= 'Z';
--miso_SIG <= 'Z';
--sck_SIG <= 'Z';
--io_slv_out(1).dbusout <= (others => '0');
--io_slv_out(1).out_en <= gnd;
spi_slv_sel_n <= (others => '1');
end generate;
uart_Inst:component uart port map(
-- AVR Control
ireset => core_ireset,
cp2 => core_cp2,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => uart_dbusout,
iore => core_iore,
iowe => core_iowe,
out_en => uart_out_en,
-- UART
rxd => rxd,
rx_en => open,
txd => txd,
tx_en => open,
-- IRQ
txcirq => core_irqlines(19),
txc_irqack => ind_irq_ack(19),
udreirq => core_irqlines(18),
rxcirq => core_irqlines(17)
);
-- UART connection to the external multiplexer
io_port_out(2) <= uart_dbusout;
io_port_out_en(2) <= uart_out_en;
-- Arbiter and mux
ArbiterAndMux_Inst:component ArbiterAndMux port map(
--Clock and reset
ireset => core_ireset,
cp2 => core_cp2,
-- Bus masters
busmin => busmin,
busmwait => busmwait,
-- Memory Address,Data and Control
ramadr => mem_ramadr,
ramdout => mem_ram_dbus_in,
ramre => mem_ramre,
ramwe => mem_ramwe,
cpuwait => slv_cpuwait
);
-- cpuwait
slv_cpuwait <= '0';
-- Core connection
busmin(0).ramadr <= core_ramadr;
busmin(0).dout <= ram_din; -- !!!
busmin(0).ramre <= core_ramre;
busmin(0).ramwe <= core_ramwe;
core_cpuwait <= busmwait(0);
-- UART DMA connection
busmin(1).ramadr <= (others => '0');
busmin(1).dout <= (others => '0'); -- !!!
busmin(1).ramre <= gnd;
busmin(1).ramwe <= gnd;
udma_mack <= not busmwait(1);
-- AES DMA connection
busmin(2).ramadr <= (others => '0');
busmin(2).dout <= (others => '0');
busmin(2).ramre <= gnd;
busmin(2).ramwe <= gnd;
aes_mack <= not busmwait(2);
-- UART DMA slave part
slv_outs(0).dout <= (others => '0');
slv_outs(0).out_en <= gnd;
-- AES DMA slave part
slv_outs(1).dout <= (others => '0');
slv_outs(1).out_en <= gnd;
-- Memory read mux
MemRdMux_inst:component MemRdMux port map(
slv_outs => slv_outs,
ram_sel => ram_sel, -- Data RAM selection(optional input)
ram_dout => mem_ram_dbus_out, -- Data memory output (From RAM)
dout => mem_mux_out -- Data output (To the core and other bus masters)
);
-- Address decoder
RAMAdrDcd_Inst:component RAMAdrDcd port map(
ramadr => mem_ramadr,
ramre => mem_ramre,
ramwe => mem_ramwe,
-- Memory mapped I/O i/f
stb_IO => stb_IO,
stb_IOmod => stb_IOmod,
-- Data memory i/f
ram_we => ram_ramwe,
ram_ce => ram_ce,
ram_sel => ram_sel
);
end Struct;
| apache-2.0 | 09d0be5f6e05adcc2b0ebcb73a3e22f2 | 0.486154 | 3.772953 | false | false | false | false |
grwlf/vsim | vhdl_bugs/entity1.vhd | 1 | 912 | -- Simple entity test, in/out ports
entity main is
end entity main;
entity unit1 is
port (
-- BUG: java translator doesn't allow default values in entity port
-- declarations, Aldec does.
inum : in integer := 1;
oled : out integer);
end entity unit1;
architecture unit1_a of unit1 is
begin
oled <= inum;
end architecture unit1_a;
architecture main of main is
constant CYCLES : integer := 100;
signal clk : integer := 0;
signal o1 : integer;
signal o2 : integer;
signal o : integer;
begin
terminator : process(clk)
begin
if clk >= CYCLES then
assert false report "end of simulation" severity failure;
end if;
end process;
u1:entity unit1(unit1_a) port map(oled=>o1);
u2:entity unit1(unit1_a) port map(inum=>clk, oled=>o2);
clk <= clk + 1 after 1 us;
o <= o1 + o2;
end architecture main;
| gpl-3.0 | 838a24063f63c8eb10c7b75ab6e34abb | 0.626096 | 3.390335 | false | false | false | false |
wsoltys/AtomFpga | src/AtomGodilVideo/src/SID/sid_voice.vhd | 1 | 28,633 | -------------------------------------------------------------------------------
--
-- SID 6581 (voice)
--
-- This piece of VHDL code describes a single SID voice (sound channel)
--
-------------------------------------------------------------------------------
-- to do: - better resolution of result signal voice, this is now only 12bits
-- but it could be 20 !! Problem, it does not fit the PWM-dac
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity sid_voice is
port (
clk_1MHz : in std_logic; -- this line drives the oscilator
reset : in std_logic; -- active high signal (i.e. registers are reset when reset=1)
Freq_lo : in std_logic_vector(7 downto 0); -- low-byte of frequency register
Freq_hi : in std_logic_vector(7 downto 0); -- high-byte of frequency register
Pw_lo : in std_logic_vector(7 downto 0); -- low-byte of PuleWidth register
Pw_hi : in std_logic_vector(3 downto 0); -- high-nibble of PuleWidth register
Control : in std_logic_vector(7 downto 0); -- control register
Att_dec : in std_logic_vector(7 downto 0); -- attack-deccay register
Sus_Rel : in std_logic_vector(7 downto 0); -- sustain-release register
PA_MSB_in : in std_logic; -- Phase Accumulator MSB input
PA_MSB_out : out std_logic; -- Phase Accumulator MSB output
Osc : out std_logic_vector(7 downto 0); -- Voice waveform register
Env : out std_logic_vector(7 downto 0); -- Voice envelope register
voice : out std_logic_vector(11 downto 0) -- Voice waveform, this is the actual audio signal
);
end sid_voice;
architecture Behavioral of sid_voice is
-------------------------------------------------------------------------------
-- Altera multiplier
-- COMPONENT lpm_mult
-- GENERIC
-- (
-- lpm_hint : STRING;
-- lpm_representation : STRING;
-- lpm_type : STRING;
-- lpm_widtha : NATURAL;
-- lpm_widthb : NATURAL;
-- lpm_widthp : NATURAL;
-- lpm_widths : NATURAL
-- );
-- PORT
-- (
-- dataa : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
-- datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-- result : OUT STD_LOGIC_VECTOR (19 DOWNTO 0)
-- );
-- END COMPONENT;
-------------------------------------------------------------------------------
signal accumulator : std_logic_vector(23 downto 0) := (others => '0');
signal accu_bit_prev : std_logic := '0';
signal PA_MSB_in_prev : std_logic := '0';
-- this type of signal has only two states 0 or 1 (so no more bits are required)
signal pulse : std_logic := '0';
signal sawtooth : std_logic_vector(11 downto 0) := (others => '0');
signal triangle : std_logic_vector(11 downto 0) := (others => '0');
signal noise : std_logic_vector(11 downto 0) := (others => '0');
signal LFSR : std_logic_vector(22 downto 0) := (others => '0');
signal frequency : std_logic_vector(15 downto 0) := (others => '0');
signal pulsewidth : std_logic_vector(11 downto 0) := (others => '0');
-- Envelope Generator
type envelope_state_types is (idle, attack, attack_lp, decay, decay_lp, sustain, release, release_lp);
signal cur_state, next_state : envelope_state_types;
signal divider_value : integer range 0 to 2**15 - 1 :=0;
signal divider_attack : integer range 0 to 2**15 - 1 :=0;
signal divider_dec_rel : integer range 0 to 2**15 - 1 :=0;
signal divider_counter : integer range 0 to 2**18 - 1 :=0;
signal exp_table_value : integer range 0 to 2**18 - 1 :=0;
signal exp_table_active : std_logic := '0';
signal divider_rst : std_logic := '0';
signal Dec_rel : std_logic_vector(3 downto 0) := (others => '0');
signal Dec_rel_sel : std_logic := '0';
signal env_counter : std_logic_vector(7 downto 0) := (others => '0');
signal env_count_hold_A : std_logic := '0';
signal env_count_hold_B : std_logic := '0';
signal env_cnt_up : std_logic := '0';
signal env_cnt_clear : std_logic := '0';
signal signal_mux : std_logic_vector(11 downto 0) := (others => '0');
signal signal_vol : std_logic_vector(19 downto 0) := (others => '0');
-------------------------------------------------------------------------------------
-- stop the oscillator when test = '1'
alias test : std_logic is Control(3);
-- Ring Modulation was accomplished by substituting the accumulator MSB of an
-- oscillator in the EXOR function of the triangle waveform generator with the
-- accumulator MSB of the previous oscillator. That is why the triangle waveform
-- must be selected to use Ring Modulation.
alias ringmod : std_logic is Control(2);
-- Hard Sync was accomplished by clearing the accumulator of an Oscillator
-- based on the accumulator MSB of the previous oscillator.
alias sync : std_logic is Control(1);
--
alias gate : std_logic is Control(0);
-------------------------------------------------------------------------------------
begin
-- output the Phase accumulator's MSB for sync and ringmod purposes
PA_MSB_out <= accumulator(23);
-- output the upper 8-bits of the waveform.
-- Useful for random numbers (noise must be selected)
Osc <= signal_mux(11 downto 4);
-- output the envelope register, for special sound effects when connecting this
-- signal to the input of other channels/voices
Env <= env_counter;
-- use the register value to fill the variable
frequency <= Freq_hi & Freq_lo;
-- use the register value to fill the variable
pulsewidth <= Pw_hi & Pw_lo;
--
voice <= signal_vol(19 downto 8);
-- Phase accumulator :
-- "As I recall, the Oscillator is a 24-bit phase-accumulating design of which
-- the lower 16-bits are programmable for pitch control. The output of the
-- accumulator goes directly to a D/A converter through a waveform selector.
-- Normally, the output of a phase-accumulating oscillator would be used as an
-- address into memory which contained a wavetable, but SID had to be entirely
-- self-contained and there was no room at all for a wavetable on the chip."
-- "Hard Sync was accomplished by clearing the accumulator of an Oscillator
-- based on the accumulator MSB of the previous oscillator."
PhaseAcc:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
PA_MSB_in_prev <= PA_MSB_in;
-- the reset and test signal can stop the oscillator,
-- stopping the oscillator is very useful when you want to play "samples"
if ((reset = '1') or (test = '1') or ((sync = '1') and (PA_MSB_in_prev /= PA_MSB_in) and (PA_MSB_in = '0'))) then
accumulator <= (others => '0');
else
-- accumulate the new phase (i.o.w. increment env_counter with the freq. value)
accumulator <= accumulator + ("0" & frequency);
end if;
end if;
end process;
-- Sawtooth waveform :
-- "The Sawtooth waveform was created by sending the upper 12-bits of the
-- accumulator to the 12-bit Waveform D/A."
Snd_Sawtooth:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
sawtooth <= accumulator(23 downto 12);
end if;
end process;
--Pulse waveform :
-- "The Pulse waveform was created by sending the upper 12-bits of the
-- accumulator to a 12-bit digital comparator. The output of the comparator was
-- either a one or a zero. This single output was then sent to all 12 bits of
-- the Waveform D/A. "
Snd_pulse:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((accumulator(23 downto 12)) >= pulsewidth) then
pulse <= '1';
else
pulse <= '0';
end if;
end if;
end process;
--Triangle waveform :
-- "The Triangle waveform was created by using the MSB of the accumulator to
-- invert the remaining upper 11 accumulator bits using EXOR gates. These 11
-- bits were then left-shifted (throwing away the MSB) and sent to the Waveform
-- D/A (so the resolution of the triangle waveform was half that of the sawtooth,
-- but the amplitude and frequency were the same). "
-- "Ring Modulation was accomplished by substituting the accumulator MSB of an
-- oscillator in the EXOR function of the triangle waveform generator with the
-- accumulator MSB of the previous oscillator. That is why the triangle waveform
-- must be selected to use Ring Modulation."
Snd_triangle:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ringmod = '0' then
-- no ringmodulation
triangle(11)<= accumulator(23) xor accumulator(22);
triangle(10)<= accumulator(23) xor accumulator(21);
triangle(9) <= accumulator(23) xor accumulator(20);
triangle(8) <= accumulator(23) xor accumulator(19);
triangle(7) <= accumulator(23) xor accumulator(18);
triangle(6) <= accumulator(23) xor accumulator(17);
triangle(5) <= accumulator(23) xor accumulator(16);
triangle(4) <= accumulator(23) xor accumulator(15);
triangle(3) <= accumulator(23) xor accumulator(14);
triangle(2) <= accumulator(23) xor accumulator(13);
triangle(1) <= accumulator(23) xor accumulator(12);
triangle(0) <= accumulator(23) xor accumulator(11);
else
-- ringmodulation by the other voice (previous voice)
triangle(11)<= PA_MSB_in xor accumulator(22);
triangle(10)<= PA_MSB_in xor accumulator(21);
triangle(9) <= PA_MSB_in xor accumulator(20);
triangle(8) <= PA_MSB_in xor accumulator(19);
triangle(7) <= PA_MSB_in xor accumulator(18);
triangle(6) <= PA_MSB_in xor accumulator(17);
triangle(5) <= PA_MSB_in xor accumulator(16);
triangle(4) <= PA_MSB_in xor accumulator(15);
triangle(3) <= PA_MSB_in xor accumulator(14);
triangle(2) <= PA_MSB_in xor accumulator(13);
triangle(1) <= PA_MSB_in xor accumulator(12);
triangle(0) <= PA_MSB_in xor accumulator(11);
end if;
end if;
end process;
--Noise (23-bit Linear Feedback Shift Register, max combinations = 8388607) :
-- "The Noise waveform was created using a 23-bit pseudo-random sequence
-- generator (i.e., a shift register with specific outputs fed back to the input
-- through combinatorial logic). The shift register was clocked by one of the
-- intermediate bits of the accumulator to keep the frequency content of the
-- noise waveform relatively the same as the pitched waveforms.
-- The upper 12-bits of the shift register were sent to the Waveform D/A."
noise <= LFSR(22 downto 11);
Snd_noise:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
-- the test signal can stop the oscillator,
-- stopping the oscillator is very useful when you want to play "samples"
if ((reset = '1') or (test = '1')) then
accu_bit_prev <= '0';
-- the "seed" value (the value that eventually determines the output
-- pattern) may never be '0' otherwise the generator "locks up"
LFSR <= "00000000000000000000001";
else
accu_bit_prev <= accumulator(19);
-- when not equal to ...
if (accu_bit_prev /= accumulator(19)) then
LFSR(22 downto 1) <= LFSR(21 downto 0);
LFSR(0) <= LFSR(17) xor LFSR(22); -- see Xilinx XAPP052 for maximal LFSR taps
else
LFSR <= LFSR;
end if;
end if;
end if;
end process;
-- Waveform Output selector (MUX):
-- "Since all of the waveforms were just digital bits, the Waveform Selector
-- consisted of multiplexers that selected which waveform bits would be sent
-- to the Waveform D/A. The multiplexers were single transistors and did not
-- provide a "lock-out", allowing combinations of the waveforms to be selected.
-- The combination was actually a logical ANDing of the bits of each waveform,
-- which produced unpredictable results, so I didn't encourage this, especially
-- since it could lock up the pseudo-random sequence generator by filling it
-- with zeroes."
Snd_select:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
signal_mux(11) <= (triangle(11) and Control(4)) or (sawtooth(11) and Control(5)) or (pulse and Control(6)) or (noise(11) and Control(7));
signal_mux(10) <= (triangle(10) and Control(4)) or (sawtooth(10) and Control(5)) or (pulse and Control(6)) or (noise(10) and Control(7));
signal_mux(9) <= (triangle(9) and Control(4)) or (sawtooth(9) and Control(5)) or (pulse and Control(6)) or (noise(9) and Control(7));
signal_mux(8) <= (triangle(8) and Control(4)) or (sawtooth(8) and Control(5)) or (pulse and Control(6)) or (noise(8) and Control(7));
signal_mux(7) <= (triangle(7) and Control(4)) or (sawtooth(7) and Control(5)) or (pulse and Control(6)) or (noise(7) and Control(7));
signal_mux(6) <= (triangle(6) and Control(4)) or (sawtooth(6) and Control(5)) or (pulse and Control(6)) or (noise(6) and Control(7));
signal_mux(5) <= (triangle(5) and Control(4)) or (sawtooth(5) and Control(5)) or (pulse and Control(6)) or (noise(5) and Control(7));
signal_mux(4) <= (triangle(4) and Control(4)) or (sawtooth(4) and Control(5)) or (pulse and Control(6)) or (noise(4) and Control(7));
signal_mux(3) <= (triangle(3) and Control(4)) or (sawtooth(3) and Control(5)) or (pulse and Control(6)) or (noise(3) and Control(7));
signal_mux(2) <= (triangle(2) and Control(4)) or (sawtooth(2) and Control(5)) or (pulse and Control(6)) or (noise(2) and Control(7));
signal_mux(1) <= (triangle(1) and Control(4)) or (sawtooth(1) and Control(5)) or (pulse and Control(6)) or (noise(1) and Control(7));
signal_mux(0) <= (triangle(0) and Control(4)) or (sawtooth(0) and Control(5)) or (pulse and Control(6)) or (noise(0) and Control(7));
end if;
end process;
-- Waveform envelope (volume) control :
-- "The output of the Waveform D/A (which was an analog voltage at this point)
-- was fed into the reference input of an 8-bit multiplying D/A, creating a DCA
-- (digitally-controlled-amplifier). The digital control word which modulated
-- the amplitude of the waveform came from the Envelope Generator."
-- "The 8-bit output of the Envelope Generator was then sent to the Multiplying
-- D/A converter to modulate the amplitude of the selected Oscillator Waveform
-- (to be technically accurate, actually the waveform was modulating the output
-- of the Envelope Generator, but the result is the same)."
Envelope_multiplier:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
--calculate the resulting volume (due to the envelope generator) of the
--voice, signal_mux(12bit) * env_counter(8bit), so the result will
--require 20 bits !!
signal_vol <= signal_mux * env_counter;
end if;
end process;
-- Envelope generator :
-- "The Envelope Generator was simply an 8-bit up/down counter which, when
-- triggered by the Gate bit, counted from 0 to 255 at the Attack rate, from
-- 255 down to the programmed Sustain value at the Decay rate, remained at the
-- Sustain value until the Gate bit was cleared then counted down from the
-- Sustain value to 0 at the Release rate."
--
-- /\
-- / \
-- / | \________
-- / | | \
-- / | | |\
-- / | | | \
-- attack|dec|sustain|rel
-- this process controls the state machine "current-state"-value
Envelope_SM_advance: process (reset, clk_1MHz)
begin
if (reset = '1') then
cur_state <= idle;
else
if (rising_edge(clk_1MHz)) then
cur_state <= next_state;
end if;
end if;
end process;
-- this process controls the envelope (in other words, the volume control)
Envelope_SM: process (reset, cur_state, gate, divider_attack, divider_dec_rel, Att_dec, Sus_Rel, env_counter)
begin
if (reset = '1') then
next_state <= idle;
env_cnt_clear <='1';
env_cnt_up <='1';
env_count_hold_B <='1';
divider_rst <='1';
divider_value <= 0;
exp_table_active <='0';
Dec_rel_sel <='0'; -- select decay as input for decay/release table
else
env_cnt_clear <='0'; -- use this statement unless stated otherwise
env_cnt_up <='1'; -- use this statement unless stated otherwise
env_count_hold_B <='1'; -- use this statement unless stated otherwise
divider_rst <='0'; -- use this statement unless stated otherwise
divider_value <= 0; -- use this statement unless stated otherwise
exp_table_active <='0'; -- use this statement unless stated otherwise
case cur_state is
-- IDLE
when idle =>
env_cnt_clear <= '1'; -- clear envelope env_counter
divider_rst <= '1';
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if gate = '1' then
next_state <= attack;
else
next_state <= idle;
end if;
when attack =>
env_cnt_clear <= '1'; -- clear envelope env_counter
divider_rst <= '1';
divider_value <= divider_attack;
next_state <= attack_lp;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
when attack_lp =>
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '1'; -- envelope env_counter must count up (increment)
divider_value <= divider_attack;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if env_counter = "11111111" then
next_state <= decay;
else
if gate = '0' then
next_state <= release;
else
next_state <= attack_lp;
end if;
end if;
when decay =>
divider_rst <= '1';
exp_table_active <= '1'; -- activate exponential look-up table
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
next_state <= decay_lp;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
when decay_lp =>
exp_table_active <= '1'; -- activate exponential look-up table
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if (env_counter(7 downto 4) = Sus_Rel(7 downto 4)) then
next_state <= sustain;
else
if gate = '0' then
next_state <= release;
else
next_state <= decay_lp;
end if;
end if;
-- "A digital comparator was used for the Sustain function. The upper
-- four bits of the Up/Down counter were compared to the programmed
-- Sustain value and would stop the clock to the Envelope Generator when
-- the counter counted down to the Sustain value. This created 16 linearly
-- spaced sustain levels without havingto go through a look-up table
-- translation between the 4-bit register value and the 8-bit Envelope
-- Generator output. It also meant that sustain levels were adjustable
-- in steps of 16. Again, more register bits would have provided higher
-- resolution."
-- "When the Gate bit was cleared, the clock would again be enabled,
-- allowing the counter to count down to zero. Like an analog envelope
-- generator, the SID Envelope Generator would track the Sustain level
-- if it was changed to a lower value during the Sustain portion of the
-- envelope, however, it would not count UP if the Sustain level were set
-- higher." Instead it would count down to '0'.
when sustain =>
divider_value <= 0;
Dec_rel_sel <='1'; -- select release as input for decay/release table
if gate = '0' then
next_state <= release;
else
if (env_counter(7 downto 4) = Sus_Rel(7 downto 4)) then
next_state <= sustain;
else
next_state <= decay;
end if;
end if;
when release =>
divider_rst <= '1';
exp_table_active <= '1'; -- activate exponential look-up table
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '1'; -- select release as input for decay/release table
next_state <= release_lp;
when release_lp =>
exp_table_active <= '1'; -- activate exponential look-up table
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '1'; -- select release as input for decay/release table
if env_counter = "00000000" then
next_state <= idle;
else
if gate = '1' then
next_state <= idle;
else
next_state <= release_lp;
end if;
end if;
when others =>
divider_value <= 0;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
next_state <= idle;
end case;
end if;
end process;
-- 8 bit up/down env_counter
Envelope_counter:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((reset = '1') or (env_cnt_clear = '1')) then
env_counter <= (others => '0');
else
if ((env_count_hold_A = '1') or (env_count_hold_B = '1'))then
env_counter <= env_counter;
else
if (env_cnt_up = '1') then
env_counter <= env_counter + 1;
else
env_counter <= env_counter - 1;
end if;
end if;
end if;
end if;
end process;
-- Divider :
-- "A programmable frequency divider was used to set the various rates
-- (unfortunately I don't remember how many bits the divider was, either 12
-- or 16 bits). A small look-up table translated the 16 register-programmable
-- values to the appropriate number to load into the frequency divider.
-- Depending on what state the Envelope Generator was in (i.e. ADS or R), the
-- appropriate register would be selected and that number would be translated
-- and loaded into the divider. Obviously it would have been better to have
-- individual bit control of the divider which would have provided great
-- resolution for each rate, however I did not have enough silicon area for a
-- lot of register bits. Using this approach, I was able to cram a wide range
-- of rates into 4 bits, allowing the ADSR to be defined in two bytes instead
-- of eight. The actual numbers in the look-up table were arrived at
-- subjectively by setting up typical patches on a Sequential Circuits Pro-1
-- and measuring the envelope times by ear (which is why the available rates
-- seem strange)!"
prog_freq_div:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((reset = '1') or (divider_rst = '1')) then
env_count_hold_A <= '1';
divider_counter <= 0;
else
if (divider_counter = 0) then
env_count_hold_A <= '0';
if (exp_table_active = '1') then
divider_counter <= exp_table_value;
else
divider_counter <= divider_value;
end if;
else
env_count_hold_A <= '1';
divider_counter <= divider_counter - 1;
end if;
end if;
end if;
end process;
-- Piese-wise linear approximation of an exponential :
-- "In order to more closely model the exponential decay of sounds, another
-- look-up table on the output of the Envelope Generator would sequentially
-- divide the clock to the Envelope Generator by two at specific counts in the
-- Decay and Release cycles. This created a piece-wise linear approximation of
-- an exponential. I was particularly happy how well this worked considering
-- the simplicity of the circuitry. The Attack, however, was linear, but this
-- sounded fine."
-- The clock is divided by two at specific values of the envelope generator to
-- create an exponential.
Exponential_table:process(clk_1MHz)
BEGIN
if (rising_edge(clk_1MHz)) then
if (reset = '1') then
exp_table_value <= 0;
else
case CONV_INTEGER(env_counter) is
when 0 to 51 => exp_table_value <= divider_value * 16;
when 52 to 101 => exp_table_value <= divider_value * 8;
when 102 to 152 => exp_table_value <= divider_value * 4;
when 153 to 203 => exp_table_value <= divider_value * 2;
when 204 to 255 => exp_table_value <= divider_value;
when others => exp_table_value <= divider_value;
end case;
end if;
end if;
end process;
-- Attack Lookup table :
-- It takes 255 clock cycles from zero to peak value. Therefore the divider
-- equals (attack rate / clockcycletime of 1MHz clock) / 254;
Attack_table:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if (reset = '1') then
divider_attack <= 0;
else
case Att_dec(7 downto 4) is
when "0000" => divider_attack <= 8; --attack rate: ( 2mS / 1uS per clockcycle) /254 steps
when "0001" => divider_attack <= 31; --attack rate: ( 8mS / 1uS per clockcycle) /254 steps
when "0010" => divider_attack <= 63; --attack rate: ( 16mS / 1uS per clockcycle) /254 steps
when "0011" => divider_attack <= 94; --attack rate: ( 24mS / 1uS per clockcycle) /254 steps
when "0100" => divider_attack <= 150; --attack rate: ( 38mS / 1uS per clockcycle) /254 steps
when "0101" => divider_attack <= 220; --attack rate: ( 56mS / 1uS per clockcycle) /254 steps
when "0110" => divider_attack <= 268; --attack rate: ( 68mS / 1uS per clockcycle) /254 steps
when "0111" => divider_attack <= 315; --attack rate: ( 80mS / 1uS per clockcycle) /254 steps
when "1000" => divider_attack <= 394; --attack rate: ( 100mS / 1uS per clockcycle) /254 steps
when "1001" => divider_attack <= 984; --attack rate: ( 250mS / 1uS per clockcycle) /254 steps
when "1010" => divider_attack <= 1968; --attack rate: ( 500mS / 1uS per clockcycle) /254 steps
when "1011" => divider_attack <= 3150; --attack rate: ( 800mS / 1uS per clockcycle) /254 steps
when "1100" => divider_attack <= 3937; --attack rate: (1000mS / 1uS per clockcycle) /254 steps
when "1101" => divider_attack <= 11811; --attack rate: (3000mS / 1uS per clockcycle) /254 steps
when "1110" => divider_attack <= 19685; --attack rate: (5000mS / 1uS per clockcycle) /254 steps
when "1111" => divider_attack <= 31496; --attack rate: (8000mS / 1uS per clockcycle) /254 steps
when others => divider_attack <= 0; --
end case;
end if;
end if;
end process;
Decay_Release_input_select:process(Dec_rel_sel, Att_dec, Sus_Rel)
begin
if (Dec_rel_sel = '0') then
Dec_rel <= Att_dec(3 downto 0);
else
Dec_rel <= Sus_rel(3 downto 0);
end if;
end process;
-- Decay Lookup table :
-- It takes 32 * 51 = 1632 clock cycles to fall from peak level to zero.
-- Release Lookup table :
-- It takes 32 * 51 = 1632 clock cycles to fall from peak level to zero.
Decay_Release_table:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if reset = '1' then
divider_dec_rel <= 0;
else
case Dec_rel is
when "0000" => divider_dec_rel <= 3; --release rate: ( 6mS / 1uS per clockcycle) / 1632
when "0001" => divider_dec_rel <= 15; --release rate: ( 24mS / 1uS per clockcycle) / 1632
when "0010" => divider_dec_rel <= 29; --release rate: ( 48mS / 1uS per clockcycle) / 1632
when "0011" => divider_dec_rel <= 44; --release rate: ( 72mS / 1uS per clockcycle) / 1632
when "0100" => divider_dec_rel <= 70; --release rate: ( 114mS / 1uS per clockcycle) / 1632
when "0101" => divider_dec_rel <= 103; --release rate: ( 168mS / 1uS per clockcycle) / 1632
when "0110" => divider_dec_rel <= 125; --release rate: ( 204mS / 1uS per clockcycle) / 1632
when "0111" => divider_dec_rel <= 147; --release rate: ( 240mS / 1uS per clockcycle) / 1632
when "1000" => divider_dec_rel <= 184; --release rate: ( 300mS / 1uS per clockcycle) / 1632
when "1001" => divider_dec_rel <= 459; --release rate: ( 750mS / 1uS per clockcycle) / 1632
when "1010" => divider_dec_rel <= 919; --release rate: ( 1500mS / 1uS per clockcycle) / 1632
when "1011" => divider_dec_rel <= 1471; --release rate: ( 2400mS / 1uS per clockcycle) / 1632
when "1100" => divider_dec_rel <= 1838; --release rate: ( 3000mS / 1uS per clockcycle) / 1632
when "1101" => divider_dec_rel <= 5515; --release rate: ( 9000mS / 1uS per clockcycle) / 1632
when "1110" => divider_dec_rel <= 9191; --release rate: (15000mS / 1uS per clockcycle) / 1632
when "1111" => divider_dec_rel <= 14706; --release rate: (24000mS / 1uS per clockcycle) / 1632
when others => divider_dec_rel <= 0; --
end case;
end if;
end if;
end process;
end Behavioral;
| apache-2.0 | a82dcbab725c31c0ffdde5610d540bd8 | 0.635141 | 3.218276 | false | false | false | false |
grwlf/vsim | vhdl/IEEE/old/stdlogic.vhd | 1 | 42,553 | -- --------------------------------------------------------------------
--
-- Title : std_logic_1164 multi-value logic system
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE model standards group (par 1164)
-- Purpose : This packages defines a standard for designers
-- : to use in describing the interconnection data types
-- : used in vhdl modeling.
-- :
-- Limitation: The logic system defined in this package may
-- : be insufficient for modeling switched transistors,
-- : since such a requirement is out of the scope of this
-- : effort. Furthermore, mathematics, primitives,
-- : timing standards, etc. are considered orthogonal
-- : issues as it relates to this package and are therefore
-- : beyond the scope of this effort.
-- :
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the types, subtypes and declarations of
-- : std_logic_1164. The std_logic_1164 package body shall be
-- : considered the formal definition of the semantics of
-- : this package. Tool developers may choose to implement
-- : the package body in the most efficient manner available
-- : to them.
-- :
-- --------------------------------------------------------------------
-- modification history :
-- --------------------------------------------------------------------
-- version | mod. date:|
-- v4.200 | 01/02/92 |
-- --------------------------------------------------------------------
PACKAGE std_logic_1164 IS
-------------------------------------------------------------------
-- logic state system (unresolved)
-------------------------------------------------------------------
TYPE std_ulogic IS ( 'U', -- Uninitialized
'X', -- Forcing Unknown
'0', -- Forcing 0
'1', -- Forcing 1
'Z', -- High Impedance
'W', -- Weak Unknown
'L', -- Weak 0
'H', -- Weak 1
'-' -- Don't care
);
-------------------------------------------------------------------
-- unconstrained array of std_ulogic for use with the resolution function
-------------------------------------------------------------------
TYPE std_ulogic_vector IS ARRAY ( NATURAL RANGE <> ) OF std_ulogic;
-------------------------------------------------------------------
-- resolution function
-------------------------------------------------------------------
FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic;
-------------------------------------------------------------------
-- *** industry standard logic type ***
-------------------------------------------------------------------
SUBTYPE std_logic IS resolved std_ulogic;
-------------------------------------------------------------------
-- unconstrained array of std_logic for use in declaring signal arrays
-------------------------------------------------------------------
TYPE std_logic_vector IS ARRAY ( NATURAL RANGE <>) OF std_logic;
-------------------------------------------------------------------
-- common subtypes
-------------------------------------------------------------------
SUBTYPE X01 IS resolved std_ulogic RANGE 'X' TO '1'; -- ('X','0','1')
SUBTYPE X01Z IS resolved std_ulogic RANGE 'X' TO 'Z'; -- ('X','0','1','Z')
SUBTYPE UX01 IS resolved std_ulogic RANGE 'U' TO '1'; -- ('U','X','0','1')
SUBTYPE UX01Z IS resolved std_ulogic RANGE 'U' TO 'Z'; -- ('U','X','0','1','Z')
-------------------------------------------------------------------
-- overloaded logical operators
-------------------------------------------------------------------
FUNCTION "and" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
FUNCTION "nand" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
FUNCTION "or" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
FUNCTION "nor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
FUNCTION "xor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
function "xnor" ( l : std_ulogic; r : std_ulogic ) return ux01;
FUNCTION "not" ( l : std_ulogic ) RETURN UX01;
-------------------------------------------------------------------
-- vectorized overloaded logical operators
-------------------------------------------------------------------
FUNCTION "and" ( l, r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "and" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
FUNCTION "nand" ( l, r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "nand" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
FUNCTION "or" ( l, r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "or" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
FUNCTION "nor" ( l, r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "nor" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
FUNCTION "xor" ( l, r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "xor" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
function "xnor" ( l, r : std_logic_vector ) return std_logic_vector;
function "xnor" ( l, r : std_ulogic_vector ) return std_ulogic_vector;
FUNCTION "not" ( l : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "not" ( l : std_ulogic_vector ) RETURN std_ulogic_vector;
-------------------------------------------------------------------
-- conversion functions
-------------------------------------------------------------------
FUNCTION To_bit ( s : std_ulogic; xmap : BIT := '0') RETURN BIT;
FUNCTION To_bitvector ( s : std_logic_vector ; xmap : BIT := '0') RETURN BIT_VECTOR;
FUNCTION To_bitvector ( s : std_ulogic_vector; xmap : BIT := '0') RETURN BIT_VECTOR;
FUNCTION To_StdULogic ( b : BIT ) RETURN std_ulogic;
FUNCTION To_StdLogicVector ( b : BIT_VECTOR ) RETURN std_logic_vector;
FUNCTION To_StdLogicVector ( s : std_ulogic_vector ) RETURN std_logic_vector;
FUNCTION To_StdULogicVector ( b : BIT_VECTOR ) RETURN std_ulogic_vector;
FUNCTION To_StdULogicVector ( s : std_logic_vector ) RETURN std_ulogic_vector;
-------------------------------------------------------------------
-- strength strippers and type convertors
-------------------------------------------------------------------
FUNCTION To_X01 ( s : std_logic_vector ) RETURN std_logic_vector;
FUNCTION To_X01 ( s : std_ulogic_vector ) RETURN std_ulogic_vector;
FUNCTION To_X01 ( s : std_ulogic ) RETURN X01;
FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_logic_vector;
FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector;
FUNCTION To_X01 ( b : BIT ) RETURN X01;
FUNCTION To_X01Z ( s : std_logic_vector ) RETURN std_logic_vector;
FUNCTION To_X01Z ( s : std_ulogic_vector ) RETURN std_ulogic_vector;
FUNCTION To_X01Z ( s : std_ulogic ) RETURN X01Z;
FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_logic_vector;
FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_ulogic_vector;
FUNCTION To_X01Z ( b : BIT ) RETURN X01Z;
FUNCTION To_UX01 ( s : std_logic_vector ) RETURN std_logic_vector;
FUNCTION To_UX01 ( s : std_ulogic_vector ) RETURN std_ulogic_vector;
FUNCTION To_UX01 ( s : std_ulogic ) RETURN UX01;
FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_logic_vector;
FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector;
FUNCTION To_UX01 ( b : BIT ) RETURN UX01;
-------------------------------------------------------------------
-- edge detection
-------------------------------------------------------------------
FUNCTION rising_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN;
FUNCTION falling_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN;
-------------------------------------------------------------------
-- object contains an unknown
-------------------------------------------------------------------
FUNCTION Is_X ( s : std_ulogic_vector ) RETURN BOOLEAN;
FUNCTION Is_X ( s : std_logic_vector ) RETURN BOOLEAN;
FUNCTION Is_X ( s : std_ulogic ) RETURN BOOLEAN;
END std_logic_1164;
PACKAGE BODY std_logic_1164 IS
-------------------------------------------------------------------
-- local types
-------------------------------------------------------------------
TYPE stdlogic_1d IS ARRAY (std_ulogic) OF std_ulogic;
TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic;
-------------------------------------------------------------------
-- resolution function
-------------------------------------------------------------------
CONSTANT resolution_table : stdlogic_table := (
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ---------------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 |
( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z |
( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L |
( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | - |
);
FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic IS
VARIABLE result : std_ulogic := 'Z'; -- weakest state default
BEGIN
-- the test for a single driver is essential otherwise the
-- loop would return 'X' for a single driver of '-' and that
-- would conflict with the value of a single driver unresolved
-- signal.
IF (s'LENGTH = 1) THEN RETURN s(s'LOW);
ELSE
FOR i IN s'RANGE LOOP
result := resolution_table(result, s(i));
END LOOP;
END IF;
RETURN result;
END resolved;
-------------------------------------------------------------------
-- tables for logical operations
-------------------------------------------------------------------
-- truth table for "and" function
CONSTANT and_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ----------------------------------------------------
( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U' ), -- | U |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | 0 |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | Z |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | W |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | H |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ) -- | - |
);
-- truth table for "or" function
CONSTANT or_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ----------------------------------------------------
( 'U', 'U', 'U', '1', 'U', 'U', 'U', '1', 'U' ), -- | U |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | 1 |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | Z |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | H |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ) -- | - |
);
-- truth table for "xor" function
CONSTANT xor_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | - |
);
-- truth table for "not" function
CONSTANT not_table: stdlogic_1d :=
-- -------------------------------------------------
-- | U X 0 1 Z W L H - |
-- -------------------------------------------------
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' );
-------------------------------------------------------------------
-- overloaded logical operators ( with optimizing hints )
-------------------------------------------------------------------
FUNCTION "and" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (and_table(l, r));
END "and";
FUNCTION "nand" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (not_table ( and_table(l, r)));
END "nand";
FUNCTION "or" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (or_table(l, r));
END "or";
FUNCTION "nor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (not_table ( or_table( l, r )));
END "nor";
FUNCTION "xor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (xor_table(l, r));
END "xor";
function "xnor" ( l : std_ulogic; r : std_ulogic ) return ux01 is
begin
return not_table(xor_table(l, r));
end "xnor";
FUNCTION "not" ( l : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (not_table(l));
END "not";
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
FUNCTION "and" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'and' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := and_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "and";
---------------------------------------------------------------------
FUNCTION "and" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'and' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := and_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "and";
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
FUNCTION "nand" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'nand' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := not_table(and_table (lv(i), rv(i)));
END LOOP;
END IF;
RETURN result;
END "nand";
---------------------------------------------------------------------
FUNCTION "nand" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'nand' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := not_table(and_table (lv(i), rv(i)));
END LOOP;
END IF;
RETURN result;
END "nand";
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
FUNCTION "or" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'or' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := or_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "or";
---------------------------------------------------------------------
FUNCTION "or" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'or' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := or_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "or";
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
FUNCTION "nor" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'nor' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := not_table(or_table (lv(i), rv(i)));
END LOOP;
END IF;
RETURN result;
END "nor";
---------------------------------------------------------------------
FUNCTION "nor" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'nor' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := not_table(or_table (lv(i), rv(i)));
END LOOP;
END IF;
RETURN result;
END "nor";
---------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
FUNCTION "xor" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'xor' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := xor_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "xor";
---------------------------------------------------------------------
FUNCTION "xor" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'xor' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := xor_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "xor";
-------------------------------------------------------------------
-- xnor
-------------------------------------------------------------------
function "xnor" ( l,r : std_logic_vector ) return std_logic_vector is
alias lv : std_logic_vector ( 1 to l'length ) is l;
alias rv : std_logic_vector ( 1 to r'length ) is r;
variable result : std_logic_vector ( 1 to l'length );
begin
if ( l'length /= r'length ) then
assert false
report "arguments of overloaded 'xnor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := not_table(xor_table (lv(i), rv(i)));
end loop;
end if;
return result;
end "xnor";
---------------------------------------------------------------------
function "xnor" ( l,r : std_ulogic_vector ) return std_ulogic_vector is
alias lv : std_ulogic_vector ( 1 to l'length ) is l;
alias rv : std_ulogic_vector ( 1 to r'length ) is r;
variable result : std_ulogic_vector ( 1 to l'length );
begin
if ( l'length /= r'length ) then
assert false
report "arguments of overloaded 'xnor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := not_table(xor_table (lv(i), rv(i)));
end loop;
end if;
return result;
end "xnor";
-------------------------------------------------------------------
-- not
-------------------------------------------------------------------
FUNCTION "not" ( l : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH ) := (OTHERS => 'X');
BEGIN
FOR i IN result'RANGE LOOP
result(i) := not_table( lv(i) );
END LOOP;
RETURN result;
END;
---------------------------------------------------------------------
FUNCTION "not" ( l : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH ) := (OTHERS => 'X');
BEGIN
FOR i IN result'RANGE LOOP
result(i) := not_table( lv(i) );
END LOOP;
RETURN result;
END;
-------------------------------------------------------------------
-- conversion tables
-------------------------------------------------------------------
TYPE logic_x01_table IS ARRAY (std_ulogic'LOW TO std_ulogic'HIGH) OF X01;
TYPE logic_x01z_table IS ARRAY (std_ulogic'LOW TO std_ulogic'HIGH) OF X01Z;
TYPE logic_ux01_table IS ARRAY (std_ulogic'LOW TO std_ulogic'HIGH) OF UX01;
----------------------------------------------------------
-- table name : cvt_to_x01
--
-- parameters :
-- in : std_ulogic -- some logic value
-- returns : x01 -- state value of logic value
-- purpose : to convert state-strength to state only
--
-- example : if (cvt_to_x01 (input_signal) = '1' ) then ...
--
----------------------------------------------------------
CONSTANT cvt_to_x01 : logic_x01_table := (
'X', -- 'U'
'X', -- 'X'
'0', -- '0'
'1', -- '1'
'X', -- 'Z'
'X', -- 'W'
'0', -- 'L'
'1', -- 'H'
'X' -- '-'
);
----------------------------------------------------------
-- table name : cvt_to_x01z
--
-- parameters :
-- in : std_ulogic -- some logic value
-- returns : x01z -- state value of logic value
-- purpose : to convert state-strength to state only
--
-- example : if (cvt_to_x01z (input_signal) = '1' ) then ...
--
----------------------------------------------------------
CONSTANT cvt_to_x01z : logic_x01z_table := (
'X', -- 'U'
'X', -- 'X'
'0', -- '0'
'1', -- '1'
'Z', -- 'Z'
'X', -- 'W'
'0', -- 'L'
'1', -- 'H'
'X' -- '-'
);
----------------------------------------------------------
-- table name : cvt_to_ux01
--
-- parameters :
-- in : std_ulogic -- some logic value
-- returns : ux01 -- state value of logic value
-- purpose : to convert state-strength to state only
--
-- example : if (cvt_to_ux01 (input_signal) = '1' ) then ...
--
----------------------------------------------------------
CONSTANT cvt_to_ux01 : logic_ux01_table := (
'U', -- 'U'
'X', -- 'X'
'0', -- '0'
'1', -- '1'
'X', -- 'Z'
'X', -- 'W'
'0', -- 'L'
'1', -- 'H'
'X' -- '-'
);
-------------------------------------------------------------------
-- conversion functions
-------------------------------------------------------------------
FUNCTION To_bit ( s : std_ulogic; xmap : BIT := '0') RETURN BIT IS
BEGIN
CASE s IS
WHEN '0' | 'L' => RETURN ('0');
WHEN '1' | 'H' => RETURN ('1');
WHEN OTHERS => RETURN xmap;
END CASE;
END;
FUNCTION To_bit ( s : std_ulogic ) RETURN BIT IS
BEGIN
return to_bit( s, BIT' ('0') );
END;
--------------------------------------------------------------------
FUNCTION To_bitvector ( s : std_logic_vector ; xmap : BIT := '0') RETURN BIT_VECTOR IS
ALIAS sv : std_logic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s;
VARIABLE result : BIT_VECTOR ( s'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
CASE sv(i) IS
WHEN '0' | 'L' => result(i) := '0';
WHEN '1' | 'H' => result(i) := '1';
WHEN OTHERS => result(i) := xmap;
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_bitvector ( s : std_ulogic_vector; xmap : BIT := '0') RETURN BIT_VECTOR IS
ALIAS sv : std_ulogic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s;
VARIABLE result : BIT_VECTOR ( s'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
CASE sv(i) IS
WHEN '0' | 'L' => result(i) := '0';
WHEN '1' | 'H' => result(i) := '1';
WHEN OTHERS => result(i) := xmap;
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_StdULogic ( b : BIT ) RETURN std_ulogic IS
BEGIN
CASE b IS
WHEN '0' => RETURN '0';
WHEN '1' => RETURN '1';
END CASE;
END;
--------------------------------------------------------------------
FUNCTION To_StdLogicVector ( b : BIT_VECTOR ) RETURN std_logic_vector IS
ALIAS bv : BIT_VECTOR ( b'LENGTH-1 DOWNTO 0 ) IS b;
VARIABLE result : std_logic_vector ( b'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_StdLogicVector ( s : std_ulogic_vector ) RETURN std_logic_vector IS
ALIAS sv : std_ulogic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s;
VARIABLE result : std_logic_vector ( s'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := sv(i);
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_StdULogicVector ( b : BIT_VECTOR ) RETURN std_ulogic_vector IS
ALIAS bv : BIT_VECTOR ( b'LENGTH-1 DOWNTO 0 ) IS b;
VARIABLE result : std_ulogic_vector ( b'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_StdULogicVector ( s : std_logic_vector ) RETURN std_ulogic_vector IS
ALIAS sv : std_logic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s;
VARIABLE result : std_ulogic_vector ( s'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := sv(i);
END LOOP;
RETURN result;
END;
-------------------------------------------------------------------
-- strength strippers and type convertors
-------------------------------------------------------------------
-- to_x01
-------------------------------------------------------------------
FUNCTION To_X01 ( s : std_logic_vector ) RETURN std_logic_vector IS
ALIAS sv : std_logic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_logic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_x01 (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01 ( s : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS sv : std_ulogic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_ulogic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_x01 (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01 ( s : std_ulogic ) RETURN X01 IS
BEGIN
RETURN (cvt_to_x01(s));
END;
--------------------------------------------------------------------
FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_logic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_logic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_ulogic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01 ( b : BIT ) RETURN X01 IS
BEGIN
CASE b IS
WHEN '0' => RETURN('0');
WHEN '1' => RETURN('1');
END CASE;
END;
--------------------------------------------------------------------
-- to_x01z
-------------------------------------------------------------------
FUNCTION To_X01Z ( s : std_logic_vector ) RETURN std_logic_vector IS
ALIAS sv : std_logic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_logic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_x01z (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01Z ( s : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS sv : std_ulogic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_ulogic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_x01z (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01Z ( s : std_ulogic ) RETURN X01Z IS
BEGIN
RETURN (cvt_to_x01z(s));
END;
--------------------------------------------------------------------
FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_logic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_logic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_ulogic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_ulogic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01Z ( b : BIT ) RETURN X01Z IS
BEGIN
CASE b IS
WHEN '0' => RETURN('0');
WHEN '1' => RETURN('1');
END CASE;
END;
--------------------------------------------------------------------
-- to_ux01
-------------------------------------------------------------------
FUNCTION To_UX01 ( s : std_logic_vector ) RETURN std_logic_vector IS
ALIAS sv : std_logic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_logic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_ux01 (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_UX01 ( s : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS sv : std_ulogic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_ulogic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_ux01 (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_UX01 ( s : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (cvt_to_ux01(s));
END;
--------------------------------------------------------------------
FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_logic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_logic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_ulogic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_UX01 ( b : BIT ) RETURN UX01 IS
BEGIN
CASE b IS
WHEN '0' => RETURN('0');
WHEN '1' => RETURN('1');
END CASE;
END;
-------------------------------------------------------------------
-- edge detection
-------------------------------------------------------------------
FUNCTION rising_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN IS
BEGIN
RETURN (s'EVENT AND (To_X01(s) = '1') AND
(To_X01(s'LAST_VALUE) = '0'));
END;
FUNCTION falling_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN IS
BEGIN
RETURN (s'EVENT AND (To_X01(s) = '0') AND
(To_X01(s'LAST_VALUE) = '1'));
END;
-------------------------------------------------------------------
-- object contains an unknown
-------------------------------------------------------------------
FUNCTION Is_X ( s : std_ulogic_vector ) RETURN BOOLEAN IS
BEGIN
FOR i IN s'RANGE LOOP
CASE s(i) IS
WHEN 'U' | 'X' | 'Z' | 'W' | '-' => RETURN TRUE;
WHEN OTHERS => NULL;
END CASE;
END LOOP;
RETURN FALSE;
END;
--------------------------------------------------------------------
FUNCTION Is_X ( s : std_logic_vector ) RETURN BOOLEAN IS
BEGIN
FOR i IN s'RANGE LOOP
CASE s(i) IS
WHEN 'U' | 'X' | 'Z' | 'W' | '-' => RETURN TRUE;
WHEN OTHERS => NULL;
END CASE;
END LOOP;
RETURN FALSE;
END;
--------------------------------------------------------------------
FUNCTION Is_X ( s : std_ulogic ) RETURN BOOLEAN IS
BEGIN
CASE s IS
WHEN 'U' | 'X' | 'Z' | 'W' | '-' => RETURN TRUE;
WHEN OTHERS => NULL;
END CASE;
RETURN FALSE;
END;
END std_logic_1164;
| gpl-3.0 | 1dcf39e1efdebf0dc74e4ec12024cf1e | 0.381759 | 4.3417 | false | false | false | false |
jairov4/accel-oil | solution_kintex7/sim/vhdl/AESL_autobus_indices_stride.vhd | 1 | 28,947 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
library work;
use work.all;
entity AESL_autobus_indices_stride is
generic (
constant TV_IN : STRING (1 to 75) := "../tv/cdatafile/c.nfa_accept_samples_generic_hw.autotvin_indices_stride.dat";
constant TV_OUT : STRING (1 to 80) := "../tv/rtldatafile/rtl.nfa_accept_samples_generic_hw.autotvout_indices_stride.dat";
constant DATA_WIDTH : INTEGER := 8;
constant ADDR_WIDTH : INTEGER := 32;
constant DEPTH : INTEGER := 10;
constant FIFO_DEPTH : INTEGER := 32;
constant FIFO_DEPTH_ADDR_WIDTH : INTEGER := 32
);
port (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
bus_req_RW : IN STD_LOGIC;
bus_req_full_n : OUT STD_LOGIC;
bus_req_RW_en : IN STD_LOGIC;
bus_rsp_empty_n : OUT STD_LOGIC;
bus_rsp_read : IN STD_LOGIC;
bus_address : IN STD_LOGIC_VECTOR (ADDR_WIDTH - 1 downto 0);
bus_din : IN STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
bus_dout : OUT STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
bus_size : IN STD_LOGIC_VECTOR ( 31 downto 0);
ready : IN STD_LOGIC;
done : IN STD_LOGIC
);
end AESL_autobus_indices_stride;
architecture behav of AESL_autobus_indices_stride is
-- Inner signals
signal FIFO_req_ptr_r : STD_LOGIC_VECTOR (FIFO_DEPTH_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal FIFO_req_ptr_w : STD_LOGIC_VECTOR (FIFO_DEPTH_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal FIFO_req_flag : STD_LOGIC := '0'; -- 0: empty hint, 1: full hint
signal FIFO_req_empty : STD_LOGIC := '0';
signal FIFO_req_full : STD_LOGIC := '0';
signal FIFO_req_read : STD_LOGIC := '0';
signal FIFO_req_burst_flag:STD_LOGIC := '0';
signal FIFO_rsp_ptr_r : STD_LOGIC_VECTOR (ADDR_WIDTH - 1 downto 0) := (others => '0');
signal FIFO_rsp_ptr_w : STD_LOGIC_VECTOR (ADDR_WIDTH - 1 downto 0) := (others => '0');
signal FIFO_rsp_flag : STD_LOGIC := '0';
signal FIFO_rsp_empty : STD_LOGIC;
signal FIFO_rsp_full : STD_LOGIC;
signal FIFO_rsp_write : STD_LOGIC;
signal FIFO_req_temp_state : STD_LOGIC_VECTOR(1 downto 0) := "00";
type arr_fifo_req_RW is array(0 to FIFO_DEPTH - 1) of STD_LOGIC;
type arr_fifo_req_addr is array(0 to FIFO_DEPTH - 1) of STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
type arr_fifo_req_din is array(0 to FIFO_DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
type arr_fifo_req_size is array(0 to FIFO_DEPTH - 1) of STD_LOGIC_VECTOR(31 downto 0);
type arr_mem is array(0 to DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
shared variable FIFO_req_RW : arr_fifo_req_RW;
shared variable FIFO_req_address: arr_fifo_req_addr;
shared variable FIFO_req_din : arr_fifo_req_din;
shared variable FIFO_req_size : arr_fifo_req_size;
shared variable mem : arr_mem := (others => (others => '0'));
shared variable FIFO_rsp_mem : arr_mem := (others => (others => '0'));
procedure esl_read_token (file textfile: TEXT; textline: inout LINE; token: out STRING; token_len: out INTEGER) is
variable whitespace : CHARACTER;
variable i : INTEGER;
variable ok: BOOLEAN;
variable buff: STRING(1 to token'length);
begin
ok := false;
i := 1;
loop_main: while not endfile(textfile) loop
if textline = null or textline'length = 0 then
readline(textfile, textline);
end if;
loop_remove_whitespace: while textline'length > 0 loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
read(textline, whitespace);
else
exit loop_remove_whitespace;
end if;
end loop;
loop_aesl_read_token: while textline'length > 0 and i <= buff'length loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
exit loop_aesl_read_token;
else
read(textline, buff(i));
i := i + 1;
end if;
ok := true;
end loop;
if ok = true then
exit loop_main;
end if;
end loop;
buff(i) := ' ';
token := buff;
token_len:= i-1;
end procedure esl_read_token;
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING) is
variable i : INTEGER;
begin
esl_read_token (textfile, textline, token, i);
end procedure esl_read_token;
function esl_add(v1, v2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable res : unsigned(v1'length-1 downto 0);
begin
res := unsigned(v1) + unsigned(v2);
return std_logic_vector(res);
end function;
function esl_sub(v1, v2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable res : unsigned(v1'length-1 downto 0);
begin
res := unsigned(v1) - unsigned(v2);
return std_logic_vector(res);
end function;
function esl_str2lv_hex (RHS : STRING; data_width : INTEGER) return STD_LOGIC_VECTOR is
variable ret : STD_LOGIC_VECTOR(data_width - 1 downto 0);
variable idx : integer := 3;
begin
ret := (others => '0');
if(RHS(1) /= '0' and (RHS(2) /= 'x' or RHS(2) /= 'X')) then
report "Error! The format of hex number is not initialed by 0x";
end if;
while true loop
if (data_width > 4) then
case RHS(idx) is
when '0' => ret := ret(data_width - 5 downto 0) & "0000";
when '1' => ret := ret(data_width - 5 downto 0) & "0001";
when '2' => ret := ret(data_width - 5 downto 0) & "0010";
when '3' => ret := ret(data_width - 5 downto 0) & "0011";
when '4' => ret := ret(data_width - 5 downto 0) & "0100";
when '5' => ret := ret(data_width - 5 downto 0) & "0101";
when '6' => ret := ret(data_width - 5 downto 0) & "0110";
when '7' => ret := ret(data_width - 5 downto 0) & "0111";
when '8' => ret := ret(data_width - 5 downto 0) & "1000";
when '9' => ret := ret(data_width - 5 downto 0) & "1001";
when 'a' | 'A' => ret := ret(data_width - 5 downto 0) & "1010";
when 'b' | 'B' => ret := ret(data_width - 5 downto 0) & "1011";
when 'c' | 'C' => ret := ret(data_width - 5 downto 0) & "1100";
when 'd' | 'D' => ret := ret(data_width - 5 downto 0) & "1101";
when 'e' | 'E' => ret := ret(data_width - 5 downto 0) & "1110";
when 'f' | 'F' => ret := ret(data_width - 5 downto 0) & "1111";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 4) then
case RHS(idx) is
when '0' => ret := "0000";
when '1' => ret := "0001";
when '2' => ret := "0010";
when '3' => ret := "0011";
when '4' => ret := "0100";
when '5' => ret := "0101";
when '6' => ret := "0110";
when '7' => ret := "0111";
when '8' => ret := "1000";
when '9' => ret := "1001";
when 'a' | 'A' => ret := "1010";
when 'b' | 'B' => ret := "1011";
when 'c' | 'C' => ret := "1100";
when 'd' | 'D' => ret := "1101";
when 'e' | 'E' => ret := "1110";
when 'f' | 'F' => ret := "1111";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 3) then
case RHS(idx) is
when '0' => ret := "000";
when '1' => ret := "001";
when '2' => ret := "010";
when '3' => ret := "011";
when '4' => ret := "100";
when '5' => ret := "101";
when '6' => ret := "110";
when '7' => ret := "111";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 2) then
case RHS(idx) is
when '0' => ret := "00";
when '1' => ret := "01";
when '2' => ret := "10";
when '3' => ret := "11";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 1) then
case RHS(idx) is
when '0' => ret := "0";
when '1' => ret := "1";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
else
report string'("Wrong data_width.");
return ret;
end if;
idx := idx + 1;
end loop;
return ret;
end function;
function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING is
constant str_len : integer := (lv'length + 3)/4;
variable ret : STRING (1 to str_len);
variable i, tmp: INTEGER;
variable normal_lv : STD_LOGIC_VECTOR(lv'length - 1 downto 0);
variable tmp_lv : STD_LOGIC_VECTOR(3 downto 0);
begin
normal_lv := lv;
for i in 1 to str_len loop
if(i = 1) then
if((lv'length mod 4) = 3) then
tmp_lv(2 downto 0) := normal_lv(lv'length - 1 downto lv'length - 3);
case tmp_lv(2 downto 0) is
when "000" => ret(i) := '0';
when "001" => ret(i) := '1';
when "010" => ret(i) := '2';
when "011" => ret(i) := '3';
when "100" => ret(i) := '4';
when "101" => ret(i) := '5';
when "110" => ret(i) := '6';
when "111" => ret(i) := '7';
when others => ret(i) := '0';
end case;
elsif((lv'length mod 4) = 2) then
tmp_lv(1 downto 0) := normal_lv(lv'length - 1 downto lv'length - 2);
case tmp_lv(1 downto 0) is
when "00" => ret(i) := '0';
when "01" => ret(i) := '1';
when "10" => ret(i) := '2';
when "11" => ret(i) := '3';
when others => ret(i) := '0';
end case;
elsif((lv'length mod 4) = 1) then
tmp_lv(0 downto 0) := normal_lv(lv'length - 1 downto lv'length - 1);
case tmp_lv(0 downto 0) is
when "0" => ret(i) := '0';
when "1" => ret(i) := '1';
when others=> ret(i) := '0';
end case;
elsif((lv'length mod 4) = 0) then
tmp_lv(3 downto 0) := normal_lv(lv'length - 1 downto lv'length - 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := '0';
end case;
end if;
else
tmp_lv(3 downto 0) := normal_lv((str_len - i) * 4 + 3 downto (str_len - i) * 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := '0';
end case;
end if;
end loop;
return ret;
end function;
begin
-------------- Assignment for output port -------------------
assign_proc : process
begin
wait until (clk'event and clk = '1');
wait for 0.4 ns;
bus_dout <= FIFO_rsp_mem(CONV_INTEGER(FIFO_rsp_ptr_r));
end process;
bus_rsp_proc : process(FIFO_rsp_empty)
begin
bus_rsp_empty_n <= not FIFO_rsp_empty;
end process;
bus_req_full_n_proc : process(FIFO_req_full)
begin
bus_req_full_n <= not FIFO_req_full;
end process;
FIFO_req_empty_full_proc : process(FIFO_req_ptr_r, FIFO_req_ptr_w, FIFO_req_flag)
begin
if(FIFO_req_ptr_r = FIFO_req_ptr_w) then
if(FIFO_req_flag = '1') then
FIFO_req_full <= '1';
FIFO_req_empty <= '0';
else
FIFO_req_full <= '0';
FIFO_req_empty <= '1';
end if;
else
FIFO_req_full <= '0';
FIFO_req_empty <= '0';
end if;
end process;
FIFO_rsp_empty_full_proc : process(FIFO_rsp_ptr_r, FIFO_rsp_ptr_w, FIFO_rsp_flag)
begin
if(FIFO_rsp_ptr_r = FIFO_rsp_ptr_w) then
if(FIFO_rsp_flag = '1') then
FIFO_rsp_full <= '1';
FIFO_rsp_empty <= '0';
else
FIFO_rsp_full <= '0';
FIFO_rsp_empty <= '1';
end if;
else
FIFO_rsp_full <= '0';
FIFO_rsp_empty <= '0';
end if;
end process;
-- Push RTL's req into FIFO_req
FIFO_req_write_proc : process(clk, rst)
begin
if(rst = '1') then
FIFO_req_ptr_w <= (others => '0');
elsif (clk'event and clk = '1') then
if(bus_req_RW_en = '1' and FIFO_req_full = '0') then
FIFO_req_RW(CONV_INTEGER(FIFO_req_ptr_w)) := bus_req_RW;
FIFO_req_address(CONV_INTEGER(FIFO_req_ptr_w)) := bus_address;
FIFO_req_din(CONV_INTEGER(FIFO_req_ptr_w)) := bus_din;
FIFO_req_size(CONV_INTEGER(FIFO_req_ptr_w)) := bus_size;
if(CONV_INTEGER(FIFO_req_ptr_w) /= FIFO_DEPTH - 1) then
FIFO_req_ptr_w <= esl_add(FIFO_req_ptr_w,"1");
else
FIFO_req_ptr_w <= (others => '0');
end if;
end if;
end if;
end process;
FIFO_req_read_proc : process(clk, rst)
variable FIFO_req_RW_temp : STD_LOGIC;
variable FIFO_req_address_temp : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
variable FIFO_req_din_temp : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
variable FIFO_req_size_temp : STD_LOGIC_VECTOR(31 downto 0);
constant IDLE_STATE : STD_LOGIC_VECTOR(1 downto 0) := "00";
constant READ_BURST_STATE : STD_LOGIC_VECTOR(1 downto 0) := "01";
constant WRITE_BURST_STATE : STD_LOGIC_VECTOR(1 downto 0) := "10";
begin
if(rst = '1') then
FIFO_req_temp_state <= IDLE_STATE;
FIFO_req_read <= '0';
FIFO_rsp_write <= '0';
elsif (clk'event and clk = '1') then
case FIFO_req_temp_state is
when IDLE_STATE =>
if(FIFO_req_empty = '0' and FIFO_rsp_full = '0') then
FIFO_req_read <= '1';
if(CONV_INTEGER(FIFO_req_ptr_r) /= FIFO_DEPTH - 1) then
FIFO_req_ptr_r <= esl_add(FIFO_req_ptr_r, "1");
else
FIFO_req_ptr_r <= (others => '0');
end if;
FIFO_req_RW_temp:= FIFO_req_RW(CONV_INTEGER(FIFO_req_ptr_r));
FIFO_req_address_temp := FIFO_req_address(CONV_INTEGER(FIFO_req_ptr_r));
FIFO_req_din_temp := FIFO_req_din(CONV_INTEGER(FIFO_req_ptr_r));
FIFO_req_size_temp := FIFO_req_size(CONV_INTEGER(FIFO_req_ptr_r));
-- Read request
if(FIFO_req_RW_temp = '0') then
FIFO_rsp_write <= '1'; -- Indicate the output is valid
FIFO_rsp_mem(CONV_INTEGER(FIFO_rsp_ptr_w)) := mem(CONV_INTEGER(FIFO_req_address_temp));
if(FIFO_rsp_ptr_w /= DEPTH - 1) then
FIFO_rsp_ptr_w <= esl_add(FIFO_rsp_ptr_w,"1");
else
FIFO_rsp_ptr_w <= (others => '0');
end if;
if(CONV_INTEGER(FIFO_req_size_temp) /= 0 and CONV_INTEGER(FIFO_req_size_temp) /= 1) then -- Read burst request
FIFO_req_temp_state <= READ_BURST_STATE; -- To deal with the rest data
end if;
else
FIFO_rsp_write <= '0'; -- Indicate the output is not valid
if(CONV_INTEGER(FIFO_req_size_temp) = 0 or CONV_INTEGER(FIFO_req_size_temp) = 1) then -- Write single request
mem(CONV_INTEGER(FIFO_req_address_temp)) := FIFO_req_din_temp;
else -- Write burst request
mem(CONV_INTEGER(FIFO_req_address_temp)) := FIFO_req_din_temp; -- Input the first data
FIFO_req_temp_state <= WRITE_BURST_STATE; -- To deal with the rest data
end if;
end if;
else -- There is no request in the FIFO_req
FIFO_req_read <= '0';
FIFO_rsp_write <= '0';
end if;
when READ_BURST_STATE =>
FIFO_req_read <= '0'; -- Stop reading the next request
FIFO_req_size_temp := esl_sub(FIFO_req_size_temp, "1");
if(CONV_INTEGER(FIFO_req_address_temp) /= DEPTH - 1) then
FIFO_req_address_temp := esl_add(FIFO_req_address_temp, "1");
else
report "Burst read out of size!";
end if;
FIFO_rsp_mem(CONV_INTEGER(FIFO_rsp_ptr_w)) := mem(CONV_INTEGER(FIFO_req_address_temp));
if(CONV_INTEGER(FIFO_rsp_ptr_w) /= DEPTH - 1) then
FIFO_rsp_ptr_w <= esl_add(FIFO_rsp_ptr_w, "1");
else
FIFO_rsp_ptr_w <= (others => '0');
end if;
if(CONV_INTEGER(FIFO_req_size_temp) = 1) then -- The last one is done
FIFO_req_temp_state <= IDLE_STATE;
end if;
when WRITE_BURST_STATE =>
if(FIFO_req_empty = '0') then
FIFO_req_read <= '1'; -- Keep reading the next data(The data is storaged in FIFO_req but it is not a request)
if(CONV_INTEGER(FIFO_req_ptr_r) /= FIFO_DEPTH - 1) then
FIFO_req_ptr_r <= esl_add(FIFO_req_ptr_r, "1");
else
FIFO_req_ptr_r <= (others => '0');
end if;
FIFO_req_size_temp := esl_sub(FIFO_req_size_temp, "1");
if(CONV_INTEGER(FIFO_req_address_temp) /= DEPTH - 1) then
FIFO_req_address_temp := esl_add(FIFO_req_address_temp, "1");
else
report "Burst write out of size!";
end if;
mem(CONV_INTEGER(FIFO_req_address_temp)) := FIFO_req_din(CONV_INTEGER(FIFO_req_ptr_r));
if(CONV_INTEGER(FIFO_req_size_temp) = 1) then -- The last one is done
FIFO_req_temp_state <= IDLE_STATE;
end if;
end if;
when OTHERS =>
FIFO_req_temp_state <= IDLE_STATE;
end case;
end if;
end process;
-- Generate "FIFO_req_flag"
FIFO_req_flag_proc : process
begin
wait until clk'event and clk = '1';
if(rst = '1') then
FIFO_req_flag <= '0';
else
if((bus_req_RW_en = '1' and FIFO_req_full /= '1') and CONV_INTEGER(FIFO_req_ptr_w) = FIFO_DEPTH - 1) then
FIFO_req_flag <= '1';
end if;
wait for 0.4 ns;
if((FIFO_req_read = '1' and FIFO_req_empty /= '1') and CONV_INTEGER(FIFO_req_ptr_r) = 0) then
FIFO_req_flag <= '0';
end if;
end if;
end process;
-- Generate "FIFO_rsp_flag"
FIFO_rsp_flag_proc : process
begin
wait until clk'event and clk = '1';
if(rst = '1') then
FIFO_rsp_flag <= '0';
else
if((bus_rsp_read = '1' and FIFO_rsp_empty /= '1') and CONV_INTEGER(FIFO_rsp_ptr_r) = DEPTH - 1) then
FIFO_rsp_flag <= '0';
end if;
wait for 0.4 ns;
if((FIFO_rsp_write = '1' and FIFO_rsp_full /= '1') and CONV_INTEGER(FIFO_rsp_ptr_w) = 0) then
FIFO_rsp_flag <= '1';
end if;
end if;
end process;
-- Pop data from FIFO_rsp
FIFO_rsp_ptr_r_proc : process(clk, rst)
begin
if(rst = '1') then
FIFO_rsp_ptr_r <= (others => '0');
elsif (clk'event and clk = '1') then
if(bus_rsp_read = '1' and FIFO_rsp_empty /= '1') then
if(CONV_INTEGER(FIFO_rsp_ptr_r) /= DEPTH - 1) then
FIFO_rsp_ptr_r <= esl_add(FIFO_rsp_ptr_r, "1");
else
FIFO_rsp_ptr_r <= (others => '0');
end if;
end if;
end if;
end process;
----------------------------Read file-------------------
-- Read data from file
read_file_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 128 );
variable token_len : INTEGER;
variable token_int : INTEGER;
variable idx : INTEGER;
--variable mem_var : arr2D;
begin
file_open(fstatus, fp, TV_IN, READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & TV_IN & " failed!!!" severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
report "The token is " & token;
assert false report "Illegal format of [[[runtime]]] part in " & TV_IN severity failure;
end if;
esl_read_token(fp, token_line, token);
while(token(1 to 14) /= "[[[/runtime]]]") loop
if(token(1 to 15) /= "[[transaction]]") then
report "The token is " & token;
assert false report "Illegal format of [[transaction]] part in " & TV_IN severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
-- Start to read data for every transaction round
wait until clk'event and clk = '1';
wait for 0.2 ns;
while(ready /= '1') loop
wait until clk'event and clk = '1';
wait for 0.2 ns;
end loop;
for i in 0 to DEPTH - 1 loop
esl_read_token(fp, token_line, token);
mem(i) := esl_str2lv_hex(token, DATA_WIDTH);
end loop;
esl_read_token(fp, token_line, token);
if(token(1 to 16) /= "[[/transaction]]") then
report "The token is " & token;
assert false report "Illegal format of [[/transaction]] part in " & TV_IN severity failure;
end if;
esl_read_token(fp, token_line, token);
end loop;
file_close(fp);
wait;
end process;
----------------------------Write file-------------------
-- Write data to file
write_file_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 128 );
variable transaction_idx : INTEGER;
begin
wait until (rst = '0');
transaction_idx := 0;
while(true) loop
wait until clk'event and clk = '1';
while(done /= '1') loop
wait until clk'event and clk = '1';
end loop;
wait for 0.1 ns;
file_open(fstatus, fp, TV_OUT, APPEND_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & TV_OUT & " failed!!!" severity failure;
end if;
write(token_line, "[[transaction]] " & integer'image(transaction_idx));
writeline(fp, token_line);
for i in 0 to DEPTH - 1 loop
write(token_line, "0x" & esl_conv_string_hex(mem(i)));
writeline(fp, token_line);
end loop;
write(token_line, string'("[[/transaction]]"));
writeline(fp, token_line);
transaction_idx := transaction_idx + 1;
file_close(fp);
end loop;
wait;
end process;
end behav;
| lgpl-3.0 | a1c74a2ef39fde8e8523a211b657e286 | 0.431409 | 3.803811 | false | false | false | false |
jairov4/accel-oil | solution_virtex5_plb/syn/vhdl/nfa_get_finals_1.vhd | 1 | 13,308 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_get_finals_1 is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_finals_buckets_req_din : OUT STD_LOGIC;
nfa_finals_buckets_req_full_n : IN STD_LOGIC;
nfa_finals_buckets_req_write : OUT STD_LOGIC;
nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_finals_buckets_rsp_read : OUT STD_LOGIC;
nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (63 downto 0);
nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (63 downto 0);
nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
finals_buckets_address0 : OUT STD_LOGIC_VECTOR (3 downto 0);
finals_buckets_ce0 : OUT STD_LOGIC;
finals_buckets_we0 : OUT STD_LOGIC;
finals_buckets_d0 : OUT STD_LOGIC_VECTOR (63 downto 0);
tmp_28 : IN STD_LOGIC_VECTOR (4 downto 0) );
end;
architecture behav of nfa_get_finals_1 is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "0";
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0';
signal tmp_28_read_reg_67 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_tmp_28_read_reg_67_pp0_it1 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_tmp_28_read_reg_67_pp0_it2 : STD_LOGIC_VECTOR (4 downto 0);
signal nfa_finals_buckets_read_reg_72 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_28_cast_fu_63_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_pprstidle_pp0 : STD_LOGIC;
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it2 assign process. --
ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it3 assign process. --
ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
ap_reg_ppstg_tmp_28_read_reg_67_pp0_it1 <= tmp_28_read_reg_67;
ap_reg_ppstg_tmp_28_read_reg_67_pp0_it2 <= ap_reg_ppstg_tmp_28_read_reg_67_pp0_it1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
nfa_finals_buckets_read_reg_72 <= nfa_finals_buckets_datain;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
tmp_28_read_reg_67 <= tmp_28;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it2 , nfa_finals_buckets_rsp_empty_n , ap_ce , ap_sig_pprstidle_pp0)
begin
case ap_CS_fsm is
when ap_ST_pp0_stg0_fsm_0 =>
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, nfa_finals_buckets_rsp_empty_n, ap_ce)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, nfa_finals_buckets_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_reg_ppiten_pp0_it0 <= ap_start;
-- ap_sig_pprstidle_pp0 assign process. --
ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2)
begin
if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_start))) then
ap_sig_pprstidle_pp0 <= ap_const_logic_1;
else
ap_sig_pprstidle_pp0 <= ap_const_logic_0;
end if;
end process;
finals_buckets_address0 <= tmp_28_cast_fu_63_p1(4 - 1 downto 0);
-- finals_buckets_ce0 assign process. --
finals_buckets_ce0_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, nfa_finals_buckets_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
finals_buckets_ce0 <= ap_const_logic_1;
else
finals_buckets_ce0 <= ap_const_logic_0;
end if;
end process;
finals_buckets_d0 <= nfa_finals_buckets_read_reg_72;
-- finals_buckets_we0 assign process. --
finals_buckets_we0_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, nfa_finals_buckets_rsp_empty_n, ap_ce)
begin
if ((((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce)))) then
finals_buckets_we0 <= ap_const_logic_1;
else
finals_buckets_we0 <= ap_const_logic_0;
end if;
end process;
nfa_finals_buckets_address <= ap_const_lv32_0;
nfa_finals_buckets_dataout <= ap_const_lv64_0;
nfa_finals_buckets_req_din <= ap_const_logic_0;
-- nfa_finals_buckets_req_write assign process. --
nfa_finals_buckets_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, nfa_finals_buckets_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
nfa_finals_buckets_req_write <= ap_const_logic_1;
else
nfa_finals_buckets_req_write <= ap_const_logic_0;
end if;
end process;
-- nfa_finals_buckets_rsp_read assign process. --
nfa_finals_buckets_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, nfa_finals_buckets_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
nfa_finals_buckets_rsp_read <= ap_const_logic_1;
else
nfa_finals_buckets_rsp_read <= ap_const_logic_0;
end if;
end process;
nfa_finals_buckets_size <= ap_const_lv32_1;
tmp_28_cast_fu_63_p1 <= std_logic_vector(resize(unsigned(ap_reg_ppstg_tmp_28_read_reg_67_pp0_it2),64));
end behav;
| lgpl-3.0 | b78e71eb8f7575872379c2a486719533 | 0.605275 | 2.663198 | false | false | false | false |
grwlf/vsim | vhdl/assign2.1.vhd | 1 | 44,479 | -- 500 variable assigns in 2 processes. GHC works here.
entity main is
end entity main;
architecture arch of main is
signal clk : integer := 0;
constant CYCLES : integer := 1000;
begin
main: process(clk)
--{{{
variable a0502 : integer;
variable a0503 : integer;
variable a0504 : integer;
variable a0505 : integer;
variable a0506 : integer;
variable a0507 : integer;
variable a0508 : integer;
variable a0509 : integer;
variable a0510 : integer;
variable a0511 : integer;
variable a0512 : integer;
variable a0513 : integer;
variable a0514 : integer;
variable a0515 : integer;
variable a0516 : integer;
variable a0517 : integer;
variable a0518 : integer;
variable a0519 : integer;
variable a0520 : integer;
variable a0521 : integer;
variable a0522 : integer;
variable a0523 : integer;
variable a0524 : integer;
variable a0525 : integer;
variable a0526 : integer;
variable a0527 : integer;
variable a0528 : integer;
variable a0529 : integer;
variable a0530 : integer;
variable a0531 : integer;
variable a0532 : integer;
variable a0533 : integer;
variable a0534 : integer;
variable a0535 : integer;
variable a0536 : integer;
variable a0537 : integer;
variable a0538 : integer;
variable a0539 : integer;
variable a0540 : integer;
variable a0541 : integer;
variable a0542 : integer;
variable a0543 : integer;
variable a0544 : integer;
variable a0545 : integer;
variable a0546 : integer;
variable a0547 : integer;
variable a0548 : integer;
variable a0549 : integer;
variable a0550 : integer;
variable a0551 : integer;
variable a0552 : integer;
variable a0553 : integer;
variable a0554 : integer;
variable a0555 : integer;
variable a0556 : integer;
variable a0557 : integer;
variable a0558 : integer;
variable a0559 : integer;
variable a0560 : integer;
variable a0561 : integer;
variable a0562 : integer;
variable a0563 : integer;
variable a0564 : integer;
variable a0565 : integer;
variable a0566 : integer;
variable a0567 : integer;
variable a0568 : integer;
variable a0569 : integer;
variable a0570 : integer;
variable a0571 : integer;
variable a0572 : integer;
variable a0573 : integer;
variable a0574 : integer;
variable a0575 : integer;
variable a0576 : integer;
variable a0577 : integer;
variable a0578 : integer;
variable a0579 : integer;
variable a0580 : integer;
variable a0581 : integer;
variable a0582 : integer;
variable a0583 : integer;
variable a0584 : integer;
variable a0585 : integer;
variable a0586 : integer;
variable a0587 : integer;
variable a0588 : integer;
variable a0589 : integer;
variable a0590 : integer;
variable a0591 : integer;
variable a0592 : integer;
variable a0593 : integer;
variable a0594 : integer;
variable a0595 : integer;
variable a0596 : integer;
variable a0597 : integer;
variable a0598 : integer;
variable a0599 : integer;
variable a0600 : integer;
variable a0601 : integer;
variable a0602 : integer;
variable a0603 : integer;
variable a0604 : integer;
variable a0605 : integer;
variable a0606 : integer;
variable a0607 : integer;
variable a0608 : integer;
variable a0609 : integer;
variable a0610 : integer;
variable a0611 : integer;
variable a0612 : integer;
variable a0613 : integer;
variable a0614 : integer;
variable a0615 : integer;
variable a0616 : integer;
variable a0617 : integer;
variable a0618 : integer;
variable a0619 : integer;
variable a0620 : integer;
variable a0621 : integer;
variable a0622 : integer;
variable a0623 : integer;
variable a0624 : integer;
variable a0625 : integer;
variable a0626 : integer;
variable a0627 : integer;
variable a0628 : integer;
variable a0629 : integer;
variable a0630 : integer;
variable a0631 : integer;
variable a0632 : integer;
variable a0633 : integer;
variable a0634 : integer;
variable a0635 : integer;
variable a0636 : integer;
variable a0637 : integer;
variable a0638 : integer;
variable a0639 : integer;
variable a0640 : integer;
variable a0641 : integer;
variable a0642 : integer;
variable a0643 : integer;
variable a0644 : integer;
variable a0645 : integer;
variable a0646 : integer;
variable a0647 : integer;
variable a0648 : integer;
variable a0649 : integer;
variable a0650 : integer;
variable a0651 : integer;
variable a0652 : integer;
variable a0653 : integer;
variable a0654 : integer;
variable a0655 : integer;
variable a0656 : integer;
variable a0657 : integer;
variable a0658 : integer;
variable a0659 : integer;
variable a0660 : integer;
variable a0661 : integer;
variable a0662 : integer;
variable a0663 : integer;
variable a0664 : integer;
variable a0665 : integer;
variable a0666 : integer;
variable a0667 : integer;
variable a0668 : integer;
variable a0669 : integer;
variable a0670 : integer;
variable a0671 : integer;
variable a0672 : integer;
variable a0673 : integer;
variable a0674 : integer;
variable a0675 : integer;
variable a0676 : integer;
variable a0677 : integer;
variable a0678 : integer;
variable a0679 : integer;
variable a0680 : integer;
variable a0681 : integer;
variable a0682 : integer;
variable a0683 : integer;
variable a0684 : integer;
variable a0685 : integer;
variable a0686 : integer;
variable a0687 : integer;
variable a0688 : integer;
variable a0689 : integer;
variable a0690 : integer;
variable a0691 : integer;
variable a0692 : integer;
variable a0693 : integer;
variable a0694 : integer;
variable a0695 : integer;
variable a0696 : integer;
variable a0697 : integer;
variable a0698 : integer;
variable a0699 : integer;
variable a0700 : integer;
variable a0701 : integer;
variable a0702 : integer;
variable a0703 : integer;
variable a0704 : integer;
variable a0705 : integer;
variable a0706 : integer;
variable a0707 : integer;
variable a0708 : integer;
variable a0709 : integer;
variable a0710 : integer;
variable a0711 : integer;
variable a0712 : integer;
variable a0713 : integer;
variable a0714 : integer;
variable a0715 : integer;
variable a0716 : integer;
variable a0717 : integer;
variable a0718 : integer;
variable a0719 : integer;
variable a0720 : integer;
variable a0721 : integer;
variable a0722 : integer;
variable a0723 : integer;
variable a0724 : integer;
variable a0725 : integer;
variable a0726 : integer;
variable a0727 : integer;
variable a0728 : integer;
variable a0729 : integer;
variable a0730 : integer;
variable a0731 : integer;
variable a0732 : integer;
variable a0733 : integer;
variable a0734 : integer;
variable a0735 : integer;
variable a0736 : integer;
variable a0737 : integer;
variable a0738 : integer;
variable a0739 : integer;
variable a0740 : integer;
variable a0741 : integer;
variable a0742 : integer;
variable a0743 : integer;
variable a0744 : integer;
variable a0745 : integer;
variable a0746 : integer;
variable a0747 : integer;
variable a0748 : integer;
variable a0749 : integer;
variable a0750 : integer;
variable a0751 : integer;
variable a0752 : integer;
variable a0753 : integer;
variable a0754 : integer;
variable a0755 : integer;
variable a0756 : integer;
variable a0757 : integer;
variable a0758 : integer;
variable a0759 : integer;
variable a0760 : integer;
variable a0761 : integer;
variable a0762 : integer;
variable a0763 : integer;
variable a0764 : integer;
variable a0765 : integer;
variable a0766 : integer;
variable a0767 : integer;
variable a0768 : integer;
variable a0769 : integer;
variable a0770 : integer;
variable a0771 : integer;
variable a0772 : integer;
variable a0773 : integer;
variable a0774 : integer;
variable a0775 : integer;
variable a0776 : integer;
variable a0777 : integer;
variable a0778 : integer;
variable a0779 : integer;
variable a0780 : integer;
variable a0781 : integer;
variable a0782 : integer;
variable a0783 : integer;
variable a0784 : integer;
variable a0785 : integer;
variable a0786 : integer;
variable a0787 : integer;
variable a0788 : integer;
variable a0789 : integer;
variable a0790 : integer;
variable a0791 : integer;
variable a0792 : integer;
variable a0793 : integer;
variable a0794 : integer;
variable a0795 : integer;
variable a0796 : integer;
variable a0797 : integer;
variable a0798 : integer;
variable a0799 : integer;
variable a0800 : integer;
variable a0801 : integer;
variable a0802 : integer;
variable a0803 : integer;
variable a0804 : integer;
variable a0805 : integer;
variable a0806 : integer;
variable a0807 : integer;
variable a0808 : integer;
variable a0809 : integer;
variable a0810 : integer;
variable a0811 : integer;
variable a0812 : integer;
variable a0813 : integer;
variable a0814 : integer;
variable a0815 : integer;
variable a0816 : integer;
variable a0817 : integer;
variable a0818 : integer;
variable a0819 : integer;
variable a0820 : integer;
variable a0821 : integer;
variable a0822 : integer;
variable a0823 : integer;
variable a0824 : integer;
variable a0825 : integer;
variable a0826 : integer;
variable a0827 : integer;
variable a0828 : integer;
variable a0829 : integer;
variable a0830 : integer;
variable a0831 : integer;
variable a0832 : integer;
variable a0833 : integer;
variable a0834 : integer;
variable a0835 : integer;
variable a0836 : integer;
variable a0837 : integer;
variable a0838 : integer;
variable a0839 : integer;
variable a0840 : integer;
variable a0841 : integer;
variable a0842 : integer;
variable a0843 : integer;
variable a0844 : integer;
variable a0845 : integer;
variable a0846 : integer;
variable a0847 : integer;
variable a0848 : integer;
variable a0849 : integer;
variable a0850 : integer;
variable a0851 : integer;
variable a0852 : integer;
variable a0853 : integer;
variable a0854 : integer;
variable a0855 : integer;
variable a0856 : integer;
variable a0857 : integer;
variable a0858 : integer;
variable a0859 : integer;
variable a0860 : integer;
variable a0861 : integer;
variable a0862 : integer;
variable a0863 : integer;
variable a0864 : integer;
variable a0865 : integer;
variable a0866 : integer;
variable a0867 : integer;
variable a0868 : integer;
variable a0869 : integer;
variable a0870 : integer;
variable a0871 : integer;
variable a0872 : integer;
variable a0873 : integer;
variable a0874 : integer;
variable a0875 : integer;
variable a0876 : integer;
variable a0877 : integer;
variable a0878 : integer;
variable a0879 : integer;
variable a0880 : integer;
variable a0881 : integer;
variable a0882 : integer;
variable a0883 : integer;
variable a0884 : integer;
variable a0885 : integer;
variable a0886 : integer;
variable a0887 : integer;
variable a0888 : integer;
variable a0889 : integer;
variable a0890 : integer;
variable a0891 : integer;
variable a0892 : integer;
variable a0893 : integer;
variable a0894 : integer;
variable a0895 : integer;
variable a0896 : integer;
variable a0897 : integer;
variable a0898 : integer;
variable a0899 : integer;
variable a0900 : integer;
variable a0901 : integer;
variable a0902 : integer;
variable a0903 : integer;
variable a0904 : integer;
variable a0905 : integer;
variable a0906 : integer;
variable a0907 : integer;
variable a0908 : integer;
variable a0909 : integer;
variable a0910 : integer;
variable a0911 : integer;
variable a0912 : integer;
variable a0913 : integer;
variable a0914 : integer;
variable a0915 : integer;
variable a0916 : integer;
variable a0917 : integer;
variable a0918 : integer;
variable a0919 : integer;
variable a0920 : integer;
variable a0921 : integer;
variable a0922 : integer;
variable a0923 : integer;
variable a0924 : integer;
variable a0925 : integer;
variable a0926 : integer;
variable a0927 : integer;
variable a0928 : integer;
variable a0929 : integer;
variable a0930 : integer;
variable a0931 : integer;
variable a0932 : integer;
variable a0933 : integer;
variable a0934 : integer;
variable a0935 : integer;
variable a0936 : integer;
variable a0937 : integer;
variable a0938 : integer;
variable a0939 : integer;
variable a0940 : integer;
variable a0941 : integer;
variable a0942 : integer;
variable a0943 : integer;
variable a0944 : integer;
variable a0945 : integer;
variable a0946 : integer;
variable a0947 : integer;
variable a0948 : integer;
variable a0949 : integer;
variable a0950 : integer;
variable a0951 : integer;
variable a0952 : integer;
variable a0953 : integer;
variable a0954 : integer;
variable a0955 : integer;
variable a0956 : integer;
variable a0957 : integer;
variable a0958 : integer;
variable a0959 : integer;
variable a0960 : integer;
variable a0961 : integer;
variable a0962 : integer;
variable a0963 : integer;
variable a0964 : integer;
variable a0965 : integer;
variable a0966 : integer;
variable a0967 : integer;
variable a0968 : integer;
variable a0969 : integer;
variable a0970 : integer;
variable a0971 : integer;
variable a0972 : integer;
variable a0973 : integer;
variable a0974 : integer;
variable a0975 : integer;
variable a0976 : integer;
variable a0977 : integer;
variable a0978 : integer;
variable a0979 : integer;
variable a0980 : integer;
variable a0981 : integer;
variable a0982 : integer;
variable a0983 : integer;
variable a0984 : integer;
variable a0985 : integer;
variable a0986 : integer;
variable a0987 : integer;
variable a0988 : integer;
variable a0989 : integer;
variable a0990 : integer;
variable a0991 : integer;
variable a0992 : integer;
variable a0993 : integer;
variable a0994 : integer;
variable a0995 : integer;
variable a0996 : integer;
variable a0997 : integer;
variable a0998 : integer;
variable a0999 : integer;
variable a1000 : integer;
begin
a0502 := 502;
a0503 := 503;
a0504 := 504;
a0505 := 505;
a0506 := 506;
a0507 := 507;
a0508 := 508;
a0509 := 509;
a0510 := 510;
a0511 := 511;
a0512 := 512;
a0513 := 513;
a0514 := 514;
a0515 := 515;
a0516 := 516;
a0517 := 517;
a0518 := 518;
a0519 := 519;
a0520 := 520;
a0521 := 521;
a0522 := 522;
a0523 := 523;
a0524 := 524;
a0525 := 525;
a0526 := 526;
a0527 := 527;
a0528 := 528;
a0529 := 529;
a0530 := 530;
a0531 := 531;
a0532 := 532;
a0533 := 533;
a0534 := 534;
a0535 := 535;
a0536 := 536;
a0537 := 537;
a0538 := 538;
a0539 := 539;
a0540 := 540;
a0541 := 541;
a0542 := 542;
a0543 := 543;
a0544 := 544;
a0545 := 545;
a0546 := 546;
a0547 := 547;
a0548 := 548;
a0549 := 549;
a0550 := 550;
a0551 := 551;
a0552 := 552;
a0553 := 553;
a0554 := 554;
a0555 := 555;
a0556 := 556;
a0557 := 557;
a0558 := 558;
a0559 := 559;
a0560 := 560;
a0561 := 561;
a0562 := 562;
a0563 := 563;
a0564 := 564;
a0565 := 565;
a0566 := 566;
a0567 := 567;
a0568 := 568;
a0569 := 569;
a0570 := 570;
a0571 := 571;
a0572 := 572;
a0573 := 573;
a0574 := 574;
a0575 := 575;
a0576 := 576;
a0577 := 577;
a0578 := 578;
a0579 := 579;
a0580 := 580;
a0581 := 581;
a0582 := 582;
a0583 := 583;
a0584 := 584;
a0585 := 585;
a0586 := 586;
a0587 := 587;
a0588 := 588;
a0589 := 589;
a0590 := 590;
a0591 := 591;
a0592 := 592;
a0593 := 593;
a0594 := 594;
a0595 := 595;
a0596 := 596;
a0597 := 597;
a0598 := 598;
a0599 := 599;
a0600 := 600;
a0601 := 601;
a0602 := 602;
a0603 := 603;
a0604 := 604;
a0605 := 605;
a0606 := 606;
a0607 := 607;
a0608 := 608;
a0609 := 609;
a0610 := 610;
a0611 := 611;
a0612 := 612;
a0613 := 613;
a0614 := 614;
a0615 := 615;
a0616 := 616;
a0617 := 617;
a0618 := 618;
a0619 := 619;
a0620 := 620;
a0621 := 621;
a0622 := 622;
a0623 := 623;
a0624 := 624;
a0625 := 625;
a0626 := 626;
a0627 := 627;
a0628 := 628;
a0629 := 629;
a0630 := 630;
a0631 := 631;
a0632 := 632;
a0633 := 633;
a0634 := 634;
a0635 := 635;
a0636 := 636;
a0637 := 637;
a0638 := 638;
a0639 := 639;
a0640 := 640;
a0641 := 641;
a0642 := 642;
a0643 := 643;
a0644 := 644;
a0645 := 645;
a0646 := 646;
a0647 := 647;
a0648 := 648;
a0649 := 649;
a0650 := 650;
a0651 := 651;
a0652 := 652;
a0653 := 653;
a0654 := 654;
a0655 := 655;
a0656 := 656;
a0657 := 657;
a0658 := 658;
a0659 := 659;
a0660 := 660;
a0661 := 661;
a0662 := 662;
a0663 := 663;
a0664 := 664;
a0665 := 665;
a0666 := 666;
a0667 := 667;
a0668 := 668;
a0669 := 669;
a0670 := 670;
a0671 := 671;
a0672 := 672;
a0673 := 673;
a0674 := 674;
a0675 := 675;
a0676 := 676;
a0677 := 677;
a0678 := 678;
a0679 := 679;
a0680 := 680;
a0681 := 681;
a0682 := 682;
a0683 := 683;
a0684 := 684;
a0685 := 685;
a0686 := 686;
a0687 := 687;
a0688 := 688;
a0689 := 689;
a0690 := 690;
a0691 := 691;
a0692 := 692;
a0693 := 693;
a0694 := 694;
a0695 := 695;
a0696 := 696;
a0697 := 697;
a0698 := 698;
a0699 := 699;
a0700 := 700;
a0701 := 701;
a0702 := 702;
a0703 := 703;
a0704 := 704;
a0705 := 705;
a0706 := 706;
a0707 := 707;
a0708 := 708;
a0709 := 709;
a0710 := 710;
a0711 := 711;
a0712 := 712;
a0713 := 713;
a0714 := 714;
a0715 := 715;
a0716 := 716;
a0717 := 717;
a0718 := 718;
a0719 := 719;
a0720 := 720;
a0721 := 721;
a0722 := 722;
a0723 := 723;
a0724 := 724;
a0725 := 725;
a0726 := 726;
a0727 := 727;
a0728 := 728;
a0729 := 729;
a0730 := 730;
a0731 := 731;
a0732 := 732;
a0733 := 733;
a0734 := 734;
a0735 := 735;
a0736 := 736;
a0737 := 737;
a0738 := 738;
a0739 := 739;
a0740 := 740;
a0741 := 741;
a0742 := 742;
a0743 := 743;
a0744 := 744;
a0745 := 745;
a0746 := 746;
a0747 := 747;
a0748 := 748;
a0749 := 749;
a0750 := 750;
a0751 := 751;
a0752 := 752;
a0753 := 753;
a0754 := 754;
a0755 := 755;
a0756 := 756;
a0757 := 757;
a0758 := 758;
a0759 := 759;
a0760 := 760;
a0761 := 761;
a0762 := 762;
a0763 := 763;
a0764 := 764;
a0765 := 765;
a0766 := 766;
a0767 := 767;
a0768 := 768;
a0769 := 769;
a0770 := 770;
a0771 := 771;
a0772 := 772;
a0773 := 773;
a0774 := 774;
a0775 := 775;
a0776 := 776;
a0777 := 777;
a0778 := 778;
a0779 := 779;
a0780 := 780;
a0781 := 781;
a0782 := 782;
a0783 := 783;
a0784 := 784;
a0785 := 785;
a0786 := 786;
a0787 := 787;
a0788 := 788;
a0789 := 789;
a0790 := 790;
a0791 := 791;
a0792 := 792;
a0793 := 793;
a0794 := 794;
a0795 := 795;
a0796 := 796;
a0797 := 797;
a0798 := 798;
a0799 := 799;
a0800 := 800;
a0801 := 801;
a0802 := 802;
a0803 := 803;
a0804 := 804;
a0805 := 805;
a0806 := 806;
a0807 := 807;
a0808 := 808;
a0809 := 809;
a0810 := 810;
a0811 := 811;
a0812 := 812;
a0813 := 813;
a0814 := 814;
a0815 := 815;
a0816 := 816;
a0817 := 817;
a0818 := 818;
a0819 := 819;
a0820 := 820;
a0821 := 821;
a0822 := 822;
a0823 := 823;
a0824 := 824;
a0825 := 825;
a0826 := 826;
a0827 := 827;
a0828 := 828;
a0829 := 829;
a0830 := 830;
a0831 := 831;
a0832 := 832;
a0833 := 833;
a0834 := 834;
a0835 := 835;
a0836 := 836;
a0837 := 837;
a0838 := 838;
a0839 := 839;
a0840 := 840;
a0841 := 841;
a0842 := 842;
a0843 := 843;
a0844 := 844;
a0845 := 845;
a0846 := 846;
a0847 := 847;
a0848 := 848;
a0849 := 849;
a0850 := 850;
a0851 := 851;
a0852 := 852;
a0853 := 853;
a0854 := 854;
a0855 := 855;
a0856 := 856;
a0857 := 857;
a0858 := 858;
a0859 := 859;
a0860 := 860;
a0861 := 861;
a0862 := 862;
a0863 := 863;
a0864 := 864;
a0865 := 865;
a0866 := 866;
a0867 := 867;
a0868 := 868;
a0869 := 869;
a0870 := 870;
a0871 := 871;
a0872 := 872;
a0873 := 873;
a0874 := 874;
a0875 := 875;
a0876 := 876;
a0877 := 877;
a0878 := 878;
a0879 := 879;
a0880 := 880;
a0881 := 881;
a0882 := 882;
a0883 := 883;
a0884 := 884;
a0885 := 885;
a0886 := 886;
a0887 := 887;
a0888 := 888;
a0889 := 889;
a0890 := 890;
a0891 := 891;
a0892 := 892;
a0893 := 893;
a0894 := 894;
a0895 := 895;
a0896 := 896;
a0897 := 897;
a0898 := 898;
a0899 := 899;
a0900 := 900;
a0901 := 901;
a0902 := 902;
a0903 := 903;
a0904 := 904;
a0905 := 905;
a0906 := 906;
a0907 := 907;
a0908 := 908;
a0909 := 909;
a0910 := 910;
a0911 := 911;
a0912 := 912;
a0913 := 913;
a0914 := 914;
a0915 := 915;
a0916 := 916;
a0917 := 917;
a0918 := 918;
a0919 := 919;
a0920 := 920;
a0921 := 921;
a0922 := 922;
a0923 := 923;
a0924 := 924;
a0925 := 925;
a0926 := 926;
a0927 := 927;
a0928 := 928;
a0929 := 929;
a0930 := 930;
a0931 := 931;
a0932 := 932;
a0933 := 933;
a0934 := 934;
a0935 := 935;
a0936 := 936;
a0937 := 937;
a0938 := 938;
a0939 := 939;
a0940 := 940;
a0941 := 941;
a0942 := 942;
a0943 := 943;
a0944 := 944;
a0945 := 945;
a0946 := 946;
a0947 := 947;
a0948 := 948;
a0949 := 949;
a0950 := 950;
a0951 := 951;
a0952 := 952;
a0953 := 953;
a0954 := 954;
a0955 := 955;
a0956 := 956;
a0957 := 957;
a0958 := 958;
a0959 := 959;
a0960 := 960;
a0961 := 961;
a0962 := 962;
a0963 := 963;
a0964 := 964;
a0965 := 965;
a0966 := 966;
a0967 := 967;
a0968 := 968;
a0969 := 969;
a0970 := 970;
a0971 := 971;
a0972 := 972;
a0973 := 973;
a0974 := 974;
a0975 := 975;
a0976 := 976;
a0977 := 977;
a0978 := 978;
a0979 := 979;
a0980 := 980;
a0981 := 981;
a0982 := 982;
a0983 := 983;
a0984 := 984;
a0985 := 985;
a0986 := 986;
a0987 := 987;
a0988 := 988;
a0989 := 989;
a0990 := 990;
a0991 := 991;
a0992 := 992;
a0993 := 993;
a0994 := 994;
a0995 := 995;
a0996 := 996;
a0997 := 997;
a0998 := 998;
a0999 := 999;
a1000 := 1000;
-- report "tick";
--}}}
end process;
main2: process(clk)
--{{{
variable a0502 : integer;
variable a0503 : integer;
variable a0504 : integer;
variable a0505 : integer;
variable a0506 : integer;
variable a0507 : integer;
variable a0508 : integer;
variable a0509 : integer;
variable a0510 : integer;
variable a0511 : integer;
variable a0512 : integer;
variable a0513 : integer;
variable a0514 : integer;
variable a0515 : integer;
variable a0516 : integer;
variable a0517 : integer;
variable a0518 : integer;
variable a0519 : integer;
variable a0520 : integer;
variable a0521 : integer;
variable a0522 : integer;
variable a0523 : integer;
variable a0524 : integer;
variable a0525 : integer;
variable a0526 : integer;
variable a0527 : integer;
variable a0528 : integer;
variable a0529 : integer;
variable a0530 : integer;
variable a0531 : integer;
variable a0532 : integer;
variable a0533 : integer;
variable a0534 : integer;
variable a0535 : integer;
variable a0536 : integer;
variable a0537 : integer;
variable a0538 : integer;
variable a0539 : integer;
variable a0540 : integer;
variable a0541 : integer;
variable a0542 : integer;
variable a0543 : integer;
variable a0544 : integer;
variable a0545 : integer;
variable a0546 : integer;
variable a0547 : integer;
variable a0548 : integer;
variable a0549 : integer;
variable a0550 : integer;
variable a0551 : integer;
variable a0552 : integer;
variable a0553 : integer;
variable a0554 : integer;
variable a0555 : integer;
variable a0556 : integer;
variable a0557 : integer;
variable a0558 : integer;
variable a0559 : integer;
variable a0560 : integer;
variable a0561 : integer;
variable a0562 : integer;
variable a0563 : integer;
variable a0564 : integer;
variable a0565 : integer;
variable a0566 : integer;
variable a0567 : integer;
variable a0568 : integer;
variable a0569 : integer;
variable a0570 : integer;
variable a0571 : integer;
variable a0572 : integer;
variable a0573 : integer;
variable a0574 : integer;
variable a0575 : integer;
variable a0576 : integer;
variable a0577 : integer;
variable a0578 : integer;
variable a0579 : integer;
variable a0580 : integer;
variable a0581 : integer;
variable a0582 : integer;
variable a0583 : integer;
variable a0584 : integer;
variable a0585 : integer;
variable a0586 : integer;
variable a0587 : integer;
variable a0588 : integer;
variable a0589 : integer;
variable a0590 : integer;
variable a0591 : integer;
variable a0592 : integer;
variable a0593 : integer;
variable a0594 : integer;
variable a0595 : integer;
variable a0596 : integer;
variable a0597 : integer;
variable a0598 : integer;
variable a0599 : integer;
variable a0600 : integer;
variable a0601 : integer;
variable a0602 : integer;
variable a0603 : integer;
variable a0604 : integer;
variable a0605 : integer;
variable a0606 : integer;
variable a0607 : integer;
variable a0608 : integer;
variable a0609 : integer;
variable a0610 : integer;
variable a0611 : integer;
variable a0612 : integer;
variable a0613 : integer;
variable a0614 : integer;
variable a0615 : integer;
variable a0616 : integer;
variable a0617 : integer;
variable a0618 : integer;
variable a0619 : integer;
variable a0620 : integer;
variable a0621 : integer;
variable a0622 : integer;
variable a0623 : integer;
variable a0624 : integer;
variable a0625 : integer;
variable a0626 : integer;
variable a0627 : integer;
variable a0628 : integer;
variable a0629 : integer;
variable a0630 : integer;
variable a0631 : integer;
variable a0632 : integer;
variable a0633 : integer;
variable a0634 : integer;
variable a0635 : integer;
variable a0636 : integer;
variable a0637 : integer;
variable a0638 : integer;
variable a0639 : integer;
variable a0640 : integer;
variable a0641 : integer;
variable a0642 : integer;
variable a0643 : integer;
variable a0644 : integer;
variable a0645 : integer;
variable a0646 : integer;
variable a0647 : integer;
variable a0648 : integer;
variable a0649 : integer;
variable a0650 : integer;
variable a0651 : integer;
variable a0652 : integer;
variable a0653 : integer;
variable a0654 : integer;
variable a0655 : integer;
variable a0656 : integer;
variable a0657 : integer;
variable a0658 : integer;
variable a0659 : integer;
variable a0660 : integer;
variable a0661 : integer;
variable a0662 : integer;
variable a0663 : integer;
variable a0664 : integer;
variable a0665 : integer;
variable a0666 : integer;
variable a0667 : integer;
variable a0668 : integer;
variable a0669 : integer;
variable a0670 : integer;
variable a0671 : integer;
variable a0672 : integer;
variable a0673 : integer;
variable a0674 : integer;
variable a0675 : integer;
variable a0676 : integer;
variable a0677 : integer;
variable a0678 : integer;
variable a0679 : integer;
variable a0680 : integer;
variable a0681 : integer;
variable a0682 : integer;
variable a0683 : integer;
variable a0684 : integer;
variable a0685 : integer;
variable a0686 : integer;
variable a0687 : integer;
variable a0688 : integer;
variable a0689 : integer;
variable a0690 : integer;
variable a0691 : integer;
variable a0692 : integer;
variable a0693 : integer;
variable a0694 : integer;
variable a0695 : integer;
variable a0696 : integer;
variable a0697 : integer;
variable a0698 : integer;
variable a0699 : integer;
variable a0700 : integer;
variable a0701 : integer;
variable a0702 : integer;
variable a0703 : integer;
variable a0704 : integer;
variable a0705 : integer;
variable a0706 : integer;
variable a0707 : integer;
variable a0708 : integer;
variable a0709 : integer;
variable a0710 : integer;
variable a0711 : integer;
variable a0712 : integer;
variable a0713 : integer;
variable a0714 : integer;
variable a0715 : integer;
variable a0716 : integer;
variable a0717 : integer;
variable a0718 : integer;
variable a0719 : integer;
variable a0720 : integer;
variable a0721 : integer;
variable a0722 : integer;
variable a0723 : integer;
variable a0724 : integer;
variable a0725 : integer;
variable a0726 : integer;
variable a0727 : integer;
variable a0728 : integer;
variable a0729 : integer;
variable a0730 : integer;
variable a0731 : integer;
variable a0732 : integer;
variable a0733 : integer;
variable a0734 : integer;
variable a0735 : integer;
variable a0736 : integer;
variable a0737 : integer;
variable a0738 : integer;
variable a0739 : integer;
variable a0740 : integer;
variable a0741 : integer;
variable a0742 : integer;
variable a0743 : integer;
variable a0744 : integer;
variable a0745 : integer;
variable a0746 : integer;
variable a0747 : integer;
variable a0748 : integer;
variable a0749 : integer;
variable a0750 : integer;
variable a0751 : integer;
variable a0752 : integer;
variable a0753 : integer;
variable a0754 : integer;
variable a0755 : integer;
variable a0756 : integer;
variable a0757 : integer;
variable a0758 : integer;
variable a0759 : integer;
variable a0760 : integer;
variable a0761 : integer;
variable a0762 : integer;
variable a0763 : integer;
variable a0764 : integer;
variable a0765 : integer;
variable a0766 : integer;
variable a0767 : integer;
variable a0768 : integer;
variable a0769 : integer;
variable a0770 : integer;
variable a0771 : integer;
variable a0772 : integer;
variable a0773 : integer;
variable a0774 : integer;
variable a0775 : integer;
variable a0776 : integer;
variable a0777 : integer;
variable a0778 : integer;
variable a0779 : integer;
variable a0780 : integer;
variable a0781 : integer;
variable a0782 : integer;
variable a0783 : integer;
variable a0784 : integer;
variable a0785 : integer;
variable a0786 : integer;
variable a0787 : integer;
variable a0788 : integer;
variable a0789 : integer;
variable a0790 : integer;
variable a0791 : integer;
variable a0792 : integer;
variable a0793 : integer;
variable a0794 : integer;
variable a0795 : integer;
variable a0796 : integer;
variable a0797 : integer;
variable a0798 : integer;
variable a0799 : integer;
variable a0800 : integer;
variable a0801 : integer;
variable a0802 : integer;
variable a0803 : integer;
variable a0804 : integer;
variable a0805 : integer;
variable a0806 : integer;
variable a0807 : integer;
variable a0808 : integer;
variable a0809 : integer;
variable a0810 : integer;
variable a0811 : integer;
variable a0812 : integer;
variable a0813 : integer;
variable a0814 : integer;
variable a0815 : integer;
variable a0816 : integer;
variable a0817 : integer;
variable a0818 : integer;
variable a0819 : integer;
variable a0820 : integer;
variable a0821 : integer;
variable a0822 : integer;
variable a0823 : integer;
variable a0824 : integer;
variable a0825 : integer;
variable a0826 : integer;
variable a0827 : integer;
variable a0828 : integer;
variable a0829 : integer;
variable a0830 : integer;
variable a0831 : integer;
variable a0832 : integer;
variable a0833 : integer;
variable a0834 : integer;
variable a0835 : integer;
variable a0836 : integer;
variable a0837 : integer;
variable a0838 : integer;
variable a0839 : integer;
variable a0840 : integer;
variable a0841 : integer;
variable a0842 : integer;
variable a0843 : integer;
variable a0844 : integer;
variable a0845 : integer;
variable a0846 : integer;
variable a0847 : integer;
variable a0848 : integer;
variable a0849 : integer;
variable a0850 : integer;
variable a0851 : integer;
variable a0852 : integer;
variable a0853 : integer;
variable a0854 : integer;
variable a0855 : integer;
variable a0856 : integer;
variable a0857 : integer;
variable a0858 : integer;
variable a0859 : integer;
variable a0860 : integer;
variable a0861 : integer;
variable a0862 : integer;
variable a0863 : integer;
variable a0864 : integer;
variable a0865 : integer;
variable a0866 : integer;
variable a0867 : integer;
variable a0868 : integer;
variable a0869 : integer;
variable a0870 : integer;
variable a0871 : integer;
variable a0872 : integer;
variable a0873 : integer;
variable a0874 : integer;
variable a0875 : integer;
variable a0876 : integer;
variable a0877 : integer;
variable a0878 : integer;
variable a0879 : integer;
variable a0880 : integer;
variable a0881 : integer;
variable a0882 : integer;
variable a0883 : integer;
variable a0884 : integer;
variable a0885 : integer;
variable a0886 : integer;
variable a0887 : integer;
variable a0888 : integer;
variable a0889 : integer;
variable a0890 : integer;
variable a0891 : integer;
variable a0892 : integer;
variable a0893 : integer;
variable a0894 : integer;
variable a0895 : integer;
variable a0896 : integer;
variable a0897 : integer;
variable a0898 : integer;
variable a0899 : integer;
variable a0900 : integer;
variable a0901 : integer;
variable a0902 : integer;
variable a0903 : integer;
variable a0904 : integer;
variable a0905 : integer;
variable a0906 : integer;
variable a0907 : integer;
variable a0908 : integer;
variable a0909 : integer;
variable a0910 : integer;
variable a0911 : integer;
variable a0912 : integer;
variable a0913 : integer;
variable a0914 : integer;
variable a0915 : integer;
variable a0916 : integer;
variable a0917 : integer;
variable a0918 : integer;
variable a0919 : integer;
variable a0920 : integer;
variable a0921 : integer;
variable a0922 : integer;
variable a0923 : integer;
variable a0924 : integer;
variable a0925 : integer;
variable a0926 : integer;
variable a0927 : integer;
variable a0928 : integer;
variable a0929 : integer;
variable a0930 : integer;
variable a0931 : integer;
variable a0932 : integer;
variable a0933 : integer;
variable a0934 : integer;
variable a0935 : integer;
variable a0936 : integer;
variable a0937 : integer;
variable a0938 : integer;
variable a0939 : integer;
variable a0940 : integer;
variable a0941 : integer;
variable a0942 : integer;
variable a0943 : integer;
variable a0944 : integer;
variable a0945 : integer;
variable a0946 : integer;
variable a0947 : integer;
variable a0948 : integer;
variable a0949 : integer;
variable a0950 : integer;
variable a0951 : integer;
variable a0952 : integer;
variable a0953 : integer;
variable a0954 : integer;
variable a0955 : integer;
variable a0956 : integer;
variable a0957 : integer;
variable a0958 : integer;
variable a0959 : integer;
variable a0960 : integer;
variable a0961 : integer;
variable a0962 : integer;
variable a0963 : integer;
variable a0964 : integer;
variable a0965 : integer;
variable a0966 : integer;
variable a0967 : integer;
variable a0968 : integer;
variable a0969 : integer;
variable a0970 : integer;
variable a0971 : integer;
variable a0972 : integer;
variable a0973 : integer;
variable a0974 : integer;
variable a0975 : integer;
variable a0976 : integer;
variable a0977 : integer;
variable a0978 : integer;
variable a0979 : integer;
variable a0980 : integer;
variable a0981 : integer;
variable a0982 : integer;
variable a0983 : integer;
variable a0984 : integer;
variable a0985 : integer;
variable a0986 : integer;
variable a0987 : integer;
variable a0988 : integer;
variable a0989 : integer;
variable a0990 : integer;
variable a0991 : integer;
variable a0992 : integer;
variable a0993 : integer;
variable a0994 : integer;
variable a0995 : integer;
variable a0996 : integer;
variable a0997 : integer;
variable a0998 : integer;
variable a0999 : integer;
variable a1000 : integer;
begin
a0502 := 502;
a0503 := 503;
a0504 := 504;
a0505 := 505;
a0506 := 506;
a0507 := 507;
a0508 := 508;
a0509 := 509;
a0510 := 510;
a0511 := 511;
a0512 := 512;
a0513 := 513;
a0514 := 514;
a0515 := 515;
a0516 := 516;
a0517 := 517;
a0518 := 518;
a0519 := 519;
a0520 := 520;
a0521 := 521;
a0522 := 522;
a0523 := 523;
a0524 := 524;
a0525 := 525;
a0526 := 526;
a0527 := 527;
a0528 := 528;
a0529 := 529;
a0530 := 530;
a0531 := 531;
a0532 := 532;
a0533 := 533;
a0534 := 534;
a0535 := 535;
a0536 := 536;
a0537 := 537;
a0538 := 538;
a0539 := 539;
a0540 := 540;
a0541 := 541;
a0542 := 542;
a0543 := 543;
a0544 := 544;
a0545 := 545;
a0546 := 546;
a0547 := 547;
a0548 := 548;
a0549 := 549;
a0550 := 550;
a0551 := 551;
a0552 := 552;
a0553 := 553;
a0554 := 554;
a0555 := 555;
a0556 := 556;
a0557 := 557;
a0558 := 558;
a0559 := 559;
a0560 := 560;
a0561 := 561;
a0562 := 562;
a0563 := 563;
a0564 := 564;
a0565 := 565;
a0566 := 566;
a0567 := 567;
a0568 := 568;
a0569 := 569;
a0570 := 570;
a0571 := 571;
a0572 := 572;
a0573 := 573;
a0574 := 574;
a0575 := 575;
a0576 := 576;
a0577 := 577;
a0578 := 578;
a0579 := 579;
a0580 := 580;
a0581 := 581;
a0582 := 582;
a0583 := 583;
a0584 := 584;
a0585 := 585;
a0586 := 586;
a0587 := 587;
a0588 := 588;
a0589 := 589;
a0590 := 590;
a0591 := 591;
a0592 := 592;
a0593 := 593;
a0594 := 594;
a0595 := 595;
a0596 := 596;
a0597 := 597;
a0598 := 598;
a0599 := 599;
a0600 := 600;
a0601 := 601;
a0602 := 602;
a0603 := 603;
a0604 := 604;
a0605 := 605;
a0606 := 606;
a0607 := 607;
a0608 := 608;
a0609 := 609;
a0610 := 610;
a0611 := 611;
a0612 := 612;
a0613 := 613;
a0614 := 614;
a0615 := 615;
a0616 := 616;
a0617 := 617;
a0618 := 618;
a0619 := 619;
a0620 := 620;
a0621 := 621;
a0622 := 622;
a0623 := 623;
a0624 := 624;
a0625 := 625;
a0626 := 626;
a0627 := 627;
a0628 := 628;
a0629 := 629;
a0630 := 630;
a0631 := 631;
a0632 := 632;
a0633 := 633;
a0634 := 634;
a0635 := 635;
a0636 := 636;
a0637 := 637;
a0638 := 638;
a0639 := 639;
a0640 := 640;
a0641 := 641;
a0642 := 642;
a0643 := 643;
a0644 := 644;
a0645 := 645;
a0646 := 646;
a0647 := 647;
a0648 := 648;
a0649 := 649;
a0650 := 650;
a0651 := 651;
a0652 := 652;
a0653 := 653;
a0654 := 654;
a0655 := 655;
a0656 := 656;
a0657 := 657;
a0658 := 658;
a0659 := 659;
a0660 := 660;
a0661 := 661;
a0662 := 662;
a0663 := 663;
a0664 := 664;
a0665 := 665;
a0666 := 666;
a0667 := 667;
a0668 := 668;
a0669 := 669;
a0670 := 670;
a0671 := 671;
a0672 := 672;
a0673 := 673;
a0674 := 674;
a0675 := 675;
a0676 := 676;
a0677 := 677;
a0678 := 678;
a0679 := 679;
a0680 := 680;
a0681 := 681;
a0682 := 682;
a0683 := 683;
a0684 := 684;
a0685 := 685;
a0686 := 686;
a0687 := 687;
a0688 := 688;
a0689 := 689;
a0690 := 690;
a0691 := 691;
a0692 := 692;
a0693 := 693;
a0694 := 694;
a0695 := 695;
a0696 := 696;
a0697 := 697;
a0698 := 698;
a0699 := 699;
a0700 := 700;
a0701 := 701;
a0702 := 702;
a0703 := 703;
a0704 := 704;
a0705 := 705;
a0706 := 706;
a0707 := 707;
a0708 := 708;
a0709 := 709;
a0710 := 710;
a0711 := 711;
a0712 := 712;
a0713 := 713;
a0714 := 714;
a0715 := 715;
a0716 := 716;
a0717 := 717;
a0718 := 718;
a0719 := 719;
a0720 := 720;
a0721 := 721;
a0722 := 722;
a0723 := 723;
a0724 := 724;
a0725 := 725;
a0726 := 726;
a0727 := 727;
a0728 := 728;
a0729 := 729;
a0730 := 730;
a0731 := 731;
a0732 := 732;
a0733 := 733;
a0734 := 734;
a0735 := 735;
a0736 := 736;
a0737 := 737;
a0738 := 738;
a0739 := 739;
a0740 := 740;
a0741 := 741;
a0742 := 742;
a0743 := 743;
a0744 := 744;
a0745 := 745;
a0746 := 746;
a0747 := 747;
a0748 := 748;
a0749 := 749;
a0750 := 750;
a0751 := 751;
a0752 := 752;
a0753 := 753;
a0754 := 754;
a0755 := 755;
a0756 := 756;
a0757 := 757;
a0758 := 758;
a0759 := 759;
a0760 := 760;
a0761 := 761;
a0762 := 762;
a0763 := 763;
a0764 := 764;
a0765 := 765;
a0766 := 766;
a0767 := 767;
a0768 := 768;
a0769 := 769;
a0770 := 770;
a0771 := 771;
a0772 := 772;
a0773 := 773;
a0774 := 774;
a0775 := 775;
a0776 := 776;
a0777 := 777;
a0778 := 778;
a0779 := 779;
a0780 := 780;
a0781 := 781;
a0782 := 782;
a0783 := 783;
a0784 := 784;
a0785 := 785;
a0786 := 786;
a0787 := 787;
a0788 := 788;
a0789 := 789;
a0790 := 790;
a0791 := 791;
a0792 := 792;
a0793 := 793;
a0794 := 794;
a0795 := 795;
a0796 := 796;
a0797 := 797;
a0798 := 798;
a0799 := 799;
a0800 := 800;
a0801 := 801;
a0802 := 802;
a0803 := 803;
a0804 := 804;
a0805 := 805;
a0806 := 806;
a0807 := 807;
a0808 := 808;
a0809 := 809;
a0810 := 810;
a0811 := 811;
a0812 := 812;
a0813 := 813;
a0814 := 814;
a0815 := 815;
a0816 := 816;
a0817 := 817;
a0818 := 818;
a0819 := 819;
a0820 := 820;
a0821 := 821;
a0822 := 822;
a0823 := 823;
a0824 := 824;
a0825 := 825;
a0826 := 826;
a0827 := 827;
a0828 := 828;
a0829 := 829;
a0830 := 830;
a0831 := 831;
a0832 := 832;
a0833 := 833;
a0834 := 834;
a0835 := 835;
a0836 := 836;
a0837 := 837;
a0838 := 838;
a0839 := 839;
a0840 := 840;
a0841 := 841;
a0842 := 842;
a0843 := 843;
a0844 := 844;
a0845 := 845;
a0846 := 846;
a0847 := 847;
a0848 := 848;
a0849 := 849;
a0850 := 850;
a0851 := 851;
a0852 := 852;
a0853 := 853;
a0854 := 854;
a0855 := 855;
a0856 := 856;
a0857 := 857;
a0858 := 858;
a0859 := 859;
a0860 := 860;
a0861 := 861;
a0862 := 862;
a0863 := 863;
a0864 := 864;
a0865 := 865;
a0866 := 866;
a0867 := 867;
a0868 := 868;
a0869 := 869;
a0870 := 870;
a0871 := 871;
a0872 := 872;
a0873 := 873;
a0874 := 874;
a0875 := 875;
a0876 := 876;
a0877 := 877;
a0878 := 878;
a0879 := 879;
a0880 := 880;
a0881 := 881;
a0882 := 882;
a0883 := 883;
a0884 := 884;
a0885 := 885;
a0886 := 886;
a0887 := 887;
a0888 := 888;
a0889 := 889;
a0890 := 890;
a0891 := 891;
a0892 := 892;
a0893 := 893;
a0894 := 894;
a0895 := 895;
a0896 := 896;
a0897 := 897;
a0898 := 898;
a0899 := 899;
a0900 := 900;
a0901 := 901;
a0902 := 902;
a0903 := 903;
a0904 := 904;
a0905 := 905;
a0906 := 906;
a0907 := 907;
a0908 := 908;
a0909 := 909;
a0910 := 910;
a0911 := 911;
a0912 := 912;
a0913 := 913;
a0914 := 914;
a0915 := 915;
a0916 := 916;
a0917 := 917;
a0918 := 918;
a0919 := 919;
a0920 := 920;
a0921 := 921;
a0922 := 922;
a0923 := 923;
a0924 := 924;
a0925 := 925;
a0926 := 926;
a0927 := 927;
a0928 := 928;
a0929 := 929;
a0930 := 930;
a0931 := 931;
a0932 := 932;
a0933 := 933;
a0934 := 934;
a0935 := 935;
a0936 := 936;
a0937 := 937;
a0938 := 938;
a0939 := 939;
a0940 := 940;
a0941 := 941;
a0942 := 942;
a0943 := 943;
a0944 := 944;
a0945 := 945;
a0946 := 946;
a0947 := 947;
a0948 := 948;
a0949 := 949;
a0950 := 950;
a0951 := 951;
a0952 := 952;
a0953 := 953;
a0954 := 954;
a0955 := 955;
a0956 := 956;
a0957 := 957;
a0958 := 958;
a0959 := 959;
a0960 := 960;
a0961 := 961;
a0962 := 962;
a0963 := 963;
a0964 := 964;
a0965 := 965;
a0966 := 966;
a0967 := 967;
a0968 := 968;
a0969 := 969;
a0970 := 970;
a0971 := 971;
a0972 := 972;
a0973 := 973;
a0974 := 974;
a0975 := 975;
a0976 := 976;
a0977 := 977;
a0978 := 978;
a0979 := 979;
a0980 := 980;
a0981 := 981;
a0982 := 982;
a0983 := 983;
a0984 := 984;
a0985 := 985;
a0986 := 986;
a0987 := 987;
a0988 := 988;
a0989 := 989;
a0990 := 990;
a0991 := 991;
a0992 := 992;
a0993 := 993;
a0994 := 994;
a0995 := 995;
a0996 := 996;
a0997 := 997;
a0998 := 998;
a0999 := 999;
a1000 := 1000;
-- report "tick";
--}}}
end process;
terminator : process(clk)
begin
if clk >= CYCLES then
assert false report "end of simulation" severity failure;
-- else
-- report "tick";
end if;
end process;
clk <= (clk+1) after 1 us;
end;
| gpl-3.0 | ce072a9d1828ef540d3b0b007223fca2 | 0.636188 | 2.730951 | false | false | false | false |
jairov4/accel-oil | solution_kintex7/sim/vhdl/AESL_autobus_indices_begin.vhd | 1 | 28,943 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
library work;
use work.all;
entity AESL_autobus_indices_begin is
generic (
constant TV_IN : STRING (1 to 74) := "../tv/cdatafile/c.nfa_accept_samples_generic_hw.autotvin_indices_begin.dat";
constant TV_OUT : STRING (1 to 79) := "../tv/rtldatafile/rtl.nfa_accept_samples_generic_hw.autotvout_indices_begin.dat";
constant DATA_WIDTH : INTEGER := 32;
constant ADDR_WIDTH : INTEGER := 32;
constant DEPTH : INTEGER := 10;
constant FIFO_DEPTH : INTEGER := 32;
constant FIFO_DEPTH_ADDR_WIDTH : INTEGER := 32
);
port (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
bus_req_RW : IN STD_LOGIC;
bus_req_full_n : OUT STD_LOGIC;
bus_req_RW_en : IN STD_LOGIC;
bus_rsp_empty_n : OUT STD_LOGIC;
bus_rsp_read : IN STD_LOGIC;
bus_address : IN STD_LOGIC_VECTOR (ADDR_WIDTH - 1 downto 0);
bus_din : IN STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
bus_dout : OUT STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
bus_size : IN STD_LOGIC_VECTOR ( 31 downto 0);
ready : IN STD_LOGIC;
done : IN STD_LOGIC
);
end AESL_autobus_indices_begin;
architecture behav of AESL_autobus_indices_begin is
-- Inner signals
signal FIFO_req_ptr_r : STD_LOGIC_VECTOR (FIFO_DEPTH_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal FIFO_req_ptr_w : STD_LOGIC_VECTOR (FIFO_DEPTH_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal FIFO_req_flag : STD_LOGIC := '0'; -- 0: empty hint, 1: full hint
signal FIFO_req_empty : STD_LOGIC := '0';
signal FIFO_req_full : STD_LOGIC := '0';
signal FIFO_req_read : STD_LOGIC := '0';
signal FIFO_req_burst_flag:STD_LOGIC := '0';
signal FIFO_rsp_ptr_r : STD_LOGIC_VECTOR (ADDR_WIDTH - 1 downto 0) := (others => '0');
signal FIFO_rsp_ptr_w : STD_LOGIC_VECTOR (ADDR_WIDTH - 1 downto 0) := (others => '0');
signal FIFO_rsp_flag : STD_LOGIC := '0';
signal FIFO_rsp_empty : STD_LOGIC;
signal FIFO_rsp_full : STD_LOGIC;
signal FIFO_rsp_write : STD_LOGIC;
signal FIFO_req_temp_state : STD_LOGIC_VECTOR(1 downto 0) := "00";
type arr_fifo_req_RW is array(0 to FIFO_DEPTH - 1) of STD_LOGIC;
type arr_fifo_req_addr is array(0 to FIFO_DEPTH - 1) of STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
type arr_fifo_req_din is array(0 to FIFO_DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
type arr_fifo_req_size is array(0 to FIFO_DEPTH - 1) of STD_LOGIC_VECTOR(31 downto 0);
type arr_mem is array(0 to DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
shared variable FIFO_req_RW : arr_fifo_req_RW;
shared variable FIFO_req_address: arr_fifo_req_addr;
shared variable FIFO_req_din : arr_fifo_req_din;
shared variable FIFO_req_size : arr_fifo_req_size;
shared variable mem : arr_mem := (others => (others => '0'));
shared variable FIFO_rsp_mem : arr_mem := (others => (others => '0'));
procedure esl_read_token (file textfile: TEXT; textline: inout LINE; token: out STRING; token_len: out INTEGER) is
variable whitespace : CHARACTER;
variable i : INTEGER;
variable ok: BOOLEAN;
variable buff: STRING(1 to token'length);
begin
ok := false;
i := 1;
loop_main: while not endfile(textfile) loop
if textline = null or textline'length = 0 then
readline(textfile, textline);
end if;
loop_remove_whitespace: while textline'length > 0 loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
read(textline, whitespace);
else
exit loop_remove_whitespace;
end if;
end loop;
loop_aesl_read_token: while textline'length > 0 and i <= buff'length loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
exit loop_aesl_read_token;
else
read(textline, buff(i));
i := i + 1;
end if;
ok := true;
end loop;
if ok = true then
exit loop_main;
end if;
end loop;
buff(i) := ' ';
token := buff;
token_len:= i-1;
end procedure esl_read_token;
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING) is
variable i : INTEGER;
begin
esl_read_token (textfile, textline, token, i);
end procedure esl_read_token;
function esl_add(v1, v2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable res : unsigned(v1'length-1 downto 0);
begin
res := unsigned(v1) + unsigned(v2);
return std_logic_vector(res);
end function;
function esl_sub(v1, v2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable res : unsigned(v1'length-1 downto 0);
begin
res := unsigned(v1) - unsigned(v2);
return std_logic_vector(res);
end function;
function esl_str2lv_hex (RHS : STRING; data_width : INTEGER) return STD_LOGIC_VECTOR is
variable ret : STD_LOGIC_VECTOR(data_width - 1 downto 0);
variable idx : integer := 3;
begin
ret := (others => '0');
if(RHS(1) /= '0' and (RHS(2) /= 'x' or RHS(2) /= 'X')) then
report "Error! The format of hex number is not initialed by 0x";
end if;
while true loop
if (data_width > 4) then
case RHS(idx) is
when '0' => ret := ret(data_width - 5 downto 0) & "0000";
when '1' => ret := ret(data_width - 5 downto 0) & "0001";
when '2' => ret := ret(data_width - 5 downto 0) & "0010";
when '3' => ret := ret(data_width - 5 downto 0) & "0011";
when '4' => ret := ret(data_width - 5 downto 0) & "0100";
when '5' => ret := ret(data_width - 5 downto 0) & "0101";
when '6' => ret := ret(data_width - 5 downto 0) & "0110";
when '7' => ret := ret(data_width - 5 downto 0) & "0111";
when '8' => ret := ret(data_width - 5 downto 0) & "1000";
when '9' => ret := ret(data_width - 5 downto 0) & "1001";
when 'a' | 'A' => ret := ret(data_width - 5 downto 0) & "1010";
when 'b' | 'B' => ret := ret(data_width - 5 downto 0) & "1011";
when 'c' | 'C' => ret := ret(data_width - 5 downto 0) & "1100";
when 'd' | 'D' => ret := ret(data_width - 5 downto 0) & "1101";
when 'e' | 'E' => ret := ret(data_width - 5 downto 0) & "1110";
when 'f' | 'F' => ret := ret(data_width - 5 downto 0) & "1111";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 4) then
case RHS(idx) is
when '0' => ret := "0000";
when '1' => ret := "0001";
when '2' => ret := "0010";
when '3' => ret := "0011";
when '4' => ret := "0100";
when '5' => ret := "0101";
when '6' => ret := "0110";
when '7' => ret := "0111";
when '8' => ret := "1000";
when '9' => ret := "1001";
when 'a' | 'A' => ret := "1010";
when 'b' | 'B' => ret := "1011";
when 'c' | 'C' => ret := "1100";
when 'd' | 'D' => ret := "1101";
when 'e' | 'E' => ret := "1110";
when 'f' | 'F' => ret := "1111";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 3) then
case RHS(idx) is
when '0' => ret := "000";
when '1' => ret := "001";
when '2' => ret := "010";
when '3' => ret := "011";
when '4' => ret := "100";
when '5' => ret := "101";
when '6' => ret := "110";
when '7' => ret := "111";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 2) then
case RHS(idx) is
when '0' => ret := "00";
when '1' => ret := "01";
when '2' => ret := "10";
when '3' => ret := "11";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 1) then
case RHS(idx) is
when '0' => ret := "0";
when '1' => ret := "1";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
else
report string'("Wrong data_width.");
return ret;
end if;
idx := idx + 1;
end loop;
return ret;
end function;
function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING is
constant str_len : integer := (lv'length + 3)/4;
variable ret : STRING (1 to str_len);
variable i, tmp: INTEGER;
variable normal_lv : STD_LOGIC_VECTOR(lv'length - 1 downto 0);
variable tmp_lv : STD_LOGIC_VECTOR(3 downto 0);
begin
normal_lv := lv;
for i in 1 to str_len loop
if(i = 1) then
if((lv'length mod 4) = 3) then
tmp_lv(2 downto 0) := normal_lv(lv'length - 1 downto lv'length - 3);
case tmp_lv(2 downto 0) is
when "000" => ret(i) := '0';
when "001" => ret(i) := '1';
when "010" => ret(i) := '2';
when "011" => ret(i) := '3';
when "100" => ret(i) := '4';
when "101" => ret(i) := '5';
when "110" => ret(i) := '6';
when "111" => ret(i) := '7';
when others => ret(i) := '0';
end case;
elsif((lv'length mod 4) = 2) then
tmp_lv(1 downto 0) := normal_lv(lv'length - 1 downto lv'length - 2);
case tmp_lv(1 downto 0) is
when "00" => ret(i) := '0';
when "01" => ret(i) := '1';
when "10" => ret(i) := '2';
when "11" => ret(i) := '3';
when others => ret(i) := '0';
end case;
elsif((lv'length mod 4) = 1) then
tmp_lv(0 downto 0) := normal_lv(lv'length - 1 downto lv'length - 1);
case tmp_lv(0 downto 0) is
when "0" => ret(i) := '0';
when "1" => ret(i) := '1';
when others=> ret(i) := '0';
end case;
elsif((lv'length mod 4) = 0) then
tmp_lv(3 downto 0) := normal_lv(lv'length - 1 downto lv'length - 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := '0';
end case;
end if;
else
tmp_lv(3 downto 0) := normal_lv((str_len - i) * 4 + 3 downto (str_len - i) * 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := '0';
end case;
end if;
end loop;
return ret;
end function;
begin
-------------- Assignment for output port -------------------
assign_proc : process
begin
wait until (clk'event and clk = '1');
wait for 0.4 ns;
bus_dout <= FIFO_rsp_mem(CONV_INTEGER(FIFO_rsp_ptr_r));
end process;
bus_rsp_proc : process(FIFO_rsp_empty)
begin
bus_rsp_empty_n <= not FIFO_rsp_empty;
end process;
bus_req_full_n_proc : process(FIFO_req_full)
begin
bus_req_full_n <= not FIFO_req_full;
end process;
FIFO_req_empty_full_proc : process(FIFO_req_ptr_r, FIFO_req_ptr_w, FIFO_req_flag)
begin
if(FIFO_req_ptr_r = FIFO_req_ptr_w) then
if(FIFO_req_flag = '1') then
FIFO_req_full <= '1';
FIFO_req_empty <= '0';
else
FIFO_req_full <= '0';
FIFO_req_empty <= '1';
end if;
else
FIFO_req_full <= '0';
FIFO_req_empty <= '0';
end if;
end process;
FIFO_rsp_empty_full_proc : process(FIFO_rsp_ptr_r, FIFO_rsp_ptr_w, FIFO_rsp_flag)
begin
if(FIFO_rsp_ptr_r = FIFO_rsp_ptr_w) then
if(FIFO_rsp_flag = '1') then
FIFO_rsp_full <= '1';
FIFO_rsp_empty <= '0';
else
FIFO_rsp_full <= '0';
FIFO_rsp_empty <= '1';
end if;
else
FIFO_rsp_full <= '0';
FIFO_rsp_empty <= '0';
end if;
end process;
-- Push RTL's req into FIFO_req
FIFO_req_write_proc : process(clk, rst)
begin
if(rst = '1') then
FIFO_req_ptr_w <= (others => '0');
elsif (clk'event and clk = '1') then
if(bus_req_RW_en = '1' and FIFO_req_full = '0') then
FIFO_req_RW(CONV_INTEGER(FIFO_req_ptr_w)) := bus_req_RW;
FIFO_req_address(CONV_INTEGER(FIFO_req_ptr_w)) := bus_address;
FIFO_req_din(CONV_INTEGER(FIFO_req_ptr_w)) := bus_din;
FIFO_req_size(CONV_INTEGER(FIFO_req_ptr_w)) := bus_size;
if(CONV_INTEGER(FIFO_req_ptr_w) /= FIFO_DEPTH - 1) then
FIFO_req_ptr_w <= esl_add(FIFO_req_ptr_w,"1");
else
FIFO_req_ptr_w <= (others => '0');
end if;
end if;
end if;
end process;
FIFO_req_read_proc : process(clk, rst)
variable FIFO_req_RW_temp : STD_LOGIC;
variable FIFO_req_address_temp : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
variable FIFO_req_din_temp : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
variable FIFO_req_size_temp : STD_LOGIC_VECTOR(31 downto 0);
constant IDLE_STATE : STD_LOGIC_VECTOR(1 downto 0) := "00";
constant READ_BURST_STATE : STD_LOGIC_VECTOR(1 downto 0) := "01";
constant WRITE_BURST_STATE : STD_LOGIC_VECTOR(1 downto 0) := "10";
begin
if(rst = '1') then
FIFO_req_temp_state <= IDLE_STATE;
FIFO_req_read <= '0';
FIFO_rsp_write <= '0';
elsif (clk'event and clk = '1') then
case FIFO_req_temp_state is
when IDLE_STATE =>
if(FIFO_req_empty = '0' and FIFO_rsp_full = '0') then
FIFO_req_read <= '1';
if(CONV_INTEGER(FIFO_req_ptr_r) /= FIFO_DEPTH - 1) then
FIFO_req_ptr_r <= esl_add(FIFO_req_ptr_r, "1");
else
FIFO_req_ptr_r <= (others => '0');
end if;
FIFO_req_RW_temp:= FIFO_req_RW(CONV_INTEGER(FIFO_req_ptr_r));
FIFO_req_address_temp := FIFO_req_address(CONV_INTEGER(FIFO_req_ptr_r));
FIFO_req_din_temp := FIFO_req_din(CONV_INTEGER(FIFO_req_ptr_r));
FIFO_req_size_temp := FIFO_req_size(CONV_INTEGER(FIFO_req_ptr_r));
-- Read request
if(FIFO_req_RW_temp = '0') then
FIFO_rsp_write <= '1'; -- Indicate the output is valid
FIFO_rsp_mem(CONV_INTEGER(FIFO_rsp_ptr_w)) := mem(CONV_INTEGER(FIFO_req_address_temp));
if(FIFO_rsp_ptr_w /= DEPTH - 1) then
FIFO_rsp_ptr_w <= esl_add(FIFO_rsp_ptr_w,"1");
else
FIFO_rsp_ptr_w <= (others => '0');
end if;
if(CONV_INTEGER(FIFO_req_size_temp) /= 0 and CONV_INTEGER(FIFO_req_size_temp) /= 1) then -- Read burst request
FIFO_req_temp_state <= READ_BURST_STATE; -- To deal with the rest data
end if;
else
FIFO_rsp_write <= '0'; -- Indicate the output is not valid
if(CONV_INTEGER(FIFO_req_size_temp) = 0 or CONV_INTEGER(FIFO_req_size_temp) = 1) then -- Write single request
mem(CONV_INTEGER(FIFO_req_address_temp)) := FIFO_req_din_temp;
else -- Write burst request
mem(CONV_INTEGER(FIFO_req_address_temp)) := FIFO_req_din_temp; -- Input the first data
FIFO_req_temp_state <= WRITE_BURST_STATE; -- To deal with the rest data
end if;
end if;
else -- There is no request in the FIFO_req
FIFO_req_read <= '0';
FIFO_rsp_write <= '0';
end if;
when READ_BURST_STATE =>
FIFO_req_read <= '0'; -- Stop reading the next request
FIFO_req_size_temp := esl_sub(FIFO_req_size_temp, "1");
if(CONV_INTEGER(FIFO_req_address_temp) /= DEPTH - 1) then
FIFO_req_address_temp := esl_add(FIFO_req_address_temp, "1");
else
report "Burst read out of size!";
end if;
FIFO_rsp_mem(CONV_INTEGER(FIFO_rsp_ptr_w)) := mem(CONV_INTEGER(FIFO_req_address_temp));
if(CONV_INTEGER(FIFO_rsp_ptr_w) /= DEPTH - 1) then
FIFO_rsp_ptr_w <= esl_add(FIFO_rsp_ptr_w, "1");
else
FIFO_rsp_ptr_w <= (others => '0');
end if;
if(CONV_INTEGER(FIFO_req_size_temp) = 1) then -- The last one is done
FIFO_req_temp_state <= IDLE_STATE;
end if;
when WRITE_BURST_STATE =>
if(FIFO_req_empty = '0') then
FIFO_req_read <= '1'; -- Keep reading the next data(The data is storaged in FIFO_req but it is not a request)
if(CONV_INTEGER(FIFO_req_ptr_r) /= FIFO_DEPTH - 1) then
FIFO_req_ptr_r <= esl_add(FIFO_req_ptr_r, "1");
else
FIFO_req_ptr_r <= (others => '0');
end if;
FIFO_req_size_temp := esl_sub(FIFO_req_size_temp, "1");
if(CONV_INTEGER(FIFO_req_address_temp) /= DEPTH - 1) then
FIFO_req_address_temp := esl_add(FIFO_req_address_temp, "1");
else
report "Burst write out of size!";
end if;
mem(CONV_INTEGER(FIFO_req_address_temp)) := FIFO_req_din(CONV_INTEGER(FIFO_req_ptr_r));
if(CONV_INTEGER(FIFO_req_size_temp) = 1) then -- The last one is done
FIFO_req_temp_state <= IDLE_STATE;
end if;
end if;
when OTHERS =>
FIFO_req_temp_state <= IDLE_STATE;
end case;
end if;
end process;
-- Generate "FIFO_req_flag"
FIFO_req_flag_proc : process
begin
wait until clk'event and clk = '1';
if(rst = '1') then
FIFO_req_flag <= '0';
else
if((bus_req_RW_en = '1' and FIFO_req_full /= '1') and CONV_INTEGER(FIFO_req_ptr_w) = FIFO_DEPTH - 1) then
FIFO_req_flag <= '1';
end if;
wait for 0.4 ns;
if((FIFO_req_read = '1' and FIFO_req_empty /= '1') and CONV_INTEGER(FIFO_req_ptr_r) = 0) then
FIFO_req_flag <= '0';
end if;
end if;
end process;
-- Generate "FIFO_rsp_flag"
FIFO_rsp_flag_proc : process
begin
wait until clk'event and clk = '1';
if(rst = '1') then
FIFO_rsp_flag <= '0';
else
if((bus_rsp_read = '1' and FIFO_rsp_empty /= '1') and CONV_INTEGER(FIFO_rsp_ptr_r) = DEPTH - 1) then
FIFO_rsp_flag <= '0';
end if;
wait for 0.4 ns;
if((FIFO_rsp_write = '1' and FIFO_rsp_full /= '1') and CONV_INTEGER(FIFO_rsp_ptr_w) = 0) then
FIFO_rsp_flag <= '1';
end if;
end if;
end process;
-- Pop data from FIFO_rsp
FIFO_rsp_ptr_r_proc : process(clk, rst)
begin
if(rst = '1') then
FIFO_rsp_ptr_r <= (others => '0');
elsif (clk'event and clk = '1') then
if(bus_rsp_read = '1' and FIFO_rsp_empty /= '1') then
if(CONV_INTEGER(FIFO_rsp_ptr_r) /= DEPTH - 1) then
FIFO_rsp_ptr_r <= esl_add(FIFO_rsp_ptr_r, "1");
else
FIFO_rsp_ptr_r <= (others => '0');
end if;
end if;
end if;
end process;
----------------------------Read file-------------------
-- Read data from file
read_file_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 128 );
variable token_len : INTEGER;
variable token_int : INTEGER;
variable idx : INTEGER;
--variable mem_var : arr2D;
begin
file_open(fstatus, fp, TV_IN, READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & TV_IN & " failed!!!" severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
report "The token is " & token;
assert false report "Illegal format of [[[runtime]]] part in " & TV_IN severity failure;
end if;
esl_read_token(fp, token_line, token);
while(token(1 to 14) /= "[[[/runtime]]]") loop
if(token(1 to 15) /= "[[transaction]]") then
report "The token is " & token;
assert false report "Illegal format of [[transaction]] part in " & TV_IN severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
-- Start to read data for every transaction round
wait until clk'event and clk = '1';
wait for 0.2 ns;
while(ready /= '1') loop
wait until clk'event and clk = '1';
wait for 0.2 ns;
end loop;
for i in 0 to DEPTH - 1 loop
esl_read_token(fp, token_line, token);
mem(i) := esl_str2lv_hex(token, DATA_WIDTH);
end loop;
esl_read_token(fp, token_line, token);
if(token(1 to 16) /= "[[/transaction]]") then
report "The token is " & token;
assert false report "Illegal format of [[/transaction]] part in " & TV_IN severity failure;
end if;
esl_read_token(fp, token_line, token);
end loop;
file_close(fp);
wait;
end process;
----------------------------Write file-------------------
-- Write data to file
write_file_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 128 );
variable transaction_idx : INTEGER;
begin
wait until (rst = '0');
transaction_idx := 0;
while(true) loop
wait until clk'event and clk = '1';
while(done /= '1') loop
wait until clk'event and clk = '1';
end loop;
wait for 0.1 ns;
file_open(fstatus, fp, TV_OUT, APPEND_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & TV_OUT & " failed!!!" severity failure;
end if;
write(token_line, "[[transaction]] " & integer'image(transaction_idx));
writeline(fp, token_line);
for i in 0 to DEPTH - 1 loop
write(token_line, "0x" & esl_conv_string_hex(mem(i)));
writeline(fp, token_line);
end loop;
write(token_line, string'("[[/transaction]]"));
writeline(fp, token_line);
transaction_idx := transaction_idx + 1;
file_close(fp);
end loop;
wait;
end process;
end behav;
| lgpl-3.0 | a2ebb3b56400a9bdabe6cafde0b84482 | 0.431331 | 3.803285 | false | false | false | false |
grwlf/vsim | vhdl/bigvector2.vhd | 1 | 644 | entity test is
end entity test;
architecture test_arch of test is
constant CYCLES : integer := 100;
constant size : integer := 16#10000#;
-- constant size : integer := 16#2#;
type vector_t is array (0 to size-1) of integer;
signal big_vector : vector_t;
signal clk : integer := 0;
begin
main: process(clk)
begin
for i in 0 to size-1 loop
big_vector(i) <= clk;
end loop;
end process;
terminator : process(clk)
begin
if clk >= CYCLES then
assert false report "end of simulation" severity failure;
-- else
-- report "tick";
end if;
end process;
clk <= (clk+1) after 1 us;
end architecture test_arch;
| gpl-3.0 | 06db1138ce3cf8ae5ade8c433cd5151e | 0.659938 | 3.111111 | false | true | false | false |
TWW12/lzw | ip_repo/axi_compression_1.0/src/dictionary_block.vhd | 4 | 4,106 | --4096-entry dictionary block
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity dictionary_block is
port (
clk : in std_logic;
rst : in std_logic;
start_search : in std_logic;
search_entry : in std_logic_vector(19 downto 0);
--Write enable & entries
wr_en : in std_logic;
wr_entry : in std_logic_vector(19 downto 0);
--Outputs
prefix : out std_logic_vector(11 downto 0);
entry_found : out std_logic;
search_completed : out std_logic;
dictionary_full : out std_logic);
end dictionary_block;
architecture Behavioral of dictionary_block is
component bram_4096 is
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0)
);
end component;
type state_type is (S_RST,S_GO,S_SEARCH);
signal state : state_type;
signal rd_addr : std_logic_vector(12 downto 0);
signal wr_addr : std_logic_vector(12 downto 0);
signal addr : std_logic_vector(11 downto 0);
signal bram_out : std_logic_vector(19 downto 0);
signal full : std_logic;
begin
dictionary_full <= full;
U_BRAM : bram_4096
port map(
clka => clk,
ena => '1',
wea(0) => wr_en,
addra => addr,
dina => wr_entry,
douta => bram_out);
with wr_en select addr <=
wr_addr(11 downto 0) when '1',
rd_addr(11 downto 0) when others;
process(clk,rst)
begin
if rst = '1' then
state <= S_RST;
rd_addr <= (rd_addr'range => '0');
entry_found <= '0';
search_completed <= '0';
prefix <= (prefix'range => '0');
elsif rising_edge(clk) then
case state is
when S_RST =>
state <= S_GO;
--idle until its time to search
when S_GO =>
rd_addr <= (rd_addr'range => '0');
entry_found <= '0';
search_completed <= '0';
prefix <= (prefix'range => '0');
if start_search = '1' then
state <= S_SEARCH;
end if;
when S_SEARCH =>
rd_addr <= std_logic_vector(unsigned(rd_addr)+to_unsigned(1,13));
--Did we find the entry?
if search_entry = bram_out then
state <= S_GO;
entry_found <= '1';
search_completed <= '1';
prefix <= std_logic_vector(unsigned(rd_addr(11 downto 0))-to_unsigned(1,12));
end if;
--Did we go through the whole dictionary?
if rd_addr = std_logic_vector(unsigned(wr_addr)+to_unsigned(1,13)) then
state <= S_GO;
search_completed <= '1';
end if;
end case;
end if;
end process;
--write proc
process(clk,rst)
begin
if rst = '1' then
wr_addr <= std_logic_vector(to_unsigned(255,13));
full <= '0';
elsif rising_edge(clk) then
if wr_en = '1' and full = '0' then
wr_addr <= std_logic_vector(to_unsigned(1,13)+unsigned(wr_addr));
end if;
--last entry written should increment counter to "1000...000"
if wr_addr(12) = '1' then
full <= '1';
end if;
end if;
end process;
end Behavioral;
| unlicense | 47f639e3a588b00cea5e433dcdd9ed0b | 0.448612 | 4.202661 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00478.vhd | 1 | 4,371 | -- NEED RESULT: ARCH00478: Choices in an element association of an aggregate may contain several or no choices passed
-- NEED RESULT: ARCH00478: Element simple name properly disambiguated from simple expressions in aggregate element associations passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00478
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.3.2 (3)
-- 7.3.2 (4)
-- 7.3.2 (5)
-- 7.3.2 (6)
-- 7.3.2 (8)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00478)
-- ENT00478_Test_Bench(ARCH00478_Test_Bench)
--
-- REVISION HISTORY:
--
-- 6-AUG-1987 - initial revision
-- 5-MAY-1988 -CSW
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00478 of E00000 is
type rec_1 is record
f1 : integer ;
f2 : integer ;
f3 : boolean ;
f4 : real ;
end record ;
type rec_2 is record
f1 : integer ;
end record ;
type arr_1 is array ( integer range <> ) of rec_1 ;
begin
process
constant c_int1 : integer := 1 ;
constant f1 : integer := 3 ;
variable v_int1 : integer := 10 ;
variable v_int2 : integer := 1 ;
variable v_int3 : integer := 5 ;
variable v_bool1 : boolean := true ;
variable v_real1 : real := 3.5 ;
subtype st_arr_1 is arr_1 ( 1 to 4 ) ;
subtype st_arr_2 is arr_1 ( v_int2 to v_int3 ) ;
subtype st_arr_3 is arr_1 ( 2 to 2 ) ;
variable v_arr_1_1, v_arr_1_2 : st_arr_1 ;
variable v_arr_2_1, v_arr_2_2 : st_arr_2 ;
variable v_arr_3_1, v_arr_3_2 : st_arr_3 ;
variable v_rec_1_1, v_rec_1_2 : rec_1 ;
variable v_rec_2_2 : rec_2 ;
variable bool : boolean := true ;
begin
v_rec_1_1 := ( v_int1, v_int2, v_bool1, v_real1 );
v_rec_1_2 := ( f1 | f2 => 3 , f3 => false , f4 => 0.0 ) ;
v_arr_1_1 := ( 1 to 2 | f1 | 4 => v_rec_1_1 ) ;
v_arr_1_2 := ( 1 to 2 | 10 - 6 downto 3 + c_int1 => v_rec_1_2,
others => v_rec_1_1 ) ;
v_arr_2_1 := ( v_rec_1_1, v_rec_1_2, v_rec_1_1, v_rec_1_1, v_rec_1_2 ) ;
v_arr_2_2 := ( 5 downto 1 => v_rec_1_1 ) ;
v_arr_3_1 := ( 2 to 2 => v_rec_1_2 ) ;
v_arr_3_2 := ( others => v_rec_1_1 ) ;
bool := bool and v_rec_1_1.f1 = v_int1 ;
bool := bool and v_rec_1_1.f2 = v_int2 ;
bool := bool and v_rec_1_1.f3 = v_bool1 ;
bool := bool and v_rec_1_1.f4 = v_real1 ;
for i in 1 to 4 loop
bool := bool and v_arr_1_1(i) = v_rec_1_1 ;
end loop ;
bool := bool and v_arr_1_2(1) = v_rec_1_2 ;
bool := bool and v_arr_1_2(2) = v_rec_1_2 ;
bool := bool and v_arr_1_2(3) = v_rec_1_1 ;
bool := bool and v_arr_1_2(4) = v_rec_1_2 ;
bool := bool and v_arr_2_1(1) = v_rec_1_1 ;
bool := bool and v_arr_2_1(2) = v_rec_1_2 ;
bool := bool and v_arr_2_1(3) = v_rec_1_1 ;
bool := bool and v_arr_2_1(4) = v_rec_1_1 ;
bool := bool and v_arr_2_1(5) = v_rec_1_2 ;
for i in 5 downto 1 loop
bool := bool and v_arr_2_2(i) = v_rec_1_1 ;
end loop ;
bool := bool and v_arr_3_1(2) = v_rec_1_2 ;
bool := bool and v_arr_3_2(2) = v_rec_1_1 ;
test_report ( "ARCH00478" ,
"Choices in an element association of an aggregate"
& " may contain several or no choices" ,
bool ) ;
v_rec_2_2 := ( f1 => f1 ) ;
v_arr_1_1 := ( f1 => v_rec_1_2, others => v_rec_1_1 ) ;
test_report ( "ARCH00478" ,
"Element simple name properly disambiguated from simple"
& " expressions in aggregate element associations" ,
v_rec_2_2.f1 = 3 and v_arr_1_1(3) = v_rec_1_2 ) ;
wait ;
end process ;
end ARCH00478 ;
entity ENT00478_Test_Bench is
end ENT00478_Test_Bench ;
architecture ARCH00478_Test_Bench of ENT00478_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00478 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00478_Test_Bench ;
| gpl-3.0 | 8fd243dd3a8f17118d91060809c0158f | 0.497827 | 2.775238 | false | true | false | false |
grwlf/vsim | vhdl/entity2.vhd | 1 | 849 | -- Simple entity test, array and indexed mappings
entity main is
end entity main;
entity unit1 is
port (
inum : in integer;
oled : out integer);
end entity unit1;
architecture unit1_a of unit1 is
signal a : integer := 1;
begin
oled <= inum + a;
end architecture unit1_a;
architecture main of main is
constant CYCLES : integer := 100;
signal clk : integer := 0;
type arr is array (0 to 1) of integer;
signal oi : arr := (others => 0);
signal o : integer;
begin
terminator : process(clk)
begin
if clk >= CYCLES then
assert false report "end of simulation" severity failure;
end if;
end process;
u1:entity unit1(unit1_a) port map(inum=>clk, oled=>oi(0));
u2:entity unit1(unit1_a) port map(inum=>clk, oled=>oi(1));
clk <= clk + 1 after 1 us;
o <= oi(0) + oi(1);
end architecture main;
| gpl-3.0 | aa54b31f79717bcc73ca7ba9d05e3c14 | 0.648999 | 3.156134 | false | false | false | false |
jairov4/accel-oil | impl/impl_test_pcie/simulation/behavioral/system_pcie_bridge_wrapper.vhd | 1 | 14,507 | -------------------------------------------------------------------------------
-- system_pcie_bridge_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plbv46_pcie_v4_07_a;
use plbv46_pcie_v4_07_a.all;
entity system_pcie_bridge_wrapper is
port (
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to 63);
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrBTerm : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_buslock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to 7);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_TAttribute : out std_logic_vector(0 to 15);
M_UABus : out std_logic_vector(0 to 31);
M_ABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to 63);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 2);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 7);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 63);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 63);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 5);
Sl_MWrErr : out std_logic_vector(0 to 5);
Sl_MRdErr : out std_logic_vector(0 to 5);
Sl_MIRQ : out std_logic_vector(0 to 5);
REFCLK : in std_logic;
Bridge_Clk : out std_logic;
RXN : in std_logic_vector(0 to 0);
RXP : in std_logic_vector(0 to 0);
TXN : out std_logic_vector(0 to 0);
TXP : out std_logic_vector(0 to 0);
IP2INTC_Irpt : out std_logic;
MSI_request : in std_logic
);
end system_pcie_bridge_wrapper;
architecture STRUCTURE of system_pcie_bridge_wrapper is
component plbv46_pcie is
generic (
C_FAMILY : STRING;
C_SUBFAMILY : STRING;
C_IPIFBAR_NUM : INTEGER;
C_INCLUDE_BAROFFSET_REG : INTEGER;
C_PCIBAR_NUM : INTEGER;
C_NO_OF_LANES : INTEGER;
C_DEVICE_ID : std_logic_vector;
C_VENDOR_ID : std_logic_vector;
C_CLASS_CODE : std_logic_vector;
C_REF_CLK_FREQ : integer;
C_REV_ID : std_logic_vector;
C_SUBSYSTEM_ID : std_logic_vector;
C_SUBSYSTEM_VENDOR_ID : std_logic_vector;
C_COMP_TIMEOUT : INTEGER;
C_INCLUDE_RC : INTEGER;
C_MPLB_AWIDTH : INTEGER;
C_MPLB_DWIDTH : INTEGER;
C_MPLB_SMALLEST_SLAVE : INTEGER;
C_MPLB_NATIVE_DWIDTH : INTEGER;
C_SPLB_MID_WIDTH : INTEGER;
C_SPLB_NUM_MASTERS : INTEGER;
C_SPLB_SMALLEST_MASTER : INTEGER;
C_SPLB_AWIDTH : INTEGER;
C_BASEADDR : std_logic_vector;
C_HIGHADDR : std_logic_vector;
C_SPLB_DWIDTH : INTEGER;
C_SPLB_NATIVE_DWIDTH : INTEGER;
C_IPIFBAR_0 : std_logic_vector;
C_IPIFBAR_1 : std_logic_vector;
C_IPIFBAR_2 : std_logic_vector;
C_IPIFBAR_3 : std_logic_vector;
C_IPIFBAR_4 : std_logic_vector;
C_IPIFBAR_5 : std_logic_vector;
C_IPIFBAR_HIGHADDR_0 : std_logic_vector;
C_IPIFBAR_HIGHADDR_1 : std_logic_vector;
C_IPIFBAR_HIGHADDR_2 : std_logic_vector;
C_IPIFBAR_HIGHADDR_3 : std_logic_vector;
C_IPIFBAR_HIGHADDR_4 : std_logic_vector;
C_IPIFBAR_HIGHADDR_5 : std_logic_vector;
C_IPIFBAR2PCIBAR_0 : std_logic_vector;
C_IPIFBAR2PCIBAR_1 : std_logic_vector;
C_IPIFBAR2PCIBAR_2 : std_logic_vector;
C_IPIFBAR2PCIBAR_3 : std_logic_vector;
C_IPIFBAR2PCIBAR_4 : std_logic_vector;
C_IPIFBAR2PCIBAR_5 : std_logic_vector;
C_IPIFBAR_AS_0 : INTEGER;
C_IPIFBAR_AS_1 : INTEGER;
C_IPIFBAR_AS_2 : INTEGER;
C_IPIFBAR_AS_3 : INTEGER;
C_IPIFBAR_AS_4 : INTEGER;
C_IPIFBAR_AS_5 : INTEGER;
C_IPIFBAR_SPACE_TYPE_0 : INTEGER;
C_IPIFBAR_SPACE_TYPE_1 : INTEGER;
C_IPIFBAR_SPACE_TYPE_2 : INTEGER;
C_IPIFBAR_SPACE_TYPE_3 : INTEGER;
C_IPIFBAR_SPACE_TYPE_4 : INTEGER;
C_IPIFBAR_SPACE_TYPE_5 : INTEGER;
C_ECAM_BASEADDR : std_logic_vector;
C_ECAM_HIGHADDR : std_logic_vector;
C_PCIBAR2IPIFBAR_0 : std_logic_vector;
C_PCIBAR2IPIFBAR_1 : std_logic_vector;
C_PCIBAR2IPIFBAR_2 : std_logic_vector;
C_PCIBAR_LEN_0 : INTEGER;
C_PCIBAR_LEN_1 : INTEGER;
C_PCIBAR_LEN_2 : INTEGER;
C_PCIBAR_AS : INTEGER;
C_PCIE_CAP_SLOT_IMPLEMENTED : INTEGER
);
port (
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_MPLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrBTerm : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_buslock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to ((C_MPLB_DWIDTH/8)-1));
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_TAttribute : out std_logic_vector(0 to 15);
M_UABus : out std_logic_vector(0 to 31);
M_ABus : out std_logic_vector(0 to (C_MPLB_AWIDTH-1));
M_wrDBus : out std_logic_vector(0 to (C_MPLB_DWIDTH-1));
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1));
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1));
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1));
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1));
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
REFCLK : in std_logic;
Bridge_Clk : out std_logic;
RXN : in std_logic_vector((C_NO_OF_LANES-1) to 0);
RXP : in std_logic_vector((C_NO_OF_LANES-1) to 0);
TXN : out std_logic_vector((C_NO_OF_LANES-1) to 0);
TXP : out std_logic_vector((C_NO_OF_LANES-1) to 0);
IP2INTC_Irpt : out std_logic;
MSI_request : in std_logic
);
end component;
begin
PCIe_Bridge : plbv46_pcie
generic map (
C_FAMILY => "virtex5",
C_SUBFAMILY => "lx",
C_IPIFBAR_NUM => 2,
C_INCLUDE_BAROFFSET_REG => 0,
C_PCIBAR_NUM => 1,
C_NO_OF_LANES => 1,
C_DEVICE_ID => X"0505",
C_VENDOR_ID => X"10EE",
C_CLASS_CODE => X"058000",
C_REF_CLK_FREQ => 0,
C_REV_ID => X"00",
C_SUBSYSTEM_ID => X"0000",
C_SUBSYSTEM_VENDOR_ID => X"0000",
C_COMP_TIMEOUT => 1,
C_INCLUDE_RC => 0,
C_MPLB_AWIDTH => 32,
C_MPLB_DWIDTH => 64,
C_MPLB_SMALLEST_SLAVE => 32,
C_MPLB_NATIVE_DWIDTH => 64,
C_SPLB_MID_WIDTH => 3,
C_SPLB_NUM_MASTERS => 6,
C_SPLB_SMALLEST_MASTER => 32,
C_SPLB_AWIDTH => 32,
C_BASEADDR => X"85c00000",
C_HIGHADDR => X"85c0ffff",
C_SPLB_DWIDTH => 64,
C_SPLB_NATIVE_DWIDTH => 64,
C_IPIFBAR_0 => X"E0000000",
C_IPIFBAR_1 => X"b0000000",
C_IPIFBAR_2 => X"FFFFFFFF",
C_IPIFBAR_3 => X"FFFFFFFF",
C_IPIFBAR_4 => X"FFFFFFFF",
C_IPIFBAR_5 => X"FFFFFFFF",
C_IPIFBAR_HIGHADDR_0 => X"FFFFFFFF",
C_IPIFBAR_HIGHADDR_1 => X"bfffffff",
C_IPIFBAR_HIGHADDR_2 => X"00000000",
C_IPIFBAR_HIGHADDR_3 => X"00000000",
C_IPIFBAR_HIGHADDR_4 => X"00000000",
C_IPIFBAR_HIGHADDR_5 => X"00000000",
C_IPIFBAR2PCIBAR_0 => X"00000000",
C_IPIFBAR2PCIBAR_1 => X"00000000",
C_IPIFBAR2PCIBAR_2 => X"FFFFFFFF",
C_IPIFBAR2PCIBAR_3 => X"FFFFFFFF",
C_IPIFBAR2PCIBAR_4 => X"FFFFFFFF",
C_IPIFBAR2PCIBAR_5 => X"FFFFFFFF",
C_IPIFBAR_AS_0 => 0,
C_IPIFBAR_AS_1 => 0,
C_IPIFBAR_AS_2 => 0,
C_IPIFBAR_AS_3 => 0,
C_IPIFBAR_AS_4 => 0,
C_IPIFBAR_AS_5 => 0,
C_IPIFBAR_SPACE_TYPE_0 => 1,
C_IPIFBAR_SPACE_TYPE_1 => 1,
C_IPIFBAR_SPACE_TYPE_2 => 1,
C_IPIFBAR_SPACE_TYPE_3 => 1,
C_IPIFBAR_SPACE_TYPE_4 => 1,
C_IPIFBAR_SPACE_TYPE_5 => 1,
C_ECAM_BASEADDR => X"FFFFFFFF",
C_ECAM_HIGHADDR => X"00000000",
C_PCIBAR2IPIFBAR_0 => X"c0000000",
C_PCIBAR2IPIFBAR_1 => X"00000000",
C_PCIBAR2IPIFBAR_2 => X"FFFFFFFF",
C_PCIBAR_LEN_0 => 28,
C_PCIBAR_LEN_1 => 28,
C_PCIBAR_LEN_2 => 16,
C_PCIBAR_AS => 1,
C_PCIE_CAP_SLOT_IMPLEMENTED => 1
)
port map (
MPLB_Clk => MPLB_Clk,
MPLB_Rst => MPLB_Rst,
PLB_MTimeout => PLB_MTimeout,
PLB_MIRQ => PLB_MIRQ,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MSSize => PLB_MSSize,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrBTerm => PLB_MWrBTerm,
M_request => M_request,
M_priority => M_priority,
M_buslock => M_buslock,
M_RNW => M_RNW,
M_BE => M_BE,
M_MSize => M_MSize,
M_size => M_size,
M_type => M_type,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_TAttribute => M_TAttribute,
M_UABus => M_UABus,
M_ABus => M_ABus,
M_wrDBus => M_wrDBus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst,
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
REFCLK => REFCLK,
Bridge_Clk => Bridge_Clk,
RXN => RXN,
RXP => RXP,
TXN => TXN,
TXP => TXP,
IP2INTC_Irpt => IP2INTC_Irpt,
MSI_request => MSI_request
);
end architecture STRUCTURE;
| lgpl-3.0 | 3cc606e7ffb24a49d3e7bb74dd65ef91 | 0.584476 | 3.05282 | false | false | false | false |
jairov4/accel-oil | solution_virtex5/syn/vhdl/bitset_next.vhd | 2 | 20,856 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity bitset_next is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
ap_ce : IN STD_LOGIC;
p_read : IN STD_LOGIC_VECTOR (31 downto 0);
r_bit : IN STD_LOGIC_VECTOR (7 downto 0);
r_bucket_index : IN STD_LOGIC_VECTOR (7 downto 0);
r_bucket : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (7 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (7 downto 0);
ap_return_2 : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_3 : OUT STD_LOGIC_VECTOR (0 downto 0) );
end;
architecture behav of bitset_next is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv32_FFFFFFFF : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111111111";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv8_1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "0";
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal tmp_fu_131_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_reg_214 : STD_LOGIC_VECTOR (1 downto 0);
signal bus_assign_fu_141_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal bus_assign_reg_219 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_3_fu_147_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_3_reg_225 : STD_LOGIC_VECTOR (0 downto 0);
signal agg_result_bit_write_assign_trunc3_ext_fu_165_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_25_1_fu_153_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_27_1_fu_159_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i1_p_bsf32_hw_fu_120_bus_r : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_i1_p_bsf32_hw_fu_120_ap_return : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_i_p_bsf32_hw_fu_126_bus_r : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_i_p_bsf32_hw_fu_126_ap_return : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it0 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it1 : STD_LOGIC_VECTOR (31 downto 0);
signal agg_result_bucket_write_assign_phi_fu_58_p8 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it0 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it1 : STD_LOGIC_VECTOR (0 downto 0);
signal agg_result_end_write_assign_phi_fu_74_p8 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_88pp0_it0 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_88pp0_it1 : STD_LOGIC_VECTOR (1 downto 0);
signal agg_result_bucket_index_write_assign_phi_fu_93_p8 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_phiprechg_agg_result_bit_write_assign_reg_106pp0_it0 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_agg_result_bit_write_assign_reg_106pp0_it1 : STD_LOGIC_VECTOR (7 downto 0);
signal agg_result_bit_write_assign_phi_fu_109_p8 : STD_LOGIC_VECTOR (7 downto 0);
signal agg_result_bit_write_assign_trunc_ext_fu_169_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_1_fu_135_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal agg_result_bucket_index_write_assign_cast_fu_174_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_pprstidle_pp0 : STD_LOGIC;
component p_bsf32_hw IS
port (
bus_r : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (4 downto 0) );
end component;
begin
tmp_i1_p_bsf32_hw_fu_120 : component p_bsf32_hw
port map (
bus_r => tmp_i1_p_bsf32_hw_fu_120_bus_r,
ap_return => tmp_i1_p_bsf32_hw_fu_120_ap_return);
tmp_i_p_bsf32_hw_fu_126 : component p_bsf32_hw
port map (
bus_r => tmp_i_p_bsf32_hw_fu_126_bus_r,
ap_return => tmp_i_p_bsf32_hw_fu_126_ap_return);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end if;
end if;
end if;
end process;
-- ap_reg_phiprechg_agg_result_bit_write_assign_reg_106pp0_it1 assign process. --
ap_reg_phiprechg_agg_result_bit_write_assign_reg_106pp0_it1_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and not((tmp_3_fu_147_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_25_1_fu_153_p2)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and not((tmp_3_fu_147_p2 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_25_1_fu_153_p2)) and not((ap_const_lv1_0 = tmp_27_1_fu_159_p2))))) then
ap_reg_phiprechg_agg_result_bit_write_assign_reg_106pp0_it1 <= r_bit;
elsif (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and not((tmp_3_fu_147_p2 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_25_1_fu_153_p2)) and (ap_const_lv1_0 = tmp_27_1_fu_159_p2))) then
ap_reg_phiprechg_agg_result_bit_write_assign_reg_106pp0_it1 <= agg_result_bit_write_assign_trunc3_ext_fu_165_p1;
elsif (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then
ap_reg_phiprechg_agg_result_bit_write_assign_reg_106pp0_it1 <= ap_reg_phiprechg_agg_result_bit_write_assign_reg_106pp0_it0;
end if;
end if;
end process;
-- ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_88pp0_it1 assign process. --
ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_88pp0_it1_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and not((tmp_3_fu_147_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_25_1_fu_153_p2)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and not((tmp_3_fu_147_p2 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_25_1_fu_153_p2)) and not((ap_const_lv1_0 = tmp_27_1_fu_159_p2))))) then
ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_88pp0_it1 <= ap_const_lv2_2;
elsif (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and not((tmp_3_fu_147_p2 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_25_1_fu_153_p2)) and (ap_const_lv1_0 = tmp_27_1_fu_159_p2))) then
ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_88pp0_it1 <= ap_const_lv2_1;
elsif (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then
ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_88pp0_it1 <= ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_88pp0_it0;
end if;
end if;
end process;
-- ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it1 assign process. --
ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it1_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and not((tmp_3_fu_147_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_25_1_fu_153_p2))) then
ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it1 <= ap_const_lv32_0;
elsif ((((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and not((tmp_3_fu_147_p2 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_25_1_fu_153_p2)) and (ap_const_lv1_0 = tmp_27_1_fu_159_p2)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and not((tmp_3_fu_147_p2 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_25_1_fu_153_p2)) and not((ap_const_lv1_0 = tmp_27_1_fu_159_p2))))) then
ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it1 <= p_read;
elsif (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then
ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it1 <= ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it0;
end if;
end if;
end process;
-- ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it1 assign process. --
ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it1_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and not((tmp_3_fu_147_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_25_1_fu_153_p2)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and not((tmp_3_fu_147_p2 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_25_1_fu_153_p2)) and not((ap_const_lv1_0 = tmp_27_1_fu_159_p2))))) then
ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it1 <= ap_const_lv1_1;
elsif (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and not((tmp_3_fu_147_p2 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_25_1_fu_153_p2)) and (ap_const_lv1_0 = tmp_27_1_fu_159_p2))) then
ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it1 <= ap_const_lv1_0;
elsif (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then
ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it1 <= ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then
bus_assign_reg_219 <= bus_assign_fu_141_p2;
tmp_3_reg_225 <= tmp_3_fu_147_p2;
tmp_reg_214 <= tmp_fu_131_p1;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_ce , ap_sig_pprstidle_pp0)
begin
case ap_CS_fsm is
when ap_ST_pp0_stg0_fsm_0 =>
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
-- agg_result_bit_write_assign_phi_fu_109_p8 assign process. --
agg_result_bit_write_assign_phi_fu_109_p8_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it1, tmp_3_reg_225, ap_reg_phiprechg_agg_result_bit_write_assign_reg_106pp0_it1, agg_result_bit_write_assign_trunc_ext_fu_169_p1)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (tmp_3_reg_225 = ap_const_lv1_0))) then
agg_result_bit_write_assign_phi_fu_109_p8 <= agg_result_bit_write_assign_trunc_ext_fu_169_p1;
else
agg_result_bit_write_assign_phi_fu_109_p8 <= ap_reg_phiprechg_agg_result_bit_write_assign_reg_106pp0_it1;
end if;
end process;
agg_result_bit_write_assign_trunc3_ext_fu_165_p1 <= std_logic_vector(resize(unsigned(tmp_i1_p_bsf32_hw_fu_120_ap_return),8));
agg_result_bit_write_assign_trunc_ext_fu_169_p1 <= std_logic_vector(resize(unsigned(tmp_i_p_bsf32_hw_fu_126_ap_return),8));
agg_result_bucket_index_write_assign_cast_fu_174_p1 <= std_logic_vector(resize(unsigned(agg_result_bucket_index_write_assign_phi_fu_93_p8),8));
-- agg_result_bucket_index_write_assign_phi_fu_93_p8 assign process. --
agg_result_bucket_index_write_assign_phi_fu_93_p8_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it1, tmp_reg_214, tmp_3_reg_225, ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_88pp0_it1)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (tmp_3_reg_225 = ap_const_lv1_0))) then
agg_result_bucket_index_write_assign_phi_fu_93_p8 <= tmp_reg_214;
else
agg_result_bucket_index_write_assign_phi_fu_93_p8 <= ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_88pp0_it1;
end if;
end process;
-- agg_result_bucket_write_assign_phi_fu_58_p8 assign process. --
agg_result_bucket_write_assign_phi_fu_58_p8_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it1, bus_assign_reg_219, tmp_3_reg_225, ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it1)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (tmp_3_reg_225 = ap_const_lv1_0))) then
agg_result_bucket_write_assign_phi_fu_58_p8 <= bus_assign_reg_219;
else
agg_result_bucket_write_assign_phi_fu_58_p8 <= ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it1;
end if;
end process;
-- agg_result_end_write_assign_phi_fu_74_p8 assign process. --
agg_result_end_write_assign_phi_fu_74_p8_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it1, tmp_3_reg_225, ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it1)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (tmp_3_reg_225 = ap_const_lv1_0))) then
agg_result_end_write_assign_phi_fu_74_p8 <= ap_const_lv1_0;
else
agg_result_end_write_assign_phi_fu_74_p8 <= ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it1;
end if;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_ce)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_reg_phiprechg_agg_result_bit_write_assign_reg_106pp0_it0 <= ap_const_lv8_1;
ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_88pp0_it0 <= ap_const_lv2_1;
ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it0 <= ap_const_lv32_1;
ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it0 <= ap_const_lv1_1;
ap_reg_ppiten_pp0_it0 <= ap_start;
ap_return_0 <= agg_result_bit_write_assign_phi_fu_109_p8;
ap_return_1 <= agg_result_bucket_index_write_assign_cast_fu_174_p1;
ap_return_2 <= agg_result_bucket_write_assign_phi_fu_58_p8;
ap_return_3 <= agg_result_end_write_assign_phi_fu_74_p8;
-- ap_sig_pprstidle_pp0 assign process. --
ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0)
begin
if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_start))) then
ap_sig_pprstidle_pp0 <= ap_const_logic_1;
else
ap_sig_pprstidle_pp0 <= ap_const_logic_0;
end if;
end process;
bus_assign_fu_141_p2 <= (tmp_1_fu_135_p2 and r_bucket);
tmp_1_fu_135_p2 <= std_logic_vector(unsigned(r_bucket) + unsigned(ap_const_lv32_FFFFFFFF));
tmp_25_1_fu_153_p2 <= "1" when (tmp_fu_131_p1 = ap_const_lv2_0) else "0";
tmp_27_1_fu_159_p2 <= "1" when (p_read = ap_const_lv32_0) else "0";
tmp_3_fu_147_p2 <= "1" when (bus_assign_fu_141_p2 = ap_const_lv32_0) else "0";
tmp_fu_131_p1 <= r_bucket_index(2 - 1 downto 0);
tmp_i1_p_bsf32_hw_fu_120_bus_r <= p_read;
tmp_i_p_bsf32_hw_fu_126_bus_r <= bus_assign_reg_219;
end behav;
| lgpl-3.0 | 2aef2ab8c97514e6956a46bc04e3ac21 | 0.631713 | 2.52984 | false | false | false | false |
grwlf/vsim | vhdl_ct/pro000006.vhd | 1 | 5,357 | -------------------------------------------------------------------------------
-- Prosoft VHDL tests.
--
-- Copyright (C) 2011 Prosoft.
--
-- Author: Zefirov, Karavaev.
--
-- This is a set of simplest tests for isolated tests of VHDL features.
--
-- Nothing more than standard package should be required.
--
-- Categories: entity, architecture, process, function, procedure, component, generate, after, type.
entity ENT00002 is
port (
x : in bit
; y : in bit
; o : out bit
);
end entity;
architecture ARCH00002 of ENT00002 is
begin
o <= x xor y;
end;
entity ENT00002_Test_Bench is
end entity;
architecture ARCH00002_Test_Bench of ENT00002_Test_Bench is
component ENT00002 is
port (
x : in bit
; y : in bit
; o : out bit
);
end component;
type unsigned is array (natural range <>) of bit;
signal x : unsigned(11 downto 0) := x"AAA";
signal y : unsigned(11 downto 0) := x"000";
signal o : unsigned(11 downto 0);
signal x_nxt, y_nxt : unsigned(11 downto 0);
signal clkx : bit := '0';
signal clky : bit := '0';
function bufX (xi : bit) return bit is
variable r : bit;
begin
r := xi;
return r;
end function;
procedure invBufX (xi : in bit; xo : out bit) is
begin
xo := not xi;
end procedure;
-- simple summator with l'size = r'size without size'controll
function add_unsigned (l,r : unsigned) return unsigned is
variable left : unsigned(l'length-1 downto 0);
variable right : unsigned(r'length-1 downto 0);
variable res : unsigned(l'length-1 downto 0);
variable c : unsigned(l'length downto 0);
begin
left := l;
right := r;
c(0) := '0';
sum_loop: for i in 0 to res'length-1 loop
res(i) := (left(i) xor right(i)) xor c(i);
c(i+1) := ((left(i) xor right(i)) and c(i)) or (left(i) and right(i));
end loop;
return res;
end function add_unsigned;
type integer_vector_dem2 is array (integer range <>, integer range <>) of integer;
type integer_vector_dem1 is array (integer range <>) of integer;
signal iv2 : integer_vector_dem2(3 downto 0, 0 to 3) := (others => (others => 0));
signal iv1 : integer_vector_dem1(3 downto 0) := (others => 0);
begin
x_nxt <= add_unsigned(x, x"001");
y_nxt <= add_unsigned(y, x"001");
clkx <= not clkx after 1 us;
clky <= not clky after 1.2 us;
process (clkx)
begin
if clkx'event and clkx = '1' then
x <= x_nxt;
end if;
end process;
process (clky)
begin
if clky'event and clky = '1' then
y <= y_nxt;
end if;
end process;
o_3_0_gen: for i in 3 downto 0 generate
tst_gen: for j in 0 to i generate
signal s : integer := 0;
begin
process (clkx)
begin
if clkx'event and clkx ='1' then
iv2(i,j) <= iv2(i,j) + j;
s <= s + j;
-- iv1(i) <= iv1(i) + j;
end if;
end process;
end generate;
o_1_0_gen: if i <= 1 generate
signal xi : unsigned(1 downto 0);
begin
process (x(i))
variable v_xi : unsigned(1 downto 0);
begin
invBufX(x(i), v_xi(i));
xi(i) <= v_xi(i) after 0.1 us;
end process;
ENT00002_inst : ENT00002
port map (
x => xi(i)
, y => y(i)
, o => o(i)
);
end generate;
o_3_2_gen: if i >= 2 generate
signal xi : unsigned(3 downto 2);
begin
process (x(i))
begin
xi(i) <= bufX(x(i)) after 0.2 us;
end process;
ENT00002_inst : ENT00002
port map (
x => xi(i)
, y => y(i)
, o => o(i)
);
end generate;
end generate;
o_7_6_gen: for i in 7 downto 6 generate
procedure invProc (p : in bit; q : out bit) is
begin
q := not p;
end procedure;
signal y_inv : bit;
begin
process(y(i))
variable v_y_inv : bit;
begin
invProc(y(i),v_y_inv);
y_inv <= v_y_inv;
end process;
ENT00002_inst : ENT00002
port map (
x => x(i)
, y => y_inv
, o => o(i)
);
end generate;
o_5_4_gen: for i in 5 downto 4 generate
function invFunc (i : bit) return bit is
variable r : bit;
begin
r := not i;
return r;
end function;
signal y_inv : bit;
begin
process(y(i))
begin
y_inv <= invFunc(y(i));
end process;
ENT00002_inst : ENT00002
port map (
x => x(i)
, y => y_inv
, o => o(i)
);
end generate;
o_11_8_gen: for i in 11 downto 8 generate
procedure invProc (p : in bit; q : out bit) is
begin
q := not p;
end procedure;
signal y_inv : unsigned(11 downto 8);
begin
o_11_10_gen: if i >= 10 generate
function invFunc (i : bit) return bit is
variable r : bit;
begin
r := not i;
return r;
end function;
begin
process(y(i))
begin
y_inv(i) <= invFunc(y(i));
end process;
ENT00002_inst : ENT00002
port map (
x => x(i)
, y => y_inv(i)
, o => o(i)
);
end generate;
o_9_8_gen: if i <= 9 generate
signal xi : unsigned(9 downto 8);
begin
process (x(i))
begin
xi(i) <= bufX(x(i)) after 0.2 us;
end process;
process(y(i))
variable v_y_inv : bit;
begin
invProc(y(i),v_y_inv);
y_inv(i) <= v_y_inv;
end process;
ENT00002_inst : ENT00002
port map (
x => xi(i)
, y => y_inv(i)
, o => o(i)
);
end generate;
end generate;
end ARCH00002_Test_Bench;
| gpl-3.0 | c47b7434990fab237e88adc080759074 | 0.556282 | 2.782857 | false | false | false | false |
TWW12/lzw | final_project/lzw_compression/lzw_compression.srcs/sources_1/bd/design_1/ip/design_1_axi_compression_0_0/sim/design_1_axi_compression_0_0.vhd | 1 | 8,124 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:axi_compression:1.0
-- IP Revision: 29
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_axi_compression_0_0 IS
PORT (
s00_axi_awaddr : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END design_1_axi_compression_0_0;
ARCHITECTURE design_1_axi_compression_0_0_arch OF design_1_axi_compression_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_compression_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_compression_v1_0 IS
GENERIC (
C_S00_AXI_DATA_WIDTH : INTEGER; -- Width of S_AXI data bus
C_S00_AXI_ADDR_WIDTH : INTEGER -- Width of S_AXI address bus
);
PORT (
s00_axi_awaddr : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END COMPONENT axi_compression_v1_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S00_AXI_RST RST";
BEGIN
U0 : axi_compression_v1_0
GENERIC MAP (
C_S00_AXI_DATA_WIDTH => 32,
C_S00_AXI_ADDR_WIDTH => 6
)
PORT MAP (
s00_axi_awaddr => s00_axi_awaddr,
s00_axi_awprot => s00_axi_awprot,
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_awready => s00_axi_awready,
s00_axi_wdata => s00_axi_wdata,
s00_axi_wstrb => s00_axi_wstrb,
s00_axi_wvalid => s00_axi_wvalid,
s00_axi_wready => s00_axi_wready,
s00_axi_bresp => s00_axi_bresp,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_araddr => s00_axi_araddr,
s00_axi_arprot => s00_axi_arprot,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_arready => s00_axi_arready,
s00_axi_rdata => s00_axi_rdata,
s00_axi_rresp => s00_axi_rresp,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_rready => s00_axi_rready,
s00_axi_aclk => s00_axi_aclk,
s00_axi_aresetn => s00_axi_aresetn
);
END design_1_axi_compression_0_0_arch;
| unlicense | 43f99015f7a89a0633b9d583bf3c8faf | 0.708887 | 3.24182 | false | false | false | false |
TWW12/lzw | final_project_sim/lzw/lzw.cache/ip/42f801f2e04cbe7d/bram_1024_0_sim_netlist.vhdl | 1 | 52,972 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Apr 18 23:18:54 2017
-- Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ bram_1024_0_sim_netlist.vhdl
-- Design : bram_1024_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_21\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_22\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_23\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_29\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_30\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_31\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_47\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_85\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_86\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000001D0000001900000015000000110000000D000000090000000500000001",
INIT_01 => X"0000011D0000011900000115000001110000010D000001090000010500000101",
INIT_02 => X"0000021D0000021900000215000002110000020D000002090000020500000201",
INIT_03 => X"0000031D0000031900000315000003110000030D000003090000030500000301",
INIT_04 => X"0000041D0000041900000415000004110000040D000004090000040500000401",
INIT_05 => X"0000051D0000051900000515000005110000050D000005090000050500000501",
INIT_06 => X"0000061D0000061900000615000006110000060D000006090000060500000601",
INIT_07 => X"0000071D0000071900000715000007110000070D000007090000070500000701",
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INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4 downto 0) => B"11111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 29) => B"000",
DIADI(28 downto 24) => dina(19 downto 15),
DIADI(23 downto 21) => B"000",
DIADI(20 downto 16) => dina(14 downto 10),
DIADI(15 downto 13) => B"000",
DIADI(12 downto 8) => dina(9 downto 5),
DIADI(7 downto 5) => B"000",
DIADI(4 downto 0) => dina(4 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_21\,
DOADO(30) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_22\,
DOADO(29) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_23\,
DOADO(28 downto 24) => douta(19 downto 15),
DOADO(23) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_29\,
DOADO(22) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_30\,
DOADO(21) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_31\,
DOADO(20 downto 16) => douta(14 downto 10),
DOADO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37\,
DOADO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38\,
DOADO(13) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39\,
DOADO(12 downto 8) => douta(9 downto 5),
DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\,
DOADO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46\,
DOADO(5) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_47\,
DOADO(4 downto 0) => douta(4 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_85\,
DOPADOP(2) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_86\,
DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87\,
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
begin
\valid.cstr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 9 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 19 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 19 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 9 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 10;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 10;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "1";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 2.74095 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "bram_1024_0.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "bram_1024_0.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1024;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1024;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1024;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1024;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "zynq";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "yes";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(19) <= \<const0>\;
doutb(18) <= \<const0>\;
doutb(17) <= \<const0>\;
doutb(16) <= \<const0>\;
doutb(15) <= \<const0>\;
doutb(14) <= \<const0>\;
doutb(13) <= \<const0>\;
doutb(12) <= \<const0>\;
doutb(11) <= \<const0>\;
doutb(10) <= \<const0>\;
doutb(9) <= \<const0>\;
doutb(8) <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
clka : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
douta : out STD_LOGIC_VECTOR ( 19 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "bram_1024_0,blk_mem_gen_v8_3_5,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 10;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 10;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "1";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 2.74095 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "bram_1024_0.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "bram_1024_0.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 1024;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 1024;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 20;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 20;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 1024;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 1024;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 20;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 20;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5
port map (
addra(9 downto 0) => addra(9 downto 0),
addrb(9 downto 0) => B"0000000000",
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(19 downto 0) => dina(19 downto 0),
dinb(19 downto 0) => B"00000000000000000000",
douta(19 downto 0) => douta(19 downto 0),
doutb(19 downto 0) => NLW_U0_doutb_UNCONNECTED(19 downto 0),
eccpipece => '0',
ena => ena,
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(9 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(9 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(9 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(9 downto 0),
s_axi_rdata(19 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(19 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(19 downto 0) => B"00000000000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
| unlicense | 93863a58b61dfd8d0c758f9b55fc1b0c | 0.70643 | 3.445557 | false | false | false | false |
jairov4/accel-oil | solution_spartan6/impl/vhdl/nfa_get_initials.vhd | 4 | 15,083 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_get_initials is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_initials_buckets_req_din : OUT STD_LOGIC;
nfa_initials_buckets_req_full_n : IN STD_LOGIC;
nfa_initials_buckets_req_write : OUT STD_LOGIC;
nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_initials_buckets_rsp_read : OUT STD_LOGIC;
nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
ap_return_0 : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of nfa_get_initials is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_ST_pp0_stg1_fsm_1 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "1";
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0';
signal nfa_initials_buckets_read_reg_63 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppiten_pp0_it0_preg : STD_LOGIC := '0';
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_pprstidle_pp0 : STD_LOGIC;
signal ap_sig_bdd_136 : BOOLEAN;
signal ap_sig_bdd_67 : BOOLEAN;
signal ap_sig_bdd_135 : BOOLEAN;
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it0_preg assign process. --
ap_reg_ppiten_pp0_it0_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it0_preg <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))))) then
ap_reg_ppiten_pp0_it0_preg <= ap_start;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it2 assign process. --
ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it3 assign process. --
ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))) then
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
elsif (((ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then
nfa_initials_buckets_read_reg_63 <= nfa_initials_buckets_datain;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it1 , ap_reg_ppiten_pp0_it2 , ap_reg_ppiten_pp0_it3 , nfa_initials_buckets_rsp_empty_n , ap_ce , ap_sig_pprstidle_pp0)
begin
case ap_CS_fsm is
when ap_ST_pp0_stg0_fsm_0 =>
if ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))) and not((ap_const_logic_1 = ap_sig_pprstidle_pp0)) and not(((ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_start))))) then
ap_NS_fsm <= ap_ST_pp0_stg1_fsm_1;
elsif ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_sig_pprstidle_pp0))) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
end if;
when ap_ST_pp0_stg1_fsm_1 =>
if (not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce))))) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_NS_fsm <= ap_ST_pp0_stg1_fsm_1;
end if;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it3, nfa_initials_buckets_rsp_empty_n, ap_ce)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_1 = ap_ce) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0))))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, nfa_initials_buckets_rsp_empty_n, ap_ce)
begin
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_reg_ppiten_pp0_it0 assign process. --
ap_reg_ppiten_pp0_it0_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0_preg)
begin
if ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm)) then
ap_reg_ppiten_pp0_it0 <= ap_start;
else
ap_reg_ppiten_pp0_it0 <= ap_reg_ppiten_pp0_it0_preg;
end if;
end process;
ap_return_0 <= nfa_initials_buckets_read_reg_63;
ap_return_1 <= nfa_initials_buckets_datain;
-- ap_sig_bdd_135 assign process. --
ap_sig_bdd_135_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_ce)
begin
ap_sig_bdd_135 <= ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce));
end process;
-- ap_sig_bdd_136 assign process. --
ap_sig_bdd_136_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it3, nfa_initials_buckets_rsp_empty_n)
begin
ap_sig_bdd_136 <= ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))));
end process;
-- ap_sig_bdd_67 assign process. --
ap_sig_bdd_67_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it2, nfa_initials_buckets_rsp_empty_n)
begin
ap_sig_bdd_67 <= ((ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0))));
end process;
-- ap_sig_pprstidle_pp0 assign process. --
ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2)
begin
if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_start))) then
ap_sig_pprstidle_pp0 <= ap_const_logic_1;
else
ap_sig_pprstidle_pp0 <= ap_const_logic_0;
end if;
end process;
-- nfa_initials_buckets_address assign process. --
nfa_initials_buckets_address_assign_proc : process(ap_sig_bdd_136, ap_sig_bdd_67, ap_sig_bdd_135)
begin
if (ap_sig_bdd_135) then
if (ap_sig_bdd_67) then
nfa_initials_buckets_address <= ap_const_lv64_1(32 - 1 downto 0);
elsif (ap_sig_bdd_136) then
nfa_initials_buckets_address <= ap_const_lv32_0;
else
nfa_initials_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
nfa_initials_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
nfa_initials_buckets_dataout <= ap_const_lv32_0;
nfa_initials_buckets_req_din <= ap_const_logic_0;
-- nfa_initials_buckets_req_write assign process. --
nfa_initials_buckets_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, nfa_initials_buckets_rsp_empty_n, ap_ce)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0))))))) then
nfa_initials_buckets_req_write <= ap_const_logic_1;
else
nfa_initials_buckets_req_write <= ap_const_logic_0;
end if;
end process;
-- nfa_initials_buckets_rsp_read assign process. --
nfa_initials_buckets_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, nfa_initials_buckets_rsp_empty_n, ap_ce)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_1 = ap_ce) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0))))))) then
nfa_initials_buckets_rsp_read <= ap_const_logic_1;
else
nfa_initials_buckets_rsp_read <= ap_const_logic_0;
end if;
end process;
nfa_initials_buckets_size <= ap_const_lv32_1;
end behav;
| lgpl-3.0 | b3ca85edc5b7b6062fb67a1fa7faeb14 | 0.598555 | 2.713258 | false | false | false | false |
grwlf/vsim | vhdl/IEEE/math_complex.vhdl | 1 | 17,881 | ---------------------------------------------------------------
--
-- This source file may be used and distributed without restriction.
-- No declarations or definitions shall be included in this package.
-- This package cannot be sold or distributed for profit.
--
-- ****************************************************************
-- * *
-- * W A R N I N G *
-- * *
-- * This DRAFT version IS NOT endorsed or approved by IEEE *
-- * *
-- ****************************************************************
--
-- Title: PACKAGE MATH_COMPLEX
--
-- Purpose: VHDL declarations for mathematical package MATH_COMPLEX
-- which contains common complex constants and basic complex
-- functions and operations.
--
-- Author: IEEE VHDL Math Package Study Group
--
-- Notes:
-- The package body uses package IEEE.MATH_REAL
--
-- The package body shall be considered the formal definition of
-- the semantics of this package. Tool developers may choose to implement
-- the package body in the most efficient manner available to them.
--
-- History:
-- Version 0.1 (Strawman) Jose A. Torres 6/22/92
-- Version 0.2 Jose A. Torres 1/15/93
-- Version 0.3 Jose A. Torres 4/13/93
-- Version 0.4 Jose A. Torres 4/19/93
-- Version 0.5 Jose A. Torres 4/20/93
-- Version 0.6 Jose A. Torres 4/23/93 Added unary minus
-- and CONJ for polar
-- Version 0.7 Jose A. Torres 5/28/93 Rev up for compatibility
-- with package body.
-------------------------------------------------------------
Library IEEE;
Package MATH_COMPLEX is
type COMPLEX is record RE, IM: real; end record;
type COMPLEX_VECTOR is array (integer range <>) of COMPLEX;
type COMPLEX_POLAR is record MAG: real; ARG: real; end record;
constant CBASE_1: complex := COMPLEX'(1.0, 0.0);
constant CBASE_j: complex := COMPLEX'(0.0, 1.0);
constant CZERO: complex := COMPLEX'(0.0, 0.0);
function CABS(Z: in complex ) return real;
-- returns absolute value (magnitude) of Z
function CARG(Z: in complex ) return real;
-- returns argument (angle) in radians of a complex number
function CMPLX(X: in real; Y: in real:= 0.0 ) return complex;
-- returns complex number X + iY
function "-" (Z: in complex ) return complex;
-- unary minus
function "-" (Z: in complex_polar ) return complex_polar;
-- unary minus
function CONJ (Z: in complex) return complex;
-- returns complex conjugate
function CONJ (Z: in complex_polar) return complex_polar;
-- returns complex conjugate
function CSQRT(Z: in complex ) return complex_vector;
-- returns square root of Z; 2 values
function CEXP(Z: in complex ) return complex;
-- returns e**Z
function COMPLEX_TO_POLAR(Z: in complex ) return complex_polar;
-- converts complex to complex_polar
function POLAR_TO_COMPLEX(Z: in complex_polar ) return complex;
-- converts complex_polar to complex
-- arithmetic operators
function "+" ( L: in complex; R: in complex ) return complex;
function "+" ( L: in complex_polar; R: in complex_polar) return complex;
function "+" ( L: in complex_polar; R: in complex ) return complex;
function "+" ( L: in complex; R: in complex_polar) return complex;
function "+" ( L: in real; R: in complex ) return complex;
function "+" ( L: in complex; R: in real ) return complex;
function "+" ( L: in real; R: in complex_polar) return complex;
function "+" ( L: in complex_polar; R: in real) return complex;
function "-" ( L: in complex; R: in complex ) return complex;
function "-" ( L: in complex_polar; R: in complex_polar) return complex;
function "-" ( L: in complex_polar; R: in complex ) return complex;
function "-" ( L: in complex; R: in complex_polar) return complex;
function "-" ( L: in real; R: in complex ) return complex;
function "-" ( L: in complex; R: in real ) return complex;
function "-" ( L: in real; R: in complex_polar) return complex;
function "-" ( L: in complex_polar; R: in real) return complex;
function "*" ( L: in complex; R: in complex ) return complex;
function "*" ( L: in complex_polar; R: in complex_polar) return complex;
function "*" ( L: in complex_polar; R: in complex ) return complex;
function "*" ( L: in complex; R: in complex_polar) return complex;
function "*" ( L: in real; R: in complex ) return complex;
function "*" ( L: in complex; R: in real ) return complex;
function "*" ( L: in real; R: in complex_polar) return complex;
function "*" ( L: in complex_polar; R: in real) return complex;
function "/" ( L: in complex; R: in complex ) return complex;
function "/" ( L: in complex_polar; R: in complex_polar) return complex;
function "/" ( L: in complex_polar; R: in complex ) return complex;
function "/" ( L: in complex; R: in complex_polar) return complex;
function "/" ( L: in real; R: in complex ) return complex;
function "/" ( L: in complex; R: in real ) return complex;
function "/" ( L: in real; R: in complex_polar) return complex;
function "/" ( L: in complex_polar; R: in real) return complex;
end MATH_COMPLEX;
---------------------------------------------------------------
--
-- This source file may be used and distributed without restriction.
-- No declarations or definitions shall be included in this package.
-- This package cannot be sold or distributed for profit.
--
-- ****************************************************************
-- * *
-- * W A R N I N G *
-- * *
-- * This DRAFT version IS NOT endorsed or approved by IEEE *
-- * *
-- ****************************************************************
--
-- Title: PACKAGE BODY MATH_COMPLEX
--
-- Purpose: VHDL declarations for mathematical package MATH_COMPLEX
-- which contains common complex constants and basic complex
-- functions and operations.
--
-- Author: IEEE VHDL Math Package Study Group
--
-- Notes:
-- The package body uses package IEEE.MATH_REAL
--
-- The package body shall be considered the formal definition of
-- the semantics of this package. Tool developers may choose to implement
-- the package body in the most efficient manner available to them.
--
-- Source code for this package body comes from the following
-- following sources:
-- IEEE VHDL Math Package Study Group participants,
-- U. of Mississippi, Mentor Graphics, Synopsys,
-- Viewlogic/Vantage, Communications of the ACM (June 1988, Vol
-- 31, Number 6, pp. 747, Pierre L'Ecuyer, Efficient and Portable
-- Random Number Generators, Handbook of Mathematical Functions
-- by Milton Abramowitz and Irene A. Stegun (Dover).
--
-- History:
-- Version 0.1 Jose A. Torres 4/23/93 First draft
-- Version 0.2 Jose A. Torres 5/28/93 Fixed potentially illegal code
--
-------------------------------------------------------------
Library IEEE;
Use IEEE.MATH_REAL.all; -- real trascendental operations
Package body MATH_COMPLEX is
function CABS(Z: in complex ) return real is
-- returns absolute value (magnitude) of Z
variable ztemp : complex_polar;
begin
ztemp := COMPLEX_TO_POLAR(Z);
return ztemp.mag;
end CABS;
function CARG(Z: in complex ) return real is
-- returns argument (angle) in radians of a complex number
variable ztemp : complex_polar;
begin
ztemp := COMPLEX_TO_POLAR(Z);
return ztemp.arg;
end CARG;
function CMPLX(X: in real; Y: in real := 0.0 ) return complex is
-- returns complex number X + iY
begin
return COMPLEX'(X, Y);
end CMPLX;
function "-" (Z: in complex ) return complex is
-- unary minus; returns -x -jy for z= x + jy
begin
return COMPLEX'(-z.Re, -z.Im);
end "-";
function "-" (Z: in complex_polar ) return complex_polar is
-- unary minus; returns (z.mag, z.arg + MATH_PI)
begin
return COMPLEX_POLAR'(z.mag, z.arg + MATH_PI);
end "-";
function CONJ (Z: in complex) return complex is
-- returns complex conjugate (x-jy for z = x+ jy)
begin
return COMPLEX'(z.Re, -z.Im);
end CONJ;
function CONJ (Z: in complex_polar) return complex_polar is
-- returns complex conjugate (z.mag, -z.arg)
begin
return COMPLEX_POLAR'(z.mag, -z.arg);
end CONJ;
function CSQRT(Z: in complex ) return complex_vector is
-- returns square root of Z; 2 values
variable ztemp : complex_polar;
variable zout : complex_vector (0 to 1);
variable temp : real;
begin
ztemp := COMPLEX_TO_POLAR(Z);
temp := SQRT(ztemp.mag);
zout(0).re := temp*COS(ztemp.arg/2.0);
zout(0).im := temp*SIN(ztemp.arg/2.0);
zout(1).re := temp*COS(ztemp.arg/2.0 + MATH_PI);
zout(1).im := temp*SIN(ztemp.arg/2.0 + MATH_PI);
return zout;
end CSQRT;
function CEXP(Z: in complex ) return complex is
-- returns e**Z
begin
return COMPLEX'(EXP(Z.re)*COS(Z.im), EXP(Z.re)*SIN(Z.im));
end CEXP;
function COMPLEX_TO_POLAR(Z: in complex ) return complex_polar is
-- converts complex to complex_polar
begin
return COMPLEX_POLAR'(sqrt(z.re**2 + z.im**2),atan2(z.re,z.im));
end COMPLEX_TO_POLAR;
function POLAR_TO_COMPLEX(Z: in complex_polar ) return complex is
-- converts complex_polar to complex
begin
return COMPLEX'( z.mag*cos(z.arg), z.mag*sin(z.arg) );
end POLAR_TO_COMPLEX;
--
-- arithmetic operators
--
function "+" ( L: in complex; R: in complex ) return complex is
begin
return COMPLEX'(L.Re + R.Re, L.Im + R.Im);
end "+";
function "+" (L: in complex_polar; R: in complex_polar) return complex is
variable zL, zR : complex;
begin
zL := POLAR_TO_COMPLEX( L );
zR := POLAR_TO_COMPLEX( R );
return COMPLEX'(zL.Re + zR.Re, zL.Im + zR.Im);
end "+";
function "+" ( L: in complex_polar; R: in complex ) return complex is
variable zL : complex;
begin
zL := POLAR_TO_COMPLEX( L );
return COMPLEX'(zL.Re + R.Re, zL.Im + R.Im);
end "+";
function "+" ( L: in complex; R: in complex_polar) return complex is
variable zR : complex;
begin
zR := POLAR_TO_COMPLEX( R );
return COMPLEX'(L.Re + zR.Re, L.Im + zR.Im);
end "+";
function "+" ( L: in real; R: in complex ) return complex is
begin
return COMPLEX'(L + R.Re, R.Im);
end "+";
function "+" ( L: in complex; R: in real ) return complex is
begin
return COMPLEX'(L.Re + R, L.Im);
end "+";
function "+" ( L: in real; R: in complex_polar) return complex is
variable zR : complex;
begin
zR := POLAR_TO_COMPLEX( R );
return COMPLEX'(L + zR.Re, zR.Im);
end "+";
function "+" ( L: in complex_polar; R: in real) return complex is
variable zL : complex;
begin
zL := POLAR_TO_COMPLEX( L );
return COMPLEX'(zL.Re + R, zL.Im);
end "+";
function "-" ( L: in complex; R: in complex ) return complex is
begin
return COMPLEX'(L.Re - R.Re, L.Im - R.Im);
end "-";
function "-" ( L: in complex_polar; R: in complex_polar) return complex is
variable zL, zR : complex;
begin
zL := POLAR_TO_COMPLEX( L );
zR := POLAR_TO_COMPLEX( R );
return COMPLEX'(zL.Re - zR.Re, zL.Im - zR.Im);
end "-";
function "-" ( L: in complex_polar; R: in complex ) return complex is
variable zL : complex;
begin
zL := POLAR_TO_COMPLEX( L );
return COMPLEX'(zL.Re - R.Re, zL.Im - R.Im);
end "-";
function "-" ( L: in complex; R: in complex_polar) return complex is
variable zR : complex;
begin
zR := POLAR_TO_COMPLEX( R );
return COMPLEX'(L.Re - zR.Re, L.Im - zR.Im);
end "-";
function "-" ( L: in real; R: in complex ) return complex is
begin
return COMPLEX'(L - R.Re, -1.0 * R.Im);
end "-";
function "-" ( L: in complex; R: in real ) return complex is
begin
return COMPLEX'(L.Re - R, L.Im);
end "-";
function "-" ( L: in real; R: in complex_polar) return complex is
variable zR : complex;
begin
zR := POLAR_TO_COMPLEX( R );
return COMPLEX'(L - zR.Re, -1.0*zR.Im);
end "-";
function "-" ( L: in complex_polar; R: in real) return complex is
variable zL : complex;
begin
zL := POLAR_TO_COMPLEX( L );
return COMPLEX'(zL.Re - R, zL.Im);
end "-";
function "*" ( L: in complex; R: in complex ) return complex is
begin
return COMPLEX'(L.Re * R.Re - L.Im * R.Im, L.Re * R.Im + L.Im * R.Re);
end "*";
function "*" ( L: in complex_polar; R: in complex_polar) return complex is
variable zout : complex_polar;
begin
zout.mag := L.mag * R.mag;
zout.arg := L.arg + R.arg;
return POLAR_TO_COMPLEX(zout);
end "*";
function "*" ( L: in complex_polar; R: in complex ) return complex is
variable zL : complex;
begin
zL := POLAR_TO_COMPLEX( L );
return COMPLEX'(zL.Re*R.Re - zL.Im * R.Im, zL.Re * R.Im + zL.Im*R.Re);
end "*";
function "*" ( L: in complex; R: in complex_polar) return complex is
variable zR : complex;
begin
zR := POLAR_TO_COMPLEX( R );
return COMPLEX'(L.Re*zR.Re - L.Im * zR.Im, L.Re * zR.Im + L.Im*zR.Re);
end "*";
function "*" ( L: in real; R: in complex ) return complex is
begin
return COMPLEX'(L * R.Re, L * R.Im);
end "*";
function "*" ( L: in complex; R: in real ) return complex is
begin
return COMPLEX'(L.Re * R, L.Im * R);
end "*";
function "*" ( L: in real; R: in complex_polar) return complex is
variable zR : complex;
begin
zR := POLAR_TO_COMPLEX( R );
return COMPLEX'(L * zR.Re, L * zR.Im);
end "*";
function "*" ( L: in complex_polar; R: in real) return complex is
variable zL : complex;
begin
zL := POLAR_TO_COMPLEX( L );
return COMPLEX'(zL.Re * R, zL.Im * R);
end "*";
function "/" ( L: in complex; R: in complex ) return complex is
variable magrsq : REAL := R.Re ** 2 + R.Im ** 2;
begin
if (magrsq = 0.0) then
assert FALSE report "Attempt to divide by (0,0)"
severity ERROR;
return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
else
return COMPLEX'( (L.Re * R.Re + L.Im * R.Im) / magrsq,
(L.Im * R.Re - L.Re * R.Im) / magrsq);
end if;
end "/";
function "/" ( L: in complex_polar; R: in complex_polar) return complex is
variable zout : complex_polar;
begin
if (R.mag = 0.0) then
assert FALSE report "Attempt to divide by (0,0)"
severity ERROR;
return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
else
zout.mag := L.mag/R.mag;
zout.arg := L.arg - R.arg;
return POLAR_TO_COMPLEX(zout);
end if;
end "/";
function "/" ( L: in complex_polar; R: in complex ) return complex is
variable zL : complex;
variable temp : REAL := R.Re ** 2 + R.Im ** 2;
begin
if (temp = 0.0) then
assert FALSE report "Attempt to divide by (0.0,0.0)"
severity ERROR;
return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
else
zL := POLAR_TO_COMPLEX( L );
return COMPLEX'( (zL.Re * R.Re + zL.Im * R.Im) / temp,
(zL.Im * R.Re - zL.Re * R.Im) / temp);
end if;
end "/";
function "/" ( L: in complex; R: in complex_polar) return complex is
variable zR : complex := POLAR_TO_COMPLEX( R );
variable temp : REAL := zR.Re ** 2 + zR.Im ** 2;
begin
if (R.mag = 0.0) or (temp = 0.0) then
assert FALSE report "Attempt to divide by (0.0,0.0)"
severity ERROR;
return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
else
return COMPLEX'( (L.Re * zR.Re + L.Im * zR.Im) / temp,
(L.Im * zR.Re - L.Re * zR.Im) / temp);
end if;
end "/";
function "/" ( L: in real; R: in complex ) return complex is
variable temp : REAL := R.Re ** 2 + R.Im ** 2;
begin
if (temp = 0.0) then
assert FALSE report "Attempt to divide by (0.0,0.0)"
severity ERROR;
return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
else
temp := L / temp;
return COMPLEX'( temp * R.Re, -temp * R.Im );
end if;
end "/";
function "/" ( L: in complex; R: in real ) return complex is
begin
if (R = 0.0) then
assert FALSE report "Attempt to divide by (0.0,0.0)"
severity ERROR;
return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
else
return COMPLEX'(L.Re / R, L.Im / R);
end if;
end "/";
function "/" ( L: in real; R: in complex_polar) return complex is
variable zR : complex := POLAR_TO_COMPLEX( R );
variable temp : REAL := zR.Re ** 2 + zR.Im ** 2;
begin
if (R.mag = 0.0) or (temp = 0.0) then
assert FALSE report "Attempt to divide by (0.0,0.0)"
severity ERROR;
return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
else
temp := L / temp;
return COMPLEX'( temp * zR.Re, -temp * zR.Im );
end if;
end "/";
function "/" ( L: in complex_polar; R: in real) return complex is
variable zL : complex := POLAR_TO_COMPLEX( L );
begin
if (R = 0.0) then
assert FALSE report "Attempt to divide by (0.0,0.0)"
severity ERROR;
return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
else
return COMPLEX'(zL.Re / R, zL.Im / R);
end if;
end "/";
end MATH_COMPLEX;
| gpl-3.0 | 494f3ace0bc026c34ee079f3429e9311 | 0.568592 | 3.475413 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00189.vhd | 1 | 17,623 | -------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00189
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00189
-- PKG00189/BODY
-- ENT00189(ARCH00189)
-- ENT00189_Test_Bench(ARCH00189_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
package PKG00189 is
type r_st_rec1 is record
f1 : integer ;
f2 : st_rec1 ;
end record ;
function c_r_st_rec1_1 return r_st_rec1 ;
-- (c_integer_1, c_st_rec1_1) ;
function c_r_st_rec1_2 return r_st_rec1 ;
-- (c_integer_2, c_st_rec1_2) ;
--
type r_st_rec2 is record
f1 : integer ;
f2 : st_rec2 ;
end record ;
function c_r_st_rec2_1 return r_st_rec2 ;
-- (c_integer_1, c_st_rec2_1) ;
function c_r_st_rec2_2 return r_st_rec2 ;
-- (c_integer_2, c_st_rec2_2) ;
--
type r_st_rec3 is record
f1 : integer ;
f2 : st_rec3 ;
end record ;
function c_r_st_rec3_1 return r_st_rec3 ;
-- (c_integer_1, c_st_rec3_1) ;
function c_r_st_rec3_2 return r_st_rec3 ;
-- (c_integer_2, c_st_rec3_2) ;
--
--
end PKG00189 ;
--
package body PKG00189 is
function c_r_st_rec1_1 return r_st_rec1
is begin
return (c_integer_1, c_st_rec1_1) ;
end c_r_st_rec1_1 ;
--
function c_r_st_rec1_2 return r_st_rec1
is begin
return (c_integer_2, c_st_rec1_2) ;
end c_r_st_rec1_2 ;
--
--
function c_r_st_rec2_1 return r_st_rec2
is begin
return (c_integer_1, c_st_rec2_1) ;
end c_r_st_rec2_1 ;
--
function c_r_st_rec2_2 return r_st_rec2
is begin
return (c_integer_2, c_st_rec2_2) ;
end c_r_st_rec2_2 ;
--
--
function c_r_st_rec3_1 return r_st_rec3
is begin
return (c_integer_1, c_st_rec3_1) ;
end c_r_st_rec3_1 ;
--
function c_r_st_rec3_2 return r_st_rec3
is begin
return (c_integer_2, c_st_rec3_2) ;
end c_r_st_rec3_2 ;
--
--
--
end PKG00189 ;
--
use WORK.STANDARD_TYPES.all ;
use WORK.PKG00189.all ;
entity ENT00189 is
port (
s_r_st_rec1 : inout r_st_rec1
; s_r_st_rec2 : inout r_st_rec2
; s_r_st_rec3 : inout r_st_rec3
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_r_st_rec1 : chk_sig_type := -1 ;
signal chk_r_st_rec2 : chk_sig_type := -1 ;
signal chk_r_st_rec3 : chk_sig_type := -1 ;
--
end ENT00189 ;
--
architecture ARCH00189 of ENT00189 is
begin
P1 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_r_st_rec1.f2.f2 <=
c_r_st_rec1_2.f2.f2 after 10 ns,
c_r_st_rec1_1.f2.f2 after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec1.f2.f2 =
c_r_st_rec1_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec1.f2.f2 =
c_r_st_rec1_1.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00189.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec1.f2.f2 <=
c_r_st_rec1_2.f2.f2 after 10 ns ,
c_r_st_rec1_1.f2.f2 after 20 ns ,
c_r_st_rec1_2.f2.f2 after 30 ns ,
c_r_st_rec1_1.f2.f2 after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec1.f2.f2 =
c_r_st_rec1_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec1.f2.f2 <=
c_r_st_rec1_1.f2.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec1.f2.f2 =
c_r_st_rec1_1.f2.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00189" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec1.f2.f2 <= transport
c_r_st_rec1_1.f2.f2 after 100 ns ;
--
when 5
=> correct :=
s_r_st_rec1.f2.f2 =
c_r_st_rec1_1.f2.f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00189" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec1.f2.f2 <=
c_r_st_rec1_2.f2.f2 after 10 ns ,
c_r_st_rec1_1.f2.f2 after 20 ns ,
c_r_st_rec1_2.f2.f2 after 30 ns ,
c_r_st_rec1_1.f2.f2 after 40 ns ;
--
when 6
=> correct :=
s_r_st_rec1.f2.f2 =
c_r_st_rec1_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00189" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_rec1.f2.f2 <=
c_r_st_rec1_1.f2.f2 after 40 ns ;
--
when 7
=> correct :=
s_r_st_rec1.f2.f2 =
c_r_st_rec1_1.f2.f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_rec1.f2.f2 =
c_r_st_rec1_1.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00189" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00189" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_r_st_rec1'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_r_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_r_st_rec1 = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
P2 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_r_st_rec2.f2.f2 <=
c_r_st_rec2_2.f2.f2 after 10 ns,
c_r_st_rec2_1.f2.f2 after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec2.f2.f2 =
c_r_st_rec2_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec2.f2.f2 =
c_r_st_rec2_1.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00189.P2" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec2.f2.f2 <=
c_r_st_rec2_2.f2.f2 after 10 ns ,
c_r_st_rec2_1.f2.f2 after 20 ns ,
c_r_st_rec2_2.f2.f2 after 30 ns ,
c_r_st_rec2_1.f2.f2 after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec2.f2.f2 =
c_r_st_rec2_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec2.f2.f2 <=
c_r_st_rec2_1.f2.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec2.f2.f2 =
c_r_st_rec2_1.f2.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00189" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec2.f2.f2 <= transport
c_r_st_rec2_1.f2.f2 after 100 ns ;
--
when 5
=> correct :=
s_r_st_rec2.f2.f2 =
c_r_st_rec2_1.f2.f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00189" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec2.f2.f2 <=
c_r_st_rec2_2.f2.f2 after 10 ns ,
c_r_st_rec2_1.f2.f2 after 20 ns ,
c_r_st_rec2_2.f2.f2 after 30 ns ,
c_r_st_rec2_1.f2.f2 after 40 ns ;
--
when 6
=> correct :=
s_r_st_rec2.f2.f2 =
c_r_st_rec2_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00189" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_rec2.f2.f2 <=
c_r_st_rec2_1.f2.f2 after 40 ns ;
--
when 7
=> correct :=
s_r_st_rec2.f2.f2 =
c_r_st_rec2_1.f2.f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_rec2.f2.f2 =
c_r_st_rec2_1.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00189" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00189" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_r_st_rec2'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P2 ;
--
PGEN_CHKP_2 :
process ( chk_r_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions entirely completed",
chk_r_st_rec2 = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
P3 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_r_st_rec3.f2.f2 <=
c_r_st_rec3_2.f2.f2 after 10 ns,
c_r_st_rec3_1.f2.f2 after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec3.f2.f2 =
c_r_st_rec3_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec3.f2.f2 =
c_r_st_rec3_1.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00189.P3" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec3.f2.f2 <=
c_r_st_rec3_2.f2.f2 after 10 ns ,
c_r_st_rec3_1.f2.f2 after 20 ns ,
c_r_st_rec3_2.f2.f2 after 30 ns ,
c_r_st_rec3_1.f2.f2 after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec3.f2.f2 =
c_r_st_rec3_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec3.f2.f2 <=
c_r_st_rec3_1.f2.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec3.f2.f2 =
c_r_st_rec3_1.f2.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00189" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec3.f2.f2 <= transport
c_r_st_rec3_1.f2.f2 after 100 ns ;
--
when 5
=> correct :=
s_r_st_rec3.f2.f2 =
c_r_st_rec3_1.f2.f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00189" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec3.f2.f2 <=
c_r_st_rec3_2.f2.f2 after 10 ns ,
c_r_st_rec3_1.f2.f2 after 20 ns ,
c_r_st_rec3_2.f2.f2 after 30 ns ,
c_r_st_rec3_1.f2.f2 after 40 ns ;
--
when 6
=> correct :=
s_r_st_rec3.f2.f2 =
c_r_st_rec3_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00189" ,
"One inertial transaction occurred on signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_rec3.f2.f2 <=
c_r_st_rec3_1.f2.f2 after 40 ns ;
--
when 7
=> correct :=
s_r_st_rec3.f2.f2 =
c_r_st_rec3_1.f2.f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_rec3.f2.f2 =
c_r_st_rec3_1.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00189" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00189" ,
"Inertial semantics check on a signal " &
"asg with selected name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_r_st_rec3'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P3 ;
--
PGEN_CHKP_3 :
process ( chk_r_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions entirely completed",
chk_r_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
--
end ARCH00189 ;
--
use WORK.STANDARD_TYPES.all ;
use WORK.PKG00189.all ;
entity ENT00189_Test_Bench is
signal s_r_st_rec1 : r_st_rec1
:= c_r_st_rec1_1 ;
signal s_r_st_rec2 : r_st_rec2
:= c_r_st_rec2_1 ;
signal s_r_st_rec3 : r_st_rec3
:= c_r_st_rec3_1 ;
--
end ENT00189_Test_Bench ;
--
architecture ARCH00189_Test_Bench of ENT00189_Test_Bench is
begin
L1:
block
component UUT
port (
s_r_st_rec1 : inout r_st_rec1
; s_r_st_rec2 : inout r_st_rec2
; s_r_st_rec3 : inout r_st_rec3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00189 ( ARCH00189 ) ;
begin
CIS1 : UUT
port map (
s_r_st_rec1
, s_r_st_rec2
, s_r_st_rec3
) ;
end block L1 ;
end ARCH00189_Test_Bench ;
| gpl-3.0 | 11dfe71f51d97dea74c3751ec6f7f84f | 0.455257 | 3.266543 | false | true | false | false |
grwlf/vsim | vhdl_ct/STD/standard.vhd | 1 | 17,693 | -- The sven STANDARD package.
-- This design unit contains some special tokens, which are only
-- recognized by the analyzer when it is in special "bootstrap" mode.
package STANDARD is
-- predefined enumeration types:
type BOOLEAN is (FALSE, TRUE);
type INTEGER is range 0 to 2147483647;
type REAL is range 0.0 to 1.79769e+308;
function "-" ( a, b: integer ) return integer;
function "-" ( a: integer ) return integer;
function "+" ( a, b: integer ) return integer;
function "+" ( a: integer ) return integer;
function "*" ( a, b: integer ) return integer;
function "/" ( a, b: integer ) return integer;
function "mod" ( a, b: integer ) return integer;
function "rem" (anonymous, anonymous2: integer) return integer;
function "**" ( a, b: integer ) return integer;
function "=" (anonymous, anonymous2: real) return BOOLEAN;
function "/=" (anonymous, anonymous2: real) return BOOLEAN;
function "<" (anonymous, anonymous2: real) return BOOLEAN;
function "<=" (anonymous, anonymous2: real) return BOOLEAN;
function ">" (anonymous, anonymous2: real) return BOOLEAN;
function ">=" (anonymous, anonymous2: real) return BOOLEAN;
function "+" (anonymous: real) return real;
function "-" (anonymous: real) return real;
function "abs" (anonymous: real) return real;
function "+" (anonymous, anonymous2: real) return real;
function "-" (anonymous, anonymous2: real) return real;
function "*" (anonymous, anonymous2: real) return real;
function "/" (anonymous, anonymous2: real) return real;
function "*" (anonymous: real; anonymous: integer)
return real;
function "*" (anonymous: integer; anonymous: real)
return real;
function "/" (anonymous: real; anonymous: integer)
return real;
type INTEGER is range -2147483647-1 to 2147483647;
-- -2147483648 doesn't work, seems that it parsed as unary minus 2147483648
type REAL is range -1.79769e+308 to 1.79769e+308;
function "and" (anonymous1, anonymous2: BOOLEAN) return BOOLEAN;
function "or" (anonymous1, anonymous2: BOOLEAN) return BOOLEAN;
function "nand" (anonymous1, anonymous2: BOOLEAN) return BOOLEAN;
function "nor" (anonymous1, anonymous2: BOOLEAN) return BOOLEAN;
function "xor" (anonymous1, anonymous2: BOOLEAN) return BOOLEAN;
function "xnor" (anonymous1, anonymous2: BOOLEAN) return BOOLEAN;
function "not" (anonymous1: BOOLEAN) return BOOLEAN;
function "=" (anonymous1, anonymous2: BOOLEAN) return BOOLEAN;
function "/=" (anonymous1, anonymous2: BOOLEAN) return BOOLEAN;
function "<" (anonymous1, anonymous2: BOOLEAN) return BOOLEAN;
function "<=" (anonymous1, anonymous2: BOOLEAN) return BOOLEAN;
function ">" (anonymous1, anonymous2: BOOLEAN) return BOOLEAN;
function ">=" (anonymous1, anonymous2: BOOLEAN) return BOOLEAN;
type BIT is ('0', '1');
--The predefined operators for this type are as follows:
function "and" (anonymous, anonymous: BIT) return BIT;
function "or" (anonymous, anonymous: BIT) return BIT;
function "nand" (anonymous, anonymous: BIT) return BIT;
function "nor" (anonymous, anonymous: BIT) return BIT;
function "xor" (anonymous, anonymous: BIT) return BIT;
function "xnor" (anonymous, anonymous: BIT) return BIT;
function "not" (anonymous: BIT) return BIT;
function "=" (anonymous, anonymous: BIT) return BOOLEAN;
function "/=" (anonymous, anonymous: BIT) return BOOLEAN;
function "<" (anonymous, anonymous: BIT) return BOOLEAN;
function "<=" (anonymous, anonymous: BIT) return BOOLEAN;
function ">" (anonymous, anonymous: BIT) return BOOLEAN;
function ">=" (anonymous, anonymous: BIT) return BOOLEAN;
type CHARACTER is (
NUL, SOH, STX, ETX, EOT, ENQ, ACK, BEL,
BS, HT, LF, VT, FF, CR, SO, SI,
DLE, DC1, DC2, DC3, DC4, NAK, SYN, ETB,
CAN, EM, SUB, ESC, FSP, GSP, RSP, USP,
' ', '!', '"', '#', '$', '%', '&', ''',
'(', ')', '*', '+', ',', '-', '.', '/',
'0', '1', '2', '3', '4', '5', '6', '7',
'8', '9', ':', ';', '<', '=', '>', '?',
'@', 'A', 'B', 'C', 'D', 'E', 'F', 'G',
'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O',
'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W',
'X', 'Y', 'Z', '[', '\', ']', '^', '_',
'`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '{', '|', '}', '~', DEL,
C128, C129, C130, C131, C132, C133, C134, C135,
C136, C137, C138, C139, C140, C141, C142, C143,
C144, C145, C146, C147, C148, C149, C150, C151,
C152, C153, C154, C155, C156, C157, C158, C159
--,
-- ' ', '�', '�', '�', '�', '�', '�', '�',
-- '�', '�', '�', '�', '�', '�', '�', '�',
-- '�', '�', '�', '�', '�', '�', '�', '�',
-- '�', '�', '�', '�', '�', '�', '�', '�',
-- '�', '�', '�', '�', '�', '�', '�', '�',
-- '�', '�', '�', '�', '�', '�', '�', '�',
-- '�', '�', '�', '�', '�', '�', '�', '�',
-- '�', '�', '�', '�', '�', '�', '�', '�',
-- '�', '�', '�', '�', '�', '�', '�', '�',
-- '�', '�', '�', '�', '�', '�', '�', '�',
-- '�', '�', '�', '�', '�', '�', '�', '�',
-- '�', '�', '�', '�', '�', '�', '�', '�'
);
type SEVERITY_LEVEL is (NOTE, WARNING, ERROR, FAILURE);
-- predefined numeric types:
-- Do INTEGER first to aid implicit declarations of "**".
-- type INTEGER is range -2147483647 to 2147483647;
-- type $UNIVERSAL_INTEGER is range $- to $+;
-- type $real is range $-. to $+.;
function "*" (LEFT: real; RIGHT: INTEGER)
return real;
function "*" (LEFT: INTEGER; RIGHT: REAL)
return REAL;
function "/" (LEFT: REAL; RIGHT: INTEGER)
return REAL;
-- type REAL is range $-. to $+.;
-- predefined type TIME:
type TIME is range -1000000 to +100000000
units
fs; -- femtosecond
ps = 1000 fs; -- picosecond
ns = 1000 ps; -- nanosecond
us = 1000 ns; -- microsecond
ms = 1000 us; -- millisecond
sec = 1000 ms; -- second
min = 60 sec; -- minute
hr = 60 min; -- hour;
end units;
function "=" (anonymous1, anonymous2: TIME) return BOOLEAN;
function "/=" (anonymous1, anonymous2: TIME) return BOOLEAN;
function "<" (anonymous1, anonymous2: TIME) return BOOLEAN;
function "<=" (anonymous1, anonymous2: TIME) return BOOLEAN;
function ">" (anonymous1, anonymous2: TIME) return BOOLEAN;
function ">=" (anonymous1, anonymous2: TIME) return BOOLEAN;
function "+" (anonymous1: TIME) return TIME;
function "-" (anonymous1: TIME) return TIME;
function "abs" (anonymous1: TIME) return TIME;
function "+" (anonymous1, anonymous2: TIME) return TIME;
function "-" (anonymous1, anonymous2: TIME) return TIME;
function "*" (anonymous1: TIME; anonymous2: INTEGER) return TIME;
function "*" (anonymous1: TIME; anonymous2: REAL) return TIME;
function "*" (anonymous1: INTEGER; anonymous2: TIME) return TIME;
function "*" (anonymous1: REAL; anonymous2: TIME) return TIME;
function "/" (anonymous1: TIME; anonymous2: INTEGER) return TIME;
function "/" (anonymous1: TIME; anonymous2: REAL) return TIME;
function "/" (anonymous1, anonymous2: TIME) return INTEGER;
function "**" (anonymous: real; anonymous: INTEGER)
return real;
-- subtype used internally for checking time expressions for non-negativness:
-- subtype $NATURAL_TIME is TIME range 0 sec to TIME'HIGH;
subtype DELAY_LENGTH is TIME range 0 fs to TIME'HIGH;
-- function that returns the current simulation time:
impure function NOW return TIME;
-- predefined numeric subtypes:
subtype NATURAL is INTEGER range 0 to INTEGER'HIGH;
subtype POSITIVE is INTEGER range 1 to INTEGER'HIGH;
-- predefined array types:
type STRING is array (POSITIVE range <>) of CHARACTER;
function "&" ( a, b: STRING ) return STRING;
type BIT_VECTOR is array (NATURAL range <>) of BIT;
--type FILE_OPEN_KIND is (READ_OPEN, WRITE_OPEN, APPEND_OPEN);
type FILE_OPEN_KIND is (READ_MODE, WRITE_MODE, APPEND_MODE);
type FILE_OPEN_STATUS is (OPEN_OK, STATUS_ERROR, NAME_ERROR, MODE_ERROR);
attribute FOREIGN: STRING;
--
-- The rest of this package is SVEN specific stuff required to make
-- this implementation go.
-- Note that all things are declared use leading $ characters, so we don't
-- trample the user's name space.
--
-- attribute $BUILTIN: BOOLEAN;
-- procedure $RTINDEX (I: NATURAL; FIRSTARG: INTEGER; PASSAP,SAVEFREGS: BOOLEAN);
-- procedure $RTSYMBOL (S: STRING; FIRSTARG: INTEGER; PASSAP,SAVEFREGS: BOOLEAN);
-- attribute $BUILTIN of all: function is TRUE;
-- attribute $BUILTIN of all: procedure is TRUE;
function "and" (l, r: BIT_VECTOR) return BIT_VECTOR;
-- function "and" (anonymous, anonymous2: BIT_VECTOR) return BIT_VECTOR;
function "or" (l, r: BIT_VECTOR) return BIT_VECTOR;
function "nand" (anonymous, anonymous2: BIT_VECTOR) return BIT_VECTOR;
function "nor" (anonymous, anonymous2: BIT_VECTOR) return BIT_VECTOR;
function "xor" (l, r: BIT_VECTOR) return BIT_VECTOR;
function "xnor" (anonymous, anonymous2: BIT_VECTOR) return BIT_VECTOR;
function "not" (l: BIT_VECTOR) return BIT_VECTOR;
-- function "not" (anonymous: BIT_VECTOR) return BIT_VECTOR;
function "sll" (ARG: BIT_VECTOR; COUNT: INTEGER)
return BIT_VECTOR;
function "srl" (ARG: BIT_VECTOR; COUNT: INTEGER)
return BIT_VECTOR;
-- function "sll" (anonymous: BIT_VECTOR; anonymous2: INTEGER)
-- return BIT_VECTOR;
-- function "srl" (anonymous: BIT_VECTOR; anonymous2: INTEGER)
-- return BIT_VECTOR;
function "sla" (anonymous: BIT_VECTOR; anonymous2: INTEGER)
return BIT_VECTOR;
function "sra" (anonymous: BIT_VECTOR; anonymous2: INTEGER)
return BIT_VECTOR;
function "rol" (ARG: BIT_VECTOR; COUNT: INTEGER)
return BIT_VECTOR;
function "ror" (ARG: BIT_VECTOR; COUNT: INTEGER)
return BIT_VECTOR;
-- function "rol" (anonymous: BIT_VECTOR; anonymous2: INTEGER)
-- return BIT_VECTOR;
-- function "ror" (anonymous: BIT_VECTOR; anonymous2: INTEGER)
-- return BIT_VECTOR;
function "=" (anonymous, anonymous2: BIT_VECTOR) return BOOLEAN;
function "/=" (anonymous, anonymous2: BIT_VECTOR) return BOOLEAN;
function "<" (anonymous, anonymous2: BIT_VECTOR) return BOOLEAN;
function "<=" (anonymous, anonymous2: BIT_VECTOR) return BOOLEAN;
function ">" (anonymous, anonymous2: BIT_VECTOR) return BOOLEAN;
function ">=" (anonymous, anonymous2: BIT_VECTOR) return BOOLEAN;
function "&" (anonymous: BIT_VECTOR; anonymous2: BIT_VECTOR)
return BIT_VECTOR;
function "&" (anonymous: BIT_VECTOR; anonymous2: BIT) return BIT_VECTOR;
function "&" (anonymous: BIT; anonymous2: BIT_VECTOR) return BIT_VECTOR;
function "&" (anonymous: BIT; anonymous2: BIT) return BIT_VECTOR;
end STANDARD;
PACKAGE BODY STANDARD IS
-- logic and shift functions on bit_vector are not builtin
FUNCTION "and" ( l,r : BIT_VECTOR ) RETURN BIT_VECTOR IS
ALIAS lv : BIT_VECTOR ( 1 TO l'LENGTH ) IS l;
ALIAS rv : BIT_VECTOR ( 1 TO r'LENGTH ) IS r;
VARIABLE result : BIT_VECTOR ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
-- REPORT "arguments of overloaded 'and' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := lv(i) and rv(i);
END LOOP;
END IF;
RETURN result;
END "and";
FUNCTION "or" ( l,r : BIT_VECTOR ) RETURN BIT_VECTOR IS
ALIAS lv : BIT_VECTOR ( 1 TO l'LENGTH ) IS l;
ALIAS rv : BIT_VECTOR ( 1 TO r'LENGTH ) IS r;
VARIABLE result : BIT_VECTOR ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
-- REPORT "arguments of overloaded 'or' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := lv(i) or rv(i);
END LOOP;
END IF;
RETURN result;
END "or";
FUNCTION "xor" ( l,r : BIT_VECTOR ) RETURN BIT_VECTOR IS
ALIAS lv : BIT_VECTOR ( 1 TO l'LENGTH ) IS l;
ALIAS rv : BIT_VECTOR ( 1 TO r'LENGTH ) IS r;
VARIABLE result : BIT_VECTOR ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
-- REPORT "arguments of overloaded 'xor' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := lv(i) xor rv(i);
END LOOP;
END IF;
RETURN result;
END "xor";
FUNCTION "not" ( l : BIT_VECTOR ) RETURN BIT_VECTOR IS
-- strange, but translator raises NPE if we rename 'l' to
-- something else
ALIAS lv : BIT_VECTOR ( 1 TO l'LENGTH ) IS l;
VARIABLE result : BIT_VECTOR ( 1 TO l'LENGTH ) := (OTHERS => '0');
BEGIN
FOR i IN result'RANGE LOOP
result(i) := not lv(i);
END LOOP;
RETURN result;
END;
function XSLL (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0) := (others => '0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L downto COUNT) := XARG(ARG_L-COUNT downto 0);
end if;
return RESULT;
end XSLL;
function XSRL (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0) := (others => '0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L-COUNT downto 0) := XARG(ARG_L downto COUNT);
end if;
return RESULT;
end XSRL;
function XSRA (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0);
variable XCOUNT: NATURAL := COUNT;
begin
if ((ARG'LENGTH <= 1) or (XCOUNT = 0)) then return ARG;
else
if (XCOUNT > ARG_L) then XCOUNT := ARG_L;
end if;
RESULT(ARG_L-XCOUNT downto 0) := XARG(ARG_L downto XCOUNT);
RESULT(ARG_L downto (ARG_L - XCOUNT + 1)) := (others => XARG(ARG_L));
end if;
return RESULT;
end XSRA;
function XROL (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM: INTEGER;
begin
COUNTM := COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L downto COUNTM) := XARG(ARG_L-COUNTM downto 0);
RESULT(COUNTM-1 downto 0) := XARG(ARG_L downto ARG_L-COUNTM+1);
end if;
return RESULT;
end XROL;
function XROR (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM: INTEGER;
begin
COUNTM := COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L-COUNTM downto 0) := XARG(ARG_L downto COUNTM);
RESULT(ARG_L downto ARG_L-COUNTM+1) := XARG(COUNTM-1 downto 0);
end if;
return RESULT;
end XROR;
constant NAU: BIT_VECTOR(0 downto 1) := (others => '0');
-- Id: S.1
function SHIFT_LEFT (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return (XSLL((ARG), COUNT));
end SHIFT_LEFT;
-- Id: S.2
function SHIFT_RIGHT (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return (XSRL((ARG), COUNT));
end SHIFT_RIGHT;
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return (XROL((ARG), COUNT));
end ROTATE_LEFT;
-- Id: S.6
function ROTATE_RIGHT (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return (XROR((ARG), COUNT));
end ROTATE_RIGHT;
--============================================================================
function "sll" (ARG: BIT_VECTOR; COUNT: INTEGER) return BIT_VECTOR is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end "sll";
function "srl" (ARG: BIT_VECTOR; COUNT: INTEGER) return BIT_VECTOR is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end "srl";
function "rol" (ARG: BIT_VECTOR; COUNT: INTEGER) return BIT_VECTOR is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end "rol";
function "ror" (ARG: BIT_VECTOR; COUNT: INTEGER) return BIT_VECTOR is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end "ror";
end STANDARD;
| gpl-3.0 | f1e0cc8bd458cb8ce750ba287785aedb | 0.599326 | 3.362082 | false | false | false | false |
rauenzi/VHDL-Communications | Serial_TTL_Display.vhd | 1 | 3,207 | ----------------------------------------------------------------------------------
--Code by: Zachary Rauen
--Date: 10/28/14
--Last Modified: 11/2/14
--
--Description: This takes in 16 bit data and displays them on an external display
-- using GPIO and serial ttl communication.
--
--Version: 1.3
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Serial_TTL_display is
Generic (BaudSpeed : integer :=9600;
Boardspeed : integer :=100000000);
Port ( Clock : in STD_LOGIC;
Data : in STD_LOGIC_VECTOR (15 downto 0);
RX : out STD_LOGIC);
end Serial_TTL_display;
architecture Behavioral of Serial_TTL_display is
signal DataSection : std_logic_vector(7 downto 0);
type state_type is (bit0,bit1,bit2,bit3,bit4,bit5,bit6,bit7,bit8,bit9);
signal nextState : state_type;
signal currentState : state_type := bit0;
signal bitEnableCnt,ByteChoice : integer:=0;
signal ByteMax : integer :=8;
signal BitEnable : std_logic :='0';
signal BaudClockEnableMax : integer := Boardspeed/BaudSpeed-1;
begin
BitEnabler: process(Clock)
begin
if rising_edge(Clock) then
if bitEnableCnt = BaudClockEnableMax then
BitEnable <= '1';
bitEnableCnt <= 0;
else
bitEnableCnt<=bitEnableCnt+1;
BitEnable <= '0';
end if;
end if;
end process BitEnabler;
StateChange: process (Clock,BitEnable)
begin
if (rising_edge(Clock) and BitEnable='1') then
if currentState = bit9 then
if ByteChoice = ByteMax then
ByteChoice <= Bytechoice-3;
else
ByteChoice<=ByteChoice+1;
end if;
end if;
currentState <= nextState;
end if;
end process StateChange;
States: process(currentState)
begin
case currentState is
when bit0=>
RX<='0';
nextState<=bit1;
when bit1=>
RX<=DataSection(0);
nextState<=bit2;
when bit2=>
RX<=DataSection(1);
nextState<=bit3;
when bit3=>
RX<=DataSection(2);
nextState<=bit4;
when bit4=>
RX<=DataSection(3);
nextState<=bit5;
when bit5=>
RX<=DataSection(4);
nextState<=bit6;
when bit6=>
RX<=DataSection(5);
nextState<=bit7;
when bit7=>
RX<=DataSection(6);
nextState<=bit8;
when bit8=>
RX<=DataSection(7);
nextState<=bit9;
when bit9=>
RX<='1';
nextState<=bit0;
end case;
case ByteChoice is
when 0 => DataSection<=x"76";
when 1 => DataSection<=x"76";
when 2 => DataSection<=x"76";
when 3 => DataSection<=x"76";
when 4 => DataSection<=x"76";
-- when 5 => DataSection<=x"7A";
-- when 6 => DataSection<=std_logic_vector(to_unsigned(0, 8));
-- when 6 => DataSection<=x"79";
-- when 7 => DataSection<=std_logic_vector(to_unsigned(0, 8));
when 5 => DataSection <=x"0" & Data(15 downto 12);
when 6 => DataSection <=x"0" & Data(11 downto 8);
when 7 => DataSection <=x"0" & Data(7 downto 4);
when 8 => DataSection <=x"0" & Data(3 downto 0);
when others => DataSection <="11111111";
end case;
end process States;
end Behavioral;
| apache-2.0 | e9de322714050db17887eca4dad7f424 | 0.589336 | 3.478308 | false | false | false | false |
jairov4/accel-oil | solution_spartan6/syn/vhdl/p_bsf32_hw.vhd | 3 | 81,913 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity p_bsf32_hw is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
bus_r : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (4 downto 0);
ap_ce : IN STD_LOGIC );
end;
architecture behav of p_bsf32_hw is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_lv5_1 : STD_LOGIC_VECTOR (4 downto 0) := "00001";
constant ap_const_lv5_2 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
constant ap_const_lv5_3 : STD_LOGIC_VECTOR (4 downto 0) := "00011";
constant ap_const_lv5_4 : STD_LOGIC_VECTOR (4 downto 0) := "00100";
constant ap_const_lv5_5 : STD_LOGIC_VECTOR (4 downto 0) := "00101";
constant ap_const_lv5_6 : STD_LOGIC_VECTOR (4 downto 0) := "00110";
constant ap_const_lv5_7 : STD_LOGIC_VECTOR (4 downto 0) := "00111";
constant ap_const_lv5_8 : STD_LOGIC_VECTOR (4 downto 0) := "01000";
constant ap_const_lv5_9 : STD_LOGIC_VECTOR (4 downto 0) := "01001";
constant ap_const_lv5_A : STD_LOGIC_VECTOR (4 downto 0) := "01010";
constant ap_const_lv5_B : STD_LOGIC_VECTOR (4 downto 0) := "01011";
constant ap_const_lv5_C : STD_LOGIC_VECTOR (4 downto 0) := "01100";
constant ap_const_lv5_D : STD_LOGIC_VECTOR (4 downto 0) := "01101";
constant ap_const_lv5_E : STD_LOGIC_VECTOR (4 downto 0) := "01110";
constant ap_const_lv5_F : STD_LOGIC_VECTOR (4 downto 0) := "01111";
constant ap_const_lv5_10 : STD_LOGIC_VECTOR (4 downto 0) := "10000";
constant ap_const_lv5_11 : STD_LOGIC_VECTOR (4 downto 0) := "10001";
constant ap_const_lv5_12 : STD_LOGIC_VECTOR (4 downto 0) := "10010";
constant ap_const_lv5_13 : STD_LOGIC_VECTOR (4 downto 0) := "10011";
constant ap_const_lv5_14 : STD_LOGIC_VECTOR (4 downto 0) := "10100";
constant ap_const_lv5_15 : STD_LOGIC_VECTOR (4 downto 0) := "10101";
constant ap_const_lv5_16 : STD_LOGIC_VECTOR (4 downto 0) := "10110";
constant ap_const_lv5_17 : STD_LOGIC_VECTOR (4 downto 0) := "10111";
constant ap_const_lv5_18 : STD_LOGIC_VECTOR (4 downto 0) := "11000";
constant ap_const_lv5_19 : STD_LOGIC_VECTOR (4 downto 0) := "11001";
constant ap_const_lv5_1A : STD_LOGIC_VECTOR (4 downto 0) := "11010";
constant ap_const_lv5_1B : STD_LOGIC_VECTOR (4 downto 0) := "11011";
constant ap_const_lv5_1C : STD_LOGIC_VECTOR (4 downto 0) := "11100";
constant ap_const_lv5_1D : STD_LOGIC_VECTOR (4 downto 0) := "11101";
constant ap_const_lv5_1E : STD_LOGIC_VECTOR (4 downto 0) := "11110";
constant ap_const_lv5_1F : STD_LOGIC_VECTOR (4 downto 0) := "11111";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101";
constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010";
constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011";
constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100";
constant ap_const_lv32_15 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010101";
constant ap_const_lv32_16 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010110";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
constant ap_const_lv32_18 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011000";
constant ap_const_lv32_19 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011001";
constant ap_const_lv32_1A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011010";
constant ap_const_lv32_1B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011011";
constant ap_const_lv32_1C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011100";
constant ap_const_lv32_1D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011101";
constant ap_const_lv32_1E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011110";
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_true : BOOLEAN := true;
signal tmp_fu_278_p1 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_reg_522 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_7_fu_282_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_7_reg_526 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_8_fu_290_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_8_reg_530 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_9_fu_298_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_9_reg_534 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_10_fu_306_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_10_reg_538 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_11_fu_314_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_11_reg_542 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_12_fu_322_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_12_reg_546 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_13_fu_330_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_13_reg_550 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_14_fu_338_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_14_reg_554 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_15_fu_346_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_15_reg_558 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_16_fu_354_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_16_reg_562 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_17_fu_362_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_17_reg_566 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_18_fu_370_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_18_reg_570 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_19_fu_378_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_19_reg_574 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_20_fu_386_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_20_reg_578 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_21_fu_394_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_21_reg_582 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_22_fu_402_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_22_reg_586 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_23_fu_410_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_23_reg_590 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_24_fu_418_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_24_reg_594 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_25_fu_426_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_25_reg_598 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_26_fu_434_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_26_reg_602 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_27_fu_442_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_27_reg_606 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_28_fu_450_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_28_reg_610 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_29_fu_458_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_29_reg_614 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_30_fu_466_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_30_reg_618 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_fu_474_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_reg_622 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_32_fu_482_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_32_reg_626 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_33_fu_490_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_33_reg_630 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_34_fu_498_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_34_reg_634 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_35_fu_506_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_35_reg_638 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_36_fu_514_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_36_reg_642 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_phiprechg_p_s_reg_136pp0_it0 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_phiprechg_p_s_reg_136pp0_it1 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_phiprechg_merge_reg_265pp0_it0 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_phiprechg_merge_reg_265pp0_it1 : STD_LOGIC_VECTOR (4 downto 0);
signal merge_phi_fu_269_p4 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_sig_bdd_764 : BOOLEAN;
signal ap_sig_bdd_178 : BOOLEAN;
signal ap_sig_bdd_183 : BOOLEAN;
signal ap_sig_bdd_189 : BOOLEAN;
signal ap_sig_bdd_196 : BOOLEAN;
signal ap_sig_bdd_204 : BOOLEAN;
signal ap_sig_bdd_213 : BOOLEAN;
signal ap_sig_bdd_223 : BOOLEAN;
signal ap_sig_bdd_234 : BOOLEAN;
signal ap_sig_bdd_246 : BOOLEAN;
signal ap_sig_bdd_259 : BOOLEAN;
signal ap_sig_bdd_273 : BOOLEAN;
signal ap_sig_bdd_288 : BOOLEAN;
signal ap_sig_bdd_304 : BOOLEAN;
signal ap_sig_bdd_321 : BOOLEAN;
signal ap_sig_bdd_339 : BOOLEAN;
signal ap_sig_bdd_358 : BOOLEAN;
signal ap_sig_bdd_378 : BOOLEAN;
signal ap_sig_bdd_399 : BOOLEAN;
signal ap_sig_bdd_421 : BOOLEAN;
signal ap_sig_bdd_444 : BOOLEAN;
signal ap_sig_bdd_468 : BOOLEAN;
signal ap_sig_bdd_493 : BOOLEAN;
signal ap_sig_bdd_519 : BOOLEAN;
signal ap_sig_bdd_546 : BOOLEAN;
signal ap_sig_bdd_574 : BOOLEAN;
signal ap_sig_bdd_603 : BOOLEAN;
signal ap_sig_bdd_633 : BOOLEAN;
signal ap_sig_bdd_664 : BOOLEAN;
signal ap_sig_bdd_696 : BOOLEAN;
signal ap_sig_bdd_730 : BOOLEAN;
begin
-- ap_reg_phiprechg_merge_reg_265pp0_it1 assign process. --
ap_reg_phiprechg_merge_reg_265pp0_it1_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_ce)) then
if (ap_sig_bdd_764) then
ap_reg_phiprechg_merge_reg_265pp0_it1(1) <= '1';
ap_reg_phiprechg_merge_reg_265pp0_it1(2) <= '1';
ap_reg_phiprechg_merge_reg_265pp0_it1(3) <= '1';
ap_reg_phiprechg_merge_reg_265pp0_it1(4) <= '1';
elsif ((ap_true = ap_true)) then
ap_reg_phiprechg_merge_reg_265pp0_it1(1) <= ap_reg_phiprechg_merge_reg_265pp0_it0(1);
ap_reg_phiprechg_merge_reg_265pp0_it1(2) <= ap_reg_phiprechg_merge_reg_265pp0_it0(2);
ap_reg_phiprechg_merge_reg_265pp0_it1(3) <= ap_reg_phiprechg_merge_reg_265pp0_it0(3);
ap_reg_phiprechg_merge_reg_265pp0_it1(4) <= ap_reg_phiprechg_merge_reg_265pp0_it0(4);
end if;
end if;
end if;
end process;
-- ap_reg_phiprechg_p_s_reg_136pp0_it1 assign process. --
ap_reg_phiprechg_p_s_reg_136pp0_it1_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_ce)) then
if (ap_sig_bdd_730) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_1E;
elsif (ap_sig_bdd_696) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_1D;
elsif (ap_sig_bdd_664) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_1C;
elsif (ap_sig_bdd_633) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_1B;
elsif (ap_sig_bdd_603) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_1A;
elsif (ap_sig_bdd_574) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_19;
elsif (ap_sig_bdd_546) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_18;
elsif (ap_sig_bdd_519) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_17;
elsif (ap_sig_bdd_493) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_16;
elsif (ap_sig_bdd_468) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_15;
elsif (ap_sig_bdd_444) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_14;
elsif (ap_sig_bdd_421) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_13;
elsif (ap_sig_bdd_399) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_12;
elsif (ap_sig_bdd_378) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_11;
elsif (ap_sig_bdd_358) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_10;
elsif (ap_sig_bdd_339) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_F;
elsif (ap_sig_bdd_321) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_E;
elsif (ap_sig_bdd_304) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_D;
elsif (ap_sig_bdd_288) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_C;
elsif (ap_sig_bdd_273) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_B;
elsif (ap_sig_bdd_259) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_A;
elsif (ap_sig_bdd_246) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_9;
elsif (ap_sig_bdd_234) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_8;
elsif (ap_sig_bdd_223) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_7;
elsif (ap_sig_bdd_213) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_6;
elsif (ap_sig_bdd_204) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_5;
elsif (ap_sig_bdd_196) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_4;
elsif (ap_sig_bdd_189) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_3;
elsif (ap_sig_bdd_183) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_2;
elsif (ap_sig_bdd_178) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_1;
elsif (not((tmp_fu_278_p1 = ap_const_lv1_0))) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_0;
elsif ((ap_true = ap_true)) then
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_reg_phiprechg_p_s_reg_136pp0_it0;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3))) then
tmp_10_reg_538 <= bus_r(4 downto 4);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3))) then
tmp_11_reg_542 <= bus_r(5 downto 5);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3))) then
tmp_12_reg_546 <= bus_r(6 downto 6);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3))) then
tmp_13_reg_550 <= bus_r(7 downto 7);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3))) then
tmp_14_reg_554 <= bus_r(8 downto 8);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3))) then
tmp_15_reg_558 <= bus_r(9 downto 9);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3))) then
tmp_16_reg_562 <= bus_r(10 downto 10);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3))) then
tmp_17_reg_566 <= bus_r(11 downto 11);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3))) then
tmp_18_reg_570 <= bus_r(12 downto 12);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3))) then
tmp_19_reg_574 <= bus_r(13 downto 13);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3))) then
tmp_20_reg_578 <= bus_r(14 downto 14);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3))) then
tmp_21_reg_582 <= bus_r(15 downto 15);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3))) then
tmp_22_reg_586 <= bus_r(16 downto 16);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3))) then
tmp_23_reg_590 <= bus_r(17 downto 17);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3))) then
tmp_24_reg_594 <= bus_r(18 downto 18);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3))) then
tmp_25_reg_598 <= bus_r(19 downto 19);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3))) then
tmp_26_reg_602 <= bus_r(20 downto 20);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3))) then
tmp_27_reg_606 <= bus_r(21 downto 21);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3))) then
tmp_28_reg_610 <= bus_r(22 downto 22);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3))) then
tmp_29_reg_614 <= bus_r(23 downto 23);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3))) then
tmp_30_reg_618 <= bus_r(24 downto 24);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3))) then
tmp_31_reg_622 <= bus_r(25 downto 25);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and (ap_const_lv1_0 = tmp_31_fu_474_p3))) then
tmp_32_reg_626 <= bus_r(26 downto 26);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and (ap_const_lv1_0 = tmp_31_fu_474_p3) and (ap_const_lv1_0 = tmp_32_fu_482_p3))) then
tmp_33_reg_630 <= bus_r(27 downto 27);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and (ap_const_lv1_0 = tmp_31_fu_474_p3) and (ap_const_lv1_0 = tmp_32_fu_482_p3) and (ap_const_lv1_0 = tmp_33_fu_490_p3))) then
tmp_34_reg_634 <= bus_r(28 downto 28);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and (ap_const_lv1_0 = tmp_31_fu_474_p3) and (ap_const_lv1_0 = tmp_32_fu_482_p3) and (ap_const_lv1_0 = tmp_33_fu_490_p3) and (ap_const_lv1_0 = tmp_34_fu_498_p3))) then
tmp_35_reg_638 <= bus_r(29 downto 29);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and (ap_const_lv1_0 = tmp_31_fu_474_p3) and (ap_const_lv1_0 = tmp_32_fu_482_p3) and (ap_const_lv1_0 = tmp_33_fu_490_p3) and (ap_const_lv1_0 = tmp_34_fu_498_p3) and (ap_const_lv1_0 = tmp_35_fu_506_p3))) then
tmp_36_reg_642 <= bus_r(30 downto 30);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0))) then
tmp_7_reg_526 <= bus_r(1 downto 1);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0))) then
tmp_8_reg_530 <= bus_r(2 downto 2);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and (tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3))) then
tmp_9_reg_534 <= bus_r(3 downto 3);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_ce)) then
tmp_reg_522 <= tmp_fu_278_p1;
end if;
end if;
end process;
ap_reg_phiprechg_merge_reg_265pp0_it1(0) <= '1';
ap_reg_phiprechg_merge_reg_265pp0_it0 <= ap_const_lv5_1;
ap_reg_phiprechg_p_s_reg_136pp0_it0 <= ap_const_lv5_1;
ap_return <= merge_phi_fu_269_p4;
-- ap_sig_bdd_178 assign process. --
ap_sig_bdd_178_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3)
begin
ap_sig_bdd_178 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and not((tmp_7_fu_282_p3 = ap_const_lv1_0)));
end process;
-- ap_sig_bdd_183 assign process. --
ap_sig_bdd_183_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3)
begin
ap_sig_bdd_183 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and not((ap_const_lv1_0 = tmp_8_fu_290_p3)));
end process;
-- ap_sig_bdd_189 assign process. --
ap_sig_bdd_189_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3)
begin
ap_sig_bdd_189 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and not((ap_const_lv1_0 = tmp_9_fu_298_p3)));
end process;
-- ap_sig_bdd_196 assign process. --
ap_sig_bdd_196_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3)
begin
ap_sig_bdd_196 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and not((ap_const_lv1_0 = tmp_10_fu_306_p3)));
end process;
-- ap_sig_bdd_204 assign process. --
ap_sig_bdd_204_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3)
begin
ap_sig_bdd_204 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and not((ap_const_lv1_0 = tmp_11_fu_314_p3)));
end process;
-- ap_sig_bdd_213 assign process. --
ap_sig_bdd_213_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3)
begin
ap_sig_bdd_213 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and not((ap_const_lv1_0 = tmp_12_fu_322_p3)));
end process;
-- ap_sig_bdd_223 assign process. --
ap_sig_bdd_223_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3)
begin
ap_sig_bdd_223 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and not((ap_const_lv1_0 = tmp_13_fu_330_p3)));
end process;
-- ap_sig_bdd_234 assign process. --
ap_sig_bdd_234_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3)
begin
ap_sig_bdd_234 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and not((ap_const_lv1_0 = tmp_14_fu_338_p3)));
end process;
-- ap_sig_bdd_246 assign process. --
ap_sig_bdd_246_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3)
begin
ap_sig_bdd_246 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and not((ap_const_lv1_0 = tmp_15_fu_346_p3)));
end process;
-- ap_sig_bdd_259 assign process. --
ap_sig_bdd_259_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3)
begin
ap_sig_bdd_259 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and not((ap_const_lv1_0 = tmp_16_fu_354_p3)));
end process;
-- ap_sig_bdd_273 assign process. --
ap_sig_bdd_273_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3)
begin
ap_sig_bdd_273 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and not((ap_const_lv1_0 = tmp_17_fu_362_p3)));
end process;
-- ap_sig_bdd_288 assign process. --
ap_sig_bdd_288_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3)
begin
ap_sig_bdd_288 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and not((ap_const_lv1_0 = tmp_18_fu_370_p3)));
end process;
-- ap_sig_bdd_304 assign process. --
ap_sig_bdd_304_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3)
begin
ap_sig_bdd_304 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and not((ap_const_lv1_0 = tmp_19_fu_378_p3)));
end process;
-- ap_sig_bdd_321 assign process. --
ap_sig_bdd_321_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3)
begin
ap_sig_bdd_321 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and not((ap_const_lv1_0 = tmp_20_fu_386_p3)));
end process;
-- ap_sig_bdd_339 assign process. --
ap_sig_bdd_339_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3)
begin
ap_sig_bdd_339 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and not((ap_const_lv1_0 = tmp_21_fu_394_p3)));
end process;
-- ap_sig_bdd_358 assign process. --
ap_sig_bdd_358_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3)
begin
ap_sig_bdd_358 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and not((ap_const_lv1_0 = tmp_22_fu_402_p3)));
end process;
-- ap_sig_bdd_378 assign process. --
ap_sig_bdd_378_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3)
begin
ap_sig_bdd_378 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and not((ap_const_lv1_0 = tmp_23_fu_410_p3)));
end process;
-- ap_sig_bdd_399 assign process. --
ap_sig_bdd_399_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3)
begin
ap_sig_bdd_399 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and not((ap_const_lv1_0 = tmp_24_fu_418_p3)));
end process;
-- ap_sig_bdd_421 assign process. --
ap_sig_bdd_421_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3)
begin
ap_sig_bdd_421 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and not((ap_const_lv1_0 = tmp_25_fu_426_p3)));
end process;
-- ap_sig_bdd_444 assign process. --
ap_sig_bdd_444_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3)
begin
ap_sig_bdd_444 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and not((ap_const_lv1_0 = tmp_26_fu_434_p3)));
end process;
-- ap_sig_bdd_468 assign process. --
ap_sig_bdd_468_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3, tmp_27_fu_442_p3)
begin
ap_sig_bdd_468 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and not((ap_const_lv1_0 = tmp_27_fu_442_p3)));
end process;
-- ap_sig_bdd_493 assign process. --
ap_sig_bdd_493_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3, tmp_27_fu_442_p3, tmp_28_fu_450_p3)
begin
ap_sig_bdd_493 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and not((ap_const_lv1_0 = tmp_28_fu_450_p3)));
end process;
-- ap_sig_bdd_519 assign process. --
ap_sig_bdd_519_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3, tmp_27_fu_442_p3, tmp_28_fu_450_p3, tmp_29_fu_458_p3)
begin
ap_sig_bdd_519 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and not((ap_const_lv1_0 = tmp_29_fu_458_p3)));
end process;
-- ap_sig_bdd_546 assign process. --
ap_sig_bdd_546_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3, tmp_27_fu_442_p3, tmp_28_fu_450_p3, tmp_29_fu_458_p3, tmp_30_fu_466_p3)
begin
ap_sig_bdd_546 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and not((ap_const_lv1_0 = tmp_30_fu_466_p3)));
end process;
-- ap_sig_bdd_574 assign process. --
ap_sig_bdd_574_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3, tmp_27_fu_442_p3, tmp_28_fu_450_p3, tmp_29_fu_458_p3, tmp_30_fu_466_p3, tmp_31_fu_474_p3)
begin
ap_sig_bdd_574 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and not((ap_const_lv1_0 = tmp_31_fu_474_p3)));
end process;
-- ap_sig_bdd_603 assign process. --
ap_sig_bdd_603_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3, tmp_27_fu_442_p3, tmp_28_fu_450_p3, tmp_29_fu_458_p3, tmp_30_fu_466_p3, tmp_31_fu_474_p3, tmp_32_fu_482_p3)
begin
ap_sig_bdd_603 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and (ap_const_lv1_0 = tmp_31_fu_474_p3) and not((ap_const_lv1_0 = tmp_32_fu_482_p3)));
end process;
-- ap_sig_bdd_633 assign process. --
ap_sig_bdd_633_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3, tmp_27_fu_442_p3, tmp_28_fu_450_p3, tmp_29_fu_458_p3, tmp_30_fu_466_p3, tmp_31_fu_474_p3, tmp_32_fu_482_p3, tmp_33_fu_490_p3)
begin
ap_sig_bdd_633 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and (ap_const_lv1_0 = tmp_31_fu_474_p3) and (ap_const_lv1_0 = tmp_32_fu_482_p3) and not((ap_const_lv1_0 = tmp_33_fu_490_p3)));
end process;
-- ap_sig_bdd_664 assign process. --
ap_sig_bdd_664_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3, tmp_27_fu_442_p3, tmp_28_fu_450_p3, tmp_29_fu_458_p3, tmp_30_fu_466_p3, tmp_31_fu_474_p3, tmp_32_fu_482_p3, tmp_33_fu_490_p3, tmp_34_fu_498_p3)
begin
ap_sig_bdd_664 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and (ap_const_lv1_0 = tmp_31_fu_474_p3) and (ap_const_lv1_0 = tmp_32_fu_482_p3) and (ap_const_lv1_0 = tmp_33_fu_490_p3) and not((ap_const_lv1_0 = tmp_34_fu_498_p3)));
end process;
-- ap_sig_bdd_696 assign process. --
ap_sig_bdd_696_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3, tmp_27_fu_442_p3, tmp_28_fu_450_p3, tmp_29_fu_458_p3, tmp_30_fu_466_p3, tmp_31_fu_474_p3, tmp_32_fu_482_p3, tmp_33_fu_490_p3, tmp_34_fu_498_p3, tmp_35_fu_506_p3)
begin
ap_sig_bdd_696 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and (ap_const_lv1_0 = tmp_31_fu_474_p3) and (ap_const_lv1_0 = tmp_32_fu_482_p3) and (ap_const_lv1_0 = tmp_33_fu_490_p3) and (ap_const_lv1_0 = tmp_34_fu_498_p3) and not((ap_const_lv1_0 = tmp_35_fu_506_p3)));
end process;
-- ap_sig_bdd_730 assign process. --
ap_sig_bdd_730_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3, tmp_27_fu_442_p3, tmp_28_fu_450_p3, tmp_29_fu_458_p3, tmp_30_fu_466_p3, tmp_31_fu_474_p3, tmp_32_fu_482_p3, tmp_33_fu_490_p3, tmp_34_fu_498_p3, tmp_35_fu_506_p3, tmp_36_fu_514_p3)
begin
ap_sig_bdd_730 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and (ap_const_lv1_0 = tmp_31_fu_474_p3) and (ap_const_lv1_0 = tmp_32_fu_482_p3) and (ap_const_lv1_0 = tmp_33_fu_490_p3) and (ap_const_lv1_0 = tmp_34_fu_498_p3) and (ap_const_lv1_0 = tmp_35_fu_506_p3) and not((ap_const_lv1_0 = tmp_36_fu_514_p3)));
end process;
-- ap_sig_bdd_764 assign process. --
ap_sig_bdd_764_assign_proc : process(tmp_fu_278_p1, tmp_7_fu_282_p3, tmp_8_fu_290_p3, tmp_9_fu_298_p3, tmp_10_fu_306_p3, tmp_11_fu_314_p3, tmp_12_fu_322_p3, tmp_13_fu_330_p3, tmp_14_fu_338_p3, tmp_15_fu_346_p3, tmp_16_fu_354_p3, tmp_17_fu_362_p3, tmp_18_fu_370_p3, tmp_19_fu_378_p3, tmp_20_fu_386_p3, tmp_21_fu_394_p3, tmp_22_fu_402_p3, tmp_23_fu_410_p3, tmp_24_fu_418_p3, tmp_25_fu_426_p3, tmp_26_fu_434_p3, tmp_27_fu_442_p3, tmp_28_fu_450_p3, tmp_29_fu_458_p3, tmp_30_fu_466_p3, tmp_31_fu_474_p3, tmp_32_fu_482_p3, tmp_33_fu_490_p3, tmp_34_fu_498_p3, tmp_35_fu_506_p3, tmp_36_fu_514_p3)
begin
ap_sig_bdd_764 <= ((tmp_fu_278_p1 = ap_const_lv1_0) and (tmp_7_fu_282_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_8_fu_290_p3) and (ap_const_lv1_0 = tmp_9_fu_298_p3) and (ap_const_lv1_0 = tmp_10_fu_306_p3) and (ap_const_lv1_0 = tmp_11_fu_314_p3) and (ap_const_lv1_0 = tmp_12_fu_322_p3) and (ap_const_lv1_0 = tmp_13_fu_330_p3) and (ap_const_lv1_0 = tmp_14_fu_338_p3) and (ap_const_lv1_0 = tmp_15_fu_346_p3) and (ap_const_lv1_0 = tmp_16_fu_354_p3) and (ap_const_lv1_0 = tmp_17_fu_362_p3) and (ap_const_lv1_0 = tmp_18_fu_370_p3) and (ap_const_lv1_0 = tmp_19_fu_378_p3) and (ap_const_lv1_0 = tmp_20_fu_386_p3) and (ap_const_lv1_0 = tmp_21_fu_394_p3) and (ap_const_lv1_0 = tmp_22_fu_402_p3) and (ap_const_lv1_0 = tmp_23_fu_410_p3) and (ap_const_lv1_0 = tmp_24_fu_418_p3) and (ap_const_lv1_0 = tmp_25_fu_426_p3) and (ap_const_lv1_0 = tmp_26_fu_434_p3) and (ap_const_lv1_0 = tmp_27_fu_442_p3) and (ap_const_lv1_0 = tmp_28_fu_450_p3) and (ap_const_lv1_0 = tmp_29_fu_458_p3) and (ap_const_lv1_0 = tmp_30_fu_466_p3) and (ap_const_lv1_0 = tmp_31_fu_474_p3) and (ap_const_lv1_0 = tmp_32_fu_482_p3) and (ap_const_lv1_0 = tmp_33_fu_490_p3) and (ap_const_lv1_0 = tmp_34_fu_498_p3) and (ap_const_lv1_0 = tmp_35_fu_506_p3) and (ap_const_lv1_0 = tmp_36_fu_514_p3));
end process;
-- merge_phi_fu_269_p4 assign process. --
merge_phi_fu_269_p4_assign_proc : process(tmp_reg_522, tmp_7_reg_526, tmp_8_reg_530, tmp_9_reg_534, tmp_10_reg_538, tmp_11_reg_542, tmp_12_reg_546, tmp_13_reg_550, tmp_14_reg_554, tmp_15_reg_558, tmp_16_reg_562, tmp_17_reg_566, tmp_18_reg_570, tmp_19_reg_574, tmp_20_reg_578, tmp_21_reg_582, tmp_22_reg_586, tmp_23_reg_590, tmp_24_reg_594, tmp_25_reg_598, tmp_26_reg_602, tmp_27_reg_606, tmp_28_reg_610, tmp_29_reg_614, tmp_30_reg_618, tmp_31_reg_622, tmp_32_reg_626, tmp_33_reg_630, tmp_34_reg_634, tmp_35_reg_638, tmp_36_reg_642, ap_reg_phiprechg_p_s_reg_136pp0_it1, ap_reg_phiprechg_merge_reg_265pp0_it1)
begin
if ((not((tmp_reg_522 = ap_const_lv1_0)) or not((tmp_7_reg_526 = ap_const_lv1_0)) or not((ap_const_lv1_0 = tmp_8_reg_530)) or not((ap_const_lv1_0 = tmp_9_reg_534)) or not((ap_const_lv1_0 = tmp_10_reg_538)) or not((ap_const_lv1_0 = tmp_11_reg_542)) or not((ap_const_lv1_0 = tmp_12_reg_546)) or not((ap_const_lv1_0 = tmp_13_reg_550)) or not((ap_const_lv1_0 = tmp_14_reg_554)) or not((ap_const_lv1_0 = tmp_15_reg_558)) or not((ap_const_lv1_0 = tmp_16_reg_562)) or not((ap_const_lv1_0 = tmp_17_reg_566)) or not((ap_const_lv1_0 = tmp_18_reg_570)) or not((ap_const_lv1_0 = tmp_19_reg_574)) or not((ap_const_lv1_0 = tmp_20_reg_578)) or not((ap_const_lv1_0 = tmp_21_reg_582)) or not((ap_const_lv1_0 = tmp_22_reg_586)) or not((ap_const_lv1_0 = tmp_23_reg_590)) or not((ap_const_lv1_0 = tmp_24_reg_594)) or not((ap_const_lv1_0 = tmp_25_reg_598)) or not((ap_const_lv1_0 = tmp_26_reg_602)) or not((ap_const_lv1_0 = tmp_27_reg_606)) or not((ap_const_lv1_0 = tmp_28_reg_610)) or not((ap_const_lv1_0 = tmp_29_reg_614)) or not((ap_const_lv1_0 = tmp_30_reg_618)) or not((ap_const_lv1_0 = tmp_31_reg_622)) or not((ap_const_lv1_0 = tmp_32_reg_626)) or not((ap_const_lv1_0 = tmp_33_reg_630)) or not((ap_const_lv1_0 = tmp_34_reg_634)) or not((ap_const_lv1_0 = tmp_35_reg_638)) or not((ap_const_lv1_0 = tmp_36_reg_642)))) then
merge_phi_fu_269_p4 <= ap_reg_phiprechg_p_s_reg_136pp0_it1;
else
merge_phi_fu_269_p4 <= ap_reg_phiprechg_merge_reg_265pp0_it1;
end if;
end process;
tmp_10_fu_306_p3 <= bus_r(4 downto 4);
tmp_11_fu_314_p3 <= bus_r(5 downto 5);
tmp_12_fu_322_p3 <= bus_r(6 downto 6);
tmp_13_fu_330_p3 <= bus_r(7 downto 7);
tmp_14_fu_338_p3 <= bus_r(8 downto 8);
tmp_15_fu_346_p3 <= bus_r(9 downto 9);
tmp_16_fu_354_p3 <= bus_r(10 downto 10);
tmp_17_fu_362_p3 <= bus_r(11 downto 11);
tmp_18_fu_370_p3 <= bus_r(12 downto 12);
tmp_19_fu_378_p3 <= bus_r(13 downto 13);
tmp_20_fu_386_p3 <= bus_r(14 downto 14);
tmp_21_fu_394_p3 <= bus_r(15 downto 15);
tmp_22_fu_402_p3 <= bus_r(16 downto 16);
tmp_23_fu_410_p3 <= bus_r(17 downto 17);
tmp_24_fu_418_p3 <= bus_r(18 downto 18);
tmp_25_fu_426_p3 <= bus_r(19 downto 19);
tmp_26_fu_434_p3 <= bus_r(20 downto 20);
tmp_27_fu_442_p3 <= bus_r(21 downto 21);
tmp_28_fu_450_p3 <= bus_r(22 downto 22);
tmp_29_fu_458_p3 <= bus_r(23 downto 23);
tmp_30_fu_466_p3 <= bus_r(24 downto 24);
tmp_31_fu_474_p3 <= bus_r(25 downto 25);
tmp_32_fu_482_p3 <= bus_r(26 downto 26);
tmp_33_fu_490_p3 <= bus_r(27 downto 27);
tmp_34_fu_498_p3 <= bus_r(28 downto 28);
tmp_35_fu_506_p3 <= bus_r(29 downto 29);
tmp_36_fu_514_p3 <= bus_r(30 downto 30);
tmp_7_fu_282_p3 <= bus_r(1 downto 1);
tmp_8_fu_290_p3 <= bus_r(2 downto 2);
tmp_9_fu_298_p3 <= bus_r(3 downto 3);
tmp_fu_278_p1 <= bus_r(1 - 1 downto 0);
end behav;
| lgpl-3.0 | 69853ab76edfbe93d9a3f9c1be1dc1dc | 0.616825 | 2.1275 | false | false | false | false |
Given-Jiang/Binarization | Binarization_dspbuilder/hdl/alt_dspbuilder_decoder_GNJCA5JWVP.vhd | 1 | 947 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_decoder_GNJCA5JWVP is
generic ( decode : string := "000000000000000000001111";
pipeline : natural := 1;
width : natural := 24);
port(
aclr : in std_logic;
clock : in std_logic;
data : in std_logic_vector((width)-1 downto 0);
dec : out std_logic;
ena : in std_logic;
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_decoder_GNJCA5JWVP is
Begin
-- DSP Builder Block - Simulink Block "Decoder"
Decoderi : alt_dspbuilder_sdecoderaltr Generic map (
width => 24,
decode => "000000000000000000001111",
pipeline => 1)
port map (
aclr => aclr,
user_aclr => '0',
sclr => sclr,
clock => clock,
data => data,
dec => dec);
end architecture; | mit | 43ed5b9eb08d0154926961525461f482 | 0.670539 | 3.035256 | false | false | false | false |
Given-Jiang/Binarization | Binarization_dspbuilder/reports/Binarization/Binarization_example.vhd | 1 | 2,455 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity Binarization_example is
port(
Avalon_ST_Sink_data : in STD_LOGIC_VECTOR(23 downto 0);
Avalon_ST_Sink_endofpacket : in STD_LOGIC;
Avalon_MM_Slave_address : in STD_LOGIC_VECTOR(1 downto 0);
Avalon_MM_Slave_writedata : in STD_LOGIC_VECTOR(31 downto 0);
Avalon_ST_Source_valid : out STD_LOGIC;
Avalon_ST_Sink_valid : in STD_LOGIC;
Clock : in STD_LOGIC;
Avalon_ST_Source_endofpacket : out STD_LOGIC;
Avalon_ST_Source_startofpacket : out STD_LOGIC;
aclr : in STD_LOGIC;
Avalon_MM_Slave_write : in STD_LOGIC;
Avalon_ST_Source_ready : in STD_LOGIC;
Avalon_ST_Sink_ready : out STD_LOGIC;
Avalon_ST_Sink_startofpacket : in STD_LOGIC;
Avalon_ST_Source_data : out STD_LOGIC_VECTOR(23 downto 0));
end entity;
architecture rtl of Binarization_example is
component Binarization
port(
Avalon_ST_Sink_data : in STD_LOGIC_VECTOR(23 downto 0);
Avalon_ST_Sink_endofpacket : in STD_LOGIC;
Avalon_MM_Slave_address : in STD_LOGIC_VECTOR(1 downto 0);
Avalon_MM_Slave_writedata : in STD_LOGIC_VECTOR(31 downto 0);
Avalon_ST_Source_valid : out STD_LOGIC;
Avalon_ST_Sink_valid : in STD_LOGIC;
Clock : in STD_LOGIC;
Avalon_ST_Source_endofpacket : out STD_LOGIC;
Avalon_ST_Source_startofpacket : out STD_LOGIC;
aclr : in STD_LOGIC;
Avalon_MM_Slave_write : in STD_LOGIC;
Avalon_ST_Source_ready : in STD_LOGIC;
Avalon_ST_Sink_ready : out STD_LOGIC;
Avalon_ST_Sink_startofpacket : in STD_LOGIC;
Avalon_ST_Source_data : out STD_LOGIC_VECTOR(23 downto 0));
end component;
begin
Binarization_instance :
component Binarization
port map(
Avalon_ST_Sink_data => Avalon_ST_Sink_data,
Avalon_ST_Sink_endofpacket => Avalon_ST_Sink_endofpacket,
Avalon_MM_Slave_address => Avalon_MM_Slave_address,
Avalon_MM_Slave_writedata => Avalon_MM_Slave_writedata,
Avalon_ST_Source_valid => Avalon_ST_Source_valid,
Avalon_ST_Sink_valid => Avalon_ST_Sink_valid,
Clock => Clock,
Avalon_ST_Source_endofpacket => Avalon_ST_Source_endofpacket,
Avalon_ST_Source_startofpacket => Avalon_ST_Source_startofpacket,
aclr => aclr,
Avalon_MM_Slave_write => Avalon_MM_Slave_write,
Avalon_ST_Source_ready => Avalon_ST_Source_ready,
Avalon_ST_Sink_ready => Avalon_ST_Sink_ready,
Avalon_ST_Sink_startofpacket => Avalon_ST_Sink_startofpacket,
Avalon_ST_Source_data => Avalon_ST_Source_data);
end architecture rtl;
| mit | 433a0e3ad4bf005fd4fb99e93f105f14 | 0.719756 | 3.042131 | false | false | false | false |
jairov4/accel-oil | solution_kintex7/sim/vhdl/nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4.vhd | 1 | 2,896 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4_MAC4S_1 is
port (
clk: in std_logic;
ce: in std_logic;
a: in std_logic_vector(8 - 1 downto 0);
b: in std_logic_vector(6 - 1 downto 0);
p: out std_logic_vector(14 - 1 downto 0));
end entity;
architecture behav of nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4_MAC4S_1 is
signal tmp_product : std_logic_vector(14 - 1 downto 0);
signal a_i : std_logic_vector(8 - 1 downto 0);
signal b_i : std_logic_vector(6 - 1 downto 0);
signal p_tmp : std_logic_vector(14 - 1 downto 0);
signal a_reg : std_logic_vector(8 - 1 downto 0);
signal b_reg : std_logic_vector(6 - 1 downto 0);
attribute keep : string;
attribute keep of a_i : signal is "true";
attribute keep of b_i : signal is "true";
signal buff0 : std_logic_vector(14 - 1 downto 0);
signal buff1 : std_logic_vector(14 - 1 downto 0);
begin
a_i <= a;
b_i <= b;
p <= p_tmp;
p_tmp <= buff1;
tmp_product <= std_logic_vector(resize(unsigned(a_reg) * unsigned(b_reg), 14));
process(clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
a_reg <= a_i;
b_reg <= b_i;
buff0 <= tmp_product;
buff1 <= buff0;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4 is
component nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4_MAC4S_1 is
port (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4_MAC4S_1_U : component nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4_MAC4S_1
port map (
clk => clk,
ce => ce,
a => din0,
b => din1,
p => dout);
end architecture;
| lgpl-3.0 | d8928162835cae3afceb6a8dc7f262e9 | 0.559047 | 3.182418 | false | false | false | false |
grwlf/vsim | vhdl/IEEE/synopsys/std_logic_unsigned.vhdl | 13 | 12,038 | --------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Package name: STD_LOGIC_UNSIGNED --
-- --
-- --
-- Date: 09/11/92 KN --
-- 10/08/92 AMT --
-- --
-- Purpose: --
-- A set of unsigned arithemtic, conversion, --
-- and comparision functions for STD_LOGIC_VECTOR. --
-- --
-- Note: comparision of same length discrete arrays is defined --
-- by the LRM. This package will "overload" those --
-- definitions --
-- --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package STD_LOGIC_UNSIGNED is
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER;
-- remove this since it is already in std_logic_arith
-- function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR;
end STD_LOGIC_UNSIGNED;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package body STD_LOGIC_UNSIGNED is
function maximum(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := UNSIGNED(L) + UNSIGNED(R);-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) + R;-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + UNSIGNED(R);-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) + R;-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + UNSIGNED(R);-- pragma label plus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := UNSIGNED(L) - UNSIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) - R; -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - UNSIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) - R;
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - UNSIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := + UNSIGNED(L);
return std_logic_vector(result);
end;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR ((L'length+R'length-1) downto 0);
begin
result := UNSIGNED(L) * UNSIGNED(R); -- pragma label mult
return std_logic_vector(result);
end;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
constant length: INTEGER := maximum(L'length, R'length);
begin
return UNSIGNED(L) < UNSIGNED(R); -- pragma label lt
end;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
begin
return UNSIGNED(L) < R; -- pragma label lt
end;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
begin
return L < UNSIGNED(R); -- pragma label lt
end;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return UNSIGNED(L) <= UNSIGNED(R); -- pragma label leq
end;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
begin
return UNSIGNED(L) <= R; -- pragma label leq
end;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return L <= UNSIGNED(R); -- pragma label leq
end;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return UNSIGNED(L) > UNSIGNED(R); -- pragma label gt
end;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
begin
return UNSIGNED(L) > R; -- pragma label gt
end;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return L > UNSIGNED(R); -- pragma label gt
end;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return UNSIGNED(L) >= UNSIGNED(R); -- pragma label geq
end;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
begin
return UNSIGNED(L) >= R; -- pragma label geq
end;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return L >= UNSIGNED(R); -- pragma label geq
end;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) = UNSIGNED(R);
end;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return UNSIGNED(L) = R;
end;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L = UNSIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) /= UNSIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return UNSIGNED(L) /= R;
end;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L /= UNSIGNED(R);
end;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER is
variable result : UNSIGNED(ARG'range);
begin
result := UNSIGNED(ARG);
return CONV_INTEGER(result);
end;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHL(UNSIGNED(ARG),UNSIGNED(COUNT)));
end;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHR(UNSIGNED(ARG),UNSIGNED(COUNT)));
end;
-- remove this since it is already in std_logic_arith
--function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR is
--variable result1 : UNSIGNED (SIZE-1 downto 0);
--variable result2 : STD_LOGIC_VECTOR (SIZE-1 downto 0);
--begin
--result1 := CONV_UNSIGNED(ARG,SIZE);
--return std_logic_vector(result1);
--end;
end STD_LOGIC_UNSIGNED;
| gpl-3.0 | 0dd712fd51797228d511078e85198161 | 0.595199 | 3.837424 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00640.vhd | 1 | 106,540 | -- NEED RESULT: ARCH00640.P1: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00640.P2: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00640.P3: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00640.P4: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00640.P5: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00640.P6: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00640.P7: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00640.P8: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00640.P9: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00640.P10: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00640.P11: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00640.P12: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00640.P13: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00640.P14: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00640.P15: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00640.P16: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00640.P17: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00640: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00640: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00640: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00640: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00640: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00640: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00640: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00640: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00640: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00640: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00640: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00640: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00640: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00640: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00640: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00640: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00640: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: P17: Inertial transactions entirely completed failed
-- NEED RESULT: P16: Inertial transactions entirely completed failed
-- NEED RESULT: P15: Inertial transactions entirely completed failed
-- NEED RESULT: P14: Inertial transactions entirely completed failed
-- NEED RESULT: P13: Inertial transactions entirely completed failed
-- NEED RESULT: P12: Inertial transactions entirely completed failed
-- NEED RESULT: P11: Inertial transactions entirely completed failed
-- NEED RESULT: P10: Inertial transactions entirely completed failed
-- NEED RESULT: P9: Inertial transactions entirely completed failed
-- NEED RESULT: P8: Inertial transactions entirely completed failed
-- NEED RESULT: P7: Inertial transactions entirely completed failed
-- NEED RESULT: P6: Inertial transactions entirely completed failed
-- NEED RESULT: P5: Inertial transactions entirely completed failed
-- NEED RESULT: P4: Inertial transactions entirely completed failed
-- NEED RESULT: P3: Inertial transactions entirely completed failed
-- NEED RESULT: P2: Inertial transactions entirely completed failed
-- NEED RESULT: P1: Inertial transactions entirely completed failed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00640
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (6)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00640)
-- ENT00640_Test_Bench(ARCH00640_Test_Bench)
--
-- REVISION HISTORY:
--
-- 25-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00640 of E00000 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_boolean_vector : chk_sig_type := -1 ;
signal chk_st_bit_vector : chk_sig_type := -1 ;
signal chk_st_severity_level_vector : chk_sig_type := -1 ;
signal chk_st_string : chk_sig_type := -1 ;
signal chk_st_enum1_vector : chk_sig_type := -1 ;
signal chk_st_integer_vector : chk_sig_type := -1 ;
signal chk_st_int1_vector : chk_sig_type := -1 ;
signal chk_st_time_vector : chk_sig_type := -1 ;
signal chk_st_phys1_vector : chk_sig_type := -1 ;
signal chk_st_real_vector : chk_sig_type := -1 ;
signal chk_st_real1_vector : chk_sig_type := -1 ;
signal chk_st_rec1_vector : chk_sig_type := -1 ;
signal chk_st_rec2_vector : chk_sig_type := -1 ;
signal chk_st_rec3_vector : chk_sig_type := -1 ;
signal chk_st_arr1_vector : chk_sig_type := -1 ;
signal chk_st_arr2_vector : chk_sig_type := -1 ;
signal chk_st_arr3_vector : chk_sig_type := -1 ;
--
signal s_st_boolean_vector : st_boolean_vector
:= c_st_boolean_vector_1 ;
signal s_st_bit_vector : st_bit_vector
:= c_st_bit_vector_1 ;
signal s_st_severity_level_vector : st_severity_level_vector
:= c_st_severity_level_vector_1 ;
signal s_st_string : st_string
:= c_st_string_1 ;
signal s_st_enum1_vector : st_enum1_vector
:= c_st_enum1_vector_1 ;
signal s_st_integer_vector : st_integer_vector
:= c_st_integer_vector_1 ;
signal s_st_int1_vector : st_int1_vector
:= c_st_int1_vector_1 ;
signal s_st_time_vector : st_time_vector
:= c_st_time_vector_1 ;
signal s_st_phys1_vector : st_phys1_vector
:= c_st_phys1_vector_1 ;
signal s_st_real_vector : st_real_vector
:= c_st_real_vector_1 ;
signal s_st_real1_vector : st_real1_vector
:= c_st_real1_vector_1 ;
signal s_st_rec1_vector : st_rec1_vector
:= c_st_rec1_vector_1 ;
signal s_st_rec2_vector : st_rec2_vector
:= c_st_rec2_vector_1 ;
signal s_st_rec3_vector : st_rec3_vector
:= c_st_rec3_vector_1 ;
signal s_st_arr1_vector : st_arr1_vector
:= c_st_arr1_vector_1 ;
signal s_st_arr2_vector : st_arr2_vector
:= c_st_arr2_vector_1 ;
signal s_st_arr3_vector : st_arr3_vector
:= c_st_arr3_vector_1 ;
--
begin
P1 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> (s_st_boolean_vector (lowb+1),
s_st_boolean_vector (lowb+2),
s_st_boolean_vector (lowb+3)) <=
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_boolean_vector (lowb+1),
s_st_boolean_vector (lowb+2),
s_st_boolean_vector (lowb+3)) <=
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_boolean_vector (lowb+1),
s_st_boolean_vector (lowb+2),
s_st_boolean_vector (lowb+3)) <=
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_boolean_vector (lowb+1),
s_st_boolean_vector (lowb+2),
s_st_boolean_vector (lowb+3)) <= transport
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_boolean_vector (lowb+1),
s_st_boolean_vector (lowb+2),
s_st_boolean_vector (lowb+3)) <=
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_boolean_vector (lowb+1),
s_st_boolean_vector (lowb+2),
s_st_boolean_vector (lowb+3)) <=
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00640" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_boolean_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_boolean_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_boolean_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_st_boolean_vector = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P2 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> (s_st_bit_vector (lowb+1),
s_st_bit_vector (lowb+2),
s_st_bit_vector (lowb+3)) <=
c_st_bit_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640.P2" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_bit_vector (lowb+1),
s_st_bit_vector (lowb+2),
s_st_bit_vector (lowb+3)) <=
c_st_bit_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_bit_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_bit_vector (lowb+1),
s_st_bit_vector (lowb+2),
s_st_bit_vector (lowb+3)) <=
c_st_bit_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_bit_vector (lowb+1),
s_st_bit_vector (lowb+2),
s_st_bit_vector (lowb+3)) <= transport
c_st_bit_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_bit_vector (lowb+1),
s_st_bit_vector (lowb+2),
s_st_bit_vector (lowb+3)) <=
c_st_bit_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_bit_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_bit_vector (lowb+1),
s_st_bit_vector (lowb+2),
s_st_bit_vector (lowb+3)) <=
c_st_bit_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00640" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_bit_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_bit_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P2 ;
--
PGEN_CHKP_2 :
process ( chk_st_bit_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions entirely completed",
chk_st_bit_vector = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P3 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> (s_st_severity_level_vector (lowb+1),
s_st_severity_level_vector (lowb+2),
s_st_severity_level_vector (lowb+3)) <=
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640.P3" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_severity_level_vector (lowb+1),
s_st_severity_level_vector (lowb+2),
s_st_severity_level_vector (lowb+3)) <=
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_severity_level_vector (lowb+1),
s_st_severity_level_vector (lowb+2),
s_st_severity_level_vector (lowb+3)) <=
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_severity_level_vector (lowb+1),
s_st_severity_level_vector (lowb+2),
s_st_severity_level_vector (lowb+3)) <= transport
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_severity_level_vector (lowb+1),
s_st_severity_level_vector (lowb+2),
s_st_severity_level_vector (lowb+3)) <=
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_severity_level_vector (lowb+1),
s_st_severity_level_vector (lowb+2),
s_st_severity_level_vector (lowb+3)) <=
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00640" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_severity_level_vector <= transport counter after (1 us - savtime
) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_severity_level_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P3 ;
--
PGEN_CHKP_3 :
process ( chk_st_severity_level_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions entirely completed",
chk_st_severity_level_vector = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P4 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> (s_st_string (lowb+1),
s_st_string (lowb+2),
s_st_string (lowb+3)) <=
c_st_string_2 (lowb+1 to lowb+3) after 10 ns,
c_st_string_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640.P4" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_string (lowb+1),
s_st_string (lowb+2),
s_st_string (lowb+3)) <=
c_st_string_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_string_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_string_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_string_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_string (lowb+1),
s_st_string (lowb+2),
s_st_string (lowb+3)) <=
c_st_string_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_string (lowb+1),
s_st_string (lowb+2),
s_st_string (lowb+3)) <= transport
c_st_string_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_string (lowb+1),
s_st_string (lowb+2),
s_st_string (lowb+3)) <=
c_st_string_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_string_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_string_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_string_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_string (lowb+1),
s_st_string (lowb+2),
s_st_string (lowb+3)) <=
c_st_string_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00640" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_string <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_string'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P4 ;
--
PGEN_CHKP_4 :
process ( chk_st_string )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Inertial transactions entirely completed",
chk_st_string = 8 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
P5 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> (s_st_enum1_vector (lowb+1),
s_st_enum1_vector (lowb+2),
s_st_enum1_vector (lowb+3)) <=
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640.P5" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_enum1_vector (lowb+1),
s_st_enum1_vector (lowb+2),
s_st_enum1_vector (lowb+3)) <=
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_enum1_vector (lowb+1),
s_st_enum1_vector (lowb+2),
s_st_enum1_vector (lowb+3)) <=
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_enum1_vector (lowb+1),
s_st_enum1_vector (lowb+2),
s_st_enum1_vector (lowb+3)) <= transport
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_enum1_vector (lowb+1),
s_st_enum1_vector (lowb+2),
s_st_enum1_vector (lowb+3)) <=
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_enum1_vector (lowb+1),
s_st_enum1_vector (lowb+2),
s_st_enum1_vector (lowb+3)) <=
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00640" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_enum1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_enum1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P5 ;
--
PGEN_CHKP_5 :
process ( chk_st_enum1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Inertial transactions entirely completed",
chk_st_enum1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
P6 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> (s_st_integer_vector (lowb+1),
s_st_integer_vector (lowb+2),
s_st_integer_vector (lowb+3)) <=
c_st_integer_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640.P6" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_integer_vector (lowb+1),
s_st_integer_vector (lowb+2),
s_st_integer_vector (lowb+3)) <=
c_st_integer_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_integer_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_integer_vector (lowb+1),
s_st_integer_vector (lowb+2),
s_st_integer_vector (lowb+3)) <=
c_st_integer_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_integer_vector (lowb+1),
s_st_integer_vector (lowb+2),
s_st_integer_vector (lowb+3)) <= transport
c_st_integer_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_integer_vector (lowb+1),
s_st_integer_vector (lowb+2),
s_st_integer_vector (lowb+3)) <=
c_st_integer_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_integer_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_integer_vector (lowb+1),
s_st_integer_vector (lowb+2),
s_st_integer_vector (lowb+3)) <=
c_st_integer_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00640" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_integer_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_integer_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P6 ;
--
PGEN_CHKP_6 :
process ( chk_st_integer_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Inertial transactions entirely completed",
chk_st_integer_vector = 8 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
P7 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> (s_st_int1_vector (lowb+1),
s_st_int1_vector (lowb+2),
s_st_int1_vector (lowb+3)) <=
c_st_int1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640.P7" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_int1_vector (lowb+1),
s_st_int1_vector (lowb+2),
s_st_int1_vector (lowb+3)) <=
c_st_int1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_int1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_int1_vector (lowb+1),
s_st_int1_vector (lowb+2),
s_st_int1_vector (lowb+3)) <=
c_st_int1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_int1_vector (lowb+1),
s_st_int1_vector (lowb+2),
s_st_int1_vector (lowb+3)) <= transport
c_st_int1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_int1_vector (lowb+1),
s_st_int1_vector (lowb+2),
s_st_int1_vector (lowb+3)) <=
c_st_int1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_int1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_int1_vector (lowb+1),
s_st_int1_vector (lowb+2),
s_st_int1_vector (lowb+3)) <=
c_st_int1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00640" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_int1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_int1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P7 ;
--
PGEN_CHKP_7 :
process ( chk_st_int1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Inertial transactions entirely completed",
chk_st_int1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
P8 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> (s_st_time_vector (lowb+1),
s_st_time_vector (lowb+2),
s_st_time_vector (lowb+3)) <=
c_st_time_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_time_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640.P8" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_time_vector (lowb+1),
s_st_time_vector (lowb+2),
s_st_time_vector (lowb+3)) <=
c_st_time_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_time_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_time_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_time_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_time_vector (lowb+1),
s_st_time_vector (lowb+2),
s_st_time_vector (lowb+3)) <=
c_st_time_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_time_vector (lowb+1),
s_st_time_vector (lowb+2),
s_st_time_vector (lowb+3)) <= transport
c_st_time_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_time_vector (lowb+1),
s_st_time_vector (lowb+2),
s_st_time_vector (lowb+3)) <=
c_st_time_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_time_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_time_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_time_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_time_vector (lowb+1),
s_st_time_vector (lowb+2),
s_st_time_vector (lowb+3)) <=
c_st_time_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00640" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_time_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_time_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P8 ;
--
PGEN_CHKP_8 :
process ( chk_st_time_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Inertial transactions entirely completed",
chk_st_time_vector = 8 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
P9 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> (s_st_phys1_vector (lowb+1),
s_st_phys1_vector (lowb+2),
s_st_phys1_vector (lowb+3)) <=
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640.P9" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_phys1_vector (lowb+1),
s_st_phys1_vector (lowb+2),
s_st_phys1_vector (lowb+3)) <=
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_phys1_vector (lowb+1),
s_st_phys1_vector (lowb+2),
s_st_phys1_vector (lowb+3)) <=
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_phys1_vector (lowb+1),
s_st_phys1_vector (lowb+2),
s_st_phys1_vector (lowb+3)) <= transport
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_phys1_vector (lowb+1),
s_st_phys1_vector (lowb+2),
s_st_phys1_vector (lowb+3)) <=
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_phys1_vector (lowb+1),
s_st_phys1_vector (lowb+2),
s_st_phys1_vector (lowb+3)) <=
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00640" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_phys1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_phys1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P9 ;
--
PGEN_CHKP_9 :
process ( chk_st_phys1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Inertial transactions entirely completed",
chk_st_phys1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
P10 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> (s_st_real_vector (lowb+1),
s_st_real_vector (lowb+2),
s_st_real_vector (lowb+3)) <=
c_st_real_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_real_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640.P10" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_real_vector (lowb+1),
s_st_real_vector (lowb+2),
s_st_real_vector (lowb+3)) <=
c_st_real_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_real_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_real_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_real_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_real_vector (lowb+1),
s_st_real_vector (lowb+2),
s_st_real_vector (lowb+3)) <=
c_st_real_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_real_vector (lowb+1),
s_st_real_vector (lowb+2),
s_st_real_vector (lowb+3)) <= transport
c_st_real_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_real_vector (lowb+1),
s_st_real_vector (lowb+2),
s_st_real_vector (lowb+3)) <=
c_st_real_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_real_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_real_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_real_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_real_vector (lowb+1),
s_st_real_vector (lowb+2),
s_st_real_vector (lowb+3)) <=
c_st_real_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00640" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_real_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_real_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P10 ;
--
PGEN_CHKP_10 :
process ( chk_st_real_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Inertial transactions entirely completed",
chk_st_real_vector = 8 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
P11 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> (s_st_real1_vector (lowb+1),
s_st_real1_vector (lowb+2),
s_st_real1_vector (lowb+3)) <=
c_st_real1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640.P11" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_real1_vector (lowb+1),
s_st_real1_vector (lowb+2),
s_st_real1_vector (lowb+3)) <=
c_st_real1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_real1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_real1_vector (lowb+1),
s_st_real1_vector (lowb+2),
s_st_real1_vector (lowb+3)) <=
c_st_real1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_real1_vector (lowb+1),
s_st_real1_vector (lowb+2),
s_st_real1_vector (lowb+3)) <= transport
c_st_real1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_real1_vector (lowb+1),
s_st_real1_vector (lowb+2),
s_st_real1_vector (lowb+3)) <=
c_st_real1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_real1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_real1_vector (lowb+1),
s_st_real1_vector (lowb+2),
s_st_real1_vector (lowb+3)) <=
c_st_real1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00640" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_real1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_real1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P11 ;
--
PGEN_CHKP_11 :
process ( chk_st_real1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P11" ,
"Inertial transactions entirely completed",
chk_st_real1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_11 ;
--
P12 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> (s_st_rec1_vector (lowb+1),
s_st_rec1_vector (lowb+2),
s_st_rec1_vector (lowb+3)) <=
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640.P12" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_rec1_vector (lowb+1),
s_st_rec1_vector (lowb+2),
s_st_rec1_vector (lowb+3)) <=
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_rec1_vector (lowb+1),
s_st_rec1_vector (lowb+2),
s_st_rec1_vector (lowb+3)) <=
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_rec1_vector (lowb+1),
s_st_rec1_vector (lowb+2),
s_st_rec1_vector (lowb+3)) <= transport
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_rec1_vector (lowb+1),
s_st_rec1_vector (lowb+2),
s_st_rec1_vector (lowb+3)) <=
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_rec1_vector (lowb+1),
s_st_rec1_vector (lowb+2),
s_st_rec1_vector (lowb+3)) <=
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00640" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_rec1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P12 ;
--
PGEN_CHKP_12 :
process ( chk_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P12" ,
"Inertial transactions entirely completed",
chk_st_rec1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_12 ;
--
P13 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> (s_st_rec2_vector (lowb+1),
s_st_rec2_vector (lowb+2),
s_st_rec2_vector (lowb+3)) <=
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640.P13" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_rec2_vector (lowb+1),
s_st_rec2_vector (lowb+2),
s_st_rec2_vector (lowb+3)) <=
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_rec2_vector (lowb+1),
s_st_rec2_vector (lowb+2),
s_st_rec2_vector (lowb+3)) <=
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_rec2_vector (lowb+1),
s_st_rec2_vector (lowb+2),
s_st_rec2_vector (lowb+3)) <= transport
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_rec2_vector (lowb+1),
s_st_rec2_vector (lowb+2),
s_st_rec2_vector (lowb+3)) <=
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_rec2_vector (lowb+1),
s_st_rec2_vector (lowb+2),
s_st_rec2_vector (lowb+3)) <=
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00640" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_rec2_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P13 ;
--
PGEN_CHKP_13 :
process ( chk_st_rec2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P13" ,
"Inertial transactions entirely completed",
chk_st_rec2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_13 ;
--
P14 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> (s_st_rec3_vector (lowb+1),
s_st_rec3_vector (lowb+2),
s_st_rec3_vector (lowb+3)) <=
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640.P14" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_rec3_vector (lowb+1),
s_st_rec3_vector (lowb+2),
s_st_rec3_vector (lowb+3)) <=
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_rec3_vector (lowb+1),
s_st_rec3_vector (lowb+2),
s_st_rec3_vector (lowb+3)) <=
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_rec3_vector (lowb+1),
s_st_rec3_vector (lowb+2),
s_st_rec3_vector (lowb+3)) <= transport
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_rec3_vector (lowb+1),
s_st_rec3_vector (lowb+2),
s_st_rec3_vector (lowb+3)) <=
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_rec3_vector (lowb+1),
s_st_rec3_vector (lowb+2),
s_st_rec3_vector (lowb+3)) <=
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00640" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_rec3_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P14 ;
--
PGEN_CHKP_14 :
process ( chk_st_rec3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P14" ,
"Inertial transactions entirely completed",
chk_st_rec3_vector = 8 ) ;
end if ;
end process PGEN_CHKP_14 ;
--
P15 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> (s_st_arr1_vector (lowb+1),
s_st_arr1_vector (lowb+2),
s_st_arr1_vector (lowb+3)) <=
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640.P15" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_arr1_vector (lowb+1),
s_st_arr1_vector (lowb+2),
s_st_arr1_vector (lowb+3)) <=
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_arr1_vector (lowb+1),
s_st_arr1_vector (lowb+2),
s_st_arr1_vector (lowb+3)) <=
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_arr1_vector (lowb+1),
s_st_arr1_vector (lowb+2),
s_st_arr1_vector (lowb+3)) <= transport
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_arr1_vector (lowb+1),
s_st_arr1_vector (lowb+2),
s_st_arr1_vector (lowb+3)) <=
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_arr1_vector (lowb+1),
s_st_arr1_vector (lowb+2),
s_st_arr1_vector (lowb+3)) <=
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00640" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_arr1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P15 ;
--
PGEN_CHKP_15 :
process ( chk_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P15" ,
"Inertial transactions entirely completed",
chk_st_arr1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_15 ;
--
P16 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> (s_st_arr2_vector (lowb+1),
s_st_arr2_vector (lowb+2),
s_st_arr2_vector (lowb+3)) <=
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640.P16" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_arr2_vector (lowb+1),
s_st_arr2_vector (lowb+2),
s_st_arr2_vector (lowb+3)) <=
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_arr2_vector (lowb+1),
s_st_arr2_vector (lowb+2),
s_st_arr2_vector (lowb+3)) <=
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_arr2_vector (lowb+1),
s_st_arr2_vector (lowb+2),
s_st_arr2_vector (lowb+3)) <= transport
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_arr2_vector (lowb+1),
s_st_arr2_vector (lowb+2),
s_st_arr2_vector (lowb+3)) <=
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_arr2_vector (lowb+1),
s_st_arr2_vector (lowb+2),
s_st_arr2_vector (lowb+3)) <=
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00640" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_arr2_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P16 ;
--
PGEN_CHKP_16 :
process ( chk_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P16" ,
"Inertial transactions entirely completed",
chk_st_arr2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_16 ;
--
P17 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> (s_st_arr3_vector (lowb+1),
s_st_arr3_vector (lowb+2),
s_st_arr3_vector (lowb+3)) <=
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640.P17" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_arr3_vector (lowb+1),
s_st_arr3_vector (lowb+2),
s_st_arr3_vector (lowb+3)) <=
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_arr3_vector (lowb+1),
s_st_arr3_vector (lowb+2),
s_st_arr3_vector (lowb+3)) <=
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_arr3_vector (lowb+1),
s_st_arr3_vector (lowb+2),
s_st_arr3_vector (lowb+3)) <= transport
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_arr3_vector (lowb+1),
s_st_arr3_vector (lowb+2),
s_st_arr3_vector (lowb+3)) <=
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_arr3_vector (lowb+1),
s_st_arr3_vector (lowb+2),
s_st_arr3_vector (lowb+3)) <=
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00640" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00640" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_arr3_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P17 ;
--
PGEN_CHKP_17 :
process ( chk_st_arr3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P17" ,
"Inertial transactions entirely completed",
chk_st_arr3_vector = 8 ) ;
end if ;
end process PGEN_CHKP_17 ;
--
--
end ARCH00640 ;
--
entity ENT00640_Test_Bench is
end ENT00640_Test_Bench ;
--
architecture ARCH00640_Test_Bench of ENT00640_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00640 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00640_Test_Bench ;
| gpl-3.0 | 27305c5d1a02ec6b5d37d9f312c33d0a | 0.463976 | 3.625413 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00109.vhd | 1 | 13,436 | -- NEED RESULT: ARCH00109.P1: Multi transport transactions occurred on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00109.P2: Multi transport transactions occurred on signal asg with selected name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00109.P3: Multi transport transactions occurred on signal asg with selected name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00109: One transport transaction occurred on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00109: Old transactions were removed on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00109: One transport transaction occurred on signal asg with selected name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00109: Old transactions were removed on signal asg with selected name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00109: One transport transaction occurred on signal asg with selected name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00109: Old transactions were removed on signal asg with selected name prefixed by an indexed name on LHS failed
-- NEED RESULT: P3: Transport transactions entirely completed passed
-- NEED RESULT: P2: Transport transactions entirely completed passed
-- NEED RESULT: P1: Transport transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00109
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (2)
-- 8.3 (3)
-- 8.3 (5)
-- 8.3.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00109(ARCH00109)
-- ENT00109_Test_Bench(ARCH00109_Test_Bench)
--
-- REVISION HISTORY:
--
-- 07-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00109 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec1_vector : chk_sig_type := -1 ;
signal chk_st_rec2_vector : chk_sig_type := -1 ;
signal chk_st_rec3_vector : chk_sig_type := -1 ;
--
procedure Proc1 (
signal s_st_rec1_vector : inout st_rec1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec1_vector(lowb).f2 <= transport
c_st_rec1_vector_2(highb).f2 after 10 ns,
c_st_rec1_vector_1(highb).f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_1(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00109.P1" ,
"Multi transport transactions occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
s_st_rec1_vector(lowb).f2 <= transport
c_st_rec1_vector_2(highb).f2 after 10 ns ,
c_st_rec1_vector_1(highb).f2 after 20 ns ,
c_st_rec1_vector_2(highb).f2 after 30 ns ,
c_st_rec1_vector_1(highb).f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec1_vector(lowb).f2 <= transport
c_st_rec1_vector_1(highb).f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_1(highb).f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00109" ,
"One transport transaction occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
test_report ( "ARCH00109" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00109" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
procedure Proc2 (
signal s_st_rec2_vector : inout st_rec2_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec2_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec2_vector(lowb).f2 <= transport
c_st_rec2_vector_2(highb).f2 after 10 ns,
c_st_rec2_vector_1(highb).f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_1(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00109.P2" ,
"Multi transport transactions occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
s_st_rec2_vector(lowb).f2 <= transport
c_st_rec2_vector_2(highb).f2 after 10 ns ,
c_st_rec2_vector_1(highb).f2 after 20 ns ,
c_st_rec2_vector_2(highb).f2 after 30 ns ,
c_st_rec2_vector_1(highb).f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec2_vector(lowb).f2 <= transport
c_st_rec2_vector_1(highb).f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_1(highb).f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00109" ,
"One transport transaction occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
test_report ( "ARCH00109" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00109" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc2 ;
--
procedure Proc3 (
signal s_st_rec3_vector : inout st_rec3_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec3_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec3_vector(lowb).f2 <= transport
c_st_rec3_vector_2(highb).f2 after 10 ns,
c_st_rec3_vector_1(highb).f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_1(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00109.P3" ,
"Multi transport transactions occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
s_st_rec3_vector(lowb).f2 <= transport
c_st_rec3_vector_2(highb).f2 after 10 ns ,
c_st_rec3_vector_1(highb).f2 after 20 ns ,
c_st_rec3_vector_2(highb).f2 after 30 ns ,
c_st_rec3_vector_1(highb).f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3_vector(lowb).f2 <= transport
c_st_rec3_vector_1(highb).f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_1(highb).f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00109" ,
"One transport transaction occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
test_report ( "ARCH00109" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00109" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc3 ;
--
--
end ENT00109 ;
--
architecture ARCH00109 of ENT00109 is
signal s_st_rec1_vector : st_rec1_vector
:= c_st_rec1_vector_1 ;
signal s_st_rec2_vector : st_rec2_vector
:= c_st_rec2_vector_1 ;
signal s_st_rec3_vector : st_rec3_vector
:= c_st_rec3_vector_1 ;
--
begin
PGEN_CHKP_1 :
process ( chk_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions entirely completed",
chk_st_rec1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P1 :
process ( s_st_rec1_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc1 (
s_st_rec1_vector,
counter,
correct,
savtime,
chk_st_rec1_vector
) ;
end process P1 ;
--
PGEN_CHKP_2 :
process ( chk_st_rec2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions entirely completed",
chk_st_rec2_vector = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P2 :
process ( s_st_rec2_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc2 (
s_st_rec2_vector,
counter,
correct,
savtime,
chk_st_rec2_vector
) ;
end process P2 ;
--
PGEN_CHKP_3 :
process ( chk_st_rec3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions entirely completed",
chk_st_rec3_vector = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P3 :
process ( s_st_rec3_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc3 (
s_st_rec3_vector,
counter,
correct,
savtime,
chk_st_rec3_vector
) ;
end process P3 ;
--
--
end ARCH00109 ;
--
entity ENT00109_Test_Bench is
end ENT00109_Test_Bench ;
--
architecture ARCH00109_Test_Bench of ENT00109_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00109 ( ARCH00109 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00109_Test_Bench ;
| gpl-3.0 | 73de2a053a913214600fb9aef3f238dd | 0.530813 | 3.740535 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00447.vhd | 1 | 14,251 | -- NEED RESULT: ARCH00447.Chk_s3: In absence of primaries that denote signals, an equivalent process statement for the concurrent sig asg has a wait statement with no sensitivity clause except for maybe the signal 'GUARD' passed
-- NEED RESULT: ARCH00447.Chk_s2: In absence of primaries that denote signals, an equivalent process statement for the concurrent sig asg has a wait statement with no sensitivity clause except for maybe the signal 'GUARD' passed
-- NEED RESULT: ARCH00447.Chk_s1: In absence of primaries that denote signals, an equivalent process statement for the concurrent sig asg has a wait statement with no sensitivity clause except for maybe the signal 'GUARD' passed
-- NEED RESULT: ARCH00447.Chk_s1: In absence of primaries that denote signals, an equivalent process statement for the concurrent sig asg has a wait statement with no sensitivity clause except for maybe the signal 'GUARD' passed
-- NEED RESULT: ARCH00447.Chk_s2: In absence of primaries that denote signals, an equivalent process statement for the concurrent sig asg has a wait statement with no sensitivity clause except for maybe the signal 'GUARD' passed
-- NEED RESULT: ARCH00447.Chk_s3: In absence of primaries that denote signals, an equivalent process statement for the concurrent sig asg has a wait statement with no sensitivity clause except for maybe the signal 'GUARD' passed
-- NEED RESULT: ARCH00447.Chk_gs3: In absence of primaries that denote signals, an equivalent process statement for the concurrent sig asg has a wait statement with no sensitivity clause except for maybe the signal 'GUARD' passed
-- NEED RESULT: ARCH00447.Chk_gs2: In absence of primaries that denote signals, an equivalent process statement for the concurrent sig asg has a wait statement with no sensitivity clause except for maybe the signal 'GUARD' passed
-- NEED RESULT: ARCH00447.Chk_gs1: In absence of primaries that denote signals, an equivalent process statement for the concurrent sig asg has a wait statement with no sensitivity clause except for maybe the signal 'GUARD' passed
-- NEED RESULT: ARCH00447.Chk_gs1: In absence of primaries that denote signals, an equivalent process statement for the concurrent sig asg has a wait statement with no sensitivity clause except for maybe the signal 'GUARD' passed
-- NEED RESULT: ARCH00447.Chk_gs2: In absence of primaries that denote signals, an equivalent process statement for the concurrent sig asg has a wait statement with no sensitivity clause except for maybe the signal 'GUARD' passed
-- NEED RESULT: ARCH00447.Chk_gs3: In absence of primaries that denote signals, an equivalent process statement for the concurrent sig asg has a wait statement with no sensitivity clause except for maybe the signal 'GUARD' passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00447
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (8)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00447)
-- ENT00447_Test_Bench(ARCH00447_Test_Bench)
--
-- REVISION HISTORY:
--
-- 4-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00447 of E00000 is
signal Control : boolean := true ;
signal s1, s2, s3 : boolean := false ;
signal Guard, gs1, gs2, gs3 : boolean := false ;
constant C : boolean := false ;
begin
B1 :
block ( Control ) -- Implicit Guard Signal
begin
s1 <= guarded transport True after 5 ns, False after 10 ns ;
s2 <= guarded transport False after 5 ns, True after 10 ns when C else
True after 5 ns, False after 10 ns ;
with C select
s3 <= guarded transport False after 5 ns, True after 10 ns when True,
True after 5 ns, False after 10 ns when others ;
end block B1 ;
Chk_s1 :
process ( s1 )
variable SavTime : Time ;
variable counter : integer := 0 ;
begin
case counter is
when 0 =>
SavTime := Std.Standard.Now ;
when 1 =>
test_report ( "ARCH00447.Chk_s1" ,
"In absence of primaries that denote signals, an "&
"equivalent process statement for the concurrent "&
"sig asg has a wait statement with no sensitivity "&
"clause except for maybe the signal 'GUARD'" ,
s1 and ((SavTime+5 ns) = Std.Standard.Now) ) ;
when 2 =>
test_report ( "ARCH00447.Chk_s1" ,
"In absence of primaries that denote signals, an "&
"equivalent process statement for the concurrent "&
"sig asg has a wait statement with no sensitivity "&
"clause except for maybe the signal 'GUARD'" ,
(Not s1) and ((SavTime+10 ns) = Std.Standard.Now) ) ;
when others =>
test_report ( "ARCH00447.Chk_s1" ,
"In absence of primaries that denote signals, an "&
"equivalent process statement for the concurrent "&
"sig asg has a wait statement with no sensitivity "&
"clause except for maybe the signal 'GUARD'" ,
False ) ;
end case ;
counter := counter + 1 ;
end process Chk_s1 ;
Chk_s2 :
process ( s2 )
variable SavTime : Time ;
variable counter : integer := 0 ;
begin
case counter is
when 0 =>
SavTime := Std.Standard.Now ;
when 1 =>
test_report ( "ARCH00447.Chk_s2" ,
"In absence of primaries that denote signals, an "&
"equivalent process statement for the concurrent "&
"sig asg has a wait statement with no sensitivity "&
"clause except for maybe the signal 'GUARD'" ,
s2 and ((SavTime+5 ns) = Std.Standard.Now) ) ;
when 2 =>
test_report ( "ARCH00447.Chk_s2" ,
"In absence of primaries that denote signals, an "&
"equivalent process statement for the concurrent "&
"sig asg has a wait statement with no sensitivity "&
"clause except for maybe the signal 'GUARD'" ,
(Not s2) and ((SavTime+10 ns) = Std.Standard.Now) ) ;
when others =>
test_report ( "ARCH00447.Chk_s2" ,
"In absence of primaries that denote signals, an "&
"equivalent process statement for the concurrent "&
"sig asg has a wait statement with no sensitivity "&
"clause except for maybe the signal 'GUARD'" ,
False ) ;
end case ;
counter := counter + 1 ;
end process Chk_s2 ;
Chk_s3 :
process ( s3 )
variable SavTime : Time ;
variable counter : integer := 0 ;
begin
case counter is
when 0 =>
SavTime := Std.Standard.Now ;
when 1 =>
test_report ( "ARCH00447.Chk_s3" ,
"In absence of primaries that denote signals, an "&
"equivalent process statement for the concurrent "&
"sig asg has a wait statement with no sensitivity "&
"clause except for maybe the signal 'GUARD'" ,
s3 and ((SavTime+5 ns) = Std.Standard.Now) ) ;
when 2 =>
test_report ( "ARCH00447.Chk_s3" ,
"In absence of primaries that denote signals, an "&
"equivalent process statement for the concurrent "&
"sig asg has a wait statement with no sensitivity "&
"clause except for maybe the signal 'GUARD'" ,
(Not s3) and ((SavTime+10 ns) = Std.Standard.Now) ) ;
when others =>
test_report ( "ARCH00447.Chk_s3" ,
"In absence of primaries that denote signals, an "&
"equivalent process statement for the concurrent "&
"sig asg has a wait statement with no sensitivity "&
"clause except for maybe the signal 'GUARD'" ,
False ) ;
end case ;
counter := counter + 1 ;
end process Chk_s3 ;
-- The following depend on the explicit signal Guard
gs1 <= guarded transport True after 5 ns, False after 10 ns ;
gs2 <= guarded transport False after 5 ns, True after 10 ns when C else
True after 5 ns, False after 10 ns ;
with C select
gs3 <= guarded transport False after 5 ns, True after 10 ns when True,
True after 5 ns, False after 10 ns when others ;
Guard <= transport True after 100 ns;
Chk_gs1 :
process ( gs1 )
variable SavTime : Time ;
variable counter : integer := 0 ;
begin
case counter is
when 0 =>
SavTime := Std.Standard.Now ;
when 1 =>
test_report ( "ARCH00447.Chk_gs1" ,
"In absence of primaries that denote signals, an "&
"equivalent process statement for the concurrent "&
"sig asg has a wait statement with no sensitivity "&
"clause except for maybe the signal 'GUARD'" ,
gs1 and ((SavTime+105 ns) = Std.Standard.Now) ) ;
when 2 =>
test_report ( "ARCH00447.Chk_gs1" ,
"In absence of primaries that denote signals, an "&
"equivalent process statement for the concurrent "&
"sig asg has a wait statement with no sensitivity "&
"clause except for maybe the signal 'GUARD'" ,
(Not gs1) and ((SavTime+110 ns) = Std.Standard.Now) ) ;
when others =>
test_report ( "ARCH00447.Chk_gs1" ,
"In absence of primaries that denote signals, an "&
"equivalent process statement for the concurrent "&
"sig asg has a wait statement with no sensitivity "&
"clause except for maybe the signal 'GUARD'" ,
False ) ;
end case ;
counter := counter + 1 ;
end process Chk_gs1 ;
Chk_gs2 :
process ( gs2 )
variable SavTime : Time ;
variable counter : integer := 0 ;
begin
case counter is
when 0 =>
SavTime := Std.Standard.Now ;
when 1 =>
test_report ( "ARCH00447.Chk_gs2" ,
"In absence of primaries that denote signals, an "&
"equivalent process statement for the concurrent "&
"sig asg has a wait statement with no sensitivity "&
"clause except for maybe the signal 'GUARD'" ,
gs2 and ((SavTime+105 ns) = Std.Standard.Now) ) ;
when 2 =>
test_report ( "ARCH00447.Chk_gs2" ,
"In absence of primaries that denote signals, an "&
"equivalent process statement for the concurrent "&
"sig asg has a wait statement with no sensitivity "&
"clause except for maybe the signal 'GUARD'" ,
(Not gs2) and ((SavTime+110 ns) = Std.Standard.Now) ) ;
when others =>
test_report ( "ARCH00447.Chk_gs2" ,
"In absence of primaries that denote signals, an "&
"equivalent process statement for the concurrent "&
"sig asg has a wait statement with no sensitivity "&
"clause except for maybe the signal 'GUARD'" ,
False ) ;
end case ;
counter := counter + 1 ;
end process Chk_gs2 ;
Chk_gs3 :
process ( gs3 )
variable SavTime : Time ;
variable counter : integer := 0 ;
begin
case counter is
when 0 =>
SavTime := Std.Standard.Now ;
when 1 =>
test_report ( "ARCH00447.Chk_gs3" ,
"In absence of primaries that denote signals, an "&
"equivalent process statement for the concurrent "&
"sig asg has a wait statement with no sensitivity "&
"clause except for maybe the signal 'GUARD'" ,
gs3 and ((SavTime+105 ns) = Std.Standard.Now) ) ;
when 2 =>
test_report ( "ARCH00447.Chk_gs3" ,
"In absence of primaries that denote signals, an "&
"equivalent process statement for the concurrent "&
"sig asg has a wait statement with no sensitivity "&
"clause except for maybe the signal 'GUARD'" ,
(Not gs3) and ((SavTime+110 ns) = Std.Standard.Now) ) ;
when others =>
test_report ( "ARCH00447.Chk_gs3" ,
"In absence of primaries that denote signals, an "&
"equivalent process statement for the concurrent "&
"sig asg has a wait statement with no sensitivity "&
"clause except for maybe the signal 'GUARD'" ,
False ) ;
end case ;
counter := counter + 1 ;
end process Chk_gs3 ;
end ARCH00447 ;
entity ENT00447_Test_Bench is
end ENT00447_Test_Bench ;
architecture ARCH00447_Test_Bench of ENT00447_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00447 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00447_Test_Bench ;
| gpl-3.0 | 51ef18a611913ccc0ea06c50966bbce5 | 0.561013 | 4.588216 | false | true | false | false |
jairov4/accel-oil | solution_virtex5_plb/impl/pcores/nfa_accept_samples_generic_hw_top_v1_01_a/synhdl/vhdl/nfa_finals_buckets_if_ap_fifo.vhd | 3 | 2,827 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity nfa_finals_buckets_if_ap_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 16;
DEPTH : integer := 1);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of nfa_finals_buckets_if_ap_fifo is
type memtype is array (0 to DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal mStorage : memtype := (others => (others => '0'));
signal mInPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal mOutPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal internal_empty_n, internal_full_n : STD_LOGIC;
signal mFlag_nEF_hint : STD_LOGIC := '0'; -- 0: empty hint, 1: full hint
begin
if_dout <= mStorage(CONV_INTEGER(mOutPtr));
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
internal_empty_n <= '0' when mInPtr = mOutPtr and mFlag_nEF_hint = '0' else '1';
internal_full_n <= '0' when mInptr = mOutPtr and mFlag_nEF_hint = '1' else '1';
process (clk, reset)
begin
if reset = '1' then
mInPtr <= (others => '0');
mOutPtr <= (others => '0');
mFlag_nEF_hint <= '0'; -- empty hint
elsif clk'event and clk = '1' then
if if_read_ce = '1' and if_read = '1' and internal_empty_n = '1' then
if (mOutPtr = DEPTH -1) then
mOutPtr <= (others => '0');
mFlag_nEF_hint <= not mFlag_nEF_hint;
else
mOutPtr <= mOutPtr + 1;
end if;
end if;
if if_write_ce = '1' and if_write = '1' and internal_full_n = '1' then
mStorage(CONV_INTEGER(mInPtr)) <= if_din;
if (mInPtr = DEPTH -1) then
mInPtr <= (others => '0');
mFlag_nEF_hint <= not mFlag_nEF_hint;
else
mInPtr <= mInPtr + 1;
end if;
end if;
end if;
end process;
end architecture;
| lgpl-3.0 | b4df98bba2a601d3b6dc36406fe5c3ce | 0.496993 | 3.647742 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00620.vhd | 1 | 11,844 | -- NEED RESULT: ARCH00620: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00620: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00620.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00620.P2: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00620: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00620: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00620: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00620: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00620: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00620: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: P2: Transport transactions completed entirely passed
-- NEED RESULT: P1: Transport transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00620
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.3 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00620(ARCH00620)
-- ENT00620_Test_Bench(ARCH00620_Test_Bench)
--
-- REVISION HISTORY:
--
-- 24-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00620 is
port (
s_st_arr2_vector : inout st_arr2_vector
; s_st_arr3_vector : inout st_arr3_vector
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_arr2_vector : chk_sig_type := -1 ;
signal chk_st_arr3_vector : chk_sig_type := -1 ;
--
end ENT00620 ;
--
--
architecture ARCH00620 of ENT00620 is
subtype chk_time_type is Time ;
signal s_st_arr2_vector_savt : chk_time_type := 0 ns ;
signal s_st_arr3_vector_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_arr2_vector_cnt : chk_cnt_type := 0 ;
signal s_st_arr3_vector_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 3 ;
signal st_arr2_vector_select : select_type := 1 ;
signal st_arr3_vector_select : select_type := 1 ;
--
procedure P1
(signal s_st_arr2_vector : in st_arr2_vector ;
signal select_sig : out Select_Type ;
signal savtime : out Chk_Time_Type ;
signal chk_sig : out Chk_Sig_Type ;
signal count : out Integer)
is
variable correct : boolean ;
begin
case s_st_arr2_vector_cnt is
when 0
=> null ;
-- s_st_arr2_vector(lowb)(highb,false) <= transport
-- c_st_arr2_vector_2(lowb)(highb,false) after 10 ns,
-- c_st_arr2_vector_1(lowb)(highb,false) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2_vector(lowb)(highb,false) =
c_st_arr2_vector_2(lowb)(highb,false) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00620" ,
"Concurrent proc call 1",
correct ) ;
--
when 2
=> correct :=
s_st_arr2_vector(lowb)(highb,false) =
c_st_arr2_vector_1(lowb)(highb,false) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00620.P1" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
select_sig <= transport 2 ;
-- s_st_arr2_vector(lowb)(highb,false) <= transport
-- c_st_arr2_vector_2(lowb)(highb,false) after 10 ns ,
-- c_st_arr2_vector_1(lowb)(highb,false) after 20 ns ,
-- c_st_arr2_vector_2(lowb)(highb,false) after 30 ns ,
-- c_st_arr2_vector_1(lowb)(highb,false) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2_vector(lowb)(highb,false) =
c_st_arr2_vector_2(lowb)(highb,false) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00620" ,
"Concurrent proc call 2",
correct ) ;
select_sig <= transport 3 ;
-- s_st_arr2_vector(lowb)(highb,false) <= transport
-- c_st_arr2_vector_1(lowb)(highb,false) after 5 ns ;
--
when 4
=> correct :=
s_st_arr2_vector(lowb)(highb,false) =
c_st_arr2_vector_1(lowb)(highb,false) and
(s_st_arr2_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00620" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00620" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00620" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
savtime <= transport Std.Standard.Now ;
chk_sig <= transport s_st_arr2_vector_cnt
after (1 us - Std.Standard.Now) ;
count <= transport s_st_arr2_vector_cnt + 1 ;
--
end ;
--
procedure P2
(signal s_st_arr3_vector : in st_arr3_vector ;
signal select_sig : out Select_Type ;
signal savtime : out Chk_Time_Type ;
signal chk_sig : out Chk_Sig_Type ;
signal count : out Integer)
is
variable correct : boolean ;
begin
case s_st_arr3_vector_cnt is
when 0
=> null ;
-- s_st_arr3_vector(highb)(lowb,true) <= transport
-- c_st_arr3_vector_2(highb)(lowb,true) after 10 ns,
-- c_st_arr3_vector_1(highb)(lowb,true) after 20 ns ;
--
when 1
=> correct :=
s_st_arr3_vector(highb)(lowb,true) =
c_st_arr3_vector_2(highb)(lowb,true) and
(s_st_arr3_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00620" ,
"Concurrent proc call 1",
correct ) ;
--
when 2
=> correct :=
s_st_arr3_vector(highb)(lowb,true) =
c_st_arr3_vector_1(highb)(lowb,true) and
(s_st_arr3_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00620.P2" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
select_sig <= transport 2 ;
-- s_st_arr3_vector(highb)(lowb,true) <= transport
-- c_st_arr3_vector_2(highb)(lowb,true) after 10 ns ,
-- c_st_arr3_vector_1(highb)(lowb,true) after 20 ns ,
-- c_st_arr3_vector_2(highb)(lowb,true) after 30 ns ,
-- c_st_arr3_vector_1(highb)(lowb,true) after 40 ns ;
--
when 3
=> correct :=
s_st_arr3_vector(highb)(lowb,true) =
c_st_arr3_vector_2(highb)(lowb,true) and
(s_st_arr3_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00620" ,
"Concurrent proc call 2",
correct ) ;
select_sig <= transport 3 ;
-- s_st_arr3_vector(highb)(lowb,true) <= transport
-- c_st_arr3_vector_1(highb)(lowb,true) after 5 ns ;
--
when 4
=> correct :=
s_st_arr3_vector(highb)(lowb,true) =
c_st_arr3_vector_1(highb)(lowb,true) and
(s_st_arr3_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00620" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00620" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00620" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
savtime <= transport Std.Standard.Now ;
chk_sig <= transport s_st_arr3_vector_cnt
after (1 us - Std.Standard.Now) ;
count <= transport s_st_arr3_vector_cnt + 1 ;
--
end ;
--
begin
CHG1 :
P1(
s_st_arr2_vector ,
st_arr2_vector_select ,
s_st_arr2_vector_savt ,
chk_st_arr2_vector ,
s_st_arr2_vector_cnt ) ;
--
PGEN_CHKP_1 :
process ( chk_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions completed entirely",
chk_st_arr2_vector = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
with st_arr2_vector_select select
s_st_arr2_vector(lowb)(highb,false) <= transport
c_st_arr2_vector_2(lowb)(highb,false) after 10 ns,
c_st_arr2_vector_1(lowb)(highb,false) after 20 ns
when 1,
--
c_st_arr2_vector_2(lowb)(highb,false) after 10 ns ,
c_st_arr2_vector_1(lowb)(highb,false) after 20 ns ,
c_st_arr2_vector_2(lowb)(highb,false) after 30 ns ,
c_st_arr2_vector_1(lowb)(highb,false) after 40 ns
when 2,
--
c_st_arr2_vector_1(lowb)(highb,false) after 5 ns when 3 ;
--
CHG2 :
P2(
s_st_arr3_vector ,
st_arr3_vector_select ,
s_st_arr3_vector_savt ,
chk_st_arr3_vector ,
s_st_arr3_vector_cnt ) ;
--
PGEN_CHKP_2 :
process ( chk_st_arr3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions completed entirely",
chk_st_arr3_vector = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
with st_arr3_vector_select select
s_st_arr3_vector(highb)(lowb,true) <= transport
c_st_arr3_vector_2(highb)(lowb,true) after 10 ns,
c_st_arr3_vector_1(highb)(lowb,true) after 20 ns
when 1,
--
c_st_arr3_vector_2(highb)(lowb,true) after 10 ns ,
c_st_arr3_vector_1(highb)(lowb,true) after 20 ns ,
c_st_arr3_vector_2(highb)(lowb,true) after 30 ns ,
c_st_arr3_vector_1(highb)(lowb,true) after 40 ns
when 2,
--
c_st_arr3_vector_1(highb)(lowb,true) after 5 ns when 3 ;
--
end ARCH00620 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00620_Test_Bench is
signal s_st_arr2_vector : st_arr2_vector
:= c_st_arr2_vector_1 ;
signal s_st_arr3_vector : st_arr3_vector
:= c_st_arr3_vector_1 ;
--
end ENT00620_Test_Bench ;
--
--
architecture ARCH00620_Test_Bench of ENT00620_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_arr2_vector : inout st_arr2_vector
; s_st_arr3_vector : inout st_arr3_vector
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00620 ( ARCH00620 ) ;
begin
CIS1 : UUT
port map (
s_st_arr2_vector
, s_st_arr3_vector
)
;
end block L1 ;
end ARCH00620_Test_Bench ;
| gpl-3.0 | 31e2e76bdd81a1c77c3758ce63dc1d49 | 0.530395 | 3.317647 | false | true | false | false |
jairov4/accel-oil | solution_virtex5_plb/impl/vhdl/nfa_get_initials.vhd | 3 | 12,351 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_get_initials is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
ap_ce : IN STD_LOGIC;
nfa_initials_buckets_req_din : OUT STD_LOGIC;
nfa_initials_buckets_req_full_n : IN STD_LOGIC;
nfa_initials_buckets_req_write : OUT STD_LOGIC;
nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_initials_buckets_rsp_read : OUT STD_LOGIC;
nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of nfa_get_initials is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_ST_pp0_stg1_fsm_1 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_ST_pp0_stg2_fsm_2 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_ST_pp0_stg3_fsm_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
signal ap_CS_fsm : STD_LOGIC_VECTOR (1 downto 0) := "10";
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal nfa_initials_buckets_read_reg_59 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppiten_pp0_it0_preg : STD_LOGIC := '0';
signal ap_NS_fsm : STD_LOGIC_VECTOR (1 downto 0);
signal ap_sig_pprstidle_pp0 : STD_LOGIC;
signal ap_sig_bdd_131 : BOOLEAN;
signal ap_sig_bdd_130 : BOOLEAN;
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it0_preg assign process. --
ap_reg_ppiten_pp0_it0_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it0_preg <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)))))) then
ap_reg_ppiten_pp0_it0_preg <= ap_start;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)))) then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
elsif (((ap_ST_pp0_stg3_fsm_3 = ap_CS_fsm) and (ap_const_logic_1 = ap_ce))) then
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce) and (ap_ST_pp0_stg2_fsm_2 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0))))) then
nfa_initials_buckets_read_reg_59 <= nfa_initials_buckets_datain;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it1 , ap_ce , nfa_initials_buckets_rsp_empty_n , ap_sig_pprstidle_pp0)
begin
case ap_CS_fsm is
when ap_ST_pp0_stg0_fsm_0 =>
if ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)))) and not(((ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_start))))) then
ap_NS_fsm <= ap_ST_pp0_stg1_fsm_1;
else
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
end if;
when ap_ST_pp0_stg1_fsm_1 =>
if ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))) and not((ap_const_logic_1 = ap_sig_pprstidle_pp0)))) then
ap_NS_fsm <= ap_ST_pp0_stg2_fsm_2;
elsif ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_sig_pprstidle_pp0))) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_NS_fsm <= ap_ST_pp0_stg1_fsm_1;
end if;
when ap_ST_pp0_stg2_fsm_2 =>
if (not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0))))) then
ap_NS_fsm <= ap_ST_pp0_stg3_fsm_3;
else
ap_NS_fsm <= ap_ST_pp0_stg2_fsm_2;
end if;
when ap_ST_pp0_stg3_fsm_3 =>
if ((ap_const_logic_1 = ap_ce)) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_NS_fsm <= ap_ST_pp0_stg3_fsm_3;
end if;
when others =>
ap_NS_fsm <= "XX";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_ce, nfa_initials_buckets_rsp_empty_n)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_ce) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_ce)
begin
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg3_fsm_3 = ap_CS_fsm) and (ap_const_logic_1 = ap_ce))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_reg_ppiten_pp0_it0 assign process. --
ap_reg_ppiten_pp0_it0_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0_preg)
begin
if ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm)) then
ap_reg_ppiten_pp0_it0 <= ap_start;
else
ap_reg_ppiten_pp0_it0 <= ap_reg_ppiten_pp0_it0_preg;
end if;
end process;
ap_return_0 <= nfa_initials_buckets_read_reg_59;
ap_return_1 <= nfa_initials_buckets_datain;
-- ap_sig_bdd_130 assign process. --
ap_sig_bdd_130_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_ce)
begin
ap_sig_bdd_130 <= ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce));
end process;
-- ap_sig_bdd_131 assign process. --
ap_sig_bdd_131_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0)
begin
ap_sig_bdd_131 <= ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))));
end process;
-- ap_sig_pprstidle_pp0 assign process. --
ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0)
begin
if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_start))) then
ap_sig_pprstidle_pp0 <= ap_const_logic_1;
else
ap_sig_pprstidle_pp0 <= ap_const_logic_0;
end if;
end process;
-- nfa_initials_buckets_address assign process. --
nfa_initials_buckets_address_assign_proc : process(ap_CS_fsm, ap_sig_bdd_131, ap_sig_bdd_130)
begin
if (ap_sig_bdd_130) then
if ((ap_ST_pp0_stg3_fsm_3 = ap_CS_fsm)) then
nfa_initials_buckets_address <= ap_const_lv64_1(32 - 1 downto 0);
elsif (ap_sig_bdd_131) then
nfa_initials_buckets_address <= ap_const_lv32_0;
else
nfa_initials_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
nfa_initials_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
nfa_initials_buckets_dataout <= ap_const_lv32_0;
nfa_initials_buckets_req_din <= ap_const_logic_0;
-- nfa_initials_buckets_req_write assign process. --
nfa_initials_buckets_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_ce)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg3_fsm_3 = ap_CS_fsm) and (ap_const_logic_1 = ap_ce)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)))))) then
nfa_initials_buckets_req_write <= ap_const_logic_1;
else
nfa_initials_buckets_req_write <= ap_const_logic_0;
end if;
end process;
-- nfa_initials_buckets_rsp_read assign process. --
nfa_initials_buckets_rsp_read_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_ce, nfa_initials_buckets_rsp_empty_n)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce) and (ap_ST_pp0_stg2_fsm_2 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_ce) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))))) then
nfa_initials_buckets_rsp_read <= ap_const_logic_1;
else
nfa_initials_buckets_rsp_read <= ap_const_logic_0;
end if;
end process;
nfa_initials_buckets_size <= ap_const_lv32_1;
end behav;
| lgpl-3.0 | d0543431109587b82f8f6c9a8e0d831f | 0.582463 | 2.801951 | false | false | false | false |
grwlf/vsim | vhdl_ct/pro000026.vhd | 1 | 6,192 | -- Prosoft VHDL tests.
--
-- Copyright (C) 2011 Prosoft.
--
-- Author: Zefirov, Karavaev.
--
-- This is a set of simplest tests for isolated tests of VHDL features.
--
-- Nothing more than standard package should be required.
--
-- Categories: entity, architecture, process, type, array, for-loop, function, if-then-else, Attributes-of-the-array-type-or-objects-of-the-array-type
entity ENT00026_Test_Bench is
end entity ENT00026_Test_Bench;
architecture ARCH00026_Test_Bench of ENT00026_Test_Bench is
signal rst : bit := '0';
signal clk : bit := '0';
pure function integer_log2(v : in natural) return integer is
variable log2count : integer := 0;
variable x : integer := v;
begin
while x > 1 loop
log2count := log2count + 1;
x := (x + 1) / 2;
end loop;
return log2count;
end function integer_log2;
constant data_width : natural := 32;
constant addr_width : natural := 32;
function bus_width_ctrl (width : natural) return natural is
variable r : natural;
begin
r := width;
assert r mod 8 = 0
report "Check the bus data/addr width. Actual width is not multiple of 8."
severity WARNING;
return r;
end function;
constant bus_data_width : natural := bus_width_ctrl(data_width);
constant bus_addr_width : natural := bus_width_ctrl(addr_width);
constant master_num : natural := 5;
function bus_mst_control (addr_width, mst_num : natural) return natural is
variable max_dev : integer;
variable r : integer;
begin
max_dev := 2**(addr_width-4);
assert mst_num < max_dev
report "Number of masters is bigger then the possible number of devices on the bus. You must correct the number of masters"
severity ERROR;
if mst_num <= max_dev then
r := mst_num;
else
r := max_dev;
end if;
if r < 0 then
r := 0;
end if;
assert r > 0
report "System have no any masters!"
severity WARNING;
return natural(r);
end function;
constant bus_master_num : natural := bus_mst_control(bus_addr_width,master_num);
type device_conf_type is record
addr_mask : bit_vector(bus_addr_width-1 downto 0);
addr_mask_msb : bit_vector(integer_log2(bus_addr_width)-1 downto 0);
addr_mask_lsb : bit_vector(integer_log2(bus_addr_width)-1 downto 0);
registered : bit;
periphery : bit;
end record;
type device_conf_array_type is array (natural range <>) of device_conf_type;
type addr_mask_boardBit_array_type is array (natural range <>) of bit_vector(4 downto 0);
type registered_array_type is array (natural range <>) of bit_vector(3 downto 0);
type addr_mask_array_type is array (natural range <>) of bit_vector(bus_addr_width-1 downto 0);
signal mst_conf : device_conf_array_type(bus_master_num-1 downto 0);
signal mst_registered : registered_array_type(bus_master_num-1 downto 0);
signal mst_addr_mask_msb : addr_mask_boardBit_array_type(bus_master_num-1 downto 0);
signal mst_addr_mask_lsb : addr_mask_boardBit_array_type(bus_master_num-1 downto 0);
signal mst_addr_mask : addr_mask_array_type(bus_master_num-1 downto 0);
constant const_1_4b : bit_vector(3 downto 0) := "0001";
constant const_1_5b : bit_vector(4 downto 0) := "00001";
constant const_30_32b : bit_vector(31 downto 0) := x"0000001E";
constant const_1m_5b : bit_vector(4 downto 0) := "11111";
function add_bit_vector (l,r : bit_vector) return bit_vector is
variable left : bit_vector(l'length-1 downto 0);
variable right : bit_vector(r'length-1 downto 0);
variable res : bit_vector(l'length-1 downto 0);
variable c : bit_vector(l'length downto 0);
begin
left := l;
right := r;
c(0) := '0';
sum_loop: for i in 0 to res'length-1 loop
res(i) := (left(i) xor right(i)) xor c(i);
c(i+1) := ((left(i) xor right(i)) and c(i)) or (left(i) and right(i));
end loop;
return res;
end function add_bit_vector;
begin
clk <= not clk after 1 us;
process
begin
rst <= '0';
wait for 10 us;
rst <= '1';
wait;
end process;
process (rst, mst_addr_mask_msb, mst_addr_mask_lsb, mst_addr_mask, mst_registered)
begin
if rst = '0' then
mst_conf_components_loop: for i in mst_conf'length-1 downto 0 loop
if i = bus_master_num-1 then
mst_registered(i) <= x"7";
mst_addr_mask(i) <= x"FFF00000";
mst_addr_mask_lsb(i) <= "00110";
mst_addr_mask_msb(i) <= "11111";
else
mst_registered(i) <= add_bit_vector((mst_registered(i+1)(2 downto 0) & mst_registered(i+1)(3)), const_1_4b);
mst_addr_mask(i) <= add_bit_vector(mst_addr_mask(i+1), const_30_32b);
if mst_addr_mask_msb(i+1) >= "11100" then
mst_addr_mask_msb(i) <= add_bit_vector(mst_addr_mask_msb(i+1),const_1m_5b);
else
mst_addr_mask_msb(i) <= "11111";
end if;
if mst_addr_mask_lsb(i+1) <= "01100" then
mst_addr_mask_lsb(i) <= add_bit_vector(mst_addr_mask_lsb(i+1),const_1_5b);
else
mst_addr_mask_lsb(i) <= "00110";
end if;
end if;
end loop;
end if;
end process;
process (rst)
begin
if rst = '1' then
assert (mst_registered(0) = x"3" and mst_registered(1) = x"1" and mst_registered(2) = x"0" and mst_registered(3) = x"F" and mst_registered(4) = x"7")
report "Wrong work of a for-loop"
severity FAILURE;
end if;
end process;
end architecture ARCH00026_Test_Bench;
| gpl-3.0 | 58b7a66cf5b4db02b715b8db2158ff8e | 0.562177 | 3.524189 | false | false | false | false |
jairov4/accel-oil | impl/impl_test_single/simulation/behavioral/system_mb_plb_wrapper.vhd | 1 | 14,546 | -------------------------------------------------------------------------------
-- system_mb_plb_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plb_v46_v1_05_a;
use plb_v46_v1_05_a.all;
entity system_mb_plb_wrapper is
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to 1);
MPLB_Rst : out std_logic_vector(0 to 6);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to 31);
DCR_ABus : in std_logic_vector(0 to 9);
DCR_DBus : in std_logic_vector(0 to 31);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to 223);
M_UABus : in std_logic_vector(0 to 223);
M_BE : in std_logic_vector(0 to 55);
M_RNW : in std_logic_vector(0 to 6);
M_abort : in std_logic_vector(0 to 6);
M_busLock : in std_logic_vector(0 to 6);
M_TAttribute : in std_logic_vector(0 to 111);
M_lockErr : in std_logic_vector(0 to 6);
M_MSize : in std_logic_vector(0 to 13);
M_priority : in std_logic_vector(0 to 13);
M_rdBurst : in std_logic_vector(0 to 6);
M_request : in std_logic_vector(0 to 6);
M_size : in std_logic_vector(0 to 27);
M_type : in std_logic_vector(0 to 20);
M_wrBurst : in std_logic_vector(0 to 6);
M_wrDBus : in std_logic_vector(0 to 447);
Sl_addrAck : in std_logic_vector(0 to 1);
Sl_MRdErr : in std_logic_vector(0 to 13);
Sl_MWrErr : in std_logic_vector(0 to 13);
Sl_MBusy : in std_logic_vector(0 to 13);
Sl_rdBTerm : in std_logic_vector(0 to 1);
Sl_rdComp : in std_logic_vector(0 to 1);
Sl_rdDAck : in std_logic_vector(0 to 1);
Sl_rdDBus : in std_logic_vector(0 to 127);
Sl_rdWdAddr : in std_logic_vector(0 to 7);
Sl_rearbitrate : in std_logic_vector(0 to 1);
Sl_SSize : in std_logic_vector(0 to 3);
Sl_wait : in std_logic_vector(0 to 1);
Sl_wrBTerm : in std_logic_vector(0 to 1);
Sl_wrComp : in std_logic_vector(0 to 1);
Sl_wrDAck : in std_logic_vector(0 to 1);
Sl_MIRQ : in std_logic_vector(0 to 13);
PLB_MIRQ : out std_logic_vector(0 to 6);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to 7);
PLB_MAddrAck : out std_logic_vector(0 to 6);
PLB_MTimeout : out std_logic_vector(0 to 6);
PLB_MBusy : out std_logic_vector(0 to 6);
PLB_MRdErr : out std_logic_vector(0 to 6);
PLB_MWrErr : out std_logic_vector(0 to 6);
PLB_MRdBTerm : out std_logic_vector(0 to 6);
PLB_MRdDAck : out std_logic_vector(0 to 6);
PLB_MRdDBus : out std_logic_vector(0 to 447);
PLB_MRdWdAddr : out std_logic_vector(0 to 27);
PLB_MRearbitrate : out std_logic_vector(0 to 6);
PLB_MWrBTerm : out std_logic_vector(0 to 6);
PLB_MWrDAck : out std_logic_vector(0 to 6);
PLB_MSSize : out std_logic_vector(0 to 13);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to 2);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to 1);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to 63);
PLB_wrPrim : out std_logic_vector(0 to 1);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to 6);
PLB_SMWrErr : out std_logic_vector(0 to 6);
PLB_SMBusy : out std_logic_vector(0 to 6);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to 63);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
Bus_Error_Det : out std_logic
);
end system_mb_plb_wrapper;
architecture STRUCTURE of system_mb_plb_wrapper is
component plb_v46 is
generic (
C_PLBV46_NUM_MASTERS : integer;
C_PLBV46_NUM_SLAVES : integer;
C_PLBV46_MID_WIDTH : integer;
C_PLBV46_AWIDTH : integer;
C_PLBV46_DWIDTH : integer;
C_DCR_INTFCE : integer;
C_BASEADDR : std_logic_vector;
C_HIGHADDR : std_logic_vector;
C_DCR_AWIDTH : integer;
C_DCR_DWIDTH : integer;
C_EXT_RESET_HIGH : integer;
C_IRQ_ACTIVE : std_logic;
C_ADDR_PIPELINING_TYPE : integer;
C_FAMILY : string;
C_P2P : integer;
C_ARB_TYPE : integer
);
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
MPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_ABus : in std_logic_vector(0 to C_DCR_AWIDTH-1);
DCR_DBus : in std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*32)-1);
M_UABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*32)-1);
M_BE : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*(C_PLBV46_DWIDTH/8))-1);
M_RNW : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_abort : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_busLock : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_TAttribute : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*16)-1);
M_lockErr : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_MSize : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
M_priority : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
M_rdBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_request : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_size : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*4)-1);
M_type : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*3)-1);
M_wrBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_wrDBus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1);
Sl_addrAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_MRdErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1);
Sl_MWrErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1);
Sl_MBusy : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS - 1 );
Sl_rdBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdDBus : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_DWIDTH-1);
Sl_rdWdAddr : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*4-1);
Sl_rearbitrate : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_SSize : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*2-1);
Sl_wait : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_MIRQ : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS-1);
PLB_MIRQ : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to (C_PLBV46_DWIDTH/8)-1);
PLB_MAddrAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MTimeout : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdDBus : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1);
PLB_MRdWdAddr : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*4)-1);
PLB_MRearbitrate : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MSSize : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to C_PLBV46_MID_WIDTH-1);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1);
PLB_wrPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SMWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SMBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
Bus_Error_Det : out std_logic
);
end component;
begin
mb_plb : plb_v46
generic map (
C_PLBV46_NUM_MASTERS => 7,
C_PLBV46_NUM_SLAVES => 2,
C_PLBV46_MID_WIDTH => 3,
C_PLBV46_AWIDTH => 32,
C_PLBV46_DWIDTH => 64,
C_DCR_INTFCE => 0,
C_BASEADDR => B"1111111111",
C_HIGHADDR => B"0000000000",
C_DCR_AWIDTH => 10,
C_DCR_DWIDTH => 32,
C_EXT_RESET_HIGH => 1,
C_IRQ_ACTIVE => '1',
C_ADDR_PIPELINING_TYPE => 1,
C_FAMILY => "virtex5",
C_P2P => 0,
C_ARB_TYPE => 0
)
port map (
PLB_Clk => PLB_Clk,
SYS_Rst => SYS_Rst,
PLB_Rst => PLB_Rst,
SPLB_Rst => SPLB_Rst,
MPLB_Rst => MPLB_Rst,
PLB_dcrAck => PLB_dcrAck,
PLB_dcrDBus => PLB_dcrDBus,
DCR_ABus => DCR_ABus,
DCR_DBus => DCR_DBus,
DCR_Read => DCR_Read,
DCR_Write => DCR_Write,
M_ABus => M_ABus,
M_UABus => M_UABus,
M_BE => M_BE,
M_RNW => M_RNW,
M_abort => M_abort,
M_busLock => M_busLock,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_MSize => M_MSize,
M_priority => M_priority,
M_rdBurst => M_rdBurst,
M_request => M_request,
M_size => M_size,
M_type => M_type,
M_wrBurst => M_wrBurst,
M_wrDBus => M_wrDBus,
Sl_addrAck => Sl_addrAck,
Sl_MRdErr => Sl_MRdErr,
Sl_MWrErr => Sl_MWrErr,
Sl_MBusy => Sl_MBusy,
Sl_rdBTerm => Sl_rdBTerm,
Sl_rdComp => Sl_rdComp,
Sl_rdDAck => Sl_rdDAck,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rearbitrate => Sl_rearbitrate,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_wrBTerm => Sl_wrBTerm,
Sl_wrComp => Sl_wrComp,
Sl_wrDAck => Sl_wrDAck,
Sl_MIRQ => Sl_MIRQ,
PLB_MIRQ => PLB_MIRQ,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_BE => PLB_BE,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MSSize => PLB_MSSize,
PLB_PAValid => PLB_PAValid,
PLB_RNW => PLB_RNW,
PLB_SAValid => PLB_SAValid,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_TAttribute => PLB_TAttribute,
PLB_lockErr => PLB_lockErr,
PLB_masterID => PLB_masterID,
PLB_MSize => PLB_MSize,
PLB_rdPendPri => PLB_rdPendPri,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdBurst => PLB_rdBurst,
PLB_rdPrim => PLB_rdPrim,
PLB_reqPri => PLB_reqPri,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_wrBurst => PLB_wrBurst,
PLB_wrDBus => PLB_wrDBus,
PLB_wrPrim => PLB_wrPrim,
PLB_SaddrAck => PLB_SaddrAck,
PLB_SMRdErr => PLB_SMRdErr,
PLB_SMWrErr => PLB_SMWrErr,
PLB_SMBusy => PLB_SMBusy,
PLB_SrdBTerm => PLB_SrdBTerm,
PLB_SrdComp => PLB_SrdComp,
PLB_SrdDAck => PLB_SrdDAck,
PLB_SrdDBus => PLB_SrdDBus,
PLB_SrdWdAddr => PLB_SrdWdAddr,
PLB_Srearbitrate => PLB_Srearbitrate,
PLB_Sssize => PLB_Sssize,
PLB_Swait => PLB_Swait,
PLB_SwrBTerm => PLB_SwrBTerm,
PLB_SwrComp => PLB_SwrComp,
PLB_SwrDAck => PLB_SwrDAck,
Bus_Error_Det => Bus_Error_Det
);
end architecture STRUCTURE;
| lgpl-3.0 | 1a11fb8aab56c1f198fe985fc7699fb4 | 0.610408 | 3.039281 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00469.vhd | 1 | 2,109 | -- NEED RESULT: ARCH00469: Entity name list has more than one designator passed
-- NEED RESULT: ARCH00469: Entity name list has one designator passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00469
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 5.1 (1)
-- 5.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00469
-- ENT00469_Test_Bench(ARCH00469_Test_Bench)
--
-- REVISION HISTORY:
--
-- 6-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
package PKG00469 is
attribute Attr1 : Integer ;
attribute Attr2 : WORK.STANDARD_TYPES.st_boolean_vector ;
end PKG00469 ;
use WORK.PKG00469.all, WORK.STANDARD_TYPES.all ;
entity ENT00469_Test_Bench is
end ENT00469_Test_Bench ;
use WORK.STANDARD_TYPES.all ;
architecture ARCH00469_Test_Bench of ENT00469_Test_Bench is
constant C1, C2 : Real := 0.0 ;
signal S1 : Bit := '0' ;
signal S2, S3 : Std.Standard.Severity_Level := NOTE ;
attribute Attr1 of C1 : constant is Integer'Low ;
attribute Attr2 of S3 : signal is c_st_boolean_vector_1 ;
attribute Attr1 of S1, S2 : signal is Integer'High ;
attribute Attr2 of C1, C2 : constant is c_st_boolean_vector_2 ;
begin
process
begin
test_report ( "ARCH00469" ,
"Entity name list has more than one designator" ,
S1'Attr1 = Integer'High and
S2'Attr1 = Integer'High and
C1'Attr2 = c_st_boolean_vector_2 and
C2'Attr2 = c_st_boolean_vector_2 ) ;
wait ;
end process ;
process
begin
test_report ( "ARCH00469" ,
"Entity name list has one designator" ,
C1'Attr1 = Integer'Low and
S3'Attr2 = c_st_boolean_vector_1 ) ;
wait ;
end process ;
end ARCH00469_Test_Bench ;
| gpl-3.0 | ede679b754523850856b881da7f3dc09 | 0.552394 | 3.396135 | false | true | false | false |
jairov4/accel-oil | impl/impl_test_pcie/hdl/system_stub.vhd | 1 | 6,382 | -------------------------------------------------------------------------------
-- system_stub.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_stub is
port (
fpga_0_DDR2_SDRAM_DDR2_Clk_pin : out std_logic_vector(1 downto 0);
fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin : out std_logic_vector(1 downto 0);
fpga_0_DDR2_SDRAM_DDR2_CE_pin : out std_logic_vector(1 downto 0);
fpga_0_DDR2_SDRAM_DDR2_CS_n_pin : out std_logic_vector(1 downto 0);
fpga_0_DDR2_SDRAM_DDR2_ODT_pin : out std_logic_vector(1 downto 0);
fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin : out std_logic;
fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin : out std_logic;
fpga_0_DDR2_SDRAM_DDR2_WE_n_pin : out std_logic;
fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin : out std_logic_vector(1 downto 0);
fpga_0_DDR2_SDRAM_DDR2_Addr_pin : out std_logic_vector(12 downto 0);
fpga_0_DDR2_SDRAM_DDR2_DQ_pin : inout std_logic_vector(63 downto 0);
fpga_0_DDR2_SDRAM_DDR2_DM_pin : out std_logic_vector(7 downto 0);
fpga_0_DDR2_SDRAM_DDR2_DQS_pin : inout std_logic_vector(7 downto 0);
fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin : inout std_logic_vector(7 downto 0);
fpga_0_SRAM_Mem_A_pin : out std_logic_vector(7 to 30);
fpga_0_SRAM_Mem_CEN_pin : out std_logic;
fpga_0_SRAM_Mem_OEN_pin : out std_logic;
fpga_0_SRAM_Mem_WEN_pin : out std_logic;
fpga_0_SRAM_Mem_BEN_pin : out std_logic_vector(0 to 3);
fpga_0_SRAM_Mem_ADV_LDN_pin : out std_logic;
fpga_0_SRAM_Mem_DQ_pin : inout std_logic_vector(0 to 31);
fpga_0_SRAM_ZBT_CLK_OUT_pin : out std_logic;
fpga_0_SRAM_ZBT_CLK_FB_pin : in std_logic;
fpga_0_PCIe_Bridge_RXN_pin : in std_logic;
fpga_0_PCIe_Bridge_RXP_pin : in std_logic;
fpga_0_PCIe_Bridge_TXN_pin : out std_logic;
fpga_0_PCIe_Bridge_TXP_pin : out std_logic;
fpga_0_clk_1_sys_clk_pin : in std_logic;
fpga_0_rst_1_sys_rst_pin : in std_logic;
fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin : in std_logic;
fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin : in std_logic
);
end system_stub;
architecture STRUCTURE of system_stub is
component system is
port (
fpga_0_DDR2_SDRAM_DDR2_Clk_pin : out std_logic_vector(1 downto 0);
fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin : out std_logic_vector(1 downto 0);
fpga_0_DDR2_SDRAM_DDR2_CE_pin : out std_logic_vector(1 downto 0);
fpga_0_DDR2_SDRAM_DDR2_CS_n_pin : out std_logic_vector(1 downto 0);
fpga_0_DDR2_SDRAM_DDR2_ODT_pin : out std_logic_vector(1 downto 0);
fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin : out std_logic;
fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin : out std_logic;
fpga_0_DDR2_SDRAM_DDR2_WE_n_pin : out std_logic;
fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin : out std_logic_vector(1 downto 0);
fpga_0_DDR2_SDRAM_DDR2_Addr_pin : out std_logic_vector(12 downto 0);
fpga_0_DDR2_SDRAM_DDR2_DQ_pin : inout std_logic_vector(63 downto 0);
fpga_0_DDR2_SDRAM_DDR2_DM_pin : out std_logic_vector(7 downto 0);
fpga_0_DDR2_SDRAM_DDR2_DQS_pin : inout std_logic_vector(7 downto 0);
fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin : inout std_logic_vector(7 downto 0);
fpga_0_SRAM_Mem_A_pin : out std_logic_vector(7 to 30);
fpga_0_SRAM_Mem_CEN_pin : out std_logic;
fpga_0_SRAM_Mem_OEN_pin : out std_logic;
fpga_0_SRAM_Mem_WEN_pin : out std_logic;
fpga_0_SRAM_Mem_BEN_pin : out std_logic_vector(0 to 3);
fpga_0_SRAM_Mem_ADV_LDN_pin : out std_logic;
fpga_0_SRAM_Mem_DQ_pin : inout std_logic_vector(0 to 31);
fpga_0_SRAM_ZBT_CLK_OUT_pin : out std_logic;
fpga_0_SRAM_ZBT_CLK_FB_pin : in std_logic;
fpga_0_PCIe_Bridge_RXN_pin : in std_logic;
fpga_0_PCIe_Bridge_RXP_pin : in std_logic;
fpga_0_PCIe_Bridge_TXN_pin : out std_logic;
fpga_0_PCIe_Bridge_TXP_pin : out std_logic;
fpga_0_clk_1_sys_clk_pin : in std_logic;
fpga_0_rst_1_sys_rst_pin : in std_logic;
fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin : in std_logic;
fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin : in std_logic
);
end component;
attribute BOX_TYPE : STRING;
attribute BOX_TYPE of system : component is "user_black_box";
begin
system_i : system
port map (
fpga_0_DDR2_SDRAM_DDR2_Clk_pin => fpga_0_DDR2_SDRAM_DDR2_Clk_pin,
fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin => fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin,
fpga_0_DDR2_SDRAM_DDR2_CE_pin => fpga_0_DDR2_SDRAM_DDR2_CE_pin,
fpga_0_DDR2_SDRAM_DDR2_CS_n_pin => fpga_0_DDR2_SDRAM_DDR2_CS_n_pin,
fpga_0_DDR2_SDRAM_DDR2_ODT_pin => fpga_0_DDR2_SDRAM_DDR2_ODT_pin,
fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin => fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin,
fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin => fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin,
fpga_0_DDR2_SDRAM_DDR2_WE_n_pin => fpga_0_DDR2_SDRAM_DDR2_WE_n_pin,
fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin => fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin,
fpga_0_DDR2_SDRAM_DDR2_Addr_pin => fpga_0_DDR2_SDRAM_DDR2_Addr_pin,
fpga_0_DDR2_SDRAM_DDR2_DQ_pin => fpga_0_DDR2_SDRAM_DDR2_DQ_pin,
fpga_0_DDR2_SDRAM_DDR2_DM_pin => fpga_0_DDR2_SDRAM_DDR2_DM_pin,
fpga_0_DDR2_SDRAM_DDR2_DQS_pin => fpga_0_DDR2_SDRAM_DDR2_DQS_pin,
fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin => fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin,
fpga_0_SRAM_Mem_A_pin => fpga_0_SRAM_Mem_A_pin,
fpga_0_SRAM_Mem_CEN_pin => fpga_0_SRAM_Mem_CEN_pin,
fpga_0_SRAM_Mem_OEN_pin => fpga_0_SRAM_Mem_OEN_pin,
fpga_0_SRAM_Mem_WEN_pin => fpga_0_SRAM_Mem_WEN_pin,
fpga_0_SRAM_Mem_BEN_pin => fpga_0_SRAM_Mem_BEN_pin,
fpga_0_SRAM_Mem_ADV_LDN_pin => fpga_0_SRAM_Mem_ADV_LDN_pin,
fpga_0_SRAM_Mem_DQ_pin => fpga_0_SRAM_Mem_DQ_pin,
fpga_0_SRAM_ZBT_CLK_OUT_pin => fpga_0_SRAM_ZBT_CLK_OUT_pin,
fpga_0_SRAM_ZBT_CLK_FB_pin => fpga_0_SRAM_ZBT_CLK_FB_pin,
fpga_0_PCIe_Bridge_RXN_pin => fpga_0_PCIe_Bridge_RXN_pin,
fpga_0_PCIe_Bridge_RXP_pin => fpga_0_PCIe_Bridge_RXP_pin,
fpga_0_PCIe_Bridge_TXN_pin => fpga_0_PCIe_Bridge_TXN_pin,
fpga_0_PCIe_Bridge_TXP_pin => fpga_0_PCIe_Bridge_TXP_pin,
fpga_0_clk_1_sys_clk_pin => fpga_0_clk_1_sys_clk_pin,
fpga_0_rst_1_sys_rst_pin => fpga_0_rst_1_sys_rst_pin,
fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin => fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin,
fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin => fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin
);
end architecture STRUCTURE;
| lgpl-3.0 | fbe4d5caa6959b1aa3681781ad03be76 | 0.641022 | 2.510622 | false | false | false | false |
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