repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
besm6/micro-besm | tests/2910/vhdl/funct_block_alg_beh/components/control/test_vectors_control.vhdl | 1 | 146,080 | --------------------------------------------------------------------------------
--
-- AMD 2910 Benchmark (Functional blocks) (Algorithmic Behaviour of Funct blocks)
--
-- Source: AMD data book
--
-- VHDL Benchmark author Indraneel Ghosh
-- University Of California, Irvine, CA 92717
--
-- Developed on Feb 19, 1992
--
-- Verification Information:
--
-- Verified By whom? Date Simulator
-- -------- ------------ -------- ------------
-- Syntax yes Champaka Ramachandran Sept17, 92 ZYCAD
-- Functionality yes Champaka Ramachandran Sept17, 92 ZYCAD
--------------------------------------------------------------------------------
--library ZYCAD;
use work.types.all;
use work.MVL7_functions.all; --some binary functions
use work.synthesis_types.all; --hints for synthesis
entity E is
end;
architecture AA of E is
component ccontrol
port (
I : in MVL7_VECTOR(3 downto 0);
CCEN_BAR : in MVL7;
CC_BAR : in MVL7;
Rzero_bar : in MVL7;
PL_BAR : out MVL7;
VECT_BAR : out MVL7;
MAP_BAR : out MVL7;
R_sel : out MVL7;
D_sel : out MVL7;
uPC_sel : out MVL7;
stack_sel : out MVL7;
decr : out MVL7;
load : out MVL7;
clear : out MVL7;
push : out MVL7;
pop : out MVL7
);
end component;
signal I : MVL7_VECTOR(3 downto 0);
signal CCEN_BAR : MVL7;
signal CC_BAR : MVL7;
signal Rzero_bar : MVL7;
signal PL_BAR : MVL7;
signal VECT_BAR : MVL7;
signal MAP_BAR : MVL7;
signal R_sel : MVL7;
signal D_sel : MVL7;
signal uPC_sel : MVL7;
signal stack_sel : MVL7;
signal decr : MVL7;
signal load : MVL7;
signal clear : MVL7;
signal push : MVL7;
signal pop : MVL7;
for all : ccontrol use entity work.control(control);
begin
CCONTROL1 : ccontrol port map(
I,
CCEN_BAR,
CC_BAR,
Rzero_bar,
PL_BAR,
VECT_BAR,
MAP_BAR,
R_sel,
D_sel,
uPC_sel,
stack_sel,
decr,
load,
clear,
push,
pop
);
process
begin
-- *********
-- * I = 0 *
-- *********
--------------------------
I <= "0000";
CCEN_BAR <= '0';
CC_BAR <= '1';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 0
assert (PL_BAR = '0')
report
"Assert 0 : < PL_BAR /= 0 >" -- Vector No: 0
severity warning;
assert (VECT_BAR = '1')
report
"Assert 1 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 2 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 3 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 4 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 5 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 6 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 7 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 8 : < load /= 0 >"
severity warning;
assert (clear = '1')
report
"Assert 9 : < clear /= 1 >"
severity warning;
assert (push = '0')
report
"Assert 10 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 11 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "0000";
CCEN_BAR <= '0';
CC_BAR <= '1';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 1
assert (PL_BAR = '0')
report
"Assert 12 : < PL_BAR /= 0 >" -- Vector No: 1
severity warning;
assert (VECT_BAR = '1')
report
"Assert 13 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 14 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 15 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 16 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 17 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 18 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 19 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 20 : < load /= 0 >"
severity warning;
assert (clear = '1')
report
"Assert 21 : < clear /= 1 >"
severity warning;
assert (push = '0')
report
"Assert 22 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 23 : < pop /= 0 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "0000";
CCEN_BAR <= '0';
CC_BAR <= '0';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 2
assert (PL_BAR = '0')
report
"Assert 24 : < PL_BAR /= 0 >" -- Vector No: 2
severity warning;
assert (VECT_BAR = '1')
report
"Assert 25 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 26 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 27 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 28 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 29 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 30 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 31 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 32 : < load /= 0 >"
severity warning;
assert (clear = '1')
report
"Assert 33 : < clear /= 1 >"
severity warning;
assert (push = '0')
report
"Assert 34 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 35 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "0000";
CCEN_BAR <= '0';
CC_BAR <= '0';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 3
assert (PL_BAR = '0')
report
"Assert 36 : < PL_BAR /= 0 >" -- Vector No: 3
severity warning;
assert (VECT_BAR = '1')
report
"Assert 37 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 38 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 39 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 40 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 41 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 42 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 43 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 44 : < load /= 0 >"
severity warning;
assert (clear = '1')
report
"Assert 45 : < clear /= 1 >"
severity warning;
assert (push = '0')
report
"Assert 46 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 47 : < pop /= 0 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "0000";
CCEN_BAR <= '1';
CC_BAR <= '1';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 4
assert (PL_BAR = '0')
report
"Assert 48 : < PL_BAR /= 0 >" -- Vector No: 4
severity warning;
assert (VECT_BAR = '1')
report
"Assert 49 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 50 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 51 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 52 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 53 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 54 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 55 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 56 : < load /= 0 >"
severity warning;
assert (clear = '1')
report
"Assert 57 : < clear /= 1 >"
severity warning;
assert (push = '0')
report
"Assert 58 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 59 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "0000";
CCEN_BAR <= '1';
CC_BAR <= '1';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 5
assert (PL_BAR = '0')
report
"Assert 60 : < PL_BAR /= 0 >" -- Vector No: 5
severity warning;
assert (VECT_BAR = '1')
report
"Assert 61 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 62 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 63 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 64 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 65 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 66 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 67 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 68 : < load /= 0 >"
severity warning;
assert (clear = '1')
report
"Assert 69 : < clear /= 1 >"
severity warning;
assert (push = '0')
report
"Assert 70 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 71 : < pop /= 0 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "0000";
CCEN_BAR <= '1';
CC_BAR <= '0';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 6
assert (PL_BAR = '0')
report
"Assert 72 : < PL_BAR /= 0 >" -- Vector No: 6
severity warning;
assert (VECT_BAR = '1')
report
"Assert 73 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 74 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 75 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 76 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 77 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 78 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 79 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 80 : < load /= 0 >"
severity warning;
assert (clear = '1')
report
"Assert 81 : < clear /= 1 >"
severity warning;
assert (push = '0')
report
"Assert 82 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 83 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "0000";
CCEN_BAR <= '1';
CC_BAR <= '0';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 7
assert (PL_BAR = '0')
report
"Assert 84 : < PL_BAR /= 0 >" -- Vector No: 7
severity warning;
assert (VECT_BAR = '1')
report
"Assert 85 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 86 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 87 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 88 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 89 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 90 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 91 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 92 : < load /= 0 >"
severity warning;
assert (clear = '1')
report
"Assert 93 : < clear /= 1 >"
severity warning;
assert (push = '0')
report
"Assert 94 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 95 : < pop /= 0 >"
severity warning;
wait for 1 ns;
-- ***********************************
-- *********
-- * I = 1 *
-- *********
--------------------------
I <= "0001";
CCEN_BAR <= '0';
CC_BAR <= '1';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 8
assert (PL_BAR = '0')
report
"Assert 96 : < PL_BAR /= 0 >" -- Vector No: 8
severity warning;
assert (VECT_BAR = '1')
report
"Assert 97 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 98 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 99 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 100 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 101 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 102 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 103 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 104 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 105 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 106 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 107 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "0001";
CCEN_BAR <= '0';
CC_BAR <= '1';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 9
assert (PL_BAR = '0')
report
"Assert 108 : < PL_BAR /= 0 >" -- Vector No: 9
severity warning;
assert (VECT_BAR = '1')
report
"Assert 109 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 110 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 111 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 112 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 113 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 114 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 115 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 116 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 117 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 118 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 119 : < pop /= 0 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "0001";
CCEN_BAR <= '0';
CC_BAR <= '0';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 10
assert (PL_BAR = '0')
report
"Assert 120 : < PL_BAR /= 0 >" -- Vector No: 10
severity warning;
assert (VECT_BAR = '1')
report
"Assert 121 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 122 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 123 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 124 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 125 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 126 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 127 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 128 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 129 : < clear /= 0 >"
severity warning;
assert (push = '1')
report
"Assert 130 : < push /= 1 >"
severity warning;
assert (pop = '0')
report
"Assert 131 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "0001";
CCEN_BAR <= '0';
CC_BAR <= '0';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 11
assert (PL_BAR = '0')
report
"Assert 132 : < PL_BAR /= 0 >" -- Vector No: 11
severity warning;
assert (VECT_BAR = '1')
report
"Assert 133 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 134 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 135 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 136 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 137 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 138 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 139 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 140 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 141 : < clear /= 0 >"
severity warning;
assert (push = '1')
report
"Assert 142 : < push /= 1 >"
severity warning;
assert (pop = '0')
report
"Assert 143 : < pop /= 0 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "0001";
CCEN_BAR <= '1';
CC_BAR <= '1';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 12
assert (PL_BAR = '0')
report
"Assert 144 : < PL_BAR /= 0 >" -- Vector No: 12
severity warning;
assert (VECT_BAR = '1')
report
"Assert 145 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 146 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 147 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 148 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 149 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 150 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 151 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 152 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 153 : < clear /= 0 >"
severity warning;
assert (push = '1')
report
"Assert 154 : < push /= 1 >"
severity warning;
assert (pop = '0')
report
"Assert 155 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "0001";
CCEN_BAR <= '1';
CC_BAR <= '1';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 13
assert (PL_BAR = '0')
report
"Assert 156 : < PL_BAR /= 0 >" -- Vector No: 13
severity warning;
assert (VECT_BAR = '1')
report
"Assert 157 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 158 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 159 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 160 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 161 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 162 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 163 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 164 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 165 : < clear /= 0 >"
severity warning;
assert (push = '1')
report
"Assert 166 : < push /= 1 >"
severity warning;
assert (pop = '0')
report
"Assert 167 : < pop /= 0 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "0001";
CCEN_BAR <= '1';
CC_BAR <= '0';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 14
assert (PL_BAR = '0')
report
"Assert 168 : < PL_BAR /= 0 >" -- Vector No: 14
severity warning;
assert (VECT_BAR = '1')
report
"Assert 169 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 170 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 171 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 172 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 173 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 174 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 175 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 176 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 177 : < clear /= 0 >"
severity warning;
assert (push = '1')
report
"Assert 178 : < push /= 1 >"
severity warning;
assert (pop = '0')
report
"Assert 179 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "0001";
CCEN_BAR <= '1';
CC_BAR <= '0';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 15
assert (PL_BAR = '0')
report
"Assert 180 : < PL_BAR /= 0 >" -- Vector No: 15
severity warning;
assert (VECT_BAR = '1')
report
"Assert 181 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 182 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 183 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 184 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 185 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 186 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 187 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 188 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 189 : < clear /= 0 >"
severity warning;
assert (push = '1')
report
"Assert 190 : < push /= 1 >"
severity warning;
assert (pop = '0')
report
"Assert 191 : < pop /= 0 >"
severity warning;
wait for 1 ns;
-- ***********************************
-- *********
-- * I = 2 *
-- *********
--------------------------
I <= "0010";
CCEN_BAR <= '0';
CC_BAR <= '1';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 16
assert (PL_BAR = '1')
report
"Assert 192 : < PL_BAR /= 1 >" -- Vector No: 16
severity warning;
assert (VECT_BAR = '1')
report
"Assert 193 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '0')
report
"Assert 194 : < MAP_BAR /= 0 >"
severity warning;
assert (R_sel = '0')
report
"Assert 195 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 196 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 197 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 198 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 199 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 200 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 201 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 202 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 203 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "0010";
CCEN_BAR <= '0';
CC_BAR <= '1';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 17
assert (PL_BAR = '1')
report
"Assert 204 : < PL_BAR /= 1 >" -- Vector No: 17
severity warning;
assert (VECT_BAR = '1')
report
"Assert 205 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '0')
report
"Assert 206 : < MAP_BAR /= 0 >"
severity warning;
assert (R_sel = '0')
report
"Assert 207 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 208 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 209 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 210 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 211 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 212 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 213 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 214 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 215 : < pop /= 0 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "0010";
CCEN_BAR <= '0';
CC_BAR <= '0';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 18
assert (PL_BAR = '1')
report
"Assert 216 : < PL_BAR /= 1 >" -- Vector No: 18
severity warning;
assert (VECT_BAR = '1')
report
"Assert 217 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '0')
report
"Assert 218 : < MAP_BAR /= 0 >"
severity warning;
assert (R_sel = '0')
report
"Assert 219 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 220 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 221 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 222 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 223 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 224 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 225 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 226 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 227 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "0010";
CCEN_BAR <= '0';
CC_BAR <= '0';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 19
assert (PL_BAR = '1')
report
"Assert 228 : < PL_BAR /= 1 >" -- Vector No: 19
severity warning;
assert (VECT_BAR = '1')
report
"Assert 229 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '0')
report
"Assert 230 : < MAP_BAR /= 0 >"
severity warning;
assert (R_sel = '0')
report
"Assert 231 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 232 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 233 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 234 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 235 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 236 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 237 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 238 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 239 : < pop /= 0 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "0010";
CCEN_BAR <= '1';
CC_BAR <= '1';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 20
assert (PL_BAR = '1')
report
"Assert 240 : < PL_BAR /= 1 >" -- Vector No: 20
severity warning;
assert (VECT_BAR = '1')
report
"Assert 241 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '0')
report
"Assert 242 : < MAP_BAR /= 0 >"
severity warning;
assert (R_sel = '0')
report
"Assert 243 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 244 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 245 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 246 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 247 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 248 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 249 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 250 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 251 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "0010";
CCEN_BAR <= '1';
CC_BAR <= '1';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 21
assert (PL_BAR = '1')
report
"Assert 252 : < PL_BAR /= 1 >" -- Vector No: 21
severity warning;
assert (VECT_BAR = '1')
report
"Assert 253 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '0')
report
"Assert 254 : < MAP_BAR /= 0 >"
severity warning;
assert (R_sel = '0')
report
"Assert 255 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 256 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 257 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 258 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 259 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 260 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 261 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 262 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 263 : < pop /= 0 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "0010";
CCEN_BAR <= '1';
CC_BAR <= '0';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 22
assert (PL_BAR = '1')
report
"Assert 264 : < PL_BAR /= 1 >" -- Vector No: 22
severity warning;
assert (VECT_BAR = '1')
report
"Assert 265 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '0')
report
"Assert 266 : < MAP_BAR /= 0 >"
severity warning;
assert (R_sel = '0')
report
"Assert 267 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 268 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 269 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 270 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 271 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 272 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 273 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 274 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 275 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "0010";
CCEN_BAR <= '1';
CC_BAR <= '0';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 23
assert (PL_BAR = '1')
report
"Assert 276 : < PL_BAR /= 1 >" -- Vector No: 23
severity warning;
assert (VECT_BAR = '1')
report
"Assert 277 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '0')
report
"Assert 278 : < MAP_BAR /= 0 >"
severity warning;
assert (R_sel = '0')
report
"Assert 279 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 280 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 281 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 282 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 283 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 284 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 285 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 286 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 287 : < pop /= 0 >"
severity warning;
wait for 1 ns;
-- ***********************************
-- *********
-- * I = 3 *
-- *********
--------------------------
I <= "0011";
CCEN_BAR <= '0';
CC_BAR <= '1';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 24
assert (PL_BAR = '0')
report
"Assert 288 : < PL_BAR /= 0 >" -- Vector No: 24
severity warning;
assert (VECT_BAR = '1')
report
"Assert 289 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 290 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 291 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 292 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 293 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 294 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 295 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 296 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 297 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 298 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 299 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "0011";
CCEN_BAR <= '0';
CC_BAR <= '1';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 25
assert (PL_BAR = '0')
report
"Assert 300 : < PL_BAR /= 0 >" -- Vector No: 25
severity warning;
assert (VECT_BAR = '1')
report
"Assert 301 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 302 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 303 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 304 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 305 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 306 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 307 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 308 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 309 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 310 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 311 : < pop /= 0 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "0011";
CCEN_BAR <= '0';
CC_BAR <= '0';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 26
assert (PL_BAR = '0')
report
"Assert 312 : < PL_BAR /= 0 >" -- Vector No: 26
severity warning;
assert (VECT_BAR = '1')
report
"Assert 313 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 314 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 315 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 316 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 317 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 318 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 319 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 320 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 321 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 322 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 323 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "0011";
CCEN_BAR <= '0';
CC_BAR <= '0';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 27
assert (PL_BAR = '0')
report
"Assert 324 : < PL_BAR /= 0 >" -- Vector No: 27
severity warning;
assert (VECT_BAR = '1')
report
"Assert 325 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 326 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 327 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 328 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 329 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 330 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 331 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 332 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 333 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 334 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 335 : < pop /= 0 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "0011";
CCEN_BAR <= '1';
CC_BAR <= '1';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 28
assert (PL_BAR = '0')
report
"Assert 336 : < PL_BAR /= 0 >" -- Vector No: 28
severity warning;
assert (VECT_BAR = '1')
report
"Assert 337 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 338 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 339 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 340 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 341 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 342 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 343 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 344 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 345 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 346 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 347 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "0011";
CCEN_BAR <= '1';
CC_BAR <= '1';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 29
assert (PL_BAR = '0')
report
"Assert 348 : < PL_BAR /= 0 >" -- Vector No: 29
severity warning;
assert (VECT_BAR = '1')
report
"Assert 349 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 350 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 351 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 352 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 353 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 354 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 355 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 356 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 357 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 358 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 359 : < pop /= 0 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "0011";
CCEN_BAR <= '1';
CC_BAR <= '0';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 30
assert (PL_BAR = '0')
report
"Assert 360 : < PL_BAR /= 0 >" -- Vector No: 30
severity warning;
assert (VECT_BAR = '1')
report
"Assert 361 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 362 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 363 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 364 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 365 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 366 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 367 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 368 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 369 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 370 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 371 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "0011";
CCEN_BAR <= '1';
CC_BAR <= '0';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 31
assert (PL_BAR = '0')
report
"Assert 372 : < PL_BAR /= 0 >" -- Vector No: 31
severity warning;
assert (VECT_BAR = '1')
report
"Assert 373 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 374 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 375 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 376 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 377 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 378 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 379 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 380 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 381 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 382 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 383 : < pop /= 0 >"
severity warning;
wait for 1 ns;
-- ***********************************
-- *********
-- * I = 4 *
-- *********
--------------------------
I <= "0100";
CCEN_BAR <= '0';
CC_BAR <= '1';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 32
assert (PL_BAR = '0')
report
"Assert 384 : < PL_BAR /= 0 >" -- Vector No: 32
severity warning;
assert (VECT_BAR = '1')
report
"Assert 385 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 386 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 387 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 388 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 389 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 390 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 391 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 392 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 393 : < clear /= 0 >"
severity warning;
assert (push = '1')
report
"Assert 394 : < push /= 1 >"
severity warning;
assert (pop = '0')
report
"Assert 395 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "0100";
CCEN_BAR <= '0';
CC_BAR <= '1';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 33
assert (PL_BAR = '0')
report
"Assert 396 : < PL_BAR /= 0 >" -- Vector No: 33
severity warning;
assert (VECT_BAR = '1')
report
"Assert 397 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 398 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 399 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 400 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 401 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 402 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 403 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 404 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 405 : < clear /= 0 >"
severity warning;
assert (push = '1')
report
"Assert 406 : < push /= 1 >"
severity warning;
assert (pop = '0')
report
"Assert 407 : < pop /= 0 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "0100";
CCEN_BAR <= '0';
CC_BAR <= '0';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 34
assert (PL_BAR = '0')
report
"Assert 408 : < PL_BAR /= 0 >" -- Vector No: 34
severity warning;
assert (VECT_BAR = '1')
report
"Assert 409 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 410 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 411 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 412 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 413 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 414 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 415 : < decr /= 0 >"
severity warning;
assert (load = '1')
report
"Assert 416 : < load /= 1 >"
severity warning;
assert (clear = '0')
report
"Assert 417 : < clear /= 0 >"
severity warning;
assert (push = '1')
report
"Assert 418 : < push /= 1 >"
severity warning;
assert (pop = '0')
report
"Assert 419 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "0100";
CCEN_BAR <= '0';
CC_BAR <= '0';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 35
assert (PL_BAR = '0')
report
"Assert 420 : < PL_BAR /= 0 >" -- Vector No: 35
severity warning;
assert (VECT_BAR = '1')
report
"Assert 421 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 422 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 423 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 424 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 425 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 426 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 427 : < decr /= 0 >"
severity warning;
assert (load = '1')
report
"Assert 428 : < load /= 1 >"
severity warning;
assert (clear = '0')
report
"Assert 429 : < clear /= 0 >"
severity warning;
assert (push = '1')
report
"Assert 430 : < push /= 1 >"
severity warning;
assert (pop = '0')
report
"Assert 431 : < pop /= 0 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "0100";
CCEN_BAR <= '1';
CC_BAR <= '1';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 36
assert (PL_BAR = '0')
report
"Assert 432 : < PL_BAR /= 0 >" -- Vector No: 36
severity warning;
assert (VECT_BAR = '1')
report
"Assert 433 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 434 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 435 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 436 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 437 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 438 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 439 : < decr /= 0 >"
severity warning;
assert (load = '1')
report
"Assert 440 : < load /= 1 >"
severity warning;
assert (clear = '0')
report
"Assert 441 : < clear /= 0 >"
severity warning;
assert (push = '1')
report
"Assert 442 : < push /= 1 >"
severity warning;
assert (pop = '0')
report
"Assert 443 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "0100";
CCEN_BAR <= '1';
CC_BAR <= '1';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 37
assert (PL_BAR = '0')
report
"Assert 444 : < PL_BAR /= 0 >" -- Vector No: 37
severity warning;
assert (VECT_BAR = '1')
report
"Assert 445 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 446 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 447 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 448 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 449 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 450 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 451 : < decr /= 0 >"
severity warning;
assert (load = '1')
report
"Assert 452 : < load /= 1 >"
severity warning;
assert (clear = '0')
report
"Assert 453 : < clear /= 0 >"
severity warning;
assert (push = '1')
report
"Assert 454 : < push /= 1 >"
severity warning;
assert (pop = '0')
report
"Assert 455 : < pop /= 0 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "0100";
CCEN_BAR <= '1';
CC_BAR <= '0';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 38
assert (PL_BAR = '0')
report
"Assert 456 : < PL_BAR /= 0 >" -- Vector No: 38
severity warning;
assert (VECT_BAR = '1')
report
"Assert 457 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 458 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 459 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 460 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 461 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 462 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 463 : < decr /= 0 >"
severity warning;
assert (load = '1')
report
"Assert 464 : < load /= 1 >"
severity warning;
assert (clear = '0')
report
"Assert 465 : < clear /= 0 >"
severity warning;
assert (push = '1')
report
"Assert 466 : < push /= 1 >"
severity warning;
assert (pop = '0')
report
"Assert 467 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "0100";
CCEN_BAR <= '1';
CC_BAR <= '0';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 39
assert (PL_BAR = '0')
report
"Assert 468 : < PL_BAR /= 0 >" -- Vector No: 39
severity warning;
assert (VECT_BAR = '1')
report
"Assert 469 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 470 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 471 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 472 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 473 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 474 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 475 : < decr /= 0 >"
severity warning;
assert (load = '1')
report
"Assert 476 : < load /= 1 >"
severity warning;
assert (clear = '0')
report
"Assert 477 : < clear /= 0 >"
severity warning;
assert (push = '1')
report
"Assert 478 : < push /= 1 >"
severity warning;
assert (pop = '0')
report
"Assert 479 : < pop /= 0 >"
severity warning;
wait for 1 ns;
-- ***********************************
-- *********
-- * I = 5 *
-- *********
--------------------------
I <= "0101";
CCEN_BAR <= '0';
CC_BAR <= '1';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 40
assert (PL_BAR = '0')
report
"Assert 480 : < PL_BAR /= 0 >" -- Vector No: 40
severity warning;
assert (VECT_BAR = '1')
report
"Assert 481 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 482 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '1')
report
"Assert 483 : < R_sel /= 1 >"
severity warning;
assert (D_sel = '0')
report
"Assert 484 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 485 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 486 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 487 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 488 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 489 : < clear /= 0 >"
severity warning;
assert (push = '1')
report
"Assert 490 : < push /= 1 >"
severity warning;
assert (pop = '0')
report
"Assert 491 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "0101";
CCEN_BAR <= '0';
CC_BAR <= '1';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 41
assert (PL_BAR = '0')
report
"Assert 492 : < PL_BAR /= 0 >" -- Vector No: 41
severity warning;
assert (VECT_BAR = '1')
report
"Assert 493 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 494 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '1')
report
"Assert 495 : < R_sel /= 1 >"
severity warning;
assert (D_sel = '0')
report
"Assert 496 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 497 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 498 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 499 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 500 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 501 : < clear /= 0 >"
severity warning;
assert (push = '1')
report
"Assert 502 : < push /= 1 >"
severity warning;
assert (pop = '0')
report
"Assert 503 : < pop /= 0 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "0101";
CCEN_BAR <= '0';
CC_BAR <= '0';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 42
assert (PL_BAR = '0')
report
"Assert 504 : < PL_BAR /= 0 >" -- Vector No: 42
severity warning;
assert (VECT_BAR = '1')
report
"Assert 505 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 506 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 507 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 508 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 509 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 510 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 511 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 512 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 513 : < clear /= 0 >"
severity warning;
assert (push = '1')
report
"Assert 514 : < push /= 1 >"
severity warning;
assert (pop = '0')
report
"Assert 515 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "0101";
CCEN_BAR <= '0';
CC_BAR <= '0';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 43
assert (PL_BAR = '0')
report
"Assert 516 : < PL_BAR /= 0 >" -- Vector No: 43
severity warning;
assert (VECT_BAR = '1')
report
"Assert 517 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 518 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 519 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 520 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 521 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 522 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 523 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 524 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 525 : < clear /= 0 >"
severity warning;
assert (push = '1')
report
"Assert 526 : < push /= 1 >"
severity warning;
assert (pop = '0')
report
"Assert 527 : < pop /= 0 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "0101";
CCEN_BAR <= '1';
CC_BAR <= '1';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 44
assert (PL_BAR = '0')
report
"Assert 528 : < PL_BAR /= 0 >" -- Vector No: 44
severity warning;
assert (VECT_BAR = '1')
report
"Assert 529 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 530 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 531 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 532 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 533 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 534 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 535 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 536 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 537 : < clear /= 0 >"
severity warning;
assert (push = '1')
report
"Assert 538 : < push /= 1 >"
severity warning;
assert (pop = '0')
report
"Assert 539 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "0101";
CCEN_BAR <= '1';
CC_BAR <= '1';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 45
assert (PL_BAR = '0')
report
"Assert 540 : < PL_BAR /= 0 >" -- Vector No: 45
severity warning;
assert (VECT_BAR = '1')
report
"Assert 541 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 542 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 543 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 544 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 545 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 546 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 547 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 548 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 549 : < clear /= 0 >"
severity warning;
assert (push = '1')
report
"Assert 550 : < push /= 1 >"
severity warning;
assert (pop = '0')
report
"Assert 551 : < pop /= 0 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "0101";
CCEN_BAR <= '1';
CC_BAR <= '0';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 46
assert (PL_BAR = '0')
report
"Assert 552 : < PL_BAR /= 0 >" -- Vector No: 46
severity warning;
assert (VECT_BAR = '1')
report
"Assert 553 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 554 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 555 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 556 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 557 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 558 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 559 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 560 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 561 : < clear /= 0 >"
severity warning;
assert (push = '1')
report
"Assert 562 : < push /= 1 >"
severity warning;
assert (pop = '0')
report
"Assert 563 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "0101";
CCEN_BAR <= '1';
CC_BAR <= '0';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 47
assert (PL_BAR = '0')
report
"Assert 564 : < PL_BAR /= 0 >" -- Vector No: 47
severity warning;
assert (VECT_BAR = '1')
report
"Assert 565 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 566 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 567 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 568 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 569 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 570 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 571 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 572 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 573 : < clear /= 0 >"
severity warning;
assert (push = '1')
report
"Assert 574 : < push /= 1 >"
severity warning;
assert (pop = '0')
report
"Assert 575 : < pop /= 0 >"
severity warning;
wait for 1 ns;
-- ***********************************
-- *********
-- * I = 6 *
-- *********
--------------------------
I <= "0110";
CCEN_BAR <= '0';
CC_BAR <= '1';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 48
assert (PL_BAR = '1')
report
"Assert 576 : < PL_BAR /= 1 >" -- Vector No: 48
severity warning;
assert (VECT_BAR = '0')
report
"Assert 577 : < VECT_BAR /= 0 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 578 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 579 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 580 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 581 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 582 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 583 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 584 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 585 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 586 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 587 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "0110";
CCEN_BAR <= '0';
CC_BAR <= '1';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 49
assert (PL_BAR = '1')
report
"Assert 588 : < PL_BAR /= 1 >" -- Vector No: 49
severity warning;
assert (VECT_BAR = '0')
report
"Assert 589 : < VECT_BAR /= 0 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 590 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 591 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 592 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 593 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 594 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 595 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 596 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 597 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 598 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 599 : < pop /= 0 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "0110";
CCEN_BAR <= '0';
CC_BAR <= '0';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 50
assert (PL_BAR = '1')
report
"Assert 600 : < PL_BAR /= 1 >" -- Vector No: 50
severity warning;
assert (VECT_BAR = '0')
report
"Assert 601 : < VECT_BAR /= 0 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 602 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 603 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 604 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 605 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 606 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 607 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 608 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 609 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 610 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 611 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "0110";
CCEN_BAR <= '0';
CC_BAR <= '0';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 51
assert (PL_BAR = '1')
report
"Assert 612 : < PL_BAR /= 1 >" -- Vector No: 51
severity warning;
assert (VECT_BAR = '0')
report
"Assert 613 : < VECT_BAR /= 0 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 614 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 615 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 616 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 617 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 618 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 619 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 620 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 621 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 622 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 623 : < pop /= 0 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "0110";
CCEN_BAR <= '1';
CC_BAR <= '1';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 52
assert (PL_BAR = '1')
report
"Assert 624 : < PL_BAR /= 1 >" -- Vector No: 52
severity warning;
assert (VECT_BAR = '0')
report
"Assert 625 : < VECT_BAR /= 0 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 626 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 627 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 628 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 629 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 630 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 631 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 632 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 633 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 634 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 635 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "0110";
CCEN_BAR <= '1';
CC_BAR <= '1';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 53
assert (PL_BAR = '1')
report
"Assert 636 : < PL_BAR /= 1 >" -- Vector No: 53
severity warning;
assert (VECT_BAR = '0')
report
"Assert 637 : < VECT_BAR /= 0 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 638 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 639 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 640 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 641 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 642 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 643 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 644 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 645 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 646 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 647 : < pop /= 0 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "0110";
CCEN_BAR <= '1';
CC_BAR <= '0';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 54
assert (PL_BAR = '1')
report
"Assert 648 : < PL_BAR /= 1 >" -- Vector No: 54
severity warning;
assert (VECT_BAR = '0')
report
"Assert 649 : < VECT_BAR /= 0 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 650 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 651 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 652 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 653 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 654 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 655 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 656 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 657 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 658 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 659 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "0110";
CCEN_BAR <= '1';
CC_BAR <= '0';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 55
assert (PL_BAR = '1')
report
"Assert 660 : < PL_BAR /= 1 >" -- Vector No: 55
severity warning;
assert (VECT_BAR = '0')
report
"Assert 661 : < VECT_BAR /= 0 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 662 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 663 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 664 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 665 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 666 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 667 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 668 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 669 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 670 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 671 : < pop /= 0 >"
severity warning;
wait for 1 ns;
-- ***********************************
-- *********
-- * I = 7 *
-- *********
--------------------------
I <= "0111";
CCEN_BAR <= '0';
CC_BAR <= '1';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 56
assert (PL_BAR = '0')
report
"Assert 672 : < PL_BAR /= 0 >" -- Vector No: 56
severity warning;
assert (VECT_BAR = '1')
report
"Assert 673 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 674 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '1')
report
"Assert 675 : < R_sel /= 1 >"
severity warning;
assert (D_sel = '0')
report
"Assert 676 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 677 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 678 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 679 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 680 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 681 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 682 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 683 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "0111";
CCEN_BAR <= '0';
CC_BAR <= '1';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 57
assert (PL_BAR = '0')
report
"Assert 684 : < PL_BAR /= 0 >" -- Vector No: 57
severity warning;
assert (VECT_BAR = '1')
report
"Assert 685 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 686 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '1')
report
"Assert 687 : < R_sel /= 1 >"
severity warning;
assert (D_sel = '0')
report
"Assert 688 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 689 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 690 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 691 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 692 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 693 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 694 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 695 : < pop /= 0 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "0111";
CCEN_BAR <= '0';
CC_BAR <= '0';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 58
assert (PL_BAR = '0')
report
"Assert 696 : < PL_BAR /= 0 >" -- Vector No: 58
severity warning;
assert (VECT_BAR = '1')
report
"Assert 697 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 698 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 699 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 700 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 701 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 702 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 703 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 704 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 705 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 706 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 707 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "0111";
CCEN_BAR <= '0';
CC_BAR <= '0';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 59
assert (PL_BAR = '0')
report
"Assert 708 : < PL_BAR /= 0 >" -- Vector No: 59
severity warning;
assert (VECT_BAR = '1')
report
"Assert 709 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 710 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 711 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 712 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 713 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 714 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 715 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 716 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 717 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 718 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 719 : < pop /= 0 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "0111";
CCEN_BAR <= '1';
CC_BAR <= '1';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 60
assert (PL_BAR = '0')
report
"Assert 720 : < PL_BAR /= 0 >" -- Vector No: 60
severity warning;
assert (VECT_BAR = '1')
report
"Assert 721 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 722 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 723 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 724 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 725 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 726 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 727 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 728 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 729 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 730 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 731 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "0111";
CCEN_BAR <= '1';
CC_BAR <= '1';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 61
assert (PL_BAR = '0')
report
"Assert 732 : < PL_BAR /= 0 >" -- Vector No: 61
severity warning;
assert (VECT_BAR = '1')
report
"Assert 733 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 734 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 735 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 736 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 737 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 738 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 739 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 740 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 741 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 742 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 743 : < pop /= 0 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "0111";
CCEN_BAR <= '1';
CC_BAR <= '0';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 62
assert (PL_BAR = '0')
report
"Assert 744 : < PL_BAR /= 0 >" -- Vector No: 62
severity warning;
assert (VECT_BAR = '1')
report
"Assert 745 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 746 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 747 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 748 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 749 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 750 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 751 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 752 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 753 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 754 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 755 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "0111";
CCEN_BAR <= '1';
CC_BAR <= '0';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 63
assert (PL_BAR = '0')
report
"Assert 756 : < PL_BAR /= 0 >" -- Vector No: 63
severity warning;
assert (VECT_BAR = '1')
report
"Assert 757 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 758 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 759 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 760 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 761 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 762 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 763 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 764 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 765 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 766 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 767 : < pop /= 0 >"
severity warning;
wait for 1 ns;
-- ***********************************
-- *********
-- * I = 8 *
-- *********
--------------------------
I <= "1000";
CCEN_BAR <= '0';
CC_BAR <= '1';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 64
assert (PL_BAR = '0')
report
"Assert 768 : < PL_BAR /= 0 >" -- Vector No: 64
severity warning;
assert (VECT_BAR = '1')
report
"Assert 769 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 770 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 771 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 772 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 773 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '1')
report
"Assert 774 : < stack_sel /= 1 >"
severity warning;
assert (decr = '1')
report
"Assert 775 : < decr /= 1 >"
severity warning;
assert (load = '0')
report
"Assert 776 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 777 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 778 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 779 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "1000";
CCEN_BAR <= '0';
CC_BAR <= '1';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 65
assert (PL_BAR = '0')
report
"Assert 780 : < PL_BAR /= 0 >" -- Vector No: 65
severity warning;
assert (VECT_BAR = '1')
report
"Assert 781 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 782 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 783 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 784 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 785 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 786 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 787 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 788 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 789 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 790 : < push /= 0 >"
severity warning;
assert (pop = '1')
report
"Assert 791 : < pop /= 1 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "1000";
CCEN_BAR <= '0';
CC_BAR <= '0';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 66
assert (PL_BAR = '0')
report
"Assert 792 : < PL_BAR /= 0 >" -- Vector No: 66
severity warning;
assert (VECT_BAR = '1')
report
"Assert 793 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 794 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 795 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 796 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 797 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '1')
report
"Assert 798 : < stack_sel /= 1 >"
severity warning;
assert (decr = '1')
report
"Assert 799 : < decr /= 1 >"
severity warning;
assert (load = '0')
report
"Assert 800 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 801 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 802 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 803 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "1000";
CCEN_BAR <= '0';
CC_BAR <= '0';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 67
assert (PL_BAR = '0')
report
"Assert 804 : < PL_BAR /= 0 >" -- Vector No: 67
severity warning;
assert (VECT_BAR = '1')
report
"Assert 805 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 806 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 807 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 808 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 809 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 810 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 811 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 812 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 813 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 814 : < push /= 0 >"
severity warning;
assert (pop = '1')
report
"Assert 815 : < pop /= 1 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "1000";
CCEN_BAR <= '1';
CC_BAR <= '1';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 68
assert (PL_BAR = '0')
report
"Assert 816 : < PL_BAR /= 0 >" -- Vector No: 68
severity warning;
assert (VECT_BAR = '1')
report
"Assert 817 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 818 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 819 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 820 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 821 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '1')
report
"Assert 822 : < stack_sel /= 1 >"
severity warning;
assert (decr = '1')
report
"Assert 823 : < decr /= 1 >"
severity warning;
assert (load = '0')
report
"Assert 824 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 825 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 826 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 827 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "1000";
CCEN_BAR <= '1';
CC_BAR <= '1';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 69
assert (PL_BAR = '0')
report
"Assert 828 : < PL_BAR /= 0 >" -- Vector No: 69
severity warning;
assert (VECT_BAR = '1')
report
"Assert 829 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 830 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 831 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 832 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 833 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 834 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 835 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 836 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 837 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 838 : < push /= 0 >"
severity warning;
assert (pop = '1')
report
"Assert 839 : < pop /= 1 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "1000";
CCEN_BAR <= '1';
CC_BAR <= '0';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 70
assert (PL_BAR = '0')
report
"Assert 840 : < PL_BAR /= 0 >" -- Vector No: 70
severity warning;
assert (VECT_BAR = '1')
report
"Assert 841 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 842 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 843 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 844 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 845 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '1')
report
"Assert 846 : < stack_sel /= 1 >"
severity warning;
assert (decr = '1')
report
"Assert 847 : < decr /= 1 >"
severity warning;
assert (load = '0')
report
"Assert 848 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 849 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 850 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 851 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "1000";
CCEN_BAR <= '1';
CC_BAR <= '0';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 71
assert (PL_BAR = '0')
report
"Assert 852 : < PL_BAR /= 0 >" -- Vector No: 71
severity warning;
assert (VECT_BAR = '1')
report
"Assert 853 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 854 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 855 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 856 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 857 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 858 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 859 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 860 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 861 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 862 : < push /= 0 >"
severity warning;
assert (pop = '1')
report
"Assert 863 : < pop /= 1 >"
severity warning;
wait for 1 ns;
-- ***********************************
-- *********
-- * I = 9 *
-- *********
--------------------------
I <= "1001";
CCEN_BAR <= '0';
CC_BAR <= '1';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 72
assert (PL_BAR = '0')
report
"Assert 864 : < PL_BAR /= 0 >" -- Vector No: 72
severity warning;
assert (VECT_BAR = '1')
report
"Assert 865 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 866 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 867 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 868 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 869 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 870 : < stack_sel /= 0 >"
severity warning;
assert (decr = '1')
report
"Assert 871 : < decr /= 1 >"
severity warning;
assert (load = '0')
report
"Assert 872 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 873 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 874 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 875 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "1001";
CCEN_BAR <= '0';
CC_BAR <= '1';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 73
assert (PL_BAR = '0')
report
"Assert 876 : < PL_BAR /= 0 >" -- Vector No: 73
severity warning;
assert (VECT_BAR = '1')
report
"Assert 877 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 878 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 879 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 880 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 881 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 882 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 883 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 884 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 885 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 886 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 887 : < pop /= 0 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "1001";
CCEN_BAR <= '0';
CC_BAR <= '0';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 74
assert (PL_BAR = '0')
report
"Assert 888 : < PL_BAR /= 0 >" -- Vector No: 74
severity warning;
assert (VECT_BAR = '1')
report
"Assert 889 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 890 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 891 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 892 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 893 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 894 : < stack_sel /= 0 >"
severity warning;
assert (decr = '1')
report
"Assert 895 : < decr /= 1 >"
severity warning;
assert (load = '0')
report
"Assert 896 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 897 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 898 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 899 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "1001";
CCEN_BAR <= '0';
CC_BAR <= '0';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 75
assert (PL_BAR = '0')
report
"Assert 900 : < PL_BAR /= 0 >" -- Vector No: 75
severity warning;
assert (VECT_BAR = '1')
report
"Assert 901 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 902 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 903 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 904 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 905 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 906 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 907 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 908 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 909 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 910 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 911 : < pop /= 0 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "1001";
CCEN_BAR <= '1';
CC_BAR <= '1';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 76
assert (PL_BAR = '0')
report
"Assert 912 : < PL_BAR /= 0 >" -- Vector No: 76
severity warning;
assert (VECT_BAR = '1')
report
"Assert 913 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 914 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 915 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 916 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 917 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 918 : < stack_sel /= 0 >"
severity warning;
assert (decr = '1')
report
"Assert 919 : < decr /= 1 >"
severity warning;
assert (load = '0')
report
"Assert 920 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 921 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 922 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 923 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "1001";
CCEN_BAR <= '1';
CC_BAR <= '1';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 77
assert (PL_BAR = '0')
report
"Assert 924 : < PL_BAR /= 0 >" -- Vector No: 77
severity warning;
assert (VECT_BAR = '1')
report
"Assert 925 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 926 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 927 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 928 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 929 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 930 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 931 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 932 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 933 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 934 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 935 : < pop /= 0 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "1001";
CCEN_BAR <= '1';
CC_BAR <= '0';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 78
assert (PL_BAR = '0')
report
"Assert 936 : < PL_BAR /= 0 >" -- Vector No: 78
severity warning;
assert (VECT_BAR = '1')
report
"Assert 937 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 938 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 939 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 940 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 941 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 942 : < stack_sel /= 0 >"
severity warning;
assert (decr = '1')
report
"Assert 943 : < decr /= 1 >"
severity warning;
assert (load = '0')
report
"Assert 944 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 945 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 946 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 947 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "1001";
CCEN_BAR <= '1';
CC_BAR <= '0';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 79
assert (PL_BAR = '0')
report
"Assert 948 : < PL_BAR /= 0 >" -- Vector No: 79
severity warning;
assert (VECT_BAR = '1')
report
"Assert 949 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 950 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 951 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 952 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 953 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 954 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 955 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 956 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 957 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 958 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 959 : < pop /= 0 >"
severity warning;
wait for 1 ns;
-- ***********************************
-- **********
-- * I = 10 *
-- **********
--------------------------
I <= "1010";
CCEN_BAR <= '0';
CC_BAR <= '1';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 80
assert (PL_BAR = '0')
report
"Assert 960 : < PL_BAR /= 0 >" -- Vector No: 80
severity warning;
assert (VECT_BAR = '1')
report
"Assert 961 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 962 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 963 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 964 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 965 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 966 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 967 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 968 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 969 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 970 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 971 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "1010";
CCEN_BAR <= '0';
CC_BAR <= '1';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 81
assert (PL_BAR = '0')
report
"Assert 972 : < PL_BAR /= 0 >" -- Vector No: 81
severity warning;
assert (VECT_BAR = '1')
report
"Assert 973 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 974 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 975 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 976 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 977 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 978 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 979 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 980 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 981 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 982 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 983 : < pop /= 0 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "1010";
CCEN_BAR <= '0';
CC_BAR <= '0';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 82
assert (PL_BAR = '0')
report
"Assert 984 : < PL_BAR /= 0 >" -- Vector No: 82
severity warning;
assert (VECT_BAR = '1')
report
"Assert 985 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 986 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 987 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 988 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 989 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '1')
report
"Assert 990 : < stack_sel /= 1 >"
severity warning;
assert (decr = '0')
report
"Assert 991 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 992 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 993 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 994 : < push /= 0 >"
severity warning;
assert (pop = '1')
report
"Assert 995 : < pop /= 1 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "1010";
CCEN_BAR <= '0';
CC_BAR <= '0';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 83
assert (PL_BAR = '0')
report
"Assert 996 : < PL_BAR /= 0 >" -- Vector No: 83
severity warning;
assert (VECT_BAR = '1')
report
"Assert 997 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 998 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 999 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 1000 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 1001 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '1')
report
"Assert 1002 : < stack_sel /= 1 >"
severity warning;
assert (decr = '0')
report
"Assert 1003 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 1004 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 1005 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 1006 : < push /= 0 >"
severity warning;
assert (pop = '1')
report
"Assert 1007 : < pop /= 1 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "1010";
CCEN_BAR <= '1';
CC_BAR <= '1';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 84
assert (PL_BAR = '0')
report
"Assert 1008 : < PL_BAR /= 0 >" -- Vector No: 84
severity warning;
assert (VECT_BAR = '1')
report
"Assert 1009 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 1010 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 1011 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 1012 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 1013 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '1')
report
"Assert 1014 : < stack_sel /= 1 >"
severity warning;
assert (decr = '0')
report
"Assert 1015 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 1016 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 1017 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 1018 : < push /= 0 >"
severity warning;
assert (pop = '1')
report
"Assert 1019 : < pop /= 1 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "1010";
CCEN_BAR <= '1';
CC_BAR <= '1';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 85
assert (PL_BAR = '0')
report
"Assert 1020 : < PL_BAR /= 0 >" -- Vector No: 85
severity warning;
assert (VECT_BAR = '1')
report
"Assert 1021 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 1022 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 1023 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 1024 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 1025 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '1')
report
"Assert 1026 : < stack_sel /= 1 >"
severity warning;
assert (decr = '0')
report
"Assert 1027 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 1028 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 1029 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 1030 : < push /= 0 >"
severity warning;
assert (pop = '1')
report
"Assert 1031 : < pop /= 1 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "1010";
CCEN_BAR <= '1';
CC_BAR <= '0';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 86
assert (PL_BAR = '0')
report
"Assert 1032 : < PL_BAR /= 0 >" -- Vector No: 86
severity warning;
assert (VECT_BAR = '1')
report
"Assert 1033 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 1034 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 1035 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 1036 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 1037 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '1')
report
"Assert 1038 : < stack_sel /= 1 >"
severity warning;
assert (decr = '0')
report
"Assert 1039 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 1040 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 1041 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 1042 : < push /= 0 >"
severity warning;
assert (pop = '1')
report
"Assert 1043 : < pop /= 1 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "1010";
CCEN_BAR <= '1';
CC_BAR <= '0';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 87
assert (PL_BAR = '0')
report
"Assert 1044 : < PL_BAR /= 0 >" -- Vector No: 87
severity warning;
assert (VECT_BAR = '1')
report
"Assert 1045 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 1046 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 1047 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 1048 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 1049 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '1')
report
"Assert 1050 : < stack_sel /= 1 >"
severity warning;
assert (decr = '0')
report
"Assert 1051 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 1052 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 1053 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 1054 : < push /= 0 >"
severity warning;
assert (pop = '1')
report
"Assert 1055 : < pop /= 1 >"
severity warning;
wait for 1 ns;
-- ***********************************
-- **********
-- * I = 11 *
-- **********
--------------------------
I <= "1011";
CCEN_BAR <= '0';
CC_BAR <= '1';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 88
assert (PL_BAR = '0')
report
"Assert 1056 : < PL_BAR /= 0 >" -- Vector No: 88
severity warning;
assert (VECT_BAR = '1')
report
"Assert 1057 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 1058 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 1059 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 1060 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 1061 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 1062 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 1063 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 1064 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 1065 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 1066 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 1067 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "1011";
CCEN_BAR <= '0';
CC_BAR <= '1';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 89
assert (PL_BAR = '0')
report
"Assert 1068 : < PL_BAR /= 0 >" -- Vector No: 89
severity warning;
assert (VECT_BAR = '1')
report
"Assert 1069 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 1070 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 1071 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 1072 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 1073 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 1074 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 1075 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 1076 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 1077 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 1078 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 1079 : < pop /= 0 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "1011";
CCEN_BAR <= '0';
CC_BAR <= '0';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 90
assert (PL_BAR = '0')
report
"Assert 1080 : < PL_BAR /= 0 >" -- Vector No: 90
severity warning;
assert (VECT_BAR = '1')
report
"Assert 1081 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 1082 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 1083 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 1084 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 1085 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 1086 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 1087 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 1088 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 1089 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 1090 : < push /= 0 >"
severity warning;
assert (pop = '1')
report
"Assert 1091 : < pop /= 1 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "1011";
CCEN_BAR <= '0';
CC_BAR <= '0';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 91
assert (PL_BAR = '0')
report
"Assert 1092 : < PL_BAR /= 0 >" -- Vector No: 91
severity warning;
assert (VECT_BAR = '1')
report
"Assert 1093 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 1094 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 1095 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 1096 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 1097 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 1098 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 1099 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 1100 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 1101 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 1102 : < push /= 0 >"
severity warning;
assert (pop = '1')
report
"Assert 1103 : < pop /= 1 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "1011";
CCEN_BAR <= '1';
CC_BAR <= '1';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 92
assert (PL_BAR = '0')
report
"Assert 1104 : < PL_BAR /= 0 >" -- Vector No: 92
severity warning;
assert (VECT_BAR = '1')
report
"Assert 1105 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 1106 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 1107 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 1108 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 1109 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 1110 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 1111 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 1112 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 1113 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 1114 : < push /= 0 >"
severity warning;
assert (pop = '1')
report
"Assert 1115 : < pop /= 1 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "1011";
CCEN_BAR <= '1';
CC_BAR <= '1';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 93
assert (PL_BAR = '0')
report
"Assert 1116 : < PL_BAR /= 0 >" -- Vector No: 93
severity warning;
assert (VECT_BAR = '1')
report
"Assert 1117 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 1118 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 1119 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 1120 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 1121 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 1122 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 1123 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 1124 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 1125 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 1126 : < push /= 0 >"
severity warning;
assert (pop = '1')
report
"Assert 1127 : < pop /= 1 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "1011";
CCEN_BAR <= '1';
CC_BAR <= '0';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 94
assert (PL_BAR = '0')
report
"Assert 1128 : < PL_BAR /= 0 >" -- Vector No: 94
severity warning;
assert (VECT_BAR = '1')
report
"Assert 1129 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 1130 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 1131 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 1132 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 1133 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 1134 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 1135 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 1136 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 1137 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 1138 : < push /= 0 >"
severity warning;
assert (pop = '1')
report
"Assert 1139 : < pop /= 1 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "1011";
CCEN_BAR <= '1';
CC_BAR <= '0';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 95
assert (PL_BAR = '0')
report
"Assert 1140 : < PL_BAR /= 0 >" -- Vector No: 95
severity warning;
assert (VECT_BAR = '1')
report
"Assert 1141 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 1142 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 1143 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 1144 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 1145 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 1146 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 1147 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 1148 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 1149 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 1150 : < push /= 0 >"
severity warning;
assert (pop = '1')
report
"Assert 1151 : < pop /= 1 >"
severity warning;
wait for 1 ns;
-- ***********************************
-- **********
-- * I = 12 *
-- **********
--------------------------
I <= "1100";
CCEN_BAR <= '0';
CC_BAR <= '1';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 96
assert (PL_BAR = '0')
report
"Assert 1152 : < PL_BAR /= 0 >" -- Vector No: 96
severity warning;
assert (VECT_BAR = '1')
report
"Assert 1153 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 1154 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 1155 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 1156 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 1157 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 1158 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 1159 : < decr /= 0 >"
severity warning;
assert (load = '1')
report
"Assert 1160 : < load /= 1 >"
severity warning;
assert (clear = '0')
report
"Assert 1161 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 1162 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 1163 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "1100";
CCEN_BAR <= '0';
CC_BAR <= '1';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 97
assert (PL_BAR = '0')
report
"Assert 1164 : < PL_BAR /= 0 >" -- Vector No: 97
severity warning;
assert (VECT_BAR = '1')
report
"Assert 1165 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 1166 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 1167 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 1168 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 1169 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 1170 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 1171 : < decr /= 0 >"
severity warning;
assert (load = '1')
report
"Assert 1172 : < load /= 1 >"
severity warning;
assert (clear = '0')
report
"Assert 1173 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 1174 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 1175 : < pop /= 0 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "1100";
CCEN_BAR <= '0';
CC_BAR <= '0';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 98
assert (PL_BAR = '0')
report
"Assert 1176 : < PL_BAR /= 0 >" -- Vector No: 98
severity warning;
assert (VECT_BAR = '1')
report
"Assert 1177 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 1178 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 1179 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 1180 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 1181 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 1182 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 1183 : < decr /= 0 >"
severity warning;
assert (load = '1')
report
"Assert 1184 : < load /= 1 >"
severity warning;
assert (clear = '0')
report
"Assert 1185 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 1186 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 1187 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "1100";
CCEN_BAR <= '0';
CC_BAR <= '0';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 99
assert (PL_BAR = '0')
report
"Assert 1188 : < PL_BAR /= 0 >" -- Vector No: 99
severity warning;
assert (VECT_BAR = '1')
report
"Assert 1189 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 1190 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 1191 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 1192 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 1193 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 1194 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 1195 : < decr /= 0 >"
severity warning;
assert (load = '1')
report
"Assert 1196 : < load /= 1 >"
severity warning;
assert (clear = '0')
report
"Assert 1197 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 1198 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 1199 : < pop /= 0 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "1100";
CCEN_BAR <= '1';
CC_BAR <= '1';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 100
assert (PL_BAR = '0')
report
"Assert 1200 : < PL_BAR /= 0 >" -- Vector No: 100
severity warning;
assert (VECT_BAR = '1')
report
"Assert 1201 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 1202 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 1203 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 1204 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 1205 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 1206 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 1207 : < decr /= 0 >"
severity warning;
assert (load = '1')
report
"Assert 1208 : < load /= 1 >"
severity warning;
assert (clear = '0')
report
"Assert 1209 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 1210 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 1211 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "1100";
CCEN_BAR <= '1';
CC_BAR <= '1';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 101
assert (PL_BAR = '0')
report
"Assert 1212 : < PL_BAR /= 0 >" -- Vector No: 101
severity warning;
assert (VECT_BAR = '1')
report
"Assert 1213 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 1214 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 1215 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 1216 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 1217 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 1218 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 1219 : < decr /= 0 >"
severity warning;
assert (load = '1')
report
"Assert 1220 : < load /= 1 >"
severity warning;
assert (clear = '0')
report
"Assert 1221 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 1222 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 1223 : < pop /= 0 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "1100";
CCEN_BAR <= '1';
CC_BAR <= '0';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 102
assert (PL_BAR = '0')
report
"Assert 1224 : < PL_BAR /= 0 >" -- Vector No: 102
severity warning;
assert (VECT_BAR = '1')
report
"Assert 1225 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 1226 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 1227 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 1228 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 1229 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 1230 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 1231 : < decr /= 0 >"
severity warning;
assert (load = '1')
report
"Assert 1232 : < load /= 1 >"
severity warning;
assert (clear = '0')
report
"Assert 1233 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 1234 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 1235 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "1100";
CCEN_BAR <= '1';
CC_BAR <= '0';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 103
assert (PL_BAR = '0')
report
"Assert 1236 : < PL_BAR /= 0 >" -- Vector No: 103
severity warning;
assert (VECT_BAR = '1')
report
"Assert 1237 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 1238 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 1239 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 1240 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 1241 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 1242 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 1243 : < decr /= 0 >"
severity warning;
assert (load = '1')
report
"Assert 1244 : < load /= 1 >"
severity warning;
assert (clear = '0')
report
"Assert 1245 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 1246 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 1247 : < pop /= 0 >"
severity warning;
wait for 1 ns;
-- ***********************************
-- **********
-- * I = 13 *
-- **********
--------------------------
I <= "1101";
CCEN_BAR <= '0';
CC_BAR <= '1';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 104
assert (PL_BAR = '0')
report
"Assert 1248 : < PL_BAR /= 0 >" -- Vector No: 104
severity warning;
assert (VECT_BAR = '1')
report
"Assert 1249 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 1250 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 1251 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 1252 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 1253 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '1')
report
"Assert 1254 : < stack_sel /= 1 >"
severity warning;
assert (decr = '0')
report
"Assert 1255 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 1256 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 1257 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 1258 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 1259 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "1101";
CCEN_BAR <= '0';
CC_BAR <= '1';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 105
assert (PL_BAR = '0')
report
"Assert 1260 : < PL_BAR /= 0 >" -- Vector No: 105
severity warning;
assert (VECT_BAR = '1')
report
"Assert 1261 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 1262 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 1263 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 1264 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 1265 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '1')
report
"Assert 1266 : < stack_sel /= 1 >"
severity warning;
assert (decr = '0')
report
"Assert 1267 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 1268 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 1269 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 1270 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 1271 : < pop /= 0 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "1101";
CCEN_BAR <= '0';
CC_BAR <= '0';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 106
assert (PL_BAR = '0')
report
"Assert 1272 : < PL_BAR /= 0 >" -- Vector No: 106
severity warning;
assert (VECT_BAR = '1')
report
"Assert 1273 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 1274 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 1275 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 1276 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 1277 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 1278 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 1279 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 1280 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 1281 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 1282 : < push /= 0 >"
severity warning;
assert (pop = '1')
report
"Assert 1283 : < pop /= 1 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "1101";
CCEN_BAR <= '0';
CC_BAR <= '0';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 107
assert (PL_BAR = '0')
report
"Assert 1284 : < PL_BAR /= 0 >" -- Vector No: 107
severity warning;
assert (VECT_BAR = '1')
report
"Assert 1285 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 1286 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 1287 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 1288 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 1289 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 1290 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 1291 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 1292 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 1293 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 1294 : < push /= 0 >"
severity warning;
assert (pop = '1')
report
"Assert 1295 : < pop /= 1 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "1101";
CCEN_BAR <= '1';
CC_BAR <= '1';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 108
assert (PL_BAR = '0')
report
"Assert 1296 : < PL_BAR /= 0 >" -- Vector No: 108
severity warning;
assert (VECT_BAR = '1')
report
"Assert 1297 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 1298 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 1299 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 1300 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 1301 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 1302 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 1303 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 1304 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 1305 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 1306 : < push /= 0 >"
severity warning;
assert (pop = '1')
report
"Assert 1307 : < pop /= 1 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "1101";
CCEN_BAR <= '1';
CC_BAR <= '1';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 109
assert (PL_BAR = '0')
report
"Assert 1308 : < PL_BAR /= 0 >" -- Vector No: 109
severity warning;
assert (VECT_BAR = '1')
report
"Assert 1309 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 1310 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 1311 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 1312 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 1313 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 1314 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 1315 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 1316 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 1317 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 1318 : < push /= 0 >"
severity warning;
assert (pop = '1')
report
"Assert 1319 : < pop /= 1 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "1101";
CCEN_BAR <= '1';
CC_BAR <= '0';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 110
assert (PL_BAR = '0')
report
"Assert 1320 : < PL_BAR /= 0 >" -- Vector No: 110
severity warning;
assert (VECT_BAR = '1')
report
"Assert 1321 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 1322 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 1323 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 1324 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 1325 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 1326 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 1327 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 1328 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 1329 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 1330 : < push /= 0 >"
severity warning;
assert (pop = '1')
report
"Assert 1331 : < pop /= 1 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "1101";
CCEN_BAR <= '1';
CC_BAR <= '0';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 111
assert (PL_BAR = '0')
report
"Assert 1332 : < PL_BAR /= 0 >" -- Vector No: 111
severity warning;
assert (VECT_BAR = '1')
report
"Assert 1333 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 1334 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 1335 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 1336 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 1337 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 1338 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 1339 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 1340 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 1341 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 1342 : < push /= 0 >"
severity warning;
assert (pop = '1')
report
"Assert 1343 : < pop /= 1 >"
severity warning;
wait for 1 ns;
-- ***********************************
-- **********
-- * I = 14 *
-- **********
--------------------------
I <= "1110";
CCEN_BAR <= '0';
CC_BAR <= '1';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 112
assert (PL_BAR = '0')
report
"Assert 1344 : < PL_BAR /= 0 >" -- Vector No: 112
severity warning;
assert (VECT_BAR = '1')
report
"Assert 1345 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 1346 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 1347 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 1348 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 1349 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 1350 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 1351 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 1352 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 1353 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 1354 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 1355 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "1110";
CCEN_BAR <= '0';
CC_BAR <= '1';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 113
assert (PL_BAR = '0')
report
"Assert 1356 : < PL_BAR /= 0 >" -- Vector No: 113
severity warning;
assert (VECT_BAR = '1')
report
"Assert 1357 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 1358 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 1359 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 1360 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 1361 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 1362 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 1363 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 1364 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 1365 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 1366 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 1367 : < pop /= 0 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "1110";
CCEN_BAR <= '0';
CC_BAR <= '0';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 114
assert (PL_BAR = '0')
report
"Assert 1368 : < PL_BAR /= 0 >" -- Vector No: 114
severity warning;
assert (VECT_BAR = '1')
report
"Assert 1369 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 1370 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 1371 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 1372 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 1373 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 1374 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 1375 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 1376 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 1377 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 1378 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 1379 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "1110";
CCEN_BAR <= '0';
CC_BAR <= '0';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 115
assert (PL_BAR = '0')
report
"Assert 1380 : < PL_BAR /= 0 >" -- Vector No: 115
severity warning;
assert (VECT_BAR = '1')
report
"Assert 1381 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 1382 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 1383 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 1384 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 1385 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 1386 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 1387 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 1388 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 1389 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 1390 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 1391 : < pop /= 0 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "1110";
CCEN_BAR <= '1';
CC_BAR <= '1';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 116
assert (PL_BAR = '0')
report
"Assert 1392 : < PL_BAR /= 0 >" -- Vector No: 116
severity warning;
assert (VECT_BAR = '1')
report
"Assert 1393 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 1394 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 1395 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 1396 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 1397 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 1398 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 1399 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 1400 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 1401 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 1402 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 1403 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "1110";
CCEN_BAR <= '1';
CC_BAR <= '1';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 117
assert (PL_BAR = '0')
report
"Assert 1404 : < PL_BAR /= 0 >" -- Vector No: 117
severity warning;
assert (VECT_BAR = '1')
report
"Assert 1405 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 1406 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 1407 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 1408 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 1409 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 1410 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 1411 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 1412 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 1413 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 1414 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 1415 : < pop /= 0 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "1110";
CCEN_BAR <= '1';
CC_BAR <= '0';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 118
assert (PL_BAR = '0')
report
"Assert 1416 : < PL_BAR /= 0 >" -- Vector No: 118
severity warning;
assert (VECT_BAR = '1')
report
"Assert 1417 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 1418 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 1419 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 1420 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 1421 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 1422 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 1423 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 1424 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 1425 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 1426 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 1427 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "1110";
CCEN_BAR <= '1';
CC_BAR <= '0';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 119
assert (PL_BAR = '0')
report
"Assert 1428 : < PL_BAR /= 0 >" -- Vector No: 119
severity warning;
assert (VECT_BAR = '1')
report
"Assert 1429 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 1430 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 1431 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 1432 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 1433 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 1434 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 1435 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 1436 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 1437 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 1438 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 1439 : < pop /= 0 >"
severity warning;
wait for 1 ns;
-- ***********************************
-- **********
-- * I = 15 *
-- **********
--------------------------
I <= "1111";
CCEN_BAR <= '0';
CC_BAR <= '1';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 120
assert (PL_BAR = '0')
report
"Assert 1440 : < PL_BAR /= 0 >" -- Vector No: 120
severity warning;
assert (VECT_BAR = '1')
report
"Assert 1441 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 1442 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 1443 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 1444 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 1445 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '1')
report
"Assert 1446 : < stack_sel /= 1 >"
severity warning;
assert (decr = '1')
report
"Assert 1447 : < decr /= 1 >"
severity warning;
assert (load = '0')
report
"Assert 1448 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 1449 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 1450 : < push /= 0 >"
severity warning;
assert (pop = '0')
report
"Assert 1451 : < pop /= 0 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "1111";
CCEN_BAR <= '0';
CC_BAR <= '1';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 121
assert (PL_BAR = '0')
report
"Assert 1452 : < PL_BAR /= 0 >" -- Vector No: 121
severity warning;
assert (VECT_BAR = '1')
report
"Assert 1453 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 1454 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 1455 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '1')
report
"Assert 1456 : < D_sel /= 1 >"
severity warning;
assert (uPC_sel = '0')
report
"Assert 1457 : < uPC_sel /= 0 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 1458 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 1459 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 1460 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 1461 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 1462 : < push /= 0 >"
severity warning;
assert (pop = '1')
report
"Assert 1463 : < pop /= 1 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "1111";
CCEN_BAR <= '0';
CC_BAR <= '0';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 122
assert (PL_BAR = '0')
report
"Assert 1464 : < PL_BAR /= 0 >" -- Vector No: 122
severity warning;
assert (VECT_BAR = '1')
report
"Assert 1465 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 1466 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 1467 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 1468 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 1469 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 1470 : < stack_sel /= 0 >"
severity warning;
assert (decr = '1')
report
"Assert 1471 : < decr /= 1 >"
severity warning;
assert (load = '0')
report
"Assert 1472 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 1473 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 1474 : < push /= 0 >"
severity warning;
assert (pop = '1')
report
"Assert 1475 : < pop /= 1 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "1111";
CCEN_BAR <= '0';
CC_BAR <= '0';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 123
assert (PL_BAR = '0')
report
"Assert 1476 : < PL_BAR /= 0 >" -- Vector No: 123
severity warning;
assert (VECT_BAR = '1')
report
"Assert 1477 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 1478 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 1479 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 1480 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 1481 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 1482 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 1483 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 1484 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 1485 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 1486 : < push /= 0 >"
severity warning;
assert (pop = '1')
report
"Assert 1487 : < pop /= 1 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "1111";
CCEN_BAR <= '1';
CC_BAR <= '1';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 124
assert (PL_BAR = '0')
report
"Assert 1488 : < PL_BAR /= 0 >" -- Vector No: 124
severity warning;
assert (VECT_BAR = '1')
report
"Assert 1489 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 1490 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 1491 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 1492 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 1493 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 1494 : < stack_sel /= 0 >"
severity warning;
assert (decr = '1')
report
"Assert 1495 : < decr /= 1 >"
severity warning;
assert (load = '0')
report
"Assert 1496 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 1497 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 1498 : < push /= 0 >"
severity warning;
assert (pop = '1')
report
"Assert 1499 : < pop /= 1 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "1111";
CCEN_BAR <= '1';
CC_BAR <= '1';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 125
assert (PL_BAR = '0')
report
"Assert 1500 : < PL_BAR /= 0 >" -- Vector No: 125
severity warning;
assert (VECT_BAR = '1')
report
"Assert 1501 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 1502 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 1503 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 1504 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 1505 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 1506 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 1507 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 1508 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 1509 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 1510 : < push /= 0 >"
severity warning;
assert (pop = '1')
report
"Assert 1511 : < pop /= 1 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
I <= "1111";
CCEN_BAR <= '1';
CC_BAR <= '0';
Rzero_bar <= '1';
wait for 1 ns; -- Cycle No: 126
assert (PL_BAR = '0')
report
"Assert 1512 : < PL_BAR /= 0 >" -- Vector No: 126
severity warning;
assert (VECT_BAR = '1')
report
"Assert 1513 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 1514 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 1515 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 1516 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 1517 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 1518 : < stack_sel /= 0 >"
severity warning;
assert (decr = '1')
report
"Assert 1519 : < decr /= 1 >"
severity warning;
assert (load = '0')
report
"Assert 1520 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 1521 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 1522 : < push /= 0 >"
severity warning;
assert (pop = '1')
report
"Assert 1523 : < pop /= 1 >"
severity warning;
wait for 1 ns;
--------------------------
I <= "1111";
CCEN_BAR <= '1';
CC_BAR <= '0';
Rzero_bar <= '0';
wait for 1 ns; -- Cycle No: 127
assert (PL_BAR = '0')
report
"Assert 1524 : < PL_BAR /= 0 >" -- Vector No: 127
severity warning;
assert (VECT_BAR = '1')
report
"Assert 1525 : < VECT_BAR /= 1 >"
severity warning;
assert (MAP_BAR = '1')
report
"Assert 1526 : < MAP_BAR /= 1 >"
severity warning;
assert (R_sel = '0')
report
"Assert 1527 : < R_sel /= 0 >"
severity warning;
assert (D_sel = '0')
report
"Assert 1528 : < D_sel /= 0 >"
severity warning;
assert (uPC_sel = '1')
report
"Assert 1529 : < uPC_sel /= 1 >"
severity warning;
assert (stack_sel = '0')
report
"Assert 1530 : < stack_sel /= 0 >"
severity warning;
assert (decr = '0')
report
"Assert 1531 : < decr /= 0 >"
severity warning;
assert (load = '0')
report
"Assert 1532 : < load /= 0 >"
severity warning;
assert (clear = '0')
report
"Assert 1533 : < clear /= 0 >"
severity warning;
assert (push = '0')
report
"Assert 1534 : < push /= 0 >"
severity warning;
assert (pop = '1')
report
"Assert 1535 : < pop /= 1 >"
severity warning;
wait for 1 ns;
-- ***********************************
--------------------------
end process;
end AA;
| mit | 45b6dcd584029214649b8cb7ae24d15b | 0.574514 | 2.750466 | false | false | false | false |
besm6/micro-besm | tests/2901/vhdl/funct_blocks_alg_beh/components/output_and_shifter/op_sh.vhdl | 1 | 1,756 | --------------------------------------------------------------------------------
--
-- AM2901 Benchmark output_shifter
--
-- Source: AMD data book
--
-- VHDL Benchmark author Indraneel Ghosh
-- University Of California, Irvine, CA 92717
--
-- Developed on Jan 1, 1992
--
-- Verification Information:
--
-- Verified By whom? Date Simulator
-- -------- ------------ -------- ------------
-- Syntax yes Champaka Ramachandran Sept 17, 92 ZYCAD
-- Functionality yes Champaka Ramachandran Sept 17, 92 ZYCAD
--------------------------------------------------------------------------------
--library ZYCAD;
use work.TYPES.all;
use work.MVL7_functions.all;
entity output_and_shifter is
port (
I : in MVL7_vector(8 downto 0);
A, F, Q : in MVL7_vector(3 downto 0);
OEbar : in MVL7;
Y : out MVL7_vector(3 downto 0);
RAM0, RAM3, Q0, Q3 : out MVL7
);
end output_and_shifter;
architecture output_and_shifter of output_and_shifter is
begin
-- GENERATE DATA OUTPUT "Y"
Y <= A when (( I(8 downto 6) = "010") and ( OEbar = '0')) else
F when (not(( I(8 downto 6) = "010")) and ( OEbar = '0')) else
"ZZZZ";
-- GENERATE BIDIRECTIONAL SHIFTER SIGNALS.
RAM0 <= F(0) when ( I(8) = '1') and ( I(7) = '0' ) else
'Z';
RAM3 <= F(3) when ( I(8) = '1') and ( I(7) = '1' ) else
'Z';
Q3 <= Q(3) when ( I(8) = '1') and ( I(7) = '1') else
'Z';
Q0 <= Q(0) when ( I(8) = '1') and ( I(7) = '0') else
'Z';
end output_and_shifter;
------------------------------------------------ | mit | 0e18111865d24d8b7d8ef6e4d239121b | 0.428246 | 3.512 | false | false | false | false |
varunnagpaal/Digital-Hardware-Modelling | vhdl/alu/top_syn.vhdl | 1 | 11,125 |
library IEEE;
use IEEE.std_logic_1164.all;
package CONV_PACK_top is
-- define attributes
attribute ENUM_ENCODING : STRING;
end CONV_PACK_top;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_top.all;
entity top is
port( in_data_a, in_data_b : in std_logic_vector (3 downto 0);
in_data_carry : in std_logic; in_ctrl : in std_logic_vector (2 downto
0); out_data_c : out std_logic_vector (3 downto 0); out_data_carry :
out std_logic; out_data_comp : out std_logic_vector (1 downto 0));
end top;
architecture SYN_behavioral of top is
component inv
port( inb : in std_logic; outb : out std_logic);
end component;
component nor3
port( a, b, c : in std_logic; outb : out std_logic);
end component;
component nand2
port( a, b : in std_logic; outb : out std_logic);
end component;
component oai22
port( a, b, c, d : in std_logic; outb : out std_logic);
end component;
component nor2
port( a, b : in std_logic; outb : out std_logic);
end component;
component nand3
port( a, b, c : in std_logic; outb : out std_logic);
end component;
component xor2
port( a, b : in std_logic; outb : out std_logic);
end component;
component oai12
port( b, c, a : in std_logic; outb : out std_logic);
end component;
component aoi22
port( a, b, c, d : in std_logic; outb : out std_logic);
end component;
component nand4
port( a, b, c, d : in std_logic; outb : out std_logic);
end component;
component aoi12
port( b, c, a : in std_logic; outb : out std_logic);
end component;
signal n106, n107, n108, n109, n110, n111, n112, n113, n114, n115, n116,
n117, n118, n119, n120, n121, n122, n123, n124, n125, n126, n127, n128,
n129, n130, n131, n132, n133, n134, n135, n136, n137, n138, n139, n140,
n141, n142, n143, n144, n145, n146, n147, n148, n149, n150, n151, n152,
n153, n154, n155, n156, n157, n158, n159, n160, n161, n162, n163, n164,
n165, n166, n167, n168, n169, n170, n171, n172, n173, n174, n175, n176,
n177, n178, n179, n180, n181, n182, n183, n184, n185, n186, n187, n188,
n189, n190, n191, n192, n193, n194, n195, n196, n197, n198, n199, n200,
n201, n202, n203, n204 : std_logic;
begin
out_data_comp(1) <= '0';
U105 : nand2 port map( a => n106, b => n107, outb => out_data_comp(0));
U106 : nand4 port map( a => in_ctrl(0), b => n108, c => in_ctrl(1), d =>
n109, outb => n107);
U107 : nand4 port map( a => n110, b => n111, c => n112, d => in_ctrl(2),
outb => n106);
U108 : inv port map( inb => n113, outb => n111);
U109 : nor2 port map( a => n114, b => in_ctrl(0), outb => n113);
U110 : oai12 port map( b => n108, c => n114, a => in_ctrl(0), outb => n110);
U111 : nand2 port map( a => n115, b => n116, outb => n114);
U112 : oai12 port map( b => n117, c => n118, a => n119, outb => n115);
U113 : aoi12 port map( b => n120, c => n121, a => n122, outb => n118);
U114 : nand3 port map( a => n123, b => n124, c => in_data_b(0), outb => n120
);
U115 : nand2 port map( a => n119, b => n125, outb => n108);
U116 : oai12 port map( b => n126, c => n127, a => n116, outb => n125);
U117 : aoi12 port map( b => n123, c => n128, a => n122, outb => n126);
U118 : nand3 port map( a => n121, b => n129, c => in_data_a(0), outb => n128
);
U119 : nand3 port map( a => n130, b => n131, c => n132, outb =>
out_data_carry);
U120 : aoi22 port map( a => in_data_b(3), b => n133, c => n134, d =>
in_data_carry, outb => n132);
U121 : nand3 port map( a => in_data_a(3), b => n135, c => n136, outb => n131
);
U122 : nand2 port map( a => n137, b => n138, outb => n135);
U123 : nand2 port map( a => n139, b => n140, outb => n130);
U124 : oai12 port map( b => in_data_a(3), c => n141, a => n116, outb => n140
);
U125 : nand2 port map( a => n142, b => n143, outb => out_data_c(3));
U126 : aoi22 port map( a => n144, b => n133, c => n145, d => n146, outb =>
n143);
U127 : inv port map( inb => n147, outb => n145);
U128 : aoi22 port map( a => n139, b => n141, c => n137, d => n136, outb =>
n147);
U129 : oai22 port map( a => n141, b => n148, c => n137, d => n149, outb =>
n133);
U130 : aoi22 port map( a => in_data_a(2), b => n150, c => n151, d =>
in_data_b(2), outb => n137);
U131 : nand2 port map( a => n152, b => n153, outb => n151);
U132 : aoi12 port map( b => n154, c => n155, a => n117, outb => n141);
U133 : inv port map( inb => n156, outb => n117);
U134 : inv port map( inb => n146, outb => n144);
U135 : nand2 port map( a => n116, b => n119, outb => n146);
U136 : nand2 port map( a => in_data_a(3), b => n138, outb => n119);
U137 : inv port map( inb => n157, outb => n116);
U138 : nor2 port map( a => n138, b => in_data_a(3), outb => n157);
U139 : inv port map( inb => in_data_b(3), outb => n138);
U140 : aoi22 port map( a => n158, b => n159, c => in_data_a(3), d => n160,
outb => n142);
U141 : oai12 port map( b => n161, c => n162, a => n163, outb => n159);
U142 : oai22 port map( a => in_data_a(0), b => n129, c => in_data_b(0), d =>
in_data_a(1), outb => n162);
U143 : nand4 port map( a => n164, b => n165, c => n166, d => n167, outb =>
out_data_c(2));
U144 : aoi22 port map( a => n168, b => n158, c => in_data_a(2), d => n160,
outb => n167);
U145 : aoi22 port map( a => in_data_b(0), b => n123, c => n169, d => n129,
outb => n168);
U146 : nand2 port map( a => in_data_a(0), b => in_data_b(1), outb => n169);
U147 : nand2 port map( a => n170, b => n136, outb => n166);
U148 : xor2 port map( a => n122, b => n150, outb => n170);
U149 : inv port map( inb => n152, outb => n150);
U150 : oai22 port map( a => in_data_a(1), b => n171, c => in_data_b(1), d =>
n172, outb => n152);
U151 : inv port map( inb => n173, outb => n172);
U152 : nand2 port map( a => n171, b => in_data_a(1), outb => n173);
U153 : nand3 port map( a => n174, b => in_data_a(3), c => n175, outb => n165
);
U154 : nand2 port map( a => n139, b => n176, outb => n164);
U155 : xor2 port map( a => n122, b => n154, outb => n176);
U156 : inv port map( inb => n177, outb => n154);
U157 : aoi12 port map( b => n178, c => n123, a => n179, outb => n177);
U158 : nand2 port map( a => n155, b => n156, outb => n122);
U159 : nand2 port map( a => in_data_b(2), b => n153, outb => n156);
U160 : inv port map( inb => n127, outb => n155);
U161 : nor2 port map( a => n153, b => in_data_b(2), outb => n127);
U162 : inv port map( inb => in_data_a(2), outb => n153);
U163 : nand4 port map( a => n180, b => n181, c => n182, d => n183, outb =>
out_data_c(1));
U164 : aoi22 port map( a => n175, b => n184, c => in_data_a(1), d => n160,
outb => n183);
U165 : nand2 port map( a => n163, b => n185, outb => n184);
U166 : nand3 port map( a => in_data_b(1), b => n129, c => in_data_a(3), outb
=> n185);
U167 : nand2 port map( a => n174, b => in_data_a(2), outb => n163);
U168 : nand2 port map( a => n136, b => n186, outb => n182);
U169 : xor2 port map( a => n171, b => n187, outb => n186);
U170 : oai12 port map( b => n188, c => n124, a => n189, outb => n171);
U171 : nand3 port map( a => n174, b => in_data_a(0), c => n158, outb => n181
);
U172 : nor2 port map( a => n129, b => in_data_b(1), outb => n174);
U173 : nand2 port map( a => n139, b => n190, outb => n180);
U174 : xor2 port map( a => n178, b => n187, outb => n190);
U175 : nand2 port map( a => n123, b => n121, outb => n187);
U176 : inv port map( inb => n179, outb => n121);
U177 : nor2 port map( a => n161, b => in_data_a(1), outb => n179);
U178 : oai12 port map( b => in_data_a(0), c => n188, a => n189, outb => n178
);
U179 : nand3 port map( a => n191, b => n192, c => n193, outb =>
out_data_c(0));
U180 : nand2 port map( a => in_data_a(0), b => n160, outb => n193);
U181 : inv port map( inb => n194, outb => n160);
U182 : nor2 port map( a => n195, b => n134, outb => n194);
U183 : nor3 port map( a => in_ctrl(1), b => in_ctrl(2), c => in_ctrl(0),
outb => n134);
U184 : nor3 port map( a => in_data_b(0), b => in_data_b(1), c => n196, outb
=> n195);
U185 : nor2 port map( a => n158, b => n175, outb => n196);
U186 : nor3 port map( a => n109, b => n197, c => n112, outb => n158);
U187 : nand3 port map( a => n198, b => n199, c => n200, outb => n192);
U188 : nand2 port map( a => n149, b => n148, outb => n200);
U189 : inv port map( inb => n139, outb => n148);
U190 : nor3 port map( a => in_ctrl(0), b => in_ctrl(2), c => n112, outb =>
n139);
U191 : inv port map( inb => n136, outb => n149);
U192 : nor3 port map( a => in_ctrl(1), b => in_ctrl(2), c => n197, outb =>
n136);
U193 : inv port map( inb => in_ctrl(0), outb => n197);
U194 : nand2 port map( a => n201, b => n124, outb => n199);
U195 : inv port map( inb => in_data_a(0), outb => n124);
U196 : xor2 port map( a => in_data_carry, b => n129, outb => n201);
U197 : nand3 port map( a => n202, b => n189, c => in_data_a(0), outb => n198
);
U198 : nand2 port map( a => in_data_carry, b => in_data_b(0), outb => n189);
U199 : inv port map( inb => n188, outb => n202);
U200 : nor2 port map( a => in_data_carry, b => in_data_b(0), outb => n188);
U201 : nand2 port map( a => n175, b => n203, outb => n191);
U202 : oai22 port map( a => n129, b => n123, c => n161, d => n204, outb =>
n203);
U203 : oai22 port map( a => in_data_b(0), b => in_data_a(2), c =>
in_data_a(3), d => n129, outb => n204);
U204 : nand2 port map( a => in_data_a(1), b => n161, outb => n123);
U205 : inv port map( inb => in_data_b(1), outb => n161);
U206 : inv port map( inb => in_data_b(0), outb => n129);
U207 : nor3 port map( a => n109, b => in_ctrl(0), c => n112, outb => n175);
U208 : inv port map( inb => in_ctrl(1), outb => n112);
U209 : inv port map( inb => in_ctrl(2), outb => n109);
end SYN_behavioral; | mit | 82264aa0705f93a9de77308067a4cbd4 | 0.49591 | 2.731402 | false | false | false | false |
kuba-moo/VHDL-lib | reg_ro.vhd | 2 | 2,277 | -- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.math_real.all;
use work.globals.all;
-- read only register
entity reg_ro is
generic (REG_BYTES : integer;
REG_ADDR_BASE : reg_addr_t);
port (Clk : in std_logic;
Rst : in std_logic;
RegBusI : in reg_bus_t;
RegBusO : out reg_bus_t;
Value : in std_logic_vector(REG_BYTES*8 - 1 downto 0));
end reg_ro;
-- Operation:
-- Report @Value to the bus when address matches.
-- WARNING: this version of ro-register is NOT atomic.
architecture Behavioral of reg_ro is
constant OFFSET_LEN : integer := integer(ceil(log2(real(REG_BYTES))));
constant REG_BITS : integer := REG_BYTES*8;
subtype OffsetRange is natural range OFFSET_LEN - 1 downto 0;
subtype AddrRange is natural range REG_ADDR_W - 1 downto OFFSET_LEN;
signal offset : integer;
signal bus_addr, reg_addr : std_logic_vector(AddrRange);
begin
offset <= CONV_integer(RegBusI.addr(OffsetRange));
bus_addr <= RegBusI.addr(AddrRange);
reg_addr <= REG_ADDR_BASE(AddrRange);
read_out : process (Clk)
begin
if rising_edge(Clk) then
RegBusO <= RegBusI;
if bus_addr = reg_addr and RegBusI.wr = '0' then
RegBusO.data <= Value(7 + offset*8 downto offset*8);
end if;
if Rst = '1' then
RegBusO.addr <= reg_addr_invl;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 5c881a70b031ae75da158c4c750b783d | 0.649539 | 3.696429 | false | false | false | false |
varunnagpaal/Digital-Hardware-Modelling | vhdl/filter/iir/bq/filter_misc_functions.vhd | 1 | 8,790 | library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.filter_shared_package.all;
entity filter_extra_functions is
generic
(
MAC_FILTER_CH : natural := MC; -- MAC operations per channel for Main filter operation
CHANNELS : natural := C;
ENVELOPE_EN : natural := ENV;
ENV_MAC_ID : natural := ENV_MAC;
SETZERO_EN : natural := SETZ;
RMS_CH_EN : natural := RMS; -- Enable flag for RMS function. 0-disabled 1- enabled.
MEAN_CH_EN : natural := MEAN -- Enable flag for MEAN function. 0-disabled 1- enabled.
);
port
(
-- Input ports
clk : in std_logic;
rstn : in std_logic;
cnt_mac : in std_logic_vector(natural(ceil(log2(real(MAC_FILTER_CH + RMS_CH_EN + MEAN_CH_EN))))-1 downto 0);
cnt_ch : in std_logic_vector(natural(ceil(log2(real(CHANNELS))))-1 downto 0);
cnt_delay_mac : in std_logic_vector(natural(ceil(log2(real(MAC_FILTER_CH + RMS_CH_EN + MEAN_CH_EN))))-1 downto 0);
cnt_delay_ch : in std_logic_vector(natural(ceil(log2(real(CHANNELS))))-1 downto 0);
give_rms : in std_logic;
give_mean : in std_logic;
envelope : in std_logic_vector(CHANNELS-1 downto 0);
set_zero : in std_logic_vector(CHANNELS-1 downto 0);
valid_delay : in std_logic;
output : in std_logic;
-- Output ports
source_rms_valid : out std_logic:= '0';
source_mean_valid : out std_logic:= '0';
zero_y : out std_logic:= '0';
zero_acc_misc : out std_logic;
is_abs : out std_logic:= '0';
cond : out std_logic
);
end filter_extra_functions;
architecture filter_extra_functions_arch of filter_extra_functions is
signal rms_output_s, mean_output_s, cond_s : std_logic;
signal tmp_cnt_delay_ch_s : unsigned(cnt_delay_ch'range);
-- Envelope enable signal and absolute flag
signal envelope_en_s, is_abs_s : std_logic;
-- Set Zero signals
signal set_zero_s, set_zero_1_s, set_zero_2_s, set_zero_3_s, set_zero_4_s : std_logic_vector(CHANNELS-1 downto 0);
-- Valid Signal registers
signal source_rms_valid_s : std_logic;
signal source_mean_valid_s : std_logic;
begin
tmp_cnt_delay_ch_s <= unsigned(cnt_delay_ch);
-- RMS and MEAN Functionality
Cond_Zero_Rms_Mean: if RMS_CH_EN /= 0 and MEAN_CH_EN /= 0 generate
-- valid RMS and MEAN output if requested
Rms_Mean_Memless : process(cnt_delay_mac,give_rms,give_mean)
variable tmp_cnt_delay_mac : natural;
variable tmp_rms_output, tmp_mean_output : std_logic;
begin
tmp_cnt_delay_mac := to_integer(unsigned(cnt_delay_mac));
tmp_rms_output := '0';
tmp_mean_output := '0';
if tmp_cnt_delay_mac = MAC_FILTER_CH then
tmp_rms_output := give_rms;
end if;
if tmp_cnt_delay_mac = MAC_FILTER_CH+1 then
tmp_mean_output := give_mean;
end if;
rms_output_s <= tmp_rms_output;
mean_output_s <= tmp_mean_output;
zero_acc_misc <= tmp_rms_output or tmp_mean_output;
end process Rms_Mean_Memless;
cond_s <= '1' when (output = '1') or (rms_output_s = '1') or (mean_output_s = '1') else
'0';
end generate;
Cond_Zero_Rms: if RMS_CH_EN /= 0 and MEAN_CH_EN = 0 generate
-- valid RMS output if requested
Rms_Memless : process(cnt_delay_mac,give_rms)
variable tmp_cnt_delay_mac : natural;
variable tmp_rms_output : std_logic;
begin
tmp_cnt_delay_mac := to_integer(unsigned(cnt_delay_mac));
tmp_rms_output := '0';
if tmp_cnt_delay_mac = MAC_FILTER_CH then
tmp_rms_output := give_rms;
end if;
rms_output_s <= tmp_rms_output;
zero_acc_misc <= tmp_rms_output;
end process Rms_Memless;
cond_s <= '1' when (output = '1') or (rms_output_s = '1') else
'0';
end generate;
Cond_Zero_Mean: if RMS_CH_EN = 0 and MEAN_CH_EN /= 0 generate
-- valid MEAN output if requested
Mean_Memless : process(cnt_delay_mac,give_mean)
variable tmp_cnt_delay_mac : natural;
variable tmp_mean_output : std_logic;
begin
tmp_cnt_delay_mac := to_integer(unsigned(cnt_delay_mac));
tmp_mean_output := '0';
if tmp_cnt_delay_mac = MAC_FILTER_CH then
tmp_mean_output := give_mean;
end if;
mean_output_s <= tmp_mean_output;
zero_acc_misc <= tmp_mean_output;
end process Mean_Memless;
cond_s <= '1' when (output = '1') or (mean_output_s = '1') else
'0';
end generate;
Cond_Zero: if RMS_CH_EN = 0 and MEAN_CH_EN = 0 generate
cond_s <= '1' when (output = '1') else
'0';
zero_acc_misc <= '0';
end generate;
cond <= cond_s;
Rms_Valid_Memzing : if RMS_CH_EN /= 0 generate
process (clk, rstn) is
begin
if (rstn = '0') then
source_rms_valid_s <= '0';
source_rms_valid <= '0';
elsif (rising_edge(clk)) then
source_rms_valid_s <= '0';
if (cond_s = '1' and tmp_cnt_delay_ch_s < CHANNELS) then
source_rms_valid_s <= rms_output_s;
end if;
source_rms_valid <= source_rms_valid_s;
end if;
end process;
end generate Rms_Valid_Memzing;
Mean_Valid_Memzing : if MEAN_CH_EN /= 0 generate
process (clk, rstn) is
begin
if (rstn = '0') then
source_mean_valid_s <= '0';
source_mean_valid <= '0';
elsif (rising_edge(clk)) then
source_mean_valid_s <= '0';
if (cond_s = '1' and tmp_cnt_delay_ch_s < CHANNELS) then
source_mean_valid_s <= mean_output_s;
end if;
source_mean_valid <= source_mean_valid_s;
end if;
end process;
end generate Mean_Valid_Memzing;
-- Envelope Functionality
Env : if ENVELOPE_EN /= 0 generate
-- Generate envelope enable signal and absolute flag
Env_Abs_Memless : process(cnt_ch,cnt_mac,envelope)
variable tmp_cnt_ch, tmp_cnt_mac : natural;
variable tmp_is_abs : std_logic;
begin
tmp_cnt_ch := to_integer(unsigned(cnt_ch));
tmp_cnt_mac := to_integer(unsigned(cnt_mac));
tmp_is_abs := '0';
if(tmp_cnt_mac >= ENV_MAC_ID and tmp_cnt_mac <= ENV_MAC_ID + 2) then
tmp_is_abs := '1';
end if;
envelope_en_s <= envelope(tmp_cnt_ch);
is_abs_s <= tmp_is_abs;
end process Env_Abs_Memless;
-- Register the absolute flag according to envelope select
process (clk, rstn) is
begin
if (rstn = '0') then
is_abs <= '0';
elsif (clk = '1' and clk'event) then
is_abs <= '0';
if (envelope_en_s = '1') then
is_abs <= is_abs_s;
end if;
end if;
end process;
end generate Env;
-- Set-Zero Functionality
ZeroY : if SETZERO_EN /= 0 generate
process (clk, rstn) is
begin
if (rstn = '0') then
set_zero_s <= (others => '0');
set_zero_1_s <= (others => '0');
set_zero_2_s <= (others => '0');
set_zero_3_s <= (others => '0');
set_zero_4_s <= (others => '0');
elsif (rising_edge(clk)) then
if (output = '1' and tmp_cnt_delay_ch_s = CHANNELS-1) then
set_zero_1_s <= set_zero;
set_zero_2_s <= set_zero_1_s;
set_zero_3_s <= set_zero_2_s;
set_zero_4_s <= set_zero_3_s;
set_zero_s <= set_zero or set_zero_1_s or set_zero_2_s or set_zero_3_s or set_zero_4_s;
end if;
end if;
end process;
zero_y <= set_zero_s(to_integer(unsigned(cnt_delay_ch)));
end generate ZeroY;
end filter_extra_functions_arch; | mit | bd1af4df08dbdfae9c93bc07d8041a19 | 0.505347 | 3.545785 | false | false | false | false |
MartinCura/SistDig-TP4 | old/rotador/rotador3d.vhd | 1 | 1,880 | library ieee;
use ieee.std_logic_1164.all;
library work;
use work.cordic_lib.all;
---use work.float_pkg.all;
--library ieee_proposed;
--use ieee_proposed.float_pkg.all;
library floatfixlib;
use floatfixlib.float_pkg.all;
-- Rota un punto 3D, usando 3 veces el algoritmo CORDIC y rotando según los ángulos para cada eje
entity rotador3d is
generic(
N_BITS: integer := 32
);
port(
ena : in std_logic := '0'; -- Enable para rotar
pos_in: in t_pos; -- Posición de un punto a rotar a la pos correcta
alfa, beta, gama: in t_float; -- Ángulo de rotación en x, y, z respectivamente
pos_rotada: out t_pos -- Posición una vez rotada (o la original si ena = 0)
);
end;
architecture rotador3d_arq of rotador3d is
signal pos_1, pos_2, pos_3 : t_pos;
signal vec_1a, vec_1b, vec_2a, vec_2b, vec_3a, vec_3b : t_vec;
begin
-- Rotación en x
vec_1a(1) <= pos_in(2);
vec_1a(2) <= pos_in(3);
process(vec_1a, alfa)
begin
if (alfa /= 0) then
vec_1b <= cordic(vec_1a, alfa);
end if;
end process;
pos_1(1) <= vec_1b(1) when (alfa /= 0) else pos_in(2);
pos_1(2) <= vec_1b(2) when (alfa /= 0) else pos_in(3);
pos_1(3) <= pos_in(1);
-- Rotación en y
vec_2a(1) <= pos_1(2);
vec_2a(2) <= pos_1(3);
process(vec_2a, beta)
begin
if (beta /= 0) then
vec_2b <= cordic(vec_2a, beta);
end if;
end process;
pos_2(1) <= vec_2b(1) when (beta /= 0) else pos_1(2);
pos_2(2) <= vec_2b(2) when (beta /= 0) else pos_1(3);
pos_2(3) <= pos_1(1);
-- Rotación en z
vec_3a(1) <= pos_2(2);
vec_3a(2) <= pos_2(3);
process(vec_3a, gama)
begin
if (gama /= 0) then
vec_3b <= cordic(vec_3a, gama);
end if;
end process;
pos_3(1) <= vec_3b(1) when (gama /= 0) else pos_2(2);
pos_3(2) <= vec_3b(2) when (gama /= 0) else pos_2(3);
pos_3(3) <= pos_2(1);
-- Salida
pos_rotada <= pos_3 when ena = '1' else pos_in;
end;
| gpl-3.0 | e2f905b7322cc2955cfe2952b8a03c43 | 0.602886 | 2.214201 | false | false | false | false |
natsutan/NPU | fpga_implement/npu8/npu8.cache/ip/d74462b9dbd19694/mult_17x16_sim_netlist.vhdl | 1 | 637,075 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
-- Date : Sat Jan 21 14:43:33 2017
-- Host : natu-OMEN-by-HP-Laptop running 64-bit Ubuntu 16.04.1 LTS
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ mult_17x16_sim_netlist.vhdl
-- Design : mult_17x16
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xcku035-fbva676-3-e
-- --------------------------------------------------------------------------------
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner="Cadence Design Systems.", key_keyname="cds_rsa_key", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=64)
`protect key_block
fPF16TcpNgM9dNC6nyb4WjUK+7bY8P+I62AEEiiM/KOMhIKuPOHBoWeWL2UjxSNO68WLeYIZp8lA
I7rHN/CieA==
`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`protect key_block
E6OKJxjnDRUVVFwAhrQMAtoyRVVpuMKsXlca4m9CcIt6QI8vnYN0tf7gH3uVuxZ90322B7kUeFw5
Pu0UeqAoBaSyysHuDqXazxHy7oyk4BIWChvcrp7LULlVLcL76obtSwsXi1ORVmpdTi5b+AcD+WUo
OP1PSFj5jpodG+LwXm4=
`protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-1", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`protect key_block
x+agogSsgbiI6PGyBpMY8RQCDzLctIr3EaG23mH5kJHlNmNKNolnP54yJ8Y7nIFi6yl6tlyOLMoF
/kxU0pyFmIj8QM0/MArMxPTiemXbDLS2VKtonyK9dDH7VbjFnRWwzK0Ngkas0+nbW3TqGPAY98x3
251QPjQoZCw3A7W9PDc=
`protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
KNs7hA49BKKrboRSEkqIGldOa3ndCnhjRkSn8lL1xFfKUn+p+Wbc09ogKV6YYnPU/RaF1LbzyoE4
udPSNea4bST+08IjO5GAxXqUugcig44J+hzpGKmh7oO0TuyNbYq1CnYcsZXaD9vsmNYz8fBDoW2S
VK/mYa21mBKTOuTdQ1yp3wi73aJ1G9N6Ngt7ovDUrjyd5oNxxNlvWU8JkJDinbEnci0qjZ3Wu9Wg
y44pHUXf6xqwFYJpZ1ZcGRKl83P8p74+pLzt19lw9TPlTfKI++IowVjb6wo36ztNDJS0QjQE5Riv
hwbPU/Bt3S82MVCY5NAA6bKC/8NnoWMbmX8Wiw==
`protect key_keyowner="ATRENTA", key_keyname="ATR-SG-2015-RSA-3", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
QaRubtGbYrmCghuFdQuTgTEtoVYYLcPnD5z0C7mo18fwCG17qy0y8mj8xWiwE6bo49IP1/JXSIw7
rTBwHFOVrmbm926sWNrF1r3IHB83C5cstprQ1om7vnkw9XX87SjkscphhkrHmi08jjzW4qX96m61
/ymclz5TlAocMQJGz/jwscvIMOrrbuH4SkWQOLQnRfx9GIOv5Y7PM+w/wuDSeFXsAXz7Ahq3/qmU
cylNfSufW7/zfN4RZB4u+d28AXsuFe03aSF1dpW+uBK1xtNZccvj9h9NMN0cuwxt8ZUlLJw8l6e2
hqRfTTZl1F4qnnrJu6w8h8uEGrmgnQG1AW0epg==
`protect key_keyowner="Xilinx", key_keyname="xilinx_2016_05", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
XXj6Nc59BeA5Kznlx14IKravf7ohERw7h0fbO7pT7/HsiPDCWh2DlTGpFUcnbNZslPN2RfE0nJNX
WMzLQtaHK4Bm6kxY71OsXEKm7MAIjEdLwOMtJTtlZrbm7chBbSxcW6sjWvI36jk5De3Yct9Ao1py
DpQ9NICUtRTwGG8SAiRkAXRh2Jv3rKvnookQrlVxIkNRSBMSgbwuTbq1ze/KMUZebBWwJNUVIC9r
RV/i9wjYXBOeCCUk+cGDC5uSpwdLXYV9ZxhQUU6C1ufAaK2m4OIUeBqPc2ski2O0qQYQ67c35k50
ynO8H9PTEROPEOn5c37S7feU+36OcOOAsVBTBA==
`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-PREC-RSA", key_method="rsa"
`protect encoding = (enctype="base64", line_length=76, bytes=256)
`protect key_block
OY2dawYF9tInyCemgCe6QEMkC/7TSGzSBNJnYt/Gc7EF5dCGsTH9VXcGbZ2mUocKtRfoAWdRBBEm
bYfl6x6FbPUhb0/G1cVlVEQ4o/H18n5hF99JS0/fz0SNPWznJYrrCaGAm92JkSpjjAnro65+V/o9
mk6n/sqoLm3jlJlbEtRcocwBHWWmGWSA1JVq5EGq6rgZ6BzVS2QJTj0eNwmYiRwHm5C7pGUUPAmV
Cpq+NReEyh8QLXu+MkLA6W5HNoZrOImyXs04lBJpjc65dBJP2XhsznwBdKX+HirxB4dO2zUVJzS/
mu4FWq0hsHmaMPi31gZ3qX43Fiv7fOwrRHPkkw==
`protect key_keyowner="Synplicity", key_keyname="SYNP05_001", key_method="rsa"
`protect encoding = (enctype="base64", line_length=76, bytes=256)
`protect key_block
UpoKdwYrRaKo+uHA0pT6HjqBoVhgDYFTAVhYUatjhT0TKw0u0W/htQsFb4x/F/1WX+Ff5ztSA22r
fuYQOx7SaKdiNQa9T+Uwe5fBhUbZYFfh9CTRMRLTJvjL94RMxL4C3N6tVm8vbbd6nTmK52jCWosD
IiQVEYPWzIuJp8HD8re8/XAXVfmgXt582ne9Xr4rk496z2gymo9OsHuubbQsjX/+yJZ8C5lTeifG
X2DJC37xBIY7LSqL/rtS2GvoBrJki3WFq8QHBp+BPdk+CbhPHpZAvvv78vOc1ewwE+YHYbjUx4+N
YK2WZvPCcFynjhDUTfoohvkEMFVjoWObkMWOjA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 460688)
`protect data_block
ASJdSUmcAS+uVzML1XNG9slt4XYLMbfUrNwffg5NP0MwsFXTvowcQi4KbSxDiXkcJZDpOouJjgT3
RLWiEPdEdG2HZD+1SZGBbJl8bzkmhNk61G1omc5DGpTJDMRhBEPAreGGfTQRoby7p2RmILlNTNyh
M6JSvh6AXLDRylAF+xLQazXMK+e1G0dbhBFqi9MClGKWEtPGGd8pjfUvuizTXWY7ZG0nSqyVIrPe
3r1eo4iqP+6Ksj2i+r3X8weG9IWNrnjPlxplevJQUfc3/Ldoj8bwystNl4+XmgyqVG0DxbP7v5af
4c8gIYJF0RIeU2nGcnIRmcNxPKbtIdQdXo61isdzCo1KgmN6c1VJTHmQ9FpiO7LTCcLu4vY4R85r
KQYXNckHcRTAWTElWgsgCuGtXgLyw4CR7o0z7QjSldKTA9sR9X5P0Pyqi9PJngsc24VaReo4bhQa
HNfH5jyQYIiyCUwa2KFB5t3iSLjYrfp1Xoir0/nE0t/CsiEWYSuryNb9X4aNPkghWFHHawabvikI
BKQiDPYw8Lh4Qog7o1/zG012WJieGCIg0NuBnAxTtnCGyXMZC5AjemhDJLefQJwRDkqWg9iXEoqQ
EIYD02qRcSUiS3dim/JmRnkzkc/Vo7nXgJjyRcCc3zj8AoxAlqDRI+iIouRhknJEcLQR7yNlE3s8
J6yM/t0nAY4NIr2nMeVYeKIIv5Pt0qZBejELuM9Kvdf66CKWSU61x4WgDyILP061Hb13JHDvMUDW
zQ9nb+6JUb/2tehl8PQ7fsJ5IyIKWepTfaxfjJIKt6yx47og0Ohk3QZZGks2UJtvKtQ4EM3/4uSJ
fb7+ZyU1+LOyc3ZZPGISqR0XDc3zha3KhgrGp3wAzhUcHdaKICblPweWWfbXIZvmFmnhU5Iout9B
7TFzbHnvIQ1yyJTg8li7BYUg3MFS7HHv9/Wtyl5HGxkULRT1wyJyToc9TZpkXpYDkuNuomAqd52J
I7pCyK6Ycigvy2tM/eRDxVI1lmDQFAtK0DqWNwAPDFNyBSJ47x/XuGa7nVwmg2Nul9H+Oc0a38UZ
V3CSz28FyJK6coKepOLgkDR1Vl3/kJxIqxYC/X4mZ6D2Nb1+KJbm0yejLnV8/UsyqEeRYu+eQzM7
pA+uHmrEI1s7bKE+lj8YbW2NTHGKRlV1vAbmXrRVQdWvYXLa+nCvAjENOnIztLVBw3UCbwQOdL5o
gnzAXGwy/q0IzfIogLEU+hFZ2q+22V1ElbB/edee6qhEvSP1so9R6HSSEYHfRjOpasQiw2B6w+1y
UEzGuUKiNV9kq0BAaPaBAqZcsYKcu/7ytmpGImc/XqW0FWATXhh7OaXKUmDdKrnfBDmy6xsfMZUB
15hT82GOWysAd/m0qxFK6igf71S9gYSwkJ+t2UpqghnVrWSvXRj3yVIedRrW8sEFsIzG1+imhwZG
GKDac0ovfMJldiCQfHNAtZhGfGqbd4GdSl4AcZIhZ3VZS1kQ0zKXOZYjeAeWZZIbeB6u/UXIhNsM
4MPJvAxRx9tCc6DD6y4y74UzDLjX0wV3RVqsrfCf7Myg2zrVNv5hk21V4ppk8hRqOcHpKkoarfb4
qVkC6C3yDAActhJnNypEkBUypRKlQHYp82jhD6gabeL/GwOKhij9dkJvSEIFv/S0IASjDkgjgDSA
W8d2/9+In40nnm3GlqNHgZk3P7lxvTMsKB0RIKcc0dD477lXAkjDPQOAosk3JWpQw+GTBL8PqA7o
I7zf4SVs3W4Drg7WYQ2Bodbjc6F2+97FIE4ZNM7nRn65A61wZT1t5y9FSqpabhCLi4rg2plu6Lmp
aPoJgXodNRUdU7ww517ZbAEVjrC5k0V5nqToOvqI3TV2kmi+taPWF6DmCVXNr6chWHISwUi3Ti8J
4tKYbfcBXegWPlu96+rEjOKdVjrEMKYKmhuPebZyI5qPlXqdL28+9M4/1AQc2f/k2IiOA7jPSF19
7Nub6XV2/nrkjJmsnukBFtIy22z+FTYwAwdJsU3n7R/GOdeJPxC4CEC2P1VMR+m+dF+y9otHVwvp
FGM8Gd233TITbo86wuwklIqR7YZ4U7caq5E7n2b5tCBlFwB6meNXHYUfnCN6hHNeLBA1RUUxckxn
RoASXaFbgtDuQYuGoROvy0i0ESc5p4Q9pJCSNZagirgmHID9hD9lfS4Wdt5XZ0iefRwPKNHb8Kp/
PD6/Z6kB6R7ske3GTAlIa4QNW2aVd0kKtf2+DsLNlisfdjTkJgUwG53Dj+wsDzGloqF47+Wqvi7Z
jHRhLpkV+zZVE48j3MD3sK6MWuGQBlC5kX2rJxUPYbi5nzKC19E4IraHaFaD5Chc/bgcu9+S3eC3
4S0UbqRkRfvx0Jcnhv8jrrWj5CY9bIvQKWEh+SF5Pxnb3QP/qJziTA7HwPFN7QhHTf8QwvoIKArO
+n9U6FBaCgTriU4mEtrIaCq4DfIrzlL1yXl8N4smWaZwZmLCOqMVDiNNrR97vyICr6/4uuVFHtYS
rkNWuvPchN/GKfcCvFzOBL0leUsBkQ7ryzRppQwYHKgWf4EmDKOBL2BGBOBYAvM3/ko9BSqSI5pI
eE+SWmJOOrbPJNEgPVCIfv1mTTEKZIWjigLg2FG2gMvg/jG5eL5HCmvN7ws9V71hwH378Izo21wt
kvtvQN7tq6qEXcELVJWTEOIdjXwokxE+YLUbkgZgT91WGgaVQXD+kGyIisuyxF1kUhjJeVDHEuGm
5VPq12Xts0pE2zHzc7uHnLzsDmsiM6cgeEdYuprJy/8zk0mUmdyKFGWPEv7+H3KkiCEMrbgNeSRB
5PkAmDpgoUztpXUIAX1pSHeTdOT5Yh1tQv25RSc6sYH+5g9MGUfseS18onpLJgPXh95xD/38IRx7
r/xDOpGSf0OuXxVCThWUcKEhSW3zYwMxgpeAkQUH6q/VWtN71s+bkc/C5ODQQykJCyFV2Js1NuJF
Yyzpm8OBxpfTKxWwRUAiJLRnvk93AEY5TqQshkZlNBje03b73qnO1u5Fu19CiugLxipVB3RD4ekC
bEVGNBlFL4xYTg4gbs051XZo5rTU010skkGLITy/A7ZeF8JFExR1ZTZe8WKklQ5gIiruw1H3tR+S
ysuUpeofEjiU8VlETWnfICIMv3AVGy7W9ujk9nk3SsQQtWpcjRsbZrDd4I89rxoCb/Xtb85nLogh
liLrk4dNpidWllivY8lpXyXljjp/QyyVZZ14v9JDx0VADCzoHTTEwx1/Yu2ZkiGooyhjeb0puzcU
n/fOwcpT1VYmdNX+BMk+uxqX6lz2CejqkKcbV2UxX4o3JEk1nQBqsrcupb3T7Gy+WYpdO/2XNjcl
glPlfs5mnPOes0Zwr/NyY9nfdomyjr4ThNKxo6nV+1AI6JaavdH3R3qQW5Y8DPkZWbwcRQE4syZc
MGVk1GU5RHHoETTuF3Vv+EsVHVNY5nrnshSZoydt/o72qWdL201bK6pQ4pRKNW1KoRoRWdu9IJA2
LLtaFaJ0EbM6dQXL7ybHBCHtcjS+/FE2BW9sOJwUpwFiQqimmlQadAcGHR90AHb9WEqGbinuoPzv
Ql09FxtH4QciFg0b1mb8eZP2Rdzmq8AzjNTICKUBHT8qYsI2O4+VUMdVMKBO/KRppWYJEUuxZzAJ
F/PqPhwqkQrcLkac2j/x7H0e85RcOu6fu4bRT8NuRBynFUmehB//4s0LU6kF1k8JjZySE3QZDOCD
/Y3eoq3SQgdqI2YPZy7qrf4sVXmZ7w5CLthqL16BxeOJeSEtvCHUYsZCe94boBbj3CJH5dJ5EPDp
oHCzyAkEzklMS8fSwU9hBFLB3ghoQjiHvErxkbzZA9tEbpvzsma60lOATr/IPar0MT5/hyq+n5tc
V7nywvtWt0p3g+amAQ3CV3CJrEWbROB8nh+Pg3zIzWFrjQkTlTpt0EAQ5KUB7hGVboOqrMrtzFy1
hO+eQpR7qw6P5AuGpJDtSD15HSrdwGcVais6DOHCQ/gd8AtsBpqegSmRzTOr5AWYsA1Yg4YmGuKv
55JkdNiV0a6vB7Qc9P7rRn2xnvipx/prDxYrYdMVPQC6tiljKfAwGHqUHGoJ5HytbC4TABUQ8CvS
Xgj2ZApZ3jGTYH0oK0M1gDIfQseTpztA97Z2l7TXlU43ARqzb73itMlxhW1+G83ef+u+YML/jDvy
/VhdvYXeFRxFc0BHwwBkzTy+Rh3ifmMYgrZnExWOgg+DV5WeEiGdVM1swkPxbrG7SDF+bwwrVQ7y
i4nlU/T2S0/E9f+ZpE8nYYq3qW2VkwMGI2OQWY0pm2s8Zvbwgz5Jy6X0+yAM+1wr91WJ/orsew/J
cZFdAcIgMQs8/R0YNP9k4n/5/wxPvd2fWNQCJJrND+9joOfsPp2WpVfxchsov2tHTKSdSc1C+D1M
hSjB8qtdvy/gCKOL96JA5qhLI9J1BsWt27+5tOfXWOGOcmycoSlp0JAMc0Om3C/Z1QnJcR5XNRdo
3ewaxooq4iuT6eNj55MrPHqGczSvKDUy3B59nZAqBYw+dqqQyu4rKKZtqsgYmb/50qN21QZ3Iz0q
ZbvQPYt3n5o/vlZ0xSXWjR8W6cFXlkdZYPPTQJ+2gNWUn2FzfZKqWJdIYUZzDNryP80rgwTiGxKH
tl3dij0u1R6kEs/LQZLFSPZviqzd4n9v4nSUhGk54dQeq58q7ivCR2n/ZDsl6dqfJW33ehqsd+oG
9N1o5bz8ZujtEXEYZYnrTy2YEp+jF7UyBFZuNKg7rYQURkMhIw6v3PYGLn8Ti/1non0wPGPB6QPP
fMoL04fASm13S9KhHXLfXvUTkH4jWOGR/DxAJrbs0mC5EIBdX/7Uq9P3g5MCZfRPLuhE9uog0clf
baeP4hFdlS3W6s+pe4FbknorlvwrY8+Qt4tNx4A+A1j9DGuGO3Fxi+T9653WoOb1l4/0TfdSRacT
xB31ZVf2yhgRsMVyktLsH3ZS7+0SCL6MNQVN7wl55GFHJNqjYWmZl+l9BqIKjxhdJkeBaft8IxXr
lcyezAreBLgtsVt9yLXOo5zfsMKKAanQm24uvCmmwAmHiERZTIJuZVhtCzrC/P/ZJ33yp4dr4Zrb
m+y0Opj3dvwzwGj+DGgwiZE8zXRv9fTD7gpL5I+2suiDACtyZfML8cc855lrkdqbMbOSZSZVGpv+
b5xxe7bfmjP7asHM1gDh5KV3ktBXoSKvOUMple5zWhSW4clzasUv53EqiTgX6b+7+CgF94RoOXQZ
1Z0LcWuHK0H8k4B6/NNVbz1qGNKW6F44Gk6XkzXXpJcYpj8A459r4lOWYTLsSglhsjsc/NCfmQ5l
wD4diIHeeykplvFFi0yEzQtt4uM6rNcQHUfn+FSD/+lXXBOYx0w7Vxb9kr0FbK0kOTA4BSkcPWs9
duLSWQonddgqOuwv02whpKWJ44JlGK+uOKbkYXNeGgVyQflQleoRQSV6YBbYQRF+spuJTmWBLRtS
dxoQq0Quo1UsMlevAtcPCb336WnjY3az7dqzDTi3g7FhgG8JcspClvaZRpxmzZUgeRdz5Qz/5FXq
FlMpD3LnFb7lIklGfgAXsykhmIQrLPY9veAQZrMMaou01mA1cSl208rUs5TKCQdvjmTdu+C1KcMH
u6SKbdiQBHHpcYwYlJkyI/zJWB7RQ7Hm1CS3TNPRVOD8k+ryg99YhYdbswMVhN329txGYrlNq8kf
azTg9WE4Zbncmz27ScuoFhmqfYjh4gr/bx940EqrBtP0RRWByRQgkqOM35M2cCR77rd8vPm23I5w
8p+6ybNUbt8CFiZAc7RnhK0rKm8I+o7pU34HSjU7iJQWr/2RHOjsBXKVknaZEvbfrdU4HWLImp4L
rrKZG73VMJUPgNDuuZRUt9NZd+Cc2j9J4wRepdI7ihLesSvLcDGw84sFqovR+37mXmMSREAvagl1
kvYFnqk5EyCNecSJNXU6dZcIOD+TjF2GvZNARA0tid0mhyS08SRzfJA97pg3jzT1jp/fGlXnzk5y
zLmrG/zGoE2iQB6knin7wPmoNDVBEyegFDGBfbfqU1chtW376puSF3Bjk44o4p2jPFXrv1jFFAoo
HImHY+UltFajKJgQ3UFL94WsszUniL4hR1gz9XKhtu0RKZyf6UV3Q1dfSGrDRshKpj2pILY3qHQI
FvilNOz/SxIWgI8GkJpPCoalQEG3sqyOIY1PuKp5g/tT9bCFismn5jSwRkAU0P+P/5u9RWEah/6E
NnincUoaryXk2fUCkyroPw0pzEbpCdSiy8IxkDeQYsDH22xyXp+yoqo8hXZoKXjxaJXBAB+IWpYN
wWRvL4He1x4y139hq+96FxOmLHESrcavmlHDgbMbDlyz5eBZQhIe/AMGYV67wBE+a+INOedfGTgk
S3aZn+QIOPtA/DyoMk1hk129DBTKOI4E+bDTBIFrJGRbuF8FUe6RbaptZyFHbrxDpvnzwC09KToz
bojggRsMGvaLIlrVZdgLeSFCPlsNFVll7VWy0/vMLHSsFKaEL4/pSUs4lKe/5DONs4S0SygPBvmC
A8hk0l55RBRAgoYFW1k3RhFZklPUHWmab8AOZr53cwsPcyFqRQZgf0LGGR/ashjyIc7k3BdL1QfH
TuVU7QJxD2i4+opJ+2JjcGf5AzcweVaGihBC4HZRxaevCtlYtjlRJtHlLm7SkIKxHl+rfvmTQ+pQ
tedTJRusnlOsPpVRebLK496e/ZCRs8MS/CCA4OVqgNCcAQOx/LGGoO1RG2P5UEAcromh6FJpzTfB
adrP983sfI7qhnj7xUKaqTdB625vEvMXAi7IvL7rRVbolPdf3famJ81RK1EaVPSP1L2jQVxQTxA+
B8ljyOqpEt1z4fxxpxj8mvMlOSucJpbscjewQCdXxOMt6eU4/Py0gSB6sV9FXbx5JSOiS/Mj8w8H
LEzdy2TYNTWoy5Xj+SvzdNaB+40XHNN241jchFbdU/qbSZmLfnbQdqQPBVPWsgRcKnYD0No4IieZ
EiVB7zinTx7UnQi92hZylqDhph6Pzr6/HQmxICTEwYWVw5pww0AdWUakmgHPqqABPkyrqUddrYE/
oA5QHAMOLQJQQYvAgGHTk+9ICvVw4IUG1ivL2lFUNk7s6vEcQOFoUoRTkUb58KHGQihpiAEV84wU
MKTkDZhjKvfIqdqkRYlIyF/XAF1LtVHteQqVw09wVh071E1eU+sBsTBatS8SG360KVcGVu8GAnvD
irJwy8ama+F2C2GVkRs04P9gCd3mGGXn62aAvNJCGhZO+FvWED0B+EXLld6ae+Hjw2/tZLpyMQAD
3HBf9c5VFCgeciezH3VxArylwyBVvVPlPh5sg0MbsI9x7f6DvVtj/sKFrwfcaR5DqjBdGq5vCb3b
lXPJBlAC0fZiGZrtZXVMjUccM7JGRtXRn7HZtYFzh6InEjITDaU53CcxdvWdTinDm2izeWMXZea+
+aandi/f2Rwr8EcPwlom5K2MxQOppEtMPDItXDiaD9/xW9Hpxbyg7SrRgJEmYO6XZ972NMsbJUgR
/ziL/iN2Ae18bJ/YVmnni2enbpgpwXKWLcuZgTMf1SkDchFe52FVzGSJdU5/xD1gpifYfoqzeYbv
nBxvLH8oMh0rpcl5VLG3aTGJVrcUCUJnqCTmW/ZReXcqa6puEtTHJSE6+kzZ7/qYWRyexM+g9PHp
wop2deveCrnXpCEjhi4p69U5WG/ToksJ/v7JRWZcNKmd8GYSi1ggjIYf10eRL3yWxnFtUxgqYF+Y
pMmp4rYXich4BhH1ztrrx1qjSiV5qufeqC3BkQnbPE9RkYopyxy5ap9dv5Rd2YQJwQvO1/XkbonN
g5KGEEhJU14+Bng6gmutr/Xf1YgYmEiMxTlCu3PRgErMtBsUJ6hBVo9YXWjTwPo1bjulPaB4p2Iw
GqdfsT5N4aAe67JyV6ajauxT6N6O+t5jBSVZabNCahhF+9JE4EEvqH834BcxUCzHMIIqcMSl5+Sv
TwFFk7d7ydhWbcDkbuf2kfDqO07bwvrkOzjS/GvOmwanGC71Y5vYbU3482Zp5MppQjch+V1vE1/R
fbvK7NMtGy9Xz9h7n/B4ihS4XvljIalsxI3hQE1+hQHswbqagFaPn6e7AMffChhPJeoVLD1rqvIL
HeamkfIcEw/wUAhDDyCGP8oOvSTPHPLyN4SOdz4I8nIaRvmHHYSyBC92SFAYseBE/9A8Wyv63n79
GTO2AwO/+GhARdJQFYTF6/FtHLI7kf2AZay/jFNZL8RIGCFAcqSlJrDOjECEGP6/pUz7mE/0xlue
VeknQ3E6cMiyF24G2p4r18TGxawTfFpSPIbJ6T9H5wmEfl3TiFwINjWkFrxhnHsGYH6lFoU1niHi
bGGGJVxpoaPAJCHJzSb54gh1U9n6ajNlcdEVE9gEpLBQyNdVpvANX0Ag3Nq6A4TXjUcSXOwHqjEf
NvDMwUtbGsB69ePSY3rkVT93Cp4ZVPeAjN/evDL1NA0PIQkaa8lvrNOUq14D25z9gJO9UjgaFGxr
At1z0HtXpCziV3YFLngWf6sibq5ZMVzsQewwVG670R4NqlPy9N+Ih0ljoH7bsSynZJE7OrSoNzUG
mRkaxuDx2BJbRjQJUrbBCkU6g9rAr0JqH9JytvEAjW/8wkjWa2lMi8YwnuFdp5nP9N+XEUm2rWBB
GamEmZUDLRSE26nnzOkCXejCq7Ml8nMIaGolVtCuKaAvkyNeIPdVO7Fn+ylJ22TFLR13WtBVFj1F
ItOWVDmaa76P+zCHGvdcemCumOmo7iqP2Q1BtKfVhrOHsQhPtJ0MWyaro7uYv6lyhYEZ3Jh0dFSo
TQU9m3/9ctqqt72uDUFAAFx7tEi82vEp6K88Emh488Qyt/GpiC3VaMA1PxhbJuRsPTSu0GfrOf8x
i1TYNoRzE3Xubwem37IRe/U8e1qDTdWFhGRxmZV/MYaZG6lhyAgrev/J8y7hvPB4dp1LKVEvPuKJ
UzBOLZP4i/InZzQogz+czFLFBfzpma5oj2cdj55vfI+sm7dWSKFNSwBCMj9z127rS5pqLSo6BvL1
nd1/1Ji787LPlF9f4mD7KUIp3TlcfXV47uyao3YJeGR1Jb8uwY0w8Bi3GESkp3J4ynrG8Ug9vya0
t3VXv5nPIhoNNEXbaJGAZ3uE0g9RNaS2IyxdhzX1s16kGrLNf8Eg5xzXbwTP/I1hugEq7r4oy9ju
h8zTk18JCsZcnq3OELfEpJYnRYI3VG/AsBFONtZs+PJo3D+6QhDw/65niYPLTwg1/UeZWhG9ReM7
KR24yNrBNoFlY8qhrc1X1HFFBM6U0JiunA/lu2YOWRHCUXS63PrPUXc/GZMEaJYn/8eHPxR5mOG4
EIPjD1pjlMJkPlTk/578wuud7Rf37kzTv5Cc86v2vYFPsVWo8kT85WZHBNujPwMCWYZGjOBjiuVs
KAJ6Y+HhRZmEN++r4Tfp0Gk7t3SzHOfPoIQnym7hZUANw9zGDdDcF/lqGBnKTwIfZeopW/lAL8s/
cT6xVfeclJo9epeyPlEuAeWAvbESAfpBEDU2Kc2koLEITiz1waYd+VXiyGxLblsNk4fBuPyo28WL
wL/ME7xcOWT6aNbIB1wfx21k++FsY5OXW5SRaRvrmts3+MY/l637Gv5ogibNtCsvTIMtDSxL5JEO
edWjgGde3N56BKSHwuR/36G/wBF1hfyhvfL0yQiGhuSTIoHDrlKrvyVs1FAROpOWOVAPsz+TRqCI
8QnAffnA4pnIglFMNpONArn7uC/mV8eTcLkuIt0cVFMU7hFGApyBumWFW4fepwv3SekhmcgXGNF7
T9sJbUzMZhR44jDpWqoE50vcunYmgQjDvgtAFiq6qca9yBTOGX1zaXq/TduOrJNNcY+tqSUlE9mB
WvLKmHnPWq80hSdmYdXknNlLCF3AEd8ixImdjlzHl0jGgY+ZVixuN6h4kWtI9i0Z2ftDBZNYKQdC
ca2FBTlb92zHgv9O3SXWWGmRC49+eJg31mvtxgkXtFc8bF9HwN+jlATBgFRO4+RxhpwXzAFF8RxE
2w1BmXF4GGPxdBhvl2C77XORKch/NlBCulPLhBAGDUSsukFGcDsZ0h6tDNILTqUydjq5sovNLv6S
kRTJuLx0eGWLxVKWuAEC4xYa8SkS2d/Zhl/Ac+BcHMMEbKYREh2xHeRotCxXXAReMuk3dpBy4AJF
nhpbRHnb6VHOWLkqh+4y8YuSij0KEawWudzP2oQBkAw85V2lNiX0vLhQLVoSJAvhL0QkoNCJqzw1
mmC2AM3HPNX1ak7XvFnEIqUcKehlBm6tvG3wCHo/keuPNax6nAeRjrm+ZIwM1kHAAbYWpY97NDK0
xz41v9ejhcIXR6EPuY/mRFtdOAXcwhH3B7BMAqjHyne6dW1GOj2fVuTBN30GAL+NQXRo8Mhol8pk
5Gslz7iwHXQKj9PKY7vJ0yHzu1nt2uJIc4GvN/6emb/EZLA5mPe78KFxjXlfjnc89cPK+tKrZZHq
3Ka1GFS2HPDDNyHsuEUJ9EPVgWWX3LNIEogguugeCobkOQnbiYzHZWYNd5afhucWYKzHVxltZOLg
JuwnKFL2fhfL8Z3hHBmSFdsNnFzwtlj8rHW3NwJbDuZSYzJgKuwlsElzRRtKNlHVr7qtpyee/67x
uDSnia8Ew6K2ssbkYaSH9a3ptHFRjss6HOrdYPxi1V3urkjJwDmdTChwBvhkTgBkpxsxV7/6D/n1
XmXQYSPbR0Z/LJixMfWWwnm+0uxmyAFnAlU+Ued6fWhemrQeyLW/nRBaxngJyvFvhIEJwtxDOsNm
+34Ot+FQRcXqRC/h5NGxmKCzO4T4KDXtVhmtAqH3rvdZ+MLcasr5qjNDqCXjUtSvcyWFiC7pQvB/
mTAuKOI44rFN3I1EjivcCdnJ+y3XHbKkf2rLDfp5fY5yej1jXBCymV3EMJv4C/GcFZDDgRdnjIrX
uGTm19/UnVVvBD5g/bM2bCjlIy4RgBlzwXmjv2Le647J8DuHKFnn22GEdT/dxVOb3MXBSr+ES5jq
jB1r+wy+oawFYGNf/ca6BQGYwR/21CxSJl0g9wxoy7U1JlkFAtQFRl9zehGeWCh4UGJnIZScwEh4
eWCWCcPi3gy58dWfcyPmoqwKhqGuuzG3pd86GhAo8T4zGFqUYJS8FWnyAiwVr/yW/lZAYI+OKG0t
zz+HwCzOyRcAQ98AkWXwASWg8dSXa+uTxGIbNwr22pzM4he3s9eU+9McgFuApUCOTnTP8S5d1ga2
TRfXKO7QDyfzm/ASNmWclInM6yh3y29C5rL7iJ6i3/tkDBF7io9EV85fXDINfXayCm1wy3jX+MFd
v6rrORQ5+6By+2t/ZYnOD8apqHo73jLAWRFkXPrQD6PgA04ooNV74TTY35mhrRPrqWrz8FBVPKx9
J4V22dF/DoCMM64BREQ4Z96pZxYFl1e4h8/MtCNxoK9qUnKkCB8zcDRQ8bnUq+Oa5dvKHGQ5wm2w
7DegtZIu134/uNyZ4dwh58+CdCtC56985OCPVsFxitE3EJE/DiI2BSqocwJPUIrV0YXPjPJjO9Rl
ONj8nli2OodqKTQV2YU0pko/WtVNnCIwLhomVsBkOR5sfQ+rfwN9b1OAVNw+7uS+PgWa8c5VKt6z
7sbGAwfkDRwc1OjFrMLFSkcCVq2U2/EdJSmncu9TijZoW4XMEK0/PBVwuefZ+2JIUbgFi7/pzV+z
PSlnCcjRqlqslX3i34HHyVrriPmjrqT/c23hpP6SUGtpsSKYlN9PF2nCvzPFOfzN14Gu4bz9RFg8
s6gHAnL1pLOVbLHiUfghTgV0c0f3A1BPvmXAqU/lx5p3ZAl9/ihZ5m2ooUwE9uB3a+z0aPPo37it
R/8tnd+TAsTf+OiGTugJJP7T1kpreX49uoY5ck+w2a9ojX2n3RRaZvrZ2Zcww0tI+B2OjStZ8LU+
7nHTJnR/lhwXBV/QY8PlnuZU+u+Ou3j9Za+5nX0N7BGQcwvcb5B27DL0HbSvV+8kWfD5dKIrC+Jy
XwFn38SXOF6EeI/q2dgGeA7SnmOJQBAL9HiDaAJyEOHXU42FHBBcMinqPpM4Jryx1eLPzrm3kHAd
H2M8r7fBt4goQc3F78VgJeKFfo67KhFXZRDpmIcGq3EdTeBN/cHy2QB/hFBMy47bisOBJzu0uE22
06iBWQGV7nwozmNL7603XbWX5mj3YHbvTxvtz+sdkma3NGLYAgpiM8lpG14P1X7PpVwXpkurtcBj
gycihJiQ96rVKXqMPEqoGI71jyAh+XyVCbfaIWpa6tOIXpzZRSjKf/nyVDp6ceu8nQxIOvEqRkw0
E9NwNA4hrY08aCezJYMUtSypkBQm5c3f8M6FPFB0VgJDYDQfiNxhF3pkYPtDbivD4qYx6VSS2/gC
Pulh8Xc6+4i8S8IpCn32dnLNwO1F42bXkY68BzG4Nvpcy3LYy8NpExB7KAi7WxU30WFUA3ZXBhgV
FmHEA7tgIpi2M11IZqhUHlG+BVs186IQTSa83bGFLJQv9EgWvRgVCbsKbsdlgQ+0Lm6OQOadfL1M
Fdd6OR477Tvkdnv3Fh8FmfKErVQL5ul7/44UagU2IfGPMsKV0fJ+R0NsuRLYo3VTglNr8ZSNMu7x
UZzfhsldhjpFbPiRPKQCaMwk90I+7Eao2nhazqgOt6BMeOteNHf8OMVGcCFgj5FCrl8ZL8qepvnJ
r1U9GL90Sx+EueC1hIp09XG2uiSYUyLyNe8k9t1LU6cEhZxdPpAS8EhNlEkvZF9j7fUap6vhaL7E
0dvROxbUjaCKYI3jmgkwYc8B2IZytsdUGdGB0utQBTkSbhZeZUao+K2Ikq8ZHYZUTJXduolzCg8J
+1PtIIBHeDEjG4o0g+jmVqhPrGeoLMBKHQLNl1B50FuFQ9G+eYyROGOCR9N+BMGDyHG/4NLAZNWH
CGgbFq2svbek3f3IobuPWLMEjyAVNCnS2gsE+5IQGKXi3HGf8rMKNlXFN24OLQz98coc/J+M7HpV
WXMMnYZDrnZ2XWuwXzsxexiMHj8U0HcEuzGa7y1soWP546OW02jNW6k2lSSyM++gLvhzqS0STZAe
ZlWLKoP48385fsus89l9SQbIcSpR2zw3clNucYDeoiII6WxrKxUbbW/6zJDufEPXQgLrE083JXrN
gJPZK8wpzQfegQzpQLdcCyFJO4arkZulebn2TAQH60mLA8fMGnkJdnDVYKI9xL+K21guS4x1lDbP
lYCKS3bhFwMFUh/6DRQm0is+yydZ3/uKoeLi97eFUCa/gGnOOeiZy6PqkTbAre/AewfHX2uCip9o
YIYjxQqJP7P6lfnbKH0cXZRTciOl3HaF1AMZjDZUqy6tRHiOIo0nz2IMcJncnYitDaPXQaIQE2C5
CFz3n7pzzbsdceleF+WusfHkFh7WbGeZTrShhDWeTsGasKASZcqvvdZJvZ0QoSDVqx3hIUHWRzC6
S338Ga/F6q3qx8Cw4B8vwNh3CYYoN7KkX35CYDWKTv/fY40an8cWb/haV1Okqyh6L5/upXldnhZo
lLVdQrxS8yp3wwVvNwExkazUZotwhVAUbPAbQZREjTR5YfvBQDTU5bmpDpB1FetiWUE4DVK2tb+Y
I1NmGp72rk6qxZRtNDXsYu2xD/A/+FvRnrhGVYSaGNpVfJ0LlBIDw+lleSKAowxh2KbeCIpwLDgo
Kp4k60bFY7OB1f8//EUNGeOv+K0CfsWf72oLnviFNuNWAOWxaEw8T3Bg2ng7APBa8x311SKULCU1
IQomvAOXcurDMkR7CrKpa0jDESmLjNTtF1WRyuG/VQhkootmBT7BoSx/afa4m7jnIeyzHSLbJT9n
7Rq8KXK9flEp/mMOBEGSDP/UZWq+t1RdKzWCQ3dGfBrCVPmEvxI0X/4yzWljhwj+tDaUf6/CXb1q
wtnma2pdZRa+jNRGoK3ZXgJlVN/vyAxUHZv2kpLafgG6hhlN0iW3GQwAirKwKTytgdOo1n7+BceG
p9tzAZgHew51kHhn27/qiOHrYJA8Z4Kh64LgxbRtZf/peAIuaQcTZ45bp9VJBhUmnSBZQrzUeGj6
MJs0AqlQPGd4fEkmkqPlZSlTRMkCa4B0HSPCNkE60bXqWu8/51fMhT20eVV26FvC5Hs6u+2IVbWQ
EDkOaA8QAk/gN1l08MrFdZ9IcT3/bshjjTl2jrN8OXh4HsasJqc/FeMY9LtRjXboyUzRC38wCAyG
SGjLOJLXLI/Z6tE6cc82AicYci4sdvM2+ep25YVDLhjv1g8TeEAYRS7rlGn1CPi08ROFKGlZahMo
snjgez2RXTkaqXOHb0AduMgZfLCaLPZdYC6Lz9eukqK5a1Pa6X7cAmWWKiBjjBTftEZCmAol/RdD
G27Yo/0IXrJpvjxEpVW1guU3BP+Du0qmShgH130gL/XKQIuHDRNT/Ke5ugnQUbDoYgnGtgFTGovG
BiZ9nlyszivQAFsAF35g73KyTNpw0YDT1Txj3yLvv4U73nZtInfdhzS16cCA+WUpIDn5Nny2ix60
BI8etaDC0Hs3tt3juZJdCacMnFdx9Gr5HHNmzRbovtw9Hny8sWq+OSDUF8aQQXNaYXENhfa2A+/k
aPmGFkYk9duKwR4EcP+FlJICN2WwXRh8EXcKY5ro4a6HUwiNi4HV0mMRd33tpkS778w61YgqybOd
PX1a3i1MPEiFxek1rrUEFs4J3WSmIrynw228OPTB+BvVsN4NA+pCFdbtsYI8B99eEBhYOnfamiiB
SaksWaGQp8cewpXXs1+Sv3aqmms2D4peAuRvdh8kIpEAC0+xh/xCrT4tPl1ls5nAPbvnF2oIORtl
HnG1HYWUtWtkY11wTT4/pScrxeXVpLpqDKKy3Py6gjEI1hToC/2Z9fNAWQ5XMstXi2qH4EhcUSB7
dicHSjuf2J1fhnKTOEdBeLLMDERUwXRWcWJOUmQBQTjyqcXeVkbFzf5+VH7eJCMTpvzCUC3eY3tE
tKQ5dg8WMpWP5OfrUF/vQSRXHiswQr1sK0O0R9iQ502LMLwE03jaVDGhJCl/2Z8DsRUR3n4b3hHV
AA7GNclqXK5stDtYxIq84whdwWwK3oC1yfzfilEjeOWgjy+XKCT1QFQmF4AmIn2IxwUysBtkXXQ2
I5l7ya4URvr7wwrQJasvWn2QUw4vcWS7V5ibClBYJftBJ5wN+s3TFmgwN0FCLv3B6teYGQZ7Alx5
mp5+TPD2eM5q91Drm2G5krAcmIXv7wWmdGrVXy0GknIHNktEgCqUUp4/df+8i6HwIK/RadASfym1
z5SqDtM2M0DLAkQziBw3ZhPHZi++bt4zMoRGVhdaMmtWa7oInjw7J6pDMpUE6Ki8lKXvOJW6Nrwa
Py4zSmMWl8+mr/r/8RFz5KjFoYgyfI1eEJslaoD0K+Q6GT0TeKQnbKK/VREB/XpKxvpJMbcvckex
ItYJhK51UdlLQ/PdBhD39oY8n4rzkRdUZiPytU47cMNQaxTBjMKsnvtiIiP9piWAhQRwVxt64zpw
9qxu2M/7Oycqq9tFBfBL2PEbICagH2bs/Ai7t+sOdBggVIOfzQRRcdsjNqgVFNqLaAlR7FP3rh7Z
f1J4GwwtYzRIDmnoaLQ9lTHu3FDDAFNeJbauCrJpY8AAgxNoS/GiuZNRDk7q9N96+TM+5ZniJTLG
vnqvPIzZDumDLsu9LhbnrOotB7MW7j1Kx27r+rVtByQKzPKTDeeOrC2GadBHTXhExzpeAS7k7SRS
K94MlZb+zZFDa6ISlpbv58KKY1QquOmE9FE94ih3+h6gR1tw/cmpIjCtpnpjG4PJqB73Nhxcnxaj
Ra8D0YcAfWHCWSiQVYvUcduxe748xSNLOyNIPCRKWS4LyTkMwwcvP1csUnu8axqEGFg0R8bn8l5i
eU+m1f2DdC7Zfr3MFmXDSlVksIGALtfNlso9jhzroMwG4hvSZ15aR8zrOWYjum/7oR/h1cR38DCU
UWqeWPsmcz7K7ilZ8gxXCsiX1tlaW7R+Vy7Xk29PT9mg7Ud6RLs1HF38QbjuuCjbS8SGZCPkdb3W
k4g5eziMMX4NXZsk2oE0ZZPda+qTXzpFkL7TvT20L4ieoXr0axFVW6cBcSy/m/oFXxdpk6kb7BBL
udoL6BEBNIsmoS1B4CWxmx/e1QtUxlyQ1qt/RdpWzojp8FQCx71U6lSDZ2C7MVnB0lPu7VwHrl1v
RtlRRZNOQHduGbQypYftUt7rPw4LqTEtaVCEENtuD+9jLqUQl4bP94cDgPBHNhYe/NFWlWb/9xqe
26p//tfyo9pH2riOSJKYWn72BprwUea9Pu0NeG7wz6Yrnug2x2T4tBJthprQ73mCrqswMKxshPTa
si/8yb8G5O3C6sb3NKZno3MSObnz0zvb0Ufc3mjFKQTphlWy8PlxcD30e+bjHtb0X7ryEl2bV1BX
9rdv6z8X7DfvVANHcTksbx84JmIxePQ0mPTufCBlYLC6WMeiss3xATlaUMMmWhgIfHreldmjlhr5
61hJbyitZDXX4g/uaPXqff1vwRgLeRCuuBeNIkZ0W25t5TXq/Ljur6UojXZ+mqmiMkbWRFgbxGZb
FnCjnq+2pZ2B5EbYbh4/vpkWq9JumIhAmiYMjl7ulsBZ/US7zfOfD1X1i7h2ykzbsDbdySs8aJ8D
R+aQXKwPkmtChslvKuaERzocwJRzaIzFd0neQoI0v3SD751wxf6DFyA49aBAmmuOB4mKdkh2GE/S
9a1+5yGeM2Zx6SlzldmFtAqxU6HUp+6+/Z0w4oBCqAkPgkzxZkVFgWOGRd4kdOJlGg5+sJ4nujXL
7RNHX5bRi8GMxE5/obSNWMJKSJB+R4p0+jln9WeKJ8BfKPO+/9lx+O6oiDWWZfl0V981j3uiuRpD
FlKV0No4g/IujFVtfMdEVKMbsWE/ciM4RdDgmfbdccnWoMRKWa4YbuolJa1TCtErcRPCfd+m2Myo
kC6tqLx9ggnlTp3QZJFZmIPAQbw29tXdB7im47HMcs9xP1ZMN3Zm07/W2uk7WG0q1Iq+9wAZgS7K
EPFbrUv/NXbdgUaox/Y89LKg9tHnk7dNSEgnB8f8FSZjvpHuJAD6Qbu7p6BV7Sca3UslzNw+tJ/d
98Vqqkymo8kJkkDg6EBAD2ZGgmbTD1CksE3b2qoz8GA+ADk3PzPHNm4FOd/aOezb+AuS+xhSp4mU
dU8FpJ3alcAMfFbUG1kzwLx0ponz37lXHe2hEYZnxKY/TtfW8rFjV8j+6qWkC4JOgswE46zELySR
jHYcRAiMCtHisNnnisuiWPSAFqRcCpGjTZKPhankT0NuCcEhizMJljhvO21R0re0ZysXhK1cRPuF
cfcigOX7HgJ8tDP90PErDRk3+7i7mH2GVHSO2M3Mx8IdZJjHpFMjcQkz90xAQxk44VbneXdV8thQ
lR7swz5EPjNGGlM4rgbE+VQzh2Yh+fVFftXLpGZmZCN34ZDSHwCctH4rkNuTTlR4ES8d0a7ojqKk
UaYGnSV5nwPkyl1CApDxqEngMLnMRawZwHRowgb8X42v91dd5eO9Tfd8rBitbdWx9vLd72utsxuL
+GTU1oOnRJlejFT/aqTYCklyktRsti/4q/59Eez6UAIg2QA7MV9wsdQeCmQs0zNZOUhFcJaEGhC3
BuPsCxPMwkFNEU8Qkh9cDX9dPM+CD+W6kUUmK5eYzx3MJJk41uyAXWkdwYHClokfHh2RmJf99hvK
wlIbTUeHwqvhSQH+iuPeQrFgNDJQyMqloTc2p/rbjt6707KeQ5cuff+bmJbBksxxCIHANbPIij+0
qsSMDeF0EzysaUfkEsxm5foM3d25u/Ad6wRGEbaA7LiqfYK9Ma1yjchpbfjUtB/Hd9BZbIEh/dwW
ZFi9SXxnVImiLMvs2UCg5Bb1lLSKI9Ejauo4odBhS+N9Rbw3NuEBNAsaJVCZ1Lo/3ZErIS/gZ4bP
UYVF+10NqbjwBxYfUyvA/zvz8ByQuov3wHpST81uGFBlNZa6iGBirKehxgFugtbjCASBXWeUxFEn
yUyLoOwjMKuO9JYBhMZAh2jcoxiyIOpjLkxAR/a5PKIahOyfLMNBaCjgUeuHmOAnBEWeEXoIjd7S
0g+nWH+8a27GvtOPtL7mALmA8Pd+9NAesfhMcIO14Sxa+pnsOK/IhpwpJjYSqKdSZwlanfE0Dimz
rA4st++6mBAG4710HVae1sv6jmatDXHCu7CfGUI2DfZ/KbQpawrgUhZJhcFQGNE1QKrBhcSj5T4l
X/kJMUASEliZgcTzUfKke2BCx1HIPZhSTnqKISQCsTld/9NIONqTvbNa9cU67tKxUBEUWld5yAS3
eSDHXpcxQm2jycT5f8HCelF6qb3Ju+0Wbt60IZiP3qgeViouDYmCsYGvBYv2FXelvAgq8qrZDA4/
sbiqZmexQhQcZ0Fv5yfc/xrjxHIzTtLgfFK5ELeRYS9M9nNTrl+tN2q6mfxAR9d040hLPqA5DKsE
I9RdoLp7sLrx8NanKl/f+LsTOwT3gPbQFP/Cv8hAs+9MFkYN2XMeHfHSsw1YiaDP3NX7emJKoX2C
ywa+wBVPN8lcdqCla+4OOXKnnZZN84vvpNshYo4ts2UD70syiNNyJIZnfOLCPdfq29JMBdcVXLSL
B5lm7Ssz3h83VjzWXcfyITRWxfsNo8Y+RViXmvQ5PZI8yE+ZcBj572JOt/G3jeJtsV5jVJwJ5k+g
PqaD9+bKNDscYbijAbSMO5vSOCSQr1qdHJdQAqOnkXXiyCCm0jQwPzbgzw49BkyzRAW8eshmUQfw
PtQcxOhN6JdaZHaVBU6m/QjjjLCKdtwZwXeTk6bheZfJcWOkpRoNDgcVQnT3/OKtCNXh6R3OitPX
EzADwQIraNeizao8tLnLaoZB/DMxRPx9hCZn39IabYR7OFIdLZVa+DFfYwFNj1qLDQqPg8cBUWpp
mkbMjxrNryBSFyr75xE48SAn1eAfkLh3gNkfG+V/gtX1GLQi41VE5ftkc8t78DtFtWwg2Ncz1yse
Hk/DL+e7YgABZ0mE6tp9tuNvRad+G4k9IJIU44cO7bMSrxDGqQuFxQe2j1QZMRNobrc/AWKrspHN
HHwyQURgabnUul2Z6RntXmKZdW7PUVzI7UpSGuFeMy3m7brQ/jptHGeI950f7Va5FoUdNARrrMYs
CP5tDdPUnNWr9YnuZRNdedZ2RrR2reG2+dsWeEe1XzJwsp/Qv1Kx+v6itL2wj36duFOV1pN99MJ9
V5IgW+sd4gIE7YUaCqMIdWE5gQ9lBC5rb7bP70YqVteYpstxQnUw2rBwutTYRJdub1AZU4zITcTp
VWgvduZnr34crA7ZObFX9uNkZc5D4ZeXShD0dLYBC63KW4EP3P4Zxfxwknhx7yipV/tNMiYh/lDT
JEfxMiISOQcWY9leJMYKodTSQMXf9GdFmEPMBuy2RpufwXdRyXrCukpZtTYBuyzBQ8mbXH8C96BH
USXuwCqtYVVElJx1sXq14UDkpKkK46jk0K93XfD+3EK5S3K4XHGWt4mTTQ1xd94UGMpDLkl/MqPJ
CcEyYJ+T1XCUnxtzWl369yJvj4mz84cXCksTsfwaYgVYDwwg/1NVBr/L3ABXzTYYOH0sxmJGAsXM
ZX+tnH1G6hwudCzNhhI3zKKWWSqPBf5bBsxoksGl28Z0WnlymYuX2EGbImqJ1q5ZzQIYqRKiB482
NVNknEmLu76wEt2XZuWcf9x9lIavhOeVMKOgy9Gb+/vgy6MYY4PTb82/nqWvsjSj6MNd/5OYwD9v
RGTUVtL816pQwATwFgM+xzrwnemYMKs4eqdMwONAorjgMFjODDE0LNV9T+HzLAc8mKdqUE/SwsRZ
aftSkwmySm7TlmGdJoiqv1a85RpDX2k+FFRDxa7JWGBfcvItWeHs55v4jXPdUzCPh1Y35WPClRWd
Emk0vFHR9SRr5Kpab1pJlNFvS0smNxwg6cWk+A1I3a64uJzS8gXGsEpJJUa0Xgbh1ciSP2DiE4O9
vPx4ZTP4f6aRXtC94flV6u7x1dQVoGfEIW+8M7Y/1de5cFFYNgKV1/tOkWLdt0POZWHuO3Ks+lex
l8mKGLZRDg3X/ZGRm6lgvU7o7KgqPff7GIFNbkEKGghYsfplsismFQqs5zvbRZ1drbXp67XcIzK/
E65x5VQ96R/TpXFJ5A5cAEjrakOlm3pkuvUKU3kH/9n2emDE1gG7TOeKGN5arU1AFLRh/BRpHC8y
OVRSZ0C2w02A3J/UAqXNcoP3/mFrNRJoyWhnleO+iGeQ8yCQ6NJN9M1Uv4GJ2IszCuwR1N9eqeo9
Db/9jCqmvULHglx6F7HkiteU9XYu/81KNvQ/xy1X++tlkJL2L+yxuOiw4sJQch7pABDQcc85boXY
csdlzlZaiPilGAaiWFBM2WE948X+csuTLbagbgjPtQWW9WuIl7oWSr54sNK+9KODIuEgegcJdUmg
BJOYnPRsEJqa6tvG7wu8xjm+Jr9mXkONDUOev+ZwQjmhHDd0/yhRwBNyQK9b+hGRd48+ZpjnUxRq
EVwf+AUslZ46bXCVPFgD8zWZm4+5HMYYOkJmk9ijNxDt6vE7pkxpDMlxeDAzZOf+4I6EhozxmSHV
XTUZvyw8Irw8ih6LMn+VBUHFMNanQlNQm4C+5iLIFQeSmgxgauiSEaWSb1hbLbXgsn85OACtl2Rl
7DNFBrHvIi94TQk9xQMJnevaMfL76/8jipPD1+UGTVVOnEb6FBcdgYJwzdKvbcwbp3AbpswFXnNd
u9rTiLFj4nRJHCzvCA8VGzNo/F56aDgUKymSW3JZFzgS7jtyYXUhurCGkSoNchicWMKpubAGIJWj
AKdpOH3QbsarBj7qzTKNbYR2XPTmo0eMS7dTleJVwk+P2fKmbDdFCr7YODLdBWL1J9b+CgJuXubw
+nRqXiUF6xyfV+n4R8Z4uDLbWwAvlArKg4C1zyi/DQ/3HQXJnAEES4LBcrpZhjdvP3IQr3m8hrBW
5PhOm0uLf1oXmj7A3ZhgZtBk6L54uP3u7VEW0TGwYB/2bpBUrpICZKwYnq/1qyY2K/PkEIdZ7K5Y
IBgtnfXqS7JFw8zL52cqEcfktKLp6ApkoJ9OB/gr46w75s2/ApzF9bEfmIRSsBcJrWbGzew9IBY5
FRsgqHiT4h2cuX3e/3NYWblO8mMXf5BEAHJNoZbKvAgNmmDa8E3MUH7b+07K+nOi03r2nDP/C5dJ
NZhSZCU0baejMNyHvc727ooR1BhckKXgDM0byNNMv01wq2vFkcgfqo4RNgUIWA9509aISPRHbvx7
WdnghuYWMGKDuFrpgw1jeIYgVgvsNqe7MXOLBxwX/pZRLXaqkQ+E8GKvYqxw0YfYvrS9vtloB33n
6WsfbF1XiLa3+LUQzbXmGoxUHwmFNZef2ypc8kbf1Blp9UA3Gly69duP5oNcVRS6apRewqHHTPUE
Rir3dH2KfKkZ3gIoGQqGJQnO6G4oRRCDd/w5Oh0/ugYQ8VJHROSnPnDZ2gMHp0yMOmXoUBZerLpM
LJW2Hni/g5PZLPlR5GubiTkZrvbQdPUcJWE030NEPuVQNVHFsxqD0NBCpNNJK+h6n5uqc0ZrQK+L
zHCKmVob6NPF41vJY8WecgxXsyN9hdK7Ikb2oEm+GfWMJ7Ip7OMHsL6IXvH9pH/QypPc2mqkIXvv
Z305/RuX7rhHcWA6EisWVli1CYZhYNOAvWjOXwuWbzPPvQxZUbMF/7XgiKso2hz2GnhudM64Xh39
ywfRLDObyBUGFvsASLox1AoIicKPyXIal3CX7sMNATSgloseKy4FokO/CbVvddLLCIc+5CzY5CNI
XtJJ/jdFcAQsG2qNXP+6I9Eq73t9Ljza+QhEI/7sCwx8YvlQ6Kg80YDeMoTzd6w6Uz2JtHHHsauF
gLiGn3tJT/hqRGL5jwssNSmmcHDt384mn1Lx3VPFk7WC0g8ViJZjBq64XcvyFj3+GvX1nSdH06kO
oeupcOrvHfqtUttXtpfHhMahdhxM7ynJQKerFk86itWVxfrerGH7nrTLTCC2tFAYap5IONxKdCsm
t4Yj/5aDIbXTObcW+i1ZhPuU0QpinMtq0uXLfLJfiKYDE+HR8MpE9ih5qUKTsEY3fplDUclRcBEs
nqmuoKcR2gcqfBIWmNBrtjUi0NR1aQjzex/OH7FWVSa8zxy4A1asdOCffkZPQ/M5SAqBBrWxx47T
8tDFg7nC6dlMFvUgoSiKuHrRf33WtPlE7lecUaEP+tnGqHGbISzBXKUO7y3cAMkps2KIvptH6aMi
mT6h3wjdCvWB1FyE6X1GfxS1H780+dV3UNNwu9fAgjBgewHh32acpfQeq8+YBnAenRgBk+3xoPxg
b7nt5VNZk/6u5wlSP9rKyGg6p4eGqUzK1o5rhUfB48bHl5D5zzEu7MmRxDxxbI0CsZEjt+MsK+H1
6xSibaLEvMmW5eHlEOAefdIYMt5YmJk6e+yIt9ZNoELyldQqBemRVhPsuXsJt49+CK5KLGXLdy/C
dtQ1Lu9vYrLmHTWFjNXFD74PLLEJSU3Meg3+2ZEUIc9NCUqbgCTNP8Ahv7qHO0hUNyh5PfcVyUf/
E+WPLniNSYr0fFGqxRYLZvoXJqh4Nztkq/UxbGHD87VKLswtrd3DS69ZYENlVPbt0FMHxugv/Y+x
epa+QwUOJaw4mlh62/Zztf8pyxdT/t7j8QFR3U44G9pT226oAdqwpGGA+k8lKIE789OD/7PBjWuA
SOPy8yZt6rIgxvY207D7c3Vl+mrZFcDh8lWqcVWKeJKqB0nBGXjbb8U3WYoM7FFaBDjAr7b+q2CL
NSilrPVZn5Qz9eDFasLvF9CfFw+bmtgwB6HApA75/gs0oZQxLfhKTblkJ3IaAFpv/i4sdOoAKdI4
7uyydn5IGCSS2MYG7xXZBRu+hn2qzvJM5if6AGj66Z66VbThDRvUc9dsyOCAoPziBMj93CC4TICG
daRG4CdhjpxcY79CABWYB2jVmgS4jFx53DqvHtfgj7yPfjT0dBrIGfBFr31eDP4icFE//3RC30o9
QwKw8k9AqYx4Mhe7DP0IRAddwig0Sm2vIvix5jZDZehyLnzNbmA1vFprHhZcsVXniDj0EaajeEDF
mXVAC1/8WAEvDJxZVIeA5MRxZXbRxqdMtLEXt+qpfHEOahs+AGXsXfra/Wg4nUd+lAx2GOaA1ci2
dOE4hXMjVUlupwr2NLwRvwdHpEIaix8Z/P+Nw1ug1xwmCMpQoAnLkr26BBU30Ultk6GNpEobHmy0
0PFbkywZI1ZxXbDL0dNqUP+hamaDvXVQLoShbSxnCgYL8bOPCXXB+1Pj1i/96Nxt2TJQ8MJTok/Z
jTaYsAeAUdezZj3BxxqT/Q+m+wjY8evnlNedaxbZ3tpwXx9avdsofV+PXN0y5y5yfqyfMv2xVr7e
EczDAEDPmGpIPwOnEyEGsWTVozDDxRreKg0aGqsiwd+xiZAUgpAHk03HQlVA6kDW3cERlIW6sNzw
b59Hy8EMgfoUNQrhLDnKCMXfH5+t4XdyJyv7P9OYsWVd05WsWlIU/ph/u2kxrH0QoKL4cmVZga/e
pLR1IZbdPSc70PGcrMyPxTxiSsT43TGfrLLQtVYmGl6b98YtngVWTwyudTR1HKZUUW39LcKYaXV8
K7S6ySvD2Od8uByImwFSJXTwlgSQOI6Q0517TZDPfGNBSSiT0aQNVelwL0DzB61XDTpGPsKhertI
FYwEX8K++YXE8bhR2qUm8VvKIte+S5R++2eKbI1+1OG4MpGTX7wPwRyFDlrAAVqqwqXyu31i/z2A
Hyf4Opk7yFDRIFycy26wfKxaCKtXXb2yJdb5K/3ErHaKmt+JW3vnatcFUV3TVYBaX2jNc8i5tiCG
om0zj82aXZidZ/tkZo/KQ0q1KH3CmYyrMMnJpE17Zq4fE/WeKpVgebLOXxRtJNB8dKraTNEI7K2b
ZSKRW4KYt1WhIR+C2ISyEnq9DyWG9zGRgqyQRRDdl5gyQJcxGuIL2CdxgpmzbS6VCxwVzvO3j/08
LXErnSldhF4fFJcwbQhI6XqwTbGynPq02UM9Oj5UDyksZG2brLuAkKxBCgA2+XehhE0XAdeGQ2ri
LbwdnvX6rFUZdGUw3gkRx++7pt70fFNq1AeUA0WrIguTNDuT8liWEREbCo1xYsq7Pdhh3dyKJZfF
1JGqt8XcjMAbmEMvEXq9I0zrmmfhwY5lnRXuRKk4+QVXZ7FymuatKFI487YIojbpHevcUIG9S8oP
C1WOkhN2ZlxLYW4SujLFoG0hGPLx4iC5LbCphbx3as9M9oaHliRIOzxAFqEvnle/RRg2uOFnl4QV
mAzcrkffzbI0HQFDsn64iPYN/UNcdZJNLdiYzZTjvS+wgQf4cEJO0iU9ugq0E6093Ubn8XpMNj0w
ohGFz4d27WiOBrXwQ270/2KCH1LZnG3zgo8LL6LGUf4FlckDHCVQ0gmpU74ZqJr+BZLikTFEosaq
FvFirDiI/PFwK1M593kVysNwwUpXEzYkLU4pnvkaQCDgk6+kUggJZ4nUQj2TtqSZJhxOweQsfK9I
Ie4QPMFC5OfP7vGzsXMS/nd6dXuGjBAg912CfjluPlBXvCzSxysaDfuLMNIL4K7ZCDsu1Fq5Fgyy
XUZGRE2yCLdWyHXdxHbWWsFSGXfTHp3rhifjYgv9VFl2Zq9c57DLTbnU+aRR9xTa4k+hcM6wTJro
uOUGE5UjeWLhk0roWkmz4L8UynrXNj4q2/qzaPRO7IWZr1iDH2dbsPPTBz6agU6f8RnlMPUkjmYV
dqfgCAh0oI+JrGdX0EzLaDG08Fqx8exk43L9q4XT/TrTtwVmsAIAXRi45IpgKeqi2fJt2OgTPov1
yxqdxMrnL/pFe5bOAr3tn9Zi76j5dbqRcoR7mbbnGvtJsZ4KJt4b35i2PbPMQdKSxl8eztzV2+bF
ORQBvv0ik6ytANHziPLftExR6Ta2VwpQz4wm1PpHWE9a66iDjk9TcClYiVBR0AD+mlJ1qqhmFl5J
GZc9LWRCUei3Ze6g4nMY+NFZqsJnbNGMu7v6aMgwQql1LNgEcp0q3tfIrgwZMxreRjOLntcT7B1m
GV/KOLajpIZ039bwjd4vKvNp1ojVOs8hnUVlW8lJqYopzb9k2W10lJBVI+CTVWE7Vk4vV2XJEIuj
oUPU4Uo00Z5ZGghpDhg7iHnQQHqwgufOblroEgTWQBWkv3q6yBYtwFV+7hTF0moZvTlnIyBXIZ8q
n7s3C1cPAchF+CzKxBKfHzVT441LVAyWFeVcoA0yHzxjawUz/nPUNGagvAHcq8DHVyw8D8dtYyRI
M97Y4Z0GfUC4w2iKn6ikkfBQt05EO5crS53wCnNDa1ri32iFCfYIa5dgbydxvDCwtiNuZtMH6eJv
VsDJCYn3j6CWPplU/5wYdS/ha/ZIFG5htvpHULRrFv8HMSWEw/NZRuch5nahqrCpFyF0VQ/f2tPe
RmWWATw0WM7Z56esIA+kFgwN5es7YkzgMN/dgqqvyfJuMPtCgwCKHYgxToK0X2jMlCQs/VJ7EU/i
f9jvfE3m/YKrWdYbLm4MZkq9wPKi/xXWQVZot10rvAb+pUfWB+Zhotw5StMqB5RBOD8QZ1H8GcJh
bWUE09ECN7tYii1PFKvEh5paXx1G3ykjnIEj3Qh6zz1RZUDJcYEOk53FMb0amApLLsvv3K3XhJOh
rc+Pdf8IIrrjKW/7LJ6V0YI5Zr3HwhEqve+CXDxnrd80hdLVdz6KpwGkBD3kWShwqAiQOSKCZosF
PASFoHOBaoRu6vPt4f/ha2sn1zbmV/1bmMEC2P6gkabc/DZytYqGu279oH0dIutOpQmGH2fudJGL
xw2z5ob30iqfi3J7SafiFkDWh9GTJ9q3noJEf0xjjK1QSv+1TdvOuNQzH5dW4xv7CCKOxKowl7mH
oD86VBIBRxhy9CrXHF7d6wZHy9qHuBwBDFZmsLfu4jjwqvXVpr9efs5dnDnshUGJAddDeiZGPSc8
JFVBSvx4YXJZp6LoDGrPx/Gx3upHbqRTeWdnmMh7ReJyIzIVbfno3bYhSDgwDPBV8oRG697B4baZ
C88Q2ti4gK/i86m8QYqvjmWEvZvfa5QJbFyGdMr4ZB+xccU5rSwPDyNKmAGr6FH+PtFAP20AxOs7
j8vTrF0U82wbMiQ804n15n1CuMCRpj3EkoOOzVlldPNRETjDTjNTOm5grwSoTFNGpz9rsYue8d+i
vak6B0viAeXAsIW1OFwcLnjTOcb/U72+su1Xd6OS3lwz02nO02AIYyJO5YNSCYWAEJLzlBTnaLvs
qpyrFmnqKNkqKnvb1vG1P368a0LMj74bO/nbdbvoNTilD9s16YZfR5luT1c4sC3RKjO+XFJxsYSm
lbSvcU7bwxsEgo4QPcEmWOD2o4pJ0Xu3sagvdZGdtzIUyD39u3O+mo7DuPvMCH8VlOFFg88DPVsh
ztscVe8q7huyts2Fwx7ej5/BKpPFavcowunCiCwfUk6kw6xZZJRD6Bzs/ov6ctuVprMiq/Fb0hWs
lEjR4EULZp2ej7fR1ft+V43FoSXqc+Tq6KNhUaGAknFAE5/4SKfHKaID7ygmYyIqU30KCmRMQhGq
CLOnozI3xs+e0kthSBVPyIxdoVCLm/N2W0iu5qIDCLJxJhc3BUPeJouKc+rGjIDrmkb1L+gZrIrg
4kaVTh4v73NlD1Gjxt7/vxAEB/LtPJyu3SfVcJM8K3RBYWKxzSEXAPuohXOCLHwOqevFyS/jkilc
XC/U5fsWHW8ys1iBQt+Wd6MTKuW5EPeLzHGgkLmcyyqcuHVFi+lhzslY1uo+7hsLWJwA53GfOPCV
ryQdRszsmtbLNTWscqQtLky1vw4t+ZW3HQDpOEJF/ncl2A9Ynu5Ssk0khbwAgF3kKf7E66+gj/ww
sS1Tq7DpiQUW30qL5tEoSB4q6PIjFwwWMgNSDnp2dGTWyX8apbPRqh6mqALFznttd9xYnDg/rrmm
I2EAjTEMZZ/ja/QDzSaNQpPOshItrNkpBzxQBpIQPfFEYceUnycbAlZUhCtPRSgkKHDeFhC61rg1
fljRG+JM1tpE8fK41CPlSLiwqLVWoE4gXwn25rwcgROV0Waevx3jHULLJtAN0sdYH52zTyRx7uzZ
pbHPOyLpHCLKrzHARFXVWRQ3Vz6141yVg0+lIluwyJcL5GfjgSFZomPg5NUlxYNMhBQmknzToEoo
IR+S9wPS8oZyoaKZqMLDkasytMUSonPMjs/YSRyY9vhgHPhSyZHv8ClkCL0+jR1Tza7jdLgANU5F
NvFwwV9w4Hjz5UxRUIX4WghlCGXT4t1kAs+c2iVuS4W2wAWfz07cuZxNGula3WiZaJtW1j0nJLrs
M7xdMZpGYZSKVM70dKkLNpsb0jhn8j7u1D6uWy3hnIcwrwiQ1qfEODHkuRrR7vYV91i4+9T1j/uI
U+o5NAnjmbxeRwIHgtitlFATk1SvpstNGmxIrVSyBffcXkErB8dGSF7i5z/pSyH+nWvcYnmHIxmS
Q1jIM88r7ZKySrrM1oXvgmysKZUTxYjlEng1sWAMlkSHVKRF4I2PPSMlskVzMEg/3Xee3M1a6h0j
+f05Y8R5YUSh5X7EcagjYtuA9Czj9dxSUL9Sk+i8O2k2EX9SWW1Sp09BMZkn/9AD2K9HzMUgggu7
TaVYMUyEHcLQAR6yv9CB76geOaT8PSAXhjoI7/GvAz8cZ3QDukiZhTO6acSwCTSpxPF/RsQfiywC
FfIvt3X8ZwLp8srKC4+pKiWtoul2KxCSqTH6c6T9l2d3sD4rvrzCDXEJomP4txadephbKWPbDYpq
63b3ALHnh+KVrdEEHW9Di0uwlUHepKE60K9f24LeGaE8p8WTx5mKXgOe4sXoHL2irQwMPoT2kaEQ
gSSOGVtS3lToMbtTIca4V3o4eOcoOX//DezhHa23VuYtFNYWzt+HCWPwQI4zBvIyWs0dvJ9yIg2E
Ac37m+8lZYk3TeB4hLB3wQZG2Sbg1XNm3bMUdzsUsfwk5nm/k5hi+jyoPga4CzCxhSniKoV79mKt
bvwrBATQ8DV5hPuINiafoVMKO7apRf8bMUp8TVxO/LhaGUaWQK2wGyJEqpJ0T38cyNVzbzhBmsHH
chPsCpuN60985nH4AFkC/rXRAv3suvlvwbZOSD1s5K+ueT7TTbkxIiZt3pbkVzr/IaHVm+sS4Swc
SOIc7uUXfq+qDMLl7Qvkkq3WMb3IiXWHXE6sgN9l7qjIl29ox2wcKBTrIod59dZo+FzMb21EChaR
bQ4ZrIxD3nMJGLYbAMUDV2RYYHCFoDnjhEZPhnl/bAJt8DCmtXQFaWhIGP/HejBeRqKX2m6380bj
RyhPRs+csg8zZ8RQmGPh4A+Ek6Po573PJqD/KDB4BBVZ/jN2b9A4YhQPyEu/k8IkYjk5WSQqTrJc
PuSsk3brCwcT4IKntG8nYP+M0+31tlb9prMRl9ivNg8lL02/pJl1T1t2dGen9YFZz4IkMbXXA76u
BXQNX4KfuikaAEUTxebbKP8fI1lpqWnjR0r4frat6mR6gGBeEf98IDHmNHZgqi8AxJBMruek2Fp5
mJSliiuxJHcEbRQfeMJeSW1TRWf6ZF+ZIIcGkt2zfn8LJLgo/DGVFMQdFPTnRlKwoYl6Hve6XqXP
/75r0sL2BdfhrXeXgiAeqD9cRwA6vVc8KAMqwZe5XRYluSMn7v+xQAFM3ftstTZiwFpbjlbADCpV
esihJZYgVe7cJcbn8Pr6fWjF9hV5pIjJXsPTFGkKvbgGW8RUbCZ9kExvp5PvsLXkUjGS2iVFuK8D
uarvl4SXqL1ES/xfzM3lQM0dEG+CXp97loSioCY6i6qUD6+/SHrdpQAvyE48+T4TLJQH+SigmHt1
lZ2KSBMEwG9Jk5w9ttJZKWs5ODPhLULHLb2ZGNc9NQHZqDR6dnJQv16+B+/SD8GENOjZOcjU2Zlo
gINGTMTXD0yzUXafEAXMjALgXQ/WCxyxCG0wAqOeI96nYbWZjBskRnS5AVPOJWZM7g44XhHIaRxO
lxA8AK9RIfIH4QSPfTomUBGM4Vee76BUIjCyCSorMpgZ6BDJmnHlgMxx9nHaoKqGipyeVMglf8JD
9jDZX+DlV97W+DmFU23YFRDC80CyIFLjphDHKciX1wGJcQyzfg2PH7WTSyQuXxnIy/3NhPnZYru3
IhAXrX0pzB9JhIIBEQ9oOHhW7yWU0MPKkoBpNXDDCCIRxCcXul4om54LhoPHtqX08ebHJcdRPetN
/SiovjTnZafbnLdb1hb06bOkJIiL77Zkeg/DADX2bA1KxP7GiFt6NuPNsDxORtGaaOoMZlxukdEV
Ctb31f/C1eNOYmxrqDHhWSWzGhCbGD9YgRRM8wVy09FcLSae97sbLrB1MQDB/I3qvpAGjWuUFRhC
HLp6vLpG5wMDXVUu40yg3Axz9QZb1WsYbnLpNy3ko3uAnevKO1tqEjUmIChfii66eyZhzHpDBGRz
wB8bBE+JLxM2aEfYzFM6XdA16HLfc02hbMBeepeC4Y85rU4eumrH9f09FjYBsmW10zEpKdvqrPPV
gVu5/A93zoxVtmgGtorJ5QMwNO/+BavexO/Vj+rqHxlKLbH9pHorkqC9nJGiRIYgVjfT5ol2KXuG
1qFeDCpKB7MrKdaIvw0qE2UMTIgbuErIno8Z0GblBIgCQQxmoE8H88GcsdHPo16q3Zm34wT7Ic0j
y5YSEOGblTXQtqawj/ER69zB+Pz1PYyZ5rOHWbMz61e9efbR2avE+dUG+tVs838F7nw12svHo0rB
raJ4cwaS8H8GSec3LWZK5wxL/0+kyysGeAmcZNuJPvqPVx8YpyBd0k6q/yjqEXhdythvgEaH/uyQ
TnyQrsmPR6py4sPO2PtHLW0uBcr4dOyDxivHLVh2BnHr2cXGymP4sXo01FBTFLNwTLwhcYm10SHq
lSN3OBFry+Oc5LZuoNGL6sD7VyGBmTL7R+Cu7/qmaAb+GhI5tabx57zUJyiC6HvfBQVvJuatCLqi
AqRRf8EZ6MANm+Q/21OfvuWiv6y+qjUigYIy8bEOb0cExZtUpaElimg/WC65+sbwFRaScuZwafE7
nW0NdostcRQKCxaEgTDspSZIE5U5/iOyp6Vcfl9w6ZjvXuOcMMwWqWA3ZK03KOIzRlh80tM40+0N
H6VcPQVZnANaCHaJVx39LCcVaoWUmJ4XE70590uFSQvKCFacwCHZnbRpqThaKHxPveeG1oubVHol
Dqy4bZdh3Tv+UgYhrIktXJGWrtwX+q4X2/37psabUbOkb+Sd7xuH+7uZKXkF4Q9DMuu0MDbkokPD
SGCtI4tksASTNxnR9hU9L0xLbdj8o3Xo2nXCgA1tt8NfWJilvQTUv7a7VCWzGpcU5M/4TJwja3ni
yMnVeEyQb6qXk78NQEm/TgP6hON0j1gUR6JiXoPDL3Bqu7JXNm4qCAA2ZCLapXTphpbtShAcpHW9
sGUDGy/EmUNVgdP34a+UwaQiCNnMazYiVe46LAk5zoRFkRdBIq/wIOqtJ8QvAS06gYakdQMAlPih
AElsqsVMWUe5pRtzTvW6lnRdbcySwQyVogickA7shtN06YlwTAOSm2MSgXXciH3jhT3YXs0LUCKW
0QyZyJpHdYm2ww3mFGGeNofn3Xc7yjXgoxI2YDxh6waP7ayMaByBFKMH/wnQT1vMD2wAvxbyBlL1
Q0uOfjalclRQlclJuDOIOXpMhEANsG3kJwn/9eg9Rvk9k7/zK/bFGppD1fOpTeIVVrpjwh74rHpr
qU8QTOHWPAG6AfBcUYCdTfVU+wLimzwvdRqE5H5lvMkdPFnb75LfqlUpyFCBJpzQt4vCvD67VtRx
rgp+TUMwLccua24LjoPTjf4X1dPsou/6zLkNXn2Hypx94WIXgXX0cw80lDRyPLu1qzg1tevBrnAP
t37sOJfGIY+4vmvGfJb0KC/nfSg5epkM8jVEcvU+4crNVdksYVHMAfVGPTb0jQAAOJffZmWewylu
Vf4kYV/Atg65jKrR9ixun/4f3EiktaltUv+8h9sWJ+2rl28AzXTe4Ra444QU+XKDON2SwNPwAwXW
kkPFP8NGxzR/zHCjcz6kfsNEscPQlXvSZADDe9EI92ut1fBaYFbHfzo2sO34fCWiZWKiPiMkMYv9
rfT2dlHrqvN+UE7UKf5gW6lmfVW0obBkxEcA++Ax8ZzPSz4s2ZzlRktz8yaBqLhL9NmyjjGh4K9Y
wYa0w8BUnQ2fPfNlz2BEWZBPs23OpzAvAinDmEgQPukxL1HnnMxiLWuULgckcQ9Q4tNhE1wB4ygg
OFtApkqnM3FLd2BnIWOSZrz2skAYYxVGPQNjdYDAMdaC6RacOIZmik739hJj+ZRyjC8aER2c3mjm
4T+gXo/8VBpMzD+z7h//sPUNc70eHHNyXeSMnftVKJdThX5Ga5Qjo4rdB2YMmsf+q2xeTI0VUuWp
cQOG/3bCSnCvtdNJtM8XGADHuifgzFJy7iezM2IEyP/1e9EycV3ssfqbjcPkjwo/hOTzmxdVlk8Z
vUfaqpchK+h1z5gu0JIn4LD79YBHC5fqKfAX1miiTPaMCyt2MT6nD8CZug+eS5lB7OkmXU5WQfjz
ord9aDU75rkNc9KhfrPUhOOxY4jYR5/DFFgLkG+ZvO5+zzPSOkohF6I7X3CmHA+/kyerKXOFhKEk
w3HmEF/nK56ojPNcQNiPOHurILPsTrgV6UMy3BGAVJIM7s3nPF2afyxYQJOiujByyH9ZOqi1rWQM
B+S+dVpE3zHhpCfnBb7s+X0+H7MGfF0oFyGhAk/pbnd5k9p+wbIOzaG1Kwc8JW6mQuvExzM72856
2dc0scLA8anP9uQ73jjwR1ckrQPfgk80sKSVAhPV/5ZVb2D9cFHhtkquh2ipMmWD2w71oL+cPkcf
W3Vd6lGZL1Fp1GIhXoRYvlbaYHBfbJw/xFa21VGl1FvZJZ+bgjQ0zTQi3hz8ve2ms2nizS53VKzI
amOu6/bNGc0CZdbjMD4PgM3QQyoHJaH4fzJFGSkmWOrOwTfrgFAD+4GbnJs4lxMJFm41afoGH0yM
QvklukrckDfuzYTRZJlDaVeWKA6QivQxNrtmcxNDx0QkXvwvF7LhxS6HN9K6ycEPvkDBG/Rpl41o
uSLbcY3EhyRr8FsQLUG7PlZYejooHc/mt8ThKZAThFAyeT4EDidFGmbY5YVgGd21dkiw9v2CyLgI
uCnB/rl3rqYm3uBXLwjob2GiU5psCqcPfD+OY1uqliVZ4Go9tijoTf9GpxzlSRoB6nz2Zh7bfGrA
m26gGNYGU5DoQyuw/qFGvHm9lOCiHV9+dl8Jut8eUunjVIGTj8nMON67IN+/f4U0RujFtgcbiLsm
7cTsMkttpU5PMaixpczd9GLPBhJ7FTOSuqQgzlMnkkevqeeYj7GtPRHr+dR2lJV80yoHmVFfZpxf
ZhMYpiuYY3qwFVAtk6zDRcjJtz3meOM2hQz47TVB8rH7R73j9aJKoIlM6YO/RMtEpiKw/TidYQga
e0yVCTSINfA2f7gZbz7oHvhTJ6VC6Ruan49tkfmB1wntVr14AMuShngBomekEV5FeXZ1OCFdPzDu
lNcEks5f+rfT2WHHGk6yY7dHQU4ILpE/NBTfabZ1eR/CbIEEGp0nm3/t9SHtO5K7q5K9U8mm+S5k
O7eCH0QVEfwKXeU6rRUdNW3oIg7wAglZCJMWoadnwxqcjt6UMbcPPcs4L47JAeyGV21K1mgj/3v0
o7/yAJQ6MQuEjXKgf/F+bHPhm8Ex+ud8s5DejyyAOCpKaO2jz/M+xS71DWbvrJkTGnNecbKRxDQ3
h0nz/yl7+Q3Abzs+UZ0ujT+GN4NTN67LkbBGuU5qba+o7PmID0W/TqXRmGK5lZkbJNBdwG1N0WvB
FysXDqd/bUcVG167U9WxwO0bFIVS3Dc3f5RkF3PN/TR+eGRp1OkLYkJYwe6CRfLuWPAcOTt3O9pA
bL1kzsgDI2JxqdlRkZ8mpsJfURpPSIDLrJtW4RKiaVxxbYcQvIJZADf8DTMi6JAx3pOHeoXLSTBL
+/bSh7ejF74LV/01VNWRVvd3esiZUMmQU+Z3uxoo1oU/mWbaWp3rUK79BtnoKr/bOkLkQsA8zAi+
d+7uOUTQmnVhTfPZTK1joKqesdH5yoU14alM284x/ShcYQ5et9gQcIJK6Upc1f+reU8MngrE4gkX
0olRloRAKYrSJvXfG9KVs7SFUjLHK+9x3ZiYBnBvBHvKM3GUlljXCj9b6uQdXaxzVM+cefQ9DWtn
+0S34aONkf3hN0m5dacgpvFT0xlOO4CuxorRdQLU3qEFWufatRTcu/FL8vNTZePLck3U8PEWhc11
9e5y1uWPPnaAhJhg2v+fzkohNsowpsmV0Jt3Zlyt3qrqc/k6YkR4NRyfLFz5OYPoF9U4g305Leur
PR9WIXWhXbVQ2rFZPB+6kakVYYnrxKCZ/hLyEZ6uWp/X4R0ag5Z2Lv+EuY3Ws4eYsDuH4mxjs0qa
zznu4v8L//UbjC7OxX446tr1NnP/h6PtD/1ukuk98gm4485OAs41ijIoNzrfTtwpODEG4E9lFo37
I2f2jG1Obp7sI7ZbfSJzfbCPKwS6u0A+7ggsF/RydKWS/PojLG876h0stALR6OORV/1nsq7G6fb1
5BcapnIeLRniTG4r57d/Q9+xrHiflrcZbfYMsFyAVlsUZmu3a7C+x5Lybe69iJnA5leKhUTz6oLq
TmTXWiQnm3c7a0dZTSY/P1GxtmCwLTXruIU8NUHDUyVzvv5FomU63VpZXSeMmtx4wW+OKXodbx3k
hzFhFfT/1M3k1FJeMjDtaJw93LX3K690BQtVRVCU0skRIxc+O2FqqrAvxvMObazlCukzyE7AHZrf
2i8zUrDhLNHoy/tRG1ufoYu/lWDQkVsgpTiuTG7Mz+UcrMWdM0e2V9eaz8SCWGk2ffp/WhzrE0QJ
BrSy8QZjFy+zaq9ypbWiEPHIXM5UQHNRMwTUudrLuPcZxLbsv74otRN/E0we+NYNQ3iGz3MdoM/t
p7tiRQDUypAq6NBKXXn42HZUFQJ59gIK82WKjkOrh3saSQimgS+uZwW6Z318UED+h2w4OOuwCDTk
PC936hPICbheBYw8aCFcTL8vMT8NjNWCF0JaVzHSE8tjMlHog9zTaKikeNz4vEhpj4xAfPbl9Rmc
5GKbRB/BoSVzlDahxLISXM9HKycsB5BDPytW38fwLHppeLapK23E1F8ZkOvBqrWUrsy5OUpfJtOQ
HYq2FIDjQRvfc7EJamUgWtiuGQnOpojpm5yeMebQgouFVgA0Tx/jL9YhIww84JC07KYdiryCLIY9
UiY+58u0Nuxl29WA71Zk4jUAsR2WY/zKkHbja8a6zyZAi14OYLdn3mkn7Uq9263C0WZaJAuhAoOD
o8R5sgTrkHW4hxcCgw2xxcZ+pMOn/Jj2uBaxaTFsrKNKF+lEICbgNBcju+yCabL8sdUZiDYoskfk
wnCR/x9mPYNDq5vFA05QoraEFTBs+9D9Zz/DJ8PZqqk67T/mToM9Kh2CZYpQZyzz/q2Rsi+Z1wn1
zuyyVx3dDslezHEdW386eC2DVBwiUGMV84LlMJZdpjHMizrLSwtgMnaa6pXDRgLAnrC/8Nk8wBFl
3LHo5Czc0fBbiBEJzBAzYKcf/X0lvxl9S1sTRRTXvyqV5p4areGFsSa2X7QFkMvHDwgIxyp4qadK
2FTDRbIHkeEYtgDc8o683p9sF/C+Z/OuZfX30rNI1eT8WGN68U5C7UllMS3i6FJmn2q/1xaxiL6l
FNvDOlpeSpDglIVVWsRUzmkkZmTW5lpmIk/ZQfCpx6G5dLqVAm1A0VcsU890u2RsGAz7dlHVtOh0
E/eY8uwZpv/T5Wa97GFBClIcFsZGWvy6fAUq8DJ3e/CSrzAi7YHwtj/tR8KwlTkdll1+g7u4Lcmn
lJr+X4Xo9ZYT+0qG4Rb1Hbz2yed+sbGOU4gUaxYugB9quai0mVCjTipj9dCRzKZkTTNVhLOOg/mz
b63KJqXQ+UE4AGsUJYtv63Ae7zUO/kojZ4Jo7kqP6gEHh//kuzUPv1bKP7LjYgy6Xl4rDL1x9R6x
sK8rithNT00HoR1gTAdkoF1n8k4tiz2ju0JooFKom1/pWsB4KZgrVxlWiUnryvcZLoIcBudN9jlp
AkszqVUJgaTWf+JRxB5jBfoemxlKdzDUw6BjUh2diQF0rydE/V5jWClhGTxulksHpbmXBY8XXZkM
JcuWkd9CUhselYNOBIEjU9E5jCic1P+KjfgdYwvsOh4EyIXAhU+RESJjmmCjG74sMZ+zBYUzvGAQ
NRnAlUTJPDWOFX+PJmlucoLy2rRTfJMYV5S7GPmLfoPrOpLg0UsdcWSNFll6/x2lkRkeHNo4M7Ug
S0GmQCoNbhP74xZEKRHp1Hpl3gvcPRa7FTwjQ33WCotQ6jHWIqlwhmvmHssY8njkuwzjOEoq4ODK
uKEFV4Au+GOS77/mEUYKuVChk/Wdr3NEGRK9GSNNiaOCBKwZc0zlF6BUp6iqUhgRb8g0/Jj1tpUk
G7/OEXZvjp/JsSde+jUIzWBorUCO1PWytqgbmI9HTgAA23V4Gi05LPtRWC9yZGGK/vuZwW5cx+Hg
7y1uGUB1KGtoBHSGjvMYvFh/wtwZzfdYEldZyj3S0yaUDypUu6P9efAzelV53GEz9qduzb93Dh88
4eCYHB/yJ4kzwVpnfeYzirxsxXZjDH4cY3aw0EaW4A/vfXa/GFns8lnzQAiI9mztEbPu+S1QmH0D
joEVE0n5R4ACSl4a0zGsa8W36922f2jJPxNrZNMLeszPErw8yM7us4+vIwzaxrsVkSvcRRMMSI8a
xHlSRhfDyYwn347AziEoORz/lGxeay3JACbEfWDluLQS9uq+tH/8xXj4H5aq9d0YfkaxmN8y0UpS
FVPxg9rK0w1nn2m3r3qc8sPUOD8L4MXygtEJQx48We7A4iRvPIvm5qzdHQnzm4im63VFFUnz75p/
cU+I3n7McxxvwsXbT078XLJieWWkn9caycIFTGt6FDYlfP+maz7oUPTsFbu71syZXjqeP0CzNwY4
sOx6g6ecK7DTqBxw0v2X73FEpLN30KOY+lD3l+Epi6WV78cJyDQTDOZIwihQjeyyErGQ4+eL/2qX
RFl9jl9/T48BoSxowPuPxF53rf6wQsVcMOZCeKOWOX2h920YC4KEhYCkAyTOFTPF7KdDJzLzKFbR
FMKAeDbWfidSFmrES23FRXnmi/7ZfTaO6g75mukweCBBpYAJy9se68IVde5YOmT5vBJ+22VnUXWR
2icj3dHxN7d98qFEPIgwOuMfwI8tbNEH3ike9aC33tGuTFJrwtw5Vmw8Sys2tpxHn6Xf0llPWrMd
5r98Nb/oEDcSFkiLBp3s60VTDVr9YwDd1WuJdKUCjjvPf9WYesJBH2gacUaEhIHUl4uqqQ6nf1uS
28J5dZHuqtosidR1tJ6gsRKxZC8D9I59NAJFHL/g45bsrS1nC4Y8brem1mjiwRmA1e8i01cWuRWr
RciPQGbHzWAywPqD7/2LBB6SkgWx1g/JoAMlW+CZ2gMVM9hcHKzNQN/Y71TcaJUvy8vx0XUW22Ub
KS1hCflFi7Ix956L+fbKADxbxjfLdlRwNGGBFUGNFaH9MQYYLa06axSB93PEvEbkQZdGYeelZtVI
1bAxerVr/SfMMs1YGGnICLW+1GbfI5laClYweQbDMKkSKmFtnG1OyORNkycIHszaKsOAnTWcb42j
UBkW7U6r2WKuUOG4PG4BQKlgWuO96UTSZljyHeN84oy+DFo+whYk5f7lYUEXOY7ycmXnX8ppLXLh
8l/ztAslcbhZiYMnLAvlHu/PU8UyZL6h3V9+253q9MKZ63hOFmCEOlbI6tf8QCCxxEWq9tRtAqrz
dSRA5RoIVjQyCQrNVtbIcRCmOfDOnHeORd52k6YGbYlySC9QyjLxqIeQhjt8fVzR4Ir8jzbWt1lf
uflpJj4l/Hqj++uKa6SfW7kPVH86pdMDCfe9Qv0Eyf9qLlLTCPWLlj4MPa24bO+dbPpBdqpep1/E
A8meF7S6m0UIG66F/jKx9YSdnvJ+m7ooifeKBklkMNOjTG2GuJE+YvHD6u7BeVQWr0PmJDnIouRd
oueTjK1RO4ldM7H02RVA3PRm+8gpkvd+8big2481nzNtrKSp+UYw3r672zPemftCNctNEthIoIre
EXH7Uqtg9JKyBN1lqkwS8lr+2C3/iSRIxCH9GHwes3KO5jNzvNKSx1cD8JERn3+0m1MxLDh9aTUI
7qZwtMQzkJr10HSThGQP11yDDZ4nuLTTmsT8VST9TsAavp0TLMG0rPSREolyZjMBHz87G4ZI3IUH
A7faafydS9ip+nPSu3BPFLsMo7/5SmfgemiSQbiytSLhqPijV/CxOIUI7ZG5N1PY3olVJo7MxpYA
F8Ol14xqnoZ+5f3eF0K3CDoO6Rv6Er4IPyuG8F8rovRJC7mV3dz26h+cp0tgeKcEiPnl0uYE+qAX
pCq/Bl0hvjNQpHchN66I5mf6LJDHk6hkNEnnGqA+lPN68+loa0tDPExSgZFrr7HXQoAwPXpbe59C
kvusOJbEfNXL0+CPLehOUes2QlgM8Etz6Ey1A12JC6bStInMiqX/gUYGx/oHWt4Z4E+2+GCWhOVZ
oOIf3o8Kh7IpFR5Sv+zkGtMDGIpzsMJgmpoJ/dqQ3a74JBWm2+NApL+ju6PgPDhRmj2RVFmtPuFg
QvT27ihN3D/rSaCy9qEmWLKGu9l19NyQV3AJv7cNJgU3NU+uaVBVeRSnnXPszqadoc6bs2fzbCWu
rQ11hCY69Qz0XKva07Lt5va+VIaZx0PdPsTmk/MoGi4HeJgoOt1FUTW56O2XQtcn4dGBVdLABfwQ
mW82gazKSZVLq4T+DcWjoRsr9Ps9xTNHkMIMPhjjjKqB3g3wlw5k6lCJgJzWfYWA+0HHxwaip3nh
kkVgUQWX+NcmBZUFhLMpY/hFadvMp0FBkr5NI4pYSQSOVMg12kXzAUPI75XVbEK7Hs0opgqziw1m
8AnuBJFcSiMa6nsjDaJhdoUQdmVNfehG2bHlfdy/uKtd+h4isApF9/wzrhOufbU2QqCttRHs8xuK
tbgvTpwrR8OPl6QNTme0wOFSDybJdrss9g6woLB0rtmuwarHkxsgctr2lYWX7dJW3e9M+Z1gekq5
MyQ/RGtFcP0YM+NG4zVYDhbMxshbkyl8ZySJUZ/ZJ+uZKpSFO481Pbwmq0QWQH3idEkxDxrHEmht
RiKP/vdlqea3qoPUS7mYHgGNGA6KxOMw2m66lPJbVmKYmJPiYWClt73tHeCEFBuK+Bnkxl6wTYWF
KVDySgDEmjdZy/IsDBR3KGs3GZwnZmxPOhOS5bjsLvgoL0e9Hn6EWozwzbvxu/hgijCDSmQrx6ZB
6Ps4GSKTqIwkJSZIYWSWgeDlIaU3Uif4gyMd2CazEGWsc9tpAsZhuAzaaX/lSN4jD1hMmlLhgDJ+
6OEv9yj5XehFEs1gb9N0p9uIbL8MoqZu9OhQij5d3610V3+xpXBfyIarM55Xd2hm0aHajjKNl1Ed
t8XycWl/qfNoW+aKPBmvXWGVge/UTCXm2iZNwrtv57V66i/vFu5xcJJ9368dFlfrqYpmcPdwbqG0
8zEkYrlD92Nl0X5q4E5i/D0TgAcHi7pq5fOpVJnu9VjKY2vO//NqWrjcpmbO1vM9QyBMt4mUXbry
D/+QhNbcxaHVk3WOJROt1OuEETy5o07LMFdkTzdVOY7OSzM5lvA55/ycJ6L06piEoIwmncLI2y9a
PDb1L7GdaRuUsvGkrM/Xh08z36ic0msK2HDsyxHWPPlF3KODeG4uCwzywZZWAU7yhwEd6FG66Vq1
7gM7QhHWSRN9yrCYbmzVSJHz+ALBW+PWL181Y9ei0Lgv0UxLWe1pAqcNwQ1uDoVovZgmJ9fkCifP
StDMLna3rbDUdvNu7+jrHHpOaRHlmAeJYnqIWHeXTv/ac/nyC9ZAuoxUniOyGc5qxzZgDDACpHaj
Lz+GZZdl9h61r7fYPNFhQnim1Jmzf9vDxHI2GjbiH9nqjMllVvXG5wPzJ3tjFuqE2D9ccZ3hF2hl
CjyEgkY/cz75qsHMWZpQSeV7pMXoN/HBHo3xnCAv9kUgelsg764GmtgUppWQjbabwmAuJXB3FAuh
CdxCEPn+Hj69JpxFdzMndNBP5B65eQ+QWxkEyW/Sha864KBdY+kxdG2wt7vdhoHVWh1r69vPb5zg
VBL0oGndTlc5OaLpS3h8uZQqsel644CBw8jK2443VjzxUsmUrdgOUstrXnyU/TVA6Z/ArieEsVff
YlNCJIgvtuHyAo5eR+HWeU5JjJrEO+fPtqpTlaNqkDZETTdi/hsQGwUByHaW/Qn83YLC30v6TmIg
MsdMplwj62zEgJngkDZvtT9LDwSrfkszuo7A4XiXFLJQ/ozt8sB73hot5kbWODMY/j17uYV/nEuN
cpz5uY0SJ5gZySfA7KU7TM2W3NqmFBkdWnHLBtJGEO2ZkDiY342C+bhF8gWtnf+QMl8sPD+nV3cb
AkN57uaMmxO58G47InxvLiFCe0qrJErURBJqFD/S4uvcknmiXI37SicmDWCFZh3/IuRHfE7SHkSu
an5WD/k+RL8Exm4uWSL+O5H3ulyEcnLLTPWW4SWvnN6rkqg0uukpB7fSaOPzzM0QRvXW9qWfocLz
sDj02mEU7NEPbAVAdZkQNvQeqd3yXSXleJcTdTlxxWDup/jdWXtm95BumtMoFa+rOlvIKyu95DT7
MJOCsXOoBBLUNu6FfKuNL2iKlZMCNEsYweWwCNIEJYyjPIQPtSI6ChXAi60oOy/iWQXEBKONaiqj
SYQHRYlobUhneIEQK84AcfjaukszR++4Ry1BflVz40qOqk1hUq2XgTpQ2kslYVaNdMyfLz+OyxQi
qXozkpDYA1G7W56k8jCh0nF2Gz6tiGCxneT2/HGdS+9jBgjl7s++P41lg2oC31GNhPyAyxJFYcN7
2qyjGojeVKPBep6oYIhG+mAxyX0Zo2LHr3czzSEFc+4KT3DBzo19AJdUzYakRY3SVXnGutKmWYgG
MCnnagBS+KaVD/i5XROL+9wsLDys9cUMVC3BK8YDAL6kdKrKBVSOap9vgmEkILX4bKVJqSalz1Sv
knHHGihMUnJeCESFqKD8obEGkn+kKSfWPzg53xGXA0KXPFaF7svrE3/a6tXTsUCvNdkfSifYbvdp
vW7EkwiwIgEePQp1XbQlS8glS7JCSQXZG72pjgo8uLZ3MMPgxzLhWjMzcf72TlhpG9/KhgNjNoNb
idqUAk+pQ2kmaHGxrxPrzhxkjYrvLu7D2juhF/Rc6VJzzG6jf9UYZTmCrfWLVi1YyFWdaBR9zaXF
2pfaftHoSbn3vxJidC21mIFGG51bNOoTshjagBuQEH+WyDQhLRfjn8AOlDJzxGSkFPWIu/2BtX09
1hNpY0Xh6SvoSXCLcFW/td3CJqCIZ2R0emcQz+GczQ8SmRB0V8ruLdibU88791beRpG+w46geRgS
AoSHdUuTA2QI5SutTUwVxEL4vemonTBiczX5uhcRgxMVIukpIvWuggfIOTV+d+VpyuxNnO0PKveO
pSqaTA38PEn0Oldv2CsoI2yeQ4QeYbHBrlHKfDy0iCQ8ZlI45SajoI3BINHh0gg+Q5bPgpzrNOoe
m3hkZ8+TYjDhzBfygAOI2JtbhM9HvN9an9kjNM6k2vqgQEguW1ZTTatrt40DZWNmDthJw4p8PJkk
iwAdLBjE6dj2OziiO+3nvPBiZ1u++/yZ6D8KwOjVkU+d/kggD106JwHhLkAy8FdcyZXDLcM06nfu
LrPe1Ezvmmz3tF1SYjHAO+fTv9lv/sCgYbGgiZ0fVFLpMqNY2WsHvPJrarp4HGldR6VjshrYZq/p
JWI1j1GwyaMqVAPS3fdepVe/r+OcYZPa4DQGzLm2fbfmMQHRXtB+Js6/ZeXlHsraP03LEiLgw/vT
kGaf3d8+OauutO+Byxh7KzivQBpQubD40EuWvoh0hUiMubp/TBgfghkMk1fABFiH2Uxj7hPC9j3e
SQO+obXW4R4dtwcsdUBIKtFXMyn/8DFESQEB+IGTGMXmN1Qa34s6fON4JMfhROBCdHBRY9Beu3V8
SvnSPs6tqDCJlnaQe0K7oS5deSoAyRaGeYR+zonEzhOqdotRXujKZnZqfsWk5qY8brCX3Dlgm03q
1DG0sFpVNIdGdQQQ6iaM89k4g/5PothaZhHHuMWUok2Qal3afOt/RfnRBCRxdyGl77nwe5d4vUUZ
YoZOiM2zkKDBz4+Hj6i7EtRmowsv5hgm4KKoshWTEQsPvL/KgyUjPECn/FvB8lY2fLs6uHMccDED
MVWErMTf1HIRDcRr39afJx4+aZeH9xAxbo+2FDoVvhTOASyd8p14mGrcVstIcAJRvJuJeE+qhJAd
tMIoFDDa/wds+ju0vbTNUDTY3rn7yLLB2j8NRDU5njxjij1iXlGUi8wfz/SVouvhl9mw904v1ZfB
R+fXZHxybLzBJ5qSw1+8YvyESl6cStPnVUbz7igjoP5M8mW+6qhkBfI+gprio09WZIJW8g82ojZ1
6aBP7/WOvGLJN7t16iRTTZHKjwfBEf0B0LcX0kbrlwawSgEK6SGY+6R65NpXfunC1vgtrGH1/RqC
Ew1mnVPDfw8wLmovDZT+flvyxNve9Yz/GPFwzT5Qx7cQXYIGeq//qwJ9QP1+vrEvZ0fAmpvwLFOK
rvULffoYio0wuxrtKxx2iKWKehMJ9Ku9C80YkbcnQZb4IGbP1bhgEBbEJGABhADxoissHOZQaeY5
BHxuMcvZpigdblrV4bVd5s92BIQe0ORGIUAFsyq27dFJhjkj/J8SMNstGkt5utXaQGalB1mC8l8P
/cLZCnCz0CJN/0vMabuQ0ROT0JZHCJq0KMeYN78v/46c4ToBaBUcmzCq4BwbODrMD+5dqZqa8VYi
p/2EpS4NeTyrIVVX07OJI4JQ2YS3KP0pr7daNNPRh0SVImfPLRw0ykGI2JDw6nZq9NJIa2c3/1FI
7YXySuHoqwjzF7VpEirDk8xc+ff12OEkS+8t+w0yPLtLcJL4ohJZzM3L8nItupfQ1up7ZY7HXvdI
jcktfXLczISilb04VTC93g7xg9niPd2CbhaDuX1r4BixhZzUhmqLoSBIl7wRQupQ4Nf70+SZMgie
h44IHddFHTAFsMDAec6+0/wdknhx993M0RwRvcCT+ZEZUT9tDCxoN7culBdPuKAfMzmgOKN6EZ4Q
zGDPP36wrj4DZLJc/CUWPtUhFh6n/7brvo0fJsO6vCEDy6v/4rofAOWoembgZgSAyHgrSwKQwpXT
4/ibZ87NJtqAorWLjuxV27xygZaA9mGOItZ3A/HOZlqnpYQukXL6T/BKfi9DI2zwN8wKw9LwS7TY
OWNzTIuQ2RidBdZbcoJF/Q7Uzn8lPEVofMcgOJMZ6N+ph7lsLy7JPx4AckavppRNOSKhrfLKToNK
ku4jYzrh3ozHuW8D3GsTWqBiACoQNdZ8/0YYS+9a0QxCS1k9H0mOs77v9Ef0Fe/n+YZlw0UtpOBM
ovEWO1MCH6SoQJF4mYUvhMhQM1aWwuOzSeX3gB4moc2llyPQ/0eM3ZIj/3gF9pdH/HUXoyFX3Bjd
GyxGEh3Oyv+td6RIPQuYpfhQ/Lh2fLr7BTEegRM6Q17rV2tNeDFL9Li1fBWwcGSKv6alHxG8BmH4
Pyrd6lIfo76raN9vBZFZ+ZxmKO6Hff6o00se6mNHa8GSL/dOwuF1sGLUE+WJ7gG82XQ6bQiQEZh4
sHCNlzRyBJVp8XqJRO8wsklwyr6/Lx0nuAFrqtwuT2kS+RGJ7F9qrNY3gRiHY76qCUxp4iHoj48o
pJUDyy/5NwWSuxOJZIJ9pbaIf8XOa8U3ywQ52L8r8ErmsAR2WsEVFOA6K67O10KNXaz4d5tJHetC
1tBbvfC7zffzfmD7uPfX3ZIIjUEr0AOxZCyeQNbD27G4sPhMDFLAp+Y/Hz58aMYS75FhEURCM5jB
oVx8NBRZva9IqKsxddsQa9D49kgV68raAbJXuJoRYBWtJk4EPT2ymDZOYJ8GLNjZiRpgvwecwvsZ
eK5OUA11KewWC4MQt0HisNHyng0Du/38qZYot9+WpsegLBRFCMNatC/8fUoqlXQCfWKVEsAC7R9s
WMjIGKwveQKzQZ1hXPbZBTN2fAtGfJ1xtoDXUd9u8AO3R8hiOcgHiWBulmoAQ4KsTY+z9jtot3j5
4th0DKoDd6hQvrvblUppAwQg4dYK5SEymInerTgpMdqH8wxMwRxtTZn0HBVqe6ftaQSfj12+N5zC
JTe7y/C84Ucp1Gmj61KnXa9DYR3On7x1f3tNoDNg+KBjzEZVFB8bQpGa+bjtXb7MGRO/c/Ts5EB9
TCYRwLjGYsClXJX0xLjHVGwFV2nUsLq33uBOfoxIP4c9MTCWZfGau15RN6DEaCYV3eKyd+MVmBC1
UkjeX/V2ZyaztmIlr3EjefHVLSgqYAH7TpxSiHaMaXGGbOF9onNZX2ssjIl64VPwxJp98J4284lf
P5kxaomK8HZhKuDIgELAx7ThDtvAWNy4df53quFTZROj86lJVtY479FgkBRJqRl0TEU76c491MF0
hc/IzC4a/nr4EdGXow2u2mIrSv2FoVKiVLmXCNbvXOw9jraz4l8aaF6MlO680dNrMb9L/qkJnu5j
o89nbJQ3tS6QyVVsQny1E4SCGmrXNST3Bti0c9L73Pae7y99BwAnKbtQU2/QHDzFAyYQQpm/JnMG
7jbJWPX35i5p0mwwMqADoyIIVwy3/e5vGaxtaVyUUIrZWgjgDChU/aU45kWq8ZV29iDTpE5vtBf0
X207lF/IbRg7HNsS2rbFMctIHKnBRj+v+7aMiREO28bVEqAxsNw5mkBhpFwVdU8tAGIp1cbxzlyl
tIzBO1P5mBc5SSawH+Z3OGCQPECkyZVFUSp5XWbuVEjHOcvCUz9dhT4xVwqXBI/bIV6lr+LGnx1A
5xDK9jm97NgG5Pp7kKe/0n34GetTGAjxmQBR8lPtHVk5LAo1UJbAGxXTwqoC8fKDYhxfH1Hm9inE
UAhGbOqwxD4dGat+pjjy/mCy3UWmNLrksY0E7hpRvto4dWuFk/23tOGo8Ib0wWAU+XdtGwby1M5e
sclyUE8OdowWJkyCEVjt2GV41ULimxiMzthZnYzeDOHF7ILHQuyEsoq6HHH2sgE+ZQJw5LKgy2qz
OJH2oBv0LthFCnAaJyaJmkoM/B76bVmfxAlEZzlR028ECivgA1C0/FbxxYD8i0li/pnLdrou4g8j
FcBSUc0a1bFa1DIRIpPPGaxBoaizbZB7i/++ta2nvOXChpQg+6DH2T3J72WVAtxZxd+6tD8OIhnP
DemnWkI3ulZdbKr5W+cvhUEzsplQM+uadDs1kxtnNnjlznXYlFPPEeJImTUReNNovoSRlgxqouXw
T6RjqTJeYoEdz5xfoXpUN6e6Ei5Gnl524646RM1BHq6zwas2gTmZz49Ke+nrrcb97ZsHFWe0NuwJ
ZeQ/EN4ak722VEaD7oxhAx/3bI9QGWLZsdU4AuT8RM/po28UVCBSKRmaWRf5SUdB2cCfR+RHP1Ry
0uXzH59PEU/z8UVR7XEQXNhppTKiOT5zBps8IgFS3EXUDomotQHP43/iwA4CkA1uUHLFcg7zw3FY
C9UZIYGXGRWqfdPRWYPPKg9cxkIGJB4NjzYrcDpAVR+V5TPptLYy0zMd/fPsRGGIMRuX/CPhL9tm
wRl7ZDZ8PjZBcn23NfyyVqFUcpLeOCEx1wjM2saaYMo4wQS7i+tExbeM548Q+ggWYW1FJvJvk3J0
kztAjdskd8v2N3xo2CFC4Yf/3JgUu93ZyWZCcjEZk/SdkMN7gpAL8KAfAxfcPwxSK/APJUbBb7hV
oNwXo175No72mieAs34jT6BlJU2reDfpkvJnBib8sFpqDcq6Dyi0flYL630jZ9fVbU1+tjeqXd25
tslOZmBAHaPzZEwNGthrAFVOe3SQGd/vD8j42lAB3j63yPMGsl6/G11KJMD7FTyQ76WVrd0rEgeh
OlrC0HdFgP8RvAZtTLCVACSXt9n+DP5AGQkN5d2m2dmzwsMh4bcgnju6/X+aOT9qMphqtcoYX9gD
LLF2bdIvAWrqXVpN4hTORVO3as8VC+o1v5eYaamBrQ6t0VgAjjQwRwGdoNHp7+yTZJeYXuj3AN8s
FLGFX/zP4+cYtM5JB3W08Rlm5uoSSHoDA55HC8Z25E+zz08jBX2cb8fTzUG6BbmLoim8Z6sTmJty
PolcAfFGn4auN1W3pCM8cnBDnL5WZIQhFpGr80V5JiTqD4AUdr9ZvVTqnPmfenpanRp0dXthKOvz
7piFN9UFMyD6OzOtftUEk+nzuNXDOzle0xgmclCtvg31m99Z3XqGdNbGI2dOwsuZZw/3G35KV5qr
fszAX2EK15R4cBSNKwmx4JHWRzrp9cIyCl9RND6854Qmu4uxjUujcuFAUqiKme553Cv5kPm9Wcjj
JdKYV8RKYPuM52riy7R3gRscQPiI/Rw8wEuJuE9zav/CqyibECiBfF8xurX2oEepU9cU3gAmpOo1
F5/IfZ/h5nvrLgt3iyMBIkr2sMNYMeEkNaxlDn9jo/FW3m87VUcHK1Z4glc00f7DwPjp8MIbpukS
L3W8max5Zwzw9gwg3AgL+qlFHQDMRO686lGx+qCXF3Eyby5QFb+EhCqoUp3Ooqu1T07q0Q7WVOdJ
h4GN/c1lQV1hwwUpbDHJNxfJn5lUvlWpO5H1ggaDjEOMXdK8CdFzxUuD9NKWdrniZ2gs6TFYxvRo
c6RUpYXoDOl8WUEfwdvN7kIVCInAVJ/tcqQOJ3mkuTQrCMidLWE7dTRSAIyd4rFb4C0aWDusZH3Z
v6FMd25rolemsJHN1LQL7TEuHVGexsyFUT+z/B4Y4MQ4NbuZVFdyS/1ZwjMUG2+5PSNe7i0Yuy34
xHJ3pCcqxGrzEFwLx34JtoM3G6+h2V/KLE0lTl0ShB0iZbkTqLJDWQuQUMjhC9SJgz0gqwylJWzB
nrm9KXh7y3JgDEgCBw/nu2wH3EhvYUbocpFiVotCZWCK1bx7ZQWxXmgzVVg2RAwU5qrUhxFXptDY
dNaXs/Tdn/y//4IZy9Tsv4hYP/a5jtjYkNCD4d/vOZkPSPvMYjphwEM9yMXR4tUGslLZKNEKT06H
cegQ0KcE9uxR9QUUnfLvJ5Jd+arbWcmHVlX9sEYilA5dcJOEpJr1+tEY1ERBivI29xHhsgVISeg8
fitJvIZB9QfZi7ayEeyG+XNfnwhR/wGhtJ3rd7A71d5F42HCqI7nuclNvaqtqxl1pWKLiWwRzBTo
CwVBMopcPRKCebaOaNPwOX/gMGMObjJed7HQcW5HKHNJndbH/8z0Sk699iRwjPASY3mCCoXokFnl
0KSDddKgrWx0CcCj+k+HcorD6ljEAWTMlRQ7B/xNF2+cAELF3rrfUocH2NeiWv6evfYNbk/Qe0eR
TH7Ov27NvNB28VvdM7kPFcPoMSL36ikdJkXYxT8+qvdVggUYXx+pkmYQN72X4+aNgce9GvFRlnGR
hkPSR/9qO/Wi1BpikIF0bk50zw0dh5V4tlAJacCLEbhI9eijHi5uzy9eGtE4t2apyC68fF4IgLuf
zzXUuFo0wB8x10igKMESKqRejwQlLAfcGFP9iIqyQeXkXhq7MXfxkBbvlpR+TilYzZK+hx+l6Xbn
l1Flv8BHln5EAGFHTiuPrHP0INWWUGsjV95RMD3W5FBc0//JjV9SFZXoX6fIQlobIRuTuZpFXXPd
GKSJYpA9hZpT3uFgIQ2ql7+040f/2tV/lB2n/yBmiqAJI9tD2MPoyWWtpFp+V48OPlxVDYaC/cHr
lSfMvSk6LlPUl27udCNbIopL0+Z7+XSav8WbltZRUlBSsTyJlYsCbuE0FAlsTRtC838DSTQht9XI
fN5qEZ5cLhHWDtaSp7czEuucbG3MYT1FpB+G0b1MJHiyUyo8FonpwcJ+YvuZ9vUQ0u8BuDo/yLTR
pXqmaypfCQP08OQfG9irzpF4sMiCt9b7QbvcEIwhnJKRcIJhYe3C7P+xyKvOi3Q8JxSE+2lTKeKk
6fY7lAj5Qui1We8DOMsUWkpNnSHGI0l2c/KWgpoLDXrdA/FWROC/zdbLXNnjTMTFkWa6woj/Xm4H
88V1jsGnhDACg+/9tQ/hQErySOvrwYGaN8Lgd+mchcO1twA4mOV5DUc37GBm9LsKaFfdeKer3o6G
cRHKjqRFbmzD3x4hK7PRGOepfzML0PiuH2iC4LiuAvrCMaQLfnt+U5XWaOxd24qGqVoHRwecP997
75NmYi7CeS3WSY4OuHgpmUGf/SLBVMcJVdWG7XCaC8ndaTMq4l78zVcORF++V2fLTqJitsHij6Fp
XZCH5fOFfC18AhVz5vmsP7YaNc3oNmqSjuaq+PYUDQ+UXDytw9oNYUKavcaapxbuH3qJ9ADEOFLF
7eRYyl8K5W7WFvEiyU1xh9UGgPZOgHMwCrazxBHS+VahE6h330cCuuDlWmGdVq6T4FoNzm9PS9hv
svhEKCJqu1BdIKLjIxn83JmT1Fd9tzO1N9lxiFB8SKasKqKu6hZ/idMgcW6qXdvbsI7qX5F5Kc0I
E9Bt4Gs+Y1itk7JcgQ87vbLvmSaiH199IW3HrrLY0yZv6dTUZu98MD/Y/SFDnxChDNJk7J0a/Hc2
a4XSH+W/H8XVfnAYjdqgs9QboJe0oGAou+6dP7Bl84wtBKXQT0IbLY77rSd+hSjl+UspR4tozzzp
LVyB8FaaJdBzZvOtErOfzw40SiQkpiA2mWkGVoHcq8kpk9grG6y75KLc1qjsvFhcBwWbYSZpXucS
qWFMOuLuX/m7FtzaCR89SKdBxd9rzdUqXoDwmRc1lEf0WLt0i4961y5iAtUhT73prs02oni+rf7i
ZmuhaujiQkeskrbiHpHcE+TWO6RaDBUMxEXw9LCxUv6lHqcVyl1DkXH4FRowo3WSfFmW/30d610C
2bM6GCVhk8MTTcU4Oz6ObDvCVp6l53S4yeFwstk358LB8MtaS65BAO4oLTEvr1Sj3k5kGavRJtGc
7UgZbMJNWLXlTV9Z8hFPaYledIHlHXtDha7zzNInAonghalWFQxUx2kYShX4mHMi2m3mAAO/0poh
+HqnvKzmPfC4cOqsS/rZArBAzxg/gbGyj6airWly9cj2v3iNm93QN1QKAQhl0DP+lXz920v3QNwT
NUbQw05l19w9vmc1GDG6Td9uPZSAfOJZqtWjpqKc3oBUpBfgeZ9GNlExB3f222eevauHcnapxu0s
vcdTnLsCEl/qeZcNI78A9ojfABNFq7fawAAu4zVn3dGInhCg4+CDOqCjsquY5leCTurKaDD+GYw9
swpHfFQCHJwIyA0KInrQJN+fj2EgyRasYxdqJI6oEJTrovRYjUkV+zDR3/7526tZp74igWnpSZl4
wjpGY7OC4CEcpeppA3RNDmkFW9B5tlWM6uJOXHBL+zA9oP66JN83zAF1I+wFzdzc5LwgERwY6XG9
0wuf2wLM3nCYG8HHE63/K96+G9fjNd1DMUkoOAKzjOXXDEsK0xeOqRj+j2iQQaKyvdL9/HTxszKk
MkxYEboPQofZEndRdc7Vg5apSTo65rQbeOdHXlEe6Knd+DBku/V3EU+ff92iMPlXFodTAlqcVJ9r
Ewueeiiluf9VMwzQ2NeaI0fJqnMuc9bXApRL5a33aP8AZriGAqfXvC12VbmDWXWsqMCvj+OAeAX3
eYoNFRAsoSghvbBQDrxZqL8K8sa+1KcznH998hUSKLw7nSBpNy+Cv6nSv1LR7wo7VXgES6tgeFOA
ALXQwWr47xaZQTYZlcTxHPJMvNOFqFvs6JB1iPetXiQa8mjbFO49pdVT8HIy+CcB45xv7PMdtUMf
M1oZY+a35MGDpdngUR0bA98jk1LtmvgMdXFROLYMi3luvnPw3ntfoZOaHsXTK+N75yPkATcF5wfe
Llbdj192Sz2NiK/zbm2vZx+kJlfVJH30axSIWtkdqIGaqHnxEhTWpCFM7j3vVloPiAlk8lxsTyOr
To5S5F4raGg36qjpT6SsTdY4aT3JM4LzEQ1DcazGaAdtQp9NWGDoXMf68gFRvu+PCpJXVBXmPiOq
HTfGRUD1pX0OlxnCNBD0qvU503AXjoLd7V3AXWjPJHfP+YvnETBwVQjKsVr/pbfHyoDxHWgd7Lqd
H1/TaqOOya5z+TzleFDHOYFK1wS7RVqZpPpeY1MMjUxIjpFbSlKdRoheJh9ra8zvmOLls36Z6wif
gBx/mC7g/pnULjdRlozZdC/63CK5DaBkyr8muxBdIcVAhXPiF/mz004VVK836uMV9rel+N3iLc96
rG4GV302VBDwDg5YW8UDkGlkOBqsdtNtT/grBD9cn3MXRObuKLFi9pQoso5noFbLrS+k7jl40wrv
xk/vy5cUgJK2nzgDct68gV7CKQ5UYvZGefvAnwhHye0jhEkQ4pZgGCgQEfiZPouT5pz6IPniKQgS
60VDLTux7yw8K/wgn8vXDTpn+ZPJAFFdQfttBFC64/K6myHmKlFw8kfsRpaYcrDxer4aYUPSHJhv
o3g+G083ZJ2XC2y4q9E3qOYQDdc0W64N8w6SHilMdYBKewnFsd451vTlVHZ93Rlpr2OC4s2b0YEX
LUg4e40hP6/wM6B9DhpkXYY6dajKj1SuEUeIlCzmPmMOdqkgp2NDnLq2cfp+E+HaI9r1aKEsAEtZ
A2x6HD78M8KxydG+UICTxyyyoFDFHp1fvthbVIn3PflqIFZpTted0C+kpw7TO6h5bKrAsawZZ9Bh
dR2Mq6M2JFHhFwFP7U3KK3G6RPTsLGDhao7Y4XMnjlaPHZjTGSVmzyd7F8lwjzf17sHuMBv6aH9t
V6E+odjA7bybm33LNENpzFmAYKVW1KNsYi60TF33nJEz4y5p6A2xwNp0W+AVS3HUdzs/ZyTQ+rc5
ozLKdvByeCENGzupoMoKLVTuQYYtbuKMV0e7H5V/uO9PCpDScPeqYvrgTgQFuBzzjxXkNQ/UBFVt
mRfZktaazE5Mq7HzSQhfMmYkQjpL20rvsDjJ7H89VfBSXzgz7yYe+i/2LAJw63uuIBfneC68psoz
GzAcN/kqJT00QdFZ4ZE4QN3uO7zKEYpjipC5fek5HYIStMhuhloOL5oCFqaF9ovvI73DGuKMUCrP
gjguyvHGxUmaHvpFyCRY+JFuc/Youz9CJHXojynXOGRMMnH3tXJYj/MrsqSWOtru3+pFgvh2AF9m
d+YH78RreaZrVgq6vXfgQHzSCwsUIbhoZLQPbSqEnRlm0P3LC7wam13WtSvS8KsU4Q3WUpAUoLuH
Zp46s5iTaQ5HWwi6DrC2VSYwbrHufteFdnKvYyQz404Jnu9ZKXbJDMTTJKcxRVZul0wbpu+9CD4B
VPk4Pt/oB423UZfI7oicF/QMcjAHfBjskEIrXiTT4NzxxW2vwczKPIEKIwO/7YQPuv8wHX1RRjzi
znC7g4mUPBtNIUcyBxUHHrucC4Iw2KQtohz7Oz80XdB7ihmifV5HENCE8X+H5Yu4OddIvXopqQ2B
Z7AhbltVb65NRl5LiD+pBiL5AmSKW48nmZBsBV+qXk57oGsygfaNURk+ycXkqHSzMpNkU8CcA0c9
O431MA4B5df/tXOygEdtH5aTCY5rKczZ5/HdZ5rB/E2zBQu2L777EImWAaKs4mfGWDN8udO8U1jR
R+/LnDVUZN1EXYQHZyv4XVxf9aIyNqCKVPDdTf72P1AzBNJRhaWPIC2Q63nGAbA1DEwRo89lxXDi
wef+7UxKoFvF33D8c3XWf/q1WUC6EweqfobpRLoyWEHIaR4oX+NIgXw3b1dqRK3jacKjY1a0tgoi
AQiKKpJIAuGBEQUTxPDB4jNM6+FS8VRW7PWDPYNzlL5ocp9lN1oYXoDRKA0fscnPOH2kn9NgmIDs
OLCDfXreb40KfTdXNlR4ZG+iasLkTAjh1LuPrN1Gpfez7jVIkaHRPlYAtj9WFy1fGFHPu+JIqD4X
nYHXqKCo56V4YdfC4OPYY4PsbBuUdWr3PR7jxznORVtW5FvR6h+BiRaHX9iMXnG8+bJ8KxPYwCug
KjuYIEmBVGUSoqgxqK9Cu57cy6fM6y6SnQk3WBCGsj6mF13MxkT1egV2V2ut9gH9YdOfp+gDFFHs
KQAUceUiJQOIYAuF1OeHkkTQXQRnOueO8XLFE0F7SRAEOg58COZsWqQbqS4NKplZ7MidcjKi7u5E
lYrRN8vszqGMgxHwXOegttr4AbMQIKj/Ml5OzR5RnXuJa4PwsWgHnmLiTP5zZq3/bD8nft8wRT9i
9FLZGgtR5pymNtancstCWKqFPHdYhGU/xZc90Ml9Bpt5XKN9EnMdusboce4J7rjYAfEmIwlnCsHh
tQhvTTQ/kTIa69W0+qnLsv0IsGJBoTYssVXdXn2H/Op/6vTUk9eIbgYWuXOht/sDzhkW09bzOnA6
A+2VHVLXpPn/gkn4ExQFN39UKWOJOg5UU4a2sXTg5s9gUJtyCVOBSdF2T/8gnwKyCZ5JZm9NBh1G
JUTfwqFRIO0sgpiN9aigG0F8d1EZmDGKro1Nb2zSyYLoCr1gCEZqBDgB+LGlW2qUXVsXHkb6W9fd
v0o6Ckcy6Prrs6h+3BVgOb+xyxAIY2iYZWolKrnubb/sUw/9nyWkFKdBXIUZq6VsgIxHBbKWzc/3
Bp0RJ8oXN9rOsPRLyjW4eQGV7qmAsJBzCu4R6eCnwu5WwOCFVdudDnOZ/Z6GVD0mjab1dLQ0eM07
XYRXAIhST7499SPBKzZgRj4Vuzt2ZgnLyRyqk3ql9lYWfWvW5gZUj/Aqj424wshoY5/jkgMJXjxh
wkbkB3f8Sb5wI8r7x4eAsPlyFBf9nI7xfzBKET/LhW5aPr/fDE0DLBALZKnKeyISOVaV6NH4vKRk
H9qwWOa/+jhm/cavwuu7J9L+zxwmPHUQAID2K4LY2XCUTnEAManbN8uhMgXJ1xMmaNQJ0aCLa5B+
TJWAmaUupRi1scAJAgCDfPMsWqUTapxsuZCXHCALAScHViyB0UBvtEam94iI3CUggBg5G5ftNWZf
/RPR+cwHvhr0JxUs5kPIXrwKFMOEFcnR8h3WRg1y6pojNlwvrL16PneDKWnV3hJ7gMgJoD6/TQ7J
tA/PJyLiChpEHtvRmpYBBXLPQ0lRNEgGPUfWEmVtyOyuY49pY7N1cgfIEHY3hldBMl8EJcq56Ryu
shSiQqZ9tol8+pip1nA7NBcwgVazm+vDF4/k2dyK5UfVRdXqzvx4xJT2NsjRadY3R8JjZ08fYMxK
9+sHGwBLphQ+fRIo1tTGKf9WDvKfu7aRWbrrkmZGXIL7SdGaoulnSkPhfkycigfnMzrdf22lG2t1
d5OLifyKgP8pZ+2nZmt3Bf8bPL+UOBh8NqCVo29dAPZ+DQk5Z9p6QQshQ6meKTKA4ezyosveSHwy
IUDt2Fkqs2GSfRA3t6jw5Ws7c9PoLB5k+/i64n/6eMwcbKdUoe5llY7ODLGoZtgnqzO61c3igETk
iONR6nKbZVqs67OkxyD+TYNpifIrbpDlfOM2XJi5ABZTOr1Boh8tNT4KkfPsgSxVYK2a2rCQvGNv
7hvIeynimfmMCp/Dw3i6itly/eWJ/87ekJqtsLvUt6BIE/sDnETS0xUYIFWz1y8cRMs32cieVrVk
blKmI4rrZsRyDEnoaRBVJ+zQrsTJ7k/vCdIu/9KzWewj7FtGbVqNTRmc1FTkJq62r+6uK4ZZ5zrz
KgCLE0YwJdmz2RH4ZZnc7Ex0jS5UmFH5hdYVZDj+JdwenpLTWsZ17T8LR2PaGwrlZVRtR4Yw9wGu
HddFt4DD4y4mw2XLUWIwn4nFL1W15KP5Dv58gZZsDhfSbY7ObalduzJrToXT/S2jpRBBjGVJBGS3
Nf/1Tk/+FO8kNUEmNGWbrTKfa2lfu4AumfPkIELhed+oBt1VJMud98jv3MMztYwYsnbA154OwZbq
q9kCw7WjYTQE9IOR7SB9qM5AR/j1cyeRpGuD/Nj0r2MpAFVvKn+IdXzl6SVE3LYbziYq9wF4TG5H
2ETWVZDz9YO0Fb+lz3EqLM5ehm0ippZq9DeDxC8UyYUBYVqsMrJ5o3Y7WxZGLXQH1nZsU8209q2D
nqyPVJApQm/tDdk8QngDC6iIODcJJRGBj1LH7HJJhQaNOIXIhkn70W9pfWMYjDSna9FTuMjH7mdl
RbXXR+h4wDj21YgBz+rAmnL61M3iVlhF/qkqgZMOs3wzDwDmfOSjneq0DZy7W81YNIKicf/jqvpu
NBjEOOik8cQDcEvU4lO/9Nhj6A7rs/0uKF/6MUIsJ+oV2Yq4NjbxSbvtCEWa1PyjvVLAGBNh3iV3
N87n3uRiiipqzOM/eTr/Ld6d+btwZ/GRjFn4pwq1v4E5nbzxITpcryt51I5GL7NLtafGJB8Ot9mm
70j1oA/H0ud73zmP2A/MVFkdmoELv9xOfvAohKu5mDR9RLkxsA4Q5eGCalpwSZo9DvyEmxpCHHaA
/JUTc01bWFSPIebzCxfdMpbTzWPFKTczkm4gEXcywr9dTir5qr8XtrPyjND2IEz8/ruRzQpljB4i
ol9r6CFfkft1DbsswQEB0XTyb8RUN6qACnBgtnzcHIY4I5ZaaOChITT3Se78br2BliKqcUrlq7KL
or0TrxMY2BEdzVfJWdkgO+9xdFlHmBX/yOu6hIF81k0CI6oSwCImr50EA5eeQJft1nGlYcD1Po4J
MgDpxBK31N9bDkhCcrKVoXzGO8XTWj5LlSQ/W7Y230cvFEIhsYbyszvIHpbfDRH1mhvN4NY7EJcC
cr0dD9G7jqBgw7YbWzL925oLuwhqVUx/R44S4n6ggbjRWuL8SLWpRzVwUf9QcqDiACn92v5C5QNd
3WJkz6/WukEzGj3KXdVHVanHHMn4ovgGoyh4A4BOFsERsIn/54kbzk3M7BgY/WTXMhoiJzQPfdbp
AizoG/IbhTHFo+b7h7eq7Qn/1fT0BpHF9lGQmIK2doVYUegf3o+CqydncNqIZ/vzPgEMZ1LHazcz
pL6/ySvgEXoXD9Xi8ec7DH325NP2DAueoZacHRc7muZafZZhOmAzgPcSwQC5juzdjS3HPK9VieCy
tihrK3DbcPxKzSjLgyPGOmPcWza8wIA7yEmg3d5hFubPXV6MITAQjTlXCznIQ0b/jMeMKRxvzBqB
Z3291yEAsRJhO+adUqRaGwBVkbxHGNgo/GBB/WFB9NIm2iujRqWeRv1WvRLpwvtQAujvIUPVDcZL
0rlYS+VAlkpOnOicmkkhiA6VacwXNwc3ez6jEsnFSC6Mp+H2F36GVTIbDlP8vhjsbtEdnX1QySC3
goWN2Oerw1X21SIPAOVhBUIq7qTlJheJsbhtpJGnC00cn+38sOqU3KsBR9RatBYAB8FOgMWmNrfB
aQIftXQTTqGJbUMs7reUR5sGcC3ycJbRCnlUfAsWTs/lm9BUwEylrZcsV+eKTvDlh2rDIOJA1mGo
HNgNPYSX1ZrZECMAv7lIRnRS/1rQYTbrf2lq01Zp0Fx6jDPzny1G96wKwk7FevuGR7D2aMYh3ffs
2mFnimhjt9R8LSmUu2sxcqK+ro16Zl1xgSgbrrylba1WAR9OkzNpGDCML/VdRxcWprxZO59ESWXG
8/kjl+XXTCA/jQbeLlj0PmKwScEKiHKfCHV9MaScVACDAuo+CdapTdvG93WBXNomLMY3jquqtmIs
A3XlE/yALLpF7tF9PGh+/NnP82kaJQ941448ES262+KZjyz5ZSl8al/vymFYvDPNnGo87TJZlO1e
Knr/RpoDbdV8RuwB7ZPj3QM23Xum2cpetoEfHEWEdl6t5lbND98kWyQvwPT++qPkhpE50dXYwzbR
ACaluJYssy5APPT6nl3yiO04hgoWrwejfYSZIBYkUm6/ZuEhm5kDn8o/mniNd7iCOPxQ9TY5uQYt
+phrLtAv/HY5fV85ogteDnTl64nL2rHGZBKPpgHckiE7JsgTfLuLjUSZlx3bEJclkWgBkHQKw/DF
osU5xBRSUT4Cil+OAEJcopiB3ye22JSczMlwvFphcSWQcTvwlv1ZT/SrjFV1x0YQGQTg4VW2JI8U
U72DGuCWg4hdChvodFhQlbQlkmdtihTiFD9Ol9jOUrZ3AvF8vCVzVXO8M+4SyLRcllG9l22Ffh/k
14HrlkBGzRUSvTu+XzC6rmkSa7f7DyRgswbeEAyMNIgG1vXb1TYjXHj8KhuPTpU+pSde0m12xJIB
ReSlghXL+1gU9MIL+4a0bB77JVMvFdzzUU3YjIGdVFpRL7nzSDneK0UiOUaJFAunV+X+HUQdwAiC
6oZrAW6yPsycRMSYine3zMOlSU3+BHH+J2F55TCnG3rvTLTLdR6btoUv0awZGBacjY54cgXNxcy8
JgowOy8VVsQrU2LIR5PhJ52+UD1yaWZzHh7C6Its8bpvvGWzK75j6Tn1rPlBQuUgEmD6chp5b+gC
mOB3kLlto/xgwzCalgfxzn0X34cCdPhAUK656BSA9+dGNh9cAKT0mvKmFaLMJVE0/xY666uyr8BC
k0qxPXeiUrvteEvj7XPUI3mUx+1Dh6PfO7AKTW3Q55O3WKdcs4zUpotO5mIMpV6tiHvGrMSCjac0
kgNPWKXoxTjMj19OIeSr2EN+qEsSQB5WLC3hyz+a9fzhtMBiehvR/5C3TBjIsQffiFIsPHutgpId
zWj1u6vkW0dGV0GyhiqFqtPF6TxC44TCK+3TUl4XIfZ6X+97oUvodidzEud0KIB3/taqZwp46LfN
vCjYVhfAmKOQyQ4Pu/43GpRADY4x9c129SITIsFcQ0ZPZeloem6M3XW6/VidXgHlIHpbR4ozZdID
BWKaaTCLWH0rOMSc6maR4TlRFbr9d/TGuJAbSFouHXQE9QmhlGF5iP8Lo+6okb/LDvCyP/aicUrf
xvJ3+7qd65kesm2vzMdX+dVviVYzKH8JvgkZ9jUHIXJmJ2JAHMWJFuVKeKQxU679W5uNiNUbtowi
UnPy8HS52cf5c3/JqMRFZPu2viuQinfZHBvQxVkamS6TWX2cWgWw7ugHCHx6UkAGJzeBA0SvCYXE
JNcSZESP6UUfF2+5K7vS74QL9J3VGt8/lv8Gubh3MvNzOeOjtVTHinYpp6gzQsokg/VMcL91uxC9
vYJd5A6XrT7ag26tAWik6lCEHot+roeiYIMymJxxJXJ9Ze7Mk1rPmB5x08sqmTImciChUKBbgK2M
akwFNoHaHFEoF3U8e+4lYQADKFfMPMTYKqOb3nhAIBqB2T5Vv55qh6C1YwEYffjcQs8DLOLQBNg9
mgOJxN7GRd+HZ9UNlsfCPE0OlkZTNhipUtxDjBuy9tApwkPgPWVeYse7LFGrvTeVjKkosKulH85G
CwcrLb1xREx2mHQip1b9xq9AtAvCC9GHM0bgVU/3gsLLgLtRL2sDwULSjrN4sxT5loxMst4l26kT
oeoOzydqfQ0wcfbrQDhSvTgAYJyxX9uDCCJR+/GVQbhFMq+ZNjByU4AVIwJsN7H8nXZtQbxeS88k
Gew2gAa0/s6EAea/0uXfi18+HfgzkY0XVY+ciFWSV7YIClGIxZx3zTHrMGhhRfpkmS+78bpTqzi6
yZ+Ws6r5ofaZ71241cNXezoXVMBPPFJfcw+u6e9s+U+VOApTxDijKWUlSTSCv525UyzwcOYIEzdS
J8r5VFc9N85nDF5J8pn1vYtKdwseY6vn6rzDXO8zo8dhdS0FAS8OBLbXP0pMG67aapC6a53JqzIk
IJ4/sE/UPtRnUE8f+EZgcxg+4GlJAKV1NuJX92SjIaWr9ECaW1SWzyg8hsv3JAG+MGccbHBXMqXc
qXUoaQO+f3Kd4gfXyIcBSrMj8gQT+3Moy/jalBGoRNdPfUcRN5ElvXPkyR9wJX0z4rOrHP7s29Z9
begW+F2E4IOlx9A2ONRsSPT77dc1FQhmm/4ILrTF2mObxgEc/d8mrq9+OdlfT4wdDOZw4QJaAbov
RXl1yhCdmYQALFNznHynbuTOCV0T5dXUD2REEBrOdj7YsGGNU8LpsfNg8Y6/PyufIWqTsd7jUQ2q
sZSNVa+YbeTQTZgT7ooWpCCsLxKnE8E35PFHoMXQdVc+Q7Gptf7Ciqk98AX9le9knuP8R6295vW7
MX/8MesHJMLj+dNT0Gi99vQSG7WQanO3NclLojH+tdKDKXQEp2kk1Tsx9hlE/G45v1gsoHfjGtvJ
jwGHSLPN3n3Tlmnwhe4McBR9TRlqvwL8iqytpP89weDt1qlQMs5dYHDdh9BCiJ6KjWgPieeqKw73
ZSPtVsxY2u/RuUQAam7+UgSgCgFljZcMPvSlEmZeDwlobzqyxIFkRZRe6vUxLMYgBjj4RnYgFphz
avOv3W1zEReoV+GsTHsazV5FYB4lL9Orr2q/UCIf3wAv4LrtPra7VtsD3amUfGICWnlWcVQmUBms
hoTTMycVwq00XsJ30I+pWkzk1uduc0To+OGEB5U0wrBw1cAkXAhFYsou8YDtMuMsuKIQfIXBB/mn
SzrgSHjDjsqOo5UMpeZeQ80aNuFA54yrvEjzc6TYUO19WlECEnjsYG+bynJ/sx3hCKd2q1NAxQHa
z8WyzcAIkpr23ofQm5WiqicNWe4x3LMn302FermSzG3tzHh0bMnvYBfjhD/yuhmMaIeM9/egAXGs
faJ4Cfa9Skg8s27Tz7X5Sh7RRnKlq89wy/aAlNFmgAhaxD/qqk5GF1fmFF3Z14a2eFC0Nz8t9Yqu
XJwfiSdX7Ca+lGPzno1wB8VlKb4bVdisDZX3gPSwkpVgwoWOaZA4c7fqK6KkqCDvMciS8Uf7FBKJ
ehxNLb8kuKK9ydHn6sZ9keqzqgKVrF3oOxVVCqO0mtAIe6sPVnZ3AHccqlN1h23K7fKN06iiFl41
0hXGPCGKyiiC2Va7yjH7ra3BVLQFMnPN2oVpbc2tGaV9hJ3QdUO+zgVmsk8jg/yRn+KJCIuksCy5
kznXZnDj5xECpkoda0lH/8yr14tLx6EoBCqhvCLybPU9jwWM5tdIYkVX3m9asECEfggncITYU5LS
oUSo6YNlvwBQVuKnIvyldHtsp+l6wx7YYRxCwcng2mP71uMCLiuKkF/rm9xmwJqN2pgJlZlBAcW4
6mBeUEtC3a61KcR04ybScBhfTSM8xEn0ImjvI1re5BqE/D9MRI0P+nIeb4DHDga4hoPB/4lHIfSV
PQaXJlZZkrw17KCtwINFgCbfxeTNwEJoX1oo6SR5cKlFog95064wgkpoqXtrA4PgCfLIEGOZlQmd
uvTBJfyM5kkDPK4W+zhlTpVpT/pzHFRl/bzccDSj5uOoVRETCEXFq6JbhQRmOK+OjLD43NDUP92o
Ym9wvRO7wZHA/wesTRnpOiL9xHiwmgC1Yh/cvoCoYetEbEA9KgQEnCj7AS+NUoJmoB3C7sFGKyzi
X3ifvHubn2VE8cgZIU4+WR7QnAuG1njvGrH8un/KL/a4/gZzbmoVSpU1ObFkTg+LK/cWV8QTaUeK
bxhBU7GScy5SARQaDdSZ2JDEl+J3yV3t3aHVksop48i0IZaRUiiGp265Inq0eo+V5Ukprggd6V7o
3FUDg5U6ecrNYzQDX01GKD+1X1b7fcb4/rEYNaaegE1F2DGOIpMDrnlXV4KVqxqIBYrxnq/gGWXD
QPx4VAEGQVKKGhDdeh5mf49ANZ/Z9H3/Wj4Slbi6x47BeWnrFTWg2WpLAm4W5dM8BVfZaDAkFa8a
aD7vc3hZjYaIJjmF6TxVdRNkJPmJlKzVDSSj3pdkUZRVJ11Vsdlo+4LKqrQIx3rMtTfbWgAfW0y8
NAIMGAel9VEFdfR4DMHqKy5X+6H9PTD54+byTdO0So2NA/qyROHGq2FQ/tNnovXRF5DDEmZ97SaH
lQih8OP4BOdTYbx5VVHTZm8CdG+OZmUwUzPMpv/B3QCbhuGrhgIf1zbIlLuQmqZLqdOrSyXKY8Ti
3VYVyhQkF8cRGcEp13d3TNFOqAOsmDbMLBkd7h9u29ff62721x7H6XNKdnXBmc8sU4d62bKZ6DC+
2QrNcpbyDZhXv3t6rax8lYZvVHf5643UtXdwbVX9FL4K/knKdMYfTtOKFapcFgIVt+rxCMtjzACK
yc+qQuNkqTxlbJ9KtXJW3G5+4wgem+gi0mJG9AWsI1mJkD7Hxj9UViPEk1B16AY2j97vYTej9Tjk
glZDTnuKWDhq85xo1/z046272z3a5o0r87475kqDLRI84dC+cacp+765UvUXija8EzMnLBI6W/i+
XUR5+IfucVgjQpmKlBY82Cg4+pRzhHe2zlyh/P32/h1M+UxT0oebYsXpCR3RuE7Y4zldnCG97q2x
Qh1QZus6/cHAo71Fd/Qz5NdOXhMl9R1ihfqQqXr/PHn7LoTAkyIrTVgAqEamk3T2r+X/i+PPhd0x
FihMgtoe9Gr0iV6MCVdOGWM9wvxGu8RwO2exl7IkI5nxcJ1kn6FE2CxbDMKKDZa6o2RtMELlYCoi
dZwK9e2Jq1rXOyud8cbvEJw1dZaSt/1D2C0ZYwKrTjl5FVOxP5G1VCMuV7i7Scay6njfE4mKw1cP
GW6AFaKsWyIrugbmxPQCx+dvJTVl9PeRLUhHMGmIR3y8LBw2llBVXmj5QD1coMYsjwgPt5cUnxNX
ZRqg0NCYNp4InoaaJIp6VjdjM1YCMUaYef3NChU5xBBzULGi8lgEK0GPHd6YmVVHqNgvmGYJYEsq
udQxfWSU55oCKVkTqr7oNdPGdAdsdr0Zm9WJxYD33wUHbM9Om9DviO8ClcjxcVJSZNas4Up2eIOX
xshI3HnyM5l12e/T/guo46HRSL43cTxUhnSKvRho5oGWnBKD+qhxgSzwkP6QiHHwNnUrWROWRg9z
iNIenusov2w3o0Ci1Fz3nbUnGfkYqANHZlJ1AGBgn1kzjPYBdAhQfgd+OhFe8+4CW/tik0pIGbiy
P7Os69C7CrvgHOAfLLn0MqkTI9rLDp3P6vhdNaTnrWYPAvNBfXDhQKJsw2enPyitvCRmR0Ny3XA2
sm9gJs4FZIDBOqTnpGYe8wh1inGs8hiPdD037lKjgb9aCMp+slQO1Yntw7gdRDvAGIeDqqNwlguh
zNGX02P1zSUC1LgLNkexzSD0/IYEVesDUgLKiA3fDLkt07qQ9yRfCtx9BmJ6Y672x3OvATk2q0W/
TJMYd3EyIIMLOzPEQZgZzq3ueuviArGAXAHTzOIiqQiWoaMwlIee6lhg2CQxbBI3Bxy3f06SMUo3
2iD7NLMvbBEB7U75xw12ZLtGFMzpeWrnauw0kWof4G6IXvTRPhuHQkEUTW6qPgoP4munfYwtvMxa
7+erJXFpqqI9lfv1ISwIOo4Bfo2bD0TLtTZUn9+SiydD3pGl+gYmpRGVIRZwbYtb6dZrEtk18V7a
FtInmhdx7If+BwlYs2Obm9UkxqN/QVHTnVyL52c/6IDPhbgfRaJLpJp65kTgiNo8HHV6+gCXGujs
xq+U7wwlIAaD+MG0ojFKN/YoyNf2ePVgCIIPyetXVsZnt9Li1yxCESncKnqq36Tv4KAtTbeWOtew
SWu/Ul4N1txmGPHqds0h5xaXQSGvtFAOKSHUL+IFmLUKxW1u5NoVRNc2Y0YA8Q+M06r4MvddV77w
j4moJtV87CpFeN/tqgG8Y8TZVXPZjnVj+m5KU8qoTn5JpfwhWKn3Myh5ln1KHFD6k7lKiT286j/Y
HKRlvnKEHOW8m4PV5VoRK6VvGrThh9wGLMhjExbPMUKH8Cxql1DCqjMNnhqwOUPznqA5jG8mShFK
w34oAQqpMcznjzdBcighMuav7hHjM5+cSbYC8MscL5h9NQkbj5bArKpneD9ojSLuooyJnF9DMelL
ch/EP/SpoQcC4ir8oJm0T8Cx+8PuHlPA5x4dtvJlSYxwUKiTlGWYDXawN0gsRUif8ik7vGr4J2gV
WbDeCvXRs1S6uazXEiftFH75vgbIvW8WBQTv3SOLXcq8gFBdCjPJLbeCgc/wJz6R9IpqhtrC6Wxq
wPxhNw2K60HOPQmoySNx+Pxk1VA68e10jRBtoKGrqxoLlN59tmKMJwCJZdMEFyNQgAq50HGabv2c
VsK3k0iZq5YCszUfM8V63yZAb9Ov7cettT5aF6TmNbKW2JKNGE8QY+FH0S1AW0Um8CKFmBAAPAxT
pSzmbAKHmut4Qave6mcpJJ7W9zr5L5oeFpVIHqfCd8YqOHPIDFYw2hVX9py5mhUNFZ5S/qRqoI2d
52iPo8sLEly63Sk5iF/AchHYxQgbgzCSWeF3HmNKGP4rQBDW/UXzIC5wJ0788MoAQ/D+fuVYiugp
zUOvW6dHfj+GNG6i41/B/IH05HpNwvh5q4DvBXwH6/YzO6Vqg0CQ7KcZ80fDp819MvtO3C5ctW5K
tOC9WBQtHF86OvrxC7jqLKO0hRIOZWs+z8LXnIWMe1IL4y2/7SCNVBoAIWLM8QNFECap72YJ8mb1
0jB4gnm4N2U+W4qaMMnRRywBHEfmOx+5co9vVUQU+lTbaYHth6nZZKjBPzrjZfzOcco50PYOv9dT
GAqzlCNl8or/OzMW5/AQSPDnnUNHMcqq1bzQiR0Si0JvAdTrOzOiQws4lLbK/o0z610BNSkJ/xON
MATf+I5kPBZ046qUNoeKFUOHH7NqUgBKQcD0p5CGc2flzZ0yIad1RgI9CJRZ+4L3Al2gd9ICvsxc
NR4Txhf6ay7dt/szTXghm2hO3EwHd44lWLhUM1V1tM6qPrdXCLqv9meFN5Ik52bpE9WDuoj+VeH7
SjbuKsGG85iRCIT4fQZHRdoLeGs5PJh3kgfyoB6SNhPvItw25NS7eOMFHuTPFZq6aUnAXEposhFm
ekaBzSm/UWsd6R3GFiLdtzOKyTOjcXG5vF1EvQhRfo3OttvIqgq/P3VtuXK5s/M3Extdkghgye5v
0ONBpYr6av6MzflJR+kro7WnaHzNoVr0vWdcWp5Twaq8kyo/X8+ani2gBoYqqfPe7qB09TEp09Wy
zTrcdtfdtUik7CcG54MCRmcuOwzwKJAobPOMuh6hPkhV8IIp17zU1gyJCm9o5BA91ktEflxq52h7
M4V4bPSB2QPDAacbz+LsriHtdQLBJr9QCNelt4OwA125MZyhoyKHe52dB8ZyrKqUqZrbTqSbGtfs
0+zVPw3Psjh283R7Bzf//oZR/UnSRMdLkl80UIC8Xv+wNJ7MWCAaSAzcC++RhfAcWBRE+Fp4AwOx
oRqPO056/JUCJehKAiY3zGXtj1lCey2ltuiNz5JytiMYb2wN0BiNDwv43zPqpTxaQWvZffiZip00
1Ut9kMyfXOtoioHKJ0OCv/Y3Y89g7JZoa+u+3uDsm+JMT2JWJ3qr3N7+GvEXStqU6QOHyC9uzzxC
A2yUK1tdTflnGke9zQ4Pk4aYl2kl4IOE2ZOrxdBalVbL99Dwe0DkOr0tmw3wljJ7cOzrEZZRsRWT
2iKV73CSz37ViPWG10IiAYcRBu6H6fPkZrw2D02+GwXIf+rQoE3nSSgovVQVtx9WOc5MpDJEsFq/
vqIrP9gVe9fqeqFCPy28JGW2wq1aeztEX797aMxlZq5n1v+baiUNbFQzmsW3n40/je/APQqODcEH
TJQHlS2qguCCNUW4VPmZEn7flPOVOXPQM8S6Ch+WFbdV6FW8dxGdqSBdIBb/Kqa9c3a5R88UdUHK
1XNjYOovv3URMR88PC+NDWO4EAMjOyyrWyU1uADIWqUa+6C7JQG1uwwY02meSTAaEz7/1eXCjJvf
tScrzJNhyP9eL5IGBcbRw19nRVlvykf5K7zCLcer1wom8U5VnIDjtc9gZazuYExYODHjW/zvM4eK
RItkKH/A/RslS9IfUu+GCFuaZYzqVJTXu/lu1l+vbLjL8+zgM1qzNwi3NAVmiioxeIVvGEXtgwYV
67lvvI06PBjdtAQyGv2aISJAxVuXl4ieNs9G5OiexXVDpYvUbcUiB7bUO64EAiHynp5SWH/VkZ5Q
gt6C+6p/mbV0xta0xdKo0RY8Ln8r26DCLGaT3pbJDpXFNscx9rXR70uMWq1iR3wi7ev3UCr4CFiC
z3Dhp71aK2R79eUsvVIVLfRnatdPM2mdmJoEfvP9KaB+aqhg0ItFwZR35bvMMUdZJNVT9Dtzbxgk
QJDMWScudLOYMeGRCNRek2wS6qHGSLiC8tE/MsOUyYDS+0KF1H4zMAvl+Cjux7KIUP+xm9S4bz/T
FZ2yf6M3tFh+dQjD9Aj/a4k5MZfrJiGXJGpIbYC4es6MjuajKVOGOOH2JZLT++yLBROoHpwYwEWT
vpWxjUDhUfNI8cwpuHgGVV2kiq1e7Mig591a38OWWqDSAPdZ6tgWlbkrxNQ8Sm3LZSMoQ54EEK5M
CtaTN4ABfjxHl89l7NZGywTdmC5beXhvMeSpl3j7lJM0vgj7Q2e0i2aV3JwA2ZOKnmBSPsaaOEV4
wUYLZpVo/PED+B6zI5a+sc8Lhtk76WQUs71p3/iE2FvptEu15za8+LwfbusHTRi54E5k8CaHjugD
1vte0Ix1zyYYAP3pISgbBiUrXDP7MRPy9byGFLnj6w1U98WYRmu3ilRMPxGEL6NFhGTnuajGu3pW
KrCYN4drtTX+ekK1MOkk7I+BKcChtdKF/GOXvKlU3XFBYn5FtNFh6H/LY+T4lw+q+4sH2jgZGpKG
NoAT1I72ngejoTKbNNRj1e3Fx3TlaEp+rR7mJ8ycC28zM+Ot5BDOr1emQZhvWCwP5NPvdY457JD0
aLpEkhxcPiLTxGhYBd9gdkiAAtiTTMq9nw27QsZ1+1cq+/dVBbwJwGlCw/+q6N81Tm6v6SEtBcPJ
zmnyL9vYdoHWNKbwhPqwtUTCZBhSjEsbOdD9RVeXIrvSVQeOz6Xgv9NkpuL/4oTvolpEOHYhCZCH
8zzbdddXaEmZ+rM3ch46z4iZ95G6tI1tMXac768ed3rGG8Ay1bN4c5JhlFR96dCN8Vbr5dR2yrrr
7FZwRP9LW6jQfmAmuJU9TApL4AgrfCxnl91hFG4MjmEOTsrx/BltV4y1y2qOSh+ALSKhArOAE3GZ
KeVPc0hZ6m3JnUpi7sFs+K2+eRLNxpzVFvEIL2F1GcTceDvCWAnpIlZsog7QTajARQpQd4Z/ZJ7o
N5uWrCYFwTxo97Zj8ltQp+7MPUgujOcDoP2sr2hq6ys3ydLET2Ror3rm4aQ6+8dkyi5LLXrIOQ9d
kSeQ1iwKd+xy9vyKjaUBgGpwbYAsy8TcEUSfMd8n5YL11f0QC2OpTukGV/1BFE0BX6Sj5HR5aLHr
K0CmMVFIQhqWvIFk1TwqqE4TXzD8IfHOuuXMDscme4yTsO9wv6lDU6Wa7xSaOoknOBWf157q/iRI
7qkWZGSqIKOFRsZKlLDktqnYfLBD3QvonhMomlT7JV/NFupS8dom05Lw8sHfaq83ijM4CEuMZbXr
F9tKOuHo/jyC7qbpW3/q6Li0GGO8iK55lCfNQbT33DQlyUCyxYgZYnGpa7yX3zc7GWlvvnG//IRR
chRBIZRfqWmlNltdQskvBIxfew0pixnUozSXK5w9KD90bC9fpB+OCQl9xFwNcNthBKsxJG1galqm
tPAQf3UQ1ZQj4ruHRHDVNP6WolhanEett/ocTNu6jf7FBxwpiLtPzfwsEh39vU7IVW+hHrpFRXPB
WNsGk1IOaYa42K1lZDCZgVIEjTLpQQhBYwcUtIYVkZXOoKKi9LjtMQO1ZgaRxrLm8H/tFYqzwgGR
nUWhz8xhP4b6HQ8mawELc0/g5q+NJ8gl1n9FrkrQFMYz+NfP8Sx0q+1aGAcurN7UmHFbGFh2SqFW
MshVLdsmAn7KDvoAp7jsogRho/NXZd4Ji+dawXEucbzW7AB2O4b0VBRVjjv0YT+6YW+knOkGFVYC
Wh4PEHRfRcH9D/XGZ+g6Hf0bH7Eu7giSy/aLDcOGe/GF5x7d3VKlnd42l7LpR4xcXborFWovmdzA
Dsrg/B210XcyCxkLOzLy+TAitw807dqzgsEiEOPAVpQ5lVlYt3HgnqcECXpcZ6DvcFWl/72GHCAv
rgk+GfX/KpCI7pCC+MpgVa0QpBwPQKgvz4wmZMJVX5FTK6qQD+KUwdiA1gFmnh+gNHpIL6IKEmf7
C1j1UHQSJOcL/UAihAwB1ar30eiWV0+ZRL/Ox1rFEc7Tawai0rCQY4LdbjdUuncWmf578HptpdNf
PChAAAspTvnHb1v1O/V9dzYWP4qvR3zXAwli73hfMjjdfJqncf4h+Iyh4865aaTB22pXtnif7th0
YudZP5ELgsjH9M7lTzfIIwwpjnACzFC0rtxCy0g5IcttdD4fOBjXYGCPgHJKMZQ1w94yCD9bEi6b
HnxpvwMal3SRw2iVp0CkSITiQ6Ky3qULsTev1Fd8K9t5nJ/85DO5q7qkCoAXtSPVUWLyoovQRZpQ
j2Ty9ByXo9Eptg9HYHAA+4wCZRM91THaIuWk4z3PG1xQtbUXu3hPY8WPwl6HIWZV0IiIgYEUByjJ
9KckLb81Z/cFIygMFXh533OHA1dXX5Q+YH6fqsli/WMQN9VISVHrnjy2eNC3cZ4NU1GgmIClcrDT
a/Bvg5IHzgmOG/JqINE45DM9qgzvconjJ+VWGikf84C0u5TGYvI5WS3LqIH1ulyGllkk1J6piyld
gaUX3eVfUSOAXUKBcvLlEC27pFNK83RuAN1WWMEz24qOqEtGj9gaxJUOS7ymg/csKXCCDArIGCrA
jBxDIGPbhcbjdWBNOisRG14+k7qboEdU6taKaV0zez0B+P/3LOvG9KPU1zNH2vKWhaXxH8Wcly+o
2306vtRfNRqo/lkVstvrunlsuNEwkhkgwBqDI/vrx9rlcKUvbNofImrPCPukORgrLoq6EZHjjqS3
2wuKE8GchnIVGs59Ixk5x4gMuZ5DMA7xLnWPLzGWYQ+nMtbadj8BOq+ftRKZxyrgocQACKohRPLb
Sq3If8+OTrOju2Kmk2FOoNbPN2EF0VsM+Tt+kuMCopQbvYTNg0gHzOkqaagzBe1jL2gG50g1Y3p7
n6AIZH5p6vuUcKdp90e25I5Ks0eyGiEBEYE/E/pmBmtRk6CA+IENAQTnZaAwkYpRypTv4I+7XDGc
dhTcVbRHFHbympA8oCAo1umU9Z5FAa5d/hbMIq/L6Fck5agRVsU1H+PuQMibyqXqMneb3NkTfmP5
EySBpVKLWWvhN5SVzGprx8DTB4KZAOsFTZ9WEa+NboUzf6wU5ua3UU0EE6TlWwFRjnFf5R4BB6c9
cJ0G3XbC6I7WmUK81RZXxVs3wTmeQx3bJHKayDiEr/nvFdRu4EY56h+kxW1tWfEiry3jd2k3VGh4
FW1Grrt0Tzm0AKLc1ZvKngvIebFMDDh3oj5UcXlc2xUz1VeabernQ07/tAC7YsPcG3t/KjgQYxBN
CaHZWm4WeAFf4uK1RTICZYcsZGUUfSpvJ48bINoNP5TDuhXBWvBzQO2jXJiK32S4g6tfgnZUUsKI
zmxVBBt2pdCHVyUsqtgiYJnZ9RBo2uRLTWHYFyoQOzgWV9pXzETRBOLdCJWyKlGVFGiZun3T0WDP
F/+EOlswQ87hvo2Wx6FaNF0z9XgfLz9ED00AmIU52jJ0KfsMOrCtFlIaQrXmucpQv4+xaKUUlY8m
S9c/VY5YCnQApK86AoYr/gBOjj/tAH8zfDBzepA6dcvxpN/a70uTUk/RPrBf0PeWfZS2I5B928im
N10W01Wc4vIrsx16ePLuvS9+aLopHYuJEVxVRRO6J9KhYoB3oL3KJbMAQQO9sOdRriURG/MmgZqF
7wfpJ9CGE+65kKeKuAJsb6FbFkqVEn1II76V3yxJ89YuviLpUK14HX/Q1wscwPur9lVbCOVv/3Kn
YF8S0NlriQKEfylBSj4AgOROXFsEmuuacuvSRunp35x9rnC1s0DmMCnpzo1MwoqA9IAfinzJFZba
spSa0UZoGl8Q9nnUWzJm4E2M1ffubKDU3x0YdCpH3olulBH7P+kUJaQsOsan1mrLg0ll2FnOImyu
oQQFVbt6MEiXequXn9WVg0YpBV19diPlsR6xaIegEelp+ARN7UUXozGwnvISPowCb06uDADrYrXy
eH44NjLEh+bv3s+p36InVLYWuXRVnuot5H/9n928Y18611HrZFX/fvdh2IHQ99k3/W/uVEyBvS4o
QAOLUNb4kzkeTke4eql5hC8VbJjtEjaxOuC+xz0u8jgutejpA71Rl5FgUoikaOoGJJ1FO5X19uID
Xz3gm4FSjEgl7GicvJFnuA1uLJDgRA/AOwvppyAQfohOzRbr+qJc7P7GD1RlPM3Fo3NUDfZj3P2B
3xFHcy6mg5NLNhBSk01xRZzlTR/MfRRfztylD4iyCLvU4YOSxGRDhPWyA6euNU0iJg4h0dZiI8l5
Ogc/msD7ug/3Kl023BhYIBVb56B+eKqdRReXRmVMkR338Ps/FaFaQg6SI+a0mx0Hp81/wu1HXqVu
qk/bH7BEMxspqdIQSQqCLQJsXTgtW/9XqXVxIQgS+nEqr2XWAvy7HqjPiyfDERDTx0OFCUibc/NK
LdhkPBRbuvKbqJAPFjfxHofKNSUKm2m7WTkP8fGpjDk7N3oQCYJiJ540tFyhMG6i7YUN5sf1yScf
peiUsf7vG743M8vn0Kokd8LcEHd2gKX4dv1UKAOYoN6K1XIO7rYt9K1MsvF3Dsa+zxt408PzlsFw
sB0iDoW242p6pBZ2WRgi2O39VMSnEHjmg2qorT8qvKSjgPdTAV5rmN0FaigpCFEQc7xc+aBPHqO6
Jy5JP/PXya3W7BqGTGWyK8bflEc18SIK1wUu4aWAH0Nx+3cN9RYGZ4plh7p2CdxE29MJ7DKgN4bw
0Lsn+7ubf7Y2d9ZDbkqIo8NLoOAfAFSnuec0ZdaeEWpm95EEMhI+RQbwv+Rm+cLx7Z/MfsKC6m8d
03iz4tPuATghhnsxaj84tqUO4/X9zTKiauQ0YKrIAX8Ti07ZF/M4/EtyL6SFmenWt4pQlKjT4Ack
lS8YlwSjuKl698ReJELcATJl0jYN69AHuyq32wrScB/L6yMSRX6bjxaafcehDsQ2K0fXfO8cU9LI
ebljJNLUjxIG6X0uCcm5s4pgBKfD1OnBLZnWmdOo+eNtUYd1TdBGBYZT0OimT6DhOiKbm3TivU8Z
zCDoXWf8MZOSCdVk6+cR7ZRvofvDrYGnWJe1/BI6tea1fU8vjM7ir+j56eGi76TTtF1k12ueqr4p
B32HvUgTOEnsPQ5tNV/2VMDf9fkKn36qY/uc6auc9oQAMNGeagd64S+1QDgcRul0GxvS7bIAEyCT
nKTLEvfFjlJ2y3XiilcmRWZRa8OD3H+UOMqeO/p1PgTOfEXm+NiOirVJ1HVoBAviF87YVwJkR8j0
dkQhNg7CLsJNQKd34W7XrxufiAjq63PD1AX+eq/LugbPfLYYcr0hChrA2bGqQ1oZnOXDFaogKFjP
GR4JXzbMUaIo+B7Q1YJ2eg7IgCS/jSwN0IqswyAoYhV0Vr3yHjmVd6XkbP+2ei/FkzU0OOt+oNLs
JtEptAWPBsTHPMF/IU/jbqMzG9Zkv53NfMQxv96TmLMn/yYPly7FOnXFxDCGLnBYgIWhL+Wrk3Oo
hHrsRYpiI1fYqD5areE5fg/CXeKOe4BLFDQcfgVX8WTgHTrxr4PQmLltJRZAsmm+Ps3CZ2h6PYyo
TBJnIVSt16Ogc4FAG74GIrBztGLJvsoIBBEniY3Xtg/O3WckqQHoUxCRYiiZHa6GHI2+8sS/fFG+
NLqCS/K+yJbw1tExDitkTm9cvIeW6TTZvnikRczOfk6OLCtdoAY5pxToaSnpbexyPwVQa3sNM3ga
kjvM6JFgiJeEyC+6gRx04Ge18DU6Z5NIsSC0qqQaXaQGtZV2QONb8AYCSsYSO/y+3/80ami5eSVO
E0K3Nl54c8s3g6fhObbY6NMPLEV7grQSAas5X7TYupSmLZW6SAK9LeohVA9xEdaKNIVWwK0iyDG8
Xl82EgRMDlU021rf0SAjNM6ENLOxkT36Q2mqc+BkBqHCMufsViEBSx9Uehzwcv2CpZUTv0pARmbH
Tyt6Xeaj+/oOrQA0T3Dsrpe/kJVQcrT/cyfrezGAGo3FvXnVmxppVmyXNBDAra0XSrLm/rR4IQyp
mOfhYas6eocmCxAkv3C6vWFRSqN9q0bdAN/saZWnBRDT6JulYMePYF8LGg8FfoojVujVgcUf3lVd
Zxd3iaJrkh4gYh+slIMZyDYmcDdmxese7ROuI/Kos9lK+xvLMGeTAQQz8VsMDx3Przz9y1iUmxUQ
MY6u4nIJbRbsEF/mHu0QuxTxovr3dDIYZQgIUeUVsILeGDUmo39cORrd1nnUapNNKwoBaEVDTTli
ADYaW0K9DxAELcmfvxbY1pYY3iMromgfDrYGniCXaf0JkxOtzqPsA0Ko9BwSSpAYO1JrWvNEfbIk
+e/bNl84sTAKlEfqAeSUks1/BcfyyxECX2rkdHZDfQyI2LalbDKfq2nY7wRMOP00jI4PrnVIRY0q
Vpj3ZSj/T9CiQfPQPWLHUTLxxHOh0gvjDSFYpf4D0syNjx5TgcS+w/wpsdoXgyQeFE/YQpoqDkN5
XnUAv7Jtcc0r5Ml3tQT9+oRiLXB9eZB8aHKvyFJPybCIyGGG+RRrJHdsAVUKgKew1htfQcDDd/Jy
wegVGakKq1WkSYlfb2C20r+0JZMPtimp5S8vguD/DjHGnz/wffOUImoEk2XMvxbssM3lJ6bkr5S1
2CnaFSAKR7+DPhizM1qrJh3zMtqtZ5cqqC8b9C0alIvOu729KmtyLn3gwKHe/H7Wn+DVn7XCYgyo
uo09cvlaZq/HgiH+wG+MG3waVFQmGcjOVOpTHjyNcjNEI9E124SXzx5umtYQBklKiQaWGhSf/7QI
g7xaZy4898s1CcvAsAeK2XJaoAiNDI8ehIxYvlRe1G4p8UZBQCDPMuwJIQiZmLvB2DX7A6TuU1T0
a+SlAvAWP+IPgd7lXH2moJbZf9xo/avYCiGA44+xbEYd42nfEPPbWbShpa0A49iALbdjC9J+kq0+
frTtsIsK2Uo35WyPFoDciSC5y78K/e3fDBCGX8UCzMcsG8r4ow1YStTPMcjCx2TPAj1mFni0jLbI
+23mgssnOViv1YscKn4pKsPULROx/Tw+NiWGdKAz6JPIClCE5EnyxEh2RFW+Df2SIBkN3E0M+Rsz
IsEnt9A6VdcaAxS8040pMtzNNO2IHEQjNePLlw32VJhLimxFFRwQYb1sXMBufuqGdO9vSCKdYKLk
8YArK0arMMUrY62ABibhRhXprDWDL2jfSbMFO8UIK3SL8jX1jXW42rVtKEf2hHioZCHk+IGwfoyn
zEwzo3Fa3q7q86Q2bOpfV8FvKVeMs7nqDvp6oJDESqQmVb4xw0ye69pjg7EmVuKMOmUnpdc9Kxi7
e9Nspnmyx1d83RmsAL1RVJFMj+Ahz95PWyz9lQZcHRye7cbDKJZ4DTl1Ki1l/IqYBSep8gcDN0ck
4qAyJg6LEOHCrhNvLe0cl+LOsZluYTq2E9dRfCtr6s10I0P54d9W1V/bV+xEqFO4Rh5zyrGxOncB
dUAHwKGrZ9U5dx+ES28OYui8Le1mhuZVTua1PmAKPmMR753ND83u1fXGgJ8st02ELdwqvohGAF5x
8t5yq6Ju2S9aUg+FN/3n1P+DTCo0XUeUBvP7rdCsG2lD12bXKkD6CCDTmsizkXMspm7n+js5slxU
/bz+TilP+Vx3DMc8Qku8pNnuUt+avh/9O2d7zFeGa53f9M/0kdWXl7eXm9ZZ1ARlg58iO37WeebU
7MsUcbAKNZFmkkYrTnazEP2tgjFBbD1IAdxc1asQ9vbsHofHR89mb/2KdfUTPrHMIciONGAIRk/N
81Jv0yQP5/6mQgFlAfBwN2+0Iq4UtmfEVg0UvhCTFbBxeCmKBQ5TpIUbr1COdlE5jR8U82PXgX0c
3V7eowrE3ohaPP2hQcXrYTtt+mjd3syfNl052V5ICC9pQzvKPlmytRYg9c8GsusxwRSKXCAqy6am
LowfCyQ6vUoJxPtbYx5eaCGTRbWsdOutzTEtB2JO8+lvsshhTXTIxULAtgE/127wrEauDOIPkYsp
yD05SiZgZWCp04+K+NCkYHJu+FrsQ1AORdEAmaNhNQ73mvyxdRwXbmVqHP4CN/k8L+b45MQ9N0Ec
NSG2Gc1EhrdTWe2lwatTUpnmCD2imiQ/ugFqw/et8JRcgaRvpIZo0M0M0QpDut+uKMRouWjTl3Uu
93db+kliBQxVKZflwMEKje2EREJFyQSZOwTheP7g006WTgGKi7FuiVEHfUecJLy+JiqWWpeQzWeJ
vrJuxppsjSSMOhsQcV0v+4Vn/VSVR/+o2GuKr/2VW8uHdNMpQiutPaBfjiBEdeDpzxqaz7sudCbd
1faGKI0GePsPQ4FNwh/Ktg2Q9PVtSAYyEFfJnfe4vL0EdfrWznmSIVi+8WoC5KNMRsihjA/IpY8H
Xma+34GM8BMZpbdicuhuHeeszjq741/zYBbTIzBgGkyg51LhAPjZnbelSlHAvC8dgbP9VQtvZQDc
nSJbO/oXi66N+5Z/d9FmFn8azJOc8qZ/TWnSr+R11MBGFAQxLHiC1BvIsmjL0E/InIz15gh7OSzI
WB+iE0+3LePE+rC59TTdILKpjyUTYBbbVraL85gpYeUBYgPUzinS0cu37+0G5gTkjB8wdUGEfx5o
V2z+w8nRrHHxeQXcGN8e62d9O7v2JPf+QA6pQg9FhNAkjOhj+FsnyWOKOQ3rli9GFs+uzVzt40Bv
7gIQDg9Qbtt3a6HzjzP16ItgUpbFuo7imxu5RViFZAi+esQ7fqio0YuWRhR08LMAa62MFscAlHrx
KrBghTcSCvPJ/43Fbemvyd/liEsxfioo0nfEtYFVmSmeEUAWy0Teesm9zD11uPwftREPF8c5Ozzn
1PGbFywrHZtHB4dcA9tQh2/NHY9y0iPh5kuYLK2gib+kNX74tbJP2mZmEMAvqfztunA/IHerWRC8
kK+uL6lanfaS4gJa1MUdaV0TkOyABQ9zGnqWn0lXbaqZm3B4yRwmbOqP2xloLgq2WD5HUUprwG4K
tGiO2rg8doZmnW+GksJFBLvDp+xdDELqSydN4+YNd7mVx/zEu81jcmLRXl0CvG9QQR3tGHTDueUM
bgng2vNchnB4oeEWn1OqSw9BTkOQ0RH+Xri19IiLLyf6heLWW5uszvqJD2Z7ZmTz1lV2pJSdznMe
wVbr7lASkj23auqPIWd3e0sQMse8vSOWsb7rhsNdam5f0YgpZpw1fR7kbIF7dsYUFt1EjT7mPJhn
bxxKGPRCgI0+ctI2a7ddPw+yj7xZRpHpW7rXw5hbpzbi34XudGuamxVn2SMlBKq53UPUk+8M23h8
zWrgphZTacHbqHmrhYRH9LWaxQwkigTCazCl9jP/l1ldX+a6h5ggdgZb3p+hm0jcBDEptMesJji9
VEPkRWf1SHU7P7QX6WSz67qsiduc3EOsk0kC77teiLczYWJqqx9OI9Gkrjxm1ZdiGDZECSpZqgog
kimjxJ5KPc+lc5JUlpHgIqsfN4Q2+xVobc5e7HNegALb4ND5OfwlZtrc/i2vuHvoprO3uKTW5DPI
EAdXlYEZb2xqc4f/Cwfe5vL8c5UNB/HyzYd/Ik0h/oXzjhGsJQWSBrNjrobhUYPA8HqEBUNEnO48
jEOxUycy1SusFUIb9MCmoUvIyop/h0MLK8kklPQklLl5D5NDMGRiyLKTAeCHH+Oef9p3G9nPLWas
Q/QRCaPYrVH6dcl6HW2vUTodt2RosY/QgduyuTftUpHr61ev6murhdPkgAtivnki0yCRrgO9q1tS
s1+1SIR1JD17AopOXe4dKXArkQe5ncUiH1iI7TxFgHQhlEAwbjNRX/ftOpNl3CWjPfQytMg7RCew
Cfr03BXB4b9FTSX5GaS2ICTClcolAJb1EoGQlkZFoTJEgq0iZTWDa06gghxWSp3gbf7U3InBH6hG
87zgSRYHYBB8od1JFk9yyXSdCPblQCeTwHo/p29gaIFLj/TDQAYE/bhqL+nCNls3MpBWHvBBYW/7
xuN1Dh0yfUtZOWfy7OTDXb9JhrpaUvCV+OBdl1Ltj5Ojn9ITCJN7B0i3/xXnAVJoxncTYTWLCF/A
GcBf8Mn4vd4EY237qHSZC/VVql4kfxn1oQiTiB4IE8tE+yLbvSYezB4lIS8Gk6gdO+R1xKf4kwey
0qwp/Mawxc1+zT8Nx66TeBR02ys341kdrrOcSKgAS9iNBBp+ow7eXN3Pg2xwxHXjuA7+wQuEGOvl
7I5OblmrTb2LKdp5ijdKUCToJb0G0FeMObnHqBktZBFEnBKHWlF4Ri0HTcia04JeC5s49IdHYDyl
f3AhCVyhzXC7Ppy9e0n8wKMLG1M+9Pp78rVo+2YucBABk4NO0A5A8cw7Tzqq6vAvSsYb9GCgiNT4
a8mm4Yz5EWzvth1NokbTk5TVBTMqKw1TOgwws2pVcZ/Hr4ub2X7WGmywdPu+dNF50tzZKNXyI6I8
0l4mWTMx14WgCHlkRj9MrpJ9WUkNsiDmPGRWqRFWBGQYTvpMt0k/aXBvnaz6hRBNdMGWj4mLI5bW
gDUDVlCV/1ogWrvvBMYhKc/QcwnbaBwbWA85FX83t4goOf6TMGmmHPSdNgZ609wW4tDgv02G0kd8
SoD1prYNBXbIkPt8oqC70h389KTm7DucaCxyj7/E4ApWEzsh58IsIzUTWNhxkzoA5Qfu6xaehAUA
/vUSsF2zmjvt9dcwz6YuQzVAc3aXq4dW6PhLA60AhrnafNvKXytb5r0E+ecZ+c2L0FJq3g4kR/5S
VXvoiw/cPB8ErOR4J/+ye+ZA821kMSYo8swfJfaW4dYSp37rjdDDqk3/1V7EKGwxxGH6o321a0Hu
WpS44coy2tXZVWxsJDP5ZP+Z1WzulbNAbxgy9fM2LQvc9unUiGwucENf/dH7HBDStw2eRnI4LTL3
fzipKJFF8Lj3gcznh3xNLI96Ppt9gXvGuAHf4sHdAiak4Twk0aoaCYap6eHOKeQ0E8SbMYPtMq2S
bivBL84itN9xoLTyVGYw52DNlnVxGzPTOfiDa7fSY4AiE5hzW9DxT5G1rTAft0BxEspVjh0iig1p
NNcurMT9eism9C0QkWzCUPXmYxWAhbIehjHdxYN9HYjz65KD0ZXTzLqjD0WrH06GIFPo7YC/fpUc
kU5Jxt/h9RVE9EJy3CCSHoiPwo1savR511l5dWeZcI+iW+hfsGRvD4OoGCECJtmuFKVQUqM0kHx1
3Xzd0fD6gNJSywqeg78oq7ds8qHKP+d7mnxRbgI+niEZ+zmG1nGd3/7q/uLRhCPczUGpvcc90smc
6PhfdOXURJSoPWR9u23017AMkg4+iOsznbx42DYmyID8NBkgDvf2djT4zr/kTQqwOPwx19rzt009
/2zip9NYbHhShwybVt6LHbBZWtlesfBl/rtIdCX1mZComq2fLd8qJX/e17hdqX6txiFjSYn/LurE
0Rt+LZxdrL8UtMl79BmQxxCaQcLWtHWF7z7bdgh5fI9MgfVEe/B/gP6VUClksj3hyjOrErXihsmR
qDYqpmz+8hTurG7kdEU/4yhnkvddUsBtKEx45DwqOTWDknHeo7h6Axn6GNwDVJvplntvyup2+eV6
QZnIrQCilauxjoS58SJsfqYWkHv9drWsrybR5ylGI35myv3WzbsFKHboCEvj/wNcEZo1w24ws0Re
s/pgPhStuCFwAiLYJ1uqyY5idCxZBgmgfRFBG60DjdzkmX22yZHwshUND1h9ro01WKrTtMua0g7H
hwhrZptE/TkM++vmi54CGS0Fg5ZDN3CVBszWEq0DPYybDiGrjl9JUUGnblztnYcaMSg6CYJgRS74
RK9zMwseoKioej3pOkijPMIOKiuvVe+KgdP/t9XZzevrqMunBtFK1iue1yplyI9ORC9FmOKH8hnl
95V3a2LlhXF17fP/qzfctCBcSsA3Dv8mWz7QqcTuild/UJuptSw3O671L47cRrrm2d07F3RYXtfh
W7PJ3ibF7xc0Z8PPCIcutOrvp8oas7V8Ldb1jObRP3fIMjr4XcAY/HGsJ3K3K9MOuanuRq7GjWOf
N5klNhl4f7yAo0hj6DSEuPJZeDtNBrZkKPoG4fvsXuWKw7+ecrTjrUsORBcXXj+yuxl0i+LFlgmt
ki0ocB35AFxESOCRl3X5SYT4UqlLRQD89VVH/wr+pq73O2hVxVn250R3KfbxpQBm8SZ2IlFWeJ3L
G/ufiACWU2Hl1POgdpQG4Vf0ehSKc5zi9J/KMEsRQRGAyc4mBfZcXAU9bQiDl8XOgVFX3LBOOXzo
e9ynzPuw3J8ODylI+LqEPhUp45voLLLEtOWccMLX2awLViEyywp4bXK6hHFJfRwJor7wj5tEjpk7
G5NXaL1UJkntPUCslmrt6riOfh6QUSOnTT+9bGg+Zwf1tM/gB+UoKjd2s0vNmW3UqSuzGQlhvdIA
lV5vozJ67yRJtkgFin//uQfW2k6e801R+r7fTf9YlGkP29l0Tj9xahqFqluJjvLN1lqdAWR3Wls0
my804mrFybqTiBwlL5QOU0cLri2MVveLJM1DQc1g4aiPdpG1yKaf+cf7LTonMrQeQd7MHIPIeD6z
InzIeVb991eqQjMdh+qyL36/Sgp8VINeuni4O45WpAUb9QWUkT+W2yc2a0p9jpVaAFWAQq4X921x
teJQLmDZLLF70JwMWRVkqcseNSXjFFtl6wrvkms3HKGX5izsOJnubJdx2ty2rSJW8WnmLiYKCraV
koP8pEPcSqxsmokjfki4g5ScC9yMcGU4kAWtUMbFJo7Oit0i/QY2GypjquA/WJbBnLPFHMj9Sl7J
fWTu200mYIhQcSqGIJUFnIJlfG5C8mZtz8+z2Ug+uVHxHwaHr+B5YIe9ycmecFcXmcu6bNWTfCat
Kf6AYgaEMgCqxGdTf+/9TYJepx73nb+fRaFeCKkF2/x+xsZTESXYMZ1LArI2E/sGGx+n32rmX0WU
XsC65ePNaWLrOquHIpF8XNUhKjlbiKtX0E1fsY/RMyu8uMbzccYY9Nnybyhl0lv7rraV8lx18VTD
aq0b4jGn+iCRdc6p6VsD+YOy3LMCDZAN/R5rIC+WYedffenyuRpepMesa+XInIDaM8Smpgn1FK6R
+CsNnhykHYdE5IcwoMM2bFm8rW8NtIBMQ1R57p2ixabgE1hwwEDGzNy9xRwVS21TQXKiAeVoiaJ8
ZHMSUL4C6VuTYdIx9kMKWAfQtyMw97jSFVx2iHRBgfldSh5tKeasCoKYEJoQB0wZAi9hWoIaoXsi
BXGh+jinQmMKDX8hFZTVRUTdddEEPQr71AzPnK+VSC4+GhbVzkAWsmjiC9g2A9x0ZQE7Q/IVBnNY
Jksp6QGEysecwGdt8R84efPcb1PHqMHE544dTJq/WSNM33rLkFkqmagNedhxIKsckHjHq4+jhFE5
GllSJxsA/41pDqZKZn3rKnzcIKyZ504P+KWBxj/ZyhVoN8meFMy4weE9GaDPCy8WWPlAbNSGNJ2Y
kbE6tVoflykCddOotjtl3bWp+tts+3Vu8VbCwXS9sfHPH2fSojlxS/HLNJVYttLU+hjoVK05aJAS
9JKzRG/rPGb5M1zk/Tk5pYfum3bOEOjoe5n/utlANSP2M8Ef5HoABDeDxJHYlZDL0dDFY1LkoK0v
JH2rHy8qBsGdi/B6+0wMM8WcEdvef6A4JzNNVMhwSV3C81dfs6QS6wPpmxA2ovbTXSi14QIlCi+2
CvH22+k3XeGCNx7RNsRTaIoa165wyqmtW0MFYlTRRGtKytjLuLtm44uMTIdR6f3pZTO7SclCj96A
V6uujUAEDFSJP33MwgFSAKB/I/bQsFJSGbBZXZeKPCiNiNamuTmV/ezZ/j+srMkmjRNvANeXnM5N
HXxjpc+cpTY/HejbdF4/8rL8hWZ3mpWQmMei9wxdtrHLWkXO8U+n62RhVgFtjc5u7nUbRwxbiV3t
1olLwZGmLUPEEibTCjMOOM/gpv708GsyX6Fl1MyOes7K4syYlB/JbIfR2yWj2g29jdAVbJ4gAn0l
/EFZsEHsaexnUjw4zg276o3RFe0wQKo/6MzoXSgRdiRrVzwkV0CJY4ESdpNZcJ3muj7jA5LuU1c6
L8Yizq+XW66DJCxO02jC1AcEBYEPEFhyENm9rl/iXEC45srKrM31EgNYSGbIyF9eeJxOaUy5YgBw
e+V5EDijPOPcf/BE/6k1MDZenHeb7pfv3fJ/tJDF3DBAJmfjJ8ejCQfrSZcBA/ExOoqWC6PSBjvY
+41MQr97Kvs7lcVetBXo6KzNIeGx5rTFF7Of4BCDBCNGatSkBSKJKWUiHoZC1mlirxp+gNUTrpNM
SB7pc+lQuiOmC6Xy0QN9gLi3+MUrf6s8MZU/aIkZwTY1tFjvLxSunzrSKg5mOIc8bJnum7kVnsX1
VFtz77wt2Jiyf4IskAEJQghx+dc9e4IdRdfZt0B3RBrIO1sBeEcF9isFsHjGfqQSLd8oIlzqkxWc
SMHbwlIZ6cod/1sflS64JMLYU8DYO1sDkAVobsrNWYSoLJ2GGKBS/0DTHb+Aq7a0UTqi2lijYgBW
/WyIPSDvZX34Yccm3q3n5C31aVBjgq+ZZ//jMgVWJ5DfghhOYonSoPNfvBBJ+A33eQiboumv2NVK
TfI7GFq4lpqiEfIwzN7FlSk1fLU6l7iPXMDEQJ+HcX3qjbb1o0eiUiaZZGLmdQAL8Gpi+RqIW5Zn
l6pQkcP2wY0rH4ciBUW4wvOWK89Kmhkm9aKho/uu803vNOJQqCFNqNDYgd0uT66dvH8k00uVQLhs
COol6Z9X1cv48eMG9aBydyQ0eS1EgPyC/m/NVelMbGqCrsT6ufchNwF8v+EFc07ggJJ3SS7U3lID
RT+acKLTZPndu84UO14EjdIwQCDHxuT0CCOxeC4cQaIjQX5wdIzyVkEzSdaPdRF4RYE6K4IQdtaL
pDyJaCokiQ0sNqDykcnOMHYZzZgAzph3TK42dgnWFdBcQLwBX8oTwL7kz/cLdjROr8R0dcSpTxWp
/yk5ZgJvBp6YmtlsA1LPY1TteIj/hqkO9oMdKY3llGxD0Mo9bakpsGXQAFSkZmJCPUhHB+5rrNzZ
jPn6N8kPRxR9VoTcfax0rSch5VabCnl8GndPP0IDtSLbstRGtrnmBxQhn7adiv0gnouF1SMMDk1x
7fUqdL5gMZwVVOChoPfJG2HELGt2Fk47xakFnqSidFJWEftZ4KggmjgFlAqH9xmvxIMvwb/RZnR8
30YGKEoKTjhprSfb5CEYn4YVcSxIt5e0iP4KvNVvHNr0KOYJxQN1/VwqW7Di20nM1pDtA6o9bFNb
lry/6YbT7x72UZbRrt9xCUUuu5E7XAVvP0zS5j+JQNnZgEmPQQ+3qPZ5Y/jvG+idBfjyq0fYoT+D
rpHou7f5FvG5lzN6AaUNlzFnQOUn+VER/2TKrt+Z+74y/k8bUc1dMSUdJte/LmjCtdV3pLVpypUJ
BzDiZoOM4xaHuEP7Xz//xTkBxQZUb/GnrrPUUmgIA/GIP5GB+z7qp65RDmfoC8w+oCD/QNGHKalN
5c4IBQkDiLy0MdVNRa34Ncv9ujTt4QKQWTVhoYFpMYTXaglgDca4CIDh1T7SiEfL4Sz+XX8DhUAd
S6KGf/BF0JAOSCGMgAEd4wgteXKjeFqj7KzBAebRDMhhQgMiVg/+jdc+GRUA7QISTeAXPMblX34J
MEBFbBpxiZRn6epawFTiiudC6rdOzg/adENv9ir/X3Lzi15rASFROedwnYEICpSH7N2CU2VRZlYb
L7Q6CDW9MM1A77pY+YodqM0J27Jrin/iKiC48sUkvnxkE0o4V/xZxpX9ldYKB1egsEaKuK/29Gz2
VAV+LHuUud+gJ7wdfA0mqU7R+aG9XGuqN0QuXgP5UBBCHk4RA5ePNL8HnIqzxQAaNNM2GR13ytdq
42v2im5MsdIXn9Cp06ml2SsO8lQ8x1ImeDxi/sB57TW5MU6HiVUX4StZPYbfD9WsXl0yPs1Fq0OL
q9xWyiiDuYMzH5x5j7zBkq2zu2RQ/28/R8ij19Uj6si8OROXm+sfpLKKWuBTWgiFLvwMqo2BzPH7
BjQeZM1p90voPrRZfJT3cgyb/a9fhSPD6UpnMMdsctiMO/4USjWX0a9DUSm3jGBiyqKWviL+njeH
atEy+NuNpyQf4GWnJVkJTHTpD2mnKr4XLuF3Q+pMDPtxPi9geAY4qRz+M5UIKuG6AEhbzWEd2EmK
JXk0eLR1QR8B/TWM/HJ5VQGs8CxhTdA3kewfrMnQTYmG5daycdlraCKT4vp+IqlL+DgOkk83uMGi
fkpktbBXcpcqkuHxVZu3kFw7I9bf/ZZL63DNaCLNsupdpOv31h+LyqM9+QFr8o+J0opRj16D5WHl
AvXwfbQ+xceDh9WiTVzLvVnB0VJNd6NTBhuDNicQJnTLMpa69qwh9hxPBzzXmO+Tx4XAuDVlTteP
66n9TLVYzFs7yVVfJHaw51g12fdxYT8VDAYsUGKA3KSjtOver/LGqyinY0gYpOpV92bGngdN+6nK
tNtI5AvSIgECvCCt8iKYgsaCo7UVpuE9xI3zPwItP6qBwHIYImF7SxyYfYokms3Ao8ALdEuTYH2f
yMeZjNZFKy/OF3VGKh/UfOKazIHrQtm3t9ZwRZGWkNY9MX3i7HAwaYIQje9/sGKPte1hg4ARsDzx
VOs5X5HoTFL3T9pcPBgzB6nps87kOmT9mhmkhZgLKWZg6hlyxSw18IjpzRsQTmvjXMhK6egerMW5
KPbFdML5al34gUX2z9vFKiEN1edb2iOoLDKUmbENgcoUU5nrKaUoouWRZXmeJXZb2yqXpoUP1l37
Ge3sgjqvt3/ylNVn88CL1XnQTNSpnbBrQJGjHhTnlxD13tP6GJj8hPQl85EmjOeSENyqCHRstnch
NjPzg7KI1UH4ooQk7Lx/ilytnGjEZp37HYYz8C2o4VXEu6ohTZDCQEVP1o/wkvKE1z9YaFehH0DQ
TijL+U3XSVPPA8Ri/LcAwCRjrsIY6TW6bA7HTp2zDcsV0nwthzQdtSj2kY9dS54EjggJsZ/yr8Y6
alj2P+QhRTVWWlAxqthAlyNk1UY9m8r0Ng4kzAn+Cee9yaN9Q5IJL4E7u/oYM35RJDdSwZIuLsgd
co3b5AnPWCgj9nAWuAP3q7l6FtVJwGP1ScSKeFt1G5xbyW/fGRClePDRom8yzatn27xH1fx3fxv6
8O8DZOz4d1tQmpG/pTMa/VTfqNmBYwhWhvCQkiKkyFFOvgQ7mKF+MA6Ta5560gH9sTB7Ym369X31
SMC4rJ9so5t4BXIFZPckohQGfFsrqJRjuhqMAwlioTpyrWVmfCXebNJneBUHTy/i0N1E4Sc8wqVK
/Y3+YjK/rMEA0mINoouEoJWCajHH1MIKvDuUEzRQum9ziTVyIEgxQztSD3N51lObwjxyPIg4u/Sl
tFbOt1QfurUpmKG1T+0Ue3ewd/mVDCuFQ6050wh4F8g5LppQhs6yTyaxrPwFxRqIDXnFerr2pa0g
vJbr4f/B1QqLjUCwx8T6vwqPcgedo/7VuFza7RxtBQ7ERGhkWz7jVWAxGmhZGoekcnW+vooM2zvb
YeN3xlHk9cLLzVjAWYo+/mVxdqoMeL0zZHrIlT+ZF7ZBwRyrHAdZeYJUrnEeITkl912w99T6vju3
Ak1sa9GeAqKBLpLXHxsfSKhllbYHzqPHVMdu0JjDL7ExfMdNi6H/7r4T7mtxJJeNkA1x/zQ2BJ0+
2kcP4uRIwHt756cw0eAcRAiy4bai9p/hyBu/iNas+6cnfHYHKfNqTOvVgyQPgMqkCtd3wvvfdeod
GVz6Keqn0+4RYql3BfhguJX3CaLYr7EswbDzbauhtop+1xaIaUvrO9jJcWZjDc9PuMIzB572kdZ4
+jLLypECLgfbqrQYR0NhuWRqxz6kdFeTbbGf0O1ckQFA6/KVxmQJw05iVMQovgPho5pJ9gk1BS1t
RBYnSggQozptGiF59abwJKIFvdJKIwTIQ09F4l3SbAtZ3gJc9QkfR+nlgY12bUDoZe/f+6dNQdqN
cJMdfl0JO6nw9KynLDubTnXwHpYAEn/TyYpyH5Ksk3B0rQ6yO0CPxnz7zBiBovEF9Gazqhe1+K8k
8PXCeJ/tJ20hr1AsVY9yO7EKu66IQx/9f+el8uQwJhmYs3wnLlKLh8oP1wkStc7aIpSj5n18eFwn
NKAgSRAPJjoe1udHEO8pv0VKQQpJHNDa5ftbEwzx6jU5M6dOFeBj9HI/DU+N7K5HAo7DekJ2A3m6
30s07BUkmNbgptSOq8zUHouiaFtLGecAcJmAxxaWVXL2dMvxwg6SqsoLD2OfK/BbranRd6eGrzUt
9wpkH7aorZgetGnFhFLIvAkuEPcB2xy29GrTfq6AshjfEv9P72wIrzV6XYPI6ByXzQO7QJ0yij4D
aouiOIdX1zqIk5i3Qkl1wtRnXGc6hGY7rIqSFxUy7uuVrqvZ0z0QnWs0eKSVjKWQK7CO3mCXzSdk
bNCro87yrM5+/bd/NjeR7iHmajWmQOBbxmYE8PZWoAtv5g3ll5Juz1QKTz8k2xLddad2MvmD2XRK
dvZnT6+ZMgbnoxqSNmW6qlb4eAT9ji2FwS6ACiz8BvMVNWTLLsuvv7s7wK0aVKoi3OLKPQ4HcYNS
dirBgR/e6tWoOP1VJdDP++Z92yn5YX5pW8pv9qqXMxPQeRKJFFiPsJ5RgxvtW5rQbLvobD7rxtnm
WVCA55ky8G7FZLFrHqANWmIN3rOYZ93JWfzwCruU7WKyTDi4c2QIQ7KEznn7rzhzhHlrZ8puCIwf
1pwYpR4N82Khp+5Bc+LJmG+yDRcE9u27jJLSlaRWe+GgxjmzDJFFqmSVnn0a6Vhg7TaR7jlyv1Sx
HyZ/inEiBPg622YvtFcGWfxEvjQPK9Vi/pqbZYp0w3Nt1qdt36z+4X9aYpr8vnxX9UJ8FPXTtBCg
BeuCHaI39+fmwBGza4Ynq4tffx9wBw0WiTOBxUMgW5iwQYbA7uvmwtn7kPyPgyk76vW/vGJYRb1c
4yCZt5QU42WG3g8IoUHSo16S4mgByNeQoeVyNvNezvLPu4DUxf53IdNAPtbiwxWbGnpH0msc2CHb
S9sWZU+PD6yV0FpxQ/MT5pXttdcTijLKJQqLpscU6+QnC++UEI0zJJc4WOchN/MBTX3ZyJO2giXi
9Rq5F9KhZBr5VrCcDbdH0ZvJixThssKNvj3joXBczRH8v5oHZEnGmZLRR+a0sbU4u7bieEA0TVRn
FWx5oLQ4io2T0QunbzDkpEbaEohq9Zqj5DEbplNBEiSmw+ky4wIKlBmIZI6TQHwMkv53kFHViu07
2fwdGLpcfJkfIZXFH3bvhdSCBiLYgx0sa67ABmuZF+XVS97+hD4Zjuix+YWrorxZDZutE7LBd4po
beDB6fkPHCWxe0W2kGuxKqVS1xHGQ5YZsMTjX1WLseHOxPxTaBV9QFd+afCX88QnnQ2pwgnb1zOy
saDfa0PC/3spz4iJwuuXDTlg19p2uCSAPmjPHxXu568G7N76qWAU3fWMMn0l/BOaQMlNKrBV7rqv
3R7C6A7I+QAorCyWplWztZ2Xn/ylqgKfiSJ0+J5Y/d3SpwJfSUt6+MMIgQjzZCHgCNGSxmAnYlzX
2bDwf86QRNT8+2NQMJ3C4oPhSN5iNLeLnaXlbUhaN+9e2SC2Fe75PxWAQ2EY18yy7d8xnCk3yk6k
iDrbRl+WP+4Kf4f9gXEPSKyHVwY4vYtHRIco0VNpqfpt8Nz/XCwx/jeluC/7tM2CLe1u/Lu/IDZi
BRFb/He6VpvKErk1XttRGGMb45nQREAUrDKVbZpJUNpqF6R0Mn4Wo4DiMjjLAbvEgQiCgcUDwhKI
HAtULCsrwaVAb5GDdEZ/3kxBq7O3+87tmUYOQzk75Qr/OSEIi0Tt/eIC0RcQp44bU3UUd42OaU8D
wjek6bB5fbKnhSTlo4IIJsc+GWkpE/go0C0TV2LJCof6d3ZNFpMF4MNS/2DCVo5nK/qolwxx9G4m
Sod4Ll7PxKgmeCMYRRE6hzqrqBj0HYeOoe1uJ6Bbv2imfyGWrSTgQiLqJmp8iCN6SkC1KqMKZ7V4
zuiIHOnToHkMQxjI5OgQHFsSTYbdwGgWsf/d5x6E0+Rt5F6eEJQPxSRe3xPizAHrBCP6awttQ54c
K0TCcaHJdo4bfASOUg5hXn3KCvdg0V06i6v24Lx78Kgnx9FJ6j17nBPePkwZgfhYka87PbPgcSOz
mjjundZPqGEBBniQJDhinObMVroi1U6AeckauBx0zWtTz6hGA5HI2rhrUxNev7BNK0YfEFDOz5N1
dxfzaY5pa97oOBW88SbZQCWDlY3e4WqJr+tIKV+VT5frviNzlpTOi90FgNxI7dIvIzWroL6o9LrT
wTa3hzfG3LX4b+ZmW1EUPoYc1qpjkcx4Pn9exqzxDWuFGRzMQLQxMniZgoc5kyArDlE6sSFeXZzr
qTqWGYQAxtI/OlORjwGjv1VFyyJxlNTKDu4G1o18megSXd7pCMnymxm3WHpmpaME5vcCqJf3mRQk
pylp0mHhQdI31ZIdgX/Bt58N/J7CIPmiYsyzQka+jrQf4wPb46kUNzOSny2kjvFgMKcTlKgNzvxd
kVUMrT/7hNPnld13IbqYPNL7HImO7ouvnZEn9K4oKnh2wWhU8C1FNn3Rw7cRDQcS0ofFzdBXvRdh
HHyC/W8NK0BF9GL8r8jt3YtdjwrsTnOfCMg+V8ZJGx6aMmmiEsVWZ8g0dIQhtSg9/LzL+VfUxpvG
yyW6a1X64u6kC4Tq72WaPXRs27d82gBREdEQ0rVUda3VFkewHGt5mgZozJp3ZjEBlhIrDh4rBBB3
xTUfg1AQn/fyX943IiiBzTD4QW3uGCvTPTaXMSXrFzMqSmPe9wU3liQbaY1oir96iCRVW7JiarxY
qFFBL18eBUw76vE0c9F1qeucWvK1yzAXEn8BPVPLsNHB2oqEi3OcUF7ECJKEWV+IA+/r2gzTkdQd
+4lhOnacUd0Z0RSKa0avuk8tjwljxNJmEcC7RlNnp9UBwVyL4bNxw7CpSYmfTAsnH6sOhYmos/+O
i5RcO9Fbaw8Kt8fvmc/0l5cefQ2P6FMUKp11pzIn34mn6QXWfBs3mZj7VyLZlRGlLDJXwlc3A5nl
X+6mejemQFZa0D09yZgB0m3CnKFTmPVJNZSjfbM8nfo/M2Va5EYfNVvAnyU8kCmUmXHOWhVFGDOt
ibuSBoLIC6ACGLkz1r4XfzcBOv6yaAkbeZGxmG18lbaWa78jufrFiJvkstdRMGehw2vulAYo0G6+
9eiyn51ExrfFYEJ9r+BlLnTj1TInIwCOdIOExzSlgGorsRChsVmtIbWtmt17sEpaetqDwk181dpV
bx3qtB6UnvDTXrSYMAYb9gnnNLUbpdT+xon//flz4BzYcJUrZXGlXP34gcg23+qvVLI8eMeQvdVW
ifgERORPSLOMWT2t+9d2kZWPUBAjrB98XP8PP8oabkqcAjWoI8ILbb1Z9NQdUr0GFmQPkbsOYXYm
fnHbyqqSVVP8BSOdlfoAlAL+J0gwTUnEe8XQzBKN6KFk5TS6gjEjApOwoZljw8JwB40BEKzHrBDY
eQ/EOsNGLF/qPfE7SzhOeokKk/JmBLp+onpGzgcklfxroOKIZ3+P2F27PhRnrE8W++lQ5+4DDFsx
VZCiuPxccD0KrMk5SznlXJRCxqMfdEUN83TVgV40VGNM1Y/JhrvQZ79NFlw9tudn9nSXLGpa8Ttx
tdMY6bp3dvWBnw039zUpONxAetJJcJIxuidvQIOjEuuiT3qnzRFcJE6eGTuQoCXFLI/cDY/8FjCK
RdA9Xrsm9u/5Gu/SCXvovV+BPWaPNKSqbZfHpTB0d2ipTLRPFHa5UNkBMyAzcU9jM0pM7ZjPfSAV
ODiGv6P73ILYOVar5pesRFeimC7ju3ky4QJXiLQQr7Uy8zNpN6IfOHMxO2WrkEyyM4n5QHmFr207
8Db01jGo5hqchKwwQcUfdNKM+dF+Ku5UHZoYKYhwB+Hc7qFgraeh4rjrcZT9aAArxkP6CCDtk9Ct
8R7KPPuNvhl48DO8ebs+XgkT0GE+R93d8pS/KSsTZMHBzgIxIVlqldR24lJUpGEh0uv3Pz10xl2e
FJMADOLkVWcXzmgy9AkMp7/TIIbdf+yb7OgtwzoBnEb5SoHrQbzvow1ZMMhghiV9AL7HE4MQ68vA
dzmu016UGg9vz3MQmm2ymrf3DzTvgf4k38KBND2707ViyfrTTX/r1oUpWp8C1EldUu9OaOJ+wXlB
Jdin6d9ziNvRdrWzZ3h/eiNQMRe3aJ3EiA86pS1D9WnZtWrFB64uOx2NDHsHmAZdPf3BTwcQzoHb
pBvFG5YHqeDSJ8FKW5UzDy2hHFEMi13RSPY2/4zk4a/mYt5UO6F0JKSV5Bk8hb6lpWawqo+TCKvq
7Bs6epLb9nhF0fJnAGG7hxvGC6rs2U+cdgN/iyHgMtgbF8AACwupOSkJIQVepwp6MpkQn5+105+u
sML6ws00stnPxRRO6KecdHjGbg9H0jxsc2R2pMr/tHOy9ShEclQpO/obmUdODLJOtiykI/IZw7Mj
m/h5YvvxJwr3Z4RtTip42HBoIGGRerxmX57IEhjWL+QG+nf0K+e3+cNkcI+LOHKroms5ta8i4ccJ
WSDnrPVpe7lyHbmNOUfAmxt/J2cUz00zjoWR17XP0XdsHd+jVHkH42eVlFBfORJJENIGvEfoQUcN
FbNcqM9RmHUo6aB1kHHU0IxiwLrnHo/W0prDFPQb7ORuJpZWZ7j1fFPjZILO026X0XyY2Z4Sq9EW
7aczreZg+SuOoh8lLNKhNvrkEY1Skr25qQw8pa9L1H6vWpfKfhztgVbOaJfCjL6X0K+KnbEOPH4+
51FURZazi5tDVcqWXTMKtU9ZB1Na0MgQq3QgPe6teP2acMbqC+RM3uubYimYUbhtiyu3WKwPXAGq
svGnlhk9mKlxMvdNVLyDq/1nQFK+tsSqyUmr8KZ5u9XUAWilrGaQuTWhKr8Y7q8XWs9vzS0acy6I
wHdBK5tPs7u5I+fdX+q+P+IqA0Ai2lPCs6+09ITxnnt8ELepmmUYrmMEmTYmFMpFXRuF2ZKT3mC7
JdsQW+NIe80FTn9GG5zXyiNzC9akybKk7fvz9tzvLBtYpRpLxDI452TUKU2fHA69GcfkAXS5xUm7
f8iPdoC8y+T24iIL8Y5TwISGx5KbK/zV5zJvkjC6vTmtxW/l/fBy/vNrNGibDNeEJc9j9Z+kBSr3
gVvjZLqX3uHcQ+opQMssXpJwdgurpa3UDUqMquFL1D1T9c9Qjo8sIIP2LLe5jJQRZLuXTCsVd4bv
XNeqi4N8MXEupj6Xx/XEMyXqlAMcNu4mez/4jmQ2E//J8auycujt1wtcFbeamwKEs0yhVtSLItPJ
XHLcEZy9sgc+966EuZlpOfE9Yp5LNGwWk8qRrSz0d9/aeFRM9PeNpFAzKTZSFilDJB0g/ZS9uZ3G
bXAcdAl7O/0pz4ZCVoE6VX25bPyGxd85t5DC1ROvyP50soGPMxPu46QGkBsOmiob/Khel9bcKc5m
fIa8KF4Icq+mMmIu9S9lgxwHjJhuhp7cNmpS2fGRKEPKDoIALCLmVJz3pDtYrYzYUGNTjccXasVY
gRXS9dr+7Sffpdevf9/i9w9K3EUZc0kJCc7aaOj2fuuBfRUAlK0qIeYN7khphQwKjB6y3XSS5+RK
Opxatq5sXt5ul+RvO7r5cFdhoryQCfgvTcXGtvc6dwiXgu4rfGR1DGAmcFHnmQmWbJ/vMBilfEMJ
jN3Ab4vvLIuhrkJG0wm6pavoSDIuCP1/lt8jHTekGuOzFq3YdHPMnYTc1lB7sbwyX06VlEYOtKxg
/FJtUmNOrwBi5xs0xZrLv4QNzbnxK80Vvb5ARafH2t/Y0P+dTIxlgAM9eHJPUttyx1qT//gPhJs0
1felCrImY4IIilBLYKQZ109c4uTlcbLWaXTmaBk99nJA5Tl+08L+Ok7Eakc62GK56QZnW9sCtS1x
Is6M7ECMvMW2xXEjl+/9lTi7hVTCSPxJ8WWU//yrmiYUd1Nwe0bvQFrFfA43Y9hUdiYuzTLuy8ob
5XtaOep4wEYi982c92caUcv1tLUviwCXBvHpHO3Ml3rQH82wTI2ANpgyVxDvorc4MqsLXBBJAzTS
2ngN1oA0WwY3XY89D1U/qw3a+9NVroO5jXO3Hk7sCU8PokLKbN9TTaJHH254OxBKCMQOf97cmYrC
UKvZ3wTw1Dbz8KAsO/vUTKsJfY6emC4nJgSfXqFiQK5vl95B5MRAEeWlO4UFsbpg6Cz+XIA34lhd
j8tcCvZDxI1IIJ3fmqvY2Jn6Wy+cGTtEGIPYXD4RNqjqaV0KpnVhhB4AknIYKFlNk4Ot4Hf+w5PK
rbHP6Zi55MUABWRIOEvbZmDJSpYvgPwQDVAQn0xic9eChQSpU/wHCfDYWqJHE96R/F+DQPKWU/QO
3iPaL6zJokSZ+U0sKUtYOgKq5FFouN0Ay3cawOE1Le5hosbNe8yNqGCwBnhSnWzEYB63DttW2/+f
KxMZ/bSxrvQFVTK8kXc73r6d61cKTjpSWWk00aOZ4Z+B/A9eMaOwU/8GiET2xRwtnzCbSJgESVLo
Apch9Z62Xg0tYrMpxQr7Mvv5OTiKoeMnTfhmMGq0//SuSULum3FALR69TUiTFBUKTvyIi36hAoWx
IjsWlSj7iPrNFsMdwHSjLldUNZ4Gw0juIFOlNEOA/8JUso6cZ5n9vw1ttVc3SS+W0bf2vFOj3oqa
OoY03H84E4sIR3HVWrbX8E/pXCmxAoKUw7tiFahsswgE0sqn0UhdfEj1ovnV2N0GaC+4KtRioq7I
FvVkbG77/IL2Aur7P5iUFCj0AALH8NDGfJOwLt3XamWHkBFHP/a/42vYISq0UZjI9RS3+ha6A+rs
zpvS9z8UXEYzNlmerCXJL0YMb/DzlGQPy71+ECFfcENi8vG/Wt1jUqiBQ18YCCI8+5yVayobqBzV
j4FxvdlvV/GW1j04UGnGsMmpysrNqzxouiTkX8PuwaWQMwZvH2c6JLI5F9qAbsvNeek9/K4kHjwp
IyiLENLBTpXLxXN4mVhqBVCPQnHVoSsyr8+1PKgCCmvBiu2dPI0O5ZbFRUXkjUgt08lWXXNgjvpS
PZ0tBbIiXRJVXnHjrts25+bBBsBYQLGor88kGqZsQohjh7YzxlvUtWGsBHX/eS9YAzo7gJGz57d8
fpKeIjqmPA8H35yacnDsMQxQYfp5ULXm4FOe5+PYLUVgKWZNhT2o15PMjT7UxYnwE6Je99QtRsWh
o5h7lP6RHSQQe715w/Qn543/IlRclyvM/DN3XQyb+qNbzWGxYI7RyiKDCff1aXgGzep4AlbiZ2sj
ONepRdbo/zRq6VgBWkdPCgkAWeLF1PZoS2OLgB9yXgwSVFwCKe1ZxM0Rrl+mzKIqvCp8h48pLNp+
NuLd9svBw44Rt5T70LpPa/uSrdEcURi5FcNCBovaNWQVvrUVusT8lTMP2YEHLYpElDyQ+/eAIChA
ODk0QfkwcIdzfXA2fcItk/cd58FDCiqxaQtQei6C73qIFPRg5GezxdLPiJ8SrmBVXYHquFLXM/ta
RLcgVpkbpKqK3MzGwkMtbN69zig1DriCiVjHe9BBsZvySmzlicP6FFPlRNYoXCBxIMm+Ws+WsXI5
3TU7MBVMWCoqhcyYfudCUHheLZ3EMx+yf+ALIXC4f2Z9DUp886bnwg5hogHHQXIYl2rYiEJo7UtO
vkN8zM9SeDLD02BRlEBdUUia6NO6aDlk4A9VyIEzjfRsIia6jD/+uCCNs7xg3fODlr55v4PzOzqA
9W++r8NyS9eKcNg+6RCvCSKsqD9hIGqC1djYnNoNGxisZ8MFRXucCwci5X73dbr48Lf29xf2zyH3
6LNCD3aEQN8LBdz2yLvHDGVVzj7740vbP+lJ0FilNs/Zr7SlQd5XEC/bpCtJsfEe24ImSjarxp0W
0QHWxd1b664QNzhPpYsYY/CaMvzc7nPRj+tYCh2Z31CMj+FY0qiX6ZZ/h1hiVPwp2SWObOdmZG5z
55nbRdZAO6n7BVl/2ctpF9iXA093G4wGcR4+XXBszO5VNAXvFWjsAdAcMN0Evapzmzf7X3fwQTsf
UxWX0gxnlCQXtZhacFG2i8KsQABe/yGBELCL1HvPEKl19jk9xSBtJ7r54m234ZaPFo4xzDRHvFaI
hKawwRd762QWDf6uBBfkFN+ywU8tNiow8jhOtDuzoWC2V8E8odu/nGWMGAztOsdHB0AtkKD6tH0M
3v+iJLmpS5VGqVmhDc5/Ts23p0lq+cwborAYDOE4IDu6dSOMlNCYTtlzcwULak6BkMwk/cPPw/2i
qGgI0MOqu0EXlA+obteFA3nJRBPNL0k/Ydg5gfBB7N4QRIEAR0B3Z5haThSj6As03FI0f49W1aF5
6+sCJzg3gGRe9UncRwMrduqSjxcsuYTEezMPJSOLWgQR6JFNuFiRSVT6WzvvCX9L1tI5SlkC09eV
I+WPA+SQNEqwv9LE2UtKXncwEjoC60g0gwU3slvFZvGWiAkWPNDVoXiq4vrVDvA8hTl79uiLy2Z2
z2HQ57I6Qi+SZwqQtIzoZc3TcWQJZ/aJX6Lbu+qLdOH7koNQyduXW831QzTwlgCNuOe1dx7kCexj
p6JRPZ6SDRh8Eu2rtl34ZsaiwGsAVOQl3nmxVBKcaIgwF3+h9WwcOK70F5nmL5dupA+wxvqpL3ib
s24F6vSLbxPEgY25as7G5slWxAZsbgjJ3GLf76Smvzb7TXgfmdMr8MN8+TSJLDU9zG3bVeZlg9kg
2nXmtf2JkQmPqcN1Vu67Ft1tg2bczjo2FmTKCbl1jnxMZ8/vhqRudSpBu/tdqTZcAc0mE4sHLVYi
+zqZB2V+ENnvmnCkSDM8eacAt/FhzL/Cw5i3za6h867R+y+CWe0reOUDM2iSudNr2hnvIIsQ00Mf
Vq1DX39zRABPfq3QKpvwSE4IAUd7+ITT8CNhpzgnNDqHZOEB6g/owdLX5E2mDbd9u1thBK/Wa83m
aZOvvxGvzmYGA/FdRsScc8M8vXEEF9i7n3pdzwNrFvurm242Lr+r1vXfSBj2pqR7sjeBDoTRpggr
oOrcYd2Ur8nWhpzCNhBzt6tDHWVVg1/uQi8lGLhAkRLDGGZKR3wpG+USBWsCPdTobjbr373hz1Wv
DzLPeuAFll04GD6Zumr/eSjK8I9xo3f9ek1ufV9tbqncnDQMlCYLL3i/T1FKotWo7KJV5hrvqQpo
6R/5dICi3W5D/DD5CS89bYv5po8CqtELMCNYNjZu0QkBSUU5NqMnTX2V88Om+gbMC1I/6J1+D2QZ
S/uR/ATezA1qFGotcsT/Jo4Sy/iou7VyCeD0WPv0f44Luxj8VhThj6c5TLbXBNU5RHohsWK1iRqt
ao/Yfq84FiaQddT+3AsM4U/BJlymQjurhQyVtuC36yMT9QiQ0LwMqcZyyAwIedpZDuwqzpccIIi7
6lL63i2gVyNRUYphNzCVsiCe8nERqmle2IM1ssTgjMqwBmwy5d9YtzvMX2M71cQMuJLtkrtDg15V
qsJkAD4h2r1G2CYOd4TC5rnuOqKbuxnPdCZ6q43hAx/gkDIij86nx+FMd9qVLor/avWMRMYlgaEd
ANrGBf6ZWAoLIDmWFlOB5k8pnalSxeUhnb5WZTjMsfpA4y8Z9Pghf2DiLqtbdpixV+5s1hs4OL2I
USnRshKTWjykO3j5eJCxIcFqQ6do8pBskAxnLfaShWyiATyuTcG7f5XEgVWnxr7+1AmjKmJcQcRX
dpzH/1xUVWInONisFyJ/MuZ69TCiNxGRaFMD775kNntORL20E2ux1XAmrygs5EwQR1iSpueXyxmy
XZkWEvEhMjtBfW6A4DI5VJ+do5eKkrWd4pLI2ibdhBGjKzNFUCc51gE5wKqAZy37EBONKo4URrKf
chlM7+ngL4rEieuEHpVSkydmhFeQrWoNqrFIfrtyRLlAHUca8dR6NxoAjgqvT3YKqceSOdiNEIMq
zujdo8MonMKz64OtNPUmLKgA2h50cmoiSEY3YvuvOQDB1/qqMpl98CdKpQD7XxvKnqXRfG5UYVrS
RpLP2kRvIRFXATxbYvQeNdIKlxbQLGXQuINkFm6Qzh29lidnzoHhej23gqVdAnOS3vPIejKfFTG8
P5gtH9rjRzd0Kbhoo4I55Y72wngPa5pDmUWgI+XBRVp+tDjUrLW6QaztQLLHyTlckeLawGejlC3g
0aiv9ZT2JXY2BQewg1yLMfJVrpcOQyNN5DWknvwO8xc+Q2rKvZtadIlr329mhizMGV6Xa6whM51j
rDxcqlX+qGJrD2ZoZwjNejQA9zucHy5luv9k8lnUWVtqIU2jX3CTjfd2qTNk28+VJ/1RPkYnsNqa
UGn936BGngw32GUMXKJBdBuPB8xEjxovYqFkHsHmH4troTlVzVJYvywruez+2DpygvZx2gPJaUcS
8mQjQVSqNjec3yYdFZ6jnc2l+shlrGJzzJBPYJmVBZ7DmH5BtlGtU0XpKn40HxggVb8YEtGx28i4
UA2U5m/oyPRBYxI3WQgXKlIgA6fipyH6PDQWRYqfv1FQQXAwdt0uszinM7EyHByV679zLluaYQia
Ceg6oUpUzi2rWuR/6mFwEUovN0/watNi9z1Z+6K/JtUUdNm6ib6uXkOt8ewO1RcFFpdfVE1vd3au
k7zJuYAdHnmaFZAYWEkgBto6Yq4D9+RuNk9UJIWJrTVcIpGRrWm1fp0k+NSk/pr1ukM5+Q/uloKg
YkCNcsgWqLp5xmFDTtECVdhyjydIFYEnoR2Z7/+uwdH9woYxVYaIMyGxG4R6h5mcE6So6+G1Dtw6
GWXRkGJhh5kU8qHqPJiLmvG6e5rABiFiI4kFgw13AHxesOnxo92gyr7dsCrh4FVRsRwqDeaypPZU
oDiT/qo1zwF26FUBNTEVkeu8S+tcF7ZwplA1M4XW7B5pyeQ+Y9CfmjUPMriqqjlo4gL3TopnoqPd
vPP9vi3jzcCvyMjiS33HuscociQKalKM+7RCQvyHF28tRb2Tr0ER23O4oA1X37aK93Jvw8H1blXZ
Hc7RFU+a9Ri4J/Ih1szAYXB1XY1lHREnblKnzwUQo5SSNE/Q22uSLy/LLcP7KcxMeAwI0gm/Bypk
rtAMPcB34O2FV2d/2B+nEmGCcbr1CvZ1ZR8c0da2bIb0nzYH32iNjpaHI+KzjNnEbqJphUjgqlkk
L2zmop8WkF6jaRaHZguSVP3aqDaNATNc7psoZBK7Ek5BIU9rvnTtxXQKf1+pIOLnAhPeCmMOgNjE
qn5T+p9vDqksbWJyMZZs1PuZyk6rgHR6e1O/F+p1n69nU3J5oKwmQZ1uXw4pVE0LlFni0xSXQsKw
I+2CctwgrrNTlCvDQeuU9uHBXCiHmpY97iw3lTDhmxwCW8CA6I0xXFsridvr+qt9c4WyTz+VhTf2
A4mQyYgfFOaf1uJ1GEblOwON7TH4v7m0J8Bb2B5XTVIR8uzWM1KZtr+YXjqDbguE+4ulb1GK7BWg
wKH3jdRjMy7d18KNylX0dUePt5vD3TgtMCTxyM2rcsHvIt776EgwyY0kLhRt/l5A4HTRExfnrg+G
DqwohkC7jaB0KBlAXIDTaLgRYDxhn8/kkaSNdcYTYKKmmVmFFCEpsmwbPSvW5f1D5u2dz0Oa0Dk+
bXmeSeBsMy8NOBJPg1/9gVBKZXPvYT+UJEemhP4jVWJaNtPPw2RpqfmjF8NS/+W5VivyQovjQzLj
3xBBp3NH9klnSMWU87ZojpPv3vFENmG4dg4S5FEeCFtQViRYpAtNypFTcHkUrh2VPx7bC7ZF8B/l
77nTJ0AdNrzlAvpln8P9qpDlnBn3oOBRI5KtX6/uhLkeMeYfj8F/pJRDgtNewt/QMqZvOU1BaWo+
XYqFt5NnshPKzNHpkJZZn/JbQeXnnrZh1MvxpZZi3UQpIkC5CbBN5zqaO5N/1qCeN9BzPsPqHvep
5rdqZGFPehgwu4Rjk7anYGYlswfnzrxN4cbPHkHZxpBCIO5o0u0ASVACKR05mAguQ8WpVZRtiQfU
PqwIRJ77i5V45iFW+Q20TQ3nQAS8kiB4XarnL/MHYLo/C2hgLDPkjLLjXo+FuWr4RekekMXh1l+z
jHVFUfzrXLbdwJKRvUX8v517Q9bdzt0JiPW+MVWffX0Cac32WLUmeuhhCGC3j22C4tNZ3GKKWzIW
1vFP+byWG1gpYl5JbHh3tz0q1NEnT6sfdY1WPpatkVCVPHQ87Ykn9Emts2/9ydW4F/Ks7NI+qVo2
TIYnW9xQv/1vb1SLgqBM4tRnbu4UTgwReXOjCbEzc7usntRwINGhN+Yq0Rq5H+v/6J/lfoOO75Bn
dXtAlH9GijbZ3wvb5wPQIckYKTL+PND6wpZSNEW5JrNE0z4EmmVHjAhsCWYapAScG3cu1cQpWH4g
1oHkD2agXjzyNp4KVjyxZCuAzOnGegCP9qwZSszbvX5GsUUJUSKrLMeZZ2TW63k+YAAD9Xc1uh1u
0OkceGONGqN732itHDKPck/EWNt1OAAnqKaufGi1J5uBqNHxHDv4UiYMgwJPzuEAPp4mHg9wIdKd
bZbehRUiZPe4t5o6bUk6ruxcKcpMTDKIuJpeCvPLSPJm5kR240T9qKvgN2CnJ5tihJX/RiZSdqBr
DjsUnH82H85M4SBtUnbtJasDO7QO1cRhWPTVyGqtgnSZniTLSvoZWYOZjuW/GcO1XSnPac7C6GML
5dx/TF8aMtkKQiCr0hgTakKTJMjDDbadi8p28i8FrT9l9r6Lk4xcUdEUQeNrxPuVAeSwL8rTDJb/
+x7N+r2NssE7j5BtzbXYz5IMSzANIfhNObCv74JroXibvxRzl5i/jVVfCGuc9qJayd9k0PL7D03m
Ta3sbV+Hwby/3MIrzQCUmPhu4+x4HVlgPN4HRQTI7S1ePiGeyxQk/J++uDGA/kgutPPeAS7ZW869
dVO0tOuUVvx7B/IfIc8RE3bv+LeIhfil0/WAS7biPCFu5Oz0+jcCCPUdOYyKjhXF3SpuLxt1RVcI
UhUJHVzvJDcycyIrbKSS1V0hgBBpo4yAexfULQY49EL1KI7NW6VuHUcaCXHn0ommnbTY21uepEQe
2Lp1fg+yNlPnA7N7k7WHUJ8nWD1rwCuzHylJDbsYbplZvWj2IKKWlo++tMZIGw/4YHsk1jlscxaG
/g72g90P5DAqcDBrXgN4cvetUHZmux/hmjD0IYHL/0XK8W4KVRy36/gk9eTOiN/uscaQewO5kkyl
6meQOXzPdlj9kUefNDp/wpTpAh/4YgLueE2dGZbcPHKr3cDQFK5nRtYjWsEhbjb1/5jBs1NK0q3d
YB2VTUjkqURkDwSFrF3JKeSRJZ5BknFXHum/OkIJlrSw/XijpSDFU63Aap2zkGRh0A0z+zij4aUu
H4egAaCqykZHbFK7ywwSHW35Tm7Lh2L/N2kAgJAT+tyk42N0zoCPBmeIDuk1h2JjG7zVunQs2h34
6RyrVOClG1tjnCvf4cmYP06hTZuKHKoPx7mvc86SsoYS3KfM1a/SJPIcwf+c+YhrwqhuLRdH5IhE
WWlb4NUUYfmWu0jPcVFH5behknlUvU2Z1Ea0KA7wzDiO7n2Tpc6baTT8oBmy9jpknUjc68lNt7u2
wILE2KFKLMHpeosyis/rVtkxV/1ZryArMkARPvudl+oa/zhu1OV6ogjDnrO9z9UGVvnp8OPLzYvU
rImSNyqXSpzVdDevxEukNUwEjENXBElDK3CjGGc7aSeVedpS+CEBDj2FmKOKE6kxH2j6PZT6KzyY
gRzvWxc2fuDawQ0r52kI1PNC6Z9v9ln2vVF9WJ15aPpqzvbNMi7H+8ux9/A5j9X2ARyd7c+6zyMj
rJ/c2JF04Y/HU82Wyhxv34BAQx0unB2uSJ3gsYX0EIgQv5fVaQvIY2z/snX8j9BD1VXOabHDRkqD
4rCcQHnrdkkD0kXo8LP2/v9yduF4B8viQUq43zHbp6vcepuLzUNXIoiU90jUWNvRjtJpD++pEDt0
uHAcOLHuQSVJj8Tee6Iv1GuoWUXrQukgoOp5EH7vbkbe5HFSexS7YlU/YPxJgbTSMswaqWv7Fhyu
syf4yd9GHheeJc7aWHA2AKsmdUXsTgpRwcSMBqrd406MUytJJvafoBBp6BoQ81M/2uM9zpU4W3Jo
sXzaa2b6mnV/kG5sEnvEY/Pjrdq3qntD2CsEvWjLKu7VmHXjm9iN8KJbu2HZIBC66nBclaTKb3QB
r8A3/fZHHuxz5jdI7Dwll1hFEtw1E/6zGpa0DsPi4U81p/5xF8QopcgqrnS+s0wyd9+BdBLQ5v6X
oRo91O0Bys6+p6xh8l3VB18C5XKYbpj3baOMAfvfNE9hHDokSM0eTc1KMTQ7H0e1ucaZwtmp47Wf
yT5aiN/TjsHLZSXvzv/AKYK156T/SgRcRA55uCUZN/bSOT7y2enqq4xE8rEjAeue0NIlUisYuOR4
SgNLbrZb0sLgfEAy/d5FVZi2jclHz2MNDyvXH6xkQPVKWWRDvoxVce1Jvxk9DFYmlTZav7nf/Hr7
QeclvDo4G0hmyuaXkVUbhvIxzWTTfHnrEP6r1tNN9qWKpAESZOGl7M9vR58/WQCa+kq+eYFf2C/C
oP2LrMFCPO9TT5gTeDe02EqLf3SqESkGOe4taHeWCkttZj6nUwK18CTcq/vwmhDCbOAoEjQt37CX
XkTYIiGVAqfvlrv3tIGqwpFhmmAtexjU+aaSQITXMW1fWq+n5zlvoh8uYVxINt8+vhETmGubvBHx
y+F/9uAI0BJTXQVZpgEV++O6X5oWzworgq5tqy9asVEMh71i+f5kzy2ViM28HnwBzr0QwRowlgpw
zZVF2KN9BHEzL7K2GHu+A1FhYCeWWn//2HbRqK0whg+Fmb4OFgw8ahBWUHL0fHph/SqnVavs4+02
Rf0LFoCE5eqXRW9zkVPxLCNVdR74JEMLQ4yKOStzgeXh/vInvm38KkaX5/icJLGSLGBongoUZH+T
QYc2hOzgaTY95Wmk61NordYn1Y/xtU9zUt4e2F1Eeka090N8/knFNMSHyNQE0dc9jGb7G6FKD/QT
oeg+PSyz1wA66eZzEXrTOFhF45F/yu8G026feYdR/vjYF4Kq/CrU0WSAhtZhL8COo8iBNfp2Q0Zc
zETptVq0hdU08wKyAqGlj2ukapLA0JraSaaaPEhqKR/+t9CUy3JoDVUUBQvf/mhtwaLRNw/c1XIh
UMohCeeA8YeYvksh3NI5/hlGH4HnTof8c6yzxZIecyZ4+fpKnOv83tuUqzxazYVULxrX4bPFt0yr
pPMYRWZlwswv//vvu+qgtWbafqzbK3VYcsSc6RpzTXUzWDI6Wb76t7IuvfZmQ61t5Cd+SIWXfVPv
VxucsHLsP7gEV4xyJDIX1Ewq59k7OTKxWfx2fyrwhXvAD8e2s0/N24+TMl/pEIyJRdcJhx9+YVk1
6YPKsCwp8L3gmlxdWYLN0SXejU6dct1DCOFNH4RSj/7lVHwcQwJ65TDZutVj+y6pidKfyDdxicxS
zITW2EkZT61NeN0+vwTUeExsRmR2PB1oxx6eHkUk8seIu0JMj/fLvQX9mIECp0ms+Y2EWh3WIIa/
XDpLSB3rN9lZP0AFvDKxyLSTCMhptm9PIgi68rUgntoCrqF9hoHBHFkQThMejtA38fmrPCsSgLp7
ppWOQN+7XCVwY5JXZlhNX4RK4Pej13Byxn2LAEf499/g3qKzOyRQrgAzd4QxUXHDj7wKfuLQg7d3
/kWiGAKTYtkca5By5TUzp1KvjIl5s3ByvUK8LmXHVACE8hmTybIphZS49xiyIhOF26Hl3FH1KvQ6
/c/+oTigqs6hjui0AeSwJJrlvdCe4An9jVINSdI34n/748b1JKfrJIKJY3Gh3H5S6B4bYKqN1pyx
06KkJNtRQYD5Xxo8MiPO2MLQuGIhSTpbN0ln8RuXJQY+XG7LeCBROYqGG5zdxfpN/vNxFYBXXui2
g8/a52EpL+oeQ1bF1Fk9O9k+Mt3pRJwx6bOd6Vxp2G1tcTAhfbtSb4f+/DLwmGKm8O3Jw5p7jAUH
9HuPqB6bJK+lF9T7SXSuXKpnqya4FVPYqfjIA9ryNNw4V08dswfozDNzP4RPCyLhVTB+Vizql4pE
yWLtbvrKnluRXRjo3vIz7ojBGixIjBGexCW8fKiG17hrbqfaEnY8RSdADaO3PSGQiZNLHMpzebTt
6sdOqByl5yArXsl+oz3FWu6EEJKdaLVTfdxU8K4ng2aGvFfCQ7ItN2nxhKP3HUD5jFW/e2/unYJw
pCetTZ6mCVTfXtcz3VrDXRfyp3W4o0D3ZcPlUu3egD8TdGCbSSQC5NbwDl/R2okmVKi4F1pEhv5n
zjDmpfJDF4FTccLcA/68y+XnotVgq2+JM8bI0XvdhGVXgmXgjKLxNU+rHC6pBPYPx7z+oVle/31v
1DzIzm2gKP2SujDL8hGwTGdA1rEHf7XX0W85swpPPBBl88S+/QW9TQI+/ssSw8nqxQRphYi3yC5E
BYaL5kUSsOqNzSI44olbVsMwjQQc6+NZOm4DPzFcCHMOHiQRZQB8hhRovVL15GSm+jUUfjwPc8xz
Wp7TzRMH+w0CCqEaQEmv3GSUBIpsO4762OlSzwmqHmzNf55EK2ZUYfHW9NrHADobMwAGKYT8tJZc
v2G+HXr0WIQLZbTFNu+zHlz4IKvvcyzhNIOJscz0x6CPIsV7JMf10PSMa44jMD2EoQUTt+YmDP9l
UCwqgpEAoSVCUFu7agSQVSMc7Sh07Zf73wmEJW3u9L8531+qiIILXeKzs72MS6TdiOeESN5z7AsQ
6FAIJ9ncEML6wuj6U/2ooqPRnZpvaaUxiTuoyliyYKKprxfkb/GJyyKJNG5lGJRTROOXsdJSPMut
Z+qZMor8Q37hMNoVCpwCHiVUweZSXlpv59i/ZkBLjwEZV8PdbORv9OHGgKxLretM7/iiNChCBqit
7Hn4BsyOTtxN3CaiJqjcor4wSmWoKFtBW4Awfb7KfRRoSzmz+EGMK9cQwz7W7xR8PhEvl/AJBpGW
/bd6KZyFHw6AtP8rYeGkgnQyYQ9Y8Z8cHUwGnNUXy3dFCGj4c6++R8oN1gcLnouXZPWD+OS7nBDY
blqW9FKHFyHS4A0VmE8+/2GxlVdJR6QRjd5jNfpU/EhjpV0xFO0O8R+VZ2K6/T79UG2CvbGAXBm3
lxK26PkxB2i7ftVpjhg3s0UccL5wniVOgVx9q4QWj0AfleCL/ir03dVU8Bo9gL8u8S1iVy5GKPDy
9/wuwAaD6tHkPvMWhz4WUZX+8hTfUXTO4+PfCAEWUi/ku6w6E1iSyXhJOnDM0BQoxne0seK3Y8Vd
ChPk10Tq4DShdArMTehuYKGrF1DVWqNGChruFzzr34IP2vW/5Ud9Zh5WPnVjopEeFP+V+n6RC+Y+
WZxHiRjC/uyM7unm6eUNGbbg2/LQtUMoScU6xWOIxLpDo5hXJfku1s0GeWLLCrkL4TGqB4IT4sY4
lwVgLTASku2BzuHxFQMgRSz+H/IaljGWNBDP4sJwLaFtMZvBj4DaFCE8CWSZ6lfw5cW4YZtBM6N6
gAV1XGMN2fSZtDh8W0wPU2OCUtHIRUpoPk6zlmblXmUEKFEWqBSpblO1baYRvBkfT9fx+NUTibNU
8W8Ku32CeRqrBLI51AvVpBWCaH30iOyGCNY6Vkfd5zhNWhocnmksCCaBZoPqPIby57Svf9aR1+q3
7AwZruaGmX1H5gCXBpa3rEAUYeECDorgeY9z10NP/ywh8ikgwqZUGDJyeuyUPH2EqWG4Lj1ioyxZ
ZNeF9naKTijSCZyYlBTAG3+7x6DB0xAQT3WMQk8TG9eqbQoPKqe2+O+45jcV5p9o4jBy6gqPf/4e
IKnRkDGbMUYhtY4EPs04N4Bn/MLVlcWRMe8lSH/qZP6C9KHaj1nAHpr3BodJWV4w1mAFai9SdEJb
k7Ru6OZTlHQPsBVFxMKpxOTm4azvYJ7UwAayOGafs/nApSoZek/bU8QUXtHKxq1CF+RgOdCIwMIu
dgwEYIC5zskLQggp7NbpSThLAlmrpdKYtAGkmnwCTHjiUnBKAEyxtBVrmjwcT+W62EUauzr0ZQJI
VUbCTOhh9tZI+Q3ptg78IvSqt7yNhVkYrWUZO1pM2MEOYFy3WlFaseQaNthb1s/MJoOUYltHXexE
9efxfslb3C2fyOhEG9MvxAmG1gYdT47YBrZjsTVhpc3gf/caUUyBFlSoQcZRmVZ15h3zQtCcXxtK
MoBK0DPi1sxOyTPj7zrvzsnF9CKl+rmplfjcaM9d7DLY/QUlOzXICA1THpZxNPKq4YQ1Y8jeHs1s
GADtqs3JRgtRUrideDlaV46YM7kUpsY9Gd9FyyX+NRNVcuQUJ4wy7V+lKGDzmtfdvqgaD/qCL4w0
QryV3AUlGlRj7VUjYFhjFjSOM2XBMMtOMOZToU+AuO+GROeJyoa7HKDebUZfCaCNfKterSKZhmML
3hIthS5gD93oGK8rBTLZnojX6SB3/VQDyEspIFOrqdd5nwTwp0AlvnJGe+fscVFVSSMoohsyuowl
Xi1LMipvCXJ9azsrXGYjZD2brg1OJRQ/c1T5QeH9y13rOCwzVG7LHjURBbEpk+oyrOdPMicQYiQt
Es3n5847P9GjwJm60DMkQw4Z1T6M96agHRLs6Ms48YX56HRGJSH/5lcLn3fllQ/ot+QtsXr1igDX
abDDSePm8oKZhJMadwyTlgL7TCQ0O4jsPsXbDPBVQACqk+3RbtxvEcSJG1Cwp2qWvAL/HV0H6EJV
5gcaXQQeMjKC+ez3lPWXhf+IXJ2P7Us8C8E++ACPxc2q4m8nCRWYFydfX69IXIyz1krbitJO0bRw
h+ZoQC/Seb25gjAnatCS1oz1Pwpt9Oq5t5lEU8KBPIfq9aXKRg8BkdxKYh9mRqeGnGDf7bieD1oQ
msf6j/JB0MGlz2YFZkJAqliw0qvwI0nv+EPjrdQ0AqZPXOuLYhtQiHva3GkmDQESRNTiUQ+y2/f5
iQT6aSBbTPC72RJUt7uSyVjw03gdQ6oHIm9B9KuBMwdldoIseGfhTayEeEbcHuRePsMaoJOHjMAy
PpnamNfpNFKTCJBvlD6IeB2tKsAif2YdgIVUraMeoPhgDnxYjKec/lIPH3MWLrN2Xhl3FXNvGvZM
xajXOCyFVYiq1uLoeTNJktNJoJt481JDLWuEP4a3w1Z3jkj7Fer/1QwYbgdz3VISWEY0r8+O+IXt
Jwwd730YGnkkL3VWYELmD2iKcxqFQY/0nKwKZz7SDbEoAsp1bWppJIQaegx/Jg4GcZIoSxI8uyWM
LIO17NBpVE0JxJIPeFx1PXAvUyB/ZUyKyBfYVYWLFk5fh0/ePAZbbrbYX96FypB3OEI3oB5SiIFx
nl53KwENWNvXvis8KAOvEp5l/4eFVFS3ngdIW1t9UpbelZW9QRzJLYRqEuuCTTtPaZduY8xCmn5v
e++VAitw7p4fiUXfhyMbBH/LWv9HaF3xNZSm9WapgF0Hktj0NY26F9ewJRXggsJhEhwJhPgF24E1
wu2GFmR1lS3SWdYAOhAG77AtEuHPGwv7WXp8NTBrG53GpQfXawRZeCd07zNYW9S0ANXqMMaybfP5
f0NeQDMgGnqGrUL6o5oxkhsY7JbCVLfA6Mn8r/sZlFHj5P/3dkFbWNypsx0mgCQ86G5bxLz8hMDr
cKGPFRRCj9yjB1H9GVvlZYljW63TZj1atpGumkeGJuwZ04FXLDOKPo+n6i7VkUrbxMT7SYNh5ZUw
dWxnM6mujRhb4BZJZnu4Ls35xcrHIGyPzhJ31STwiI9X/Mn+3tg1d1YH5TVK3whGTmd7z3yeaIa5
2xTK8nDq4WqkeAnHi5XE4LrYs+sq6KOzhTkHbGvN0lkQg/aZ+xJbZ9rX6v7tVUChgJRQjuX9LwF6
dzkAUJ1dYEoxystuXOrrr1SdqhQm+3l+FGeFeD6ovNx5JDno4qNuMsERp+Hx1Ntz3h+/gyT81QrG
5sBGjc9sGBTARHubGyQI/kWBnbJgCw6jBoAMWubIE4RqVH4vZIJoIQfyF/DJF8OWpTOJlhJypYBJ
ReaD5SYWGmVUo05myS8b5Wg6V98FRq1b/n+5Z8T+AINnssHyUPmAO+9QmVQGOzCIllyw4wivVwrR
4Oq3uOKwuhsM4+xlqSgd8LYm9rf6yts3DZ5uItOFl6JH5GtJmVcrhUY2HZru5zWPDPuV3lUdsTMm
PLHC6N1G3T42XxB4YBPWtJyzKrPt+zV3wGhRujq62NqjTC12i+tUoFP3orEKnAlOyBoA0oFCFODT
mRtofJAglRH+r1s0u8qHYNzo+aZrOVCp9ie5ONpnWiMKw+Su07qGRxXVJNdczjwMtuwA4G565bpD
xm6+XmZu4GTnzGxYF9CzmlxlHKpGPkpimUwz5fdxakMhwGeCjVWK2ZBv9i5o+qrcQk7dfXt+mGaX
8InwNeerlKibbUq7Uf1/nyQcs9PotsLGKbRqW/NiBuAvtUS4ev1aOyBdgrHurhRtqQ90ZGxuSi7r
3hWLJJHs8flRAbpNt02gsG1tSgEFXk4/YPUlYpdt7GXE9SpK9Or3f+h4fcGl4rtpY8Xuw/snVX3Q
9A3a2jIYVXzdIglASftplIXC/UfaDlOOrJJpx5XZKnGiYbH9oHj4WvAe+cwu7LNfs+InB//Y5RHM
MpB7yHWmR+eFHumDCS4eNrd/w53jc+p9/WzJB1QYNu4XqcNo6XyUxXgd2zFRKXwVEw1BMRil58Vt
JFtflojR1HxJVC+566BqU12jpkaTi6k2Y8TpAx13tbpiuMyvte3TI/i+gYrsd+WCmkLGIJXvrwpR
e7+YE6ei/rjJqCANvi8ZERt3GkZ6qDU8+rWcWkKdSXlQVU+wE7opEgiN/9QivGFHyJp9mjg45u7d
8Uemte7tjsHo+rwtSYDNlO6kT+sf//GnMPVmFsK4MwnxBUcZqeUykWK3xGYbZDg66XJaeHkJL1YN
scRnHM0mf2xUM5HNqUNZtsmlM9Hd8MShLh+ff1L4acyS2EkqF8UvlGOIdK812JGHfK2CVVnRxXSM
42nnjfep2TYEW+STvUoKWL4a9DssnY332gWOx3BWQ1jsG5s1kiwBaYwJq0HW1tHerC3myCs8zq9J
N2Zjtp2IqNtm3FS/d4tCR8g5MXBQ6fxXKl7lHo9JAWflZwtR8Ny7xjevUJcMnHHZxloJnzqNClmj
wAkLi/355mBYcH9x4rbBGeb76ltU73cTCprTI30IPWcLbn9Krp5zk+KZhGLGwyr0fXHKee+aYHN+
WdbZdbyfh9dtDnO+iP84PeDTbODwSkKRpXBpI5ad8sLUu3IJno0lJgof3jzhNYX3CJyFd/+4sTfY
WWOvv+y0XPhfax8nepBu+SWsukVEfyVZevydtulR5e0IJ572mQxSnNw3UiIJkcGgSujb9ZxL0cx2
5/++1mfCBThV3vAewV+0JsW8aaZM2xXnxCTqrUrr+eaf4G1nF4cA4IwRavYtVooCXcGUKk2Nu/bs
AlM6cB8LJa2tLfKjbmdx+CJuabW9Epk5/NjK9BtvHC+57ZGN/eWx1B+EKczo7mNQnsBFHLUlAUlg
s4SMPSRK9IX5eQNu5qa+l08wwC5bZKCcigGjaHGs8YEbYEBKNyreEiKZ/Llg9Va2K1b7HydUjAMM
3Obt9LSF4MVB02XPkffqhyZ4A86xmP/s1dljS9vioVhwF/svc36x7Ii80xfzjOI84Qwv59IW+Cqd
RjGAOuC7VOm2xsI9HWrkQLnmZC1wluhkwkr/f53Jv5Nia+eQV4kWfR3I4ELRaRyrMYHTCsj+/kTV
NWoY3tx47w6foURTFlWZovRcgV7G0/wu2eZ8PeYDEvl9HRBbBEA5LouuSKmDfj1ruG/9F7XkBaUu
hvuzp3lEtuBmgCgAy61DE5Fg5cIcscLz5dPj3j/cDgjXPD7kk8VVypgDKDa7N4kc9c+W5UvV2CVv
EWW1JTaooigb09cHQxkFM1GL5KtwPHYX6Nn9UDU5Xl8YUn99EInInxBkVI+QcziufloKK7x4q4Fz
m/b5KR5Yp7Cv2LVJLLaY3ijPyn6zbQIHreHGYCa1oFyBP3KDLc5HftEWDxC7g50RDeRE3UFaMpZt
VTfp5mYy5n0gOj0uPhS7wZvwJas1YvXKyXqQK/PUIqi5iWzR3XiAYyDQgMCoN1lu/f6DHolmDo+g
V/A4AFwV/95TJLSU70LdjK7o5A+hgec0e5j5/jX/HLjvuY1gNBVHQZzvE1RL9Q8ZndPWZch/mavr
TvqIqM7ZLarVhO7vN/q4i6uMGc9XESrUH7YhRxtXwg8Q2JiCD6i5y0/id5GK2vte6KUoJ3t8Uiwh
hzY2Mzrtdh5rSckijJMGg5Bc/swERooHv4iXPhABJmf+tZ7lpvAdiAaalQnkaBkF7/ChfhgYTDPb
kJYRaDrzXMDMFyW74aSuGbTp+lbioZ/1RZvPMJZ1WZpihFn3l14jvIii/zKry41D/aTTEq1yDMFk
7B3EnjJ7Ut9kFIXZ4P6fvYw/BEqcbexFN3QgioouzaDqjrRvPzwyMV66JhkMQpo7ss7FhPiXgN/1
LLOs/Agd/stLk00Nw63ye+O7VOaip4RfX9e8ZKzV2pEC+H/Yfhb5nwwfuAR3w5vyRzfPTGiTWkVj
SZopuynqj9oSSADbML4l4/SLWwkFJjXQRWjg8MKJlq2GSBbrNsRsM0+RDSdUSrQKWIqpiEN3hx/S
xvkFGMX9jW4jyKUY+Y75i5ZpbCCyQeKS/LF40k5WSQOI1oJYkM2NSpSmmuADyn4FLkjC+UyTo1EG
eVAhYTM/RNSKXfcw4zXOdUj7ckuoGt7VOFuGeM2pDhaPUwCFuOE4G3YKds8E9U3nlBVd+W9+2Jny
VW75SrqQ4NBReVhPASR/todiqZoSz4XlC/Q/49BmaBpmBxG0kwxFusHheQwLmFdLqI1qxd2VYZ43
09mwPnyrqQKR4W8bJlrK7yeJFLjKGJu8dXPJAq3o+ttssqwGZyu/tynnl2Tgw3YT4uPkyqnDpEIl
qk/vNbW8PQKfrZ5hqvUc3BIn2MbNZaYMrDh3CZFgDD9kB1DFcIBjnsR5tfobo1O98BiguDATKsMI
m7MnLmt30z35cY8fFuEvabMq1zCu196OSIMYHUOxPaYoK319HZVi2akLRpwN3E7oqp5xjOZw+/nB
oxxgBxGbYe8dWRhJCTO/b92VCNmYUrQbAg6NRCxEduCeO6OEYZ7bcP5OwwN92mjSCwgR25ohXhrx
O6znlkQjV+wJSoq3ZceymK/leq1KfdQVdQjK2gojwYMkcnUlOsNR5PI0gtjMqC3Pf7U2L7gICchK
rQbEfsn2OqUEqdwo3dQDfBSQkAbnkCBdXFfEBcRJcfkYH6vbz3P0BtqHjJy1hL7hgeDqqBvlv1rt
RRQhzTofMwxsW24CuUDZNFuT7q02f/dtNtkdO1W3xVad16+v9IjxHn+DupaGYfCmepNEhzyfCVx/
q2HUaRsJUBpaX1ijOkOFerTJa1pzX8+TntPNp4iBJCQXGhpqa2MHxTmw47xfi0U4z/YTUtacwHJi
KQFnO0anV+3fShlZdTcuxbzifPG8IWwP1Z43E0NbyPEGuBZGLigG/+9Usm1S6icbHNkYx4qkVyzT
Nc5aXTuvlN6duON2UaLHxS05IMYlrRg+QEYcLd4/zUFXDx00LthFSojU4dFcWwUX0u+dD2Gfq0tm
hvBRvbQnwCydFySVkZuFhc3LQ8ExlN3WbK6tCW9TmbHrePEhWqLxWT2cZO22fNXeCvBTuQms8ztw
IqZFmkJbdra/FB36XAf29UzSvBI98n8pFyRUw+zWgi6ruXt6QadYuI07PRm2H0vKaWfX4P3Avpyj
II/3uNdt+9BrwbasJ4X8n3bLavchlKV+DCYb5BKW+0KKJUjKb9V5OEqzkwiKJ7oyYdOr/6MGDiBU
JUH9nV99rjMyW0Z6hlu+o7MAgLJZMVKsDvXLa+DKAkAZmPp/EZ2FevZ825671cajJzyrt72R8JL8
C5ZxOiGoj0ugb6BppcQ0/kdh9pQM+XsFgmEb0VvEDNXwr7Su+LDQa62dQQiMCfN9s1+ZDcEmVirC
11op6I1Lg9E+yNbV5LIJUDWa5MsF36ncSyvU3DDmZg/w1vSkEpm49/K/9/VCtoyfEs5oITGZk1kF
p32MZliMI8X8MSnqia2RPdBTUGz+Qs2FSf/lTNqlzfiZ9PpRJL9sp20ov5GtWkm88bh/qcKcJ+NS
cDxfPiStRk2pSlFO9uNtC487Ir/Plw92QiH2cdDCRKhKa+IIOpZsWl+I5pmEzP+xqct+ydS0sLPC
dqTbbA9qIGjcnBuDPaIQ12wyYFJxYaA7A8zUUbG07thYR5gaLUVDmM7MEaRbuA+qmKb6UhLTRCrC
TAHFl/am/HrSX18uSjkJhMRrF0Qo/6kgVBiWXrNIMI3cKwbblJ0mV2Cs3uW0AIyMi2sP82mAfUUI
RO3PPxXeFpuXU3UwRO4jezqziu+CU8vyPKXW5eU/ihg0Et1CG68tA5wdh0K7fPeN2cjALuXKrzCG
tPtaA04Ypjk1SiuIzXULv5mHOxROfreSeMVXddDudE3UAlYjVYFKOgdjK32OI54zQ21PESNAq3HP
zlcDFVya+DeVhtufgidIZsfcNtvT0HI/+C8qALsbZwH+aV3hH8AtKkLec0SbpJ1x9qUsr7Oylj5D
mC23Oz6oWJoBLFoocxze/8pKH1Jdt6HVg8I/STJrcJiwhwPm7fkLCsA/NboHHUUEID3RV2T5OImU
gVm6Vcs2Axk88L6hdVGqO12QB3ylXRBUYEF/Tg5JNGHXvBp1jSS0paN75Yz54vs9I9/+iN2HX/KV
jnPDIUP4f4+o+qOlS70gVkULCdFU2cfKlHub+4yxXx3D1Zfcxfk8SMty8e1bZ4G2CNd22a1hn8vw
RkPlKOqzeqQ/XDFIz/uC+OP3YFQyG6S0pMYoCMtBAW5eyCUWG0PqrJrnLIqqA064zARjfgVKDmLo
fNlQYC1cIjKIIt3URPPRwewyqMw4WEWBXk+xI3F+4uhqzxVy3nubOJ58kPkhPAcXlWOlb/KX5i1k
Q70H3iLt9zkkOe01EgdmGHRmAPLcaIONM2frbESndsFifKsdEbdtsGPKRhrwiRRanSTIpzd76A/r
ZwGwLhiu4pv250sU45oh+cvbv7G9ieW0NdZY+Oey0pxHSaPxy1VcOvZBCkJfepXSv4RHHrWzE/4B
RjZA39NxE7i4vXIA5Ff4nJQE+y2mk4zYwbKQyXWictKKZeEKwilwFlweWxEhPJuFlE9pC28S9XNW
RCTQfJhZIrXWbv6mh1fP0LiuTkSY8fy1zUze5FX6tzPHtGwmCSjwBG2yLzHPCKJOmh+/w1IJoxpT
HqnebA4p9BOZCDrmaFgZl8ZX890TithBydl4aW6KnJLxDgos+6xPJhMOCiAHlbljVmQDddzdPNIe
am6o6Ah+J6VbDltlcvbFvm8PupTB8r/1cKleEn5Nk3+BX7YKdWDcTTNoBU0F4gDYlfQZTHWI1qPn
KvCHT5hWRv4H5zoHbET3L9N0MSq9Jby6PhTVkFBlxFR3iZJGXqwoZhDjO6eFQMdRS6CsyD1sXI4G
5PGRwdhY452V+2LSKPnkLmgeZzhmzyTypPWQrHG9sjGwBhS5NF/jSKy2l/PFJVXaS+L6A+r9+pb+
/9yhPH4jQ4rfrNciZ9DQDJA9BL0IM+lVk1fzDdPImJeHlWzW6Gbl32pYF3sox/oDJla1SEqtEJMf
h8NccIGnMdLB1gi3aQK0QMlq4/dwAJ7Qmca4x3HG0Lue91RNrG2VNbB15xR/84/+RX2EjDh+h6ep
wsylmKk5EIBOkbDLc+QDGbtgPEUdLC0+H1th+bfTSwTXdQ/O8qP90HaJYt0xcOGgBkKNFz4YE9O4
k6yCTjXIpsgRUx5lM2k3+k4SE6/ugFo5eS7MgBzPHvQ9Xn+juv2x31uVrgEjRQR47z+GnttNQzX6
i2Y2h6L4bHC9e99dVop8I1LzD67tXheDmFWeTDSR0bKB3+YzkGxvItt9JcC/ryosSVsM2ILoUjym
BCEyxY3ddq7wmPe/Xw+6uNXQR+9bjbYtqErHTRvpZg5+AYP6arTNOdi0WH3A1kDFZeNC8ATW/6Nn
s7WPOth+COlELt8jktMYI8bGU3Re+ZFv5ybKdMFVn28WA9vngpNGJ8d93LA094fwB8Vbn4cWXgij
JiUmD5uAw2bTZXtWa2zYPem0xxrBkJuk0VVyTcU2C7srEmirBbLfjg/xrWditWFYl4ZIQURSd98T
EeOj1uoIdiNUqh/cnrMDlgXbc5JRoIzUa6kguBPR/N0aK+Vw0pO446WCMOJfmxVZuFiUHhwkt0m0
k2qyH5YLBmFGdnt6f9L52tynXH0AnJWIfhcFp4EUmmsQ7iSkTkTKREW3GEH86JAaoG+bDF4mlPn8
2IPj74dlrOTvpZlh6CHOZqjaBEwyHhaxLqffYOhy1pVd8p9fnT5y+PAAl/k/CSYymjd0vWtfeYvu
LyG/TcyrP6Ib9tHaNYIFMg5JhEgcftwprBsMRAmwFeISqzPAXucDj9hNHPfRbn66VjmvHRKzOfKj
wBp9aTv2JSrh560rlVw7S7112cutZlyGC96JSX+oilxw88Dz+7fLxO2gVOHn5Dt66HdTnxY5E488
7FIkeS30Gv3/HMxpkpxzXuE3WKGzDMcst1F+KMsAa/FRWn16JEqg7rvk6vUCofkqJ5l/c7zSAi3V
4fEynpcu26GxmzoOPnr47NOeoCrf7X/pJgXEAv8ow+tvOd7zZibsKHzGkOWV+UzuN2efmmdigMtX
/R7zu8HGVQsjUFnytqCD2YTuD4uvbVMUz3X+5rRl+lmAX6r2WhhKLUORucaB068WtHlFAohhCeQW
hxuO7c4ueiAF2MWbJkVbju/lAE/mI8czikUW/fjiCKN01cuJNrV6qc+J/qPkuMmziqiDJhqQTd90
7ETlmBLJNadx00fm0avSBPFgZREJiA5GBLKf1ntl+1cec5htv9RCaOzI6a90I1AL6spiRBi5Puhk
3YC2M8NEJl9BV6ovfqui9d2mdambikbY+GidBOgKweTQoDuBdZIk+H/zzNAvcmrLLm0mRhTft58w
EU6OtZt8kK6KbUlTPlVyZdESjGww2ZfESAjhrNpdRAyrwSuw8u+IoBZ1zRn0XMeLEFaJBbNYoMql
ZOPpL7UM22k+Wu6Z2cY+6/UwJ/VaPHkTED5h6AIFZkTNIIL216HNur3124yV/0D38+wQpm/qB4pl
u2WF0djK3CldGC/GSWhF2Y4625Esr2ypaa2vpvsEnbFlwmsYvA9OhKEzqS3QLHAlEeLOuRQ4M2Qs
O18l1O1oTJcYANU2k3xAkzIjKLK0i1WBCQb4LzHMDZNSW37BGggHtD7Zw23hXiI61lPYCzY1UxEM
N+5PPwUcPs75bIDTb8UACyEQS9r1Q/SHdlmEmTjyGg3z14EC/F2SUDpOL2UpCwHz/5GibRNlYydR
aDw3WmXgWVobFU9AQwnq3hSe4Y9RCHYP3Bjn1jEX7mNNGu/Fg3v7iFWaFTb70WART1IFLPOoFs+J
2ViwI7p45WW3Qa0rVU+y6e4xnc3G0PFj0J8HunfDSsGVrL+4yNPtrPsgxbyVvV0NK3HOGIMoixOx
Q3M2fHN8HSN3m76aNrnUUcJzjSD5c0WA21jUCJJMJWz/gFtehWPnQkt3uKGzTmiQ0cjmlDundzfE
pP4VIF2AImorIE/KaHZxnCA1k/J7ti0EQDAvAxD6vKc1KgIFxroNW1mHtSWlqw308GrE/5+G76Mu
Fbf9opnwFRF4pH9BbXhmZSYYAIrAlohRMu1byaKtqKr2sUecTPg11wulJwXAg3f2ngRZxOpPEZs+
dvE3leZx88puVOvgZCz40FtMaWe/LwnnRouoqkbimWDcpGKRpPEIJf0hPZKAVOe7YQll6+1cCYZB
hhTQ+FCvPbFg+VphtPcUoKJleBSHe+OPA3u/Jaw0lbQsDyFNaAP9wUER7M7TraeOEabpmetvya0v
ZWVi6d7/h80lL0D8Lc0WPtDB3kJnBVPzkDww8iPf5qtaXS7C+jGj8AD+HFdBH2c0tFKTurrOOZco
ZAp5iOVpcdL4090eKvpDceQkunO5eY8RRrNSAy9g6tNMCyjc6Z6xiH6gUjoblcgZae3Ya6lg0jZG
xFmLN6XU7LIPmFWqqGFI7aMYuW2rSU1HvdYWaXRx8UqkTxBtqX44eh+GsU409nJhn33v5UhEYRlZ
GgJCZbXTkmpSPYmVjth2G+aPzh892fdzd37lwWj/EyTlFRXBhofxKDfOcgrbsZFQWGcXU8hmGi1T
ruLQY5PFrNwX6ijpsEM7QsT1nYCFI03udg6Ul3uzFIPOCJWOc+/rOD0InDfogfgYs8VGwh9KAMUk
lM1fqYsEj0q6aPpQVm68+126YzOuJxCvgoSmHt8cL9OkHrpYtbJAmyOQYnklS5kp5zqDdc2SYvit
KrDUwYYniVFepNZ7e3pfvRyHTpJKuShkZDmj3b2DQSwug6ZsiwdC2I9SoYOg7fMXmEMJ7TaVoQbO
40Bo9VsupsORkNkGno7lMBPoE9j2+/KnZ4FhFCf5C46XRi8/BdalrHf8PooBnQEvzSthUy3oc5Vr
Vxq+XX0tsL1iZB8MOry++TWmKR31dJXmgZwP5stlDSJnRHZgE7GCe6v4rhHr/tRQA5wjZLCqRxaf
RHVrfisk4ulJP+/amk0NM9bBMCX3sgfi6p23Js+pnvR0GlpqxVqhDE7N+hBNdYEQERpgkOL7LOGW
RRDM4GMMQhpTqCur7yJoR/V/NGuZYD3uFtSBE4MgoAI9ytI/YnwcLmevjJB7EkKPuuYmL3XENFe9
DD52RDrmNikaGUXZP8OsVmZNA31a6nli6nLoDUx4t6fHjtGLmIUN7/IPGvoHcyse3vaaIUEXfeUk
G7lSCyhlSejCPcSCeOTl4e1uKwN4ULbu+1VMbO3qddJmEyEZRMpo35AreLpVas3W0aceJ/Y5Bw+f
isctP2m/v1b/C+UcDqaaoyAWSM586zaUOtqUX9drCs8m9D0vcH5jOzi7RLOu8QA+0Qg6NegM/Bnv
0+H1NDkt0OFO6kLk7DZujJ3eluOwBgxol1htS+hDMmFaE05WAhHfabOuu+w3qg9H4Nhe0IwLc6la
HkZ62vqW+7t+yQf0Y5L5KF5jAmauMvs0nZacUvW9gWYHm2Ltmq6D+vc7g3zMjBFppsDU5P3bYVdP
htM+8xZBtc+6G0ISRyzxSPN1a8VnoJGIF0k2VbMruLnM7vbhCIe1AFok7QrLfgXntBVxMwwhIrUV
5mnuC0C5vSeZNSwQSu2+UXkTSNphnQUtYDBjTApUoJ22zf4Wl6SGDQu9t0wjUcaHBCdmuapTdM2R
UD1z8qmR8ycrT8WG3S5r9eVLXFZ71yulVzAuQq5VN5ROti38lAwxAZL0tAXZFiPFZVSUHQmGGRgU
pfPD9zGbC4OIFDsSXG9LqWQBZNk5c2sZCmfCP+kb76MWcfZX+Gsis1rNCo3fbZeGcNKXg4VMERcz
GWkUyrQsi9Kry0rfZHH/8Ldply5xQF1+G29cnSBzV/cOOJjBdHMRN1+YwZK8FtJMAvE79rHYJq84
IgisJS6nyP67zypRJFZSQ9uZtznIQB+2Y3WQrT0cRss4ekhBq/EvGsYYpA5LxBZukHBpDam1GvaV
VdM8dq1atu+iPDKAdxqCj75GiagJhV3RC3KxZVfJ3BPZAcZdfTpXIhgXi0g6aRdQ2nqeg0wSru4i
uF8KrRlDVxtt7z/E11VqA/tQrx+dtagVc1xoEGKCx3vB285ovBb5EP/cZ7yBgCh2xjBFbE5MVSPp
V54rWM0WDXZxoWD6duXAT2Fokm9XVWJFIYynmqNk5cwlPklEmL1Rd7wjvIgzTXhdhQ3PxajepEpA
B8SZ5v6sZouvKjWZaUaaWu2qDLGNUeNYqcA4jedN7vuWdgVrm6wvkx4TrT4c2I2gepS724zlIqX2
oPfHNDuvtY0reixxNKSOEQQx4wt90fWI/2q73HQZIlv2UHBHPY3ZNPaoMIgIt71nUyDxgU39zt1g
R9rsEZnT4CXLVyIYk9LLzmNTyiq0te7H7t4ToDXQGVeoCxlJYUnj3YjFej2YnFbena7cTVH0qDkL
pIbqX2f5Rm5bg3USZFBfEnSw5wGJGfHbDMI1RUghmWlpQyFBdVc2ZJVttUNGQ2PZgRTqE/v9PknV
NzmdX8HIxw+givZjaXt7qXFqMw/9Yl7n1dsc/tw/2vtGJhJpNPkLQHtebxjmtZQPybb374WmsQ8G
AwlPEMfuzuTMRPMVwdzz/GJLt4lzzSvW6ZAVDwLgS4eXnCB3V5vvkhGu8EwBijNlm4gm9fiJRxQD
3o4caTkI+jLsmxnjpvdXA8PAkVxKurear3CJf5H+58VEz5kw3HVlT/mj5D/a6JIOC07x4cZT/GC1
tRIOjK/IeO+seQYoRLX9fvKrfUy1y1dwoF5eszCXHcrf9UDNmYUP7RXe29TrWXcExyBSrSCO6r66
JSlYuLkBeY/J0tdWKdsPg54VlL9UvJc2G2YIUjVdzgiKeT+fV74lgrXRhd8ubNd1qgN2zrNUZYG0
OgRFldxn83H+6Yi0LII3atJ+DORr9SPLSrVu6PZeBOSkI1dYGl/R0vk5r5odovl2rZWbgzwPzvWe
G1jon6xhQXYQKOpUanCk0otdtqbg5NVqC5klktsrz9Uuy+msnNpnXcUwfJeuJ9GoLl9j5YpHEemm
9BCnrWPWiToBcUG8kUNscPjWxj1eX/jt3A5ueEqJO9OzADsCiTJOI0CM2nlw1UC71eAjdsKV8cWH
vuaHuxH9WjH++/Ocp9Cst9K2epplmDfX7qMZe79j8sr7SI1zsjB0H+uuPXrYqf6aSwSy+I9gRc77
K8zeFNymVSmToeLMtp9J70Ouc+P6GmMmKpYyrI3GWPWkVJJaNM+T6Z1Q8dejGWx5YKHavZ4c02Lq
9MOJtVTBR8MEpy6HYgBzs76Wy4KPYFVSE37oQMkPjyJZWY9uEwHNd2TPaV+u9f90nY3RYIBG1Sj7
6eA9FHKhyAdSELOWZIlNQkekHVYv/zK2rWk0miC8SpMC8o9FuZSwt3ArCrJRrzDkunVXRXIQ32Dw
jbea/Lqf4MotHiQ+qQ+P+XvKKBcl2bKwM62IUvTFlwHPN1WYxH7JdaH8vs7mlzCm3xXTo0rj3esQ
wwt0O4Z8ZwLRtmAf3+p0B9WwNUjJq+/BPYOX76TQXuYjZ8GO6EUt6y7v48Yob6fB7F0qoeXo8ZIe
rEQtD9wbu9pW8qVgr8ROmnvL++t9qNUASZaxR9ElgKHPOE0ph651jdRmdpRUj3aPiothsEsqz5cP
yLeRY/16j4NvFNwNYhSEQBCJTKRNBdsMqGdyIAVdpkjm47uK+vn4Rkr/4rELxVb8SZ159VGjf0Hp
FJVZpf5+/cTFjZP13OMR2zU+OtwuJ8DOdTcSPcX0QWmo9kAgKsYEHO0k1ZjMJ/fCw8br3/kBOFV1
+LTHYOvFig7gXCAZDYEsEwbtu9BUcmXPDqunQeeTxO0DOuYebhjMO4nLoa125UU73t+7k6LgeysN
i3FL+v0GBeVG02FtJqQnqDEkxwJk53tbxdC4/AsEGhMfoxz+H2QaTStKPajRMSEVdRm3T8jPRaiO
amRDMKSfS/E2cWEcqCGuhqPQmUTyzk1xVRA/b0+QpWE+iBsNdz23UXmatyla57sUkmEBVIIiMEXL
zQ8f2uQWUbVUxsG2wD8+9c4F2j3FYZCa8KCuVCr6Nsmgkxm5zICB34qXsKVhZ9Wen928ARofs4p5
0lI8vf9gd3BhELHKXz94TyoaMKrIaYyF8gwhd99pi4NFXfmc+IjPUuvzFh7jCAqdkOnTSTJ7GnGR
1+4c0x8Y72Scq8VHgy8kR4Lc6j2b4LMQqfZHocyqg6vwRqXj4ozX5Parx9lkLEoKn4LZ0mVJ8lAi
2xSu7OsdwXA42j/RYyVG7ZuH7jrTcibEUAKUDJD4knPu8IaC1R7VZsqsjN3cyB8L9IjzarQ/uJWV
9pBd4BZ9KxPa6hJcNq/BjH6pQ5bG6iy9Yu1IXilPfoemDF4XBgXeEwA7z8F3R+IvcOO0LLAPcqh1
wnLIEZPNq2oTxbyJ5JUzHF8GR0ECrkF2qtLYiZR2neInPx/SbuuHaCvc/f+mcJXoSJwo/iUvjO6W
6qwmWdrDvgEivQFqzYtQhbbVxOvDEIDMcVoUQftnQn/q7mguaEI0vl/cGAxr6tFOJNgC8my32DPy
UwZtQsGKIWk4+vpBvx5ZlPKCcW7mLWh9bD7WGr7H1hxqHSLYoU9rA79S2Fth1rwBeS6qwZjti5sI
jwXECBNwvCte30vvLGnZG2xfPM/ItdMFw1Lmjpe0IcpuNd6uG57CzJop/hHNDidoqeL7GFA8JzOq
Z0gErxNTIr6tKJRHTAa9gsP+rGnSdxkR+EGKd7oPN7+mRFpFQCCb7mWgyNBofCBkVP2WtcBztLpW
+in5iaoffAHP5oM6SNdmYhTRO5y0e3V0dKFrB1xL/zPU+doO9Mm11aLqkrklWrl+31SpDccvI2q1
2IZx0qLmsuOPHFV1d1ta5VdhFpI6OlrwlbzFTVzLSKxnxHng/cX9V9QMsy7i4nwORtGiBWm8nJge
vkyVtJtsWpciuzn7teuTwst3z1XhXPeaw8EyKQuBAHGQ3DeVlPrc2tHsbPMFBIA78B6Xpy4Is1C4
ssIg1fj73ouninVFaUhFmGbfuSp4xhYpIMKPHOFCFULfT9edlmnbiD4ZthABT7+8HZjdiwSfIUK2
heJ8Fc6LpDthJ1d3WJvJKtEPhAVSdgCWTr/X5zHAdTff4glr5t/k21ZdM+t0bIqqmCxEWCCkt57b
09ItYLjgO7UKgtda25bNHfrui359oXhU+JCWbmk6NjL57XO3vKp5R7d9osOW5KlrVBC5WfFERvkX
Mt6MvkG5zXmx8dPeXXj4+A9/OD/Dn4VNqSxv1NT/PQakpiTFF3ZCfZWKSthCGDghNH91Tt4Solsl
Z02ujazFrSlU2a7N/jINlo3zIk+o4sdHDrrxVIc7Bur85LaEPlL+Gh2BNGPdGRPNkVr5oMFbG0Bo
8gyNh7HTsMi/i4rAKx446J2T8PqvstmkcxRWlWeeUVnJHJsw+n3CQQDkuyjTlZOc9twfwcFI7qpd
ElPkrkGA3Z73/8wzBc2SuQKVFKaKi9PTPULHv+Wv4H5/e6zgIpcjAEpZ+Ras7WcYL9QmjSqSanBj
dmu3CwoaxVUsqR+VVYU6Z/3jCQWa4Qd9p7FzftfWcWP7fP0rmOFeB473FiUJCb4NsIW8P8+RI7JH
8DcnoMUuidOX2/vKCkYorQnvMxEKSVpHx2Ziu/7RCS+awskaIyt5rKX+YkGhKDM6PE4g3Hy2pz9S
LSJF4xWlM8D1jW9o/5eN70H699hliEcin4xSv8Y0kS2jvuYyf4H08qsmaDnJy3OX5/dPCvpSkcNw
+IX0FAJGUPACqZGGKiMxlt5qeVR4yR06S2rIeGDumXnW7crqU1CTnUdCoctonTKkjZHRhEiYD/yl
RZeMHATt3aENOPqGIl1BwAIpY1RAuvsNWIONBV3tKSlsqJc2chXgfwm2KMAAOs/9cNizY1GVjPAu
9QIWupwUfc7VNBJOnG3iMrg27D+VCfAWKdhQuYuMxUK4y4dpSxOY2na5+GB2r68WuIaNWTw0G6E1
uIOcVayxyi8XjiTxisnE4Q3D3q7Z6KnYnmswxO1fO3QLq051mWb/AlIwDSN2V1rs3oob1LSSWfGV
Lh7ecYeSxOLI4HQ+sVd3n+37dW5szO+xbXyoO09MVwbBIyc9SgYDviiZIjJw1Xp+HHY+9QMkttwo
KO4Hkg5zlz+L1bJ6SGFXT3YxHz0M6HKjAU2RCRVnPGbSVZbx3JypoU2MaYeGhcB2ycg8DDr9sGyl
cgS4b+j8sFgu4aUx9miOLHaO5+c+OFtz5snRnTEIzX7sGSbzyxseYCCzUFvgTEgobG0flDQlCUul
tzo/Z/JHjyb+UMPsEufx7I9f4pNP7V4ngtoC+wOlaziyYDYr0DxJ16FhhxMMPNYWuLH3dOe7CImY
OjRtI/xvito5Sz9D9rcVGlQnPtb1fHSV/B+DYoY6SHJDlX+ggkhoxSvoVbnvrhLoJ/t+wc8qm+K/
CF4FDp/6ZRD0bRJiAc6rRlLQzfguC1mggVjALZ/3d/YXmHvcAnUNHChieF9oY8YD+jIlDM0QBzRv
Pmg6X41b3zGyLs979D7VRLDNOLabmIOfJwwTSpfSeJ4ijhROU9LfDVJtbBqbzVJD4v1HgYg2fE+n
dZ3lACp0KhDODFcxnpWKbEmYD8uByD0bHkx7pcahlmKGRlVBla0zWPBXwEc7J/L0wTLbr85vPD/b
z9SGMNOGCQQXfc+m0Fgnsy0+22s4Oth4ZJhNOuiep+1pPdsCcQLVWzTwTwjeCxLTWXBtnmi2xbRy
O4czGM8I4d6KKzLnb7omT1+CHuo3UDWm6OJs/nXNdA1yqNqo72180N8SLPQaBhkeN3nf/yQaAYI8
AQva8X1L4B9ighMnEqu0FxaQ3UoVbqSA+YavzFbweMiub9yVte93uoa2dCDELsPws3dYPoOvI89G
9jOnE8ezxcqMeLKcNWKZ5ycrsLIWV+MzIob0a8JoMGE+2z+WZIqqyw2A/CoNVyS8Bb4GTZlU0igL
wIpIYOTihdET2Wf8zZtDCDog5MQBm34TAyyfD12MIXFfcsJVrQgJbS45dp5p7Yx7kojrtt97OOdv
tlZf4g+qjlu7Dbgf7APUVwoEVhbetQ7OPD6V3zk4+YebX6qFhPk6SNLEKdJASOp1AngTOqPcOsMJ
KJAyJFqCEUsb+gHneQqe5s2P4ZZK0zOxjlgnMtdy7kvQh14IDYLR80N6E6SVUm97fJwCE8wnHwPl
U2GAiRLIxAZ1FMwH6u5fQyobJdcWjLP+7woEp8tRpEzEe+TJzzBHyWoK+D9mrDBGVOMe50Of3qv0
7jyc8rkX8vGhPAbmOHMnwmRP+EeICBhNWc681bnXokCp5G2Hdnjg+u5Y4HPgF4ckLZ0xMy/rIaBx
648KgmBPQ16rM3OgsjEYKDapFVeUmrbNRt9Z8QmgHcm6EOxNd8MeBLMwpHk/ApSPjoqvnam1IaOA
FAASYL4bImlT4zkES4TVTbn1OJiLUc0ce4dyVviq9ScuV6n6I1K9Qn3xSlRzq0sDXvJ4FWXSHGjN
4bOXJ5usByI581E1wuKZSIwXAMV+VKvcCw0TquxI+288R7FQx/LPBiOJjCrOTsqgE7jIq/7wEiZH
ZZA3mUwtRuyU0FsV29FFOcjj+fgMG/eAx6EwxG1x1QrZ+lVZk3K3ITY+onEcj55H1KsxuhHpoVUD
7i8VO0gKLNNL9sWmNoArgZRo342PyyAMzKPc8pcORv6G4bhBR+CbOdoyQPgVQcJMtFzyUTgRlZS2
lIB/7cRfZtkr4FOsowjFlij2E3pxEDF6EJObK+uTAs6gLY6QUdVkqhMxy0HbSjL5cmE6QQnkP7IJ
6q88i9ajg/EPkkeI8LD0fbifzncLsvdbn32/OTLtNKtGGXru5Vo6DC8oiGw40HtTrgUw2CZ4tn8P
27CwXZVVY6gtZDypvVle6JiNjGJrK73HheHJiQEti4H9gTBwqMPimvgjcf2/Qau++wSXLBssN1Yp
A1DdN/ZKhl/ErWW04xgESu3whUWLLljLar7lt3SD+dXzTtNb4B6NQmXreKfLYeHHoo/6M7eFROm4
u27zwoAfh/XQaeaoU1K3yaI45Z09zKikNs0g3jtRVI6L3K5iLnquG3Z9OYC02rSj5F6s7bGmefrh
mUpaE2flJLDLmB+D77s3Avu/3MiaovLDaCF7886NygioUG5i0wo/GehPQK1WvB9oeKVfSj3lGKIK
b0oi4fFTnTbLX5BoAC4YWobRDum4eIxH0pAXpMgNanJmyCALi/scgw3PC2rdY2e0ck3g6kptOojZ
WZk+cURY4OR9eEc3HcNPAbLiusjuezkSLbCEAOwYeLUKvW/aavGoiDB7npOyjuaQy2+8ZhqwTRNW
M9GcwDQnM4706LMU+CrAa/3tm1gPueJqf/eRfYyw/G+3nlu4U4Y21/HBP1Y/fnZeSPljybQXptli
ViGAirEDVL3hoEUDZVk+EPIGgqNb4YxbwsDBO3fJI3ho0F42UD+osr1cFIqdwCR6zYECa0ypJE7l
8QriJMXRF+e71PV3yAS5zuI9usI7x7gXbcQdega1gA+lskzgoUvToiGosuDj8gh+/2VyXpAvVwT1
mmF5oxKX5fUn+W0KfEe3jnaUgnBP8Abj/eoGt/IRw6svLU0pg1bDLGj+GCY/1xVt9d2mmnug5FSv
d5si4fWGU7+dyy5pohpicYRteo7CFO77Z0aNu1F0dCGm9qt1Crc2I93Jm3haipIAiGPeDoN5v3Eu
cqJiHlHsIQb+uer3Py8mxUNjMZq02nCH11w+AMEq0+17G7LYXZy28Z6Ss56Bwjxk6wA7XIh7ZKcY
owS5g1KuCIC1HBtG4LLZ2w6+CpEo1lO1ZwZBGIctX5zZBRTPbOk/X0QzIPC6jgL4nHYbTrmCoOss
EvvRYS+IQrv9TnzqBu9OHUvxdx/h1JDqPSrilQipRRCRxh3LWiOk8l2yab4Zo2DYj15ywJj7l0w1
wJRprj5riXo86TyCv/Q+8OqRWy4Skx6gNIn7x3kptaCdVQ9fQUDdCn8KSPh+vuwtCQgYRLyWeHat
4lowzRJPeckmftLZr9qvV9CaIOnd5QHo3XaJH8mjuWPD8c9m7ZJW7PojhWTjnE9QdfA+f/KQ2T9s
SHJfwZ7WL0IheMCy7gsqCCYyAc6Kk3EQmgEXklbwJ7dK4N1prZYWBspv7Ldd8pNJl07qQpNlGw2E
MtbCUBcTX2jjLtASWBWVUfIY9ARwtMqVGdGSeKYo9Q6viMmtGA5Vet76BySfXkG3wLtCulSst/IU
vaU6rzFE9WO/Yih5JrVUDw+9L7qfgZUGrqLaM5Dt5+18ayoR3fm98uj9Y+LS7UM8qvRsBEuimAvs
Up5yy26iFZSI4t9FG3YGCjqH0OPfe2YURTBdYlgCnEHtlojUjXtredpHhJSDvjNT4oUEsnko+kyL
PfqUaOBZfiVVmB7k9PmkJ1vS56nFPisrlcoB/SETc2Zc0/uvV+kfKMDM4BDr4y3QHd4HXizK4Gz4
xq1Nql3bql5Smqwytv2OTJZAJ0SdAPyHLE6YN3LS5hXCMlfszoqeucy8xC+UaniVPTVLKQFTcBg9
KSSLjHdW/aQyfa2fDxDdMWuqYoRm6zTpNLXf9VsCmpdgDPgo+BIK89YWIHqige+OrvEltOqZzhYS
b5nXVbxHkNmSQGdDYEXtrrGpeE0Mamg1hel28iYnKPl70hoSUQmINeLxKCa32b2eoYm9MWDvbWyH
bJqNkUJmCK5y47ZCZMibwTR8hNsHdfupAt6OaJqgiQ2kuIcIH0kr0vDR2bbJU2zDKB772u8F8ZZ1
jMNesMdCokiP/hRGUVUS1uZQ1t4WVw/24TxtYjukhqBAPEsOM902OVBmTL1Afew5qHP3iu+lgIDp
7lWyra0UHkcEmzwPbJ8fOXI+IGPHH0OFrx7016/Od4BxCPs6UzKooBfqGiYnhI4JpV2+pQ+yZZvu
Ny2GLf8gsim/z9jKH2rWFaezZCyqvV+Sv1s3piXwfnHIjDqwE86kHJPatIxoe7JNqq3SpdZFN1vY
UEZqZOqCzSVEfjMR8ReJ8X4ZfRAxdnigpALdxrDXJJMTR35ykNNfM3DQcrUPE8VoQuPyN38HDXQg
Uc8wJGWeweZLfRkh7wG2+iVWFpjCOfsTBLsjoBRlpcZ7Egcptk5nXl9peeHrc1v98+D6x6rTO6dY
xYBT/vFi1/GLX60+35ZOtcZvRwWFvBNj+86+vYqhvv2O0+KFJFeTEp6VQ1PPju1Ojyrl8E2QCXiI
dUTZHdco7x1oiT4CP79AOXxG9JuJxsBlnnxL3YJf57ahLAvLe3Vg4Y/FFx5pToIR22hJ6UJ4CpZl
xQOadkn1VmAbiLTHyDUtjNHOmK++6XOCo4eeJgZSDk7eT91mI4pcUx6X164ipfBp+0EU9a65lsGr
67Su71FAxqbhUfBth23EuiyV87Fa2rcHvLzeflEjsy617nMXfg2PI6KVx/hgGbCTFPMug4FDK5up
CpFF6vCKrECPVPhAU2AYve23PvxR6MyOK85tyUEAVJaRkupA+gvUWyeOa8u/qcTTmzG8RWd5w6qz
OfK+8J/cuKFnyWblCQiUogfh+WNSrYveYhzSqDGaWD9zUO+hMjLL49jS4Z8WLAFOgRaHFY05FE5W
YnCICTYJ3fzUpKHQlilSQ2cpOEaDHB9psQM7yuYYqdJOm/q4gP2177Kc7y+mzP+rXxJrhNNeCd0t
a7G+J5eAjVo5qwKpyuVwwwLA+ORH+eni00QlgizsDsnMEBWkbGiGtptp5FnC4U8zF6rtJGsZxbla
sc+pFO1Jm9AuG2Llm/00AfiO0Y7/0/qIf3eNQY3H0gbvnVoqBsdn+rMm94X8YwpaO+4LGuVKPbFp
8DIsAOWDc/gS/ZP+D8i+IHsr1ez8WAz3mmNg7pRiQksQiFoQXTWe8iC1BECXpA6hC3JV+fzCBsEP
wQll5OcMZi4sXZhep4OnRtYRDvdsiO1TzM3bifPdHv22ALdqHaL0gG6HY3HLQ1HNTO1SlRKX+CRb
ugHfxpEbpNENeINM1EhTnK6BqIHGjq20BJqaWx3EBN7LdRhjHCGcIjaZYcsBvBDQY3M/Cv3/kqzR
gtThoJPoLJeFRxgtcraEN0ep/D9YrLXqpy6nCSYWl2Pp9/pgelLmXNP3SuBD+SosdguFXT4i1DXt
YQ4p21zkDmE4P5NGz0d4C8dx83Mx1QErOAanXSXNFmdegBQXwuwXZbUGEwLzORNsXmEw6DYNxGQw
PO9eaun0LSxXsodzkuIJ/d7ztGseA2YXUaSIjIr81i5MLZArxibg7TcMLe6cfTPDlElB6FCZi/XN
sqvFm5rmLSpyHQ84StI/uc4CXPyEfIL4ErJ9tSQCVhd5iWDsetujbZTf6RoD0LNBcFBGZi40hFRb
PZ+4NsZXoQFi4hjHnZRdDTaPU+BQrlm19c0iK2nITgC0zrJAbkHMXBm83MCgOdaj1LMXOtt21fU9
1e4efVdPqD2d3u8eNfzqOmmiy+MT7gfHkYyIrK5dcMJ+YCKF5WpjAr/pA3qqGDaFbkolgMXnb+kh
GTsjph4w4g6ZX++8tGheH5gAchMnzuxLVWQLngzXqyneJ66w86R2qPw5zc0ivPUemM2zSg9epK09
XA04v1TjDeVDeSyAAh+NFEIZTnVxKppsVUUERcK30XizxQaHZ0VFrf6C4fT2DRrbOF5FmPo4YuXU
Br6yDaiiGTfqe9ry0MgQ8NwOGVOre/wYKstYGQZo7u5PzTWTj+PH3cKR3YZ3ggoVjlg1q9yUZPo4
UtvfINdqNN1fVsX3iITD1PbwemIGdCLjhjsXLuSX9NgLG4/tR8rVaQnaeVu5B2HxGP1nwoMKRZ97
T2kj1TfxM6t15VwRvGqht4uFGbYoIoju8RbqWZh0RZX6hdI4mKRRxZEhtXgCbVhYKzMRvSB2aoYL
t4FB21rJ9uJR+6aRmorfPJMIvIBT9alJxrJ7FsaJmIPdq7o/p4SImyGNQcwjSVRfS60sYu537tTg
eq+jm20v78wZGDsBEwTs1lKvoxxkxqKmhlTwZcrYdVSjNuN0aTFQzohQjSmNLL62c22P5GYB0qqB
k9eusynqK+uPOn+YePE8u6A8wajrJ63D00nrf221ZRnnb6KV9DG08qOpnmxj/bqUHbwKm0x6Nxdx
lDIXS/Omw72BvgFTbpHpso8xQhT7+ZpGDJarDlJfsejhBvwiw9ZR4DqRSOPuiSw5jH0oTqSDhdkt
loGZCSDNPt9vulQTCV979IckM7d3S68APb48S3A7ubU+4kYSEX6SxdpaThgmu+jna0vTFV/WlHpn
nRoNSxzFNtSQMQDxFgcsvX/Zia3hN2uIZKrpricWw0kOoUp806KS2okaecKuz56bvY4f8bcUGBjE
3rlDffIhgxga8JxOZqT/pwoSEkNQgOK904d+zvlx7tmsNfpiO5kgCTbyVxcqQktyNMm/dpO7+8jj
AdUZ7UXWfWCe2afEY2+cqL4qY4ji1R4IV0WG/RKv/68o27qqPb6DbMUTEkX32yFbYhCwtYLce8Wg
lRwp36eh/I1DqPC8p/pxetgZR1FRD9Ls/qwsQ3dTbMSybSpNhtQ1bpwt+nQzt6bpMlHyKkZiytVT
D0aqyKBB+SGMywHp3u3MW/Ai6Bymt1cT7OlQ2uggeBGfvLX9yIpP5mqCgUz4Q/D6g0RuiuCf57cb
jTuj4bpirf9Uuplg25K+ZO9/1TKd0TNM04Q54/eeFkqx34FwZAaFJ7Z2ACOGwvhu0xE5NyjDGKmm
Hfyz5PIIjdFGxAGfO96MIi/wemlusSPmglWfRMhuTsqetz7v1Aq7EQpL9OJ8tGdInQ3JfOYniVnI
7ktrM8K8FmBRCcihFnHf6BB1X/+849MKZWDDkdqwVRUD8WmJ8Mej9ijCGbQLAqhf08fycfkmW/cO
tMcoxkutLa7s+/fw/57k/fbBIGv/CkxIGzL5g8QieCwKamCGR/6d6U0BhyFM+NwcV+yhzgI060Sk
1VOifvg59JSFRgDnvpgbzluJ1+ITzpPycFKWKzvtnKzIdf4LN4M02PzL7xTgl2xLgMq57FUi6nxK
zOdoqvP5ohGRm1Ds02elWps08GDVkD2LJHXbnXao+hyRpPSCTpLLGSl8sQ+rgAyLUkvSXDsIrzWO
2pQl8S60kC8fucdoB2VS4bS57o2wOYRg+Le7kjrt9c8mw2I4uvuN1D1e75jjPDJUnN/OzYT/fDnf
kb4XaboFwk2eb9FCSizX02egheDoz+56YnlBP9YMuujW8JUkC40JfHlyDZ8EvP/t8XOwHiuEViCE
RKBpAxB8l/FTAOWNBEefofnqRTFOMhkrVhRr1zn0BfyxzrgINdTfnRQpmYvzO0RMb1w4Oyv0Mwa4
SBt291h/kWwk0o/gWunzNCAzna+R5vV3Sk3F/0PGrr/gTXm1nh8EEnVfgBzSgRt12uz+7kSlgQ4e
88La3Ob3XmaVNhCG428MCyP/LG/GxGIQ+Fpc3l4+qprGhXHqCNAxtJ77xQQzirAq7y4THvcoqqlE
pUHwgy7TfJZsJyGAiOMQv/3pS+BzjxdenJ25UzxapCLPaKNHKYokPM4XpucbnsjTihNuETjy8VaP
enf8ZCcrInL8EwwgrYkqP1vnLuUkhvzqD1HYC/QZE2wa0v0OTgKsHfNZ7hhEQCAQ1shlWULdedB4
OvWInsZetd8r3zxhxpFEjpgvK3bLe9yT9SSfOpawoRz2Ce41fgFIMGdo1oZdZSckToA9UOKfcqS3
dKvuyRZYHfkDPNBR0rbl/vsfIBZWCLUi48D01P2cylWil5C24qdZQSQLCSMVKRGK2w0jNveGmjLJ
Au6mBoeoCNdGysql4iO4esIBhCN6adgcXHwRL0gkyBPUTR06FR2Y49426uVhyC09CUe3zvUvN5TO
q0dOydRlRTO6d+fiHN8GwkxU0Q53Skrha/8MBtK0nKc+mU27xidRj0qi+zqdEDPNHsTKg8HNBLoX
QFZEG+0DYiQDe5P/EmCQPCew/Yqoy9HKUWkMI9Q2771/3tRos+8JaIQ9cuN8m3x9nT68CYd1mQuQ
X7gFFqC4RSFyh1VOlzhR6GcdsMKePjMiPgz7W/hVJclrpAAtk5z/hi+JqcLp9NSwIu0tvxhgyTA5
6ctJsKMs6jetdTqIkklSJm9C7cOYDdSVuFH6ERDAx0wWhtt3X0u7Y5qffsXxHtlRiX6m7lS9+Wc2
6fDjfb5j7GzOLCjizdrIeiMgjxgtj2aONDgymP6G2P7TLLeqIzO+d7IHTbqH05ygoYZfJciFBnyz
Pj9AR2O3IDHYWVCupDms72RkDi364vm+to+6FNlZNxKJb/6DhMJl+J6n7Q6zM9ctDjlDP+Lc6EK9
3tWfA7HjdIGNo8GkN6s/hw03oymiWmP/LsxhYIwmtS/sGOcAVRVSIBkkaxAjzzYHVP3lAeaJZvIA
+d4UEwfvs9vF3xfEw8Kj+ldSkTlRtrEfjftAlUfeqR54NjToIrPt+yEooCyRzRMIJoe7DLJZnHH8
pIaZTs1undvuw+XOVdf5CzYZhT5fFCAhAo7VSjys6DoKt8omQ1OlMvHbkW9/JanaamsWz5zP2xgM
vMV1/1MQrXAK3lRa2ImhFPwX73S0OkMg0sjiVxjSBR+4VU0BURYbuLOMWN57NU3CQw0zjQhfldQS
RddihCvTFWuNQExVSyZtRGWt2oiVFFE7dKCzZD+qe2FYFOZ3EhVE2lM+Z+Xdq6+qXVx6AswgSZ4O
erIlko6+tpU0sHTbNTt1LM355Pp4ylOm1tIOQY4pSFtRohsWDaJxS3TzbmwL80SvWOKX9CH8hnVU
QVaEa3Q5vDaOdYRsX9E6VNxict1SUi5DtoH+0W5rce6uDhIlA86scBJOF6zejUpG2zpCeKYpdCVd
t4aTL8IQ4LB4z5jlh7ubspR9skEBTAtbWNnW9BVaNS4XAYNt0P11VoE9Gd7i3IkeubpLsayOWvKG
dkJdPyvA9DYpHqFh4YCadf4w2IJJm6HTuhPgBDrmSM54A6k9yiFUXinLJZpSDJ6oJ1t5k07fHRwX
bDOzMRypifC0N8wQtN5Hi1E7lS+bR6u3H3lnODPm9anPat/p6wjm64e3oJKESsIgwPNarxrhkrqj
u4/v64Uul4n4fLlNhxMkYIAmC7FOsZveQ1ZGZVDSftISHD4FYghT17aMfQbwWVa6b6JGBgvTnnYT
Hnua/QLBRw2gSSzOQB4CQc9uH9ZQZd5IAiUsmB41OTM5rtzt6IizwlwB6H9bKlxUevBhRoUO3vpR
MBokiejrz+QXcEo78SU/xlzQ5HcHkh5RjkBLVY/aPMsHt3tU4PfaDkQxZoC/yhuyr9SSCQIc9PYM
/1l7AMDPjZRoq+ENyo/4sjHdNh6wouADH4NjEwvXJ+YgLQUIGhQ6nnxaG1ah2j/+az2hoEH1X+KD
LoxYe/wo6rBiMxKQ1XwqHM03tKPVHTFyVZinPCNHhcP0wmcLat5JwJMT1XqApStS43AOBBGZ0zrs
j5MVMigowljAggYebuLF47sOTcDr5bOZKYFy0NO/y+GRf35Q+oLWEucyI0oEFgYRxbOYFxh4Qi7E
xHQKM1PmJOPt0uCWOFTQswooV/wyPtGqIvhYLypW45DWtXpNGsyo2hLIWzqEgXhJlVHCcITKzmSk
pLUsCPkeb1SnTIL++WVFJWSEWOnPbdfFoxISqkjO6EtxNDDqRMYR1+iB21XwM/up/zZ+qyZQ/tuC
8h+Bb4gpo9qDR/PBlBWELBX9WA1Yf5YIMlPVWG49/ga4bcbJmAw38Gzr+nDGcKLnkiMwCQprWGP0
Afb/WOVTeNWqrZz6YPBCE+mYBbt/LL1i8nLtVladzbwlhUo1EoaeAjJahf2kBGjc00DqxwZgHY6N
2CEGd9onUJNjuODYnJvBhqtCH9bfgHIF+shPFAY4/J9uDWCTGj42xMnY3S4UEwgBW2NIK/D2A1ag
uNIpNzTJU62pnqri+Gn7mfeqw8m9TbPa8Y4siDwdvrhiJ+BYbzCOoKBadg+sb0LtH1R5qXpztKxw
BuTTHVnk/m15BqUUdxvVYW7k23CoFnprRTLGni/OnDPernc8YjNzHEkn/IP6QqlwJE8Az+d8988H
L1mx2/ptZbFvF7NgcACD+F9sLXqnIvsrE5rGp4Zrgg86/2Vr209p301LNMGjuKQTnuVSoXuLgLQH
EXzsJXNa0Asu/LshwwKSprWbt4kmDmg7Eu718Btu84dPgkkmkUhm6Q1y9rQJC2cnD35l+oyius94
F4awMphKnNEHes+3XVx5KfDVOrrml/cd2CGw/KuvON3OpN+YVQbeQ1xzZcpQ1YCqU5IKJYEDRgtw
+UHMRGe0LNM8l9ZA3jIXT1ymGKOYmmNPMe43FjO0dz5vbM3BARg8VAofRh2Tj44SW6nBK769ODa3
SrBh81ahDT35/z+SvLIyhKvOsVdShK0uQW4MFIvNxvQyZ/EBit5A0GtX9M0euc3b5ROxZYN6bzIS
B4/ogFFkK0iTDTSvRu5kAAQo4QQE+QafFPa3d+LhjlDU69+BwE2UW7oxbo5FsiSygMUheda75uS+
I7ZwZeEYRxM5dR2hsTYo6tEDezakfwuwOWwt6MRx5osNw/O6e5b9x0vrn+aR7EkfRIsNp4KRj++6
3kkefvjIEo7i/hxkuVLUTCXHIVlu/FzArJ0ud6Hl6/wybF905KRuwZ0ps78CKHmd/GCJ6DRCbmR1
q4xtjq7q/68x6NW3+49gPRftCzH9U9/t1SBgnzeT6OH33aH7/Xr2BkMfIPRuMkwDsUhmZJ4eOcjK
YC39AU8xVyV0JsKS3pgBLvqCn//RtM6gbNEpCafyF/CrKSUVJC5vP6l4x7h6bDn1SChvAVxUP99U
XXyr01DwXPx4RaYnL/s/gFdpa/ERr6TcaLC3Ms+NVh80U7z6s9Ngz/6ze+i8yV686SyGVEILzVYN
FDQ3dPhJWkfb0YOF8/uKL2RHBOFyMqcOIyZhVibOQ6omeVLiognt7wVEf7ASyE9wHaTjeLEr8sn1
ekYVZjoVPESIZCtiMUZnPfrNNy14Kcxr2nR97le9m2dTfDXnEuuxARcesn7/RCdMJnytYMXxtJKv
hvY94ly+LncfddbCSrl11Trl34umfHeYI3iCYxo5kYrgu1XuqsknOiOjxG96Fu5qcB4EFxjNuj7d
DVHHBC+93yPouqqkeNaIV6bEnF5XABKy5X9x7+uNL04S8zxIXgGRe2b5AdtBYhm42iIohU7rSyXm
qBvaAB7D/ddLHBoNwTyoeXJhlvKSiYa86nGNsk6sT4lC9/94QMECFWDdnhH4sSuC0rfiSGkIY3wS
UrPnz8Bj2e0YY9rMcnx1M4gV4Oz3preh1RV948QfY6smc6PyeRiRBUw44pNYBq5U/0h8zYJPquce
4uWoJ8Sv4fE0oY73hXfyGCIMa/Xc7rwYqmKoZS1HaZ9niMAuRu6cg3DWUI8A5rDQLw4iHhq0/Sba
JDu0e+b0VBNGZyHe5QXkSmmDFawczscRGwx3S9hPfSBUbZ9vDZZv+OnDAxxkkjq6qDukFK4XLAp6
4D3gL3wqf3qDHGx/JY3oEYCxpXy1oOegk9qdteSZcZcSFN24rkhdxbneSBbXKdDncfAaMDz53+sw
o4KLre61lxdYs+dHXsezY6hbNtRque/rybGmU/vsdRAgH95T6vbeekmAkUcIF0gekykyYEsMc1VS
FmioUDDEdAJS3b3HAOxV6AD+nmyL/GdfHRHdIUtEAl1JCZGL0DRkVgxyXfAORYDtxwmqZ+GSUbnj
o/IhKhWR7upe2pEC3CJ26G0glSSqsJlii5KIeTcBmih+hwnTsm3UpgbawL6D6f/BVXPl4I/NVroi
bB1UtQ8ADw+zE+jigFDiItN2tvZ070DwA8DiacOnISUd0tj8cAup6kHn3GatvxotH3JgiRV9XKiw
qFZze8QZsFeTELgsRTdt+HzOdZQ5ywD4tDPxuT10S6BzuWUjOkuvaZNY3TbMkrEDQUlUVOnRqPNG
SaVr39YrUPTYTpKSF7F5XqYFhc8uv6cEfwrbdEmc0cP2YJfGdGZYn64Z4uQxzeKELauER+iIXXrN
dRa9/rfcqzjR1/sUe6iyFdQrlRUvNF3Qv9C8bTOkABZC4UUh45YQYkCzwW4CkGSTyJtshzWmhHmh
ayUK5WGeF1TeFaZec8eAvqsQuJtzAIDCaRSnMyTfV52YaEEXkftubj07kDxHM6bPtb1v2a7fbpmZ
EkO0EyREf93M7h0cnLoDLMKX4KmXPw88IuYz8XADdCR0vm4IXQ7o1xNJYd8Ar5FJJo9+obv2b0TT
1K/osrM0D2+1rX/K0b6fGvS2LRcpZ3KNJ2iV+lllguz4Bop/9yOb42LW/fWRk6ayU4rjIwb5PXNt
WtJf9NCIsAprK+cbP4EcjRFhRKXOQKdmQSlejevyJbf7DeByilYyxJS/5aHWv8fpWRWp4lQy781a
5lDyu6BJH2RDShJFvuSeLjrMLaYVzo1geYu46uMQvSFrNC0SqDEJIU0SOFy7XIBZxNho2Ucq1W0J
Ef+iBoTQNuGKRHEYqvDx3dMIUJ1pdLdbrIZSUy6uTyf2JkYMbPzjOTvQ91PfsDcw8hNIJfdbjcPz
glBYuglM2r3TSso20/mDIRVY+B8b+lETSAuVQDQPEDiiLvz9tMGyJRcxmFZJR9fAvqLpYqgVmEVI
/+V/HxF9KP/a+zgAyC4A5Duwl7gt/ogrMuBW6C3m3ttvE9BeVxlJWTh9JYO6icQrL7fmRcx20g3c
gOIJZshiDBSmMsMHGIopAoRZBHOax7nUxdiLawvqglosl44WsNNhT1qdlZyjFWrzWhnhKakDmDj8
q/ylxfTxq8enut203nNzH3LC/apd67IYgdRBKBjLqGyKs2WdVCg5qERUfVKKbWap5Qnh2iJM+Wcq
p0sY1HzIkqlGE8PtdaaL9dXcXb+xbzMS15UgaAFUu6pVwTvAFz0Bpoqnyrv4x0vG2mQqyoWFAYxm
1L1lJxxPI1XLNedo4cPCy+KeUNoy59BcktmlQHuxdC/uXAHrK9iAI1iG7e4lkArDdhsezidifVW/
TCaEyVwXjt5r+dgtsMoKWoJ+bdQR+zTpZhRZL7T4zHKLK7mXIgLq0j2F7vZt9VmbS3bHolZmwgBs
60M1WZXYxn0JG5VRfxvYHEZYyZf/yuL9decKNkxWxEnmSTMN36hO5FHi9Y3iy/vg/tFLutRQVz2r
/JdQ+CKRmiIhqX2rfulQOdhCr/7g2IwhCei4eYI8dJxQ/AiXp90Sgx0Z3uzYo1gGSesSJ5RoKsQ1
Na3w9vu3BVuH4VLVIf6BGzru+KJyKdMHNdhDuEPsPQ+RY3lrBPGtt3PsWZ2Fg9M99Ny0nDe90uwP
ODmb0680UCx7XuUNhv4GS/PwxGN1SIIghGHk8799iy3y8Kj73x55DfbOqvlMoTYkVPxe1J89C0sI
TPOX0BbN4y6yCAzQyofGtg4kfdBJVpa2BdzM+6z8Q7ikoBHRRsstasMMDxpIxu/tkTvKtn1xVRNK
KD4lIlRPQeX+QAnyVHynyQllmhQT9KPZ58GZf4KA3t9J0Dd2N+I9qgteGbnDUrj0PB1+Ze5MSD1k
Eg2ZZpMzh6agsIlMDWmoJFSZBYVIqC2Odvky8VVXWebN489oxON4km3Zaa6AhGFEOz+kqyWR9Gzs
Mk/yaDxlcr3HFQNBp8FFFtu+FmFQsDz/QxfhmX9o6r+orgttaL7peUiPqHEvRSg0eYNDgL2BcjHq
MJn5P73MJSmENd72FZ7s8T0Lkt/1aPnl65I7uT+khd5UjXlugSnNl1HIfVIXbqQB+WKJHVbdo1fA
WeDE/I3hsq2xUDnLFX2Z0byBA5lunCca3FcA+Ay5WfvBKoh6+CTkoROoav+8ERkwcemj3sbkcQ6T
QKDWAPE8tdaXDtfmRfIa4LfN3Y0Jm+C0PBMhUtzAoW8wp93gAchXnCCa9WWyGfnXFyJPyfCX87Iy
9hZVkAcSUzPqb/m2HtzRyTxoHm7nINPhfbyJt023+7V5JB1zsUURaSLMPHfcsFHFeiEkKfMArW2s
sjDeH9xV3crVaWvvBAwhMOXVmicFQQ4nsEUipOExnPbv/rqod1X4DcMvoianvfmy7Xwr7kixTogt
3M9ASmPIiaL4T23CpsddzyHuF0ceRGaURsujiSxVM0mBEirMAtfoejfgGObD2IYZXC/5b8yGMT/j
XgRukw1wOkK+yZ2VdsE/CxQCUyPa/KMWkXPwzf7ejs6ooBbHE509YxkmFUCSat6ZkI9A9gX+Y33M
h581VVo0aBAc198pmDXj97CU9jxHEFWqy+28LvMjHwsSx3Pz/GL2i4HSHS0BQU6FoMdxb9LyLWzK
JSOc6EKw0tqz6xjIfvURZMdoGn2E1HLMcoIFrmldKhNjd+Zln38oL5sfYPcDBajupZaYKWN1zJow
9QP+A2OGhPABllnIqlNXDiXYO+zHNeiourwkIqpNXzfPlYRLlsP3MMHvYh9DivdGYTrBrd9cQJOi
DDhja0DfzyJxCctvIsh+2eHNM0GwKDZPf5qLdDPBH0sror1K+Op7M+1PqUSETWRZwEqVDlPIvwwd
rm598CrGpvzzAI2KoIC0ICPDbarcjfOUYjljmbwy+AkPoAvxMboL4cYZK9iHrRi9xY+C3ebJAIpk
X5/6n/Ia0Z/YFv39f7bUvKROVrsXkDrt8DcM3Zm0BBcY/Y/PGQXSP3HmjdisVsQc/e+LqSGZRL1K
XReJmnoozsSr6+LmL8MYiFXF3F5p2iEq+wmb7FR2psuXlrWxmwJBpVLpU/G5Z9OQJMRM9XrA3E0N
Ydi8CVKQPexsSbo/ON2jIx/FOSRuKRD/o2ZXQubURDtB2HL4REmIWQhLc6BjYW1yIews0TxJSmUC
a0tPE8dfZenEPvNJ3ZuuCn01fiq2V8IhohbVmorEdmzPyuIC94neAYBS8llUJFYRclJkCBMMP7NW
PsRxTMg7xesjLz/fs4I6ybNOKyVb+mRCobGrrySRX5CzsVOiETpsucYC/yq40ILIhLhfHB7n7Tcn
OaAKrtnPzh0uM7RVDAFDe1cBTQj8Fq6zfaefzV3Foic4QnfS0cB9ZssU1ehurVXG6k9NlxiXYvWI
pv8JOdEWETEIBnGYgGHoonSdoSX7hlJHrs5yr6YGLGV6Ot8nw7Vj4u7MXfelq9uTWlbtM8aeghPO
SL+/yOICipSZvcUPmSV6D75BGC03AeED60NoD7D/5xmN44ZTNegsKwVU7CVDSDAm9rUTn7XeoLnH
lrAZZOUluhIFQ1GVxlUpYqaLXrHSOeMJ7hYPtWfoIfDt7aJ/xduirY7moz5HPcfD4TTyRLiNrF62
cuieI7s8IgB41Tkwx1Cz/MGtrJFwx+nAe9ixx2dPM+wVc6pzzUM5ZF2oFczUoT2y2HwLhFt8yK/x
zyMJWuH9TQoPwUBwILQ/SVpvvrAeygSzoDduxaKWREincYNUkXUCBjX6tEARg33q5cKdKmXY2hes
Va45N1pbRV1SpLC5elQ9aWZl59pu+FMXr3j8RnMOAmWJlPNhFo72sS/9/sCz+75IzPPJYTK4o4e3
U9Wrx8u3VV2WB2PYaw+iLk4Ss6DrAnPMcTYfchMJpYzn95M/APwE4ojAIyGnScKG+59rRNIDTeTO
oGwYpoQZf4MgakP4UcU/SRIUeMmb3VcNsPsngq30CY/048GAU+CWRRS6Ux5y9NZXXO4WaIfS+pOg
B9oEFb7YmTWeAsRrSarNh4k1tSZRAIc3cAd1h2b3UUuarsyt2n5wPlh8jsKds5B0XdWx3IyElJ66
qD4JalDw3eBOMDOlx8e+/ghqve+1ZwEnnQHwPvQb43/Y1UBhuNlL2SnCxihITI8tc2AG1DtD+LiI
3prHoJYpKgBKPKvsGiLeo1FkdJWX/+3gjKhPO/MfsEB3MbGL7ltHv/vm5iRexStWBJ1pelebkcJz
kOaf3LLG/T0V8PKKJAxXJydZqTmHad+Fb2evJui56pvtO1ppiU8LhPvfRJkjx/lzig+fCUuPb4Q5
pt5R+YeWUoXwovuV9RHNIhVQJiHYDPnOewSLCRzjtTxDXTN6oZ5pgyHCJLc5FfM1I/6/pX6KlMBH
BBLGCUEHp9GunbOjTULQsSNyy0Gvag5SK4M7VHEMNZR7l39wNLdA8Atpiix0hmrnVU8mOotGlykA
CO/Ark323cwJFKu8WAlwIh6xqMJW4QeJYGaDh4CCubPNkwtuaJuUhrXxZ7bYKeW91E3XR5oTOd6r
qNaNqw4f1YhfH0hd11r2lgv7tUFFtmZP9FlPYlFN5jfLizaQATSqFR3RpGmU+QiYZ3aDS0mp73Ca
680YEMWD89qRgaYEFnWuFuPpdldhKK72JNCNW40wFriaUjWfSWu413wub2aApDTiPjSB7x6IQy04
speSj2BbQ2bwA5mED++yEiy5qQUEn9ipH2ml8wo5OYixUXTOkDG1mXXjWHHFGK+8aK8wCuQFSYB9
Y37+Hwdex87piJPbJbdguCVP6/iZshidjjnsEpnFgUGug/MCyODy6Qzt0+JELcJRdMpHoRErAS2V
IVsP8SRyB/GpcwXNDRI5ubL/Q0fXdsJbHI59dwmi+phsbXIiRlaOZP2RXaFJEoVfC4wgSMkRkQkb
F3F1K+XjOfPbdY9t5YcWfrq8ehZBkdguaoDOAwhfLxIjtMba7Ko5cSm/PzeYaBNK6+kI814jfeme
wdBnjV7zFN/rU4p7dLDh4tDCtfvCxuS6vLJFe8qrKZnoVHpVHQbsxEWKDVo9FKFAberBBSyzxi35
3oXXpoVrknyfI00A8TZ4Av6DAeqEPCBkpKVBMq/i0ub7emibrboLAqfaLS2JWpIeH7qJYPjpqidx
o3u1PuRrVu0CoGSPwiTakDAQQarQBrKKrg03ttF5UDEUezi4UqqbBEBPf4usMMIeX84MnT+VR4JR
4dSmIw0y9VldzgF0tDRCdKVCTZ1+qyBZZVb5+tufPy8ll/4eDMglqAP60krZq5avv3ezWO7T+0Rp
5IfcXkuf4JMTBaWARIuUURXt+SqCQGz/kfc8JW61LqDpQLBBbZNZVsvqgIvyMpQqdfLuX9VDGUrL
jflHbMFRY+wJgM/bKO8W5ZO/nArnj99LbhNckizgcyEnNvrfuTaevespaRF7yl8uRyeeF21wBoaU
OxVTq57HaNxXuz6GRATc7smI8IEs0pYXZkNnBc5bYLtV4hgbq+3GTBfS+Q8EKWJRxF+nVlujLl95
GYMiAaMlMlvA1lIAVyOEtNiHklzwiWbWkqbvCTfExq+n1BHe+WO42xyq7JOum/NqEAOJCNfZPcDf
EKLyYIx6vwRksuGsAPAOmCGeSDi/cJZBCY8pRtkaxn7QqKueCMYEMb9prDjSQEZs0+OIRVp88GGh
Yw3b6l1DkmYenNyGSkp2Wbt0idcd4jTRzVu1b9opXOuUPyP8j1HVPGnHOUyP3mY45sOizGqvnXCZ
cyWO7srPYt9Z/oIo4RXM9hNOpMKOlBhi01YhP/SOo41ZxHjtwwkSqSgVSS8UAD5N7n5EFroFT7wV
d+60225lh7WDlxMbC98nbdiIY44AXlLfBKQpnwDCVG5MM7DZsDKL1+mFhskxd5wxv7+4BEmZZrIV
mKDMX2AeAdQQTk6DXurlYoVdy93Iu8LgKDCth3zlbJMAijBXNFkHjf5Qp/76VhrTOMxI4pL4VY+b
claIlyFozJV6aBrITIOiEjbCRCagQvK67HrOtFDQZxr9LkJbB+5yic8bo5y0OI15vK5v1hTAMLlO
w/TdohwgmMtWtf0CXS8TIeKw3Ntgu/IyeAOkW2+JoMzn3K1xGDU8bXKPEVfQRnnJsIV69dY7bSlU
TT3PnviDaP8HPo0L759n8u6BzrZ1IwcDFPY7yFCpr6tpGU+ZoKbZ5n0bQz9FGK/UvLIuZlQ0AEb3
nMtFAwaizGnoTHPZlx92EgInHh1ahYqG8AwGac3SRQ10XqoQaF/KwzhVpQ7KTfmN1sOGfphfiElm
fNhxwA9ZkI3vbvKlri1dpqXOVqgEifTEf+pk5tFXt0+FsCSS2GN4K7o8bWw//VXkX80k9Aqinju9
diFJA4AKSBMRPhU5HOVoy90YkG90WHYQPVfRKlJgDZE7MFj3pw+FTSowaOus2GrO0mymn3MymPTp
55TCt30ISQjbih5qt33Gi+75Veg55YmzpwpLmDojcrb+37nx4R7FbwuD+uGiKJ5WzQ/bHCawQOu1
hn+V/G0KzdJUAXeVk17n3AlRT1SUu6kez1MF/wDi8y5scw1Tu/da8gmz696oEssNwkPKuSuepSug
9P/CgckZK5jQ9mgJQ9aZEmHHfFIpsU//v6xVVoS1W4N6KddRwf8gSKomN79vZKjJswlrdQy4LxQW
SXVZZb5cfV4BnTn/xPrwXeOuJgdvO5XMgQSGf+JMN9bLCv0H88RNkRK1FZlqe1xeC9YMWbQonaQS
j6n+towcEfwJ2kFlfUzluovz+ukd0kBosffoQzFzy1chH0M6xOSSAt5yierF/9oOP5C9XjbOFYIS
PGhbVxoArXQKLe55fDuN4uDTWObrEHLx2yjCj7FxI4kCTbyIlQx8xzwctMIQ6mWqXAe2zlL9GMrD
nRQX0bKG1VONd9+gn2cUMNd19IRxRK/AOXeIhTX+qdIJYLj1eHXwMvlfA73VbJhvRkWodsUVeE2w
6SdnPhWHzve5dx5BrKHid2ElkKDFbYIxoaPUfVE0htn4PwrumAhwjW2az3zMMR4m28ime5x1XhAw
slJEnzKGR3XQgX/XIC5cW6V25M0DtHG+f9InO9j7pg+KMJdAiuOBjP6rJm7i1FxjCIzY8N/uU5jg
2FLXzraU7vEw+fE4SkKfvhaSmuFxBaJ2mlJg3VA1J3NP8xgk0zE9AfuugnU+S4ioXEI3ZCFCDKtE
UCMaX+B5+2yD4Ajgdc2Saf0URkGdqpuQxIVqiolDV7b37vlc+h1l/7nizcLp2uwJwI1Tx7dsx01Z
KfHnECFdqjbtKOpQWIrotfpvhKaybxtZEMmm7dCwGFTfi6N1CCxkB/huWdfVm7jiQac4xOELfgZe
8Q6sar9xQ7I1Hj/vRfh8U7amo28Bls2HXVPhPih926ULzaOJ2DIAAnaxd4OJoWVpBBFeIvh6VFlW
pcrnY6HCAwlhunhURmmWseohguFrRdzWUv9Pzm6ZoWFc6cEegih9Da20DfD1DcwNr0O6V+16N/Fv
0/IPfq9odJ3iN7OoGJWb1PwqSz3j+dydlG/vY4N9y7n7H2Vl6rJncGRe4fI3gLEHy/GFh1QMwjSz
C8ZVu6mjiS7SrBLxFjG4+dEzseXxgELIFRQSHZpGvBEMBgExYe1YT5TuSG9m+I0Z7ypCKo+ayzCF
qI4TtFWOkPcaMC9GbeufgoQtyZ+5k3BptkzzhisuxehcROxNLv3aEGycnVt0s40wpluXutEevJMN
8SbMAV1QXE50qp1I5gWoJNejfQMys8lvQfUQVec1aKeYBWzD+435JlB2ZIF02EYgmuZg/ToK4/j/
OVZygBbmBL0TrUuusxB+bpSe951lp2fM4FY1zqzJcUHU1s9s1QJ1AczzXlABqyx0vo7LLW18Xewv
tefc001++swbu7rYryzJ7ieRphQhDx71i1r7LGezbXVSu0rVCxBSX4XSH0o8GGqUlCwCsSjxTTAI
psRObvAvVtDprIShJ7C2oK5OlS34ho2xOVNeAAj3hLhbF2m4ZW+aFjyadma2fQs+woZDfh+ewykA
wiEDVapSAItOTxYkIeSJYPEEoTgKjP5NZ3Y7Oz6Smd9m9vwbGETNmP1HlqQEfHEJYR6sNQuBrtYM
uGsdb3+MXIiRXVy2ZL56pyAMdVIAE/SI5ARSI81rEr2j1YGFeKGAzyhf3F2gQVgETv0wO4sb/9qD
STsa3NIfLpFXde7nOwdaDrBTdoz1UlaF/2Hi+07gXx64RBA76H+WVpEcQI5Jwu9NhqrAAIsAr2ak
VhuPBCwcE/Y/hNFfHMi8hTLM9AXwtDFHguzHjcwuXL6XKi2GYkBc2MPEmPPF6SR6rE/JxxwHv70O
8srhsLYem3i0nTj0GrSVjSsogZD8arJxv06joP/3UVtsarW3EMjkQyLkOBb0347B4hMeizOZwKQg
hGm98zMbVxQzPkurIQsFuWU3Ny8gq1uPhfSevAcUP+TsMBsYajVnOwQ/PT4xU1Bz+j7PiP7KG7eS
X56q8fVF8rDoVKmkdfxUxnUZZeqxgPmile1L0XjpP9T+jti3c9BO29kVGe/cL4bkiPgNRSA3z7US
nEI8JbkbJK5MedBtBUuHgm62UH35Vy+qDETQbj/PLOGHLoK+PpXBIh39Jxu0nl4IZw0tdToMVnWY
ozk64rhxDvFUnIDTg0iwckCQmSDh2xqed8Iqojx/Gd1v0gfMeoKlAnQiI9LyptsqBVeVYB2vp43N
6Tyzp2V5ZxRPV01hqegU5MKvLA5wWRu/ILyHPoGhqYjViUkwuzJuXJNT2/cONvWeUcOGuAce+sj9
qQBH1fz7QPPuWOWYFoYnsQsJLZVaZ8qpXhtAoSYTNIXrEzJHBI4mhH0WoksSdCnBplZDHOpBk/V4
B9bjrTsnzTyXeDCZc22SWg4gP2BYyB2d3qh6x5OE2g5EOGFjhQmiAFMB2AsNqvA83DokImPoS3pi
uwBCoeZHEJrDTcweLoubj/KF0me4U3XE/Tqhr0F5mPfEoDeBnRWLBTCWVE8IAeOEXWwOVjNZOz8d
V38yWeXnqb3BGgmYYWspNtP+DEDRnYyhjwpEA0Qg+vm8NeF71rD+eX+DYFa/6678NUnFLVr8cV8A
Q6fhcIHYJJ/fvfbon7ua4taGwCHYVVByqdLOwh+ys8WJ6iIF+ymoSdCWKB1vm++EBEN9N8TjWN3t
souEe32X6kNTmnNNWPYGEQ74v/AF7Mvq8JFkmZNzDL+0/AZmg9GKdLUANCduy7o9iQ7mKaF1xalE
/H5gbRA8B8N8VeTu4flWAJNhpEtSAIqmg3kedSuayAUL/U8+arod15wLBlps2GgNEWPVb+EaliD2
ax8ZQxrCCQ/bH1svgtsxCgQEfBHjf1i4HhDeJScBAciZ/X1I7FMmeaGmV8DZo2+kLzb5TEEYSe5Q
zbqt8NKTDtiZAhhjjFJ4TZ7GEV+pgjuFZ0WpcLHBUBOLOeJOul4ur3tP9s6nU8Jop992cbUPP+nP
6w7v3NDBtX7HdHGCb8t0C5W9j8K1AqiQ7UeamXnz1Fgm5NbYXWBqrZloX9Jq2V5LAwL7XY9ilWw5
sLzOsqQgSdn4ShJrPxXSo2hZSJ+wofSmvmIZ04lV+q8Z8QEvYkdOXNhtTvhTIblnbrVzfDVcrxFb
tlg//HgB0DSnx24JitEPVpxYoHL1tSbWC6doWbwWB6N0QIKMFSsghnI+EV5r31fGmhMtW7L77PQE
XIgbYIUnkSQX6Gl5U/sucgUe08W1/ou/jqF9Ai522mVrlskekeZFuECVfGUEi7GcuwIgps439KDp
VwH2NrEJ8ncJHn4s9oiwU9MB6DEcriv256OZaNSomjw6KaoTdeFGsrMk9uOaUsOew4nL0F7yldyd
ym1Gvv4yqUhBpuaarZU89WNAQWBoGohQcighd8+k18bRlcHcFXmV7+kxKsRt3szqGEJyOonXmw/t
hLhocpareWZDC27COk1ll6a+SOmwArSgdc4FPglZ7n4Ly0DTBiaXgyq9jzTm/u3Tgz5wPEwvc2Er
KVFm2NtY4v6ra5reyTU5rgwtB9qQO9+S4E7/dN/xsiwveTe17QhIgPfmnOmV1ILVRThvaUlPETeW
lIN/mgu5AQqrWSRulnUzyQjySBP3JrMMRAmP3r8RPNXhx0lBSP7ZuJKR/eFJmfY/ZpNPYaaifK8f
SNlfKmfvH0M5XhzJv7aW3Xi2VmoqM7VR5cz246yhaQBmnPRNPl/m5xnXJS3WguV+zwlhHS3/JAVo
jdzSK8CpQsGSXt10OpKvUruefHv1MRAq86v4bWWdBxTsKtCFrzzVw9vMf0m1JvRDpsA4PlegvTvj
RW4WYKOlKRqg9a2iKbriRoJC5iFfHlKkHNLWvry4EeG7iYNQmYajGWidwAnIf7/Dd3ThiZHuLH0D
hP/xJvFBlbVigGmUuM7LmvW9bE3ZZ1193fJF2/9KaNh+k2Sz5FmnWzo+9Y9tr7cZm9yzK+n8HQ2L
v2OpSypPs6MuDdGSg4zfPYF8MlRGv2XEAOGEYD8ATibz/e8thtkEZk+J+P/GcfNz/aj0ayURmveQ
ctS5V3nmrXEK5rRrFkEXC8iahO3kKl2MZucwe/mqy4eEErYvaiYR1a8bjPQ1dhp2LWy1udlFjepp
aX4I9PYJ8P76PwdL2CFx9degiiuP3VHJ946kdvGHl/QG9iNQdJILIHhJ0mcvWD1ZJNESyhsCjwmV
goxC8bdgEn1r7+jI9Y1gJwGNdyyhH0fPVQ/wrC/CbuGDjceE6YX7EgUIxxskelbzXCKehqEgLAiF
212wywKAw3KACf3jZMADjU16ISeiQZFPTDqQDfHkevCaXBW6MITnUJHJUPqMMzmTfbEHAzeouKNI
cZf8fIzA5dsSCw20t2rXmOToPJsXRaIaKT2bj5Vxv+UQNyY+qgYP2r5mcXFKoTSq1ZakFIl0hMGU
qSj7gVuKtvvMn7VLtCMheKUZbPmrVRqGu4AjjV+dIJKJdbvoxHYgh8Wu+LSPGUfHGuMTWIiUl+WC
roFItc8Zncgne7FLeGQpGXngh/j7SrE2IZucJa3JZWHkNHOZLrxT1GRiC/5td/mvjV79bcUgQZgY
GNyR5l8OCGREPPYLeQBp/uF0RFQH/WtfeV3Wui1kIDh79xEv2GOJcsMfXYYTKuf/PC4xPwChZxcH
ZfPcsI9iL5YRX1/LoHkVCnyNEbDihF5BJTrjs3dRolV75pnsnRpmoDhHMbG+jbsk2GgzlZwctmML
YHxFt8xeCm7iiLgIq9HlhX4nW+VkR0A9V761IQF/YOOXN0D6BKg3hYek6iCZSlwz9OV7HU6Y8g9K
fEHZOKoBgKioHe6K7T2yxkrJ++Hc484yJ/HCViKZTVRskYThFPiUh8sJeUjV3R5Gr9wTpSPK3jsF
CH6d3gkXehFtOq+LA8YaUt0ZjVdOojJsvB4RRSpI9505wOaUUt9AerqvOshEeyOUomjPt2cw/tQf
3cJCy0osiWYPL5+9Hl0POh7jq2n/Idt/H6HWGzOcVuEFacqPMDeKeZAIKXpWQHxgV3zyo9JiSngN
i32/WLCvGTtcEoQuHNERmAx6VbyXZFEcl2mKhGet7RLcSmluxjm4sqpknPivpAGKHWzYH9Cx8W9S
KvByfZ+2tMMB6o5Bv/xS7m4t9qNrR412myN4NuSlNzEEve/FyOXjF0QtB40jbosSUCL9R6Ka0OZe
s0Y3sIFwyc/6PXpIdsu7Nu1fYv6mzfkZKEk7V7JKmQL0yxQDWEJOuruhC9ITo2Oqf2vO843tsiLz
Ycbh3PR13H0hlX1Bdp/BxX6NIJoBs/LxsB3c3VqzqljYr1ocVSMnKsXrJfKGjPzyBLkF/fL3moKe
n2BKpDvpWzRaWCuIr/pDnY0s5R2G/UogA7HDpU3iTxODK9k+zZeGCqGOnNIXMNZRqFyWmiczsDgb
1Pzcxb69D05lZOrpqUqqz8MBr/KJW40+hlsq+fgo+G7MLQKAazjP7+7NhOZrmWH2zL57XHnsQ8Nj
Hcr2gmUMZ2j1ROFWdvDN+sUCRnZIyaHWFRzV7MR7r4YN7+XyhhMg2nNc5lOBly7nNX/rKtq4bQ83
OCmYq6mPUEgp6ErNW6aTYqYhf1Csnge7P2zs3v1itCGTP6fbXOycxRDMqGDsHfbIFUEM3YOQlRmN
CAD7gYhFN8V7pclqOBOBD6DSCDfqEN4+T/UvGGcuVjAFDXID8SMYGvZvNRQxuJrB/W1+AI6rI5Bg
O2F1EI7ToXV9TvLpEM6HpWMeGKe7RmrcqFvQdqJBe+cMMjzlrtjwGQr6dY7FSUmuDqjrHtCIwjF3
+SZJGC256nBaZmsup2M2JtDTUCl0My8YrX1V+D1F+RyWvJEpuwzKmPsyhOYjSkjzljhti/qzHN1A
vR7jDph4HpaUUSTANUvvh25u2n4QFdRb4Kdy09lpn6tF54atag17N7cuHrmQntAgnLbE9VpE7pcz
66rfDEmPIMmGy7pJbim3vx1An01h1y541Y5iyIKPhArQdsloDatjOPx0vBZm6Ttt65SzWP/Q9f0o
1J5UhlAiHHep2NmVWIFNNqlE2KQsQk2XvBIz5T155/F9jQH7VYN8cwHQ7vEkWn/7Hd8/MwgZV583
G9pxjQXMa4oRp0ELU8hcA379nWbpDht7y8otdFjeeZ7FtoPpsUJ4bPBUSXea22YIISU1dGb7Pozm
scRE3Z9uWwv/pQbuwuqW5JRFaJnWlZpzxmDwMuoXxnis0wPevRlUaH7MKXY/HMmVXxYskN0rjmnf
rI4Tp/26xTb4Acb3sqhl186hO9X+dF15lR/AqTN3LrRR3nMAuJmXoiNZFZCjK5Npebgc0QQrl8y5
1Dv+r88lWDrWwBLPprsSorm+9TQ6fJ9qOkr7164ufUh3FuGnyMHnLd/EQWDQ3sdQxTiKdJqPfdp0
sjjZYJOz1ScmOHor1zps/mrio9TgoMK3VgT9UF74Eq6uwPb/MF1pho5CyKa1oZeEBNYmUtOyOPZw
E17jvN86SReytpo6PQt2aHgv2eO75cyETbMLrHW2sgR1Kv9UOQjhCILjRUMU//cUf/Cn5TwKYeGF
d1AZ8gB4ZNzpI8VGlm7ViLloaJxUxywOiNiAneaPJp7oS7BgcDpkAIb30NFM3OBow1PWGDtFJF3t
zrHf3h8ZUHJ7JmSbPA64kderM6TOrVBJwlc5tG/LqazRHOtwbl5miuxeDCCqPh5BhGhp+W4n/t3Z
ouBXll51ZL1yrXslBgidLHKZGtwIt5yhA9MmPscMCrzqr/PmcbydaNNbs9HJijsvtCNJ97Y5d4lk
os6m4RAPdiJ6R34SyBWYXCQAo15Qinp1785rkFE0bflXOJkMTFt8b09amgnAgwVvC9+ZSYqh4Td1
qqzWHLIJtb3SMTgrYWdff83IPHx78AXiB2aTHOomB8Z+mTYk9tdXgDba913BuCa9c+psbiIh3TBC
xF05yGmwvEYMmxROX84tel95aCmBZEs6m8dxvvGI5AQi1Z9JtWINSSf+Txn9yj3MJL0R4UBjH6B2
shgO1HobQmc+KjPCf54PklOuR1PSI3JvH8Hh9OhY2ThawSyWj6gENVRsfW+xHFr9GNQ9ehE+VPE6
spHtUHZoXUwFOXKv2CKjOpIfq8HV9O1J0rXGD4/uycxgCgAvjz4prB9MyMi//PsmC03IrGT/a8w3
bcSfQX17nL1zmdvpdD3vb5984IraAyy0aHUQpb3vAxS5pUIrh/KE9//orqME3qzQBB7RMgi2LKVw
VPS5M9Boe+I6Gk/F58Ule5HFolHcvuu+xMSAd/J1ukJ+zxw8+m6Veon4VOBLCvPVHW8je+I98Z9Q
218ksvac28gkk6tPhV/pE4IKGGlr5IcOJKPZxxqrxG1Sh1SM8TJ7aa2MWdhgKUtzVmyp3KZvm3ub
upgMc1L/4coQ3GIVRhYwT0ahQCBbiZbSitEQ8ZCXPPI0pj3KV0MoCGTIAqPmsyZyXj/EJctHflDT
qYH34TzqKx0w8Tp5TWU2nMgwvDIPD99zfJTDhc6Bt76+e/wbPRgynTlo25RQilZ4vkRKmKXstEtT
hKFiOQ+VSnPgE6VoNW5i//DW5p6414WMKiMpWaZLtEd7yvoq941T1Oht+gUtIiayZGVYSb9vrH2I
7cAhOfqEfpDGrtw0W11WzthhgMFGv9OR3s2yPLVXvaLLi/yKgiBIEzgyaMGfhQRlVevqWrhzkBb4
HcS+CQWh7CnKt5NYIWrPvcD/cS7zkdS4ZfUhMC93gcVzsRtxCQw81SuoNweC47nnqLF8z8FiQd+v
VeKX9IU1OdBuFd1nCccf3Ga1eGJR4SXtUaH4JkPZ2sZ3XMRE2h17zgfhYSS23yrfw8uiFblAZZBu
lWUwwVUfkJtFO19X0cYWFhyJu+LHJMZcwBANVvYiaK3RBTg1UhArAikUPFZpaI6NTgVWM2ZIuuVx
xGEBBnuIOobyjnzMiB/i+ef+OXrSGNrjZ1icgJgRnPGCPF8vfkS3V/PnpvqM2fCfWUckWN04CrF/
7AnBRvov7hXM1R+5AgkKWJBKExMYYQrpbz2T6F//hexv2YXBJdmYBUIX08aLatbOlGOZJf6OQ8td
lV4k5YE7Gxmtw6EhppJVF1UyVcCdAv1oflmNWCpo0fulLUeIVbSqX+8VFXJC+MT8b8TvW/uEwK5D
70ozbyGz0QqpJIijVhsFwXutOP9rgT//OfN8Z5mEnd5iaqne2ipv++p2LcDb6Z8CAzKOF56pjeXD
SMLcZfz1rvaGMT7cUEiWEHB0myIXjdAYADUw3peAKz83cp+ABp3Ix+GfftuTPWlJ6Kl4BAaaIV+U
PxdHvS8FLhfDWdo5FE7IrsYtwWn4GaTFxs4sTkQqsAmosXVRLUxrTC2mHAPr5wkkf6AzoyUQuskk
7D0w8jpsquBrZbB4WYFlaNvG04MBBkSXvQb/xprZFrAcdGufZsy82Yx7gPIk2WGtD9u77vypqyyc
wAwsC6u4o4zM3wKRlc2Xr4j0ywewxlUmH79Ad2LloIQVq0gHNc4MiSxOuMo6UJN14m/d7JunD65B
D/4AKmUAcVVlqigSGtC2oRJFzd8Dw7QZSjNOr3jyzWOsI/hp12gThh1pY/I8Qb/GiJuIf8c4cnQa
n0Ak6UYY8Am9B/FTqhtX977oaJrn24HBHUEcspOnqi75fctgR1vKYU9jGQuH69xYkkKKANyRvq9U
QkllcrRgGRfkC6tCGGOz0cTTfNq821ijYeHDyviJHL2yNQkGGokiiZSLPMkuEVg7Mwgsf61nvgPQ
lWNT6R5tvcPBhwSQySxyXU9d5NNpdRwM/6p6k7LdSWf399ySobaq/KKopEx46l8QpG+/svTj8w/R
UKZziKMoeIDr1Ce6aFUO62//7C2lcWzwNq7rgL8X75cTGCkbix526Az9JsXECBDHboRJvoCgY0aF
G/ZTgW55qpoFcnvKB0vFaBuef4g4GvS6kdmfs2HkJMOvHrKtH6Sj8MR+wBaoT4nP+lnHzNPpxBbX
1ZQKPxaXAPYNagOGtuewY+g4uEeRj5IxwZlpzYFsQeJORhsXupSI2ToOdMwTAJx9DCldhiaTPhW/
5z2CGniRb4K/sCimXxLBiEcepRVkhskxk1FVcG2dwHL6Vrck+3bBXFyqgXE2D0h4X3EmtFf2WAtN
kHwWvHP/j/WYjG+egvtUmZB+FzmQcaa/QprCVow2G2ENjv+OfI1RP3MMI397iAMeF7ia2dtO5tP+
h4tgPoP9Ky8jnVV1VZtPmfNzpi8puRj+V4Fk8xvvLHc6Or+nzxLmhUWeMyjIRh/W066/+CDVpvpM
965KlgfdllmBdzVEqvRanY1QRMkKxUMi5MczSeswgOvR/t4F8IyCygLPmV/+lAXxkmt9WU24aVrG
Wm3N0H26b6hPd4rAdkF4lxPsUwBvxsPBXd0isg/6bwvpghwki6hFNUmb1oSbGNY5LRGdM0rcH4g7
c0uflOKs8DSHaAHLKBs+zRizf0hM7FU/nfB3CgZmwvHZu2xATFeDkn8WJ91zusb18ZslJgdEVXB+
k99dTwSe9mbs6250pAG/g555sSJev4Ukk71PxoG92EKxI+pYHNE2gut3dChI5hh9dKUjM5Wkh2P5
zzSIAF70Ebmc50WxkssGFIXsUIgif+c+X9gnQbF/n237VYA6p8GzIA83wyt0mnrNP0FpEe1oI2VA
t9+ylp3mc2qnsfCoOJZaWvXn+Har5G9GbzG0kCR01A/mnEY2zGAkVrMTA5XSckPCqZz4J1S3cxem
oULlGpBB74UcrCExOv0kV/h8Iz0G3xUP/QKjl57Pk8lSJ6UALaaFdengUdTrw/j0P4iFE9xYDOEK
zvZ/saT/fcpmTgXvAdE12i911d4FJ4hQUJE8wMWEs1V2OBeNUN5ppEmM+D5pf8zJok6+mseS/dla
s8xv2Or1mu4DNiQapqBW715F4hGHnruRlvZwJWJTIKmIxzW2t6DId0mZp8f/KrKG3sokHG5fC1xK
M7yrElH55Zt34EHqeWuoPq/8J7TK56vPBgfwkrZKlNvlPo6tqA+2Aj2w/gd3wbK8AyOogQw5YpNi
wkg23FRcvd0eytsqsGuUoT9oWQoG/107LyUc/60Mh7FdbMDIPMYQadZky3fvc0WBQ3lV/F0JZIY2
Oekc/ZWYnkDDtD8as938BHV/BEH29ha5CHYu24rQOG+FcOKviypbCD3tz4CYa8ZCLTGNO2vBoK3i
I+9gkEXy3KxJXEK2aCVuzfRVuyGOY7nh/y4vA3N+LyyCYgCioHdfdFNAkxVwc8a8XimZ0lgo8SVT
SE27wxbfNvg0mx03ymeuOYTF6jAl8HWiF9tVKvTYiwTvSoVnCY4ZiTPR/iJybkmRjsUMc7SJp10E
zoE/1uGCMCBKglDWZOK+hElDPW0HNqb8QJ+0YZIu5t5xJodXyWqso7jZrJQchN2pUOJgWeOLnPBc
aJq5tx44VQEjawZ/bk2XW2D4tJqot+fFz17Y9y7YQcuATUm5yGL54DkkA8L6cwLr4G4OBoUkZvdr
x4HXqe+GHinKZMxV0heLaCs86+SZ/xKg67ah63tqZG1J8eik4QycxEcYvkxVucki46iEjsfP4awM
qOcelISMKf9N61RDUghgp+iIHBv+21GFPI3aQP1nQRgFJROGSLKfEmVc9d8vCiabe5NiGZTss34+
ba1El3V15yoQj3wgp3Y55gbyA66jbrjC2I07jsIt6ZWOKphKiAWc6RCjowry8e/8IIcjb8pAn0Cg
BCmnBg4jvqcPzrAGEEr+Jwz0ZfPWFZyBDdmnCmdQnxfXMRvsyEBo9Z4b8JVVd7qIwYXWbDpFyOzs
acN+cTiOkz+td0eRSYTyr2L966gDC4WW31+grsQntzZCQ3nVEEWiGfyExa1WhKtnSdf94MWfo5GD
BDjGgqdvQJxK4PEUu4mwxrdZwyKJC4Eou99QcGL8hGKlFIxJEu3LxGote7Z20zqzjAGVG402a0fn
B8Diic3OU/EJ6vI4Bv6lbQq0NI9gHZtti0JJOghEsLdJnlbaSOmFnDG3qaNpDSh/fIxDrFr2ljys
rMQlaSV4snXPG38hg/fKCwBi0JX4vSeCnyj3/PBAIR1iq8Ls4n6BMJsrRT+1BmGsKf6k0ntQoop3
CPhPfOgO5t68H+/UERmUgsOvxVOa2j3lrcBshPxz/IuOj1Tlp/6AM+LFH4hpSTVdqk+0bfGcky+s
syCBr0axumBCQNuyJz0Csb/Hi9iTzk0+g4y4LNSMGS/lYjRH+zeu2AVR8lK5s0VWVG3DVbZyp+yM
0I4pTQ5NMJdxi33Ki5GvFSinGrxNqNbLm/63THovseELD6pgm/mZJZcdLzV/TkXIU8f8VEoTrxlG
8x+wHzTIIvsYgKGReKMpU0Y014RQc7Db3SfXv51N9SBcfkhzjqwt4XO7P2QGCc2ZOvozLpl/gfpT
L4c5qPxzQvYtWsXwOS/UTbtWENDx0zbXL/FkydOZlpNyQKIfV9lGC2cHeo9B4XyIjkx0DSHvs1GE
w/Ws6NDCHpi8XMH4AUc1OWvgheLwq1c8cIqlSSQggi3O0Cb5sQqdkRAh1hA+Qn6b/0ShIsxzCBET
ec+hnqAyOidXpT32TdR0nyRF/jLsBUOTey45bhCZK/JqyMgmP82MW598TQlxM3A5ANOk2ViCmp4l
zFjbp8aQ0yrRsUo/4xU08LqnrJBT4R/4DGHqeI+947/WX3ch1d136xN92f8CIfxHA3m95mJCleZK
GzFG4OR6XKVVdj826d7rLGRergyHcwg615QKPspdQEstcLD/eg/AxJG+qpYoVk7kVN94WZu4iD6B
3mzU3ejsW3/6mUz0GytRPPDMa6UXNkDmNDRetf15TFMSdFuqqMq1L3yHDUpbSV5S+e95n+uNhNmE
tyneorloWkPhEDU/LtJgEYdrCPRLkybaqCtW8wJOfT5NUSpR1NGQBpjELNvG8znDWnOd2D+w5eDm
PReCw2itF5En6FVAnsxsER7J7odmWAC370MXgdPHrk+03oZZtQUTUiSzJeIqJfvgcKok9Vgr2VGT
9n+/QNuw3p2c1BRO6XE28pBwZO9OwI6PF6skU0V4b0uo7BdLe8Dm2WPs+zTXlsdnT79aULIHHnx3
OrZfM0TZsYgcqEloyxgmMzYd1elvMYI7t5tVLPgWw3WkS03ueTv+U8WDWUNZZ9GjmdPEYlJlfIcC
bJ6CCBCJ4nTFOeSzWzSk5Korykiry79+Y1n+sR5rZOVKfghwkDFM5J5kShsAxpK481SHInQrzdq2
bXHoF+yimprPrb0vJ4qrh8G7cCRttLBJoHpNoJ9HgyYbPQqxaNLDn6eFZBPGPvMwUgviE7roywiq
oKNqHhFCin0sh+XZGqI5LcfGwYBhDqcG0awTC6x8BInFloGnSntbqAONfnfBvL/IB2Gzcti/kuns
ejnAch4iUsjkEIl7tcYpLwlgqGxY1MbeXMxjF/L5YYkdsTnwbf8bSE+dMWB3QoLljH0nc8Z5zB7Q
G5vhxfy8EDN2F6Sp/kU2rQMniM+pfCj6cxpJ+Cv736jCZXNgT+CuAePvqkUaR+gBketOB09iDbkv
cHH45dSchjuquzA3Fpz+mUAKaaO2qYqi33N7CKTNBeb6uuK0pNypwX8HoOItPNLks5NPFDPAf/Hv
55Ui+3DuyHVuVBHJwiARIjVopv+NO/jcv5pM/j2kXVU6JeLXk+JfytlY8ARck3bUpWplH652oFz3
iWp8quCf63Lku66aCR4idI6atDDT4UbyEUt1Go9pezIc2mAFG08XOIyeFPWuMRqXxcOjiTncsY36
YOyK6yWds4bmmsx6xlejT0Q4rAPPNDN0/nxiAwX002wbNf3A0NA0jLMUEDj6nBElto6UZcOTA7FQ
H7C4thpQw16MQGx/I3i7Rf6QtyYZlkxzUa2ULteZoGg1I/swJjWoheKjeU9Y8CbdROpVc4HbJFeV
0TEfBzTda2qN3a+Ui08F88saKopQskZt5Y6Ey0i+j6+xfQU1IzUGbRSTRA+meb7V/gM/O4xOZsD7
3gVs+bGO4IrbfJFn/kw+fcK0M4iSEgjRHd69q8u0Qm5XAe1zEuYQxtIXkjTbVZEq/mkJpK/Sz7RV
tF13HvvegC2w4yTMS0U1eDsfsETKBTkCpUKWunWt1J+tU4J2T/VIdDXYtlCK9Tq/RMahrj58SE21
8kYfoB/5srlJh3xoUTarU8bj8Q8zCD8Yuzqfhdosor4wxuoXn/BtW5dQp23EzuEGYRTgL3ukHz9N
b0+9H5Qm5E+8zc1aDOPxtEbQtmF5EzzbytUiR3XTbLNyPdEJXSsm3w4kA++yuAqS52Fcnsu6din0
El82YXG6LUo3rdXoWyR8MLENO3qqO5ASxFpn0JZF6KTaGIv5Uahclw3gYDNwzd0dqMyfK3cQ9kas
xpZbOwdqaXXZ97A7ecHGP6ozQqxMGQztNw3GZbITX7rAP9YlvHQ60cxxhAQYrA2SxvBStDBg5OJI
4yoovBWJwLmourMldevE12KAmXwj+XBKmA0H9Hip35rf6AHRjghEMrX7rvHVZBuZz74RmeWO/z1o
BTr4Juv3hUSKXfF5b2wOZDi1d14jWUu3lQgPjjxVgQaNxJqVQiDhZNI6+QjyEOtnByFk+s4tmQVB
ODZ29CC8ItKOr8xK23Uqfe+LjqzcuoU965PDn48wJsrpl8GjNCHU/29RXTyFuCuixpb1V0EqNTOV
N+7T4mp9zwVKZGePeLJAuwxm3XUwM2O4hpEtWPeSK/jqwjTBV3OkItKG6v00L1XfFWYSQ/vy35Pv
ahYzIM/upJ4UoznPMb1Yv/b99w6K1h1MAM0UJA4x23MhnW45uzlBAv5tpcwffHXQa9uc8D0YRd+/
o/XfKNvBqGVNGi09G0kLV+JuculqozDdCFOPKSt846E2PtoAOTUsJSJeuQ/i37z7wZN3MY+AIy7J
aJY+twKbJAR1AwR1Jc0Jyql7cnRKE30fxdMHLVhuXdc3fHG7jYPa0Zq4ArRCRATVgzjsUCIxEtlO
P9xc+xD3quxFUKDHfCqG5W3UmrNfKVS1sJSSDQay7s2DIf/DgAKlKV/uBv2q7MK66CAW8tbbjZcn
u4zZKabnmhIvrkBxb+jWRXE6UOcrTmUofCcd7+Gp/p/tiHZ9Mva/ptYA5HLZeqLNV0nwZzCZdcl4
FxhGZLaMO4IaH//O1D+uuW4IBk1ywxAlz358+PsUoTasDvUd45qs2HHHK81R0iU2nSF7T5WBcIvh
7bv9aDrTBB4JhuNpZU8CHDxgmfZvXmkZfuzJcpPB/c4e/AifTEv+1owIikqaMgxDPx3ZhtvavfwD
GYd28PAoQjGYH7fvL4OawTPRA6SxEnPjBi2D5XeXbTlDIEG2EtS0XfAaqsMtxYYG0o2IfopTcsdS
GoElPmB60j3SbY4IwQWnttc3xqobBbWUF0kciStcwsZbzxw1ZJr0Cv1LRuRT++wwuDqwwug529AM
TtyDzJYJSzsyxp0mY6i/bbJTtWxWjPWQuKHqTmZKp5lom3JALK4TxhYqg3DABTUMju0pnNKlvAnM
5G37kwoBLvyNwIpJYmCKJMEON/xvgwuco1vXi0YHhYQohPzV1GYhCPiIrdKjSs2/pNQt/Mzd9xw6
vZ6OpmMQIEyDln1ceEAMLje4L72kzKpVMNWeOAJZRhzUOQySElQFlLkDE12ufO2x/jc1Z26QXmaI
bisyraBi0CKLAMNZltq3pCEBbjTR7EvjjZYHwh2ltRQew7Mv844/Q/Z+tFig5zKKYi5QkKn68Nd0
n/K6N0ePWKFVEv+t9+yMn4s13/c120OD3NO5lIJ2HK9N9q/IuLiQf2FTk/LSOGN+4tzAYchHWO9p
7syxdnbMqbgbsHHRH7fWJVEdmbKMXQYRFuFPge2fBRx2jk2OmwNWeE3eN6azWppZFR5bWH6SFpHK
RjAb40CmDxE93EzA+5HrqfvA1jhfWcU2PgqxS7dNjcuuSblN2ly+vgnlBQyLQdW1DiVGes7tOpJe
I14kEJ4Nz3OxinDp5onPvN+WbhGozMPsxZ3dScDVRsHytYVq0jorkqBoRVOwq+lwrjnrdJHZk7rt
nZwHq1djnETmdHkrcR7q3T+x6BLL9jFzbQ3aUNkv/JsoUnSYf6RrhPmkEChd0W/5X1+Vnuaa5wTs
fYgFx//Njx+VVTH0cJi1vn47wATOCs37EcAkFqhkuYwemyLDWsFjVrp+mwI8TFX6sVARgo+40Hbx
tkkeHQmoT0TyW6nqiGMoNPg6HLeQvBOT5LQEQbOeXqy+G2ZDDaYNBk8ilP/0xjecX2ZeHC0w1wLO
xq/kblz1LErq04v9F6OR1rBdKtye6KbI76lCuVedtT2eEodL2vcwxqs/lfg84k1ZXgnqf3r4Njna
ECNzMaULzYRjOp2adxXrMsZsi1ML71DF27VGXj4yyjeKrDWLXRJE4cK5dRK9uFQ/OmHCM59KPTJb
6c3cdyPLx5Q13vCrfSIasIpm9UgaQSDhptAqFYRq7UHHCMC7bYFb2Zqu77SuOiV0PfzYrjLBULoW
wKtZVo+dniI4tIIKg9a3L9jXsSJyc5aDvS4y0n+qc3/lBJP8zQ3kWT8IDzNfAIt0o9o0aNOz60oC
JGJBzw68UJO7XjTxhVGf7GdwJeLpWDRKfASb+DxB3fHLEpv9ZqE3YXTqu6voavK3diuCH46enh+O
5LZhXlwLFaE9/z6ieAdOIKKaJzsZQ/ETSqK7T6gCbCVmj01lGJNXHjP/GofyRr2dGwQ/E6KynK18
26LMmQhWQJx+hlChKunIVm7BG/4Tln+Q/j9KwSIEwlGHhixRswQaivNhjpEclbgxkl5GnUaa92qY
U6fVW/xtKZUGh5jsMyMVLvwS/YgWesd+dfxZ9sTlIBdbRzJcAV3MQcY7wCx3Vt7yh8tK9NpTHoEb
ENpN8edga4RHXrAf1INPr5GAc+NadrvXxg8gp2WTTHgsknzgYCsRBVEIxN98ZX+yub9PcquTyw05
MojwsGTAYT9adW6gpN+XyV9xeImNdOUvqE4jRD94nNy+/QZ5/Rn/GlRx/+zREBOGFV/VsHLX4jMl
I8PED84KJq62UnJz51zJUTtFbQonhlQhO+C1XqVdkfDCj/7iwlEX4V0QVpml9wbKOtGxpr968FlG
jbdueS8LcJsHGpFmHxlfqA7ghF6qvddi8tXw6gIWivpVtKGnMf+kuS1JuY9joze1YVQKe2SeacGz
7WD5UhDJkVmZ5xP0Nv7b7FPGyQZymrlLYleDm/YgXYnAUidGzFnEVb9X+0OlVRJ9C74kTtoOriBj
aQ4vaUnMphD8usRBfPmLwprYiQ957cU+jFyZ4PqsVLfcNJxLKcrG7h/EbQGSALuNZNKo/d8mOgHa
m2E9ElyIN/+WX0HeD3vZKd0yUkz4ojKXa1iMJEERt8nypEihQ67lUwpYQ6IHFBQYzuLpQ9I1GyGh
wqycr8ghK5d+FpqyUlnbaPHN/7x8qpw3lZl/icuwvz+QtwBVzpTlqw4FLOWtD8irZv4gPpO5eCXN
wUsDnQIzExHAcTJ0eBvHyGxFBF2BI9YRjZUp8LuIrj8ZTpKJibypXgYGZXIugOEQXnBd0UBZfK1o
31yrOlyFORthcMV5FY6V51an9etAW28z58yeCI0gyQTw8H+BUtqAv2AwqzQJRMdjYoh2NyszylFX
c4fU8FmV/1mcK+OMThgFUgJ9oaQhAsGI+hoquHyw1Vb1kXnLGbWf0ee6doaxmbUaJI786xaltnS2
RiD6PgDFaGXlyI70e5BX3lZNxDN8+NAeuINAICQok6R7Z4rpRXyoit5FviAfxPfzzPDKLlyS0zNd
JktAjJgIj/M3/8LZlluKJyInjtXKazChS8jDfzhywo64lHTgOHmOrtxqDNpWJVx94kZAirgAuElh
kpPllNVct9Z2FG+XSHJJ85h2Dj6rHoqJCBsEy6gkvhtuEzhk14sgteYxiJCPvXLxSQttpYGvVey+
3bCZn3RqBNZCC/7wZ0ytGZFrw1A5D8i8kHY4qkMHkPw0BuJT6q/9SVoO7hgIPaosyezMF7+SBNtY
x/RkrNs+EV/gJCEMerOjFdTzsk5nQQ35qUnSPR7sNtDTLHTxy/nmLFcCp+2dmCRhhmAPy2LRwczX
HwZH9Ir94jXbEPeMEFsjAitzuMh3K+MLq5p6erFG146y9mQuALW+6o0rA3pfdnkhZsl8GcH08O7v
rFEiLQkaZO3LD4zhKVnLZXIC7WOxw2ngoSerGq6nr8XgG230zNSvOxX1OhmK2jKhaO5NC2ww2tft
RVF5lkzZgqFGK0eUVy+FHob+jZOdZrmzNmfWxulOBaF3bBsSlgIaV0cSaaozi3dzc5tloXyAHx7c
0RcAu2Mn7et57fDaT7aBduKmL3oAkP1oaUEsEBNNy/yXxH3M2eA4ccAksr/bxU8pWH4qSl54GpbL
CYX5BClzMfjVTyqIwMC4vqmDfpK+5cSTK1J8CiaS4nqTo/n7jEXdq5PzORa8Qkb8clJySM+YEXX0
RM4zZ6aH5vcNZTSuiyyfx7ygdLe8d4OjeX4FxkNOpfqCfVClKCBICHve/e+q9/J3nEDccQIBPHtb
G9FM+AK2uf/M/mzD/sv3pcc4BWFHrfMLcS4kr9fvK1Sj8oFnQaM6OVMm3kBN2CvqVh1q/FiVUmQ+
P9LE879g0XQ/vrTpCu9LTwivRDvrxh+6UIQ9B/ZAYhXUbApWPLRe2oripzRqbsiyX0b6gVpLtN6M
+S0d12Nxm01PbCbbgNQpYYR2cJmqLbSzIxEAwkbUoUuZibB9PURsQ0/jdSHWwDsCtQ77TH1fDDy5
1lpdjIl1PpujUIbCQDgWd4FZRr2eAlcFndIWPtKWPZ9Lxevc5SHZtGxzhqCyEo+VzCcvypIKHjsQ
d4df7LR2eNnMTRFxhns3BSLIz+R0O9NBEo1p+LZB/XVAbz57BXgnYF7aR1z4PklvLcaJ6bXpTKYJ
0QyvAhIbRmMz8wOkJN7CUs1jKYCqsJA2dK8AvYi66+WQz1xkrqt+wjEFiR5AKLZmpmnOSruRFrpc
jYpFoe2N/RO7RCcxqrgMBeZ750uNSfkSj/DllnwfzNwgNI5c2KSKcYiPoiR0wh93bMgFe5MdIQGN
cD047oJUD0QMAp5j0Qv2xdzWq0XmD0lfQu3KPjPuSGLB34zBPCSJne7/Q3Qx6JT41Ckn+wKKnV/x
aWgwfWFPEMq/zsMvjd6Bo02N82r24LmZ6FB3G5ajA+SlnDyc2O/sKPACVzZruQg2W99Uj2EHA3X8
O9os3Qxsz8nz7K/mPLYBtp2NQbd18FJSFGNumbBynoCgU6aU1O3qc2YqMqmD1fyZA0rGTj4HWCMs
Ofm0pj4ebN4QG1Lo5vfU9JKeNP6tL5lVNQp9KwO4LIZD6grs2zis3S01tGSO8R9jAiKElHTQ3yj8
BfCi5SLlUpq1S7FBLqGGBisXhKt68+ttJ1K2q94emwfiXDkN/pX+fccSCBg14nUdpholW+9ucA7r
uEODvuO+Cka6lWIbvYRow5+xo32g73ISckkyAmPOj1rBYu5J/K3H1XHMoUTmIeI9dIisFbTmBeeS
oLLB3CpIaQ6KsNnaqs8f3/dTRtEKGAkQoTGfReVSPePepGQygxLinVrikaqPbK4ImsJDVcuZhyhe
FSCaoPQ0+9t4A2aCFinHH57Ha62A2VQf0KMEdaoL4EmBvTfytwtTs90pG3B9uKnI7vO1agCxKcSQ
XVI7BnC/NYh6/JpoO0W5Npq9yebXScAZ/KaHjwdxK3qHeeqi/ofz8pkiHAohW7e91I/bdsYGotHy
6Jh7q6/ZQV3WSNLxxMzWhnBzikDXc3Gv7SzFMpzIqbJ7UgQfLi5Ey0kYjNao1f8+xdmvVRZk0Ud2
Olo/v9hy/jS8FqxUslP5Ns5zgJmnvd+J2tCFBKl1CheVlV79SQHBRggJMZ8/m4s2xzKA4GmTYXpL
1ABmF2RYXOrccuwW/kO9+QtAaMSnyrTrM3uEzPJqtcRy2iiuQSdhLJyETKQUzxlbxQ5S15ubM8a1
Uw4YqoprMbXRMnjYRaLqSMoBwreWaC7RPWu/MqFT8AJbFHuj8QiKvqFlnMPwp4A8Lt8vcPNJhmik
ZJ0sKWfGOQKi79OrnqACGWaLTSj0B2fEyfCe6vOL2kcR1rerx6u46laaggIVjGQI9q73uKP677UW
6LK6pkK5YFPpzrXJaU2M9Dde3wAHdzTxd3jCfT6L8PlDqm7wExEPnmX4uxJW78wSZcjnvnBRutrV
BLCzjeqEqY7EkD1Eib+Q4SodR702xu7q8hdjyj6QwMCbN2TfjbFiDpUxNPPhJ3KEemo0JYbjxcah
0SYUlIBuAOfuygeEPCZgW96M9rA6DfwdVgkCHQ8wkIbOgowklwP4WKwG5mOStSs4FXcqF8+wfEDw
TkjVcziSvSh49AI/J9FJdR7+GImpYdKnqHsOw2BnOhWptawKstTWW/nHCBFYgcU5im/SvIXNGTHn
M76fmDfWJcIhkiTuXb1rcZhbyMgpjbneUO/XUm2Mnv/9xqvgmFNR2X2gVh2MsJMxfnWDSxA8znmz
mEQC1YDHuRoheXOSCP52CpcldFDiMetecyVRGyPqHASyyQzJ47KlUuesBlnzov5g3bhoWHnZukby
ObfhUPo7kYaHOe/UWsh/lYQVMftdisgNfwZUoHSO2BcMn86BxvK27Y3AtSS8wrkmLlIw6J3HlJkm
Pp2D6LpobkMtRIM0ATsmgJdafrTT3Dvbgdsy7ctS2PtPGG4IwOpP8DqeVFVBBroB5imk6+ts3x8K
Vzo8Ki38i3iG6hTgDKYH9kSxxGE4Ri7r5XRR/e7gexQ2tiYtMxUAreL/Pj3kCXG1YcvvJV1nqQmc
Z6zTerRRp2I73iWSZwlDb4HtFiQcxTrdjtUiYxoyzN6wmrMaRKNp1aRg8ijoHjvyDoN6P1EwSqeS
eGB2vd0yKTQ7uFrbbkSgrudoifZSCyTk01xLN8Lt/WXONRYT3agmdsIPjqF7ilpwc7hGgVxI9DRs
6v+o/KDUEknPGsJbAWjat1fgSI+Wd10McodNqjCOBi7MqKgKuWunh9TDxB6j70sol638D8+ADQF5
KoI/EGjmAYVuvKcQi3a0Yf5BUfITbgBt7Se5ztSL3slj8RrpKclJzHvXdSMrp0nSJlBEx+vhgEER
Anq+hvfcTrsrVY5bu7dmwCtme77uyafPvdexOOTknRpZBellGbsWh5s3Jd3ARbxwLZe5M0IT4d/k
ZN548Zcf23p5HyFRz5LjozAKvQ2Ip3VDkL3wccZ5JgGcGfoTJm7qu0MGw1OFWbCqUFVYSh5DnAFs
LARGh03l6BF/7JPOUkLnadYvngiR8ms8k7FNhv7x21FYpFXtXbuyJ/MSHey0JxBRIILoJK9gqCqv
haHwDXEZGsO9E39uSisiKAIoKn+6xwJmHxp4WKSViad3zsyh5WV1/u6WIiEm9z8opcaaW+wESFm7
BOgQyCZtN5GUoGEusDaU5JwbnrO174vZ8UTvOwDiSH9tt+RewjBXe3t+31kRYxywR8LU5uGMkU/5
K1klJpxPMvQtHbeVj+AjckSvuW7gR3h9m9aNU/gpDa0ctqCjTDK3v7p6+6nyQpKIpGflefAGDljR
AKg9AbckXKrnZLXL9QN3SVDdrpB86qk3614Qqlrd1j5I/mp2CJaIbAYmtZHnGxyNepHDBb3H2uDE
jV1umoVqsbMyymQsUkmXmJLF1AhNnwgX06g/zT+YbWXVSWWYKlhjzlZOcq8AV+1QFjkFynH+xhx1
SXh2IL7YyJfxVRaYld6uCII1HZmXlfaLY4Ocamg7A8Cv/072scQ0BfQyhQgjIEw4r8ePUJwVsFpF
7lZq3R0gdGsgVsP46TPzlExAlJXHYkjRBK4BLYT4d7Id/haq3GfiVzzcOHrIdPO7DJ3R6dtieUu3
TMPM8zCaI5/isqkZsEkbLXqRIDOuxheL3tfCptQK+DtIrLzev4MkINNtnCBkF3BNAD9ResR5Gq59
bOm5mL5YFccJM/IIEvXDKFITdd3smYwoAvCho4IklP54F2SPTLEv49Wc59JoL1vmsFAJe0lbLuad
l6lUtUJAxXlrypn0Q1ZcOqPMvfZHfPqfFnnCwIagemJibH4NmGvZI7DMHOUe8XoVUjZSKlX8obbM
Les9KQLAkKDIh+Kmq5QFD44gSzMdFCeKFjBgIZDkAmxePNwTTuMISue1N15TIRFjLPkLs2neqvCs
hn/rNAKAh9A4HKqAWkqRu5Z+u3Z8xuIwwZ0P4/fcPyukqFjNuUAtIM1syj5vE0EphXbc9GlDy0jw
7SDEJlmKNrGZG9HA5vp9lJr1OJKnxZVZxZfHgRdAhPw4qw2iOLNJ+y9X4HSWtVII+csaN5QWGDUr
vbUAIlXvViJk10P0YFFa/yVF0APSmo8c8CN8YAjG2xQJecjz+XD0VO1idA9W6ZpC/5GaKQrBl5+I
BpiihGZsTnCpzuL4xVZjDXm8VQVjMOS4cOPBF6wRYhG44MZTtX8GMFEb60MVRC75Bl/shLoyHdkx
l0qGCr9SVMdCIi7AKnZC8F+O+XhY57Ot+uw7r6jKGNZEGhVw1yuWh27feZWGrSDMmo1/SbAGQBkt
GOdHkXJn5U/hlnoUMt8i27+zJkzM5jfLKlURQt/Pe/tLgQM2rUjOKX6gqVAR1I+dE/5woNIxZDw9
eNqGyv0tWptznEYci4NeHBU2M5elI+Tow48LLLC3tEx+4A1R26/kph0J7Z4AbaNxOESx1E30d9hI
cvntbxcbvgJ3B6O2A/K76Aqp5I75ABO4Ipz32+fZ9enqI8Z/7JtCjTcv5lxCdLTm2R9l1S5hoP4j
CCyb5AFSv8APgRT6jASnOYt+BOY6O5xS8UcSmKJBEc1+jqU3efIgPx8tzfMq6Oic2aCdg9g+13zl
ng8pWHpqr1rEXNdAqU29d/qi92zkmX5MnfTfiiy7D27JZqOiC4+rT5NeR4xkRxSAGoa4XyePhf//
4S4gi2gYLcApGz0IJ5tDTSb5NJiXtnhyteYXLTJWXnpRK0uw7AHo0IA7gtDaBOpMz6OY/+1tQH2Z
X7f7Zq5Pz9Ma7RSnBZdhxBhDzM3IO94WvXBdXSAGAutROK9X+Bk0bE+ijbxnNEPt2YgbMvnPjJlr
KCw4uzJACphPYLhxGIyhKi2OsNdnBrju74jSIvuDlM0dtvFtvoKFWmt8ASGMYTgxuzGhXP4l5apY
tMp33Py731wW1vhnN9GmAtlYEreeAwd73MOYVNiaIfWMDal6cp6z7qnHt9ChMpxeeIK60WQHpLm2
a2ktRCUKRSGmxZ3BIYqjdAa5IAC/BOt7YuwQJTWxpBYnaEkTPtAoieqTeflUIaI6jECRVuNFexJZ
/u66a5IMociiJ3G3LJucOhgDyKdZTSeqWWw3Db25rZGE9Gl6NzJ7qZdvRHxKryytwkecj4zE51vc
imzzGMbHkokQDuPSA2XyadwFU1WkQZPpBhCisv6Uyq4y5F6wy5eSHzm61FFQBjvEQ1vszW0kfOPC
pTo46qojYEhvges+yK5vsXrykCvZ0HQmV331doWa14bVrKX5HHBIHIh22N1Q2pD07NODBIwO1fTG
ajPtjaiHpWiaqy7N8OiaksnpQI5STFkrfHiGDCPKKqzpSA85CK39BswS+DPkOAh1vhu9WqvYx8qh
MMs0fRqKOA+/ovATYaYkCkWy8xYh5U5hIRyRISntLDwXKV6fUetINsixu9laUoPgti5DjpW41UJ+
gV78LDGL+F3jA9pKViPBV64ylhljoAnF4BFfTLNPc48te7nrBU1JIxuxxv7GXQvvGHEdTE50PUHo
0P6LKj7Stw2EViedsph3nom7a6TDfPzZvOBkh2Kd4Px35vWgxaw53aObWBREPEIHnvhphZpSVVVq
7sr0eaGj8O4RP5/seLccSy7HWvf2xECh4NQnntFunURuTT2hX+JXAmQ4Mhf0J9usQzUNBktwDR9/
Y9BsqW2mUwXQN39YOrs/dCwUPTyEGUMK6UUrHCSp9g4gXtKvwNwHiSJ9H/hvrOFb0ajuwomXwVLG
ctDRB/8bet9zQTsyQa465owwAoDzjsUMzu5tD01cgdU2L84aY5NDsglIfBK0sfk+t50S8Z89fihC
dn+0gtNdpdWQFZh0UnLaFusEwclOxwRM/7FFSlMzXKgFMfxzj7IFEgJUrzzPXGh2gcdneMTzXoFo
ejwzOUWQ6rF3b9sXZrHBHLFyKIdQPaRP8k9/U09yZl1JQ2AasM3kf/Q6pKLI8itxTj2WZkxVBCYl
3/Y8ma9c18nctO1S9ejGfjVKCcFla7nSfShiKcBLMQy5699u7n8Zwykv4bYVvG1VfuRi4gwdRI9H
gR71lilkROlh3PcoYH7LvolCN1RcyQtrLvvuBISdUVZff3ZNN20LD8tC2ZLvaKf8+jr5wF/X4IkG
hl/XATC/oBLq+/hCf+wqtkBfSFJHA37WexuOgstAvdCeoigDJBtkFCsJZEisGKDCe+SSJd9XzplW
MbFV5yJeP5O9Ax5ZSh5SEqFeJH95yHLLUYZKRbmBRXQygvLsPqHKjT76BwCZm8zjaxVqiUyu701K
Y0ARpxEw+GEQHxLbu2ianduXQIywHcKuGszneREJeefYEhpRJonLt8pOt3VR+HMlhzoT3Puhfk06
FkSD10n516Xfvdie9VXNE3TPWQc83G1Q6Uy2eaWNYwaX1HTeg806JfQgVc9Hgc8bSTMQwI9x5fQg
Z9w0enSbp+lW081NOX8L0qMLbIWxYbeewkFYlgYJYL4oYjtr0POWWrwAxrqSnpfRZjfjqftZ/qr+
Bkm0p1TlgOT2lcinssDr2IoPEUlsJFl+1QIaUBZnQe1lTqqV/Ueq8VzMARjH/MLz46onJq1utkH+
lMnI+vOG8kuahC2m4aX+R4aS7TSXAp5OMGtdYtDa9ViJOfs1gWgQSDvh1zd3jy5xrWEVPBdfm3SK
Yb2OZIugTU/lbkCmQw8Ui5rDA3vjkTB39Xf0lpmogabJiHLFKNhcWc5kyV9p6JTxYkF0Hr23koML
xSLvgPT+zawmDxSR4w+4ZwjW3lxYZo9Tj8AU2G4+TpJ3yvtnu9nl5tWEVOGT2H8ShHdDvitzhApl
TRPzhjQ3N3PBzxGxzYV6flTpRIUZgmyE4Q/yUxicEsGqk6idWBZ1+ceWzwInVV+QHP5o8i7fxbWy
5zsJacXi9tGXMqj5KD2nzbKs+SqxUBLKzrSpcT0NYP0uCmnHZ0T4bMMXv+ixEnsz6vqyar6VhMqu
c6MikhMuqxneqV4na2kDokdKebfznI5Nhp8NG8DiuuaQKIEfuq+bRLySgYPdYhDTnhgbRCcYUVbR
wFJzG/oErAsIDlfgpMfdvilTWmeeJVPga00EF7U7u3mnVi1VkTayPKSKV8BgY5FEQyj2f/Sb2r4C
8KLWGySLY/0qsxQivC1uxmkJh7Nfk0vylJ5p4hARVI3QOAic8CKjOk4uMUMkgx0+eHdylP7nBuyS
3NpCYV8F25fveBaP82KDYM+Yj5yoGK/20UyeNr9khYxzE7/TVfDQJFurQ/n0OmWm7kG/DlAQLqyc
RYhyRRi2Fr52HT4o9lBR72dcrd0OHpbTUy7rLSTXsYmgelyTkMgrHQ1K5/FhyxeqmbCUM4MAqdZL
MgSVzrPpbNE8FZumNfV9ebP6o7DpK9VraLINJXuQ7K8KL1iGXaD/mdwandwoveF8qLwIJSrdgEwi
B4yUwdLW2HVksIesF76IZ7Pg9VYzgjKzhT7BOEco5xExt8Nr4sYZ3iHPYSraObTUvbzM4T0AkzUY
v9wMLAYdKZfaoQF9jmpHzTVBl5DeS1tLbAR0h5QaeTIVJshrGjrEvDKK6aYYu2GnoGW16/+epqWg
bSRV/ZCxk/l20aYfs66hZQKaC972AuRuqdt5XUn1+UuwyZpdSOrlGXGEwloUs9dybjXnkeWzN2Ew
21bUSJZOS01bgadQlEbIcFUHvdDd5/tgRxQ/eeYH2Hrqjf/Ca3tnKIdMDulbQT2BUYANlhVYnh71
2d3UMOrK5DKvV7tN0HFzxmP8A17bKKYtV4mPg68aSd6FeKf66fPDI6i2cAElg9KRigLW+dFU9ywx
roCNIoK+9Rp9Et16ddredjbroHWTr1lvSzdzVoAjdGWRa1lySPUkHGXfOakc0QplXCE566i8JYPx
nx/2o3tGYUkL3BZaXPulljK0UQB92kil19bPmrd3wC9yiVVCSIHDxMrUEuOEkDmR8RCmApCY1WvZ
4qtpI26fXMDxOBDG5f+efzG9X/7lmMx6982KPk4GnimmIHgS6LT3VniUpYkiqXVCRXGjW35qxBkL
2hQ44QDjNZ/67UINv3kAKJuKzGqgdRVA82qV2Yc5wGUTsecL/utMDKyENFeSDHAq2XhDfIPQHhuh
8tZ3mYRkxkm3gqWHW85uePM43yLj7mbBviZsyG7CAtkKq4IF3SstYDlr9TpMytpFkxNGLh0faNn9
kJCqUExa22eYL95jYSSuItiNJXgZmv8YlrHgnbZ1SFokzENOgH96iu8gQTbhLiwWQ90UIJZhCZzD
KASL7jvQfO6d+DRdLfNlLGUDAbEjdqYjxChjpvTWl9POzLCUizpwrrNcoxkmCQkkNBxpXypg5Zi8
t/tbzoKopceHzy7g5K5039oRPmDBn7kiINic9iaUgyYJ2e8b49f6sp9sJ5d76fWP3RUIA/C9Et2m
Ht3q2W4xnGEghDskbdoiuz16QM1uyMNFgj4Cp+m/PLio6CqXBxq8ok7jdFMPwjwsWWZycsVvrSya
l1Uxn6yhwaLmcWqj66ZGRV9b9TPGJKoaLhk+DKuVG7dHHwLuhFDu97yxdiFreBP/OB621V/y0UGL
5Ohbr6e5wfLem+hkqjrdlTqgkQoY/UTgeiPvdmISj3wUfdB6MMQ2aqmZj6A8rnQFpOd58SaC2CBJ
lyycvyPfePQU8bKOKaSluTx2a4y0Wxs4pLJI6WGC0IsJaoqssQ9Qs5knjLU9oo2KyRBLi8mJ1tm1
oI/39nV5bf+gUdEcBL30cb0hw504wnNpow3AOIwKOlCYv6PnPpJgejp0Yx14sw8iOcj2geaC8br4
3lR1Dfq6vLSepNHn01MVN+mlPkfxgxNyo0bx0Wl8AXtDTYP7W6+vsvXPVpwWGShVJRRQvsyT0Nh0
ZGY59EJxpyoJEyTNxlTlpf5/Fmf4lTZSnvPuGQ20MGGeiUcr9/g+bG2cKkqH9v1QX9cXx7TiaflL
L6xGG5xzWCAg4thiV27GIoqtbPHkqMW3/TuYo3d06ZsJAlQCokXkgijVmUPyL8Ik1AGsYOW5b/uJ
4ex3DG6dMRx1U55oqjWVXit9hVaz27E/zl/wnx0woJjBWtdcyJolta6asTiowwfXRkHIq2KfJRlr
7ggnjjUedA+vgH3Thl3xLq+7Nait6hvcewcxKKe4suxUnwwIxTXklPqNmwimtF27Q9MFA0ROPZ4B
Pogq+1kDQYcMTxqs2Dp6tGnhFQi/+qD0vxZwURfThR0ICqEoc9VFaHlADrJ8cCK3usELxu0sZkZP
wR7yqpsY3ScLaOrUqWF3j9hsSovHZXkUR9wS/rLwuGsMadaKoM8Jd+rGCqRoxUiXHrdayFBptrv3
2cYYFHYhdfLRUcKUCy4j8pFrOKrXR68qEe+S1PJVIHt9aCu2P+/Vg9SiX7UVXT628Y6DXYmX1GET
TWivc/n0WFAYCrRY5hruQ2m3OXVqZxHRRCn8ume0azx+mImW0z+1cWFZgqFWBfsKX4R7z4GQeMWD
qBCUZka/vikIURM9DItJSL5o+LwZXV57HQ6k6ichMjdF7mj+CWwqpox3JweJqbnMXqxqDmQDAB89
FsYt35IL8p0krjqan7vbbUEjkYFPfyQ8a/2DH/Kr70QWf9RzrLeOhRpnQ3So9QMRHRPi5PkugVyG
g42t+7cREAPDSKkTwKx/AQZlsNcOXvDTxkf5dchKZ6a93pbVvoBihaeBjI7t81xh4tZ+hIdnEuBW
hn2IAuRWVmo6YgXlD8qOtYpNNGz21pKmvCmBPJE2uOfbFuvdx/mWvSpvgo5QxlWSAIkj0KYzf+fx
v5nkrdYXyZUDu5z3K3xZoJKXWugnjM1LeIXA5Au0NhjIA5JtF+4vM80cg7fGevKpZ3ydR2+G4+LK
3R0uHK+sXUxeRiN7H/W7RTlrhJKXQTFEwFg8ttzXj7vsRHP9k85esGcG9OqWzNVVch6IouDUDxnH
740VY12GNS3N3lqC3OyVk9BM3p3gfbRhP3hoNoDQ+g4CtYXQaTdstbqmYmXeuxSEW2sfvcWzQdj/
dmh4Edu17x8l0pi9NQt62yqWwjICYvzPR2bssKWP+lnE/jDhDzegtIbvHicoD3jx1X5oZ73lpnkx
jMYqLE1hJIoOs+qPSiDQdGnIDWG/TC788M7kcdbAPLMmNCdHsKPiSAXZar9zGtY/U8Nq9+5yaeJq
VidsA4q4fkkMcSQXNm9GjAUtRN86R+2dsKWZE9jgiPsKajNNb7MeB39otXwt4/kkn0yXDZ+ekOik
pXQwKcLvbCVK7B7zOEtu6SdKcTro7FkjMgZljf5sO88toiQ+ZpYXNm3g4iprrb5Odwk/OmynfH0H
go1vpDAb9AtUhVVlXEVNKgrpGnsLIBMi/L3nWyTD2rXoREi2RQNMiBiKtcqvCd2q7J7i0h/8Ufkg
nyB6cF4Mk8bMTkDQaXVkxXCPPa7GvC+vtpAcJJqFAAOWXVFu/QyqJHDe2GWl2tH0vfG67im/pNYh
0WrmkzUONrjmEEgzvAD4MvKBV+nJj+S1uWUnE29K+m7qw/AbVOFP/i8m0LaVwjpnmkH45OO5l0Gq
th/3fJvgZd55FAB6u4EmVTq/m/pXENWtRBZTA66IQS+puV5PugId8w/BlH+18PaFA1QYLCdXSEF3
ExPHb/CpYTBxM3To0to53xLzEaT9nhj/Y4YHhMuVYLeNgBbZGivzWIvZSUwRL5FMlj7hlNiXbysE
HArYpGM23dLoOCWaai0kPNwwFKUXy8U2ZFLa3OTGPp754KwHCc/2SGavzNqvJ/dgzYQwUdU5GK0/
bVedi1QkiVW3ZTin5GgkoWqEfwjHTsUVBfC0V+BAVYzvCw+rPTwis+cvA1m80dVBBMzufaR/vqoK
DjCKRp9Nqfzw9wSwQtg37Vvz+uzcyHn4k8f3hbGJzc/BbVRE2Xn2HYqNxNg62j2bARw+D4rObleS
mf9IlBr1P4hYCn0rH5mexEBjLNG/DVUGWADPjkotchvODDcmibJsAK44tgN1qW2EkOdDxE83s9WX
NDOhgccARHl/1XEVr0Q9LWOD+adtdTZC67gYvvaCAEOz3Qkd8jkd4uP3t9TKtey4gy0EoYOIndz1
tJSlbSZtfQMHZS3tzHKA5TLsoY9Qxm++Ef3JeLbnaAGvSrMbb5P/DBi6SGAH75OXQ2rYL6zJlV3W
0/0Ms48xc1kLOWbx2B849nMQkHOZ1HayfIILLEl3s4FM+zf7YEDluTDyaMdvwpBZi7k+dttY9p/f
dGNdVPkWQk7Kba0VePOIRm7SOhyF978cVi2wReHzuoVMlxe1yYSeagAKnZdWa1eslJOgH4JhBxL/
eqWjWumW2td+D/cd5nsJc5nMLQSMOSejA6F631T6gX/2vz+wXHjcgObnQVHCgrmE3wm0IZp2Dpog
XVgcGGsEKkgy6tt18w0u67ucwyavgoWDRIwTajTcshELhKHoCLJPn+lAozZAYjyGJofDkTdI2mmJ
eAGShitq5frur1CcDQsl9wIaRgCer/dPG7fKKHWydt4PRgPSoTyQOOHlx4iTT5rNB0iLKFjLZnOh
clsURGaRq+eI1uG3l0dBpc6tMQK5587RdlPFZWVr63OCHoTw3E+6ZJjy0TjpLOgpZA14JoC4eJbp
VEqm27NTqYNmLfcegLlxN+u+AOnhQTT0RY6ZHYSAq2qdMUOjWjXC6IYA+CmqvgVijrOasuYbVwMU
T5CPbWQfkLFNLQpN4irv3THlE6Gboi8GqoEu2rKM/z/khEdtaOlTz01nGnFplh8ed1DY3frPzVu8
SrN2eymkYwhG31OaCGmLBzZJ7oFLfIoHa0mjZ2dhZo1nPUYKqj0IQdmSHmmlwBxF46aetep9ZS1M
BxHOg+rSQYSLVOiTvsgaA0z6YgVglSOAdL8XSR+RlF26bhTJZPZtHvrHU5FSGDSB0eLvZlvq45NF
474HcIzmbHFlyPeRimO1gRBtGF4MDMpjws5KJ4qIqsrTuLBjmpap8HX5VifXzGZw02Tbsa86AQ1d
r4UkXehl4pSuosO3TeV0t/DFCpeCaBzTmlRBOt8rZrQF1BLJDkA3eo5IX5i6nT9yka6BgJBJwlIS
Gd2Y5jw7TYixn2t+orw6FcBYvH7Otfg+8riMzW39J09exA37YrTJpggjOexepGVdNNeOdIB1hNCS
MHlUTA/I/fW6Abb1MDy04uLV7WY28jcyKZHYSuKhjZrTiuDJf2XOinwvuMeGqOrlAc5HwqTR7I3E
caymh6zROYr/ePZTFLkDlMZrUSCfzD2p7WHkKWXZ0x8FWBDL3x+6mqvH3Y6xc7excVw6/+NvyTNd
5M8XiMEtKpQjpvj83kdrjQB0ecJkQzwfZlDQaLIT1bSUsZBkEZQpTRLdLVDnW47+q8uQ3BGu2Es8
eiR5Led8z+XEUlmaZLG8AfytvfKDbzGvXVi9n6DI5VUrWnqJX+TM0YKXf2wScdlqqDpKnSoGrbSN
3yxU05kUUrYNgV6+mCnguSnyjTYIdGiPJbbrFeAiy43jUCaNoPCiQs/LTj+yF5te9TMBoen5HsSs
iL1+rpOl5BtCKTDKqLqmvGwdfOHYoUUBFrpl5DsAyFaBhCr0ytP2iYebjJqTNWy+zTYgbq8i6Qtf
hl4bJ45Wri+hlzY7lMoNmkwLnNGK5Dd9rP5RXIIINOAl+6LfFlSeNgCZm3Ky9x/WZUzbwRGn+2ce
jXWhGGMZtFOh5oUYmmuCFGjjT+cqirjs9WjGuwrx0u85WfdBYT+1rAPnsbjHXqeSzRWi0GA7ohTn
/PsmFzrdVL1cRCtBvbHTpgMJBDceGBm+MXv5ghitGwLudbr3zrvmxLRF8LqRZ+A33/SP8WDn1F/u
aXQjZWUXw/VtSj7cZeuMJ3kQwcvanjSLl1OdqOCTUx61YQW0RgFnkfE4QOsLPrLMhLWxLBuskGE6
EZRTH5eBkCU5hQsUeOx/WwouDIfrxKBGWtqU79Fxnq7FyQ0kn/awkooL1iyhwYjeMkFkrRQVEXc7
eJbuPc8KHQBXIVLlb4807lcHoR7VnMqyOL6ss4VhFlxYFkD0GVcfZy4B9j6z4Ix/AcdbZl0Jr2QZ
m5OeONaVWE7y1nkZ7Dkc34wj605wgdjcA12ikweFXd//IvbAHyCMvcwxtxKrj1ch7Qyv3/FKxfuO
mVac6VGGR/5CgTyf5h5K+a3By7jeUnkODIcT/3qSfGh2SnPPafPvxT0gElVml+36+zkgBDBEMyn4
4mpbBYpArs+29GcpoU5EaQCrJKqnUnWOFkI2noNzhrLlR/nUQGuC72jDc8pzDcFhrrpxMP8+cjBO
pnerO5BVU8q2XHyCAMVjM+2i+P5RaYlVytGgBWdZE+/IXTPotEEnPqwFDTYLfF6dsF80XGNwGxUY
PkDVdLOkGH7G9JZF575mRWpzklpKZHzLi0RC7CltwIPnUyJ4K/8YA08zG+ePqxnq7d6bKyLV0VsA
est8lltSvupiP7pxhpIO+Tzb8Fc/6crmoOx0zxFN8bZpJMh0IaDYQGilevo/APVqPNqlvyJG0R0p
rUzcEEZljlmBWLFVDiM+jmeKbRl6Kag+RZoaW6711pW/v+1DVL6fKT7RsajLyxWr+kVv2WOcHUGT
J0ONoM1Hb1DalTqvyJng7Pnlttpi1JC1zeSt3X8JlJojNHjVLM35qnW24NRIvTnwc6nfqBNW/rRn
kI5AXF3+Y04ZRMhrGp+I09uVl2q6QASQR/ZMSa3k1iGZ64RsrMyAhwN8O6Jg2hLTbC9b++nGHACU
dvps5PsGiddeevunrXTsC6A5Hxv9rID4DvlujWEfkkFnaTfOGXrI25/PejpCHppJJxa5rxAL1PvT
YBp7MYfgVRk7PSNo9Wq7b4bGHFn3HLlX18CtnXNLYvT4L4TSVBPkaGokFOQGUmvYXbzPRIOQJ2es
gCys07/PMdh3esyy4ASn2IyHfcV3lmODoBu4yLk41im1UlCvTti34Yz6OT6MEfCc7kbua9AixEYr
pHT/9Ojd55INj6/Umj7TBNpChhOS0FE/lQqem/llwNGBFG7w8xr+Nc0sfI/mQmrgFzmHW4/rCjyM
cKKOEmffmqJiwXipzkrcsUlCmTuJrl+2IB9cjG9yIYu5wqYM8xKp3vM3r2FI6YFxgobMTScS9XXO
+Eh4BKBS2QoFBjba+x7MjOawR1WvtQOL9cyrV4UNDyOIpAi6+Adk8XJeyQfqoPxv1oi9TjHWn11R
e9zOf1UU16ak2M/neJHlrS9jEhVYJD7uXO568BDPKmiI/UwQgEFlC7A0oQHKz0kt+Y7pxVSjpTS4
PsSgvuNGh1cXlmNdrKku1/57N+3rM7pVThf6L4FWWEOLCjCbMTYMKv40gtJKLmQ0g7IEnhNocncV
bE7QlP85Zw995/aK9i96csG0Hzu7KzEdjIOl8kimey+go0cYpb/6OErst5LapKevWfY1ZXcPc9am
77Rfh56n3nxDrYPWAoOd23YWQsPNR/LuXOT405VIdzVBI/fPwK79y88WaqOy4gr9zcye5rCHn4Jw
phoUp9SjbOqVmDEspVXvT+69EmM8xwtrVf0FIpeV+VabLmgkpn/W4ge3FwyZC/FwN9XaJwoJjhvl
g6VE4WXDq8ZnGaAgnA2LDpWKm14cr/OBBXIvFcDrBqDAKz3yvcM2xoy0akFysJNPckg1zYn7niLJ
52McXM1GujMGc7Kb8EAGGF/qlry//9rem/A1g6Ud5bVXDlUcrzm9cHSQXikSFyLny4EYeLnNp6pq
yzJxI+WEIQuGCppMHEkALbPJv+lfNppKm3pLyQ6t9tIPkTr++ZwK0oJWHf8++hfc8F6CgoUOOhaV
q2HF2HHGFeENA3sqdQLXRe/u5E2WWs/9idX4UVBGbqogB90zAS2O7U/hZKeH1AfDPDNneNpDP3Ox
YhrbrXGL2P/yndL4YY+bPwEYJIXiMkVPixA9Vs7qNP4uW4zIZYItvZkNtp3Xhai3kNsOOpplx+RG
zoCPQ1YarFapbmuB1cQPrsP+99AjeKKvaHvSzgyA0vcOPRGMsq6KIcnfIwHJE8M/3HgKg8XOo1kC
S5Fn6J8qD7YO74DcKWbw0X02Z4fOK/VhmsFyE1l4+IcOVtLivD8DaVoB4Ilxjflw1Pcjn878KOJ1
rBKPzdDrLM6BSipTTS7rFpDf3/MZDxWjXI/K+bFi2MJMObYmKMayXOPhyiiWwbDqgXWHANymaP3k
klRaTljzuIop0rFWTTFTgVEx1ZP+bOQiIu7KO8oczQR72nKwcJvBYKyGRtyuN4dHxQxwKItBCKss
u20PSmDoRbnhCdF0gx7N1F2xMpVhvo6gzgAETedL9lU1GU8RPBJFdJZasiLLkT/Cu2Y1yTwFqKb0
IjZyq7T+YwiwuSQnX83wRX0kxrBhJcErkajs1Dd0NA5Rr9NBZQk+kpCZXEgcYT4uZa9D8G3b29yy
TNUg+PCLSoHXn5mmiWmtYwI0KSUG+vXyOqDOGFG4k34nL73kUXbao88bWjVoMw3TmIxI8Q9G9WZJ
srUuxvNf7bh6Jd/EVedgiGcxUuxpkcv5piEpgnf780KXxgIPG0MKaw5MHxYFIpO67h9bTzR8miA3
Kyhgw+fWHuwjFOaJCZlNIjptlRpsLJhskYnkZmc1cXf7XBcITMYnXz5wQkBiqF87/brr3JReXv1z
Q1HOST1fAnFsu6FRZezJoep5jP53uDOhwzUf0AdvFONx2jNX7wcgCOGhaakODbVtoLjpLIlI9Oim
/CDWv6AcismZUVVkJ/OAO6ulVGdGG35qLe74vZKb8OWmRL0NCsOQr7laSkPW8k8kqO9VSXPGssOP
OGVu4fxGmwJBT6Fr8G4KoSKzvJPJqdS/vIisAVml6DynCqhEqCrRPQEXjFM3OJblVzvUK4zxNbf7
qIx4kEKB0cowTnda8Kh2pIPGADIIqOAW+j2YzZTrluQU7lkN4DrzAfTaxsMNyavHmo4coDQkxMhI
R1jDEddyRpsXWSvF2iWXOIRkU9iB84JFI5Ln0Kwzg6yW0anJ4p8lzHVAFOwBUl0IilwTlb5+ONPy
HK5zHdZBFZCQlWGEyerAD6Zl+d5t3El7nzB6EN7vzUOBYsvRgQCJI1ksFvPJqKSRBvuT9DSsAwdj
YO//GpZ046LXKBsKjJKpHr8WhaiYR+ZQydrqbGjbLFV8I7l6UJADXO/amQlrByDIUI31PN60CLEv
beo5hWwZXIQsm4yuqbYs0tZBXv4UnbikKCHostucX+lBiMb5faRcCElncjSHpomOMDD3Kuym3S8l
dQMvAuX9PBcXbnZR7zngdIgC/nk2u8A6LwYmZ/9vrjhvcq7mWSd7gV+1EGY+6b5xctjvOtsG3G0C
pgrQR/6+eYdJ6GKH3Itu7YnjbGfOUUUgecVaDhNgQi5mLH6Jh+CbKspcGFbXtcn30OKGvfa3VnPl
0frUTiXZ2nbxrdimm+o8SI+yh8KMZrCb3mR4OzJaAAwRP6GnXorMvBF8Mg0iGY9mK3Rh3gen+5to
4GN2vRI7n7IEtEkjYLIWloylQQ7ZsH7/orFZqt3P3A5DuwR0yQlaS1fgQb5UxmTJ3bl2hSkNpO7C
bwb+n9PYPio4RMtNUCqlfiDuTADTqvau9zTNZW4UwA8tejih7VmGmuDB3QS+EosMjN6nan7FIPhD
iUjSydJf9CgHnHrWr8xOg/ZtOLcs8bCb2UHWkc+69CIKdLMaLa0Ah1UO7NNe+/GPU20+vdWBQb0h
8qYggmwuVJ/9uQg1WS91QqrPeUaZf5Y55QfJPGeozYm4Ifi8tRSDlet616o5w/rXlD34GOG1MB0v
VlwIsFM0fY23K/30M+N1h9lBmn3jpfhnVxHzaXZaInnheYY30HIzSlYAJ0VNSqgDpTbNEdyyk2dz
xe2g+Ml7a1ZhPLGze7TebEa/0PYqXEMGslRHzYlrC4rNhReugs/UL6pYxHN36UEX607b8ltRidhz
LRLUrroiKHeg0qmrvlc6SJrLWNy67y/BbOYQA+b44ylCdzQU+DyWoyGgQQ6bBxGgm5N5K233yMQ0
Qp4bL9RKKRIj8jtAQO4DMqisdVlgqy2QIO44/XpBEdtIc57zYXVlBKEFIPRk+UIB3mnneXphHrhA
R6J3hmZ443tLYcZ/aJThhkPjD6yjVy6KKza5WVwdrPgOItF4MmFOV5NeOD/9mq799FOZKNoh6jDI
gLq2yQNQ3rZYMo0RibFkVfTtuU4jbzo0KUIdHY/mKo3ycrT0EOVAzjy8eLa49dBP2iLDhUYN/8IH
1hRQpxSgpUu7ZEh4OeFr+Gc4klpJz8/UF2Mj8hh1Nz++RiU60HtqZejqz/f41VCVvVYAAL9ZnHqM
8NRPpD3V2glVfFEjF2zdwQJwBVJT4usrKvqybR4kZSJWfivt4qYBgyr4h/8Ztt5C6dLoGPdiJc4K
paz0HA+4qFkqBqA2e4n6IAXaCPAZ/zv7NSVKj1R7z8e6N1VuvziAQ9jBAbJqsRUpVBhd3JzthXBA
9ZbImM2tmYb2uTtSWflhyJl4h0FAHVfypmSKuNQjEW19tUp7IRzJrTd2LbKWNQF2trl/RTmiwPQV
o8phmgHw74nDu95hNy99tXQ8zehHe4G8DMGJwQe+o3WbYhV3BMM/NT0lAvG1hBVw9R25JFyw1znY
eILXPaey18UVMaCQyE4CHtOkGhzdmRsaxZJdOvXO724rp1Go88ihI7Dc9Pls7Lv6htl27MrAV+K9
CIYeASSB/pRki9gsT17/9S8l6QoHV54A5vb9rOEa9iIEOLx3lsD158laHnYRkNH5rc+zezug1T1t
0f5wQxQ3ALwgKsXcC5D25QF936razd4YuXZSelB6Vn28jOBR4rg0WxnZl40YwmH6Gr6Vj6WY8NFQ
SjeXvo5+mTDKXcW06zuWsuo42LJWD6hz9qTR1wXjXvrhT4C9LPuaFyCxP0WYgsubrPF/ckJb9v++
GzT6QLkm51s9exer8K1qgILHdq/sdnlBp4cePImveuu+WOPctKKqx+lvXbtmb9HmjOCRDUXq7f99
NOTBBm3rEzqJBi2RCN8xi1DMohUouFm5tMUItuj4UaC1oigs2UkFhiA7xj8lICWxhmEZv+euwwXV
3sOjAchZdP4hJgc9asbKdOif2G/gECFSNjqYmH8T+pPdz7INKL44riIewk9SCzXVnpO9bfYz0oPu
2VuM4tqxFxXAK5aMXwitmzIGdxGKca6VGOuo+IF+Iu7Ab+Xq4LI1cVvCSYtQsrXNGeTVNYwoIxK5
u+WJumbFbW7jbOgRNu7GL2ve0pF+STgeIIXxHKBbZI4aHDUidVYpELwB4UQzvv1w5kzLhySg+BPx
FFkyQK4dYWKnesWTULOziTGcfyArhh/NqmLM0qohnMsfesoTqtZRZx3dF7rm2M2+GMdY1D5ChqQH
738dHeVEbpW0KeKaYU0TN5b9WJL13PXLdPdLVWW5kLXBTRLeIlZ3ZPKMNxb8dEwAfS6kMB5C+UZO
UGwMenTFfR+GbwL3h3ehLx170Wo96posL0mA28KV9t6X7tIGiSE0MiCj94zlxDkgwLyon24PMUDv
fe0rlLQkJBgBIEBhfz++CrneOH2NA/8acr/s7K9m0NMYqIrGNyb/SPOGpwkSMLMKez2gvqRMkGs5
qS05dFrhUnaeDPsY1DWRibBPAws5digoM1u9XIIS99HEb6z2ekJ9L8WPvQxXKzJZv9Ewx5iHJZ4w
vtL4NMiNpThO4qR07dSlfd7A2Z0avNF7t2At7eIxkZhirVn7Jnl3qMCz4lxyE1OpZ1Yz13ZVJ4eG
U5DznxRHB5J0Gs/tvuIBVihgYZTOLuzpTpOtn2hkCZO4Wp6cSwW2zAk2VL/ot6rKIMdsp141qEW+
lRWL2w+WvjrQR7JF0+0y7ue9ezY8BBgeyfhIf4xtZghQBD5TgYw2bWcEnRfj3eO7btYUDlgVVV/C
Ohyp7+KtscVyeHYeJMBYJsZQarFuyaMGpLtHHk48QvmPozgqzPtH1hYdNQuCm5qSksr2XyL5JnDK
LEkdMlQf9toq5oz7X+Y82oWIA8pn+V//zWyhRj5zE92x4Ew5WI4Ca9fG+8kVw4b34xPlPruxHHim
3Vtg5JQ8wYxydx2N7yPrIfcv4HI6HGsFnWUcbGvJzKk/Ikkh57cAkv492KPzVmntBzS08EllI4LZ
tPIYq22E14FRB/zCi8DYkAQ2N8p4GmWx+vFHGStmeIr+cDQ3jydOOn0+kjJsbI4q3zbPJFBYII3a
6cnkdiPIQtaGwVynxewy9Dm7Zp8sSMg7xKrZQf5RVNCrhboeWeJojPCqNpKeBs1ra62HYVvQKIwI
ECSfMNYCsNS+QaONP9PWYvtJLYTb86RkFZV6+iyI/hhjsZRuT38f9fsLvFOvgV5U6OCdlwI98Eh2
qFzT0T4YZ1WLCJfuaXZrOWmvW4glGyz+yB0vZrXg/c7AOBsrghEsfKIWVafMJ/yOC3feJ9rTuCsW
EEUKUqUYGavZwzarHuQ/cZenKsejlHeGlvCqCu/6JREt/mkap5UH9vttWPs55r8xk/wfw20wPGUi
tMTm3GSwa924n4PifoCgsgGQE/mL608WB36uWCk+Oq/d2WcvWBaHsN+swJ6vqRwfafiIms6gVNb1
8KxnaD2r0xlq5XtMTpFtfUdwY18E9/lBQkIAhTg0DRU6PtY6YKFismVIUSe2BxnKdOSrruKyuwdv
N/d+9fW8dc7N++DZ8Ow+sc0XkJ3e0hCcYqQZvkniKcVQFP2a+I5bhSiT63JD1b1dkSYEbsYNkwow
pt8NmoeknrEGKadIQF83epbqC2vmW4fjbViSW9vXZwLOxKUJRDSC3fjLa0gpHK4cQ3/Mzymz+0ea
3jdqjz34Q6GdinNtVOT3qaVuE38xhPToDyyFPkApxcKi+Wmyf05nIlNQYoWkIX94y3uJoTAmL+wT
DR7FsIHNYuGAugzKnQ1JbOINC/twbvg3ZJot351Elhn66vw8vSCSfTSMqdJpKTzofDak1y7BuHUg
Emw3VlbmqCRL0wk94P4qBwMHzaiwUXvY6YXeRdWwqKdg9VDQP4FmoXLijVeadP0pNwmpFndmjfYn
40itNtChTFTgigeYOxwaCZ5iqnmHQSxBJDYPJi8iATw5LBn3a0iajyaUWQM2EGU7WxfJAIgs1vT8
3rW29WfMHUwH7iyYFSgfA92U2NvZXdLUF7Yfnd9596t0XU8XxWrDaFo0L4oqplJjO3ooKckUwyZ6
FylfWsD4IHsqL1lqIgk6Jl3FRceTSfaIRBPkXERXptnDUaNm/WLEyiI+bs8cSHEskdGwsyAYfRK6
A7zQ+LQdjM9tOy0qP+QblC+jh7O4EgTxU8Sp/ypYYgC+ZduZ8bJZJHy57adTNJFsKm6YeioaO5vH
9SNYOoZs6BHqbUuQaPj7tO+l7Jjrks5p7mwfx5e6xVNKXC7L7A6Da/hw338sbt4P8UdiW+Dev6NS
BjBkvPNa1lQIAS8fOfZ/NJrFzg4DR6yv0Qv2GQUSconY4zwdBkr7dc1ga1BZf3h6kmxf7XCy8NKw
LARTisL41T6RldG55+FICxsTFlpYhYKquoMdGJ4qnw9AM4DWaRCNyk3tX0uvHWGQG8AWgdfRKmNi
Jx2mOHmPMVyWeloodZQMaHgyWEFkH+tm9UaMkucSdTB4uf9ocnrBItOKvFyS7i8mOqMDfJhdT5bh
k7mYdof7rEAYwkQFZDYZNsIwx6YEuK7rB7UBIkML974wpYWg5D3geh2FcBRlsbof8bRYj/rI7I9U
PB6WVpUb/AN1sRFObj0pmXn/9Iqr/U/+t+4H86Sh6PNUt1VFvnjF3jpGKCn42JmcqVzGxhfzqWnY
SPO6PDjelDJAs0414OPBLpQaIvgfTMyxSffcKorAquJSbJ1v2ledT/0jiBAsQipwCp18keAmKOdH
ORytauLCpHg6TWZrcEhUjAr0ufkxqo37sDdk/RFIHrXtTJ3Mde6FZhLKXAd5Ozzdhk/Pz+nwCLD2
vN19hxEMNOw7zZoVxS0Pd/WgnQWkgSGjYIglWS7qR8KPYeWEB1NSMdkEfijp657xcXwPWvPJyXJl
ghSl3Zh62wP1HDPyAke9G56KzHeha17GZKPavZufHFo+0O2atXuKV/j12hAsIina3a33dLrWT1W3
+3cs/yIVVHn+dddGz4JCjSdpePptApxx0BIswA9+fi5GO9crc0/8//3sQU3mqxAUCiZoDjZokJdj
Ja1f0jibpN5wQxtIntX5KJiR2Pp3nXz2Ratr828hkQXSRaJBsVe+9clF1WGwYdrKIAi9qEmisyCC
+Xruxb+WYlLyTHsC3gSGPJYad1shepnoxpEoZXP5ubocsrbVf4K/+wiyF+/nSwvzOPQxHoKgFSKz
DO4IPOTTz2Bom4egVewcqvuoZKiwGKAr/Af16o1a7Rpx57qdnl1jY5pcu7Bh8ZPfguPViD/UMdrs
gGPB1urQGFuMtRGHEYvrUiTXdIS1PiDiLdlUHKJR3VIV7KkFOFleHT6pjxd45uu8Et2JERccsdWp
YmOeNg45sh61S4cgR9okBm5h1WArMpVMHBGU11Pg1PnD5VbnxhFtIdCHz5bhYZKgAyO3ugFgiDdV
7XaOHwl1v6okc+RHBwGAhHVmoISqdK9jz5zrs8m8CsxWSHm5TpqbQteZzLgVNMFGmVb5qEdjPxWm
s3X0RWl3p3/u4bCbNYBz2jP+NxdF/5TsOPQo2pH1JKEhCu7EMhG1yFMKXmUOJEKzKEd+VLWjLtkc
zoMvNGjaSQhOFPKe8j4thmE8bzMoivIHl2Bf/ylZv8EZITfbfEFkQR9tCvS/3twfnQ0pF1Xbvuwa
W6doRi1qOKjJ/8BqARfP2uzxDOWCAL22trPzTlOcBfezPqXR6UgoHRDimXjve/TTbZDOAO+LHca8
AqQ/jmQwYolhw2CPlZq/0Jj8xBJN7fvgp/MkstOKyQYEnqXpS12oEZkzh5DdpujoBDsr90bacaK3
ZDR4pwnEMizEvz3665m8WJlsfaxhYvt0TskPnp4U9oBJV9OytqWSCKkaz/9dnS2YFVkHB8vS6wr1
itxdetIpWqWjCA8pSoBeHle7iO+QXzle4KOWTQGk61ovsyRTwBsDfSPdrYSLYLJmzSzMwRwT3hlu
sY9NklKlZvx7cPkuW13drN2RtEDnS+xmxw1zoi021jGZjvOeuAVDvKLp/k5xJoJB41wH2RITbAQJ
i3jRR5vIANxES4ObaOfnSErGulSc+JeVrn/YcCL1whPOfJqjGrBVFTFq3QcbVAFKEeX4oDH0Of1b
J1Hyx9Dyq1JwU5Fh04zB2WsuYVnhZBwyOqXrHadaCk5ASq0yc6u4BcF/qbtFHXywPSLdxiUwKmfm
gqAOBe8A1BTJ3yi0/xvH3+bAhEnPJarGupgxOprok/XsQpXAFKb+SkXzYLRR0w/0RyDE2beaFSHJ
2K4ycYXHeIP9MA4mMgpRuUAUNAbjMM8B2znOmRFzzngfdjjexWd5HgpujDpf6I3DtiAx/LoGWRO5
XYWZEGqrgydzt4Ggbybcvyy5T/draXdYm7pT0JVbfI9rE8QTTBfkPeAseEv1ac1MTfU07N0oA+s5
l4Vm9QciTSOFeIf1dEZ6cI3gkhsmGTiGsCiEmbM5ywyHmEKkQmK7Pg5Hkc5AyCCigzCA/0Zxt2YX
Vp6imqLyWBLw0UNH/PV/s0qT+C6NxKCufh4ddyR8CIjeo5JMUn5JKPWcYtBwwVRsbJeDalFjWb+r
xeU0wzNmyWTMzCoHkqz+WxMq+5jmzeIpYkw75N6BSTWdtvbwsUwijEkQiPfxSpRnz5KfL1Hj7RzG
nFslQwkoi50QDvpBL3yLxON0Crv5+XptSifRI81ww77VTAJ+goNQDzLrM3b30HzZ3OQ0p2xdwptJ
6Hp0gFmMZ6qCRFhXIG2MPmKQZJOMx+npAcOIuYtmOsdJcuwcZ86crdCPycRggK0xHAvVllVzZcB2
Fu+wfQ/GMr9aVMKVKHWNWraaDEgteDOTVyQfxUf6tyQyt578jkbMIhM2/RgHdkR69gjn6LGOIb1F
/o3wLhVNekBTbjp8umJtf/+YSWH47ixE9rLVb+T9ywq0aTEq5XL+rr/kTf81rCCWBFNTnma05ceO
8N0OBaIHPzUYrttGuhXwtVuv81uWxTUL9GU/yFT36vXwsNvKShJN4hEE6QtwfBRmnexlchoxLYPw
TUoGGg/iF0SmGDRdXT0vB4n3KNgwgfy6DARmxV8G8cb4nQWbY0axmenvakJN6oeXhsTI/T4Qyf0E
TtXXnPyoe4I4owTYYGXg/jk8pFE3kLGYCPDr9m3na/QjbhO0tjm4NyOw8xYpbQVttC2IpCDcORgv
iSMzwH8tCD8IUI3ayWkhwAPGzLO0KzsL33HvnoK2Fol9mVWdc8ajtxGKJ0cGaSjMlDSNjWqPhsB9
1mwxlSbHPDHF8osBfPFSxtFOs2EcZlvreBa5XphDSIPc/w4oBbP/urtDq42vGm3Fgg29m35vwI+F
QbggGDN/EBEWz6gmFzwKhJf4K/0DxmZ6ZWvK5zlbid6UvFfLUIXFQZlpizQYQ8gq9cYT5FkZDwlf
gI2cmhoh669yIJWV8N8JBgLcAKZX9EqeRRon+z0FKDNVF9XBU68XlgYI/TFSXuJk1CFYPknv29mT
673YBVuS3ZG8MebG3Sgzngl886Y26CVZj2ZTcSfgFg8RmofQUNLPtMPJaapmmMybZDuzuDFl1q0n
7g8X7MHL3mAXcaigU0WuK4X6Km4LphWeBUIAUB279yukvhLWeBVIyeGirBm7plU1S3DSpy/+GNFH
9CgnOoSAYaNQ7y/r+7EPHk0+LigQlNmv27DzQSSwkZ6wPoSPL+mcjlTm/rrjxKI0BiqUMu2KSuBM
nz+WNY2sH61eJThxLxelVEx0YoZek/8kF+aADac+/Q/DCU91qAu0pD5xz66XR6JUhnKOD2Qsy7/v
4KBvYDNWl0A0FqnS8KtsA8xlDkRPJaHdhEoXGq7Lw2TKICGl6lLznBQnXoDt4D/SyTpu+n5ZOmBb
FnV+/1ChOEDb8uxOP/LYFPktv6ayxL8oE/fW92/N40Eo5ffdurz6Z1/oJZkz73OPpp2FO+IDQFSt
IjqQ2I+ziRjT7m0mifyLvUhz8zZRPHtkquYM0Z+Iovhoohv21ni4Jzc0R7b1o2vJwwP+eUF3JVR/
myQt1eA1luefDRyLSiZpA4faBuPnvD8JV+yqZTX1py/V6WgBoTwPaulYxYlnVk+qmGoVi0bjdse+
ITkbd1V/GG3RlHQsOYdEqyu5eJZs+6dwC6Ay0KM+vxFRdyQB1Ptf/nhZMZ3rXmr8fV/JlSykessj
e4s/LB/5EJ489opwefRHTGG06W3/l7YvVECDY4PYi6uTmvYqX8Mecz/oI1ZJgjxxFDn6aMKqX5YO
8HdHC6YE59XRtRVTaRF7Q/Nke796kz5Ox3/eBDEPaCxlKkySIq+lXnBgI2hN22sne+XFL1OeBqMF
bMFAEUPv5ggST1hztv4LN6JV+Qm+V7lV8xscPPzRLmMyMWdApRzZe5f6t497I6gqpJrdOXQ9pllI
Pl6V7guVcgofkwEL3Twgx52pKvvDQmEQHDVT8pUZQKfSCKLZessAgtgqu7+HATxNZI784AXIG6kZ
oi24ZZu+AJYCPvlIaqfapEv/aMR7JQwbbrA4lCAQyo+uKYcOaAtPhYFBiwHmVVa/dYy09bTQHQN6
D2WCxQjnrm57WwH3Fnoe7J2BH5Fzc9waThoJMMfn93+jRrhJbQ5g3tBlbBaaG08uhsQ8llNad85a
YDAva/+Z1rm95u+4Rvep/VOAbhOWgmkxJyYFh/16Ls755poBTX5OH0NhJDP+tj2hTxLpESSgt8x2
48X1yvydGlxAC+XHRkfnB+0cljzAlqJxtNuR2qUYkm5tRn4GEePYln3SDuPddprowTPNcju4zqdA
tZZ5+HDAITQaTYIUPpHRGCAcWpUMRU2k8LWfyjhRynne2EhHCKA8yev+saypcrjTWzWEIeT6xHZK
9Jpx7MkNMFZwlCcaJSqZrMuM0PK3tEm5fUwGt0/Lg6sE/A9bi5SrjGbuzKFwJq8wRHwj9FCZAmZH
xDcqMi7AmJvmx0kgjFq4tyBRb+MFGNcQFTskL0OIb0vOgqIgys95TalqwxCqolZgsbAOmK92QLb7
7sibL3oXxRq2JjK9Az9wDpoYiGpHTDxbjPsU3HA9iukRfSEYXOT8CyXQeps0WcOU8lr137ahZ2Oe
IwKG2hrHhB2UCuWFAreAxnxLLquPH5YSed/yQGzlxO33Aic2tj53TeMKtBT7DFxo7ZMdVnkIz+ul
1ouwIWlhTekNhwdyajrIk5tuRD8CYeFJ2wYuYfyboMj85nM5waXVhSKfL4piACDA7d24XKReoDnG
XLDqVFL1u1B3rZyLSKoxeLv9g3ZGpXWBO2T9AywOFr573dk/SrlkttZxTBXPDrUnVypvkakPT4t4
8XA2l6Fi2JmAQMT5L5j0TNGhKQjWKCFG4TOv/JVzMYUv6xXJ/3Uak89wG3xVBvIU8wm1gOTPxfa3
g50PCzxy/+YpFXK6YZvK6QrJUN4zwd2WEltVDq+nsajy23hNxkcF0M3KZwAcrbnR6YdtcUMp4Xpv
QFPBQqAjaSXcHT7j5IHtC53+TEUryhv/w7Izy4X15dmxL1Xm4y7lR6IZrZVE92NWw1cx9kPh2rkD
mKGv1M9mN2cd+vsdLdg7rViXoMvkUH7yLdZDr57fPatGuUt0Q3NLU0fGtg9HXKNm9PmbSRJ+hdnj
y6QXx/bsFBohpEwDDB/7umX/exMsQP9Lm0gero2+qGroH2DI0UH0Lhr4rPmTAR+u++6XuPBqNjZR
LvnV5YcoholXQ36XgF17/QYMJnGJW/MI53yadCOtVHKcqQDqf0/Apcke5WLd9bYKYO2sIbm2NyJn
BJcB1Og6WLkjzXvbRl4OP+EI1r9hu1wqSL1kpjR7HbKw5oV7kbsse921B+AW+sukLBzL868IKjtk
GWS+w0PXTxV+KdNFIIxClTtZEK5kC3RCRUSXY4sHtlM7YhnWWzBl49uOhOD/rZjOff/bDHZPZoCH
0g3BoIliYw/pTrvFDu8/+X2MbbEW86EXybtJmAKczNKHqjI8dmnBPOz5hjDhDs7G9p7am3CENdsD
gCv0KuSJBzf5DlD8RfNFdWkEcWOn2O0q18y02oyzX0DpxXm0zFTTJbFu0cCJljHFVhfC5/hs8iUv
OwURqYGoK29l7BqDEKF5asnyPP7gD2kyOCKok58FXyr5Cp37G801xrhlFZzAD4AdaWJMkihm+T4O
t/349/DG8mC4+/PDu66qLn2ovSpPMfpmHQ5DwKy0we7dH6Ij6ySi+Z9hDxaNjryajboUlimIAjqk
6FpBx3s1398V/xTvvxicyaPLwbbj6rAHtk4qiCIcHgK5K+O9BiUq6pfQMnbJNevdyRZ86Q3kPcbH
LNmbCezoTrrOUHJoWJNLJWpflwueYcN8bE6du+xwaQSaoadgjJs/71XrpbbA0KqqAZo1e1bkO7Uc
UMI7ujwfHJTbE/MSWZLtaRuqnQskxvHsDSx1RtqpnH1YFj24R1Jvor4sYaoEA9FUgBeG31r9sVWP
T4uq2jULA3qsV99CWfHGXN9Q7pO7x2FB+4dBlLhZ/hGGHB2AI+LHUoeBP067dCaTwx1zEjfaCnVU
W1PEgZuv8DXyChAWzleCH4kI9/RKKRDI5pb+8kjp/1AefJCvmSylAaYGpaD3Gfy+dFmCbAiOgeH+
Y7sZe6C02SSPFNyj6f79j73LQC+JEFkbN2yyqV+bGfw3t9qSuEB8pMJTshi/rY/v1TvlA/pDbRkD
EtNkdXm7+fbF1xVVkaV9fiE77vndCgZS9M+X3NydUlNW5Kr4wAkRWFx7hfpOBDtdebeSw1Ek9Wu/
zVLzGjQsqRVdc5vCjvPlgH0j41LFKC7TKdjL0FDUciG8VkmkLrYzPBQIxOqhZnQ2AXe5ZhdOgGc3
WH+YQ/7arH/wzWahi8v+/taYEfC34QYN095DSjDjcP6+1IiMsCckyTrJBnTauxfavbKBw89OYKyQ
eUPaRWq1ScPnPf9aRbc1n3rMyJMz4C9U+dRJIBGWdIbPx3LCe5zJW9W4w5ZHbpGLDeWif48BFFNz
UjhrAPcACG2pkscFxWInoPJDQZCcUELPrTTkTEmw8eNrNg+UEJRt0LntfLhDzX+XQOmuGK7NiQes
5QN//SaTWRg+spUEyLhuKapASY9KKC9A4FNOndDG/DsOMAMVE+/cwi0+OW7wEkmBqOMZRk0W5MxY
OU5lNFc2YyQ/KnzSYcPqsWEtqHLTH29+P4AXtpaCcvzHXJ+MBWM5tJEgv83LlV8VgkOIMdI/rgaW
w+zAQI2uzXV3bZVSebhSjRIHu0sbyh+E0mbioJtUXWR/97UutrjLW2unWxAsiNj+UbqsBP0pnyBk
PFFVKbeHmE6EI+x1xHNCvZwp4HlZdOWmmtuuVgkv5VNptvf3bXDZf+O7kVav3dwV4jyxWSgpwzb4
h1Iv0QpP+7ets7RwppKhVzwy0d5JuApmXTGl+DJYc/lczSHGypjSxxz9oJGJ7JBZs0IBWpY2drBR
RnZOGXOjqUB9QN5QA0tS5XiZs7hJzrCccDi0azCGXRgGIzATC+HMjq8k+E+RwZuQwNAX6BKPp+Ie
L6uzrF0DYW5RmnL/r3V0dF6EqY41YrA91B+QW7BaXD33c86xIxsE7JdGUDswWdJp4uunTT5T1hZn
Bi/deKswhnsQh57LBmKgnFJGjshv/rUmqG5+KNx2ngwwH1kI17hmNFK5pgkcM2ARuggYTyHMMJio
Av4CTTlydhMgZB1IVU1qOp9jE+SIwwjzcpXkgOhHWt0+RkC3hiPEFX7D7Z5y0FvG64YlI7bI0/MH
MezZ3Q8wQDlLNnWR8kz3/lvDvsv355Nu4ojp5ECxtDGud5WyQBxlfAqVDopzrfQEfofvm9NJSDNv
1C+zh/DtB9IIiRkqdFym2ASDYp/uFuMiLyNDOvvjMQtd0h0OnWDxMreyLCbBsqkvwg76StOOXwM9
jSFMnR1+y5IiaaK9IAY/2++lN/g4bbjrrdj6gA5nTQI2avWwGI5aZ9ds9HuSjUu9kjqqQdSw0ts6
qPWVEimcfgfidUKBsv3ED5jANnf1duZnHpXy7CQNYE7PzCdSl+UekyCSgn7SCuCq+f4APjWNhsi7
EDs+jBvXlo9/a05Ck2Cd7ddgJFzQw8mweXL8ggB4rvkhHli4gi3TdBONkBWNpG4r5Tn8/B+bYGdk
hJvGj1xB/7UxS6TP5kvKNdbUGO/3y2sDyhhaWfIbs8DY4s9meM1TfbgGCTlcvtyo4mVzpwl9fVWb
mLL/u4rUaT/4AJVBhK5xwf/0Ts6vL+SWzIHm27PNOzFnyGfnwz5Ff1iMYmMnyRSkTz1nPMx4jrAc
JQv3fh5gzM7wSivVFPlT0WZv38odrLTGWTFxMYZdWcLbAGedPaHtqx7zIP/S+7s4odRun4tGL2Lw
xDBlx+ZNU0MPNC9X7YznkjRAGuY10uxyLpiXfXD4HQI+raZwRpbdAd0eFe7/rEj13rTEqyeOjJAd
dwSAh77lEyNCsJ5zJA5G8c/1+W51Inu2LBTz4K5eYSOxfJwziYRMOt7RGhT5EIw9LvrtLap7c+Gr
t+S8VGUL3kIfMMgHZVn+Ick7tTNyC1LFJ3hzpPbey00muZ3z5iFewJ9jlmn5ivKRjbS4bp0SZhTK
+0OTLMRpt00yGeMA5qRgSAe+ygs18RWtgfTRrnIYmUlx4zkD+e1iIQiSdmPSvYwBVCrlcilyJt4I
06I/XmR/4AfRCqsc2mJucVfW6AwLn80tC3LIJeo4vm/MonzLNoHgKEEU3ODfpNUBj45TbOC9eQtY
lkm5kOaavsIc/ibEcZgj7CB467yQQZpptozvLxU5oXIYsnZlrHIrgDFWN5wrhwQXoI69iRTED48R
kZMlXJ8m/O2d46sny9aHiqI9IxbIKCekJvkoPqvjfYLI1IpRQ7ag252a9c94g/2XzRHBlPVdE5WO
ziE02QQJQ3CIK6whhDLDlyfvQDXbDKfx3OTitWLn18j3fqRoC/1VtT28KyUJVoXVUvIX6hCBAFLE
SOa9zcDXr+dRbNZC+0f4H1cA/67tvkVei1ipeDv3MEYQQeHQBpyhTKAZl1Oxel07GWHqTqTw7Lrv
hMoCEOmtTX3aq0gM5R+deDPvvLmwKgRM5ArC7wGpsXiSHlwH6ub8hVdUVDF8tnTZjX+cuAqw2RWR
DbaIQOWUxODZ32rVaJH8EeETZhpYIbPPm6X0pOQs5vBQ2pQgJJb2goMKhZ3u9zP/Bkpnke1r6cO/
HJR8jnCLuVs/hn+LrpbUBYqqNjRJdqV8bgbEmw91ZdX1P4RbVm/levF7wNevYRAbMERLyzEqUTP0
rYbz0y34wMWpocHBt4vKl28ZInxzzk8ZbnZgjTr6Veb6UT5z2v1/sKxa5CgeL/WB1veQrU5247A4
U1QePRpwovnRwGVbJFU+wtKwlF2OxbHyhrxn7LbroXdpmwML7Wt2ntKCIxB3iMMk+AbtiNevjZNo
U0VX2MmLQqV+jZVibk5Hlmo5etlS22h13+PvrbpRAekcmjUKkv7rtjfKbrYKWxit/3INTQ1JyRKT
BmfFGCWVbFXPhKqpefY5731k6vRBGx2psSAfNMUrnpX5d2qY03gVD/9QfF6tZbAXSfb5r57zTqnq
LZ1srg7A8u7KCx/Kqi+kWqYY1HqZK4HlhqmJ8FS8cIt7C28LpfVuy+rXg72jlV7xv7hFdUBawaXB
pLUo/1xhsodJ0nMLKRtZDf0XyOBB/i9iHuenNfzSScnRuQj4GffVVnVVreOcDeFZ9gLKq0pBGh+R
Ie9Pv8SMVDM6PgjQVOSMoCrRmEIupxohLcKrUbn8j7jl6veHnTmkxA4s6PTa3MXjbgNC1QTtVnMQ
wLf8a1ccJTWMdHf5hAU1SGpMAF2vJggxsLvOiCTude1QceRki+8N2ot5upOoW9dnDBYVqJcUlpU3
QGV2Ds078d66cGqemawwXMhHOfgwtvtRABM4dY0LbsjypkptCfPTgflC3l+L0pDqAOiAQVNq59Df
jK3xHmlHllHj0Jv2TBXrDAXV52C/lQnVt8NN+zjiJkVtnS9PQhLK5udDHuEXdWjUEN/QyY/iaOqS
PLlKwHomSdsTyVQP9Ic4k5CZVDshczM98E/Y8OuFnZYAqwfhpNoHyHT7LkZ+TyK96ditIYJpuIbG
XBZJlIJirYcDS7Iv7zHsGu7nACpiFUUODSyMgK9aGuPwwRYJlvGdtmXIXJ2F4chAV5LK1dvBOQMg
jFPopAOGfRE+55qDKGeZq0cm/Xu761IvFVHGBlLQJOFXgbv9XLYMP9w78BvtfEjKj9TRkr3xTpkK
AoLqjtqzIgSY7pdwRGyxVhcfs3pLTilzUWhQaMtAkeXrwiEAJBaNyChKhagOT4ZIPIsUNdjkC28H
RBCJ4fcv+o/Wl5urvUxTh2L0ijuZ9yesp/yoA96aK85oKUg658PHp5dk7D3dL8nULFiSu0eK1F59
A+j7ERSSN70qAMrny1WjLBSWK4YZqf7w83ssFqPa3JAV4Ueqk3mNpdnKFIH7jBsWChAbypbJEvg6
twoPqK3pbyaIZVnmEBRf4KTlV5vH0PyFbE4npTL+zu6hHDNSibZxHnK2qChNBLk183/M+tnfvzId
EpkSomujk23JTw+FRo0rEoCGdEWetkAcHK82B0v0ljk7RiHYwOIznd1A2WmMyWSf8YQI9mqVqPO0
ge2jPDJAnV5YrgKT/dqERvhK08FISaNT/L0OIoo0D2QpEXytUEW0bdnrfeNbgycfEgETUuxzIo0h
7949Bu/1iNWLzF/z1r/nQxxkiQfVUTTNHGYWlC+ae4yI+bQ+yoZuHuurTh9I6gmScI5AF7OrwMSm
K4wPyEqqWJkwDvAwtYKKK2pyDR5BW74PV2hhTxoFdCOXAqpbpTPZy5ku4CU0GEDy0JvMcxGIJJHX
306pHd5ukC8Pzg0Km03LeH4hg3dNS/27QzetC4AOQHKtfznJFupuT5hq+c599AEyH06uxpVt4kfI
Oq41j0bTCalL84hP6uCz/Tj8U9Z5MEyE395TnCdQXRvBGYmKinKH+o0qE5PxVeqU7ju8LbnOlsbr
A57ndBxU+mGcaq+jOcWeTSeRu4/15YS+ixCPij7wBx92taGrNltbS79JqiA1GID022G0cs6usqEa
HpkLzRqEwHp+QacTnTE4b2CoKQA7fmO/ghJVWaEeBH1MpbstUqfiVDrEZ3XUHHV2JySONRA80Wrb
yhXt340wFEivSXIiAXfBAvLurGMwQloDPAN3yfmY2xYQ0r8Bu3xXt7cJgNvpT+qy7Yb/uAJxjteF
50cde+R0auDpOzWATX/jG8tBtEGrKPCjW4icV/2/uySAHhdZACNmSkqaKct9piBsPDq8sE/Vhthc
GhZQ9PBKpvK1zua/mpUi94jRSqGTO0Tk5NwHEFgCSdKhUfwdplnyKt71LpwzJfzV1t5hbZp9HOwo
pDO/6PWNvXtTGLgdhMGjTMpnbUuGakWAcilLEqSADbcdh9phdcGQybjMhzB7vNXnsSLJDKNQbiqu
p8lVRsCAftwRG6GkIIrdTm60QjKAAfI56Iw4iBIZt+KfjOeCYLnqV0jTIT+C4ec8/gB6PCYBR0we
HF9fR4XE6aZYGuLtNXiBcnPsAOyN2A5wZXajGsRrPIpMbQqTQ7Zped8XzIdUlACBjqiP/ea6h1TG
oGvDqdV0CaP1MyDT1vgfU8pZT/6VTz6jfVMvEem/5PUdRn/yK9Z7tuh3qrvgD6C53eCjg4GDDq7g
HOkoZibXz+3qf+R3errLiP5LvY83funFxeIYZI1PCnVLjmnK8v4TyMfAo1s9lGDs8Tu0s7INpRjK
v/oJ0NwH2F740GbJKpPkniaY1vPWNRrkT5niLCEik01sfIeQhL8HJ6p56k6UWOEFM17p2RX1NIg2
9E0e60EEgFS/Jo9OrfqqkuN82txBgrC2OTVVru9oyIF5s4dq0T3WPRqop5qn4/W+KDZA7jdYoRY/
tJ1haV7u7IiqJpD93I1BaDJaRybsUFKOA3gWrSOUqJJgHMPJBJEjAjZuSF41LBHK2KubJf/0UY8R
Ta2uk1ppw6e56EMQyaAk8aI8MXTYXvR9k+fsSnlxxpwdKXG69o9oS1MzhZnYA5oIhHKMb6uin8BL
8sOvZ+rwQA9LgmWELYF4VEIYxCj/OZyoLJ1yhrVrqFzxj6yDV2jyRUYgOed5s6Ykya/q4UNXNRLo
NLMiwKWsWqeHdPHG+yBjjUpiSNOaYD/8bNn+bHpjbiSz5/ZUIYfO2AcvHfl0uRTT27xbGXVnTAQB
0a1JC5RG/VvkUcycr1/YnUQ1mdK2hs4rT+UzjEryBAFjUWxODw47nMK7ow5MX/EENOPQZrSrebTR
n/bNH951mYL5+5X7dEIqArHIp74OLPcXzUFRdpG4XnO5vHXYazWDaLbl9iv8YJCBUKuAS5iPB8F1
pN28Zo3ODKFmC94bnwWp0vs3SGWlGtdoFZY+llORM6sAtgRIAIy4OtnIUDlRh0wQiuFyjZMwq5v4
KI6btjTVU4H0W7I2ZZubFWP8MRMM9yM0+8s40XD6anJ7KtoV4D3zJEruzWBTex9mMuYjaBW90YD/
10VAHIzZq6t0nXoixR56iqeYOuP4JM2zwzrRL1s2/LMRCFWD2vlUMJ+jinPFWpPjxaoER+8VFDoT
XwEXmszNsU5l2vhCzEDwOilIMzjXVf9mDdQV3bNsvQC2H5/6IxfRbH7c7SaB1yjDUy0jOLIgendv
zWLsxnVSaIXGtR+ne+LgIXx0ODhFrmzusRyzeEbn4ihIrHoTbVOVOdqqBprdVnbYmDvNNTKZ/qoz
mjJVGV8DOWcYm2lRQPiD2CbtU8nmzYXOokz9Zd1MtWiYZOH8KSgVOo5KpGcNjVPXPEIoYiH0WBtF
nmCC4LO+SCKQQFirD67lrQNfpOpweYVN4gk5sGdbuWEdV+xY7kkHFCy89+lqBD+qZ+nXIPsxFUmz
d2mXmBk4BKp3qzkSXdxTFNatIIune8PzlX9aplhieCO/pw0NFXbDZf6L3KTzNg8axnJxFUghQ54S
f7ObgyUXrk18BdQjCmN1MpLXfM3KKhCqlbJd3Y/rtyby1CEZFzWB5Eh7NvUpyHDmBVE0F2KLapnf
hyMczKg4r/C65tLNYE1u7uWq3IQJfyRvgL6iMGh66P8kf4A/4uzhbD4ujxK4vgS+jAwz2pqHJSP2
HKZdsA6EGqKDq9a52ISNhxMwtbq7djdPlJ4DmJRVJI995xLoFeDnW40v9RIu5XnUlKqlTZ2Xyv7V
yL/vEywVfkefSa61IpGmTdG6Vb1Vr7PS1a8SjFM0RGqWYze6TTKRRrF3hHZNIu5Arvya3A+42SRZ
N4/aVTnEy1JhTM6B/2p8SD7KYumJfQ5sFCAXUSKlvklSy/9eplSEYId+fX8GKrFoFlIhB/HLFvYL
c5uVenDFGg7KhK5/SklOfl7VoGJK9TNanyfj0aPgfy006B+NhIBPDLwQrtrCMWskHrYiBl5HcY4x
oxfMM592LC1S197sIApZHSSW+uik4YhdnMrkmp1L75v+dHAgdoWzsfvzexRcUJ++4x9nYLMPJ08L
7B1i3MdvHebfVYHjXNpYqISDRnoIUvkCe7punj+0QV+g2dJMEr4dvaPkTvgnr6l5OByfa74a6ltv
Pu4rclPGFXer7DR0aEy6IEGDCa5IsNS5rfMIKvoqBhawTkB9MejpytZ7YOFTrXcyqzMKeFSgZW37
yJkzeGrnPdg9NH1i5Ss4+b8lFIVxGe3O1JZklpudDtLdedeKi/16nf0JhRKwWUp9oSsAc9Id7YT1
VCaIKvb2l8o+b48Ew+YoWzXxeJ75n3k5u+zRRyJru58kv/+4L3qEcAt+A3ITKblXqDxuJdDqRPJE
iEN0RFifQ2TWR5JctDBhZLMxt34Yvfj3bPtC+3cOqJ2cM37evhwTWYbP6tFLxvFAYnxFgFcHFRaX
04nJLnAELqgkjSQ7Wq+ZlPepKAyQoIA9sx8xWALxyN07Gbt8UHLNpqgjGYlDfMyz2McDpxxLdQ9I
aiOhfbvxuWWUJ5kwi2F0HMBhlD1ZKeGIi5EdFijI6w6pDKnrFtZ542E8OKLoGpzdrzoUd7vVViNM
gio/TUuqQvkX7ePVAaEj8uG7K6TY28/0C+w+M7IR4tLOk6lkZiL5dHzaFr6gtajCql7UFfFPs+50
GnmfUA4VKa9IkTwEVMglYGqv8NuVeyAJLDayK58OLSKskyHWVZ4X8KF1NrFHmw+55+vqY6L6Avjz
BO1x4q4wviuz3NHs58D9ivpDI6hnlvLAC63lESzl5tBK8cm3RVdnrGGYiuKjA5zafqPLQUou04M2
+o3XPDulzdqJR3PYMTEVt5WIcaKVbmtDEbcV2r6wy+t9jIIWceiJGLmHrtCBVB7FlRCF7pcHs4/+
IJ4ddEEZ5LH7Myk3x7nZYZ6CuUxDc0grMlLnDtUzh45eWeJS3JB7Tzjipq1ETw52A6xZhEXZk7Ec
qBILfwshMAkot7CZ9EByb/MtsmKtXJwmrwUg0JjPQKqyzVOJFavc1Ssd+K+AGSsrkALO66E7QzQ6
NNGFlQxu/f1P/GTcgffC4MwTn/+LjWzeVLGuhaCLrIFkRxXAPbHyVKTSXcgysxKonD0w5Q157SCX
cFqu62E6tuPLZvRXmOr2moqlfzi6kAJFzoQRDU+FAa226Zd4cJURLh4OVdE44aIBfvibHlvUVI0l
2k+HDXF8rZhNX025Rquw06QiY+tyZFcVqPKQTrViMS1HCm8rURIX5oFQGolOLTZ61WMSRQDizJT2
KYyEI3dq/JrNFUoE24hjcXnSdCweuH8zQJwNPKQOB65CcTj5ZMMNhPy689BObJ3HSZyfFzl908Wf
NRuII9yRSAeMBRKtxwPgTbEm3hkHm5z0HU1xBqVwLtiSUyYMgVHJ27APYM+Kq/tecn67JFCsrPDV
qbhGvLokMbi815EmITh+JvptUb9qe5h+8YlkHpWSCrLGhLGtvL8jH0uhAGZ53r6cWAd71UAP2lfe
KfkK/gkbSjjs6JQD4Ckkzpx6u1I/7h46/jqBiFdv15wXZS93avYNc8GzASnbkFG7yl9EeBeH2dyd
bpxlxFNtXWOdFlV4ckmHcpvvCjTTmf0VbODV0YAb/1jWsigRbJcH2n+XllmbOVKewEcGhXqWNpGP
uwBYzYstUsUe4jrAQn4p2aQYiB1FE6aBMeTNeO9f2eFzr1nhlzTFoZEhyUmDMvm1+vHQJZk8uWWm
etYlib8GYctm5en2LcmnlRfOIzZZv6tKeBBXcGX5J8h7wuPzOuaftZ7YUgt3kCHD7ESZMBs+TdSU
EStAmSWIovIumVxtM7oqd0aohhCkeuERQf4mPARFDqhtFwytmeEsR/7zmUeOeis79P8w4LV8dEUV
boQ/qCe/cRMlrC1fMErlm9WudIUnKqHTYMCML2DKnCxTccgsMz/KXINZTaOOCQGZIq28q+3JHjJt
rchp2CnxP5f8ZclUJ2pABnBTSdd2oL1HtniPaak86oA1vCrEX8/DestXFxQTyJREtGpKecxGDijH
T6c75kMav34Jj/rDV0Tt4Xtwcanf1ddcKEzbUMRdErPFZ6bClEYy5IV0sAtRQ2R+/KX27P6eI4/8
H9k+Mj81IgXDTyiVHRURnYhkDau5y1oaVur811I5HjxL3NkCMZ0lI4BEpI+F/arEavojgv0GW2QS
WHh8WaH24x/l03Kv4MgZGNbVE1gphi/JNWmcF+8c07VhEZ4Jh4fBbv3EmrAplyAvj55ZZZBww2EN
df7xchnMa7BFadvk+/ZIqNG5OebtC7P2+1hyWK6RWYrvGUiPwpsOnrPH2AqGvU9nuRoriaj+Ple5
0ostQFwsmfrnDjQLoLmcJbeFUW5yICXBxCEi34GwJ9ZIBzDYgkPxS7OgCDVU8U13TYlnvL47wcdh
vTwkLm4UwYzN5jtC9S5Yguer7zen6iTIdzZ8bjQ5IBT+NldUD/b/0Lwgm65M/Oc14/6oaVag0Jcl
hZHM/c/BcHnGnz/NnvjcPoPoCILtd+2Wq3cybjeXP63p0XWvL/eXiDv6JD6/MKwy+HXfSQYQrn1X
H5jPYu/Q7HnzExhKyCISpmRWKKXt+SOS8zH7s112TK2nUg066SWMKI5RzTXUIDtqjQhAnvF//3fZ
vrAn/kSCbVqXJhhjQlk7hzJzFE9eA4d/qM9XBXBVei7GZIjBofOHYkQw4qOn6SIpakvABVdY6tMq
6N4wsf1Rdyrg93CFkYdKS8R3ywd8hmwTL66SMzLwT+/0Iq11dMSporoOhkIeSR5jr/J4nusdtaKw
D9A/MDTGq6hyEkdvKUxupXwWDGXNgYysNWy5iIOaXVKXNeBx0hSWGPOcMg0eKw9LZ26F/9suKw+W
iY1AAItGEA23pbrIY7C7IXCVZvVIPlew8kmd55JLGskrT81NgNCNLaRNDKO1ippA0WF/wgFXts2t
UAXLM9347NJlLkskLVf2foNWG/xnTMLOfCF8DUdf8YNWFculILSzMB/xyleCOVx0WxQKOHp1Dl1S
3OLJ6HzBpdPiI7JDM2oKNvRTs+hJfJrHKUSve0gXJgK4Px9i99c5QbMhYiHPo6p3DSiA3u2HyQVO
4kvx2Aar5+oxLMLCqYCtMMhxuChY2h2R5SxVPBcEWObmDMwfXxD7GZMuxrxAFF48WvicQJs/L0/E
jtLxB+NmSfjPGzPvXm49ssYMgM82EMzUmB2mNUkRb95Rh+krCfmOLr5kHyh8FL6owHjRqVPf8Oc1
N3Z8Ofes93PoGCCmLuv6wcCBVXojF/UA5G74sLdN0YdKqwzGKBq055dsK0xq7Mg9TOgc/FnpC2O0
iNmrMd88z8ZJ3vm+FdmNDU4zaUoT2jmTANII2A2ZL7EmhwPBBarrJQEn1hoLHmsd55xng51EnEFB
ezpc9VHRmSRJjEttwBVL7ubbGPyUo2zkvMvCwkqM5N02N8UkBgt7gacV907KfuA/Hb9woaTEEt7s
effWIoL8kToFcBYw/LPqzS0I6pe2sKI+WO1HBfqzzPXMwnyrXYeubYp8t693EEGv2iWzPwu7yIjs
RP9ovYHD/yBATM/MZWXIb00tkOTMuMDULzzlegMnB0k6P0QzxKavcWE44H5wptgVtK/iRvkbS9xM
NnQLSxsJ48jums/lv1yJbdbR7jUA8mest/4k+Wq8X7qraXE+Hjb+NyLZvF2wAndBTQNOgXbxsQh3
ALS8tfGgNrlDcnWQNPFh3Gzxu7jRHEBK4Y4kqd7ztRS6HUvFljZzaNhU0ITCSrv9FtzuZyjVPTBf
dp1sFDmErtGscqbauMXWteTgkRlhXbqptn/D5WSb1xYnD/P70yoBAshP/kFEX8KMI/I9zTwiKegu
yWNQfZudBgeNgiwv2NTw4ljgOiL0UrNkNPHNmL9d0p4qWCg/5HFKkv5KoBmjQqaNjtjGTvXKUkQ2
3tMf0vam+6sJgK/umqAd0/DFPWCBz3/zDQ4ot8aNXOBYyg9ZJzR2GzAk+gb2zENIxr7O2Mx1+eDJ
EQir7Y21Tqqqf4m4MhXY+O6uY0JmF1tfe/HHfmyyAO8dEVGBMMms9ytkj8y6bL3KVqR45zS57XiA
E4G0c4ZZsMYM/GxJKawubenW5Ctis7I4iqMLJ5KgMlfoU4o68P8F8rLXWqjT5hMzu7GUo6YGGmq/
L5gooi+vZfpFdJZrHfWShkytPzNrVyQIMGkv2VLjRbsmc89TqyWy5CHSF2H9Dtt80/ustPZ5PFs2
xCCFPyyHrVtRIxc8DWlQilnxJHfRkLviQY5CY5534CII3deY1c8B0XCBifhMbnqcITl/sbPQTLnf
5OXzpvhy+qmZOEoflQ27687QPLDjGiIKmvqRm0TFncnaO/GxRD4ADnK9vGOlmhBL/mZz6EF/8JIR
sp1tnc3Jse+K2xy7fk3u1GXlWHx/NCCJJQ1OOXTdEKTMPTEfEKbHkQubhRjUOuuLLGJ46KVheUx8
pYSzWpDfdjQ7c9GE48k4m9K+f9+qehOfSrotkPnGvCFnX7v7v2OKgh3x0fDXJdl+hbx6HWk9qEB4
ScB1bXz3OKim9dk94rkyg1xc7u+Hnak5ilzVC6I/T7azPcjGjoU11U+nnRZN7iekFa0fHgOuTiRR
hKvu+G3n3UpEFqk0DYBProuNrgSxZOoQSzjcu47/d8mYXRawbZotYupKJ4WciemfbEp6Vq0srgL7
lJYhYq05pbW7J9CikRlTilMLDgshMucg5TaBGoBaOBJLbqs1Nm9MXpJ8bNEubVHH+ILWYpco3DXG
M44wrkGblUpdVpRQHrBt68ftwfSvxK9RgodG7w86dolTs+Vu5TEIgbzMXAeEDSEeU7V36zEHrA9+
55gzZU7hEt2aLilSIyMlyQ7KplwQe1atm95nhYvD7BTnNTPLb4J4xWhzkUoIxpaQ2mUAvOvPaUzz
IiNp+RFL7B3TgBDwobamAU4otfaP25m1WMaHLoS/eJTqEheojsnLMid4jYxecDaUdE1gGY6UbcIP
JcrUt8kDOfV8jlDPCihxqpvMgz0oWOxKZfumyCe137iHw+VZs5Mv3GP9gn3acCsS5FiVV98dOjaY
ms2oZ/Blr0qdh36M03ZHjBUnVwVLOOHfr3jjcYNfc4FYK/hzUalkWo6ISMEMY3MqMip1qdzn/jnf
QpznjBY4eY7pWHuMu/ziYAlhrNXnq1ZqVTFHMVT0v76rj1vKqnRdodu/GFfcfvihwp6ok8wpkje3
lKbhyU/T38mI6aznU/sv+oBuS8zviNP8WNHngXhdvTFyoi0QvHIXFUFFnPSpFOMFoSwjeBzF8bWe
sQTx8oIwhlmuFbx2qTuLGmKnx7CjRbm9FJ1kU8izaT3QHppBIQ2eVMTRYKkvwlyWYDTxMPgwkLqM
CZHteF+mA3rr4kbVHHmHQlUM09tgR0+lpcmI2em6qk+MVEMb10xhrhMtPDWAzmGvIZBH3M6Lceri
ZCZNrkaF1HoqjUlqf+/o+eEi5RtbXjcJ2vVRaxTUlRMt98whjvb1xJvNfKI880QDzSOsYaWDLpoI
KSlCAhPVatCCXfcFT01lXmwv8YIzon9zcRBj9ZKMwQmveb4qZ9X35fCDZsbob5WhmO9dcsg6T9++
eLdLtEccgojlLfQuvAeYp+3z6WIfvnzjFt3WLU6nIQpiESRKQ+mjWU6lJu8mnQMlrcWK6lm2kAZ1
Z6PyQytVFDS6Bsj17AR78Q1JNlB1heD34cu5k63awhdhOFIVBt0vD+/Nbr+EUYbsc+Bk3huYRr5o
BRsxyE7LwE/jZfvYjIc1olrhfn6x6ES01nzcfNH/1IDj4mUMycBNz1r8wfY2x+MjdzZ9pkwdAwcY
siSUd90ZDR0QesjA0/0djiz58FecLmmPVUwXiSE67aVUS6MQssTwXo8VPoN50pmtd1x5BegWbHoZ
iMHN8ISxvkCbDfkznZIX0cRz2ErI1MXMvLSQ0dmeb/SkbHOCb6rzvlieQY0U9zLcmUl85IF7v14t
mfoXvzt2FxhxXaHT2dbLuMZpOidV6zsHW7Fa0SiwCuddXM+YeyymI6wsOGWoaRcM2tqxfV13d1WN
XhrwgApX3eXlUCbViADYRWP7vz0BRRG5HYpd95Ep0mLwu3YfZsOJc5uVXMUf3m2gaWP/3jM0YWLm
RRYv9nXPhdFmioTCzdSuiXf4KZFyc/OENWQ8TfrMH/9mz/PtDFpmuh7kxRFPwSVD2ftyTNm6iwWy
xvS6IwaSBtGLXRtEWTL2sy2q1rSaYBNPki3NzXWjP4F1vwWsQlaFeYKwp2nDbXMrcgoz6+hAabvQ
UxAC0iC1my6tZZceUe79MiWLBQCRuegSBELe87iHD8LWsSnRn7mj65AAJOwXqh9u0XK14ZcGXNjW
jIA9zYjiPK1ZDMgXFO1Rnf1O/H3yaOp+vasSUStjsm3mQ21H1A8w5ww3JqrL8eag0dFsOlGeRnar
Enit7r/CM0OK0Vvp/jos8SmikfqOtTYoBTsx6VqExbwoGVr13Fisdl7MLEAS5r4yMYy3ViK7hogB
1munwwlzUvPE6YSRpTN4K/quPvSJI8lw3k59kEio6XWCBa43Bo2R59YKUkAm+KZPxIYbcMBvNCL7
GfM7Mb3wk6sd44rxb0PUx4WDfeunxjbSiTPtVCc/tn826ZHeE91X0Ae39llfRWvqkuSe1RhsRi39
1xFGKwc+D2L6GIyPzfU3/ofNUlmIwK2eLVI6cWga8LPwLNjycQmw4vIlR4b0efxwwqWEddD7ER//
HCqownl2Ef1hkpsk4bKapFtyJ00BIUGJH22M5MDSc2O/HwigSAJ1FBkUX7sMun5ID3h8/E2HzZJu
leqjL22VIZK23ZDQazMwVAC0gdibDYGlWqEJimkl/pj9kaorL2S5kwC/TAbUa6R8LODa85SHOSJQ
WLX52C0DyloKbEgg0lISWtgIbwpyr3MeqFGJ8XLtsRtWlTUAJvTCxe5nP7fB38iY8XmbZOAVgpRK
SKqdXnFZmyADMD7lxM5RzQYdjVltSaYd/Hg/krhbiDirKVbEGsav4EHhHmiQjINmVoVY1KIs0f+J
MRNRnw1o+8DBqH/beszj8xPYqq5KdcpiC44xhhU2QK9+Tg+L6CgviI4JlmYBN5TA0crwT4DiKZL4
hLPJwDFQjAtgLSWGtIq9eKNOtsNMr38oORqEtoBhz+ZZmVpLaBcKB059Wwpl/5mpQef27LRMDnMj
Pf03AiOfN7g67tdqob4qWJHHFNxLyLSKvzm0Zw4Ov7dJUv5c6jPTASHMZTuK8qZUTN6KxAb1ZGKZ
2yxB0pEocLSSuaqXzYtbYN17shrDxXLCMzTEz93vitoKxui5XmgectPSKVrBYKk3a20Rl9emJ7GX
LMKNYlnmkfcOB8h1yba7gf2qPSWO3AscRyRCfNjMuBIdLnsGnbYM3uMD5w1vbX/0aPtJbmVY8nvC
s72VJlL7wzYM0bx6MtWVo2EzCz8MsLVy9bkMPHE0nd/79sONdQApXBitXABbmcXX9b9b1MS9Bw3T
ItXlmfTkP8Ks1hS0CvlXUKV/X1xhXlITfBmQTK7DW7X+C6PO00dwONtcVFRjKcdgIYptdQQuEpzy
eYG55wgVdj5rQcJ/YQaQshKqGkCUY0r/FGYaI3Lqg4RNxcePxzYa4VvqE3u+wiGRgPjS6fjzl9Zn
hYCMt+/hp8UMkD5Agd9ZqvlRXmjok9VIrLQStMgtNy2Adcr0rRh43L5WdV7LOMlaw5TH7lQZWb9U
RxaNQwGYW/ibSzWWjDVMO52dazc/oaOl0PKb/ed+YZ5sP0A5Wg/SEzD35faExDImTHuvIjASYjWh
atTi1nOb6ghhgk8pEGYHyuUf+1xhUkhiwe35URmGAGuLWxew2zwterfp7zs8qt2Xxq9KIuLl3ha/
Za8Vgozo/CBxuDKppjxBG3QdLG92TGJHC9xbBo8U1lbh+bBdGotYn2PizdP8Nf2Dn1cZAB35CW+b
dbiuE2a9uAeK699g4x+24vRCheP190jHtrnIvHKDmwwBo12nVWfkzDz0/lOKgPtUR3jHhJo/aRFB
RuEUgCq82RxUmd9FzuR04lcJ1cf3z4lSuJUQSymgvNhmzkhHEUtd9EBjZcGUVTOQounbHcKExllV
CeyX6ck0zCzmvSlO4T4W75TNxzMpWhmsao2VUOhHWH9jEsL2h+fk/M8lfvZVDUtW0FXgo+taoRvC
Xj+DB/bjk3rYnoIqFqQWjh8hU9ajrjN9/YhnCAAY345mLK9BN6A6jtDvnnnVbweOEzyOUA57BBnc
WWGe33T0cYvY+qGJIQwyrQJgATMp3vAcvAtMrl3zp71ucNySevb4Ot4F+rCwMvRvH3YUMgVqPcRm
Axm5ubBJV0WctPqJ1xUEKWjHM11GFqbBZEl4qvUhT65AI4Mo0u0r8iq6UYtDkYuPuyfffJ7p43ho
UIbK0/7VdNPxyam1gDtNQvHaKactQeTl95DCWMs0EtanQA6qOvMquPErbpo8vJw/XEfvBqWtvw/n
cyduIdW4qJFVg/w0ndR8xA0Ci8Pj+Xk3eQWNANTTD2VBIBZXxL3Egqqm8YbPFBy/N5cenRddVPLO
gucVpxtHZVraqHx4niBNJJ9jAv1fSVMttkAGgnZxSKKQ2O5yEYRL8+BKayoVdHCH2mY6wAtXIiQf
nPvm6JHpvU7bhy8kOlWwZVwBTMAkqTIihMNJ+pjQcWHqC4Q+4jIGI011LfzFw8MkjNTx1rSCZUNO
QLpdUZAmpirV6UCts4+kWS6OlDVGi1unQ5/Q4JAy0qyerPeWa2CNt93UV4ejqprHb51qwcoRCAV4
vlg37Z/q73Q3a/nIhM+9gSAQu7RLBFOvWBTB7PLFyFuTfnqwl7n0SToW2KMlf80AP37XZu9cnipU
uxjcMazaKouTlfd3YDVMNsWvNEM915HajdO1bVqJgn+hRrelOr5MxyZQQUo4FvymQtfnNoUOaXWV
Qsw8SGZDdpo2pAHEYTyUIv++LVh0lHn7Mj4uB6hAWoAyV4RoedcLRzpmhJkZXnzaHJHq3hl2bRqR
uaCPrd2hcOOXJsOk39zI5nLUNsblyO8ev2BZ6B2b2BK9Xmp7Svvs0waJYXCMoLljpxuaapTizq74
tfDDNK37Gtw2R/Z07p8pSThztkXCDLpopQ5hGH4l2IRxNGl+lDVWSfvbHVpboWS1pHSbxVgVn/1u
O0CYG5ruoVYm5JYjJM43uUyR3EajESd+310yujfRq9SbMAesKVIJMTOwP2w2IWrV1hpDVZtUXXzf
cTQne8GK48MECa1D0ISKwX7YJ7eq/Gslz6N9ngyqIlphZDOsr89wx1SmkUtEJ4hB/tlXYJVKD6zb
5Yjndub4TDW0jOmkS0g4u6O2lmXxfm/ywVEjVS207XNLMMg8vAgbvqQ75+ZU9uwuEl98ZnTvx7wZ
5rbgICT/sO0TQQc3uEhV4mskbzhI8rppQxRc1rKQBxPO5wFs7D4hxWHlB21lmI6ftJfse7aBTB26
vbVLLw5/tYxR11/JNwgqFJNXZB5ay2NGU7jci1TZ3YkFVhv7UqZ1X34WaumqO1solIUzVyzg1vtJ
xcUW7x15JnxqAiLl625Tc4F2ZdzlS3f1DdkGRa+OJyL6Cw9d+4D0kZlQ/DfASVKo5USgRBBFocUl
yK1Co/bWA4oemcjja/R8hcklGUPJKU7GsOdnoHgersEQDa0z4Z48JUU3S0dSBrGd28As13qIhlg6
5XnRk5hfxWaNuk1lbL77zUZsePKHL8ST/tRKzEnGr0OXouaTbumPZKBCgE+KlR2Rspm2WG4texwL
VnVRAckmGahjvY3IvnE16asM4GL8In2lizyJ0etnHggiWJjVPsSz2YAGQBbXOOhA9NntmRMbozwO
w8l3IIWPxOe2B6g/VKKJb3R/YnEf485FV8vW0tORIpbdDD+hsWTws4rc/cqaVYSJgYgZJ24iJkb9
L1uB21wMkj+YCMWNYHst8RG4qkJw8gd8g6rsz4ONSNrg0REaokel/etjmxXpCrDFoaWoQZYQUurP
AR1wizZh7ps9SRG5gccD1H25HG+I1uuVDaIktBR5V4Kuyaqlb3Q3L37+HpWdIjYvT6UiblfsiO9F
dUP+wp2L1XOEDkdxFlU+X+iweHzYqLNh5WG6RdDkpp5qK7ZjH3UbYTXiQCwNzeWrIqtK/2KKg9qp
hIoo7SRpOHdhZu+s0Ea+VaZhsU6b2mNBaXdA/iuCwbcL+/rXTYCPbZYXDmHcqF/TcOPscCcpu2XW
BrKAX7J5g/crsX7toPJmC7Ti97xeTv4Yk33JiQcRYeScFO3XJUd/kFHWkDcgKKUqpkpiaYd8+Ydf
6oLOQBESZvrp7RF3c5NnKVUejJPAHw4ozqExmw9iCXtRamzxNz4PtCOd9EhMrPICUjb6NIpYnpwA
tZgVNs62xpcZfhC1xseWKgDTZp+5N/MZ20g+OZf1exiWg4AvngHsuyCcLygxMIBc+1Onzk4EViUR
DW8qGvHcBH4EdScDRzpxEUz+cQBZZvMxMycIeuJp/jjnPPqTjDen+CeVzDC7brpOd6Z8capceEz/
yu/zGszc92hyZaKrr/Fa//U6AN3qjAN42MnUi0qknjW3p/ALp5FtFK2JwbWS/PALVOakXPbk/SEI
rvfaaoDyKoTPfLohn+k/QsXqHZ69k/6XtXgHmknAttUJhfPnLUDu+Z/H0BAbZzlQ/yBJNtiC7EEg
myLQ8ioX4CIfx7OfqQDHRFL/lwkZtub4wb14EsH4NnQdDOzXtByijOiTJoZJ4Tu5O0BXFPvPkzLx
is0pIj5+VhcdBalL2HvE3mY5oaBu32jcOQWXxUhXpGYF64hkam02CsAKw4nriIoxuKPaL3FFldcH
yqlycmCn+jTY8sKGlpfkU4AdWIhd50oGM8ayRlM0xkvUADrrtiMDsUsAZ9PGg9mE0OBWLEFMCyFL
l4z16yWAamukXV0fCUZXsLLNzCq2XkP9xZKbToh+qFkC1p3fbY8OFe/NWTswdt5whMCHTSdnXh68
JKTq0PAzJBH/GfU2m2WdEsUgnEZhCpvuoKnpXcKFEGKBySJsewaa5uGtj9GdOF1eIk8HuMZyaTUL
SQV572tc85K+q1bcrivilTsW24mTLEoWwQqrezjzl3NIoVJdsjJBnLchuqoSVZSpgnotqILfWVea
ATS14jb9h2sQQ5Ri8EoQIH62aRMAU+4ADmLRHWBcnbytKfokM2ggtkZb780NvHW+The3HzYeiF7R
r9hVZYYyslBnvYP3FD1bzUcxv6Ks5ECuzPdQZnyokQhxjVVC5wnYKwTvCk6bCXIUCqVMFoB0zGXG
tKRQhPwjHro9wQw98psqZ/F9cn9UuTP0ZVMKLPCMliX0bDdL4KlKeUVLmvImA+dbJBiVbANowB+e
gI/btUwiKXViAvcgQHLznfz0toEs+Q1e74646UAm4efP/uDxee7rE+tR9MMuMwA/PF++qGVEZcPY
4DBlvOTr/4PTxBO+C8TUJ73xpnRgR6rzzuJCEjMJyuz/r0QZz8Aq7x6umAbHlrD+9Ask+xv/KmZF
CpgXi3zX2iOt0Gk+fiYyRcs/nyfiXDU2iXjWJfnjY+DyDrdjzoeES8w8ibln6+GRn9A3tllo6iUW
PigVufsVNEZiuvtOXPNGJ8YO4XgkXDkApvJcHPBaGU/prXOyblETyfhYjoo9C3prDY8EsXtYaQXa
GzJ+I3vPbJ9s/8RsU/cKHi8tc3rt3pKdaIlaectdudaNY+oUeKvfQ0vj2QH4M0M4tl4xtOiUFjgA
hHpcP5YhqlM4pyuz8UGolIqCu8urRmmBzRL0mM9XoQfFt4jkyI5HVRQ0P9/sROmAupLnb8xb6JxL
Fqk8h38G4A60EfX+eOipjMfdBFZ8Oozva7NZhxA/Oe+2vPPZPLOSvp+lRTi2XPQhCkXfxajyoBO6
8hVyvEuQOZw48Kf2vg/6NRpYaX9Q0xGT38PbNELr74tkkTsNGy4EwXUKus+uUNrUnHKukIxmYq3E
gZT0ZwLuyY3qij1gOpxj4B6/79ldMMTMS+oOifH375y3tOGHqhIh46mnzbsMoyQ6tI8WA0jlzucR
6SgURWW2btSFBjowKCvk0X8SR7H+mnmUyuXcpcG1tZ51AO5YbGI62q8j2L14V7NFgJlVXAzukHaB
znldI0nAhYeNO8PavREgvCgp0qfl8efd3mXC2EUxY/hJ0tqJjfCW2bTwcl04YUN0l3UxWybFwKrU
WPJxQ3r6JO4uEGVXDpV0U4Eazqf2Xg4awKnlb6bb/QF6YH/7WMn8RSsycJXNgXMt8uSempViTGbu
OuXaaUcMdbM5YqUO90xt4HGW1iKOm8q/znP6KM4UaRK8kkVqTTaW5PW/xnVMrwO9c2X8A4J1iQeM
rGGxWPUB2TabBgqWGLQVf6b4XSUdsGvFAUyOjQEmb+li0onm+uQgTkMhlvPlOQgCRGXce6wdm0gP
IYj8VNpmXzryR0jJPoALbvT3dqFxKd3de/wsMKw2O4HnSSE4Rjrg5I+aXLf9LPR5Uj9iru6Uv14A
HAm0sVXRLPO7nYyg4WCVtoM0JOaZOLtOfT085XtiexIQy4V4psundYvNFpO1us+qT61mDSBggj3K
YgJfao7vvja3WGZzcUv2R/kDQJwWVbvooOUwyMlH/qNF+lHdbh2grZ7I3hPP+3nMcbj4fFBquuDg
ZyLCyaDCESQAFaCeypBnIAAn9c1lbOCOPKCHa6U75/SM5RzI9z6Jjxzg6MlVyYm8GXS7EWqZHWUt
TQO8bNn4qKX2xcr9kfFuUcVBS5G7bWY87CaLPLPRlmELY7lkRoAQc0L5i2J5gYCmQH2ehGho8Cwg
+1gXd6nMAyF7D6HaWHIzYhxwh0nTFRUu6dZs82F5/unTkGPhqtNNNrF0tWY4310T2Y2XzyYAdQWl
JVGxdeJ9eElbSjxwvzjMPe3rJQ5BNErjcFrYF8Xl19Bjj1qztAkD0goPmAwH8v/HsRsKOy2meb7T
iO8PrRGBcbNF0auJWt5itRUKuk1bWqzBCcIfPVF/vAi9JHBLxNxiqzGdQ/wa20x5qGrxfENTX6vr
zWs4mZoDG9DPIvLTIH5mIez4mPO3vXsrYihMJhgMD0owZangZBYU5GBTOTg6oBvfqXv5Vfs+TL0X
RllEm6rrO9sXTjOBvWvot/6y1r686bTUEFDCSLhFiMnISPBAwIWYR1AIPB3sakcO1Jw+T6bq/Mld
mB76/GILBPrCV2XBxjWeoU09LeU7PE0+4mowOzZrjFwWb1b+jpuQXT7EhcSqj5FsWTq0lLway0sO
Ry+3BC3oq/CbbhFDm6I9dnplC6F5LXWDRn0/2bn34oUESZjCfvDxiqyao9dqqAMu2uWqEzuAYnDM
Sd6R/VZI1Qn4dstZ44y5mvbhASwBWUnLQ4FNjjKlcEFtY1kXvP4MJrTgWzNz1zwPBltY0byzrlTv
kJOdy0OGgJmXcvoy9ap3g6onKALiDQWZuIElgrD3AV/et2Z/uNrp7wZBdwfaWa55tLE/cZf95WTO
ejrtaAI5VOSFkqKcKkZy91hDH5b4R/c0syV4yluMmWpXBonGdggAzRiF5kxJYEEMQNHG9HajsOg5
XgTjUn07uTGn1/obXYc/YSqbdXwBmclJ6OnzunnxxvnAI2LixFqVyX2fEcj0E6O2UPWjEELkx7GW
OC510QuQRV7kLDBFHhBouxZYNhtwZ09r03lgHki7y40T9XqCr72MEjbFIHqbhvMhFa0PDMSTRViQ
RBALftXhW3RJ+mOrq1taxUJSghnIamolILXguAtKCkX0/M9VhkQ/W5DjYa2dW8Xgxm56PFivlAiE
3BSZCLJNJFkDIjwvSJI4SiSuXUgyYI5H5LYkhUHp/dUMfBBVbYbEEGjn1stl3fQhVHlQsAbtqi0Z
BWeCmY1FLX9JbbhGr6qGnRstfn+ibI3ALkPzA5QS9sEZK5GTvzI0XBwmyk6azzIiALgFSyPCGOp6
U1oNprywh3zYtVMh3xKDp0V/Fv3R50avaGShQQxc8ZvTPLO6M7E5J4N76cjmSkXV53l/tS2LCyUH
TCtuL8ztEzPBsg9NhoWYolB84tMDLY1Chr62D1uwTicKch8oXlz6aCw6cLH02t7VHqvMn4Cjarw6
lLK0Q8PyuUSxr8hZc8waEnLYUgLckCc+4BE4hiDrxk/mzNYUd57XB38f2j9FLNPySzfPqhsw3+C4
FEenykB9MyIsh4X7r9tJA+Aoo9+bttvBdK+Hz12MxDwbc3z3yMNE5U1hqsgLS3aIkrFUo6GOoB14
uQeSUbLymIJrzt7uNv7KVdTjxaiMj2LTZyiVzHME3gVMGHP6LKMENfMLC+8LZg6ofhVL2YxQWBFT
PccXmr6YSbYFFN2hw+oFHyf/ib+mjq49F500dOpBnphYkrhU1kUZH8ltxAg/iO8q5UPn4US42E/q
8d6Tu6Pf3fVGsYCOX612oDqrEhD0J8jQpkeQj2j42Yk+d5PP0QNES8j669+mTpn2m2Nb7KNvsbSG
NCGXx8bt+6MH1KQCg0vCUy+WRxg1yJugfCHDrglXpXK6UDqcs2BcQgzftgf7gMtaE0za37M0XbZW
pIj2YKFsTnG2TxxFCmzNL3ltPD93FY+NTAkeDh/PGTuDl9M28bqIeSiBOOIO4LZ86Rlo2hoGqHPj
DldHx7JqZrM63YtZEUrmgU1cb7t90aV6+GRX7wgolmwU+QQZZdtZuMeX9++nBe2wfnWlYl6pqmfj
AI8l43PsOtVK95UoFW+4tFGYwcVrxrnaVdMFpraVZHlgHYAukkzPJ0qbAwrYARMXvHpA1vUj5Qlg
tcCl+tLfmugtSjz5faTG+ztkn4WmO38frU2xmzuZUz20HtfzGS4gFv3g3eo8FDaDrumYliXXiUs/
XIeArGHlTvCqs9VLFlxAa88cL3AP8aKTL8jacEenGpdBnRlO2T4D9Od387jDRpkMv8JSwF2Y20/E
z8lVpmpClALE2kGPt9cb2Pz3K+I8omGsdvrA7NpuMi/pjCEn7RU57EcVFEykJvFraaEdSZga1CPU
RDWOrX/gIRrscKOTA4VVGXtMn1A8jkXSTG0qJn0oyWHPi7rPROBxSJjSG+1JVrc7TIfT7pY9Ym3T
vVzOA3Cvbexcc1bIHNMXNdKpnpZdfURbKXhTdf/rifMs/e1MmtHmlbycKsi+2J0+IBSNzQRCcY35
Jxe6LZL3NG4Eqtulxo4fI71EUce4MmKIqpiQdT2hYfKUss3USgvGUNOb2tXN7ffDezPGNV239lAT
J94I0rz7c12Tc4TNR0t/8WQDMBKQ1AJu7qs8sQTslXFyZAGoY4fWmesxHPWU54khp65Wcr8nWqs1
OVfdAjdqAHJ9FYuIstAmPWD0YtIP+EIY9ild2NtEgVRomjeMtYl1348A8EPovWykjC8LfiI7u8Od
B8zDoftDHO7oVUusXM8oIsX371byS4IiPvVY1cqECovmg1JTEmyMhS9UKLHvuWmeDrIZJP4ODgfc
CrMhVToN4ZJGWxO9/yI4iIBuaO7u13N8lPhhHvXb2tZaNvFmfXzglXpPlbbRER2C+kmwn9egymKt
k6fazfzQwST7/2iyGLWfRfKnjTyMjsnXUclR4hiMb5GqKs3Zbc6YmQoqzgFkg194fyZwRyMkzd25
mYf3eHUxDE2ggRQ4ZZdGIeKypJ1xlyiSBNlMGTG2AiO+xDnDNNPbLEolnYTBLoXP1YwpHoI6ozTu
au4HWS0JEDpw0QCjlMLoOwiLGhn5LNsDZaqXK0FdGFYg9BEbz/mSgHtHD7BIfGRKRqIHHFBy3XfA
4320fSxg+EqjEol1nTa1yKRlVP1cxd9FdM6RBqRxur/kuBaeV8Sm9AuRVyJuOOtYgYRC8Jx85y13
Fe26vSM+ROvovOpcLfHhQ2BGZNBjXYMZES8pkGCbdRjyfVrHre8qfmLrzS35Z7+aK5d8gM6Utq6F
3NTmpDYKJ4AwZvxT1S4NHsa58vpiRX5DEyYpbe0beyhhoIdt5xYkU8s1mVKk+4SL8ukQ1nZofb+J
6PXmEASOuAye4O8uZzwcrS8kMet48WfUXbkI+lnEmKhd+qTp6exokWYo8AL8oBwHSDldNwrHIGPF
LbFLrBmD2Ap4BNLDbX6E5bYP3KVRtvc2o1PZPuKZ3fLNeFneUyZZpwiCViCVx86N45gQx3QenytA
FBlTxEXtTHvbHDQAS7MdDBSx1ZMJcNyV6v74DJraYxCHzeaUqNpisIi5Yq92QwPkiihY+spTx1Zt
yhudWn7ujHHEU+GixltObQ97Xu8qPt1ZOIgMWmxO/EJJH3BVHOyG0cu7znbA10IHZ9BukZW2w+oU
PEalBg8/G5zvhq9JkKfAC89HvjjbnT4qivA8B7a+aQgJsiXRff+mgJ89oZF/+L13pQ9ipo9X86cc
Ag3dI0lIdZb+1uSJNw2YWip7KAyrfJuPF+Ks5gz5xcIyyMjhCV6wOF1gqsPkpDtnrBji0vox+UL7
3L61MroJ6MO40As0lZYdCSusJPhCjbI9vO0k507UUDTdgtUGL/Ej/mY3jptlD7Kw4hr48BOjYVuV
GXBq1tjhgBusXtN41SF7BPbEDibpYtcFnm+nScBoDssXMEW1M99EavFRsR91CbbYJy/OliMH/+wL
ls2YWDiLBl6PZbxcd1p6EWFlTZ7/n+4CPV2YftwGGsfqixhzaomOmIxQ8E5SFfR5x4rj8TpQ4s3A
4jh48dLdScDAmyygkmuxqTdX9Vl5VrLqyskJ7jgiGhTblpvhJopL1VGV6k1oUsErWliEywqfovkU
omQbfUpxMjogCE1VizmoTEAY4c51gGQ1K6TBvG09+xP9v3ck/dUbXrmWwpN4p+cyf3Ir2EHG542T
Z5arWvSPK/zKEMo63dgY24cv7URIgN88p1SmdtGmqEwSEmniOILLTTnD2p3ITeivrvOe3giF+uGL
oAseSiF3vXCzGnUTEHOp/ys5/60Zk+jfRQdQpEwy1vm7D7R/+qPldVnOZeQL+/AGd0XpdR1FBaFu
CVn3FHKqoHPVuWfXRAyhD5A2KyRD288oVaMqgHFPahoO243GBdwKmTOVaZzqRbd3agJ0tvEc1HmW
Nt2Azml1FBz2wqhj/rBK/cDB7Vct+C1QnwTqhsStTJA8fyezF+YH+BHv1B5dw8tTF0VMW887DAzg
dYZJSJ2Ll/9DefKxIw+HY3qlTTODRkUeMSNN7glwkm95cCHLbfOsHLCpEfRTbWX+X6dr+wvVBtAC
5yyVGaR/dcjmyChMi6YvYc/QwF0b731h6iuHwNoVrltMU6JvekKs3/tjnzBV6QbcwXM/+FbOFYnk
wYZMOShq3hL7qtrONzrTekUWOz0cNVFcaFGUg33r5jOWiOENU4hAeNDqeW+ef9TYDPPQ18jyQYfV
MNb5KxEYYSL5eiKbYdnALNqWh2Sv8YVmwwLjYP4GV23dCZJ2qDVUGXM2pTZyR8uNieJl/7+RPoE+
ISHRFozPZc0Ng+H6mhyTHMCny94Zs1kprY+G98Ue6mQ8pCojqIxbVVGchVfwRh9JCSkWrRP063JF
ht7FB3WS1hrUqH7i3ddZndIRmqmFilOHhsNtTXl7VBwyGFm3d+XA+TTmC/ucXbKsSIhU/tMijrow
H4/T1JNZT6qiPuXrE1zYhjnFtptDwwDboYpvSiZhTygFrsgnQVaGb9A67PTyEkmRuK0ZiB59Nn5E
TmenuNY3Shl7nOh/JJzVS6IuT11fZQsOeN3QCTlqCPfSTJ5xAVdQuH4zYQkH0IGcndhud3ez6BjD
9BVXfXThdtwoRw0LDiQOwaDEHTX24rsZBy6VicVaMDWbprQq19Y+S+B9SZpZ+bNgPdykdNmSxh9T
7NjtF6HFJfOzTKLYsHS/UIJZ4d55fCvFLEzOvxrpaxhi7BZZUoV/aN4Xqy8ACCZkdyNhMARhY+hf
8LdPVlr4c6XXg2v4rS0YYVXtZ63a8mDUuBGC4fO1FgcJvy9J+jqpL3YGuyY//Nb6BLeavZwRmctw
+RP/zE0yqUDZlnA5YgVb9kMONem3F/WwrCRmZyy+Ws3ibtZ5WhbIsd98UkLOLvDr7ZAw/upbEvv3
OmEGqEDn/dJRMneYYvNSGa8R2ur65ooibS5Kso6Cn+K0cTTOaEIR3NGV0oz5K/nfzHrrF83j1tk7
flLd6/MPql8AAnDf8cfN4IazMh37UGSBB00ICTYwzHNsNXk5n66Yr8HKrL3fiVgi37QmVYVrL4dC
tzGQ2+wrAIWFChqSQGfMa9x8J7LiSzCOpalq3pufb44BqXVvd6B3oa/3AJ9PyST1V/JNJQPURWxJ
7tbb3DFlXt+onBi8IxAOetLOBgmEzkrqQf6KhmM8z2P6dCBxepgHZsR0kj+s3ZNTG/BlSLWSF//G
cWnUWrsdxUjw4Rh4WGTTTJ+qmq3QDaJ6NOghE9XsG/UxH/cvjbGCK8apDKB9gpSW7b4vkLApQrmq
lDmPELlnwloSgzsQH32eDE0Rf+80eggDnbTCj/eOCswo+0l+wEKAxJOhvaGcq+PxO+pX/K/VtR/O
D6MJ/hNpo8dITIB/fhkl/Lirh23qg25fKRfzcHNfj1OY02l0mTyXNcwbXZCrYzSIyBQ2XZ7cF954
OlGmp/5yM5Fzy2DThEJNd91Ebb7echxK+2tVMdQgTbDV1/NkYxUzj0dgvk0vc31G9ZOiME1kDrtK
xV3JUk70ujqkFhXXzisfJtDQFNkkklySLwrXuJaiu6CjJEybgWJIe9YXjQkFl06atXLOcLHJO+QN
5ZXK/aaky7B+N/jpH5O+ThvUpvfUcra7NciwdYt6hr6UzKHWd4k/f0P7n5NjevSdw4kvIcoqpNYQ
3DE1Aj4VBa86ke0JUbVrOv6e7f+48XBXbsl3ldVi7pHjvtIlgJXNQQIWIaBWMyFwsEpiRuAkQiZc
HS75fbliRr/rTnlJNuH/MiZadfGjDbSfW1tBo6zmfuVncsybbPXNuDu9fr4lYaCq+NFWeE2enCqB
R7C9iVa7S7vUDGdsrTZg0B7t/YMBnl5xHKYrhJvuBa7yOB0tX12619vo9m6vbpe+Qckz1eWT/ueQ
juhd3Hyijfch+efX15HJqV4BcN1XCObHcN7ozsUMM+97uAYZgVmC9nh2jtLsoc+sF9SLxWr6M29t
JIdd0zPoExy1aHFM2TDVcxTVwSHEwPRw07y+8TuEeWpWgU164rsbgCS2rcu0U0nd/dgz4T01T5sy
zbsxGziQdRiYVkqQSROcF/nHAMBE/T3GKqY/yHKkjLSQVxsuaweni8DBYsWLgAwJQY4NyLbIURqB
dJ3rDsPpQs3gYW1QOs4QacWQrwtXigUFgzoYhPwnOqbGXCR+NxUz6Sx8G849m04J1FAU3p7z7QHW
KWtxHTEv0Wut8cIsJqaBUP5V5f1pToyxxBfUCwaGD5LJkjqui5JrGJGclviWp6U1SBACDBtg62m8
XTic7BsctUdn+Umc9BI0ZEw59Bc8Y5oMk/rRm058pbUWMLahW8AcWu1QeK7Fek9ZLD5R8XrrzMWG
kqqWxBHPidR0vsTUdVS26HX+XrRuWEDkTUnSDquULowdBST/7h9SPa4g2janetQ9tmIgFkRLMdym
u2ZA7XA0YoTHPoaJrWN42DYI0GoEJQPlcv8tCFu5Kt5wbqsCZucTHNgc9flgIQvXYbuWXJ8JNQOx
Md7ms3DksaF9sr4L8QWM5RyXjoDjfqOljD4TqKl60t0Qa6yPf2s3pk4mHh0s4AKjzpz+RL6le+78
bS0b8hTG5oHAIwgvY18Va9KzKnw9s0LfDvsWj1XbnmcGVqc7JPQcz45hR2OGL7Gbqc1VcEm1CNev
LG+ivLC8BeczoWAmliEknh9kjkYD+8eGcDmVZFZOp/KduSnWP6UTbgVCQqLsPMzx/cspBTAh+32M
vQsBo74D2ZsHpzq6oxHTRavBfycAY+k9QR3bLRqeLxbJtMAxTkOE1p1Mmudzy4cddwECG0X1lUkH
daKBOIV5Zn7BQffvqkn3cfOmcCGPsgpkKePwIFlK5lGWAkxRLNiLucx2itdnFBnac3p1VMyyNWIi
YzUtsTf5jbmXVJyGWnAfZ6taeWBimUf8fPiSHbO4NgsoL28TxQ5BQLru9xzvhh1sr41OjwVuUpJI
8K6AdgsX5E+o7M8SYBmzhIfWFs3cyVLmQwbg0vfCy2ln44rMBWm0gxEM37pf/4m1fggAbmajBgNl
4xWY/stCQpFtTu4b1kjJaRol4hlWAjA23/o9xwU1C1K0nrAZzAvotXloszmHJWNEUL+nk5qXLW0a
nNu2FOJiBpknJTkvmtSlYL8DFvWXLFzlbqlvm/0hsk4L2ciJWP7tu+tgXMrsCYTIBSR+2hhqH7a/
pUtKNm9xxB8PWjWx2+bjfbUmfcS9iFHhWT9gqxAD7lcFEKWGqkhCTzbzm+vOb0XRArOJF/j3IyYy
1k259C/aPSjGMy9EZLOEWXko5B1lZdy70x7wvDIsz1umCjTkLu6RMirZlOcimLdaxZZFUCKld/g6
g9idq33n6qs/NvgD9VQuJPK17+SCxjqSsk4PfDT1aFF/k8DfuyviL/d/vtAtKSj4JTBjJ2c10CgB
388yXh1ZMhI85t9piQnLh4uQZ3JI6gGc4qmQ1jE+UK2VwduMquwUk49pwKai/2rN3TO9dwsh0OwR
8AZkZGIoEecMoAZ4pu6OfNlMRez7k/VKOtCDPLZDYHTNGlkjzstRYOKFrXN0LDdmixYLc/dKQgOO
/Uisy2tfxEtF0dRtr9Mvqqi752wZQ2bq8cFWjZDEPMDXkLM2qtwWfmOl6G27pRTEj7F3DTqGWULp
aPtYMzaAB/wKnm1cM7hUZ2vaRoX17O9WbvC/3GoxSAhyqjSc0N1MdeEWWKrMe3pWLW48tVvjLQyF
w33pcVuqOy6dVUya/dB3S1I/tBviIgxQyVzVkRWrrKObIqhD7rG0Yy+SY2LDXHryyiYc0A6QLxl7
Y/cbo5OUnlvQ8YnGaJL1oFC5IdFQGmgleaGUn2W/SakyxYybkuLzYG9Ktej8SE5RuXyq5FhNPit/
xMgsSVVJp8Ff+jC34gCCNHJkv/dCXT/DXFMWDn3EnJkdbX9ZJx1CtUNIAf/sozbtcJhWmfCMko/F
yRIkJhI0U6y9PpGuOfoLyE5NiEyzaxsPWr6P9iyr4s8Zpdx8U0rVfmByX7c/B3MDjQXaIkwzvZc5
Du+OL2qfbvktRybbuVw5vDsdx2G1vjTDqtGFPMPFSAkjdeIXH3ps7ssf/ihCBARlw6ZWrGKhYKTG
g0PrKLftLlAxv1yt8zz2jOgk1bllb9cbz9Fbv0BDNFa6/v6zee2aUnEaGqcgXWyXF3k6SiTPG0Mc
u3ts70COpQ8dRqAVp6SBlntYIdyU7RS79Rat9llYD765JynfVp7EuMBSTjvN0toUVXzwWQA5uDG5
9IpUmBHD9RSz1QoUirslX1KNhJvRp81zpjw4HOfjwmYek51i6hXLsGlWHjZszXkN3/aOwqSVMum5
RluB1EkK2/Gy6cn1uSOK2nlJeDCcFrq/6mFVzDRFn6vfwnJ5QmAJB7Jl+oZPlO61VP3xWKsF8pVg
tQ2KNxBn9OhxwvGD5eOPaTI+ZRrzUxVsrz8+e3gH3vEC6sPe3bon9/zlxfv5ICVEXVGc3JJKVyP5
5Pl/cMVqn0SP4vBdoZ0Nuwi5zQ44xMm166CoklYMJLUb49M/t/WM2uYaT2kwNmvkkb67JrYIYXHM
A2OrVoNMnsAg3k2vqddvxr7arf27lzWmV8mNuGhpCpWhdhsmYxRMljJ1qdY6WdPdUBe9D+huusSu
7lH2O5hRFkTVf1jVMI3nBnUJLVKg/TDLualA5kAlX/4XaBK5kIwGaB1bgRptjmLB4vAAlnBIHx6I
VscN0Xo7AL559GCVczlHWgfJ5iiEBRFGd35W/2tYf5Nn5XSag6gNVH+J6uKoX8aBUsMVgI8S8PVo
aBupClH9OofO/jaf1EMNym1RZjHiUiLMpuP+BNPZuYblWt/wdHiSxGkj9Lp++KdbMHDTHlddV584
QgOa9GwZfWl0KDUVOigR9SOvGWJDkCNbpYIkdV25k/sZ1r1xhL00Luzjq/wzD5Czf1lTy4Mp3I+U
aOUrJJ1etBxR1/oYCDMLEnQ4GlawQr/nMg3zn2GQ2C+uk6Sg2zZfirGKJripY4M6N98ZKmrEEVOd
ctLzRCFhgFKhPkd+P2JQSNesbcyoZylkg/zHY24w/EbTtuqC5ers4+3ZVEO6KWLlVmpOXfOY5R70
6PeRQyOPTrjVSaHbt0ncJX3Xjx+OKuOHH0HQlxhzCQa3vhIyIIEfoI/LQLofdPIZ7gfSSXwsb6hU
ZFPf7ZORcLiXNjNcHlfAJyBGmZYOYOv8+RWrLAqohOtygkDUrfb7HHKJ0Thr4sQFXU0Cvlw3ub96
zpqFR4KRDl2ZXaXSlMayPnGRGV+oCLhGZfnUVnEsbY5Npe2OclEbBnbX2oV+7zTSa79BhvxFreoG
UyMJKjY+pfH+izk0f3ebRKuP0BOxdzfIqIMNLkKME7uWgthku6gzBL+x4b75qtNMFGC0byqtQehu
vUjRP6D0YYso4LADmYYD8quryZLtfuzF8/XVOvxao9tfekf43/aH3fvyERls4tr1JG+YM4ymf75w
i4vGYfzEoab2Bj4L6dw6MhF7CcFoaeXzdHPvtg6aRhJZ7Py6OjeHkR3vtlEorsjOegv9pan2zu4a
8kTQhPlg2U6kPCFu07lFyeLcKj9zP0/KlsvbkMUgQ5sszxiM8/8HuNiz3CrYLN5EZAW9DaJ5fPC5
NuwBh/cOO5lOT4tg2ztTF5C0H/fpU7fMgMhtpA+rgURqqPhayHs88uvfokqbnc4/hf5LXaiwByB4
VKsqtmQH3P2S6mKdevv7sptDA2WeoEUJ1llkIoLbJS32lPpLCX6XZ4doNFaigWGko5mrckdL9yt2
MK+QkjctyKIQaROOQpcEMQHI5Rcx1u1c9y8w3L2Fqqrtp5Ihox1H30WaAUAiPlpXyFstC1H5bsx5
AM57InMKJTbhomE1CLvvex0Pbc0mF0hXWRqqPepjO54qzogGgBQJLbjHgHoaBBVJxS71q61cf2HA
hgdCB2y6PTF4QfnReiMeN9Igcu1LNmlXXKsCM/RwBwBT2z0svzgIcgfVJIwq6JTmrOQuIwXEVD7o
LGcA4zRidK+hBdbeB2aQ1VqxIBqsizd+DeQGen+gd0NV1oSUH403NlgS7JQlzyZqqN6FlQsS4C16
zO0mvee/kWu6pcKLJ4jHoVgugdMy6XgYJKoAFbTnvA7DwEYuoiKXpanK7Nh8fbKpWhV7i+3RJfF1
kjrmpl2ONezmavnbn0cPjAVycnMw6hEiQX1QRYXd0tT3QSuGQXxfMuC64e3GHveWKXIqwSjSz7Jd
MTW9xsgFiHks0PJYSa9E7CifUkW5OOaJa9pSNBlyHXjO3IGq41Z1l58DqMdafkiRe5hf/WgdaGGX
O/xIZNA9uHupZctVUpTL48fvx/k4bpPjaT8HmTsASokrw7c5VeOUF0nxcgNifmr7XLK5NeTbTl4N
g5TWD4D/+aNZVxQPMCYHuj/RtYYK3/Z9EqaP/YgOIrD0fCP+ZTXUPkL0sT9wQl8izwek6rWtonSi
OJxXyhtuUygAotaqv8VuCzK/UFbiO21oemigYByaV0nUkQJKwff+xUHEgpWrvo+qKsUdO36dWMlM
k7DVONoM9nlmdXK+dW5/d5QmpH4gAoU8F+yeKX964bippNO03pWmjc+XiPKWaWjJWyp5eA0CVaEO
CU2Idaro/UTSUG01ohWCBJXZAJrmUE+I08nGbS726JHQSpj7G4cl0e1zZo35CJk1ClkdCifO9jya
RwEToaiLfGiaRIFdV3xGTc5x1Fv4TZVRsA42d5+/87kk4vrTg1j4LuFNrWS1b3hd2YRSUaNt3R9F
uoS6mGAsZ+21jbECdSqEFy7tRvIPykQgCdZ2rTCh+GNGecJKy9x9jalrvRtD/oyeOAXZpjocecaG
YDOl3nksGwq0j8nI8L8XHGhLNje623FxiHkjPxEuLx77lb2JkHoT9hIy58jaRaQSUgqZCqaMZASr
PVg7VzjkO+beVrnLt7hXdvsuwKso3xPTvqH83pVYbZT7et62ARtkBLXFQPrHXmFzVHdLtZSTV/vG
HOsYpYv8xjn66oA2lPxIPJKb1I5J8CQAVmnOS/UMAqbCOw8MYEQbEGHXTbyPigW2Gc9bbPWA0Sa+
YRaVJZ2Sdv6wV4fdp4kXSq1yrvWFB2C3ES1trOQBk3HWurNcMij8KztafYliej8MUZfi1P4L2AjI
37sgMwljAe8fiYFnhrIAXRS/uiruQZ65gmKTPkEFkAMdZApO20pWJUUfNJdOwpnfcmHcwE09enQS
DE6ZVSCVtwDIb0MsmqoN3Cg96Da8ZZProE8pxX4nwDVv6OBnL+niLKAXrqqSjGmAC7VXvKUOxK8Y
1hUEDrpdQoDWnUI6C9Wdv1mcE7mO9ZUlkw2c2H2skCt5nTUvT7D71CauyG+yF5dJfvu1phy8FhYT
/zlGadsY97M8NXDxqLDaNAdPq5BYLybx6yNyZ0Q749VchWpFzzcNMwkO8F9jKk2FCZGVrL8L6atj
xJ7tnHFU/gfb0Jp0D+AMQMvKbgeXDu+Ssk9j5fEHfGIhD22vFB+whzglafT6duowfxqiRuL4JNDW
G9OQJkQbg03tFoz3cjnplVv05vWRrgTWOnZS21D9ef+Ukd4WRXa9B9DfdRHVKkJwkhuMGMKOp+1/
g6Jn0zMbODNkxIY3r/psZFmRBDqH4KnZab31+eHAK/U3qO7XVzJDPQpHHD0cGAqGqGit1J3sVw42
lQldJ26CHPa+8l4CfnsdU2gnuopna1qieiUT1TLxmpr9XiP9jlRUWA06w8eMsH9M5xle4XFVysic
oc35ihGCRK+SDLWQrLUvxNeJH+OCWGwzUaDGhW9dcW8Vrpirpv3bJN64eFwxidK+yiJuA4l9Lsfo
c1lkZhmRaXzzfuq6QwF1bzmdfluLUadeHCNpehvy8+W68g9c0wuG8mQLoZDcgGw6mkJnBwZWvhwc
fMkLI8Y6u2/UK2m7h5Ypqx2tJvvu777017sejeHRn4UAASM4sn/KeUA8UBAelSAkXbldFY0T8Cy/
9ix4z+9OpJ/mXzCDLn/zLhVM0TWOy8ggD0/0riVDgfKcf+MxAgnQSGdCxdULFugADp5xbkmpMmw9
GPYVmPxNocaonL8XIHGp3dTSKHxng4g1fEIDBrl2YVelpkbjNfPcXtRq14kteqyIiEUo55eZCNET
Qo0yWua5l51XTDhiS4W7pA6rZrkmT3wSMBBr3RUMW+ac7gqottJ/8cM1ebr7iW/PyGa2h/xq2IOP
AiHPespNKV8u1H4frGQyQl8W5MaU0BkcXgJysQq07StuA4Zu8U2n3Po8CJb4Hp1HdkjYm7EEADqL
+qjKvjeOx7B+82m75P1fcLR5zmUB6ojd9ee07shl8ALUcvMsCHh+D8jJ8dIQ0M5VN+qi15G63e2z
02v1woBU3a0gjzF/UUjmRSjUavxcE9/aYyV2r1dC6HLvi3ICCYCxZYp+MUvezdnNA90VWvjqLWIY
V3uqLDqwfOQnMnfDf3aFctvq9gfz+E0fjzDxqk8twaZjwb+eKhpgwowmxN2scv60ZuAJqTg1C0IC
YWwrehhhpHe7xnr+f1580Z4UsGTuUL/KwZoQoUcmoyWv+XuiguR9z7LEx2zxhkF34DUXxr9rJfq9
H0dhMGlYcx9mkndywb+IOulXr8Z3jBo9d4/evqca6VHOiQEnv2RxmvRLs4HCGjh8kKzuGwzQiPrC
mYB07RR/IzSJvqQiaYgXpIBuAsLdbTa+fwQxm+1BrKAUKktXZKR6FVa5OrkFGu8CrixD9l8qXSzO
SWQixfXsngGOdY2MqOZQaVbVJsrQ8Am/BVbghDQ3E5cSe6S6W5RK2y18SZ53Ep1eFFfrzYagNG4z
RCT66Esn2gh+xithMG8Te69U5QrraLPpfqjWM0gH/3Fw4e40AiAGS/ti815/PCae8pl+na75CgLs
dD7pc4nVmkivro4Uay7YHkIn8IpD+4kkSgqXEW/G3TsYy8+PaUmcveTPzNn0MWT1QcxY0SicSaGm
9hi0TSFDl+EmBFBLw37VJVXqaDqDv1x608Vn1xcYCWgqqq37rYG1QK6RhpsroYBGvCkNwj5YFOVy
4u+y//Xt9JJhl1FL6hPQg0oTsI0sz/yzu0/jqNiadXkH065+VdduVWvH3QAmpF2K0VTvX8N4QBG8
4CP7fDyb0Ak6xOCuHVhpbwrjMdd60esQNvjpTtg0K3pWV2PAFXEBbDgVs+aW4oPkFrSyTn5Qo5O/
wQ06fxanHwUkHbWjBQf7vBGdGAEh9SRlJrsQ+o2yCAr9pCLWX1gtAWo4xhyeqHn824DHEmD2LW3a
EFZixCn6tHWdHHJnCtL78IF9aZ2nRALd3iCRC1CVT7Jqlze3MjqbR/rSiCzzOhTOKlggEycbdvbQ
q0UR4kD39TDQGTdJ2bgl+g4STz0rXTBXYAL9Y9hhaDxWmuPXijWC2HBlWoCY5gLEQMY+lp5Dfm7D
kbI5/sQwD0D9T9603Tx90jnxVZJ0tcPRNLtyIloXUOncnNNb2Jiw3++K65YXdKBGdKwkXS4xcbr/
+sZ2QpPMQRE/OawpNRd8fry15TSN1EKMoPruoFrnUA01mMAFep9jlIW0JU/BjXJ71cMe9EkQo5RU
1rWYPCm2Nj4MAr5AbXXKIp9lfW9oYTIVEeseXyYMHS/9gz0UKD1siobY1m5kuelEsonZbApyPCFg
tryPUYjKDhLEW/H9AZSwIonBMeyQCtkBPgKpMUsa3hWCXRYByO1O7PqHZ3w8njVB4NR1cCITThdh
27LOaqZMJBwLYWa1oop9XWchFMqG3Hbk1bwcOELrSKcfHpU1vrbhCimTtI1YWZkiLEnu06yAFfPW
qsQDeVh4V3veUncBJt3rQ5l6S0f1rhrPg60vejR8eVkNS+gsxo6rCJ0/ZmqfAxbtRGeky62u0vnf
G6EpZYjKHdNBJS8F3gJH+egE8GGGwtdE1ng0DvK/dAOWoGhI/2HCRJ7iSBF9z2YOWrcvklsNkBio
H70jV2IUldSKM4rfafKv6MARtM7SgQjY7VFg5zLEwMrBVI2b9iaSavBosSiMGSxmji7A42NouSkt
u3X5AauI+LzeDBUrWrTR2+G4q6JDhG1zs2vXYBocgtNLKe8A8lQ268Z5rt0DE9T7GJg4H9YXiQLS
mctYKSHNd2p+jb+D2ZvAdPWNEq7tkU/qLa8Ak3mIQWfWFhTznM5nINcdPwT2mpL7/7vnAO/dz5Qm
ifmYgU0zKE8kcG/sno2xWZ4+SyVcrvsRSoFpWOhb1jZYN4z9e6FCGBiPj5/LHmc542KG83yHt60r
3/06kUnv4q6oeOlILX8aUOf5H5woP/FRe4/zyFE6kUHJ3fuOgJQuMDsC8mNFL3HmiHyAW/HmrjBS
cbxoLko9Cgk5NoyOpFpUi2aLUmbsb1hwl1N7iwioNUEs9JpMX4Eev/gQxiVKhaoaHC4y86VzmAXy
kxy9HXcCrkxbj/jawpgnUSp+sddeaR2WDw21u4Es9R70GMtynN1HElWPjGNhk//zegNXMRaii/9+
sgtAVmM6Wlz6xvJ53wTE3RyIfkznnXKIQlkOMVS/EovFkScWY466ftHFj4OZhE0yP2iCtRPD2Hc8
tRQvMqv8ebzzd7m3XJWJW7LktUU9GV3c8rvrUPTxEgMKMM2jheGxZTsMoPfP3d3kUa5tpwSqEvKz
zrQq7+P8M5yH6Gil0VGlt3c9QJog/5z2mK74C/Hq1S1+J9T7f8FWe7VdOeOophij51INlFXFuQP0
JA6x/fW8lto+Zfv74/3bxskEIrlA+o5AmZn/HEry+KOjW1oNGzgiZbpg7hfTNipu81wL62CGzRhb
bnGDVY5XLhaxZp4dAaOFfvjGAZjPRL+qtpbif9thIRaZliYSxVCye5dnxisNWwQwg0apIa7zhlNl
69Ri3DPE5GCXncbecI7ixVaSzgVIVBFGW1krlI4slvF5xkEU97QJQdkEbCYn/vRWIqs1gmtBkX1Y
qBfYbvvN6cRmsP7ztdWaTSY9M826tXJUsvHC9aYItEhgGlDT3zin7hmz4gZnRcyr6NHd06kEuWiY
jpkUL6rnO2rfA7KhfR4kGD5kuCCJG5KBuhXgJ5Sfvo5EgT3L3XTsIDMkMHEKT2BkEa2cdzpxHRYZ
Uq5jmPoWvUHNa1JQbB8cIkQrlqnjwrMM53B24x5EVsO3J7xdCqvntTMGm/2bZAeTLNliVjVYzMUJ
nndKxmkqhsrfUZ5R0T4iS0dQIg/Gi5H3uHY4jOAYLXW4AidJMtsbmgN1KO0Ynq0dpjO7TP37OCR3
S71iLpW0NHPXvB3kSbP1SzIvONp17HMdl+j/pQTSY2ONnA9v5ngLJNnozYxts4iuodGOLKykqsuv
h3wpWFyy68OPAw73tR36kO+e/a1k5k4XFBzrq0xuhc40MLTLjNfNCxHy/F47TIAy2yoYhAwr3H9h
BhbtXGfstMWN3Z+ihPaWPMEyP9HX11xmqyODH+hzRvdkesxJsTIfxm33jk3bxt/3URAon3St3yAU
iF0J33F2dOenv+ACXRjc8siFLZUCSKD4u+lygqZ5XgLhKMPB0DfwWVKmIgC480BnbUbcDdyHdWmf
GgjfYoWFKkHdEuai9rcWQ2SvmgWDZUGHp0xuiTfph4BEGqS35R9MIz77j9Js/iLwxiKE/C5uFf+J
NpV/0r0baO92JSDR2vk7ejha3VW6h4X0QMgG04BlV6rzBVJNqfIGfAXo0ZoezFJ+xyJ+/S4Z8kTw
jsls5VwSzUfm1JG/l9MabREM5VRTuYoTGJ3LA3cUJqOxYIfIvsVM+KlHZxuJrTKj/uE+aXCTs0u8
9WuZ9fUYrVyFMvMOBhc/tRMDyXLrJH4JGqkeJ9NUbBAPfYmgu3n//NQBz7GNHmENXWWTA+H6J29f
XILQ2EvXBLC3XkniaF9qDS91goAL/D/GA8ZrvRZgKgA+H2p61kQyU0GJ8th5JYbadij32g3rJeJQ
cPyOg5ClJWNwOV+mTH6lpZTa4FU5v0w0rFivoN2g/h5/BioC3flVCESvweB0Ao4fYK+pLybr9A2v
U7Uhyquxj/106KBV5RiH7W2qCvUP+pMQMujWsRg5iRQnhaYJKqSQCSCigm0i3yIf6Yil5j5pDkr3
O2GIUnJjllcJC6SroOyTZxeHCbaSWC482aqw9M1bPrRDjhbu0Su7cFWMSx3ekDnz5QDc8mBXmQZa
/PsjECbAwjvw83452ROiKmEBOT0s2z5YORL6uy8AIQODbP6nwVAc2r7WnwO8SfSpTy9ObVQyYRoM
NI2q+k9wXxRscqZI8AlvElspXOt6YbJVKXYyuHj0chIFw0j/Y4GkzMhNZNVY2wulvNXngFuqOi2I
3F5/i59R8A4XQApX+TF/dsoZDvkcYw5LB3eY5tBsHUj8LTj5/uHGjT/mIzGzIjt06+HDRBDpq8cJ
GGxNCEdLhtGC6J3We7aprJmgBNqtTKZRBf4gAqUFpIEuEXMeOdpDQJtVuzdvPy0uvaRR3EJv32Hg
cByW3s52F4irB5pQkoj4wmj3PrfsVtg2J2WCr/yJYCH5qnz3ePVrD+W7agUJno0E0QccgENjZzaj
uTR/CbqXRxgVDB3zcYKYRSPidw/7Mfeo+3UjFoq/hBOokRV5gy7A7EAGZ0uX0RXt1ptl1TWkIJkl
c6mFa0amuO470tBzoAoUbr/rT+7Emgem7HMYa3CCWp9gp9emVwPc42L7+Duyhk2Gzq4HqxZReZkl
JsOpM2mdl7c5iqFK4YLdfZCj0LfLcKDLePcug9cxLnyoD9e8iINQIyabQQC9u7WL9z6xv/gauooj
+Mi9R1+aEUjqQppzoRXBKYcPyiOsXJoq+EX769hLBx2o4N8mF5967mPJyJhtaO2GEGVB9zohHO80
1kurxKLFkNcxZpRKlZZ6pXU0HP4GulkQoCy9uyme8lxlNmBXlcc53NrOnE0+h10EfJHU2JpIQALX
DmZcodyJX0QqecmkK6a7pHaAFDjYB6rimqA7mM2PtvFbiToiqbHgoioOoFFhf9iQGmta3BgsJH/y
SxGQ3nkSVxrZu1lEgIVO/WAm0EC2ffEE2VJ52iDYzsGDOIqfwag61v9N3NhMqC07AtPqFz5dumuD
XAJwI2iuPAlb2Fts+Ue5bHvaeSHo6P1nyJLzsq+GcES/tuda2/xHAk2bhoo1rlIOugUNQZLyNZdJ
XC3jun6ao/jPUvUqGwDWcdGZ1govdoRwQ/zjeGcteWB0jSC6I/baAetZbsUYD6V3eirNhccAaQSd
8bJXpbcKjlAUm0Q0DIv1JiYofaRZgqpCZqzkHDZK6S6t9pempyMyjwgFKsb4pDdQ4WUPXIRAmidq
ckRZ0+r5pjQFPokGH85S2ChQSEXeJ/u00CerkwO1FvV+btzYSntcL/M3PUt0mG1oGEmWVhipYafg
Kc5V4ub2uZZXprFwtcRSxLpQsulhp5n6nnsrZqRKUkl0Mxr+S/ozK52czVx1ngVEYBsdWDa0TzKy
SH7S291cEW9xM+CASXg4uz8FgM6txjLgVubbmfPmgsxLppL0rZV13859XJYjvzPubBujVD/W2NCm
IE54vyXQ1x6FMKQFcZSOxE1fV8IO1xd3+sqgTuFL1JlCjWqa84QTvTMmovCXAHmwqU6Y2jNnVuf8
pgx1DEAY3BX/G1uprIwD9tVt7nSvIQtPu7CtuRPTpfwRS0sXkYWNrrhbvVyxHWt0WvtGaO+ImbY6
i1BE+QzCAgWSS07ZddrqF0d9YGvhZJqRP2dfDx66atrjDJFhATyqVT/a9IVUDDC4XzZfEe48yYsP
1l5Ixnt8GPK5U/3g9MChNT2FdEa3wQl9JKNZdyISVDHq/1aR5nsf1zIpeRPG2JnxPzZQL+gs/oU6
Ac/O3vMgBgtPw1RAJ+sErLQQMTiU0mA0qHmAh2vozbdbOJcjkNp3dZx8mOs+Iq0Rean5Dz6HAacL
RvnQDZfiaKuD013+nkKk7xjyZqf6/ZBYmZ1KTNJxDNSROCohlDDZon5DgNN1muhND1TnjTVIEKH6
Wcn63w+qXXX/Thu8XoVgQrnpivJwAmVvyD5ua8M9w8aqsER0KEy/6d7Us6pZLdcIpfD4ZUyak56/
dEoAjs5/MHOvIIPxgfJx8/sWxTs5474NRavzPqoO6YYorakSdCDxFTDXxKAp4PCd79b5VeXkTTAm
Y9kTfJkWxE8Egx5IKSjlI4YVAcoJaxBIOlZJBmhNan+Pdszt60lsuwqQ858M3TigxhGQ+YMS3lCR
pgwU7TN/+UXKV6YBQT2/Qin+VV1XaZrr4Vs2ocCg8NsIkKapH1/HC8BA9NBvDrUdbGLqkzc+fRV+
4/ahna3DuuLPXak0HluE4fCskXabJw7F6Ft2ktCFuyQDdJp3EW+5ePIkXoJf6vLWLMwGo83AtmUe
wqL6/Pfq7G8/4o7y95o5S4kBFc88h06qWMIM55tys/d761kgVd3VKgL+GJ6hrEDZDhBhLjkqIVxc
evSSxD+8Qjx2FR6JQxC96QooRaQ7UhsT41DGeFFbwkWV/O/l87irZvBQImV97BGFJtoqFOg1nMji
xYHzSh0ybzYKqOfazlxYqyjwTvbVw1WfTc8GkGe26nYpu2NvDnvC7mJfE6KxLgjgqoUjZOpl+Mpj
ehekiW69nD4vDUpGRRenQFj961yrjSahLEiISQAH07P99WWi1Z5rgVaiCnhrqTXXhdbFL9ohTl63
MI8Ll8zfQHT6TYJckJ4vHVZrnVaLwhMkoQ0Zaly5T6THuHAYFsNIrzWYNUJLfEyvYKrb3+4nPYaK
JWmFUqDptwftzKVNYdaMoQP5CPJSQ4ArXracLwkdd6Gyb3Csbi4xxGUeKHsY0f8I1wWMCyfkfv+2
YVPmUyYwEZXfjpn9+K005pitHSxXaNLbTk/VCNi59UfUWGFlcYgbL8h7SgGq4cLPKp+a+mox4HfP
AG9eV0c/hG9JYuuP1Z4Re7EMMAnExvMceXZaIRtera2QKgrXV8gBTcM6wyVjqlycUinxsf1lYstH
pn/zEbaIca1ZKDoNiHQdNYnMztwPp2f85DmU1fOwGEEc4lRbPGjoYJBSv5ptUKGYHm/g71svGI3h
YSN+oesupg0GK3nitkD7rqWFHFytkY/SHGV6Znsd2T6nPy6GgbxCEN9QEu6a96TmHtKoCBbQ86vP
wMPBpBS1wDSH9NEfcY4yq4VE6NzScv9QkiA5iBjxIWB/OShqErnyZEjc8DY9Nzy40hUo0sqUtgDx
i7hSec67Quo3af/1xGDmfyAQMmXZHqq92iLwSMEqPyzA3re63kR5iFJVjvU2a4SIZJ9EAZScISxq
COd4FseMM2F2m+GY4Wi0EYpJVSYOZHC4/Xmg3Qve15gLIQElKN3xmgoGufG9O5XSH7eBxwv8w4Ip
v6jKuvxswernUAZqgbdV988AZyrrcpXvkf4sUvDRkGOPDqt7eLiephtv1Ev4rS2fn97IsKibQf35
ZxEPmLhUm6Qo1yQUmDFBjYH4HmoU8XGP7UWr/nTFwbqjnu/nJm4bJl/sQr92yEV6mkXFXoOpkvW7
FKzoEDbRXSSiYs8nJXl2733D/WYj/kx+bS7nTRM2AhiY1Sc/py8ANFhmeRP2IR6GDSJ2EMK2QQ9E
DRwLyUtoGoRp/7VsF9E1XjlciLi9YTCiwICjdw3EE9hOaOHjQfrvxeArKXp2w6ERJhceuBPu4ZPe
xCjunSHhRzA7qubFzV9H8JUd+eu/VJMhyHZgp/4SRocW2nXSv0SrmEI7ptWKX4Z3CcalIqgY3mPT
R9AgK08dv0aiOMP80YoHPWuOueKh/ksL6xpdL7RokiV9SKiJ7GJk94Qw3K1G2mAqGslXXT9XwPSC
GGlb0PFypeTGwGp5kYHVWrM/ZBSfQGSX86qgbdlbqvkp1mE2Ht/uXKLWwD9gX6cOVo9xvgBGqvDr
dYZJ/nrfaF+3YzuBM3XspSo/7ahiFejwf4fG6RA+LWWExDf8kpM7zCQvqMYq+vkBJcPhuHQ44wg+
L2Ld5FRPBEb314ZIpM6UJGcQ31eA2Ousj9sU94Ce+Ycf5+zuZJKT+zVx/f15klE/kfL86Gn6D/Uc
vfpUmPUpbzNIjoHSEG5vDljI7674KBznPOJVtwpGsaxtTYIyOgROtJ1V9nRVPOK5x6oln664rf67
hZvgtc/Tn/NpgPAZNo5Rb8RJpen4H+94+dsKlXZcyy295F2yzpNBCNBJ6koLIjSfcWzBWcooMB7z
BA7uHAhV+Zm2t6pSR7YstGiFQzpLeDl4jV4Juru/x9B+2QdtwqB2KJf/LcqG1dy2nZuU5Yw9MZsU
MABh9KgEz5oJIH1/Wltw8NFzX6RxeszCD4uTwHze1mYkhI45VR8ZOWTbbpru/NKNzPjpO/AoJw6h
3MvJ4eZaV1T1XZyBn4/S7tmxx6G0ablKSEbKCqmYA6U1ybk6VEz3Kilzs9Ehmt40u0VHboiViJa2
Xd52LjpMAozTRI/rc/cwp/6At8z8srDE20da0pDA/xlFDcZzbCe5Q+CdGV/VWqn+Ot4Htg5LAQFk
xy22+b8EtFduPJN/kirE3PDZ/fb8KE20hMFu9n8t3axQ5BeszOK1fmF9RW7/BofYBTJYHYfovEPF
pN8kRnN/3MRrxPOyP7pBaCLm7Lx+Xcx0KWhP3UIcWca29DMQkcGQQ84RYMImJKcbZ7VBxisYBg4U
aCJtq4RRRi3AIgEpGYtRw5zGDPxoyswB0mtCFQhq31NS9w4mh2nVA1JSjEEkBN+rH9SiNKQLKomt
HzsvCYNOYz0uufuKwqMvNA+ZX1Uk9XZF2V4Nkha3PF3+SW0EkVmnmyjJZrurcy/T5buGOWnehDYo
Y66P5Qeh4hQCxZCLJxbbowdh5hAOrWVfTUfuKOXFmKdbXHjWzfy5k2HLgZ03Rrnpj5405Lz9xGfC
HOd9gP2mhqWYoDPXHFNCod8ycHeEZwyuPraCnUAvg6ltaUEDJ6eDr9jruPD7WhqUQXQbqnWlDJ/b
D8YQqg7GCI6s5NUz9PM7rwj3NU7oeQdPO6fRebbZhey/2MJ5YpNuk07svHhCvmcu/t7T46WQ3bt/
iqPgeb2qB2fWsn5yxfJL79NGLH+sUe6ucJeCtY1RK4QsQoljmiou95h/a1E1/jL1Rn1IXrQa0Wgw
V04259bnPRYNeQKx+JczTmW3/8qjebFH43HJULAEoTd8PTiIoNhwFBEtjq8h9iOcSY1ooBgnjXfO
kuXMMyA7s6KdmI14dEYc3FmgZWMH5TpQZl/IenVyJIWJpV1Ve5R+j2ZDyXjouUUpPWzK9vLMwBEj
P5px7p3rOUhhCOUQNtNQhkphtygE7NOJeBJxRip9QSwE+o4ddq3kr51N+mtjtcAUrdBA2I+7SIk+
oNZby+5yOMXZ9DQWmy6MWGk8uJAbZBE17IFfM6Rw+21wstPxP3mE7hsLaLbIEJBoSyAXww6fUgii
u24LSUT0OpOcbVxj4DqUP0+CwsVpnxMRuE0W+WZcL++66TgJpuVhPFVzwvFMiVHzoBekaMVHEnfF
Wrbnbyrp9sQ8ZKBI3wNxmTTrEepyFeBuVH2CSwjEHV8hEE6CnkbezG1ZxBjx7YHWXyNrK7+df2l3
qd8NDJqLbSEw67F2Hdn0X7zHCW0vQPO1qbRee1jh4M/CFonn01Oz+DI06w43TqFoX5tqO8Fp102S
wxpOAJ0Q0NiXAA0RbPg/ApRzORZkJ0X2+4sNZljgSsxQOo51JN7cbbEukw22J2SQG/mFsPUXCXb/
Y6J5H4neWk0Uk/jIHZ6Qc2alsEVcCS8iXtAWakT752QweiCANONv2LJbNjel+P4nA6mpSIOaxg3k
y+PGZQNaINyu1pST5lV8QgDiFwqqUd1XXmWepmNxuLfMwGU6gPkuD1qPtowndxVC+LXu40Is4pTA
T+UnrJVu9gmh+8NlU1W7HlS/bYAhZMWuWmriDBG2XyFqTBucOpnxaCm1X/DJziiCMIPr1M3zcGCl
+9AMXbVn3O1flhACqqr5MaAZg0Lndn1mwIPX8kIKmXcUP9ns1cTWrpvRny7CYpZmdvv/Xh7n+lGu
zPMZzaqLSCkAaKveJetgi6CyDmeUZr4Ij95Z+iZJ+kV1qq/vFYGqAOg4yNrLkczejEZkKVF7FUq3
OvhwXOJObrcJ+1hNJk9BawK+BjDxCkLDI/J7nHysmFSsJ+NBTK9C2V+1ActGxDIz0leaN2+bSCcE
fSid2fC4HDFWSneV3h65GI4o9DYL458aRw0znEvZsWlPWQYDvNfQ7D2mxVZlG2qVGTCxN3Lktjxb
oK0eZk44NnCZ7F/ayIQA4XHWF1MZ1H6+NLkJ85ecU0su+qFMNcV0E543plc6699sRI2tzp2DUZRk
1kfjVaicJi2W6T1gyC34Gcf5n5gJ6wgdC0U1cQWbKmJnEm59x7z6Ip83ZP3LMnvvVtRxSsSt8sFk
m8GOEtafmfWMePc3Hg46dKkRaO/ObWpktzjufeSJ60cnfrQKRyvoW8zvFGe9NFa/c04tFa0XJ7KI
YjSyLVqNM/7Ryby3TN5JA+OKB0hhmazSbb68Zp5iG39eQLEbSyYiNOk4M/RgVAYigs0gPZKB6Lr1
Q8g08iWJnO1ZZdJPsaODhpOFWE6aCh4Enx7PueKlVPzfv+Pgn1W05bRK4xeHIUMEliHPzZ05obTU
x7OQWTZAuQMaSS918XAO4g5gYLkRh8HDCAa8DXOmWnGoJf1cQNRfgSaU+eYqC6ruUfn3iP8DsO2b
Yh4jO+bun4spgr1ONuzNqLRqRuOdl8GefqCnCHrZ8FGpwrIS2QZkh7Ko6dHlDdziA6a1V1mCM6Nx
+OKpetdq8P/JezhxxeMMxJqKkZuUa+S5+DoJR2iZlPVqgYsjJy8a++FHwMRARVfjUdMcrCBklY7Q
fsPiV1QELmb3XPIpC8RJfwporRPJMcAjz6zugl1WPqUkFq3u5AAuSda9FOn+vzWebyU0UqjZNG0f
ZEJydhEhdvIrFL8PuiVkGqYp34D1yIuCOf3PuP9VN0q2py6nBpvn7z5P1fSg+flPl09o+N1LdjaJ
LDOPGVKal/QNhZNSiUqcCB6wtBuhLLgcy8qdhOS90+I2QURa101thkYZBFNIW6fklOHHVHzIZg+Z
1eMfVNP1mhFdVWho9EzVE658tRzALPRkBn1tSmE+2glytLM5S9rxvrGfNCb1uWB6mnjT5Qbp4xIU
CGV3XqyhambiiFoaA0TjJxTlRYV1pFPIJyiJMWhZ+xRbgqeKESr/qBaBe/EldATLYr2aL0tYh6w+
ixBG9pKWay73sGsrpWGn9Uhv5+YEvABAizhBlEGAhgTcMfiFZrirXOUhoX8gIJIcGck8XEWQ1Vay
s3/VyolOcGXid2SV+91f9iHutC+hcaQV9IKy4Z+fUqKHA51uX2nU6YLhbVglOwptw/iU/1V63wsS
82eMSEFOFK14FS8bhovJwCsoC99FuebIHecqphKXO2gB8qwhc1auEOoUtqq12sGh9TSOrMLpNgNy
gMIbmih4P6FSvmxRdXPgRVQEihGWOpwCYn0pRX2DaBKE7pmJmYDVOWk3LLmZZTx8L8kmNYmJFGlq
syG39wbGkYpeq7hJmDCw3raw468QF3uZgeYSH9aWzafBncq8zcManw0z96aT3uPzi5qqn4jFfy70
lNYh4BejVpzSQQBdFXoUXky4HE00bTF3ZqeDWu7jL43C/gUD8q+Ig7kQGjctvC4XvGtGCVb56qFW
t3UQ2A1W6XKo4Deqhb7SlEWLr+qGdPaLJQH463aYAO1XOAk/gOyYtUSjdcE7L9FZW9z5Ev8w1G4u
R5qiJjlRmB55RlJ/oF0an/FrU7JSrpI5UBw5EUS9XZGvzpKa8XXS+vu81MQgLIK+aKnUELIR8X5o
8ypXGCxUFePkVT2OcQn/Mo8oKJNgareELiR1M+xoSw0pwx5VPaRuEwdyxDjNZlzqeDu4e3cTI4ZK
D5+hPbWBa6VdyFBAtvUpiHJosH4qk1Po2OkrItVhIgfrgGq/XzkKIqwANhdytPXum0HPXJMghXl0
2v4jFzYTmPCGu1isUZsynIW5TTOZ/cMjqhviQHDOsun5ebrgjgQGjj/fxBiCcgey5vHHox+Cd8BG
EW/G3EC06CUbK7E58zRmy/DYF32ViL6iLf4uf2wdYrMHsiwJ2hKXdN3kFIbPaHHeUlOtghzxFLjs
cT45gEY5Ey4w8KL+o02Q50Pc4ajhk6OIXhJGnkwOOL1IJDrjP5R6KOleOKE9ukozOY9w+I+3rAYa
u/+1bKxUqMvcxIS3XoX+ne7SK8tkfs8EWxo36N+ejM8g1sr2V88JMlnkg2+A4N7dUADb4df8MMSz
MdbzPALiYJZ+ZLNYMYhcbenWeDQdAC6rahzneQt0W3ewHAB9BlX4niSdFsuHZpEq+yWxwrne3aEP
9FrFhnPZ3ywfAvlr6oYSa99SIcDvaQHIjphJla2qhIILY2MtrthYnWFWLCDWsl/Rp2m1AtCmsrAp
Mkepmatm99lsOjxjbASyS2ITgGM/EMbMSm9ys5qYNxPUvN69nvnLF/Wv5NtNMj7q4Q9NtJI6RSow
eU8hbs1zt19kX57id6HR1BYCAYvVee/PBvy8+fRlBp9qeAU34/NsR/au+LhoXWfQ/Uu64wCeZa1O
26L3p4lP1otQjsUfxy3kGTpKtnSuHtdtzNjGq5/IujrlUQJLrJ9befcYSDAl0Fxf+gOWuI0EMXCM
bUBrH6jPrG/AmrjNteAbhXG9j3wSbYSksWqYvzDY5s7uIoy7C/WbtoL4GueOl60+A4TCC5CgKysq
RVmeBbGReoViQ7jg/GM86bIwkbQwqymrooiVMNeWNfGQmYZ1SdUiOPp/JVJpghfgkeWE+ZRS+S7D
3iTrXPOJPzkTPRh5up7Ctck6KtUH29TTaXV2d4FDoxUqOK0+KXxM6mBm8ZDY5Ji1OH+75IdF/H0d
cnYfTCszvIdr7WjySNKRqblD7O71Rtdwa5sKdTOPAOBibnC7NddCx8UmiykFba5CXwJy9HQhRJnl
Ahhy7hFZE3w+id8lLGS3qhdkTD4AGrAlGhfu2KxpqAW7Rop76Ph90vriNhw5Gi7WJv82dDOLhcrN
ppCAfLWTrHvIuJzv2yJa9f/z3P3KxZ2ysLEs+VYHtmVsDoGulJJ+v7qMHbuNncQPO/R36tHTGHCS
ipmZ9npeh1qfFP8j7chscKQKn3jeM2kXi7FeODDQ2ksnikFRi+sjeh6Pkw3LUEarrmCBBSNRje3Q
Kgari39Ue8Ra2pQD3WQ0DOMiB1i0d2LwxziG/x3TTlIpKC0zix7TisP+RwuA+sAyq6lZf64RyXeU
tKDO/60kvlapyhe5XPx4Mc8fyPkHQ2fpbBWCZGwC6VGB1XZE8nJumXJec4d0gJcWkLtugXhGAebw
vRjDhqW4kfkCdUUHmPGoS5ubzpKhNXrjNa62LO3+4W/nXqOhYS8bdzMPgUfOhhYxUpGulOv/wr7+
IrXQX36qYq4cayAOOjr44NuNrMUq23seTp6RzZSoFDxl0Sl0D86bOV/JSeSWxbJs3kR/25nyaRPL
qDp7JDEhUXvgrNksLbmJrRGwolIOkhRSouvuZQEhqMreO4xRzYgWJUAjnNNdHO4JGrZ2Bpi8fQV/
8MiCYNg+BnLLh6mdH/YW/wn4p7qqZ3+IQJO4kc4L0jf0CUBfMfFteyCEULESohH7jnxGBYj7usYW
KtcYnplmiv2Hbtq7lxbKHgDxofgsLrXXchi3cO1uCLCuLSpBmMPMEKZmQfh+fxRiC+oVkQ4QzlRy
BzUCB5+7eNrAKlVbL48mhOgGN9pOItMeWlfgY6A436GeS/maD1wAgWqozY1JZp+QXva6afYit1Wr
o8iQ6JAypT4F2+Jp4ni/nT4xirWdqPQmiyCBkr+La+0PE1CvogHsxe4ncUzoZfLzlncRrnPInNx/
Tw/6uArUbVQermStcVw25OfZKbYI8y1l+jx6Jtvx65xrY44qkPOMud03LQ9GuJfP6kZHtbBk5FRX
xoAYdnONJD7FnpWR/bftkmjFHeJCreJ5goEnphR60w9MQOsBqKV4ParpbOe/468E7uyXCYsp2xyi
CVhK8YnVtlDcUKzpyHfX8di8HTduFlsqk5Cv10kFRyJTwIIXeEB3XuCvecAQRyxpEIiFg6Ernxkq
hc8Vs6sC2ZTfCuDB3/mS5qDBDp2koaaxXDzCk3DNmkDMGFtc86ye9nFsf2wvbhF2xprjNxXQzMhq
3dtrOkd7pGcqqOyHuefLJDHbxGx4Qf/EZSZv+gwBj7w4dDO3JbZ8e5e/VZ0KlnCR2bB0HxExCQkA
zJgQbeEYQWj/ZnoUiqD2Iwdy1BeG2CSM12TRklCDLp3TcPTTVhSKXFPvHWePHqoS9ki2JFGUOOU6
Le8ZzhOM/kf4JkI1YQeO3VPm0+MpyfPlaNvcan+vmDL6Tj5F47WMCwImUd9WkVvBZwEdu0sCDc6f
236aThLRRZGivzqeClNdqFLY3YqlxdmVpYNRWJzNYrc/kx7/UatL2eCsqeQO5uXXImnWvRyfO8d9
WapoNHdjDfGbRJu+MSQNtrhR088XzivJiMDzKe2OyyFTT4E+YYiZYuOOPziu5NdDF6In+jutURAw
ipmS9qnni52LFYxY1cToKJ6DvRHfsDb7Wy/HXYEL7tu3Jv3keb568kJWOo5VR6XliP8UNp4NwTyR
jzz3w+dJlVT7DJSt4w6EQ+KgG975RR6bT+cdm6eXyXyLzmlBYS/cDj1YdhjdofcsMyBCXQkmxg3x
SR+SyhalJDGMlbxR0TU8rBNboVj/JQ3uJEa97XPM9udBJMqZZvxkLuKHOrsG6YqzDoSFkMoyY/bc
IxUHXw3xfFJ0FXaNnq/IId6G9Q4wBmqd82eP5k4Umd8YfQiU5XDwpBizATfu0ZZ1cRBLr7gMEopx
TH5NcsaCYUu9q/HRqhUNNCTq43BwcoBfRualC1qnoVktjsnwlzh6XoMMEabPLW0SLDI1yXdjF9NQ
oOtJBwG4TjWdgFzP66OKBbcYcu9LrZsD/k3PjpmTCZrH9V6DmtfBE9BDEqDfFqWqbJ9ymIlUhUzQ
PtU6/ZmuqUhKihC3W0IkNt7IdeO0HBdL1Ehv4ktwxVZ+P55+k9zP8GGGqudPpxiqkiLMQekuTWSR
FNbIPfs83nd/eP9zN/VKI8X6Us0I0RGbON8DgCO1rT+uGDuoE81kI2Xl8VvTW0lJqChzgGre4eAT
nUpICK/6W00EMoCIYLHZAqubNqHlO1jtqlWQvEGJ/edgBJ98gptoCNIesRUoWglo49jwtKoKDUSO
NAxRE9waRW4nQZyNjcNN7vBWEwtkuxlx+QpF4zmG/hQ9mNKL3KrvyoJbyh3wE6OjSrbhqsc3rW/U
5s4B5XmloYRm2zc7yijYrlj/kSTZ136ziQzZQCB4QZeJYobvaT1I1YyR+5o8YvgHlSgUtD09FZkd
2rky8iGg1hD5WdNUw0zg2+VNUqy+y4UdxcG88ltw2UZgDfKa4TOsFMa312kOhu7KRVA4MxUGzztv
OIVTMlGZ/VtjGaEguyL9mh2Bud/mzLZ+P3O3bTV+EsqHRgLm+q9j+EcNMtOo83XYb8uETdH63zv1
f73VJRjblj/mKgy6aAvXzMOQHoPx4SwMIp85G/nYtqSaz7cEcGR7UPL9TQX1DRll1pZaG0ZLgi+M
sI29H6YbOEi2IaB8PblUl8rNgrr8JTKxW6ty1Nb7qQ9oLkb3Wd6skMswU7D29S34jX+XuU03zdg1
O7EuWbuKQp++s70Lvw534i3knjk8Qi77oVo2DknWCgS6nV7xUzF9W4VNXbeVQ8N2MM9c3WH6kk4O
fY1Z3dTnBhBr7nVG1q96+g2BaBhP9rOcjpTB02SdFEcm/kp8Aeu6WTwYrlIMLjIVbJkJrgMnk6fw
ju0vjszse8QiogHufN2UJfFIZtwz8crXvlJE0Lob2FCe3k4xOqzDaGvc4SELgxUNzXPASk7N7mw2
3R4x+Dkp/X0R2RH/jJlv8wXuVSsD2MjOCXyQsts8swkNM1Hbjvo8AkbK5935i469v4/ZiCQlfCP5
+rM0JwJ6vKi+Gb4pIAcKWKU1daYImYRHJVCkHDle5i4zUSuZer8NOs5ldCOQYxH8DIzByssQj5GF
kI+Lf81RwPLuXgBuewAk5E2nLO/x7iNNQP3HlLalkU/mfokOm7yM+aGf0wGPtqzOR7Q/OL7bnNFo
Pvhf3U4JXp8lfpomsiaTuD98ddooxmW+VqS0YYk+uDXFHD+N+1gDjws3zQpTtJMXyq1LeMQPrPRJ
iPa9cO1XoapfWfbt9nRwlhRFBwEyDh48ui+XSiCQ15KEPzu4QHaDbAZCERLmIIHtVQEK/1HOPaoz
bJ7i1y1GYzKIFRjowKVUqD96cSa8CCWixMjdiQfdXgMwZ94k+Kb9Q5iZG4M2VKvlATzKYqIVa3BL
t75Z2HQIga8u07cAXEQZ6Zjfh66jm39DneJZt7qNFEY8jYOZobIRgpfZJZfOttrZxhbva2QVTE87
YOm1LP+hzHYVZlh9VB8h68oZ8aYsd1wFTpgxbswD5cCQZ7eXt/Rq1kB/eNLbBOKEhffE6qPlhgby
bvKP54H/V78/luByskt6sZdZtrNtDQO8vSF3NazR8xCUaQiuFd0avsXZWmpnDTdRI6yctstroaAF
QXhNP3lf8ZFDvGAO7b9XIwvfcxDciSbNEXLZPTl+2blFH0U8bYO9Vh/vB/G9CRrOhy3tMwdVsvi2
zM9kImsP7okAFkRLggPcl7DTCv/cX2kxkFDJjufxSN3QZZTUZMgKdUIWfcVgsXfXFdoEYD7MlRjI
rVHYAK3yjkxy3uWpjfD+VoatgEXCjoLYYn4kcH/wUrfb8UpIU4S48ffzMEPqCWHrEI9FFA+zUm1Z
8NrwoDltheHdSIx/OQiJu+JS7Y9olatayuC+SyLryO1LtSY6CY//8tfQnZMoMBWsriS54bHhRKGt
WA2W+q4DG/Fc4UzV4lzcGMzGihQLne88h6MBGQhbhE2gGiydeID5BmxUyxSyFeQQoTa7YmUxpmKd
F450j2veB6wHH4S8M69ufdCtZ+zGm0HaCJd83JF4dCBzEkSlC2N1YRjHWlgwRIngXyXmI8IKvh21
NYW2+VvmqAuuO40EnF3DlVf3D3YjkaAOFq9PH4vLQhvEvOyh5QDA+76Nh2nUCRe6LwY4W62UeJk4
cuMcThNrT6xbBW9O2jeuHcFt4qG1BlKrVrW353I/ajZ9AmVpFbLgAZLjUmBkhspdgCvxdxrrqsmq
GugAYH6TKjOABQ4gXyRDYjH/MuLg5V1nUh5mFsaL9+8YPZ5N7YBOOo3bS22IlXMQiLq1x9YaUQ9i
j2dR7u8pnG0nx17qGjinK48ZPvcH5tSJWtxQr+e6z++Bad0OCS36hqTpLVkIhLG20tjBD8dx0z4H
bnb6KKZwR9hC18o36hknrj8ErgaHKMpQAyld3y6NBJyGKje8xAyU97uAOOpS/G8tnSREaA0SVRkK
W4OV4+zUYZna1ZK3osLudH2VltloEKDMPv6SuOy9l0dI0HQh+16vsmX04AEaN3+k4n37KDQJcpTx
Zj3Uh4gIxKnRORmz9ynv9/IA3Qy5X2g7KPaOwanGhVkM3POLP1kyLm9tLULhyjYPHATrynfMp//v
UlsNBD77HxX1AsZi3s5otr1NMxSMSHU5C3ST6Ij7r8x/cMA7pU6J9iUUpNzy+XL3xa6sJFoPgiq7
bfwu5h8VMI+pXFjKC8514qEpud08OtgNnVTimDblhAwOkjDavdCaqqyoqsRfT30HtBtXJidsGmQm
EZFp0zhvJLn9XTLQ7SwmciynpimF5H5ym2UMWD5eFREg9RitQmeLUVKdGguGx1cbV6kQ4t51MHEU
sfBdQ0ARxGmWeizwja1OG2lMi5tGB4Ge36g5PTKgwY4hchaevLW3xQJ1XitgKIiFYRBaQBtrp3nv
atd4OENi/IPtLVjIlt3MUgWfDorTjRlCExMrhh7zv27Ru9DkCcJMM+NBIWQrxCSEeuYvQB+Ib0Hk
YHKqcv1quD0mvlBDYChe8MypmagTiwwbxaBR0JS5A8vVHVm7wndTm3VSkBXasAFV+arWTz4eJLH2
UfuyJpFJD20pzCq9AEC2efFVbj1KKPl00bY4fckfiXkOi0XDB+weG0QyREvMY9+qfT61fwL29EMu
/1COZ32m6fpD4w+ExLtGYwMVBQvSorOsWJpaiimNaf+ZJw+U8k2t6l+wV8IY/Bzvg7kfRZF2IoZ8
O1TXMx5Fobugkxa9S9l5NzF4PF6IpCs9FBXeKi1npNmlqAii8I3okoudZP0dcwo6uSNv9og4gIZg
kjS1+Aj/lJoyGPCqNVNpf0uErm4AaH1Z6kinwLAC/A+N3PPmzgRFDlxsYEZgXCoF5LXQU4yaPeRY
Pw7VrH3EdVzqcyINqZ5I8IHMYDSizSP855gwy7cAFyJhZmzsGeJlMphwnnM7b2n2CGOcIfHeiFvJ
BAQ5Gd1gDrbNDxSjV3h3abe0BdUaISLrExPhOlV/J2nyq+caNV2SW8yLrOH3/j4lkW4HWkaPOcVP
dRHEfUFat5Kw97FgdwKOPwtwTQvICT/iNWiXQwKwQtPj4jODO/jsCTvFPpi0F1ug2WRUSaLNvSRI
LUM4pbn7NwDZomcdpC/LGp3OO0hvhAUPbwffkYGhPVnZ3hpE+f9WwjnNt6RQ6xstojuuTQV21GTo
3kTPfxTaoMqNGv6DcCAsT4PyvIWQLXWdkOFaNGkuiKXKW7HpZm4IQEe4VocN4Y1FKJMLgoD/RIGq
3uMeYQCEGxhu/zsHyYqQUJtOpAnHgQ/kP0fkRXf+rdhbaTPVEkhJ89oK3R0MK+A5d81sJVNZPrvS
B1o1aH/h5/D1Ev+LDT6CO/Zvm1dsHiUjfkl9jSxAGLY5y3SIjG902uWJyEiuz/iYk7xQvhC1oYiP
9G2YXTWUjPqP3KViq/O6epprXIlvl75MSt34Wu8eQ8BlYCzfAnwV8/gU6A2mSFAk7xam/yr1+Yar
8pgKCWGrLfB+0PGLrrqTjZtc9J7fS75BPeyXTZVBbR3oSV6QJFa4mn3EzgmvZJXXyFWIIyZ5/5wU
pBcG6sL1G49hhMU6Uj+WBSQ2s46sU8rZhfAZ081nTnDSlQFjkUnwgCzDMVd4HVY2XilJyG4o7cPk
q+ErKid/e7QdGKdapbQC4yx1SpWblGuMdjUPy+vEYZHGTnh6GZOm5E0pUKoDR/pwbh0GBX0oBEOC
UcFLh/5jNWp1i/Ng2Y5mhgQogNPrrBn6o4P7p6Cb6UWV7xZ5RDYtHv8bz9zSHndsjn0xlU/8vwTl
bZzV7x3Y02zjsv4NJFaCb1PNZW5c7bxEzCbpk/eexcLCqxPvMq+J7reraqtNG2vX7xrnRUa3KaBf
e8YTcde16peD4qG3tkYWZALus4W0AA7qjB8Ye/MkIerK7yHjli8AlNnXqm/C/Jo+/4oEnZw3UQ9g
B/AkrBB2681aecumBbxZcTJGakO57LtH6mLBfObOGgKXJRvvWGJoxV6rebJJFJJxBm+zujb7aky6
ABvczzVKKu65/F0tEaKA4Z4sLuPuIOsFOZpPnUbF36SlfptatDZ3zqp+JBeGAmMAV6XlFB3lxXwu
tQmCtDeYF0Nt1ivFAKTThAvXH8/EI8XjRw1Y8+p0D9KoJbwrVkvXHf7J2PqXIqhWyhsimkFjMYK2
BVqpTKDXq9owGeSAX12chCLQR8vchQOnhdHKu+IvdGDsTkhCfmlo69QTSCZnirshuof+znOTf+nz
lrpggnyA4wtrqdo2O8hsvCsmPIqxmwkY1HlE63oW4AXvTgIqczsuBlxpIkOqyIP21txkHyirg50Q
cEtAxXG3uADZ49nyOKO/G8vjPs30P69Oqn10GH7yhh2IS8RtfbDDRpA7QUgB7Wga6iLaqQ9q6wiF
8akGbrDKP7sOaaF52Hhn8ZVjnWSVlvTBgdK8fNXbuBO6Y3sX40L/vyGffjKMLXynZdOYKUGVM2uS
OvYDNVVITogQkLVvPfMCC+iBlER72475FonnC5RdwHeZf9qKQ9hpbQl3QJsoraQXc943sceMscUA
n0GA8OHCugoKZ9xAxb29UMScmWVqJC+NQ7QGpD63ptrbeVChcBEwt35Se2aLyF2VJA/mlv3GA++F
TNtptcWVTowmpnNwlckjhpvzmGKeIReVo11vozujLTPdU/0XkdL73lIlGF4x65C0G9V1oSXkiW9+
BhwVEmFhGpMD3x7R1g2jJJboJmFKX661Hvbc+alRkLpyBiVRTMM+H4YDpim0mDTLZQ76lSBLvune
wtq5EPWV0SrHurA38aYJfRFp1zLBgmzR6PHZTcLdxXWOMww/LODMFB3MnkqVhwiPsst7+AdYuqAA
rm0zGMbzkX1GBGra7xDnIDkBIwCapPXdpVICh93va3M0WICuRINx1oAwlgzg4IUR8SvCXwFhdtke
QPHG+cWmpH8L8v6+6YnNQ5tZqAM6mbMA4ld3qo8L075sG0xaodyZhaFOhq9N9paHDnwE7ZRNGKih
rqMuPuiB73ouY1MER2fi5C5vUs35lfeG7Q3e6lvJw3tLF6I+Vj6X4/qpghfC91oFoTmysTBPDz0V
lqCXbjS+aMjnssNN7r0nLWNdlOjbjFgAn8+DCV+m7gwvu0Ft0wPM0yTv9ZXdIfK6G7R351iqEhB+
OARbgYGWprTMUuYH1jwcVGJkJrVjCJpQahJrkdSaDH6nG/lNed6Vz2+fjpIsPPWv1WqRkTgULl5t
ZQA+WRlWSKZVjNIyJCh1ijRdy3LEEuR61sNl9J26itU4OtStMr3vo2N8D4XgKTy9h43qJGpqTsJw
2Y8n8HjHJuymCzJl53axKTyqqC6BRMg8JjA+xF/KPJYeruPP0MBvkO0lkPJlrU/1LiprIkiFnlli
2xDgJhy12W5OpQTILT9iWhVhCWlYq/i03PUuSm7AFbAgWLaE6OVFslFmEJmgWwJUSIM/hI2p4DB/
8rnHryBp1UsDjwHfrhPaa9uGAAvMkt3sPJAopxVSWIHUEKvzOnsJ1DSJ6FmCDph+b1kwlxPqcM5W
6jFWeo5WCfcNf711lhiftbKxIuFtMHHYgZgypp1Z4nP0ejy2BAqWzwOvD7z5ordFEaPFYMIv3eyK
cG7dg89Tu6dznWCGzeM76edQWC2uGYCjBmGFrwSjNp7mb1pnA4sFASEVjEGetKI8tDsFe9sg+nod
aiiSqCyiT5crvcMXRcQDJstpo/78V/8ZFwbybebPDKsBoO0wck/JPqmIArYxX+hccx/ckiwGJHQ0
BK4cBOgpwrEKzL29oCduvA3gCHgqvN2Z+2WCeMPC0wNjc7zQybADJNYGnDT6OXm78xOgAEoj2Ost
nw2zh66/knG35BTGEzzrvdJmbgEdObLItxedoxCYAlTLDIaMEk70GioXT6OkzPxPNRs3mwwuvNJZ
FsEkvFNyN7uBiABe4N8zOMewsrOP370hgRnNu2Sy1c2Jk1uqKcUnDJ7UhH+bsDjXU7JRnidrMn/k
FU4oftl5NIGLJsyNOoFa2GwSuku3M+5xj/3bNKGqFEPQtkM5W1lmyZC1n2A4RbIYFo5DSBhgeRDr
qPcDHaXPvdaJ3N+YnUZeyA5+jiNJ6Oer3qWxh9g4erfZdGzDnjhz5N4lNsgiTy2m8itezOzsG5E7
ug0fRoL11JZqcZz8t7o3OhrAjZ3eZPobO6WUTR2cMUwQsgmGWdZ+RNQ9K2ApUbudZS+mMfJDE183
/9hVqb+WLRzWuiXVisSLh6b/e6ngufNlMr0SOCzoY8d9nw5hDQ5LNeTclgQhAmeWekPqjt/lmW0m
WauFsXt1RJhtszUrhh1oS63qOhlN2EtXPsk5Fqox9uSm/+u5EWFonBodCIrjb7fNN3tP4o+r6A+e
ES5T8kHgS/BV54uEGa9Ryuo9YEFavXV+SLk0AyLSXNC6Jjd85DqOhOg0GXFtKXVttmQFpSaKrvbp
dhWGIIpKakhbW3WaJmvDMQwSBWE7bpUvP1plc3bLPBptHvR1eqppjSLGgBuH5M1y4xJU8eRqJhtt
ZUFL5zkyN4KF+uyrYETB3shylqPDKUA3PdBgn7IskC0xgNrpjWA10aiBYgdaxcr/7oZxjuJbJwSn
6ehCg7Yx1SY65wSQuFQwlBtBE+M8jNAmVQq0rkWCK1aqpl/OlWHlelbZvyGctZpChhzanB0ujG7h
V1SoH9nDiOg8TCQmgaH8izvGsxTP0nKUZ1zja76fx4lV0np+OIfd7iuMCJqPYK28qNE/8xwNtcuM
FiK0ukGpxJKif08w/OhdqHPriRvZQTAiMxiC9OIidBnGpMGuQOWHgE/SpJbGbv62ckBi9djfCi2I
mwJAWIR685OHmLplikh234fOUX7YSoE2SQG0AXsi1BqjAAfKv5ryoHWkKhsKtLCp1HwSn53hOYZv
LD7KIsJW4gnvzzThgRzAibFlNfP3xuFv+FWZzaCQUzWMlJZYNtRAY7fqchRaCFdMoZg1Le822oTd
G65eqewyUNQ0hWnOvoZGZ5h3O6x6NLXg0DUe1pZ66pJ0RmCyUr0pkm0RpnjkHTL1YEkiSUT3f8qb
h29yx+0utOhxcKlQd7nEmWu89LFtC0fK+CIfAisxHhNxNmgLqZEVL2nnvDfYFToEz1NmKL56bQZa
l1qu2H+eJejWUdiaNDp82+UdgdIF6dmcHfk8fF9v/EkDAkWZH/ChH7F59n+PXBDPvT4VgT0JnEae
uesX0Bn0ajHQPXxWf8LThq9ylX71btnDHpWKrn1W43+FDVh8pwem/Z4mUGq4v0BpNUQgKAt+Qhl3
BjiQxLynrrzgp/BvbYs6sGutb9uSAxGBZn8F9DEgqJyjW4Gvlts4Zstg8XgCIupfH6wV6Jhjlu0o
qpQfKQ1S6puErhZV68e8NE8rAKW/PEM21e1NXu+RSJRwQDPCEaourPs+1hEomy2zLa9Gi8lrY6an
e9Pm876pGnd/1kO+RcUsKx46qgOWSV7/Cbf0Kmyz8BYWfSh0Ml6XlVBEjNGopdEMpWK4h1IJhb13
eqkUeQlQ3xVUG1Qm8hkrGrMDssrTUjzscRninclUvVr+dcqi8g4a01xTGsZ/rLFMDz4veWzqEXpk
1v7B8p9ms61yurw3TBSZX6gajL8OGaFgvtMMyIk/GpL6jcYnt4I2LhQci1F1/5ML5/Rf7GoQ1/Oz
Ei1fQOwlFN7CnHssyiLctM5QxCgwgIBCN54yKwdgmLxECv4FuJnL3Q7d5Pyz9BjhTvpCQ7T0uasd
f9how2hXY4lFZeJpEvazOi8TgHeOGYhA+blaxt/aTazgGo/1rMbRHIAkuLAeMyZF9op2HOgpKSfA
0Q5frdJpHJ+R8vltKQohV4JQmbFV8EUpWr68HW81tLZSV6xeVbYlMPPxpyIvYlrGRPngbz2VD9NN
qfR/9yhY4MB3sDqXqf1g2BuSoX7QilLgUieGEhSBy9XsoDoDLSaeqLenyDBsKy/UGndyHxfmU2PF
bEM4mt86UZ6NgbYvp5WjfhPsZwWapRVslQnPCmvPFq+icCT5QFHe3kmAEFpCMkbb+mjE9gzawh6T
RyOmmeeGy9GNNIrTYP6delm0dMCIbyCg6PHraOJRX4mn/y6YzVi7OZL8WMhjqXKvx1Nt9pQd97Cf
jttBDznYTCxaEl4+2D44sE4jPuo3uUKXHliKDAP4gbk8fKWhxcSOKArAmISFuYixjkLs0rRrmjYh
cOr55oUv1tPTuMcG0Kv7mVD/QayFb65S07EvtVJJ3a3wqRdJDRH4FLcdOHffjxfRjWmXAAr6YwjD
kScqa0MVXoX8Htpc+olmyAU1J4NaZCOPEnmO1Pb3M9dIBwFuBxuEjz0tzDfLP4Eul0lgftlIS2q4
hVT5vjnKcaF7l1tslLl7WoOxkp5yuivplw0d5zO2GakXd3KcY3tIshqtkRFGwwUKUG/IsjHQ8tc1
Df83u7Vn0s5h3DiPU8LbVH0VZ5dFAYkK0QhBGq3uODUaHX4mMtqZnipkWezLlp0uXxdZUdMvJUrA
9e8AwtVcCfTbNNMhNZo/sK5bQ4fe6KP9GU5/clMkPc3ojma61C/NMk1yzAVyNY4sdeD01ffPmUjx
NRXCk4TvS3L+BFojMvgAc+3lW+pGE4+pg3be/vEutCc+VJDt1Lb/yx0dnYE+MhIKR/tH2nj4qFTj
Lv+niwD7mwzWLKgSkncurHxFIv1Vya5GPeGRAhUmQlLrPy/jen/tTygGRHVLc6ieoyiBlf2tPETe
v46NnYN2juzTY4IZ7w1KUWsldj4A6P6e+viTxYJZjLdJ5xGAwh1YouiX+JprD0E614xbAjIajeGu
A4G3z5A2ta78xxX5Q8ljNsDvirjTJE8w/KYtnmYVpLQE+IqZLnCsifDAD/2UxW+cpN0iZZSiOjvX
mD3oUt0ACXGqyNHXoYh3tIaVHxqXRGHp63ryqb6ojLbOQGD2Pr/fyQ42YL8bfWtKir2S8jrzPPte
J0XfzMe8UmNQ9+qX3FDD+SpRvH+/jAjCxxdp+SxC9Hf9RWGz9oHxOm2CbFPbZBrL9Mf5Z05KRCX4
I7jNgsRoJFws8XJ2J9CIWDEmMWHsjozFzQ6V5ubP2RkRPpfk2l8Vnmgg7o+/890Qjyx9i/PCZ5kK
L23Te33yFoxQFAwVfhj4SqbMsbJm3ss5snEzzdfX3pnesx4AC2WoZJOdINQ9E5nMFEYs9tAJ2PD3
AxAMt3L6edFmTTyndh1ExaJzXsyX2tSR7YwcfiavZa8gS19+u5FhIlvh7vILsjrwq5wsgzH7nvKz
YZBdCRsTgSrEIuBckjtAciqOvcLNZDzOsuhcY+xFeC3TpJyOMy++jvoPfy6GxULyn6P3quE20SlM
tLZwV13iGfKm15n/ek/N6vDSxoV7ABM6ORWJZRz8EMPQkYi77y0XkpWXn79xduUzgywEDWPl5xWl
qHtFnt0N43HtzC04QpAdaQsZsIJrA476j+RU+5p1Sot+VNVU0LN7SrHgfTg6HDbm9RMFqYlPdF9g
JjBp//5S1/ZLFPIPdK9SJRW/95DqSU8TQ1wGOtRDzuQQ08yTe2IArZb+tEnYasfbS2RZgdi5Fw/Y
g+kVtsMAtkt6B3kU1VVqAUc1lTPFAbA5XxxJZRLohIkLFE1RXS2fu38YCqEzxLfthfeZ867Vdp3R
NR8oTI/s+oRxnzJn637j1jBXHWGiKDnJBXJYhxyrmi8qBv41qbY1fAX1L06TOHN7hDh1wGs1pb8A
zoOpSbnvUPJy24HvtlFuhNBiK+nLbNlJgyD6d5g+fAXd1NSjuY58J6RsJFOT1bmAG7rjBvAvAmz8
JYjqn9F/ipo4fU3vS+DirHdvkuG7K2xewnOQurAgGy9W3ZzJcVp6uU5exxhIua92rrBKmkiCgUZ9
usXPLcCcRn2nos5BTrdp6IjFryCLNNft//ycfsYZimuHj0Hk3sBjlyxjA/mJB9+mL0sbt9D4LWuG
ha/83rtdQoxTzNH7HHnuJ9PZR8qt1Zj+w8Hp0W4lOzCpzPaX8MQgbKET1wrn8xNpzjqpyndzauX+
5UOuxFvyzpAQLZqhKnGLl/aqnOa3OoSOlbHekcuEwPLjCol5GEBk0euWqMxD+9EERAnk4W6HJBvO
NugIvL+vZ+6E0I9C30GPISnDH0ZEQy2DGtTVwCmOzOTpGnhgEOcdWv36pCh0Yg5m79ANVVnxOy5t
k0e+0ODUp+a5zy6dFpg6nA+SrogbQ7NIHmXDCI4yJwQf/bvdzfPxLheR9qZwbPaJYZMGyYDHNIPn
fgdXbo0pJxJPF7d6tsGVB+Zfefwvc7ztRJawLQVyB0xU+qZxqoOMkDiBNW6yuZClszZdbOcMzyaY
TXN6k6x8YA7aBEnME5T2WDNeerF+IZyZeoMpdAeCr3Cvthk2G5TfVFt1K/u1h3DZnmFwbqy43O+/
cyFNh/SzquxxHFDwi8WwJ1MpYuNQX1Oj3XZ5WVVqj7JGgfd2WzdcXhw9OgHWxcteelgiRhpfNMCt
sWUhzqv4W+NTMVXcJPsG7veyFz24gPzxSdwgSbPDQHNowt/6/TLjmPrRBA3N/OgmLguyuAlSXTrX
+OFJIH/nDRafWAhKoZqay961NnasBuSKPrgx8ZZKliSAGzpspxBfAZRBoqJgHcNcI9+1p3xklL/9
0M7g99WFOTdv+Z7GDbC4nXwebiX9DG4ONV4diSecepinrk/0AAwKXTnES12b8i3IG8QFjjdP+YzO
C4YBQcJK4m33hgXi4Jsd0WRidScDxLDruEqzQxOMiIplIOhDXDrPLdaAuYZsNO5DiVtsnOeG7Knq
GVdFWk9QJLkkOxVucOJi9jDSKWNbscbfWmdVXyAwUOvCSVYdWGD7BOwxHnDf7LYhv9ZjMjdfE+Du
P2pqG9M3x8kKoCp1eFtsuw6PKatZqYo/Q8IkbeawH5ZavBZd7ZiqN94rmhAVHI2IzfMQh65qj2rJ
TYbMSt2ijLYw/seFCP/LicTfd/rx9JG+U9jYNIqqZiYopo0tUJA1+Dy6VAj8ah4DIKSP9WZMoBel
1e3YFPOmYZegQ+jKgtRZlbLtmgiBw5PgZmKBIPLI8aJFFtuVvrs4Yi3U0Ts8toh3mJWBPt4Qy6i6
Da9Y+1xlPJozxnAO73TEOk49D1fFQJgPGwGqcj/NyiGgBUMKi0uBAy2BeXW4qaxQMO0SU5t5ujjO
565Y5KaB9ysy/P3GlnvXXpfZdS320ZnzvIB0HxTVo02YofVZEgiy8Tk9+q1GVHV5rzj3TnXq78kc
Xa+L/QbqIYDB8OHyZVdhxgh+Urqyl7bwMUCmpzRH50Mqwz0DGrQ/6h9LvuvQmNkY0LWzObB5Gk8q
G7FDNfizqjMMlz204PujEtXnBtXUobljGiPilOwvlAbXyBKecFzMarRVVTeDrAEylSLR40+g1+ym
a183u33IsgKsrUzrKGqUvPmVKRO/9EDG9JOj3pvxFcoRhN/7y89HXWPzdQnH+g/WHcZKKzHn9Apu
QSlZ7uwOVcyK3eC0r6SDwkU7mxts3YQf/ALlpu1TM8C4HF5qJRk5mzv1AXt0Ga+2s3j9zJTtYIww
NIfidHuhbRKWZOgIcoKsdCV5aYdKYgD2qbfoGRvQBfaDv248D67vF5xDWkv7v9f3hvmxhmutLun1
HOFIoH6Mg69YfeEQ5pgrEakQoatC1XtbUJ6/UgPUubveMP0IyIURX4W4yfskdcA6t8iY/yzk2EiY
p7190MLkj7fLed+Y+Ai09Uywm/mXvLDEnEgH1qGNfkHYZoxOjx5agkB0ul9L7FwcxiPUUf18FsRH
nKRQH0tVPzkFoQhYdMhBwIejZJ5bsUAAsZKtqjfEDkAi/ugOERJsAprysd+3gIIu3ufhxhrClR8e
Y5bhl0d1CQuocm/Ku1+8Qbaua9xTBj6XL8fX4ODlUWmK646XpA3faGO5Ze+jHdhoJ3XPi/Wa3SZQ
XurhSopgUblgCt7ZcbqF3ZwQileIffO7As3TNzuoNdpJzRb1QmgA2HfLwMHeDsenuaRxqKfv2cLh
Vg1kh3YX/n+lbTPdKltpGvZ1dCTG5ViclF0NZV3rC2TqVmFhUUW1p2U+RewlcveUgtUBA0NQvDzY
Bqc3eSH0IOjPn3MLqeaf40fK2Ynrz1/f0jBxG9Bfok+xED0raEAKKuo+n4hjg9GQmTYO9jWpATGg
kNPuWR/aStSiYy5StjfiOSGyZUKR6c6gXK/IRVkStEMa47dcdbmvmy33i0qo9PViTaqMHiSXkCAp
lTmF8/wrJ7gNReUuj/+AwHITxAZGLt92IT+tp+93dA/mQZRN2vvFgWCqZdyDYD3zlrBFdzqjNZ9A
PcvRW69pYF69cufszj/YIxrDSTE4XJ8eqYxvfB6kCgs/AhFXltojmAH0ZY4HO696clzDRUJvaZdU
hGtrAFcJFXJJ+MN5pu/4UPxn6PxAAPuYcVZ9hXNsqzNrhpgsMGOZWnM41XWi6yRsNYjDdPLlBABb
2YdU1kYPvfeddC0PErz/QNtNzGlJvp2MFFy+2+sIZ3O1ZFkh/PCHcgugaACie61ohGHPcbX4O/S5
zJNp9W50EzvG49iNbVgQ2br5IwlxV8N9/PgdBjPYhmfCbO8v02/9oLScxvU2FXXojjtueFTsiZIe
pj/74YY/bI0nex8NY4WcwXCWNeH6M4zSX80+duluheYqIWWw1O5SHRxT8jo/EwQYg1kkGtoM4g7H
83daFGK4a/dhUjCODgPiWICHRCHN/F1ff1u9Rv4cV7JstVfDsf0fYBFf6yvA8F4ITcoBKwFiJ/ps
Yr7jWWdkvRpQi7/kmaufcK1ftjaLDJ3FB2jR0J2azwODfJELB5SkELMUfeJfhgg+KQBW5QjOdLq1
E7ywpOisutvZKsfhAzKL23S3jfUnkkHG9UUNJmtvq3an52Smh4enWdXlSQZ3e2HFMkWNAdk0pFDw
KGckLX8CE+XmhzvNOl6MrT8gNwsBwxmdfbFwZLI4dmedg7woXzG/tdLP6AprUs2w6qAe9pWJH01O
Lw2k67b5ICdSvcj6kLXn6tqgEFhk7HHZbDh3DqxN0fhLmVOAbTr8P2WD6NzcEbZAbwo8IxJNr3G+
OfZ+bJXrQiWwHbTkk/lrsWt3LBTws6mk9CfvWUSIVEx3ad8E+qCLDvaMoJjOIVt+hsVS1XmJ4IMJ
HKJmczHifGuYrgvrbRimGOWzW0dULgX1nLjIMaFWILrn/9mWknx20ONYeutjycq4yYRmHS4pyRQe
EvpWZy3uKdN1oMD2o8zvQsafomR7hPi8B3llDJKszvybxgf8gU53evhDCgpr9PEcbKJoIwjlH9O0
G4/xp9KpagZHBAuKl2Z4L7er81uiP5l8a2ftJrtXB++JiEAnAqGeJqOqLFMb5R505dr+12pu0CFf
DXUnKHzhdJsQ235HCLGHZWLAuWQSm/ORho5L3v5DCTtmKaGCGMt0xs6MdZ7CGE5ziCHBlbAc02ZF
3sF6NOo/itB0MMApBXJRX6w/DlRF0ND4m+SOtt0+Njpu4kLHi7qCulYPjNxQ0301qwWIEty7kUEz
ROgV2j37TiOVqM8ssdFwP+mf+EOdD6zp4/496/5cxBCzLEI01/R/WXbF7GCfy6TLxODWnhM+xoyx
1Kh1nllfal9yv/DZQOJa5QRDRiU7N7XM1AlU69wKX+QrkQN6tWkJ/BvO2LcURorKtmcGFK6dDASz
8kKa1IlzlmpcFLRdiI9KmZriJ91K6rZ8YwrwJNHeTsN90UGenRLTgYWZ7vPuZ5XbbLaNgD79xy0E
NYiHp8QWOT+N5Tan0axh83OgozDMxRmN02EECUGX1wYDgRE9xbIba8Jsp8mIOJl30ACnSQVpj6Ou
4kIm3GXgyjfGzUebu8S/2yNiwa55L8Ldqc2BpZfPXqAwGcYuwsITrBruaUMouAUkeXnSDKaGp2Bc
A8v4b55VweF8CNJH8MieYzDqGSeiel0/1gRgbkzuWi28N7MMU+uscYDPc5FgRlO2btc7369yRIb2
RJLLTlwVIBoeGvxNZfvk7UMwCnTigE707DhKgEGGdVte6CPUVFgH1yithjg9iEEL/OrXPaxRe7Yz
ty6In1Ry5sPNrGkO22scR3Cbw98va9rwSmHZOMvanrQxC1bkqF9V8vt4OnZB+26QRa6oTI+oj7vp
e6BBGsunSrY7bOZMjXedvYhT3a4zHnRtLm2Cld4XGYpfQI+wbnQYLuBlC72CL3QPgV17SqUJfpl6
6fdpP5QutTFD7AJQkt1YuPAyUGFrOW9d1AKU+XZhlagbmJPbKwwD/omNUJilFPD7NxTNJjBsokdW
+TmeDBaH1/v6zBgaXa9JeGRqr2PIJ9rf8SzO/NvulNg6z+IVyHgVAHZARCm5ZqsrPVpyckSFn4ZQ
ZOn1tXIthrKTe8wub0Wr76HmUTm9AtybBZ2x0TOfESSt0mdRbsnpR5dS7MBOAvm1A3VecqWsXJC+
VT3shFYHZFmMrXxm6JrdnvRRmOYcj8zXX0ayyia7loh/FX0+naNj7Ib6DM/dRRaR6dofJsYWUUXl
gzKtokxvwcg2amdSOWF6ZR+e+wZgsG29K+vfo5hIfExn1zUhGpiURKJBApwvEL/A+4X39+0OJynm
dM/C1KSWyzwa9cLfxhIy71pTgJ9NILysaDPGASKUkYRaBoOjlcT1ghhJStIucrDxHpKxI3PvkXYa
VEwRuJz1mHuG1oLbhV4apqpzLYKuTL83867n/81d++0ooMhf7nj3YnxpBjjy0a/qVSsAOkP0c3cV
kRM7o1PRJ78wsXPd+edlENOlNUbusVzm2cEEANyhY8EGcE3z9qjTC1GAB06Yq9/SpiMUNNaz/b9y
pkvS63n+2A6OHMmRbYDlUVn859tKT5+/REO/7+Cv/OONR7Q+g9W6NjF2Vx1qbJoMkEqVo4t9vWe6
xFq9qKH7/RDnMUR8AVgFBLf+NQgoOKEAnkN7TqWQJvZzcNjRMRxr3yAN54wSsIEA08dxOwSuwPgl
N5sWCs96G1SlyJaxDR3FfJ0rc9sVZCMhWQU+ixahevzObTu1ceA3Hd4SF8I7kxx4Hy8SYXhuEEkL
9rlAQ0UtEz1mC88fGGzx8n6JPOrKNomQKJ+vUMPthSBDKHgXls0ex0VbfTtudMPc6RcevcUF2LIy
UyVdmi4QxgdEsNQXrRPXMcVeph1WZLRTDsq7byvtLkHi2232BjxV/aYi+4YgJ0+lFDh0NV1oYG3D
T7uU2pn8XP7bYmpn5pu/tnyOnMZNl9qdsbJmduYcqXnKb2HmHlpa82S5V3tyWNcLhlQMyNBdclJj
aLKN03UHJjmjsBQAJGCtM8i3HHUWGUcpVB9A/9KGY7/jeixg0Ztz7sDItTUf372RT8rN5MqMr4Jp
Y4OjqleT3y1jJcWMi5e/+AFYkUDGtW1yAXXW5RQkbvULgckU5ObCnkVHozFvTpFoMOIzsFJ5y66e
xUOXa8wbH/45GgTM2KZOT0KKCyGeWEZoKJPApEQNn4Ceilw6+yFvUc1z4wNDxFIgPJQeVeJK+tMY
vYl96gyTBf5E4vcfP/O7EVLM6cmIY39oPvrSSw/jO4bIGzdlax7uOYLlEBjLNcEK9gFE9iXUhyAW
5yXPVFvwuQMMbiAG+EiKgdg5duYOFBs7spTJyP80vwv2GGCxSR7VBM9ubT+EJFtv/GxNdeKA+aCN
t+OE4PC7AekElKZ5eZFCzaLwm2POVgyMnx+Lzr+EMF5kf3Ao/03yjQbdVq4RMgaPVGMmvJtoxC6/
YPOv4387Xjze/LQMHxywtf+Y5hcBJsSxxXB16kPx5IDr8Gix4TqTLP1tu7HPbp2zrnVd3pccugm2
bL2RtDvkVJWgq6lWtAq0K/SBAgOM+hdL3RA6wWkgXn92ixf5vh69cWUgTYH0jn/c+U7QeyFONF9U
kZ98YIsgsuV6LVz40aQvXK09Y09IUolpo9sU9pIpBTfbD3Z59m6SdRwwTu8rjwR15FvcczgFoOIf
ZpPgmBpr5v+ubQ57SO22ZUEcKq4Q3GkBhT9Bt/iMqoYscBgSAsDXgaSEpgVNIc6O3jGTsOjGyiuw
qvOGTQxuJj4kyJ4Uw0G/UWqsOURRzMQi4kRixr0LNnZi+n4NAE2uuLCaf6bAviFYlRti8abvVML/
CNYpQC+daKNHJBmcly53EvMQMc1Hq+HgmuNreu8uwdDFq5gOcMGwiSuPkvnQtdaSrMHRjPIMo9fb
NcufOpeTq4NiwvG6HY4dOr1EAzXbEBn2XYlcPgsNpNJZ22KAo72/9VbeQQ2ReXuL+f86XZahAt/x
nEtHLEHJ490TnAhEwaias3o2AcWdYlOGRGANOMK7yuDyGZ8SnySRqWZJj9NVW3EYSMJ9Hh85qL0v
IfUTk6UYvVC+zF9YVLFgXMY7GRCTmM1/jtUY/Fl/BKUIvDS/6/HbTkNNxv9epNe8FTXyPZmcQ37D
PvluEF5zx34wcevCF1+8jaZXYufdcRmyb0RD6XLRuuVnDI1WFZsrDkzFUbcSbsrIXQxYlL7vvWC0
kaqhczb97F4pahzJ1I0DyD97DwpLD1Kqny6HMhT8IpIl2Y2lk+f4lOoKK0ummDLvAYUQVsu4lbV6
sDxZU+HIrOLTYoYFoGJDHxwjknhnL+YEBJ86RyiW37PssiWsVC5eQ3CjdnNvPBEOrImFQuAvnEG7
hbeQSa9nyk6GgWs9+AtuVJ68+G/d7bIrGcVg8mKQ0zvk4O1PHRYonfp6YcR9TxBuMq7ZV1A1mQTC
Lyr2n/hdomy+0tofOzsGOHJZC9TKZz/xMY4zhdOaPR70XhVWcGfwiKOl8FSqVEdE2Nm/sVk8nKi7
WFwWvMJi3CFHXK+qh5VtapO7pn9kjCZYV4U8434zuyAOgb0CdYiIrSS+QkBtirjVtHx3hrifNxR5
fxxy6NRn+kiqjliNOOOtQnYkhw81ZdNsVOaCYrswIczX0EbAzjv9t6ysgOwwp2vIff4pPIaMrAZs
6OIRRdwpv/NJUaXlEPaK5q8EYnbiGVOffu62yCoqvgdMGCKlOtC/eEstXj/3kqHmtSEXi6Sx1U+v
Kj0kOhrJpmw0zsaNm5Ik5ZHRWL07itt9duCFNRiEhJTvtEWsP5t4Gg/m5eTeiTBmXgTEmsv0pUqq
6nN9UKG7/HlO0Ri9uh58cUI2K4cALjrxIRRKvrhx5Ib8YzjXQhWfI4D/Qs6I0WrSXVJK4sLWBXZW
9HYgXBpsEHHxcdqoxAjl6WpJLCPTfvoQBJlT3aTAjktio/VGfHBJSdJLySduFWn+xe6CVHYUR5NO
j8gvU8jbIMQuM+llTxT0aIlKCnylz7V1N9BVV1UCfW0HEbMyqwifU3jXZuAmK2Kv5bdDvtcsL09d
fluRNqyu4G8r9z9oNtNlCCAsuV2wLmVtanXEeehMSANxWSK+r3j0g29hp4caabojiEPjjcIvK/th
Fm/OaE8TToaACzuYPkpCBCLrPw9ujVQntwIGj0ddD2MikctfVFqYOXJZUDcIHEAPb+W5U+fdFQ+X
6zwNwL4NQ/Vadity3JtHqPNTQicxVKGioOGxhe5FmgfYKB4Sn15d5SekuVIvCpQZtJB5FVcP2C4l
Lg1JPHRAsnB8dek51XgMsQjm06Ivh48rv5ozPOfbIpI41yJDa3c81V/Tvhj6OlJI4BZb2u/p4MW7
KHngqYXEnjA811z1WrZVLmtHO4DpsZgQuUj5LwcJxh5Xvaupsuxz8PwHA/tw47ppaQE4A05ozzvP
Lrq+aAFnq2IXsR4niqGukLbLbQLr1IkzICVPwhxAlG7/vEV/jLVKUMGbe+9uxrr6tFpFBZmBUCDu
nuSXCG/x+J7cYvxREc+nzXoEamoQVWOqoUWwY+KMzOgojAPNE5DfLrqadnZgqICW9WfbyM9/g3tN
llv3gOKDDOEUsteP7j8n20yodrybUc4PE0GH3JtVGZSRHLsE26miLWL0dNYAj/uzwqaLhZYLQp0t
TJ3FSMZFcQd4fIFK4YSakJLRRDvM2M/XRFercwghAZcpB2DKRpQH6/aLemijcipdW5H2ANdJG7vC
/agyid0Ow+SDyP9C3lamnceLeDo93ixpi/b0aciVcBAohtLFOpSIuQIgbs3f7WDwRTwv8V00cYX4
Jj5u7D/ZfJsZLwqmS5fqUv1IRBvcFr8r2xAHRxCkDsHdGE+NZGPwFqQmtB9LTgFGaPVdO1MeV0C4
rlVQeflcYxiDQMzxvXXy1e+FX+I1Z5tSoTWIFZkK6DOipeD7NKtPkGjww+laCJoqUjaTeaXAYl5y
oYk4DtEplJZxdZu7OOPt01E2J+Vi0LvvEZIN7l41Dpto+fFTA2G6FM4fbnwmFbTEuSxPScfGtUjq
8UZYg38cEE2Sg68enbP/xK/vB3SsAbakffiHioB4eZTgbSdkWSiSoFoE5P3w5Bya00PI/HzQTECg
zp19v3ad7ppYpeDOWjwzMHFh2EZLHveM3VfRdFS87TmppCCqZciaggvtg8Q4A11NfYr06zoKXLKt
jhVhtoj5+I7470ZI48NPv/Fg6D02p24XQc+UMfxbQdQSlO0yXi5l76EEb+tI3YYuYJZaeFOXw9OV
8UEmZIuJUkERAtZeyY9VGd9CwebcAJmRPx6uHjXXJTAdwKnXqpYJAo/sbJCBZ1I2x+21VZMS6wgL
PLf2vmI2S/M71eDhWZZZnX0i8Asad/iyS7K2pIfts34Grc+9I4dg2ZDqLXozigfp0aLOCqfhOwFZ
yomWji8AX1Kr4INQ6iaaSTsiMaK+VFWj5a9SLJZ//cl1t0Gq6nq3CmqcWhvcPt8vpyHZh0L08bx+
xyyJa1VTAEWkT/sIDCRD4q0VPweQnSngr2Pa3WkRTpNOZZ0uLRv9JE0BspgJSC3bsOd97FnX2Pdm
dBariLHudbCTSUQaaoqae66Oa46iswdJ1yxdhjQ3MHb9HueBJbF9tYP/Xloiy8l/E/4vUJPMfv88
UFtEsS5SPRoFxlVBgfsUMULhoQYsSAfGxXR3I0yrswHSQQid0Z9scnE0+S8Wc7OxIVXA8gJgZssU
edlMKrtehPdTaRVVcvdCvp+s1wdnxOnXoXt0vGZdvxVX7XhkvvnDhh1E9OCpqygtP4RNYGkMhGbJ
wgPQXpAr3076XIu6sMSYwHn07En6HCynQ2JFiWlUBtVWFBAbuUiV+9OE6pNF00hgJ4QH4ew5qOiH
3yFNxNFKSCw6zbFDrz969zEoo+tfhPoQY8PhWbatH1n3tr7Wi5H0ON02aESCxCQfLanE85Ulba6Z
aiArtiu9JRLKQasltu3spxwEjKu3aAzDyFz4iWEkyS1rgueFZ31ZbkCs1s5xAPpO3scOJbAVKtbz
VUHXvRMO9tiUQIuymKUrJ+gfxw9coH82CJB+yKygYRvvAyl410DWARYDnZB1R7CS0H8RYDg2R6uI
mJAeVekLslUtzvgkTr6FWmHs3ntRuBV8pjMePDiEIYX1EkcfqQy7hJqZSzCEJ0Rk3671BCtykAev
d0IB5JkdJ1IuOqOq2IVrt0QS9J/2FYAUfFh4ipDSdogdqmGgm3WutQcTrWWn56TdBvmDKNCg24yN
5E8clEkWyex5yy0UgTIH0XZguvhmRqQa3o1NScz2k3CNlc3QB+Vx7Z1xWmxEAdt31FmxwtHQ96OS
nSHBA9leihOW1fjl0CLuvC17+TjdxRpCcoW+geWJjksjhIMuiawH8qjpFp2Zx5bwiwxVUJ8nQqVu
ksKM4MOXpsTfAy7rr6F0eC3yH/sWkV/omI7M3wCKZ1AT//LJ2Dvjifz8OgeyILFbpy1qFHrAw08L
zMafMQROBu5TFISnPSXvuHUmfJJw9ZmgGrM0I+CW36lBflxBYpuu5mIwrvMr6gmfLKt0Jav6kcyv
ZdhMEPMH2NtPd4VyDp19ir9e9Odl+PER/ob7/QxgGVHodxXkySRx1wLqV1kc+R8OJpHSbm3CQGQ6
cMtwo0qfwZsLXnXvUbV1dzyNnz/kmEruC4+MRdvkQgUaV5sKu5uv6d15AvXrChvkzEua2rC9HCTR
sb+ppILjN4B2auweRT+0F6GWSjXLHVLdANtaXgP8x8E9HRYltAvmwC1jojueJXh+yLao3Qbqh2yZ
Txkbnbijjl3rri5EnTTjHPe3citmDawopKnFmLtoaxEbCoPjO/+j4jgtWloUHgyAOmyzKprRDPsK
L9tAaxTnGCZZ25jVnpb/H2SKGQjnF58ph6moCK4on0NRV3ohKHCiCo6gIjl9L6rTFGdGuzTYDliF
Z5RCPMByzwyBag/iusuq+QddiURClmVMa4jeRpMEjGiGhk4zZo/iy9IySvsu4Tt4fpNyy/UnBZ+b
4qzXMzwll8EKGD7lpdR0TEEXjAXxGmhuuOw93R9na8JNez0PBpSKyhDnVa1OueB2elEQyRDbp1EE
nhGUkEufg4OQp0sX3qkVG9N8w53b7BGQqyEe8rdwx99RxtK/Qfaz5GPSD3W1prQydepFbYZVGtQa
qu5SnYNZ+RpmVP3uwgcnHqedZp1rEnVSFFgMUfRP3Dg4pGiCy+nSx+2ZKUSyNoDknzDTXRohJFvx
AT7COyTkg1BwEsRn1zIRLi2FiWR525V2h7e5nfYScMQ2BbpDgNoQoYqQDj9I1sigwwB7y6IYpHw3
KlDI1SgPiI97255QyUm7nJ5vOtrrLV0CnA3Js9VxtLv6aB4840aoLUr+0M3hG8p4LYRiTFGxAiZc
7fCl9ne0jEDCxmRsBS+VNW2DZFoTpjMnaXANUrpkLAtHlVyuJP1o3Z+Lx6F0VsgC8qhw/xGgQI6X
p6EvV15MdQJP7ymuVBT6bje61jKrujyEo0qaa9dX490gP+E6Zpr/YyMhbx9XLIJDb4IPeSfHtawQ
JcSiV7uNDmOaT7Fo18Jsq6RANcZOeWFvQ47jQAV7MDSHMGhRM87VM7C+wvmaSED8LsoL/iU7Ddu9
nviKYdcPslqw9jOwRUgmtes1V+LcMioSfWT8qWkNeYGMoscNIdCdDZiFJu1znZ/keJ2gOmCcLymD
7tv7j4SyN/sgZu6NSTykb9j3TnHoH/jgpMcKcqhADv4gFEiCBQ+ADXhPKhx9p+aGXO91oJJ4xzvf
55vBbCrGf+B38P4fLeJI/m3Foa1XvFhWbY8FQHSllxGuu9XZJJymc1FbWENyRU8GVE7i3I8Dsx7J
nBi3kHubecpyDlL+YT/gGBp8kmTMcwXjGa6q5m7eG8k4N9tGuM/KEBToc1eRH2TsveKwFc7DQVIH
P6bYf7D0hQK2FhKrUu9MAn9FbAJfxo8Yf494XMV/LJIr1rpxjZOnUYQLBGFhHh49Our6N6ON5Tw+
A/bIgF7FzV49U3n3Mfk4OtizIqcCKLCdZrXZFi7yIpKf4hBq7JkbQSQpLlxS94GeKkwMpBsHJAy3
CanCpjlGlNU6Fe1VGws6OeGCAmxbQdNTu5AwTnZYFmCinD2xJxJIjaxU5Sst6KAgy7aLHERdD2nq
yFDhnyGw7Aa7wusv+t7EQoNvEV6b0kAnQYEYO+hrOoxzYA9FEkiR2fTCq5xvsQldARgPmOJ84Ncs
sDCbGl5UrJCSvamOJTub/44WHcOxF2NqoTvFD4GuTLpFflq8H5Vzvzk7fgXeFAA0W+axNoHPZxQK
/O3P8bnGoNAOQe6ZlKGsKJLzZ7Mk+FUlxOvO99iGdVPO5A9Ar88rvSGKQ+8Imgje7q55JEQHhNlh
9ofuFCI7cs3Dxas86xvwG7zoawoTp8TiZu7QH4ChM+wOk/fRW3XJ12eMKmi6koN06GROdof1H5Qf
CqVyvjh6MYmk7Re3+9BwJ9h8unPPR1TSPgaZEkfxWfD87v8cZO2SdMBCorawbNBRZiTrbjQluXv5
2//AUYYwTfnTZIFoAYK/Ws01denNDtaoTkVnRIrp2rp129TPx4iGRry8d2b7q/PNOApjCLkAkIUV
rlkQWxI0w+kB40FE+qE6kB3sOUyMMXit21xOmowAnpciInkOyWmFtZF8QrpMmZPGRoG3YxcJJsG7
xu4IuzTyGMlJow5Gue7p/PzBA0aTYee4vTKzXiMwzm0RZtmhHds3Bgpj4ZpHx+LdF8oQukhnJVLM
UNG6QpBowqfRcA2827ggHSbFr6PI/vM7EwyuvcuS98/i7Bt5CpBZGglIpEBJ3m62SXdsqTTPAKkJ
yfblWKMczLCltkX0vxMHZwh4m9AC/11I0+NvjDBh+nEs0u8JOOQhNlDuqxS0Dvnx2F/3ElNs9EDv
AdH1Fuy/G9KLrm9iJ9RNSBibXjNtxfXOQZZiOwVyPdClGgQ2BHYfF7dYvZ7s1GxcDNvkcndujGTP
AumoJWNYk11oU3Q8GaHe+cxeejYG2n4sd5iwe7dQDEjixDRfsKpQ1gvKoPZflfIMQaVybIyJlm/q
Y3lqaq0pI6JMFlwVBigbqPKoWURBCyJFubSUqea9+Q+LqGBA7Ej403almRy6sZVqMBify08wzAde
H7QbW67XtdxKA38tCKIiYJrNCsFvEurzv/sNI1DrJ1sBJZ6SMGNnnK7bV5nCvIGMnQBUD7sMXrsq
idj688nz9TDn6RwQwQxq2QcTloGlRlLunjUlPw2mnEHT8KE3u966GJh95gC6jnSqJRz3CNE6Vg2I
gUrBlfHS5gVJBcQv3v8f+GnzWpQM3LTuPbVBbDF2wF6R1Y4pSEiWeRwQTTvbDNJ+gDxsOjqCKwFi
jBJ1Q3SYlPBXHxfIFvSGWExWOQ1dfo/q9K5Dz9Ca91j06vl2hMCOJfj04kpx/zdYPXAL12buYc5P
SdjoxFquAQQqO8izJyBVBillE26w3kFPZxVSevd73uGObNTt0WJrqzFkH4UaxkKfgeT53BRPsC/a
aMX6MdeOJEkjJ342/yGjk+Z89Vs7BVUEylbFaIiRBrYVW/+TaOYJWB/QjmuEC5kNTK0Xrbeqw172
eE3k04BfjTX1klFGobGB5GoEKA1mLK1FmAxYBZ0NF53TtTrlQPPQl6xHucZDN/imc+cQpb+HvO8C
Ki15OO74UciVg8y0FyfdesbTa3l0GbUw3WDmwvO4/ms9/gE1/e+3cMhLyvwS8e9vyKLrimwF25rW
tthD48vjjdwI+P5MZUkWBI6U4QO0NNdX1tqnM9k7hIUteQcvI05bvYKr5rwCL9ObwEOe6Q7YsDgJ
QZk8Vav2Ie7bkViKhTz325IoOmDWs7wfDSXu4Fi6QFJv3tHQ6cEq+iUm9JAbBC8+KeCCNyFUUmRn
ITvuCjTq4wizpaWO0kdEIEOXEoCVJmgJ8lO+b6ixszakb7NJqoW52zTP6YCoiV7NPQSTaHt/vNkU
DpHUhLIWyP0gLGtZTwRlLUxdRWAI91xvyLM2XWMYU0zHkIJcDOvV47DsJTS8TdhbUdLnyufZszIw
9a01cqCdvJkTty60b93BzrhkcFFxMkKmk2JnYqushOSqOvBzkL7Y2hw6D7osbDwsDVgNlhJ7KtZQ
/g+OUp5vyWd7zXI69yG/vv/4w04cVDzUmmLs+5ALGCmyOwo3fLaaudH2gkah0QHqn6c/a2SglK+S
7eCUjKBIUwYBBarQhLPj3b7S7FzsQHLfbS2s7vtahZpuBWH6HTqJDsFoBulD0Z6kfaxL5BFJzv8x
elgQhKPPNHyT23GaHDvwt8tYIYceLA+hc4EBVEVzj9yU0TTxJGUfOpwMoD1bXwgC5m6yrEpfus+K
FGmbk96Gz4fGMRrJzrLYRN/OFSXn35AHg/flZGF6QHT8AwHCtFDHvAa2QEFoU2j80u/7wUcb+WKF
L8AqBr2zcwjv3k/bRyLtJQBjiS3BwDw2Sjxqwy9zJ02ren69AtJLBayUWkF+jnFD7B+AmgZ6/eEa
SopUsTspDdGU/BiB3IeUJ3NZBi+cctd8ny4O6MQAISgsoLPQeT4MBRNOi46+krlEZsa/0KRd9Mam
MsYL3vMjsYe+0UXrTh6k60OLSdghr5kOe3EUbKbR1108xcIhH8J6U8jEAi8iGQpLUP1OOwsBav1d
jPWjuPU8jhLKfcdo7axdgZKr2MzjXupEZmUHv3SZ2eQWGCWhsPYIX0Hx65rrMaTAWrrTvEJRK4k3
YD9/2a4ZDFNTRdrLfJmh+vVMBg2lzZSMmhwGxct179AkUyhGxOXi6ddoaUcbb8DQCVi1jRVjT0LJ
KCqODV5G37pU3esqz5+hJRf0unWsvsoxib0qPFRoN8kcyon7jDGrOu6YEbGCgQIuTpAxSaE8zKYQ
PqaHYoFGj+7N5Fw6VmfqLQclx+OrMvazvOEb5/TO4Ux2FhN/Q/kPETt+KNZeO/IEe59uLQqJFyn4
wz/fFkdK3KXF7WRqdKzlk9KRTaIzd+1AEqCxWqZuqkdJ02MlgtLIZAf94rCCQbG6YivE/U8NdDvJ
W+8di/+V5clH/0q12MPVHV2ax2VWrx9NehSIJUGa2ucQ31V91p4QGumdRnLvPyjk25UMltpHQdWi
D3dooD80w+AGIDXD4K6+MjhvDYR3NbYueqMO76yPOJXNvQ3w4NhIt1iCmVfoXjZsmgYfzRwhkQg7
OndT7Z+PWmvMoLXnGB/fPVR05+BCKSJyfnzuACee/QjcH8D6j+ARQmcBSaVWsKNZnc57t/Rrk0ZO
09bX2ipObCQNTxQ58L4oKQMhtaulr4RQ0XSIzHaAKA69ko52vREMvef7KvOssIHkHa5r6lWqYlJS
z/tmFd9Tz15CVon6VRYLhbpV1JE+pJL9WDZFeI+cVJi/AF/KzY6dqWX2myBhGyJPvnGGl/o7UU01
8Q8waHNmytZ6t13s5czsMiohyxphMvAKuI2YiIrvehlmU8zCeXCImGa/GoaRplP55cBQwO+xISwO
HQlKMdYozaaQX22+Lk9p2yHP/bbsM9LHs5tzXw55KpSl0uwY9pBjNV/IlLY7aIHitpwb+J2fQUFA
RyOVEr3UMrg1TjwZ1S6NzEzYEJQ+GRMJe3STIij8VmTfem5yb6yy8WWfdsxguKm/MQf75HyZZWzQ
aMOb5p9tNCNMs+QP4Wc0kAIIxnrNQRrR98RH0B38ZSE5+FODUwRcTB06NaNogJBlvloaO5eVXxVu
H2WGvmPVtb5c1ps01rVHG0YrhrM1SCpgnmoV4di+nxh3qKlYQPBOs41hyA/pnY8b5Rg6aDW/mrhv
zOKIM9atCbr+ijLU88B4zB5HPAIQiL6B90IfmSxrslbTvleLngvjexnttu3TGRA9mDQI3rCzAcnK
3doUt4jKrBp7nHuhf80DChlP4gz1WegD+g+bT4f7GaC7kfE5FWT1PI1Pk765zo4A/ji+c0yO1uCN
0TdocKM+h7r5Bsqjh4GUZFnRbceVJZ+pY+8U6GBtvBJQcv7Vpnaznjeg+AatUPRz610zkkdahcec
GBTLa64sErlz1ug+8H+VR6elZE+SNOfiNx8kTs1CbWxGyVMlahdRSVQLddVPeGNQkgLx2/8Ch3Uz
g08jycVnub0fFDvW+u4FUXUYrYeBoP5YcKhVYWFo6vErRaIb5n40E2L7H3AKOr9OlU7W0N813Ig2
hd8LS5SBi4jHqqEplAwOYrqGdngbd7agjwlFonv064dwwTS95hoI6k9e3CY5uDNlToenYhmlTF3W
l6uk8OLfV+i/vxzATuD5f/KrqU12TA/9izvkbVCNdhhArlB9SS6dEh0yyR1xDFClgC5wEl6ajhNA
lehtt28N9+OkCflqDcx1xco1N+MKz8Z5ENAiTW2tBo5C4eAUeq3Xm+UgurnijXthXUUYTXGNQ4ex
nSS0SQYfrinRM9NMoJ55w1YmEPSDw++B80/T6F0iQBbViliFDERG+FYn19nHKb75GSQQ7X2HJFwO
2YhhE9BMSUPsv/SQERM2hNjxa9FWoG+G6pIhoT/f2n5b3WuyFyxbPIe/6MxbrAG7n2mIfngLKpzD
X4FBLNozaZVLKfLzYLukR6UdNHCLaDiDw8NC8CvIv+1mI991sODo0dS+DsYXqPS0fG7z2KfDarpu
5PgpWitpxR/9+7beClKaxsG2+W4LYnWmVvSWGPxMrx0413JFW7ngySXZS6ukA3kfAP8LMBv1pBEp
+4xL/901Jft/jtA/eCjMUXmNktbdKqLKkX209RAJoV8NCbU4mTZTFiGwhVtt/wYFOl6x6Bk4yC6X
zNZT55vmjyv4KY5h0zyqcvaylWxMAif4hT9CMtELdNHgDKfpXbGd/zFmqhW+UZYgst13zaT7kWB4
rnQB7STj5QkNA//y8kvy9W+rmhFDd1FsCMJ8+FzRG2gWy6cZ3HFBf5Jpp3Bscq7g2wfOOyoxNFzo
M3DYCN5f7PgC2GOIB0YZ7adInEFcEmyYYDpERVn6XTAjYI51qdMav+n8NpzGk/VMl7PdsacQRV3b
alLddU9QJgaDzrIHcTDoAhtvWP+SJZbbX9B8J5KEpyRY7iG4uGAMNb4M6yvkxs8uoYrXoydb/3HH
UifhX+dUX9wdyNk8OnEs1Rjw6bfGcZWntFYQDQ6hvl8ncVT1AcnRNdYjTJXij09CUv7yZLACTCs9
u3gQwE2qbsUu9qn0CNggQidHcUwvLxj5O7xyC5V6nSqqwySHVAvHxCaB32abGzXMyotOnDPclPEU
FvcX8lg/TxpWPH7nXvUIwIvN95s9EWyZcDgDygsikKBzfiHSq2ORONhvMqtzDnY/kuFzlhcszzHX
jIlTw/y7y6122/6jGDALxaB1SjcF/Jzi0e+zWe1fodcBFKiULUOxT7UnPmo8fT8vDvZWZlTb/RqK
IJ0QlB038c9rPy9YYaS4VqIhDDG58Sif1y9CtO2qmN+Sth3JoIK5DLIbqODc+i0lnyExWvUatcFv
Dv0lLkB/I6nrrwgf62A8pw+T5wLbtH2hIVQseEYxlUR2VhdpSyXfw90yajjZrRT+Cq+bIkuy5oi3
Y9X2lcG82sa0js6tE59JdUy2eNCJPfJaWsBCEk4RjpfoOUVZlmFR7UUOR/wXL5gSLrvmOEd70JJF
XfQ4pLG+Fk1SmH+nTXK8pR3z2Uh/ZWPaE04GNiDtZCnDRvHWG+8VBi2w6ruTosnPL34ySAadqHJU
KjuW9r97M28vrl7tGIzebH5hAvJtq9U38ETIens1qbAo2P9nf3GJiLyHLV0QtXbiK26wORM56imU
BfXgx4RrlaBTfvle82dRL4KVhS3zcpA8/ptu17CL1m4USDTu4FpDYKPJLkX2O52I/pFXn/Yw9T5N
XFfztwhBL7std8pNYsV3ievrSf4mKsPBo1O63V/pSO5J+HroCbdqGUb6IX6OZ7hExGABC4P4eT1Y
Buja4CvlkD+ncu8dnsjpWohRdol8jhNWcVW8Y6Lvm0dLncQun12ms5LI2V/LM/9Dx02qSHPjUyH9
R/gJSdYVVwfVTl7qCwYsyTCCz9d2hnLFZ0AicnqkLqzaQywaLaoSXhqkMlb+YvjDPXpI0y36s9jx
1CtP4Sn68zIYhoY7V4D5BpbbrIza2fPn31ZS8ZRF282Y+le9jpgcB2evdVHLULe32UaiZXF8UhDD
t0d0Ek+hzK1LIjmGlJlERwcC4HkEaR8X9wOCQMxO7W6OiHccvys4pZ3J7wHCaXN0AOhoJRwuGN4X
CfR1+zA2V0/1TC3rk4e1lGzDyBgHTHZ3LIewdwYUte1qosHg5FHVQRs8hfzKL8guWtQ+EvVenTo5
fvzVbrvMUBKIVzW0EXGZittqIi/u2gygNudlgcXBWaKfkKBYaGwkyoAb40DdBy7gc5i3t5EPoeQG
p/HVR5P6DI2acadkZkD1zedcmiYPV/JEjv4SKGZVSA1e85eZJQOYk/SG0KBYVnbkZRag5YFFDdQC
RfbFnuhHnlGfqe0/WNgSBU/RkUF14pZKW0hvDrC5OnvHtdjo74nJuL96k95wpPuBR/zjBXyD1YAf
DO5PDWkBbIMPm9/pkNv/E+L574HEt2p7azjTSzbT8QMHP6qy97lD8FY7lUgdSaVKo7z9EZb7+Ihk
eWYFYI+uKfJGOf7+SGm/PFomatoRuVuzcje/7iWyKkIeNzrrqjmo6j9cYOSa5poDOfwit5MtfUnO
5fa/YkFiwLm2l7ntudzU50Fn9X5W50bwPueQxA7eoi0Ii+IZsSN8G0D5dw0qyjSKdnQ01EgpUzag
j0JPviNaJo4nn5KUloyaU0pYM2RbfkrgAFY26XzKgmqZLSEMHRYYbJ4TrNQow51iOaVEVllQ6fNg
uoL107nSjhTeBSEkXLr4XbxNmx7qx7kX0nuwxlGOdWdBtjNWDMn2Xy0H0e7QxW+y3qb2i3p4gEPU
Vt8ntRtev5oNrwCLUkDSaAsdQgqVCd/stOpRUyS47zq0cNU4yr2K8dfFyNuC0W62F87zEmPoQLeu
Pzz5oLnSObAVcP0IxEaHgJfMBssX7ZkFEwHUSlOgepZTB+zmPTG/V4axbo8YGfDxKPICuMjr8yF0
af1hEXirnyLTBbAPH5bQiYdHFVZv+B6u0G+UapAyhbSzek5c+Yd23ovmdR0GKhIzMNB4jUTUqdyY
0jGIbpx2eMLr10BzXr5rrN+aG5Ho/k/Xz2/x47+68vev9UcLlvrdq7NUXbxwnYGw2sjpdzPvVeKG
5nhcODTcekVvuAsd0a3rJPfR16ceC9J7imHpIxQnfTPvhHceqXal9aW/fR8OuNxXa1+eRtWJ1E2L
M5xe2/NDvaM5NWsqTr6mGcqK2jZ8rNRk1txSZ2NXtISSUVO7XnjECMi67m2twOSJDf6xLpNwvJVo
wPJcHi25t6Y8v/d8x/+Lvwb/cf0XaG+en4Hk5BziZyMnATzT0eNmHKgA884fX/PNBfUEI15unuxE
P3ZRujjA2wdU0k/YVOCjYsw42hf+OBmjhmjaTXMjBJ2ec7TcFUhqEuIJJDz0oO7jl7lYYdj+yqRd
zEsxifuh3N5OT2p+/bMVG9pD2yVUoi7mCDggv1cb9IHtXvJAHMWBAVaeFpZwnMQnC/Vy2MflKiwS
3xhsOzM5FukIb1zz1evChTT5WaTTpGZ3rfmqxN8ikzGh2vo4b9e9zqkoXpSMHZEwfPOEF5iIhHHK
Ab4tHVKBLRapQaTlQOblIlPKijIglXtOXDtnk/MQQqod5CyZMteFv6QIoEXUTLZfo3G7TcDu/feu
IWoExKN4DWoFFXo6gi3qnYKbjgac0TTR5PEFYLznlZOxsj2IrayTbTkWKFcR10bsLtaDjgmEtwI3
Sz+eTIm/m+BpIccpgKw2g1e1devZUI7ckpcHtzXtCGpjvEhBVrmLtQe7Ljuvn47eoBi2QYYou7SI
O4h+1iFLcSQ8emJ8sy+jDtoFhV8pT+WDYesCaIeMc/YNpdur5mcdv0DKtha5CBov0nrnOx840BwF
1bPDbdeTBtPgJxsj5YaNI+RJiHExHeZ4XK333Swb/PUVtoWmOysejeuzwe5B5ckeHMg9W3P6GrZE
tiFg3VJ/+xLZNsTdQZQoAX4q7i+yCNDguvNxj4sR6NWtccb25wSbHikPmfesjLDVDqvkGg5MYSvO
JC4Dp9helLoDUf/7DqwNRAUQ4D9qj5/FW4Wleuy9GA/ufz5e4l7PWeDwPEZFq3hbz1+rJDCLfwPV
Y6RE3BB2GNiWYPCamCY7afpQjIcdpdo5yrRhwCoxR5aEePMPBKHmzjyUu5cSTo4R/7EBXuf7qsTs
zvq/z6War7X5EOAg8o4+e5A2GrDXAwCHMxFdKXxFE36EDZoACwt0JTgwEDnSNqN0Hbfe8IJ/IJhI
ZlZ+xGZPDa3NDIVsudnrTJ2r43ugiMHvxJM9tyR73IozXddetGSvX62XpM69cQqrGF82D5e6s203
gOxNWuGQP+TeWYU9ym3lZEXm8XFHMknfAb4WKWK9CgiFHYQFW/xXANsnF7ix9yOQqT/k1exp75sz
zS7jywbFY5FdPmLpKXtoGbAvbMsGFQnbajyAl4HI5ouh/T6O6x/P21zjkk4LfkAtESjzgTGbnw5N
j0naBba2wF9s10Wmwjot8oUGqkStVl4KQM432uE9CAVm7y/xIRhmW9JW1NejtklC/CMT75N/ZGtU
RfbxBFBmzjN4R0qucybctQ6ir7YkJtfPUbo53WQ2kmWk3PQtXAJnXeo2tSaKAuRNcxF0NUFCEdM/
sFfXjIzeU0SqILRb7RfNwP4hSgwJ2/51MTikYbhYrwhe4yoP0oUbrwEHAtB6VgCjMRB4F2bthbiX
tgARNs93p07qyvA5Cg3tMx+WnRAfTnaTq4uK25rqHQmd79aLmhSC5y15MppAmc+DzUVr9Ii1JaNN
+vTnWA3QY8kRRIBps9YPE4OArKJoRMICU4MDWVNYU0pZCXCLq/8N0aSBjH1BqdjC80DDc1m8uczh
QfsZb6lueU9yk5PB6DR9aIJ48vKpGq9NM8JNBp6sHHbdFFN0TvMbARp28IHdBL4Rhxf8geQoNowj
MOfwqLnSRVvzfYQCaSJ/pUq97Z0IONRLqS2bhS+0PcW5sg46jq+pBcq5+L75BUCoOQ3SytcLhRgc
mpNE/aeJuUHT3I5vIHtr+rUF79i7jttOAu7RWftG2kkNUIurPHFKLIElF0+lS53qmcGXDcrI2Ze9
QBFrEDxPNttXPIU/qvOQJC6FwpzWmryMDm6jquEahGWTa5LsKv9yZ24yQ/NlsUF6/MmvJfIEdt2o
LG4RpuGKYscS01IaAXK5MYxOxtvT+rFadniQT8CEn0OdiDMBfVlFN2TPEDF+kS+fRsqzvJ2B8v13
pK8UkRR9GWpfDm3FLEQyIusSBr2IhKowaQA97ubqTMNmpSvGEKUw7b2LTk2zzxhkubqBQSk/6hkl
LhQjTJkhiXEgBvoimR9R9GX5OlcA0pl9QfaIim2HVZ+cOqY42LJw5hFNAvlI4A/cDf/QfZLyBmVD
qy2hYBpP+O9KTWAv9iyez9BLfTEW+80x18qAXH0xIspARIlZlKageDxic4oy2Yb99h2S1XATW6x4
Uwwto0ADgEGjdY6QTOl71fxAJlFzAOy3EVk0XEgO47SATtS8Dh0fvixuCnSGvvWmMSenSRJG5l+R
LUjnBddoRpMR9Q4L2l+gFkyCClheE0e5yZSyZ+k9EewtarBme7lQrYiQErJuUWpfeHjWnCYj035a
sE9cyhQpATHWeQfESJlqQ0LX77+/YUx9Oxm8pNdS8OsA5kCXK1hM3JHCchmsl8ugctGSIUcMb/r0
jPwDfy8r377ki9OB+fAuAVOnKUeU1xpPSsRuJNFhGX8IWZ7Yw85BsWYeHCeHSgn5QYz6I3zMXm+V
SDaNM/8ml4VX2sqJtL95luZrCYH0/FF5OWRRr/r2puiHrGs5eDITVJoC9hT7op/MG3lgKLBPvsGP
GskbrbUDpSNNz3erb7t3vT6Y2n0JA62J+OOeSALPJ41+MeMeXPjp/1/N+6ykevuzO9blbGWKErI2
YUsgTDJ9X4hPOMVmr7quT2fD3C1ZvWuuBjJmEHP2p8vgktkUIDLQfS2LX0/hi1m35bVt8oyNaEVE
j1cdu2K4wz+WaoPrqdps/E26vgRTj0ZgfOsi4u7oSGZsLfdXmMb9c9H0dnmY3Cl1QD7rTb95WH7F
r5JTDQzrpRCWXk4HDBP5hUpTXVzZvODQboP8JGI2zdD0PxwZWPRpxXnKwQIsrOGNFMz23aNKs22S
O1owR0iZzYce/p3AraoFOh1Pf/S7uHY1HAaJEiNS+QPHapM9mZD9ibTIJmfQ1DrnyWgW+NPX7LeT
qTSxwHpml1aT6i0ZDqBH1ZFD32anLcwUIRTmc2K1ruYE8mjKKUAi4N0gixaAWWRfNNWlntyXRo/+
iYfXvWlrtEJQviGCmlJ1B8TlLG8oQ7LUbzjvHy1YLqRaA0rvJNFYk2Z3Lp8eSk4kjjCAEC4gU8SV
1dC1qHSvqVJ5U7LyFf50Jz9bG27zI/6v7Fst3OcLmgDNvvqBBteCEr8tLUbtUjjF9EegOrGUEhk0
mbaeCOQgPBboc7JHs712JZrGlKdSSbv/nXBbAvof1YQJomeo3H4hIbWbMbmsu17SUOBvXo+7U32f
Eg1IbgU2v/l8uIFT7r3Bzwf7bCcl5tQBoZhBLphrdOeFxdqRkIsjug+XFbBTEhSEwoFrlwW7PVU0
CDqQDsahX7DrbmHlJ4t0NxVSCeJw8MnLjkp8jWl083nn2AYkDfeka842zaEYYCO3qzRRVXrUBMXA
i8egVA1DcajSBWxCwgNY3lhO3PPyNh3ec7bCxxD431dCEIPLAtSI3qsH+XZCpP0WUyEygyVM5bZ9
y7KkZQIfkiqOBvguFUfE5KOuS4CaQPOcNncq2tPcQumUXNQR1xWRoktWH+/qmnvHWyYXzcbIxvoS
HCPQShy90QYN+J0lZI0drVU4EGXEDOw36Ahg9hB7jXToIwlcgOkbF/jRXEdgmCK+wodmt6m9bynG
mnnnXcQPIDMXL9KrM1O0HNeJ9qNR8o3dV+tMDRH2FDiS6Snqje+BCOWKDYjpYbuqTAQAlO2emWiz
M3+dORnI6MlufeWIotBEaTW1+/UQoAjglmavQ2XR/jISXk0vnKbHbRDUZHcH+O8eP1tCticj5kKc
u2G4zvIhDtaAv8Ur2JLHRq1KudteBBr4PEs2OrYAAnbUd6vl+XmYVxUo5VxtbEoBZfnmenGninIa
TS44D9SVF82djEDZF5eg74QdmZhYM8/6J6w1th1T8MKjZSA3w/s3miZe1wz+y2ijZaKQkk0ppg6/
WcCXAfRnZzq2E5W5bvD+1dOdHlx6X3BAY21seDELWPflmJosn2WkDpwyjKqow/QkqLoMnetWDkAd
XVRpZiZPzk/g6tf4KkNce/Jxuw0Mlo1vbLcZZLEd1kShFgHY/kmo4UOTWg4Sn39rWDakK1GubXme
OVwpxL9jCoymaVKQa+NNwNvHaVwD80rIvxPMUdlhIU5uUVOBlDppK114k724xBWrIXesi89K9nlL
VnXU0mtsBkgYuCPu9DG1IbD6e3m2tzHX3vso6piUKjj9ekcdmJy+cFryPlxDuijqQqDELS6YKJLy
fWBt+7dPI6ea/l1gtFZEq/o9z3BxtYC1qJWFZUZJdCW5052uw3QLpdFYJEDtSa0o3UVyjECstWuY
iTZIueoEBjZDJL0YAed0rnAsS2ohcU6ihs5VkM9ZZNqDBw2CVTie6IpcSeSCaa6LarjvYt55i9Uc
NAw/WEvtUvf1Uh9gDusXz0bUqzSsw+etlCV/r8Er7SARyASpktz35nQn3/K3USBoO5NI6e6r1clr
10mKJMwMxpIXYsWhG9mgHoo9gRiRio9cMUE8xouvNLcbE+gaIVv8mzWlCS8SjbXORpdSR0eoWxd8
JCnwd5W4SXdKWzw1KufSY2nYwBy0+3KOZC50vzDTXXBtl5wRB6xtvb6PmIAHmAl3RPi0xFZzCH0K
fJCQngrdzgI3zYLIS440VKpokJ49el53vhCJUxrxYiFjXNlrVOo/dU6wl56rNh/p9ERdUA1ITqea
oAYXFeAPqCsFqPod3toP/NmUDEBd6mnFeSSCMk0dcx1/n3ctz+em9wI8LfDkFDs77Nj2KBgYIWa5
pLK4tivz8Ta197iH76eK4CAp52Xgpbcvi8AkaYTGcarhQImudf+XVTKdWorc/EahGlNr32hjlsHQ
SO3ORrqvqdbymGurCZhGn4t51Gh3JHjvvkWBvizNlDWaHz50ph70S91YJB6YCjhfUISK4O5UI2fM
DjV8S+h8DB8t2Vs/GGQcFxSvD4WD9a3M76y09gV38qF79BBE/BSG63X+jD5c2H/v7b0Een5v8V7Y
48QNUVYhHLDD49f3x3j88NchaLYUCmKugta6WG5I4IlhvlguQfWeV2GDLGCq5gZErZb9AmjEg8W0
ABfd1RG3Wsh/1GyphpyaXYcjugRkthxl9eiLGrJavFpUkfiAX0XYGDjMmVbcsHHKb23fRdorpB6s
BdYonH/jbvDVLyqxQ9vRIy44I/XVlqge3KAWsmYylwQcE3IDllDZVUuP88FDoTY26hIpLzjDzsoV
asJDRkLxYqSI3eM1Zq2DcjuEGm5saVLeomzYJeGCfnxSGDrfTrGrAVj/8D0aX+m+tlvLjKKztKnH
I7VKh79HQizfqp3eVOgbdWXvS0GPVb1rkB+tSJsgBCnruRqfX/9ZY+/t1QD4RWVJTI9HCS9a8zzk
1g5uTqOa5+s75EjL3wHx4hz+pqOUW91jh2s3B/W8mPz2JJr5LIDtk76b6yiZoautqMrWKepFNzP1
wKG3XhJr5QrLRcqQvE1yjKQaRZsF1n5MtJGxcuw5cquSiD5XBSSraEg5RKd3Loe3cbq4kGofcTA6
5oe3M+byVAuEyXuDlm1aZNtvJWkO8tG3K2evt48RcRfelgErAyVUNWRojtgTwbmWAOesq1p7C4b5
D/Newolm0mltevAIJ1Ts6UU+4DMyn9z7B2KeYR4AJOq6mOmoq9qDCaA48ScMN+0h+hypDMwL3mG3
NK36MiAlb52SRV0PUnJ84aWu9fHd9bwIW98ONgQCT76gKRyoDjta3gLYbtjuQTFxxn08h2t4m0+c
0PXqjkzt/jF9M2D9mjPG/MYhHH4ylModHFFLGjKiFpXdmzBg5Y8ms8znX8xMqJ5uJaT4gKsjjWfR
LKNaDmGcXyAlUmJtnq6OHuR4yrBqZGAIqcbTVBE3xVqtyh2covD45Vt4lb1I2PyG72jKI9ADRD4b
t2wTX+DC+Ne+wr8jyhwj5pDAl7fUNnbsaApGdd1+pi3M/51bdXT3i42PyBA+PwHSRL7SZakMnW7b
mIyG80eKioMkPP409XS6nz2MW8be8Tu3X7z0LlRULOdiUQPX7Dm1RDjYPIBmuTHrCLNk7XL0d9Fd
X7BhvbhTwp3y3NFO9QtqOHym4LIQmjcvm2noimm21EEGykucIB4nWvS07rkmTjZ6NcMS86okI+Z/
kKAxhDXBEEO3cGK7Dy7dUpBQmpSVpfh8F7R2J6iRZwbhPIQhhD/y/961WBBCruB6lcXUvD6iipjY
u/q5JH4H5yVpa3bjWW5k9NvEsbdPizGApZ8/gnn/FhfYKfFR2pNPIbR5nSe+5MK59u2tNKWmaPhI
/OfiQtw5AzZKhSttUtUiAgjykz22FvYiA9mU2HOpCqsTfize83A52QxiexD8etUm0SwhnhWgumxG
fkccrcD7jENoPasK93WOnznXZHdwMrhuIM6u3223Ke4QUqPR2TeoJuINIwrs8JGG7kPO/OUwD22T
yFEdP2BwcxYY143olgODedU1N/2FfZMjs1vy+qOPgty86/9vbSLKaU/tpyh2PD04n+BWKDTffnpa
ZgxeuVTuCXrnL98eVfgOb2WygOAEOW4uMUs4ZcMSQDOfsZRIq2luHnOHL7+DTpmdtk0fKPTPReTa
0mzvLd9K59BbFhk/vBoBkFjaOywqRQwH+0EEykkmBFssnCTHj6QOt1vDgKsuy/F6EN69yBGGfYvV
ckb89vlN8CX9m/ZY8Ob6P4zqZ6ecaCRK8XiEjhPajF+oH1GiMk/JY3yVr6k0CcTuaYVijjfB9Rn4
xcecRno3nGH+6cKZnmxcRHcVq0NDv4oQi0gM3NGkcQAj0dsONoyWB7M3F6BTJmM+mAaI75fw62Qc
KVkwWm5CT3c4dT6WSHacF8V2yo2nV/6z3Ywc9klJWT+ZdpwCjJQmNHxwkzmI9AAD4o2WRrfgVjt6
5REwIkwG64Te6bsus3q+HtYjVUL8ZS1OO08IfzSU39dYD+hRvO/5V5pY5DNLQztS1f/rM602La4/
yErmFW1NxlkXID1JKDVxsZrSmFmoG9tnYYZNc2HeGoFB1XJxE64Ein2nQGvqh5UrZ9KsKKKbKbC7
SoMFhbx7EPIMJBkPp4sPV4byo23WUbJKqGwzOUmW6xAw5P1GOdVNLWa5B7JzvU4w9fXSAdCcL9bZ
fYAHelIE6SGlksLtmZUSU5sY2OjS+GA2l5Z3HbQ6FuNmj5xRyas2gaAONi9PyuHFfBDaaB1qL6tj
u7VdpXsM8LVGoQV+kCEOWgbkiVW8IxieVX6HJljhcX3/k4ehTIUkFFi9wvjZCkO2bvPT+qZ/3qAU
8Mun3ekqdZ/nLAFVdFhoMDfT/cuVpeQiC4TztM4G2g9Y8xbZIQU4UGj4eoatx/o13k2BcQydoyNe
VxcIjeUYsT/Z+4ZKl9oAYw5tSRXy0kOD2g3WI2EZPv74FZV+9bq6V043Zv5pqUeY8iOT5HzhP4jK
VhvUBiQ9vIZ+76QyVSjbJ/4uyYe0Rn/Dmv6aK4+REHn+ULeqCdMW2/XA3MPa1yPDzmT6gqv/W5Lj
ncdNIisujB79+BQnBz55w1ZLYUGCPugpF/nQHyopJ/5xEN2UzqgKKeOvsofiUtBaomkWvhi49ASS
gCWcASvZnDPTQJipBOmdw3eEua3aUdNXEqCrwj/vVueAjkGWTY0VQRMKgHPdF7C/D/lf0xBsbMTd
1bh8oNTSTYPvxuVLnsscJS1bY/OKyIdQCRdmx48Gh+ePHc6cpxk70HqTcAwlCpox95cfLzeGDWU8
7Nb2MZ8wHVoZEbIQ5NJkEEPzuRE0n2+hHboP3xx9+BTHNM7hW3jSbtA1bZzWM9DQh8NuLWfX/85W
PgQG6WmdqlPW2CHAretx6TrmIIEEJYGYAOdJhDRWB1fFPLSnrWBRJwEuc3TuAaDXFutVCRkgDVPH
LceysciYfr3CWOJprDwav9AfTvMwpZLzm82Sjop0L2FEsMfAPuhEDwbgUXVIf5td3Uj0BT9PKLlO
Pnw0gt3QpDpABRGrta2Z70/45TrqX/NykhPCpFUwKnu6sGb1FafJ+saNZkSpazdOi66ZixIy+ZpL
6lzI6oyfk2IaZZFJnWXHHOehF+QhdssIzYMM2fdlUZzGQ/c25QmaHRjHjYUbqhuBur4ABDXVoiKG
fniliKwLva/wgR0SfO9eSm6oUKosRbVitu2ejEpXzP84LT0Dyd2+/rA5QoEMWcjlBZ2tIKKa7Dfc
9tyD6PseuV7tB8tr+5Tut/hJJqNXpfzJ/NmHFTDcjmUF21IsQx65FWDhxJBZZ/M3OLuCf6TDfhlF
+AMKdloLQT2GWWt8+SYsbGMMQy56CkhHKbaw+3iWL51ksELGmXGQy2xjjqHFE8Bzua0jIutpd3fv
YgUs+AgaJzsSddW7JOmxZWb5jEQ9VD7bvHgd7biJBjEnC3Idhjzf/eLXPPODie6Ygn2xMp85fYhK
AELEKMEZyjKT8Q2szzVVXmx2QHktEcKIG4RcKpRpO7m4G1XSrTshkbyYxdDIzUlabeLVgkEFVKd/
y4zBns9tRDMyI+4tHZs0KNJ+rCBg4R5qzQEumh5h+/H9sMijDwAo9H4GXjeFHjvBjIgLVcbDqHRY
C7/xj+MUoaMUw1HOMKSOQUUIpbn17D0KUBv80yKDoxfO/L2ZGrjz304LxMRJtTsAG7Gk5Nd0BRgq
dTllPByTd1GT+rnwis3xp9iyrjzhXvADzaAkX/hHj4M7EGl5zx4lFEpZb36ZQZzBrYfBxSDOi0gp
RZ0pcXg/IIlo3flFy4hp7ou/D8GrWhPiQ6/2nMNx8uEu3RAfcI9dKvGNUqYHPBHHE0cp9r8v2Vyc
YYRRUuuPIxd1+DOPsYnkBCis52R7iwg+g0f4Gx891IdQ+QOHR+HSYSwGo/cxXYaIPys7QNfxJ3cy
Ud497TQQw64gT2Cy4bqD85jJykTiGSPoEL0+EVEkBU1aVvJS+JLyHtM3VF1NJO4tz0vKPN1AdiTP
PqY4K+4EyjPT71X0+N6lWjSu07HlUpN4XwYiBzphroxDjWY2Uq5CXPasBaQytT0OMe7/CfXmmwQ0
glaMcpRRJplvC3X81fF8OsRZAu7dADLJ5oBNHKlXpFSDLVjsKFyohpojG2FmS4wlhW7znT1AQHSX
Jr+obNK+EaNPuMEzfjRdIBCeWysCkjj1blXZJZNxuIpOin77KwdO/fDWZ07UFZ19fU2laYP4R3Wp
VOdl78IRBLCNHiHdZgtwwd5w1htXAgKtOexeItGaCdDzrbOuLey3LWZ22VoVLV0U+fxa/D1M108u
t3A5uWPVuJEMs8XBj35FXcA7eewUcsS9bEFr8xo1+/4i55fwC6Yk8Gv6qRXetc7D1Ut05rNM0zW8
dEgIpTeUKyt3f8ZqcfFZzJcWTnuGof1NkAhp4oyyjYBAeZBg+cmipMB81NYnWrCipT3vx8pa12mp
CwZNLqgbqNWDY0pT3gQj/T7lS77jSxqEL3BNWZfq80j6K4HisNw6mOC6mw/eOQm1OvxN9tedfGHD
5S/2Cg2quqhTqVbLIvcdx0eq+/7/Y2ATY99/90494LDwSpmaWh8eHOu7uQhZgc7mSrxx6iCvvx+Z
KnrGikF6Pi1jaUQS7ibBQMQtIeeLc2EyxaoxY4kp2xkhoiNUvVbPQUNI2A8vDG88ZmT2RQYyDogg
lzYLp4QkgYgXcUwxq1YE3YaAN8w2iKwCvfur91X7nPdv9+edPAFGTKRVywZumMGtNxmOxGJsj5Sr
ornOomJ9W1DizB0sAuxC5gct4DSpcLu8hSFGLcnCJIjfy/dLq0dc1qFnorsbExNafn5SbTcI00rv
Ykxcvgg+8KcPqRXZxdZmKgBfCHrV+yGm3J5kwqzmGT28YecKCztdbm4S2Pvt/yc4pQdmKNMXR4Nd
nv9Bk4J7CisNoo7Ql4NTgAyYrtshyXSjPD75+fmS9ArEJ+MPOPOSoW3UIrqYHm3VIU/1vw2kILqr
mXcl0SAP32Leo+V6fkKx0l4JjgP/MdHvYI8cf7IrAsflCazrlQOnjYjjgLZnBfcwShLa9q1xMkzy
fuYGLri5E8FhoX7NicuP2QPih8PqKMQfsV3EI6LVYxNq7nayw836+dtFtQox3JIWHPOLacy6SpOJ
BYj98sisc/TKpyq5lwfGyvTQhu/hgDOwsUVLQ7c4AjMMyMPPfHN8Y4Z+yf6DM5YNVKu7sQzrn0FZ
gIHG4wiSfqaqgEkNzbXVfxO07ilfwjYDDwC2KkEQy3ljJSO3LgKp9u1hQvx4G7aomKf72UQszzTP
eMvzBvsdqffI3CGmdUT/NwbiIQeTWSz3rkd3PUzr/l9qWIHAodJTFAPTdH+bVivHUaC4GWBse2jH
ssnAwjR6OYhINlDKf5jgPe80RAVQ4/oHRb5ndFGHEOUlEW5zb5suQduoQ4bI9iiBD7yH+j6oruqR
zHc98P6dMq0VblqtjvoDjPopwEZ1/BoU2+xb22btsSdQLiOS9Eex8sYSRAMyCRXrsbWR4PM7ouSp
unihWuGWMaKQQ+fUK5X8FdWtk7K6Orsickts6koJeqfI5brK6BL5dTrnEAyjQMf7ClUWvOak35RP
6wHmtcs2gMhuCKO280+h938jBTSHSV+fJYgxv0S5WfsCaL+kAV1Rmi6LsYGCMSjM8LNXB/130UpR
kU2LwzWLNdFGWIqTLfGKTtPFPsnMZhiHagrctFA5PIzasCB9PgT0ZfpaVIyi47n6SbWhG1wLF1qt
nQaBlkgbdLWX6Box7GuzXwNFx0hQqCeQhxSlNfpkFexvwUu0nGuEB3RxNY5ZMnhsrYQuJMyCPUFT
Xuz3CIBKD1evlrojslSs1FHXgl48d4r6Bet+Gbjc8xUHre18wZQeJjHNkKmUSMzcVavZDbe3tS40
br/jT7pD8s9PSBk9qlLA1YrkEGhxAZSldRfQCXDdRAB1qmpxleqJtSNu+cARchXbjCXaynhLcYtl
jrgC1LHnJQ3KnYRw7nbfAXir0eORkYm5YEru02a2zslzxyt8eV30rRyZejjt7ZZ5gFG23nqq9ljB
hSVBTrxLYIJO6BUNEbfRuC0TPzSnkKYZozbRpC3/upNG+DsdS/C10oLaub2Rm54BijlSTAlHRAPY
btAYK1lqBVt9tuKB/vod1DOxJBp0ht5HRPn2M3KX9y1PtNHN23wtye8CvMFKa5PlAK6XgudQTKpy
UJAwMO0Fg0/4ZHDwqiIaAiQYEj4tv/x+8tavMTICKyQbXDN37ukgJ/EQD5JS3HgcNy/os5oEL0Rl
P0nMc1JJhtqC27DfcSQnjgRRuY7Nk/jTW/qmtCOB58dE11+A5gmQ6EysHRJTqV9cqOLAmj18U1Dh
ctNEram/DERxEZOtqQuPDQjRa1NNuUnYtu4K08dj5I9+ab0sUQHcLgCVvDjUdmHUm+/Ai9v6peRo
UvwaTOAmitey2TD0/Quvzbc3FKUpXIZ3fm/8tbzxgTTc3KWFqdI/Ene0zJM7WxrzQHbT9p+0gN+X
2kW6SVmhX2sWIcbxpO/rFGdLmH5kqbi6qjwseN8ytKRTCF4I3IIThCmxvrNnznkppcTxPEmOAtuQ
eHKqieemoHOphSqoAdOoE8KWDKYCM4+jxgLYdY1L5JMmw066vT9S5+W33zDMG2NkWng6Tiuen8BS
11Ch7EZySKApX3HpGKw3vUDRyjz7XBchYqi1LzmkJAjLBrURbhP8yEo4NMGrDGnIWdndTulPdxjj
bBaEzeOquiIHsDKwTgJS8cg8nzAYvqxzzY82RAbOQ6vULVaqXSjPCriJcvU2qA8FPyqROqZ5H5ws
XfUQm2vEjQxz5LO+Jr3VyHwzlTZAQx1KgWr7OnrG3KZ3dXFw2aGMkYorDCI0nJgm6GGAZoSUAd5+
NVdfdrQyuA1A2g2npYb80ddTjfl4lSwO7mcXe+4qw7RxXhXBCdy5a3ovEe8RI+jUmtHrbNTsulLb
Y7YNuaFnL7EZMLw+fZE94AT63NGnFm48fM61Ol7OZrCtm52G5zfV25HkzwhZ5A2FMzJnemRpxIKv
XKqvUkTjOY80PVuvn8BEo9ufs/aOEkIOfGPswWFVuX+zWwNZZt+2JUyLs21JPC0Jx2ujQ5iGUZIN
ZNSoLxqlgXA99SAWkmB4tJ6bMgO2RaguodYPu0bEeMxe1mW9YZsoL1AbBDdiiAnpAQJgA4JxbnWl
u8rboetmbMG7v3lRidKnIYgQEZvHtbyIZ4fPs9XGbDVnTuF+GMl3JU3mEbzKYccN1LWOeLSK0gbm
nAi5xnN58Jx7fJRW/Q7JU7FpCc+HPHrAvSmGXrN1tDGGtP6HENb8Wt9MLohHKrPG1pHsO5B09QnR
5jyU91Ps+ZB/yT5txr01RV9sururQdVT91z6S7r9ze8HRWE36WNBfoupbECAWmxvagUVnIeXrOvr
muY6vOR95tdbeZNxXLdBR8c4iTRI8MfpdbQPl0zqt09UxuyNmOPXnwPlKyhqPa0p6iAWJb4p36sj
jenyy7meFaH3HMKAJEM6NSH7Ql34eEsR+jpdhAEKHAzC8TKaB6WXFbKLVpFdhnJgm+IFP2ErH7AT
VaD97kYCBcZRuohHl2c8NfsxIgYimNUFQBHewvvQFBGrHn6evLHqWlY06V6CwV/9qESNFRnp7Ygi
yaM7+y+2/0umxl+YZ4qcZQJ6MlWV5Mu6qzBx8WL+iAifRH4XQiP8URGaWmjEW22rjY24vawFHTQE
vgDRNGupzKaHOyDVBhO5XPj9fnFJlKApP6gdDGrjGlLTcKLcgJFcJaXDoA3KK6mbWy8uqtwLtIUR
Xmc883R8rhDxAqBv61yBI/fjJVsNKlCvTjRcixr3s/pgzc+J3YHT+QM7igdHFUXhQjxPphvwXN0k
mIt2wWdnnc26qv6iFV1mVLw0bURDwc3tZ//0qX6vy9vxdedP3C5/SNergabnQ8DTdO+r/IfoxxQs
RzNfEKaQq2ZBzUuFoYshf3b9s2Yhqcl6zAXBTVSM2uiVvyKh2MD0g6+NkhnREUrYdb6FEUuNsRuz
OHfM5wHvFA4isbrC6qHdVnCUeR/0D7R0u8e1oLr1n0B2HtIg0HLtRp3zutlsQCteaZWRTK6/0vV8
QqkpRc2rhXzoen16tNrKRA7f5bFpXtPUZl+CB+F9n2o0SKfSuoG5UWSvFARv6khiADWetlGr1/zl
jLU52UvJg8FJkwfv0XcaIxlWVnIRCmZXkwzB+oQOEOaCVDFMXivw6tgYJ3VxGAwV+OzVG1EolmtL
Weh0SK8Xf5v5NyLft7osBPlVjywHhmF7ju3OMY9Pmy2DUaSu4HBK5Bk6hrO8P95sPRcKSwPshpd+
nTCu1vQtwr7QjkF2jSWWtCtVVnYXsuDx/toil0qkHafXrvdelbcPY9x7pzq9PPqDujkRUWlYuxsH
FM7l6/Q+Y+iOWtG6wb8N5nhU3Cthh0Vznpso1OShDcolN11KM9xs6Vqerhxudlta57ZotJ1IVFvi
TeanjxDY9tzXZKUhLIo/YxrQAZRtHnCqHo/eKgcdvK1uxH7kxoamSXfq2ZdkhTX4oVRvJVfZN9IF
OJOAYT9j3IvTyHNab9zwUvGzIHYO9Jjzk0tzL+NWUEVARkdmjuuPogey3RLb5HAb5vzhl+LWvoto
kpF66cQ9UVE424QM92aETyZPjGfWbNYdcGOaC1ZJNj08kOn94ZQhLeknYJDITjcRaUUTnAb+ebY/
TLSCPGF8BFMv1anHnbP+oMx3FGFml6BIVORyTOLO4CdjsAUhKqe9ZTd52iWdmWRY+f0wS+Wv7a09
+TDPeYjk4ETG1oCZTZrZPm5r0sEtKbO4XAZz1gT8wuatFpFdwskPgVSAYkLSIb7pD3015u65OAJA
cw50+eKJ6teeNRANz5GKdLfeUe86qyThA6w+nyD0s+el3n5hk16briG9VN4NFRPGCv6fdwNdvCq0
Kwne7NztlE/NcXPdG8pbgZiqGjXGsbWUcGlZThhfE4t61tHgXrllUsT3ADMq1qS+jEo/D9MzeaLA
7r32Q6Z/WoJNLbZP9eWBIizOXYHordg5h1ATuwZuiNVJE27JrWC5rHKPvGcTFYnS1Kh+LuqGyzm3
Mc7nIpeMJrNayVcVzp7oMHrfYi+gp9m6/AEakbaoKpi5HSW9XtcKRtgLqVoKy0bYhkzqvmve6Ed7
vQJF+hLZk0MRvseEjGEtUqJC+dJXjRSO4Q9+4umMOmmwhTXI0JIGW5Mc5oclcfzoG10bbuiJI9ji
QSvOd/6DZJTlO4v2tKuspNBNG0Aw4J6WuUfLzy6NKmDV2qqvoLfx/3hm/3ZtU3wYYyeh4H4H9ego
h9RPfUqwc57iFHyQAB1lKB/W0Tqe9miixjOl/86xdQT6mBG8jZEs9+3VSiZBlOO7xWDmBFYMx16X
Kssml0+yQHR8urTR7HslHEHVXBh/wInv/9ZINAPhiXTS8aXEhWM798FZ+A1PGS8FujhfB+cr+zDs
LROe3fJwStrsYwB26l6dhphf0MOdTAUfC+6rNtMx2rBL8rv0l/vkWduf7BVpq+CpwCXzIfHGlOeC
ljBAUZluyPdhhfRPajv6Xj4SaSI93O+VjWezaRQxofAXWjkbENHyskGGI18EzgBAKJlDp3h1mnoa
Cddh/zc35pEK1+B5FCpgWjvGrAY4A/HyKV2qTuVWMxBlp/3dcqR+g0vt3/4f+uXt9PlfioHX3+ji
khpPYB269dO0b7UaGFfPqi+5jvYWHof9sDrVMnNwyVYNSopKZ7wiO2bDt1pwwXxIZYcK5i+QPSA6
E8pXBDi/vm5TbxLjaFYDFZfnmPuo5437kgnYEKZCoq4l6LkOSZzCuD9O08KJj7ses1ru/Bm2Nsrd
k3Km0a9fMHyS3PKbZsboBQX+iNYPOBRm8WxsoXSZoD7VPBc//pvXnzYuAqHlasi0stS+UHu5//b3
7ca+Vu8BcJcsn8O23Ozxa7djS4HEGOZunXXQfJJCaXiS4YM8A7gGa5hrIppwVuuiUPlcrf2324Ps
D9pFDaMvK4VdPxwdxQcU9o1JvdGc8Rs5/1oPOLRee1iahk6guJMk/BHaMcp4XtMPK8E+kvm0ZTB9
cFk/guuLRbMGSd7KJ3yv2zHHGQ8wA5t+QFQ7zYkR9qTviNG+I6jFxbCFbLKTbysAbyUbRNfJ6TGJ
kQuj0a5UZ64zv2E4+CjKegmU29O4tfzZujfS4Pop5Jcxl4PMVaH8D7KQ+3TLvpq53mQ8M0OsVY7y
3WPVe6X5hR5tALLHnmwoN+DzA+oAbuOXT2p9KolDblv1+gq9+YWJfaNt2XqoRAIRYYw8OcL6cFmQ
ccETueSNTH4YopyI959ZCu1Rflj0kAF6o1V4BL4T1UQ+Yk2oUic0VOiAg3mC9mUEs5lAdDjxp753
rBnepELewLLhtogrSNoqQ4bxb7WvXoSjX6PctC3BwFmBa4pDG8JOGr1hnVdpRd0mKzTAIzRnAOJZ
o9Hc8Ju2ScU9siAY4MRHIleUXv9LeD8aTH+bN1sJM+erHjBlx+STfVhYAUXFaK4rtEBDszf41s0W
GR9m418R4q++KjYWgLOR1T6D+0+i4Xhu62hTJh01Cb1KGHnf6ZUljM/f2qsZgjnq0BkrLnTnt7iR
CGS18bzQgyQWam0VWp3bz/Gi1c9ZbHj7MwABjL9g6bIayb71sqY6srn8cLeHBlHdB2h4XqDizbE/
nrur12rgjwaTVerGYmW8ZReEjlWUaUaPStpXXHC6vlWvbxPb00uFC3RtUfuHwUKho5LZ0AxzVwjJ
kTj7sZFiob+8x1u+xzto9ysB8SgCEwyjHy/mBep71yliM7ctat6uW+6GUnrUihqzMHlaYRaSX3qZ
ApTBSQ3OI4ONjKRGMZy0SBd9Q8fukd/oiS0SE3MuIlvObQQZJ+PZiUVmJ39R0cX/e76M/kPX7Qbv
xwhyLuml3jbg1f3dzTy63HopkIVVAdFA+9Z6A11T36l6mk90ubclf1ZtMwwULFKaoIMY3lGf5bQ5
AzFoVH/CCXdqQSzYuR2t9qpZzjHjD4jevkosJLLaq4YUiyGb7RBmYuiMgizaz7CkmVO5ZhxFtQuN
uCHcVcXdgXvFatKf3jlFSSruM43s3OExNubbp6sfl8L8jSyERr3X0SifLpwkrYafPpYbQ5cM3QmS
0kNyN7Kjjsp746ipfaDLlZuQXFPgFVy2jqg1ps7IDuYwFh8qmniG2RVPFwp+gkWhvcwX6y4JvrIG
73bXkqvWko76tWgQY7ZXEdE4J9hTSPXaZGYWQv0GDeNDfzGusmzkIXim0nnKbGKAjq4f27z/VVPL
e7OQsp43qe45dPH7F/cIbrfVACQ3K5wGzsPGDgj5qYVP1c3cdxnSI6LhOnLn65UKMhBrqDJe4bfg
LMNGziWd7exeSbyGCBkeUOyv/H/2LzSkZF1P2L0oIcOlLzqGFX5RQiheZvT1c41Cb+JOb4Nnf1E/
zLCRPMANw2ixVnpE34ZxLVWIOTS2B3nq8fiFCmAn1ka5lhtatqBQ8ocxHHpNjCd6He/aa1KUhtBc
OnYCGrbe4herz9LOJlAmLJQ5LkAew+hblNpxl2bP3HGx5DHar359IxZLMzqCc8FpvEXBkoO0Ff6l
Tj+94fK3b7pbnmcraIe9RV+8FDx8CpAW9+MDFSVzPS2XmyCtomShZcXmXxFpkDK38YMadyaOJVrj
ca+7OycOuRrNXpcSrpmcXodQfv7ZWKAOZU1BAo/j4wbd3D2WrTCAYH+DpRWhu9qYduWfch/aJHVn
1X+iSo45xmPszaoL/xj7gAiaBUKI7fbVZY4RAMrUxWLQVclAC64jtqwYrqflNLA1nbqf5IGkft/Q
CVP1iCNagnv11lPG/gESni+WFMpTP/ZyfF1+pUPmXIof8XUpkxoihimgJ9qSWsY8daAGUabgMNJb
RaemY73miial3w6UqnxBrs8tfTg786/8XKdATHdpeWx19Xehr1b08PeOscIvrIJOKK1dbwSR/bPs
WO7hVBVqW0ilI6EFT/Wki9z8h32Ej4a2NMKc5YZMTtapDoFGwT8Q8nFVGImhH1RMm5GKzVfJODHl
WSoz/rYHZ402XYAPfQVTSShCfC/2D5OaaPKJ+PYAL9i9teWpIg6OMJYjVByw4p13vH1//BXJQDc0
cWAKZY5qq+gu88SHQ01IHyVB3Jc+v7U1FU3an1pVo9Nz5U9VGznaz+SM6vwIvNPr3JY92qpI/SoD
A+DqNLPpe3tL/9i2TQYLw9ccEDtrKuzrZZ0lnVRPWDHpQOtFEyi+mZULOPCKyB/UiXEN+c1rsmmV
voyEk0KJyP4nzh/BcRd1VCJfkpAgIR39TAHvhZ7+zFB3O6pFEsqVYfTST7Gfvjql7GOIprShOg3X
Rab9g1ijVfVWiZF1VLGYatSHcq8Ix+7BXMmPkuxwl/4IxIhpsR9CVm0U3C0+0QeadQBt+sfE6dxm
M++uLE8fQzIRcb4jMWA2D1WMnovQSYIWsuqm0/5C0u7AbEXbwrnyxO7pi3vI6YVuuQT12ozSzXj9
Ro20tESsJaiw+T/fJP2l92D1LuTFibdpGOTBNMvA7rc1ekKpbWOHCNXnf3QZNuwipvTJqkuJIzyF
wH399M9STS8XV69QeFcTRExcr/bfD1KFXaPy9i0PfSsHHr/qjs9MOjA5B6pIPRl002z4d8TIA5Sb
098uUNaN/VqEV8PSE44R8LW7iUB0R1BqiPvwB+w36aFH/dZlfHUf6jaMJ0UNCPJQ/fvDNn+EKCqC
yP6rRycGFk3JEn0DMVu+MDO6NAat5Sy/HSaI3nFoXyMtY66lJUQTCzbk1PEH3V8Xkn115Soq1/3f
+VXupmbzyNIXISRs8X9u163pxy4FuHYfJRFhNUNHtFxe5Gzj8Mbd0U3kY40TbYwvgLdplMaARqaV
CJ/fg+1gI4CGd/Rl+1GHOMerdxFX+u7XjWEfjJF87gvpH7pnxeZQbYDv/snr68OvDsSrr5OqvN0e
K7uaI93nedT38x+zEq1rwnczOQQ9A3Xz/ADCXz1m8AgU++egtTI8rZyhdBOa1YRhoygtGF7TtNOA
+ZI+TkYrWPMtBhlrVGEa2IOHmSV9RJSeGDNSq6BgMx3qoP3qQMo27cEUbE2Ojp5Ay7Diy8aB8oeR
FxUwwlDukQ8oFZ8hUiUvzjKfuIkSSByDKMdkwkr35eQfdUNt06SjGS4x6EBmmRTu4/rF2EN8KpTF
RUJXQCR1pFXeHu3bcNjyPJ88b3BvIwbKrM5MOGi1Bx3X2qASPSsgBAuuPVJKTOV1vITx4whKYb5n
qfRoPNxI2+L9w1Wd+M4+dzVi5nPLkEQ87kzyZp4RxMTzSWS9umqiE9dPr5Jt1WwQsDA+shH89A1q
l5Rl6bGnG9kKv9egbrateUnfQUXvR2MktFsMEWYH/HMcONeopsxPUJB1X0ZpBmMiX6m5Mv2DZNP4
oB3jzmroSk/GkwGD4ls5yYR+kTY4FKkNeSWfi7PYtg/lRnARih+zCyrCWjX+agB6FwrpQbCKnadG
+2Ur9N6kuN5M+arfXATO3+ObN6y33nJdjPaFAmfbaunDh0+CWWEaVkWXP2zRzkiENLqWIa8t8bsC
XNYnuz9a4TPQE86sxTzxVlKNe4j78B9Xub+AUPzJ3PNm1hReaFdL+h0x55u32drmkCp+zQu4d0gd
KYiVF4BQV/eGQXjNV4toCzCt4yZ06YNWnLh55vFMKEnR3+YDzBVpVvKzpjVKDts1m3qsj3hXKvt/
7keQxy+8frTIN2kdZJcf9cH8Ddx62yz6EV9PnSFiOwxVuLwZ4PrxkD0zfmW94tUip4UpbVwb4SsO
TOcP7SCGaZNyGHLBNUttf7qCcEsrbsPG1l6xyoTZ3/AyHjpzRB3oLvaWV1IicmnNS+bngpMGX3iU
B1jW9eTZvFBTW+hq8CV/UBlaoTd+xqTmiGRzM6ya9H3wqcBAdw8roqVehNCGHVjnVsfFw8kXhFiw
IZ01b+8GMeKWxxCWDnvlhG/1ac3Wx+UwtrqogYGgS8eS2Ft3NH2IyczNDTzHZqIyHCTcjcH3jChL
b4tp7MzCps9xdC1/03yzZrKOtiYc54vY7si8Azb1bM3ZHl9bPGvsuXor87mXzcRB37UxcJuUVKzt
h75fr0HSVXOdvajPIIRyf5VqAapjT9fyBS/PrInJYjFn7cIiNXVqWawVHFaEWQOdGLe1KC9CB8mM
b0frwJRB2TG8GAA21Yv+tH1wiwpEtRBXfXgeON0lCrzfFwO+UqPWMDvVq5hZBVF9qbB33/khwQnR
XyFF6U4iUGQKE061HcpKFt9IqIQoLLrQVhDe9olCkcbSbwc5LhUMb3vOIrN2Go+3StWvKLbdA4kN
Pv4Yov7/3DcikxNo41T+PiHcImqACBnJ/siVmfmqwB11EgP20cxLO8ErImF99PVFgYT7h+f/gSji
xS9raAmO4h4i/ISzDxGv2iimnS8IMVWarZE8PVLdcRaOjJyT0gpUMgm4Euap1OD26svozmopmYQn
2A21pNjT/0CIQRqC0ysOj8q4UXAoecyedZePoocDYCT1uWbChvGobTiDycqwOawpsaLxYPO+XgpP
D5EnImm+/KNPUOU/Qy9AFHY2T0P12BCW4xAVFoaGMahs4Ar08tJ+dX0PRwQxGf7ouPcUQ541/BPT
X2t+l+Bt9doCC3z+KIUIVt1ZqgkH/QuSVc4gsGkgQJZ6ONtvASMXrSaxkJrKrZwSzaTky+ySXX/h
vELjl6amAsUTSxr5bvluS7M0yYypQqy6dQHWs6uoxDvr8bq0M9DNRHwsDvpwJLxbng+1Zkn/rW+J
2LA2OhVVo332DE8pY6+w+DgOfAlhg3zgMifcvh06UuqoD7K7D7hNtj1AUvoWiNVzge4gWkJBqt8q
mEWBa/OU8SlJVx1PuhZQczdmYoT5nYy0veB681Mht1fNN2ej0Rc6Js4ngzD7Dlzwz6t5dOu2yLJy
NvlY3X3BTsH2rxwvS+fjw38Y6ARtvd9rRgUYYKiOF6m0NzTj8z9EhM6he6gvZourOdKkzmiVEP/y
WzLgQwB4rKfL2ZqmHmQx56nxC4acqFHzNWKqWMFljAjXKDT2B1O7GB1+Tn87z7AVYSFHoYi0efBs
AT9DC8K40Xykkgj5p1j5ERhPptGpnt7Vhcrefy3Bssvoit0vWLqLAbFoxOVposZ32JyoaWT1NzLB
8hK0+sgwdDcs/gNUzJTz+fNxriJx43lukN82GHLIQD/gVtbOrsnZQF8iy62eOGoDvCupPnCtTvZM
eLoDGCNuDu3nabo+iC4o3mw2lRWYVUNPBu7rmIvSyx96XBduUKFdrsDjF049g22lI9Ak0VAQd+NI
IapeRZLwZfK68Uvp7N3rTL4fquHFt1hWl39eG59mt4HA6Qww2jsThkzGZYtjYyLQB7cZlZYrcpdE
ulyc8XdKo22rS5mlYT+LEww/mnE0kjq/+P8EOLEnCK7Ot2dUt0KeltesiyUkMl6uWEGYMGOQCr4D
+OzlbIMLrWjwF4NxEwqe+W+pXEVgaVojekrWO8Lr4Hz0pn+TXd2vh0rZ4/1uJIInQosmoXMjxyvZ
PQ6u7+a1SCiQnOsY/QRHZcdzdK9UzzzCG17iyQB8W5gx9rEM6XuHgooTDgyKqCbogfAKS0ft/eMF
6HUfss+06Owi4bN97D0ZhsZ0Gu7B2jACkcq7Ae6Nw86oWK43TtZjs4anFgC4QBWzsbwi9YXqaqr8
7j4J1yiaEJ4d96aeV+DJVL0gWpYWsZPpEH1OWjdAUwFCBag0hpmHUpW5UkbDGBzfeTW3uZmr+X+z
XV6ZhtCx7BYEnMaY3OsDLdbnkVuJ/Vbzd/yJR8ZxZoivOOlhlDcUH9a3i2YBxvzL8ZdMWlICI0KZ
3AKjaYi+PXv13ZIwAMYuctZm9jj/frWBTb5/luozL13a83TCF4WhqCQGoucvjSD94Ixt+M1Vj0bJ
DA1N3qp1PZkaWHrLLyrCprqqqqtoXJ9sfsUfFNN/cNSmrX1yhAZgH07HxHMiFXkYmGfZvC+9TU41
qVCuT2DJ9RenNQ6Z7zkY5K427Ydb6HTMyNcI+YuNWaEbJnz6RGC+Djf0MXNz+AEsVr29r6rKLhNr
IFxQ2zbmfzyC9ExplOOHgbJf3gYXWKpy0F00FCYcVStMAKp8PHqbkWqr2pxSelpF1kfENBPeFd9M
AC5bdINdpDsJkDvHFa5pzlhsTPoSQ9rj5R+cxkfB9XxUx8Iod9h9KMmDj9X1A/R12UZ75BgtN/0S
mUeZY9Ja9Hs12402sO2ka9YbSWJk1mi+BKS7QXjJrw20koZTb2T/wkYVkhBdedl0EMKIQDkldSVW
c2oT8nwA+WG7pa9xLAEh1s5GjYOKi34t1/y9zW4sXX6Y1tcEHRpt6yTiarl3tUt53/Rf+E9jL7E9
It/2teq529sEjiAdEJiCCvGIp8bjThuxFDC+TNmzhO84jy818VEDLBaxr8BBf+eXXq18Wl/bmjEk
9VdkY2susxiqb9J205zmYWk4/faFtH6yNyqSYnfy2vJMJ3VlJmFrcJuVU3fg5Rfi9Rqzz3PJpIt6
CxHJ4tSwNaYGtUEZbtUPUVx4gVxMqmyltLVF/M9JWawm2WbsWKlBQDP18XeV3VhgaC5/9vHzIGem
Fj8N4GBl23nabeKwGc7O7lGGfACdwBLCb3sTtPrPsCU19ANA7mG2HWMjp2KJwQ1gky3W1GuoAnuU
bV87/dFHphiefEGcAmTtvTwv+I4SonIyrwHjSAz5lZNQw/8D/PEwq1aNlOQKpgk4s9wmycTepWTD
YvolKvNz0FUXSTcNl0HILh+J8HomwmfWgIcaSbfLH/RhHZfI5/M6kp+jhZWVrU/AYUCHitF2Omtv
cr9NCIRqf4nDVjejqziHERGIC0tkOBQzCMGzTLeh1z0q90WWHj6BAkOu1f1z37IEn24FbXMzyQhu
1v+Ll93X7G9uKkSZhHKmkeQ03itkoMu6c20z2RpuWJPK35E4Ec/UeRDpTF8sTm8DoQe2ZPl2sjps
oLvT00i77MJRfnC7ewrmEHMMMXEqqRcohtmfk+CLaYNeP+JpLGLW0pVxjI107g1QrBVxYLPpJulj
2RivyJx7+6FbjcNT9u2ClkpkhHDFMsqzKC2XCzQFvAYsIefKwr3t8p6xeDtss7loBylgfl6+9lKe
j7gXuJx3BMsEcTL9ci+wdfGcFA0JXSo0+VfaRjXyZ+yTtWEyoka73whx72oV6Lso3Y9HQpXnn9bX
tg8kslPVZI82wWPROeAhXyMLdQwy2QHI+GHag/5JZFl/Udv3vyv8zD/eVYTIMsQhAG75pXgji7hG
KMeUgCz8CuNrXqm5h4MtZcPigeg8CmhXaLkxO+ThHO2QLeCemUSZaS30K63sWCElN4OQRVMmk2fP
OLlEAo+BWPVEeNosGlXygbtLXlfYAYegjzJ9nAk9gMFxl0WT8YfcmYQ5Ui6lK3H5rvLi4E/u9M1o
m4SNgCeOU2jwrP3jvu5yIyubc4m6UsqejId1eOs3vrbd1oSSy9zuuvSQ+8VXVTW+rmI1oNciRwy3
Ni/thDolyE1vF4ZvdssPs4ATMbcEf3WcVPYscyNO6ZPudjLmjWCT8JWLOLo4YpH+ykL5fwNx0FKu
IH7KfNqxvM0SfZI/60hrTr7qNcVyoKAawADDeBw5bcgVd75I+agp8gcNzRZp60178HOw0pJcNTH7
EQ0DE3Ju00cq9jIkKinMRJCS2YfuhCEtpbsgnamf819HrKkbp70Xk/8bpt8Wu9SBMZipFbHkL1ov
rLIQ6t4b0R7yAObnEtsRevDOdoNzzOR6FJQPwz0IKkOByTcHEvy03lOGpDhXUUyPHFWOcwcYRD3o
hMZJnYrHD21UOMjjXQzYbg94XTFoTS0Yo2IUhs/xsNpUwSmU3RMelNvAFK/4vsZkjyhskBjJgy1W
m/MFVmjSC9ewPEo1FMUX4vu6TWQ0AN/cC3uiCvYaoL1Qh7o72ehiwd5FHhxRvtn6Vk9/Y7PFno9z
SEwPpBmfMIudYD4nNxrH7oTsGM2Xcnv/VEfEB9QxKArRKp8E1m7yO6BY6hkuLnF5UQr7hAq+f+Y5
YfK7etJYbLl7zM+KvCTB10n2KEA8oA3uucBaLiARuHiEfbaUGl3GNz+LmevKKclrNUTHpjPcWzld
hmCFdFE+xyCPCxEBf651myOqbm70/C1XJlMbJPLQSY926cTUsUGQdvg6JeHuEULWOSmD5hhV19bf
F2ILwGR8cEaRS9BrWOU32+ovX8obqvfHze+fG7nkv43DxwrXhr1FrmlLRlZkaFO97I7bUlV2l2Rf
g6JGyrXOK7Seal2IxnIS/UFeA1jowS92EhOpQ16gSHZ+CzLrZLT2cJVszoxSobbydUgzb5EnKTRj
kUDhPrJW4sVcbl2KVuC4UueqIm46jUQDr4C7qtT0RKacQ6uH4AD4UdbdHYF+R2uh6fV+ArqOHhOA
XTXqLBEFiXyQykjz8sOFQ82neW2E7rmkIuj5QCv0dFIQJVlxrGqote+DrHQSbeXPuC2eMuZWezn3
MiOoyjEhfVWmSVN5iT7LAOOeoe+iZpaRCFWejsA4i5WJaEkeXk2DDwRlohmDDcfuJF7Lgsso0Rq8
nmk5umNPPKwgnBS1F9Lqqe9cPLu1ETOjI6KT75IeTE2M5aK/G4tkLWXJcl+2k0vitLNNmJg2UGad
ulmOb7xI83H/8XYiw4u0OQE1mAQwWDrBf3SAq4co9BaB4fFHXK+Mqxo195nTluq+VsK5WB9qhfe0
D+XipVSNO1Po1QZ4sCYvCG7BSNJW1YIWKt7R+fFoFaFf8A3nT2ShMuJ9LVhnBcfW+7v1KpaMS2l7
Pva2HrLFKSt+0HORIxC4tXdgUefbAlFo99V/lK47UiCouuR74/1kIMQeGDDtNW/47+La4u/UVl44
nn8xctv2IJQvnL9+8jo+NahS+MVnjjugD13PBKTltGUxY+0KqRtMZZnG9KrFxrMvaS3jkThPgBcl
VFk2cKMg3/HcfHcLlaxH+iTg18V+qqbrkLw6+mRnig+K8kybAQRFqeUBvlK3l4IFbehgrkjl75ZQ
8+wD0rXJnDiynl9C0blQnXpxUQqe8Snp3+50Sa2aQ74jLSPxJPynStSeo+TiH9oMXvRyWpfMdQVY
hyvceh5rmR21o5a7OPDREpJ9aX3M+Dx9oAM25EtHAMxaLwQY9o5LoXSqJm+Ksa27ciSnSLup3Ocm
eb+Wr1RJEs7kB7AG3oB4UJAUiy+lKjBfGwlGqoEAC6wLdeg3mGET7iYrQ0MNPmvAUlThfLAr8+Ht
kKLyY4zNG1hZzePBwbkJXPDomufn4pcncIuRBhJRLE4mSMXnKYP4jMFqjcOvh+QCVlgAt9EoSk6r
NeqzAvpYtAAQ8O3NfudR7896CJPKXS5O9RrTF/su7DXMxj2J2gXggxo0MYs47oV5jEATkh9nvLnG
RtbsuzJSxBE9OR9pUEOlZKK9HHw8gmC1xCKGWHe5H8xY+pFh8DSIp6cqUkur2iWF7jYFHK3FIcad
YN6rABvkEnuM1Tj/Tb3WHjLruFP80c5XhRvvSW7bQqc1NGpVMg2IYHuCrlhZpaObImpHDp2Xgsb7
r8WSB/lggtYrXS0C4X/r7ZsP67aJSTv8V/P/jpOkxKMdXJogzJPAeBDeynZ1w1loLD/uZT16E4Jg
BEvaINM60OGRjf75VzE7gqp8JzibmYYE/uxlJfCY0moaeBHET2W7a/Opo6A85uLp7F7LbNSaqvrc
EdmYw9hDRBanQ7lVdZ6fGtlJi/4qAfVryrmbKhdwJPpA22rDB9ikygA0xDzmCxzVpxP96UlonSMg
i87Mk1L4pKPwvWgswKIfKeBu7KGVPdkLaTu93wH+UaORG2bF1rFKHNChtDrdTfn8RF6M6lNgcL45
xSSOjwD6m/B5B+EGsB9eXLpj76sbbXBJbbJfIyd97avmCcPAFdLELLXnO8KzXVjms2CDk8WzX+vc
rV19l3bne/ZxB0TqtcMxgcI71HVJ7RaBNWUB0USlPpHia5wnbFwhkxtib9yWO/ZF/x4P5RQO6yPt
JUNMGMss8FNGA82onATuoPjO08SVQT9XTgDzGCkdFs5WbDcaeSTkgRMWK6KIpWs70igdnyuK9UYs
9H3suJ6ZqqMeQd6wzSkXFRAxZGG9MZs3zp+iaRiFMUwzLSjWlQBwpxtDbKARYVrjkzqW/o0P+7cD
Wf3BbJMTo+HwRrGOkJPY1H7v9kPTp5YenFKkH0sVjDxhrvMe1YTHFDvyhEPRu77XgqcW2kMwXXWg
omytv3rKT86NIjJ6aqPjDjgU5D6v9bggBKrS9IcGZt0CQqmtd+KlyrkqGpIpF6k5b+fPf4iPeqCH
Jy1J/+1ZnBojuRbMwXsaMNhQweQXo0RfBcZ9XRk43ozX7XfrQqfcM5InVrAsyqb1K5Z3DQz64eAV
XSa/mMiJ1CyCjYtN7lQsIAJPbVnUtrFWyF78wIf6YUny1ZujuIyg2j0I8lDsRfFw3M38VPNIQKGd
qSV+W2SMYvLlKgMkmU507p31ZbtssbUy7VFASZVRiqbzl4FEKqDtQF3o1HLlgdG0b4sYLg0dkPBK
mHkJlIze5cIy7SIj8BZRWcD0AlwEq5AjMN7/2i7A7k3I4HGQPND0VlSgucQXkLBtvsUSd1AgIGjE
zr5IphyDjc4FUZpL2hkX3SOks4rGilmWh5ozYMotg7w4juVDIshNI02Eu/WwbdH6DISxSJxQdnPn
3oG76EFkgTynDtK2Pb/tO7vV3ZB31P38JFbrBOXQKkLkRn4VKkcjbct5wbr6n+AtPeRnwxWjgc3i
SidqHcywsvSCLJ8Xfir3JtyW3SKxLIqkCpMA/9ngp59aqWGRvfhrIVzqylfqSsi8qQrfeIQdpz8R
uOH+40kTasPv+y+uADOzJSqTDsx/SHOnVKoZjvjPTKxo4CxNZsUv0F7iOPenG3tpN30ILMPD5Hoc
1q4s60Yf3xJqINFsslhTSZQrMf1PPVUx4Hj7jmOElI1bQg9wy2Dxfiidv22YwfUwkMLtxPa+Bky+
gVZdDWFl3QPpCmjYipXC7/8HHwEKNnavKqPagUWj2bYG75VlKDgc270cz6F9dsG60r9wARXHjmzC
wdi1tFrQi4P3bZBoJFlSZgsD03D5Ou/h7+rDFSknDYdIX2FHlmRDTv6YETQ/SU8FLzv71EqdPRdt
B0k0kANirIajyKBnypT1CbnkGcAhT2bjDrYkRCY8w8g8NxlxMj8laNkKeusfDeaw17VQ0mXCpUDY
i70mIwe0wgNc6oduFcvhfHtgeug+Amnu/iVTwnLpojUqf3WUtV4b4sDIU/NJD5sEqfmA+iAueGYb
714AYwBeYKumC6xciqu3lS6/yq2EKb35daPFjTq+zQ/SDwIOvK59k4vanhhupkjB+zxaFpQrBgrV
Xy8Xtkk6n3yhC0BdF64bGBGPf9TaGMUKhqVhf0hXdHbLRcKwgE9A1jfEuv7qchLClKPXdaPCQoQs
Jz9g+o1FTzmZOYlIxjrEd84PhVhdivwjb346KjaAm6lk1DzaHHqwHFzpXn/m0e7zTEpQGX9dgZ35
E+vYHT0Dl+3itwMwqT4GfTMKSQUpYtpAahbcldj+HfRLlwcdXVNxQR/GKZOoQ5B6jjASMrDx7Hcw
h6xmrRjGlrB+UHjLpcnu0kCXJQBTB/r5Jtky5eWI9xKJqfP+mF+6pqGarBwTGkk0YTBnAHItfkID
0vD8v+8v1WBBDwGD+9pzPWhjCM+pAPv+3zEc9UlgrN8H0VSP/uDWlBsnLCvTGvq9YXwVBi0cB8+v
UETnRtFAJ4XCCsevT2AhldBHDlNN5Xko6FRzuSlHQjWE62LUkc2rC/yKXRija5J6+riTob86B8bM
7eXXX65AjkzZTIMEPf5jihDYQFHwJI7CJomq/bqrfjGpvdVZaaFU6OxicyCbGVmD8zq6uULPKxOA
9a1A549+0IrWixim4RwdmpkTpQpJxFnYVxJnQdqMx6KoXu5TfOvrcMQMEqefKp3VLIZrbZCqwL/Q
In5YbiO+RAHKFr1Fzce1PIT3/sw6fxKCZJAd7FaobcpywjFJWaG2IdIrSPG13FNW1JWbTnJNdKya
US++rQrb95eJNiYv6+AZlU3qFWYhp3ZzP5iO1Z5+RA3deW5ko/OXuKcxql4JpFUEUsm5bA9BMWNb
893g0L3EGGsedF52WuAl1HEt1o3UMbNH5rOavJU2kCqa5HdSDCp1wn5agUU5Ih0/6TTmSLwOXJ2R
BD9lWCWB6vNrxQ7De/SME0va7LBwHuseGqL+Oqg3gwv5Z2jj2MUrolW5xMQ01sIKRPKg2yqazMD7
sFalPkrqh31fLUHWAx/048ZtHKT8n8vEpHTLyDuF/akpjeIAkJjMi+FIKpzqoBXuTOxli4Cs35ZY
jJ4ogyg3+o/zoTMuLp/GtrHPjVRfBtsZIWLu1g/6uyxeKV5s8Hkcp35lESuzVmFWrp/WpGx3KyTf
x2KO7k4T62UGrtVMpaqXWPxR0uZ2KUN7QQm5SY8OWoW3XrWXkU2AUodvZXoX/ZyUlxHWN7zNX/Xb
bpaqzrSGoZvlGneOnqA8+6JF0s4jZrUswKYED5KUqz/e3Gelvc5XZvdKCPgeNYXZlDDyqn5DTz7h
WQb78dMDVoPZUsS+4TEWaSuYYg/8rWxwj5ryYFQ5rS9O1T2VxDQg4pXb6D1g4LzY9bFEGAFn95Vs
owhdCs6N2+yoSGuqJwavmwNTJjWr1IuCpT6HBKjBb4Gl8qIMp1gyNOpLwAGxWh14uZRPEp76JZ95
cnG6iNGTmm1q988CHy4YjSxl/4QX7kKYBObZhDf7Flv69h3+cS33b1PJjRN8ayMCUP1kDrQjXXZp
nLyrr3YxqcMHOXoTWfhfJr8DOaBrygFMeRCinvKIAal5fQovMGD+itYyRv8b+x4k3AalvhR8bVKd
z5UXUiVuP9CSWRL3cV4NByqL8yF8WwLkrtkP61v7u47nO43bCiIk/D82e1MOxaFauyIZ9Cl0rFob
m9q/YJNnJkRzxdGpW1cgz/MJfnoZ0RXvDST6dC710SvTXmSyI4DhyZW4tao+rVQiPq5yaFKQNopW
UIzPQxXvwcuDnIQEJ5fjmg5uXU5GTvqEGuT4kkXytGAvytt4ODfmNBKTYMj7+iTYRcvj2VNfdRV+
jbzK44NBdlYKfUh3d9dXLCX2IsilDyNwAyCRTSeg5aXu/2j2Zf10+oVWZHEFAAsl/0bLJl6yJncB
uonQGTsw0hgBwVmuARlWFmTwMqp1ZzayNaQrqmvR9zzEzrbKJffcuJNc9muMTOaCKpxRQt1Un/3t
JQVULLs2QZ0C3/q92FwgfpBbzgcqADxEmJWqE/tkSf/afPn6Dmh3NBrSjsj7dJCuff7fmhsCq6Wr
FbKctaOlyAsbGchuQpD5UnQIZMgVlSMlIZLtsgXIwoKq/r9qgbd91p9ur5+Q+9CI+0bOyBEdMpSA
lMRsB0SuMjk1SGZntzDGnsLfOlCjwlrrzw6gsPP+nzwEjlLRihxYv/1KxbLcBPhSAUBTW6YsornH
2PJz/sgp/y44bw21aeqox+ffFpoga6B/8vy6O+t7faLh4hEIuPZAzkTV2fEPXWSY64J8dzyU3g8D
WE+NqclQgZNkRk8BK0IbWCPiF/2x3jvcw01an3ytuHwC4jGk6dljFiAtq5hJ3R1bqm+OnymDoghp
gAy1vhcoPdmhp1h48znsCzmCrWO0rO0n2+xS/EeyIS3HEWc9S9/bBEvm4rQNxUbDAN2RgaHoqhfk
M78zAYG8nx1HHuSqor4N6+R1+MT7kyaQyEOSPlURVWiXJIKUTBUYgGjFVKT66r3bv/d3Sa6i12yu
YXXyI6ybvhlAj/fyEXy85ecSdMJ8O51zZrh9BSm4J1qEjjwNk9egxblIKyyRslJNJ4EoF5E3VGEO
PMUJsK3UxlYMeheDYkqWknPGwQHW65n6YMtNg/mqG7RwCFbsL3yQHxPfhj8CqzRYfCVzT7wor+aN
HoOrY/CYAKB11qe52a22YjsSOpVe4Tjf5Ioz9YzPAKiu5TOYqwHg9ECIGhwFARVYTlnwwrvEFrtI
9OoSjegZziNjNgcK62WWrZy5TcKgyFq9UxkZuqfyTt/bUnMfSK1lKl92wxQf3W1PQPEje7GAdcAV
fluSUwp1A57PBD0d8EMZRrxQJJ8ma3fWvkD8knNFoNATTTuhyQjNzA/b7M7f+BpX/nh8RHqZVdDR
sh7bU5YH1aNbdOolVLgxwW8F6isHis6qUy8OBGERHnMm+Ruv1gPVu2bb6jNnJef+zUN7KyNWYe2N
ZEw3GMTtTBZttuqFRIc94lDcia65zjtzBJHuVMbPWzTm9cq/8cFP/3aW0KqxubWGoOHxAZzEaSYX
rP71ghK0YJthu4dtu2QM2JVHVttt10l9v7JwapNY6dAUtKQRHyRa4sOZx0lSnwmb8F2ljGk80uSs
kVcJRpnPfo8rxF6X3+oGt3FIqW/VKZqoW8MJRgm4kBpzfIAhgKOsvHLWBznNag2EV6n9VYBdATPK
dv6zpoldgRfznYAF6V1kcUUWU7KRlW8PoDW5jhyfHV+X7cnoDOOwaGtu/3xSR2NdzCWO4+aaMW7L
EJ3nFSXCQiVjpSM/zR2TWVzGhie3Kqjvl24uHEUEUv4GsFRl0MrT+LtwPzzBqnt32gk4n4j9T46o
8HPfYCHaBLTHj9SAaFC7LVbOsWzE/Vz++QAXTdkFO/OMBAAROjrshGarOFeYz4ZnklwA+qIUzg44
IFtc/ztkfWylkNVTLpHvK4jVt1EMByVPNjV0LLa4B9pxRh9d9nBRDpF8CaqQs2gHCnOUvfX/R2Qg
J2hhpS7y8p6ON9KP96KCeh4H0A7NRc1m//D/dJxKCgyF6D4zRoxSCEz/B+T0wwq3SPPXccORiNOl
rEOCDjW1F5sj2syL5Yz45xHhRlFg4MRArB1Vd3ofdNEcA8kAFeSejzq22s5y/3OkxVhs4SDGnTqJ
R47W2x2VhtCD7Uv+xvpHgh3CxF5gCHMnf2+orh26KJrgrHvXCKzf8BaIbUxBaFJGATTk3LcK05U/
SA0Ub8CSnsf+tjZVWJ2IwVII6jyQiN5hAmimFKv4d1dhgWxlB5Py1fTHseF4yFllEZqAMQJoLH8y
d4i3K6G4cEKy0/1aSGv5yHMt8aKYkwqrU7o31tIthTn5ydphtSdqYO5q1RKJkF6RGY3KGUBBM23C
m3Z7sTp0h4lx9evpMGkF4KgQJh8RrOk4HyRMb4xQAftWxENRQJCsyJSiI2tvVOVie5HrqjvWRy/c
+jXDm1nVEr6faY0q8acxG9IDKZ0O4orM4fMHpCNW/EqHDwpMca0ECMeLVrTRakbbEcWEvPZOotnQ
Pd6XU3tYMdP0Rai0f4ukK27U7pPsEkhDO6MTQJ3xDBt3gRZ4m7KpX/TdE7DG2/EWTrmqFSCpCTel
uzzC9T7N9ItYVRCp2sQaHBzR4HYSvM0771U/OMUWwJyDLj3ZVBaAc/kvjgGTCXV2gini8XPwAsdM
LQe5l5tMqqRHL/HEjWkGHhAXC4/5B29kyLApyeQbA+v7mvSyyPBvpbH5OJKo6Ll7lIqAGnrw6RQ8
fbWNTkSy/hzXJe4ob1zKZqewprxca9mbRA3XO7t9Ksyi62MjBvegxUTc+QJJQD2jEHhTE+aGL+BF
BTcm48Kzm2ppf8z4hYq1UGGzzYM8rzmG71aR9SSjhYKnU4+QO3kOyhztEUK/C0/2CXtdCsZ5l40Q
0j4otPF+IU0DIoUVyKZFg7dA/WvvrgefGML7Pv/Pfc7sqam4T3/ArZ4ZBu6ioL2+HvbpkQRzHnYW
I/GstGJTJeCyfCiA0mPzFbfQm9SOskN4oc0okBc+bYOFq6UihQNJN8bpBv2fpiYZErC3ZAvRE7zc
/ZIaMlMtC0ibOi9M9oh5KP/L9JsIclUZEGmK6+o91XNXKs3Mhl5HjW9F9QT0l4uWTZYKf5H1Ujqy
zwcFzWv9j/IMGvInBOBmVuUdTv+Yn3umBRJoOZ20x5VtkjHOt0uxDcrgIXrXPZe99P3c2usDy0S9
meHQgSE1Uz/WBxemOBgpEMtrue71Mqro5EZGy+NX6lER1gIt+8KsAWh8BMjoVlCmtL30NQoD8Gt7
3ioLkXqESjjLfLIvqEMxGMtnG/gZdnF7gjhBdO6B8GEVwjhlfCFkobr+hKjUmQnDqxOKJQ1hmjRc
FUx5a8xIDN5orqQZnwefQh12sVN7QPvU8oLsOXw5KPzkA42VhrM/Fa+JQR/fFYpzxQJhESU6Ub+G
GZFZx9XQiG8kLuuSyUasJFwbwGTFzNZp6faDN24osGDPfip9K7z+IGvpXfiGPE1C/KrVBb4xNCRC
IKf00W/GaU8fwwwosBttavrS/9zE98OHV2t2gEkEzpWwTXElzn4Jfnww6EqMBrAnlr7qGlEm06O1
lY6nYdZkMt+HPK3xJMnP0m1CYDYk07E8aZFM0wJug4HxXaot0QyNJOYwukCE1VPc0y3kEeTN4GAU
TS7vy15ZIqDFemQrMy4kQs5Ipr+2MLYFOh9rdRs1U9CC+qS3oNk+z+SUQBND9HuXtE1r3mMCzX2J
MsN88lp28R9gzVb1fYXNxq/3znmA1ESbnAQzR8JB+dTzo0FOYiHZWNt7xGsSYXbob3bKbgGGV9FQ
eiHEnKlsgm2ngCRM0bM+23R+Gtu5o2CV0NmsJP6HQWSNvLDFXfNtUGOQI1NP9VnZEq7nnIUNH1K7
mLNhPSQPSoFsACT8jULDygtJt5Z6HBYjnEyetgzONwb0ga/WNWreVcHOiYNYOcySJz4enA5GgKuI
6z/0uNBze5ZOybyl+dEGeJHXKMpN/QCbgE8pGtfK98y2o+zHNSdv2ORksRsGW8k4s5DbVt6zKzZr
lg8t1i6cWbwh7ELyRGST1vOEzZEuy4NdzLLNV0Q5QFeMLlSQzh/PHo+K1ed5HBx5ti9k4KTBe7dn
phwkcDCUzaAcO96MIUgJjnLvlYgxWJrPvkI3l2PXLLD5QOqqfUkf5CHL2YfnRCA574WxxP07TUdW
MO5++Tp7j5R+8s7KsVrDGGnWfVIw0x77uBx7xX5EvoVZ66IXK0b77Gk4sy5qIbXUxMwU1/MavDeN
H5sDWYt5YEU+meUkAFQQd4XV1GI9lhDb5+GLEEdmviIBR6VhwptlG00TE/fc0lx+LZDZejz9CWos
cLC1Up7ymsM1mzasetC0wTWHRJ3tfglFC1VEvypxEre1ELgogl1yWhYjSNwJRNzAJAxRSR7WeIeC
M6qV/XTLF12DwWeiCJVxFquZ6igRvNPHDMM5P+3i47HRSTNG812eolSnnK20Dyu1BPKxw+JEsray
mp5nrRp07Tm4nXuGT281fJa0TGU0G5Qk/WmSo0aPXwG41RFrxlBr7vMhHuxBRmZjeYKpJ+GGAqWO
wHRa9Hcx807SlbthifMLPtrSnyvVRGB/E2tOmFOx/31k53e7YMz4EsbDn9lWLPQJctMdKbr/6T61
rdFlygbPrYOPuZI4kpTrEKDiTIDOhltsvqXOLkWU7zIxr6VX/SYAnppAlkR/cfImQmecW6sNsWdX
++8JKaTYwJGg9NG7uofV5yOO6qi7LlGEPCYMj8ihBscg7O5+UM1K4n2y3i4nnlOJyayKs3fsXW3U
OTPZpO9HB9CCJ6C1gWfnL7Jz7YZyLwAAdByhE3oJTpiflVOQvazrdYW2To74eq/XG8+oVCVp72ag
4/bQXOypAEwYBEC0rzvskljaerof9hR3IAQLnFeYRFWD/XH3VJx1s0OOn+g1XbCABii/Fzd7FURo
TeNpKbTnGy7/hPaAG4R9buMzh28bjCgD1rX2HfTt4FdQxD4QtPh359pJTjbkqxswxdDoMkTRr6Td
0UtfLByjLC0riVBbn2zpXJ/Ow7yAkzJzUgVGTa0kjvtDxik/YSOglGu3FErLoH+8X8O6TYUajwKS
oRg5YheX54qNvWP0cfXhUM+E7SltDzPzi6nl16z8HXIm/Qs2AAkz4Ad7JU74Sv/R4m042kZH2KJ8
Bw4Nx/UJ18FLLzX59NYrt5tInsD+xJ9LAQNrxGP3xZ2UIDvAzNvUq7nEv6YT4XDWner771QV2RSG
yXW0Tn1YPcnHf+1Xno86Ok4TOqOvqSGBnyrRYS9XdAk0G1N59NE85IPPJSwSMzy1qDU4ubqUGMnD
yLICEobpY+7Ua+/ewxqgHYx7uXPGg3lFDXL2y7bh8qOJ4oaL23ewt2Sy4gyZy9RGhGU17+VlMMI+
3uZ090UMONOGzDS7y4pz2OcZ83MBGRDeSzmHhRPOQm8gZM6Q/5UoT+gmCYLpgM9xqClw7gmxEqon
JJ512UXza1XVnZaRtQ5e9wPWKsZdaNHPDxz8OqYEsmX+lC7/aq4ADcwkvY4slc+2kNRJxwhoeY6V
bkz+n8y+4l508jy24DHSLdsgOqCcnrsBaJxruK3/kWjynzDCuDkcF2e3vPJvcaXevfEb20L7rxj+
VNgH+6jPIrDF/Q4r+8ulA7PGcMj/d806CsfYNszEL9w4IOBPYjjFJkHdk+NfjqmOGwbJts5rOSdc
TQ8LvXlfzZyLzp64hR9WfW6B++ZsOxUZC0coGmw7sG53Mp2Gz6KP6Yyp3aXPyI2lsHzsSnbEirb+
XWaHm08r8jBO8wT/e0nIeVWyh+xDlGGB5rwTAvWepe6Wua3KH1SMCFaf2zmjYcEuM4/Tzja/ARea
D5aJUdmP81QjbMJ4ZLQHovy0YHmeQcjcFelpP/hJTRo5b9SnxBrIZPMb78x5v/zH5kM0oJcJogTW
nvCBHmfjVspoDyiXjHSsJh4YwbfJ9x5W5FHPZn6DkCt9TZ9sxFEyen0/ncZ2J5/c2FKHDNmfvfOP
nDKEx/d1Lm/x4VlYPN1kwrptCkRVJHCioH6kO05TqXhuO+AHuE+aC2bynPnG0TzzhxDdofqhUhMj
k3VLDA6HVGuVR8wlzx/DCjn3I+5ry3EMUOOcvGoIvCcmEV3rYBuhrF7QSDwz+8ilqU2OUL4YQygP
yyq3txDKgYkHKjQ1456dVnNpUGL+w0PEEXAFX2BJFgHF6tPiDta9mce+wlKcfFDS5GnOEeIJDJEP
fOwYZW3m/Mc7na/BG3oxV0tJiYrG7VECyLrRp2QmDGTbvhxcVmKYFN3Wjc6zTNNyhvGDRvxPVXuF
olt3rKO1jLABe6LuGge3DtDDOwXfX7gmMwUY2n4vUsXOipx2EZaayJA+dYIKFjs04c4Sj8KkuAT6
/au+Sup0Nrsgd2TvRlwFj19rqeN5r+qkpLd3GzVIHDq/ob/c9Z2/j4Hoag3Kw5fA+EkqDQfUsSK/
9W6wmH2Db0GyJb/vMI6LbUbWZ2qOnKHuM/gtffOLvSy16HW+zMw7vhs0L3t6cI7+LNjcOIUqKLt1
mcfZa4F+WYto5f/3n/q/bsn7NkRGyx3Vxwdxtqyc3uVtq9Jk0otUgFbWbcBcm/6sgm37hwBVPhfd
99uh/zN8o4oAg2bnUb1QYbmdmpmE9jqOe25A9a0kPJJnhXIzqAXZ4pAPap9r3QLEWPFpI3jGqolZ
93eHTsdr7qeIgAjORX2KfVpB4k8QD1iJANJ0o5y0VjkMbG50IznaDSDP/5g3YGtfHKIRtyBfAoyX
0Zk88QWILlOeMXzCcqEMe7wvvf/KWL29xHGM63mNxFggO0OpnYZPUEzUv2s8869bttt5wmf3gZ3P
Qm1Mvmqisv052ojV5TiNwhuljAicZ/WE49kMFbv9yOlVglHdC9y3vQwBNEhZuOcXmAIPho2TZZEu
4t5hvF7+qspEWKPqzX7LYK0EJTnKJxHVhPQkPfH+UBSSO591PtBypdLfuq7ITMyT56FythgWnouI
ERHNm2H5KmpyjihXKOvpqO6xHb0iHazwg0a5QF+z7v0uch3lsDGIsbt7B3BByHPs0n791GHs8t+P
Hsbpa4n8NgLknZWMSWhWdc7w5OgbaoAXy4e4DTs7F4ca2jucuWN36O6i+zWZnD0ptLvTeDChhshd
g1vPkXlzy/3Mb9qQt31uDufUjXGUttxkOehofeniHm/OfY/gz6kl/giueT8I1fksuZVx6lkEDvPL
hHq3+GQTbpHWj7Cpcscbjh6OwtTWmXrZ1/h9xtfweD5k/N/MvmeB0sL6E4fKnWN51FvpremihMUh
nLXKu77hs02+NRbkqgPrP1Pewk92XeI1mLyrnNT/9ErakfVoVJZFN+ASXcKbXVUOJvzkQuapM31g
U4aQnv28gtyCd8kKLl/gZagNqTMymF1AR5+yZ8HU+ZBkIPrXmbMJg2sIOqFXq4CtwwoSgYx4pW1z
/3lMPGil+Cgn6sP5rQUG4o/sFcM+z+6LIgC2rWgHULMmyYA3PyA0gJ4m9FTJ8zjPOBCfS8ez9DX1
Z60Nqg+CUiSSuqvbKu6ATmWyd7jX/wPOv8rXqbEOLbzqJJNpEmb19fFeKwOGKuHpePrehyQNgySb
tyWch0QxNzhFMyZXkm6dIYuHed3++2naAcLYxhuz3FZRDGf3QYXjNDUdXUVPFvRVqhQDvEfl36uO
PVxyLBJXpTy9WBn/F7Z/54mIcXubv7oO7zPJV6YckRHnPEPUmG5vyynVRQ57pQiSXTSKiPq6tC1R
+mnvNgb/i0lzT9tz299wySnOvZJgsPoY8GcbGTPhg0C2R1f84vwVC6gDb5XoGgxS2NuNY1RlfOUH
gYXiNv7K3LkVxoDkzmeqFxjI2yKyADVOYEZunp3KXMcIHxRJu6Vn3h2vG5LSupb2eij0YJ4i5bzz
dZ712JNm9SfqdGwXC6YYPpUzVVaf/gbqdDdwTYQDe+S/nZGCJF6WBzU3bh/XV5mhj7aJ211nx8Hi
j8zAfZkvNZEbgVYHO8+hkuH7WomLrHeZfikjdB6MZ5yyFG2DXmZYmJ4aNXRS0NtW9Kotvi3ieOn0
ntw1iJ3HssS9NzlBEwDR8rGB/2yYu7duzPmxkCgqTg3/PaWjMdg04C4I8Q4FveI3dtTJrQYHIFDT
mjM8Sa+8emRQ6d68P75g0jPMXK6H/g9U6n8l1uRu61ct+WsO8TFdDFqDlJ+8EDeGycQZvvj3LV1o
ML8ijrP3P8Dws8R6aPwQzO20/tr4H23BsylGTSx4OOPekxZLGoY/xcFk4NmJ0EiIfPVV5j1gajHh
EER0Loi9v/evmv30ZFr0w4wGo7eQ9Q8hLWCDnBWGGlzhp/bCV3n7H+1oix7k6DxOn0mKOWsv8Y1t
H/c6RYmpc3Lw5EIxq114sJx7ogbursdrMusCEWDmNvpiN/NembrmKukTZ+XvOyY3Rgx5RxXVN1fa
9XMkW1fF//46U6Msth6lKE8fVYWaBj2uBw2OFocBeh1o49gqnDU/5tURzvoTsr5Q08gdd7q8yN/n
kHcTGec7g14lCvqs/Z7eFRP3DDDw69sk3O06TZ2TiyMO86JHQiDoCkVLdS9ghMff8rwHVi79NheI
vU9NUUfAcNgkCzqCLp6aGqQTJUkXgkOtDDdfTVlDY5St4s938ll4ZS1jNj6ygNhJ3JIWlug4AxSJ
LDnAfCv0mcaR5B1JcEfOnlH9U2vtXObBs4UpyDKd7WLl0x2pfxO98PGpRqwsO716DQK1tTXoZj3y
dKmwY8ME/kzDY4rV4/JgNBVX62/F0B+vDB5a8IBx89R/yNoR82NpnpCqJIsQa3d/sCkHYI2+ojN/
9FaJnaHyUpzg5/Tu278c7p3hkfmdYC5d+Pq3OSCVT4k1zbZULQHViW/3fD7OnDz9vOaWDl29Z2FP
F2HZrTFhcW+DJsLAiqf73X1vVBj81iAFU1xoBUeACFyIuaXUF+ZJYquaHFPG9P3QgUP52qUHuRzF
CkDhHt6yqPjJQbz+2ip9uvQ8Mvr00UUnmQ0Y/Z3V00es/0SCluoRecQiDV40iBVmZjkshb1rIgtS
VmF2SCzmsAMedlkqjUuWikYbmCDRL2elrBhUoannl7KqpEBO7iC1KkKkH+aB719r6x3NwGtqD76t
iItoPCHxsi5KRTgRVXjLjoIw9uCQcvwjxrB4UYLqfuV6wqrRVwTLgina8FKrixJBIjkmlIoPHqya
u5XecNqbeo8Q8P1Co0KSNjdGTbbu1MI9dmMh5/zjlbNy8f5V1cN/L6Pb9gutlr4HgYg6h3bUaY0N
CnEGfsTgk7LXaD2UQQTghtTlbmwCXOjAkqqUVAw7U4MSDKC50UG+7UUlatmamd8AQvMMnRUizVkJ
5Y9eC9Q2XRvVvphrm21V0WqX8JyZeTM0Qm7C5Grwa6hLxIS7KfYw8Dfn1rJLTvfSghKNz10E4hxn
lHxFLh74U9m3l6gHckdzO2seiAQelAPz2Fuqx3z8/NFjSaAoATiUw1jEOUVD062g0ywxQKtqdIvZ
w0ltvZLR1da6F+sXFS+mKumUFedwkmHGKmU2QX6h43Nltnm+Ac5sc+xke7f+A46t6VppCxG/nqNT
YaBbwQsLGrs0mnPH/aMqeGEx30pm1/4kzr4IKCEYz1EsAVcb1YX8Xd8o01LB1Q/s1kMPbeasQgWm
IDblIUNzf2tpRiVqYbYLkz1y61bZZNPFoayr9BPPGtBWwIWOFyp8r7n0Iaa92tNJn8/+dFpSLtiv
qtimGwj+ux+3c0lAifhxshCpKMLr30R/o1e1EPkr7DJOwnswLO2ITSZOIedjnxohPP0d4wQpqxeN
MZ+8CJdfoNvQZ1GfMr7HlhDt4ekE9SoJHHVo/jI24P4ZeJ8C5LsuDiubRtkz2WGqw1KQ8dhXIenm
8LIRnwd/R87ZQbCNUzZqVKM0HUxRbPE5KU5MMLaf8h6YdlnWkzjp5dRfwR9ZIANHD0SDvorcCxAj
6gXQ5NOrocY3MLAZ8A6KhYqXob1rHo3tTw3a56KHW1mPOmrAJM3txHHoJitib+GwtNNUSiLsiAvs
YNnZwCr2Dbp38J8Bz0DL/ZCWHHuBV6Osg7HF1TgdxaL+1G5sE6otGmBNjB1ormlruAAt+OEJCrCb
LFlvI8JJ0t/H2ujqtWIygSr7K+SOHuTuI/r9r/ZRCARUpPnCJimU+vJ2V3argTO91ddwWCcgGyT2
xuRtLw+xb4TvnqBOLUOPwFVDN/tCAQmDWSBFxpv3rzDgH8ZknBqZFcPw5NF38fcQ0E83rRCVUN+F
MYsNUV0sW/5RyyDenDEX9AGZRdjJanDGO082tNWmsiAX7U9Nx7nM6TeXLPhGCv8ZhdGgxjygkk82
x4My/ebYpB9U34HgEN3caPHkSqAa6hwID8SOfxSo7RK55swEnMHpTds0LxEe6YngeByfL4hMpW8W
yVuJ/gSGPhbmJKmsfdcRNx2P12ZlJgIy2T4dSld0ZzCqWJAlFwInSqd7e6WZQP87wvKG9kL5QcWn
eqZjvGeRQuVxOy5nm4w39t622f9MV0xRgtafIBRCl+8R05cIOgmBCeeAjMiPnS5vmEel6qnYRq/v
An8xy6nxH9Tvj3HGGPNtfr5IZnqsf/GmsOdISJttVWKAOmvsNQzd3/G3JqY5Sa3gOvbLmN7XvvY8
Yb0cV5sL7S+IPLcaagLOqx3znxtChX5LQGXU9X54geJ74GeEiQLe+6+MqnSxkWl1wdpdT8exM+eC
jEJhJ1T3GTmX4Sg0HYzqoWKJx6Q3rrc4AO32/f3xc4nP6MXs8D3OQiWJCW97eQWE702jbNU7pbHj
e/osNcXJ6EgOxUKpQisxdWnmlTpzlQJYO4ZKPbQcPKI6ZqvBCcoJfyGfk5RxzuXLV9TAlBRZEJtD
mVeetNJkpGdXHlOxMqC7edjbJzIGJWWrd+Auw39C5yjVDAyZPNnJXC6ozCMuxnxzm9oe1Bk5Mo4y
jlBGoU/+YtpraTvpy9LFYEBXeYuHq0X75wp86XAKcbdU8541JoPX4xz++6v6CBwPkgNKyJp4Yv75
0hDs/HvKDW9rIuoa4a2Qzm68qu2VKV8Mgy+AcNRBOnhTFI3CoXxkPE1UaZJZuzMavGQien5Z5JVR
mqyx43oozw1fYT1HH4smC3MYuBS7w42N3XEOjliArBXoW3fMRwdRMQzvqzUsgOJey2ApElzJKrjl
bLwZcXs4som60nX6efSYAgc5QSQwUkVdcetxs7O7Y+PnhgxNdXeYkvMe4xxLteADHL42+wW++wG4
ay3bn0a4uBu77cBStsMtXuyRAQrAtG75cBEwAWGPLoiXxgKGUEQCim3vT1fL8xE3JMzxCHSp3j/b
aYLl1SleQYvLZS6M3/w2ZTc3S7wO2njWsgp/98JslHHfPhmkJRbnJt6UCHm/KS77SigXVub9dWL+
5fMMKGCaovKdGKfnqcALvtWMRtD2Jh2ZDcjHsWlxqMCkPdKfHnW8y4xJkT16+6cfGMUn3AxORsmM
1D6Cbf96o5bIwsV8btrrnRi8+LzzHPNYLQRH+kGU1dSEBnyLuNWE8ie3YghX6VDchaMdLnkh4nfH
Flvi2K6UjZ+/zH6BVoL5ak2R9woDlj8uykaOIshk3+llhQUAeT/5Vr921biV3aOt9QxX4Jn9U5uZ
lS3qqNsTITD/r2YlrTJblurZGb11bvB6bLGZHjxktqP/kjrOT3YELkQNmtmy19mtHicIKDNzZYsi
hOEYmIF5tLmBX5GQI89fqcaaYiesiMNiG7bZxaikYPNuWkAD4dXPily2ZQ5uDkcnYOiRIyQqC97i
YJTq1uR/bDLr1JoK/EYwRvU7nCsjlGriba33l1pcbYgJ338cTyS+qe6NyQFgrcW9sI7n+nqGFUVw
9DtUA1+NhkWIVKbqvErWGUoqg1xdpqcoRfYM2dDGJiCExdnmfFVsv20pwuFX9/d0BTZaVNJqWyDg
I60l+gWJtDEOyoD/nThgn/VzxpyaoNMTk+3uZra5vmS5528DFvllxjn8vBs/pf8QDRpf7t2zUNA8
trEYgHqJ221C4YujMr6mgsNWiSBl1MMBF7kr9IYK318gohYhuHNcE2+0051BU5IcAIRsWtwiA/D7
7qaDifMrdg3RDC8DFFc2nOZ7OE0HYUwO0BIHaR29t94gNSIDC2itvLyW2JpQca+CSjZK3b+ZHeXj
+SHKiGTk/7C/qIYENFgQxSKpHl1gT6ieHna9nCc95VG1EI3xpaz3j5PpzW9nfYI7bZzALVX+qcDy
NMTs2m/d1V8MwEYyN6TK5gHdcC0OEbR+VQ4OUVK6BX2UAuRuEL0HhzSkXXIzn2hErXjf+RQMllGb
EtjAH3w96aRJvIw0ZAVcWkDmi+LUBUOqZURadIpXLgMPx8NWrbns+GzijbYMA9ZlI4yJczO+U6GB
jcSreqxxwrwjwYrhmVF5HUu2YpxjMCpChqfP7yZgK5neJZDaJfINns0pkHHumNWPTsTk502t7nND
y2kf6FAI3V/5yy7ny3r44e/tZuzhqh1J8YyQiwzqIzc10RcbjGTvT/HcnNWfM4u87wxb4UhWr98w
Ku4GXj2OUiG2tIMIMdZJ5M/Qb2FqSopbMVdIR1nmnlkgNn/ji3EMruYfhm5Yarbmt3Nwy18o2WZc
w160iRJoBDBJ3kO8OVptuPutKk0fahbDCE7uUAx4CPPI/qRTMKtzvcGwEVXyWe1cPDHKbUAK/o+h
8QYc2BD6Juy2NR2nApWcq2jBZDV/ZcER9BRxOB6PD1PJTtfO/OgvH0u8NrGjI+p07dtij0qOvkXb
llvnU52s/w09HBa7Ctb7p19zT4hpaFjqHhpAToJi1z1y9K7pcKGrpLAiQSE9m5AfKQA5P02JYtXP
+zZFJY+DedG8w5ji8+yKNWoX0fcAp/MkH7IOeTBVUJ2WV7cXwo+iifEA0KHcbzsAGU9UYvqpS+e0
ih+XWk8RfqTF2/4DL0bAdS7/99asUPHtUg66DKdVCFZBwzV8ySFs6ldyGpq/sxtLuPA8IA+2uRMd
uia7yyjv7cDouPTFrFVxmdCcsO9csa6ZUgtKPphqS9uzVn/Cuc2fWKP3LmPE0cfujDVRCbiBxojj
lol0GUXOyGAa8l83q4J6v9NbFygBfXu3fnT/vXsATFZdw7uubYSax8BJ5xzHDwHD/D8A5PnYtV0Z
kn+dYZUeELRJrlR4sxWrJRKhvcoCBkK51qEcWI94Hvs1QvW0vG9K8qwJXcAE1H7QYndSDVzvUhHU
FDh+Uxjb1nULYt8eRkeRCMKEcUl+pFP/swIVL3rgiukWZqIFQJ8mnrivNDq8MNWgfckzOdTyKfoP
nnEf+/oBV5WhuPVMbw9UCEyShDJ9BXxnb4dtc0m4w9OcYXRqSko+Bi1PEmtZOfpzM9dWTRjDh2DI
VoPNGrZIMgAJSRoi2+DAzkxbV18YdPRJ6TSZD1YR7O9gsYOr9RVpVKui0FqXEIF5cPoYDvc+Vq5P
krsrUCnSdhzg7388mqp6BM6NTgUDTuDxtBEpA0QTzRtTw+B+Rj3U8XUgwAF3r54ItkqXLcZCU/Ay
gwyDuH6WS5S/wm0uUSaMTiRN7bHpWYCbPs1CNUvtHgp6v0jMyk4Y9vWbQZ1iD5+OyCRFf6fO+PW/
nSRYMh0cEcLufbYQ6K9tBVGyLF9OBP6bsZS5gHgqPmMhqU0NASXU8G5GDuAFcwta5gg/eIngHzxz
j5PvyDyqbY9669kfXGb6UtUtHSy8iN1HB0pq3TxtHOLK5F1n6HIBAVI4oxF5kVgndmCWv66Ocw0h
AimORuSX1d7QyTFql3hWFea90esDkxAa6jAWN9bl4Ht7WpFqyBskYL2ALaVRZP6r9ILHTyO93qxL
3S3S8Fktk76hEBWY/XwDoYZrJs5KVTSyiqVP/BL45UzkutJN/x09q/As0aYgojCg6iz9fZBI4DKR
mD5VLZNDIJQbJ0p0F3Vd8/9ujGjLmnMAWWgYjG6NALZ90o1LrUlKN8vbfFPAw1TPq+SOOE2Jjblv
H6fwYg2LR8BF3WyWT4ev0jrVl1lNOsxV8DUy0Al0eEWrpFbJFJn2hljP90ut+fHbQ/amtE4VX92c
wLxlFu9l5MPoEeofYEzgpI6VULH1JZTmZ3DLYz6VkVgJjMM80Gxy/UPYHorv/KKqEmDiJtWYbt6s
RHztQoXtCiqmRWptCh3E4TEmbIfPSQuMBtKA6I462q3XQNWzZadH9/cAlav0B3P7d4XT28vIjPVc
b81Y+IPjeZCRwPlVoosop4Cmf56qzQo1yIVqg3dQGyacdwYDr6Rl45OLOcCFoRN4Rx4c91fAUetZ
EdJ9Og2Ea/ks4qmmb6pr5RSXG0bP4mFfSliXHX7PdAdf9rlb0Mt3RL1VSGL8emMMHqCgq1fYnnYT
OooK3bp+Epn3t7thCPY0LdgaqnmtE3scLYmrTnX/TRsSw6LQ6Kph/evS0epmhciKq+La1hYvselD
fKEVvAgi7cSuLn2+zjjPS4DvdJYsVxn5DsqmR+h9L2yjn93B/vgOY/nWPv8XDDI0hmzdPaQIRlWo
2s+xvJFaxwxp/8kGSc7wemPZuRwRKkBo2zmHY76UIylNr8jnJbTo2MZGGSel4NS8i5wJn97zC19o
cT4DPLIJMAuA9IqO34LPS0s5edMO3k9Lpo12kcC0UJT2AARJ74miUd52EWpVZc4EOfvnq8GUEOgS
qs1xUSJqDMZXAhzTt0wGBm6usisXJMOM1CghtxBq0Ty5e8cR3Q8sctzrqPX+pXtQMyByhtYDJS4s
yWxKxUUY2aj6zM/EwwVnX9HyMIUwC3cA/Fo9id9N6Tposst/1u9AZfQ/awYe8xlmu5Jq1vgeHyo8
/W2ezQWfjP8MdbisxahFcIy7ZxJn2HgAb/KSrYlcQCZqkLawcDi8dYV1zbTr8H1l95Gp1Z0VBVAu
e8Amhz/trwJU4mZPyhELpST1jRgsNQkMIVekDnmjf9Bm0jURlzLir91iPPt5xTqPgvTcseU7Q3KI
E13VabYwJkTbt0ADoXH+kh2SZ5tOHvaWn7NIig6OrimDivC5ZLUkMInclKYgeM+lJBmhUe0ol9tG
9fIFVbYWpoYCaPsu9p022wb08XLz9FMJcCddBGCD/SBmCyNIZs25SBvyZ0XdhLoaYkskKWUmy68e
rgN0fJfmgZC7pkC6Ggzc4meyF7MBbv+yITjkTB/1yBgPL2PwrdC3BLzAXLDbFAVE9maT6ADMgaX1
JxaC6wqh3eeC61NTzg7WtS0nMwx64ClYejnuw0sXyxdaYhGM+pccoX4aSRQbJB7KRhJUbjbdp/9Z
n+8HH0bRIA6lX7UoPMD9aOI2QcAdJbQUjeKJaZI2vnVhi/hJv20JOgfl7lgjAE5lcyx4po/zZNoi
FkXaPCyOSS/ISfu6Zv9rCic6aO+Oh2OLhsvPneYNUlGXJ4DsUzIwSj/B6pvr8JD3J0PAjuF1bqmv
lHgGPtSr7A0gt9aFlYJjFsAE0lPVo6uVKB51y1S5cfJzABQv92rm3PURc7w07jgVxqtiCB1W7IN2
HuR1IsZf+b+3XowpggVXiPUN2OZCWiJjitknemUGP+HwcCSoM30Bybl+zDtSU+tyApAHxyD7fSHf
l7Gs5K56I+Mk5vdKtLy9deI+rPQt/TxtjFbuxjBEamHvaYmJpGRsSVQTYrlRkMWASY4MAwtPnpu1
M33UdxlZqwU/tsmGKpHHMTjGeMbX5RVEZ0GQQtYmYU4H3dBQa189MMDun2VzBLHbnuHB8puGiX29
Njh6h7Q4Acohr8W8hgPpGQFGq8u4Mm536zJBYxWVoiD7BqNKEsjgccJa786vLQH1tL8f71KuPTWE
1S7J1WBMfv8ENNdslqiJcEsCvnWzX3DoUbnrPxXCp3VxhJ7iHnm5FAa64GlVWWipLKBsiCEJPb4M
F28fKQrxj9FbikbUFuVEf4Q06H8BjGc8t0q2ysj3OrLtnRb22CaABpQIeE+01Fr7lItG3O/WEni6
BNqKM5hYh1P07yFg8v18G0PHLy3Az0OXDCVxwKz8VrPvBlU1vecelTAQOzy2PEfNKu5TeIq2SqWm
0hwz8X7XobrnRlLvCFH6JUbnlwcQEMdZuejV9olqN8I8Ljbj2pbwF1FvAfbVve059dzU4yPI5LTd
Bo+GaFGbDG8A2i3oPcMRIGO0KD8CdQqtTlujlXkzn8q6TH9MHi24xurukUfGLBtjaQH+hJR+FXcz
pHHrt37RHUvnU2TSx4dX7y+7BALU1PJnoykcfF+ij7jqaLcvX6ZkIbygg2A0sMcMVMhhb6Xs9HEf
K8Wg8wZwzqi5C6go+8+GY0KxxRKzzyWdr4T9L2puGkKe7tzPr0V9PYrgidrG/Tc2En9dp2bUdQYB
zIl13UxKW5Xcw/ubQkwE+pJWKVNbQbA3Lx5nVkJInzMKvrzAHRrIkj3o4HcTwnW3i5PG2raMCUTj
OG8wPVUwDqD7rQ5rPNhSQO34CBlVH1tAhXPcXarx7JiABGgWS+vfsQFMaNFUpoA4FzNU7vwjiO03
kKC9Jkc4qn02wWOobvU2IU8yp/wOIDuOJ5EkpS04hpocRRweL8k0u6RNyKo/YJrRig5X553MkSuZ
CS3vj4+c+4kflpZKFK1dJa6bcE6ibsY/RW5POcZqi641xx/w8ARZhcUiTAxUKA5F6zUA3krKkm/l
0S+70tWTe74WhDS/RQYWU/a4+TKtGsiSwrL9YZ/9f5H9tDM4h8UTn0NRoR4xHJOIyLyX7ctRAKLd
YNmDKB6ymMXv+08SEqa0qoFSil1G3OFDdb8UdxDXDK508BzAmMSsN0G+P9RyJtz3hUr5E+tSPcf0
VbfafFBab5Gul4X7WsUZ9HyThj3DoHuKVRG02Ozm0pywQdtEa0Ek/5MF6tDFG2UcLPaoPAu+ZNTJ
ueEIG3QhN6Hg4NaVSYBqRbFwKnnrXfarIu2h7tkbJ3nd7vqAWToA0FFrkFS5WHiyRAsWwRvsfe7y
2jqr8iQSWJfgEP6NcbELlA6zIEP4D1KDQT39DoheEPvRSVm9mDGN8EWENlRTBn6jAIxE3DzUWFea
55ETpyPEu8xQrtUNvdE2wGEi+COm09MnyZ2fUYltWVBilw50T/EIzMuiqA6e075Rj36Z8PzhYsLJ
MkBJJFLICF6TUcY6+nbUeiBLg65MWkKsBGvedRt5Uhu5uXPJ7zyTwB2R//63cIBfV7BhdX265d5q
l87NUOex9N++gf8+7ARR2cgGdBE7zMCrydZBFyOWAnlsJJAalWf6tOaObxm06yU/OUW4TYNd7nfE
AWiphWH2VDo6jKUhZ1hE2iBCyUMHmpflF0uSaYk0j8BT0PADaPeiMg2LavrDrUVb5ffGCl/tkUS2
sTJbNipjAUJW0MUWl5AUloVe7/W5pRCJWNLGzaILpr7ex/Lvmxdne1L2TQtf6MW8+Zqn5ElLHyVd
Dvtv70BPlSePEXX4lPQdncZ+w29hmPDoQui/F4Vgf5KYBWX4v7TCHWLZ9dklsTZSvLc+jdA3iChy
/ezWy0gSZThaoJnsFyf/b6cK+NSJiPicON07v808nN14AdJgymrJW4ePNXiP/F4Elss/pTaUhZ2+
8V4uQp2XubAOVjgaTv+OdpFpAS9UEZTgI6YkZDFpW9wmiPR2J/UgbjlSFW9PxAE0SSbF4F19Q1gC
0dUK1ynB0qvDMQht2meGZRjYOwY29bkDo1KKu0GOCufmr+BNKtmvyXypN6H5joIqKRziRRLzJ4cr
wv//WujRkLKEpLLSsu8wLkXW0TJ2TO8noz6rpzFxQarP3bHHgH0FkMuj0i+CPWpIK6jvYd4iXJz8
1fJ+MHUPZkrLVQh9TfqA2OshDJrO9t8nbyBjC1Sr6GI2Dv0S8AjhgWeLKsgKYUfRPt5ffDXLd6qs
Lm0NB3JoYASngIfzPhKrVwVjAYyLUv+HfBXNNoVF0r83jwIK04uNkJ89B0KdNxLsDZuGfiHG9zIt
L2ouHIhdI7ZVg0y1t1rf0h3USyglgL3wwDZ/n1aq4bKItNgI6/yhJTjAcpbFbZOe+mNqoGzMZ5Hp
xh+nQYIWDjL5MVOf66SKinCw+0k4TYxdpV95/ohy8RatStLY+1Yj6rsm5sH29E18e3XpM1T9ntJe
MDr1kC+ujzFk1P8ILI/bfGrnfGq//lawmLJnpdeW99JZhj9622GfZ0jorTGP94YDu/fFFjFKfVgk
+XhOmgoA50CowbbEzeNS6DRMquTU8fz7sCEhatoIzbiAYuCBUw0xSzqO2LW/HKs5PzYkuqV45MaI
DyO4nXUBIyUU+BKo03XVfMirYkPvVY9SMJNL4r9yVHlwozI4T6L+D1hMNe3GU0yfE6l4igHYSZjL
OqygtcDsf+GhLg1H7qo36R4Z+PDyVqj+qnXiUp5WHt/+W/uzTCbCINrK6FsGM+09HU2Ma44yC8rj
WwDmRZYusm/i6GlNXueVXSDHngb5q01mbWIirKcPV9GzqQOEUXz6YuFP+WG5dINC1wxY+3T2IJRm
p8Z31XGQVKuoqMKAyYSEsGYzkzNOkcnNctu5c3O2XwVjQpW8gbxxBpNQW1fW538H8zpfCJiFv1H/
d8w5Wlv2uYOmDFoNW/5AInxvQ+LPZCmP85ifHj/Vn7IM1bhIkMiKXbHKWuYTxK1R/ACTvUCi4j/i
ndILj9y1x6M6/4jVw5IVuNxnMXBPeszmxL4ti7qtXEIONm34im4lXCLbfI0GWaRC1INg5g0lolK3
DZ9KsLqyQeVv5/mMaUw/H/iiJjqBVmtW96CujYUqeHeB2//1etmrRuWoQa87sjaOQb2jcMHdtWvC
juNKyoUEtdQUhwIihaTO7BpLlUL2LQ4ZIbi899rSbKS8f0edAanMR0SEX65kYNrWIdRzfqRfg69J
vTKxoEYQhSO4PEsJao9YFg4iAgkb7J71/MtxdSty0sj32gvTkmyO2n7oFj0Va8jcDZxgolqALpBn
a2kf4CK/pavEKGp8spCuPbMCXqRlf2iu+bKOl+pyEC+B0F6zc7hpyXsy7eFZFnLL2LFFw4ZLz51N
HyQZT0LxNVGk6/WKIfxn7KFYdM28WJz3DNrEmJ2vjoREHPMZL/gt7XNCHuSo59QuVrzfp46drAfI
SOKPRVUdsf5SjcoW6jy0CSn7Jd2r6orWeX0yR1B+E0Ez4R5uhBMwXo408gwFfbP4gFBdLyXRHSSj
NbD96wdkzLLZf3aLZVOFaHNGesTqaPNNwalgkcXWHIKpVDmAXBBGmPZE1p0jZ94nuvmvzMsGtD8s
hL8RKuSY0q2kEN3qcmwME9I+93XC0IDXm4Xv1mHQV0ePZJqQrJ0rVaSZPZMf2hpkvwDhtLDqgS9z
58Z2HzZYVWjgugDPSTSfAea6/+o7soMXq+/bd5v56PNBxBlzPQoNAyl+c/ChxIc6iw/JYikvEDJ2
XVQcOL6IvzmhFQPI88he9BQQMIp+kxLXXknihJB7SZYRFZjg/U/du5YVT+ozoCvvtQUhW8+fCdRQ
nd10gchM3gvdo+Yi9/6RCduhx+Pn1e4OX9mjUybsQ7PO5rnnqvKVlWvqRbazs0LqjmMlUvTXe43D
kS37JjIlhn4WFO4WGKuF7cPW39XEFuMqAM4RW7ROBam66qr4NsfMoNKCZYI3o026LQ2KY9GmJlRC
HGToJY0kW5iHK0o5FVMUCeWlB+XyrLXk8OSMFnb/cF/5OOczy5IGT/kAw58e4Y2DUittdL9kkLu/
cdUr0G2S4sYmN2lZdYUX8xw1uN9kWw/OjxqU/OsnUF5W4LMChv3gseb5vMnx/O7W7BFZ5+LLPwpm
+fTgFUGmSUbZxk+1sv+qeOPYNCdeNc8ot3+BcTqdtS0zTxlQ1tTmTKuZSS9JB/xGLEsLxZl+PiYt
+PWLXLBv/pbXDf4Icgnq0MmAS2jXpiBxPs6ioQsoRcOjZxalaZnYV6b1s/gSLBjjIpD7P20uWgx6
O0J1dNtQ/4xer4aDre5PkoS6mALYR/Yk/Ri9yTyF8UHfBQMcTDqQ2Em6los1XT4ZkXqAFITMXFCx
UQPErKHHFlhGLZZigNlCL4Q+duLZuURGrEt+2l6WuP0bP8/fv+TPO9mWh+GeZwK3sgHlFdptNCN9
xirM4xurA7m/Z8OuOsP+siVC6dyWvWRkplnIfXxlieADJf7T8JJkebEtCk1H5GaaeqHekh0ppVRO
mHvtuvmmH/pg8xILZo2yDtR4N9x7A7s1TNi6ZY6aCw7WWLXnDt/YSDlmd6JmQKqUs/VbLVWxk36c
fQmvCOnaFq47L3SIDNMv3VAqHX8tNZTETclxwJ7GPwJU5Rq1O6IuMVvWOI6YNsdNrrF0ArLPlI41
Ba+qn/u2Ukv3pv6dRNZOa8+FSb+2aIvjgkPvoYw3N8tYmPXwChiQWziA4Y4S1pf1l0fRxZoOIFpx
NENXwmB8uCzKo/fnJU9N86G1ETRkBiJK7B/1zuyNJxxydh5e9uK850GEpgtHMuhjQSaTUJ208J/e
4CuUubMhNr2NGjZBtE08Amt8lpYNn2UsZlButoO3Ou1mG85JMa+ei8wY8qPmzQRpmxup683qTXjk
+RHqApztgPyi8Gz5qorf2SXDaaQpSZvd1Z7rBBDGpdtHiNIzpO5x6rFfRcGCwQSRxVGhFwOJMKBj
cQReMMTM0LOE6rEYfW6jdTJjU4si7edrHq9nfHl2wiT5JI0v9vfTplbTpnNcQRu312vWZAEZMMJe
7fSgQmTG0MINZmAUTYqB/+ccvAOJFLajLuv0TWlzLmCShjJQN8eiN14ULmA9yXdL4xfAQ03Uuzmo
4uYZ+2HsprmNhPJGBt0QcIi/4uAcXJnX9owBzdy9PKjPJje1CADFH2Hh1QT74fDC61PH1THMJ/nD
0B1lNA0drEInxLOu3AFNgMowS5gDAs+G7CU0KrbHyhcgga0VuTiUIcz3Ma5/Bk6gMTmVt1k8AYl7
tgKX9g9tHruKDNN4p7vhvY0yXRo8eqIwLi55bsTOoFv03N5vF41Ol1zum7dM8MkcmolZzylNvDb5
l53iGwQkT/znopC2YUTJ0gWv7P7f4dQFFpq8BqiQ0SRrIKE8SDQI1ZoMEuNWykbJBpxi2xvJ6C0O
2iFbJtg0f8KB8Oorr1Kd6xFVO7GjgSWs2Ee2m8L8P4fsTOm9BcXglrN0kdQ+qKvBz1u6iFIlpQIw
CeBYAjGJcVICJ9QbNPJmqvTfICctbruUT5H5aTOs3cKFEQsB5f5KQ8HViyJHXIzQVd3H0Jf2T8nh
AU3vcPs12mV/vOmFIyX7BOGhb3W3iKOHG7E5RdHtI/IrNh4hX/oQ3Vje4aALVD4xbOceVr5/tAjQ
qUVq/TKfTVPZ2436MJDFar1Ja2+xAsHVSvP+zDoODdWMU/VC3fkVIkKk/rRsBdOb1onMA2TF4ACo
Q5hNQ5WSmFY9QTCtsP6neocbb60ogEt7NND4vB/TSWGA+f/EHaZUNBC+x+Sm/8hP2h+Uwi6OwkjD
w/weT9GsdLdsGgpMrZjqtv123XtYou5YFq8K6pNWHRJp2+2SjljKzuQkABs6TA3PxyyE1aj6uL6K
lYzx4PwsX0vXASHJN/rEMeANW/xqyob2P5reY6AhkQ0GdcUOR+PoAbDSvrS5jd2c3id3/UgIP9AD
pcVSuDohU9uQtqQdzCPZPgOoJZGTof4j9kTH9glhQUjVNaAmV4zkOhipHCgp8YsZQpzS+hbuNHnX
e15a607XQiL+tkp1/Uqg5Z22BxGu7S9PqbitdXjsVNrTjbVaq58/RhcmwHjjaf3/9EHxZyWUIiNB
3KVFtBMAkQic2evyMzJ5v9LdwwzwPuskKDnrGlcvs/CwK70eUAQJRO20dVMG792O+P6N77OiMIS4
5xQCnVc/WAHZ86JqfAYXXIWkPJ2izs0tazqpE2frOh3ES7sz/WkFGNVRB2sCWX2OCicQQi3JUWv3
wE5mMxtQ1NYg6isGMbp/MyPrC7dV8ZYtsRDL3sq7dRLIX2B4IL52SYugybnl84tusmc2nJ3kw4+u
KTagPOXa5wbygEiSDAYTeeelFK2lfi4bU/w+/gRNtRhbcDMMUd7oDusS42IdDmHdoUhwiZECmqZQ
7iNVuv6iEV12sulv3X86dSkLlr28Buftjay/nZM4brGkrPSUyW1Yq+NJfKEPYuzoyagAs6/enohk
6+UMpCQpOow3G1xmxLwiofMilddQ3t5aheTX0y5bU0a4N8h33yw6ZVmuERxOsYEHL4dprnIRM4t+
K6K3JGeZdmaFcpL6vtijQ4vE4d04Z7dtUvBI7ad5IEVGwreykL+kpLN85Jp1Ti0lLSZ2P/BsqMtL
w0rM5CjfztMtsQcA3z03So99/g/eegHZMnOmnuuK5IBYR74dpqQGQnIKnoLn/bi34oQ/Jo2pMaii
Fb9wBVp7tMzRKdM9JKoJBk9P6CQDksRY9xG5Soij/tTaoYABmWjXM2K89HRLcOzeFnfHx2CU9flK
hmr7I00YwrbgRXHBXvdmrTPzYd6nxLcZ8vm8oAdpEofCFwoBXeiKsIrT3jDnzAFOAuLoieouEdSV
9lHpyngRXjrTlmVcpG0HIxw2ooTtis44qbcZi2lVOdmZ1M3HEtPvb2Rcrt5jSJhu/n/Xv3dDRn4x
h0NCokfHfjKJ2a/8AQ9DJGHp2jdrbYWM0WIjzRxyf9W8+zB/2K7fYiyMq9Mknmjet64Vw5x1mKV2
yMFrR73twbfDhBtww6qiryho5FvckY5xol5dCVDM1EiRjcVOrZC6HNKZTlk5xEVTWtn+Lsmw6ibK
ZCu7W8tByWpD2bbuFCq0Ygrm8MAYmHFeNR4gShYHlE+JkMkk2e5KqzjVDJxiAVHlrKUBNsDUTokR
lbK9a3roLJxYZEE+GrBPIJ/TbgyUiOpUO+GB0HiGAGg8ZgA7jH5r6JHOwtWR4JDqZc3NzNTu3ZxK
9i5aEG0ex6OtY9I7n20lzu4Xwtl+CFLSf56Hicgi3KSBSacDxxvf+m3qYFMVMDSjVsys3zcF4ukj
A03v3qxYzqyKGoeZInUchmERED/HhC1hDBBziSrealQluddyF+KHTgXX4vKsQmE1vLC5NHorHRxB
j18uWmbmqUv+27zUCwFZyU0vngjXJv/FX2IIgt9m0F4Z5o4JTkyOmI9Wm1zr/QLkTYpM5xYNE0g6
vNwibIgdcuNtmPLdG9gf+Tzao19jo2kguLeSch/ZsrWOtPwYH5ALwWfrHXuxbgA/UqjPFKQsfwSx
FgeAZXoK4dPCNm26FaFLgJEpBR2UZ2MGVsBzs3l1IZUAcS4lSArmteWtUjHoM5/d02bcQSw7bTga
45gCMWQ977Gtp8DJcptbB+rwkSyPocQGChkgx5xZpGO09v/DxOKLgBpI0c/phQLhAi4o1e0UyNUh
JQTcwNohAK84MjcyhdiOWcejptxgl2Otg3QgMmHQlUh4UaJDAGHZR2Fo7ez5NJL+2vWlzA33s2iF
9lQBIdCseTaSCWPOBD3rAjIovM6GB25X0utL8xLZoOx3FV+deu3rV2FWqPYvA6z9ZHvoFsyL5qF0
DKiMzk5if5lNbWHUfiDK8AfN8OPK7GkU0YYAwxDwlOjCjJ3pbNMpORnnDy3oz1wqlx3ZAoiTY2zC
1HwjnDv5h1f7cWymP3BfS8tmmP6ffb6Wxo/VPqLcwHvZStMrPwrVIhb/VJ/jXBHO2CM/5WUC70P1
hEI5gTf4xZ3Et3eGFR+WaoBrQiXDe2SYGuqoOZO/d2ue0S4vEyigSQJX2vRGY5AKbN8xEiGGqxR/
6p8N8/S7vXkrH6YDYHcay9xzZA6FPzy1b0QAMbIqjk3Tg1HIhhnZS2Tm0M7dV1lbWbNuO8lP4VLk
1Htzgrq447p007JNLjb2+XYQ5TMdamJkioBLGvaQVi8XWfyTrHKqWeevRLVqLVFQSrDWMBD9AUJy
KvBlGl6rtsd9+rGL65853dw6GXnkptTMOXf2Xrr+KF/+kOAvkQaDWkx/ZtqIzubzSj8p17fD/LI3
1/a8kEandcU5HDTfS6QWtoAuc2AAkDv7dHOY83FYYU0aW2rLxzzTQUk80Fp15iqhlBpaGfeVr1u7
MUHwHYejVpQk2noRAG8oWay5H4NIvYeVlIJN5g0nY3rWb1w/W3r0VlpWtmer3IZezL7MxoWuOIU+
6eZTUyLf1bWkPa8JjFqt9/e32uX5LvpfT2A3UMionXlFnHN2eCcIZfqTNAmQ4I5e+XGFPfUd/Ss/
wtlSq0VUBPTgF9+Fu+4EZXaztpWj+NhXLVhVk3xIqxxvXrA3/qWE9Kf2OaCXmF4IpKIhNoTQ97tY
bViiuLVwuDSfdYc6bQM9/f8CV13WDLOOF9T0iXtIJglqDIbY+wNx8Y7wD9LFX/1EK3s0veDaNb4B
KiBSKLJPUnU6wJbXhaxpDarrQrBFnNDMvr7MaQ49c5pa1ggKHo54ecAlG5bee2C321pQ7pKAwiIy
zKZ23U1MjEb+WpUFYY6NOBnaoBr092ZkJB8YipBwUrOSDyURHvBYWf4sLG1k23Q0FWclinXRhMy2
lsF7nl1raNhh6QbzA5FWKpXMzJLcUDAqJEAnCH/X2BT9tXbRZErLsHRmwxDr10hKz28l8iK2QIET
81SaCpRjynkDdq66pcBzDNVxpfavM+FzJdPIpBU8NwfXUQJ95wyxninMs3Rb1plT+ddvUuVJ8O58
IFylf8CZxgRTBIIapmdV5jcdrt+iCTUSz0DQC+1ODFEPF/7J3lx08Kcr0Va9H5j6dl1rQk4luaIO
vkyICRQyLMLny1qEMXtm+pJze7ozQMwEKyoIW20Ah8McOWw4++nimzwLjDETM2sRrlWykvl44qge
dny1/bRiaTIaursdx7nCEUTnRefhT/DdMmfgwt1iFeTaCJyPmYKKHeEmWJiOcEY1leprrpqoLpZU
2XenSpDMD8zppLKqAZB9k6YXtQv+nONCauaYowvot/27PUAgDXb18nvAm7j7L+1xQo804Zb/ffh/
LtWusgMmF8P+eoyzikVJixCvS9C4H73x6dTBzfFDTWSyvYGdjDbUXxlvztadWJl5E2uVj6oFB6Ox
TNAwyuvlQD5lyObYOKnF+CY56KFzvX9QvV+4UoXzZU+XJ4rXQ5+1F2KyQiUkFUJVTSITS9M5SX13
h5kAUoKOMHIuNmGyK25VWVm7eHf6ikf9o8YMJuRdYSa0hv9OYMlr8DyWF2nlMkprSvdN8wmBYGNa
tNwhHQbXDDK9q4DkUNOALpnu9USjPfMI92qNWcj/MYajbhceHnmxwGt6ZMHKH6gso4ptc3ME9BIq
tayWmo/AgOxXeJqWYl9J23Va8EOCYUkYTLA4DQ1kjWye6BloPdgIv/hv7HKHbxNVEaXr1EuWzS3x
kuDcaw7+QR9b8Qi6pXDkiXmz9+UxMJ+ZELJQikAkHeAlIWCy3fGfBhLtt4l+ZC/hZjIPrSumy7Yd
qqjKWtJTzjxxzPhPhIEnPUp8Xtin0ADSo33WTRgVJLbklTiJZldeogmpW4Mi0C7gniejzHjArgpd
uJDqXGYAr2ksh4ZB0JJeUPiPMb3rvCPJwUJgOCeMrwJnYvSOiFPk2vJEBwcWtXcyeibjuz4slPkx
btNUNYe67jZxX4kVRsYh/gou/ohQaUjqSQWtoVDJ1BE8vqWEKCmwsTZj7y2jfj2/0CtUoysPbulS
T9I2vMN/RWqYkT8tp5QLCf0b4E+4uR5bntXbX/0EI5AzwTogo9ugtl8eT3RekTldZprXw3kP8nGt
ziwss0Vjzpz9vl6bcPZNo9Qshc3rCs898NvSWyxbeXIwyLg143WI5nERvT7JGv3IVuJn9Cf2R+fZ
8pQjA9hLhygVkWLQf3xc+ThPyQn9ZxcVG8BS8Jb5qnFHnoQtq2i3V+HkAgNWek9D22JDKHFf9ZBt
4by8pOsVvD5nRefnvGBQl67sxjQI1YecJ3gwB9cHezYa59X8FRcsltUbO1KiTYGvMqFsbzS5bwCq
SQg3vKte0+oE9IzwdIVlhnRSLOmAz9uB1wyacrSNm7wS55qvpaL8tWynNinaLcYf41pXKhGHviPg
3JDmp6WqEed6FR4PdVycyTQcBWjWY6JAsOQMAOttrLlj+ZrKEUxX/eaq7I90PMcUkbdYwGzoKiLR
YdkAvzlKtzzuxxajY/KE0NatvNyQQRNerJ0rBm33Qj893nKVgrUouXJk99MYGicl07dcpl4NcQmD
Ko7ZKC4igXA1jXNL23E0bOWZPjCAGnasIFMs/RX2wOM2CH/dXmC2jfn8BWNUXjqCwpF6ooWt4yFV
t3aJjar5VnzqbuLcikJWCuTTdQjwPbB/cx1dFtZLRzMXZtoyQ8oVthd6hW16SArtSI2T3yssQ0G3
y0fzNTgPxzgenGokysb2liUSMI5avdi+AV2JWc8Nt3GoH8fTv3QrQ4u3PfUVuUvS7QFd5RWadVLi
vSTmI87l9TFf6u/51lOLSFBFIM96ST94nC25k8LBACMVkeVYN8ZzEyWEgLBJqlRZcr7A2qX8lqxa
YJQMxPIEWb1ompoy1tOVNOSnWnIUc2uz/sVdXDWUL6P2ViG9tx4pQYrIc1qK2G1b+xosm7JQNqzS
rAIwIVBb322RkZF3pKHpR0ltutnap9AZOYBr9bX6b5uAJ96qsZMsjScqHiFPdYELQ6qVNwH0Dywf
djw+0VYdKrUAPyqfNw/h+R1viXrxoloTZCEVxpuMmjZLZl5ZD6+nVzNqNee3bYzxctuFc8n4MZtF
2QrNLTjjnK7Wz0HH8utcDqKGRanGuP7B3DJuFamA9Ub2vTyWwFniEmzxvJu9YjBxvQoCaZmt4NSe
gi7g3qpo22Gd18zMmgUBfJYZpJ40XKarJIBuJsa5tnrRb7hUNj5EDA6b4gsz5VsXKQwFfVF8TmRh
OrNnvE34eBKMyWMHU+NbRmArQDhj1JIeYRnFB9OEPdtmNkyyK8eXsb+/CYnaLaafz6+JaKyBjqav
TtdW9ttMNUaoGZ3fXqKAhVfSiReqybIoj2cU8FfFVWiZze3Ss1Z6PFgjrs4WiiMm/vY4nEmqLzIN
IoORil3Ctuy2m0RSOAjM+0dNBIrDOJCNGZWhAS9jGMM0BfdUi8TvGdq0GM0de5FVDWlWslT9gNNF
oqPA4bI2AeGgvjemoGNYe7dscwD6FoS02PD0O0FGckUZ1x/vxvzHPJpO+dLbupXRe6i5kLmM4cFb
k+B9VV8VF8j0Ql6B2IRdqmTCYcVOnVgtlyaLEKawka+1RkmL8Gmb3bEODOv3+pgxk6qd339tH/A4
MYAiXmhcCYHFtw7EwuEmGvnmIHKn/JrEHFgEkqEFlhT/Ow+nMKdcNS4f8fWC/nm+lAs5KAT4r07r
m/CnyuTrsEK3qr4JjY+haZ0cHYaZgI4gEzLDqjqBvNUYRM/mqktkZ6vS99gRlH3RlrmQnVUx9wL3
faHob7Y5YYuca9HmMkQMcYJQ92b5vJL/8WlDy+WMhCpQTitEuGEqsnRd0p/L+hZVMxgL5LnCgsaI
st/RjOy+L/ChSkdW8TVCPCERVCOjaMqgqDlHIOVGbk6HP89bmbf9QPLbJXxfY8T3tFlctai1HYbf
iVXRIQ0trnTmu+wImHZNMwXMCpHWOzdJHZX1ocfwQypTmouLQmS11vNYJqLDPYVF6zil4GLSWFW5
IAW047hcS/vSLaiDHpFlcIvjhzffCznU09oQq7Nyw3D9ZykIVHswktQYnn9aqH1APUWoQsZ+e9tN
CidtyyrfZf5f3ULDCM7pOPrT6FMXXpGGzejy+99qKChorU4sOYRmYMr8ADTOwORvzKuyqk2PS8qY
tM7kvmOlyhgR5eSTrUt0Wu1K4s8QN3TVT3OKmSu3rMWhAm++KS3YbjQ3eZYton7caTkCkIakxzV7
W9sct7Mr0221GN4f9izrxIMtqt2ELueDULrGQ4zAN6czUZyeKPEK9nb/0GOo4coQA6Sgc9J/YO9X
LIal2Wz0+kdhsfZ7PZne2oMXtYF5il7NlmU8GmzMbAw2TRyGEmkD4//6/HI3eEOWiuFjRX4HTgsI
NqcR/ItY8nQ0DgwxOMZ9+kRWUj4U+IRmf13wX7ivqGIdoIlnZ09e0JF0dRm78aWHKDl+dmgEF61r
eTy5f+vv7NmJEaSM1MiMnCFh6mvYohIq5rWisnGEHDa6yXmhrd55kdW/sgwgkD2O/7XeCiNNyRoC
U6dh2mxvWJgnsSmMDL+91dkNxwAsZOx5kVx3D0aZ1EzwMCbb4rbFEoWGF7bLbEslaZ+2jjBedq6v
b7zB8SX9ZG047UNU8QZ8tv8iAsb36S8wDTiIgsMxc349vj7CeJnlSEq0sno0NI2+wyQQi0Ujz+zG
doY80pc8K2RXl/chf/w792aNH9D2XgNTOVUCyJVADuWln0dbkTBn1ism8p21i1GEy4R1ffmEK4G2
M+B47iJ6XltZt/XbvmuAT9CDam2mbK7O7Iv/Gdwz5ZQhmHo9dgASmRjmbIBUx+YmlG1KhHzMVzJ4
1/jL/QfeIfl1mqNr1MmhH/ssqHQrbkWdKYb2jWvFJoXEZTKwnmEcB405lc8LQ9TMTOhfgQugEJmB
cnsroYc6/hTDBIgAmcCADm6FzXadQ8W5BO2W7uaehjsmldyL2WWeF62Nh6zYACyO4a9EIqHn9t9z
EUeyNk5eAGgiBE47ls38XozKXevU2ZULR+7cqd+Rn0kwPblYemkVNC22Hw8vTjk3nNGv8a7smGF4
0InVJ48XOtSvgXmb5NyX+lHRQNbSKinNdC+SyE3eBR85G3s6aZdn24amaROK5BpqR/VbjIac6cg3
g2fEjjN/mlhiCnpRpfgvzWRsMv2Nply3h5Emb3RVC1WMkC7C6lP1pNsxJtSmK7T560H7gF7EaGK9
vVu6szl7apw02Tnihh/hiWTJmoKDmk9PsqKn7TuAbX7WC5Z7HlJN1f84VtXYij1CvUbPDG2Ctm5X
D1TbKinCOAuNBQawfjLX1jFnGAopZnhzmu0ikYxJgTNXNK2zVz8JHF6isXzLHVFNjVRRQIMZ4Atk
laP/FGa1+b597l6IT5kt96pqDFIRRqbanHF9JUpbWsLsUMp3IyHfh894PXpRgzbaJZ8nN0Rpa2Fq
Nmvxl+YtBJKcdx7fsLvYV4arNswqSmwzJgqqXvhIi9i9q11CE1uX3xLHy/eVNhUC5nBMn5BZJOEg
wcLlS7Tqy5Pmuuj0Aa6ba/iQBzoqaZghY/mKIjDmPppXyQAELKgVsewgaVFnsv4YSXbgfS4X/9h6
6j7U0oQljHFOh6gloZhcgFLjtVl/RDI4eQcmnrUhD3oGVKPGxkRnN+/t/3l+4io+6pz7X8q0s1AQ
LgU+30WchtjsfihslaC8rxMIo1nWwXPP4CkKEUPOgJ+BmLyZdg0Jg/Wy1FWM9hi3HWV+Nelwy5vO
tw7dWz7m/3cTTOSevy5v+NxCrJHnF0mml7SEtT+y28TX7K+SZx+Lh7qplDCl+tBZoM72EYusM5CL
nHTdXKbE1scaKF9CmmN2VZPB1FvdSxwJqED+bkj9FlrOVuA/2x0gRYWOyFtfoUHEWtOJmKjrPqlK
To458vD3n1a/kfOj0UwM94XXVyKH5WhFIuT+8ym9z7IJP97w3uqwbu6p8EhOpZevCk5JECrqONWa
fEOns/x2WaH072wp915CAoYhB2RTVOmWe3/lcWEc4hplVP58ABax7yPMMXi/B5XHGqEDYqTemNuA
TbgZrJBHWvzwSGTqc/KxGDa8qc7qxnRseS+47Twl7Ti/IfGNDQEBBA/fzALdWhLNdLAc78UeZCIT
mBjGrItVioZ7GlbFMK/TS2INl2b1pF8wAzfk8iVobuFhzKeorbY2b/VKhFMq3R5elAvuWcc7oyIh
F2uC4IwGVP52x/YFOAU02QrceI9bdwddW76QSTT57M02cUHphKtZgZxnjx85FZdjKRWCrgHUAGWI
lP7nfxt9cDQ8yYhja+djlblmAzcsP+wLdQlqf1uzrOoW1AoQFn3JXoj12H1oizUnSB6NyrFiUNrz
+dGP+kXehFHJ/mYBlKb8SWX5LK5LhpGWD8eIBkS6Pr7m7bbdB5uzpYLp5a5zJ/DXPL+VACtMUZfe
EBg7IWLuvVlC88TN0AnwRppA/Oj78hMYWkenhlTSi8bQy4GCk8uUQayT9+Q9hfbOJ55Z0Xt7A3TZ
klx43DY/BUc2Z7H7D8T7Q4p3DMPbspNE39es21M8OmG9H9EK14gmcKEktdgb6QZSwSM5XfhkxY+v
b8S5WJjkxYV33VhabEzSs6Q7aw0HQv8Yryqh4ZpiF4Jqz/se/RS7NHyMDJwFqifA5ip+qDec22se
iUWc+d+t5ZcaAw/glw/TwQXRRs4ghfKYO4TeEfmPMBOaIMkj1t6PEtlFEt8URqzyZEPSm8C1lkAq
TyI8hZ/7znt8WDd5qerIk7hOWnHKP+JzWl+K0+hY2QFCcjL0nC40McqKQj1Ntr8maxBcFqupNAh2
ibFrz77z+smOrBJgh9lDUgURLRGexPAQvqsKoBP8/dmTBUPHmxI15kFI45WMZm10kYsqJ8YIRV2y
WTcYigHI3PG8zkVW1lCq/eyDXpbU9rxI9guWOTTdvzLV9TZcZOiynM3GbOgjQHzkwXmPxJdJyi06
XCuR3nzQUeXR7bRcDhTEjlJgJX/E00Ckm7UgOrVuLqO5tXHb6lt0kHKZTwtPlBS3JJzSbYmofAqF
sA/GZbieifItfCTd5C/VYIa5Gh1PjeEnBus/26XLnIVVmmF32YICf6Lc2PcagtcoHvcEjWg8+GnF
8RbRCuoZlGdBQQAM3EwsQXQoPOYK5A/ScwkloVpJWBRBkiXdckW+CXl1cAtCOJb9d4tdZjF+HVRm
/fZMvph/P8yjDCaC5/gtqkMyI8PZ8hKA6IBsFw9tckjOQZAcu/R2Ibac/WEsN1vK47gXFM6vM6Lq
rnbcXkS8Fmv2OdNtPaaLE2ES/RcDolLIANeSamaFFUUsIM9yQK9tGKiO/fIi7WwAezVdUt4QWtbs
32F3SnisjNSWaUU857YnyaAsjRgkXcVByqHjpuPhkcaXtKmbCS789Is/6TxqTFQwgz0YED62igwV
sOuC7u9/Sg49Zhavzk7sRI7mPskb/T8f+SALj98PTpcOG1wX1yCJFcl0PnDK+nvUpxPkO0WaWHil
JQrR+GEh3M1EdNbl4UTaT32op/TFRi+0j43TXV+uBDIKRMcnq+6S+Ri5nQD/jYm/NJinkegm5Y6N
gGCsszdpW58Bef8yDBWVkcRU3dQIwnsUE4p7yKSIDv98bg2hdOTBXuKCE0eNTOK72n5Awgn+NLWj
Blyl16UCcf+HdG3ySq4j0Jf2ME68tk/2kPBwDPAjM+Kcniu/ugRO9FQi3bY5wmfyHLFCg/vez7rZ
jQl/Rg4HA4wL/kHrMTBEHIhKpfjXjM5UPlHHoPk2DGZKjk9nyT9+9DqXD5UT8EjKwX4v/Naf/8VY
DdgCLX5wM26zaf/xAURk/GFrX501pbl+JMssfarTf7VexiamHEJ7n73oxDbaqd3o3fFQxNeVFnX0
r3QtbKTuceCrW9t/D5d2pVbmzEeyHnbmdhh0RQQOQvRndfOR0wJII28fDio7Jx251jz1WkGyQri5
1CsOFeabRJuwGw68LyjVjhGGABTKw8Y2d2Gitkw/fxqmPQRVp3yiUI3ynYmSbBLvUSXrAxNqGDiW
LdU/cNDc7aG1OlJvIy38xDlbszAhHs/RpL/Z+zq/dKodqsAu+dYLB/wsa52IaQ1nrcILpmI7+Xtm
VrhUsQpU/LYiduQe2N5gfsPoGLY142Lola/n+TshAtyTHd8S1Xeitpy5zRFTfUSu1BJKtT6jHyuf
dSxVJhvTmdCUPomuimce4ByzMRSzWWqRJvP2pH1O76zOa3iUbXZSCmvvbNev2cOy/hbm8D5qo61/
EghHFmBJIkzHDuR+kjDFzlBwTpSlm2iM8v3xC5NXbngE8EqtFOSONK1Hf8q8rhUQuznMUJ4vAJiy
VFmcVgIp/lbYA3PGXjTjNnuvaDP9nLfI7cUv5oqz3yJ0NH2VkXqEsSay6DL9JBoqt4SSqDJEe/eZ
dCWrps30eGVsHnwQcTsS7KoXyHmlmsu6gfk5VvTrDdvacX8EM9/xalqxSCy9Quk8/f80JMV26Zvt
DFa+leSAjN75mkHdu5Pesr73mxt7v65r6onGjFTtkx6D5xPdUviCfWNXB8HX73uqu1zACdrNOyuk
zCDwJKusHTLhYxHexnWeSvUxSO7Fa4UAR0JDPcOFfjPZ6Nl2JupRuifcrm80or6azevJ9vhSY89S
Ho+WHRrfHL6XTZ2FHm1RikJetgVytGYgXc1MAXXyaM6UKobgoi/6Oss4sNr3q0GfzU7up2Sns9iI
GxI4vO7undajzqX/mSSQVlqTREzQ3LzNDBb5MvjnazN2DILP46iXJ2gBBj1xDykuCSkz+8Vk+Xtr
0wfIGie8TwHAKp9+S6l0GVKXllmJ7vC7rFks8k1lTF6r425bucfqIBnaZVVx37PMtqTXq54P0Qoz
VdkMW5dFNdRJZltbC10V5Ae49Q/h4gfJrlh6AqnakZJjCgjPWN33//GYkg90y52QBipBugV1ncRO
U5pkWM6cTjfCv4sv3l+8vUE7tOOZc7YOW7mqUyAidxkGeP1BdefSxzqq+JUdpY4bpDYluEfmWmG3
L9zf97juyRy2ajet7deFJ+dYgnAhpFek1WOMiYY14w9z4lWOSrFZzY8mt+mprogE+c9m7kxycrir
+lqVMJklQg9Bxtn/Gmj2o/NIRkWL42i0DTtzpD2/teiuWU5sYGBl8248zm4ZK3EBsc5uDPkPafx5
nUIJ2na7ORLIeATP5l943fJ/cLb93YR8zmuj3uCQcPQP67wB/pZe5x1JIwhqM3SsEaeYa+1C4TqN
8+PH37Ek0X+vusDF+djK1yuuV4aYt1BPeN2QpIw2kdFG5HB28Pfcse4HuDEVGB0urx82e9Brk349
rmPSKWA4OqtCjXQrqZZjHJevI1vjOTpEOvt50K0HV36+mbtpgndW0PDHS5nXaR2Ye+TAS+q/OMqp
g9fjDAifbtvNVu92DGt2NMt5onVXqAZ4J/SNrfe4yNY/jXF9+HCouE1qZ4DDa1Ottw2p2zlpj/0d
gHWqoxVB74WCB7KvAVev6fcvrGcvFMizW6C37FNXHmXHiP80xvE2Zv7LLJk3FnLbLwwJHD1I3KO1
qUmFZPlgP6oV8HltMegYTd8lr4E4dW/mhxjkixQwzOnXctCSpfWr69I4OVcm93Bzb4gV+lyPKu2V
XnEehJsiJsPfq/BA74jtHcgLqEDmjA2iC+tig+lR9iv8t9k7FxwyicoCz5Rm709XAjUvsYmzPxFM
wKkdbT4x4+FuZP1I5AwOpZs8i6Utu6hJeGFSBSSHf9Ct+TxsCkF3RKZ2VCekGz+XApLWKr6V2O4O
Xl3l5AFTXfi4QcV32q90wN0aPPUO+j75ETG27ivDhrtw1wPBXx6s9Ls+5dwvLyntI3v0araSD3jY
lFII+aGemeoaObJkMY0P1mGEzkuxfDFtVnlXGTGLSmfgNjH3zXb7KENpeQwpR65Ksy4Ocy6jG1es
3+f62F8rsK9u8KdmA3igysy/QpLDFSK4ZKfyAiGAlJvArsa8O1orS6aspScc7Is48f/FIfTVTg1H
nZQE17E0aWAhoBHWHYaPBqhCzApS8Smwmuqn+wBi1mEzrRMR1XITWoxaZ+2KRzcLRvb258097q41
bnbCAuQGfj1d/YkOjwE2wseLkkHLcUuj5as9irBmn0wKKx1Y7497kfsX15Z8r3VLBEAkUR3cikET
ssfscfLZ7DKO4qmAjgJXqMHYS5RIh2emGda6LnkUhH5Mu9dduVPwan7UAeXHqDVMHga35Zccco8R
Kz12WRViIp5swjn5OpDH9DqONvUr0XiooINRN4x0Uab4srxOisQ9OAwMd4Ir+HjMAOnYaAYOEKTX
H3OzzA4C5Omt9A2DF8BWLzxr6FFuek9vBGv/MdVH5zP7a5xw+/htdhnyZbzMbMsJ6+RJorPhVx3n
Ky/KpymV0HgB7NZ1bw8qtsQDujpZp7ZB/sx2A5NWwItKLiO3LdGFHaf7M1dGuNZF26JCztfxjK/m
1orFF0K66t3AebbtV+aCGCewkLTC3kpdC0CU8wNseegQjjHZGHHS4kT5eBapt4QK0xR0bdwRszR1
r3JFSFdGH12j/hqIQuETkJSXM9Zb+Igr8X549NerPgqxh+n3NLzsKKR6zbMAKuDDofJ8RTS5r23G
neJPsBGPDWLShLA+ri+FK9ZXQjnEHbJu1p21DSehltbsmxCfRsZuh56zVi3Ic9dQk1dwDYUiVQMC
5gmhc+QdlTDFZrSNkEfeiQE0L0gjUkrpqdXbY7fbB0feyVET3zaZAoqP9zJ5ne6wkaWz3cyM6i4i
dQNT1sAxcxI5Qx/AVAIR157DZDlHlWQCs/2YmayiF+sQibBki3p5EdIyY03bpwHa754fM47JwgdG
L+AnvdXWM5i4255WSu19dePns5RIRJQZB09FCY5Bq/CVh7V444wFA1/QA5KcVSeqWIqj/AWBqvyu
Ywn0HPQ4GiF1KJHs0iG33+wpamEAkLIKtS6ff4hOne9QIjIJId5KWefqFcWX0cJew5ZBXBsnSpDb
yIUtp1Vd0FhYRbgBg9gzt2kVLrlgmweFSOLV3FCcqzH7SSbOwnis8HH7iO+KzoP+CcaEF2pvvvRO
CUCTgQ4I2XBoqbarwpYfg0jbPI3tXKPVR+PQO6P/eYXzjF+7WvNnKgySx+9Vfm2YltXxpiC4X++z
1xExwWhjtAxShmmxTSsdweD1CKM2qVItEQLWF6oJFQWGVR1Ol15hamrQShd2D3HZZSJtbcwrdoXK
xFsZg+jyMAlG9wRWW+9Sn2I7nlddvZTvnVxhI2hvcfo4AJWUfnq26/ZPZ58WtunoxTqQ33AcvZ1P
GzDsZ+xMLqiaLWIdsrfS7T5b0liJtTyAmVHjscxz/2WDojsPLv6Hdp6ebb7VAeBqv7u2J07hb4MH
g5Serr0+GtTbM4KTc+R4UMFgxm9dLVlPehHDkvfRzMJ42ExCZsGQGZWElidXS1LgpX6EH4GIJcwe
V9WG9e0IfIw+R2+VQFZTf5YASi4m5B0dMyLolkul7Ylf8O59ADyO1hxup+6rW6d4ctU5cTlf/T0W
4N2UHkXgVq6nNLDr5JuXesw/vcjAPL6z+/cvqasgu1Q8ZHgQasznR4v1cq+YdOColRVLLJKh2Y7N
C1Bf6t6l0eDMOKzmIS8QJ18ybIZifc2et0By8WgQqU0uokhKllgM4CPNqUIuHroURJVxrzLf4dSo
ENXFdoUb4JiT/MlOudp8CmKSlEDxPh+vNsTdvfjAiIYkf+6VI+VxG/Xd5vN4c/76AbyzmPfeQVmC
dFX/uRlTWdiCvV+cmedmUhv8ET5BHRZZHC1nZiKyyoAUP6I4/YWxr7lwL/GsI09x3mQ2BIOCP9EO
HxfE28Z0xin1Bgszejw7IgFxYGdLnxczPe+UsQDC21TmZ9qzo+Qvqg0cu5oN08K9CzDPm/xz2Eag
mRMwHqRhqaQJUCOMD/9RDzxHgOWzw+6btztYI7R4/8vH1ZUIKzAlC9Hn1CGP2lcImi5GgYZU2Hpo
vmOxX2A4DoG9i4Qj9Jxe3GXxCfJUn4tAIPwmFWyPUWM3eywfE5EZBmCNknLkacltOKq1YLOgVFRC
k+sPIzmDwos+8w4RnN7nHXt99ron7OV4uaGOJw8ngE4HnHhrGPUWugSF2VDwa9YqheY9J5cSzYiP
xoJEpKqJW4C5DdjeCfGlYlKxlaaTEGdcfwSid8vkBw33ht7anzgeaP+r85dFvSF2rQhq7LX5nW8P
bNK7jdXcRLEOqIQ+f5laknXCVQUCfhEg2vSKZ0G418b7Kj8G35Lsc9BQJUob3voL6DXSjoHFXJwk
XjscntKQnVq+rPemRTKfnCx9FnucDBieCH4cq1aQ7qwAFJKwhjttK7NDuZcPPe3EqV2tKdlOuZLX
Hk8IWE3GenJNHEF+buKoUZb1SBU4ET83LHWrSaa2//zqhVrAKfeULCAKBblw6AVw3yBHgLqUDiIv
aCPPjs3XvKIwSeBZvTWvRVeNjqeinO45V1XbK853+xRLO6qizLeuweQ32DNgDp2njwiR5ZEyfpds
qjaxAwTxVbgqB92Gx5KdAhgkrJ9SmwHDDTmmrjbKSkpKlrzduT31oLij10gir5EH9diB3gWy9U75
6l7Sp5CTWBBon4cN7P2TZYkl5CW3mYlzqsKcPNKU8wkNVKOxfzsylVl/HMorq5b+of3uFw9kHFAx
GhwfUFujirkZq0BM4Qlizb5MHE5oaUffSJBfk20Z6Srv2zjwWEk68KLPMyRDQeCLGQlbINmj6cNv
5804vSFLgO1dWCis3fQ4Bsa2zUG0gYOD+RyPFXINaKWvxV8VxUxK18iTcLG593c/vorf0KmVdbnO
O2zBlz/oKDOC9RJsRZjzH2tsKbQXRMBr0fR2UW5D+EtHnvB0FFJEQTNCy8vZBxXMGoFHw3dbaIaS
XmoLOrG24YOfXXpyJpU3GflnCX21iviW9DYxV+Jod24RiNr21OBP98Cq1nVOFKhg/xpZLCowxTY8
fw44EM03cSDivzywvMs8h/yEzYnB3FczW6jnM1GVke7tQHjoUq1rVW1W6niaS+eodgxd0jFAPAL2
d8OhQz0doQQY1R9T+VAvZkytINlMsJ2tb8CbqcR5lMuUWzivUABCbwyEXL1mnBi61O4vosomfV50
9L7OIjzm4xlPTsi28OJcNPUW4NPi456BWT+kQ4Fencn7BWGwQHW2mr5Rbsh1ejMwBtPye6PX0RMG
UmAbxjufo4PMaoizwNvaFbmvGfM5nKVNT5FhwuPypoWblKl1Z+C4Av4Oz+IUL1+gMteRCJMTVSbG
kYX0hK8Ww61l6KuTO2tuz2X6wFd1WRdDvGJSkMnHMTWSdGCdMoG/+g7WcV/FuLiSNIrSKiz44H8d
M18+nEi/KvV+UR+yBt+7TE17FuoQv6nG7LTuJygjLWx9k4Ka28ji4KpJrbW+6cJIcprV+Nvqynll
DX4zB8Y7HlElzvbtuAWxC2AcNGfzpYdwrfN/pgG9/LQ5VUyoRvHssvr6CNULxKZOD3BCrxlIfApK
fZCUUbVZ07OvhFDW7t6K/X1KC2JNI4S7HPsNA/ZrtRfCfYvmmaNwXdbanzPiliWGxxHGFUf4oiIO
xsb4g95wM3A33zWFqwqqeCXYR1ZNktN8yWkp0xFRLyc/t+GBY42sYrvIu/S8/Nn9M5Qx/vtoKqM8
UCQ2RmC7Aj2cG63ypQFMFGwPJOVb1Nf22oIcPyBO9c5XgTrnp0zDc+GviOjEx72CHdUg/tIdwU5g
VD2vLq0HsEnJupz/r+BjCcDKRWLQmfxLCII0/nTQs5HgU0eBE1JErk/uFgs40HGr+axsgjyAp86l
WBfkvx7t03NhQpDPV5vnwdKX6671+qAtKRzyKc2JYbp7YTLY2ETl213RmTHsQ3gFpVn53ahLkMHv
HvcL4hs7RqIe3tp76lYsCCnRqRGtgQcMVMNfJ78Fa82uQ2yl2RoLZH1fy04lLt0A+FuKtxpK9RgY
03JBHyNCkiqs36LjCuDztV/5JB1U8sSujdg/j/Hcy8NTW5nyL6sZRqDiLtNtTMqb5ANGAcYNioSP
MorFbJYw9GwlRwC+q8l3tyADMxFq0LDGSFU/drZYyRXqy3VJD71ATrWAWWr0ycatex9ThbV7TV07
68kWJMi60O3ZDTQeeaL7jE5p1OW5Y6xCjve7n+gHBJGNuDUMqNO9/x/RQX88Xc3xvXqbXeft46Gz
n4kPt6KA715oqDyrPBbfpJt1LGKhNaHky9/QSRNmPlLXVLfht0tHQGWh9qT7OWvY5o2LHGVgA8XM
OFUjtpve+nby4EMjXcW6g81YU6AB8WdS8SVKf2n18PHQvhJciZebM/OeHZHX6rYyy+VT6rOsfBHG
VWR2WP2XP2j7baB9tMnT4LjJohKqTMZQkSYsA9Ca3GV/v8WFa6XZu7FstJOoygSh5jZNCq3rLRnU
DG/E4lZglfbe50HhMAIcdHNVWqlc1tLe/HPsKyuKqsoUxDWo/rEAPXYaHCulmQ3AFp+3aqE9JFMb
04ySjn/axGiIHWPBONukQqpmEU28LKsbIm3KogcskoSMlQktxSwgKqXQRl9TocMMb18Pf2wnZ7WT
A6HtR4oz+mraO+JC/Cl3zg+qg39PBFQbAneetg9gIjYlTWPCIwtsHslycge18vHiyE/RgwiJGVio
r/H8ojLsiQWsULecUFUBvf8QkRLKCz48gHYVCaPTIZyImK3s/wQ3vr9/mij2Ct2ksQcktMsb3qeA
HmCPpyME4Onj6nhQDFixYasLAfhLbKXvoysjUsWfk173/old058p7BouGUWBF7Tw71LRAE8K9gmR
7P0/xl0cXH/u+s/nyO5rh8p9r587AbtXSw/gvRdXZyIEX194cyq7O07iRlAkbIUx8Ejq+87vOkId
FBVAue/Ihl9fUJRoibau0cej1torY7Ng9edSje0Ki7fxUIqKTtvANRDQzPkj7vrre0ARZC6oMdLq
hyJEXqFZa78zgAc5E3C6PCqBEaOG8dOvUAHQvdxGtBswsa8i/W/L034hGt/G17t7aiuPE1X07b7l
IUHcNb9ZKyQ5te/L/L0r/ebbts25OaYywJIzK/VFkG7wK47rud53XqxJIq8zUywAI1K4QQ39ZMnF
S6LCjEKBv7Q71pd5sVIXMBEpLLKj3E7/nY3EbyO6EHXuqBfqJPgeDaM4Bkx63MbaYlEJQvGhKC2a
aJWLbVmdm0OCuhzjBYCFqrzdDTfWoKKz4mIAk7B4ublhFc4N6bulRPfQY3rkYbdTB7j+ZobDJSDS
7j/d6JD+kbXkqJ2Pu6iV49ZySE7aLTvh+PdYkVZwYlQatWMtEXf1SgEGEb4c1XMC+MCHFPxGAnld
mA5z+2CS7rPr8/hPrsoQagSkXM/TVTMnIJnaayQ1iex5V/1ddaOOmrBh2dl5D1MynP19WVFbyB8q
jJpM2e6iu7yuCcaOxDoHUkVG4vm1NfbQuzAfzB3t/ctrB0M/52GyIqsCkhwiOopTEzWJrFJ1XDw5
Rt97MjwWfYpVG7Jr+/0+UKv7iFjYdqg7jdDdXbVIkj1af8pIJDaKovRL2ykrqtYr+UKJZj1hGAM1
LlVEltTg54Lz8gARapvfDP4tK7cUL/4WqdvuQrlq0Lb36dpzyeKigjrj12fnfJXhMSvfsCqozJw9
WzfdJBJEpOw7TZ0+lPD3BjP3Xab6rSts9KsQ3YCxnKoeiylt1nUTCXKo91UQgfn7+sImuZZCIF5b
1lEUB8yKN8vfU+fYlTRlm8Oyve5nNOJyHfvsUJIVlD9ry5GCPfEkELPCRDrr8IW7nQKq8gz4H9yn
a12mIjeWzCrdHZHFRCVzG8nmU5yXsPP5aY4VhhOa7UP1V2FAOTbqyTwhMdONT6nZ4TLW66MgxuVX
HqLmh7uKHI6Lsd/Ejgdt4KHMtifJtVtuib6amDoZiCIpLj0abgHblaLdLBL7Q709Sg8Okaj7p9uT
FJINerpW/sm2WU/BaVwGYVY9DbjrlVmOPqvGLGbGzqQwcmkTTiu/jRS7S1xrDtgMQ1DX0F9cg+EN
LkiQLb7IBLnh96kdMR4hlOTrr8xeXidENOK1nzigukKr1b15VY6z6ybHgCNUfTu2B5uQ4GvCf48/
dZ1kN6R8P1j2gh/EgFvyZo/0c3ovrnC4UANevuLNj1f8o+b5Q/vyJoAeWmUsbZK0hiSpLYATrFOb
bURAq9x59/kGDLClPtqD2XLJLBwg9O/dHsgBXuXUjwsCdsPAZj08Wp38hwxQo1Qej/RWEiaoP/NJ
8xpNYNNquDKFGrGl4w4wgPa1sW+T3tMp4/FP/jqvsbXeDW7+sRkD1S95n+1NFGq3Q92aR6kzhyrV
Xj3msZ3izdzRp1efNsRWpXIdwZHre1WW+S7GRP5WMG4AMBAIsBS0m6IwbG3mb1lB9BuhBjsTdBMU
MGpHeDrbgDH1w7WCgtb76yjl6Qt3xA2qOFP6rJ34aArcTA6iiKWWN1Zz+3Tbal3f0GTSwHudQ8a1
I9n1u7wlrAlJ73jH8+4xZfAigNwaV7/lsVCLhDfYOflrzxrDGDE8ZrrD/MQ1kuGPsJg7gYWs6D5G
eAevot6BgdrUVOp2HVJg86yp0kZc9AdnYaGFECUMOy4ntEApZBjr7HagRB3fV2osYgNK8415JIX4
cqRrveTCMw3c9IP8tLSgn6Nvvfb0Zb5LSiBAjj6f9CTPv6foOwzmbbTI4ObtWsd5wS3VWSzD9HMk
eAFsfEwNlrGWrMvnYwB0m1l3FyEZJTrbrRKa2kBiEbbTzVyct/wZW3e/2S18l4+f6OLb0BbECujJ
wKkdmF3RdfDy0IsEA28r9VhN9Vp57A5AatPl/VvZIjl8nQR/SmzJCl9nLIRSykcYNXruRaU4MXWI
Hm5kILIHjawZAd34I4XO0JYTzQUgj7dm2NgWGfK3sORZUCQJE/RRy3v0TpM5mdLkYPymGnNGO8Ai
/xult5nEmKxZylqF5bqSI3WfIGllGdeyz+OwUwb5RJtrC4Htm5T2cyIJ7XGZnmAEJC1lxfjqgz35
Bam/vncq3B//oKwBLqolaSJ59mSO/7TM8HEhtmejX5UQjDvroNaDtyl4mHj4gof5MKeyf0iuY+bw
8XbHq7/X1ovf5seAnYt1JBUMFN7XerutR1SXmCVE7nWYQnb5dXsWdt/MC3oK1/3TFW0D/Y18qac7
2aDY03B+P7NElGJXj3NdoD73aVTZVqpt0N7oKuWI4CxaB5CO1NfGDpoWU/wf37U0Wjj3AWGbmftS
1NiX+ZVfHah38jRabCqTCumpgaPjb7HDLgdBpdpLqkKysVWbgq+F8t70krt3LTS79wF3eNU7Mvg1
pWTdx5Hj8vla1HVJqDblwg9PE5w7NNQiMbxnV6fspkQeK1aOiTzpafb/SM0VcqaMTX15WxbMrLsj
8W8JV6VU9mV8IxEk07CSP/YK76Tu7k+INDJbDFFLm2Qmu8TSD8NrJZ937bnF04rPIkDK6EvXytvQ
g5KMyIX00FYG2mkU0l1IsRun+b0gjYqgkxo0YMDT4JKxH0wsX2Q78czvJQhaB5NL3PLinezAPnAz
7DJWnOvAdOlbZ36JJRMpZloS2/1bmvKXqHj5icUMPO7hiEc3Tw9TptGnD22NAFSI2KreVY021m0G
COzCtb+5kcuaFOrZd7LQJdPBWAUSjawT97WK01yu8/CneDB+EP5RoyiuOt3lV9MH7ErcizrWCg+0
eBb01FvyIWVUXBm3+YjlE5K1tpRE2taGUfADrEck727p+qYxqds0tV4Z3Njw/AaJKEWt6r8XBxLC
2K5huq3wnG2JJsenlh5+P+b7d0Nl1D7k47NFeLQXVDmpnaCr9bh7auf/T3fyyIPR1X0F+q1MX3xJ
nJ/glJv+oXstDmmM3H78SnUYEa/jpIQJmbgTiH8ARgFZqNza5d5mitE+W4axC9IOwyz+Pu0WJsMt
XMjCpjISDVsJLmxsPHFkG1UGCz/89qUav9tl3w2yBtd5CVQ9195oZNPIlEG05ZfSGg8DFhTNS+AA
eDiXGzpMaSVbmj46PqVQqbiOhKrorXU/VppEHOPnvY+PIr/W52NgeBmUKqn/G6/zr9CQ7euDGC/L
iPJ7OUT32JpMNg3QT+V9mj/k18OfuqeKPk/1N2/whyd5Dgb7HypMVHpCg/iDEGhxMjRKwg9QmGZ5
X4WCnE7a2xG99gYUlmslF5c3jdYt0KO5n4FEtWPnh2rcRS5sOaCf7hW6bXTM9sUb0dxQSyd7tL1F
2e4MhXtqOVuF65+2NsK1kL3tfn45od/4b57Qq2b4Oh9X+6Ftst8ZBSYI65k9fJgfrm0E8+k/Sfd4
dBjDu0njIoTLuMiGr8X964GVWHcBnx+bqANnoQ1BI2NxB3BFbydizxHcZZaaUEYeBJjCCHkgOX6c
KuHMpWiBYgtOI4/wfHolkCXzn0VKxRa0x7/YWOyiohrvhzKQUkBgVy2I7H3HR61W0cJLBDmTWEHt
L7KHzhEMckd8mih6zr+CWF3G2dB8aE3wXyYvw40Xx/+tC7dvxBXTz+v7rZ1sdbH82dWX5nBWDQxZ
7V+Gu7i1zSfeaRQtj9x9mh2smHSLE6FJ0SKmlTWW4yvfijT/+txZ+WYEDTqAhlZt7lWf8WSbgToL
nlQ9+3UwkgckxpLE5D0xGjoUPIzKmW36bWhr9NyRAYdJ/8pwDGLGg+qCtxeiSfdGhF75x2Prid1W
8ogwHuAa/ozyh/UQjr7uY0fM+S/K8OIXEsF9wICSTiAvC1T0EUjocNDT0+ssts8Sd8I1O4IyxeXw
6pJ5PXOAzVMiv+QJIcMBiGoSZIufllnrbXg/9+h+lHo/1p6MWYj+fEFQVlhSR/YD5SNWMNgxahsA
XSzPBnCeBCK2ZXlbc51mlY1AW79aWhQiwfjysNdnarxe7I1LU2pJTjpWVp3IHeaEFDm3e/78O5Eb
XfopTJDgNFHbLokYuAoatM9UrNnNXPinL+v7qSluDB1AB2Vn3+Kj65AildcFEvQE+QRiafDAvePX
wm481lWxk3/xnM7albkIViFmPOldp180XViWQDhCA7j6cjTvovdtYIKQZQ0ZW5MhBCpt2h8BnmWn
jY0228hWCM10VoOuEPOlt0lEXqUrCenM9Hs2trDWaxgaVjRPqeS/8GamDwvA7U3qVn9t8aNB3Kpx
WGYhowrU67Ka190k23myW4NUVMPABstWwaLRflSQNv3dPID0WqKTWKkQ3/rjG+yZgpzhey4tatjL
wydgwkIHJI9m/tfRdC2QG66OPxaAFw3Gv3+BiFnbBkpXQvSlKh4/iSlCdqUYwSq/4SnKvYtpqnXP
msiNEmGZP65PWO3YuQ/hr2Vj49AP9sY7j73KQcG/BdePJ3mAOH2PdrNUoSgnBFAyg457FIVn6Wkn
+JnJUY2oXGHB/yE6X8nHKrcyOzBEeF9tEgD1t2AK8b1LjTM5ilwxRi7N3knQz/+Nrgn8VikJq5b4
Ge/wB89Z/okTQe+OdloTCww0iRvb3jxmxneqHYEVWfc+LkUiB+ZMqol8UDQlhJ8Fp8UNarLSHZ7z
hVq64b3Irw6vBcs5JAMqX02+ZM93cH3iprQ81pWPWA3ol/j/px6omGHil7MjJOizl3xnsJ/22AWB
dm3TuBXoTk1hIEIcSrD1xpWiId9CTmW/Zy/KUFLfduy1Za2qQDuFacCSsimUyRTaRGrytQPim5HX
Wq4BPRtWDcQ7Jj2jjPxV8JvAhuZUYH4aKROmfy8v12Rd2jq8X9PXqyGcmD9waFMEnmv5khOWj5Yd
RbAtxum3Is8Fzlf3+TmP5iO/x5NmH0tAdxW2UBX+ap+WOx8Yyp5w4rq4eQzswzV/asPC9qHwSNIf
BCa453mjr+9v7nvL86hWV8uTNODxIaI1JmYEtDhx8tzdSd2RvyCJdevmVxX44aYnoZXWqnsxhczd
n6BItsszBTTF+M+aYNM79oFX2pzKWW7rJ3JGAxAD7dcYYWSxM5kElhXtVCVY+eUP3PmADj5aFZee
pnBg6SArgiQk5lQuW7NesJdlZ2haw8CaAvC5tHFP42knezT6vBU/HH09Bl26BsP9YrCvGEAIKL4s
0366AvljbNCnJADv5CcAcKXkOqQSGA7p8kk8gflmorLZ/rjoLzESsIahgdzfNwfJQnyJuZHvYB84
kr7fSBymVJ/xduLbB6wMenB/EeYXojk2mS3hrplReU+40cva5rSOgoBHdQSb2RSb9+F3NZZugrZb
wxPZFfYAUC4YrI9AumTdtvXLLaJ+fvZ4FBYKfIcAdZM8+XaCzYwVa8GUGDNB3InV2/+WloMNf3Pi
mIe4Z24rsA+atjonnvxp8RyzTcgyXHqGl+zqQqXapV89WwB/tnCNQcIsAdmxm1hzUsUsDCu4/haW
ThgfTiiTz3ItOuXtpqfQ/D3mzgJjV9n9iPVw3qBG0RlMhkkfP+1mB8WIQLKbpf/1es6nTD8x9lmm
B/myDJHCGNqiL7383HnVQiue3xn4bIdGzDbIrB+usNpX8/Tq8ZtEcJXXvcn/b4FSfElIsGJSlfCY
/F9BzxOwhaBNLE3qPIXylKdiF5dL8oOXNzhQ7M4o7zqumEW2GE0KN1OeuyV5vuRBEPwWl51Pn08u
W42OpLZaUK9Wu9/rXl64TqodBwY9X7wWlvAeUB4QFAzMzwFyd2HwlW15dqYxQ3TeXeYLiyr3PnC+
C1rqhhJKhflweNa87XFO7GHcELO0tbhP32ujBIwnHDzGNpNZhU9GOq330cER/46Y+U0H9aPN0Nr1
O218gh0hLHUGKUVT+3+KZaFzDy0LvUGenSsJQFRNXMBSkwOlZ+5kmzP58s2jAKgbEPcQdR3cu8TY
jGkVKm0q8XIhMNdCX4MKK/V3oXFXiTA3wckhilZcWJn50jvUquklSIISp/PwFI3bPPCmQDtDkuKS
tAjiGeL7TimkXYqfukmdZRZ14wNe5wTomQJirMikdSOQ5JbAXZpFST2DZ6WyJqifkia6rw1WtaCs
oO2kk7jo40P4n3N5H9695x8ttTXkUmmuBjPXEZPnB5J4eljra3lGhit76FTzK7tg98WR6F4bmHdX
AgeUvFu4UWvkdES+S5nC78LWGHWwxexTHo0ExGzouCRYe9HBGo+VzKB0foPfkS/W97qFDUOoHC2e
XpMmPLASCIOKTI6q9keCbQo3gIPCxKR9RpoNczJ9zdSP5lZqEYfen6qXxn+nV7trTStqJHUt5j4U
yZ8ley49V7ve0oYkqaKkYwgKyb0UXagwe9b7T010py8iXzQJCl+UPnS2i8uNrY0YEryXLEiJmMlN
Qes35I+6kpRBcs5w83MKfMHuJG5E3wViOLMjKRhgW3SVVKRwuJ0JQQdrTW+FDY0W60OKwcexwupK
Fi7KejLChrsBsmRhlM/KmZhA+sfGXUeSWCBYjfM4oYH+PA+JVyCOy7VKPL+obvRfGYi2K/alkZQg
sY/ZtcJnFuD1Ma8S4MeBoqUYepgzzoVWNUESi+FaVYLU4xcSpxBBYc8n6uA6KPH/KVH+rljiMC3m
rKzV/6KoCxSCn7Ubg2w7bf/OLriR+caJVk1cuemId9mwsU3QIihJeN463HYebjmCkgLznNQDu3xO
1XFHYobTMBH/Yxw47tijyoO/SmyrytoN9iscJ/6CfHfnsp/+pae5Z9DTZ0KYlzvr8V5dgKD03WSh
phtEFxnddi0WpMtvcGdEFCQZlENaylDDmtDgyZRt8bLa8waRTPCbI+WxPsbtC6TiZ8Q3u6Ud+Tuv
UGPbWcRqplqNPb6XbRvaCPZcSsk588l67gWTmeZX5YInKYy9OkE2/rSUHrFA4WJpUAB3sQ4tnB7L
+eGKG+eLlMTtDcBGsSL35pOCaDe/KnLWorTu48maVVV2B14te0U8NL8298uRrqpPqm/YQ1nsaOT8
RYF8Hve9oEV5btQT9nmj6vOA4NazZKxZBoTPw+lifmkx4PsJeAwjPTGiTqrli7WFEYFDWcdnTTUS
8+LpI4HHtKqFbZLQNbG6k7i5miVQ7lfm1KF3143PdLhIW8+DeOLT2YIrtyL9k/RFH6clvV6dsKXh
Xvqte2Iho/pK4+6eOEPUeCV/tjCuaQa71AVj45v4PvCD77UKBqCySJkKb0cYgKqYkN+Cw5TEUa10
vHdrAqV/2/eiIsTVxEofFXlDsr3QF9CgLskQqaY3BMzZUKwsjxT5CJGI1YaKguXKcRu6w05eBfyl
p6b82eHevpN2We6I9PePMs18t7MgnphztndKtQOn3R1/tRVLLquaQji1qpCa2D2D73y1uKk7jO+Q
v+sNaX093eWcHT/5SO3rZJ2MWlbKcfWhfKmKNpJgQMlpGtAn9uKTzTFnS38I2zUZgRGauu+sKbw/
YBXjcFY07Ap8ucPyj+bzoamBYAkYxK/OaK1Xzwwq9ZSxFh3fz8oYwp12poSCPsv6iZ5U2EGYBnEo
fPXYAhegnMT90tgDj6/XwbFCbd/DSDZkf+Jf0kI9UJYSgigESAA+gZvBn+P2v0oQFjxowVmN6kmF
RM7Zs1SSjtIc8yi7dNJs+4z57MLj3ZLjRbONJf2MhdzNt72X47i1eqPgHN5s9H38EzOsq0czpmoD
81KRkmzQIHHZtYHcGn4gks3GJMRqL+8Kiiq6pFIBgPxjd+bTAFsYnfByjzBRFlyjFSsy2Bm3/baG
Of3lh5AzpjaEmVYRUBSTEJVe+dGkavPff4o+JrNNqiwSm88X9sw8wkJ9bloz+xxxZ/Qwu43QeYuv
1IdXm8i4IVlcim+FoYW5YCjffowX0ZUr+/U5CQlZCH1Nq1yY/EujEKYQPz03Y8ABipF3gF5AV8jW
7EJ/JjcTvCR7Ow4SEVYXJnwGcR/eya59VXW2DGbTgR/3JPYytCBHX0xyLy/eDMN88EKCUz2EOv7o
4Jqbg5kTNSjxJVbdDXzWJGXsBTRsA92HL2UnV1p/wN26D54JX5AtzmRpmq6ogeOF1r0/iIEhLJVL
D2Z1Q2f3iBGgdLFhH7OJrUOY0DNCZiVn3PQ2BleEHhbkXXULWAUb7NjW33QH6+cCpbe5DAYDgJrk
6ppTHCtAHc/53/evtaThgzKaLrNaq/H7C76DrVuSZVN+JWrIVbO5JZdQ2LLtqMhSHTeC0RYej5mi
LKr3HJcLue1kgg2fH1bOHUIXa3Q3j7MIpXDg08cpa2GrBEpXSaHNjG2NCsrN4SRAEmrN+NHqXhGo
76jpbpVUJF9rr0Z0oHj8Bqko1U+6XS/y3Q0luUzzfpsM3VAdyL6pRxaZjZHC+aLkBDXBbYeADueZ
iMsgYklsD1KCGj264qK9wXGNaoHxLXujG5HCsQNvQyVcxIe/aIkexOWuKBTlGduJgi/n3CiXYVq3
zucZScjhpuTxKMhO3cG7U+bkjTMJKJjiMPPmdTtIAj6ZU5FhoKhbQfQMR7sNOihMtXxR2QeYbDbS
FEhlqG+Rv2uZlSPIg6/8c2qgZusYoZt7ww7+ASNypp5235UrE/dZTL2FvZoRv7/thw9QHt7fvj/8
/Wd9hxXVcgW5gArdJ3dkhHR1YCDAAFkUMXUlx8jdWOqQqF/CDuPUS/fwyj7pQew/CcuMi5etXBa1
ZTYyztqLEIv5CROtmlHrrmfnaeB3djyI/E0IWw7CrvpwVM9c7Cbr7cD8LhVgUO0+jdYnI26Cmg3h
DaiHF6r767IK3fJ3btgoWzZrX1Y80Ydc4zPQve7OrGptZbwve8TdjYt8tUB0qy4fDzXNyPPKCNvB
wfmQBAwZ078RFSXB3aopOM+bnXDLf6dzTc7UAgJ5nqYT6++5KLpnDO+SPLvjhAjutc/HDqZ1d0If
e+ih/mHkCFIuxwYwxRJ5d74b5fbcf7VwdWm2wz8r1C2WrFV7fSnuHT2Bs0d71sEPWNpMopzUuz9C
jMp17ZM5wbxFLBttWNTssytGx+vUnl/Jn2g5feSG4pnOBujAIf535YpUZNyqvEpUuZEj1PpIzqLe
JmJI7t3KIRBgodCusWphCIcAM/EyeCOr/t/7xpforne9ZmgE3WJ1imNc+jNNIkFi5ThpnMHsVq4K
mgzs66Swn4rKHMlJEwHwpIP4yAOeJP/Og8IggCXbszBYnWwJNjorid+h40nM+m1AZMxdiljfvSx1
juSo7REewHBk2DfUPtnLms1CBF6X9s/WLB1ZoNfZohHAG5zlH5eoMYcN7s0lT/BAsaguE8RFnG7y
3ctOSceoUHsPfwlgWahYQwlGuMqj4An4vHTieo4wIryG+Sug8wCybDllHVPxXNS81TK+2MJu1YmG
tuWi1hGCt2Lb8p5uqy/qU3IicNb21AC1mgWgyW7tZUWJnPHab7zwI17bn8gBVGAyXGN7bM3sWiXV
XTiO/E2Yj1HfVKbWZKNakNnjjXMIM1A/92PEuyhGEgXh0Fa3HGinN4cL2yAg2nb2fiRqMZfgDqcj
wx02ioqG19/JFCtmiUdZAN1/PIUleqtlXbtThdCJUP6FxbZwucCc2mRtYQfX6mGQ+OHr6EdEdzss
LVyM8c2/Yxv4bWxNDEMiJ5cml12EODzmxqK7LI6Dp1FBgPxne6begBIq+G4wNj+1Yk6KFy5Y92Z+
IIpmC0qjnW9/TmH0eV5VDwcTR9OVP3Jc8ZaOS09JSRhM31FCZWCmxqPgKNP8Mzjt3Ka9xg53W8dY
AlzT4eYVzQoqpwutlpmVc8eU4AUlhnt2j3JlT6r/FWUpkywtuI5xtGTqj6RDREt6SY7c03OkL7D7
erlMERrrgrkTw/vYs94WpGtwjGaZhjxa6blnHa96r5hVDK3+X4QqnvND4tEfbRpvZ6GiUeFvudeH
vkjjJCEtmUPftwjmPwtV2rDi44ZMBS/vNCpE3YuP0x05a3ieauJCastJr5WEvKh5R0lppLIXsGyh
8IjCjEgl3fuB5B07AoRv8ULmWV8rK8WJBuenRAUIi5VDqVXuiJA4yhxiLITc/HHaglrzpuYBfoRW
Tnaxl6Z9tJ+LWET/vNYUAClza3nuiU+52bao2twIkownY9/Cc7CfRTtsxk3oKHNTHC4QX0RkMA7T
PNCqid+uOzS/dzpTmxukY4m7VkFzm/P+uERUmWPyjpHzsyO4epQg7r0glJ3/WXBGS3u0huubuRVp
fRvt1cl+hFcaNXe2X0C6p5h9NRGPrHsWsZL+EcaF60n80RNpu6D1+bGYXfXEg+t+HBkioVMTkWns
GXQIU8ttO9z1J9GSTlmSQHCTRLig8+jS2G9tsRQQ0rsLWei+B9Xz6LUn4sW32v/JceHMtZeOOmjS
jxkOHck1t+lwYTq6csP6cyHonzShyovlOVO5laQjD1Rn4+UiDKh7a4UyArCtl9GDTNdot819rv1a
i2jwZ8zGSAhYyp7BFXHmEqwvzuEoIPAWIdqFmHejYR8WECuLSIEIDa0WFv8sLbqhWcxgtyjTzSpQ
A1Ip1dZwhnWgdONiOS3gQ3drB49y/AeKMzhao1a8iRQMdsI/kdkltBKaZhMlmSWqIuGTJ5JI+zCH
Llw3eUnwHbU7KqL6XVM7o5pyFNEPPZ9IqHIWf+5G30CyCQwgAZIEZqPQpUycCaLUJpU2NADnTcn5
EyOP5RFZczOKxfV1UizDYRHk4P7xWjw+8VCsgYicdGbfc+nsFLj8tJZRAQzQTEll5BAct+3FGSGt
+6rMMEHoENPMKfrxr5fLdhxSX/+0I87UeStRkE59sWYhE+L9eMv0y0YiGaaCXK/9S3+legGtZnDh
x9fHhGJljDzGaiANN5idDvzPoWzPb2X93wkq2gcAOaPz1TRWTB67oKxj1KHlj28KDbPl9nNEmUFX
Y3b4K6dzrQSzIgrYeXX3F2aDJwhEaN9ji/MgtXmHErsQOD3lNKvY7YpwSIUb6viqJiHekxE25hMC
PX7uitj0Q8PC1iyzjx5Fn2K6+FsbVcRlojAAvKqRgCgbHeWRa99j4cEuEWpfhl5y9Zwkg9DzuJMV
qnWs17qpsJrHjFsaKP0u9QVL9WkWa+8zb4AoLisypFiDPaUwkjmuiO3tDWG1vEfl6fHYA86zkqzp
RuTOwNfhtofvU2fDCspnnEiXuwxDhMOJlTF8BVHMRqKXLnvTc/OK5fYo7u3c1rIYTzWbfP3PYEn3
nyJy/90iyv78TQRJ7M3b46UY6xG5wA8Qt6eljh9Wjjaeq+F+FWeL7HVRVFNlv/RRmej75U9H66Yn
FpJx2++pc9zygqjI9oZb8vknWjricDgki3qwH0FdUsBqmDBnnyn/gqHS83O0PFN/1Fn6dtlfy8lN
cXEE6u1hyPprSh9a1iWdkHJdghp294idks7mZ2v/tI6kqN7/WT3Kgi0NT1XsPNtXLYEQN6sa1xgM
SWgk2dMOBLtKdOqPKge5l6n1ykhl5tBtZMue9AxwlTQPypAKLznz/c8HQGRdaIGSa3V1fQLBskt4
eRGQscam8b1obGEsdNQ0nribTiG46o6hXrjpyrjtLqn9D4ks1tXiiMMTSYmPe3+/OTK+HiPwNE3C
tSC9gTk5oAOYG1WYrg6XKYKJodUfmlJlYGlUTPh4I24Obc56kQ+epPPNq5PQ2+KL3l4t/RaYb1IK
KmDf0C+IKTfZqsl8b8JnL1oZXI+KBTCSYz6Au+/pq6vMKKog2sODcGtMe/0Tte/I6hLDY9jZ9LUT
UzUWqzKc/dIRTCxlwBQO2poI27gagfIXhaNMyK1w0MoWkP4FfQGA59MyseJMyp6BDNezePkqRkmt
dLM7f25QhQsOM8332MO8vW7y0r3mVqFXlzTszhIGY1/t9FvHhL3sEUd9S9M9hE5SFo2vMhNsCi8O
SOqhW7YM9crqqFmU9W/V1jh9FGDtpjaHHZkEltEIBWzguoxiE+XTLqHqMYj3hZnVy0Jo7PhnIKDd
dnfB9qsCcuZOpz868NmF6BLbJQem0C3BVyDhFkG+Gg6UHAo48xLmcjkhpqRXqoX6e6a1e516j+yb
hz5t030HT/iBcbpel0QmD9yXi5G545WZ/u9/3O0Xx4McGCM2CABVjvxQbdykHNqfCOllggDI2SEv
AJcUHQ7Ov8gb3II+nkCkNUjm4yVlr0SUeb/vmDg0yaPhzd5As5XVrcto3MigKc43OGBuw2SBrvWG
WxeOWf60KM2yaGBP9iRz2cwSrwz+fM/fi6aPccrZyrEE4KuZEgjUt0y9wET7jTbizpA35ECI8kYD
8PU/ib3z4Rs8JM443iCzSfV9/ZXo7V8xSnSP594ZdDF8zF4pEsc8m3GYQk+SLo+K0Gte8m16arvg
SR8G31njBxFWifXkiV+LJGalM9uB3p0joBRpybn57NmDcam2ock4W3e3+Y/d+2pH2ItywIh7FQ66
op7aUPXbgMq+x7N0iN6oSJB65+Jfix8sT0liB2SX3V3dszWyVfeU/mYrnIxf24EWOHpJUws/uD0i
rzJrzLvSXZJVQkY6+AR2JJ6ksuSuugK5Rh9DDyzT50M8hx9HKQ7GnF/bNmfxhFR+9KwXrkNMn5pa
ayER9w34gBpVQe4o9Y4Xn70xp4HiI8/mMGrEh9yKUHjjR2Cv4fZUMtzqzy1evc0jeJkIoXyXwvX1
lEEIZ5C3lytNLDH+xdx9vAnEAvQeoZ7q+s1BCK8X/M9wPhT8txcfoyoxkO3VVC+Aes0iikQ1e2VZ
jdtbLuTjye7uiCpYk2wb8Jj+CbH8RIqCFrPfU69DLTZ07EDVtILAKScvy6ZZChojAl1pwOiL2xqh
lF37YMQGSwpkZtKDrnC26yhzhTPVQgmE0YzN27nFW7SsRpXBaWNj45UUEKQ32rz2EP/HjF5zzSdM
Vfec/6sk86Hy5g1NL9r/97cniT53UnQMawHfMOlamv6P801JDagDL8mltHijD4jpFbDFg3OxG8cx
8btmd4AGzVdjLWkVFdZe9YOC4JinP3oniunBOsXwqJVRNNYNNlncog8eLWhWHtfSsDtH7YwfpurA
ZhluOiln4Bq9SlYVMA8Jp32xUiovFCsnNLCntal/4Itrs5v/kd8DKDgBZvajV0lfH7SH9GvW5V0q
pBOR7H2XCF/hpvbbVZ7e0W+01qn3cXAF6bpkdXidD8k0rbbtxnyJQQZe3Ja+XXxtWM+CZlpePyuU
aPHzmWdrWq/Oa1BrEtRkMC5pTFJF7HMf1HPm95XtFYnJn25GSb5Zeb2WVjK3wnD8uC4ZHLtoU44l
BkqO3eZ/6dkTK0uHzg3LQrj2OXvm+0L5+e7Taf/N0NmTzYsHwWIXYV3M0v7t7Ag+GGOhBWLqb29f
JHjTJ9HqXnVzRXCtRvTV/Ah/CBNybgTt7sr5P+a7ucgZA8gdiVJyMvUOLLfF569ZOPwiiyOcdh2x
63mJQ7Z/Yv5VmJYBBpiIhYKwZXWiuXBrFy8DYhb7JfxvR0IGKndlF19cLztT7UBQwESFhjxS9gCN
Oz8NuWjeEnMjItpWuPSfYQM+nN2RDZ3heNN+B83amQEcy6un7oLTBiRpup3gIfJmF88Ymu+QtyQf
1y3EF/mh/WKCD+r402DU0j0TYYkqakRn/43p8tuxyp8GkN3Ot/Bti4z5wX6LDAQTjAb0FjrSccx/
iVR71Qe4uSEm7J9OJkLUK0i2CdIX9qkak4OI2GHnb0Owyw2EzXD9/BCjLKSg+EVDQouS7Kh9u0tZ
GebcWyuXt8wakCQuHeyk9OsFnMq8dYCLNTfcNVlcfszwr41rvtGGRnOQn2cnnJyJAsQSA2TB0B0G
qGM6HZB1gAuXERcETdrq+GyAhSzs94Vb88ErVl1jWHfaqp/+sf7t2K4TbQALKFw+h3jfU/E8hfGw
e8b+3Ft6udHtT1HpXpOsyBRJhbvtgQWTxy6ZKS7IpO6FqhQjy7uc70D5HGCU0YTPL5wxeZdmSk9e
SzqDEZTMrpG71Q861/30bvwwjbA0tpxGKOhnURYuteZGBi3oeRLJ2U+iRWjDlKbNME1jjERKCVzy
ezmDCxV0cn+UvHqcRQA2p7Alxz6AHo/hSd2VPvJCSS6HI7sxysvgczZYc9+hOaNumMedq25XJDcA
QvmM3QptFtbbFrgDvThKVR00dQGfJZBOPOcDVmKvYmxSYkyMCsua1jE2XyqRWSS/NlitPHQSY2gd
nQSwd9kCiQyEKbHGU03Q09qFSc1tllirqn42Dha0IngDTvrbf6OUtT4JWr0JyNkvx1Cxm/buJLrX
6ev+v00zbTO6xBir6U1x+6AqurlCWglARGWPI+hP/u8aUXJAm44KXSwt7YoUTd+of45qvzFE7GKQ
ygBkFbcd+LesjkR5BGqxEaC5MfHOwjQy63MpdJ14q6MAr9KHTqcirulA7qe5Ba7Bgon8Js5uVNUw
Er6+rS9U1sMtLn1dgS0PBqJUKN4t0O0lsNQIxHxaVilpSLakSmyRj1kybf0f4OCgd41jd2W8b1Wx
6lBtZXhmmpNvpCaY9eEJb6y5r3INDXSe1sjzm1Brd7fx57xXZEyEhjhtofsRAEjPr5pXs9P9TO1D
r7xeqp13JKwyeNrhRW77GFW8/O1bXuakAXb9txm9Y2xQAuwOmtnl+zU6VI0fw7XYB91zW8jlaE3b
TcMycx4Yaq0XQsM7HSn8gg56AEwYzMcUCmDoQZHEtcbfgsQPCvczOPmbuoR4fq1X2kvqzCs/yk5C
1EGXA6GW+ibGQxBnwdfbEqxM9sLWrmiGh5pkL/3qldnL56vtjuTWB0+2bvVreE+BQmHrra/f8I3B
gXaUJ1wp+NV2YoNvMRZnbdTDivba9Aw9fJ444KuD3RhsdoBLI1LS6r0IknxpSFk0B5vV47Gp5bK/
Tlci3r+bYxsU6fL8scpAqO5xaYcIXd5q4RHbveDceH+cppPQTUv8iw6nNLG+7zr6oMZj6L/axkpP
NG78zqKor8M/3aB95KM/Rq/1XHtNKxd/gaEWgpdMfqDXh+h5oqH1JzCqqyFO0/JNc0GbBXlo9vXL
myshtvon+iSE2mUyJCNHXeroH78lsSpAmrz3xG+f+vlN4QI52ZR33ruoTlDATGxSLCkx+dzjwmdf
f3SYcBYB/HYl/+GeRO4cvQXcvBxVWTz8Q1bJz1GWLIdGkkk16i7xS2TyYRyexaFgXfxJazM3l57m
ugPCayaXlAWLM8147UXQ4i01/naAI7hZVCIO/VaYkBQr5VKO/oatUR4tCwKGDvoNSE4OREktGvi6
VdP/osWDDtjhL7qygXvDkLpkpDFDHkETBGt+0P+gVSuRzfhe82oMv5Ic41yGRJXRo+9PQmYx6TIO
qWapEmO/jiG8i+z4tVZ3Vn415MqAHVgZM7sftAijB6nbUwEedpmr0hCrhdJm3hEuYwfbXeyogVHH
Ojya8DgO1tMkP89KWu+5T4Gk6GiLju8eO0Dd3GNM6wZeRsoDW7Z/ZgOTnadM+3LNqFLUBdsCVITt
QTd8dk+IwEJYSHjG9pmw1XVjJMIufh5I4pbjSil/XnGjqPlGdFT83xYG9752CMGqyG8BdFEHJejg
l4cza7cD11l53+7alU7nJwFSBgIaLtHVu54g6ZCSbmwVNoeVlowyYYj+vziMRgjO4Zuo/wZLMYcV
USYlht/jGjHEB9gmlTWpNjdq8Q+1/d3f6yBphiTURbzGHWxTKKV+E/ra3AiUXDx1UrwoAsLTA0Fz
ga5vVAXfQerVyDhDvovx6qEayfuyQSUbbaYRySOd9IWecBIfjn6/J/efCRtiGAy6JKKvG/OzCYbK
oLiIEBQtCPDnDYPYGNiCnDIq3xMYlc+sEyNq4nvKmOHRCKVXik8be2mf66Kw7S8FUpU7/w1FSEZc
3cuvciSqLqKIA9eoAtOD/ezO0hgkBz0WL2BicJdR19Kw3WOS9Vb/W4soqY/74Oqeh+pju0RhP1jZ
pUup8TNNK7rzAk8B1dG67b5TwvMdWyh2aKN5vvt2vQb0AxDFIvLVcIS/5+yie6a/4A9NeN1jzmM4
A89avcHXvXI1G6KbHI4ROfqB9BKoKltno/dLTO1Z6C6HTZeEWnO8S5SgcUoSlPl9hxY/ruM5FTIA
tBSW4HCi9qOsW3hwAIyiLMhztXuSzBqohw4fkZMhuXdf1gfSmYTATu3xxyOwVXRMzv/KE8lN4Ugw
eZvIGCYcYWV6JJNwuLi2d+T7G6huJguWTDOdKSINFRx+jWAEwAwJyxGqXFEIoEFR8cSG1Jr4J0lJ
H+JVohqLf2wQSs/joPgsbU6kgJMfZKlRPm6FGuM2L3knEbGrhC5xBIjwPxudN3u5hG4IL+z8PaHs
5ec2CgnEavsCt8XBqrBq3ObbGXRYMSDJXvQFZJj4l1jHScJYwqqzOF+3Ftxc6HK0FXrUsoAENuj9
scwSA52N+yWGh1FtBTKdO1MdgrAOPs+pKVH8uhjp5s2q9033T3bGZoRtus+956QqOLG/XiEIBPEy
SVgyfo6mdyPbhj0S9PO8Y4ZYJ2H+si3dfZIuBT8IKEKV+TL5ioRkHzTyLRqwCZTwg/Db63kWkuA9
kV4bFdjxT+A4+ixBpxuduJ7fl6miGOW9UTYV5UUn+i2ZmpwvVyd3WOgjkCwgq8oLwWlRAIrynvmo
01MbltgGlh8KqC7gsKeKNRkTDJ6Qm7hg57UcCXPCXir4gQfNZlsVhR1H/7bhAyY4C5SFA1J7qfSN
AeFgsgy8Gthxe9YcwhrMK2boaKZEjOFmXMb76lwsTR1/HOIOUyqwneAptqqrvkjjrJbPD6e/oIXU
p5VTpVeImnBduNIz2O+Gl8qwWzbt5Jta4oH75xJ2uzNjTrnD/tM8lUt6RcYGEDQjxKwZMZrRZW2e
Rrrfbokcsej20p08esCVoBgKEenxp2YjaImJYwrGG56vfc6xsA883Jv9FMqbvXRiqw6KVDz101K+
zWi6JDTg+MUnx2BJpdHN8lcTNk8jlo6fD23qVEIodfupF0ZT9TUkIMhWlGOyqJke+1D6oijy3tzJ
+/hnfg01fm4vIVUkuKnrOLLIus3f+hitVqTY8RuB+Gw6z2AqJAajJITHOGm+2Avr0OnGGb2yhtPH
K5jUR8Sqoa0u8nDsTUPqkIJZiuBG1AQss5GUW2u4EEr6zKDOe6zNC/jmHMAbQ+sMAzmiBmsAufWJ
hCDYCIqpetJOVDuh8TUe4NV69/F9gZKr7P1EqhrvOhe6E/1IWFkAZyswoF74Xu6g2LpqYV4gyerY
HokPAyM9tpKlhDeErJElEB4aRlfb4JtazQFi1M8IfF5z6Vre1t3HxqqRKSDd9Z7527W9O9P1M0Wk
/hciSeNmjeL0nCuvNjvIc8hyQVbGA4BO9Lvz0GM9W3OIOaGHkLkOpiUpb/PtOK/YEiBaLsOsKM+7
1fZFDJIkcgAvnf9g4DVm3s5vWTbDuovV7PQeqzIJ1me8h64IHy9u2LUpO7SJOe5vrHPG7y3T0YGm
UR3TK2O3J54+T7p/PZoT+9BOYuF2l9wLUCm7SA5+DUPE3cTN12Vt9kOoFaLjB1hvfUHca4x4J1+j
3ysK2nkvvGi8EQyhU72Bipuh+LEgxQeGN/PwaJdaxnPuhINfTISKJsBz6ulDXNHBzcEH3dCMysXy
rkRc4Vrb70yZeTiRTdxKs5lfdKLM2dx4rSz2IO7P4+1PxNUda0fxWI0lJRG9MeFb01kycMo8ex8Q
sZTuJ8H7ngk8xPUYzWAh0+tIpPpA4SoN1itrkN+ZEOOkk+QKZmDNqA6WL6oWpe+aDdn7VRw8TigO
Eb3ETg8o+GF8ayfmiCG8a6FWUNxET27c4Bd+xeWKKzPH/SElF0nfCnublyqAfb7gE/jQ70DUxuFF
tUCYWLEicQxL/wHuzGzNyED+ZruOmILgzwPrSDEPzm2s3Cvm3hDk1q7rXZL9ai9fF9JIbrjapno+
TlNqeR7MFFlcHLZ+PLg7AIN3PTJYdAiHlREvdWZrudK2UOQ479hOgG+aMIWeAdHXxtPdGI3IPN2U
SL2PyK4jSyhD/K0AVUp/gajNpyjp/53VkPb+0Jiz/oeKqzEjsoxxgSkXrQ2QP4r4M7o4W8Vw076h
0Dj7vR6xT44GrXWfn37QRHLsI5AKYWlA3pqP4bgtrxMRCLRchCjORK/zjPAYwwCu4XP4q+fE+ZtO
wSfAOc1WXf8/rUpvPUPHm9KMuSxHKl5sFqvHvOxDGeJHmmZLGYX2/B12yD87++9bmqbdijs1tx+Z
h6s+hXp9L0MgRgSjLCG0ZmnbLFxV0CYGyfXhPN+sreHlMIuuXJidaYODGEzIX9G7I9I0nNDQB0K8
4AVvrMMBbvNkLriqH9tycKX/kkpSvw3Gz2NsAdQVoXdMI3XVmNHhVRQiSqay+VoFe5D7n5invvpq
aYuMIojndxKHHZunE5p6cUaJd5wsEZ2WlvoRJSb6HFwZ8kezeSxNmzKsqEtWSgtJ8bTJbRJc/uUT
ldb2uIi3o97mpqPA7AEBcFrvO6b7+JCCuzzA2t8380ZHFPG7Axa6Cos4a+X7o/PKda1Djrj4mCyY
tF5fDqtIDkmfyMSGVA/4+EOoH80L8vZFt5V7Adyjbz0UywOeikt8gsQGB4lTqDNhN6DJgBo4ntLB
lx4L/HHbkBZ1LfHPi1OdpNYUuD76LsZQruSpLtNmMRqTn9+dfDG/dz0iB1Vr/8Wtr934wtSv1Yow
MxNnGI51yirVccwDh18X2qHr/9Egh2YI+X9JyvWY2PQyOhCfKBdD8bwfi8OdOXdLuj+tckqZsO9h
gl6F6CSgjAa1dqqKW6g7rH5drPlaZ61anxreTADRdMrbuGgyz+Ai6DfgiB/munDhVIN8WePHLaxr
1H+1MkAvyHJFM5Tjavu8kUrnq2gpFF9eWnARwjfVpGY+8W03t+vfLsgb8YLg53p7RzVD8zy7BLdO
BXmcWPkFrLRGj7uSoZZK/VdyuzWvhDiIAckFB1jqrbIBrQuPqR4ZCNMS5uLUgv0+uMSl8rNU5JxA
lkaO3nyLKjLSFiby9wyN8FJdN6esiB3ZgpnWlj3adl7map9OlCWfq6as9eFIlspz5ZAsnOFvWnPV
x3tScjgUi3VwLGbxyn0oY9FfIFRcmlJLA2b9M/+0kuCB+aohsXIddDvqTlUr9Sz/RsC+TtT1FSAx
PmA48RmhC+4gKYNeEgelt1k4mqac9hj0TCBA9HeY8KALDJ3n2FQKji8lxXiKKRn4KkPawFURegeD
FrBJ+WDPmJ1i0QVK+GxIPLynBxQC4/VtFd187Yq6mAC2ZPxSkIMAuqWGkN5b7daOIYxD8L5/ECmp
cYFDnQpZruSB8K4knrNVV87mr9pYSC/q6AsjT6aBGMzO4iW37VXKu4PNmNqKHtlElgrS21i/hRRC
3GUj2Lui6ahgRbBUqZ73JlfMnaOumUICGOHOOxA6NvuD33xFDh7ZTRj7vw6o2ByssYC2wkKpVmLV
slLmGTWtWmdDhneQK0El/RDn264eQGCLM7F/PvrUtjkWjMolzn0nXmlbSnFgFiBpg+VX5SpGfU59
lUuJru9CyiEO6QJKC2ghHiAW+BxiwPPVkP9gNC1t6d3/1Pn+xOML2xd5wpuEgOTxDruuZH5S6YJQ
J2lAKt4CAmHt/1z/1Go+VDB4sABfY6VH78SjIzE9SoVvc9HoQ65n+v6uWR1EJSK/1eQcK/hou6g/
fbVW28+gb6MHqjA4HogX08adszpMIOW+q/poY8Py3rKyx3NN6WqFoSs9dZeoDGo5OlZh8GgVA1Go
5SN4wFa1YS874atjLD6M5jG1I+asUiub+psakvYr4j1rPt69exDwE1+I+xRKlaJN6Ao4MM0nJTuC
+lBM+SlJXPDizCnKXrU58FZ5B8X9ZOK+xQ5O3oyB4/Z4RswYCvFLqjACE3RtyHHie6oTcdeLrYDO
Nd23KDMk5g+5OZh+aV9nnJW67ZkgXmpCMwLDbXkAinkn65vbYjCAZAkEVlhXu3+7V/Ne53ce9cXH
JPm4OuWtviqlq+EC/7oQ0JkoHSgTNinzA0fiwQ/y0VuGQ/wLUztXEf3zvblzhAcj5wHpS2zUEE2J
KIbuDQ4lur0Cf4ZM+386enqf7457ka7li9L+gW4KpwAL9JlplLBVO0VcxHVw/eXJzhWfhknzSd9Q
Dolm7xID4lXgp84s85UbBAwGU4Kli9xZ0cpiJuBb7FiMHxillRoxFEOT+55lSuHkN4lvENJZvwyz
AsZAvNDRwO694uWwOvZnP3lgSDG5jWmsnh6hmVheCKAQ2nwCmQ/wrADeAeI09eX7sN9bP+xFWqga
dM79GpWBhEfveVhNWfN0YDy0ZKU9WzUEIBz1Cwf/KEVvR8yeKPBfn2pwNCJPuV0YvySX5qIUbcFN
WZf8dZKgE0EoYrXqKEpJa8rS29e/VIf6NQdkNYPGFmdtUd+ZQnsfccWIh5MqvKa3eAOgr5eZ0csf
OnZNbfKiJWcoS/PN9BLdwLlZ7+CkhIx/n+M6hcr5VaAm2MSG5/AntPj+vXQJAeEx50pFJ11xqwRd
alCNTKYV4zpbBCvaQjJQkaQCVlMzZjvjJZcrOyL7PqXCmXm5AZYQ0A0OqxAfaZ2tAh6SNzEBEDVz
h/XRAE9px+aDsoxMr23rLcKKUbNj35p00ZTMGBIXqB/iMahAza1j4ir0YvdpRSCWFH6fNlZIL4lI
xpKG9Re831EyGKBEEoiW+I797BxNZly4cEFR4SVmhObLhaXR8o8lO1pHmPgSNI9MlahJFQFb4bHm
6yL5gSGA6T9Dj5jiYbgl0Ssx1Hgt+v0NjUom7L4aU6O6IGwNweWFmPjt213aLh00yUxYEJsBHn3X
ZKIIdBA5R68xQVrte+cjFHIvOBRiMiNcoUHDZCh46h6CWjFQSxeJoTh26LxzzvXrjgWvB+ICk/pG
AYKYmzwiuYespcW8Ua0xvh0fNNNw9ncJm5Iw2B4XL5Pedgb07wpBpjEZ7W0cGDcz6ql8OCAF01oq
ZZ/BNpl1ib8iT7nex9NvrJh9OHpX/RPsPxyKBwO9SyAG1Ibj1UMS54EfURv2uXUXjT4P0nRg7XKz
FOs0QH9driC4Veej+FCTN9/iiP4YKrJlRBTxZNC+ygOmpSRwZpiXnO15zel7e1fnpA2vU+91O0Uh
NkxYOvaFk1+guf/pwkMZpH05FlJ8sFsD2KeCji9yAAE4tdNTr/is/4ARqucqSNsoceoGgE9gbMDQ
gpEhHVKlazmbWS+bDhV6jojkMuNtTPrLMy3pgQ79dkNsJVdcoBAZUO10yHJQR1kXc2z83qa7Y5+v
RE3EFguWu8V5b0AxjSnQnIKqg9dM92AdA7N97LqVow9JzfSDFhBfX1XO8bc4wngGqMLCsECxRew1
0WoOvxdulPcAzi3s8GNC4DsrF2crLPZbuub2Yo5MQIYZBeEtB0UAJzHrfT7PBVulApL2WJC7SxZz
tTY5bRyqGgxRaNKOSZgFiOOBsLTqPpIGBTtADkeBSBvtYWOLM15D0krgWswHRkaGmMt3tFQZnlpa
eib1utAqlEVtO6b6HYRoPVA2+WTazb1l6nuWXZshlxpoUjwEfuW1w+3kyAWSQYc4mE5b5ty/htvL
fiVhemXlcVbgvULpK0u/iJ7i4lSqeVQJxKPLiV76QN9adzfEhe0fu4088BmIGu19GdZB913vRHYR
UhKLZwtY89FlXTuDGBYe8YcPiXJkS+KC34HfEht8s2HqYoLCh95IQXZxRrJzNyBVg5z1RSzbVAM4
w1+cYQatgmL7ECWpTshvMWvPXqODkEU95fp0mL8OrFeSiKZTfcGZngpa9GeEPN1YRQqywogdV/JM
W4ECpgAZ8oF6Bqx22sq7mnGwNFOWfNHmz/hu7XqtjoOFYHmyzj2ab5RtqFEAtyKiqmUqRsy4fjR6
ApWxhvnJ89BFsgUsHQon5AchEkW5QKNJdojepck8hC6HfhySZWA02LmqcuMEdNsrQdaiXgahK/J/
DmtnafGLD4FYhqapYqK/mSyacgbafu8DhkgZITml2CBKnoUPhtqstdD+DM1aQ+8dU+MCddcqKog2
Rpo/VwfkIPbySENL4ycb1Qv1FSpT0MxVyp74yVwSDHMcibMC8TpmfuJ0dX9VYu6ncn6BW4gFiObv
c1djLuWBIhDPwaqC5+jkjeMy08WjNQUqBH+5ZMUAHFGQ/1P3q/FMcLv5Od5zOdBrScY9A/vg2iUK
hRl45hA0YI596aDrFZafIz4gLQMV8ytWb23I55Y+wZeQxT0p8uQ50zlye9ChZJJ6ZsmDVcP56sLD
Zb/I9YTXiRxz1lYdXMctqsKNczBRRXSt6olC+bA+KQ9Ey6gLq720vMbp/C8q1tmZwy6zyP94DrV5
xt2nmthOfBlFnh/APgjrK8FT2VWcKTolkHRZwGTWQOIZn3DpRvzs4vuAlmO1wGCsmAhNRnMDLlIu
unMutxDaWYanOI8W652G+HaeVN4Ly/QOUaqpaq8Ze+S+gbRPDjB9jZjQIR706HjAl9Bjkv+ZatGh
2a0eXK1sOrrieMLmznp0LwjBwxa5gqeNjSJfj3DBtCSiU6ysl5cqBImH+AOxMCL6/8LVvpQPrJcD
kCBfMoj6lxO+tguw0p1rtE8JBXNkcOgosDVOeoVpb/S/nmFCL1NJrSTUKQECWKyFFxUs/ubXENPw
Hqy+PxWxcA9VcC3ryGL4WVTZAHrCApDsy+m1wPfYAh39hQRVsova3vtEZsHqkFCz2uYoXYtubGEo
Xc6XTBIifKQWYeNwEO3QCfC7XLxeQZrKzqN4UI1K8yoBPapsksZuVM5mK2iZiXDsJ7tEhz0LINUA
0bzZP6B2NbyqHi4wsW3NiIH38VpN8uFhvdD6s8j5pNcp6QGVEJ1+K+mkj9evTJkM4fg75E/lX3jA
LUxohfuHeZo9iiVmFiq/xSyzn52aWgeG/NY7oletET/fPwBqZnvg5DMpahjy5Okp3d2l5wCbRRtL
lyElp0BWe8JG6YqKGgidY+RRshaJfoLX5OB7a59ngPxyFFdV5wVUqIEo7HLopj6s5D0wjU+dFPV2
THkIqelNlqYk2GioTKZkcefWEeVYxjJ2lLo72dIC1SVnNOuSKn9RZ+TWqjQmEEEGXdeMSI+t/ecf
aKk3JzFmtbqHbXwWi3Bfzb5sTXCv4/fe+D69bQGxkdDRIXKvcroA50fxHABr8uJs2H5In68x0/hu
E3P22jUhnedJD2huhI+n1JxcDOR4pMsU3nM4iNnDhEpGdlUDQVTs9UPuTqZcvXCZbK70RvMn6V61
IEg7fhmZwusg5mlfNlKUeTab0ilK3D3NTBu6j+cUXU4GKexFQR3+p0TRvYMPjTYSyVcUpxW6wxc3
0jS6PT6nfFqQdG679TkX+PYUAa9E87KJdqbor9eIAPV9RpeDhdttkcugD4B5QW3+rbDJJakR0fhk
KQt1tcmOjzec1uTLMMeU4hH6naExJR4FPwJPvRPMDpckXYm9y2ysmINCEUisEVCC/vfXhDYs7B3+
h1ZKM+hWMscj865mvRtFts6XlGA0EW3pQKu8dzA+zV79s5Vu1nx0CXodtDhkH6a1pjthqTv84xXG
dkS8pDY4C5czgmq5hvS4gJnhfwVzJNOfsNUrc+XbPAweMI2VWU9x8DaHXf11iiKTvpJN9r+SDPwz
evggchfaPvRv+s1iiMDprPIvP/KhbKQcrxW7IUQl0g6kpc2zFlFwmhlS5eX+CY16J0BTtPsGzTPC
ZhdFkeg/T0ZvORY+YMbNtV1bslusqg+QGi4cxCq26Vaan+EMlny/fIFGo/HR04np3LyeHSfmgiZM
wMfU8UHRlba3h6c3DrKebBgLYC5wSRRfm+HyLLQ/E4fMRdut0XOIEmr5o+LVEF4dJkda5QVvutVN
r5wIHN5D+io4lnldSr2asaPeQTBn3JLTkLC29i1R2U0cQg8Nfhn5nXL0Ea3TxZQNgxOhhUvBOYDA
AoQbgwct/6ayQvp56YQGvs4n9gRIaiqglSa5OLPqLekZfkkYwfbT8FruXnwRMRu/fBUVoqNiW+8C
ZxvhP3ejSo1JU1TcabFyMkg+8JhU6/seH6B6NFqR1cbknayjypTksp4GtJzewf8kQpvXcGXAg7tb
FWvgMd9yuqa1XlB4FWo7N+6IBPhTWe4v8B9OYlaEJoHE9G4PziebDqpRtCS8H9NWhj7Y82JbXwCu
iF6l8MG8iNQMiWT1tyurYLBzarwIw8zD5WNSGiunva2TnAYmNipadcveJYyEseAMKQcxu2nydEaU
TpN3O3kP/cAO/S/fn+AL8wWswbmne6PcDatoXbXyIfOmE2ZDYET2o7H0ftAgh0IEXS/0vFZMLP++
XMTLmdHD4ub/F0S1vAJK/hSmyFfB1FLkqN2Jm6E/I9VhMJ4awHJ0IWkng9Imk18u3A6LYAxUUJ5u
MVP2kgi9rStdI7wQJ2+3DUvFIajlYQLSh2u6diWoA5lguU4c+Nr4y/1AIGtWfpUe45Lau010fvqP
h5RfSqislVN8rGsOFc/s9GFhUgxlNC5yui848E3068GhrHoSyG0DWav6ULpPgW0Vzx4u3Um6q3v/
wbPKzxbsxd6igfy4lG0uXEVQG4Pq2nnhxYFgeT0QmejjmKwnM4EfuHCGLDewyvwFn8CSKHi6Rveb
1yN/S3Wl3cGETHlGKRGf0TGMnKk0pOVtM7zgCyITbJY1jQwnEEqSXWZnpVH28tPzqjJQbjBHOz/G
mzd7e/9nMiGFLSWwnh0kEv/0lOAsRX59VTC7DZh0vEXdFXDn/UXcBuQYpJ7WevoEW5CP2miTs71G
QefhLdrSViVDBXa0wx4rKUAE8pWp1Xh+OJGjG0vAHv2B8Ud177YKSF11PRoPiT83Zwi8F/EZo7pI
VYF8hHGp4irnt2hVMJ7WzMzX173Gy7SCkN4c33K9knFOxrFVRl/ikaJwRTi+xFvD6kdvDosWBqYn
JXTj6q8gPqjUdpa1JyXEMTpQUTpdPj3m+2DqMP/SEmuF5IN4baNte2gh8DKmdgseqPw3ImOnoCGh
eYf54cwZEs43ekA8c3Zff5KiyR1qgxbgvUzpCYaQJueSUgmNMddXJgv+VrPBzbbv2vbkNVhniL6x
kn4pDh76uwU2NXBMIvBp+RyXO4HvHzxH5AVbzlXM/M9CcR1/qaVDYJvsALsZO9reLdNBNuLDr1lc
tQ9Tni0yJrcXFb93AM79DtUaNqy2jN4TCCu1yrZd8vAsUuke9Qj/Pezx8+zrWaXIrxFDzMMhMt1k
GKyRV9eCC6bKzPvAVmybRW10i6QxizDZ52Cvr+CA7t5ZHISE30umIixNpvodHgkLmix390h14wc3
Ps/D+QMU0i++LOmGnCISdG4gwbMN0GoMJeO38/jWXupK/xaCa8T6XaKY4dbgZZ3QWjzjY3UqX5vO
N33MBHNWa/wEmJcskXbQStRkCxIeYl00fHiZlMUUcx6kAasQdPPLb5HmMPlG+cWPJWZXQJOfepA6
oGGXaAzYtvGG7EYrOXaVxWEhBnKW3iPP3vNbBmPHjhNv6PwNeySO/Zn42NKxmYYA25Su6SGzXYcJ
NxUqZBZ8XBbOSZpWCUq56eqnfV/JuJhprILXiOLtgLxHrSAVs/lQbR6urZyp1pjHQlLmMTqP0Qmh
LJOtCgd06eKZ7V07IecGfzSuwl0c5Gwc848OyDUoxC8K6c8JyrxclLpWnNI2p6mq+dx5tM3QdJI9
fNPTnstJ3JC+TsNpCiyGrmMk/NcGActUH8RM0ucF/ohCVZg9DwKGGsN8pXAMbhVgMw3VkQNm927T
00UOkkQ162qb7+0OjM1uMq3UpaxurzrCzRGmuAr40ydK9C4o2OGBpeNCI6zYE5Qn6w0JunUDtGo8
h6RgPn0Ke2o8paU6QBKNLq704ris66T4xSjIgORiru82C/Qt+YDsfvEKZQJSce5Huzqt7O5LBv1E
KhbVPP5eNJOyX5k2dLlQMpas5dQPHrx0nG5S5yhNTfM35OnDI7ZfMqkAtlOE0+vf3vVQPlYrhFbg
j7jg/Ykd3RwIG95I4exD+/+vAilfyZPAFlJ0r6UjryO3zLO4ubh7Bi/7BzlkUFOFshLY/t2Prw1v
hJ4iTKKoiiKQZtHztxOJuaZq8DtnX8Eq0/h1NF4gC1IKtMcupLRV+yQ6HKfnxHVf1M0juBG72U0B
VTCPjX/uHeajd/jED/R/Xv8LETfNvBjwkWumEjBduLLA55i7tEMcpj/5p+PIHu4ED9/tK737ojgo
tBSCRty7wQwVvryy25eg1JaGH0QJQ+0yuue4q1xpm9MXSHshhVsdi2F/GvhqW4OxRfqNulAty6tx
TLUlL0VFSWb9DrCIv9GuGZBx7C9maJTcMu/TKiV0TGFceWeXokCPGItclW5JYsJoLySDmLyx6ZJ0
B9mjGH9l0k5SwDnz49BNqriNQGHNMNfwzYyQM1uQvVnE1plAeu3Arlbb31Rt3N0O90RiwSNJQOSo
zI6Gk22A/2lm9MfCGny6VygSH4TlzLu0PIV6ucAT5UOlPZ+01q/jeX23BDV0sHiXl2V5zpK1n50K
ptfCMG+JHjU9wOV5hOs72zmloez97tbIIhc7lZLGkJXBd722twfN+7C0xEcbBMhwhS1gqiz9kQ0O
jR+NebEHp2SUCybkZqppqQBORDHUNyXqCrYYAR4u0picgxUePqXmSUc6gRbDpWY0oaqT/q0vzZ9M
udkNqxlbqCkETzKl2wgu5XR1EpOPJopGVsupbrTC59994CxTMlTBey4TS5M7Wj0Q2c5gALGfI1Xe
TJS22g4ZAcvEyQk52YDxWWqyRo9UYYCF4Oc+x7rP/uImcb5paEaaO298vCp/dUilUfINBpfqnXYy
bkqiXathq32ttcnMuDaazlqxP9oOZlZvRn8Pfs9jnxZM1QcyulLdvoxTJSnlULkv38j6zcuQgNkV
+hh0490RMNu4n1B9rx2eHtsFIvijySl8IkGDaVVar2oTVVTvr039VElTbiOqY7ybBM1iMzeUtuQV
APnb3Ioe9lVfrdmQ/JzDVEd7a7+2BGiEoQYGWeVyS/MQPM3wTezXNZBdwpVuy4ki946/TA8mrMLo
K2U03IJokDCIje2jGh9MDHgwfKYoNNvy8ct91b5hfPKla0/IMfhjCuOWzwlrrVxHWEpTwbeIoaj0
/ojlSpKB67CZZmycLqsLw5aW+mK0GDf1wmxd3Ji6kr1cHs8zyrqYSdXgKPP1vT8qForMKmbJ8MY4
pKfydkAJGuBhw/yGqapkM8AxXevteIVXNt4dWBzn0z7V0Rif4WAdRlJ6Z11VFqGEp7U2dK2E181U
u3nFeWPSSbU3nb8ae71GJKNHb81f4zqOJevdIjjxipRASGkXLDOrM7WVO3pLT1PCXCg2cuBQA+rw
utUDFb3ol4VeqyIN+qoW3SoYONP+w1qasbMZxyW9LPDjamS4ymBx/1aMkX38k8CFjYxGq9qQdk1s
d9tysEOEf+O4bhZXoXqtw+SCLiHZXv0ESMH7/fPhO7RuvztlTBz2KAgxMOHHppL5cv9BWPf14UWb
mTGOH+VsWsDTRCpVu57oH0Dd+fsm+9itSmeTEce/rxrSI1FLv+wSXU0AbL1GEsELVirMx7/oPMMX
6FcF4SRApPNZL5tDK69OE4o2az1m2pmIwIeXmR49DyEq5AldZsx5Z4lfJNudCo7mp1gdg1ze2qUw
tqhT5+oYhXso6HGs1XcCoCQa/cEyS81tD4tIaKSDqtg24Z7y4tyItL21WWQsVp53cXvU8b8bMiyp
VUq4GPFG18bTWN+vRsWfOurhLw01Lm+yk6sNTAPyIWdnXcCSyyOzmwLJEtXN1UbSC55U+F357rge
fzkNDBUNgnSYpQ85IDQuwxarBvSHDH1E0xzX3F2jr81cshJzuEVAGWTDadTMtrW6J86ILeZ2f6Vr
2LqazkrQEF+zPiGY+ONtNLvAQN0LUkZBpjJeCkgUQLFb8w+kynlWMS0dK/sdGnj3GwuiwQRZP1Jq
N10M1wlQZAUHJWqal8Ehfg/OvOkFyPzZybY/NOOM2D4H4BBE4rBIquVsjjA7GsAL+uIszUzVr+0r
E9A5d70nEGlMWd895xyDOdwIfauQUvqOFhESu0Fg/6IBh6Qn7TyvYnXJfDbWX3EA/vhnE1o5Aj9M
s4QHtx5RBWmOeSp5frqztkaxXs9lGvcuthed0rFgLiXB1eEKiMe5wPSAUDjGfZCnkv3m344EoDK3
/3kjV4m80sMT+Wv2S78DAt54imBBmw0mLiWe7Z7omv3CF2F4RAUJnNTXPKptFoVn4rPvjZSe5YAZ
fCDaPOGPPY+//o9fvOtAYGyl44RTcGxGCldspmSIwRU1OtVaEtHyICmet48NxMHP/JI3HQaiQGN+
uRRyZXLJpwpIr9MojdE6rcNjeSmp1MAsBVcwLI7ylh4hu+PT/CnHS2p81ROqGJpm3DBb+VzG8X+H
U0f4qDcSDj95zX+QF8bUCHS3rpq+xdzdRXfBKsPatd5N832+gP6Gj7EoBPsPFy5kKqhDjtEXT0p+
u5b5eaL2rgw0t6wz0OGjWGugZxXpYfULQqckUZBWgcHHc8UAtvFxNhxUJeZQJlQEWQkeCRCEu5P4
jI0jQQjMouN3b/UlV46vbbjItYzKlYB3jliP5vTpIo6/rpfuxSdGMZB37B0rAUYUci4dbQjSJSkO
sF1aRcaFNRPxu6mF8NnH99yUaySnHN07MWAyrT3Ewc02O3MG+L/MNtzIdIiqn/oShqCuwmAelleR
z3+K8yYQdpGizR9t67vfl6pLrB2s+sASI8B1aH0p1E/QWbncZ6DLacg8nw1wRISOtSbt4wBzT8cS
hHzym+ADp3aaHx1ETx9cKFBO7wfJkxNOlzVF/hqZdGypzoBjaorIM/f80ptzPIyJHsd+HWt+u+hI
I00cD/EMpZX3SQGFm8xr1OfYeXPZL6D9u5nSdGTBIbsunWpkgdU8+6ZE2b/7NUd099vEW1/GWG7d
3y9xNQGeFxbvZKbFL5CWabk896p3EZQGY1eHduYEEiW2J3P/YOe8Suy+JKusV+3s2AEM1CSPYtA5
psMa3Gp1meUT4ZC4BonY3wmoj3ikYOj0GkaswGVnpU8Iub9BeiZt0UNr4/PPY8W9RwhaJHxUbi0G
qNh0K+DxT9PNEWcq+nq5NMq472sTbTROSG5zCweIZONdvNL19D4EzRNafh3Q7d4idV30u+tpX+pO
HJOcN3hbANLCl86oIEwccR38eeWyCiLKUn2JtKjriozP/JS7NROPnJDP2ZOEsDAnDPca6mrX2N0s
uXQoNOEuEoOZa6HRzcfAJXvqG/BsUBYq5GSl9OIi1HrlzGaHr9OJCkp/dBfAIlxiaW2ptWfArsyi
VnZj3pdV6JgFuk3uksGIGzHtOO4YHsCjuMeLYIbnn2FtrXQnMAHr5bZvOGvByK5iZVbXKkUQmXgu
e5DgPDhOXIAhDVOg9CkGBEnEAMPlsipM9mm7R2TE9P+FyMue2zYZo6Yc6HrL3urTcwdNTTQa41R9
QbzSK2yoV/kTTKcYqwGUk2SdsgiAd1uIRn4g5owwgPSDMI0GIOVaHgEve+FZ4qfHINjFMii2PA1q
Hx57f1ic7z+AQsGBWnr9wIMdIuYvF0xPE4oXUUJUiCEYBe7d1v7ezmNKUdr+l6DNviPd0cYSO+I5
zgBYWvemSEN/V5j4vA4Fxstw+4UFW6URFI8Y2ydL/0fjpe869bisK2U2dKd1m8OB1/+329+gLFhg
347NqRwbwvieesNfZhBxxzNCYLWWwCXdLDgxNlHzDsthwZmv1AmED9xnsBKI5ip6ef2BVxJWN0Go
Cu3lms32SZMDOm+ac0QsoVX6Zg4Loeu8RdeNYr72mPtm4ImjI5X+ltfbFgBZvqrVoGkx1u2fL8aQ
7oWsQdfTVHwq8zZj/GscnBplhD+aP7xjtcO0fDHFf06TVcR9nEtxSNqkPg14J+ysYfa9/lMkn7Le
SZgnhUQz7wCgi7oHjVwKWTwN6S8a5/5KDLKiXBXNSwBNC4RMapczuyl0uyGM+bRgPjRn5kMZ01l0
Ju2VtMkKmWDuSJeLHD9EgIBeHai05PZ+JOL3QUyvEn319wv+/uwl3aktbKLQp/hdCrFh3XrUIjBg
ZGlMRBrY/ZWIgjwf9KZ7z27Lw3q48oKRrzZJPI8x6xJgugJLfBDZkxy5wprc3uKXwV5x8EaciWuA
s0WzO+gxCAMGZFcDXjvDzSADHdsXO/F5z+kcXVPzsycXJbrX2zpRvL0x2xfZS3cSGxog+tenUgRm
tiBd3P5878BZvcPRimgNeT0W4ps/q1G1RyBTH10VXSh7iGvUImmr4AVA9ShrFiGO9tjo0D2koki0
BxXzivsaBdBPyJ3/sJFhfV3uvSv4y5L03WXZMk36+QB/dYx/55vCWcBcblKefeUx5gkPadnMsFw3
DJfHwaDLTdd2AwFjtpKY41NtAOnYu173CAfU0+lJhHR7QzRcI5NfDvMLWu946jEA7qZPzb81VHkJ
s/3BtRneblLCPorFSoXDbEEYl0DrWKYG9UDTJ/zL/gzjjMlFqLubcYwiTXelQvjZfwW3fxJIWzYX
mfdyl3RdxebF/dlr9Gkmy1P590SsSEQXsQxNpBS9Om+ef58nl/IePqfQzjmB9KIxwm5nNcZyyPBD
8ZzMaeNIHwjkDfjbZDHJuJ1X/NfiGGV+Awh/AMdBoHYhg0BTeQDkVYnIxO5aTYBoHTrkYI1/7zcW
Pn+B5Wn67KqUqPvfQ/A14yey27g7vp1JzO7Ktp5c1q8brF60TfgY6VQFyiRiUR03BTEYVlluUnCD
xIlrKrMEsTwMVlQ9z8UKyjFoYV5gWo8wea157NNkNUGZj4JIQTXu+CAJpwfjF87Aw2VA5qQ2Ih64
dFFTqHj+TG5QT+eEe4BrWlltl3uek6y/L9gqvhhU/s0pHNC2IDSGhmNyACpiGTKcypMYbJhTgRlp
X1OhotUUsGq92MqiwUT7fSPDMznMurE5yy3MCautGowg+n00TWigGwh+XW9aEoEORPM6PER2INaL
dnwqDy/OQElcs7fsB5UZJvNPUHBOlN9O5pIJx03HEizCb+LkNPN4vjRGCjpVzfpIiTYQd4/BodA9
dtf6NkfFn1Kxnq522gEQtR9kcf2ElQKaqvBHFSt8qajwXHzzxKiV+EHX3uAz0fdfrkf8CONqA56X
2CUUT38MzKus0kVbOcXD7R2jBkOVgUyPulPoH+OSx+Nd6hmfny89p6rKgmIVZHKhnvWwbYaR5gdt
yIN1mOuwc2XHTxExMYIttUurOxu5lXTZLcTt9azvMEgF+qgifkJZRQnK97BwMmEMuRQndK4UCPjr
HeTJ3xo1RDTsOcBPjyq1phSTuXK+1XuU/VdAfV6RQgThd4+wb2GwPppweUmmpgsLT376H9/hQYbV
o5Pb3Y7cdA54C+1dQQDyQmHmUyzM0yrZFAihUCr3MWBf5yIb3hKfkpIv4oumEFofAWbGizHPOaQK
7rOM1PHsiRmuRHP1YRn3lLdYnfIXRfZ1M3fFTTbSZP9lyu/w+BtlMNcTs9LQlEmq4hzIYVaCD/Vn
6Go25QwtokViVLyhrYUSHxfx1vyAkeT5GnNyQK6qqtfV7SXBd/VPvOLhKqWr+IpqmWxGG8VLITdi
4mODtEAv+OCzxHnh73XHoeqNAu56ynGgNRaGiHTTqbmdsHDmHDYfuuCbqxazxVvATdOZQAonNO/U
nRuqrFp3MDBVE78aSrkDi/pIK3m/qz7uP2rT83qHZtOyao4Q69HXPrmerNAckhkOqE9WiDC+8J2c
wvUNTSKhwSfKzbGgMR5rx36YK3/MVGVIt4NUHVlG28dAZg+iZSd9OJJy+MNP+kO+M40OHoaXAssx
q/E9//w1LZkNm9DASMYG5qeTAIm08QWYAOm7q3+UKifQOZqhyl26C2HSjabGQ9uxwGrKad3PRPmJ
/kYv0RTy4Ydzjovx+cS4q+uyR2yhXmagnQfus5EFjLNsjANFwwqFBFJWBx0wBInelrX5EJkJf/ht
RIHwfOhg3yLhbEYRuKHniy7ijBuganJUaZKyi2SP+EeyOxxjvpno5ym0Q/eM0MFwvSl/v5lURTAc
WKng07RzdGai9uEuSXHU4MCNOI94gtu5BnIfx/x1lBQCH+8h3mouM8UUQ3EiM72d6UNP01wOT1Nr
dXgjDWTL02zWyjZdYHN69LDpjNA8jG0w5/PsRfBN0zftWf75U0PtEwMa5+uzrR9T2Ghalmj3RmQy
X3oRHBjvBDFM01PYKKh7iA18TjwuH3EkKgmcPvyvybSayj5e+Z7HORjqVdp7MLdZp6HBvp0a8tFE
ZzMM7NbXTdxX97F81uZ5HUOKfkHfA3pUw1YyCv4fnhfdov055pytufrYQF/b3O3/X1Wb4d5AuQ5w
idOSOHRSU2AZxO984K5wgaWMFDG3EE9VJFntP4a9hCs2+WoXzrvnGKetGuafvlpMcrxCvJ1phy1o
9vNpbDgiVk5uLHzcXId7jkh68nFhpMJ1mfoTTv2hgmgfEWmTRN+1M2pCdZ52WNP4MJTk0zPGjaL1
vRH/2qWaZJVPkkI072iNrFqApul4qWoRnDuIEfqIsaBdCZlbNyhpN5i4flNyH4cacSMIEfcrpSYl
1cR3jk2pNn8a3ZEau7uYMJ7bcnqUtw08gAcTFyLSd3RA32oJkcl0tfdPYehFP7v9pnKMLW9w8c6D
/41LH5vHYGC5Iu5hn6CMsrrXfvQjChrVlv8Wqn+9d1r4QnOaKTGOZTKpvWwvQOfqre2/jkJThBj0
zIj0vElxs7MJZtU77RKGCorGhfZubTHayv874+xuyAzpbmt4UXB5Z7avaedRDfwS9Q1bWUKZfwAj
+9abBHsG+OH2eU3I4P5p3s474ZIZYBt3yocIxLoQUq1m5qgt1T3VyeAYRnWQ+ihGPKrY3DiCYKCn
n2ZbdlhdsXGbBNefW/zD++fSkWUgYW36kT/KSUeQzCZIR5weEA84LVDkeeJCwAB7/PqKOGs9uVc1
+Gkf9firgnMuLXngVoxXkfkZgRqjoK2spkD2VZE1uA9qrWGOYmoi40hxMZ19F/o+M7zdSy/Z9/8U
pZzCqcSGkLv9dJNbA2sbA33MmDgZbQ+/g3aIumN8EROH4fLAQaUZZVrAuZnyhlT36NBIe+WOs3K+
bjyLQVdtPFPu70ZlSDXFRa5b70ILpZWnb5o1340uY6og143sNGeLtxqxWF3flNklECoLbkE6xNPG
amAImBAzJH1pg57OwjKgclku4aQA6jX89qxWqJCYqaDDz3eEzRnQ1eHBwfC9Fgd2hZqMCI3mohDj
cdYxIF7Gd6wz94sa500thW36bDXXZIMZSdHVu68A/Eo080xaSvC376RKps13wubemNar0N4GKXcg
bJKu5OY8x8/CE8LgN9I/o9W8mx/hRUc7sTzwWZWYn+WQJoIX9idKD3y8wPgcku9sOW0ULtthiVqR
3RourJor1DDzXKXJp1yDldJpjK2ZSLYoC7wm9HyoiNl5piEHLYXwHNmpt6x6zhv66U28TkkrChoe
X7NDO7WjHyLYX4wVpGN0A5dmIxQXKACBhETzjgVS864Zd9olwjQD1OOz+iEGPKEKPl59cRsOrZ4E
4R3sxEZ0QpoKTR1FUrge/9od7nDzPiGs3akJ/eVerMd+hUQ/lTQ6IGbmuTVkQ+6dmc3GQn1rXp/e
TY7qkiPkuysXf51kUdg/Z7zpyT1XDm3QBkmiH+coPFMW5FXde9q9f30qtJGeUwhKnqqKyon8YFhJ
1DRzxLcczlLqCwW6q1y++hUOJMLW29zoWe/VtYHc9kdURuyTeeLWbTvVpg6fzl8mfLFzcIHV/BSX
6nODZE4VobW+QKBJv2MyClBxTbcINR3v0/BuT2bFFTHE2LZ0DUNNE2wo9O4Eu23XCp4CAgvwa4mr
JHsEsENV1i6nYhE+a4QXGtuKh7FnLAn1j9UiGdIEMBOTWngfXlkEsuhmOiG/qK1wQR3pWsek8Zel
2LFfarmWbF6stD89996bJRb+Nfu1WnWLdfv5Ju05TDkL5lSiByVaabikZfyTQh97NCKB3IFCxAlc
1JoCvpnnEVimeqUpvsUr/MANlPRUD0fILcT2tvPfxt0mVnWUInKA/rsHcteLnNjMh1hNgiogAP2L
Rw4PR7K83YyNY3aRusqwnFfxTLM2NQLrUqxE5JCTtN9O0kwcxT8WgCznfIwfvwZCUh06EOQFlm7R
Zgnx40diTlhBP2O5DAahJIwjC9qVFgTnmKT6rLHONOOTqU8mkXw/q34NhGfVuzMWF4fUvYDMR2w8
Yd1yTfFgAo4bP8ATwZJVbeKgLyX/91WJzorAAxP4RQdkS/NOtr5u3QALVoVdSmu+xgVQazJfP5xZ
8D+ZTlqCeZVSgeDsj4nWjFbb92+aK4MLUJOjbpbZ6dRp8z1egrT5pXkJYTzxzy5VpPxgXi8WqDAS
8h977f4FcU/DrE6I4/oGEPg9xGvGJ/+mERPWqH930gv4bi2qndam1NOar5xw+WtXm4TbEFTEXFFo
AXZ1RhRR3Tc6Yr3m+jr1yRg/31FXInKA15ggyikugHV1gEX/Gu5a/6vE1EZSjIdGZpJtoiw9vibv
wlfGhA0qC2zk/n66a9BA+zR31HZBMTTWDWNW0SdfopnM5AW8eKZumMTJp69AmUEQkjkAcLJ1izUt
ygdXwEz5UNIzRB53ocZacSaAH7IvuAMA2y7jnmz0s/6FEIteVPCW0pjz8ugAC6SEmvtIxUGooHpy
K/AUt6qP9S3RrX/FgB1+wU8ungiquXLMUyQINe1RSCE8g/Fz8xo/y1ckDehs9/zKYuA3m3YzR/bv
u90ypY3ca/f2ibYAMkWTg6lPN6H3EX/PHWfQf9OCwXBiqSHK4RQrgBIYo5H6bsPUHU124cNZlF/a
IJar2xEZlzeQn3eCouhwFMnMoO/J0nnplqQ/NEUNgVWU8QRecLIOEZ1RhFLRcHB7/iWHVTOlnpHE
QoOm5XDDffnpx+cFeROK3H3kNA7imS0+OcGTU0Y9kXmDdKhywoY9WXiUizq5wsQBnMSuRlgBOxlU
i74Ue3I5EFOLQxHvWVDQFbQ8gADziGZzjRPD7r4/6cwPp12RoGBoD10DmeSAT/xWPd7PGUZoxLnE
a//M6qTImmi90EzkxRrxc8X+0mZhSyCicMH6WQt9vc4a527cyBip7qMEuDQhFxMfalZan9Qctd3k
nKkelNGvWn8cKGj9szUoy+iEi0Ri3Ub6ihRdbqmgMcwjv4I/JJMPg2cazrklLs1xokzV7bg2N0Ca
5xKaQ4XAp+YEkDW4mwuzQTSYc5iMbOkjQa5awtyLWgeKSGmK/kiDjHCoqYrEoQHDOuecr2X0/Ql4
nL0stogepiFYkdUkJqPy8hkETZsFtP4FpGWZOMyFaH5cFbEzV0pTUlwbxQ2xwzdgXQSPn7jCD0/p
On/z0PKocy9ZjvVIKA19VBIjfBg4kbCnn8D55fmjuNKKb7BdweIJPsvvfxBda2FjT6LQlGKGakS0
dBQ7ZiYQSxVQXG0wIsjcBbQa1pz6Bos7UsW3t5jGDLc9BAfUHmcH4+oAIgP/mmQ74jjMUPwnCdlY
HNQr3mlcsoxPeh1JYCL3CmT9/04PeyMB45jgUgL/Bg/QMRfLfTRWPj9d50dvD5YAy66+Nc5zJyeL
Y0UlCsk8rMguOkGdm/8Q9CpVThO+65bk5d4MTSoVOn5YAZ2nbd499FucCrGDxeV1p0aakfYXXkA3
8wyUzvfQzLzhPBFTu3Zta4Bd64gqE4fLmkWvYZpC6AkpDauxkw4X5UUcEbEosyOOEa62e1IVLlBI
x9gfEU9gnjidZ9RMcElnsdUY520BGV+62IrXJJQrQ1jj/oMzhi8wskalBb0zYOxCze8LQ94mctxm
5JrKhgizg6KmakOF1wfRSimwjxllbj00idz/NJSWJI1z6GA0ie+OIjHkN0kNa9X/BYueADO2Dwuq
4/bFdU/3h+PmvAcBRxascfXP8W3c853vJSvGV0hN7qtPrzbR6PBCZRwUzKToL6g++sg/2hcbk/Fn
ZkK3cHYXwp/OnU2dZ1zD+dsuBDhL45uLaD+0bGWOiET2WjRSJrOrNNTLFiZO5hfcuJAYsXWTzH6h
PckwliANHeKBVaamH+MhJTuge8sdiuznmLtGElEpjvLNRsQC0wVgYl7btT3PVg23rwXGLkD0/buG
u3xGcfXHuyRu/2GcClZNb6ejmf6aHdf+gamD/Z7kQA7ElbpNl1/sw4tXAD1tkUM03Z07dlkZE5Af
/l+h+B5KxrSy7iJyOvJ7PskWXIwppyPH3RahgTPF6gX2I2OPwT21nPLsYABS3g2mk65HIAs+S0z9
GNvLcPBBgm2UfUmzjq98AbusPgAqMn4xEQ0/bzJ+fafKSshYt5uKyYzgxi0s7Fn6+upqrWNGXWQs
J1LUc+J+0Fj+eMIq9VFlwSOR6AnlYeP4OYgTmWVhG5TXC+a+sj5YkoQbHCNBxpdBrAWXduRq1gSk
w5DjouWXDV7TErrdiHLGFFpoV5dXa9S53NoZJUvCX37klOGu50kRZZdiS2GElbWdAwuIgPJE8E/R
qE4+uFfdqfJivl00c+Gv004fWZo/dkwoV9kBEe/vkhpFCSCGtMmWdYO+FCFokyAz1L2Kwn4dBh4x
Jz/CI62MRzVMub6RzAm3xD5j6ypcErIl+d5szyL8enupRxx1Q66yAkzwq1+mq4enSRC18s8MVXqc
AmiHsNW69upS/JK/o2Lws9FCWklZmBugC3anxe3Cd2liOe+nx/M9fEc0rUw9/yni9b9ifHTSiUF8
j5QjbicR/JhAF6M+xPvaKoX2zhFvQdxLrRdARyzlLfQxk0h7JhHAqqoI+DqeqXYwMfrl73boBWLm
jYNvbY+ELpKRHX7hrciiobUgudzQS3UeGkRsZA0cG/TBwASRGQ/su17PvTiNx6kIDZOUajGJ17dP
zfTD1bZlOFYZ9aSlzwZK6gf4oC9+dp++DE9BdMJzoX4LanR1su5n2Yjqc1fJ6hl0LZXLHHc8Zlqw
t4Kh2mkWAzV+EI9apf73rgDGWC+ISXrTMu1EHa9Xg31nrL+25nwxEdhWgPOOziI3b0iYljCGqMmE
wS5odPr20aI/s+pdHqD5Lvr3fztbx12wJJ/aIK6VB72KrEXxz7F+NZJgMqYxJ0/Wiah7O8MPtlqe
GaXjI2J1MMB2gxtYOuaM3EQUR/fLfFUbh1WrwdMg8oLpMiT6Wi8tj7kfLYxYdsl8HW072PLh6jtf
69JrP8MJZiZrWjwmOAwwKNPdjZXDYlzAMLa1xFhAf5vC3F9XmHbDpSFFo15/MqASe0RKZqYurJio
h3Jlpbs3ogRUfXkQrP8yeq2rsI+p2263dVPhqsaTGOaHRjTt5vrsOOOdvlIzp1NCPm5yb9rEYX//
m1fzUtpeyKpo6YDFsdXAPNfQsIFKp34uRyCPafDSNj02LS+Va1IxHNN8JYMKpuTciHUSlrpibqGl
nLyVZ4n4duzAcRZk0jmuKCVUdR+Jy/vGklvBQibPniXOZMrvp4Eaco5VY/rDn3pDqBX7B+JfP43x
XLj3LRrVmElW9aN1J6FT3PutfNkmUQLJZwJ2OpBWIqDT3oXkv2tIS3UNZZxVQkpQ7KUYpRxiqy8z
DkrJhSuf35B5xpm3DghH0RfLOlmcGBl+G2trfYAusD4S6vX6JUBWJJAp9auuRwOF/3wuPzNIhl8X
nkXgPMOP/kQ5OgwUFivsMYF4mz/Z6J9OW3tHi76L2luzOkJyJutPX/JxMv71je2LVg8iBjfcTI5D
cf1J8k8MCkm1kS7b56eUQ6y1BHMbz5Oke9GRDpAMsomP/G7pey02SsYnzrtpt68qsONKi5Q6eeTE
CaValiHtYgSW1yQ0XR9mWLVLtvQyhZNbtDQZgE/Kh1NJSen2eOHCXvnYwDJR+DTCQANmimNtePYN
P0R7nM4ODb03xbBrVO8KuE/lBHGhpD7JH8KCOuVZSkQrpCa1N0KX358f3XyDsAsU5YZRcIjQwz5H
cKGgDkc6mSQv+DwZD3L8zmboBpopt/NVjR07+nshA0b1vb2u9ELFIOB0gTNglKtWxWLoiutokebl
HmPNYANZby0H1y1nnLZaP3SX7V9dA8O84XTYkuKpPlqtKC5999q2AdohbK8+WyD4IcNF/fLZ6OWk
/axc+kC4gbhocLNaHvmKCXw/EpDNH2/8wWaeUWcquZ2UVnDcT2Oov4QiJxGx15kUgzUvWcKaEQFT
sA8+pR22EJHDRaIWTkb0i9ZjUuu8U1bSekjKv3+Hs48LFOvS+K2YGYWq2JAVbj5RLsAgnGElc9fM
hT/k9dAc/Je8jFRc5xgBQZrj0jyO2cuFh8pvCunc5n73exAiz3k/f+S/mQ3fSZExYH9MoqNL/6UM
apngom13ujEMOjhje20dIWR/ymQPhSF37viPI8+RVuDojPozWtQ4Hf2IOP2vBqZTUJ//YR/koLMO
Y8hKatrTca6xy/rA5bQf58G9AMsGmIqnKpKZFawfRqqm1kZuWIh7iYPkd9DlDws3Msq9f+OzRUG7
Kbe91QJaSolvqqgsjMnlr2vnLLs568KlX1sip9TRd2sUDEExYkh9xKqOt3+wCrrTVzuCXzoaZeyg
qR80sCj0iDvTW6eybps0CsL4UrSUOBbg1Doz+WAbvaOi0ZJvWibft7hSSXPUOjkg4K8SXbUsl5Eh
5GvgpASG7q5lJ70Y6mCzaZPbkk2Q5nSwVy6xk8+6WUGz6ErgAJjDi3Jix8XMIDnm5Ybaw/yYFop0
MyfK5ttoL6LGYnuGXjfMd5zffEiFGgbBAKEzdby4qMtxTvA99bmZPf8TGamJ4/dPW9xeREbf73Zt
poD4GB7bRy5vIB9LQ4UmHnb2cR6yrbgqY3WDDmJiDUc9NrHI1FEne9SNKcg5fxJ3KA0UVVKP7ZPw
FtOt4UZlMpNrMhGeA3El/CdOBq383Aln8ua8lvoTo77/c1w+P39iLKbNoZPBWrz3AlBL/m8UKybH
QnjhTAbqJfCDr4pPbY802k/f/52aZKmD+r784KPUY8uX/Mod5YUcU9lv9Z1gUpH6YSqjnGevOH60
EeyM86Ccnq4d+WmsO8yY2f5frKYvI2iwY1MsDx9kAG6WydFoVTMUyNqyQtuYesMtuDStGLrxU6L6
4tjdqKgMZVWIXScDcvBqOeQJmNjh95a9wn4FnnqHuJVOTokntAxiKtZkcgcqDE5BpRkFniuQyJP8
RGQfXX2HLL2J15iMRXMn5QNbFVUfQDlD8YpNFBPmPsi+rEjCPXlegL38VNr5IcTFRG+xt0ldj/G8
I2BBt3ytCgevmKC2WXpGI7oJ/47x33eNMiT3+SIGR3Umxqem7LAYrk7y4PKQ15mEZ5Zgzn8Ub2PT
KwCzLHSse2CChylHfZ3fsHeOycSpz8YqfFZNLXo6cLWE1R/jlg8tbdGuYhw4URfTu/OC43o+Y/OJ
Bjf6wQ0uOO9K0BS3e8R7HzNu+Hj47PBHOk66Let6ndmvFUXSrIFon7aITSkKZYf8fzAXNG0ka0Ye
gAD3TvNX1pdbivdY5tPiybU42Q5KbQN7Lzb3ocIyVT2v0wBSwefwaKbbb8Cqh/esZw99ATDG4+tO
FoOocPZ+p6Xf60qeMoUkV9rtKw7gs3zSw9FMClBwH+7sBAqzr4f1Z6RwSyQWBQCH4F/RCKdWOg1t
mPa5UudbTwdi6U//iS98nByuFMOotHXOeUKa9J6GbZ+p/ikkk0lhjYreGSWy7cmLfQ+5apMojbgj
ltHrVsM5xLzfXyIhjIBoJIZCiET/lGDhzX9XoD5xtLA0XLwDoOb48XdfWRDU0bOZeSrcnTioLek3
IT2Dwe9KHiyCvQLD5geyd4764VG0cDYVPEwJKsxAcmlWBtaOdfv61fs7gLeGUqToumyHO4cp+kPv
lVaQB3r5o041xHR7X37x9/UBEBcluorRWEbmzA/CMG0L0/88O6WQ2sSJttgouUmQW1XCzMsY+OKg
MdLIxuwHQbf3OdOwtG21EdGE4c4VrXeOqV6T1DZlsAquDC3kZfgXB3+27YshBN3brWoWAjhHjwIL
+gJGkSb+umkiUiUamVbyLNdg73Wtfm/VMrJKYaY5Fd1WzG9YMxxGryXyLHlmgMr0jClCZ7qAeZU7
CDnBPWxAAIcalVuYnmL/BgKeoK71p4LSeq3tcDk7i7bttR13kmmS5kfpw+KESeUbAgpv8eEpV7zd
c1CYiostvUx5LW2amc2Vdnv/dHJiNqv/GhUrfGmXf6s84JWv6f+2/t5N1v38RFTcYUQ/4YPH9k3e
fbk2jzpU6qY4MW0vXauNxzC/OSl6XzyUOxGgn/qiTuI7/hvfIa4hSnNffKQ92pA9LXnN92fV5nhJ
27DajwAw83p8V42Su85O8i8q1mh2n8lRZ/K7UFcB238zbDbwyRkT1FgQh1gvquKQHfFia3n+GAsl
WZKOfd7qQSfq8pzVl5ARESNZVKliT56ptJW8WnGhItPIklPGpROGpq4jenTIZjw6BMa+eZx4EXbt
xn31mbAbBWDrwDbVyIUrkUDmeNo1VAEl9jZJDDNtuZp159O7yaNGE2fzC1v/ge5MyHV633w0yrth
qD/KsFewNj0j7VYXDkoeiJc+P7mkawoGrHUquQNfo7C7+0v5XyAaCyA8VI47YMaDo+Ad25LzuFCe
B2BA+FeLi7/5ZcnqDGom/r3svMtuZy40As7VxzTv9ZqogRTXhitLyPbcLOxrh42mJMUC+GevFfeY
hzBUxIXr9KDXbWNPk9ZLXnQJK4IHWbk7oGQm2wkYIsWT3O17usWCG3KdVnI7WRhGjuOK70Uw+Yyb
hN8wLcEiQX5iaXMTgEYN5oh9OAd1e40Jbm/7VftNt/Fmw6mktqBWt3zJO8XySEqJl5cNSD7xWiKf
Z9KQXS+SNssIQh+YrLYRG6/PI+rx5OVa8fpp6AGFFknvhLKzO5V/ouVD2pqoBiDGTcAXW2mENxQs
W7HnVyldyx+D/OKurGzPLfLEkCHLNsi5a+4Q3MIbjAfIdq0Bcqxd8cQlGWza1Ez/+raz5KzKirZ/
bCBEbLu6sXuixAK7U1uHx2Yikf+898Nwu1xoFK/ZZ7ukO8WBmPZ8je3ef4h8MtUhvsR2BBcWTNN0
ZZRmZW6atTD9BW+fPdkMoEDP7BrnSVi9hg31ZCKlISeE9RHkq0GAaP6RqqlS1JSphkrzUK0LqDk/
xLSsTmRmN8OxKJ20zCjAeRHVG61+3H/l66FtLQhRuxQkwHmaFAw/6Qf7eJXDLAOWnct+3MeGBUSq
OA0zTTU/TIOWh3HMrFNfGGaHiSwFHfYGlWM4hKAQLY0IyVnMzgx1ISZay7+0MXjAlQHvcBKMyRB5
CvTQfX1fSZKXSAaVpQ5cD0stYCSJwNbY12fWCccxR3C9CkuPMgWIeUyCsW+IkZu5govj3N30/fcQ
+51dljaaTjOWaveCHbazKljZkBKIEkzq0TCkbB/X4A+pxvsM8Hv8RchypwFYYFEMJ3uPToHqlAV5
s7mbhe9OJR32LtNdRneYpu2SbpRAGGkCUu7jrtAdcwdxK7ruSug+r8sCvq0YKeQcwU0IAy4FzJxL
LxfptEfON5jNXcggOMIxVB3EpKePWdULa5poAFqYpKGG6rxI4WfDteKOLrko4+3FkM0yTj6GtVkm
EDHatONzmVNfMej24IHHXGLBgiR3ITkxMBhJF7nIFOIazhTQove7Lth1cp95nLWmYvWibt8VoT6g
NtiSNWbcPCWCoI18bvrL9AlWDqy67TgT4PxJUNZrs+JMksIRCFgFEUblAIZDPczWmhp2N9mw7Vf7
JmnvG5V5SlGLVi3ut8bPxVjXysOjfQkbDlPwLmFkr0g1w13xy/iV0e7KgX5Mm6w1FHtDMjReJrtu
+hq+OqdBgpQwovcAbknlFTAQTIFeJB93Yb2qBtkl05eIiyWD9hZuK3vVZ7tqCllnSdniV7F7blyH
mwJHBcw8Rwc/4ZsulKjgbunQGmVDEVK6t6vB1ogXb6M6L56QVmGeS1vW/MigIVCOFjOsDhY/Ob9V
JRbGQeQjkQdu3OHRtEgsPPpxoN0GlexZJJSZ6xK0R7eUojJvhjowUr7Kirxe/pCmK72lLpzGHnDA
rb2DYTJxayO4hYFlsPF86r8UGgyCzyxVByvXRdpkBE/F09kM3sV0OTXGtBNm/T0/sl3KpSXqLThe
rCQbCEiaXnz/PPU90wgUM4xzDLZUei0ITCUzg6w8P+sunZ+VhQ3mEkO9XDV8iZtkfLOR91Aj5XXF
NbE17yTN98C/rlk0AZV0O3bDve6/GJPTQZqufjLYdC+Fj5Lp4ueBRC0jnyzTwxmdUVmyA+FiECWU
P7W+h0N7xbIEVWHv1h251XjleCy3VK2GyoDXmdjrWtSOlW4zzpMN/UD7mdzMcf3voQ6G7QqmHB/s
CnsKND+ZAn0HHrAub2k/uxPOsDTb2KaJmETIYIlQrgj8D76fGWUdV83KUhyVSSmOQg9WwppyWnS2
5xOdDKSlanKHmhFiPDOcSrS/HRkaA0LIXCwhnsNtTZRRq2HTRi1IM0uX9P7hqDbg5rn721WXvCJu
+coyonCDJU6nmtreAChQAiBwlsTpKxynw31FLLZmIrhTgVzuaw9eAB11SB23fTBVG1+1w4ciATZX
8J2Qh/GojV5lEqBx+7LLHM5t+3McWYvwRgLrz05jL/SmYxwXP5HVAdP5HOEH3EYY35eoo6CHqth0
k3uPlVb2JxGsNUPwdCIwOb1Wbxx7Vu+rrccruwjI9md/BQYdln2KWmmT8zmJ4S4d+TrJgULk2VP6
zOCv70coEFAcamY4PD35aTI9wzgodhg3lTRRuYt188kaxl2IV/MpBp7AjWJKD/hecE/dvXc51dic
L6USx2O09hzOltsUIFWsw4BO+f11F2xP1e54xbVJAJdU+DODmaOkPNaA5Z6KtP8L/zFzbc0SMytP
sWBfxjmlGF3b7JYw/IPGR0LDEc3sQBUh+aBixmNNXkw2OXYn4vvzDUlIijARKm8f/iO47xSwlIGU
ZUZP51V5I+YiUwZ0xLpcDgl1OI0kuAK55NGo9Rxr6JOxOO9He7kMFw8S3neYgM2q8YK8Wh9HMfhM
fNFVDnEZEpBS+g7CfW7CX9D3fNOtzUzwS6Xzgy3+SbGM5Z5v0dd4sQpxJ/JplAchJc5c1ComzfCo
6btaZNnQ97P/Q8waBFMcKeotlT+/XNybGP0cqstzK28I3a34njx5eynECMthv1bcSi4nTHqIu3ug
XVILW/GFJn/0TDeIn/HxBUqjEgMGDszfW/9gtOh6GkyXFAjgEOrlp9vPEFNR+k1SyTPxFa/nr2fU
cBP93eGSWquwmYCeN6+AKI539DMnEXvSX0M7yanvkUBiIlH/ok92TygrkORQbSyax5JNcOjgcHEM
PXfWrKSSkB/UEp9N6rV5oi0qCwRXB4Y4zZHYYhhnQM1zTMFCAaQc9zrEWgV5TqbuYBE1ihzVI0k8
8H1q/ITj+RfayseUZE5DebKK0BmadQzoORU57T2lrerYALHjRx3VpWj9seEKPVC/PYKfhXwR5vyD
rzDtzwjMa3/WrtJjbCoZC86kHk+8l6Y8antOtuDF97v5keBFgISpGNkj7omwCQ/0ZsiTw1T3ctGC
lC7oy5Ccj7ZcOfzFa4yvU7yDe2sEC+FMYSa2lblLcWempEwxjAvTUf7NM4YqwOX2ZEBD6wcITZQf
RTXsUHcKwAqfMmNBwQZTL2b1+LchBMUliwh0HFV1Sr5/M+lYgtjShNxLgJQ2CNTdS1oUtzMhEAwx
vMryRfw8x4DqqbfPTjr03PDWVrOjNMu4mSQTZzbPTP7KqQ2g5F2NtqabV9/F5r99RQfuen8Ve0wJ
Eq3eoXv1HTCROueUeLvxHNbVy8ZB5FIQHlcVd+91sAKLzQM3jwvf8ok9U9cw8pnAMa8Mx/O0eNaV
oOUrh77+1OtkF/ot1fhMrGk7rmYVp+wb8Z9+Xe5sVXdG+cXgslYMYlZib1Wtz2XpnLABxijjgfxa
isgwcZn0CuqNO05FM6FBZmFSGTngsoQqcPGc8jZ3erDhyXDJ+5Z79OE7zRI/VDcXroBHhQ3odhlE
szE9c/2BUgooOOlLUQyGG2aDhvPLlYRLi86EHfguHBY1Y2+6lv33DLRVv8nNwq6JaudH6c7a9+Yp
79w41foOKPFcgOXr+3bXY6YuGqgMKSZ6NZ3dkfCDEzb+kN08UOweZxa5lLaHhAgz9jzkmVP0MZtW
PgwDSyQkKu7ptvxSlMQ9TwJ+ZSuifRFZBqJsFe8QiofSXHTF2LKLgecanflkl5DROjp+x6T2d732
wQ9Cwosd2TQBtNKr7/eRlfHRhAXqJh02P3l/ormqRwIF+iUSo0cMHNiQcfH1nCbXtoUoiNbyuAko
CZtHvkX+MVtD93fB4OfPPxbD8fq0Nw65J+w+nZQOzuX3UezTOv4FxbToDWicKhC3v1PLfJcGHXa0
cLgtlzh7dIhEZ3P8UH+YM4ojV6DvCw4nkOm4WuQuvxqMM/8zmsj7czqpYhbkmCIuz2j8v96czOLM
ITckDHMoaRQ6YI9WRb20oVWZBHvQmNJyh5E+wo+IgLnpWG8fYmK3YWmcKfnYYBoYcBxQ+AaBFjc5
i+Eu8lal+5RiHmao2iMZcXlE+xL58QjMXDj3iUVNnrxNn9qU5ml1KeO06R8eKm98zcmtURkXwvXp
xRFdW0W5gAfwGbVRC3CbIDndzSguGpfFre+C3u50nZilFeCviRumGe6L5ZochunUtckJ26UUBxm8
WcPKMpPcB5sUZ83rKe7Nt3bGNwM6gb4u8cxpcALSgysntQ/DSCJtuSvAfz8MlZoovopKNZ0vynlo
ag5RfKRZCCZl4G3ivBUHppLHgXJBP/geZLuHWxFsKUdqtluqaLX4b6LU8c6kKyJsyBfqQ3+TYO/y
VYyhunTS4TflFvzOiiuNN3G8roCqHV6zElXT3lNIGqXCAlO6Bv6jF1fs22WyJB6K+HkU7JL/bK8X
r19x+Ix2Ym6CnC6f8BCBfW4HLxoEE4jS7nJz+X7kQ/fMfmakIyyQuJZ0UwJntnGeW0lvUwpuzOaK
R4P/QDPVO7VRHvZ0FB28S0vm/my56SSqCMrCt55Y7Te1xlvXCmjocQ4awJpfttEdV9Po4yTlojsX
wDWxz8m33tLVB1H4mPraVo7lUaqE0nxSa2Kl2JaU0FeN3ZPAuGCAE+Nu48Mzrm3j8MzsrHZSRBVs
HOiYMeZxLwnszHI/Ez/p+n300rxTJO153Z/pV1l/h1Hdt5RxwVt0MAw4lBC6ySvusFenYIthlB7M
SiHhhV3tjmJmSOykqmF/gjt6LyGTRFm0ScS9UHpQ1Ha38X67ptTPqUZa6WMhfWR+rl3r3txM6lzJ
F1vvjHFcAQFs7I5eE943J7n4wN76vnWUL/jNxqnAMsTUDNPEWc4jwU4B8FDWkYdzD6DzAVt7LFyT
080rqPP8AJoozxo/vLX92+ZALupAJgdqIXiibPygULofQrcY4SmYhROCJnntRKXjgjJfS//gu/6U
P7R8UnyAMehq9FrX+TjlAZSWnBR+d6ID1Y9nT6QGoG6sSHYJ9PwBGhHJisgPQQ6/akjU+lTKlz1h
6sqTPcYgajhXqqFweUrjQMD24GLC9LrKPVzwCQWJwweYgfNIf8vEVcMH5T+3bMb3hvOAbZewFT1n
wwY9TDMh8pP7Vz9C4ISUD+IjaX/D1sZ73/B4jc3Wqkktpz2x8YVImlqHcT0Dxy96JxAMpg5UwS3r
m4bok/bl+JrA246UPjT11Af/5GihJ9mHPnw9YHjqNnaBbkBwB+MhbQma8/vwpTURhX0m9dAag+h0
TcjAjlQyTZRSIQaCv55ro1a2+O5pdnz6hL+MLIuhDsfhh/sSB3vV9ioC4WICQq8BjQL4NbSnnD/i
tRXBACOcprYntHscBvnaudq8h0mvUa2QnoxqSWqpDfWatS/htuadI3gkXJRC6OZJo6kIh6rF0iIr
vdJy6PTY6mWkjj1oRRvwaX+HB6ThDJQn1sRrnXUotwl2GSjD1yrz39plHVsVzTyZbFKuqLn0daTX
5RucGjDWdZl01KfeLK22MOxLd9kFHcAJRhdTLjODgI4NTSIiEp420qYwXRWm9bezlNSwsVtnaMqt
czVzPZh9/xgrurGXpkbYepG0fx9piFY21T4pyhJK+PQgqbtjLNmH5GSFfFpU/qSSv7AEp+0cAeEN
hCA2hA9iU0RFoKxXvSSFiOPum4MMArXJRM3zAoFw+5qIq8ZQH/U8x68FO7qxjA64zMFM+JWoqSk/
53Cj1PlNTnLbdr6TGaGcuQ/aa67ouR2GY4ZsbRPmBdbBIUCQiVxXy0RLcMoKMY3L2gk1F4iNNYiN
fvNWbMQL8n8DSil22xbvxExDWvGrjew3KlQscorNxY9DrilsO5dMK6Y73NstTfE/EVQolFhfXKR3
aNeutvIwMaFQkQ7zPn6wkfAPmsCGsB3xcZYDHOy8sBJJoLK7rAG61h6SpdHNqKwFHsrGeGhhbxoq
eo+ncG9Lxq7wh4MKzJAcNVG5Av/zbLXdsldAdilD2zIQMGyzsKfssy3wB8gxZtCZSdUWfULkg28q
iPMBERksJ47lntbxy5HczifN6CA1p/eIGss/RkXJA2/5JsN6eld7HCwlKoNGYtcQbWJAw7dJ0lKR
c5H0kMMGeYDYZfkUz76fa6ObQsbBTt3RbVYm+kSl1tvunUD/9j13VRNA1303gMCgTQTdQdEOU08Z
ixnqprwpX8rQyWZ3ehUsFkebWBUTQDHExaHW88SoPOoU/rLCYsHA00H/dofBbnoyJqVU0kdRMFpx
3+/9E0y1zXDDVLaE21d5/fZof3gzn+1vHVu9XonZF2AAapeZ1TF6MhHDGiMQc4iKcRsMDPI6JbRz
0tIkEAarqULSSgdH7aaNmMF+bMTDaEht6DxhcaQSLG4L42qp+Xj8Wy5fmsf+cCAapcggdG9LZhU7
Zzv4a4VolPmX0XlljbM5X7LVACZ2gf92/HzLV2QbKyno5EADfiE87YQHZUIXBfjUvYjLqLq692kX
V5jsC4GRJF74HoH3mLd591a6XrLYWkNTLHIova+bAo4Q804Z0tC6KAsyE7TmKxNvqCOGgJ5PUQv4
jJ4GlR1D3NUnxD5iMnv/FjhRkr5lgx+OIC+uQttkqcOU1mrayWR8pk0UhuqxEJ5RKYngwL7PpnhC
h0AxQIPbR8z7nJT2a/WMRv3gKl8iI3VGlS40YXk4riYX3COd4k2OhIeC2TuzA9gPJ4dBtugKS7Eg
pGMFO7Gsh1ZNY5symq6IDVR4OsZwlKdItguO2Fiv+OtFRE6ezLJOltSQmVmhW1JfaueUUvYcmTPB
BuAn0wxX6NejAyKjr4AIxLrFxJ32KdixSrn7ix4wgJTpE4hz2PBK+iyyZNAbf38YZL86lKkfpuXp
An2Tx8foPNxJYSHHJem8OEq/UHey0aBib1i+MBF0bIryDYyTdxCTy6o/UWUoiXD8S/0ZyOgmAyFz
D4YNj8J/s7O5gfJ7ZY1lauDt6r6rr3Cge4tKyWQwko2KE1Gw3nv+T4QUPNiqZ+YCw5WsGbuvJuHg
bX31o8j6giojucVgx4rXl76c41KrYkvF+gA+nQSUg+Yyrbg9DN6E1YT4kniFhoNRE1PNirshKINY
U3Jn9iXUOrJQ59Mm7GWNF+2pa7Ua6v8aoKYz6VAA8aJrB/wxgjPl//vWWuI4eUjPla2XJLJOGSow
ijG5ssDHsacnKnPRoUiHEUsWXk484iNDSRizKLc1JsRpCYoAeQt88hXH3nQuPcw+DsSqOoHCsoYm
72xr7pCgcH4Cn6l10uKcPbBEMKxPcGICKcXaRP9pLOhq1NFaZWAHpipzCsINppjFPsYpsLYVCMjh
D3wYJwu+cf/gLMb/5WuWPWRcFHO5sAxLwBLKOurPR67IZLdK9HlMiWCHmisXMLSZv+HTaFHjyI3V
NM5X6cU9MFIdAG+fdlM/jnfrq8rh/T85SFkzbigJKkIqamwkv8p6HYQW/katQUe8VgGzgUM4Wge8
WI1/M9j3jvociu7kuGO4amFdVExtjzt4ydQ8ahtT66+XgjXdPDLsEeh6Fquz44/E5CL4pzmxyeXi
+O2o2XHmNK0IxqFNUfFWJGMYdN4evJHYBQqNo7M56EXF2AKoPbp7UkVcqc+Y8iBUM3i+4VbGWBHF
Hc4SuFFa1NlVSMACWcVy1opadOu6/aV3RnMApAYyyB4MbVUwQXAjgZTm2sW/M2EnW7UdLly4zB5z
GTqqa29lg0a9JlKyQQT288/jtjNlZ0pk4D5GFGAVZF9hJQNNyrv6ioD3zou5NlyyB8qxprm8uqsR
ASllCTfZY1oxT0raazP0xXjxS/Zes/Y+P/g52JdgR772jNTIcBBi55dYJpBIzETu0uMzfLNBh6R4
JY5UY5TWPXKaic8kLm7OrupcX2m5a2wIP4sZfGt0ME5H3LgOrSgOXU9orQWc0vI/bR5ThHN2YjfQ
On15I8oG874bjrT84ZljGc8S6FmTHUfRLYvrpFpIpNeXUqfJ6cboVqSupXv/SJt69pYRjoCtFQyR
yC6Tz6goHzd/4Sw84x2x+jb9086glT+1lT/+r2qRQ5miU8n0gJFMSVADtL2YUw+3Z+P3SPKbn+R3
g98lP4bCjOu0nhZp7mhCmPlSZPSCZzrkTtuB3R8qmwvGLHNmZ5MzPTheorevfjbygfb7S0WH+aui
uElYE64iICtNdX1rD/qcMsu1pOX4Oex1xLiMR4ka72xZfocxLjoJ6yr4UYoPuFQ3ePwXrCELBrBX
AQ5uyzWW5va3m9Uy/lUfraHstjxGKSf3zqy2xwiVkMv76MBhdZEiTnoAYRHR3LgQohSs5jZA8k2r
xwzvy4QEGaMlmmfCie+t4xKhIVzwEXH/cdCMomKD64JVXYZ5lSuH5MDwyD+3t8njd5dAcPZK5tl3
QwXpvGR7SUFrVZYEDUmR74zTU12mbkO+zbujjttdsNEX16+PdXI4M36Ygr5xVOPmwJP68piO2LiN
FNPV0WQWJLxK2jKFSpONdhgCf7QvmMMzcXsenzBMfYxbH9AApRlY//0XqzviDRXL6LJqIJs2v/BB
LSySllP7zqrHhjQJEqMGA9de6bjsjguK4ZyvgICdzb2/KQEQWMtVmQoyc43d+XCkHjn9LhYckRmk
TD0v4Gz3coT6AcFSSCMSoAatw7MisPvj4rHOIT955Eo5tjOLDodknWX/eUoBh1gDSHBRE2aNoZlC
zKrjVX0SpTv7PEaWeaS6Uz8IeKcDi7OzERfq6DGPQdUJpmsmmVtLCT6zByeWMwXJ21UosqmBVr4d
ZImQfuGiYiCMYXT4FF+TpL6b7o3Sa8m66OQEPyRcVummypG+VDcy67YsLoBVDo7pq/4GZIoJFWAy
JpN0bb9Eu8dLlT7JHeEBZaTn5iY/W1nf0fnjxzhRXFg9bJRhrJD7AuuzNAH+zUxAoof+4dCh36ys
WpoJMVilKRzoWMqGaI0VB68b7rZ1RoW1Rl70m9jKZ2z08U/crv/l5ItxOYZwJ8bMU3mqp5x83Nzl
hDtbDkbBCekQNGly7rNEEUAqGTfeztXai3L5xicPMRKcVsI0rVLa0NeVfQzp8EDyre0BqSNBSP/m
1urL7KkMyqoSRQd6QdlRitPW0MLHAUhfmQj4pMOlk9qMBFNUxYyV+xud0ho5qmV8/dtpsh45Qcp9
6GonY/yDAopVOfbsO3+3RQiY4c8CbhTOxkgmq0pkXmM6JA23qt5X5KKUlUkj/o2Wzt8qUgMlwUlY
BCKL2RyPMdHpbPgexlOMlLmkR6xw2eytxfEAzmhMxHz4/ftQIDSF2QFtR7AqWyMIHCwWGe8yu2xv
NjrJb4gGmJhtNM/DCSHS0cchVPncsAu5gEEvh81OZ+yWLVaI5wLlPnDuLrQTXgcL0175rUtjlQaJ
LfX4iQz1Tmgae6/YDARjdXH5AdB8YohFQcnz4FUKe2vedcFAXaSAZsG5JGTOfOFioSCWABvymQWz
S3uJ60f2gGYKLj1bwY0/9ubRjsQCLn7A0o8tw8bP50DY8obW1cyIGo9XSNs1Q6JAiL4relJCGcK9
eyN7DNU5ZnNMFzhsAdQww9K2eLi92S1jWwNmBMWVkrk9W+2guhgdsIsuLoMNLQXnCfleQKbJ2XDa
ZSiFnYF9JBJ8J43YrGvy9zLxLtbr1oQXNSD1b7mpBTpNynxhB42jsZh/6d2JK7g2Pg53RYR2uAlG
aZAAcwJymfOACVs0GhGv9T17JX67PVDUz4OyAjSI+1L4jWKqMgakPR0hQFym1MAk483GlYhjgNS0
iUzhYf2PWkXLmhlqwLAgzJ1xTjnQDT1S9z3wrVUhdXPUs7NItxsGIiqSoWrQLS5h+IV4LeB43cuV
rT8suxQN5UJGJnm4yDv4DjUMAxD1qTF4QlMbfGuEzdCrHRmGfzhvBhoAdB93gxtQIUqOczwjfpEt
8N3lk1XUSO9fEtL27xeTJf97IpZpRwGLBi0GYjcQ/dHf8UDxe7x2lqBYWhIW+dU1J/HEhpXpB6wI
BgKq9Hv/Hf2p18ndMQkgVQybW4DHR9RqZSWr/0uH8PysCh1ZT+3/qw1+JTFqNvyakfP08G7OL/pA
0kiJZMFVktOE5c4Y4U7a9+J9MI4x20lpiWzF5TrquSJFCZ78gXVDa116aBgQS8VJ4JcRQgtuofeF
q1OuIVMYb9C4nx7sZWkP/TdFbwK4gM10wYbKaRES/DX019EkPvNmmmeoheP6MT3rHzG97FmKukQf
kp4+lQdQVxQJl8olgcmACrkL4dKRHrM+GyeRQGPZCl0uWsOfKFOrrjymGlQ8gbtkuP0Bf1P3iv3H
x4PbEj25PEBOmhrVFCreX1C7n6CrY+YeKud+2oEj/+kZauseOIEZvG/flJDRDfbptiI4w++Zv3Jf
th1g/s4fJJqzKmlZoWtJuFPAVvNuP7hh1Km2LyCx69kWH2gOBmH5yqXstD+L0HzhpM38Wc882ujr
IiZ7YpBLc3QH8ocWPjkEzQmPdhSGih0nILQ2e0UVGUhqOaenQ3gmCiNVQjryEy8jOMVAHLm89vCD
nAk/k4TFue4JnykakjimDE4UxBCtsa4VTEQW+WnA80T7EwwfDSCjEJIB7dperMut2mkQFX0x9Y0+
wwjrbs9tfF+yscECk+ZlF1CG5Exwab84DzSbdnGHybH2u6OCwoKnweHOUA730OMhwSDL/MOJm0BK
AtyybTxDIDkH/U9xwxWbMBBF59bfgEZ6c0pbDkiQttZTCHD53Ox3eIjzorG3R3hapS0tlmAnoEsV
2tWZZ/e4bTQFFHJ+Dabc9gEBByt3GqXXuGBaMAXcuSU3532bd1weA797Y3ozCUmA+WMY+qIdcLGj
I+6VwlzUb2st9vkLGaFgs6lcf2Ti4zSsNYEClFoXMaH13NAuFfgF9Ai+yy506t5uuPaABs6ludbh
URxn3OR5VVrYyO6C6RGwvANmCY9OQJX0FxQwzOl5lk0Bys67kC+G1MONugtxeeTDEL+ftKvSJ+bU
DNO2BK40n2ie0UlkDPETpmqF6kW5AjWr827sQmQBm49tnnv5XOb6WpfYTIokK+OAfVa8vO0ky2dV
prHPpVGLQFyO5PYZIOYrVPiwLE3T6gruAGD1RlW8NnTLuXV/6f4lrrxVpsc8A24pLzFemx5a6OT6
P1Y+ctf1KY8JhHMd7+5UzWXe2sY6JfMPyA7BDpNduXDjhjSd00u08+NOUbsGU/omgGJGgtrJ7j1B
sRKhl+X8s6t56uYGD/ptnrLNapIxs48wL8hoG70mY5THCgjVr2VZOjV9Lj23cqMHO6zKWAvEHclH
o5V76GTHhHoOBlNtpY5tGTgPJjWtFdFkLSAdpNtdr3KIiayxRyXPy18pt7e7wuoNCoF5H1hAa5qm
KtOJqfR7EKxhFAaJYhPMULop6Bi4j7SBAkPBck/lXnvPThBZShfbUByijyYLWIxhff3a0nnjGv0R
hVmqjFfdcWXpCObqn0VYTVQJ3+ZtLOcqn2sGDacmlLoWCER4XX4AUXDaWW4sHSysqbDg48YBlkH7
8Sa+PylOYsC/MsU/elrU9y22wldrVDqAkNZclut30ps62E9b6rkn2Oi79K9KrC1w2mY5WzRS/5LL
2yaY6Rq1ToN1qEheDzgxgAg3cvl2EBgQP87SowvNp1xI3YTIrcQYjQrFlvVTP7NAqnIIBazvSoyL
g5OiblOtHi5TGo75eUAXsJWq4tSaQnH1lSyah5tWXZaV+Q2yP/fRnlXQXglr/y91R6e0tvO2Qo9Q
sn9SDXBWRjnDQU7GWD0rTITBKK33Mzzh9THoi4cNmYH4BkNf4T++9J2Rd8MudWiUIYwMl3EAFq7K
LUxXNz34ov0jgrvrkt5bByGiD+swcTTr8K1IPCqMHE9rjsev2KSZodQg+1VDD7Ci5u/VNumHC4Ru
HUZONdhCRKhHX4jqKBJJsA1ZxFMOD3tjX2neVrZKIhJCaKx4Y3BAf16EVHNuWmny4VAq3UUGSkiZ
kOd8TFnC185EUc0Gxpc7Z19hD3Cwc3VBTmneBdgKPD2JO5WsrRQD9IaGBeUv3EwFb/3qiPeMwcHo
0rhFzARLugLhF3JlWGN4RXBJn9ioZBPdgshEs9S1slAhPV0lDw3dD4s8lMDlwDkYDVt4sgSszx8u
XjkWBc6hOnlyGdHJmEvp5qh9tqAP8KTqPsLbfImvonPmZ8vzlbUgpyRjsEpxotG6HPhSvVe9hvGq
ocDGAK3yawZhuvohhaH1zAWx0z1rfTmmhIUxvgmAnYGhfBM4N17wEO1GnOSf7PS+7Jg5+8/cCVtT
rStZkR8kmx3JodGKag3bxSL5qmVZ1xla14FMrVBjRndhgBIXWbu/YHMvgqDtWX71DjjydmjWmUx3
mCLH9JhaNlq1+cBP/sIvU5uXcJtpyxlQgbTMzYptPva8MMESPyXXddaEfMvOJ5unE0uTSn3aSrGy
ttJ57fgF+bFY7OgBoipc+JzmnxcZhokPwl5S2L7LMFIG2VVLz7h0Kbt7BWfXTojIn+1YhF8m1GBY
pZ5Jsryp25gE1oXDKUcxnxUxUnc+pbbQr/wu3L3dKZc2UM+cydKQO+oF0DG+qZn5Am7SadcBKwvc
RGCwbVaG3OUCJHDFzI4WJqo7+fiQeC0IVtWdOGsLnap6BGV4FVtHIuxUAU19ncxrvLRxQJnXjR+N
9o8vW7GZq3ZN17coy1AWwXZdEKCxfJuLLsjFZCpDtvvx4wT3vV8AhCE70HpezQZ/vgVWVh9UPf78
yWPgVhX/ED0025Rbv+f8uTSHEBTREH9nFJ5CSpy4GuLstySwXJzq/7hg10M0c4CjrYHdkALq/ir1
RtVkz65snieMrGQXoUpi0OyJqpEf+wU1GdeKkI2ozKRS212kmAVQobhKTvd7qwfbOIxSwzGDVx1z
Y6JSuBG4uWguwEYMDinkgctg4LX19folIvGxwm0tUmxe0l10xbV+Q8bSgvDBTlqE5IGiCdMCKhGi
DfVIqKDMGt3NXqei3gXgIKUUZmXqjf77STRj/oIP4jWhtcbfpJWS74K6xf479XKKVLQOHDy+ea7T
6AeRaKoyVCUqhakge1ldV0enDuAIn6CXKAfaw3i5AJTqPuWEbsuPyXNfGG5qptJIBeBuWmMdLaAB
UC6vlKrWduJwT11vxKJh728t7snXUX88o0WFA+FTuH96GFdLXdWgantD+tLg4krLZaFHf79JaEWq
ftD4bVwhJGZGiPMgblLBt7vUyh0up2KDznHCN7q9UCcOfvQ9aFMOeRyYXq0zfrJYczJim6UDg/mJ
CsmUUou569XoZu3tgZvBDtMXD0DodogAvzh00W+T6hqYODcWnwutK6go61sb2lVE9kT02bSA2mts
RwdhShpoaPlVcfVKtWZAQkY0jwswMnHBvkQHrqJajhYIxWqFal0hwnVZHLyjUK1CG1jetKEXbFRj
hm2NFMhrhKlTpXBdYOx+PqYFPYD789dKRtNgbnWuJAD7Qm/BQzm+gFbnhz+Od42HuG9bpDsPHs4/
oNvOqPVNJoVeLREHqhsUVD3bbW35443ud4gr3S4Oa2P6TTVOC374WXR9I2SR53KyKBvY1hfxe6IN
dZrfYZjkdYA70FNyh1eC5VF8EtBsRkKR0VryjhWqijih31xj2NTcO0qX59cW7JLEm4gJcc/XJpzX
/KVIOMhhPiYkWf7MTL5q2qyLr5gAEpuwZQfFGhviT3EEP5tWgpMVw/Y63J3l80OuJJpfxJgqXp8Z
ma2PEuAxW6OaPnQYgY1oULaY8scFlTG6jdtdapEv63CSxuqeaopsQqYc20irSjiACWTFhcr80PaF
vYoSoW6xmKVh9xJRxnjvoFxh98sik1ar/MvSKg+CjZ2evxkZfkmzbRUJv5WkLaFdTQjEMjSlwZl4
BwPwJ/ZQJtGPtby4EmzHMa1Cmc+dWoJaorPntYNNpY4aEDa5pzKD9ienOuAjb0f+qJ0zMY++knNh
FkC1ipC+b151SGje9ELY8R7n82cCZ34tXK/mTBkohd2Z6sArynYQ5pUtGr8MvGB7clchb153YKwq
QxyAK4av4NpHtuz4OYlKe7u7BMUJNePms9SS92KH6ph/Oh1EkWyQZ7ym4w948GbqHBLtfgDYciPC
V/LoxBdVekcCejU/zMV3UhLLI0YUWjKviqhFkgJ5S1sPOKTywQPQbwZ+WbaCdqHz0pnBohigdmml
JUc6MxdZv6vch2rgVatAnZ2dI7NMoSHm6v8ZRw8bH/QFi1vGolRF2TFY71ZW3ywG4QGdhub5nO+3
yyRsgwm5FnPWdh45Vao4WQZlqimMIWuP4BmkZ4R2xGJzur2CHR9DqE9kfvebDc7dBNp+JDKUr13v
rfcXyoR4IXwZp7Zb8YYYB2+N2XJvLJmBfbbVLH1qv+p6pDLGbFH7thQezPigAjKDmMb4RtB4hbYP
PC2exjHZZ0oJE5zPx4RFgtOVFkAyl3HmCK5D3U/qhw9yn/HSrfNlPwZ7FT45Bj3eZWND0dllHcd3
6FNp0I6klCXi5WP1wbmiCXSWHXdr8B8QoR5PKsbkcqyAyXc9IfcCVzGGGSiGXcZlYAZ+ItbwD3K2
6l1GZOpLagmXOO2jBatDNwhpNNrwkieeoFyDutNOrjYucLqpENv0oQ+xdWdQ5jystlv33Lrm2Qnw
gSXwHiBOG5kydWdZCuz9YWRPpGchfo5LEgFW8aCQjxC7Pw5aKk0yUqhxpVlM++EadOLn1VXNaLBl
wY+grPQGHeDQ0IlxsXOXJnYplfxxHhWrw77CzzDLjZ3KaPwg6ViVKz2ShyfiWEzSOq+TKB4aSoCl
W9+koQ0Ab092jCdGYO3KscJPPoIlkTMxJeVaRh/cNXVrdUbKdz3LG+imZ4whP/VVDKd4Cc4N/RK9
w64iMWyTX1g7sd/DW6zD/HB6ED17i7TAkohdCtWBILyrWPYbRv7z4352l31r3T3A4BDDALY9DvZI
j4NneEo/KjCaZy9whkJdO59zKzpZQES8shSGwwXGC1U0L11UwQbfvtFs5iaK0qL+t43Aotv0IrUN
r2tgjML2KxfNUAQ+KZBFv8QAEF5xVxOa1+RCrQU6SMHwxib9ThDBlswULgWeX1kuQCXeyKiEyAP0
+H0oVX+M7hNOhrC8uTcNHmR4h9ooRJ6fw3UeH9IuCL1qq+m8g9RAgEtYTmnnXlPNOJz7ZKEPRRMP
U4fE57rvRTjujLeJ4i+Lm0xakX+2HDfThQxm5EwWTCjzaeBdliBxLcinuJSC59HRSUe4BCS/ezhg
e26yyitY0dpGLZahJ3kghcD0LzOUkliiJXF6LfNnsdFGz/5NuibwP4nxdnpbz5Xnn6g4th/jEJ+f
f0D43ObLA58vt/Nb1OgrfcC2M/lMqxBtPnmsQ9T30rwtiNS9z2U8NDOqmnHldpjjotR4Z8/3wDty
gOBsQj8Z6rPwithF158HrJXvyplIdKiqwuigxflg+TWRXqkpv+at083gpQFhX/oVhFG3fTffcY4W
8coznTghd98MFyfzJt+1HsnWlmVwplZYf8N14GV7QZroNdN7JG5lVf9jumWB6rBJhbuDUAWoOHMV
VhBokcOLTSIgNrUqRvmLmVwykXse4O/LVkxU3RBQzIywSvudmuLBX2q/9/xSpPMyfXcBfQFJTy4H
JHALaD5YYOG8jaZksYAJmiS816jC6EQsPqFHCZU/h1XNlC//DgRLt/y8uYq0dSJQLS4TZ12Q/HrL
rk7aCofs9HbA4mPnHrdTbV1uzarWp5MOM8c2SUytCqUDLb3nhw3x81ui+nKg3zj0Zztv8qa6+URN
j2XfprMF6b/OE1heArhwlsbIpFCSr0bpdYi+rECzZ5Jfqq2Eel6JR4wavA8Gcy4FiD2JoUGsYnIh
04mGKt2LcAazfJrfAtW+muS6IPbL6cm1JuQ8FLC2YEas6YJ85DD8Bm3eS9nDaEK8wweS5AlJ8ub3
EHLrwfi6xKHLLHers8e2wKXfnYxvE6n//9LecS9svnBrC2bqvQfMQPpft/syNV6u3wtePVMFY11b
eKMPxVwOdzfAENOQoYbmZjpCyofRXuudHdsWFfsakAZ99Y/6H6C6cdWAUUTxQbzrcqGkfQ5igYd3
5dCV2fZoMYLdwXh/npQbnBs7MZ7jSCzpClg57kZntpBLQ9OkwJFPhftu2cQxBX0G38vVyhg/Dj1M
ACBhuUPZ4OPT/yC+Mj0HmnUTiXRzXKVCSxqrzlQy4XZF2Su9h05JBbbfmT1KgPrTFDqW+CJdOPB1
u74lsVI+GG3h8qGL7ubcEco92rDN4rj/m5kCOcDtSrIQEo0AuXfPjsxhH1l7hnrKDl9UVZeqtW/6
boOrUmYZyduW9vZlcDYgZXW8+d/5hi7I50N1SrPgzvfTikVZCJt7aqv8UMpcMoQKRtIkuyr0YncJ
AfdP3BZAI0BPu1euTQqyo8VRhGcQA4E7wXk9QEb1Q/IiG8DGIFmIOw6N9lLVps+EH30Tiw5OKa94
ezg0h84/W7BxMzFIiAsZL/B0iba0wq6buO18whGh53WUNvKPp0NYPeq5s3XJVYQxS0G/ml8csRtz
7tHdc1Xpl+DQkCn6+pFyPRmkb8f6ZXWsB+KqS5uTzyHG5PQ3NM8bjbAcagmRqi4g9ZdZGaichAkb
vtgqTpXd+1E7gj8XICnyzeN8+I9qeKCrk29tmuNngZ9Y6yARcWxsJY8M5VYCduHL7I7jVSwR/CGN
z1BZuQlpxqZ5uxWCGXLYZs0oLOPvDmSzuorUpgasayYNeIRyifTuI1fnlo0EsF9n+77P72T9TE9g
PWBrB7Izk8gVDoP+RcIUtXsy/lbSfrxRR1PmAMpWXY1iemSSbEJfwWqn22ux+2yNs3wAKtwh751T
cWRkL3GgKr3dHmAi/VqPF0b4QOCwneOH4LHs1SPyMr+5cazjZMJtTtCgz1pAGdSN2SyfsGzXFYJW
StgULda63kuK7VpinLx+1vJZ1fvv/1ruCngs3xIl4t0g5ai3tn6Kr4PaQZTttddJuiFNCdnIA3uv
VLtbbY3cr/yV53FLkxr+iOQwBL4hDqlDBdveuFATK7CFR3PjBaQeIZ1+6/uAx+RuuLVaUTAul1NQ
GXOs0murDWKTQuWPevk7EQg3/rdGMl6kfGuq6f4mO5moCa3tJS6zLlIRId4dZaGW95WnZ3df+wdR
lGREr5yukk5j14uKE6jH9hml4ixl7oYwpM96xejoJpI20eZmiagr8/7QDPrqlR6x46CS5D0O3FU8
y95h1GsX1MzRTJx7JicsXAeDfWli9fx8pod4OnHSKYuTySelGD6ne35CO39ROgB2kT9r0uYnoyvU
yoUvnglgCyjiu3kCN1jGfWfdyQT7sdSZwhP/tkD/XaU/vaElexVSWyIIMbQawaYwRZo1Aa62Wzuj
vmmu/fp1Tq3xyDQbFbWOvbz1tix+jXusbbw0Qfekd8Qxt4akERbglbKaILYUBPLYfPN1KEYlrugB
HuNDlAqZoieV8eOuJZidnRfbgniY7QQaI8JKA6zXHzu+AKYgEj0lxFGhM3xZahZFk9clsCKPucoB
hVxRltDxQDc3351ci63U7ktCegAeH/GTVJWK9wdiE2NWB3IzYBf6Qk9yxcN66anQytLdpi4Fvm14
HZARHY4w/sWs4asbA0toa+pNOrqMqS5XpB4BOFXhivfvLrABHnzdCTKPQUu2jdQdnL1IW/Cl6Hki
q3pzGoFQS6CcHu94BrRAhrV3KZtekONPSl0DM3/3Hl8uj+2E3ygr8f2yXvGVScCSMsgMWIXuOECI
Yb8t4nb3KBnl91yBjr8AW2fB8Nq17OWFxDA8I481I7e+gNEelfPTpr+cIqaMCficRskTi81auZls
u7iu8Rd52ejGyf/rgXrl6L3pPwt6/YfaoysLrrNqCtZHXhm2QpwKFcvWi0hJ2BxVMrzFbQIUd4Xw
z8tMgnEetiFlj03K5zc0fkWVoZ9/IEWuQLAfpifKq51tthb70f7aR41OO1lzjQC0WKMxtvVZuf7T
Kanworo57Kz8pswzcc3UwJavTlp2w0he9+vvPCZo0t1n28fRq173ncAKRaHmIAF4Oikt/a3H6FYL
Jo9p4a0iK39gNks9IoDhWsdjyBVh1K0nBlFoXugON8+pxn5dCTbGFxaVHn5CquKUbFLscMcT4A81
rrCUU3pwUIgi1Pz+cqSLVjgazbE3pDHnmGRo7+p2u8xsLen3QqdBg/mwQBdClrFELbBwGeIgd+9U
CUBVSZuhdrwB9743qvN1eLOft/u3rCDLq0vT5Id52FsTRLW1SqTEHPZ+MZDR0LmvDd3ew0PpYQLW
KvsHBzjotNI1FIakqqruURcDO2JcIkzlmB+DMmoO4kD4h14AZ/quQVwIW4cYOpBG6Hyln611zbFA
+gUrojsYdc1pQAroc7xvZiaWjA2A2gBmZJYRGg0zaZyI4i6lahxH24zGPu7gr+jhGsXKVVEGi6i7
yMwnGZr2WTpfyFFtmQKnXhYJAZJjvTQOjyFdq6Xt5nbaWrpirNwe0haJxnqrfuZZKrnEfjHz1NsF
zG+kW7dAHboQ5CTpA+eDqrzGZSveo95nqN4+E9h6TdTAqKJw8UxjoCxPDKILno5EP0R5oDF7FYjH
lARsH0tEB5amM4e+DvPyia4ov+IFRgPEe5sMM9nhOWwy8hnI+HOoF7+HWoRjHu0RzMfFKSRiNv/H
8HOw75dOKQXklmMiwGXqtV3Mb7PDBAoijTImsAFf7koq6T4U3Ifn583ABizAkaA4yT4UHZwv11TZ
5WNZSzdzWsryn/j+gjuUna85YdhIDcIwOfVHuO0amXHsChRI+a2xKRCLHmVIls5Yz33iYn/x/sLB
Oa4fUSwqmVgUGHQawhloOm1WfSbcv1iSx8wGjhzB268hDzpaOPecpkGS1RzWQDf/Arq8iWoIAmQG
Hf9EsumCIPs8uMGUrAgKretV62FkzpVTi2YdcGpakd0+ApDjqxpp7PAqz0Vbd6VHd0C436LUetIL
iFKxb016NG0wgG8d8YGe5U5NMKucOgrhTaQjghOFR7gRijBwv9wpIji9NAeI41hrjc/DYF5XjUG4
HOVjPXXtXlCn56IBhauoPRJXMa9XMZoU0woQY02OoKq0+moxaravsIDt9+/+v7n/b2UGixTdAeQs
n9dSNC/p7t+NncgMU7baXLMvM6Vlhe+GTVz2wpii5vHOHYCiVa8AczxnI02kNC1DWd9OY8p0JVe7
Qk2Af3gezJXBgH7soyNm2jTMBUr7DesLd0rRdrB1eMx3+IDk1iApY2BQqXiIaLyN3X+uR78AfeDS
0nEgr69EKCaV33RHU7AeHDOUbDD43LOxjHtu2kMkonMpPQqa9NlDGNhl9sVX4VqgXHe72gLePRxg
4TG5IIX8mjyhN9qr4/7PswSC0D2iTARsdIGJ71mXSSy2ZS2QWpEZxgiQXg0DGDIndHiotapKe0s0
RwVByFniqK+gDcHSg7fStywEuOiKMAdjJLhlPf5pveuWWgt5uNmIzbnDzPliEJ2ajqTtOHr7mY+R
eKU3yDdthKyxkbQ9f0YzCOg7s5zxGvo4dsGkPBXMXUXBdJOFuOmx97+gHxDqPenjpwzwOCeWOtBc
966McvE7t+98+xBCW5+qyZLz/9bk/D0pczDea4Sl64RsgbQ5m2w2TXFIuXhN1K+NXX3jRXlBwpB9
q7KnIslru1et2epllUCU0k7kCHmiEyRLH1PB89o4QK8h/ynDsnTNeCKIcFwvSXoJbH+XVZpYXECZ
pp5wGD/phI0GNkpoUhyCQs6lskP/brKjvtgGYVpsG/VcCQkCtD/DVcHNXd0yVI1knR52jRqR0giP
iIvm7jEy+3NnFYzwqwgGiQoMw1vrQfUW84xoWCtyrPYYYVmCsfPMbb6dedb5JurRzwouIeNiq0YK
R8WFniulbcrE21NpaP3v1L14iCk63frNU6wtRY4Z6qNlXmlr6kka8kp2ZD3Y2xM00yLe92H03obl
2LPnbIE/XVPJ+EdlkGhjIMCs0XMRDTQ5g9+FwYMJxayRuk1FALr6HZQnDEUJ+tLhoJgnABwrGijl
6VbRywSh4cHWgDMj+EvnGSrws/YOBE1+XiD0GVdKMXR8/ySWuTnGuQ7BRqnNnse0qRwlZRqpR64R
qvxxyUgG/ymWiy7cMvKA+zmt2r7v/vrZjvfXCe4aSroLqghTJo3A6kg0DkkA0/UNX2BjRhE/v3Pg
f5kHmF+tbu+t1+Y0Vz3WF+P/z9eHQ+ph2PCf8GmRiHYSmsBw8Tr3pOM4aTC+uOcJU1qCiN501S+v
bzjIChY61zqDYjA09MeibzyjVOeTon1JXiOQn9e7TtXPvqHx5jLR/t9gJGxBwA9ZKz8AODTgMyMp
5TUmqX0bzI9ZlS9L1YF/4CC7meFFI2gf7ZAwpMZAfvrjbG7/Gi3b7BvwLukWpa8tE322C1xh5n6A
CUOBcSsWBOFjKu8MYFJ4snhg2Mpx9est+pwomB2IBtk0h5F4hDVZZFs+cTIha3Gk+BJ+fiRtNL/N
O2w0QGGUpEYHvTkBCXyQMH0BCC3gymMeHgO0tFTiy/qH6Zoz2BuROLhzQSdIcA2gwQtsfDlrVoDM
MRciju/Ncyzz7VovLSeOZ/ID9FlwpWfACFVLuBsBneLLSAX2djM5JhyKilUQR2OYHW+8SAyfkjfM
qhCNx8DFBNwriUna5+9UEqMHN2KbLPChVH+eLwW5+avpn4wcczD9jJmbsFrehdoQq0o3xysOw9gs
9bO7WpPURfyf4fBr0XcPLxy2SZ35Eq0wVH7OQxYEZS5ZLSdTdO4T0bJNtiGYWLtkDpJdj5WmRygS
+rJz3CN8St5FQqNnPUNX0ycTL9cPK8sjgxzsDyygQ8Qzb5aOXp4cQgPF4VJhr3DP6ujxTSc037hv
iTGKcxRN9IiQHdb0zBwtMya0/NDHEjQjW4Yf6OE+dgn24kvMUHorjQuFgvXUn5RFOvjBUCfWJ80V
UUagkPcATlDOzU/2bb+8BASp7mcEzd4iCXcRCITbn14xcdyR+Lb9Fuahd3NYLWcvHwxLD3TRlhP5
X97w8j3urOqyU3fsvd5TZ44pD/mTMU8mUAyPbtFX/+64Xckdzh9bkGfsUctdadqhN7AGizcXg6eF
LZefxtCsmis1w+CjcPjhXOqpKxgAdZ8LEPi5SNtXytYrcKp2x62rgjOwiGPwp2Og2v44yznFXf5S
AmTSUGo8YZ/4w5s+PmLbfDuL/8CetjHZwuBwSFhexFnYuMF46fFjCKXPs1EqKdacUZnNdcEfmM42
kc5+OQXsCOaT+FxDDuYd9W8td/tSCgHH60BzHeCNmy2qUUJZ0pNAm7iCyGKio09YN8VTdf3M4X+5
OiS9FzsCEDZLrJrlm546S+pWUH7uGRBlcCmiYlrkfj1J2XHHgatu0rlCPyr8emr/sC17c0vElURe
zyEY7eh3i+LqCuWDQ+gcoDem8dqjfqtjQ8LSTTdNRZryGiG0qssfvGslOoVybpLa4Zhgs/zbralw
K03HCnOVnxm4EYkUKvxr/SWK+aRUIebyGcjGyqj3LtqX5fatRAxezXkaz5Lw3EwsySObZ0jZbKYS
5Hm0+sH3meZlrscDJDqiNt7FoZLnrK/LIJz08KCq+uV+BWggDx1jCqssiuzMG1/YxdKCUQpdhWda
F7/lxm+EYznjpBv9Tuy6ICBrPZNNmlXG/IQndgkvJ/M5s0bew3CqBQjFUBxbRIVmkHXENvfJN39r
XHQfvL26551xsGSngpmVHEHmBZyiRb2CLaCGy49A0aKrNJyctIlzRl+KWIguRwqu/m8SnA9dYunS
P6FEePEbu83AZzoLQi9Bjbsthmh9XLdR1BPT3maDD+0tTQ6BDim9d1HyICbBTUW1DQQ0G3dNCHmW
m5vgXB/EJ6cQxaP7F4mrdJZmIE9GpaTqUIEgE74Qno1691Y095g2/qOfTBLaLk3sh1zDkYQrFlY2
6bKQNDcvwtGIwkR6Z8O5yzH2wV9HosNDM1GJViPRsGkViCqwO7lK14CwJHMPRH+019AcXhvpiwjR
2iWgDo7leT84+Akskiqp8CqZ74AatA1PPsf73PFSbbAdx/LcC4b7LGLXLpXkPNTd3tjb/PbxZdTX
2GhgmnVAe3o3mJM001j9XHSDpckiJCsI90nSMGuIQA6nffeR8fCrz3U2KDOtnzOH3aen272ew6wi
QM8tO43MIQB/pwY/Uy/aHL6cfi66swmwebwQbMXGzB1zQ9vWsxirbAzrAlfHorfgoi0cBBSkDTD1
h6iQQkeMPI3wZPeaBE+PHvaCzuYQy5JoJS6wTy3oJGARMadSPRWfRKjp1q9+U9sNGhGP2pAKz/Lt
PBykq39cLKOUt8ZJ9UZ8Q/ZLtu5sNvFsz1feXDANrdYWjPn39cmiSmKVbRJCZCCwsARiZu68qzSc
HBodj7XQ8kiFeA4xCel7DQMiIhwtMkQFocsxI34xh7/5ciMmE9wA/H0fbgaXohJakso8PvoOfxdg
5zc3f4BbrxiRktZDhKteAGiCeCqbbD1jgit3wuLrJbHdmxcLC+cRjOhzitMtaFkWtbC1MFTeYkMZ
3+3AD8bQ9FNK68NVGCz8qkASAt8rxg7bM69XLwN1S/BwkncUhlurBWnCKJNjpG1+NR2Y6gYqBIAC
1jqPBHdUhv2qYxbgxncsnIqW5s8agHFIHxWtHtEXR3kIqy5ecA6B3sr4t3JGAOrcsWuNzMT/ujn9
N3QqJSebC7GBy0Dyx94+zooXy1kl1zPrssE++EiMU5gBqXv9badKhVvLgGrM7bb5MUSeRLt4tSaZ
1xpM3YON96ikcvX8qGl9AHlrIje0sZJaovikVpmSRJoypolUZXA6+ex0TTndaVZpVo4HMqcqGzaC
eBnwl+2sHk41gCJgo25/yLTPkiE/n7GpFzL9IMZW9Al2MJSHMHItxbO6mpFrbJ35KnN1SSxGahSR
bXnaqpdSIF8M0wrg5M6299ht0dc+RPbxkby23ZeMg9V2D/kTYGw3pBdWu9Glftrp/AKdRN8mptVt
t2FMUsyiCV/z8569oFE+FVxivljLOLmd+fQ4vIojZOMhO/23nQloh9vzr4xAN9Pq4wIrqfj9a8z5
hM40iCR9FCb5JX/EscpJOu6HWw5wqfpMbIMvw5bZifG8YLERSRp5bUtI6KpLXOtuaHX8KTMGHM2A
uBABYhunfvqF59xB3P8MTY3hg9sDiIU+PPXhuKYzJZhXK9AAwTpYLLSFdzk5O0/iIHQ39Os7BA29
oaxSGlbiIsa4T6bXv9YWfPUgd/qACeNtnAIWWr5dFl+s6P6GcZ7OD8X13tv/PE0cY0gDE8QGmOLP
hqsjWvmL+2E0L2P+59si9iZX18UUB9pPM7tILwIDxqn4mchAkbHSKfyLTOQVWIekUH+YvZdfGi+k
N6VMQAz9RqY/TW5mtoojM0rVHNV+uCG4k19D7/67EoP/aIRqEm215CkUKwQS0ysPKtqUCkbyqzsY
qJcuOVig4xNQSsXgfOEsYE1QybA2URp8/o3KFO52aWjMXm8t5kCVEgEEKd7U+giic8gUcnw3Tolg
qWrR/ejPpvmglRImfW/+Vf4mX9AAxS7yWTXfdzZe7KRJ18eMI6uawgcH+K8YD7XNF7xS6WsQ1FWL
nK7KOKpzqGk7MqoI8D/AdBX+4rEmjHf3sJ5Sbsj/Wu70esGFP/JE6tIZ3eE4QlXOJ/HWwsbxynTE
3O+ceJ1Sggyaddn3uJaIF6bv5bplTyMtjcV/V+zfhQkJUL/ZjTgcbBDiQ+rlgcl0JYKa8NYyLMxe
PcS2cz7M6xdwoKXJvPfVh7EgwlXtzWDxTsjTNJcYVBAm+gNa2f4tDluGe3yZVDTPk/UlxlH/XtEZ
VDQ/HpaAF4rBxZHF+gCb9yXby5c79Ob6dzocXRZJBMoqbMTuxLVzqiu+jrraZ41gUHZysSy/6GVM
JqevCD7dDG/so64suU9VFnuspn3lmJtRb5mJhPSI7YqGcxuIS8Pk3PinqMgc3T5Iq/GsVOZ9DLOX
Ss7x4LWZN+BM1VX6ZF5wn/T7dCc7a5jS/dDofayh7bIZII+xggQv0OpJS88MaB3guybJrIvblqnE
PvxlaQc0nqV9p81A8YN07ks2wqP2dlMS1k1GgzjqAqpGzLDmBEoA52YscYDHhS9+3O/DKSUfnsrV
g/AXDLfEFLpljfdJEeKz4pMR45F0XeDZhZVqj4dgbxrHKkSMmRWCuCnP7UiHm3PGuozoJ2nBGNRQ
uonHU3LdKiIGdb33OQfjOaMSGD26eoznrYZA0dzGmmXb7qXavXHPHUb8FeNQ4RGF9Y/CEYpdVzfV
btaNkJBxZoKF2Xu6p2jq5foxjXkABJJlrK3Azt/LpIzd933XWawxwi0AmZTEce+pkDJ/eSZp2C5c
FXVilNZFZIBsBQrk5vx27M8uRvb8JN2PFtWSvkiRyx+r1bvvHQSsAQ07eaBA2+myxWEOir9ZI2xE
bSU2jmsL4UHLjHLNDz+dykqPltUxPIm+QUP14WK+NCF62/lcOvNPj30kvtsEFW+MucpJOiTtFziU
tD6FWJ+KpGvlOpJM+nnUiQdxr92D3++nG8J8DAaxhN1mXgnWIMI7hn1MGATBjFV9MQZJU0BSUEwr
u9QeTgK61mn4onw+fjOY0Rn+q8FuSlAdHbZD7NW4ehZ6G9FcuC078SZd9222tZa7/bWEH1+Tnmer
pfyU/cpimYUlEAld9uQpgG6uoQPXvgogx/WfJxzR6ho1nlmnep9yw21cap93oADoNR4JXcocpUYw
L3JFD218J/X59lajx3AmD+ovqUc/XJNxVoCTwfU8Oo7eXDSKPSCvRjfdRbMx5Zoo41FPdwIwLDFB
0KnXcN1h7tyKf5IpgNmP5p+yYVGYdW37xT2Dy9HlNbG4VwO5DPB98hgDpMhp84Js06zhqtjOOvgW
Yu53RxW3wx27ZQN3H1xJ/lRDnPCl7tAyZr1zp8iAvE3xeq3q5mZE8xZVG3AqOf7gS497KlIciRrj
mMahWEyaloQr0XLM5YfCCazrx8SCFn+EkemySn9ODMfuALORd1Pe8bBIPL2eD6T4GzHLkZg4mqVR
gIaIRXt7XW4kj586vhwkSu3p98TieSO77NEqpkubiFKXgx+O2IsDZ33B62zib7BRyiZvwM3Nj1tw
wVjZSO2WuEeYBopfM3FwG8voUGdtUccpC9ZMNjKYypEEFeFhjZwaxd4UOOjHgvoKxjln5nUtbhgR
TGpdalXCBkYAsg0IfgCyf9QYQH4OJAeaCFQW7zHjSy7qyRXuwIEfe1spiOORyn0HymgMcly2Zfb4
Xwm+8T4W0Me7KgZCdssChbR8njtveEtFf4mYxO6hoZVqWKL5Gfof2TdKHOcd9bdFOCFX/aRAXQXp
p3lsTG8CWqhQKTtrRTLy7LC9nNdUUFVulrpnUZcDn3h/IKo9emu/M1Tx7LI46rApcXFzaQt3r0IP
8U/EaV7Y0LrPCVA/L3Vv4Aj3L+5YijZ0tpYSpOH3I8ncmRm9lODn+4SLPigSSHVz+PxOzONfebBF
uZ2K6sEItEimNRj51GgKDyxQFayQuf35xVRbPuOWWCx4nnA3PlRbH2qaqMPeUAgoBuprevkeC3rU
/7Y9AHd8UyWuiKbY+jB8dbR9plHa+fxCLXaDMmdxUhcX6kMk/oCPbSyfs00QZKc5q1uVAdJcG28L
H/iOqHLU7SSLx8665/up/PWzxGWN5Sn7DqXm3mvayJf1rd13ejdoaFrp4qoNx7T5nYPOWK520C8n
V73rYLn3PZUxkFJ8PJROIpDld+344aaYtlku61PZG/1nRxn7sYN7I2t/ANC8mkvxQGmvFkHRhE4C
3d6Enay7KkCy8DY2VOrqwdpKxUlMes/vyljVWz7r5kR47xvob5HlU48T+/5I7tcFSdsFHPKaUx4z
VILpfZcir2pV0n3tEPH1PcCbfvQ2Hru/VsS9vw0GRJ/Zz/u2Yv2G30Pr15FdGzf94WVcjMjBKGt1
7+XRG2m810lpbnxtD+VPwTYv7j4+5MBex8tf39fbZ6F89qef9NbxyevOTkFOGYdnFmX3fbl6Ym96
uavsmhDmf57LMn7T6l98mNMAUhG/XnUKqTs7i37M5bkDTsiKoqVMmvz7MxDC80HTDRLCBPkstlm1
FmByozehVlvx9VrkTWvPsOdrPZ7B4EkURfnOVN+gZ22qI3ioU03bum6eJtLsGltzSdSFN9kTcLGa
qHESMGQNzjaSbMf6wnuVLEm98I4avwloNMEzTEiKHLUUN7SrIuQ3m6sHjr5voPGxYdKV7dbFxv5K
RPmd3ZqQ4kqgW/L+IAw80t753SmStLDTI5MwA6nsxhr7nITyCbwpJ8YDbllKy0Xpu78vp/ja4mI2
xtcSXF1lHLEfgoisFHCX40GcBYThD9nh+ifNFR/omiALZB8mD3WF+z8hqGJGPLS76+D69f/opp+X
RxmQbldvt7a7fYYUEO6DVPvavsE+mMQW+u+3f1sjoRyK+p0jsSDi+AZwPeUp697C4gv8X0Wl6c8d
Yc7OYGw7q6sYOwhhW7PfA7Zx8g3CEJCLmVzxHVHOXnuZaUcQIEyQxQowfID3yLcgygZKA3QB+JIM
1Ct8s/LpKop89E7hd4jvsTRN6EdlI4gyFMh1i2MJFlunsaF2femM3bQJ2BFh+xtdQDkVU4SQltrx
R/3HSqtgwSBwd0Il3nB8LbfAXI4c/ll1cLuvAS4KgfNiVPu+efDQ0Dvygg7F0gACBSYWrb+KGq3H
jS3GHzZrD+gJFsTUSCiY9ZvXm1f6U0GkDHLnbhugWjdR4AUK0J2rYbDt5PfK4YbxR2TjHDFHFqlN
sW74jgtP9vSpY+BnuKZOt2FmBEfIyS12JrSsURvDzsjfdB4FDM5E2Q8RbkLLRv3FXjEhdFYkOWQk
kUbxB93jgrJuy6obqayIuRtiXEnmw/ltArGoyYav/tfNKrJQPQ3JOh3n5+4ueadf2cWVvvDeX6at
2nBzYPXkif7J1GZGJpVneAsnq0BRMxB+EfNSSihNekXPbhWcjEH9iPGMDcO3JleKneVu4HNn9QjX
G/0gL4XiPaTK7LeOec1dfVqyAIEn3qI0qJDknbamPxDbr6fY8LK8YS6Zlrkq2jVHrhgL+G8v1XoM
1eVvfpnLcWviptIt3YL5pwUY+TAIpVM5fQgLwSKvMU4qyd6Z7iczr+aF4GW7gRKzvgF3lmGIvCdo
pfDZJvMjifEkh+xHtR0pjnAQE1Dg9yaRBq5oYn1zwyzhNFVFhTv3up3H6RRpO0/o5PAu1tgUZ4lP
5QmRuO97D9QQAzOxGu8rlLDh8UdU3lfZLthR7Lj3EG55NX1ANqT4n0VQgl/3WzqO8BDgKXUmS1EP
QYr7vfQgOzZOfqupSI+xEzLB/Fi2v5lQxHsGxPOyOBFMrWY0UofCg4ujBB5gOSGYoz63JTiRvljx
uCCuMI5FaatuAjrWaV3fUFPQy6BV5Cc1d4o3LOZiSlnw0+E3gp9xIQh3yB7q+kODhw79Nsbxp6Mc
pghqSnsxD+hAH8zV7mn+PFsQmVHlfM7MD62Yo2KvJPG7DSYbF07CUh4HcwN+c+q9q+WsEvQTE8PC
TdrLfuXmU9j9GAMA7L0vVr12Ezl4RJynnA0WdYGPv01tXCKcMX77lXBaftGJ4IG6jRgxKsy4d7jt
HwlH8tjlRDwmE28j2TeQhefjs0Ppgqnqs1bp0L5QpNRfLd4qbtJZL6iPozqsfqqUC8bw1DcbEaL2
29oPcuBlJV7/xuYabOey9+8/rzCB6oexxF+0SbEUHVPvCMMsq1eL8trvxU1o4SF4WfK8IIuacjOl
c81XCYbOTDx609I289y1iVwGpj16Ya0se4jqR3fLEaGJFNVnu0+V9Cq3tbnb73H3j9luUs9kEoGd
mLR7jtQl8KL9iIbf4xHQiq9F83WUDiLak/O/AbxuTBeKIUnCEPg0pUX8Rl80A+32VrETBIDODB51
R8ujnh2UQqSugqCbHGIG/4dEWPwxL2R+cMgdd0CdbilC0QqCmSaRza7c9QWYB0noGLkU9OYhWtaf
E55V8ajyuXGPXXKyY8bS6gRLBLENKYYVgPhcWROy3uA71jHHWP8djPjz7jx/GTNGslTq0ZyLzcc+
FA9PwfczY0m9CF6Y5mGWwC0X3o7g9oEFkEywy3m3S4sIxIV0BHevK0tFSzoZoI9Ek1r2yn5ML38b
BjoWqMu6nybZA/AkbOSjPzlRj41TmrRTTpsX/Pn9er/0Rr0PmGt2h9FCw5lHh5RcYpKC+iNZL9rb
7hBZ+1EBPL10l52AZmVvJp470IfK1QAiBZq5iSqwbCttHyEbg4vMtaaAlxssUlyXpUQcFDTEqctV
MlSQH8dmixWIctvr53ho04t3poas1JQzJObuAzSdKo4Rn9iatvGHfkpIWd9OEU5fICCwTPxEkm6Y
+/0xP3vfEmwFQ6VFszHtz3pVsDNGuOu010C4/QSAtSvLyUtE/AixBn5rnoR6aDy3S08rGv4Au422
KmERgUYP+d5jlvkN8Jj6QVf+HkHiU9S8qTLRPA20VMoDLEAH2CxoYcpXqHFXinGxuNV5HzaDXZd1
0d9qq+Y50Dltdkg2LAhC9H0B1g3wupY10VwrO4PTng6koae5fDHkOCtVlB3k5Y5kwlyEYA3ZYJ35
r1m6zZdFQbILRoZ8bUXEfe9j2dIC1sUVQBEjFhhbhP+6fz7rTFuWlNDPFppDOS3GfLHdzJxCNc13
u5iiRx5DOVGndvvggY11YtUEx8+GJcaonguOAerZqCLKBP8bK0g6LEba7F20SqjVFvnt6wRq+acK
vbuG7V2fceithePAbpZBH88Ir0z8bHbf4JgYw5PLvfcR48H0+hKBkCTQzsCeJBMt5IZQh+9FK1tG
iz2pPPhTKGev9lH9yQ5kJltKD86LS+ToovpaTWJ/vNHOR93kPnqcJOo0dAkqNU54F2hr9gwVob2C
oiUM1Atzq5PT7y+cbJ5FlICeuwV9uQPOo8qINA5KgxUn1rcZK074JFWck+81wLCE1BSQpNNRrlMm
9MZ0ZV/rSPpDns8J967LuJ8q0dGLglolNn3KAz7/vsBifeT00rh++tC/rvv/PsKZM1Ttz3E6WkUl
kUQKmy7p1J1oZ5+gh9J3R9PJc5jXfLSlfRM0gnsMPzodOVXDVzT/K8EInEfFRb4c3Frm1jSdABGv
vz2X2KCUkDBlLzC7HkBAN0n/JDZwAHHN095IlpTZYz0X82mBF9HQdHnnPpv68f0VESW+z9h2ebkW
9yILIkwNK+wWu3R65OltdEGccd0X07dMpSeyRUSWYreWGyn5svyeUgwDKVsQj8B7RgNkNhCttobC
XWNgldzFQlHEH7VAOpGTWxjfT8Vwx7ya6YxtisZCQbon1VOZkbSWjAnbunZoylv99/mxKhzAuYr4
mnVznUO/dwCdCN36BB+Orwn594S3RGB9z7WLKrBOFw/7LUuO1sAxxBu8Oj0JYVqehB/Jyrwq8/iL
gu2T1LUlUMpuI/Hd3ES9kQNf3jh4P9Lvn89fwHszOWsBC0MOJ+DPag4KTevaOmfdLLQtjYmIfsux
sVSOQhG8dWztvrjXwHrmLOpVd6aincBAYbHoUG7XMiTdINcoxdGe4gQ5wMTY3f69v43oPzYs1Hcq
JOApinSvtDsuZ045iZyJK4rBLxiBKRSiFneLeXZj126eMFRMoTuv3LwdlYBfbNbXXfGa0ZvnXDgA
b4VZ9mz5LFieDwNE6tOeYoEjR2fffoUXPrHpTPajp2SRe/KoHneLwxDUNLl718/+HAw1v15IWc0H
787lW3n5Y8aQNIzT+D3s1rW8Ow81fHgjWjSD0Z6R7hCfEcMRbAwviSqIgg3tZlb4X6xwKKiru/rs
cf3sqVNIpJdjEmSP3eutN1k60ti8NazV8EzJ4nLiPZGpNxDqo3a+eC1Jv99/7l159KmWuQOYfYPA
f/c9ko0a6w2UodK0NH/HF02MmMp/eC7RWbPYEQzMIl6A24FV4lP/mHE/E2nGUa89xGJSGoDV+w82
PaCddqH7MPVq3r7OAdObP+cZUEphTleVbe1fINX7+9ovSVj/o5C71PrnvzoS5v/KLnChxIDF79gN
KQrnZwElmmMddO9/H3fjpY7QEMxKvkT+a/qTKHRsJxQzUHsRe1G1eo6Oa+Z0YNlPfTEb9XrpLczm
33LvD0+1nxF34CjkHM9qcd8EodCr7tjSJJmMoiysPFl+U4/QySp91zjQOGvgoEFpprBAdNLPUC/1
Fu3lCsZ5HI0IG9iQ0Axo69aLH8yU7MUowhuRxOfHmxhM58qp2PYp7xybqXzpdKwNqoi+zK/j6m7G
XGxXfc8glB0YsZVflvlDHXH3PrwuMU4jFBsmH+Dt++NvUOJes94vkyYKobr2IFCvQT+xysvIqE6b
C+N6jsx+Pl0YT2y2J2m5nvebv7r9FOsdD6nZr3WVqRixpgUH7oixs4d1iiulhHA7pYVltT8PfR1B
XJhS7G93AJRbMv4rNpO+QGw5Mn+47memYn+r8mcyQOVR6wqaf1SGk9UVUvec0OoSIS9tUYET5TOU
pHDAGzlEGM3CV9leoWOvbEyr/GzFwYPZFjFjrAa/uTtEGfSSjMv5I8Xl1yadN9grAX27fqfyZq2b
M2Bz7JJ4tJb4llzKM5XrXW4gYuTUchG28BDEY3C1b0IDwc8dz2OBAwmwBFv9HxWVKe7wx2lGdOL9
oEp13zIugwjWwk8VKFdBOzbA7ZIMUndKE59jIXombUma+7Ce5Cdbv2cP3D2C5FgNnab/FJh2jXr0
XrAhRUKTnJAuGBYJm29bNgLTl9Z65usfgo2vLECocnmbj1gOCeZf13M1U5YAt7RHegEffNnxUjRK
7nUdH8OTxSW85ivohUqa3BwG8GO/IN8NaC6P0ywihScJXFDnR0p5rNlXabUifMUdW2A4CNixuQR4
bI0i8Sbtl7E3fv0MxfKd+kOU6qsyVk23vps/mtaYzFVPhYlgyZiHlBe6AdJuTCdpXmza68F0lUM8
lGoTSsuq2JyqRXHW1kwOno1Nu3m5ahAKjD4lVtrzZ8wnNVH3NTbMYQicyWpk+KHuslFEecVMa1zp
b1oKHG1OBLv+3LTejhoaxAvSNhes5t+xjXW0ItXfNZcD2138Vg12W9a2CyMPptXGSbahBCmdoBBN
A1mFSqXQhlnlA0dPBwdCP/OtTi+r1hTMrG3D3zLQofFzD84C/tV44h66n0jWpCHtU72AN1fslVp0
dzXIIky55dux61buoCWu1prJA6Ypz4ssfoDsRkB84WRWCkCgfGseWcyFL+d/QKb4AY01b5C7tbDT
aHDObGX/v6wmlQtYNNfFgZr4ZdGeqBN1IIKCzWXjFqBL5psECpJx9eUvj1igcVv+n7irOgpCO6nk
mmUIOYDK0iI6rr9VyO19vXMSB1Zt2D4uxpZhzWg5pQRLWI8I0ISpk6hdJvI7QbROLRJXf5X/Uo3e
z8FUcOBbX+LrVj3FhdZnAaqaoNgRp6CufCLXhqiYoz4uoxR5o5ot+f4RcDW8fIDIGGn2vC1WE2Tz
wk51kLDkAIUKhijpPdOZ1SV1tmhZZLuoBLBAlK7Msvb91ukR09JokcPM1InG0/tz0t5CNLW8OUgu
QW/gS8cm/OPz9Lg2zrrlDrMZcW0VRtF0DySRVGG0T+TM+1agaqnNUDaUtY+fisJ1pPfHISO9OCSe
BC6U91f0z8H7w5mX+qqIBsWhG+PxqLI2ECkR4iBDCQ2l7PjE+LqgX7rbsO2HeN159n0n/oUsKcZD
ZTtBeVcwCwuJeQ3XqERb6uq7QbAyEGflgalceTlvZ6bMe+oq6dUeZzWoBA7DrH+i+yfLczyITiNV
2fN1TDlL13IMBvW6ALjI1jRjdOS/fl6hg/3VEXpJ5aeczYXefYj06GFg1UZVjmBH/XKV8TNvWMI9
li1jP7DE8jT+VWjedxNQmGKjqa20uHNpI6yJ2gbE1y7Yg3ASgFX+ZfpwxDTobYf4JG0fv+moNgB0
7HnxfdsHCjVA8M5+wcHdDMzXExmSq1vXz0s0ZHn6XFsxSsANrOUbqDbdSUnbOpQeW1R5A1I+wIz9
bVScq3U69yZEIX4oLuHTc9dRT/vfnvW5afS3hVpa5C/fJFeQBFloGwPfm5tYb2pxTHJup1p/YnYJ
MmU00W5p6j7/+8y8M6dcWyTHKGrDwtrPLFvjZ7P1DQ/aKy19Huwo8qWfsnki1fWIHe3D1wn2lZw8
iZdQcH9LJW5j8OKROFsh1hkHP/VdW90TsGccTS5knuxR0adTWKrAeXSYnSfICy7N7ar2IHTrrku3
auNtWVoAsVGvV23Mdlixd8zN7DDj/X4IJOd/ZPM+wBfE+3DcOV4u5KrD8Wa2o81o1qyWP6wvnQ3X
8ncD2/Mynr4MWdI+K5Z92w8MsDQGi43yzbiZ3QtPRumgi95ZR2UWUawcNV/EhMaZ2thjAJaRk/nw
t9J7JJ4D712QsAHvYrDkN+CrM/7njbOmxxIvNoo9Fqj81VR/7Kpn+fOmT6Jp6Q4HQaJcqCOgFaVz
INRq0tXsxugOqWBmEkHOb3i5NUeNUToJyNJ936nbMXBZz51TeZmrlUmUnvdyOdDHbNGkLRmJKLhH
Rokt/OGVyJC4gwB+LezKItBMXUpngo/86mxlAFXUZSyen37D5c3aPipbpOy3/QnRJnOVp+4Y1nMR
xump/qeh4rPfXBlHwEdzbODjAmrAA7Zg8S+4VXVhEQOg9227uHjneV5aZ2NZ//B8mBdxl87DOkj7
djlNUTGucKaaoXlrk5Mi+jo7cNK3Vlln1g6ozsmqUZ9Iy7iIuuPep8jkRaBBWLD7QQUAHy3EbBMT
U+FgiWCM+7N3pTqIbqRQ9NnnQJzlmySjY8asnj9LMKNAkmW9bv86JkTUfl6oH/moHx6Ah6PaY9Oq
hDXncb/qy5FfiXRXqkyRlbn+r/LM9ZqBoSvLncztGZLYpBvNCxE3szYYJgDAzGAenAnuIyJoiEwL
bdwyiBS2J6IfKFdW/mLc7tTvlDBaf6BTYK6Yqayaoj2bNXlFuD8Gj7lVtOc7XUW6YQkK2lnKBCNf
oLDm8/bPN4UuxP+oN39wcT8eqOpToT7tFJug4K0ier4PMtetdgmWHwYLHdqe7DMKidUdNfuM6PkW
I1tR4scN3h0niI4NgYTj201Dmm/KSrwdrp1vczsZT+2/zHz+zXZ2mpTUu4+uWverbCdFq2HWDXfq
nEW+TmXkCysghzWpAmV4R8Ge0MYBWGT91Pj91ydrN1P1prd7g6rgVbb2rFjhomVS5p2eN034f9CN
CpeCp4rlIRcDIkjokEK1DyBeA4A24AdwJPBu2jWRqWRLqzSX8jeHA4LpCexmvE4fkT4SAKPdC+lr
BMn5tFvekG28JdII/uioZLy6tKRfQyXmZpODm2iUerlcEPTYIGKcdr/D4LNZmqxxM9LoOPLC0uSh
bRN6gfkVkhy2lnMJxKAyFzhLpztOahJBXHUPosT+xL/zcVQa29h64pLk9AIGeeEM/S1ZwdbS8sUp
6qDyfHaJYN05lMjYosGznEgiCxLweepOLJnaCHuxuxG6/FK8Q7IRqRMcMo23jXOCyZ9CWXfLYLIG
8VjKsZxpWJkhCzTEiALc2AzL86R1BOr7MnrVHYC55yFDNHh6qeGhRHWnOBM0iGEYiZefGX+xBGwR
pH1wBdyGs04+jp25yGBSkJHM0z1vEpSO8wLZf+APvZckW2cR8BtirsWx0Px7Z4DS1EQfEyHn7ahD
vy2f5DOiH/j2LbEgPSMfulsOjOKUMQUkdAHrIiJfrTGNiu5N6PyqrEGXOQ3B8ACdIvs2+M/sihA+
jFK+bQue0+vygx0DV4zOFUO3EZ6opd0lxfpglNov6EE9OURE2P6LYdMHSVId4Zb3zqqQvr0ff4l/
cRhS8U67QrhDR5mIww8T3Oso37+UxQ/kPZbvgKFr1Al8IkBLx+LS8B+ZhRC0c3zXWFnGF7HDo8yS
bpI/LRImHnwZX88v4DQ9QwKljVMMDIgYkRjf7PERRd4P3hRHw3Jo65xQKCEYKNJaZii3hfdQiNym
ge9i1Ld7maPtqdlssDk6poBVFcDW7Na4+YqWWR8O+aBjS4nG6H5KgTxQnW0j7i+cAYQi5dd/ksCC
xIFbCmLjvbwDKmYG01IA1QGaLwBgTJ3JUvss+ASA+wBy1y1/I58ts2cDzB6/1xjA0R28+PL9hFyY
hAniTszBBpL7Ays+sEH8GWEN9cYAS6esak2Tr2cyezDQqLCsVIECyRQ1gu2jRMivjbEC2DyGPwvj
E4FSY9yDJmP1LIJRx4oJsAsPfFr+00gaCsORgZPwdvM2Bg3AqDSablX6OdhaniNVhIxLcThNnmCP
vfpnjB8K4UBBfU4Uk+COQ+AFfZaZIdRCsOvKn+Gxch1vkfYYDboL+d3PQw/mmrnMJrslpKZm3KhB
WfMrToxFMNbYy2WOqdVqBI1gnmzxoa0BQwAudK1Ixoq/YHcpmxSjomW4kOuJp1IyLzGpJ7wybf5u
/+WQ1As2ud2XWO40TaAYqlaOyDkj/YDwip88gJ/qWSr7KrC1RrCQQxIIb0rqFd6Sbe7xqe2ynccT
npBb7UQ6wP3UfrfPXHdwMxrg4b7LCPoF7ReisCYlNIUV72XfnepOQ/lwuKUqCNRh1BZOifWEDKGb
pXJhccPwrc8teUGSXlAe1U+rDdJaao4Es3m3z2CxSr04ut8tKAzuRNmInrxkucKbHH2KDrxrbBUb
jzWro7f0d8Pf1axeXV/afKYgQxwR4c+TAkWMCv3gTHWgmLxQQfw1zpgAfmMwfMH/i/8P9P2tfn4r
+mZSv8lRPAxfFxQ8p5kiI+Kwmopgt8ArY6erFtZ6kRIb2U+mbhKGi8SkGxPBKYdu9juu4Zn3b1BW
rRy08JRAQqOoiUhumX4UMaCVXK6jaFBh/Oj+Hi18qHn33U28d9LxD3nYBFbAeJCmhyIdjuv9FP/i
zXytXbvWj+vY4DD/YPIWmiOizuN9hGZ4VsColYaxmTcAFPZFciiZEiTUvbCUTCqRlDIJRJX+vkEA
Iq3d9qH79LOci455HcqHvBSol348TSZntSIsnXc8UwSSrjyJ4M20ZIzgnztg3uMt+h+brwvIaRAl
BSnqqknJdp6I+liV7plU4N1HjkhoB/mEwSe4aRMVqaafnJRlXcVcsH+TDAFUqimWxtCnBqRN2sTv
ay4yGyondVC8iVai/VRGdCYI8ZHYbgmQeVdmXjw5B5EOMhvYb6pW1BlWX6/uiQprKX1tYNUHFO+q
re0LPxolYFTADYuowOdmalm2wJ8ToZZJbCASZwa4geYZxWP037osfKsH4pwaAH1YZtVLNFbDMCuE
CdiOrwOaYk4slI9ikMp8D4zbcA1gid0yQ0URfGB9ZDNxiGGxcqwrC1SgXnxiZbwp6spqmmrr2E5D
8jAdQWx8hsjpUT+HNrLdTmMI8qQcZVdVRZABLDAVT3j7eHzBDoR6mVikck5tEuUwwaxhh5WWF7Qw
0bFV+yPszFhdUjzRw/xV3eHnYxIK/lJpgazF7qh5Qr3yRCHVClBoZlOXGGBhGxVTD4bVXD0XToTs
dxYSdO28+8n5z/30tm+kfJEpUEkFFjr0NsVJEniK9W/0ohq+Scf8njiPlJGS8szK/H2CjnhPGe/T
BJ0fCYBrksK6QjxLLFw1ITYpfMRNxCvTmDECLWag4B9wW3ikhrom2wMY4FJMvc2D65r78ZX7ui8t
vQqE3wEZ09KGHteNBAHyDzyVdmUIS6S1B2YTh2QmcM9fqnnktxNYLtSM4gt3L7s19FJ50YEwIg9g
ouMWDd+CdbBbhgoQJDVDuCqysJyOfQJw2QOvEllTeKUpGZOsvrcLLnZ4LqyEokCcXtVh0ik58CgA
I+qtCMKBgWEXY3F4RBvI53FBzgypcpB24cnRwWGrrFH9i5pYCidVsYp5NETvZQCVEyn/z1RAP/Ii
rtZPrvsCEZFsD15FkFKcXN4+6juvUcOl7cmwIMN9bPyI+6GIXB06Q1w8NS7DXjceZ8J1SSCjZ7VO
Ooi2Igp9saL5SOtd40AgXyYqoI18zKUyx9mI3FFLcbh6kAw52dqspC1nEJQud7ShCwXdKT6mdCF3
/cs3m87S0IhJybNu2SbjmJCGqbze/ySj/s5yc8Y7+JtJ1ri4iEeZdzO3oqsXZTG/aC7z4q9t6Q3/
e77qcjOYdsLBWen2XF2DMQQ8rM7jWs1Gmnzxer6XHvyZCP/H4SuFQB/mDGe146TmessQdBMngpOc
YMpZMgq5/dCsNKvl0ABkDeu0ayZcPTlWFDvs61fZH4NjIoI8WI1ryusxTv9gP9OAmLbCOYxBQ0+j
RgpVdpTp3rljytfCXuUiNLlVm1DhsiwzRjsgsdu3ZtmEt1lU3uVcv0vj4+YhHDodbuibmeFyR88h
6awvJZt9fxGYT5391qEnp4+Ry8cSHpEwMUHMN6JF0qy2zFZK5Pjq+I/YrgL+OCBNR2DMYZbhTOsz
6297oLh/ZugaMTJrb6XqnJLlvDKVmq0QMqlHAOgmcvOesgymOdctTT8VgsKBoQ+u7yr3hvuJM+zr
a4nnOQ0V6DkNoIfFkGGeUiaqmc7gA33+eLJf8EQJfgREaaFdyPreMNNiFgeac6DXCHpSTf1c/3Tv
YfchnraU4koIZlwwiIE4DuaE62GHHD3UPnjVTTU3jkTxaPyNh8zbqu34vSeLx9OxMWdmwnp+S1xY
xPnKWbGv0E/WWYplkyBC6Y4chczNJUEOy+HR5sHJ4QDB8pk2lyvt7hTfQ0zYzPFfDBb3t15cZPPn
OKEgoqdSzvHEgkzyC+IT6iABmfUoLJIT4fVlJ3miWvCOY3ItfD9ZFVImqkL0KEXMW3OZbi10Ar+G
riJBpyumqkOFRMd/yiEUKceElk25HKOktv9xbE7RlWamZcqdLEiJjROaG70kxXeimX1NXxF5x0QJ
NSfnDfTBKc0+aFvs0ncWc0QD1FuKCct+KB8FH5XI1hEKIFnl7UyYzzLwawhsXdGBJSgVdtDIVtNM
wcx/sYmSorKcec4xXGyaZ+5iCp0pU6duJwau+BsK3P+FHKqkPz79e8kWvb3vmRquCCibknqo8J7W
+tkw2CqG06mo0yX1d7pV+V7o1+Tn0WU/93K515fH6pddPMRu2mFPt3GbiQthHKF/NsjEQudojxpv
X0tc4VY6yHqlMoXpEP+Y0ABbo2b2WOFr2N4/Fr0ruK2rJQ2fJEwDg3mFvwT7K/Z1z64fVeIFRSr4
dQNUQ0heCVh6+CiEjhP8CozUdOHg5jGtGdOxaWIcjBwHmb2FQtOfwvv2IWuA9kUEniNBWzg7yrzX
CqvzD2/NNc9+UGY2Qe7P0+rJV9kxaSsH79QxOkPJdXA8w7Q3ar0eY6helybr3BLXKwiugfb87UJk
cRhfQwYLrOh0gOASeeQudI9qys6GQ6Ry4MY4TWYWrbftjQCQDOC3opt/7Gmyi2IFFSyxD+a/NDDW
25CXLy/Z2e36YSe1N1cU4/BeDwmv7UAq8WwKSpxpLTqTVAcJ9BRrYkabKn8zTD1tt3B2eFPHITvo
+tvbwbsMuq4lnNGkhp8Zv26ST8P7y0bhsyiRiCGmrSr/WuM6T2DXG/9MOQBQuVxU2iZFO2NR6SB9
oGBPMoQWMgsdkynWxQy0FQ+EDPELsr4J1+lyOtCyte8VJyvxeS65xnyzNA0QJI7f86eUJ0aKuOIY
MHJRzdT5PiPsoG5BI3bg/tN6gbCecpzXonBafj7mJB9H3BKEvJZ82Bdy7ZqXQgZW4/lrYRljB3Y6
gmk6rQ02A8FWefUY/m/ktxxAx4kk2fR5HxesfOMAXnDDOZicZjpPrNU837EJRxiulXUCB/nKpxyX
lamoN8Oa1cMFB89WQ5vyoz068MPyXOB6wnWsdSYZrPV8qctLJ01ITa9DiArFXdh0AtB8TawhafAf
CMotxcoL9QeH6n8L04dpoSxcFvMZFhGcq9JTC1kFr902V+9Upa8//KqAOWpkgwLjc0rX41Mhf1jM
OqVWovjgmUHVRXS+x4AbpfsQ+9hx+EnefJUuJJ36DbvyJmWcsnBFhGOtHmaHaIlSbEjeNsxGT2yF
2MOqFlku4d1gT9UowtFq63KSOvzMIWdnalqSbtAL0mYEDKwRMj0F2mCEhrwawtw+YneeOMGz9ihC
r7X7FzB3IBXvbZWAxbssJIBOiuJXgOFjhGwkBjBLE8KkOdeQscW4N6DYHDrK9RzIymxH50SUQ6xp
INY2aewc+TSPfx+S4sNPbPxx+MMqWXOafKQ1+gHkGGomQ7ddffWMpyDTqtSUcJ/31oGOcer0ii93
9sl8cbsGR1xJUnpYtWR2SFVEO8SJP8c/zPXRyD79otFxfMc3rk4wlxaIQF5pJciUqVRqKnkan7e8
qffnDxNTmbArwAf4PRjYohQ86RFEIGyaSaAwXxq82ZJlFOh2EecAkeb+EITx68sCQjB43E21aQka
2XHSAX2N7yyEtO+YbktURUPQLi7UxE1+h1lw5QOFM6yBCvkynuWHqs98V0FZw9iIXyTmF+Om6W/3
iZhflFcKf1XHN4UDVIU6RV7CuMyp+5odC/Pb0xEDxhLXmAydAmF+EVDGQiqdHwvd657yE9SI+PEK
ghqnPTNGXzT3v+s7+MvKOPNuIGLoEFNnJEPLHWmjuJvjpv4V1hfkwxw2PJdOmd1p4E/KVUV8E/37
gDI9uwqOaeaxDvxBfn5TqWQ9hj2wtv7xNtzEd/J9mJENqEAbfR00ZRAHpTO74ICcJ8+SrhFyevgy
zFzr7zPcMuFohHTxEwGRdi773b6gWqSB1bRp2FFT1ZkaFTdqxvbLSznQGqnZQZQqda4TK72qdEWj
bFYBDMtezCTXGgAyGcSlG+NCbcRiWz2npb1wdumQO/E9DSmvqEM9x+K/pRmkS727U9NuB7rUdqpJ
N8L7sMPPpUlW0vt8PFqXAU63IjZVe6yKOiyAbl3lgLxqy19h+CvT4U2PE6Ax0Gk+unzd+0YfEqa+
/f60aFBJMHmwjN9l5+pwKDZi2ax8VdErlIqQzKFpFsGFak1angFIvwpMWCzS0r0tLSbjOKFqRVtc
vlaom3fHtuPr+FfZeK+PihzBjASFWAxv7SqyuOW5iULHiOYyuvuuvI+DJG63gC6GSH63XEdoUYkG
Mzyc0unzGwBjS6jCDFOaQEmYLzALWTr8vpWJ7xIWHzeBemID3yolXm467Ilg8s7+WFMyvADeyal/
5H972hOucOdggVF2mevnIIwsOrub3At51hxiwe571qwZArk3FmcJtuvbK+3izEv5/d+dzwLsjVL/
Uh/YVS5iYuLrOSe1XijYysY43YGShWgA6gqggEOgVqpdRmh4KWoBnC0HzgdDtWvzEOSpHryZSDCi
oKap4GntWp1s4QiylpZrUbHdt82bVsGUa/n3nugvEAJ3kqU3u8UR3nGzXbhEIVbekEF6ZAfUgOPD
1glBddOjGL06avTDKoM4A/gh+1y2zMOtHJnj7Z2XrHkseip5eoQ1gQ/3ew+LMtEKso/Agx65OaSA
c3kZAPKXyLcLcZMpbPan2JNDzLWglbapYEywZj8Mzp6Fo/H406Vwg1IUT3zM4bXTrUrVg4QRNFPG
ahZryDHSp9DY9QzVsUB5/yqIYGjfeikWfencC4KkcIPvV86fjDckyLp3QwqiRXLhD4amfF7mie8l
XJGbzaPvuQyeJZiOwt6k6SSQLjZ0HafpNPqcFDynyWPlZYHLJuarM1AiywQwO4rK0VGmDQtyT2Jm
gm6/lvAeNGOTfcipIKeaPs3HjaSmyLjeAY2FMKrfGQhB+03JO3JhbwyxUFI4jyArHsUdbKHuaOMc
Tn+sCV9vzGP3J1V/TMHK29eTzHCExUyarZ3wgcYGg+2cEZWa+26bfJgswvRKbZcaYGLFHMs65n/C
yQiC2JoY3cM+VMJQE6VdIiCvvuxqYNxHNcs+OmcRgsqyemfXvIuJMtMAlvyASwVkix290pWk2jFq
PfBr9RbWEMiPtuQN4Kz6BoyN1sAb7RHxFS5IslxW/y+VB9hjp4GVstvPYI4elNEFWynKu2QWFKg+
UCdxmS8j2/dXkj0rCUEg4f940IxRwdPxa+PyCMRfmeCc3wnOO/w6I9IuhAtgpff2E/i6p2CibFvP
yAOvkmfMOjkDp0c2WnMQP2itIHlL/Vp+kiJsqbuPVjNuIiMFMyCR0F/N6prV81KknvU5PwXqmNC8
mDKiQ4iMtCTO/RPwgbZC+WzK8kQLhG3WO7hdjHr6p9Jn8VUtQXKxS8MlWnyhfutVeHsKAl3tvjmF
oHLeiyy5PM8dKZ+4Hklg/0hI8oMAlGvy5zLuLGklOnZ55AZRWYcmRra8gVKprUTpIyTaitddcAHB
Mu4GuG+5exZOkBWHiBCSM+j3d+mLWFSVPKX5xspOu4Nzx4QG86yYs1U6XQT0SLAhXa+4YTcnFrpo
rl5M+kq8jE3KM30NE75TdlVY7QJt2ESXCw8YDznJ6ZO/Of9H1poSzOS1h8uk97i3L3UIJqES4g51
b4XjFMKUatQfMnZ737ELEXEc8AomLZ6vPCQhhP6KuAsAaDyl+1oe41PhxG6tF+DRigGZYHa+WvYa
1pAet6EOEeqJSNxfy8fj72/nfqWbxT2onte5kX5Vx1JTcnAyZI/ysyIPnVlEJuU9mfGkga2I9DIa
SeqU3P1V7vwexKxOsXIeMnRnlZ2+OrEmRVYiw7wPW/h1zYO8z/W6qFaMpx0ny9stbBV2tlzW0zxR
5xW9AC64w/11ey67aT2nZMt2edsnCqHy0yjsyQVvCOe2IfRIBm5HI5qk+GvBnCKE0tmRQNyfv90e
wLS9bqy1LGoaSuf5tldO6Wltb0+j3P2ydubpW8VD3CgJhxxGQUWvOT46IOPv/3NMBk4GquzRt3wn
NJffJ1RvZaxeV/6fSNF61AfSxVmN6oAZK+czSmvXEoUPuAH+cnUh6FATW+vVYW6wxY/yLTYu0tU+
H/1coWGx/ExXEHimofqc8BIyQ6X2eTZaBBmlgEQi7j1QwcacnpPK32Rd4ig1t032pEnZ1hZfll7h
FJt+iAfTQhZfsf8Y+NlelsnNw2Zns0Mm7fU3ugFCHGBbdLcbslCLfxJGkCLafoTI0oL4C9hPpVsc
kpvCv66nvnTc6esQkN+Ev98vrHRJfp7SxOhBIq8xxiObfnxqH4HkHI05rgDEUBKJn2/E46l+zte3
Or9MIAct2FiT62BmDzYElPfoO5Hb2Z1Nfpo8rLwGn8lZfW6P9mdmEXyAF5oLbNlZzfij8DsSx2eI
VgInQzpJktVqJhhRA0a7C/TVwfXbY4eCUpzEuN9iFLu23A/4vB7Fd0DTrM9FPHpaGkFB+TIxFXEl
wLtWNc+ToC1Skan0YmQ3qcQPd6b/8nRhWZ1f11S47FkfmzwB0EoVRf7iAoTrVOyV76OEuaFMT2uI
R8iQW4pBatFpQDsTR9FQAGxOAmRyBgTmWIX/lWrj+8MnGBGTQseqDHPP3+24D4JcVxWsoWa+5CYf
sXlcn5jd0SF7oJC9SSTtJxIt6Yt56AG0nJrK7AS+bSHXeY3a7BD2dBm3uNd5rn+gMyx5eKGwDeAh
NHu98MOKz5sdLk3+gkvdQYkPIUU6Q3/iOCnpxlyNZM+EYUQXJqtNxuazvev2sRNWux2+Kd4uFcLl
vRKQyievzntX2Bx7vrIC8Ozr6DKCZSAzZj+ZufqTFSmYI8OFIQ7kDyc93cilwqaXs3LAne0qshw0
nG3Z1Ossd+KUDLSuZI+IbSdQaG8KICB01b5Thpc9cd6tLlip4419ymqjxl+DHFyE7oXXhyOihGpW
Vvnz9K1XnDEc3c2DSwDj8T62NbisrLvihXOY7LSAiJ3rCNuTjItyOVWamjCb4GO8+cxfjW9oHn9a
TmriU1ESYdVHGJdFXuLhn3EFqqarW3GKSSHNCvIPdx5Y+uGkRfZSMj0TQHdMAzErmN4Jsdr+Lpfy
EzYdI8lo03ZmvYhiGqGcNgGglh9TCBGf8kV4M9udam1+JpWZj51hpW5hn644EoYYNJSXZj5M3s5B
VrCbvYAsJyac9mKGbFDN+F+y/Qm+EKgL+fwS/IK6L6qlvTw4SsTjzE1W+cVDRyBNdIDPYXKtgMS+
e+iDdAmcnGKdHJIBNrnTN07/zpAGxoa/m9Z1hlikcLYfCwwDMhXDNclXnTJqOEOq8SD8em7S1Xfv
KUSC/vp5A6PeXiZuwqzuX+uucAkGhRlJfWUcsUamvF3Mac+VpTXx8W2Xopkmx+OkzPhV1C9MRAPb
mM+GAABAvRCgBforY+77JQ26FvVX80D+oOUObLBjgQ+mOcyYTJ+XcB+/7qdEysAgY27DU/9CJy9c
G8HsHBwaX4VqlDdbkN/G9udpSgqNMBrXEFwSPJbHAwoix6kWRQsARZw/I8dLT1/i8DzQ4NQW72A6
KfAxON1e+uPONuVRRttNMJ58hrVZseNxZL7vWK3ZYOp7mWupJUc/cQDmRp0b1ppMvhOahbm9Njje
qoT6mGh9xQrwK4UDkJ8MzdmewQaZdUw3irFJIGKM54PE5BD1GqVXY+tG854CvT9TCQFwqIn9HaSv
wjbHATQBmzoAvZ9ES7Y+EbXZ7SBnXOWSWOKJkU1hbuRkFKi3ghLwod1H9GOO2gX3GToReWRNfftu
ICycoN8+Qh8OTk5ifSYRHP2ec3mTl3RbFK4UAI2AprKoWx8JbVmMBIou6VEQ4K8cUkznrCQ5Dpvv
nQgqBOQXS2bplHDJXUhEn/9o6rGOAAAtizrWCdQVQAmWkc6/S2SLvrz+ue148LwR7TyqIkDJbHNx
cEWoA+t2deV8YkNP2bSzicV1m/6MzvYnk7vT+3R3QB28Ch8VgQaHLCU7Y5erQ62VaM2XTWBphUL8
dZiCVTL1N9fi1Maqmufodyud91TpxQs/uBTW8Yf/y4iRkFXpNKoX83y83Io24Te3Aqy+7xrfrjG5
pXfY00fzYgy4Afjmt+KGMUVwRMUJ96gPobBYghN5uXWwHvWGPJA/KfJGUqKcEl8wupJHeATRDqEu
hkQvgLmmSgkdKQ77byqQQe7NP1SxMJ8fjdez5fnL1ie5xktcdekXIenX4X6fbnEQoo5mUlJ4IF/D
e2PStgJMQXQVqd2CJRfeWGxKUGfcv3jkgS/vfbTlKGibEnRCi3x7ahicsqTw0Lbbt+Vuw+tBFtYf
ULvRrdRv40KCedymiRrHfxSG4G9odGW2ZRksX5HA/R3HF4dO7+YETS4RlCVoxi7OlMJPl1Fn0u20
LDnJwJYJkyc5p1crZL8sKfIgQvfQ4wQlnxq7ztvXcNK6Z535Fy6A1LDzwoBvE9Dth8yHBXVkArsY
VJwOHr16/0IkZ2fvj7tefLUXoYk4ohvFs6Ehr3JmK7tIOme45Aqwqjaj5zKK3BKKD7S/q0UNob5+
iRUryFrwlunxKK9wqtzf9WzKhWgVOR7Iv5Xe4DX549wV5Fm1ENT1BS2KUBc5xsW3bW1EdWZiOzJ3
2AFXefKYZRZiimmbdPpVyoseFwEYkbDZ7V4eaiSgKEqizJ6Uo8ZHFTtJmsq/0yvYTVjEQ/OIr91A
eO6t/jK0yO9U52frAv2mjBcxahUT4oU1IQPuhIrnd5RMWWcoMz2KIC2YPaXkSBfod3TbkLYWHChH
fNEppggh/wGayBizMK8TEKEF1W8Y8dDbKdXG7q/jJYJ7OlCfcBND0frW7b/3yrubD7PBx9zsyAzL
XLMUv4PSY1tASxcHMzpti00gHEh3jbKEVH94j36+Y/dgYbssIsPcnT932RyVndOe8o38/DO39lZ/
eq7ReVhT5ZlkhJ5pJaa2RKRjDmypqdNks2bqB2WL0J80LWbSYrtkBPIRXazi/EgYpFO+lj/MB7Jl
oU1aasq0TtG2VqnpVKlMtyVqdyAkBP609ONfmIng1h/9zWH7JoPNKT5ucbQ/aJoKDBxjePdxixVa
fryemiV9MMN9SE2Eu3MIesoFW/gNOLGhBNZP4wN7mx+U+x/5uzPTjuLbIR5t6uELaGL7go0xnVH7
JfexptNMRmwFGewyd9HPcI5b2dK1U2qWz+Wuz7oBownU49lv9TaWRadLC2hYsY9Y8RujqlsMFCF0
go6PjR1rzy3GH7C3nn09EIKbK7Gd+Q9EgpJdfWSNfDOfxZIgoD3i9A6eDpA3rWnKKGcxFDVUrZ8T
mRgMJTcr80VVXkeODXk+Ap8Xv7tBICDqz0K6SCwUSwF4g6eqJVU5ifdZr98h9eDeZlY862S4f99B
GhfzRZrNXFENwwzAj3DlknkvcQ+T6rj7EYTycRx2U1comTNxCITi78vUxKBY/hpr1poHt4KEMoqR
kxmxSJP/GhJJPxW8jO5+DwyLvuLKVXl2JcocKIYcJF3r6TuEkW3vk0BFb3fmLlE9I+AH/MViXObC
QMUhzyFRlr/daVbbfqaKhxvxsOLsDjIXT5IE/383k6velJaH0nrde8k2TFC4nzAacBnrq6zkSTXk
HAtyVTH4v5CNe/Wtggii2+OgsLxJQzRtfKdheYgYDAgUL5vLn5RzFzYOMxbiQcaiyN9v++HfpbUg
WnmUq8okOyJe0d8hpxG5CDKdQEiVYcn+PxOydlw6BUZxBjBMkQDM7JYvrGcZXfrDPIX4Updr/uKo
PPTTqhzt8UggMSKIoCWmH06dR6xBAiw4tBbn6PZqMh6YtOkn2ROsFGWjCeeQzQkOpaTE5WZFDeKc
N/7wMwsdF2qPc0cBzOLVDEzNVOVsVKICU9/Dkfb3do8SBbYRSmtr0TELFvCc4GmlAvw4954bPnSy
aX+CeSWEm7CBALwIA26o8FhIBXROFTRg/XXD9bBaMTz6aS35hrCkQhST61ktiGfrbeAZ/Q/hiPAa
/vQsQQtunIF7sUGVbZXoIv7CIf+xDE3AyTuqeEBfr9naKqemncWSDnNJG97x8nnNwV7xmdQlkZXV
uMlWBTy8wv2widNTcE3lF4gCb/Pg3Y2j+XXcOXdu9qDcLzWtlLgtEf7AgKm3zJ9vIC7im+/kfWLS
AWox9zl3+rE5SRlhuFdQSItopZ31hXWmA7mHyLpW034FcY9jtK3mVLOF4UeGVoukwXkgkFsXf5ZB
lI77ucSZSVyqXE7kwaOIOPDc4KRSyqA9uZ6a5C104OAEkp9572aUG3N4QVyYRUNpHihTne+8eVMu
fsmCZY7pEXPLPiCxc5MKPvFDX4DcK3/sc8jlBRKvH5gJ4Z2b3iTwuR59D87Y7JA92hC8ncQR0H31
zMu4Yt5Gy5OPNx6+ekGarSSnUcwsFXoCMOuEGhXZoX3NfeLRZMPd8V4PFqOIyK16MOS+aYSAF8LE
ZKItQ6SOCZyxC/Rr3Uumfstl/QjECDHlqFz51Atf8XwCtu33G3SRAZkX6CstUfJ9BZiKD1l0lN7e
H7yjIGSrUubcxA0GkzZ4dTVUNd0pYSS51mtOQI0C8o/KovXl7hMLtibkTEUWOEM8N2BGxiox5l9E
sF5HKFCJWNSP6v+BXRdX2Bu3rOqNRVzMIkyoTTfzNXmugG60dzh4Yl75QPCTbZp+S+bUWwWWi523
mNpQdPj1T2vi3TGqhYArfcKLDtoqidc71thNf3qah4/VCkwvXugz2swEqNPt0UV8rvr0xaFZbc5R
ytyw8LIQziW53oexEHkbO9DXmlyeMnAZm+/aA2+OFCn58J6/NjmRd0UZnOniW3BnEkJ/Gd92hDbU
ktXRzux3INP8i2dQjCP8Vth75CPmcTdAZkROE5MJioL93Ug5GIOSwraQSR1UPkbZzFeVB/8C4D7/
OtUSTSuH542fbOVoq8wszRkF59TaJVOHOGmaT1oNYHCKtgo0Ik0Ysh2j7qIhfztpJoLpD4vFIzC3
78jSOb82R7kkLLAzr584WVxqkGHdKuujzAeS6Jvzg1pbSm6AY2binWJffJWpFyl/5jBjAMNXAe4u
/yL+26TIBZBbndmHwKXPtyYWFZDS923+T8qAIzbE3eqdwiFZSkBxGb8f3hPSm9Kym/vVksAJDq3A
VHMvk5ZbWSKrsLw7weaWYBsoz2Gh6utpDZDDad6PeErPUqEk3E/ANkDrcQtUIlK+KptlCywt9ax8
4ZPhvFMjF2zG7ACFuZpDEkS6kgGPKsOgG6Gnb25bomtJnxj+rzVEq+n0akW5FuTJjEulZoffNn1T
KmMALjEbTbbnh7RkJpusTyP/kF6kf1M8S55gb7srlgEjBomehBI4sBSAOMw96B7ggXQCK0eKpEy6
5ftbCq6VnppdpV/PGjtoJPjO0sQUgfcrtzvjnApY1S+ZVRQ4qStBLCR52z7og20SNjjPfDxoGwsK
zSxOcldSytwShNR9J2yxRuoWN1FOpTlnRyJGZ4yllFXG0b5vyTXgB2Iq0ibrtPOJ7QCQ9Y96tbs3
/R41FGwu0/PwimMBukL3PzIyHBS8R8IeZNXl8AMUKQiN37qDAPqUvqmXzAp93drj/ntjI3gYYFO+
GfPAnNTTzFMTIFnw8c0JdLioxf8O6Qo/rhigOvRK6lHvNFuCffQOXkhaK+f8TJvFtP3GXmfeQpRA
8JGLfBqWrhJSy/nYqhf5ugoubr6NCTBKmJb3T4PqV4129rm5eG6xHWZIQwbWihMAaHK+fZv0mLuh
7Oem0ulKl4pg9B0IOwVqfPCIMnngtg5a/ga4OU1bOZ62DVCgSPPNOACt14N8I3lnfAO/T1QqCnO9
oT12Wrag2osw0S8XUTk1pNyi40F6q4prjlf6FAyW8tU5Lj56zdjPWjAu6w2w4k/22jknRBlkYixE
I/ZHeP6krTKjKsVyWdQeEclt9B/zMqnMsBzGqlHSpgUZ0fTwd830COCy3J9bRaQ3ezD2hrPJJJVX
CtGZaXqOf5nb/2nNyZ8V8CILWUFz/7XjbsCzNv1hgfWUSa4XKBTuhz0zl5d+rR0x3e9Cgvz9dWk9
MBcG7xAdhG7CDu8C1uvYbco0uZ2m3ntGymtmP8aZwlD62VLRH93pHsdKn8GTbJ8VNQ2dGTzuahs4
XAGmL/O4QtvbwolInNGNeBSHxN8O9OAG1muCeUPnL1zvQdQtvOLQPACQbe+jOpge5jf0lM5MFlim
0KbQoezo1iXeVDJXhG5IQveg78enwtj6xqApFCD6ho9N0BegmOdSl0a0x95XrqrZ219vAyzjdqB4
KGG33XkgoWX03uLS0kiMUX1uo3RXWTk9Pzggju5d75JykCt8Woy1Ik4oa0/zT+avLhkAWPn5Hv2k
nhT1vRbTyhBW9eBDDTqCUbTpvFBfOvhe/IL6nfRGEg8rgPvuue8gos5077w2K+RTdHlWhBi1YTDi
V9d3iZ6eUWRwT4Cf+wbh3tlFa06gp/jcqHGoW4I9pysSDFPZ0EIRw2sEcOhbYNCXPScYiZUQRdRS
OLC0XePNWsaRgwTWwLdg0En1KjAaW2VHk0ijd52e7BjrSoZxXusKFN+OKbTcmbogxAl2RvHrZOZY
DVqSzUmb4jZl9pV0Ou18BRC4RYouKqc7G9bGyZPoR3h7RnxFJLW9wRcjk49QBSUFhe67FfRgWk32
tMhurcBeeWifzymSP5RpUWqHAzGmPGo4ZmKBRonRT1tWbx2iIUg+/FNnucHECgjV0PivOTOHoFyZ
CrMHtYfUqRp0NtA1gWP+sTcOJjr7QAcFUoRFWgnRrSLoBxbYmrbw3LuU/LcyjWLwzqToE7M8dZIN
SNYXa32shIPyQVvPrVmIUDt0c63uOFepP5R2WDFbznTWVg218nDsb2QJVk8Is1U39y/7es0ahnvm
EDxokE/9XYk3AV1q18YL8Bqsa/cTy77aWUE+F1rJPG0V6Lzsk9sRQ/Swop5sJtjHcKzAy0+GoxaZ
0wKxLCGuWSapTHZ9269VpB1HFD6mdN98N8SfHpodi6/c4rGYIPiLFIMHxe8Z9xtLEfI8ytbMP3jO
nGiUj7FP3Ra34tY4EgwciFzUHPa6A8n/WAtOF+K8OfZnfDkToTHFpyQ/Vpd/lFBy7xaDlh+8vC2T
38R9j2uqFRCNQNxoVHlHSa0VRfUFC2WaZVBFUb+l6ZI6DyN8tuH5EGIOj8JmOQg0wdsYIinI28E3
cIh3Incftw7pgS0cvO0mTggxxgXGNSnYPnmM9jsoNMHBcggJ87Cn0STcefVUClovoi0RC4kjuZdA
ayGa4s05b0RcCVB2gGMxGSy1jE/rFw083dAIwkSwuMgIMaFrDkXJ19XBUxZXZ6eLN8o1xNEdRrDR
hDUmPKW+QAI4MCFLLVM/w7k7BBHWfz9JwGzf/HGPsjaJKDEVadmT6EVFMm9jaxOn0u0C7YocSe2c
EvMb2xwREcNKPOXTFMU9zBGFd9MlTp1YUU8XchclrI+Nn3q0hc1AWVp4OqrVTqP7N32EtzlrBiqZ
gieNjsbBfNegQHcRbnvE9oEcIU2EZ2h+dqdH7dl+B/iEUoe1/6o+PLhdD4bPhZrQxuNcncqeUQsu
2KgBcXWkLh+qw1WKTSmZH/6Fytqx1yUKMoLjzSNRMpToPZhScrmUH350nlaTtgGTohGDuYQKELMp
VqqZiQyOVq0pu/L03HPBsMWsFqBX5tkJsFRdBv4R6dwTMvcyvfv5dIuhdj+pQylEpKwDHjdtTSCK
Oovm0q2mLmBN7o8VRcd3/+uLwCjpGbGijeT2yizr8fa5NvqG7/AfU2UMdHPCNYz2DlAT3NHcC8FZ
A0y+tJni0GiuAypIJrM/WL+lfiBjtbL93lNXWYIe6I7xQT7voo27EBs1ZjxacUi2UrqQN4Zy1+6M
OHqxIX6f8z+8eed7lB9YMGbsa6dgwrgr/pHawIKSwgEXEDoneD0hI9kFnakt0f6gJTQWmwY4WqFa
B2xTPbVRdzAOFMIhx/izSbp/QG+Mcqzk+GtpGOntDCBMqyy7IvmSKI9csGkr2ck/iOAFYUUgcU56
ivVB+6d0F/SyB4uXwGatxJkFb7C8HRKDvafF4Qc8/q9Wv3GGKbN//2DJZxIKmV7sKf1GwDZ7q+lP
KvXBGaeG0/OS2gfR9DuZMlAOU93UovuX5QlFNa0bEmL5i2riq3GulyqCThb1yWq3T37K4OqXkU3M
iSPni6CAg7e3rjHT8E4ATcPUCm2jl5SXvmQqlpBQGATQPfcJBgMy+9oZljHa8f69BNkwL3U0feFE
cUuyo4cmBnmL5zGRietl4Kz5Lx6dXXnP0nkJBUKQdG8/Mbz14RDuii3Xb3PqCql6BwweSHVC70iP
0pUu84zJbzifF/TYOpURNa7ISMjoV6BGVM7t7smE3JViD323/lSnQZL5dnjLOsWTg3RBsodkFZIb
WP3e1rj7igm/Q6XhOm3DOEj55qsq+CSkYKBiiuT2gfmj60y9fzavVmWbhDSYX5S8EW0f6akVdvM9
3hQ8HUafQxBWQEEdc8iFm+b1dYcwhYbWufkmxzc3jRPjknIGijc1lUo5qwbLTp6XtCmFERyMMqrb
Jj7JpXaq4TwK1tjFS1oKvUyc+NSyMKD93gPhiBzpDDvc/+9uQcGd59rB1gPztcRSIZAY1MIAwxwK
oaKLxrTlSbwU2aEqdcp9Ezl7OIMxZ64nlWSZzz8qGbE8sWe1q41g2Q7d54YSD5tuq3CTPtEksM9I
5Q9E4qdroaELwg7U2o3/2vv8pkdavFm/g28VGKwYCwVTRB0cymyn0GtcAzyxE0KHQFPCSY3ZrB4U
Qn2A7itTwKEsSMxcJnoHJoZsuPqlqsNpMgdE7r0M6ixvBn7o9rllEHPfhshBi3CsWpoEVqd7qT0R
/5sdBrLDKIvRtorzBW71MCHlb1irvCxHk85ZA8tzlpomGlTWyugHUiVcJW8RkDB4gBoFOJCL5XgD
F1aV28dpdPlTrsdawPcA4e1inSBK2cFpTx0DBD9W+eAJroGeCv352HsKoRWFmvuchGbYNOoDIaTi
UDuFXccyClxmAlZqYTStOD4831lo994EnijbYIOPbPJmGW4twITrxZvqcNyaZcKQbaLixcEkxGw5
bcpkDLFNno0VmzB9AlLB5U6zxcHe6ljxd+J7ploY2b5cYgxvAqF973MUcoceuAOairh1mBEoeEc/
D+qMpmTOWbKAkaTUYPnDoKlmjkw9lW8ruEmpakAFpxtsfRX+SmFSweY4ot29arB2aab67o+T6mPX
JtKnYh9qk56+VT5wXoRq3fHo+FBSq4bAI+vyEhZIMNQ2+hyclCYjg99SKxNWVRkOkM7Q2ppVLdun
d28KT+bLfqr8dWFUiA8NHfliKee9OCJ2JwFJ75GGTwqu5JMCybuPXwqyBY48Yyf+JJNAPwk/Rr+K
sPuPRgCEMVQu/oA5wZ/zsHKoG8Ny9cPJEh8FGJvXwV9r/sD/3VhpNRTJqmqzMYqu1hQdxaBcXqBz
2kUgK4e587yKH9XwaDvQOgJ39hSffxWB6w2tXc68wIrUz1+qMWo17bSRHLqKSq1iMMC3kGfHuP9Z
nfAWuax7uVfKozM2dyyLKFz2YEWiZnJxYAxrRTErC1BCJxIo/c8cOSuOVsJjvtI9umTQ3iA9txAo
b1vhdKEVjeCDjbMWS8tDkS9/9j8ZlmkdrMNLMANhiqzt/pn6OnE9d7/mEKkxb15wqn8DDZCCStwn
boS48/3C5P051Js2U1yQPVRIcaobM55g4m2tw/bjUBDz7E+4spkKbBKBunZWaXJmuInYQ09grAGN
Q23NofpXEWSr52ya0IFntjoS3bVe0KvQ+fkRLR59Uok/cAVvgUSdEVc2Xzi9D1tZl3ifjqo7jg4X
XhJ10PtxREgimcGRAiimHtcUkAE9Zv3nudLUgHBBA7cmXtFJSJa+oUIred1cN3iSdaXa7Xj0nG7I
//ib4hSyz4l3G+9/cq6dbEP6YFGlJzozY+X/bqb8FDomnNo84z+rLENMBn+kGGo3Tj9m0Kf1tY8l
nF7DBR/gHkIEeGwMy/tMRW2JCCJCrE30d4R/3DEy+tCRG9UzXXdxs5nTjL0bHdZnZ7yCxxQHkk6V
eVRTjymE1cBF7tzJc8CP8i1HUgIATobprADjPjmSD62QfR+F6G1fW1SnSneVwx8P2MgWarVjb3DG
tVpYwGUKlvjdF4D9thIPDgxhQxaQix8W5zoGlak1kxzezG3lEGi03hf+019J6e6bhPLvcqnavw9i
p3Rr4RAgQM/5r/p2X00dmbQcMCzRmOfLz9cQVTD4foLvU0oDxDEOmja2QFLfWj+54nwFv1Ol7H5/
1ozA4fH58N8mFRtK1DROdI5Sr39YWVlHrHk5UmxZarQv7xdWsb80XHWOPnTcZnP0wUh/gBKAc3qP
rMIFxxS5JOzg7alFzmks2dWHdxtKfNjvmGK/YZPMLz0bxXo9nb5uSok3uYT6CxlDyN3z08kN5ZLb
AVgtBCISpzpJktg7KS3JBNu1GCE3X4u6tANyb3P+KmufGM1oix1whPR+gxcrezKggvVn8WC4LBfj
fVmI6V8EuEi7BV3zg/UGqggfSUXQmWLAATWAhM9ywt7/bkmLUCdY4ybVtWFXtFSikaG4NhW2P6G1
/ubiL6HdZm1+dcKtM4cFRmiRZQizeCNxHqnVdtMvW9T2r37uhfPfM8gNRWvpim62WG3HdXvjPEAP
ePLsP3/7eKnHQ4uqQy8DR2hh5dhgyd3kZtvqgryy5KGNvboK61Pe8NO2M5+/ZJmDJln1idDXN4zd
ifnx3YI+BZjSpZnNIjWy3eXNjE7QU0Lr8yLGtXE9TxX7YHypUwP7+s8bA94LIR3qeawJtWPmh8vp
NTveYfrBTtpylGtTefSxjclQOVSQKVlC6YKPaN3xfn57SViecFSEEncB5lfJEgvd7gEQtHhzzTA+
myaGCIdbg5R9hYAUw8L/8lboN29LCxDGEc7M3hTuV10vkybNsuRtaRRkf3L1M551ZPs1xyhykipp
DEE+DAGQIr4DaMDkMHgEmUqclafHDzljFuV6VqUGgMoBR7ekZLjIPtMY82VCur493M9g3dQIFkNk
mZKKH7+Q5JyAueRnc7knWjCVhxpVuAJPSDl6og1CiOHvX9o04EWt8Ka/IxDyUgajju8+qpcPVxF7
tyUtLiQXlYg9ftxPU0HJcNrhHbYU6DdVyO23W35RfeDBjUr7wkXCqQwPGSyRroxUhBPoRPucFGad
cFz+MGe0pMh3m2eNkr2bHCuuEuEDnL8Qmvo3V055BavTNaGVTElCBGreWNOeVmxErKVamcf9giuM
kH69vVhExsI1DHJvF0nEpS5qT2WoeQ1bgJedkS964C+wuZioVjHjExAIA63o1ykbp7S4XDvFuRsq
k94HlfHrcjXKHuwfRIwr2GzpGmIxgnDQLBwd/TkA4Kv+S0BphKvFSt+FmHO0SnQ5DdOh68fT3s/l
UZUAo0+dtl96RO+XqdKLg3XEMwAT4AFG+9XqY/s7Y7+8H1lyoXVrVm/xkV6fa8x117ewMY0DyHJf
Q1+6NML+IK2BWRvpLeepBskckpfkEIZVao/AiaMbnccyQvTGlHEKuQah72y9pn1aAmpKthqUeGwI
OahIjxa5/AFJBdBwKg9Ha23J5f6kqYvwluiQxbM6cfCSs+nWI1vS4XbiV/yucuPZ4baT6tUv3OZW
Hp5Q3zFuXzmNSIQlREmI0t7FBKs9iTpcFBECERIRIE+zqNdNczgg9o8FwBjUrJ0c8HUCwgBvoTzW
P2pOYq/dphWX2KpOgknBkdiyGq9h7kDHXn+Sguakx8I/TW6YSjtkr5kugM2MfLmvSrJ23Tly22Eg
08gK7IxWVPZZa9MxSzpFoWW2GEmAXmqfdKG6LFoWyu+tgH7qAm29WMiVRCNo97b88oo0mvBpxpF6
nRQLBpNHCTtatvvHCsjQ47Gql+r12ubkQadJAV2n9S30c2REPq6Bh3wgtVB1+1x6SD9wOkGHCGM8
aDINsmiqUExR1VDvhBHCimV5BVvXpEhxDACmCESf/FogtcWOPnNLyseXqXLeSVH9udUub0DohVTb
nDePUKXTP88KEskJ1Cb5ueSFIetFtI4mGQIrrZYNANffEXi8mpulFdFn0xDEvnYZzWRzgMBlABhe
2GetLPwWBnfnnPhOpfvFYMrD7j9s61p/HQq0xPhCr3jA1pSeXUkQQWSui6etjvACtLZpRGmTiC+Z
aN4ZW8TuE7jJqcTciecfqDupel08sWz//4x8ONNYBhLZYwmxPQvTAPSwKrTABbnuRibQFgeUBPoA
zC+fM1zZcLkzNacOc5OsGRbV2vsSWW9gzKtD3LBkofRSXSM/B4xg2mW6VkqoaFlovg2V3VMsrFfq
MiKUoRZ+WMGubLgd731WjlRIBA9ZouVBqCdocyLmFqrBWucxtD0D1SebvYmJkACgZbRoNcuApTJa
Zgz+TfW0HOIA2d6hRfS2hSrKegHV1n34ECk51dlLS5kabX/WrTALgAmpLUDHqF8DV3TO5CHnb0eZ
fWqxdahH19+c5IdL69mOriVgXcKwumU6P5sVLBxWtFuDfgSsIsGRsVtJuSeigF4VKR6xKfNnRLGl
xStQ1L6AvrVzgtsomKwTX1hFtf6FlcJO+QGvzflIyt75O+4oIKz9jw8fH62m9nAgorD6IwQ+1w6K
WmqYhWxWQ9Ej6jmht99BujTUcWwkk4KjKm76rddpC4hSB3STcBgaecWWHSvAZ9WDHqQ607P+fL0U
kovNUI4fmRjcZjLdzo/TswLRhZwuASmQYZuZ/w5Qh6TpatfusaeTlMXuhFg/gHKMO/zlmwtXrSV6
UkeAr1yOzlElrSGvFZMK4ERu9Z7mxGxyIx7VVnzLkaOJy+Eam22eyA4UmlUhWFEYYelA6gQ6Qoiv
AG9VtLQuuijilTN1QRanTCqrWbfU1hhqk8u6Vnn2msMarulSzSiTzFHpRtGFoxC1X/14IFN7zBBE
bweyP0w1ejo2FdhhekQKnWePBC+0OTUbe/sm2TxVSa+iZPf1AO48YEyrphPau5b1+9BkfMnww4ZT
Oe5ZWrnSLpc9y/DAOTckgyFvsiHwAVrPUNebKfQytyFLr5CARtZR3NQbC/oGDfcFxqHWMTeOpCWZ
kQ/N7wD6uE1RI5+T4MTAzzrK7gEiGbwPie70uRL+gnF6U2Q9LWIkd7eih2ReYrxkvsjo6SMw2Dgh
qOSiyoNyC3DrSrtLflzFkJESfMxCxnriXH4GDqKydiljGWh4eu/BrJhw8jwFf9coPbkj6gKjfttx
WTCU75j8YsC6By2htmgpw2Fw7Eps7O5RoGxMVYhiOc78DAUWWx2c5Q/4GoXNfYylB2gqyowRUyft
Nhx6zrOxUtZPUZpCZA3evfGoh6HFYaSxK7HdKVaHP91ZsvZ/BfL8JP5gSEu8yPlPV5g/o7nDJDfY
yAioVWdECr9/EuPuPtpBPySisFTNXLBsur23fVjKDBLqUum+XPSxfR+9p34cY2nZdI8tmunsxBA2
wlVx2k18//lVeTseq1Pz3LK2Hoe0NWJ6vMk1eeULhEVvEVoXUmli+ka/WailM15XztVbZt7zgXgi
caH9MhpqOkOb2qH27YnclYSRJORypYs2Wn0tTTWJf2jyuj+gAhvSCerEmnwkKDBIPdHELo2nFAQP
kNRSYy4aYXm6OZO33fB/W2iwWvJgV8YVQm9TqM+dTe5LZcvxv4dQ0LlDlfBliEWdARCcAtKe1K39
LPsCUi7s+VkVfyNjsmPMENYYIpGN2HmtgCtKi046woYtIkEs6QO9UdGdeUL+Pk7yTDnKAjVzlDP7
oqPVZ1pR7bERmt66/V/SBtEBaeSB283iQpxIOt8+hjnwKTnik5oEPkRGpdooKGIs67mciYJzwzRM
TBxpUgIeNXpqIcFhVCJFwvD0jGIqeygnKkAmmoQ9LkYuQFVP/G6A55M/UZj+mezedvSZ9itA3es+
yUKUDMi4UZzs3ubn+pBuq6KeLJIi8BMnzgbIu5gKWnBTAD28DluPAWKEzNoI72JJzuX2ViAiBF7f
hmsKNDbY5jDnQI0h0+TSV1nyAlGVdG7TlIu/RjykAgwkWa1kW4bNb+YEXkzxrq22GZAIkMyjvZw3
H6Hwvai7jtdvLhnpmaZjl9lpXbppr7sVWR4fNeehi4bjnetKaX6hWZTBDhsDczbWAFCsd90It9bB
Qcg/AMRmmmpKf9XYA2xIN5dLxyu/6ZzgHiyIhi6AWyqiArjfJt7twzJaN7gH6GMp/dT/zdQZMb4M
RdhFfjt/0YqEQhRp2jk32V2sK3VFC2Vv8LETRMJoYGTwB0te1gteIQxVsmOGF99hhF0512wysMwf
ZnfriLrIkIlRHjPyb+hZ0rsJQscpoF1t8IUWBDdtcve9kSzO49zM6qFOE1lIcAPQjnXEGwDeNvCt
8tr2mlzXSkSOW4uGNLKngj5G9XKqYp5drTFiGeBibA+bE1Fq3lfaePVn4OynFOPPzX7v6xTpfwPv
X2gsXRers/d5LAG42VYQV7XbAki26fY5LrhM3GhrW+8IPutO4xXjCbNGEijH5YxR3pJaSg2xEK0e
C46h9jyVGZ/tx2tG+VZ7NozJ+BqqZmj1cW8fj9xscEQkIkhZrEicQMvc6rZ1iohbxSpcgTwDtDCc
sk+ICDhz5wqYvbwJjEmsAdqMwOJvrdO2oU3Nb6XFHCyGKP7+n9VZcckPKs8nfplRETZjF9ybg0rm
IxgNChWheh6GLQ0eC73yF1i0oz6JpCIdzu9FaHdH2SqZ4BiISRjhwuXBKjJex4pUKUT/EhTIcz38
BL0RpuY3pIfzRLGkhOc7LC3ojcYLH37yd8NGG+qzt3I/8rG1pM4G8W43Phq7WNC6fM0aa262N1xT
2jOG/rJ73YtqR8Y90LIQfw/rgHFWGauaCDhYY45c4K+tWPxQpK4IHIgJKiobk0K0mMI9DU9UQcHB
dhlCv4/x+ZRNg1blaBqpbIwdZAJVIE1K0MIsBBUnm5yj8d+lBZH3SJdni9KmG4M4PDidRD1opuwV
VAUrK0xxAOHJmBLUpcLXO9yAslwx8VdGQV/NVhsYEXvvXVTLY3zQbDxg0+nCPsnLjI7CuYLoTsea
mrOQ+zXDyxmngSqHKVJNH6uLdqtxNGJmN3NdijqHxAdzjNdsTtTMa7vslGyl1z/w4zW9yhLQ3rFZ
WJeWS25pAotogaJoRJYgJ8dx0NqFmq0w3idmjxPB3gwZ2yJKk6LrczAJnqj9UAzgDUGZV5gE+fqY
w5Pbp7FUGPUAP7/QLIdOffjVYc+IOtEw2l4UoVvTNTrqkyr3Bq2VWF4hmgyzDuao6KzTRWOYHinz
75zMTFYybfF7O5o1JT24gXtFstoOHjVxwFVLyVwp5gwK+8hRAiop8tGxw2pWJZWW9ppC7+UamZcn
kosVEBaHuxB7uZxrimdZ6yGeHb/DxIYlwCgxaDcRctO7MQqODDvP3M/yo5sjPJtCyhJBDK1/x6Wy
u5o5k5ic9VjLP6xpuZNEYhAuVWJoTNAKxg0DHcpLOiTwFwXfroOitoOPopn+OuDkr8OqrWYC37ou
jz3dwE2ws5/xfTku5tSS3fANuSk61KLhmLtzjxiI6RGDe9L5NMERHI9Nvf1Ixi2deH9+dLmbXyvf
UKT48hD81qRAMW4HQ2m6MG2Mx3ARuhgrzQpMWBYeok5i9y9VKZFHwZ+VMi8Ggr7Wu0USZeZyHCIo
MGfwCHNn56zssVoIQkQ8sd7A7hEYfKpwp1e+EOb8gmmh1akSpgwfb407+Q7gJgfe6phvZFUYZJYO
gB+SOHUvwaOzYHJhXf9QLQHgRzMwjhoFfYQq5tJ0QlFdpKQGjWY4caKI+RVSq1kYox+3Qem4vdnZ
f5Pp1j3RCLCe56WYYpuNeerasUfXNVylnW9L960oCCCuRz8Ww6iZCqSBzJtnQ4oEcX+0pQeJubvF
WYaR407l7A3VhTIAWvygRXaP/gB+PdQBmhdWtp5IgUTnnqeOn8B8MF5FBkM4GE4cW7JC0e+ttxyr
HV6zgEG3n5Ui7/21kN+DKGDaqc489plSHuZ90Pvk/EIvHvrhFPxY39lpjg/TSc0028fbcpNpH1Fm
g8YK08la6wbnEgd22KeFD5FshW3K9g0VZECaYNblfEDC3bqTTU7ygEjldzLWPZfWLrbO1ko0VHmt
mG214b1YgcIk9qrA1friHpyb13fdWWX/5xNYCt1Iex3CFnFT4oNhApiTLVaDHwTM+3HtOcBxb3Fr
+aqsx+rAdqyVWmMCAr8Y5H9SzXDZnhO0Bln6nWUmGKQ3HeSROqKgbkOiO7TTMZupVZIwFDDIjeR7
5vvTGEc6vB0vLcd+k3ZrkdF+xQq4u6Qgvefvihg793JPmChgRF+gyd0XziflITKr0D/GvQDbm7rz
yqDo6KqB5w6yL8zNghm3nIi87S95nGx2CkZRBZzPrMDgP9kXlFOebZYvBfaTyOOUpZKttIqTWNpc
F33uSsGFm3nD6un530SU8onaGwSR4W56HRCC1OPfXHfOcmSZPv/3mPr0dxgW/qawuoYSjl/nRXNz
TlGYoNV9xX9roXzp51kIkAIYVNZA/iGd6L6U4agFNGvCmXlGsrsWkeL6kJYiZQuvw55IXjX3LLXM
m1TRM00MhuS28phn0W/ye3CoP1JDsfmQZ1Rz6DIwaZC9D5sUtqBQceglslQ2K4MjA48jfe/63hP+
NlWIeH6gYeyPLe78svJguE5r13NasSJ3iQ4YJjDPcbTycIMDj42EE34KP4pn6i8bgKTkfWEpaP3U
+OuRh8H4EWvnw0cSEbCb85AKzCNKyO0DXNZt1uvIIyzSRgqqRIl/y9EE2yRfhHh/WKYXmQxfnpWy
ZNMYi8F3fvxwcOLKfSoZdfjO35yn/GBep/Nc7ldHSd378TQ/zltTaPzd6vCxhm3uBN9mPYX3KK8l
ldo0J4kQAaMss8hLgGN3vXC/no/bvrRgt+7iONo6w/PzqJWonOIobYeWBFB16AfTlidr8MROpVOJ
bB0vvXZ7FACMRauIQYW4atwQZlsDDXdd07MkgRxxSFUuBMHu3Wq8XuNt19IQuoxdhHDNa7pmmTJR
MGjLv8leeuA0O71GMQXwzV8SCjWTC9qZ16xamUJmH41O8m6RvTRl7dxSZmicyF+4qx6gtAtFXofa
rB0+hCyNLj1Ch5F4CJxEuBoYLGTUzMMjBbZN5iy1d8ZHgFI0hJpUOYBc1Vx1TFrbVT1hUXXWOROz
szlBO4zeVvqAfjsc8SlPX3xiGo7mSlsijwteOgVTgooI0yToic6B3I1GP8zM4wWiGPWcVUVGELxt
Km3IZEJUh8VvWSN/KSV7YiB6V+501jdZ6so7LutzfRESMb/egIi/AHtNqbLS8szLCGbEu3PnhNRw
Oi07TCDXE8MvyybbXKj/ZqOABC5STqDVbsj0nAZ7XqPdl/0h2LJp4i1jyxx+hD+LkWzZvLkoM6RS
E44N9qs/VeCxpB3wET2C+9IHAbc7N3moXqEVn+3rNqaQoK8uP5Y6u+xkRGomNVVQUmOfsNW9fhdg
FFmqQL+9+cm4ciqajfPG32wmZebS51KsFLKj6cK8+9yz1VtuxqViVijjk3QWgm7T+XGZJyBbKb3e
cKZXCywxLvxpg1GUqBmVkeUnyOFBVxWrovqmV3EzPOL7aPq5hkV4VTFB9Zq12p6vQnSpMIkcZxpV
/05qq/0nfYpG0ZAcWphcGAlNF3jDOtTKoT3WQKDwAW/kNPnZGRdDkRV8I9K+CKIyxLPlrilaWgI1
HEBw/mKf2EiXBRBsR/ATJRegjmSC88KsGiCg5p9tRL7tscuaJG7X1N0oVBOjLWBnSw159QOzWm+r
ARqf5sbCl7wDeQvRr0MsgShzFUkOvi3v+m4bzJ3UqflVtdbRBTBMd+Sy/htFRxJZm6gdiM1sJ1NZ
UHcMAvSBgdh+p0CwmZWBXHkaNyMJQaO7Y8TteSYMgY96HTN7AzjqjLOp5jMZikoruPmokIcSeSn+
a8gZ91Y4sYUMDNjpD3sJjYBaRGjGTB4ouI4xq0JUDzQcSXRPRvnuESwf2gDcmNisNbAz0Y7CcbcP
gNIX0qGjioIsiFBKZNsCEsimbiS0b022F/uyLnOKtWNNDnb6RgzggMTsySpuvnxcxfMd54UmWzO5
X2aLNr03RN58ZV/mkOZeVBTW0WK+bgD1b2WAg/opTPT/PQzPmf4qkmz/MGnirfyUmilIJ6qswCR1
WRLY4geHU+BD8/qD1qgAg1zJQXHrwb7sVVYWZzvy23OXOE23IbSTDeMtERqXaM+od3kgW5nNC4Bv
c5N/2ZCIaYNI2stwUvCNG/h6uftnwsY+a2a/yZDRVPndspsDyl4S/an/sdkvtjeF2L3C5ZrWDitt
ad+PKk6cQL86wigHKDBttzXK7yb6F1YatpdwVPge3vEdAbpQYnhSW62qKOkXWrPgeU1EolDvcxSC
vzr75Q81FhwHEz4S80LWM0bMGUTbFIYFN1bO5bYVfKOLL6HgQwN6WJ/3gnX85u5a6HZPcqaHy/SD
5FyzXlKRmIoWIA0m5VK2zJmc+9TrI/CkVwP9RpRkPuR/nwuRBz3j4Iv09lhZSZNuw98OYLHFCMNj
6oIj/h7DkDUOpvAn4MuSfS3yl8aRK3XvcVhU5n/uwkPhbBBCd1sZjNcGAF5jqPbsXvZrasBeUphe
+rp8a/i8CyMs9TLl1M8Pwduicr6JLR6rJu0t9NZDQkEOxQ/q0zV4cx7ZHY33RrLeoYaW+KO6jjYd
hPgMe7VbM8bYB40vONEjFs1gEx4Io7qAlI3+wOWBFAxeHqQX8j4vwuqvlxbu8I2xhJW+/fxzm6Lp
CM/zT9GZSZndIG7eOnqioBy7RSGPT1sBS5NBsxm7nlkjcW+zuazU3myPG1BY/nwPLcU//jEpA/uP
d3th3/cKGHIgbDW9mDO9P60XSZ+4vIEL0Iva4f6JZ02YLcnEa7d/4xdpVBl2zM/NHw1KWifaSnSl
Ge1oxUeCpy/34lGT3mXQYsOu4eFzPk112Avn/lkmDSB22F8liXToJSfT+TRUuTS1N3heJoQrLpQP
P8OTMp1pEccbqxU4SjLzAS7gt1vm89ZDu2mYkPYhBwUw2MOXGgXHUzqFYXpAuC9Ux9vOk0OEfahU
hT2KsGzxXYOSyGmo/GIivCS3kttlMoU0CmaGN5UhYuFg3NWDsnH7rpmgS49kMny8Fu1VgOYKy+a3
ZhrF31xS8PvL1dhFBJk5xGtz3zjJU+AZAZaLjnRfc5K/Pq6XBWPSdRa6Osj+WTxgE0dhvUqYJQ9C
obLDqylcwTwJokZGg/18W91oYA4yw6NQQqBePzvAK8HTR0vd4eU/n1eZgSpgyx2Pwu9i8nCQLQiA
lP0MMTB1Groj/9R3x+emu9eq3K3aHq0MDJHVxPyseYP70idN6SdHP0vzRbHT0erETABaT2kFFA3d
tnKgkYKZhVL5gxqlAFfth8KvkUxCzjzmQrgYANMPHYPXzfdsgiUl5aHVrfzv8hPdHGRvm1oVrcQw
lRnNdvGnwx8zh5gfCEwnD9xVNdIJ3Z6RG0Hl+3qPnA/cDqZzi9CyNTp4PV+SWivxu+yOR0VRP6dt
JYRHcDGY2179j2W/eBfCLnmWBSA+6sBFVuz7pDpbvVZFyl4oHegEkEZCUtBxK/HlvXwEqUqywEOY
oL/OWnJDwPhqqVac44tZtHDifAiqxGJ4/xd8cKOX+ORBNJPyKWzijjJ1ZwQOnvD2GS96nPw6D0z7
lREJFv0wYPfh316eOzCdRlbSE8hZberqC2ChJC+TqVAukh22bPTwNwwJLlDUBbPwlGOTv6btRpb0
r+W11qkAMpNU1TELdWUYowBlUoOiLAhn2JQIFHf4eI/Y6eBHChjSbGhWIy/X5TfiwT/0maFkzLOf
xJ54DX4YvXFJji5gZA2Y/THCxCNUQpZWaguKk+++DWg8QxFTGAldv0+OO3VY3KQm7uoQyyLQ+M91
zCY1OEvVzOR7dSYutVyoSb3TeOPATxtLS+I17J/v9QS2rgkMjXLWpYID6VPLoKx57HQikSB3zB9v
gehFJgZfG/aIMaCSoyO6W3lM7pYmndSVm4gnsFy8SyBd6pCDzbF1PIHsUgwJyOGIeoqRlr6ytbe2
rMtHpX8SnZib+DabzAkWoZr/WnkZvWU53wX7QYHC4Rx28f6VizD3JV/39SM5BkMAt4bkbcP9TU4r
Ja6M5MlFtF3mbiy6J4KXz0chXg8inc0DourMDtEWKM69RZQ+g0r1KgkK6z03m7K+0ioMvw0Gm3wc
9DQICWEQycLnOO7JtT5lPUBea9iYVg5I1DL2ix+0iX5yg4W69BeUmpj9vuSmE6lniJy04QvzfwaT
o4H88yEc7xLzRrfn5vCk8jeIl+hwdBf0Ysj6dtaiYOJ8Tu1sCf5UvqqbK4KfIilYtT2UZDOcj0vg
f3fS61c0+dkiZb4cua7mUwOXWl+8oO+iaDZ3iTzoCJBa265/YJu/FkQXKXnjSKCCd6I4qU5+mZCB
oioGA4jh32RwuQKNikDhsb1iaRiCkJIK1xHmf5AK2/aa27FUxt1zasnVupJUj6LSLLQX9mcAXpYv
RvXFUkvAB8QcqnAtdA643dNU1cKxvOgT3a1Klbxw0Jp/hhqx7d30OkCrKfS69iQF07NZeQxPJk4V
sBv8PtzfbG454M+xRU/89VDxLs1JUmXdiHccDoYTKXjv1jKxwy50wiulklZbFIbA+hwdYCPJF2ac
1Xz8FgHA3gPr7nBoLndK9X8VEQi2JUvQeYuEB81JjE4WrQLja2gUGFaJ1601wfIxeNpHaiUFWtWB
FlbKOxhTqxGJL5XIYrJQrosVPEjcy9VHQB2G2dCQB4WMdVmqqBUvEQAtK5y8xT12qlik73PrC/JU
zfHKHCxTaM5iXTPxdnXBhHCzrChPTPasPcTXPhzjp8uaGqIH5zd47MynaQeMjdnwjEUs29SJ7F7O
YFigckfqETpFY0cCryR8EUKuFsveFSr4QCUy5ssJA9EBYI8hJYEvI/cgGVbnwKyZSv3nLRqSGKIq
8WSCCzyfPjWZqTxNwiuJz6aYxqsRgKAFdIgZmLGE+K8XiyRGdwdIWCBlXDSXS5/4nE1mU0ATiaG4
z21W9nNV5w/uv54NsqnpXfUiBMXiuPf2ua1Z0epFmpbupGSrlvOTIQJIu/etw2tnWsKBTYHNUc5A
m3GT9H7lCxK+p8oh0+zE5tWR8I416QqapAuVDDRwTf/7+8RATx+TDmgj4kLtMcgbL/Sk9HyeEtLn
KKoUMTlQhluzYoqQ6D2UnqsFk1indzeuOUBa/IqtvFSaTY/0fJLfHdjkoVOb2yClYy4gIFu9y5Mk
ES+RGA7Lpflzygp6yLyUX1dTRMkhXDxopv9TJU7ggfouCqaxkawjvaV92tudq0BWimwxgTCDDAWM
l4WlzM/wFXkmlNW5sw9v/q0FJzM0G5nWyxN8g9l/clJcjJXM7OsDV1G5a2q6aQhYLnGrI4ag3kk1
pd6BM48YmZ7LpJQC0TbLddbvU1TdOroxuNjHGocGuxa0x876ApX2RzaKtSJ3w1M/7ljHW8jmVZ2m
3UBGugmeq8Gf3yBz+mVT5SXYdCHUszs8vmRAk4PTblYP6JZDUPnCi5GeSk0c0pY3fy/jF9k3vsCG
DUejMbiLb24lYTjSTpTpJodVGnXzwkJf096/QfR3/qebN3RskpJOAeJiDTQ3xmtgOSdOOHeVdXu1
N4JrsPyqH/umKVqmEWvvRx3VGlnf1jOeFlaVRj+CNpQJgDgpqkVTXlWSYW8RnuBI7l2izJS/fJSn
KlSX5qPVAn8mUk7ysNy+NM4n471XNcP/+FLU+ExQSnRVQC7o7rVu7hB8wfk/5noBolL8mywHlXZB
vFuAp9gFs7hDAFDYSXhxCCOPvpVBOV/O9j2yJnU2cJujoKSqIkTrZzC7q1aVOxaiIcT1jaozP7au
qz0AA+Qo1Zu4jlFDwJ6p1vzvb+hB9fdjOCmQFSVGacEH4C5+qSuQEThAbMa1xwssvflJpAFcbt9h
qXNz5O6OZOFzLTaPvg+nar5tBwaZl4YeIcJXXPMELcjZbsrvro/Y4jwDMa9TXay/wVU6ljbTrMnf
/S3x2CZIPcQDpCuUhmpQ7PCKKGotQyyzP5RFu+oHo0Mgr0Y2Vz3SKMqufBstsDXIEtyOjKgxVhi8
J/SNkaR569Zg/r//+5h05iwJw85vkZp+70i1PmWpMhZyaywKVBVi7vla/kBGnty/dpHXZTVu4NPm
jD99n/rHOzmth03bmqGId+HmKwhG+RDNTB5mJcL0NWNuB26yPiS28gCbP2svEUrQdnYrlwNK/2tv
oxRUNWXb4Bu/jR5Y74n2bTxLqvJqjAp9wCYDE7JBiPL2VbGr8/0KAfK8qNcKtLuzpmfokkytbj3j
7nSiGTvdn41+u3aq0GULNcgVllXdM1jhLfEFdpuBUx3EonLZW7hzDGzCC5NX81B1zZC7Byk3T2s3
4kNja0zDpf2MZZViCtIOEQz0V5+fCPdkGejz/mCeROrNT91kskf6X8MJSsZG9l4siBB/Jb1CPlcr
+NATDfer7Vx2VGYvU31r+ay8MfTKJAUeBnocrFOhcMFPYzRpqwV0ceEEVEjjS/0rH7M1hYQpLyeD
M6mZ2h22IDolAGsEA67o1aUO0Ol+MH109lgjYBBQK1NBooVd9YiPcU8EpxMJaDflMd8K4ePWb9bc
0z1fcUe9cQb4tWdGQObIZNzBisT6Oumn+RiQJFjoynMowBzrLABGoQWw0j/B8gdxbvjfa1to6DAW
GnQKNW2icsrqRKF3suU5kFndL+glwSiwgQImdse+3zN2Hi47vufbFEMzhs9YK0ZnLzAHb1Iv87xn
FOGaZW1vFCh0igYHqaVgesM72+W85Kaz9P4Z4+9JAhepBAUz5Ka2147l9NxPQNAv4PoTvc4pRm90
P2gAg983nKTZBs+iQ34cBVk1U03EyDYIGcbqD2VPrkUegHXvVciz53TY1dYC4xX0dTMortqFhLF6
JjP2kRFJgoD099MCZleVE5yW2mBSJXJ/92WB8eb2MFqeQm88m7KFLm6zIGFzSHtbH29S2l5lCYv8
o/sFi6nYkcwJqwHfpxeRkctCQly3kERa6wpayywK4W1iBynddOsQLC/7zvekUSF/cgRuQfn6K2Vq
eWYwnzHZboLo1tar7RW+Yc9UL2lcWkXE2FLrcA7Q5Zw5n8CNnabpHSu7gXrAF9GL59/HciEzR9Xg
MONOugJMB5hCjNJkAHUqZAd3LQIutszkKaOPG4XNx8Heq4B1cUCzfjwKZCCiQ1/WzlVzPMMSWg0Z
GB0yudGmLxtdRH93GGfrNi987RZmrpHNLwHtk8nsU4nAmw8hafiCm0f5hMglMQGdPFf+Df/wp0XC
bO0g2F0dOJzfbQ0pfbe7GB5bnB87E/N0EkTPvqXErsMKuFJEewPmUoWiEpufp+yLb2IhueK0AdkU
YnugGVbF6ehx4+cgqk540PrrUTJ7ivhMpCjizftJ3XjdtpWrdNneazRpig5g1ANPOb1xoz5TJEDA
bkCcqtltCccayXbPJc2WmzXyJl5SMMdqjqQ4E9Sx1rRO+wfRAZDwmmAZrp76KIUQONOa3eS0tAh4
ecRQUshSjFcV8VLOrohgSPy0jZ00IU7jRHzRu0zB/e6qeyy5l1QV2okPIUF6NrFxqYJyUdZAORa7
R17aZw7OtLr5iXvQWY2tAUQkxCTeGkO5k+vAoBKMih5Y7CZLK4u/NrdAp0geb19SA/g4EeNTPfm5
DstsyLLAE9SECtPPv5qM/tihj/l1xLC0KOMI1pPb3YTGN81N2Qz6ad7hLRugg2OL2VwEo81MuZAS
jrcnUyMtLPxfhKi5e70T6e+QLmUFVnPxFfXNyWBEa7INGlF1sSblxCG/VVRBKVW3hUONBJR0nuNp
wWvqYEpw4yufyB+DMFYF1+tOScmjobQeX6AGo9rxKSIIrG6so5ziCDzCXYAFS85e1wY1+GnUx3Au
Ny9qAZk+JgY/lCBOnvFGX3xBfCTpfRBYesor9WyIq+3rbU71gkI2JZpe1HzDXusAA7hHa1okgv4S
ymttBFiLr+Mwi70pvWMRulKM0cfujLvdiYYB29py2GL1HYaOiIqVK0oNdmpm/38ea+2+CE9Y4mrE
wAqZW3en+yuDq2CBDE7zadsncd41srhTMXfvcUACJaWc/45/D4pO+Cag3RpBeG24Zkcv4SVwww7Y
o+tU2wSmAQd1hBX3osMMPmhP3H7jeqLq4lpZeafmLAUxnboqO+kHi6yvUBXzPKYQ3GD8ATvug8ov
lvwf2psjh904WM+KdmE1icpbUzmkYyh3mTo3babONkNwYyuqTjDWaepifX9eCYMyg9b2/EpQgR27
7eq9GNB2gfLdZz7H0sHccYomGxoWW1lP1U3ulzjSUGGGhkYULtovSBbN/AFtwnMTRJhUvo8yYtPT
JTlyRj1wwDaSIu1g1IpoBnZ0u07VbUlNCq1XI0ijEcszv9gZcieFB6K+jJjJ9PCSlAzPUpU5RJzo
OfxtVdlTwZh0fObO73dARC1HEnKx3C/27/41EM3ocmm3CYaiNOuO9aHcEIazE3yMXyGPZaEyd0zg
R+djCFapJ87iAIvjn0K7/6Kd8Y3ZofJi/1+79coxorKBxN/G2QTo6ryI5piuz8pt3asUrqntmB5b
TBe914Ioz3blHqnRe0BdP75fK6YHQ7SIPJApMz6pkI2+plWwhJGWF0FdPMa71hEgh7Z3fHG1kFiK
Ak2jk988tMAPFX1Ki9e/pGgWT8CT80LZshiULjHv0uFCHPsaH8cxz7rtEdRCjlyo3gq+npNXx6Z4
AiZmtYGAEHCEtC5u5nqPOOzJxVK1cFZJhqhHSTDZtNbWY1BtLFMOr6ACCL8/MsswzYw5JCwXjKJt
D0Dsa4ojNP8k7f3WAdd9XqO8ioRjUMGWYivjmmM1q6IOIJE5BSalJJSC+A12S2nuMQZfviOh+UAk
6ur3hyMZda+z/pOhxmOpnzYJ3c9nSV0d1sNAzGcFlX92I8+N2stPbrO1MhRApxI/chkDU1zWNjJ2
m/nNvJyaOus3d1SDJ3k3Vi6n/Mlm15U/0c9hR+zzFLIHkKuUTr+xsZGILkub05YLnLDjw0B4aK8U
v1ba1+b1oqrx0wlb3VRr1BmOEXSXZmD4q4KES9BWG0abnvCNNlnZSHvD+iMiDjvTz1Z8jcSADTyt
eDtyXZMthCwxswkqK9aBnp+UG8HDTWX/sivFQXADR9hnNscjsdoOP93CWFi7c98L3IO8kMCRzV9y
Q/S5BBM4QmSiFmykPxdvR5fooafEBMBmdytXC0JbHrhGwR2OS7e4RpPog26bMzl848qwHHCMTPwe
3BCZxcS2vban4mJdTbFn/DbImGvhKfWbkuNsoqE3pdNBFquIOR7us+y2+K8Sdrs0TFvBLmzeI+r7
pLPwah2bAIcjEByg7HZgLAE9PGzZOOUnuTT+6Y+S9FQOO9oNq9AbHPQM1EjV4yAws5FSrb92PRln
Om9co2bYUJu3PhOIq2MxyWavkHR/dvv3AXRJOrOlGkOJQpRGQZjo5fK6xyGzv5nsLPoTmMEplYq+
hxl0Iye9E+a5mfhVB94SbZWbUzMjgYEj2uIlqjvsWoCnd07D/SXjyoocEc50+C8XNJBZnFlu/PXj
WOg1G0FNJeMETg46ZCdtOvTNE5FP5CaHG38gX8Ao7FxvLYnuMTPpiVtXw+1sF8tRMNdX1eHBlVWU
5NrbIVwIfb+xhkGIz/t7aTqjOCaosCXnaKs2515ABiQV0p4KpvNw8cJjBzcJ3u4KUytUmf2DNVYZ
vzEju9NovSbMtRTDiSFUAiVndRKaxk0LAcBcwbX0rT9GVuuZ5aeHIjR/6nOmE9d/P6X0AOEaAzaN
7i+KAj1lryBiwN54mjMbZZ2C1GDNDNlmEZN04Y/8YIkrOcLs5pyz9qqhj+CGTtMJuuKkht/0m8+K
cA2/rcevaVy7xLe/7rd24fXT4RyuajQxezYDghtjTjM2JbU5j0IA85U3QR1CF7+DjUU/4xCxgcVK
DaaFExsxwsYwa+c4q40l3DGfMFw+k/Ba8f/gT5vykVHwNdKfoUsMp+y8vdHzF5t8AutRrnB7dTG9
LcQhkdgqVD8pFaxH3j0MIHMoSDFc8xTtJjp8PPaAQPMYI5HtM56z6lZLnll9lpT7EKt1hDwFLyd1
2KnwRFjujciBdASsTh2+mGf3iVJnTMXblVNakgq+aQY8Co2iS8abjCsy45+SCb+IGkue8Sa/ztgN
B/TmkLSGO0OboIwRPVshlkmDjJkUxUb8lo10rf7XjrPMoLevQjyvYO901++k9lQwfxSfD6uueqVG
oxt3duGHwRw/qmPsPCTpjRn53QAHNCN29EEx3Lzrcs2oR1pxNKvtrPsADfNCwmAw2wxPV07bANRx
btW5fKn4V3T4UmwasCTk12tgOr4Zu7SEbBv5CU4O+ppi785v7NK4XHQ8H5HY4pxP0HxwFD/sYLKW
lKph5lbLcqIMOfBhyLqti5xrzeru5nX/cN6CHQd4BfuAIj/xwqqwEqaUI8ZG1tYk0TTJ09DqOka/
qrlIvTBmiRslRQrtqr1c65Vx2sPPhuEwNweWBXDoxzhh78bBQ6Jad9QJDvxOToUEzzYvP8pt8KKT
tSm7fbX4QAdIofS660fPhqRNGOyBvGHh63cppmEfCr3E14OxzxKUdQddFy5oxs0pkSQAMm8rfVWi
lS9e2V1CJeDQDglO3Ty7nye+Nwjwn8cs9HpU4DZTYQKStukh+tx3eqPitIXyYbPdeFRAPGRp8+h/
glNAq29ImAUgtPh82wPfg8BIEgSdpG0jhLbl/Metc933fL7zKwRChTYA8vNij1IuUBzY2Z+m+ubu
h9vfbg44yATFc13RYmgmIrIcojwVAHTNxYiMkrnDVt0Ntjnhrls+vZjlMuI4L/Yz/CvbUC+u34Sd
6z4LMzd/TMN8xazduSOhy6v6/W7vX3YZZwKQq3sn4aG+BUKZtkERFW6yFUsdYHRFcnqORwBJ4mbA
3jb2IFaCiDemssThddxLumX2++gGktTyX2mex8adh9wAuJdmZB4ni5OdCWX54r+0as0rJ7VYwrtK
iqfaeHTnlUPt8lgEJbWz4LjAzbi0liIJofUN1WWLLJT4u+qKPMrli7PEmfHmF1fmcHSAxO0BwUY6
XrfWkMs8SjpmqOW7Qf/S3qpQUg2Gy6IxqvVPBWGnRUmwq1YjMVm7svv6XxunNTetTLZB3aPRm4ji
f4g8cbabeUv2i+/vA39cDybuicneI+oXWndEBj2/NcPkIIU+fG7Oln9ATIMn9fvjPfYZAF02EbJ2
zba40dBBvZ6zHB7zgyWE6u1COf3c6XE0ab6i6qF3u1pSlqKg+0JJSdyfL59AUEA3i3CSAx2xjnM6
Fz1OD7HFeiK8BjD27Bd2BHPPYH/Z67Cs/kLIVnOG8SAIxkJb3m6vyTmqtR1SVjtA2hfXCBtSX8TP
SeCIZ90/z+M2Nx99si6SKcm4EooHZOY0Tk858dDJNClWmL2x7Llse2/kGvPN2aDjI8ve4TfS3Xmf
7kEyXlA1EUGXquLg3AfS3V7OzTEtBIt7druCmgIGZyZcgvJtMma3/BtTV2niL78mGQfOrXKPC+8T
aYpoTSf2vuzrwURGsiGqrB3pjx48sfdGfJhEBjQy2mWyW29dFKq0IuKOtXkRKKknl16eS27MzVal
na3pIRq5+1cEYVJrutd+EhlCW3sMrLXo9hF9sCjUHUP6rfThwIbA3hE8nxF/gMhgyTlsHbl0fqRd
h39xUNLOKlv1hZAmFkVsK83BlgpPTLv4fUnoSlh1hzG3B2sMqc/MIP2vDJN7b/Nz8E/FVBPZb/6s
BASXqlTIjdaucTj8LpKqPQoOjKx9UKIAGLmHQXM7VPmobKzoH4+XPjtWMt4F4f6NoH8IVKpXN58I
DWzPQ0cYEtFaDi7GPfvxFfm9sPQ8Bic/ucgG6J8mcm7MKYb06IbXAeikmM+wH7AxLrC844GwxuGQ
j4pSSPHzj8dZxlmRWr8RsxSWLvrmD9F0ZhXGy5Q4jcOJHtt5gkajPiesN2vYlJrHHCPhC4xZ0kMx
wp+iDRcsp0JJeNXVcxoPoEAXKEMYfo8thI5fhTguEGGOw3PIvCCUD2gtVmkfhe5jt0+mbquWzaUC
9S3z1NMTVgcs3v2VXtr4aGON/OIRMVNYMoEV+OdHEk5z5Np3zU+3qZ1YKxXdZJgP+boR8pD5S1C3
K01uNfeLpIhL1vWj0x/bpt0gkQYDRbrgiHeYXOBvC2X37YJv0c47frpv+xTVSo+NpB7Yc1+fsV37
RrH0twyCgrF9rdxchruhGEHUYt8wvXBcSMunkM1AvrBhfVazqK59i/9SHz3A2gtm4iZaMo/J1gsk
h6eNK5qI1YDN7HdksBseAE/4Wqeq5xyJ1g/dGKM/XDlnB369pv69DgPjyyyTa69gcg1chkfMEa5d
VEHTc0lfsLT4Mrwrsb/ttpp3CTJHY2EOL/VIkjb9/G1VUElJ8+0zwu03ZUc8tZipRAsv/8VRW8X4
LzWNKQuAwZJCemVng1mpLenuRoQjJpIjOLIzkRyM/gpt6ByqvLbom2zFt2TXKcMTLiVb9WPkAuat
Iheo/mhqoJGWUxWIZAGLuIJ7U3M3DeT5HIE9PHY4d5pflG4dgNxzn410DFxHF8TswPlz9+1nwdPG
VVgYnNv5CCPqaalwP15KFGdQ5+8zgeR0Rn7bBqBiCL+iOVjQ2FVOUD/GEtOhJgHF7jTsw1tmIJlj
338qWZ7Uh0Ruvfg5sffB/F8IY9MrUH5tPm01vsJtPShjaM0dSXK8AMTmDYkd+CyZXPX3jMihG09C
uojz73Y5NZVT8pomloE3yEiHQZ4sURL6IL2MXzveBu+WcQ6AnrxxBu5VLcEU8TNmRJX4/KGsQSL5
ipFLpleJOZ3STtjgiuM0qEQUFrD0m31jLl1ryrKqmmnnHACiawZw4Wh1zu9zreaiubw8X8Z0AdsV
9O3Yqhwd8Oy1HE7WNrgM0wC+B7OhhOzc72rR8y2pn1P+g3Dlz5tKJ6FRfjgxGoAUJRGqtVtLS5L1
mW4u/yMCItZBL3Q2HVep6zorDzO+FQl7NS0m6IOhDHV3uxXwQnYxDvl5pKpvCN6LnZs0T8isSgbN
gNUds9H70L5DVZ7vur9t+4Ol2mpk7MdydEoETtQH5Uo0R4y1Z/Zmon8BxZymqdYwkxtkYQgqADza
sS0LEvfvHpKCoE1OqelgjP3jrJ2/ncqWFY7KMX7jFETI15g/fEzP1VzoZJcz9uAm4aGqgZTVnULo
CeTqVEuttcmnNsPVMxr0uaJ8H513VbXd7TYg2RSe0gFTyM59S5ME2DQ819Jn4deTj9DVLzkXDVa3
ArmPmBpxoGv+Q7qQa3q4d7Wdnd8MnZ0cXEst9oVWiNJwtXGOAU31GQpJLCSIe9LG+FxntL4S41/p
NPPz3QnuWUQ2qWm6jZAjzw3FSPEFzZ8TM6UD/8WQTxEvrpnrl7iDqLtMACjzmARG5DIOpGoX8gDc
Hljyib+beOP6KCmhhMPYTDZzI4M1nLP+0kabHqjlh39ZboTmnjnDg4IzOYciQ+01K4PDbmJiCJCi
9eR0cJyMWLRxDUEukWMkPVJjOzbnA00xwtK7adupoRg3CenLfFjYWP7Bvl557lcIXP14dAsRpfOa
s7e6XfWebmclPU5ZSuZ4dMOFa6e9xgI2ajXpzR4N8rl+RGaNxByUcFs7DO0JDCtsRjh15qF2yo0X
Wng+Ev18mXYP4yayOTIFH9A+KbmdTUNWfeqtUHU4bjJBzeeu5OKgYC1CksnggACigQC6lR1IHHFe
RzjhE5c0uAeOuZOrFkc+m1n3QFfatH6KI2KhulmMjpE7qF1P7mF19xtYZp4CS/PK+h+PIZxglB+Z
xdJ79UQOm1o+heKtHXMu3KMEHTb5tN+/TBdggVU+61nSSdiGc+oRSXAWdzX7BcevqK75Eg9zyka5
52s+aVx+Da/F0Djxu+D1AzrKq1gineTh0xKWnJIPoP94lcXzq+h4yGLTawRKbFtk3oCrdm+rjQwQ
wPbgeqfqYsSK8DT5OJFiHmU9W9gNjnYB/OdvbiegYvWxhAiKP1tSmyjpUm364eVc3DhsQr3tsft4
vrgi9tynb0LyzL0QPFPZH0KxNmhKwJMYuQL12OcBCcdzv5VcLSBhZELZuyC4Fu1l1vn08ekbrrrE
4P5ofmf3NybhBwnhYmDQhNEoYFWWtggKl7cLzykz5AnIvYlE/mnl/bqf18f+kEtLr0810WIUqAL/
9Xznr2snlunVTbZobblSS3onmhpGzPZMTzztu49YIl0dp+VVKrudiFAbuVFv3GGRcSbMZw0AM/M9
P8CIs2X16qGXLPcX7IQhnMyMXBpgtq67C10Ij7ueTjvCnOikrwepx/oY8GFCq16bo1wGA/F3bYr7
8w2Q9EAdm+xcgjkc60P4cYh9Ux7T4M6q2hAuFtM17K7+eH/cj0prghva/fkytMQk5ymsQC2KFxgb
HMigB5rKN16IuwEOHDLj3qxuUQ37Sb8wfpJhqkrP5Zgz1+GpaXQ3EVXJzBo0ocIMnxnA9iusD8aP
yw36w1lv0vxxKCtLbJDLoN6fjpDA1F29rn3cKa6ZSQv7/BemVPGNnmB7sdaYUeHQFKnyi+qNYXCy
dub1kIc9wL4ijZ1qldYQFgiLlmr5I9v8nNtDRF+zYYOyUCbfYL08XZLdinzmB77Ha2ctj4Uasgox
EmI+WgkqK5kIQE4uSRLq8uIQXtG93RqsdTeOcogLzO22P5c175gms4XYuwEp9T1KfGtp5eFUJKCy
GhGVEYJbTASMQi02CSHt5M5YCMxm0JAcUIKaIXQJOeJdtOWr3kvMYrpvAzUJU8PP0I17oKKFGQaF
Z0d57FGyi7prv4wg6ixPGA1DeAprzQwguwzXWH5JpenmM4LMT4/wXOvMH1mm6+4I3Li+H2wI/RQh
8wmpVHAcgANieF+vsDaUojpe0a89esQxj8h6DMAN6/SRraX9x9e2qSBd4GLvPggguJKfwZKiI23W
vyn3v4o+FQ0+K78lnsrtM1nNXy0dIyK02t2Vb3KP3+ca8LeMkZEI/C5oqlFquUtgyluHiPL9s549
d1NFlkupndm9RMZDBpyMM4rougBs0KAPuy+hv2VTd7sjmHp28PQKbYN02XEFEG8IjTYCLRw6cdbw
RWIB/y6Ff/Q6S4xDT4ahIfZvncRUWQHnxanEy/A7+jxDssiq7hZ3IsKCb+2n/T0BnRxGq7khrkLC
Zl1Ql3EawWX+qQJ2bRTmPYp2FeCX602434jR5fVbnEhfo9Sfmv3xcvoWxMAa+MbYu03aHDFk+0/U
VYJuUROONAGf2msgLCQwMUuXBthJGokJ9MTq0hC5//eRdNKN9srMoDRpaBGUjYK+gd+mUl4SrH9W
W4EepYZYMHKhWH02pK85aetu6yCq1dCLJc1ubBWcSGisYe0poFLXJ8y1kfTMAXpj5hdsBgLM7Qg8
MTehMf8/jAA6JVx5vNahUzxqKkoZ1gMtZ+aSR2y0ogHwOh27wC8lYuXirparL6lxg9pMlAIIC4Sn
EW84CXv3zYPkLqEE64tY/9BxTXLxznXVzbe//r+sF2H+gE2Wd7esa2xe4VXFRjqp5QqQ46ET7SeD
ytKwfHeMFs6bySXThFD4bHkY6KlKVl2wGgLHn0Rnxr7l0vTC/yiSKyKx6o42YRlPNi5+aqYVA8Jr
ZXT9+aPAb0QbXNSTLYW+ZS9NtAsx8wIONkNuiblHVVybjx1h6WNzpsG9WyMEDux0o5gbdnfTnfno
mHWwxNDf/IfYicysosMuPDYYFNXOqHfSOw57lseyzCLcVqCR8e9rOBP8lV8rQ5RhKVhkhVd8B0ss
37sRq0nhAZbXLAu/m6ODpDCSbg9IbQnZ9zHIThAuU+kmStpNA6oUTYnL97rH0Y4vRVExXvURvJya
lv4O33ifSONPChZVVklTnrcuTAmxcrdoMbkEWvzo0e9MTUvVjBvyDnPSRzyfhcY5Xv+T5R0oXR8J
9UpFMs77XpS098CFODW93WWIaEK+dNhJisvglsKd0LJxZO8Ql3+VKfUVQ3sw0Fa/aqDXyaVRaw5Y
XTXl/sA/WCqebYHrFair6GwScnXJTIKDFcukYhq0kwmJlRyg7Myw8XMxuaibitBmiDMfEj2Lt1gy
fU6YL3j+rcOerMKDEadZiiv6/ZTdgYGCgFdX7xP8fx8zGq/s4aXFnU2cWsFc/s2Gd5diVRHcw3tq
evWYLj2KMFvZCn9s4Itw313F+ysGgQLxkeRjRZhhv491eeai7+VPtFNBqEPDHr6+lSvNZhJeqMIX
6ZfZNPyhPW0GskwNlaV5k/vf6bTEV4dMTufimCDByKHwH56nnRdXsMUjrpvpU90iiwQl0snVKRJt
6rVT+N4qesHtuky+hZT7NDyYNs0hB3A6/1X8U9SISwatEK/FqCppnztxwLkUiI/bzMSAccJf0dg4
ZI9FEraD5ROA+ncY5tBKocTejYPlNrHkibPCvLv1/rimoTE8d5hSPgZVkHYFizF1/YKD82FVXZD0
N6zsHR3GerVDrXG6/yrWaDIFmKFbMETJ7a/j3xBrsVV8v9caIR6Ep5qQFQJ60P/7igbm/m9fSF4/
D9Iwe/hUSe7GoQkLKGbeIc5ZahrRG3Il8ncR5vlv4p2oym7NvD6k178nst+vaj9BuJ4haOAsJfBo
SU+DBq4eNvelEZzpLCihXfesKH+HV/20XdJoNTfpw3lACmJBhjShrHzw2BFSekNJdOPd0bYdhgm9
cc9PmfhrfqzVRWk2wDhyIW6/7j0bHG4IHG4yR+z6Jm5bgPRKqXFgTd1WO7M+JX3B8kxJvXrhlQcK
H3RYoOIPjc/PpL3ID6rCZr3ojciZbFwMGkiumu3mwa/nJDL6hK3wmTDLm2HLXiV23ylprtp5YRI7
KfdrWSX/Mnro4YDQj2IuM7yS3qAQvv2pTvgkFwWOAKGWVNEWeEFQ/XKHtRMrlfl20lZqhocnHTUy
l+dVzSoDMZ2AeYcYeh4Mf8EPku6GfzwYVWOOfA3goL/PP6HBlroZkT41USJD3JhyDftVw3ipUUZJ
LkHnc8ts4h9p4+NUaHpli3x6krxFWU8TOjaRElZ8gZj+LOuZWXQUgzhM0V+kctK0SyAjoDhyllj0
XJDXSVkWDE3FOV0kRPeL6T6QwjApBj/ksQCOHgqTPne8BUaiCLc+51r6nsFCQp+pMpu8iTxKq2/a
96SdZ5LbMwZgQCENOZixc5bnVO7SWmys3aCcUBUpt2sRVgEVwuz4W4Tf3evfMpdhv/o92aM42R16
cpYisxQzG3cZDNN2lt4XKG2d6mMrObweri/Qf4qZ2QqMgC8u/hWuYf2gCLEnh/d71Zox0i3nQqn8
P+3ewqnyCy/DClLsHXnr4VJMzprDoD1Pl4yA5rx/QcOPu4yfL58elKXIcjhUlG26ArPX3sncBoGx
bhNariJcz+oJB9KWx0DsvmN8uMiQgvn2cO0AeqR3hYhTvanTI+Ky82zDkn5E37fXwTVzvPvJ7Slp
wKwsLOnDQrehC/0iFLYcSjCERXpcge4tJEc7XJ0glfphE4fSEDb9ZMP3p2ZxYybYowXfjLL8ZELq
/yWlIPq+yUX9hWivHY9XYwdGxqip6Dfpy4o0K8tij4QgeHlSoFAgvIjs5OI3F4FGd8CsGdaZd1IG
qWuILwJwk80/w7AxDHU9W5D5dDmpzSCQlahWuFXPTr0sm1pa/sy48zQxcy52oAnufZ4hEHSkmnLV
HxnwQ3ZmVr8zMSL19i60YsvV8JNgMhHoCyb2x2s9oxKY4BOZPRJl76n2zandU3KeWpptVEkRlqKn
Ekfka3npZcxFPtdjFg1PP5MkUbjRIzh0MKK2wNomCtE/DRMcU97Y3liV+W0JAmPtVhfmHyah5wSu
86MtojUeRh3FwLgpuCM4eb+upl35sUWiPRpvkZyh+DZTZU5BZJNWJLAzOv+zp7v0fvY1DPVsYpJO
Tr3F/mT5FkWw0JsnqKkti5M+Pv2C28wTzBITFpFhSEqbf5PWj+EGDOs640zc1Ht3UTuI9F0RJRLR
cjsiaFVJ1nHasmtkNJ/Ln8Do75wS//wicdCwF92QVF2DTEhE/j5xi7NG6a7WuQDjdlxfU6ovlUPP
SaV/uLdPtqh9wjgVaNd2T4SZZ2pfJpcsFPOmEncP5uaxe0K05EDI4I2lS966xpPd/iBMLHFuVAmk
iR74GfH1Yup38hTWCWImG3aGOD0QXkWzBy1+RQHzNzQ+hVBAM/QEso+b8RHmo19sU4esgqz3oXEX
XI6RsokOCkfS3MSbpirF5WZnAm7OK8FxpXmVKFjX22FReMEICx2pIie/YThcV2p/69Y3NOruf021
UYyu8QLnacKu60mFbc1mBbZcOyg+H0+8hya1DyOznCztcRPmSsR38YujWLH3k8DQtQlP2KSK6dIx
R1TPZgsYicsVA9UxKn4Y2h9iUVgEsXVVXnCNyoPEfw0jtRVzAAWsLQGW5DThK7nPNe/n/pEYqGZz
NOZqFNPrwrKj1Yf+LfEclXtEX6Vvk2E8cetJ01JQ7VqMO7dHNt/NeSG6V7JHNcN7IZa6QjTJGRfA
hY+8iZMvd3nbIZDlG85pByDGsjutZ4C4onWVXav5lmoH0/ZstxtsaqyCQpg73AadvMZ/m+vZima8
Dv9hvLpjz3S6AWDf7SdtQHZCl4oquJYUh2GDZ0KbxBhuRTXI3O5h42AfelA7KvwMtpmw/4sqKRvI
K71vkJYnNA9NPjMcad5ohBvbny5ii5wjhA0QYArR9zxp5oKkykx7efh1vsAopdr5EScF8JPcsKDl
8W97DLHCYYnX51Saz/fedJx5fv+kY21BFlVTbSlqwsMaTB+3cJDWAQcH3bbx2INVXgtmXWWccN9L
N8XMkkxEgvhc+m/SDTrTv9keOYujL80u6tITbZ3TOp5ApGDtOVQs5oPwmXuZhGUE2nU03St/ApRY
aVlwqGIsjiYTpLVO1sF51E8VPDM9XyfuwVvqH9WBIdekcHUsqy15/WfkorGYXL8nah4jks1aa4ee
834pByxNepGzif9Xv2l+jQLlv1uw/ceNE+DfPFYlR9vo61nHnWl2VdPek1IEEGF7bEe+P96DZqFJ
/NHh3F/rnzEYLdMfcCnN+Jub0iNaMv5qOL4U6pbTS9H7PCl1v4AvRL6FjNHdSIaim5ux10mXSFF2
cNH4lt5tv13KKxc1OEGl1LKXtRGRFxfupB6gOXuwhv3w/CAfhlV7kk50Jn0yARvv2RgtAkrbBPMh
GbcEWGovU0tiF3oBIXXdoneeX2RI/4yUDr/N2pPLYve7OYUZtySZUJNTjgOyozy3kR7zOm3Xepam
BEGLay3CWRfmkeVZ467ATpw2ktbfMeXyHOsKvXFkqocX/h6KJmkx/KDEObyvhF/jSNVRjJl7HOjI
FCd5G6q9ZINhetAUrhY4S2FZ+3Agk5g0RCegf+sraOMmgE6YiHQOtvy7ImkNE21bCDIeIfASMcnH
2syQnEzPPKiXC/iKaehSe2MSBatQW58hdbDdzE0iVtLOji9wmPfgqdFCvBpef5ZPUPddFABpLt32
EgQ+Fjbz8VoA3tJNUYdCt7gn/WKeB1ozhHyEnegFiL7z+8YWw1IhzRQZEgGsMQs10uxdVStXCWIh
gf0/u/oUnjsLjhWM+n8SQVHXB7q3gi4euBMeZqplHg380QuvioCjKd/2t5fx8KfKbbGcUhci5AMi
7t5d6sJjldTqUIdYhYR+EgoPBvUu7SKJrwsgBK+K67thuTeTrV1/vHiVUZ2sKkHOvRZzt3410CiD
Oi9JRHbE/PGmMURlkTQSSK4Ykf4POrmlKzIzj6Q34r7P7pk02yQe1T7Fp9QE1/LjWCU58u9OwXRa
02nmSwJEh/PjAXD1fivHXTAMFlze/pHwjPPNjoe+7KISSVzgYvcQaBUv61mKlPfXbc0FSgQpy9lI
pAHs0vygTb9Lh/tTcy9arHvWV9EAM+rUmv4OjVH7oB5rxCMOlTeIoLtOqSp0FgUoMCHYwmVfU7Ha
wbrFuRDjTT8iByAeXVwu+8FgkW5sjLxxlLQgUbK+3PnjUhPd96QVU2vexkASYDtFMvAk/IKY2dJv
evPbtidOixBvvXg4mxM662YUeSH74z/MUkz3eXmshGmI5T37nMmtEP/ymddSS7KblAZkn3UUJntw
WyQCZ7a4KkibltaZBfcJjyyUbQmC4tEceMMv2uR7iCkke1JzwsUwUS86cVwvJwGa3H4fiD0zziSL
JUpy0Vi8A5qLVF6Mlyjg5wyMJGpCrdkg0AjIcA6DgnuGgB2bN64MguHoncInn5yaJ/Vj2oIKNiWj
gUEdF5WLQePl2MJ/Wfs723GeGGAQg09uD5NfaBxS/lWEcCGb1FmTatbTVUQekK6hxi71bKFemG9d
H+wCcSeWdhGHSzipzZhKBapA/bJOKsDWxiPzjxyQ3U6QqU0k4JHK/DPABf9cbsIRZjkl4Aq7TBDs
mFztmJIE/Wmz9itmolPrCEHzQKGp6RwCIThFT3EWHvuUqRC/nNxxEChjHJAkagX025dgzcqeMYgm
X82i2eCtiFErOyF9OPkpPKcbe08Vjh7blldEdn4ZOeDIfKwOvN0Ag5s00u1hEgHtpQ/wGz4cBVxP
JO+O0+BIXkuAevxQVe9tcrxo0W495zbkd7GhBW/KUZ4ZvwQRbOy+5EWBi/+pfwXgxSOOnXBbI0W2
h1i9HHmCeWtgSW7HgYKYM+iPm9JgQvi7iWofiiEf9KgyVZVUM2tWhEniM0KaVkisSttfU/9k1PCb
WbrhnCJHOIHrzXo6V6UpJNcGvmaBZ63JW+Xy/CSr9Qc48p92qgHhW1Ie+JO4wusjFFCqdyJhRS7O
PW95FHF9/O7lkzFENRadoxRd+HRdC2MOBE+/XbOBZisDgRI3kR7Qe+ySCtlTv4HPBYHM2Tr6cy2C
UbLzCKqiK8hSyw/uxeSTeTo47vmxgU0wdi8/hhxl0DY2Sx2qfr5d6lVojHKuZiH8jVeTsPK5xswz
DYIRY2Fh2wmDT4zJk83YyBPnlGXLjmcX4IY+MFeVFLuWTqmYw3AiCrNntH5fgN/A7Fzz69ANij+1
eUvRxR8GcLeJ3q41qH1W6pOtZFOTVbY3eig1zC+9doJe9ZpPPnfFovTkzI8NBuwW3aCgrFE/J0wQ
7HlDlboi5V99psBtVZYeTDQeVJaRWHbnBvKCoF0tULYIvvdBOFyMGgGIXs3iPPN1Z7WWbr1iMmKl
D4u23ajtMz8elpg0solS/jGYUy9zURT3mk+M2qJcM97xEvZQd9q9b2/Tk4fauQ9jqU+rkdxi1VKe
tum84XmAcNVkmBnD0HAELzkl0bFn/OfmCaRIYZfEaTOqtlHVGrBJ235v08lCJSSf+t3HE1dbM7AO
EOmmO821KH/ovpRxsw8tdL/2OcaZJdQuzsjpUQWLAvtkX+eYsv2oc6DE6BvZMXrEXVNKyDKyNPs1
04ONt+HH6ZmwNT0ECYcfZeswHHk46vT9d29FnKH04VHi49J5pVphzQnYxpxrjBT3OBqzFVSoddib
MXnFJjHfoeoLS3RVFx0bF8IR1zTiiNR8dMf+a6ngNba/vHKAS5SeAWXxSdlGOuF5L/DwHicsY2Mh
pzQOKKUwJcn6fEOhQ/L2PxiJykzap7oE/LV3GpEPfTz3bSwAmdZd5p0TD49cufvTbIsJywjxd0oU
fosq/EVyQEN8Jba09gGM6LOnTCr27/DaO6uRNr4P56B0t7PS6lpM8k1QjiTwtsd4NOzaQzhhis9h
ybXNwuQ3Z0sWh/LnqG+Pa3lRcplzo9Ke+dwYNYwBPTs1nkG842JIR3Ok4y9EBeYrJggOQ7MSKA0T
0loe6eTztxfA1Ui5GfhGULdivKzZT+ub5mRglU3AwGPkrjV9Fk+sJUG7ccBOpt5xXo5q4URNawlB
J/p9HJ5cP3KgfUwUqoWsWF8Dte69dCAwkV6RhvzqQ/OFw6Ej+KANhe5W+j1MEXHzgXSp6nwKJGr9
ciumv0bYG05dk7vXGxYKl9L3pgKC1DeMDeZ1Uey3lNNITaXMeluBkmle7Up6ZCqmyCFFCI0WDI+Q
9hWg+oN83HF2ZuOwidfX4R4/LcAyVa8/e0BxGt1XfkfiAmOK80GU8R0SyWMjByho0e6uxj2V1/h/
lk22E1ga6r/WzfqXx/tJGA+7xmVTqWFldqcNDtk6UYt+Lr/e8z7CH3oS+rjt8m3DMR/58dxLk+iL
8inhe9eNWgy3Qws5KVU8MKigsZIQ9/3+/5dnvvM+FcfXlb5L69DfCf2xsrml5OKQcqFPNXCaxFSJ
YuSBTe/wLo7KoArFEUVxpU7KrlKelZbWguachuxwl94GRY1DYmtSSQ88GJY7IUupTExBhz8JOzT6
TtXalbqfqLQllsBrs1A80yus7MyAfYYgpOshvhMlSGLCTIfVq4/zgqq+7/8MJ67iVhi0N+ApMxeg
96iFdcBB3hxuwJ5Qr0y3aDCJwVtJBvzpVpH9V4yPKG797xcm5fFOxoQ2ZUY97dSbrzAlXaUh0QFp
m1Ex5WXcqe0BuFwE2zXFbIwiKBfp4m7kbofV0RMm1vzDxrMdbLsSFBpv8lrHNs5pbDYkvoON7AyX
+qpG409DQR/7PJfEr6BLYXqvEOu7oipyfRVqsTOed+jc1lZ9i064WqXH2I3O9tc1P+UhNhK+Azlr
UVoVz2jKFVemzTY4FBqyxfl8lMsyv2iQzL3iaDix5DVub6zarlVGKJUg5XV69C4MPI63ILV1mRgg
HBw8SyXAGE3kxn3WNdkjlQVVzgjc2Gwexx9oDiwZ3FR7r1x+oM+GQdW977a6IwRlHzjOsp0zIbc5
Lx4fFF32S/mB0Gz1jZSgkZnROV3eIJ4re9+i2K9u/kWiiekcUAGE6UuNXxKdPy7g1l/ztVEh0Ebm
lhqY3LdRfmLKLU1YmFH9y81UvV4pFFw9sEqQ573bSeBPUCB1BpyHIwPV/M1S0ouBXnV6lGuqt2+A
OtaH3qYBH/aoPtlryQlLVmLXhmuCiKf9i1/RDYOEk42TL2pNlbtW+5kBUHCi2Q08t10QaSCqKOk1
HOjvkD6CwkoIovO27wvzCoiu/Xo9CfGYVceL70sAfNEMEtU1KZJjwYe1RiN4ibAPF4iHPPkDSTIV
waKlznlUr6W/qDV2YXLMh7sQAtPzbTtMEktI1I44wfMqo4zg8IzzXn7nntZ050s9VOGLycJ+8iWo
4x29A1h4GnfAumt0ZZqBWu11iA39J91qDLDvr6T5LNbG9CX51n49xmZT/cNoxKMyStdySdnodZTY
0EgG+J/dMRTqKLVv84bPbHyzvx3zW3c+dqgiYoyeHDI3Pn8raQoBGE2g8ud6A+mzdjyapA+CTucj
uTw+OWwEtwaERUjNVNwIFQaMAPWey1m3QxeCUQRg5SS2qPRQgIr4ueFeqsSPgv/BHJI75Fpbphz9
E7/TM2JMj+E3FYssrNE9HLtDaoy8EJwYbVsRjeYVBVwlh7x0XnZtYwRcuYNjajk3rfpLR3QgtaF/
RQTcBBEAIXXD+XmlyD7TA5Je+4UVew/OZD3rRotrgQllksaaq/12tKnfyXPM0cCvGY38JU3VU1dY
mvcn4MSO80BKxVv55bW58Vfdh+VgEX5MxhXJ7Zf/OOmXTxSeyL4ExhUUBpVqRqyNWTzz3Ps3NuIm
rQbFsRm8SQEq9z/pSKmkh8EbBpKfsfITADyaAE4BwC76Wb1kZDRHkamr7i5Ql+HbVVwFWgVZOwa6
Jvb0tu5l9QqCZd+AEuwlsBcHOmP1yiYkZ7F6nMN9HNGCWJ1OhxjAhhzi9y8voaAyUHsVud9StjfQ
+/0PkC4KJ1p3+AuUaaSkwWUXUzp6DiOszVww0JAwoN+j+vfZGXHr1slhScCrfyR6tC9AE1BbYTPr
NzgRyUHEWfokfwKFYQdcTSCIDPVTdpMAxIwXwAixtS2L2LYVCTzYDJjeEtTCoUhRaMEBifwzSmJ/
jtFEAECLBNaBiB4QV+GQh6Pkkaoi+J5T4cc3zUbnPC0fLAkiJRumbxPHqWJUEHueernbX/MVVj7G
Ac6u7PDlhqOGpAyfBLKScAqzmJ3GAUKdt2r9BxHscEMDhG7Ok3k0wrfRej/+lM9wstN0Jae2For+
GTsTAzVoUIB46RJ4wrN2VnRyLPhohCXNcTTMwUjn4x6qDJljdqh7VlnmT2JRqp9odAtO61uai6k6
0US0WJqnOVN7LJehxRAtsexa6ZZMm6k29j2cZOiXc/7nDg8NxwMLmD3Gr3qdw59BAIBMfejA9fUz
P8gBDK3YPdF+rwEaHT7QAxmVz7ARO0a1MbAgU9ORnEohykDqhfzVcqQiXL9G2oBKYn6bI6uXucWJ
bVODGM4BX2aJiN8Ch2JSkMRc0ySxS3bamuEF2h1GntZxE0mHvDkaHPaXayXL3rwd3EVhdSpI/iTw
MQq0Y8Xg65XVBUZNJf98WC0WudE+eG5ADcxVLXdyqFtGw7oPFMwYcssWzuebVs1FL81yl8O2IEYj
ZTWyw8zw9N5AbzhYuqFagnl5SsjtuZxQQN2UNyXrhWy7gM1fJOvlu3fBH3RzLQau7NbF1cBMfcFV
q3y9IucniODJvNZCGExagqmLJF/wx1S+35gn1pAxUmup3+lRVXDkJHlTB7U/66u0KU++Dn9RE7BA
HtBAUOvdMljbnZTPKW2DzqLas/yv07TTwBUgPPnocKY7r2TZNtIUEucz3E/8HJP7hV/7QVOvijuc
zcuUuzDecTRTDb7hY+rHWK9WRaxxP9gjgi8ukw3pNf76kNh2X4KH9RFCt/oqXg502CUIfJ2E3gYw
STnIpxZbH7ZTUrgmEoh3Ne6tOah7Ayah8VOK49PJidtyhNGfL5Pc8Qf4tlqeDSNWIbu3j55pFpLp
ZQtm8/C6Dbt8YeZWe1yypqyVCB24TO8/DxvQqQfdiiXo1qB5ezONyByAI7ysgbfukRxnC9qKkuku
i0ljVy5KEqDGRQWKqyBlHXHWKhMAWAuzXOecb95nIuKxYx6coMIQQ2yo7VCQaCZYqoCpvvylqw1l
czKLViZ62KM7C6z7dp/H8bIPZ0RpYSXWMmr2UhvOOootO8ohzcb+8E+l3SacIBlX2rWfg3p/8ce6
Yzvnv0MLt4D2Jd+1K4q0Spc+UkolsiZuADTHq1hnMxkkZKktPxtjM0hnZMxeaM1XCG6vxQw9eZCT
Y8fyUuR0a6hiv67pzTKFjXEHrjp0+AanBQRBHTUQzVZztbUoHbEJ0RTfbgFSQ1qjQUgZpqzZ503J
FiMV7QYvGKeqy8QYryfG0l9JFW9tquYWE9TUty0CAzp8Ze/5KOL5dFQweYgd6LfXaIJ5UVxHEj3o
uta0AjrgRxCwOPGDztgd88bGhzRLAJ7/OLhzoc+ZMlLcb1pL+6upDLWK9hQ2YaIMrZ5kUBTNAqYP
oHAwFcXrIHIe7nQPyYNxFLidCuWf9vufPfeWfMDOPT2HApCj18CM82/83Ko/wDeziGb28d3C9Hfd
RvJzVTgjKxI1HnJ42NSImnr+1dugQ9OXI/RlopxYB6zXWhWlXqPU2IWkfrt3sISLhUWVLhedwmnQ
hot8gZRUA0ltdG/gkXSgJt9l7UnH2KREPnkqd5AAcBwLqhN5SMPl6nDnT2PxpMx98h8bId0mDqUe
XKQzDYe8rODtSjWEFCQnJyN5Yck8cWICqfiQ/gCS91ra4k2aFxxSg3pq0AghA4AYN6ipUkLHEMsd
8x9da97YEShugFfF6Ibcdrshi8DzGtsehuD4qn4pDOLbYX78/hM30XL91y9W/Lc95rmguMRbht5G
Zj9c3/0qAbypbDYzjrhCuM37wJzpiMN9gtpPuU2njHC7pBl+LJRPEguM0PzZz8EXnXAeU5IYHZin
7Uz+v4ooH9jZp+z1AKAmdjqv9nGHQD3kZY98lkiDvp4g+ZwTLoFs+8TjaNo9yG7Qca+TcxznPvRg
P4fyBEktj0L8cB9ii3vnaJgwK7HYAHeEXXCf5Y6GKtKp1u+JiQR8WM8ab0PaVyyp683YujYZXwS3
SlRUCYgKAjMTuvqfW51A2Mq+LI4ONcI6UZ2Amkpq+QvO1uOVLrWkY70EGfzLFLHViQ6of4ATPpaC
wgj0QT4WFXsxM4PSeRArSkyE2BeHm34MElVv6P47B/zx4Bj2aWumw4k2SPYYzXTqqc1fRNeIzBS/
gLx9bQZQYm1ujQ7Z8HbiU+dLAItxFpVDlf5jmVru/1PDmE9HXxn7b4V7z1WA4jjvyjEUXL3Ak/ZP
0hCTMEclh3JzuNk/GGJqptq2A5K44heS5u58Zx5VSMwyKN9h4pqhbtdDwZQHcyAIV3jx43iuvYBa
ptjSHpI7dXKiPO1QdFwLRmH/mg8Gedhscw8/j3FTSR7PpNP2fKlDWmX3q5xUfNHb6TEnOqd2GurO
cXABHYpInZ6iTZ3nkTrVKpaIj8bz8Jyy7ZHkfMjKnBaQRVaXbB3GpHn8iUU5Dem6VbT56YDuHoyX
TyVkiRBLHb36WKWiCs1Avx7lP+Oqk00XOFg5r8ta5aOL+Sr7nrgHL9MfTLPiCCzTBVM2XHkhdWRM
i6kN2dcwKkyKo+i+8/Z7Vl8OFq6ZV1QhWoe/qsaL+G6xZTNMwzRSo4YrSqUStPeoNwXW7ZBX5lHf
K4tcaVl/3c3WVckRoO885zDz+5+JfUom0GFsr0sPqNRRenXUwOEdd/EbXjJhP9tR9/8I9MEeHVTN
LhBza0qhpPff4pHYvd1ZfVLBp+japMAQV2ebqzrbIsGyFcrWXcZVN7iwgNH1IcUmw97Hffp1Tx8Y
6AmWb3ywnKzMpCrNhWa241niL+mZ5W1BqzkL/oGzWPjJTwaZCiS69uZh6m/yCalL8kEBx6S5pu+Q
Hz7YvOQxO4SlUGqPwqJy/q4nCYznqUw4RY+WTBXFd87TE3Vex2sJVV1OQzSo4Eb4tG0i9Zbf99YW
1WdM9KNGbiKYXbEU0on8bgO1tfrIP6LRuc3/hsBh36gYmC9PPD4lNhurqC0U7AW+OjuDledrgVOD
i44dnEVtNc3/ycv4S2mJvMfvh4/Q80z9ZVkXOHMLuzH/nCw8iariQiQG59PRS28JFlxrXiAniM1Y
Ze/KDS9GanYmfzyodUGImZogCEzYcLKl/iD2uZZwJ2v2FetNBu5oZlu0jRnVC3xiDy9dzkiVEnca
Ha9V4b5IobaK9zPCgjClQAi19kTTjS0creYyqF0J5805QXIaCkJw/Wz0pgrB/qDacJjpz2HDG9ig
qRd0IL1P6NG3Yi29KNL1cV5KPi866LPtO1eaXjKqNGqCSAZWrq77rb5zqkzNNkkDD05NpRYu7HAI
YhFbeepqvurzykeA7UW2SYxvbLZYOdTwV8SCrFkoPbY0xYP0qkxzjyFrGg6ESDPuVOKokp968o0y
riu1v8YrKoxik5hibBZcmzOTF3dVJ0rzgQD3Bn840f/FUU+jVpZPHXbGdCrCoL7b0igkwwm0eSGR
ZRlZggruMWUvz6Sfx+anoNsQoi3Q+1933UKP1XnpIHZi2w4jVnRd/FTjDFqgyztgPGZJfsMOdORQ
TtyeJIKP3zZWbSckKmo102p4EEKPs0Qvf+UbY2LBiCO68vUiFFmKdF2OgrlSApppu/vpNWue3Gm0
vU7T2Pn1c1Cd1s0x136pCFczoSFBaHgtAmuYFKk1dLqxKEvWQAuPI8B0++kJT3s8AoHMsVoJJQwm
jVjN9vhlMjRhJynimiLfQ+amIQJmKqTTOVA2KN4PV/5KzRj96F50VgLbDh7IhJCUpYCiR6z+TMDI
/cVqCUgRgVCzlYtzNmeJ6SDOUxF3u4Qjqy0AY6xpxyzetfYMBvHrGjl7vSLlFXqZwN5esRMWyZO2
n/zOKxgSbTrvAdq9Kbt2XZ/NpANz7vMhJy3WBstoVU1zm1vRUH9Wt0aszlfR+RlrlM9n6TBB3tzd
gU4B6tTrvsYJdfWy/KZGELXkiaj+kC51pE8csP4Imvt25kJiYC35lDoAAHxEyHtlXqd+V55Pc+5L
/ce4zSaScEqQ2iKwmbPXbqeKqkiP1vuXBshe7C37qGSPVJffaE5d8Lq+hOh+bk+kCiZFqwL57Fkn
bKz8HUtcFqroqhgoBmgzsEridqHqKuTjhB7T0WUbsn4TDBB7J5GH2up8Z3TCtEbGq6vK4ox+iOCu
8kyaiAkYmS1fGGLwPR7Q4RWWvmX94iQtuI+GGfQuJoEmMe21WEsYqx/36/P3MdbWV1F82bOq7wyU
zjxU5oYu6xqDkdf7svWipOfSPyeu2TRJdbfcCvTUeRHRBW3t17l/CGPs/vPdevQA9GrBKBn8RpKI
muSyuH647WVB5hRfZwydtUPM/5spjD0dLZfZobBubA0/gR43bqS/2H4MD1XSf3K+fWbbeSx0+LvE
g5rMM1fNFuuTtt+Rak51JMit4yneFdPgH7DAozahjLPPVSg0UabHpGbGtba+TKtey6ZZmGlBb6al
V0oqsQ4X7VjQGfBOQRaMBFPgX+vLXXQj5vxaCCO3TvrGIXvCm31BZdza3xhGSMgf3ugRCQXKQlpb
TdhezIKjT/QIXFUbSfEnfh3NJ+EdlmBTFW4ACy/lqUjfSu+HO/2xc9IF3C+pL7hqplsJsPnzxJOA
lKqIBEy9H4M8VWyqabXMW779R1EEUl4Ug4JxMUnKwnnyWaHyn1BKbFn9Ff6zI/DmyTdQuMHX/e/Q
DK6viwphruIbq7CyBR1ssgUOgKG4SNb4NOfQhlhGJrmqcU82KloNDe/r/MRi4sbYMsbTUTt/TlK5
JhaqUYsFRdpDEfl1tMXe5lB9Y1vC+MJApJUGN2078lcL95nNCzRSKKW6K9NNUHFgWj+sHr54yDKq
VupvaVWP27decGyEn6d75doPzWI3Gidswagkylpb8uGu+mIzz+wZqJgPCbtXt1ybPr1HkJ8/Inx9
sTt4kr8V9M10uq3CKIQelUhN4pX7UWg+0bEDvqueruua1RigbdfTv3ak8on0HYl/l94IvPUSRkyN
uzufVDUV409rCf10AogtobgqeA11L+O2W9uHDrq5nW5QQT8rwMgnHDXQkfANE/pZccN/Ykaosuit
KNHXgYUzOc4/9clJbuaFWK/iAShHe3E7i6fQ6xdga2yMdixCu6dgPxl4EiPGNMtt+rvtu/bpns25
d96m49k8kzsqJaqzY5HFFB52sLP379J5EAVjGxm/vqsvh5sNUrELEk6Rmke2+pP5GdF4uTvM+hSF
vAP5/k6Jc+pbv4N9rXmcQI+lu//JJU+ek7lw1EerpKE9n+/R6U2QjpLSlDwCVWqOvdr9cbgtMpXK
RPZkFOBYAMf5sPrrJ4VqWiOxZLgdK/T/xZYNjsf2lCLaWZ//7NjaUpwVGwtaqa5wqj/d4uqXvoK4
hdBPE+r+jWBgCzV/lP+HIhE/bUEQ95u+yzb20esba2HCet/Y2RfFdi/qhI4U2zZBKdhxrEEAH4Y0
j7kzULqclzuyj7P6Bm5Dmppn32AtJ3oNKVDUC4Fy/WnKqwSBKJjSX1Hf0zcfWii9/7xnRudMEMpi
kAj4UlkEcwFb4GHGgh/8WQV0f5uamEh49qcMwWgSN6UFh9oCxBABL7cz/IEaAoDaWMOZDVa/mq3c
J3qqN03u+7JxaPCf2FPFEdnObUBM+c82kFkuw/Bk6CW06P+ueNXpStkiM9jGZBeWoXlqjUFyX8u3
/WPBMJavKtj2XtLM2h5IjkXc6bbvFsLf/UIqGCP0KxvBN3rPG/QEu3BS97xxQ9susFFwVRJMgkqf
m2rmLBUjDv/r8pTH89QRoGNFj3fIhXqxqUq8T7FjwRav768fomS2C9cND51+mITIKYYhFb0kWVL1
/yqWqZW6RmpqcNNATE7Bj/ZvvcIE8Uyf+3ljqEKF4jJEFJv0gtY1Dp6puWoS90POSBpewfPvW1q1
2NPcSYuOJCzf4A3laXMdTui57eaOhs/w5Hf1I+HuG04v+WF960KuGUU2MAquKtACk2vfRz0jHmVG
BeyEXmmGi/ncjoF64i9/+0i8wXUfPucFT+BCcNT4suryqrTxaI7qVjmmpIWew8KOXHVoq28nd0RT
so3i7lwUxPom/eRrNqEj+kr4cL4rla6AnynHy9giyJR24fkWh35bhRvAFzvjK0D7A28oa+EcnB6p
IwiPdVlSf6p+LX0bn1YLMNMwiit9/raCIO16ccnfA+f+6g9outdAIQyBFfVEjZ+3CizR3A5DiiND
pNd6aQizE3zjO9UYqTF/GXoDUX/uswnZpORAHbrlKmB7sz+Wo5H2fMHlSlzEG/lj7bRWapbgXkkU
XOCanveOsxqJ+7aXP2x8AU2+H5qAfzNon356H7AaYhO5MbghJvENDT+jai/9owLaQ+PNVvbAg0zg
e7JzBDEAxAMMkQctf7LeQWKUDi1/TLyCYGIrkxuotlJ7mdAGriY6C4IN2EKJirVsgBOX9HBEFRh6
0fAB/rqJBTZGyP31BhSqnAoOAg+x1yeL9VWWx9xgAdpF3/Kj2aS7S5Av/0gEY17VV2V3318wunU6
0gXt6nvFDz7Wra8ZHmjy+mTFnthq7SYwnW0j8EccWlNpH2YgjM4/nVMUdWnhpoUAb/MAocjgKEqE
9qDJUtPKXfDquNaOavfPc5rFnSSSE2l5RUjngKaiEXeTWPlsChKMHnQK+BGvgenv8SdwNCGj4FoG
zT1yKaaUJmdVpyr4ZeBaMr30djkeCvJ4B2zSaAbogt/XbPx7ypLHc84OnOpKRXV+scVjQwsXoSsD
HqHNqD38RizodRF1CKzCVG5Q1o8VLOqL0MPUoMMhb9+bS0DhNrVypgFnZOe7upJ651KhR27LmxUw
vPk8TSViIiMFIYMppqgNxRv/4i2iIVfTM+X4+EW7G/apyeMnkLxzE7plqceTzjD9ievAB27w0gbc
9lyLNdoePnn9ZHwLIVsd0xAozPHHCr+6WB1SwMOSQvw9vsycViju5fA/u5sWZa7X4PIr5JG3umEC
V8TA3W6GRnKITD7oS3iGhe5KmISz3D7CddRugKycukXsKGi+EVWOSOUIFZJqZdQCX2doTO/Ghsok
aqys8GVFcCGcccaBobSvBvUThaiN1Bk4eClhNI4bkg/Hy4xna4QQYUKeyYcSWC7dCAEpvBKePHLx
tM+tE0+N9kxHx2052l6XmD3E5riIe3LUgX/QPZRKEvA63EofmyHDOIQkN2KAceesRawkGuu3rZ8g
b5cao9l0sXc3M0kZ9Z7WO4nuRZjnALMdFxGdkldNGK6+roAILXRxfTi5tFEoNee+gyu8I8/eY2c4
NOhc79Wv2xgYIR+MQfCDDdEpncJ/6botMB2V8s2faBaKGEBXpbbITd/4BWMMFUR0rHndso6iKw4b
nNH9x4w0IYxUUfUWO9/MJe4XETa7RqblNLnKyRABMOUapHwfxhsCJ6ETsMa5HDD05OJw/JuLLaHL
NEi74Otucsna7a6rh8+8BXVXW3v2rHcobhk92YFl6NX7t+PO5ns9kC98htiGTtgxS4gDxaXNIPDo
wCFIga7F3UZqSka+BgAGvOBwkdiIb7PyT75us74pgwYEh3WnBf33A+WI7KADd/ZZ20yl+AAbFr4E
+BDGCdib9uQ1WdGITngv2MQJSXrlKGEju1S+Qyg+zUUmh8GZOgrubLY0qChcpceRy+X6BHtRRJ9j
FwKEjATGyJoTImLpxV7s8JBdWjd256jwLPfjkdIH4S5dARyZhybUSDTHv8l390m1mZlUKrVAyVMX
IzzuueavzFoQdYqqZtrNoA7GvFhqrB4no7wKv+pCm0dq5m/Fw1F81AwjisdyaT40AklxxzPli0Y5
YnD2EKcQdDMI8jLORPcT8tVfyAOfeDOlR3dFzwJxoSRY7rGkkh1BzB8k31B8izIID7UGUIIdNZhl
zdwrKy5CvrdjFKlD10Q7pZVyBvwfJI504z2ZXMkeTbwKny0mFrfj8KhRkKKLf3mWbcRCmngpeOlq
dZrTWO8I+i/98Ea5KH1uhSCPevXOkqD7zp38ZAX3adA7M72IQVAEi+RCex0Iw5AyzTRUQyKParxY
NW4TyQoszD8YkXL7Q0aAhkp/RxT/zum2RoG9GLNFc2rxiWqS616daOuNS3jrwyld4e1a9XFspwE/
+vNf3jf+3KSIEbtSi2LJ22If0WN7lLgVrrmZaCHD35gt+IfiKRgQPkpIBsUeKqdemEW18nnaSClx
PnyGdeCEFp4k2nMs7jTThqj5WsG5Wp6oeFAovOf2CZEsXKOKMlBrmcik6J4ihJOtSNuKVSNV026y
IqNqLvEUyCGvHd4o6nFoDQpH2eyayLnw3NsW4L4alKOdDssdaj3rT8BMFxClfNILT7p+EmA3sB6d
//hAXZj1D6xBd4RA8Tn1srFkjx8KxrRYJC76MGCiBB6RwrjMWBIbhXro9X4nY5WhyIBPaQ476uq9
1RxwpMsQuG+c/IiBVAhJ9oLC8C0CAiz3xQR5lBbgrkgWQ+3+11eANBq8n1/jaewrVbwjYcfWSK5/
DvCG8QiF2HV6ouV8Q0nOUjR+Ar8g2dMIjBp985dFMu5kmo0UjAu+R/+lXOUiP+COF5xsr9AgpXzn
r7v1LUYIUbJXQ1AEkDEsuZzXs8lZ8lWEnqZ3ZBdBCoMFx1MwPc+T3K+lD8M+3+rttJo4GpZdTsmQ
w5Krwe8NrWYNzxTHDrPRRXv81F3fPxhsmXaWMuM4J8j+9xWJr21vCXvLhP4CNXSQD+ehibmi/rHX
58zzG6ja/1a2r5ObdCSCpCQGC6Ancw2QFXWzS1mKUA6C+Z0+Vt9v6ab8xpaTpN3kIlxiuPX5uTXw
+u4JRNdY1v/cworqg6amzHZwTTiEwgTp3m1xV4kcKGiQXDuwcLvuVLgORUB4KwPIpu9o4KeOA77a
cJMAMDB55lQNr0LIvVTq5q1HISRJCWwqyOPqXS+MEXb/REevmchfEDgmXxXnoGmzkqvCM7g2Watd
Crujub00N8pc/99fPm9Rxhcs81phZ9MrHlIjEL/20BL/XdJdyxLhm4LcRfauEAhhapMqTI4gBg/7
Sw0NyUw7NN3aPiepFRGa/SmluBSU7p0ZHGVuSGaelh7HOgnU4XkV4BmKO/b9UfhkRsAbn9bvTKBO
4aNbOlzUOrlr5dGZeofQs7afw36OpSjM+oX7XI7V+WADrtwrCSye5S8fqcP4lmUUi4KL5XoaLKC0
VlR7/unPW0PsLX/cf+hKgi4+F0fF9ArsMotAUyfHI5LSdxyFS+JyJQ6PBlMXhu41AcE+9HmWlOk/
UkYfJmTe7U8m86azo0wlI74a2pUpIlicKe+Xp3cSuXt/Cw4Ma40fa7orEvuGAyEOq+phhHba+2AX
vYKturWdfQTI9gM1VjU3uhrngaLjmUITUrts2pJRBVKpn1QfU+ZvTc5KvJf/S1i4Ahe2NW6gcUhj
/3so7g6w8SBa4XMAubwJqV42Qz1kpO151kfaYLzWJGUe/D8VftJ/c5OkS3IdFaW9IgPXEbGz13Gc
/frYKXyVy8wyqfo+tzNBPhsuWv4J2weTTnHw+t6qnA16pbs++VVgbPkimGSvp3ogYFjimvaTbpez
Adg4gSnXufRDfJwH4I8Kq6qB6jAEG+gyIQOZfG8itA/yA8a6JlAKi9GqK1eGcGaSW0isbH7QVQE1
1nOG4sU6r4vCpMKyUiKrNcFq+tYWSQVAcWnQ31hNMBhd/DRB6LlNEVvcW8LiiHx6jJm+Z3lwYyqt
i+j+pLVn/ie/ZcYe0CDWist994THwgYZpayQ3BDGIVr8szgd6LVG+gJqSyZrf0wjNlO6nnr8AyIM
ci7WthaVFx381awJhEocKvh7iO7/Wlt3F5B8nOGUfRA0+VOu3jum71GaDlECZQOYPD7MI2Wbrxlj
8H4Bmc+rOIU5H+idZlAPRJZOjevalDhIN/Ek4u1ibeb/t4MpHdBZfAxhWF4UFETQ8XS4mNno/wMc
2efvG2WTKRBpDMDFbuwyWJbkKgVHepsEEj5YeViXZYZVlqOEBhWiYysa4e00RZfZR0+7d6fIfFqe
hPj6tMGPuZ1nIhODve5SZO3NdeFUyLZMniXfwWM/YawsnkJftuF+taK+gG4LMV/oUHoC0rDTdzl1
7js9xMt6IKmmWISk2XKPfrupN0UyOeouPCMycsXDFLIcRc2oFKG5G3P5ZVwgKbGyrElARTKKSy2y
PmV4XCmbuc6AZ2KM+J/9H7XBVF2MPSt0x4CAfW7pLlGg/131uPXE23bm821iLqjyxvEfreKEOCtT
dKGXnW8VdgoRg0/Av2jnN3CFmRSjn2tQb1XiuP97/7rUOLQzh/ST5RJfYiG9DugxvfRWbWjy/cS9
ACODOE8ycpNZCskh+mWEQGKdhi3sYXuqJ9xq4dQm3pSs87MyCGw1dnkP6AxSXQT+ozUEjipvAY7/
wH8G7EXp+ahRnYiWPzs7iyjM65ja36yE2x7+FFeV/AaSzo/7G/nhoHl0XNTs8cSJH7hpuBQJzBMr
ctlJmHRO2vH1KUQy40KxKxuOksQI3wY8uCpYy3JcBWM7MmLm+WcEFT64IjTA7Ua0E4jCB7XzxuqJ
4+nWA+/erHU1QVT2+6cJk+ykbaq9XGV+I0hopGSvz8FFtlHzZxqs+V9Paf76BHaL1Sg2F/bPogpV
i1u1FE9dNzq7hLPfZG2EtIHBX6bkW3jo7eu9/Lpl1PKJCnGv6W65hyHgqy/FzT3IDHOAKY1F2WG8
NrqbI5v8EujzO22slGVzS7UaTYBGL5touB2zKjfVOtalAyf4W1qZPTNzWQeMxbd5pjKE/E2IuvZR
rweeGDrooOO7khZ7VlPxZUAzM9PJ2kCLEPHjBGCpslS1Lybn8vEeCEn/5/n10NvYBdvzdYroCz29
IHYxsumCzqepZncFMjDeEyG/cq+imByopuzGJ3bQ0C+BlNguUvr7ePdhG6jPor64dfGueSKAD6Z5
9bC43f9JgVcDhMtlzH5NIvHPrlol6UCggWzC4o5YsRzu7fBNm5syhnhSw9WhONzE/hCjuG36nIL/
kB5DC30gYTNHX7FqIWAE3b+4v/3k/52PKq181DKGvdu9nMkxqL2Sh45gL4HfPBypSXVRs+haaKFU
z6G/4GmxncHFOG0XVcFd59/wQZKc4NClKVJNpl1eZryUYYbzVXTIi+72PxJIvoVG12mLvgqf2/vk
wUOeG2HYP2pRpck19l/ARR7raqmsuSohErzxwto/5j70kWCQ2D5NtxhsN5MuoMj2Hj9PfH+TqDR1
Ub7ejG4ggn5GVbld+crmCdc60LkP/hUbQBfe2JibXt4KnZ6Z4elOnPY+VJw8tv4ij9nLamXP0H/F
CnUrfJEEzZKGvlqxuy5tnFwV1/bnqy5jtvIibVPgRqx+Lj4m9GUH7mZk80/N3iq+deemUqcL9vmt
Xgbgtp/na7SvOZhJsPo5g6D8YvmlWofRNrXBQS+ETOBtBlekf1Y0xLEFo+NsERTP2ti9T0M5ZRJv
FdYkn8YZbzdVIa5hWJqv4zhLLUpstTRk4U51VHl+WS7tOoDYwnU3DqUX8CUxNf5t0rc6H2r8r+/J
cQUc6GmJePdEtb/c+0lxw8nOiL0AGPaS1AgqhLEcjnWjvHTflm+YZds5lrW3lgpc8gdUJ5x3afG8
3t0wmX6M+q7eEIESI+w84CsIsIq0otwvFG6/0AJWFU6K3FBsQJF9fE1ikuzhwYhgxJX+n+zWYNfI
iUfNPgQLWiN+jvl+msB6IudxT2stIdP5g/PXVIEXX4Zb0X2GgEx+HKfsRjjAetBBpl86wlYd0RD9
TSsV/w7+C9dbDvidRuRnQW524fT54jdmhmvAwnlIqAnXDzYMYioGY47jbsGwnXVrrGQs7bDTbKna
wd8BiUBjw8376rzZacNaM07qSZZaJ8pFi5mA+utTbbWrjqmYIuH1A3R98RuDCr/PbG49llt7bAjZ
sn/+0lGT2h6XUEvsRqtFECmh/IqeUWqLEQDfrFvpl7/0rhPLSGLvXQRTUhpk2bRLQ+dI/NfloLgd
d2U6P7GNW1VdSwqy9fL3/uMT7DIqr5AzfSH6ktDitkBylwNyycpJ6CY9uf1gduMxpMZnWGDFm0KX
ph7EeJmm9zM0mqkHAjbLXBV799E9AeuGuYSPzdNnS1d5rpDDFCS/C+LQZ6N8Jnt2519BDoEb/t3I
/cVXvjC2jQLs2g1te/OPWAJa12EeTvJmSzLhBejxjaCj1CnbJew3gyoAfbUjlHINwsqM6+1kGP73
Y2tOzNpM/j+/ZS/FCvy9cvUfelPZGVhHK38HBi/IZZghCVxJqtnNVfmxZmg9FMnsAuazDGWJQPg9
9OcaStR1tBMNO0ULV1KiBrFuqTVZIRZwULskhs60ArV8/FbW6IqUivP3Nm1zV+278rurk/ozQA7X
W9VLZiYsZc6OmpjouGe1LWcETm5Ldc//AKxFjomJ21uetyE0AIqM/CMy1a8YKrewvMhqnc2WQ3eS
uJRlaKu1EVhHUQU4lEX5WldmAVdFG0lRbzIhRtqC6TB6+8hBaZ5LKE3Def4fRI7lBGFkxyiXSYRd
Oh7wEmpflc8zC1gizKQRlvXmGbpXjwj7Qb1gJgTUV9pln/ZWLwm+/WV2A4syo0M3FgLwaunSu65f
uxWc1rrivpsqG+kvjWjX1Mh6xGLxL0ZDCSEUd4eJwa2M7RfH3e+DqCk6pYu/SRSYH5RuOZv6yjeX
dRY7lsKMjmU6dPNAHM0bXYAP3YjB8pb1gIG8ZbqA9hDgklq5E0tY0R3pU89MQAsxwE3oX0ipI/PL
rNY2dmsQ7CdoezApLlZXHpcjrVj64IEOeeAY87SQ/bnkbmHawektXnlKHl3GR2x2tpda/SIMKyu8
E06FLn7yWneZif68XMQdnyq78vqbDnQXwWJnjdfsvSEz1WuNJbX8ixTCkQsT2wB4nVeposrJCaEw
2FFCviXTUp0L0JaZaVtpC45RD5Nl/fRpST7uOtMEFxhnz6mysGKRs8NojwAsRxjqYACAo/WUo36N
aq8CcRb0/dqody78qFYa6JSvC+Q6k9Mt3JNUaYzcXF6vo6SdzLWf/LLrtFURTj+hDwI0xoUh4AJO
GCTg6N9DrWmZ5YdfGJnU5VtIJMF16jPw0koZBBwJWUeJsUH+BNmD0gR5Yga2Ut9V6HhKWDLYyGqu
UpYlCxrydxkZ1MNN9iqti63Ev6GcaFB8dJvKedmb2ToCdIjklQ2RAc9RZPwz0+GjyqzBRCjWfE+T
uhfB+8+hMFb9kZqcc3vIradLGJeTlEyT8a0L10PTMW66cM785eCvSJpbZ7ZXH83HmmOTkm6YUS0L
Ba0c4cSeKwh8MMWL+SAko4fWoyXgKkoCQ9MVEQM3i074R4UdZHoQ5rWb5Ey3ZvQt5+SeLgqWjuqK
8H2ciJh4ZDUN13nV3+32P38ApeYH+zmUtVsGqBRBfQIhGy26kqlIZxyLl/s+HOwtb534Nmwes+FY
fSFH0t+XR9Xq+/Ym3E4uPZPiwrc0/nZZwwSSfc44OOkE+4UbnhP67zYveWLTH01uPZbF3WDz7qfD
htkkPvutqPmYGdEjVICFbLfKYoRh16gaA8H+iNGs0zfVgZ7pi/SjtX86kzC4KY+dFinuYVMZ6Ppv
ng7kIKE7wxnX/2sCcqu9PjYSxSOkJIsFn12P9f6Sux3Zd7JMaeVXz6sISrSRXUN3TyOvHumsMoMV
j3ZWx4QC+YYL6Q71BPH0jSdY7jCSljt9gis016qOnAc563X6kZ9JdOhmB+r/7LMZbmgJUS32v+tT
A5KWg6QWeuqHj4EIJrv3JWs2TFYrQ5ziHpcv5OOJUhxnbAOEgS9pO28ZcSVCxuYFMYXscvXpGN+l
eSSQ50l6tFFuu+QKigasxT2VkIM5y5burIT7KKwKCBtkVREBMcPmA4ozLw5YY7m8ihy9VyFb4h9G
6BaLeMM8dG7m9YDaaiNaGWR11/wID2evW/BY7C8JltXwkijf2ThVLZ38CdH1o+2tfZyWyv3/rI1p
EorD985G/1GRU9QvfWfYahQIR0Y1d9SQgUUVEOtPZ6EmGVrxnC6uKH7hABJyVLG0XOJOYKs1co/+
4Lk/7tip8OqE55HohAJeLAcQSBVLDAIxKXoy/a1Ec6Q0MazL+rk7NnLQR/davyJwHdNs6NUqVFcK
kWON1171kNIi3mjAgd2flPMHhsY7FrfqC9zJPxdKj3YllYKCwX+s3ZCZdmDZutaCwXWb2iBeAQlZ
r11dplD1i2lwdKRKBlwhrf6JqIkdI+ipBHDGvXf9sKDygiOdS2emLvt42e8sRZtxdw4ETRy8AQ1Q
TAxv7W+Rgy2JFzhkMtQv2pTwAz+ZKpTeaCS2Sa4ZemcdsJQT1WKgfLB/9bDz9VAFG1VzKkFS7fjh
gm+k7AVB1OW4zyyjMQGZOL8a0Fcc3Vs6eBj54BVSXdqUXFSREL63bPE+hM7SdGMSjOemoHQYnXV9
7PVAS+iWCBORU9sCgW5yUN9vSCSWr+NlQDWnO8k6zJpnDBbLUgQVSjvyWkUR6yhhL/rM5z9lwlJd
WJsDZgyKQ0qRaytIfajPuTR073aEYNFjti+x8UWfqXshM5SOAwrRp+qoI789K6ol3J6A5d5PofA7
V6iX0ENi0FzEDKDHvrBerdXoIBuB9YkRDTX7otgnBo+EtMyoL3vcTDgsifINkYicpD/aFQE3V7WO
gSveR9YH+y/PWK77qK5Xx7y+yutV1GUkOo6RFVMc5KLlpa4YzzV1Q5iINEPNszdArPE4XJlx+hyR
ToqPz2zlA5QBROJqEswdNsvelJ2850xClsNsqLeutgppB9gw2fHApX8wyED93oAL+OwsZI9Aott7
JRCmn0kcZFJaiAkpc67ZPm/R9qMbETpQ7d8ivnkxpdPJwRrafPCpmx2jrRu0cnLi/30vz/BWGKRl
KlWH/bJLTR/zA8tbFlV2h9yAb+NourQ7dI4Lw6LdepwkfulrudsMBxfAFObyb0IC5LiKQdOqvNFD
FyUg1TO59LouepqnOFKarJBJze/8S2va7wmdfklbqIvkC2b0zM0C0IKreD2P8K17aw3hH2ZQ++o8
PgzklHYmnhkgz3/7OHifHtWDcpgssDXVMuai9f1RLiKBe8HFaW6ZJSL9noWOWnQgbOFiRKDv+Bhd
6yCraqzAs/HmGk/MooqYLe1+Kk9VNwRp2Qbfol9b6jv18PbS9m3VuwT+bvU3DFotTEyVEpMxUqiq
XyuS3mzb31jevE5Qb4+vYrVJpR4edXKfIhkYGAq9hZV0+Dex47sBg/wpXBXTYqPWdrEDu02+YYtG
lDmRap5VJy/6fcBEDalG9PAeHM3v5gFrnean7JdQWuv4oF8KidXkOBOJMpIF6yWn24yIrzuhOX+z
1kt0sPQSbAkaIO8MOqG4QidonLZy3rBdxSfPsn7zMDPm/GtQ48KqaI6mKdvE6TsMnPxr9Ef2INmV
T0dSZkmlJW4+4WQK3rVFVXCC1WCe4Dqv0WgId6c0l+08YUkmVOv5oSavg/bhNegOns+I6uQVdn0d
bpJ8+vU1hRSyIAoeTK+FBDXRwb1fvhmDUs9ogtw+H3/1I8VZdjNxkg2F6IquxvwijSxyhDIZK6vC
d9P64DqVP5/wuNzcRl1qgvh3RaC/E/lSB4Rwtck5xgkHY26W2jTX+O2Itn8geNgkb4Embf0OwMHa
+B+9Mxtnq0hDzCkYfZZ+3V1yh8xCoGE8ivI7Jp9159NlIqX8dNpm9ohN1PerT34e8Z0J1m3vQPc+
0uqnxDmmf+8MO5ln2/JVCmYCfRdEyl4VcWWnTi10sQrYNETw5N2tR+VOACPmIoZfSqQnxrCeILex
qSyDNO1FngFY1CidMBuzelJqonsxvGgLrMpiKDzwkrqdi5V+02BV8GzFRX3zBoj/MbiN+FBBW0rp
u6TqIZB4iMCyn1/O1cKBmTOT32iAOuU2toAocdmNi+zGfeuynbbu41kIgaktdnz4PLPiKhiX2109
fJIHqmknZbLtth7SeIX/HaW+MGodYM5xvUJ4bLZBJY/shBq2NzLhuqdv8saCiYfRc3U7LlwIMTbW
FfzSV063Do6uoaQUfDlCLT/lN4Gveyy8OTlSR5XkxxDiR7j/TF0xx9ALvwiyzhU+tYknHy62crPw
C/RWsJWKJxYCSjSJjiXkrsSieIxrH+2jt/rvo37fs6jtT2D1MDoh0+UgDW7I/LE2jaLYGN5I1wi6
DFxZdigVoH3Hj84cNmG8yeqLbChhIuzl0ZhvMiAMyqeydJOfvDV8NVVeEsBAY3qHA3LCEfV1MlIw
6akYd+So0b6er90aKMCNyqzq61FieiFQ58naSeP6Hm3Aeu4JV+XatOngKpTsT1o22oAWVtCjMbXO
/4nxLYaT9x3TzvupextWaQ+CI+x2krpGhKZ4Xo4hu8p936B+ivy1tiDutvLwzVHAkNogZn5wR+2O
J+pJaqlgt53hxaIfXUoA07esxxnIJHhwUyH3sEH/60VPyNqFFFBvmU43I5cDAIJX1ObN7h7aTkqh
YHWaFDunc/8lEwr6pz26y46dxaAPran+fAB1JglfyYvTAYs0hckCwrvhLk2ANwAg8lIRXDbe8Q+w
SjRM37kjYsl1474xm2wF1K8clfFIVCoKRRvCWMQT3Jhjar4l0PTpTn5nrXYz491nAfnFHAwtEI4i
8y/C+rBd5sS6pdrvP11ytSCflyrXjx/EoHozO3RTPgehifmsYvQpNQCvsHu4nR2wdaQHtlFmSiow
gpwNs9dqMqOMHYtkUqf1hJlrxT4f9HuxFDROVZ5PelQivKm74tyVZ9tn4k7LekeiYx4ZaCStQVDg
GNcpIO7MD60WW9mafh4ogRtNFgsVBRQOej6AMRy8R/2lGOOTOnrlpJQZJ/el7Ofq8vgqmWH5deWG
XViN08mlxoqPE6ahKMtw3Ee5DMbXDQha2yb76eSFddX6IEcIzNXI6m2RD5YZgu34qKmsV/F4JKBH
Olu4DylN8b7c4jFmfzco29OHHuTqkQa9nWgeiBbTqK5xUowxUaHqHb3G0zwigxlvCPlKajEraHwJ
Nsq4FYWMCCkRxLhBR0506ASnW66rFJLlOwlkjJHgy8LujOK+leijLn4HPAo4AwhfTXQzHzvYMTQX
xx8F+WZCXRtgGk9xiWrrwRu5UStV80vn6b0WjP6/nV3cKMm19y6ctj9tUlLWTXMis1NiGeQtyUtn
9mMIQJzLEKNgBPTkkC7Rz99gro3NAY8AMH6k6JinNNH1orou857a6vB2CwnRQxyy/e3OucNgudev
c2Mx2kZxU7Pa/gs8FmaLfC3NxSCYZL+7HzSFDIQ50ogimEPK7K7ZfEow4qGi76+gmpafxppXOrS0
kZM4la22uwwOZSypkPIB9rabxP0DhgQGrqUvPNl0MH5PcIPCGNnnF3DJ4o6MO3+ctAOOTaAx1P4P
PgQCeIJ+v/O8ug12Fzof+Set7u9NsJGbQT5wZDmRxYocRHKeUAs6UcTM62Q3GExlgF1hhiwRy38I
DizzcfgQX3jBvift8TNMcv+/ilDOWi9GZFbu0n0UDXQxU7XqDAVXoTlT+63d1X+w9iii7yYQiu/J
VtjzTYfx1UoDf3KWRolQjKE2D75yLqRYtPBHdA1L1mL54s3tJy/lPvGefFaDeMxM/Mu+j3+UNsZX
hZHyp95y8oKJHyO2UhqISF75dog8rAWNV+XkBFjhz72JB/KF3UtOuPCtKfXUqiqAj5MWKrv+5XU6
P4qDH11SBLHx4nPIV38YBkTxg58fJFnshG9TWsii0EX91P5ZtPEeRfQotsSXvwgz2fttRKEIqHMb
AqHs4Zjwf/CaEBF5CWyJBtU2n/WCISciLSXrDkHSNdzUrqMuS5vTO/UoIrr/2JKOKVIhhUSFC+eW
BxO+Vf64MbqHoierbyDJxez5bcNxQbwr5P8K/FNXVP2JJlmuP8fAouwMF/yIIeq2KN9c+e/sym8P
ZnpNnSDpS+METApSdOHf6+hbSBfeI4McLdgkAyEpnMoL6BIDAwBB02HPG0F/CWrRlHm5O86TCp9d
Q+TaEjRo1cJaLdEbb5OofhC5V1u9TOOAdDL+qjHBbY8I3kReKSKQe75lEGMwe+FZScScCf8h8lPt
r/pB60yZddLaMsRos11aiBY2chlzOO3qmHXxlZ2hAqObAK5QG3btL0jvAdPLUzJWPLcdL+ytY+5p
JbmoN7fk+PW+gxYBiGdtehXUiMwQY00M5S6NIsQShEN6y/gH6SQLWdadvWuYtQLMg/5tW634uZdU
sjQ/XJ/xDcTILhSXerp87+HzA3pUN8VNDsUrSDYCyiFldjKFLff8klWgu4jQMals1Wnez9bUzqzH
sidU011CfLPHjkUH42w90M2ojMzTgzRQE8plKViDIs9SCUGTzANTIY+j59TMoMSF6wftoWM4hkf6
fy1D1FBi7VHrHzkiMhxx5oAro7Nmz8WuC8e96i3AyhqPymzy+p9Y5CX37bjx2MpwKH4TxkyKtkKS
/JlH731jW2z8jIqnCfLt3pEaB2d2hv97JDbskBSIGr20vZruOllDB9xJZ1Pd5ghhwUekzM7RPpCV
DUX1sDs3HpkDAcgbzb3DH6Bm4Pqx8DiFO6SesqH9eKZJ4OZO6HkNEQVo1Pd7FPIzv0ZhrWzUlsv5
pxP0bL0Fi4eLQrosmcd246mXq03BItuIbxI3B3GOQXPUivWXKRtalYqffspSebXf7MgHOp9edXuq
D9gbtVKkpcZKesALdGT749hGhE0zaXBog2m8msbdwMylXmfNjfogTqkayDFk5/VHkvH8Ep8qYHVy
8jpadYxffHc7k/iE+IwgzzSjHtoMstWZMGcqKCI9kvgAWams6d9smR298NJZoVQzH1XS9T0NwBBo
05qINbPoctAe2CmUkstHSA0Ks8493Yv4GoKcxmyzupb1s2EsIzclivlLbXtbA1x1tp5vRs6rcE8j
0AYj6d8zFPoAzBwYyXNSgTnSg/s5TwffbXnrUX3ntC81XqCSdvROwKRgKNJtcwWiPB3nKVCK4GZC
+l04GgCsnGgUSJq0uNl0d+8WtwrKh9K6YZiZXbI9dHMJBc86ypf7qmmsJpL87WgeGiZGGAr81vIZ
qXHnx6pOE45kuA15zz43SrESBCn+m2WrgMNxhNkyoWDkP4ernk4JPY4t83OruPVwZLQk55Ox9aoV
EVQfmAH9Y/N4+G06tov0ea/sdRUUlTqLmwdlyHBpLjtyFjJZ6eSHerG/ZL6ZSnR6D+MZeangGTvF
i6vprGGejqgH0P1w9tuuOYRCOVpgPRNX5c4tyUkC6xkGmi4t1mWxZIm0vIrQ53W6hrVvZPMn2SH8
6c/c2fjdJtGfhulmw/EOhIBYgtpj+vrV2y0RuwX0eH5bdM/M2T+nzkhvBfDy6aZZtPMtFJMqywlZ
T7u6mv+PWSowEQbpOePknmePggjbP1LXykXMx2iWxVg0ogA2oFr1VH/GJS0ew1AoP/2EWVPz8eV4
aA/kpGzbdNCBD6zBf4r2mYPEHykM+xz/9GjtN9o3uDqI+QHqogPos1wu7hDhO/TBBTHR4Qj9KHzs
Cvc3iNEa+ce0k+XWpbhB+fOY0rxGo6rNEqx1kIBnBDU6t0VcO25BsY51rVkKI+my/QpY6l5TRO/t
P0wfPhtf1xwME70VFwdUkWcM+ilcbHxqFRyIaD5Uuo8HNnROE4r+8oi4Gtua2/o+mvOSuXIM1PbX
K/mpchJP39B8iN3MNy1lMfynjjpu91B0pS/Z1G1NbAQdLvaADEMT6nBgqOIetkT3eQZEMhPuFTXR
zvx/gmnpcsp/OTliSP+kh4XL2judVj1/dZUmkvkdU8zzHBAlFex8IigKT9noeePVhQfTwxmzqFzB
FBMy9R54HbSKvMOoriAMe9ZBYE6wcj+xcrPaNLbos7RBi7k4DepkMeSEFwhgQXmS5d5kejEF7Dw7
JG1GIH6BWBhLkLy6rko8h7Y9J9qklJw0qpWBfz8OspKPE2hcfWceSso/DdhSq8zStEIY4tpGJ0FD
M9F15mxGFTvs9AFY0eznjExD7stTwCJQ6m/2bNmD1KErzBVK7VyQYyoxcFTYiyHtgEKmM+nc0LLM
g/RyJ0vB1s/lrVVl/2kPf/bEt/BbSLjUcEQqIMTDfpyyO065fC5B5/d7goXSlqNfJnc5fULW7hfI
iHnkQ/veR0febwDp7rZRcOiSAt2v9ly/AUdT2/4xg3coYL2mJEX+eaj7P1EIAML5MGFdRJf9NNML
VyM3bDsCHqbBr03zhVOSTuNfxCNuAOEMiAbuRTY0uySxm/vB7yBS/cTNKTCaP2tM2Oc3ZaFizRpI
WNIjyFdITW8G83aXL0gW/gWyVhSO6mk7i9ERY2MDd4kjXdsQYZiia2TWLfAbi5zJ3bLlWWIer5S2
1wR4WiaTyYIb4MjLgeyMtKoXliN3ase6NR+aAmweuMSfsLzv7ZDDCb03uoHNAazVG1Dd6I4ea/Bh
M40rn0EKMvWWxnUF73PYxdGKQs3U6jPxOxYARV04y2gWsO+uOiLtAi0Dn8gVp73iaTm9axxRL0p/
coekCvAFzjUI7nhMXfvE0UpxC3YQf8Uq9ShzVCpH3trYntIyCViYMEKUEQpcEuATgHkivzMliKZE
TlFfWwAmfl8GDDK5f8vJFmCO0YprZrhI04uWRkT7I5ZPFVVk3YeKJ3l9iAZ282VdlB12PIrMnPfk
VL1WT7pGcC1cnx1ib70Cz0QK5BNWxO3f+JmjyzxDj7EDQoFQ1degcj7hdR2laZcuWgrjugBgMRmW
jZQOEC/rH26g3WvN27UDo7NO+6bTxCM52swDJGWW1JMaOQ3HlXqapq6uxol7kzavddNn3neK7ViM
97Ra+neDcFBH2Hoc2ygXcg9MQMUDaOmJEmoMLD0G9i/JfV7thqF//7Vb1xR0caKf4jZqkKlfaZ9v
GAA54D0OngJ3Rk9zFLSEUlzsWehHImAJTqWWtjZXXoyQKKu8M7vzPb/zuIOd5EXBD6xAQBHpmLMF
ZSW4ebl4IYZOpCGr21siaaZpW1gMP4burxrIxPnLoBItV85oGAjeA0Vfqev1lPv6b/FSvY3iZAq4
RdFTjANeADZRU8V++1AEHFWZx0BAT79xnC1cMhYy1ktqOhI6DtlAg2MXvpaFqQM7Ji25Y3r0vU8+
qDdTZcHftcd7KgxAVQlLd9F/Z5L85crRR695tXApd8sK3Yd3zd2ZcHiNnbJE2aIepUGfldUj3Yy6
rz/y7E5CEwUOkWK5IquUpBspjfabC39AN2+cp3J6JY0NgFBsnm+gM+PDRQHx5b3+f3EFlySxZrht
bACZvKr0b0X7hI9t6Ql+I08CzRw0iv5nT4Ab+iFQ7nMumIOmnLPUpi9ggFIZedj4yukhdmhpH+6r
mg/BFTiufoe8U520ASpq5gTLOlu7681qC2Psj6JDfWZYykTEQ6UR2ltXFl1tnSvxuw26QxnwoORO
PK8JFESj7N7xdJe1dSgqBX8mPM7M8U97qvnTJ+qPivN9HzOKytnAOetafhxbR4f7gCEnc5zZIXXD
DsoYUmaG3T3qSTB2TVV0dDp++jmOz8qQ+agicyBABZUHgiSkiUPiJQoscR2jgoPVibwpGHX/Niqr
7kVhqRUIfRdXEOMrWms2ObgaqPukJRfYMkc9fbjb7WgjsC8WVv5BH/d99xHCFr/6S7BtziY2ebXa
r2nu8Gyuij1Ae9xHsc61TejuLcHEUa6fsk04vbKhDHfM+8Y7yP2vQ1nfFczktHnhs+oG+VjewkW3
skqRMDNrSvRYCVtljYh0ZzgEWi0t5cC1N3Umjg6xwawBzGekEQTkIm+uD1+y6R6YiL8fXW+JnV0Q
/mhWFsQcnE7zV5rYRcfdEmzwtad59Tj7H2cOhnFb1D9zmL9CKuXLPhBLDJg2aHX0YNljXCojJzgl
KOyHlRkTUkDvjs5KvPRFD70k90vftN9aBsc34Mrf1dGIapijqWKAr7peJ9QB8Y8LCs7I+rAgFJdU
Ujk1leD511zX8mBxynZZ7+V+jj/ODYpUl6RC7pPOGVi5Q1VOxj1t/Y1zJxu+iX6cGPmjMYudS244
t+YAH5V6nSJFli+25k2Z99VZre2OLRitvZ2Z/yjEB01Ss2ZkkhzAVDIpQGkFUKxZ3M9MJfNrdRMF
l0W1X0cX1RRsoLTeQvfxTUeYbukvcpCFwhRfd9SaWpHFGiP3qa6KpngtBPR5Qtyn4+QsXNaMTWm3
vfaCgyPQk4g5E4cgEuiBnLCZ+Vzr1kaj8Jz14LQty+jKLM1SwZ4Wxad4XLzD/1dKjPqHd3zYd4Xz
FyIgRoDqMFaPlacfd+L1tYyeHZoyJE5Ek3NtUGima2TfJHxh1Hj2AieEefuZtgH406yrWR78E9HD
6WWsGw3J8oGTeBDNaGCFVlJLMNFWBGpXV+N3YH+gpMkaJXLFfVxydAOgZvxKNPnOwhLb9TI4Cp1f
KI+kPLMiTYFStpNdKsYSVcaXniBknnlOnWIDL1i/FAZhfF9AlwuX9gPY++Z2QOltjiRi3pdsX8e9
SijBzPlLVinvZErxVUdzCoW4q0gUWtCVPO/lnYgdhuOp3u+x0lAc2o6CJ3Qq60K0v2IHjcgMMUsg
7URSHfvmr9zdJZFc+3gSPOYWM6eRgj3QN7X1LEj9/SmtaTpF5VqnFQUpu3vUsPdOYK619PyEj4V/
iiUa/JVvdJQ52N6LAMMDHKaRXAtjim7RVdEn1hI+CrH99t3CZgSem7vA2TOxeKZLZ1z4nTmGmJbY
WKdL7USaY6ksJdcw5SZFsAKAhmMBi1XMGCRjW6MC3z+Nsvt+/vEH6W27WLlb+a1oKprB08AfO8VV
E4V9Q3Aczx7n/rqvY1znUj24uEUcqz8m41EzABiyL7yYeikQA+iJQNTndu86MRV0kYk3WFgZGcK6
vLQOlkeCdjn7buK3CsTtuSPQIL/jXBZFoqr8GwBdNG5tWJRXOfbk+VcZMNYz6VYWBXg2OZXT/9wD
LVLgNph/Y02uwVXYs/5goGqMumEM8Z/OP1Kh3SYRcHHk8Uw4bMC+2W6S0jxRioffQgrWZErfch8u
ZYMl3vk7WQyW4M9ldvExMZN8otYflNtXCmEtFNJ61fILIKBqfQd33tKWbeCiIMFlnQSDJ+Np6zQp
BzVszYOhyWH2FZhrV2RXD+UYWLsvjnZWUdXOKcu5W1hTiLxVu2PDAlaQ0DD9MW3v75olBs2XrayI
Q9He3foCQHOhIaySlqipeBzvW58ca+cakG43f25RAan4n7ADc9abzkbJBAWIfrdJnROWMn3ZRJ0G
L+jp2ooEUV+aMZY/DeO8kwIE/+sJLFr06uGcwCi1+Lsapn/fpskILtX4j9GYD5emCUWEqmUIquEo
ojhYK5IqbDZrGWYOvDSw0uLeWattUKvQKlHe7NeksQw3xr2eB2YaVrKgPDwK7jwOCfx8XpMpJEVj
Nn5vL2vRApo/4fbBPbJGT4GLKgSDaYKCjTfRF2rhbynSqk2J9cysyyZVtoNNsxfgWu6lI279KcUc
9TsPVu+ox46vDLlQfloVR84fpqVHREAsnf3WXNNROM+glKXrDLLq3yN9dldCo5QkqDF0Vm2ce3KJ
2FMsixKyDs6APhBfIsO4E3Ks4EnwbKQaumSt6sYDRzh9lwKXnXbi9AxTt0tXTLXK4oCXZ4ysIhsC
Gt1+9a7XAPPLyT2V4lJD3GXlammtVJ/XE0AsSjwoWRequ31ejgEn6cEPYUlPERSxjhvbSl4FA2AU
qhNvr1vYhsqhT8Lds5/mfpLT3+GNsgk1/BkmmL0ZQADHpPjE0NauAZHpM6WCakMBntbGaKDcSACr
rpdx/7ZIDMvBgiPlAJcc9tGxq1YzYilmctkE50Zu4kgMK1pNC53jCwLT511OGRWfGfm7vx5h1s6C
E3EKzYAiYwKbw6NOwtTnMBxB2tHSuu1QaqM+qpaUUpfuHvHG8VlrWiXmv1lgp+SbBUjPHoI92v9L
krEfe+ux+e93OVWXH9pJ1jqiLSv47q9ZyGcP686806wOq81tJJYsxg58wZsDYP5IobIvBW7Jl5xd
ZR6DB8NEvEgZ2eqlgAbilqYt+sMBJNMGZlNV/Q1IjvYZqDhW9OrchE3Txp8YG0JYPd/XDRakWmKc
USm5A0kowE/RPmgLMLevFM1Po52huMwOcfhSHFka+VdwtOgsPAf7pRf3eTGmVxBYr4/PFN+Y/xf7
Y+X5+LvK+SFamAGxVPE5g4AXLdZMrLQiI29q7YtimnmoXQNDI+vmA/Zre9ZcINhgoii0tmgUsPiO
367h3OjEPq0+cGvsS6qwi7EJ26942OMg8McncIqQG6RfDstdU1w0L5obeKF8OjskuDFOEpKdl8eg
kpK7a8L+AB4cY0y1j5YJl60ZZ0accsIKB9auLeArPlb4gAcuqMC17KHqV81Vc4fOoMBdj/1iJinD
s4wA/DhkwRqrKkxlJkXwy0uZqVxXl5QQRFvLuBHIH3Lsfh2QTK/T5w1PjjGoLys9xQY5Lcfqk0Hc
s1n8fy6LIqKcxFngnWbw/2u8N3LQT7ednie6EZa6Em4wKC8uYTbrg1Y1KDiRGzz6RRf8H2l4SbvK
Dkuycrvn9jd+UvssaMEhCLGtj6PNgd+W5xnVGg9SKsD8AbBHVRFLTV2v7JPLOXElFCMWE5fXgJ5P
iMZWDIzaVybrkvO1cCYC32PBAc/GL2EYVDelIYFshzz6ERrCVJjBoWkP8mwIL2iEXDazKLyB6F72
U/uwSnEVTAMs3Zou/DheoqoXAa9gH+CZ5klLDyuCgD+kmqaQiSW1vxGv2wnS6H5ByPQ6e7+NQrq3
St0SzpjIVv7DkH+z6dY1qLLDHs3vh1om2GaFdRYlbr6sDXRlx142G8V+YRBTFstvmp96mtYzjQKe
PIOcsd2tN3v1gmI0Rzl2gwx29OrwpeYPpN4keV3SGbHJbex19duHp6gU0wuPsHQ91IUAf4aG6hw0
vAbSdmBZ5QkQJVaWS0Bp8lCoo71Iu1ukkO0hUBo5W90LdQjXx7HUzk9MdJmiMojaytZwgj1WGYtk
b6C6MUIerU8RU8dt5HeWPgXGdCIcnf448Vqp8DDbR5QKhARZRefG0ebnaKUpOOZhTmhfUQmhJUgl
4x+TFASMvv/sL15VD8w3SN7rWOW+a91MQwZFu45wOpXITBmIYrY5teUnW2eaz+qTz0Mqy2HeHOWy
B4A0cr1RhF0ScVTHrMXguqApuoQ/04uCnK/Q7ACkEUtaUuic+aNtTTgQIYRgSAYxAN2RpZSFbfvg
V23c7SE6S8VX4wx78tkuTtRDCRqaUn11IKmVrtWLuJeAAtqu44oG9wedpf4VlhKTUqEWE98tHXXF
5yqjZ5v9yhXU2C5WUGFOcUrl1e4nrWby5a1WjLfhu7DPucCLUNV7a8iA7ZrPVivZa5MzYSkf7bOW
ieNwO2MlpjvRyoVpA+V8SE2pZ8L0v+kPcCGqXezkFG6kXwD1VDZKUZyGMYUwWU+eFpypqprYZAo/
+tiCcnyBD1twWHQYrOV8hjOJIo2TuIxU7q6i0Iw8MWR5Wwg2iH3CIkAyft+a9WEqJvag2gDLYMnE
11iOGOEJnQAhKuaNq/1aA+aYcaMBp11BY1ebc7ARUoUyUarHEstg/CfoQd8fvPZ9uCEbCZwnCnrs
qL48NNMpBbKV6Ba3Fp7E6aGRujrsssU2H3cXKOor6YghjxerZoSpjxAh2RE6DWnJuSSyu3y+nTfy
7jpVjaOvCqASZNBUh5K76oIzHQvcMtTnclOj4Al4uNXRdKg6IhgnI07k0x66B8Pn3AwYF55fk17S
YhVtX/YLUHLdel4LgQRl+IFiTnxe6FHyHK5ZMKfMZxTYWFoLX2RoZY+K8i3qKooPxRl1h3VgTy8d
hOWbk8A9y3fdnByQ7M7SAoQ/FdfgNVrLXiISnEa7r1R4E8jHjggQ8vdASCHHS/FANV+yWfV1Wyu+
GOYC++EtSieXAw8i0uz/cieZC804tb3JrLgVQLH4wTId0SauHHm7C5/9S7wEMRcPlnotE6FcIxgX
ngnJgGyjXNec2kE+41Jr9JlXBx0jbWQEqvrER22EsS8VN+T6yXMtQySvSZJTnezcQOYgohcIGVpj
88n4l4T99/kLEXQXVp+YptfagKgpNVq2W4jWtOdierrxY2kXj2lidU50knk6Zbd17AZcNjGGibr3
e+uukDhp43sh0CdnQoGROUaVSjly4fHlX6EtyrYhyk4mnH6bsY7wQxzfctcbkYYzFp8C3vZi4Jw7
S/b1q6seSXWAfw4V1tftH+2EzD7zV4vFTx2RBqYc3OiU1Xe+dZWAGBJkC7Ypc5Ol644QTnWSbvf0
yVBFHQhFmDPpBTNzVcpjCF6SAsEkVgxQIxW0X4vP/X0gEgLJ02WAkQG6ohYi4ZsiPeWj3xvmgNmr
bF/A2jkhaG9ZGhr5hNtshPoOuTRWefdNQvV1GEs0gIjZOzbCVNMQtyth7nywQseV/UJeCY4F37f1
aZJKM6SA7aT5V7ofUt1SFfSKajGcfQzJTlNDugT4wYb0pe6wGrKdO8JjLHmkrE5sjyMBxVnZckul
pJObw9aCQMAEGfB1mf6v0UbHo3IanZqwqcsNUtdXGRkIxSpwW3+va4thQkyJuIqAC49Z+YQzh8xz
iaNQ4kfStyM+jV+ysMzdr54X8yuN9N+U0h2TIotryUUMaK4BP2xV0mhSiDmr+MUSJDYLvRuTEsBI
W/TiT2OM+nd22Fgv8gIx3LATQ8NcNjOpX4qo7lC7dx2pL6+D6ZVGuYxVm8XlzEkyaZYJo0NVOPNu
LRYrifNMZiG43XtcCzQKrUFzeV/Imf0vkrCe628+iHU4DDx472WjKxy3MmqFq27p7LKEwNfGtiwY
uKkk7KMh8RnpmoWxN5v74qHydqKBH/TnYNlHMKA4GUQDLTEQaNPtSuJqVh9bnEXsQOyV1+DokhJg
KJWvYVi9SwodMwGgXZUgnSRr0ohsNQsGhnXQbdozqGHBchZ5fkfmz+B4tHukO8BpIn6vrSx2+Nx4
EFk6496sAtdtoEAsQ7owVRhlw7L7P/YOHwaaUiPQmFVC4F6uitL/scc2dnfBf1ticuTsP5rb9cxd
AgYqMkmpjkfxJB/sgrgPN1DT3E7Op9N4zqaq7i9gpB6EkvxqCTluC3n7+FwfmrBOlfYx2JmyN/18
4Ucc0SilRgLUP8aROYDW586BmzKApJLFajL+36FB1NCQcv9YCYXvLT9+6+TujNwX5+zRsyct4G4s
XK7/piHcXzeO2XvgcW2p30M4B54sB1Gl4udn1fpeh3PMhNoB1vsEmnnp3y/iKr/ggMK5rlJxIavf
Vmege9wy6gN89QR5J6xcG4/v9yfZJNKYBGZSFA1QrHBrAGph7arWgOThvukbAvj7gEAptMA43eAD
ET1GGhi4P1G6LsanADnckryG+T12gH0BPLKOIOtLXuFU5CWQjWHp8flhpDc2nF2h1U5oQ9J5e6tE
em/KpQhNPHmBdvzsxB0+ZykuFLzAYqEe6/S5/f7DkW+/BFWjyi7Hbk/HLGC5CE2dZ6NK5sWIz3hR
PUuEl1AQ+16Yur+EaOHLmcd4maoS9yAwR8DJ7KQB1+S72ABvVQEBcZsMHBVewy6gZ1zzbab1FTEN
WgErAmiuspDgzS+4OmjiVbF6kU+QGPVtJvpqpDEnjjEdXXZGg4BCHca33GIHkOj/7c8bIbhNcN4q
JXmXSTCbeFlaL4Q5BrMuYxGBi1Wg/IGeTozN+sUN7vvWpP14EghUo4IZvj/Sz/901ZY2ZQJmoRhc
Umpe6UJBjAOaJVlBnLYNJ14b5EfYHXGvThVYUtMAw9E3JTn1l/j/1uAfn0JTrhDVWLaYVG6gW8GI
5pxcChkiXUbzDn8aaGy7HHI5JxI6pBkPiaa29WnQiCZou3z6pN7/BDhitV4HFydH69MP8IbRAXSF
suVt+vUnyKJMedNjW49VgQ3QzdfGuUaAuTvPnrS7X5nR11DxSBfmri1qXjME7GKsL6xlO/yW5LT1
DqTd706Hn9X35eaVBK33RT/Y1YrtAbNzm+cE82ypxqdoZu3z9MzEGS6FeWYqTOUnt8oc86Cm8Hf8
q0VgQzv4zxV4HdCmTrIds9Y9t7Cgc4k9mcF+M5g3bTfFu7qo7jlaE6e5TKXTrtOgt6bLy+KHqivP
2vqieBHCDyd5/O23XhD+cwDcZMpB+Lf0uahkwVpJkkAxXkOVbwNr77vhudkxSe3QUSECzSPTd+Fz
q6NZakby0mwdBgnZJtH3xinNangNUHxH00+v8ReNhVS7PtmglRBPWyz0xS0vwsYHCcvR/PiQmzG7
t7ao4TJ6uD5j9x/hbNrcVMsJnI7pNY8px0k4hvSkWhfqA4x+xmkr4lTxOS0cxEh32pE4n08py5YS
JScWYSlql284GWBETSMCiPc2Ojm6ZSG03JHH/mpbt6i0BG9Y5hGgpakI0q7ohk5dFXX5M2A4AVGo
bkVy6kKsqSIZ2drdEXH/1ASSrOXyvWIx9eq4bFnZVgaLFNG9rcNLAQUpCdrRP6D1U+bXXiBvW7ka
wqRxZZiWf0CB7CLERkPeEOOY5PeqKarH9WCcsPM+XbkAW6czxRK4sgfRADm3Y8d8cSw3AWopYPuC
ForwWjr6NOMxkwube9uBjA8salIfgJwTU+9xP76nfCKjDOanjWFw8vwC3aVZOxMZJpPsjYr6M68H
ab0qfM4hyRxD96bz0hO+k+9T4Kx6lpZa6CchXIRYh94HRcTPFDc8dcBS7zUMOABXHSYMJNhgQnIl
WK5k771J5kWW4WjtA1gMQyNdQDfZi/MhEqFO6SSmZUNB9y47OoAJ5DfAnewYlMEjrdkOFaCRNMcF
BasuMvM2k7LSCkncW4c2SXL4AdHnqAXx09WZ/urGkhgJNp6oB1EhTQkY0Iff8HCMzAm1yluMJ1gc
2N2gPsXo/i4VpfGcI9SuhhnJr2EzPiX65NZHplfXZPbwMAZzshaSkhUEOOOMcS9avg/NnNk8Ecf7
HBYqCgbWbE3HPvE+Ptc/9iB+7AuwdL1D527F/YkmZ89qxdPT0XwPlCI6xK4iXmaut/lu2FsW7irU
Wmf8amkbFk3Bjmoy1fhoC0e+EQpcJTsYdDJYMlGArVdPHCDDQnXw0o1nizErx0w3aalRG293/Jiq
LU739YBefpkMkY+kP85sDX5G7K/3MJfo48Ovvbihn/GQq4DB57wdE4tsC2Fnxo0GdBFR1pd1B6PA
ZOF4q3QzFUvbBdCTGEtdCuTicrwYR/ACHLPB+ZbdQp3SsE8QG//Usgy0+vpcVfep7il8DOtJnheb
AeOBJEdcGuqb2d5s6uE0VFe4B4Rg/ebwWaJHARMAkKtSwn910LrLnbC3x/ZlbE7PDHTsuP+wPzvR
5Z8Jha6QMdqAAiiMJ6jXWqvLPVwoRnIwIWHAde+x0a2i9w1jbKok8gCC+VU7aWP9T+N6jE9UmSeu
al94hrLysUa6SplM3z5P6j14k6o3ICFswKVFt39VbuevQTaBPnHoc3Sk5W1hcv8hYeNnmqmILy2q
xZ6uhxwjPEnlG8NVwGVvK+sLylDAzZTQe6k5XzgKS9c8cPWWZZt2w+nCGvVVs6TlNjd4TxIv6rSP
RriCUsqkNyJDCrzG+jhFqmCxPdNUGknhoMTF6Hap5ZQwkr/mbPgrPLB67cxJLLO8rnLVOBwkYr4Q
2SnBBLWF6QsrgsVb7/A9TAV2apHM7LbqoVKM118AASfWzYQdAtkLvynJyqazWnZVoKwBhxlIBqAg
nJQetuhrN3TgJ06DHUTts7NReavFuZHOWMljL6fyOgw3iNyaQgkC+VsuDXLlNPIvWyLISSEbC3ky
pBdomlgg9Z+sClz0GumEDoa8rLTmWqSP6uV/sMwQ2qwG4WiUxqx7FHIweyXA1Yybn0mUBcS5yRtB
gsVCyxL6DrWCV+oxRTof18sm9h/4aBWviLeDkTIbc5tgRD2UmcMJ9W5GL5KOudVfClJbcAVmf9A6
XLBKGzPH8sIP1ihQ4DDc05o066vgQ0vkQcsb8RgKHXnGoCfdf4EUXH2oTib4QAhLJ4KtH/q+wgGN
9ZgRWzky/fptQAy91cspys2SfetHq7+ZOSWllcCcPpL1lQafdzSbIh7N1wZgjDC+GCjX4ZYL2SmE
3uptH4OyXQvmCOsH0HThJvn7z2U/7jX+LqI/U47NhxGaVP6pP/3aGC4J9rNQ7qnphKVOOs7Mjbz1
EWKG5XOEdCA+o0XUjUxnER9WZyjCd84+2BnhtdmMW1aNXHt2+CHeTQqxhJZG8tmQlGRGzZnEp3aj
O05AIYrTYyzMNmPUenvV5sTCwJwgXtXU7VpgNigIwBhtNgyjxo+gZEWcrDWiakMjOvLkMvH2ko3n
aVlT+vaMohk7byMEcFZOlZDn9ShgGn9RDK6tQHyL81mVCwoWb7ofPRqwI0Mw0p2nArRuzv+kGYUi
hrI4Lb1txeP0DXnGCLWdRrCVAbIWTIL+hv3qeikRqNYu+0TaBJDGYqcgWb2Zmyx4bz3A2clnDWAS
vl8hufpP4kASij3Vbnxx/PUEojqAs0iEOXmVfN+FAO0+1fW5WgNhgQDv4yhWLL15d5gOToauqjGw
ZkJwD5su2YiWEZmNWwe4GSSQw5j3s52ib+lXFd94slszPBJSko4ozLbYynl9k7McjmXkBhSzW8Ov
keJa9py1Dt8W1I0r435IZ4LpTGYuLzymxh82aOs5Lo8hN+ZxqOJHmdmIndgz3jVrZ5NfwYlifvlh
rYAc4zwv43KUsNp7WdCwIoIciWqmW9bhMzwQcf1Q0aUTbqhD1bJIJ1n0QtkNfts8JNsC5zxOWGgg
dPSK2F9t7MSoCI2BXYfIvLvqeoDSHo7rNKARE80A/XphwGX8C+TKiPMZOX+6EOxpbNQtPR1zS4nX
t7FAMSm39O4UDTah7rzf1UhAypsaG64dcHFp7GuopUryrH/0EvXGIKkq492gWrhcFs58we0gBh1h
u87wop+j4mlTvAv1DZQYzK3DCu+BIxG0xnutN0b7Blw1YQst2o9KLGE1Z9Zx7UtGjqMnqLol9TZd
Ynu+rkpBiWy3P43BOz1q2OvX5q3hAzk8Nqd4uoXyrtsWkh5EYYJKFl6NkrwRh2MaTKtlymjT+uy0
CAUCaTSvQ+iE0gbXrlFXMNEPehDlXihJ8RsJk5bDcFOapJA2rk6BcbJJTYd9CYIoE4ZxdTXcQ4ON
n/R0qKJ3xihTH6cfnXrFC4Cifg/ySl2kt9qM65ZK+IBLdgdUSHnJDF62rtDhoSnl+Mo/eNx91V9Q
K0l9CU0p91DgL3oytY+inUNS8tN8U5yHQEhHgUeNvAibmIQbpAiLHsyNdeLLdHgc/qLv8xGZtqnT
kfgTddYq/d8yRyq+Nx/ezHzD6kC3vN7MsxscVCCDEiw3BSxjfCYE+WZ17KA478n1lN9sowZN2E4f
pFvQ+EqdiT/VwopJxMT8869WoBQtkqiVQea0zAWQlHBLZcUr0aW9OJgOOfJJxn1l6njzBE4s+p3L
mZVlOynkxmBR7mvi6AsXEPlGUrW6b3u4N8RLlZCGuSzV59wf65mrpWbKtjs9eREBdzXsHCYY8d9y
/DQskOI7zlYGB6MP9BDbDM9nU0tBBqwnl6MhpZE7PV+R6+qEUj99DIt90rZxywcQK/c12fhcc5pK
HA8LBKcdNybKpOpdiOoj/05Xw2FvNIDgn6MZKEhzVsK/2EfxBmeJ8lEGAt3WKNwt85qUMh5dhV28
oTdD4TtJChj8ryHNranzETo8Cv8w6Khv563bAR4SH5KsphpHmZsccsPNNOYNVpIsWTD8nDzatt7r
/sHOQKfCJz+uU8ycV3mElOmOjt//l7oVoiA8ZB7JFCi2C7iztyJoi5iQ6hTMJZY/dq1pypztTm2r
F+uVSK3HOkoIQ6wVpL+GeyJ9i43DlqaTwiho0TKnzjYPxuFOTFZu3Rub/S0V9s6iGGTbLG+qiroG
PymzJm7DLTfT0ZeBBiPhSDimaF7Lco0a3l3cx196druMIDOu/f9PU8RZQntXz+FiewV2YFWYNMuh
seZWXjKWhwDGsPAO0O+v3InCGQp03pUI+ieBDn/4eafTthBjTVnlqlSVDGGT9LBYln68yPENjWiy
PF5Rt3A4JonFNX0O1p9DuGGmAHfAX9qUYEpfiiWMnEMHjBB3uhutMygS1jwH2bIV9L4NcfTyTC+I
+PIeaJdjDCyOuHGL6rrAMe2OBfpU3KK+ODqzlS7nRZe7VVyja5Oq+RzV+V3qzzDcscQE7gx4tHlf
y1tDEGVCgfQbi29KHNR1np9JYp7+6mipUB8C7k4VZlUG+owutLFiQxlGsmt/H5rjQ8F/kpUtZsNB
VbFhqWsvqNXx/qF3wdj3wBYtiIHysLA+jAmg4JG4ufYDOlnTgnIcAFhurB7XDt4gJv7YMTbeWkGz
4qG4b/ZN/id4ASXHOPUf+NF3yA+/tUzRU13w6QidOTdyLpbM/93ZhxooSXnPKR8OF1QPLVPYjYXz
aXZEqg5vu8Y5q7iA10TPZktHm4OV8817M2sJhWrTeeU3zhZbFMWFUO+locKG4d8O/3MceSNw9Nfg
iVNRd+w84RCjxP6SX8dwfYTWATvvs2G6dB90PcSiB3QeJ2g5P/fUUMzPLjqx2+lVMtTLx6MV4/re
e9sZFEXGlURbzA1r/ns5K4TBVfb9hZBffP6zbNQqxFvdhzkhWc3992Ce7Y3BWdr3Ifw9ErolH4cI
Q1liSwtMWm9Lm6Q/fU2KpfY3NJoAkd8HmpLGBlhZ6SjtE6flEcHrToyZSXSHv3aio63/hnDGWZ2L
fol37yol1O5OoIoQarvW5/eCtkWSShmyY8TL6x5vHcJxobORMtBjj5IR1+hpLdK+9/yuJqbTCsaK
AgMvTaU1pbIFkdqumjFHK2xTd8ALkgXRHpe6DrFBIDZ82OHLfK/4I1tfzAjGHTvObBUyhvXiTxuZ
KZtuezqki+oxCb62VMR6WgULHvt7L/G8qrnKarbQXm8B/2WTa5WHqKYgLxuvrr4cCoXs+hiZHlU0
tgy4M8Sjr84tUZuj3COowq6OAVHLL9rC5Jjsn+TA0nkXsNG5bsFPtI4e9l92dDInaWy8Xef1C/cb
mH5NsLbC+Gzd1gKB89Wl3SScw/nR+HAhXMDerqc3PnJqoujUILYn7+ARRej7WUe4laxxU96+8xRg
fEXn/eIs0vfJiLvsClT4yssrjA3FywQ1K3vVPdN7TyBd5ePBKHBuP2yOM+ybbmP5FId3kWOY2oy7
pntoGvZExKreTtN1wjB/sB0uBrX38TydY3aKZBmndJP6w3xao7HTb0WcZE5O+NKy2WD9SP3via4P
kJIKkW1Fc6hLM1GmhFk1Rg8b3QvehMali8g4pdBJiYUM4C74ywTZISQr0ypwDxICYfJrC3NeU7kL
H8qdjL0gjj4ypiu/IiqpDAApETaGi/3kWr47WiTWqLq7dGMrVgkkLZshML0hBUAFkY8FyHcDDK3L
Nj0RpWOcDuD/IWWKrV6wjXRfRxvvIK2W/iTBbNfloCW1XepK29kWzrXJxmyb0xj8NU+ZWtwSn3sT
kKdqKT8eL0iQlI11BwTOhZuf82xDtBwpcNeXfQ0wT14l3SVLO/opggV6JLZN3DPhpKnX/eAGge0R
Gg4UNhEmz31G1bhP3eo9T5e5k8CtebPWJPaHLFGs12+qm/3s0APMXTWCRuURB7lS89THfNBS+PZ9
rLLSFL6ca5odDvkAxhphUuFoxUJeR2EqSJLeESxY/QisPUGJo9ifeQPh3Cx/tESzBjpbxpMqsfIy
VcDJJ88+/kx7fYeZ5uVcHJPiWfcGqWdDJjb6zNPOCTjQ5Dm4i2G6DHLprtSo+Mh2t+NLhd4ZYJIW
7dqNAfvi5NQGVp0ak3uG/Yv4RBRwxh6Gc0i9S88hF+gC41wxP3CWGZAFbt52+e2FipvVeoMF4tEa
IAnJORkjAlrZB1d/d8BJuJNb2bjXXtb1gFcNF0QL/CSvo+H6h47SxMDCBqi61X8JM0pz2e4Jd4wN
tuMa63/Ca/5XS8zrC86I07v9WmAlwkOJwHuidPFfNi26saWs9EhHiHX1JIfeNYwbK8uH2EMuIuTQ
8AGZeKk01N/9DMsslR/NXe2cDUL+Gsal/sGqArMtMKMilRsK2R7dS6NXShYtpmkXOFLz3P5w2QH2
MYT6bZzkjUiYE6faNGuawlvt7C0E6YtPde7lS2oi6Xv8TLDEs8SeU0brr2tGpMlFCAftmVuq3vUM
qM5jRrX5eBRu4JYo6HPKmhmIWNG0g18QwgpTUlg7Eb7GSI8HNTuckCTObQhKiLpaN+WiAdI+Pr27
fkyFCxzuU7rVolCF1nT5bPv39EmNth189Fi6fuRGxWphv8TAh4y0vbP9QVh3j8hpZjDtxcRh4zYE
USDhJanIGDEetnYkoM6UKvl9wsTWFYZ89JyNN0dMZ3uFMmqcBdh0Gd8lfHn0wkqTHQydbpnsWyAg
baqHUnautdLmUU61TwQOKIZimGx2xgXaaFdtC6BZJko92FoyxCNKsoZUGdS7+cctRd10j7cgaUNx
qAtwU8GFhU5PFUuwvRIGMEjP1DJsgAE+kqJKimct9uMfCgwDbccrMK3KaFXfDNL13o89ZgmDqC+v
w1oGC2UOqDDaNJcUDzv9rM7MmIUanZPczeL+S65EC3wbz+fDcySpG1rJ711LgmJs9BNyiuQ4PKv1
/W4NGdWv7/xd+zZSHUpY6TNGIx45fBuHC1Po8584TFd1ggRTypSpMK0OuceRq7De7JGkW4CT7/ch
+6Fl5lxK4XXHn1tHnZWpamG4AwDk1uHpJiJju+xOhSjN+FZeeQmtSo6UUXiuaNXncOnpzIik2btK
KY0biZzoDU10di5h5UCxEXfxOaBshu+ZHIwoWINbPtbpB7kftvETbl4pTTRRxQmjvYu75WH0HKuY
nkPYUR4bbIvBZEgRgOz8BslBAW815b4Ss1JTKhUv1yMKwrVc2LHVqil3ZnKvwjRwAIYc0ahBly8D
ktNyOveqA7zPepFMN1ahv7y76VuBAU0MItSmgfqZGd/lvd5X/qjNP2akbbfNldrVY3LUCAz4h6NP
Uw0SdC/d+s96gri2WvNFp3Rrj/F/hnIg3bTQXr7LFRZsKChDJnYhRSQJ1BEaqXMuLc8pRz1UZc7q
EhTUvKvm9vWdhjVmHQlhns5qZ2v1dwfAyycOT2SJ9NClushT9D8UkwWG7LGrpWwhMf09d505SEjb
Q5fbiYwYRJOx2OCUEm2Jt6P69ZBktKrJSYlohKfr1I1a6dmo4q3wkaAIO3n5YYS6Dm5aC1hR1CL+
s/151rqggS8DwJJuMmB50JXvSJolHFAOkzZTkaUTFGZpzmVpkCYcFR6f7don9XYZ+VKhcJz6NfyU
TjVT5jCZAfv+x5b2YGl79f32GihLRq6It/zH4DHhgMAPc293bfoRjCUEYMpBUAYolfzxpL5gRav2
PXvKE642MTL2DBjm1FmGgSsF5zpDh0DLvonAFh0QuMCorp7ZKvHkwm5gPg/xgrwAWwOS+KKXsT4N
17SyylDQWr7OwFw5T2CXyP8025RlONbhG0sz973sI44a7lnPQ8jQN0VyKpP9+YRaKuVxJCRoAPUx
EakzgksVDU3T/WWbvKyymHvgOv8ElzrSpTIoW9y8vlv2ZfU1fFf4r2Ykn2e4NgGU4objGOgjg4ej
X1eFLMlEZfG+08on0ATEqC7iy4aXG9LWKzy9ev1SgkH6oM3KD876jgxqECcFP0WDytkbgBBcQGdq
Pi/nJyLyVSzwo+g7rcQP6pGANPcRd986mbHuoNCtuhKT56doJB+xHWdgZLmSYbyBoIO7ovhdeirN
FlWlQ9atYmcTXCWEsg/08dxDQOUY96UJNterxT+Y3+Rx08j9DoeSV3eVVOV2UgGVS8gcd/L/YRb2
oP/4rEMS1si4M1sJuby95B9111IDVcDucAFQEXFcGJcjEp29xP/Pk5BjJyES/6Rlt4JrEym8/RKA
Dll6QEcMdz7RO1O1rTbcfErw2Y9RYg0PHSOlg2hYJyJMCQAPkQeYnXBnDfsAD6+WXcqyHE25o5jI
mwVRntMrRntmsSobxHm/1iCJ+ryW5H8yKncZQgf1tHkkO3nkGbE6Qup7aXcTtBk+Ib8Mdzy/SXBd
nm54Mb8+nERiwvl58TBF/aCFOr+0oot69CkDmYZy29zly1EVKj8tkDHHapomn9UkvYn2Pb5Q0VRp
qz33IuPZlSf+iTlkeoo/GZR/x8Wbntgzj6iqsbTKCd79v4nQzLC3GXg7qksrhTVozDLkYk8wQwcX
2lQaPUpECgQgRJzW/niFXJmKYGEaABNZcfmRpXN0x3XCDkURrEj+tN27ayhrLTgeD4wqnIIfdY5o
Kxf3knozlW2D7+4tcYeN/BeewdwiayoQHA16EaMnucc4EH3VCRFh4pNA8tsl5Ot3ngueOIXLfhRG
G2YqwWSRYBIx90w2a3NMiexp8E/qNjIiTVoDWOOn/m+Qa7l41xqhr9Uc/PIfZvSBQBXAI14Tu0GU
GgAm/MbA9m5YN+Hjm9QUiaF7AOAId6iBcEx2Mj+y8W95uLdDIlYwZnd/UIRo5YVEqI6NYk2PPl8w
gkkzDHrvCoX8aqRBSss2jeavxeZRNBfWrvIG4g2V5XQh5GN+eZGGOr6tmbqlMJeoujp/Z6QwS2JJ
xG+QSrriD7tKcRq1OuoBXcCRlc0cWguz1E0NkZgE+7Ad2lnngqdhW2bCLwqtiXFM56jAdD1lydE9
282YCI0Y2Y2rECK8QU7wMUs0GxmRFKHtQPrwy1Xu0CicVJMRkh+SZIDyWlVPRe+5lyR3h8l7u4+y
KUIcdCaOk2A4c1upNq3tcF9KRh2VMI8Xvhaq2wE8ngjeHlL5FZtVI3RpWqUwKOkr/EyIclkUN3M9
qZPVJ5dVhTXSUVFIMdaRlzyYf59jHHhsUWJJK+YadkqKH6oadchWDZSF4muISWOUJpB/4IT/Scxx
Q9Nt8DCMCJyWhRZqp4C7bSxdtBnM03GCzCTg/s+R5dsHUg1ormjruXBDbgugwyIhyfNb3rq9KsLe
+cn22tAP3ysOFWm7l9MRfFGMrAvYe7ewm0e8liGXEK/iypq9DJXwcXIQSUNMHxABWqqIythANdWm
4t/FJZesjdgLynUMEyhRfQVwL0LyNRutEv8aAnh0JdYDQdaBNqWS9ndpxg0A8QHoji0NvYW7Y5UB
cbcAqxf9T1nmwd1a+L2CeLYNkRZtPG14oKVjBOXVNm716gN6ziR0ZOl1auplRCc2VXVOnV2FOJ8j
UH05EAjGzsx6vmazLl4wJY00yVeCoZKPQ6Qx0oqU8sATjWouSzNxo/xY738wHfFy92SpzcWN2UbA
nPfkDnUYBt+CiMBiVwnKIeqC1+xdxR+4epLUxar3i2yOqccKgKFhqjrpwXB0IK9sNif2owOQtGH2
Zorr1v1+FfmmhD2Cr0vLL20k+lhAFzLqt0YL8oh+Xms1rqJKiWo2Es0O7qmbAl698zVr6V+FxtTG
qGDYwIB73vWHu1dYGAxUuKNXmPvgFQpGS8uY6G9IbA+xtJlcdCmva7ndvq0kltWLlW3pDzqI9BZG
wupjnChthp6PqdSkrHWu8cxZ/kN3IxzbxM0ZbsIyrekXbIfR6f4wlqWqPUurooIBE80SjmjlC0vU
VK7eG1Ebvw3Jfw7YHuWtE9UtTEl704r39ncjYmhELT51+yhbRy97bNz3l6224KEzy4RRc7q/5UzG
XeFI/KC33BZX+N+GvHjqdcvHu5vtgDaHLFNtx+6zmM6tTgAsqneQ/GhiTa/hyyYDe1r7hhm5/5nz
pSbPKMM8GJaZH6coKPqh1D+uTKEyi5RzXqu78iuV8nslhJ/Rr8wAwzBnPMMkeFJP4cqxc2QEM80t
7n806wugpUXzxNs9Cir07v+36u91XhRR+RyqIMI/2ufLskM90eP6NTBHsyvOljHM7cDHVuAEZ5wX
WnWvmgZaMqjGuoFFZebFJyachcuH1yqXNYdA6rcdjDlw3rCMZ6PtC77zO9jMRwlXEN7rsjMrOVXp
i8CxsljWEoWHNoEmpbSYzXxRNaMUCu6z/41+ss4PiMvqm/21U2/DJaH89oJIAw6/qofdt7xYZiQr
h+Mlb0u/RC8uqRfq9U8rBIN+NnIvdHIYw5JRc6GJDmzzsEjOrjPGrrvN6Lhuj9uKFnXfh/lkRoAO
D/Wx5O+TUCJX2zna1aviEZlTklgUNIfUXIAGsY6Os4/SLL/6Fte5bIx3ZBJ5whS0zaaIA2CxPdAz
j+OdwFNaV8WKuIoBpoCj3eyPURuEQLjhBHVZQ4MXZHeZSCPfQavi1VxhZGO6larGOpivcqA4zChJ
sg3weWcJrtN4cWr1h57fgXjrPoLoxWadfj/44J+MQl86D9BZBlGjH3iORPmNS5L/exSxD9eMuLjC
32Y1It/fyesOhmDgBkz5roVJ0T4Hw/Ky5OlgspiSFkfhwWdslSmJwdVopyEUoBAKBdDbgoa0CR91
g7Us7+aEI/a4UYts7FUZ8G0JTERI7wQbPa7zu06tPQ06YQmUcLy2wx/kUNX1MsC+VAg6YEEY/nYw
5/z8gm/pNl8ga/KLVcE5M+gvxbE5h7ti2mzXnej64prxYnzcN8j23qolAKVWs+K+osjzQmOIXgAJ
6XTmNSZ6b0mJGG5YX8JfVtNh3+dBR2pKOuDE8RNkyKIEABhH6UlXGlledOK35mkZcBosuwgjlYzx
J2ICZLbH6bqhuUecYkXdJTg8+BG87BgfbW7ENJi2cf+BmzjyKBOsIGim6XE1Cf+5fXq0mS1PgVc3
ZJvb7KRD+NQSbL/rxWjfJ9LWrq7Fm9wVKUCKPGyWtcmDPe71CW7GECnSi86Z2pcIbLSr1LPeyfEk
+Ii9yM54023zsCViSozGoQUv5/pkZ2MY34zS7nbEb/uIPxq4qc0LqLAm4YaXkCYGEGkXzW/b+yA4
0nRA2HIiTse6qcQi5e27rgrHrInizEq9s5Zqm98zDxV8hyQW0sLmFoOTTcjBcszb6zWrbtEdfjMI
uQ3mtWDkpgYvjHEQYbuIhSjWen3C32FJTIpFO7oNFCdFpYlWery+3JYdSEci+0pvZxMi37vvpUWO
HLwABrOlnO1Uxj5VYyTjEVsv1gPqLKzy4ieou0zfsn5ZG2HBIrChl+iOz8sjePTls9zbtJMcuB+N
YgS5CFOemhuG7fuHmMjgXiazUONL4D39mj8sP5s4Mqfmyg91azCgKVcuGr3fQEoutP4L5cxJKMU/
R/fFhWS5HI4HH2NuaDJEsEU6xzmbHZjlkH6190vucUGZSaoBJ4iNH/PaQV2LCVdRdlK/UBb8rCnR
kCVyL1GjkZ6Lxn4MqpMrFGSmTggcjoiuRUwhEicLHB7YXtAEPUI/OP20qNTuy97WUQZ/vNraG8KW
iJkOyOsb2qekSNa6Mv8uiNH1d22DgyB7UVlwaI0WH7OimAWPEMEiMMXeSDHRYwf1lHbYXtT66Wdb
rYPC9iDleGwro59ezsfrs3ovAjO+pztF03UzF1mFZZb+9aJUEG4FVlEBE/oCmZkNfaTfeurqmMHD
m3WW1Ie01XdsxZjQrD6LyebukOlD8XUP5louqIcXXd/WdijdQtGKiOLMBkU9HdDMHd+B18CRdjjD
gz2FXtn5XD+oQQCLR0pYLBKLTfsQ2uOtPGCLeagZ1g5PgVunJobQJXyoAqkvGPcNhDBWW91CF8Iu
/R4+9cK9fVKV/J1h/NFJ+v49WWnDNEGay2pp/Gb6+lgHmi7H6FJb4syALluTo6k7ajHxVZIY8Dqx
c1Z5//hOUvvOgx+GNyF9sPL9LQBeDvPuE2UhlBDh0UrIR9kwmBOYTi2ZrtoBgt94Yudkf98psC20
jabE4YGDEYbL/5GYe7cagMVTBI9EirxsKULXKGDg+XKw3PTf32XZkzTcbGy7Y0jE8ej2SqTx73oR
MmRhIf75Iozu9tqk+1dfR9oj6cfN5th5UyxhQXX6W2wsE60B4J7fCOmF7qh7IMxqhEbT0LRkqn7u
c1P2v7AHKvRLZ9X1Me5ehh0K00omr+kW5udSvKvLMCFXG/flGkZdCROetCC1zA1GYuoQr3BJPiUc
U51laoxiWIDzG6QjdKZaE0B0tUOQXFjvbrKPHhQEmnwCjkMwxF42X1iaEQJuVXfos+QKC6m0x0l2
+L8LmtFo+ZK4S5ZXSQTT69RQ8KdCMdAl4VW+ODr7V5IW4+Ls5hIQunVWV0gJ+mixm6f8q/QSUa3v
ptddw5CFapmhkgDiQ+XKzFc/kebjKSzIbHsLqqjjo5nXM/gpqyjXuEsrAVSaqVtFtXXvV+ykcckn
zKVBVEp1uKpMkV6wzKKpZ8nUrNJXcWc+n/8uCUENfvkxRmKBmqyey3wsct6/M7btX4t6W+ymaVfP
TWCWNIHmFZdpKHju8sd+0gaEeGE45ou7rqhw8GR63/8Vujjqc4F0oJf844RVJZrUWxJqTxr1wnx2
R5sseyGr/9+bmseK7m5XuSpStQitTJQ0uB1+FITPg+nCFaLzjNET9xqnsPHs7atiMIo6RmspoLZP
i8M4R8ffymVVPtsoUXEt3Scy6tL5rPkaAyg+NWutrwuvCDkP/ut/u42mheV6XGBzpxdoZwa6MXWL
PFHsav4MgsYhgRntgv3WB90Q8B2pc4kZ1Lq5QQ8e/9aoij+GrhwjVtVc/tyAHDZfqMHmvuUERfCE
ixvMov1esTWBzC6FL0lGxVVZRzxKUIlQPsWy46Q/wrCYIeHz/Tc/mJJ/eRNVeFqwPtaN7QVaxf8T
uQQTj2fIJByhVbX0/wNDlOn834PwnQCx/My5LeTnxNMPHOSXEcJYUkSU7S7qsr+ZYI5MqkI/TN4Q
DwLZS6dYO7Y9cGzrmVSdwyD/fYUuGYVzJh0w4x3i1dn6AMNwEyphaWkkK/p3uMazgP/Nbb4Ag1PO
PEdFpG653LIc4utZ7I9aTGuK+RiVY7OWtWE53UCLmp/hWbPwnA3UqIXjstbLfyr4EzYsZVAyipi0
wp5y7uYvzFCvvKCzzhWgU6cvo7vzxmmz5x0q+mF2oc3FPpuspEiQsTwFoOT+IaHSwKYPUR4SNWqJ
Y5tkzQpGmHDz4faBNqidqrqb7sq5nUXRAPBSDIPCsn0K8XRbp+8sJP+khhddm1LjPFVhiDkaM0ZZ
3DueJ0Z0/simpZl8XY2qyTF4Vd9gm71ZZBDH/kYN7UlICVDB5sH4nrAvzg8q8Ff5WHAVpmvpq7ox
t4ybjuVDtY7EGykMOlVLQaeRe+n6VQPOR3A4OHyybh1vsfvkM3IqB2pEwRSdhOJCLULbS15PIC52
XKzupVguDoVyVBCQRwqkFmg6T7cJSbN8fgyIrrCY0ym6pX0b3LzqLdmmdtNXRBhX8lPamLjplb/G
ytaxsrkSjHRyoH+11JMw1NJFyvGQ80JVHsguWUDd5qDuB9C7DLJWGjE/5/cJzo1ioqUtKWuNfEf6
ZGcp14YMgsL+fgP7erurJ/2+v1elsWvpYyWjfS3OkpzBMbDHR0ayEN3D6Lq0Q8PiyDaJwJ/FtOEr
G1uVc+18NC5a+l9hLHg17Lz6bQ4vSqC47xhFpq4RgMfPLQb70cc4PRSxyOVLVGEKJYPh96rEN89E
tXkat8bkI9sxotRR9Jx4waZzBULdw2TW0m3wN7C0pCaDUNk0vpbFEYURpv3ZSbfxjWcl48iZ6F+J
C+/kZrGK95t4WQXlzJNktJd6f97aC7HNHJ1GVnuySSWcpbzOTAGgexhSos7oHOjfDBX1DZMaqpto
qV0SqKDU+A82kPMvlCosLNJG1W9EuXcBigqSLvXJ3CtFNX6uKUtCq8ZryXdMsypASGCfcpHGWNpC
hK1RbW8dba1fsqkuh5t9zs3sWrlAKliMwEvfJSExWrNeByXIXlLp3BTGdJF+Uk+4Zr+B7NTAGPSQ
i+Y1yxvVl8QdZMjm+bQeqXpVAZzvw/Im61qSuCVa7K1NQSuE/eDJsYp9z8Y33AtjQubEKvOJZhTC
p0mvFHQfn+xjdYGmJc64c9B7dfzTCgaoOPBqHHzCVN45U1HRAht0eytBfVeZtcSbWEtiHZstSxjt
MPtzvzUZaaOyAy1vnrUn+qaOwZOK8czUi4E2DXMEq9zHPdcDQ/D+u+zLB+rnKDEeE+83l8RLC1Au
cMl/2QlBgCMaaA1FQHfbbH//fb05n7CcaE4bxqA9vn4o0Op5puyzZD7O7kD1X5NV8bBtHWI2eGlK
LXTVGCwoOHf/+UAaKhXrbCF5QGwwHDg4ry7c3YuCWPQoVJFSO60nD57HIZ+Ikevxb6LpMW9z7oXd
ySIgk0hWyULTVHsN3OHJjp/XMBodrppTxywC/5WnEtvjBhzRi249+TDb00Yuiw21p9hT9gADsnMU
TMXLG36nxLYZeLEgfjU7kjHKGB+D2LZbGcY8jJcK/hClg4KFJefScMTnulDoIANdfIdpS0uclgjS
BvtJddLP7CHMwQFb2H9cHxnU0+FqbjRQVcwVlv8Z28euWO/FrikIGfNi8WBRBm3K3CoNuOiC8Fct
KYa8umA0+XEXxIOauzdfAybNXqj+rNomi4GOgYo4Y31+OPXczP2BJym87VwI8F/Sfd/S7UZuO8C9
7Tyu8eVlwwgd9nXJ5/puee3MWA4tA/vvr8UWx78hHDhEQTx9kxYhqOJM5TqiYygcjau3UtiXdv5X
4QOEO3T8a7TpEoyUcSIv+LddtzIbhR25D9/EGp8W2k8VXcfqAsi13uGv5qX2FT4NTSG90vdR63OW
bmb9sWcNl8E3EN4IPqy8ljnA6xv21p/fX3xl14IdiMvKXeofw4biU3dBZ79Wg355hpylmzmZRVX5
6gE14Mli7b1ItDekdTkdU7PcBv4yrPjYZxgekFGUxI2ZXpAMNlTLMCCtn0hE/7W2/80Q7L1ao6Yn
GXQ22u0OuRV6ItOmXkiYZdWRF0rF2Q62GW7YAEX+KpxDylNIFUQgT67eCfUT3C7gyIISrRo0lW/7
wPKnEv9OpS7t+8SDyAw/EKesIiPYKBJh3YRfDV182uTH/DetWfLaM/122+57QkRxcrq6bZZjzWvL
LGh7gasf22XFSkZe1TdO/nin4QYdNzyf2i0vtVJwbH8NFsJmB9e3QPceFD8jM9F9peLtXmNAj3qc
LAIMegS5KGALdJoE0Hod+YBe2WaiKWCqF42vYAqxxcmwd0Fci4VE5ULJHXffx32BdS0GGD1M9JHw
Hp0ra4OvboLgQwN79CDoPD4QQhFyqGoq9Vn2YpN9NC/AdKDiLsUTjmM5P+Rc+n6CIbuS/5WZlvkB
GqneQSvgvfSAEWbFJJPPU4xNVCwJEhTunAQBtSKBLn8WFCFn/Yuu9M8xku+b+3Fa5+vLlw6d6Bj7
SbeaCKLVX7S9qYLbgXpy8OUcVk4V8dqTYo+CSih6jpG3X279NMIli9OceYMHwqjGwFyUGFB7E8cf
2E9urgBYrewW/gyTscO9WBv2TPt1BzKUt8kRdgEPfJn7kG8QhYsaMiqpRdylfQKi/Jwg+bijJJWO
yX1NTkY4pBJCS9QDPwwd1J9xlXBe8YJN216Kn3xEjHmzgaI20Dggp4+A7pTY4Rpxr7/JEsvxC31z
JmSGlSO0iRb9fUGYcX8oloe8Z2QzLTbyEPZl24s3NSiqrcckpcQQZMFpNrhcdpV5DRt+oT0Blh8u
odW1vFbcftNwxM8iiKDWtMiqOoPosDjUMg0dCt+kK0CaExjLChitK309ZkZRcKQFx9ajP80JPzv7
3RESwzvunAzZTxzhiB8t8FZ4NaPAVOtuuGapUprbxOwpx6BC6tcFTGleEjjg7w5j4pYqkFQA9hx9
VUX3yduPJI/i0f0qKMxfTH68LXn06LRsoyy1l9slZJ6AikXwlNYJFvgscBiWWJBjAzOly/RvgKza
5uyEkaB4QlwnJmkdXvoFUC6EuijaL2BZR7oLa9yrVpFkx5qZAy09ye1yeVLMajJE0mdBezlzxDah
NvwedvHCv+pkIaLwX8bVE3HZMk9dY+I6OKGk0J57aWTem7N6ffNb9y9JIojczbeDjdgVnZCNeEp0
NRkBhjKlPIxc5/Zk3YUSRVXTxVeQr+i2bPK8ROvFFMWs2/7JZ8jzrGnf1GuVznndGNDH2Z2Fks2N
/GQC9tOhtNcYHiaCSAk/TszyBOA04wah9afl8p1ZZFCsQo1MTnVN/Ka8BXkRfh4gbuK1kc+72GMh
SUkqpinzuJlgKF8WezKWOAQMM2eWpWDHdqFZ7jxDEEqdkB9lzTq/L2kJUKHnOu9pAHQmFHrHtI9F
fB5itg4cO9UV7/M+ZtR5jgkf/SpAweThRzTl2BD+pCDYvnHyhtp6aGiEAH28/XWkPQNHLKuDJ71F
XETJYIwgJH1WWZXkbEZjed4Lwqw87JlQFAPHvVyXGubjcNn7GnPhSkvcU0G5mj9iKFEm/BVzpxW6
gUG8rTAjywYX/twi+W/exmHweCBcE7a4EREI5r9SNV3ceHZvNLX9tpjyzLfYFFZYRGaR2G20IYxU
Qk4yTl4c1XaLdwJZhnw+4u5DBGAl9fLsWMZ0N1MAVh/DORE4/84Nxty2LYslzbsi+kQMRBPT71Hn
42lOcFBXyCCM5RCJoO+Zl2S8L4QhauvNbUjXo4M13jWIXeSn+r/1tC+9OQ5W3ai7yArsfZ/OcrFE
A52oYbt+djJT/ENUdGYrAd63Bq1Z/NfwvusMs6eQkyN7aHkSv/Nj/d584DCO4j1fs3VNwjowGKYL
e0v7pgNH7np2IRINz1SqrrN4PYJGce+NmjRT3c1JZJBI7Tq0bvToP2STXTxd71ZKYR+ksLqa6dh4
ZtDh4TT8iVv2UI18VwCOxwdHgC4Bw24cKEpdrzoSvTv6HDH+gzHNy4SaQB6Vx5cbHl18Fa0uQMDq
5MeMJnVdEEwMELRBUcmop/FIqO/VW/c5OiLc04P0vMDDsHOJgFd/MgZgnLyqJ7nvMW7cTrtDLjwC
JyCya/beo0RNFCarjunJdORjr2XNiT14ougGo/NUFD3ecOS693qUJj33xLIBrM2DYt8Y62No52ka
/KL8jDGjVQo4RqZcJr2x4r6q57LaHF6HVfCD7U21HKaXlddBtn+KbZ48pij+V+tYl06neN12Zjvl
6bUarIjGF4+NT92WYEt19ia2y4hPm+t1vJj3xL3nbG2g+4NCaZXIHO/zStXlcGqi6MUdTslmChHm
OqP+aAlqeeWOkhHI3hZL3Ks0ODT7jtYxke1UvS4anvU3iXhwjMhfKaM00/gdNz2pSf9n3R9B0Duz
T++cbCWak/YcnbLg+PgP0dkCw3puHc+LMkwupDvj/ifl5UenR2a39U1MCa696BhMdRalzh6ba62u
7jiaz0kknnKL0RqQ0TSAX8E0362gYfqAVnxXoc93NTC43gubLWKOft7t8P+ym/4UMdPF68S8Zxeu
qkBOtGY4ZJDJQosJXXZyi4KtLgM22SrsUDxuofvK/g2SOpdq40a87FPR89HQ4N3tgGaFmdIhPnAb
XnZhj5qOiUEgokGER3eIjPowyOTmsbKLwr4WD+4hLpYDG1cqstUm33F+H7M/sHiWLmWL+LQa+eD9
WD3e83SUfRTuvSA+t3bgyN6YomwAVyIizRtzdYVYo2x8bCiIB+38+uPqm9Sw2KXLTesiZrMMgqX7
lcnIEYS933kDiJCCYtpC8od/APdzFuGxQko/b7CFUyhhKT2rD9P33bclJbWZk3HcZNZ40x8yKpAy
cubSotaGSsVUgXHKokc1XZeYln+0SBGcXw44bc858uYhSQOD/8YpKLwAbY2JSTotDkw7XdI/udoB
QWO/mn5bQxgYWrCyAOh3oXNAENSfuK6wT3qBpMt82FMu2938SgeNWiYvnrtWU7VasD+ywuMBQB22
9rFhHbpsWtT8z2EHJmcYQCvEy9sDFeYHD3sSgm0ixq4ZIKKqtqnOOHYoYgop6cz7Li/TT4zB8vlv
JMBAbnOARrL8kOVDxfmqB+CnPMozRXdBQEoZ/JaKUm7Ds2lQtrcNKIVTwzHuIf2bMjVPjSRTMfLs
lhlDCuJRSpKLGL9w/Wtbcf0T/0d2spy27gu6LfBBaeVEkZWTPAPYRMWqHx9/qrkvgwDK+QTZU1h/
HFjX4UYlMRaAH8Qk2c56mqbZIxj6upiXN5PvPKrbFgm9H2XEEesJ7fHSLmwM0GTXlMwygFOaZoHu
7o+1X3NcvTCidmCrx98sjsxibLWsG57+Rg5R9tHFAtl24PiZZ2KoNfPxVWglSUBSZ5fjvRoHLLmY
EzaCLd6ykJQ4LsvTTgLYhhJQETdgdspO19pDAKzOmZTyl/ilY3nKfLFnjSa7dD0MfcuqCyTXn+Ih
8utg9wNArKuQFZPep26fC5ak7uFwnmzyhCGm3ETx6o4SNiGeaEEOl6P1IMC7OhACai+iCTaENXs5
hi8jSI3Etj1CLLXu4LQhgpAwKB7CaJjpgiVHf88mlXzlXPTehWTHhpMRHIVUkBwBJ88+EXUMTifX
M+B7oig7Nn9qXz9PFgjZeNRbtMDgFpSU9RmV/SzdjxHUDcO8MDY2qXdRc7v2HLfj+HcC+dglegX7
EGjpsz3Uv+13f/ZHVoo1PJJ3axnY7zHoOsfqm0zmkEsCoBeIgilkg5YU1rqwu/OUhPm/8tmiL7II
G3GHote2jU82JQq54EQaNnMGlYAe2bzbeKmwETXOLDWdsFDalqGlpQR5uvqAV1qszjXYXPQ22Js7
nupIq4RDscdTU+oSRkv/ACqAAOi7WLBIyOsqo/MNeUpbWiOqpbZzX8O12TaLGOlwOqPwyHpLfXZi
ZHNzf2TBi6cXcU4jDRwXtqm736OUcMJ0497MAGuwJ4Jpylb4Pyx3umzrA1GHSUc1/iZ3M7flcOov
oU7VVYQ4QIlVMRqjZzwhYtvgTSViMEpHU3woVYoQS1vrMc9RgWt/2jJSWTMSda9lWPVZnsnSyYl3
NVqSugeALBPmqCpzXQxktp/OtAkjFPfEgszE6ail1TdsNCAt//dRlLgd/zPjtko5idCGKWuBubam
+fa91wjXTrkJuqgqi/qUB5OIcaT45tOTlPPo2uF3ypDvoPWOBDnHt4wx+RjWDypNpf5YvuNk6G1G
t2DL1G/f441KsrPgJK5gA7iG2vm+w0eYDrd7+/ANShvk08KHQFjCzXISVob5J805+F/qQB4RbKVW
SRPEGUxy2Py33aD8AdwWz4SrC+3tRtfSnMrwD5ngTSqHegQYIkmc7pytrRFbssBGmGGqLyXMDNXa
didbUKrvSNm8GhNP7oj7YBuyRuFJPtIcgTu5RuaUSuIda7uDDyUI/1uS7nyOVZECoW9NMsQraMsx
TQxjzmRDQEP0qnp+83J8pcbqgnCB1qH1AFajmNaSbWqgha++zqOubCIqfxDS0vAe8DgpvUZKZhBP
7XgMpn1V19x+jstij5fY04f0RkYeS2p5zdnECp1DTfRFE1gv4W+w6Yvx2zdXfKE74vWqCcKeUbTA
2SsO8XQGN3tE4AMtBv8qEhz/5imq+/4L5ovnsUbpkz/7HwySWBC+X6mzO5o8LVrJQsmqP4wUj6ut
TK3MVX3goehpJM/9PQQjiOJCA/YVMo6mMpSQ8CYdzRzfGxuL0lpN11ogs/HJZ/SF1+6NBlqoCCDB
5YiAygKXAIvMeuyE4c9a6SKP1LJBpj7q992DN8adGrr6gBWffqD9gJPrRmcEJTEZxzd5A8uRmabC
LMoDZIPM0+7eLaMMp9Ist7y8Naw9LluoBPKtyp4rPNBSZXW0++XhrUqbBCNUXXolxdu5Ps6OYA8I
7xwP6CR5aQR7mMt4dVbctrszdHa4KvI0+nlHpH9PfNcc5pzq7WR06vGfq7k1GqxZevfVcb+7PsNU
h5h7/mhOhzp9Fb3z5TBmZt7ElV07HFmV8q9CbfzZZ//z6yvA/apFTgMqVua/91FLo6FV5b9cud9E
sXxqAWJac75PY6+KlQQSUFjA7tt26jvg//TcFDt+orOjcEu6LN1iD0FT/+AHqvbCCyAfXxYl33I6
G3DVHiPFoHREXXs2YM7D2JpB0Qxd/pLr22htJib+QVhvPeyk5JjomRTRcLZj/H0iufOmLM8TCdd1
MBbSai3PTNttaWpbAfnLEScUj1CZcZE5jvMemVmES5COsZuDabv3YH602ypwn3d0KLxIm+AdFaRY
y41EhmaNE5SQ3tGn5DUZ2B6JJAK3lFfHTE6RhbgZ332oWkQNsCqqEm/bDzx2tVNc15s7hHNtPiWX
bumwRxeAp8yVLZAw9uDQFAQXYJo/rHD6EnoAispx8G9B4fl3+EYQYPZYIN/nWpjwJZM+n9T9Fj5H
QZ4xCm9RF3emfGOHRcStjL2CUZjJ50fZzweZH4sNOZ11pbdzwJcupGTBdj7I8CyHYBbVkPfQ9C0N
dPHk1QtkvJVOaIuvIBxy1UFj3HWulOl5uodF8Q8pwiU3a6kSl1pI5rDpn3VfEEOHqte2cpAaUP5S
VThJ2O4r1XXyUrasP8zHOzFzTRRtvFnwdRjc7gpa+7cMOxXXrImDz7Cbe6O4CdUyNVgBXDol+/g+
zLsZRJi3rxl02oKfDh+xvfpIhvLbyArxZnqcIo1dCBRBV3LVXLpxnZbxVViJ+gPDJSeursrcuIgw
P6eqJx5z8O9LD1/grOOrio5nUPqXD07RxE6xixDpi8dekm3/HIOmm6Wi/Iubs+93y4EJIcdKfCHW
qcUPAdBM2EAJcVFVhUc96c+SgjDsLSPJCy3gs3DfSxL0aNcI+vEtw8y79W0y2khF4qagOUDJF/BR
jTXUGUGKydLneRjPODgCYn8/om2pJcVQNzGPVJbRvKwJGXjDuje5zAB9YAY+1zLAfZxR0VjoI8Ja
Ap7cygUeriwbAko5lONY3GVsNbJfXbaV+fqKVqGhtOGA09OX9vspHlV2gitlYFXDt8LdqgtheqMb
SDOwaAMqjZHApVGA1gysabWmgCVorUlI3ma/h2f/rHUjFvddOX0rPIO8I/R471zUkLX8Kenv4kIx
t+O/teqsvqfWagKuDDd+7NYSBr12Bt/wSX8B/vJvxGyFpbcDByK7NxTcQKkEL8n0Y1calcgNMAib
luy4HR0a+7Le9rWG1bLbmQafh9+BrWDj+XRvrhd2FUqyHGIOLSZdADat9R40uKWweyFjnr+HjKrz
PThmbhH5vSDriyxfuo/xeUf0Xnmya+bAwq6sRfftKb+WLWuyG76OjBNcnJqtB8vxW4uYizvU9btO
/j28nu/jlWlfSsMK5F4Uw/2X0zLa0aEbWrBq0micLRidZIKcP7HPqIOHW6uG7D4oV21w0yzyNvFk
kcPuJlW8s+6/HZe5fnI95yfhZkjScG/b+G16dWIynkzI9URJ8EJ/m18rYKB6rtUl2D8Y1SliwEwX
doyNH8xjNIO1WKEvQgqYtjIgvyny3IG5V4A0ASryLTl5JfHir8tc/yqbEGoDSLC5uLZkYfZejIwu
GMinDCsEHXbipPN+Q4mrPtKG5RLZTSaw3OizkEpLsVGeodExO7zh2p9Jt8nZftgfqqJFd+MHQqRc
96WJ94ank2L/uK6XKGp/EvzVYESemaWWyOLWSRiPuAO0osPHqk8lPiozil19Vh5e3DPLDAAe7zlt
ZQGVJMQmHnGxamOsv1FpduUSrFe89SssDQy5/sGdhijKD0Z9Mm4dmHYk1Q3jMMIbVIthJzovNhVO
NeU7gQm2MHbZPt4x44YgkST8ERC4dmpMoCZZaMolT2t3apkZuCYqGqwQL6xZaQl4Eh0gmUB7SfXd
M2fYTPHSAZhwRrGTcmGhyCG6DrQQfcyZD54CC+h8f78F4IaxkVlJ0izbgHu7gmX5AoK/t5H6QsDL
e9G4ThmLkLEyY9tmPYok1V7JlsSWnhvpnn/c42gwtwDNL3fdMQDwzYVv1xT6RqDSHeS7NSni0GGo
6vdU5imXN1LE1DYjVq/8UKmQETf6oS2+TB1NRFzjwZKs4XEYlICxtSIgIR+Z63ypUHTqP1FBWdrA
nPzfocuveJtmJaP/VA6W9RIsEMPZWelM7p8F4Yt6I9SWTwhmDoFy9A6pFW0v6PBH5w4z6AT3eeJq
l7yOucUvtzuj4ds9txC4vPm3NcLtlPcdHXWtL10sVtXyjIom2jYDRKxcFW7L5pS6ZUgQ+3eYLzXI
F0G7bWSwF5ujVj6Jac1K7tOxvf60B5firvO+xakUbtVrQv0hWDO2FTXavLHl1k8cMvTa5T6M0S58
s0wUrNd+Ov4bfqDzFkAonKPcWkbYyPF1yPgZffr7rC5xlYTb9vSJMAskpGJ/93/0iL/h2jsFkuoT
6tuGJBSd5N6G3ALuGPd7V1uRz0DgcgbwwtATLyUIOGxP2A5a+HVbtMMfX+zICvCj8XYZEoP3eLZ/
33lt+aclk1E8PG3y+gB9nx5Z+g7tM9Mcfki8vDogkq34g1yPU75CCQi0KCKgwB4KZZgtzZPqCmPB
u/D/C9FemMQoX7F761CEfWBYB6WGwoAepftqBCqpQQpbE19K8lonaod/DQCdqKlmYjAG+tveYL00
i7wbWkxQWCszbYdjS4+ql6hrZEAIkvIbqE8LgeRhQYTUh619AYZH95rdx79PeXjNLC/UyU8SMZWI
HaGsSK8O0tQZT9PKqlsXZxP80+gj4+8PgYt7nNkf+/ZpzuX+ZeJ4OxVhsmEtDE9/bechooq2Ewk/
vA2hWidpl/3tMN4YLyQNeaVhSRR+MrZEq7FDCKY24FqekIUi8FeQNL3bMh7JBb8GLSFK5WJl8QXc
CEnjMZOArRZ5HQGR1UKZkfIDQ3TffDAr6jPULyejm05IjrUNCXHeEP9KphKmAt2ArbR6MgnInwcm
TREWgzEfRXF0iy4Lj++7GuqaR+UwJuETcFaGFwut3ORXhMTjUoxl0SP3rxxhRssVAIrWEpTD36fc
Z9yraTvIbKA7d0F8vr80XCEhOPfSWVyi7jjaH76eVcgkosyiOdyJjzHkiMAGX+cSTAH+Os5eNq60
XHdABcAAMvnRbVmHKqosujDPsObOJ5CrMJ5yh3QPbBVTxN/Omcu8dZvcPny9OtyWNK64Vzv74TpW
Ro9xgZxZpD6PJtLuyktsYk72VsIX8SRB59X0Ej78kD2XuhvV7mS7zZlY8QMp2cJ0sKhY2l9FIokM
ZoLII/jx1pchVQPCxuAyaARTeDlCbPBaJ8eZ637kFWj+MgtH+3ytKN8mkgSfRTdz2M/dCeRwyfzD
Kgn4w3VEswlB2RJZx43rSDF1WOn809O71gYJbGaOSLEX3cKF9DAZNh7xqnWm23nG1rL3+dVOa11w
7MncmN9S4zyUNfjCojf+lePRZUGhqs8zUBkQ4qhV68DXOIbM3KxYQQ+6eu2PRRibAD4BFtwHKjsn
g92H3zBZYL+nWixGBi7VWCCeuQajAM29S8F9GEpWPWzVu81I9Lhx7R/shL5iFXh2PKSCf8HuKSqu
OBkCXIZb2EEmngCwFoxDSkgjGuIdozx5HihclC9qjt2Tv6fIXop0BNVFszqtd9fD+hYs1LcDKuUL
gmyu83Afm18kOd16GU4gdXepRy4DA/icA7JG8k0so7CRlsmRyMx7zVV4H0DFQUGGMK3io7t7b1NY
8Mj5OG1xktjCHbCalfh+Y8AJstznE/6tk3skt1vpj37j1HUyoQzvdXHBZqOmehNCMpedmtP6G7Cu
UacHPB7ri+6ejk1pRThyj8Q59J4AvY+FhpaF8+ulwbRI1MSoTeDYgWPITRY/BWSZRSKNWnu33G5F
02NGPYSj18lSGMbSjHnlii/HRvMA1O/nbUI5Mjmpb4UVurNI7hHWxKLVQNWbjbNZ1Ri5Il0ux4K3
MdiWuIXZtTBQi7T8U14uBVGeTKvEk9hAll65raqlaye6W9vqeiimEsxjwtWmd0E+iVzeL9Mq46Qv
FpkqrTjh1AzDi1Fb/+SUPmvX1Kut57rogrGtmwALWgi4G2dmOmxrjpqyjSSvU8INHZyMVRN8T9If
JxhvNiXb52NuOSga54In3jwx5DNomf6Ahnj/tU8ke8WX35kugVy2cxufc8HfEeA/9XoNYTbUet8z
v3oSOyol0vDdARW9QGGZCcPgmI6pHEXDyQZRRNTlSWxEanxy0Oo5hjHeDimIh5FloCJKqCTPFUCI
jhoouxjTdcVl+3yXDLdBpLELqPx55j0lNQ15VtIodCqiDd33Y4zgdltp8joB+tCBFn2vwdsluRfg
KrOKFojPhh3a2Xs0jsK+9jank2PAyWxhlKiCDW1tI3sLm5+VXdMQLLcg0tECiOQaqygXD9EePWbT
vf33st3hs7YgMIYKfa8FsZwXwm+mdrCT1pukuNcz3Ytho12IULGtoIZ5055iftRS0u8EvvEo+Yum
B/3Zb9ltdbsNMR85G5frS/m21PSgCO+WxrjeoafeWpy39i2nRXMm/Ulz6zD/VJtoC3pW/0+iq3Bp
N6jZ+5z78geOdXm2QkRoge7Xlq3dh7Z8l9/EDn6LkVYiBv+5sYwUOdle71g85OeXn3mXS/JK8/mg
BVX5RWFXcUhH9VymlEtTwxYnf9OJUDgadX2BX3a3Dg9YoK/YGAg++GsJSLOah0m6WJ7IwQ7ao0r1
8DP8YFzTaExiTCDqlS7/0IrbEJO13mv3uTEDsVzAjVco8h8HNXwdga1Je/dk9XGq4xeS6fH25Xh5
Kz/LmPjLTUhV76SgcFXE1JJA/s8I8ZToxUtNf8l2PvpBJRLxT6x7q3lUnkNcorh+i2pOjb0aAzo1
yZ++NJ37Ez0oP4rxAMdQr2ZGUwyjvZbFkzAFsRri9uNoxmNpTb7luOANllKoKDyM0oSBD3ZRDUE3
O9+VkUpv2XzHLFT4Ww7XgRtHuCXKuWluBQuzP5gRcMSR+lVI6O53TB681NJbj484cMuQ9fnudEn7
lFXEQLa+KtmogfUoVdoGCd0n7J6+0zBiSTIsfDVv79plTtrpyWDQrRJEolyH67Q20b4O53i6je4w
xGO+fnOZFIbnjqXSLNAEoBXTXGEhjyu2gB7H1l2IPOSGcisdR/uPs+VWhiGaYOrqXAQOOMd47IBv
/1cNaHM2BAs3fORvUiiPaEmKg/SLZKkv68k9XgbQOqeqI990gDsICWr2T76h4+Ybfu6+48eKN4Ma
GB8bghuNpBHyVFfu5c2QxGfd6MXb9ltM88PtGkSliAjF4j7epSpMdkEczTW/+kCSMhHvUhoj8hiE
51iYcohtkCFCLOp2m0roX3ARGIabuwnf9dfZ0o38kEHxre5oGjiJUy4dWWmuHsgQzaqArBvDMaQ/
/Gsh3K11HeoLHkjhWbcwquy0bxzenP0DZSni0WAU1sC8SYeV+rju8DYvzyFBd568dFLOehxwJQsL
dUR8hAvb1+b8Rc6zkLkx+DDc0Ri5EKRDc2wOl50EWhp/ttn0WT+dT6ozOdlTbfmK5qpX5BcXEzgn
tRG0yjd9HyeVr6wXy838mN0RZAp6yWnUfmD30Bn1uMknptuknctt8ictDLJYis9iMoO4QSIZTgEz
4q1LvVTq+f1dkcE4GQql9SGtnHVdFySgajo5sWMZEU1bH+KYY+lHFFGoJef9Jqj7FGkBR4Wgrvo7
WhwrAQktX/uOOSYLKINKTfleo18n1joea2aoEGT+DqQmtoVHsWEy3EvGlNmBDLq8jyC3ST01l/r5
KH+hxXbmI4nFwJy2U1XGOSQJQSyShbpLr9KpA1JKXjO4iFsUMH64wZLGcoq5h7U/VHQuVm3btCXZ
vW1xa8+MpnC8HuGpjN9eulCDHZogMbypHD/K0tRLrKtWfz2+M58vHFaOnMVMuaqtNX0lOOBene+x
OiFr002sqB9L82+b5i8juMYB63QzVj3FB8BQQT1F4FiBh95v8XzMphkEI6KjbCEfHyQ6KkwnLM0A
N2PhkeVeQ3A05tySu2zI/cGnTOPPJoDd7dQ6rxwWySr0kJG0rwyCLqjtyKYyfAKxnxV8K6YWgIkU
Z+tlzyegP1fpL7MRM5pcK+qmtTwF/L3LTej5mcCJqUEAQ3U7ortKp1tqHdlGvppKRyy8ducE9QMP
ckodCh4o+/X76qDYjZGljCVTNieGqqnJy1WOkAaSemJt9tmgsTlQyS/d3yEAumGvd5HSNa6aHFL6
XkXLUrPHJ9w9EyYMxCueZbOZUTSLQ2fpLdP00FVbSWpEIUdqMm8kAHaMGRBjeISz5ktvJT+QWmUL
5qn2bMo3DWUxjQQ8jv+U/xYi1lPcxu14ZApdEyOMQ8epncqphpzOBT3b0Qc87lAXl4/f27FVLOFU
SEdCNrwWAprxqKh9A8nX2vknVoFViQ6AZGi4wXaqZHdm2htn03YWugJQvF2anWtoIFVPfbfMj6Bg
O5m4JXGOtpaCYcz86jXmquudpa0Njo9eDS76DpQq1p/CC0AdKNRpRb90wbaHAGFMjk63AsO7eqDz
AcHygz02zqwMegAV8TZJ9wPJ0OLms5GClxg1fZ9GZMFCaZVd6KZwRk/1/1q+I2JZwOpOBcTfcjD8
3+3jGu7Gq80xhrtgr+uk+gkI/+jC4+pSKvBUQ+go/OIwrYnOf/hSj2bmzaxSC/JSZcLsfwE4pW1Z
5qqJA2YuV8TvMIhkKWE0G11Px7hxVevkA+ubGFNYz3MsJLmY/EOxA5f+zCVsy0zIQrf396I7Vosb
zbdr4BzUqUlvPuk/m5FKlk5Yasl0k5oJY5UXebjEH8jTuGHw4jj4vhoaz/6+ihGcXX57f3/XSqqv
gMG18PbVBjQWGHaYh+V/FJAwgqdAJnq8PvpnYkhiXTx3bhxM20DPn6bq4bjS+1CVQqrTo4vMAp5n
0G/ygmi96q7K+uTJ8zuhaQlf5oTvUNj1OkVAu2mQ/UTWpZmRlKnC/RiXULS93/s3dR0ZMJ3D8K7Z
TQbalyoVZ/3l2vqzJEtov3p1rNKpwlMobkMna+FZGqFJLJ1rzhbyETX1KFQBs+k2P3rxTI3W+Cch
xTo8DWjEWoWUjqXF/5dFj+Vm0c5IH2RasKt99wlwVr+4lTEKVdgi6rmrj0D/S+dyjX/8HRWC5V4r
jrRIq4qBlZYfl5vwE3ShljLsGhu9mP4tgWk0h+O7DpitNJq/4CFSnYBEiPnyW1uWxPHks7ZTBQC8
S7CqtFnCfrcK59VHCYOv4xzSOevCK8ENpG7HesuIxHrjQesvSDXTnfU6QWE9MKOq4//g9HGSN0P6
ypc9hUGZ7fYXGcWwZxmIjlVwZyW15XuDJT8GZdpSPZNKcEd0y2YZqwBygnEidNIT2pNP8vaoQNAn
QQKAz/uhS/nijOMFC1rRkCDTJoXzTeMkW9qCBAgTrkJJGDFsiF+mYqikfik8P858iv+qk6ttimDN
vS8ZpzEOsywDL7PAgxRQqm2uGOeMmu6j4NK03p0YwaZ7CKmuS5G1W6lBGx0HE3SO5J5AhqgPO8fD
fqSRhqi4d8ervTmvNsUW6rJmwi8iLJpjV+X7zXBdVJ/iw4knaTsydey1zS+0NjKr6/tJp3BTWoaX
4lYhisAHaILc0GBcgZAE6ENXqFQ27c/G7GPm0HWaBsrVAfhfz4uCIqh9JSJlWGGIhyqH789/7Rgp
7ZTECgekcgzJsSKUbJKQitcp/XGzDNXCCUAgabCxNs+3AFSUB0yVtTIJRw74hdS2YZhbSkKD7Vgq
7ABMjBSAed/VcibAP6wTaSSbFSrm/NngmlyH/c6fQ0yk7E6DU8+eNcLsAHKgdiK2t1zCsh59ZupH
FI0Xx1KsPRUM8jKg3SuURVx8E7uYaOBv4Ldths7r3PWMY+t2RLOpFAebjKOkVEO3Pr+J1IR0mWzb
q+KRFjblfr1kOYsmAj/2ae+JxeXUot8TJV12fVDnW/sfu2+Uu7Wzzez67jvvgO7PcNG2r0Ylwvwx
6HiiQARHsDdHc5uJ5z62DEn/y+lXlnbohBd2dpyPLL9j+LszoyI+S2kuc19F1+ciafibQzY8V4Ey
nsEGaCmoiBnjNTNQlX7mWSLRjvtxOjoPlvwZUDHc+UrvbUGiNJN+Hge0hEywf+8gw44X28CtafNV
PpgQVxJVEnJhTjAd6JkOfTw0bwXbtFVeBPfxukoq99nGRtQv6ePK+wcl2dxvIxfpVhzgLEaXQ/Vp
a8g1jFNfdazQIXwiBD741fdZdYx1lfErJcuklLuIevwol9n2/l+gKkUULt3di/byY3sHfVzJ5i5n
vhJZWh3Jca563+mGoF/305UfZQbdXjyzDm4W/QYN4jOYkxdOfZbevIhOInJ7AKK9LO5F58N9BOR0
CKh1vszmpnbrgB4K22e0UneAhE6aycXXY7JU5Y0ojKF14cMeOwXdT5Rc9bYeR+WMXYOIDFG9SiKP
IRwF6hNbvowNc8nKWDwIksyoTS0MHNPMNet8i2KXdj7uNi6tNXNQPDfDy12dz+zjbkRbsTT+wMvM
QLqOHvFkUNO0fXoKMazd81LAidz9oSl2ni/CNeL3DelMdXlXPLZQWx0sl+xVlos5sJ0hJ/j9pdel
jPu4bcYmu+dVp33GyNm1W9M+NkY3akPKY4sEe16hIsgFotObqEK2+XISDi/qiX6/rLiHuShmzXvl
8sUtUacTvU7QOrTc92sA1TgbiFzOTDVsN+GG1omUohMGMwQv8tPDefizA9WGVIy/+1YNuwNQ6Ro+
wHschzINZqSAOSWjMHVKjFPjmp2GKTMy0gRsTp6uYPlE+FyXA81spfWo8jcGyQUjc84F9AOr+8iJ
UUT6Xt/ziG16diyjNj4jiavUUDkukfzCDURGB6TE/396E4E0cPldks/vEHe3wvMnbgc5BvuN+uJW
kROtPVgpkd9d7y4EvDwlTvnv0OxBzxoaD7v094aNnMtAB06Po0mGnMS79xg/k2gPKSMagq6cdY/1
kHRZp0CQl6NJ2k9SPf+cM/ePhcALHwLqH5CgOGQIT4kBwkGXtyEiBurVUCy04dk+fEeKen4Mk07s
5L7jLu8B1ROGyrK0iR2BgkzjUz6bTNXPgTKYDSXdGcmm8pDv0MZ435bqKwlQUHUvibH2Ldg/uw3F
S6SV+dD+TvS4QT+D1PDH9BXkGxViif4F5dCq0jQ1DHQCboUDJZQTBmeNvPT/7be/3lzQHB11F/Yb
eCyeKBvKEZ9EGJ9Zdm+qA1WUQQct0JBKONR9ux2FXG1PdFaImz0yFhgrbH6mpdmpIAidG5FIfTKH
fqjSruJZHV1kTk5pdMALAoNFco18PtSNPabZ9ggkpU34gmVKktIdL6EMa+rfW8y7QrpooeG5UtlT
UTnH3wjP3n2uWBgIh++dJQG/zgFLYyIQtC3fRv/sueryjsondmh+tOEfxqwLy/lHyWYq+n/wnm8Q
X0QfV6yT7ZHo6FZ0g8NakO0BqhufSjyPXS4I2eUZWKxG9tzaePIpvrUz6aK3Zn9df29w0Do2nf9A
r5cAOiO2VzxU6vcOS78qxANzdRaquM+/L3S+XSViAdKua/vKoL0yBKNZYouukfO8KqyVPocveQBc
bGPG50xL0BHGp0NPJdYqYRlaql2204kzoKk4MZq+OkeytlG1OYabhBz5z1EJ1DecjyvOJ2zOiSHV
UVp+Xk84WEjDxXPt+ETDDbxu57pBkv1W4YEcF+/OQewQCLku4zIbLa5dRg4N5ulmfOU/eKPaZhms
3Gx+02/vg14hx8lq5SerUnr7vzdYOExf86Vh61wj78+yH5IRDZA1ZJsCMi6I1s0RYDoIMhlya3Q9
msrdeZIlGtN4p7OmKivDMqLeK2PA80A960QnnnKoT/1FvEuR1QTVVk6/hAJBKx4cDOT+7GU4V1fC
rTd7mgDIoBR0Ny1OUTwFYP8S3CQNSfVTOiuKAgUwEaOtZf6lXw8BZxi03NrOWbcbEkvd/QlvUPKB
bpoOY2T6vnAietmknA3O714HXvtQ7AhUaQ5fgvXSdbbRB8mXcTie3jb2oVZdXhPrUMOO3IMXxHEU
BbPzTUJ0k2zLTf6YGJCT7KTOk3Mh0sW19yKxMlA8iNKxPhmN9eedCbc1U7D4Uq4aoTLyT4OMVBRu
/1MvBz/r3orkYvjfjrClO/n/KgRG0oBPy+a2K/5lDHukigw96YPklvv68fz/m5vLqTciwHlPJvTC
BDr8nS7eU9MKfz4ZBkvmbqCfsWpYOxXecBZD2YjefXK6SfwhL1ic3pCAE/yN9TJNzWUMCSML66Om
BKu+3zBD2yhDBOiYKYwXnZ957EEQMmqFmS3fAe03ref7nhPKvtPHlYv+zOgH+b95E3a0r0ieluz1
dWOA8L9Q7AUc+v+EiHNe38lEfO3BtT7uU2BGxXcIKGphdSurGBrMCt2d0b1NGL7zYGzKOiHXeZ7+
gPCcp/g/aSETcvtUuOCJAfLtPCri2OY120B9ehZFcaN73PGWuG9izNHHOn7p4PelMqMS0COORJAv
N2L1O8B5KILW6Llq5uyNXg+VDKyju3buFNksh6GUjDEA9+rLb5L10AvkQY2CXVxPCmKHCYqDMAW8
pct0pVQjXtwyg/e8JbN0Rd+LDYZwfwnY2cBfuzCkYnBYgM3MVeZJDpP0M7+aRxpO0hEJLajINBaB
axC7XVA9pYstBE6oxjKeNwfAUNFEyVAgQeTyU9geOA7JWnN8hg9T41AsPn1annZGx3oo9LfoiAjS
MieZZWLVz5Q6OgnbbYwg80kWcbZysIs9jEzR6WQJ/WuRpCv4Hl0Q+DQ2lckgSy3t2Y4shT6M6yg7
QYo5eCwGpNFEpn7/1gBcPm5ZF9FqmQP8cWfKuGL6obiXkv5siis3WLpwcMXYc1ajQvmNJ/JyVlBb
VZKN2D3lWz63J/kVIOvmU7HjC3wuetfNotWQprV8pOjcLvrqgEZjcQcV4ZBIOAbx+99IX2eKse7G
eVjRPP6J0IgKu9TX3YSR9xkgskvSW/jVM3r0pPTXz0xW9NWWx/Lz9aJexvGpEdGaIlVaJsrms8Wm
Ync7AsLc4XFa4GA9CU4XTiteB8xDqfsT79IOor1NoG3GjSPqsQKANU6tf1khz9aSLDFV8g9vhQBF
ccmh4hW9JB/LRiPVaCbVbYqBycpsqga7FOmZVIze2+dJNwlIRRhCPltUbfu4Pb6O/6196jS4bas5
8NubXzoIRAUmYpdDqZwOP15XZp4OWl5AJT8euvbVGnp9bjNaw5QqDRVQ6Wy+XF9XK4A5gLpHn1yQ
3vLpsYlYyce09Tp3Ydqo+2TZovq7Cv7dRkR2WGw+eINifbfE9kvIbvlzpjA+S/3v9+fsFFwVyQ8d
HTvfmGKDxtonf6Qd+eDEeIoGr+7Pup7nMpAVq97MIvevUFz2KtNb/NNx7GxOtOx6FP0jDARnuzp2
sDt/adPM0SceKHhMrxg5SlGKbM8h7btQ6MNBgAyeZdesF5pHBY4esDdJ3vrwDqiT0/rpF797edgY
uLK5yKcwtNx0HIYc2nilcDaQw9jMM5JsR2PGbZ3k5Mcj1qfuyDUAa1n4RpExo+O6mbRl1qfnZ5/a
lkxoYDVVJoxZIxdP9mLCD9HJf8K16zmXY77NAcKjDifezEH9n1w/hPPYQABWBZyTwVNQ2QWmq426
iKqm/6gLf2bL0C9dGcdC2kd63InmcHR7oaBGWaigNTdtILA1nT2m5M5T2rA7qzm9isokAvw4YVWF
yS5xM1ZsHFGH35O4/wxLRutLTb9KiqkHuNyqfB8CW+6dihxXjZvu08TKL+CRrj7YtgGIJv6advd8
32IWsNfJ2tHpKxyCPVSY3RvQC+fHC0eAL5zFQfFpymge5tPLR9sn43VLvMza46PxTtzTAeQTokHI
fKqupaqJsnhbVfcPGbJCFpQRSlNQEcfKVEOctnt6RxdcNzm2O35xQPbOVSiyVUkeOYrEOyhnA4c1
HDuLPI13kcn0Nh4jXMGEqzB4d+gGHbM0mG4z9wBL1La3wwmW2U3NcE/flPreFv7t5E7FGFt3GYRm
KF6FbMFE+JdA/julONdlancb1EL6NSh5/OxfsBcYtglpY1qXtIC5BawEtOWHFDQ952fM9E/t8Cps
Xp1q+5bdOecvqmEpvB2t/NmQdp1Qvf1MAvJ9CdENE6AJbq/E3py2CY6G6w5aoppigm5hyHoKDZ2U
ErjGnTv5nMw12rb8GZbSogJSKBp+Hx9KsBC6DyKg7Muy/JJ226x+uCW4DgPOdkbIqEf/vpYQVG8M
i/pgWTAzaw49863g0TjZbcz221LvnXSsI0gQNk5MyengF7L1Dm0C2SdiMYkvJ15iOzgX3Ug2CCom
CPB1uNe5vF2vqTpGsZRZ5s6qyS4JYpnx8RAAjY3UsEAe3CJxvLialP8GKrm9PKLU4sZ4DEiZtf83
A0MtUlRkfC48hQ2bQbNjYR+lvHPL5J/O6VyedcsK7aeNSWHbdffrf+t0ShGMBkqRP56RFvGC+w+P
AEz0nfMVkDvY91tFF45+Rctsot0BblnlzADTRAhlG/WnkxIpSp61yo9VLQYz1H9Rx27jitDk1ulL
S5dHaVsORGiyQwEQFA90N3xtbULKXvOJmvk//JP6AuyvND/vPKv8MUis8HG9UFhcpVb41OcKXtcF
WZy59Ng4i+hf5z6d5Ch2ZzDvoOdqK1KDs/mW6lzAGNwiAjda0GADPKtd1n27SDRswa96EYES8U0q
yeoispPJekrN9OE4q7JmMh5XAH0g+l8HGGIKbGOR5JINrD7iUjYKy46H2lNZ2hvB/uyjy0nisZBb
fE/kRPY2T/B0xmwn3ReZIYYFcjjrKWzG5K2gR/GZs+OINODcDXo1LxN17UpoFYFqoVjIz3zSmGEG
1lPI9og+WFc7VxrMnYorKF/m5m+chOXkkA1T5af9nN62BhsbfiagJaN0mYPnFsdkbCxXKkQ6FjTQ
NlcQlPVcxFmANgJm9GeRNVuEt05yRLxYL9ouup1szideHSt6X4JyGgFHgV+K3VMd/IuEeCtIR4Ih
Zimn7jjUaU1dJ47R139LcTSMP2rP79TfZ0JO38v2I32yFhb76yjZVT1IsUZ1tVu5YLE95FTEex0c
kDG13Gx4O9q/PbeDwmSesBmetDuNJJbuVPcHJq9EXg5loGry+vT3ztX9gC0WfbruA7D5BbQ3SjLs
w1ZN2xuGyV5iq6E+4XyBwGp6nkkMEKlLxScrVxnDVK8dNViennqxJhXKBx0HAhZcWnkwdYoSEcK6
8MRd2je5cINXO6jKcg72ad09EHrZ5H01umjVZDJuclmpqZyLFMLdH1IpMF5c0XdM4EwYoFGpguof
lgRLNYXkZKvNyISTKzNhjVEse5N5bJMz0cl7ZX9//2jOb/TwWRozep8GcHe/OclerUviX3fpacTC
8RNyg4kDr/fLxqkZGwIkBL8Xh8GGjRhdVEF07+wovS6ohnhCIq5J6uZFVyIIawMcdgO9zy3bFqp7
tmZU9Ox4q/WqsaanKUmOvpvQOwc8expnyfn2rMzPgmeFlVXIN3N/THPpErswYhsCa1FMeFy5VXpT
uwtOeznuQrFjjsgq2IQHGFq2PqUXDiCRxieiTYdYeoPUZe+7cT69v2CykUy+XN8eQGeIDtoxp/SX
pBscFUxZp7VV1qy33pUnUc7JOAeFPgmHBfq8fInZ3/QxvHG5TrDJMvCi7LvpxYIocu6gU0mKvxoq
yC6CQHiWfNBTHqkRr2dPLT2SWpWEfRePYydEze30TPNJhbPRAH5tE6wdrwL1cxzUMoPy/gNgTvA9
PX0GV/tMI8Y75b+3JS5h+gGVCeq0rV4qZhnMJPe1KpAlN7rWgdTKXoQyNrKRGZSE190mZiPC+270
CgGF7Dz1ioJsOtNl1ShR3s2LfjvKsgs7+mxISd3w6rTzTCf+XR3JdtPViBay4cB0NQSazvXu7zKm
HiqMtzU24XWOynBMfSdprwq6SmyC8BaoOWA4gpsUxlA+F4cnd4Um9GJ2PX9qxRc0VmEtTfy6MznL
Z3q89spHmhaSMzk8vRpwyzI87f8OJmRbYC4yydAf/G2HglAX2Whz63rpSPwExo7VSW9+DC6CizbA
V9BFl7ow3YradlNQhbSSSaV2JdqtDD50xWcqJXKdDbNdVfbJy9lFvFo0Ry8oXzo0bHk0O4HcDnfm
wv592+wyFI0cxPJX9H6hDKpUsojI+/L3Xuf0wuDVVtB6y96J7WyvVeDT6Xzunq61JJSeOH/S/YwO
XIkVbteDftEXkA4JeyvJ9TMt9L3cNonsGPuj6hEPTmQIXaaQpacrG1eWoHcMXfOBzg2K/Z8c3s+9
hJetp3wCVtUXQP3BxymWiq6y3CLiVXW0meY2cNIh/aebZ0abgVK1azIlTa6zqypXqg7xwySu5adN
+xD7tQEBfFJIPQBgqOmNGFdTCU4yyP/ztpnGrwJKs/w/d5EZ7PJsX2etFJal8W4/qPQXBLtshSWY
vAYOTcL2imjVtkVlsjU09O7YfxCJs8qGkIZih4oqgslXjZ7RT3XqV0pGTwcrs2VwdmC5mI/98MTQ
kAuSHf3hOulr+8eO/B7s97GV97oUpWssL5sqLfaG7kPnFsI+qIupRtgMYrUED9i8QM70VB2O/s4V
oCGLfRQKYF/afl18bIox+CKeuefZdwEF9hbqSjadKk598zuHlnG8ergy3DwsrT+qXOvuLq7ZNkhT
JlypT2vTv4x4MgRcgjsjvGycH+XM4WLcscJoCsIF0t49mKhmnhWpWWQ75tmF87Ec2CkVt3XzWSU3
/+Yrvjmh9ZVSP5PJnhgRith2G1qhjtzJxsu6yAtRjKbPvvEhDsLvfdma/jAMG785cpNcjKi1/+3w
PWdIzaC4sHrgWVZRi06p6a+vP/FWIIqgydyJV/jzFY/5tcpsW7XxwO4titcRPP7kGxvGsd7QPacr
Vn67LJcJwJBESVJOFpKdWZviLv8dVm56/u3uUFmuzsgfgK7b9im41VgqL2m2mWyYKbVn6P1CcyP/
9Ozbm4HVHzTu5pmKOLZPY2d89rJXLu9KtUI5T5eNXP9SyMHnMGh2z3ibF19C2JMSB8z7RyhPz8cm
4pgd9zsvFxLe7qUTyh6Me3zzr2V3mg1GwhTCCNSI80H7cX+PxBoSMOJT4Jv1zck8lIKvsQAkVC+w
MscVEX91TKe90q5/sv9vZAJs6DlhvdtvcMoah7Fyhejy4rPxq+v7VNqE4JHcsSBx9U7UAYaXKsC4
ZvNvYv1cDapfNHLpJDHtJtpy6oEkqEoprwgC++73s0OzbH8sgvnxUFbrMoWocdgcmKkF7HIYU219
AuVyPdg0JMuZ/71UhWkssu8jHDeSdaN8YkYBfs6AVrpCmPokak3eXiPmVZ+x8ufvTQOpLCErVgiz
mJjanfanQPW+ANkqIrNjFXhUUCtw+nVIDl8rY0eVk8XV+/WiPwZGEjgsgpXUjZdO7ICjGZLPXF+V
SH1c4Bw4ZYhls5/PtCPUZzZb85rzMhMev6s/73VliFSG1lKyyJC/axoGer6gEWSbzW7JTwgzb1k8
cWKHiS4SRU66PJY3uqrlX/kpY0UvFx6xG73LPHjLMY3FpArjchKQLLy48wnDrwNMKbdbv7y6wbkG
QsVsB3dr11l5W4p3xkNEZCH2XyO4fQKFHvg+5IfSSWhFFRsnjvvb7k3U6ToJPF02AMR5gu2sWnjh
7TncQVhJ2ZnqczEw5ivcNLD7Ebjv5KR4+JZOY9OUZIsIXGu2abqyrClLK+1ovfcptIXm9SSopS0H
5OrnDfy0bL0tpc8tn7jyx+XBl4P9BzHnMrkGt6dSzQPn3ipCbAdmZHiNLgz4QeqLRgaPARblqSs0
ogIgXCbS9ztrd63jG28HE+tuCuwf8wC7sNxxpAPKW/ImEYyE782K4vahGzRV0OFloZ0odGZ95hF9
bOP/0h7nQMJOrR8Swp1aHhK8kTIVgISFMgk8+pldzEBnXOb61TveH8BW1wUHZALeUzzV46C5aMUi
kOyo+RM2ogZSfOz3sKQXKoF/ll4pc3khZJRTs+/De7hLufdIzvQAfPFKzH6DvCJbnja7rTPlYbhF
BQMUfgd/jCXDbzwPyx/33/lye8J/qqb365uUDC2tPBZ8ZZy8yRsKcqfIrF6UDvYJB5avLhpxwiqk
SDAokaSplgnR1keqiMhN2qalNVPu/MwxNZPq0cHOHZc2Vua7c3KmOVTf3A/IRfdfRsM5dxOnDfSk
cfNBn+RuHT4BbrUB5Sl3JpXOX1WqG8KNFCyv+DcfmudCAzqGFLbuYSPFlqQiiGhd2sofLN90PmQp
0bIfQ62syJILp6bLJGKDdQYl0Z+He46cCFzVrYGKyQeLv/aravKS3cXrv/UHbH2seWQSLo8gkXxp
9cWVFAT1djThuaXD63g5am59hM0dWroCHRGw5BHbm3tX3CHTzMLIOadQnSJBx/827h0VgxDi476b
SNtFPiMS2pMjN5LuzfWu4QzoMcXtj9J6vUpVKsFcnT+X/k0yw/mKHNN1NWOKa0HkovJTGmRN7Cda
beuG0WhzyDC53fsRik+1sl84tlKIKJ9PVTgQZYU2m5rKOQOM5VaqZfX5wb4iCaICGlp3Zh/Nqws3
Y6Q3w1rnuUKPy8Gh4TWU5/j+D5CiDSrRCDHBNONquSehBIh5nQbs9f4J3jrJW6JuiAcTAOzmGB5s
8eRJIYMkHieAyQUtADHoDkhXQ62vgvfVAssfGx8qElDK7xAVHFf1+zdjzVxzJVhBGmvmCcb1iNRB
u+pPTpPRsoEGVbK1RCX+flzZPmDqaSfJ/GiIspZ2XikjQG0Pc9hKFIgWNUrk2nC5CgAiAkKO65yq
MS05fWAoATgJUnT/kySfWZFVbg0nW6kQ4FjESQZzZHb0aZZ2ojWTuqI4IoS/+zUpXbb9WdKctu2R
vmQU5VDZq72EB4T3U1XKOqsMu+F/Rt2eT8el/DEXQSkDDLHFFethVRv2d99kDyxZ7TxWWcFgI2WZ
zXA8P+6W98N80/oKNbUnYJokDGwM4n00+4DcbFXLE++IWQ6TFlTCedfBsx0Wd3anlctyZs7fUFgO
PvVStqZGO0UOgbheJYH135O3hC1imythAKpcvyavNtmQEdTHlzNPw227xr5fQ+qlXm9O5odHrvnE
FUng+gbxGHf1xwJ6tnyiywAn1fFlXLuGdMnA929AKTyAUj1Vjbd7C7p4O0MMugDUt2sFIpV2aAx3
55XZdfyKOAUixG/LYDCsfgoQD5Nka7iMilbrQxagk3P/DSDjWOvZUk7z8RzJqTaeQY3YVWjOer/3
LLtZTx8BOnHTpF2/3UI40tzGgrXm7Y3K+m664oIU7aI3gCzwV+weRvwTXTehAr64paVhk/Ao4r+1
vgBuf321EpPq2QaB3cBAWXrfQ2TUx5Sxf0gRSF7IE3roeRq3GIrm4FjTnKdkZS4HclVDIGYYBd9B
9lchsuQUgz/byjQ3judC0SPFDGtRHhGpPaAs1R5vbb/G1Aw0lTQFjswsfnWm0dh4/GxD/WayYFT0
FjjkDgZ9nvbH1uZA0bL4spDZ/muye+tT/2tPXvG3Wn/VG/wX5Olc9Zr1sHnd9ufgKmGX6mGwadDO
1VkXfyrBleRiuGjfL7ZHxoSV66c7PtDCa6lOQ5Gv8lrIcUXXzq8uD5R2lYJxeH2wybpxQulrI534
K2QLI+m9mIZOoe2j8exuFDoauZ8P2ATbRptVn6Z5qcKSKErlZpeg+Yw1n51swk4bKGururaXgW6a
6CKai7cAcUoJeH4nx6RlYtvQQRY+cJK/oS1Thuaz+2qaOULbbQm47hAgXL53u0Bg2h7aSWcaSh+G
fMimBZ1VI4DX237xMqbJtHiQlKUmdDtRouupkb9XtQBV8M5DnvVHRK1/gehNjZRQIiKDFeo1ad6H
doUTG5Q6HmDa9+eu21u/xixP0OXUOm0H0xy8/SBzYaXey44BDpLIUVSbPSxEYhLbk4IEFz91Y5u+
FqLKP68lyK8luzPVFYjxdrJZdRUMo6mkkrCeyF9kVLtnORqc8zdK9qtY/9a0C0mvKlxwXjF7KcG7
Pr0lsu8ECe8js9gQdbFptqbA7+YDZM5G7OpmTEHNDgOQ5EgWvhHOYCmv0xNzq9k7ibVIAJwmZ8cT
fKN6uabTTfk3aGgPu6Puxb7pC05AMGcNPB/H9JSYcuGhnbzIFdBDDl0MY/Ol/cWW30YzPSi9YW6T
ccPtBHf/Y8LzrO41JcW+zfY7qSSsNlwQUYvJix2hJfHOoIEWObUpITTqf6oxfcD9OkJi8vsxbLtR
gvWGgbhrXF/e4DWN/LLrwg7fklB+NYtPL9DCQf8yghBAPL/s3Pen8v8gXF0Vbsj/jWKNbm8Q99M6
UTWrZih2CGdOjTIPSq+C4V9p2R2e53YnuVOqJTa3YLnFLyaz/4B+xYQEBheS6ucJFxBZsQuVg4kN
w1KwvVnNo1TyFpUs7wkBIOtUQ1++YiXfiVwKRLoAISOdjcBQVc+kR50uYALGjqtWAQtCtUNrckEr
gj929+V9fU+APVYAlAo/th7q1LkpXIZ7x/JzLny9nSvbZhjWtCoknKe0J+Szgjnw3a/+R1dE3uPJ
onSBZ5nWIHX1yvp/abcdZOG4RknKet8z5KttaXskoHB7TL8gVWwSgai8Lr9p85tDT1cxRYXbVTZA
1qVS+DaqGL97j3isooAicgRKrNdKBVYZwCPl1m9piF6GEjjJ9dUqqwzsY+HeFgPaCsGb+P8piAuR
JeKPdxE4W2EEBRZicnNiK8o0dy8TwnTblaCfNTx1YF10hy6ZNEhS0czNhvmExurMoDAv1R2XG5kU
xLn49XMpYnmG/vcSdrEx52ldmqTGifrMydo1JM6quICUsrTEGPpIRcSjWHWRHDNvSm//E/1S1zwF
600dxBvpaODhqLLtBB2UetBG/yzpQuBlqoIqXhfzA/d/aVJCZtJqqwJtoYtyzH/FIAyix90od+jE
DhFCxMtbI76l35LJTg4riljMGSQ0IekIlIqDDp8w6HiOrpZ6/GURYG7oaSIOCG9tefz2Zgh7JsZj
fF3vZe6n7LquRPuN8l8MshEtqKamuSpMF5YCcnbSlKMXHYfYMOXDo/Iyniw2pjnI1hSvRjljCkUV
kQ9xE+4DO+qt1lpEtoOFWKGFJJENn3C9IjXWijaaE10N1DZ1Toapg1r6F4MQtpSnpDlXIoc4BSxM
eWBXQuGi88PGh62NQoIYai0+RM2HzDxqIsaQ3Sroz5jevnijSW5APy2VVG93YEpR8Dl8A+9KtI+W
RytfctRAWSerekMPlTt2qtTsSiw/5/go5SmJCVGgxmgQX6HQHQK/YOFW4YpTRoCCPIiXVSIIwkqv
WomuRkYnSYJV+sHBwq0Qf5d0Ucbh49VllvNoQ5dvEVfToJhMyEo+2BcDkhaNfrT8M3XjHxfbgn2a
wz5R6o3U21B7l33y94HC8NTrbSRZOj+qE3zbaVULUwDaO9pbbyIoxSjY3L5fqHded3hb6odWL0zL
YL8los7e0E1gfHUAP0LM52wBVG5/Fxs+xz2gNCK6sPR+4R2fzmof5P4yJ2/fPpvCZotyuUxdHFm6
tQ1NWLliHJUS5RJ0qtRQY5bsC53piDbZjoTZHbohJLIswYVVP3k9xH77lbKTz7+cPyfBU+tB6uaL
u3cmODOJgy1N82xGMKL7GnN17Ycd3p/sawoRhb0hXPI0ND6xuqJq9D2m+/jtKQafEL7dbZZvWeAV
wz9VN8y2MOft8LfCcEltDBnRcozyb+PCiA6UIDnCHNfyrZTXxuiIM0ujEF8j8YekS24pzS/7b4g4
Cv2VAgUnWLbUoKqvbWDXTzmtiL9lhGx5yUy3ka/LIQ9OiD+T1TteN2jnNPgXvj0A8XsJb6lDDwtg
i9qiLOZ9HHh6gA4MJzkxC86g8/Lw8mxuuu/hX0p5L+7XdX2STNbaeuJf95s6MaRqA/5PuMj/kC6h
9THaaGLEWnJ6wEHt1fYpmrGkW+SKWTolT99st3ecta3UOsmg8JOdG0dT6oOUqb76w6sY3oltM+em
Qlk0ByTZb8mIKxo6dZpfpCpzNgAWFHR/yXARpSP1MVhMN1qUbgRmQ6BG0HhdxDMyOzgECN9osSFN
T/29iPsg9yuQrF89oyiLdwaHrmv9Rq7G0I+xxcbDxHutDoLrMlr1//nDNj/WE/MVi3JOCg09ddMQ
OAFFcY2hud4MGk+mr5T9Z+e4k+jVOULtFk3nDtMvJjIDCFv050wnEPL0dFTl67eBDIuF5MZ1Aq99
N5xZ79rm6CMWYlvLFLysP60RDqofF7zv1IA4p8sTGU0LnQzTwNXCoFrLfoXOnZ6vXrR6PTixfu7U
YD0VY0zpvMr5LLIfwHPphMpkWc58uyWLyYBQ1mitHh9rKBrV/pcCJ9+/CsFSuS1ve+/i2bnZ8jas
UU14InkBQH88dw7GVTLPXkY5lkOrbErfbIwfHd1Ha1uUqetE1S8hTTtEqXFEUitE84aTtk/eG4dI
bIS65kqH49delLwCQ6jDaKEBAs3FwOhWT4I1uZzOhOHdRTvQ7zuTcEg9LnoXwvSn+yjfPS5xSOUT
/qgMo01AJWz/eFor5SDvO9PtvA6bGx7ZpCkVgKv7nv7DFiODISyrkulHRxcoJFxcThV2qxONh2fY
Vi1js1JpeNdjGfXowa4k29ijgf4SrA7NkkVzm8TLKg4Ny836UG4u752JXaiODLv9FQk7RWGMqFfK
/I73oo2UvuLup03lgxkfayOziDhp2aTI46u7lhcKLXeWoNX0EvrNu29iCeiuvaGK7qn0mgGGu5IT
9IJ7Q3ecOImDoW8iVvcaY1W4LD0DjO3usutwfjfLjhrra6/W6Y5FK92b7ZtQH3mmSPwR6syVzf8y
7oOdxSS9HVQv3u7rsca/qR9zg3FccVY06JCQCWysiow3Xnlv0AZQXslzdHfPi9DqfUcBDLc6khq3
EffqbrSjlFWxXc2qANVhT7NEH3wwyUPj5TyJcC9hT6+7CIpFoxtKDeOwakQhf4QPtlnAOaqF3AjC
FhFi3lMc1ArKg+xK+Rxtwpj2cctnHIRJwUfrHp74yYFTPpRZdn2/yewCiySfxZXBcYljROAJmu62
Cn0cMPph5JH9eHOzZ5HV1greAWR+7tGU5cNH8HDciMcft0ne5B4Vp3rBu3gUvvaL9K9aQYiexLZn
TCWGC3HjEVvz0u+7yUudSpKSU9qY6XGZzWQRycNHB+tOlh04vRvZHafojeZTwbX2Cf5yPjCRHLFW
ivGVS3NfzZnemH2yy9eZI5W2iHvGKRcPl5v84VnO06l7yNgke1fNg0bdgq885DeIwhWuIUSnyLmA
uqmzbyiWeteGzDgRFpEkeqFu7hfLv8/nrdlffdd4hrpR31QqhXfjZwNAYNsbyYOBv0Zi6VcEUjru
G4c3rvfAItOb96qyocvNXg6t8a6JibymIcnDxEbJJYb5cOB8/HVL42qRpI+fP6YmOGfnHUfDiI3L
cXTQo+nl+HADCrRWeilq4vN6y69e+oQgB+yyOBpSAvKOB8Gfre4IbYLQSZqsOkMWkwn9YvGa94YT
x92WsmOmzjP+nCxWA9XK6l88TafSVKlj07T5IaXL692hmziFsuWi1owh09rhDUTfkhmSmKZe5mwn
C8L7X0YbKc1TDs8HDeEjcARJAPB8HLR3XM4ZHDtPq5X0wkPkODG+Q8e/ju5z56eU71VC1sLgIOTz
dXgjr/UjqM/4T/s4vt34ksK8gfwbN90or6wpg5/PvwN4O8NgSvOmtp0gWM4cieotn7NKMZrUiZ4g
w5ywTPnWpKRFNBE6Dqh1Iv3rQcuZfhq+iDhs1OAqdiwIVO0FCZHhUFudcwHboW0P/O0e0RnwkWKj
NqCsfzRN3McGtoggHxGGl77MYtj1Kfv/XhoSpMj32ND8MYOWeHdITuIO1vrbU5y1Cawth6MATXvN
jQhuTk5ihIW9E3i48/spOlviBQvF6q4AotBwO42llUtHzqPrMYvYypfWLSLES4CskjTs3DGCAsLJ
X+CKhgvtd3hGhxa6V73gEoTYOcApzDBLgfQ8An9u7DBigk/pL/uGkPyszwo6rE8ILVuuJl+8GXWp
voczZDKmhkpxfoTeUN/XF49NZetNrSykSZHPfJpFm6TyBl792afgrB3eGNh8q2LQGsRK1rRrZbS9
Z/qf8rJIUAxOg4iO2o1i92kk01qCPRZ+3difBsmrb2pB1bvU9ShE83fjbOXzusPOXvZtXXeRd4Zq
GtBbttTgkcCmTjH04rBX72GCtS2TdLL6dd5FuTf8oBzcidCOurHEeSRcBXNXlP06SuNjIA8db5h5
NW9pma75kOPmFwVNrMKVFVIs5rZZVA7v1+i8g4J1BbKc9Me1vs/74UkMr973CIrXxfhlRi9/Lq90
xEDKhg+0XFoa5cK8EC1xXbJMaTJFm+V8osA3RCdWz7npm1ptFmk7s1c2DVGwM56YJEIqFYUYeC1+
6GiTk/NYxLo/bvDwU0YsDEMzzykxgv/c6vFSYnXP7564h0py0+fbxU3WXgAXFZw5cM6u0qzyj6Xh
sE+I4BERBbmwQoyny2ZQjt+O/F/6qnJOSAH8q08XTwC74aq/Avya46Ttg73gnrUd/+0R0PyMKZsm
DmmRj1YTvCvTvy/QT7fLeW0hd4lisfpwKU0JrqCrMLbElkP79sk/ArDrxiC43fs5e5XzfBWieDD/
/DBx8i3vsOiI5XVKpmsHUBvRA7yN2AXyNex5N6LPBp1XffSIS7Nn8oRUodY2s7Jgqz69O/1bHfZh
FW41f4V7gvO1Z6vMDrC2SMujvwbA24nTmuHr5sZBNXRLZ5x16ImH8KuMpDzHnFyCTHdOBiiUFDDI
DI6A1417TSD1DnVi6lPnyuau2SSh03Mj+h9eTO0RhqCUDz6t/E5/yFLGu/UMMNrvi1iLwSqsM3ch
weX9hSkK12dhKNUjQH4p+HAHfX5a+KNILyP9We7rYeoKF1qpMAA6tLru5HQfHI3im5k3qxFNYNJf
DXbzRYSdXB8ZwLz0p6ZrTc5kthbSASC0QaoPDmn082gNEfip1dh3RqNO+saI7SE9DEyopJdf3a4f
Opqu5e/VqzQZ2f7GYqjl1MVssnL472EV0NTjF4CSx5IIvSeLuvdi+GkIbPxG0hhOSqmahO+afvlO
r60E6XsZ/UnHiXOJZgbW38Crf36oNdsGC52ibNsKDPXEAQyD7qGp5GRezZLDmDasiTmKWA5t2X7G
nS5yQZpy5BGErCjTZucSYf3X52DpQ/R/NqjjqDc8JzJTe7HzqdoDuf5qySIriiPcMoViyf6f2mJt
xibE3+tfAmQj4txw/VCdrWmVmkcUs3vPj3e6WSV+EHzKppYUvFspzpij6Sb5DhfA3TGvL2DVqyrR
W02xaRwDgyoSymbGmsI7FuiU1pqktGNLkfQzAzciDivGuTX8+8t4uzOiir71QFZu0oX91rTf7ewQ
IZdi4g7XOBkzz1jLRI4css1FUhcG3C8RA2aWhR+QdZUZMynJdeiAI4ASMDiAMnXUvyQs9tA/8qII
8qgdkbuzqUCWyLxba6jHUTd6DKpk40efJ6v4oUeNkHRtRHQAdAoFXb4l/3w0Z+mjUR0QGA8TayG1
bYpoMwcpg7LzW99SDEO9yyaj4uosgLJ4BxlvInFklr0l6/iSV5DlXz5vIGmQidA6hGBthBGlRzqV
+BPpX9crCr7Tcjmb1obDyJrW+/bRihgfNLXpQPggFPmhLzBV0E+cxM57+nzT/Fp6Ayy2F5V7L6WC
XPSLmaJ29LMt/nGA0V2YX0RWsb8MBCpBZJo5wFkt6VaLCSavLwVUlhzfOPtTVrlczt4nTHJtNVSt
flMmU81kZ/mQYHv3jE4ptTW9Un0eqd1m0Oy17KM/wJltsN1LFg7suEgUk99kFCs4rDdLXZR+R1IK
+j7+vLI3unDogwXLh3eNeOtW4v+oZOELEsOljjyCXVP7bu9koz+2szrLYNq1BTWWR+9ZMONv09VB
uyqS78welcp5/aq4BxuHIQiz2l1vcjMCrH2AoAQdtZMlxYIsxhJ1CvL+NrSVKMnn8fmrXqSmNHDI
SovbRLpy6ItfPgU8rgJvqT4q3nXSRhaHSF3U3RAzGccpjVkNu3A1ehm8m84dALkBR27allrTDaxR
vzDII4Xp7hXYb+mTPmUt+k5MqCkCaNWzxkmFcnflymz0O3flAh8BymiV+ZSDVglOf6SYORCnN+w7
9/ur1L2iJ8Yo8gPrTXxZWAnK9XF6/pDPPGHoi4H4eMOs+LJlwRPauuLe0EHThbD/e66VIhqa5WD1
hnSMc4yzWSlsvKrJW/IWeEt6yPRGl7MnLVSL3WejcJbH1I7xZRGHWeK+LhOq9XhKrc7q0ftCP6B9
nLqr7PbK/iuRtAv7nUw2YvjFqzZE7ghhZu7/ZT56wNVW2sqheajVMHhFxIQbCTqHCxhNDiR6S3dv
XUjG05L/GsX78CEzt7K6yAiujOTM7p8zcMlB8XoB1ERkIdAUseKgUOV7jamyoPCaV9+qOZI2wpRS
WKMCPL0s259svQrwRJ/EG49emdXMoj4kR7k9dF9A4FO8NcTyZGhu3N2cC98cbkn2pR+9fQwyo2Xr
+x3bXvpYf6eCNSOn4D982Lu2/txcnTEq3/4SrES805usF5B9n/SROL9JCCKJpabW4PzuTKomxZZ+
wpQicENSeFOvyTABIGWsuVCOJEgahHoKhEokzxLBjt8glTBVsddXT4eJOFjOs2u0uIFfoKkfZqzV
286hk3g36B8tvcXh9D0TiVocrFly9fbe7rqMDL7pmZoZ5uaJ2lJWDl330qCubjSB+ow/EvEX4ceH
uuf7qZiCiYn4A3BwjBSZUIJMwLrPI86vpIz6kVJBYv9XAZ08yV90X/4l2xWUjYHz4V0Q7zDSne8Q
kETDN5Xw9MJvsadrUexqDy6FtYMrJP2FPYZ/VqvBeYgFbCdJxpRyv+6w/Suna1Ovnvl5hbkhS/CT
ZlN08yxMe2bbu+Fi+czrgDSQI4F0pGjV85XA42m5uhii+msIZDVq0qfqA7Ee/xV0/R4J0+7rW2/N
6tc/gtEMujssRM42AwoSYweh+Kk/rC2cv6q+lE6o+TWXw05qgABCVk+Rw3tCIMa0jKuaRiBuiz7N
OOzcbe8PWkVAoSm/kiHaxGHFNC6CakAgusj+w0ILJ+oQQO9D0V7DCuYE6pcIAtCNePayWgL4DrZC
D2OCSyCHP+HqS1svv//Tda1wg7vQOBXgDluGb5DX+K9Do6S5oSgVmQ6bDOUb7w0GVuLKxALhrlpP
uTb+AD/ryJz3YLoluR/gqxlsiOrtBMiuy6Rox8Nv1PPMb8YmEHL3yrJ2ZZZvt0oBaRLo6WHh0BqM
k2SUfM/4ZR3ixlOgLiWX1B4mrmEMSVuvwFQugRNAKcyMWn0hMG0hpPbftyKRlEnwM1U5jvL1pdEg
FPLAmiBgoaf8ku4sljz/MF7Q82JxMhlAnTYR0V9mKkKsdQQT7q89E7ZwzWGsGMPiFo1w2V4iylMt
jRZUICgGqFgiZ+E4L7iukvvotnvFigw+IoRE6XCb0GW+N52DTnBB0CptncnYRlprHSOWSjfGOzNH
MYYDu0C/dFFZe7L/3F6lk4+Y798xUCODbr6QThI0TjUt3wHeO/1Q6lBD7Nfq+fQmVrFayl9fP5s7
RhIVSupWtHgVMIMl9kUHfFZczmteIidog2g/pv2F+OInM+8V5PlVKsXSNgPbvd24gx7UXiutL9tD
EhpOUYg8I2fo7CBIc7rX1f0ERg6CBb2sZufZIOLF2xoDlWdC++SbJND4ZquKClgl01fnc/XM3+ex
bHVh+0OlD+C1wwjsMVgYaASPjnyX3vviSv/wjb3UJyY9VuEJqPMMvQCs5gl2mM4z4N+4zz2VBhXI
rYV+eeeXeiCei0UxLTRdfqYE/JqKEVxepwAsnPBYONyHc7Vvwo7G88MWNOH8ebYRXCspQNso2nt/
cnJsdOpBvfPvF7bZ+n4CQ5eFFGt7Y0y5OdIRRIVWhsiawQ8wc7SmfHHM8GyjHifFihs83bzyXjDX
WSw3KoZN8PVjKiuPQrrLVqDLxlEEBJ8OeJZgKiLPvrQU/0fI3R+dmtX+C7BqTIWPx2C8mFo62R5+
WtMA8HZvr3C1Ob1u6s+LWKOkdMapxPOmPfFlcgI/yNCiBfpixsW//iFqfoHlE74afE8bAPMaXwTq
xSUf5hw8Lj3Bmoy1OlehSKC3g8kKFBAzRl2w9CMyyEbapt5jkpd4w1Gbb0acGSiOsH54BddH9dHy
zNMeDx38rY05bGU0mIK/9knOrFQMJA9FWdTpBdap8L0QTvzEKiO1C7vAO5exZ7Vm46b3jMSGqbdE
MuozEgimj1oH5s1OVdhjrvxNxiYyDrRZxtHNG065HZ9xb325gHKsnfXFW2AYGLnE0fFYeGtupgCb
bpGfRrkNbmv3os3tbvSmp56n35867DJnZrh18kbQW8EoEtA5ZgYlSJ7UlNEwSwh3msHllSdqBt8g
+odKnLInEKbQFfU70CUROk48zeLBksHi6jwgSnYltkcXFRlbmV+5Q6NRS0Hw8YO3nCFuisQszdcg
7a6z5l88WjmhMBos41aC++5Uf4Xpx6cg17vL+LVdmXCRiSglzryO5CaNBPzwU13HsB+HrJqg+igZ
sTunT57uavaziN8ZQWtB4pu6nRavkhNYnMopfY9pZp0yfbExiumdT+m2k5koYa0Tz0eMbNyuGExW
PSRZhvN1Laql5L+c26utvxdaydWVM/t0nZES2ZydNGNuZPah1C0Xn55uHEchtw9c+ICDl5oDOEcJ
ELKQqSmtVEcsIV3pOXSNBQHZ985OAJCKeAZUZYQ5VoBHh3wfXRGbrgCPYqgLXiFBNutRpRyQMm0d
p60JT/Siow7cunnuVrQtR3VJ8ZEpd2ia9UtsW1wN2NIoqX6LI4e6Xs8pl9TFd8hXGspf+1TvpRnL
Prytywbn4uWQu2e6Lk3umFFW79ZZclDircDFJKV7pDf0AXa2h2+WGEaATIayEsoAL+Wd6MwLmshu
ddc/BhrjBRkDQ0pCzfne+pRH6IG1yKseXKWO/R2NsEHhqaxWVr6vJQj32AbWwZ3/CZmY2KqWJJon
8xtoqlgjnvWKBAuZ1knoxHL8/KtfaFNhNpcdy/4OijmL3F8Uf6b9HFJCiE9Qg3KGwySZiMiQ9APg
afzoPj2WjdkHjMj89WBwypmBabfcV7jilocS1j398MxxxormwzqVLrklNe0jolj58PSm6MjDUxLd
jGR6UI22lewEW5u+PSxXcTrVDDZjuuV9b3OJ5xWw+M/7KVRHTPZ6IsmrXX8NJSHIG1r9y/sqqAJR
2Xc2cyHO6dQJHOoMlm5q5RN+FrV7Bw86ypCP3Ss3xcBsbVV2xfSysekbbTfuav/Q2TTFzCwiMxS/
Xia1JXnb0VIQ1n+nHyjQcCf+RhdemSDeOhVW3/HJWMPM8w5R9FCXJnX6B8657jC05MrYS9Hnq/R1
MnrAT83et5MWwPOdCJnSxvt9ZbBdBoGXipLSPxsi7i69cPz0D6UR5SD1O1BJL/HWwcLiya4bJLHP
Lz6dKiqwtv6+ggW4WO+ufV6wo0rEYB3tXIkWChwlx7oARKs4IpR+vCsXkLNag/b/zmltgx9BzgAr
tQ9XhMuF3wHzMh7bG3NuZYy5lqJ+oPEu0qQqHu5HhfDSToYdqqJwhTaih0nMdOj8Xkgj0HWiaZu1
XAbVVWa2BurpB84YLti8cXhdRGPulSnq3Lbk2XFGaj+HrKR8DByIMsmCoibKQZbnstRBAuU63vxV
Feb0kjYNFlICUF9dIkhKCg6ydMbt31WOOPw0wXlbIwuMjdIMGSHPNMr0/+fdVTlMwsuhXDs7e9N5
/fJ4LchbAPkV9fQdc+iTgB5wCWDj3bs620pHej+RTqqWPm9iZdho7So6rY7AuDYzkswiQlpc1ze1
ZYRH3va/oq+2eJBRvp52Byy2CltIKLEusaZ/Gm51BCCjFaQSSbuDAYxPlNu2ZU6nI7fYM0qFud0N
+FG5nH3pUAjqQVs9V0/SR59ryQAVy6KQKA402kScSgn8JxFgxWxsneK+FbcredKDH3d0OWDa1u7e
5qwhkddCo5F/F/EIywbeP3XUSa06N8eReCRQxNojw/+DQ15Hh4RWbZpTLdRxHNE5vJUFfgbZEjhW
wlNeuy5w71YS58ad5X0g+0uBq+lxqZ06DZgWYdH2p7CxyhisQo+ih5pKF271No/vsuUuNWvbTnVm
7lOvBdg2fbESk69CZaZLHWGlYjmfiTRcKu2/xb8ojmPmtDEBC+Kxp1MO3Kjn1v2WcqWqXN6acoaj
fiwlp2Fhc9lqNRQcJW/L9Cc8ttuesU0yMuQLZkyyQJUmf4C9BYj8ZzAlRHVbSW4CXgW64Lu6GiiI
ygJL7lBM+QPgeVXos6QFtDCUB9Xq5LNg9Lm7Cy/YLmCxdMEeyQE6fQkLJx3vd51CWUlcqq3n8bx8
kmvIiv1v9vcRL0Yl4n3bxNdgONWx5zr4MG6jCpf497W0QaTz2PKXj33RvhsKKhgxyzQC6RPAHeV5
LhE7bz7myUK8VD9a2GUHfowO/CFDwsfB2hsZ6jwtzVdwhBYwHSpK3DHzEkZhXEkVAuKWh4kQPduR
VbusifDPs8cRk0rFlrKT3nlUHZNn9DYrJeHxjz6k1+fjCZSjTleToXuWi1T2h6orlmfMvfVHZRtJ
XqBZqMxt5ukvadnhrYzq+LGL+QIyTTPmsQQc8iIQ3F1TtJjNqZv9PDlnLfE8/DvLGK2b3fNHk0tE
Ol3/YMHm2yH957ssvSgmLcvn1clhPBi1daO0pPY5YtHDxccCmiasJPu/PNUuxfJRxHc2N4Ur50sh
2XiuYJtqTUEUlM7r1HsnCuVC4r1Fo9u1Zn16WXOxDldAJT1uTXS6tIKSBZ9X8XMH7WX7MvwbbgmL
XS8TOvPcPFSVzlOrwgSKUk04Dr8ACdlZJTdbB/q2VqDez6tSxzOGCKAQQBCp0FPF1BCw/zOc5IFX
zyZ9Mui7BcSI7nJCJOMjcFv1eBEUJRmJTtZF7ObT9xFW/8Wf3eMIhbBKHceKvsRyQ6mIWonffqZ9
0sKcNSHDPn6lPXggZ7Mqn9HkmI/pZlajGwGopvJ+twuUcYZ0AYalaDW4JtNwNYn3fwh/jhsn0Fjd
0vL0TwkTUDYqW/Uvcy4bwu2JGnZX0357Pd8p8F066GwN44gMgk+GZuifV4ljGy6vJUKdJ96MyQac
T9SCLYE9ArchLpbTYUPF0OEr0bxU+guM2XC7gkTl6t+rXEjEiYaO9ScY1wGNS76M1zaG/juJdbuY
9KDjeiMHtwVu9Od3lCjYI/EU/sjGeQji9rUcMMgUCunXKu7R26djihva4gXW0tPbuhQQaVmaSavK
MqR8OjWhN73141CaSXayNzbICV8LciDdhq6Za0Y6U5PZwPQ4cGhefFWCSoUKsR47UEFUaLtETQSo
TGpWH/l/H5NSkCMChyZf15P2YMm0Td5ddUmUFHjhbDqTbX692rRj1lv4LGrg17ws2vV1p7aL7sPI
B98ZovBGdPrLI1er2GFSSOFGMjXT7rm3r4sqpN58dmzcOGMpW4PRhoxk/RkVor1HuNlcGsZ6qrfD
j9GB9EWaGDqevKuqtMwfbKsPRdoskZdXqUT5ARxKySNEvkaeI5lYtdDCOm0wCjln5SZ0ruFQTEvd
VnD2BGNxa5Gl+CjcwATYp+yJoE4MoWppJCxBoZnY6cntQizxUEgY8LCt+CXWA40B1lqwCS3fJpvv
vjqRw9Cmfal8Wsro/cWc3Pjp1VU6jZAbNUX7teMo1y9Hr31oleBD5wa/uW8+XSuQWXO5h5pO8QsX
fpikQCTNAvt5ymDobA4IVn34FwQhaQ1aehpkRcON9Q7WGkZBUh/yHyVJdkoxG1f8a4ROBH/Tue2l
oSCGxH0hYyrfZ7InvTzITBFUF5IHFLw0+WNRDkCYwlewZfbihtKDW4nWGPK57fCy0f3e4FGJNXxJ
hN7iye/PBFbPUSWJORPTN1beikEbpjQ6lAI9BDw4Eam+vwMWn3j7KlzW9d2/AgOab5GLFD3iSIrD
NWUPThv+3Fz9jdUXaD0XJnto0Ew1R8cHdRLcXFHFAnT4wSxZ/JDJ0FY5XIPDHta6T1PSbKcb6iIO
pKKMWt5niFD4pHjtiRaJmC64wxFn9C6/jSng7xvecsUN+vSKVF0xPxdQ0edOSkimeVbJF/XXPj6q
VcyNQ4+vZZ0aYh5HpzW9uRODqLay3uTkLslJ9GF4xT7wOFsYi7cIhVFOtORdAkVEsVbZUk+3cLah
P0J+OU8XONXH4dJyG4v9Zls2O1vy2qI3yJNWN++1aQGmpsQ06KmrdaENIW/bdbzabSj7vGLtRake
YNeSfALxK963uzNp+Khbnl0imzwCG7/oD75rssWqCQuH32+aol5c46FkvtLvWDjPP2eKfeUMeCZm
k1bob5YcopFv+z/P0IMwppCICtNxbHrMMqIrURYnZTWc2z8FL13OBZuc8gO2TxJ1bYlMRKjNF9B7
FzZ2CnDHSGnpaudl25XlZCKsfXLXLN9nqWz1VJHFGdis5h0RXBX++DsG0plAw0Yc3abvPikiaUZS
sAjbR7BSZ9iEN/U7TlfACGBTXzWNjxI9LSkGjr7csxEwAy8zkDBWhTiCcDdFXqcljs3Z4r6AvzAC
r+TGDIgEThFztWgHIN15+oV8EWh54mqUzQeiFVXhFRYRQcy5ffTGOZQWJQbnKrZQ3ozz7AQ59ck2
JXXg3ex7hfkk2kNu9hr5HrR6sTGiylF4abETzwTgA0qYEs9JX2X0H9/Ezkf1QbznJ6uXjdfZutsP
gDl+qRj+9riJpaKFvG/FgnFB+1WowHqRMyZ6NBNb/vOb4gMA7EYq7zzEPCyzRdnVJCEMKB5Ybqs/
awxCrbAdCejOKJa7y+Bp47oGinyjOk/V9kSlGIHUrBn98IjPDwKt/7pt/CxlMxbOyzJ6EFLeNTNi
MVv/OJx9zmeLTauv5xUJf65FSpDXWSQv5p0XNxBruRNa1rOABlE0jyjE0mHWUAzhkIxGqwbCYbWG
w1234WZqXPpBMePelRLnu+PkAoz0p5KcQx7DZL54mUIINDWDPW9PSTjXP43/igWnX1Jsm9lkedhM
6fYECMEhPO2QdTKAdoQ6sefobgSamEYKjmNtAQsMadz7GWYtSKrdr9/224mg3nhF3Sgh9dSOCoaf
8tg6yAorleBhuPD7iUN4Ers1jdUQ6B769GLzw9JC8I3LcT6CC4vaOlYzZdoPhcMoPP5LZbsY53du
Yo4XEfgl0qiQVM2Ax2QP8M4BIpyR7PndNjCRFAuCntGa9fiViYpGLBVPnt+pdlTmudIAsTIEidch
MZxgAdIHLyooBjI6rpJEB277TuWWgr/s0BLxazKsrzSk59XbRckDLuJIXe7xH/9bVL8+kwPBP3E3
6XmeCgazEGsPMo3fJAcvJdbklkQRIIxusH++1dXVfxlibAzoj5I//koeeTBssaK+XWPeAMirnrmD
lrGlZAKvim0bRdUW/Q/xH7eQ6ZGEjcnj4HFJYPkn5L0Z+PdZSKL/H5jBhSV2ChdfGaoUTJgu/fQ/
kCox3pDK0RdlygKhQcuuZ+KhAa3px6Rs8o1k+3PuI7Vo2wQfceLFuw0SekB8gk2ppJhGyC70WhhZ
y9ly3feVek/oFJDvE8ZQgj36DWnN7brWp6r3Jkq4l7LpHAUdoYnfFPAVRBS3Gn6rMPWmBJRn02iR
g4C6Dcm1E1U3FF1I7cDfAZ7UUmZb5L/o9aInhVvwSgIIDkileyuyQNFRkTUZU6EGelZN20eq7CMF
Qz9vdoPOn7HL7w559qHipXa6A9l1Xj1CTL0TYJYZj/9YpIA1VzEIF/gON9myeqILRYKVIQC99/fL
T3RRe4pi4kt1iVStI6eIdOsVEZ/UNbjf5jc44jFQHSzxYGcyp6iOEqXFtV4OzqmTK2M8m4MdeSnT
e6dPbgwWpFWCtz6cRoaUPguBNQ+XKX6ukgDHiXdc2NsaLpF9Tyy1mwfL+UrJ/BEDuHNOIjC6b/ws
RCpI37mvD7WS40SjapLs2d7HaKKQ6WDWtAtV2XDJnSKGICvWmsqhjX1H54b4x7Oltn1xQrNodmVu
ljSa6uJG2H+qf9nJIwelaucXiq9NonGmTjfMNJHtNM77kJzt3e5SsEpS5AycGjcMA00BTNaGowz6
sR3KIZxtMcoXqgpMw42fvYfz9Akyovy5q1yfy9IfOMVw28bxYgy5oyYq4igWT5QOFlxFL9H5oKOB
deoNcVw/gcwhSv/8LMN3mJzxLe2RrL0qON3sZ601nV6YyiZENXE5fEZNYSeK3jpEkldEgUJtPCI8
EWOH5BWi+31BKFldmA6WKEFkJXUg8R7y6S1ps498jpij9SVfA9ghsA7dcy1mJk87nczUVyy4HFx8
suzRavC64UhkFZfEKbJOzs5WBAktcTG+iiaHXS7WaL7OfVAbqBXyNhs4B774Srs3741BRMPhp6O2
yawcngw+n9KN6QAo/P/CGhvFEEgaeUARcJ/KH8LG4Rs2HoZklfqDJpPwyPWkU9suz94D0+l34Rie
b4d71bMQ8bd9JTg8PYFlQQo6NaeZzvv6Z2WlM8znvgGLptussSbRz+hysTfTWkw3Ccu0uSFZau5X
lFDw4k6YX5LywbD+rvk2SD/xz3GoMQnTmzlwO7to4kb+NxA31K5irEbUEqLNJ5W/9RK5qZWGnh9O
43Yo4aXZ+1LatwZ/gKUyibdcaTpFmTHi4TdFp4Y5mO5snc5eUJpKxj44uKRat4CBIdBzLlKnVxCd
aHxQhWMB2LXXmkFV5/pV6aaGm7r8LIj8GTlLqiB3TxiNMlTZkfORTrBbiIqJ1XzW/5CEEYlbzEda
A4psaizXi32etRzOi+I+dilb48k2Z7mNpaY/4lR1cO+gKkm6vrozewe7H7Cekr6y87e2y13hCMfx
v5s+Y3JI9/c/uiayhuDBp5fLuNd21tWtTLMijcupDIgD3Iq/Gq5nt0JFlBun4jXFsmoTmUZGjtLF
xC02oeNqs/TYQFINRcWGduCRFmi4NlO1JO4Mc/YAHfTj5bbBE41ClOTg6wdc57g9VWOjMIEz50wq
Lynmm3qlymHSslG0pSiuD3YiiT2YVWIAWOogq5rKuBEwfmpTpL4R8zqrTGAFsV8jTxTE+RGUod4l
E1qsvIdhOrP9rnauQU2jx+dJYaumzRV6eQ0ZgItRjliAKAoF1gB5766jhrrlssBw25be1gxjz1Ts
Y1KWVBp5oQM+pnFScBcpYMWDR3EZDK8oJFqnA/3K2gqBDaBjU75noGCQnF+bi/ZgmbewRe35v+vp
3saAKybTPLC1QdQX7isWU6qfUPR4Wmi+tIYeoGYOyj7AxCByzVU55R7y0XDkLhIaRdzhAhH9cmyj
9tE3i9QJCBsnUYbiL/DWnd44WH7ZtRRagHx6/3KdeC+pVdgx31RMwEE9vFrJ15K3FeXIJxjxQZWl
SNVlbOadNkAZFbLeCo1M9di2pCk59dgjkpFtzeRk5+FN/W9oGqlLf/JBSGl0VMdsLEi0HQvaaGo/
kHNTprA1i+++POpNoA57eeuQmnxSnHk4jmP3dzjHl8SsIOPpcG2YKj7IAKlR3MU5JPCkSk+/orxU
io2sdIXerKZKs8W9TPNHFDuWnpXXWn5d0RdvEyYRZmmyUyTjSt/SmnGJg4nkd99/sEzAgdNLOMbp
YTFJMt4eSjv/I+krV2Tstjh/8SjA8Hcxb80Zp4AQlABjckZHx3oAO3T+mkNX/lV/OaWg9rq0kUXv
iYftpyK/8LbTyliV+EVEUT8CWEdYu4Ym7JJZ1JUpo7nhkV1uNvEvmnzCDupBr4Txhec7YiULqsdj
GWZZ+lKI3MDw8mr0hkDUtUBeQ9lrloVlWtKNviPXjDz01SYrV5ZaPupCERPW8cI4K7ux/TcpUED0
nNrVGf8bhX8g52DDHx/YJxReA1lGzirDtSGv8nX32j2GvlnH0rrY1KxhfPt/ldUHRiGz0vudr2Sw
fLeow3cSV+Uf2774LuC4OW7B+CSc+kN2QFKVVMi0ggwy1wyyvvvqZc7UiH1bwQzqJF7VOMTGnwob
W3QwxY7DGIIwpsLkk2HRpJyfFNFm4zRmqKEx1JpxlQ+U5+VE9jEPp4f6BRmmDm5Ouu1ztQweihAj
uVqFtIc0nYAGO/sG44HmHJUId+AlGMWEFAJv8xmLELUrb/NAocOq7kz4Wvu/oVkuo2tl5h+bB7V5
HlsP4HAQnLs2qjALLaw7JrHlWfcG4617sl+rzxxwAAR4UPA+tfK7R268fwk4hrQEpOL/4POJv33Y
fd4yoDdYMsiAUhheWXE4WWTMin8MDkZx8bdexmweZsUxOWvnlh5+2PtMZzyQjot2SyMHWElzrKDu
1UQ+uuFCv1dzqB3aVQyqzgoAkClkBSrVBX47nP8WXPEnpsnOvQCD7OIfJyfFu8ciW1BejcOpBmET
oEJC4Df7pN5NumS+NiX2XvbxPmTKiwBBrEuCKS4beqYNWH0bE9/sSgVsQhGV3C9C4/fbYcRX3+As
V+EtoboCEtJEkPycENPywSNCf4y6wFvA1hp3wQlwYt+pIAUMv7h9iZ6cSeOhMPg0pz99jej8FE82
Kpno0mqYSMH/JpksOv2pGqFSnRXXqX/J68LLsEwjBLhAEQHBOF33FW5qAmJwNnTifjx2yE8V9mYI
0lFunWobf7OPAYAb1I9nob10Qivp3dD0Vq5w5qNZXqFVzsm1A8RblSnMsSIpt5SEUvOyS6H88f81
Ar80ojaLI5SlJqBFed0l5MpZlsLVrWuRZrAL6Kjsk7dvpOAaFAZjXJJj5tYTAwy61GMWJmAVSXVf
jo/BxFR54AvQ0kQsw/MkDnR9nQ56Af2cnTVZccZKSvZ7Fpv72ZYW+GQbleBkGGfUIbqcmq/E8aSl
EcScukoOqGSPForgjLqQIZxuglpWQ6ZQ12ey6H/QUQfoPfBp19nK33I1n/ad2/zI0Xy+M43U0L97
p8jZv3YWd/wZTrt5DTgKMbvm/lE+BZiqxxaEJtvuHDgiuT+mFziAMNlJH7HwcAq9J2WPKtbS7qBp
030GMjbIdxdXqUZlIme+tClmNRYvx32cbzB0Oxiodh8RBtklLv3szHtSVM5ofrubQN6/JVTsNDIO
3gDExZsNxP4K17a6iSbWHmq56Md/lffq1xCNcQUE/NNAB3Tkj+XZiG3APaapap8SE/ZLyvKSNW3F
odcjhZ6fwtndfCs89m3LqVkktesfnhTGNqEk6wH6i3kpvv8zaLAsF5epA6OgN6iY8ViJ+N7bx6Gk
4fZ/Wwkm4O51utcomuZ9V8ymuHpUfFDCPGHHIC7PTKNLcm59Y3BQ8+gt3MmaMWTBjBd1xZfmqtTJ
teRHcL22MnbIX/zAyM5rhVqvDtZmU1ygRlLUSOWLVM3Z4C/jxPJUl1FEkjMIEIyZw8iG7ia05kVf
0ZEvWsnIrWBp/wdFTMHAW3S3/Mp3MoLe73Jt+Xdz10c3xSgquyTKEod+tRL7Lsc0fO03fgwGztYo
w0hOqVSVMnQHQKTQl7iPvWpVyIye9evNwVwh4suxsXYG23fNBjmZph5VnqaJ7sSliqNGl2ufxPwF
nPq/47/CRl4qdg/eC3D1vDgqQi201mPLSs81Jf1Fv52Vj8WWlmeD9HONk4H4fnvzQ+0XpKLCcNlN
FOsoaewTWxjJpskFlOX35uNnZP/CnML10sKHtD7ilASwhE2fPZ/mWef5qf07xYK3b7w9rojJSxcF
qGKRzVlAB7i00puEQ2CCybDPUyAdjBKXkb08m4fb9Xqqj+LSHp+iMzsXNyiey+27tlFJXMkwwZle
iK6IaEdyio0/mC3hTj0SXJnYQBuLCImEeu0HO1CBfI04VQNCGoMZSxUguw9ocnGe9pCsxpz0z85P
g8ln3hAntsGTkQfHqqqFiCEZwUuoK85lJS+pW+3PrHRv9k1NeEW/QoIuteY8JkcWzlPQnSW7EMK6
vGVOmfvNgf08Qo1nxFaHyUi0aHh2913haRenA4bE1i/wU9lkHJ/RrNG0YZpG2T15ryN5dm0l3GBj
hgEGrscafmU3ccgGFdeGBqjoDKR/tWS6W1tMokjNv36eSXl/fFSKR/XE08fIesOJfYGZ8YfUYyIf
nZafN1tRDWEj7ttj2H0LeHDUffQndJe0wWF3RyjV0BC0MSLmW0kqYpIcpEARLQzSHEQa0m0nGqTA
VzH7KhtwschRJbI8mjSjlinglZDXKwJ7rCsh2XTCRVt7TWkVS/7VjqeE5rzo4BskSRRoeHBzXCZf
UwZ1i/eSqU2/S7cTbEpjZbbwoKPkSK2yy7rt7EChNa5+aIiUGo74ANHLmQFOetB3KrFKp1fIGERH
XedCUvRt2cfzeWbiKNVSu8lgU6VUnIiRXC6BbTQqzmmxnTK3EekugLl0JIcxFIMI97X/OJSVdY/c
tSgI9ibSt4qapGPy2pSpPGiGv8z+WDIrsDnhhn39ORrTgUfprsR2lFrQhWT2CLdFbNpeDyCOqjSp
W1roue+Q7vtKyCXesHQzVQEuqKX+bBMdRcLmIQmWkm7PTwwHiGEQ0Msg+V2vPzoSRI+Qg9frlekW
xBh+kHkx7WWQHk8tzHrDbFhAiKZSv+SAYB/Wayh7/stP+rPyhnX8YpB7VFAfvJDcEZLOE1ca85en
SvDjVSnsFJZMDngqwicEpgXlMW4+9ngJxFxXZwrWYDex6Rl1l9vsXcsYdaChF643UM3YCY1aKLtc
tlOKiKglIL7at9njjzmN1YYu6//gv+j0cO8ps5C2NRQ6ZWdMRsbGy4HdZWypz6M7IuIWSRE+Lvjh
f/ivwYuOa5K5+bbIrX2BatMYqKeL0kHn1b8BrE++PlhXJsHJXtmdQdX5isauGLzgNn4+akC8FazV
ZDPHX+Ue4uHgNqyeGJ3nAJAnPMWk9xCgHOYLmRpJtHmOTl6OBzh6HEC8oTkrLTqXaudidBUINghj
trGUNAyk7ztXm1g3yKtCxnDoP57VAJnuInHd0TYphIVTkfbbrWBxsuG3gsCepdIb+J4aZfcTWyiQ
SKsEYMyESdk7lzXY1pzP24yT/inH/bxaccTS90AvKpIS5L5HKU7agnF873oL+WSoLb/xktI5Bz/i
/YMboRlPK283WtgQadWEuwv8iYBNAJsmQhjuSk0VdW4ldXOV4FI1xPze/ywZFVqvr15byukiqrgv
++6kuRfU6YmjLfbrm05OgnUMxY+7TSsPE7Vq9snK4fIa+oulEr40A0nZ3Y84XWdxgiqy8ZuNc0CV
Zux6hberAbgaJeLZLm3ngUU20x8hZbENcKz+nEyTPefO+z84xT0gk6+Uv/5JUwpyzNgvIa9Pj5ks
shTNNjrTr7v5ruCiPgdvNDgSgEsn9YkC8C6OLY6cRl3XhJm9Vslk+kn5raX/Z3GP2zT6iaTvu4LQ
0v+7WYMoUg+utkOb12Y3bCtA8fO7R+F00KOuBCWf2oyA8wgez6iuT+OYu62JMZUYxUj1kn8NUiK/
fAaVP5zoGO+Op8wNhTStH0JvOADbuU5HgkxbTWu3SFheVNz5HgJ7N/+7BF1IW5dJwMdv2HW3ljZq
H/9NJRk67k0GAMLlLGovukDs3OWqzIbuLWyqUhe4prjKIbwTdTIsYqr05TVHMX8Yr1C4JJ3MjoXT
CrugUCR45GfZO3YKiXOgCG25kcfZhuqnrBqWea/yh6smMjLTXz+y3IJkpN9nf5ucMXy7h4ndQB5n
9++mjANhjNa82xxMhSlEf5hvwD+1bLnIDybrqqMQA6rY0QMcujYS1+HIIP1P0Yk26z+AoW72dZHR
J7L+Gt7kWTPUHOhDnijcaTVCsX9ka83BZvHCh94IHaDnd7jfipJqi5V1QFawGL27Z8PZ6E9WPuXB
zjXr35qGOPfEtZRItR72lc2j7fRLwvFwDr0K1lyuMtYu3Z9aSn7pcHSIQyvmx6EjTyb4YlrFORtm
ML6L9cYrBFxZ0B/uL/XCsrSa+UMjuZkJInGHse66xoYOMB/pnpLco5kl6Bniqfe4JjThxQrHCFFt
LT6UZhQR8nNCgpFTqVMRCIdGWm9G8TwH6SpNOFQzru1p+9OWjLC9AEimFNoPHp2V4dJuQ/rhrMy/
rfBPd7pnge6GVk4NId8kUj8XjWEbftucLlagz5wsB2EimB4TX8mgkqNFpxqd2+z0T6TJj/3WKscn
Gr6v+Cd8CcDisqPCss9emFqG1oSSp9RhUVguD6W4PaYOOSnKVW1ztDMHMEzT/bEaXZsWMwg7dZYX
BalTCZPpEmr9RVxGcQIqrKRxBdh20ymaDVmTbvETpyrG7DLJmT74cAwTny69qWpqHYc7vAdb1RYy
T55ZAKHyi+NgvVTcEYdhXNRmdlnqGi0EwsKLxDl4CY7LXgozVOR/WQPniGweKOtaC25c8QPfUqXP
3MNeo/ZNzAx1VsynK433XSkdO5K58NQFcj8EtIwXNiJxHE+0TPAPtFWyLXXSBiZ3uZovs/S7ivVP
sLFGhsfMDd/M6vAid7WJKpfVwGPveeq9Gb2/QyG8U8E3XdmYHf5eT0EE8CYnZQKtJWErTFfKnQnn
e2mQX9C9/DXc145uKroMiHsql/LRk1mKM9N6O/39RnVtV92XZNltLOZ1AR8MHmRLeYqdBrq0l1xX
nNWFH9sJVvS+Bxxmjn0cwdZtsL6bpcnZRI62yECn6/zKv3xqztm29eR70HBflgdsUab4c793grPr
WNCI5VxL0Ct8h8L5qvos4aNp0HiuUS+mwDGFmVfTvoKYBHWrZvyaIGml9Iee3JOlHmdUmOT+zoXw
za5yZW6uVEsqqtp8bjjy4l6Q7I91l4UxFbEClO80kSXvxCRnBfI7e6oy6/cJDluizUEen+fXnhp/
utbUSOQ5FPRbg/9H0LHmEYdNiOYLbC16dEeGODoVFR0E+OCFS44Rq7jjrxnwTx5lsTEvCIvZ404O
fdj95gmj3uwgrziJbsHQV/XSP8u8J6JJ6D9ANfEm24oloChOt2yNkStcmSkcw1iIQMS/qZqKCOJ6
a45W1hLSRval3E41lT8Ezsy9OCZ0LwBv5J6WJ/fubNUgalHufdH6kq6tMzZ1s6OQ2DQwX/uNqPpd
cue9q+Eybk0n2pSVmS4cWYhFCtQvLGaE4vjKRZjLsJPEyP5050SKoUAWJPpNEjALQgJjiIkDJblC
tGI5ZCVV1rSbz4mnaVxMZjLHR4K2qFd09vOg12Y1tFw8s8Qs+6mK9kWQorI1tnPwMKtOSDvAmVpU
1c7uOJO6ZnOvaKlCtZ3mPg7EMpUB9j4BvilZphtCXNGnkJonZQf/Cb3k+PqE6qg2MkVcfTz6AKL8
67+Pe0vBQEHTAdRwbN4LH0Jb3heRbj/Y4qkIOU1KUaGT6Su23AC3a+BFOjhE93ZX1z+wAly41L9z
SB0/N2wCdf0YrfMz9dnNuvf7x9RnYtB+zCtbynyoaLrnG0ymxKvnSfEsKL2iH6cZMAEWJLmQrn6V
wrOfl14ecRwjdch8JZxcNPntRBi5iiLN4Apau1WLAa5DqCA2tUOS5fJSg2inCJUXVyA7AYR8Locn
3caTYoNi9s7m2zZshQxSdK+UbTDOYXsw++16FEsjACGxMt8EvtC9nEqbqt0OxL8A/LcqTqBhtFaA
IS9tEcn3JYXEAClTavW/VQSB6748uHKku7aMmI6VcAkg6pWH+yPRPiox14ZS0kCqYaCoNtfO3Zxv
mXk6GC1O3MVJ+FZor0Cd7srfavB/XulUEmCAVk/9+XuWa8kPDKzNIalw11+yRIoy6rRpUwLHeiki
sr3k4JzpE0VoBCdzvX4Bh4b0ZNonBEvOi2Ehock9f5rBbhOtZxCWyEZVzagzHjkrIaEu9STaIdJi
1WCtmT0wylyMNr88/M93UunQrsfMmqQ7aRQqOeQZJnbP+4vO4w9WMuytYINRWcxSHNeNTp5pPAzi
g9DrrOqfllfSAPUCCrZylIGyLyyY2zX4XzgM/ynf2aYweweyLPXk0WaBcpBpdU09I/nbiIkFp+Gb
YAvwQq+iDSv+FuxlZbTvtY9aPPZsMMoZiQatk0sxJu9X++rWcM8HGDFOtASe/fVtK4wEZaMLagGq
8wYgg4i7bW9DUGXxEAKMOre3tGB/KDHWnv8eX3YXugeBte23f1/J1DMWUbMiflAf3+DmtfZHB21t
eSR92VLxexqYjJRxeyu+JBa7FRreF39eD8blpaAxpbxVofUt9IddfuNmRuZyk462NPC9wB41ztAs
9vgLlT8RKMR9eDlirEUQQUOhSkloyvriD+0lmBXk7HemlBPNrIO6BowXsfjJYtbWJl5NGaHScQqt
AXHO7Zcz4jvv/vH5/4l4vOA45P/xDXUnXX+p3siKCJ57soIthLj6v+rh0apDC4JLvAtJvpv5sIhp
tDbVBBj+/Gq38B6mYcuKxXoTy5hdgbLCwjG895MaWCDISqyRZbY6n69BVRQ521PrdGpBJ+qn/ZMe
Isjzc8ttP6tYfK8v1HqscfA5oikH0I0niyRn1wFMjl+pGGtY5rnlkFaKAsOCfJQXRD7UVEkaGrbH
hS8P7ypU1S7WrIWPqghY8YgPNlhYu5LUK4tGiiiKK0VLM6nZx+BV9uSQcsw0ehc4pEMmuQzlkt+J
gj4hZQCYxg4xL45lOnluD5QUW/K3beryJNJ2187BPxloICfBlrDkX9nEITLqEHEfbebvLzQ+pAmQ
B27E5mV2t5+YftkEd6BXvKanYxASg1/crO+0LDPFwLlRklmFnFlclcSGcVfBTxZv+8BckGAt39kR
o+ZnQz9nkC/guY/EoR2lB2MMrT0CnPpAokhhEkBZuU4oIW3knnM/3jF04uUuC2oResRnYsqfFX2k
N3D10YqaagqlPbmOvy2DmhHA/OPTadqfXj8D/ldKVo7lw1xG/ltwIAViQ3ok7ZOLZF4ZdWw66VKc
pqzoTJ4KNPBzWW4cK77lCKQRrO9Y23E3Bzg0tuJGL6kQ4MJE8WP9gdqzYCi2kPb3XwG8l2aWKmSb
8ts4juLrQBw/AhyDyCPjL3qg38ohQdB11w4W+jgBbu1ojQJjnCn9brH2GZQaCAhJIwU8FNdfJC/L
YNMCiQ6wa59HotHG8hCsqkdA3aAO4guK3+5E/tEl10r57Y5M/DrXlh23BkKlxSlaikHiqA2/MGb5
mMxrgGSRodWlRpqlUIgRo+P+aH6eb8xc2DfF1g4fr+NemsKxs6QQVdiVOkDoPetSiCwaxznqdSTC
8cEl+JhccioZDj2Cqkv2YZW9Q4zN8TbeLJpEtxEo6sXQEnXdRtLIoujXkmjYKzMqB//+Rjq8CvvU
/J1gpS4qu3lbJO3cJqZJ69u1JcheSS+Tt6opHWrV7fYdETEQuVZtIBt/VQvpxDYaClogB5rdpmQ3
gfFCk90uIlCYjLmm6vVnhVY9daOO0Rx7D7C8DxkqTAb45SoOhFXq0qiLjuLBRlZ/T1D4vT/yIMni
B3C9l0dpd1e3CpQxodo44Hx22uGrlkWNk9yhqMzKmvQRqCxC9G9IYW/L8/AeDHjbzbANSZDrPHjm
G2L4znKRhebau+7CIbmUg/eBgXSSXrgYsqBJD1PcX9U8/FpsBCraxfvhwjVlImT3CNZqcKiSEmD7
Q5bud187mC/FpMYlIFRWruNNphbzjaDOOuzBW6MmDxDYs+YRyu6kQ8voZkrFwTiJhRHp2h4tgMms
G9M2TFSUhwFpCdEMQQOxwfGeyhL/5GR1EhqCUsGs90tBCu7mVwmiZMFZuq7c/OFtP3hulol2vaTn
acOm/hdTVYqsBlO3cPSte3upiJNu52b2t6sH8oDqotSmXC6hk7QlEu+WVepk5Kalu2WZtppFp95i
86Qirx4JX/spvd6mP8st27N1PGZ5PjPHMr2BpyM2WKzTUlvkkIjF1J2itYGCTPdrCubZxkBl56L3
xdiV0nelZu7W406Zxi9GiW7IyIiX/jB+JpVHcdswcOxj+aoRXWuvKd6C3SY88oe0heqnlb4ZIaMe
XlfJ9+Bc4ZOYe299aLl4tFgKhiYgdOKNQlVC5rFvQAfjH7KkqJf2yILsaEYZOSEfxf19q1nOabht
8/j4PCdjPr5hFyQ6bjOGHFYQQhr6O5NRemQOndMbIElaNnZEy4m7KdLgCYVk29OkZuUEu0XDC+ct
pBwR9laR5XdU5ZJGdUlckrRvopz8ENI5It8E7+bBC4gio0XEGI/VeR9e2JzlsZS1EMP9XcqHKtIL
DWf/kRSC9QSlcBqn3fD7kPMD/vgsRJ/ObdGDeKQB5xVRwJkbJIHB5SpL+Y6y1NrXTE8vsuUJiRmU
UlNGw4+yUl57XpPyM4kryh1xEKY3VFBLvbQJsu8zt2ehRxMMm9jPUgwNsMUUjqGp8imRVfnE+kh7
haPtIh82XnUYqcSIVNvl95MQ0f8KKYQjw4MwthKJlOc7S2tWYysRTsORLTgacYBqeR+b1tMaKqYp
H33aAvkfiWvSLnwTPz3gqydwNu7hJWJozri3xNu4+DNK8XAMQYO3uJRQCR3oU3kYjoGxlMZyUnNW
BSg73fz5pIqnxBvdyLwipV6WVpaBGItqVOBfqAFOSiSFTYxxn5cr4/RX+bhrSdsqSFSqfuW34kpZ
gNoJCbhpjHX5yA7msNyPxJLt37Ci3O2evOCVKhGQ8ai9GPcYmsrz3VQCWgtmnkk2z6c2bXwTMSF1
/eMDMfJYFc0irnARowsgY+IiJmPfz7+NzF4St5EbPp1l9EqZS22cX79SeYXDgszDQ6QhWQ5wmGUx
2obyOgXbYm3RW30Kxx8u1G5jRKxbWOHsTSChoIcz0+KZRkG2EK5ISbUdkwYPd1WPVu86INhTeXaY
Ur1JkCkPYEfKTzn7pTsdEMJYe563VFBjaYBBh3O4FKtMJtHgDIjjvm3UoFFLa4DOPqoTatRKkxX9
yeYg3VpUEBT5ODEVsu+yHSObP7+bjJVdkeSQKaHvqOBxQr8xeRPPc2UIdFjfaQsMVpQAD53ZzknR
bjiwlzq+0VW+1rObBZOb6CYZvuycysiogCh7VoHd0qn3+m/W44JTiS7OtWy1elzuydkbiLBE4vtv
1JnU7PxEZ+QAxpjzUIzC2h0+0QTpcc+1HcRzUDnzH9xLpLn3qTJ8CTotIifzY/CloVl7cjdDokkq
MVD8azYvEhDD4hmcnx8/esaIdYH1momAZtAp1ZiYPDTA9gtGANEuesti/ZQWSZhbDWAn5kVOzS+4
c+MAxecegM7pLBqWFGduM5d4O3ivpy6I5/o8CoqnbLMJnLqtrf2hVcWnavXj82WtRSEncY/ysmZP
j/4zN8Ymc4r4fMUD0hDnZ+5z2KRhJQ0ITFSloEat1M6qtMqw1rJrAAi60bIaEaG567jzyUvBMP+o
RjvA011+IFtc9lws1vXU6BRPbWy/fYqg3PXxLljWm2p/kZ1TUdq92mhXwru9flYqqtnC1oxo8PIZ
5ZDx4yJ4xQX4r1E6XfstzNloUZamA9aA4OT+4pr5K/a3WLYagWbRyWZ8hu5bamo0EZLM636vNnHT
Fk1Wq7awvaKe8UWSLUzj53/0jMjY4arcqkvcpYqvboqIYHYNAXzYOjY+GJnfyYrIjgWEikGkO8hU
HG5/ybWQumX6DmOpydgxeA9s3cfbxzBjq/L0zM+RjE+ZFV/vVQO5zGnTyPQHR5jZ7GugS6BCY8jQ
R0zBBlKkC9DQjeg9gyG+C3Max3okVHFSOkVq78KiJbDgm/Pr1LXGjVk7cQTnEWHUvkhd4gjrRHtP
7DHR8YUaKViRrajaBrxEWcb2AdKy2agNAfS1gmIQtSEHmRKcL8EHCp/yk1laEzcx57J5ysorisJo
eKwCf57WCSV50g1b+Q8eRVL4KzdejIsIOxglMHBJvuFF4D8t8ealCtE5zifiuJnCr7k5TiFgKTiS
3wo/ffezeuHrEgGgljt0dyPm8/TFTcMtVOq9H/UMhaWpTv5kGa0MucLeRNZRqhf7wQZOHOI4oJ2U
CNyHwDIXxz1EmqgM5TEiLzsHR9l2fPA0pozNVIEy5qhs8ZkH7EeRN8zLvnPVMmIvDVKyw2Gcelto
SnEQx/gUxRqUFz6Z6jUaNnDCgsC8fIcox0kfcq3uDRxC8MpCndYULs1RiiuXMO5MXmd/UbjrANw8
zt41l9bRiKdW4O8dGLjRv7ajREn8PphZqR2BC6m+QWirXoFVrWhnF7WdhcqKa+bDlcN9/nPc1Rnb
xBnZV1X9QdmOcG/QubMP9keMC8jdvzsQwFBcii/ynHIwPr31H1XDwoVfY0miBEs1S1I+Fq1US9y0
sYPx99coF0NOJKcDZj7K1Nx8Kv9vMmf59xA75PcMEpv/esprXIUoVrt5qRNd9+PglmmHl8NP0UAJ
DMjQ2knkHYneFXWnAPLpyvK5NiP7jOtOT4Rv9anIDQO7MB5boeSl2rI4+zKaO8jNjvta4nU8fUmq
VdnzkB2GWwN6PvOrHmcJB12yq0999O957Gw+TmYp1VuTq997fcP/njNu9PNVt9e3zK1LltwQpiPA
mDbGHMbYsyVq0vhGuJMZli+WzOpBfRDEji/PM9FfT642uaEaRq+kRdhUp7WpPnBMIW4KGgH1dvtL
qKLq6dsETiFtePIyD9Z/XdFdqI59T71Opoyl4STR7rSbApazZEZU8XQqN4SfR10ujaEDAmzl/mIu
Q8ZICp05rB9i36IBINR1QAhRKwh5sq+53C4ysPaxQkcydB0q8fMJZxQihGNIrt4+Rz6opz4VpSrX
eXE9C6kuy+AlqPIV/sF7VLXbHtjRN7kEeNBU8ziGu3sK0zsZJbhhMutcGJpLheUTFkZ1IZV4N+Vz
YTpJ5K10KFBVPgHec4jd3kjDIZ3RWZP38/JEN5ytxtzmS6E4A95PiOOf7E+yeX7opYYU5mwP6/7T
fAKPZPCi78/eth4CfF16+6U9iQ/opZZHRqyUW5CKrNerNIzu+x8KUZ096EH13qucQLzgsgXN1Wb6
S3oTlmq2p+EC6MOO8IVBg0hI9+s0EZEwJyah6k+TqwJAgEyPrTYAcgU35yCk7WSQp5eWgIRQ7wyH
wwcYurTYcKHkUNEu0ui6tHUVpfSXmpDIx0UL3TBISj5MH+Jqa0VZJvu3skiAoZ+AGZF0shxQ7/tH
uwjr5XdZoJNHLpKfa2guPyOFctN62y0KI7UEtooTFbXlWt9W4WMF3oxSIKKPmgyPyZZluzfBnK6G
mK7kex+tEzU+GPEOgJoK/rPrmnYRy2JIWgUEQ3LslCWKVAFz5di3a4FK89gbSqr33Vw8NJUX6pV5
ebSbG/XxCUzS0Kwly670PAyFcEGd72CxCLyXUNs1i4Cd2pDbFzc1WwJyWYtdbnBHLCyAanuHn/7T
FyqSkVD/bOYE6P2vZL4P2O0UZbQ0fdIw8/MNCK22NZmYb4Ir0LT7DvV6b7KW0tROoTg4wlWyMS8G
LSAIL0O3bZGV9DUtPKSWZ5QDeqaw4eQVONpv3b1puuCW4KmTX0FOOYeMDRuLczwuUPaOsABt7dVH
cfafVTPPJtBH08r4amO/wCF4/fdtGI9SKJ3a1LTZmxEdJVHmIdpl0XwAoAD3irLo5ESIuh4iqlrq
I7a3YoYl5vCN+c88hgXCjG+bou3PrDINwIrW/DVw4Y8HyCqw7iQnk88437p85htT9zOR/xp24lYd
1oxFJ9sAaPc++bZwLl4G5Jp6hfew2dMHeAbrd/Ye0ZkpKDxAaRdJNpVQj2g1oYUHwg+gKFM1zBCh
QE90AK3ZNgm1LmgIGlUb3q9SyxHpsNvrTDg7RuqQgiXGJGx7YP+lEv6p4D73VgvtgUkGdyXzcIUu
d4hOoP04hpPNmXXw4GlfheEeQPFp9I+CqKH5EOMKO2ipD6n2Cfrs0IaE19k+nTFUaljQbx9Osvxc
7xO77aAOlNkS2udv5MpVYaWUNuojRz8XB5UNUxy2rW7rpIvSn38uLs45AsrYEOpoRfGUgOhuGHZd
CFDkSrbimhwvOEf2Euwmg595ll+6PwCDTicjIuNfZUOnNquTjHKZX3pVeoDj8bi7YPoBlpBvwQSu
vuUZAeQp0osCoVfNqCv/F92MbI5KPBy2TgWXU3WdaryoSTrtJaBAfqKKNiCS3+Cm07STawZm93w3
8800lvADQve93a/LryhHbXzuza+65YPNqS+y8htEodmnxjazGBmIzLAdoYfqsvw/djIsTSIo2xZe
BDmO+q50mpnqPn3rwhtmjqHFdeg8mIhydMWDc2YqsKZgv/cJVVQtU7S3SfjDsB6IkTS9RqyeO6t7
F/g3JXTE0IA+iCq1Sy0l9R5IxNPKtTEPJ3HEYhilnAE7Mb9KYeOHKa5CiavhdYV1VTj4AL8C4zBW
hHvBS+46m2KU4c6p5yhdghF78SZZZRzRRD4mDQXLgy8ys9ONhG+uhfvGYrhJuVBfuoS/WN/nuLJm
i9RvUYYhsVQpd4eOjpTxMTIV3AEg2gP7i/CTTNb1BlZQ23XYkZRe1V+UC44gBbCcbtaDnyUDSTpO
KO3x7vOrXNu6FY9MaN0FriHLNFG/wPbCeWQ1abOAewZy4TTrNm/hQ2sM5GVpi6VQDHqRcJZVOzFp
FqU9n/cWxH1RgGfTrzKsBwKdZAIA0gxEfpXyW1MlPvTsf8/eETwhlfrMGGDL1V4mskeXYLyNyWc1
xjLQlliE2uJzOUHgiuFg1OPoN7vF3Dfs4ti+v03J/iJU7U51gYVb5nq3r51jfiUvYFWo0WbZ0XD0
bT2fo3oI/zfdKqZI79i3dxZNwXzek3bvbOoQpk462cQgDP8EdUkpqsoAvhwDxlOl6ALBswceDEB1
LeWHc+puT4LX/3q781a/XoSreW1IdR+dqpUNtOaOaNTmGF+IR797itO2GYbXcjzDIB1CPTVXtuyf
d/KdKLBnGLiGRI2xAuyHxxoNTXvjzgg3G508BDLK/Kn8QyUTBRJ0fOKspSk4xv/4AORNAD+mwE0r
AjxvpQyXaRiiqvds7vcZYyricM18hJPMzC4XfnZi0EAjb6iIsXuxKpaug55oFvsaVbKaRnReLB1n
+7wmuTnVaMfQPt/l7dGLrmZIrIc8brkzhKPWChYLEdGyDaJ8ifm6BrnpimCDrmS7M6c/c3RKrcqk
bUgN3b0ywu5XWxz/Cviiz68EnXo+KK1+isEqsb3MgWx650YBd6Of++OQ0rQYgIBZNhPsf4bbEZAI
y1L9xng8TX0knvrxUijNFEFUqSgERMvlg5r2hISrVH7ErVWrn2sCH5dc8ekKDF5euI5rG6fhlH7z
Z2trLOy8RTzFsyrHzOdKhV8r5a4kycUrVW0x5J4FifX1P03sRv8o/kie4YnWuq1fiSNeDc9pd3LV
/iCl+L0D7qsD6KVOwFxFZh7gWeOfqU1RL94SfRj2PSJiB7Asx5OLH6IPUpCWKB5GMdv2lPioBZuM
ScEjpZtsiC8cfKuPkTkr7XwYe3a2qQoifgILFjzQzV1bgzZ6BQj/KL3Q+A5BRvB4eh5DD404tM5J
yTvhepM8Yh74ylAIchjEuuizfqru3khd0s9DYBMIgqYXL7VLEifrGxUmeNkQGuhtuPO3IeWNoBLV
9DHT0VNrnIV5VUrNKscP9y6sc1xFLTInAexO6NLYr2JqtgUbd50vHqkQsr32b2Xlve/v5r6/B858
wHShbSsaIBipmAXQTstzGPkJ6gA9+FcucWNprm0jhwdb63NMMA3LFi52m0058vt7lJGMnJa1Czoh
OHOD2oIgjCnV7lQ1ih5MLISjUDNZrRqHTxY0o+SQHQ7Ix9UTK90P1vWpPPPsf2pgMU5Tx6N1lSOR
weOQsqyf9u2E97LZvcS4cjkMSuE9FFB6RuVTRfVmJbKNxtrATjPYnQJBbWgMy0i06TzinDJYsgPK
TqPUVBOdejv7mK9GYzniUq8cJCXket+4ezsRST3LoFuPQ5/aLTcdA2gGen3TU1VUKTNw8AVlMbuW
6rR404eYZTb8SIxjPY7vFP5vHOG4hX4A2LR5rlSwvEb1OVT26CJX1Y0VdYTncWGQSBzZqq4H3DWK
qUJC000bjK62f/cSw9XBTeAOOz62CT25M6P487sVoKrFOsDDhG2W7HCI9yP4cJ0Mfkm3VFSlwEPo
0gBvOZjum6GY/Syub7ZFmLFYMY+y3Ad3yMdqM910t6Bk4mOrVVgodExT4zd4ZJ2+rbd9w96+jCmA
g06sPg+5q0xfM09hcTXY6vUBWBi3SR9SupRc+WCziJRw1SgyTppvJYfpHZvmVwysIQOddL7tAvhQ
cfqQC7HFNZrC2Pv185mEbxCYQfjfNO+XeFuipLLA54bCNOvX1EBVw5qhCFETQ1ysZhMMB9ZK+G9W
2OYbozPqQcFeql1MDB7uZJz0S35xKwG37fKIYSm/JsWR5QfOfAdVCibkzH42Y8VDsKn1Baun8Ulu
K05UA3hy4EyAOVbv4pWXcoCTC4fpRJx9JwGy9uahy3rAmqukk58J0dnFgLPlLt6MPWoluTekSQz0
x/7O6ksI6G+8+N31Res1myQ1NRP6s010Nux5zAEANAco94AzSOcTy8PQyG0UTCtGy2JOIVhLTnhf
y20U8+E9gwnWxV2mykx4yTQYAyRdu0Kzu07c/rzSjr0ROVsAwZ1n3fD8BHUcZF6t1rOXIacvWxIr
fQ1gJrb84uPG+CskQQl6ZoGC/i6t9KudfwoexvfXSJGXUGaHAl9YkeogKVoJbRl/hQUJoO/x4THD
JwdBl84YmfaDGAgJkfz3vFbHlSVHpZ6WPcjbFVgPDGYys7sV8k7+ac0QNNAysWudGj1//BjDFtqF
61gnb0UhBd64MlvH+q0x4cIir7+XI1VK+XJzZ0Dh7iQkJ6UhnwHCLJjUZjVNmqAh71l6mY97XaB1
baLV1jFb9NPuEh39n4Ea0KxvbxabEJ/a337gTZobfn6/AKCcxpXTQcnO840Y7AxMN/wYKRhHQYCN
q0dg588renFtvSolJnlnE7Jza+rQjrqsUxfSQ8pbPJ7Onz4qAq+3vUEQAgXaVCZtVfu2FMSgxi7T
7kvQ/FU96lW9S7BtiLOCzDamcnSDwOrVtMyLRRqzGuFQnLGL8EHX2Zk2aGmToJm0FuCjXFNbL51r
HAc+OvmrPtg0UHJMPnmyLC1rMYUVd8Eb3W63fSaxgE29D8RvqKGW4fjVNvVL/D53eqczwl0llBOu
uJrHZVK8jkNqwxsuM28tXACKJo4jPcy3pieVdt9SZlok6Nff+z8FU3CVu1tf4OsthUq1jukII0zH
9YLRlJ5ZS4lx/hBdvmLt4lVYZAt9VhsByRDlJB74EVKBQC6de5L+ZJnSd162PtI+vty80GEI94pm
4BWojTFFYmA+jHZvhymMXvV7qVxCvVm/jykfQHhrQs2fETcwXdFIBCYqVPEm7w9TpabOSeqfOVOX
BcqAzZbgkbOotIYnePJc8sZTJLVuqfsMEQuZH7I9jL8ONIEpUiRygMZ0k3A90So412u7ZRQflPSq
OFTiuF1GiGMal1QwlbaH4sB3jAyBM/tP6pK0hSmPcejnMS/izM0YKNQKtnR06dZ7OkOlfoOlf0Rq
zpkH2OnCxZfWLd3ur18pTR70sJScqvGQxJkpCO1ePbUmW0mF1hS6RrDSVg74KFa+V4NHt55d5by0
N2SEKn2j/hyXNkLrRnBNheo/mUgNgz7zaZQeYl1GBqbgKzT/HEuqCkB23qsXA3QHmBJuHSZLbQOs
u4/qtQ1tCzLNcblpb6H7gfhLEXt4Q+wA3ff52gGXkcqhu3uNnawdYFIzch4b7mbFrt8HpQhgLZLo
oUvTyIBK4D9dOOiTj3Ljkv7YKdT0F6AtALkf9GrgvumSijPxJRLgNkPWUNOIel2OLtGfpSNL7HM9
2PN2ducrl7ZSwaPG2biMa5T9Oqcllns2zZAgH5r/1f+eyAxfdrYdZqHSNG60/2kMMSFjxNuy0261
CAT3V4hSfSRdfBsNBVHLQ8OM5U+nSFYLWqdvGly/wkjeQO7k6fJFOvVhT8uAkf/oyNgaxfCI2KtF
p3rAGjEbU0x8bP+sJv708sveg+cuRjJu/seEQeePO0TWAtDbs4TYZ/L4XbN8QBCDC8BEkiT1K+DW
EpktOJmN4TcYgC1QmxVy1WzK+5D0fHO0/VeNY283lt8JYVtQ9bPibabHtYVbdMNT+ppDOqizS03E
nPqESlvscfBdv9ftHJ8yAJoNW35UT1d/I6gvlMbmqbZpzREUY+RDreRM5PchSIvtbia4evMM/EQt
kfMgNY2lK+sil1jx/zGNQD9vORYDT+oRTbAjJOWZaeqjoYKrd1BJCMZ8ipGY85X22fgjzahjEsSZ
D2wafc5SEoGRHXDKOHLbNNeHDYE4o0LE7bshTLlspx36KtXYj3u6IHDhNLuAH4YnDIEs/hd8bbzF
NIOgoxtruONIYHiw4Xkv9iuWEzpoRdyH1eLy6NhCsDyzN1hssFFCSKpF4Ku8z6TTfE5FLliLA/DZ
M4fzTVhUostTOltgvbpRqlYZfAVunDi/qe2IyDgPTBljRwfbVKkx8DMpxqrqSw6w00xEFpmoY3yI
kNoetHyZ+tncRFJFZcs/cB03j9KM06TArQeUnGOv31KKsxZVFTZAafLelxwiCQ4NduKrWZbs8aGd
VwT7nS/0Fv5Y3anzLL8vNuTDHwv4Luua4a2cXpWHcfcLRAiPyX4Y+sWJlo6MV8f35dQGY2rfkr5m
tdIJG5FZ2xmvkb33AtMb4fnvuY7YYLdrvfB2g5bBxNsUBxizwM3lKoUzAG+IAs1wj0bczB6yXMOv
TucUpZhuCtEN37m1dX6a2iLr4S3Y+PllskG3hXfYekmQL6GPd3VsSHtRkjqD3/cdpIH9Ag1t4MJh
vu+Q1wMQ0h//73V5jGwR2CGZ6v18EALA85MFXlezmuTkIutuWUQXII1N02kZ3vao1qNgOA5YlQ6X
lOXaMKQsdxhPpRu+CpX/NW5UvZsok/Ldf6CWWlMFVhQ78g8ZUnz38u3QxapREKpSbFuMrE0iD6gJ
1TIz4ED316brjU4QQ5JqOx7/olAPktJxealNAjKRcPf6F8B45BFl/xy/PI+4R9lobpsoPL5lT/sK
jAaD+NHXOQhzlA/7vRibCPEK/AV4dYjzj7fpb96bRSSYitMwWOdAG1dVPRntkHTu7MDgLFQBcwvA
9KQPe6NUGJBXq/Qw+W2UoG9KLGCPGqut7XWCa1Ts3bCWUpticG9nWkOiZdMtxmTsmzT72XnDgJaa
q2+HCq70/U8Buqe/Hmyuse/REOF60P26MoJ6BVov08ui1yeB7+UodUhMV2Vq91NTPQ5MWXI7VRzE
DkfThQfzKOa9xC9AtXSGkDxcT1UQoPhb25T07s91FtcONANZeusb2hQrVhQSLnCCCjGGqBysSlVD
j4ry1XrTfUSYfT92W0jIDv8okk/l9jeTIlD+bhBlbF4VmYaq48+gbGppppZIVRVi61nvMzC/QAlG
7dIB+iWVghsfFC2G/vpYn9lA3f+ZB0sWRfy4E6/6jxA0D6wOJbuWRfX36KTBYq3wcAgR9fZDme7l
267l5Go3JY5oKJFJqV8DWSGGySbcK00Qu8svT3UAoQLRekopfa/QdXyfWmMiCbG9EAQs9VuS1bIM
z9x6uKIrjTvwyh7rX1g0bB74dkyEZznk69VQhT+LmnpYUwC4kF8tgWevC8RlqpDSKlvh8GihLehl
0IkAW5qRFFqW0DDPN9+IyAIUc14t3pXKefwW6FFv5UZN5R0rE4t98SRR+MgAxyTNosLtICoytG4z
I4NgofQmlk+BQAdH1UvJYDwiym27athYJDO43CvGtVq9CfPS1haLz4+yEwGqWhreMfyAmcrZrxAZ
JA75cFbtQgSfAIS9leEzJn8v5FvOJKt/HSoRVQ7gwE+vvOal1LJslyUM4fn2xuBeMHt6quOeXCcU
E4XDtpo55mzmo1mt+XUkeUI8ma5Q81VgQHP+09b4M0x1Q7PI9q3rULzQPz1RDrENpuAVnA69+g8C
32AWEsrZr8DSEA08R9d9te4hFx0MNM1SYC0dOW1h2yPEJjCJFnJ8OW7WNAQ/FzX1mLac9TfKPmoe
hyOhxsPQLG7PjlmBeJbSmKDftTBHmBkkCj6WOmKhbnXfgp6gV+SOsNPv3r8JPJNJa5gjl1LGkyqB
1+9W5rf2OkU/9HSakROTUPmqzmsFo9fuRy+KjtHYZyuRKKM0+LjdXjWVHvvMa4MIGZN6/KZMT4WU
Os3SKdNC2xOuAYJZ8Ge0b4RE/vQfbHNkGw0LW2NZ+WJxSnPnxDQcUB6tGOp1bEoMcOIbjMm+OU5O
A3GmGvnHW1dEeXPtjC5gS6RQgrmZ642uNsClSF7wIcRxizvQIMsYAsKtVuy6inI71weEQKd0V+Wj
BluHs3dWD+6Tp8hMLIqIblZlVxeOahMweWmUY55KKoVeYWKsQJRYEG98Rgo7i9XkpWf/3i1CFXZa
NpYMUZRTghRtP4Plaqvv9XeYl2EfCEXr+H7DdeYJZOq2E6M/i5gtvViV4mwLXnMNEMfgUMqlf70b
1DAn6BT2K37iIEAh5ZoHrudHTY+5W4OHXHQb4RYx2084rXb/FjWgbGG9mrSwD6lbtvEOc6ZIgHJK
s2bvyxz/8Tj/Lo+qbURBlP2qCm+ZUkrjuy14vCYXXuY3RspbxaPrjA3VJTXGJAAF/e+N2s6+cF2A
6XmUh7A+PduZD45qq9L12hywWHujs0furfC/mbSktOO56+IY5yZj9aykzm/eH5ubNxwFs/VqXwAS
/+d+IUvuwJRBj4YFb63cGxIscbmUufeDw/c6O47I/gu+GNNO5h2ZgpJorb1B6/7KPqcgDgrcmF0m
DFs1ZYui/F5s/+G8z4Ys0tBX+Gkp6MV38nW8Bok1QKH3Rj3ZAbQZfPNN5RcL6xm2zvvxMAiIhjkX
hXJ9yLqgRUMR0HyjkgiK07mSIvMqGXEONaKiHlFVOYWi+p2C91/KqoNjP8yeqFVOPfztksyDzmcn
zJ2ki9rSztgIn3cqoK57IkDhGo/jJdN40ux7ZVqh6sbAkuT1yqdCyAYMni32nRiFS19o5EvXimCb
/RNm8ebyb4XlPuhPZwFvOJkWJgupMmMl5enHNU77ekditQo+GsduLqMQbQ5+MDLYaDL6jvZ9Gues
do9CzsxcmYLRaVCZEOBLLy3c9j7dUFDwA3bjDyT3zhknh7UeHSFnOXyr5Aiw4P9XYK6zA/FnbAB5
GuMBH5NlysDo0JwvbfRPbS5go0lGDrviOaMOLG9H6Qo503eUB4OP75sYeGHX0RbHXoU4FYPWizaH
am88vWhFRZMdKRRLXByrRY/tMbA3z7LOVFumwST3j+kCTz4Ae0r7hFuclp8SkaZZoc10XVYbu6k8
0BlYqtyKuVeaGR++l3DusmTEGOBrA0DTCgVm7VdIwVGihJdnSSOZhvqzBSMYWPUfsPPkZ0C98yyx
pm/KumW2R0sgwc5TEjKG9+7zlmvt2GLWB8fzqxljy9CN8gCaabDFSMGqw69pt/1nbW7KQ9wniqWy
UJ8Sl88QONPXltM9tmmUoYXPS1yMafw2oOxjIIRNy8Ec763RRtJDJ0GchO7fvFlKBsjnh1SnUgbO
f9APn0vIn0ZN+2/7AAUwNDah/5Pld/9Wj4lk305mlCe8UYozT1lgpr9CqeFYm8JL4949enjXknb4
LuGNOKkbt2BHkbt+IGbG7Rqu6OG545YvIuXko1q459mjA3J2tNDLXodD2ilFRDhcIWjMyLGjxZ2E
o8+0LO5GEwF89FVoCcTwT8Zr1CzhCOJxgOs4yGVrj53SE6Ofg0xthVRDPu/LOsNTAZzbROwncdwH
eoVSIkAkIlo6T6+7HChxu7SE0dNIQHIrD4ED+kk2vFihTl3yrPeiZkHn7MpEbHJCPWKBG6/dQ0FR
klPsWyEhx1TZkNX8NNM3KSDwZLkt3CvA01SDZZ9Fy2qudz+rpPJDwGx2nqJOEJm1ZjWpGpy08IAm
0aKt9uG2GzHK6Xn7PqLYEtZ2UxVSWyPdtzyrRfM8c+Ty7S22J42UDeJnRw9WFCnmbdXTL3H9GtfU
QmvndFITRLwAfBcrdFbQgWrB661d8lLvxCEPFuPFSuA/FKspzPfnscauViq0soT2hUa4WJ+06t2s
y+w4SdTrruVp0n3td3gvSvJ1acOOoKE5DOq0Mnlw2cxPvis+cvgOEm4ba5hod9lm4V+kQIZiMIeK
9tKJECEHc/p3eW3XF1jbGC1ouP5yUHOQL8cYjyQO9F02zwa55tmMnBJV54u2Iaxuow6GgN00alKs
RA5SQCe05lzDlfMUFmFV9XKMyKsdbhZdJ0NXuQMra2EGue0KFKnmthkk/pG60ISOOCbMNmsv7QOR
fVpf6m50It6zvUbcPcwAlPx/mSMrK6PpwPfyod9mOQOldSCFnv3JEOsyMRdlBke9b/kvt+tPkBWx
QlBbhpLdlkB63TKUwHOPOKNIKtsAqdb+HkKeGKtEAvgALd0GoXYGSN0Sqgomtb8ZhFT1Dn66OdZR
bcFxWOmXcKXCXlXDfWl37GEjqWIOH3FkGT3ORitekJ293wapYkR2Rm75ZU3/1xnudqHYAVjc0dFV
Xv0JISWrw0HvjkbnzxSm+4qyAoJqaeFBg9Dj1J6Wi0yhqDntoE9OneFGrZTKe+fe2pOcEUytP1Ic
sqzagGBuHkcIewc9o53wtUkGlo3Xj63FbqwkKRYn0WJbXpOuaQRHgJEnYE1VAkQ0kewzjpNJpYYw
Dm002g1DJizTPBV0G4CCpuQ8tYqEOPmVPB6M9chtT/7+iDVnzg+QvROVnBIyWQYijB21YBd7hnNK
SDjDkVJO3AOMFbNo0RS1rD+NX9VgyonofEjnSgKi+Vs/MK1mEJHmdqWtitaNPb92AiLGv+h7J6Rf
Udq7ruFQfcyluDV5c71UawV9QfbY6bKME5euIe0qyIMBHQncsyJsxoQiNqgD3w8tlStpPLGo3ixv
03LhRr7OPWcslAJfEYcsWuab1pfjjWVAnU/bw9BrgbQrz7Em8gOghcWmVWDu8YFMwgZvJ/Nz84Xv
DF7lIaa1b+Z/C81NaRI+rGSQyONHfUCorjAz4me3mUN+7SKZLAb60KkJi3c0DGPLWhKnpFNDvvcj
HuY7OMbCWUX1lGUZjiZSDo2mP3+dJS64m+sDVNme2+7+QzEcSC0PZiL/zvf/LX2H7vaRgOBBWZbu
zb2iBGIu6+QoSLKkjTpKenIFhw6Jf1G8yHcIPfvIJoe6DHZlnIDbWc1Ckk1u7usfQ+qmzvqxbnMu
MtgwbLhP1ARs0/hQgnu+TSKVsEHYflKcUktiueOOksZAzm3FEY/TmfWXQ3XzadK/ZRihR3qt1Qka
0zLqIw4t7OpTEnxwLNFTUSRtZtNy26ifjo39b51cXCUaEBYlA2sD1RoaURQQ+XNMGPBmwxB6bEOk
1LEg2p646AGFZJrE/AVFiI4ehFNFPolpDM0hv0zxfPsR4+U6dPBr9Lw4z4uU7i8MjdI+Ceap+EFw
Oju0FZKAlcXD9mNR1kvYqaUIn6ZvEXHwSIWskKyDsa5SjJaKC5FarJgxU3MXYVGeKJIRpEMf9UQh
R70wDmVJ4Ll9bFJRbpEVgWZLO48bV8rT+OCBuV+WKbFw/iCMAEPCR4J5F8Kctc3O8IP4GuN9X03g
Nm/1rI6wZq0NPoFVG7gVmoMddjGDOMfnVKD8/8PcTpw/1L/fbnMxvXSj6pEGgyUyt5erkaeDjDln
W6agxGZ2i3jebs2SLxgeVvns8spFfb0s0scZBqysqndGsK4BMX5Lr3feX0Xif6qCUTyonkGWRhDL
IBciLJ/+0yeAZeazHDKZT+sLU9fxtJhPbYZbilfVaBFDPjD5P2O2wT4uw+nKJjqdUSgnVnH8vXaf
G8CCeiM26W69F1omtUyXKb0vH7uAB/V0z30f947Ct7ARBGgiuVcqMCbYJB5atU1v4RZ3lJ2I9Gpc
DQ9+VzyUTYi66Sc5fQBMFoMdC99gYxsfcpxwt3Pnm1aP4OEAjyr6/Ud+jnXp/BpJJJ0q9AisaZZZ
AMoDCGzfieyVIfohUXzFP7sisXTJyyJ18+PxkMUAW3AjIFFkFA8sFH5WJl8NyDULlR67zrpdH0D1
iWOOnqhS4T2g/LRjbeCLtqtyOCRJPkkNXlc55b3u0s9Ji1/GJ5WFIXhXUNLnWHwSMHEpbGCcQPhU
BclemrjdjXAlkAtyyocx3EcRt3FY180cwbBjS8j7fbRM2fWJqHApFdiTS/Hkteg18hiAuo+WUdg+
4AEg7FJWBfPQpMPqSNfZxgKde02/mVFP9d5yXkbMfhLt5Kr4ZpZv3qBFr2zC6jQorGVScaMAMiPJ
fXivJBgBS66Dksb5VD/mm49d2lCmVUeog6YwB6EEuZx5AZDmP6LPhTURXAAppz+ckbgrXcsTrsAp
jVNGG4xA2S5BmLk7q/wYCN+YRwYTEpg7qiWorpKETVrwBHtb0tZJNarg0ILMXMbHuQFwxDikj+kJ
2A6VWBRCgjZQEUmgPPW4W7VrVy1qmZuTqzKGM5uBUcpY3CN3zWXkxGB41+GES4WPK4hZ7JryJfay
4o+Cy3N2bKvv8oRQEZdla/n6NKDUQUTZ9JMm83RiwrGnSx8QBK9yLSw0/41AkjFYBePeVCiW8Emo
DQtMOtKRzZHqcxR5OMKQSslT9HbKkXdLvCWoTQ2yud9cXo2qJjhZYZ3kIqrqaeuxeI2iXF4ZIjie
Q6acSV2n7TuwuJd6cXojPUNblDYeCTRzrOfjOwXLW+b//yCDFqVDiczEYBhNQSBSlKKhqdJWg2UI
RWC+lPvy4A5N2fCp3z1oR6h2TDKEm2nMjB/rR3JDTGNA6IA8mIdXa0uhYNio1UOj71wf+j60IT+0
mSbOo8IJdJK0PsDKkSNHnkiQ6wGzcEQO408IufuKa5c7yBXGH2vs6jQPDpFTev7MT+Drez3CHBs1
E88UUpQFVJM/iVNFQPK4kfDHkWrndOb+PRqOV49wikluFXn4ElutLfhWX+LtNgZdZ6OdIGnjkB9/
7ZW8wzkmt1ZOGQhJ0gfpn+ZN4imYuAUhZ9AgU4uuQ0NaD95VptcgpOxbl9Mpbqo5LaMa+vhgerea
/gqG8BGVdtt3Dz1E9SoK2lSILHdlklzlKOQ5e3SMaJrIKNurQBYASEeasu/qT7RmvkxHQFrmUfaS
fI8ebrlmEFZEi+sLcckqrfcSMRE0zyIN8f/1JEPAcgq5lf8EQ7M38rIpYMTtExiE+VhqYfAxiP19
LycDV4CpigxQ3gMsh7yV/bceaRCiUMOxuopN3tGxie9tLhC0sjmP5W1MVv08pROVzX05DFxB5cRG
ITp38x/qj4SuoMtX4rJA4XyysE75Z4geAHZSa8BqdbMP8Rco8ekEcYeyC3NmOstPIBkvGl9kKW0K
dXY7kb+8LzrYcbYqTkitf1ILAUVveA1FHiE8kERrtk2EI8WO7Tbn5tmSWbk18lvuoTWxWpoO4aaq
V53J9OXxC3jhUQM1PPJQEZY1lQex6EuvYnGxt/1sWCLlVB5xe/WrdNzvOhKN0p9co36oT+jpwdR/
Fs2YfIOK5Td300wfjLbDYJhTSFzswSmAG+LP+Vh/zTdza5520W6G8BwL03Uk2NblwLQTIbRHr+gP
ACj4xdTqa7DkVdG1dG204hIg8TfkhvK9aNgkzCbiDE7f6VAd9nrJE5d2RAXfjQnuqvjzHhhOSg3+
CUiGNKiL1mvcpPiAnDif2HQHOhYkfTHvqDdEwZebFF8vgGPKvQcRgI6g/QnyVzJ+xcSfuu2Cjx1a
b/01H+yMFI4e0upQ3JJTFab47Hyfbag1ruT8h+iZwrcW4KSso24rGMJjujl3Pe5EJAGV0llLBX15
zUicuSJRhVk2rgRwJp9FM+rNoXrvG0CeHLp5OLxPBXvY7hUzhLznjw7VTYes/bSi+ZudBiLZiSGR
3WW/+pFWfs4vVNUnASct+jrgp1K5kkPkGz1lIj/IqCaXoeL5HvrOhwhdpaZa/MJlWprNiCQTLcdg
2uNrGlLYc6LvWSnHLnXBFTCER+B6axbGeW5yFI7USAaITTiD5OWTx2wmkhBNHTdbHly5wJMGs+WQ
SHF9egb1nPu+7bDCsxaTamT8QLQpTaogCrDQ/mnBG6aGo2n0XG2j18zEq+gXSAeeNQO+9KTSzt1c
8ww7wEe/NkWEeLwOka9h2oJFUoTWHsqnHUxFNPhEKINsxACsUYIVqDUKiHFa21IiKOejRfqg3yuv
dg5RKWdC2nMvz/Z71u2yvP9Qu3Fy/XGvondA1BGfrTKd2RtTbFpYU806j+M2DuFKZ8eUkPgXKgAM
e5X9J5wUpysUtJupEsGRE7P4adqpXoAsiIh3xcKp9Ly9C3jYbb4YGqBxtkO+xvT0Y8mx4rtDeIHC
kvvr/ON0Z51EWGV1fpD0OoQMxuf/2UccIzt0/ngwXeRx/ahqIS7D6rA7gAUMR/VSfek+L/6aVIzW
0S28UlGwBEHhTfE48HVPBoRplnYlAFGKFgf5GuoGUetyRkYGr1Oxy27p/1k0/qtu6VWpU2oajR/i
G0ovtLncgvznnOGxzIwitDf2Frxgir/2/OwTB/7lkXATwITzQtS4KqLOzm+iyIPo3shllLTjqZBL
EOuGP7TkJ0CufzFGR30D4ZqHRXucaYZ9um6Qu+uH90YNIvo2H9vb4P/3DvBsdcMV0qYHCj5na2/Y
IFQBm4IhiKkLk50ccU0WgowuUhPdkpCWiAKq56APojGHlD/CMnIRSLQCu7eqmyTRgNmxFZBfb0/0
IvdmPY4PJLlTb1/3I0M67VMIDvqBEYqLzs+MwHikw4/qGlhjsy8nbcSl6aSSzWxVNS69ZPKQA+XY
vpB7y277tm/Qm8DGcT5YuekouckrnWtE0KYYa4h94LlJSMZZJlB7uZFEsQZeNigniSX3pyFD/oJ+
yZYOJ0HztUA5sl6ZVqNINCd3M4kB4WilpwU1kcN0z/omoDguVoEvd29mvUNMUks5KO6nTyHPF1nz
hy5Zf8tIq/WzZHF6JENRfT0KXpbl9a7Y0ZYDRu0yna60lvga9Zm/VFwdct71u+EOddHh5ZMpMo5/
f/t/YRFCBAMy1j/jOGx2VJ9hMLmNpn7AitlOZwkTpFgUsf+0n7gHWY0C37Sbw5fv4QC/Da9VAkYg
aqeeDhnQS3+zdV38W4esy2JbzUXDQceG8IBdC6Az47um9LefhYXb+OaLA772G3vC51K20Eq8/Ky4
yRqihbPIXVZRfOmLcRWrgP77XJAy/rXYFUY8GezJZXols9WL8S12GL141QY6tz565CfflEdlMRSZ
IwToWJAN1RnwjNcM5loWSoowQ6RBVAepwcmxFtMm9P1QW2MTTB0kZXzItfPQDsNBweEhCJDUIk0g
0ThnmfkmGZmeQ9AUu2z7ubdVXpwmoNSf2tK4WYaNu2Ililtxy/vx5dj6mOpIkEhF+30Prgs9Y45b
tT+CftrY+eqFlNLDcoPSy35tCXdq+8nhiDKf+gzqtwBcd4RHBXEYWiXFOhrmNOAmRL3vszzxTIIi
uD7OtcDMdbXqf0MmLvf4WuSTQM2syWcaPzzRopVKKkjTDpM8JVYktojySoR9oGPNWPltRj1ygZ9+
reuFNvE/74fDoXJ6WpNx1Z++8Ao2E3W4iCd9TON9JzNQVuSLiHvD5yOYT+RAsWFy1kLwV0rDjSWr
muOw+81inFj7symkGV7xGNpOIjSWaz8Tzgr31s7eErfFxpItsis/b1K6REjrpQN3WSOnPeH4Oi9i
tYrRyfvmnpv/hDF5mNJjd7MN21PonE6nqFKpBF2nRZaw9bKZ7YOR0Sr7Hqj6WOSc7LK/ng4Juw19
hescr7rj/R260QpKzfScgM7PT0MlhS839IxuzNNFGFLf7V28ZItFfb5pjk46p8ImKXAGMT4Bk388
EkaBTUQXE2NNmEeWuB4djj+idsZYqKyq48F7Da4ZWBE1dzGbKE9oR4bmOt41+BH/LuNm9CnMfghJ
GVgEMuqc0zmQoGbmSWAAiF+K+PMq4PTYyaCnHL9JzVCO1FSRmBPk8DkLKFzfvZqqbqgHlhBao24W
CVrrZQ0lWACCPlv8glzTQvpm5JIcJdHSI50pHh9V1o2XGyiEbvQ+ZwXytw3MZhGlJ5vC8fkaN9Bt
FZb/7MXndDoXOhqAUWQdF6aUhF/3ynoZsszISou4jLVYD4We4wT5t9eoawfds9QNFDtlKJ2JQhjL
9m1clMHwSyqWDAsd5/zhBSQXiCGyAHAeMpYtVP9agLn9QwE+Hca3n4cu+pSojtajLTndW+YYQS0x
ot1j29ZcMZBMUn+KpiHfBILFu77P+yKzQJ+95pqR3yrVUPOltna5w16+9Lv3qexRqsyzcbXxyXq7
EBbHp+cd6O241ajXVg87MOd4i/V5w7G4nKcauZv5Ee4/PlHCFfgHjbkZYOQIjibLiLislEkfbby3
xwf/uMWOPfOJ6qhQs1vc0HLwvmJcGy77EuKJLEJ63W6xR8nqRDM8WNLr69M8C6FBBUrJDh1qdHKn
s/sa7Tyb9FE/1Fnrxltnh2MFoSVTvn0t1S5BIvpIU2//tiWo+QrTJDSMvyf2ACTVNJbuFt0NA1i2
jYwYYUcBjAkoedd2qb0ya62wp8ZtbFE5OEznoSO64oBK/2eYvYI7Pw+Br4ZmWCRnc+93J2xzuoea
eGodSLEnXdrlfYzbFiX3N1Fm+X+sqEa/JvWIO/cJWIFUpemOHC305Ex7VB9nTqAno38ACaagGRtm
V2lVPrGwbNvsGwjOek91wyuk+sy4DvqolMkJf1koY4jFKO/U2NfAduJrtKtCbrIuLKzLbtdP13wC
Bw/tNruqpzxUUObYGoe0akofkF/hw4v/c9Dx+MLKjgqj13XLiVBYveerMZEW3cL/ub5eiL44s8bT
ZpQBocOf0BQmjapLzP2aqjR86v+HatVk1tbT3DM9eUz5uzLCJuuyRzp8ISINOQGCoJv59M74RrfX
Q7ROAY8vrXX8eh4EMVbx9nAL/AOeEJg2kgAe+ZqalTQ/TIxUNjslRrt5cixlMXLT9xfeBLzam/5o
qOA50lu+wVvdx2Hg+seuRd5FCiSCE0FPL5VrizqQ67DDWl3L3WWMuhA9YiIEbiPHQIX6Ei4KeZ1E
VDKN4wYczPjZXjK8oJqTT4fSo/nD2UU3NcutThA2hAkbFqan50ONiPJqX6mrElvjGXXVy5dUvR/o
g9qFvMZ3Mb1yrjIUXt754uBJO69b30MGhwlJ0PKfpA5IW5aKNxWx5Kf8mK5zPqjpCTzml0lN1aC1
k2YHIoGjdBFMd0PNgA6uOcpgE7PcInJZqOVI/rzOfv4NVIABCHim/Qs2TOW6CSC+6rmMRnQRvnu0
Z4kU+TH8jvR4bXut1CzpGyoXK7FiU0tuHFjyRTjsr4ToAyn97031Ec2ONpHK8KFaJ8Bjm6M8tzMn
UUgzuiCNJL7PX1n7hJVguU9UDB2UfhBhbP0jKi3oArWFywiVQZIqlrJC8/uhl+/XYmt1IB+WdHSv
t3+ERoZBQeoHY5ChziBpXfDEeVqSRfa8MTWfQXcN8lRnjF1Bb6FOtqBIrlsg16Y2gUsgPlwjzHAg
D3AIAF5pYQC8mqh7EIMIy2RjNQIsEivuQX8xbkiEW1r+1KhJ4dkIw+dt9ZwrVDaSM2VKuijhgYpQ
uygkwcVrZc1UO48fTa5mPSToVxEuFE3JclEXC7BUqAXPQglwEixlW7cDA+lJbkEboASOXnXZtlMu
CN750S662OHN+Je1SlrUbJ8TeVWx771N4yRjaj2Z+j87MSAbBPNudA2F6p8vlp8mPehhs59E9Xu/
T5njfg64r5VcZhU2fLW8OJe7JD7VwUNHdvJXERoq4S1Bw4ksvCGco/4vlaX46Gs7xCz+cPwREDZR
6+x7XobzLq/76sYKB6tRozqb5LT1c+Yc9H8P4leJ42TP9MCImEBBi7eBulISNmEAXNuEsiBFySCf
Q3aeESsVttcGom6gB7UEKeT+VPIGH0wV/ujR9JpOn38SM2yXc7shH5Aw/XqV+aH6GscK3fKrRnvd
GqdLxWOaEDzD3MY6JtY5msJHOhVlqRHhkNMp8gHR7HeM0XPlQlNmP0u6LdBG2JCikA65qF5eTTt/
mHUySPL7j8gdxlJXC+VDBxbQuO5Z6nitbe6stqXQKYdjQe1DyCV7v1GmSgKbjSehvzqZjn6O/zR5
tBuxPWG4iQhl/xq2u5BKh88XzwU6JUvQX8tDJdv1ti9FB/cKBbaKp/qg0IbvSJtxEIcSjyKhxgCH
/+JtRRfvPBmS4CtguUyid/rmKwgwankd9mPidoc8Tg8gmAmTulAzDwJElplEilNOI4ZI0sPWMzKl
mKI3oln5RJBXJ4Crym3Kx1siioUH4yxyjzmpoiVZfFSFSQ4PdLlxfXKclPP/eWRQCzYhq0geE+Yh
t5nY4V/IshYYtyVbfe0VdqCZezZZES8WI0TEIgFsjVWbJ63gbVfZ42ftaNH5Shg8puO6amYDCMPf
NtjqcWdLKpyKREFozW08yIZBe+HWUQLLtZW8EwADSFsJawMgQm0l6cnGVY76MJO2LY3JvQk7+6vh
vxk8bcYb8UXL+5nZInmZbe3JmPBY/dGca2jLf63tJ92EDk/2Ekcs/sTc1F3znanXX7DJ22jDf+89
AyNam/JnD7u4NHZBLnUeQFSc77jZ42CYTPdmjZUPRsBEX0daWaDtrhnvylXqZ4e2amgPPxbYlVPe
EFPVogcAVA/5QxQMhk5DpdxQ2jl4iOUobz3QCju8RUfEraX15STqyoGAlZCBJEquGHUQBE3ErUrU
HMQodLLSZKftX2G4Qo6m0V+KtCAZ1An3VFefEX5ZTQFB9ZDjv/Zojh+dUTQtLihLZuEVLI0XF2DG
lEn8NW0/e5LFuJLfYRsu8yKsVX+nvMAvFJ4HsHKsrWFHViG2mj59YaJloaxyBWIA0LMMh66/HDfE
0Gzv3r92+mI+bB0Tjohi3Ja0mLKoXXeU6C7p9JKQZKuJcT0Sll6WS+0TBPv5pgVmi82yNBme9d6u
m+13YpgnJfRqETq6UNVKf7lPWixkbYUC0HzAhKSK+wPHQzVV/fDZvN69HNGenduHvHK4pa0QvqeA
VFR3GgizIcUkp5iDTew8p7NdlPpTNvCDQSzkTNWIwk3FrxkNCYvLkdeMoYep98jBvGrhpo2Sl4M2
PptP1BmPjSGkg6AR0lvs+WxkoIYhPGOdtDoEoZ6UdEqjYr8UVeKBza4Skcs/iKaEid9gjuYZY6vb
xLjSF4Ro2PzDvqEaJfbnorMRP2pZU+8dhq+YV1ejOMkhnERNKuhEvTxAWxLSG0diMr4OR+xthLJk
PSNFy/YNExcZtL71KHPHO/s70d5fVFb2uHNhcfOAGk234TQMgIjg2JWRN2a1rXU+EUPHSnxfdcA7
hIz2NeyuZvlQM7YytyBsEdWhqlj0jbe0vL0SSLXre4NgsxSeip0tKmTLbQmeG0c+/y5iStBDZjyi
oULqsI8TVr23nkcQQsLz1Ccf2iNiN5B7Rp0ALCcw6pUKzqtvLtHT18j2dgib6J48p+PtPswbG2oS
GDvZVyQXnQV/g+lbhAgIg6xvEdzEZkfcaG1vfdzVE0yuUNCqr6cmRtV7o8zCwgH6IR/yNg8zV/6A
XcDMCM9UudmPLO55k7DFRkcA6tArbmlCbQGAMgqS0G3q2pZTSYsQxN1+EBtWZPwQqHMApQRc2XUB
yrxF99DsV0udtVhB1TIPVN9h3w+O51G8taU13qQe5X2lX/r7MvoAixuaVntxKLU2jS3q5x02bOsr
sr95SNxZxdsauHorHkKPd7/+H56vnXBJxhV4AHw6oZQZD41ToBekXHUNvgAlYPpShpBXqJxqIJex
dtiaCUhjLWrskaCJoRXvLR5zBAKMb2gl0mpotMMAEdcjDG8VrvaEr4pk4FUhmcdWwKexG4FM6Dxf
eoA/hquaPW+L9pttTD0wUyX9z2RI9nLiR+zSoxdG+bsdc+nFAcfbIqLRyXec06pFpO0jc7IdkGFo
WJqNA/30OR0lsMdP63wO5ADrLFYcVS0Z7QuLen4NRf8PkWugw6gIT+brtu3ERG4OLMEa8qxsH3sg
FrLkkOB7llW8d13LJZvsnUioOi/d4H77V5pUcTdRfaTKF8CUiOC9Od8+dVnYxJAIANkX2R1Q2dXC
HjfG5LgMy3TMMqXMYs6Gwzvnmy4gQLwsqUYrV4wTyoKotKesZXStu6hDmxUTYkdOyjLCRVaApL5b
4rjLlkdXnf9qU0D16ITpMmrkFd3NE6OfeA5+Ifo98Sua2aBCGmlMU6yDkPSo6wHEMjr0APOQlz3H
B7t4JW+8D3ascn+xmmyUoZ3qD3bnYBxEyikyBRX0dQzNtfYhKV3K/mXpMEndvyg1jSJ2mJyR4ptQ
bPakU4CDh0zmYkxyIcaYiu3nW/mALcT5BITnkh8/mJhPB6g7jPwmgfPkwT5/ii46KyUwJ3YD08Z3
cLpCOIU2qhFjtrpGs2npYbdy1CyDfVy3/BQ1CrSow8/PzPpE9rO1fkxCOlxxDW0WnCRtq6kp8bAA
9c49bzqaHgh5Q3+h8V9qOcv8Vw1oUcF+Hl+vzqnHErV1bYENbHwy2xz8C9y1bMrZBfYzOb9m4ZjP
VJSMHqcXtpgTUiMtbqAoTUcjcGgPL5cq/mQ8tprPYA03k9Fz91r7KXj4WUM8cBmm+Ei32X9j4/jC
loFNxZCH6U/2Pmq4L78qqwMjaTfxlnaf6Pj8JzBq5OnvZcSI1iinAWjzYrxwC3NOW530skhH+5KH
peVNOOZWbs1kuG47G4e4KmvTv3HsG+k4DsKrxQ+8BffHt+OKDEYeFX0nb46Aoe9GfHr3tcIR3BtM
Fi82daFOb52r+tJVNkOguPrcwA/24JdBO4id8IpV6jV98C6cCoJB7OZSRUuelfPgHteE8t10/Beg
H4ZxtGyi4BdfynhxZeFal0EFDGsyhZBqGo+R0Te54fhXcJbYzg8f9Rrwb+XCliKZJ3ig6xunUE8i
Vu/XZKhDlpJyo6hh98hCjrr4NdUh/6ADqvas5nFb5zj5suK2uVEYrgWpIFr2p955liLJY8VZuX++
rGUgdgiJx4u8a3NiDDOgZyTyItm/bz5tdpS/0bjf5ejhGO7N9e6Sh7dd+/LoMRTFTf0oGqaFIMqK
TaCfMwlYma30fOIV6C4WKdBJPAqA8TTq3mXnzeNsheLs3Th/W4pm/YgAcAo0CezHSqqRaIXOj+SG
u3qFeCSenXE83u27DpEF5+PDSkRCJ3f8ST28uctCb4KXQ+47LGMgeKPOZDf1fewGlRfcGPved6bh
ZMpc4dc5L1O/LIPeVm/OwLQk5s9uC41GeYtRjYeXZfU7P6eLW2FXPYRQlMJW6dE+64Blt5LonOWH
giq3FaGf6t7E+USWoGqoKgvvOGq5M980tb2/5q6N81nyjVBAOfX7h59qcMciMNjqVVI9FqkMsDvM
whUfc3GQXlIecQjUSb5s7WOAr2q7yU7JD+o36RO2t209XCGL/Oej8DIxPW7Mhmi5cmVpFqey5rxy
+TYP/3eQ0Pqx86mohHX4nOqvlKNf0lMie0yMSi18N6my4BCBrU4S9NqKqdsw6E/MBsV0YnPvOcBn
rGNBH3OMpugYEX5+Taf8xhOypYMq+fML06yI40yO0x3TeW0OBD5jc7zwWOTAD6c0TC/pgluQHMct
oUDJ6Cgxa97d0c0gXLcIRpIxmw+mo3qF3xr9XuzdStQofZeMYleE9jUNAFSu6Lw9NXh8dIQMn5cB
eYtSH60f2g7v6sC41LTWobI2SlJQX1iJK2gAWH5AfzkbYmdfDZq50tppbmMAE99Q/N+Ji6toTFjp
q37HCIHteygwZ4UJiCFkFxurKCU2xxlT5hJeqKbJX4tLAtrgQ4eylfi1BGYWvCR6mWwoo+5FihbA
Sl5eve60/qZ2S9Aed+iwA0k7nXZ6/hs8Kipqh/WHlkkwdA2ECSBeQBSiFMpQkYim93RNb5N4ak0f
nO0ySVTrPZxfv4GdbBNBrpzwJiqx4AIYnwU8ODJ6sfFw4aUvixTCElhHagSaiX6CA/2lHjniXfji
PveLUuuRHdlN7DzxFLDoQ9+OBUdvbU/0OuR7go2DTXl+JCd8Bt1DZK/ojA036d7aJXa6urzGFDNl
5e4OLcT5YkzG2xzZKJZmspfSlR/ljKExmVwJfpAzyihWwDArJCKZL4hjivCXCCrKooRNszc100Ah
RGagfqQ3cvwj944NE2uBOfugAo2qDy+3Z6jj5b/kO83QLXlDVNWlRQB3mKIhKs/tK2ViWX9ZJNqY
1WGCgMsGnirJR241gdSjMdIp/rAkpKT+3a5fAsEVT6sSVw1vSP+zqE260cKDzDo4pSSqW3GdtrQs
82jpf1A0/z92/1B7h2H2yhJEqGpuX/wbnnbkSw2jzcqUJPKl/nPuLIx2d7y0eLDt/2yWB8IU/cO+
rLYY32XvMDeQEqOfRP9ZircAUgKTC4dbpbI3sWcChJyRAIGrC4e8WYhRIa/cilllA7tWYIIuJ/YZ
Hn+KaAEW+Ye6ztkdtNX4ttH5NiQ1VIm73++SQrb4Zw4VYPKZS7pbg3ywsOtSzW+ho1JR74jH+keG
JlLhVVxbeNcX4f0/mgb2EqINJC59H2gUY+cuDstm4TCzyat5BqSsbdgkrHjonrOEl6eHxv/WyzIw
oktwHGswVKgLFDzfqkxVdE8GC5XOnrIjfrGQOk/ou1z+ZiFAZTSnvb53zrTAm/fnpf1Sq55sU1QO
Qtcy+CYOLPH40QYUywiQM+PAWZydfDR4Rfz12ylEd5BBgNeN2sbXr5keSOrfV8TjlNLxh+FCE7OL
9IF5rlEuhlj+kgDakavhHkdybjV+fSX1yXQW0dv8/cY1ao9+2EAOcZW3iMoHAfJQfomAixDaR+bz
P0SfinfBztcHVGA+bLilweN1FKGfbISE5ltXsoePll07AosghLFJbhonHdaO0JdQQoxypaiIHgX+
3XojTqzuBiPaXX+ty7kQ/SBWPKQlotl19Q4RvWesvwrsFgMo8ooqfWugBUfoX4J1F2Rogli9esrx
wfoZrmZAmoR0GHlwMvULQnHWR8sprflvF0tVfLSoEcQm3EG9yfd1JDcig5Mju5bU+0C1rmi5X2bu
Jflmu9HePqw8Xr7gQXxq0MCTBciGlXtfW1XjArQoEGqLc2oVqO5O+1Z73b0dTX+26W/KBY96ce4V
tGT+F3YM3QsdXIaniybOxmu326KFdjSLWCpY67XVMrp5MI3KwINvllQGqsFQWmZ174liKAi6KLoP
NSsHBLr8ZXT+lXBNvXtcptaRDBTlrmWBdnaHGNJl5J2GjUknYbmQ6YToU6juoNDVxmbDEC2qS6X9
X1ZHZ2NpZpj98pxTUq3ZWSojYhYbnVqLpWeHB8QDQzh/6gCuaYJ207jTEcD3wBOXV1tq1tMtpFR6
fgX6GTfIzv/EKksq2NCdiCKKYpH50IToM71/1B8hMmqH5dwKoMA84wqgQP7pNKWS/CwWudDkdpzR
EpbsTtWSNHdkHWea1bdQJ8tYTbG2w6qKekU3bUvGLjSLUBOkbmznhSrN4BiLSrT8Ho20GAIgrLmd
UNUB1BLiwZg2LXw2R1CQjXp918FlGDF8QsYlNa5xDCxDTLCSu7V7MUevod+MYvyhw5qaKygVnp/c
YAdDKK20gIPGsFwaIPQFUhEHk5cKNiAFfpNuBMSrhv3CrQ1Itovdv8dXXVx2NeDXh5MnFtV6eB3z
JIg4nWSuEkxYMqPin7XS2FSHceYfbxRz1HdOrATbjbgRaOjJIa1x27R5WqOwh3LNcsvCBWkpagmL
7AgoFjXImeUXOWJyUO7n/jVdcU7w4Ipqocu9lE8ZUZfVaMblTON/Sox1KQtAekKPHSYhEQFkH2UO
ljfRFu5S5mH81wu2y+jogs+1R0G6RJs1pBlB82N/qZC9QK4tC7F1vsznJ8fsIVFktWM/BsZsPdLi
Mt5ObzuBxg9OUcfIM77Z4J8qp4nfTTrDST2fzi4r8izR+OYUWRZLpkQFO3bn6Ju2mAgHeqWX/aSn
MIb3hSO/9iRDPqc2Hr15I+0LAVkY/ZeCL5vJMKzDxetVKQGxJJJbn6qCxSUHWIC5QrHeW4r8snwE
V4BAeMR2kRAPlO1XZ5q0KS7KnrLvTNqJptgmiGVsNA0ljRSKbSSz04EIqYLzZO3pkGz7s4/J6KcS
XXfOlbRKHYV+mkbrfhFHTEmK3Us8VM/BQ1gkM0Uf5bIS2LG8Qp4mMdEvOeybeMIwMpzViCQh6ma6
5wCW2fidsrssQ8u8aDHQGvfYp8IzWCVVmLKn/r2M8J+jaGik8NtdbLkBc+Ltc9Fzcf31W1u8p2up
4ZzO+Cfama9v3PULMRl6+TVUu+gDEJkYDWLbJMggWL5Xurk3Q7zAo7Hg0VH3hIMn2FH/OWQW3kdM
VRozzjRsIED58Q0sTbXHSC/dzz9/+Yygvkck060jaG2OesxSRy2c8DF2tIJ3hhUul401z99C8ESS
/IdmvKpiyq0wwhxEgFztyjgj/BYbbfH9u1wYwPUl6CDuECvi/4SBR6RPWe/UduxQSZ1LAW6zXfGT
qOeZ7PaHg3QD72RqCbLof9Iwiwy4Fj07xKDDjjVBje1uCLod65LjhKUwQ0kqmhCYNOISCIiSD66q
G3zq0RShunpc2uBOJpauArqsph45yPMgqb5f99MiFQu+dkIipe73mRC+AWbTyeyb/1J9BeybstqE
QROWKk9qGQRDnYY/48NR48eLJzq7u7jmszu8mVEefNKbjEiivMay1WmtFyrFKZR604V1nGgfm7fl
7BO7Gr08wMvW6NgEQD9E5xQnZB+SoI2O3kNE1NAAAFtuKcl3l57Tl16Sgatqxbq1d6/QvpZTnDp6
Diuk61/oRc5pJIfhhDGx8TWN6eSiKF2y3LcsIzJJYUmRoEJWV7TbMGdY3mqN+b1GM4OPqzZflgxV
MeZe9IAPxp42AThOyI28rim3Qv3+JLq8Ugb9Se90YGD/U+LPFsSTQx4Q710xlnL7ftbIeSZk27Zc
F122OotrS3ST1/O79FPPB/GfDyTlv4XrSsgZ/O8TYKEDAv6FvDHgMw1tf5mkBKOCzNdtVybRl+pC
Kjlx7W/F1gxchDG8zGHsWRx7DaeMjdKtnW1/HkfLWVj0YxoQbdqwWNuJEtEbXomWbJ0pOFfShFOj
U9IxOwh4HOksFZsES8BCfP6j5OTh7TxZdXzUj2ktPluskym84Mbwj9I3TP7SZSQduy+SVZ8UjoyR
w6IjTkjc+bQ4iDprXRSbfW+Yxt2pxj2RH4uoUNZnyE+vHMXli+93T81qJO0A39UbFwBa+GEcBdBM
EFR7X8dVXeQ8HGp28D1xVbpOe2MDwlE2rvpnxTqKc7771I+bgkp2MYD8VisOUW/wGz7SByjNLRqY
+Wb4qIMSrzu95IMjINR1txb4BF87LPiIKBL1eYr/qGgiZ1X9z89AsvkQBeo1uLg9GCOguq6OMF0u
UXf7Nl0XTQr9p7XN+0WQdDUN3X7z8M+ErkVZKrL4XDn1eUbl5fNpt6Bo9wY9Fuijw4dZ99lpQr6y
VH5zeZ2/H1j3njBLrMLwS/X1szYe1T/RgiUQTxBZrQZHHOKlcPriwAO8BGbz3nMiXD8R17Ja6pq5
lEByWIhzi4wtY3eHLqwO063qJPTdH3cYIh9EGoJZF+qwNflnJ6Om/K8BQ0aw6APzLLlr7QoiZB/S
C0bAu3IDOAZU5Mb+gQnSBqfFPLNDRaPO0VGFFGpqYAEgX0BmisNDruHhtMzOxlM1zDNev68jZpVo
KUPoKO3gOZABiM1PuqkARnxa53ob98prI5CqK43zbK56q8VwcfX5AGgwpawXtBFyKKrJabznXiZH
5hogrZXs49Q4wnNpYXMV2TKXcV67nasDx2fn+aAHpYGgFJItPXKq9v6fpzkA18617sB+Z8AQUWwu
FAIw4x2D2dQmU3L3dCOqbWR3LHhqm4A9C+mtr4sUfyHbDnUJmyyiprChSvXUO52p5ENLY5SdPztN
SwDQvaF4S2eW7vM29RFg+pJo+tq6VMIkNa4m6HxuHlSzIxNCXWZapcAs+mJUJaTkSVfn9pelkzm7
H9szfUmLD0tMOQWd0csO8nLO7LJQxUrxpqDGMYDVhzfTjr54PG+9q9c4AXxRGDWRhdEbmCjDT6To
FuKgWPPb801Ri1KOHTOtT1tIAAuKMiZQDplgA39qp7jPNYmz4TqK6NBL6/Qxv84de7TYYcjz3VCQ
XdkrRMwwr668n8XhidBqt/1quBZM6Rq6AyqO9HYRlvt6cnf+FcevchJEMqK/ucqcJ90eeHfOchIi
kpFgqzW53awBYQjMvl43/aZqQtl+20Zsmn5N8R8FTKFGqn3yC5ebuHn2UrxY5W6P9x/JjOxt5niG
/8FScivF7d2DYGQfXUv+oXbyDsWCb5+8Lh6lFuBabNv/sdxgNJHwkd/ohSsFEw89nePmufRuVmk6
rZZaTuTAm1c/plkZewJ0gJOjxEul3apEKkJfS63GiKxtR6FmP36cTdrnklMlfHqeH2RyM+Aw+wDM
4HF5lTBnqacaJ89u8UDQT/4FWpPteGCdpVrL0BqBeBVYlD3p/N6dLQyOlXAydrV0+ZFUCQ6DfkHY
VdeQHyHGQZwHg9UFDUqc3b/EXL/+aroG25Bb7QmxDtNGiWK1G/J9vjNw7Sj7iwryhMzQVkyS/MWj
nI41BOZTVMU6sqlKixzagmbhuJKJZ2h4Hx/6VKTH/fcTvjwKuqv32QajlOSh/P/Lu1qsApDbgkg4
Ctj7Nx9J3t3p9wkpIlX+/Bfg19ntevqN8/jLWV63XsO+FGFR84fBUkIHC7Yf2rHEzpZhHTlQl9Ry
Bwhlzbj6VALYESwZbVvL2YulB+bP5LxKND6F4mX5lLGcEvlAjKbmf03KkztWMTD9kcimlifRD2zP
O01jNeLFk5lNHVHu/nvc8wozB6r77W+xy9QOEqwkUDSnIW3MJzkHEVIieiiInng2rpaHxpgHs/2e
avBfJvjRHj0Xpb5TOKbFdQVejKNBtUU11kGvLhtGkrpY41Fw5QNXzrUKPyH2w62iC5mBA9HSzD4t
ouM75otg7E1vsh1V6LPZ0Fv0v7zqkf5aT+JVWgdv4bHqwXF8h7xMJI0SI+Sx8N4xcfD4ewZNTInV
nGg1PdMvoV2weGvm6tTZ72xgtcUOf1hz3pXhJOQrMnYlgCF1yeMgsjuyp73XU/+EOf+lySBq/hK5
L5JDHMYOOLuD5JT6nDZuFnx6FqsnENqib/1TdxZCFL/U/AS+XDU4IacGyDSmYWjdPhySpHtT7X5C
XUSMqDYuwWWbsbDPScjGGoW6QyBtJvhWLm2adPcs+5nL/GT8dwmxu+TQA1hfz7MkNmySHJ/nBB/x
NLjbDRB0KR0EiSnNEPmXjV8igwB9T6wY/DCJs+aungRMLmP8FJk9m2sUz6iS3I8nPXIeaYIkWeoI
Hml0x/yRXo08lDIXvlhzD5c0g77A4h1xwzsH4wWhoAa3sJ8mntMJlS6w4lCRbrc6L4DJLPDI7QaB
EmeBONXQoSHZjpRdOYERG1DyAA60VXJxbo8g9S8RY6o9mQYqsJAJ5QlrFW7x61kNCdAEZZL3UD9e
NfHYazr9hqphjEfV7Hb5LflkNwksFXrLKjmD3CgKi+PNHsDDtxsTRFWB9tfZinnPHVi+JscmEECw
RS6WUyByomqM7N3IBj4XlhibZD1cdUpw15zf+2M6y2ThyLKsHWq9ewOCUXeXahFYDWlmfDQlLZ9Y
aQrLhsbAjqTyLL3O+fQfzqTBoBJ/JQBB0lWwMicYcVB4nIhtKCFvCGgeSWtyudHq0W0+fv4gy+9O
CUve73boM45fY7cA1XcCKgmvzND66hDyI/D1cqXf2Ux4qpnWUPbscZIPkPl2BOk7aSD86UhTYiyx
rI3K59y+NkloPii0YI5uzxKMHKHllEr5LlOQXhD3kulxtufJYQLwr6NbnrajFTgbNYweM2bkTSa8
1wjGWGGfbhZ4UtyNb1uRHFiD/Lw9iyGKRg6RF/lCGEi4wgidAEazGjJQBEscwmntd6X2BADZmfIl
o5/orOIvGSXQr3Q/F0qNwEVny5WX0sIDHJfCyWNg9BpY0LKR2ldzna7V+99oPJoqsAGluoqJaCf3
DcQSrjQ2+zSvRJFBUkO72kIzgO6Tu00tmLXYl530WQrLuHbBqUT5VCzL2zaC5q0G4+MCMRbJhbFO
LhVorlRMmJRgU3xNfOQlk4KCKB5+Z3Fqmk/cqdwDUu1ASJUrge92ymI4hM1UkMBUJJeM95WCRJOq
5Wrru9GvbdnMoaE1Ga4JkKHLe6Ls5K5NtRMc9uzCTrJlRoeRtpBDt8P8cGzMsNqHi+jfoCMB3TTL
PIbMdSrbb7j1oCVbbDTuVxx2z8A/7ynkarczf7p4NRsAk/kYimaGzLOAETkzxtiRbYes4Fx0AX9r
QLXQgb9LByTU25geSoikFrzDAK4AxncDnuEmHu+VSACmE0ywKcOCbzDWrgCd99bol8Qd9X+jR03X
J4NZIHnuYxBSiAbCwgeAXd3zwtKUncC6SGnSRANfiJcoQjeZWndA5Ke9USJ2Yke/Hi7XGqT5ZMzw
bjD9jqo9aNyv75YE5HlFWAM+rGQ2Pt2NadLbDneKmXd2ePWY45+qILU5Yr/ARe1IFKuzexRUj04j
yIkeUSDIDuGGzsFsDwiM+mIvx9StoW7gpgRi9gWAdivtWPVE2fU8fVWeJbKAJnJhMkEV7TRJuEtx
lTCLbIEf8fobjSyo2JSSwoAXslYdK6GAr9ofzI6Dbiz3Ek6WuZX41U6UhvtYxaju5xONZ8fN+fST
mHoRIXAnIe9F6YzEdcNQTItwtLcZgwSJwMD1jWeHT7a+l8lV/ysQjBpjl0NZyvDFhswq4F4PHr1y
1QnfmAF2bqdAOQOl8fAeSPki7H6grW7WqaAGlmmcT+Y++JNeHGkhNIp4coehNt8GcqBbkGv24ZHd
gV6LhccHsyvtVp7xnAinSjfYKDt7z89v6ejPkR7sptagcDJE31n+/X+z195ErsruJTfTSeee6hrq
FvU+qUBtm5jWcmH3zzNbeWEAib3Ed35jgelwtk5T0qYaNfoKM1X0Xd3DMd86KgaGbz12l/rHG1sR
1w03M8HftzdFZTM5cB+yOtQ/lQPqJkyWxTOLYRsqnJk74m43Hn9M0CCdJ1cS0q2d1/oNOss9lO7X
7B1zSJ4UYioOqyXSwE1DI01qGA0nAqToBEcEPnnvWAV3F5DPovgg5YeHQUADnhEVWAc8uJPyCxgK
bfdQ1CBmivRYHBP78tMFqR5NoCpEHLRXbFPszpOCiTCqhyV2n6rHu4yShIkuhNxwvE9utPV0AIDO
TQs4LP83w94msaUlHOhfYdH1jQBbUApVi3KdMCvKi7SuYkviacKDRSnnRIP6vXE2JBKtMGluhHYw
7exwMx1dHRZCDcDyXmAVG5y+exfff3OzqZURz3KAITS3KYsUle46rIfjQiBWSnkEscIUqyCQUYTe
ZT5+l5toxzO/qCZ41yWx/+zpjg2H78ZW7HwBqCsLF0BduyARNfzOoXGpRXMnbdbhSdVJIO8qYNS9
VYj6uau/68pI0mn7t4mkEgwDrcSPkz48j6yO1fro4VBk+Mw9pGp6JpX1eM8wwkPHDs+bSbklr4nS
6U7VcQHTP/PAPSOWyPp3vGKEG+gCQFKWS47sC1VyAs5KnbNR/144iNAqvr9Wamfr2eDbuXNbIbWM
dVYiJk4J5bFPHb6qQwLmDX9+ZTHqkW1tWYDUxd/SxPFgmlgeHPh90wHVLDSv1t+KD9vyQbTLDB4q
iY6+H0liPbgDLPUkLCDhqL09jIqjZEh6UQhSpOa8xByavbq3lpBmRAnXGqQpUW3n3691cFrQEXQ4
KXGSNraONYLo74y+MEZC1o1oyHYc+eReLnZVokiQ6EGKHdpaXHdGhm4gluFC7KK910VnZVKLedCm
hUH65IvENytJC3MfBjL8qox9z6RNSwS7Qr6XIj6yrpeUgV+AJ5dg1MIP5EsGTYziHe8AQ/hZxvBZ
qYv+7ZTjcAK6dnkIomRxtdlVqUQlLkAClDtRFFgFp97b5k9F19RKK+JCL0VSrRe8Q739XatFNUHH
VUvnTzXd9XJanJkQm2E3GifYZ7tm1MJkWVYFTyzM2f9QuIwqd/+CO65aQ2TbqVjeQ3GhEcnKeZF0
X15S40h4fV0IeSxsDuBwS8AhBxzFqIIrU+8ayvWHtFey2zleVWQMnMLEPBCu3/tjheDjKA7tX2rf
new1YocpT/IEEMY3BI9ujx5lyk5uucB/3iJgItgwhhgzyz/2YAngT13cP5sgdowEoogG6wvfBy3t
sVd9FLapzcWX0C8XZCvcZxgWUxI1bZhmf1Kbv2R/cj5CGqka/6K98Oy511G3wcYs3dMj5WWJxIGa
CZ6AQBnJQLJW6XPXRiauYk8WVh5TMGfJwcEmRQA0/MXjZZtPyGBZiVRZeQNalCqzF0lUysHd03NM
wcAym21RwY2CE0KWwO6dtZCQaPllcebDYMVp6IydGfEcmdmgKJIH81PR+oY8Th8GQRGzvh9OJBFm
P2nTnagOJ4CcJX1QUp3thZ0qChpOvnwhmrrKFRPt8tjzs0OPJllF6ZwQCNfswKTtHDbnvhLshfFV
Fenm8Skj/b2surEyenIfvc9Y0Z1VbjPIp//iro70Oa6JL6OraXhnS3ADW5S+iOJAR3tMjsdECqCC
LCD0g/kgDmIOC+bM6uSE+WHywmQsFOir7spwZ1x+gCz4aMImhNTQc+7ZrCwpfEnOyQqakouMSfF/
cyKaYwsAwQTs3VCF3ElY+jzV5TBy5LdXpSx8OcOGO2sH18txcnnL4BeprD4OVwLZSEeQICPWO3r5
EGeTWUoZss48rAx3Trxpy6wjlSmIGoC8sHsth/wByoCFodhCIFo3+z/M6mKhi+pz/YYaUd0Nry3Q
89+bfmAJeqN4tACh8zv08f7/PteDtFHp5X8qRja8sZZJOZ6PjlsCf+mwiaUe983VUFJh5XKuxaGJ
h+INJFWfPZ1cwNKO+Qim8JOtMJ1dE0rLb/cDbYwYUjWTI6ZJUi0HCLxwz/F2v3QuRIEigcpKrD8a
WjSrt4JlOeVm0IGw78HZrTqWgJAgr/5SggMqmn4F/KPQtQBainIoRJRWi4tX0ZPxklUpSMm5kYLT
7jvIvXS30EVxPgt/ElAj0RV6qzs6SWdWhDKl/AoLCFHzgyZ8XKP/fktIycauqocJIKsraDU9n44D
TVH4IHiKYJmqyK+9kXljEGdYdWD7SXi9e2ulcrsz63sNrsLOgkvL6t3pJx8Kaa0/G7KO+UYlYr3R
Bt1vXdnAZYsrQT81/DpZQy8IkQkYD7tjb2BspCJ3rVAj0iqt+/Cuc0Z77aP4Q+YWrlrx8osJdJUj
RSoJ/Q3QhXzgV/bVSvTNwslvfDJH2YbhV38GR3p2odIh4/+LYAJRykF6y+K0PySj6APLQaQXtR6E
PXMZzT0d1hnensb+i5ysE+K5JKq5zWoLKzngr5JiqzZrtWybMcJ7jCLxIf8B3Bjs/UcPl1DcgvcU
M0Vue2+KWHUenEkY0M4K8Sodg2Jl9+rzPwdceSF9mT4LhugJX5E2eDcioiKPjD4QvFbTtfXWmYUN
tTWZB2QIQgt2L0P3S2pi6bFmY/VzrTWjoAGNhQb+DFoA/72cYHf+qFYCHkry1A6Kf6Ncafd7/z79
2LEJjO5Sv34S05GgY+18iEx+JE8l+g1Oyx2HRa6JUP4xMa4QkHzodkF2XzQiyNg4qw2Itwvaq1A4
ikTETMlpljnC5hnCmaS2PJ10yIPI5rrv5YHFMGXsR2ej54Hd7E7vpLV59N/PXHwNDIViTSBYySyQ
sQfUcWjmXLdmnQb9zRtM6biZGuBbx1Lc+kx6PubkZlpHNbk73PBwJRRuU3W2MGG+07arVZs/yiFS
TH632S01ASxJ47vlvLL6KLHsA9ddZaQ13RUCbspJJxTXM7aYjZ0VnRWYWUDDNJJyPwi/5VKpOR5d
zHfutxxFZTmw4JCryYkf1qA7y0D3b8T5bfmr/r76RABh3yvuAI5o5kz4ZdBM6AouBnKfCOvh/EJe
RH2ofu0l9qLJIMKheTsnS5l3AKHmY6dHwxDCnGLhs9JkJHmEF+ZYgSxNM7LKHtHayAEC4j35wJh/
m2BOVt7XecCxB8rZsrW06UTgML8biSu59HoE/krIbCZ0eYdX4x+6/H/S/J41zhLtCpHpbwr/x4/a
DsgqbIYRMzwwd4xcE+eckD+b50F8fttKT2/+ooDH2oZQxO2cDmqS69e0Thv444P4ao6MkAqeyOLN
hv3+l5//KQ46xCJDN59L54FWLXElDM3yIQlfE624JLSTInXTd8FgvFzrQyQP/jxlYKBU/ENOyU4U
/SnJw3SG2HjUFYNW89720iXuoQjq1hrr9JdmXcGnTRnCi8Vcnjc9g0Wa9MYuzpvGH/BW29LLC5Wx
FA7IfhoPWvyzaIG7hgqsUFlWok7rLk0cJsL36oderNkBFgmjzHiKQ7m/4z3YdZTh5jAMFCkrhAFw
D9WLSLVjX1qfwmIIchZ5E3vAvm8mG44LMnMs1VxboIFBrVcB+4mUuwmS6nD0L6KIROn266HOXYmZ
X9wjkN6qgHD8bbL54eFkin2wkgTRZMMWLhmH67cTg/9+h9mn/HxPXg36OdCdkGarG5Qv4UwVr9x4
AY0fHrpmwuiD5XJS5Kg8cKTESbHRxtKbcD/6EpSiH0c5SkcMtjXNfoqI0qdajAk17upIMDK+3I66
wjbfjmFfwhT8+8auw44wKJvK9hk5H7hBuAV6XssKDx1/BtojUohIhreiLHluw2KrP6xFZf5c513T
v37BUxb/DG5hTydXHKtER9PeRK5xC/eBQ92BghP+g7jEr2VVrmFJG1t/Abx3iTw8vulKMUnZPMda
s47uWFkN8Jmrg8Z+zW/OoQv7N0D4DtwBS85SyIwkg6XRsrktIrVkpB382Ja5uF40TRf2Zh6mL0Kt
qAP3y1y8W87H8dshBdkKsGdaOV7NbE6L0z/9pwWGgCks2gYBz4I03mugfRBY+pi5YIIOdQJ/idNI
Yp5GP20xEEUmbburiGFqc32rEBCkh7aLkZCsTamvQJj2nwDq+CyGltU53FIPiv5vJJkCWuYLyk0Y
bqblZv/7UPkobJzgVG0TwDKJ1NI973foYtGL/32hQYHcjoExBSUKTqELVtsvHfy7YOKZFYFElkBd
A5EUAURM6E6haG1s7vogNMQX4b3SsdDl5voqHdb9Ve072FtmUqxjpUlJIOJlweGpZLtO2ztnyYck
aFo7umDcd1wnTIKMsFgdROJ+yDxJghXvMuHA/ALuCvVbHlXIBWDqcYpUr48WSUWWbFZWoAkVQdzx
zqyLJZuudSgj//qYsrYBuPIwBqZ5LfE7LfZuBPVNpym0qr4/xUZ49aCqqBMCRBRJ098y4y6e8mC3
h0gS0cybDiTq5jNtQeCWzqwSwOa1NFNOtjbra1GpIPoZ1IF1CyrxApezx+mRoN+3zyZLJzEDuzUs
jWTM5xU1CAhs5SjeeCHL+ndd2sNkNwQ+LTc/WbyeD05SYI1LsYSsgq57PV0vPb+Bnub5NpiszBdO
SnBgE0KXhPXmJ3JES19Je0z9ErhhPZIMXiJ7hFJsbMkvhscMRogs+QO+9NPDWsGTHN6nptMlavdI
hbr5BBMOez7UKCq64EnhtXgHfchW6ULke74gj0iXjwfy24dcc0Wpu3SC6Vm4vfMnpT0EWaRJ5q+M
D3UZYJ25vg02FWBMskuuLvmGzHc4iAJGKU8NppI2msFgzRLgpvma+Ir+QJRL2iNV/pxd81joHmsG
6PytkiJePZVPFLh3MspUjBluDo4V9p2r5tov+Be+5sIt8W6IwkVJnAQl0gGoZcV/vczNy4EkPubl
UlvJ6xs4N0yIYkIbsc5X+1pdG6rdZIi6HH9eKlx639WtITqG140q1BsJvh4e6BIKJbAWVNkPpl6i
4HsoWj1mBvkmtwwyWvmspccbA5QzriDf5kFwipKVRFJWREEHavxnGihHTYQfvmfSCjjCYVDNxRnd
Vuc17oGwCPXlGShdq8ziKA0Kw1aTbN7SFTSxWXJIuH0OGEHxl/bYZCRIVUm4BShxOFM3PLoPXF8n
qaffT9jcQv6s0RC2ZbUzMTonWqjmHiYjFw+3Z9pDwn5dEAqoXN7u+udSO675VcXnHtN8N6XHCHMp
XYlo+OO6SN/s52Wm92RQ2/MrYJjHCZy2MhnFQoZc860Dph/AMJAtgAtNWN0HC+E2UGNH7EVTOHkb
4u11OPHVYKIYEj8ey5UFF3eqJZ9iLdI1+cON7Zn/9yiiJNhHgNEYrEaBE3FqqtoINlVjNLLmvsyV
UEEJED+90AAV+Uju44w9S1nL8daoWpWvph8NflJn1bCSQe7yCJ0V1SbwZ0JCKONqJOvU/Du7B3V4
pserveKsD2e1usVHtfRQJsnbGWb23lb+6N2kC8lCreYzzXoQVNj4Ql7ME+DTDteVWJZgZbg9YqQz
1JJCfpcrxvQf05o8UsdXn5kedamg1jJ4JfJTwiUArPzzdOgHZyDLiiaSiUuv2Js0ui2EisuV4a3o
f4rtxQPKCzWOgd4qXd3GO3nw6bRnbe/z+QRTl4TlmfcVDKlBrNVpg4GhjBQdt6AWJdHf4cLd/0dG
/Mtb16GSShYomA7bn6rO6DRp35DELlLUaWj1BtUYPGi/S+BMOBzWWgKpLXEpGWTpNj+bXd4Yd6qX
l2cDwkXd+BLDxetxToKz5+1pT0NzCZ2v8ncA0ffkg+H3NSJQREe7ZoCUPdQRF3GcmDiz/vzHFx5p
xeMj68iUTj/irkeDh3F+bkf3obzgaoSS7Y5+XWXHfulWeBEGaEnhf13C+3FRYNLdNHJmYK6SbvWW
beLvqNA811jl+TcutyyBADjIahnFQpMph9yU47cF8ZJR1enMYGF5jTH0tk3LJJtcUXe58vRXlnvL
NISKiyrTBMhYSKhAkRo3ZihV/kcr/dZYXndAW/QAQ7idxpXA+g6kTaYR4YrMvTciYEX7C6dT+NNz
LzHDy/o4MpepgMlXviu/U4maWeGu+tjQgy4neteRUltzmDTtALNma0kwGE35DfybFHAfO76Fmj2q
oQ0hTxSjfL0xY7I869YVOuIIjiIg3ZITw2qY/cR2JgtDppu/K++I09iOQhe/nD23hU1XpugRPDQv
gQ9zjZGmXK58HwOpvbZpgv3wkcZKZV31UbGRwy6hEgdt8+fJ6EYRdldSAj0+FPu41et6CJ05fw7E
YJX4Fo/PHvzUPbmOopngWWMyr+P/H5nkVeSZPVfZEwi4UoP/+A5r8Uo+TK1KElJSVONAoeFi5uYc
/thAIxuo7swbrcCiQ9mDqIIB8q5VOnAp2e1ZK4gSkCWrdnUD+erdaaTGroITrDyyr+2U3omU0QM1
s9Y0AGlph2qS0tlnBX1tF8XGXcNsNHp5c/Up/6ycImA0pyWA2pyXJAtXtszx9tHX7DiAqPwmuJW4
8rZ1Fblqcej/sojcXDM5R8FNWEbLTknbyt7QksCNZ1aosRIvtpt3dJQ9O9CCBUbVt/pU1C88DBFR
vkfucCW/X0SfONHWHGgQqcDs0H3uxxN/liRiqJm2FiPYOvnkkfOLJt4JLrkfSOuPnCDiUgU+221G
HUbucrCoVTYJxEhn/JI3mmaH3aaIwk1ceMchYHY1cI6RThlZLAw0KNAqLtxseIQ68TVCSxttIY9D
WqWVWIuWHWDeiNAJIfZyl54pJ5mqiKzhffKlsGXrmT1gJ77t9q5lhOnplge4gNQ97ZZWFvmwgnDW
K+eJ0lsFpCbrym31evCxMX0k/j2GBzG3gFaVE/P0mhyCtscH0QiVJ7dTrBzg2rGy2E6sNAOcVkbC
DjY9+rKxGDhRiYHGtyNv/hKADhu2+F9LFLkM412xlRZkoFYCNIlFaegZ93a3/sbeQ5C97mdmTIMg
t/0piFe1DtHQ5q4jmuPOSE+srD3M9bGZONc9/+FZc+dndoqglX+A/MuYfaUCvQiMZoB4AVG4QEy9
6tytrGxXnJOWUJoLpqpKxWRKU1f1L2TNiis3c4T9hYLYuGl0MMig87xqKZ46p+NVPM7Wn41O6QZg
7BN+ElY7ky/faBoQBOWOAdpv2+oNEMSXKXyu/MWEpJ/lYYQY6NpscJ+3mHEejhkVVanF+1rdU1xl
dlu58Zi2fIRtGMXednx5O+RJVIBnBqej3/bXuczzlNfKYBh4LTKhPGAphKaf7pIgoUYKN9I42R3i
0cQR8pJDzkOOEXaFGfABMBH6gqg2VoVRuNWcUKyGuDmH6Kk4HY+17jdMwxUw/aX4mGaLB2aceHip
QlKrcnBacZ1SbK23E4XLyGRY213nquDLaJhXqfKHu0BVd9YvGmUTOLEddZ7kA2RrrEcOdwAd/SY0
B0l/XDiqjz1tqvq60u99Sgejhe/1BKWPUt5I+jT4ou6o4Btc9VmPEdEW+C0sKxq+aV8y6sP+m6oS
oo661OBkDGCNQ7v0gM27+w64mxocQw+2lNqlqoB5kUdoXpR4n4k6JeitdM5Heb1b1O7++kD0K3da
RzDbetL7dXmOoTCv8eRYgSNFZQwLIUKvO5BtXVW/X+p+obzaZtODBA9GMTtkzmEUoTvvHo2MH51r
psvbLqzT+1sPFRN+Q48nhj3lAOwhAwl0kDu8OhO5HbckxaZaKGXy4Oi0nr7NJQn3yP8tS7h2pqzS
/ehWOLz8hM1sa4QUEpAHEAyzBV16J1lNsuSGZKe2F3dcyxeh6PqrYFnXe52BIT+jQ3hIC+8zMOxs
5TSPqZTs5N/98UNEYzZohCU8WNNxEEVB+RtZltct+Fuyg7jIPcC/UqFIyLWxYHLUu+aYtA0s8J8M
TGobMEOaj9Ix2m1rORAycG25m7rQaaf7Y9JMNCILOtSBZBDLh663JcaR1FJl5HZuYiqdatyrMiKl
ziJ/B2+vPKJxKpGX1wdQLrAGdTtL63vabYQevtYiANvjK8GLGiKdo2dVkw5B1Pe7FFERztJOm9pZ
TfleeH4iNN/tjnAxKmHX2rrOUJp38FQ6yiEC3ReU5/AL0nU+MqeuqHkfZv1VE1li0/3iF31xJE8N
qINC1RppbMrpEKw2QkkM4JfZc+1vdmuf2wG2GU8KfFB2Vs0OBo/Qf+QzNOmO1pfk6UX0gbiZe0Yv
D4MmROWLNO3jd56YIEA9q/1iwDZXn9ai+4wMQWPX+5nhJuSaTcEy3vpGwTNEz3XT1FULMDafyT1d
oAryfNPftYIQg4UuuoZQkfMtoA7M62d2T3IpO+4T7hPZfWrnb0UXrYJaiOVEcV8pJ95b78B++uvi
zCIOMhSdkR8FMH59TMYS2ENkvMig9JsR1MNg371bxqZ6S5sO8gdcDrbTlhr1lZ/B4o4Zzu5J1lED
agYZM/QcLhrL2+45YvhdUmmzhh7xiejTyPkUUyFIIaMP4aTPr87EWp/I2pYxGxcGuh3S83iLqmAg
lR9HviVE0oLpDj+7DXzFL9Xn3lvftPF/BJbMJ57pKWZmrevV4F64n3bu/kMrFYLr6vzaFjKYK4gF
4KV4B3oO4e1njysrsXmVsdc5nI6MTDYqhwXU2gMCwhb2QiZZrWXtCWJjneCTQffgFG2j4NWYkPHX
cQE/J6DOAAvoQkFhlC2+SQUB7t2ETn1Rht7tSwCqtSxIkUXgQBtyqbcpLdGW9z1B/iuRe+68/KZz
VKBrZX+kfr1/5if2CtWnWRd3FqNVzgY8SVystEqV67Mk8kqXKAfDueX0UPBx6QXIhHG0nj2qgMXv
IUEonm+mc8a/WrIv5AJ7qEJRn2Gy4b8d7soqZrjBUI0x1ttV+oht2sEzhS0j1dXyQqLz/8/zad/d
1sgwAre3lmkmgeUdp7nLPms5lCJOyIdEvZzl5ZPOayqulXZB6MDTvMqGACQvl4wB1WXpabBhWdUq
wNDREXZG2dcX1XwJFYlEDJkOMFMu5TkIq1I8CgCdvc3YUh0A/8yfx8e6zGfQ0QC8xTPsjSeEJm93
7yvLw38p3qBxe6eTXeP3NqRtCvPuyPO6TBcxJDBTumZtVi+l+l+F+I+oPgCtIeN2IDWIBmcgZ+2K
ZwQSfmSjUCkl2OBBVnFb4jn/YPft9qbGMO9jv9HbHHBaASUqIFq4fD/jB5K8jAhfnzQBHP70lfdf
r6m86WF+E4wFR3om8RNIRSzfj9m28RkoqRYD+m5mTUcaj3Wwk06q9Y0wv3+bV8WZK+gkR8vlSREy
XQGZSRwkIaVSO7Hb/nzhNL+PE2iaoJZCYsu2h2BF3qhyB48G1521anlDmWrYf5L895G0AEgdWa5I
WmBqrfDX04Edv8AILew8cR6TUzBzlT37uDt0Lz403+zir9SdDZqWCSO3Kj1jIcu/2teMp7kI63Cw
2GW0MiRi/9FCwArtFq2OZFh8LqgLv9L1hh+VDJaFStshtZEq8UQmcbhXubvG7lQHwJgSoCa2xesw
+KITwnG2gOZwOJR3oMQnYjiCF1Po32wN8qkexxy6w4SV3TeIiSG0pcODiqPSmozzaF1LtB7HsX89
UWVFYwmVvWK/ajHyNpx/vA9r0srz/VJGHHlFQPHPpPTXfR97sCgmHNjX/3SIz0VsLfua92yPV6To
Hk60KR0Jt8fPmD6hysPZ/nkxcHWqulsmAPFUNvx/8zKAoO/dKcgJZHxH/DlsL21uIdPJph/e8NMC
oGNwXaz16POvHOjHJjzV86ZhrDY1KfdrZcHcnxWEpMf/EeC13wp06gK4I5P1NPkN2pg/E8JSxdtc
tuW5pjCEVosVAiZK8SBAi+WmQjR0YAY0h9CCiXfukUQgelmdIitbQPW3vmXBY4wZwG+mtPmYCymX
izGww39VTrzaqvdH1qm/QMiMrS8GjS/2Z9qfYwJbshJGzb31j5J2MIR9REjhdtOeWzmQmLbs/j/T
C3k/vFnV6ncP5XjmIi97aAMYWU4cCRuGU+y2eMGL37SshXoV5c1WC5rtxYiqS7ZrTt39sztUh5Xg
D/XfSup1SvGyEuuSGD4IfFiryB4Z8FAhmfRZwo/xGzkMdAtWv19q5rwgQOiYWaTlzKRM3XmvUSWf
DRs6sF2JXNyNGaz571vZ5OnL8bqgsUMEhXldog52/S7wE5Nj2INJ0ZLcc6ur2+NABz/j31TENoXW
jM52wgAlgiOk/X9UFuoFRrPSnh3ffSUKiRPKEVbvgcb4vAOnOD0hHmLzeW3c/plZ+A9ZC7zdJJLY
/r749muOz6ZtAno424aQCva7/JmS7vJ0hmj8WO0AKjzBVvmNDgfa0UTPvmQMhnhOCVROPZjSqZlS
j/yL611HnSyoIYz4WqXugBXQUhngQNqrAeLbt38bXmVAUKUdZV5aWnOgu8k7MIx/T3pPCySXNhxW
Ali+E2+OA/qT+zf+YXw1jef22+ZVLZmVI7Q+We11wob55w6ZXDnHWGA1JsEJbmVQzn1uE2/aLtQl
LXTbwJZJn17ArforwcBqXqPMZD6GyYasJCD6Lza1I4QstShr0dTRDJyx24FdnPME0CBXwJ3b3Ls0
MBvPzzIoRzAOS9rlL/qPaHzpeiE05vf63o9kIlnaZQd+k1ZiopbxzjcwE1Fb++A1D/QMHbkjBQju
+4NT6axf32DF8Yas9lnhspdpKiMoN4VNMCst5VIJXXKhtZ0OzZE0UdJmhiXixS5NwyoZ4lH/VjDy
w+xOcH50rSJGlr7P3uHO8QK4WYTZsQFULa+3292iE6ubdjr1tGXym6tjSLeHegpW+JLIOM4Mfasb
N97aDFFW5Ykq305TNU9gV0k177DZaCTQez+Eifk7nwPyCFCcKmsPy8lde6w5cnj+47nNXMhR4EHg
d4OhhrjlJi07x3YqyGq3/q+Je4/awBWDzNDMFnhrttUB1OD9ZPyjW8zAqkkMOLSRXCKh054NPtwG
ZQblcRAkpwrSrZA8d3oImWJOcE8013DSV4tJ5GIcuHuiaqc2PDPTYfz+dB0Q0gJRS2ymxHpLbP5L
fv5lCvREQ68M0hjVF9i8OV2C/ekg6Sq/ZA7vxRETvinUvHhWCxtJWGPoWoi5iQt9+JIXd1G2iHmk
/nDw/GJ46cZ4dcMWa64iVh76Mji2+uPUMC4lQ9/QM7gRHXOOTKwUWwcTT8nE2S0yL/rzzoSYQMY3
xDB+1yEzRoybhFUUZYdbStLSXAcBjPVPM8gPBGJs2DwsUteldRB46ITZ/9trGnlz86YE03cZibt3
nIsadJEFI25JeW44p/MLva5QdB6gtuxOnbKFEVRFDzWPG2oopQ7J89SPrOoxzQ04AqPE7uKoGbK1
isAhKncgiiSyaACAfbCTbJxbvH+jCV2tNgC2mM24qEfeqMy4DGeI+XKSHrI/Rw1y13XCJEToNLzG
ZceFOBZ1R+NdcbiO1BfTeDjHKyzMEQvJoxhtqApswEyPC0tSLD0kuHxUughayrwDdvFSDn4zIG55
fvWwR3V6fsN1U8zY8hokHZOUwe5WWSLhKMUJIf5lhCjQH/SLu3XpWqgMzmmmMlKKnxIQCtp7j1I8
Pft01C32jpP+y7NKCDaSV2K4pwF1F0ezdzyMTln8NVaTtmEu54lcXlWj80BNwn32rxhccqFkb0Qi
nEKXKlWTJGmylOd6GkY/CAZCMMKHy/8ScPI0/MF3rVS1sI+YSKlW/+xd3qJO+H5S6gnsUDe9RomR
JXMFgrk/nSHEMHsB6u/fDcZW/tuHWa83Kl3ufQARb38iztxxNRidoebmUQRw6DnzzdNg0+SjS1GE
i1lshGc4P7DVUf/RaFjVFTEbDbkKZuhr2cxhXdZeq/8MpK8BDDlozzVtdB3ZvkO4BjNbi8F5N9nF
Aqgy7GfLQ2TJOggPWY+YxMgEzI3WEX12qSoUkss4RkNHs/Cgy4Z4E8tIymRacw6/ACpYNMQdgUoz
QVh9S7dvWUHnbv4Fm6JITKhr9hPKgOhzoV0PI7RNwQAqGHLUSwTInkLFSUR+9ADIJH4kQ4t2LnRB
wg6cmmCr2whwMgOKiPsOiV61ZWiE5ie0sj3lLRLp+TQjSzFpvDgx1x9wvWxxF6mvG2GD7Gox521f
JKe0rswzvaYC0aj8+FxpEb3FOPJPECJdkyJVcvyQ3tbXUKLQUaHJglkHlmNnH9MUrc+/nLXx0A1P
GmV2+TeoUtKQsnzwIgxz/tat3wvw8VS5f2j9Q7OxDvo9SnXmgEiXhBrS3gdK11UfiA2tdB4Lja+G
R7u0jvCZXqv3CZY/G/Rw90Vh+r/pTIqpyhluMZoY+Tfhy3I5clzH/pGMA5nzL1m1WTGi6uJW9q+u
MVdOXfPZQ3ElHdx/STVFqZru1xR0Ktlerko4rHRSEfD53kXwcVqsQPnYfwH5HOAqwV1VELmOHYcc
rtFOjnZPtd4ydfE4jIVbwjZ4TL36Psz3fsAWikzckLReTQzpVD358lBwgUYHw3ZF3pq9rH1z3rQ3
R2y54y13xnyhjiEvqXc1AdDkF4nLuAa/34V1njnKGCEOvUGCIx1DUCCTqiDRxQzacc5ANND8WZvI
SVE6GExFXSv3ANTkLPaRZAmWNVkoejh0/G4TGxxfj7Gi0Bnu6K4k4CBiuaXBToK9dMBoyi/4+iGg
fR/l2fPO+sHAWhWNkMBjIQVLajk1iNB0yP3tCq4B1c1ZiN7GoycJDJtIjZPCofazveNRWiVLjp31
XnruUXZ7onBVA1XSXW2yoqLTd94CZ7zoWwVyY9sRbEGQB7tBuaBZgdB3QiEpZFSkEfEc2QFh1Oxf
bf3tPruf0coFhYgEendxThojWPvwpRdpe91Ah4UpslpNLI8kMWJzAbhUghk6qsqKJGJi3R8ZbAQb
OgiJKvFrKBjNa5hY7V38HHTBf4W9ixVp58eQe1SKvGrZH3C/vPdwtk1HakztMVLRdUxrQ0rcov3E
EacUEsHeNs187R6yggdXATSSaR5dHSgmXhhKvcPUbx5BsH5kJ/KuxqKeecwBB6fmHrzBXA+2zSE9
PRpikidQ6Ij6cvr5RLx5v+1Qo33RTkzrrlDpjmhnHThCQw5iKv0S/e2QmUH0DnzvpDZU5C6o6nCo
LtDVY1QBxKXWLmVVNOyjwbGLySvzyfkqRKKph1s+fU6IZXZC326duoXjjqnouCUnZS++/YPzi+Wn
o2RTr0j7lYMnex8e2Z6ofW4ymzOicsg/9dfEt4dwGVfzRT89jIK75Yb057kXmpUwTrScxE6hdB1k
NnQShPLwQwf8hwWMSv0PxhlWFkI5dYkNsVJCMiJiqCxV/cIw69TZcDNW+mzyAGJmr4Ne/wk6TY6N
w5GAetBYtByd8M2VExHMgGNdPu1BhrS6yR2+X2xkwhNVbT2dzjHvrp8fP7WY55UKDcyaUtswt6U9
/2qyYnInDEjoduFh3KwevxrZH+Peerrl4GyrlWqXnWYvOVqVdXaQlE0U6HRo/oyTx82vTMsMp+2t
nDqRVq5gsHWeJ6GQV+rWvumrD/xpYYE4Ymt9C3nJfbbll+MUcxbH+33HWApcdZCxmNbhE1lqKUYU
s4LM5Yugm7iXamX92I966CgNOkwJqEKtDp3etauk8IXj0eqhuuRZvXTc8NE8/rLRJEtUdRuy+5nt
Fbe0Q2xDkd9myZohMzn+Z+YD0gt1RXiopCUMU3v4XARmlwX09AH6HnWPp56Rc/ZfxFSwokTl2GX7
kle3P5HEjHE2NulUlRbLsKMHB/42gSynzJMGt5XRa+JABJO8mpHEFY7HrYplL7wBjNh6Ew0xJi83
6DDI3dkC1+JTi2P68Mcn+e+NGyOy2kaMsbkaiwB27LaqlMVhHd8eHIfhHtU13DR4VjOZtqePVq6Z
T/jcjENTtBHRt1+J38ZW6Vjys+gQTEHPGZMP0ZbGx/di7WbdhFnVu4Ly0R8FqkReELBMqKZ3XPsT
Z3eidK0WbSEwtulh6wk3U6+aQvJgVv/j7wvDYnxbtlxYWosEDLFP/OUOVb1Xo8Xq+uKuO3mkCZDs
KHIINlrNnAQRfY1A0pYA6nJosTLx/oOlIEc/Ww0hKvf1uGq4sjzcutC6BluZTCsQILCcMvv2YJhQ
LDqYY5nHLYFCiZa8Zb+eYkAfrUKw7B/KyqcfZnCdABxO4wVUG0NdQQ6YepxUJcEB7ZYptNiHJppA
TUlXsh258cQO+NYu8gthXeQHW0Qi4b2ancnwcBEJuZwkzRbmQlaT6rnZo4F6RhtfTwtMBW2E9RpS
xnaE8Nvnu6VwciQQXueYAIbVF8znLpOhSoaU83Zv43taBuRWWzImRcnuh0ZadQlnCapMSu62Wa2j
6SfPODCfH6ypa1DGF7tm7aPr+6m+jpdDeEj8OWsXBmHbBg/fwBmECWLNqCArvC/EA7X0XGcm8zm0
ce2cauckdV3Q53qw9KsbosVjawwo5rNFEx5XAuhmj6EDYxaS3CFSRLIUJ5J1qqodB4c2jfi5xWVx
UtD9gdyGQDfLXbowQH6QwRXWi1VZnYOuU3kP9QnTcPwOTbCTMH3IO1C/CA9m68kiCu3iu+96jIQB
8VewPGXinT/UnfNIIsCcHJlfwumHy+Wh94CflSxGarjMzPAUfHGdZmLSju4UcdJcKsfhHWKgpPfT
dm86p0XorT7/52f5nD4FbPAHcY/uqZ8nuvu7Zg+A10qYCTpB/HLjL3vJ6Zf4YiJ0P7ORIXT3ZXag
YtREfP+1tkPRfJpRPS0MY8/r03Dqfphv8sQd5PfuXHPYz6/Pijr3moVHr4FFjNWXujLblUShZFQs
swON6wNl73ZCyqcdXC8A+Zg2ifFcX3EYlzrJkkSX6qpxkZk97AnwkC3XYMcyvoNnLFfI2+Nawfee
BGh0TnRUt2fH2uF5j5AzC95kqFpU4DIjPammLkg0/Ke7pl2MXgAz3CnJQw0WE8aYb2IoyRY/exRQ
Yz7F5bvqNM2RRcVPmZk3DeJ2JG5sDBs2z6SqgztI0oDMGPIqQiQ3EIEX4zGLqqnCm1N2Ma9SZ0s+
pjFbLoG5fJi1xMn0sPJaMnMEh/e3Fkuy7d/3gx5vEGPDqAy84ynI5LTzXImjiI87Diz18dPFloMS
jTXQytytFzG4VfqHTt9h9wE8c1t28bLObePJaXMFzUkQTkbM9WdanG3G4SebX2P3I2lYpnwi6P/V
45BDrwn9k75AjtCDDOF/um+lapSuIP+HhQS+aLx+IloNYWIobsOxs9XuXUCOiT4TfFWIhv/37eiI
NkW8lAkzmNTEVqNToKoi0ZXvhxnxI4lhx9AGipxmK669eyxkNwn+Z2lnhfCHepa1oe8w6FzpCZye
G1zmcyFEnIs/xHv6t1P7iw0JoNARO32GeaH6vVzXuTNEOeQnnLOMGagMEYrxklS+o6UqyEjlJjuD
v59PyDOp156vLOo8MlVMqTQpt0+qnofomJOKEwX+e6o4I7SOPhts5bcMXtFvM6xMgFwlcI6ig3QQ
QhqtKAiuqjtF4rvHtVBloaDbH6n8yabmZuKq6amIOPE3v3rwpIqdKIbhTYD//bLcaa2eLjWI7wVY
QPK/k6ShYEjzdhZs7l3OwoTh0A+HfQddLr/G4gnkHtreiuOa+Sfwnpm/ET2eRS4a59pVM0iXifHp
NZu8fw7G5q1lpp64kT8a9oo/JtO31xHY7pIHfNHl5f0tbxmBN8jj4Ej2KMs3GD/m/OP0iekhNW4y
9U7PHRmqislPylKZJTaH75axORWxOK5QHP9SB0Aaho6iPfuRdh8gLS3jNQ7hKtJuPumHI8X3A9kg
eWK6SVzexQzGk9hfKt+x2bVS2riwZ0kbTJvEca+7+8zGfih6VU/kRAQpJLEGioSJ/3ym7UxkKer4
MWDEVXV5FPYympQYzppGRxs3KGhRKvNwMqFW5bZLdY1/S5g4JjOk6wwX4s4KBFfq/Qpv6JjV4zv0
cCympBooBf2ulrRB2umf5ZWr8h0TR9hEb6oj9nzAHNkVa46fV7NzxBHNwmHGj7iX1Mchrz0VoUxL
nYZ1SCuEQDcfrmRcO75Br3+MZCsKBjtBNZ8zBw7Zu1WY9Lcjzb3FfdFdLurZr9Eto28RCMFVmkIt
LscDIuRlZEepCS2aSdAVn9pcUHugEk7GYA32lypbETFN7nbQz5BXkoM/UqTlEDjamd6iw8CKsmvq
41+0DYj6AAH190yjahZOsTbnQzl319mqx54ShHJzuaJgI1e8R9jC34fyCP4cd/bshyscE/7azmKe
/YOV3OEGfMUR0lIPkKWHEpXxqpzTSSFqaYRss5q3kyIbP4ZY47DuaTd9l92wZpgNY16qtZQMC/tR
lPlTcc5WWtPP00DZcLJVeD4Ht6ULC3DrzXqXjnHrHfDAWmHbCuR520OPJKpfBdYLydF7cjPS+Q3Z
FJ4FHvEVZqfaDql9LcTkcf3Ut/TtYUPdVRh38Jp7G8gAOrA11/yaiXQPuZuw4P3jGijzpae6sFYL
GbrUIQNVLBvBqNafMs8agFJ8cgzMp69efVr7jv5O6RrxTY7jUNNGkkEBEfrk+NZ0UhXMok3RhA+m
Xo47rPifJjhxhNErvGUVPby1DrXUHCPu6U8YsHAU942CFhOF+CbgsYRSTCcJ+fuLGPqINL4ortbP
xDJNDDQ5OwHo6iRIG5BnruYBtWaU8Fs92yqNDQpc90lMARiaoBqq4DmOJ85yMnH7UBvu5URUcIWC
MePgZAA+dQC2IpIpjiQzhTpMaqSpHTTaZ0Rj1bipyIPBJ+E/tCKM0cRjyTFZ9Fxo0LFLBYy/7ogX
TMnehn50421zoL7A3Du7fsqjaqYxuZ4BNu1aFYeayyPLQDI8cxQ/oOmSL5b2T4tY/T7NZ8Ia0BZv
kRV1NY3u/QsiSOPnLthJ2y5zMSEIBy6HcDzDP8ztWJLWhVP6S11z+RInsV/MmZBCO8NqxLFPhUaD
Iy+h1SaL6MqyBSSReXzWdTLjV4ldq5dBO8MJ0nauDdgAWHD+HUOqC0lOkfCKbv/4iwe28clYgGxz
/jSrEjb0zo0pcF57dEu931MRYLR1tmRhqJ2Z/ooIMnTYuqyHImWBkmsLtMzlZP0CIjTtzJkMm94w
ifkMhxs5m710cWUc0h/E9zlelf0/6r5a1B4/gaXF3tp6M87vVxb/XGe6jLB5zzPKbo2IA/somhQI
GiqhRlA8QYQYJQCvapQqxHG5/AJFbPAoNhJZeyBaUMCW/lgJm7TgqVatDRDstawac+WMI43/Bi+H
0Rz6YjtzVy9G8oR0fYsNUbpMISEbu8+CVvUcmKWBY6MgnAz0pQUQS4qkIDpDn0wub0BmP7x0ec5V
mBfFq68pLByjFwp6D+kHB30AhFN6S9Y6Zf7+X52Xpk43z95EmnaoKZUylELI/0NSoQ/w69KK2pi3
emGYXIkr7qIz7d2FZpNra2VNAGhlnjuLN879euEliwTCmfbw9z0aEQorwghuJAJ+jF3EZY2Eejjz
64ZpqEiYG8SVAi5HkEsUz9xhRIxG1F2KA8EOyUvGG04ojnWi7ZtVeQIFjSRp2sg3oSaG1CU9iCKw
iDI/WskyAEO3cKgb3xHPhf1aELDCHOcf3XBuxOceEOs7T0TiY8dznzd5mtNXbkR+LWEu30o5i9AH
TNyeSe2yCNq2xvK40oQ+cd4bOdEETP4sXvFrDvjtYKKpfKA/MGEc5+eee5ctbGY3MCqQgFBhxvyP
BA2IjRWOKnzkSGtmMs6s7mBxnBM8vDBLzSl4vxUawZk1NXTNenXDF6VXz2N1qTJs5aNu6fEk6v86
TmJ+ptS7Mri6MYFCpBd5ZIMqj11ZOdWMmipfKNwKWC4REdbgTiNyRECI0fPaxGKO4ifnXJtSKVTl
46angniOjyXUGkKcnrjy9jQHpeZE12CtbiaguPfXI7yiMbqAHNmWBrj9K7ONwShZRtxl8Y2b46c3
lTx+/cPwJKK9EsQljmEolfLZGQ0gXf+DcYMkGwo5BT0R0+1eA3rWs9W+wEZ+9MK1to7bs5b7nkqN
WjtfWmKuPmv4Gqf+wo1a2NX2l4NbbpKLCFAnaaoeXapF4d5lHWidIztAPy4Qw/a0KOo4oP7ukfsi
XlAKNSkMt0U2TqN4qeofFh+0AKQ60yID0N/aXJkTBBTs606X+JVFrgw9aqLZgyEHGoKIEFMurgDh
GjxW0CWo6Wm8u5wdcKusZyBQZZpr/j64YTy625AF5cIX7jkaudpmMoSVL0TnP0O0qR4QJi1ePX2i
biCWBCscnjJ74djnB8lNRvIRbb9dKZzMMHIYDbm+fNooNmadTkThgQidAfRmQIvEEtYzx7JCSpEI
Gc1pEoMrtUqKr5zCbKdBfUpWs94S7bSCh4n7DK45nhtNKoo+yuBdZfs/J17koczluQsE8A3ZTphN
z+zUnfuysb4+tQJrXItIX95C47sGUwSc8LDXUFrwnL1fMDb+KaSGivMUjj1yk1EUjAxkPHrQr8GE
hsUygksqfNuv/bDL5HZTcrCljlq8iuOpEP2LBwyEdj5EQdLbwHSIJvCNPPiw6fAo36nEc49qDa0u
4VM6oow+0OEeOJQnqCc8J0rkJtswnKLRDhSyeFevAIBP3T6r1IkJ7PueG20dK2kV/eTVRqra6bsH
8XHwv03AdCqkjBGBH6VRlHf1RZBJJuJfVfv6mF2Cm0s2Zf8SBMowIrbAs8+YhFD+AiHFby5TJniB
foTKH8/o4qBYGPFhcA1rjF21yIXLm0N7vSFgXs4pTcrIlz/2CNF+H0w3K/GHBn5KLo6f5ABUrTK4
cNsJZWox20gMUnxD4XDq+ZE6JDI3jx01klCEmRo0jJktGABVxQ+YA15bIMDqRotWKNc0BySI1thw
3fNPFbgbCZh/k2EFyow2fbJh+q2en5vlTA3ZUA8/ICpCWJSJmLt/j/y1R9uK+VWuF76QvxwcXK3O
5no8xXT+rW/lZyPALUPdMoYuld9gMpbtyMwsF/j/fXAAau7WV98tEagRaYygQNl5SRnI5TVWvA1F
AbhuR6b7iD6k6OnGC7pQcdNlzHLQXovxHUrmYMUdp437k80krf7UWsZjLpAUaWjrtJ+zQtMNvW6J
lIQQh1W1rtr56CYqpYNf7WmzQRviJ7ICM6qBS9gNp8OpC7COsNjO2aZ5ewpyyr7YmaYRQNiNCCHE
YlpClOqc3js8bPQRH70f2O48FX7O0O5Cd5zFggC84w3L9JfX/SwapDfFJ7jd01jR25iVhNZnxYQ+
WP2AxFXiFzG/tlKkzJelkEPHYR0uZtG0D+j23YrReZhIPmhyeDMYm02gP1IRqCd8dltcDqXpUeDY
TvlcY2JDRjk7lRjx7M7epN82wUOKUN3n3LaJAhqASbqhYsdim9ZlGsZ+D/HJyPiQW8H68e2TgxO3
pJTbrY0DtOprRf0LRqIfHXvbeQYg4jfv6705Oe/tA0rdMpfUaYyseGDb1sTnxAQiT3vf/1s1B6xC
YHuq/+iNsxd0evFMU+Oaup1t8vxCoAvRi+7ywf0SVPYgEyNl8WTUe2cPYBtIUd6JK29vaznY1huW
z14god4Tjh4xSLf0cHMTaP8UapmjaKGqZp0+GXKexIgkuKZMrlHxX/mqYrprH2XQb9yQGGwsLMKX
GFXxtd8glpa1dLaH8YXpR7pdU0ej1PR09WcPiYJyM91HdECoAswVayvxP/Gd/YQA5ZrWtZAl6rSG
KXsvNlmAddpO179M2i9CAgBoBsAQltxzF+RL/+WYc54YZQwdz0ee4kMy7towR8fWP8cmineYW2Oj
5zljbC7mlKxVwqKTQGG7MVMrlOL/WN4GxtaN38UtilN56H5mD1t+CkxKdRqtEDCDz1KBrQePb+dN
MBJg7sm/UVE+B8JUW08myJUWsl5EWasK9Z7QKLWbgkJ0GozHRTlVyTVm2hbyicKa4vKYv/pCW0sG
QJndRjCI2yg1MsACUdj1/inl+4H6mwUTcqWUii+YZAIILeUGGkAq8bAcSGInYBHVSvkVWIxMgInm
AcJ0QJOaMtqF5azkFyuCtP6HQB0RE9DSs/9pQ7Cl6hBEm5ij1t4EZuELQDYranYdD0kb7kbF8CLP
7eW+NjpNZSXnqC1ksbCxNmOJ3vYzJtR51xRpRlW8NVn38kw3WgWfNT+Iu1RJ00VZ8Nf9QAhYiu8h
kWXBvlr9863PUgfYP6UA7yg+7cm7JITu/jDjagN/TUH4GlrVXwYTCur/ByxLv5lv53Pfy3397FlX
J1XiPLk1o9gBRzsjao8795lRL0zuwaMX2EkWk1MALqwtQ7sY/y08kZ5Ux2oJoRRsPwsVSEdRvDD3
0eZsyJambJl2bxm8QX1ISaBbbTbJjTVbiQ7pPJ2y254Fu7UWlNriBqmXXKr+YZT5s8JU7GEF5nFS
SkaDIbRDbUPax9V8b40xLxYOMNQ+aCk2nkgn4KX5O02iQcfPEQkYGuNxnxKnIXdw9npY9jd+Mxdc
RoCES9sRWGpqfrj5SXSKDT36A6PX/ZpBoWC7fn7x+Jbgw6V2mGqbBZvWK2KjBDqg2QDQ5BDWNpE2
CLvdA3oxrqql4S81Ca+rpwsuFGaOnWoQa4nsV+xiw5L/jS1PCIapwm86ZsV8zwrfq0dggs6vrq9B
05+Kr0F2u5oUHHsvhZcQ1ciaBvF/3iZttp/e6/iMj5STxaAWqsLkRNZwjlbw3lHv8Pgnvn3HXOqB
/OrzIHiY0iG0A62RzqN150kEf5FNfrkWKf8ZgP7M31OEfXog2ZI43ClFMIzcccZ/U8d5iSOmzKaD
Tzk+1XHkXFraTZqFHg7nAr6wLHPE2y4p3hID4FtLqSEwNBFk0GHzdFvAVY9ilJA6Q2U+uL1d7dFP
jpNgLa0lGCkgvYbSLZt/w4KVN202Gz14kdfs9L+mdvRlFFi4Zf/QmJNfNmyQw+6vbZ7IFEGxfl3i
oeEw3W+7Zwxn27XxE6fc8VKF/N5vYJKA3a5+nrkouZMRdETCfeWp5vCC8NauAhSxqOg8L+vnboZZ
9VLCCueiaEKiJ7VN1UnmdMHEQtfQ2zLrM9DWjr7KY6Gemh39bTWqsR5MTIhFyyId/jmmR1VD9dRu
dy4K8g6iKUoXsw/NGzdaPJFIW20YfpxfkMNgQU5HTiM05nhj8DPSF4du/khPbCIYAg2LHEfbahkc
ZPah145WgO77rTilbFhKDsp9BACSB+alqSqsR8m2T3EK6ej4Ar3Q8wO/1lwg0tSsxlpdX7iuXbO6
sjW+s1FXwYL7KYyARC6rnk5K7CNOXztNXzyZ42UqO9OT6XJBCh6J2kJEen2PIQKjXtGkmbJ9lZE5
hkbZxaPMQLwtLvl/db2Ne7SrRF6orzqBEtPXfZJjGLYfg9CO7Hv3PrFyiPiz2gKXUNb8k5dWL/yv
tnmn+mAmAlA5H7ktDAPha6EOgL1xezqdQbACx8KzXWAPfHgNVs7F4TocCPvTvRf31xrEkQCDA1J8
amKlToUWtoFno0hZM+7j9Wk2MPdV8D0GlkVl5MurFhnDMnYrTV/rYw7tFeN/NqFpU1IAjxfpJN5v
u3hEC5LNpvMQbyX+E4K4WVxq/IS6ZVmj21zrsdKMJjSjxRTCNSrN5M9alyF2vzY0dje0oac2Lg7t
yXoYHowqSMUjczuty7QqiNK+69OKCgfsktX13tvMnexwF2Bm25zGK6y5/1HUsx74Z+glNTumryjY
UixWdPCt1yCoOWpkZxnY6DqG3CEtgM8k0T7mpfvs+K/UFwivk+5uW0FuKkWd95Vlrp6/2HdoCnNc
PC5ox+By52I/2pmj6nw7y6a+GaMtPbpTggpT39PeDEyX8D/cJPOvSIKN9PJuPiS3kmBWssW1QdX6
EAN9+/Sv5obTrdZvnsnPS7BMYEMVpSimmOoj4WrJP2e48g8YT2fEOwOWL6nwJ0P2f7FINaIpfEEl
8HZA4PYGDKzj+iL+kcmbTPzHkHZSjph2jvRTZGjJda635K5YlEgnPwQV/ilWN6AvrB/sRCnq7WUk
j33doNv4oT9YEBvy2fHYw4cc5DAkppnC9Y3L7UwGX0Jwbp/4Wgjz3KFMJmCfKva8GZ8MhFazWVVR
N7jZGW8AfzD6CWl63NtOzkxkpRS5AdJRXlhkx6HyLYRpBR4b1oMBPveOf/4Bx7TPxuD4eyPKtEuj
uBM/lcSxYEuxvASqVCI5S5vRYZL8rfMBPxHWv6Lmg8xTBExwFu51wMF0hnUkdsOFuAssIt6gkDgx
M4+oAf9JnpIG8WyX7l7HvzxwJy/YdNZWfQvKMrEghZo2Xv1qN9oqFB+N+Fn5mvgdePS69tFsUfDe
/ZlPKkIEVd3wQ7HOwmC96TecbUG3UEeIoEE8qOvI6yic0LuU3W25T7n+07lZkou/s0bBQwwb81yb
Iikp8BIiMq/I1TiOih6RxO4BPQb+UP8HimEPHvPI1KEl9GQaylh6IR+e1iPTGzxD62x9KutM/j4R
lNnx13Z1dbDVpN7zWnTzvzJca3iYFr2UPJT1N/A9gdikASk1QXefir5AIiHbzZbP0mKy9LyiTjz5
pWsOasVsNAHE9FIJBhlSTrmPaLsPHwFX77wuVxkTLvjA+oJbqgBDi0/jF2i2uAjoVhjjhHdyCGYc
t5c7jkIVuIGfofDUPsQpAeJF5vQpbZ0JoDCjDj383RTjB8XzH3Zm3V5bltLWIzsLTaHgUx6ODTHk
ON/oV0WQPAh6owEzy9izgMmomNooLwvi946PUFtCxmiC98niM7wZDRyZKDdDemu7pRdCI7X9Pyi0
BwZICVU3i/dpRGE0YhteYP6It3zJe3i9UIQezcsxn7Up93YuKvnPiBxQycMARE6Q20hIl9teKcT7
xpo8w1Zqh4hp/O7J3e8RSPnTSAe5b5H/j7E86vcthsIwca+vzUDE1NjsL+0BpwmWtmrTv37SuePZ
/CQEIzxuG6TrdmG5l8j8yknBqNOamYqW+87048rJWP+lXLJxap6OGTMhSiKSwRnWym5fgM5YFnPw
nmci4GHSUosrBwBd6crXesYoeYj2JaMzcFyE8FzipVjfhlvevu7bLexhPEM9TKKr4/xEt5a2dD5E
sR4He75xDVSzIsXdGmKFA0DyAglyJ3msB8WRRn1v1wsVsdgfwOQFOYPQtmPBWqJRH+ieXcQw3T2S
4b2ZYezdMCPtZwyMl/ZQBPWtkR05Z6rB1tfZQqd/4k3TgMDrx2GaqNY+bS7OyN5wXhNd7saDWhQV
4XN8gP3UeoeaUqYZi2KXGUaLBEFU3y8pqt/6vtoXUqWzsSI4TksHI7rGF9AslJn0jydp4vQqQM3s
M4K9ODyDOJCx3P9PeXyNlGbU9fTl0wZWiYBs3BMvyzSyqrTgpnn6zX23jdgAUnA5TWRuADXv8TKf
uX8TFYOBiD7Q4JOaKbmlZy0xO/DZDBxJgOT3D5/dsVAawbz2kBSyAsuqIu3Ve3D3GKHG9BhyiGHh
qZ7jG8e2AdyK9l2qsKv7XmmsnX+KzerM7Yo0CXEc1wJk4k9ew5ygq//U4MqpMm5xzN8dqpbUKppP
1bFh7L6xDMr4zmQbx2Am/yglyOsmvuBBBWq45Cw5tTklOo2PSJQj4VhcfKgnbU4LzxOXliMoLF4k
2Xu6AIWK+aPFoWM9K37B2hzqHbpwbhzx9ZUktNcMyRwyL+KKswyIS51gdMpivHm99/lBf9uT4brz
ad2iE1eWk7tmu7g8tkrcAnygXk2Ct0SJHCxCatlaR5vnaJoTrvFuzxm2XN0GYoLo37nHXw7Ww8Gs
ApvO280xV9vNGNVjxVWxe6C1hjpAnV0l9fnNxE/Axlpr6hQ1ufpNCtFZLwkzF7/xZlPLgL0vpOf0
uvvGXH7WFw5Bix9Iy4hij12UI8kG3SQMWfBJEDgXC90/h1xFA7LRBQfIxxrDZJL7BBo5Q1Z8LUzM
qvsJmvWtIwfytdim6QefZghUKfgQQBrbl8uyNd7N1txkv0VkqkZVuGczzBRcOryH0bPM3MIJmzbg
zblUyu4APR9jEPsOlgiu2aXFggRdnZi/Xbwe6qFS9C0uelDS21xLQcYugk1SaBFPkJw3VYyi+b+4
5Qd+yYjOAme4iEIK9xfCpaY7WFdN4CTiiOI9wveCmX699FCBeQRs8rCEO0pXpr1my/e4gSFc4xqF
d/bxplKIfmzKMt3i6aKxydPjUQYRKakD9fyA+XLN+uLbau1QL1aeKtjdgT5CFiLl5uDOsiG+EJZ7
gPD8bW7LybBHdjEq/vjYdKRmzI6OXEQK21OqYFzRZk1VvDgLREI0fTrSGWgrF+3MAto8H1eON+oM
EbwuQ/S+XJCzqS4Y4VRRlC4BynSp2Ow/quOpWbssN7kEOVoF/zS6QpgMJtJJg0x9EnltJzoHgf1U
dP6WuR3ntBsjSleL3iF398xwEsnGyO8pxHUz7qUcwCxAZ202dlJt7nWQ5PJLftCve6u4TBuEgKFG
NgArJHBnDcKymGzUy7H4KX3sVsHZegyy3d+s44wNT4GQZwyfcwbIlq+7fSS5AUSKOhNwxWBfW/Ta
ERdk4GCWQqbFVB1cbZ7VoeldZMQG/waLD4mwViIbVip1Kjz7C+M4ImGcdHlBikQtRwtfNOpT6HZE
mSRKrB0j226t4S0CRZ1hklKST9ywisxQdByZEvpuZijr9emDaj8TK6eA7zbaKgtf1hbBjMaV5LIT
0XxquVOyAftrQnRYLN7ROgD6QG7OwHG5lMbXJOfF5zY4WiQ8/ys1RAGcTI2l6dvIKfbuno5hBxx6
5J3L9gb6juUSneqn/ashg7JetpcNp3VOmmDtHmVuN2WMWP1wUYI4k5TsewHtd8WU0uxRVnpY+8wH
21bpDz9kCRivUSAjDO8QXdCMS3XBYGiki57rfubETlW0S6o9WKSQYeLwdE+n8nn6XsoUJJiRbOnW
U34AEcr5PD8WZbtVFKU4mboc9t1YE/RmNaTDsVttdtd8dfg+5MYG13oDaqWMUrMfUu8pqo1v0fbX
6aKS8r+3NmOCOQFd/ParqzxQocyO1n9gNMVZmwiZydEFP/AZCcq8KdqWUzjwSwEjgqeERjRfddRy
drgFLCpqrcm3jbEAbnmsvnjYKYqQgoiq4cF07EKV5Ldc4DLjVEyEfusonJexTt+F5vug9T+I4yyd
TeFXPgxQ1jV7kHbg3C8cVQ92lclDDrUdmJFKag0QkgKRm+BrFjp2fUfyY9ni1Mzq962U14EcoswX
0W9b70iiNEaS2ZXTObujBoN3VB/npbAdeV1kXNmSCfmhJlOaCvoqPUXrRUK29Cr6sIvP/+tjhHX2
XHDZL43D07HUCLuxSxqsib7zvdhbrqK4OMdqEWugV8ubMSzsUb0Jvo/4TObghTEPOZ508G/U7TTn
G8UgjyaBZldUDywn5SZB0+XExt7lYx2tBQr6MWXakwbKaHsGXfiECmZV09XavD+30IQZmDtw/qD6
RCQLqaX5j/0g5bIXpM/OHjlKoTJdiMMJjtozldo1PXfddAO+2c9DNsC7DEYcdQcuIHqqxRTGCatD
6E3aHM5H5LdKPawpxQZxFjjT96BjXvcQaSCBYerIRPYl51N6nN2WaBm1KDSw9XqGZDLoe/nCq42T
nSo2+tZ0oDsXeiRHkJEo9Ds6QMAtpwlTbOxabLvLt8TzBBI4QdYa4tc2OexGYVjgbj+c+TZNyiOk
ds9PlwjVZoDQIfZVwB1ONlmm3p+S6Qw56CsV9ykeC2ShCPBjaB2LmkHFhsulHq+s4yEATCbGfF1G
1jF7ZXWWXs0+JovBSn5uEE5ot5gcgDdUtdve/RdWoEKKRtxKSemtF4FVUe9wHbDPmSkKGulFoyWa
kU6fDF1ErJeMdcK/vEnnbUwjqlcjm+e6foIwLbPKmFCVWeBI167Ecc9OqBBo84+7e6EIAtiX+Tis
TR8D70aYK08EEgP9dtyLun8OU02JDh7rnggDyF4dyiaOPXrLHrG9F0IYCf6PJXJEDfFCTP6djDFB
8vG70RGwZc4G0v33NeLqN9hgIOg9QX35zv/hNHDg4bQ1cb0aFt01Z7ZSTD3AnlSuwWSZ8kJQ0peU
DI8xqfBehlb7TgJQtAvK/fy2b8bj9Jy9+QbbVB/OeULkY8bbcViPoTQlWyDrGkYLY7C7WxngHUvt
wPUZ9Co51w/OkIjPr/IEr4dw25G93EckmejbG4UHFZ7/KkaeMiSN1L1JCVlOXlUNrgSXyk/dJanC
SBFwYXIhxam0o//CBmJDhc7McH9nIwHUbF2HIV0I/Eruy8ihXjhGHevDuyTIx0znGo3fvlc2rwd0
C+sEbZcRiJwvz4ElRzpsIkbuUN79Qz5JNsbn02tisUvrlDQVWALPVlLxts+ZUpRlGSREObkKQtZv
CygO16A+TwnrgHvuLiSkn1yTo/RZ9nQSSXE4dYgAA+98u6qJ8LhXapt4T51RLuif5Sz99KMGku6M
QOnjPIy4avVxLJRl+sMXI145yctTy3ErGJvOxLWkgNpaUt3ShHi6co0YDBeABE6tJlsmSqbJVyYM
h7WedQqm2tKm2ZhdiTVSUIm/FVGLPCa8itzQSMV48hvrTEVBTzm07r8c50cxbWrSPXkzSL7+0OVo
cPdi5pLPDQXaUNms+zuuTk/RDZgRBBuQ+VGP7Ofnn5Rq0FO+zx1iKhM7NF+qEkhdM2UAEscYqg20
+aBIW+au/VeDJmYcdqPqrwE3Gjo3/qx9ID7RgeKjOwsmd+Dj6aBfrRWG9TVNLSe0JzHoWHUw/JZE
mRMyUcK+Usu6nVfRQL6+ycftFLEzZIzpGLCTnglf6J/FykrHff+QWad5tunlnacXwAV+pcARDbLR
fYV54VvAtXaYBSS5W4z3WF1YNgXDwXJWnjlViIRQH3gIDoq8SMdc5tKtkG7CWur62JtGkwFIx+Ek
Z3FJKxX2eiLaQ5SDNb87361SCNqW1etPOByD9SkvEIbRI54P2fnBKputuz4NOmj7cC/2DfZRzvQY
OP0q1U/HqXfP9L3JA1/Kp2sRLmAaZUDEk4BauNYr3eLNnVPQdUJi+GY050YLHh5h3/I7cb3McOyu
/Qt13Lg4TgyaKiHMblx/T9+yviJrqM0q68gHgcdMfOAOSd1SNNr9Kg0qkAqveHZTIjWBzV1QE+Ak
7efcQ1WCgBwIm4dBX4za+sFUSvKykUnly0ctQIWvN/wJLsRw8+SG8ZoHuuN0tCb9+iCUCsDG8vkU
K3N1qE/cnsN+YGIsABPaqFxvrLcJbp2vEV9lF1mtWm9MFUjriV9dXWi3xHceCAnOJawXNu04tqmD
dZbPxjFPgHyfaV5wE8LDl51K1iVwJ1KNlDxqfmtqXh+mdclSZi8RXpT1W8puShB6aCiIoiRWWFru
8077uJmz2Cyvf3LS/7nQu/EKoo42oKCGH6QlAsuHuG7zUtN8EJNfO9qDPBzVUee6xToFxMloihb+
S5iDPfR8paKMdVqL1LUvWda+cWZ+m4Go8eUJuAzlJXwd1Qzdc6ruy0+/jQNI5fnpPoIJ+cRZkqSv
jw7eVfiFPBjSC0bSC49HqLGoc5U7q/OFxC5eU1VUtNSmt85ukbA5qH9jodGa3D6iMcQ4K9pfeiik
YlNri5wJA76fCr/CIkVwjqh+hX4AsLyDUeBkSy7oIajCmGgX+WTOKbh4FzjI9jrKldHf8wusxQw+
P/s2IlNs0to9bW/Cl7C96JuQ17JAOtMp0KNRppPpPvlyGrig56U91u1MIEhsoJyAJj4+iSHLwTRb
ZiRboKIyAWajdwwKTVyb35lRz+gSTqStV9kMI0FmV4s+QGEqm1jntckZBHcjq91sAAco8hhDj1Pu
8xnTIM7d+TARJLl6AybUzd0Irvb3N2kdldQMGCenj2EANT/8vrXlYMiR0EZi1BMLMIHLPky/q0pS
T4yLIbur5CR53EC+vLj3m0U6ePiVLQakcMa5Vr0owv2V8DqeGiCs0XoMn8IO8MGqVNp9IHYyuGXq
y92AiHc4rArNpKtKnAgq3BWqsvA0IR1jXClFtIOJJNJ5OP2b8746UstQTqmngzUKr0MJL+RJdh4v
wnyJPNmBDPpi+usd4EbylHBR4Rg5hLxn1wYVk+Gm0xKHNNYafGnpZuog/ecJzD7n6lXbmip1M/MD
H1S/Vc8SZAzroxtWoodpKpOpcct9VnEiq26044sMXCDZstlLkQYts8zi3yMliDdrGc1a+DD7twnc
BCNG/+7Komz4kOblEmvnc8NUJZMPzLG77yzyx2PXDHIYpVH5J0RnbTyaf+20iuptXd9xcNRZ1TUW
9Ejp1d77F58YmklxpU/uftstsuJR4i7B7IW+nUINzWPqcVsxrturQ+fdDZtUVdyJg8dUXAMxMdnk
V7BmROkmTC3MuQT3+ofcbN0oCCI5kc4sn+4rrjqaS70jsKWEgQaEsN7lsjAd8pcLP4vQywz856Cj
DcFWhVG2be0N+9tVajcX6Plw2y0vXTPGpYDfK3S3yXwud/RjMJwgX8qwqeTyBMsBBq/DVoMuO34c
ZDpqABw7KSbJEmEBo47jiYgb0hcfMxDw7JKi0Ff8kAU1Eta34q1yjFmJLWy9j9BLYccAj187kTd/
jqhmbYdkAF/5H9h3cg3mrKfXjCrde2URLaPy+2MjJTuszeCef112x/L616kJY/3yL4FjcEVXcL4K
b1+idf58sTHIuKFGCROhhJr1JSozMIiVLglMW9aU3MED6qDEbHeNQlHuBbqrnP7M6sB+B5/y5I8B
F5cQI9BPWww2eQBdfS9wwKyyNIvHdb4mnkDV5MFtYNYWuJQQCyg1HNHnRiKvG3y2T8WyE0pVChjV
pFy6j2BSpGrn+FBCGpum9VsOxHKQDWtX0mTyhgXWE3QNc1PNSG1XazGLTD3MDQy/az+0q4cr9r0o
AblFzkfzZwsbpKuJyVlbPX55V/vmFpool5uSIJoJ+FgNOrF+yNmVO/sOyDuuSAuPDzGOXm75IznJ
ONOyYIUnhA4u8/IyoPdX2MKMO025JMiAFOfOOtAzQWHqNPtjVg3PH2tRokDgNCgpU1QhRIK//DxC
JXkv9zj8OQ4wsZrC5F8oUk4YBLTO/i65I/isridai+8nC89LjEkF9+1jELyt44ucrhndtk5WGcgd
Qj3NtzvHXCkfK3lLw7CLcXI/aK/1YHph+irbCUX0Alfhl3Jk1fVsDqlL010gAtAQIi176K+zMDmq
/gm683RYmW4iwvEBtpI2H1Pp44gro3sNKO0+JdPD8c4fqRZT+0dRZ3ShEa8yqcBdNYwHn+NG+xlq
itXIl8NDBENlp16OeLU2T5JrLCSbjtF3+HT/a1hCe2N5IKn9TCguxKFQ0zJNEUrDARplgNFf516K
jGxXpJSf06/1aYDVDyxqILdNj7Ccx2zimVtxKiSu7xSGa/i1NhKDo+gLeJFJMDaikAKAO7A07WG1
GdWrDjwVSSRjAsUPX3Q01RS2k4LuIy2w/NrrYQU1oNih8yYsheuB1zkmG7+4UrGZdcYE5IZf5F4A
OSFNTszyuHTnoqMocdsC4Ul6iyuWYbdqnSncIfZAOZLPrwx1IjjkdGgy4F1SXPV7T7nP9+Snm3kB
zuIuLUA75dvVzI8yOmuqz2e6OZ6kpwS7ZAmKs4BYeN6PMfWLMDXzxJ4TRdDqFAMP/TWF7KTl08q2
EoFuMXE+VFMpgUOUlspTW8pmw3yfS/QQeU6mPrM07HZVoh04CTNByq2abrGrKqgDG/eK94Kxewgh
wZE+e9bM0ygPyQ75t296tBEalubGDCzwrLZZhKPywnmHV9JDSfCYiU7cXUY5qKorxjTfwTgKAcbg
YVtkIRXy7L6L2CpaBpticzo3AO1dRjj7t49mcqjXNIgk/t4v3SVSata5m1HEkuiCMJ+8SPhToZWq
FZjaLXDwOG9SjBRIypNdp5Z+mNhgOy8zicjM6r3B45rThmqvGTa1lMRe1RooOZFArdizUUSt58XW
gxFHM3wZzc59g6Nj16ezIBZQXQcTWjFiYjl3RGsV91RYk6s/e9dAg2XTc5IMASXWlzmBWuwZ2ZvN
7543A8hJkbsTT6L8nMETU54JcPI0lhpCP1Y8pS435mqfYMBjUPoMNPU2ryLUVxtHH4q14+mWL7m6
/WgTu2UDBDi/ytY70xxfyJ2F61Yyj8SocQ7HzeJSKMsvXB0rPW8aALDY4B5ASU9vl+YIbGGOfRxk
X6u/u0VELCaz2B6lUWQTxqdLKwqK4PGUdMtn5Sar1PThiRiaQRynlouPqaTM2rLOOOgsuNRfEZUi
/DalS3qzzmzTvHX8UhA5S51CUGHh1o51TbRjWkQlIXZrDBNGi5lUq2b/AQ3I9yj6GXbJ7O9txdNY
NsQxUBZFzLRNbRg2umcUaseq8vWYc8XHJQl2vy7xeb5wyMNCrBpcOreinH4ua/hOiqfKqEvQZupI
Cid0W6jh4s26UUXK5u1mB8ia/fkWnsCWRXtaEki36GS1cMMMMwjU60uRMMUF9GDzfpS6r2voUO0A
oxuP2DVkyRXaojNv7r0sy9wUQ5+LxOHsBG26jiWqb/ZhSfc9cpjQ/bVgtLfw7ZkKbaC7ML7To6af
COkGrhNlOFh/ur0Ia7Oq5qCBO1aQCmFB/2EAjEn2sJE7F1OkEkf3QdCLMSjld/wTFQXjDNqZ2dDl
43EMv4ObH31SLX2nF5MB8dFAqqA0p0Fe49H5WM7VPJXO1UssSB/WtLeZFMzlX/jRxnVVW2+v2RYr
u8adA3ffpkBb1fYjeLzX6A5rUggiwkV9jE7la5H01TxezvByjFio5g2celsjOMN4gRYFtErXd7aU
FC74xinATcWSdYzh7L9/m0+YJxzebOlbvhdYxI5RPTZMo8IOPIK35A41qBHblwqPxsTtXgZaVlPQ
Gh8OGslXEluEuTAOGOc30+X12P/WZNneSsMh/nEZ/QiTrVWJ1f+o9ADPQsiA+I5mv7nqBxotxMuD
h+ePCIc6KHvfN0Mr2ggZlFtsdSdBCnl/oAmngraEvbjuJfhOmTIg4WxVD8jkpEGqHXsi9RDLog49
/CTD8SVmKH6sJ4UcnHZ1fbdM95oIN7RuMsufj+d6AIkoY8/ZPu3ThL/M4Tkzy3+g7Wur4KQYDK71
QfW0Dq1255olkx7oZHd9DH1dsqLGHSbos1257VuPNC9fngVHHKHAT1vh4svyxOpJutV4j0CN7T73
9G+4lr2w4D/Gb2SW+DM1+cXrGBxfujei0Wu0y8SBev88plPSNKTVO0RpmnA564erOfDSG38vfzlR
mqkV2P+RJpjnzKr/vPyR33H+e+/Ecz29NeIyLM29K82nDc13UGuLgqGpW8EN/XNMYGUD7Kulfx2m
nYCHrtcu7X4m/HuGg58zkyUm23HlrRzB0nUYuDW26rX+DZvy9Q2TRI4ORtH/tHSeqaGHvkEk4zgR
DxHZVmktweAzWkSzuGi+b9+bxAH/4eodQfwua23YTOI834wpPtdhqZTjzv6WaHhCbDhk+hf1juZm
gDXpdb9Kd0f5ifgahytsAa6jXUvt4OVyTfs5qrDeAN1CObSK0RrPsqjr5S6/NDR8VxZgZbb4VDb/
e5aSNvnZgdMmUMZXIT6G2XZkRk2R3dnEmGzkf9V4yMA8LfR+BP79o8z6B1vSMA65Aglur/ibCjcv
1dCOwXzocJKkBdNzy2m3jMRcRe27Al4G2TVw1/gWhXtX+AAUvRmVXUaZeuJ72r01qnmTlFi3AhJ0
c72ruuLirPQyxnKrcyXTRBMO0UgNE6QwYjy6UJ4T/oGWod2jxYmqaNTDs6gOtcMMuDgAsbS4/MpT
MLBFKAWrzn2AY4D7+6DYwKvvfuSUWl+l+jy6+2c6fPbIu/D2n4GCm6WgtFfJWM4qWg/39Q/6FS73
KQ78nO9i1uIdl1nWlHci/AkizDzNb/B9ew7zeScmCEOGmwwmPMXX0eiIZ6pAbUvOCzLXRGxmpL8Q
jHcdqoFzNByAGiSlg9wijmM0JXvVDuaP9FHcg1AIYkzF5yn3nuiW2KdGvdYOGLD/+rTrj6YE8+ak
4vaEM91YHo48fJGo9JBerQ4123q5NZc2LImWr9m55ZKUM3Hh+mH1ITgLIkgjw6t2ZOMDpUH8rGdO
au5lMp2m8q3QJ9u3Obes1eXqPJe59Gt+3GJwvlWDIZ4e1aV8YCBRzk0QLpXSesF59xCwnZMsMHkK
upkSCEhdlyFaQ86wxQLymMRVOeR//k4CZgw9Cz2UDb62Zc1POEkrQ8trakza2JXkLSwgitAKyfe5
Vu+lAXPPL8TuikmikkLrsfTJ3IpzPXXJQQoVrvo4NPM3/4+a5ihGFDi+hoK01TNpFtkxsJJN+ZqQ
Yl4j2wRV81QlS+LtzLHTR02GtDzLOiEHN0h6boBqdbGP4aN+hk0BMWKpSANYjWso4DFvjjVw4dE9
tMkA2TRtCOvF/9IQIv+d+iAsnPM9pGBf7S+lnjaf72i6Cpqvqmt6QwhebUbE/bHcQLua6MkctIqm
93AOgFcNBI7W25x1mOZwg6QIw7b59l5Uz3HiE5fqLimJoqpaGAH+riPKw15+zD5ZTzwOeJD1QHPU
j0FHnHq7MId7vLAV8hsk9BYBhfJ9mFoXa6pjtXYSfvqhutkFdXxtvaVd/szE293f5y19j2CSqIul
Vyik4SGdWlSAIW6M+7+b84ls3nsuobl1DZrm2j1YP3oW+lNdUvVrLZa67e0cuvxmWF404ZAvwKi5
BWjcFBq0MhE012o2VO8CqlAtI/H1Wi+94bf2n36Uq8eAEJXc9pBZwFIeoxKek8jPv37tm+xhNb+P
3hP29jHFThh80FChmx9cdMAJG3QFzuQ+4LiIDXjUSNZv0ea8r9k1WQ3JZA79a9GCDJMv3awrHpHK
b4PIz4M9Dt5tId2qZyrDgV15u/npkkcxl8shCwR0iSRw5rdfutrmYYrFDlFxAQAyIgyBOIWTqlJo
WHK1MWVqwnd/AyYLTwE6dJKeloTpMQrrItnkNR4Qsnn6VR70e17G4XoKB3juAEbbKnQOka28j587
J66KJRSGFLlo6yv6OvEGGi7lTYjr5sJDkUDITPZV7PrvTvxJCo3qmnmhVKQ9qjDJG7/AhAPI0Jmx
09G8ymhbqlFizuRTcOMWZyS0iZhe7KZyhqCjD5W7s7aOK/GbvxOBGqSH6Emi9MkRzvefcdNXCpIb
5MUp7ncIOKZesZ0FmyCBRk6QjKtQIAv+YAeMGjUNPK9JWpEDSkaoRfVTV/uA3gqrozkJsjynHNUL
Lb93QZirZOKi9dnfb/2jdypIkv9xmGVoyP4Z9z2WHf6YGXtDvGU9wnJAkdSW90mHck70LcX5Z9Er
5plh3cEwbTOIUnl0QcXjseutRT3I6tYkqbzzUInrzD0jJka/fgUFnHFuCGAdnzuMVvTv8GYy3yYV
gznUwuzyo6YyhJL7cTBQJrOuB3tFGtyK2xU2eLgTT/SnEw1uaWLAfadYopsf5mRdEVoEq7W7KcTl
qaiESU1wP3Q+coqHwxzMxnnmagcrNYwrKwxMUpUh2nX3fdiyACQc1CgiosQs1dGPx9WI8FECtw3r
N6Eo4HBlzroFcnVhmtEyljPS1BXMsIDRhjSbTr/WNRXrA7ew7S98uLT62+E6HiPqBDBtAqUbZuzV
Yg1tBGbDT2LH2UPHmSzTYOjVbfcrm+tunhMritueBQYEjNtEYP9UMBofTKFtgz+gysLH+6VpzjKv
TBXULbrhzkhxJCXDJtEUpWbEHdUf2EGReTqEqsJWEMYCgX8XYKflCm9BeNwLAxzQ++fL1TMKXiXz
Q16sk/eAqS0bnSXz624QsDITWHLx9g5JrdHB2bizCi2P8fFdniZFYzbAhPn0u5x8rph+03gD6RJP
GGYVXCqWp+eTw+oUlNUnFdW/W6XPARPMtUEBdOzGhMrUVNxSRJfNBsJLJV9JuzGb3vAavqSv+ioR
2/jAV+MUIhAQspd5S+mmo9mK33qndCP06BQ45BiVTYSolNuZz1FYmCaTwOxJgP+j8FBe2c+wJvaf
rc6y/94eoF33HkhpqXbsXjNvsf+yHKiyMP4uZ6TWaQRJ4HoswgqfByh9NvGsWV3wELEyoRTvxKPq
wr8Bf/p+N76RA1mIglT84obzzhHoXzuU4HDFsuqmgEfBOlBFTGaGRLLVoChtFDw+P7C9opc/c4Bf
kULg9Hp5kzIrtCPN9egVDyj2WETw/EEiqF0wAIXLI0VKEi66We28vaMFmG0/ziYuog+HtO51Yq8H
fKyTAsCLj/G0v0ifqZdYkVq8KXzeiDH169tpZdUAuRdDp2t7KtiKKrqHyLFrOO92EDYbF7Ihv643
iSj45MKilUIDmCnvGTzGimWOi4y0nt7Zu1T7yMqPubQYKpw1ch8ZRefnJUHtswPleaM0KDcZNSUs
ZTxg9H9RBpcXPka8FgZZ7qL6HiJQT8CIzaObfeS19M3N1qcDDeXBXydrpsUM4KMVs+Nv42QNN3no
5ho/9eKinKLdJryAdSAlnSuxy7T+iT0a5YOO4ixCGsSQ2AC09fg4L7o85owGRzDP8pzNOu9o8SLu
0KsdhEWeLpkD7HDUI1Mkv2ZnaS/OZz5ZfRoPz5yw7k0dpctLnuQENQguq2Cr/oKFbvBJHdtuDZgH
oYtMBhFwSJNP17M+V+MKhFl3YYOLq1uGebFehensHs/inOPjtGBfYvxkIrZIYxBc+ZJOCvmst6XA
57td+WyLrXeD+ziVPAOJas/rm7PJTIAd+9jumOYaZYTx4Bg8RrAjgrclxRTmaVODpg00av+205Up
v2QA8c3Or1+Ur2lddG6SF5tMkuiZ17vIozw8EbvBts3i8JQDdO3PCSXYBF7Gh0uIEclTsv+R/1KO
1hZ429IcNZNbScgZad/eiKp8hDZyU6xJ8kQLDkmfshtMFMXEulxk9/p6zUfDOWqFFk7nZRhVSfZJ
7ON8lmGvOOwc4qCr+ftFs/rQ6tHZHjooglV7H/3GsS0cW2pI86duJR024+P0bXDIkhaCXjkKGJ+q
iTWTTLBNy7a4IUf6nRJmBYogCqqq+TkCeGEwQMo+jA82n8PcrxLmtkJmHrjQoFTaZhz28pqPvX0T
u+vcQDvQ1zju2E9taeiIZMwmUre7P654P7qzumSq8+fIqKCwlTgW8vgKnl7qIpmh4ZwYCa88H5wR
ICIiPy1/l7L1e/hSnf6yixepeNr0AAxCFcBgNEvopqWhMJie2pvNnSuEkJIA1UEZqsRMtFP05/3L
lu2distlL8dAMOK+WCE43o6FfFHtt2YhQKMcoEoTO88ZDMAqDZX/PxkzEwuNuNs6iIJpMMmuA30S
PRZ1vQ6/JwhY3941rXDdlrZ7/FeZnlGarUfGrFAhjeB6R3+LrhK01AhGkmYa9mRCKGxi+OlG2AQC
9KAeO4qp98vEOkEd2bKQuyDtFUSV9Kwx7gvhvw+puD2jmUzt1Gk5CF8mXdFa8+TnVcFb1HbSul5/
0rBnsWUTqQtWBJflttx/d5pHrmXXPY/uLaU+VNFaxRdinUfQaERj1mxhFWn7/8Yh/hndp4v8k1nt
Rya8zjlQc+aqutTQvx0pXJj5D6oMjxqQ8NAZi4bcc4RSRL7FTqZU9jA1alBUikMRc8DPuDOVmXgT
66mIf3VL3Go7SYMAJl58pdoCfYdxp+KtsgoODHf2ICf6VVGzLaJzePm8NL5/72fFWzA8bfM9+S7t
PizUHmfC6cjsNAL40hILnM/SMBY2zjkmZODFEXujwPY6JyOLLrpcq9iNhCqIR8NwmUq9VIhik/II
zdslQmyopNhxlgWvSys4YQMTm1iLmbUa99vHB2aQMCdgXMmSf+rXzbb/RVmUer7p2M7G7NGFpEqO
Zjxa+WnOdrfPLlNMM3l26VSf2Un+EOYyPoHJlUIoVqe9YSzuRbQqiuQuI2PtwvomUoRxvZkWSHNX
ytydDFcz8iyqBOzPC1jaQDJj4qSEwqB46OpiHjKoneFIymuetyl/OdwFvBBdadyKSpAhvJjKsaKA
HWEO578JSE/YQLwnbj2MK5oD2ibXPJ4oSz9HAdnDte/TzSGH+n7I6b708+XJlZzu/BRi5KNdODVP
rJGuVj45AN+V8QoT7KUVSiiSsOWzoxwFLFWfI/7XB9yWLLkOIGMLK/FjPCA7ftRhlqIFLmDsxUqt
xucC5qVEh5IeywjZG+I6RcjoWCNl3MMNIl/vLCpDPFAymVKmR56ah4lFrZna7kMyibiYPA/o8sC8
ZpeHrF3ce+QAGdN2CZUCIhloFsV9fjTIsNcxX/C1+jovwwwkYTm8l5It+mgWaP4DxCdp9nAW7wik
B9jjweNJnsPF0aOfro7xAbEjk4kVm3+hZ2EPbCVrx4fnMyX9BlWYrDgDLuXHZIZTlH/hylx7tHzO
wpWnQlQ7lBzUvlB/UJHpc1e74ab6m/oY2q7ncI8AwLLg0KBvGC9Ov53tKAS9ZLxWLOSehzYpq5X/
6Gy/ihVkXz9x6XxldPl9PMvKKX/UQnAhT9SGvLzNgCLjJXtiX4xbGQOtNPttBhfOgwbRqNaySPbW
/J9vInNdmNmdaoto7UqohsGItSJG4m7a+qZOQUiFz93Lwa+EuvKPNhiBbWwmRZDMyaQbUHnhC0Gk
LSdghSRPcpUQlEm/bNgwAsJ2Dym17Nio/Q3g8mnm/rIU9gz+3pFPnQ4R+5h+9oIfIZzX6QJh06V9
QNHBPBCUpY0MPDcTAlsIc5tR4BwzIN0AzIr90Nw62qH/5JfRsyhfLNb1jHo9JyMxUI2+wZDXtiro
2fPPc+KuZyJ0u9REQMsxXKFyc16yULQUyQXXHPifyXXJklIdvNc9vDPLwG+/tgypeD+fkjy8o2bj
rnhqZdzBxBgdtCN7OFJOzpqyGJozlcXUoAJ+oZcrBOevZUVASGgfjig65uEQOJBwReV1wL0txlEd
QIWxOKm6C+lQjDBPmqjH2Nvsu6AoMsgZPCx1j4WH6qG/wtge/ELieAaNupHuMRXlasicNT+0xe/l
zivzg0ysdDmgIKWp6QFuFQFbjPxjklyhefb1HFqtNIUACs044d+uyEfrWYgentK6ztZ3KVtMY0mM
w9XBJuT8jGVJ/tV96wNAnMyoAlIKnQdyFfi4V7WFFxrlGchpjtrdmyWAPbWFMpohtcM7xfiMS4E9
PkqJa20JPiV6k/R6Jjs/aedF+TjXeEtxQkMwV6+FQKdbe++EKDOzVU2Pyt7L8+y6m1nOEq0lcUEm
CYVpQwZJzbJebkjydS62mjTX7pveOcZZnbZP8wvainEThZZs20D60DrO9VW5F0n+D5e7mbz77WVN
UZ3mmKJDAvtR4BULtFt6aX387n71nUYqV7GHwSfJoh9nLV9G21f0mSUljA8qZ5wUGfUveBqWr6cQ
lL+omdxGi+B/BXwh/WXlOHJMcDOMBx+YQgsi/7elw6EUV7tB1K0zjXcGyepI0li7ikAHOQPm4jlh
rkeUoLgertF+U+pUcjme53y0iN+mqudG0MgNFIuLj4JHhGHbOGEXFxOAcrWOzDnVDtUgkMSC7bnQ
sl9MhuXPxWjrYWB+hXfM43dellyk+RGay6pEPTwBKbLkT5PSx5SjNaT3uRDf1syuI7VuIvShEtTH
ET2hpXKXEcaPvz4cCgHWurFMpuNZWnm7M62BQ+LRys1DdA8WQivfGbyOs5Ipa8Og6IP+/ItLzXKM
2om3Q3rXCCkMtrThax3AFy66XvdZXMX0NX/r+AoO6no/UbWloheH6s8v6wH3r9rkFIVhJmMCo/B+
1DAfjNTL/2n4AjGVxtHNDT5Sr8XWSgBU3xAa6go1z985uXRMYXy9ZZf43LolMzJH3l2LfGXhmMzY
qo8bD77VEUFKJeGw80JGM0a5aeqr3wXGFRqPUE2CtW02rH0g57H1m8FpU0x0w/iXRGDU8VlUxFxG
FIRAJ+OZO3Jjpz1t3WGe8t6pTccVlIkV9ap9pS8/GF0neuuT7fFx/hK3r8LO0Bci6jpnwZdbXilO
Umt04Hlh/tNF3QYPY2yJST0LqWl/mh6yOda5ITPMNFZ5W/r99pK6TWAkVq/z22cgGBE2YWYIem6L
XA26xs7lvuANobYpU+b7ZJISSZGTOjok4jUEOFEDqj6HaIgaz8b5dy4Xf+q0BL0+KlKOX+79FC/Q
CLYaOYcu/BaXd0NSczqUL0dduNBGyGM9v/fFu9++EXBHwwA0Ix1+tGCSviP9MV00/pTyVdecE1y0
HSjJtaZtIPz/JPYraoRsPriCI6SzFgiWSSFbNnriLJlxpS12YqUI8vyBkbGXmeGNfcyBSRSSFvgU
4RcE0XdkKBlHqfFcgkNaXSNC+C5v+ScESsHorQqTbVOSOwi/8CKdtY4ZHOYDveOskbBWkH+wSEXK
lRxyvzGiMutS8Xr+3lAmfA6NGI06xETi+2YvhRUnkV5dXJueBpQ8/dYcK8D8oe65KLXMasCv29H3
45fr5+ezG8f6Yv939jmvdlx7IBSLPCBCld/AIwNS6NWcdWmddTsiWhgDOA7nsog+DuCYMvRZEZoz
tTQY3S+ucq2rZSOvjD4+yYVpJh43XqGtycEgSFYL4KB8p24R5J8BNEKIg+KpurfxWXXhG3OsFCoV
QONQxQYspA/0ytxzEppM7HsAOAzanvN0t27ep6GwBrIJddAUOBX541t3gAF0DaizmmGuIcnfI/c9
Aa8UOQ2ZilIlpKlV8bI/iSe+VDf00b31roM5qIcZPQOGY9GXMxKvNW/jX5qRWqIMiwKWQODyWt7W
6+BQqn2Bgvwr0KZmFGzlmaYGiQHtJi+X9ejKhMkltLkourHMOtbsxQhrpmCKctVE8QD33mvv8QkF
SLVVR8uVrFb8eBeP8UogsjMOrA424B7JTiY2l8euUvTdycohVaXZ+C+9cBpnNLWb34af0a6qQaFF
/hpUsQhYWsF5uvmB2tuyEM1eosr/7iSbfTWHpfj37vEWkMu+lc0NG4GdEWA5mBNrWPl4EKIzgoct
0lEO5Z2aT9TP8WprqpamGds03P7Q2fN7krjNjcZ4Vk8cvY12VKQJPEJyE7nD6RpAW6G23PjaXkz5
PKwA/FT2BId65P9gh9z6ZA/2CTACeddoy993ArCGuzaTR/tzaufO1pYWyhB2Z321S0Vnr7M0F93D
kdk110YIjnLaRzL7lbXkugNbqJJAa5fDjvAjpW3npHw/FE/GweZs85frImuU0IbIcKeI4nUkT4bc
6PinWNYoCjXVJ+K2WA/4kcpOrQyKLr6a3GxGIQq5fQmBf6WvVwqAUYND+0hkWewNRvu/K8CLJQrH
H6Xx8ReuoYnt4D5k0n5E9uJ9znuioTLDdLrWyoTkysTydZAYvdb1/qqxcvWLJTLO/Q6G6VkE0vME
134fqdi+yeqFl1eaU79N//N7MLXX1vqku7VxLxam/+nqJjeob0GibzCFqiK5WsZEhG6q7pboqJp1
49oOcRd++apkH5xRv3YPGrYXGsGYTWMxa3zMlvCasTouSLp78lAju3ASiDJp0o3jfSMsQxnuAqXa
Z9/0W9dADyGp4z5HqmBvggq6rzRJEN+cNj9HjOrKtXUtgWZYi8oPa7EcD12KRxfI3pz73Q4yD2+R
EW8tBLCKAGMngocMDuKKuQuyhzazZqwneea59+n8K/nyjTvu1+mOK12T+4N/vBSglIJpn1YAbm3D
K3clIAODvnbFoeZhqjhgi8bc9xiUDCPk0GFRqqCHULeHIn1ycLgakFaj8jlORchne/zgpAQ9Bl2r
l7wHWHqFaCMh/JpU+MvcXKo6VJ2YfTtOBL/Mmi+qKWc+6WfL26klLUf4Unr5xfIIYg6GH8jDGjNg
70bazLfT9g2TgG1GPj2fQhVmYhzRSOrlNM0+zBKF1Ayy0P4rOka5VhWYXgXUTpCHsD4OKd5TglOr
8wZKRKHUp9+vr4BLDpOUpBZZ21BtgWQO4grzhTI4PyJ09ypw6PaK1viT+c51wXHSK5g+aHVnIA4G
avq/5MdgMXF2jZBP9+/R5tLHGmejDQBuP4uopIbs0lbYe8fp/K1Q0ChND4+Qdkk2OEILko2KxVpE
ZA5dcaocmVpYJJdf8lSpkj0WS30jJlEzdNnoN3lxPXokgxTEYi2so2YSRwQ/GILdD0hkN5Gj7vrO
nhH20315h6u9CixvKwuxnO24PXwymMAoBwZoL8CwvyheVZbw03J/1VEzGYLc/euhY8FJLsORo7aF
orXTgdxorIPXKkQyloBtSCFYc3Lw84BC21EY5/zlGQNH/R5IHFcc2k8w839TwbeXESGkOo8Nehk0
TktKgascbiDxObr7kzk1r8UNf5yr9aIm9PevLQRq03S3AocWrV3CXvwwEizB9GFpT59u7HZeLDae
ophLKegAZACNl7MIB6KMzHJvrghEfIORp9mrmITXe3xooAXOsQ+Xn4Ji2D6ItLSA1CF4BHTadSgM
Sxmp+cc/Ju3vkjF64EKnD/q4R0iWyJtxfl2Py/G9hxCpcq/d6XQa4NpvZNRh22Obe4PVUK6pYFpB
QzUBLlBrKQ9ymfPAyX7TEbzJURZ6emmifCEkiYaCR5rukAEQiN8RV4H5hLR/X+Q9j6Dbn+6TCtF7
UMoinknlB47oPxZ/8CS4XTR72bRPEKrydfC9qn4ikGuEmBagoYWKLT7S5K7X6Ty++cA890RGktY0
Idr3EzWmWfBpxRu5v4q2tOnH4z42N52Leb3rJXzqFvrx2MmPcF1aav6Ij/+lD9qG4i5OivB8t7Di
QqcK8Kq5/LIiVWMVgHj2in/aB49AZgu3ofAjjzjZBGV7pkYQtCfkFWCJ5NptO09xJRCfOHrkwFrE
rJ6ZAQSUummLijKcAySxfUuBQtyaMXJCxhDA7535mBVH2ebsWvZrviBumRBmOViqQm3kFlCrzif0
84c72VKmf1tsjy/M/hpmwO/iBuq3PP4LsiQPZc74BUDzUXQB/reDIAtgej2zEhVPk+BZD470iH7m
h4Xma7E2OveW5rEiqM4sQ68itJ8Yr28hgtc4/j9A+RjqGiuJDUFVuPgsnqaMj7nFLS1hrgjLhjai
NepMOwdtXyhMykufeVeErFSLpXHl0C11MEgZs3lC3uiIoDntzPBd/TwjMu9VhFo5JAl7DhY2gT0k
g5oqdW5/h9mnPdaMZUKroi1MBb8zO78ulCZyWUigy9Dat7nmmZlowA4SAEGRRLtsnbp+U19i9Sxg
ehg12GHLEkO8YqWBzG1utGyWUJwfcaaYlUlh1BXW75GEoi4krbTPGOb478gcE7GD1nll+x55d93L
wZdZURoGjpWOBr9A2JALp9jCCKdvlwruyzlsSYcq2T5wN9QYruk+S8/DakJXXOocQQw0E5wZHney
qpQG+1z+HStcR8JRsqbKaxYm44aVPMGNnaNUFZgqTjEQRvzpg63EQKfctwfqfHE9vqTiJKuhfR6f
l+DmPGrFUYLy2H6kZ6ayaqNHFEaUNVvUebrk/BpDRwQxTa1+kK4VazAOpbBzmwxrE0q+aPmpYWu2
ivwE3QBF66PVwzelsa6SPwFFJe2tQhhBWS0xOkSMThgPdOF1tUQSqLnRrd4ZNyESPk+yffGvA6jW
32MTIItwHyOkBSWZFMj/xSQOxWNkaxodkAR0xA4ubXBeUefwCXa19/IjvRYP+A+XPUGaIZabuymn
ZDN54uNhj0saMQtakvMkB+dS3gX4Pf6I8xZX77L56EVPevMO0jIFACCODnfa2anznkwYvEAmBaE5
6RiTrZ3PHWic1gWRrUAe3LW64ECSgDTUOZAU5Z9ZWgVO6Ad8SfRF4bSoQ4qPiGWAFqfj9s9OTRSz
W/ODCn+7XVj1ZCmZFZ+5q9N+BYhQyncrw97jmxqo/gtRWrulVcNAlpAFvII4seGEXn/FqNxzLhqP
hFyNGa/NqM3mQf2JG8TNMq7/fwILnY+no5G8jV/bE8fVTdH6cM45MM+AaD3U/proYb5bLs2AJLL9
gcjJII6A1WyaNNsruU/UDUR8XoTCz+eCdUCv+b9biu89By3aSF7P+aujZtKC3GmbToPsiEbr9KUC
MUfgzrPSkTsMOGXYKDe7KQiI6+yo4IboZW8pWgTtjeFv01vB+vpbJnXHH4i6JpyeOmRU4DP+d7ri
BXaDWJjjG/A/vfo65IpCGSP/fmmJSc7SQhZlREACMvYr1FFfyd62GVFemKoG8IwbXAkOQXyqsub0
/nPnSgRNa0xaaJDkOtuWBvBPKsPyQXszZTdr0yPTcSPnE3cktITNf6ZUC0cWy9HmgyU/O50nfwVI
I2rHWeVnRtME01em8jO/O3hPiSpgJeAg86GpYGeQGwylxWd1Ym9nk40lCT7gWNTipSdfYNXO0TPY
2YfknzvcOdDkHH+pdN7HA6mlcf13WoMLn+UWKtYkxsNWeLzV+kpkixl1sIv47kVQ5j57cFEN+U0P
b//KntvfxlQTtOMCHVUbd4PLnrrQUdicGLnJwjegJkXJpAe3hoWCG+N8W6zeCwyR+cW9Jpy/Ji/j
+MSiFKjqaW+5I28trglTTWI6My42FWm/fUUnXDb3XZjfib2LsPNfp9tU8YrjnFqAodUKEQEcZxB7
1whvkSZkMyqDU73aC3ezcewS84/s2Hj1UBpEGcpfnswZ31k0YrZePcQAnqVjDmu+QvRW+9LmekCN
hnfeomlVPSUgOB84K1VeP0IV+DqpeTlGLSyUorAV+1OJJEDS/gN4HOgPc//LJn9f/S6wnCouV1+W
PrILcbiGbysjMrymEq4dzUZfvMZi0qOXoTbaD6DzxGpN33w8u2RWUMrnqrCu5NvBZ6uiJvd0WEJ+
Eco2GtfS+p4sK2Luv/tgL0DkGLXlqarzp3Wgu08LKwof04G6mjwueLD79iVDfYSkE84IxTuQQLDn
hLE8f0vV/NYMKVl7yJCcZNwKO3FCfNMgcPV1+PSn3Fj957q2McqhMJD38gQCmTiiL6P8NZ+kAJmg
KYQPdtAGwE3jMF9AV2OEfMApz9frdCP4IjF54nTa7zM8uMguAKYf9A5DmJfvQAu77M+qCHnQHV2E
S2VrgThgdhNG/MA4CHxXIOWk4UWkFHscYbr2oAfQatuvquejNUOmohaa3R038M2nojo1I8Ey0JSw
2f86WZRBxBEhajhvcCeM38QOcY4DgErxEiX0fmpKlAlIXRJIymGFG2Rdh6wZXZMF1ThcXPbwnR9B
rHyLLs6/aOUfrlyMU9B6J62y8DLDyGm94l+cu9DLMfXoarpER5RW6HMn0mMTZURYCYrKnJT+oIcY
xl95nLHejkK3ViEEjMtFOeFSdGOZlTv6hlbwmDzcWSSmsl/ZWMB14j0w+GQ5uPA3qcysxdxPm+Gb
a+GFjr9M63SAolue0leaDTjzA4GzkjEel5PPA4OI8/Ckp4rHUVSLlRmRrrQooFuEZbMtnX/vFjWs
YFse984REBxBWvr5p5WknpTcU79T+1quD8BMvcxUlAfrzcm3/z+lO5qpJd/rECn9nfrrBGjqHgvz
3vnuEInUmsmZikhHbb+l+0HzeRs25klDwY9xXTCBu3y8GlWNnSfJWjqmecaWYojhAA6K8WEVAJra
RFv8jyMAYyYdxQ4zEJJiGB2DpkvqPxGLva+aF5lFCke1wCQmzHF34P0YPk64Z+mOWKfLYIRrJa82
k0epOZJCb2O2sPrB6t+BXvaAExAKcW1e1NUzQ7ZkdERKWlfmQZ8qyZeb0jlZ6JHLORE/q9Vl5WSD
ClNANQ5SiC7AEh2/2MZKh/EBjpqOfWdo00N2fbhNU7tbqI4grK0UGU69axUV6EqJo9Wv4HHsG/FS
TbbOgKZUbIgz/hGT4nAPwnRzSzkKfmplYvn5FmUPPZuumeG7tqFTKxodlBLnLf64oMcH/CbQ0Gud
nSE4uo3RxLGV4I81nbyJ7p0jsVtFwPnjcjIFIPdUWF/NXTmvShg6v9D2MOfr/9hx7IibMKxK9JEX
egGNPBhreqohPFyd2Nvi42qMD5JdRk1wIMmGSlKIHYUHZhlokxoQ5sWqDEx9LO+3/4LJfnJdkf3J
HIssqR/VASf+hhge/mkbTPBNVKTpZoJYswPmzghzvoK/Ww44FHVOGzWMnHlJcFei5tXz2r5QxIGy
1mj/9Ty0ZPEC1fWVdO3iUpEbnGOrxzo4ePJGRLiMvqXqy+GA76024EM4b7sBiMchH3hanQR/1KQE
x53FzVYCUrVfYDKPqMU5ILvav3cyMGrd5oVR39soin3WhZTnxdWoXC4JTung/YEUIuLZjFySWFRh
sHEai5p0alqYSj+oR1TxsIP03vsmwxNJja8PAzbV2hrP3u3cDPBcKg9De0X9VZzFchljH8t/6MqU
NSqVvqqiy5LikOVrrkfeAqoT99CDhp+lOqX6EvOrdPeJGuxWF2JXmO7Yw0pfsuBAN7EhEjunJEja
SssrFtaiUKMWIuqa+WWd+ovqjMgEzCsDZEk8OsTFxTxsmwHTmZeev88k1D37l6bYzZpnXJaJpfTl
p0kQ7Q4WkUhWozNVqI+x4tdQ4V/HNNm5ci5MEHgsF/pC25b4LUCLFJy6nhvT5bg6KONn6wuiPz6t
6fx+x/nfkSqJ+ShEJZL+OLOQH1plwVvwU5ZAHujDIajbE6nzoj2Bi91f2ZUkYHmrEzdwO1qsePqa
JWvkvMGermAjbeo2DHtsHKS6734yfspvyRn3Sw3zfHJ4mSawFllCRJFGKP80vI9A+xgs/h3wNetP
hhxB4qWBvqFt3ThINYHtoEr4GsMLThEQ58M/+ISYh0cPBxaiW4b04HVShDWpX5yKhwDtV3GEUsZY
q6yJiY4MJuD6+Ps/Z7q9Nmn5NMcj/toKFIEssSR/tz6wxDu6w8xSOau1vSIRHu0tEuiB7WJihSug
6l02qF+NWq+D+ZFiIljI3V54fpiDGSpauzjEzjp4c6Qx9Z4j88zT9xwuCb/gDcxPYtp18voRavkm
nhA5UdnhAEEC9Idv4c9H6H82xh1nP6Cfo0z4flRaO8i8BlRgjoLK47Gl5qzeATNuDCWGwiSmnWnH
kjIdJ5/CkcvqHsbZ3hSoAlU+WVc/igF+f6FHxIADfPk3lt9Koc3keiSsDpfq2ONsDaClr5D9BrMp
NwapGjOAlp7UgISMwfaM0vEHEM4kqePdOFuw/5ZxYbL14WOXSzBxIKNovJEGznwa542ffDIvo0R5
KmylU51RCrf9+hXwaZ8l9A9mXorHUcwNXPR41UBpjReUD25pNNzLi7YXlEEZfm+rggLLf1EaBkBC
hVz2hkfpO8iI2tptRsZhsmRNfA7mTusIGbRDanw1fpkxkAY+2enh0TLxnTyyGAG0t6u2UjLmha0e
MQYhsl7Up6HG/pzI+8HutANWlSOx7IS/3yRia2YEa/aedJ7ofS7JAXLRQooC9bgCfNkYO7eW8zLr
aJln8+5BA8qC6LkomaX58/pWcUW7ichw2GLHfl0T8UJRcYU9K88NClRObAnU/1dgVmoEeIPu8zCA
JosLNr35svuSbg73OjmpYfR2Z/6tfRSO80qPxPtTBRh+WG277vZnv0dS6JAl5NwCTnaeyYuK+B8d
k5woI/RVhmlsKDpue+njQopDD0cKZuSR8PYb3WpK3OHdJf6oyzrwwUYtjwclwfrQAXTem8Qu3mOW
Wh+K9/V3z+72JE1TpaQ2vFTH7V0iDme4c/oqZzHs9Lpy8aXQrpvdVYgmjFmoL1kRK9q0fW5QigZB
hsfp39IcloV16Vhpz5+lF/sL10xqEgGbMpIOqAm1/4uCTxgX0nR8uA1Qm+F2LMF5XEdwmvFkx4GK
hQevrVU9kQXY9edv9uKZYu+E/FtOhjHUMljpMJAHr99wlyxX9jQhPqQ86zD+H0OvwwnmCHnh/+wg
PLt9NNkf/r9iSMjyPJYs9ivqSQNC1DtyOVYkqEkwr0mnxfaSPllbZJBtegpdmrT+zXOAiWXz1IXY
GH+L3XLjG/aDTeNvPHXVMKlFOpHV/ju0Y600T6OL6HYSOzECgQSUGLG0Vy/Q4zepTS7QJwZ3whlR
EFGY2Xi+8oOUkZaTNvVv05cm6hB9VBtRrBF5x0FDriTfNI5O0pzZL9eaaxXT7yWvwvrZcjhHQ58/
cNu6usGlnNd02/OKFJWF8b1Vjaq75ZxttDAOC+/gTAfxeE6rHzg3hmkqW4Y7941+eo73wTN2pCuE
Pj8zz4/KQcSTJQZlUJx+LN4JwtRZ+myJwR6YcY9cKvhuu/sW2WzGpvkC0/6YF4QM3JNcw2FRTDnp
1BGYWap0wxEuT6ktvN19IMYTBbDrzwIEFpCNQ6+xW5a7RJGYHaen0jqjub+DvIWJ8gFmUy2QaZuS
8uUH5NDu7YoTJ1aANlCYXOD5txsGvfwQPzx/QhdcF5GP0w80ViQlaTCuyM+gUyN7AXnTM2cFQZAF
sWCKGzaKfXzWfJyfG6ziP4MR2HOWvucIG+4DMi9tCULJOyNb0m8xy4+OTtPlZxnKDteSaeCfxQw/
+CQHVTl8IjKQmez8fF7G6piZX3zTKm3QUvsRTR9fRidXeHsqVxN8CJ6++bRnhOnp2/XYXeV12vQ7
JM00GtU6Hs1d6m0PIC6qXKyAJ5FmaQuu/JzDxoikClnSOIzXdHpPucFe9kvXYEPvuq9lT7xI74Y5
ctxSGQvgMLtnNOBjt7i5iKnmAm8GXu924y4sm1XJM3VApyg6HbHFKuPHK6vjYiEI+KQET7ufUmyK
ENuq1iSOGdGbGHCJZ4DxEjrIYOclHDAL13yYFga1ctVEmrViB9YWMFjrAX7C6UqUKxJaW3UFKfGP
XZPyAaSwS86g/qvgT2ZvVzC6uwcRPj7einzcGamGQ7qgk/SSAyO7JUquaPJcilOJL+2Q/TlCuPB1
NAGNljZYgwgKNiv8/pKz4K+js/AkKtFM7lmCXHMyp8fp1bliALynk7TkyzKGJ+YykuNYW+ljkyEA
ZxIva7STdtxwE9Ctw1LjpU3d+R9aN3ib+Wy711KfMcilpp4MDtltos4CKWfzzPPI8XFmjS5ZkZ2u
0/fw/hafWsZiCRUbFe8cIC7kbOK1BjzBcYDRGDWKNg9z4gCdJiV7usETGQftaNEL81eoNMsJFd2Y
GIklQqyuFQsntnKgn/YBq+RAkK09JFyVUJrSwf8AvZPSBg9DG6C71AsN+/HzS1qtUHXjYZe7kqIa
5z2ePOsrJ0iUnkBW/zoKLDNFSMJjystlRDGhmLItXdsaheuWqAM9xvn3gkqpo5nPBSUHU6PS9iTT
In+x4Mjiorz9lgEW0uCOlM7ovaGDN1p+T3m9Dsg2yjxw44P2njQza6aS9am8CCRA3fbNIpDH11GJ
93wfG7cuPqkRZRhjjPq40ym0zyBOaEgQxTGroYxIYpV/E0TU4Y7ehsX4yXY5sCnNFuqewEivvkmC
+idQoKzi1KwfVDOaD6I1F5mUOnF1rgIjL2H4CPe3NeJ4FiKLQWMsohnuFVxEUennPQDDos7lr/1c
1L1CEBsDoxfvWElKLe266eqpVNhuWzNiP8wrfZ66vxBw7wafPIKPCVmJK9x53IeXgQu3WfH/7L47
XRe94n+7uqXZOITpPgz6QW5A4JWQdze6tRAYhwM6EYbZHmoxmvJiOQkrFTpXfdfCjL/XOKve6S+j
xXXfz00YJ1Gc3O3KjTzWD7qBz/1WmpZmjfEPIxT5/lNI8RbobZ4zvesB6pLkxfmFTllMtIPRt8aD
oXMIM9JRGcqlmc6sDVqLsm2dOuH+/oH7q+yIiFY1Q6QLVle5N1MCkwRwlu3HCCmkOHKivCyJLWex
RR/xFCiTXI0/YNwAewYkblHDRCYh41UH6wv+kWrne1Z5nyueUIyGGN12U1zjhjAOtgVQb22x8A6V
jDzPleHVy7CbWQ4YirjyOOpL6znVXjtjzrS3nThtCJSa19vy0KcKk+9LRYIqf7mskQvw/9LN5bGo
CSwhr2OfJs33fcR5g3JLtDkmvRZeTJD/7zHLD0+6gtwBOvrIBWkoLcpgv+cPXKUfMIVlrmFI2EiP
xo42bGeM2px1hJX7y58ZysMgmvOFAfJPT11unBrm7Bi3Jk7++TOW01HI0PB+i83W8YUiJ5NAj4g+
3raL+uXBlB9sf5WOgrx+IhmWDqwz4n5DJncSRusr0sH9yKDgmQAivaXPzBOeS3cOGRf5/kWsB8lU
F+/n2YLmXCs7o75prllCwCjAta4o8ceY6IUFmhCgOdlfVP2v/XaHUi2igrv9TsZpN76xJ6hZIedD
uzmMaRYapWC3Sp/9VMvzq9S+hRAbt/mnn0Ho76QUJgTRG72eeO50/uHlavU6GlYGJ+ag1IHbdFba
u3grD6MgzfedBHxDN3ouJAwfa41afaMmsN7KRjDZKJbcbnKvm831h3UUbSWqDCEB6jJrsUR9OQ5k
v+ym5NHRZAwibBSF0ilPUcGfagvY+xJmqgVOoPdxzAr1WnmWiZyQgkU6lRMRgvLwavnw8MSD7zhg
QWlDizJNQOy0GPnDYlW/3gTOXgTBsMVT5nURFN7VsUYwTEynWnZipPAVnnU+sfabDYDogEoQC0t9
T9Eqvxi3Z1qEMA5rsFqirXn2Ja/sKbl6VlxalaxyGILtDH9rIBExomLJD4m9fgyzANg8RQEtSphp
zf74OEV9kdhC/64OT0RFaitIYin+S+qQy3Zlj8H/S4QEUdrrbNJ01ry7tK7PMBvOXGFVMMu2s9aw
qdbRVzfLyHwVzObPYOUq1Pc1P+rJAwj6h5LYBkGKD7CtgwpcdgS+8YQcSDdCXhfmRm7H3b6/rXvg
clbqmkcrZqZzSb0XBqd+hkNHMFG363ym6HuN6z+JNVugiO97eR9omwK9lecACUc8IE+Iprddvftt
FfAE/9EClI6J94FhPGOgyZokqmoGehQGKZPsPsUtB7G0v72jjDp2/7UqtpTszuu9e6O0LiLox/4y
MxPh6uE9liNR0PCcuB1X40Lb7+wcrc5nAwnppi6IRz5ME7n09PHuRUyHG87OYaar3CIHX77qSR8y
gRIrsyZETRJbwrSqAti8kdMFEK2Uxeo4rj+dOU1huUbiMkCgiFsnDIO21keo5CtwFVQYe1NZs6p7
T9VsTQa5d1TsJzi3BvxwQxk86UzviUaEg1iVbCZBwNlpDsSOJB/YxCNevIHECvPERDSPgV8+wpI5
YJvsUv4p4a+sVnjfEV6mzlV3E1IuQQYza5nSbkCAiT7WKzBc9j88thGfZw+oBqWdoJ9eA8IZQIkO
XbdVdtWNYQaNJ86+V/wDQzOe25luNx83sZqaoLPlw4t7XJ6hmME1MFmxCgTVDdyXDbI5kfjd6Zj2
ZB86gTK7OqmLvguk4rvXpGWl+rr5fS9iYGlXvzVYD6gVRgYKjgUC5AfcSpRxlItZczbT/aLqe/3/
AVIzMRoPxAA7D7osTw1g4/R/RrFZK5eyuR9pZ9rqJn95gHEwsHSsWGDZHgt1ZOK3Qba7NiVcGLEp
C0SoY/zhNxwAkgaKHnagzfd9ObSEUgQ17JIfR0P1DMQdw4oaN/VScu18ILLmvfiMCysc0WJYGlJK
dudTaYhulr68l72PjrOi4jLhq/RAzL2Z4K0AyX3ESRVJhO+P0PV94a9l5zNPo2jbDD1FZXtoxxJf
pGjL8eVU+2/lrwfvjIFLUKKmp43PF0mIVfe7FuC8ZnaVD1NxTqTesCRf6lazoVTevoXO4XMDZ5ir
WSZl2vQ8A19b/1TYbu1dtXTLFPgMgp4c4zMNioJ53/QVeqbrMTWOPy7yv2LcDTuIeoSMMCinU+pP
iiXyyIp/wFis5OL602kYGAixRFGW39V/2TNGoYKNDbekMNCZBR5CiwWpikOgVAj7llw2VpTAhFc+
BOt7deR66joRE50rd2ecEr8eo5+oQ8gsBu4bin1RnuAlUOXc9FXEzVfUhtshcrTEpyLqR7yYydW5
CSLfHexWtSijKDIasUL/2sE3lKIJCK2oVm9vEnAvQ7CIfblJdhgqs1d+BLwSCdB6ITKaYc+jhzzW
RXCAU39r8r/yqyrsTOdHxovfxdg4176B/OCLtJeKDEZlWnItT80WqcbmypnEI4LtaMaz+OjRe1QH
SMdRNyFKGmMLGu2B84B1I9TgvmC8fwlNhtH3mRuYB+I1z7niG3QIB2EvCQXJE2J5avehTSzmFUr0
he3gkFZ0DdQQqNZ030cvJ8PFo2dyeqeB3o8WI2e/h7NjX+vubX7wti9e6W0cJ56oqMP0kIIoDYbX
Z12Q67Kr475RKQEwqR39ZS8cRLp0wWTyCnSBokrVBq8dddxNxM/XIi8s0vrS3F+mPugQGYpEJV92
fcIPlL1d3nfALzKKmctiGYCBahUA1Gpw4cdDPOHDE0ccd3sy0P3Az1cC7DA+j7A9qdaq6l+htXqN
fa/ehBiKJPWzGgIRRUfsD36RqhRKhcYhQF8QN/S4HqwPB5GvKtq2UShCecmAVFDNx2bKpon5LM5p
0F5ZWIuv98DXlpCXlf48+HY3AtlpdmDFRver8XkkpQ0ksa4VEYWfPJQ4oSddGG2HXVJ2ufRucmu9
fp54JugOtJEeYQWIGR0YmvtSbGk/YdGG6JC56/1CHklO0cL9eUxh0Hve+DmmZy0gf0rVXvsI7dVX
2mlB00Z0DHbRqkeeZZOssV08XEQyhvqPO2fCkijJTfFrPXRi42AOQCHON1FHacEEuKnZB0TXeBq+
krWBdfp7NeJlyGUyvvCKGeS7Cm6IsBHJcIY8IULaT86hHVfqlVbgUmrLaLo8kT/e8SxRFP7y0R9l
SPIMfWrj74TJt5z1EH82wCkKhy8Ov57KuDl0gZX79EaY4YfuYykeFWkTyqH13pIvUzZZ8/UmATtg
+qNR9YwyoIliadoPVGEnDMJyH7KzwZR3RTxAla74Y5dAR26uPtZp0YAaT5Hz6Vv1F1Q8MQGhjAks
h9zDWV8RkcumDXrP9UII9gzUpSh2tCaZJl3mOGdThjmtnwMBkK6NOeAu4EbOP+JAPkE9MZOERtm9
2kmnOT+XnB+jCKhlQYHj500KwT4zVFzzH78zfqUTeB/kg5O/HX4rwAzfIlc8oNHvdBwZGqrBquw2
cVTF7a0wbXJxge4asn/X1RtTHfDnwRs2A/gsvu+RiJjoHdw8lwZCwnS2mMeS8VsNjAR3RcS3Cej4
ld9vKoU13M5zn4rzs88+GgfB9EYTdpR/Ee0pQshQdhVxwfKmKXJMvNPmay6tUnY6tXZyLug1Wb4h
Mm4Rxf2EkRHIFIv5g5x/Sn68PP1CSXt166+RZKBFgtjQc1mGd2VDrxS55IEsENKnGGhk/a9Pmk5L
Aaj+yFsnwbg3DndYoZuzaS3n+qdg3/VSbCN99k/EFRh/bSlGDR2H6kbBraKMzcKKdoW/zNSj+O+i
xqxA6eq8QxcfQQ8MIhlX3tXDSYrO6YzloPjBn9BBCB7RIrzWcB8cWCx6v0fTIWlqObIlqGD9e47k
kd++sBei8owzn0sQ9mQSLJDirb6P9icXCBaM/HIyLqfNAloSZCuaEFDybnjNRI+eUXQ1Nrh9ch/F
jIv04IgUyTVCr4SfvEHgtj9r+emaYwmbv70aX9DlT/mpOsvlWTKLYC/2wIEggfr0mWOkv5o56uQH
LHwHRxlE14jPUvvozaKbqtvICSJNi0SuxNKjHjaCcLqaUYakdpxDf3n3YcXXfGLyt4iGKAAm/iM3
55y0lQk68+3meTPlXiZHIIhYqAA5q6bZOwkI7pF6iMZipzcIOufLX0pAQOvGFGnqFbPEDmXzhM58
47tzdy4o09x2TVgbw5Wv6dYk9rNd7KXBT2XqvauK6rBTOT4xjr3kzb4eUnWUxzLpnGJks15FnnbE
anGKHUFD8nk+WKqhyn9okACc68UE3SYKH7BWcv5qoFe8JrWQvo/ZxxwB905moalHC4WRr8ZkHo27
IfhcIRglvbqxhm7TL/q7DWPkWVaaBbvRvg7u7zSOqZklGznsvBCX+NLilih7wT7Q8V4oQ4tGxNcw
cIqLQMWP0aPjKAaiXE53IXZDTrzkTgTJuvtCfaDLNC9kYfh68Cc/sHtWqCHNIGzlrALTJ9/G93PU
TsOa5qg+RoO4hEYr8oVWc0ifoaYEGUbxtmcOm+M96qTg4Cky5Bio0YUXOnvtd+TP+okdFFme5/Bl
zG1rmOUqIBDbXsFRNIW8be9hBfR1T94ot3dKyzo0G42SWYgjMFYzAIL0AqjSuaCMW+l+I5tvGBgU
pKhsNIZtWsKjXex0+yVYCbiYDsXlNDN44ay9FJCrpQe+iOBvTKMlSHGY+w5bsFEpl6cizGLCyMMr
ApcRGm3eFhn/BbZeZP5LBBvEcKrEBbCSxon7YTjsvzr3J0VWbsqFh05LhXxQwXFpS36//rYTzH0Q
hKtXqz6e6YE/RnpD5Wtt1odZ5H97ZjIdA3r6QiQyHsCJWb3O2QVmMz1J1VomU3i5KLyunj+D68EL
mo1UAk920vL8uCByla2JemULswRlMU7uzOn33+qpuEgO9QReAsEpxIQJ4LAcEoHkBr1x7FAYvNTb
YbcA55lfHdN2ApU00xfU8zsGzpMyZo6+fE7UeNKQU8iN02XcGx4O2pobQ9AI0hhHwNXo1Nhiuvcy
kKRLc+794Aq5cPr08sNHKnyL9Ckyp1eH++50mNSQ6vWy/GT+e1+nnRyT5UJYU4UqxDAD6STxV6Fa
zLK8gUz0YLG3JV+T/OClo1jKRRIa7aKVbfuTOf+UNtNY5mrtFvjofiX2ezQSkJEUcSgv7BVD5Q5d
WNWIXNJwbUq4oYMQh3I=
`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 is
port (
CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 16 downto 0 );
B : in STD_LOGIC_VECTOR ( 15 downto 0 );
CE : in STD_LOGIC;
SCLR : in STD_LOGIC;
ZERO_DETECT : out STD_LOGIC_VECTOR ( 1 downto 0 );
P : out STD_LOGIC_VECTOR ( 24 downto 0 );
PCASC : out STD_LOGIC_VECTOR ( 47 downto 0 )
);
attribute C_A_TYPE : integer;
attribute C_A_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 1;
attribute C_A_WIDTH : integer;
attribute C_A_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 17;
attribute C_B_TYPE : integer;
attribute C_B_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 1;
attribute C_B_VALUE : string;
attribute C_B_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is "10000001";
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 16;
attribute C_CCM_IMP : integer;
attribute C_CCM_IMP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0;
attribute C_CE_OVERRIDES_SCLR : integer;
attribute C_CE_OVERRIDES_SCLR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0;
attribute C_HAS_CE : integer;
attribute C_HAS_CE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0;
attribute C_HAS_SCLR : integer;
attribute C_HAS_SCLR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0;
attribute C_HAS_ZERO_DETECT : integer;
attribute C_HAS_ZERO_DETECT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 4;
attribute C_MODEL_TYPE : integer;
attribute C_MODEL_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0;
attribute C_MULT_TYPE : integer;
attribute C_MULT_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0;
attribute C_OPTIMIZE_GOAL : integer;
attribute C_OPTIMIZE_GOAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 1;
attribute C_OUT_HIGH : integer;
attribute C_OUT_HIGH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 32;
attribute C_OUT_LOW : integer;
attribute C_OUT_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 8;
attribute C_ROUND_OUTPUT : integer;
attribute C_ROUND_OUTPUT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0;
attribute C_ROUND_PT : integer;
attribute C_ROUND_PT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0;
attribute C_VERBOSITY : integer;
attribute C_VERBOSITY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is "kintexu";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is "yes";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 is
signal \<const0>\ : STD_LOGIC;
signal NLW_i_mult_PCASC_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_i_mult_ZERO_DETECT_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_A_TYPE of i_mult : label is 1;
attribute C_A_WIDTH of i_mult : label is 17;
attribute C_B_TYPE of i_mult : label is 1;
attribute C_B_VALUE of i_mult : label is "10000001";
attribute C_B_WIDTH of i_mult : label is 16;
attribute C_CCM_IMP of i_mult : label is 0;
attribute C_CE_OVERRIDES_SCLR of i_mult : label is 0;
attribute C_HAS_CE of i_mult : label is 0;
attribute C_HAS_SCLR of i_mult : label is 0;
attribute C_HAS_ZERO_DETECT of i_mult : label is 0;
attribute C_LATENCY of i_mult : label is 4;
attribute C_MODEL_TYPE of i_mult : label is 0;
attribute C_MULT_TYPE of i_mult : label is 0;
attribute C_OUT_HIGH of i_mult : label is 32;
attribute C_OUT_LOW of i_mult : label is 8;
attribute C_ROUND_OUTPUT of i_mult : label is 0;
attribute C_ROUND_PT of i_mult : label is 0;
attribute C_VERBOSITY of i_mult : label is 0;
attribute C_XDEVICEFAMILY of i_mult : label is "kintexu";
attribute c_optimize_goal of i_mult : label is 1;
attribute downgradeipidentifiedwarnings of i_mult : label is "yes";
begin
PCASC(47) <= \<const0>\;
PCASC(46) <= \<const0>\;
PCASC(45) <= \<const0>\;
PCASC(44) <= \<const0>\;
PCASC(43) <= \<const0>\;
PCASC(42) <= \<const0>\;
PCASC(41) <= \<const0>\;
PCASC(40) <= \<const0>\;
PCASC(39) <= \<const0>\;
PCASC(38) <= \<const0>\;
PCASC(37) <= \<const0>\;
PCASC(36) <= \<const0>\;
PCASC(35) <= \<const0>\;
PCASC(34) <= \<const0>\;
PCASC(33) <= \<const0>\;
PCASC(32) <= \<const0>\;
PCASC(31) <= \<const0>\;
PCASC(30) <= \<const0>\;
PCASC(29) <= \<const0>\;
PCASC(28) <= \<const0>\;
PCASC(27) <= \<const0>\;
PCASC(26) <= \<const0>\;
PCASC(25) <= \<const0>\;
PCASC(24) <= \<const0>\;
PCASC(23) <= \<const0>\;
PCASC(22) <= \<const0>\;
PCASC(21) <= \<const0>\;
PCASC(20) <= \<const0>\;
PCASC(19) <= \<const0>\;
PCASC(18) <= \<const0>\;
PCASC(17) <= \<const0>\;
PCASC(16) <= \<const0>\;
PCASC(15) <= \<const0>\;
PCASC(14) <= \<const0>\;
PCASC(13) <= \<const0>\;
PCASC(12) <= \<const0>\;
PCASC(11) <= \<const0>\;
PCASC(10) <= \<const0>\;
PCASC(9) <= \<const0>\;
PCASC(8) <= \<const0>\;
PCASC(7) <= \<const0>\;
PCASC(6) <= \<const0>\;
PCASC(5) <= \<const0>\;
PCASC(4) <= \<const0>\;
PCASC(3) <= \<const0>\;
PCASC(2) <= \<const0>\;
PCASC(1) <= \<const0>\;
PCASC(0) <= \<const0>\;
ZERO_DETECT(1) <= \<const0>\;
ZERO_DETECT(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
i_mult: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12_viv
port map (
A(16 downto 0) => A(16 downto 0),
B(15 downto 0) => B(15 downto 0),
CE => '0',
CLK => CLK,
P(24 downto 0) => P(24 downto 0),
PCASC(47 downto 0) => NLW_i_mult_PCASC_UNCONNECTED(47 downto 0),
SCLR => '0',
ZERO_DETECT(1 downto 0) => NLW_i_mult_ZERO_DETECT_UNCONNECTED(1 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 16 downto 0 );
B : in STD_LOGIC_VECTOR ( 15 downto 0 );
P : out STD_LOGIC_VECTOR ( 24 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "mult_17x16,mult_gen_v12_0_12,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "mult_gen_v12_0_12,Vivado 2016.4";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_PCASC_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_U0_ZERO_DETECT_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_A_TYPE : integer;
attribute C_A_TYPE of U0 : label is 1;
attribute C_A_WIDTH : integer;
attribute C_A_WIDTH of U0 : label is 17;
attribute C_B_TYPE : integer;
attribute C_B_TYPE of U0 : label is 1;
attribute C_B_VALUE : string;
attribute C_B_VALUE of U0 : label is "10000001";
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of U0 : label is 16;
attribute C_CCM_IMP : integer;
attribute C_CCM_IMP of U0 : label is 0;
attribute C_CE_OVERRIDES_SCLR : integer;
attribute C_CE_OVERRIDES_SCLR of U0 : label is 0;
attribute C_HAS_CE : integer;
attribute C_HAS_CE of U0 : label is 0;
attribute C_HAS_SCLR : integer;
attribute C_HAS_SCLR of U0 : label is 0;
attribute C_HAS_ZERO_DETECT : integer;
attribute C_HAS_ZERO_DETECT of U0 : label is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of U0 : label is 4;
attribute C_MODEL_TYPE : integer;
attribute C_MODEL_TYPE of U0 : label is 0;
attribute C_MULT_TYPE : integer;
attribute C_MULT_TYPE of U0 : label is 0;
attribute C_OUT_HIGH : integer;
attribute C_OUT_HIGH of U0 : label is 32;
attribute C_OUT_LOW : integer;
attribute C_OUT_LOW of U0 : label is 8;
attribute C_ROUND_OUTPUT : integer;
attribute C_ROUND_OUTPUT of U0 : label is 0;
attribute C_ROUND_PT : integer;
attribute C_ROUND_PT of U0 : label is 0;
attribute C_VERBOSITY : integer;
attribute C_VERBOSITY of U0 : label is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "kintexu";
attribute c_optimize_goal : integer;
attribute c_optimize_goal of U0 : label is 1;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12
port map (
A(16 downto 0) => A(16 downto 0),
B(15 downto 0) => B(15 downto 0),
CE => '1',
CLK => CLK,
P(24 downto 0) => P(24 downto 0),
PCASC(47 downto 0) => NLW_U0_PCASC_UNCONNECTED(47 downto 0),
SCLR => '0',
ZERO_DETECT(1 downto 0) => NLW_U0_ZERO_DETECT_UNCONNECTED(1 downto 0)
);
end STRUCTURE;
| bsd-3-clause | 536a54a6c81ee7ab4a98a4f4aabe369a | 0.950428 | 1.820188 | false | false | false | false |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/proj_pointer_basic_hls_ip_integ/proj_pointer_basic_hls_ip_integ.srcs/sources_1/bd/design_1/ip/design_1_rst_ps7_0_50M_0/synth/design_1_rst_ps7_0_50M_0.vhd | 1 | 8,083 | -- (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 12
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_12;
USE proc_sys_reset_v5_0_12.proc_sys_reset;
ENTITY design_1_rst_ps7_0_50M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END design_1_rst_ps7_0_50M_0;
ARCHITECTURE design_1_rst_ps7_0_50M_0_arch OF design_1_rst_ps7_0_50M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_rst_ps7_0_50M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_rst_ps7_0_50M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2018.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_rst_ps7_0_50M_0_arch : ARCHITECTURE IS "design_1_rst_ps7_0_50M_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_rst_ps7_0_50M_0_arch: ARCHITECTURE IS "design_1_rst_ps7_0_50M_0,proc_sys_reset,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=12,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=1,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_aresetn: SIGNAL IS "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF interconnect_aresetn: SIGNAL IS "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF bus_struct_reset: SIGNAL IS "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_reset: SIGNAL IS "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_debug_sys_rst: SIGNAL IS "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF aux_reset_in: SIGNAL IS "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF ext_reset_in: SIGNAL IS "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_HIGH";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_2_FCLK_CLK0";
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '1',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END design_1_rst_ps7_0_50M_0_arch;
| mit | b06399fc852fe86cf72ca5fe41e4a4df | 0.728195 | 3.487058 | false | false | false | false |
varunnagpaal/Digital-Hardware-Modelling | vhdl/filter/moving-avg/tb_fir_moving_avg_time_mux.vhdl | 1 | 5,510 | library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use ieee.std_logic_unsigned.all;
-- Testbench for FIR Moving Average filter which averages L points
entity Testbench is
end Testbench;
architecture test of Testbench is
-- Constants to initialize generics of DUT
constant L : natural := 256;
constant L_BW : natural := natural(ceil(log2(real(L))));
constant W : natural := 16;
-- Simulation control
constant CLK_CYCLE_TIME : time := 10 ns;
signal sim_end : boolean := false;
signal sample_cnt : natural := 1024;--natural(2**(W-1));
-- Signals to connect ports of DUT
signal clk : std_logic := '0'; -- clock
signal reset_n : std_logic := '0'; -- active low asynchronous reset
signal fir_en : std_logic := '0'; -- handshake signal
signal fir_in : std_logic_vector( W-1 downto 0 ) := ( others => '0' ); -- sample inout x[n]
signal fir_out : std_logic_vector( W-1 downto 0 ) := ( others => '0' ); -- sample output y[n]
signal fir_rdy : std_logic := '0'; -- handshake signal
begin
-- create instance of FIR Filter (DUT)
DUT: entity work.fir(rtl)
generic map ( L => L, -- L = Filter length or number of points to be averaged
L_BW => L_BW, -- L_BW = Ceil(Log2(L))
W => W -- W = Bit width of input and output sample data (signed)
)
port map ( clk => clk, -- clock
reset_n => reset_n, -- active low asynchronous reset
fir_en => fir_en, -- handshake signal
fir_in => fir_in, -- sample inout x[n]
fir_out => fir_out, -- sample output y[n]
fir_rdy => fir_rdy -- handshake signal
);
-- Clock generation
clk_gen: process
begin
if( not sim_end ) then
clk <= '0';
wait for CLK_CYCLE_TIME/2;
clk <= '1';
wait for CLK_CYCLE_TIME/2;
else
wait;
end if;
end process clk_gen;
-- Reset generation
reset_n <= '0',
'1' after 1.3*CLK_CYCLE_TIME;
-- test vectors
stimulus : process
variable seed1, seed2 : positive := 1;
variable x: real := 0.0;
variable en: std_logic := '0';
procedure apply_stimulus( constant en : in std_logic;
constant x : in integer;
constant DELAY: in time ) is
begin
fir_en <= en;
fir_in <= std_logic_vector( to_signed( x, fir_in'LENGTH ) );
wait for DELAY;
end procedure apply_stimulus;
procedure apply_stimulus( constant en : in std_logic;
constant x : in integer ) is
begin
fir_en <= en;
fir_in <= std_logic_vector( to_signed( x, fir_in'LENGTH ) );
end procedure apply_stimulus;
begin
-- Reset
en := '0';
x := 0.0;
apply_stimulus( en, integer(x) );
wait until reset_n = '1';
for i in 1 to 4 loop
wait until falling_edge( clk );
end loop;
-- Enable filter and wait for M clock cycles (falling edges)
en := '1';
apply_stimulus( en, integer(x) );
-- Apply simple increasing stimulus
for i in 0 to (sample_cnt-1) loop
wait until falling_edge( clk );
apply_stimulus( en, i+1 );
end loop;
-- Apply random stimulus
for i in 0 to (sample_cnt-1) loop
wait until falling_edge( clk );
-- x = random number between 0.0 and 1.0 (exclusive)
uniform( seed1, seed2, x );
apply_stimulus( en, integer(floor(x * real(2**W))) );
end loop;
-- Apply upward trend stimulus
for i in 0 to (sample_cnt-1) loop
wait until falling_edge( clk );
if ( i rem 4 = 0 ) then
-- x = random number between 0.0 and 1.0 (exclusive)
uniform( seed1, seed2, x );
apply_stimulus( en, integer(floor(x * real(2**W))) );
else
apply_stimulus( en, i );
end if;
end loop;
-- Apply downward trend stimulus
for i in (sample_cnt-1) downto 0 loop
wait until falling_edge( clk );
if ( i rem 4 = 0 ) then
-- x = random number between 0.0 and 1.0 (exclusive)
uniform( seed1, seed2, x );
apply_stimulus( en, integer(floor(x * real(2**W))) );
else
apply_stimulus( en, i );
end if;
end loop;
-- Disable the filter
wait until falling_edge( clk );
en := '0';
apply_stimulus( en, 0 );
wait until falling_edge( clk );
wait until falling_edge( clk );
-- End simulation
sim_end <= true;
wait;
end process stimulus;
end architecture test; | mit | 62385a1eb3d25f735d0166b67c9da435 | 0.470417 | 4.241724 | false | false | false | false |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado-hls/pointer_basic/proj_pointer_basic/solution2/syn/vhdl/pointer_basic_pointer_basic_io_s_axi.vhd | 3 | 15,335 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity pointer_basic_pointer_basic_io_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 5;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
interrupt :out STD_LOGIC;
-- user signals
ap_start :out STD_LOGIC;
ap_done :in STD_LOGIC;
ap_ready :in STD_LOGIC;
ap_idle :in STD_LOGIC;
d_i :out STD_LOGIC_VECTOR(31 downto 0);
d_o :in STD_LOGIC_VECTOR(31 downto 0);
d_o_ap_vld :in STD_LOGIC
);
end entity pointer_basic_pointer_basic_io_s_axi;
-- ------------------------Address Info-------------------
-- 0x00 : Control signals
-- bit 0 - ap_start (Read/Write/COH)
-- bit 1 - ap_done (Read/COR)
-- bit 2 - ap_idle (Read)
-- bit 3 - ap_ready (Read)
-- bit 7 - auto_restart (Read/Write)
-- others - reserved
-- 0x04 : Global Interrupt Enable Register
-- bit 0 - Global Interrupt Enable (Read/Write)
-- others - reserved
-- 0x08 : IP Interrupt Enable Register (Read/Write)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x0c : IP Interrupt Status Register (Read/TOW)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x10 : Data signal of d_i
-- bit 31~0 - d_i[31:0] (Read/Write)
-- 0x14 : reserved
-- 0x18 : Data signal of d_o
-- bit 31~0 - d_o[31:0] (Read)
-- 0x1c : Control signal of d_o
-- bit 0 - d_o_ap_vld (Read/COR)
-- others - reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of pointer_basic_pointer_basic_io_s_axi is
type states is (wridle, wrdata, wrresp, wrreset, rdidle, rddata, rdreset); -- read and write fsm states
signal wstate : states := wrreset;
signal rstate : states := rdreset;
signal wnext, rnext: states;
constant ADDR_AP_CTRL : INTEGER := 16#00#;
constant ADDR_GIE : INTEGER := 16#04#;
constant ADDR_IER : INTEGER := 16#08#;
constant ADDR_ISR : INTEGER := 16#0c#;
constant ADDR_D_I_DATA_0 : INTEGER := 16#10#;
constant ADDR_D_I_CTRL : INTEGER := 16#14#;
constant ADDR_D_O_DATA_0 : INTEGER := 16#18#;
constant ADDR_D_O_CTRL : INTEGER := 16#1c#;
constant ADDR_BITS : INTEGER := 5;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_done : STD_LOGIC := '0';
signal int_ap_start : STD_LOGIC := '0';
signal int_auto_restart : STD_LOGIC := '0';
signal int_gie : STD_LOGIC := '0';
signal int_ier : UNSIGNED(1 downto 0) := (others => '0');
signal int_isr : UNSIGNED(1 downto 0) := (others => '0');
signal int_d_i : UNSIGNED(31 downto 0) := (others => '0');
signal int_d_o : UNSIGNED(31 downto 0) := (others => '0');
signal int_d_o_ap_vld : STD_LOGIC;
begin
-- ----------------------- Instantiation------------------
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wrreset;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdreset;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_AP_CTRL =>
rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
when ADDR_GIE =>
rdata_data <= (0 => int_gie, others => '0');
when ADDR_IER =>
rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
when ADDR_ISR =>
rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
when ADDR_D_I_DATA_0 =>
rdata_data <= RESIZE(int_d_i(31 downto 0), 32);
when ADDR_D_O_DATA_0 =>
rdata_data <= RESIZE(int_d_o(31 downto 0), 32);
when ADDR_D_O_CTRL =>
rdata_data <= (0 => int_d_o_ap_vld, others => '0');
when others =>
rdata_data <= (others => '0');
end case;
end if;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
interrupt <= int_gie and (int_isr(0) or int_isr(1));
ap_start <= int_ap_start;
d_i <= STD_LOGIC_VECTOR(int_d_i);
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_start <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_ap_start <= '1';
elsif (ap_ready = '1') then
int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_done <= '0';
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_done <= '1';
elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
int_ap_done <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_idle <= '0';
elsif (ACLK_EN = '1') then
if (true) then
int_ap_idle <= ap_idle;
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_ready <= '0';
elsif (ACLK_EN = '1') then
if (true) then
int_ap_ready <= ap_ready;
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_auto_restart <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
int_auto_restart <= WDATA(7);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_gie <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
int_gie <= WDATA(0);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ier <= "00";
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
int_ier <= UNSIGNED(WDATA(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(0) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(0) = '1' and ap_done = '1') then
int_isr(0) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(1) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(1) = '1' and ap_ready = '1') then
int_isr(1) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_D_I_DATA_0) then
int_d_i(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_d_i(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_d_o <= (others => '0');
elsif (ACLK_EN = '1') then
if (d_o_ap_vld = '1') then
int_d_o <= UNSIGNED(d_o); -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_d_o_ap_vld <= '0';
elsif (ACLK_EN = '1') then
if (d_o_ap_vld = '1') then
int_d_o_ap_vld <= '1';
elsif (ar_hs = '1' and raddr = ADDR_D_O_CTRL) then
int_d_o_ap_vld <= '0'; -- clear on read
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
end architecture behave;
| mit | 25ddacc1d8eb4362c28b7bb6db720bbc | 0.429671 | 3.826098 | false | false | false | false |
natsutan/NPU | fpga_implement/npu8/npu8.srcs/sources_1/ip/mult_gen_0/sim/mult_gen_0.vhd | 1 | 4,811 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:mult_gen:12.0
-- IP Revision: 12
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY mult_gen_v12_0_12;
USE mult_gen_v12_0_12.mult_gen_v12_0_12;
ENTITY mult_gen_0 IS
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
P : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END mult_gen_0;
ARCHITECTURE mult_gen_0_arch OF mult_gen_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF mult_gen_0_arch: ARCHITECTURE IS "yes";
COMPONENT mult_gen_v12_0_12 IS
GENERIC (
C_VERBOSITY : INTEGER;
C_MODEL_TYPE : INTEGER;
C_OPTIMIZE_GOAL : INTEGER;
C_XDEVICEFAMILY : STRING;
C_HAS_CE : INTEGER;
C_HAS_SCLR : INTEGER;
C_LATENCY : INTEGER;
C_A_WIDTH : INTEGER;
C_A_TYPE : INTEGER;
C_B_WIDTH : INTEGER;
C_B_TYPE : INTEGER;
C_OUT_HIGH : INTEGER;
C_OUT_LOW : INTEGER;
C_MULT_TYPE : INTEGER;
C_CE_OVERRIDES_SCLR : INTEGER;
C_CCM_IMP : INTEGER;
C_B_VALUE : STRING;
C_HAS_ZERO_DETECT : INTEGER;
C_ROUND_OUTPUT : INTEGER;
C_ROUND_PT : INTEGER
);
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
CE : IN STD_LOGIC;
SCLR : IN STD_LOGIC;
P : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT mult_gen_v12_0_12;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF A: SIGNAL IS "xilinx.com:signal:data:1.0 a_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF B: SIGNAL IS "xilinx.com:signal:data:1.0 b_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF P: SIGNAL IS "xilinx.com:signal:data:1.0 p_intf DATA";
BEGIN
U0 : mult_gen_v12_0_12
GENERIC MAP (
C_VERBOSITY => 0,
C_MODEL_TYPE => 0,
C_OPTIMIZE_GOAL => 1,
C_XDEVICEFAMILY => "kintexu",
C_HAS_CE => 0,
C_HAS_SCLR => 0,
C_LATENCY => 3,
C_A_WIDTH => 8,
C_A_TYPE => 1,
C_B_WIDTH => 16,
C_B_TYPE => 0,
C_OUT_HIGH => 23,
C_OUT_LOW => 8,
C_MULT_TYPE => 0,
C_CE_OVERRIDES_SCLR => 0,
C_CCM_IMP => 0,
C_B_VALUE => "10000001",
C_HAS_ZERO_DETECT => 0,
C_ROUND_OUTPUT => 0,
C_ROUND_PT => 0
)
PORT MAP (
CLK => CLK,
A => A,
B => B,
CE => '1',
SCLR => '0',
P => P
);
END mult_gen_0_arch;
| bsd-3-clause | 3c1a5c6c7e199477b55b72294133ee65 | 0.665142 | 3.568991 | false | false | false | false |
varunnagpaal/Digital-Hardware-Modelling | vhdl/filter/fir_picoblaze/top_testbench.vhdl | 1 | 2,072 | -- Author: Varun Nagpal
-- Net Id: vxn180010
-- Microprocessor Systems Project
-- December, 6th 2018
--
-- Design: Testbench for the Generic Nth order (L = N+1 taps) Transposed Direct-form FIR-filter
-- controlled using Xilinx Picoblaze processor and whose output is displayed on seven segment
-- display
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_signed.all;
use work.fir_filter_shared_package.all;
use work.ssg_display_shared_package.all;
entity top_testbench is
end top_testbench;
architecture top_test of top_testbench is
component top is
port (clk : in std_logic;
rst : in std_logic;
out_seg_p : out SEG_T;
out_dp_p : out std_logic;
out_digits_en_p : out DIGITS_EN_T
);
end component top;
-- clock and asynchronous reset
signal clk : std_logic := '0';
signal rst : std_logic := '1';
signal seg_sig : SEG_T := (others => DISABLE_SEG);
signal dp_out_sig : std_logic := DISABLE_DP;
signal digits_enable_sig : DIGITS_EN_T := (others => DISABLE_DIGIT);
begin
-- Create an instance of the FIR filter controlled
-- using Xilinx Picoblaze and whose output is displayed
-- using seven segment display
DUT: top
port map ( clk => clk,
rst => rst,
out_seg_p => seg_sig,
out_dp_p => dp_out_sig,
out_digits_en_p => digits_enable_sig
);
-- Clock generation
clk_gen: process
begin
clk <= '0';
wait for CLK_LOW_TIME;
clk <= '1';
wait for CLK_HIGH_TIME;
end process clk_gen;
-- Reset generation
rst <= '1',
'0' after CLK_CYCLE_TIME;
process
begin
wait for 100 * CLK_CYCLE_TIME;
end process;
-- print_messages: process begin
-- end process print_messages;
-- stop_sim: process begin
-- wait for 24*CLK_CYCLE_TIME;
-- std.env.stop;
-- end process stop_sim;
end architecture top_test;
| mit | e6a0860a42fee332e1cfbc1e4cb57e4e | 0.61583 | 2.977011 | false | true | false | false |
besm6/micro-besm | tests/2910/vhdl/funct_block_alg_beh/components/stack/stack.vhdl | 1 | 1,907 | --------------------------------------------------------------------------------
--
-- AMD 2910 Benchmark (Functional blocks) (Algorithmic Behaviour of Funct blocks)
--
-- Source: AMD data book
--
-- VHDL Benchmark author Indraneel Ghosh
-- University Of California, Irvine, CA 92717
--
-- Developed on Feb 19, 1992
--
-- Verification Information:
--
-- Verified By whom? Date Simulator
-- -------- ------------ -------- ------------
-- Syntax yes Champaka Ramachandran Sept17, 92 ZYCAD
-- Functionality yes Champaka Ramachandran Sept17, 92 ZYCAD
--------------------------------------------------------------------------------
--library ZYCAD;
use work.types.all;
use work.MVL7_functions.all;
use work.synthesis_types.all;
entity stack is
port (
clk : in clock;
pop : in MVL7;
push : in MVL7;
clear : in MVL7;
uPC : in MVL7_VECTOR(11 downto 0);
sp : inout INTEGER range 0 to 5;
reg_file : inout MEMORY_12_BIT(5 downto 0);
FULL_BAR : out MVL7
);
end stack;
architecture stack of stack is
begin
------------------------------------------------------------------------------
stack_and_sp : block ( (clk = '1') and (not clk'stable) )
signal write_address : INTEGER range 0 to 5;
begin
sp <= guarded (sp - 1) WHEN (pop = '1') and (sp /= 0) ELSE
(sp + 1) WHEN (push = '1') and (sp /= 5) ELSE
0 when clear = '1'ELSE
sp;
write_address <= sp + 1 WHEN (sp /= 5) ELSE --
sp;
reg_file(write_address) <= guarded uPC WHEN (push = '1') ELSE
reg_file(write_address);
FULL_BAR <= '0' WHEN sp = 5 ELSE
'1';
end block stack_and_sp;
------------------------------------------------------------------------------
end stack;
| mit | 7693a179e6320039b989183da5880103 | 0.445726 | 4.040254 | false | false | false | false |
varunnagpaal/Digital-Hardware-Modelling | tutorials/xilinx/hls/ug871-design-files/Using_IP_with_Zynq/lab1/hls_macc/vhls_prj/solution1/syn/vhdl/hls_macc_HLS_MACC_PERIPH_BUS_s_axi.vhd | 3 | 17,323 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity hls_macc_HLS_MACC_PERIPH_BUS_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 6;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
interrupt :out STD_LOGIC;
-- user signals
ap_start :out STD_LOGIC;
ap_done :in STD_LOGIC;
ap_ready :in STD_LOGIC;
ap_idle :in STD_LOGIC;
a :out STD_LOGIC_VECTOR(31 downto 0);
b :out STD_LOGIC_VECTOR(31 downto 0);
accum :in STD_LOGIC_VECTOR(31 downto 0);
accum_ap_vld :in STD_LOGIC;
accum_clr :out STD_LOGIC_VECTOR(0 downto 0)
);
end entity hls_macc_HLS_MACC_PERIPH_BUS_s_axi;
-- ------------------------Address Info-------------------
-- 0x00 : Control signals
-- bit 0 - ap_start (Read/Write/COH)
-- bit 1 - ap_done (Read/COR)
-- bit 2 - ap_idle (Read)
-- bit 3 - ap_ready (Read)
-- bit 7 - auto_restart (Read/Write)
-- others - reserved
-- 0x04 : Global Interrupt Enable Register
-- bit 0 - Global Interrupt Enable (Read/Write)
-- others - reserved
-- 0x08 : IP Interrupt Enable Register (Read/Write)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x0c : IP Interrupt Status Register (Read/TOW)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x10 : Data signal of a
-- bit 31~0 - a[31:0] (Read/Write)
-- 0x14 : reserved
-- 0x18 : Data signal of b
-- bit 31~0 - b[31:0] (Read/Write)
-- 0x1c : reserved
-- 0x20 : Data signal of accum
-- bit 31~0 - accum[31:0] (Read)
-- 0x24 : Control signal of accum
-- bit 0 - accum_ap_vld (Read/COR)
-- others - reserved
-- 0x28 : Data signal of accum_clr
-- bit 0 - accum_clr[0] (Read/Write)
-- others - reserved
-- 0x2c : reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of hls_macc_HLS_MACC_PERIPH_BUS_s_axi is
type states is (wridle, wrdata, wrresp, wrreset, rdidle, rddata, rdreset); -- read and write fsm states
signal wstate : states := wrreset;
signal rstate : states := rdreset;
signal wnext, rnext: states;
constant ADDR_AP_CTRL : INTEGER := 16#00#;
constant ADDR_GIE : INTEGER := 16#04#;
constant ADDR_IER : INTEGER := 16#08#;
constant ADDR_ISR : INTEGER := 16#0c#;
constant ADDR_A_DATA_0 : INTEGER := 16#10#;
constant ADDR_A_CTRL : INTEGER := 16#14#;
constant ADDR_B_DATA_0 : INTEGER := 16#18#;
constant ADDR_B_CTRL : INTEGER := 16#1c#;
constant ADDR_ACCUM_DATA_0 : INTEGER := 16#20#;
constant ADDR_ACCUM_CTRL : INTEGER := 16#24#;
constant ADDR_ACCUM_CLR_DATA_0 : INTEGER := 16#28#;
constant ADDR_ACCUM_CLR_CTRL : INTEGER := 16#2c#;
constant ADDR_BITS : INTEGER := 6;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_done : STD_LOGIC := '0';
signal int_ap_start : STD_LOGIC := '0';
signal int_auto_restart : STD_LOGIC := '0';
signal int_gie : STD_LOGIC := '0';
signal int_ier : UNSIGNED(1 downto 0) := (others => '0');
signal int_isr : UNSIGNED(1 downto 0) := (others => '0');
signal int_a : UNSIGNED(31 downto 0) := (others => '0');
signal int_b : UNSIGNED(31 downto 0) := (others => '0');
signal int_accum : UNSIGNED(31 downto 0) := (others => '0');
signal int_accum_ap_vld : STD_LOGIC;
signal int_accum_clr : UNSIGNED(0 downto 0) := (others => '0');
begin
-- ----------------------- Instantiation------------------
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wrreset;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdreset;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_AP_CTRL =>
rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
when ADDR_GIE =>
rdata_data <= (0 => int_gie, others => '0');
when ADDR_IER =>
rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
when ADDR_ISR =>
rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
when ADDR_A_DATA_0 =>
rdata_data <= RESIZE(int_a(31 downto 0), 32);
when ADDR_B_DATA_0 =>
rdata_data <= RESIZE(int_b(31 downto 0), 32);
when ADDR_ACCUM_DATA_0 =>
rdata_data <= RESIZE(int_accum(31 downto 0), 32);
when ADDR_ACCUM_CTRL =>
rdata_data <= (0 => int_accum_ap_vld, others => '0');
when ADDR_ACCUM_CLR_DATA_0 =>
rdata_data <= RESIZE(int_accum_clr(0 downto 0), 32);
when others =>
rdata_data <= (others => '0');
end case;
end if;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
interrupt <= int_gie and (int_isr(0) or int_isr(1));
ap_start <= int_ap_start;
a <= STD_LOGIC_VECTOR(int_a);
b <= STD_LOGIC_VECTOR(int_b);
accum_clr <= STD_LOGIC_VECTOR(int_accum_clr);
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_start <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_ap_start <= '1';
elsif (ap_ready = '1') then
int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_done <= '0';
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_done <= '1';
elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
int_ap_done <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_idle <= '0';
elsif (ACLK_EN = '1') then
if (true) then
int_ap_idle <= ap_idle;
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_ready <= '0';
elsif (ACLK_EN = '1') then
if (true) then
int_ap_ready <= ap_ready;
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_auto_restart <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
int_auto_restart <= WDATA(7);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_gie <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
int_gie <= WDATA(0);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ier <= "00";
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
int_ier <= UNSIGNED(WDATA(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(0) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(0) = '1' and ap_done = '1') then
int_isr(0) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(1) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(1) = '1' and ap_ready = '1') then
int_isr(1) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_A_DATA_0) then
int_a(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_a(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_B_DATA_0) then
int_b(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_b(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_accum <= (others => '0');
elsif (ACLK_EN = '1') then
if (accum_ap_vld = '1') then
int_accum <= UNSIGNED(accum); -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_accum_ap_vld <= '0';
elsif (ACLK_EN = '1') then
if (accum_ap_vld = '1') then
int_accum_ap_vld <= '1';
elsif (ar_hs = '1' and raddr = ADDR_ACCUM_CTRL) then
int_accum_ap_vld <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_ACCUM_CLR_DATA_0) then
int_accum_clr(0 downto 0) <= (UNSIGNED(WDATA(0 downto 0)) and wmask(0 downto 0)) or ((not wmask(0 downto 0)) and int_accum_clr(0 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
end architecture behave;
| mit | 371773e51eb55f95f95533903e0f2cf3 | 0.437049 | 3.8487 | false | false | false | false |
varunnagpaal/Digital-Hardware-Modelling | vhdl/filter/fir_picoblaze/fir_filter_shared_package.vhdl | 1 | 3,058 | -- Author: Varun Nagpal
-- Net Id: vxn180010
-- Microprocessor Systems Project
-- December, 6th 2018
--
-- Package: Modifiable Paramaters, non-modifiable constants and types (ports)
-- for the Generic Nth order (L = N+1 taps) Transposed Direct-form FIR-filter
--
-- Modifiable variables for Design of the FIR Filter:
-- FIR_ORDER = order of the filter (N). Note L = N+1 = taps
-- X_BIT_SIZE = bit width (n) of input samples (signed 2's complement)
-- H_BIT_SIZE = bit width (m) of coefficients (signed 2's complement)
--
-- Modifiable variables for testbench of the FIR Filter:
-- CLK_CYCLE_TIME = clock cycle time
-- CLK_HIGH_TIME = time for which clock is high
--
-- All remaining parameters in the package are non-modifiable constants which
-- must not be modified manually as there values are calculated during using values
-- of modifiable variables during compilation of VHDL files
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use ieee.std_logic_unsigned.all;
package fir_filter_shared_package is
-- modifiable variables for design of FIR filter
constant FIR_ORDER : natural := 26; -- order of the filter (N). Note L = N+1 = taps
constant X_BIT_SIZE : natural := 8; -- bit width (n) of input samples (signed 2's complement)
constant H_BIT_SIZE : natural := 8; -- bit width (m) of coefficients (signed 2's complement)
-- modifiable variables for testbench of FIR filter (uncomment if simulating filter in isolation)
--constant CLK_CYCLE_TIME : time := 10 ns;
--constant CLK_HIGH_TIME : time := 5 ns;
-- modifiable constants for testbench of FIR filter (uncomment if simulating filter in isolation)
--constant CLK_LOW_TIME : time := CLK_CYCLE_TIME - CLK_HIGH_TIME;
-- non-modifiable constants
constant MULT_BIT_SIZE : natural := X_BIT_SIZE+H_BIT_SIZE; -- bit width (n+m) of signed multiplier
constant EXTR_BIT_SIZE : natural := natural(ceil(log2(real(FIR_ORDER+1))))-1; -- extra bits for accumulation = ceil(log2(L))-1
constant Y_BIT_SIZE : natural := MULT_BIT_SIZE+EXTR_BIT_SIZE; -- bit width of output samples (signed 2's complement) or signed adder
-- N = no. of register delays or additions
subtype ADD_REG_TYPE is signed(Y_BIT_SIZE-1 downto 0);
type ADD_REG_ARRAY is array (0 to FIR_ORDER) of ADD_REG_TYPE;
-- L = N+1 no. of taps or coefficients or multiplications
subtype MULT_SIG_TYPE is signed(MULT_BIT_SIZE-1 downto 0);
type MULT_SIG_ARRAY is array (0 to FIR_ORDER) of MULT_SIG_TYPE;
subtype COEFF_REG_TYPE is signed(H_BIT_SIZE-1 downto 0);
type COEFF_REG_ARRAY is array (0 to FIR_ORDER) of COEFF_REG_TYPE;
end fir_filter_shared_package;
package body fir_filter_shared_package is
-- empty
end fir_filter_shared_package; | mit | cb17a4c97e2f832ee5a73b7036f5af6d | 0.646174 | 3.640476 | false | false | false | false |
besm6/micro-besm | tests/2901/vhdl/funct_blocks_alg_beh/components/mem/test_vectors.vhdl | 1 | 7,654 | --------------------------------------------------------------------------------
--
-- AM2901 Benchmark -- mem test vectors
--
-- Source: AMD data book
--
-- VHDL Benchmark author Indraneel Ghosh
-- University Of California, Irvine, CA 92717
--
-- Developed on Jan 1, 1992
--
-- Verification Information:
--
-- Verified By whom? Date Simulator
-- -------- ------------ -------- ------------
-- Syntax yes Champaka Ramachandran Sept 17, 92 ZYCAD
-- Functionality yes Champaka Ramachandran Sept 17, 92 ZYCAD
--------------------------------------------------------------------------------
--library ZYCAD;
use work.TYPES.all;
use work.MVL7_functions.all;
use work.synthesis_types.all;
entity E is
end;
architecture A of E is
component mem_inst
port (
RAM : inout Memory(15 downto 0);
F : in MVL7_vector(3 downto 0);
clk : in clock;
I : in MVL7_vector(8 downto 0);
RAM0, RAM3 : in MVL7;
Aadd, Badd : in integer range 15 downto 0
);
end component;
signal RAM : Memory(15 downto 0);
signal F : MVL7_vector(3 downto 0);
signal clk : clock;
signal I : MVL7_vector(8 downto 0);
signal RAM0, RAM3 : MVL7;
signal Aadd, Badd : integer range 15 downto 0;
for all : mem_inst use entity work.mem(mem);
begin
mem_inst1 : mem_inst port map(
RAM,
F ,
clk,
I ,
RAM0, RAM3 ,
Aadd, Badd
);
process
begin
----------------------------------------------------------
F <= "0111"; --#1
I <= "010000000";
RAM0 <= 'Z';
RAM3 <= 'Z';
Aadd <= 0; -- Load F into RAM(Badd) where Badd = 0
Badd <= 0;
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
wait for 1 ns;
assert (RAM(Aadd) = "0111")
report
"Assert 1 : < RAM(Aadd) /= '0111'> "
severity warning;
assert(RAM(Badd) = "0111")
report
"Assert 2 : < RAM(Badd) /= '0111'> "
severity warning;
wait for 1 ns;
----------------------------------------------------------
F <= "1001"; --#2
I <= "011000000";
RAM0 <= 'Z';
RAM3 <= 'Z';
Aadd <= 0; -- Load F into RAM(Badd) where Badd = 1
Badd <= 1;
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
wait for 1 ns;
assert (RAM(Aadd) = "0111")
report
"Assert a1 : < RAM(Aadd) /= '0111'> "
severity warning;
assert(RAM(Badd) = "1001")
report
"Assert a2 : < RAM(Badd) /= '1001'> "
severity warning;
wait for 1 ns;
----------------------------------------------------------
F <= "0000"; --#3
I <= "000000000";
RAM0 <= 'Z';
RAM3 <= 'Z';
Aadd <= 1; -- Do nothing
Badd <= 0;
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
wait for 1 ns;
assert (RAM(Aadd) = "1001")
report
"Assert b1 : < RAM(Aadd) /= '1001'> "
severity warning;
assert(RAM(Badd) = "0111")
report
"Assert b2 : < RAM(Badd) /= '0111'> "
severity warning;
wait for 1 ns;
----------------------------------------------------------
F <= "1111"; --#4
I <= "001000000";
RAM0 <= 'Z';
RAM3 <= 'Z'; -- Do nothing
Aadd <= 0;
Badd <= 1;
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
wait for 1 ns;
assert (RAM(Aadd) = "0111")
report
"Assert c1 : < RAM(Aadd) /= '0111'> "
severity warning;
assert(RAM(Badd) = "1001")
report
"Assert c2 : < RAM(Badd) /= '1001'> "
severity warning;
wait for 1 ns;
----------------------------------------------------------
F <= "1001"; --#5
I <= "100000000";
RAM0 <= 'Z';
RAM3 <= '0';
Aadd <= 1; -- Down shift F and load that into RAM(Badd)
Badd <= 2; -- with input 0. Badd = 2.
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
wait for 1 ns;
assert (RAM(Aadd) = "1001")
report
"Assert d1 : < RAM(Aadd) /= '1001'> "
severity warning;
assert(RAM(Badd) = "0100")
report
"Assert d2 : < RAM(Badd) /= '0100'> "
severity warning;
wait for 1 ns;
----------------------------------------------------------
F <= "0111"; --#6
I <= "100000000";
RAM0 <= 'Z';
RAM3 <= '1';
Aadd <= 0; -- Down shift F and load that into RAM(Badd)
Badd <= 3; -- with input 1. Badd = 3
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
wait for 1 ns;
assert (RAM(Aadd) = "0111")
report
"Assert e1 : < RAM(Aadd) /= '0111'> "
severity warning;
assert(RAM(Badd) = "1011")
report
"Assert e2 : < RAM(Badd) /= '1011'> "
severity warning;
wait for 1 ns;
----------------------------------------------------------
F <= "1101"; --#7
I <= "101000000";
RAM0 <= 'Z';
RAM3 <= '0';
Aadd <= 2; -- Down shift F and load that into RAM(Badd)
Badd <= 4; -- with input 0. Badd = 4
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
wait for 1 ns;
assert (RAM(Aadd) = "0100")
report
"Assert f1 : < RAM(Aadd) /= '0100'> "
severity warning;
assert(RAM(Badd) = "0110")
report
"Assert f2 : < RAM(Badd) /= '0110'> "
severity warning;
wait for 1 ns;
----------------------------------------------------------
F <= "1101"; --#8
I <= "101000000";
RAM0 <= 'Z';
RAM3 <= '1'; -- Down shift F and load that into RAM(Badd)
Aadd <= 3; -- with input 1. Badd = 5
Badd <= 5;
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
wait for 1 ns;
assert (RAM(Aadd) = "1011")
report
"Assert g1 : < RAM(Aadd) /= '1011'> "
severity warning;
assert(RAM(Badd) = "1110")
report
"Assert g2 : < RAM(Badd) /= '1110'> "
severity warning;
wait for 1 ns;
----------------------------------------------------------
F <= "0110"; --#9
I <= "110000000";
RAM0 <= '0';
RAM3 <= 'Z'; -- Up shift F and load that into RAM(Badd)
Aadd <= 4; -- with input 0. Badd = 2
Badd <= 2;
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
wait for 1 ns;
assert (RAM(Aadd) = "0110")
report
"Assert h1 : < RAM(Aadd) /= '0110'> "
severity warning;
assert(RAM(Badd) = "1100")
report
"Assert h2 : < RAM(Badd) /= '1100'> "
severity warning;
wait for 1 ns;
----------------------------------------------------------
F <= "0000"; --#10
I <= "110000000";
RAM0 <= '1';
RAM3 <= 'Z'; -- Up shift F and load that into RAM(Badd)
Aadd <= 2; -- with input 1. Badd = 6
Badd <= 6;
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
wait for 1 ns;
assert (RAM(Aadd) = "1100")
report
"Assert i1 : < RAM(Aadd) /= '1100'> "
severity warning;
assert(RAM(Badd) = "0001")
report
"Assert i2 : < RAM(Badd) /= '0001'> "
severity warning;
wait for 1 ns;
----------------------------------------------------------
F <= "1101"; --#11
I <= "111000000";
RAM0 <= '0';
RAM3 <= 'Z';
Aadd <= 5; -- Up shift F and load that into RAM(Badd)
Badd <= 7; -- with input 0. Badd = 7
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
wait for 1 ns;
assert (RAM(Aadd) = "1110")
report
"Assert j1 : < RAM(Aadd) /= '1110'> "
severity warning;
assert(RAM(Badd) = "1010")
report
"Assert j2 : < RAM(Badd) /= '1010'> "
severity warning;
wait for 1 ns;
----------------------------------------------------------
F <= "0010"; --#12
I <= "111000000";
RAM0 <= '1';
RAM3 <= 'Z';
Aadd <= 6; -- Up shift F and load that into RAM(Badd)
Badd <= 8; -- with input 1. Badd = 8
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
wait for 1 ns;
assert (RAM(Aadd) = "0001")
report
"Assert k1 : < RAM(Aadd) /= '0001'> "
severity warning;
assert(RAM(Badd) = "0101")
report
"Assert k2 : < RAM(Badd) /= '0101'> "
severity warning;
wait for 1 ns;
----------------------------------------------------------
end process;
end A; | mit | 10d199bb83645641368fd1a22947350f | 0.469689 | 2.940453 | false | false | false | false |
MartinCura/SistDig-TP4 | sin_usar/Char_ROM.vhd | 1 | 5,378 | -----
-----
-- CHAR ROM COMO LO TENÍA EN EL TP2, USAR LO Q SIRVA
-----
-----
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
entity Char_ROM is
generic(
N: integer:= 6;
M: integer:= 3;
W: integer:= 8
);
port(
char_address: in std_logic_vector(5 downto 0);
font_row, font_col: in std_logic_vector(M-1 downto 0);
rom_out: out std_logic
);
end;
architecture p of Char_ROM is
subtype tipoLinea is std_logic_vector(0 to W-1);
type char is array(0 to W-1) of tipoLinea;
constant ESPACIO: char:= (
"00000000",
"00000000",
"00000000",
"00000000",
"00000000",
"00000000",
"00000000",
"00000000"
);
constant PUNTO: char:= (
"00000000",
"00000000",
"00000000",
"00000000",
"00000000",
"00011000",
"00011000",
"00000000"
);
constant V: char:= (
"00000000",
"01100110",
"01100110",
"01100110",
"01100110",
"00111100",
"00011000",
"00000000"
);
constant CERO: char:= (
"00111100",
"01100110",
"01100110",
"01100110",
"01100110",
"01100110",
"00111100",
"00000000"
);
constant UNO: char:= (
"00011000",
"00011000",
"00011000",
"00011000",
"00011000",
"00011000",
"00011000",
"00000000"
);
constant DOS: char:= (
"00111110",
"01100011",
"01100110",
"00001100",
"00011000",
"00110000",
"01111110",
"00000000"
);
constant TRES: char:= (
"01111100",
"00000110",
"00000110",
"00111100",
"00000110",
"00000110",
"01111100",
"00000000"
);
constant CUATRO: char:= (
"01100110",
"01100110",
"01100110",
"01111110",
"00000110",
"00000110",
"00000110",
"00000000"
);
constant CINCO: char:= (
"01111110",
"01100000",
"01100000",
"01111100",
"00000110",
"00000110",
"01111100",
"00000000"
);
constant SEIS: char:= (
"00111100",
"01100010",
"01100000",
"01111100",
"01100110",
"01100110",
"00111100",
"00000000"
);
constant SIETE: char:= (
"01111110",
"00000110",
"00000110",
"00000110",
"00000110",
"00000110",
"00000110",
"00000000"
);
constant OCHO: char:= (
"01111110",
"01100110",
"01100110",
"00111100",
"01100110",
"01100110",
"01111110",
"00000000"
);
constant NUEVE: char:= (
"00111100",
"01100110",
"01100110",
"00111110",
"00000110",
"01000110",
"00111100",
"00000000"
);
constant Err: char:= (
"01111110",
"01100000",
"01100000",
"01111000",
"01100000",
"01100000",
"01111110",
"00000000"
);
type memo is array(0 to 255) of tipoLinea;
signal RAM: memo:= (
0 => CERO(0), 1 => CERO(1), 2 => CERO(2), 3 => CERO(3), 4 => CERO(4), 5 => CERO(5), 6 => CERO(6), 7 => CERO(7), -- 0
8 => UNO(0), 9 => UNO(1), 10 => UNO(2), 11 => UNO(3), 12 => UNO(4), 13 => UNO(5), 14 => UNO(6), 15 => UNO(7), -- 1
16 => DOS(0), 17 => DOS(1), 18 => DOS(2), 19 => DOS(3), 20 => DOS(4), 21 => DOS(5), 22 => DOS(6), 23 => DOS(7), -- 2
24 => TRES(0), 25 => TRES(1), 26 => TRES(2), 27 => TRES(3), 28 => TRES(4), 29 => TRES(5), 30 => TRES(6), 31 => TRES(7), -- 3
32 => CUATRO(0), 33 => CUATRO(1), 34 => CUATRO(2), 35 => CUATRO(3), 36 => CUATRO(4), 37 => CUATRO(5), 38 => CUATRO(6), 39 => CUATRO(7), -- 4
40 => CINCO(0), 41 => CINCO(1), 42 => CINCO(2), 43 => CINCO(3), 44 => CINCO(4), 45 => CINCO(5), 46 => CINCO(6), 47 => CINCO(7), -- 5
48 => SEIS(0), 49 => SEIS(1), 50 => SEIS(2), 51 => SEIS(3), 52 => SEIS(4), 53 => SEIS(5), 54 => SEIS(6), 55 => SEIS(7), -- 6
56 => SIETE(0), 57 => SIETE(1), 58 => SIETE(2), 59 => SIETE(3), 60 => SIETE(4), 61 => SIETE(5), 62 => SIETE(6), 63 => SIETE(7), -- 7
64 => OCHO(0), 65 => OCHO(1), 66 => OCHO(2), 67 => OCHO(3), 68 => OCHO(4), 69 => OCHO(5), 70 => OCHO(6), 71 => OCHO(7), --8
72 => NUEVE(0), 73 => NUEVE(1), 74 => NUEVE(2), 75 => NUEVE(3), 76 => NUEVE(4), 77 => NUEVE(5), 78 => NUEVE(6), 79 => NUEVE(7), -- 9
80 => V(0), 81 => V(1), 82 => V(2), 83 => V(3), 84 => V(4), 85 => V(5), 86 => V(6), 87 => V(7), -- 10
88 => ESPACIO(0), 89 => ESPACIO(1), 90 => ESPACIO(2), 91 => ESPACIO(3), 92 => ESPACIO(4), 93 => ESPACIO(5), 94 => ESPACIO(6), 95 => ESPACIO(7), -- 11
96 => PUNTO(0), 97 => PUNTO(1), 98 => PUNTO(2), 99 => PUNTO(3), 100 => PUNTO(4), 101 => PUNTO(5), 102 => PUNTO(6), 103 => PUNTO(7), -- 12
104 to 247 => "00000000",
248 => Err(0), 249 => Err(1), 250 => Err(2), 251 => Err(3), 252 => Err(4), 253 => Err(5), 254 => Err(6), 255 => Err(7) -- 31
);
signal char_addr_aux: std_logic_vector(8 downto 0);
begin
char_addr_aux <= char_address & font_row;
rom_out <= RAM(to_integer(unsigned(char_addr_aux)))(to_integer(unsigned(font_col)));
end;
| gpl-3.0 | e00f4985fa99a05672adaf50db09ab4c | 0.460852 | 2.843469 | false | false | false | false |
MartinCura/SistDig-TP4 | src/comps/ffd.vhd | 1 | 426 | library IEEE;
use IEEE.std_logic_1164.all;
entity ffd is
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
d: in std_logic;
q: out std_logic := '0'
);
end ffd;
architecture ffd_arq of ffd is
begin
process(clk, rst)
begin
if rst = '1' then
q <= '0';
elsif rising_edge(clk) then
if ena = '1' then
q <= d;
end if;
end if;
end process;
end ffd_arq;
| gpl-3.0 | 12fc42b84600b40bf78f2a51672cdd1e | 0.56338 | 2.535714 | false | false | false | false |
MartinCura/SistDig-TP4 | old/rotador/gen_dirs.vhd | 1 | 1,069 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.cordic_lib.all;
---use work.float_pkg.all;
--library ieee_proposed;
--use ieee_proposed.float_pkg.all;
library floatfixlib;
use floatfixlib.float_pkg.all;
-- A partir de una posición 2D (x,y) mapea a una dirección de pantalla (i,j)
entity gen_dirs is
generic(
-- Bits por fila/columna
BR : integer := 10; -- n_bits_row
BC : integer := 10 -- n_bits_col
);
port(
pos_2d: in t_vec; -- Posición 2D
dir: out t_dir -- Dirección en pantalla de píxel correspondiente
);
end entity;
architecture gen_dirs_arq of gen_dirs is
constant SCR_W : integer := 640;
constant SCR_H : integer := 480;
constant SIZE : integer := 160;
begin
process(pos_2d)
variable x, y : integer := 0;
begin
x := SCR_W / 2 + to_integer( SIZE * pos_2d(1) );
y := SCR_H / 2 + to_integer( SIZE * pos_2d(2) );
---dir := x + SCR_W * y;
dir(1) <= std_logic_vector(to_unsigned(x, BR));
dir(2) <= std_logic_vector(to_unsigned(y, BC));
end process;
end;
| gpl-3.0 | 7014eae6fed4d9e42f6aac89f713961d | 0.638158 | 2.62716 | false | false | false | false |
Feuerwerk/fpgaNES | i2s.vhd | 1 | 5,939 | /*
This file is part of fpgaNES.
fpgaNES is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
fpgaNES is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with fpgaNES. If not, see <http://www.gnu.org/licenses/>.
*/
-- this component will output a left aligned 16 bit audio sample with 44.1 kHz over an I2S connection
-- while SCLK and MCLK is driven by its own clock the audio sample itself comes from the master clock domain
-- and has to be synched with the audio clock
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity i2s is
generic
(
DIVIDER : natural := 4;
WORD_WIDTH : natural := 16;
CHANNEL_WIDTH : natural := 32
);
port
(
i_audio_clk : in std_logic;
i_master_clk : in std_logic;
i_clk_enable : in std_logic;
i_audio_reset_n : in std_logic := '1';
i_master_reset_n : in std_logic := '1';
i_data : in std_logic_vector(WORD_WIDTH - 1 downto 0);
o_lrclk : out std_logic;
o_sclk : out std_logic;
o_sdata : out std_logic
);
end i2s;
architecture behavioral of i2s is
component biquad is
generic
(
B0 : std_logic_vector(31 downto 0);
B1 : std_logic_vector(31 downto 0);
B2 : std_logic_vector(31 downto 0);
A1 : std_logic_vector(31 downto 0);
A2 : std_logic_vector(31 downto 0)
);
port
(
i_clk : in std_logic;
i_reset_n : in std_logic := '1';
i_sample_trig : in std_logic;
i_x : in std_logic_vector(17 downto 0);
o_filter_done : out std_logic;
o_q : out std_logic_vector(17 downto 0)
);
end component;
constant HALF_DIVIDER : natural := DIVIDER / 2;
signal s_clk_divider : natural range 0 to DIVIDER - 1 := 0;
signal s_sdata : std_logic;
signal s_sclk : std_logic := '0';
signal s_buffer : std_logic_vector(WORD_WIDTH - 1 downto 0) := (others => '0');
signal s_data : std_logic_vector(WORD_WIDTH - 1 downto 0) := (others => '0');
signal s_bit_index : natural range 0 to CHANNEL_WIDTH - 1 := 0;
signal s_lrclk : std_logic := '1';
signal s_sclk_sync : std_logic_vector(1 downto 0) := "00";
signal s_falling_sclk : std_logic;
signal s_sample_last : std_logic;
signal s_bq_low_done : std_logic;
signal s_bq_high90_done : std_logic;
signal s_bq_high440_done : std_logic;
signal s_bq_high90_q : std_logic_vector(17 downto 0);
signal s_bq_high440_q : std_logic_vector(17 downto 0);
signal s_bq_low_q : std_logic_vector(17 downto 0);
begin
-- Low-Pass 1st Order: fs= 44.1kHz, fc = 14.0 kHz
bq_low : biquad generic map
(
B0 => B"00_10_0110_1110_0010_1001_1111_0111_0101", -- 0.607581963
B1 => B"00_10_0110_1110_0010_1001_1111_0111_0101", -- 0.607581963
B2 => B"00_00_0000_0000_0000_0000_0000_0000_0000", -- 0.0
A1 => B"00_00_1101_1100_0101_0011_1110_1110_1010", -- 0.215163926
A2 => B"00_00_0000_0000_0000_0000_0000_0000_0000" -- 0.0
)
port map
(
i_clk => i_master_clk,
i_sample_trig => s_falling_sclk and s_sample_last,
i_reset_n => i_master_reset_n,
i_x => "00" & i_data,
o_filter_done => s_bq_low_done,
o_q => s_bq_low_q
);
-- High-Pass 1st Order: fs= 44.1kHz, fc = 440 Hz
bq_high440 : biquad generic map
(
B0 => B"00_11_1110_0000_1101_1110_0101_1111_1001", -- 0.969598287
B1 => B"11_00_0001_1111_0010_0001_1010_0000_0111", -- -0.969598287
B2 => B"00_00_0000_0000_0000_0000_0000_0000_0000", -- 0.0
A1 => B"11_00_0011_1110_0100_0011_0100_0000_1111", -- -0,939196573
A2 => B"00_00_0000_0000_0000_0000_0000_0000_0000" -- 0.0
)
port map
(
i_clk => i_master_clk,
i_sample_trig => s_bq_low_done,
i_reset_n => i_master_reset_n,
i_x => s_bq_low_q,
o_filter_done => s_bq_high440_done,
o_q => s_bq_high440_q
);
-- High-Pass 1st Order: fs= 44.1kHz, fc = 90 Hz
bq_high90 : biquad generic map
(
B0 => B"00_11_1111_1001_0111_1001_1111_1000_1000", -- 0.993629344
B1 => B"11_00_0000_0110_1000_0110_0000_0111_1000", -- -0.993629344
B2 => B"00_00_0000_0000_0000_0000_0000_0000_0000", -- 0.0
A1 => B"11_00_0000_1101_0000_1100_0000_1111_0000", -- -0.987258688
A2 => B"00_00_0000_0000_0000_0000_0000_0000_0000" -- 0.0
)
port map
(
i_clk => i_master_clk,
i_sample_trig => s_bq_high440_done,
i_reset_n => i_master_reset_n,
i_x => s_bq_high440_q,
o_filter_done => s_bq_high90_done,
o_q => s_bq_high90_q
);
-- Clock Divider
process (i_audio_clk)
begin
if rising_edge(i_audio_clk) then
if i_audio_reset_n = '0' then
s_clk_divider <= 0;
s_sclk <= '0';
else
if s_clk_divider = DIVIDER - 1 then
s_clk_divider <= 0;
else
s_clk_divider <= s_clk_divider + 1;
end if;
if s_clk_divider = DIVIDER - 1 then
s_sclk <= '1';
elsif s_clk_divider = HALF_DIVIDER - 1 then
s_sclk <= '0';
end if;
end if;
end if;
end process;
-- Bit-Stream
process (i_master_clk)
begin
if rising_edge(i_master_clk) then
if s_bq_low_done = '1' then
s_data <= s_bq_low_q(15 downto 0);
end if;
if s_falling_sclk = '1' then
if s_sample_last = '1' then
s_bit_index <= 0;
s_lrclk <= not s_lrclk;
s_buffer <= s_data;
else
s_bit_index <= s_bit_index + 1;
s_buffer <= s_buffer(WORD_WIDTH - 2 downto 0) & '0';
end if;
end if;
s_sclk_sync <= s_sclk_sync(0) & s_sclk; -- SCLK Synchronization Chain
end if;
end process;
s_falling_sclk <= s_sclk_sync(1) and not s_sclk_sync(0); -- SCLK falling edge
s_sample_last <= '1' when s_bit_index = CHANNEL_WIDTH - 1 else '0';
o_lrclk <= s_lrclk;
o_sclk <= s_sclk;
o_sdata <= s_buffer(WORD_WIDTH - 1);
end behavioral;
| gpl-3.0 | 69a90f7b369374451613907b2b03a99f | 0.634282 | 2.541292 | false | false | false | false |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/snickerdoodle_try/snickerdoodle_try.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_sim_netlist.vhdl | 1 | 198,671 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.4.1 (win64) Build 2117270 Tue Jan 30 15:32:00 MST 2018
-- Date : Thu Apr 5 01:27:52 2018
-- Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim
-- d:/github/Digital-Hardware-Modelling/xilinx-vivado/snickerdoodle_try/snickerdoodle_try.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_sim_netlist.vhdl
-- Design : design_1_processing_system7_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg400-3
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 is
port (
CAN0_PHY_TX : out STD_LOGIC;
CAN0_PHY_RX : in STD_LOGIC;
CAN1_PHY_TX : out STD_LOGIC;
CAN1_PHY_RX : in STD_LOGIC;
ENET0_GMII_TX_EN : out STD_LOGIC;
ENET0_GMII_TX_ER : out STD_LOGIC;
ENET0_MDIO_MDC : out STD_LOGIC;
ENET0_MDIO_O : out STD_LOGIC;
ENET0_MDIO_T : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET0_SOF_RX : out STD_LOGIC;
ENET0_SOF_TX : out STD_LOGIC;
ENET0_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET0_GMII_COL : in STD_LOGIC;
ENET0_GMII_CRS : in STD_LOGIC;
ENET0_GMII_RX_CLK : in STD_LOGIC;
ENET0_GMII_RX_DV : in STD_LOGIC;
ENET0_GMII_RX_ER : in STD_LOGIC;
ENET0_GMII_TX_CLK : in STD_LOGIC;
ENET0_MDIO_I : in STD_LOGIC;
ENET0_EXT_INTIN : in STD_LOGIC;
ENET0_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_TX_EN : out STD_LOGIC;
ENET1_GMII_TX_ER : out STD_LOGIC;
ENET1_MDIO_MDC : out STD_LOGIC;
ENET1_MDIO_O : out STD_LOGIC;
ENET1_MDIO_T : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET1_SOF_RX : out STD_LOGIC;
ENET1_SOF_TX : out STD_LOGIC;
ENET1_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_COL : in STD_LOGIC;
ENET1_GMII_CRS : in STD_LOGIC;
ENET1_GMII_RX_CLK : in STD_LOGIC;
ENET1_GMII_RX_DV : in STD_LOGIC;
ENET1_GMII_RX_ER : in STD_LOGIC;
ENET1_GMII_TX_CLK : in STD_LOGIC;
ENET1_MDIO_I : in STD_LOGIC;
ENET1_EXT_INTIN : in STD_LOGIC;
ENET1_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
GPIO_I : in STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_O : out STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_T : out STD_LOGIC_VECTOR ( 63 downto 0 );
I2C0_SDA_I : in STD_LOGIC;
I2C0_SDA_O : out STD_LOGIC;
I2C0_SDA_T : out STD_LOGIC;
I2C0_SCL_I : in STD_LOGIC;
I2C0_SCL_O : out STD_LOGIC;
I2C0_SCL_T : out STD_LOGIC;
I2C1_SDA_I : in STD_LOGIC;
I2C1_SDA_O : out STD_LOGIC;
I2C1_SDA_T : out STD_LOGIC;
I2C1_SCL_I : in STD_LOGIC;
I2C1_SCL_O : out STD_LOGIC;
I2C1_SCL_T : out STD_LOGIC;
PJTAG_TCK : in STD_LOGIC;
PJTAG_TMS : in STD_LOGIC;
PJTAG_TDI : in STD_LOGIC;
PJTAG_TDO : out STD_LOGIC;
SDIO0_CLK : out STD_LOGIC;
SDIO0_CLK_FB : in STD_LOGIC;
SDIO0_CMD_O : out STD_LOGIC;
SDIO0_CMD_I : in STD_LOGIC;
SDIO0_CMD_T : out STD_LOGIC;
SDIO0_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_LED : out STD_LOGIC;
SDIO0_CDN : in STD_LOGIC;
SDIO0_WP : in STD_LOGIC;
SDIO0_BUSPOW : out STD_LOGIC;
SDIO0_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SDIO1_CLK : out STD_LOGIC;
SDIO1_CLK_FB : in STD_LOGIC;
SDIO1_CMD_O : out STD_LOGIC;
SDIO1_CMD_I : in STD_LOGIC;
SDIO1_CMD_T : out STD_LOGIC;
SDIO1_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_LED : out STD_LOGIC;
SDIO1_CDN : in STD_LOGIC;
SDIO1_WP : in STD_LOGIC;
SDIO1_BUSPOW : out STD_LOGIC;
SDIO1_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SPI0_SCLK_I : in STD_LOGIC;
SPI0_SCLK_O : out STD_LOGIC;
SPI0_SCLK_T : out STD_LOGIC;
SPI0_MOSI_I : in STD_LOGIC;
SPI0_MOSI_O : out STD_LOGIC;
SPI0_MOSI_T : out STD_LOGIC;
SPI0_MISO_I : in STD_LOGIC;
SPI0_MISO_O : out STD_LOGIC;
SPI0_MISO_T : out STD_LOGIC;
SPI0_SS_I : in STD_LOGIC;
SPI0_SS_O : out STD_LOGIC;
SPI0_SS1_O : out STD_LOGIC;
SPI0_SS2_O : out STD_LOGIC;
SPI0_SS_T : out STD_LOGIC;
SPI1_SCLK_I : in STD_LOGIC;
SPI1_SCLK_O : out STD_LOGIC;
SPI1_SCLK_T : out STD_LOGIC;
SPI1_MOSI_I : in STD_LOGIC;
SPI1_MOSI_O : out STD_LOGIC;
SPI1_MOSI_T : out STD_LOGIC;
SPI1_MISO_I : in STD_LOGIC;
SPI1_MISO_O : out STD_LOGIC;
SPI1_MISO_T : out STD_LOGIC;
SPI1_SS_I : in STD_LOGIC;
SPI1_SS_O : out STD_LOGIC;
SPI1_SS1_O : out STD_LOGIC;
SPI1_SS2_O : out STD_LOGIC;
SPI1_SS_T : out STD_LOGIC;
UART0_DTRN : out STD_LOGIC;
UART0_RTSN : out STD_LOGIC;
UART0_TX : out STD_LOGIC;
UART0_CTSN : in STD_LOGIC;
UART0_DCDN : in STD_LOGIC;
UART0_DSRN : in STD_LOGIC;
UART0_RIN : in STD_LOGIC;
UART0_RX : in STD_LOGIC;
UART1_DTRN : out STD_LOGIC;
UART1_RTSN : out STD_LOGIC;
UART1_TX : out STD_LOGIC;
UART1_CTSN : in STD_LOGIC;
UART1_DCDN : in STD_LOGIC;
UART1_DSRN : in STD_LOGIC;
UART1_RIN : in STD_LOGIC;
UART1_RX : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
TTC0_CLK0_IN : in STD_LOGIC;
TTC0_CLK1_IN : in STD_LOGIC;
TTC0_CLK2_IN : in STD_LOGIC;
TTC1_WAVE0_OUT : out STD_LOGIC;
TTC1_WAVE1_OUT : out STD_LOGIC;
TTC1_WAVE2_OUT : out STD_LOGIC;
TTC1_CLK0_IN : in STD_LOGIC;
TTC1_CLK1_IN : in STD_LOGIC;
TTC1_CLK2_IN : in STD_LOGIC;
WDT_CLK_IN : in STD_LOGIC;
WDT_RST_OUT : out STD_LOGIC;
TRACE_CLK : in STD_LOGIC;
TRACE_CTL : out STD_LOGIC;
TRACE_DATA : out STD_LOGIC_VECTOR ( 1 downto 0 );
TRACE_CLK_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
USB1_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB1_VBUS_PWRSELECT : out STD_LOGIC;
USB1_VBUS_PWRFAULT : in STD_LOGIC;
SRAM_INTIN : in STD_LOGIC;
M_AXI_GP0_ARESETN : out STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARESETN : out STD_LOGIC;
M_AXI_GP1_ARVALID : out STD_LOGIC;
M_AXI_GP1_AWVALID : out STD_LOGIC;
M_AXI_GP1_BREADY : out STD_LOGIC;
M_AXI_GP1_RREADY : out STD_LOGIC;
M_AXI_GP1_WLAST : out STD_LOGIC;
M_AXI_GP1_WVALID : out STD_LOGIC;
M_AXI_GP1_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ACLK : in STD_LOGIC;
M_AXI_GP1_ARREADY : in STD_LOGIC;
M_AXI_GP1_AWREADY : in STD_LOGIC;
M_AXI_GP1_BVALID : in STD_LOGIC;
M_AXI_GP1_RLAST : in STD_LOGIC;
M_AXI_GP1_RVALID : in STD_LOGIC;
M_AXI_GP1_WREADY : in STD_LOGIC;
M_AXI_GP1_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARESETN : out STD_LOGIC;
S_AXI_GP0_ARREADY : out STD_LOGIC;
S_AXI_GP0_AWREADY : out STD_LOGIC;
S_AXI_GP0_BVALID : out STD_LOGIC;
S_AXI_GP0_RLAST : out STD_LOGIC;
S_AXI_GP0_RVALID : out STD_LOGIC;
S_AXI_GP0_WREADY : out STD_LOGIC;
S_AXI_GP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_ACLK : in STD_LOGIC;
S_AXI_GP0_ARVALID : in STD_LOGIC;
S_AXI_GP0_AWVALID : in STD_LOGIC;
S_AXI_GP0_BREADY : in STD_LOGIC;
S_AXI_GP0_RREADY : in STD_LOGIC;
S_AXI_GP0_WLAST : in STD_LOGIC;
S_AXI_GP0_WVALID : in STD_LOGIC;
S_AXI_GP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ARESETN : out STD_LOGIC;
S_AXI_GP1_ARREADY : out STD_LOGIC;
S_AXI_GP1_AWREADY : out STD_LOGIC;
S_AXI_GP1_BVALID : out STD_LOGIC;
S_AXI_GP1_RLAST : out STD_LOGIC;
S_AXI_GP1_RVALID : out STD_LOGIC;
S_AXI_GP1_WREADY : out STD_LOGIC;
S_AXI_GP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ACLK : in STD_LOGIC;
S_AXI_GP1_ARVALID : in STD_LOGIC;
S_AXI_GP1_AWVALID : in STD_LOGIC;
S_AXI_GP1_BREADY : in STD_LOGIC;
S_AXI_GP1_RREADY : in STD_LOGIC;
S_AXI_GP1_WLAST : in STD_LOGIC;
S_AXI_GP1_WVALID : in STD_LOGIC;
S_AXI_GP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_ACP_ARESETN : out STD_LOGIC;
S_AXI_ACP_ARREADY : out STD_LOGIC;
S_AXI_ACP_AWREADY : out STD_LOGIC;
S_AXI_ACP_BVALID : out STD_LOGIC;
S_AXI_ACP_RLAST : out STD_LOGIC;
S_AXI_ACP_RVALID : out STD_LOGIC;
S_AXI_ACP_WREADY : out STD_LOGIC;
S_AXI_ACP_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_BID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_ACLK : in STD_LOGIC;
S_AXI_ACP_ARVALID : in STD_LOGIC;
S_AXI_ACP_AWVALID : in STD_LOGIC;
S_AXI_ACP_BREADY : in STD_LOGIC;
S_AXI_ACP_RREADY : in STD_LOGIC;
S_AXI_ACP_WLAST : in STD_LOGIC;
S_AXI_ACP_WVALID : in STD_LOGIC;
S_AXI_ACP_ARID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_WID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_AWUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_ARESETN : out STD_LOGIC;
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_ARESETN : out STD_LOGIC;
S_AXI_HP1_ARREADY : out STD_LOGIC;
S_AXI_HP1_AWREADY : out STD_LOGIC;
S_AXI_HP1_BVALID : out STD_LOGIC;
S_AXI_HP1_RLAST : out STD_LOGIC;
S_AXI_HP1_RVALID : out STD_LOGIC;
S_AXI_HP1_WREADY : out STD_LOGIC;
S_AXI_HP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_ACLK : in STD_LOGIC;
S_AXI_HP1_ARVALID : in STD_LOGIC;
S_AXI_HP1_AWVALID : in STD_LOGIC;
S_AXI_HP1_BREADY : in STD_LOGIC;
S_AXI_HP1_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_RREADY : in STD_LOGIC;
S_AXI_HP1_WLAST : in STD_LOGIC;
S_AXI_HP1_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_WVALID : in STD_LOGIC;
S_AXI_HP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_ARESETN : out STD_LOGIC;
S_AXI_HP2_ARREADY : out STD_LOGIC;
S_AXI_HP2_AWREADY : out STD_LOGIC;
S_AXI_HP2_BVALID : out STD_LOGIC;
S_AXI_HP2_RLAST : out STD_LOGIC;
S_AXI_HP2_RVALID : out STD_LOGIC;
S_AXI_HP2_WREADY : out STD_LOGIC;
S_AXI_HP2_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_ACLK : in STD_LOGIC;
S_AXI_HP2_ARVALID : in STD_LOGIC;
S_AXI_HP2_AWVALID : in STD_LOGIC;
S_AXI_HP2_BREADY : in STD_LOGIC;
S_AXI_HP2_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_RREADY : in STD_LOGIC;
S_AXI_HP2_WLAST : in STD_LOGIC;
S_AXI_HP2_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_WVALID : in STD_LOGIC;
S_AXI_HP2_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_ARESETN : out STD_LOGIC;
S_AXI_HP3_ARREADY : out STD_LOGIC;
S_AXI_HP3_AWREADY : out STD_LOGIC;
S_AXI_HP3_BVALID : out STD_LOGIC;
S_AXI_HP3_RLAST : out STD_LOGIC;
S_AXI_HP3_RVALID : out STD_LOGIC;
S_AXI_HP3_WREADY : out STD_LOGIC;
S_AXI_HP3_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_ACLK : in STD_LOGIC;
S_AXI_HP3_ARVALID : in STD_LOGIC;
S_AXI_HP3_AWVALID : in STD_LOGIC;
S_AXI_HP3_BREADY : in STD_LOGIC;
S_AXI_HP3_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_RREADY : in STD_LOGIC;
S_AXI_HP3_WLAST : in STD_LOGIC;
S_AXI_HP3_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_WVALID : in STD_LOGIC;
S_AXI_HP3_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
IRQ_P2F_DMAC_ABORT : out STD_LOGIC;
IRQ_P2F_DMAC0 : out STD_LOGIC;
IRQ_P2F_DMAC1 : out STD_LOGIC;
IRQ_P2F_DMAC2 : out STD_LOGIC;
IRQ_P2F_DMAC3 : out STD_LOGIC;
IRQ_P2F_DMAC4 : out STD_LOGIC;
IRQ_P2F_DMAC5 : out STD_LOGIC;
IRQ_P2F_DMAC6 : out STD_LOGIC;
IRQ_P2F_DMAC7 : out STD_LOGIC;
IRQ_P2F_SMC : out STD_LOGIC;
IRQ_P2F_QSPI : out STD_LOGIC;
IRQ_P2F_CTI : out STD_LOGIC;
IRQ_P2F_GPIO : out STD_LOGIC;
IRQ_P2F_USB0 : out STD_LOGIC;
IRQ_P2F_ENET0 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE0 : out STD_LOGIC;
IRQ_P2F_SDIO0 : out STD_LOGIC;
IRQ_P2F_I2C0 : out STD_LOGIC;
IRQ_P2F_SPI0 : out STD_LOGIC;
IRQ_P2F_UART0 : out STD_LOGIC;
IRQ_P2F_CAN0 : out STD_LOGIC;
IRQ_P2F_USB1 : out STD_LOGIC;
IRQ_P2F_ENET1 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE1 : out STD_LOGIC;
IRQ_P2F_SDIO1 : out STD_LOGIC;
IRQ_P2F_I2C1 : out STD_LOGIC;
IRQ_P2F_SPI1 : out STD_LOGIC;
IRQ_P2F_UART1 : out STD_LOGIC;
IRQ_P2F_CAN1 : out STD_LOGIC;
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
Core0_nFIQ : in STD_LOGIC;
Core0_nIRQ : in STD_LOGIC;
Core1_nFIQ : in STD_LOGIC;
Core1_nIRQ : in STD_LOGIC;
DMA0_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA0_DAVALID : out STD_LOGIC;
DMA0_DRREADY : out STD_LOGIC;
DMA0_RSTN : out STD_LOGIC;
DMA1_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DAVALID : out STD_LOGIC;
DMA1_DRREADY : out STD_LOGIC;
DMA1_RSTN : out STD_LOGIC;
DMA2_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DAVALID : out STD_LOGIC;
DMA2_DRREADY : out STD_LOGIC;
DMA2_RSTN : out STD_LOGIC;
DMA3_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DAVALID : out STD_LOGIC;
DMA3_DRREADY : out STD_LOGIC;
DMA3_RSTN : out STD_LOGIC;
DMA0_ACLK : in STD_LOGIC;
DMA0_DAREADY : in STD_LOGIC;
DMA0_DRLAST : in STD_LOGIC;
DMA0_DRVALID : in STD_LOGIC;
DMA1_ACLK : in STD_LOGIC;
DMA1_DAREADY : in STD_LOGIC;
DMA1_DRLAST : in STD_LOGIC;
DMA1_DRVALID : in STD_LOGIC;
DMA2_ACLK : in STD_LOGIC;
DMA2_DAREADY : in STD_LOGIC;
DMA2_DRLAST : in STD_LOGIC;
DMA2_DRVALID : in STD_LOGIC;
DMA3_ACLK : in STD_LOGIC;
DMA3_DAREADY : in STD_LOGIC;
DMA3_DRLAST : in STD_LOGIC;
DMA3_DRVALID : in STD_LOGIC;
DMA0_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
FCLK_CLK3 : out STD_LOGIC;
FCLK_CLK2 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLKTRIG3_N : in STD_LOGIC;
FCLK_CLKTRIG2_N : in STD_LOGIC;
FCLK_CLKTRIG1_N : in STD_LOGIC;
FCLK_CLKTRIG0_N : in STD_LOGIC;
FCLK_RESET3_N : out STD_LOGIC;
FCLK_RESET2_N : out STD_LOGIC;
FCLK_RESET1_N : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FTMD_TRACEIN_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMD_TRACEIN_VALID : in STD_LOGIC;
FTMD_TRACEIN_CLK : in STD_LOGIC;
FTMD_TRACEIN_ATID : in STD_LOGIC_VECTOR ( 3 downto 0 );
FTMT_F2P_TRIG_0 : in STD_LOGIC;
FTMT_F2P_TRIGACK_0 : out STD_LOGIC;
FTMT_F2P_TRIG_1 : in STD_LOGIC;
FTMT_F2P_TRIGACK_1 : out STD_LOGIC;
FTMT_F2P_TRIG_2 : in STD_LOGIC;
FTMT_F2P_TRIGACK_2 : out STD_LOGIC;
FTMT_F2P_TRIG_3 : in STD_LOGIC;
FTMT_F2P_TRIGACK_3 : out STD_LOGIC;
FTMT_F2P_DEBUG : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMT_P2F_TRIGACK_0 : in STD_LOGIC;
FTMT_P2F_TRIG_0 : out STD_LOGIC;
FTMT_P2F_TRIGACK_1 : in STD_LOGIC;
FTMT_P2F_TRIG_1 : out STD_LOGIC;
FTMT_P2F_TRIGACK_2 : in STD_LOGIC;
FTMT_P2F_TRIG_2 : out STD_LOGIC;
FTMT_P2F_TRIGACK_3 : in STD_LOGIC;
FTMT_P2F_TRIG_3 : out STD_LOGIC;
FTMT_P2F_DEBUG : out STD_LOGIC_VECTOR ( 31 downto 0 );
FPGA_IDLE_N : in STD_LOGIC;
EVENT_EVENTO : out STD_LOGIC;
EVENT_STANDBYWFE : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_STANDBYWFI : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_EVENTI : in STD_LOGIC;
DDR_ARB : in STD_LOGIC_VECTOR ( 3 downto 0 );
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "clg400";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "design_1_processing_system7_0_0.hwdef";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "processing_system7_v5_5_processing_system7";
attribute POWER : string;
attribute POWER of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "<PROCESSOR name={system} numA9Cores={2} clockFreq={867} load={0.5} /><MEMORY name={code} memType={LPDDR2} dataWidth={32} clockFreq={400} readRate={0.5} writeRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={49.999947} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={6} ioBank={Vcco_p1} clockFreq={99.999893} usageRate={0.5} /><PLL domain={Processor} vco={1733.332} /><PLL domain={Memory} vco={1599.998} /><PLL domain={IO} vco={1999.998} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
end design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7;
architecture STRUCTURE of design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal ENET0_MDIO_T_n : STD_LOGIC;
signal ENET1_MDIO_T_n : STD_LOGIC;
signal I2C0_SCL_T_n : STD_LOGIC;
signal I2C0_SDA_T_n : STD_LOGIC;
signal I2C1_SCL_T_n : STD_LOGIC;
signal I2C1_SDA_T_n : STD_LOGIC;
signal \^m_axi_gp0_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp0_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp0_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp0_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp1_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp1_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal SDIO0_CMD_T_n : STD_LOGIC;
signal SDIO0_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SDIO1_CMD_T_n : STD_LOGIC;
signal SDIO1_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SPI0_MISO_T_n : STD_LOGIC;
signal SPI0_MOSI_T_n : STD_LOGIC;
signal SPI0_SCLK_T_n : STD_LOGIC;
signal SPI0_SS_T_n : STD_LOGIC;
signal SPI1_MISO_T_n : STD_LOGIC;
signal SPI1_MOSI_T_n : STD_LOGIC;
signal SPI1_SCLK_T_n : STD_LOGIC;
signal SPI1_SS_T_n : STD_LOGIC;
signal \TRACE_CTL_PIPE[0]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \TRACE_CTL_PIPE[0]\ : signal is "true";
signal \TRACE_CTL_PIPE[1]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[1]\ : signal is "true";
signal \TRACE_CTL_PIPE[2]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[2]\ : signal is "true";
signal \TRACE_CTL_PIPE[3]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[3]\ : signal is "true";
signal \TRACE_CTL_PIPE[4]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[4]\ : signal is "true";
signal \TRACE_CTL_PIPE[5]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[5]\ : signal is "true";
signal \TRACE_CTL_PIPE[6]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[6]\ : signal is "true";
signal \TRACE_CTL_PIPE[7]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[7]\ : signal is "true";
signal \TRACE_DATA_PIPE[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[0]\ : signal is "true";
signal \TRACE_DATA_PIPE[1]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[1]\ : signal is "true";
signal \TRACE_DATA_PIPE[2]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[2]\ : signal is "true";
signal \TRACE_DATA_PIPE[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[3]\ : signal is "true";
signal \TRACE_DATA_PIPE[4]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[4]\ : signal is "true";
signal \TRACE_DATA_PIPE[5]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[5]\ : signal is "true";
signal \TRACE_DATA_PIPE[6]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[6]\ : signal is "true";
signal \TRACE_DATA_PIPE[7]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[7]\ : signal is "true";
signal buffered_DDR_Addr : STD_LOGIC_VECTOR ( 14 downto 0 );
signal buffered_DDR_BankAddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal buffered_DDR_CAS_n : STD_LOGIC;
signal buffered_DDR_CKE : STD_LOGIC;
signal buffered_DDR_CS_n : STD_LOGIC;
signal buffered_DDR_Clk : STD_LOGIC;
signal buffered_DDR_Clk_n : STD_LOGIC;
signal buffered_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal buffered_DDR_DQS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQS_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DRSTB : STD_LOGIC;
signal buffered_DDR_ODT : STD_LOGIC;
signal buffered_DDR_RAS_n : STD_LOGIC;
signal buffered_DDR_VRN : STD_LOGIC;
signal buffered_DDR_VRP : STD_LOGIC;
signal buffered_DDR_WEB : STD_LOGIC;
signal buffered_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal buffered_PS_CLK : STD_LOGIC;
signal buffered_PS_PORB : STD_LOGIC;
signal buffered_PS_SRSTB : STD_LOGIC;
signal gpio_out_t_n : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOTRACECTL_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of DDR_CAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CKE_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_DRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_ODT_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_RAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRN_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRP_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_WEB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS7_i : label is "PRIMITIVE";
attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[12].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[13].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[14].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[15].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[16].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[17].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[18].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[19].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[1].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[20].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[21].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[22].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[23].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[24].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[25].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[26].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[27].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[28].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[29].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[2].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[30].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[31].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[32].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[33].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[34].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[35].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[36].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[37].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[38].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[39].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[3].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[40].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[41].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[42].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[43].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[44].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[45].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[46].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[47].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[48].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[49].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[4].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[50].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[51].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[52].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[53].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[5].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[6].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[7].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[8].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[9].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[0].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[1].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[2].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[0].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[10].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[11].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[12].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[13].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[14].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[1].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[2].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[3].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[4].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[5].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[6].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[7].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[8].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[9].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[0].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[1].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[2].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[3].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[0].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[10].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[11].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[12].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[13].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[14].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[15].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[16].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[17].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[18].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[19].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[1].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[20].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[21].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[22].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[23].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[24].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[25].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[26].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[27].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[28].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[29].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[2].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[30].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[31].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[3].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[4].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[5].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[6].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[7].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[8].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[9].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[0].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[1].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[2].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[3].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[0].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[1].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[2].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[3].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
begin
ENET0_GMII_TXD(7) <= \<const0>\;
ENET0_GMII_TXD(6) <= \<const0>\;
ENET0_GMII_TXD(5) <= \<const0>\;
ENET0_GMII_TXD(4) <= \<const0>\;
ENET0_GMII_TXD(3) <= \<const0>\;
ENET0_GMII_TXD(2) <= \<const0>\;
ENET0_GMII_TXD(1) <= \<const0>\;
ENET0_GMII_TXD(0) <= \<const0>\;
ENET0_GMII_TX_EN <= \<const0>\;
ENET0_GMII_TX_ER <= \<const0>\;
ENET1_GMII_TXD(7) <= \<const0>\;
ENET1_GMII_TXD(6) <= \<const0>\;
ENET1_GMII_TXD(5) <= \<const0>\;
ENET1_GMII_TXD(4) <= \<const0>\;
ENET1_GMII_TXD(3) <= \<const0>\;
ENET1_GMII_TXD(2) <= \<const0>\;
ENET1_GMII_TXD(1) <= \<const0>\;
ENET1_GMII_TXD(0) <= \<const0>\;
ENET1_GMII_TX_EN <= \<const0>\;
ENET1_GMII_TX_ER <= \<const0>\;
M_AXI_GP0_ARCACHE(3 downto 2) <= \^m_axi_gp0_arcache\(3 downto 2);
M_AXI_GP0_ARCACHE(1) <= \<const1>\;
M_AXI_GP0_ARCACHE(0) <= \^m_axi_gp0_arcache\(0);
M_AXI_GP0_ARSIZE(2) <= \<const0>\;
M_AXI_GP0_ARSIZE(1 downto 0) <= \^m_axi_gp0_arsize\(1 downto 0);
M_AXI_GP0_AWCACHE(3 downto 2) <= \^m_axi_gp0_awcache\(3 downto 2);
M_AXI_GP0_AWCACHE(1) <= \<const1>\;
M_AXI_GP0_AWCACHE(0) <= \^m_axi_gp0_awcache\(0);
M_AXI_GP0_AWSIZE(2) <= \<const0>\;
M_AXI_GP0_AWSIZE(1 downto 0) <= \^m_axi_gp0_awsize\(1 downto 0);
M_AXI_GP1_ARCACHE(3 downto 2) <= \^m_axi_gp1_arcache\(3 downto 2);
M_AXI_GP1_ARCACHE(1) <= \<const1>\;
M_AXI_GP1_ARCACHE(0) <= \^m_axi_gp1_arcache\(0);
M_AXI_GP1_ARSIZE(2) <= \<const0>\;
M_AXI_GP1_ARSIZE(1 downto 0) <= \^m_axi_gp1_arsize\(1 downto 0);
M_AXI_GP1_AWCACHE(3 downto 2) <= \^m_axi_gp1_awcache\(3 downto 2);
M_AXI_GP1_AWCACHE(1) <= \<const1>\;
M_AXI_GP1_AWCACHE(0) <= \^m_axi_gp1_awcache\(0);
M_AXI_GP1_AWSIZE(2) <= \<const0>\;
M_AXI_GP1_AWSIZE(1 downto 0) <= \^m_axi_gp1_awsize\(1 downto 0);
PJTAG_TDO <= \<const0>\;
TRACE_CLK_OUT <= \<const0>\;
TRACE_CTL <= \TRACE_CTL_PIPE[0]\;
TRACE_DATA(1 downto 0) <= \TRACE_DATA_PIPE[0]\(1 downto 0);
DDR_CAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CAS_n,
PAD => DDR_CAS_n
);
DDR_CKE_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CKE,
PAD => DDR_CKE
);
DDR_CS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CS_n,
PAD => DDR_CS_n
);
DDR_Clk_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk,
PAD => DDR_Clk
);
DDR_Clk_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk_n,
PAD => DDR_Clk_n
);
DDR_DRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DRSTB,
PAD => DDR_DRSTB
);
DDR_ODT_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_ODT,
PAD => DDR_ODT
);
DDR_RAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_RAS_n,
PAD => DDR_RAS_n
);
DDR_VRN_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRN,
PAD => DDR_VRN
);
DDR_VRP_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRP,
PAD => DDR_VRP
);
DDR_WEB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_WEB,
PAD => DDR_WEB
);
ENET0_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET0_MDIO_T_n,
O => ENET0_MDIO_T
);
ENET1_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET1_MDIO_T_n,
O => ENET1_MDIO_T
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\GPIO_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(0),
O => GPIO_T(0)
);
\GPIO_T[10]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(10),
O => GPIO_T(10)
);
\GPIO_T[11]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(11),
O => GPIO_T(11)
);
\GPIO_T[12]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(12),
O => GPIO_T(12)
);
\GPIO_T[13]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(13),
O => GPIO_T(13)
);
\GPIO_T[14]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(14),
O => GPIO_T(14)
);
\GPIO_T[15]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(15),
O => GPIO_T(15)
);
\GPIO_T[16]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(16),
O => GPIO_T(16)
);
\GPIO_T[17]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(17),
O => GPIO_T(17)
);
\GPIO_T[18]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(18),
O => GPIO_T(18)
);
\GPIO_T[19]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(19),
O => GPIO_T(19)
);
\GPIO_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(1),
O => GPIO_T(1)
);
\GPIO_T[20]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(20),
O => GPIO_T(20)
);
\GPIO_T[21]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(21),
O => GPIO_T(21)
);
\GPIO_T[22]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(22),
O => GPIO_T(22)
);
\GPIO_T[23]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(23),
O => GPIO_T(23)
);
\GPIO_T[24]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(24),
O => GPIO_T(24)
);
\GPIO_T[25]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(25),
O => GPIO_T(25)
);
\GPIO_T[26]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(26),
O => GPIO_T(26)
);
\GPIO_T[27]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(27),
O => GPIO_T(27)
);
\GPIO_T[28]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(28),
O => GPIO_T(28)
);
\GPIO_T[29]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(29),
O => GPIO_T(29)
);
\GPIO_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(2),
O => GPIO_T(2)
);
\GPIO_T[30]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(30),
O => GPIO_T(30)
);
\GPIO_T[31]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(31),
O => GPIO_T(31)
);
\GPIO_T[32]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(32),
O => GPIO_T(32)
);
\GPIO_T[33]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(33),
O => GPIO_T(33)
);
\GPIO_T[34]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(34),
O => GPIO_T(34)
);
\GPIO_T[35]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(35),
O => GPIO_T(35)
);
\GPIO_T[36]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(36),
O => GPIO_T(36)
);
\GPIO_T[37]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(37),
O => GPIO_T(37)
);
\GPIO_T[38]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(38),
O => GPIO_T(38)
);
\GPIO_T[39]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(39),
O => GPIO_T(39)
);
\GPIO_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(3),
O => GPIO_T(3)
);
\GPIO_T[40]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(40),
O => GPIO_T(40)
);
\GPIO_T[41]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(41),
O => GPIO_T(41)
);
\GPIO_T[42]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(42),
O => GPIO_T(42)
);
\GPIO_T[43]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(43),
O => GPIO_T(43)
);
\GPIO_T[44]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(44),
O => GPIO_T(44)
);
\GPIO_T[45]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(45),
O => GPIO_T(45)
);
\GPIO_T[46]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(46),
O => GPIO_T(46)
);
\GPIO_T[47]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(47),
O => GPIO_T(47)
);
\GPIO_T[48]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(48),
O => GPIO_T(48)
);
\GPIO_T[49]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(49),
O => GPIO_T(49)
);
\GPIO_T[4]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(4),
O => GPIO_T(4)
);
\GPIO_T[50]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(50),
O => GPIO_T(50)
);
\GPIO_T[51]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(51),
O => GPIO_T(51)
);
\GPIO_T[52]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(52),
O => GPIO_T(52)
);
\GPIO_T[53]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(53),
O => GPIO_T(53)
);
\GPIO_T[54]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(54),
O => GPIO_T(54)
);
\GPIO_T[55]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(55),
O => GPIO_T(55)
);
\GPIO_T[56]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(56),
O => GPIO_T(56)
);
\GPIO_T[57]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(57),
O => GPIO_T(57)
);
\GPIO_T[58]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(58),
O => GPIO_T(58)
);
\GPIO_T[59]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(59),
O => GPIO_T(59)
);
\GPIO_T[5]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(5),
O => GPIO_T(5)
);
\GPIO_T[60]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(60),
O => GPIO_T(60)
);
\GPIO_T[61]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(61),
O => GPIO_T(61)
);
\GPIO_T[62]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(62),
O => GPIO_T(62)
);
\GPIO_T[63]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(63),
O => GPIO_T(63)
);
\GPIO_T[6]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(6),
O => GPIO_T(6)
);
\GPIO_T[7]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(7),
O => GPIO_T(7)
);
\GPIO_T[8]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(8),
O => GPIO_T(8)
);
\GPIO_T[9]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(9),
O => GPIO_T(9)
);
I2C0_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SCL_T_n,
O => I2C0_SCL_T
);
I2C0_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SDA_T_n,
O => I2C0_SDA_T
);
I2C1_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SCL_T_n,
O => I2C1_SCL_T
);
I2C1_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SDA_T_n,
O => I2C1_SDA_T
);
PS7_i: unisim.vcomponents.PS7
port map (
DDRA(14 downto 0) => buffered_DDR_Addr(14 downto 0),
DDRARB(3 downto 0) => DDR_ARB(3 downto 0),
DDRBA(2 downto 0) => buffered_DDR_BankAddr(2 downto 0),
DDRCASB => buffered_DDR_CAS_n,
DDRCKE => buffered_DDR_CKE,
DDRCKN => buffered_DDR_Clk_n,
DDRCKP => buffered_DDR_Clk,
DDRCSB => buffered_DDR_CS_n,
DDRDM(3 downto 0) => buffered_DDR_DM(3 downto 0),
DDRDQ(31 downto 0) => buffered_DDR_DQ(31 downto 0),
DDRDQSN(3 downto 0) => buffered_DDR_DQS_n(3 downto 0),
DDRDQSP(3 downto 0) => buffered_DDR_DQS(3 downto 0),
DDRDRSTB => buffered_DDR_DRSTB,
DDRODT => buffered_DDR_ODT,
DDRRASB => buffered_DDR_RAS_n,
DDRVRN => buffered_DDR_VRN,
DDRVRP => buffered_DDR_VRP,
DDRWEB => buffered_DDR_WEB,
DMA0ACLK => DMA0_ACLK,
DMA0DAREADY => DMA0_DAREADY,
DMA0DATYPE(1 downto 0) => DMA0_DATYPE(1 downto 0),
DMA0DAVALID => DMA0_DAVALID,
DMA0DRLAST => DMA0_DRLAST,
DMA0DRREADY => DMA0_DRREADY,
DMA0DRTYPE(1 downto 0) => DMA0_DRTYPE(1 downto 0),
DMA0DRVALID => DMA0_DRVALID,
DMA0RSTN => DMA0_RSTN,
DMA1ACLK => DMA1_ACLK,
DMA1DAREADY => DMA1_DAREADY,
DMA1DATYPE(1 downto 0) => DMA1_DATYPE(1 downto 0),
DMA1DAVALID => DMA1_DAVALID,
DMA1DRLAST => DMA1_DRLAST,
DMA1DRREADY => DMA1_DRREADY,
DMA1DRTYPE(1 downto 0) => DMA1_DRTYPE(1 downto 0),
DMA1DRVALID => DMA1_DRVALID,
DMA1RSTN => DMA1_RSTN,
DMA2ACLK => DMA2_ACLK,
DMA2DAREADY => DMA2_DAREADY,
DMA2DATYPE(1 downto 0) => DMA2_DATYPE(1 downto 0),
DMA2DAVALID => DMA2_DAVALID,
DMA2DRLAST => DMA2_DRLAST,
DMA2DRREADY => DMA2_DRREADY,
DMA2DRTYPE(1 downto 0) => DMA2_DRTYPE(1 downto 0),
DMA2DRVALID => DMA2_DRVALID,
DMA2RSTN => DMA2_RSTN,
DMA3ACLK => DMA3_ACLK,
DMA3DAREADY => DMA3_DAREADY,
DMA3DATYPE(1 downto 0) => DMA3_DATYPE(1 downto 0),
DMA3DAVALID => DMA3_DAVALID,
DMA3DRLAST => DMA3_DRLAST,
DMA3DRREADY => DMA3_DRREADY,
DMA3DRTYPE(1 downto 0) => DMA3_DRTYPE(1 downto 0),
DMA3DRVALID => DMA3_DRVALID,
DMA3RSTN => DMA3_RSTN,
EMIOCAN0PHYRX => CAN0_PHY_RX,
EMIOCAN0PHYTX => CAN0_PHY_TX,
EMIOCAN1PHYRX => CAN1_PHY_RX,
EMIOCAN1PHYTX => CAN1_PHY_TX,
EMIOENET0EXTINTIN => ENET0_EXT_INTIN,
EMIOENET0GMIICOL => '0',
EMIOENET0GMIICRS => '0',
EMIOENET0GMIIRXCLK => ENET0_GMII_RX_CLK,
EMIOENET0GMIIRXD(7 downto 0) => B"00000000",
EMIOENET0GMIIRXDV => '0',
EMIOENET0GMIIRXER => '0',
EMIOENET0GMIITXCLK => ENET0_GMII_TX_CLK,
EMIOENET0GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET0GMIITXEN => NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED,
EMIOENET0GMIITXER => NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED,
EMIOENET0MDIOI => ENET0_MDIO_I,
EMIOENET0MDIOMDC => ENET0_MDIO_MDC,
EMIOENET0MDIOO => ENET0_MDIO_O,
EMIOENET0MDIOTN => ENET0_MDIO_T_n,
EMIOENET0PTPDELAYREQRX => ENET0_PTP_DELAY_REQ_RX,
EMIOENET0PTPDELAYREQTX => ENET0_PTP_DELAY_REQ_TX,
EMIOENET0PTPPDELAYREQRX => ENET0_PTP_PDELAY_REQ_RX,
EMIOENET0PTPPDELAYREQTX => ENET0_PTP_PDELAY_REQ_TX,
EMIOENET0PTPPDELAYRESPRX => ENET0_PTP_PDELAY_RESP_RX,
EMIOENET0PTPPDELAYRESPTX => ENET0_PTP_PDELAY_RESP_TX,
EMIOENET0PTPSYNCFRAMERX => ENET0_PTP_SYNC_FRAME_RX,
EMIOENET0PTPSYNCFRAMETX => ENET0_PTP_SYNC_FRAME_TX,
EMIOENET0SOFRX => ENET0_SOF_RX,
EMIOENET0SOFTX => ENET0_SOF_TX,
EMIOENET1EXTINTIN => ENET1_EXT_INTIN,
EMIOENET1GMIICOL => '0',
EMIOENET1GMIICRS => '0',
EMIOENET1GMIIRXCLK => ENET1_GMII_RX_CLK,
EMIOENET1GMIIRXD(7 downto 0) => B"00000000",
EMIOENET1GMIIRXDV => '0',
EMIOENET1GMIIRXER => '0',
EMIOENET1GMIITXCLK => ENET1_GMII_TX_CLK,
EMIOENET1GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET1GMIITXEN => NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED,
EMIOENET1GMIITXER => NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED,
EMIOENET1MDIOI => ENET1_MDIO_I,
EMIOENET1MDIOMDC => ENET1_MDIO_MDC,
EMIOENET1MDIOO => ENET1_MDIO_O,
EMIOENET1MDIOTN => ENET1_MDIO_T_n,
EMIOENET1PTPDELAYREQRX => ENET1_PTP_DELAY_REQ_RX,
EMIOENET1PTPDELAYREQTX => ENET1_PTP_DELAY_REQ_TX,
EMIOENET1PTPPDELAYREQRX => ENET1_PTP_PDELAY_REQ_RX,
EMIOENET1PTPPDELAYREQTX => ENET1_PTP_PDELAY_REQ_TX,
EMIOENET1PTPPDELAYRESPRX => ENET1_PTP_PDELAY_RESP_RX,
EMIOENET1PTPPDELAYRESPTX => ENET1_PTP_PDELAY_RESP_TX,
EMIOENET1PTPSYNCFRAMERX => ENET1_PTP_SYNC_FRAME_RX,
EMIOENET1PTPSYNCFRAMETX => ENET1_PTP_SYNC_FRAME_TX,
EMIOENET1SOFRX => ENET1_SOF_RX,
EMIOENET1SOFTX => ENET1_SOF_TX,
EMIOGPIOI(63 downto 0) => GPIO_I(63 downto 0),
EMIOGPIOO(63 downto 0) => GPIO_O(63 downto 0),
EMIOGPIOTN(63 downto 0) => gpio_out_t_n(63 downto 0),
EMIOI2C0SCLI => I2C0_SCL_I,
EMIOI2C0SCLO => I2C0_SCL_O,
EMIOI2C0SCLTN => I2C0_SCL_T_n,
EMIOI2C0SDAI => I2C0_SDA_I,
EMIOI2C0SDAO => I2C0_SDA_O,
EMIOI2C0SDATN => I2C0_SDA_T_n,
EMIOI2C1SCLI => I2C1_SCL_I,
EMIOI2C1SCLO => I2C1_SCL_O,
EMIOI2C1SCLTN => I2C1_SCL_T_n,
EMIOI2C1SDAI => I2C1_SDA_I,
EMIOI2C1SDAO => I2C1_SDA_O,
EMIOI2C1SDATN => I2C1_SDA_T_n,
EMIOPJTAGTCK => PJTAG_TCK,
EMIOPJTAGTDI => PJTAG_TDI,
EMIOPJTAGTDO => NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED,
EMIOPJTAGTDTN => NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED,
EMIOPJTAGTMS => PJTAG_TMS,
EMIOSDIO0BUSPOW => SDIO0_BUSPOW,
EMIOSDIO0BUSVOLT(2 downto 0) => SDIO0_BUSVOLT(2 downto 0),
EMIOSDIO0CDN => SDIO0_CDN,
EMIOSDIO0CLK => SDIO0_CLK,
EMIOSDIO0CLKFB => SDIO0_CLK_FB,
EMIOSDIO0CMDI => SDIO0_CMD_I,
EMIOSDIO0CMDO => SDIO0_CMD_O,
EMIOSDIO0CMDTN => SDIO0_CMD_T_n,
EMIOSDIO0DATAI(3 downto 0) => SDIO0_DATA_I(3 downto 0),
EMIOSDIO0DATAO(3 downto 0) => SDIO0_DATA_O(3 downto 0),
EMIOSDIO0DATATN(3 downto 0) => SDIO0_DATA_T_n(3 downto 0),
EMIOSDIO0LED => SDIO0_LED,
EMIOSDIO0WP => SDIO0_WP,
EMIOSDIO1BUSPOW => SDIO1_BUSPOW,
EMIOSDIO1BUSVOLT(2 downto 0) => SDIO1_BUSVOLT(2 downto 0),
EMIOSDIO1CDN => SDIO1_CDN,
EMIOSDIO1CLK => SDIO1_CLK,
EMIOSDIO1CLKFB => SDIO1_CLK_FB,
EMIOSDIO1CMDI => SDIO1_CMD_I,
EMIOSDIO1CMDO => SDIO1_CMD_O,
EMIOSDIO1CMDTN => SDIO1_CMD_T_n,
EMIOSDIO1DATAI(3 downto 0) => SDIO1_DATA_I(3 downto 0),
EMIOSDIO1DATAO(3 downto 0) => SDIO1_DATA_O(3 downto 0),
EMIOSDIO1DATATN(3 downto 0) => SDIO1_DATA_T_n(3 downto 0),
EMIOSDIO1LED => SDIO1_LED,
EMIOSDIO1WP => SDIO1_WP,
EMIOSPI0MI => SPI0_MISO_I,
EMIOSPI0MO => SPI0_MOSI_O,
EMIOSPI0MOTN => SPI0_MOSI_T_n,
EMIOSPI0SCLKI => SPI0_SCLK_I,
EMIOSPI0SCLKO => SPI0_SCLK_O,
EMIOSPI0SCLKTN => SPI0_SCLK_T_n,
EMIOSPI0SI => SPI0_MOSI_I,
EMIOSPI0SO => SPI0_MISO_O,
EMIOSPI0SSIN => SPI0_SS_I,
EMIOSPI0SSNTN => SPI0_SS_T_n,
EMIOSPI0SSON(2) => SPI0_SS2_O,
EMIOSPI0SSON(1) => SPI0_SS1_O,
EMIOSPI0SSON(0) => SPI0_SS_O,
EMIOSPI0STN => SPI0_MISO_T_n,
EMIOSPI1MI => SPI1_MISO_I,
EMIOSPI1MO => SPI1_MOSI_O,
EMIOSPI1MOTN => SPI1_MOSI_T_n,
EMIOSPI1SCLKI => SPI1_SCLK_I,
EMIOSPI1SCLKO => SPI1_SCLK_O,
EMIOSPI1SCLKTN => SPI1_SCLK_T_n,
EMIOSPI1SI => SPI1_MOSI_I,
EMIOSPI1SO => SPI1_MISO_O,
EMIOSPI1SSIN => SPI1_SS_I,
EMIOSPI1SSNTN => SPI1_SS_T_n,
EMIOSPI1SSON(2) => SPI1_SS2_O,
EMIOSPI1SSON(1) => SPI1_SS1_O,
EMIOSPI1SSON(0) => SPI1_SS_O,
EMIOSPI1STN => SPI1_MISO_T_n,
EMIOSRAMINTIN => SRAM_INTIN,
EMIOTRACECLK => TRACE_CLK,
EMIOTRACECTL => NLW_PS7_i_EMIOTRACECTL_UNCONNECTED,
EMIOTRACEDATA(31 downto 0) => NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED(31 downto 0),
EMIOTTC0CLKI(2) => TTC0_CLK2_IN,
EMIOTTC0CLKI(1) => TTC0_CLK1_IN,
EMIOTTC0CLKI(0) => TTC0_CLK0_IN,
EMIOTTC0WAVEO(2) => TTC0_WAVE2_OUT,
EMIOTTC0WAVEO(1) => TTC0_WAVE1_OUT,
EMIOTTC0WAVEO(0) => TTC0_WAVE0_OUT,
EMIOTTC1CLKI(2) => TTC1_CLK2_IN,
EMIOTTC1CLKI(1) => TTC1_CLK1_IN,
EMIOTTC1CLKI(0) => TTC1_CLK0_IN,
EMIOTTC1WAVEO(2) => TTC1_WAVE2_OUT,
EMIOTTC1WAVEO(1) => TTC1_WAVE1_OUT,
EMIOTTC1WAVEO(0) => TTC1_WAVE0_OUT,
EMIOUART0CTSN => UART0_CTSN,
EMIOUART0DCDN => UART0_DCDN,
EMIOUART0DSRN => UART0_DSRN,
EMIOUART0DTRN => UART0_DTRN,
EMIOUART0RIN => UART0_RIN,
EMIOUART0RTSN => UART0_RTSN,
EMIOUART0RX => UART0_RX,
EMIOUART0TX => UART0_TX,
EMIOUART1CTSN => UART1_CTSN,
EMIOUART1DCDN => UART1_DCDN,
EMIOUART1DSRN => UART1_DSRN,
EMIOUART1DTRN => UART1_DTRN,
EMIOUART1RIN => UART1_RIN,
EMIOUART1RTSN => UART1_RTSN,
EMIOUART1RX => UART1_RX,
EMIOUART1TX => UART1_TX,
EMIOUSB0PORTINDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
EMIOUSB0VBUSPWRFAULT => USB0_VBUS_PWRFAULT,
EMIOUSB0VBUSPWRSELECT => USB0_VBUS_PWRSELECT,
EMIOUSB1PORTINDCTL(1 downto 0) => USB1_PORT_INDCTL(1 downto 0),
EMIOUSB1VBUSPWRFAULT => USB1_VBUS_PWRFAULT,
EMIOUSB1VBUSPWRSELECT => USB1_VBUS_PWRSELECT,
EMIOWDTCLKI => WDT_CLK_IN,
EMIOWDTRSTO => WDT_RST_OUT,
EVENTEVENTI => EVENT_EVENTI,
EVENTEVENTO => EVENT_EVENTO,
EVENTSTANDBYWFE(1 downto 0) => EVENT_STANDBYWFE(1 downto 0),
EVENTSTANDBYWFI(1 downto 0) => EVENT_STANDBYWFI(1 downto 0),
FCLKCLK(3) => FCLK_CLK3,
FCLKCLK(2) => FCLK_CLK2,
FCLKCLK(1) => FCLK_CLK1,
FCLKCLK(0) => FCLK_CLK0,
FCLKCLKTRIGN(3 downto 0) => B"0000",
FCLKRESETN(3) => FCLK_RESET3_N,
FCLKRESETN(2) => FCLK_RESET2_N,
FCLKRESETN(1) => FCLK_RESET1_N,
FCLKRESETN(0) => FCLK_RESET0_N,
FPGAIDLEN => FPGA_IDLE_N,
FTMDTRACEINATID(3 downto 0) => B"0000",
FTMDTRACEINCLOCK => FTMD_TRACEIN_CLK,
FTMDTRACEINDATA(31 downto 0) => B"00000000000000000000000000000000",
FTMDTRACEINVALID => '0',
FTMTF2PDEBUG(31 downto 0) => FTMT_F2P_DEBUG(31 downto 0),
FTMTF2PTRIG(3) => FTMT_F2P_TRIG_3,
FTMTF2PTRIG(2) => FTMT_F2P_TRIG_2,
FTMTF2PTRIG(1) => FTMT_F2P_TRIG_1,
FTMTF2PTRIG(0) => FTMT_F2P_TRIG_0,
FTMTF2PTRIGACK(3) => FTMT_F2P_TRIGACK_3,
FTMTF2PTRIGACK(2) => FTMT_F2P_TRIGACK_2,
FTMTF2PTRIGACK(1) => FTMT_F2P_TRIGACK_1,
FTMTF2PTRIGACK(0) => FTMT_F2P_TRIGACK_0,
FTMTP2FDEBUG(31 downto 0) => FTMT_P2F_DEBUG(31 downto 0),
FTMTP2FTRIG(3) => FTMT_P2F_TRIG_3,
FTMTP2FTRIG(2) => FTMT_P2F_TRIG_2,
FTMTP2FTRIG(1) => FTMT_P2F_TRIG_1,
FTMTP2FTRIG(0) => FTMT_P2F_TRIG_0,
FTMTP2FTRIGACK(3) => FTMT_P2F_TRIGACK_3,
FTMTP2FTRIGACK(2) => FTMT_P2F_TRIGACK_2,
FTMTP2FTRIGACK(1) => FTMT_P2F_TRIGACK_1,
FTMTP2FTRIGACK(0) => FTMT_P2F_TRIGACK_0,
IRQF2P(19) => Core1_nFIQ,
IRQF2P(18) => Core0_nFIQ,
IRQF2P(17) => Core1_nIRQ,
IRQF2P(16) => Core0_nIRQ,
IRQF2P(15 downto 1) => B"000000000000000",
IRQF2P(0) => IRQ_F2P(0),
IRQP2F(28) => IRQ_P2F_DMAC_ABORT,
IRQP2F(27) => IRQ_P2F_DMAC7,
IRQP2F(26) => IRQ_P2F_DMAC6,
IRQP2F(25) => IRQ_P2F_DMAC5,
IRQP2F(24) => IRQ_P2F_DMAC4,
IRQP2F(23) => IRQ_P2F_DMAC3,
IRQP2F(22) => IRQ_P2F_DMAC2,
IRQP2F(21) => IRQ_P2F_DMAC1,
IRQP2F(20) => IRQ_P2F_DMAC0,
IRQP2F(19) => IRQ_P2F_SMC,
IRQP2F(18) => IRQ_P2F_QSPI,
IRQP2F(17) => IRQ_P2F_CTI,
IRQP2F(16) => IRQ_P2F_GPIO,
IRQP2F(15) => IRQ_P2F_USB0,
IRQP2F(14) => IRQ_P2F_ENET0,
IRQP2F(13) => IRQ_P2F_ENET_WAKE0,
IRQP2F(12) => IRQ_P2F_SDIO0,
IRQP2F(11) => IRQ_P2F_I2C0,
IRQP2F(10) => IRQ_P2F_SPI0,
IRQP2F(9) => IRQ_P2F_UART0,
IRQP2F(8) => IRQ_P2F_CAN0,
IRQP2F(7) => IRQ_P2F_USB1,
IRQP2F(6) => IRQ_P2F_ENET1,
IRQP2F(5) => IRQ_P2F_ENET_WAKE1,
IRQP2F(4) => IRQ_P2F_SDIO1,
IRQP2F(3) => IRQ_P2F_I2C1,
IRQP2F(2) => IRQ_P2F_SPI1,
IRQP2F(1) => IRQ_P2F_UART1,
IRQP2F(0) => IRQ_P2F_CAN1,
MAXIGP0ACLK => M_AXI_GP0_ACLK,
MAXIGP0ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
MAXIGP0ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
MAXIGP0ARCACHE(3 downto 2) => \^m_axi_gp0_arcache\(3 downto 2),
MAXIGP0ARCACHE(1) => NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED(1),
MAXIGP0ARCACHE(0) => \^m_axi_gp0_arcache\(0),
MAXIGP0ARESETN => M_AXI_GP0_ARESETN,
MAXIGP0ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
MAXIGP0ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
MAXIGP0ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
MAXIGP0ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
MAXIGP0ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
MAXIGP0ARREADY => M_AXI_GP0_ARREADY,
MAXIGP0ARSIZE(1 downto 0) => \^m_axi_gp0_arsize\(1 downto 0),
MAXIGP0ARVALID => M_AXI_GP0_ARVALID,
MAXIGP0AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
MAXIGP0AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
MAXIGP0AWCACHE(3 downto 2) => \^m_axi_gp0_awcache\(3 downto 2),
MAXIGP0AWCACHE(1) => NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED(1),
MAXIGP0AWCACHE(0) => \^m_axi_gp0_awcache\(0),
MAXIGP0AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
MAXIGP0AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
MAXIGP0AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
MAXIGP0AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
MAXIGP0AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
MAXIGP0AWREADY => M_AXI_GP0_AWREADY,
MAXIGP0AWSIZE(1 downto 0) => \^m_axi_gp0_awsize\(1 downto 0),
MAXIGP0AWVALID => M_AXI_GP0_AWVALID,
MAXIGP0BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
MAXIGP0BREADY => M_AXI_GP0_BREADY,
MAXIGP0BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
MAXIGP0BVALID => M_AXI_GP0_BVALID,
MAXIGP0RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
MAXIGP0RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
MAXIGP0RLAST => M_AXI_GP0_RLAST,
MAXIGP0RREADY => M_AXI_GP0_RREADY,
MAXIGP0RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
MAXIGP0RVALID => M_AXI_GP0_RVALID,
MAXIGP0WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
MAXIGP0WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
MAXIGP0WLAST => M_AXI_GP0_WLAST,
MAXIGP0WREADY => M_AXI_GP0_WREADY,
MAXIGP0WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
MAXIGP0WVALID => M_AXI_GP0_WVALID,
MAXIGP1ACLK => M_AXI_GP1_ACLK,
MAXIGP1ARADDR(31 downto 0) => M_AXI_GP1_ARADDR(31 downto 0),
MAXIGP1ARBURST(1 downto 0) => M_AXI_GP1_ARBURST(1 downto 0),
MAXIGP1ARCACHE(3 downto 2) => \^m_axi_gp1_arcache\(3 downto 2),
MAXIGP1ARCACHE(1) => NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED(1),
MAXIGP1ARCACHE(0) => \^m_axi_gp1_arcache\(0),
MAXIGP1ARESETN => M_AXI_GP1_ARESETN,
MAXIGP1ARID(11 downto 0) => M_AXI_GP1_ARID(11 downto 0),
MAXIGP1ARLEN(3 downto 0) => M_AXI_GP1_ARLEN(3 downto 0),
MAXIGP1ARLOCK(1 downto 0) => M_AXI_GP1_ARLOCK(1 downto 0),
MAXIGP1ARPROT(2 downto 0) => M_AXI_GP1_ARPROT(2 downto 0),
MAXIGP1ARQOS(3 downto 0) => M_AXI_GP1_ARQOS(3 downto 0),
MAXIGP1ARREADY => M_AXI_GP1_ARREADY,
MAXIGP1ARSIZE(1 downto 0) => \^m_axi_gp1_arsize\(1 downto 0),
MAXIGP1ARVALID => M_AXI_GP1_ARVALID,
MAXIGP1AWADDR(31 downto 0) => M_AXI_GP1_AWADDR(31 downto 0),
MAXIGP1AWBURST(1 downto 0) => M_AXI_GP1_AWBURST(1 downto 0),
MAXIGP1AWCACHE(3 downto 2) => \^m_axi_gp1_awcache\(3 downto 2),
MAXIGP1AWCACHE(1) => NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED(1),
MAXIGP1AWCACHE(0) => \^m_axi_gp1_awcache\(0),
MAXIGP1AWID(11 downto 0) => M_AXI_GP1_AWID(11 downto 0),
MAXIGP1AWLEN(3 downto 0) => M_AXI_GP1_AWLEN(3 downto 0),
MAXIGP1AWLOCK(1 downto 0) => M_AXI_GP1_AWLOCK(1 downto 0),
MAXIGP1AWPROT(2 downto 0) => M_AXI_GP1_AWPROT(2 downto 0),
MAXIGP1AWQOS(3 downto 0) => M_AXI_GP1_AWQOS(3 downto 0),
MAXIGP1AWREADY => M_AXI_GP1_AWREADY,
MAXIGP1AWSIZE(1 downto 0) => \^m_axi_gp1_awsize\(1 downto 0),
MAXIGP1AWVALID => M_AXI_GP1_AWVALID,
MAXIGP1BID(11 downto 0) => M_AXI_GP1_BID(11 downto 0),
MAXIGP1BREADY => M_AXI_GP1_BREADY,
MAXIGP1BRESP(1 downto 0) => M_AXI_GP1_BRESP(1 downto 0),
MAXIGP1BVALID => M_AXI_GP1_BVALID,
MAXIGP1RDATA(31 downto 0) => M_AXI_GP1_RDATA(31 downto 0),
MAXIGP1RID(11 downto 0) => M_AXI_GP1_RID(11 downto 0),
MAXIGP1RLAST => M_AXI_GP1_RLAST,
MAXIGP1RREADY => M_AXI_GP1_RREADY,
MAXIGP1RRESP(1 downto 0) => M_AXI_GP1_RRESP(1 downto 0),
MAXIGP1RVALID => M_AXI_GP1_RVALID,
MAXIGP1WDATA(31 downto 0) => M_AXI_GP1_WDATA(31 downto 0),
MAXIGP1WID(11 downto 0) => M_AXI_GP1_WID(11 downto 0),
MAXIGP1WLAST => M_AXI_GP1_WLAST,
MAXIGP1WREADY => M_AXI_GP1_WREADY,
MAXIGP1WSTRB(3 downto 0) => M_AXI_GP1_WSTRB(3 downto 0),
MAXIGP1WVALID => M_AXI_GP1_WVALID,
MIO(53 downto 0) => buffered_MIO(53 downto 0),
PSCLK => buffered_PS_CLK,
PSPORB => buffered_PS_PORB,
PSSRSTB => buffered_PS_SRSTB,
SAXIACPACLK => S_AXI_ACP_ACLK,
SAXIACPARADDR(31 downto 0) => S_AXI_ACP_ARADDR(31 downto 0),
SAXIACPARBURST(1 downto 0) => S_AXI_ACP_ARBURST(1 downto 0),
SAXIACPARCACHE(3 downto 0) => S_AXI_ACP_ARCACHE(3 downto 0),
SAXIACPARESETN => S_AXI_ACP_ARESETN,
SAXIACPARID(2 downto 0) => S_AXI_ACP_ARID(2 downto 0),
SAXIACPARLEN(3 downto 0) => S_AXI_ACP_ARLEN(3 downto 0),
SAXIACPARLOCK(1 downto 0) => S_AXI_ACP_ARLOCK(1 downto 0),
SAXIACPARPROT(2 downto 0) => S_AXI_ACP_ARPROT(2 downto 0),
SAXIACPARQOS(3 downto 0) => S_AXI_ACP_ARQOS(3 downto 0),
SAXIACPARREADY => S_AXI_ACP_ARREADY,
SAXIACPARSIZE(1 downto 0) => S_AXI_ACP_ARSIZE(1 downto 0),
SAXIACPARUSER(4 downto 0) => S_AXI_ACP_ARUSER(4 downto 0),
SAXIACPARVALID => S_AXI_ACP_ARVALID,
SAXIACPAWADDR(31 downto 0) => S_AXI_ACP_AWADDR(31 downto 0),
SAXIACPAWBURST(1 downto 0) => S_AXI_ACP_AWBURST(1 downto 0),
SAXIACPAWCACHE(3 downto 0) => S_AXI_ACP_AWCACHE(3 downto 0),
SAXIACPAWID(2 downto 0) => S_AXI_ACP_AWID(2 downto 0),
SAXIACPAWLEN(3 downto 0) => S_AXI_ACP_AWLEN(3 downto 0),
SAXIACPAWLOCK(1 downto 0) => S_AXI_ACP_AWLOCK(1 downto 0),
SAXIACPAWPROT(2 downto 0) => S_AXI_ACP_AWPROT(2 downto 0),
SAXIACPAWQOS(3 downto 0) => S_AXI_ACP_AWQOS(3 downto 0),
SAXIACPAWREADY => S_AXI_ACP_AWREADY,
SAXIACPAWSIZE(1 downto 0) => S_AXI_ACP_AWSIZE(1 downto 0),
SAXIACPAWUSER(4 downto 0) => S_AXI_ACP_AWUSER(4 downto 0),
SAXIACPAWVALID => S_AXI_ACP_AWVALID,
SAXIACPBID(2 downto 0) => S_AXI_ACP_BID(2 downto 0),
SAXIACPBREADY => S_AXI_ACP_BREADY,
SAXIACPBRESP(1 downto 0) => S_AXI_ACP_BRESP(1 downto 0),
SAXIACPBVALID => S_AXI_ACP_BVALID,
SAXIACPRDATA(63 downto 0) => S_AXI_ACP_RDATA(63 downto 0),
SAXIACPRID(2 downto 0) => S_AXI_ACP_RID(2 downto 0),
SAXIACPRLAST => S_AXI_ACP_RLAST,
SAXIACPRREADY => S_AXI_ACP_RREADY,
SAXIACPRRESP(1 downto 0) => S_AXI_ACP_RRESP(1 downto 0),
SAXIACPRVALID => S_AXI_ACP_RVALID,
SAXIACPWDATA(63 downto 0) => S_AXI_ACP_WDATA(63 downto 0),
SAXIACPWID(2 downto 0) => S_AXI_ACP_WID(2 downto 0),
SAXIACPWLAST => S_AXI_ACP_WLAST,
SAXIACPWREADY => S_AXI_ACP_WREADY,
SAXIACPWSTRB(7 downto 0) => S_AXI_ACP_WSTRB(7 downto 0),
SAXIACPWVALID => S_AXI_ACP_WVALID,
SAXIGP0ACLK => S_AXI_GP0_ACLK,
SAXIGP0ARADDR(31 downto 0) => S_AXI_GP0_ARADDR(31 downto 0),
SAXIGP0ARBURST(1 downto 0) => S_AXI_GP0_ARBURST(1 downto 0),
SAXIGP0ARCACHE(3 downto 0) => S_AXI_GP0_ARCACHE(3 downto 0),
SAXIGP0ARESETN => S_AXI_GP0_ARESETN,
SAXIGP0ARID(5 downto 0) => S_AXI_GP0_ARID(5 downto 0),
SAXIGP0ARLEN(3 downto 0) => S_AXI_GP0_ARLEN(3 downto 0),
SAXIGP0ARLOCK(1 downto 0) => S_AXI_GP0_ARLOCK(1 downto 0),
SAXIGP0ARPROT(2 downto 0) => S_AXI_GP0_ARPROT(2 downto 0),
SAXIGP0ARQOS(3 downto 0) => S_AXI_GP0_ARQOS(3 downto 0),
SAXIGP0ARREADY => S_AXI_GP0_ARREADY,
SAXIGP0ARSIZE(1 downto 0) => S_AXI_GP0_ARSIZE(1 downto 0),
SAXIGP0ARVALID => S_AXI_GP0_ARVALID,
SAXIGP0AWADDR(31 downto 0) => S_AXI_GP0_AWADDR(31 downto 0),
SAXIGP0AWBURST(1 downto 0) => S_AXI_GP0_AWBURST(1 downto 0),
SAXIGP0AWCACHE(3 downto 0) => S_AXI_GP0_AWCACHE(3 downto 0),
SAXIGP0AWID(5 downto 0) => S_AXI_GP0_AWID(5 downto 0),
SAXIGP0AWLEN(3 downto 0) => S_AXI_GP0_AWLEN(3 downto 0),
SAXIGP0AWLOCK(1 downto 0) => S_AXI_GP0_AWLOCK(1 downto 0),
SAXIGP0AWPROT(2 downto 0) => S_AXI_GP0_AWPROT(2 downto 0),
SAXIGP0AWQOS(3 downto 0) => S_AXI_GP0_AWQOS(3 downto 0),
SAXIGP0AWREADY => S_AXI_GP0_AWREADY,
SAXIGP0AWSIZE(1 downto 0) => S_AXI_GP0_AWSIZE(1 downto 0),
SAXIGP0AWVALID => S_AXI_GP0_AWVALID,
SAXIGP0BID(5 downto 0) => S_AXI_GP0_BID(5 downto 0),
SAXIGP0BREADY => S_AXI_GP0_BREADY,
SAXIGP0BRESP(1 downto 0) => S_AXI_GP0_BRESP(1 downto 0),
SAXIGP0BVALID => S_AXI_GP0_BVALID,
SAXIGP0RDATA(31 downto 0) => S_AXI_GP0_RDATA(31 downto 0),
SAXIGP0RID(5 downto 0) => S_AXI_GP0_RID(5 downto 0),
SAXIGP0RLAST => S_AXI_GP0_RLAST,
SAXIGP0RREADY => S_AXI_GP0_RREADY,
SAXIGP0RRESP(1 downto 0) => S_AXI_GP0_RRESP(1 downto 0),
SAXIGP0RVALID => S_AXI_GP0_RVALID,
SAXIGP0WDATA(31 downto 0) => S_AXI_GP0_WDATA(31 downto 0),
SAXIGP0WID(5 downto 0) => S_AXI_GP0_WID(5 downto 0),
SAXIGP0WLAST => S_AXI_GP0_WLAST,
SAXIGP0WREADY => S_AXI_GP0_WREADY,
SAXIGP0WSTRB(3 downto 0) => S_AXI_GP0_WSTRB(3 downto 0),
SAXIGP0WVALID => S_AXI_GP0_WVALID,
SAXIGP1ACLK => S_AXI_GP1_ACLK,
SAXIGP1ARADDR(31 downto 0) => S_AXI_GP1_ARADDR(31 downto 0),
SAXIGP1ARBURST(1 downto 0) => S_AXI_GP1_ARBURST(1 downto 0),
SAXIGP1ARCACHE(3 downto 0) => S_AXI_GP1_ARCACHE(3 downto 0),
SAXIGP1ARESETN => S_AXI_GP1_ARESETN,
SAXIGP1ARID(5 downto 0) => S_AXI_GP1_ARID(5 downto 0),
SAXIGP1ARLEN(3 downto 0) => S_AXI_GP1_ARLEN(3 downto 0),
SAXIGP1ARLOCK(1 downto 0) => S_AXI_GP1_ARLOCK(1 downto 0),
SAXIGP1ARPROT(2 downto 0) => S_AXI_GP1_ARPROT(2 downto 0),
SAXIGP1ARQOS(3 downto 0) => S_AXI_GP1_ARQOS(3 downto 0),
SAXIGP1ARREADY => S_AXI_GP1_ARREADY,
SAXIGP1ARSIZE(1 downto 0) => S_AXI_GP1_ARSIZE(1 downto 0),
SAXIGP1ARVALID => S_AXI_GP1_ARVALID,
SAXIGP1AWADDR(31 downto 0) => S_AXI_GP1_AWADDR(31 downto 0),
SAXIGP1AWBURST(1 downto 0) => S_AXI_GP1_AWBURST(1 downto 0),
SAXIGP1AWCACHE(3 downto 0) => S_AXI_GP1_AWCACHE(3 downto 0),
SAXIGP1AWID(5 downto 0) => S_AXI_GP1_AWID(5 downto 0),
SAXIGP1AWLEN(3 downto 0) => S_AXI_GP1_AWLEN(3 downto 0),
SAXIGP1AWLOCK(1 downto 0) => S_AXI_GP1_AWLOCK(1 downto 0),
SAXIGP1AWPROT(2 downto 0) => S_AXI_GP1_AWPROT(2 downto 0),
SAXIGP1AWQOS(3 downto 0) => S_AXI_GP1_AWQOS(3 downto 0),
SAXIGP1AWREADY => S_AXI_GP1_AWREADY,
SAXIGP1AWSIZE(1 downto 0) => S_AXI_GP1_AWSIZE(1 downto 0),
SAXIGP1AWVALID => S_AXI_GP1_AWVALID,
SAXIGP1BID(5 downto 0) => S_AXI_GP1_BID(5 downto 0),
SAXIGP1BREADY => S_AXI_GP1_BREADY,
SAXIGP1BRESP(1 downto 0) => S_AXI_GP1_BRESP(1 downto 0),
SAXIGP1BVALID => S_AXI_GP1_BVALID,
SAXIGP1RDATA(31 downto 0) => S_AXI_GP1_RDATA(31 downto 0),
SAXIGP1RID(5 downto 0) => S_AXI_GP1_RID(5 downto 0),
SAXIGP1RLAST => S_AXI_GP1_RLAST,
SAXIGP1RREADY => S_AXI_GP1_RREADY,
SAXIGP1RRESP(1 downto 0) => S_AXI_GP1_RRESP(1 downto 0),
SAXIGP1RVALID => S_AXI_GP1_RVALID,
SAXIGP1WDATA(31 downto 0) => S_AXI_GP1_WDATA(31 downto 0),
SAXIGP1WID(5 downto 0) => S_AXI_GP1_WID(5 downto 0),
SAXIGP1WLAST => S_AXI_GP1_WLAST,
SAXIGP1WREADY => S_AXI_GP1_WREADY,
SAXIGP1WSTRB(3 downto 0) => S_AXI_GP1_WSTRB(3 downto 0),
SAXIGP1WVALID => S_AXI_GP1_WVALID,
SAXIHP0ACLK => S_AXI_HP0_ACLK,
SAXIHP0ARADDR(31 downto 0) => S_AXI_HP0_ARADDR(31 downto 0),
SAXIHP0ARBURST(1 downto 0) => S_AXI_HP0_ARBURST(1 downto 0),
SAXIHP0ARCACHE(3 downto 0) => S_AXI_HP0_ARCACHE(3 downto 0),
SAXIHP0ARESETN => S_AXI_HP0_ARESETN,
SAXIHP0ARID(5 downto 0) => S_AXI_HP0_ARID(5 downto 0),
SAXIHP0ARLEN(3 downto 0) => S_AXI_HP0_ARLEN(3 downto 0),
SAXIHP0ARLOCK(1 downto 0) => S_AXI_HP0_ARLOCK(1 downto 0),
SAXIHP0ARPROT(2 downto 0) => S_AXI_HP0_ARPROT(2 downto 0),
SAXIHP0ARQOS(3 downto 0) => S_AXI_HP0_ARQOS(3 downto 0),
SAXIHP0ARREADY => S_AXI_HP0_ARREADY,
SAXIHP0ARSIZE(1 downto 0) => S_AXI_HP0_ARSIZE(1 downto 0),
SAXIHP0ARVALID => S_AXI_HP0_ARVALID,
SAXIHP0AWADDR(31 downto 0) => S_AXI_HP0_AWADDR(31 downto 0),
SAXIHP0AWBURST(1 downto 0) => S_AXI_HP0_AWBURST(1 downto 0),
SAXIHP0AWCACHE(3 downto 0) => S_AXI_HP0_AWCACHE(3 downto 0),
SAXIHP0AWID(5 downto 0) => S_AXI_HP0_AWID(5 downto 0),
SAXIHP0AWLEN(3 downto 0) => S_AXI_HP0_AWLEN(3 downto 0),
SAXIHP0AWLOCK(1 downto 0) => S_AXI_HP0_AWLOCK(1 downto 0),
SAXIHP0AWPROT(2 downto 0) => S_AXI_HP0_AWPROT(2 downto 0),
SAXIHP0AWQOS(3 downto 0) => S_AXI_HP0_AWQOS(3 downto 0),
SAXIHP0AWREADY => S_AXI_HP0_AWREADY,
SAXIHP0AWSIZE(1 downto 0) => S_AXI_HP0_AWSIZE(1 downto 0),
SAXIHP0AWVALID => S_AXI_HP0_AWVALID,
SAXIHP0BID(5 downto 0) => S_AXI_HP0_BID(5 downto 0),
SAXIHP0BREADY => S_AXI_HP0_BREADY,
SAXIHP0BRESP(1 downto 0) => S_AXI_HP0_BRESP(1 downto 0),
SAXIHP0BVALID => S_AXI_HP0_BVALID,
SAXIHP0RACOUNT(2 downto 0) => S_AXI_HP0_RACOUNT(2 downto 0),
SAXIHP0RCOUNT(7 downto 0) => S_AXI_HP0_RCOUNT(7 downto 0),
SAXIHP0RDATA(63 downto 0) => S_AXI_HP0_RDATA(63 downto 0),
SAXIHP0RDISSUECAP1EN => S_AXI_HP0_RDISSUECAP1_EN,
SAXIHP0RID(5 downto 0) => S_AXI_HP0_RID(5 downto 0),
SAXIHP0RLAST => S_AXI_HP0_RLAST,
SAXIHP0RREADY => S_AXI_HP0_RREADY,
SAXIHP0RRESP(1 downto 0) => S_AXI_HP0_RRESP(1 downto 0),
SAXIHP0RVALID => S_AXI_HP0_RVALID,
SAXIHP0WACOUNT(5 downto 0) => S_AXI_HP0_WACOUNT(5 downto 0),
SAXIHP0WCOUNT(7 downto 0) => S_AXI_HP0_WCOUNT(7 downto 0),
SAXIHP0WDATA(63 downto 0) => S_AXI_HP0_WDATA(63 downto 0),
SAXIHP0WID(5 downto 0) => S_AXI_HP0_WID(5 downto 0),
SAXIHP0WLAST => S_AXI_HP0_WLAST,
SAXIHP0WREADY => S_AXI_HP0_WREADY,
SAXIHP0WRISSUECAP1EN => S_AXI_HP0_WRISSUECAP1_EN,
SAXIHP0WSTRB(7 downto 0) => S_AXI_HP0_WSTRB(7 downto 0),
SAXIHP0WVALID => S_AXI_HP0_WVALID,
SAXIHP1ACLK => S_AXI_HP1_ACLK,
SAXIHP1ARADDR(31 downto 0) => S_AXI_HP1_ARADDR(31 downto 0),
SAXIHP1ARBURST(1 downto 0) => S_AXI_HP1_ARBURST(1 downto 0),
SAXIHP1ARCACHE(3 downto 0) => S_AXI_HP1_ARCACHE(3 downto 0),
SAXIHP1ARESETN => S_AXI_HP1_ARESETN,
SAXIHP1ARID(5 downto 0) => S_AXI_HP1_ARID(5 downto 0),
SAXIHP1ARLEN(3 downto 0) => S_AXI_HP1_ARLEN(3 downto 0),
SAXIHP1ARLOCK(1 downto 0) => S_AXI_HP1_ARLOCK(1 downto 0),
SAXIHP1ARPROT(2 downto 0) => S_AXI_HP1_ARPROT(2 downto 0),
SAXIHP1ARQOS(3 downto 0) => S_AXI_HP1_ARQOS(3 downto 0),
SAXIHP1ARREADY => S_AXI_HP1_ARREADY,
SAXIHP1ARSIZE(1 downto 0) => S_AXI_HP1_ARSIZE(1 downto 0),
SAXIHP1ARVALID => S_AXI_HP1_ARVALID,
SAXIHP1AWADDR(31 downto 0) => S_AXI_HP1_AWADDR(31 downto 0),
SAXIHP1AWBURST(1 downto 0) => S_AXI_HP1_AWBURST(1 downto 0),
SAXIHP1AWCACHE(3 downto 0) => S_AXI_HP1_AWCACHE(3 downto 0),
SAXIHP1AWID(5 downto 0) => S_AXI_HP1_AWID(5 downto 0),
SAXIHP1AWLEN(3 downto 0) => S_AXI_HP1_AWLEN(3 downto 0),
SAXIHP1AWLOCK(1 downto 0) => S_AXI_HP1_AWLOCK(1 downto 0),
SAXIHP1AWPROT(2 downto 0) => S_AXI_HP1_AWPROT(2 downto 0),
SAXIHP1AWQOS(3 downto 0) => S_AXI_HP1_AWQOS(3 downto 0),
SAXIHP1AWREADY => S_AXI_HP1_AWREADY,
SAXIHP1AWSIZE(1 downto 0) => S_AXI_HP1_AWSIZE(1 downto 0),
SAXIHP1AWVALID => S_AXI_HP1_AWVALID,
SAXIHP1BID(5 downto 0) => S_AXI_HP1_BID(5 downto 0),
SAXIHP1BREADY => S_AXI_HP1_BREADY,
SAXIHP1BRESP(1 downto 0) => S_AXI_HP1_BRESP(1 downto 0),
SAXIHP1BVALID => S_AXI_HP1_BVALID,
SAXIHP1RACOUNT(2 downto 0) => S_AXI_HP1_RACOUNT(2 downto 0),
SAXIHP1RCOUNT(7 downto 0) => S_AXI_HP1_RCOUNT(7 downto 0),
SAXIHP1RDATA(63 downto 0) => S_AXI_HP1_RDATA(63 downto 0),
SAXIHP1RDISSUECAP1EN => S_AXI_HP1_RDISSUECAP1_EN,
SAXIHP1RID(5 downto 0) => S_AXI_HP1_RID(5 downto 0),
SAXIHP1RLAST => S_AXI_HP1_RLAST,
SAXIHP1RREADY => S_AXI_HP1_RREADY,
SAXIHP1RRESP(1 downto 0) => S_AXI_HP1_RRESP(1 downto 0),
SAXIHP1RVALID => S_AXI_HP1_RVALID,
SAXIHP1WACOUNT(5 downto 0) => S_AXI_HP1_WACOUNT(5 downto 0),
SAXIHP1WCOUNT(7 downto 0) => S_AXI_HP1_WCOUNT(7 downto 0),
SAXIHP1WDATA(63 downto 0) => S_AXI_HP1_WDATA(63 downto 0),
SAXIHP1WID(5 downto 0) => S_AXI_HP1_WID(5 downto 0),
SAXIHP1WLAST => S_AXI_HP1_WLAST,
SAXIHP1WREADY => S_AXI_HP1_WREADY,
SAXIHP1WRISSUECAP1EN => S_AXI_HP1_WRISSUECAP1_EN,
SAXIHP1WSTRB(7 downto 0) => S_AXI_HP1_WSTRB(7 downto 0),
SAXIHP1WVALID => S_AXI_HP1_WVALID,
SAXIHP2ACLK => S_AXI_HP2_ACLK,
SAXIHP2ARADDR(31 downto 0) => S_AXI_HP2_ARADDR(31 downto 0),
SAXIHP2ARBURST(1 downto 0) => S_AXI_HP2_ARBURST(1 downto 0),
SAXIHP2ARCACHE(3 downto 0) => S_AXI_HP2_ARCACHE(3 downto 0),
SAXIHP2ARESETN => S_AXI_HP2_ARESETN,
SAXIHP2ARID(5 downto 0) => S_AXI_HP2_ARID(5 downto 0),
SAXIHP2ARLEN(3 downto 0) => S_AXI_HP2_ARLEN(3 downto 0),
SAXIHP2ARLOCK(1 downto 0) => S_AXI_HP2_ARLOCK(1 downto 0),
SAXIHP2ARPROT(2 downto 0) => S_AXI_HP2_ARPROT(2 downto 0),
SAXIHP2ARQOS(3 downto 0) => S_AXI_HP2_ARQOS(3 downto 0),
SAXIHP2ARREADY => S_AXI_HP2_ARREADY,
SAXIHP2ARSIZE(1 downto 0) => S_AXI_HP2_ARSIZE(1 downto 0),
SAXIHP2ARVALID => S_AXI_HP2_ARVALID,
SAXIHP2AWADDR(31 downto 0) => S_AXI_HP2_AWADDR(31 downto 0),
SAXIHP2AWBURST(1 downto 0) => S_AXI_HP2_AWBURST(1 downto 0),
SAXIHP2AWCACHE(3 downto 0) => S_AXI_HP2_AWCACHE(3 downto 0),
SAXIHP2AWID(5 downto 0) => S_AXI_HP2_AWID(5 downto 0),
SAXIHP2AWLEN(3 downto 0) => S_AXI_HP2_AWLEN(3 downto 0),
SAXIHP2AWLOCK(1 downto 0) => S_AXI_HP2_AWLOCK(1 downto 0),
SAXIHP2AWPROT(2 downto 0) => S_AXI_HP2_AWPROT(2 downto 0),
SAXIHP2AWQOS(3 downto 0) => S_AXI_HP2_AWQOS(3 downto 0),
SAXIHP2AWREADY => S_AXI_HP2_AWREADY,
SAXIHP2AWSIZE(1 downto 0) => S_AXI_HP2_AWSIZE(1 downto 0),
SAXIHP2AWVALID => S_AXI_HP2_AWVALID,
SAXIHP2BID(5 downto 0) => S_AXI_HP2_BID(5 downto 0),
SAXIHP2BREADY => S_AXI_HP2_BREADY,
SAXIHP2BRESP(1 downto 0) => S_AXI_HP2_BRESP(1 downto 0),
SAXIHP2BVALID => S_AXI_HP2_BVALID,
SAXIHP2RACOUNT(2 downto 0) => S_AXI_HP2_RACOUNT(2 downto 0),
SAXIHP2RCOUNT(7 downto 0) => S_AXI_HP2_RCOUNT(7 downto 0),
SAXIHP2RDATA(63 downto 0) => S_AXI_HP2_RDATA(63 downto 0),
SAXIHP2RDISSUECAP1EN => S_AXI_HP2_RDISSUECAP1_EN,
SAXIHP2RID(5 downto 0) => S_AXI_HP2_RID(5 downto 0),
SAXIHP2RLAST => S_AXI_HP2_RLAST,
SAXIHP2RREADY => S_AXI_HP2_RREADY,
SAXIHP2RRESP(1 downto 0) => S_AXI_HP2_RRESP(1 downto 0),
SAXIHP2RVALID => S_AXI_HP2_RVALID,
SAXIHP2WACOUNT(5 downto 0) => S_AXI_HP2_WACOUNT(5 downto 0),
SAXIHP2WCOUNT(7 downto 0) => S_AXI_HP2_WCOUNT(7 downto 0),
SAXIHP2WDATA(63 downto 0) => S_AXI_HP2_WDATA(63 downto 0),
SAXIHP2WID(5 downto 0) => S_AXI_HP2_WID(5 downto 0),
SAXIHP2WLAST => S_AXI_HP2_WLAST,
SAXIHP2WREADY => S_AXI_HP2_WREADY,
SAXIHP2WRISSUECAP1EN => S_AXI_HP2_WRISSUECAP1_EN,
SAXIHP2WSTRB(7 downto 0) => S_AXI_HP2_WSTRB(7 downto 0),
SAXIHP2WVALID => S_AXI_HP2_WVALID,
SAXIHP3ACLK => S_AXI_HP3_ACLK,
SAXIHP3ARADDR(31 downto 0) => S_AXI_HP3_ARADDR(31 downto 0),
SAXIHP3ARBURST(1 downto 0) => S_AXI_HP3_ARBURST(1 downto 0),
SAXIHP3ARCACHE(3 downto 0) => S_AXI_HP3_ARCACHE(3 downto 0),
SAXIHP3ARESETN => S_AXI_HP3_ARESETN,
SAXIHP3ARID(5 downto 0) => S_AXI_HP3_ARID(5 downto 0),
SAXIHP3ARLEN(3 downto 0) => S_AXI_HP3_ARLEN(3 downto 0),
SAXIHP3ARLOCK(1 downto 0) => S_AXI_HP3_ARLOCK(1 downto 0),
SAXIHP3ARPROT(2 downto 0) => S_AXI_HP3_ARPROT(2 downto 0),
SAXIHP3ARQOS(3 downto 0) => S_AXI_HP3_ARQOS(3 downto 0),
SAXIHP3ARREADY => S_AXI_HP3_ARREADY,
SAXIHP3ARSIZE(1 downto 0) => S_AXI_HP3_ARSIZE(1 downto 0),
SAXIHP3ARVALID => S_AXI_HP3_ARVALID,
SAXIHP3AWADDR(31 downto 0) => S_AXI_HP3_AWADDR(31 downto 0),
SAXIHP3AWBURST(1 downto 0) => S_AXI_HP3_AWBURST(1 downto 0),
SAXIHP3AWCACHE(3 downto 0) => S_AXI_HP3_AWCACHE(3 downto 0),
SAXIHP3AWID(5 downto 0) => S_AXI_HP3_AWID(5 downto 0),
SAXIHP3AWLEN(3 downto 0) => S_AXI_HP3_AWLEN(3 downto 0),
SAXIHP3AWLOCK(1 downto 0) => S_AXI_HP3_AWLOCK(1 downto 0),
SAXIHP3AWPROT(2 downto 0) => S_AXI_HP3_AWPROT(2 downto 0),
SAXIHP3AWQOS(3 downto 0) => S_AXI_HP3_AWQOS(3 downto 0),
SAXIHP3AWREADY => S_AXI_HP3_AWREADY,
SAXIHP3AWSIZE(1 downto 0) => S_AXI_HP3_AWSIZE(1 downto 0),
SAXIHP3AWVALID => S_AXI_HP3_AWVALID,
SAXIHP3BID(5 downto 0) => S_AXI_HP3_BID(5 downto 0),
SAXIHP3BREADY => S_AXI_HP3_BREADY,
SAXIHP3BRESP(1 downto 0) => S_AXI_HP3_BRESP(1 downto 0),
SAXIHP3BVALID => S_AXI_HP3_BVALID,
SAXIHP3RACOUNT(2 downto 0) => S_AXI_HP3_RACOUNT(2 downto 0),
SAXIHP3RCOUNT(7 downto 0) => S_AXI_HP3_RCOUNT(7 downto 0),
SAXIHP3RDATA(63 downto 0) => S_AXI_HP3_RDATA(63 downto 0),
SAXIHP3RDISSUECAP1EN => S_AXI_HP3_RDISSUECAP1_EN,
SAXIHP3RID(5 downto 0) => S_AXI_HP3_RID(5 downto 0),
SAXIHP3RLAST => S_AXI_HP3_RLAST,
SAXIHP3RREADY => S_AXI_HP3_RREADY,
SAXIHP3RRESP(1 downto 0) => S_AXI_HP3_RRESP(1 downto 0),
SAXIHP3RVALID => S_AXI_HP3_RVALID,
SAXIHP3WACOUNT(5 downto 0) => S_AXI_HP3_WACOUNT(5 downto 0),
SAXIHP3WCOUNT(7 downto 0) => S_AXI_HP3_WCOUNT(7 downto 0),
SAXIHP3WDATA(63 downto 0) => S_AXI_HP3_WDATA(63 downto 0),
SAXIHP3WID(5 downto 0) => S_AXI_HP3_WID(5 downto 0),
SAXIHP3WLAST => S_AXI_HP3_WLAST,
SAXIHP3WREADY => S_AXI_HP3_WREADY,
SAXIHP3WRISSUECAP1EN => S_AXI_HP3_WRISSUECAP1_EN,
SAXIHP3WSTRB(7 downto 0) => S_AXI_HP3_WSTRB(7 downto 0),
SAXIHP3WVALID => S_AXI_HP3_WVALID
);
PS_CLK_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_CLK,
PAD => PS_CLK
);
PS_PORB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_PORB,
PAD => PS_PORB
);
PS_SRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_SRSTB,
PAD => PS_SRSTB
);
SDIO0_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_CMD_T_n,
O => SDIO0_CMD_T
);
\SDIO0_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(0),
O => SDIO0_DATA_T(0)
);
\SDIO0_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(1),
O => SDIO0_DATA_T(1)
);
\SDIO0_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(2),
O => SDIO0_DATA_T(2)
);
\SDIO0_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(3),
O => SDIO0_DATA_T(3)
);
SDIO1_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_CMD_T_n,
O => SDIO1_CMD_T
);
\SDIO1_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(0),
O => SDIO1_DATA_T(0)
);
\SDIO1_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(1),
O => SDIO1_DATA_T(1)
);
\SDIO1_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(2),
O => SDIO1_DATA_T(2)
);
\SDIO1_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(3),
O => SDIO1_DATA_T(3)
);
SPI0_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MISO_T_n,
O => SPI0_MISO_T
);
SPI0_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MOSI_T_n,
O => SPI0_MOSI_T
);
SPI0_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SCLK_T_n,
O => SPI0_SCLK_T
);
SPI0_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SS_T_n,
O => SPI0_SS_T
);
SPI1_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MISO_T_n,
O => SPI1_MISO_T
);
SPI1_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MOSI_T_n,
O => SPI1_MOSI_T
);
SPI1_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SCLK_T_n,
O => SPI1_SCLK_T
);
SPI1_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SS_T_n,
O => SPI1_SS_T
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\genblk13[0].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(0),
PAD => MIO(0)
);
\genblk13[10].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(10),
PAD => MIO(10)
);
\genblk13[11].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(11),
PAD => MIO(11)
);
\genblk13[12].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(12),
PAD => MIO(12)
);
\genblk13[13].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(13),
PAD => MIO(13)
);
\genblk13[14].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(14),
PAD => MIO(14)
);
\genblk13[15].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(15),
PAD => MIO(15)
);
\genblk13[16].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(16),
PAD => MIO(16)
);
\genblk13[17].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(17),
PAD => MIO(17)
);
\genblk13[18].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(18),
PAD => MIO(18)
);
\genblk13[19].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(19),
PAD => MIO(19)
);
\genblk13[1].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(1),
PAD => MIO(1)
);
\genblk13[20].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(20),
PAD => MIO(20)
);
\genblk13[21].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(21),
PAD => MIO(21)
);
\genblk13[22].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(22),
PAD => MIO(22)
);
\genblk13[23].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(23),
PAD => MIO(23)
);
\genblk13[24].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(24),
PAD => MIO(24)
);
\genblk13[25].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(25),
PAD => MIO(25)
);
\genblk13[26].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(26),
PAD => MIO(26)
);
\genblk13[27].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(27),
PAD => MIO(27)
);
\genblk13[28].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(28),
PAD => MIO(28)
);
\genblk13[29].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(29),
PAD => MIO(29)
);
\genblk13[2].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(2),
PAD => MIO(2)
);
\genblk13[30].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(30),
PAD => MIO(30)
);
\genblk13[31].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(31),
PAD => MIO(31)
);
\genblk13[32].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(32),
PAD => MIO(32)
);
\genblk13[33].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(33),
PAD => MIO(33)
);
\genblk13[34].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(34),
PAD => MIO(34)
);
\genblk13[35].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(35),
PAD => MIO(35)
);
\genblk13[36].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(36),
PAD => MIO(36)
);
\genblk13[37].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(37),
PAD => MIO(37)
);
\genblk13[38].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(38),
PAD => MIO(38)
);
\genblk13[39].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(39),
PAD => MIO(39)
);
\genblk13[3].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(3),
PAD => MIO(3)
);
\genblk13[40].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(40),
PAD => MIO(40)
);
\genblk13[41].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(41),
PAD => MIO(41)
);
\genblk13[42].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(42),
PAD => MIO(42)
);
\genblk13[43].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(43),
PAD => MIO(43)
);
\genblk13[44].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(44),
PAD => MIO(44)
);
\genblk13[45].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(45),
PAD => MIO(45)
);
\genblk13[46].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(46),
PAD => MIO(46)
);
\genblk13[47].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(47),
PAD => MIO(47)
);
\genblk13[48].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(48),
PAD => MIO(48)
);
\genblk13[49].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(49),
PAD => MIO(49)
);
\genblk13[4].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(4),
PAD => MIO(4)
);
\genblk13[50].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(50),
PAD => MIO(50)
);
\genblk13[51].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(51),
PAD => MIO(51)
);
\genblk13[52].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(52),
PAD => MIO(52)
);
\genblk13[53].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(53),
PAD => MIO(53)
);
\genblk13[5].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(5),
PAD => MIO(5)
);
\genblk13[6].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(6),
PAD => MIO(6)
);
\genblk13[7].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(7),
PAD => MIO(7)
);
\genblk13[8].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(8),
PAD => MIO(8)
);
\genblk13[9].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(9),
PAD => MIO(9)
);
\genblk14[0].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(0),
PAD => DDR_BankAddr(0)
);
\genblk14[1].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(1),
PAD => DDR_BankAddr(1)
);
\genblk14[2].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(2),
PAD => DDR_BankAddr(2)
);
\genblk15[0].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(0),
PAD => DDR_Addr(0)
);
\genblk15[10].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(10),
PAD => DDR_Addr(10)
);
\genblk15[11].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(11),
PAD => DDR_Addr(11)
);
\genblk15[12].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(12),
PAD => DDR_Addr(12)
);
\genblk15[13].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(13),
PAD => DDR_Addr(13)
);
\genblk15[14].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(14),
PAD => DDR_Addr(14)
);
\genblk15[1].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(1),
PAD => DDR_Addr(1)
);
\genblk15[2].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(2),
PAD => DDR_Addr(2)
);
\genblk15[3].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(3),
PAD => DDR_Addr(3)
);
\genblk15[4].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(4),
PAD => DDR_Addr(4)
);
\genblk15[5].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(5),
PAD => DDR_Addr(5)
);
\genblk15[6].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(6),
PAD => DDR_Addr(6)
);
\genblk15[7].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(7),
PAD => DDR_Addr(7)
);
\genblk15[8].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(8),
PAD => DDR_Addr(8)
);
\genblk15[9].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(9),
PAD => DDR_Addr(9)
);
\genblk16[0].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(0),
PAD => DDR_DM(0)
);
\genblk16[1].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(1),
PAD => DDR_DM(1)
);
\genblk16[2].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(2),
PAD => DDR_DM(2)
);
\genblk16[3].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(3),
PAD => DDR_DM(3)
);
\genblk17[0].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(0),
PAD => DDR_DQ(0)
);
\genblk17[10].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(10),
PAD => DDR_DQ(10)
);
\genblk17[11].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(11),
PAD => DDR_DQ(11)
);
\genblk17[12].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(12),
PAD => DDR_DQ(12)
);
\genblk17[13].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(13),
PAD => DDR_DQ(13)
);
\genblk17[14].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(14),
PAD => DDR_DQ(14)
);
\genblk17[15].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(15),
PAD => DDR_DQ(15)
);
\genblk17[16].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(16),
PAD => DDR_DQ(16)
);
\genblk17[17].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(17),
PAD => DDR_DQ(17)
);
\genblk17[18].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(18),
PAD => DDR_DQ(18)
);
\genblk17[19].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(19),
PAD => DDR_DQ(19)
);
\genblk17[1].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(1),
PAD => DDR_DQ(1)
);
\genblk17[20].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(20),
PAD => DDR_DQ(20)
);
\genblk17[21].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(21),
PAD => DDR_DQ(21)
);
\genblk17[22].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(22),
PAD => DDR_DQ(22)
);
\genblk17[23].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(23),
PAD => DDR_DQ(23)
);
\genblk17[24].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(24),
PAD => DDR_DQ(24)
);
\genblk17[25].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(25),
PAD => DDR_DQ(25)
);
\genblk17[26].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(26),
PAD => DDR_DQ(26)
);
\genblk17[27].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(27),
PAD => DDR_DQ(27)
);
\genblk17[28].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(28),
PAD => DDR_DQ(28)
);
\genblk17[29].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(29),
PAD => DDR_DQ(29)
);
\genblk17[2].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(2),
PAD => DDR_DQ(2)
);
\genblk17[30].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(30),
PAD => DDR_DQ(30)
);
\genblk17[31].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(31),
PAD => DDR_DQ(31)
);
\genblk17[3].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(3),
PAD => DDR_DQ(3)
);
\genblk17[4].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(4),
PAD => DDR_DQ(4)
);
\genblk17[5].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(5),
PAD => DDR_DQ(5)
);
\genblk17[6].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(6),
PAD => DDR_DQ(6)
);
\genblk17[7].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(7),
PAD => DDR_DQ(7)
);
\genblk17[8].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(8),
PAD => DDR_DQ(8)
);
\genblk17[9].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(9),
PAD => DDR_DQ(9)
);
\genblk18[0].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(0),
PAD => DDR_DQS_n(0)
);
\genblk18[1].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(1),
PAD => DDR_DQS_n(1)
);
\genblk18[2].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(2),
PAD => DDR_DQS_n(2)
);
\genblk18[3].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(3),
PAD => DDR_DQS_n(3)
);
\genblk19[0].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(0),
PAD => DDR_DQS(0)
);
\genblk19[1].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(1),
PAD => DDR_DQS(1)
);
\genblk19[2].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(2),
PAD => DDR_DQS(2)
);
\genblk19[3].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(3),
PAD => DDR_DQS(3)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[0]\
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(1)
);
i_10: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(1)
);
i_11: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(0)
);
i_12: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(1)
);
i_13: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(0)
);
i_14: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(1)
);
i_15: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(0)
);
i_16: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(1)
);
i_17: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(0)
);
i_18: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(1)
);
i_19: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(0)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(0)
);
i_20: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(1)
);
i_21: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(0)
);
i_22: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(1)
);
i_23: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(0)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[7]\
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[6]\
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[5]\
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[4]\
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[3]\
);
i_8: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[2]\
);
i_9: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_processing_system7_0_0 is
port (
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of design_1_processing_system7_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of design_1_processing_system7_0_0 : entity is "design_1_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of design_1_processing_system7_0_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of design_1_processing_system7_0_0 : entity is "processing_system7_v5_5_processing_system7,Vivado 2017.4.1";
end design_1_processing_system7_0_0;
architecture STRUCTURE of design_1_processing_system7_0_0 is
signal NLW_inst_CAN0_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_CAN1_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_EVENT_EVENTO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET3_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CTI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_GPIO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_QSPI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SMC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP0_ARVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP0_AWVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP0_BREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP0_RREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP0_WLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP0_WVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_PJTAG_TDO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CLK_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CTL_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_WDT_RST_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA1_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA2_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA3_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_ENET0_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_ENET1_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_EVENT_STANDBYWFE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_EVENT_STANDBYWFI_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_GPIO_O_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_GPIO_T_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_M_AXI_GP0_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP0_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP0_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP0_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP0_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP0_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP0_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP0_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP0_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP0_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP0_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP0_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP0_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP0_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP0_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP0_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP0_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP0_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP0_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP0_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP0_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO0_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO1_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_S_AXI_ACP_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_ACP_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP2_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP3_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_TRACE_DATA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_USB1_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of inst : label is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of inst : label is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of inst : label is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of inst : label is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of inst : label is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of inst : label is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of inst : label is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of inst : label is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of inst : label is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of inst : label is 1;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of inst : label is 1;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of inst : label is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of inst : label is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of inst : label is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of inst : label is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of inst : label is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of inst : label is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of inst : label is "clg400";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of inst : label is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of inst : label is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of inst : label is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of inst : label is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of inst : label is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of inst : label is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of inst : label is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of inst : label is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of inst : label is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of inst : label is 0;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of inst : label is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of inst : label is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of inst : label is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of inst : label is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of inst : label is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of inst : label is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of inst : label is "design_1_processing_system7_0_0.hwdef";
attribute POWER : string;
attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={867} load={0.5} /><MEMORY name={code} memType={LPDDR2} dataWidth={32} clockFreq={400} readRate={0.5} writeRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={49.999947} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={6} ioBank={Vcco_p1} clockFreq={99.999893} usageRate={0.5} /><PLL domain={Processor} vco={1733.332} /><PLL domain={Memory} vco={1599.998} /><PLL domain={IO} vco={1999.998} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0;
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of DDR_CAS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CAS_N";
attribute X_INTERFACE_INFO of DDR_CKE : signal is "xilinx.com:interface:ddrx:1.0 DDR CKE";
attribute X_INTERFACE_INFO of DDR_CS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CS_N";
attribute X_INTERFACE_INFO of DDR_Clk : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_P";
attribute X_INTERFACE_INFO of DDR_Clk_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_N";
attribute X_INTERFACE_INFO of DDR_DRSTB : signal is "xilinx.com:interface:ddrx:1.0 DDR RESET_N";
attribute X_INTERFACE_INFO of DDR_ODT : signal is "xilinx.com:interface:ddrx:1.0 DDR ODT";
attribute X_INTERFACE_INFO of DDR_RAS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR RAS_N";
attribute X_INTERFACE_INFO of DDR_VRN : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN";
attribute X_INTERFACE_INFO of DDR_VRP : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP";
attribute X_INTERFACE_INFO of DDR_WEB : signal is "xilinx.com:interface:ddrx:1.0 DDR WE_N";
attribute X_INTERFACE_INFO of FCLK_RESET0_N : signal is "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of FCLK_RESET0_N : signal is "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW";
attribute X_INTERFACE_INFO of PS_CLK : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK";
attribute X_INTERFACE_INFO of PS_PORB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB";
attribute X_INTERFACE_PARAMETER of PS_PORB : signal is "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false";
attribute X_INTERFACE_INFO of PS_SRSTB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB";
attribute X_INTERFACE_INFO of DDR_Addr : signal is "xilinx.com:interface:ddrx:1.0 DDR ADDR";
attribute X_INTERFACE_INFO of DDR_BankAddr : signal is "xilinx.com:interface:ddrx:1.0 DDR BA";
attribute X_INTERFACE_INFO of DDR_DM : signal is "xilinx.com:interface:ddrx:1.0 DDR DM";
attribute X_INTERFACE_INFO of DDR_DQ : signal is "xilinx.com:interface:ddrx:1.0 DDR DQ";
attribute X_INTERFACE_INFO of DDR_DQS : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_P";
attribute X_INTERFACE_PARAMETER of DDR_DQS : signal is "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11";
attribute X_INTERFACE_INFO of DDR_DQS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_N";
attribute X_INTERFACE_INFO of MIO : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO";
begin
inst: entity work.design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7
port map (
CAN0_PHY_RX => '0',
CAN0_PHY_TX => NLW_inst_CAN0_PHY_TX_UNCONNECTED,
CAN1_PHY_RX => '0',
CAN1_PHY_TX => NLW_inst_CAN1_PHY_TX_UNCONNECTED,
Core0_nFIQ => '0',
Core0_nIRQ => '0',
Core1_nFIQ => '0',
Core1_nIRQ => '0',
DDR_ARB(3 downto 0) => B"0000",
DDR_Addr(14 downto 0) => DDR_Addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_BankAddr(2 downto 0),
DDR_CAS_n => DDR_CAS_n,
DDR_CKE => DDR_CKE,
DDR_CS_n => DDR_CS_n,
DDR_Clk => DDR_Clk,
DDR_Clk_n => DDR_Clk_n,
DDR_DM(3 downto 0) => DDR_DM(3 downto 0),
DDR_DQ(31 downto 0) => DDR_DQ(31 downto 0),
DDR_DQS(3 downto 0) => DDR_DQS(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_DQS_n(3 downto 0),
DDR_DRSTB => DDR_DRSTB,
DDR_ODT => DDR_ODT,
DDR_RAS_n => DDR_RAS_n,
DDR_VRN => DDR_VRN,
DDR_VRP => DDR_VRP,
DDR_WEB => DDR_WEB,
DMA0_ACLK => '0',
DMA0_DAREADY => '0',
DMA0_DATYPE(1 downto 0) => NLW_inst_DMA0_DATYPE_UNCONNECTED(1 downto 0),
DMA0_DAVALID => NLW_inst_DMA0_DAVALID_UNCONNECTED,
DMA0_DRLAST => '0',
DMA0_DRREADY => NLW_inst_DMA0_DRREADY_UNCONNECTED,
DMA0_DRTYPE(1 downto 0) => B"00",
DMA0_DRVALID => '0',
DMA0_RSTN => NLW_inst_DMA0_RSTN_UNCONNECTED,
DMA1_ACLK => '0',
DMA1_DAREADY => '0',
DMA1_DATYPE(1 downto 0) => NLW_inst_DMA1_DATYPE_UNCONNECTED(1 downto 0),
DMA1_DAVALID => NLW_inst_DMA1_DAVALID_UNCONNECTED,
DMA1_DRLAST => '0',
DMA1_DRREADY => NLW_inst_DMA1_DRREADY_UNCONNECTED,
DMA1_DRTYPE(1 downto 0) => B"00",
DMA1_DRVALID => '0',
DMA1_RSTN => NLW_inst_DMA1_RSTN_UNCONNECTED,
DMA2_ACLK => '0',
DMA2_DAREADY => '0',
DMA2_DATYPE(1 downto 0) => NLW_inst_DMA2_DATYPE_UNCONNECTED(1 downto 0),
DMA2_DAVALID => NLW_inst_DMA2_DAVALID_UNCONNECTED,
DMA2_DRLAST => '0',
DMA2_DRREADY => NLW_inst_DMA2_DRREADY_UNCONNECTED,
DMA2_DRTYPE(1 downto 0) => B"00",
DMA2_DRVALID => '0',
DMA2_RSTN => NLW_inst_DMA2_RSTN_UNCONNECTED,
DMA3_ACLK => '0',
DMA3_DAREADY => '0',
DMA3_DATYPE(1 downto 0) => NLW_inst_DMA3_DATYPE_UNCONNECTED(1 downto 0),
DMA3_DAVALID => NLW_inst_DMA3_DAVALID_UNCONNECTED,
DMA3_DRLAST => '0',
DMA3_DRREADY => NLW_inst_DMA3_DRREADY_UNCONNECTED,
DMA3_DRTYPE(1 downto 0) => B"00",
DMA3_DRVALID => '0',
DMA3_RSTN => NLW_inst_DMA3_RSTN_UNCONNECTED,
ENET0_EXT_INTIN => '0',
ENET0_GMII_COL => '0',
ENET0_GMII_CRS => '0',
ENET0_GMII_RXD(7 downto 0) => B"00000000",
ENET0_GMII_RX_CLK => '0',
ENET0_GMII_RX_DV => '0',
ENET0_GMII_RX_ER => '0',
ENET0_GMII_TXD(7 downto 0) => NLW_inst_ENET0_GMII_TXD_UNCONNECTED(7 downto 0),
ENET0_GMII_TX_CLK => '0',
ENET0_GMII_TX_EN => NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED,
ENET0_GMII_TX_ER => NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED,
ENET0_MDIO_I => '0',
ENET0_MDIO_MDC => NLW_inst_ENET0_MDIO_MDC_UNCONNECTED,
ENET0_MDIO_O => NLW_inst_ENET0_MDIO_O_UNCONNECTED,
ENET0_MDIO_T => NLW_inst_ENET0_MDIO_T_UNCONNECTED,
ENET0_PTP_DELAY_REQ_RX => NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_DELAY_REQ_TX => NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_RX => NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_TX => NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_RX => NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_TX => NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_RX => NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_TX => NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET0_SOF_RX => NLW_inst_ENET0_SOF_RX_UNCONNECTED,
ENET0_SOF_TX => NLW_inst_ENET0_SOF_TX_UNCONNECTED,
ENET1_EXT_INTIN => '0',
ENET1_GMII_COL => '0',
ENET1_GMII_CRS => '0',
ENET1_GMII_RXD(7 downto 0) => B"00000000",
ENET1_GMII_RX_CLK => '0',
ENET1_GMII_RX_DV => '0',
ENET1_GMII_RX_ER => '0',
ENET1_GMII_TXD(7 downto 0) => NLW_inst_ENET1_GMII_TXD_UNCONNECTED(7 downto 0),
ENET1_GMII_TX_CLK => '0',
ENET1_GMII_TX_EN => NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED,
ENET1_GMII_TX_ER => NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED,
ENET1_MDIO_I => '0',
ENET1_MDIO_MDC => NLW_inst_ENET1_MDIO_MDC_UNCONNECTED,
ENET1_MDIO_O => NLW_inst_ENET1_MDIO_O_UNCONNECTED,
ENET1_MDIO_T => NLW_inst_ENET1_MDIO_T_UNCONNECTED,
ENET1_PTP_DELAY_REQ_RX => NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_DELAY_REQ_TX => NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_RX => NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_TX => NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_RX => NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_TX => NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_RX => NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_TX => NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET1_SOF_RX => NLW_inst_ENET1_SOF_RX_UNCONNECTED,
ENET1_SOF_TX => NLW_inst_ENET1_SOF_TX_UNCONNECTED,
EVENT_EVENTI => '0',
EVENT_EVENTO => NLW_inst_EVENT_EVENTO_UNCONNECTED,
EVENT_STANDBYWFE(1 downto 0) => NLW_inst_EVENT_STANDBYWFE_UNCONNECTED(1 downto 0),
EVENT_STANDBYWFI(1 downto 0) => NLW_inst_EVENT_STANDBYWFI_UNCONNECTED(1 downto 0),
FCLK_CLK0 => NLW_inst_FCLK_CLK0_UNCONNECTED,
FCLK_CLK1 => NLW_inst_FCLK_CLK1_UNCONNECTED,
FCLK_CLK2 => NLW_inst_FCLK_CLK2_UNCONNECTED,
FCLK_CLK3 => NLW_inst_FCLK_CLK3_UNCONNECTED,
FCLK_CLKTRIG0_N => '0',
FCLK_CLKTRIG1_N => '0',
FCLK_CLKTRIG2_N => '0',
FCLK_CLKTRIG3_N => '0',
FCLK_RESET0_N => FCLK_RESET0_N,
FCLK_RESET1_N => NLW_inst_FCLK_RESET1_N_UNCONNECTED,
FCLK_RESET2_N => NLW_inst_FCLK_RESET2_N_UNCONNECTED,
FCLK_RESET3_N => NLW_inst_FCLK_RESET3_N_UNCONNECTED,
FPGA_IDLE_N => '0',
FTMD_TRACEIN_ATID(3 downto 0) => B"0000",
FTMD_TRACEIN_CLK => '0',
FTMD_TRACEIN_DATA(31 downto 0) => B"00000000000000000000000000000000",
FTMD_TRACEIN_VALID => '0',
FTMT_F2P_DEBUG(31 downto 0) => B"00000000000000000000000000000000",
FTMT_F2P_TRIGACK_0 => NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED,
FTMT_F2P_TRIGACK_1 => NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED,
FTMT_F2P_TRIGACK_2 => NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED,
FTMT_F2P_TRIGACK_3 => NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED,
FTMT_F2P_TRIG_0 => '0',
FTMT_F2P_TRIG_1 => '0',
FTMT_F2P_TRIG_2 => '0',
FTMT_F2P_TRIG_3 => '0',
FTMT_P2F_DEBUG(31 downto 0) => NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED(31 downto 0),
FTMT_P2F_TRIGACK_0 => '0',
FTMT_P2F_TRIGACK_1 => '0',
FTMT_P2F_TRIGACK_2 => '0',
FTMT_P2F_TRIGACK_3 => '0',
FTMT_P2F_TRIG_0 => NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED,
FTMT_P2F_TRIG_1 => NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED,
FTMT_P2F_TRIG_2 => NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED,
FTMT_P2F_TRIG_3 => NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED,
GPIO_I(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
GPIO_O(63 downto 0) => NLW_inst_GPIO_O_UNCONNECTED(63 downto 0),
GPIO_T(63 downto 0) => NLW_inst_GPIO_T_UNCONNECTED(63 downto 0),
I2C0_SCL_I => '0',
I2C0_SCL_O => NLW_inst_I2C0_SCL_O_UNCONNECTED,
I2C0_SCL_T => NLW_inst_I2C0_SCL_T_UNCONNECTED,
I2C0_SDA_I => '0',
I2C0_SDA_O => NLW_inst_I2C0_SDA_O_UNCONNECTED,
I2C0_SDA_T => NLW_inst_I2C0_SDA_T_UNCONNECTED,
I2C1_SCL_I => '0',
I2C1_SCL_O => NLW_inst_I2C1_SCL_O_UNCONNECTED,
I2C1_SCL_T => NLW_inst_I2C1_SCL_T_UNCONNECTED,
I2C1_SDA_I => '0',
I2C1_SDA_O => NLW_inst_I2C1_SDA_O_UNCONNECTED,
I2C1_SDA_T => NLW_inst_I2C1_SDA_T_UNCONNECTED,
IRQ_F2P(0) => '0',
IRQ_P2F_CAN0 => NLW_inst_IRQ_P2F_CAN0_UNCONNECTED,
IRQ_P2F_CAN1 => NLW_inst_IRQ_P2F_CAN1_UNCONNECTED,
IRQ_P2F_CTI => NLW_inst_IRQ_P2F_CTI_UNCONNECTED,
IRQ_P2F_DMAC0 => NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED,
IRQ_P2F_DMAC1 => NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED,
IRQ_P2F_DMAC2 => NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED,
IRQ_P2F_DMAC3 => NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED,
IRQ_P2F_DMAC4 => NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED,
IRQ_P2F_DMAC5 => NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED,
IRQ_P2F_DMAC6 => NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED,
IRQ_P2F_DMAC7 => NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED,
IRQ_P2F_DMAC_ABORT => NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED,
IRQ_P2F_ENET0 => NLW_inst_IRQ_P2F_ENET0_UNCONNECTED,
IRQ_P2F_ENET1 => NLW_inst_IRQ_P2F_ENET1_UNCONNECTED,
IRQ_P2F_ENET_WAKE0 => NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED,
IRQ_P2F_ENET_WAKE1 => NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED,
IRQ_P2F_GPIO => NLW_inst_IRQ_P2F_GPIO_UNCONNECTED,
IRQ_P2F_I2C0 => NLW_inst_IRQ_P2F_I2C0_UNCONNECTED,
IRQ_P2F_I2C1 => NLW_inst_IRQ_P2F_I2C1_UNCONNECTED,
IRQ_P2F_QSPI => NLW_inst_IRQ_P2F_QSPI_UNCONNECTED,
IRQ_P2F_SDIO0 => NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED,
IRQ_P2F_SDIO1 => NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED,
IRQ_P2F_SMC => NLW_inst_IRQ_P2F_SMC_UNCONNECTED,
IRQ_P2F_SPI0 => NLW_inst_IRQ_P2F_SPI0_UNCONNECTED,
IRQ_P2F_SPI1 => NLW_inst_IRQ_P2F_SPI1_UNCONNECTED,
IRQ_P2F_UART0 => NLW_inst_IRQ_P2F_UART0_UNCONNECTED,
IRQ_P2F_UART1 => NLW_inst_IRQ_P2F_UART1_UNCONNECTED,
IRQ_P2F_USB0 => NLW_inst_IRQ_P2F_USB0_UNCONNECTED,
IRQ_P2F_USB1 => NLW_inst_IRQ_P2F_USB1_UNCONNECTED,
MIO(53 downto 0) => MIO(53 downto 0),
M_AXI_GP0_ACLK => '0',
M_AXI_GP0_ARADDR(31 downto 0) => NLW_inst_M_AXI_GP0_ARADDR_UNCONNECTED(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => NLW_inst_M_AXI_GP0_ARBURST_UNCONNECTED(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => NLW_inst_M_AXI_GP0_ARCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP0_ARESETN => NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED,
M_AXI_GP0_ARID(11 downto 0) => NLW_inst_M_AXI_GP0_ARID_UNCONNECTED(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => NLW_inst_M_AXI_GP0_ARLEN_UNCONNECTED(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => NLW_inst_M_AXI_GP0_ARLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => NLW_inst_M_AXI_GP0_ARPROT_UNCONNECTED(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => NLW_inst_M_AXI_GP0_ARQOS_UNCONNECTED(3 downto 0),
M_AXI_GP0_ARREADY => '0',
M_AXI_GP0_ARSIZE(2 downto 0) => NLW_inst_M_AXI_GP0_ARSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP0_ARVALID => NLW_inst_M_AXI_GP0_ARVALID_UNCONNECTED,
M_AXI_GP0_AWADDR(31 downto 0) => NLW_inst_M_AXI_GP0_AWADDR_UNCONNECTED(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => NLW_inst_M_AXI_GP0_AWBURST_UNCONNECTED(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => NLW_inst_M_AXI_GP0_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => NLW_inst_M_AXI_GP0_AWID_UNCONNECTED(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => NLW_inst_M_AXI_GP0_AWLEN_UNCONNECTED(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => NLW_inst_M_AXI_GP0_AWLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => NLW_inst_M_AXI_GP0_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => NLW_inst_M_AXI_GP0_AWQOS_UNCONNECTED(3 downto 0),
M_AXI_GP0_AWREADY => '0',
M_AXI_GP0_AWSIZE(2 downto 0) => NLW_inst_M_AXI_GP0_AWSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP0_AWVALID => NLW_inst_M_AXI_GP0_AWVALID_UNCONNECTED,
M_AXI_GP0_BID(11 downto 0) => B"000000000000",
M_AXI_GP0_BREADY => NLW_inst_M_AXI_GP0_BREADY_UNCONNECTED,
M_AXI_GP0_BRESP(1 downto 0) => B"00",
M_AXI_GP0_BVALID => '0',
M_AXI_GP0_RDATA(31 downto 0) => B"00000000000000000000000000000000",
M_AXI_GP0_RID(11 downto 0) => B"000000000000",
M_AXI_GP0_RLAST => '0',
M_AXI_GP0_RREADY => NLW_inst_M_AXI_GP0_RREADY_UNCONNECTED,
M_AXI_GP0_RRESP(1 downto 0) => B"00",
M_AXI_GP0_RVALID => '0',
M_AXI_GP0_WDATA(31 downto 0) => NLW_inst_M_AXI_GP0_WDATA_UNCONNECTED(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => NLW_inst_M_AXI_GP0_WID_UNCONNECTED(11 downto 0),
M_AXI_GP0_WLAST => NLW_inst_M_AXI_GP0_WLAST_UNCONNECTED,
M_AXI_GP0_WREADY => '0',
M_AXI_GP0_WSTRB(3 downto 0) => NLW_inst_M_AXI_GP0_WSTRB_UNCONNECTED(3 downto 0),
M_AXI_GP0_WVALID => NLW_inst_M_AXI_GP0_WVALID_UNCONNECTED,
M_AXI_GP1_ACLK => '0',
M_AXI_GP1_ARADDR(31 downto 0) => NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_ARBURST(1 downto 0) => NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARESETN => NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED,
M_AXI_GP1_ARID(11 downto 0) => NLW_inst_M_AXI_GP1_ARID_UNCONNECTED(11 downto 0),
M_AXI_GP1_ARLEN(3 downto 0) => NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARPROT(2 downto 0) => NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARQOS(3 downto 0) => NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARREADY => '0',
M_AXI_GP1_ARSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARVALID => NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED,
M_AXI_GP1_AWADDR(31 downto 0) => NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_AWBURST(1 downto 0) => NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWID(11 downto 0) => NLW_inst_M_AXI_GP1_AWID_UNCONNECTED(11 downto 0),
M_AXI_GP1_AWLEN(3 downto 0) => NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWPROT(2 downto 0) => NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWQOS(3 downto 0) => NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWREADY => '0',
M_AXI_GP1_AWSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWVALID => NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED,
M_AXI_GP1_BID(11 downto 0) => B"000000000000",
M_AXI_GP1_BREADY => NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED,
M_AXI_GP1_BRESP(1 downto 0) => B"00",
M_AXI_GP1_BVALID => '0',
M_AXI_GP1_RDATA(31 downto 0) => B"00000000000000000000000000000000",
M_AXI_GP1_RID(11 downto 0) => B"000000000000",
M_AXI_GP1_RLAST => '0',
M_AXI_GP1_RREADY => NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED,
M_AXI_GP1_RRESP(1 downto 0) => B"00",
M_AXI_GP1_RVALID => '0',
M_AXI_GP1_WDATA(31 downto 0) => NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED(31 downto 0),
M_AXI_GP1_WID(11 downto 0) => NLW_inst_M_AXI_GP1_WID_UNCONNECTED(11 downto 0),
M_AXI_GP1_WLAST => NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED,
M_AXI_GP1_WREADY => '0',
M_AXI_GP1_WSTRB(3 downto 0) => NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED(3 downto 0),
M_AXI_GP1_WVALID => NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED,
PJTAG_TCK => '0',
PJTAG_TDI => '0',
PJTAG_TDO => NLW_inst_PJTAG_TDO_UNCONNECTED,
PJTAG_TMS => '0',
PS_CLK => PS_CLK,
PS_PORB => PS_PORB,
PS_SRSTB => PS_SRSTB,
SDIO0_BUSPOW => NLW_inst_SDIO0_BUSPOW_UNCONNECTED,
SDIO0_BUSVOLT(2 downto 0) => NLW_inst_SDIO0_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO0_CDN => '0',
SDIO0_CLK => NLW_inst_SDIO0_CLK_UNCONNECTED,
SDIO0_CLK_FB => '0',
SDIO0_CMD_I => '0',
SDIO0_CMD_O => NLW_inst_SDIO0_CMD_O_UNCONNECTED,
SDIO0_CMD_T => NLW_inst_SDIO0_CMD_T_UNCONNECTED,
SDIO0_DATA_I(3 downto 0) => B"0000",
SDIO0_DATA_O(3 downto 0) => NLW_inst_SDIO0_DATA_O_UNCONNECTED(3 downto 0),
SDIO0_DATA_T(3 downto 0) => NLW_inst_SDIO0_DATA_T_UNCONNECTED(3 downto 0),
SDIO0_LED => NLW_inst_SDIO0_LED_UNCONNECTED,
SDIO0_WP => '0',
SDIO1_BUSPOW => NLW_inst_SDIO1_BUSPOW_UNCONNECTED,
SDIO1_BUSVOLT(2 downto 0) => NLW_inst_SDIO1_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO1_CDN => '0',
SDIO1_CLK => NLW_inst_SDIO1_CLK_UNCONNECTED,
SDIO1_CLK_FB => '0',
SDIO1_CMD_I => '0',
SDIO1_CMD_O => NLW_inst_SDIO1_CMD_O_UNCONNECTED,
SDIO1_CMD_T => NLW_inst_SDIO1_CMD_T_UNCONNECTED,
SDIO1_DATA_I(3 downto 0) => B"0000",
SDIO1_DATA_O(3 downto 0) => NLW_inst_SDIO1_DATA_O_UNCONNECTED(3 downto 0),
SDIO1_DATA_T(3 downto 0) => NLW_inst_SDIO1_DATA_T_UNCONNECTED(3 downto 0),
SDIO1_LED => NLW_inst_SDIO1_LED_UNCONNECTED,
SDIO1_WP => '0',
SPI0_MISO_I => '0',
SPI0_MISO_O => NLW_inst_SPI0_MISO_O_UNCONNECTED,
SPI0_MISO_T => NLW_inst_SPI0_MISO_T_UNCONNECTED,
SPI0_MOSI_I => '0',
SPI0_MOSI_O => NLW_inst_SPI0_MOSI_O_UNCONNECTED,
SPI0_MOSI_T => NLW_inst_SPI0_MOSI_T_UNCONNECTED,
SPI0_SCLK_I => '0',
SPI0_SCLK_O => NLW_inst_SPI0_SCLK_O_UNCONNECTED,
SPI0_SCLK_T => NLW_inst_SPI0_SCLK_T_UNCONNECTED,
SPI0_SS1_O => NLW_inst_SPI0_SS1_O_UNCONNECTED,
SPI0_SS2_O => NLW_inst_SPI0_SS2_O_UNCONNECTED,
SPI0_SS_I => '0',
SPI0_SS_O => NLW_inst_SPI0_SS_O_UNCONNECTED,
SPI0_SS_T => NLW_inst_SPI0_SS_T_UNCONNECTED,
SPI1_MISO_I => '0',
SPI1_MISO_O => NLW_inst_SPI1_MISO_O_UNCONNECTED,
SPI1_MISO_T => NLW_inst_SPI1_MISO_T_UNCONNECTED,
SPI1_MOSI_I => '0',
SPI1_MOSI_O => NLW_inst_SPI1_MOSI_O_UNCONNECTED,
SPI1_MOSI_T => NLW_inst_SPI1_MOSI_T_UNCONNECTED,
SPI1_SCLK_I => '0',
SPI1_SCLK_O => NLW_inst_SPI1_SCLK_O_UNCONNECTED,
SPI1_SCLK_T => NLW_inst_SPI1_SCLK_T_UNCONNECTED,
SPI1_SS1_O => NLW_inst_SPI1_SS1_O_UNCONNECTED,
SPI1_SS2_O => NLW_inst_SPI1_SS2_O_UNCONNECTED,
SPI1_SS_I => '0',
SPI1_SS_O => NLW_inst_SPI1_SS_O_UNCONNECTED,
SPI1_SS_T => NLW_inst_SPI1_SS_T_UNCONNECTED,
SRAM_INTIN => '0',
S_AXI_ACP_ACLK => '0',
S_AXI_ACP_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_ARBURST(1 downto 0) => B"00",
S_AXI_ACP_ARCACHE(3 downto 0) => B"0000",
S_AXI_ACP_ARESETN => NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED,
S_AXI_ACP_ARID(2 downto 0) => B"000",
S_AXI_ACP_ARLEN(3 downto 0) => B"0000",
S_AXI_ACP_ARLOCK(1 downto 0) => B"00",
S_AXI_ACP_ARPROT(2 downto 0) => B"000",
S_AXI_ACP_ARQOS(3 downto 0) => B"0000",
S_AXI_ACP_ARREADY => NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED,
S_AXI_ACP_ARSIZE(2 downto 0) => B"000",
S_AXI_ACP_ARUSER(4 downto 0) => B"00000",
S_AXI_ACP_ARVALID => '0',
S_AXI_ACP_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_AWBURST(1 downto 0) => B"00",
S_AXI_ACP_AWCACHE(3 downto 0) => B"0000",
S_AXI_ACP_AWID(2 downto 0) => B"000",
S_AXI_ACP_AWLEN(3 downto 0) => B"0000",
S_AXI_ACP_AWLOCK(1 downto 0) => B"00",
S_AXI_ACP_AWPROT(2 downto 0) => B"000",
S_AXI_ACP_AWQOS(3 downto 0) => B"0000",
S_AXI_ACP_AWREADY => NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED,
S_AXI_ACP_AWSIZE(2 downto 0) => B"000",
S_AXI_ACP_AWUSER(4 downto 0) => B"00000",
S_AXI_ACP_AWVALID => '0',
S_AXI_ACP_BID(2 downto 0) => NLW_inst_S_AXI_ACP_BID_UNCONNECTED(2 downto 0),
S_AXI_ACP_BREADY => '0',
S_AXI_ACP_BRESP(1 downto 0) => NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_BVALID => NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED,
S_AXI_ACP_RDATA(63 downto 0) => NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED(63 downto 0),
S_AXI_ACP_RID(2 downto 0) => NLW_inst_S_AXI_ACP_RID_UNCONNECTED(2 downto 0),
S_AXI_ACP_RLAST => NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED,
S_AXI_ACP_RREADY => '0',
S_AXI_ACP_RRESP(1 downto 0) => NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_RVALID => NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED,
S_AXI_ACP_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_ACP_WID(2 downto 0) => B"000",
S_AXI_ACP_WLAST => '0',
S_AXI_ACP_WREADY => NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED,
S_AXI_ACP_WSTRB(7 downto 0) => B"00000000",
S_AXI_ACP_WVALID => '0',
S_AXI_GP0_ACLK => '0',
S_AXI_GP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_ARBURST(1 downto 0) => B"00",
S_AXI_GP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP0_ARESETN => NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED,
S_AXI_GP0_ARID(5 downto 0) => B"000000",
S_AXI_GP0_ARLEN(3 downto 0) => B"0000",
S_AXI_GP0_ARLOCK(1 downto 0) => B"00",
S_AXI_GP0_ARPROT(2 downto 0) => B"000",
S_AXI_GP0_ARQOS(3 downto 0) => B"0000",
S_AXI_GP0_ARREADY => NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED,
S_AXI_GP0_ARSIZE(2 downto 0) => B"000",
S_AXI_GP0_ARVALID => '0',
S_AXI_GP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_AWBURST(1 downto 0) => B"00",
S_AXI_GP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP0_AWID(5 downto 0) => B"000000",
S_AXI_GP0_AWLEN(3 downto 0) => B"0000",
S_AXI_GP0_AWLOCK(1 downto 0) => B"00",
S_AXI_GP0_AWPROT(2 downto 0) => B"000",
S_AXI_GP0_AWQOS(3 downto 0) => B"0000",
S_AXI_GP0_AWREADY => NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED,
S_AXI_GP0_AWSIZE(2 downto 0) => B"000",
S_AXI_GP0_AWVALID => '0',
S_AXI_GP0_BID(5 downto 0) => NLW_inst_S_AXI_GP0_BID_UNCONNECTED(5 downto 0),
S_AXI_GP0_BREADY => '0',
S_AXI_GP0_BRESP(1 downto 0) => NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_BVALID => NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED,
S_AXI_GP0_RDATA(31 downto 0) => NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP0_RID(5 downto 0) => NLW_inst_S_AXI_GP0_RID_UNCONNECTED(5 downto 0),
S_AXI_GP0_RLAST => NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED,
S_AXI_GP0_RREADY => '0',
S_AXI_GP0_RRESP(1 downto 0) => NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_RVALID => NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED,
S_AXI_GP0_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_WID(5 downto 0) => B"000000",
S_AXI_GP0_WLAST => '0',
S_AXI_GP0_WREADY => NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED,
S_AXI_GP0_WSTRB(3 downto 0) => B"0000",
S_AXI_GP0_WVALID => '0',
S_AXI_GP1_ACLK => '0',
S_AXI_GP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_ARBURST(1 downto 0) => B"00",
S_AXI_GP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP1_ARESETN => NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED,
S_AXI_GP1_ARID(5 downto 0) => B"000000",
S_AXI_GP1_ARLEN(3 downto 0) => B"0000",
S_AXI_GP1_ARLOCK(1 downto 0) => B"00",
S_AXI_GP1_ARPROT(2 downto 0) => B"000",
S_AXI_GP1_ARQOS(3 downto 0) => B"0000",
S_AXI_GP1_ARREADY => NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED,
S_AXI_GP1_ARSIZE(2 downto 0) => B"000",
S_AXI_GP1_ARVALID => '0',
S_AXI_GP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_AWBURST(1 downto 0) => B"00",
S_AXI_GP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP1_AWID(5 downto 0) => B"000000",
S_AXI_GP1_AWLEN(3 downto 0) => B"0000",
S_AXI_GP1_AWLOCK(1 downto 0) => B"00",
S_AXI_GP1_AWPROT(2 downto 0) => B"000",
S_AXI_GP1_AWQOS(3 downto 0) => B"0000",
S_AXI_GP1_AWREADY => NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED,
S_AXI_GP1_AWSIZE(2 downto 0) => B"000",
S_AXI_GP1_AWVALID => '0',
S_AXI_GP1_BID(5 downto 0) => NLW_inst_S_AXI_GP1_BID_UNCONNECTED(5 downto 0),
S_AXI_GP1_BREADY => '0',
S_AXI_GP1_BRESP(1 downto 0) => NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_BVALID => NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED,
S_AXI_GP1_RDATA(31 downto 0) => NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP1_RID(5 downto 0) => NLW_inst_S_AXI_GP1_RID_UNCONNECTED(5 downto 0),
S_AXI_GP1_RLAST => NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED,
S_AXI_GP1_RREADY => '0',
S_AXI_GP1_RRESP(1 downto 0) => NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_RVALID => NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED,
S_AXI_GP1_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_WID(5 downto 0) => B"000000",
S_AXI_GP1_WLAST => '0',
S_AXI_GP1_WREADY => NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED,
S_AXI_GP1_WSTRB(3 downto 0) => B"0000",
S_AXI_GP1_WVALID => '0',
S_AXI_HP0_ACLK => '0',
S_AXI_HP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_ARBURST(1 downto 0) => B"00",
S_AXI_HP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP0_ARESETN => NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED,
S_AXI_HP0_ARID(5 downto 0) => B"000000",
S_AXI_HP0_ARLEN(3 downto 0) => B"0000",
S_AXI_HP0_ARLOCK(1 downto 0) => B"00",
S_AXI_HP0_ARPROT(2 downto 0) => B"000",
S_AXI_HP0_ARQOS(3 downto 0) => B"0000",
S_AXI_HP0_ARREADY => NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED,
S_AXI_HP0_ARSIZE(2 downto 0) => B"000",
S_AXI_HP0_ARVALID => '0',
S_AXI_HP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_AWBURST(1 downto 0) => B"00",
S_AXI_HP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP0_AWID(5 downto 0) => B"000000",
S_AXI_HP0_AWLEN(3 downto 0) => B"0000",
S_AXI_HP0_AWLOCK(1 downto 0) => B"00",
S_AXI_HP0_AWPROT(2 downto 0) => B"000",
S_AXI_HP0_AWQOS(3 downto 0) => B"0000",
S_AXI_HP0_AWREADY => NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED,
S_AXI_HP0_AWSIZE(2 downto 0) => B"000",
S_AXI_HP0_AWVALID => '0',
S_AXI_HP0_BID(5 downto 0) => NLW_inst_S_AXI_HP0_BID_UNCONNECTED(5 downto 0),
S_AXI_HP0_BREADY => '0',
S_AXI_HP0_BRESP(1 downto 0) => NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_BVALID => NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED,
S_AXI_HP0_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP0_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_RDATA(63 downto 0) => NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP0_RDISSUECAP1_EN => '0',
S_AXI_HP0_RID(5 downto 0) => NLW_inst_S_AXI_HP0_RID_UNCONNECTED(5 downto 0),
S_AXI_HP0_RLAST => NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED,
S_AXI_HP0_RREADY => '0',
S_AXI_HP0_RRESP(1 downto 0) => NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_RVALID => NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED,
S_AXI_HP0_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP0_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP0_WID(5 downto 0) => B"000000",
S_AXI_HP0_WLAST => '0',
S_AXI_HP0_WREADY => NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED,
S_AXI_HP0_WRISSUECAP1_EN => '0',
S_AXI_HP0_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP0_WVALID => '0',
S_AXI_HP1_ACLK => '0',
S_AXI_HP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_ARBURST(1 downto 0) => B"00",
S_AXI_HP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP1_ARESETN => NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED,
S_AXI_HP1_ARID(5 downto 0) => B"000000",
S_AXI_HP1_ARLEN(3 downto 0) => B"0000",
S_AXI_HP1_ARLOCK(1 downto 0) => B"00",
S_AXI_HP1_ARPROT(2 downto 0) => B"000",
S_AXI_HP1_ARQOS(3 downto 0) => B"0000",
S_AXI_HP1_ARREADY => NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED,
S_AXI_HP1_ARSIZE(2 downto 0) => B"000",
S_AXI_HP1_ARVALID => '0',
S_AXI_HP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_AWBURST(1 downto 0) => B"00",
S_AXI_HP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP1_AWID(5 downto 0) => B"000000",
S_AXI_HP1_AWLEN(3 downto 0) => B"0000",
S_AXI_HP1_AWLOCK(1 downto 0) => B"00",
S_AXI_HP1_AWPROT(2 downto 0) => B"000",
S_AXI_HP1_AWQOS(3 downto 0) => B"0000",
S_AXI_HP1_AWREADY => NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED,
S_AXI_HP1_AWSIZE(2 downto 0) => B"000",
S_AXI_HP1_AWVALID => '0',
S_AXI_HP1_BID(5 downto 0) => NLW_inst_S_AXI_HP1_BID_UNCONNECTED(5 downto 0),
S_AXI_HP1_BREADY => '0',
S_AXI_HP1_BRESP(1 downto 0) => NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_BVALID => NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED,
S_AXI_HP1_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP1_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_RDATA(63 downto 0) => NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP1_RDISSUECAP1_EN => '0',
S_AXI_HP1_RID(5 downto 0) => NLW_inst_S_AXI_HP1_RID_UNCONNECTED(5 downto 0),
S_AXI_HP1_RLAST => NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED,
S_AXI_HP1_RREADY => '0',
S_AXI_HP1_RRESP(1 downto 0) => NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_RVALID => NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED,
S_AXI_HP1_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP1_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP1_WID(5 downto 0) => B"000000",
S_AXI_HP1_WLAST => '0',
S_AXI_HP1_WREADY => NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED,
S_AXI_HP1_WRISSUECAP1_EN => '0',
S_AXI_HP1_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP1_WVALID => '0',
S_AXI_HP2_ACLK => '0',
S_AXI_HP2_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_ARBURST(1 downto 0) => B"00",
S_AXI_HP2_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP2_ARESETN => NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED,
S_AXI_HP2_ARID(5 downto 0) => B"000000",
S_AXI_HP2_ARLEN(3 downto 0) => B"0000",
S_AXI_HP2_ARLOCK(1 downto 0) => B"00",
S_AXI_HP2_ARPROT(2 downto 0) => B"000",
S_AXI_HP2_ARQOS(3 downto 0) => B"0000",
S_AXI_HP2_ARREADY => NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED,
S_AXI_HP2_ARSIZE(2 downto 0) => B"000",
S_AXI_HP2_ARVALID => '0',
S_AXI_HP2_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_AWBURST(1 downto 0) => B"00",
S_AXI_HP2_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP2_AWID(5 downto 0) => B"000000",
S_AXI_HP2_AWLEN(3 downto 0) => B"0000",
S_AXI_HP2_AWLOCK(1 downto 0) => B"00",
S_AXI_HP2_AWPROT(2 downto 0) => B"000",
S_AXI_HP2_AWQOS(3 downto 0) => B"0000",
S_AXI_HP2_AWREADY => NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED,
S_AXI_HP2_AWSIZE(2 downto 0) => B"000",
S_AXI_HP2_AWVALID => '0',
S_AXI_HP2_BID(5 downto 0) => NLW_inst_S_AXI_HP2_BID_UNCONNECTED(5 downto 0),
S_AXI_HP2_BREADY => '0',
S_AXI_HP2_BRESP(1 downto 0) => NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_BVALID => NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED,
S_AXI_HP2_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP2_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_RDATA(63 downto 0) => NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP2_RDISSUECAP1_EN => '0',
S_AXI_HP2_RID(5 downto 0) => NLW_inst_S_AXI_HP2_RID_UNCONNECTED(5 downto 0),
S_AXI_HP2_RLAST => NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED,
S_AXI_HP2_RREADY => '0',
S_AXI_HP2_RRESP(1 downto 0) => NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_RVALID => NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED,
S_AXI_HP2_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP2_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP2_WID(5 downto 0) => B"000000",
S_AXI_HP2_WLAST => '0',
S_AXI_HP2_WREADY => NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED,
S_AXI_HP2_WRISSUECAP1_EN => '0',
S_AXI_HP2_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP2_WVALID => '0',
S_AXI_HP3_ACLK => '0',
S_AXI_HP3_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_ARBURST(1 downto 0) => B"00",
S_AXI_HP3_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP3_ARESETN => NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED,
S_AXI_HP3_ARID(5 downto 0) => B"000000",
S_AXI_HP3_ARLEN(3 downto 0) => B"0000",
S_AXI_HP3_ARLOCK(1 downto 0) => B"00",
S_AXI_HP3_ARPROT(2 downto 0) => B"000",
S_AXI_HP3_ARQOS(3 downto 0) => B"0000",
S_AXI_HP3_ARREADY => NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED,
S_AXI_HP3_ARSIZE(2 downto 0) => B"000",
S_AXI_HP3_ARVALID => '0',
S_AXI_HP3_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_AWBURST(1 downto 0) => B"00",
S_AXI_HP3_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP3_AWID(5 downto 0) => B"000000",
S_AXI_HP3_AWLEN(3 downto 0) => B"0000",
S_AXI_HP3_AWLOCK(1 downto 0) => B"00",
S_AXI_HP3_AWPROT(2 downto 0) => B"000",
S_AXI_HP3_AWQOS(3 downto 0) => B"0000",
S_AXI_HP3_AWREADY => NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED,
S_AXI_HP3_AWSIZE(2 downto 0) => B"000",
S_AXI_HP3_AWVALID => '0',
S_AXI_HP3_BID(5 downto 0) => NLW_inst_S_AXI_HP3_BID_UNCONNECTED(5 downto 0),
S_AXI_HP3_BREADY => '0',
S_AXI_HP3_BRESP(1 downto 0) => NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_BVALID => NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED,
S_AXI_HP3_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP3_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_RDATA(63 downto 0) => NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP3_RDISSUECAP1_EN => '0',
S_AXI_HP3_RID(5 downto 0) => NLW_inst_S_AXI_HP3_RID_UNCONNECTED(5 downto 0),
S_AXI_HP3_RLAST => NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED,
S_AXI_HP3_RREADY => '0',
S_AXI_HP3_RRESP(1 downto 0) => NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_RVALID => NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED,
S_AXI_HP3_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP3_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP3_WID(5 downto 0) => B"000000",
S_AXI_HP3_WLAST => '0',
S_AXI_HP3_WREADY => NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED,
S_AXI_HP3_WRISSUECAP1_EN => '0',
S_AXI_HP3_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP3_WVALID => '0',
TRACE_CLK => '0',
TRACE_CLK_OUT => NLW_inst_TRACE_CLK_OUT_UNCONNECTED,
TRACE_CTL => NLW_inst_TRACE_CTL_UNCONNECTED,
TRACE_DATA(1 downto 0) => NLW_inst_TRACE_DATA_UNCONNECTED(1 downto 0),
TTC0_CLK0_IN => '0',
TTC0_CLK1_IN => '0',
TTC0_CLK2_IN => '0',
TTC0_WAVE0_OUT => NLW_inst_TTC0_WAVE0_OUT_UNCONNECTED,
TTC0_WAVE1_OUT => NLW_inst_TTC0_WAVE1_OUT_UNCONNECTED,
TTC0_WAVE2_OUT => NLW_inst_TTC0_WAVE2_OUT_UNCONNECTED,
TTC1_CLK0_IN => '0',
TTC1_CLK1_IN => '0',
TTC1_CLK2_IN => '0',
TTC1_WAVE0_OUT => NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED,
TTC1_WAVE1_OUT => NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED,
TTC1_WAVE2_OUT => NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED,
UART0_CTSN => '0',
UART0_DCDN => '0',
UART0_DSRN => '0',
UART0_DTRN => NLW_inst_UART0_DTRN_UNCONNECTED,
UART0_RIN => '0',
UART0_RTSN => NLW_inst_UART0_RTSN_UNCONNECTED,
UART0_RX => '1',
UART0_TX => NLW_inst_UART0_TX_UNCONNECTED,
UART1_CTSN => '0',
UART1_DCDN => '0',
UART1_DSRN => '0',
UART1_DTRN => NLW_inst_UART1_DTRN_UNCONNECTED,
UART1_RIN => '0',
UART1_RTSN => NLW_inst_UART1_RTSN_UNCONNECTED,
UART1_RX => '1',
UART1_TX => NLW_inst_UART1_TX_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => NLW_inst_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB0_VBUS_PWRFAULT => '0',
USB0_VBUS_PWRSELECT => NLW_inst_USB0_VBUS_PWRSELECT_UNCONNECTED,
USB1_PORT_INDCTL(1 downto 0) => NLW_inst_USB1_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB1_VBUS_PWRFAULT => '0',
USB1_VBUS_PWRSELECT => NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED,
WDT_CLK_IN => '0',
WDT_RST_OUT => NLW_inst_WDT_RST_OUT_UNCONNECTED
);
end STRUCTURE;
| mit | 4949981ba15a5f246877abfbdcbfb5c1 | 0.637048 | 2.770092 | false | false | false | false |
varunnagpaal/Digital-Hardware-Modelling | tutorials/xilinx/hls/ug871-design-files/Using_IP_with_Zynq/lab1/hls_macc/vhls_prj/solution1/syn/vhdl/hls_macc_mul_32s_bkb.vhd | 3 | 2,990 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity hls_macc_mul_32s_bkb_MulnS_0 is
port (
clk: in std_logic;
ce: in std_logic;
a: in std_logic_vector(32 - 1 downto 0);
b: in std_logic_vector(32 - 1 downto 0);
p: out std_logic_vector(32 - 1 downto 0));
end entity;
architecture behav of hls_macc_mul_32s_bkb_MulnS_0 is
signal tmp_product : std_logic_vector(32 - 1 downto 0);
signal a_i : std_logic_vector(32 - 1 downto 0);
signal b_i : std_logic_vector(32 - 1 downto 0);
signal p_tmp : std_logic_vector(32 - 1 downto 0);
signal a_reg0 : std_logic_vector(32 - 1 downto 0);
signal b_reg0 : std_logic_vector(32 - 1 downto 0);
signal buff0 : std_logic_vector(32 - 1 downto 0);
signal buff1 : std_logic_vector(32 - 1 downto 0);
signal buff2 : std_logic_vector(32 - 1 downto 0);
signal buff3 : std_logic_vector(32 - 1 downto 0);
signal buff4 : std_logic_vector(32 - 1 downto 0);
begin
a_i <= a;
b_i <= b;
p <= p_tmp;
p_tmp <= buff4;
tmp_product <= std_logic_vector(resize(unsigned(std_logic_vector(signed(a_reg0) * signed(b_reg0))), 32));
process(clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
a_reg0 <= a_i;
b_reg0 <= b_i;
buff0 <= tmp_product;
buff1 <= buff0;
buff2 <= buff1;
buff3 <= buff2;
buff4 <= buff3;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity hls_macc_mul_32s_bkb is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of hls_macc_mul_32s_bkb is
component hls_macc_mul_32s_bkb_MulnS_0 is
port (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
hls_macc_mul_32s_bkb_MulnS_0_U : component hls_macc_mul_32s_bkb_MulnS_0
port map (
clk => clk,
ce => ce,
a => din0,
b => din1,
p => dout);
end architecture;
| mit | 5190eb9aec3d0576b044d3bfc50007ac | 0.523077 | 3.378531 | false | false | false | false |
MartinCura/SistDig-TP4 | sin_usar/External_RAM/loader_extRam.vhd | 1 | 1,364 | library IEEE;
use IEEE.std_logic_1164.all;
-------------------------------------------------------------------------------
entity extRam_loader is
port(
clk: in std_logic;
reset: in std_logic;
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(15 downto 0);
RxRdy_in: in std_logic;
RxRdy_out: out std_logic
);
end entity extRam_loader;
-------------------------------------------------------------------------------
architecture extRam_loader_arch of extRam_loader is
type state_t is (LSB, MSB);
signal state : state_t := LSB;
begin
FSM: process(clk, reset)
begin
-- RESET
if reset = '1' then
data_out <= (others => '0');
state <= LSB;
RxRdy_out <= '0';
elsif rising_edge(clk) then ---elsif (clk'event and clk = 'l') then
RxRdy_out <= '0';
case state is
-- LSByte
when LSB =>
if RxRdy_in = '1' then
data_out(7 downto 0) <= data_in;
RxRdy_out <= '0';
state <= MSB;
end if;
-- MSByte
when MSB =>
if RxRdy_in = '1' then
data_out(15 downto 8) <= data_in;
RxRdy_out <= '1';
state <= LSB;
end if;
end case;
end if;
end process;
end extRam_loader_arch;
| gpl-3.0 | 995bb7ac9f95f99d047322a7c295afc6 | 0.447947 | 3.788889 | false | false | false | false |
varunnagpaal/Digital-Hardware-Modelling | vhdl/filter/fir/fir_generic_transposed_filter.vhdl | 1 | 8,076 | -- Author: Varun Nagpal
-- Net Id: vxn180010
-- VLSI Design Homework 1
-- 3rd Sept, 2018
--
-- Design: Generic Nth order (L = N+1 taps) Transposed Direct-form FIR-filter
-- IN:
-- n-bit sized Input samples
-- m-Bit sized coefficients
-- OUT:
-- n+m+log2(N+1)-1 bit size of output samples
--
-- Operation requires:
-- N = no. of additions
-- L = N+1 no. of taps or coefficients or multiplications
--
-- Filter must be reset everytime new coefficients have to be read
-- Once coefficients are read, input samples can be processed
-- Input and output sample is registered
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use ieee.std_logic_unsigned.all;
use work.fir_filter_shared_package.all;
-- Top level module
entity fir_generic_transposed_filter is
port (
-- Clock and asynchronous reset
clk : in std_logic;
rst : in std_logic;
-- Handshaking interface as sink
valid_x_in : in std_logic; -- Valid input sample when acting as sink
ready_x_out : out std_logic; -- Ready for input samples when acting as sink
valid_h_in : in std_logic; -- Valid coefficient input when acting as sink
ready_h_out : out std_logic; -- Ready for coefficients when acting as sink
-- Handshaking interface as source
valid_out : out std_logic; -- Valid output when acting as source
ready_in : in std_logic; -- Ready input when acting as source
-- Input samples & coefficients and Output samples
x_data_in : in signed(X_BIT_SIZE-1 downto 0); -- Input samples
h_data_in : in signed(H_BIT_SIZE-1 downto 0); -- Coefficients of filter
y_data_out : out signed(Y_BIT_SIZE-1 downto 0) -- Output samples
);
end fir_generic_transposed_filter;
architecture fir_rtl_arch of fir_generic_transposed_filter is
signal adder_mem_array : ADD_REG_ARRAY; -- array of L = N+1 memory (registers) blocks to store adder outputs
signal multiplier_sigs : MULT_SIG_ARRAY; -- array of L = N+1 multipler signals
signal coefficient_mem_array : COEFF_REG_ARRAY; -- array of L = N+1 memory (registers) blocks to store coefficients
signal coeff_cnt : integer range 0 to FIR_ORDER+1; -- counter for reading L = N+1 coefficients
signal coeff_cnt_next : integer range 0 to FIR_ORDER+1;
signal input_sample_mem : signed(x_data_in'RANGE); -- register to store input data sample
signal output_sample_mem : signed(y_data_out'RANGE); -- register to store output data sample
signal ready_h_out_reg : std_logic;
signal ready_x_out_reg : std_logic;
signal valid_out_reg : std_logic;
begin
-- shift coefficients
read_coefficients: process(clk, rst)
begin
if (rst = '1') then
for i in 0 to FIR_ORDER loop
coefficient_mem_array(i) <= ( others => '0' );
end loop;
elsif (clk'EVENT and clk = '1') then
if ( ready_h_out_reg = '1' and valid_h_in = '1' ) then
coefficient_mem_array(FIR_ORDER) <= h_data_in;
for i in FIR_ORDER-1 downto 0 loop
coefficient_mem_array(i) <= coefficient_mem_array(i+1);
end loop;
end if;
end if;
end process read_coefficients;
-- read one sample at a time
read_samples: process(clk, rst)
begin
if (rst = '1') then
input_sample_mem <= ( others => '0' );
elsif (clk'EVENT and clk = '1') then
if ( ready_x_out_reg = '1' and valid_x_in = '1' ) then
input_sample_mem <= x_data_in;
end if;
end if;
end process read_samples;
-- Generate N parallel signed adder (registered)
accumulate: process(clk, rst)
variable signvec : signed(EXTR_BIT_SIZE-1 downto 0) := ( others => '0' );
variable tempprod : signed(Y_BIT_SIZE-1 downto 0) := ( others => '0');
begin
if (rst = '1') then
for i in 0 to FIR_ORDER loop
adder_mem_array(i) <= ( others => '0');
end loop;
elsif (clk'EVENT and clk = '1') then
-- N = no. of register delays or additions
for i in 0 to FIR_ORDER-1 loop
-- sign extend before generating the adder
signvec := ( others => multiplier_sigs(i)( multiplier_sigs(i)'HIGH ) );
tempprod := signvec & multiplier_sigs(i);
-- generate adder
adder_mem_array(i) <= adder_mem_array(i+1) + tempprod;
end loop;
-- first multiplier result requires no adder and simply needs to be registered
signvec := ( others => multiplier_sigs(FIR_ORDER)( multiplier_sigs(FIR_ORDER)'HIGH ) );
tempprod := signvec & multiplier_sigs(FIR_ORDER);
adder_mem_array(FIR_ORDER) <= tempprod;
end if;
end process accumulate;
-- Generate L=N+1 parallel signed multipliers (combinational)
generate_multipliers: for i in 0 to FIR_ORDER generate
multiplier_sigs (i) <= coefficient_mem_array(i) * input_sample_mem;
end generate generate_multipliers;
-- handshake interface
handshake_mem: process(clk,rst)
begin
if ( rst = '1') then
-- On reset,
-- 1. ready to read coefficients
-- 2. not ready to read input sample and produce output sample
ready_h_out_reg <= '1';
ready_x_out_reg <= '0';
valid_out_reg <= '0';
elsif (clk'EVENT and clk = '1') then
if ( coeff_cnt = (FIR_ORDER+1) ) then
-- Once coefficients are read,
-- 1. not ready to read coefficients
-- 2. ready to read input sample and produce output sample
ready_h_out_reg <= '0';
ready_x_out_reg <= '1';
valid_out_reg <= '1';
end if;
end if;
end process;
valid_out <= valid_out_reg;
ready_x_out <= ready_x_out_reg;
ready_h_out <= ready_h_out_reg;
-- mod L=N+1 counter
coeff_read_counter: process(clk, rst)
begin
if ( rst = '1') then
coeff_cnt <= 0;
elsif (clk'EVENT and clk = '1') then
if ( ready_h_out_reg = '1' and valid_h_in = '1' ) then
coeff_cnt <= coeff_cnt_next;
end if;
end if;
end process coeff_read_counter;
-- Next state logic for mod L=N+1 counter
coeff_cnt_next <= 0 when ( coeff_cnt = ( FIR_ORDER + 1 ) ) else
coeff_cnt + 1;
-- mod L=N+1 counter
--coeff_read_counter: process(clk, rst)
--begin
-- if ( rst = '1') then
-- coeff_cnt <= 0;
-- elsif (clk'EVENT and clk = '1') then
-- if ( ready_h_out_reg = '1' and valid_h_in = '1' ) then
-- if ( coeff_cnt = FIR_ORDER ) then
-- coeff_cnt <= 0;
-- else
-- coeff_cnt <= coeff_cnt + 1;
-- end if;
-- end if;
-- end if;
--end process coeff_read_counter
-- output sample is registered output of last adder
y_data_out <= adder_mem_array(0) when valid_out_reg = '1' else ( others=>'0' );
end fir_rtl_arch; | mit | d8e94d955823b78b64f2b8eccc2e1814 | 0.517211 | 3.970501 | false | false | false | false |
jakubcabal/uart-for-fpga | sim/uart_tb.vhd | 2 | 8,507 | --------------------------------------------------------------------------------
-- PROJECT: SIMPLE UART FOR FPGA
--------------------------------------------------------------------------------
-- AUTHORS: Jakub Cabal <[email protected]>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://github.com/jakubcabal/uart-for-fpga
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
entity UART_TB is
end entity;
architecture SIM of UART_TB is
signal CLK : std_logic;
signal RST : std_logic;
signal driver_rxd_din : std_logic_vector(7 downto 0);
signal driver_rxd : std_logic := '1';
signal driver_rxd_done : std_logic := '0';
signal monitor_dout_expected : std_logic_vector(7 downto 0);
signal monitor_dout : std_logic_vector(7 downto 0);
signal monitor_dout_vld : std_logic;
signal monitor_dout_done : std_logic := '0';
signal driver_din : std_logic_vector(7 downto 0);
signal driver_din_vld : std_logic := '0';
signal driver_din_rdy : std_logic;
signal driver_din_done : std_logic := '0';
signal monitor_txd_dout_expected : std_logic_vector(7 downto 0);
signal monitor_txd_dout : std_logic_vector(7 downto 0);
signal monitor_txd : std_logic := '1';
signal monitor_txd_done : std_logic := '0';
signal monitor_txd_start_bit : std_logic := '0';
signal monitor_txd_stop_bit : std_logic := '0';
signal frame_error : std_logic;
signal parity_error : std_logic;
signal rand_int : integer := 0;
constant CLK_FREQ : natural := 50e6;
constant BAUD_RATE : natural := 115200;
constant TRANS_COUNT : natural := 2**8;
constant CLK_PERIOD : time := 1 ns * integer(real(1e9)/real(CLK_FREQ));
constant UART_PERIOD_I : natural := integer(real(1e9)/real(BAUD_RATE));
constant UART_PERIOD : time := 1 ns * UART_PERIOD_I;
procedure UART_DRIVER (
constant UART_PER : time;
signal UART_DIN : in std_logic_vector(7 downto 0);
signal UART_TXD : out std_logic
) is
variable rnd_delay : natural;
begin
-- start bit
UART_TXD <= '0';
wait for UART_PER;
-- data bits
for i in 0 to (UART_DIN'LENGTH-1) loop
UART_TXD <= UART_DIN(i);
wait for UART_PER;
end loop;
-- stop bit
UART_TXD <= '1';
wait for UART_PER;
end procedure;
procedure UART_MONITOR (
constant UART_PER : time;
signal UART_RXD : in std_logic;
signal UART_DOUT : out std_logic_vector(7 downto 0);
signal UART_START_BIT : out std_logic;
signal UART_STOP_BIT : out std_logic
) is begin
if (UART_RXD = '1') then
wait until UART_RXD = '0';
end if;
UART_START_BIT <= '1';
-- start bit
wait for UART_PER;
UART_START_BIT <= '0';
-- data bits
wait for UART_PER/2; -- move to middle data bit
for i in 0 to (UART_DOUT'LENGTH-2) loop
UART_DOUT(i) <= UART_RXD;
wait for UART_PER;
end loop;
-- last data bit
UART_DOUT(UART_DOUT'LENGTH-1) <= UART_RXD;
wait for UART_PER/2;
-- stop bit
UART_STOP_BIT <= '1';
-- move to middle of stop bit
wait for UART_PER/2;
if (UART_RXD = '0') then
report "======== INVALID STOP BIT IN UART_MONITOR! ========" severity failure;
end if;
UART_STOP_BIT <= '0';
-- in middle of stop bit move to resync (wait for start bit)
end procedure;
begin
rand_int_p : process
variable seed1, seed2: positive;
variable rand : real;
begin
uniform(seed1, seed2, rand);
rand_int <= integer(rand*real(20));
--report "Random number X: " & integer'image(rand_int);
wait for CLK_PERIOD;
end process;
utt : entity work.UART
generic map (
CLK_FREQ => CLK_FREQ,
BAUD_RATE => BAUD_RATE,
PARITY_BIT => "none" -- parity bit is not supported in this simulation
)
port map (
CLK => CLK,
RST => RST,
-- UART INTERFACE
UART_TXD => monitor_txd,
UART_RXD => driver_rxd,
-- USER DATA INPUT INTERFACE
DIN => driver_din,
DIN_VLD => driver_din_vld,
DIN_RDY => driver_din_rdy,
-- USER DATA OUTPUT INTERFACE
DOUT => monitor_dout,
DOUT_VLD => monitor_dout_vld,
FRAME_ERROR => frame_error,
PARITY_ERROR => parity_error
);
clk_gen_p : process
begin
CLK <= '0';
wait for CLK_PERIOD/2;
CLK <= '1';
wait for CLK_PERIOD/2;
end process;
rst_gen_p : process
begin
RST <= '1';
wait for CLK_PERIOD*3;
RST <= '0';
wait;
end process;
-- -------------------------------------------------------------------------
-- UART MODULE RECEIVING TEST
-- -------------------------------------------------------------------------
driver_rxd_p : process
begin
driver_rxd <= '1';
wait until RST = '0';
wait for 33 ns;
for i in 0 to TRANS_COUNT-1 loop
driver_rxd_din <= std_logic_vector(to_unsigned(i,driver_rxd_din'LENGTH));
UART_DRIVER(UART_PERIOD, driver_rxd_din, driver_rxd);
wait for (rand_int/2) * UART_PERIOD;
end loop;
driver_rxd_done <= '1';
wait;
end process;
monitor_dout_p : process
begin
for i in 0 to TRANS_COUNT-1 loop
monitor_dout_expected <= std_logic_vector(to_unsigned(i,monitor_dout_expected'LENGTH));
wait until monitor_dout_vld = '1';
if (monitor_dout = monitor_dout_expected) then
--report "Transaction on DOUT port is OK." severity note;
else
report "======== UNEXPECTED TRANSACTION ON DOUT PORT! ========" severity failure;
end if;
wait for CLK_PERIOD;
end loop;
monitor_dout_done <= '1';
wait;
end process;
-- -------------------------------------------------------------------------
-- UART MODULE TRANSMISSION TEST
-- -------------------------------------------------------------------------
driver_din_p : process
begin
wait until RST = '0';
wait until rising_edge(CLK);
wait for CLK_PERIOD/2;
for i in 0 to TRANS_COUNT-1 loop
driver_din <= std_logic_vector(to_unsigned(i,driver_din'LENGTH));
driver_din_vld <= '1';
if (driver_din_rdy = '0') then
wait until driver_din_rdy = '1';
wait for CLK_PERIOD/2;
end if;
wait for CLK_PERIOD;
driver_din_vld <= '0';
wait for rand_int*(UART_PERIOD_I/16)*CLK_PERIOD;
end loop;
driver_din_done <= '1';
wait;
end process;
monitor_txd_p : process
begin
for i in 0 to TRANS_COUNT-1 loop
monitor_txd_dout_expected <= std_logic_vector(to_unsigned(i,monitor_txd_dout_expected'LENGTH));
UART_MONITOR(UART_PERIOD, monitor_txd, monitor_txd_dout, monitor_txd_start_bit, monitor_txd_stop_bit);
if (monitor_txd_dout = monitor_txd_dout_expected) then
--report "Transaction on UART_TXD port is OK." severity note;
else
report "======== UNEXPECTED TRANSACTION ON UART_TXD PORT! ========" severity failure;
end if;
end loop;
monitor_txd_done <= '1';
wait;
end process;
-- -------------------------------------------------------------------------
-- TEST DONE CHECK
-- -------------------------------------------------------------------------
test_done_p : process
variable v_test_done : std_logic;
begin
v_test_done := driver_rxd_done and monitor_dout_done and driver_din_done and monitor_txd_done;
if (v_test_done = '1') then
wait for 100*CLK_PERIOD;
report "======== SIMULATION SUCCESSFULLY COMPLETED! ========" severity failure;
end if;
wait for CLK_PERIOD;
end process;
end architecture;
| mit | 14250b4e3c2a413205b040f74a4f4da6 | 0.501822 | 4.050952 | false | false | false | false |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/hls_tutorial_lab1/hls_tutorial_lab1.srcs/sources_1/bd/zybo_zynq_design/ip/zybo_zynq_design_rst_ps7_0_100M_0/zybo_zynq_design_rst_ps7_0_100M_0_sim_netlist.vhdl | 1 | 35,878 | -- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Sun Sep 22 02:34:31 2019
-- Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim
-- d:/github/Digital-Hardware-Modelling/xilinx-vivado/hls_tutorial_lab1/hls_tutorial_lab1.srcs/sources_1/bd/zybo_zynq_design/ip/zybo_zynq_design_rst_ps7_0_100M_0/zybo_zynq_design_rst_ps7_0_100M_0_sim_netlist.vhdl
-- Design : zybo_zynq_design_rst_ps7_0_100M_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zybo_zynq_design_rst_ps7_0_100M_0_cdc_sync is
port (
lpf_asr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
lpf_asr : in STD_LOGIC;
p_1_in : in STD_LOGIC;
p_2_in : in STD_LOGIC;
asr_lpf : in STD_LOGIC_VECTOR ( 0 to 0 );
aux_reset_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zybo_zynq_design_rst_ps7_0_100M_0_cdc_sync : entity is "cdc_sync";
end zybo_zynq_design_rst_ps7_0_100M_0_cdc_sync;
architecture STRUCTURE of zybo_zynq_design_rst_ps7_0_100M_0_cdc_sync is
signal asr_d1 : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => asr_d1,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aux_reset_in,
O => asr_d1
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_asr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_asr,
I1 => p_1_in,
I2 => p_2_in,
I3 => \^scndry_out\,
I4 => asr_lpf(0),
O => lpf_asr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zybo_zynq_design_rst_ps7_0_100M_0_cdc_sync_0 is
port (
lpf_exr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
lpf_exr : in STD_LOGIC;
p_3_out : in STD_LOGIC_VECTOR ( 2 downto 0 );
mb_debug_sys_rst : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zybo_zynq_design_rst_ps7_0_100M_0_cdc_sync_0 : entity is "cdc_sync";
end zybo_zynq_design_rst_ps7_0_100M_0_cdc_sync_0;
architecture STRUCTURE of zybo_zynq_design_rst_ps7_0_100M_0_cdc_sync_0 is
signal exr_d1 : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => exr_d1,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => mb_debug_sys_rst,
I1 => ext_reset_in,
O => exr_d1
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_exr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_exr,
I1 => p_3_out(1),
I2 => p_3_out(2),
I3 => \^scndry_out\,
I4 => p_3_out(0),
O => lpf_exr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zybo_zynq_design_rst_ps7_0_100M_0_upcnt_n is
port (
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
seq_clr : in STD_LOGIC;
seq_cnt_en : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zybo_zynq_design_rst_ps7_0_100M_0_upcnt_n : entity is "upcnt_n";
end zybo_zynq_design_rst_ps7_0_100M_0_upcnt_n;
architecture STRUCTURE of zybo_zynq_design_rst_ps7_0_100M_0_upcnt_n is
signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal clear : STD_LOGIC;
signal q_int0 : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \q_int[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \q_int[4]_i_1\ : label is "soft_lutpair0";
begin
Q(5 downto 0) <= \^q\(5 downto 0);
\q_int[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => q_int0(0)
);
\q_int[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => q_int0(1)
);
\q_int[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => q_int0(2)
);
\q_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => q_int0(3)
);
\q_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => q_int0(4)
);
\q_int[5]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => seq_clr,
O => clear
);
\q_int[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => q_int0(5)
);
\q_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(0),
Q => \^q\(0),
R => clear
);
\q_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(1),
Q => \^q\(1),
R => clear
);
\q_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(2),
Q => \^q\(2),
R => clear
);
\q_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(3),
Q => \^q\(3),
R => clear
);
\q_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(4),
Q => \^q\(4),
R => clear
);
\q_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(5),
Q => \^q\(5),
R => clear
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zybo_zynq_design_rst_ps7_0_100M_0_lpf is
port (
lpf_int : out STD_LOGIC;
slowest_sync_clk : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zybo_zynq_design_rst_ps7_0_100M_0_lpf : entity is "lpf";
end zybo_zynq_design_rst_ps7_0_100M_0_lpf;
architecture STRUCTURE of zybo_zynq_design_rst_ps7_0_100M_0_lpf is
signal \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\ : STD_LOGIC;
signal \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\ : STD_LOGIC;
signal Q : STD_LOGIC;
signal asr_lpf : STD_LOGIC_VECTOR ( 0 to 0 );
signal lpf_asr : STD_LOGIC;
signal lpf_exr : STD_LOGIC;
signal \lpf_int0__0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_3_in1_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of POR_SRL_I : label is "SRL16";
attribute box_type : string;
attribute box_type of POR_SRL_I : label is "PRIMITIVE";
attribute srl_name : string;
attribute srl_name of POR_SRL_I : label is "U0/\EXT_LPF/POR_SRL_I ";
begin
\ACTIVE_LOW_AUX.ACT_LO_AUX\: entity work.zybo_zynq_design_rst_ps7_0_100M_0_cdc_sync
port map (
asr_lpf(0) => asr_lpf(0),
aux_reset_in => aux_reset_in,
lpf_asr => lpf_asr,
lpf_asr_reg => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
p_1_in => p_1_in,
p_2_in => p_2_in,
scndry_out => p_3_in1_in,
slowest_sync_clk => slowest_sync_clk
);
\ACTIVE_LOW_EXT.ACT_LO_EXT\: entity work.zybo_zynq_design_rst_ps7_0_100M_0_cdc_sync_0
port map (
ext_reset_in => ext_reset_in,
lpf_exr => lpf_exr,
lpf_exr_reg => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\,
mb_debug_sys_rst => mb_debug_sys_rst,
p_3_out(2 downto 0) => p_3_out(2 downto 0),
scndry_out => p_3_out(3),
slowest_sync_clk => slowest_sync_clk
);
\AUX_LPF[1].asr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_in1_in,
Q => p_2_in,
R => '0'
);
\AUX_LPF[2].asr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_2_in,
Q => p_1_in,
R => '0'
);
\AUX_LPF[3].asr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_1_in,
Q => asr_lpf(0),
R => '0'
);
\EXT_LPF[1].exr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(3),
Q => p_3_out(2),
R => '0'
);
\EXT_LPF[2].exr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => p_3_out(1),
R => '0'
);
\EXT_LPF[3].exr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(1),
Q => p_3_out(0),
R => '0'
);
POR_SRL_I: unisim.vcomponents.SRL16E
generic map(
INIT => X"FFFF"
)
port map (
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
CE => '1',
CLK => slowest_sync_clk,
D => '0',
Q => Q
);
lpf_asr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
Q => lpf_asr,
R => '0'
);
lpf_exr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\,
Q => lpf_exr,
R => '0'
);
lpf_int0: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFD"
)
port map (
I0 => dcm_locked,
I1 => lpf_exr,
I2 => lpf_asr,
I3 => Q,
O => \lpf_int0__0\
);
lpf_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \lpf_int0__0\,
Q => lpf_int,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zybo_zynq_design_rst_ps7_0_100M_0_sequence_psr is
port (
MB_out : out STD_LOGIC;
Bsr_out : out STD_LOGIC;
Pr_out : out STD_LOGIC;
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ : out STD_LOGIC;
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ : out STD_LOGIC;
lpf_int : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zybo_zynq_design_rst_ps7_0_100M_0_sequence_psr : entity is "sequence_psr";
end zybo_zynq_design_rst_ps7_0_100M_0_sequence_psr;
architecture STRUCTURE of zybo_zynq_design_rst_ps7_0_100M_0_sequence_psr is
signal \^bsr_out\ : STD_LOGIC;
signal Core_i_1_n_0 : STD_LOGIC;
signal \^mb_out\ : STD_LOGIC;
signal \^pr_out\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal bsr_i_1_n_0 : STD_LOGIC;
signal \core_dec[0]_i_1_n_0\ : STD_LOGIC;
signal \core_dec[2]_i_1_n_0\ : STD_LOGIC;
signal \core_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \core_dec_reg_n_0_[1]\ : STD_LOGIC;
signal from_sys_i_1_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \pr_dec0__0\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal pr_i_1_n_0 : STD_LOGIC;
signal seq_clr : STD_LOGIC;
signal seq_cnt : STD_LOGIC_VECTOR ( 5 downto 0 );
signal seq_cnt_en : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of Core_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \bsr_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of bsr_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \core_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \core_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of from_sys_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \pr_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of pr_i_1 : label is "soft_lutpair4";
begin
Bsr_out <= \^bsr_out\;
MB_out <= \^mb_out\;
Pr_out <= \^pr_out\;
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^bsr_out\,
O => \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\
);
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^pr_out\,
O => \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\
);
Core_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^mb_out\,
I1 => p_0_in,
O => Core_i_1_n_0
);
Core_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Core_i_1_n_0,
Q => \^mb_out\,
S => lpf_int
);
SEQ_COUNTER: entity work.zybo_zynq_design_rst_ps7_0_100M_0_upcnt_n
port map (
Q(5 downto 0) => seq_cnt(5 downto 0),
seq_clr => seq_clr,
seq_cnt_en => seq_cnt_en,
slowest_sync_clk => slowest_sync_clk
);
\bsr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0090"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(4),
I2 => seq_cnt(3),
I3 => seq_cnt(5),
O => p_5_out(0)
);
\bsr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \bsr_dec_reg_n_0_[0]\,
O => p_5_out(2)
);
\bsr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(0),
Q => \bsr_dec_reg_n_0_[0]\,
R => '0'
);
\bsr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(2),
Q => \bsr_dec_reg_n_0_[2]\,
R => '0'
);
bsr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^bsr_out\,
I1 => \bsr_dec_reg_n_0_[2]\,
O => bsr_i_1_n_0
);
bsr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => bsr_i_1_n_0,
Q => \^bsr_out\,
S => lpf_int
);
\core_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9000"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(4),
I2 => seq_cnt(3),
I3 => seq_cnt(5),
O => \core_dec[0]_i_1_n_0\
);
\core_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \core_dec_reg_n_0_[0]\,
O => \core_dec[2]_i_1_n_0\
);
\core_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[0]_i_1_n_0\,
Q => \core_dec_reg_n_0_[0]\,
R => '0'
);
\core_dec_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \pr_dec0__0\,
Q => \core_dec_reg_n_0_[1]\,
R => '0'
);
\core_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[2]_i_1_n_0\,
Q => p_0_in,
R => '0'
);
from_sys_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^mb_out\,
I1 => seq_cnt_en,
O => from_sys_i_1_n_0
);
from_sys_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => from_sys_i_1_n_0,
Q => seq_cnt_en,
S => lpf_int
);
pr_dec0: unisim.vcomponents.LUT4
generic map(
INIT => X"0018"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(0),
I2 => seq_cnt(2),
I3 => seq_cnt(1),
O => \pr_dec0__0\
);
\pr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0480"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt(4),
O => p_3_out(0)
);
\pr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \pr_dec_reg_n_0_[0]\,
O => p_3_out(2)
);
\pr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(0),
Q => \pr_dec_reg_n_0_[0]\,
R => '0'
);
\pr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => \pr_dec_reg_n_0_[2]\,
R => '0'
);
pr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^pr_out\,
I1 => \pr_dec_reg_n_0_[2]\,
O => pr_i_1_n_0
);
pr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => pr_i_1_n_0,
Q => \^pr_out\,
S => lpf_int
);
seq_clr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => '1',
Q => seq_clr,
R => lpf_int
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zybo_zynq_design_rst_ps7_0_100M_0_proc_sys_reset is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of zybo_zynq_design_rst_ps7_0_100M_0_proc_sys_reset : entity is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of zybo_zynq_design_rst_ps7_0_100M_0_proc_sys_reset : entity is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of zybo_zynq_design_rst_ps7_0_100M_0_proc_sys_reset : entity is "1'b0";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of zybo_zynq_design_rst_ps7_0_100M_0_proc_sys_reset : entity is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of zybo_zynq_design_rst_ps7_0_100M_0_proc_sys_reset : entity is "zynq";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of zybo_zynq_design_rst_ps7_0_100M_0_proc_sys_reset : entity is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of zybo_zynq_design_rst_ps7_0_100M_0_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of zybo_zynq_design_rst_ps7_0_100M_0_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of zybo_zynq_design_rst_ps7_0_100M_0_proc_sys_reset : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zybo_zynq_design_rst_ps7_0_100M_0_proc_sys_reset : entity is "proc_sys_reset";
end zybo_zynq_design_rst_ps7_0_100M_0_proc_sys_reset;
architecture STRUCTURE of zybo_zynq_design_rst_ps7_0_100M_0_proc_sys_reset is
signal Bsr_out : STD_LOGIC;
signal MB_out : STD_LOGIC;
signal Pr_out : STD_LOGIC;
signal SEQ_n_3 : STD_LOGIC;
signal SEQ_n_4 : STD_LOGIC;
signal lpf_int : STD_LOGIC;
attribute box_type : string;
attribute box_type of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ : label is "PRIMITIVE";
attribute box_type of \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ : label is "PRIMITIVE";
attribute box_type of \BSR_OUT_DFF[0].FDRE_BSR\ : label is "PRIMITIVE";
attribute box_type of FDRE_inst : label is "PRIMITIVE";
attribute box_type of \PR_OUT_DFF[0].FDRE_PER\ : label is "PRIMITIVE";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of bus_struct_reset : signal is "no";
attribute equivalent_register_removal of interconnect_aresetn : signal is "no";
attribute equivalent_register_removal of peripheral_aresetn : signal is "no";
attribute equivalent_register_removal of peripheral_reset : signal is "no";
begin
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_3,
Q => interconnect_aresetn(0),
R => '0'
);
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_4,
Q => peripheral_aresetn(0),
R => '0'
);
\BSR_OUT_DFF[0].FDRE_BSR\: unisim.vcomponents.FDRE
generic map(
INIT => '1',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Bsr_out,
Q => bus_struct_reset(0),
R => '0'
);
EXT_LPF: entity work.zybo_zynq_design_rst_ps7_0_100M_0_lpf
port map (
aux_reset_in => aux_reset_in,
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
lpf_int => lpf_int,
mb_debug_sys_rst => mb_debug_sys_rst,
slowest_sync_clk => slowest_sync_clk
);
FDRE_inst: unisim.vcomponents.FDRE
generic map(
INIT => '1',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => MB_out,
Q => mb_reset,
R => '0'
);
\PR_OUT_DFF[0].FDRE_PER\: unisim.vcomponents.FDRE
generic map(
INIT => '1',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Pr_out,
Q => peripheral_reset(0),
R => '0'
);
SEQ: entity work.zybo_zynq_design_rst_ps7_0_100M_0_sequence_psr
port map (
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ => SEQ_n_3,
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ => SEQ_n_4,
Bsr_out => Bsr_out,
MB_out => MB_out,
Pr_out => Pr_out,
lpf_int => lpf_int,
slowest_sync_clk => slowest_sync_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zybo_zynq_design_rst_ps7_0_100M_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of zybo_zynq_design_rst_ps7_0_100M_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of zybo_zynq_design_rst_ps7_0_100M_0 : entity is "zybo_zynq_design_rst_ps7_0_100M_0,proc_sys_reset,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of zybo_zynq_design_rst_ps7_0_100M_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of zybo_zynq_design_rst_ps7_0_100M_0 : entity is "proc_sys_reset,Vivado 2018.2";
end zybo_zynq_design_rst_ps7_0_100M_0;
architecture STRUCTURE of zybo_zynq_design_rst_ps7_0_100M_0 is
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of U0 : label is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of U0 : label is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of U0 : label is "1'b0";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of U0 : label is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of U0 : label is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of U0 : label is 1;
attribute x_interface_info : string;
attribute x_interface_info of aux_reset_in : signal is "xilinx.com:signal:reset:1.0 aux_reset RST";
attribute x_interface_parameter : string;
attribute x_interface_parameter of aux_reset_in : signal is "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW";
attribute x_interface_info of ext_reset_in : signal is "xilinx.com:signal:reset:1.0 ext_reset RST";
attribute x_interface_parameter of ext_reset_in : signal is "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW";
attribute x_interface_info of mb_debug_sys_rst : signal is "xilinx.com:signal:reset:1.0 dbg_reset RST";
attribute x_interface_parameter of mb_debug_sys_rst : signal is "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH";
attribute x_interface_info of mb_reset : signal is "xilinx.com:signal:reset:1.0 mb_rst RST";
attribute x_interface_parameter of mb_reset : signal is "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR";
attribute x_interface_info of slowest_sync_clk : signal is "xilinx.com:signal:clock:1.0 clock CLK";
attribute x_interface_parameter of slowest_sync_clk : signal is "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN zybo_zynq_design_processing_system7_0_0_FCLK_CLK0";
attribute x_interface_info of bus_struct_reset : signal is "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
attribute x_interface_parameter of bus_struct_reset : signal is "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT";
attribute x_interface_info of interconnect_aresetn : signal is "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
attribute x_interface_parameter of interconnect_aresetn : signal is "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT";
attribute x_interface_info of peripheral_aresetn : signal is "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
attribute x_interface_parameter of peripheral_aresetn : signal is "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL";
attribute x_interface_info of peripheral_reset : signal is "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
attribute x_interface_parameter of peripheral_reset : signal is "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL";
begin
U0: entity work.zybo_zynq_design_rst_ps7_0_100M_0_proc_sys_reset
port map (
aux_reset_in => aux_reset_in,
bus_struct_reset(0) => bus_struct_reset(0),
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
interconnect_aresetn(0) => interconnect_aresetn(0),
mb_debug_sys_rst => mb_debug_sys_rst,
mb_reset => mb_reset,
peripheral_aresetn(0) => peripheral_aresetn(0),
peripheral_reset(0) => peripheral_reset(0),
slowest_sync_clk => slowest_sync_clk
);
end STRUCTURE;
| mit | 7ecadc5413b3949681de109b54275e4c | 0.588216 | 2.868634 | false | false | false | false |
natsutan/NPU | fpga_implement/npu8/npu8.srcs/sources_1/ip/mul_16_32/synth/mul_16_32.vhd | 1 | 5,681 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:mult_gen:12.0
-- IP Revision: 12
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY mult_gen_v12_0_12;
USE mult_gen_v12_0_12.mult_gen_v12_0_12;
ENTITY mul_16_32 IS
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
P : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
);
END mul_16_32;
ARCHITECTURE mul_16_32_arch OF mul_16_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF mul_16_32_arch: ARCHITECTURE IS "yes";
COMPONENT mult_gen_v12_0_12 IS
GENERIC (
C_VERBOSITY : INTEGER;
C_MODEL_TYPE : INTEGER;
C_OPTIMIZE_GOAL : INTEGER;
C_XDEVICEFAMILY : STRING;
C_HAS_CE : INTEGER;
C_HAS_SCLR : INTEGER;
C_LATENCY : INTEGER;
C_A_WIDTH : INTEGER;
C_A_TYPE : INTEGER;
C_B_WIDTH : INTEGER;
C_B_TYPE : INTEGER;
C_OUT_HIGH : INTEGER;
C_OUT_LOW : INTEGER;
C_MULT_TYPE : INTEGER;
C_CE_OVERRIDES_SCLR : INTEGER;
C_CCM_IMP : INTEGER;
C_B_VALUE : STRING;
C_HAS_ZERO_DETECT : INTEGER;
C_ROUND_OUTPUT : INTEGER;
C_ROUND_PT : INTEGER
);
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
CE : IN STD_LOGIC;
SCLR : IN STD_LOGIC;
P : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
);
END COMPONENT mult_gen_v12_0_12;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF mul_16_32_arch: ARCHITECTURE IS "mult_gen_v12_0_12,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF mul_16_32_arch : ARCHITECTURE IS "mul_16_32,mult_gen_v12_0_12,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF mul_16_32_arch: ARCHITECTURE IS "mul_16_32,mult_gen_v12_0_12,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mult_gen,x_ipVersion=12.0,x_ipCoreRevision=12,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_VERBOSITY=0,C_MODEL_TYPE=0,C_OPTIMIZE_GOAL=1,C_XDEVICEFAMILY=kintexu,C_HAS_CE=0,C_HAS_SCLR=0,C_LATENCY=4,C_A_WIDTH=16,C_A_TYPE=1,C_B_WIDTH=32,C_B_TYPE=1,C_OUT_HIGH=47,C_OUT_LOW=0,C_MULT_TYPE=0,C_CE_OVERRIDES_SCLR=0,C_CCM_IMP=0,C_B_VALUE=10000001,C_HAS_ZERO_DETECT=0,C_ROUND_OUTPUT=0,C_ROUND_PT=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF A: SIGNAL IS "xilinx.com:signal:data:1.0 a_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF B: SIGNAL IS "xilinx.com:signal:data:1.0 b_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF P: SIGNAL IS "xilinx.com:signal:data:1.0 p_intf DATA";
BEGIN
U0 : mult_gen_v12_0_12
GENERIC MAP (
C_VERBOSITY => 0,
C_MODEL_TYPE => 0,
C_OPTIMIZE_GOAL => 1,
C_XDEVICEFAMILY => "kintexu",
C_HAS_CE => 0,
C_HAS_SCLR => 0,
C_LATENCY => 4,
C_A_WIDTH => 16,
C_A_TYPE => 1,
C_B_WIDTH => 32,
C_B_TYPE => 1,
C_OUT_HIGH => 47,
C_OUT_LOW => 0,
C_MULT_TYPE => 0,
C_CE_OVERRIDES_SCLR => 0,
C_CCM_IMP => 0,
C_B_VALUE => "10000001",
C_HAS_ZERO_DETECT => 0,
C_ROUND_OUTPUT => 0,
C_ROUND_PT => 0
)
PORT MAP (
CLK => CLK,
A => A,
B => B,
CE => '1',
SCLR => '0',
P => P
);
END mul_16_32_arch;
| bsd-3-clause | 4da925b16997a2a7efe227e06fd72191 | 0.677874 | 3.341765 | false | false | false | false |
MartinCura/SistDig-TP4 | old/fix_floating_point_files/standard_textio_additions_c.vhdl | 1 | 16,020 | ------------------------------------------------------------------------------
-- "standard_textio_additions" package contains the additions to the built in
-- "standard.textio" package.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee_proposed.standard_textio_additions.all;
-- Last Modified: $Date: 2007/03/13 18:25:58 $
-- RCS ID: $Id: standard_textio_additions_c.vhdl,v 1.5 2007/03/13 18:25:58 l435385 Exp $
--
-- Created for VHDL-200X par, David Bishop ([email protected])
------------------------------------------------------------------------------
use std.textio.all;
package standard_textio_additions is
-- procedure DEALLOCATE (P : inout LINE);
procedure FLUSH (file F : TEXT);
function MINIMUM (L, R : SIDE) return SIDE;
function MAXIMUM (L, R : SIDE) return SIDE;
function TO_STRING (VALUE : SIDE) return STRING;
function JUSTIFY (VALUE : STRING; JUSTIFIED : SIDE := right; FIELD : WIDTH := 0) return STRING;
procedure SREAD (L : inout LINE; VALUE : out STRING; STRLEN : out NATURAL);
alias STRING_READ is SREAD [LINE, STRING, NATURAL];
alias BREAD is READ [LINE, BIT_VECTOR, BOOLEAN];
alias BREAD is READ [LINE, BIT_VECTOR];
alias BINARY_READ is READ [LINE, BIT_VECTOR, BOOLEAN];
alias BINARY_READ is READ [LINE, BIT_VECTOR];
procedure OREAD (L : inout LINE; VALUE : out BIT_VECTOR; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out BIT_VECTOR);
alias OCTAL_READ is OREAD [LINE, BIT_VECTOR, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, BIT_VECTOR];
procedure HREAD (L : inout LINE; VALUE : out BIT_VECTOR; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out BIT_VECTOR);
alias HEX_READ is HREAD [LINE, BIT_VECTOR, BOOLEAN];
alias HEX_READ is HREAD [LINE, BIT_VECTOR];
procedure TEE (file F : TEXT; L : inout LINE);
procedure WRITE (L : inout LINE; VALUE : in REAL;
FORMAT : in STRING);
alias SWRITE is WRITE [LINE, STRING, SIDE, WIDTH];
alias STRING_WRITE is WRITE [LINE, STRING, SIDE, WIDTH];
alias BWRITE is WRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in BIT_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in BIT_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
end package standard_textio_additions;
---library ieee_proposed;
---use ieee_proposed.standard_additions.all;
library work;
use work.standard_additions.all;
package body standard_textio_additions is
-- pragma synthesis_off
constant NUS : STRING(2 to 1) := (others => ' '); -- NULL array
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
-- Writes L to a file without modifying the contents of the line
procedure TEE (file F : TEXT; L : inout LINE) is
begin
write (OUTPUT, L.all & LF);
writeline(F, L);
end procedure TEE;
procedure FLUSH (file F: TEXT) is -- Implicit
begin
file_close (F);
end procedure FLUSH;
-- Read and Write procedure for strings
procedure SREAD (L : inout LINE;
VALUE : out STRING;
STRLEN : out natural) is
variable ok : BOOLEAN;
variable c : CHARACTER;
-- Result is padded with space characters
variable result : STRING (1 to VALUE'length) := (others => ' ');
begin
VALUE := result;
loop -- skip white space
read(L, c, ok);
exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
STRLEN := 0;
return;
end if;
result (1) := c;
STRLEN := 1;
for i in 2 to VALUE'length loop
read(L, c, ok);
if (ok = false) or ((c = ' ') or (c = NBSP) or (c = HT)) then
exit;
else
result (i) := c;
end if;
STRLEN := i;
end loop;
VALUE := result;
end procedure SREAD;
-- Hex Read and Write procedures for bit_vector.
-- Procedure only visible internally.
procedure Char2QuadBits (C : CHARACTER;
RESULT : out BIT_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when others =>
assert not ISSUE_ERROR report
"TEXTIO.HREAD Error: Read a '" & c &
"', expected a Hex character (0-F)." severity error;
GOOD := false;
end case;
end procedure Char2QuadBits;
procedure HREAD (L : inout LINE;
VALUE : out BIT_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : BIT_VECTOR (0 to ne*4 - 1) := (others => '0');
variable s : STRING(1 to ne-1);
begin
VALUE := (VALUE'range => '0');
loop -- skip white space
read(l, c, ok);
exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
GOOD := false;
return;
end if;
Char2QuadBits(c, sv(0 to 3), ok, false);
if not ok then
GOOD := false;
return;
end if;
read(L, s, ok);
if not ok then
GOOD := false;
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), sv(4*i to 4*i+3), ok, false);
if not ok then
GOOD := false;
return;
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then
GOOD := false; -- vector was truncated.
else
GOOD := true;
VALUE := sv (pad to sv'high);
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE;
VALUE : out BIT_VECTOR) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : BIT_VECTOR(0 to ne*4 - 1) := (others => '0');
variable s : STRING(1 to ne-1);
begin
VALUE := (VALUE'range => '0');
loop -- skip white space
read(l, c, ok);
exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
report "TEXTIO.HREAD Error: Failed skipping white space"
severity error;
return;
end if;
Char2QuadBits(c, sv(0 to 3), ok, true);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
report "TEXTIO.HREAD Error: Failed to read the STRING"
severity error;
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), sv(4*i to 4*i+3), ok, true);
if not ok then
return;
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then
report "TEXTIO.HREAD Error: Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end procedure HREAD;
procedure HWRITE (L : inout LINE;
VALUE : in BIT_VECTOR;
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin
write (L => L,
VALUE => to_hstring(VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure HWRITE;
-- Procedure only visible internally.
procedure Char2TriBits (C : CHARACTER;
RESULT : out BIT_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when others =>
assert not ISSUE_ERROR
report
"TEXTIO.OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
GOOD := false;
end case;
end procedure Char2TriBits;
-- Read and Write procedures for Octal values
procedure OREAD (L : inout LINE;
VALUE : out BIT_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : BIT_VECTOR(0 to ne*3 - 1) := (others => '0');
variable s : STRING(1 to ne-1);
begin
VALUE := (VALUE'range => '0');
loop -- skip white space
read(l, c, ok);
exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
GOOD := false;
return;
end if;
Char2TriBits(c, sv(0 to 2), ok, false);
if not ok then
GOOD := false;
return;
end if;
read(L, s, ok);
if not ok then
GOOD := false;
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), sv(3*i to 3*i+2), ok, false);
if not ok then
GOOD := false;
return;
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then
GOOD := false; -- vector was truncated.
else
GOOD := true;
VALUE := sv (pad to sv'high);
end if;
end procedure OREAD;
procedure OREAD (L : inout LINE;
VALUE : out BIT_VECTOR) is
variable c : CHARACTER;
variable ok : BOOLEAN;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : BIT_VECTOR(0 to ne*3 - 1) := (others => '0');
variable s : STRING(1 to ne-1);
begin
VALUE := (VALUE'range => '0');
loop -- skip white space
read(l, c, ok);
exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
report "TEXTIO.OREAD Error: Failed skipping white space"
severity error;
return;
end if;
Char2TriBits(c, sv(0 to 2), ok, true);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
report "TEXTIO.OREAD Error: Failed to read the STRING"
severity error;
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), sv(3*i to 3*i+2), ok, true);
if not ok then
return;
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then
report "TEXTIO.OREAD Error: Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end procedure OREAD;
procedure OWRITE (L : inout LINE;
VALUE : in BIT_VECTOR;
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin
write (L => L,
VALUE => to_ostring(VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure OWRITE;
-- read and write for vector versions
-- These versions produce "value1, value2, value3 ...."
procedure read (L : inout LINE;
VALUE : out boolean_vector;
GOOD : out BOOLEAN) is
variable dummy : CHARACTER;
variable igood : BOOLEAN := true;
begin
for i in VALUE'range loop
read (L => L,
VALUE => VALUE(i),
GOOD => igood);
if (igood) and (i /= value'right) then
read (L => L,
VALUE => dummy, -- Toss the comma or seperator
good => igood);
end if;
if (not igood) then
good := false;
return;
end if;
end loop;
good := true;
end procedure read;
procedure read (L : inout LINE;
VALUE : out boolean_vector) is
variable dummy : CHARACTER;
variable igood : BOOLEAN;
begin
for i in VALUE'range loop
read (L => L,
VALUE => VALUE(i),
good => igood);
if (igood) and (i /= value'right) then
read (L => L,
VALUE => dummy, -- Toss the comma or seperator
good => igood);
end if;
if (not igood) then
report "STANDARD.STD_TEXTIO(BOOLEAN_VECTOR) "
& "Read error ecounted during vector read" severity error;
return;
end if;
end loop;
end procedure read;
procedure write (L : inout LINE;
VALUE : in boolean_vector;
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin
for i in VALUE'range loop
write (L => L,
VALUE => VALUE(i),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
if (i /= value'right) then
swrite (L, ", ");
end if;
end loop;
end procedure write;
procedure WRITE (L: inout LINE; VALUE: in REAL;
FORMAT: in STRING) is
begin
swrite ( L => L,
VALUE => to_string (VALUE, FORMAT));
end procedure WRITE;
function justify (
value : STRING;
justified : SIDE := right;
field : width := 0)
return STRING is
constant VAL_LEN : INTEGER := value'length;
variable result : STRING (1 to field) := (others => ' ');
begin -- function justify
-- return value if field is too small
if VAL_LEN >= field then
return value;
end if;
if justified = left then
result(1 to VAL_LEN) := value;
elsif justified = right then
result(field - VAL_LEN + 1 to field) := value;
end if;
return result;
end function justify;
function to_string (
VALUE : SIDE) return STRING is
begin
return SIDE'image(VALUE);
end function to_string;
-- pragma synthesis_on
-- Will be implicit
function minimum (L, R : SIDE) return SIDE is
begin
if L > R then return R;
else return L;
end if;
end function minimum;
function maximum (L, R : SIDE) return SIDE is
begin
if L > R then return L;
else return R;
end if;
end function maximum;
end package body standard_textio_additions;
| gpl-3.0 | 2f00a8ef2678e5319eb6d2e3ebdd638c | 0.522846 | 3.830703 | false | false | false | false |
natsutan/NPU | fpga_implement/npu8/npu8.srcs/sources_1/ip/mul8_16/mul8_16_sim_netlist.vhdl | 1 | 287,556 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
-- Date : Sat Jan 21 14:33:05 2017
-- Host : natu-OMEN-by-HP-Laptop running 64-bit Ubuntu 16.04.1 LTS
-- Command : write_vhdl -force -mode funcsim
-- /media/natu/data/proj/myproj/NPU/fpga_implement/npu8/npu8.srcs/sources_1/ip/mul8_16/mul8_16_sim_netlist.vhdl
-- Design : mul8_16
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xcku035-fbva676-3-e
-- --------------------------------------------------------------------------------
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner="Cadence Design Systems.", key_keyname="cds_rsa_key", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=64)
`protect key_block
fPF16TcpNgM9dNC6nyb4WjUK+7bY8P+I62AEEiiM/KOMhIKuPOHBoWeWL2UjxSNO68WLeYIZp8lA
I7rHN/CieA==
`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`protect key_block
E6OKJxjnDRUVVFwAhrQMAtoyRVVpuMKsXlca4m9CcIt6QI8vnYN0tf7gH3uVuxZ90322B7kUeFw5
Pu0UeqAoBaSyysHuDqXazxHy7oyk4BIWChvcrp7LULlVLcL76obtSwsXi1ORVmpdTi5b+AcD+WUo
OP1PSFj5jpodG+LwXm4=
`protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-1", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`protect key_block
x+agogSsgbiI6PGyBpMY8RQCDzLctIr3EaG23mH5kJHlNmNKNolnP54yJ8Y7nIFi6yl6tlyOLMoF
/kxU0pyFmIj8QM0/MArMxPTiemXbDLS2VKtonyK9dDH7VbjFnRWwzK0Ngkas0+nbW3TqGPAY98x3
251QPjQoZCw3A7W9PDc=
`protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
KNs7hA49BKKrboRSEkqIGldOa3ndCnhjRkSn8lL1xFfKUn+p+Wbc09ogKV6YYnPU/RaF1LbzyoE4
udPSNea4bST+08IjO5GAxXqUugcig44J+hzpGKmh7oO0TuyNbYq1CnYcsZXaD9vsmNYz8fBDoW2S
VK/mYa21mBKTOuTdQ1yp3wi73aJ1G9N6Ngt7ovDUrjyd5oNxxNlvWU8JkJDinbEnci0qjZ3Wu9Wg
y44pHUXf6xqwFYJpZ1ZcGRKl83P8p74+pLzt19lw9TPlTfKI++IowVjb6wo36ztNDJS0QjQE5Riv
hwbPU/Bt3S82MVCY5NAA6bKC/8NnoWMbmX8Wiw==
`protect key_keyowner="ATRENTA", key_keyname="ATR-SG-2015-RSA-3", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
QaRubtGbYrmCghuFdQuTgTEtoVYYLcPnD5z0C7mo18fwCG17qy0y8mj8xWiwE6bo49IP1/JXSIw7
rTBwHFOVrmbm926sWNrF1r3IHB83C5cstprQ1om7vnkw9XX87SjkscphhkrHmi08jjzW4qX96m61
/ymclz5TlAocMQJGz/jwscvIMOrrbuH4SkWQOLQnRfx9GIOv5Y7PM+w/wuDSeFXsAXz7Ahq3/qmU
cylNfSufW7/zfN4RZB4u+d28AXsuFe03aSF1dpW+uBK1xtNZccvj9h9NMN0cuwxt8ZUlLJw8l6e2
hqRfTTZl1F4qnnrJu6w8h8uEGrmgnQG1AW0epg==
`protect key_keyowner="Xilinx", key_keyname="xilinx_2016_05", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
XXj6Nc59BeA5Kznlx14IKravf7ohERw7h0fbO7pT7/HsiPDCWh2DlTGpFUcnbNZslPN2RfE0nJNX
WMzLQtaHK4Bm6kxY71OsXEKm7MAIjEdLwOMtJTtlZrbm7chBbSxcW6sjWvI36jk5De3Yct9Ao1py
DpQ9NICUtRTwGG8SAiRkAXRh2Jv3rKvnookQrlVxIkNRSBMSgbwuTbq1ze/KMUZebBWwJNUVIC9r
RV/i9wjYXBOeCCUk+cGDC5uSpwdLXYV9ZxhQUU6C1ufAaK2m4OIUeBqPc2ski2O0qQYQ67c35k50
ynO8H9PTEROPEOn5c37S7feU+36OcOOAsVBTBA==
`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-PREC-RSA", key_method="rsa"
`protect encoding = (enctype="base64", line_length=76, bytes=256)
`protect key_block
g6oxAkLL8GcWvh5zsG2NEPeSeOk4X8vSYw6rc0cWfXGzoVwKq0xJRmAmNnXkw80Ki6QO6KNEpxRE
3XK5bwNQT4Pdrd2JMYlzNPPf3EZfIhfhrJI3Tjh5KHyyU/1LM74jwWmwPGq4RI+sPPXkN587VnnW
5J3dugwPqSbfxwmx5h/CMB1Krqhevi9iDSsuuoMNVdWllfjNPNTz39e/o0krqVWqlGmKRRzxXwW6
RRXnItyGDcLAXbTlxXLzl5ov1ZTVdZ3u49hu574cK+4po4OM141w6YniIH5vZr8qB8ImHnRQgCMp
9Ihp9oBBY19f9k5CGTpLWytm/dPI2Vay4QJXkA==
`protect key_keyowner="Synplicity", key_keyname="SYNP05_001", key_method="rsa"
`protect encoding = (enctype="base64", line_length=76, bytes=256)
`protect key_block
KhH7tm7QV6fZwtSCF9QOMuYJBzsvB+DkNLQC5kA6K9BS6NLlaYA0cdT2UzF7HC6du/RtfhfK3V5j
XzKi9kV+2UsY49jRUVJtYt23zFJ/55DfaxHe8mH2cXYHjuSC1C26QgPaAWAiDW9dkRgv9wAQzVSE
M+KYStGMJHvrDHsWyS2bDWZkzakay1+wJxvkqarCVN8FbC5RLzLOWQyPGDRBX57kJnD64sYnSo8N
Td/T4H0ot4nzg5ECG5xWVpD/DGNS2bSDDQSRkrx+hG+m9LdcNWXjsmpV7KMT9QlKjbd/r7acXKq1
cDCofiGaAbfyl1Tgi9k2qvwdUfrZ7s+MTIsFFw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 202720)
`protect data_block
fL6xIE3wItD16j4ChwKOvcCmPcgOkwP6nQ38xbuOmaJX8hortvlm8MQvfWYCnAmRWwmPqcChjP6T
tfbCIKkrCTD8zcl2FVs4Tg1L3FNetyufNP9y/LZJP9A4VtPkPMTOHhtW1P2bDHuASEXhLrCcZJ5e
MQenxw92o9erbeuEtQtZxxy8hYhfAggoW4mhO1eGvi+7j0x1XseYnoLoW2hxHGcduuJZeSLcjlTa
ezV4qnVfYFLjYwhnycCp+MLdHWxdc4/uDrFO94ydd7ED+VVdzF2T9G7LtkcuxfGhCx83E5+/Bwkk
tK2GqNTxii/+4/tt6BfzRAhF2yDes29oyGabnVxV3EE/bzlzibz9WnOXO4zqaL6/Gf5NvhlZHZjt
2PNqzvlJPNoD70nIH009mm2XTJGGXIs7/Tme04CUgeZtkODbYMFrChzyaOcfUzaFwdaJFLofa+71
cEjxbvRg9tbFg4TemdGGdv6Mn6n78vG0yltTT/5wUwNqyTLRuEv4ltkdwZkGJw8QRYcmaGy57XlL
GmHLSmYLSMidGy3u/cmcs3UOg3mxccm5K5Et90arxEXV2+1C/Z8ImCkN72R0/vu3X3tCfDiqLaq4
cErX24zGohjTO3fG3TE5AQ6MnGQjK5HA74fraBC89y7dOOz4VewQjqk8UjQGEDAqqrk6411h46/W
ShyLsXBe7J45DKkHWSeSj9M7nBQBreFpv5GBNjDwZSQWm+AKqIYM0XcAfDZ8ktGvmkmLYZIavmEB
ocmTB/8g5rJxKE5dPXsp3b6G3YLhhTCWEZdytosHGLhAzN+yh5uYa5b6zBkDB3YYMOEVr7qrRxrY
aqfPimk0apgBKGArPvIzcSg8n04R9IIRh8qyBDRlJXIullUt3YeRZ4YTh24Nidi9vstuZyjL6au8
WJp5jbUK8hTycMRQRiyzTGzO50FLKeX9NM1IfQFieLerDljmgQe30lReccWFNHdpDXcIr7YEJ47b
Pa7waWNE9UeVoDIjhYbM+rhOplAkd77dn1SeaVJJCv1KlsdWOzwz89APs9zsM0tH1rvyzymXEXuT
hEsap75a/MWF14wtx5nQyFkOXGOP7wuGo1DJWPLfjeJ/SWH88kQ1iz1+nHnBoHa4r2wbNSF0tttz
yFl/hrEdlQbKgNvdQTEyLlWADTjyfD8dPYOug8U9AVlO4q3fqNbaIbMdPl7jc7XFhjQzy75dKvaw
gLypy2mTawv/AGkqro6tDgDG+aww//Ry8llR9AMJl39nz97G7R0z541Ij+R7W281FOCS/CXZAkzK
nsI6l5gfJBuEj3SdR8up8cUxMXb4oU494rl3jBZYOjfTHIHRbv+EejaXhhzLAQkAONP3Ynl4Qklq
fuU/XKRVQnuBXJ/DpB1SsjR74CELGK8hImQ26u0z8OehjbF57Qz2kVsZwk26bYj09ZiwiqJ3r886
Q0N+fPNLKqr6g+jsPjiF7aMzcBeAvvo1hK1uOuNamc0eL6Shl/J7km6H1JlgmIPiCpywpqGxLsIw
gfsczPbK8ZWJmnPL2A0SsYiEmri9g5I0T9sYng92GgXtmwLmuj4vOrzFxBKuQBebmlAMnedyv5vA
KL7+LfbQyQjGYhekgUOI5L9xotAX7d2cLJhVnFd/eFd0qpevGyGR6u49tgMZEhW9kIuDnnj8ZlR4
w7K6/SLgEsvNmdWkj9SaRlq1yKD1FKn1hsnEgaP1DoLwM0/Xd6UHTRzY4Xbj3i2YJqsvLAXK+mTN
nXmu1tqlPq3eC9pKmjEguxIHXtJkKAKCvnS/qs1OdanrK0JufAB1h8yX2XrihfbzfgsG+T8p2HBF
6a78YZbyuFhjK/yB2Kj5Ro3fSaOsEp3x0RI8qMB58bFTeuZDkvuko7+fQNrlpnXKOscQtv/CIRAv
ujapfb183TJJaTMm7NObb0Njwex+iLncDZANMiHQ+PsqP+o/bE193fytQy3nOllRfl4mn06L8iYf
iF5nbgFfGqenkU7ug6Iz93WpF9dBlSTAjX6MqWJD2qRJ61GvMhg7do/CLkkgB3VCBDCJLwpiUZ1B
kc90RCMVWTlqlYj1xBoqv39LrC6WqOqei2mfaaiSNaRhA4hn18BDu6F3nfDS1oyfQpBVBKIRuaIi
8I046WjSzhBcCdL+VKO2++yQbeeOyD06FCp07jVFrSe6EVxSOa3tQa3v7oTjQOQZCov8MKC9mw0U
cRYw+Zm+M+q2JisrJObvpfD04Q134PLFVggZXAEAXb1Sj3PRTcHN17atAn8/Rl7OS40jkDBhNU0l
q5himimSaIP2DT0q6C7sH83CzKk9MqPV5seqeOq4YX74IfqW/mE2wdhqhJPJ/dQRgV99/8VtgNtq
grWp3lDQXdpVzuHs/nM+q4BehMkc95lhu4CxbrIPS631JbrJKaCeO6GRsYnZ5Iz5M9EzwjzeDexp
WBEMjLB873Aa73OV5a/mntTiAuhg5bCdmwS3ESyx39iGDEBTFcM2+GCVI760MCpWgNo7ZN7PI7VC
97l1yjL/7ZGGr1+Gx3w1XMlzgrAPpdEMxhNYE8jjrXCGjjI2/4fC7ISO0anriEX799K/dbA1/uBV
rgoROZkLKlz05EBbFXeSXd8eZ5wpw5c35ehV3oU2HLIlxBnTaJbrBZRn/IHWkI9E7Jh4swkNvlBn
Onn1VM1a4A4Sc8nzSFqL0+p26GqWISxRHHppUqUbGrBfWUv0e2xERS0waGLY/Tl/MiCww8NzHKdk
rldB8vGe3J6fYuNYfwNfm0potfVTY6Z1+hepkVIRv2eebRoTXf9RksszKOCgbTXBiIOcLo/cgvDI
TWgp/XMmwxMdpbWDYxV+r2JoRAUFEGQOpcVN3SBoO6sMTDOcSX6dgg4x1/7EPa2EakHBUyk+DDoP
32g1Px7GRs9OypWPHVl0JE3sL4SYUiMOuQevoQf+VSlTmYRTNqA/r0fIC9i9RuKVm0u/XVbKQ1Uy
Ju9NqUgsDYJq1k724oMbaevZnLbM/9LpvJKsvrrjxZuxcLsZ78z7RXycg55YrBfldO8B0fKuC8iU
McCtV6No8zYBHY8EWvG4s1JvVtTqcwSsvFTnSQzJ/fbWMItDY3mv66mGVkj6ySCzKMyBXu1N+M9A
x3iyGYF47PKxYZnXBhRhX2gcVqbNpwnGpPOHwasc56VA/XNQDvEmQAH0Ffns/SF3QHsI2e+lgFyl
f/4xrdVt6ZZxhCOK3SDFLjusBHke8E/sS75B9aG665wN2nwNre/WVJ9+SxWQ3TXCegw3ZdUbH6Fi
r+6TGe3iMwLn5RGzh8zMXn2wnkWOEvzSQUA9YKgS19PcWdltPbBSeekk9GbPTFpyInl+GHLmloJf
PzAeoWEU/vpOVviFkHEWrV/B1yNUf24kJObJswy8Sq5YFgjP3x9syKFN1KqPYHM9KwtjAr6XaP9p
76y8pJF9/NLKlObZru62j+XGoEzNFIeLj42l4FO2i6U0UlXIP/O4BK5gUVCa0fnsdybzxd6KA6PJ
ZTM4ZVHg8A5L4Q7lVpxi1yEHgDO4IS6h6+zvV19C6V7084EluK9v5RooFdpvBC8TZrU/aDFrdt/l
u9csCSwCEDb2rMKHZquCzGF3lkctDXkC3ieazf202ToQcizJiEKFGJj03aR+fg4fgUsiNT2mUrAz
DacpsXkaOISQDXotnPYEZywr/xSWDzEJNqHTef5N+Q8mV0IGEMxNhHb/Ds8kiDE8ANN1+wSJbwqU
LFvBdmV7EsqwYJ622oPeHMuqbaew9SI/Jy61D8iXyrNkhD/G45jU4Eyc+E3yq5re2DcaFzqCcqMb
B0hIqCRXb6U/8ny7k6SgRVD5IpQzh0eKlsoTLo08PFSNKv1P4fq/lNXFuNkdxaVbNmvFLLAovcSE
NB8OL8q/wXBiUZMagDGqGfxQ9pxOcOjSdQElbglPlaKhDLlf/Xnp/WSmmpxt1Q7ILBKjrrks7acl
sNOGkunPURj+3feTwitNAJNQzTss9+GfnS+RHFu4UZ/PkJcUNJl7j3VV23O6FmqJb2e3a+iYK+FX
j91+F1n2vT4mxVywCs0tmVbT1Tp4a0y0dvqFBb19jWF4B2BtGJBEEVrhDpfMR4W73gsfX8KV5JEx
twjJcYF0i6EUkKHHDTir7GTL9nMHcNKTxuuponAL7X1Jv2W+S+pVXQb4N5NeOGPKwciu5/3zuaHC
B4c4HN+bODWY3w1ny942mj5Q9a8EwP9xjmCsubaPjeCfcI/q6TeIDqDGVzKPje6oDn9x6BH49MEc
Qb3jm5s8Xy99QKWvdazbuxz06cm+TMGfhU4/bsSxm1CCvqiAixPaIFSEmaz0CxW+YKW//44IlLZh
fAs3GDFXnxZymyedMEi0RM1euKWKxjeflHMbelp1stxwGUxdCda8fLTOs+Kat+nvEgY6B79rnHV2
n/BJy+idj8AVU6j/Oa05fgxrb3N0+F0Gr8ZVm+hHQsqy15bp/BOoqqequcx3mOE93gqRilhmBXIt
tkg5GPKO6x6OBZCM/N8cP0iF3m+EInThaYPP7ziZlM42CHg0FK0hy2cmrWAA1RPtoopqhvOZvZwI
or87vh/kPSPX5iQdwaHEY9sQ1I4IfBZnikEqif2Kue2UPKDlNuA2irHL5VB+OLlqeZnhZqQ3kGRd
lrdgXqF2eikZYG8tqzLFPT3BkwAOrcElzHJwd4zWWn8JZw834WVhFhVwbQrrSCmj3SwUNfit4eE1
YlOIdEL4Zh0XULlf5EJhBas7aQay2sHMl/JOhMEDUzynZgAtS3g4PtpKXMLeWkmzkd7fcdrsng2y
p8hVTKLMxpaNMCOghKHukLqdaMHPaYkPH1JQitDynyuqs3S4GyobrGGihbUeoOAD2aZB9yJLcwUv
711naM6x8aSh/IFZZpN5OJFZ7yUfyfxg1yUkavJzAtxEIW8PZEO20ie5Om9xnUto3fuNqj6nJGSm
hWKmvXAj8xM36Xqfecav1kx3xfVQyMwnyOHQXRjvOWLey1JgD32UFwUBjQAFvrkRn5jeGHnTO575
LcCLiUSNcIHgu3wBghzxS5hF6GsDF+U+woz5uN3zyHo5vg9HrDf7z41ymkhE4sopk8LmwtHLrYja
yBsSdRmAbALSyDphRFnCO6r5uJe5oTGsFnXDvZD0ijRX59U0RV8uTjr4zL8Bh83w+QbNTDmBiGkl
t/4L8Ugx+QOmYqtXyH3Gxc9UXgJQZ22RDXPHoNisSsTS/5uiKGXfJglf3vfQsiciL26N9xqszySV
lpq2SsJlhEMDFjvn3hKvjRph20EvKMYoJHVI78nQGXyIEft07nlPdZWO/+k63faHPzhyyko18g9L
Ov/BtmSMgfrEM0PEbt/H7xXCn45eOjCqWwLYraJh0MAS2CvaHriV+EGP4YF6iurmAPkeehO+UkS4
aHc56+ZsulOxB5AUmwv0qGbPeKUzyHivWLoLDAmIdycZsE6gVh2IteG2bfqvWM/u4Q+Tp5PaEvxa
Fw3kgIqfQ/x//UPb2pXy34AeEMDHsjbMzWWJgDXCCR250gJ1B6fq+QHMv4zacgJS0QMhZsRrv1fi
WkOTTeMEKSUeZo0MdobyGwSeTalpY0CVwJZMG3YpL9kWkory1CYHoX+HnPXCDSmpc3Ggf1OZh76V
0SzS2NBc9dEOtzpT4QXCOhczFEn3oGQd/xjwCnIWBDBUNJRInUDHDT1+RRndhrQMrZFOqUa3ToBB
A9EtaYbJ0g4X+bud5aCb1u3SPK3tRJKFg41lyqo54kkIScZOM5WCDEXQci2w42OjRS9dAsx2l5ZM
1kK8ygBCKNXGPHb0OfnDAN+vEoI28j56wXGVa0d5U/Elki0KSmAo0wzncaSkNRmpjgHCTIcZY32n
piUm5RIk0IKBn0za+oT1k7vaN8RPtEWCcfTQspuWyx5ZyiylGPXOrVxlZATx2fikTNveWIfgMXJ5
IhBP7jQAQF6/RvB0/9KN2WmJW+TlQ6B+y74Ot/JlFmL3Yv8Z2QhoRHvXS5B0HauQdfs3hFjRlbyG
NvC8M56dU1mY0lBSlYdOLyRGcaxRgw6oMaPxycoIW7aBux046YqyAOH46PBS5Iy+DCk/e/PgzSO3
SGRIg2bH5lTJSdRflzr/cf3t5oY5RskZUAuE/Io3xdAjmEQrIw1GUiEEpU8c/RP4SbgJgLmaEayu
FSZKpsMP9Zmz7oKfqs2KriA91sStETRohFlMLyA+wXG/YKUuYULn9WMkzcjArLDcZd/b9lGn1Evf
QO/9/j17Gxs/Rbm+oWlIzesfgfGThesbT9ud1c1i4vOXCbqmMmC9Jcb0JcRPbrTnV9w9+f+KfROp
aBLhZg0GrHN5UKAxw0f3yni5L9ghn3vBEGj3Mag1yquUq8Hx/m9zhxIanHT8pGVDcviqNQK0OxPK
VjUOt/gIaOPBCsuS733SGrVZXYjfLv96HvlSscuoI6ToOKlCqlsunho2cYtvnaW7levibMyAVhnL
f9LPpyOyIH+0O/j76UXUT9U2MFoGd141GFMZmFzydpyOfAe9Q/cHTucCnSDDuapV/fL2deCoDp/A
rr/XCvuiHo3i3VfkmEptCovB3v7irX1Elig7vV6mZ0/6rjKl3aieA7zDRkFsfRDafD39hN4N9pPk
v/DEkwy0zv/0SgvrHtibLTnUsetr0/BnP5LZPXlbYMlE8hGqRu7oF15vSh1H5zt6AHMen0JrrPOD
CGlfBrwzSX+AdYR+DQYeg85jif6Yq0VUfG8qp/PSgJyX9lZO6GN0ndVLVRmUpW6sJgMEL2AOrzU+
NexHZVP0c8y6cDyI5qmwAJpLuB/RMAu1MGS4XLulsoX/VCfcyNyhKdj6ydE81RwBldq9rmKmXj3M
PTvbuCvtSDBUzNuQODLftyrH/iWEULBzgf+S/PMFt0bYGADahdUQ+DgopVB4vuX5r6NxTC2g6AUS
hJUm9tsDTSre59wvMAWGjW8QytNdqeL5shUZY3OVCX4rSv2/1ifZwsOpz3fOj8mki0HZ9A3D58yF
yt0pEKObzv28ZoFhW2RarNj2KrCCkIQ8h7u0hl6sX/ifQUi/SVcBu+PSPj/uBeGLIToPXbzTrf83
9tDJflCW6fETRxiOUY3PMztLa7pcoz+2BQexxIHhswDXyh6Tdms7ALat27WYVatBJr4qVM2yvIHo
s8YM1x433Q+qw1qFCgoqFaeAirl9hv5Zzg20q68D+8mPhuVNEag7UwgLM9/LONBxvxW1TzSnYGls
wnozRpbijYd5NrHe7qnOwoPqzP+j8r2qXN2vXYPUOvvsexab2Gwf1GahxpcdPwej+VflAQ9Fofsg
jVoGvbpqigXqDqoGQMHiCAxd3npjaAnW31G3oEA3Q0AYN8nVt+oBUrxh42qxrAUbouZVM7aWGqFh
dAAiFQPxKS7RL1RnAcpej7TYlj9auRWb364KaiyF5rrevaqAMkrJ2UfhUIi62sA3dNyFwMsBgzH7
nDUTpx7xzDsYO50jzUwbFtXiYqrctpcrLqXRGbG37qoLh5suUKPxOvPCbxU4Nu8g84b7SzXMpzk6
RCbqR4uAixlZNlGRrbMh+L4HXgyBALl+bAGcLblYvrmTvRUJij/88FeXG97bsXUMI5URxMbJZeGX
NU6x1GWBwnLtiBc3E8u3niw4+uaJuJs0fiEoQ7oZmO9yEE7MOcOM3gBAF2KOEczmOIVnUTtgHHFN
WNjW0k4AgcJ6TQbF0ytX9y57NDm180fk2OjkB/gjA0rfLQ19nNZ5aQyCvdja+ntNccy1BYf9fiHA
TQzrgC+Eadjb9DbuIxW3RuLdt4FiE3OKqUQivJC67mh3ol7BOkME4XNBWTLi4vF2D3V83Wq8viRb
5ZosEC7afqaTQSVVlKgYGmPpIWtpKuVSqY+4WTY1GkSvzf1hxVf2Ma+94UzDBQO+Yo1S0koQuvlR
gihgQzniEuPmxoA01Iz9fZZecn7lrzYwJRBIclOS9W08+0SVUyo+wdM1i2p65XLheXUTD/hGHWld
tSVaIB+k8DdvFsN5ts79sRIv103MwQJsa/OVh88iKR5sdjb5/g7RDSkeqJC5APmYoXSsjYWH8AlN
+y/J3K1Y2r3dZovTAIcV0Oy+Iea8/UaW0i2zVDdxopCNo8O7S1jAn7sfaV86V22ZdVC9cBXBkzby
8PHDbxg9SxXmmqsEaCkDcnIoJx034OH/ssV8yKpceoT7AHc9lTdEuX7d3/rCD51Bs4raCj2SRs9L
gX3IxDXKgDry7i6be260oawOz18FJPW6x8aWJfJ0JpsxoeSEnqeeGAc8QIEV62LRQVRpfHHp29X2
HgVsOD839bkzgDkkFuEaHpBesHe2TqbiLDqdd3g4wKaHuNDFC4/CftEl3H3uSImE5Lf5g6QUKd3K
26sSetMiD+NaFtH92ASW/FDWwdd9fJ6EnzXIsyWPQXQ10cScvMgi8PM2n8QIP08W076Zrkj172IH
6B+m98xkxv/yYsqriRaRRmLMGW5Ff50Oq8aU1pjXzcv/7p1NNJyshklaa9YXUMbNE/lWTvK+FrwF
p1/dUJzQpymCHjsae14yCdF2WypVE7KAZugWQ//U6qGW/aGC9QEpzR7lQcG4knhWiZcvSvvHvuV9
ZfJh9Fn/lamUS4aw4JxhCOWNQxTkZnR3e1a4lfF/ipkeJ95m+kQpVFfNIkuetcLVT+hZ7E8anQ9t
zvi8CAolkhhLGVL+1Z1sCGmBRWtgsCUA56tjKrq4J69z9EUenhOzXyKBhqzhQLBO4qHSSVhC1ygg
AShAJajfTCC5IIh+XxkWGreKw2SWCJN6+piI5TOhGcNedRz0vhX9Yivv0KLfIOikcuBGhC4EILO/
HQfwM9Lj0iRTYAQ6PiYtNZOh3UXs+lZyNmCEPRtY8UPPgU3IKhqLCyX7ENoAdZhQntX7qrHMoxxS
kYnsbhXsL891Y50yUcdhnsqzv6oOt/udbZFhD36xY3eyX7RiYS6/HwI66YZJPo+2INDKqGye+ssF
JvDIngOMnSwIG2rP1n4f879KVlMIX3zpq8aYGxLepvEqDzkF39UV3oQysYDCD3nSymfM4SSz0O2u
f3VMFx1zrLS4s8uNFEggZuN9F5Ia26l6sBaBLSduxYk2ZNF6sozgQ6/h6kMrRa3frI9jGIC/f4gz
y5nFBOFmecz9JMXKL4Gny6i1TyuOtGQiRipztWCa0t1za2E2h5z6q2cP6Unvro7u0uiA9euYX6UL
qIpMGbc9gbLOwJpTlRE6aF9+rDzGXU63hy4pvoYWEB9JCj23Y+abZ+0g369p0TaoB+b3nzFdU3yP
trGb1IygBol+ByXfgfTIaW3KkrAnebA+7LIn9TghYpUxqXeGrkLBd18kSLKLDMrdD44qmMbtY8rc
5P5feiUXCO80Aku3ARUykA7sUWs/fYiPQshHwRakkAKgkYhKjs40JRSxuITUd3xNwvPVxnotcpVC
Vgw/+LaKu18SJIx85tRt/XZsXIAOd5hDWJV5dS7jURXEVaJN3fUttCGDf35p5Cu/m1aqEq+bqLnA
xzNuT2Ly4i25KKdRFfO7HajzZKjqfHVtSmZpuAPyDcB3CFeIv6KigyqIHJhALejlAUEoCpdn3q1f
ZPhz/eiB6vF57D9bRXaxyVR7W/RlDrKCep90+Sgb3GLago2iSbLaPRFJLAe1K7tNzESqMDpi/hOq
DJXEfz0rnhkvrkof8wuB4zMrUu9ESqeonc5y9EofjhfZTuCmVQS3cBCwt7PyXWiHtRxPI6wcTX93
NATooMsFr7cAgudAIo09gxgquERlFfp0JiByNj1yCOd9VLo1YdMmruMa0nXqObaCfRD9n4DoRu7k
zcX6jRnmDQsr7zhL0LDDXRKQRJURiQluJNgtRwrWbgtcxK1v13tU//9BS/z1l6VF3qAjN+hGE6kY
hHfaTBivMm49GcMXlcwp35mIgL7OEvRKL4crib4JrQeeNRFhGvkzakOOQZG+C90bf8HCSloEWt/1
5TAEnr6DMJAjNtEl/8YBWozLAvWRH0m2lH016pggPadwSpAhex6p6x20yB43hnK3YFNuXjEwnTki
MWcsYS8gU60bx4aU3BdO5AMxiXaArKUKtyb4IZFwv9Qjkv7bVPgcEQxrJg2caRjNK+dbkqwZ6ciT
ZjvEAj1Jsy00mh+UR+ZMTkR6xf64bYA8J5Jq8qCyH0Ny9GoOz0WmDGuKZYsmhQiZkO/wPhxVroba
2Z5g7/Io1NeCghrrVBjd3tpLFVTNGNdQr+cj5JkAG6uQzwMyZcIzN+pLxLqVo2UrYwcsGnCgGdcP
ianvVm93GyBu/HM/sZ7EukJPmloSLvbZGvDQx0V4ZWuwrblVqDigqmxjSgDhhuH+DW1gnYUoCshn
H5VGm2y8fQjF0HkgJUXPseCvyunw78jtir8/A6wbBwasoAMG/OHOWD78pv7SwT85IeR3NDg+z7BV
oTVwz0FEbcwOg506KqLFy3cONGEOE4HDyVlqWYYGV8tOUK29JZYyCzV53A9CU/J+sJZjr9/mkpPo
JYnwLeSzF5XqIV/xe9wr1uq8SK1E3LgM1oQCFHt3QoKNbUu49KCn1GQneggC5XqQCCtzix22UGFZ
hakhcLlujeQCLIfKWJHdgDd21gyquSfjX5Zc/MsL6xEX72B3/Lz5D5wasHwbVvvZdHJM29Nw5iJB
I1k9hEMJXsydxXkGEe8Dr+eV01f/fKqS9d3vt0axlIPLvx6N/r5j/9QLraAwuqQh5aHrD6JA4XGl
+f09rqhUgPxFW7Z7dwT82liGhhYysdqFgVaUkElEkwDCS64AtPqeMHKX9YLZU4y68a8UrEWEzoWY
JVceLUhfLAj1KNxY4z7nerggwhniNjxfHql20vA52r+cz9SFmprNbnwM8xpGrEIe6sPBUWDznuDD
947/s4WzzOWeCeBX3ypgvsTo/43za6tfqPdSVEq9Q2jBiJR1Oiaei3WWMxnX1PtxX0G7ewBDBa4V
HwDpY3uwFGYTlF68qg4Z8BoCt/VDm27EHpWxyGuu5/yRKZ0SQjLdhtJ2ynD6DPmFV2KY6z0V4hbf
2YNOfOXNT4lUwFQ2Np5vnAttnq2WgoqfhhvLXz2GAJjcs/gEETQ+Zslr5/dr/u3N30mEyC/gS76i
Q5fq/MhwiaqIpRtwSmcxAVxWtNpPz0qtEF+GGxGytBNYNRjhPlG1P81ZxU8cf4KFhQsNe1qwxP1R
IcNXXn1lhr/r0D01jnFtRDwvPJPPnTytPzYx7RLNf5Qn3kkVKrQVqs4gLOVnyzIWyk5ooWLS1lwF
0j57p8E6llHKRnrxPRCsBdyCrm5pkacGdOo9jfmO9mzlEBcrEEuLkKBE6AkOkuRkQl/ebbqyttMy
oJ1LVBNrPHhMsX7yh7xx58F6wVCz0yjUAfdxMaY/jmu7N94uhJWZJjfsbC+u6iyCnZ8b/L6vaXYZ
AJOj2PRMbPHpMxsXTHyeEEwBg/omVnJmdJzQUfOi485kNRimh7WPsXRHfFCshXuoUj3JVMwfUuUq
OGI0D/zGMPikCVanP8pGU4JSk/2chYdYYShcXsfzPCxBbbbL5UuMxJo2lDolcnVOJQkyHKfuP59Y
Mldsp92Ooxm3ono6+E7pan4/jhmEOTx7j/jDpK/cDfnFDMbMml3xGSkAslLW4z6VZH2u+IbENNRx
yIbewagA/4Mp0qk3buW7FRhjhi5haYbEOg5cEzkDyOtl5k0WAQAI/YW88J9SfgA88jY9bX5j/H+z
4Q5L4Se0FNRxYsXKIKrk8MLAvLVQNFZoTAbPiXGmoCgxrlCNcU7ALkkP2cZBybGQco0SqYYMX8i+
2KnTSMbJIU7u4A4P7GrJFlEeOcUJ10tkvrbhCLgxRRCtawM6wgt9gTmNzalH5TS+5OcsR5LcPjmt
P+Hn8sk0gCzKKVUGP56l+O+4qRA2mfheJ/7rgLe6I9JAjZZS8JnypmH0QshYEWUMtWW5srtSjLPX
HELzMhjLeFNqn+vJdrB1y19LFw/lUW7oeVUKsVn0WiRNSiNDc/0uZapeq6D0var+aQpytk4pnbOV
7OqFidWCf4hC8mFoUAZkk3hdZA9Fd2ePd+i0s47xPqDebjwSkziVmoxU43iUfdT6ecGoSeQgt463
nCqAbyxah+hlBp8xNDThWtPHjVP5pmDx+LYDxAkz13o6odMlUsvi5io+CGVSZxNZrsRtqpBGg7xS
zQzPcZOD+J/1lg5aDJAFJYBKOBkazyFGlUq0b1gOaDhbNxhGTSPs6xLpM2qo/wp8ky1Q60psbBXf
YHPUz7XkCopi+4Dd5FjJ9eS0H7t6wUL4Ovy6/bGqzBU1H3UWi4zWQTPQgedgQnqRMo/KONofvshe
0nZb/9ZSfu42yq7LaERUFPe9R738CiiW4LzWL2W+rDmPeOaUBVYadm2JY9V9+koVRrGH1xWH3Z2o
dlc4eQJdIDOStBl5RBjyr5aHd3X4rK98iQfrUOZY5jMcLlYb9DnQJY6/y5LIZQvpDyM2tQzLwfn+
tFM2OcZxDyUxTMpwz5MO5+XHphL84T+a4ZH6Rs96ykdTOzqXlUnY7nareMHeKTPlu7ZR9AScb3XO
UY/Xvx0/lMherOeXzl8W9/POpi+gIjJY/tImKpifljPFXmq1VbfJAsHNUgLvtnjaSD9i/10yV1RW
3gBVnVZHNDmvfUWrAcm1GUS5NtHxKfmTpnleLHNC0awaKbS/sHeD48vZPVXAGJE527Ke8Yx0C1Kh
BzyJCkBccpkFjxrxU2HZ24pZMXIfq/ccBwOZV4YCGkFZkAjHI6fKFRd4J9eIiTI7eo/rz57QfVIg
Jl9mq1jowangzI28FsbxRw3/Xa5sM1AdbG74ngxBn7ZgULu6HILS3u8sGLLH30iJ/gmdOuTg5+wy
YXIhkphJRZqqZt71L9s2BHP9IvXIjG7oF9TWlhLX79qMCM7GtUp0MdEEOl4fioEZ9n7H4vCFWv5z
EEcLjFa0CFr1zACMvxbknn7DuTSWDFJ4yZpCVmhK83lz8/efOMQUii2a1HsbqKqTTF0Lw8Gpnxlk
ig3rK00K2FPe/Kd1lj8oWBERmRm+PveBp7KtF1rToaEK4L82LT8l5BvKN+DeRQvrfOeK0C2XaE/V
jFFDmD2q9dAaQN0xQbEQkEi1JQPvoJ6TBqSP8jHnsTPLuQ2b4pdRxGxRyMz9e96L1gNLU3OXdSPU
paCrYx+tIVB4SKwZ/DUrGkgfT3MBWDI32m6FlivtPAPpXtJpxZQMQhrJGOFe0EDt1T3jjPcBmdt2
5sPaDj12Pgihnd1vih24N6YsUjLZ95woAzpBdokl9u6jnSqQuZYVbN6x01Pwh2IfWatMtsSISVcA
1XRAQ5nMxt1chhCny4+qZoQym8HZu4sHHWXBFHrQbnJ/Yymk7eZ+o2lUCllD16zEZ0f03rhJ9ePW
U47YQHKKs+zVs8epNfOznuHYOb0osbyc7FhOPmq0uG3scD3SjvCXAtPSQquEhnF6iNdJMp2daE9b
bD0dXkqSsejue/KAMoVjXovyq+MEiy6vVYqIItBIQAMK/KyWSK7xknQQq8+VR8YdkwhhFdYBvVaG
u760PLpXPkC8IK7/1D6QosgQ+cw2tbZtvO+sl/l0rlZ9nEGSy8cw1RMPL1pxykViiTZ7VWO3uQg5
P13jOPN9eszEQp44m8t2mH/3iR93UqKwx6164xcXPHjulW9fYQPRXRJ8zxLlHoYDEo0ZQgUZA7dh
Gg4GSh32QePuAl8q1LSTSDzzRZUkD8IOM074To0P8Eeq4eG8csIVWBklrHLWxzopCiMwokAcBHN8
kkthL4C6YCj4/yu2lp3Gebj3bS5XP7oXxe0C1ZuwJNyKImVBJSHK6cnFixsngQAKf/OVDo9FW4G2
EnQGy6K/JVYEltWiHMGAFEWPcRNwNezsn8pgu4E58I/e36dOgeU/hatsazLFX1ejNYRc5WQAO6ve
8NHp2r7n/CVxlqVWl90/9ntRBKkmVWyh4k0OEUesQXwQ2BusR7ZUl5Bq5gU+cfDvcEuRiXFrdgGR
NbJ0QXHVrNRAV/S7y1M4luM6r9cTHB5XI4jBmXVaEqXSXNFIjjdO3EuUpDzsIZAhkbt7lGZw0moX
iQ5e01izDeU4yxd6A5DUebsdC5rWUJHizoqWWeGelG1D83QnPR5RzailJLSa1iwr0AaQ7HA75Dbw
LKiDFAmNVsCD0VQlJAvnFq8bJ0bpwtkDEO6qoROsco9FastXV6MfoksXs50OVJYbNlnJKb3/J/sU
8NJxD0qfeUFSChmq4rWS6qbvgG+h+EoOSAAY+ydKYfr7oo2Ga6+AN5DwZi8KGzuK9ScEFEpU6H+8
R+5iu830n5x+9J37TWLTWqrbJ0LTM4H672y6hI+pjSQPqi3km+bGZeBgkl0IZLnx9rhKCNBXaBFt
6/NGhtGt/GBy3V3CQgVTeiQw7RDWYwMWYWRosjUQMNNq15lUD3E+VlX+sbP6FmvX//O4PlmP/2v5
wJAG7q1RnooMMRGQXKUahLHStJ0gQZAkWIUTAFc9qcesF+rQM2CbgdxtxLMxZ4wVw7ldCTkDHX1I
dR2nVHt8mOQwSCb/RYjVcJ8+QV1/uhia+xKr1hZYo/IYFCK4i3ZEYTXxVYGom9Sz4rQhLOpHsEpp
FUhzq0uL+i/xhRs9t8crlUenE+/WyBb6A6WXSPs2i36vNEXrvwIiS/7YUg2FyWs/7tOil+Z5ryXe
wYKadO4b7Vm17l4dJNfsutyS4z9OcjA6oLLVwMUFHQIeLP1WwWJAiwoqdhk4xTlYmaC7DhtinL3j
QTVVw/C1uUvuYaNZ0sjyPu02jgW/qkB8bB8KyVsNwm9Wz5dbuCknxmgXLpxaNaokJOp/RMnexgyT
87hSe9jL0xdPcmAX6CGIA3oGdYlbBkzdHwEseGiwGsrvKCRaycsoRZ4jM7s77p8rErYPzVppXdd6
dM+ZYVLui+n/RKdw7qqzEfsXmGg94TXf4PwJc6T0FKqtMAgV0KZql5q2bJq/h+uVyv9saX6l8Sih
Kq185G1Z082nz5d57nukZIFSkXG+XL/szVadWBtZ7nXVFjtYB2AJHHq3aqmvrmpg1/2VLkT32PqS
NNtXaPNJBgz1KrMXvKlxzitEDmjdoelNZ08x962SCiFmthyaxBqyEL0PImSlxQrjBGu4XHBfzlVA
qcNxoqicw1E/QkD0pKTXv6rtubQWO9Fw9aDE3LvnQ3YjTAZg4TdmdrAoLZUDE+R3gAFfv3+8Te81
cEIQ+ZEmXRjACugVPMlm13Jo4keujZ0+FB5zwYIVygDCAnLMPB10sh/KCxBXRfzlYWtxdPUqkRiz
FzTkBKfdgoRQnLitexuiz+ocAtEY/MnsNFfyiV8avlRkhGozkU3b4x9bQIFLByX3zYvIRmPamidY
02khEZ/pt9n3dNxBfIDWMrCb2VKPLOTnMsQqnugyKp2uUvTAC+TVmXexNvaIuPxU7ltel/fUxFXH
9GHZV9F+Otdsd3X6V0eC0HrtMIw8S+/MAGoPGNh4EFeaxC1qNUFD/P7JH3ZNylsdCRf93gOfQYzz
pC7NzGfekXQtqu7qTyd4OQPit7DdG0BJFF2lt/vOJP46aDPqBMxIAxjo59iKPB7BvlJtdDsm3urs
xTqAOB2zyyTAsd2xetZ9jJ2z8KBCQ0iUWXZ8qOwCP86uvqRVpWAxsjILIfT/g/QmevY1eySNXI0d
NPjhTemm16GVZjLUIV5id9utbbhE+tpYqM5hUSxcmZQYgGUo7FZmCBPgGN0svuApgvuuQn0z3SFu
PfG/Udpv4eLNqbfSnOeApVu/sZrL3OldJPoTtcPbTpbtZR6FKvljCAOpu9bT3XQ3jlrmRJDlgovQ
KVb8/6feR1A8nAFJxAE9b1sxM+zMD1nWiAFOHtoa0z+fCN046cDzBfcVsOrbamn7KGP3ExbrCBWZ
ptZf/xuCsEzCTvI6ApuTIQJl5uo+IvZB47XKdWnpjINaLNRikBsxXLCco726WYqfOqDsrtA9xNP0
Is7BdGuuI19F2dPwUjUZ8v68Fc0Sh0wF0CztbyPBU6Ztf0XvJIq6sijnvJcZ/cT/PjET5jp/gVJJ
1ebvk6hhHlix+JB0UixxKeb1jO8cXG283M0Tp/5DCvvpnvt/AQBgK3rlxW7b8jvIcds74i1KH1c1
FfshJUEPp+f7NldQi6c3Om5KWVNmgNUDGqB47BslqFD4L1o52vVuZ1uTLkSs6EXh+Id348hBXFOA
FQ+Fqojh6Y9U3JcYSelvlLzT2lbttSvifyNKZ+T4ERNTbKRu5XiSIR7WE72A92lk1ZpO4pyf1AOq
+/vBWRexUr5VEiJdCKMNAUFPaJO/UPa1Y3km9ah5YNSRANdKnblvd5sA0Oek+2Aj9+/rOD+5dnH1
hK8EVJsiNJOIvBEmDX4umpj4P2PpoEjw9ICPAwhWp+YI5diQWJlhvjZ+6yjTlfG6O1cTt6YFbs8d
YljZ7XU8rQpg4mL+H1mxnRKGGy+qvljdWuAewr9H0C57NvdX/nQIiRYiu1EUyJWqIms8QIVVV2Tv
y+K30ZqfyYQ96qoknPcneUzrI07NPqSsUnR1grz5ZOzUxR+f6uD6mZ6HwYmuEP4+IPPcgbVbQPfd
RpqOKI0OuZOulQqmJ9pUkk4n+1ENZMhQH7fmiM/Y48iyBKms3Ur0OEOqvIadE1Aed+vs3hPOaE3y
XjIoCprdJ+TVbjw+HtrkEJVROVyqUPIyUpuLiSpFglFS06dg1uVH87MrCfrbvSPdYB5qKUd8ZKAK
HWB/4Rtbd97QwBMz3okTvfN5A8Iz9W7r7nBGadM1EkXNxeSlrbY7/gJV0P+tsa+qc5uHTlBlpb0e
GMZe0zR3NIt2n/3cHMsU4znUwgCfkUFTF/yLh75lxCYhhUxhH6QAvAMNhbYnXPoQe5FNeaCU0nKf
G3ph2MpIm5SQWiBQXgCXeGHt4qH0XbN+57xKIFlBApaMJBKNsiJQtv3nZ8e3MGdou5xiaCQRljUB
q23l/Bbjb/R6AUwVeKTzCGW6oDA7z6CuIL7JuG1xThCji8w/FxG32fIe8Esd+hQw/AtxZVD4eqHQ
goKKUEnQmeCh3FVG6JojM0r8qW7uCg5p0V6gejrAPPZVIGtSFdSyjDBertrt+1viAYmrXniIIAS1
ZDXGgdJcvhWzr0UYYh1k5qexabV8RV1+SUO9nk31l3dtkLvkdxw3/83IbwEE1WHaycO5ZhVISbRO
KufaZ120och50guAKcsk9GB6NGRyTpPSXyyZ+dmmNTAA1xqRSOoOd4Mu2bGJFlMEyH01doFh5F4f
qrvDHO4bHNmQnOBQp8L55GpaFhhvYp5QXKFLy5YeIduNalHqRT671PO//6dJcbPus6sp20pNbF6m
SgpqQBJdxHksMqZq6oKF7qq0rJyrPa5U7W8LNL6/R1d8I83rcNYxEi7NIJVqRGHt8OCcyFMCh7Ju
FzSwOAphkwkr1kvTekI5HSzVn3HoWLqN5EbIULyu6QTzbm9nmRkOtDPz1pH63borKE2M2nLb5YdZ
2EKIGKJo7uKJcygZ+R7GYc/sLJfgjcei+8xF7XtlIiTHcVXZEq2CWrmSSBtIhHBiHrdt/4BnLL9z
iOcUCttTTfuSRKPjAVSPscaXHDTUEL4hJeK0Q62fYIW+FBKTgxtTd/eP3lqZxKL4BL96N2vCSs9K
QNVEZbutFFLS67gv7nOcZVVfGJxwDN6qISnonqU3O/U48UrFr5spZxsOSam/6otFzhaPpuzfqeeV
ByVGly8i8TvR0GiL2HUJE9e7fjUtlTJPrjicziO6s//NkkOo4j0NXnqAdhAnr464vbjtjabr+uMo
64gvFdxOmxRdDpiMojo+q3m8konu+pXgcJiooMoGlvoecM1pJ2fIuMcNhaD68R4/VrPK74yU/y2e
mtypg8uF6a8Me9xroO1kpkFZ1W5LfNpy2tTpUxu8HhBQ0JD2Ouq7j5FJn/ABy4tt8tpWs9PgNaVi
m2lD7IV3VB6XH1t/yXmHxsU62k2DRn3y3KTSct14HqdLuFgRWFdA9XW4p/lXcogZWRk/HfdHNuy2
S5YoLQvSXjq7YFwMjKBZS/K/vXXwunQ6uFGmun+nysqeyxNQj4qILhNWlf9CMgLRXhMILklfTWFY
qayKG0TXHX19ehUet+GQlHoH2EFgJAXvZL3akFhQxb2/AB7KiDz2v7W1CY4oGx/KGRxKYHTQRssB
ZstMkLJ4LS3meP7F/iRfvgqfSq5Udyx3cBwUuEJ0Grg6wDReLsHA3YI5ayThpQYMVTkGvFfqpCk3
a7D1KqHQO452Ssqo1GadaYHrao/jIQDhz54WSiEM4lYl1oZN/pwTclnZLg+5icRFRMgmRklx0BQL
Xgnug9tks0qUhtX9FfjGcBlj/U2cGC/T0h6hKLM8vv2P5uABJZPob2onMzvz/UeWaU8sQryndhnB
vAxE3yKJDDQQyCtKTdARi5BTZxk/Vu32SPNYO03Drqi00R5dsUnDs6U2Sxnmr/bPRhS6x66cLldB
JU2SJl9Cl9J1GSyEDrbpS5Hke8xPta+UU9Zq0585ko/hv41O20rCooWqLAjkw9UKkXQTgTsKNSAW
TkbWdVmW3TjtbG74Svs5+nS7ZCs521l1L/6zskykeZwk6invgrHv43dg1evE+j4NB+wgnP789Jpr
/6fhRtne0GA2dToSwve81TWbp5I0/vqO9OR00QwGq6wkOD64Qoet8wjs8b8Y0NclwMOhXQTMkHao
pMs0M7RTKSr27/cC4cGmupwuf0eGySOrV93CWTvS+n5VZ7ZFeT8axEcVnxTEshM6kjLxT0pPyKta
nMdwxSr0m/L2+zk7+q0leLdBp8gXgZ6Sx5fPt704Bm7gb3l2y2qjd0fEMz4r+99GicfApcb00cwV
PPU1QVwHQGhjbk48L6/RBuJ1GJDJ/hoW/jxFqMAe+FsaOJ4YSLfld5wCJ8FvDoyWjqs/oySy1PJQ
fHxB5s5On8c0DMNEDHJTfivNOSeWf5vyhRrPPXMy/f245kwD65JVOxZo5BIEZWzuWkXpIo4JqHdQ
WOwZO6BY4NRnmPE6VOvDersQyKmSDKL+B+tnHRZOzHTBhl78fOWvKMu+N9SSqxmb+OrndbtTGli4
O7cTsqO8kF6mW7sk15Ue2eg+ppesaPGmVWEuU7LtverJahor9ENfTFx8MAqrkhG56vbuSzkCcj59
SELa5t0xMxVXS0l35KTwinwiRf2k+Sbw1RaSdeOuxxY6+7QZ4ds4DptA4SQn3zhXu+KuCqsFk5h8
3qhxtVQ2kms/rwsVaJXsREDIdjkxNFlKLMxV3fUex0ydLu+CPIN6BW6gZhb5bCflf9F3V6h19Agm
QJyndenMSEtvw1/LzXkdgWZ5CmQXrCQIPUPNeKJaAX31ZRchNZMLAPvRZSuV7P/2ksxVm1CpTAdr
b7XbYMHoC/6YbSQkoDA85nDnbTCkyw1pPAqMVdf4n7KrRlJrDVwuIhqT4VXcTWgtx77OjxLva2oo
POnSzu2O59ZROU3ppF8hqijvFqer2n3gXCAoFyCH2EcMNC2PsSZzTW0D1O0VZJwCLrcBIj5oAJQT
xdWpgp1CIefo5VNJwZaPw8G+FUWvZUlkuxg8asVP8jz6YLfxK3LsIzrTpR2DdpO0NXHgk00g7wc0
k6RC2NaY3Bjctjx7bmlHoQIL0uuEMS6+6QmeVMAFEN04Pn4vKJQ4K01yswIagqhPF7qvhi0k89aL
FyiLwDCFTojlRwdc171J+S1lCMZ6E4PMip/Oem1k6knF/wAJhAha9OkKqMdBrMUG90xaNmDcfFzd
vFEcOU3i9+kRa2nAaqrMTSgShqX5UEn5z9mkt6PQe6OJJ9JcCoRma1KduX+0kFKVLs1Frq4Da7/J
f0pjkd94imX91kURrako6wF9m4dLkdFFR1gr5FvlnHg0HfKxVixBt+1bVbCxXlY8fsXvJUoWFdPJ
HFHoH9wniFz8KfKgTgkGPyN6MBhD9LJ1KGRSTBwmFm8JbdYKUkjQ60gcdUmJuIL/eUtVLU7tBpEc
dciF6tN8cyWxOqEkBtMKssXNNUgV63G4k4UcOVgmiDQa74d8dD9eGd2pnMnO6RURkxnSOpzlUU/O
Hf1flxt3R8y/ke2mAAFGaa+2Z5uTG/w135E0QVf+b4IUW4izITbiVbRT6mnutCwCryNG/33voY6Z
8DmUmVrk7d6HjigHVEwo1Z8KNRiUzGYAs4tcIg124VwrdnqbQK2TYv5/ZtObuDuu0Be/wxJ7h4GD
ukboekM0KG2e0mqn+MUZtYewW1qXDM50uZcUZPUpHBzVmfuqvamR61bb+8PTBaz4+POcKW9FZT2C
e71+CnqY5iYaCFs04Fp4qSEvuxuY4xGRzMq7nHwbwscxn6vUvE+D+LzTnneqEZB6qfXcp3C9lUUb
v22BkfFBgSc7M/r7/RlH63faWKJpw6AmA7Lw17u6acS7WkSCk/X/POlQY1SGDgUbqKTU2m8jCOz7
zBz+wAGy7YHMmKeN2j4rKSymQVfO+3/6WPbyx+XakwRdN8WHpDEeEHNhfno1XvRB0ns0h5DwEDd9
fS5obLPXPKIUe8+GHwjiyA6ZBcDhW09yYOSTvLcvblWt6e+6VCGNCbsfAfp1GMXgeC5SxFUcVK7C
+iWRDQfyQ/wkd5bVpWCz55WTUU44lstDhkfFX1mikGXQhVEODwBhICjpRXruWez9DTBhjd/OXmYG
jB/MFRYNd5GOQRRix9R753//7v+izlhI87BLUvOOHhhCUA6WmajvhrzW9dHEDNTXFz9USxQl7JZS
fhwNGb6DN2qXdvsslB0XDcN24rj7/jv1cHttuWOhE/nIt9vFDY5/sU2oAgNMf4F7BkIjp2P9mVy0
bZggmVlxVFUJjG8btrevWvDbowhEeMULBO//KSGmbgRUobGOnr16JDhiS7eK3Hxo5WnXzHWNWHDs
U28vA6RWPtpJ7aCHu2ikfKFl0FbZQR7gGZH8ZhgzFKOQ5/rdse/N0pBczp/3k+K/wwERXHixhXOe
47U72npYmvWWDK2pW9shxpQFOj8gjDFEqj9e4L/C10YxfxPCVuH+j18ZzWhVZ7PwEyR9r7T2ZjDl
GzQ/xH32hl3RZzZF9p96xKaGHMzaj+VZb0Q1HKYZePHWA7cbgZUSsCm5jn8BqlXTGRxXROOEOmPG
jHiBSsQypZAzqq4Ymb9BgE9rLFWLmFLWUn5OyXCx9k1X5HtvHQHMvTAbcLed7Zpdh4/j3DdonAg/
STl5+VUhGrzk31BrSYv/QjOL7KKSp+58JoQbmCKb3LcLBGm2cyJOyjhbXmPoUTzuS9ZQkD5hNB+q
A9tQhPRCEoSsuYPXykBfPid/BagepcCjj/P+8e96VeDoAW6bpUGF6oEu+oh7XlkM4tgjwzBqwaLS
mA8TqGG8G7k03+tXDJcQUv1UNuZap/yv2yXtUtWdCSdcvpjAjbpmbSMqwh0ivarbMQpM6SjtqY62
KyibKI13Z7hCYjTGlHzntqFR6cNNUhtTAkZ0uJMgtWniTAOD3rvIj4x7RJ6WKNa69xQempjt6L1F
hrvdGvovWHztR2G2zWqWI9R/J9gxcuoBDQ1W2wy5FUf1zztjWJwNCwxBH62LXTkVoX4J+ZQ3rYpn
2/bet2VxY+DR2PJQEE6HQToClSgMeDQipE13XTOuc12Mr49g7vGKCoSushhbC7nGyKMk1PF2+3TW
bXU2xVRRbefYUUiZ/tjlCuIiKm6xPrMEwW+cO43oQivH9PesfrWRQgj5jJGzVRN7oTk6Kvr6tr6R
9Ab1KK7sEYk90u65G9GLzI07KqYKB8ZM5Zf+vpZ8A+Bu5YyX9At7bR/pT2zAYbK/pwspLyh2pUCs
xIBn2/EeE98YWD7VuK64q2LZVWFOwAhHYPmU7idD5LwifBKEBQGhp3qavR14G+Kv8p8Ky/LHqBLE
bGzkXVZ4Ib+QbsMa3cz5gzo6xrYNafsinlCK9ZDVrvRCN9neVKYOBrI/TkdSHVxcl7TRlSm/6mga
YqxY9SdZ4lQIxJ6hb9lyV3CCMVCAV1lWL8d4WbBVMD5AgAEgSwSGNaYqyKqeTgfaWnGFHqJy54yU
GSl2InxuSSeHwOzF3Mt8IA7UW+j7KIUp5p+uZr805FDDgdpCAGdGpQk693e6HoMT4c3DaVm3gaMk
mOSWPrxBBrhFfFm0Opn9Wj7zLgDCCF47S5Y72Ry1tl6BYB6leKpF/oyrm/+gja1jySo3eHBMHY8H
5Y0TG/61yca4WZX9WUO/0yeyDMeP+2whsrAgVoquS8Cljoq9gVksJKbDPbPftBrtQ29XuZumUDLR
kTdY8PEIQkqENjJkY75GCMzyh7eHuhJd5hq838x/LjlKGxKDjkRzcIEtm5A8qKp6+krsHmpG5NAW
roJM2saNSQyVhAgxGn3IttGV+ug+/sIdRJz//+A0bAzmkVltgmrbVLAJ1y99tXb+AvhuQe9l51ne
wcHb/oj+9C8prdYJ0gFtJFZjoqfkLTDpL7udj2qfr9h7PjlXiC5N3hO7vrdkQxeSMBRNSiFznLBQ
sfNd9e1wq+dY7ciOJcodAarnXvuopA29MhE5RQAX1JnLnWFkFcyvMKxuJK3fnnRyOcGWgDZ1AKPj
jXkX4MKatQ0FmLhCa64uzyVRRJPTsb3AObpl5vI/Jv2C8g22Ol4tInblkFP1TL9We0ihrnz6Gdad
aJjj641HNU8ag1eQX7CgpH101MtqmJ2vNfMQCdAu6Cne9CAkcpRKHhtU21p1vhL7CXJPSLSvwvgs
THhrV8jHeFPAl0B7q5+zxNSlIV12OwriW3sG2SbYDlfJCktDtxfUggORwMeTlW1dTtStJQDm9nS2
E9xnZEQHRSFKFsIFClLJwJ8Le7RhkF6ymYJtqU6hmuPBtg3jaTpkrx/zF9HGUP3TUNPbNk70P3+p
GhZItQZF0/vlSyJrTsJUGcRED46fdvtWtWv1DZ0Q3TV+NE929O6A6EfVRgXTUHwRlMGlf7dGs7wv
1RFUs0a5qQVYvZby0RbQgsT45gjN7KAuI2XmTkWkobBzK08rZY5UdLmbZHU0V5OvA6PHHEnllS3U
xxzuwlaCgQ/YfJ0GAca8Oyg5zsdFbbPQdJ0W9eyAH0dKGg8kK7Hin94Tw3zPTLtEY2z1AmBFYGwz
Zb8/W3kJ84UzXNgPboe7ay24jBLriQCE2ASD7Dmgbi1fr7DKFNJoXL96nIAK7NAGm1fBIh3wlmlS
rIIxMQSr2ShdmL4fTUUMnFHMdcfNnfMXZqXIFtj/LCu/+i0DWy3z7iw/6DK23mWeaweXRyET45Ge
rTVmSscJH+iW+9yxtzXN19mFUbK53TuvEW6BYvt3iIlWNQpOvn8Bi8B2nNoyQmg/Zra269X3N8da
s7hhECTweAwm5Q4cBtea+68bXaWAzzaUK2trhbowbQJnJMyWr2VqH82LQDOI7whwa99i0bFl48ZW
CxC5r06tMF8esHFKvF6J4/MClBUqcjkt4xcKAbHya4wznWfr0o9CC+nXJd56Obyj9LisDS+HrFTZ
oP5vO4akBQglcG3NVySwABthLNO1ox5c6+dlG4zlKpaV8SevgDGWkr9PgImPrEyLeIwZspNtilqw
SMa9CPUSJtoAcH/SW2XtgO33ajJwMXiU+n2yItCd+EJkSup/ivpjcsaHb7rMVIIqVSCP2XUHzH5K
ypLHXMFhpjog9wG1g2iRCsDrJnlTomYsp7OvNs6sYn2TrRZ1dxkob7ORl9B/P9qzFIjWu81gw8Fv
JA9tRoZ4LfvfmMz44Dxj5l5mCE6qlFZBlz7QadifQiUcMulf7v+zpWWYA2ueAKepTUbRs8fxXyfS
FOBGhUhseEB02igk5RSmSx1pHGUAzV5kM1UcVEzXPgrCSf/oL7NsJFQduMmax+xkw67y2efKI3/L
rc0ElXvF806Dw+oPfKfMywtFghGGS/73dZ1ypWfkNH6waL895fkchPWpXqiDUire3oIDZbDRYPPu
h6DMZzlniD2cJXUX83P6fEI3MMWUCOH02sF+H4tylUq0ZECsGzDa+0m6LstmYldLJIKY0zRTJw+p
x4RMjesKBnlZ99lN2/e3WDswFLqSWrCtbi5P+n3NCWIcTEZpXHv2DnoY8Om/rw/16A22pLal+Os6
48qZETAhahphEHSkU/R/ig47k9FV6aGnCBTinBhKetbnkf65sAtIfVTPaex+p2sKUhZAR5+biY31
kI1bnQ/+2ipQcsSXYHnzhDESze6Qszf7XLwjMjs4EnbnqhpJ3hE32Fmn4y5Q4uKeD40cgZwL/Up8
GZtcsuODcqVjgEDL5hfCFkFThKlnga9CX0YEkcFG+nL/qZ2aKelENI7hSKoDfdgpYeuKf8jJcUgW
2N4/JplJttBsvKjgGdYF0HdGuUsanVRMIByrTEJnsdCrEcgunq6crxHbvxP0ew4zjIEg67RcqQAG
shcCNh6raDhOzKtKZgHDQW9XsnRFDzCvw7C79IJVULDdH/frsYlJM6nKkvwHMUUVKdnyU6EkFWe1
3OyaUdzQHu11+ekg0WjQ15hk33j5mdY+EAz5ATpS9JmYIKDReeENhwjahg0xDuqQIlpLKS9DXo3C
gSK/Mt0Et/2iDk4XM4qJeUISWoYrbO8Yg5jQtg8CjYi8pTr6ygB88AZTvhoXvrZQL3CLHm2hgNuK
OR4HK1eMf+zMg83MutxuTAAV+F4M5CoEdNDJQKkVdhFqrQMT41XYjaRtMsGIdzZ/iOQPONhYf+sp
oJduOrd0shK41RtytAXwf9PG9BWv6ETooLksG1Tf/PiAD7SQCXgYw5/Z1oRgzyH0cGm7nDMQeQaK
ouHCjX9HrR41hov39DNP5K7aigeWgMpO7YEHArd5Ko9TA/9EH/dmTNJOhCWF5WFklg9fw8jFI6/5
V1XbjBig+dIosrgbG1pybNH2Qg1q2Yg9MLQVc1mRHSnB2g3RI4yKGq4RxAb2Ve0Xh7E6w5gu1RRn
/JKD8MD/0cleb13/E4aAUIewJ5ah5w/OIKXJxgiPBPNHkOrtkDWJ8zjjpGrBbeMnwi5OgBj2J6Wv
fT19IdJxgrwO8fMR9VlZI4tQvtJW3zOt0l2CUh0PD32+WTFPHoj3qtQIvg9zOMf/rrnSutEszOyS
Ig3P3S6+XimjI47wXWPMhHVEHXzgQVU7MEBqPEcQ0Etg+Nx5C1hceLxy5+UbRUO54kUMBEKvrdxJ
D2EVxorIajhgSybAp9NDQq2sPI5DJAmiBIL8ccxCBa5HZ6RQQLpsLlqmfQvERW9+v2ba4naeFTTi
vdCmanhO5X3Tn1OtnlJkYtj3Fz54Pq46tk1GOia1OJxDt5GRLfy8XcBZedvCPiv0O5C90qTCYn96
scIpSyHA4cAcg1cOJuJeogRf55xXsIQpbxjfM1/3tgzRKKUkUy440f6fJPOczkyhQF+tPLvwKD1U
9Vojy5fCsySEbzccRP8kk4auHZdgeFlAOLbeRFk3xDl20pJOqiFG1O0UXW1OFGXLvv5wbNTKblaf
eryQp4W/0ML2vXDmVtNgiLXR2RmkffFIlzlSQN3GqaZEBG2d02PLj2LAH+OFiREnfoNwyC8WGQFC
pBTdkQWjOMSlF1weDaddj9BWvwv44e5efNoIW3ney/qb8+Kp68QcirWbudZgYlxx2UwFv6magibY
JJApDliWeSm3EG4fPw5g2oFsccpu1fuiCAQh3r5m2CC0+1ceacwkYwu+olYLjy6Dfp9W5l5FvcQJ
16RZHXHOXBG3BknDwJ/uol/YjLpn+Sh5Vv9N5SOoix+scanhZ1LhaqrVm8sNH3vPGUe2Ifx1nLV4
sfyUX8xlzyhOKT8emlL5IVWNaskHZnqVi2UM/Hk+KHdSiLo2EYsDizvwR/EVFFCeBHubumc74iyq
J+F8L58Jmt/r7mZDrgJ/DLY34uSUj/ZXtL6M7lp+D5NkXlI36jotH97dwZM82I8jZCH9f4G9JTQc
vm/HoAMSpRquTgBY5efneypBJCRdJvTkB2YkkZLyUrgWwsDb1kKIbBPO0fg3RnDjGr/Nc2vjgrWF
B63WI6IBO1bZJOD4pTpGv5a9Vsy/vXDSp4UdLBHZ4EJoVDYXSDk5HzL2/Byq+1syYF8nEmjhoAWh
xI0lMD8vp211dRZehKbFL+14iuGLeKv9Pvk8ZJcn+Kph/+zpGV6snX9JfxfIlTRi3XnFLflqAChl
8bJJAIDW2Myj6faY+n4P7qcYhXtJBkLyLwzzO9vkVW5J8i86lKE7B27aHWX79AJbUKXEgMzydVD8
X+wTW3gdnnLYVjh3Gj4LmQLtPjzR3+b2HddUPts3QJZAWxFghDI/brWTtRMa4MgSwnd9UTN0phlE
59GGIyhqSg4+E2TemhZjmaouuaOwIDnnP+3PzW7Lw/KAKdtrZPPb9PthwuuW37K5cqf0AkbabEl3
49HnA5Y1F0aJY7hMKyng9nZTvnU+Uw5lZeXgEhsRHwxygkMLsFWeNmURghXZ7GQkGxeWAo/8mC22
t55URIHI6pdDGYN5y3H9pAbmgzcJN5aSIXExHi6M4HxwO12FTi2zbzsBghKCao3usZWc0SL39tr/
yp7KYe4fBchWt6RPtM5GnMXbn0shrv8O9UQ2TrBPklQvcAlfudvZaqx61uZhSIB/87d4L+0qCZL4
NJTqPf3xDhwJQTRXmUt+taFwGXER9tpK4v4WBPjeNwwrJGJedC9jQ32cCwvRWh6rR083ZZPkrAHm
Scql8/BT/Kb4tPrAGjUectWDn8QXKiXAe8+ou00/RXJC3Ra+qvwL/AoyJERBgPPTmhpbNZaMnWj1
Q4FM8uywQf84Zo196BRNF5yKvxS6DCTjXj8ZoJz5tQEMvczS3lptRChgS36F0g+hI35+8r5DGBCs
Ki0ZQNJwdY98vK+SOoVM2eXUQ9IIeEel5mx5lahQ5azjaUgs3hVLeSYS8h4lEyH9y5bEN+GwoBsh
MAu1ikqTIx6TDfSB6+m6pFhAoVxuwiPrH0RnS35X3DD7bVM7zanjBhhIKjX/jQQ2T7u8IP21EVH8
aoHiWDL5ykxxZNUsAEpX/iRue3o5DsFsEjr/f0rMdSAB2PavT6NFEoJDd0SztumH+e2Czx212VBv
xCOt0+H0o2u8GMqt6U7InJaB5u0sc0tTknraci5ydpbbMxV2SsUz1BaoFUKgO9gFOUWCmVKRBHZE
zH82eXuANHE+84bqTKLsYv9OwDXIRPct5/qL169BKv+8P+jufwtw/8i90LilLPfKyc2phledtO9z
DX6xCVJyn8MwVpc6OxrAVgtZOMTQXXcjLmSWsaJer/NRjaTIB/Is22uRAi5IDm4dJTFi3N44uzDO
MPBeYGVK3/Rc1VXJpSTinN2iMTjC7M39wH56RukEyQghwhFvobgt/cGxHkDnhYhLOlNPF/f0g4f0
RDJnRFqXJLbysx8lDG6VZxw1sVK8CkiucIF7aG2nP4lyDNmr7RR3KXO83DkpCH0w13XkgGds7tIf
joJevxQN6K5ic/oqgEXII7yWZe4tTKOFoQJI7wwtrWWNH/XLax3i6r0NkUzjrzoVLJj55Y8ilBE2
SQDjTZ4s9t+/2jA5GurdjXhpB6YM6uenxlCpXlYvni6PlP100PRVKJNnJFX3xtwPcdfLqZBGIpc6
SUuULVlMUSsHSAnBOwP6XQZG87PdmoCO2C2oly27peYnovZtoAMXIguYuQ06CFKJMY5oCri4qoCJ
Qb3M02h/kuxerE2EXZ85+4EshriA3RUz4hvDKZC2iR0OddvTYmxOGfq7Z4gwFW4FMDc+sOr1KE4Y
A8Lim1FIFvnqo0ogUADa1W36TG6Ky2w8k+Skhw6CQzJY2dwTnE6oR+WFanX0ZshudaUOsgSSmxTx
lU5m+tka5Mr724y+KdJUfrnQIGuWIhnFdSQDAts95zgHnCcj2x1K6HSWsaTsieuUFYpdT1ZFVWIP
otcHoR0WB1C9IsY8tiuAGdVi2+QeVzkqdDTpXmxGMt4Jni5b6g/+FRYZs8oi5fH9O+r7NUXNThFm
MY3AOMZ7lDs78OWI4wYAH+UtEAA/RwI4Wvq7Bmm7E9+KaTfuIOFGoYrYge8mq51eFzZLBs9xPFnv
2viqufmY9SuzoSsh2i+yBGlYdh2ILAHVjjlLJmLrlIZp1C2HdOqKSvNFY1Qep1JKMnj16laa1RnE
L0AFsV1HdOHUKb8U6yZ83h7l5vXWQ2LaKiTCZkwBEJEuZon1lZbN57wsmqRx0P95hSxnzXcs9o8k
ar0bArYIBSS1ao7L0XOdr+04yxvjDLyXI2lpf3MDT4FL7oP7DXHlNbz9GoGSZFzN9CTShalFYuhI
X7VVgXpwJsk4rivJj9+42QUmfBXRBho0ZkPeSfyU1qtqy6lIbwVoe9fGQeAdam7cR4OVc8NYVLDs
wIj/sE1WE8OWFugxq0+Gj4bQVGdo7VRXVQIFlygymUHDTgvZuioGhkJ6rbBU9QWB0k74UzlhQo7i
2/bm2FYyK5DJqmXQ76BnJU6Dwj+3wAKb9EV2rYvgekR3AbMiU4OGNtONAQDWSSjofHoN4sDjZsf6
WWfYKrCHIK/I0K3/lqzY2TU+gkPdAHu3hNrmMqLWT4wh20E+eXEPoBhlKXuNAaWhEilI050KpnMd
cOYMAuKbSBfaJhdbmpxVNStAZJqAEi3CRMVUhHQ8cMiO49IwIgn5pAynTIynnN7A6Z6KzZoDcbkG
SvzQ5gmiTgp3A6U2h56OqJQyqM7Q73k+3LzGCXgF3OMLHk+yM/Ig6ptRQIm1B+/PwbnXhqiqU4Ta
GOgNzsm/nGp3dQATzpZ2bb/rjQaUiS0PyL4XcMJ796KuLRc9YSjkSqU7WUidf++tN5w7qJNPoLMz
GNZ7CgXgICzp2ZkDw7znj1oLnIHWAqfX9rA4PlKnJ++JMWJqpp96+C5xbEZhR2RJBzJamQ5O29hC
Wdm8tssJewE43sI/o3C7AOSNG8/RJGAyq1RN55D05JJArCEbILlhf0L1g4Vd0du/1xPSYebK8Hwh
KVVa6rF2ktHWsQMNi63v6cvQMMDPPqWE3nMT/8QOnmDPQgjTFctQxTmt6N2e5wEQCJGChC3rFXBv
rhGQ69HyeuD48ZZfnlDs57C4LESyhCG8INlc9KH9nvQwK3Lf/Yf4hrB9Bu5SPjV743O49to7TUDE
ZrIrxoOUFXDs8jFqSxqPfk3iEwQVOUNM9x/GcElFp9BAZ066Ax8PbJb4nOj+7gbmjAG+KBAUc5qO
bqrdQ94zLC3t59rliU4dYeUjl6FHhydtJwvCDJrzgyyxfZOpMU3cHU4gKVv+UyjO2pZ8tx5KKjkl
xrPZrKq8bA8IFVoKj0zQU6/GeL0y3A+2zONVRPXzB6jXJjr436kbbMoto6/0T6diP4WftAI95hu+
X8/vzdSFy+LzGL4PdJcxqBIJNCyqXPvg9M+sUJVpi6pN+XF6DyMpKmCn9wGjDDhpidjlA88UKQ0q
3M9YKXU+iQiTCQe976KFWXlXOdOW6ATLB1UziOecdhK6BBYSlPQk/Lj2slLS3FOr2hZI0Co7+cam
l7xLoWqcJ4yh3gzjzpOQnXxl+GmGKluy4rRyMb53itPY5bdNVcAf9og/pelrPY5n31spcafo8Q4O
3ygm43padQ3um7rh/UsQ+dMUAnXa3loSTnXjC9+hjK5v5Acde45OnOK14FCMxWOK/POpGnS3QUUc
NG48mEFJ8eHMq8FQ3CQLFMiTb+o4zBxjaKfcFF27QozzGG3gML85ShW8c6jkGjDsC/D2dsEVCNqn
g2QnRxtsH+Dze2AsThHoW50LoR/Spt0FU6NIE6M2HD1DCniryMeuxXH+R/+vATJ0QdApdWllVMq+
5M3gCQNkpJBtMynJzaX61Q86jZ+yKeNN9rZ6w5NDtKS9nnbO5rnWfRD0aH9hJJ5nVH+pEDJHORq3
EHQLTFW/vIodtAGTfAqyo6MgBUFwQMcAiq3PNnvIBfjbuJ8p43py5UA17XAiqjpJkgwq/xek5Cfm
F1311Xve47WrcmDAqmMBpdCg9NYi/CqxAoautU1mmT0xJMJs36/o8imfsrV7aHFDf0epAh4ogXdw
UqiyuxM4VAqVFNNDyzK6nGVDqquxN3Hn0kDuzVvB8/ukh57OWapKikCULkt7du4yLPDGkVZcnzZw
rmydUzOztZAPurcCWLJ8TdyuW78wVFPbPrr+f2k/aruNQ0P2ottVSapZF/XURmbLvseFxA0kI74W
Uis/4egS7pW6roAPIKMWfUeZeC1LZT8THp9LClfj88FZdBrKvZENL+AdWS1SEoAOubjrJnnhrRr6
QjU6XveqZKAW1doQAEHv38X3lBavEFdfq7u90iBJWQiUTSOtEB/u1aKwrspLJsm3XDX0VMuGCFet
S8UODeuwBb4H9m/v8h84T8uT7L1vFZ++VA0ISi/KH25CwQvVeIMBY2hBCGKEUu5/ypwZC3Un7cJT
4u5lGs0lRui/0iWU9tWzYDki0u8IsGQgUTk3++M0uEZjJ2uwH7FGYOzjl6b4dSuIQZuVEFMpgown
QRvwIWUrqVH9GBUrXYM0J6YmMNkOQ07RmbqCaFPVFJgZb9AVbTTxGvSil+F4XHF/rQB7xjjkulmQ
2vFNbu54iYVUaTG1wfDHDPgcJWGCeo87kcpibJl+YUWVU1VaKKmTIEtCsUMMavs2vP1LXbGxjqkA
M+QonoqwwxVnYvlKwzywc7TNhSlkJKHGkP/+j6jf7CODXPTYfvuXQ1wl/e7cv+gSV5EibOOmCVRq
hOf6RBq4havy5FKaO+exFb2xqZ0WC2+jG6AC6lXcZ7ANux8f8Rl46DZ3rDHB3fjlJUAqPhr0hC+G
4dJqZThpbTFkvDnhUQ1TEUdlH9+uCo877rf9s2xoZJwjWOgOQEUmTZQUWrBNGPIWqF5e1l7xg2CK
NtKJpVBVbAWx1cK43UTXey9GTWM+54+I4dp6fAiJ5w2it5a8dE22tFUmHwaWafGAKUEqO++JKpM2
AyefxzyHpDQjKL0TS/noxcbVuvpf03yoSHLKDdBquD35AiIjg5UZ6MDXEmW12k76rHSBzMihKI9B
7JbaWlkDi6T0tNwli/3sP5rAhHKepD2wTfvFOGd4sTQAKhgqfppAAj3D1RkOcGibPqRL8yqeBzMV
VxTs6Q54VC7x6//hZDwS7ErGYt4kx9VB5FLKo0N2O0JwEEFYW7vqNBbHO3p5YNtsndpVXsVbidLP
XL+7ZPFIyUJMU4qaTx1NGiQSisesLyVsTGFb5CQbMY08r32ZRzhxhJ+F+qlDHwlREY1qVASqxUdR
Qn7003F/3UbCzczttR1/TZoVTQzkehRue95CvanIjEgqg/9UYHYMWXJn182SOVZ6a1aSG+SXJ5q7
A12nyrusz9e9rb0vItlEwGQTXcmIrCQAdRziIl767PoDh7vs57Jk8i/I68liIc30xk81YRK+3zOx
QOkCl6Dv9UGOQkrqoT/UBwf8pgJvZWji2/ORuTVJjDYW3Tx4cQaEdDLc/Vzz3Ltvinz2bojO+sFt
OQzgXgsP0SMB8x/OsY0ds2uqSXNLg5kcekpsjs1Drv2RikGWqVCHnSbc72ZTa7aFWNEwA5hfwPNK
RkBBaiVducDq5yPctb2MXNkxVMtR6QHFH+ZFVbEpYuV+RYsvbVHwHey4E03G4lHrmUmRpkhhW8Mu
7nK8t7cgIRFpJzRcqQ8zM5oXwV5Ei4+BESF9Hv5VEvb3X0EcZ9PYCiv5afEhpYWvhTtDlmfo4+6H
mHvG0WR5TX1fXjVVPu9RJKWmC7vTPl6XOEO7PVx8SK46n8jwXLrJfz0G1jCGAAKOIHxkLMcM12Vi
wgtvJK4Zi/fkBFcAE0iPiUEk0dtvL3WTFP2lTXHtnlC7imMo+saYSxzABJgZlYlCyFg+2xFeSfqM
halqiflJgmuqQ7YHYBJTDqpQlUnAR141jVO1bkWRfLR19I1h12KC9tMZLRewr2oCjC2ZO58c+8rK
/6mwoIVTqFbRi+eqH80lOaYfAu9rOeuXi6Ap3UFY6C5wAt2imvKCt/mNjLCM1d5paEedUXuJgccg
DRY2YrgJTJkQaedL0O7X1deNmoQD3xr3XUVAOE4LmbPYIt74dHB4AKR04nji6DPiKpNsTzKsuanQ
9x8sW5jxIt8b2nid0fVc7vojiBiPM4FArLgHk0QFg5Z7vOdtdTVXSkj3GEH3igKzf7ir3Xr+xX6F
f54v2ZHBKPQgMUMouY53j2mdS8BIEntDn4QMuWL8ryMOtksb2irbQWwBQSeUAuJh8mMMotH5v4Zl
nEVbz8O7urgS4CswoEPjEwFMbrCuHZ72uytoztXTQMJFZB9kEuk46wnfuOYdzyE0sh1UnVfv7OHm
R2QPwA3vJzVGO3HWc1iE8tnyiOI9mSw13A1IT5oSRknrX2HER6b7efzHKtL0vEPbwyeHQhKD0nI3
dtPPnZHqktrxbvqwyR4A7293XVbdQZUgZp2+7uoIUoXQ22R8POiR7Gn/NNA8/6bTE+sH69WkHNV9
o47+YqQfTfBrsM8hHVReqiWCjaUrhQiisYGZAGY5oNzm7Dd7mtbMDYz8QUZTHsvmpRV0tgS/lfyt
pKR/MkO6c+MsDGdaVmAYdX6sFSclXf4BB+qinJRq1639W02XBX5m6rjcC62jjnOjQ+XXs7mV0uXq
RJQElU6B59wsQboZMTBp5KbpmhMxm86xrEY4+f5M9ZKM8LTlygSB0wjWc7Vj/QJZwi0pRayiFJ7J
rPI6KrKKTqrjbYMRtIvbfut32Ydhl6GwF4uuxEYfy+cpiM0cdkPDe7oy5iOhb7LuUQnVEPPLyba3
kq7RldTxF7+dw5+ZXiTFCJqvgC2SUggN2uX5MBfMqoFC5zToMJ/WIfe0/5j6JMspxPTg6VmwChKb
e+Ah3nOfmU7LBuZzrHz6qQoUXekIO/9GDvZ4mUVjK+l4QwBgwSZYQSHHylIUsEYib+pbXe0Mr8Jp
s4PDLb/4ZlxjW23mzxPofC9SRIOqfk+abhOt5Z6VbArJdvJ0q+A1lxHP6MAyGdWD4NEy3ihfTOFE
Tdn26Akgftv23pemr6CYz7sulbNP6wCqV+2MNmCgk1I5iVUbn9UTIAFzO3H4fJEeQdnNnEtCmmSU
3Vyd8d7c8z446oxKFXk43ufWWCUaq4cncfbAVVDaYFBj18n/tU2e8+3uPI8d3ZlmlPHaKiqHk00r
hfrhAIAIeqeQfcD0K3FBDUBGsTKyjEf5FZeYTLSGefLmJLY3hNUGyFOn2zYYfe4fpO37jot2WS3L
NZ73POu3z2hM1o0bFHR+YQf9rG0GVJaCxUoJXeV8tO72i3+MJDKRap9JgmVYf3vd+qi0TJpmBtSi
6WXx8dwypgWD77uuyP7zYCE5norIAmVG0bBnyhMb6aQiXybe+40/90XQl+TgZTTEM+mCG9bH+LLi
g5Eq6E2uqMsErsW/60S9coiXd6SmoA4bn/hN2J9++t6Hv3h/sBDJ9mWIZ08ID+JqHDx+nfKEUz4y
0ux10ykBrW/za3Et3Ax5Y77fE2GFWM4M9ej0/RXSBuSxE2V9iY5IuQMwete5GVZNcMZF1sc1IK84
8zIrz575Py1Up3Y2VLTXsnwuzoBN0vfJi5XcWXOlN96OrdBVilML2pDksujL+g2Hrt1n7lasjK/w
55XfsDCBwkloIZfle2BCS0/GmWkYSZ+iD2OzUUwZ8QdPZYE0AJFIpHCUZ67xqcCjdfu8uvcvILEj
VnyiiLCdYhR1rTkTUDRYgr2KBh5tR46EF2Hv/gAbxTDlkf6nWkC9oF5glr3tHaRoKeiS10x+QrZR
Jmm8gHR/CwExlqWD3PJjWpARQjKytDys43rT5npvfNuyPp6OXVsqiVlhyTCW6yndRypRvswKJx6B
WDoRqoIokdBxYR7QbyZZE4rqWXetizdINetkBe8XNf98n6EFz4PTjZ3Fk4CPG+AJBg8At6QfiIZf
XCu+fb11tzsyKC0qASFjCrXQnei5Z2YOODsqTrcBTR4q1aXwmUUV2ESB4ah+mjN/uRSNELadrqk5
19bSDwmboEMzQbpJBOMsPUOaJSTaYH98P0fZhM4xhVEuT1JZfT5U1UHoiJzma8XTVdamc2IsGuRB
4qb88sYm22eHaIiNLl1qfc+f7GSUAF3piOu5fMg24KYu7xoAbgfYlLOCQgErn5VfMQPhRM23yJOB
vkTWlMN6iFKp/3v3SGKMBc8YwZFRnmlDs/IKwvry3BimouG9R0l6320M2y0zY81YeuHAQkPW8Ent
lR7RDYTQvduNBZZmI/xAoYYc/dqLqK9UQle7wZCbmA6WLLww6FhOgtCqq7QvRcF+kaQzT+t+laPd
JIEFsoautq2wcwioPJtCONiGsxXYpkP849x+GgJINpDpM7VO8oAdaKBDb4CNn4e4dr/UkEHgjH+V
vmyxPbc/rA7C2X1PeHiNO5QRv89yJAkXfQbydTwUU7qz3hw0pXUBBEMHfcYNPVZeOgIq+hEgPjsq
eA/kc78Fg/8A01oLe+FngEVB18juLGBh7NCIBvNb0M6fNYacoeIdXwLEX2mNtY7A9CT277+oXwjV
sbGShPgzOX3MKrH88eJr2zk+80J/Sw7u2j6IWa8XCtX1NgwV6dmL4CQ7XqssZRIIEqJR1ycziIK/
lk+Yhln8crrmTsl2pojAjDC70dZnNG/qXP1jbsF0Si9ei8EoDYiW35gt6OBeZdr9cJJddFrLd82i
lexK/nQn5fAij41tquo0a+LKERKH4+Qx5MYv6egrWlViUGSL0nT5x849BI4GvLiR+KOLPI2MqS2b
cuJQ69QJEy+PBe9AmOWeS+OPbI9cD0B+wbg21xLAgsEJXw6md65DfEs7RwrKn9/tB0Yutxpe4B6A
ip/5pBhgWRDEcuocRE+Ef8EWjxoQ3H5wHxwAg/jpHhN2wSKKMa/S3YcY8nzCPxa9QLm5mOdZNxq2
XFhlYrwr9sW8oRonu/7vxFGTaX6SwPDdRJvoT++BTKk0mPZdl4nigIsAfOWdA9w4irY9mf2KzB8p
ad5BXuJsbKxpuurZVN4DaZh4bKQdBpkLU4cGK1L/rEA4YDZOxw491fWh27pyGxyg0qgzZ190xPWC
M10fitVXcjlZytuh2QycgZ4NrdPldzJPsy/sN9M7MCvMXf7bAIPX6U3k5w+rf+Ip7PuyalSZjhqq
iebUEJgidTpNKXljeBC0TR1F7JN4wOC3O5bPUSEvp8XOOlSuV/x9W21u4ALP2DjF0riuT84qSbSn
VxnI+AyzmjT4iAz/z/5evet2129ATIp5ejl79W8uaw2ZH/OhGTmqYzGbsxJ2FMfm5kd2jf5oFIiC
RfGo9lEei1Nhh7E1iWGcFuhdVV6uteHyiSo8HGf7aAyQlQa+2fUWQQBM0wBpNeFP+pzbjjz5n2ob
yzMbIjaEPP7GSJVOTiMj4uyjuKRYvtT8zlS4sSYgZZivz4jntLEMlxf56WqtK/Qy3BXSD+4s5Ye9
ypz76Rsx7AL4ey5JpN2bh09WVTs41pjBl3tduL+B5A7TqJi1kkBNYF1NAkpdHguqAe31GcNnf75H
exgDcxZ4s/bNnNQcaUVjQZcYIKOhdmX2598wlLYOqbRhL5qGNoTDg8+epZ3uB+kxMFW6AjPoXtzR
fTmM36nvBe1stBzSh/s5hRgouwrGmFxUlGro5VfMYzTNcd2FJE7tef+FF+X1xJ5lu3yDYxML050V
UYfTuhYrJmUqzPZ0J39gV4SniwwXOnXuu7aybAiCWJpwzB8hzgs3PmwF8ScIzKeuPc2SRv1Ic8Og
4WzEcUbTV0TTQvrM88t+zxFQHoaoNE9Wm3n7iu3DnJhhxwwQQRL+u2xLl1jXJxP4828Cl1paHDzX
bvnXsgiqpJH35rm2nTPi+iIO6ghD0sCCwyrODmU7TilXO/XATHIjSjhtxjd/vV/AsBhhknKdoA5I
OiRW2gKXRfl8Bc5kO0RGy7n9aaNxdH9ijan+XN0jySQzDSFHs4s2lgY3HBLKoLeGj0ApSDdx/cP3
ZUuFlvZOpbNX2Fv2oL6FsH9wcpXMLxU+uSeQx7gxKbL2u39ZMz/ISUu/BGnTaH5N8MnSQ5t2WPx9
C62GVlbADK6GrLnZZ53dBLPhr6NxbBZ+naEKLhM2yI+bolkYyvKC8kx1zMpAoaEAatplidsWqzM9
BeEsay2HAWXDXcmGJr8vMbpGL6vH/bPERcF2+k/NoqbJZAyqhqvnNauztKP2MhhDmHlCjokKXv3X
WNcwJ5CoyUZ7sSB5XF14UVGh0XlyJX71VrkTo3Urq7aKmGlxtiMj9bABngwVkLCCscfPe+Dqow5i
1bHeHddeEIMyo3pw/ZJ7952c/IW5UTOwsseo/hO/66RllHN2V9nMHWo5aH3ErNCYvzPoQL6phyKd
NuYMQYyJdVIa4xaw8Q5rdrLZXkr/IakdwCi3650bjVELqlFcVZfHIdwMu50m0seIdVYA5KYaZpYf
S8clMlAIkY9n64suMI2x1Bw53mA7seTweZDXDR18TpQlhShl9dbxOVROSPx94LrS9x5i4hDnyCK4
odbwH3Bpo7OxU8Uqlt4KE8Msp6Jeg+MUSZROQ4t2IvZR/O/s0LFCZ52+VaSmbBlT7kLGzd/rMFTU
SWN5Ieyz61J1e2SP3trHUGu9iD21UIetenH3GWlmKtnMEGjLI+kkEHFbHz4G+/WxSa6CtXBxZhc3
2CgfCqBGKja1AzseV+UhqWotdSyzm6O2az2wkzUFAeoqjh4rKtHYyRu+RjwF3a+aYyo3ng9JTfUq
/7f8O1Hg6VaoXBB9khiEIOocIN/MYxHl8MjT8onS3DYmw8Jf2wkDBmnbsGP0F/VVud/CpqqPFtt2
mnPNG8dy0/8GnB7iLSGQz8VxO0eNOABF1SsBMK0U0MQZQDow+nfaLL/hWI0z8M/inhkVZnh0bt/L
4Kaue8nZ17L6WXel3ELESv02Irmyp0jNDyFTaQPO0KW4TObOJhpkMU+shesXjDJnhogrjXsHqonF
mtrCiAAlobtfnDht8a0VTwlrUFUToKncxrkUmVEFrXvUT1aMDnY5fsXFp8uhl/td0pE1eZEekZeJ
YWvtPX4CLKr54f5LCGgBkFiArqiZ+gwifGPG5UpxTCVec5tM1wCQeGSbQ9aBQSJJl5REAGC97qVo
Sl9sSH8hHSUoh98de+3TnIMc3mixZqVsmNQnD5Rm7AtJxIc41UkLMTxVMd/a40yu7/Wvs1k3/U65
w0xXIGzwFR2SQaImEy9/YRN3JzrAfaUO2MKnU5BCF5hapIZlbaDBFyR+8+NNtdiHU0OA+Kwja36q
3jH0c/poK+62IKZ/8hvV/kBDjcgBw6ObiG30k2x4PNX1bF7aUXNtM6KmSH24FeOfDnThrGC3nTwS
bvHyLO9BdaKIdZtqUVCyJpiyPS6dppzz6XZPAwisBSRJVTlP6kgSwCZmql8KUAl7h3wVYqUnOaA+
5An5YVDvXC4CR2CxYoCgqh/IM3y+ICpC5feAcAfmJIe2QvMPMkyEfU5sXBt1ZS2OTUNeZouC16uW
aIrBVFONbtWQIzxcTIQF65wzDDfyODhDO/3y9SsNYqEm1z29CfZROYHBwQGTpkgNLhpEcELQSbWq
rCTtAhn5LAG2vsqGschmNEbfkV6I9uRoFoWz9HokYcXGxT3ezIV6kZg11qIruR7BbSjkng8I2A6R
zYgKEhn6jP1x4YQbBeIwft/cqA9t2SrXlsqrjJYnV+OxffYk+fnnCxQKR1/HEn2iJiJReQls/0VH
Ay+dYSwWIQRDg9Pf0lPLtCqMJOzesyHwWa3gk+AuCP8EBIY2UUNP16TFxeVLhz+m7DssgsgCiq/K
QW3lmxOnCZRFE1zirGcVUUvzWbHzjpUuuX8aK+txi3uue7qW6MvzjZYBgVatSECEGhu669QRPQua
0LtxW8L2W/Fx/E/fb2DWNV64126N6blMxoFxg/CUIjFFVeZR/PUJr0Y0IA1P9QYsvFvAo/nVW+TN
IPceyKUYMoC2JNH3i1El/b5WIDIP+xNUD2Loc4w92INp3DixkVziSKminmH7AFJMJSC5bm2qfQXS
ZCPPwz6kEFEu136zgKezW0/RZWnqJniNPU0hlru6IGSEG3l0AlBqmybK4cu/CUOTne2qPWaDOQkN
V5USHX15ceVD6bI6Fgc0uk0/+VIlGLe4aL9HLN+otW956bVzUrFYmpaiBKYoTHwsAq6KbtZV27D8
79+VTysujAMU7r3BcaIQWSJhfr5ZCQpgfoN+MFQFffIRD03Gs0QDBRGkq9vZVo9+WZJnoRWtobXO
fGseYC8IpCzJlm7Z5C5N/os7d42VQKUH6QNeao+ce8bkVPhzDum5IqJcuQpxEzeSmB//AqEUWRu7
W3DOk0xNHVQCKui+Q69ZTPBmzjcmEhLH88bVbnPtg6i82T5wNo0yZOXB2pec29GFYafLzGzpfjY3
BW7BkrdDemQLeZbopUw+nDfDtEaphyP7K3s7z7Rn31LJLA5i8JG1wNLuaqZhVSLsB6YTruqyxFYK
Vzg+tOJEBHoUD0kHHCJqKXu1Rj9dREePDU39TJmVk9XzsKBR/skOQxGI1+q/IcLqhMAD3fVWCh4k
p2CgTExlNFylnYcLKL1J+Dxex8Gd26JZ9/0a5JA4UZKaq3ZsasiQw4e2TPoGR8h36ZYM3Vw5GLxn
9Lx0f2DJH3l5kMIipOYrLTeh3WmsUzlcHDt6grDyd9aM+LnaNSUJEBEGvwtjWNhYVa5um2BLdDKN
FjV7oHknzG3Gn9DwTud84I2MYjCX8wjGTgSSVYJvnQYfKLxrL0pmiSEvvf/+QUG2KwG/RV6WJyfu
+/btpqJPaYiCD3fuFTdAhXhdb3uXa2Gom26pphvklBcFwyEyFlyNlMY5tu2dkZDOVPOZ8TbDx1pE
2k8EnR9t9if2dMTNXpNmYsUwy3tPCBxEzKvTXRmWSLCg9qPgiLPE0AFBjg1MT9KKt9zRZCYCd+mL
NAZDYENyxstSUFGIBGw+GY4tznTPgLGCwClhHESGsRDQcR5kVpbV3zeBj+WTR3bnDHajohJQJ1k1
F/jYESprCUe+9e91APvxbDgM1mvi3uxnsZ7qRSt3ZcmavC71UpIjBNjdUkpvagNq36uk1D6/PWJm
UrFUxKaCeE9pZCrWBmH2FHrIHIzcl3AJwHcsLfCzQhqXQX/wRDlYdtYjmEHMifknIFpV5hG4wwWT
1t4Woz4lOU5t8qwKTZjkCRomQykp02aJaS24lt/IgyDgpknfZLUsZlmaaIZDrmiKQUBLPLF2+xa4
hhi8lqyToOB+8fDTV/1b1Vm+qa7bIdjzAEwsBBx23vfLFsTo5ZoU9NLdnNb17idCU0I9/HawPMHx
G+vf1n+7ZmtHtatpZLpDB9znu7FZVK6496xzHPGXCgkum/C32cbdL5ncYGa4BXTqQu9osgunm6vh
ILKuChLCObdtO2gyjL/7RrvZjlLrDWGHBlYSHdJehfKIri7Rb4d5TB6bqGvdDNGPFQ3U909u7L+l
EcRsicT9FUEM1RIn9ZqfAVNVazhRrAgqlU632Z2TwcO4evN+Jl+h9dKvTPJ9kXbWIy3cToDEwrNb
9V4GzFtJfZZWb4yYBTyBgI795H8yHUXAKGgr8uSeDnOE6cNZ78HquzgAEMYXiIPlsvUutKYxLF7H
td5JPIkGg8SJlhxfZuRx3rDpDq/D03yiEW8BZFIML3F1TJB45oEKvqJWA8GjcpXJpCCzgTkT3OdH
EjsfdxYOv1iQsgsGv8QzvKmimpE8NAWS8Nyq1ZbMwO51BcyIpXxOIIOp/h3DPdcrjjCZAkq5jtOf
vpKyBDA9fHtZN815VVdczMyFbgJ/TaAD+UH4YUStmgESTfIiQlQ8uCBpckL6ar5XBlkgIOMcM44R
8HJ+muttPIlhfHFG191fZC3433kf3+iC0leUeshLgPS3mDR1fJRzmZQJ+JhqsoOl/Flip3kvldJN
zRtwNmPvIsLdcbHjc6KKn5iKGWcXg0VkG1AwX2z0K2iIhfyOZF3N7Tz2RSEopbmp9s/O+yp0YAaZ
65u6cXUtazRXh2Vaqgk98GjnxVOpWY61PuUV691SZtJIXo8pMLkyNT85GbKR3128W5tb9ymf8qar
P+ryD2LGNsRgp3vOQ7fLU6s6H2Ozt5kTQ78okvgVrdVzmbMq3qh2Y/q4WNxYm4FHKGa709ASE5de
4OdnQ0jrr/PE/MmV7iuK24WnP/AHbnqMDQ98hNrhktaOaupcTALp+3NyppNTtY+wsW7h9yE09/Oy
VTWf1T9VIHTX/u8FzvpeDXJEVO67Z/pXmm3T/18jpvUvqWVuii+zW2kUhDY0LQUTj/oHz3+e6zC5
LTSxpWmEmmyluZsXSorieYJcEygrcnO3GU5vu8naLCEh6pqmryLbqoTc/5iUIFlkeYz5xmynaG70
pnmffSdmxGa4L9ZcMBywr5MohC5LNSsYsCvJ+RIgy+O1F0ZYwahI72yt8WpCcSU1PIRP0gi9b7qf
2qamurGxzsv4h4vsH53qVHGxSJmDx1s/9RAHIV9SF5cmcHU/TkLDAXo1Czgedeutd37ejWmj1G8g
JcX+ROv6r1kYXOi638VPpdvZL5J2NUp2x4K8ESHILO+XkB4WfgJCnJeETV8BkceHyPphcm8oJzls
rddY9yypQm4MNV08Ras/Qwm8X2/JVMah/5a3m5GjYjfd47rccw0z5CMKaGiSSDymuYSSm8EbaSUC
HDCjSrrgiHEdrVMfEQP2q4vgs0+y2zIcfahxdogBoHqWsf+KzxG+l5tQcKHRvKAsBKUhbM0KgMOS
VvAu+hIigiaChrPMPiVnl8wiXtfLj8Q6y+gqmLI6PsbO6ylKyGW7OznGpPAuL0VG2XZHQ7skLnMP
/uvRzNrZ+6YDOW7clGYIYoYhAHlXeC62VbtCInfM+mlqOEyuZf3s7S9iC0951gQnsTKiokDoFXsq
aK58gy1uIJeJHXVf7tau1KTAKssSTr7HLj1EBi1XL27w2aVVxv/gFNM08qvT7USZOnZ0HBD4j16C
HbxSHZpUNuU0qra2WkNtb1phF7puVJgUKkiicm8Z+BNWHSnibyMmf9pieql4ZGrPqZjJn0SCCw/z
MScAioiqhj54bbEcwcDuQnTCvR4Y8dg6T9Em4v+pXlvLX52Z+MTv84AAczRPJ4EPeOOJXdvpgftU
mNQZhOhPNA8KU4BWvayeWcFu64Z9094xknAFY7yQ054CQ3mF/jBPs/ROSSCzFBXHBcSdFIH2Ac7W
izTfhmi1oaUzU5gsi6xEqzPUmcJwlZqlxWCGiubdkhNJ4sL0ejS8aMFjBGsuLWTKdYY4EJu5I0rz
Osu2CwFF38gfQ281QF7Pe6H3iJ/s7TuV7fcYJcMR91nfv/SacJBNGOdvmMcRGAUSFi+O9AIqE7b8
V/1NrPzbjAPprgB1y2RmfYLaenEVyU4nOPKCxUd21jSJnnz6cUMHwDkhxe+UY3yzog4OqLMqS69C
0giK3syCNoVZ5ITdDtLQh+Z9IQcJavmboYvY5LxEE0n/v9K7dEYCRlzLfkX1IqJ5xI9tFXjTOWZF
fVoutihaynQ2fICPHLFkYq+mOVjShDp/NRyzso+HrbtOYSnifiGlCx3xIg9jGnNGr10mJ3xDhm3Z
HZXwbedQFVmM+1JzLSw0bc9mqeMQH7PfjK2AwEk11d2i4HnT7q8tcJv7z7Eq3zgGcz0nORUx5CZk
T44u0PwROEtu358utfsGiuqYNin2kLaLofhmYia4LPw3cn+IMYrMOrYKT9f5CYJwaOclkERu+Xi7
/d7ciYtsHERZ0CBI469DJgJ6AdRjh4IUKQqAwoVW/zH4MrJECI+XQq0w9iP+8ISye1T55lbYLgQ4
Wf//jlgkky0E15iSXuYxz/fKLhCTmLZ6KziogRmPksDHUhsStSFOf8PVvZQRGP9+W1BhW2G9yuRY
aYt9J/fD8cD7BwWdLy21M2QEShB8FoDE8FhYYXyotaFLl3+wNodoRjiNfP38JAqRC1GR0mUV73AQ
46pHERZKVx6+NC8+RIaipMPNepuhqJoGvlITtSui2pR14PPii+pYQ4SbIVw1IvBgLmYKli7NaYXV
uJiH8tGGkMtnoULM1KeoFnRxiBEnfM7wG+hCJNInnpx869zIU/wAtk383WccXZ2tNU1F7nSmYDVb
u3YcBgEF4xaPwmZZc6o+qwGOWvUvfpA1ukgHHbC8tsw3QTSO6MgYga2oXofHZIgjimUniSwAAXzn
xt7wXqgV+2tt759LyoxvLMaGSYpZ7G5E3rPCUEbVHqgZZvAtjKz5Had8yIARaDhliAeKd/7a+JJB
tXcMAYMa3YQfpJSb8gxokGKukaNR9DvUlQG8nSAZxTNLQEnaX1I7bgM/gWc4lzJdArE4OlwTkkU5
dwS6qtvNiA7NYEYvT8nzxXjMOyEBXV95KRubx5W4KeR2srReACGZ8zRW+x79encL1q5DMQGO5Aj+
tIABma71J8mwJQNX3dHENNC4HgSLrLygbmciDcBkGPU5Y1eh0BusqxqopaqYmgK0DYjNmcLh6MlR
AkF+gdXnRYm76c70cwn7PSwe+DHety34YjN0kZZsZn8809No3a1CytyJaQ/eR1TUGBdR4cWw/Zru
z5HdeAHb5eTLOcy0I77gnfBCVVsOxmEIRvXmF2KTwYTSag1EaMeIGJQUykHc5cmAvC5/kkDacAjr
ESzpmt7oaxM1TCwBK8fF40/5daXj1SxE2id4p0IilLuI2QCWNiJMeO99QNd2a1P/1IASxKy4foVa
EwaUQyVn3BXs5pMVgQLQNdlrbn/br78+/eXGL3vySciKaauLrq4syGmqMq2GHgLIJJ1hRkAtKEuS
h8/hRlnENcxqcDFUMZo463n1EanB7vo88OhZ4O2/Bc7L+vX1sQWIhaxEdVz7s8KzC8c+u02lbXUW
alrdMdudVWbdvnNU9lg7ddWCHvUFKBLT27QH0qW01mcINekycl+e6P4L4P6bWqB2EszfqVR6NAtX
uqGQRsREhlfoU/N9pTZEvJdnPnolM2NmfOP/VQcwZD0OO6jPMgLXhcWKk5Z3r/fE17fEmBfhQv91
dHJDMVJKOlMmTsFgUOccofqYa5P6Ml0GJtkXHmBx5rk4a/G/tuEi7MZTOOFgV3o7T8UjQYgilN3K
FrucbGOUxvjRCWLxd+qSLqFJoF9uhg0KHMvUNndjJOD43NfGrA1doGDl/ODgmLUwMIvEExkOD8HF
bQMveDRY5GjMyZoEywDMsVrL7ZJNG1j1ub2HBGJZljTNJvXP3o9cMR6fgxLxl4Wck11Cl/06Rbs4
FDuzrxgPMcYgB+T0tV75wnbqRAKBFANa0OMCtJKZXQybiohpXT1TIsxkSPTLvntDCrAR/K2/md7n
Vl/oe8SuBJHQ7GQ0zozVjcOxeYIfMpJviezkGlUxDVsBlQjy94aoM9AVgYCL3YjRCnx2ypNbBEdM
D7ESExeYJ1otUK9g4CjYSeoBDc3Fi1vBmw5azek7GyJoIDmp7gx2dx2dnTzx1Za1/X/I3aN6mDPz
L+vKKFBHh9YWHrM2gHNfxJz++PqaK0Rkt7x/9zkQSAlszNp9BWt2oerYSKRDY94jpWvXR435wrp8
tjJQ+yEPo9+0b0L977oWV+vwc0MEqO4JRW2kh5fKUivt18yN1rZe0deO3WE1XmIuYPTVWpVMrDPS
D895ktPoDdKIiui37C130vZ+8kb28iN04onuTFb4EOFo4XAMnuXzjG5INEjWvD7WH8GjWGklx8bd
mfhfGtbgCSReKBKDUPe6HkUEu1WGdBabYZU8sZeuT1QFqJFtJlZS7/N++jT2W1gLE1HoRv1mFssR
uNIctk2CkTp3txak0x+JVTqnW5VOLP8YykEV3B4SQNHyxw83ngELRDgGiYsO7VFxYo3+PeOLW5JU
+e5QOVO67TvS2os50qiloolYnIpQ83C2SMEmKlq/yBjwg6y4cW/vjhhz14TrqMy+kjuEHWneI2bu
J9MLLWpujdyjIDB5gWRobhr613amq0JmbdJARMz36pUOE9hs0wi1jrWupVZrWCb91Ydvc+E503S3
oQenVM3YgswYN768au/5zQLfrftsFS6FIqJn0/JeOZ8gzlKTZOXsRvUfXMQsuEkMt64cSbvPV3GA
B1AdMYIX37GUNUhCAVctGU9vzd6k+VbBx6kwo8aiuu7WQkFxJ2GhPu4SPTiTWajgPEq/MK3+MUY/
TTFG+n+lNo71exrPaJv/d0sAtB2FGEm3J3DI1moGG54qWveA0jTidWi+DYT2SxOTtMmt+WCV0k4s
eDgo/ha4HZeZuS6Hb17GUyDsmgblNQr27eeVTHFNB0MJy6Hx4phOOoHG/AdqxHPvGmkbFYR0+jcm
4cfBZtMkXq6ZytBXOXZHe7HLVHvWcb/A83zHV8mkG/0BN+qCo9qQumwTVJin60YmmjV9UXgQAGc/
CSTEgKhsF0gqT1rfAlo0wDt1x1dLI2/rbFJYcrxnFJoDDM1LTKYw7NeZFIc4c8eP6dBhwBh44wai
HQXWR1TQSwJFLTxhmgO4cLikUZVkzToZxsknvu2OftRLh60hHaiWGTvA3IhyqZa5mKVP3zbOTilp
/j4jkb20sBV+MxVfVQI9ENkRlvs4zUso8e4D7GzcChIOaH35uMb6H2EhgagAA0JSE0VR3dm3bCcF
zJKOPATnHyBtrPN646WfYkrwOD377P1IVnb9RaISttTurYBXTYt2gHXMw0973dlPLajEjueR3bPN
XZ0gStodVmy8aFhBymIlEfDKzFqM1FoF+/lV7vlHGQrTY7X64Ann/HtNh5eU7yMOTCIj13EqXN26
AAAjd1lTWeSa8Kb2lNsJRTwHbNsTiRPlrPfbz6LB6xj0YyOWovsET3jjqkJz0g9b+JAZ3c9IqAyW
k5nNJSDY/Sqyt3DFjD3WQQ1h0eQJ1llUz3t8XBVoKK4M699Ge9cgoNd4o7yVcas2HDXJIzibKakF
JI849PryZweAMgwiF13Z+pdwgVkUdQHUsW72exaXZLSbsUyu3MeUQWengk7uAyWzzZHKWFPXPNsR
ktXPoFDUYoD6BBvEYR2JFluseSoqpnkL0JYkYJYlPXJvNKmixj1XxLhIb2kylOExDrmmsVofuDts
JJLBEH83gM3hmXJJP8dJwekOQU3J7ME/JI9e2uNt0S3C1hhV7wvbq+1sRED75bCXMuAvTzSN1yDW
6mAjZeoXWm3/CuNSXzwHHk5cctqPib/oTPJxA8Vv9L7tcURX0UWHV9r3g7I6ylxiNpQt7oeRgrgZ
ti0ZJUZFEKCEMGm7BToVVRLbs8HgUnVe5cAS9CED8MN5Aa7VRm/t739+apgEkrJU26NpTQ9t8zXG
I4ZjRjqVCkeLrYM+jj9ao9kKWAaIviLSlHILcRevgxRC0c/AXgydw3uUzmX0PFFGViQtNZXGRmmy
avksRCfeM6M6qi0TCnoW+knNDaCop4WGTRovOFB5M5VcIdJJBLWRQlSwQddhsrIv9Yx1EsRnrSku
KYAlpTVPjo6ZbXulDs0SCzB3j6/5yYFka6C9Ce3eHtqazUxDc0YLAiPVzCQehbHhl8gkTXx2r9p/
rS3h0witdpKFMp5gV3eBScopSSjuGTdWF1R9SgI/OMyGVUS77t81P+7NupmJCehRqxbe7BE0RxLG
pOBdFoI0FQZ6F6I5S2IoF0ob979BihTvG0XI4nUKWqmLDrfqLMT8amM3D1s4ExMhlCv16BYN0zKM
/Ku9//bOKvEROxt8v4A2NdCkGbJTGEJYsiQFGea/vA5IUREDeXUzItfz0ETQvJ30NtmSmljtXL7E
GbArC4rhcpf77fYDdfSl31jjUuqayAxQoTxaUB+5U3jeI1BM4zO2e6mOFYrSCfdwdqsWBCSRe96B
ji+FknFNfHAz5v0R5DOKhBZuai5tPLFPGYBSFvfvCkwhft1MtORSbPi5kRj9VDSbRcOpBZdkvyDQ
WyPL8KJxE3m5Nz4tyfJwcjd6VVynFVZohCyJfxdekaAoGRplrsPXObEJ8fBD/V3T1KEpO9Q//xrE
+X0/GiWdqtZsZFE8nY2COgMdDYQcdLP+enyvgeqLEoueTNdtJtpD8SnX11zyGAzmOR6lk8iESKqC
B9zw4C6b/BzoiG4NOjmScp61bEM6sf1oh6R5eL6VsJmwH912VhOpSQe7Z29nrJ3kHnnE7Nj+L5hu
LJPU0VulkhpBd0ZM6ZjDa+clNpulacLCUMWfcqHjLVgvuHtKoUw8f6hYXiog8we+XdcftSNitA5f
dH0m0FA98nXBZfVbSkK3AsyGI1I2tYxSTtHw5wtH0ygVanvHKp7DHumS0lbZCoiuiP1OpVbiZotn
yk4uPgVH4Q7cIonTZvdaO3YnXHiw5LqIwJ/pNLcsTMsEh0+piWQCxMTVqjxAD9jvNSqYdIiSXo/L
i0sRBVJ8k8TEWfOh02/BVUNyQMfdQFzVoHah7gdgZ7Q3W763GK9JYPR1vuBWmV2Ejg2rAE8CAp6a
sf+TqvLVVglpnHJ9gyRtm0S42rKkJG5ah3jrlzFbUzt6A4e7Ns1y5ShJW/5LdBigpfhWm8X6JP4d
lkTykaDbi/M8Z9Q59lOe2W5xkdvy4XSExTohUJcKrxavW0+0D7FEZ5klB3352jecnbzSuiKAbNDg
7A/ix1JcuAV30J53PfXi3e0BKp2AS1CydGiudC0lAHU7iCnvz/S9Maz00HEoOZbGzoimjAVGLT86
zOR0R/CMD708gnu9C9KoRyhbJp0G39zQMLhtN2tbKedqxe7XzxXjy1UNW8YkuT3x910D1q/CLb9Z
N6NPCG/I/FrZCmosNbwKzNu05g+Knd2IRRsrpTSgiAn+YAFpze+SrOs9UhZwbq1F6IQiV1M9RWFH
rOsheaPhZoQczJiAuii7qjesr3okYp/UwHWY95UTcLuwc4CdIyKLnawffuM3kjxJBPy8HtnoVdjm
eO5aMWIPQ/3/1uaEDeAwz0qA97ABJOem+tV7LAdPR/F02e8cTNeCZYlrGEE6s6zfFO1LvtCZ/BVe
JhGrL51yQb5Pkp/sM23Y6wu4y49hHs/oVA+hLrrODtsmfEXGDjN7Mu2ydVHX3Y0aiN0gVml/Xnrq
Lfhzr2Hx101Do+CE13ZH/HZ9HdEFdjN4tbPt64huA0cmOSuSc9F5t8lZog7jNtsTgYeCY2KuyoyM
zmbfSwP7OifGyzAKPhtHcSeNgVLZFP6RHNYNyt4ee8uYWpHFREkqDIsu8ecsnKH21DFlPavNJhRT
aQjJ9yxTxMPNIIpjcqAHAPLpX+SCPGnNRyTEJ+aocPc3EEu2WadNzhJOjytS4I3Nuw4CbpgZxhst
B8NNKNeV5WctGS0P3UHG/xbvwEmDOnq1do/6c4vYzYaESx20t6EA5jicETxEUQQ4GNc7ye0ap4Ud
mqddiU5F5HJbTiXeRE+jP2wmil9QyWM0hmm7wpXVXIb+p3yfSsbC95XcJ51pRoTVop8eJ0rBQXF5
YXdFNf7WbAG8hynGn8nkCScSAnxV0pX9Hf7wp6TeIRHXD1yyu2wH5Wb67bjmEnEZe46D2XD6ICY6
XNJ06HEgdfwFHFJtRGxZIIEqVbJQvjPi6k0vFSGRclPj0oJcQ+jjZihVlYdvE9sZfXEiMyo+tOqW
W6LTmJO0WVTMCn7ag3rU5i1rvlh6pWBs7lq4HFSObmu3xB1NlEndAm8oWh0eDdgVTdVaiMdSRObA
779oKsf4S7jlDbI+T1jHvoXHNEN1AeW0zMzFA/rgJk8LzfaCEPaZVK5lLmP38QMwmew7juBa3PBa
QI25LCr6GLjInH+XWovkYzgHcliL9K7w6gEmPQT6kn0rmUn9e7URC4mHjsKPEJ4iogBDbXiH5BoH
qrel/pgCLT/RZLZ1s8w69F2VX2ah1pYEoarm3qvnBD+A3bkwCWJQip/IeuTbd16wuPHL+5azV7gn
6bPToUs+bF4GO54e7aFj1LvEvMc69J5m+9gRy3AHC9bN6th1aPFLlnjsPwWOxSKFBff9muCJGsKK
LUKgs9hmPpidZhi0B5fL4ajK19m0hAe/MBrniZN13PKop4CaGrFp3JuwVO7iAOVbG8rqO3KHgwNE
zCUC0fWiyL1hgeZoJCLGm7OGmrqPcnVgx0mJkWSGRuUBJvzyHJXtdGR1X+7KqTvPhh+uU0+e2drZ
Wv+A+AFnxEgNQT+ZQD/xUj916k6bWpXQOWltuXo7G0EWYIYTXi5LakUAkfGvrRyUKfYPTSlaYr6A
1+iAtwdLuYY2qC32tsXx8iRvL3iMPttGP3xue8SDqD8zdo0qoZJkfWAfNQTHY/Dc6P6YYVvat3ZI
qHtjH8shhm5vT3XrDUmXY2ZA3DNUzhwfC81iu1K8JDFknkpX33Mx6WodQT8j6pLGBwNrpmJ+6X3I
S1+orImtefq13raBYe1QOKgKW/sjehgXtTP60sr/OKDRAeod64lyob4KKxyJ5ObDO/pHPgoxAaYm
S7kduzHdtzOcyq07DyMGsdk6LY8sLXC/CNOl0QnhQjfTSovi5eJX93CvPJN9yBQyj46sHn0U47qC
HU5GPs9WTMvg8fpL0uow2aWEgj9ku4pXU/lz5INSzMtCnaj6gEPSvlgMmRiE4qtSBVGLm6R7BSbA
gaLuXyEvRe8NBiY6vR6j1oxpTFFKsx1uU4tv9MHVoannMK0eakW/GHjYgX13e7Os+d5TMaMvA/Dz
ufKDKTp/fyHi893FBsUc1dfVE11Qb/pnm4j9G7ZtMaj2LBt73OxBsiWttpxITOeSKSH++iKY5BO0
7+3qdJwoQMqfT1+4Wd8lksJKLTPO6N+oLdJmqSUVgDhnLy4dZwLQ/mnZoeNsJKPC8z71DP423DDF
HBW2xFZFudIdVGMBcvIjBM/t3NXQQPmjNvZdEfI+u87BVnRmK7dEOeGnY7iACisFSZ1vPEYAHEvi
D4rrPjHz0gyJuD04fiNcFe0wbEWToGLIk8CQ/COgOGKxOaXowTLh+UakEZhruifoPCsvg7IHS6/Z
iiDHtPOMJ6H/k1INjUmVJlmfcQfe7EoU2kYPYMnJ+j7r59nkdUNk+PzmK8WNnfpqsnQICNtey437
LNAFYBhzTcTsolGC7LplqMBQ8TUzbTzqziHL5orZsQkjhBGl355BxvsMKL2CujMuRf0nOIEGAiNh
jwl1VLnlKhMkbzTis0fcKhfKGAo27nEewXAEmS91PoUy4XT8w7OtnePWoGxOc1r8x2hU3CqKyjSF
KcKcGE1LYj6lDhGnlOOPFWhDRFYcohqcKR+ufL9ecLi/ygHgYmCrQLTTKKLhxPbdnga2lCxkFO4l
j1dHWB7rPgikDqQzLhqXqxM0SHRGR0x/75w1xKg6vlOqSx3+S+XaQ0ujj8o4xi4tzD6+aSS8CXLL
bUE2qiihk9IXc25WPnnrqbu1cKv93OfrpRNs8VVKtrgdBCeOH1TpfJeo7984EF5LoRBJJUT5MhTG
aEdX0EQ+0uUiOY3CZGfTAIeRPFWdAlg8tX9ZoU2M7aat5gk6M/qENSrNfjsb5bQ9bPM5NvV6BGo+
S/TjIwleyK7scx4wsOof3vk8ZloPcsGBXwlzkNhByDJj5mtHsnkXVXUUKJJoOCfmxCE8TDddTiwf
SLwp5el/b7QLrz7wsnumDnA3Be0UgaRJjsmnx7Bvo5LKpQgHmJirDNNgi9C74e6QbUNCl815/jbU
yxD3K0DX3OMlOd/EbR6zW+vLDrnow5PNaXKsbwaalnrNPxi67YwIsQke3G4YiIkA8rq2uq1JKC5V
JYHXRV7JXGjPzIht5CYFI6kEzH86dE1rl9G2N5uXdRXJ/mm5XymVsm0AvDu16A3wfIULBqnI5SFP
6bKVOMao6gbLvthP/oIyQSg3urPTJZ+X+5TxKIu3p2jr8TZ902ugPlULS02Uje+0JaQKlyE7IVFN
FAQn2pIyAvePqtbJAFrlHVWqh2C4J7XdcFFgAiNtd9hupV5tNIumseUr+1YZFakZLpSGQJE9fKZX
Ywm1GDEt0rXefh30PGUt0bF6lJeR3Ej514yp0GRK+lXXLY6EuIDU6jg65265UyzRmzZuCBXp9vLP
YB9NgTEBOU7aHVdw0SkUecPC0KJhwJbidTxMedxvBIGeeghVP7h/esN7iZVprnr4IAhR+A6s94ov
zNeLNqy6ugeWAIdbk3ABo589T7WAJ9YmkD/S/GtNCl3tmvj/VvZJjR9RtEaxfmfO6nFe6j+2dtye
jYVc+kLp1UXGmaD/W8h8D7E7XtOCSNmX580+HJQ7nGc1KLahebp2xQm4c0ciyHuxS9N5d5zGjZZ7
7yMM5e8XTR6sN5BLI61nxubIVrEU0E8gXVjOksSksOiYy4k8CFGVs/uUUQ9PJbH9bDqIq0ReTDLs
Y9e09eRjGWxKuouumfyfmFzhLF5sk7voGV/m/qXymueqa4erRf90FE/hY3V55Yzg9clsqZAsefbX
Ni+B3mwfWOtqlUVflPCgrI37yMHPFcS8aU8yburAgD3y4zpU01/+z6z6arD/po5ZDqixWFhC3qcj
1FBhlkeflYqaAinemLpRx5d5SZEwnO+1vl2f2KHqeuQhXIzvvE/rwvNi4uJZU2lYev/vgCLaME+0
E0Wm6Utk+X7M1d0tNgJDQTiXcotjrPM9pGxsjKJ228ty7CAnT1Ofb2TEGLI93RkpUyJAZ56rr3Ue
enOcBxME5R+T5+ssBuB5XOXPhAt+IVpUW1rAtk9MdN7CBgxWtAy/xazpzX8njKN0CUOoTjbKnwpK
TJ13GdNx3T94xBFLjZlC1uWHbKeHmY5pbI9gMoSJQh8rhK3yICA6ZVaidHxTmwID2M0sr400SHpV
QSHrKGc+/omuH/HLkdpiB7Mryog/gm4U5nMYA7PKphC9yZ8Uf8hS8iw7ftSKmcdjFWwuzVrBy49G
b9ewmLi2c3Bv6pLOCma3nxpQOm4hapaSu3zWEnN24ela4IjS9WuiCJRMypDh0TCaUwotVucfMy05
syMPTbKkVikUkxXAmillsyUog9GpTdBlC9Ho1Bh/z83D7F/LnqftII8WKPH7iGUYxVakvWV3t19g
3rLVe6nQgsSw4ao3V31MnQuy3VoccNMu+kHGk0UZ7NmN2WQjmQi+PEzzXMXHw0Oh+sNdL9AKWtPP
NT0bfBljiNrPTDpIfdrrZnGyabnvh4lTomgJvIpv29Q4Uk4zim/Kon7nuYRjZiDpfQ1JRYTB5XM7
1xp3pJC56G5YRFnJYcI1Gqbofeq+CfpxRYXl31TgtITJHWnmNqGigf9eTebYhxJvBJZAowod5TOl
BBem+ZINi91bnlHvkAimq3mIJcANX8s/963iKrpDtRNGROhH+o3mMXGS4rTnuu/0WVGwogh9rr9l
AHjpr40TTjGsxLOyhsBXpIcrqa+AT0LVDHD8zlvzxn9gY0Lj+nXKNvoXO4AWZDJoOHz0aWqIvehH
rFKBY/N3x1X61lC0Cd+SULkqMgWmBiqGPrG0V0jj7qNOEPY3A7GYBotgWtrGLVFqxTfJbQV6zTwd
WSBe1rVSQ55E5Vh8kHGEiZVTSCrRyeorILM4bEplo+Y+ik4w5fWr6craTcySMWue5NNNFfqlO6zU
6JiAZXcwpTfyb75KiB+2ZzMpO3z/Nv5LShlItRXMm07PBgypA+zYiHQuuA9b7uAu5SsfIKib4vF+
pBYa9RvjQLIjTLkZv6NEKH8HD4DbrquUqtMQQ/goHm2ceFah0dffM+cYdUerUBha+DNnTfYKbHko
V2KSwCnRM1GxWPCS/4PU5J+oc+175NydrhwxiF9EKfPXcw1mJnlgoMWs8qAtatCjJII31cVmHlKQ
PIdsG24JYAJW47N3TFfibsKtDdvurmt66oa+c7tArIlei8nG19wOAdpej2DEZros8I5lRil9ovUM
KBS72m7gQcH0cbbQk3L6WC3XlDa4Z7TQTa6st5TNdtG068F9er9TQJfTjGciXn++lDbABCSL6qE0
Pl7XavbbYtigEPKpOAxh6rSoNaglhNwVUBvWb7QcIHRI9o/L9AUvZY9r3GbjW0d9KwE2+8I6K5OG
NfeseARo9390gUSfdZy4TZv56qqXkDiwQpHhmQcgrTw0v7q6IX3Ji4xD7s9i0twpkLuh/QQlRZ+E
DR6eLDrLrUKKlK1seYW279doWmduIxHnWhYg/tnqyBCyufqGi77lOc5bNthZj+Sv8iUx0/R6NcGG
OW1/Mk8gJ+eSJ+r7+rrcPCZTR7DpMblvaH+PDcAOC97GOet3TlMwGcfh4fEhQJNQeKSqVvEu3l5O
ovzRhL521lUrrT+eYlFNRFaitnDFlz0N6dfGB1iFC82B9hHbWDNV/IFvbtE4rlLjxW/zfOoQ5x2h
Twzj2ImAtJnYHCSMZLIuCSD3wBwTeya7O4XxWp7ZJAWb3UDbYFnWDaK275aiX6PVDfRJQd0mvMHF
ForW7cssOeueSi6Mb2kaIb4gOLLLJhRKCyzUrwA14pdY0cGbWSc/rRnzIV+IRFcDY1XYTtYxCxDX
Kz6oHd4Ngx8V7u5QqWMNG6eSIue1f1Yo6ktmKkCQxn1WEj7j9b3BplvCWu9FGJitcobNac76ocQg
xlRqXWhmrNK3PY8tJ+5bZT3iLCrn9bIxA/y7Q53bTmsHlZskRvO2XGbEQzXU2BgVWK09ZwNsU1nG
VIjtumbF7yaNjHRZGui25Sqa+9GnwkIjTyJClmK2uEpEUWQEksA+zSRCPn3cPnbcbSLAPzxA8Mps
PqhiJv6jb9tWoLhhreJgZ0LNCXl8qvrukNc6pi5TzTe2/bs5R5UWpfLv+b7VeGN6+/mgm7neYrg6
5SSBdu068k3LfAjbMwQYCKZZ3cJ5ZwWgdum1aIVUYh7E9r5HirmEkDv9fo4ScTtEr2cHfPpINY2u
XivdurR3XOQR4LusouRuIkXEATdTymkS4Adp5YWVEzxg4cpFmLL4Hzl2eKP+Sqc8a6ujYBc07Xtc
zgBzCdd9HgYTrFwQs0PsybNCb7iNRJ0qfF15wXx0l4FQoIQN3Npmdk+AXJIKNkTR4itZVht8psG4
8YWFy1ec6ZmLPLJCIwmr2XrM6Jhjhm/2f14v2ghMnusGrkeInoKKpx6fPzZtgplQ7FdNaW1Q2gpZ
gQggbYsXQnMhuzHawx8tHKnwrqTn/3yssOdn9tRwlskGzkOrh5ImLU/4OuMGyepmTJdO8jz8U7dI
r02CIt+CqCovWig1Z3N71zxjABInBmWMZ6ijlsGhFjOvs0bwkFZlCRJbvJYYscH+v5uhKP5gr3Ny
jGXyLEstC/Rum8QJhsXJEDIXpWV0HmUqr2RSJMif3e1WyUmcEzTmPivTBRv5JXikYIPiEP6SIaHo
1Sko5/S55auIIW25XHYfa9Zt9YS0zq4eHk4wwHbKVZzGmrvSAjF+LvZcI5wiSXcuYQ0UVxsFx7fX
wyFrY8/eUMvM3oGnv+xRcrDinAGBhlccrXS4rF3Y4IT1Q0hFX00i+VAMyZ9Y/1uxo35LGpGlwh7O
eyJUGkdlrNhwJsOqUfNH3o9DJ530vVxBO+iTRSHzHZrTNx19t3E/R/BQEeM7xmWVPGOPMN29DXjq
1RJVH7VAldR1ZG9OTl0/IW2rEV6yd841mh75peQ3LhfHiCw/XUvq6lRvyrg5wQrE35WbEMTnBAQs
oZR7pRmFyLjepYFepkHUWx82Mos9l7jgJ6riTKSAhBwG2F6NSTPE8QZ9blKlaVNeoL7amNeStOYH
d7bEOG5S5F5WJptMY9dEQXIJ24X/6hvorLxCmNoG2YSIwurp19XY2UfZX1Hwp2iwYvR4e7oYJJzT
poxtPLL8tQO0aY7fXDfYli58URiAcE6o8kEDWYoSyOHD6oAdt5ySiHEzkuAbIGn165fhksRiFH2r
60YlDtl8Km1U50nC38FOk9/eOhFWLdJkDsJM8DA6bL6wTTV0eNIl0S5IFohP1TWOs80H26dn2dC8
lBH44Thld5Sh+YZrmEEbuQuN0oYDUq7flGThjgorgMvzKuM3VODpqB/QIuV0emRZ+g9fTavPctAP
wOkU9P3jrkD43XPCdFBd8U6IXK6bK7QcB330jP8dxVxcFg9fEaMqtZn6zBNdryXP5EK6nTd/jSmY
dyivrSk8Apfy8+RNGurjnACYrE8hS8j+KF7O7TuMEIwfG+yXqqKHP+uTm/PkteI816YtUoW/IInr
p2Xj9heCzKHdCee/F4IZrqqjQsfNfz7jG+nk/L/NaQGU6K7HsIhoA3WiOfz1l0amWzhdEp+0WJUs
u66Q2DbumdJJyZn/zz/BZSnODaLVjO6KpAPuBf8FrLbx5uIK/R11T6w4YgLaoIGZC1k4Hj0YOXWz
TEA0Ma7JGgo1LaR29XY47bwc9yJX427lHfVIPtYr6I/FZbB3c6q9p5OpwDwKHRgWYdMIw6LoOlVL
ssNpKDjFSuFSSsoYYCWuAU+u/OnuV9FMMr4dwJigCLGgIBEx1+3RRDb6xkh8wD1EWkccA+B4kQa3
+yXGtdjCqiREp5/3EYXEacCD/8LAozUIOSFFnrgJ2dz4iB3mjAGO6rfgvjp/8gC3FEsxoeG74yq8
Gcje0bXzl1aAQLIFVx2I7YzreG97mmdztq9hkXxM58rbdfxHeIkErCYCxSapbPh77ApTVUk4iqTm
GJ/H0OrltQ/wrJCFAJm0y+3SpZj7xZSQineT1jMwMgXoHdPBZfvq4c+Db9BZRZQnK6LUx8XX1S5l
WUKlBgTnpoJ5Ybe3V+lVHSlANlOiMRaYnSTljvwipFVrnC64sQbYJRGW2f3+5ZQcRVu6z52VJLsI
wYzyBjPfldqpba00kRCEZmNPvZzv8IqJYjsP51uC9IVZ6pmtJN0kXcxz/bsiMGHP6cDl25YpkoqX
YGtq/jRAzTyaN8I2f1Fqpe/ADjNZtJDpA+7NpMGM+8nEL5QKYswP5pPICmoaF9R2bUpEHwowvMUu
nrdt2P5ooWX5q563F6V4H7AaHhSqbufUAbr2yW4g/gklhyUzkb3ciPN2bsmDTO4WYa/Mv5Pw1D+n
UP+qDrPMZ0VSES64jIHO66jm5gfDVMqZYxl9Y0n/SNHHfcCavnrawvj1b/iuqHCrJMmObb4u2DLy
HxWj7UzlmBnECNIdxo4gbRJa7KM/ou2HdsznYtv/+V79wNydKM0bJ+pvAZES5467tumS4fLdwvnv
nAAzQopoc20ptjSKkq+GBTtXroo3ynWf3aesCYt3tPMc5axJs8YjSoYuTxkEef1Miy0WNdJ1jQNR
NnDt4sV6qwSDRCbT71IrNvaDGdH3eIuNkHVhItLkv7Mu291abJK4QqUvJ6yY6EDDtyrxBwDpjZju
wJuhXe9toN+c6M7duFsHCSEDd8a73UzEIwmNBNhSdWyfeXQNmq64urYEI59PT06pe4KsJITIsqGn
vyZ4jDTAXDZMKEWDwwhDawOOIddU9rk8LfDYpkdZj/vttmCcp0/U7drZ6jYx77Rgw5f0DVT/Nbki
Sr0/cUin6XIZeF4ePBQyemu+KSrjKcHeGhFByWWLEETmAjG3YJgdGYKSNw1yh96DxfPJJdfTtthy
krN3Dmow0XgGWoCP66hOO8f/LwvmmMIu/1nTPJZntO0YNgC08KTEdYVuRvuVVpw/sXWJCJfB6SXa
96fSIaLk3kF+QSoxc3GWoEgzjHhcduDc94cEM7Se1baxb0DHIONQJji8rV2+YQUur7dGK+WnRRYB
3z1X+3aOgQG6I5eHgfsFl2YwSfVmakpxkD2GeTIgXn7dayzH9B9+Ep0BQKQt5Oijr3W6xzBEdnL0
HhZVdKIJHcXgT1QR4yrkJmC+kl8Um+qCJSH8amOm+bHeXriTySiyLehWz0X4BVrp1gWeM89jtI8Q
PKYABp8aofYhwW8TOHgGCcmQZB/Wb3a4N5AAtYbsNLW+ZPzItJqd3suow7j3WHLqjD3U3z/G5Z4M
dmqQpxLof34QyIx8MupjHInRoZUdG36THrCclnnPGHkWoaWPktescgW6HKlwOYxg+MhRJWZKG9Rj
/a2mlumlpvZlvNZzCdaQcERV/4m/wIDyBz2eRGx8LABT2ZPG42YCCuCU1OnkqWVPoPBkaALe2eRi
LFDmP7shbBMXAVNzEhduUkA5GBX6x60r4sh8fMZeub9IxBUajmgdjNCF3zsImQ6I8dZBtjJK2Wos
C5svZC/yZKU0A8VMUEipoR1b2t4nHvxodVYxxa88qR1NhbQQxdLuY85kkNClggoXw4iBQphjLpTO
oY12AEhanFGqgZDguQBk10rTQ3zgSjsPHthfdrUlVsXVMdbguA1zrBkVS9b3QQ0OC5Sk5uf9vf51
FBY3ywZqajGgk9CjM8aN2kMthadKS+CXvTSOK4NqzPTAe/D/OK2R/3m0Ju70tDDuiuTP1jI9y2/i
xzj26xFGGLlKRD4XUSywoJrfB3xoQSGlGT6fd+y8m9aEm4o40lf0V8BtTXZPX32jRaCS8Ww6SZBS
ilS9lCBHvyDudl3MKcuqSkj9iSpCTlUs5VmIWEEtBhBu7YW2HyC05GSaCkB1Fr7AcIYaK8Eo4QUV
edOL/v0qb84TOZTo387zTakUK08/slBQoftj59ZaxmtpMAPbKREAo0dwkQHR3UD5JEgHcFshKXPt
I7huWa5AYKSc4nbs3PEG3ApgC12dlWJEvQ6QWonbRsJYCa82eyngHkKxJGbMRAok7uVLoqAwvVxA
LuSpJzu/GcjEOtWx+wV84SbU9oDxj9SMvW1GgTwIHfFZDIbatWnt/VjZ/81iyn/gRTId1se64hBU
Fv+RUXjpNH5yqtubMl1YiB+SIHkXRyvoI31zsis0pe95NYWN9Y4N573uR0b5J05UW0HHjUQEOjig
dHs+/KpMNHHI0izVPnPIMEgiK1rFlWkdmynbPJ3xTfNfqKs9Z/+b5xoauKBIFniyRcjwQ9DOK58Q
+ut6/irEzpZWKFTjkzxsuCcLKUY/YdmMTrgRx6yd90nvB/4Bw/+HLWZFpZVTr33FvmrtZB+tj0IF
ZZ0FK2y40AKbWpI5AL3tjCMjm/QyLdfgPvSgrbYpDnwOWNRIEFpmH56r7dXVd0zQI6CCKVXJXU6q
X0HmXofaE6y1ciNH8H17U7zvXRCSe/t5IIW7O+zhjJjl9TDQMNAo4FJ2UkvcstAjGqIcStEftUzl
2TtT9rmFbvlc3sUqa6dP5K4qzLUzgsnU7SikNexexp+lBtvYTega9+osnn0Rh/HXL0967jFfTVuz
dRMAXT2deE2hM6kK33sqCM+ZhQbgyB9TP9++1FgSosDqWX+tll1GDzir+DcsjTZHDd2Q2pxdpuh1
+bxrlo6XReCzfZH5VgYU5evE5g79cSm3OqtCJSnUY1u8guBEqaAlXkzJr2VFQjGMQq9eEMBehwz7
yjIIIie012xW8hmHYQzE0s1KN/7gffniU8rtrtd7MTiMwiCV9vd+Vq6TNEf/SsY61+GKAiFFMURc
m9pXvYX8ZSgp1BQLZ3PW34FjOuWVybFCgqyep2sPqSS7lrX0xleG4Asv2P5W8LpRcUzhmDEIXf/Y
jtU+7q87smH9XdDZDKBpuB8cQRg8IUCx8onesvqO+P58ckD0CF0PLqwq9MRd5sYF0P2uzfWssGMz
GljW/k+bxeB4536KtBl6vg3CgQCpnSin+4r0rPet4oNOshM0kUsy6+GLHsr+KYzHR192/lwK0M6t
Yaa8tfzQoKG2zaeLdGLN1AGwG7fFRkVC35gGmvYxyx7MKjomGVmyM18jN1K6W+ru4ofe0ciamCTi
FaHK0l15sRC1A2pg2PxbdPBisZ2tt6gZRV4e2XK8nd3pVRfLS47eJmEX2lCgoTUwvoyB0hWKCk1S
9dkXMk3B+T9bDFviw8KFHAw1ZY7binfOERS64TDmHaR5qLwexqxP81O9VfgXMJDn7pe32DycP0xU
QzLqRmS+AIlPD97LsE+4EabqdIyRi32IaBn29CEFWqNB2rcEoPNRveSWb8DkQX6+aLm5agygvxNA
m1LEJkCUxE9/S067GDHKn0Y3vWILeF7xWJ8mILI2fqSlDzDiWCoSFlRY4qwruhKSwVGmt4l5fa7B
c0IKmd3CF9WeNsLLKR0STXBnq3koYdXYBdozvVbX6ItoVub/o1JkkZH8Nm6wUuwa7FwnwvwArGqO
El+CDfgZIh8qBMcwPOhmgksGSh16uhROhr4LiFs1OrT5pazNVVNqWVWYeJsX20VqRRv78WxuSpcN
45eLc2Vj5xc9yQi0wV9xZEdSsgbLpi2x7rZyjyEONdpe+lAg/xA95RwDJu2FB1hw/uM/HrI6jNQ+
MiZi9GX82b90DJZ190Mx1UggX4uUyFUn04hPH+AFhSsO6Z2pKZgtM/FvzI4PQ6fRVjKw8eOIRCyN
5o5YjwFR8NQ03oXMX4SRcJ6H8Ba0SAB01QrRp31uyunYvCJlWXEShmKtktZSDk1u9gdjW6JQjaxZ
h1om1DWQOPUFauJiH1CG4393yaLgnaPQ+C9KqIGImiQ0N8g75L0KG8GHMy5ib6qSzmkMVPj3zpLV
B5d6/RmtdRQoIN0uebsy688/LZJNh+a6eHQaEyE5NXSooTuIhZbq6DHcRcLIWXqpEJO07k3+h+dG
23gzkdLTFOWcewzQnGTXh24Z6gX3RptgbZJDB795di8N9yp/HtrSE1WJt6Q2eBxKyldaIG7dMimu
i33T9Okpsj2/BkyUId6l9dGgc/wd5yOQZapwqoiOjxurxFKIFa1D7O4DzUzgG9E/dFXu2JjmE4Rr
HpfzcTq+nYR/Dz7sAMrpuhMWeT7UY8WeO0gC0OHvDCzUmipvzhX7tysVqgKDIrwJK7D1Zlm1Tx+K
r/3SnrgmkxTf3Skk0pR9ORVliB1XGWGcA2V6SmUwLvVZPMuo4x9YP7LydxDU82B2lV4TfZsuIeHF
KigNTZNvB9f4jB55o54ytGitabGze4fczbihb9iTrlFwattcKrnA/uHJH/xs3acM/WOnr7sEa6ey
d4sitw888ybLhYr0khvjCNuwvWy4Ri4ZIiopli1fNLnmxaieDgySxakxybFqOyTPYkRwJ2RiEv7L
pMBIoZoMXSGjEYDM2mu7jfhSYIahSzZeUghYy8mY4iecF25oxIOhwDNYYGbsiA/oPKCTMvJ8sS18
21XGn3DaNMEhmRMzfDQ3/eFAJG25ou6exww4NQAc4umww1p6iVJ7SWf6emHvX6KHI3POSTiNefMT
psxEijQ9MCqCKskeA+NVCuJbOA9bK5rmq5FI0CwsF9g5AZJv8lkuYFj1j8QC1ra3XNrEg5dTIDx3
/zePaweUDnqnfpFPF5ZjvjaSqfCyTNWAtWi9VTfmGSgWPIaseN4mppIzwpTIuWfeJsmmlQL6oiC7
bR8eVx8wje3OXtzDD4pARNMM/yENJNtp74u7rQ+aTgEmOxQp+Cl8qw/UpY1UGcmL3yHLa+OfBf2k
gj9gXDfhkdvlf60G8nBpW6PStRHO1YZnC2fPfRPPJke0SWikwE5cH+UFKYc5YA0PJpK7vKB731EV
V12m3nxzhW1BJ28rXdrVC6M3Yx+D2v6apJ4eDY7mbd4a3KrAuMHhv2LP5pQc3mkqgsdhPAsJgBh1
a+Tid2HxrFD+eJE5EqGfgfboZFFYmvk6GSFwbt6LxIeEdIJJcJpsQHqkdrypEtch+nYaYNyDOcpe
UIZQFk5WIXlB3iUXa1VbtGgL8D/+FL3e2wVTwui38lgKLeUgMNBVkaoZRoQlUulX//R+ZTuDSLyq
gAGcmyqybrlqNQh58/xcyPErZ4s+pKDH52/zBoxOBLpEoj6F+e9xQZsR0yarimj/YSWCRNF0drsj
M8bnXeMFUh9ibHKoFN1sox9j+PjVk0sZbZJ5iM1YxWJWiL4X4T/eIkmNusTwRXQJFsGYbo16F+ag
ZceqF1KQjUPGHhRq8isfq52vl6FrtxzXMxhVroIQ7Boq+t2E8c7awMNhwQDRm7EsP3TcXM/p7mNo
V40WcLhGNHPlv2LWf8qo0UAL6DuwEgcpE6tg7STv/qNgO1iZPtsNYH9YWXmqgrc6uT1p42KN9kYw
oyPGgjUGnbEg/+veVre1KNJBMfWbQm8EApcum9/dAZDa0aPYFnvAmurIaWiYjf8VCnl0n00E5IG7
/cDO8/QjUtaf6rVhtOZn9Y7TdA3+5fLd8xehp0BdWzWBE8LlCc7HHzWMbQBJHYejD68xbEm78mD6
iiCB6ZpPX3ZL+1FwjCmQYbCqRS33l57IpLaKRDMnRhDoooGkLJ+y/yCeCmh8iliHDvkZtgGzdW9x
469b8GIkFV1M24uRfabzuzk3H2T0x+AhZ9QPyFDrS7L1Ff9azRt9qxDe5txSGrHmJIRlCb4FZ4cm
u2S+sEryDdUuzjHHg/iwU14Q/MR2dh8DJQ390kaKVthnY7tc0bjFVkTJRTwUFVKfnNdFdNQuFeTd
hohXq2j+LyQ51Kc5yIxzU2gfqVD//yP2tatYU4uWsyoiR6Dz8NtKEi25Ygnb4AAfn2+pMK7rx2I5
1MdRKr3PZlyyTLH9FOd0SiWqA0ydTGhORRPErFeaUUGYU4+31oqneXbF9WoKI9fouttQ5E16VQQX
HEKzWhVXU/e9pRVjD4bGOdkbRH8Fm4x2xMLTJDmM1Ph2CE/ZS5LisoKtbr5SJzHezqHhr+AMpGUJ
X3/bEKKxWZSS4UUvrJ3ZBLRBih3Lo7oCCN6+GcLDanFUgh9KU8QoqyzLRJCx/K1G2pJO49yraUB+
TaBHWlBQTX7WiWvbslRqK7vmQzbwKfJlrJ2OuREHryun8r48AIJXUHDonohZJ86FXmVbpvumB8u5
AlDa1UxnWH9VjI7aSgNVykgl+3vXphf3qC1H9ffIZQWOlyUMeh/RKuXgn2U0hwyUdTcoS92L6k+6
K8pqTtq+Lxuav82kTXa2L6CGiRTF6dId3mAVq0d//IVWXdVLQLSCmKxz0I4KuwuaJlQHEruLo2Z5
iZ/XQtVwJxoHawULDd/vb5iTHKgvECozOROwV74XhGdUocvQYRHjetK8YoCP/EfBLrxZvWnltffa
LD+/HR7CU7kBli4Egd2KkWSXq4y+BySdCjYjI/XHuicHet4uqH13PKA9h1ku6jQ+1gSgq7H3lgHo
1z5MMx6ffT+mBSpz7WlwdW1f1TiMnwscna1IbV0cI2DhQ3ZtofNz5eeO3RbsfgA6YteYBi+lDPrK
q5YU3gUDPRE0QFGqL3OavU+vDVUUoM6u6uzkkfJEmsogzd9YcG5Y7dr/1jSkOiSNfqsiAmMX6ezC
IzMk4K8fQE9L1PqM/UWlE++dF5si58AKTgLiHaTROCeBTJ4jIJDIvoJ64EkOiZbk5Q2cEG8toz30
L7Y5qzTbiT6NORiSVhpZfSIIh9AooE+2/SrJg84YYepnCGyG2HqFYj/9yXKuXIlNb1y9LK4GaCFM
tEWMK7WYRzuT5Fvrac/IBda1Csl/kHTNHlVNjZkG3Dls0xdxfWv7MnioUoH4vb1SYcI6YrrD1biL
qqsxOpjJ5c+subrglhX6MgDqy3mGxA++7bK/oF2QhWrcO86SIINEo+gF1/jMqTZSi3OWw4vmay9z
/1TrAIRD/TtRvhiv731AYxrD+wS9TgRjiQpN3UVOrWuKs9EUV6Nb35YM78Lp7H8/UZE+ogEwz/tA
W6fqpOtHqNFJPOcxlRWYyCkTKEw3fETbTaSav8yr59iaF15gZn8s/6/x6p1DJnvNtlxiVhSvatIY
pB8+0T6sbaNbZ0AVCam2+scHpK23f0T0cbC5QyGN9z0E9Nj7LO8dvr3n8YwzIxDAbmFAUuAstLk+
gYtleDY9ydfK8G7/Hq0mWrLOAUuzAdkg7C6HC1M1cO/syex7dV+UDiXs7H/VCO1JJFPOyCvZkxOX
nO+UnzD6TmV9TIw5dnDbU7EML/govlVibbijNQF2Gh/ygKMFpQoxorppIU6/BQhTP9B//x9xi8Or
tf4NE7/uAcvO/V+1SWKOnGSCzpQJuGYlMwsappnYY537RSblMO2vtCStBTwKxm0xpbXF2Obbi7rZ
s0tcx6vGCX/n/CED7ILAP4R27ONj52XN4PnwbSyTiFNp7KkYGeBk6vi6cED6xL2RLxosyi5c/M/F
ORvo2UyqOPRNtyygYdGiNtTtoBSKvQwWsoYURWov6ktHG0wlxEqeomX+X+ULPabW/A0QAMipz0/k
1i7vbA+As72UZndkm8iFnglvF1bCHaD1eiDhJJBBXdH9VWN/mPrSwDdcrfiG+GXUEqA4lI9mjthB
laApV7NPiH0O/Swl3pPuy3xbWSZb4q2AsYxpre/wcOWR1AZqA4i6L9fw6DpGTOut4dFx1qNIafev
tTE8kyKcCGN9DHwLMLbqdZ0Fp5DTYEArFSy18PrhoLFRrTKfF4cOj5tIKOdGcxWgnyO3fpk5rlEP
T7R3wAvDMaFcu8RHiiJkGhabtVMYpi74VymY436/Bg7eWyJzqPMWuLPjw6nMEqlAR0dxu74DS7RT
IOqlNhoi/u97WmS42XzWQaB9W5EFVMw+nB9esqbKGrc3trparkfLpBMFOQSvAqfQ2DNeyrwnpIS3
WZgxiqtCttjLCpIHNa0+WNekjEVTas7ESVM6NjJP32ONelhvsvZp8Zl7WOynoZgKotAf5tIIJS6w
C5ic+ITrVnpBg6f5uExWisMvY2n6chZPPFQg4rePZmwhgzDrm6ihlxq7wneSk1J2+M1WbQPJ14NH
1vnErdeJg1Y52cIMbgutWc25Y/O6wNrqpGBn32ujgl0EPAL5G/tcweMO16NAliW+cqvaXAwUxDSV
cHueW2ZNMArsBLRfwHRSET1GV6mFG6ufVjUUqnzUYE7+6a0gM655CWTTHEdZzDgkNtQCRNpA9mjk
iUMf4pWBg3JmlITG32PtI0x1GIAbONWq/nXXTjHica4f/9booJFSpfZRS25WjSy7GSsChUg7MxsE
cAHNbsvPrG/WrEKbnmMbUe6iRNLDSXSd1PAGqbKiXllleRt3KknlSXsOCnc/28KbZyesqUrRbQI5
gvRgtufNOjgF1F5c1leW6SA40+91urCLPv2POkkTem0Am2b3RUHcJfa0+dSaGTI+MCuOIFPqfSks
aJk6kOwo/l9y0k13n5dcQ0UYKNo2k7u5PaJjLGANhlkLNjC4bFB6LnXaZJkBD0JtqyiqWmnP7NP3
MXMQNByDqe1SK+an0+eZxdwfB0PbMfPK8JREI62YieU8s9d7/y9cPHkr6d2G42Tnh1jfeMoYVjwI
f95eI20vv3r/+QzEDz3XHUWB7yF8j2jAnGLeddj4XGJXdWj4C1pA0yU/9FtrPbRoLxcM3tBq6MZ/
TQ2S8qZYoYcvb3Bqv0VCFAsu6D8jVcXTNmWa/8DFEQG6xo9YJWMWY/t/9HH1kuHNa8oguWA0khSQ
bayOjeOBaPb1zaoljIqG4fKa33g9REVWm8gG1sAB1maMq07FlaNM3kOljXkLW7MqQfW04HQsZoPo
MTF/00RYU8msynWRKuRZ0PNXNExa59opYbMbJ6dp+lTetEwN/lDVS/nHSAVf3XA7rTZPe8U8I7kj
oXqR8nNqhC6ECk+NUUKhQmIbAiiVcH8lOd65VWLyf7whDTVx4yrIdiV89mAr3OGb4d97UwlVcyTj
PWlVL8UlFLHfLhdoL7g61yaBliC6Yg72NQ7tmjZE630evKxRD4cmBXEy1Ln20KAnkV0D4tjG9G13
JfWeE6W57ZqaxOXSgI1Wv9KXD9dxA2e8iGeGLzGc7YUkGBjn1XB4fCIJvST2TX9V9sDzNaOa2qJc
2wP83Fj/lCXmHFpj1E3DopHSafA6fnffhJraPs4r+h2jMAoXbQSkgyWTac7kY/WfxCVBakDVYxIJ
YXzrzY6EU02ftJ/PTWoxNAwARhO2LIRGTZgXi6YtFVnfxlmghtHxeXJ5RqDlyqo4XW1CKEkNTpi9
FIB/eRgRuR5JLL6k1aiE3XZj6BGTucfRLTt9WrXLR48dOJdoznwOw8SkIyUyKJvy6h95vmjw1Ir6
ZGJKteKCLK8H68TLIrClHObFH0UqcG3dZzLMdykG0AjkMuYQtebZSPwSlfSpQhqEaXyqplDlCRwj
DZuoUUjk9qo7h/LfUs4z7wHKHgGrItq3Seh+lHgRG4zHQzkP3DfyyCvW6bdkXfAT+TX8faxw9uwG
C6lztoDcIGix0NusiOF0lPWPje77ycozaxfu0QtzmZ6uxZFDhfABZ2m52YX6nFDmbwxljDQOgUMb
sNp8cbicLg/uJ1rfAvf4PPR5DPGqRtSA50bucA2WfgXAZgZ+32/1uNdCNLVZPsi2/FGLdi9+z1g5
5wJyBbkAMyiAlxoiJi3tzufQsRgS98AmNy04YwU/2+kWEJ8k53XmPFfxpQpTrPR619ojjxd5gCxA
rB+V593IEnCvQlyILagT2SBYbzK6ufA2fpdOsgX4TNL+gc2tjw1ey7Ft+rDc9eQrwWQjffxUJcK/
19A71JvvaHracZTnMf5K/5604eZIMhTEs3LAMdmtXLIxBZ+sCvuvnC1VMlBYqceexqk9KRGd/H+K
lCSqLsRaoNx0ZQE0J9XCs2koRqNP+Tsa0PWpsHqCLHdtyw8ye1n30Uwanl9tns5BW4QNAb0u8qKZ
7Ed/TUEwO9jA5AA2aFQqzcvnR3l2QhO+QSvwoakfaV6Sw2anvay0HbIJdjTGe5aEt5wQ4ZQEBiph
ajQR1glk2bBT900qVXrKWExjZLOJkFXA0NPcNeBgdGoxatnNeFj/udGdL+9KppTBksR6a6MuDPND
jIYDS2J11+4QnFI4+EdEA5Hqv4APUZIqpVFNFxC947SUVYOnpd4uw8aWmIUmEF91gx2C7HfgF2D8
bFAEbCbt3DcgwR95TFw/tUrtRB2UDylVRSGvsf2zhDiiwd/Ml1IrZCi+4/W6n5gB3U+f9m/MvpHg
lO3UTix7Gul9Xn3SpRngfPN9DzQLNDWZDYqYeV8rqTi+R2FV9ah4jES/KvF9WXD6js0qBisBYmP9
2ZTatL0/phPnawQ9gASh5spkaZzTS0RXroHVokCyvNawRdYOdFpE40uvEBt+VRSD1L0X9C/5iZ1M
ghGrMX91hfwFnFV0Oc9Xe8gOuvC7mFJ6S5kIBukX5LOA8SX+7mW7p2XEkqoeoUO1Pifsr0Zm8KwH
sci6hdLzS/oJGg33A5lX/CaG5XKIxDutNVc8vB7G4ZAi6XaUDPDjIq+s9PJzQ0ybjMOwTemoUCX6
bYi/0RqtBbV/UuFxFJYXvpTiDCthmJVDLosoT8hknRHQGmKr33nccSPhG3Q2NjUfjyDFIwk7cW+L
CdiWCpAEC/p9vUoi5uDASF8RaKY2A9EYUuNmDx5hXXfiPFKoPVRxSzAUoku9yu6F21/oMi5nZDiH
9Vgps03l2hI0ajDl0+PIJ+prONLFNvbwjzN0ISKRTp+a7VKLHkHhXFMXCG+ATWdbxjjEhCophzUE
Eo9mWT1r7INB0s12VCS4WI+HhWfhXfyuBhmApBqnWTs2rtP+ky8HJUyag0+GSHSzW82Q+Xsjf7MZ
LuYsf/QmxY97qIPqoScAKlQhTeJYSR0Y/KChgj7sfVZxwIQOBHCMcLj1OxcbhP4WGNRg2k4YouNR
JFxjq3d+BQJSPGXTplqK0MqqR7yeHBcTnCJTRUKyntUk++xp7JDvLUdK6zFmBQu0qLF9590LY+FT
cJVBykAvqPpiRPtdGX890g044Hxek/TXlxAulagS3PVFy0cHlyl3PYUQOiR2Csg3zHpLASDcxX5/
JM/wrfagQV0oybEwjfNw+wUesaQnPYCnZpMpVHfgqo/BVKouUsRHjUgPilIWPpJ14WUIjBdlSdta
zOsdvXj7ng/akm5EeChh+0i7gobtbEIS5nNicVVr8qw2o3Iv4LdiUoDCnEHL5t7pU80/o7xkEvzy
UmIe80NjYF3nGwCX2hmw49XLzJSWSYh2EMknE2BEl5BYH5aoC1u1DBdH5wiqkPBON8nOHQgqGBXm
uAWEDcqJcv6LO0H9kHCVxZDE4/g6CjrXvE1go7OJKIxENqrJCvvQIQs4eodYLdDN5ErJDtP4RBZh
oo/7LfnbSfTWh69Rm+h1Hbabf/IOASUEpkMbT19STcsAnaiv1/U4WcTPGYWqhWHXwDi/YT4kBzRJ
4Rjr1qH+Hy+RI1bIpue29qG63pAYJNF7/T++h+R7TPa4uumLShpZ0AtJ++/MR534I8+iFNcr4Jth
64QvglRDFXaAqbA6cCTfOk0HqPEFhNU8457F1OYpqeNEqhfnDX71/LmrvhArr2lSmK0Nbm/QjgIO
+n0g7TmjafB3TOLM2BNzxD8qih/jrMxjWmnMmiqmPDeR1kactnKdgO1Z32lkVIOXGUd+IQzre9+S
H79u85FNsXZz0L1y45F0FhgCWX2faD0j5VEbI09astwv2hKd2Io/sO1l6F7MnpoBs+3kH7evhFwV
PHmMGDfWAbjKaL5U2L0omae1JaW91VrGwVmTQqoFDKOvVsiqYxNKXg4syqzru3XlmlRMeDRLo0Qm
pwPMG4GFtjxHPqtW9XbWMGiKDTSUj4T+O0pFnf9ibijD/TqBWXgKWuDPaYcbFO9CCLhELah7D/NN
+mG9W224wdL0t+KlqXAXLwXL4oftoKbn/NLfS8KzXkZPMyY1CSistDlYBqIXZlMVKcir+wbh84n3
jW2cjgWeE2kPl5msyXRMS4ovgu5Vi+UbehkcueHTnI1OKsf81yXxiaK6+SAJ4e8/JRlCjMI/auoL
AuzVk54KKYsjqWImGWUt2hXmt9ItWuwae2mimJ8CfMnaJ6CFK3ftECgl+UjCUKH0LLoYwSKJcHJ4
Mx/KjZVeC8pgTKcxCZzRYJK4Nf22G9R6meItoF1Rspd1CvlodcsF2aReL90MgUY8fQoE6SRhoLyK
C4WeVK+6SLLeBwORl0koxJeNLOlUSbB+dwh+InVwBgOAfz3ZuD0+ebGwHYq4Xbko69FhjCItZqj3
G4htHqai/2ZBhj/H6OuU2Z8GgXy2do7H/9iEUrjnFnyl76uOp8FdGVrIVKlAsqUNJmhstx+StrlD
kwFlzxzpVQE3mKDxVrQEZOOwVbTFfXeQl139dOnHHklNhQ43dENtMD/it8Zowpgl18FY8xiqdRYj
EWHbCwbhnEiftqNk48qn+6boGwurAoj9VgR7qxtbym4+7WabhNbV9wbYlcrrIX0c6FMd5ZF3n8MN
Zs/rmLdhWCxPermm2CDA0JdR8Zwe+dgP5X3Ur4WdoRhdnpQ2XYXqFP+QUxKNQ9zZ38vbeeXlfiYr
odUZX14/tKwYIhP5mzN9WhBdXVpjEZa3QdMMS9GNLYsVskg37pi4EcvFTCBJwf0UEGtWdITwSVtB
b3360OKni8A0C9S54rY4kClnVs2Fca5L3T+6geso/PVSIjFkK06cAmZOBgmYC3+1fbX6w8RFtw+Z
PiEvkhPz4qr+CXCZrpJPwCn8NVdQlI5o9hexkGu8xPMzT8argHZbshU2uafxCIsYhMsCwf4RoDOp
Kdbb13uGs+jZkRd0WZozJBe1vZNI97Ga7InaZ6WktApM3Y5SC0UPv8CXo2kxy7Hi2azbYRo2bIPQ
7Zqi/0mbLHSsWY+Lu/8hXt/bL/5bo92HU81R3fkMBc4NXlcDD948iZfXQIBUXW2K+8wYnVUZ/6FK
9OpifrYtReLdLi43WUVW2wUpQ7kopMD6zLdHznSC8hZNTvAf0bFaDaawsij6/KHZGcZ1GnPrMW+D
rr/l4L9wR143B2zHnizKoaLo/NlIUFFBffWYfrgJXcfhCXyTUSJ/TD0djuwxkZUCg4OUzy06soWw
XV8WIQQgi4AQ5k2ba6fMvRPhNQs3LRF7zo+c5p0eE6FBmvYHyKt+sJlYjd8mt4wH8JXKIdUdtKPV
D2gH5NSpKGURtEYWZvTUeqmQ4jYbbSgGQZSEk7qn8fWtCk0BIhM3grkGNZWqvjfihjzJgLgPZ2n3
AhWNSqHaF/yMc8lsUYEnChpTk8yf4LF186L42ILswxCVK6wET9thxAU64JxbGgyUnmI46kCGZGJx
K8IjfGZR4HUAyKiRbhUO6D20j2URcZflgRa+RglAu2OP8OVaw0ezu7n1UBPfDlDETaGBjWjp9fXJ
JF/BKfufcKMwbh6pCwoy352BrivEX7pT3Uoe70W1KYsW5/90BILRwYwoZWnZKcr4gbhGj9o4J8/9
rAOG25LuI/rXzN5WeNPAAqwajhiHf2i6IeGYZQq1PoobIKiJON1rPMylqR4eExcMiG/z6gMOHxrC
ECNsYH4Szu+BHvB/LZNdyJbs4wysp8BJOa/kGT0L/hCKhpam91dYSMN+qcQjyaXZLRDVR4NUDodA
roerN+wYmruzyc9T2byrygSnZ6l9SgFmitCOenFd1dmWneiEA9W3/4AsWI1Pq+EOk4KtHN7IVFzc
VCQxpxv42U4tJeW2ZGB2rAb2ibayTs6W1/Pdrr3Bhh2DwZsZh5U++M0pnKRjbmclYpNuFY2L+/Tu
DMTzEZdDoslaI87LzY8AOphwsba6ncFvn/otdpqDqV5Bvw/Xg9EJ95B+/cIIbSvgNr91FsrmkMGZ
G0hP2XqAgXjTND7ICjGzF52LlpZS55/txmkwyLh/d5iM3bZtI+dK6NHxb2gRF4pUj5uAI8RDCn2O
k/kVYvkOef4L8Ub05+ajg7oG9HyZRmQYhsqlC01aOCkYO7kv1XMyTBipy3IMWwxBmi4etjEJ6SKD
B3Z00KlnB8eMoC2CNG3S6u++S9HuE0P/N4XaFUE7JWhqmfti0emwvaFnZg9CTtx49c7V643wDrdZ
tBUcfqXncp2NTcRwmEXUtpC8ae0uc/XcUc5+4dgegCc2IszBLLNk+WmE2XKjQ7gy6Cx+IwKcLIwS
3ttUHZY9IQvBJOcItRre6D00VA/3hlwKsx2qUrq/e4LNeQFQkTfWAPZ5QwokB1jb0ITbvX/O6wrY
3IyVdluN0GC29x4d/REE4PnZ81rDQNNwj0+9eRPerkQ1jqjYLq8m5Yq4lpy+uJAUSEdXlCv9h8TC
HdZddq9CFkKlyS5ENJReYFIWsAkmNhI1x7CUJeo6rSWxpHZt2f9K4d66JTcXvjH1zii2+cIyX43n
NW70xe0Nss5giiejbHDLVyBvJrX3H7QhiVGp1Hf728szlPmQV514mA0w396hm5XXg0dDhoUqyY+P
K6hDOqZitSkdpPiEqqVGYZK7IN45vVBrjt7tKbG2Mv8UQXl4CeeLUuGFxs0kI00oLQ6+RtEWl1XU
Kvr9Ic54AciAUFnseM2SwL7SGOy9dcSkAaWPOt2/FuSbD7E5RFCSj/WxndT5RIIOAYHfL+ahz1YD
PXh764afVf2sHeMwN3oII/gIX6pOzq0m1ZfYylnjdi+3I/pFpCPk5zNti640gArqb+VoaeRraLkH
EFCgGfzKiyPx8uE/2WA8vq9OLb+l+nlzlDklvJUsHaipdXPPYIAXJmXcCMrB6GshyybuUq/hq+jo
6aslwSODhb3PcXq6/Hlixg/xCrIuSXWaGywK4Pjv4xldYa/fLuIuKgBBezs0rIiIJK8IbM8Uk9fn
6LfNtqRsLgXzxQG7hVFL7idpMRAQtNXxG7nVk5gqfXH1CjTfsQBxvu4eL295m79+hPv9I8/hL1BV
tOCNfDcRmi/6ymOIRx4qPj00iQM4O8FU9EuUZBtlPSd+lCSHRgcCHCfj99QYJAp36gSm8X1nkV00
iDlbKmJlQlj2GIZmHph2a3BDhoDUj3wzXxFDVAPfK5u18lWj/Wy21B9zzerswY+EXVeLUJHpJdeN
MDDoZ08mblRJN+b0CmXCW/2vV0BtZM8SNzYKnA6bs29+JlaQ2kdW6SXntLRr35goaehd2W5Mum58
eUKSXxtnGGwxI2/ATm3SDoSNZwz9drhtp/Jy3bnBSviKZzVvaMeCQhrPcO5rWTwycYw6MyV6T2AM
YRRUZO8gpxth0pgJUYlIqa11JCBRozGVN1xTijyF/4c2N12hP4U2J2bPKvQqKlKc7zVUPtPYZXRr
Qbjz0lONh2iAQ+HNHubQj3BsQ1loyQ40UgxWW5+Kce5jvQmse01YsO9p5Oq1zSKp1eJxHeH0oogs
RHR0HAR9QOTSPJ/zO5vgSZoHO+R+QXBF84/xriPXL8YG/2uhh08+HuEirLmqk5V+ZJdtMQhP+XVW
tOtB00MxjvesqM277RDN2Be8e9+g6BtGQjsV8zX7B4Jdlg7yPCK0Vjgupa30yV8Cn10hO9ZXP2zk
BhBqEDXeVW8TDQjaKG7L/HoWuhZxtyuoWuZpnP/JP4Nl30hpDPFQ5h8Wn+Z1ODVQJEeysY4d9+rg
/gWNh6TarPL11bGuYvLTB7IBrLak7yWgIPOdtAmU90VpoWuQ8r8fQlJ0gIl3xnUbBYl1Ubpk0fWT
NdJ3ba9iN0hcZMl+F1vd/UsJda3NXepz12srZwI0WmWSQoLr6KmREW/fKN4Txl8e5jEQFL68zf7d
HRfxgygvDXj00f06KT9svMz+5nxcdQb8b+Mijq3RQXWp/TvAGF2ORUtNqTH8k7JX22or/EjY6xc6
RyhTJRts0+dC2tN2VFunE1RlnJxaJPolWAyPQrpkvrK/8mgQXW6DsBwatJWqJpF2urDXX/KfA6Io
iV9HYm6v3NXAREgyP7JZ054nsaSwL42Tn4iEIjLqsTBLnSp7lAX482h+n15lbMvpMPFYEsFypI19
6+Scsnqj7PeMRYlraYw9M/8s2RuI4M0V6jsURyZxB2UvMoSpO7q6lYtrziokG/SqQpf/tvhviQme
/yeI7D7PszUt1XFVr0YPGZk/x4lZ2a+3golMyky3bdAvODI518e8gPSd1D47aO3Um0Fck75Eacjs
Yia99R0U1rNJ4Sg4ur0w9rJRvIjl6QM6Tw/bRrZlynwfg4xiT1QTePGJ3QwoNyJlu4i9ZXmBEK6x
e4fJrNDNwz9RXkIEjja3n8fEdslnfgJKlM4oLlTSjDCGAMSe90HbkZl/p/c5/UtxPCKs49y9cAsh
nVZ5TB1OgP0S8nNjxzILpR5jCmwqyWNFdvyqhcU1RqMmS14/YqfCsx/a+RdNzwSmkgDB7uJHG/0S
pV3R4SupdTjUDz2M62Zr1wki7qExazn64Oyf7W6YcVp9dtnUN1SY/TW1VjXqbwiRSnGKQwN3m4/q
IlNMRfjFg63SwTnxZcwSNHgyY+jeeBadsCsPpCD53G7imbv8WJvMcsKYs0qjB2ergc1U3JvDg1fi
JCDBTfryCVnGOKJC8N1K+oouNRWHfSIGO/Zm8u9pfxeSjSPxSMncgEIhtNm8EMzOjbCa+hv5QkUL
RmKuxsl7+8/Hfn6qkq5tsdt/fwAuUzuDnr5Z3dCZ1mwwTyeVzikUyErbsUbsQqKH2TWFPf8RN7AF
PiHWsPxbGuXhmk9vABFVzyjLxzpj/eDuno06MaitkvdtSxBfI070A1z2J6DpOP5mPb6duqJVc8Ot
Y8N8koGnGlgPMWCwGdhi5aJhaNQ1J5D059HzU243zJXuocbOP5+zuNCIHKdh0w8wORen3pVArR7e
6fxqRtfJrhZSRVd5Rnf8J0yTh6VVKqUPEfUxz+z+Z//Qs6IDIWmftfOLMGJdZCRCOpVs+HoHchuy
o5ElUpiBCHLG64XBv3ue7gCWigd/xDlXTnSQ64aJtqdflKBb2Ds9pAatjsayMv5UnZSQwGfEvBal
/5Kmm0Nq1Mpk7easpjR2Nc17YdGs8XJVWN4Pqm1RD5ubVeYMOsNJPuf805pQJgnE/LJUROSsyhBR
ShdIPrbGo/hq8Fzp63AgZACQKYyvSTJ6z0Ey1pE1EPuC3AhB4XW+t4TKH6dPHOCgiUaEdhUGl5t6
2WisNIr2Rlt/nwsNyqMGjjzJnqmehEg8OC+HtAzRHvilB/tga0VwyvNb6nU2oCP83MsIMdvVikQH
2zgO1lx6u6W7lDXLgQ5xTUa78SKqodTWNAOUqoYzG0rjZL4PbbNOlqUJsaHNs5OI8Kz5WgNv5srX
o2OoFlvZ3VrzZV6cmXHrDY2OdQUVmBV1vGDPqi1480yD+eGKFoo4BJsHOvNCpfoquvCk1+BDhpAD
Vespr252Ni+vN7Sn+AEtpjreiRUIa8XdS8FEd4AnILACPdE/A5tBk1aaqg3jFdDaCE294AWitOd6
SL/t+wEt3VBf1efcLPlirp4AhQrDt9JIKE8UZm2Yv3i8Zq9EHRatj/Ti4JlDGkDRue8F31yBBd3i
RtidQ/wKnSQDscSwlg83uoEQ/SC1jkukpdI9cOOsphxHYtBUKnKoRJt61ZBiuaNNuTBnAC0krOCa
3MOVDnrw3nwc/A6MZqmVXOwGyEQp25L4DM9OsQCp2E+QRyl0MpcFp2JLYzK9Uco8eN68lQS7qAre
VrocllvTAymTcbHCMz2CYgaXf1gy7fgfzRSMropOjAJU+jG+1nIqiDqNMThzZ5UH14GJNk61WLma
hTycTCWR16r7XwrqqxGH3xd1O1K3OaFu9/R9UXnCub3i8QaBXB5L8ir2lR0Ny5lLi7uwF79t01xx
gzQapT6H7wgqzZyeJ3dwksKxMYFuxFFnkn5BUMJ4dquRFpFoKl4u3dFwt9nXfpCZ+TZVSZJTA447
q1nk2UitXqO8xU8kE8fxJqd32z4ZmYL58AcvrzVF2RprOOY5eOEdWFZUU+6/qOerTyVMiLZ2aLKE
FzGtBmhOLzDaBdPwYCY3HetE3tKuWBYvZLHHFEw9hQ7JR+CocB03UglMirJgIah3mhLU1cAu1pFz
X5K4DAdw5Zcqbr/wV8c2sGfECEmCwJcWTdkZPduSAvjSzbGDW9Iem8xfZkrLxzlDRCwQ9W803TYg
yPMaYGCU4kLQzL7NMFVxHRLgytILbVxQtPYkPbBGzyIRP8FHOH3/6TwQUuhqklE20YyqpfC1RHYn
3FoQTjxNM5rI0/bdIpxD3kl9lNdBfa1bcwu9mYylFmkqxxUGwBOy8rhfOc6dRL07Tz3mmoIW+QnP
hCK1z3WzIk3/sKNrNgb+Ssfg0tXjUPOTokpJepBmNaB9Irb4nMbR5aykpEoP22SS8rdFKiDTyk8c
dUYPZYAJ0jvbTthyvMzAiiQ5VudWMuO8h84yEy38ufZa8QLmlXWwewySiu/aF7XSFoXRYwJW55w3
HrnUwnv0g8RpfS4KG6mqsJuPouL6KEIsZK8ETHegm749SL6jMMvJnJjwZWn6TEC0spjKz8CJBpTL
latN/hbUAS0lUdhWXpCjuTC50F1PKi/TdCOb3PNSv0+kDujqLQqB7SO31oD12vGwaczZmWAXHvMx
woMCvrk/DA9gG+QFPuZj7qqzbnd4VBqQQtpT5s/pB4O4rxncr7E2JXDRVIfhnt8att/Z98G603d8
uE7bke/bDz/3yOGOlvwRjkqKrDyO0hP9tycrKq0CBuLRDTtE7/OwvIe/4BHBTAMB4eX0iSWBf4Jn
BF9k/rSyKk3K6ofvSlQksDKNTWf93FtTLfA1z38QmNHsMfbmk1GqgB4j5mESuszClY+z5/shiRwb
Xto1bAs1c5us8zSuDeQAZKkcHv1nHvuFscX64M28AYNO6wfwL4dj8P4JRzAYv036ezT3aau9rg9x
P/v/kmY5bcYu4teby/ge0DIsWd8FKAtoOsKPvyz+CCKVSiTNqvq2Jf2SKUfInFjlAsRlHOzihNQe
U7u2Czivdf3XG5HS/GicF9mrkiWuXWU0/ftjBIQ+T8GLKiyDW9zl3AGqZjocy+LYQ8cna5IAM6Kk
lkldTxBN2kjLAKTzFI4NdfUNApnTWM8hUfJX436TsRMq32wpALBuzoGi4Ht3f3P07jIzQDpZMI1F
HX1hn+cJT+wrLSNBLRlue6Uedmq0VxxM0g0IqnKLCpPWlBO75Qargx1XcD1dakcJrxvBTZ5b3dLy
+nhAXh0IxNx/BN/rVU2qU6xMgW1cOZigchdcee+LndCwiDelaw7WM4aYkKouMruHa5CH9a05IEg5
KgzKAoZ+gBJ3jEI+6p7LfhahubKyZvdnxjjIW6A+0OKIy1L6vPP8TSdBoCWuLKlnyANytGoWOonP
GlWxYfrtFbXDamQDaCR7iDTNSimLUWTTSvotT8udA/+l0aUNP3JthFsq/tDHRePKbmNH/WQ0Zr1Q
Xek1YrM2MfQi0DuQ/RGD5sWLTsZQpXqSBfwZD0NXw0ts7dYTv/FVtrZfT4tv827CdYZypJpZbz2/
SNzaAtLG1jvtHr7CYPdzfJvT9mzpEWeRpBEipgOCLr5Mbb7WIPLqMdpZdM4kdTaMMtnhJ1vEcxmV
nBng51etIsvqFDsgb/lcqUwnwYAhMiHS33XvYKraNlNv7b6saM8Nu6LtFAo3bCeRGX4icOyu3eFg
MmuUTlij91lbofdw4y/AK+t7jlDbPf7MQxbYSJTk1SN6rooPC1TXHe7i2JU+9RV79gsKM/kKQ6ic
hTgjOYWPj1iJ0lNVDF/EZWv9VePsZ+THm3KShTLtQEH6NgkOQqZHweTnhlbPELq8xyOh45XkpNLW
ZoSN3A+P3Maglge3hidJwIwTLxjamOO4f9jXqnS4uot5LLiuyYxSdm2+SBEVr9QXAaIfFQ/eyjSx
4I3L5xkQEJhEi9HpprzD2n0rNxKR01gYrRgyooqLLdaqGN9ga0ACDGK/NSs0BNIOi0jJ5GglvZjY
99PH05JFmmfntP5N+u0nl2QP6xuJ3FwOeLBBs2Bj92gjIXYFvDkbppdM9Ul66tRH0aParVtRMDlQ
6YZqkCac8Q2zs1hPk9LHaNc3gcBWT09Gd5UsZoIAAXKXcf+JnFadE1LeRtC/41tRYoL+ko77Gv86
um8Am24paffHnlwtKi813WLMRBh4mhaXoAPRQyZWpCneb5uQSGDbQoecgIVoisrBI3YTZu16gGXL
IQrq2yspkxuqe+V6vX6jwDIPfUsnyC/Z5HNH9mdAINtoEcVAfl15W2vctyPybNpTOKjhBUk+l/Y5
LzZXQ8kxDXPLqWPpyLlPi0soru6crlfy+l/H5y4oBf+/+5jz2E40rjEVyyv+smOfdWcMzZB3tVoM
v9Zg3oETxI6qIsJOVLmHJly4PVXmQw5CHqPaOWIzPPZxUShaF9JZ2f5pFppDJH4pCDltBM1lhVOD
BHf8eqMpLw72xi90Twf87kl61jgo89KZ1EHvTfVYQSt/57zTkPqEREIjjYE/tZNXjK+WmkVJA1O6
jKHKI5vKhfnPtCOptp56Ibn+pxy6JmawH7EXvqXzWDf/8OIkZxMgcGtqsjCfAv9Cyi4LQKGFZ8NE
6XCvrXU8ooAiDCuLmtM6T58ryo6YFE2ql7SOOTAYXae7AG80L8gE114aVmbjDz806Qeay7BeHLfc
/X5YlTldV3mTNLTKmuFnSI0jqoLlnOwbUs8SfDYFq4DlHffiQgdOu7nyrs5pEIiaClnb2qSpbG41
u5ZKtT+uOhb28k7YeumLhRjC27v17s1eD7JYOYDthZZz6hAD/EelWTEUNBDizPTHpn1KCyvBre7u
wuiphSEsukTrtpAXBkmO3Y30OR5jnwjtJpd6oNJgVHugWjqybQzX7zq7DSFoLj9eyX2t6X0ISJSA
XQXU0Uydik/qBVVQbaUvbFRu6liFINPx/gByhDqNVLETJhX+qOrjzcGq3cOZjO98gU08eZBuJbyH
rjOqrJs57c+8hl7In+yKVIdOPZtp/oiOiG9nMiNxWOLxiuVeSP5KntgkzHASwXvV7YKHmo4fNJfa
KmZNPn2M173VKfv9yfB42rMTKrKt4884sYSkLe7PtnQ2jf5JPhGoSb3hg7akFknN12DtfDD+YOSV
D40pISlOwo03vXmOwnoBWv9BbGtZmn3ocOOVJlMeQUPJq6m6NX3ZvYw9y2UbBhAIs9N6MaEqqWwR
4P5Ft3evdldxt9lG4gQcqEuI1d2HTZiEd2oQgKcpG/NbKkZS6nKTctT74A4CZD3DhsSFD3/O/QXK
Oe3xtEhUNzwwUK7fDZpuHxnsXu9B648ITu4P77M6KSGUDE5d8jDwW+b6HHLvbyWJyXqcJN2XkUvH
tGIotLtwFBVp/1S2BjpLfv7OzFbVesYC+e2qi1tdODVVqalzVnWd9EibNFUG/OfC68XnIcxPFuTX
q+ugyjO5KwouilnyyKeBxjm7F6UgDINgbb+QvQjt+gVWDojLswgL32TvvjYGbMAGSDnmG4bzyOgM
IxMvf/TpRNEQcmPJIDlBtBpgVzOp4Y1BANi2AOTBpqNgjZGUlCYrXylqAral7UgSrO4N4NHeqB9p
yJYYAJ2aq7MZ5c8XLwmA6fCzhpnmKfTQV9Kd6LHXB2tCVh7y3K9balbdtaic1bQE8GBp7N7+DfRe
4MCtfT6hSmYdMsVFoRFwa9nlgzVADGWQCkZV8L8afMglPqM9HnA1Pan9ITPoSA86g+AeMHguz4xp
eUtuMUXcwoSERO2l0t2aJ85cedzIpRW5tr99Nqim2tmy37gwSVn4jXO7pbcoPbGNfIo4/xp5VdV6
06AQQGxGNb5fgvxWobmbN4kJAFpVX6F0mqJB6omE0dgq0gg64BKyrOy5Ca0xuSmPfkdEDVGRDL59
5/AYqRA+XPC2QP0FczMKjOxjWqhySTZUb+I13FUyi+RUiq3SaYgV5DS9IDQcjB1pabnw47dVgl08
cxhgWcQPtUJeblDBwHcFaylCqh7IjzL5EiegyufagXWfJ9rBB+hC6Z4+jBguWRUq/bU5UG6agmpC
s2HXW19fJC6hasajYXWq5RdxWaFLUnVQ1tNqSC6h39jmdznY1sWx0xCqaqzU5D7mh/yBiBiTq3wu
F4pYy3eyI5WfrmD+koBf0Vebnv773+4oxdHPsg0/oIhvPHTb2g3WliBDWBpE6hhnweKNcj+f8Gn8
WaXTu1XlJO7uOgerhr0VVxAjk5sCYpCfXk8yrY7xu8rm4259XpNAVcLdqrLpEhn4g2fySqaM4d9+
E4ZiTbDMVk/HQ5KOXXljblNIg2Kle5/kklDpWDVs/Gm+XEEWOK+xGv+0poYYuQS6BB4qD3zIEhhK
jdfTnHVvM4v+L856bnaW8ltch+bQHMmMSOThQhymRloXJLbRw6wpNqbZ4CldskYjyGluOB3agGnV
VRDpyGkhO66s7PoB6AruYSgx1hdlSzR9fKXoYOmswrOUCWYeQsik6oj+hBUBXP3IKqXya8wJGixm
8bLvtnO65PMNksRS7urCto6+cDQVsekkJ2mZW32cQ+mXOazUHlG08fcY/XirpQwBPMo05Vm1LvEy
bUlJaMWBg9sVeOd7ihsLU6JCYQrbpZHnHNMUUTD7d712qPXyq5jR2AdGme3QUqAZaWxGzc+/oGTd
Bqt9eCcE2Jd0UlMrEPuayDwPIQKbIa4kWdbKQYXDZOz6qYBWjvuAyOtgULGc0sgdZ1l7W26y7v+9
IaSfyL2ziHgDbrgxMuhN44QK5eBPb9WazGLMtqsHNIXSqQS2wFHCEmlB6GWoWYMqhjEJV8/5xAW8
whk0hFXGo3l+qDf/3FQUfJpebLqiXMYldYdmRoZRUNad3a3DJcuQ8b6ZLqID8ROBFrN0MdJPqVAE
Vx1gSA5n59xj8PPCp8ACZq5ID3UDrx/FkKZ9iA4gRCqJowAoxCMIEpgXjHlZmr5QpN4A/3wkkv6+
xmI9/+jtoDP5GWWRADXUjpRY0JbHm2TroOGUKTBxsPHTgFiwssgWsu7mLKVy6AyvuUnXlDjRv67A
JuAdYfmXDMh2jAR0LDa9VwyN942BTNaz/s0g6/I495bTvHG2zXp2wJZQTYAi66TY7i8s9AgZF0OC
e94Fq1FPM1l2k8GQvGtZOTqdoF7pQlSb3/igXAGjSQjCuqKN7A834FXBSRtCsLB+iUy9JogIk1bL
l6YnyXjqZ8SDuoqH2QtzSXYoT/cbu+KruhNuiyLJeURsnM7SAi3r8TjHFCIe0m8Fpk+rR6Cu9+3p
uH0uIsW2oHkvn6D1aiNiZt+BlSpuo+pvtUeAdSSgF56TacxzqqUwZhjfYHBnjFuxvF1g4jTEPCXn
LlQDJ9VKziYDHr0Gc1VKLmqSEQB8wD9yIQ27kPC30KbKL1X065elab3G0/x9ha79/KGyi3EQ9M7Q
y6bE+CwOPf6N+FX+nJTzlfkQOBreaQEeuMJAMinZ8JGp/k+94IqTAOI+3rQkSS7uapfu4i/APxF1
/c+vvQIK9dCzxKh2fyNzINNyL15pL6ieiNUys+DWphxLOZOjcWxHkI8gwag/bv76KvzeLCj5nBoY
8wHL7ShnCIrwuVBTEwP0EMKvfvO0jJmpHrOxbLwt/ZqNDpPtwb1YctqgkMCkfXWOun9S6CSw+kKl
ILchqh/bUJS3GGYuDqJcBa75XvV9Nk75xRbv8OoPjdX2PIqvojCmN0FRS1bT20PKqI5AnwjAulg4
7vat8V/qt62TJUve29WMuKLs/3VHcda8/A9zfibtM1AZFiNUPkyPbCIXQ9V6XVsrMI0SRFSC3CiF
Sh6VdA57+B2hpceQThGXwnRWDL8oL/6nhJL/Kv+pu1CHrt/ZsZ4l+YCz25Io9lTT1zfuCT8rr/aa
1PUyMH8ya8DDNFevgRFXRCdM96yecdl5UoOPFiVkea+ZkPzhJdNpyC4OcR3qjW2OfygT2NjR1TOx
CJcWWsWEsWK/0LQ/FrWPYPmZ/DeLXOslvqYnryqWz0n0BghJCJAQiZ2LU8kWwjLvciGyb/JnRHej
4125EuhvDws5uYpYkd/rvSM38BJYRAk/o1h0dGxdjO5FSa0i2GZfkV5xIVOCugq/tiK3JoOtOHgG
iH6SOU1s1p9MWrUxtQ7cDTm+juyWYDhQiPJOcv+v5nDjA7jC7QMyJ6b+Qgju1VL2EnHMZg2PdAgK
Hg7MH7oxu1eg3uq+sy0AeI4BCmHP+qvdJ6oNeYiPOTC85L2Z/FU76jYrMY725hwuR1lcF/HJA4wp
q0ekqA3vfKFgRIe9bNom5EyIoDmeARWC+3BNRtkhb1o6dvwSfhZvExt778UpxZyph7ivZV0eRQ7M
tsKhnFdgNEmmjUDAPWjADGvyFolcf+Clu+tir4WaE5uoSj91oM3HlksADNBFrPm9tcU0Yo1Tml/f
x3ropnVKtR/iwuIcP6Sxe02BrqiIYwRvvQxLZbCBgTjbrjQQ2tbZMtb2ScB20gIH3i2irTpcg+gu
vhdmD3VylAfoudHeqQr/BurdIgJOoZwJC6L3HOh7Yk5JptnY6BvyWl8cq+syYCJHDd79dvSoBLah
v7RnKw0rPqy/5ZJ8CAxRpeetpDper2QX5PDxaADmmV0mibZtcZFKLj1jJWfmomeKEfNqK+gRg1nI
SjFgU0UOJHve40lktQH2Bwvu8iN6OOTaLp/1b06DavhUZLERkN8URG3F0c+yc5tK11qv8RTX7yOY
cTJvs9GVu67qOVpEOs4IOpPor33Ci09skk5ZEDDjJ6rIJ8/JyDZwqmcQu80bD8VzpTgwzrgCja3/
02NIwIO7vKjpNke5yKVpXKDeS5gP6m5oiRzoFy4JEF4bGzIZzE+ulnlGis9zVmLIQ3mKfn6kIoQx
EnoNFogHH06apRS7ZXoJIxCWe7vLI0UfBqIcM5ydF2HxIh4alI6TJlnDwayT0Gp5TsfYV9OWf2lx
ZOpVGrUWkb3+eJq2CNlgBAl3UDxfRDEkRH1WP+OzOE9vskaUd4aMi91FPpVD3IS/1ynz/azf7Kyw
K7dnc7DszYAYzJ71s2vmJJ+BRjpnl/xZ1CR/x9tRBqMahqxpMzMUGl0r4tQJ2VEMCIy4bZdeIxEq
dbFf4xpMKSdlMNkB0M1pNSP/yxuy7TUc0YDCnhvdbzP0pveKnDpJ6lrPG5fSb8HdoFZ39D+YREz6
Hjeriv7NH+sbOhJdkAMe6qJkkt9wQnlMiQ6mk669rkQP4Bqh/+GZzf1EdOeCxPLBI/RAkkhwWJyJ
WtejD/zXzUrpwaPD1ibU7HMTpoJOtx2X0Zj3Pu1b345M6UkAGQn/z6U5VC7pQ+NOA7RuFuo7avzw
oJt3jy/qvrAAmXBKw2b1QDHQ7ypMTu6lOfi/fDYtSk5Um/3q92YLQKdqWvn9XemGUXpx+EoFYngY
4rR+kW5L2IzxVJd6r/qthn8YpQrq2DDtI3o5rOH3ujCK3WQWkg9xU0W1L1f8WTyay+iPFuMQCp+h
D3iZOzFUcVEzkBbAYoL9kutDa9LPg0RJLSPFYUXvgQ/RpLwkhSeXg4Teom6JCU57N+P7OooPP3Nq
3b5m+0PKFoFIZ6eSdqMcovPLn6148fpfqVKJIgPBnJfyxo1elDHvGptfEk4YL2e326nV63Ng932x
eyu6Q8qR4ktaKph+gh2Av7yjE+fEYYxU4BTTkUXD+SiE0psDhMrQAWYCRwa8sTGqloH9Z6SI4U+P
FtnpUkQMSzHu2ief0UY1nWBdazKg+cc7S3T3L5lSEuOWrrH6XOKdUzI7wLEnCRLPp11HrOFzvzL6
88E+WtYP6h+NSuesxnwk+ylEJihkIpDn+NViE2+rLnsssCSObTUsLB76mhxUsuTTifotz1/cEFkI
1Zxl5sFwTeoYlVWOmzTHmo0FLflusy5CIymYUmBzZrCkm21qRJR0LddEM/9NYblsLYNp/ZjnDgHJ
i/U/J52Dq21dKkWsxvnzRok6TscnQD0thD9BIoPcLomWvNeKmHBbCf2RCcnhqRKEY+ir71fUF6wb
Z2cT7h0FTYN6oYt2HmQt9BS65BlvHDeT5iKYHOHMyVlK3mVdtfzXk1BYmwDgSr5Kz0k9zmQuCDZ/
1usGIS6oCOA3V35LkYDKwCOY7jW6TamXOjVRXHCrFFt+mB2qV6arlo74M5qLEYJTtoFFqtCjtfH6
BO6KPzQyMwzVW7ic1R0pyMWYXFmQlDOETh1jE0gdfrp99MyRyh4/k0X9wfgOoqiXcvFcD2W/Ai3l
96OOzscdR9VyTW3aJUH5JQ/Kt8McfHuvgVWvHmxx0BRCHySQ1DDCLqcON+xbYprZnR7H+1DFdpcY
uVdV8bnGzX6rW6nuADV2qoPKeC0izya7LQGFpj+rwqxe75ck1aGoPBXZzre+Snv0nyRIKLFtM8C7
h+SgZGTYK7QlVRQ9twipCRWI5Hm6a6ejJ9UMqhMlbmzGQ2ZTHQoPCWyM/2MQbeh5L2yfFgMLQxuT
wT/lL4OWdC26dLjdP0UuzUKQ3CgmxVUvSx7BLRfy3eaI+rv+5rtuEUNx5uirs1/f5SkLf4/i47nW
0Mv/QXOLoHGuoU/n+64hTgKQ2duKQPWFhb/B5llB32rB8IZUUePCpRynnjy1Kh9OVK9D7gn3alsJ
4PrBWsPlvkrb2K9loVQqr0h/UT5kW/k6+ynGSoAaND5i4d02tXdVdsg3C8aSYuNf636xyhZ+Dpxa
7zWieSJ5jpqAA1huYJq4hz+9M8yjp6Zx1FALf/h3bNwknk4zg9yeRyjnY2vjvHwpQJJiBXYRLzr1
SgSueUU6HmrVopJsVOKZv4ObZWALwQ5cGpKNikHt9btq/QTk8AX9mmggyYdSCyiLpc9XwBLuNWVr
EvL/Yvl5vYI5wS6xvsqRk4UifHB/UJhQX2jyDO/E1C6nMZ4xow/fFariWpG7YUTbeFP44mAFh52p
1Byd0pHJ2P5kwI5Xft/QBig0z38E2zIIkcWH13DcHSYQooPAPXAP98bu9ACGD5+S+LM0qSmfyY3E
1VAOA72UH0/tmXBLEbpoD2A7V5iznY9+j2cybdE/u/gxpExguMCZ2jKQ9GmvbsYviCSCntUdj5Za
P+yo5q1tjguA09+rlEFocYzOQIKX9DeKoTjMmxL8zcLocDhJKPfB3YvcydmIbJbOhIdK5qvQ3+Dx
LaivB2wEyn3NV+nhw7O387AEs0Pxa/IBtKvkYbrtlsDhL3FETdd9g2jWKrHNnkdyp2LeKdL9FMlb
MMq1IcUX6aMWCTSItBDjQYTcCrDKOLEYN1C8+zw6mxxrgix9qwftgYTJYuyKn9Ui1Jzett6yaZ4p
Ki+NBdvyMGCjXfUh9pZhE0B72h7YJJpKRWvapNRfucsTyMqbszpaaK4sK1uNal1A7zZf5x2rhns/
qN+5N0fH21dKDXTRulny63RhPIkIdLLBcxTkGXMOwsvTNen6q8YIZ5kyA8IYYaSnjaG5lDzaZbFb
1ioeVZVnn4+EAqHwALTZQjj4FcBW52XpJiadJo66CBwyAW+MSKZOK/OhOpCvjZGqD/meLpaleKV/
h0gV/6iYBlO+VmhLMjPC3/mjGY/i5Aob9+qY9dgS5Q6uzb6oG8qYmraoB5YU1KJjGs+TOXkzrRv4
7vlvw2VXHpdDQE0/CDZw82WwwVD1jB2hFFS5BMimVoLpRNcu05BFOfdQ7RMzscc45wUa+HvqwOYb
0jXwLEaeGpXr9nTl+qNbwY6tpPe5Z9R3kkGMSXXPRw5MktpKf732VVoJXqrgR49EDAvUNxQrY2jy
3dBedW/t8/MsamYj4C2Dqzzyk1xRR1aP8TqItdF8Jl+AhuKwUoC4pUgSERGrhKx5D2Wk/C5zBYQ/
MR9UaUcEtrT10FUPSVJBuXaDDh/LHyDSkMUspx1alzeVGO/ndhh4x8wWQxt0mc+1eugzDDhFJ/hZ
ABpezHT50uA300YLIOJQTVYONKPsm60mgM5AiSj6P0frZDaeZW3JIVhh6p2IWT/GW9IFoBNjiY6S
jtslAsxCnYv6ut4IsbVa4gloFQBdr/oWhmF7z6mQD+sDTWMmECx14/jni0mkbFDLLbiu4ZdIeaAS
RiMB0SVir2qfGNp3rwwqCJFdNF/6z/NPD3rE0fZCvFdlU13neamBcQldHlQYkuchezllqrbpIwJA
fAmltG4EbvIgavqMKCrr0Bik1VjiuVKHJkSsMK6ym/GN5TJBQSK8kS6ZKODeDqd9liwsilAdr4/C
yqZ6PNax0Dex8IdPXsvvN7vhWcHSZHlToixtXPYzG5IKcg5TU0Zhzdg34wCOy5KIMBrnPHwT+Twy
NS3XlY2b2XU5P09b6rAmc4HeGEh2/+NtATIgiZj3NOIYjG425i6C640VwEP0DCG3nhqa6c8HKBEc
95P4QRZgzjKQ/ctKGgxQU6xzo7oVVxo0fIG5/lEHspbCiDUJxc3P3bcoJPXrip24WHUkq54el9p1
BvCbVxT4eJEGkVvH0IzG1bih8LimDUWvYcKo4T7dLMzDsf2cBwG60Bd7ZVmHR5FATlGF5GELq3Mz
26UGSD/yh9PH6Olmx3Ul+mHKl/5vhtvGNMcc/y39tX+6kmpSi5O1DuSxmD5LQIcCp197XxOF+1wD
Xk6miYZpKVgpwTDS7rXnbW5wb8jTpps8TdjrCw6L5eUjoFbn+uRNCIi/fgdYv2dvSuZf4zwQqxFs
uOYeN6L02WCuvRRMqLAfEG1u7VhdsLRsEwUpLNqBZINmsH43SDshd3xR1eXJgrhqe+YmlM7h1bQw
6XQiKEPWPCMbSRekn6cmGEyynUpYuJ0WryuiZxUoGGmbLpQuIcGcgwDGxtRW6wBLvlK6+d6FSXfc
DZyfb1On6fOVuZkiurIwIUEzZcmKwDyYRcIruReJwVZkpdu6DW24NOnoxMmszPy7N8vde+U7wsMv
dcCJZZ31oDRKojk+hg6eLekNg/5pRkCLJvG1397sJ9/kCKIjqJcWwaDspnpOs49i5uHljr2sQOdq
ST9rpPiI93600sO52iwtQoRwE1RisX+Jj6d9jkJH+aJuaR9vRJaP1UORqicR+p8/+V88CrfnAZUc
wqETtWWF00p3V0s+lWyNBSll78wknt73Al8tKDilF1/3skHjPqkdFBCbNWWeyz5+ABK6LCrrKTW9
/0yMFOJhHi7P8vZjiNQLJBtMYmo+iirFune7DJ7Yif6X7xPbucdAHCcj+fAaDZCXY812YeX/2hFV
zmeUHtTKAuMQzmQ9Jh0sGndUEnVzZ+jmg8yz30UEmy9lX/364HoQVFoCrOr556WL5sBdFIZ+ORZm
djP52FdPM9kmmwk/qXGmfU7iOTHsqIiFMC/RgIfA/TOP3HENsDRCgLuWgTyYCPb2/Qiewo76XNua
2f16rjG143Zx9L/42yz2gEHfIRPVYrRbuKdkqmxKn+b94VNUxN+4Rz/j3pBzFPO3GndgB5wg2AQ5
nji/q/RE/MgF98orbmLlMbc0le7J4EgdezAXrzyDibNQ/QYfljlu2PGCBnAjz08rvbw80S3eSiW+
Z1MsEjklcV1qbOYLMxEUkOqm31jBljzewPU1WxeSFassEQufv6PK9slEJ5VEk4VrmBX5KR4VHKQl
uvceMfwGCt9pnLNBD0xreIrQYWo7XX+LYiiZHQK5xBTo4+lpghywFuqv86colBBukikVUdm4wqAU
RePjxdd8WdR97oL3Mm5/qYpuehsaO+TUc2tfpKFvP3pj+Bi3wIQhObHC6m7WAutgSmN+oqhL4P1J
RX4DMUqDezuN8jhH3Fw5Bw5+WV5buEcLTcdJUv+R3mGxxtYjg9+gIL0r4XdLIMZ4VYI12BnJ5BvX
p33UgEcOxJ3+/mUZjTK+AHokJnZ2/JQ1w+5gH+2SAwwEZaY6BdGsqCkpGn6aZOFR3SwfTFgwXwRt
mcCpR8Aw1kfw5wHiucowzc2ZWUFhMCFef3MP6bOQ67s4cg6JZ/Qo41fQRftMpgguSJ3d3fBibs0G
SMlHQld2uZlGy7EXs7H8CmOMAAmsLR47mNZhMPGcHM1eXIluepZaAPD1JQmGPd7CnCzqRrLDuCsH
+TXdMv96KpTOtcRJA9TbXc4VCpUBunpy2w/HjssijgR3QT9FegYFS11+FrRnh50CMW58oJ5n8gun
XZOwqG4YfCmO3tAhNiSFmUvzWK+PJixo/8T3AH5zmWQY1jGahqUc7GNMixIOMSL2yoYY2a9jT0YE
D0B/DgavxhlqzAfD/y8AvA6Pm0HFm471+qP+Q171Q3RHfsIxCe7j9GKsdvQdKo5ErNS5aG/8IQfJ
NHqx0AsaGVfVeJQ4kOUymIA0xkYdP+S+cFmzLWcRlY1wKm5TOv1ZZem4XMLJApIZ+K309Ph4thEy
pw5TnghvE2RUB0EyUEVZQcp14e7WQKlwm3dQygEL37oHmK++VOaUyOsYqVWJXc1xKeOmBZ1et+ga
6dIxhHazm3/40PvyieD9whYb3c7k2tFmpQq/c4CafnnwYEb1QcbNwtKRNmZBUTmsFNqIlKkFYY/0
16YzTI8+5NPtns/Q9LA4WN5+ZyUryzEKeOfLI+yizPdrRaLZXxOuv8BsPLKbCtnDYa9gdcgIHTGB
PU709wfqdGVqchJRsePQTcTyvoicC+xV6gEjuDBEE/rHXpH0lBIgFxYOOjO8SIA8YpCGdnPdv2lD
QEGdeWn/0utCmQuVMRfzyr8PTg7rwtEchfjghGtsM5fr37IMPPEhV9SQz+MjPZiIP/T9sZPCjDub
QL/XEyYp9ck5oYaS6oh+mG5A6vYWpxHO4BYBW4zdGogpQkV+btFdXosXOUA8S2GpfMg8/Y7H67BQ
2xFa4oKWUIWvTM4MIOsjvqTZbtbP8CqPq8fVGJ2rHus5g1Nems2yDISHiSYOJIJETZJyBSQixDbF
7IJqDjqtrJmnOPUmJNmBv4xxpDt0MELIQa/tPiWk6xigBpAkWU9gXJI5hD45rwTowmADiDRFLi16
maMWoFoL2jBM3UCxwW4WTHMKuMgeMPLYfmmNe6N2zTOWsEWDeaj6kcWpjH9Yh6mf0zyhvZ2gAn0C
s46KlsGT2X6mSUz8iOQgLEIRpOjD6d2Iuhimql/szU5JyTgtK3dqZbEg7Nc+rK2CtkmDSL6Dhtqb
ETywY/HLQJ6DdOSrnnwmt/fRapPLaTNFMO9hGhQ3v892/l7LB8YxpE/zJ6FIS9JM/JlTSQWfgUUs
A60C/PaaFbtrDCI6Rc1qqytSbjQRjUfS3dB0JIV0WN0zdiT/yjT8eHsPpMvnjD9yt0yd9YgXZZJr
NehEmKOIZUzD3cPrcVj3cNCiqeTutvgbF3geS+y6hesFNs++RkR96e30X9CKiy/w11XT+hZnAFjB
9FDhX7zd0ywNxc7OjZPPW2EBw2M/r/+3Gue9nbiaECAheeNdMKyAXH6EsN+tnCvrCj+ag1IhslQ/
4QtpOhlabQQiSZ6DMH+M7gfJ39WfSsXyb9fC+AVRtxcRiP/QxOlu8VZaRy1m13Nh80M/kPUTucI6
NaqBzQGO4qsDMm1Emhw54x9b/plSZg4L0+VUGgT/mvRGQE4OBQgr2BX62kuWuGgZ1MG2HkW/09bl
N/9PQK7l3rtyeZp6dNt3duW5PcT63Ryd87Hm/qtLi+efWYIGMrWQzNRlViERK4uebdByfZDJX+ld
6WVgGuKO7S7bJuxMmyf6mcpwzgWC4VEajjWthg2gmJWvgZj1LMCqkIjoSaX8rLOhlx9BXykTxoYg
BWg6zoNOcYYoD70idwamEez8Q32FhkjnzLnbYt03F9KciXn0CeNtJPs5oTiEIButzE5gDInlpfvZ
19NW3hYNn6MLKz7wlEAPgzCXXf7AdYcmlm+ifzcyhJfIyRKlSYKDAL+w/0+HLCISn9uous4lKAMk
Av0PtjBQv0pyytCeOGnV2OKPtPFtw0Eig/s4qiQMZqWsULr/VR0q1YJQOspIRmBv1MeOS0k8w2fA
HRDqtFPfpNrplX5JgclmU6sEtbMlu81I61VVu7RORggZTwnK2N7X1E8uhGFLtQASfx6WotDbTl3L
71b5/lPlRW7CSONDVP2HyAuNDy2B0lUcHcTIMyJYG+kyalwVa3Dob/9kZ5htfnm+g8JGRhGCWclZ
GmEVAlgkF1spfUJgShrxUNgvBecqZs0Ol+tOB6rK+5dTMULzUlb9PPS8BTXWr825iW9pqsYh9NUX
r4/lM4cpAJA0HLUreE/OqHElullFvHu1P/Q/I0f+WoBL0kcaj38UvUhKwCd86AD3D6ReSw4ApkoP
To+SN3o72bIN/qCVNYd3KXgSluCmSugLzdKglKOX45fnCy8u6NTgOwThwDj3Ytr7SzjVZ7/b/J7l
Cy+0BpW0QsaLgb40qpayY+0nvl/j0UICvrPpjdIn2FvxU7/8rxNyim+GyaEZpHabSObxy7xfQoZa
4QyQX8FKc9bvjsz6DBCXCjoF4SYQheDHDihCeAdTXT/iMSg6u06wnEUPfRt+PjFY7GrmEqk6Xueu
HOv3cjNyaN+pmWQR6n14RcbtULLWIi4M0KciVRJq3ZTQJrOYG1jeTQniHaln4NUspan7t/MonpCG
vU6ujOwXauFXIw/y2qvQm/f11NiDzgsM9x8t+KF49fUpuvyV11sWwAOTMZjFgPGDGzvV1wIJ+wUu
nlPx6pvkVASleJ0kBqWkVGvzjvyX2giyVEDaHfOna9tZc+lWXWovgc5S0V+3XusMlV9QxkFvz6vi
NxXyA5BOOiSCjb34/fnofyrrGuqxGpX1XAVQcctMglvR+Wn7FOcHgL/77LJCexdxtVH69MrabQ2o
VOxQkT0NIsTVhs8+dTigpibK1NEw4tyExkhfSrZBjns5c8O53wcKZqiW/2VjaYL33ZP7Oyv+8P0g
hU3+tcd5+vwmkY8KexfqABLU9AvXqgN/S8Z5+RIippXBg2f8i3pzDXEvxS59lS5I1ZDYzUqSjrq+
lv2827VRkuhR+/4QGW3n17M8KaLh+4mJ5ylti2COl9DZfeYrCiX7llcxMLZ+6D/Hz3ifQlQFKZeR
CtfNRawYD6HJ0rk/cnn5jYX5v99i5xC/F+x8nD08jXZ+Xn+dQ0JKBm+6xbfv5xQCa2J92sZQSg7t
G+lQy84EedMMT9AhZXKhRAQtDBD8gIMJQyrT1W7nBq6Dbm+F09eJzOCeWK3+REShyup+v4iHl7Mi
Wa1ImY7HYcGYO5+LS1OnNA+xrR2jxvZiPwdHytMvpvAnVoooCwSgZ+raYjUy7TizsKjrrgMnUZPh
4EIBIshb2rLrBQWCOWQI38XJ+3kgZsj3qFtBZL+yBIVO5crWSCIpbU2RkfeAVEirHPGigEnku7Bh
RUEy9HT+RdE9jRnE2Ft7dcivteE16pJWmz7LmJ7SGY+MreNH+XWdu7W5BB1kH4P0WJEfew+upMkK
0+kxnSTakLZm3ihFrqD3geEJIsQi36ugQVh7fK7JPqUQ5Y8X/0TG8hRH8TvJJawky/nS5Xbmcgfo
zm6kTXjci7bCgYEW9WlI59vEEeWv/kushR75/2H+E9+s246vDqCmbnUaVBH0wDb/HqqaZ7ABPB3w
HkplmDuAHaCycV/zA9k22An5x4Vggs794shZm10g94BasrilQFoCRUqa1M42daIQXH4p8hNrEWaf
iHKtlCHWK8pLQoMn17NunjjuCGP6F4GrU5NbMF7SdnHXdow3LraXDhIjJzTQqDs/caT6QJjTaori
c2dRJNVEcZP9GxCIa1Ai/KGB7RD+S2IdsD/vf0LASnGph5JhxJbxFibtErD3TKeSREkrTmYBzYgZ
HryqeyoGxoiuOWTjF1KjCWUl8VYyuwPwVtt/2DIpkRAjSGgsYv4U6fa3lUB7ocmx2NQx8QC1hxwJ
TsCae+HP/duVBgVOCVTnJo3un2HAjYjb6YrYccWzMraci9h4McvjzutcNUg+9CKck4OjdNIcN6GY
bg5OMEp70RDQBjpAdxK5wWo/lntjFdoe2ldwBrrjxu1QNX5zy99ecX+SRHpLybIzqFB+9ut3fhzu
JYzTOrLR8DSxk102ZTJTcrQefg3WVb0WqFot/VdJcWC/aNGKA9VBvRxKtJibsfy/sHzTgpRCV4M9
dH4+sVMGjQnuy+7hrv+xy5URDH1+xy/vcHFa9zU1MnSKymFGbxgzt+n6FmgalIP3GclPq4KmJq79
JkggrR7Vo3bZU9PfWvs03YXnEGOBcNgM01hIUjw2R425c84IU49GRHFC9kb3IbxhZrYthSru9LkM
vAT9gmyqdAO2LcaXQ8v3FOy199C+Aoelxi+RGZSpRy8NNvGQBGlfGoKwS9hH8u1Nf/bARf7WYMDG
PxmnIU7csAQ4VjtFQH4RfggcPGOpbai2N8jS1LB/A/2JHRJnlgerU6LTr3oFmMEfOTmTopYCK5S0
fnBe/MeKkkNR7PwmW/FFhhmctVyI62MVytv3NsBZsx+rpfP+Sj96Drj6FIby4/ov5TTnoXxychSg
kQOQhmbnrt17/FZ6AvAif6mWng8olYVLLkffINtL/Bf5ZPh2AFzBAks20aOZBDN2uVHFEdO2mVVi
0JA9SyReBBgpo4Ae8fI+Nz2JS6RBfzhB40gK743+UqQJnesSgKzNeoeSCUfTCDSwEnDC2O0czKJD
qtInjwi2rNqSMGP16UfRm3SX3S5jLgzoeLIkjhBIK/45CQ1GSu/snV3SJu4Z2OLHv+WgDMNpYWxo
P4MYpTPNnvYYNkHOajdR1OT7WMea48tuZ/935MhX+LaKvsU1bHIFItmtHhsAEL6l6Ak5AcPiweKw
ywB9Z4U02z74PqNXGL5+9FcbIBXlp+lN6FCnn2z+tTpYnxbkwYkYsVDxCilbLAcZRmmfg4Gk/c5W
o/4ZBj2oDyQqdnWvWp0yTnT11ui51iwwy6JlUvaR4sj79XFJ2kxx1KHm0gwLcPHlHB534ezfmpXx
KFpAd9L+6i/2aWY2MLheen3xaWmxgppNUnL4UZnBhXiXYCcDpS3exlvsECYpgJCNk5AMSwaS+LL6
O/x1K0sLK37G9u81G+8gctkibDJdBmA4rZBZhjYsdfawWs+ccrQEQw2/8ihnBVwf9kIAOU2Z2Lxd
jWviJgbg7oHUrjdD3L5+vD6gu1qwDtR448E12WW1tnLvz752i765gliXxklustPxn+T8WhrsQTwp
EP62cUfE/SZ4kehX+/BfxHS0kjyKGDqKkH84E/ThxTv5w2ciCRxAeXDfEDIiEBvscInHc+7+gGud
7zkBg3qC42oxar5R8L6R4XjnajfvfZAyEitV6KmPg+OYq7oCr6pw2YTIdam78kktAjO7fI3nGvLK
iUEXVrXGmstpikq8dRNIzOKR4S91p1DWqAoObTGStXQRGlrmFsUMiAtEgpQLfLYBBSG1ZYxf5VDl
UugWud74btPdWczTwEFBMHkfBLEBm+XOuYE4+DaKkRujsczi+Gyis7UaKZnoaO5j/wScccFTV8fd
44FHac3U7cR+sFQr8sGlIqjw7AyfRRmMHOwUnOZv2VbQ1JprXqdkQmtSzPj5AHPqVzCwgjA59FIG
GBMfsFq9frlpa/zOSv3mU2+rieRtzGEAgKWLvnhdBFN4wvo2D4QbO9gmuJYBLVaSGWeq7h4bVB/d
Xcfx7Hz8DHZa/AR6fryzuyuxqLrqc6okHWDMtfUVh8Pe0J+42ljnIpItThfXV8Dt9nDN54R9MFpy
kaMNtUNpK3aCmLk9SVl2rEHE9/UGhuSF8SujeYrALwHCP40FmM2ILwFw4sw+a7hBnmiNXtqDRBeI
fdCWHU9IjF4Lw2ESZTJXaeDiR0pCjkArpEfG2+/NTuQR208Rh3guQ/Ymh+ldJwSyGHyGxPXgp90U
T+kTr3jG+Ho2D4+TE3nAv8nQj2ctKS0uqxO5f0IWHDmIlyxFCiwXrgqrboAMWk4SDdtXIM7dC9EZ
OZXM+OQlk8WRie7kEJDPueIsNpAJ5BlkdkP2c5yMc1KvZ5juDuQ2r9ZrKaSL8IzXkQ+Ws30BB93x
b8XpLVtyRMXy8CGp4g6dp1EovT307yx6kdmu4wX4wNWSdIyCtYvaotS+2X71tnB68HbyH8rfezyG
rMfdIDsaJmSr04qOd/rdgzQ3bhgAQAbcWb4uFDD7ewzDnLg3RLZnJ9sfdpM/Ihrx5mHoPAqatXJG
UCKCTcrkRZZlkrdoP/sLzOoK8qeVW22eb/wzDRAED97QNFtIi+6An5K92rdUwzFH1sNkBadCjuZ3
DcmEg0qFi0f+2tXHBvnk47wDnUe4MXO6T6vWh+tErE6cp7Zl7gYL7c9AVW6TFhyrsvOm2ck0c3/f
aqoIlXAFe1EWoOIls2GDqb3yue6oXXW7EfbOXZlU24vHz1jMn4Vap8/i67KJhJNAiTzMuM7WdGba
zYGIzV4PBn+MgBBTeBpi8bG6TawgKEp3lcMfo04JDVcdoZf/UC8ZYbN262P2X+ANpLqSiMevqcrX
MuiAdcv3OrzkpVFwwCOVZVKwxH304wmN+QIUa5IfP7bIHm+zrO4BiFhWsYUh/nSQ2WsOo9w2Ns4g
YTOQKvcH97xLV/qxr+JP10Y6hEbsrF9aYwv4BVc5DsFAg2UoxKxk2+qiMqM+Yo1+ZY7XCm41mGHV
YR8rmh3zFGteRg0fy5e3amG+tEpv3Rg/uxHOESxCzKxH3sbHTt/SDSh5zfNNANLg3xKoUEgPg65I
KR2i9+e1+991cttBxzy6l/rPKM53lSMewVON+qcdc+2t3jv4pcRorX3RwM/WD9Fxhwv3jKABm8Xl
lO/7nJ9/nxpTGEsahN8ugAQycsBh9UumT+s323F+X8DXrR/ZspwF/5Q548/zzRG4mKbMZvgIwYtU
+JEhR+bmgqf9/xKKyJgjBGVMYp3ueyeZ1kWnb2VS1sHz5m3HiPpl2oMEAul9aPmCg6P2IIWHd8KI
zY31mcPfPxZ6aqmxaxZmAaJd6YNd943j2nWsE/TpNzzXi2qDMq1My7RtjcM6qqpwt/juVouz2FNi
DDkc0Aqmr2QPxOBHqdfwe+LnsFs8DCx1le9twPAA/iNOAOZkBR9MiAJPrLwFzebsSbWz4LJI/wPq
3wgEAkOw9d9xScsmeBFRdK9Mw+p2CIb0Gqub2+yUlEEeyH4HZ6wvdwHbJBCdkwZaQK6E0m+cHgnK
HJpaF4/cggHsgE3MPnnZoCRvEhmEVAGI1xjlPwThoC6V3PhMidZqkyyuGlXX6yEBSEeX4jebdtgf
Sai/1VLR4dOMDQYrD1xuusonL8nlKcUEZmPFr/4juae1UeV3ddyIkIKcPinZ/H1Zg3h8/fJfvkYp
94lRaLaxrOLbjIEzRyiZDlstrvQFLAZYYcH+SvNC8MDR6Z56izzB7+ac9sxsHizwr7T+Pavgdmao
UEH1PCrh6x64CzOGlONCiLayKdjaQECy70ZlGn0K82h/UNhfFI/dsgfE+nPVqc8bzgADYfd8BA5d
4oMeIX25STVBkNnIo1JaBrFbq5tFzVOrgVIdm1Uq4kRyzt+rQTQuIzMwwd/efkQhMKKkfnAHfMdG
sTC7FjMz3zcPSOxNtdo2h8dp2qfHWiQ0XgqKHxq5aitoh9HeZh0J3/ZZnEzhu2cEckoVEUPl31JW
n0oeYi1aYnRfE1vIB9MSwaW+ipnkfJLNi3uZ54nr9C8tVhw50AvzVF67JDZXwTfnfBx/ZUw485TC
RQMUGEXUnn79dkUl3X8FLN3FlYnGUc72DBk26J+apkrnt3jidLn+LlrqexgGJa+tHU/tNvqql1HB
4Ca/CqeLW3+gypTuE2t1QXFQyD03URenxguvd12wB1hPHPjbE9lup3wCJMvXcNJ9wG0t092ggQiY
aUVLdzJLJNXu246XZVYBuA3shHOUkAYI5rRlJOcx5VegyY5Pb7DYoEDz7MVaTrhJPE683tekc6ZC
Ss6xKml1CsKjUaySnfP7CTWTsdq5mtkUZXRf3LxbGQSjE91d3aLW87mRJdPq33VuoDkAwc4Sq62u
l2Zf3ilwit0xhlU5PZnLYiDagr+mG3X14bygbFWgHwYiScREUbDnNMajtmp0iYvDxU9ZEjYOPE0i
r2s+wMjqwg1nEjyEnz9e1ThBbA2qfSFD/DYn4Ocpnm3mIDlT8rHRgF6FE6XQixxVYbiMrzXwO95I
4kxrvL+TlYred94/8pzU2fqVu1JAbazjZNxz0tp+bkps7W8bIqbq8U4uVabSG/SKQHmW8KruP9Nn
2R7VpImpKD6JDJboylZDX+zCLXBtFdLw1zv08Epz9XvpFr6IRq+LvwkW5MCXm1OW1PR2ba5hxiEz
MPEJLlEOmvmrgFngBhY3kDUGmKfzH1jCN3Im+Mm/l0IyU4JUVu9CIORoYZ2yWSYutrlg+qa8dZSB
Z+rkKa9bACE+g57dNi0VEQ4gdCB9QN/ODE/bm4HAaRJqiBlHsX5b14Exd7VB6xHKZqgEwfSvo8mo
MUI+e40zDGpxbUepN2cxmFVvuZ+FQKpTpAW63czKQ97NYvVbEEf57BBRSGuz9DzeW58NSrCbnuWD
Jn7zU3WHoCqmCZ54OVKO8rJZg/TNISeTlwdXIqlfI6H+xd5eE7gqK10nWEu7v73aRJcFYZpaA/1U
cdV0QQtFRn+4LeXmj+stMlXCNRqELRspraqjqOYpeCCkFqIlxIsT+xlGObZeiOHPv4dN9IIDYWoT
i8gKVySewx4gmQYlYsS/KQuSrV7xtCuirsx/XlcWBSI8bss1hkkUjch2QGukbwsRY/BHWHFNkK0r
wG8xzIqGOP2JO5/n5GbCKQmxShbBdgzzTNxBjujuUbZUy6XPUjIkVPQJLMbPBx+CmR82I07Btuf+
m2061Mo76KSH1B1SNZXn1EuHus82Oc+W6unVJQnottZ2lSEYUVo2oP6LsWWVH3t6E2qoLmSX1URU
uOD5PAB1sPs8EBL0C3IY3/e8C0VNctnYxnLIqVVpO6K0eAJrNoWuNnmxTp7cbxfGcsRuoOlsH6cm
7KfnhBLKXukA3/ICRfk/mEb8gtpNg/c9YvJspzp5kSaWGMHTOIm+Ca1O67Y+L65pE2ngywAO9zIs
PZEKQa8fRshoYqE3aqY4GKMWUnDb5YaySJjywRFeoaJOql54AaDAv7d1FVMyPEw1R7V73emyk1z3
S90d6yg7JzYlaBG8YMlKuqwtqRHvvuP4lxz+3GQxdQym4mIEWS+G7HS0I3VTPjSNuEFKMflN0dbD
/BrKaoOHaVSd2fJH0SKbJXXZWa1LbzhIBMEiy6RPU5jF7CoXyo+qDvnp/9zd43/1BRn8xQ6BYI1x
9lDXIkefYB67W7A0OVpm1OgbiU4wRM1S+NWVAetwpyIB/LnPAF/2oxWdNTepLUSsybZz7bk8iE7b
JeW6xXKXx7RCHaNwxMm08DqJZg+CTC80NuP3cJUtzPxzZMEcoL3Mg8NSFQGkRij6ZoJZzv4m5C0u
4+YCLdJmT3XBw+HqG7i6bHfKLe8RiELKdQnNoczXLdbFgkcKPupXfABbaGslXXBmeVXkmkBXNJHZ
pZyRVilhgVTZXSCG0n9u63qNM77H2JsdmPoZ2ATWdmxNymXnFncEqdrqhfeOFDSDSo50x97bYiEm
gugFBe0VeOKOVmJQQgVbDcF10GiZPZzILviNcm9coL1AwutgGXFk9gqZ73e0DRUQqBcAPkLN2OUv
RYM5L7ok2CCBT5K8Ei0S4MEYPq39dfuebqK/48/YfZhztO62vnsplVFrXNWs2pbBQMMANkBhcGKi
xVD97cSAFUL5HR7xnQq3+ymgpGCc9xWmywLQSk3ZhyvmJq3gepnHnNCslYT9KtTmx9TywvxNNR7e
iAdl+SRsjp5/zd7hpx1ZOT/6VqkAGLhQVbNoe+agH4+jnEea4128VmdWxdaEMtTKwEY13rrtcSNi
xCVepcdrhy16epzYKRmMnvWJTAhtu2zIdRJKUWF82CbV86FDgsRqpwoYQ4bgtGLR6Q+08lqW4dDZ
LQKyVLhP7t3quMRzmfeei32GxrzgzC3QzgQ1dkGxN1H1vHv3vJd/M7JWDpWK1uGdQ6YLlv5NtLwN
gqDf//he14JRWIYc2BFUf3iXBr3plU824OjSWqpckhMXWcWMKnuBvwhyri+Mghbefj/jqky+LayS
+ddLZ9wZgzhy9d06DYZ3fwNTyozKqlcH6Ilky+x8tHIeNawbx3t/Bz/GLkyKJ+qD32WI09iZ8Ns9
48jURR8petrBxEBsWOFZgt3JHvWQElRNnv/b/jEQGAy9yw7dmV1oJsramIWgcNoYZY7RaobWF86W
KIv/LC0bWcqkerPy8woh91z5ve7c4EhGLWmF/Ot5Fuozur97A1dX2Pql5xtQ/n8ksGzLrTN/e9mu
5wz2Aov1++UMp2Hu3XJ79PKpcANfdyvKKmPjX5eveXkeyzbpmL36IiS3VK6xXzClorqv71d5jUot
MqFygLSemzgHsRyWcn+MPIPHeVMk7nLCO9o0MIIrycvho8qUiK+26lPqos2rkrLIiPFOOxyiyVGV
KXuPGlS9xF43ToSmFqEW2ICe1/5+nF1hriadplP+raDf+kmbqPFoeI8SB32e57JbzOu+SojdDEa6
OzXqcWhgBh3JCfYwSCMI13l4ZnALc6B0scu0NHKmZNNQ9O8GYePZRMVaewhNQVasF0R3uUi5a6/O
F2quN/RSAIuPToEqwYYG9sMvKJQ1WeXslOGbVQoIYuh2BB7vQs+TOW3T4ov9nPvEv0OFN1ESz5jL
hrsMCiUcuDmYanPaTI1Rum6glJ6AIdxpd1o9EdssWbf/PD6zCVBlw+oPiXDM30oQhptefYnemDov
bcWq0ynpy9cwYI1XBas8I7CDU9qWOEd7WsGQ7LVvUFU32zU0D4nX01FZe/47AYtXnmvnRWP+mufd
QfZzodqF1FnxPvgZtiQ8FLrsOIUH4X/C8Xm++TcfHXpz383DKxw2H3POZnUr/Zjs8F+7+PfZ/bEb
1EJYDlW9B+szyJ3eLPDASQnCltl6p/W8yRq31iItonvi9watBtBE0M70X6hzucAYcH/I6RdI9Rvy
w5dTwGf3RBO6YmCH+SxlyfAsMz9M7KmAOR6aulbP/uq773N1/zH2oV6yBxIwuC326StbUEeSMwBY
/bp/X7oMj6nzC/EKswBpsZpFvgy2M7cD1+2+ZsTzKkfNKsmdWyBzGv7TC+U0G0Vmp/it2lbkGyFa
FJ8bcW0gd1EowQa2T36ikzoxFILgVI6a7T5E5P0s0+TkVaKj2aCP7C2BqmItC5lSH5U5sGDQXFZB
hVmNb0VJHAK5vr98MaMZoNk7A1Wa4BcRJZh3FNZxHjJnZtm0TIdkBflB0/2Otgl7Br1ens3rfAk8
ySyMt5YFvDIfsKsmVF89U0GJh+cpquCV0DUmnTUbmZlvFyjGfmk2MEPCfYwYOVXUQgXMDtZAwBdA
wpvSWlstUz9p8NGQIAOP4JT7HL/FLYJzqHColqjMwqm5jKD4yugE5aIfxhWOjDlghdi99jJR4lYC
wQ6N1Euf4rb9bfoQNH5+BRGjgf1AN2uxG9NSIKhGm0EU6ZK9IwnmqHxMjNJE2/eeFNm9dvDYEFhS
KHMBH3tgBJJkb7s5src2JlwUwIqOdZKkdz7x1LyHXbjedG5nawjMGCU3xIwPuku76Fk2xjrR7wbG
S1fB9lfHqgKCGHdRO56oyuezNiNPoOy8Qg9taGrosbwJoVb5BgDO8Fa/gNAaJFDPH1rxItL50RlS
S+B9Mwnx6Ith9Peds9pFz7RquiN4844TZwK4E4y/G51dNyIvx55jGizTbXiGP2ruWI7jVTzC3bJX
ag7ehU6j+IuQHc9YSZbLGKVAGWHafUOCCDVaDOBN/fokK1jJvTcWmuZIEDXOHTW3VFH7TAQ5UIkB
bAbTLZ4FuhNxJAPmxYqmYX+Ccnoei+HPCCC6Q3yLT9S1bOg5ry2HW9eyy0wx1/Zd30fGxPJe+65r
oer7XijW5K8nhEyKyVtEJZ5+U+42EImWQOqTNH3Aoh/T+GfwPRQX0u5kQtlSAvcwvP7f5kB/ukWe
Qf+L+0fMjxLcTmxAJSpKaG8pluVtZ7BOvvYGdiZw9ynLXtEwv60ILVIxsDMz7DQ/e++HEdJl9g3L
uZ0Ed5VT1Wr+v3I/k8duA3XoVM0D4ngwPd2CZriF0W+FxAK5zkU2SDrr5BE9c23jNTG07DjmSc0q
j75NWfnSOcx4CTorgyQ9B3wDzF6E4LY4LYUcIZvgtdp4vnOpC83BA/AmnVgYpWPHpijZ3N0b3RUK
REbk6j1DppbUVvQvPtpn/leGC96wUvQ2SqT/gWZ48Pz10rYcnbuLG9RiSScqb2GnNKLEIOnE1YzG
IMEnqjUNfiGi7XYw3Rv9+3Su8AW44Kt/llN5g6nlBoZ2wxSJYSS8csz0JK6Yh9ZEHQNLTTpYGo9z
XOJYHbWXLUEw2jc820I7HpXkKG+nItFt1sLUUOB8+lX++qzZ/Enm6jYsdTceVU9Obi3AZ4QfAErq
CLpnGgmdIvWkp9p5Ns4YRrjwLy1bQeMzhjQXLd9GPUDlhGhUXJiiE4uDxK45UFSzUc+/pErmCptu
yhWq7rSvWYhrfGDdNJRhpzFU0gsG1jSQwFCrpK8ddJlrzJo7Na5m0V1y96vVlbXtwa6Fu1QWtUv+
a/4aI1lA4izyBXTTSczO3UYYJSF8Gwx0FMtqxTWOh/CN0kgemvJDALhQK3geuHg+4967PxzI7Rm5
kU84ASsqDdmNHEb6VqB+ryXtZg9vL5tUh/4n4+4MsqzGu3KC6f0fr4fowf132YkNnfBwXBjaQmi5
/O5zr6MBL63Xvxiaurakx8Dko054EaQI5T4UE2kaYn9bGxHgPIS5qi4PnaO9Ozb20e2nQ6XeCqne
ZFp5mWe5GN1X0YXw91wAWCphEf+BAlSuk1zHh9J222VqDekiy/whwEdfi1C5XlDlx4vHn3o/ykOs
b/+qXUcYYrp67Unwqd+1rCOZHpz7OqA5x6V5ucAFvUZitSmaWKIRorKmFtKTBhX0sNf+y5X0FZ/i
2z51nKnrEqBZlD0uUOkykf63r0NdfRV8N8G/f4qR7BWTOj1YbXBg3S0ISN/h7V2RhQyG9Tgl4c4P
lrGKaJWAS2E0H7h1toVMAvo/XJtUgf49nZ3fY9mZHgbd4vkzJQbbBZBcgXSvXPr5pitslZakr8SZ
Pta67VpDY2E4q2zdceDqlh7aQtutof9PChNAGpVhzI3b0TPcb+5eIHDodGjoCaqftWDlYdqPSZfZ
KwJ5kvoHeCEVy/kTVvRnsPl/wz4O4FfGO8JAYwCnTGgoK1OGgAOKIkI7WZSUqvWy/hgcUgdv+kKY
UHBhz7VwZKQ+2QfxCJwUgud978MQmuO+jGrFqeaXZyLxprSNWoNBHa8V181pMJ0E5tHpEUb+13lv
FSHYjGjtxLF4gL4zws66WedQFrvu/4uHlzF73yfOb7pLB61K9TKQKTDs//TDn61DsoY/scSiMoQ/
ejHI8J1RHNXpa2Rakg2zIcFk+EWp/wwOetaezUtRud6z3GB6RkL3Y+tV63zpQDYpeBC+Wv9irfDk
uVJg2zsldxqRVQvrJYZuH5HwhfkQCeWKmSEVKDQXXzQDYkbP+82P8hXhvjjlKxJHIG5wCNURyMqp
6eJ+sKNxfs++8tUINPpJPYIe+hEggI5EwaS5vABquylvW06SID2A2DPyRCbfn8xmqqnYc04k7rYF
SCpMEwqNxnK+rlvLj3XNyZv+64wnjNfJ/EzMeN83ByKmuonXGMiba45DNnBliwZC6+7JpiszhDh+
Y0vWAQjpAtAZhelY1QKqCQPx0TwblBH73SuWrLJEbzcUQJlTDzprppKpDCmGACwGP7X7uN/IlPHP
ZpAEzYKzAsW83QkMRe58sKHJeEeKSLnjcactzjjmG/Dl0gM2I8y//9xLKm45RmlOHEc04DFdZbeb
Xwq+nt2swFdQbVV0E1f/SpXiawMO6/e1aydXVYVWwVEGD63RXsxxDCSsJlAawaG8GLWW2sjd6gip
/mHFoNIxZzgMiUjUPabV48n+BMdniq50/5Fp2GssQMNrXx4KAAv03VsmjMF10bgj4nthA4zEUdjX
Z/sTpAg23XpVzULPleq+dXn/a1Io13Dso1wiVS4mqZyC/egQmkZDecfENxehUZrNhj7xwBZ82g3a
J5mgDwd71ahi01Qs29PYC9tvo8XzLyuDGPaO92MBv5c0PL/AZHD9QziEYzOIwEPsgf0He8R3Ylx4
44tmlsbrwBh3ZvR3WIWfP8Lg7QtqGzQKINmIsORbK0ZeB/r/ilWOwuVmsqOJhy+9HSAwL0Hpq9p8
NoyNPYrD6CRA6TgpBArbZ37s5SZhjb8KUCfHptHm2IG77FVn8MsNHMPPzBlsjvK/+kjJs8zBojIp
v6lIF4Sf0YcAhkavG08z4fqvO17Up6xoPYf85iGnoSRRwUB+HIh/XjxLRfa/hi1ukLisSF7syskE
NHHI0lHtFRcVRvw8iRra79yFal+pXB2INjBuWsR4XM2bWvH3sVlgTcls9hsjy6jhripxd2dSkEbc
AnzbR6W7V9e/3KTy2ExZmwwXaDcnxUZV7ThYlTvs5Nw6Zl87amK6r++OE5e3y87mHcgspoRrlM3X
lVY12D8HpLqadCd3/r+rUpxaATz+eOLjkmdIDxehbtcPvJa/QqS/8U5SryDqQjiHNueyFN794hrI
Re5qWOC0+8Nl35Lj85frYS6z+6Uvzc4kPt5ewAGaxwCACtW6IZ83+nEE8pkS4G4ZcI7nG80Qwweb
MyUWUhBsxby2CaBq3GowoMzX9pGJt41Cpk+oQA5VjS/hwFkOSN0xHSIZnVAyf2U+17Wvm03eOPt6
oBHm9IZs+1Qkq4vl0kt+hM/4C5SgsRAzqzCHAU7o3kX0ME+HeuNh0P3OGOFh3y+bW2txcDxBesoU
JDHlbwB5fhO5vwWixCfDTtLvFj/yvE7aDhZK/zSloAIkTqofNt42XsUgM9dVq/fZPrUpgK8W7s7z
9wr5D/kDGesLj3PO5q3Kd8rTUyLMe7nYipbhujC3ZDqSr5lMxHBacZqjR6un3FmNIpyQDPWE5XDe
KRzzOUgQqbbv9Uby1DT0hOFK9U6wM6IjgeXLaDROeO9isoJrEMCrLtErYfpCD4xHARjguP6D8mlL
P7UP4F6Uq+tNVDcX45G0iBLRipbxm6ffKfBDa1jAtodFfg6SuZVZiGZ3+AjaDc2aPcqClOkEvjR+
nDUgQAmXVWihbJeAWE+nJ7QN0IGprqCtWd8Z7AhH1HYCohMDELR92ZnGkLzFf/tYLBTcF9gslLCs
2MOCcmk1BXaHAbLMzWFVC1YIERHZAG2s1/iTqv5kpopxb4uKet7QExQegQUH0I8Qvq1kq/6Kdzy2
KHDIN1OHEwlYxjZOG66rbYxqMCYdxmyryJAD4/cAd2dwkCAYBAfHgQHvadS0mJkccm/N1Br18wZH
7Y3+URsngQaS1aMNzl89d9EiEHZhlqsvDZnZP+PsSZzsy5lnQdk7YPtHJH21GC6GEQoQ8Wi3LaGu
TJrq1iDHxWTliWjID4U9VjQroE6DuyEYTlfLKSk4d7aG8E4CIOaH8JhKaD8Zq3fxLhHXx7raYjsX
cZ6aKLFsaemiuNUIZQ9ZvvyDGdjnAK0eW+Quyc6a1WhhGdThycC/uZKdzQYIIziX6KYK05KuY5Ea
2IWtyD+q+QhADfJAW1Hp2MdAObxNqcDddZJK0zDkNneCNMQtGScbphRHDuFudmkdXhOzT2lQcKzd
9S0bBmha9IBQ8zDYKYFjGbunVD9nXayjjNCkIcaWuZrT3nXhxQDtedpKEev+tjT5rN6egvh0jsPj
UyG5PNVLshexYdPGEvDdiegCrcxo2GQZkixFT0C4rdUmKvIuvo7pC7WndrO5cOXErmSWDzYloUtY
PxdCV26pGibn7r9aKOeG1f8SHUmLR/9SlZc2oktPBH4rNoNfVdZl8o65LAAVEND24Z6qqtxxyFv4
ZFATVMQXD1vTJx2HwOlBtLgtCRTqvh1at+t+wwoA6BVxKTH0iDuSJAGFrtQAPpcpG/RXY/14c9Pe
lp1sKWD3iiH4GbVFGkRCPO7eF6WCxn+hmohj/OnWfeCJavkglNP7TyyRWJwXGTZcnYV312He2wRs
LT9HSE7HaTleILXGyEjwGP9DUNSfsUBwBYIBAii9rbLPdv0KccwCx2v8HvmqSPpJiLoEXQwhy2WJ
bJY3PrSt545SDjw877e4qyEBUBdKyXDz+b1uMcFVdk637LLHwXfdCo712Zf6GoFZodPwmgGb4KPH
6+FiW8pDWONxlKHAZg/U5XZV1uh71lrvG8B4WxIpQdSnJ8QyZPG8bc0AubQSr9kjSqsMWPdwlGIx
YTcn2rnwg2e6Ds+1tkHum19Py+BNHn5TKerT1QG1cx8PlnTpbeM1qXWEE2nBw2/rfpbpCL28ZKn2
2ZHRMqVuWhbGGqBoBXQbJcjpR2fLCSl0tDBhEEvqO5ICW4CxD2MCnFW6x3ydIjENMv1DZQESEApt
Io/ThP/SinZaXH4HI7r9RuzZEyatZFBYttCavAP/25iF84q3ipJJRI3uASdD8dt7eiRfc6CUQiz2
ssQ/W6f+hMYPJpHOVHA64B0H1/odu5xD9YhRNtP234waQNtzBFv6zJ1qZCkDQ8lQLZKO1N9J08Au
ZEeelf9VtbFaBXm7i7S5Opn1cWylIwQRYnk1HspNMv7rSWsW7hpxS/o2df6D3UYM9fzE+ibfXrPK
lIHZ0B8T8lG881cW9pR8pE6dfKWUGJDVLogShuRuaDh3cCo3GGKRW14y2LJ/vH9F05L2ublQIe0z
iY/Fo4Akq7BZOkJ3fiT6Bn7uzeBRR2eKOWEKQbmJb5aAu7j9zf8lnmToZEyr3c1efiRwmm4U6slo
JVtGSNWsjJeLbMuE3xIyNNc5QcRwn4ozHXKlv7qrY+PhUSuyLG1FRtGcmzOFH5Eyh7hQkAp+qiT9
qIo2DouXtXDyovRwFlm1faRitVPQQUKppbQzZe/+6SlSAvQqSZ73O2XEhTCwJ6vzrVzrYaUCS8RQ
yQA3i/hJwGaAH+9k+cdN6tk1xql6QeWQVqzfw03pW5+7BuV052I7s19HSO7Iw+OZ5VOrQ3WueoPs
agIy8xY7QQ/cahOxJUm3EmKwjthc2YheAqM/cxac/IWMLzSE21yaR/Cl2UFNj49wsfWSttdlZaaN
wkBMQNcDCjMv1rrohZQcXdb04b4gYSvAaea8VHPbSbf8otYcBSwMmMrZzxadZ44hqEqg0ab/iEMy
Fmq4FKyKkOzUG2VFxY5pq/JhVXtMGpZ4enGUD0QREu8KqOFCKhrza24+RxL/xymxFwwDKZPVdPvV
AqRFbZo+UICUEMRSG1pl4qoCr982V6vtInd79Y+FzTEeCw801nNCCrr3PXfNXJxIU5X2AMuIgH09
a+mkqc2TrWsig/88VkyR9ceX4t0XoTWP763plH3yaltrBiuGwQ9kqXdnwlaSQX7z6sYkTPMLjzQZ
ot1cDhgFDYwvjk4oJyTb6U9EIKCmIyVWMoRugI44aw6eftxYPhnVvOkI0ndts9QmDRNwvkjV7tpf
Ct/6aXOuAHBxtMpJ1tVyaJOY8hHq0qnXhyiBPBDjzl4Hfxeub7n9JyrISFvNqmErJ+jgu+1mxhIm
903F2cBibNwH06ql8Vu9tHKAUuvcR5q5cDBJz4Lxny4zXqHWGEZxwraFyaXTfpyDfwWG+p842yRe
ZhkCfdToj7pSAC5laJAPLmYtU0wxzflbKauPG7P7+MXOL7OA/jzgKZahA9YV2y1FxzCYXdh7H6RA
KzbaEciCQB6A23UHIOUuJQoQkvrSGNWU7OtckZPNpLtKlsFJC6yAEiW0QW3Y8uHo8Cqd7p6MZIry
n+70heHrEKk+QKOPdIgJqrob8qfSwgdol2N1hJ/Ev0vHJRFW4Q3kJE6aQzFkF20dkaAjpt7VsyJr
ILG7jiU4AAdYrfkfKBiSqmFlFClaMxW/gfQebSo4XRXJyReF1EQFFqaO9LCzJbzojCiXse2tQnLH
2Iv4u1snVdj4RmtgFCFU5747rkYCID6OBiL41ymdCVWWZEk/fGK0Y0T2Prr2LpJ0paZLXB8gqgnD
iyaM24AO9dYkAIRhfF3FCCQhcqEhRV/Lloeqf1KKCAOecYCwF2tx+xHyXkwpGZkfTpgES1RPaGSY
MwPBCeIq2qQ69b76rNv/iPsjDgdJkesyJGTRkyLBebFXfc9TTDmiusIsy5sIlvNvrXWoqyzf7Wfy
Ig5lGqW7lpXDlL2+A6JCviAGCwCE9zJ1TqkxW+v0A/vO6WCAuql8p57qGxRY+8al5kN/GdewYLcR
Fr6iTcfsA5DLrlXvJiE2g9p94i3rrbOBRd15U5dVvFHzKNd+Dprwux/GJDyB90NqcDIwq4ytQtzH
6C0godrR6T6311l/Jvt713luFto9cfzFMdlSWSvA9MBoEH1z9+4NTPE1xj0Cyhj1y6fAcJU5r6pR
pbw4gi9r/Ipm7MEiYdRIAQg+irpq/lYEZVeL8mDePCKyZpU5oZJJvNtX1Uu3srMY1NBdllJcgKvZ
Tsoqge+KlwxbAOCOYVbugt3fkQ6Dx7CvFR8nFJZzavy/YF1u8kH68WFw7Ihd0U+o4+g1kuUaUZAQ
qY6LO0+/7r/PFPYj1AhPPGWwAR67QIpHFGcT7/Ol+1YeQ2N1VfYja9e4RwTvIG4TQSV4mfVMKkcS
Fh/QmT+tl6KdBa6xjQf+rfOOPw8Adbtv6u7IL18IJYW/T+Io8aVcMwm+JZHuO7cw/5kfr8lEHlP8
LDSXuj+2GRD45o8rtsoCMizOegsxPdBK2JofWsg3qWTXJMgxfMDVEIJp1dD42bBnyYeEGmqHlMeI
K9ZuzqG8TdZzCdxyGWskKcQRNI2I9IGPNJoPRZaov8PsATeT+rwfTn8XXkP7N1podpUEE7zH40Es
3OFEvUKDDDYCSL3udTLtt+yrgqRPhwc6K1Awy3ewB7P8rVjD3vOOcveVOQHdltGrKJtYDImBc0DW
OKVpCaGwRH2jlVmlJ1PjSdOtFyH/2pTwycanWY7gdekwQx1CGIBgOKKCJBtUfO2GBGhQDJtm6yXz
0PNweAzb81c+raLlihDSA4mtVwtMhhBYncicU3JtrnYPXlGKGrFJ1oZBCB8vf5WZBfiWLapPy3jX
6+lArSbd7bwzrVhdNXhZLZpcs2JR4m4x2x+m7gnAQ/4PFCl+0zhzk8sJ5GtJTGT+ViRtI7N1gkc2
gVQ31B1JuKuv+sChS95nXdWiRdJgfPSmf27I3yXnBELKX5Z6b8zGMnDDx5aHPtMwQfKJ0hAQ3J/p
qcTJVTLRNNbjNXGsPUn4aadcm3t/zz33cjiueMWoYV4eGD4FSvf44xC6CC5ESDQY/HGAA6OIG+1q
nvhuv5x/H8f2g2E0E2sPwyL15BvSnD0NX2QGfky+UD6KrGsZAMJKnZ7+HHj2Ol9xbjYDVAopTMgp
+dVhIgxBI56y//a5pIbcx9et9rS5Y/IGlih6AvNIJNBMefUfPmXK4Dw1QTlKvyKjLgkj/255JF6I
lfMx2fZGbAR55ewebcxTH+UwdYIEEtvuBINWVjtPj6J6GavePcHMnX2x+SKj18k5jcLgmJ3p5cu8
ELH2kHk5x9x9xwqVrLeBhpjllFYzVp/uBD6Z3wOINcQiQf92LtnKcu4ZVt7xhUivhhcQwbJkAi69
SiiBqLEuML0Z8ACrjwUndA7fRlJWvTk6QXi7xHBVuXkyBChA9fHklM9rwD5zoJckbhzoTvab3eZ6
ikojNYt2LR+7QBDO9YF0nurS8IBWNHKNUtFYWUsmn5E6AfKaXOjm7uN+MWGcya3GMn39t9sdOTb4
oVEZb96er09ul7WuX7VnmWSct8YFHP+hBkwO2V1mm9GaBh9coszmd+MRkYTL54JIvj8qPdKblUHz
KjqTEmf2qfVIiqRDkJc50zhbaEe4NegtmV6CqsfvZUsPRPOwErlcgo3/tscGvvtI8VeWtVFL5dTH
Q/MWO3hs/6fxxMRpc+aax+4NHf7gzw3Iy1cQxb4OhIYU0zcfzJT25y873VvMF8neJu0iNJ75KR2q
ukUvIkhkrRUGBXQLyB/Xl5/3fmdYfJK5EPx0XdXbSieWD77sxNP7QcGEDkR3xUZ3Q/+CDkugz+JI
wwIWUEJrSi78sRWzRKBj0+/ZZ0P6BCGI28GpmPogD+idFvKKrzrG2Hz5GQ9q8TyUmt1W6S4bSmvK
IBrDRKSYYfHB27XGlefuae268h4cxHDVTRJygtHuj+4DW6ubXC4VK/Vp9oNYsvkv8D/1YfAop1IV
XrrquQKmgunjeShh4GxWRlKs/2y6IBzn/OM8x/kr0iLw82WDHaqalzxzIJrhpVdq5JqeLuUJp1fd
8m6V32TfvJ2o3k7uLGcOY4o9N+vQ1bMvJfmB8vuMVZq1W+GvwjinoeK2XH2Zojp1+HZB484kKzCI
7G5/WNFU3j2Dt/hYGnZg8SEO9tF0iN9VrMmI+HUy6XQb1YiIfWvyxPQ5Xe6cw7FEQHjHnaPBPkvp
HFEUC8Xj4Tw01asuY6pWFv+yphRMNCR7YOCVmWUzlN3Lypcu0DZBhMitEjJbTWfafP8HEqp97LSe
EifyQMhzge1Lpli44SG7DIwtKptTSspR8YhA98JdKO0OgLCovB2k/7QuzXX+/3Ae3JDyMZHTrno3
iXvZ3G1CteosJeWhwTfPVzFBLpMxoVUCPbBwzEdSDfdKixVUzaeGemhB1OVf97AvpvOcs2IRKzXO
awFd6e7aJGXYfILZ4G1EkPuhRvaZiJzOWKP1vD4F4qV47iGGwOIycQWLqhfXQJZqdb3oDdE5eX/W
mJKPe0jDuBLpRiO+ayB0Vqzj9D5XBedX0eIG550dnKbeYyx4rACk24TE6Kn9ix8Y/PqlkxoXiWmG
opq9ZgNN09G/M8ngTBlpWbjxsTDV2qzqzCmE7T309KYfJa6tvSFbNwi/TWRKFPMPlLN9CJ33CeJc
Krufa1l4xsXSEAwAwoVwuUM7Y5Qm3BjUwrfT0hLWBADXI2CZxUen63mszvrf7FsR+Ds9AwPqyw7+
40WTavp7dgrNHamiRrBjclkPns/QbIFqTHPTfsvzTHygWkINzhGi8aJn0eD12Za3jySLSwY/T7Hw
SPVFss2TWc/TevrDvt3qP2WOH0b8U3oILRdodtKUCWhA3mvRsBhSg+nWNuN3CRrx11NWZPLz6+zd
Sq1AmMX/upntR3S6eQAo4Z+bpdFn46KCTdEAJAO2PyY+3YjqDytmrPL0Cuv1cf5RlTPy+FWvJ6v8
dYoPlIWSNQ9MnPwNJCX+2xgCfVzp3lhQ+eBVpDII8HDulJS17GgFdjpk/to6gG9dgRbvUcKNWO6Q
paSbx6KWo8hDDJJJ4sLr7rprQqtUIVZQZglna1VsG9I346iaxn9hvvrxGIR0oZvj4sper5NWtKDJ
44rnPqLioplHyymWTGoLAJ2CSO6/IOKvT+OhrjGrukldkSzKdQT9lfucQ/ZIhqgnJEIifjBDrbA5
Py+woTahJfHKHmkpQP8kvM2O85uN9QWI4kjcef+2O9T47RAQMttCcP7xsYOHEtx+1Fncc2+oSau4
kwfAwfIUXpwb97gZ6HdLSzAKJQt8K07cxGGffo+C7gVWyiR69iHcbkMQAe5TkcNWhtgI8p0gilYc
C9xl6Is9m1UsD15he9DmaVR3n6DvckvS15Chz0uR23zuCaj5QLUTa06id6equdx319Y+BC9DlwbZ
BT/P2HdZhD0QrWGzyMz3jDYSKr5hU6nXpKlmYOaN32pZ6zRjTGEhc0pNrTaC0w+qkrOZsRlNLlrU
wrchxsHFJ6FYkQqJakqqXYO2blqiQQMYpn2HgPRzrj/geZCta/JGYL2ef2frja87c1pmrt1fu0M3
DZ9pw8WYwbKQalS2ZI7A19EfHr7AwGOjHp26Fyej5nrHaXRNofA9ICWq2J09hXMUgMSTtdSTX5GQ
gosm6LBEPz9Fnx5eWafBzFw7t/FVqP5AX1FaysHSk1wVRWxtJDy8oK9HpsF9GSvrHWmq8i516kUX
PV/P+TiUHcvrIR3sK3rM41cv57eqDtwVttrq8EfICbRtkPZbCo3M2F6HhIc/GCbJmTAAhJ2UWulj
aCQlcToi2vL/kc9TQTN9fNiIOXRhtJNAMMtCJEARBtKm7Lif+g/jV6ta2Tjov4xcUr9ULNZufR4i
N17DZ9Vif+nnGnsBCViuuyfcI+ffals+Wb3MnTiTTPdIPT0IhWsMR5xV68vrpjZlI1i6TDME4rGC
XeIs1Z9ftODyl7LNIpgqEsdiowACFUHhknzxImGM8uguOR9HfVQbtHZPqgKs6wSgnEe2CDI2uK95
icTHhY1hWM6RVpzwF9ObXOswbXMeIvTvMUQkswv6vt+Uk9VVoIAiRZRVnE480Hy0BlmRmy/+VG1p
gyKrsnHkhnWQ+8XTxEswdoUhATu/nWIma4uMKATZPMXFVyFIi338BeVwHwRq5ZiwTJo0zI1AO1S9
apj/m+y8NYiAqM0XqJzn0BTPJGsrVfxhbzwspRzG/yIykIZ6WWMxpqmFXrORubjdPM2uF80asfeg
pe1/ncpRzNTxOB6WMCredtdMgxqB4S7IqPZ190M7FqwB1bMHzur4bjE8DcythhS3PY3yqbei6WpA
p+2vrIn4hx2FwuPqj0RkxSA/QIKq7zMoPnNcPj6L3wpTDaL5G3F4ew5ItD92d94dEtAlgFyIqg9E
nSnlivPU3j1QcDpj1zGisJ7VrhPXdTnA00RkWCIF/OrQKU+I+Lx7j/epcCpojQvCkLfL/yd9BbQI
mIuC1nJmlkXYRZSFDXLgl4LElscyL6gE6sWSLXUseNBZ8vumwleSrtSFJGc89bpyUcRicRvJen6Q
ZW+pdJRPVyGIdM9Veq3w91l782/Md9v4Bl14mqRLc81jKz8ey0ZpwyJdOLWcwsp/a8PA3ZSuUiYI
dB9wAHB5sbkkLkUzwBkQ0S7T224OBncO6AyXhFQFCZBvnX4CKnP1+BksAWsOSvWM6EiuV0z38Zym
KPbvvf5OIB8+DORARQ24g5DmhUhkHHQj1e4t4/dvVcZNPgAZ0Pkbvc5AxLCsikATuFsfUTgdS4Jq
Aq7uRcvHbSc7hGP70hlVA27Pp9clx2GjPjmcFqTag2YkIWgleiCF5KxvKgErGyscZ0Rw30xDs1Jd
hFI4FJYJBAgsYGhiq+G7Bs3A6jx2A6woSqT7njD5hL7z8HwseTbjN6ufiyGVYBEFgTbS418slPTa
bXKpUs0CnRPhvL8hs6WRssZK2ymd0LGWcszdJnxFKfq0iHe9qKfLdo7zUV1TrSiH1xh41USaohVx
r97Psy0sWeC4DDo+umycJpnF+WE6NNfB+Gz2aIu3U2U6uC57LFW60CtqG8hvtId9t87LZ/tP+/4a
egsWOBScA+q/8vrp3rJ7MgA3SMwCh3o2utldxoU+FeBvqdl0wxL4G9rL0fCRtdGRk1eup4VvlOp9
toUio9mZ0J2KO0W5HgUZUAwAdBQaL4PkAFGNJOx6frzQl6ESGPhr0/AnYMowtb9wLNlpRvNOce/S
tl3outDWSJJNIVWJqgKccjJksDPgclLw+dcgEmaufBJy/XyCy4ZorzXqMH7IGbuIXqzwC0aGxxal
RTvVRTpNKiIhD0tiw4AW00PBNPu9ubDOmQFsfxgU2dw9dmrWGBrgUT1uzt5ds43o4ln+M77GajbD
oxAey9wTFmArm/8YzY1F0rX/7thiqErYLCW1s+arvvXIJcGNsJC2mi++8ln155kVavzRxNdwwdBQ
6tQhe4dbrQN/qQIcfxNO79kk9rbaqrB1+fEugoHmsWrJ+JHacRkwLmbyVGnOJ5kfjJ52+ulXMQ4t
iMJ6EByfeDumI5MQN0jRCjPmnuvfcIxpNfwckhutSKnY1vh1XXtytMjFmCbt6WUPm8etlwdKLt6Z
BPlEYUMr+Sf5+Jt2LTgmm/190vTJnT2dQRfNBiGAUTzxKUvreT/yIQyfglSt9oW2M/pt6diRXLtx
R0COwr+JvgMmgkjGdae3vxAPPEKMrSVFE6yS5MSLlm+y6B74ZoY/ImOFCeQYSixXtxIpip34VHZR
xL4orYm1LTyG12+fKKSap7docfuZDtQsfnXax13KS8qul7Rids5wrwg+t4srvqh1LFduCgtH6Wg1
Vv1qMbL0OkDcQ1zzA/gx1Kf2mTDXBHUlnB1gzs7Q1zfjFn2g64LoxadM93xHJ1spmN59+DP3nNUW
IGNU9xwaANJzPfgWbufELs3/H+BNhic0WAr4Z27JdKFqlDwtBE9+f6rdk8gepxHoda4w+aqJq8ZX
tB1opovm+1mku9CxKpjHYHglhARMWLAfdkd1YH4+3J8A+mj4ZcTdYjHYh9rKaWsvzW9KNUrm9Yk9
HS+EDETagqoRFBdRmKZGU7aK7ZpC/himI0fW9VZextIeA8rrPDT5NbYRQW/puCPDCnA505Ctlg/n
3D0cn0wrGzk4MmfIG3AmIAgj3agCEKsUEXImpnatSn9JrbMtRWzqhA3wPFJZQ52ETlZC+ijaK08V
wxV/D5vatuYQFnH0GOKl943AXaFPdZfjSxYqcMcKF1bpF5FqO3ucPoLJzCmLZd1PxwSnlYlMOc8P
GFDywqMBGwupQlGrrh8RkIyRhhMzQnuE9tWNS1tQHAIkQ5CpDOngMHcBqlAHx4k4PT5f5d71BJIL
CflCnX8rY6CBRlD1p3RA9za9kjC+Y6dVUEOXhTwjzF7pqF/MiwQj01hl498VBFm5sNrWKzQl613L
p1jvueeceTITMWLz+Macw+yU8yOCYdSZVpDHhkyuEArZq1JKJ1BwOFWk+IEQ2/GzoR08dIaDlPAJ
wuQtJTWMUaoHUFw8Vh1OtiM9Q9FqK+0LnoBq3Q8D18eYkgfz2gZo95qyWI0QAkMoin0vADYbnK7C
RVFmHJILhA+NZhLQK+t9dLruprI0MG8b9MXT+I/v22YURbrHUIPV4Zw7xphhwRJu5ekV34bFZc/i
tjw2XMcl7+QWCufdayvkCCIUfy5JoFJd9mcGdDNoYHHtPs76HTyKy1VxkhjUFd9TGzxHuMieKJTZ
gD9A96UpKkWXDC+G4qcakxPYgqwqscfeFuJH9TWy6YByVgyAyM+v9MulMq8tUedcYvSJM9NWIlpB
nO6mEUnhxVoBLibA9T3Lb2+luGKhZrn5m8Hy0dK6ZVSuWmvH1okRHsNIVBC1v8g5Y+a37cBzIQsm
QlU04LvXV3x8yXrl0sNfAcGhMepX5IuF0zIZ4QL63mUWT30QzTZO8NUYKvQnGtMAqupxoNvXKJC/
QqpYzNsumNjc1LPhNiUZCNd5gJ8plEO901Dy3w7PHHF9FYsKwWJR7l4b8xZ6eRkZv9WazHRnMt6+
TaHOMBMQDV5dUAcGejoh14oHqdislWF23PxJS3nlhjUH8pOQ/YwEfdXTsuhmqn6DTZ8CU/haI7qB
wsWzVkb8ztIs5Z5XGj57+3Mew8QlYTUm7rthaVViD5kcBiTION3xrLtCu78AbJEN4gkRJywLenep
qb65PAfKfKpsqwKGbctj78n8+RRDCR9Y9ej4MzRWu0hE5XE0DXZbtW7pPNMGYfN9sbafOSp1D5z9
rMfNEPJCO5MUA+XPP4vU83RMCgAttfzzOiY8URMu7I5bvaR4vd+qllCZnK9tKXCI7IHyO7FLaQtG
5prQWZT/1fYEsAKz4SZDsf9FVTFrhyVV33S+MZygjzeSF4ZeobZKXgB492OZX2o1osDGLnsexSiL
t7X9C63vUV5E3KEp/AOIGdOlMaPrVBAa3vhp67LvuPveh2FA2+P36+uaUSjSRMWrZdQiMh3ncU/6
qKB/Io6ad50IXb55GlTUfciF5fIckmjl5ZM5c8ThmwCUgyFBBCmN79AvsVCA/FSKlZq/dCP2/mIT
/RMKyuXN5uE11VdK3yDy/IMcP5lvpo43fS9XqL6ZtPKiJeXTgcyWcNOw7v88yLurfeZPxuJ4uF+L
kZt2iyYnzGvqxl7sqD1q1mACnVH1MPHsTejyplv3dOhOf7xUiyiYeudN9YYYqIGPOtfHsDGbaIXD
7twJleBddgYZv2QSoUR9onNhbqb5P30AfybcYmG3wVTuPgAbdQPDll/2l0IjfUMsVbtXj8O8U+El
oYVnp6T6bkXjB7dniy4R1oVXl+mnmtvaTX6diLuhRmtGB7M2QmH+fuFRLrTX6s5wGan26libdu4n
bdi2isXxgYbSgoKY76GPT22QIoeWyHGpFP/OTkmQKAIZ6plgAPZetAt1h3IZJkfqNRJn2GPCkr7U
+v/ReAmFlTWE4boTwUnJXvWJthb6HHIShlIGu85s9k2A90/0hUo9k7ANGevkBx9KxKIbjXk6KdgM
NSsprpme2gtTa6kEajfMcthdye9ZOed+OIfs8PM2xiec0hB13oAEF1NQTDtzcXfTRlUHuG489mnm
DmsMjsD8Xl+1AaGEsnWgK/XYQDHBvklSb4DAUr69/qeiwL24lYxL+CD490lbqLGpXlCrHJOWd5r0
eDSSm1lCNljvRlfS6XV13v/Qn0QlKFpoan/rm5Sa7qMSiPl7072vHVQFyrU9gyDHcyzRNLKl3bEM
+/0aL6RGV0in34Un/KzqRCSKBUZBVOdUdr7965hOohsk+ojOCr5J9g8CQNDOCi7q1Hbh7vkvq3w7
pNcw2RSP4UkQ3ju1FP0V349iy51AMYkmjppzu9uymiN0zk8Kw75kS2BAr8qiYv9uBbDlrOSl90Y6
MPOz4E9DGf0IaFlEsHs5N9NRniDUb05mUPgtpHjph8bIUgFxrIChS6R1dTI0AQybOhn1bFX89vY8
KD3mJh/vp1ubXbLbKJjK87ZWENvsnzR+9VzQxEVoeDDhwy/0nj36MxOuEDsrWlJ48TpGDHOAmksU
q9E02+iU5dG4zKi5Yf1LCbTxeVSub2G0lLCJ3XNjy2DJeJZADN8Gx9XPLXUgrswCLXV+p+ja48/T
VRFvObenCRH5M4EBs6wCuKLkTd/MxzzkXXy3DUBkDy2hp239GvyC9Hx1jNXuz1X9sTTy9bLbVynp
UjzWKPMzf+4kZwJuhHmLClFvMfCd+Bk9S2qv5V4LZlAvcPUkc+aGVjSJPjemYtWlUUyqA6nLtYTH
1hVawH64+6MqOwnNwa84S2JnOXnE65mtdE2Jd7HGwm7JUNLH7oTOjeLu43A2nQMIZCoyGXwB/itL
sRoMku8GwLv8Glegdd7UpFCUmDhTNxKQKoaPCv0Pgy4E2BrYqiCIIKm0ku/O/Go+bW28086bXP7x
qIQuJxx941vN/SsLwokvkOaThKRH7lSnO0RnJyQGeuorDSv+d8nCQ3DUo6WCqg+1qB0qgW01w8xP
85JmfU2eZMFYJu6AqI/iXccMA+ZdiDwX+UVGnhP5kaGkj+jvJ3KujMlrSFzGMCPHDDmCdSmMMAJR
sBKD7Cc9cq+f2AFnkLc7ZSgI4FawJJ0QizSIigy2wWEUqBCZmeCaVpeDTjbYjk1/zOZ3C4TuXiP8
Vm5Kc5/+t1hO52+60Tr4/gsifnB4+4DZs2cxsxEMBA8LB0yiW44hz6LvGkvrQ4tYBzT5p3z0ka+U
KddFwkpdIayfsQXExwSTOxam4FjoeCEgn3sYzUm2/wn2zOLTPXmzS3He/mAkmaQKMzxR7qDo6za/
WitBqcJZ7BRxahnH0CmIfvtXdnVIHLVqKCctDlpr9VtSYP2eWGYY8FXnjPVhFjniaGhWbbcc2Du5
IhDMwOWGtcrq03DlFxe5EOo7Cqpo1RDHQ+quY6dsQJIgUhoBhewjxEZtWdKrVL1vhJ7S6Apf7dps
hMnvSYO3fdPQVYHeYRyiLHQrDxpwRTpkpc7Sn/GqM0S6aoqkOFJGW+HPJVs7f4vXR5twz5PLXly2
CbnkhGo87JE9jlpzqHng9q108nHfMqx8ge0s/iELvQ0JeGgldFZyXZwiYIuI7CgQ8B6YPXGi01In
AE6ljMuF48Ff6u9hf2F4u3PZruSBDe/Kf85iwPi5EQYVr/N/441fl/oW4CEZ7FNBSSba3cvTXV/V
MKt8ujsbykcnLFB29d26qmfqmT+7GfhO3wiWMef25y6z14K1YYougJPv+HP2CcwSkmPspYCP22a+
pBJFYcD6pSpE1VpvjDrtaBGaeiraugoYiVCVb79RMOGbjXgoSz47qGAsxWf4nVXMnx7UUPfICF+1
FAI0qQiZWCiVqQMkeXxl8EUvFyBDBteKytiEanZ7NdmOlXlh9uLdJ7jKKDE/y7Guf03ISiBsPcPO
X1rt/Ys1UvnAABVFq/iYW87yuBefqF52EjGrof1VP3S1pDDmP9X8M6YqOJ/TVmL0N/T74yYBbtH/
0j8r5j61tpyyWeHu8UpOWqN5yhVG4jIekpFbPt2ayYsmb3GCU4nplKtjWzpZ0opZPaVrQbni02pR
MD0S4UdsbSHTeTUDEA9ojok5wGgwtYWMxGwyBkHvrZGpXB+MH5CYQgj+7ebWW4wm2aEVyIHXvZcS
L5yO9p/cZmbNLxfEIpc8etdra6ZK5tdQOrGEkQezH9Nsx/sfUe+uwxzOZYBjd5CoFjuww2t5FeND
H9Lo0RQBkkfPJFCfoN+oJE/w13XCS0O0zEb1ued2o14c8+KSnBAZTdvK91FG/Efrop9WNsvJtKUE
WtT14+h5cHzyk+B18COXFKUZy8Ly3Q1GDpyOlhfCvEcLC8pTpvU/sH/eRZKEpzHUJsG0sYLcMm4p
JbteBsPRIilybQfZVktbKkdYWrV9knxWKPEeGKlULTfrw8VdCpLzXq/xhk2Let4ADTBpdPuupWmm
6G9lEqmkn81aj14B1YMjtxmpGCjEr4H+QqEUL2E2bVURa+KmVNjxj9+tzjl6ZVGum1OmBrGdBfs7
EAPLebAVyiEBFWW/Uh6LGGfaoI9JNjk0x9WTeLlDXdph5Q+K5y4zdov/obPmT5tnIycgINOTeosH
SJGYKKxPGJRkMqBCm1gXgrMUcTqKojJYmg0INoqAq/MaVcy/+d3LLufMoYQSeN5TCWoe/XmmBbkg
AWZF2cjWk/bEobM2hvfQoLdx6YqKIqfUhe4zs4Vsep2azEYKG7khy31YIZMPDDpoiOtnzH0WvO6n
xmG5mxKGT97P2IvkYwP534aZU3SRboUvUB4ptHEzFduastFZNzXEzsQ9/mLL3nBLQiAZ5qnD+xCB
lhinCH8qw6xayYmxG3+gOAJvWgvuV++PsmmNKenkFFTRsAWFMJGpIIYuxZhDRSC0K3xXSSnXV4zG
8GrMZ+HbJB1HAeS/Us56S3be6cutIWw5vEVTT1ReJitg3xtsHa6RMLbtJOrLlejzW5V4QcBIOEFq
jtpAIT3kR5AgJm0A9W9+DwX4b3JJWkRFpcNlQ/0Ty2XUnGXIIJv2kH5KtqbMmYQ2AB4rZ30syFhK
+09L/NdsCTzrM0Kmm0Vc0BSLtCfKO1GQNEjhTHYTixA3yFlMDctDSNIu8z8z7sybPFQEhetEEHw+
hSlWQHGcEBOSPUYzCzHmrS05lgEx5GVgABPVvSUngHVQRl3KhqmbUXAYvOZTN0sqoR+SPytaazFM
ceRbz+qBLYiYW1EKHJ4VChxOgDq+Q3/QMpWMCSQnFzCWVSva0om2g+NOx3mQYNLttpVKhnh1ln8j
FLVuU1uU7u6Uc9UOrrf/vzXpCsf8f5I75bVyQi2Dizr9lr7UO54ssoYPLK4kw9iiamnseolzzWXX
efL9yhguFB4C1vT50jpQGSF5dUQczB5SjquWtl/LjApza/YQSaQwAAyrdpXriH0Hhoc2FTs1n3Nk
JI+ek7e+RxzqUQ/AkJsCV0Zuh7tJSHlufiaQWXfXnPSdYjJmwO6SbF/gOY4vWK012i8UR5SSYQRc
id5uJx6/O+GVnkmKMWidKDc+4nBHexfoXfuXLWWDrqtTKUEEmuna+FUHLh752PM/SslE9RqFSnYs
qFmneDe4ksCuiuifwrpx0pfq/pzqQqidwCK8y66CnaigXcf16GtLo8IFUCH4CsrMatxvdq5oAEsH
5c/opQlgEA6VyNd5CkgiXoJrH9w74UyUUPBDTAQSxdjo9aPtTvO02rK1D1GnJvNQACikI+qlkF/d
RJG8HSDHj/ILtsnAeIuUR0gzIhrQ2afoP6xNdvrj/BQNZL8qKQS7Tg5RClLwgMTk516vKxbLCFnE
ScYDeKbn19HaXhP2N0f+SOTifw5JGfI6ou0yZYTgNrD0ORIEN1hAvC57oO3p2UKsXHq3ITQcBveS
vUE2qYNGcZVm8t6RLyS02DdobfG7w6yaRs0s5//q3EyMbuBTwHmwx1XzRu6Pvl2LIv75kHlDNi+E
KxTD2sdT0hPEdKjMmdmpDswJkyZ0hYAvoF9cB/xeqtazpW3cXjopLEbo8fvz2apBnRxsUODHOorP
wg9GpUrnALFwbMOvI0XQUzLD8N3zwdmHKncDUCicYiVr433ALxHMIdgj4mNMtUyey+XYmFIPwav0
NGv8fqLrvXkNwIesh05TUF/bN/U/AJon2o3xH02CRU3Du9KhXdq+lpW/1Vg0fieIgcP0piPueWdp
d8MuIwpDwTGbq9vkrSc67QX0CL4W9yt3/ERmrQbM5NNfEr5kT019g6Q++eDSs3jQjBDcTYJWKXVS
k/xq09ckg3UcIzCAShB/7TiU/ou03TSS4qXSfRCGUHbPT7eKD/BdwJNcaNeKXRX+014GskGBgIJ+
bC3AIbxRGM7y7aEENcvBlf6SM9v656M5WwtBL8wFmbd0KnBvaOyj72++czbfFhL2FDdy2rvkXbr7
jdjOIiSU9Affwd+7qn4Qp5mstQJSbQNcrMY5d4f14HyYTAm3RmuZJasrWIYNXwtniEYYfRXCAYNO
0oOfjHSNW+NMO4DSHYWw1XZkluUps/bZEr3Z0ZGJ7e5K2xJWshHondoLvWIab4uJGV5a0D2OUf4W
pKpgFseig9DvfAqQnoqw9e1WE4jxIS+rUnQjBkZO36fOvlToaSY9tHG3kqERCcEvSW7ZcsFa2IsA
PvEYYKn8+i+qDQF9WaSRabfaAdmLoJUQE+l8rt1Hy9pte594DN/WRVQZjKqJ/UsDvW5vqUrdKEqB
wgQlUfmfrhdlEwUC3+KPgTHFxptlpsRF4PdsuHvx+tc3KWB7yzpmqVkwHmtdCggHL74Ars1yaBa8
DYqJxGdzWZqfDaPC3hmoAS6SX72F5uQyvR9RRdtoaN5usIc/ViSyJH8f/Iz6Jm/EgK6GKbGZhmAq
YzAXd4aZ+/H5eor7PeqpOZXI9sSM8SdVX243LCHh0tP55QEGxY6ri4GjU3AHC+zQjo+XhbbNzy0W
9xNyhQhjPUB7i9X+Nv7jjV2m0F9P4/lWkiMyNnnvH7kpTcRKXwK0Fahsv7yfk04s4/7KgrHvAI2v
lryHhL50eM094REl1dNK83np2u9Ddd2OVM10w8ZcEzVOtYELmw/tFpzAiM7QfoaA4vWwrc+tYwES
IwuV4jySoSCCR76b1qVa9YMdHDN1hLsnUYZqKsq54MSHHg7jvf1Youunrbbs6Xoii3ooDW1CbDI/
n4mauZnaq3CX6chnDKnSKtA5+o9FtgFB7dISaBRu/1nCnKpxsiXuyAoVc9fFNcxSFqcaj6INfR6r
46kere7+ik/kZzWg3hVP/uWynMnDT5YxqRqp9UNAAEpxWvKJssbacsk9Z/cR7F1uD7yCP5sbMuOf
w71six0ayJkbeTvmaLp1FgK09sKsxEY81MtXw5gYMZcfGliHN0ozdci2MOhxGDb2OGpeQqFJOzna
ZOhQRVbraW0YUbwPMweBBdf45ljRKfMqNygHKgh4Am/E72tmdT3B5sddjfAg6LzCrTE+6Pv3P1Dr
xDzV/JB/5YGcA/VMh/OG5S9PYkqwcIQPH5pw764DGGw7SVM6wri3hJs2pYuD5HYQ6rCYpuJjeE9V
E0EdgKK+8ExwU3SqlhCWZC/ABtEK513msgWcgimOqvMzMPIOzSf0gTClckq1yAbmajij9z7XWDG9
yq0TDWRhJrFYgV+ULZlunXhSDyHjLSsIi6rXe451vaF/HGzh30bHbypPwJO+LgPnMMc7DrkQ2THK
aOldSwUN0imL2vH/UsCJ54owW4Zjq29tQ1M9IbUL+nWjiUjLSB+a1OFxJAckXe9qRnNEcz1zCTUP
zPfCYUh3eKenZwrztbwjrpadQAt3LxyZNqIRuRAeUDQbu1lvwxdYb21Ot/4dF3+gL06ODJpz2pgM
ag/JzmRksQtZGQ27HDiU72ONSLEcgBnQ7Fjk24kE4lzIFAhiVW3Lzf3yzWnj8/yRI0i8pn9Tbnun
MolRFzgextojmQgrsa6RoA/mo0T4STd8hwyQxkG3nAobr5wrfxWIef8cftKjM0QuvYwy7ZEeDdA2
lGh9NjvYTBhCg7vivDWSwNqCg2JdvQ4rfPQIgxAYCOrSN5KXjrsu5Zgjpe37sVfQF5jc08CV2xZr
L0dkCPpVrgBmXSLtrQNHgU4+I/rmvXzsRdRYBThyGl3vSg/EgByH9/ly3SRzpPOIatd/pUhV3N48
ip/VsDKkKa7S6/s+VVcNt08ON6aDYCVpK7jhsCoodG38EpuH9n0EI/L4YtiWkV1wXctKc9YqR3zH
yjY0hlch20o0YvLK1bO5TLE/zkKutBvvZHnl3InAaIMGf5u2IkE07uwoL7Jc7RyDvbNTSA9aYofy
2pjPYCnf+4nkLjLAveqVa0Lvjh8u2Y8DtLDVF6vsnEf1OCRkOlgT1/2BaFl2ljfVHFOAdLR4iOTZ
UoEE+fR2gOPhOWxoAcnnzC29x1NFuwnpzdt2Ff+V1LNIBsiK1myLhTJyU/fAAaL/66Omz1Q6WLWD
VlH0CMwOpSpdMzPvZ+qeyArDslKXSe2fYZnOhwK3YH7dI7BSP233NDnwrQ0Kh+2vYOoqhFc5GAri
vZxKUAo76C6XPai9f2svWQs0Rug3xZSqCguLFmKJ4Fo/Ckntg6jT2bw1S83PV9eDkk7AkncwV/ms
YZHIfpd3dqdH15iwBUCbeZcnYLW3rIsE5+FLrEcai5kkl0XOeJCyh3qmPul7x8ORbC96RgEIicMf
scS/4qvMeX+JjUTmbkfqhoEFH18UU/LYaYpMuDDgxAKjs+M0uWQz+6J/fFqdcXNyZQ4dOUxVG6UP
31XB7u2l2K5H+ZoeBN30gEMZERSQBxQyUmUkZRFBHyevxbpvclZp9bYDsRZBDCcL9u60stb9KHEv
MfOnFz7Vxzeriq0iU2hziUUmLWvASQw5XoJQqXhajHm7uS9XICLKQp9t60a2NqCA+SdTOOZLfqH1
7ULMJdiOZOBeYb94vE0ICWNJoCVZI4JxoKsoJDEN66yctwDmRt1vkyRurBnV1N5STHZJJ/rUDwpI
whRmaRe26VUxI4O+ac/aanDAbwXTA28jr2gpcFQRAEP+3i/URfIxixSsFv/IBal7VMCTOijHjqGq
etIH4Dd0CCCR6viKU2Q6hqWfVL+Z6ClYcIuZZPLetOzROeaiEGfzQA39kattVVlhmbKTrctN0NC8
pJwQl8hY+UYki53dtOApQgn6ZRmqCdHkRI/8xmlcztT6Pd9t0TQnlfPOYtxvnbe6qCvsVfQzlncY
UwQ7Gk4r49V+b+cSCI8grBySAAOBkiupAZw9MMEDcnFk4Qlkma0XbnfxpeZqbABPhk3pGdXrkswG
EXcswTSdXMiWUm3IELUFYITwMJp8k3lPzZ/q8aQu67d4dgX0UxYhISZz95kAiqpX2jxwsVl78iuO
jDVBo+SHWX+It5qFiCa5VaGp2vn9mC6wPfYCXWOan9BHQuhJBdhPowkGlP53X/nP4YrMQvtbiRks
PKsz6YvpLgpcZrL5nPmDtEPiUqQG4l5b9TQb9H6DeS/QrYKo0ix/+IOSZIE+6az+9aQF8Y2nhmQ2
xgq5wbmrvz5VtbyPgiZroomz7V0dtlWjLFckGwvqulLVOkwsVSlVm1g68lMFMYrm20fizQUuXpbw
ArjmQVYHc3KXxJPWJdMZYLF6ANIxZTJvtH36AKVPeDcNE1P+PHbYFJK1YqFsqhqJFvg9/XAVvRpo
/Suhh5hNi9ZgprFYLWabwcp5KV93JzC3gDa7sB3XWi0afOc9S1k4we7lE3gnZhCSp72GWUvdZ/tp
G5cIhUHdbb8oh+uq58ieOv6hGiB+Ljoly9xm9kO7AqO975xbuChr2vCIkRG8Wa2cvd14A9P3hAeU
9R+wrvq6oewn6vxEirf+MdK56BoHaeMbo0K00CNUutU9LH9xxnw4gyI7ev//xSqCvJNUlW8CoVpS
lcJ0AJDIsdL8VEbRaZlySwRJ17nBmUXkQeXd1w53WNMSw3rb6oLI7OOt+fAaRNDw8C9LUoPRe+WZ
c/B2vNFXIXgItwJdVber+FEn3qjgKtiLFayq8T4s2l5Yno7RvtCAW7pq0CckpQzrpHHy78bAm//l
t6hCzTMcGSZV2ZYHmmL/GU4CxWEGeKfyl7BnP/4u2n8n51oHodsQ+QetayO4PmvVsjKUyuv+Ll7f
STk0IgTCHzQElXekwnnAIrIbZqOdvpVm6nWgzlPGxNt729aCG4nYzqhfSa5N8Bk2iKgb8jHMV7jg
nmgSlfDTC+tZ6onszpi0zgb54qUEZ5C4ViQjUwhSyob+ZFpnOsxU9rstGPI62FBf2XB+yby+zSIT
LyGd38wKGq9Wsh9QVFOusJSRliICmJdI3+BPRMHCPSanZkMk5ZuNdMXHiFTMEbVdeBu6NEfGb230
NT8Ysj0RvNlKTmSkFmZEpELVE9a0uvBn08oy0Uj+iMq49JrDmCL8i/q58uo3QxMpJu2dYHqZ3G7/
umip/syShPO3nl0Bd1wG1jINSmif89joNuxv1Uby4rWuTY7hZHSn6lSXC5ICpApGdd4Vb/eJ9vfi
jvP+Hky+JOwmax8sMVvCzSYhJPeecArA1xCVWzY2Oo1Vgc/MvsvSGezTljCOzvFkm807NJL8Eh0y
lZ0ZRa7QriFt8kw4g0IzKI/EBP2UBlCq8OCOrcWdsYF4Z2DjZ18Xoa3WYaMrKfMHaPWM9u221W4s
WUOs4GTmpN50UNAF7R1sgYX+MMNyBJ1uQi5zXoY+u/rkaqNAjXOtHzat7dh9AcV7P15E1pnxcy4V
w12Rt7PwvZlOecq+6DwuBjukxxGFjuCjQU9gbes/NwZyTwARNIRaj9iQcVbpWPDZPESkpuvWOZac
hC/ME1m1hxmRRJ7iyqF8GPtGOyy8HLS0+ooDbJbdi/6ToQDPOK19xUeY9svWjkx0T6QwBLWIlouO
kd0AMZlckFVtWgtPSMqhwWkA69SD6WLEW7RQDnirBXHXm01maxYvBaTyeCeAJoA0UFOxvkSj1kq4
Sa6ydDclZzIz7UL+9XzBdVYo3Um1Uv25LncIomL5bI762zDBaUBkKCAJhPjcWDxRibhg4h0g9gH+
RbGSZ68+AkJJd7pcFi2oG9KTnQn16ypqkjOhx9b11l5xRGrYKoh8UyCwseEyyUHsZfx2pM7+w+5u
KowQjY+7MEKf//tafHLK+JW3DZZbx+6nISPht/IoPAORjK8/5zyMen8fkKj4Zzjtk1xglZcMLUfF
+KlBZjek4rULrQTgoDBTZF3XJ8bFJX27/wjlPObX5DrVMGt+x+TFkNjMbRcjKGK07vn/LftfUXxV
PCWXwFTFP1+AywKAqFThpipqvLprRCv5Wn7P77/Kg7wCpO/+H0+AC9I30RefeqZb76RbY2VfWieO
6kdvSeOF2QyPWTupaM2//F7xU6WUNkVwvORBDzJFZArj06h18h/oiAxWd3pm8DiPmg5vPcm5CbR/
NqIEclzedqYFeBvVQDBGR5NCAgLrPHlyuVmKTf7rueWt/n6kzOoxme9TriOG3PDeWo5Woy+QnzwL
rhaR51AlpiKtBQr1OtQjF+SwCbzeanoftbb99J1oe/ERKhmym07Funj84BXMRfDUe6eIJUOf4QZM
dcI68NNVVOyawsDmCEdBxSLNBxzn1OeTg7eJHuMCLfE66ys711k7u50ekJk2iA3pgvt6lN/p7Xht
kosvU4/71aI6CODY63NycKqqYzwFMhUxYtl7qjyL2hYbc8KdYI9OhU06OrUvBpfvX5zEThriFCEy
mcarCzPW6EvMu36bqNxiWVvtw6l2vXJiAmNaxYC6G739QJtVZK2n6AAeFyLHK3InrRJpJIDqUaE9
VlwSvnldRkhv1DioS7pgEMsbT7i5vxa3A+A6b7f3AnNb3IXxYwKO/BEH0Wod9S9oJtlYcMxQj08Q
kepfnbVex7eVulNnj3Mj9FEHwQ3CVgDllL8c1nQUBhwV9uphg+zsg+UHyDoeBZxjXHnoI0BZUkB9
p9Igm9o+GQX0MsbqXp/HRqxy5wgjBpntbGXNDXV9hASFhh7nKW1XWl/S0WGuKhEFB6/w3uwanL31
9NbldS1zc1gIRBuvX/fM+5oCuJJkDGfwDJEmM7Y7ajHA+IWvbhPF9tlW/YFTCwh5r60b+ePZ1V8N
FmF7U2dNIPYG3oAJLo/F071a4DXTCkNAox1rnSyt7Pnjoi/+a9jz0+OvE1xryfCj7ZaASqafXJkJ
YfJl9mCHuMllG2BdzgRHOHu4CQtqOiLdU+TJvAhY0lbGpWVJsOeTR97PlCEFGkBqBWRaxB4yn3Dq
SvYbZDOc8+h9wN3Zdu+BKCpf54WJxB4EwJo2R97a8IcZtg4X+YpSRbo+AToL9JhTzRpX2tZPMt/+
A+jkmFzPMrO4uDkAtA+Thsm/6Tb6bh6CYLHvec5nppS7zmC9c8pHXNdbWeJgUhFdiXH/yNSYAkWY
F+MQeVzEs0QgOyBvHIKnJHM+y3/tegbk1q/SuJ+NWA0Lyqrzzkc0+v71AkbBJAny5tAAW/H/d/Pq
b53L7U253JBE5Oyr4QQzNzBaOtn11YMYGwJ+WBJJNfmfgJ3c11NE0t+O2+TT53dIU//VnheRY3wP
BASeR8dxhPa58y0ttTQRKl83+anrLFHXkmgTQg76ZicOLEaPdbi+VsoaB1chNCCvUXRtI3TAGoBz
RYIyUHfId+q2Fhayex0hPWPpJKALD2qcM5HdW5dwnVVqkRwvkeSjj0qmtdtfJ8mxOlsDzZsZRDts
mlzKTTTV6PONfbKBhMW04cv+3lLVXQzMCG435TQwiT/GXdI4ml1Izn48Ws0JtKRQiXVEg97wStcJ
pvtdpyAj3GAr20+yoi4u4DgWUrP01EUZIyExyOI8auIU8JXur/4sIvwKMoMNKO1xJ3O5t8QZZkb4
OY2TvaZCuNKIclDPgIB3ljNyTPEeMjZuR3OuE3SJhS/Nb35tE2Ouc4P9DfuEWZYOmVEhqi2/kARE
97l9z5iz2SlWz7iCS84jnprWs8buSB56Zdogrt6mD2SnGPv7NyQCXEYd1Eg7zzCtrR03GiwN4HBC
kBDZBDhUteAtCPHtRjWJb34lK/JaE60F5+4VLMckmAc/cQNMKYnCo1waqZQYf41ef4jcOgLpaOvA
vybyEhcjeiDpCwz+s2ZFmRqjLKHo9msuj0NenopuJDn0d5icqsFP0xyeeNJeRJqXsFYr536UEI3k
chhld6DIyxPmoPLvhAa92nags2W0W9Ek6tG6gcUmQCb/Kgtu1Sa+NG2spIXe2nwatI45uJdEcH/w
vIFaxSRgWhosSYtGfsZKSmhDJXw5upW2MelsGBh7dNpJQa5s8SZc1vFy/Z1elateIH0mhlkBUOPG
q4ZcFuGLNX29p1sO8b48xkxjgD6V6qmNzjsuaAW3UDL9xD9wh3cCgvZE+JXetEXFByeSqrmgI5bD
F08vPuuKx9mwT6Zj8wTUadf1yFImcJPyZ1Z+z2dox+ux6ys+4B6ntzfhpw2yrpp/OZMsQunoW36s
kfYjqVhSHBunPkEsGH88iKEfjSZG5OKz2MPiIfMHA7XA6hViJOeQwWPrYQZCxCzUqObIKd0+FkZM
q6gaIgbjCqRilwNinwYMOwKZfW2L9wum3QLbyFpGfAo6kKfREp5yiMojioZcDcVBITWuAqw/5Syf
vP2so3RjmjUerEUKzFE6L/c1Z/JFPP6BF7PFaTAS8i9JlhLrFcwWNatw13RwSohIJHuloHBTQgBJ
UqNY3YfuSNzh8jYYqbDL95gkH8RcBqWiQZtBAEGG6PiuXO8SWZtn9pCDv9bb6A/9/tJ+UhjPuKqC
Bgk7WPjUNiAuHEQMc/DdMXrBdxx/YgYDPgTx979aKI+RTb433TT5vwMflmveaMJO/zDaNNVu+ob7
BrvzlpQI3iQoXbLfahg4rnar13QT34tyGTsufwaRfHy0I0FrSh4oNKOmvDRvhwiRZre0painC44T
hTSTKRVU7BOTnjddPatRe/lPc2N1jIZgsRzdDgeJag8HnwCJArIa6RzGi1JmsU5jX/6DSEJtEIJW
n8VTrbMwV6DkZBprPbUkv9XQypdwUMUZ9VSDPvsF0r+DtxSi8sXEMPlUmXLgQdwvE0RfK68DuuaD
weM06MaxmsyVG07XC8OcQOwODuXzle0IiMBnDQ/QwYnR8IZ4OrkLWIWq4Og9axohefpYfB8sq+NP
vjv9P7zBuYvLP2IMs56s3Sk3BwdwY6813/4Yj7jvEPXjgcI421x9dlisgoG7z13kDbpeom/S32s6
M9mi2bAGRwScC3IQSovw7BsVumuIG/rbDXKfOUjjzWCO7lAANjUVvlysd95y4VclbP+BfXjZHFRm
SiOX9THsdbJ1zOO/KElP6+w6OMxvYrhmYSXCB2p9aVhc7wjhMolI1WOhkldLDZ2do3sj2yk9VGXG
uXAhvPV8PGVZiCrgVs21sd6LwKO7t4srIoTj08QTcwi99yA70t5WBS2lEMO+r2v+E05U0pf3Aek0
xoxt3gG0IT+lDqDZ5vwikTrOO1gC365bGyu37lmMv9xDLO63TwTPAfQErdVQxaApOjo2LuOPQ8bu
kMuqYGrjCASHAgR1FCxrcFDiE7RfmKZ0ApAEWcN3ATKqWGIHcl1BSqJ5oAtkRlotAKflTpGzw5I/
8Edzc+y9BZFanNrmQGqPCkdAJ4xV62JCicDeIRayjB4jB1LS2hHcC6dqNBYumHqRHmT5u2Mj9p/v
gMp3Jey1qX5Zwcm8LBE0UraUygk6oKKEfww8Eh/cNFCr9VARCm04ZzCb4eJno9D2Yt9MFkBpKvsL
032BwZNg2HY5u+iLYGTeWcmc7sdW/zETi5WE1JBg2pAwgucmOAXazGkpCQT1IdE9GR81iCdywjaB
KWKidCGBmmdIj8yWMviqugL5Mz8JbamoywOs7q/86oT73S5g8JX1TpTM84hRNZniIWUkKVYIOhIR
+9yp3yOUa4HEJoMXIwkRafS4haOe1MovBzKXIEEFI65A3Nf+u9FitMWnaIQZ33ovT+XJQs793fK1
w/e7AbiN0zYle26MfcQC5rfPFhmvLJt1s5jGa0s+miPxBh3cnTiKMjkDlU7mhc7kzsZXQhQwGVXm
1TlBaO98LvAtq50X9cbNlrHqeD/iUh24YWo7br/+YqVBMYPYvL8RP40pLidPvnyziNueWKiNKa5s
fCmeMFcpOHxOiXbR0/LuxtO2yZCTy3lcyZIbgP8Mlh4lhyI2hgIh0/5+GbhU7NiyLOTzt4AGUOlP
n5YJykngOQgbRN59SUQwr9ATtsThNL+RNDM7w6VYnYlPxpdUiMNSt6RLoI4CVcjFQIwQ1Uj5qPpt
1eUbEroxj409nV/9+KDY45pqAeFM1wuUH0BTHeQPQ2Uk72y5cThiXjaQsBEXxXQIuSEuk4txqNXb
nKzH+vvD8G5YClYjv+U+jXhiG+jrdi1yG0t9Bx7Ww7IIU8hFjQk6Tt6WYA7VjmIuEMCyLqXEU/N7
g5Wl+iFN2Rowb+gKl83DLQFF8tFxEbsWM8w+QYSjoCTYCQA5oMGOePcBSaFfWLSCJ7//bfRegkrs
jmD6UhwvdDmBo1UqdW5DDCQ4hYKvIzVlZqWv7VDcdZWKdhsVYqdLmqs+IgVg/zZ0lTyn6LXmBVMp
BrGVhQpqje9wLVR72OHonrAKfngJG7MLsrITvfeqKVE9v01AD+S1fZR8euSrYbbDUeH7bW/ZK0il
qbXLDer2oBluadSD9dRk07/cVLP6szuI60uoxKp9WvUF22ngYe0op/joGpVcnBdnIcxWzM9ZTnuc
6C2DomN9bmwi9SaxcCybpg+7LQmr0hROn8O1wc2m9u9QAQ/z3CmraWqziVjoYmiV6AUmHQKzJ1Mw
ahW2dZbBrPmY1jhVQ/YWCi2WWF3RIYyOkwJuFifPHGARSx8DLfCPkd4sEvuAfNgpXTEQOFNTPr0c
6R4qj+luiAop25o6mQ3bzzFdZU4FyPIkJX3XxnBtEHmFgEW8kTBn0YFgxMCRVdcuW0exPNa3y8XB
0JyavsqTuCWNTh5F/GdmGnPetEjr55oqYLqD52cZrJHHTlGsdYN2QFr9OE4eu6qHalSQNMOwxAkk
YNEzNc++HKbghFOUlYJ+SZ1uNaHo0Orv1wfF3F1iTQCbhQAjf/P9EtMHcrI76nlkbbMEIvP77pji
6KlGWSdvCpTrYXn7VVGg8IJXriXla4RaGtIfW9fOnVqI+LIIZGbOSNSF1ClR0o1WfLreJwoLI8gb
xNldBX+HiCcYjlMOviNJwbDo7xxQeRAhcjoNPELuWII/rCnubV5tIrH7mHuP7f4pbBRaIIqwVOjI
eOIBTlijgYMfxtOZPeRSsWnNf2IrWfm02LK3gteI1A+SjtnNWcmvj83BhmDR3+CaX3/Ku6agFlNA
QQn9zPA/AWgjzqGRguVxpDEHyoka0NRM+//Jmj/K8t6UZykPmA5dqSnkM/93sYZ1ZBRntqTWoBep
byxHWsnJC1if3yL4wtxWCW8gIa95fjhuYBmsDTjugKD4x910IlU1lCLznd7YcUHWtMhjprX5iCfm
XP/pa0Ve6YPO190RVo2z9XgbfCuS8tnORpZNh5588vQynvBqzGS3f70NbzeGj/s2wpefIpuz8JGO
l4uslhLPqdhcXI/6TRzG9VgoV9KfN+nRxX2O4B/lc0Q0cgPaAA5gOgCr+YWebuIWzoDIRwEvCezV
GHIvC+jsjMECKj1KOMCfY3pQYhLhc7kyHAH3KE+Z3RUmlEr1GMnmh7ykugQWWM4pCrCgKRC1JCay
zpNev94ZNOmSVyQfN8ftbCTIXv61wjKjlyFMyV33UK31p3tBQA39zFngtqA6GhJ7eieL9hrcAC2p
WSP6jSWik8/KAyAEz1/F4mJJ6ln/HEDqHAoWl9Ez6So6b1AxOEuS0YlixoQkESwihcwBZ7MUjrEN
YjrZCSz5ol8m5NVWT05vOghgNom3h1hfTwv2QP9+SlMFa0rsQYbz5+2F/mIltfKLZwVN+9a8JIeb
1RO3BCmuLAo3LauXEp60XcGk3ehVbwZIlMyhoiUNvkhVAXvM7a2pta3wt+nd3imKF7GgeOkvd0cm
xSSpYsKwyE1xT9HcMjLbGHC30XMXMO3lid9GhSJLNA95PNOLUsDDSbanC43VyWjG+z5egnR/Uv5X
7oXdeVZtaxzSnoTuxroE7M6Nr1be1+8u4G4e4sRJdecM55TuJzwEO/IZVMO5ieq4y2zt063EzCXk
vFR2MG/EyRCDdXMpIymH+t2IALFnmcvzMG/A55fCgE1F4oJMcUtMGmkuj2W1y85maR2B4KujrCcO
BoPrTtiZh4bMLZQDbpeN3KgW2XqAbucFjo4VxPA0+oD10s9WvLDbqbw0Nh98R3RwYdaj6t74p83A
qpe7+7DVcrilQTy/F32yZZvYEP8eHSw9hiEV6COD59nxEPO8ThfYAGBsE0AVB5k/wo5WhVMNGY9Y
awMmYPlXCI3To9O6e1OGtxS0RXWQ8RtKbYzDjy+VCtpmcM6kixRb4ES3b5YT7vGdlEyJeu97Xeen
POvpbEZCgYJmCjqfuIadevT9ZQvEadh2Rtjug8rMtYFxv1Ajf9dfw8+xCbvnI92y0e/VJyxBNeh3
+gfmaKLIE2bCWDATy1RU/ym01BghnD9vhzBcmvERielbMP2CrKQwTzfXxYqW4yyGeBK8Zhszu7J6
GYu3qp/b2cpd/ZQY7wLbtnkCZKoQ9b7X3uqPHbPX50q1fvOiCj3Xs1i3mcq/SdF8JzfYcSw2Iyge
r/NHNzrnGQ5slUO5OXy1Iwddg7DxvEneU688Pgdut4kDyXNuit3WgOCP60JpclrE1zEkil4ckNDe
OilPdIzQeg2J4AnyYM+va+pBmSCxjNKVzdIv3TZuMMM9BuKn2Yv1xuwI9YV0ZuAsoSXcv1+9AWnS
Opfmv7sjv1G9H7HAxsRKj8Hn/N8/QKSUzucGZ+2d3LsNEwxtgA1KdvmoInwkwsrPuhiL3QgmH7GY
HeUo/VBptVr3SlHJF/VgtGhXSG3y6Zl7Y/lnK9QQ28gZa72kHXstyah3JMaBJQt57dE05VNEj4Lf
zLSYgnv7WPzzHcUm7/9EV9v0lW/hqRCXgLN8U3k/77Iep6ROumT7ssJVzfV8HxnxDHcuC+ald9dm
oppxigsf7pHVTy3Hw9qOnFxg5nzZjxPjLsMI4xANyfLLoPGbPcr5rNJDitpa3bmkyYirLXp6GjaS
2Gj+eTJJ5rL/+zFRA2oGdjIPuj0yNlxYSa4XDdgc+rrfNvQzu8mVuSzIju2mnOT2F1RCn4nz5zvn
K/5c6qNigyKpIiNyTT2ox+LA/J0f8rvAwuYjvIQViBuQccPaTAokjDIuWkHJBs088Dgr2F3C9Shs
lqOxhNipjGfzseMZar6e1kKkowAHdxyvZup1trQLCy0aOWKIla1LzBvWzpQaJy0dR8NJPmU1kq1S
UVgkPj9VzjzZ045smbhQ7/0yIusy0YEpcjbla4rgnKWsp7Me39aBwVrUC8CNHTSz9XnNkMvxF4Qy
FvKyIKmSkgGs4p5lfhbkOQXXkkvLdUWKQtJXlPbhRFPS3MsWUL1TqzbnTXiOGy6RX6NH8aSB2uDk
mIa9L+/wSmkzTk6PcXB5OdM9zBqpTUeTiVMu+RmgCfcB8wtilX56ly1S17u7acK+pBlcE6tLXuVl
vNbFUZqOzsnefHkjk8UGzcqeA0cVT5raOJEHWh8NhP98y1oLgzFoVPkhQKsW9R6m9g817d6z3M6Q
8t6z7+TXHjFYwWL72l+gzWgMmRe5fNMtQAedCHy7AOt9LOb/j9E2b0rJCQ8tEvYlSqqsGTczZuWm
eMDsObuJRBNsx56/Q1V74oBapdzIzpkQSUsGeQ4D5uRwtI4+wr/Kkx0WQ7PTlKyr0u6QAjP8v4cR
GDc5pOufT3S2syh6m4CuP9qFCC3EeeO8R/b8v6aux3iJD63XPL8Jqp3Bynwmu3tuJOxNswG9V4Ik
lw2znBfnxOGEOIS9uY1xv8I1KPm5Lc5aPM7PH5zNMWVSecORP3B9oVvjapO1NQDYsQ0UQKQsHJYg
Wob//MhqsVfa9ORl7FfnhEubCuuF70TgTWHGhSaMBYzUsx9Ws4Qh4MIEMuLOowbyKOGcoUCJAj3a
rs00KfKjiC12laWmSIIYQdfhk+/IkRCRKT0nU8OvCB0/rrlnjTt+JmiErriQltjxKcWEJ03VHb2N
FCfIdQx6wl+Zz37vC0REPURrnMH1rMpW2SHS0t+t2tF2gIfnJ6wvi9E2TUNZA6+eahbi4HcMCm0O
X5YM3GL/iHdzaRkmyaHjAk66WxekvzPJPbdRpwg4kFi2XMNjbSA5q//11yZnx660Kzwm7GFhWMiJ
TPdBSf82sNiPnjPJd3KFLhziPTIlqccZsmkyJO8t09eu2TVIrP5u4wtbw/UHON/X5JoXe7Yu1UYa
8AK/ziJYBCho2TGJoBt2qVczob/iye7edk53LvJYqSeOO1xctEEP/1gWpob9RRMMMmNUKn9Y/zrG
F6h/BVvMNzKcEjn2ZFSM595xlVTDhOu2UiIQuEhrvL1l3v/pwpR4X/+qaFTMO6plLR3xWT3hVHOJ
GXjpAYUyTeGXwYa6O+kN4Xu1fx65s1uwHT8ogWq+sJ3XVfUkNkqjB7KDxjo7gjJA+J8uYUtt3yVC
mVXbGXpqg70UFSJLk+i6J4iZLO+hWdmnITj/rn0DyfpU8lYBYWoT2gkGFb06cFmEgCk2DyHCoKDX
wVTGAdPN14lkIsRFY9pGLrJmfctqINwNE5+FrtTjhEtn4FArwBI5hPhWh89hzg6bVeLeCfKKud1E
U63eRl0cpYvFCqqgoJW1aPplrY9JX38+nVSXEhwTMw4tPVZEdk0PG+fyD/eCXTQVFWuLQxmdGzjC
SxszJaKBgPcqLR/Ybx6FYyB9s9cPipE57Suu55hRepEiqXe+QCfiFGOz79TDVkVx7dt4hu6ipvwB
WC/7GnLaLFjRuwbJk77a9O0O6FUMy/+Oa9wIjTq0Ihqw9sWdeNh4E/Pbi0OaR7Va6HhyL9wLD3NH
5hrAPv1Mszduf+wMV86pU3uz6gMQIgEZx0jZjhGaEW/xIt01uciAkOoPUYYThEwGdRR6Gloru7uE
4OHthRjdGy7RqePqBXCLgHkwCkqJTdCoNm83Rkya0uCGwu5BFvc8slrsIw504DlUmN/Ze8SwLWRy
q4pqE7KGng3+w4VvtSDyoUkKvNIt3mjPaJIFrqlMRyI4U7KGXgei61EIiwIbgKkng47h6b2Aocdx
lZ5VK4RCCNGcwhCZKtWnOKE2sNUYKdonr7Dym0C1j/cuD6CWXXrchjtWj0tCOeBRFa740vasGKQF
IrNeP7OpD5PBKwKlJo1IsezvJ2e8o/A2LpmZG1KnfcyREQjWLh6JchiuanWbaoWG+lRf0zlJH+Dg
Zf/9l/CkBbZ7utFzGQvwpLIc5uy7giFkNrNWjASQXxUwHRY0I4NmXWpc/29nrfvJzHtPcX1WQYfC
7Y9L1Nni91ndV3LFW1xXoiTuFz76sWmjLKLG7v1ve9NKTpPNehxG90IxFyGKHFuAWfyPj7XbS6Mw
nlb6foqejDTCfO1FXYE/r73RPoDhx2cDa9aTVVE8wwEf7cYXhnv2RVAlnNnzWwT0FlpGGGKG/sPQ
h0wrVnNCzPTKaXyhRc2qMVjT+SwVVkE2QqMwopmb3WYGrD8hd+I0rhL6pH5n34tekgkNC824VhJ9
DDV44WCy6EvlxNAIWB4IxVwkDTMq5jZXLc40W8kF7RVWznq9qFQQ900hKE4JLoCfdgNIqTuPXa04
BDJdG8NkRgqupga59QIkGuKs5+7Nof7ignBw8X0houi+VuRssxgR5W3S/C3jkoO8DDQakoKZX50H
FhsBK9UJuVBhlu9Cc1++nJPEV3fxNmV1fbEGFRTEZq2qhsbSfnBTMN4hlVU0GUKLzlC98Oe6mJ/C
hA7qpvl8nvX0zf8YOyv6oKHir4hewduWPn8nOFpcJe7sLiJ3SyivGBLwvoabPZCc/Ar/4y/6laFQ
wRfahzBMaVv4dB0UMC/fATqcIPywyNMPGtHbvgS9qsPjypyLqxMIwdW2SBjNjB3rQ4y8BW9Tup9D
Pt/EvHXmjqappxO6w4F19MgpBaCWh+slL28WX+j2Wbus8Jyb3zVDl9h+YYV9L49Go0tNAHGQUUIb
DyKYnJro2B1W8/x1UgpiKRXlgmIfiBFvbAh0ubfZGs1rzyCFGImVFFC7hVsDQQkkajEI+EoaKQLn
kDUep5j4fCcR/YRoCkhvbXDtVWxyKodkXjJsnx5K7mLRa4vew0utaQj9tM2Msz1gABmY7eLZ4bqP
obmt5JS89rlWaur9n97Axgwd8WNNzZLZoPUdRgcRklPH3I5aNdGD30mn0hUDf8PaBJg+laEcneHz
BPFh4qvf72uR7qy7lsT1wbnxlm5yfjeaDHqOWQCmjzowbrRDPT73Lr0uV3+weEQ6GkMUCx9uAH+E
M5Z/SN+l+gzy5QA4cCCqsZyKSY68q840knJwGL6mpvIqjPDp0SrprwC1D9z3J/aitUs5qFlA/QIR
viJx5S9ZMuwNxk5PLy+6+uvAlC8DS9NsYcqgd/A/dQgmKjvgG2R4nuCaFsHeWO5MrO48FfopJ9rq
sLpglWcgXwiymesx5L8Fxl2DpS0+UU/aWYdFd3yM5yP+b3BeslrRrrFR8UxkGgIwBNuZrVXGiaTf
pRJDBi67D7hJGMuq25I0HRcQ2Fk7xO77RX1peE2dY5RNt22MIBsgT6G75+JzLJkMyZza7jBpj8vq
tegzBbTVx9oxOZB/UpjJtxR1tmoGqDxtiSRCFykGbb8YpRI4hG/CEkrrjGX1YVNixzj2CuLwUsEy
z1iQ3/qWklABID3g7j3LBN6s1tDj5m6eTjIWeKh788Q/a/WOkAoC2UDldzdzKIVB3/pgyPoHhpf4
HlNdIqSwF9k4dVVEpuvEUMDORGwxIaG+mleNXsu66/gzFmL1/bKZjem72dWcI6lsWX1jduGyx6Gv
6ojIVV71rnRHi+QM1yijswcUiwEjpi/lReKI2GfvdgExleKZgDY7uCvEUZERW6BlAVZ9VGP8bb/x
zC9snu74pPjZhN6xboNfcy3fZso2AkggDcnk+nUR4EzRof+RiSlEn5IdthIibynBAv4lggEkE4vE
Pw0F6frMt61CqjKQooCbdfJ3NGJfNO6Otz44HwLNczr5gbmty14suN0dVTOH+6yMsfETl1+P/Jru
nSsOYf50RJyHS8is3KkRIVYGttfhrIGqRi917CpwylfNe5ljDl9EqMdzJFdc21pzn7oAV7AU8HFw
QItDURlJzTkJDw9L7wp89QHgiUWI8DoeRkoG/UI+scrdLoWiZ/yP5COkWk0mTC4sykUMbLIjYiC3
TP5LSeB5ehh3Yb2Inq/dl3IpMTR27mbf1Z1VklA1KOS6uKy94YTi62tF4svE38vrgw82wypwfxJa
CQ/6799V9DHGOp3rv/ecrlJQg8gRgWn8vpRm/lsdioGP3WONU7X3OVrnG3TIVQcS1bN+5wZ+sxqw
plCeC0dXHNvi10RRINLUfQbNhWd4V22f3/AiUxZJbjPvrllIrNjYbXe3KGMCF6XJI82uxX+hFSzU
GiWB0HIEsyY8/m0q7ubKXDANRUR1SkUF/qHze0bOz0CsGQ06jybJp3Iq3K1AANx174B+9lzFBxhT
bXEYvYQTtVK2eXGf067y8iPWHtR2/sC+Ukks79M0kT1AAw+wPZbtDtoQMgoEHKJFBk/mTAuhYDER
E/d4KCgl2YLLeto01+CjmcF1ayhUOQXog5EdHg141KtNKN3NG9By92JH2lGYisuxS7vxWn0eMBIb
svG9Y7fp1sWoe3GeV82x48qAYbJu8Mf5Z4lZFbbeIclt2htChuvX51U4svzWhFsZCUL8i6rfEmyl
72Qp1zsKkaZ2iXEubOnGc3w27T0uKUIbFPQ4T7O5U7zo7XPTwTmlIuSiKoGobnC4Y93I84uCGXLq
kzk/lwIqeB3hG3bvCKTjpsDdQeEtS1Xqe6u8g2cCALZjWlDo+A/0W6f4+0l+TQQM76xlyRmEUru4
HDcvZgT/DXheqNqcVOcK0BAO1Pgq4LYUn8NE+7AHiz/fTGTOddCxVIAKhU0QoMferawAigFrFpjW
swbzsicbIBxV2q2E2hURM17Oa8RTpQRN3LnLnFWlKbAjY7QuRQcG+rEttUhEtOPe4qSr3MZYl4XZ
kR89rUqXDym6f5wh7UzK3sKvBhdydVAuoF4RvbEnXEZyYq6MZGED91Dd1T5Npjw2UlxhydEyoexW
KSWgb68EQtqsAmePANcF5G+7OFKqNJM0LnmB79vcg9IX/VBu8USg5U4DZfcfE7ry+MUadUNrzIFm
+w0qKK+r4E0Qy3DL16IC4bKJd7gdDlown2Hr9ST/qpsPXgiPbSaqG1czhmzqtV7rXtdmgBSQcSfy
ggxpqHqZSeKuQW/aHV2n6vmc13Fo4YPUDXxjjvQnooG0eiCvbLiKkgVkF+ZejliEffRiY6n6IFq2
STFkbpCMc4iYRVGUVQYMd/qm2410pO3mYHB5tp6eZZIlGNWEzX9Q7vsy359XIlnlEuT3r6HuQjT8
xjAAaxuzEGHk43Zhg/zRmh9KJEztsHFO73CZJCN65XAoAvQeQcArJmEv3x/u4XNja1k8+lYXqjoq
8SywQqmlsboA2i4VWQeOIa83ssBe8D7iAqFMFOx3Oi5DC85Fo7NThfGFBwANTg6mgktMTqzbToaM
v/kU8FZm9caJro+qR0SKH54Tq3XEeOFOllC+5AucjyFpLfLHq+oH/wk6VAdYFZ1HrGqnoibrMx5C
hDIU9DUXTIlCohaoUjTd99NRWSGPz0svtYJL+Ety7V4Xx87f8igin2yBx1ThQW/8C/95rPQUoiv4
6efH7e/FECoX48Acq4cqbQcE361dN9oIPff1WDYKv9eDYNMwyHpT90OFc2ZG5WQKexnHl+4p0TdW
WAPzPvIHGAuW6Ped+cYFx4LNjO3+M/646jgZsNmUqpxh5ycONSMgMZ8BJK1eHYlvwlNKyAinxhvt
84vSsuaS+SSlrtMgORmLwaCqYQwrydiDpKYy6LuMLXnZfXEMCdfk1n8eBsa3JiVQWCRwfv9uiy5L
NA99pQ7+ffxh8mCEpYqeB4LNm5mEc9yX0HE31w3JRBkVZppEQvej8sJe9dSsYU9nd0ROhib/XTuo
oIvKA3wihvwVsVskp/cpJbgwNXCIPfsxDjhbICcGUE4qehnMBytV4Jduuh11tOv09RxEA60SP8Dt
S6DqRgY0QP6B82DDNkFEwU4U20Prrxu0SBvSBAwN3hs1HoCC8GEBjnuAvVMWYTbsHbsepEMcnhHh
WyFgozRFNLKr5yJmxxTMM60Zicb28Pda59I5bRFUWhULskB+In5nXGegUj7mqDOXNt2H3JlybNdH
+ycSXEHu9exDbN+Dm1hI9sLO10BA4eiCalG5GMIxAu0C2cc1QMSEZheeF8k5PZkbj4e5m+4BnCnL
NhR5HavTliT/98KKRw51W16O/siSrtLwkoje109EmRXP7O7qFNuLAZpHJEDaOXC2oRTj/BG4R/23
bqf/ykNiAJufAfBcEygQOJzEOVfQyi29XrHBUSkG/xUEpoYSTkVxdkQPEvF2s74L02awGDeQfrfs
itVj5P1KPHj1UHqHNCOaio6cQ2uG+2wCXV3Mm8i0JAI5Rcu6xNZBO07mbgwx4gdnW3Hrs0VMuWS9
ZXMPt18XE4cHRe/x/at5fqvljY9T7pfJWGKv2aHDDCkR1bx7TdASxreax1HL6iDsBkjgmt7fKkGF
Dm93p9Kx6cR/zRCAfP3159VDlmzW+UPmwtLRiwHqh8TAhYOgqbXgZtgnhaDydyrdwP6QERJhM8Sm
Da+tpTZXucRTSkKJoAvel6AncGexok7BaiHaqdCYc2cnkd2n6qJskLfkB43bU3MOldTO+f4E4JEV
R2GQ3SirhGwioFmyaTmMFQzPXGVu4dj51UUlpwrwecLFNFj6tpvxmBsBqd/Zpdw1L8BKRB7broTf
ZXn+85Pf23q13+BR0l2aDCSauIy4B2db4kVxgbuKN4xm5hLMdAgQOnMvSDzy1rUsQCRXgCfl0USY
zwzEBpfquivRorlUm0mMYL15xM+gd3aJZmwsT7SsoWs9n4uhXDGbc5nqL/pzTWNNqZ2cN1WgHHPs
+Ut2y32Gs5VTrx6dtj84z0PGl55oKkwQd/gaQt6g8o1xzz7AXcPrZ1v8Br8vzuSXJ+4zBGaPY/nN
B6g8PsCmuhTnjnfNxz5QxtIcVUZ6LgP/9xuNZW9s3WTSAc2sta9+xBrlGkCTxTqwTwapxzEcCfHs
4uko2RSRCVoGlLDPNR5juJvMXwtBy+RVIWjZaa5mGpNdt2X15raKZLeoB8sEDk6Wwz2tkaZ+cGDE
2kwspCaYkpHyHO27yaSvYQ0WZDL82HjBnYKAlnOPE8IvdplUBM5J8HXGNdZuPT+Fb6s9hqQ2Etym
qXQiT1Arg5ySdka+mejPt3DUqCThvID1kFVzAlp9H3oR1kkfrL2vuUlH6SQJxgp1R36T47v5Ly3k
yr9+nWB0zrcqa1NNGN8RxIjq1W3nOZCM0K0xmsWI+/GPb1CqTlaUhfRK/xMpmldOBZsoJKTj473J
vJevQ3dCzAbGcqEjP1N7fwufk+e/ImPcLtr6iVl9kAv2Xe4GcuXWH0GpUNzFgxCu+SDMcbbhJ4S+
Vx4/+CETxfNdIhqp4LCBFsbI/WyhNS6CT39t6IiLQJ3+T8IIdSITZGstGdxdJKv/VwNnPWLV1df3
f+CjxDbL5QM3tLO4cSRFQ7Mbbar3CK82Ya1mUt6cBywnIh5c3bya02m6qPDTMMhcK8VgIut3jVCT
SKh7tijEfseIdKb90hH9Q6T6/wIKXHRdHJ4VRMz/0TjbKM9zwFYg1guNmBNnYxlOUCKcLJo6S1wY
obT+4+UE0y1YhoZyO2Uw75cAJyRYrnoNrPSrM40LDQ0Vv9KsHqwwqnU12jY7ie1EwFyJdie5ytxS
3fOUPN1nixwM8qjXzF919ff7OjPaSqVmxH/EKjrjqHbZgrbrplgo+Z6S2opicdB0e0r9+o69naS0
LBYysYM/qymyESbHZcomEZW2Y9GL6mm3/AnKIHCDTKUQVRq3sL0JaznRdphJz6KTy7sMAcqzhZ7+
oFXJWIlBmDCGr+9X1FI32xBnVHhH+i1k8p3YOqQHEq4Y2oge2IhmTqCyAxK4eZAqwRzoyyOdxVm0
6lScQG7v3jfvKbYv3AgtKIy+4zLL7j03yo3+MDgvr+3miN2JDjOFJj2FuBHfAyCbEMj32KX0Ivtf
w6X44rbz4ZBRBaI6QH+jvhtSLPQ5HFwyNN1T46TbvSCGOVtytg9unFFX+DuQz6iuUrqm6WJ7/4Wr
Cff734sQz2CegFYqdCgMs5qxLOdJuGi/ZfnKKQKUw48bHv5KQwOKLGCGCqkEc5hfwRqJi368HjxQ
3qtNCRPw98ToXlh5gVqr2QF2fK4HvOp876F9JBY6QrtyIBH+imva+GqzjRQkIK8UJc74PJvcAqZE
TUNUvi6lNJy9cNauh3pUZqftfzoMS58/A+cTlkeJZDf8kweGzEGThCu/FIUCyIlVAaWS+5zvcRGi
Qbiirc55skUComQzUUABs798KRZjegCdzC3cr8zJqUM11Vc9mLmTZvWtDraL7Ed4THsVq1mW/j14
6QO4MWhsmJma92+mP7jMrOkPh306wkFeuGy5peIvGwp/3kzQymymaCrX3bTaUhFgkORytuQA9kxZ
LhpirACIRfd3tfHnQmMd/ZZQV4ELKRejzFUC2ayCNj9YntoI40QHRBKZSyFVy+kmxXJmRY/FbML+
JGrdwCoppK4SrK39funwwhPL3wCWeLhdIk74cTsmmiYUluRkr2j84AFmOIhfBWoyWv1qgzj4P7gN
5Ksv8wDjtDXgS7iM0i/HK/KA+p7fOMYGiA61LC/KYFs1ZufCAEydW5u/pt9rBMnDmKaYtYRf1Pcl
tjox9q1turY4h73TuPKQK6x3+YaUsCGa4GHa+RlWLovEaWedNZR33FVnxHVitcfmk6RbY6r/H2u9
T0CI4zwZqH768o+22umGhLPF3ua0tT0ITLJJJ+hUiP4TXmdQfQ3nNaA8XdUqo8E1hsTs9rUXPCrO
XU8D/EtFJy+cJYQpdwxuy5XzQ1KshkGBw/WF1K4D+8twsHbsmgZnRKoQwSyUoJ+/kCsHDSNlB1oO
Gist6utUdAQBbW/oI6gH5VQZWQlSMPQQbfTdrdB/TEATNmZMshnPsL+iteuwcyleP1xhWTkpQ5Cy
pc8RcLi4JxlyCGRNCrER2/S7G8C7Dt5mLT0UJj3mJctNj5xLRez24D+srdMviHanUKvXQ55TkGaK
J9AoeBSo27jf0f/KuHCp91prOwYWkL+uMsun9lBpPEAe0k5Kubc/zjzpi4JYhVFYoE4XAu1X8YAj
FHesKwUs3sNnI4DLNRNR4kGu678k/u/g1i+drK7kGs+EJfhw1Q0IJyzEoQrOhZFhNkp9/jmJ/mH+
1w8lZTWl/OZtiD+6hA6xT74hrcQsdYEpg0tlTx0QBTcsbCrJOQ6B5T7D6FXBz9JduXJMQNrPItKm
XZO/ZDtQEPt/zNyXFx0PqNmcfzk2iI2TEPLeRsjinD0Vs/+Z/hm/saD7qHaETWtwfeZEsYolihJl
qcDrlKOTvfL/uNUpuQndvC5oC1XOywxVpQObF1AdNKHtl/tBdDe54AxsOBTrn/CJSH6FkcKLehVu
HSog0o8b+YvY8Rk8BDh6On+Zn+8dgnDWdRzt+63HsZAy/7cV2hteN/dTP8euYeMPA4v4KJB+urXO
U3+a2GvT0viHW4L44DonrVHJxhu45Yhc9vzPEy5F2X8ug05A2b7BhNJFjrexbPyvGYgEuxEWFN94
8tsjPEUHWbchvVHmKfyU7ULIUVoEVtE2Ru/6W7rRIneWvJU7NIGy5DrTLhvq5zhD7XznqyNdCIr2
vOC/g9qwluz6CiCRwhcgtDIIBhhafVERqhXaw/S8dYqMj+SHDRETceibFgvRmuSpox1TjUkIe7Cw
DiKihrRIgqoe4z1y3/Yz3iVNYTYJ9e4jAnNjygjEBs3fBE5EGkMPRkWkq4GWEaoSMAP0N7SYoTVz
V/ftkDayLYIHSqBN2snbT7UCgEG+Uuc3+SghgT7otuRHhe9xqYR+WdyXFPeS9CDdQYoCWXZdXtHw
KKrI4wbqA4Ns6WzavnZcW8ai+8n1NT5+hYWEaCw6v0YwXrJgQHa9o2c7iVabE3P7opdkaAuYjLf2
cki7Z03Wfu/cvl7Chvm7ABQthaYu6rHQhqBRwWQ1JOZFWhO/iLGj3G68iRdBryk5ZlPOLoqw/7vh
od+547IfF9V0CXrpeM2ZVS2du43jnP0M9rYrqvZXdIERQSmdSdtyLpPaUcnrZDtajz88WhRuhzs4
DZRQ3WBizH/qaOyc1dYIn0BjT4pep8fc0nhgIUEtQ+AHArZ4Uyu83/LFBp5lXByHfFUcn7loeJ3p
raYphqjY4RL7DAkgl8zaWVCSvzyrC1gggHjkk/5/bBaB4y1C1PgLlVCZ96H4gLBglIkIWTzycyvk
TCeV2xzdZCnZhNRzgQYTMu9+Sf9exW0bjYTctw2OLd1ekzjwum37WF8G+HLS2G+6tpr3akOelSni
S7tVXuuaMnwGQUIVPWN1UFgzFsYT+QbB0oehbxKUh70QDffwVG8A/TnVrECuUFY4OvcT0Kss2KWf
KaPSQTq5ebW2/Sx+TaULYnI1ZxVxvHP4ado2qtp9cVDHkxgYpdde9y+8oHgMEQpcIIoYxu2vy0J/
SmYb3r066K62H2Sgy4xiH7bvh+mu7u/Sd2er/pHf6oO3Q7sJJ3vXJQRge4uf5KQMVU4ycBlc3zyz
vZpDyfe8VRLvwnCNrGJIN9WZ48+enj+B4zzFokLE/bM7Pn5TLluwGOrwmUnhX8ishObaX9+tr6EA
VjHhl5mfuMNV0MZ2HNlfcYDsGSzVyWdy4ZTMDH+KXrDomi+WiXo6OsNk/G4mu7Yfaw3XJ0fhR6+D
lw6A6GR+X7x2SK1qAfCLrRd+1xQaG7F3n5xkJnjXzUmO+LT4iH4dse5HASZIc0NOmyNlzvRJ70Ys
u2Ep3414fnB94V5l+B+iDzLemh2+qtXdxB2NlUANGUpojX7kCdCEi9TbZxOpYXJgvx2JFr++iNmU
GYX3tMVgkAP57Y08BDAty5VPap1/asBqa4T4NrCAy55MP8FrPLZUDx3FooAKDOR3ogtcaYC+IUfY
N4GiDCsd69irf7gcNMaTGxvhaaaSTCJTBjYMirBrALy6GizLcUspOEYDwmiJc9Xh9FtSUHB2+O+5
rm0F4ob+bPCIKV/lGuWiZ+cCRaceK2vIDgphHRdcYX4y/kgL61tVbR98YWw3AqhId8YF5Jau31iB
xidzm97aHSQwQkBlZjciSi7r3ors23BiX2hMDkvOIlwnppCTBS3/bxoa/G6CSs/iqGjN0LXdmfbp
xHsR+CuWpMtkMCcE96kl/T8YKDMGDgCO/PJfmxSMS/+ucxe6uczHIZI4azLrHd8bvg4XaUHZ8Ey0
NQyG8vumoxojPzmCCkbWGVSERhsrmmoFZzhAZyVKs9wO106gJmOrf7JxxAmQc4taU/Cb77OHgPJP
rEHSUTvOmCNU46YOrv/d7kyjJeNB1vsr9Bs3GoxAGj8HcJUsFa+tpcI7vW3FzJRpQnBnc2VtY8Sf
+Agb/WDFIQHOJGTwcZFCu+pSo62XdoXnpDYdSxBgEA1Dj3WocFRm8/C1PapgEz757aZIC4oHbua5
c6uJTICjO5lNhNYgxnwP8QSaNPSVjfJngH/DGJUm1ie1WdMJy8dt5ueho6Z5SYjYGUv4IkLHdjs7
+3/IMn2matkBINJqTOp11o7mzFDGTh0uiwoH+UTXIaXnhQ6+T25A98/l6jPxGkUROw3jKuNDGXlO
mjroPXm2KgK374Hjq8qzNHANnV6GyoG5yfHFUgHZCE0HbTsQoY+ZQz+WxhKOEJJU4XPI4ftvZ84q
16rBh8+kSLveANzN/ZJ+Jl4a324CZpusePufpHViokYxCZuq+JjXI3TApGwDP8tYb/RN3XIvj8Gn
YikyUVfqCh3B1WEFykLQCE+af+eO3yX7AE+FtK2+d8i7HPAfkXYFOBE4XwH1HpqbozMi5QeO7tdK
ydZbm00pzdwBCqBA2SYZG82w3MyH86QaYJyuFLpovRmwgwzDsutnw+O4wVWQirGR7MxpxZikwQ3y
1DyVjZM4HxHoVYK9X1bcugvxqi+++p8p5ssr12+h+8D0RB8Ypa+6S27Kk08bj9j0OFbAGP5SP0oQ
g4stokpLT3uXo+PnhzEA+WSN4DBQJpjA7geqeJEw9UYhQKKv3greFrcPoUVAa1wEp/9qiF2F/CKd
qQIO66DB5KG45yO9apmfuOFLC4/aEH9kmcOY14lZKa5Pgg4N9YBhhmJkb5DPDUXK2Z5Aln6A/QDh
xlXc6SN9ylMT48Mf0IZ1AyvFjEMkXjxsDl+jbHup7Q53poKeimarwOJvChRyPaEV4Kp3FQDGmy4C
0EC1AD6cyg7E+KOgULQJmiN8M6GMPQVE+MaLHxDp8o7GhTe8WZEuFRDeuKsI0OgR6DdfXe3oGo5l
4QbDAokJUcNb07mFRBE9zwd/H02Q3u13uL7Eu/N8R3Bc6lcfIFXBcJwrz2DMKb2TfFX5GZQIBcN7
Cn7ZjIy1uocU2iVw7xAGTlXfG2JBq9KM8OBPl+OGLThpKD+bpdjYeSouMJCVsyHEd/2IzHjyXebS
c+aLMQp8pw2Utxgmal3g3sQCJZkqJrfQkmuLfIZeM4t2rZZvYppBbUo3eTeIqTumqH4JH8K5mZuM
Ezjocs2KntDyuky56K5VWBxerI/7KMYOF8NAr2hiVAdewCeoqZPhj/jC9x5VTY/DqP2+0djx8/Q6
z/uAVqQEQsbEVL/HAWraABOrr3ucD7WDKT7bBE9jpeKO/YC/x93GHqGs7kotSC+Eeq5bRLXZXzFv
GKjxy11BdSu1H+3tCMhTRszrRQFLhyZj7i97jI8bItIK7eUY1b6VlheyzLQ5anP3IzXGzfnhba7o
KVt2UAzHJqhiR+4op1SwTQNFU2J2eiQ2541TcpjIFqoxP69RnSWwNkk1M8N9h4HAdNjaPw5oFOuU
Sas/dRqmVZLfTClA7eYxh300jXZVywc7QjEGbyu8exi6M8B8RKZXn5qVATj+HckBtB9OBoDZY+yE
JuenicNjbsonqOcGr+2J1cjAfPRiqtGQKMMAAJd7LOW1pO2lyf22hlbui3LTOn2i3twIBFdVZt9N
kZXdERCVyTeAZEtIa/G+6wNTQacrG5P3DgvJjo38hMqrNmjZoWmJge/ndQ+PVeSwWY1F6APR0gKI
LTDQ1aqEq3JevSbo1ruePvYACmv9wRDtf/75c+OP7YPn5vWAbbfOjQXvpLMGnD2kb3c8aNMKIWb7
L9uSwv+6gdRf4Cv6FiDYynDFGfw/72v+QQlqpqkwDcwmJk3lZM7la+TxzTEIz4Xua9Rk0WR0ptBZ
yyR3v6lTUKiCc0LjAVPYSB1VICG1Kv4zvy71PkagLrUE72A1y/Gmin5RhLUxTEnJ+HfGESd2Cg9B
TLvkl0gxwEFP8JtUG2AiZlStk+Nv5I85PPsJblwPhEJhf4OhQYMG+metNEyED2Nekaz4a2pVr4ng
gAeVdXam824adBxVKpV7D/Ofm3m/ZAn85NzDeqQ6JRx1xrKKl3hL2nqcxT2SjC9r9z4teyHAuc4x
qG9OVuAfeKjhk8G8w1XWG5DMgHePzWeeOKyd+3wtFGOVcTfM4dnIWY7NqGOfpRo+/GjPFtllh3NC
CZal10x/4SgG4nVFrit5rD90YSBvYNEtXi0zmG56yVBCXEqunHXlf7bXYheOOt0uNemQvV7UTqCn
U68WIGaidAv4ynrJC9t2J3HCz4XlFsSey9qhoHf4FomiWg2XTlyQQi90cvcapCUVpLWOucl6reqz
PQmbMSC8IjLDxfiJV2icfWPYT66WjERpoMQ+lT4gMi/tWua/vDKC2zSvA8dPAYzAUgKG8MXwHJIC
FJMC/tjBlomeKCm+fDbDRASv3BRC2737PlIbZIBEmm8jHC7EKaUnSJYUkKroUtYFBBjGyWCVJELm
buinnAxMHWZT6WtMeQmvK0YhvtLGWKHZxSizvHu0hQgmZKbDopGj3GqO+nZ/0JZBvmRbAytgu/bn
o9R+Ke7rfmiOEBivBMfl7v43hbrEjlWRQrrynls2DyQrb/VwbYqS3q8p09C75tXprPdqv9wHueqS
iruMcZL4/E2KyZWf8cbYuj9YfWHCC6tDoTSXodht7myBH9to3w4brI/Dh7oJPncD93QU4v6fxbPg
APjU7P8WLX5rvJXALy65qvHjTAfFWMvYndvkfBkhPHX+92gqfylFxNEyoL2dyH+oTIYLJQp461bB
D5gn4xM6mVLayiLgHciULKN358Xwk5+gkWaxWyO4S+QYbhy+j16ejBxvf73op/l4On9hFywNA1xu
9dPdW+v3RHcahWMRvPj1G3mzbfWJwwTMfdKIp5DueQmG/bO4mwcdmfEtFl7NcFvqnJU9s8SIa8JE
5E+5kxbY3NH1F2acvm+K80VvRG4uCyNA0kGrfUgKFFq2TrKDDOMQqpLsDPEjwDnrPDJviR45gzqD
+yK7Bw7KOEjscSeVDpM6v4a7q1zflZvY9wKo9/Hjj3fSbsPvp0gTxdnvQ9p+aWfbJ8Zp5CtCqZRF
mtVwMGRMN2KWoCi1w+pn9pWhSU7UKEggx6JxEbHr3yzBsxCJFiS9tw5+u4NuwzrwuoR3JqafVfqf
/jmOJi4kbRbN81in4dQIP/oevuzY5mn/Mdu+91v0dQUgnm+AKr6Fiye57wdahj6V7lLnix7L+Am7
6bgsFGBzDegLpbgqZmhZb7Bcisly+SMxbZ89bOGPxps/abUpOkjGl49e0HbfZWG5KSFE4XR9ml/Y
j4AmwrbyAldiAwc/piuq52+ANUtlDqNHdjZgoklgmWM4e3Fh7RyVzrI6F6VW9litbd3oiIM8NmAP
O3FrGJr/sagrGDgdcH9KWSRlv5J7zTv/H9OzGKZL+toEH3UubUPlV9/etbhdHBUKHV5uX9gDHn+S
EtHe+a+rGqmmyRDXmJX8f5POUgBjRR4FmTljR7Z2MjH5wUEwMYgw2AZHjFh3xcgMsf8y9XFI/sB7
b3nAcDUe3OZUkwciyMDhg2hMgp9GiI2M/p0ymVudLYx0om6Ii3aq2ZKUl8pQCj+d5mVHfemeniCl
Ym649P1bQSZ5HAJiH7+JoZhaZzWblIUxwk+aAJAS40GzR0hsryTWnsHqDBdUAuZIV8nCVISRlns+
hWUyQAYSix4Dfu1QV7+sSt4GPNIRbroKmKRRcCuG8Ey0tOwv84TEGkIvmIApbIFLGL6IbB7hUb9e
CfA68eSxSTzDV5UTmj59si6hBFVdUlvpq+mY3DiKOjgkb2OX6XpokMgWSffM94aULHh48TzH7qh4
DPXylaYfMvSm1qrb1fqqreRlKXWfo6olryno5aqLugWPZz1BbPUQaybV7TKmRIJTeL/EgFqjTjvw
B2EMyPZ9v8f4BZOqYmtAhsG2JsUqWbMd0QuG6KEj08zdhNm3P/j+pjWEvBresIgSyvM04r0TNd2H
4wyIJGnd/MvBkEevM4xEHMF8Fl1d34P4gCTzZHJ+j/sZsFzN0t2+47SzxVdHW6EMnFEW7MTExPfO
/QntU828fycoxD0UR2Byqje47wHBFbNcOyb9OpDf/6f/3pyV6c5/LShzC7bWohKcfUTkElDImyk0
RYYP3S/oMIIZR8ddgt//Zm4G9lJyfUoGnet1VqwhGtX3YslHiuQ6xYBvpwe6nQ6ubzuCwQkvp7zI
heFTLHLEskJcYtHgudMTK+J69vYXZQLNl0/8JfxKXr2I4t3mhimuLVHt9t5yIPhsN9NtxpsV14CY
jaW2M13cx5bOv7hNnG0RiPK0PCxH8KpcWniyrMJdHjIRIu87xge/Dwjl8ljTRLVt2pjDi8nSt92h
mcPH6wYwNiI0G1yjhNx+C1rxSlcquy+CpmxTX+23uB3FZYLFdlmiD8Jo38dCd2cVAFAhxoVH+0Qa
0bOtUpaoHjmOUD0W5rkkwWnhiJMYGCZxGN3wgLnrD5W/msx26AjTgBOlKDuMzm8BnGlRTiy7MDaL
yAchSDEoffCS/0nDCendC4Wg23Mn+KmycLttmj45o/fJfNhPaXGxdVQ+RoJbRoDfxkJTST55x0G1
sCROp5fuy/VbkHXJZl78H21NU0PO7sa0qMpWRhxa0ODX6rFqf3y79PuPb48Oi6vlMUTpWlXM1zF4
Bhv4H6ixoB5bopMfup/oMWqBvLsnXslFC60YoxonAn0X4H5Yc5Sq1r8NO8zdwVqD43uUCtjY6Lds
kLCyUBMgjCBJt+y9BzmnwaY/ANkxi+K83llylMXOFujsafkIw6Q8CL4TWGb8AVZp0joUlCl2lZ7t
2MA4XRElgSe81hIrY7p7nwNEQq0Xf5gU/zaGjKUzUQKqxxjFdeIq2M+8u5V2edZj0K/rPa/iVsX4
nJWStHqhQ17jub3vBB+g7ys2yYRweNdE6EZU38uxqQW1EYMOAcPBcvNxl3OZx1FxFMN0KFhO2b1W
yoN0paK+qwQc8evJC0qUheclhsIebq3ISqHzaGrlwPyW0ZP4U02HDOB1b0p888Qba4CfOJqTc2Cs
S2EPTrvBDavP9okXBUx1sXHtuPinuGUSZxfl1BKEJWI29KP333he8vBvDuwsZZVSytgszp4LOD+h
v+CjFlkyrEZyaNfhqMN+9NAZQPI3btVTjJ3LXmZ2taqEvQ9KCOwDn5K4acGwZjYuCZtwTIpice4y
rfWjtS3iIVk2He0eatUS8gzxXvteLIqfUTyZbePeXllxxyCVWkXVu9FuihakAp/BQLX/36g4jHHv
nTr9jaeczsAhfQegB+jzls9sP5DD4IAX2jbHL4uJNNjNeIHDHJSrq68gvo9scYq+4Bhg6caLMGa2
o47uyO9b+le7MBfrbqdFRx2Cl5KkK7RYy9ZfgnD2AO8CKhGVCFCBLjcumc/1Fy7aKhIbETSTQUQo
MsLC0zXGRaqEysylhobQMhyDRwQcpPyLklzzyl1e6R/OnPHIqNgEs1BR5yt2vBsPsk2hQ/d/snie
WivdTYmPI7MPe1+66zGn2Zvf+J/vyTn4ofOpzoLHTBXF8ta+QV9ND/XCVAl92YiNcB/DbrQNgDR9
medh9n/iYB8qYUMDJbbckR8QxhyBdg9lQw/jr+TA7P7A/Cb+MjO+GBjOH3TfqrpMprvjPGpgJQNB
ux/y0ho0W1138Bz6+1r+ZyRP6h+EITiKduoaNATeyg5t5L62Y01NAohBDgdkANgMdxLVUvfKbuZl
K/aQsBha2ZAHn5/ooCyiaBqWoTolf/l54EBWfc7qymAstraIQycTgnsUls9RSViKdIvgNA+rewQG
Qnunh9X8UvF3r0I7VM9gBa82VFFi1nNTN+eF9fzQqHlKlSxGe7LlPgFOKkUjAzggrIfl1ZDpf9PF
qkgtgwV2tshiN7PJEjfxMhm+BO5pOJgsXEnGFhx5yu5Je32GSj+0wEQ6QPQOwQBf2RemxeFjok4F
42tlU0BzNbiN5Ym+0qvH6JcHfhelRNE/uOzr1dFMKWtop1w56zMh1csiEAT87nVaYwtmmJvDN4bo
6qbwdKDOnGU3SiYfZTjOn7zIgSJSHzzRK5rbHqlfnb4wHdkgeWjK5G26inlFx+0JosmBs2F6lKJt
gMf7I6XHYpxQ5l33quZzEMM0IsTOlRElP3b1BuB4V7N0Eh263mMKBOSyJppp+MbS9gAVF99qyUJk
AkSm5omOPF5MD/D5R09fH0Zw/0xddluumt7o25ZtyJ8L0RgvDWSXTw7wgjdtM11UXR5Sl9mKma28
awfHhVvgqve0NlBDFTa33kRrESzGuyBP+ZQh8Y7BRZBceB89mOyFD8SqWI0OhK7Iu/C4dBjVaCPc
ahRu0oeplkEYoNw0hNPcocRiEzzG8qc3BCD3D70aXb5bv1w+AaFx1yQTbkHoS2hEGLb2f5iTDC8W
rBk48mUVxdnIkFetImeDHBZVB+k/m/RtTnFW1ov7Hx0RIlB4KrGNE/u2yQtfWoZLD2KQUlRBR3qI
buwX6Vhf9A02AYNIkoXo5MW1ANqQxWyBHK6koxTeCq4Xd/n/HU+9FyDDUmxHRNwJoX/SDbzn3/y8
qOHa3pb/1+/kxwGG7T8VyhWGFO+yKF5jlv796DvzqTpJP1klWIbrmS2Xsn7rhuDKGWl4MAWV9uAI
WmDkaE5iHzMxCg3r4w3oUmlxpcEl5mSygIl9+eMJd3z8srU0TVlh7eBH7A1kZWYv4ykAeEJR7XJw
x8GUuFjwaWnHXDaEDnQbcQDXkUTPIBihHO4me3W44OSv/vr4FA1UW9nVIuWRzaM14/vtH8Iu1IoH
z7yAXOWYd8wjBAGkmP1oVFlv0HgZACnY18rgaUfA+jbajaMTsmMLMm0nKsBUVlyGcZZkVROt5MrS
3Z90PTeHhTsB8V+riN1wgJ3AN6x5qZIt0khk7db8fCGXmeupcSNomKeJHWiWRUkJY+UlyB3a7cza
0yBzByXq4jLbAXu6uWKzQZ3SUhSvAWscszHVQYqLyWIB1L8R+68mSKys2kY5TvrwxDHU01tmMBRc
A56DBhcgIxCpam6lXd6IOpijhxbjeLhznJ8WWYkjwl0cOKqMnd40ddqk72gScIQhzG12SEwVEEJC
NjPQNL422xIR99bCD3lTUjMAm88LsE+6VkknYyTZNFVKm20jnzksIMRS5eKeR6DI2CYjYH3kdxL0
7IIdKV6kg+vcxp0AGkfU73raxnSFMIn93KkjbHoKI3qVgKZIWqylrGadNSCOQq/Rnpp3T23ChAdM
Nk4LxTtwxK6ZHA6YGhVHFPC8YtKcbAeCCnypQEW2XAhMIGVhvaE4mnA4uUWasIfWIdPhV1ElRemY
5HPu/ssK6+yCabFKeNvYXuC1qOL9TXVxel8AMzf8ggN1eQ8upRXo78XDhvPxCbZIDg4uSq+IlfD3
ki1gf2BT5mEVIFixNiaxNG21BL40ZcJ6GdJAg8YuKJpmzF18SG+IDCadD0iWIeoO2oXzJilU8M0I
VGJu97foqYgdxkpMFq36MWFR2XFNxFq30y9abaRoMwTxY1kgF0vu9/hOBohH8GMdHL9BfJjDgtll
50YTWpWyVJjfuMVuN6hi5vBp4XkRvPVhLbigqyxmLSful81QBIW1utefoe7PYOwYatgTi1D+0FQT
JSFdmWclS60vTyxB75hx8BKAIrtD78/1HyGWJjmpQGSHs4xy7S7LphBN83lDcA4J1GCrhvRjeDnZ
8U6LS8JIZS+kV+tCyvAAH4XYGk2+81tFDGnS7wHiKaobG36AG9VvPzwJ6v/d7XUGK2FHDLWIqop5
1Re+5FTjioXSvjkp7NZQcHZQ3k5NeDr11Q5WdtDLnSn9hKnAqLqVirNHQzS5ZryaXm6hJXLxNi/D
a3rN1Ru2/K5kC3MujyQxUtskw9eEumdrFV8+y2pFt07fw3OEyuYPxdMqHNDVD6mxa/x+93O6SQE+
gQRKi5hsFIRWX+CnsdpPBN4LYKY63FSksy+LOHEO4sbuZjB8SPA8huO9/hT/RNsGCUHNKkQIbD25
tzQ+DGic+OrqI9sVFR2KK5R4MKCiekUarlCihMHIszvb5G0pcvD2uUMVEaOLggjAfDdwfpdSRTKp
ZaPXZMpjtK/YcJZNPlX9R+5HMOxmJdiGxmqBw2xQ/g++cxJFull5Ti971TTCeD2F2P3hQaixwUE+
ZciN0mZnqYkLfrtC+U6r4TzpTsfKhATesc8FaprisBSD8G1iSwVi6GfGvw/z8YDn+EgiFCQkIQro
cWe3PMNFGmiBu7kyb8Ddq5s0heo0Fz4x8cLjJx1QFf40NRDEpCz48LUMcrfbh/3M34/9fUXUSnMM
MjyzOtYHztGuKGHVlrcsYdbWOUCK0kUT1gAZzFvzPy3/OZUnrx3vQ/PNruKKwBbrqwvs9kUQlQLW
LtrTakn7U16DJrUuiB4CnaBfL4qHPs1PK2qWei9nYoUd+L94uSrBcmp1hSff/tHlhL+GMpaTf3il
rS11wt8Hca0f+Q0tI/eQqUilRwLBnwX8i7r8Pav1/+03ymWNAn8yuqse0g5xLU7carIWqsWUaD5K
PBRHyz12zC2iNa1WljFzBOl2oDnabm0VvEPJV5mgprzQ21hHmg2KTG8sWLXXCnCMkbjfsEwcKCHk
hd81k0Svz1angPBeXxfDkZJTbvlSiIxUwiQTqqWVNxK45gYKR/Kusel4zPyFU4ztzV/XnqALr4oY
SoVr9e3kIGyVw8AaZi7AIFIWPrE5Qn/Chmd2yyDpfh7dCHEvxFDDM1ArCuKFjZ5Wl22/3psauBWW
enfP+6Vi9JGrPJZEAtS4RGHuV4zId3PCWRq6kgwYQOBpT/lKk29N57x5NzrpdUYs/9ajjOL0jzxK
9CfY7vvm7GNrxaAv/liBm99lArkzOtkEGP4Eq6WLcM9GtEO4sY8ysiQlAriZ3/qPP9ZC8Zeyod/C
kp6+IVyZBZWNQ5NXMnpuokcAaWjvMSzIRxl2abY3aBAtuKp4rerswc/RmwIgeJG/XqY9fn+CCStL
wKJIFcEYHvDtXLcBxpOg4IqjwOA4W6iTLAponnPCxGpM6PQpOWk+ApBQkCMika+6GFjg1ZDNXo00
6GjH3RSheDonChi9D0sffudJNup+ENK/2+QwtJnGRzPtDotug2ssIi62UA2a52MR2GX45gjuXBNa
lDof2qYv8QqohuBTYzLAhFVZQyWa1AW3T5hvOI9SBGtVjSjRcmDk7YNpj5zvGxG0460RvOqezD9K
7wjwD8Va9nS/QQXUSfhQQYXMX+dle9G3aJmly0JyFm9Nl06vAD3aYPHH95z66M3durqYUO+pi+Tg
LXeeIPjH1iazCgeNQECVtpyBv/Gjh94SsyEh78M2IKb9kEeyeQ5Y1bGCWh1Vt+GFRvMv3qMfJx+Y
JIl4u6oesvx/hZbx55OwnLpLwZhsYFKQPSn61PFxIw/13+NNZlm5luvec7XgxOSHfQU+Sam45VgH
SVIeUcytZZsc6nsZHJaI+Y2H6utcv0bHFZhoK96/wtxjVaPo3Ch1QVYnOZMBtHd6myCWLON2pP2l
Xbi5fpcIw86W+iQloyayc+Rx9r/RYqKGbXOwPAxr4nfupUl243MWbJofDE4JvHLnBX2oh1T3t/c0
HhAlyLJKiCIF3ZX7EII+lTaV/UuUdtCQexyfkjzv7NzI0CxKrZSf5m1DoJBXyVlW6bmqX1928T6W
lFmkFo80FdUBRHppfQLP5QV67xcO/1Yf5FvNiN6mMm5tMOrDnn5R1UiEkDWYuMCvdJUkuOgwWB3k
vNttWbaiVG9TAgYTGGNQcGydim9VudftFQbDX7EM5JBT2B9MD3u0booeGjSFjw9OHdOTo7d73QDI
/lkkl3zqZ5YJxr8or/5N+OAzKO/wPnpCUf12MN0GAheJLpY44C/k4FMLCVnLdUJXLh+bWlj86kvS
hTHN4yAF0KUmN/uI4n1BOSdsELucrD90lKlaErAnMkk5/z+GBjVHhhVU/0u14Vqo0jTf2+q8/r/d
zM4z5p9MvfVZykXY8SvZSpg+mzSELaNCdlGPHWEDaHYM8EGnmH+WNzZTe2poZBYog7N1/C3WKv9Y
v83sqtXEV4fUEhjxPeaj3O1ldybMyaX8q6T5tbgV1qMzbGLAzKvCuxgG3JjUL4Q9/waKMUwJFHWy
JEv9vTQkyapFUpppbVCLkwQS+Ujv+wTo2VTkHD/Ohg6meZu3tQBv1yquPug1fNnSxP9Y7NcuWorB
EXqnWmWWLjNXznuWubL582paQZURR7+lKxxcyKkXuwYMzIaUqVbtmawpCXG8w57lHlq/zAMXYWEQ
jyBgnXAB+cl+oeLTo0mv5BWmh4x2kpe+/8fV+Skwqhh/9e8hm5L+hzblfhZFtuwA0NThb3X1LHFx
7FzAMY8yP7Vqw4IfPT2M35AhTW3EdKOYfgJ2m7ziSF9qxJ8//7AynP7qdn/U9+tn4ArTvZhUsp+t
FrK+j78wiZWaP6s3iSKKO+hC9qxnlzwOpPJJpceowSQfK9SFnLnXoqeaZbkrRIlvJRU9oNAf/1Dw
GZci8hv72PCKoraiwYdT2j/z1NhNcCD3aY5fmwzo2YEG3UGF8pnzsD4B7mgIqUQ59ZtWPFPKrWhy
pDI3u2nNJU44WqAzdUPk6FhI+hoodfaOvOtoyV+YBwio67G1nV0GFSPRMaaT2E6qGdYQxkSBB8l6
+aTk/LI3T3keiBBefkaOt5j8vfYH6JoSPhun8ZRYfP7jrsZCK+oTT5x86zGA/3yX7f5mVm3d8y3Z
ile9TXvkEUyrTt06YEZrQmp6yvVhFhNLCgnHsLFsi9LlI5WzhGiQQqDrAVAdqLdYXlW2G8QDafcZ
/93U1pNK5XVMKMLKqjM4wOGXDWWYw4mT13k1iLJdnVomEy3gYE2ywKIOCM/oQWwx6Bj0zrRaR/A8
odXJabIjUHfq0CYfA9HeAQV2shQVdZZ4cAYOnojyc07eAzNiReYvH9Qv2mot2hS07R7Rxu6xwFTZ
HuOgdlvWs9C/RUWeVDUXSS7kOEdDho8vLXb1egqE4WB4pbs57DgRy79SBYekTHVJ2Qcwfhkk0tOA
sBsLX6s0HY0BAf2qAUqRHyaf6mW1g1nXtUNroFjiWXmuJFAVG54BlLajIihWfW0PGfv+dluKXsIt
aVdeVgPn/jCwgAYkFri2gfSm/jtuUkYD74OU6YZffkAY4HT4ylGdLbgt3jKzwR55MN/hzLsm3/ZF
0NfxL+xB9wDo15Qao7nZyjcqw28+B+lFIQub+r/Fjm2+3VCwK5vjDR0k4fYwGU911tHX/aL8/2U1
K/voM/xj1/IQbo1daEG/HWgYCOz605P1rqgXU/P7j9APYT2KGQtQLoyBZGop4UZkVtTdjyXUbYYJ
T2Lhp/zJZfGyhWZIW/EK2iBMpQW+Cfq0cgwe/19Gpdjo50slqsgjjSsXgXSCp+XGKK2b+cDaY8oM
Eit1Uim9qz4iqDFucfk3pRv9YNIoWTCO/vpwojBjAmitBHZw7Zw8t/5UynoAWQ8kDR5D6d3jS6Oo
rU8IFO1zwIoHZoxYrqKS/SHOkKYuokSFEaqpGb2gq9IbzSnTfEx6GIZK4yqwnS2tOVSSIKhyohIe
eOX/vWcnsbO4ClbkV7GEQnvQ0jQFGOpramxAWIQ2W33EnEAXrAe25285ckstjyqmBgFf8N81y0JU
TfYgGNCdoY6GkaKyj7vK+c6Ay5+nzBLDXVK4zARDpFbH6Ktu8qLveY8mW8pK0uKlEkzbMng7Apm+
A8AqJUU89nAtS5UhkkWgWHOcVQR5+G72BAilkDGZdE3WxGIKbtJJJIfScXghtzI9MwbjTFr+j+DP
EP0LnCI4FQCfWeMbk1WoK/1aHvaPeNyOkOm4S5BaejpNwpE5qklkhRg3NNP4/giJRH0XTwgL5KPV
3YeFCejh8iCqtjf84xDf0cO8+U7YaCUvOs8v8pbxe5nKrjDteZCAmmUBPSAnw5ExLP8KxizM9zJm
I0UKVdTKoHKOfcmEKKWCjCCLi5yHNDOVG5HEddGEgo6tryoSvmgMYTsmyU/qwCxmoPIBy0O3L0VV
xdcoBRrQQa3nVRaDZoUo8rZVxd6ISsrxM3z64w3K97j0vrhMDTMhIGq2UpFALrD4TlV+x3x3rXsr
FOgki7uPeRZRLA1jhy3CeWXIaq01/U5N4jQqzSfQTlj4FkwNkPNn63PdpiqXfkslXdY9ozUDw6hG
MsWm8pE8H7K71r+5uPGXa4O8DH9q+8X5IqdwpcwET9OBYXNV7iE9+5E5tbdxqc7Xn80BD+hY7E9v
wWYXetQtxH7tQd7Qb9Coi3GrN+GvYqSs4ZcYkepDkray8MkWdOSHetmGm6Za+L6mDuqe1KUxLq+A
mJEWbefzLHYT6a6O7jSl5RgWRWjCZDXf9NEp/OG4CjyD3YLcNxwWSL/qmQ9w02ufN+3ls16PoOgS
4/18NGTuwpESClmNZw32el/HZX33zNBBAKGm88j84b4YPgJEZolSLjdETuirY9b6g1DJ5jHkxh/R
x7EBlqEJS30d5XhPoqmrGT4dnHR+dohn6aXZ6bdZF5cheZpiUxU9RdmNXIXODh2WS3mhF7AYq0wX
8Ywcxc9NjP8f2VPcK7PGR6B8RitcrYyaPE60Aa/wyEyavvanHt2xzK9EB1UzfEZ5gIK3xuZDM0SE
fMMtqrLy4s6u+YwgbOOHmgveVrzGN6EFaCye9B0RtO5KG6xYfFqAuz88vhGUcuq4CsFInmHQxYjU
50i9YBh7hPhw0kk3sfrqnpT1y/N2wEqqCsQFQpZE6cvLX7KSO7ENQCutm0MVecGELJ1fpBFD1Cif
F/k9J+kPESvBo0T0xx/8kyIL9z+vVLR++zbD/vzpYM7Qp1w+P+2E3hd9HUXPDhTdzRXC5ca4CMQP
vYjCDkrWXFRu4MbcsFHUofa4GWIII1OBbCltq3YL/DgRDwnSLeGATWacTq29vYnlyR2O6q5vKuRp
O+5pdjUvCamJ1FKNOqpHRPeAEKqwL0ym7NeA/ebSqDa/TD8FxsZcuhFazANAClIjrF97aDjM3WwA
9SWRagFDEhxmPpkYA63RQo1ShZwGAnXjdw9YM/SbtQ0Wm+8zfvOCJ8kusahiLdeHqpDivjbIXCoT
fB30bRJUTjHNpxX5MG0U12DcVs/ZfUpb59cLyRGpIXVCsqVW2oS1Jj2MzmUBfTPVTmoEgwoG5fs3
521AkxTv8oSEquL5cYrtNVirn7xzMK+w+d+KujukddhOx8LxZ1cENWTQs5dMOCQvZMCCt4u58leY
zk3vH7kW8XfmwMi/GRWBidb85DlH8SKTKKnRTuryXwze0LOr+uDduI3EuMk+VEgtxGJE9RBkR8au
7uxJcvsAjr1yqtAt3duJxHxmTr79VmczTzySAaEKzToj5cz5GlxbAUB7wAsVDQLqC47SV4TSqk/3
1OpMGCW5ddTTQWgWvAyB8TkzCF5ks73inP5fhc6Y6yhmGAK0a9AOlQ7nv1LxZn0eJgfR0QdeZZQg
k6XH/7jcFuXNReOnR+WFog/YxcGHH0+ut8K6oPNaDpEugdwN/ev+QSeF7A/6vHKy3VducvqP47ou
4nG0kfVAqnAmFsFpGuinS93B87HqhjFP8tcf/aQ4me+axeV26zEwILxCQ8MNlo+TFNhR8T4ex69g
LhTvL2/iO4UXHs4Y5R387+uBvcSsodhx3WXR8NRSiEBmfMBjubWKk1N9IxpWfx+sbQSxMMFNlYUI
Rq6HhDWaatj+ymoaIlFuj5DsED3/B+Lt+I9qQ6K+5u6X3yAY551ridrrl52M+JDVt5/P4Uhd1e5o
NztZ/atrz/2FO/7+BuGPWaf2VM67zA6EjveD3PO3b9lk8C+Ynuuk/qiQHDS3dTKarBiFRoNxIVm7
EaHO98OZ/oCYtPwl+KepOC7WFlqWZLunvF0Ptpbgge8ININrQUCnBGvADitUs7/EJUd1wKPsRBhC
yNBIkQWxOea8AVS7+UXEjHpckoNF7FaDod2aO1BJZeKLG6E8sthzo4xTWkyUMXGqgQWp8F5JTWvS
8ebqB0Nj2C3yiIiN4Y/iv2jOfsOogwyHu2WrLkub+4vj7EOMG4e3Sd9qGDd/UH7XFmjw8ksYE62g
4Q2lji7Ll2FW3WOba7rHvj5mTotDGpAzvWjg4SLkaLVXtixBY2b/MEhbaGRAb6R1RYDSOuCWge9s
ZCd6UmSEqgyrGe4VYvxEPmyfNPKFgnXY2BqqypaX5QZm7NqNnLINqIKEwheL2EBFKNXjN/wUEqXl
sOiR8fOXlgcjkNVi+EEXfrdFFcdHAqBk4ZINzqx6X/e5mdXEQ9eEDpRwAikXb0ivnKvmu5ibGi6m
RjNicdO4/7SPUZ4YbHWjiwjUH+DVOcPay3/PvZba+Ooi2lBlmmEugr9/whfZHo3BvnL4qpJLpkIA
6EgTgAMtDZFK9fUaxgPjlu00gtkTdi42GYk8f6S5c4cmPrLP+N+zKhMAbRQCKPJfFxHgCR5ZXfjJ
nsYJXFUVx5w2fYMjfcSNkH60STFRmq75aPG3VzD8sApKI4fML8LsgjQoHpnmp9Up5X+6dTI9Hs4g
nV/sY1l/67K8/Xogn1DLJra5iqGzqQGyvqYw/ZZpQjQHj1J4C8/5oMxchWaxomtjb4eIYHkaXTgw
NF6zTx80UEszvuaMK7duqtOcQ49ZsCtN27WrqvKyDueoHTewndAHuMHk2JRmzcHdFWw3VkUQYFat
f+1Adk2KYwm3cSzAAazdibHQcuyez9B8kCGZaxjAfmnrvrnyOv4nuuJs4IsXwegNxND46xXDgSYy
06nyvJmIyPYg1uhB3Duh0BIta9zUycN3T2To4xMBms0CKeG9lGhFekWTdc5NAfFOGivWZSbM2DNK
o/v6zf5uV9uWHuFVOrhJysJXyOgmZOBcVLK3VM0pSCuXMGBsnwe/40WWlIghwEP2LppXRWhZ63Qj
EswHKEHJEtb6RbJCxHQltZa+JppsmTkAbHYxzqG+tkP3LSooLEORjNXSU70Mg+wAhhtLLFvMCma8
ftT/xrebaJVx70ykhaLPqnxx9j0mEpQPY/ESp+v4kmmjqFchuN7G3NbOZ2ZG7OMOJf6cR/f1wpM2
SNPKBfC+YB3pR/Z/lfHKcziFfJJQQDKV5KxlgwccR1lQZXk8Xk3uzUyaar994Nb74qzklcqFAXeb
5cLxecJLillO0APNkEIoQWdVvfhsoGFf87b6HwAL8y3g3WvbTCijkgVj9AWsdwAKCBw3L5BqBJU4
vZWCd7VK7OQJCUdDnYhXDXKD3uOGoV5IBP9ELuF6AZalooRUqBHW8bP5KM+u2JEvf2BytMR0r8Ht
TmyCFXpYUpi4VsM6KVoXvnqHMOAWnpmPDIv4v/gsHl90PEzTTVItEeQk8e1Yvg/OtWHQfRlo1ROM
KEGsA+KLTQi0voZCEtHW/7st5inRIrm4VbM8QYnztMC6HFgSnNJgXXHhgmpFHHY3Lej9CaNO0+QR
zF9/KbD7hWtNBwrvBcDFc2j9xgehEu+N0+1OOosW119Y8M4/YZJB0/tZ8hOnSaYoWtC3wOyleNaB
fNU3aEdYZVB4coO7mMgZu6CRFZTVYth5WBnhOUHkB4YfbjpizIIzf7R9zBud+xDe0xhqLtqMd8Aa
QHYv9plbDNCGosxCX8zDM8C4zNQJHxlFw2U3jf9m/qkQhCNrA1ykUEEnuJwzWCesATEori6ZqiAf
GLyfW7XIbLBlO/P6HOp0ZC9FS1HlwCUvq056QpIp0ndgilZJaeOuAtZlwz9te2guuFInH9gxGKNh
XYRN7W2CPqz5SAEKGOXMkulMeIA+hruHdDwNe4pImqv2Q+J2eFbzcw2urI4n0S4UqvXZq5XZrhUk
Jn089d0lyjb6LTfxF2eQPS5PLdLH6LRCU0s53bfZyyOQ/AvJ1x07L1h7gwjbPC9vcHniHXSw7C2X
jcJUe6tmxlkT0XZEmUThWSFtI9ymT67qyYvZabU2dvAWxtpaWvUW2PzEaVnT8fyEHucUAlBulX5D
gBkC/aUkkaBr0a+0+ytbAwY280mrBN1nfAX/hDP2/bDoKwfGTmmBR4HlbU/ronsWVk16D6k3I/ZU
adtTZsVBY/kmSdI22yJjGJ4Iup/7/8XFw5FlYhDh7RlXKAUHYzfyGzUp7XnfkicfSSbGf0REbfsq
gw5Iv99gYUZh0itDuLuM15R2fmX0T1yEuIFUS96ZGlz1y49LKnP39BifuPETgnILJax/DcvA61yf
1qY53+HPuGI7XZlV9qCVpV/BZkiJkEj0Fcm3JQ2ODtl9/ZE8wQFlR40JyxO/L66SLm3M9CIEgcBM
dqP/ujyLZXEu4bVrrt3sIjjgKoCJVOcnx/tOeZAACgaDRk9MnDoixdAWntuKMz4Ar/QyDX9VMxkh
dwhFJyFVi6AUEPZX3bHVIrNmioRhFM6eSgduiPUIDqr7gi9LkgT8VtHPFviEO43xTCE0auQ8eaNW
ufz7zh6DrfEx8o+iPXvRgzHx4iEt4tEe85+1CzaLpYyP2wt/GUjZQVKdbU8IjpZ1WXo/2QF7Jv7b
v3bziDZe3EWVxUr9J/GLboZT6/4OZ4ZMLgAOl+WlffmVq/aJbOik1kcQXz+s66SWLWLHzwdNtjYH
1sy3rBa+tcOEzdQb8+WTfa+LRfevyAfWsaTtwou55nh4vHmK99DtYV/jNF/OosARptdKtvX594MB
C+aiwyIbt89UindUshJqxKjScrXIQYazCd05+oFXAWKou1Dza5WmXW3GZjx8s+DYXwjyhKfetb1F
6ocqSEXRpxAF+KDiqjX/ThuZVhbUkc5grJHOAKrsHzWBSazIbqMUXl5k0pCRCRMoZw/vup4RzStp
if/ZislUliCSKG+5FePXBHtDHz1AzXUZVRNrTAGTZ+kBulhnCo7lOM95PgRabPbedmFd2jVDaCHU
05KyMeKAwtrMGh/i1eBMeLRbznMIbUROvFz7Pk6sgu+wuwEpHRtuoHcUT1u97Dn7OVMevUitOmWf
QV0/8EfTlJFNWFGqsypJXIiBVtBy6NnYoRyr/R0vkMxVgpT+3iqdlMRbtlonK0WyiGi937CWwQg4
eIPE9YBefNhKt7KDcyf5StuX7kYMV1AvKZ4TyzaiiXYGSwdwGyrwm5qwHTJYMbpOEHGeegFjWu7v
bgLTFZdSVngI6AaSvapOd/0Uwl6OYhJXGhXs4zSWDYcziPhuVmArfAMjGtc98lNRXMrcS/vI1Frz
vEcXTl32u8q7+mYHs3fhBfHXc2MbHtycgFTn1OQ6kYHZi01cnxBawWHN1hFKVY65VtvyCbQJf0l9
RIR4KcwTZBnkNkG8SuKcZCqej5I/Q1NeMdAll60w9RI0wbb7HX9hTPhnnfpGiXO7KEMmF+sz1Hwg
aXbS76jUt0HROJlC+jxhWXLSS/Xo2x9RgEhRZg7LSo/bwFay7LPFUJsfx/QnJBzfHzL5DrM9qVDD
2rRZKretzqQbEiS+q7Kb9OzzKVMb6x2lYZedSeD/fsCpREkl8zPzXtUT2wUAIIHwZEPMZL58SgEc
x0kVYEo7TD3BE94a9qCLQzXFpxfJn6lTGGWS9m+T2FzGbD/4Cxy8EGa7JiJHssBcr8aaqIMkjv9E
5BMZATcHJwBOJE6O/LX3sLev6EQ/8ivbJSJgLyq4c0Ucdwyt++fMPZ2Ti6HzE1X3/yRt8ivThLif
ORBA3HTHIbvnHJkQvMCEhEChnLI0rAR66I/GhY+pHM0fyK1DiC9Gkk+3OfL6wcqEQ2mz/2QwuBzG
MR9Wfpy2QFWP4mSofAjsySAFyRuJPh+44zszOMSJ9a7Qa0LUwXB6iqNFc3h/wrEShVxXBm9PFrpF
Zj9mKocPgxjin1TRZI51RIgwaNHC6tk9GkKAvnBNckQpq7a4ipPMaBVsKvIchHOXnsJaQFAxo0ot
WThc2Y36Q2EyfbEnz5jeIbqorz9z9dw00UnKJaKpvp7OY/nXtlPKkOzmS2sSVEXLZRtnGdCR9WQj
gBtYkb6maUd9uTHK7x+1WmMg9IM8F4UGGkrtEypi2YsWfKQ8uw32nH6QN6o0jamRjwywKn/ch+bb
ZEoF8Jokt/0TvSSJoHkAxKbHX60Jn9Utax3OVBMsCsVBIKqJM2L0KUqAoYO9MoJhuK+S9h6Com59
Mdd5XDmzFPcZR6e55Z29nHz74+Z3irKsbV5X/PM1dlzZh+mbT+Cs+nSw/Kp2Tnysd6Ws59l+vv4P
XicKGjTjJ/anRB4HHCRXVSh3rl1ahMw5/udsJJOulyud2xCWuX09GBlF8QhocDB8KZyao6c/pc7x
kBS6ZHxvZd5gfyKepqZVn1GXEeToZgJmLPp9Ywr1pO3NetLpFqU/zsZ333FXjS6/ksRBFHeUBl9z
+C+7Pwf0IFPNyGmiQYdjOFgGFkxeHRb7k7wZY3TbTZ3gJv6yUJ2l+64lIvYAv77AO0Y11u0b3ZVt
8vke/FApxCzvYy4AocjcxVKUJogTYpWlGQA0QwbEb7UrWyYFU+CU4XBIrmCYlzt/fr8q0Zrw/4gC
aonFN54dSdgelznEwPi9N2UfB4m9yyWnvnkm+i3vJ6ipo7p7IWWTOYmdFFNoOPQMsZYBZ8kZQYse
So5Vb/mS3Ze/cY7KAsSzHJGogKJYTpR8yh6EwoqjRjSvqOp2oflEeUgIY/GwMJHepRBNdOLLi+0E
+rie6WDQV5D/2r9HZE7uwaPvzx+fMp8pmTTPQxspha8ERNzyOS0TOwjZecW2e+7asVqeRJeOSFeI
zpN5KfEjsQ8Sw3VixqR2zsVa7+U63MQDjoCc+CDxmbnYqxeK4EXr/gHVUla76spMjbQH+fUqI1lG
zkt0KrDzoGSpC2oxcqlZCVdG5oTYRP5rXmSmkbsMyQwMr+MTqvqTADeyO0ho8tjKyruZ5KfI/Pfc
ss2RpA26RDtqSpn2xJ4xe/GutfS8xq48vfyRFPY8/t5mjVR35AJQy4QHf0KsrYuIsnvtG80lrdHe
ZSszZJIfNoe973O5LnMwwC+CffSsucY2pAr3wPH/ZZCjIn1eLYl/snwJTr5xot5pNkH7zSQnbJDa
RZhne9aGJ3H03gMNWJjHtkeqlDqcBiorvqT6WxVAElhPkWnHfbH9QK5ngBnXHTpnDbDIdOBw+Pc5
orKUvVOmSef1wBQTL55EKo2Of9SkyhvU6rO2OAU1sN9ZSZd2ZHeXar+jc4cEXBFuTiNYnOi/DTvt
xCWI8KC9eOXe7l/KvUiAo6a890jFjqgmLWnvdNzHmdjVgIxSlnU1hgC29KOeW3gGXRfG0hiAZyjz
HGwpKsDy0lGCiCSBrHs1LynISWmfWQlUACBGJ2nLrWSPCcfcD/NYTQzC+2Dv5vZQGeLEQsy5sA8g
MC4a4wLHhQCQsc8zt2f6gTZNj2OYfU3UjSFAJKeI4uJvxHqRBd2sM6yjwC5qovkAvAF8AVKSQagi
+2AUcKoIkx9UrEErVL7CXlEGt7oVj89GYKHITrSzh3GceRZL0rPXxxULASAn57gw3Ge9Qfv55upA
4oa00d71E0p9ABJ470gUBJW5Lcg9+N7La3CJrtHgU3ZWDq9KEkX5ZnM+JPtiH/NGjEEIhK8gaCVr
TNBDVb2fnSQTjeHLK99WGuMqvl4TaSXWZoYOrjyV6n5q/Gwhn+71hSCLe6jxc8dc0gmKbOHstSny
+gcSnJtuvnkjUAl5QhJyQymyL1RWHJpZfDlrdWBqeGVUUUhbW72gI3izhu++rslRRGTdGwtVGMWA
e3hjYUPdeQZf+3JNA8KviAByUEZ5CtJnCeHxI9Xd5d5aE3nM8q70UnZojRSsX0WkMHmvvfSK56ZP
13TwvpEXe0/9UgywPXG8skQdGYsTrmdB9HkGxtpTzuAkXMUy4V5swhxxXwkcdobfDT4VxlK5o8pF
8/oT+ECtTPYHNS4Feg9boD9X28MQ/Ga16ltykHJ+1nisygyc4XhwwbBIGYtkrOCkotj3cLw/Yz9/
Szq2kj+1346ValLspxJfcu8cWKRJvr3Ajd4l5wfzXZb2h0Fl2FdWsbGPXoFCx9QwMDqHtB92lsL5
VULAeXSSryNUvpg8rGaqAbijyJ6wMzCNFQp77bFAaAwzJ92C02EuMF+8YaIs4RrALikV2RjnLX77
aLrflQb4xUvU5B3MQ6iUASeXILEMEmstEc8t9apQ/BG4bVApf1iNGJrypzc7fIWQxCm019VW2R21
qafz7BgM3FPJeJ24K+BAQhZS2UrVSJ3sVYjHRapgzEml1AQQFhqvxiwk5DbJ40O8aNtajY2cHH9y
ORAbsZoP22tZTgUELiaYGfqxPI7eRq6g+L4NTbMsUutvG7xNZXxezL2MyMBRKxVAHrzle95Ch85Z
/R4V/VoWmamCzqQjO8eBKhGXdWu7LWlO+DR5CiEUWGldwKKr1Fh4uD5fOTpPwZbkD87ldPbHa9zj
+LFN/loEtg6yE/MjsQF8HMgx/QY7NsgDbhvzfz0lzoSY800V83YIfAS2NGl0mvoyUXoK+LVyM/jW
3W0skLBqrd6J/JzecSQBSYAyL+PnYmYecEB9FmomaUGzhccO4ToAV+KZrB9+h7hQKZ1lS2XCXVKc
mUtxuDdtMqvdCqB+hfQ1PJ+y3aVW2i1DcNYQ5RE8BV/3MmXfmc3LsbTJJS770fpyB6CMFNX4l/pY
PwxHHP8ycOdOI7Ea1iG6NygMzGkkhrk/b2YV9ZPAAsyozLGfioEt6ZNukfCfibzxq3OpfjXc1saY
93EyX2UCRQijnYZ3eGrS43EYTatx0t97SHm1GY4pEvTkMwDdtFbNuIPvtiZh2JoFMDfCVtu6/Nsm
MjNCpydUiIUHbIxEYgNYV5AIiLytvX/cNWgRiopLTAVCvGo0gEebuU7VTorpF/v0LtFfF/jNyy34
ciOx+s7Pxwbqvh4ahtOCy8UbS005J1zKakHZ3adTgCT/pFNpcnO8Ur87sSe1ffSlI5I5rm0e5qJK
NalIGezYnM2cTVRxcNBrU46RDCw1eEiNR8MmQJO1xkIDRP3o0OIKtTvConpo6myEgRq2ksZT3ZMk
Um1i3lf7XAqaLvKq9avwQ74ea3qCKFveFsBbAnxvrM9uT6KmpAfvN2YNMV+Eqrs7PeZvuDdixcHE
HPBWDlJQCo02JM8rh+8GMCpZoQ+lpv8Qfo9v1//Oj6Hga8R43QE9u2c2UGsF5IepwEm5WkqzmAPw
JqbQlOlpkXbNyg0MRkt/5j7iF5KtjEcuNlh+FwD5n7X5CMT1NUJzbwlQ6v8mKz/ftAf4HsK9hjPE
zYHG8Ojp7lRLx0SbZPWc0TbV+seWrFuHzfbyYszLVdlHShZ576yno/2Wd8LjN2Ye6l9wJFapzICq
bGTUIbAPTEmHSDTpsiSrnHC7nEgDfx7mV2Akil74ze4mjshoKRjf6GlL44c0r3VdTkQVSa4mQscq
7dffasLkGjX16aDOj9VWIMV0Mdol8SoXXKTPF1rxQpsazXCtmILoGB3tdcnFoZX7aTz5b23QCtfL
NbZGAaeX0vPZGc9cfFsxtQXumS103dGPzhTR7RarOGJYTWAhfjuVKCv6yJDLo2een+LTu12pcxUF
kb2bmJLANsRHlNQ04/lqfJUbPrm/lxKdSZ54w2u+pAK6+cospqcumlMhpgvtajEsusPD9/qYGu3Z
0S9CvQeE0pC6kpGRSokfkHL1VKvYLLjg5YJz7dsUANMGt0syCCYC6X74d72h5hfWT4gsJ1OVY79D
3tV/sj/2WcP4zjioTQyN6CIlwZ2d7iUD+XnpI2r4h/q5HulCizIPLHyGN9f8QY6w7kTML8gz4bQ1
ldIxnr0qJnTJWrV+Ku/RzvYzJb2eqZfSAqQIo97Tvz3ofCQ2vWzF1Ucw3actU80m4SAqxqZaobZr
8JtIvW9RyQGDM/wVN//mGzBfUXZjimW0Ky+IOWO685NrLp8jfZW2Bc+jPXKUUiQxt5QOSTMoUVNN
YQmBsbvt0KP9wkQo1eh/UK97/X2bs60DVmTiqu36XafzmQX1BFdftCnGOXO3HaVmBIszMihlU4cu
Py0qqHrUL+oHO/mzRMKFQFDzwII31dMBgr00Gyvqs6Jzt3LUbJdZudpDV8qCEU2jCpig2QByyMeo
XwbGO3SPaqXKlLS5UsQXoaXjfqLiNCROCRmayvZUfo4GxkASPjuJ/GTM9yiAbQa84K5BRSYbKAYx
JUMfHk07kGA1CQ+byKTR6HrSZgch3o8dZoCrQ1+SN9dnRFxEKwX/DywmdssqFIVFe6UUr3yQAHAT
36oCv11HnKjSGNvg3kItAPqEgiJuid5YKZ5n7+nSrcsk06Dq9zfB7CwA4NpFy5oeBJZpy7X+wnkB
Alq3tnyQkgvxSUzWx+w/xEWF8ojXhixNBBo7byH/aHdyLMLx75zOqZV+YEyt1zX1kFH7CY2a5M+i
phk9nCg0NIOAYVa1IMrCn+t4DDkW7cfEYUAukh63KzbL04Vr4EXn9HbsNiOrjHe0dB3EpHdv5wgK
+thANb8C/oa8cD0qRT7SFYPkZAQfMVAHHxR0iIqhlNLE3rc/YDuZbwSfcAwgv4pxThRMlT9QjX63
8N13c0qwfhKb12o77Oon8SYzpdqO6NQeyqBC5bmAi12FM26ASQG+1j0SfcEdN6lhrbWZlX0RWQNC
NBtzQFIaYw9GPaRI3XgjWspyrToFepWZkgtIF9JM9OyBj4aAygLUnawFcFAssiBg9dHCnDkMCiIg
IUp/31pXR22tCIX4gOv2VXo5imW+Zzzm2XmJXpVZDYGo/kYHrvtwrMjVKbWxb30Mdx+7Fyhnwwvs
V80Kn3kivtk38FGeDKjqZ+1rXTkNcJsuCHQSCBPPi4EmY/RgLj3VY0m0xgPKeYuRBrdPZvhkqfga
qpuVAeBWBN+vCGkdFQI7XUluyjexQ7890LeQ5RPDi2QBYjgdzoasze7qGcHRTirZCDSli2tKPNaN
z7lUFle/qtlUfnTWtm4yHeEw9YZIUyjCeTY4GQymhYg+GhOj+3HMO3GxtC0wklYpYc7M4Krzivjn
pSp8cThCz6xnYjFtAvKmnX2cCPS5lnJWubSZ9c+2i1Pnv21ceXMcaGJuog1WGxoMhr9eKvIQTkao
xrpaxpSjBgMR+JsN+O7a5n3jZzkP/PK3oyfVWf5BTt21H/G2DklK7gEH7kd7KxR1K6uOhdB2pEkU
PdUJZ8pGChEvAsMjF+2YrxJJl1SqzDUsJiEIeEYwrPbB8/KPnUCZQMR53ca3PRj/ojWgHNeaCTVU
RXKRp2AjGFh+HmYt9uZsA5Jl6XskZzk0FAFo6b+iSCyGqBA0yad6cuvS6hG+UebUkL9zdYKoNH2n
IPaM3qENDVpFkbHlzmoA8zYZkbk9qVvfeFQTDTDzGkghHTQWyIKyOXg2PRjOYHF4x4afg5qAd6d1
y8LuA8/nWqpyMkHeSNqA8dGQNFz4ZvDc/340X59CWL9FwIAKSVFjAj9AqIZUWgOaId9GKVYpKQ5W
hSLMlMIx+0iWBgn7+WBRwpehmAZ0myLpBPBuWfGmTSuKPU+lOrobvdizm+BZVWXyEbM2EftSC1Ew
YXdSR32Yl5Ftlsv33+RC6KcnmeAp5pVAdCtpBRa+2BKmyaamTtY4sjo2LVDwC9vDO/SpUp3o9Ll4
b0R8XX2ab8JH6Uk2LKZH0kl5u+Mi9CrazVP9YDZtskMbI2wmGNj4G+iq0dn7n/zxvL0BJVHCVvuH
GhmUecznz7SwUtFEdmbJ0NXSUHxIs5yPhyuvPF+J/5Cs2HOsUsZ9HOypNDVWN6a9j5OznNksK2KM
X+JGZ4ZkJJb2kP/cFb7IQD7xJHw4r6MoAW05xQAPweddEB4CKOejMcxIdbvJiU6Q+vJIIXpQgRrc
ThM2gTAWbmNAXuYmrceZUSOl8nHILyda557A4aFllHR2FAAaa6TSkZ1fCESov+hnIAa8sVuzp7ZX
EXAbdcQNgzIdcom17TKMg10O2SU8AJQzYRUPxv7JLBSli+Bm3PCFA9XrWtQs5zLQD7hnNF1WQjhZ
nxF9CMWYdvVxhef9fN6aNvzsJTfrd7knAKyNWu8V3eL3d51s3Xosj62EVYZPeQQEAZ5DDYYYm8vt
ivL0zL2SUizB12CkYFgJnUfnmf7ejFvrm8SZQSphBCWtmf9GRtpsxnhWGrs9Uw3yWQ+5FrtRdb9Z
LWkTyeJeX6Zs22cz6AG9yHdX5q/wKVExdjGXMG78rkDwS0T8dPzi4ryPBcIzsMdiCsLxAMYsRpAq
eGTB4CbZxH/2Y4cbajG4ESMpwMwwAZm7yL6sIJDScokqu4FAzHF/tDepgq5EzisNeBwGVr1dJYD+
jZW4Pw2eEI2q6JggGL7m4QBPgyHsySMbyu6C+Tg7GUDbotu0AgaXwrjjlhlZ7t1IUDnivAi7PuQH
ZBUaXliusYrGU90v/TAnFI3tXletHYHUCM4mKeGKXYAN8h2xyiEw8ucNagjrQbkR8nbxVwz/h+qD
axeYGOH/hka1XU7AXTkdOYPodpYY9/O4AZM742TrToBPE+LpMCz/u+L+aPZ/darE75DtMExgzz3W
QV8EBHZXRLSQT1TvRt80yYc6X7zB768mz6ffD9yoTzxUJtVWmtlD2Z2Yt28RKt25QR6crrZaL0xs
ft0POnQHAfI85qvZPiSVevSULZd+PtzETKM0GV70y1boSFXMavqvO/ziITTqVyxEBthIpYvDBUbl
rh5GiOgJVssYFuqhEkhqlnTgVlb6hrx9Spt/BrXxL+7Fll+vc5/iFsnWHJ9qhb7BUg6qdDjF/r0t
9feNan8WyRLdQzyGpk35bbCtux3oHD9gpNewyfFSJhANwk4iunnVaAtnRGdtkHDspbG0EdIavfNd
G88iU+ixiJRg9LYu7gHMqRXcuBCWc9p5BsEwB/3EXGXBtwDEbRT+mQKsY58NjT0VLvEtKI6hHlEY
rR6Uh7ZQPfndoYkt/3x8jgd9SJIPTfbxNYKgKSKlGEWp2bsYb8guBKzviK8pwja167eXCw0wTUZs
qovN4HulH+NQWln/1MF9ahVToSzqcPiylQ29MhBhootsE4Lu0UQXzH9Y8WV/ArCOTJp/7DBA87eW
B1pAVEWIjYLy/lJPQaNLudqJ9Qh0eEO8G2tvWM7KjOcUfcgb7XNuI/zHEUiv/BwMgEZCeSNw6cSB
KyroXpZ8y6pRNtfQTvGUsJJT3C4n8pyOwZLQzZnWUOUtq9qwMIbTa4oeVxckl+wEXO3lUqDTtFks
IwR4qhiyx0G6JbYMJG96d0MbnI223ObiKoPnK4DpTgV3iMoBPSIGIU8irThofTSncU4wPhnIy/JW
lTaqqHNtypGUKOhAVUEXOxDKLgq0Ks8TC8JT2v1cfCdpV5O7qz+chDPTHc5hROXf+3UaCIylhdZL
SwSSWBnTf0q+Z1Rtpkc3tzpVv5r6Yf64S3Z0l1LZGqWDp6S5SVPco3hPDxZhTK+IsJABij0qgSRY
Z8fNOkT4HjbphwTfOtzzzCQwPcGMaquLzl0KySNhSQm2UFY2EOKffUT9Md59lwq3kFTjl1LFsden
IIqyvlcbtUf0VkF3R+zCSc7La/PGrRyRy7p7POpCNzbhWuqAnEYWcdY2XIakhzv06dnKxTpMVT3S
8EF8GaVy5ZKcUx7ffQD47o58k5+wuSEnB9bcoe+ffzdskwW4q1e9eMcFc8C/nnAgUJz0+Y5d+wrJ
fSl1d6dPKvdTqEANJrMRBTyA/Rml6GsOdG8xvRyO9CS5Slkl9XJBALfGGhKEFC7K2BkMz8SJs8ZZ
q7N46hJZa75c9drzII6Qte+K0jjwG80itbrB/A/R3P89Ips4S8XpYZl+0MSS6/BGV38R4ydTV2hn
AiRwMyF+YoSP1pyVxRhrquKM7B3lgmRQF+t3poHh0xPhtNJpTSnHcSZViTwxQvRQWzWkpJeWuD4e
/z+QGwW35uQhg2gJlE54clv2yITaER8BXyAUiMi0aS79+l/V66gA0fMHCze/JuFfFEjDycHWcVfO
52ha1Haa6h80TRIOhcaR6YlJoo0fgrROHYZEufbEu+Luwmiu3FNBkAQICjZFV30LqvqNFVMKWUND
JaX5zVY/oUMzkCQeXiUUNtldzwgxEduaQ5pdHppWovUlW6KVmt1R9088rtwtYkzfANfOnF9G674F
tNohFZaoIf8q7pcZQKs08E0rPxMrrbQyFkh28u3Hdq86YdHbQ3qQrRX69qfG6c7GrJwDETEO2kNK
OnBRFzdUFBuN/p/poriwcOuEqne0PXX5thwACZC4c3suIWAQ/hrUM9zfO6Fr3dmyV4L3j2YrDoKN
34C2tD73Ttvf6crxTuU4zHapE+PBcPNbFr6JB3civFy7Ol+LYo+bRbFux8iMg8Hlcd7UhqWBgUVc
232GG66qKSL3C4uTn0o8Q1Pc+KdqhkdLwshqg/0NTCXS2w7OTexr8g0XjaooamL6WarZ4m2Wxxnk
gL28sSh/6kVg6pYpzqZigDaJQmQ4tS1sxGaF2V0MgwmnpEHCsBR8qPnOzfnNZEUdnPrFpvqfQFiX
F5+BjfAX4h1ZPdYs6nGX89vWQ/2DVm/kPBX04x332ZaMN6r0xKyj3/R7Rg6k+ynKZvzUNkrnGxKc
Apcf4TBy1D+3Hjc5jcM2ci8EiLVkF97XeOAJNmk1Whp/Aw4/TfC5t5P0yOur/ptDjpNDsgF7TLZ5
nXsqoSK8sNRZGcvN8hbFc96gPg80M1J5C7SXg0XIiWawzVYxx1OPiH7TmOr1bKSXlXg7VnqiR36a
pYxpkIDU6Ghnaq2tXvBS6QqRCHz8dk1pUoA7jaQAUOs55uITQmSckb9m4MI8S3v5FLCzQxhuNgDd
1vyHPKEenAbTU2nopwZqi5/k9X/BnM5+eIYBrAcQVxpm7lOUa/BsxgisK86sR/gg+I88uePNw9wr
1JVzMqp3AcvBVJoNre57hrpfrGSxgQHtS90F+xGArGPChtCozcUd3mhuY1mry1ayCXLbhUhUCBG6
Pnplh0sDpZ3JcY3L6kkJMILjnYuJv5+VFwK2W87Lfd2iOw212cxXSi9R5C9DVrX5JLyp+KNXuYcF
8wd/v4G5bbOIYhDvT9t+weZxAPxX9UqWVOLjQuVjkLXWSfFk4sODWjvOL5B1aSgKNgocE400qZuS
rZXgATl0GYaYatmEHgW5wk6vG/k2NRaDShh4QJpveJeEE7VyB9uyI+ldwTzabva7RXI1Jm/suqNa
t20uGLH8P0nrOajyQTPdmTwy12mMayvU7HPrOcaDn6WFo9z7pfYiHUYF0IwUWFtKc61WW6dZxf/K
O/2fn/E15dtvXTrvjuhExZGc5pCG3xTTom8PV1t8QIj8I8PvamDCbMEzLcWePma7ypSQ6gxPh1hW
OETY75CDpHLvB1mDd+cPuIbJGvM7UNtCaPzkmAATFaWyn6Kdh9w1JZQgINvTJI6Gei+HCCvVrsHY
ushHxs3lgb9zKPeNTpa0Nzb4kfNJ9aZPQgQ90MIi1vsbDP8UtIJj/JN9mn8deEwY7+N9UAcYslIP
hmFBiBPWNJSuqy+BlT2VZAHZOa5Likw6l51EL1T6ly2EXoXCdxK0StVNFRCflJXH5tDykCbtiFyD
UfaNnre5sVRrjQ/QKTStoZjSJ6Rw4FCStLZtSM3HEol8SULwLabhpW6M+Q6j6Wee9tMfJsbZAPf7
s9Sbv1lK+M3n9nFV+AWyC11P2kpMkV4LF0QgiPGhEJk15lEIOKOow6RyodL4oz/VcvsaDlyto27H
Q/fYd7wXydGCq0p/y+zhEGTtI2oMtJUgfmJ2K96ngQoPcDnmuJwGYJiRinp6Miu5m2RehEvvzi66
G2IJ//W9LiONSPhxAFkOrD7f81KVyj2NqNYIbysvU8YmwK2WCCJRPdPSaXdwyutA0puSdsupkwOm
/dzBm8Mla3ThpDAWApagWcbYMNajsfQdkMIF3msPRHGjjZI0lvDp/byCCW4T/PUB6gGqsbSHZeUl
TuKapC6ZZyqkUVjcGP3VO+umLnWlhDzoWnhz6bHVwVGws0S3/dqdkUF2YcfTcgtUXXM4LBaa61d3
AWBjQHJGS1ejpSm+Sh3QfYEAn3po7fPfYkIrzl7aSnFXieGEy6fTmDVdo3ftE/A/LCM4HiXZWjVh
Luw5V5BFFK1pH/7ql8lYdRco0jbOvSzQ7zuMIl259liPy2b4stenfGNnmU12Y81Z2XPNVw9uQ7Cb
tflEjQrQ/zBx3dYrozJU54wpevva6n+PIPux5/Z8Vrx14FvdXU0es/bXEAahS30w3liSQilArrtw
SqbRt+H6dycMbok/mBj+I1zvr5HjnBlNK4r3ncd4y9uqbc8IXjGsYTC5Dd0I8yG03cHra2/eYXBz
H7nVN9Exl94+q3+Zt6vxkzLRR9gjt6lACdkH4G1xI4Y6VqQUJSroVpF0zUU47NTvm4j2s6pb4wKy
Jzq3QX/8pe6FzOaARdENcXcc1BSWzaiPuEcVmF7QIqbvn62Xmqk73ZLv/0oSI3npPY8xDAsN64bI
x4Px8wRA3QZX4Ox4/5oGjDjaC7u0HaPiY1MLNaFcj8jvDRB+OZfQ6IjbtVFBjvluOW1aGSLHu1ak
I6KIq6BibhCU+OJJGyjrd5HDKENDIV8LY3qUhvI22RL00UJ+6/T/u45epAtRGCykb07jnPcbzM1Z
cfi7Vf87lXJLProKSCQjBrQ9aD04laQN4MDaB5fpyD18Lb24zaqleloPMtgj1wQ4Yp2yCDP4lwGu
QpKT1pAGacPtcrXJBLaVsVqzWSyVyYcViAPLDeGXgNv0mor4lMOwdvrExG+fPNNSA9mOFVzbJZDm
znOcehEuEQz3/d4laO4f05/ZIE8OO/xwIR1B70ArLwJTA6Z1+m5m6YXB53XU6goCd7SjcO31s28w
JNXH1D8zR+kdq3RG/WCiMl7pOn2OC7CyIafojm7dyEWF6oBp8qaolxMuUoZJf1vMp0kZD3d96UkZ
m/Auz2LCzUimxF5+JxRIcsLO75yHw+GxD8a5fTI0t/NrkPTla21bhZgfKlg34fYlT5aEzYjIpG/3
rtseaPIGAGeV4uuxo7ZevUhNT2esaIhERNYhG4tbHwOmJGiK2YyBMKdTGWUDxVr8xfEwU544nK0L
+BvGJD6sgMSz+MPG8I6fXuHHm41NU7I4MoCyCIW+otyG5IVvxdwobf4bHPC5oId3FBZB+oUAieyZ
M8U8tfen9pbv0U0eSqbZO40HsXbB9xqUAVTm6GUHBjmnj3n7ljt1YWx0bRubzGq0Qyc+DgF0V1UO
5J9roPhwxVCmn/hp2qoGyZub8OTKuadSbc5uKasotfBt+InHamDyFttNLD3BNCdRRyd5NU3SfpE2
68DVVJjTTxgZ5RYae0OYM6qwUBbHgRW3yGQ0fCTMFSBRcoMUz7dm/iViEiMB1r5DaVSlJcqe5ovl
A3suv+LuOZPx4brmTTxhyqeFdhmdWjrxoFMTAQMx5rS6XJJQIwUygttKi8EOLchOPgDWA+za8s7k
7tmmktemUf08alxRFKqSr+g9lZNNgVwcx8W82E0QiAd3wqS6T1NtgP1N2Bnzx/tU8FYKeHGKLh2w
9ODeDxLlUEQgEJHd+qR8pvdWYp+uUlZfBoBnXq86uEmCXAMeTs7dlamlC48VHlzBKuF2y6z21Y2y
TDsS8KGID6hvKTGR0RaGbVOFicqi1cpVwkPh1PbgvmBTM5LQH+qYBpa6L5jz78FbbM8A2bd1iWHP
dJFz9EPf00GWhpyV63+iEHMNUrjC4LhIpfHQy+xnalQo1rpF3HOxX4WiqFoDqocKiAUnkGLJKa5q
mbtXd5gFzSuBX1buAQ+ry+OqB1Jo45Y3aVPXxeEvKia17FXMBbetaj5MDz/DDymTuE1J8Ka1pqTn
ZiY5QVlezpVNd/sHC6UsUlOhwYqTXB1zI4BApMjcoSxQXGchjhMyxpzK+n9A0uj4goP4G7K6TRHE
xM6IOSWIfFN0epiIM50C76YJUrbAhdKassBR8fejZdGIIBIb2LTFVb1o0yiQ6cB5+/3KJdtNxOWO
o2OumfvdVKx52y+blLzgN8oYHQpBgdSdzevhkFwrOL8xHOorikdbNb7rNZ/66njASlNvkIU4QG+/
XZiqlAHHdLEzVRx11jAc2FithFDhpX2f3tgw+e4yMGT09Qr9UvidnKzFg5ih9koQxZY6kxmLOEGD
WpiJ/A8mqSKYHe/kcixaXb2lSi0i0XwscvSmTDMaTsu6/E+C9CX0YyIk7AS5okeqrqLFNRj5XHHa
PJoDUd5bRRC+1EPxRkWZBtZLS/vnK9FrHM54Rs3YWvTL+6crs7NdoZ8i34qgvuTPBUK8BvyvIjQe
PFFiHAMqZpXhh1xtkiI/lrkTjlJo1CtBTncXOBS5CxQeagHIWya0FUAZ0rsvav4Fa02enBtMt51f
/kRHlXAiB1HQFv4JrPyOZDAFeHuNDpxaa38/vBv/MTFtTaRdS3j8i7By1DaTsw27N5iw7b52zTkf
TcjCVhzG+ifIcypATHDF6uzXzPO2EqG4h59ANghIMQxm8gCRYKVoZ6MElPcUwSAwyq8Y81qpg33f
FsqaxaACHp9i0xt6qLTbJFp3gHzI0xIq7gVbBbNfiRYxC3m+a9g2d9cnnJxLIyCw01Fp5IxW18Kr
a52xZKfVraVq24vF+sfq4/pAHvM7zr4FlTAeuD+KJyZnd9ckswEchWZQM8mDACzpwv8yf+elUDuF
t+2nNu6AYfgLVi8huoR7w7XmS52U56D62NhHppp7lC1V8X15BJajElwBxJ5bdiv/DH6MTgWNhq+z
1fKzNbhpj6SMGUs3epwfj75JHRnZYjp4ZN4yO3z1aRzNs4tb5OiCE4sMrQt4YJ9IhWVDetzwtgxl
gpvsmw+StpGD0wjyjFu62f0c2mUw2W0Zpk4+wqmlG73mRbIM/PU/dgkPj/AFx62T4jk5168d0LDm
KjqoNnx26QhQnVJJDZTGbxZneMcDTTQvwdmUBDXE62Bq//FAUE3vEbOBfZjjg+KhuZWJ2b42gyhd
2Ttidqj49zN0h49TLcEU4kdmmFgsHbvZzMVyNww1ztDBmpUUIHZKfMaleYXHk0Q9E/blON2NazrD
zba0R+4zD7nT5lXU2vxEmuJq0Y0ReUIElkdtADxNoHjdVc+uc3XRovT1tGE6xFbwEqlwLS/4Xlhi
xUWTf2p3rOL9RtizjF76xhY2f5fDWSoCozSj2WnwyDQdIpyzX2syuCHAiiUulm3f6YbpNiz9nv05
3HOfvH+Z2R3jtETGK1NrFj+JT6Yy+aSGgRvdLnMF/ZbdOwMAZ8+Nj84VUH3zA44o/2FUI9zIgSNC
dzXf2i54hhZACpfprClcUU4eFwjuUSY2bX7oOrkm/PCsubPMgcF3ysijJm+95iofkltr+Dk0wbzd
OYStNJqJPi7T/k6jX862kyY/eHNIQKt6BG8PBJdbKOO2VU7Dz/Gf11lZ+M6t8c9vzOmkp0Xs/v+K
DGvwI6O6AWOX3SFrA6vso5mrNOEPBJfSzGPu5ph7enzemqoSkwkRU4Y6LDfl3R+Vw9RevF4H3tr3
L9ALRiMAvjf3wTjotO0/fDZmKpVr7pmLCJL4jPl6ntiGMpt2Duvub7lh+aBfGP8uLnn9oiYL0YQB
oiUW4m6Q8pik9nHLn3lj0L9VoddCrqtF0KSMXPC3E75cAqng8jrZFeKfY8QA5RWbUBYCS/yCegNK
n4R1mxwjRufkco3NcJkpNdCRoG3AnTclUUcTbYpAjnrizU5+0yOAm9OjYt4jePvGEZ97wJFgD2bS
0OEJCeaVM5dv+hBPS5eRnc5zgac2YQNwTpZJr10nTnLqxkpSTzeFVoq204o76Mc+wu9LIIbnKnGU
nbmcufjD97ve8Pwoox3Hye4+wAEzL5FHVPzxSWYYkSS+NYM/KFFfRUy6KXllps8P/15dWUUbZag8
bKQ3m8LvXR8hrbPL3TuNrS+nTX4E/B5VUCIvFPw8RDHUWTb5mEsnZs2YpzPhmzouGEV2XSOKzBNd
N4YTBH9HtCzQ9yG9jKX5h/GBzqct0g+YrkdK8LSTa4Qzy9a78hAgdr5lWbAsH1H5jWsdFvN3hEKw
552lw3f+7h9fq3VAzl/hvCFayVRIT+/jnEzjMxot6UCNAKN0LJV6Eju+e/LomP+dbgReD5+lqUfR
637xyPru9NkRmKHdi9qDrVwBo/UvU/nMZJxUVMgPzKzc1cVYvijeiiUnmnNAvK7V9etY1Id4fiQg
i+JwRuSj+eFwOpK6ox20cL+bODUZL24VqkBfoQZieRlYJfwMsrG84+Dl+lKNFGk3eFQZVA9QSlyY
9oOWdO+wAU2ywPEtfBVkasWrJoP1LC+ZEirJi3R/J7LqNyrKqVH+bY+DyyOq9dPiIw660ifnhqJE
ll5URYe+dR0Nogu8p7nF5tKBERMIen4hVS1Vhqa3uqw1LIIuxAzxugaLud+d+DqbFc+iS0D5pfIw
CYvX97rP6dctKCBves9SC7GCPJqQrelauFqbaGuC7NWsGK0TlMeNH0h1nOjf5fF0VeA9OXLkn2+f
c0tN/EnrUjCiT3tzto+M2fQ97gcqp5Gq3BmPJ0FYFmF6cGxCBObDSc4iRzYmd8NC6poJSzJbrONw
wV4ESZKfVAA9SThbXWGA6pKv4OAaRO28IWmOyBYUpAZVA6UEPbRXhYWCwPRRHS9LzJ+2kooXQ9Ff
adD3FH47OZ20tthMCpUm1X4i0g12iqoPBeKtAKVOKixnLmblqedb2axOKFuB7pwnvwxZPStLIXOV
8W0gZg/3UqI0m9e9lUhjBk5cnrEsROGinSfmKE3F6dBBlOLsyPORhjpAZZ8f01U4STdQPEWd5VTc
7J7pejiymQJrBSip+cPrP71FqNlhjG9NGSMmGRic+vFobcYxelzbm8rzxqC8slBSB8ZmzxcuBYt4
bLpk+3NA+YgceO9qq/N9dJiRj+TN49/7H+4qI2qb+Y5aLK1Hkvw5DNSNeW+hQCmBJ6w+InSR+grS
LzgYRYl/iSwQUxIzXNmXvA/qa/LphYpXUa0h0FLO2tC8Wd+eEVEFCEB8bjUJo31Gz272Yi2wd52R
f6AwttJpwBkKVi0f4a2nsfP7lrgi9vAoa3goNoVSHx0HDBB6qNOiQPlDB3YntBQ+NXqX2ZRg3H52
mr5rBmkjET3zglSMkzPTTPY0/VgCq1PKeDaAaj/td5i0O7rggWpU/vd0CqqC9IAGUpFqubuewska
z9L18Bd5FpEePIUXnHA3Hk3knAttTbFyz5VU6w24ZPu615gl1GA7+KPIr/4ExBQpmoDBuNuflBN5
vwJT6sve93mZrmArGSptyAWomQaV/xgkhwglpCEab6mUho46pvL3f7KXH7EP5+/BPlLfQ9uwMJl2
UVEW3ePDDOiiQfSg4SnnSri/puuv+VLC1mQ8NyqUJ7zTqDSl5GPIrr+cE4tDgspkXnr+CnL71Miz
DpPRmxvJ1slD02Kw0gh/fONekAnSeX8PLXc7NSCB6ESnPO4FT2X/XYX+/GjQiuNBxkTFi1k6h1gr
WIf1XxqyinCFeVmrtACnTygC0w5KvBcug4DUHG/j7ALP8BIZitUiD9FlPGM7MsNEskhgJCVt8foO
hQt+CZpjawu9I1l6xhDgc1O3vg5JOf/wtmn88bZBbq/kjs6QgUovXQtVaspgryicPqF52TxWQ9I+
EO5Nq1PJd8UO+hD/HU4xXU2ZqHsYinMruCBel5zk3KhxkUreF4G3YpEHpVSeK7tFOMl49wOrYIZ0
hjSY/EycTP/1FC1KHJmoWqpXiHQrYkthdh734UpUYXhQs9uy92es2ZuEWQK4olFpOXl5kiNWMXJn
q8WTnfit/PVSdcOXZX7ZgCG8oijmS7YQ3WdieibU1DbSzpGghS+cnp5XpNSojNbtwvAkSHUWBpZp
JU6HC77NntW/DFSloxrniGVzA4nCtuWBVIH/TigyRablKqu/zqVfb45dazehoDpC3AOzWGUKUgXc
bxI7cmlONa1hYnH/D14qPdboEdxeV0BWTZnNFE+cFHINanbBQLLjVoRzN1KFaLSGXENoBOAZ4NYC
/Rm/hVftGWyhK05USOa/1oxfHkeaiPgEhU1F88w0mTo8KlVYq4YmeX0jOgjMrdjMaI2PfTnSkPXa
82STXhxUEYBxueJzoZWkH1rLBu0Vqj67ULrApiCvBAzhEfqol8CVi3QYb7zvYhpFnKomzpvREbzT
2a3NgE7+a9RVbfjs7b85TS7WJymQyseBM5YW56JbPDDsON7smpB7nhfnvCZsH98K4Of0HqYVVku+
WlzgDXCObCaov0MIgbNGNLPrIzYf2Skz3T7pv/uQfgSp0x42EdhVgWJDcXlyFGzbi+IfggWiXEa7
GE/dEzB9YS+uMOJRHNjvTOVwbz7YX+ckW41jokt91Vw7Nn7b39HzlTtAfU/tVP7OiIPXZP+KVs3c
mKT+mdwmoqfd1EJHqs5GKeuPmOP+fs6mden80goHswgRa+r2g/bAgrloTiBcaGFL44GyO4il8OZb
br7x6vhEcIH3cY41DPb6F70kt2G/4Ht3DmPXQK39TktzW9eCF5WS5WFYxZnpPUZGrjHFbacvUZk+
Kvwp8MTkCgAsVvmIXKiCegt4xzJmaMPfUnGE5Z7+OM8vveydEgWf7G/X1PtNinwvZ3Hq+Vfl4VSN
Iphf5W18B+qPGiZAa+H88Anc74MLBvSpJFi7Q1AYvkcbdsDPEz5dqlIaxck2BWUjHFJqb5HJNvwV
wUBCU5eIVushw9TUCACl2NdbLu0HB4QbHAhLNgEt3q9Y0nrQWcu619GgKiwj5Jvpt9G4ZpV2cPtF
xECt+vAp27rix7ycHNT96XallSJXQ8kasWiTNzS0VWKYD0ToswrtYBEYpjq3uhxQJDmeo5o/s6xY
Yhgn63bIvia35PqIvvy6UHXcKsEEsmzF9EAEWGlHoLAbssLrk4iQpeXXawTHLAhzmHKJ2TiY0oSx
A+vtjN5sy3YQ0O9N7woIcF4Mnv2wNUl9oC3qtoJMxoxv3nDpRSprb3hIRBCrXPz7fgocFl2VoV9H
zUt0IdUPnz74Mu6Rmv9wAQFfNaZERuE3vmPaD3xKs9YXgKMEcA04Sw770MkwfEeFap149dMyHzMS
LEfUOOPdIqRhUh9lhQEcVLlvl5tBSsFrCj7/gNkajtOKKPIH8PHwYTqJBovkKYBH+v/TIvYaLBQo
f/CTAw1qyX0rbDo/EbwtGXVYQm6oGboV3druF73iGexkmhwjHUD3DQeAABDT69ztARR6FuzEfS9s
usMPBV+wKb+Xk8xGBQOzcqBnfdOFsJr+VbxuIWzp8/QWkFGLnv+bgbdPyf1k+/zYTcuf+CK8XK4N
w36FYY7Qm4xrutjdwnwFPErypKdgJr/u2qd/tgi+80sWkRFRP8FhZ+TLh/MUQh7ltAmEV4vt8bY+
sS66QoNNF/EhLNn2QhK8t2MoyQjSBLUwIKq1plzsZJvVE0J46x3LGwsaPUZ2snUPuZEsqcp+FK8d
Rdoc7wP1hBmlch+wXNQ5qyvYaAxiH5DHLq1SPng9LtioYKLOMs5/sW84Es8E/rRw6PvPnXL/U6e6
i1yK8drFndoiHxCrltN5+FWRsz8N+p44b0cQPZ6lv4lR5U5g42DCV7/qgz2QkgeaQ1YU4AD0ezN0
5zAbLPHc8c+SU5CPlfrC6owX91L5rmZPC5D60Zq3f96IHz+HRPBMVk97N/Ka0Nj4amceH/uEwvHF
6kQPWbfmKliOmtMBsgTryvRu4eFtM7iBS5Xvhi9PsjTTutAqvoXBKP2VhEZY8jCw2WqmskG18vko
iViSt9l5pr4mAMB8Hp8h+UpQFtYeOuo3/lSy+0YEh4DY+lOceFB6KoeWOdK+edP/0cgT18QmW2Pu
2NYKhlSL6qfWGWmvbhb5gBAD51jtZwPb8kLWuPH/fFYatOwN34WZ/ELoOThkEUNbuLvW4cMWoMEV
icNZybNG7psrRBDE5Vo3ElvG6bd17w/R8Pr41k1LiYLTiQR7CFf9UQiv5z5KLv5AuBXA5+Pnnf7m
KSMSVCtX60Ag8w5JH/svJgKrLbGTJA3hWpm/iBwCxuKHNRgJarlviqzyyW72ql4QjUr5COM5HOT0
UDDRTJZoJxGGruv0DT1DcwIlU8RFgY2l93i6ZFhWLDZnkkCMt4v2k72fHk1+GhI8si70674Zqzjb
QX2mKA+c0jrH597y/wXTMq7hGdRJ9pdLP4OgnxtQaUoomgXzM+6hvzm9bfaGD/zZpGDhDOn7Hfds
0p2x2xQQwAdzhNqtlaT02lp3wM2qKQ/irP13fdCEdO2TdUS3tophcECtGhZp2zx8ie/tVyzocmEd
/CQkqaXokRC8DQ9oSBtdcjcxfRyvlnvVK5DZ67NwiKHEBmxRiQNn5DHG1aaHruDShmCTmpnjoPdb
QyBTm7EY2OaNSOJXGFJWlUMsZ8vePviRjYJk2ssRoEJklHEgCIWb6Q4NqrYJBO6VuI7En0IVbXLg
UHK/0k+c1r7hMeLD/AmLsCUcwGhZvUtJiAKA9Og/kmEEALVgZV4604m89RZzIocLb4+2peXynifi
0wjlY33oj2if4R8vCc8Csup+LfnxVmCPMHTAF/F3pRPDuOqRrLNMAVNT1CIWj6vCQJ7qPxenRbjt
LU8TnoUuz3SOEPHdbBrNPI/VDXx8yqz9mKyiYe3mtWtTrMcy2ZB0Lx31cSw3qWgK/u2UozClSU42
IICYt4u8Wn9+Qq0NWWnZvE9ZAgfouGLgkI+fFyePEGxAvd9XhH3YMk9zZDGFDkGZ7N81JyTi4ucZ
FxgEpu0k09F8AH1fflMe205TeZpFJFxNt+FRY4uVl5TliOe5VlMDxQ/14+cY+fFEph463S1aqpOt
JjKDPHeJoUwxkPsza+7v8ONxr/ygwcOg/B1VQl3BKJvD/uf6OqWcM8HQt0QeWQObNd+weMjeqO4s
/2pgHoFSi30qytD5AgJ8nh7EhVLB6bWTuB19ztQOckcB/uzBx9kUmJtJpJqHDrTHymr+ZzuRerBd
oMf2zfkWeatZr9sG0dokLSEK1wWuFjjwQJFWBVQvEYvY7nXr2+ty/C2bJ26g2z7GmqRIC4iFFCAD
o7LyhpFAaUd1sZ931Os2wcm5ak6A9XcoNKpwkydHMZP8D5nyt9iTvnTADP+ISxG9UWcXbogN29NC
/MxyxK1DNnqoxv9pW6zFkQFve22nBiA/ltBoTAl971Jb71c18cCr8KCwcX5jGv6F6yWUdSn9HVsJ
gMlcKPvHVtwBW6UYX4DBS4H4CRKRJn/X3o98srj5FXsLFSyX+IId6xOq09ghenxV1TijDovdFFzA
FMfn9AyCCh9kV/FPZHf0I3eb/FpYOn6yBNuqIzbbtGwvYE+Wa73zUI+kVbyFwyTfFlT25Hq3TMP4
xrufaGEwgjlWXXdi0bfS8X04S99PzgX2D5JtzqA142iF8/VAVvYCICBVyWrMkv1lGre2+pbE4dSs
15usNZG+4ORSdOHqbR1CVASoh3+dozCO3C6/ZYWaspuzf3Dnmr+uqPDyYnB4VvrfVoihnjRJdF7Q
+kt9KRledNgIWQnkFB90wq0BcUPQyZyQf5Zise5MV+0Pqw08OJ7zprmJ5xcfKw7tLEnN3lA4Dc5g
QPisUcZC9DqytwXN+AY+HACbMbRKL0aKfFNClm5r3hWDh3PU19SlQkO3solT5+kr9tWSGAC5XfzQ
SsxLz5gdgnWP+X2r4XyKekgdN70hpcMcyA+IX93wDNgFoeXbHq9Qw9If5dxdgNK2UgrJfPkSKAnM
aDxCQQMpgoWdcCTKtgM5T/LBFwJ9HmZ5dD+D3wrIGVP54wrIfYsI1MrbZbOjqGJuT/dUOOwT5KXX
jXaYspQKHRkMCJA8wpNlW765PnBambeIwhMPmzE83zffY6a4RzWAhqw6LVGIcmvd6zgWdqQjYpLt
TV6sF5BcSYL7MBNlKEJRI6C/0GuBcnAFmlZmCutMkQFxNIaWgM66OJPyq8lDG50uM+mokWhz0mKg
AnT4t/avBAel9ly1SpATGQ7MAeaKcDAgrSPna8Ta2Be4IbNB3YLwt9v4kWKD0YW+f+zf+6Px+8xw
nV5PGYc94Rg5o6UoHAJrpFaNVYxAL0hV93p+qw/nmGvECTv35++p378XDammizVAWDGO2MmsnrvE
jq+07i8FvTWR9waaeJU/IEUgfetUazquxUmQQwThg08eK0IpKlkXkMguxWpP9R8fXhNcH9WHl4qM
Bz7c+UkJ/gW4UvQK6zkYLWA097hYsEpmAO0Vku0LDXsIY6B7QKot4IbZohGECV+vKV5nT4bV1jJr
n8Gp+0vIZrfFXgh+edEOKxNSiQplmsfFUxUAz5P1UchdmY9q6+KBisTp6+YechJjsA2EFXMDziBx
cF0trxx6Eb5ZQ7g1McVND0ToUEZxLdHHrEWTj+CQYQrd4ndmne0ISXCdrh33RG6Bk3MswWNl2DSS
BehVT1cxOdoonmv1QBcMdzX0PGCU4WaE8/w4vumA2NnLL93ZpJRLfZzwMoZxOIJEkiz+GcXDh62g
E5npFUWEwDLRDcvbnqRuaazQL/BSfb/B79c9ot6C8h23G+iKDiKmGA1fwpYHBnx/hwiKXyNjQ+o7
eMJi6G9/yTQWgpOYWGKkHE/hVoO+EBiqr3as9NUYZuMHKsmHeKE5psJzmRlFy0YkJADp7UaJvLZf
fweBOgIA83Zzu9kliGn1ANlPi3K3/Cj8fjQKJi+usJ+2Io9pV9leXLikAF+/rCFN6vV38wsXAZ6t
vZEZ0hhxKtmerezUnhgZR1p66cqJQBQIYxU1/+qG/qHY7ptq6G1jCHKyGnMpjn/mquHjgAjD8ktz
COZwvoUgpw/AVs6WHywAoeEjsyqbE8i25rqaBTg96/lMi07+Cztg+5Qo9sDKnDz/B6WtX5CRodhZ
QnW1GjDVchLSF+2b7p8JFwo9C7cu19P17ddzoTb9nUALRYR10N5GgEjpUdRofjNQ+tLBdSeYGvzi
MF1bDeF63JEUT5oxP75lKEv5coaWARIzPh+rjDDYefDs/58L79Y6e59hFAyoVjIJ2Httul7EMQ+o
kQ4NmsWsKy14/kWVA2SCzQaQ4atrD3vnCNFnBJkkYlyDUGOR+9v6XRd+TXOWVXK94tQPSgvSEmbY
FIB6YXARiX5orPWMqf0WCBMw/yhJpQFTHtc1rdcYBKVUM73YAgTrpEIcyw/HGMIekhVvV1LJwS3P
YacQ/pBUqFyoYMsMqEnqvzKJ0Ib8LUR7PDb2i9nFzaycMq5HsfhNaKbQqTmyfnLLGbIIS/C1BnbY
iJJkdCOzEeuWi6elRwJIFtSVoz7p0hq9Sb+Q/od9BrNDIi4tOMEow+iPSoHwv5+uW+bnMbPSDbB9
K/LZ96DjWH//Fo+Ze4DHkA4a7rR0iYOTe63bWvHK4hJ/uBld84QqSiGy3iYaZMb2HJ9+SlbmXXcl
SoYPerSne8IB3nQ0KcbOCTox1LknpIRMxKgNCV7/bzn2v6nO0+p7fCHJTcKMjELooJVP9/ddE8/g
LLr/NiciyG3V/r8VW1b7eMquCu5GRnHzE+VIE49Yd8iwZeFIsd3XWAQv/w6wtgGdVRt4mvQToGZy
rSMqM3+48bNf+qsZ6M6P2b6r6S1kUpToCJ7ICmDjGIaYO1Jz43G7A3tWNe+MW1K8emzjj/qAcADp
cvDMxR2sDbPOQn22mKpT7DRKzjT6ZPp9cbGAkGdvXbPfomJrWX8PWtAT/FwDCSVZIPLdAK4kMGy/
+2Zm/5iIGQ0pFhlsDozIfXL6HFh0dnCZluDd1mF8/4vVHhg9A2k0fCszz3cwE96dABK1PRTcIJUT
k2a6/kNB5aOyAIZLFlnUp/viLZnwpEBOhdyeN5fiCEq5WwiAhOYcWj5xv9sJwOigZDJwk9f9wiX2
wgA+Df288AuCKK2rg77GuU1nO1tvYbD/K9hGRx0mL6wPtbHnFiI8855Gv4JhkbpfDYS3ujkJJOht
vY2O2xZSHWCYrOReSaL1sg7ct1erwgwv0z5UCYNX31REOPj4QR3pc1aa1Dqtemo7gAv0S3+v4NKH
e/m9zAfslcAtZ6iomQqDXkOldg5FVKg9MNA2iH3oSDfCl7a5mxA4Y7XbJy1gKFReKKAgTu8B3He0
185Th4tSsdfKhzisaWCU+VNHN3xYBM/pLNdqZvvlGtsVq/6bQNDkVaGftUohHOoI4uBL0QHbToDy
UiXmYSSPcJIK0XAN/tjAzfTh3HbW7vMUPyqzpCs83qOoHYE1nuRy3nB6NSewgXyJVsNCFnGGBzRX
I182C3no3sApBTQNG5piDyzcenikuiFvtxELbkfGR0IDy/zJ+A0D+uCZkZdZalvoLciS8URHtsa3
ZFQAVXfqJehzbYAvAwBiz62EJ2y76CGHMMjjIo2e4rjFV0wlxN0xKX2g2WHNGnYkj6JN9q04XtJW
SC8lbIPreyoCroeod6hxSrH0vOar8NjhQkozy28Dxa0pKgQnCPZayr3qVpCHhrKCci9nLTie+HEX
n7+f/pPJmOoXCQ+4RC/dDxgzBN7oSqc/BL7d5g7k1/P2OZLTex7pAofgr7zA1BUOqWSXCkdeC9PV
WCMSNHqQptZCfqzF41nqfwRxOSn8XTQnK0K/GFPnsvVDQsm8N9ngsljJMa5Y7tkhxyCM4/B3Pu30
ptNywa3LQPE7TzomABGKWUdAZwdHPj6pa3eaRGDftvYESTqVCL4EM7xv+JEfIJtTy5qGspB09U3V
SIGIMSPfSw3qv1lo3FNVyK6XApbBc8PLgb3Pz7wwz7qfhgrej9P901bSY9W1rl6Al6oDJrp4nNd3
cDlqQIV/DmvnE8ZDnBs0iKUeCF0JrGkntqeUX/ntNAkggoncQPqGbPitxwDfF9Pixojgba7BQcEo
uzU7WLCgtdyfStqpbyYhe9Bj1mcV3R4gMnjK2oTZ39X43tdf4hTWyHC0miTeaD6PYz1UeSzat+JN
rMY04tiYP5SQ4FYjKo+9OxyGkDXcd5c8adBXb4uo3tCqyX9cYbOABw89brG18lMSb0Rtjjx8YkTO
/kQ5G1/PK1EgaTCQSzcuaOJp6pusMX7H/3bdKgGCiskCKBMxoEWqtGCyfQVGRHCkVVcCd98ICaPc
aU9ENxdm0kOT8MGdeATw3BiADfbRRrVQ89DVBzwnSwycxR8uamVADw9XdkZYiqMv5CzvI+8qwPnP
8v6346kgJP9B6IMbPLh7uILFWJIf6mMMN+I20xIUgXJiw551Apn4ZBiTbroPEsBjdsIpvI/UVknP
t/mnd90VE2tt/TTHLz0Evc/d38B7OkGHbJefkYLLRaRrSIMgNfMr33iF37QqNXzhPpcOQMATs8cd
z5bGSex3nws0WKg//sJjzOk0EgM4LJmpopJPUzX+JbT/13pAfjM2CTB9BbXPu0xTPCId3M7ZOkym
RZncBH/8d+o9jBCIaO6Pg7pekl9b7rK0xs27UIhO0EJXXdomXt+WkS9gGz61KOhqM0bDcZ04aRV6
3bm96BXSMcbUUCvoRkFfZUwpPighhRu1EmrXCqyA1nJaWBg+o8IRAW7ihq1XI4rrBue08WSEpPHA
br1a2m4zudOh8m6NUZsAdwpxUSAOP0xdholynlBtIaA/iJNecSlWHS1YpoyUq8uYiXJV3pMy8rX6
tn14ir7fOp/r+1IvciDoK98SW8/apzrjxahOqkcgdtgLB7dS4yzr3p9/Se9dx3OREfWU8noqN3ur
UwGcJ/BMkpnh4kWDvEEOk6mGhiKdBB+6ZT+yOM3cw1Szj8Qnaz3ZLeCg8dO0bBpdWgue3KSBprob
lbBGLyubhD8WKhEIzzXSliDmNKw/aXKMw4GYi/JIU/cqky6A3lwy0j14Fja9iPUUjxyICsS8SIup
aSoXqHtMG2MaFb6aECSu+N55lIiQNlqQwgApcRPOOF/L5j8stv15KiYiXS5WfRpWkII365uxBzMl
djJVqGIQQH3crQEuwYf12ex0D6GEj8TdditN4R/Sl266MBLxFZ3a5FpaEoLXux1Rl4cXKTnBA2TE
FpPHqv8Cjr/9TrIIGU9rVtXvaAXhwTxncn1fnmmQLh6nwPYU+Q0GwUtp9rHSc2+1BhWU1JuVr6pc
cKXYsuLJv07f0QYGHCoID26AdB8WWKYArTaxkRLZSyvbcF+FmQTRoUU10HQm3SNaUR1hBt9snnMW
OiFuycjrTGwrOF2qHr/JsPYu5ye1wPOVIHsovogBCul+Krn9qRmFCgiIl68JX3feOeinFRl+R8B7
5dDwnYk6ShkI49uGvsx23H60eyfVkqqtmDKP4o4rtDXXRcgdWY99iC5Bizv08ik4opvM3LDWvh/G
iS4LGU9zZtgI8scRW5L73tjSLSzVhfk74leb/ABK5O5hmJRvx01Utt5tfWOddIutJMwoEP7jTCmE
mpYnHPTaMzAiRXY6lU/jx9XdNHjsc31lGmQ8KEf3HY61twHvqKj4S6qOBhl8Q64GXHI6+tQfosDq
pSKZbXfnaU9PfPIlw44eEYoLTpV2EAr0vdliaR6HCGZO5EMFWDUZfLcknhRe8prBmln8Kp/89Buq
tUpLA9+3PjApVHmpAB5EExtG8o1k21Cd9pVhploV4ESVDk+colUA4aPWfb1wzXU8vkJTPCr2Zl/S
Z2h6FLkARFpXaMSikLZHwtuwslAMoUezLkS8GvSizgRPA/9EBw9P/DdB61d5oIYuOsz5hsXZi4GO
p3yYrt9M05TnBxY3f33ftRr54Myjj5ylkfzbn6W6EWra1mYIbSfjWANS6lQOrXcOutXAw3SW1PIp
PHUaMW3TvjYjYAJOf2WdBvCaHvGNgXJ30V651s+bcjR4Kl2NtU92MsVX/Jbq3GAl7Q9qRbtd5TiV
NoQ07GuPwO8Jm9VqK1HQlnOAHdPjGQkwCbVr19ILq2K5PWphHNmc60+/eBrCyTy6wlCAkN8dKHkD
bPMvKJ+64JbvN3HYxu7kNLQYLw845OAMSxhPjtIXQV+/Z9pZe+UqVcjOxNaLflobEE+pUi1KLMV+
HJ3Iwqu0siUK1Bk9e4AGeEDTfNQ7Ih3qbqw5J0iMu7RGo//YDnufDioZKW/cJREItGkZXfKzLqAo
lvnmUg9Q+nDf6YhRNFAxQz0FEZKnbZfsXqAXYi2giFgjIxNsd0yfNI8YayE63pvjKf/UBNw4ti9b
K/iH4pGeVfE1NH4TPFCBdRG1+fQafmFgVOhMXQp5I3tl0F8RunQDi7TJxId4QsILceScs60KzAUB
twB2p4OVIajEZ5jnpxgZ5ao4yb8MAmPfUn3zX0zO86gJn/p+OB0NZtqCkXJU/Kyz8k9cBH0qHbYt
iB/pbNpkD859QNpjKw4wPl/LCfNQfR1GOUAZJJbLUsi2dukRo0ctV9XBi9CfNvYcnuy6xEtOylIh
GX8PigI5gvPxFAM0glauvoiYjcFU4155velqzonshMKi81tkNBieB7QyfiJo0Av3xRICFj9sohvH
abc/E/Ki5fCZdDCMsDipgN6tpf4u9Lf5tBEldugEOtqDHyLoh+Bp4cW5mFKFL+N932wzhwZlGJky
GR3fM4zSvJU3hV7pIontclNLhOch5gZalICtAl7LAzWaGh495qIFB2mYtwK2erTEI5GnIX1bZS+q
OPRpFlbRtiUdrbqtpv2frckrCWZGMCOh4xmwh8l1jmF3SQpg18AimXRel93oSiCcTXWSqHJKn5TP
MMk3LK7tYqA/BUAX8cQBo/A9YR7piptTkq4N3CkyzYAkGW6W9XOy9FUtPh2N26e3aBjFYP5E3PSI
zE9kd7FHZ/XulG2tWemSNHuK8gQryP0LqBONaiodP0C9REeriGpDwhm+0KVZEp1UblK/j6q3PWlC
HcbINXcGkOWoxC5DhYw29PqBdUGtxk0MelIWJnTa9vxXHEJg8sSKLqgk0GPjKlWd31KiLZzMduge
NRxsoneLKXZnXeneJkTm5EwYL6ZCV930i4Gx4rCvXhEvmgHHDBKetnb+j+kD3jaRMveFbszbpNry
4d2ZdYSZGXUszSZ4kMpnwA1nRd/EAXIZHIhUnGRFdnznu0bQlydxQb6rUgqSt5IRZmXYvMYcg+5j
558cP8TTdv2HT1do60kXW/G+bh/O3A0oiUJtDh1amxAbIP5215PLCFKPdXh/R4stf4de8BzJO5EP
g4dVMbVAyPpqTxInTmljQM7skmjTnoAZIFTkdq31IL7V3+fTSDy1MYeY1B7JpbJTlLW1vP6v5MdK
//z2gsX2BuINA2liQ3/c6aET5E5Igtq2VwjbakbfsedD8BHdRD2q3zSF+Vr1gGylL29joLVvB3rB
jl0ruIG9eeFEgOXvPDQufTqzkhZb9zi2PYoV0vEF7LUufNs7/u+8fxi+bXDfwxUwcHsQZajMdQ/g
YqMc4lnWC5R9tmYSmzUy9MjYXXHgl3tsBwESstHwIBjoaSIwe3ja//rCsRABDv6oQRWS2RV4GP1e
BQm1iZZ9tIvE95Jf3Zhw2lsjDH45iI5P1WLJF1YYkTWjJ9qY8ZH7GQliZwG+4j5hq4jNWyg0B2e6
jcOYF3CggKlhBq0axZZsLKGYoS3JbMhvWSU65mwZf8thz2gOm5/qFbjGkkd3Mx5iITCkdxuGDUpc
60hkFwCaRCKc/imbfv5KS4ZTJ60uuSt5C2ntfk91Sc8Pof/YXMSUFtg3RV0xpdxBmN6TObgVnRAa
bPDneK6GLUR+YmY4JE3F0RIIzIHVSLwPpxoVkBIhUeXCapXvyfQN+tr9vRPB19tkkgSlAOC3gLjO
OahM6ISgYMmr0X3WBXEw0YGp2vJYwIKfJiCbbzrZ1PpYYZMOaYXaVR6x4TH1zIZajNeTlRSHOTeE
6xdGtd0CJrlfapVBoZsE6Sb/90VQYoRHoewMoC8Z2PzvUd55Ews0mRq6lTWri1e7VqNVwL19Z+H2
kSQvWH4pzHt2XLaCIBvGIHMMMG0k/zGKAGY6ChNZkMoKYTMsQTUBzFdFjLfGaYPSiJo2nOThkPyQ
bcWvdNnA8WrkaxHdIANDIyP0qFQdMjgtng6QxWJk/HmDgowDe1YptnzpEosXQNmDSQqSSlVd2GD5
Qzxby16QOIt82BSlt078xC5pNPz+E36AUnCjrgYJoRUbGvmBlu8cWLjYtRpVe2SIy8w5KwYJ4Wc1
g/9ht7RPHtn0j7yrokKbGNGBTl5IJUkvrzzHWDdHu3xKqJlvRYYZjwL9YrGri2GnFRnoH4/41o6M
Ll+B6RchgbuRp6dutx2rX5Go5bpEZ76iQ63Kzb2OFAdYs5xZio8+6DKYRN14DalDkOdItcdsrr1I
ShmEzgL/WDtEVSfTJm5KpWMYzmp1W46X/DOFeBaQ47Dzazr6LxDfpbo/Jah4qMubx0C4Lk44qHQ1
FGK6afi9fGNqE3ygBv7BUihzLr+sXRg06yFjJEh5KNYDlVp/p4z+uULwIJ6IcX9GwPg4b3MHGRcD
ALRiwEIH/xX4LW28ld/S6ucRVSMZ1DCRV5Wns3LdRc9rPy3JE+FU4U126BFKNolxWH4h64GZVy2Z
ZdX5eZtiae5fBJp1xdSoV1L8oX87hF0rk3gBAna7BGczBtJ8gstlfvaSbqImBShsIN13Egh0O+JH
Wf3Th7NpTVxhrj19R9aVGOEJUfDGZRCb4Ro0TxYvkQntFEhA11kLZ4M2lfiUnLfrWp6cYPhnznZx
elPEUKljo8nbxIr9r19TymLwgO3FCL2KsgEvFltL3tWDRTil5WJXCVMhSNVW6fsWlBdbZnwL/S+M
5fthyzbuapa9xsr2iR6kfayb70sAbyK5MAT32KsuOigvwPTcdCQcXhYU9bJFYt5cl8qPO4M2/M1l
Z6dpkAz5MsZVBJslD3ECXnAUe5C8jFQVXdLOU6CIRCC8feWVMcqmH185lC2XarkYuEqh3rvZmD/3
WUVRi2flfFTJGGKR8IhCIhc+KlEvgBXgc7+oEamjSLTEc/sHuemDPprlMhODmlvZVlqOQC8XmtWq
dz1Z9DmVdswADajwJNOfdPNpUsRAN8voT5l/hCgy5QQ8SYcWZE8PO9h/QjEtGQWsSq7ihEt0waTB
8A6p36qJ0uf9jE6XmqzfAKk13OEUuVoAAvo3p4xcByvPm/NF8PE8c2E1pM02k9g7/pvfNfhhdWZo
Tn0fiwN7/urCPuDDU+p5MSdNhd2xURNgDrelD9ozUS0nRym9iQ9fiQXfMFem6Llwna0x8T7B2MXN
TUg0uByflkAdtPmEVM6FiFJNDZNcelc1hK0LDIlipaod/07usDFK6+j4kut2y+Um8aYL7Du7x5bg
7QPkA8LTB7LaXiBKPrbs3F7y+LRMorFCgIe0hDUdzvDu45VJAAg/Wcu2tT3WRIQpXcXO84nhr72f
6+Uvg/2dTnNh9MXPJLvqKY50MfC0Chxtwy7v36pwUBMOzkRIQft80+qXscIr27ZPq9oP3RH4RmUv
Pp5UFyi4jYEdp4gjt3O/4royGGTL8AAAXRda+e0WTSpSIFiYAZC+depCZbFbWaoz25sW86xk8/Nh
6ItEPuKTeAP81oVylRwdJBxt0On5XvdL++u3V9/FtbGKPBjzdZK3pAmP7O4TgCObeMEvVIfg7WfA
4pjKW4+D4lv/kQdX941BuVfy7+Oz5oAvTj0YPoIL4tox0WI2MhlDgMgRL6wQzvie1z+Yhcl8FO0N
o42VSXwf/jjMETnM3BrMsBV8+EYqA9TVTKbhxkNJzLD5OogbD/sa/DRZsKVdN9/WL13s2nVlVjlr
e3SxqASxxdvR6jgi8TCcPXDLh4zh7sz69Jm+E3jWaBhlpPNrKjcObSzY291PPusT9Qb7aQtzGEOv
vTnxySPnOm8jTNriMoFjkJjd+d6o8bydvHfYVQwdWLDFvzekQPnz43EHK3ZYO3oqanPyPtFo/LVk
ko68BmiiwbEf5ijdQnKI3d5snXNuedENCRQlh0t4LwbDaLnL4QFaqz6fZC0nLwaouz2Mk7R5Ddz3
J/gGDgNiiE50ynH0Cvb2MeJUv+1DLl4FyhAGDCypfcAlVZhyiGhLqCcp3LIbFdiZcTFjN15Gnp3s
Izog+22DCFLSNj9J3FcWVxfTz6uXcP7S4K4RjPQ9UVlkFtEEoeie4YpyWVw/r5KO1KbXcfYNu5Ru
qFwoMcuz0CeIU+RYzx12dZhHG+f7G1ijkAVhzQQMJILz2IW7gELeOZo7Gm4BgvfJytX/LHGvPwrg
feYBcpSr3kMy5rPn2XM41ij9++04kYwWMwzo9VBMpW1MaZJBHOmaQuu7MY9hdBXkYNk2kIrDaXjr
jWg3ocqvu0qmw2MxiZjzaJcYC5czUjb5xQ8+L4qXvwwi8ywU6Cz+cmI/YS4FKWWNLYKFt05iEzJy
ajJZP45crg1V1JMMgfSfeLFJLuOhd3lZ5+DzC4mJUlSh+yYYx2uCQh1XOTPs/4A4qIKsNfRqVser
tbl+0UjBvcbbv/lHGfYu4Z81FXjYZF3njTix3cUBX9jWSZ40dOUIuamrvJHaK2J//s24jc5tsen2
RdRNhnmdS5HgQD4y1u0/t/xYYSFq0Syvvys/aGcvVRzGZdknP9ON2aJoaMT6QGjf7im1MVtU6ECk
NyRLXPNV40ZSZ0LJsF0CBodxMA5XBFQZ1OigaIkKPlDvZ9Tldlc5gtpl7J4NCzBSN0WM0+kNhUeJ
jXBAF1k5BY+d+CJyD2aiPO9PfWGu+3RbURyLPg8ZkAqCp9XQGQSBTxvigBE4CGxgdkyUoeLRlgpn
XSe5mZzec0eplwwWvpITe0W9Jh3WC13bqKCGg4GpNKP6uwF+t8RHHKtAerpcXIphF5Ii8R0gjaaS
4LnT4UnZk2oFs7HenyQ9fg9SMOZT6AmgeVZ2FzJVqWbm2z4BSCGzPRTVtEZI17NIKmArlNS3j3Dc
tvQfZI2Sro4CFNkovlj05vSOJSvW2GJmaJVS7aIT/i6IiGf5Z65ExC9IPM8XwSpJxMN/iZrJ+CJY
yjLpx3x2y+yTQ2Y8Gf8ucn4Te0ju/ZnLVBE7IiMWQIW64Q4jicoACkgvPPO96fmVRV30bteVL8SV
ykE4ezYdGaIiF8m4CNsYVmZKCpeAapACmpTgeXXKC8ERbqzkA8fOiQle0MLuzum56TsR9ypMrvrF
wj8nB+BDyyNWvEnIw8qVW0Ym0YYU4GwEIZGz7i/my/TjyUhL6AKBo6hd801BFhRwAX4ZJzx3dAHl
EgvO/J+Dt2+axc1uA8IFwVOZu9w4hvPnqLfdKNDoiK3Oh06JNVVBToovRrmRolRwgZxLqcG44Ov3
NFe7OOgRYD6UqoBgA+pgVNSb60MjtnIX0bztLp76B8isTVtpHHznfY19UDQviV9OTvWv/e5WND7i
qGQh9xeajop0eZbjUpkMNEBD1169woUYDxfJNGpdHkMXcwM8sZ5e1t0SEsi6gWsPk8mktTAYGbKC
qPQ/QKSX8uLwjKV4mxzBMe4hOQzfZSWkJlfT0v7XyHeQXt6/C+2HQV4DhhYd1bz1OVJsRgCfLUp9
5p62+txWnRN+llgIXMvmE6VCkG1V1i7Ba6sQ3eCAUi0UzKz8fP+kilIokP6UjNNvbXi3oC/SNX7+
n9RnwUWY+bXQp6K8p06nX52MbqCce5VDQfGjDynB6ImQWI8wsybH3U2OxVbawlFyE0756fNladeE
+2TLY3JxoZh7H8tOdeOdUkUKLEYdDkuiPG1oI4o9c2ML8kOMtmfer5jjCuTcf7DwkrojW8shx/Vg
4M7qlWHwgcRM5TNx5T0JDxsYmnm4ia7STaj95rxVsvERh8HcUUyCqST+smn0/Cx4hiDNR9p2qdWd
027Iz8185PRg9HpE08Qeujk6S3fyaPteEvJZkgYDQlOcSy2GMSV6Q4lDwCpuhlFYoTCUI5D365ir
4oeWsW03UMqHJAeTbADp4+qHtcJ/R/H+OJcxnRotJFvmV8ZmAZ23jjXNRTODNNJwwPC3bbnfxkSl
tkm0xEmpGNKg1c72eitcAKyNJanre6nY1Tfw2QOxz3HqrshgmHdPlOHQ5alkR2p+VS8pHHyDR2sj
VgInxwNb2svSSXK+bdWto8XOqY7UiUB5NucjXIN1YFkqZx/n6RZC3vmttD5Zs7pT8pqwGWIIpyZH
kG7e/I9XCBB68Mm5q6HmxGhn4INTPMrmxB80fyg03B5MO1tDz7nMOJ5UymqswMI5cSbvSSVnqHP6
l6lZl0omcJq5VgWv+oRsitCQvVk4KUZt4hmHMKJGvIlXK/LVQchYs3NPlaiqo9l7J4OjW8x3pXgi
SZ2OSeXaJ7+8CrI7e42t5oMOztIvF0IH8t8sM/+0V3yA0Dqg94dwW0vfebhE/NrR4+Wa+SQYLZFb
ferKICLOggx5Lmo8DEwyphJONArccdt3H8rmcZUGwE58A9VfRs7JjMRsnX0FTo/h2V2VG6AfojTq
UfB/mGlmzUoAvI3wtd/RrzWm0MYTn2I2W3aU1vMjWUO/E24yp47d1v+gF3jrrvyjicuu6fbPfLr6
D6et6zPkmHuPR51pjCbfh9HZU74rbKC1V2qkbsepyd3eJXpPvpyy26U/y4zbNZ+C+M+VIOOu+ALt
NUOrBtlPXoY1boRBofukwpX6k8tcFP0wYC1/xXQjO1qexs+WiTLg8cH3GhEo43tRhfHDL3PA3Epk
/n0fCioW0rrEi0ZzDlfMJyg52oWRkm71NNnSEo2rj+1xVcNDYpZzC/tqsG3b+r/WEembA/FnqYxX
5enQQqEVixamV7dSrinbp2XkUgwxnCcg5tajAP31vnSjlXrzes5bSva7HBOb4/+C9NVRRYj4GfVN
rDAax7W3/+qCgfFaKgRuIu0pB2kh3guIFtcTvrPwR+2l4wFExWgx7t/j4N0e0V/cSdbNJpBkEmN0
pa3P0t45kYBqGBbRdYk65X/1IdcxEGIXuQ1+yG2DjPMFa5p6ZcR9agz7rQrQaFOULLMao+AFQbri
iD53EfHm88Hclq/VXUwjlRjvCCBSiiV0z7yrR6s1CzCZh34Ik9intbJJMePDrgCuUgD5lLhd/yMK
lbzsJcjkH5lmYo1Wzikn11NTN7Jhr2W7+Xj3C3trOpvxild8DrTL2ECjV9OriZm4eGjln/EMCXVq
FdmM7SyWLma8b3VvoU/DltQsy9IU7zXDUiY6AL/8FF/TY3BdlrrX12quzS/7DwCXlWwMZtgf7NcI
tG2y5Bc/uBCq7mDlWTlTFyodRG6MAt9QpeoCx6Eqr2tXKJ3zd2WILxGKlRVVoVGSjfoJoz8y5K1i
wg19Xb0POjeNs76EZv0G5DxejfeI1+fmhIIOsZbJDhMEftTGW3KeS4Ps9K3aIZvTCjwecKlZ+FbW
0WMOr8Jk8sqM+cYJYev0oFexj5NBe1osvyfdKq0PQL6OO6lxuk+yQz4qouyyXUpJ4bKdx5j/tshH
DJjMbF7gh63eFQD+Zyq1pLevvQq9iYDNC41qjQ/o/OO1u0TnhhXK7fP0gRnWCx9vsBDKgpj7lH2O
xlXx1Wp5KO2BddLUtnoPmOnb3SE8ltw3yDcVJE722atBCMymAlHyOc+rn7eU17W0uYlp717RyE5O
MDt4vJpnkychxnfyOOQn9pKdfabeYx+8K7S1lnS6wMqGeMrpkJXY+l/oguBTHJamFjldO4VyyJwU
gGfZhA16zf3KCZV/2HzOdzd1YTaLvGd2eRXgGdz9qF4Z/7Lk6Rmga62/OQOhNQzn0Ah8iF0XFcr7
iims43o5Daf7tpLfIgu3hpTNo22qWTk5uEjcKFcVWYjMnBnyiFl0X7qlDs/07z/yD/4iiyeQNP32
EOkSSnLDUWXTMsG7QLu+LJYJD+6Wssga7PofxF1xuzYUEt8TulHhTc7hc/2q4e4mJwR0QT2eUoqI
jU49sQHiCEk7idhqNDYHY7t3yMUvErNh53Pws0YTEd+MUfPOwxz00VbzyL8IS0/mmYuqmXN2qNIR
zzLjJm9wEP0VskbEWQ/tAHIaSG9fphrEbUnCHwzETyprFmfOiNF6W2l3rUcp7oqZLIHF48fDKD2m
bOh/34I4Oyfjz1xNl1zeNlx+X6i7vdj+Ww9izbmqtgx9nasVf+/7d2lGwW5xqFUknhPmOTcF5huB
RQJAeaUt0a0L7mpocfpiDID9tP8L3gS4/U4Uy2RrKfuohXKbMsMQHSuhj0+BFkiZAkqYA94m9mQg
yDebW6/DZ064WnQ++xs+BByKtg4V4FNmp6RTc1Szg6IcSCe+nYZdCOE6IaQLZzwJmHAS1RFkx5cE
csXzBjotos4VfO15Qmz2NGEP1la3FnGoZ9eZFka7JQENXjfyP2zV5vrxehQIr61o3bKpRoCCd9F7
MbTRGXuSyHJJPTwStwsSrUdI/3EhRVx+SQD7V+E/1PJUqq/wAxymef/H+8+kGMZ0QTEICLFrj0/E
BWyVjGbukUGrZR8E4rHYk7VeBawBjG0SI/M6Ef3ywulgnPyOM2v7cwXVDb1DF6OP9lf/0WXRXzTa
vniuRlGK0UoDCGQy1GajgXzD8At3i4NVctfXFYnIfklEYwA7BcRd1jY6+ymRV+VQZCYBmRbueuhY
P1s4WT4eham26GmNeoNCZ7PEj18BkTsffcTDZunNheHD+r0/XMMJGLFDhZO0kUiLq0dm76ij2JqQ
gWCLFPvm+i15B7SRt2czkcvQda3PuJoi/UUWBaH4r5fxlMHgfoJR0K4Ow1fngH0GZNmSWJhjp0qN
pM5nYtxR8yd8ajGyAXWqoyluPXgPn7MWTjZx3ZLSokt5boN06VW/5oE9ArP3eX0PlBos1q2VI7Ae
QJx/c8H8uqjOecbaCGefWa0RBAg/64wHjR7ZNC/qlMEOmrv6nP02rYevUQcslExXd8fUu04h+L7n
jFPXQHXgiGNeVV5e5VuOb7SpvBLQUvciJhM8zrThabqY99W4gPUUazlfPmVNKcm8ialK1u0VenBh
qv2dTIeHoTWSD7nAHIboC6JuPoCmj1kGwvXGN0Jm6l4YQFOdIMELiOHoDpeLFRw3eOBVhdsKM2g7
OhsMdJJaER62JPMR7vLFoB+gVjTUW4OSHDo6M2zdpEqIFIzwYkW8VJZ7EJPhAUeAZnrf6T9ieK3U
b9aC5v7B8PFSJOhzu1cz0X4x0nBpJk1ZNcDHvLdgrclbfpyVzV1qLH7RiiI10ZRj/ZV/ERj0fSZ4
uoTINRBhcSzucK73NTqFUXklqPLV6u5lLOzt6FIc1qqrhoe3WhjsiXRrLELKQqDgobMTzxachRw/
A6Zh3g+5R5JOP9BinJlgS3BpBPMSdG42k7IKqjMNkM68pKhF/7KqUO5QulHY/HhbYmJERuQEdIK/
CNP/EDhwEh51nvKMmu2OtJ9usaHjBd1fTuRhpt8arEoLnKhkniAEQpRLQeUEdDRXXfZh6eIPxEsU
QD99rAU0kYintA+rY7i/XUb6k7qk0pTowjr7fUUFY1QYACTDZoI3IMIj+IpgTweI1p4L85I44weU
yDINwpQH2sP/kGF6hRAnAAgX2035ikXZou+N1OzpLy6k3D/TwIdee5uSX3+zXgOuix1qeGvwu6Y/
njhszWdoZDcETd/YO03h0tcGQ9DhHASWHF7/7xLoN8u2RzzcNqp0QQ17QfIr0csqXyfZpMgpFZU6
dAIyNd2ae9lg+lRIxIQEnvrNMBYoA801XRCZDgdlMhAGTm+sF0j/qE/kYmpEKcaMVbe751k2NqCX
9l+jT6pzfNM7hOu1cjl5Vm+yQ9U/9iIYhEJZHFkRzHveOZXg5K7XFYuiFhhzhj56LpWFI3kgm2US
XKvIGkdAYrfGCRoA1bVt3jzTr4V3tTjqqP9IqM4I4/GpuMA9R874oX+XMsvRkj4GjZyJlBKGD35P
gn602eAtdbN91Fy/lu4aoIoFOjEv5UrvUAVvUKvV3scYkDYhZ2VWyOF2FA2+h4Nwdor7pZMLmJ2r
XeJTsFzFiSshaM5AdG5GJZ8yXBk3JgO2CoTNgueMCU9tbunudUs2SF3LMv/jnPXO1d6rLxe0rStf
c0FDrOEtL9A7QPMH4k5J6Bfld05hlD1rEuJS1x5pzY95wNb3bP0nsRWIt6vyiQzqoxGSKLQ7YJsc
qdakiNRdjJvbuqGELwQUIlMSmwtLWdGIJ28UvcpoFc5ywoK52D0G4BpEE+xBVRRB/aARwSIgCQK7
XL0+z2HHzzox5mWkyik7ODroGa02dmytipbK1ckLtW/atOIwU3+IJH1K//sEsA5WJ355CWSasVz2
8Ylexf2mPI70cVBuQmD7nWcSbGQSm/1cUVnQA3H9Kr8I5pI6Takq+oVVYhbWWftG7nKVwu8iItK2
YlBAO0dGpLvhLjis/vHXSBPLsuwqNFGjfGvQpyGyMZrqh4IH0ivfAvXwHdA+Qsnxzo+qvuyzWaOy
6iXnMQ9R4BoRv4IChX1QvXH2uaCC1/ArgsFr42cK0aVc8sooT6DyowlSBCRXsoyEhtOwPjGxusGu
ccG1oIsMszWuYd/gehFRxOyjiAJYyzk/wNkUmFNh/5uJEgIQYgmhhzOPHKC2woL5H26TxoaVKZPM
8tJQf/SZxqED5GGeqI7RIOuEwDdlFctqa/xgwbY2jcEzx2u2dy91eANdlodlUpBSczJKrTTIhNFt
MXiak+Vycn2CjLhBPquv7DKWvUQP1p7K69xpUtza0SN3XhYih9m/4yznRIujiDioW+K5Z8AoiwEB
mQABaw+TxZqlK4xc0uvJZWD3W9O0ugUGbPuWaSuaa+0tMWLLiSu6g74NZvtK8ynHgVaTSJtEh8jv
KZ9QdaHmkG85LAuNfODfA+THvxMPQ+IPgfMNRxNn/e4NZu6blTrFR8+BYd7ZGxfNyOW+XLCaCu92
hkfMeprhibqxv3VCo1Wqv/8OLYCdVLAIe34RXF5MPQsQ+xC71/xmf8A6/kng+CZwrPIUCP4YXCwn
nhA6ERsGRzfCewppA8WkhGSms5JkA8L4WEYc1epFvCzlumLLQeeIp5aI7hIxBzQVHDmcg+2kYUJA
YazxIps0uzvL46/sTJn/gcr5hM99gm7t3cBWHAl4QZeLUnpKu7ZkOa83LkKfeXn+zVUfgds42P9H
Q/xAhMVtDyQtxbFaGPEh/ii2ogTv/S/19EzAYEXYDXLL/TWW49sQGGT0hM/L6PIe+TrXoFroAZRW
Rg3okmAd9XtUP6rwbWA5NzJKSTGUbEFxdfDoQzpiouBTdOtf0CB5e7b202D51/1e4+W4kwxRV0VJ
pU5qWtOfyV02bkC34l4YDxnURqRGA5pwJkamqYs+yus2tpbCnKU+Zc72dnyWvV995KhV8faKY239
ZwgZ/bRHG+bIxvEA1NKdujKjyqvjCyZoX7kYCWN8BmTvCQZnx0QVns/xi5I+o3E+zRwzKHlVWQXU
/liMXMqL575Bi8FyzFzuNiJtlFwEGyzd4JsYC5vBdUziM8XCaf+q0U2iw3qpsuAILgnLtj5sUdQn
+8F6ZWPLR9JYjFoAitOHDkg1vJfHKZvG+oB0lTGbqjCNI6YQvnQcCkJAqCIllLRyhzOD9CLhKHr7
NqFx9bdkuVnsTGY0fwBneJMJgPhSPaZ4PBKXDZStXLZYeUfojrGIiq9qNodpBb33Xl9BGUIrYIAy
iopLDUeO69bUMnl3J2CZVFdcNhojGd9zGLfLpUMsbzDJRrrxroIYxYD9/tSNRBEfW6Bqdqg5c5Pq
xAU2WhFXGKALJAd+TsRP8/OLDpdQc1vPLf2w2VDhbVrSI5e19oNdTgFJakEvFcNICM3HrdM74Ho/
vHTeSh2DMIqSu6gvN++TyohOqRdjK13z5rQ8Fzm3jCiCFzeiRlam7Hb0gVG9ah8lg9eSbmXFqbx3
Tfhz1co7dSkr52REwRNJu4dGYzWoKcBzDxjZHxDqOtfYTMtDLw8bnBjEyWYUXV+FUH85bvqUqd0x
91nKHeunIK79oRJiXNC1d6iaTRlGwhSlSlZAleh6Ll64EQmKQumxhH+EIOVO9XenvaNpVeoNcekF
zQN6P34d4UXsbC43mc1lcMW8lUFh4CDvFQVVO5q3/b1BhnuK0pBQyDvSPqHt5ztRDp73l2lbVc+g
63QxdtCuzbhr2ObRj01VkfJkMSb3ws6XVjMIuAuloO1yW0ipb1wr8cWidG7u+yG9T43RfrIBWr3E
V2KFUu9G4Ccmnjjsithkrw9DdnW17hjs+voZO1m+iTqvi7LFLsRCA+QmCmtMbCpL06DDA3/lVnO2
y72BN0qFzlXiI6nMQDoitcEYFVJR6iwFTDjJOzV7FBHm2H6yY5zG1OI5p/N6XblJhjUObbHE+x3F
2xm1Wh7QWBDOJeALD64U77UUSBOP4Ppzx3jsSJX3mOOcUdlD4rtcNlCr/tWOrAgEcqzYOaNBnhwE
JnKX7vqx1EODkFZDEVscnWdaeXMWP1UX7br1fsuW6smSvrSISOL4ZJG++scRtk1wQE7WnAmsJK0o
xaWLrCRJePCojd7zO1TqLE8wnzrhYzYSVOj5YoHUdjXf1eofL7ZJwvT20afJyAgRbKw9y5NLhGsY
2lbjBUrB+W+P5Vu+QHJ60ss7C4W0MwCcW35anQet0IPDK68GeR8TMV4OOvtzP0lp07lKYaR/vux8
0iS6u/qme+FwKO9RhuNdoatH/US9DBzgbP28waMcKJ3i4mrUIrOULXUGGlcwQgNqo9yVkX+NIEdq
IQ/SW3crxh5pxRbKT5rd9MLGtw+SWMuQCTbVKlkQ6GbrXZ74GSlHE3cPmOrRu+LoLVFD0GwO4EKB
G1aaQEKEFf+BGP6PK8Dyop9sY74SRD3HM8TJYptLPuTgZ13R8pR9jexxH04V5rkhJwwS7Il5UKyd
+G8B3LPz1OMIo4HzADnFkKyMZdoKtpiPqvIOPcLgkKT/Us5XzmpRE9q0YUmM0Pwf9rDDzDw2D5Uk
UI2r86ojQWyCsasKB+vb9qibSiXNvuarfbj8NvVjVKiBxCdoq5lS+fC0w/Hv2uyfY9cDAXchCKDw
Izdq7YJo9HV0/3y37++6BT559Aznsm0ivonHqeKzy3YS0QOdTEvAnP/WO+erdE5oAq75J+5VgB+K
LzukD8uxTrlv2q+gLLfUpCYFT5tAbrnxnHxY0sOFfy1sZReeR8mnzOJ7dF76zMutsQPbX2+6eNUj
RrnTQnMTq4W+SGgfSWR42zdGLwwYaCyFWoCulG2gqVz3gpnxNJy1bSq8GEABtuM/51Ek4hK/kXUV
bPSeQqqmoj6YdhU9LPBB6cZVpZSRF/91pFibg4ZjBFbvXqPS+VnH9gaVfztSmFwHwKJiXGqM3wyX
rzkcY3uwLz/oL1f+l0VmvhT2lXgNZPWFhdbex9OLkBkYiGvrKCjAKf3h1kX05jaxS5G1anV9Ptp0
Ex4qv8VfR6M3A2jJza4RDXeUhU8xiIOcuAzUQQKDkENvYfDVNmM8zEQVGdvrcRHTrlvegGjzcwZL
s7acngEdk4zvo6TAN7LcJBVg54GP3ftB4DGeWqiGnA3IA8SToRJK4o5MdCHra5fItb7/DVZkMRGG
M4njNmlg2hyWWu+Pk/AuDALUKHJCriupOfe8gAUPQMjvELYE6MN0RxfxssQA3kYqrNzF9XCXOxK9
3W9gq6nHAsMjBhUx9f2SCPD5ajeKyNcR8VbkrrDmCRML+bp/hhLjZaaw2j+AW8jgYIIdmSl9Y2h+
E162oA5PhV91qsuNDOn97oCib+8IHaQkHpiKD1M6ptzialbFLA5NH5z3bJahVUWyl9fW5vpbNaTu
PvX5BHhhOy8jH92doMkyqbGUykKbVpEIM0p4HE4idjzXuGDjfGDD/T/vAZ8o+rl1zjvEwVEyamIk
IGTCDd8CcVbksVEGl7/FR+Z9YN/rBTY4gMlPYMyiMgdDj+4r8U19lYNYWV/uggdPZpjVBtMQZGZd
IRMUEzjyU01tRf5ClE8xbOLd8p7hdellREoceaUzPqo5CTrYMwP7gpuJm6V1pqwjPHKyFXSDGYx2
fI9Zkgq0IhuSE8awYJBi4bU2nQP7wRrnCuhrQwAYEc0AXt7/dDWPk0TYJ+WLw55+sFKxkIiV8J82
AnHJ8bmwA3hV9DDeh3wh3TwpWfCzsRnkTBp+92ayfS55kYPGeysGgvj6k9wYR0P1q3SS3Qgu1yRE
uFh1aiRfwRkVvxZJOwEcBSKVtgZlL4h9j5G7qVeZRDIl8CIvtq/5iAq9gr2gJ1CZViSy31f0nyYU
X7qL9tkInDxhwR1Ug5vhr4tYXCjHXR/i5XrJOt6OJjfS5ar+WUpPr2M6vmOM7A0bcSkhlFSsduMF
kICHQS0ztav9XK2gJXiDwDaNnYHt/xDyTgwwVSqBYPl9k9/bmvZOKCGwTZivghpZOxzFav/e90q5
wGtsRgS0aAupyV/ebHXTvX+Gd1tZ+wYhHvnEf4+EpZatbH3Y7vD8+Y7d7V/vAf5y3qbkQ1PJDzAv
nZm8vCPlQ0ORWfScwdmjYLvH4Sl03f4ufL2hUvZg2LlPXl1ils1K+J9UARNThG/hoWAUbm7nuB/J
NYqptCheiINioCZE2kn/+A4OyGLQd5TZVMs25M15LnkuuMHxtAuaA9cZRwjxSQhOLmccQw/6u2QI
F6uWHNiH+gCDYCAStLVZHPuD/n4ZMhRLklHnJ/ffGH1PMSJSaHhex8OLS5H/GcQdpc4wGrbk6yDQ
x8MC3rm6goCOxipUQ2s+pzu7woG05Ib0XrkTRwIRwbjZRiN1FFRwA+OUavsY5c7JTULssjQOHKlO
VSdwzRWRoCeT8BZ+C4B2kT5t6DZ4L230/kWCukGngaa3CV8LI8utik8aIIhFmTAyVZgepTexvtqc
7YQ7VTH92uK2ABcCbaBJ2rt8J2GbVGzIdMOyg6zrNlBBf+bXHaYrHZQy3LFA6Qp0+ziNjWHCd2Ki
s2S0GmsEHlXCFRs2t9OiZQHT2iGDzyt5dfGdfaBBY9mS0h/lNpuRNVb4NdG/JzjKUO/XuI1R1dan
w3ikafE3X6xczNDxZo668rkxnNP/QP7V/9HIdYIA5SyANXntGhV1HetIclGTtcRmyU6+QFsUsGWX
L9QfmYEFzq5fbgODbWnXCUlOm/h236lqdJpVvy+SlJsVwwOPeI0sBCMHYckbqPcgVGH7eCAE+dzt
9Fl6TCqqKxyKGStaY5kFKEp1VuxIvyyu9KjYNU/z7MAEC4CHw//0Cnao+9rweNmk+uDUbwfwBj+a
Juy/y0wXKIIIU4SovlLHpUnQBL8+zLfHYAaEdGAGml7nytGBwqzUTZ8NB2NcX/a5CmiS38MQMo1o
xfHB28jJefNwYLXgEXqH1aDyxmRWMKJoVt73R8MqKnE7USWUoR2TcmgfKoggC06gjNIKzUMwAV7x
+E0YokjREZa9Z+LKVL21SjccRccFh+I8sB7BUv07yTnnW586hMRMyWOTHvE0VD99JRA01yVbcoDT
LGnmtJ2rFKiQ56HnaUaXnHhGag0KMACpSSCP9QIbHJaGoC0ppCjlw4h9bWWQovWu5ktFblssSGNB
zGes7AMyuWleKGTLaLbyGasDFDG0Z4vEr2GFb3a8Z52C6Nvu+so8gSbpiKHaXmV3Zk7vDBo514q/
aAUwRRzip1eIMB9TJs7QaXPnqRyad5jHr25LYEJextl5uUvHfKVzuFv++yj2XbR8UM0o6DT9sf34
sdaiUSbAdCH++hruxFHal2glQJWUoGo37jKgtRbiDfNGvUoEal+a0ti41/mMEh1VOYUrJuxegMRE
mGNHOPqrR4EAhRy3bSMAalvcbApIAQwXDnDDY8i/jBftV4mWe3RolDrBvfcLV+SOv5vJimZDUR7b
HZ3ALQ0X2+PQax+n0CcTqNKuO91tt0pP9rle7xC1y7y3bU5+XbB4AOFJulsKu6Ura2cCNAEc574T
QeOGS0BIZCy5L3Hx9uzMEikFyg9t785ftEAnxmrgSPwp/lFRTfk4uK1xfLj6LQCtDsZMJIsefjTr
Kybq9pErknKXUwmANBjlI9cJfYYZrnj22aDdqcPZ2+/5F///WPhol++3Uv0D0BGLw3AyuwwuHagS
2jyeMD2GeueszrGl8rUbT3njoOFIR4J9ikFKOf6PZ0pN69swKpjcJUHdjMCzMw9+Ul8CvGaftNF5
4HDjHiVW6ltHEQVNN5FadcZfcBxvksYCrHxnmOnesPeM+1G8rO9SBh4J/Dmgg87DYYTy0KhWyVOQ
YfUfTcDzOCFy5eW8cgFsfzuKaaAwDqUP0qJFBdwpJxsYFpSsqNaFoUa2egjlqV00zBewn7CLOYuv
IngTgRdcbUcR4i8CKdURh7XoI9JU21XR3Rc7nQ4mCbG8hbZ6dD9u+NCG7W5/NarrjWim+2wiOf0V
J3fLbkI0b1K1WrS++81f54K65D656ln4Uf/8ih4CW/3vvWybasKMz2riyeK/uCUZDvSAza++EuPC
3g1CebiwcQgZOYVMamkuhrux1Xp+Yb3+5MzfSxEj1gTEY5AXNUP/BZefmOHEmR2DUY0PG1oNPLd2
BdLhWOEsRHPo0gybfUjEAoFETUGxvNrmmXGRXku1SLuR05/qnlCrnQvo07Lx8l31McX1e4HHyy3U
EDQkOes2OQLrkZV4OYNrKn6/KJ7K8oXyNi1/Xxuw6inNKOOwUsp89gKAH7ybV68TEltZcWQ81LP5
6HJctZBoiAhowy9+3nybhYwmuA1tutWRJmZ/zz83e1Q/zjpKRQjnvM6JjicugrZkbXTkv54P4rQG
0cFyxOGPH2WXB4558SelGMQppEjAKM3W4SBHB+FrSFhRdJ7jN8C5hnjHSHxkXDodxGQhsRinqhpu
UPHOinSHALbw1+410YYrppwdrrVk37bRiRyn28rHK0AEqbbG3fPi/fQ8sQ880QX2ChCo0pNJY6tE
Hxtx6gl3AsnOkImtMOI+xIex+cV39g9izl3yJSy0WgvLEEG39OC7WYHRr71W5lus+9/u+BR2Ae/n
Gz8kXrg2Um2DFwAaHhDbkKQM4SPI1ByyOvAnzyFDmrCSVBBpwLAhe0vdUgxOa7/YTbEh6nbSMCLv
+xlIvymn3pH9sYTM6e2zSCN2hnMtzHdx3949NXt+y6Z3JNxvcoLVaK5PQG8d0ExBl3/yKwoKTdh2
OfazAKt1XCT7L8sQZhOoGVBqiMtiH9LIlXxE0scyOtjQC+khrE0AAV93hS/KMwSTJuSXa9QLJGnk
2rryYjhuzHhR6VMGWGxk6fwNpPXfzaRN6x3HcWp6N+a3UcmPADPol2lZRzPGi4VHDb9P2uieLlK1
aCBGtuk01aF1/X1w0KaIFnLOVo5VKhx5VE4oqczhPIvcUk/Cfc/sZiDTWHeNMyGJED3BShQPUXW0
AbTDdNtzttSNQpBwHp+dPgrY+S64F0zmoI7Ovh+J/BOFaLq0+zAbVsn4F79LNGPl7gVFAEu7OASy
kBctymjq2ZgI+3aSP8thUoJw0iqINTm//6m/zGDXz8Px8JN1sv8W2I7SiDxRhw29NCYJxns9OvFk
FODU+IYmz4vYL5LC8ziHt7wr90PE9vdxp8JNJ/Da/hb6iYiyHBwO/9bXw6aV45i/AOroBIOg8waQ
SfpvvZm1GeyltTTkpGX1qbwWSya1mCOwNQYUZQYoid2cfj2DZXL5cEQvYEgYBVrhCGwZLy1C1nfS
fovmoqr7cHLSa74pUUBAWkzC5HUMceIZ8gczavm3yfNmBCitEYSAjaZPAn5xZw4UuTCJLpZsrdba
SV5sjp8mpUAgtlMljyNrJ8CTV6DfFUY7mXSmf6BzEi+czAijZ8JWOqJ5mlMs+uDt6BG48mJH1ixJ
XE249uPVOmdH1a5qUjjI3BG7n6QNR4a7Z2ok6PfOuxYNMShyu9KhcHd8NvNdyi5Hy5KKxe+Ky/aj
tDoxXzqZTeBO/+10MRUlHPkgqdAQFl5clbtayi6LgJc2H3j6PbVK/T907Lqf5P6d3de22ykDZFAl
96QQLX9j1yvHgUj8cdhQvzCVu3U2fF4eif+OcoOXL9SAD77bpv7HY7NhxX8gpCCnRlKC+QiYnYso
b7QCJQ1JZ5+Ni6ne0szwn0gIEQZPWitD73rTEUtdsj+A1iOn2aXk1WoqGOX3pxH6eOjPH1lCkKm9
c/KBDIOyffwXU3rnJQ6xiwiIOzWajc7nkbz8I0mRv7PJB55FWpqpzwciBmCV4Ns2SgbepIeZKDnA
3QThCwih+2X1g/DJbvH1O/Miczbs9HFqpoxnAMgubjyyn0kv8Y81rj47O3nZRwAhnhHJRmJdTC+B
PjQn3ezQD3vK6RmHH+I/FZN97+pTUTu4MZuOicM2tzGBcKEaa3n6XhKya7rjQjPH3/R0qg4UhT02
u2YMKBA4Za0U/S1kGFeudL1uC9WmeHKpBJwGi3mlkePBO9keJsht306Yvx6ztt4VVdd8hsNxbG4q
a3qOX+FcUyoznFFuZ5K3v4d6l8e1pTdhWmSa2ZCh3iG9oFPU507vuh7Al6BFXGQWNuYSwq3yeHg1
/n5g+Aa01h1DMWMWFQhUTOsf+T75jpqAEPOd6dVI2Ti8e3LF9A6/yQ0F85Tk2W9jTOb7C10z4rdT
KJuhHG5aOy0CBNaqS7rbF8K4VGB13JAnF9fuqympA06DTzOj9gD/OL93gL6JFW81QeVk51c70voG
CzR8WDl/40GloQ/uVnVbbbBr9IYcSW/XHvFh0vvfAQyVd+wjMExr3g2I9tJEhrkNrtD+pXRnJOLG
SvWVCJZgL0As4THk/8/OyEkbiPbSjuufJFe7y4k8Rr7MdXbGwV3ZZsshrrlwd8uYTRGSUaHxyMnJ
rIjSZiYGkEn77Zx4wXzajJJ6cT/7eOj27SR4qkcukJVns8K8QnI9CCdTInVkQwDZPk95dW/VJSTC
i2Jvml/GI6Kuhp//XW0km4PYm6J+j9k+VqEVagSXaE6Gwo3yWnmJsllatl7g75TvmhnGkLo8a4+0
EKF4s2otojVXPlSht4clXRbdxvt4trqE2gHf8KfY/6PIigO7ddy4afapc47YkUzGGa5N0qgc+YKS
rWXwxKsFjAGRuDE1vUxGUm7k5bQIh78X/Tf0OStn/Wkk8ZSdtHGK8dFNWhGZJnYy/0GFiltPUHAH
bUyEaXBQFvx+vASSJnGuLWBpB9zRLHk/OyYqzyEyeBcwObxZsMaSKkmHySwiJdq5u3P+dJoENngI
C+8LHhVbOhfedRU2vXKjSGijXThwnXm1j2SWKgwtwsFGxJCYk9+mdYzpUhg1L6okoqnXtReVOAnu
wwKPUYSRroNxZPUi9O4WzXv76mCU4Ov2R2OFksTlHXTrI+/+4yAUAQ3SW7e164Xa06i8Fqhesuej
YJE2pKFkSqqHqLae4rwORbKkcQKUY358KRRji3H6OpnThNL9pVO9CLs4o1NXD5Gynodllxk2UPSx
qxoGE7K7bj+RN8FgewY3AomqIigBdt1mJQLhTocQoWQdO5a53h31frzwUjrNPPPHoULDJb0v7fM0
5Kfl44NAWejiUT/XFWW63SSBaZQATQiKS1KF9waO3VHWUynPYYj8gUJdIwMAgZnCCrGjJX6ScI7t
zGmg+TRCqsyfFAttWsEfzzuLEkSzNUi1ZztxQtzyVCN/vgZ4W6XFDMrgzc5pS4gchCb5in24EMD9
yT0JtK5WF2L5sH0L1GJ9GXBY8ZJZQbbvoiin4C1NxhTfzLpfLwetFxc2ck7w1bixVv5bvn71dXa/
foVBIiM0Tc4dHZZMsksir41a4ijApgbealTMfKSDxgZGFpR42TGDbpShqxhD3YcyaTLVNgszoud8
Dq5rH7iNpX6jjgQMKoRQDFbWLBHTMQFqUfwdF/1u9SuCmAwjObcA9RJy7OlnMWwXAm3lAwvHQsXj
uBLIek9JE9BrVNlzCwYb/P/pLeiWOt5NTV95fqrdzuel7KW8F8uw33xs/j74R6rTS91gDL0DiaVS
ZUlZcn1VBPDknSo4K9FLTdy5M8cUngWP8JJ9SNenB5ZZLceAsabnbq9hjgZ2tf+9jifeQzmIKf9I
OnkmVDWB5/7GFJQKXtH7+KAzkCgsCZtDCuwEAlXon4f8/I3y6+jSVRQH1MhZQvZ6lFjNPec1xbMi
yMm/jq+Qty5qFuQr5OnsA+zzhYXxT4T4TtqJPsfLeLZ0des9LBerv/JtH9CjkpNA9IY9kSEhcarN
5j/IRuBVBV/yLctOLUQYw8CtfmG/qqgY4ueAlom6nfvzi7UZjO8W0wVoCJQT2WAfUOZDigKX3sI8
FBRRYOKICGKpvN22eMHLsH24GM86XJNonvlNd5whQ53foGX+f+aIp+4I4OJFk+5e3vtF65mOfESy
FEhInMZwrlKdg/LHXC+8iovGVpyZCsYU4epZWTmTUaqqboWZ0GZn8+tNUKaKuhgUD7T7t/xTla6v
4tHXfoAzd4RP89rAZrZf5ziAexgNmz4zySQ44vLJMFXrU+SRJuLgZunxZz/NXCqDPIycsq3hX5xH
ueGR8zx9v6VPqFJxGH0dgXXXCRAKvnQ2fUh6a7B7PeNl+ub7PWWxlq8H9dZ5C5MF8dCJ2kp5Z07f
KKE4bG2EmWH0jj7fVOFdcgtTSLazGTLaxA/QI/tsWxl76uxdgJJHYsBBLoUErYeH2t/rYGeZCwR5
16jGvlTb7Xyl8AyBHpQEpBd+KHUHBEkmfZVMTLWiEWDQJSPtSCyVwW+6ZjDiIU8imNQGE4ETm4UV
Eo2ybwtSXgCQf1p6OF8GHhSf07TPNFcC/ozYEDQ9DtAdqQx1McJuovCUvOPMAgTQv04UMMWSKq08
jqIiHdeFIJOeO43LG4k9OiFAp7+c//cCQNRbsNw/yli1QMxhPkhFcUXVVm5aijvIWqySslLBm8eG
Z8nD7LVEFCBs+WkWSIgGbjVH8exxxE8hv90aN2hPQW3L2duFrlmGmahGwXMtFIN5XZlvNxq5olNL
ClmHy7aOCfk/hZKEn2iy9tTaoDTK5oR6WjqOcmKoilp6q3433RQuI+Lz1HhwcEFRyn1ylm7tRn3L
FaLWvBEg4x9OgcnesrOmsQURYrNygEaYGq4fj1YebVhvJ7wDcFsoLodLuNenU7eLBsdKYX8VLXx6
XerWscQICTv3iZpSkJbh6nW0CGiETS7MAcaVxhwg+A6r5SbZtQd49mP8Nsz/MgUoG5SucSAzfbW9
CzEf8J/IXCu5UST/fdG0Q7W1b5DcveFkLD8AElL63MoGhSIVDvYZITsbDFLunOsHO5b74o1KSWik
yXjuDyMayHyef+vDuo5rQewu6lF3zeJFaKjB4MeRcOUC6WFeFk91YctrdrladudoQVjfUTiXEuXi
nMHJsypIlMNfpx5ddmYuu2I04OBcMtzk0iSnLWn1Mzky6z01Im/hUzhWe313aJanth3LqaeMs75H
30kbZ+wz9eSWJTtQX5/fuoiovD5NUIBVSYF7VOjYGgrmjUjwyKKfLTGojzxODj94qvoMlpsoAzQG
b0odbLO0YfUNAuKzDrpQDqP9Y2snoMabFimukADN6lIe6NJrbNv585cc2N0taGsftZDa21HVOlE5
FNsBWFBewug2tj4gOq5hHQu1bwLzcpXlt7UtzBO9q8fSi3Ym7TURKSTvhoOmn1D4dzXQ/uVt/0uE
/Yo8PixnANpSv6J0hoIQv/DUl5sG3txYF6r1Flh0uze4x5xWUz5Ua0M8AycS9GM7CwekE6ZObXdZ
As79NoBSMGLx7ka8EhgUQGpKJRXmAwb1kXijyOF/uVj7oTyA5g8og+catIf7ONTbag5c+2hV+g4z
DnHlK/8zoJe7LnqU424VE2aR4/B9ApEi8/c0/lmygNGd9JzSkbh99LNa8pA1qCyPNBoMdWtMxoUY
x+490/2oCrsDVyNvMdFXMRQVUPiuaTM35E41Zwh2Ncya8XsPhETZ3Yw9x6LqVOC8b1FmJWZJIq8j
9tn7wxGbr0VK+HeJ6LsoEdM77nZUUnT5ry0kUIxoC+ARWWt9E6g9d5ZWxs5V3mGvbPiwuOXDKVbh
NL/iOTvyANrmqZtnMwRypRIGFWUpZSsUsjK+r7mY0QuwvaEa+yITkgcy2/VYSvvbO6J29HDUkfvp
tUx9n4jime1nBD7+MwfBTxS6xbUr6iUL17zFTQRTt0GzBnrZg5W8UwOvC67z7Pnmg993oqMrQhOe
69AzaQEgQPMurMgnxNhIBEpQv0qFNZSWuhNL22QaSDJGkaBR3e9JE2XXVDVRUJUT9jzNIWTIghAD
lPopE7ktsJzZEjbHC6CbjWDTmxO5WMVclPgBDFkiY66/gSDbIXz46dFcQqL1Ks1kk0NxSOT6qfUh
NKdw4wm73iw1v5yNGZikvcOuCNEFLdWLptL4YUfCSbW1EsAx1HD+MXlU8gyCdS2a0RsAb/oQ4i0b
kAtBBsFnX1cK3NDJgiaEXkSUND7yVqHse1fqliL4I0fWHqYNGUMNJkcz8acSd89gxeD5iJP4wKsJ
uiq2KVm49YE9h/9k3HrdIY/S9em808Hugb1Eprn5RA0LE0JTklwBUwi6O01J8qqGV6ERPwRAq67/
wCHRksYmBbRe30MSL5ios3rzrg2ryoEY4nUUwRD1uXDhQNO+95JE/kNkXv9MfyHSEOmu7GoHNm0l
eOiTmqwaOI/uxD8A8iBSb9PfCzuSATc92fAhecvNDviqPFdd7fPpgAktGe2OzHzauFLkoQDefwVq
P5d4wFzgUX3jO9ogZPFi8ONgreQLncnTL92YMNByqVwjr0yTKp8tXLOGOE3gnShrM0O8kiiyH8Gp
U4kVizFhJtdBR7+QHwJITvERJCBdoL90WlBuiKRBkxEC416jC8SrpdRc8RZFfoi+IV64kG0CQqa/
Hqyc/bHhCZf16psvoZtW/amDY4rA2dncD3OVbmLwmEE+nzzDjLnLuXJ3teVpMQlQByOA1VAMATPm
j2GqRuIdpNCL/lU+mKsPmaXr8XhLdYLHQvsVTsUEb6XWoo4HFRDO9zRHTJZ2sIAwr0iZProGuPVX
p3rcauzlBwYb0K5DPMyc2srOxbLAQ76zNl4fcB1VVcZdoAKO2oM/zTjJ/QZ1E7Q0ePbAFamTp51J
g8lr6WSu/qqd2pgF/vAk1P/1OIJPfwcHLyyV4lXnFw6KpPtSu9LgrrR+Lc/sZybEvveJsm3tmvvE
K30nk8wagC+OdavyuRq9HhzNQFR+FmlA4EKX+nXnR9ajdx7siFyCFWx/kiD+L3MsaQN4D7ndOMEK
flsJXcuNFGri85BeWl0Yas9O7Fb6h/87yL5HWY8MA7EIL1+9Gs/hkC+Oq4MX9wq6fDNS72o3K2YH
bb3aamKBEJYEEOYpzbhP/DOl1Lz/9giDE1et8ao1BPO7U0zKd9LhQyxV6lKnsiQMbor0NtZ2BK7e
p9S601nxvXVSK7VKjU2N7A/SJhf0mfXCKtab7ePKyc3PXaoN2MsIlduEB2woyFb/v+mPSl7T2MVJ
v7/i4DuAoCCjyrRVyLDXngBxqzOjJzLpYbmVo75GbOxrYt0IG3Ep9CuSG47hn/aSavJCPLWlAtt7
8JPUBe9kmyOTApgbkE/EoPJKGkzEhBswGqBXWpYi4DvtncaKdME7V9WRzuoVik5wKCEFnjb9BC8v
QvmjLdrcN8YcGSSjg8iKR2VtHigIujOdShk9/IzwcR6vRmLSpYQg2ohvEsLbgrzIWu0MawW7XgLp
43nRxcTqFF33U9eNMQ6swwFVdgXnDaPFG9+d7pCBcUjOx97MhhUIgRLAmbusdVmSjiTknZoah0/i
YPGP09Fc/qVg3nlmoAioaDn7ZRPML4R6lI2HoG91G4w35OwXKEWfdqGZLsQ0Gk4rC+TKGlhucytJ
zlBPxq72gbS0xRfA1GE6bfa2TfF3kGzU5UFYTeXvSbf90dGFJgGTvD8TClxJLEsqfuVTsK4xqkKS
uaEzA9Yhe88/NWXjsQ7HV8r8WNDJsty46VwjE8s6xtWaRvzCYgM/yvTJqAmCkLP0cUbq3OeoZEc5
xdJdrS1E1LeJnI7ydyQ2aJyP6cOaF5c4fDwWn5wibgv3ceS0YFnX+/tgurQRXk/7lCyfQI8ui59h
yQ6KxS8JKxIyoC5Ev+N9oCXICOqmyH2uA7QxAVoXJS+MbDpgSd7h7MRYhdYyh7mx77l0LUhCDiqt
SgMpWNirqyqRDsb7YWDs6LbS0dvVPruQBSSD4MHfg6QSxkYgCLpnosagGJonFNk6DtWE33Es2Hn2
edf6AVFHPaDIq2XS+AuSJy0lal50e16wdTNhojfMucsxbd8P+pOjeN63QRfUg4qNA10eGxDrGENN
WBTfTL485ji7SJeuhaWoAWasC356dWExcD3YLiQ8j0aK65NLIcS7aq56+fqznmpYkKMlUdm8B8pj
1US46Ln37BetnLNmOIqeHKpv/4JR6ACTs2zkDC/8nMAmDZZkEmdBZsRdDjl761j5TFW+bsbMySBt
EN+ZJw3eR5v8cToPHWaDq2sc93WsUVG1Dq8YFsEyYMn8weNtVlvL5myba8pK0GN8VkEmkzb6+5Qy
p+HDcQmg6cZHOl7SxmeROyS50r6IzzMjgVdqt54Adxj1ODV527jo775pLV1+RaytHFMVrBxMhoBS
XaYJuqrzD6+vbT8MPBZ4QCKyLGSQ0Jvr7l8ytiivNCsFIawFH+6lxRRNL9pqB0gUJ7l8gGvUrjzT
9yN8mRTEpv4+2laGqNZF6dd6bU1JRxAXivJBC/UAvqB7/RlCdWSUK9ka28JcXSLHa5w/KNJ8h5bp
PNNHWMM9IkGOzBViHQZ8BgmGDTZ7in7Y38/gwCwD1HK9NT4WVGQGaZv9+EkZessN8XF1j2MFFd7p
FPlGF0X7aeX0rPfIBgiFfOMIKT9VLipjjaW7amccw8E+AeRumxrvykt0ujoca0a3tAzaxwXeb3yh
g8AdH5Nj9WSPdmCxQko5zxBxoIGH/sjMJuQYy+HHXLpH/YpxqIJ+ruxcNeFp/fiKP0Yw2YxI0Tue
L5pJkISOQ4auSwiPu9tqnp4PgAfKzOSLT16LzIh71wN5nfXdDhnCbS1yfcGcOLBpTTB+vpkaDgj7
cUyZNJxDSicYV52ihQaOH8Kj7DKpuBCnwcs8ZBEZtHDs1RgdsZe/Zt7+K/2dCYYKwBiN6ZcuHe+x
emWhToQ/ywIb8qQmo/O0SQcoeGRt88aoDWOijcxMOs7kAL1DB26k1x3DDNFOIl8kSOVGou9V3Ctj
B4Ba2udTmuz1gKNis7JrCbtsC5nujKf1hU0hxjavXXYuKOgfV+V2A2E4XKl8EzS96SuXPXO00Mjd
P+F34bBX+jurGJ+CfRNoU2+je+419g9o29f8HRUAsPp2gCDc/VxNoXHwge2eRq6zFTpxyqt203fI
7sLC7hv4m4DBByt3MzfR7RNaNLdTWdsCT62grFsN3FC0X3acRgahX0YIntoFAdWMT2pemrBLJnl9
0ub2g7gJ+0fxu4/3YpduBDXPsfH+L2iUeMZQwkm6PiTD62yBZm31jtYgPew4MXlZGv27ry7CvKQI
EsQuKvC4LlkQd6ASW78mWtrrilI+F9ztn/VJxkSrLHkJacFd28pAwHbO4mA2PR2itGsz3KZkp5jf
Uz0Wi7yBPlHIEzIqofgPCgJRqrKmwBv+ljT4LDjLqT+7EBm5PxlR0xvWAdooUQeklQxV1/VO5ZVS
GJpDdBnhlvch0F2b+tzrDU6YmUl5JygYr8IOFoFvnytW8O3MVRJzm7ldFlQksnzu076zbJw+xKfN
J/ULlnlLkUr/cTRYibZK2LLoIG3kfbt+9KvXpisOPeMec7Z3YH9rEuHl3Mtul21tGZUqbgRFurVC
SrB8nrKSrY0IKuTURrA+SlWgE78cQv4Fs5CWlhL5SUEGfkIhfxJxa9TaZwz3HCEukyN0Z6vidMz3
bVQ9N/yI+2E3QWcWDfhJWYr+HeUBeiWOA6lQoizeeUfE11EP+HZD9BxOA1FBhnXBYHab9Yu+cTKK
1AhWwtfKRtBt6NziI9BcggcLJsm/DbyDK/mhm2/Sp8o2fsKgonOrCO0IpiYkyzEMiStiC6ohGZMA
/qyR61+pgIrV3jAlRfjYibC+ovyXTObdbSZWSdmMjrnAYjdX2SuS5I2qwcsRoE2CUjOdpsOZQyIS
toubEa590+DUmRFIVa5/Q3VGidpFPN6QUFbciRH5mNKfB1YdUICyfr8kKap5gTEYIko0UzCWW5E/
pdAAeT97WEEtvU4DZ8td8VVzVkKToy1ODjKPSI2lRSqIis5UnDzKctjRfjbaJrjGEkEixg0DCDls
LYXbkNYY4K6VbzkMwWwr25ieM1JaA1d+wVmdYyK7ovjxbnyhbMbL4YriLqMMX2j04uMC5ZQfDfYT
cgS9KKqVmzDPfHmI03rnL4Vs2SK97cEAYJF28+i4ZtClwy6okAM++ToTf0//3LScjYg3HrxntmIA
C5yv5LVoQkj4+OhApzGqFMsDElkewuesM5aiZ0BhFEy5V77Hv8g4YJr8sCcVkWEmhndfq79/T9nc
6l33byMFT1mdOc6YyX7e6CXlMW/ifZmBR2c0O5KQJyds7q5OqjNiP9Iu8gtVh36m2tu64Sim8pHm
yrBIZWOLR3MI15rzDZBdvPAKZwLblNbG9VoC8/Hii8HUAtZ93r7VJ4ytwQfksP9qQyqvMvv9nmrW
I6g16rsoT/795L2AvtkWNltzXkX8nkkcnJRiITOhysEMtSGOIDkp+Zy4/7oHAzvodtKZ5NCjRU+e
6uWoTJ1PJz5X5fq+sK+7NHOldr06KrYK5lFn5OYcfi0+bSHXUP7uJVjN1UxIWEbn84GcvZOuxmch
CQTBYWxM5C4A3LzW3rHcSEtFTi8JZPh6bBCMRmZ97Vk6f9Qb7DaWgQiwlSVv3cJY43woPp6mMzst
FoMmVZMMIv55j2C+r1qR0BWFEVAI6nBUMnsKUd9u7jp5IvwgsZc6YFDyJrIQYA/dbMYvNLkQp0FG
Ta7BgY3qfpnjA0I5fNyGfoCCM7fEsPDUU6w5nSZwO402ExBKxHYdroWnZ/pC0+N9qMZa8iMCXJYj
yJPz0oJkpeTDS3rZoPMy9rgQrfghwzhZYIO0mdYaO/0uZozBIqT4pazF9tk8qoEYuJIzhqmIlNba
14w388YrYMB5c2DrbmIgzRDtaDupBa1ZsL26JNe/Xutn5uLcj2Q1fVAlkJY8YbSDfV0Vicd02KX/
3XAGbZyAu04CL6ISjDLU2XVZ82tWMUr84K14Ga0NHklGisrhpWAxKzr5WaIY47DgFP3inOWpOOTl
SOt8vwpnnkI9/Aq0SXVblGfx3cCTZV+34gygzPHA3TyYmR6CPvIF1wTVKztIpTC/IfHWGFYTb1j0
e5GmgHh35n7V0LcG2GgXM0zNhwDGvRlZKC/QF099mduVkyWIWoweB1qCoKl+tIuLGaL3sbGP0txI
eMW+zTw7Spi0tWOinlfxMXdBg9ZZ4L1NRp5qOdCXCmg89LsPE721chuYiUr5y1sYtedGNE5GZes6
pEFtKgOGkynsaC6Rcfb4ARIC8s03MflI7fNKaaSm+ICRNVX57EAAXuZAKzpuhAQ0Qd73kq+V4oub
Nr3m9vQjplkHHjGzNWswPZ3QKlPzsM2i0sN1lxG+IZW1fTgMz5oHMyVM+EjjXlSC38kBm4Bn8ej6
mso1aGTtaeJ3q6DHCgxAN5JkfGKMawPGPrjJkpcSJ+bD1Fvf6/smXxrI/EPbr6JuG7yQlRSnlckv
sDEHywPX1Kn//XBGHDefEwxe9JJY7HPQ/xpUEDrm88IFPpfs7Mxs1d5WiaFrqCjRVG46+HPbC0NF
J+6zRu0uv6f9D14kt+4QWc/e3QN160k79rIrJ4fn9i1mlZW/b09Ukm63ayfpGe23hyDxF+Aow8cP
NiYLjoFo728WCbsC0+zo5oG3UQE+BqVecuvKHfUZtDivbC9TsJ7DX20KF+8aiX9cWI2bpidYa4at
O4I22GjriR/lEf5NpUo+t8p7Aq0qNrrKLuQTMRqkM8m4KpNnoaxrXEhZdik7dzxo6JSmh7zVDPrF
iccoAk01MDNfYSzP3RX0+6MyOuiHUVvxbPlwbF0VhgrF3gmSiHm/gJGmi8uKuI2ZvRduMOn6KhX7
bACl16e/zYkwL/XfVEA3Jcbod3G3SMvqlFVET9NyvB5PIPuV5lT3q7+FktJwm+MGmSkYnkEz33ho
dyYCMQkV2Y9MS/8LR+CEbgeQ9vhGRYb72nXliuzd7NJoD4+hCVJIXs4s442ETe54ic37E67TxS3B
YUnN+Hl4+LO3XgzH+rb9DvJsfAxylA+XpmThjKs9Qv6qS+2GG5vDM09ox0KoRiLH/OMqcm1sJldB
ssRzbTcnrKVMmzxGtAUPZegbJCmf706f55dnQTXCC0FRImaISxHOOslrNKHG5p961P0hQ8nYuD+H
XKnBIAYnfUUF0j/Giw2Y4S33dUP5lKsYSO3mJFx5k/zNNw9PQo0Z+K7hHlpSccxUswcY4rot0YOy
uD3LXqq0NxkCy3117Ijm6zOcMbeH7i/PVQfCNq3Lh9wbhRioPiER+EUH6PvkEc5sUJOy1ZDi5tVA
llulxuR2vpum4jrVH9v0H20ydL+AVEu8nD2RbKK0kegkHj1p/O+PT08pVlC42Azr/K209PHapSDD
li+Fym//rWcxKhIJKp0DnxDy4O1WMrfckXpju/w26x0mHN5WjQ5ndoECc76/SVRf2b+YcuT8sBuA
QcePMpWdWAQqgNMDF7S3+WOGqRmQfLzqySQLGLAT5x0dB2OWnBoOT1ZuvyjSpFILz8J6n36x+Mew
+/BLZcnWTfxyv7+8gWbf9KOoNhvh38NAeTvTDYkWpz5RMPk0v4+Ee7PUb5hFefVpsCpXJqi+H8F1
1UOfAsNlCP6Gf2Wv3RT3v/195lI/mbBBqBqCKDwD9rptMD+lt1YMp23+WjmUUhIBPDWah5EjCd9j
/RB++wW8MCW8vmCv83sIBKzmtEffNPEsWHNxJ67OZAR3ZbArSKCY1Na5c2yXXnwlRGxP/azjkV7+
RjwmJTJgU1+hb8MUzZPd0diRII7XseN50GgN+hofCLX9HdE2Q/iyLjFx37L1ipNr8LqmYNc2z8d5
jQ0GuWhSKYQFbYxJaEUa8Fka+6UXL3eGEb0MHJobpowQeEJOqHcsoCn69FlJPpkIxi9eIZ63bMjl
aouKE5l+GMl8ndQJXOnWMss8amsZ5Gm2LpIS1vEbaJVFefk+uO9fEaIbtVfr/210imi/Se8LFVM2
pz8gsfybCZQEzHlvCEJM5tFAoy9wjUy+29VZke+c4GQ4y6FiSa79zmNCQAoIdVrCfeX4Ng563e6T
Nzw2t65bqBTD6KMkc8BcK+41M04MkFJI1/9bqPgYKfe6jlIMtrFqYdcczBVhOYaj8FAELuLvcsCY
KENHbgisgnMUb+IzrmkZLziwII/Wur9ddVLaSAcrFifg5gjM6Adyw6OfE9MKgmwq4ApIKMlPSoeq
Q4IBe5PJ4SSAJ4uzC3alecDJ2V8nMXNzDoLoWY6m8RpBpSNj2KL2PYsOCHanKyId3W/or8Krjq4N
iCnGNz9xgymToYW4SUIX6Z/hELqL93/ZTyj1/kP8bz/Go61cI45mAXJy3zGP6wfuy2oAQB2mZfb1
tvMnpXo2S/eCr6L5ad8lP196TrX2xz9RIQCRWrOmNrigM9UNIz4f+sylbVPYPGWs/+k0BK6b/IkQ
d72Ir6nnZp6qJ2mLxKvabrwazabRE9o+spaNx9ZfoI/yEgwiO2GjBMy6xwYCFhWnA6RUuT+HXKK5
zOh82nxpk2YdNJ8zrclaENHAvCqlGwJUTSRk4hnlzP8OUy55JDYWqgv6eEnNkhx8CZjGeA8u+1Zs
hZN9Sfof/+6PLyLI6lqB0DxPUtKSegGdGNKHDdjnDxIlICsx5HM9J4VHM4uWm4aJ/BmsiWqPc6Xr
VzI1iaRdkr7eKX/o/hPPoU+QCMXAkQmbwMsw8EXKwhtVY0x5qUkuPD7qYpGuFrujB3PtMol/Dwii
hP7d0i7i+WNdfxzUt77BgsyKYtTUXYzjaoXxAy3dvs1HrezA+/5XHuKvQcmOkj5ISgxOJU6GyGMD
ijeerERv01L8dBzaxQI5vRF+tcJgQ7Szi+gebZp0WxkpA8smVTuzXbkJsthVGLkJFNAltP/2pcnA
DFqwUVbGzyhchbhJ9IVgcZue34+pMz5S8J792ms8c0MsFbAAkFI15ZmB35c/s4jxIxmUbqSe/wlJ
rms/KSB0iBhLVedfpMuwJIJY6qtwcWDkP54nM/5MBt8G06DYZ2O8UkjAOLyooFyGw0UC9lzevRbN
j7rgBVQOmvPc4Qihk+SqKeKOJr+9XkBTZi5XJt+NmZigZVdjfPyDB4IB1V1RyZB6frjBFoqE3J0G
JwEuBYcN9sdGC/u7S/6ROORW4J3k4zo6rDuem9gzgKBdtd9TKBrnNeGZM6ki5LG1DyPcjMqBuju6
0l6O3CLSxQiRHvbJN6/K8Jw/V8ZfqSaNdaYV+GKWilpXSM/GfPOScukpcv3BT+AXd8Jpo6lh81ar
QD3R0sv1+9ScNplVMNtM16VSpXzqf0RFWoODcLl6EMKf03znYQF6IZWH6TuiosvBkd9nDuBfKIuU
1UBctXGEWocrXwDVr8x4oUFyb5jSFyFqoNeYwPvnyFe6cqf6hJHvOhoQpXRvoIfizbRKoL3CprzV
hqwlYsnIyq1Q5+Za1+qNGArJ6Au8vujWEWwjQzIZ+yH0dYsecXvNLfZuZQx6dVKLV8kDOPMZB6W2
hFJxjD1yyOvjFdZyqo+GJ2f3SYwXrx37OjBD2wlrP0RVSmjRdqC6rmH72IPLtOfkA3o4aQKnR9Ix
JvgAEWB0iB8rupntGly9Rr7f8upZYPuoRjqblCPvdXzzVYki9zm1q6kBQ0bhMb2wJzAr1J1RypCh
ANsU+XdgVsYwhq21NkyT9zcmmZEliZtchpG2xJW2+HfVOJcU8ugWut372ip+hGqzRYgINFu5FtqD
VD3yIRov5HmT7RLRqPdCdLs2Vtvgw6izf5mUUVmJq6TMyNs18urFXqZIJllKy7bGrbXUIG8cP7xp
Jt325E2qqoHJRwxaFHCne4rKK82QfhZNc65QUeXQzDOZi0unxaoPJoAwZ/xOiy11VSjCtv1en6Xj
3B7zFpBeuNymDhAtzfWc9j6GQhhT3X3n72iNBCcIAgiVw4n04PgTDYNj0Ir/mdxQBZqNd0+Yl5GR
Obxu27Kl+1j7HSWhwDbpX69JyXTezhzH3qBKpdftVHraCuvRxtGWFSsJLbeIszCaVxYEysUKLn9a
vG4jzw4eRLd9TI88fyz7N3QBqd9dS6blZAL3ymITHgbL5zc+SVAUjY7YjhefFT3j8JCRC8vmtM3Y
H6ZQ5Vr2IdCoxySqaA2/gvvwdwFE4r218qYGp725Wg98+86XOdgV+mQf3r+OIy1rQ3y3eRqaZh7a
Pv6O/KND02zXoexY8q2cTwjyZ6Xwg/WhZ9MJ3kRfAI6/xwwGQuMv0ueKM8H7f8T7M1JmTZSRWqMi
lm9pLaLWZgX+sPac1s+2epB2A7oRPzxE8n1V222JfAcd4BwNVUDK3iX0KXWn2MZr8MjCtjnDCeLR
U8ITeCA9tOwFL79Sh+RUoWf/Xoz9b95BW3+TXntuGWly2g6iY2B1rtluMlnWNm6P2JQ1dsrssh/Y
osSP1KA9FbuWp5Dfo1gumQKO/lyJsOrbbLFIrOTKYobNvuZR1CnywXS3juP7j1OsQt4zaESguEMZ
7CVh1fq+VhVCoFayIM5UDt6koU1vww4KBpAE0/6GAL1o+L17c1mIdRu6dZuAAOIrSCu40p0ud4sZ
lFexjQtYD112TFfoOzsUlcHhEjUcbt1mPL1ZeTGMoBQJM6xyW8Fsr7GEv0mUUjjvhsILmNgjbqts
jA3twvK1RHpPzIG2GN9OMKnbAsKrpVJYTXgCrio33JzD8jN2L1x0vP681TSaeLfzTCN+bGDm8ZKN
TOyYoZfPmGHlKr2TepZh4qdg0E1q8ruguSlIG4iIXXdRTabGqSpfvWNfYgnA2857Tra0JxFeXeHD
m/6k6J/t84zB5elrKaq+N4GnrMUIIIJqmiBPxJXeJ7JcBaU9ag7HKT5Ifpa8VIja5g0Ik+GbmKNw
kau7ijl7sm/Pc/vHSkPxMW0i4mlYsyKbOXJS5akTTaddgOLesBW9lh/Ugd7lcQanE6kHlhQuo+mO
JfmS1NJ3NbfI4CEDqjQBo2iEIHo2BN1Ezj6dws1WaHOQseaH0Bkz0li7bvTUPcUqzKVXBOY6ESF3
5kPTOI+/11obFa/s9aThtrgnIKXaHj3p3o6aUoZ5YDx0V/aiyDBKqL1kL3kOvjnur/vlR/emPdmI
QSxMGKgYuf5fSYsA5t5S0x/aJ3/ThCkHSkJwEQmYb6OEGgrpMVrAAvPQnMs2UJopX3J/l9j6C5XH
oakLAD/Aup/Ko13l3ia0i9S/c6C9v6rypjVjNbyBdOjoJXsIqdwhgIovEgiIaHIqp8Z6UqaCnhje
xumJV//aZY2ZKWqGOgzJwZj87ymQ9kYQUOxLmLan2yOU5wcXAFj6vRr44Qt/yKfL3CT3YnA4cWjW
PghRz9hrdA8W0YGKtKi+y8en85prGDW+9Prm4aRE7USx5Gq3ZBPDDleubCI5tC/T9xksQuKGCX0P
3BqXNve31lQGdOL0+kG8A+ZUQCcFueu1LqC1ZDy7tmMNdrjMfZZhuaTu4aw/rEVaxEikVXdz9SQr
xDLYzDQCbGAj3AFMwdAgg2enSDN2ROAmu0DA9nldglYEhX2OzSEW7a2xxDn8Y4/EQvvVE4G6yQCA
LjZTzeUNHvi3IW97X6hcz7O2FQV6FJsT8i8GLdjuuRv2SjRoqAIDWI1VcenYs/phGOUO7IBEa+YE
x1GM9+Q+a7uKNLiFLmeYqgMnEahvjIiX1Z8kO1HmaQ7JvBPo712bAZYSc3hqOPYm39Eme4okwTkb
9gsIxkD9rFnLMyR5Hw2b7gHOn+5y9GncX0qQQJROW+WdIYBQErmc9imUmb5hopG0fDugnx7+2sST
WRVyYEwBG/KQWqDgDMkwx5AY+t/vOlPsokLMB33Etd9PwzLoCCIUKSlKiad0kUjh6xSEtlrdH2tJ
N5d9ETT5ms1z8xQdFD5dNV2w//b5GRysIYv+Z4efz/P3j13Ig6gjN36G29lpAb0Jeq853Ztqhypa
/YMjnXE+yM7dVq7Wpig4jnZFp7hczBgrcwPK2FTBCci1h7TmiT1Cb7RmyDUU7g6zMvfpNE2uK4jg
WirgXq5ESMEW+TeHICyArKR+KDP0Jt71QYaKrMLSEGJSpCiHI5GuBhP3Zu/eA9RZeg5eb9s3/glq
ER1kMQ4hFcNrjpZhr3T8cWPcVr58g2A5alwKBHfmf4009aXCnYjmdch1itvx3ZfVk4PBZA5NrAWQ
UCAxviPe92D8afq6gwEHmasyy/C80IBmOgiSS+QkL/gF0Hubf0b9bbhkfE33Mt5wtZGgrrt5M/yg
D/toGaSnzCoubShT795y0OqVPnw3TOa7A3+sOcYKSH0pGnJZAWCS9gJ692lladKzrLHJ7wStkQq0
q5aKNeiX7H2QVpDhiyWZMSe2IsexjgLzQe3a4E5r5Yfils5kPsQ5H1KzjKmvahh53gp1jxopGUov
2ZXHL6TE7XrgwVvfGtr3kP5BjDCY1SQkRbGYFcieHkxAcvGS54n27V+jgukN4evw5F9EWEyKh3AM
o6UXid5m6QoiMBqfzaU3+2g4Wa7Yi8WTkgrEoUEe7LGZZQvmvaXbnQvfd237bVoXeFkM+abYZg1z
yCF7DtZWOHfsM59WXhqBl13XLSgYZm2g3v/JaQqmCBP/eD08TNMaBdjYvw5MNHvMS8Lzc+ldk+5f
O+gzHK4bP5NZKaRhmmt61r5QLWVsRVTj1h512+NO4yK+i6/AqQXHh/JqkHh8FQRgH2JQOwp6iFzY
/DmFnWosHnku1x7e7T+3L5v0KJ4pmWktmien2AkMJjpzoF0E5IOU0MZ54AOGtSZAdUa9IsgnyfOD
7577e34iqxl6FaYKb8GlIKqRLzx8EOtV3ZvhJZcpj52daA2b3r03FDfErxve7wkk0ej54m3hpzfw
COthNbRwiI/2bQWhh3ctbe5UZBglvZUWG4Dq2Qsd8QChT96hpe5LOT0MlLzNDuL004HygNP5chk8
E3+QxkzmuAtSwqNhdu4eGSPrGrV7Zx32vdKX/cYLITD8dHDYuFGUCiEvAr1k/iaHrxiXF9MxCbHH
8yuAN1TkLAHRFI6LpZznzUviXMJptWyJTeOhW+Uztp40fCCBohfwdFsAFE80OUbtBMc6BB8HLqv2
ImeAIynWdf6rzpYogMBsIDA9vkRaiOX/A0nmNDKP/fgdRrPuF8Q2kSDt0qtR86Fx2HnlwfQPFlkG
9ONB+jW3+n4QNy5Jxnz+pQkdBL0r0dxSvjPXzCNoWR0hEOY3Pn8ubsrgBf2WeQ3vA7pkhFxBCamP
H93c3sUk9pfiQbO+b++v1SlsqEHz2c9F7zBqE9uwDx/XQGcJ1ZmbndzF4U1OChkhTAbo2KOY0Cl7
g1kG131cCMD9sJgJMI0Ttopxn+MjrPksKM7u/zVAaOu0SSkvxjmAWIljY/MYG144+s4RgMO3UOCn
zjs773lF5galtM0FPeiY1UAmUvOSLlZlQubcYq+C6/f51j3pCRiCAqDpxOcAiyozcWkeTlMXthL5
T3Wuo7KbdXYfkQ7pHLkyWPT/vHGst/J9h5SKnOjAMg+JEvzKMqUhdp6RVO0qI9kxLWnm+tYcFhXO
9AG2ey95IsE33aaYyrb1R33SlM5vL0Pv/NDtm86KQYPrdixcWUiTS/fYdxxKRQZAIPSxI0W6g062
/H3eG2UXiZuwn0eSfOSEXAcXIpKmPQrtiDNzlaAvm9/J+gjpsHijgE1eRdvZY8e84Y2JTY9MXYdm
QRdJaqUBxFdmLssOUxkgkqefHm9mmA2NYeCRX7sJs2XcaNhpJheA+YvyD8le0E/GNk/5U4TnSTPw
RaU4myI8qo+fqA4koiRx/j8At4C1/hjhAycmENTFWaYNdQ9ARRTbVwA3mvJGu2fm1yNCAF9JaPoX
a9nYp73M66fLPg4He9P2wEVD7cA2PpKD3VhsbT+nQKuRZsr3lIu77a/sMmMvGEbfCw5cEfgoDLVx
LJRpTu3VZLgJ2zlE9atG3wXSuV3qcvTrbxZ3exe+zUV0uFYbDTbBY/GPXt1eWV4IS2qZyD25gos2
kym1vh+b79R3D0GJNNXdTlxA7zgX1LEGD3bwCXhLGDskO7wfIzZewkZuzxlTfXKznrfDssflHztK
h3prCrfDgw90zaKYcQPZT9abtVIJC0anfdQKYgo0kwIB4s0Bhlz+KoEk4gp0LmVrkfzoaMUT3sN8
vcouD/20m9NqQGjZJqfxu29XTD+NRhr55b4plggKOcmpRGr7ievvNTt//bbYHabcnIjr6q8QsdWO
VwuIs30B8RyRkwSUyxTFq/ktoE0FsZiY8Xe0M2EW/0i9Hzt2aa+tK3QWWW3dQeRlDX3KgewoYMSs
a24/dMT38fPy6+w49wlk22gsOITx22s35nJ8rOfoeDSvowWMOV36lTR3akgPFqqpHm/jhwu+Li/u
YbaB2mTx7RnzsMfO8mxSEmCfIdW4hf1C2Qtsrokr91N5nloRCX6bkxNYIDm/jYkuktBsqRrRtoTT
sicNX5cUf804T8Z+kQNfufy5R3XmN3ycZJk6Skwy38ll+wVYCjmaXsnlLEktZRV2Lr3YYr/CXq5s
gbmnRUjjf19ww57n7WHaz2v6kHq1E+KE4T+P111QXC9LA8rmjg1TNukX/WgSzfQfPMxPHH+xSK+b
OCqLEPweHE2zecY7QfrnrSFavTc6wKagEEZwTaekGVTiYCZWN5FhrqstOQHFFpN2cQ57ZJUcudSM
WpQ+CNYj2BuA4Cq8x8qarIMoQdc5rtQukL43c50QsmpBE34sGlozE4tec/mvhj5yjlGrEDKMQSQg
omzpVgPCqMhpOmLrNdnWG0gOKvjUXfO+iJpe25DPjwf5w75GfCCvGSLiWW/uJS/4tJSorpc3PDtn
cAKfktbGtc7c4e5jR3xh7fNWlTygBa0+6UROlq+0vNKbZ0S1NhHqKcNF2Axrx+srzUMs8xByumhG
vSC5XaAx+Si0gEZelmUscjdJsjjW5OS3K1LsfFK79xdVsvJLBbdnMoafRGqXDp07vbofVioA75ie
TYHU6g3ih9t9ymmUjE9B9JRW56xBjDAJZGXcVi+rk4bGd0hGnAvW4e0/dVL+LQKmVrD4Jv6ypyHq
ZbLEK2TtA4BMHZfIO/6CJ2F/Oebfkfu065jI2ylLP5H/VWreg5krBb4xFq6ydap3yhREKTZ6XtYg
4ZJMmbWx0PdD8aRrLy7b2S7BhpKYrBlSmSL4GUmtHfWokwh1iYyPce8KFBls9AzHRvinN3v3TAvE
zV+cmM8oP7DL7F4R9bIGAdosiCfZ8nWPtynWwySzTHW1XkCplVzJp/sg5k27nB6bM8Qz6tzJVu+Q
Urg89uDAdxWYQ7SNskMpWQAJEPizJW/A5Ca+nTolJ7M3QM4usW0/2qAvACDiB0xZIR6/2Sa/fvsh
3KOMwctlQd+Od6d4gw4+AkfZdYBZsOk9zNCaxtiNtuE0B6ju3L8rxAuzLVlX3GPGiTpEoikqMEXS
kmoJzhyA0gSwf2VYx5j+aSDZCOzR1k6fFMmKFO6mInu6KdbbFvafdSFUpCBdc2b58fTquk+LG1im
I19clrETJKdAAruIHi95qdfI3p13i4jTKYOydxyadtJ2dgcTeqLywlgcaWon5pNPVJPDE6GE/3kQ
2i/Wojoj37y0PBX24ox1G9aJhxuz/LkEJfjbKpqq50DhLXA1VGv2vq4y7ytZLIQ55X110s0NOh7u
gmaSdHMKvvZ3Qb7dpawGgmaTWxSfelNj3g+XoTOy56StR5Rh+ErgU1GF8xTAl3kYGzNd1QLiP/4D
NhlfG/N/SUenvIXBCEPF4vMbu3bfCtQVFyBkjQQVDkhSIZi1VmzxNJpjAD1PGcrSvPlh5ZOFjyS3
vdwNSCKT8EqVuOZdzL1uWpR3IbDOG4B84y3mxgglSbC03xPW5RRO1k23YfejgJgpS1fupny++FXN
Wwve82r55rOo1AdJaOj3fgJUZYp2dj4Ytruzm9kYWWfS44qIrCCp2nloImlUcHb5YSsUBna2tGpp
UFiNWQLr8wC6L9E7GgR0ZxfilUWADXKyG9yoo6GcFFrK6wN6vio9Z0UDpM7DinD7XQsNLlOWW3q0
Vv7maaqeV49NJRpI75ZnVrKv/iGnaN1l7TluW33LnyxNqTdOEP5DIaG0aD/4axHoKj6WzPu62zld
d6PL+NMjCP3YhFouWkbe5f1Mczk5YFxiyL7FfAezrS7od+azwFhF13tZ+SgGtxkMTC+KaMoDYVju
z4y1wRHp+yJtCanB9uqBaZPadl2qoYcQWSbMCrcPi3o59Wf7QVH6IoAdSTR8ys/LLetPHviTtNVl
ywnDAreeara80hDND/m1O1BEF8fiWtYO/xTV/+FsKmVOe7ykAmZ/iUUth2aDYvCnHCPJ9mk3F1by
5Jiek1Ru8xU7yMJBYHSnT+Gs6CYFbcAst8rmyzDZ5v1C74W20j66+96GL0uJGuL1VrZYwoGU5aMm
JP4x5+ZltiaiOtXhL10K95heD+hiGCM2k9ykkNPBK6XgWRLwgZw7hz+Wv/+yTlWlbDI3zR1OWgqO
g0DYPBgc/zjFuwtttohCCCUdiNcmUPOayphQmjF7P105P1yVnmoxMvLUA/exm3mZt5QFcNCT9YCA
mTUZzthslINNcsf5gDDmXmz2HIFLylkAt3sgl5gdVAC5ktqWcq2BMF8LVlXVHSqqqTTNdE7TM/ff
n3XglSpBRmqKKsVHuIzqOzU+mIxo8yUV373r0lNJkMhu2gISiplKNRFgvfg7YPwaxwcaqN0B8nM2
vBk6U5cINqRT5I/vpnVM5XKtXjpRHLJrEbo0zb9SMUy5sFK19T67ItRZVj3GE1rKet3v3dopr7id
URfxbAnIBkeQG1NU3hNEiV49sXmdDstmwvzEuPvBJCcBVIOKWux2GYY3XuXEO2dyWV1GQAqAQ5zR
4OIcZM+CIftCo7dKZQrZzG1dFi3IJi7TXN0YD00VsRwFWnY2f12t8/h0IZJ/kO9EGX8LFLH9cpN1
JXVhQwG8oXpsPXQwuwlQPAKI28bNc0PTpbuqbNYe3wFqL2xFhNw7gI4NdCO+RlfjMdCwBpl8d1yO
XLCYC8sQzUq81PjUD6dloP0a5XeQCrVubLJdsbT99Tl5AWLRF3I/SEI1LD3F7o1+s7K/cPWq9ug1
walWB7zAeoc4T1enHxg654xTfRWxqEEhrupeLqtJxyCKaAAITPK9B3X0G9PyzFPzS33QFEup/obI
I7O42n1yClCooW09bfcJsy8k2oH6vBrexAoF0V6OfDAC/gtmMHtkOZdvWEKbEiV7X3WCGy1a5lhZ
3s/WQpo+fjLW5Dztm73AaDsfp9ZdfsfZGMjjamciRL8sTNGXeUWOOMn8vy1/C0K9MNhU4Q935CDr
k/zdhTNacQ2opyv1ovZw2Gqt9NnfYSTshPYXwgDc1yseAVjB9ToVTcG3Ig9pBvM/+Ii8azAMmaR1
duJLRr+Iy7w3H0pKR01FeKhWTsun+ZS0dm2xt4mmBml8ty9jScSw+mKQldD6LaqrX9Ly1zdAJhiR
wxfapck9YM1eF8imm7NAGSbkEfRl1tzW4b1iKDSqWOuuIBlxDiadgQktKLogmWaw5/E8Cdpr03iX
OdVylcI++ENUdJjuebwOyYMrZV8AWiZyMMxBvKmWxZirWFZvTE9CqorTMkLy/7hKjFzALzQEdJWR
1TbNA/n3Xejph6Axfadlh9/g4HKMSQHXBIrTy6CCYP2QSBUyjq/r+vVaW+VCKDLYAa3/taisy87w
Pd5sstissPSwZlt4hD3+7cK0eFDz+cjx1EE6D3phwpARbQaHIp7OeHGYFlDWLJmm3Kau5H3eUYeS
mRar7a3GOPefNj5+g6agvWD7JXdjup0RWPBeuNI7JmF21urr6q4i9/ETG2J15hO5dt7h6P8kLLVa
dM792xqzQP7gzfcLkn4EQSN2Wyy3Qg5sJp4qd3jJW9q7vIfQR6RGbm8AKuuKa7dZpZfxr2qAADea
VB3HUvFqn3LbVdOrf2wCBeDyre5zBX0ihaB1itGfU+keINMBPx8ZN0TytWFHEUWbpKqJ/sCLp8lc
ze6X8dAhfrtvORBWH9fh0LL2yDpjyIrUTf0mDr7pHnY6cSQYScZT3elwlEXeKMj0iKMyhk851OEA
X7sige8fKVslOUaVCvOKLvdWYgFjFNaiOGLDH3CgAeUSvPcmE+Pjjli+4SKTzwtn/EE3Whim4PsY
2e0HSiX8a1SXC/x2VQjYqeb8XV4D978PITa6fUVg/fIDKhgfqi87amEgNeMPDWgTGV5EsQiVFX52
vcOnyyKSou3WWxGf6J9XxI2D0qf+MLIJNxy8B+9cnBBlAsrKQgmaWK2T5OpEFuqrEHFNkRYIf2ok
vv30MIzKhmTHvcFbv9xvkCC2mwpROXcB8BWGLTkizeILP39Ew31tFJOxjqxu1b+rjhQ9ueeo85Ov
k9jIFgRszZGh96X3w0fvkXojwy0SKFtKypUDLzcCwRT8G1Gqiob8ORTkvu2qrl0gUYkgGTXOe22E
nT0N1gnuZyz5tmwiV6ew3mmGC5nH4ip8RHOMA6ENiivXqJ16c/jvscFt2K4jD2UTZG7O6dUyQEd4
V9q+SO6yfY2oM+NkVNy+Y9ggdUHv7HcrWOFw1sq4JrJDf5bJS9DiLAdcGTaPv5ZVJZVHQGBt5/uE
Cp0FNVSlWqCxH2hFp7Xb6A2XOvJgOGtsPFiB3Iqxp3P4r6EIrflnxO+qHBdDtYNR89MZHYicjeYL
meXKAFD0bvDTKSQBSnxIBry4A5P1gX2EFSmB69GgppcyTISxhNq55VybPymw9bllOs2VF52iVZWp
zM9McV2GgJFQ9HUDRz4NftEFpdGSiI0TnC9b4j49J2fteAEOQ69UQGrXaZC6lWsX8Rq5b3dYpymJ
MpN9UhfOhq48rRwKC2NbxoOyz40+nkxjda1UxNySV+A4jrHC3qnlCs9HnxaUxrkataeuOQkYtXKL
b2n3voc6c3lRCMw5xNvlyWBeHwucGV61tgRHoWhGeeTkfPq/jmtOwYRFGotJA559HnMLlIValQTm
A72Wvo9xI2AYMOzDg3XTqLJvEJHUEl7tnUC++DOL7ruangA3GqcI3ck0JmSrIMKBjdrH+a/KKMsc
E2kKbcHdMhHKhi/oxftPPPZAlGTD7iqA1AloOpwSHOLrwZgX55EzJbRrklJHbk1zddMztia5TRwZ
fn0MATvgfT64zozF6IoxhMTHtkWLi/7KiOqSmReKjBdXmFJBZKynbmG3P27tK439zieU6BYu9/2z
OyyS4/qUd/U9z8IH7WmSOqOvT6K39s1eVNH34FzDP1/1YlxBp/mBSn8mOlQbMe7PCptpVDK/y11r
WvAcNoQ5M5BokQIZVcA+iingDiJXgaaZnFS96TvOHqxlOj+V1LKtU76zkVYKMW3vUmrfKiBV711c
+ZuNyyc0XPvq5Y3GTrWleH+7d8YY1ECvfXDDgR01yj4J0Yb6xHXAxDsiHJ9M9GKoKezcMLOF27it
s7D3UbocaX4Fk4r2uAju7HernmEE3aM7QohX/4viOxGGdG6Ges8siidMqN/A6q1h1nYxTEzqGTeP
GU/n665fiFKFgXokyXIUiKUc4tqdKrMub3X5ePEgjwAK/iGkaUb/2CmY9nKJoYGnyIY11JCZCJ1U
35sZVBkYWD+0wP6otmyCe6tkysM2iVQRmWE/zMVbC+cqWKgFTpMDJbhH6U7/tjIJJKcO6N2RfiB6
juIVEQijEPEc/9xOdF77rk0lr73yzP/F4APih44yNG9CYF0hWXAHFjL8+GD5qBt3C6qfnlgcYFCa
dOYqCaTSwGgQUP5A/07QUeBn4ZausunvwM6BnAMdjjaeO8c5k1bon0tzPRW/oWtrVYbhN0tRU4VY
NjqeOu+zEikEnXHZO+ossFo58fvhDDf+GAEEyMe4TcgqE2wf5kR5VaVGxjLVWjwoGAkG7vzm01d6
zwXwdlDPJEtTL6V007iD/uc1ZofyLatzWfV/xoitQttibfgpwpYh11Ysa5rrkq/Y9kkKBQnHPejG
ASnQSEQOxvfqrFm5YWFuyfkr/0p1McU/FsP5lqsxMMCUKJwk+G6bEWUs/BE72BiQeemwml5RQJHa
F9ae39lripBB8aZlsWn9Hqa8MZc1NpDLHnZIYwxOIUJCCGhS8dIybL9z+TdbVvgRGUctDQ9byfzX
mMMPQTAw2wqtAIji9cPccisemhpGx+OEOr/3bfXgGmka/UH2xXdpngC22FCoKDW8FiYlhGslsIIQ
VCaWap5ubjM9gGcSdjUA6Qa7RlOKminS6beu2X+AnR89nMyJVKqfngZbQzGvNLds7t2qlBZ0bmpR
qtkAZ5z63bDHb4qG9mZmmVOARiN/p5+M6qC2zGqsk0WyLbp0UbRWaN+vSYjdOqK1dx7I3aXmLV1W
rocOa6KLqHajs4NtFwc2CLDro76BwLfuHoYhH3+WQVLQE8a8uXXBZVoUtkLw+DulbLvouMltakS+
RdwGtWazyVh72adcUK4pNXJvqNOQ/8wWbComHOm8fWaJG6blTrUjVhdMfirEccyJP0PMkC5zvjw2
v/XTq0T4CRiKe/Nu/d1YhE0v11jtNChouz+qAz/djeu7Yx5I3aTrHLl53ZMNfq1NK8gzZyva7u1D
G3uY8zuKgJAJdwLfINJrVa72LbnEMb32BaF0U3yiLCo+bcX049icwXYie2M5pWw4meHHJRuTYQXJ
s/B+VASxw8UABGPq4dWxfnPcF41jICnB2hcMb+cYmwhgat4dOKX5uVQkaX3XIT6fl51FnqkSU6li
1QphZkF1VDZxxRKLrLhQiup024/9YuDhcHECyQgOoN3PFGk0Kv3SWt9kSLu2sKLwERPxoQh7E8wH
C8NQBP0tmti9PJwbHnILZUtSdL0aMDWtHk+yW8qb0FgcxMW26wYKPunaL865U7c06CwfzOicGYBZ
EnyGEBdupek93nNXDuZsS+mdxZ4aFpwO0e2Sgk4+iISohI0MNAWZLF2e6gZ9OvsQdv//CT8iJbSd
rQXguOGLaHjbXefQ3FpjdBHpb+l7X7Kh1cmCft8LPrc0go3WJy5PlSFVV4B6Z8PSpwM1ipGI5i9p
VX1w6epUHZF+G1/WC/mqh7U5SPZgSo1oJSEusvr07kCR4gQ1kdRaHXef0bBtzGcnK4obxvq/w6+S
zxNepZRZmY81QapgJwGK2oIxCIEZS7N7Bgcw1nwdWIEaBAoIbov5W1ClVgMCWJek4dz+FhVmkJu/
I/PuhMU1rYk3MJ3XWEjXcE0EOCARzhAeAA5FBQdiWjeLSK6KZ46y+oO/uwFIfUSNmkbCMGPcF70N
/b0DgLTndquxnGqUvkeLFVE0MRNIK/sRs5S3dh0nk6O4ykAWneXHX3I58IHTF+0rkLj+nGMpcfrX
0EV1N9uHmXzzqYjSXz1q1LkY6MaRzE2EbsoWzKb643KAwTx06pyncNXGquLIDLNFeUB5nDR+GDSA
S7gcLWfplhgQAaO1vppVzDMRIdJmlDEaQsbJnFRw53VdnMU0m3w+D8RM6UoqlPndrsnMFJ1r2pC5
Cvi6t7zfET9R+GXtrS32TLwM9gXzpoh8/zXKlmF+uVQ9Vp9hnmxhmv6YnV2Z0+OhXAc6MIQThQqn
jaJSEOKSYkJGayhPg7EDe87tNig7G2l5PhMQnmgvKnE0ETQgj1FkqcQ/3n1OE29Hhb67Jlk2wmQV
DeL3T9y2NnV/+6FOXoTv4PNkwTxL/0viSXdwrubkmyoDy5XIwL9xGzpdk7o9qzd8s6VBv8J93VSP
KlipmJJivNZubjbsMnc7+Q3dScw6fhYbrslcmWRDkgjNcJ5ATKhoh/mAQy3j/IgurMYff4BUIRGP
iyQ/qE/ooS36CDPcT7Aw/N4RGpDp0b9d8+tIX0uz/0QcI+YZ9HMGIdCN3PZf4E1BOlhMNKJjo33G
mg0t7rPMKP2wsn0O2rv/UaQS5ZKRe02xrtin6ZZLB7d/ai8RYJ6yuU/xFItCnbU9X8vXA2osqHzt
4Eovsvj1CFknU7hj68jHj3V7jV9DS/tCi61rXCa+B7dnGpVqwEc2fDDOHPIVEoyqyxStwhrjcPIj
24C5bVY7yR2GBaWHCQl8cjxsUOcURP9Ju4ivbEMfsNWmXCwly1T6ifVMHautRmiR9gbgguIr0avA
9uCgCJuUqpJb86/WBz0J8dxsFzVIRPZEsuOAgv3VjGKzRZWtIYsNauvwW8xZ4L/8MvVlZat+qr5Z
/QjC+Xk/xVW0JCk9Oq6VEL52mmGRoDaJSPH+vOnbNcByUs5ym/f8c9cuTY6XDhrk1khyBzoG6cKH
c/wvf4VsOB08TSKY52pgDlcQqrDX5RCNh7kmzZdzQQV32b/jpPXey2J2laWz2dgtA78On8liaUHv
AQmy6dJdpnw7d/4kdk4BW5T0fLVuWrtyTWBfS6dnNd7LXLzUdn9Q7PV9AIYDqvocNGOL1YYxR5l3
lp3Ks9SvprnKf+qNSY3HxXRsOh2svxKPgUxhr3TL18EbPNVTrjWH55B13u1ilZK7EQKfyB9G3DCH
V2ipfQu1/peNaxv2zT/+HIZ2Q4h51kx9r+A3ygx0vAUc9189Zg6DpRSw0IFmhK/fgSJXz+DXkREt
xBsGRXP/d1OuzLGGr6KGXZ/LfoAt3GzpSZ1sXtF49rO1yAhzPZMCoSAge4qyno9toAlj2LQIx4ns
6UEA4TI+JdbhQfQfam38/6UV8nm5A6+RjEBjhFHfqN/bzWQEDXb6WZRrrJUb/QPGjwzAE6cEKDgN
aRXKgcFAeO9ZBqonaiO+0o50kuuEX/O4mgVl2bALsZ9naXODxKMjR2v/ZkQW8d0xUnuWig+coKq9
7dGwxWW7WiuKFkSKyFGlZiXva59NpBwiUl59Kf7UYNGlqjVKaRST4Qwrn6tvX4HcYp0HGSCoDWi5
aNSi8VLHMmPhdBxNy/nrhGiLwyz1QM14tOzPrg6GMWHQTnWyY2DBN9TKw962JjA50ZCgx5dZCmUE
ShJtVcewbO9QK2HHR4SuqEKdK595gfauubMyqiAlXydBHNDl6W72wXqol4qO3Oe4Q1pHgrcdn0Pf
hAh3mFx+jqs8aCGJPD/raEyADJjzMlWETyAU3JantoXOpV5L21/iSMhVbm29exKXOFymwJbOAv3A
FKgclrBwXEjJ+nwxNo0NjXI+pAPkftjD3yJnGW7EtoZDo9uYlUeDxKObr5gaCW1GkF3GGyrgtyrM
aF4rWZ2TXSQkQHI5p26S0WG/G4KhuoWCaNzyJX3FZafsN5PVVv/338wYKTw2kEtsIDDpmTNAV8j3
j0PF90nUfJ9D2zCXKpdze/+FQhN0KCVhWRol/+aPjzOXJ5T02hcVZ/djPKMZdpzbGQaa9Jsw+Xhp
fNyp4lncer51k2J/P13SYw29e9Nx9+35Wvdn13eWEhADr4JDhhzNbr5bJhWSt7PTS4vyABke4bx1
Eie7Vi8yQGm5BogLAXKzG8py1HVtOcg/BOuVZ6EpVn7a2xLimPK8fLNYxjMczhq53bIn/NLqt4/r
6K/c6xB9NlkJ1ggZnXRn9WjcMpnlhe9jmRUi9l1iF5gROmlr1Xamxv5P1OmebjXbZ2RP2Ci2BSNg
l0S5diV1EMSRnUZaPDAYrsQ6OKnQQ8Itb4qNPACuGAPyJrJjYNycC/8XPdlL3/0hT/RgrGamGODD
4oFPRlPo91A8y07iZVCbxFmIeLorWx4w46Y4yL6R8qkh+oSE9cxUjldSsykHLvq5Tv/4DqG2mt7j
ChwDBMOmIjPmHkeltoYj4MJMjpKhpF/8UHtAk71jmeyClRO3xLr6PMsASv+6534F4aBNKcvwsuCP
ce5xgUh8Oq/1vRDxFDhLcXPRjL32UKTp6YrB+3f69gjgo5YBfh2Z0x6f4qYMQ5te/sEL1eogUpJr
DkRA/7ZwckXl/kMUXSUKUgpuHHvOfGmIUYUL3/B9N5hg0UqGqttbtOEGks8g7wntwbzVaU+C8KS0
nl+cT/SM4UHo7ELIoVr5dUQ6ESR3nSSBB3Ysjdr3nashkfbZCqgo71voErtEjX4mRQF5A7OxVEnu
JI0vM5fAn1WF6k/LHVFqF+ujSMmTRdTW+3Ms/IaQbiYVZHQ+x3jOyX+g72wiXC61cWum7qdvnSQn
VT6/R3WhsQ7MQCBfsJDXldY+4btUjgjgQT4zxXfFz8j3VvbsYR+2xuLsr0xF8lmyuoig6W7v+BcC
oiGErNMbnv9/Ot5h1t0ow4phzxEUbylj9y3ODK9u0khsQk5pL3lr1ErANH8dYc/6FljMCYgYkDAF
klKMCTRi4ic2O/Nwdq2bN+YIVBZYqgNw4Eph7M0BbB8By2nef5N+JRhBdeObakiH8FA2KukrEJxR
pDae/NHcDQbSknhNMhX01PwdI7wiYZ1af56CfkoNX3RKWdcDG9kl61rzvP2pfFeUuqOThWiA2XbG
pqYCA4itE3z0LuVwOLjreW+dq9Po+HPDs58fhPxBPgDuDvNZzu2U/baos99U5auSdoFvN1sMeAXC
59DbimMgi5gIePNYCzKY9jFGFBLAs9wo8O2yZ6Ky+neDzXFhSX7Wt5Xk+aQAySMrFCLJf7pP0z0R
XkJHIIsek0nE6adX3texT4XE/09+ZvU082Na0q6nSFZFnbNtFgvKXdNv1V00qqNTZ8nGHsOIPM5x
UcrYqmNVw/lpvYVfxTc37cbX7l7/wCrbtnsHQSTvS/jY6RNM3Z/8gRdmGyYYd37XHYsk23M2FLWs
Ph9b5HFbIjSRQP5cDou8xQAS76XEu9agt+DMlmDfYlAgGXHZ0MLm+7tWs9BMH6J8JrLFXqbr1VhI
rHZXFOnw9FnStRYtMKHUZ8WTG1fnurkMQoDSbQ/pUONgCOkfcsS3tHY99EgjMJCmMu4dwR6CpnsA
Ia23qSM49VYFhljTm63Lbvf5TcwsqdGmw9/nxhx/+brhzZhRwtmgsF8uvEEBtg7HM1YslsrSnrWO
9913aOqFrW+ikg12xoEtgFOoapnSdG88q5Qql7AhTlmnjKgWgDY55EHYtUh5cdOT6D8shtvhGlY0
hIH1Mg2Z3fPHlE7GzhTtuU7lTOuoWJKXGAfa1dUTWUeGwaXL3uHKCDOofBZzwm2dsU/s+n89R5ku
gQbfRwyZkk/h/NHeSbSiU/7Cf/gLIvLJIm1IIZZ9VeDm0XJBP0KXDW0qUcvyOF6sGqWzJYZBkWqR
jb/Jt6D2S4qWotEIYR9dwb8IN94u5EBM1n982QYT758ROKpGDAM8IaR04Uo8qRv3X9Vb+wOyzMEj
umg62Ymq2qy8bywNZuNUtIYuTSUNVC491xukIEGOHn9WULl1rjYwdJpwseaFcQWmuVWD13oeN3VI
8nCm1VCKV/UHk/nQ5+pZVvW7RHqbldzPFCaWk419Vn/OODDL2hX/u/fKWAch9sUQj+2jQLa7iUnP
DFEtRbmi5ryvVXqgv8Uh6jOs268uSRxb0khcgdLQH39Ud2pUI86gMtn+TDORF9ars+Iicskhw6kX
KjjcTKgT3sFjfJ4sfD1ypiaQtTei9iovgrhdk0XoL+joiHYyh8FpgswEl/jWDsh7P2Qrqvq8S/Gb
BVSJWzFRZKM9oC/PDeN/jKiIrehsEKiLPBjJ2e8Awo62xRCwH982SR7gvX6Udi3M7Er698A4Tgu+
0tfgdliVxZBj9zv5IOyX6pD7ZXEJXgql0pkZfChil63q43pouDElG0YXg73YmgFkmsiYALYBOG34
mimKBpCReMunIC6zQDK4GI+NuwTdjWDbZedvbhy/95CBMddTTVp7Bj6/P5i+6j51Fs1V+EdcM2bm
4L9rTT2TGCGevFeGCWvP6CL4j/JYJ7NsrMlGUtT8fDv8MVjF/ZBWe/57b4faktlzGkKIj0Zl3dHr
EBUkQwUbpuMJCLhSuCjM8SSmP2titHlsE1TDzUE0E7E1XeSwt2sU3jZNUSSUCa+Zo3RYDZvEWYBZ
4Ufis3sRxgsREWG4eak8nFtyKVPlEGJRrSeX/b0zJrTQTzzFGwDLNJz2Ejs5WFsQpOd6vJVrWfd1
TVzzgQ3YA0pdMyLAmIEE3eYBIxjYrl277eVXvkeUHtkuqJMGtwoAinLo7i6zJ27wVhPjuGqEC1zq
EbLHm8Vg9MptVgP69FxABehaK+Iq5f4g70E0D/1zcmuzP/sJstb6t/r/RAMHmQl45SOYwvaenvHw
4d9u+bqtP+Nxeuq8GTgdx6fuBO5+HKnOvNDoZmMhymPnoR07D7R/lRMMLAey3fKJ2Xh+T0O1CN1Q
HPJU5N95g8UlTWrOskEa4BgRY80Q1uq2lO+W97cC+vhEH6lrA+Sh4fwPa3DKTnFRionOhBphj4cV
v5dxBSwSrzgkc0EoMa4rpo3kxOjRHONI1NY91Z/iJRrDNWYphZKamChU4GJTcSz38Cw4GzOUCVf0
SHxG27/ClU/Rwsdkk3RlLA6ZyfqQ4nkDcQ/GKXybDyZL/ztwiIWzlX7/xfvVdf8PB32CwXqvia4v
eqihiyrTb/aF6uRr1C83CAaxQSAAgPDaF9UbqTpmBLC/dhS61V+J09Lg0Fx/uW2LASk4N9ojPHW7
LYs/+DALLX0zmew3zYIvlDOlKGwdVKoSEn+co1yy4paHpWzgCxm/uOEi93ONZVVgMXetEE5cviEo
LnqG7Jw8MDir1LudikdGabHsuhqHnJgRnXGaVXhw5hbz+uNAWm/MPJCDQXM5z93laZg6mu8ZFqJD
l2Uz5aQ6Z57kbVxE839Lp2mw1QHvLzWrbcpsadPzR4u25gARe3ft6xWBGgBPI+br31RYh7yxyKN7
v0wmHSPkt9fgRcckq1KzorJr2ZtrOToJkU+nxDQadSk/N7FE+Rb6NjJddlZMJ5bSLyDmWwq5YX5b
LkcUSJ6EQLFL3j4MespqaYTY/2I1u9+uSNM3y+A+VY5YXIXVz551pw594pmgG0akEopsIwX0e7GT
bISCO5VUNsQMQsEIeDyWbmFy/9lmCkKTmhN9my5X+CcpXedjJ8hVl/ho3Zg6dAWMtoPNCcGGDKGE
WA5n7ikuYEBU1TEqga07VJyqvkhcdtd393+zFZqcX7YQ04913auvN9yyrV4G2iAHWWm9jvbZ2plA
g0+2WHcLRXrLHX8UVkDCczNKVdKysLC3xb9S0Q2ak2LwGG+QjWuRdBukg9YI0m3lJ6JZiD1ZGZ98
WWjDYgv9eAUpTRo1Hv3dx9jfebk7o7UObHGyeMb7cDhJimBYuAYAgOF+QYS4QC0lGH++sibo35xv
tqejkuPXNfeBFfLNlFnQOYaBMNph9XSVrAeGA7KfoVSIfEAupGllpgs6tLpHDgw3rOoh/kd6yJjd
XtgvGJoDhJtp0sJ205nIFtk9sN9RKDxRNS4Gbp5PdLTrnvITqLhaKq9xoM1/m/x5FT3m0fvuZoNR
qhSkBx4XYscoh5pMFpZ+JDYNzj1KyUh2RR8R6Og2UE5mlhTYWuBndDFaXQAe8ew6FVOH1464odUK
HXoFde4NYTKC+D/ojTHsKq14rWZie4GyVvFD6gOkashaTr9k+y68jkdrPvrDX8aHO9IKOvHs6//A
lOLWtFK2baOnl8irEd6QaK91UGBZn1mDLLJCLG96KgTp5hXPU6WnPiMa7ZFJhj0VOr/hXr1TJGQH
EceUatjTPCyf3JEPwPvPGKGaH4qDAzU4PO3YIKyIe/MYcXaFJB9EzwLST26Di9iY1CRREJ5f2SRO
2XhRAkE9DF4Q4adZdNx/WeiCy/82tbyzEeW1c8r63TohTxD0euHuG3waPrKgHK+kNthtgHIXLoEa
ZlClP6rcgrHmZrpNFnSsJdxAjh4mtMmQKduZDHHZF66748FMOHS1Aadt3yOTEXFWiZIBcfLSAqXV
gKE42phy9+RSFrI070pEdaEVVy7gMj6ZYzc/G3anFHis0RaW3BCgzMtZ7f9TCQ7Ec8IwxVBwNck+
VWJE9LQ7dasSqBjq6F+PIx52GnuCdD24DyFXv4QZZcrHWnuJir4CvbpmL30ED50qQd4UKxoIboLu
bPXZqBk4BUd8ljsmgI+TCIiMjWY/qW78AhO+9nFuTRE/VyQfsCKjDms9lA+3sHgXazfCuPkXvQU/
HTPu9ryUyQ4lDoP/ZHA7fBN7708WC8+21SucDZFTvqKRzbyaZRevXZOWLVJHyL59S7693iX+9D+3
wLMWiXlHJdSuEDWyRDDJ0zg6f1ncosmJKEy1mVgBs45HBNvHf5uLEkuZkeu0UzgiZ0xL2ltL4Yt8
Q+RI0n1SLKOSHNeWJhFH+4Nupxx6Z1rQ3rbyZX4OLzAtgVdg58MUVE5IhO++I0teI3bu6ADUTJAg
eQlOF/VzIuKeRnVHmlCcivVQggf7ZnVGUk4aJw13BjIjNrJr2m4rbI5Pmqjm4l1vHEqKUiFweJ8E
m1O27+mNX4wuEkem2JQ70Pc3AJfk6fLBZt8l7r8eIJqQXWQUqoHMIHdADJyz2qpP1e090iipk+5w
f6WwkNftrSKmmysmJBY0RNDfxS2ls+UiPAjtMZzjnlYWShvS3lixl+EXNWrP21fCTqRHvRDVheTZ
D0r+m/LoyHPgXDB242oQe1De3/KSKtmHgMyQfLD7HzZXZA/37uCRHR9A4Qy6sFfnymauQU+dYijn
v3v4TEKIXSy5UxY7EB/fuKJ7fbXpovhHqBymDsY+mxi8/gKQg7xNs5sIKevN0Zlj+c4n4vmWaX48
Nyh+q4dy6mMHxY/cuetEfjoNCqbdjOXPCChDPxZJIalXKE5LCe8nf6dNugouEyH7vIzFVus+qnnY
D2acqItCLe7ZoXPggvzSJ9OAef6b7GJUkn0DJU2/VNKLfe1B7mlGSBIPiaoK3Lx01nQMQoPm/TsY
If1J4E8KTZhHb2t56oFQxSxBhKv3PtwRaXvnngX7mISU6cC1P74gnKp9RZMQNee4UneatElyhsrS
yLfU5UOjS4Cw83yDjEaznyzcPy6bPF72OhVxrXM7PR6CaPMR4uzs3dFUzTsiuW6mYHyoeN6a9P6m
r1/bBdFEBZfc+YRzYsCRVbOnA0ZKSWXcr1iHcEFwTuiOREaghvnR1JKKi8DAEGjuRqKy9pyEWJ96
Skux0Pu4DT1rCDsepxTbGFoC28X3dvtwv2grnY1EnuUXvuFHLJSg+HgGfroObcc+pq1duKKrD7mF
9HklP5xi7hwdGATZAZghRckrrJUSWCyWqe5ny2z3XKnq2oLLZ9yH2iFKK8M4nvDPcvt2VD1apXWg
120rhLwMvfyZ3Y0CVYtF5AriV+hjOQsVCF/dTMaFWZCRxKWtiSFmjxUcwSZhEsrewBZZqvNghc5a
hfvpEHPwMbJLYi18otI2YfLVp8oUUZU0x/FD7T/h7C2Mv2FrlFnd/LwkjaAIVBi644FR/KbHBK+f
8ZxkES8j9gPlHRvV/B6NpAnrDr4/FKpCqyViOsoHHJGWbDKN2SEx+0JO3uC9TITg1TTKrVxg7Gu8
IvqP8Zm3dFWuddTRAJCOfk1GavG9I4cAIy17vMtmc1zsdz+9jqvBgZDAaIVHrZtB8ca2jP2JB0vQ
Qz8d1v9zmG0nupKYa6ESaN0zeytRBLZpLD1jSh3D9hUZMWu+M6eODd+tfaF+fIcBfliqQHkGnot6
cloC1xRNdHaQVVwxSDZi508weP4ttualeUPsmqFuiy5NfsqYK7A0mtKVDa9I9z1Vi8/HlGslbAX/
MabbzHfQBgzYDVs5UfdeKoJAoLeXp8WMOwMiThno5Km9nc0HR1c3Ry9Kyqx0zrTCKzuQxCIRCkpa
daB4fTWtPKbKdqEi2sZM7zJLKf1ASbUjs2bZ5M9v6MNu0QLnEJcI3e4hoqQxcwwtTAFUjz4ET+YL
3fL+1ZdHZjWhkPReu/Ia/q/Jr1w/Mlj+25ASgsWRGPEsZLzhLjv3lv/IhyPArSQkempNEECk65wz
Vdx1Sl3VgMNLiOh5nTHl0hFpQgJcZMR9uMIctycOA77RQrra9A6I8zRDe0KPp0eoMqs23PBD+/h8
UM9vVCXGZaWgiy7fPb3Mfgp1+GGz3KFE48rgE/Qv8lRBuEaqdHdOtG8SKsOnv7UftLlbsuFhtbmr
dsbazR7gTXZTm1HcOfAqNrSGY1FmiVWm/Jd+AZ3CA2kg4nlUYxOXva+OdYOPc0uWQ25Mt3H+Li0H
b4kcVNtzaNm5BtQOljhlPe07jD0DCniAcR37p+MEUtqMXBK66AWxzmON90pw1/iYDjfu0lp9TzSM
1WsC+uaHqxXha+ruXXkzktm4novYW9tPv3WO/31a56E0vtv88hL65m1Yp5pVsn3DPI3kuPBV0yg0
FhP/HRenSgGsaFJrZE+tfs0hCkFzKS8etCOErIIoqwelZGkJ9VVywVRjpEMov5KGXcAFdk6W+cyE
+FZzewA/G2yoBrx5yNtl0mKaFIktxn+RfdZf1Bz9f3lYgIeZOc/XrBeHLZLGMOY2cbkOzWo4Svgc
EgPDMo3WSUZqNvY/8lduQ1mRkZKB6o4cjtKmzfNYWJiegswusrVd0XqhSkkbIIGVr0EHByG25+ws
wg/jYpdy5TLRH5d+rltC0FoHKnuieR5gUtjR0ZGQBz6dtg4rkIqqjBCEko1t0wP4/EwuDAJ0S5Av
nxEG0jL+3jqTWpdu+ptpPyL7REP1JnZ8IFWNa01+GDEVBbXK1D4qxtcYkksMyRxFfjtMURxSOn/J
qhistsaKBdH1jpZ5Hy11bocfGCMfL/1+XhC2bhE50z7CQoRNYtbsDuPJU7rQ2SQfLiO6cdsHExzS
OhT8an+4aAm6TQOPfuk7+xGDoKphP4wU7dqXIQg7cQIy1jIgph/dwVTs373KWQa22sUvxD8ds1IQ
rDW2XoxAAQ3sB8aZ1lwE705Gd1q6iBzrQJe/SxBtRQ79fpEwuV41ZJ3/EoA/b+dTPLD4k6B5wdJ7
XaX+MxDxmK/HLb5d5EV1McNR/rGSRB04SoZND94kKMABfO+oDiWokIYcyCN9kde0xpvCSZfef4SZ
0JqQKJkPl94cL6WMbwWtKM+smQtwhbT/YbEvC1+J0NAFjMjHuKv/Q6EZ19qnovrxz6x57tKiOEXi
naI3PVVc4yqr3vBEbX6YiVUKiDkVtQbI6cxRaZiJOEgDNmRrUOTP7ZtqZbAcPkBGwyCzA4BH2UlH
ZztfW/Nzg4SenAHdiFr58Q3nJiFfRSWIr18ASiYaoR448iJQF80NvlXHuScLSUUbpsMKmaabIpRP
MW5sk7IaWon244xVSXmRjvh537PvihCGHDPWcR1zkarGTgbIoNRk/JBCYIP61M34Yhbraq+DYIp4
gbQ6E7NStHqg4dreVyOpz5ArKR4x1vzbWd78gWVMo4npAnVHZ4iU2ip+eAq0eQANy1TGmU3BqbAe
53lI2J+mLmCe13YaEzv94LvCokjhXOhurpMpleiZiTxTPGkqfSgBHLZGKELcviNNWFdcvALVusg8
J5k28g/CjGNoIYfcvRmwzxwQvxJ7Gka56EPxGsf/+J5BmaxPamuIDSb1T23qVKS2qoN2IcQ/IiHJ
b693o6b0Ixig11PKwlEbU+o8+XTiEnyV6+IgJpFT+rr4232XT7WjW7DjG/7US6o/GIaau50Y5LBx
UHmS8BuAiat0nnpScih5bESqW8P44KcGAmu1naItlbh79nvBDI55qJyV49mfSZD5mmEgnkS8wbix
9KEj2vnX92BZuzekP9ivp5kVoUVM1xbAPfwuSc0JnyS9jVrTXyrw4eqdwGyDbF8mI1EEB9QGJLAf
Uz/oYpxLgTiR/Rl1cM38xIWM4bhrgHwcgMfsZcXSShhRhCpWw0Tc51ehBPhkHNHKYWmN5ieG1axP
qq7Az67tvwMi0nb/5jKVxLWNze9RUJrtqAH/maLMyRriw6CidMy0NlC43Dqi1kcnxOj9yKkiTf2/
UhYJP3z2OQ26+FDiqGteuUbx8NQlmB50MEp0doy49QSc91sVoRiNecc/WKaXZvWRebKVLZuEfFpo
w9wRL+lC1qN6nxIR5m+jXv6XCksidzX6zrs2Ky0frc5fUsEI6J/yTduUQQHaMafY1+rrmng32FYo
6AFHTmNQdtyH4spvTXcBRNp+TWgdRzfZXCsWZXXKL5r2TPB8q1ueIy7qjHjc1ATQDY25H/AbIYSC
9NqUS0j6HUskOdbsrMS4nO7vh3phzT/v322ztZDQZS31VQkEeAchZutgRDI4SeyjCZ2ylhXT02lf
bB45a3SWkSdAzOo1ezbWlCy3ImMoL42+RXkbJ9UX2jloVRBjr622KNwXQ1aqXBZs9yzoWOhybNQi
U0MW8syaR0m2Gye4Ljc34ydm3X1RLBTrsQIGkztKgTZD+twseZVfRzyrVjZJ4Lu7ew0g809IvE3B
oCpoogN+koXUov0YYtOJvctbM1n/NenqRjzGxQTzjDZFGuyJNe3FER9LH4o7dmNvibXSAgj06v7D
a4v9KCeERJNAqxzeApeJQBQErwerAh9nIAox5B+PESFwOXbfMdkYEZl89UtZB8868nf14XF4AsuL
WHYf+OJbqytVc8m2h3FmZwPVUKMJgZxuceeI6bmp1c+Oj/eFSllIOq34zwWufaDlWBDA1WaUVov4
KH7K6+X/4fowPF7vgr6YIBGi/qtcik4okS+Awm6X2Em6qL/i1dDpV1KemeC/SBHCPT6UN11b5ed2
7/lJxifpk/kPvajicxjFBuq0gKjiFnqR2HPoENwQ34ixP6MOG7xaq8ZbhKp2tK47ue6SLh8PKmIg
Yl0MZpAvAc5jXQpAJGUwVHyX4AmbRBfCKdGJl5pEf/Y9ejrPLC/nFg9Mz/eC/B8K5L2Dy91NvVL6
b0tR1x6m0EahT30BGpzyj/L8ulke4paJ/4r+IypD2xxm9WZdDKoUcuAG+IwNO2tdSnFJuKX+XgvQ
Ps0ftbH6stAY9ZJEDH5v6ztkFPNyuOUZpWkr6TBw41W0crLDLtGpGqZ4+TA2rGlztmhAm2uUK2DI
G377n9L1BVZFzVp+QI+yVs1eczldsZ527vWAKxWvYAuj91qMA3xjLs0UGB2hIXL5x9+JuS8SZliu
M9FDzpd0PHv5kXbeB1i4RNrEvIVHje9z9FLr2jNBmA6Qr5eE/CuvQ/hfjxW2yDJsPxcpcLbBmhKR
J3TtBO5qZSfGxeLo20GFWTZ6gU58oYHkUktOqKRrN7tTvqCL/akBvBx3FafWQg8Rm+oISZiejyEz
/wj0OyCd+rOIjyBxdH0AqtvPmwkck+hn+JP4W+r+mCoWgKG8ZpN56kObbz5V/yy8ewIy/1Nj/BGr
kckAnAyzdvl7P3zNcCDVgv4NMcqOMX0qSIZHqTfrolu997+zgoPRGG8SuvLwnYCPlnjo5vGPH8bg
psQSusmxq2p0x0t9Nv58dFRtplNhzpRz881LSCGCWsz5S2S5sIIL+0KeX6TPmg3T0Jeq/as1hLb+
GvPImDD3i1FBNi0Otg8kj5WPtP73z87USJOuomG4FT8JSC2S5PXhDIVFWV/FDX2ANNTjRhBVv7cv
brK37bH2Nfcs76MklOPVt96ciefGTdn+VHPAOhVGtr8XKTpioai7wd9vWXuMc+dpkY1eqmmVgC27
hrFp61BXxNVF461V17+UhPu5FifwhD8b/lmO3qPo9ISa1OPIcyKxjfed39GEAtJbKpn7axmcmBcm
PwrF+9LnlFOJyyON3xs3gNyk024HLyCS+izxvvcYyby6G8CFBb7Atytm8OCdb951erM9u6H7qmsh
unVeltMYZUkunEZFylrjvYdylxAyXm8XYRjrpy5fBzxlFIgkB86aoTMPsvyaHjZ43JoAIHiF3exm
/HCkW/pyyer+S+cUuOyvokaP+Pgh3GFxaOQe/gpX4i9d5u4kUIAZxkjRKsRuqpmS2Ac089A7dYTv
TuTSqWXXFAFIKKM8rI6RkfJwY0oSUKjgltZtuDuk4wvxRE5KtrOPyUTv84kGMVZ1ktEv3RxmVBOg
2tsSGitpRq117FiJPwIqjXJFRhOAdVZxnTfkddzlEsk5F7gBVMaJkTAL6P1ZQCnr9mr6d3cExm7/
RbDGcPwdcQq8jg0VYPd0B5eFcKNVCzIeU202hNA48cBkeuDEpD+iXa5OQ2sGVQYYJAaB3d7XmpKw
9GR6OeMZD7VJXYLksb1Q2Ni5bDkc2zjflrf4Xs1rioG1J7oINeBdxsP5fDgu7MmMqm/VoC6BNtLd
978AT3WdsWTcDdODC4vScIoZPEMM83hVVNzW7nCsIkFIjrbnf0cpbdFUbpfRqbUs+PnicMF0r8Pl
KPFkG/7aTGqReYfNhcnqUoMLY13Wp45HB1uj+3pk/SuVuNvKo6njeNT+B3xH+vxsDiEaBbWSflll
mXEHmMzefd7cn7ZhGil4KuOmgPmq1ldKM+bCdxyahgripgu5DbSF+bHj7oOEBJJjanli2SfkNRsY
aAAaQMrr1XsggJVaZ1M5xCCSxFnvQC1BwaBDgPnw/PJFy5Rbnyn1imdWVztqdMR/mBuqXrp4FOb5
iNEDGspt3LPFTe4nf8MVArP16+wIAD05tUi9hNxtqT3OuQIO9N6IvdOktgH87BOj4zXEdrqaP/wf
EyeSTT4x7y7sPFR8FOHLJbgaWu4kAeQh+H6pzSDhSBwB5N76R6kvqDn93c7OvUQsc35MJXvyOhu+
tENHvYHilJ8QX7mfv1lRifU9XqBOnegE8nx0VqOIS7uVzHFfG+O34bXqmN9Ik8cWutDWIYBqtB9J
TQXvHRvpqkxfze/iT8tRWf8wQJs2GhQ/F7gfLBKL5a/d6sUPdr1Gp5ak7zTtYYHTaRvPBRddjr11
xs+N8+Wm3rMZwOgAF8zoTdcQXomma8kvbclTV96OcnsWAm/9z1LUWCGaUvwPQYbYncX3sgO3XNur
KMLfhZyCNB9OKOrrC/k5/s5k788EjTjrFNeUshBaD1co9/W8a4eO9tyBzrxXmo69Vx0QbwvHsceH
H+KmReYQzfkbZPaWF4RrTdkgrhiJ7+LOSZ4MoPEi5Nn6vuOFGNz7vkiAUycgRYZ4rwMA4YkyxjKP
mDeVx3FGoyWOKpsX82s7bz2LDCkUsC21DMSj36HAcTalB4ftptp8gTgKvYz3ArCsmDPZWRN05XZZ
WH4d+VaDrBMwVZt+OafhsvH7eiAPQlMs6Sb7bL/9fL43TICGT1obR593TzC6By3y8S5AOeW6VxOo
SODwVoPuBdziNnXKm/0i91yseQgG09aCF0aDpn40djbCTx249esP6pSsjC4Z2SHNsnxXFy2sbSkS
jxlGfMNmTtItowWMeGVRgSzNUfPheomoEW0jvoeZ61mSi8gxfqblYIFD+LrYK37SNvuXobHGFVfm
u4kqq6vwm167a3qMpXrMfxtgWUzdj/o7Dl5KfMwgJO7PkHEa7oY+Q+uS2KlkUTi/z2cl3grH9z2p
234pVGmIv9PTHKUrah3oQSLZ1PgXUI+f4/6ObEZ9M1/mbsqhFULDqG4IWpeliHwu57yI08tjD4/F
LZ21154IufoWIytii8ZCbvGD6goTNYl2/50us5RVVZwwqeKgX4iLOdWMOZwkcmNHAKVlKb6qtalm
bpH9+MfbA6wxf+e3Oh8U6TjJw8OBrce2SYTDv0Fy/sEjjIInvB4WE6iOGFph3kJ3uYPFjp/c8cgl
bVNxcgcsBJifmyaE+33Dlmw1P//hSeE8pNXf9sszpzGDuxaSbv7ZPcGai/mltLpIoe+Y6Gp1L5TH
dqgRzlyo+iyNx5jNzcuOIt9XzkO6aFLsuxK6pxD4q3JaAfUsaa43BCh71orDRsGuftZ7C/8HZzYQ
Bx/Lr/5UdhJUDKa7sRhWVBSFGX03jUOwft8/JAUAOtp9Zz8OcUhM6j9fLz3Pe1t5USr2IHL9anSJ
5kkWzdcukitjMlELWWYXl7lgIyaKU/kxXrVlRPxUGFFM8yhSGSriFJqAWALhkPBtKmbLnI/FekGA
boYs6o/aB+GCdQqedDNEG1knItf0WooqmX7bNEqCbVlCH2U14IX1EfTU+UP2kxiBlc6Qzjj/p9CT
8VVNpJS+ZRf0ShCAP1QcdsYCpv/otnv7nnoZH8tEFL2HWI5rmigsRh1V6J0IWf3TLWQlznPXsEOr
/OOzDicv2ES8fnRZFTGSyBCeONvSpdI2VlhSEhpBfPHnAofIb9iaitexST6IVxNjQrTqcXOl3XlX
nU8RgjqUqVfSGWyHR2UnfStE59DfpNwRmJjM9dCi0xuSKoLG/+OiMkdC3FA7Cm6mJyqmZqY3sZ2+
2mz0IKTgh0AEpU3bk95/+NSNG6/tXiQbm/sxtpovo9JiWJGWtQCykh3zfCQivNVzdzhw5/GFgLWw
Lps9PSTZS9zH0w9JHO/WpJNTLU241I8JY+cynCLaiAbc4Rqbmbw80YNu/VrqkimL5EEX4BGJ7XO+
rdBnbgUhnkj4y7cGfsKl9I0elikCJLkL7F42RGRVdmapPAin2AmkG6/Y+t37vkIuVoeN0a0aQymj
XYMAgge37UPeSosdMtn+Q1ZrT60mR6WC68OISFU6tyhqx3mPTUEVUQiiokQ7K6AZLULItK9nAon4
40DklNNt9Qntsm5ODYFgmLZ/vot+JYP73nPRKmrWk608V5jLkPjXxqYN4Djog2jXZTcNFERWJ7MT
9VOwNzeu3xiJ/Hoc/YTLYvr//5V3amFjICaXd7mf1ZDC/ZZx96hVJ/VFpCDEbb47JdIrsmUA5OMe
Yh8arW5B9/DdisxtQjSP8kppmpCIE5gNnLJbH85mVM3g5pHg2gHLemYQqIBOBh5RKrbPmmsBGlB8
R4l9eCAJtemgM9/T4DfXN6zUBIJQUhYkucmmqeuVGll0Yhv1daPPQNpvQFSpY7Zl/WqPDxStUCKA
29D/lBvPbrPm6+cHxFHuJkBMugOJR4m72xJBCPxzyVpplL3W1DGxP+0bTYHe1gXqslUOkBZ3wmeE
efJ/GT5mnKVhZgt5NPpl9KPrhV+d7s4UaLGsu4WbQfU+g/69OxgCcKrcNBByFTSR4BX33rpy17t1
bKW5NNxRr1+c1ttT998i3KwwY9+nJblHEKhhR+kb87NykHN/yZrLXFCS7KicTdLykOYdZHWULevq
TKZDVq/KD1Ou59MVgmVNxrGb9PbGqJV7xyC/FOxekDUnS3oPVB8eddqGEyQXMbBhF8n/xrVNevlk
+OKg/YHr1C1dPkjazyfmjtkV7xHcXsHF2ZNRQMa4xv14FipJbc8RHeWctuymh/3Pbb56XdU872Sx
D0tF77OBvgZNckvNwH6SfvfqiGhVR4XkhnJHJMITNOJmWI221d8tdPv6442wrySQP8gRxOc2Mtgx
S8AXVOr9iHhbG/AC8rnBb7ddGcFE0yOz0tQeVZaq8xG1w5AgM5L6n4IPukpGtjkwYFQEtzYw9Y6t
w7QGC0z7lM09WHyIcFkRsMnm6gHMnYQ+H732fULxRLVFKnC6vKVxvhbYU5wLF1HQGjwiwOi/BHDI
hGDG4MYRqXjLMha1+q0euRYRew6kJw7kXOvh/Sa6yDCIsUN/4+hraxvnGErA7mhrLX0tsuI3J3iY
VePtkHZqxlooRSsoupYwj7DCIuzTHvZ73rq5p4cy+rLOjjs1v59DioGglWrShqzcSUm17zNH4VXZ
g8c9ZZPL+xkMuHyCdLiCjJNwyFQvI9EMC8gk4tUJbE6BTP0cdBz7gno0laM3zKJ2C/Utrw4pH23p
l7b/BhMApWbdznKxV9A2A14YVubDzV5U/NtRZVYzeSZXwilnRCYvmBaAampm7vN51+Rx3ZqMpoxH
gboGOSwLicdHz0V3fJ6746z9bGWQ2kZjJtNNif0iDVDa5QVNHvOq7aiRQVRt2RyrtIjFJrcyFIwc
9WuuHMPaKjlWQrX/chKAqNGpN0FFS/D4+3TGT2WQB4OLU/z8j1YO9KMOG3xYFO7uLKnf/fAxbc1v
4QWayUh3ypUkAgQXQs3hX15YC2p89vRDcLQk/DCWaztEJR+9NU09GxTNIq8Ad/zO18YY+nqF9tLY
/dMSN8/oZnWymqO4YUMF9ClKvguGBbiABt5KLF9WPVLx7r8fxBiB+WcA0bSKxpYZ4BupOl8/D8XM
JofpfOqm+wAgWRPkFQ0sAC6tyVthCSfzOIEMPjq5GemZrybHeGB7Ye2IQkhTgCo9nRW0LQbW0Fd3
ckuYvX8EtCcRid6bIa7ghUag24NqNCZif8KprI/XYZf4ldfutO3plCY7IMXXcY98xIoFPDobvUDD
OZ2ZtstawOUZ0rYtQTC8tzZbHkOwrZaV1ZAhdZQXMJkdahzdxBAQXM+9Lo4mIxjxqETaxCk/h389
13Hj+tczjdrpYWyRjyCL5JAV5NQe3bj/9demZ9iI00/Ru8aIzo7islsckYrNqjeymrfAfEG3XRke
mfmtTwuGCt9LUHtFpCYPfgyJ3N4QIf60/9qMzKl7aGxM3tnLYZjMiZ6WHscG8KmrqD3P7EVhJkFi
e8SnUzlUVHuEyfZrvodUzmW5UX0Vnnt2EbBnScYvuaj1vnRRZc3lcK19+cyM0hcRETUKQAhqgLKb
eI5SVQ/Koxa1ot3jsO0QslkiCAM4tf1NKTxMaG0DEdEdv7o+ieVakpfByXnq8XEhYwXLA4N1Hsr8
CIuF9jDnnF3XqvPgoUhN0W4ds41cAcU9TtFLbgf7ihFAj23h0cV/ZTGpgfuf14bcO35E2kMiKZTF
d03LM/A96Bj23rcqIcXEJQPLUBTklTymIGokUOk0V9VJKIX/Fkl4rrcepJvpHYml3CuqkBiuM/MA
fz3REEaTDtnvlivMQ0HfbIpX8ow2xN6V8c9vKJKj0VLoG1D90hdOA4O+veaTPTVMv4b/KJ05hb6M
n3oSuL0RbAc4XV4a9WQjO0pHixtP/41z8A6Y2UXBzurKEQz2XEpoVOSU9eIoWRd72Gh8rGrNEAYr
G5mxsl/faiO06lC1/cxs8eID38ePPUmzh27ZEJlyoLFWFBowZhC7jh17Rc844QsoNcL1AQ7zsZhY
oG/wJScTSSQLFy7kNYFov0Q6iflepD5uJzhx3dCSB2iEhCDPQoXRQsaCJX/mMwkht23I+ySi234C
7rG9pVih2eHMyLE7xV8zeX4wMKCTlgd54rYrG4/FStU6klp9Z9l71aU3SeeDc91rSds48GyGlqqM
zRNoMSYSp3VzyRMoodZv9e3tYht8VjqwKJ6PVi9agEqLHQR3nfefgHXcexj+5Dm+DmXuRQ8c3VSu
VVRckaUcLG/nNdQlnViVo4a9BHvos+cB5ARSaIeJiDLwxYKdLjlbNu+souL4aakex0WE0YdcTACO
Wn23BYzmxJIvOEBHa217OH73MCby8qj9b+nyqRRBJb3zxmnngIQGCcS5NdOtk7GKaOf0mPKjftkV
1pOaidDk6F4dvBNHlOmDyxTfQMRgQL9MS0aSIzw0DF93fb/6bM8kwwRX+4lKfSo1t4/wElZIiPDo
PHPxD1HhHHmV6odc5v/q49pSeTqaH+ztYL6spTYmTSIunmKsK0gwr5lB6gQAJpB8uQYldNnl6kx6
DmERB1r7OANtbrm6A/poccSzefB1735MDpACzcN1viJK+zJKFGXaQPLdKnV8ySIjY8eiTblgw8NR
p/Q4W3QuwzzIXtnV7otJqyVfWp49JrqmCbhIQWed4zUS37TxvV7MxQGlPHb/2te7Eg4txg/RLxdj
R6UbMST4ra4k5CkFBC2VhKMoKUwIdBuEFtpKTa8njpchVEMaBbHCsv3umG5HcksO4u4KI4V3uA4P
5obRcLARHF5vdYZTLbXJK7m6Lgsp+i8lBvx+uMFcWvwWLiZlJe1+VhLivGw/cqaOy8shtvrr/KNJ
ajgWWUIHuHA8Sq4L1boZRZsId9lNVbaHBsPUdNEEUPtNay4Qg88Eo2ph5ZPiMxga915HHdWMl6r1
qXtN+2iz+HvpGtqxmknfBx6IRkDY5MUIu+Mp+d+vCv7zAOwDeKu/pAb9WqxOO56Pugryp2lMPW+j
ANgRns7B9xn2iW40TYiOyF27XQ95qtR9k1MpEIio6NpeS00VrR040PkwIPocSLecR1a8kHVAHVXN
1giRwRzgtPMGFUH+fl/Rp94pP5PhzNn+miQ5hC9ozoflAeYmZ7TBy2tlZxB1N6AnMriRWATZjHAa
fLpo38QSkKhK6ZRhzhYT617AA7qbGvZx0is+BRFdIoWc9Y3FAScmTn6g5PULz8DRDepITIyQcpek
owExUkbyPecrsAZPVTsuE278j/aWPNYeMugXW8reh/Mtbe+Kpdr2wpEezE0eT82KHLtxe9plHoaz
pzfkUZ2DEs3Q9GeGWbYveK8236DdPTkUUZF12Zlt/vi6qj7IUeTYDk4tn5qefIMLmg0XbYCHq+QM
Jkle1Snq08rJd/1nlVYogpioTP2FFtjaKTA49aYa+k42n87J2S7Txr40PqjjsP/sZehfz0AhkVfN
FmFqod7kRC3WoqkxVrli0P9v7PJBRoM50qahqORZf35Lzil9NMih/Lmdfonwmyy25YeLBbzM0aM1
eO84FZgFC2N+GdYBV0Xsb7y07yyZZ5/bh3bUu6bVsAT0KTCU8KplrmDsnjUaUNWnUuFR09XbRKKR
YrcKwglyFX0tnjgZqVEIp47XiLMfo90LtLRjdjVaPt1ib8EfDlPamwUVNuoJdCTuU+JRM5SOakR4
p6g3V7MlFSUo5RqBeDgDTNIhsvBTsb0FMs4pHL5W+QHnlGPCth1Z93FALDtb3MkeTcCzOsY5lvH3
WEIn6+qtRiFW6ByBLLCrniV7/6Pc86fdpt0+JOzriKIpmiwLUDd0v95qcjTaDfRsNpWJqiOYswFu
Ja0DgH94RulwBPpRSSKOX4R7PtkHGnQU/Xz0YVzc0usEYj/BYsQmg/0TvCItmduAtLvSp3v1pJVf
Riy5LceSdrC8P8KaEwz8wgmQm7TnqsRDtlOib+Xa4+f+ddoVQd1DsvOgvltU8lfIx83xIDYGcVS5
8WYksPXibLVz4OjYjhV/3Welh4zSwfCz067iq5gBATSuVI+Y8r6QffgJEhvy902s53vkxYkt0dir
eU6/osi1zOI/NwQWK/3J3cKT1Y4ii/rxKxIL1VgATG7tGYPNzcI2GZxNq7ILlqDMcPmeKVqntWSg
Ni9j+VkCmnFSm/X784S0XPcXB2YPFyD4anm3vWhNguv0CAus0RWXgPJ7MUE+EyhiQyVUNODBp6El
cVkum2PmTDUI2RtTrvEinQCUiTHS8OLFfnQe0yoHPW8UMF421ASfUL4GaWpRKMs807m/DbLAOH2I
/oxvrtJ7d/F1mNd5qO0vaIgwmH2eehBuHzIWXW9EeBSeoIfp9a1/8emPuLKATc3PN/rzGpZSSXcX
JeYyT4eXkKlJztjqZGdLn9mdSxmtu/7OjEd+46R8LARup9Uevukl/6omzwT0np+dbv2Wu9D5jzbf
TWn1CO4PMlsPclR2kdLn3mrKABXNk5jhnLLSRl0Mfvw8toXfn3ztHhTqKxgrKqzCcLsy02LKAuYz
hjKQBFNeD+2N0c4IGdf1RpT+gXTAqZWoUI7Yo06fPUOHPvoFeCqw7ao5iqlARZxKaNY2LIXDPTTv
MFk+MUNwlsvEGuB5OUm1UoZ77fGjecJUF/FIGx30ikwfThkPF4SBpFRdLlDAPBC0Qwr/7g5M39Ch
MvFey3YYxV3Omj6r9CIjA0YPiJe8fmheC5CkpuJukHvoMRNnR82DBET0cnCAa9hejIVxfCqjnp84
5jgfqBPS6IoT7wWh9VuXbjInOF91/7WRNwDdJSMYC6+C21yMSPoijAeCmeIAt8NNscKv1Ai1hfTC
50DUcHcKpVurcXoxaOl/AC9i5OC+aHGxGpuLEfJNqpCBZNm8lUBnSywfJ4I+a5YV3u1XdN+rOcYI
VXSGd+zHHAt3tV/R4vi5A80lsa9uxSHRo7raFELaLv8MzlDokz7whjHFt6VUdyGazWT73iWvLqxK
dfezUxIst5s45fdqpOYzwN/1SBe/0GhLRj97x/f6q/vNMuT12U8bPtBXKWg4EHgaMjujrwAX6I1Z
UojJEIyQnAjyqpaz0F7XnWAobF3224D+NQUAe8U5cXQSFsZMqs5GcBQlK9oCUYaVOhIoOAVZnpx8
gnUoAst7bPXolsPyD10po0jiZJCW13asoCcLJcVhy31qbHX733eqf7iD/7kaCDP9w3ud+GqT0eXs
TD0ZW8ckzFweYdkMrKwh5LLDDJOD2luI7yn6yABZ/LFF94FYy0GAhBStzG1OnMtf4kvbSePFqYx9
EH28VFrl/+RiErga4j3irM4LZLXx5FZ4SrV6Y3y/rKByZ6ZqnvYbDPbLLHJMvijDtJs8TTh6Tymy
WwsfFzAW1eTLB3FjOIC4pRgVhsX2dUMziUYAJekm1I/x6ZqOFHsEdj5mX1OH71B/8jM+fwpdQYo9
4CqgrjamRP7IIG7Ay5WVeSh+nexLQ/DJ3PMzV0R7kO/nn9yiAtGVn5dyWscagC1mT2x3ohbXeuF9
kO5K7Pq9MQYY2CXTBlJruycejAfQisGLdH/EgqB0QAPdI6W2IP6oQK91Gi65LezriIR3rU/tG7pn
r5l/1v2MApipueDjI9xu2nf+q2UCw5jRQjNi4fRBkiygkfq5nD20Mx94HAa6Z6yOpGq1xRQ3uKeH
wSiWU/G/VGSTXQu/8fLGPNtIDjdRbwDpKJ+dF8RyJv3YDcCpI3KXFsEjzOSgmLZn4VIJM69QNEOY
XXOA2STef0VyIiAL9zddIsPGCvp8gy0rZ8JquyHzyXjhBm/gW+aESjvHdUpvT2272gdUrlq980TP
tA0rTZZwInm48CsFtHjIgO5L0rC/RwimOelK5L7M/xpTvHrk5dcDYa8ohbLBPRS5ZXRLnV+mv8I6
H/pvExej1UvAmuJgUQUQKh+4YMOW/iUKwI8tsVXV7SO5Cb+gzPEPpmwJZbNpE+Nby7ernjH3OaI1
Yv7fwym1uwweh0K65/SH62ZmDT/zDs5iFjEYMaIOjInEvqksyrWNavuHqLbfXs6dFtQ+te5q2ydP
NPTuWpBgjm0H7SgPXRFo9S4s8X7f0XlenHdw2vnn0JSxPsG/IYhWythKWvJpviySMf3UhUu5gcsi
WMlCskYINgLfild8Ya2vVYNOa23TXGLZamzaznIPh5/E8vnl/RCZn96Y/ll0egefVfQ+Y360X3Fs
0zmOYFpeoB4wrxWSPGi0LlELQjuAxgyq8UEjeVyD7+Hr5di92g65uVg3tDeTqY6oU/q341wpnERh
lJ55l3cv0Q+PheHRRh87frMMJ5hXzoe7MgWGe4nX6s+xUfJWU31VpjzHnpK3ToWGFp8Xt2pSzfIl
z1YR5nBNztEXiDIcJOD/fk8dXCnfyfhNCneBFBrauF+VELN5mTymz7Zvdjl7TDuewPbjpL69H1cy
6zbUfwCJYdSrdvc5Vq6XvM7CZxudtOCYDLWawTJbEveT/vRIGV04UcDmx2ansuinpO2YBpk2v+8/
2Y2/XNsohRrUR1YI0Bpr34ivaz59N5cFzII62SpauqXOL8LdxNQCUN2T9pcFVSCMAE8XJgUWwER2
1eGJAkMMMLCXGFLDUL8nPlFOmYokLvVOBveOc31sU1nYUunfxoqAsJVaBxsfzZBMj/7NRHxWEjre
ZuIfYoXsi08OuA26O5ys2vtYsq9yN7THDrCyP9oTc8jpSfy8JqLSNXraOAyX95CU4hW8i8fS2SLC
JNtndKuCvbSZk0QGUsaWzAWu0OQHcrICvQ0NDCGP9rzaZ/KEFgdL9F3tINHYXZrmf8Y/jaBZFRkI
hrp32Y4iy1nHEB5ms4Vkz1yt9D0wN34iVfrVU6DlUSzUfGKdw3tP/68AH3L/3v2NLsIUuA54zWRi
KsoX/tjb31ynQ2CWyr3+Z6+rPausA6q4scHN47JrkDdqTGjsafn0NjbOAutOKuDiyakSrIM9ZAnE
pLOYFBMCaapjYwSM3NMuXaRHHyF6A3zp1JN1kIFqn2HKWwil1Rj9yDcLA64G1RU2jdoxcw8SaXLl
dRsPvy3MpaXNr67JpaZLelV+gBoPPjyHUg7ehLOr9x7fVV/v1QmA5nEwq7o2/Jex0l8le9D61Eyn
USJvUwgrnceFxW7LAwEAqvlap652iis9LFEIONVW5x9/wVleF9xtFZcys/gsBSvY7ysX1urknqr4
z+PiFt33QbFcR7wDF95NWPgwt5VsHWEl4D76iD6RRApTCAaR3DPJ5fbDbQJeLmaA5Rk7cZdeky19
dfhMbrY+0reqUB8MLB3rW0Vt3A7lHwUL8J7rf/jKDumovWJkykDKExkfuLkeYhmLA6oZbJLenKtU
Ux+5PXRMP8O4PkWPN39VJrFXQgXdLeiKpQCR0d5qo43zkuAVozXGVTehlya/ylBspONsTFXU+5A7
0WiizrkbZjIdoHl8dRX8GmHjOTguARk3WssmCbW0ZfxwObRT0b74bimYDH5OMqOPUHvaw2li74qJ
nTNL8ezSxAv6qSf+EvmKekv0e7LrV1UGozmdhg72hk/bVX+KAc3L7QIJERBa3EXYePKM8QGa0udQ
0Cj5nKlP4lHeFY1iIOiHfrFHHAsy1f2jvORlX89Hw2n3QwW2XVbGnRBm98fNieagYaUqJcdlAfZx
RR7Q5ORYP6X55D39RQKZHUI9KU2Xlp6+nM9I+R7ihSTCwzYS/j5l+68Yst6KxK/NcuynZUAdd4fW
lYGDX5SNkN7zmGm4+OoEzQ/8JhV+NZfmvWVVdOQL8gqdV6giHabFQWDKlQhJoTNbAAM/6TXAkAhK
0BbCvvY4iEhIFWfZLNg6Adfz0uDNFaNeBQau86p6vihIIBzMu7HsmVhAXN+0LmdRgpwqDYKjU3eA
yqjdoaO4SuatN5Wes2VpMg+BN3B2eUOk8xH0xFVe6Hdk6N0ghzfrij9kOkX54+vQXlz43gSi7sKz
dbSua3fcdjIY3zHc4YpopN6BhuU0TT+8EJfjQQ+YHKke5YOElXbinrUTRGDPIExixoSXfj++l4qG
t5XuqjGEqolMJoZvuX5cCspxEjDQ2jUPOltNNJ4ItlpGZQL7xkguIgUp36g6n/6QQgE//YOwyRAA
gnREG3+1m+4FBts468o+V6hmEU61c7e7JVYu3oTZmCXN7EOj4fKVN1CZCEJRApuuxtyDIA29Qg45
YsxdR9pbt2RiFvwC7zSBRkIZWx9M02h74xQ0p5JkIkmCO2cGLf7Dm835+ml8Egphxj9zM9+EXRUh
lizZE7rGG9hWTOg0Uj4PQEmUo0qGuQK1hMME8F2JUR9arTloRPyf4sKRcL7KoopvMP9nFY0pVdj4
aiPdGhcBokyX7YemC+Z/snra99j53CHsjDF/r7Qs5aNy0rJuRataqQayYw5yK/G9hbNsXSMmBDK2
+07MF+/5oao0K1StwIk/oUfASNQuPX9MWu5ebEEIgPBdGUucpCTa0VrlMbKFw+mhajjnn/ec92cE
5CmjiwywGMG9HdFI3tbV/P2yuwU4ycaxiXGmunn9YuSZ9gkdnP+Q8Yu+HL5zTY+/BmcDvMDAZHbm
g5sYCVdkjOXeyNI4zUmaOUE7OX8jxJ4AlXqn+1kAll6onG1A5agSU0giP+/SO/rawL0QLucfFWkx
YKAXdgtSHfiEXnfAV47mW82keqi/zGuTBDtVI/1oZKpEh7prDj2JRwawptnjPNhjaBRYAhGUKmwe
ozoCiIavWYadeaIBilB7jZcvHK7D2A3tQZxc/mkTtpnbNTLaC6F1cI9E70WDqBx+xlNeKbea2Lvn
Do45S0p5Py1FStP+V4g1AsAM+9m9pBxsb/CDZ+AY6Emb1dcSnUDwwln+x1YW7TLCV142eM+jZo5g
667AzHXbdLeqREjBe8PKLNU3IRx1vEgWrxBi4uF19FqipkP60BKJQySsIao8y0YtdaT1k1NGUgEK
8+KFa3grwowJrz4ElWY8ajyS+jZcNVAAsDMQZNlN5f8evEQYvo65xbkQ/N6t5J+uEuX3E1SSMYJ1
T6zirm6ebV2RAu8Jbu2KcjRQvi3JrzHQwwfy4C6YQ6GvHD4otS1NJXhuu85bJegui/vaOyVbQQGb
OtG+pCfr/acAazi8MuMs5wV/KlijpOdLkw3cPV0iUOjMD3Bu5EOARkSKMKmEsa5rQn2FjWhYo4sp
RWqPEvFSifawHiGlk8W0TaVhw0bIYojvwg+xNOVfvguY9dRu/vFm0P0CNOuqxSmsf1/JSKHhSU+E
DSUBxOshE5uxO3j2Rs0K7+LIXr7Th2867J6+zXFY7rYpBA2mNCzCcnvOGn4pFWLyJPfu8BGdhIDD
hX3sc3W+xolA3YWiVoOv9WPQMKKOTf7Auyo/3ZIzu8N6V77A+S9LFE5x9e5MqY9LFcyYiFFTvveP
ic9L8DKWRss2Kqvycf6ANxmVFQHOcYEYCuw/M6jA/L1mbF3t6Bc4HrXflodgMtPnA2pw42XruLKy
P1yBimUpkXGZS4F5Lvr1zWBJRB+AeAdWZMnqjGLl6opQfm9Xz+UxquwITFGaq/XtCc99TWPBYBq7
Y/wwyBA+cIawQPa7IQ5BDYW8i8TXddn5UDw29JX8/L0cztSWVnhxMGUwSKnAD9/55ruPdvJXhos6
xeJu37ayq1SqxJX2b0hPia78iAhdhkWQKM/1RWVt1xS9d8fRLLEmvTn1XXRQ3DC1Lss16abM5Q4x
Rue8912XtfPt9lKFg1VK3Qdl8eLnu/dXBSJCrFIMJ9JnE24jE9QtnQn6vkQkWKQCHX3IwXmfnTbf
Oa6Pd0qvoLURPZiWgHNLAL22T+nP5O1qMh0BsRzMB59V1w7IcrSuaIZK0nkGuQvVXKR5upoiOsDl
lI9qcAzk0eoacvHhuZFI5dyvqG4EnClrzeigDzZda3N0B2116VcNeJBYXw+SKrkoXYCPcIjgIgNl
eQPjhgRg8gGRfn8nhQ0HznN9Za3JcpmCq47VTfFwqXzr7T7jA4btISOMNXTWPOIhRCDLa7EaIJzQ
rizS/rgFfXmmjNFSQQLdCGKKY/W5DegdSlpzRPWiwBuVaI27JEQUBbrlu6Lzik9tcMMone04/HFQ
VU1WmpikxK9YZCwkQ2xEQ4DQxUNWdHKvH9DL2Lj258hWgMpLgwjHYEMjg4i8A8HGlgrjfHVyDHwU
ycpJzGnfk1TgFJjt2Ab32QyWRJ985LxfONI6zMyuXXJzlMzI+RdhrIsbVKtWR/zDw3d3RFwlFFu6
CPZGlOzck9VO8iVVOHq/jU+OlrqqMc3WHDn9PmhnHTMMyTQ5cxpGyIJwsS/m+82S9y7aC111xqI3
rcSvR5FeBRnr2aRePmiynqvLIwgycLvGstq85NH1doQEvRBsxIiuMGTYlJFZaSDpuztp/HNLKwYJ
Fu5W8k+ktNRwZ+CU+3BIxR5HVBWTauyBgqMhtay20gd2WG5V9MAS1D80K/a1MLyfVg75zPJ/lir+
R6MABSbSESVG7I3+ruRSEM1VrzpZTgMm6zDZE+h9OYuAnYp9s0+U+Uv1e8JXN5Q8Ehbx/0fyoXdB
N/Q4s/dDj05DPvVnrmWCDAOUDZGWsQLRRtEenT461xNOPBt36I9uRPdEUpczTIK+GjKh9MdDiANS
ZeM9nN8wJvnpMVEBXQWeGk/3/dogsMtiODTmZkSp/+Rcs7POo5jsh/6KDklR84KY+e78I6on42f8
GjS2O5hcsIT43Gz+YJQD26oMSuISrzZBpSgWjDN5xbPuXBbOryltrGcgQtXPzk1E60Xm634Zshbb
7ylzNaXA+QmGFpT/Fb3ZU95bjCx4BA5cwcV1eHCB2dSTy61dhtndWLeTCMlVIqMe3kXXKnqTrlsG
4r5NkerCuk4H3EVM2fR9S2kHKiBW9OU5ScOqdjk509y3LG0wGf/+uHBCHDNMftcW707IprHcwwW3
bznwDbGtB7v9kL2ArXbLBocdSKilkwgKkNpgRVcfqdM4OJxGGgalTjaqRqR3ntMlXK2Sc9eGGleS
0J+F/QoHJCru4qlH8DI69Gmaj+HZNMKRMv8QNXb48p4S7A2yMT92oa1cPw2HPhBOpUXoswIM1+G3
FVxyPImZk61pJznatWC1IP8NOLBD50CpEWw2yfF557BNHB8LJEH1kpkRJWBF2vH5h4xWuZ7u4PnG
4HbF7XsjuSQX02CGgiojOCPSAFznoV67/WuBcX362DpdOR/JCqzB/6k+89W+k5KIweEv9UxHKlOe
eqiP6sp7BS0VXTDr5en+bWsij/Vp2chExYLvO1TdTaQ85BSObo+kHaNrxcCuM8HJGtEw3zIi5FfS
8q9K1ktoq+XWU9EdiHgxysBuERZTQ4XhFFhxWy9FjqQA0LtWhp3CiMQv4GvYsb5gNB+1xqCWvWqy
DL4pze0Hs73crddYW2Ikgd8afXkvDcU3NnXlUm4qOmlOCF3XKwWiK1TbXE8QinyfciFaSaqmPCte
cb571N/9ta3w/kKj0pKCyb/McIthec7AguDQBAXxWAaPQ1MV2fDkDg60vVBGG5a/5Yc2Kzcg7lzY
+GTUDHmzX1GwEMq+ZnVpFjWpeRv9ixIM5UmftcRtGs92yM/xlIRhLVtg5fUuEsY/9jkNzXqQ+tCs
37q2XPZBXkqUTjQp0Jj+dwtE52UrvwRoy7BW/VDY6sVPeI6TzY3dlmGlPz7RlmF9OvY+bFnE85V7
srAx2E22YiDFCsfNu5q+2XT2AB+ZU40bDf0zsLs/G2Z8HP3Sqlprdn3SzTdXNA+xp7U4bQohwLIW
8A7Tt4zJD05Lv6VHVwRVAlSIXbbEdzdayWH9kO7wjdRTSOE9SmxyYvZbO1EH+sWE+d0qByAAIFgx
uoRhwiGrgxnc9JNquPzWFyCGZvBFMRgWhZjTxcLepedbtt5WvdDwctf5gGOW07g3wWHw0jMmRkEQ
YILyFneVIX2Qmwhxs298XJjGTpQtl9B8Q75sNgtzsdTfD3Z5QRE7gqUT/mSFxpc3+oZV5cP51K4g
2WyGaU0NCOYS4/iFzmC3Z+gGIjUCfHsG2p7lQpgK4inkB6EZsO4y/IpAY9WeUoV5AmzHKYM5aP9i
ybnrEZ43slTsbGJHEawe/DCowKV6WWj0lhjEEYej1tWlYG1XsaIDPM7zUZDfEzJEXRwApY9vRBRo
1Xv+/bSZXMTIb3mv2k/jxDNxDq9EQ1/SW4emC1nxgvv1SrJIE40HCLfrxUOuSB8W/x9GdlNkUgUC
hKhUI07J/FL0Zu/LtaS3M4QBw0ZakPNJd58+77hTFOlniIcbWqBuTq6U2eC4OrZb7LsOHS8RqVGa
J6am8+9/4uuWN2mUZvAeABCIa652sMSPgSQXpxwQUMGDOuoOg8ppxDRWSRT9Cy9DBfhQCewCsLf7
MariUI7wSzVqo36gj5YTAAJGl8zW2wg9QYTanys5Kp5rxsSjh7Az6c/qLYJnSlY8prGnMO/LlBfJ
BN2047kkqErx2c78a4R/ZLzrT8gim+eZKOPghQXRhp1mEle0UVxESa2KpOSHp7LQnc9AyraBKIHr
hx8hSaN6Eby50ztIWht34kn2talVOI2aWzskk+fpBcwAfw8dxbk1AtM/e9jpIVWJgcEnMV+ZyQZU
y9M+Zk9AtU02haRLKH3Qih+sUcOcs6cX1Ykiq8iQgJ7jQ/Mh/wDsS/vCkjZ3A08NJOjDqrXTDdyD
suwicdcSMw6sEY1IiuMf6Mhs8MSCmEEp7JeAAiYmgUfpLxM5Pr1iBP16lzz/Hj9ovgBULiwMz+do
L8iQAik6EybeoL7dERYfNKHHE4/WueaL+J4jee9lOiWNaaJRXA3pE/Efubg/wIqgMnpvQNl+Rs5w
StX3xRHPkCCkBAjP1SviCHoqAFlUbqmevqU35HhCeAj0JozUq+F6SsMDg457kvrS3bGliIU8az53
W6Rse4X/UUmmsi8VajzGEwWoCIK9brmNAUsKKUEemVGMd+IA0bhKaF60oxsRjSj/bqlt5Sk7d4jQ
AZXfeeYecBjy9b++7BSCSttE4/NT0tFDwOPWAIrImTmbT7Xy0CcJrc0Flqc9pHV0Bk+HDNXjGhxt
3EP02HPjXIZewxHrYGSr62977q48gkaRkcaluMtCFIFZjj7mWlnOCZeurRZ8pT0RX0esqHrYi57T
IGsR2JhFPDJR0335vJX1eWVwQcPicZ0yCQxp+izpuYO2D8GEZqwabBVkPOp6jg5lAakOd15QJ4LZ
gNTLzzyKJ9wQQoaS3jOJ/OSyrrZbX7GLEN2y8LgRn0OTDDHX8MTYDXfcFlSsUcnp3JQ+FzJG+s44
Llq4LEyaDkN7gTDvLzlFB4GwA3Bc3O+rNBkSYF0tuL/NZOWkDiWQG/KLcWufYw0jrne+o9Pt3l0L
KiF7eTLJFFQiuEphqb+cuuC1n/4my9Wwrgcv/tPJed5QXhoxTeGQ96LW+gP2oalvyIklKOHln5qK
zb37BKHwYQR7801EKIko5ORa4diOI2IgpoY4+FPG7sqje/iD0BAwUjAeojYDn1i0PI9aqiFOS16T
cR6weaPVR7ic//PD2XSKuCHfcdfrQURiHzE9mL02gwaauO0MXO+IhTyW/QJI3Jf9n0QTZCA1amPS
0CW9bj7WL7/Iy0D2F85C5TjjSOCppEBETEDNj6E/yDxtQ9kANpP48xbDZw4JcJxP8q8wrt+4u7RQ
0tqEqecxO42gxtK+VI8woCJUbwxE8H6Oodfc275Ar/DvYXb8gfeRJgifsc82w4ez2y1D6nRy8q6c
jHcuV2Ye1G4uc4sEjHgABoLIiZEpOoXWKxL7SqEc100uQZwiTGAwNh1NieLjJr3tXqNi3KFK6KDg
sSeS3GJbfnmOSHwGFflQTRE/2TbJehFTM1jgj8ObH6wsbFiNYfs/LYlmwx8mpuTty0xmA7FpydPg
XMXoa+CxHQvqFD3sHOMq7nj12fZNS78oKLYavlgh+3bk2ZJHtYWucCgQCfqB3nF+KVGyLdQ2Bsns
oRQiOW+3N2KEoME9Wijc6iZ79GnKjDppHZZpWQbYnMrn1EQ/5asIARtjBnFmb2nKPwIuKyJ5sbU6
Kf1keW+qZhmVILi5lKvejv+NEnw75AU2Sx2Tv6mV5giL4002z4eVXoih64CT4VHCwKtFX+6vt3C/
6MNdl6TXLrPT9G0mgN0R8AKLFKoznqw0aUURvIaTkv0XhZc+Q6oHUh1wSIxHHoxIwnwB+bbZbzoE
T23W2teYKyAJFmLNScwPG/1afsrP8F4wrA/9FOtqNg6vms7SYyQAJ+GxwuXRuIkPDjCosRiRFwtS
bDh4PFGfmUrHt9yi9ydHvkm/m5ML32IQYy/Xso8P23oOhWDguo+iMEOwF/TAy8B8DZZ1qwC75pGW
vFBVqPpdKMcBPGmcuveS/8DKiwoXf8qUMci9qCvlQxLpIOQyQzYSzHZ2sq+7zacbRbhIC9jKLGN/
cSOY/3oRjSJEGWIW//jGex/78KNMNQbDGFLPR0s8RCLGOW3cAnBq3+KUgkEvXdNRZwvbPf6NOp0c
MvVyub8q/p5+YI1HvfD+++Wf4RCm66rR+encYhSS8FqAfLt03EqMxOnE9lwkLTO583WXav2XagTZ
r+zM7vuvAiU8/WYqGuugs0ZhTVzXPPAGc5N+iWnJUmyp+Jp9Dd1oOfqqjHEe7nLBYBsLNEpOUWDN
UfYHiautw/OAxl2D8fF7fVMsjEnS3xZBs7bIxQ9xGuBeULXcz3fTpfFlVagSX6rueWCiV1ntlPpk
MIcxwgXd7NaNfuJFqklnBvrfatrJuBj469rF7C544WVI2svEz5wWWePOufXKm0dSDZvNRL8LRzOi
UjVwak58eElno0YD3hG5eDVXdV8lSld+uZnE/oHwKrLp127vjbHpSanGa/croiGBJX+RU8idBC5d
/U/oKFQk3o7r3wNG3qO4pa6peBV5TOiBBEzGqVD+pFbCbZwxvPcKPtzA7OdePFoS+hjZRPt4lkTX
gYtID2jexq3Xp2vJzpOLTHqAVwYCUmb6o7lHQWh8aUB5Qmpb2QvA9Q2YgRbJpQGzl4HCYvTEAjgL
NcsxEWC5Zs5pSSUQCSq1eNs4ionUOynQZ4+DI82bKTtMBN7nSvA1HkK0FM6aNU3bYVnST7NUJn7D
QNkJ0bVx2fuzq01/FP8bcCp9190u/B8fpszwdvF9xO42iPguRUV5ubCK5Wyl2vN3+qOIunxwZoxY
uZLBYiT4xbf5j8qTaOLTfEppv8kyfZwvKwXbjk6D2tCySfdxoaU1sV0Kt9kYplx7S+ZlI9Shlsb9
8K0UrYTw9QOigRhF1GacyBXji/1lkLm+Ysf7DpEpxqp/X8yzudbUXuQlDP4dqDNOpU2O70T/OA1z
yyc/h2SCu6iLfjyg2hrzyiu4lBKqgBM2xcgsz3D1cKhgYDLhSB6aLRvP/v5IE0yWoPrIsaJqr9OH
wHVGSKJiYXOgi1Wzd3W8iwxWAX6Y9ABMItHhSvIN2V7E2+xFmBQc0jbpYrpwzLQmR1537iiSrNnb
iLrZUZCZAmdhBnkpefQv1UwXAdTvXx7YiukgACuXUUdTecwW22pmIoW19PGh6Ihn5odooRYr7sN2
x8sV+FfF7uo/7q7FR7I7MpJ68WU31PqfELAaZU3xgvIb/Y2vzrQo2akW0vmGonBF1cOmDddWZ143
ulohL+oe86m53+hqdaHjHGwGhW+lJOlUHl9EPMYd0cN4nuOBgCJ/PSFnvFLPYvUFN9f5GzMWdRmE
7ChOLQookBlF4jeOYBUAIUHuw3a+n1aNBwAhh0W/+FvLavGXF/v8TififyWw39ScSFVYNngPEJv1
JmYcllmZLb5VLvBTLssm1MIPejF4W/eeRkRHTzyTUHqkaQwFGjmiZWKzYa8s/+R5a9cx3P7wZEtG
37ziq9YHyRr0wWlKaGtzqbhDFd/mpzbU8eU1McXPEJZvwfmy9UlX/LD4L8ICQaOXevv58YjXuqZ1
19vyt2XSy3t7wWe+pV7274G47qmnPDrY9B8at07buqbo1/vm99CujSg1DS0t7VOgOfjqxSMPWEvr
b2SQ+Ar2nhfRcB6ou2wY8JLT1aMJsHiohZmI7KxzUeqQSC6MvdM/sFQpcGXoPD7s1M0k0xDGatZU
sO1UuknXaIkZ3YZ2kf0l4JrQYmMzpSi/Kpd7S61hw+1j4kh9gC6o/dHOOT0apYlSxzMsDCB9vDh7
7AfIKCJx8hB1iYnYiuoqIS8+i1JrfiZIS6CvGj0I6X07xlm0ekjq4aUxiBrvzU5mf127rqLrFuye
w2mzyhgXQvsLFr5a4rtM8g07XXqILAc3Z5bGRFgqNGPxikl7ePskZ+2Ol+OUB+gisTuynBEJzwZr
NAtJxQvwjrIaUC1rTtrYPnZ32/gqFT58y0xUAsiBLNoF77HK1cGgMvAkDSybecK7/5QT5wRZlp0s
XRapCjpxVMhqFyRasGIdO/sZMClEa/Xn6aTkUXOT6AFDVTIB1n+WJzFrlpq/EQNgyz/NAx+Buzdu
yMJpWuKB3YPwpNtQJTWjv6vb0d4J1evgIiK+w7Gj5ihb9N3pvDwbv0pP6vveSWxY83WbdEe6yDCo
p57OrNgPxAFK1dlqa8PLd2rw3uNarXAT/cyYtnXY0L9uKXzzjLDQZfJBAoEWvetBZ0JLJfMWm3jY
6HxEDx+soy9t/wp/io2kxPoO1qi59aDtZnW/LClq73zAAP+JM0qxIzbi0q+PM+A8/bK5tGb+UmqF
X/yo6PF5TgJ2KXsBKJRDdj0DLaHiiF00x5bdyvRopfxrIi7981UZ0Kyr8jhTNpwUQ6HsTWDoHOkI
8UTOAaBDcFlaPgq+cE+v1l/WrRc/XxTwZn5P61UP1EWY8RJkSifJ7FpnB83QW7s7Xf+AHLHho/eQ
UVjSbhR+TZTMllIOYuuCqAv/JJe44Bpm3RzEMAoYkLd+iWUJ3OCUkFN3ICbEJteEaj0RQSjRGr+s
l1YZ0vpLgQzAGb4D6kOz9c1NmJRPxVtuY5zSRdi3WspkvOQlnD364N7us9YgWC0IcMLsQwSS0j6E
2++MmPmQEV6sCuH4iL9VLYO3EObU2//Ew0Fl3yVgUZTeb1xcMcKCHmzKLehQZBa+vmMr7J5n15vt
c6l+l2GCwUJvtg6/n+Unf0o52LyKALp5eGWZThyW7L2rIJnU0h3QBXF6awgC1uOfG14H0nr2aLma
ym6+AuIuxQ8LbYcxzxz27zOAnhcG3wJu1uZVAv62hd5HrZ8in3MV6mv0YhAcK8SCT/p/mN+TExKn
2ReKAMNKfnKhJKqex6xBiTJqdR4b++kG81CK2yRwb9ABg9I0jFrjpp3YIPTiuX/ABTgTodzJDwWq
5Het6If61caVx90EBasCH502MEko+JTPGeelxr9v1c190QY8z+d0+dZ2gDGdNvJPr4CsgnexE7Eh
I1XYQd3LBhYV9C6i1qnvxgKA6dJFYsSw6cv+Ecko5TW7fmG+x3DbveXnRafeO9nqwYCEwhu3vhA8
p+hRRLZahbRbyv/engjoGjW+LQAeTpEmXG89xOFpt0WEzroVSLcI/5s2oPuxHrx/RhcD/LaxEqjM
wDEgQ52eKJmiSJnjCmjvcKpaFsrh96rnALuzcHwfxFCAfOrjoXkTapYD5+kSccjCqjNS2KprUsuQ
tDUumwOJXmuDmWIkPYxbUGqzTaKqJU/FBzQOaTZlxq+NOmYVZMgq1wSOeAtYIxDtjvjHSYWmB5gX
60j1YMWv7KvZVYtVNb13bNAXgxuAT9fjwZVJJQFtwbvDzhRO5P2usWg91AVNFUXnGRH7ho5cGXcC
muaL/iyTKOKFDQFqKceMklLzLP4GcwPeApy457te7YsKkOzhyYytWJttHQ5JkEgKBJCMeMvU1VLo
6wyzTqTaugaeHKJZQKRcgQoJJ8Pr7/3T6A+FYh17TbH3RCWod21podpogkAF6+OXCdpAIpbCMpR3
SYJxXi5U7hJhdkG1UkBAhY9+QPplRphoQYv9/ScvKLSSnPM+72cyPkbAEX2wtVGmHBW9+oo+5Ob2
ur6FnQNsEi9T/aF+rDNiZZuI+3uUG3jEMW1lJMbHJu/ZQ1VcAKrvh6ZcquDk+QjSrPQnxGlSNUTN
wh2t3avt1X9N6rpSljnN6lNW2TY9dpnLGv4cYAUyXhjnjPk0Al1HbxTGybvscgNy/CLzrwOYLU4y
GCC1Nk+77vbiFUs9LWZ2bZY6S/Ot4fZwrVxer/ZmcJkwSyq0sAtFcFM4PxDYa9kQ2ACS0DELjI5Z
/+0Gha/BLt9Q7JWiiID+qa/ePuWqD4iTO08ykF76LnC6fL5xtGpqganJZOstnvmC69fwJS+nOGHk
B5c7hl+VfNWLpJa/yOY2tDGSuLkW3nQSMXyfUEiWk2sJEOZpUKDtdSe3d1hQghpKWGgN8YM8MIFN
JE/yZXc/YrDLUJf9MrQ73BR9g6HNiik6HGNujSDqFussrPxsQlsqMa6dPbqh5Z6CjHaRjnWgEmS0
GU92+GwZm3vaRrQ6m2fYrswq+LMv3T73xrNQsdsW93HpIU4jtqzD1gQW6Y46Gc10F3uQ95WJODHB
nXJSuKDVTGSTgwu6tThUiR0s0L46nN2n+AeXrs/m68KSGMvx1P4skTtA7M/kNeo5tH9exv8XBpJi
l+DYZmWxeqdWbUjhKkU5SJdKFuPoFEmFFTvRggndjdT7q/uReEoU5TIFJMwmJDEx7MbRTWuhWM4+
XJIwErn6vdqlUfvWEW13zf34UFYAj6laqA/OAc1V0Gpg7T3VZkdwfKyITJ99dU3VCo2a1RFvaX2C
VrYlTB6C36qAiJdBw5lnR5zNPt4bQs3rO2mIEXKAtT5GKbEP672l5VZrcOwyt02XqwNUqjwAaGau
eA4e6Hljxfoenh1Hb7krclIzvxFwlE6wdtK+IwB1JYuxZ/Efy0JWKmHAReH5R6Y7OMNK8r2z/EvA
sPPVmAxSH36qbEQrwhES0kWsAzBcB3dd5+SUi2f5WHXV3ZHV6lR+JnaREfrNtPmGZ5v9xPsOwUFZ
KbkrgL+M8d92Qx+dDXjv1czgel5z9lRv21Yw36wyUY+parh31UgasP2UxPu1aIwS/I6/TK4KMwJh
AILvF+Yw8AEx7LCt+eNllHu7pr8zZELBmyipm1phFdzUsJaHk7SijCX3UePg0jg1MWDJhuAXB7Ki
gWy4k58cJNlMV33kxmPhjwFgSbVoz3mHYuX0GAyRbzHHKAPyDKcpmqMrSKfGJouZ9jTurRb37zSW
D08YIYBMZAaFHgk+NGaJmMOKEfn1poA2010VjUZFWYk2+InPQ+MmHf6m2Fc8kfBDaijCqwDrDHfV
w3+kNGcZeQglPuGgSY3yq6dC1r1WNSIG/ktZVcH9DWWwP5Ayv+Q8r0IEMayLHwFqpxN419O/7aVY
LEvRU5DevrjKYdJwilFRRiVdyDkgdkyP/qhSa9saRuE3eYDgKqQUD4YmmP6ujHjMS43ix/Vog8RA
zZXhK6nmbySfFmaI2EKlzrnWUV+fjAyqFIUPThilc4AeAuL5zvO2Owq6qBpLq7ufJUQso4tQ9l1A
R6uuxZ3kgu7Gzwx53kKtUYr9AF34szfqjkVb3zA24aK8Zr5lEgRR6m2xoAGDkQ/HPO/rHNMi2Dqx
Mh9j1CZagN0gw88F7NaykzWYGu6xH2sM5DVepCTSzx/acUtFSbmJOUUl1fVBiq+f2ZDb7uXwbgYs
IgXQJ/HEEQTS8GBCoBrlJJMqf0xLTIlYUM2SRx7cpqPuZCnVi26XdRO2cD79+RPq1tRvICp46jDr
mVpC6ZEhEVpo0aTOuKIEd1aFfP5x1/gCEV/sFg8p9s2U67e5nsWBHQ3rTL5V+yIWHV4W+tZrAlBi
sa2XsjnXL+FZOq5+ymBGcWbIta+aVOcZ2MjrD/a+U0p7/v5ERdQGdTZN5Oypyw4D3irqo/IEhv3L
1PX9/2bZ6/Q8+aPDExkNUKNSIzmgqoFcyroWeuyzrFqiAejMY/R+3h3fgbqq9DK0+kAF+kpJlwOr
Rh++tbG0O2BDC1xqgS9KplC6PSAPNpNpqiBqGbGVaeTk3zkqShlIAPmq7G6zcJOnmEIWXBN/0FIK
zy0wZUvvWH36e3creML0zKg/srN8kzIv8zu9hKB6IBYZGwDVO39qKTTLloUzfuA5g7UJYzFGRdja
PgiNIpFxHNkAsihpRoVmAtkzwbUEN+1KOZH7YxwpXa9TPaHn9vqmbuR8U8jA7RgAgXKtsuyIVqdl
P3/4sNDu8wP40tVgFQEaLcQxB2xLu7wjjC6InxrOVgris4Y/FbzhpMCoa+wDAZRhtl9cU7WaQgAI
GJLMrTtE8Bpd/P4I0miUBj7yj+5GZwGet4k01+IAKpQ1RO3bZNXldiDn36iH9BSwQawlaYOsUgN0
L7hl+WKvMH1SGNJF12GdNxXRlbjWgUm868MexU5cOpucKEg2cVFwZyadDP5DgOtm+t1X+LJZOMTe
1U+pSctG/oH376JjbmDCS2VPY24QtHVu6j9HpaEqddhDZ2FJ1GZmij/WdfZuvz/178LtR5wexURe
Ft+9lIhcmi/JteqEKCpztchN4OIzIsEZ32/HHXS8c1q6ZonfoxMId1WKnDT7PCllBlsgwWOR1vWT
WbK67T8KUnHBrJ06xspDAewEmlQxO5ofMVd0rnmCKML/z9yQ/BRE4TE5gCBt16dY6Pskz8dfGKl9
3AjaTff20nmLVchEE4I9yqyn+V1RnP4V88eOQIw9b+AjuwUzVUl6/BdkPLmiyRk1696wDTeVqB3T
QHfpcG58jcqfSivuaG0u3R4CEMFMDGdqTNDnH8sERSb7iflo52F0EpydQtPg7fxBYk1OH6i5odF5
lusH/n6GRjGOTIKpwQpK/MZO12F0YFtG8wNIOInbaYGPYqTHDeUSOrpfMEBefMIAdXsk3V3X2lEl
bhJEzHS28LnDZjE3upV8zb7G9e9NU7KKUIcZDgV5ZWbymww6m9k7HaIPYCLTlgBeUfu6Zm45pwU8
PQMDjcsfcqI3nO5ZEhrV3YG9TH7SR7KfahSVRV6hxRKL51TW3hAQ6VoZ1vGBrIqcjXiIX5ne0eXX
/03Q/4Oh0cNjiEYXQOReAr+j3bTETN4Up6yHm7gN/4ASt4JUhBhzqcnBzxhtZ6y6hl+8sLWNY7I2
z8qSiHHcxlmiaMtiRPkTuSRWwEOSDe58lQvcIDOUuMy3JmjqwR4YrW4D3UbguMHQ6OqQUR6xxgHy
PltYYmJ7sH+CtXwcvSxSv7evaUACbQRtDtlKEPXIoob0THmw9QCxvwT9sPRA3ccbIb6bgN6Orc6R
no10wKvnXrxxky6ROOtZWTRv10o/UhSllE5Df70bP3hBUcHOYQ+PqPt17bh3KVWN/a/OJAL89OvV
vKRCx0SFmikFV7MiKCbz7FFRncsXfyew/OLQicJEy/LV6tq0A48tEYlfiuDarT8vNNBCQk9SuOSE
B8MP/mwhNBMeGurGE8YF9WVwLPx81tmYNfdeuSD53t+DOz3FF3dXIgUy5Fpvt8loe4jyppstlKdq
2qfi4YkR7CtPmiBybgaOLcJwwPFes/TccUGbJFz3LbOjBC3zeYQldK033Ps9TpWlI8vAskrdzTDE
Ip4evOMZlUuT6ZgPbrZqxfignzvGZg/cjBKMPbIcCz/id2dIICPHWYTmke80LkPXQNEdwfIvbBgC
qluxm4VVn9t9X/e68Roa20Nu6V6IlKQ3zT6pFXMl/t7eX2sPIzYBVQgORl/jldpsiL+nZvfE2T5K
TqyAfLe7XEFTrXFGFpfXoqdMeQHV+QoLLlApooJ0jeCO0hWKchiVx2y+P+HDG5/0Uv7oakiabCfG
bQUDuaW58nhOvHjQWdjL6gnbwSzBNK1NssQgncTqtWpKkBhU/2XZ2vq3ZxuPNfQkRec0C9VYdp3D
RlJFVRlzV9FiSosBigg53/smQ7RKp35dyAusZZUSZ9dORgUsHsTxRiQzAFpjEXxRh5hHbGBsmqyV
DCTLma+gFh0BZrrwpMBTHptkMzS8Nsz3xlbqyvSX9+WVi2fH5ltzYyEZGZTbY3f4I7HK9C2o6JNZ
Bs/42jR0zFLMOxyaT+Du/X2auqfIzR22svkwswQ3tZnEO70VU0NKKZgg/tcPin61oRUA4/P4VnjW
dJNO7l9+cM3fkMp3jjGB1W3+G+uHu1PgWllKv1noQhOkXDcwmQpRFDPntZ1gOhpTDr/rKmO2JA3a
GjpLnhKG9oeHhjjm1aCRUtu2V4y0bSjDShaxH4lWxAFoEijtZxHY1LMMSEAudU9uHOabSUVe5Xqc
mHJqaKUHTl55J6AE6XNH3JmzvlamFE76+Tdq+JSYN/3QTfTLxQMxKaR07GHK0x/bqlsZW5GsRVpI
zYATVYGJneQdaK7sOMJlf/tRiLsA99EdnT9n/D57sHnUItuIAyGY+Tvn22ng+U2NvyCIS9hsPhAV
a2vdUBCjAapRLLC7OOKbuWcs/+Ek77QVglr0tsk2g58o/fabO47MZD5xkqD7a4uAb68nfBNL7LDT
xmXy1NIIs/9Xv2+U2VRlpzM0flP88+ACOYEgxV30bLLJaOgvio7Hzvg4hrKa0zyIwxTohUeKPdKP
JfEXzND2BEZN99sDcOouoG7xLBtx0Zlc78oBZyQlMo7lzdOEkcja3R9woDvtBAb3AOHNCy3xiC41
lifAZgeoAC89VHrgtB8ulkav4vNRHbtEQgcCLqL2KjX8GFDEUSAAB91ZD+XDTO2q/EHt3yUEsEjz
8vM7jrggcxjFu0A2YQQ8tXwyfgdaYcq+eLxiPEZ71i/VkEflYDsAsow+qA5ZQbCT1j9uxW+h9dhN
+MgwPqhJj9IiqhX3CTnXqff0K6HNbgVgXHUOzBgIAGNja9IAoq6JknEiiQQZ66J3Fte+cgXcWce4
zfJ47KLqMV1kQcv7ekn8QPP7tTsuJa3TiokAqxma1kS2ywgdigF2TxVTd8OLCKLO4qeps2hyRRBp
hWQbWf7SktygKAM7NYUZun/8KJ8dmvqsS/p4dUCn0NOBg4riHRRwUAWBzAd+9s3EHo18fmoVpjVT
cb1c2FBYJpcSdNtO69GntrwizHJpcnGAqC/sstxPsNXhYpqfYfScW1mHps7IfONegkxTaOr5I3py
7FmDzeoNx1DY2qmMAb76A9+CzN7ZJJl6VikQxVCUum14a47hiRUm3wIeGLvR8GsgZhTtz7UUYZAm
JTrqiBrHMNQo2ddEpHatTqcwhWeKgOVFlFZMBfF86nWNEl5XWAIgScEk8lNiJDpfZ7daNDodMX9K
K0gUw0yyhZfXv2+li9oPtK1uIaCtdhR8v5LfsjgNQrAaVi+xcIFyQ/ZleJF+nHYnJlYeJsK5HFiT
AbgqkLwOLSUm7Npx9HN1ZjSfT76L4BbP1K78nrXLWDJB4/MfWuUivg1/SUlDamAZfm7ZTp6Jklq2
Iah8HH7BMfuTzVY/XdDZ3XwFDwpT40LJpc2kT6QyHau1phZdiqPjKkvevzM36Hs/JazUPMDUhD4r
S14uSDjr37v04L3dkoguPVhG5GOPzusZmEb1d9S3JO1RKxdqAOknFbJa8Zf5roz6JEqAE4U58lE0
/gukjPfc+qGVtEwaexGM2+kdeXMu+Exn096ep6fqJtmHneFLlsjjPSUjF3dSh5mMXI1L2xIH7pNG
fxPlJ0ENIimJMPCr63IpOCfS+ON8N8JwgVEXzjuiOVMfMhtuJJ1ZHuxbZE9RXiJv6oMiKS8I4Y1p
XRApbHTOrmPqSXOJ7Sd5MOGUrBX0iQE5l+0nueP0lk8jEoMBEX89fYw+Ra/NgM+e0AvDbtmS+EDS
ZR7K+apSgbRYYSW9HZ94jrr8qdc8tib81UW1ls+EECs3RECrsiVIr9MsYOyfU9qoS9zKzuGsnavl
ENBRaFW06scczx7xgAK5QuDxv9ZCLrd8+ICnLmLiKFuzRBV7/pfBI20f65AX/oQXY0NQKJyCuQq8
9Xe0K9Vm63RlpegXIl5iY85mLdbg/V996HoJ1EjljY5JnJjf6/Wi0VD6/kFJ/tFB9/4ZmJa5wHkX
BcZqDfiRebt75Ti9YIS342noBG7a1TtnT1pq/xWRBNLHzZtv+raazqq4c4K5uXdDqEjj/mE5MsYp
0huTtHYEpHjuXZ/sFthVGJxkhP8ke9xphseRxzdMONTaGHJ6geGncjSlyeQ4IgR1VWCuGCBMlpfB
ZEevSTnQA5miQBwV73FO34SaCOMkwfKXt9kQmcbbK4LzQuSkwZ9adnrndVenQGzISheAqONHzYJB
Piyk5xwOa0vWDDdjpfhTDeBGJGRC3fYG+Btb3ebEcg91twEBeBQ4dMho5+G5rWpZfA+ZxO8ZFr13
ZG3kU8M1gBuHBbVGWGL0mJRtyxUNwymzsLo8I1Yqv3wik/4TVcsBnEF5LDwdBqwNMCUpc2xyNMsN
9TTDvjYGoEaqGCh3xBBW+46tkfZeyfSLuKB/OvBPEDEHhwGUJjzDAGDfkOHXow323tltO8v5xauo
hFvP2shPp8GalpI0cCTTOJORLTJgxlU0C4Tr+/hKnsK0BC5WEg1VMfVCjOYVbRjoRetFAQkLoerm
RpIegU+j1R3ubwv3/PpiUzJtmHykpYTfllvrK+Ts5XILizqHr+OOG7MLzwUeicjDPCX9Zt68Oqzu
wt8SmrtRFbIxHiXpTNXZnXMwOMneuufBusqfbyvhi8E8W21ggHyAH7A1G0AcFSGChUaV9AR9isQY
B+Wu79nl1zyzbFAE6ZXn5Mypet/La9rKzBJ07i1dsa5S1XdAm2/L+w3UH2IiUItq9pE/P/U7kWj8
UDt2vPoYQL7udegvfPdchv42emkHZJx6QB+asBYCXrNpw+frK+vll+CXNsd/bcy4J9EnDI/qZp8h
MZE1rs4CQl2/8Rut43I1GZ+M32WAEPLQ0+niWMIu+yKfDoI8BGXs1GBlC5nXHdllCXV281xLs8Tz
WiwZ30NZFuCK4VVsq/M3JcDPHKD3RqDM/XBW5545LfsuZkeOQubRVgowdiskPwslCJg6EFUUyPGf
0q87zFsugSOpOIZXB5Eg0MCnErrKFrAt40ONqc5dEQexOM2cP9mJpW81P6b9Kul9WySvPG41m2m0
33ZQg+dFaRutVexTzsEAXzVBhb1I8yasOKfxgYUxxAAnIhmj7ksY3uTUUwD9kaCnLOGibwwTBUVM
kXpkPtNnVZ/qMZAt/VKtlqNnQgQvhfxpfj1kf7ZR6Q+2lX0rXO475nxoVf1TlUn9X1igIXKXelx+
7YysXaqylBS6TrUqMyvsxPhFdqjPeuADEt3rIV+CLHqxLn+Fkk0fapMAJM8VAFIUpw3feiWFagIo
zJ9imhXvPv+5N27SWT5YPE0EVUY/Yh4M19uEJhHc1VtY1TE540pbd5cE6BqmLJQF1dkp3EC/zbBy
wOTXRycCfaozSF0fuLcjLO6j4IdvsU6/SwQg3Q8YxR1hz5A8yr7CsC/77mT4jZmz4Qr15f9N6u4X
L1dKTs1eH2WC68tgsn4cx77LiE4+Mk4+Mv8qO25Koc11lDTI+7emnGG8YT/wA6rebTsqYdRDBlwO
3k9tItfddR11CBQjwJSaoPRCCIdYLnnIoMIsBVcd8sMZ9OvlbqqyEr5OfacVgMEBtCsUzVOGKqXP
57Cv/sbJa397n1wsJGJMCDflDHniTXYgFm0Va1pXp7QCqAiKwY98cpIRIFuoEsW2vopquTpGu1on
VSxsUcg3R4f/oO4Io94RsRCkCja1j96zRfioijN48vbONZ5BQsg0VYQ4tlAS0ukBquYWfyOtPhHY
/EGsXKmNOs8/n5xunC1s3Rfj6fop7tnpZRULGVSd5gro50R52kkZoC7m7iW6puQRaM/0OphXrCoC
YRW8PswQpFX/DWFbDzmyNLJvkhZ9/uGDU6v5lwUPjlzM+MCw0SGyPTdHiYKRP3xdQkJVqAW6Ejls
BCLhKOtuW4rPTT1R1KN5FBPZj4O3SMyu/l9Mm806USJSSINrwX+6RobDvgQihART71eeJNE/0Z9F
Jw3PmhXBHBCjqUQ3l8NxbM0nh7JFsqS6Llg0wbE9maViEyHgBzSn4LCuP80VD8892VKXTBUwnMW1
cqoZafHFvCfEEBdpgeOxgnaVy+osv/eER0ARBTwLv3ZDRJoV4zeFKcphowagxith4dqx9z8QcRNc
LWJNHfx+6q6ZxJIWosnUu+RxYMfbPtvFQMJ5x+bBpGEJ+Wah52ce+TPOee0Ssfj0Z5aLmz2nh4Tq
sQeCPs68Zoadp7Is12fsS1PbRqfNTZgOpSLT07fidfYBICc6Mg+keOVnpRVB3Omenx/pb5bRiZ3P
Wgld3dRXTr8DovlUkM1qnUmeCqcM+lYxVqj7RBcDZwESInMKl7ub52l/sUC6DX32PVWGoKijuwfe
v+cmvmz4dTPk8fRnZSg81CrjNLHZ/SPh7is5OuSbOjVKHhzdtV8KZRN63FiFtGOdMS8zKQNQ8Ci3
p7TJkL4V45Ok5fDe4i8F2diOgfRWvzWBXsQRf8g/ceYmWHLcW7kHQWm4y767cUwqSWZ7sSMuXzUT
c/L5XatTvL+lj6eRu9rOp/5EcscYZX+MNH81VZBQuB4MlCfyjeZN93qsoNodDhnX6NFVMiCcFRUL
6mUBTZHlDfxXVvjRYv/RyaYRPM4AJsP5lSO0ynGm/dQBfO8sQeINCQU4nmaz/Vd66HXLnk96H6w1
EiwIGCVkGWWFIUcw6Hz0jNdE0hY7Oxu0oW5KMBBH9ugvZl+w/6pyJYmA0yQufuZw0FlRcOOYH39T
iWSfRd43vmIHZRkbFKrg1M6LtZVWy9jSZJqvAciuZGSwNDc7qpJC5hI0THHfvrLriMAW+3XJXirh
QmNYVvh26NzeGy5WnYFmbegeT96lscDP/8UlCPQCZ0/X9YacvNKy4UxzgIv6WHX2flonZJZr6rLy
v7CRlCvaRcGG6QIV3IpKihlnbZVRbm49BOG4hK5HDn2LNupujtiEUdZI9XPjLswL4FE+pG0De8/B
v4EIrNXJlKy4gMO/WtWW7qp3wJaRS/5kuyMHHfOoibA4skVzOGBPx7EoInOIC05l82WVG0SiRqZW
35eXfiqPu/kf+42WPfq6+h7IdwgJWdS1/axRgNQ2Kjr1iwYJ29c2IKp4l0bTNcPA78qt6cn14+bs
l2S4wJl/JkMTrc2AyGBBx4dFm2jl6xRafHheFt67hAseYoE6KBtn78KkdnVqL3A492A/TyNpLhM8
cpz2WoYvlrxOrh+mPMCD26/wBRaF5SiJFMlEWnGW5HyFIW+ygVPH/ffeoprWgZaym4QvsQ1mBvp3
lf0QgPcvPHIIP2Al6W3jHUTVhKyHleKEAclLwUtuRAerPgVLiBMGl3rQoTluBQ+nThe9Xonjxfkz
TredlD5ET/AwZwmfdNSDwEe27X3dD7yDSr/U3OsCmu+KEBZNTYimMV48L+V+mzJcIlLh6zr9Ae9N
5wiNzKJECBXWx40fLwLSeV3mnnP5dH2L+MsecRxLp/wTcWNhpRLWdhiwHsiPsqAIY7rKJjvkS964
1CvVKRWeWDASllnBlKFOY2SzNMUuZGku5wIc5MkjUEnY3YnhV5h/Y1TtqPZlohjwLE3KgrvOi7s9
z3Rnyc038JXBVoXmmcFSzYsPNUl9tM291LmfAaKrJTxSspFycJn81+bcd4+2NvL0wD3DKBVW64va
OBwIaZYzlvIxL4XrEB1N+V47PioqqM/JdPdxEY8KJh9XAKF7zHRQxLAbrVjwwJGQTL9gAWN7AbZs
WoSSM7Jrh0iPv76vtRLyVijje9Qkz01RbYI/bf39/gy9OvA0iiBD5piBuwCZfocPcx0pyj+xkKBg
tgMeLLRSZBSINXW9AZUM9V60ZO32U12DxdbhW+LAG+JNomtPoxROhal+puZKIifRHadTonvfGQHN
aWnDf8gYmLnGZ2qZNiMLw/MHRCmYkQPJo+knlztOYbe/k4CNoNO4slZWfIQelFwThulMhsqqPZSh
O3R96HIffsKvIKcUGfshgtEfU0dzJpIeEIAtlkk+IdIJGoa+7+SdqtvxVfrP1EdWapLYUrQ4o+C/
z2mGxH2VtREYERwkhdDZaNEqMALjGzXxMCstrk1bxt0qG2A5OOM9yoKbxgvJzbG98WtbZo0vKWJF
mtYo2KjYxwwXPtAZBUStzOhBCb78nADWMNLBH9VmyGLIgXcfvKffa2RhV46cKZhGU7Ib+eVvH3xE
aTDfrSet4K8IRrmiyV7O+p1U84aNMeLqGXes+Nsew22GaCT787khxrShOpATNEkMTS9dT7ayr7oJ
G6Xr3rjzKGLen/dF8aDXx6+4wpGxOaOPVkiN680XdurFNIHCQYjfQ8kRH2kfErIjm8gC9NcNPtAU
K4UH0NrbTnHb2gFNjQdjnCtyHCzjz3fasExPJKzeJf/szviqAOIuFQ1NIalrU3ZV7loTQfBFHINz
qgGELz1alvfsEVba6S8K6uIUpM/UMB6GY4gJ3M75zwacYOdMVacANoebUZp9HA4T3WWp2sHAioh0
/UFJ47eHyBxorORsN6kmrtFsOqmAXsD3VvjXWOxhC1N/XDygI7RwSkK/k25BP0EmLLaAD4bAQHGb
ePRtiCKhtVeSPlFTtGp3NnkMAcmJY+3pw5o42+K+6nheQ7KPxFTWOXrzNven1aXJExEmC44lgZrL
GmfESyQk0P+4imMWvdOsiJKDpQtLa+ne26kM4wMTnZRGXN6KV6r+zjL/Tzla84Qzkgv/ZEA/AjTX
1YvSxFfykJCYM5UOPYmUVcDP95UAAZidc9qb6qWHaucBCsp1wYMpZwNseMCZvVFurF3u9oykErYA
rjylcC91VJksKmT4+vpMYMRyBVQ6JNqP2ALhYqVKr2USc63xJMXa8KXS3HxpSMXIljfVS1JXSIYi
F+6sqt2lZkLq6WDYS3rraNDpiZOv4Nf78NqQPFaZXLL/QS/gFgNqawyc3ixpz4QEZDXD3cUZZ0zI
e5GAd/eTRm5H5lsfT/oe5gYRR0Az0thkpTp8uOzuyARk7paP9IgNn79+QW07F41gXoeoHaeNg3Yc
9O/XTXLro73dMKDQ9iEX1vQhb2guqndxDU6j+tVz/b8ybMRGQC1/emr6R8kBxzHQauIAg28vnLkN
8et87Xy9THN5kU9bnrwRff7zWoH5uJ3pt+mNfvwibjTAGJq4FPooI5VwDaw11ViUbRxXSKrmbf5Y
1lydbRjhUze0VM2maWOyK9M6JWA/1h04mOsHbIEUuR924f98VCQyy3gvrHEyhV5D2sdm8n5l8rdz
x3zDbAogF+qIwvVIp12mIkOufqJC5rlk5GwhBDZ2DMEOhI+6e0Sc21I+JZ3zEgiCLE8C2Lj0LpIv
1PSp29o1L4p+pNitAbUhPhaehjw5kxkyvG3Wm5uL+afE2LDdSLoAf62eUNO+BgnpWmpQ3T1NeYC+
71uQ1zXdiS5ougM/SB61u5UX8rmsT86wvml4aSJieqZ7wn0rQW9aDDzvogh893mspNWFXovi3tN5
ergnpJvF8tvwPdoUH+tCww5Q+MuMtcF8bvQblYsUXRBxcFk2tX5Ao/nm5A3ewx9m+oO7FfYZ5JeY
MbEdA4I9y8tDBIpMa9vu5HbMvNppSIYL0X9l9CTTrDVwwGXoIcDj7orPJPDyFgC4H0+ze8tH6lZ/
UaVVewSB46qmqzwiBn/9AghbMoA/oYJNhMpsMUsAor6R6lV5iBBE++HvB7f9nheGH6p8HUfHikOW
H9Mhw3zyOzn0rYJvkh6S0i+s+lBWJi/ZdWcaejFH4enD16HuNRaWNU4NJ8MtKKeE3/gj8ocihV+x
1wIvCIz5tsR+mAqFhAFBpJvtyA8Bj3gycC7UEs+XgvgdOtkrt8P+NetjqlKI+n3jP4lMtCYj0QUe
bMRtF5CfERzgNHsfGQP4HEJymYLVvO+5NaiCRtQvwLPezz6ZwvIH1qlXVRhzWRhW5svT2rtQZzoE
2uFBoiS3TWGY55g35KAmZfcFncPaAs2HNE0yvNbT0Qh80R3WmCRASFFC5Hdf0BPg4OF+X6l1tVgr
e5jBjIFR5lEtKRASAEP+XVBJp4AufmvaOFUpzyk33sMaMSmZ8+1ixDtbwygBlZOn7nVKi01w0OqF
35ChIYwVSj6jKVY6gm0IeasBApKXEu6UAu526nzHEy1NSEtXC/3DdWlIb75jAG7dMQWwtdqkHa4V
G6fdThkFu9YnsyGnZHqUeEiyl+z42hSLZyzyeig21ZtC4bA1MLvnAtcvZPZTGR2NnPIWEBdlKZeD
RPF/kqoVMXURISkLMTZhdQXsWNHujVUhz+y7HdrTz9kgGT3v4v2fLN68t1c+FWVHm4YGOpDMRGLM
jmDPY+bN1R7XYNSbYlw7WCo/7v19IDluxxQ3atMmEgeaCyBuGtoI/TfPdSN0W4DJWS/rR7BupZr3
eDcy37yrh0UdK/XDTRWmAg95JSICoRgWTtbPJignrPUe+G0bKGz/JXZ1TWCfWMNJMjzlzih52G1t
0mu2cN1FBn9mMU9+t/dDFcprVpwMI/fObE9JFkW9kWp+MiqQBckPufqLlSLnsqq+q0mN27Qb81vS
/QPxnwyZBdtAOGpvxFdw9GJWZ900T5VE1dWvnuATCVVJOGSFHyLwxYHSsqPn5j/EOztgQXQZ7wld
qgZpOnyUPwGxreYZzSrrkaPISd83+3XSSogfpvb7Mjo58yvoRMwlxk1veoyQ70QH4puqilaAavWq
N6p/DvnaK8KrPqWwT8fnJgk2kKyFu+rbHsZ28w==
`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mul8_16_mult_gen_v12_0_12 is
port (
CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 7 downto 0 );
B : in STD_LOGIC_VECTOR ( 15 downto 0 );
CE : in STD_LOGIC;
SCLR : in STD_LOGIC;
ZERO_DETECT : out STD_LOGIC_VECTOR ( 1 downto 0 );
P : out STD_LOGIC_VECTOR ( 15 downto 0 );
PCASC : out STD_LOGIC_VECTOR ( 47 downto 0 )
);
attribute C_A_TYPE : integer;
attribute C_A_TYPE of mul8_16_mult_gen_v12_0_12 : entity is 1;
attribute C_A_WIDTH : integer;
attribute C_A_WIDTH of mul8_16_mult_gen_v12_0_12 : entity is 8;
attribute C_B_TYPE : integer;
attribute C_B_TYPE of mul8_16_mult_gen_v12_0_12 : entity is 1;
attribute C_B_VALUE : string;
attribute C_B_VALUE of mul8_16_mult_gen_v12_0_12 : entity is "10000001";
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of mul8_16_mult_gen_v12_0_12 : entity is 16;
attribute C_CCM_IMP : integer;
attribute C_CCM_IMP of mul8_16_mult_gen_v12_0_12 : entity is 0;
attribute C_CE_OVERRIDES_SCLR : integer;
attribute C_CE_OVERRIDES_SCLR of mul8_16_mult_gen_v12_0_12 : entity is 0;
attribute C_HAS_CE : integer;
attribute C_HAS_CE of mul8_16_mult_gen_v12_0_12 : entity is 0;
attribute C_HAS_SCLR : integer;
attribute C_HAS_SCLR of mul8_16_mult_gen_v12_0_12 : entity is 0;
attribute C_HAS_ZERO_DETECT : integer;
attribute C_HAS_ZERO_DETECT of mul8_16_mult_gen_v12_0_12 : entity is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of mul8_16_mult_gen_v12_0_12 : entity is 3;
attribute C_MODEL_TYPE : integer;
attribute C_MODEL_TYPE of mul8_16_mult_gen_v12_0_12 : entity is 0;
attribute C_MULT_TYPE : integer;
attribute C_MULT_TYPE of mul8_16_mult_gen_v12_0_12 : entity is 0;
attribute C_OPTIMIZE_GOAL : integer;
attribute C_OPTIMIZE_GOAL of mul8_16_mult_gen_v12_0_12 : entity is 1;
attribute C_OUT_HIGH : integer;
attribute C_OUT_HIGH of mul8_16_mult_gen_v12_0_12 : entity is 23;
attribute C_OUT_LOW : integer;
attribute C_OUT_LOW of mul8_16_mult_gen_v12_0_12 : entity is 8;
attribute C_ROUND_OUTPUT : integer;
attribute C_ROUND_OUTPUT of mul8_16_mult_gen_v12_0_12 : entity is 0;
attribute C_ROUND_PT : integer;
attribute C_ROUND_PT of mul8_16_mult_gen_v12_0_12 : entity is 0;
attribute C_VERBOSITY : integer;
attribute C_VERBOSITY of mul8_16_mult_gen_v12_0_12 : entity is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of mul8_16_mult_gen_v12_0_12 : entity is "kintexu";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mul8_16_mult_gen_v12_0_12 : entity is "mult_gen_v12_0_12";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of mul8_16_mult_gen_v12_0_12 : entity is "yes";
end mul8_16_mult_gen_v12_0_12;
architecture STRUCTURE of mul8_16_mult_gen_v12_0_12 is
signal \<const0>\ : STD_LOGIC;
signal NLW_i_mult_PCASC_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_i_mult_ZERO_DETECT_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_A_TYPE of i_mult : label is 1;
attribute C_A_WIDTH of i_mult : label is 8;
attribute C_B_TYPE of i_mult : label is 1;
attribute C_B_VALUE of i_mult : label is "10000001";
attribute C_B_WIDTH of i_mult : label is 16;
attribute C_CCM_IMP of i_mult : label is 0;
attribute C_CE_OVERRIDES_SCLR of i_mult : label is 0;
attribute C_HAS_CE of i_mult : label is 0;
attribute C_HAS_SCLR of i_mult : label is 0;
attribute C_HAS_ZERO_DETECT of i_mult : label is 0;
attribute C_LATENCY of i_mult : label is 3;
attribute C_MODEL_TYPE of i_mult : label is 0;
attribute C_MULT_TYPE of i_mult : label is 0;
attribute C_OUT_HIGH of i_mult : label is 23;
attribute C_OUT_LOW of i_mult : label is 8;
attribute C_ROUND_OUTPUT of i_mult : label is 0;
attribute C_ROUND_PT of i_mult : label is 0;
attribute C_VERBOSITY of i_mult : label is 0;
attribute C_XDEVICEFAMILY of i_mult : label is "kintexu";
attribute c_optimize_goal of i_mult : label is 1;
attribute downgradeipidentifiedwarnings of i_mult : label is "yes";
begin
PCASC(47) <= \<const0>\;
PCASC(46) <= \<const0>\;
PCASC(45) <= \<const0>\;
PCASC(44) <= \<const0>\;
PCASC(43) <= \<const0>\;
PCASC(42) <= \<const0>\;
PCASC(41) <= \<const0>\;
PCASC(40) <= \<const0>\;
PCASC(39) <= \<const0>\;
PCASC(38) <= \<const0>\;
PCASC(37) <= \<const0>\;
PCASC(36) <= \<const0>\;
PCASC(35) <= \<const0>\;
PCASC(34) <= \<const0>\;
PCASC(33) <= \<const0>\;
PCASC(32) <= \<const0>\;
PCASC(31) <= \<const0>\;
PCASC(30) <= \<const0>\;
PCASC(29) <= \<const0>\;
PCASC(28) <= \<const0>\;
PCASC(27) <= \<const0>\;
PCASC(26) <= \<const0>\;
PCASC(25) <= \<const0>\;
PCASC(24) <= \<const0>\;
PCASC(23) <= \<const0>\;
PCASC(22) <= \<const0>\;
PCASC(21) <= \<const0>\;
PCASC(20) <= \<const0>\;
PCASC(19) <= \<const0>\;
PCASC(18) <= \<const0>\;
PCASC(17) <= \<const0>\;
PCASC(16) <= \<const0>\;
PCASC(15) <= \<const0>\;
PCASC(14) <= \<const0>\;
PCASC(13) <= \<const0>\;
PCASC(12) <= \<const0>\;
PCASC(11) <= \<const0>\;
PCASC(10) <= \<const0>\;
PCASC(9) <= \<const0>\;
PCASC(8) <= \<const0>\;
PCASC(7) <= \<const0>\;
PCASC(6) <= \<const0>\;
PCASC(5) <= \<const0>\;
PCASC(4) <= \<const0>\;
PCASC(3) <= \<const0>\;
PCASC(2) <= \<const0>\;
PCASC(1) <= \<const0>\;
PCASC(0) <= \<const0>\;
ZERO_DETECT(1) <= \<const0>\;
ZERO_DETECT(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
i_mult: entity work.mul8_16_mult_gen_v12_0_12_viv
port map (
A(7 downto 0) => A(7 downto 0),
B(15 downto 0) => B(15 downto 0),
CE => '0',
CLK => CLK,
P(15 downto 0) => P(15 downto 0),
PCASC(47 downto 0) => NLW_i_mult_PCASC_UNCONNECTED(47 downto 0),
SCLR => '0',
ZERO_DETECT(1 downto 0) => NLW_i_mult_ZERO_DETECT_UNCONNECTED(1 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mul8_16 is
port (
CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 7 downto 0 );
B : in STD_LOGIC_VECTOR ( 15 downto 0 );
P : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of mul8_16 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of mul8_16 : entity is "mul8_16,mult_gen_v12_0_12,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of mul8_16 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of mul8_16 : entity is "mult_gen_v12_0_12,Vivado 2016.4";
end mul8_16;
architecture STRUCTURE of mul8_16 is
signal NLW_U0_PCASC_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_U0_ZERO_DETECT_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_A_TYPE : integer;
attribute C_A_TYPE of U0 : label is 1;
attribute C_A_WIDTH : integer;
attribute C_A_WIDTH of U0 : label is 8;
attribute C_B_TYPE : integer;
attribute C_B_TYPE of U0 : label is 1;
attribute C_B_VALUE : string;
attribute C_B_VALUE of U0 : label is "10000001";
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of U0 : label is 16;
attribute C_CCM_IMP : integer;
attribute C_CCM_IMP of U0 : label is 0;
attribute C_CE_OVERRIDES_SCLR : integer;
attribute C_CE_OVERRIDES_SCLR of U0 : label is 0;
attribute C_HAS_CE : integer;
attribute C_HAS_CE of U0 : label is 0;
attribute C_HAS_SCLR : integer;
attribute C_HAS_SCLR of U0 : label is 0;
attribute C_HAS_ZERO_DETECT : integer;
attribute C_HAS_ZERO_DETECT of U0 : label is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of U0 : label is 3;
attribute C_MODEL_TYPE : integer;
attribute C_MODEL_TYPE of U0 : label is 0;
attribute C_MULT_TYPE : integer;
attribute C_MULT_TYPE of U0 : label is 0;
attribute C_OUT_HIGH : integer;
attribute C_OUT_HIGH of U0 : label is 23;
attribute C_OUT_LOW : integer;
attribute C_OUT_LOW of U0 : label is 8;
attribute C_ROUND_OUTPUT : integer;
attribute C_ROUND_OUTPUT of U0 : label is 0;
attribute C_ROUND_PT : integer;
attribute C_ROUND_PT of U0 : label is 0;
attribute C_VERBOSITY : integer;
attribute C_VERBOSITY of U0 : label is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "kintexu";
attribute c_optimize_goal : integer;
attribute c_optimize_goal of U0 : label is 1;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.mul8_16_mult_gen_v12_0_12
port map (
A(7 downto 0) => A(7 downto 0),
B(15 downto 0) => B(15 downto 0),
CE => '1',
CLK => CLK,
P(15 downto 0) => P(15 downto 0),
PCASC(47 downto 0) => NLW_U0_PCASC_UNCONNECTED(47 downto 0),
SCLR => '0',
ZERO_DETECT(1 downto 0) => NLW_U0_ZERO_DETECT_UNCONNECTED(1 downto 0)
);
end STRUCTURE;
| bsd-3-clause | 1f660b0e9503d4be9dbee93ef8a32988 | 0.943729 | 1.834687 | false | false | false | false |
dtysky/DDR2_CONTROLLER | DDR_CONTROL.vhd | 1 | 15,885 | --author : dtysky--
----The wr_num or rd_num must be less than x"0100"----
----It means Only 1 line would be read/write per operation----
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
entity DDR2_CONTROL is
generic
(
----------------------timing-------------------
constant tRPA:integer:=4; --PRC ALL Period
constant tMRD:integer:=2; --LM Cycle
constant tRFC:integer:=25; --RF to BA/RF
constant tRP:integer:=3; --PRC ONE Period
constant tWR:integer:=3; --Write Recovery
constant tRCD:integer:=3; --BA TO WR/RD
constant tXSRD:integer:=200; --EXT SRF TO OTHER
constant AL:integer:=2;
constant CL:integer:=3;
constant BL:integer:=4;
constant BLC:integer:=2; ---BL/2
constant WL:integer:=4; ----AL+CL-1
constant RL:integer:=5; ----AL+CL
constant SETUP:integer:=35000;
-----------------------CMD---------------------
constant CMD_INIT:std_logic_vector(4 downto 0):="01000";
constant CMD_LM:std_logic_vector(4 downto 0):="10000";
constant CMD_RF:std_logic_vector(4 downto 0):="10001";
constant CMD_SRF_IN:std_logic_vector(4 downto 0):="00001";
constant CMD_SRF_OUT:std_logic_vector(4 downto 0):="10111";
constant CMD_PRC:std_logic_vector(4 downto 0):="10010";
constant CMD_BA:std_logic_vector(4 downto 0):="10011";
constant CMD_WR:std_logic_vector(4 downto 0):="10100";
constant CMD_RD:std_logic_vector(4 downto 0):="10101";
constant CMD_NOP:std_logic_vector(4 downto 0):="10111";
----------PD FAST,WR=2,CL=3,BT SE,BL=4------------
----------------MR with DLL RESET-----------------
constant MR1:std_logic_vector(12 downto 0):="0010100110010";
---------------MR without DLL RESET---------------
constant MR2:std_logic_vector(12 downto 0):="0010000110010";
--RDQS/DQS# OFF,OCD/DLL ON,ODS FULL,RTT=50,AL=2---
---------------EMR with OCD default---------------
constant EMR_0:std_logic_vector(12 downto 0):="0011111010100";
-----------------EMR with OCD exit----------------
constant EMR_1:std_logic_vector(12 downto 0):="0010001010100";
---------------------default----------------------
constant EMR2:std_logic_vector(12 downto 0):="0000000000000";
constant EMR3:std_logic_vector(12 downto 0):="0000000000000"
);
port
(
pll_lock:in std_logic;
clk_control_p,clk_control_n,clk_out_p,clk_out_n:in std_logic;
clk_data:in std_logic;
clk,n_clk:out std_logic;
cke,n_cs,n_ras,n_cas,n_we:out std_logic:='1';
udm,ldm:out std_logic:='0';
udqs_in,ldqs_in:in std_logic:='1';
udqs_out,ldqs_out:out std_logic:='1';
dqs_en:out std_logic:='0';
odt:out std_logic:='0';
bank:out std_logic_vector(2 downto 0):="000";
addr:out std_logic_vector(12 downto 0):="0000000000000";
ram_data_in:in std_logic_vector(15 downto 0):=x"0000";
ram_data_out:out std_logic_vector(15 downto 0):=x"0000";
ram_data_en:out std_logic:='0';
ram_reset:in std_logic:='0';
wr_rqu,rd_rqu:in std_logic:='0';
wr_ready,rd_ready:out std_logic:='0';
wr_end,rd_end:out std_logic:='0';
udm_in,ldm_in:in std_logic:='0';
write_num:in std_logic_vector(15 downto 0);
read_num:in std_logic_vector(15 downto 0);
data_other_in:in std_logic_vector(15 downto 0);
data_other_out:out std_logic_vector(15 downto 0);
bank_other:in std_logic_vector(2 downto 0);
addr_other_row:in std_logic_vector(12 downto 0);
addr_other_col:in std_logic_vector(9 downto 0)
);
end entity;
architecture ddr2_con of DDR2_CONTROL is
---------------------clock-----------------------
signal clk_self,clk_out:std_logic;
----------cke,n_cs,n_ras,n_cas,n_we--------------
signal cmd:std_logic_vector(4 downto 0):=CMD_INIT;
--------------------flags------------------------
type states is (start,wr,rd,prc,srf,arf,reset);
--attribute states_encoding:string;
--attribute states_encoding of states:type is "000 001 010 011 100 101 110";
signal state:states:=start;
-------------------addr buffer-------------------
signal addr_row:std_logic_vector(12 downto 0):="1111111111111";
signal addr_other_row_s:std_logic_vector(12 downto 0);
signal addr_col:std_logic_vector(9 downto 0);
signal bank_s:std_logic_vector(2 downto 0);
--------------------others-----------------------
signal wr_start,rd_start:std_logic:='0';
signal wr_ready_s,rd_ready_s:std_logic:='0';
signal rd_ready_s_1,rd_ready_s_2:std_logic:='0';
signal wr_rqu_s,rd_rqu_s:std_logic;
signal udqs_last,udqs_last_last:std_logic:='0';
signal write_num_s,read_num_s:std_logic_vector(15 downto 0);
signal dqs_en_s:std_logic:='0';
begin
clk<=clk_out_p;
n_clk<=clk_out_n;
cke<=cmd(4);
n_cs<=cmd(3);
n_ras<=cmd(2);
n_cas<=cmd(1);
n_we<=cmd(0);
rd_ready_s<=rd_ready_s_1 or rd_ready_s_2;
wr_ready<=wr_ready_s;
rd_ready<=rd_ready_s;
CONTROL:process(clk_control_p,pll_lock)
variable con_init:integer range 0 to 65535:=0;
variable con_srf:integer range 0 to 255:=0;
variable con_arf:integer range 0 to 31:=0;
variable con_prc:integer range 0 to 7:=0;
variable con_write:integer range 0 to 15:=0;
variable con_write_trans:integer range 0 to 3:=0;
variable con_write_total:integer range 0 to 65536;
variable con_read:integer range 0 to 63:=0;
variable con_read_trans:integer range 0 to 3:=0;
variable con_read_total:integer range 0 to 65536:=0;
variable con_reset:integer range 0 to 31:=0;
begin
if clk_control_p'event and clk_control_p='1' and pll_lock='1' then
if ram_reset='1' then
state<=reset;
else
case state is
---------------------INIT---------------------
when start=>
con_init:=con_init+1;
case con_init is
when 10 =>
odt<='0';
when SETUP=>
cmd<=CMD_NOP;
when SETUP+100=>
cmd<=CMD_PRC;
addr(10)<='1';
when SETUP+100+1=>
cmd<=CMD_NOP;
when SETUP+100+tRPA+1=>
cmd<=CMD_LM;
bank<="010";
addr<=EMR2;
when SETUP+100+tRPA+2=>
cmd<=CMD_NOP;
when SETUP+100+tRPA+tMRD+2=>
cmd<=CMD_LM;
bank<="011";
addr<=EMR3;
when SETUP+100+tRPA+tMRD+3=>
cmd<=CMD_NOP;
when SETUP+100+tRPA+tMRD+tMRD+3=>
cmd<=CMD_LM;
bank<="001";
addr<=EMR_0;
when SETUP+100+tRPA+tMRD+tMRD+4=>
cmd<=CMD_NOP;
when SETUP+100+tRPA+tMRD+tMRD+tMRD+4=>
cmd<=CMD_LM;
bank<="000";
addr<=MR1;
when SETUP+100+tRPA+tMRD+tMRD+tMRD+5=>
cmd<=CMD_NOP;
when SETUP+100+tRPA+tMRD+tMRD+tMRD+tMRD+5=>
cmd<=CMD_PRC;
addr(10)<='1';
when SETUP+100+tRPA+tMRD+tMRD+tMRD+tMRD+6=>
cmd<=CMD_NOP;
when SETUP+100+tRPA+tMRD+tMRD+tMRD+tMRD+tRPA+6=>
cmd<=CMD_RF;
when SETUP+100+tRPA+tMRD+tMRD+tMRD+tMRD+tRPA+7=>
cmd<=CMD_NOP;
when SETUP+100+tRPA+tMRD+tMRD+tMRD+tMRD+tRPA+tRFC+7=>
cmd<=CMD_RF;
when SETUP+100+tRPA+tMRD+tMRD+tMRD+tMRD+tRPA+tRFC+8=>
cmd<=CMD_NOP;
when SETUP+100+tRPA+tMRD+tMRD+tMRD+tMRD+tRPA+tRFC+tRFC+8=>
cmd<=CMD_LM;
bank<="000";
addr<=MR2;
when SETUP+100+tRPA+tMRD+tMRD+tMRD+tMRD+tRPA+tRFC+tRFC+9=>
cmd<=CMD_NOP;
when SETUP+100+tRPA+tMRD+tMRD+tMRD+tMRD+tRPA+tRFC+tRFC+tMRD+9=>
cmd<=CMD_LM;
bank<="001";
addr<=EMR_0;
when SETUP+100+tRPA+tMRD+tMRD+tMRD+tMRD+tRPA+tRFC+tRFC+tMRD+10=>
cmd<=CMD_NOP;
when SETUP+100+tRPA+tMRD+tMRD+tMRD+tMRD+tRPA+tRFC+tRFC+tMRD+tMRD+10=>
cmd<=CMD_LM;
bank<="001";
addr<=EMR_1;
when SETUP+100+tRPA+tMRD+tMRD+tMRD+tMRD+tRPA+tRFC+tRFC+tMRD+tMRD+11=>
cmd<=CMD_NOP;
when SETUP+1000=>
state<=srf;
con_init:=0;
when others=>
con_init:=con_init;
end case;
------------------AUTO REFRESH----------------
when arf=>
if dqs_en_s='0' then
wr_end<='0';
rd_end<='0';
case con_arf is
when 0 =>
con_arf:=con_arf+1;
cmd<=CMD_RF;
when 1=>
cmd<=CMD_NOP;
con_arf:=con_arf+1;
when 1+tRFC=>
con_arf:=0;
if wr_rqu_s='1' then
udm<=udm_in;
ldm<=ldm_in;
bank_s<=bank_other;
addr_row<=addr_other_row;
addr_col<=addr_other_col;
write_num_s<=write_num;
state<=wr;
elsif rd_rqu_s='1' then
udm<=udm_in;
ldm<=ldm_in;
bank_s<=bank_other;
addr_row<=addr_other_row;
addr_col<=addr_other_col;
read_num_s<=read_num;
state<=rd;
else
state<=arf;
end if;
when others=>
con_arf:=con_arf+1;
end case;
elsif wr_ready_s='1' then
case con_write is
when WL =>---WL?未定
wr_end<='1';
wr_ready_s<='0';
dqs_en_s<='0';
dqs_en<='0';
ram_data_en<='0';
con_write:=0;
when others=>
con_write:=con_write+1;
end case;
elsif rd_ready_s='1' then
case con_read is
when RL =>---RL?未定
rd_end<='1';
rd_ready_s_1<='0';
dqs_en_s<='0';
dqs_en<='0';
ram_data_en<='0';
con_read:=0;
when others=>
con_read:=con_read+1;
end case;
else
state<=reset;
end if;
------------------SELF REFRESH----------------
when srf=>
case con_srf is
when 0 =>
cmd<=CMD_SRF_IN;
con_srf:=con_srf+1;
when 1 =>
if wr_rqu_s='1' then
cmd<=CMD_SRF_OUT;
con_srf:=con_srf+1;
elsif rd_rqu_s='1' then
cmd<=CMD_SRF_OUT;
con_srf:=con_srf+1;
else
con_srf:=con_srf;
end if;
when 1+tXSRD =>
if wr_rqu_s='1' or rd_rqu_s='1' then
udm<=udm_in;
ldm<=ldm_in;
wr_end<='0';
rd_end<='0';
bank_s<=bank_other;
addr_row<=addr_other_row;
addr_col<=addr_other_col;
write_num_s<=write_num;
state<=prc;
con_srf:=0;
else
state<=reset;
end if;
when others =>
con_srf:=con_srf+1;
end case;
-------------------PRECHARGE------------------
when prc=>
case con_prc is
when 0 =>
bank<=bank_s;
addr<=addr_row;
con_prc:=con_prc+1;
when 1 =>
cmd<=CMD_PRC;
con_prc:=con_prc+1;
when 2 =>
cmd<=CMD_NOP;
con_prc:=con_prc+1;
when 1+tRP =>
con_prc:=0;
state<=arf;
when others=>
con_prc:=con_prc+1;
end case;
---------------------WRITE--------------------
when wr=>
if dqs_en_s='0' then
case con_write is
when 1 =>
cmd<=CMD_BA;
ram_data_en<='1';
bank<=bank_s;
addr<=addr_row;
con_write_total:=1;
con_write:=con_write+1;
when 2 =>
cmd<=CMD_NOP;
con_write:=con_write+1;
when 2+tRCD =>
cmd<=CMD_WR;
addr(9 downto 0)<=addr_col;
addr(12 downto 10)<="000";
con_write:=con_write+1;
when 3+tRCD =>
cmd<=CMD_NOP;
wr_start<='1';
addr_col<=addr_col+BL;
con_write:=con_write+1;
when 3+tRCD+WL-2 =>
dqs_en<='1';
--wr_ready_s<='1';
con_write:=con_write+1;
when 3+tRCD+WL-1 =>
dqs_en_s<='1';
wr_ready_s<='1';
con_write:=0;
when others =>
con_write:=con_write+1;
end case;
else
state<=state;
end if;
if wr_start='1' then
case con_write_trans is
when BLC-1 =>
cmd<=CMD_NOP;
addr_col<=addr_col+BL;
con_write_trans:=0;
con_write_total:=con_write_total+1;
if con_write_total=conv_integer(write_num_s) then
-- dqs_en_s<='0';
-- ram_data_en<='0';
wr_start<='0';
state<=prc;
else
wr_start<=wr_start;
end if;
when 0 =>
cmd<=CMD_WR;
addr(9 downto 0)<=addr_col;
addr(12 downto 10)<="000";
con_write_trans:=con_write_trans+1;
when others =>
con_write_trans:=con_write_trans+1;
end case;
else
state<=state;
end if;
---------------------READ---------------------
when rd=>
if rd_ready_s_2='1' then
rd_ready_s_1<='1';
else
rd_ready_s_1<=rd_ready_s_1;
end if;
if dqs_en_s='0' then
case con_read is
when 1 =>
cmd<=CMD_BA;
ram_data_en<='0';
bank<=bank_s;
addr<=addr_row;
con_read:=con_read+1;
when 2 =>
cmd<=CMD_NOP;
con_read:=con_read+1;
when 2+tRCD =>
cmd<=CMD_RD;
addr(9 downto 0)<=addr_col;
addr(12 downto 10)<="000";
con_read:=con_read+1;
when 3+tRCD =>
cmd<=CMD_NOP;
rd_start<='1';
addr_col<=addr_col+BL;
con_read:=con_read+1;
when 3+tRCD+RL-2 =>
con_read:=con_read+1;
when 3+tRCD+RL-1 =>
dqs_en_s<='1';
con_read:=0;
when others =>
con_read:=con_read+1;
end case;
else
state<=state;
end if;
if rd_start='1' then
case con_read_trans is
when BLC-1 =>
addr_col<=addr_col+BL;
cmd<=CMD_NOP;
if con_read_total=conv_integer(read_num_s) then
rd_start<='0';
con_read_total:=0;
state<=prc;
else
rd_start<=rd_start;
end if;
con_read_trans:=0;
when 0 =>
cmd<=CMD_RD;
addr(9 downto 0)<=addr_col;
addr(12 downto 10)<="000";
con_read_total:=con_read_total+1;
con_read_trans:=con_read_trans+1;
--when 1 =>
--cmd<=CMD_NOP;
--con_read_total:=con_read_total+1;
when others =>
state<=reset;
end case;
else
state<=state;
end if;
---------------------RESET--------------------
when reset=>
con_arf:=0;
con_prc:=0;
con_read:=0;
con_read_total:=0;
con_read_trans:=0;
con_srf:=0;
con_write:=0;
con_write_total:=0;
con_write_trans:=0;
wr_ready_s<='0';
rd_ready_s_1<='0';
rd_start<='0';
dqs_en_s<='0';
dqs_en<='0';
ram_data_en<='0';
cmd<=CMD_NOP;
case con_reset is
when 20 =>
state<=prc;
con_reset:=0;
when others =>
con_reset:=con_reset+1;
end case;
--------------------OTHERS--------------------
when others=>
state<=reset;
end case;
wr_rqu_s<=wr_rqu;
rd_rqu_s<=rd_rqu;
end if;
end if;
end process;
--------------------dqs/dq-write---------------------
with dqs_en_s select
udqs_out<=
clk_control_n when '1',
'0' when others;
with dqs_en_s select
ldqs_out<=
clk_control_n when '1',
'0' when others;
ram_data_out<=data_other_in;
--------------------dqs/dq-read----------------------
data_other_out<=ram_data_in;
DQS_FLAG:process(clk_data,pll_lock)
begin
if clk_data'event and clk_data='1' and pll_lock='1' then
if state=rd then
if udqs_last='0' and udqs_last_last/='0' then
rd_ready_s_2<='1';
else
rd_ready_s_2<=rd_ready_s_2;
end if;
elsif rd_ready_s_1='0' then
rd_ready_s_2<='0';
else
rd_ready_s_2<=rd_ready_s_2;
end if;
udqs_last<=udqs_in;
udqs_last_last<=udqs_last;
end if;
end process;
end ddr2_con;
| mit | ac641687f1d83be34866854f7a425201 | 0.507716 | 2.949471 | false | false | false | false |
astoria-d/super-duper-nes | duper_cartridge/synchronizer.vhd | 1 | 3,627 | library ieee;
use ieee.std_logic_1164.all;
entity synchronizer is
port (
pi_rst_n : in std_logic;
pi_base_clk : in std_logic;
pi_async_input : in std_logic;
po_sync_output : out std_logic
);
end synchronizer;
architecture rtl of synchronizer is
begin
--for metastability, synchronize with two stages intermediate FF.
sync_p : process (pi_rst_n, pi_base_clk)
variable reg_temp : std_logic_vector(2 downto 0);
begin
if (pi_rst_n = '0') then
reg_temp := (others => '0');
elsif (rising_edge(pi_base_clk)) then
--shift two stage register.
reg_temp := pi_async_input & reg_temp(2 downto 1);
po_sync_output <= reg_temp(0);
end if;--if (pi_rst_n = '0') then
end process;
end rtl;
----------------------------------------------
----------------------------------------------
----------------------------------------------
----------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity synchronized_vector is
generic (abus_size : integer := 8);
port (
pi_rst_n : in std_logic;
pi_base_clk : in std_logic;
pi_async_input : in std_logic_vector(abus_size - 1 downto 0);
po_sync_output : out std_logic_vector(abus_size - 1 downto 0)
);
end synchronized_vector;
architecture rtl of synchronized_vector is
subtype TMP_REG_T is std_logic_vector (2 downto 0);
type TMP_REG_ARRAY_T is array (0 to abus_size - 1) of TMP_REG_T;
begin
sync_p : process (pi_rst_n, pi_base_clk)
variable reg_temp : TMP_REG_ARRAY_T;
begin
if (pi_rst_n = '0') then
for i in 0 to abus_size -1 loop
reg_temp(i) := (others => '0');
end loop;
elsif (rising_edge(pi_base_clk)) then
for i in 0 to abus_size -1 loop
--shift two stage register.
reg_temp(i) := pi_async_input(i) & reg_temp(i)(2 downto 1);
po_sync_output(i) <= reg_temp(i)(0);
end loop;
end if;--if (pi_rst_n = '0') then
end process;
end rtl;
----------------------------------------------
----------------------------------------------
----------------------------------------------
----------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity edge_detecter is
port (
pi_rst_n : in std_logic;
pi_base_clk : in std_logic;
pi_input : in std_logic;
po_rise : out std_logic;
po_fall : out std_logic
);
end edge_detecter;
architecture rtl of edge_detecter is
begin
detect_p : process (pi_rst_n, pi_base_clk)
variable reg_temp : std_logic;
begin
if (pi_rst_n = '0') then
reg_temp := '0';
po_rise <= '0';
po_fall <= '0';
elsif (rising_edge(pi_base_clk)) then
if (reg_temp /= pi_input) then
if (pi_input = '1') then
po_rise <= '1';
po_fall <= '0';
else
po_rise <= '0';
po_fall <= '1';
end if;
else
po_rise <= '0';
po_fall <= '0';
end if;
reg_temp := pi_input;
end if;--if (pi_rst_n = '0') then
end process;
end rtl; | apache-2.0 | 39312bae36119c8b1247d8afad8ef526 | 0.433692 | 3.782065 | false | false | false | false |
elionne/easy_bitcoin_wallet | enum_pwgen.vhdl | 1 | 2,535 | library IEEE;
use ieee.std_logic_1164.all;
entity pw_process is
port (
--length : in natural;
clk : in std_logic;
pwd : out string
);
end pw_process;
architecture arch_pw_process of pw_process is
component pwd_string
port (
push_pop : in std_logic;
char : in character;
clk : in std_logic;
enable: in std_logic;
pwd : out string
);
end component;
component recursive_stack
port (
length_in : in natural;
length_out : out natural;
index_in : in natural;
index_out : out natural;
enable : in std_logic;
push_pop: in std_logic;
clk : in std_logic
);
end component;
component vowels
port (
length_in : in natural;
length_out : out natural;
enable : in STD_LOGIC;
reset : in std_logic;
load_index : in natural;
current_index: out natural;
clk : in std_logic;
data : out character;
valid : out std_logic := '0'
);
end component;
type DenyFlags is (F_CONSONANT, F_VOWEL, F_DIPTHONG, F_NOT_FIRST, F_DIGIT, F_FIRST, F_UPPERS);
--
signal valid : std_logic;
signal char : character;
signal length, length_addr : natural := 0;
signal load_index, current_index : natural := 0;
signal next_char : std_logic;
signal stack_register : std_logic := '0';
begin
final_pwd : pwd_string port map (
push_pop => valid,
char => char,
clk => clk,
enable => '1',
pwd => pwd
);
stack : recursive_stack port map (
enable => stack_register,
push_pop => next_char,
length_in => length_addr,
length_out => length,
index_in => current_index,
index_out => load_index,
clk => clk
);
vowel : vowels port map (
length_in => length,
length_out => length_addr,
enable => '1',
reset => next_char,
load_index => load_index,
current_index => current_index,
clk => clk,
data => char,
valid => valid
);
process(clk)
begin
if rising_edge(clk) then
if valid = '1' and length_addr < 4 then
next_char <= '1';
else
next_char <= '0';
end if;
if length_addr >= 4 and valid = '1' then
stack_register <= '0';
else
stack_register <= '1';
end if;
end if;
end process;
end arch_pw_process;
| mit | 2428eae7e91a7bf2cd70ffb754b7c4ef | 0.525444 | 3.647482 | false | false | false | false |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/gcd/gcd.cache/ip/2018.2/48a4617453e14a7a/gcd_block_design_gcd_0_0_sim_netlist.vhdl | 1 | 128,679 | -- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Tue Sep 17 15:49:30 2019
-- Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ gcd_block_design_gcd_0_0_sim_netlist.vhdl
-- Design : gcd_block_design_gcd_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd_gcd_bus_s_axi is
port (
\out\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_gcd_bus_RVALID : out STD_LOGIC_VECTOR ( 1 downto 0 );
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
interrupt : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 1 downto 0 );
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\b_read_reg_102_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
\a_read_reg_107_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_gcd_bus_RDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
ap_clk : in STD_LOGIC;
s_axi_gcd_bus_ARVALID : in STD_LOGIC;
s_axi_gcd_bus_RREADY : in STD_LOGIC;
s_axi_gcd_bus_AWVALID : in STD_LOGIC;
s_axi_gcd_bus_WVALID : in STD_LOGIC;
s_axi_gcd_bus_WDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_gcd_bus_WSTRB : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_gcd_bus_BREADY : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\result_reg_56_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
\p_s_reg_45_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_gcd_bus_ARADDR : in STD_LOGIC_VECTOR ( 5 downto 0 );
ap_rst_n : in STD_LOGIC;
s_axi_gcd_bus_AWADDR : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd_gcd_bus_s_axi;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd_gcd_bus_s_axi is
signal \^co\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \FSM_onehot_rstate[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_rstate[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_rstate_reg_n_0_[0]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \FSM_onehot_rstate_reg_n_0_[0]\ : signal is "yes";
signal \FSM_onehot_wstate[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_wstate[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_wstate[3]_i_2_n_0\ : STD_LOGIC;
signal \FSM_onehot_wstate_reg_n_0_[0]\ : STD_LOGIC;
attribute RTL_KEEP of \FSM_onehot_wstate_reg_n_0_[0]\ : signal is "yes";
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^a_read_reg_107_reg[15]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ar_hs : STD_LOGIC;
signal \^b_read_reg_102_reg[15]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal int_a0 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \int_a[15]_i_1_n_0\ : STD_LOGIC;
signal \int_a[15]_i_3_n_0\ : STD_LOGIC;
signal int_ap_done : STD_LOGIC;
signal int_ap_done1 : STD_LOGIC;
signal int_ap_done_i_1_n_0 : STD_LOGIC;
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_start3_out : STD_LOGIC;
signal int_ap_start_i_10_n_0 : STD_LOGIC;
signal int_ap_start_i_1_n_0 : STD_LOGIC;
signal int_ap_start_i_5_n_0 : STD_LOGIC;
signal int_ap_start_i_6_n_0 : STD_LOGIC;
signal int_ap_start_i_7_n_0 : STD_LOGIC;
signal int_ap_start_i_8_n_0 : STD_LOGIC;
signal int_ap_start_i_9_n_0 : STD_LOGIC;
signal int_ap_start_reg_i_2_n_3 : STD_LOGIC;
signal int_ap_start_reg_i_4_n_0 : STD_LOGIC;
signal int_ap_start_reg_i_4_n_1 : STD_LOGIC;
signal int_ap_start_reg_i_4_n_2 : STD_LOGIC;
signal int_ap_start_reg_i_4_n_3 : STD_LOGIC;
signal int_auto_restart : STD_LOGIC;
signal int_auto_restart_i_1_n_0 : STD_LOGIC;
signal int_b0 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \int_b[15]_i_1_n_0\ : STD_LOGIC;
signal int_gie_i_1_n_0 : STD_LOGIC;
signal int_gie_reg_n_0 : STD_LOGIC;
signal \int_ier[0]_i_1_n_0\ : STD_LOGIC;
signal \int_ier[1]_i_1_n_0\ : STD_LOGIC;
signal \int_ier[1]_i_2_n_0\ : STD_LOGIC;
signal \int_ier_reg_n_0_[0]\ : STD_LOGIC;
signal \int_ier_reg_n_0_[1]\ : STD_LOGIC;
signal int_isr6_out : STD_LOGIC;
signal \int_isr[0]_i_1_n_0\ : STD_LOGIC;
signal \int_isr[1]_i_1_n_0\ : STD_LOGIC;
signal \int_isr_reg_n_0_[0]\ : STD_LOGIC;
signal int_pResult : STD_LOGIC_VECTOR ( 15 downto 0 );
signal int_pResult_ap_vld : STD_LOGIC;
signal int_pResult_ap_vld1 : STD_LOGIC;
signal int_pResult_ap_vld_i_1_n_0 : STD_LOGIC;
signal \^out\ : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute RTL_KEEP of \^out\ : signal is "yes";
signal p_1_in : STD_LOGIC;
signal \rdata[0]_i_1_n_0\ : STD_LOGIC;
signal \rdata[0]_i_2_n_0\ : STD_LOGIC;
signal \rdata[0]_i_3_n_0\ : STD_LOGIC;
signal \rdata[0]_i_4_n_0\ : STD_LOGIC;
signal \rdata[10]_i_1_n_0\ : STD_LOGIC;
signal \rdata[11]_i_1_n_0\ : STD_LOGIC;
signal \rdata[12]_i_1_n_0\ : STD_LOGIC;
signal \rdata[13]_i_1_n_0\ : STD_LOGIC;
signal \rdata[14]_i_1_n_0\ : STD_LOGIC;
signal \rdata[15]_i_1_n_0\ : STD_LOGIC;
signal \rdata[15]_i_3_n_0\ : STD_LOGIC;
signal \rdata[1]_i_1_n_0\ : STD_LOGIC;
signal \rdata[1]_i_2_n_0\ : STD_LOGIC;
signal \rdata[1]_i_3_n_0\ : STD_LOGIC;
signal \rdata[1]_i_4_n_0\ : STD_LOGIC;
signal \rdata[1]_i_5_n_0\ : STD_LOGIC;
signal \rdata[2]_i_1_n_0\ : STD_LOGIC;
signal \rdata[2]_i_2_n_0\ : STD_LOGIC;
signal \rdata[3]_i_1_n_0\ : STD_LOGIC;
signal \rdata[3]_i_2_n_0\ : STD_LOGIC;
signal \rdata[4]_i_1_n_0\ : STD_LOGIC;
signal \rdata[5]_i_1_n_0\ : STD_LOGIC;
signal \rdata[6]_i_1_n_0\ : STD_LOGIC;
signal \rdata[7]_i_1_n_0\ : STD_LOGIC;
signal \rdata[7]_i_2_n_0\ : STD_LOGIC;
signal \rdata[8]_i_1_n_0\ : STD_LOGIC;
signal \rdata[9]_i_1_n_0\ : STD_LOGIC;
signal \^s_axi_gcd_bus_rdata\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \^s_axi_gcd_bus_rvalid\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \^s_axi_gcd_bus_rvalid\ : signal is "yes";
signal waddr : STD_LOGIC;
signal \waddr_reg_n_0_[0]\ : STD_LOGIC;
signal \waddr_reg_n_0_[1]\ : STD_LOGIC;
signal \waddr_reg_n_0_[2]\ : STD_LOGIC;
signal \waddr_reg_n_0_[3]\ : STD_LOGIC;
signal \waddr_reg_n_0_[4]\ : STD_LOGIC;
signal \waddr_reg_n_0_[5]\ : STD_LOGIC;
signal NLW_int_ap_start_reg_i_2_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
signal NLW_int_ap_start_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_int_ap_start_reg_i_4_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute FSM_ENCODED_STATES : string;
attribute FSM_ENCODED_STATES of \FSM_onehot_rstate_reg[0]\ : label is "RDIDLE:010,RDDATA:100,iSTATE:001";
attribute KEEP : string;
attribute KEEP of \FSM_onehot_rstate_reg[0]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_rstate_reg[1]\ : label is "RDIDLE:010,RDDATA:100,iSTATE:001";
attribute KEEP of \FSM_onehot_rstate_reg[1]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_rstate_reg[2]\ : label is "RDIDLE:010,RDDATA:100,iSTATE:001";
attribute KEEP of \FSM_onehot_rstate_reg[2]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_wstate_reg[0]\ : label is "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001";
attribute KEEP of \FSM_onehot_wstate_reg[0]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_wstate_reg[1]\ : label is "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001";
attribute KEEP of \FSM_onehot_wstate_reg[1]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_wstate_reg[2]\ : label is "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001";
attribute KEEP of \FSM_onehot_wstate_reg[2]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_wstate_reg[3]\ : label is "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001";
attribute KEEP of \FSM_onehot_wstate_reg[3]\ : label is "yes";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \ap_CS_fsm[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \int_a[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \int_a[10]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \int_a[11]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \int_a[12]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \int_a[13]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \int_a[14]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \int_a[15]_i_2\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \int_a[1]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \int_a[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \int_a[3]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \int_a[4]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \int_a[5]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \int_a[6]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \int_a[7]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \int_a[8]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \int_a[9]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of int_ap_idle_i_1 : label is "soft_lutpair1";
attribute SOFT_HLUTNM of int_ap_start_i_3 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \int_b[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \int_b[10]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \int_b[11]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \int_b[12]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \int_b[13]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \int_b[14]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \int_b[15]_i_2\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \int_b[1]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \int_b[2]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \int_b[3]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \int_b[4]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \int_b[5]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \int_b[6]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \int_b[7]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \int_b[8]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \int_b[9]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \int_isr[0]_i_2\ : label is "soft_lutpair0";
begin
CO(0) <= \^co\(0);
SR(0) <= \^sr\(0);
\a_read_reg_107_reg[15]\(15 downto 0) <= \^a_read_reg_107_reg[15]\(15 downto 0);
\b_read_reg_102_reg[15]\(15 downto 0) <= \^b_read_reg_102_reg[15]\(15 downto 0);
\out\(2 downto 0) <= \^out\(2 downto 0);
s_axi_gcd_bus_RDATA(15 downto 0) <= \^s_axi_gcd_bus_rdata\(15 downto 0);
s_axi_gcd_bus_RVALID(1 downto 0) <= \^s_axi_gcd_bus_rvalid\(1 downto 0);
\FSM_onehot_rstate[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F747"
)
port map (
I0 => s_axi_gcd_bus_ARVALID,
I1 => \^s_axi_gcd_bus_rvalid\(0),
I2 => \^s_axi_gcd_bus_rvalid\(1),
I3 => s_axi_gcd_bus_RREADY,
O => \FSM_onehot_rstate[1]_i_1_n_0\
);
\FSM_onehot_rstate[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"88F8"
)
port map (
I0 => s_axi_gcd_bus_ARVALID,
I1 => \^s_axi_gcd_bus_rvalid\(0),
I2 => \^s_axi_gcd_bus_rvalid\(1),
I3 => s_axi_gcd_bus_RREADY,
O => \FSM_onehot_rstate[2]_i_1_n_0\
);
\FSM_onehot_rstate_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => ap_clk,
CE => '1',
D => '0',
Q => \FSM_onehot_rstate_reg_n_0_[0]\,
S => \^sr\(0)
);
\FSM_onehot_rstate_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \FSM_onehot_rstate[1]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rvalid\(0),
R => \^sr\(0)
);
\FSM_onehot_rstate_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \FSM_onehot_rstate[2]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rvalid\(1),
R => \^sr\(0)
);
\FSM_onehot_wstate[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"888BFF8B"
)
port map (
I0 => s_axi_gcd_bus_BREADY,
I1 => \^out\(2),
I2 => \^out\(1),
I3 => \^out\(0),
I4 => s_axi_gcd_bus_AWVALID,
O => \FSM_onehot_wstate[1]_i_1_n_0\
);
\FSM_onehot_wstate[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8F88"
)
port map (
I0 => s_axi_gcd_bus_AWVALID,
I1 => \^out\(0),
I2 => s_axi_gcd_bus_WVALID,
I3 => \^out\(1),
O => \FSM_onehot_wstate[2]_i_1_n_0\
);
\FSM_onehot_wstate[3]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ap_rst_n,
O => \^sr\(0)
);
\FSM_onehot_wstate[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"8F88"
)
port map (
I0 => s_axi_gcd_bus_WVALID,
I1 => \^out\(1),
I2 => s_axi_gcd_bus_BREADY,
I3 => \^out\(2),
O => \FSM_onehot_wstate[3]_i_2_n_0\
);
\FSM_onehot_wstate_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => ap_clk,
CE => '1',
D => '0',
Q => \FSM_onehot_wstate_reg_n_0_[0]\,
S => \^sr\(0)
);
\FSM_onehot_wstate_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \FSM_onehot_wstate[1]_i_1_n_0\,
Q => \^out\(0),
R => \^sr\(0)
);
\FSM_onehot_wstate_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \FSM_onehot_wstate[2]_i_1_n_0\,
Q => \^out\(1),
R => \^sr\(0)
);
\FSM_onehot_wstate_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \FSM_onehot_wstate[3]_i_2_n_0\,
Q => \^out\(2),
R => \^sr\(0)
);
\ap_CS_fsm[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FA30"
)
port map (
I0 => \^co\(0),
I1 => ap_start,
I2 => Q(0),
I3 => Q(2),
O => D(0)
);
\ap_CS_fsm[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00001000"
)
port map (
I0 => Q(1),
I1 => Q(3),
I2 => Q(0),
I3 => ap_start,
I4 => Q(2),
O => D(1)
);
\b_read_reg_102[15]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => Q(0),
I1 => ap_start,
O => E(0)
);
\int_a[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(0),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^a_read_reg_107_reg[15]\(0),
O => int_a0(0)
);
\int_a[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(10),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^a_read_reg_107_reg[15]\(10),
O => int_a0(10)
);
\int_a[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(11),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^a_read_reg_107_reg[15]\(11),
O => int_a0(11)
);
\int_a[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(12),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^a_read_reg_107_reg[15]\(12),
O => int_a0(12)
);
\int_a[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(13),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^a_read_reg_107_reg[15]\(13),
O => int_a0(13)
);
\int_a[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(14),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^a_read_reg_107_reg[15]\(14),
O => int_a0(14)
);
\int_a[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0008"
)
port map (
I0 => \waddr_reg_n_0_[4]\,
I1 => \int_a[15]_i_3_n_0\,
I2 => \waddr_reg_n_0_[2]\,
I3 => \waddr_reg_n_0_[3]\,
O => \int_a[15]_i_1_n_0\
);
\int_a[15]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(15),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^a_read_reg_107_reg[15]\(15),
O => int_a0(15)
);
\int_a[15]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00001000"
)
port map (
I0 => \waddr_reg_n_0_[0]\,
I1 => \waddr_reg_n_0_[5]\,
I2 => \^out\(1),
I3 => s_axi_gcd_bus_WVALID,
I4 => \waddr_reg_n_0_[1]\,
O => \int_a[15]_i_3_n_0\
);
\int_a[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(1),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^a_read_reg_107_reg[15]\(1),
O => int_a0(1)
);
\int_a[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(2),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^a_read_reg_107_reg[15]\(2),
O => int_a0(2)
);
\int_a[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(3),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^a_read_reg_107_reg[15]\(3),
O => int_a0(3)
);
\int_a[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(4),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^a_read_reg_107_reg[15]\(4),
O => int_a0(4)
);
\int_a[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(5),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^a_read_reg_107_reg[15]\(5),
O => int_a0(5)
);
\int_a[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(6),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^a_read_reg_107_reg[15]\(6),
O => int_a0(6)
);
\int_a[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(7),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^a_read_reg_107_reg[15]\(7),
O => int_a0(7)
);
\int_a[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(8),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^a_read_reg_107_reg[15]\(8),
O => int_a0(8)
);
\int_a[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(9),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^a_read_reg_107_reg[15]\(9),
O => int_a0(9)
);
\int_a_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(0),
Q => \^a_read_reg_107_reg[15]\(0),
R => \^sr\(0)
);
\int_a_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(10),
Q => \^a_read_reg_107_reg[15]\(10),
R => \^sr\(0)
);
\int_a_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(11),
Q => \^a_read_reg_107_reg[15]\(11),
R => \^sr\(0)
);
\int_a_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(12),
Q => \^a_read_reg_107_reg[15]\(12),
R => \^sr\(0)
);
\int_a_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(13),
Q => \^a_read_reg_107_reg[15]\(13),
R => \^sr\(0)
);
\int_a_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(14),
Q => \^a_read_reg_107_reg[15]\(14),
R => \^sr\(0)
);
\int_a_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(15),
Q => \^a_read_reg_107_reg[15]\(15),
R => \^sr\(0)
);
\int_a_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(1),
Q => \^a_read_reg_107_reg[15]\(1),
R => \^sr\(0)
);
\int_a_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(2),
Q => \^a_read_reg_107_reg[15]\(2),
R => \^sr\(0)
);
\int_a_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(3),
Q => \^a_read_reg_107_reg[15]\(3),
R => \^sr\(0)
);
\int_a_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(4),
Q => \^a_read_reg_107_reg[15]\(4),
R => \^sr\(0)
);
\int_a_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(5),
Q => \^a_read_reg_107_reg[15]\(5),
R => \^sr\(0)
);
\int_a_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(6),
Q => \^a_read_reg_107_reg[15]\(6),
R => \^sr\(0)
);
\int_a_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(7),
Q => \^a_read_reg_107_reg[15]\(7),
R => \^sr\(0)
);
\int_a_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(8),
Q => \^a_read_reg_107_reg[15]\(8),
R => \^sr\(0)
);
\int_a_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(9),
Q => \^a_read_reg_107_reg[15]\(9),
R => \^sr\(0)
);
int_ap_done_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"8FFFFFFF88888888"
)
port map (
I0 => Q(2),
I1 => \^co\(0),
I2 => \^s_axi_gcd_bus_rvalid\(0),
I3 => s_axi_gcd_bus_ARVALID,
I4 => int_ap_done1,
I5 => int_ap_done,
O => int_ap_done_i_1_n_0
);
int_ap_done_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => s_axi_gcd_bus_ARADDR(5),
I1 => s_axi_gcd_bus_ARADDR(4),
I2 => s_axi_gcd_bus_ARADDR(1),
I3 => s_axi_gcd_bus_ARADDR(0),
I4 => s_axi_gcd_bus_ARADDR(3),
I5 => s_axi_gcd_bus_ARADDR(2),
O => int_ap_done1
);
int_ap_done_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => int_ap_done_i_1_n_0,
Q => int_ap_done,
R => \^sr\(0)
);
int_ap_idle_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => Q(0),
I1 => ap_start,
O => ap_idle
);
int_ap_idle_reg: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => '1',
D => ap_idle,
Q => int_ap_idle,
R => \^sr\(0)
);
int_ap_ready_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^co\(0),
I1 => Q(2),
O => ap_done
);
int_ap_ready_reg: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => '1',
D => ap_done,
Q => int_ap_ready,
R => \^sr\(0)
);
int_ap_start_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FFBFFF80"
)
port map (
I0 => int_auto_restart,
I1 => Q(2),
I2 => \^co\(0),
I3 => int_ap_start3_out,
I4 => ap_start,
O => int_ap_start_i_1_n_0
);
int_ap_start_i_10: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \result_reg_56_reg[15]\(0),
I1 => \p_s_reg_45_reg[15]\(0),
I2 => \p_s_reg_45_reg[15]\(2),
I3 => \result_reg_56_reg[15]\(2),
I4 => \p_s_reg_45_reg[15]\(1),
I5 => \result_reg_56_reg[15]\(1),
O => int_ap_start_i_10_n_0
);
int_ap_start_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"00000800"
)
port map (
I0 => s_axi_gcd_bus_WDATA(0),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \waddr_reg_n_0_[2]\,
I3 => \int_ier[1]_i_2_n_0\,
I4 => \waddr_reg_n_0_[3]\,
O => int_ap_start3_out
);
int_ap_start_i_5: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \p_s_reg_45_reg[15]\(15),
I1 => \result_reg_56_reg[15]\(15),
O => int_ap_start_i_5_n_0
);
int_ap_start_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \result_reg_56_reg[15]\(12),
I1 => \p_s_reg_45_reg[15]\(12),
I2 => \p_s_reg_45_reg[15]\(14),
I3 => \result_reg_56_reg[15]\(14),
I4 => \p_s_reg_45_reg[15]\(13),
I5 => \result_reg_56_reg[15]\(13),
O => int_ap_start_i_6_n_0
);
int_ap_start_i_7: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \result_reg_56_reg[15]\(9),
I1 => \p_s_reg_45_reg[15]\(9),
I2 => \p_s_reg_45_reg[15]\(11),
I3 => \result_reg_56_reg[15]\(11),
I4 => \p_s_reg_45_reg[15]\(10),
I5 => \result_reg_56_reg[15]\(10),
O => int_ap_start_i_7_n_0
);
int_ap_start_i_8: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \result_reg_56_reg[15]\(6),
I1 => \p_s_reg_45_reg[15]\(6),
I2 => \p_s_reg_45_reg[15]\(8),
I3 => \result_reg_56_reg[15]\(8),
I4 => \p_s_reg_45_reg[15]\(7),
I5 => \result_reg_56_reg[15]\(7),
O => int_ap_start_i_8_n_0
);
int_ap_start_i_9: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \result_reg_56_reg[15]\(3),
I1 => \p_s_reg_45_reg[15]\(3),
I2 => \p_s_reg_45_reg[15]\(5),
I3 => \result_reg_56_reg[15]\(5),
I4 => \p_s_reg_45_reg[15]\(4),
I5 => \result_reg_56_reg[15]\(4),
O => int_ap_start_i_9_n_0
);
int_ap_start_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => int_ap_start_i_1_n_0,
Q => ap_start,
R => \^sr\(0)
);
int_ap_start_reg_i_2: unisim.vcomponents.CARRY4
port map (
CI => int_ap_start_reg_i_4_n_0,
CO(3 downto 2) => NLW_int_ap_start_reg_i_2_CO_UNCONNECTED(3 downto 2),
CO(1) => \^co\(0),
CO(0) => int_ap_start_reg_i_2_n_3,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_int_ap_start_reg_i_2_O_UNCONNECTED(3 downto 0),
S(3 downto 2) => B"00",
S(1) => int_ap_start_i_5_n_0,
S(0) => int_ap_start_i_6_n_0
);
int_ap_start_reg_i_4: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => int_ap_start_reg_i_4_n_0,
CO(2) => int_ap_start_reg_i_4_n_1,
CO(1) => int_ap_start_reg_i_4_n_2,
CO(0) => int_ap_start_reg_i_4_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_int_ap_start_reg_i_4_O_UNCONNECTED(3 downto 0),
S(3) => int_ap_start_i_7_n_0,
S(2) => int_ap_start_i_8_n_0,
S(1) => int_ap_start_i_9_n_0,
S(0) => int_ap_start_i_10_n_0
);
int_auto_restart_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => s_axi_gcd_bus_WDATA(7),
I1 => \waddr_reg_n_0_[3]\,
I2 => \int_ier[1]_i_2_n_0\,
I3 => \waddr_reg_n_0_[2]\,
I4 => s_axi_gcd_bus_WSTRB(0),
I5 => int_auto_restart,
O => int_auto_restart_i_1_n_0
);
int_auto_restart_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => int_auto_restart_i_1_n_0,
Q => int_auto_restart,
R => \^sr\(0)
);
\int_b[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(0),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^b_read_reg_102_reg[15]\(0),
O => int_b0(0)
);
\int_b[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(10),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^b_read_reg_102_reg[15]\(10),
O => int_b0(10)
);
\int_b[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(11),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^b_read_reg_102_reg[15]\(11),
O => int_b0(11)
);
\int_b[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(12),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^b_read_reg_102_reg[15]\(12),
O => int_b0(12)
);
\int_b[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(13),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^b_read_reg_102_reg[15]\(13),
O => int_b0(13)
);
\int_b[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(14),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^b_read_reg_102_reg[15]\(14),
O => int_b0(14)
);
\int_b[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \waddr_reg_n_0_[3]\,
I1 => \waddr_reg_n_0_[4]\,
I2 => \int_a[15]_i_3_n_0\,
I3 => \waddr_reg_n_0_[2]\,
O => \int_b[15]_i_1_n_0\
);
\int_b[15]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(15),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^b_read_reg_102_reg[15]\(15),
O => int_b0(15)
);
\int_b[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(1),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^b_read_reg_102_reg[15]\(1),
O => int_b0(1)
);
\int_b[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(2),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^b_read_reg_102_reg[15]\(2),
O => int_b0(2)
);
\int_b[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(3),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^b_read_reg_102_reg[15]\(3),
O => int_b0(3)
);
\int_b[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(4),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^b_read_reg_102_reg[15]\(4),
O => int_b0(4)
);
\int_b[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(5),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^b_read_reg_102_reg[15]\(5),
O => int_b0(5)
);
\int_b[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(6),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^b_read_reg_102_reg[15]\(6),
O => int_b0(6)
);
\int_b[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(7),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^b_read_reg_102_reg[15]\(7),
O => int_b0(7)
);
\int_b[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(8),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^b_read_reg_102_reg[15]\(8),
O => int_b0(8)
);
\int_b[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(9),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^b_read_reg_102_reg[15]\(9),
O => int_b0(9)
);
\int_b_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(0),
Q => \^b_read_reg_102_reg[15]\(0),
R => \^sr\(0)
);
\int_b_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(10),
Q => \^b_read_reg_102_reg[15]\(10),
R => \^sr\(0)
);
\int_b_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(11),
Q => \^b_read_reg_102_reg[15]\(11),
R => \^sr\(0)
);
\int_b_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(12),
Q => \^b_read_reg_102_reg[15]\(12),
R => \^sr\(0)
);
\int_b_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(13),
Q => \^b_read_reg_102_reg[15]\(13),
R => \^sr\(0)
);
\int_b_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(14),
Q => \^b_read_reg_102_reg[15]\(14),
R => \^sr\(0)
);
\int_b_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(15),
Q => \^b_read_reg_102_reg[15]\(15),
R => \^sr\(0)
);
\int_b_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(1),
Q => \^b_read_reg_102_reg[15]\(1),
R => \^sr\(0)
);
\int_b_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(2),
Q => \^b_read_reg_102_reg[15]\(2),
R => \^sr\(0)
);
\int_b_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(3),
Q => \^b_read_reg_102_reg[15]\(3),
R => \^sr\(0)
);
\int_b_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(4),
Q => \^b_read_reg_102_reg[15]\(4),
R => \^sr\(0)
);
\int_b_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(5),
Q => \^b_read_reg_102_reg[15]\(5),
R => \^sr\(0)
);
\int_b_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(6),
Q => \^b_read_reg_102_reg[15]\(6),
R => \^sr\(0)
);
\int_b_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(7),
Q => \^b_read_reg_102_reg[15]\(7),
R => \^sr\(0)
);
\int_b_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(8),
Q => \^b_read_reg_102_reg[15]\(8),
R => \^sr\(0)
);
\int_b_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(9),
Q => \^b_read_reg_102_reg[15]\(9),
R => \^sr\(0)
);
int_gie_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFFFFFF08000000"
)
port map (
I0 => s_axi_gcd_bus_WDATA(0),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \waddr_reg_n_0_[3]\,
I3 => \waddr_reg_n_0_[2]\,
I4 => \int_ier[1]_i_2_n_0\,
I5 => int_gie_reg_n_0,
O => int_gie_i_1_n_0
);
int_gie_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => int_gie_i_1_n_0,
Q => int_gie_reg_n_0,
R => \^sr\(0)
);
\int_ier[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFFFFF00800000"
)
port map (
I0 => s_axi_gcd_bus_WDATA(0),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \int_ier[1]_i_2_n_0\,
I3 => \waddr_reg_n_0_[2]\,
I4 => \waddr_reg_n_0_[3]\,
I5 => \int_ier_reg_n_0_[0]\,
O => \int_ier[0]_i_1_n_0\
);
\int_ier[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFFFFF00800000"
)
port map (
I0 => s_axi_gcd_bus_WDATA(1),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \int_ier[1]_i_2_n_0\,
I3 => \waddr_reg_n_0_[2]\,
I4 => \waddr_reg_n_0_[3]\,
I5 => \int_ier_reg_n_0_[1]\,
O => \int_ier[1]_i_1_n_0\
);
\int_ier[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000040"
)
port map (
I0 => \waddr_reg_n_0_[1]\,
I1 => s_axi_gcd_bus_WVALID,
I2 => \^out\(1),
I3 => \waddr_reg_n_0_[5]\,
I4 => \waddr_reg_n_0_[0]\,
I5 => \waddr_reg_n_0_[4]\,
O => \int_ier[1]_i_2_n_0\
);
\int_ier_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \int_ier[0]_i_1_n_0\,
Q => \int_ier_reg_n_0_[0]\,
R => \^sr\(0)
);
\int_ier_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \int_ier[1]_i_1_n_0\,
Q => \int_ier_reg_n_0_[1]\,
R => \^sr\(0)
);
\int_isr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F7777777F8888888"
)
port map (
I0 => s_axi_gcd_bus_WDATA(0),
I1 => int_isr6_out,
I2 => \int_ier_reg_n_0_[0]\,
I3 => \^co\(0),
I4 => Q(2),
I5 => \int_isr_reg_n_0_[0]\,
O => \int_isr[0]_i_1_n_0\
);
\int_isr[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => s_axi_gcd_bus_WSTRB(0),
I1 => \waddr_reg_n_0_[2]\,
I2 => \int_ier[1]_i_2_n_0\,
I3 => \waddr_reg_n_0_[3]\,
O => int_isr6_out
);
\int_isr[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F7777777F8888888"
)
port map (
I0 => s_axi_gcd_bus_WDATA(1),
I1 => int_isr6_out,
I2 => \int_ier_reg_n_0_[1]\,
I3 => \^co\(0),
I4 => Q(2),
I5 => p_1_in,
O => \int_isr[1]_i_1_n_0\
);
\int_isr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \int_isr[0]_i_1_n_0\,
Q => \int_isr_reg_n_0_[0]\,
R => \^sr\(0)
);
\int_isr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \int_isr[1]_i_1_n_0\,
Q => p_1_in,
R => \^sr\(0)
);
int_pResult_ap_vld_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"8FFFFFFF88888888"
)
port map (
I0 => Q(2),
I1 => \^co\(0),
I2 => \^s_axi_gcd_bus_rvalid\(0),
I3 => s_axi_gcd_bus_ARVALID,
I4 => int_pResult_ap_vld1,
I5 => int_pResult_ap_vld,
O => int_pResult_ap_vld_i_1_n_0
);
int_pResult_ap_vld_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000001000"
)
port map (
I0 => s_axi_gcd_bus_ARADDR(1),
I1 => s_axi_gcd_bus_ARADDR(4),
I2 => s_axi_gcd_bus_ARADDR(5),
I3 => s_axi_gcd_bus_ARADDR(2),
I4 => s_axi_gcd_bus_ARADDR(3),
I5 => s_axi_gcd_bus_ARADDR(0),
O => int_pResult_ap_vld1
);
int_pResult_ap_vld_reg: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => '1',
D => int_pResult_ap_vld_i_1_n_0,
Q => int_pResult_ap_vld,
R => \^sr\(0)
);
\int_pResult_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(0),
Q => int_pResult(0),
R => \^sr\(0)
);
\int_pResult_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(10),
Q => int_pResult(10),
R => \^sr\(0)
);
\int_pResult_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(11),
Q => int_pResult(11),
R => \^sr\(0)
);
\int_pResult_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(12),
Q => int_pResult(12),
R => \^sr\(0)
);
\int_pResult_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(13),
Q => int_pResult(13),
R => \^sr\(0)
);
\int_pResult_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(14),
Q => int_pResult(14),
R => \^sr\(0)
);
\int_pResult_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(15),
Q => int_pResult(15),
R => \^sr\(0)
);
\int_pResult_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(1),
Q => int_pResult(1),
R => \^sr\(0)
);
\int_pResult_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(2),
Q => int_pResult(2),
R => \^sr\(0)
);
\int_pResult_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(3),
Q => int_pResult(3),
R => \^sr\(0)
);
\int_pResult_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(4),
Q => int_pResult(4),
R => \^sr\(0)
);
\int_pResult_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(5),
Q => int_pResult(5),
R => \^sr\(0)
);
\int_pResult_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(6),
Q => int_pResult(6),
R => \^sr\(0)
);
\int_pResult_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(7),
Q => int_pResult(7),
R => \^sr\(0)
);
\int_pResult_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(8),
Q => int_pResult(8),
R => \^sr\(0)
);
\int_pResult_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(9),
Q => int_pResult(9),
R => \^sr\(0)
);
interrupt_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"E0"
)
port map (
I0 => p_1_in,
I1 => \int_isr_reg_n_0_[0]\,
I2 => int_gie_reg_n_0,
O => interrupt
);
\rdata[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00E2FFFF00E20000"
)
port map (
I0 => \rdata[0]_i_2_n_0\,
I1 => s_axi_gcd_bus_ARADDR(2),
I2 => \rdata[0]_i_3_n_0\,
I3 => \rdata[1]_i_4_n_0\,
I4 => ar_hs,
I5 => \^s_axi_gcd_bus_rdata\(0),
O => \rdata[0]_i_1_n_0\
);
\rdata[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00E2FFFF00E20000"
)
port map (
I0 => \int_ier_reg_n_0_[0]\,
I1 => s_axi_gcd_bus_ARADDR(4),
I2 => \^b_read_reg_102_reg[15]\(0),
I3 => s_axi_gcd_bus_ARADDR(5),
I4 => s_axi_gcd_bus_ARADDR(3),
I5 => \rdata[0]_i_4_n_0\,
O => \rdata[0]_i_2_n_0\
);
\rdata[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0033223000002230"
)
port map (
I0 => int_pResult_ap_vld,
I1 => s_axi_gcd_bus_ARADDR(4),
I2 => int_gie_reg_n_0,
I3 => s_axi_gcd_bus_ARADDR(5),
I4 => s_axi_gcd_bus_ARADDR(3),
I5 => \int_isr_reg_n_0_[0]\,
O => \rdata[0]_i_3_n_0\
);
\rdata[0]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \^a_read_reg_107_reg[15]\(0),
I1 => s_axi_gcd_bus_ARADDR(4),
I2 => int_pResult(0),
I3 => s_axi_gcd_bus_ARADDR(5),
I4 => ap_start,
O => \rdata[0]_i_4_n_0\
);
\rdata[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0033B8000000B800"
)
port map (
I0 => \^b_read_reg_102_reg[15]\(10),
I1 => s_axi_gcd_bus_ARADDR(3),
I2 => \^a_read_reg_107_reg[15]\(10),
I3 => s_axi_gcd_bus_ARADDR(4),
I4 => s_axi_gcd_bus_ARADDR(5),
I5 => int_pResult(10),
O => \rdata[10]_i_1_n_0\
);
\rdata[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0033B8000000B800"
)
port map (
I0 => \^b_read_reg_102_reg[15]\(11),
I1 => s_axi_gcd_bus_ARADDR(3),
I2 => \^a_read_reg_107_reg[15]\(11),
I3 => s_axi_gcd_bus_ARADDR(4),
I4 => s_axi_gcd_bus_ARADDR(5),
I5 => int_pResult(11),
O => \rdata[11]_i_1_n_0\
);
\rdata[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0033B8000000B800"
)
port map (
I0 => \^b_read_reg_102_reg[15]\(12),
I1 => s_axi_gcd_bus_ARADDR(3),
I2 => \^a_read_reg_107_reg[15]\(12),
I3 => s_axi_gcd_bus_ARADDR(4),
I4 => s_axi_gcd_bus_ARADDR(5),
I5 => int_pResult(12),
O => \rdata[12]_i_1_n_0\
);
\rdata[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0033B8000000B800"
)
port map (
I0 => \^b_read_reg_102_reg[15]\(13),
I1 => s_axi_gcd_bus_ARADDR(3),
I2 => \^a_read_reg_107_reg[15]\(13),
I3 => s_axi_gcd_bus_ARADDR(4),
I4 => s_axi_gcd_bus_ARADDR(5),
I5 => int_pResult(13),
O => \rdata[13]_i_1_n_0\
);
\rdata[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0033B8000000B800"
)
port map (
I0 => \^b_read_reg_102_reg[15]\(14),
I1 => s_axi_gcd_bus_ARADDR(3),
I2 => \^a_read_reg_107_reg[15]\(14),
I3 => s_axi_gcd_bus_ARADDR(4),
I4 => s_axi_gcd_bus_ARADDR(5),
I5 => int_pResult(14),
O => \rdata[14]_i_1_n_0\
);
\rdata[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88888880"
)
port map (
I0 => s_axi_gcd_bus_ARVALID,
I1 => \^s_axi_gcd_bus_rvalid\(0),
I2 => s_axi_gcd_bus_ARADDR(1),
I3 => s_axi_gcd_bus_ARADDR(0),
I4 => s_axi_gcd_bus_ARADDR(2),
O => \rdata[15]_i_1_n_0\
);
\rdata[15]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^s_axi_gcd_bus_rvalid\(0),
I1 => s_axi_gcd_bus_ARVALID,
O => ar_hs
);
\rdata[15]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0033B8000000B800"
)
port map (
I0 => \^b_read_reg_102_reg[15]\(15),
I1 => s_axi_gcd_bus_ARADDR(3),
I2 => \^a_read_reg_107_reg[15]\(15),
I3 => s_axi_gcd_bus_ARADDR(4),
I4 => s_axi_gcd_bus_ARADDR(5),
I5 => int_pResult(15),
O => \rdata[15]_i_3_n_0\
);
\rdata[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00E2FFFF00E20000"
)
port map (
I0 => \rdata[1]_i_2_n_0\,
I1 => s_axi_gcd_bus_ARADDR(2),
I2 => \rdata[1]_i_3_n_0\,
I3 => \rdata[1]_i_4_n_0\,
I4 => ar_hs,
I5 => \^s_axi_gcd_bus_rdata\(1),
O => \rdata[1]_i_1_n_0\
);
\rdata[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00E2FFFF00E20000"
)
port map (
I0 => \int_ier_reg_n_0_[1]\,
I1 => s_axi_gcd_bus_ARADDR(4),
I2 => \^b_read_reg_102_reg[15]\(1),
I3 => s_axi_gcd_bus_ARADDR(5),
I4 => s_axi_gcd_bus_ARADDR(3),
I5 => \rdata[1]_i_5_n_0\,
O => \rdata[1]_i_2_n_0\
);
\rdata[1]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => s_axi_gcd_bus_ARADDR(4),
I1 => s_axi_gcd_bus_ARADDR(5),
I2 => s_axi_gcd_bus_ARADDR(3),
I3 => p_1_in,
O => \rdata[1]_i_3_n_0\
);
\rdata[1]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => s_axi_gcd_bus_ARADDR(1),
I1 => s_axi_gcd_bus_ARADDR(0),
O => \rdata[1]_i_4_n_0\
);
\rdata[1]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \^a_read_reg_107_reg[15]\(1),
I1 => s_axi_gcd_bus_ARADDR(4),
I2 => int_pResult(1),
I3 => s_axi_gcd_bus_ARADDR(5),
I4 => int_ap_done,
O => \rdata[1]_i_5_n_0\
);
\rdata[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"40FF4000"
)
port map (
I0 => s_axi_gcd_bus_ARADDR(5),
I1 => s_axi_gcd_bus_ARADDR(4),
I2 => \^b_read_reg_102_reg[15]\(2),
I3 => s_axi_gcd_bus_ARADDR(3),
I4 => \rdata[2]_i_2_n_0\,
O => \rdata[2]_i_1_n_0\
);
\rdata[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \^a_read_reg_107_reg[15]\(2),
I1 => s_axi_gcd_bus_ARADDR(4),
I2 => int_pResult(2),
I3 => s_axi_gcd_bus_ARADDR(5),
I4 => int_ap_idle,
O => \rdata[2]_i_2_n_0\
);
\rdata[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"40FF4000"
)
port map (
I0 => s_axi_gcd_bus_ARADDR(5),
I1 => s_axi_gcd_bus_ARADDR(4),
I2 => \^b_read_reg_102_reg[15]\(3),
I3 => s_axi_gcd_bus_ARADDR(3),
I4 => \rdata[3]_i_2_n_0\,
O => \rdata[3]_i_1_n_0\
);
\rdata[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \^a_read_reg_107_reg[15]\(3),
I1 => s_axi_gcd_bus_ARADDR(4),
I2 => int_pResult(3),
I3 => s_axi_gcd_bus_ARADDR(5),
I4 => int_ap_ready,
O => \rdata[3]_i_2_n_0\
);
\rdata[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0033B8000000B800"
)
port map (
I0 => \^b_read_reg_102_reg[15]\(4),
I1 => s_axi_gcd_bus_ARADDR(3),
I2 => \^a_read_reg_107_reg[15]\(4),
I3 => s_axi_gcd_bus_ARADDR(4),
I4 => s_axi_gcd_bus_ARADDR(5),
I5 => int_pResult(4),
O => \rdata[4]_i_1_n_0\
);
\rdata[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0033B8000000B800"
)
port map (
I0 => \^b_read_reg_102_reg[15]\(5),
I1 => s_axi_gcd_bus_ARADDR(3),
I2 => \^a_read_reg_107_reg[15]\(5),
I3 => s_axi_gcd_bus_ARADDR(4),
I4 => s_axi_gcd_bus_ARADDR(5),
I5 => int_pResult(5),
O => \rdata[5]_i_1_n_0\
);
\rdata[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0033B8000000B800"
)
port map (
I0 => \^b_read_reg_102_reg[15]\(6),
I1 => s_axi_gcd_bus_ARADDR(3),
I2 => \^a_read_reg_107_reg[15]\(6),
I3 => s_axi_gcd_bus_ARADDR(4),
I4 => s_axi_gcd_bus_ARADDR(5),
I5 => int_pResult(6),
O => \rdata[6]_i_1_n_0\
);
\rdata[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"40FF4000"
)
port map (
I0 => s_axi_gcd_bus_ARADDR(5),
I1 => s_axi_gcd_bus_ARADDR(4),
I2 => \^b_read_reg_102_reg[15]\(7),
I3 => s_axi_gcd_bus_ARADDR(3),
I4 => \rdata[7]_i_2_n_0\,
O => \rdata[7]_i_1_n_0\
);
\rdata[7]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \^a_read_reg_107_reg[15]\(7),
I1 => s_axi_gcd_bus_ARADDR(4),
I2 => int_pResult(7),
I3 => s_axi_gcd_bus_ARADDR(5),
I4 => int_auto_restart,
O => \rdata[7]_i_2_n_0\
);
\rdata[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0033B8000000B800"
)
port map (
I0 => \^b_read_reg_102_reg[15]\(8),
I1 => s_axi_gcd_bus_ARADDR(3),
I2 => \^a_read_reg_107_reg[15]\(8),
I3 => s_axi_gcd_bus_ARADDR(4),
I4 => s_axi_gcd_bus_ARADDR(5),
I5 => int_pResult(8),
O => \rdata[8]_i_1_n_0\
);
\rdata[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0033B8000000B800"
)
port map (
I0 => \^b_read_reg_102_reg[15]\(9),
I1 => s_axi_gcd_bus_ARADDR(3),
I2 => \^a_read_reg_107_reg[15]\(9),
I3 => s_axi_gcd_bus_ARADDR(4),
I4 => s_axi_gcd_bus_ARADDR(5),
I5 => int_pResult(9),
O => \rdata[9]_i_1_n_0\
);
\rdata_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => '1',
D => \rdata[0]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rdata\(0),
R => '0'
);
\rdata_reg[10]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[10]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rdata\(10),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[11]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[11]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rdata\(11),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[12]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[12]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rdata\(12),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[13]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[13]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rdata\(13),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[14]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[14]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rdata\(14),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[15]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[15]_i_3_n_0\,
Q => \^s_axi_gcd_bus_rdata\(15),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => '1',
D => \rdata[1]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rdata\(1),
R => '0'
);
\rdata_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[2]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rdata\(2),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[3]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[3]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rdata\(3),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[4]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[4]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rdata\(4),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[5]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[5]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rdata\(5),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[6]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[6]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rdata\(6),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[7]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[7]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rdata\(7),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[8]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[8]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rdata\(8),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[9]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[9]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rdata\(9),
R => \rdata[15]_i_1_n_0\
);
\waddr[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^out\(0),
I1 => s_axi_gcd_bus_AWVALID,
O => waddr
);
\waddr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => waddr,
D => s_axi_gcd_bus_AWADDR(0),
Q => \waddr_reg_n_0_[0]\,
R => '0'
);
\waddr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => waddr,
D => s_axi_gcd_bus_AWADDR(1),
Q => \waddr_reg_n_0_[1]\,
R => '0'
);
\waddr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => waddr,
D => s_axi_gcd_bus_AWADDR(2),
Q => \waddr_reg_n_0_[2]\,
R => '0'
);
\waddr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => waddr,
D => s_axi_gcd_bus_AWADDR(3),
Q => \waddr_reg_n_0_[3]\,
R => '0'
);
\waddr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => waddr,
D => s_axi_gcd_bus_AWADDR(4),
Q => \waddr_reg_n_0_[4]\,
R => '0'
);
\waddr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => waddr,
D => s_axi_gcd_bus_AWADDR(5),
Q => \waddr_reg_n_0_[5]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd is
port (
ap_clk : in STD_LOGIC;
ap_rst_n : in STD_LOGIC;
s_axi_gcd_bus_AWVALID : in STD_LOGIC;
s_axi_gcd_bus_AWREADY : out STD_LOGIC;
s_axi_gcd_bus_AWADDR : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_gcd_bus_WVALID : in STD_LOGIC;
s_axi_gcd_bus_WREADY : out STD_LOGIC;
s_axi_gcd_bus_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_gcd_bus_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_gcd_bus_ARVALID : in STD_LOGIC;
s_axi_gcd_bus_ARREADY : out STD_LOGIC;
s_axi_gcd_bus_ARADDR : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_gcd_bus_RVALID : out STD_LOGIC;
s_axi_gcd_bus_RREADY : in STD_LOGIC;
s_axi_gcd_bus_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_gcd_bus_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_gcd_bus_BVALID : out STD_LOGIC;
s_axi_gcd_bus_BREADY : in STD_LOGIC;
s_axi_gcd_bus_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
interrupt : out STD_LOGIC
);
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd : entity is 32;
attribute C_S_AXI_GCD_BUS_ADDR_WIDTH : integer;
attribute C_S_AXI_GCD_BUS_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd : entity is 6;
attribute C_S_AXI_GCD_BUS_DATA_WIDTH : integer;
attribute C_S_AXI_GCD_BUS_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd : entity is 32;
attribute C_S_AXI_GCD_BUS_WSTRB_WIDTH : integer;
attribute C_S_AXI_GCD_BUS_WSTRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd : entity is 4;
attribute C_S_AXI_WSTRB_WIDTH : integer;
attribute C_S_AXI_WSTRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd : entity is 4;
attribute ap_ST_fsm_state1 : string;
attribute ap_ST_fsm_state1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd : entity is "4'b0001";
attribute ap_ST_fsm_state2 : string;
attribute ap_ST_fsm_state2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd : entity is "4'b0010";
attribute ap_ST_fsm_state3 : string;
attribute ap_ST_fsm_state3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd : entity is "4'b0100";
attribute ap_ST_fsm_state4 : string;
attribute ap_ST_fsm_state4 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd : entity is "4'b1000";
attribute hls_module : string;
attribute hls_module of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd : entity is "yes";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd is
signal \<const0>\ : STD_LOGIC;
signal a : STD_LOGIC_VECTOR ( 15 downto 0 );
signal a_assign_fu_78_p21_out : STD_LOGIC_VECTOR ( 15 downto 0 );
signal a_assign_reg_121 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal a_assign_reg_1210 : STD_LOGIC;
signal \a_assign_reg_121[11]_i_2_n_0\ : STD_LOGIC;
signal \a_assign_reg_121[11]_i_3_n_0\ : STD_LOGIC;
signal \a_assign_reg_121[11]_i_4_n_0\ : STD_LOGIC;
signal \a_assign_reg_121[11]_i_5_n_0\ : STD_LOGIC;
signal \a_assign_reg_121[15]_i_2_n_0\ : STD_LOGIC;
signal \a_assign_reg_121[15]_i_3_n_0\ : STD_LOGIC;
signal \a_assign_reg_121[15]_i_4_n_0\ : STD_LOGIC;
signal \a_assign_reg_121[15]_i_5_n_0\ : STD_LOGIC;
signal \a_assign_reg_121[3]_i_2_n_0\ : STD_LOGIC;
signal \a_assign_reg_121[3]_i_3_n_0\ : STD_LOGIC;
signal \a_assign_reg_121[3]_i_4_n_0\ : STD_LOGIC;
signal \a_assign_reg_121[3]_i_5_n_0\ : STD_LOGIC;
signal \a_assign_reg_121[7]_i_2_n_0\ : STD_LOGIC;
signal \a_assign_reg_121[7]_i_3_n_0\ : STD_LOGIC;
signal \a_assign_reg_121[7]_i_4_n_0\ : STD_LOGIC;
signal \a_assign_reg_121[7]_i_5_n_0\ : STD_LOGIC;
signal \a_assign_reg_121_reg[11]_i_1_n_0\ : STD_LOGIC;
signal \a_assign_reg_121_reg[11]_i_1_n_1\ : STD_LOGIC;
signal \a_assign_reg_121_reg[11]_i_1_n_2\ : STD_LOGIC;
signal \a_assign_reg_121_reg[11]_i_1_n_3\ : STD_LOGIC;
signal \a_assign_reg_121_reg[15]_i_1_n_1\ : STD_LOGIC;
signal \a_assign_reg_121_reg[15]_i_1_n_2\ : STD_LOGIC;
signal \a_assign_reg_121_reg[15]_i_1_n_3\ : STD_LOGIC;
signal \a_assign_reg_121_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \a_assign_reg_121_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \a_assign_reg_121_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \a_assign_reg_121_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \a_assign_reg_121_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \a_assign_reg_121_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \a_assign_reg_121_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \a_assign_reg_121_reg[7]_i_1_n_3\ : STD_LOGIC;
signal a_read_reg_107 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \ap_CS_fsm_reg_n_0_[0]\ : STD_LOGIC;
signal ap_CS_fsm_state2 : STD_LOGIC;
signal ap_CS_fsm_state3 : STD_LOGIC;
signal ap_CS_fsm_state4 : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR ( 2 downto 0 );
signal ap_NS_fsm1 : STD_LOGIC;
signal ap_rst_n_inv : STD_LOGIC;
signal b : STD_LOGIC_VECTOR ( 15 downto 0 );
signal b_assign_fu_84_p20_out : STD_LOGIC_VECTOR ( 15 downto 0 );
signal b_assign_reg_126 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \b_assign_reg_126[11]_i_2_n_0\ : STD_LOGIC;
signal \b_assign_reg_126[11]_i_3_n_0\ : STD_LOGIC;
signal \b_assign_reg_126[11]_i_4_n_0\ : STD_LOGIC;
signal \b_assign_reg_126[11]_i_5_n_0\ : STD_LOGIC;
signal \b_assign_reg_126[15]_i_2_n_0\ : STD_LOGIC;
signal \b_assign_reg_126[15]_i_3_n_0\ : STD_LOGIC;
signal \b_assign_reg_126[15]_i_4_n_0\ : STD_LOGIC;
signal \b_assign_reg_126[15]_i_5_n_0\ : STD_LOGIC;
signal \b_assign_reg_126[3]_i_2_n_0\ : STD_LOGIC;
signal \b_assign_reg_126[3]_i_3_n_0\ : STD_LOGIC;
signal \b_assign_reg_126[3]_i_4_n_0\ : STD_LOGIC;
signal \b_assign_reg_126[3]_i_5_n_0\ : STD_LOGIC;
signal \b_assign_reg_126[7]_i_2_n_0\ : STD_LOGIC;
signal \b_assign_reg_126[7]_i_3_n_0\ : STD_LOGIC;
signal \b_assign_reg_126[7]_i_4_n_0\ : STD_LOGIC;
signal \b_assign_reg_126[7]_i_5_n_0\ : STD_LOGIC;
signal \b_assign_reg_126_reg[11]_i_1_n_0\ : STD_LOGIC;
signal \b_assign_reg_126_reg[11]_i_1_n_1\ : STD_LOGIC;
signal \b_assign_reg_126_reg[11]_i_1_n_2\ : STD_LOGIC;
signal \b_assign_reg_126_reg[11]_i_1_n_3\ : STD_LOGIC;
signal \b_assign_reg_126_reg[15]_i_1_n_1\ : STD_LOGIC;
signal \b_assign_reg_126_reg[15]_i_1_n_2\ : STD_LOGIC;
signal \b_assign_reg_126_reg[15]_i_1_n_3\ : STD_LOGIC;
signal \b_assign_reg_126_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \b_assign_reg_126_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \b_assign_reg_126_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \b_assign_reg_126_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \b_assign_reg_126_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \b_assign_reg_126_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \b_assign_reg_126_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \b_assign_reg_126_reg[7]_i_1_n_3\ : STD_LOGIC;
signal b_read_reg_102 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal p_1_in : STD_LOGIC_VECTOR ( 15 downto 0 );
signal p_s_reg_45 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \p_s_reg_45[0]_i_1_n_0\ : STD_LOGIC;
signal \p_s_reg_45[10]_i_1_n_0\ : STD_LOGIC;
signal \p_s_reg_45[11]_i_1_n_0\ : STD_LOGIC;
signal \p_s_reg_45[12]_i_1_n_0\ : STD_LOGIC;
signal \p_s_reg_45[13]_i_1_n_0\ : STD_LOGIC;
signal \p_s_reg_45[14]_i_1_n_0\ : STD_LOGIC;
signal \p_s_reg_45[15]_i_1_n_0\ : STD_LOGIC;
signal \p_s_reg_45[15]_i_2_n_0\ : STD_LOGIC;
signal \p_s_reg_45[1]_i_1_n_0\ : STD_LOGIC;
signal \p_s_reg_45[2]_i_1_n_0\ : STD_LOGIC;
signal \p_s_reg_45[3]_i_1_n_0\ : STD_LOGIC;
signal \p_s_reg_45[4]_i_1_n_0\ : STD_LOGIC;
signal \p_s_reg_45[5]_i_1_n_0\ : STD_LOGIC;
signal \p_s_reg_45[6]_i_1_n_0\ : STD_LOGIC;
signal \p_s_reg_45[7]_i_1_n_0\ : STD_LOGIC;
signal \p_s_reg_45[8]_i_1_n_0\ : STD_LOGIC;
signal \p_s_reg_45[9]_i_1_n_0\ : STD_LOGIC;
signal result_reg_56 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \result_reg_56[15]_i_1_n_0\ : STD_LOGIC;
signal \^s_axi_gcd_bus_rdata\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal tmp_2_fu_66_p2 : STD_LOGIC;
signal tmp_3_fu_72_p2 : STD_LOGIC;
signal tmp_3_reg_115 : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_10_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_11_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_12_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_13_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_14_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_15_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_16_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_17_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_18_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_3_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_4_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_5_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_6_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_7_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_8_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_9_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115_reg[0]_i_1_n_1\ : STD_LOGIC;
signal \tmp_3_reg_115_reg[0]_i_1_n_2\ : STD_LOGIC;
signal \tmp_3_reg_115_reg[0]_i_1_n_3\ : STD_LOGIC;
signal \tmp_3_reg_115_reg[0]_i_2_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115_reg[0]_i_2_n_1\ : STD_LOGIC;
signal \tmp_3_reg_115_reg[0]_i_2_n_2\ : STD_LOGIC;
signal \tmp_3_reg_115_reg[0]_i_2_n_3\ : STD_LOGIC;
signal \NLW_a_assign_reg_121_reg[15]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_b_assign_reg_126_reg[15]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_tmp_3_reg_115_reg[0]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_tmp_3_reg_115_reg[0]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute FSM_ENCODING : string;
attribute FSM_ENCODING of \ap_CS_fsm_reg[0]\ : label is "none";
attribute FSM_ENCODING of \ap_CS_fsm_reg[1]\ : label is "none";
attribute FSM_ENCODING of \ap_CS_fsm_reg[2]\ : label is "none";
attribute FSM_ENCODING of \ap_CS_fsm_reg[3]\ : label is "none";
begin
s_axi_gcd_bus_BRESP(1) <= \<const0>\;
s_axi_gcd_bus_BRESP(0) <= \<const0>\;
s_axi_gcd_bus_RDATA(31) <= \<const0>\;
s_axi_gcd_bus_RDATA(30) <= \<const0>\;
s_axi_gcd_bus_RDATA(29) <= \<const0>\;
s_axi_gcd_bus_RDATA(28) <= \<const0>\;
s_axi_gcd_bus_RDATA(27) <= \<const0>\;
s_axi_gcd_bus_RDATA(26) <= \<const0>\;
s_axi_gcd_bus_RDATA(25) <= \<const0>\;
s_axi_gcd_bus_RDATA(24) <= \<const0>\;
s_axi_gcd_bus_RDATA(23) <= \<const0>\;
s_axi_gcd_bus_RDATA(22) <= \<const0>\;
s_axi_gcd_bus_RDATA(21) <= \<const0>\;
s_axi_gcd_bus_RDATA(20) <= \<const0>\;
s_axi_gcd_bus_RDATA(19) <= \<const0>\;
s_axi_gcd_bus_RDATA(18) <= \<const0>\;
s_axi_gcd_bus_RDATA(17) <= \<const0>\;
s_axi_gcd_bus_RDATA(16) <= \<const0>\;
s_axi_gcd_bus_RDATA(15 downto 0) <= \^s_axi_gcd_bus_rdata\(15 downto 0);
s_axi_gcd_bus_RRESP(1) <= \<const0>\;
s_axi_gcd_bus_RRESP(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\a_assign_reg_121[11]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(11),
I1 => p_s_reg_45(11),
O => \a_assign_reg_121[11]_i_2_n_0\
);
\a_assign_reg_121[11]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(10),
I1 => p_s_reg_45(10),
O => \a_assign_reg_121[11]_i_3_n_0\
);
\a_assign_reg_121[11]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(9),
I1 => p_s_reg_45(9),
O => \a_assign_reg_121[11]_i_4_n_0\
);
\a_assign_reg_121[11]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(8),
I1 => p_s_reg_45(8),
O => \a_assign_reg_121[11]_i_5_n_0\
);
\a_assign_reg_121[15]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(15),
I1 => p_s_reg_45(15),
O => \a_assign_reg_121[15]_i_2_n_0\
);
\a_assign_reg_121[15]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(14),
I1 => p_s_reg_45(14),
O => \a_assign_reg_121[15]_i_3_n_0\
);
\a_assign_reg_121[15]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(13),
I1 => p_s_reg_45(13),
O => \a_assign_reg_121[15]_i_4_n_0\
);
\a_assign_reg_121[15]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(12),
I1 => p_s_reg_45(12),
O => \a_assign_reg_121[15]_i_5_n_0\
);
\a_assign_reg_121[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(3),
I1 => p_s_reg_45(3),
O => \a_assign_reg_121[3]_i_2_n_0\
);
\a_assign_reg_121[3]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(2),
I1 => p_s_reg_45(2),
O => \a_assign_reg_121[3]_i_3_n_0\
);
\a_assign_reg_121[3]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(1),
I1 => p_s_reg_45(1),
O => \a_assign_reg_121[3]_i_4_n_0\
);
\a_assign_reg_121[3]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(0),
I1 => p_s_reg_45(0),
O => \a_assign_reg_121[3]_i_5_n_0\
);
\a_assign_reg_121[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(7),
I1 => p_s_reg_45(7),
O => \a_assign_reg_121[7]_i_2_n_0\
);
\a_assign_reg_121[7]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(6),
I1 => p_s_reg_45(6),
O => \a_assign_reg_121[7]_i_3_n_0\
);
\a_assign_reg_121[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(5),
I1 => p_s_reg_45(5),
O => \a_assign_reg_121[7]_i_4_n_0\
);
\a_assign_reg_121[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(4),
I1 => p_s_reg_45(4),
O => \a_assign_reg_121[7]_i_5_n_0\
);
\a_assign_reg_121_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(0),
Q => a_assign_reg_121(0),
R => '0'
);
\a_assign_reg_121_reg[10]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(10),
Q => a_assign_reg_121(10),
R => '0'
);
\a_assign_reg_121_reg[11]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(11),
Q => a_assign_reg_121(11),
R => '0'
);
\a_assign_reg_121_reg[11]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \a_assign_reg_121_reg[7]_i_1_n_0\,
CO(3) => \a_assign_reg_121_reg[11]_i_1_n_0\,
CO(2) => \a_assign_reg_121_reg[11]_i_1_n_1\,
CO(1) => \a_assign_reg_121_reg[11]_i_1_n_2\,
CO(0) => \a_assign_reg_121_reg[11]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => result_reg_56(11 downto 8),
O(3 downto 0) => a_assign_fu_78_p21_out(11 downto 8),
S(3) => \a_assign_reg_121[11]_i_2_n_0\,
S(2) => \a_assign_reg_121[11]_i_3_n_0\,
S(1) => \a_assign_reg_121[11]_i_4_n_0\,
S(0) => \a_assign_reg_121[11]_i_5_n_0\
);
\a_assign_reg_121_reg[12]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(12),
Q => a_assign_reg_121(12),
R => '0'
);
\a_assign_reg_121_reg[13]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(13),
Q => a_assign_reg_121(13),
R => '0'
);
\a_assign_reg_121_reg[14]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(14),
Q => a_assign_reg_121(14),
R => '0'
);
\a_assign_reg_121_reg[15]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(15),
Q => a_assign_reg_121(15),
R => '0'
);
\a_assign_reg_121_reg[15]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \a_assign_reg_121_reg[11]_i_1_n_0\,
CO(3) => \NLW_a_assign_reg_121_reg[15]_i_1_CO_UNCONNECTED\(3),
CO(2) => \a_assign_reg_121_reg[15]_i_1_n_1\,
CO(1) => \a_assign_reg_121_reg[15]_i_1_n_2\,
CO(0) => \a_assign_reg_121_reg[15]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => result_reg_56(14 downto 12),
O(3 downto 0) => a_assign_fu_78_p21_out(15 downto 12),
S(3) => \a_assign_reg_121[15]_i_2_n_0\,
S(2) => \a_assign_reg_121[15]_i_3_n_0\,
S(1) => \a_assign_reg_121[15]_i_4_n_0\,
S(0) => \a_assign_reg_121[15]_i_5_n_0\
);
\a_assign_reg_121_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(1),
Q => a_assign_reg_121(1),
R => '0'
);
\a_assign_reg_121_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(2),
Q => a_assign_reg_121(2),
R => '0'
);
\a_assign_reg_121_reg[3]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(3),
Q => a_assign_reg_121(3),
R => '0'
);
\a_assign_reg_121_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \a_assign_reg_121_reg[3]_i_1_n_0\,
CO(2) => \a_assign_reg_121_reg[3]_i_1_n_1\,
CO(1) => \a_assign_reg_121_reg[3]_i_1_n_2\,
CO(0) => \a_assign_reg_121_reg[3]_i_1_n_3\,
CYINIT => '1',
DI(3 downto 0) => result_reg_56(3 downto 0),
O(3 downto 0) => a_assign_fu_78_p21_out(3 downto 0),
S(3) => \a_assign_reg_121[3]_i_2_n_0\,
S(2) => \a_assign_reg_121[3]_i_3_n_0\,
S(1) => \a_assign_reg_121[3]_i_4_n_0\,
S(0) => \a_assign_reg_121[3]_i_5_n_0\
);
\a_assign_reg_121_reg[4]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(4),
Q => a_assign_reg_121(4),
R => '0'
);
\a_assign_reg_121_reg[5]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(5),
Q => a_assign_reg_121(5),
R => '0'
);
\a_assign_reg_121_reg[6]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(6),
Q => a_assign_reg_121(6),
R => '0'
);
\a_assign_reg_121_reg[7]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(7),
Q => a_assign_reg_121(7),
R => '0'
);
\a_assign_reg_121_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \a_assign_reg_121_reg[3]_i_1_n_0\,
CO(3) => \a_assign_reg_121_reg[7]_i_1_n_0\,
CO(2) => \a_assign_reg_121_reg[7]_i_1_n_1\,
CO(1) => \a_assign_reg_121_reg[7]_i_1_n_2\,
CO(0) => \a_assign_reg_121_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => result_reg_56(7 downto 4),
O(3 downto 0) => a_assign_fu_78_p21_out(7 downto 4),
S(3) => \a_assign_reg_121[7]_i_2_n_0\,
S(2) => \a_assign_reg_121[7]_i_3_n_0\,
S(1) => \a_assign_reg_121[7]_i_4_n_0\,
S(0) => \a_assign_reg_121[7]_i_5_n_0\
);
\a_assign_reg_121_reg[8]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(8),
Q => a_assign_reg_121(8),
R => '0'
);
\a_assign_reg_121_reg[9]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(9),
Q => a_assign_reg_121(9),
R => '0'
);
\a_read_reg_107_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(0),
Q => a_read_reg_107(0),
R => '0'
);
\a_read_reg_107_reg[10]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(10),
Q => a_read_reg_107(10),
R => '0'
);
\a_read_reg_107_reg[11]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(11),
Q => a_read_reg_107(11),
R => '0'
);
\a_read_reg_107_reg[12]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(12),
Q => a_read_reg_107(12),
R => '0'
);
\a_read_reg_107_reg[13]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(13),
Q => a_read_reg_107(13),
R => '0'
);
\a_read_reg_107_reg[14]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(14),
Q => a_read_reg_107(14),
R => '0'
);
\a_read_reg_107_reg[15]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(15),
Q => a_read_reg_107(15),
R => '0'
);
\a_read_reg_107_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(1),
Q => a_read_reg_107(1),
R => '0'
);
\a_read_reg_107_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(2),
Q => a_read_reg_107(2),
R => '0'
);
\a_read_reg_107_reg[3]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(3),
Q => a_read_reg_107(3),
R => '0'
);
\a_read_reg_107_reg[4]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(4),
Q => a_read_reg_107(4),
R => '0'
);
\a_read_reg_107_reg[5]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(5),
Q => a_read_reg_107(5),
R => '0'
);
\a_read_reg_107_reg[6]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(6),
Q => a_read_reg_107(6),
R => '0'
);
\a_read_reg_107_reg[7]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(7),
Q => a_read_reg_107(7),
R => '0'
);
\a_read_reg_107_reg[8]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(8),
Q => a_read_reg_107(8),
R => '0'
);
\a_read_reg_107_reg[9]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(9),
Q => a_read_reg_107(9),
R => '0'
);
\ap_CS_fsm[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => ap_CS_fsm_state2,
I1 => ap_CS_fsm_state4,
O => ap_NS_fsm(2)
);
\ap_CS_fsm[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => ap_CS_fsm_state3,
I1 => tmp_2_fu_66_p2,
O => a_assign_reg_1210
);
\ap_CS_fsm_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => ap_clk,
CE => '1',
D => ap_NS_fsm(0),
Q => \ap_CS_fsm_reg_n_0_[0]\,
S => ap_rst_n_inv
);
\ap_CS_fsm_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => ap_NS_fsm(1),
Q => ap_CS_fsm_state2,
R => ap_rst_n_inv
);
\ap_CS_fsm_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => ap_NS_fsm(2),
Q => ap_CS_fsm_state3,
R => ap_rst_n_inv
);
\ap_CS_fsm_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => a_assign_reg_1210,
Q => ap_CS_fsm_state4,
R => ap_rst_n_inv
);
\b_assign_reg_126[11]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(11),
I1 => result_reg_56(11),
O => \b_assign_reg_126[11]_i_2_n_0\
);
\b_assign_reg_126[11]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(10),
I1 => result_reg_56(10),
O => \b_assign_reg_126[11]_i_3_n_0\
);
\b_assign_reg_126[11]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(9),
I1 => result_reg_56(9),
O => \b_assign_reg_126[11]_i_4_n_0\
);
\b_assign_reg_126[11]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(8),
I1 => result_reg_56(8),
O => \b_assign_reg_126[11]_i_5_n_0\
);
\b_assign_reg_126[15]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(15),
I1 => result_reg_56(15),
O => \b_assign_reg_126[15]_i_2_n_0\
);
\b_assign_reg_126[15]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(14),
I1 => result_reg_56(14),
O => \b_assign_reg_126[15]_i_3_n_0\
);
\b_assign_reg_126[15]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(13),
I1 => result_reg_56(13),
O => \b_assign_reg_126[15]_i_4_n_0\
);
\b_assign_reg_126[15]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(12),
I1 => result_reg_56(12),
O => \b_assign_reg_126[15]_i_5_n_0\
);
\b_assign_reg_126[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(3),
I1 => result_reg_56(3),
O => \b_assign_reg_126[3]_i_2_n_0\
);
\b_assign_reg_126[3]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(2),
I1 => result_reg_56(2),
O => \b_assign_reg_126[3]_i_3_n_0\
);
\b_assign_reg_126[3]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(1),
I1 => result_reg_56(1),
O => \b_assign_reg_126[3]_i_4_n_0\
);
\b_assign_reg_126[3]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(0),
I1 => result_reg_56(0),
O => \b_assign_reg_126[3]_i_5_n_0\
);
\b_assign_reg_126[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(7),
I1 => result_reg_56(7),
O => \b_assign_reg_126[7]_i_2_n_0\
);
\b_assign_reg_126[7]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(6),
I1 => result_reg_56(6),
O => \b_assign_reg_126[7]_i_3_n_0\
);
\b_assign_reg_126[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(5),
I1 => result_reg_56(5),
O => \b_assign_reg_126[7]_i_4_n_0\
);
\b_assign_reg_126[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(4),
I1 => result_reg_56(4),
O => \b_assign_reg_126[7]_i_5_n_0\
);
\b_assign_reg_126_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(0),
Q => b_assign_reg_126(0),
R => '0'
);
\b_assign_reg_126_reg[10]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(10),
Q => b_assign_reg_126(10),
R => '0'
);
\b_assign_reg_126_reg[11]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(11),
Q => b_assign_reg_126(11),
R => '0'
);
\b_assign_reg_126_reg[11]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \b_assign_reg_126_reg[7]_i_1_n_0\,
CO(3) => \b_assign_reg_126_reg[11]_i_1_n_0\,
CO(2) => \b_assign_reg_126_reg[11]_i_1_n_1\,
CO(1) => \b_assign_reg_126_reg[11]_i_1_n_2\,
CO(0) => \b_assign_reg_126_reg[11]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => p_s_reg_45(11 downto 8),
O(3 downto 0) => b_assign_fu_84_p20_out(11 downto 8),
S(3) => \b_assign_reg_126[11]_i_2_n_0\,
S(2) => \b_assign_reg_126[11]_i_3_n_0\,
S(1) => \b_assign_reg_126[11]_i_4_n_0\,
S(0) => \b_assign_reg_126[11]_i_5_n_0\
);
\b_assign_reg_126_reg[12]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(12),
Q => b_assign_reg_126(12),
R => '0'
);
\b_assign_reg_126_reg[13]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(13),
Q => b_assign_reg_126(13),
R => '0'
);
\b_assign_reg_126_reg[14]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(14),
Q => b_assign_reg_126(14),
R => '0'
);
\b_assign_reg_126_reg[15]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(15),
Q => b_assign_reg_126(15),
R => '0'
);
\b_assign_reg_126_reg[15]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \b_assign_reg_126_reg[11]_i_1_n_0\,
CO(3) => \NLW_b_assign_reg_126_reg[15]_i_1_CO_UNCONNECTED\(3),
CO(2) => \b_assign_reg_126_reg[15]_i_1_n_1\,
CO(1) => \b_assign_reg_126_reg[15]_i_1_n_2\,
CO(0) => \b_assign_reg_126_reg[15]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => p_s_reg_45(14 downto 12),
O(3 downto 0) => b_assign_fu_84_p20_out(15 downto 12),
S(3) => \b_assign_reg_126[15]_i_2_n_0\,
S(2) => \b_assign_reg_126[15]_i_3_n_0\,
S(1) => \b_assign_reg_126[15]_i_4_n_0\,
S(0) => \b_assign_reg_126[15]_i_5_n_0\
);
\b_assign_reg_126_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(1),
Q => b_assign_reg_126(1),
R => '0'
);
\b_assign_reg_126_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(2),
Q => b_assign_reg_126(2),
R => '0'
);
\b_assign_reg_126_reg[3]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(3),
Q => b_assign_reg_126(3),
R => '0'
);
\b_assign_reg_126_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \b_assign_reg_126_reg[3]_i_1_n_0\,
CO(2) => \b_assign_reg_126_reg[3]_i_1_n_1\,
CO(1) => \b_assign_reg_126_reg[3]_i_1_n_2\,
CO(0) => \b_assign_reg_126_reg[3]_i_1_n_3\,
CYINIT => '1',
DI(3 downto 0) => p_s_reg_45(3 downto 0),
O(3 downto 0) => b_assign_fu_84_p20_out(3 downto 0),
S(3) => \b_assign_reg_126[3]_i_2_n_0\,
S(2) => \b_assign_reg_126[3]_i_3_n_0\,
S(1) => \b_assign_reg_126[3]_i_4_n_0\,
S(0) => \b_assign_reg_126[3]_i_5_n_0\
);
\b_assign_reg_126_reg[4]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(4),
Q => b_assign_reg_126(4),
R => '0'
);
\b_assign_reg_126_reg[5]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(5),
Q => b_assign_reg_126(5),
R => '0'
);
\b_assign_reg_126_reg[6]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(6),
Q => b_assign_reg_126(6),
R => '0'
);
\b_assign_reg_126_reg[7]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(7),
Q => b_assign_reg_126(7),
R => '0'
);
\b_assign_reg_126_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \b_assign_reg_126_reg[3]_i_1_n_0\,
CO(3) => \b_assign_reg_126_reg[7]_i_1_n_0\,
CO(2) => \b_assign_reg_126_reg[7]_i_1_n_1\,
CO(1) => \b_assign_reg_126_reg[7]_i_1_n_2\,
CO(0) => \b_assign_reg_126_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => p_s_reg_45(7 downto 4),
O(3 downto 0) => b_assign_fu_84_p20_out(7 downto 4),
S(3) => \b_assign_reg_126[7]_i_2_n_0\,
S(2) => \b_assign_reg_126[7]_i_3_n_0\,
S(1) => \b_assign_reg_126[7]_i_4_n_0\,
S(0) => \b_assign_reg_126[7]_i_5_n_0\
);
\b_assign_reg_126_reg[8]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(8),
Q => b_assign_reg_126(8),
R => '0'
);
\b_assign_reg_126_reg[9]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(9),
Q => b_assign_reg_126(9),
R => '0'
);
\b_read_reg_102_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(0),
Q => b_read_reg_102(0),
R => '0'
);
\b_read_reg_102_reg[10]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(10),
Q => b_read_reg_102(10),
R => '0'
);
\b_read_reg_102_reg[11]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(11),
Q => b_read_reg_102(11),
R => '0'
);
\b_read_reg_102_reg[12]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(12),
Q => b_read_reg_102(12),
R => '0'
);
\b_read_reg_102_reg[13]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(13),
Q => b_read_reg_102(13),
R => '0'
);
\b_read_reg_102_reg[14]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(14),
Q => b_read_reg_102(14),
R => '0'
);
\b_read_reg_102_reg[15]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(15),
Q => b_read_reg_102(15),
R => '0'
);
\b_read_reg_102_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(1),
Q => b_read_reg_102(1),
R => '0'
);
\b_read_reg_102_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(2),
Q => b_read_reg_102(2),
R => '0'
);
\b_read_reg_102_reg[3]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(3),
Q => b_read_reg_102(3),
R => '0'
);
\b_read_reg_102_reg[4]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(4),
Q => b_read_reg_102(4),
R => '0'
);
\b_read_reg_102_reg[5]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(5),
Q => b_read_reg_102(5),
R => '0'
);
\b_read_reg_102_reg[6]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(6),
Q => b_read_reg_102(6),
R => '0'
);
\b_read_reg_102_reg[7]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(7),
Q => b_read_reg_102(7),
R => '0'
);
\b_read_reg_102_reg[8]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(8),
Q => b_read_reg_102(8),
R => '0'
);
\b_read_reg_102_reg[9]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(9),
Q => b_read_reg_102(9),
R => '0'
);
gcd_gcd_bus_s_axi_U: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd_gcd_bus_s_axi
port map (
CO(0) => tmp_2_fu_66_p2,
D(1 downto 0) => ap_NS_fsm(1 downto 0),
E(0) => ap_NS_fsm1,
Q(3) => ap_CS_fsm_state4,
Q(2) => ap_CS_fsm_state3,
Q(1) => ap_CS_fsm_state2,
Q(0) => \ap_CS_fsm_reg_n_0_[0]\,
SR(0) => ap_rst_n_inv,
\a_read_reg_107_reg[15]\(15 downto 0) => a(15 downto 0),
ap_clk => ap_clk,
ap_rst_n => ap_rst_n,
\b_read_reg_102_reg[15]\(15 downto 0) => b(15 downto 0),
interrupt => interrupt,
\out\(2) => s_axi_gcd_bus_BVALID,
\out\(1) => s_axi_gcd_bus_WREADY,
\out\(0) => s_axi_gcd_bus_AWREADY,
\p_s_reg_45_reg[15]\(15 downto 0) => p_s_reg_45(15 downto 0),
\result_reg_56_reg[15]\(15 downto 0) => result_reg_56(15 downto 0),
s_axi_gcd_bus_ARADDR(5 downto 0) => s_axi_gcd_bus_ARADDR(5 downto 0),
s_axi_gcd_bus_ARVALID => s_axi_gcd_bus_ARVALID,
s_axi_gcd_bus_AWADDR(5 downto 0) => s_axi_gcd_bus_AWADDR(5 downto 0),
s_axi_gcd_bus_AWVALID => s_axi_gcd_bus_AWVALID,
s_axi_gcd_bus_BREADY => s_axi_gcd_bus_BREADY,
s_axi_gcd_bus_RDATA(15 downto 0) => \^s_axi_gcd_bus_rdata\(15 downto 0),
s_axi_gcd_bus_RREADY => s_axi_gcd_bus_RREADY,
s_axi_gcd_bus_RVALID(1) => s_axi_gcd_bus_RVALID,
s_axi_gcd_bus_RVALID(0) => s_axi_gcd_bus_ARREADY,
s_axi_gcd_bus_WDATA(15 downto 0) => s_axi_gcd_bus_WDATA(15 downto 0),
s_axi_gcd_bus_WSTRB(1 downto 0) => s_axi_gcd_bus_WSTRB(1 downto 0),
s_axi_gcd_bus_WVALID => s_axi_gcd_bus_WVALID
);
\p_s_reg_45[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(0),
I1 => b_read_reg_102(0),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[0]_i_1_n_0\
);
\p_s_reg_45[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(10),
I1 => b_read_reg_102(10),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[10]_i_1_n_0\
);
\p_s_reg_45[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(11),
I1 => b_read_reg_102(11),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[11]_i_1_n_0\
);
\p_s_reg_45[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(12),
I1 => b_read_reg_102(12),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[12]_i_1_n_0\
);
\p_s_reg_45[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(13),
I1 => b_read_reg_102(13),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[13]_i_1_n_0\
);
\p_s_reg_45[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(14),
I1 => b_read_reg_102(14),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[14]_i_1_n_0\
);
\p_s_reg_45[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"74"
)
port map (
I0 => tmp_3_reg_115,
I1 => ap_CS_fsm_state4,
I2 => ap_CS_fsm_state2,
O => \p_s_reg_45[15]_i_1_n_0\
);
\p_s_reg_45[15]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(15),
I1 => b_read_reg_102(15),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[15]_i_2_n_0\
);
\p_s_reg_45[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(1),
I1 => b_read_reg_102(1),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[1]_i_1_n_0\
);
\p_s_reg_45[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(2),
I1 => b_read_reg_102(2),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[2]_i_1_n_0\
);
\p_s_reg_45[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(3),
I1 => b_read_reg_102(3),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[3]_i_1_n_0\
);
\p_s_reg_45[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(4),
I1 => b_read_reg_102(4),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[4]_i_1_n_0\
);
\p_s_reg_45[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(5),
I1 => b_read_reg_102(5),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[5]_i_1_n_0\
);
\p_s_reg_45[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(6),
I1 => b_read_reg_102(6),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[6]_i_1_n_0\
);
\p_s_reg_45[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(7),
I1 => b_read_reg_102(7),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[7]_i_1_n_0\
);
\p_s_reg_45[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(8),
I1 => b_read_reg_102(8),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[8]_i_1_n_0\
);
\p_s_reg_45[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(9),
I1 => b_read_reg_102(9),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[9]_i_1_n_0\
);
\p_s_reg_45_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[0]_i_1_n_0\,
Q => p_s_reg_45(0),
R => '0'
);
\p_s_reg_45_reg[10]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[10]_i_1_n_0\,
Q => p_s_reg_45(10),
R => '0'
);
\p_s_reg_45_reg[11]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[11]_i_1_n_0\,
Q => p_s_reg_45(11),
R => '0'
);
\p_s_reg_45_reg[12]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[12]_i_1_n_0\,
Q => p_s_reg_45(12),
R => '0'
);
\p_s_reg_45_reg[13]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[13]_i_1_n_0\,
Q => p_s_reg_45(13),
R => '0'
);
\p_s_reg_45_reg[14]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[14]_i_1_n_0\,
Q => p_s_reg_45(14),
R => '0'
);
\p_s_reg_45_reg[15]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[15]_i_2_n_0\,
Q => p_s_reg_45(15),
R => '0'
);
\p_s_reg_45_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[1]_i_1_n_0\,
Q => p_s_reg_45(1),
R => '0'
);
\p_s_reg_45_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[2]_i_1_n_0\,
Q => p_s_reg_45(2),
R => '0'
);
\p_s_reg_45_reg[3]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[3]_i_1_n_0\,
Q => p_s_reg_45(3),
R => '0'
);
\p_s_reg_45_reg[4]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[4]_i_1_n_0\,
Q => p_s_reg_45(4),
R => '0'
);
\p_s_reg_45_reg[5]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[5]_i_1_n_0\,
Q => p_s_reg_45(5),
R => '0'
);
\p_s_reg_45_reg[6]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[6]_i_1_n_0\,
Q => p_s_reg_45(6),
R => '0'
);
\p_s_reg_45_reg[7]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[7]_i_1_n_0\,
Q => p_s_reg_45(7),
R => '0'
);
\p_s_reg_45_reg[8]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[8]_i_1_n_0\,
Q => p_s_reg_45(8),
R => '0'
);
\p_s_reg_45_reg[9]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[9]_i_1_n_0\,
Q => p_s_reg_45(9),
R => '0'
);
\result_reg_56[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(0),
I1 => a_read_reg_107(0),
I2 => ap_CS_fsm_state4,
O => p_1_in(0)
);
\result_reg_56[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(10),
I1 => a_read_reg_107(10),
I2 => ap_CS_fsm_state4,
O => p_1_in(10)
);
\result_reg_56[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(11),
I1 => a_read_reg_107(11),
I2 => ap_CS_fsm_state4,
O => p_1_in(11)
);
\result_reg_56[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(12),
I1 => a_read_reg_107(12),
I2 => ap_CS_fsm_state4,
O => p_1_in(12)
);
\result_reg_56[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(13),
I1 => a_read_reg_107(13),
I2 => ap_CS_fsm_state4,
O => p_1_in(13)
);
\result_reg_56[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(14),
I1 => a_read_reg_107(14),
I2 => ap_CS_fsm_state4,
O => p_1_in(14)
);
\result_reg_56[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => tmp_3_reg_115,
I1 => ap_CS_fsm_state4,
I2 => ap_CS_fsm_state2,
O => \result_reg_56[15]_i_1_n_0\
);
\result_reg_56[15]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(15),
I1 => a_read_reg_107(15),
I2 => ap_CS_fsm_state4,
O => p_1_in(15)
);
\result_reg_56[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(1),
I1 => a_read_reg_107(1),
I2 => ap_CS_fsm_state4,
O => p_1_in(1)
);
\result_reg_56[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(2),
I1 => a_read_reg_107(2),
I2 => ap_CS_fsm_state4,
O => p_1_in(2)
);
\result_reg_56[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(3),
I1 => a_read_reg_107(3),
I2 => ap_CS_fsm_state4,
O => p_1_in(3)
);
\result_reg_56[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(4),
I1 => a_read_reg_107(4),
I2 => ap_CS_fsm_state4,
O => p_1_in(4)
);
\result_reg_56[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(5),
I1 => a_read_reg_107(5),
I2 => ap_CS_fsm_state4,
O => p_1_in(5)
);
\result_reg_56[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(6),
I1 => a_read_reg_107(6),
I2 => ap_CS_fsm_state4,
O => p_1_in(6)
);
\result_reg_56[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(7),
I1 => a_read_reg_107(7),
I2 => ap_CS_fsm_state4,
O => p_1_in(7)
);
\result_reg_56[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(8),
I1 => a_read_reg_107(8),
I2 => ap_CS_fsm_state4,
O => p_1_in(8)
);
\result_reg_56[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(9),
I1 => a_read_reg_107(9),
I2 => ap_CS_fsm_state4,
O => p_1_in(9)
);
\result_reg_56_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(0),
Q => result_reg_56(0),
R => '0'
);
\result_reg_56_reg[10]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(10),
Q => result_reg_56(10),
R => '0'
);
\result_reg_56_reg[11]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(11),
Q => result_reg_56(11),
R => '0'
);
\result_reg_56_reg[12]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(12),
Q => result_reg_56(12),
R => '0'
);
\result_reg_56_reg[13]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(13),
Q => result_reg_56(13),
R => '0'
);
\result_reg_56_reg[14]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(14),
Q => result_reg_56(14),
R => '0'
);
\result_reg_56_reg[15]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(15),
Q => result_reg_56(15),
R => '0'
);
\result_reg_56_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(1),
Q => result_reg_56(1),
R => '0'
);
\result_reg_56_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(2),
Q => result_reg_56(2),
R => '0'
);
\result_reg_56_reg[3]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(3),
Q => result_reg_56(3),
R => '0'
);
\result_reg_56_reg[4]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(4),
Q => result_reg_56(4),
R => '0'
);
\result_reg_56_reg[5]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(5),
Q => result_reg_56(5),
R => '0'
);
\result_reg_56_reg[6]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(6),
Q => result_reg_56(6),
R => '0'
);
\result_reg_56_reg[7]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(7),
Q => result_reg_56(7),
R => '0'
);
\result_reg_56_reg[8]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(8),
Q => result_reg_56(8),
R => '0'
);
\result_reg_56_reg[9]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(9),
Q => result_reg_56(9),
R => '0'
);
\tmp_3_reg_115[0]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => result_reg_56(8),
I1 => p_s_reg_45(8),
I2 => result_reg_56(9),
I3 => p_s_reg_45(9),
O => \tmp_3_reg_115[0]_i_10_n_0\
);
\tmp_3_reg_115[0]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => result_reg_56(6),
I1 => p_s_reg_45(6),
I2 => p_s_reg_45(7),
I3 => result_reg_56(7),
O => \tmp_3_reg_115[0]_i_11_n_0\
);
\tmp_3_reg_115[0]_i_12\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => result_reg_56(4),
I1 => p_s_reg_45(4),
I2 => p_s_reg_45(5),
I3 => result_reg_56(5),
O => \tmp_3_reg_115[0]_i_12_n_0\
);
\tmp_3_reg_115[0]_i_13\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => result_reg_56(2),
I1 => p_s_reg_45(2),
I2 => p_s_reg_45(3),
I3 => result_reg_56(3),
O => \tmp_3_reg_115[0]_i_13_n_0\
);
\tmp_3_reg_115[0]_i_14\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => result_reg_56(0),
I1 => p_s_reg_45(0),
I2 => p_s_reg_45(1),
I3 => result_reg_56(1),
O => \tmp_3_reg_115[0]_i_14_n_0\
);
\tmp_3_reg_115[0]_i_15\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => result_reg_56(6),
I1 => p_s_reg_45(6),
I2 => result_reg_56(7),
I3 => p_s_reg_45(7),
O => \tmp_3_reg_115[0]_i_15_n_0\
);
\tmp_3_reg_115[0]_i_16\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => result_reg_56(4),
I1 => p_s_reg_45(4),
I2 => result_reg_56(5),
I3 => p_s_reg_45(5),
O => \tmp_3_reg_115[0]_i_16_n_0\
);
\tmp_3_reg_115[0]_i_17\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => result_reg_56(2),
I1 => p_s_reg_45(2),
I2 => result_reg_56(3),
I3 => p_s_reg_45(3),
O => \tmp_3_reg_115[0]_i_17_n_0\
);
\tmp_3_reg_115[0]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => result_reg_56(0),
I1 => p_s_reg_45(0),
I2 => result_reg_56(1),
I3 => p_s_reg_45(1),
O => \tmp_3_reg_115[0]_i_18_n_0\
);
\tmp_3_reg_115[0]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => result_reg_56(14),
I1 => p_s_reg_45(14),
I2 => result_reg_56(15),
I3 => p_s_reg_45(15),
O => \tmp_3_reg_115[0]_i_3_n_0\
);
\tmp_3_reg_115[0]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => result_reg_56(12),
I1 => p_s_reg_45(12),
I2 => p_s_reg_45(13),
I3 => result_reg_56(13),
O => \tmp_3_reg_115[0]_i_4_n_0\
);
\tmp_3_reg_115[0]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => result_reg_56(10),
I1 => p_s_reg_45(10),
I2 => p_s_reg_45(11),
I3 => result_reg_56(11),
O => \tmp_3_reg_115[0]_i_5_n_0\
);
\tmp_3_reg_115[0]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => result_reg_56(8),
I1 => p_s_reg_45(8),
I2 => p_s_reg_45(9),
I3 => result_reg_56(9),
O => \tmp_3_reg_115[0]_i_6_n_0\
);
\tmp_3_reg_115[0]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => result_reg_56(14),
I1 => p_s_reg_45(14),
I2 => p_s_reg_45(15),
I3 => result_reg_56(15),
O => \tmp_3_reg_115[0]_i_7_n_0\
);
\tmp_3_reg_115[0]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => result_reg_56(12),
I1 => p_s_reg_45(12),
I2 => result_reg_56(13),
I3 => p_s_reg_45(13),
O => \tmp_3_reg_115[0]_i_8_n_0\
);
\tmp_3_reg_115[0]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => result_reg_56(10),
I1 => p_s_reg_45(10),
I2 => result_reg_56(11),
I3 => p_s_reg_45(11),
O => \tmp_3_reg_115[0]_i_9_n_0\
);
\tmp_3_reg_115_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => tmp_3_fu_72_p2,
Q => tmp_3_reg_115,
R => '0'
);
\tmp_3_reg_115_reg[0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \tmp_3_reg_115_reg[0]_i_2_n_0\,
CO(3) => tmp_3_fu_72_p2,
CO(2) => \tmp_3_reg_115_reg[0]_i_1_n_1\,
CO(1) => \tmp_3_reg_115_reg[0]_i_1_n_2\,
CO(0) => \tmp_3_reg_115_reg[0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \tmp_3_reg_115[0]_i_3_n_0\,
DI(2) => \tmp_3_reg_115[0]_i_4_n_0\,
DI(1) => \tmp_3_reg_115[0]_i_5_n_0\,
DI(0) => \tmp_3_reg_115[0]_i_6_n_0\,
O(3 downto 0) => \NLW_tmp_3_reg_115_reg[0]_i_1_O_UNCONNECTED\(3 downto 0),
S(3) => \tmp_3_reg_115[0]_i_7_n_0\,
S(2) => \tmp_3_reg_115[0]_i_8_n_0\,
S(1) => \tmp_3_reg_115[0]_i_9_n_0\,
S(0) => \tmp_3_reg_115[0]_i_10_n_0\
);
\tmp_3_reg_115_reg[0]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \tmp_3_reg_115_reg[0]_i_2_n_0\,
CO(2) => \tmp_3_reg_115_reg[0]_i_2_n_1\,
CO(1) => \tmp_3_reg_115_reg[0]_i_2_n_2\,
CO(0) => \tmp_3_reg_115_reg[0]_i_2_n_3\,
CYINIT => '0',
DI(3) => \tmp_3_reg_115[0]_i_11_n_0\,
DI(2) => \tmp_3_reg_115[0]_i_12_n_0\,
DI(1) => \tmp_3_reg_115[0]_i_13_n_0\,
DI(0) => \tmp_3_reg_115[0]_i_14_n_0\,
O(3 downto 0) => \NLW_tmp_3_reg_115_reg[0]_i_2_O_UNCONNECTED\(3 downto 0),
S(3) => \tmp_3_reg_115[0]_i_15_n_0\,
S(2) => \tmp_3_reg_115[0]_i_16_n_0\,
S(1) => \tmp_3_reg_115[0]_i_17_n_0\,
S(0) => \tmp_3_reg_115[0]_i_18_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
s_axi_gcd_bus_AWADDR : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_gcd_bus_AWVALID : in STD_LOGIC;
s_axi_gcd_bus_AWREADY : out STD_LOGIC;
s_axi_gcd_bus_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_gcd_bus_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_gcd_bus_WVALID : in STD_LOGIC;
s_axi_gcd_bus_WREADY : out STD_LOGIC;
s_axi_gcd_bus_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_gcd_bus_BVALID : out STD_LOGIC;
s_axi_gcd_bus_BREADY : in STD_LOGIC;
s_axi_gcd_bus_ARADDR : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_gcd_bus_ARVALID : in STD_LOGIC;
s_axi_gcd_bus_ARREADY : out STD_LOGIC;
s_axi_gcd_bus_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_gcd_bus_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_gcd_bus_RVALID : out STD_LOGIC;
s_axi_gcd_bus_RREADY : in STD_LOGIC;
ap_clk : in STD_LOGIC;
ap_rst_n : in STD_LOGIC;
interrupt : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "gcd_block_design_gcd_0_0,gcd,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute IP_DEFINITION_SOURCE : string;
attribute IP_DEFINITION_SOURCE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "HLS";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "gcd,Vivado 2018.2";
attribute hls_module : string;
attribute hls_module of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of inst : label is 32;
attribute C_S_AXI_GCD_BUS_ADDR_WIDTH : integer;
attribute C_S_AXI_GCD_BUS_ADDR_WIDTH of inst : label is 6;
attribute C_S_AXI_GCD_BUS_DATA_WIDTH : integer;
attribute C_S_AXI_GCD_BUS_DATA_WIDTH of inst : label is 32;
attribute C_S_AXI_GCD_BUS_WSTRB_WIDTH : integer;
attribute C_S_AXI_GCD_BUS_WSTRB_WIDTH of inst : label is 4;
attribute C_S_AXI_WSTRB_WIDTH : integer;
attribute C_S_AXI_WSTRB_WIDTH of inst : label is 4;
attribute ap_ST_fsm_state1 : string;
attribute ap_ST_fsm_state1 of inst : label is "4'b0001";
attribute ap_ST_fsm_state2 : string;
attribute ap_ST_fsm_state2 of inst : label is "4'b0010";
attribute ap_ST_fsm_state3 : string;
attribute ap_ST_fsm_state3 of inst : label is "4'b0100";
attribute ap_ST_fsm_state4 : string;
attribute ap_ST_fsm_state4 of inst : label is "4'b1000";
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of ap_clk : signal is "xilinx.com:signal:clock:1.0 ap_clk CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of ap_clk : signal is "XIL_INTERFACENAME ap_clk, ASSOCIATED_BUSIF s_axi_gcd_bus, ASSOCIATED_RESET ap_rst_n, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_0_FCLK_CLK0";
attribute X_INTERFACE_INFO of ap_rst_n : signal is "xilinx.com:signal:reset:1.0 ap_rst_n RST";
attribute X_INTERFACE_PARAMETER of ap_rst_n : signal is "XIL_INTERFACENAME ap_rst_n, POLARITY ACTIVE_LOW, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {RST {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}";
attribute X_INTERFACE_INFO of interrupt : signal is "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
attribute X_INTERFACE_PARAMETER of interrupt : signal is "XIL_INTERFACENAME interrupt, SENSITIVITY LEVEL_HIGH, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {INTERRUPT {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, PortWidth 1";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_ARREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus ARREADY";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_ARVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus ARVALID";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_AWREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus AWREADY";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_AWVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus AWVALID";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_BREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus BREADY";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_BVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus BVALID";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_RREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus RREADY";
attribute X_INTERFACE_PARAMETER of s_axi_gcd_bus_RREADY : signal is "XIL_INTERFACENAME s_axi_gcd_bus, ADDR_WIDTH 6, DATA_WIDTH 32, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 50000000, ID_WIDTH 0, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_RVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus RVALID";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_WREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus WREADY";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_WVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus WVALID";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_ARADDR : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus ARADDR";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_AWADDR : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus AWADDR";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_BRESP : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus BRESP";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_RDATA : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus RDATA";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_RRESP : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus RRESP";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_WDATA : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus WDATA";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_WSTRB : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus WSTRB";
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd
port map (
ap_clk => ap_clk,
ap_rst_n => ap_rst_n,
interrupt => interrupt,
s_axi_gcd_bus_ARADDR(5 downto 0) => s_axi_gcd_bus_ARADDR(5 downto 0),
s_axi_gcd_bus_ARREADY => s_axi_gcd_bus_ARREADY,
s_axi_gcd_bus_ARVALID => s_axi_gcd_bus_ARVALID,
s_axi_gcd_bus_AWADDR(5 downto 0) => s_axi_gcd_bus_AWADDR(5 downto 0),
s_axi_gcd_bus_AWREADY => s_axi_gcd_bus_AWREADY,
s_axi_gcd_bus_AWVALID => s_axi_gcd_bus_AWVALID,
s_axi_gcd_bus_BREADY => s_axi_gcd_bus_BREADY,
s_axi_gcd_bus_BRESP(1 downto 0) => s_axi_gcd_bus_BRESP(1 downto 0),
s_axi_gcd_bus_BVALID => s_axi_gcd_bus_BVALID,
s_axi_gcd_bus_RDATA(31 downto 0) => s_axi_gcd_bus_RDATA(31 downto 0),
s_axi_gcd_bus_RREADY => s_axi_gcd_bus_RREADY,
s_axi_gcd_bus_RRESP(1 downto 0) => s_axi_gcd_bus_RRESP(1 downto 0),
s_axi_gcd_bus_RVALID => s_axi_gcd_bus_RVALID,
s_axi_gcd_bus_WDATA(31 downto 0) => s_axi_gcd_bus_WDATA(31 downto 0),
s_axi_gcd_bus_WREADY => s_axi_gcd_bus_WREADY,
s_axi_gcd_bus_WSTRB(3 downto 0) => s_axi_gcd_bus_WSTRB(3 downto 0),
s_axi_gcd_bus_WVALID => s_axi_gcd_bus_WVALID
);
end STRUCTURE;
| mit | c702196f7460b09ef383ef06752b2ca3 | 0.513402 | 2.509781 | false | false | false | false |
natsutan/NPU | fpga_implement/npu8/npu8.srcs/sources_1/ip/mul17_16/synth/mul17_16.vhd | 1 | 5,670 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:mult_gen:12.0
-- IP Revision: 12
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY mult_gen_v12_0_12;
USE mult_gen_v12_0_12.mult_gen_v12_0_12;
ENTITY mul17_16 IS
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
P : OUT STD_LOGIC_VECTOR(24 DOWNTO 0)
);
END mul17_16;
ARCHITECTURE mul17_16_arch OF mul17_16 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF mul17_16_arch: ARCHITECTURE IS "yes";
COMPONENT mult_gen_v12_0_12 IS
GENERIC (
C_VERBOSITY : INTEGER;
C_MODEL_TYPE : INTEGER;
C_OPTIMIZE_GOAL : INTEGER;
C_XDEVICEFAMILY : STRING;
C_HAS_CE : INTEGER;
C_HAS_SCLR : INTEGER;
C_LATENCY : INTEGER;
C_A_WIDTH : INTEGER;
C_A_TYPE : INTEGER;
C_B_WIDTH : INTEGER;
C_B_TYPE : INTEGER;
C_OUT_HIGH : INTEGER;
C_OUT_LOW : INTEGER;
C_MULT_TYPE : INTEGER;
C_CE_OVERRIDES_SCLR : INTEGER;
C_CCM_IMP : INTEGER;
C_B_VALUE : STRING;
C_HAS_ZERO_DETECT : INTEGER;
C_ROUND_OUTPUT : INTEGER;
C_ROUND_PT : INTEGER
);
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
CE : IN STD_LOGIC;
SCLR : IN STD_LOGIC;
P : OUT STD_LOGIC_VECTOR(24 DOWNTO 0)
);
END COMPONENT mult_gen_v12_0_12;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF mul17_16_arch: ARCHITECTURE IS "mult_gen_v12_0_12,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF mul17_16_arch : ARCHITECTURE IS "mul17_16,mult_gen_v12_0_12,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF mul17_16_arch: ARCHITECTURE IS "mul17_16,mult_gen_v12_0_12,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mult_gen,x_ipVersion=12.0,x_ipCoreRevision=12,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_VERBOSITY=0,C_MODEL_TYPE=0,C_OPTIMIZE_GOAL=1,C_XDEVICEFAMILY=kintexu,C_HAS_CE=0,C_HAS_SCLR=0,C_LATENCY=4,C_A_WIDTH=17,C_A_TYPE=1,C_B_WIDTH=16,C_B_TYPE=1,C_OUT_HIGH=32,C_OUT_LOW=8,C_MULT_TYPE=0,C_CE_OVERRIDES_SCLR=0,C_CCM_IMP=0,C_B_VALUE=10000001,C_HAS_ZERO_DETECT=0,C_ROUND_OUTPUT=0,C_ROUND_PT=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF A: SIGNAL IS "xilinx.com:signal:data:1.0 a_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF B: SIGNAL IS "xilinx.com:signal:data:1.0 b_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF P: SIGNAL IS "xilinx.com:signal:data:1.0 p_intf DATA";
BEGIN
U0 : mult_gen_v12_0_12
GENERIC MAP (
C_VERBOSITY => 0,
C_MODEL_TYPE => 0,
C_OPTIMIZE_GOAL => 1,
C_XDEVICEFAMILY => "kintexu",
C_HAS_CE => 0,
C_HAS_SCLR => 0,
C_LATENCY => 4,
C_A_WIDTH => 17,
C_A_TYPE => 1,
C_B_WIDTH => 16,
C_B_TYPE => 1,
C_OUT_HIGH => 32,
C_OUT_LOW => 8,
C_MULT_TYPE => 0,
C_CE_OVERRIDES_SCLR => 0,
C_CCM_IMP => 0,
C_B_VALUE => "10000001",
C_HAS_ZERO_DETECT => 0,
C_ROUND_OUTPUT => 0,
C_ROUND_PT => 0
)
PORT MAP (
CLK => CLK,
A => A,
B => B,
CE => '1',
SCLR => '0',
P => P
);
END mul17_16_arch;
| bsd-3-clause | 6ff7aa8e77998457c76836e3cce4528d | 0.679189 | 3.357016 | false | false | false | false |
MartinCura/SistDig-TP4 | old/UART/data_adq/timing.vhd | 1 | 3,391 | -- --------------------------
-- TIMING
-- --------------------------
-- Top16 es el clk dividido "divisor" (para el ejemplo de 115200, divisor=27)
-- ClkDiv cuenta los rising edges de Top16, a los 16 pone un 1 en TopTx
-- TopTx es Top16 dividido 16 => clk dividido "divisor"*16
-- TopRx es Top16 dividido 8 => TopTx*2
--Bloque contador de una salida. Su salida se pone en 1 cuando el contador llega al valor indicado en cycles.
--necesito generar una señal muestreadora con una frecuencia de 16*BaudRate.
--elijo un baudrate de 19200 con un clock de 50Mhz, con lo cual cycles = 50e6/(16*19200) = 163
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
-- ----------------------------------------------------
Entity timing is
-- ----------------------------------------------------
generic (
F : natural; --La frecuencia va como 50e3 en lugar de e6
baud_rate: natural
);
port (
CLK : in std_logic;
RST : in std_logic;
ClrDiv : in std_logic;
Top16 : buffer std_logic;
TopTx : out std_logic;
TopRx : out std_logic
);
end timing;
-- ----------------------------------------------------
Architecture timing of timing is
-- ----------------------------------------------------
-- signal baud_value : natural;
constant max_div : natural := ((F*1000)/(16*baud_rate)); --La frecuencia va como 50e3 en lugar de e6
subtype div16_type is natural range 0 to max_div-1;
signal Div16 : div16_type;
signal ClkDiv : integer;
signal RxDiv : integer;
begin
-- --------------------------
-- Clk16 Clock Generation
-- --------------------------
process (RST, CLK)
begin
if RST='1' then
Top16 <= '0';
Div16 <= 0;
elsif rising_edge(CLK) then
Top16 <= '0';
if Div16 = max_div-1 then
Div16 <= 0;
Top16 <= '1';
else
Div16 <= Div16 + 1;
end if;
end if;
end process;
-- --------------------------
-- Tx Clock Generation
-- --------------------------
process (RST, CLK)
begin
if RST='1' then
TopTx <= '0';
ClkDiv <= 0; --(others=>'0');
elsif rising_edge(CLK) then
TopTx <= '0';
if Top16='1' then
ClkDiv <= ClkDiv + 1;
if ClkDiv = 15 then
TopTx <= '1';
ClkDiv <= 0;
end if;
end if;
end if;
end process;
-- ------------------------------
-- Rx Sampling Clock Generation
-- ------------------------------
process (RST, CLK)
begin
if RST='1' then
TopRx <= '0';
RxDiv <= 0;
elsif rising_edge(CLK) then
TopRx <= '0';
if ClrDiv='1' then
RxDiv <= 0;
elsif Top16='1' then
if RxDiv = 7 then
RxDiv <= 0;
TopRx <= '1';
else
RxDiv <= RxDiv + 1;
end if;
end if;
end if;
end process;
end architecture;
| gpl-3.0 | c017b2058d2224e24dbee94866674b68 | 0.417109 | 4.402597 | false | false | false | false |
MartinCura/SistDig-TP4 | src/cordic/cordic.vhd | 1 | 14,808 | -- Algoritmo CORDIC
-- (Rehecho de forma iterativa)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.MATH_REAL.all;
library work;
use work.cordic_lib.all;
entity cordic is
generic (
P : natural := 16 -- Cantidad de iteraciones, determina la precisión
);
port (
clk : in std_logic;
rst : in std_logic;
load : in std_logic;
x_in, y_in : in t_coord;
angle : in t_num;
x_rot, y_rot : out t_coord;
rotRdy : out std_logic
);
end entity cordic;
architecture cordic_arq of cordic is
constant N_K : natural := N_BITS / 2;
constant Nrom : natural := 32;
type t_angles is array(natural range <>) of std_logic_vector(N_BITS-1 downto 0);
constant ANGLES : t_angles(0 to Nrom-1) := ( -- Nrom primeros valores de atan(2^-i), convertidos
std_logic_vector(to_unsigned(integer(round(0.785398163397448278999490867136 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)),
std_logic_vector(to_unsigned(integer(round(0.463647609000806093515478778500 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)),
std_logic_vector(to_unsigned(integer(round(0.244978663126864143473326862477 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)),
std_logic_vector(to_unsigned(integer(round(0.124354994546761438156678991618 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)),
std_logic_vector(to_unsigned(integer(round(0.062418809995957350023054743815 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)),
std_logic_vector(to_unsigned(integer(round(0.031239833430268277442154456480 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)),
std_logic_vector(to_unsigned(integer(round(0.015623728620476831294161534913 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)),
std_logic_vector(to_unsigned(integer(round(0.007812341060101111143987306917 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)),
std_logic_vector(to_unsigned(integer(round(0.003906230131966971757390139075 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)),
std_logic_vector(to_unsigned(integer(round(0.001953122516478818758434155001 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)),
std_logic_vector(to_unsigned(integer(round(0.000976562189559319459436492750 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)),
std_logic_vector(to_unsigned(integer(round(0.000488281211194898289926213941 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)),
std_logic_vector(to_unsigned(integer(round(0.000244140620149361771244744812 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)),
std_logic_vector(to_unsigned(integer(round(0.000122070311893670207853065945 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)),
std_logic_vector(to_unsigned(integer(round(0.000061035156174208772593501454 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)),
std_logic_vector(to_unsigned(integer(round(0.000030517578115526095727154735 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)),
std_logic_vector(to_unsigned(integer(round(0.000015258789061315761542377868 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)),
std_logic_vector(to_unsigned(integer(round(0.000007629394531101969981038997 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)),
std_logic_vector(to_unsigned(integer(round(0.000003814697265606496141750756 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)),
std_logic_vector(to_unsigned(integer(round(0.000001907348632810186964779285 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)),
std_logic_vector(to_unsigned(integer(round(0.000000953674316405960844127631 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)),
std_logic_vector(to_unsigned(integer(round(0.000000476837158203088842281064 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)),
std_logic_vector(to_unsigned(integer(round(0.000000238418579101557973667688 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)),
std_logic_vector(to_unsigned(integer(round(0.000000119209289550780680899739 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)),
std_logic_vector(to_unsigned(integer(round(0.000000059604644775390552208106 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)),
std_logic_vector(to_unsigned(integer(round(0.000000029802322387695302573833 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)),
std_logic_vector(to_unsigned(integer(round(0.000000014901161193847654595639 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)),
std_logic_vector(to_unsigned(integer(round(0.000000007450580596923828125000 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)),
std_logic_vector(to_unsigned(integer(round(0.000000003725290298461914062500 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)),
std_logic_vector(to_unsigned(integer(round(0.000000001862645149230957031250 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)),
std_logic_vector(to_unsigned(integer(round(0.000000000931322574615478515625 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)),
std_logic_vector(to_unsigned(integer(round(0.000000000465661287307739257812 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS))
);
type t_kvalues is array(natural range <>) of std_logic_vector(N_K-1 downto 0);
constant K_VALUES : t_kvalues(0 to Nrom-1) := ( -- Nrom primeros cumprod(1 ./ abs(1 + 1j*2.^(-(0:25))))
std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.707106781186547461715008466854)), N_K)),
std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.632455532033675771330649695301)), N_K)),
std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.613571991077896283783843500714)), N_K)),
std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.608833912517752429138795378094)), N_K)),
std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607648256256168139977091868786)), N_K)),
std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607351770141295932425862247328)), N_K)),
std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607277644093526025592666428565)), N_K)),
std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607259112298892733683430833480)), N_K)),
std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607254479332562269178197311703)), N_K)),
std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607253321089875175431416209904)), N_K)),
std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607253031529134346122589249717)), N_K)),
std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607252959138944836681162087189)), N_K)),
std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607252941041397154009473524638)), N_K)),
std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607252936517010177830400152743)), N_K)),
std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607252935385913406030056194140)), N_K)),
std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607252935103139268591121435747)), N_K)),
std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607252935032445706475812130520)), N_K)),
std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607252935014772288191409188585)), N_K)),
std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607252935010353933620308453101)), N_K)),
std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607252935009249372733108884859)), N_K)),
std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607252935008973260266884608427)), N_K)),
std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607252935008904204394752923690)), N_K)),
std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607252935008886884915568771248)), N_K)),
std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607252935008882666068075195653)), N_K)),
std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607252935008881555845050570497)), N_K)),
std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607252935008881222778143182950)), N_K)),
std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607252935008881222778143182950)), N_K)),
std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607252935008881222778143182950)), N_K)),
std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607252935008881222778143182950)), N_K)),
std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607252935008881222778143182950)), N_K)),
std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607252935008881222778143182950)), N_K)),
std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607252935008881222778143182950)), N_K))
);
signal x_in_e, x_in_n, x0, x_1, x_2, x_2_sh, x_3, x_4 : t_coord_e := (others => '0');
signal y_in_e, y_in_n, y0, y_1, y_2, y_2_sh, y_3, y_4 : t_coord_e := (others => '0');
signal x_5, y_5 : std_logic_vector((N_EXTR+N_K)-1 downto 0) := (others => '0');
signal angle0, angle_1, angle_2, angle_3 : t_num := (others => '0');
subtype natural_i is natural range 0 to 31;
signal i : natural_i := P;
signal cuadrante : std_logic_vector(1 downto 0) := "00";
signal angle_i : std_logic_vector(N_BITS-1 downto 0) := (others => '0');
--signal angle_i : unsigned(N_BITS-1 downto 0) := (others => '0');
signal sigma : std_logic := '0';
signal ena_reg : std_logic := '0';
signal stRdy : std_logic := '0';
type t_estado is (IDLE, LOADING, ROTA, RDY);
signal estado : t_estado := IDLE;
begin
-- Extiendo coordenadas
x_in_e <= (N_EXTR-N_BITS-1 downto 0 => x_in(N_BITS-1)) & x_in;
y_in_e <= (N_EXTR-N_BITS-1 downto 0 => y_in(N_BITS-1)) & y_in;
-- Versiones negativas
x_in_n <= std_logic_vector(signed(not x_in_e) + 1);
y_in_n <= std_logic_vector(signed(not y_in_e) + 1);
-- Iterador
process(clk, rst, load)
begin
if rst = '1' then
i <= P;
estado <= IDLE;
elsif rising_edge(clk) then
if load = '1' then
-- Cargo nueva posición para rotar
estado <= LOADING;
i <= 0;
elsif i < P-2 then
-- Sigo rotando
estado <= ROTA;
i <= i + 1;
elsif i = P-2 then
-- Terminé de rotar posición
estado <= RDY;
i <= i + 1;
else
estado <= IDLE;
end if;
end if;
end process;
ena_reg <= '1' when (estado = LOADING or estado = ROTA or load = '1') else '0';
stRdy <= '1' when (estado = RDY) else '0';
-- Averiguo cuadrante con los 2 MSBs del ángulo
cuadrante <= angle(N_BITS-1 downto N_BITS-2);
-- Rotación inicial (pongo en el cuadrante correcto)
x0 <= x_in_e when cuadrante = "00" else
y_in_n when cuadrante = "01" else
x_in_n when cuadrante = "10" else
y_in_e when cuadrante = "11";
y0 <= y_in_e when cuadrante = "00" else
x_in_e when cuadrante = "01" else
y_in_n when cuadrante = "10" else
x_in_n when cuadrante = "11";
angle0 <= "00" & angle(N_BITS-3 downto 0);
-- Uso pos nueva si cargando o sigo rotando
x_1 <= x0 when load = '1' else
x_3;
y_1 <= y0 when load = '1' else
y_3;
angle_1 <= angle0 when load = '1' else
angle_3;
-- ...
reg_x: entity work.registroNb
generic map(
N => N_EXTR
) port map(
clk => clk,
rst => rst,
ena => ena_reg,
d => x_1,
q => x_2
);
reg_y: entity work.registroNb
generic map(
N => N_EXTR
) port map(
clk => clk,
rst => rst,
ena => ena_reg,
d => y_1,
q => y_2
);
reg_angle: entity work.registroNb
generic map(
N => N_BITS
) port map(
clk => clk,
rst => rst,
ena => ena_reg,
d => angle_1,
q => angle_2
);
-- ...
bshift_x: entity work.barrel_shifterNb
generic map(
N => N_EXTR
) port map(
to_left => '0',
M => i,
a => x_2,
o => x_2_sh
);
bshift_y: entity work.barrel_shifterNb
generic map(
N => N_EXTR
) port map(
to_left => '0',
M => i,
a => y_2,
o => y_2_sh
);
-- ...
x_3 <= std_logic_vector(unsigned(x_2) + unsigned(y_2_sh)) when sigma = '1' else
std_logic_vector(unsigned(x_2) - unsigned(y_2_sh));
y_3 <= std_logic_vector(unsigned(y_2) + unsigned(x_2_sh)) when sigma = '0' else
std_logic_vector(unsigned(y_2) - unsigned(x_2_sh));
angle_i <= ANGLES(i); ----ANGLES_DEG(i);---- when (i < ANGLES'length) else
----(angle(ANGLES'length-1) / (2**(i - ANGLES'length + 1)));
------ Si me paso de la tabla, aproximo
angle_3 <= std_logic_vector(unsigned(angle_2) + unsigned(angle_i)) when sigma = '1' else
std_logic_vector(unsigned(angle_2) - unsigned(angle_i));
-- Signo del ángulo de rotación restante
sigma <= angle_2(N_BITS-1) when (estado = ROTA) else '0';
-- ...
pipe_reg_x: entity work.registroNb
generic map(
N => N_EXTR
) port map(
clk => clk,
rst => rst,
ena => '1',
d => x_3,
q => x_4
);
pipe_reg_y: entity work.registroNb
generic map(
N => N_EXTR
) port map(
clk => clk,
rst => rst,
ena => '1',
d => y_3,
q => y_4
);
-- ...
delay_Rdy: entity work.ffd
port map(
clk => clk,
rst => rst,
ena => '1',
d => stRdy,
q => rotRdy
);
-- Intermedio
x_5 <= std_logic_vector( signed(x_4) * signed(K_VALUES(i)) );
y_5 <= std_logic_vector( signed(y_4) * signed(K_VALUES(i)) );
-- Salida de la rotación (si rotRdy)
x_rot <= x_5(N_EXTR+N_K-3 downto N_EXTR+N_K-3-N_BITS+1);
y_rot <= y_5(N_EXTR+N_K-3 downto N_EXTR+N_K-3-N_BITS+1);
end cordic_arq;
| gpl-3.0 | c81952ffbb1d1174a9d040df1de9fb5e | 0.575647 | 2.889301 | false | false | false | false |
MartinCura/SistDig-TP4 | old/ram_interna.vhd | 1 | 2,618 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.cordic_lib.all;
---use work.float_pkg.all;
--library ieee_proposed;
--use ieee_proposed.float_pkg.all;
library floatfixlib;
use floatfixlib.float_pkg.all;
-- RAM interna que recibe svl's de forma serial y los guarda como posiciones de 3 coordenadas; también lee
---Actualmente debería recibir precisamente (o más) CANT_P puntos. Podría cambiarla para que sepa la cantidad que contiene
entity ram_interna is
generic(
N_BITS : integer := 32; -- Cantidad de bits por coordenada
CANT_P : integer := 100;---1000; -- Cantidad de puntos ---12 MIL
REFR_R : integer := 100 -- Ciclos por dato que saco
);
port(
clk: in std_logic;
rst: in std_logic;
Rx: in std_logic;
Din: in std_logic_vector(15 downto 0);
Dout: out t_pos_mem;
Rdy: out std_logic := '0';
barrido: out std_logic := '0'
);
end entity;
architecture ram_interna_arq of ram_interna is
signal n : integer := 0;
constant ram_size : integer := 3 * CANT_P;
subtype t_ram_elem is std_logic_vector(15 downto 0);---t_coordenada;
type t_ram is array(1 to ram_size) of t_ram_elem;
signal ram : t_ram := (others => (others => '0'));
---shared variable ram: t_ram;
signal Dout_aux : t_pos_mem := (others => (others => '0'));
begin
-- IN
process(Rx, Din, n, rst)
variable j_in : natural := 1;
begin
-- Reseteo
if rst = '1' then
ram <= (others => (others => '0'));
ram(1) <= "0000000000000001";
ram(2) <= "0000000000000001";
ram(3) <= "0000000000000001";
j_in := 1;
elsif Rx = '1' then
---if Rx = '1' then
if j_in > ram_size then
j_in := 1;
end if;
ram(j_in) <= Din;
j_in := j_in + 1;
if n < ram_size then
n <= n + 1;
end if;
end if;
end process;
-- OUT
process(clk)
variable i : natural := 0;
variable j_out : natural := ram_size;
begin
if rising_edge(clk) then
i := i + 1;
if i = REFR_R then
barrido <= '0';
i := 0;
if j_out > n then
j_out := 1;
Dout_aux(1) <= ram(j_out);
Dout_aux(2) <= ram(j_out+1);
Dout_aux(3) <= ram(j_out+2);
else
j_out := j_out + 3;
if j_out > n then
barrido <= '1';
else
Dout_aux(1) <= ram(j_out);
Dout_aux(2) <= ram(j_out+1);
Dout_aux(3) <= ram(j_out+2);
end if;
end if;
Rdy <= '1';
else
Rdy <= '0'; ---Chequear que funcione
end if;
end if;
end process;
Dout <= Dout_aux;
----Analizar problemas con el tiempo intermedio entre fin de lectura y barrido
end;
| gpl-3.0 | a6b9d5a9e5d12218ce42f329d1ea79fe | 0.581484 | 2.686536 | false | false | false | false |
kuba-moo/VHDL-lib | bus_append.vhd | 1 | 2,788 | -- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- Generic bus append module
-- Appends Value (N_BYTES long) after packet on the bus
-- Value is latched with InPkt, what is seen on the last cycle
-- with InPkt high will be transmitted byte by byte onto the wire
-- NOTE: Transmission is big endian
--
-- WARNING: Pkt signal must be (and is kept) continuous
entity bus_append is
generic (N_BYTES : integer);
port (Clk : in std_logic;
Rst : in std_logic;
Value : in std_logic_vector (N_BYTES*8 - 1 downto 0);
InPkt : in std_logic;
InData : in std_logic_vector (7 downto 0);
OutPkt : out std_logic;
OutData : out std_logic_vector (7 downto 0));
end bus_append;
architecture Behavioral of bus_append is
constant UBIT : integer := N_BYTES * 8 - 1;
begin
main : process (Clk)
variable delayPkt : std_logic;
variable delayData : std_logic_vector(7 downto 0);
variable saveValue : std_logic_vector (UBIT downto 0);
variable write_out : std_logic := '0';
variable write_cnt : integer range 0 to N_BYTES - 1;
begin
if RISING_EDGE(Clk) then
OutPkt <= delayPkt;
OutData <= delayData;
if write_out = '1' then
OutPkt <= '1';
OutData <= saveValue(UBIT - write_cnt*8 downto UBIT - 7 - write_cnt*8);
if write_cnt = N_BYTES - 1 then
write_out := '0';
end if;
write_cnt := write_cnt + 1;
end if;
if InPkt = '1' then
saveValue := Value;
end if;
if delayPkt = '1' and InPkt = '0' then
write_out := '1';
write_cnt := 0;
end if;
delayPkt := InPkt;
delayData := InData;
if rst = '1' then
write_out := '0';
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 53113ec9c0511b23ba8273fbd008a11b | 0.586083 | 3.949008 | false | false | false | false |
varunnagpaal/Digital-Hardware-Modelling | vhdl/filter/fir_picoblaze/fir_filter_picoblaze_program.vhd | 1 | 232,456 | --
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
--
-- Definition of a program memory for KCPSM6 including generic parameters for the
-- convenient selection of device family, program memory size and the ability to include
-- the JTAG Loader hardware for rapid software development.
--
-- This file is primarily for use during code development and it is recommended that the
-- appropriate simplified program memory definition be used in a final production design.
--
-- Generic Values Comments
-- Parameter Supported
--
-- C_FAMILY "S6" Spartan-6 device
-- "V6" Virtex-6 device
-- "7S" 7-Series device
-- (Artix-7, Kintex-7, Virtex-7 or Zynq)
--
-- C_RAM_SIZE_KWORDS 1, 2 or 4 Size of program memory in K-instructions
--
-- C_JTAG_LOADER_ENABLE 0 or 1 Set to '1' to include JTAG Loader
--
-- Notes
--
-- If your design contains MULTIPLE KCPSM6 instances then only one should have the
-- JTAG Loader enabled at a time (i.e. make sure that C_JTAG_LOADER_ENABLE is only set to
-- '1' on one instance of the program memory). Advanced users may be interested to know
-- that it is possible to connect JTAG Loader to multiple memories and then to use the
-- JTAG Loader utility to specify which memory contents are to be modified. However,
-- this scheme does require some effort to set up and the additional connectivity of the
-- multiple BRAMs can impact the placement, routing and performance of the complete
-- design. Please contact the author at Xilinx for more detailed information.
--
-- Regardless of the size of program memory specified by C_RAM_SIZE_KWORDS, the complete
-- 12-bit address bus is connected to KCPSM6. This enables the generic to be modified
-- without requiring changes to the fundamental hardware definition. However, when the
-- program memory is 1K then only the lower 10-bits of the address are actually used and
-- the valid address range is 000 to 3FF hex. Likewise, for a 2K program only the lower
-- 11-bits of the address are actually used and the valid address range is 000 to 7FF hex.
--
-- Programs are stored in Block Memory (BRAM) and the number of BRAM used depends on the
-- size of the program and the device family.
--
-- In a Spartan-6 device a BRAM is capable of holding 1K instructions. Hence a 2K program
-- will require 2 BRAMs to be used and a 4K program will require 4 BRAMs to be used. It
-- should be noted that a 4K program is not such a natural fit in a Spartan-6 device and
-- the implementation also requires a small amount of logic resulting in slightly lower
-- performance. A Spartan-6 BRAM can also be split into two 9k-bit memories suggesting
-- that a program containing up to 512 instructions could be implemented. However, there
-- is a silicon errata which makes this unsuitable and therefore it is not supported by
-- this file.
--
-- In a Virtex-6 or any 7-Series device a BRAM is capable of holding 2K instructions so
-- obviously a 2K program requires only a single BRAM. Each BRAM can also be divided into
-- 2 smaller memories supporting programs of 1K in half of a 36k-bit BRAM (generally
-- reported as being an 18k-bit BRAM). For a program of 4K instructions, 2 BRAMs are used.
--
--
-- Program defined by 'D:\github\Embedded\Project\fir_filter_picoblaze_program.psm'.
--
-- Generated by KCPSM6 Assembler: 10 Dec 2018 - 18:14:54.
--
-- Assembler used ROM_form template: ROM_form_JTAGLoader_14March13.vhd
--
-- Standard IEEE libraries
--
--
package jtag_loader_pkg is
function addr_width_calc (size_in_k: integer) return integer;
end jtag_loader_pkg;
--
package body jtag_loader_pkg is
function addr_width_calc (size_in_k: integer) return integer is
begin
if (size_in_k = 1) then return 10;
elsif (size_in_k = 2) then return 11;
elsif (size_in_k = 4) then return 12;
else report "Invalid BlockRAM size. Please set to 1, 2 or 4 K words." severity FAILURE;
end if;
return 0;
end function addr_width_calc;
end package body;
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.jtag_loader_pkg.ALL;
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
--
entity fir_filter_picoblaze_program is
generic( C_FAMILY : string := "S6";
C_RAM_SIZE_KWORDS : integer := 1;
C_JTAG_LOADER_ENABLE : integer := 0);
Port ( address : in std_logic_vector(11 downto 0);
instruction : out std_logic_vector(17 downto 0);
enable : in std_logic;
rdl : out std_logic;
clk : in std_logic);
end fir_filter_picoblaze_program;
--
architecture low_level_definition of fir_filter_picoblaze_program is
--
signal address_a : std_logic_vector(15 downto 0);
signal pipe_a11 : std_logic;
signal data_in_a : std_logic_vector(35 downto 0);
signal data_out_a : std_logic_vector(35 downto 0);
signal data_out_a_l : std_logic_vector(35 downto 0);
signal data_out_a_h : std_logic_vector(35 downto 0);
signal data_out_a_ll : std_logic_vector(35 downto 0);
signal data_out_a_lh : std_logic_vector(35 downto 0);
signal data_out_a_hl : std_logic_vector(35 downto 0);
signal data_out_a_hh : std_logic_vector(35 downto 0);
signal address_b : std_logic_vector(15 downto 0);
signal data_in_b : std_logic_vector(35 downto 0);
signal data_in_b_l : std_logic_vector(35 downto 0);
signal data_in_b_ll : std_logic_vector(35 downto 0);
signal data_in_b_hl : std_logic_vector(35 downto 0);
signal data_out_b : std_logic_vector(35 downto 0);
signal data_out_b_l : std_logic_vector(35 downto 0);
signal data_out_b_ll : std_logic_vector(35 downto 0);
signal data_out_b_hl : std_logic_vector(35 downto 0);
signal data_in_b_h : std_logic_vector(35 downto 0);
signal data_in_b_lh : std_logic_vector(35 downto 0);
signal data_in_b_hh : std_logic_vector(35 downto 0);
signal data_out_b_h : std_logic_vector(35 downto 0);
signal data_out_b_lh : std_logic_vector(35 downto 0);
signal data_out_b_hh : std_logic_vector(35 downto 0);
signal enable_b : std_logic;
signal clk_b : std_logic;
signal we_b : std_logic_vector(7 downto 0);
signal we_b_l : std_logic_vector(3 downto 0);
signal we_b_h : std_logic_vector(3 downto 0);
--
signal jtag_addr : std_logic_vector(11 downto 0);
signal jtag_we : std_logic;
signal jtag_we_l : std_logic;
signal jtag_we_h : std_logic;
signal jtag_clk : std_logic;
signal jtag_din : std_logic_vector(17 downto 0);
signal jtag_dout : std_logic_vector(17 downto 0);
signal jtag_dout_1 : std_logic_vector(17 downto 0);
signal jtag_en : std_logic_vector(0 downto 0);
--
signal picoblaze_reset : std_logic_vector(0 downto 0);
signal rdl_bus : std_logic_vector(0 downto 0);
--
constant BRAM_ADDRESS_WIDTH : integer := addr_width_calc(C_RAM_SIZE_KWORDS);
--
--
component jtag_loader_6
generic( C_JTAG_LOADER_ENABLE : integer := 1;
C_FAMILY : string := "V6";
C_NUM_PICOBLAZE : integer := 1;
C_BRAM_MAX_ADDR_WIDTH : integer := 10;
C_PICOBLAZE_INSTRUCTION_DATA_WIDTH : integer := 18;
C_JTAG_CHAIN : integer := 2;
C_ADDR_WIDTH_0 : integer := 10;
C_ADDR_WIDTH_1 : integer := 10;
C_ADDR_WIDTH_2 : integer := 10;
C_ADDR_WIDTH_3 : integer := 10;
C_ADDR_WIDTH_4 : integer := 10;
C_ADDR_WIDTH_5 : integer := 10;
C_ADDR_WIDTH_6 : integer := 10;
C_ADDR_WIDTH_7 : integer := 10);
port( picoblaze_reset : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
jtag_en : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
jtag_din : out STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_addr : out STD_LOGIC_VECTOR(C_BRAM_MAX_ADDR_WIDTH-1 downto 0);
jtag_clk : out std_logic;
jtag_we : out std_logic;
jtag_dout_0 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_1 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_2 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_3 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_4 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_5 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_6 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_7 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0));
end component;
--
begin
--
--
ram_1k_generate : if (C_RAM_SIZE_KWORDS = 1) generate
s6: if (C_FAMILY = "S6") generate
--
address_a(13 downto 0) <= address(9 downto 0) & "0000";
instruction <= data_out_a(33 downto 32) & data_out_a(15 downto 0);
data_in_a <= "0000000000000000000000000000000000" & address(11 downto 10);
jtag_dout <= data_out_b(33 downto 32) & data_out_b(15 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b <= "00" & data_out_b(33 downto 32) & "0000000000000000" & data_out_b(15 downto 0);
address_b(13 downto 0) <= "00000000000000";
we_b(3 downto 0) <= "0000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b <= "00" & jtag_din(17 downto 16) & "0000000000000000" & jtag_din(15 downto 0);
address_b(13 downto 0) <= jtag_addr(9 downto 0) & "0000";
we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB16BWER
generic map ( DATA_WIDTH_A => 18,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 18,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"B020200CD001900020053B001A01000C1000DFFF4BA0202E00051A121B001F00",
INIT_01 => X"1124110B11E611EA1107110F110311FC11FF110011FE11FF110211015000D101",
INIT_02 => X"000000001FFF1101110211FF11FE110011FF11FC1103110F110711EA11E6110B",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"00000000000000000000000000000000000000000AAAAAAAAAAAAAAAB096DA80",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a(31 downto 0),
DOPA => data_out_a(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b(31 downto 0),
DOPB => data_out_b(35 downto 32),
DIB => data_in_b(31 downto 0),
DIPB => data_in_b(35 downto 32),
WEB => we_b(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
end generate s6;
--
--
v6 : if (C_FAMILY = "V6") generate
--
address_a(13 downto 0) <= address(9 downto 0) & "1111";
instruction <= data_out_a(17 downto 0);
data_in_a(17 downto 0) <= "0000000000000000" & address(11 downto 10);
jtag_dout <= data_out_b(17 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b(17 downto 0) <= data_out_b(17 downto 0);
address_b(13 downto 0) <= "11111111111111";
we_b(3 downto 0) <= "0000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b(17 downto 0) <= jtag_din(17 downto 0);
address_b(13 downto 0) <= jtag_addr(9 downto 0) & "1111";
we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB18E1
generic map ( READ_WIDTH_A => 18,
WRITE_WIDTH_A => 18,
DOA_REG => 0,
INIT_A => "000000000000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 18,
WRITE_WIDTH_B => 18,
DOB_REG => 0,
INIT_B => X"000000000000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
SIM_DEVICE => "VIRTEX6",
INIT_00 => X"B020200CD001900020053B001A01000C1000DFFF4BA0202E00051A121B001F00",
INIT_01 => X"1124110B11E611EA1107110F110311FC11FF110011FE11FF110211015000D101",
INIT_02 => X"000000001FFF1101110211FF11FE110011FF11FC1103110F110711EA11E6110B",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"00000000000000000000000000000000000000000AAAAAAAAAAAAAAAB096DA80",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRARDADDR => address_a(13 downto 0),
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a(15 downto 0),
DOPADOP => data_out_a(17 downto 16),
DIADI => data_in_a(15 downto 0),
DIPADIP => data_in_a(17 downto 16),
WEA => "00",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b(13 downto 0),
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b(15 downto 0),
DOPBDOP => data_out_b(17 downto 16),
DIBDI => data_in_b(15 downto 0),
DIPBDIP => data_in_b(17 downto 16),
WEBWE => we_b(3 downto 0),
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0');
--
end generate v6;
--
--
akv7 : if (C_FAMILY = "7S") generate
--
address_a(13 downto 0) <= address(9 downto 0) & "1111";
instruction <= data_out_a(17 downto 0);
data_in_a(17 downto 0) <= "0000000000000000" & address(11 downto 10);
jtag_dout <= data_out_b(17 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b(17 downto 0) <= data_out_b(17 downto 0);
address_b(13 downto 0) <= "11111111111111";
we_b(3 downto 0) <= "0000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b(17 downto 0) <= jtag_din(17 downto 0);
address_b(13 downto 0) <= jtag_addr(9 downto 0) & "1111";
we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB18E1
generic map ( READ_WIDTH_A => 18,
WRITE_WIDTH_A => 18,
DOA_REG => 0,
INIT_A => "000000000000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 18,
WRITE_WIDTH_B => 18,
DOB_REG => 0,
INIT_B => X"000000000000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
SIM_DEVICE => "7SERIES",
INIT_00 => X"B020200CD001900020053B001A01000C1000DFFF4BA0202E00051A121B001F00",
INIT_01 => X"1124110B11E611EA1107110F110311FC11FF110011FE11FF110211015000D101",
INIT_02 => X"000000001FFF1101110211FF11FE110011FF11FC1103110F110711EA11E6110B",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"00000000000000000000000000000000000000000AAAAAAAAAAAAAAAB096DA80",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRARDADDR => address_a(13 downto 0),
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a(15 downto 0),
DOPADOP => data_out_a(17 downto 16),
DIADI => data_in_a(15 downto 0),
DIPADIP => data_in_a(17 downto 16),
WEA => "00",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b(13 downto 0),
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b(15 downto 0),
DOPBDOP => data_out_b(17 downto 16),
DIBDI => data_in_b(15 downto 0),
DIPBDIP => data_in_b(17 downto 16),
WEBWE => we_b(3 downto 0),
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0');
--
end generate akv7;
--
end generate ram_1k_generate;
--
--
--
ram_2k_generate : if (C_RAM_SIZE_KWORDS = 2) generate
--
--
s6: if (C_FAMILY = "S6") generate
--
address_a(13 downto 0) <= address(10 downto 0) & "000";
instruction <= data_out_a_h(32) & data_out_a_h(7 downto 0) & data_out_a_l(32) & data_out_a_l(7 downto 0);
data_in_a <= "00000000000000000000000000000000000" & address(11);
jtag_dout <= data_out_b_h(32) & data_out_b_h(7 downto 0) & data_out_b_l(32) & data_out_b_l(7 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b_l <= "000" & data_out_b_l(32) & "000000000000000000000000" & data_out_b_l(7 downto 0);
data_in_b_h <= "000" & data_out_b_h(32) & "000000000000000000000000" & data_out_b_h(7 downto 0);
address_b(13 downto 0) <= "00000000000000";
we_b(3 downto 0) <= "0000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b_h <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9);
data_in_b_l <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0);
address_b(13 downto 0) <= jtag_addr(10 downto 0) & "000";
we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom_l: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"240BE6EA070F03FCFF00FEFF02010001200C01000500010C00FFA02E05120000",
INIT_01 => X"000000000000000000000000000000000000FF0102FFFE00FFFC030F07EAE60B",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"00000000000000000000000000000000000000000000000000003FFFFFFD0463",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_l(31 downto 0),
DOPA => data_out_a_l(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_l(31 downto 0),
DOPB => data_out_b_l(35 downto 32),
DIB => data_in_b_l(31 downto 0),
DIPB => data_in_b_l(35 downto 32),
WEB => we_b(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
kcpsm6_rom_h: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"0808080808080808080808080808286858906848109D8D0088EF2510000D0D0F",
INIT_01 => X"0000000000000000000000000000000000000F08080808080808080808080808",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"00000000000000000000000000000000000000000000000000003FFFFFFFC9B8",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_h(31 downto 0),
DOPA => data_out_a_h(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_h(31 downto 0),
DOPB => data_out_b_h(35 downto 32),
DIB => data_in_b_h(31 downto 0),
DIPB => data_in_b_h(35 downto 32),
WEB => we_b(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
end generate s6;
--
--
v6 : if (C_FAMILY = "V6") generate
--
address_a <= '1' & address(10 downto 0) & "1111";
instruction <= data_out_a(33 downto 32) & data_out_a(15 downto 0);
data_in_a <= "00000000000000000000000000000000000" & address(11);
jtag_dout <= data_out_b(33 downto 32) & data_out_b(15 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b <= "00" & data_out_b(33 downto 32) & "0000000000000000" & data_out_b(15 downto 0);
address_b <= "1111111111111111";
we_b <= "00000000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b <= "00" & jtag_din(17 downto 16) & "0000000000000000" & jtag_din(15 downto 0);
address_b <= '1' & jtag_addr(10 downto 0) & "1111";
we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB36E1
generic map ( READ_WIDTH_A => 18,
WRITE_WIDTH_A => 18,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 18,
WRITE_WIDTH_B => 18,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "VIRTEX6",
INIT_00 => X"B020200CD001900020053B001A01000C1000DFFF4BA0202E00051A121B001F00",
INIT_01 => X"1124110B11E611EA1107110F110311FC11FF110011FE11FF110211015000D101",
INIT_02 => X"000000001FFF1101110211FF11FE110011FF11FC1103110F110711EA11E6110B",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"00000000000000000000000000000000000000000AAAAAAAAAAAAAAAB096DA80",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a(31 downto 0),
DOPADOP => data_out_a(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b(31 downto 0),
DOPBDOP => data_out_b(35 downto 32),
DIBDI => data_in_b(31 downto 0),
DIPBDIP => data_in_b(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
end generate v6;
--
--
akv7 : if (C_FAMILY = "7S") generate
--
address_a <= '1' & address(10 downto 0) & "1111";
instruction <= data_out_a(33 downto 32) & data_out_a(15 downto 0);
data_in_a <= "00000000000000000000000000000000000" & address(11);
jtag_dout <= data_out_b(33 downto 32) & data_out_b(15 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b <= "00" & data_out_b(33 downto 32) & "0000000000000000" & data_out_b(15 downto 0);
address_b <= "1111111111111111";
we_b <= "00000000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b <= "00" & jtag_din(17 downto 16) & "0000000000000000" & jtag_din(15 downto 0);
address_b <= '1' & jtag_addr(10 downto 0) & "1111";
we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB36E1
generic map ( READ_WIDTH_A => 18,
WRITE_WIDTH_A => 18,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 18,
WRITE_WIDTH_B => 18,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "7SERIES",
INIT_00 => X"B020200CD001900020053B001A01000C1000DFFF4BA0202E00051A121B001F00",
INIT_01 => X"1124110B11E611EA1107110F110311FC11FF110011FE11FF110211015000D101",
INIT_02 => X"000000001FFF1101110211FF11FE110011FF11FC1103110F110711EA11E6110B",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"00000000000000000000000000000000000000000AAAAAAAAAAAAAAAB096DA80",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a(31 downto 0),
DOPADOP => data_out_a(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b(31 downto 0),
DOPBDOP => data_out_b(35 downto 32),
DIBDI => data_in_b(31 downto 0),
DIPBDIP => data_in_b(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
end generate akv7;
--
end generate ram_2k_generate;
--
--
ram_4k_generate : if (C_RAM_SIZE_KWORDS = 4) generate
s6: if (C_FAMILY = "S6") generate
--
address_a(13 downto 0) <= address(10 downto 0) & "000";
data_in_a <= "000000000000000000000000000000000000";
--
s6_a11_flop: FD
port map ( D => address(11),
Q => pipe_a11,
C => clk);
--
s6_4k_mux0_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_ll(0),
I1 => data_out_a_hl(0),
I2 => data_out_a_ll(1),
I3 => data_out_a_hl(1),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(0),
O6 => instruction(1));
--
s6_4k_mux2_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_ll(2),
I1 => data_out_a_hl(2),
I2 => data_out_a_ll(3),
I3 => data_out_a_hl(3),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(2),
O6 => instruction(3));
--
s6_4k_mux4_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_ll(4),
I1 => data_out_a_hl(4),
I2 => data_out_a_ll(5),
I3 => data_out_a_hl(5),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(4),
O6 => instruction(5));
--
s6_4k_mux6_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_ll(6),
I1 => data_out_a_hl(6),
I2 => data_out_a_ll(7),
I3 => data_out_a_hl(7),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(6),
O6 => instruction(7));
--
s6_4k_mux8_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_ll(32),
I1 => data_out_a_hl(32),
I2 => data_out_a_lh(0),
I3 => data_out_a_hh(0),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(8),
O6 => instruction(9));
--
s6_4k_mux10_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_lh(1),
I1 => data_out_a_hh(1),
I2 => data_out_a_lh(2),
I3 => data_out_a_hh(2),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(10),
O6 => instruction(11));
--
s6_4k_mux12_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_lh(3),
I1 => data_out_a_hh(3),
I2 => data_out_a_lh(4),
I3 => data_out_a_hh(4),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(12),
O6 => instruction(13));
--
s6_4k_mux14_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_lh(5),
I1 => data_out_a_hh(5),
I2 => data_out_a_lh(6),
I3 => data_out_a_hh(6),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(14),
O6 => instruction(15));
--
s6_4k_mux16_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_lh(7),
I1 => data_out_a_hh(7),
I2 => data_out_a_lh(32),
I3 => data_out_a_hh(32),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(16),
O6 => instruction(17));
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b_ll <= "000" & data_out_b_ll(32) & "000000000000000000000000" & data_out_b_ll(7 downto 0);
data_in_b_lh <= "000" & data_out_b_lh(32) & "000000000000000000000000" & data_out_b_lh(7 downto 0);
data_in_b_hl <= "000" & data_out_b_hl(32) & "000000000000000000000000" & data_out_b_hl(7 downto 0);
data_in_b_hh <= "000" & data_out_b_hh(32) & "000000000000000000000000" & data_out_b_hh(7 downto 0);
address_b(13 downto 0) <= "00000000000000";
we_b_l(3 downto 0) <= "0000";
we_b_h(3 downto 0) <= "0000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
jtag_dout <= data_out_b_lh(32) & data_out_b_lh(7 downto 0) & data_out_b_ll(32) & data_out_b_ll(7 downto 0);
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b_lh <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9);
data_in_b_ll <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0);
data_in_b_hh <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9);
data_in_b_hl <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0);
address_b(13 downto 0) <= jtag_addr(10 downto 0) & "000";
--
s6_4k_jtag_we_lut: LUT6_2
generic map (INIT => X"8000000020000000")
port map( I0 => jtag_we,
I1 => jtag_addr(11),
I2 => '1',
I3 => '1',
I4 => '1',
I5 => '1',
O5 => jtag_we_l,
O6 => jtag_we_h);
--
we_b_l(3 downto 0) <= jtag_we_l & jtag_we_l & jtag_we_l & jtag_we_l;
we_b_h(3 downto 0) <= jtag_we_h & jtag_we_h & jtag_we_h & jtag_we_h;
--
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
--
s6_4k_jtag_mux0_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_ll(0),
I1 => data_out_b_hl(0),
I2 => data_out_b_ll(1),
I3 => data_out_b_hl(1),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(0),
O6 => jtag_dout(1));
--
s6_4k_jtag_mux2_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_ll(2),
I1 => data_out_b_hl(2),
I2 => data_out_b_ll(3),
I3 => data_out_b_hl(3),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(2),
O6 => jtag_dout(3));
--
s6_4k_jtag_mux4_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_ll(4),
I1 => data_out_b_hl(4),
I2 => data_out_b_ll(5),
I3 => data_out_b_hl(5),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(4),
O6 => jtag_dout(5));
--
s6_4k_jtag_mux6_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_ll(6),
I1 => data_out_b_hl(6),
I2 => data_out_b_ll(7),
I3 => data_out_b_hl(7),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(6),
O6 => jtag_dout(7));
--
s6_4k_jtag_mux8_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_ll(32),
I1 => data_out_b_hl(32),
I2 => data_out_b_lh(0),
I3 => data_out_b_hh(0),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(8),
O6 => jtag_dout(9));
--
s6_4k_jtag_mux10_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_lh(1),
I1 => data_out_b_hh(1),
I2 => data_out_b_lh(2),
I3 => data_out_b_hh(2),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(10),
O6 => jtag_dout(11));
--
s6_4k_jtag_mux12_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_lh(3),
I1 => data_out_b_hh(3),
I2 => data_out_b_lh(4),
I3 => data_out_b_hh(4),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(12),
O6 => jtag_dout(13));
--
s6_4k_jtag_mux14_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_lh(5),
I1 => data_out_b_hh(5),
I2 => data_out_b_lh(6),
I3 => data_out_b_hh(6),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(14),
O6 => jtag_dout(15));
--
s6_4k_jtag_mux16_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_lh(7),
I1 => data_out_b_hh(7),
I2 => data_out_b_lh(32),
I3 => data_out_b_hh(32),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(16),
O6 => jtag_dout(17));
--
end generate loader;
--
kcpsm6_rom_ll: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"240BE6EA070F03FCFF00FEFF02010001200C01000500010C00FFA02E05120000",
INIT_01 => X"000000000000000000000000000000000000FF0102FFFE00FFFC030F07EAE60B",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"00000000000000000000000000000000000000000000000000003FFFFFFD0463",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_ll(31 downto 0),
DOPA => data_out_a_ll(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_ll(31 downto 0),
DOPB => data_out_b_ll(35 downto 32),
DIB => data_in_b_ll(31 downto 0),
DIPB => data_in_b_ll(35 downto 32),
WEB => we_b_l(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
kcpsm6_rom_lh: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"0808080808080808080808080808286858906848109D8D0088EF2510000D0D0F",
INIT_01 => X"0000000000000000000000000000000000000F08080808080808080808080808",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"00000000000000000000000000000000000000000000000000003FFFFFFFC9B8",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_lh(31 downto 0),
DOPA => data_out_a_lh(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_lh(31 downto 0),
DOPB => data_out_b_lh(35 downto 32),
DIB => data_in_b_lh(31 downto 0),
DIPB => data_in_b_lh(35 downto 32),
WEB => we_b_l(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
kcpsm6_rom_hl: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_hl(31 downto 0),
DOPA => data_out_a_hl(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_hl(31 downto 0),
DOPB => data_out_b_hl(35 downto 32),
DIB => data_in_b_hl(31 downto 0),
DIPB => data_in_b_hl(35 downto 32),
WEB => we_b_h(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
kcpsm6_rom_hh: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_hh(31 downto 0),
DOPA => data_out_a_hh(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_hh(31 downto 0),
DOPB => data_out_b_hh(35 downto 32),
DIB => data_in_b_hh(31 downto 0),
DIPB => data_in_b_hh(35 downto 32),
WEB => we_b_h(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
end generate s6;
--
--
v6 : if (C_FAMILY = "V6") generate
--
address_a <= '1' & address(11 downto 0) & "111";
instruction <= data_out_a_h(32) & data_out_a_h(7 downto 0) & data_out_a_l(32) & data_out_a_l(7 downto 0);
data_in_a <= "000000000000000000000000000000000000";
jtag_dout <= data_out_b_h(32) & data_out_b_h(7 downto 0) & data_out_b_l(32) & data_out_b_l(7 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b_l <= "000" & data_out_b_l(32) & "000000000000000000000000" & data_out_b_l(7 downto 0);
data_in_b_h <= "000" & data_out_b_h(32) & "000000000000000000000000" & data_out_b_h(7 downto 0);
address_b <= "1111111111111111";
we_b <= "00000000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b_h <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9);
data_in_b_l <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0);
address_b <= '1' & jtag_addr(11 downto 0) & "111";
we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom_l: RAMB36E1
generic map ( READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "VIRTEX6",
INIT_00 => X"240BE6EA070F03FCFF00FEFF02010001200C01000500010C00FFA02E05120000",
INIT_01 => X"000000000000000000000000000000000000FF0102FFFE00FFFC030F07EAE60B",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"00000000000000000000000000000000000000000000000000003FFFFFFD0463",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a_l(31 downto 0),
DOPADOP => data_out_a_l(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b_l(31 downto 0),
DOPBDOP => data_out_b_l(35 downto 32),
DIBDI => data_in_b_l(31 downto 0),
DIPBDIP => data_in_b_l(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
kcpsm6_rom_h: RAMB36E1
generic map ( READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "VIRTEX6",
INIT_00 => X"0808080808080808080808080808286858906848109D8D0088EF2510000D0D0F",
INIT_01 => X"0000000000000000000000000000000000000F08080808080808080808080808",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"00000000000000000000000000000000000000000000000000003FFFFFFFC9B8",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a_h(31 downto 0),
DOPADOP => data_out_a_h(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b_h(31 downto 0),
DOPBDOP => data_out_b_h(35 downto 32),
DIBDI => data_in_b_h(31 downto 0),
DIPBDIP => data_in_b_h(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
end generate v6;
--
--
akv7 : if (C_FAMILY = "7S") generate
--
address_a <= '1' & address(11 downto 0) & "111";
instruction <= data_out_a_h(32) & data_out_a_h(7 downto 0) & data_out_a_l(32) & data_out_a_l(7 downto 0);
data_in_a <= "000000000000000000000000000000000000";
jtag_dout <= data_out_b_h(32) & data_out_b_h(7 downto 0) & data_out_b_l(32) & data_out_b_l(7 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b_l <= "000" & data_out_b_l(32) & "000000000000000000000000" & data_out_b_l(7 downto 0);
data_in_b_h <= "000" & data_out_b_h(32) & "000000000000000000000000" & data_out_b_h(7 downto 0);
address_b <= "1111111111111111";
we_b <= "00000000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b_h <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9);
data_in_b_l <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0);
address_b <= '1' & jtag_addr(11 downto 0) & "111";
we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom_l: RAMB36E1
generic map ( READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "7SERIES",
INIT_00 => X"240BE6EA070F03FCFF00FEFF02010001200C01000500010C00FFA02E05120000",
INIT_01 => X"000000000000000000000000000000000000FF0102FFFE00FFFC030F07EAE60B",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"00000000000000000000000000000000000000000000000000003FFFFFFD0463",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a_l(31 downto 0),
DOPADOP => data_out_a_l(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b_l(31 downto 0),
DOPBDOP => data_out_b_l(35 downto 32),
DIBDI => data_in_b_l(31 downto 0),
DIPBDIP => data_in_b_l(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
kcpsm6_rom_h: RAMB36E1
generic map ( READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "7SERIES",
INIT_00 => X"0808080808080808080808080808286858906848109D8D0088EF2510000D0D0F",
INIT_01 => X"0000000000000000000000000000000000000F08080808080808080808080808",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"00000000000000000000000000000000000000000000000000003FFFFFFFC9B8",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a_h(31 downto 0),
DOPADOP => data_out_a_h(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b_h(31 downto 0),
DOPBDOP => data_out_b_h(35 downto 32),
DIBDI => data_in_b_h(31 downto 0),
DIPBDIP => data_in_b_h(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
end generate akv7;
--
end generate ram_4k_generate;
--
--
--
--
-- JTAG Loader
--
instantiate_loader : if (C_JTAG_LOADER_ENABLE = 1) generate
--
jtag_loader_6_inst : jtag_loader_6
generic map( C_FAMILY => C_FAMILY,
C_NUM_PICOBLAZE => 1,
C_JTAG_LOADER_ENABLE => C_JTAG_LOADER_ENABLE,
C_BRAM_MAX_ADDR_WIDTH => BRAM_ADDRESS_WIDTH,
C_ADDR_WIDTH_0 => BRAM_ADDRESS_WIDTH)
port map( picoblaze_reset => rdl_bus,
jtag_en => jtag_en,
jtag_din => jtag_din,
jtag_addr => jtag_addr(BRAM_ADDRESS_WIDTH-1 downto 0),
jtag_clk => jtag_clk,
jtag_we => jtag_we,
jtag_dout_0 => jtag_dout,
jtag_dout_1 => jtag_dout, -- ports 1-7 are not used
jtag_dout_2 => jtag_dout, -- in a 1 device debug
jtag_dout_3 => jtag_dout, -- session. However, Synplify
jtag_dout_4 => jtag_dout, -- etc require all ports to
jtag_dout_5 => jtag_dout, -- be connected
jtag_dout_6 => jtag_dout,
jtag_dout_7 => jtag_dout);
--
end generate instantiate_loader;
--
end low_level_definition;
--
--
-------------------------------------------------------------------------------------------
--
-- JTAG Loader
--
-------------------------------------------------------------------------------------------
--
--
-- JTAG Loader 6 - Version 6.00
-- Kris Chaplin 4 February 2010
-- Ken Chapman 15 August 2011 - Revised coding style
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
library unisim;
use unisim.vcomponents.all;
--
entity jtag_loader_6 is
generic( C_JTAG_LOADER_ENABLE : integer := 1;
C_FAMILY : string := "V6";
C_NUM_PICOBLAZE : integer := 1;
C_BRAM_MAX_ADDR_WIDTH : integer := 10;
C_PICOBLAZE_INSTRUCTION_DATA_WIDTH : integer := 18;
C_JTAG_CHAIN : integer := 2;
C_ADDR_WIDTH_0 : integer := 10;
C_ADDR_WIDTH_1 : integer := 10;
C_ADDR_WIDTH_2 : integer := 10;
C_ADDR_WIDTH_3 : integer := 10;
C_ADDR_WIDTH_4 : integer := 10;
C_ADDR_WIDTH_5 : integer := 10;
C_ADDR_WIDTH_6 : integer := 10;
C_ADDR_WIDTH_7 : integer := 10);
port( picoblaze_reset : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
jtag_en : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0');
jtag_din : out std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0) := (others => '0');
jtag_addr : out std_logic_vector(C_BRAM_MAX_ADDR_WIDTH-1 downto 0) := (others => '0');
jtag_clk : out std_logic := '0';
jtag_we : out std_logic := '0';
jtag_dout_0 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_1 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_2 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_3 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_4 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_5 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_6 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_7 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0));
end jtag_loader_6;
--
architecture Behavioral of jtag_loader_6 is
--
signal num_picoblaze : std_logic_vector(2 downto 0);
signal picoblaze_instruction_data_width : std_logic_vector(4 downto 0);
--
signal drck : std_logic;
signal shift_clk : std_logic;
signal shift_din : std_logic;
signal shift_dout : std_logic;
signal shift : std_logic;
signal capture : std_logic;
--
signal control_reg_ce : std_logic;
signal bram_ce : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
signal bus_zero : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0');
signal jtag_en_int : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
signal jtag_en_expanded : std_logic_vector(7 downto 0) := (others => '0');
signal jtag_addr_int : std_logic_vector(C_BRAM_MAX_ADDR_WIDTH-1 downto 0);
signal jtag_din_int : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal control_din : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0):= (others => '0');
signal control_dout : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0):= (others => '0');
signal control_dout_int : std_logic_vector(7 downto 0):= (others => '0');
signal bram_dout_int : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0) := (others => '0');
signal jtag_we_int : std_logic;
signal jtag_clk_int : std_logic;
signal bram_ce_valid : std_logic;
signal din_load : std_logic;
--
signal jtag_dout_0_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_1_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_2_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_3_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_4_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_5_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_6_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_7_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal picoblaze_reset_int : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0');
--
begin
bus_zero <= (others => '0');
--
jtag_loader_gen: if (C_JTAG_LOADER_ENABLE = 1) generate
--
-- Insert BSCAN primitive for target device architecture.
--
BSCAN_SPARTAN6_gen: if (C_FAMILY="S6") generate
begin
BSCAN_BLOCK_inst : BSCAN_SPARTAN6
generic map ( JTAG_CHAIN => C_JTAG_CHAIN)
port map( CAPTURE => capture,
DRCK => drck,
RESET => open,
RUNTEST => open,
SEL => bram_ce_valid,
SHIFT => shift,
TCK => open,
TDI => shift_din,
TMS => open,
UPDATE => jtag_clk_int,
TDO => shift_dout);
end generate BSCAN_SPARTAN6_gen;
--
BSCAN_VIRTEX6_gen: if (C_FAMILY="V6") generate
begin
BSCAN_BLOCK_inst: BSCAN_VIRTEX6
generic map( JTAG_CHAIN => C_JTAG_CHAIN,
DISABLE_JTAG => FALSE)
port map( CAPTURE => capture,
DRCK => drck,
RESET => open,
RUNTEST => open,
SEL => bram_ce_valid,
SHIFT => shift,
TCK => open,
TDI => shift_din,
TMS => open,
UPDATE => jtag_clk_int,
TDO => shift_dout);
end generate BSCAN_VIRTEX6_gen;
--
BSCAN_7SERIES_gen: if (C_FAMILY="7S") generate
begin
BSCAN_BLOCK_inst: BSCANE2
generic map( JTAG_CHAIN => C_JTAG_CHAIN,
DISABLE_JTAG => "FALSE")
port map( CAPTURE => capture,
DRCK => drck,
RESET => open,
RUNTEST => open,
SEL => bram_ce_valid,
SHIFT => shift,
TCK => open,
TDI => shift_din,
TMS => open,
UPDATE => jtag_clk_int,
TDO => shift_dout);
end generate BSCAN_7SERIES_gen;
--
--
-- Insert clock buffer to ensure reliable shift operations.
--
upload_clock: BUFG
port map( I => drck,
O => shift_clk);
--
--
-- Shift Register
--
--
control_reg_ce_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk = '1' then
if (shift = '1') then
control_reg_ce <= shift_din;
end if;
end if;
end process control_reg_ce_shift;
--
bram_ce_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk='1' then
if (shift = '1') then
if(C_NUM_PICOBLAZE > 1) then
for i in 0 to C_NUM_PICOBLAZE-2 loop
bram_ce(i+1) <= bram_ce(i);
end loop;
end if;
bram_ce(0) <= control_reg_ce;
end if;
end if;
end process bram_ce_shift;
--
bram_we_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk='1' then
if (shift = '1') then
jtag_we_int <= bram_ce(C_NUM_PICOBLAZE-1);
end if;
end if;
end process bram_we_shift;
--
bram_a_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk='1' then
if (shift = '1') then
for i in 0 to C_BRAM_MAX_ADDR_WIDTH-2 loop
jtag_addr_int(i+1) <= jtag_addr_int(i);
end loop;
jtag_addr_int(0) <= jtag_we_int;
end if;
end if;
end process bram_a_shift;
--
bram_d_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk='1' then
if (din_load = '1') then
jtag_din_int <= bram_dout_int;
elsif (shift = '1') then
for i in 0 to C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-2 loop
jtag_din_int(i+1) <= jtag_din_int(i);
end loop;
jtag_din_int(0) <= jtag_addr_int(C_BRAM_MAX_ADDR_WIDTH-1);
end if;
end if;
end process bram_d_shift;
--
shift_dout <= jtag_din_int(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1);
--
--
din_load_select:process (bram_ce, din_load, capture, bus_zero, control_reg_ce)
begin
if ( bram_ce = bus_zero ) then
din_load <= capture and control_reg_ce;
else
din_load <= capture;
end if;
end process din_load_select;
--
--
-- Control Registers
--
num_picoblaze <= conv_std_logic_vector(C_NUM_PICOBLAZE-1,3);
picoblaze_instruction_data_width <= conv_std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1,5);
--
control_registers: process(jtag_clk_int)
begin
if (jtag_clk_int'event and jtag_clk_int = '1') then
if (bram_ce_valid = '1') and (jtag_we_int = '0') and (control_reg_ce = '1') then
case (jtag_addr_int(3 downto 0)) is
when "0000" => -- 0 = version - returns (7 downto 4) illustrating number of PB
-- and (3 downto 0) picoblaze instruction data width
control_dout_int <= num_picoblaze & picoblaze_instruction_data_width;
when "0001" => -- 1 = PicoBlaze 0 reset / status
if (C_NUM_PICOBLAZE >= 1) then
control_dout_int <= picoblaze_reset_int(0) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_0-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0010" => -- 2 = PicoBlaze 1 reset / status
if (C_NUM_PICOBLAZE >= 2) then
control_dout_int <= picoblaze_reset_int(1) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_1-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0011" => -- 3 = PicoBlaze 2 reset / status
if (C_NUM_PICOBLAZE >= 3) then
control_dout_int <= picoblaze_reset_int(2) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_2-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0100" => -- 4 = PicoBlaze 3 reset / status
if (C_NUM_PICOBLAZE >= 4) then
control_dout_int <= picoblaze_reset_int(3) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_3-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0101" => -- 5 = PicoBlaze 4 reset / status
if (C_NUM_PICOBLAZE >= 5) then
control_dout_int <= picoblaze_reset_int(4) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_4-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0110" => -- 6 = PicoBlaze 5 reset / status
if (C_NUM_PICOBLAZE >= 6) then
control_dout_int <= picoblaze_reset_int(5) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_5-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0111" => -- 7 = PicoBlaze 6 reset / status
if (C_NUM_PICOBLAZE >= 7) then
control_dout_int <= picoblaze_reset_int(6) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_6-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "1000" => -- 8 = PicoBlaze 7 reset / status
if (C_NUM_PICOBLAZE >= 8) then
control_dout_int <= picoblaze_reset_int(7) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_7-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "1111" => control_dout_int <= conv_std_logic_vector(C_BRAM_MAX_ADDR_WIDTH -1,8);
when others => control_dout_int <= (others => '1');
end case;
else
control_dout_int <= (others => '0');
end if;
end if;
end process control_registers;
--
control_dout(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-8) <= control_dout_int;
--
pb_reset: process(jtag_clk_int)
begin
if (jtag_clk_int'event and jtag_clk_int = '1') then
if (bram_ce_valid = '1') and (jtag_we_int = '1') and (control_reg_ce = '1') then
picoblaze_reset_int(C_NUM_PICOBLAZE-1 downto 0) <= control_din(C_NUM_PICOBLAZE-1 downto 0);
end if;
end if;
end process pb_reset;
--
--
-- Assignments
--
control_dout (C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-9 downto 0) <= (others => '0') when (C_PICOBLAZE_INSTRUCTION_DATA_WIDTH > 8);
--
-- Qualify the blockram CS signal with bscan select output
jtag_en_int <= bram_ce when bram_ce_valid = '1' else (others => '0');
--
jtag_en_expanded(C_NUM_PICOBLAZE-1 downto 0) <= jtag_en_int;
jtag_en_expanded(7 downto C_NUM_PICOBLAZE) <= (others => '0') when (C_NUM_PICOBLAZE < 8);
--
bram_dout_int <= control_dout or jtag_dout_0_masked or jtag_dout_1_masked or jtag_dout_2_masked or jtag_dout_3_masked or jtag_dout_4_masked or jtag_dout_5_masked or jtag_dout_6_masked or jtag_dout_7_masked;
--
control_din <= jtag_din_int;
--
jtag_dout_0_masked <= jtag_dout_0 when jtag_en_expanded(0) = '1' else (others => '0');
jtag_dout_1_masked <= jtag_dout_1 when jtag_en_expanded(1) = '1' else (others => '0');
jtag_dout_2_masked <= jtag_dout_2 when jtag_en_expanded(2) = '1' else (others => '0');
jtag_dout_3_masked <= jtag_dout_3 when jtag_en_expanded(3) = '1' else (others => '0');
jtag_dout_4_masked <= jtag_dout_4 when jtag_en_expanded(4) = '1' else (others => '0');
jtag_dout_5_masked <= jtag_dout_5 when jtag_en_expanded(5) = '1' else (others => '0');
jtag_dout_6_masked <= jtag_dout_6 when jtag_en_expanded(6) = '1' else (others => '0');
jtag_dout_7_masked <= jtag_dout_7 when jtag_en_expanded(7) = '1' else (others => '0');
--
jtag_en <= jtag_en_int;
jtag_din <= jtag_din_int;
jtag_addr <= jtag_addr_int;
jtag_clk <= jtag_clk_int;
jtag_we <= jtag_we_int;
picoblaze_reset <= picoblaze_reset_int;
--
end generate jtag_loader_gen;
--
end Behavioral;
--
--
------------------------------------------------------------------------------------
--
-- END OF FILE fir_filter_picoblaze_program.vhd
--
------------------------------------------------------------------------------------
| mit | f477be23d167a87131011d8c468f8d76 | 0.617579 | 6.592813 | false | false | false | false |
MartinCura/SistDig-TP4 | old/fix_floating_point_files/float_pkg_c.vhdl | 1 | 298,010 | -- --------------------------------------------------------------------
-- "float_pkg" package contains functions for floating point math.
-- Please see the documentation for the floating point package.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
-- use ieee_proposed.fixed_float_types.all;
-- use ieee_proposed.fixed_pkg.all;
-- use ieee_proposed.float_pkg.all;
--
-- This verison is designed to work with the VHDL-93 compilers. Please
-- note the "%%%" comments. These are where we diverge from the
-- VHDL-200X LRM.
--
-- --------------------------------------------------------------------
-- Version : $Revision: 2.2 $
-- Date : $Date: 2010/09/22 18:26:46 $
-- --------------------------------------------------------------------
use STD.TEXTIO.all;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
--library ieee_proposed;
--use ieee_proposed.fixed_float_types.all;
--use ieee_proposed.fixed_pkg.all;
library floatfixlib;
use floatfixlib.fixed_float_types.all;
use floatfixlib.fixed_pkg.all;
---library work;
---use work.fixed_float_types.all;
---use work.fixed_pkg.all;
package float_pkg is
-- generic (
-- Defaults for sizing routines, when you do a "to_float" this will be
-- the default size. Example float32 would be 8 and 23 (8 downto -23)
constant float_exponent_width : NATURAL := 8;
constant float_fraction_width : NATURAL := 23;
-- Rounding algorithm, "round_nearest" is default, other valid values
-- are "round_zero" (truncation), "round_inf" (round up), and
-- "round_neginf" (round down)
constant float_round_style : round_type := round_nearest;
-- Denormal numbers (very small numbers near zero) true or false
constant float_denormalize : BOOLEAN := true;
-- Turns on NAN processing (invalid numbers and overflow) true of false
constant float_check_error : BOOLEAN := true;
-- Guard bits are added to the bottom of every operation for rounding.
-- any natural number (including 0) are valid.
constant float_guard_bits : NATURAL := 3;
-- If TRUE, then turn off warnings on "X" propagation
constant no_warning : BOOLEAN := (false
);
-- Author David Bishop ([email protected])
-- Note that the size of the vector is not defined here, but in
-- the package which calls this one.
type UNRESOLVED_float is array (INTEGER range <>) of STD_ULOGIC; -- main type
subtype U_float is UNRESOLVED_float;
subtype float is UNRESOLVED_float;
-----------------------------------------------------------------------------
-- Use the float type to define your own floating point numbers.
-- There must be a negative index or the packages will error out.
-- Minimum supported is "subtype float7 is float (3 downto -3);"
-- "subtype float16 is float (6 downto -9);" is probably the smallest
-- practical one to use.
-----------------------------------------------------------------------------
-- IEEE 754 single precision
subtype UNRESOLVED_float32 is UNRESOLVED_float (8 downto -23);
subtype U_float32 is UNRESOLVED_float32;---alias U_float32 is UNRESOLVED_float32;
subtype float32 is float (8 downto -23);
-----------------------------------------------------------------------------
-- IEEE-754 single precision floating point. This is a "float"
-- in C, and a FLOAT in Fortran. The exponent is 8 bits wide, and
-- the fraction is 23 bits wide. This format can hold roughly 7 decimal
-- digits. Infinity is 2**127 = 1.7E38 in this number system.
-- The bit representation is as follows:
-- 1 09876543 21098765432109876543210
-- 8 76543210 12345678901234567890123
-- 0 00000000 00000000000000000000000
-- 8 7 0 -1 -23
-- +/- exp. fraction
-----------------------------------------------------------------------------
-- IEEE 754 double precision
subtype UNRESOLVED_float64 is UNRESOLVED_float (11 downto -52);
subtype U_float64 is UNRESOLVED_float64;---alias U_float64 is UNRESOLVED_float64;
subtype float64 is float (11 downto -52);
-----------------------------------------------------------------------------
-- IEEE-754 double precision floating point. This is a "double float"
-- in C, and a FLOAT*8 in Fortran. The exponent is 11 bits wide, and
-- the fraction is 52 bits wide. This format can hold roughly 15 decimal
-- digits. Infinity is 2**2047 in this number system.
-- The bit representation is as follows:
-- 3 21098765432 1098765432109876543210987654321098765432109876543210
-- 1 09876543210 1234567890123456789012345678901234567890123456789012
-- S EEEEEEEEEEE FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
-- 11 10 0 -1 -52
-- +/- exponent fraction
-----------------------------------------------------------------------------
-- IEEE 854 & C extended precision
subtype UNRESOLVED_float128 is UNRESOLVED_float (15 downto -112);
subtype U_float128 is UNRESOLVED_float128;---alias U_float128 is UNRESOLVED_float128;
subtype float128 is float (15 downto -112);
-----------------------------------------------------------------------------
-- The 128 bit floating point number is "long double" in C (on
-- some systems this is a 70 bit floating point number) and FLOAT*32
-- in Fortran. The exponent is 15 bits wide and the fraction is 112
-- bits wide. This number can handle approximately 33 decimal digits.
-- Infinity is 2**32,767 in this number system.
-----------------------------------------------------------------------------
-- purpose: Checks for a valid floating point number
type valid_fpstate is (nan, -- Signaling NaN (C FP_NAN)
quiet_nan, -- Quiet NaN (C FP_NAN)
neg_inf, -- Negative infinity (C FP_INFINITE)
neg_normal, -- negative normalized nonzero
neg_denormal, -- negative denormalized (FP_SUBNORMAL)
neg_zero, -- -0 (C FP_ZERO)
pos_zero, -- +0 (C FP_ZERO)
pos_denormal, -- Positive denormalized (FP_SUBNORMAL)
pos_normal, -- positive normalized nonzero
pos_inf, -- positive infinity
isx); -- at least one input is unknown
-- This deferred constant will tell you if the package body is synthesizable
-- or implemented as real numbers.
---constant fphdlsynth_or_real : BOOLEAN; -- deferred constant ---CAMBIADO
-- Returns the class which X falls into
function Classfp (
x : UNRESOLVED_float; -- floating point input
check_error : BOOLEAN := float_check_error) -- check for errors
return valid_fpstate;
-- Arithmetic functions, these operators do not require parameters.
function "abs" (arg : UNRESOLVED_float) return UNRESOLVED_float;
function "-" (arg : UNRESOLVED_float) return UNRESOLVED_float;
-- These allows the base math functions to use the default values
-- of their parameters. Thus they do full IEEE floating point.
function "+" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "-" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "*" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "/" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "rem" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "mod" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
-- Basic parameter list
-- round_style - Selects the rounding algorithm to use
-- guard - extra bits added to the end if the operation to add precision
-- check_error - When "false" turns off NAN and overflow checks
-- denormalize - When "false" turns off denormal number processing
function add (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function subtract (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function multiply (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function divide (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function remainder (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function modulo (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- reciprocal
function reciprocal (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function dividebyp2 (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- Multiply accumulate result = l*r + c
function mac (
l, r, c : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- Square root (all 754 based implementations need this)
function sqrt (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style;
constant guard : NATURAL := float_guard_bits;
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_float;
function Is_Negative (arg : UNRESOLVED_float) return BOOLEAN;
-----------------------------------------------------------------------------
-- compare functions
-- =, /=, >=, <=, <, >, maximum, minimum
function eq ( -- equal =
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function ne ( -- not equal /=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function lt ( -- less than <
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function gt ( -- greater than >
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function le ( -- less than or equal to <=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function ge ( -- greater than or equal to >=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
-- Need to overload the default versions of these
function "=" (l, r : UNRESOLVED_float) return BOOLEAN;
function "/=" (l, r : UNRESOLVED_float) return BOOLEAN;
function ">=" (l, r : UNRESOLVED_float) return BOOLEAN;
function "<=" (l, r : UNRESOLVED_float) return BOOLEAN;
function ">" (l, r : UNRESOLVED_float) return BOOLEAN;
function "<" (l, r : UNRESOLVED_float) return BOOLEAN;
function \?=\ (l, r : UNRESOLVED_float) return STD_ULOGIC;
function \?/=\ (l, r : UNRESOLVED_float) return STD_ULOGIC;
function \?>\ (l, r : UNRESOLVED_float) return STD_ULOGIC;
function \?>=\ (l, r : UNRESOLVED_float) return STD_ULOGIC;
function \?<\ (l, r : UNRESOLVED_float) return STD_ULOGIC;
function \?<=\ (l, r : UNRESOLVED_float) return STD_ULOGIC;
function std_match (l, r : UNRESOLVED_float) return BOOLEAN;
function find_rightmost (arg : UNRESOLVED_float; y : STD_ULOGIC)
return INTEGER;
function find_leftmost (arg : UNRESOLVED_float; y : STD_ULOGIC)
return INTEGER;
function maximum (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function minimum (l, r : UNRESOLVED_float) return UNRESOLVED_float;
-- conversion functions
-- Converts one floating point number into another.
function resize (
arg : UNRESOLVED_float; -- Floating point input
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function resize (
arg : UNRESOLVED_float; -- Floating point input
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function to_float32 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float32;
function to_float64 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float64;
function to_float128 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float128;
-- Converts an fp into an SLV (needed for synthesis)
function to_slv (arg : UNRESOLVED_float) return STD_LOGIC_VECTOR;
---alias to_StdLogicVector is to_slv [UNRESOLVED_float return STD_LOGIC_VECTOR]; IGUAL NO SE USABA
---alias to_Std_Logic_Vector is to_slv [UNRESOLVED_float return STD_LOGIC_VECTOR]; IGUAL NO SE USABA
-- Converts an fp into an std_ulogic_vector (sulv)
function to_sulv (arg : UNRESOLVED_float) return STD_ULOGIC_VECTOR;
---alias to_StdULogicVector is to_sulv [UNRESOLVED_float return STD_ULOGIC_VECTOR]; IGUAL NO SE USABA
---alias to_Std_ULogic_Vector is to_sulv [UNRESOLVED_float return STD_ULOGIC_VECTOR]; IGUAL NO SE USABA
-- std_ulogic_vector to float
function to_float (
arg : STD_ULOGIC_VECTOR;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction
return UNRESOLVED_float;
-- Integer to float
function to_float (
arg : INTEGER;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- real to float
function to_float (
arg : REAL;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- unsigned to float
function to_float (
arg : UNSIGNED;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- signed to float
function to_float (
arg : SIGNED;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- unsigned fixed point to float
function to_float (
arg : UNRESOLVED_ufixed; -- unsigned fixed point input
constant exponent_width : NATURAL := float_exponent_width; -- width of exponent
constant fraction_width : NATURAL := float_fraction_width; -- width of fraction
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions
return UNRESOLVED_float;
-- signed fixed point to float
function to_float (
arg : UNRESOLVED_sfixed;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- rounding option
return UNRESOLVED_float;
-- size_res functions
-- Integer to float
function to_float (
arg : INTEGER;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- real to float
function to_float (
arg : REAL;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- unsigned to float
function to_float (
arg : UNSIGNED;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- signed to float
function to_float (
arg : SIGNED;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- sulv to float
function to_float (
arg : STD_ULOGIC_VECTOR;
size_res : UNRESOLVED_float)
return UNRESOLVED_float;
-- unsigned fixed point to float
function to_float (
arg : UNRESOLVED_ufixed; -- unsigned fixed point input
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions
return UNRESOLVED_float;
-- signed fixed point to float
function to_float (
arg : UNRESOLVED_sfixed;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- rounding option
return UNRESOLVED_float;
-- float to unsigned
function to_unsigned (
arg : UNRESOLVED_float; -- floating point input
constant size : NATURAL; -- length of output
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNSIGNED;
-- float to signed
function to_signed (
arg : UNRESOLVED_float; -- floating point input
constant size : NATURAL; -- length of output
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return SIGNED;
-- purpose: Converts a float to unsigned fixed point
function to_ufixed (
arg : UNRESOLVED_float; -- fp input
constant left_index : INTEGER; -- integer part
constant right_index : INTEGER; -- fraction part
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_ufixed;
-- float to signed fixed point
function to_sfixed (
arg : UNRESOLVED_float; -- fp input
constant left_index : INTEGER; -- integer part
constant right_index : INTEGER; -- fraction part
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_sfixed;
-- size_res versions
-- float to unsigned
function to_unsigned (
arg : UNRESOLVED_float; -- floating point input
size_res : UNSIGNED;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNSIGNED;
-- float to signed
function to_signed (
arg : UNRESOLVED_float; -- floating point input
size_res : SIGNED;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return SIGNED;
-- purpose: Converts a float to unsigned fixed point
function to_ufixed (
arg : UNRESOLVED_float; -- fp input
size_res : UNRESOLVED_ufixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_ufixed;
-- float to signed fixed point
function to_sfixed (
arg : UNRESOLVED_float; -- fp input
size_res : UNRESOLVED_sfixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_sfixed;
-- float to real
function to_real (
arg : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return REAL;
-- float to integer
function to_integer (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return INTEGER;
-- For Verilog compatability
function realtobits (arg : REAL) return STD_ULOGIC_VECTOR;
function bitstoreal (arg : STD_ULOGIC_VECTOR) return REAL;
-- Maps metalogical values
function to_01 (
arg : UNRESOLVED_float; -- floating point input
XMAP : STD_LOGIC := '0')
return UNRESOLVED_float;
function Is_X (arg : UNRESOLVED_float) return BOOLEAN;
function to_X01 (arg : UNRESOLVED_float) return UNRESOLVED_float;
function to_X01Z (arg : UNRESOLVED_float) return UNRESOLVED_float;
function to_UX01 (arg : UNRESOLVED_float) return UNRESOLVED_float;
-- These two procedures were copied out of the body because they proved
-- very useful for vendor specific algorithm development
-- Break_number converts a floating point number into it's parts
-- Exponent is biased by -1
procedure break_number (
arg : in UNRESOLVED_float;
denormalize : in BOOLEAN := float_denormalize;
check_error : in BOOLEAN := float_check_error;
fract : out UNSIGNED;
expon : out SIGNED; -- NOTE: Add 1 to get the real exponent!
sign : out STD_ULOGIC);
procedure break_number (
arg : in UNRESOLVED_float;
denormalize : in BOOLEAN := float_denormalize;
check_error : in BOOLEAN := float_check_error;
fract : out ufixed; -- a number between 1.0 and 2.0
expon : out SIGNED; -- NOTE: Add 1 to get the real exponent!
sign : out STD_ULOGIC);
-- Normalize takes a fraction and and exponent and converts them into
-- a floating point number. Does the shifting and the rounding.
-- Exponent is assumed to be biased by -1
function normalize (
fract : UNSIGNED; -- fraction, unnormalized
expon : SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent
constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float;
-- Exponent is assumed to be biased by -1
function normalize (
fract : ufixed; -- unsigned fixed point
expon : SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent
constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float;
function normalize (
fract : UNSIGNED; -- unsigned
expon : SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
size_res : UNRESOLVED_float; -- used for sizing only
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float;
-- Exponent is assumed to be biased by -1
function normalize (
fract : ufixed; -- unsigned fixed point
expon : SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
size_res : UNRESOLVED_float; -- used for sizing only
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float;
-- overloaded versions
function "+" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "+" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "+" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "+" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "-" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "-" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "-" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "-" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "*" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "*" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "*" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "*" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "/" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "/" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "/" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "/" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "rem" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "rem" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "rem" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "rem" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "mod" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "mod" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "mod" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "mod" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
-- overloaded compare functions
function "=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function "/=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function ">=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function "<=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function ">" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function "<" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function "=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function "/=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function ">=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function "<=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function ">" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function "<" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function "=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function "/=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function ">=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function "<=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function ">" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function "<" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function "=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function "/=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function ">=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function "<=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function ">" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function "<" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function \?=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function \?/=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function \?>\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function \?>=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function \?<\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function \?<=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function \?=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function \?/=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function \?>\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function \?>=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function \?<\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function \?<=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function \?=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function \?/=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function \?>\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function \?>=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function \?<\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function \?<=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function \?=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function \?/=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function \?>\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function \?>=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function \?<\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function \?<=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
-- minimum and maximum overloads
function maximum (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function minimum (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function maximum (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function minimum (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function maximum (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function minimum (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function maximum (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function minimum (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (l : UNRESOLVED_float) return UNRESOLVED_float;
function "and" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "or" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "nand" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "nor" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "xor" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "xnor" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "and" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "or" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "or" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "nand" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "nand" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "nor" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "nor" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "xor" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "xor" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "xnor" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "xnor" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
-- Reduction operators, same as numeric_std functions
function and_reduce (l : UNRESOLVED_float) return STD_ULOGIC;
function nand_reduce (l : UNRESOLVED_float) return STD_ULOGIC;
function or_reduce (l : UNRESOLVED_float) return STD_ULOGIC;
function nor_reduce (l : UNRESOLVED_float) return STD_ULOGIC;
function xor_reduce (l : UNRESOLVED_float) return STD_ULOGIC;
function xnor_reduce (l : UNRESOLVED_float) return STD_ULOGIC;
-- Note: "sla", "sra", "sll", "slr", "rol" and "ror" not implemented.
-----------------------------------------------------------------------------
-- Recommended Functions from the IEEE 754 Appendix
-----------------------------------------------------------------------------
-- returns x with the sign of y.
function Copysign (x, y : UNRESOLVED_float) return UNRESOLVED_float;
-- Returns y * 2**n for integral values of N without computing 2**n
function Scalb (
y : UNRESOLVED_float; -- floating point input
N : INTEGER; -- exponent to add
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- Returns y * 2**n for integral values of N without computing 2**n
function Scalb (
y : UNRESOLVED_float; -- floating point input
N : SIGNED; -- exponent to add
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- returns the unbiased exponent of x
function Logb (x : UNRESOLVED_float) return INTEGER;
function Logb (x : UNRESOLVED_float) return SIGNED;
-- returns the next representable neighbor of x in the direction toward y
function Nextafter (
x, y : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_float;
-- Returns TRUE if X is unordered with Y.
function Unordered (x, y : UNRESOLVED_float) return BOOLEAN;
function Finite (x : UNRESOLVED_float) return BOOLEAN;
function Isnan (x : UNRESOLVED_float) return BOOLEAN;
-- Function to return constants.
function zerofp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function nanfp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function qnanfp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function pos_inffp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function neg_inffp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function neg_zerofp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
-- size_res versions
function zerofp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function nanfp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function qnanfp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function pos_inffp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function neg_inffp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function neg_zerofp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
-- ===========================================================================
-- string and textio Functions
-- ===========================================================================
-- rtl_synthesis off
-- pragma synthesis_off
-- writes S:EEEE:FFFFFFFF
procedure WRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0); -- width of field
-- Reads SEEEEFFFFFFFF, "." and ":" are ignored
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float);
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float;
GOOD : out BOOLEAN);
alias BREAD is READ [LINE, UNRESOLVED_float, BOOLEAN];
alias BREAD is READ [LINE, UNRESOLVED_float];
alias BWRITE is WRITE [LINE, UNRESOLVED_float, SIDE, WIDTH];
alias BINARY_READ is READ [LINE, UNRESOLVED_FLOAT, BOOLEAN];
alias BINARY_READ is READ [LINE, UNRESOLVED_FLOAT];
alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_float, SIDE, WIDTH];
procedure OWRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0); -- width of field
-- Octal read with padding, no separators used
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_float);
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_float;
GOOD : out BOOLEAN);
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_FLOAT, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_FLOAT];
alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_FLOAT, SIDE, WIDTH];
-- Hex write with padding, no separators
procedure HWRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0); -- width of field
-- Hex read with padding, no separators used
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float);
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float;
GOOD : out BOOLEAN);
alias HEX_READ is HREAD [LINE, UNRESOLVED_FLOAT, BOOLEAN];
alias HEX_READ is HREAD [LINE, UNRESOLVED_FLOAT];
alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_FLOAT, SIDE, WIDTH];
-- returns "S:EEEE:FFFFFFFF"
function to_string (value : UNRESOLVED_float) return STRING;
alias TO_BSTRING is TO_STRING [UNRESOLVED_FLOAT return STRING];
alias TO_BINARY_STRING is TO_STRING [UNRESOLVED_FLOAT return STRING];
-- Returns a HEX string, with padding
function to_hstring (value : UNRESOLVED_float) return STRING;
alias TO_HEX_STRING is TO_HSTRING [UNRESOLVED_FLOAT return STRING];
-- Returns and octal string, with padding
function to_ostring (value : UNRESOLVED_float) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [UNRESOLVED_FLOAT return STRING];
function from_string (
bstring : STRING; -- binary string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float;
alias from_bstring is from_string [STRING, NATURAL, NATURAL
return UNRESOLVED_float];
alias from_binary_string is from_string [STRING, NATURAL, NATURAL
return UNRESOLVED_float];
function from_ostring (
ostring : STRING; -- Octal string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float;
alias from_octal_string is from_ostring [STRING, NATURAL, NATURAL
return UNRESOLVED_float];
function from_hstring (
hstring : STRING; -- hex string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float;
alias from_hex_string is from_hstring [STRING, NATURAL, NATURAL
return UNRESOLVED_float];
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float;
alias from_bstring is from_string [STRING, UNRESOLVED_float
return UNRESOLVED_float];
alias from_binary_string is from_string [STRING, UNRESOLVED_float
return UNRESOLVED_float];
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float;
alias from_octal_string is from_ostring [STRING, UNRESOLVED_float
return UNRESOLVED_float];
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float;
alias from_hex_string is from_hstring [STRING, UNRESOLVED_float
return UNRESOLVED_float];
-- rtl_synthesis on
-- pragma synthesis_on
-- IN VHDL-2006 std_logic_vector is a subtype of std_ulogic_vector, so these
-- extra functions are needed for compatability.
function to_float (
arg : STD_LOGIC_VECTOR;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction
return UNRESOLVED_float;
function to_float (
arg : STD_LOGIC_VECTOR;
size_res : UNRESOLVED_float)
return UNRESOLVED_float;
-- For Verilog compatability
function realtobits (arg : REAL) return STD_LOGIC_VECTOR;
function bitstoreal (arg : STD_LOGIC_VECTOR) return REAL;
end package float_pkg;
-------------------------------------------------------------------------------
-- Proposed package body for the VHDL-200x-FT float_pkg package
-- This version is optimized for Synthesis, and not for simulation.
-- Note that there are functional differences between the synthesis and
-- simulation packages bodies. The Synthesis version is preferred.
-- This package body supplies a recommended implementation of these functions
-- Version : $Revision: 2.2 $
-- Date : $Date: 2010/09/22 18:26:46 $
--
-- Created for VHDL-200X par, David Bishop ([email protected])
-------------------------------------------------------------------------------
package body float_pkg is
-- Author David Bishop ([email protected])
-----------------------------------------------------------------------------
-- type declarations
-----------------------------------------------------------------------------
-- This deferred constant will tell you if the package body is synthesizable
-- or implemented as real numbers, set to "true" if synthesizable.
constant fphdlsynth_or_real : BOOLEAN := true; -- deferred constant
-- types of boundary conditions
type boundary_type is (normal, infinity, zero, denormal);
-- null range array constant
constant NAFP : UNRESOLVED_float (0 downto 1) := (others => '0');
constant NSLV : STD_ULOGIC_VECTOR (0 downto 1) := (others => '0');
-- %%% Replicated functions
-- These functions are replicated so that we don't need to reference the new
-- 2006 package std.standard, std_logic_1164 and numeric_std.
function maximum (
l, r : INTEGER) -- inputs
return INTEGER is
begin -- function max
if l > r then return l;
else return r;
end if;
end function maximum;
function minimum (
l, r : INTEGER) -- inputs
return INTEGER is
begin -- function min
if l > r then return r;
else return l;
end if;
end function minimum;
function or_reduce (arg : STD_ULOGIC_VECTOR)
return STD_LOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC;
begin
if (arg'length < 1) then -- In the case of a NULL range
Result := '0';
else
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int (BUS_int'right) or BUS_int (BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := or_reduce (BUS_int (BUS_int'left downto Half));
Lower := or_reduce (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper or Lower;
end if;
end if;
return Result;
end function or_reduce;
function or_reduce (arg : UNSIGNED)
return STD_ULOGIC is
begin
return or_reduce (STD_ULOGIC_VECTOR (arg));
end function or_reduce;
function or_reduce (arg : SIGNED)
return STD_ULOGIC is
begin
return or_reduce (STD_ULOGIC_VECTOR (arg));
end function or_reduce;
function or_reduce (arg : STD_LOGIC_VECTOR)
return STD_ULOGIC is
begin
return or_reduce (STD_ULOGIC_VECTOR (arg));
end function or_reduce;
-- purpose: AND all of the bits in a vector together
-- This is a copy of the proposed "and_reduce" from 1076.3
function and_reduce (arg : STD_ULOGIC_VECTOR)
return STD_LOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC;
begin
if (arg'length < 1) then -- In the case of a NULL range
Result := '1';
else
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int (BUS_int'right) and BUS_int (BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := and_reduce (BUS_int (BUS_int'left downto Half));
Lower := and_reduce (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper and Lower;
end if;
end if;
return Result;
end function and_reduce;
function and_reduce (arg : UNSIGNED)
return STD_ULOGIC is
begin
return and_reduce (STD_ULOGIC_VECTOR (arg));
end function and_reduce;
function and_reduce (arg : SIGNED)
return STD_ULOGIC is
begin
return and_reduce (STD_ULOGIC_VECTOR (arg));
end function and_reduce;
function xor_reduce (arg : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC := '0'; -- In the case of a NULL range
begin
if (arg'length >= 1) then
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int(BUS_int'right) xor BUS_int(BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := xor_reduce (BUS_int (BUS_int'left downto Half));
Lower := xor_reduce (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper xor Lower;
end if;
end if;
return Result;
end function xor_reduce;
function nand_reduce(arg : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return not and_reduce (arg);
end function nand_reduce;
function nor_reduce(arg : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return not or_reduce (arg);
end function nor_reduce;
function xnor_reduce(arg : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return not xor_reduce (arg);
end function xnor_reduce;
function find_leftmost (ARG : UNSIGNED; Y : STD_ULOGIC)
return INTEGER is
begin
for INDEX in ARG'range loop
if ARG(INDEX) = Y then
return INDEX;
end if;
end loop;
return -1;
end function find_leftmost;
-- Match table, copied form new std_logic_1164
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
constant match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | X |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | 0 |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | W |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | L |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | H |
('1', '1', '1', '1', '1', '1', '1', '1', '1') -- | - |
);
-------------------------------------------------------------------
-- ?= functions, Similar to "std_match", but returns "std_ulogic".
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_ulogic ) RETURN std_ulogic IS
function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return match_logic_table (l, r);
end function \?=\;
-- %%% END FUNCTION "?=";
-- %%% FUNCTION "?/=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return not match_logic_table (l, r);
end function \?/=\;
-- %%% END FUNCTION "?/=";
function \?=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC is
alias lv : STD_ULOGIC_VECTOR(1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR(1 to r'length) is r;
variable result, result1 : STD_ULOGIC;
begin
-- Logically identical to an "=" operator.
if ((l'length < 1) and (r'length < 1)) then
-- VHDL-2008 LRM 9.2.3 Two NULL arrays of the same type are equal
return '1';
elsif lv'length /= rv'length then
-- Two arrays of different lengths are false
return '0';
else
result := '1';
for i in lv'low to lv'high loop
result1 := match_logic_table(lv(i), rv(i));
result := result and result1;
end loop;
return result;
end if;
end function \?=\;
function Is_X (s : UNSIGNED) return BOOLEAN is
begin
return Is_X (STD_LOGIC_VECTOR (s));
end function Is_X;
function Is_X (s : SIGNED) return BOOLEAN is
begin
return Is_X (STD_LOGIC_VECTOR (s));
end function Is_X;
-- %%% END replicated functions
-- Special version of "minimum" to do some boundary checking
function mine (L, R : INTEGER)
return INTEGER is
begin -- function minimum
if (L = INTEGER'low or R = INTEGER'low) then
report "float_pkg"
& " Unbounded number passed, was a literal used?"
severity error;
return 0;
end if;
return minimum (L, R);
end function mine;
-- Generates the base number for the exponent normalization offset.
function gen_expon_base (
constant exponent_width : NATURAL)
return SIGNED is
variable result : SIGNED (exponent_width-1 downto 0);
begin
result := (others => '1');
result (exponent_width-1) := '0';
return result;
end function gen_expon_base;
-- Integer version of the "log2" command (contributed by Peter Ashenden)
function log2 (A : NATURAL) return NATURAL is
variable quotient : NATURAL;
variable result : NATURAL := 0;
begin
quotient := A / 2;
while quotient > 0 loop
quotient := quotient / 2;
result := result + 1;
end loop;
return result;
end function log2;
-- Function similar to the ILOGB function in MATH_REAL
function log2 (A : REAL) return INTEGER is
variable Y : REAL;
variable N : INTEGER := 0;
begin
if (A = 1.0 or A = 0.0) then
return 0;
end if;
Y := A;
if(A > 1.0) then
while Y >= 2.0 loop
Y := Y / 2.0;
N := N + 1;
end loop;
return N;
end if;
-- O < Y < 1
while Y < 1.0 loop
Y := Y * 2.0;
N := N - 1;
end loop;
return N;
end function log2;
-- purpose: Test the boundary conditions of a Real number
procedure test_boundary (
arg : in REAL; -- Input, converted to real
constant fraction_width : in NATURAL; -- length of FP output fraction
constant exponent_width : in NATURAL; -- length of FP exponent
constant denormalize : in BOOLEAN := true; -- Use IEEE extended FP
variable btype : out boundary_type;
variable log2i : out INTEGER
) is
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
constant exp_min : SIGNED (12 downto 0) :=
-(resize(expon_base, 13)) + 1; -- Minimum normal exponent
constant exp_ext_min : SIGNED (12 downto 0) :=
exp_min - fraction_width; -- Minimum for denormal exponent
variable log2arg : INTEGER; -- log2 of argument
begin -- function test_boundary
-- Check to see if the exponent is big enough
-- Note that the argument is always an absolute value at this point.
log2arg := log2(arg);
if arg = 0.0 then
btype := zero;
elsif exponent_width > 11 then -- Exponent for Real is 11 (64 bit)
btype := normal;
else
if log2arg < to_integer(exp_min) then
if denormalize then
if log2arg < to_integer(exp_ext_min) then
btype := zero;
else
btype := denormal;
end if;
else
if log2arg < to_integer(exp_min)-1 then
btype := zero;
else
btype := normal; -- Can still represent this number
end if;
end if;
elsif exponent_width < 11 then
if log2arg > to_integer(expon_base)+1 then
btype := infinity;
else
btype := normal;
end if;
else
btype := normal;
end if;
end if;
log2i := log2arg;
end procedure test_boundary;
-- purpose: Rounds depending on the state of the "round_style"
-- Logic taken from
-- "What Every Computer Scientist Should Know About Floating Point Arithmetic"
-- by David Goldberg (1991)
function check_round (
fract_in : STD_ULOGIC; -- input fraction
sign : STD_ULOGIC; -- sign bit
remainder : UNSIGNED; -- remainder to round from
sticky : STD_ULOGIC := '0'; -- Sticky bit
constant round_style : round_type) -- rounding type
return BOOLEAN is
variable result : BOOLEAN;
variable or_reduced : STD_ULOGIC;
begin -- function check_round
result := false;
if (remainder'length > 0) then -- if remainder in a null array
or_reduced := or_reduce (remainder & sticky);
rounding_case : case round_style is
when round_nearest => -- Round Nearest, default mode
if remainder(remainder'high) = '1' then -- round
if (remainder'length > 1) then
if ((or_reduce (remainder(remainder'high-1
downto remainder'low)) = '1'
or sticky = '1')
or fract_in = '1') then
-- Make the bottom bit zero if possible if we are at 1/2
result := true;
end if;
else
result := (fract_in = '1' or sticky = '1');
end if;
end if;
when round_inf => -- round up if positive, else truncate.
if or_reduced = '1' and sign = '0' then
result := true;
end if;
when round_neginf => -- round down if negative, else truncate.
if or_reduced = '1' and sign = '1' then
result := true;
end if;
when round_zero => -- round toward 0 Truncate
null;
end case rounding_case;
end if;
return result;
end function check_round;
-- purpose: Rounds depending on the state of the "round_style"
-- unsigned version
procedure fp_round (
fract_in : in UNSIGNED; -- input fraction
expon_in : in SIGNED; -- input exponent
fract_out : out UNSIGNED; -- output fraction
expon_out : out SIGNED) is -- output exponent
begin -- procedure fp_round
if and_reduce (fract_in) = '1' then -- Fraction is all "1"
expon_out := expon_in + 1;
fract_out := to_unsigned(0, fract_out'high+1);
else
expon_out := expon_in;
fract_out := fract_in + 1;
end if;
end procedure fp_round;
-- This version of break_number doesn't call "classfp"
procedure break_number ( -- internal version
arg : in UNRESOLVED_float;
fptyp : in valid_fpstate;
denormalize : in BOOLEAN := true;
fract : out UNSIGNED;
expon : out SIGNED) is
constant fraction_width : NATURAL := -arg'low; -- length of FP output fraction
constant exponent_width : NATURAL := arg'high; -- length of FP output exponent
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable exp : SIGNED (expon'range);
begin
fract (fraction_width-1 downto 0) :=
UNSIGNED (to_slv(arg(-1 downto -fraction_width)));
breakcase : case fptyp is
when pos_zero | neg_zero =>
fract (fraction_width) := '0';
exp := -expon_base;
when pos_denormal | neg_denormal =>
if denormalize then
exp := -expon_base;
fract (fraction_width) := '0';
else
exp := -expon_base - 1;
fract (fraction_width) := '1';
end if;
when pos_normal | neg_normal | pos_inf | neg_inf =>
fract (fraction_width) := '1';
exp := SIGNED(arg(exponent_width-1 downto 0));
exp (exponent_width-1) := not exp(exponent_width-1);
when others =>
---assert NO_WARNING
--- report "float_pkg"
--- & "BREAK_NUMBER: " &
--- "Meta state detected in fp_break_number process"
--- severity warning;
-- complete the case, if a NAN goes in, a NAN comes out.
exp := (others => '1');
fract (fraction_width) := '1';
end case breakcase;
expon := exp;
end procedure break_number;
-- purpose: floating point to UNSIGNED
-- Used by to_integer, to_unsigned, and to_signed functions
procedure float_to_unsigned (
arg : in UNRESOLVED_float; -- floating point input
variable sign : out STD_ULOGIC; -- sign of output
variable frac : out UNSIGNED; -- unsigned biased output
constant denormalize : in BOOLEAN; -- turn on denormalization
constant bias : in NATURAL; -- bias for fixed point
constant round_style : in round_type) is -- rounding method
constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : INTEGER := arg'high; -- length of FP output exponent
variable fract : UNSIGNED (frac'range); -- internal version of frac
variable isign : STD_ULOGIC; -- internal version of sign
variable exp : INTEGER; -- Exponent
variable expon : SIGNED (exponent_width-1 downto 0); -- Vectorized exp
-- Base to divide fraction by
variable frac_shift : UNSIGNED (frac'high+3 downto 0); -- Fraction shifted
variable shift : INTEGER;
variable remainder : UNSIGNED (2 downto 0);
variable round : STD_ULOGIC; -- round BIT
begin
isign := to_x01(arg(arg'high));
-- exponent /= '0', normal floating point
expon := to_01(SIGNED(arg (exponent_width-1 downto 0)), 'X');
expon(exponent_width-1) := not expon(exponent_width-1);
exp := to_integer (expon);
-- Figure out the fraction
fract := (others => '0'); -- fill with zero
fract (fract'high) := '1'; -- Add the "1.0".
shift := (fract'high-1) - exp;
if fraction_width > fract'high then -- Can only use size-2 bits
fract (fract'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto
-fract'high)));
else -- can use all bits
fract (fract'high-1 downto fract'high-fraction_width) :=
UNSIGNED (to_slv (arg(-1 downto -fraction_width)));
end if;
frac_shift := fract & "000";
if shift < 0 then -- Overflow
fract := (others => '1');
else
frac_shift := shift_right (frac_shift, shift);
fract := frac_shift (frac_shift'high downto 3);
remainder := frac_shift (2 downto 0);
-- round (round_zero will bypass this and truncate)
case round_style is
when round_nearest =>
round := remainder(2) and
(fract (0) or (or_reduce (remainder (1 downto 0))));
when round_inf =>
round := remainder(2) and not isign;
when round_neginf =>
round := remainder(2) and isign;
when others =>
round := '0';
end case;
if round = '1' then
fract := fract + 1;
end if;
end if;
frac := fract;
sign := isign;
end procedure float_to_unsigned;
-- purpose: returns a part of a vector, this function is here because
-- or (fractr (to_integer(shiftx) downto 0));
-- can't be synthesized in some synthesis tools.
function smallfract (
arg : UNSIGNED;
shift : NATURAL)
return STD_ULOGIC is
variable orx : STD_ULOGIC;
begin
orx := arg(shift);
for i in arg'range loop
if i < shift then
orx := arg(i) or orx;
end if;
end loop;
return orx;
end function smallfract;
---------------------------------------------------------------------------
-- Visible functions
---------------------------------------------------------------------------
-- purpose: converts the negative index to a positive one
-- negative indices are illegal in 1164 and 1076.3
function to_sulv (
arg : UNRESOLVED_float) -- fp vector
return STD_ULOGIC_VECTOR is
variable result : STD_ULOGIC_VECTOR (arg'length-1 downto 0);
begin -- function to_std_ulogic_vector
if arg'length < 1 then
return NSLV;
end if;
result := STD_ULOGIC_VECTOR (arg);
return result;
end function to_sulv;
-- Converts an fp into an SLV
function to_slv (arg : UNRESOLVED_float) return STD_LOGIC_VECTOR is
begin
return std_logic_vector (arg);
end function to_slv;
-- purpose: normalizes a floating point number
-- This version assumes an "unsigned" input with
function normalize (
fract : UNSIGNED; -- fraction, unnormalized
expon : SIGNED; -- exponent, normalized by -1
sign : STD_ULOGIC; -- sign BIT
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent
constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float is
variable sfract : UNSIGNED (fract'high downto 0); -- shifted fraction
variable rfract : UNSIGNED (fraction_width-1 downto 0); -- fraction
variable exp : SIGNED (exponent_width+1 downto 0); -- exponent
variable rexp : SIGNED (exponent_width+1 downto 0); -- result exponent
variable rexpon : UNSIGNED (exponent_width-1 downto 0); -- exponent
variable result : UNRESOLVED_float (exponent_width downto -fraction_width); -- result
variable shiftr : INTEGER; -- shift amount
variable stickyx : STD_ULOGIC; -- version of sticky
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable round, zerores, infres : BOOLEAN;
begin -- function normalize
zerores := false;
infres := false;
round := false;
shiftr := find_leftmost (to_01(fract), '1') -- Find the first "1"
- fraction_width - nguard; -- subtract the length we want
exp := resize (expon, exp'length) + shiftr;
if (or_reduce (fract) = '0') then -- Zero
zerores := true;
elsif ((exp <= -resize(expon_base, exp'length)-1) and denormalize)
or ((exp < -resize(expon_base, exp'length)-1) and not denormalize) then
if (exp >= -resize(expon_base, exp'length)-fraction_width-1)
and denormalize then
exp := -resize(expon_base, exp'length)-1;
shiftr := -to_integer (expon + expon_base); -- new shift
else -- return zero
zerores := true;
end if;
elsif (exp > expon_base-1) then -- infinity
infres := true;
end if;
if zerores then
result := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif infres then
result := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
sfract := fract srl shiftr; -- shift
if shiftr > 0 then
-- stickyx := sticky or (or_reduce(fract (shiftr-1 downto 0)));
stickyx := sticky or smallfract (fract, shiftr-1);
else
stickyx := sticky;
end if;
if nguard > 0 then
round := check_round (
fract_in => sfract (nguard),
sign => sign,
remainder => sfract(nguard-1 downto 0),
sticky => stickyx,
round_style => round_style);
end if;
if round then
fp_round(fract_in => sfract (fraction_width-1+nguard downto nguard),
expon_in => exp(rexp'range),
fract_out => rfract,
expon_out => rexp);
else
rfract := sfract (fraction_width-1+nguard downto nguard);
rexp := exp(rexp'range);
end if;
-- result
rexpon := UNSIGNED (rexp(exponent_width-1 downto 0));
rexpon (exponent_width-1) := not rexpon(exponent_width-1);
result (rexpon'range) := UNRESOLVED_float(rexpon);
result (-1 downto -fraction_width) := UNRESOLVED_float(rfract);
end if;
result (exponent_width) := sign; -- sign BIT
return result;
end function normalize;
-- purpose: normalizes a floating point number
-- This version assumes a "ufixed" input
function normalize (
fract : ufixed; -- unsigned fixed point
expon : SIGNED; -- exponent, normalized by -1
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent
constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arguns : UNSIGNED (fract'high + fraction_width + nguard
downto 0) := (others => '0');
begin -- function normalize
arguns (arguns'high downto maximum (arguns'high-fract'length+1, 0)) :=
UNSIGNED (to_slv (fract));
result := normalize (fract => arguns,
expon => expon,
sign => sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => nguard);
return result;
end function normalize;
-- purpose: normalizes a floating point number
-- This version assumes a "ufixed" input with a "size_res" input
function normalize (
fract : ufixed; -- unsigned fixed point
expon : SIGNED; -- exponent, normalized by -1
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
size_res : UNRESOLVED_float; -- used for sizing only
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float is
constant fraction_width : NATURAL := -size_res'low;
constant exponent_width : NATURAL := size_res'high;
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arguns : UNSIGNED (fract'high + fraction_width + nguard
downto 0) := (others => '0');
begin -- function normalize
arguns (arguns'high downto maximum (arguns'high-fract'length+1, 0)) :=
UNSIGNED (to_slv (fract));
result := normalize (fract => arguns,
expon => expon,
sign => sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => nguard);
return result;
end function normalize;
-- Regular "normalize" function with a "size_res" input.
function normalize (
fract : UNSIGNED; -- unsigned
expon : SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
size_res : UNRESOLVED_float; -- used for sizing only
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float is
begin
return normalize (fract => fract,
expon => expon,
sign => sign,
sticky => sticky,
fraction_width => -size_res'low,
exponent_width => size_res'high,
round_style => round_style,
denormalize => denormalize,
nguard => nguard);
end function normalize;
-- Returns the class which X falls into
function Classfp (
x : UNRESOLVED_float; -- floating point input
check_error : BOOLEAN := float_check_error) -- check for errors
return valid_fpstate is
constant fraction_width : INTEGER := -mine(x'low, x'low); -- length of FP output fraction
constant exponent_width : INTEGER := x'high; -- length of FP output exponent
variable arg : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- classfp
if (arg'length < 1 or fraction_width < 3 or exponent_width < 3
or x'left < x'right) then
report "float_pkg"
& "CLASSFP: " &
"Floating point number detected with a bad range"
severity error;
return isx;
end if;
-- Check for "X".
arg := to_01 (x, 'X');
if (arg(0) = 'X') then
return isx; -- If there is an X in the number
-- Special cases, check for illegal number
elsif check_error and
(and_reduce (STD_ULOGIC_VECTOR (arg (exponent_width-1 downto 0)))
= '1') then -- Exponent is all "1".
if or_reduce (to_slv (arg (-1 downto -fraction_width)))
/= '0' then -- Fraction must be all "0" or this is not a number.
if (arg(-1) = '1') then -- From "W. Khan - IEEE standard
return nan; -- 754 binary FP Signaling nan (Not a number)
else
return quiet_nan;
end if;
-- Check for infinity
elsif arg(exponent_width) = '0' then
return pos_inf; -- Positive infinity
else
return neg_inf; -- Negative infinity
end if;
-- check for "0"
elsif or_reduce (STD_LOGIC_VECTOR (arg (exponent_width-1 downto 0)))
= '0' then -- Exponent is all "0"
if or_reduce (to_slv (arg (-1 downto -fraction_width)))
= '0' then -- Fraction is all "0"
if arg(exponent_width) = '0' then
return pos_zero; -- Zero
else
return neg_zero;
end if;
else
if arg(exponent_width) = '0' then
return pos_denormal; -- Denormal number (ieee extended fp)
else
return neg_denormal;
end if;
end if;
else
if arg(exponent_width) = '0' then
return pos_normal; -- Normal FP number
else
return neg_normal;
end if;
end if;
end function Classfp;
procedure break_number (
arg : in UNRESOLVED_float;
denormalize : in BOOLEAN := float_denormalize;
check_error : in BOOLEAN := float_check_error;
fract : out UNSIGNED;
expon : out SIGNED;
sign : out STD_ULOGIC) is
constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction
variable fptyp : valid_fpstate;
begin
fptyp := Classfp (arg, check_error);
sign := to_x01(arg(arg'high));
break_number (
arg => arg,
fptyp => fptyp,
denormalize => denormalize,
fract => fract,
expon => expon);
end procedure break_number;
procedure break_number (
arg : in UNRESOLVED_float;
denormalize : in BOOLEAN := float_denormalize;
check_error : in BOOLEAN := float_check_error;
fract : out ufixed; -- 1 downto -fraction_width
expon : out SIGNED; -- exponent_width-1 downto 0
sign : out STD_ULOGIC) is
constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction
variable fptyp : valid_fpstate;
variable ufract : UNSIGNED (fraction_width downto 0); -- unsigned fraction
begin
fptyp := Classfp (arg, check_error);
sign := to_x01(arg(arg'high));
break_number (
arg => arg,
fptyp => fptyp,
denormalize => denormalize,
fract => ufract,
expon => expon);
fract (0 downto -fraction_width) := ufixed (ufract);
end procedure break_number;
-- Arithmetic functions
function "abs" (
arg : UNRESOLVED_float) -- floating point input
return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range); -- result
begin
if (arg'length > 0) then
result := to_01 (arg, 'X');
result (arg'high) := '0'; -- set the sign bit to positive
return result;
else
return NAFP;
end if;
end function "abs";
-- IEEE 754 "negative" function
function "-" (
arg : UNRESOLVED_float) -- floating point input
return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range); -- result
begin
if (arg'length > 0) then
result := to_01 (arg, 'X');
result (arg'high) := not result (arg'high); -- invert sign bit
return result;
else
return NAFP;
end if;
end function "-";
-- Addition, adds two floating point numbers
function add (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
constant addguard : NATURAL := guard; -- add one guard bit
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable fractl, fractr : UNSIGNED (fraction_width+1+addguard downto 0); -- fractions
variable fractc, fracts : UNSIGNED (fractl'range); -- constant and shifted variables
variable urfract, ulfract : UNSIGNED (fraction_width downto 0);
variable ufract : UNSIGNED (fraction_width+1+addguard downto 0);
variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED (exponent_width downto 0); -- result exponent
variable shiftx : SIGNED (exponent_width downto 0); -- shift fractions
variable sign : STD_ULOGIC; -- sign of the output
variable leftright : BOOLEAN; -- left or right used
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
variable sticky : STD_ULOGIC; -- Holds precision for rounding
begin -- addition
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
if (lfptype = isx or rfptype = isx) then
fpresult := (others => 'X');
elsif (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan)
-- Return quiet NAN, IEEE754-1985-7.1,1
or (lfptype = pos_inf and rfptype = neg_inf)
or (lfptype = neg_inf and rfptype = pos_inf) then
-- Return quiet NAN, IEEE754-1985-7.1,2
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = pos_inf or rfptype = pos_inf) then -- x + inf = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = neg_inf or rfptype = neg_inf) then -- x - inf = -inf
fpresult := neg_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = neg_zero and rfptype = neg_zero) then -- -0 + -0 = -0
fpresult := neg_zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := classfp (rresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => ulfract,
expon => exponl);
fractl := (others => '0');
fractl (fraction_width+addguard downto addguard) := ulfract;
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => urfract,
expon => exponr);
fractr := (others => '0');
fractr (fraction_width+addguard downto addguard) := urfract;
shiftx := (exponl(exponent_width-1) & exponl) - exponr;
if shiftx < -fractl'high then
rexpon := exponr(exponent_width-1) & exponr;
fractc := fractr;
fracts := (others => '0'); -- add zero
leftright := false;
sticky := or_reduce (fractl);
elsif shiftx < 0 then
shiftx := - shiftx;
fracts := shift_right (fractl, to_integer(shiftx));
fractc := fractr;
rexpon := exponr(exponent_width-1) & exponr;
leftright := false;
-- sticky := or_reduce (fractl (to_integer(shiftx) downto 0));
sticky := smallfract (fractl, to_integer(shiftx));
elsif shiftx = 0 then
rexpon := exponl(exponent_width-1) & exponl;
sticky := '0';
if fractr > fractl then
fractc := fractr;
fracts := fractl;
leftright := false;
else
fractc := fractl;
fracts := fractr;
leftright := true;
end if;
elsif shiftx > fractr'high then
rexpon := exponl(exponent_width-1) & exponl;
fracts := (others => '0'); -- add zero
fractc := fractl;
leftright := true;
sticky := or_reduce (fractr);
elsif shiftx > 0 then
fracts := shift_right (fractr, to_integer(shiftx));
fractc := fractl;
rexpon := exponl(exponent_width-1) & exponl;
leftright := true;
-- sticky := or_reduce (fractr (to_integer(shiftx) downto 0));
sticky := smallfract (fractr, to_integer(shiftx));
end if;
-- add
fracts (0) := fracts (0) or sticky; -- Or the sticky bit into the LSB
if l(l'high) = r(r'high) then
ufract := fractc + fracts;
sign := l(l'high);
else -- signs are different
ufract := fractc - fracts; -- always positive result
if leftright then -- Figure out which sign to use
sign := l(l'high);
else
sign := r(r'high);
end if;
end if;
if or_reduce (ufract) = '0' then
sign := '0'; -- IEEE 854, 6.3, paragraph 2.
end if;
-- normalize
fpresult := normalize (fract => ufract,
expon => rexpon,
sign => sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => addguard);
end if;
return fpresult;
end function add;
-- Subtraction, Calls "add".
function subtract (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
variable negr : UNRESOLVED_float (r'range); -- negative version of r
begin
negr := -r;
return add (l => l,
r => negr,
round_style => round_style,
guard => guard,
check_error => check_error,
denormalize => denormalize);
end function subtract;
-- Floating point multiply
function multiply (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
constant multguard : NATURAL := guard; -- guard bits
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable fractl, fractr : UNSIGNED (fraction_width downto 0); -- fractions
variable rfract : UNSIGNED ((2*(fraction_width))+1 downto 0); -- result fraction
variable sfract : UNSIGNED (fraction_width+1+multguard downto 0); -- result fraction
variable shifty : INTEGER; -- denormal shift
variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED (exponent_width+1 downto 0); -- result exponent
variable fp_sign : STD_ULOGIC; -- sign of result
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
variable sticky : STD_ULOGIC; -- Holds precision for rounding
begin -- multiply
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
if (lfptype = isx or rfptype = isx) then
fpresult := (others => 'X');
elsif ((lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan)) then
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (((lfptype = pos_inf or lfptype = neg_inf) and
(rfptype = pos_zero or rfptype = neg_zero)) or
((rfptype = pos_inf or rfptype = neg_inf) and
(lfptype = pos_zero or lfptype = neg_zero))) then -- 0 * inf
-- Return quiet NAN, IEEE754-1985-7.1,3
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = pos_inf or rfptype = pos_inf
or lfptype = neg_inf or rfptype = neg_inf) then -- x * inf = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
-- figure out the sign
fp_sign := l(l'high) xor r(r'high); -- figure out the sign
fpresult (exponent_width) := fp_sign;
else
fp_sign := l(l'high) xor r(r'high); -- figure out the sign
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := classfp (rresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => fractl,
expon => exponl);
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => fractr,
expon => exponr);
if (rfptype = pos_denormal or rfptype = neg_denormal) then
shifty := fraction_width - find_leftmost(fractr, '1');
fractr := shift_left (fractr, shifty);
elsif (lfptype = pos_denormal or lfptype = neg_denormal) then
shifty := fraction_width - find_leftmost(fractl, '1');
fractl := shift_left (fractl, shifty);
else
shifty := 0;
-- Note that a denormal number * a denormal number is always zero.
end if;
-- multiply
-- add the exponents
rexpon := resize (exponl, rexpon'length) + exponr - shifty + 1;
rfract := fractl * fractr; -- Multiply the fraction
sfract := rfract (rfract'high downto
rfract'high - (fraction_width+1+multguard));
sticky := or_reduce (rfract (rfract'high-(fraction_width+1+multguard)
downto 0));
-- normalize
fpresult := normalize (fract => sfract,
expon => rexpon,
sign => fp_sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => multguard);
end if;
return fpresult;
end function multiply;
function short_divide (
lx, rx : UNSIGNED)
return UNSIGNED is
-- This is a special divider for the floating point routines.
-- For a true unsigned divider, "stages" needs to = lx'high
constant stages : INTEGER := lx'high - rx'high; -- number of stages
variable partial : UNSIGNED (lx'range);
variable q : UNSIGNED (stages downto 0);
variable partial_argl : SIGNED (rx'high + 2 downto 0);
variable partial_arg : SIGNED (rx'high + 2 downto 0);
begin
partial := lx;
for i in stages downto 0 loop
partial_argl := resize ("0" & SIGNED (partial(lx'high downto i)),
partial_argl'length);
partial_arg := partial_argl - SIGNED ("0" & rx);
if (partial_arg (partial_arg'high) = '1') then -- negative
q(i) := '0';
else
q(i) := '1';
partial (lx'high+i-stages downto lx'high+i-stages-rx'high) :=
UNSIGNED (partial_arg(rx'range));
end if;
end loop;
-- to make the output look like that of the unsigned IEEE divide.
return resize (q, lx'length);
end function short_divide;
-- 1/X function. Needed for algorithm development.
function reciprocal (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : NATURAL := arg'high; -- length of FP output exponent
constant divguard : NATURAL := guard; -- guard bits
function onedivy (
arg : UNSIGNED)
return UNSIGNED is
variable q : UNSIGNED((2*arg'high)+1 downto 0);
variable one : UNSIGNED (q'range);
begin
one := (others => '0');
one(one'high) := '1';
q := short_divide (one, arg); -- Unsigned divide
return resize (q, arg'length+1);
end function onedivy;
variable fptype : valid_fpstate;
variable expon : SIGNED (exponent_width-1 downto 0); -- exponents
variable denorm_offset : NATURAL range 0 to 2;
variable fract : UNSIGNED (fraction_width downto 0);
variable fractg : UNSIGNED (fraction_width+divguard downto 0);
variable sfract : UNSIGNED (fraction_width+1+divguard downto 0); -- result fraction
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- reciprocal
fptype := classfp(arg, check_error);
classcase : case fptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf => -- 1/inf, return 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
when neg_zero | pos_zero => -- 1/0
report "float_pkg"
& "RECIPROCAL: Floating Point divide by zero"
severity error;
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
when others =>
if (fptype = pos_denormal or fptype = neg_denormal)
and ((arg (-1) or arg(-2)) /= '1') then
-- 1/denormal = infinity, with the exception of 2**-expon_base
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fpresult (exponent_width) := to_x01 (arg (exponent_width));
else
break_number (
arg => arg,
fptyp => fptype,
denormalize => denormalize,
fract => fract,
expon => expon);
fractg := (others => '0');
if (fptype = pos_denormal or fptype = neg_denormal) then
-- The reciprocal of a denormal number is typically zero,
-- except for two special cases which are trapped here.
if (to_x01(arg (-1)) = '1') then
fractg (fractg'high downto divguard+1) :=
fract (fract'high-1 downto 0); -- Shift to not denormal
denorm_offset := 1; -- add 1 to exponent compensate
else -- arg(-2) = '1'
fractg (fractg'high downto divguard+2) :=
fract (fract'high-2 downto 0); -- Shift to not denormal
denorm_offset := 2; -- add 2 to exponent compensate
end if;
else
fractg (fractg'high downto divguard) := fract;
denorm_offset := 0;
end if;
expon := - expon - 3 + denorm_offset;
sfract := onedivy (fractg);
-- normalize
fpresult := normalize (fract => sfract,
expon => expon,
sign => arg(exponent_width),
sticky => '1',
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => divguard);
end if;
end case classcase;
return fpresult;
end function reciprocal;
-- floating point division
function divide (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
constant divguard : NATURAL := guard; -- division guard bits
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable ulfract, urfract : UNSIGNED (fraction_width downto 0);
variable fractl : UNSIGNED ((2*(fraction_width+divguard)+1) downto 0); -- left
variable fractr : UNSIGNED (fraction_width+divguard downto 0); -- right
variable rfract : UNSIGNED (fractl'range); -- result fraction
variable sfract : UNSIGNED (fraction_width+1+divguard downto 0); -- result fraction
variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED (exponent_width+1 downto 0); -- result exponent
variable fp_sign, sticky : STD_ULOGIC; -- sign of result
variable shifty, shiftx : INTEGER; -- denormal number shift
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- divide
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
classcase : case rfptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf =>
if lfptype = pos_inf or lfptype = neg_inf -- inf / inf
or lfptype = quiet_nan or lfptype = nan then
-- Return quiet NAN, IEEE754-1985-7.1,4
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
else -- x / inf = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (fpresult'high) := fp_sign; -- sign
end if;
when pos_zero | neg_zero =>
if lfptype = pos_zero or lfptype = neg_zero -- 0 / 0
or lfptype = quiet_nan or lfptype = nan then
-- Return quiet NAN, IEEE754-1985-7.1,4
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
report "float_pkg"
& "DIVIDE: Floating Point divide by zero"
severity error;
-- Infinity, define in 754-1985-7.2
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (fpresult'high) := fp_sign; -- sign
end if;
when others =>
classcase2 : case lfptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf => -- inf / x = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult(exponent_width) := fp_sign;
when pos_zero | neg_zero => -- 0 / X = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult(exponent_width) := fp_sign;
when others =>
fp_sign := l(l'high) xor r(r'high); -- sign
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := classfp (rresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => ulfract,
expon => exponl);
-- right side
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => urfract,
expon => exponr);
-- Compute the exponent
rexpon := resize( resize(exponl, rexpon'length) - exponr - 2, rexpon'length );---resize (exponl, rexpon'length) - exponr - 2; ---CAMBIADO
if (rfptype = pos_denormal or rfptype = neg_denormal) then
-- Do the shifting here not after. That way we have a smaller
-- shifter, and need a smaller divider, because the top
-- bit in the divisor will always be a "1".
shifty := fraction_width - find_leftmost(urfract, '1');
urfract := shift_left (urfract, shifty);
rexpon := rexpon + shifty;
end if;
fractr := (others => '0');
fractr (fraction_width+divguard downto divguard) := urfract;
if (lfptype = pos_denormal or lfptype = neg_denormal) then
shiftx := fraction_width - find_leftmost(ulfract, '1');
ulfract := shift_left (ulfract, shiftx);
rexpon := rexpon - shiftx;
end if;
fractl := (others => '0');
fractl (fractl'high downto fractl'high-fraction_width) := ulfract;
-- divide
rfract := short_divide (fractl, fractr); -- unsigned divide
sfract := rfract (sfract'range); -- lower bits
sticky := '1';
-- normalize
fpresult := normalize (fract => sfract,
expon => rexpon,
sign => fp_sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => divguard);
end case classcase2;
end case classcase;
return fpresult;
end function divide;
-- division by a power of 2
function dividebyp2 (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable ulfract, urfract : UNSIGNED (fraction_width downto 0);
variable exponl, exponr : SIGNED(exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED(exponent_width downto 0); -- result exponent
variable fp_sign : STD_ULOGIC; -- sign of result
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- divisionbyp2
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
classcase : case rfptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf =>
if lfptype = pos_inf or lfptype = neg_inf then -- inf / inf
-- Return quiet NAN, IEEE754-1985-7.1,4
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
else -- x / inf = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (fpresult'high) := fp_sign; -- sign
end if;
when pos_zero | neg_zero =>
if lfptype = pos_zero or lfptype = neg_zero then -- 0 / 0
-- Return quiet NAN, IEEE754-1985-7.1,4
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
report "float_pkg"
& "DIVIDEBYP2: Floating Point divide by zero"
severity error;
-- Infinity, define in 754-1985-7.2
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (fpresult'high) := fp_sign; -- sign
end if;
when others =>
classcase2 : case lfptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf => -- inf / x = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (exponent_width) := fp_sign; -- sign
when pos_zero | neg_zero => -- 0 / X = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (exponent_width) := fp_sign; -- sign
when others =>
fp_sign := l(l'high) xor r(r'high); -- sign
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := classfp (rresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => ulfract,
expon => exponl);
-- right side
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => urfract,
expon => exponr);
assert (or_reduce (urfract (fraction_width-1 downto 0)) = '0')
report "float_pkg"
& "DIVIDEBYP2: "
& "Dividebyp2 called with a non power of two divisor"
severity error;
rexpon := (exponl(exponl'high)&exponl)
- (exponr(exponr'high)&exponr) - 1;
-- normalize
fpresult := normalize (fract => ulfract,
expon => rexpon,
sign => fp_sign,
sticky => '1',
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => 0);
end case classcase2;
end case classcase;
return fpresult;
end function dividebyp2;
-- Multiply accumulate result = l*r + c
function mac (
l, r, c : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL :=
-mine (mine(l'low, r'low), c'low); -- length of FP output fraction
constant exponent_width : NATURAL :=
maximum (maximum(l'high, r'high), c'high); -- length of FP output exponent
variable lfptype, rfptype, cfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable fractl, fractr : UNSIGNED (fraction_width downto 0); -- fractions
variable fractx : UNSIGNED (fraction_width+guard downto 0);
variable fractc, fracts : UNSIGNED (fraction_width+1+guard downto 0);
variable rfract : UNSIGNED ((2*(fraction_width))+1 downto 0); -- result fraction
variable sfract, ufract : UNSIGNED (fraction_width+1+guard downto 0); -- result fraction
variable exponl, exponr, exponc : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon, rexpon2 : SIGNED (exponent_width+1 downto 0); -- result exponent
variable shifty : INTEGER; -- denormal shift
variable shiftx : SIGNED (rexpon'range); -- shift fractions
variable fp_sign : STD_ULOGIC; -- sign of result
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
variable cresize : UNRESOLVED_float (exponent_width downto -fraction_width - guard);
variable leftright : BOOLEAN; -- left or right used
variable sticky : STD_ULOGIC; -- Holds precision for rounding
begin -- multiply
if (fraction_width = 0 or l'length < 7 or r'length < 7 or c'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
cfptype := classfp (c, check_error);
end if;
if (lfptype = isx or rfptype = isx or cfptype = isx) then
fpresult := (others => 'X');
elsif (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan or
cfptype = nan or cfptype = quiet_nan) then
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (((lfptype = pos_inf or lfptype = neg_inf) and
(rfptype = pos_zero or rfptype = neg_zero)) or
((rfptype = pos_inf or rfptype = neg_inf) and
(lfptype = pos_zero or lfptype = neg_zero))) then -- 0 * inf
-- Return quiet NAN, IEEE754-1985-7.1,3
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = pos_inf or rfptype = pos_inf
or lfptype = neg_inf or rfptype = neg_inf -- x * inf = inf
or cfptype = neg_inf or cfptype = pos_inf) then -- x + inf = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
-- figure out the sign
fpresult (exponent_width) := l(l'high) xor r(r'high);
else
fp_sign := l(l'high) xor r(r'high); -- figure out the sign
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := classfp (rresize, false); -- errors already checked
cresize := resize (arg => to_x01(c),
exponent_width => exponent_width,
fraction_width => -cresize'low,
denormalize_in => denormalize,
denormalize => denormalize);
cfptype := classfp (cresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => fractl,
expon => exponl);
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => fractr,
expon => exponr);
break_number (
arg => cresize,
fptyp => cfptype,
denormalize => denormalize,
fract => fractx,
expon => exponc);
if (rfptype = pos_denormal or rfptype = neg_denormal) then
shifty := fraction_width - find_leftmost(fractr, '1');
fractr := shift_left (fractr, shifty);
elsif (lfptype = pos_denormal or lfptype = neg_denormal) then
shifty := fraction_width - find_leftmost(fractl, '1');
fractl := shift_left (fractl, shifty);
else
shifty := 0;
-- Note that a denormal number * a denormal number is always zero.
end if;
-- multiply
rfract := fractl * fractr; -- Multiply the fraction
-- add the exponents
rexpon := resize (exponl, rexpon'length) + exponr - shifty + 1;
shiftx := rexpon - exponc;
if shiftx < -fractl'high then
rexpon2 := resize (exponc, rexpon2'length);
fractc := "0" & fractx;
fracts := (others => '0');
sticky := or_reduce (rfract);
elsif shiftx < 0 then
shiftx := - shiftx;
fracts := shift_right (rfract (rfract'high downto rfract'high
- fracts'length+1),
to_integer(shiftx));
fractc := "0" & fractx;
rexpon2 := resize (exponc, rexpon2'length);
leftright := false;
sticky := or_reduce (rfract (to_integer(shiftx)+rfract'high
- fracts'length downto 0));
elsif shiftx = 0 then
rexpon2 := resize (exponc, rexpon2'length);
sticky := or_reduce (rfract (rfract'high - fractc'length downto 0));
if rfract (rfract'high downto rfract'high - fractc'length+1) > fractx
then
fractc := "0" & fractx;
fracts := rfract (rfract'high downto rfract'high
- fracts'length+1);
leftright := false;
else
fractc := rfract (rfract'high downto rfract'high
- fractc'length+1);
fracts := "0" & fractx;
leftright := true;
end if;
elsif shiftx > fractx'high then
rexpon2 := rexpon;
fracts := (others => '0');
fractc := rfract (rfract'high downto rfract'high - fractc'length+1);
leftright := true;
sticky := or_reduce (fractx & rfract (rfract'high - fractc'length
downto 0));
else -- fractx'high > shiftx > 0
rexpon2 := rexpon;
fracts := "0" & shift_right (fractx, to_integer (shiftx));
fractc := rfract (rfract'high downto rfract'high - fractc'length+1);
leftright := true;
sticky := or_reduce (fractx (to_integer (shiftx) downto 0)
& rfract (rfract'high - fractc'length downto 0));
end if;
fracts (0) := fracts (0) or sticky; -- Or the sticky bit into the LSB
if fp_sign = to_X01(c(c'high)) then
ufract := fractc + fracts;
fp_sign := fp_sign;
else -- signs are different
ufract := fractc - fracts; -- always positive result
if leftright then -- Figure out which sign to use
fp_sign := fp_sign;
else
fp_sign := c(c'high);
end if;
end if;
-- normalize
fpresult := normalize (fract => ufract,
expon => rexpon2,
sign => fp_sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => guard);
end if;
return fpresult;
end function mac;
-- "rem" function
function remainder (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
constant divguard : NATURAL := guard; -- division guard bits
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable ulfract, urfract : UNSIGNED (fraction_width downto 0);
variable fractr, fractl : UNSIGNED (fraction_width+divguard downto 0); -- right
variable rfract : UNSIGNED (fractr'range); -- result fraction
variable sfract : UNSIGNED (fraction_width+divguard downto 0); -- result fraction
variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED (exponent_width downto 0); -- result exponent
variable fp_sign : STD_ULOGIC; -- sign of result
variable shifty : INTEGER; -- denormal number shift
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- remainder
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
if (lfptype = isx or rfptype = isx) then
fpresult := (others => 'X');
elsif (lfptype = nan or lfptype = quiet_nan)
or (rfptype = nan or rfptype = quiet_nan)
-- Return quiet NAN, IEEE754-1985-7.1,1
or (lfptype = pos_inf or lfptype = neg_inf) -- inf rem x
-- Return quiet NAN, IEEE754-1985-7.1,5
or (rfptype = pos_zero or rfptype = neg_zero) then -- x rem 0
-- Return quiet NAN, IEEE754-1985-7.1,5
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (rfptype = pos_inf or rfptype = neg_inf) then -- x rem inf = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (abs(l) < abs(r)) then
fpresult := l;
else
fp_sign := to_X01(l(l'high)); -- sign
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := classfp (rresize, false); -- errors already checked
fractl := (others => '0');
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => ulfract,
expon => exponl);
fractl (fraction_width+divguard downto divguard) := ulfract;
-- right side
fractr := (others => '0');
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => urfract,
expon => exponr);
fractr (fraction_width+divguard downto divguard) := urfract;
rexpon := (exponr(exponr'high)&exponr);
shifty := to_integer(exponl - rexpon);
if (shifty > 0) then
fractr := shift_right (fractr, shifty);
rexpon := rexpon + shifty;
end if;
if (fractr /= 0) then
-- rem
rfract := fractl rem fractr; -- unsigned rem
sfract := rfract (sfract'range); -- lower bits
-- normalize
fpresult := normalize (fract => sfract,
expon => rexpon,
sign => fp_sign,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => divguard);
else
-- If we shift "fractr" so far that it becomes zero, return zero.
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
end if;
end if;
return fpresult;
end function remainder;
-- "mod" function
function modulo (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := - mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable remres : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- remainder
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
if (lfptype = isx or rfptype = isx) then
fpresult := (others => 'X');
elsif (lfptype = nan or lfptype = quiet_nan)
or (rfptype = nan or rfptype = quiet_nan)
-- Return quiet NAN, IEEE754-1985-7.1,1
or (lfptype = pos_inf or lfptype = neg_inf) -- inf rem x
-- Return quiet NAN, IEEE754-1985-7.1,5
or (rfptype = pos_zero or rfptype = neg_zero) then -- x rem 0
-- Return quiet NAN, IEEE754-1985-7.1,5
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (rfptype = pos_inf or rfptype = neg_inf) then -- x rem inf = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
remres := remainder (l => abs(l),
r => abs(r),
round_style => round_style,
guard => guard,
check_error => false,
denormalize => denormalize);
-- MOD is the same as REM, but you do something different with
-- negative values
if (is_negative (l)) then
remres := - remres;
end if;
if (is_negative (l) = is_negative (r) or remres = 0) then
fpresult := remres;
else
fpresult := add (l => remres,
r => r,
round_style => round_style,
guard => guard,
check_error => false,
denormalize => denormalize);
end if;
end if;
return fpresult;
end function modulo;
-- Square root of a floating point number. Done using Newton's Iteration.
function sqrt (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style;
constant guard : NATURAL := float_guard_bits;
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_float is
constant fraction_width : NATURAL := guard-arg'low; -- length of FP output fraction
constant exponent_width : NATURAL := arg'high; -- length of FP output exponent
variable sign : STD_ULOGIC;
variable fpresult : float (arg'range);
variable fptype : valid_fpstate;
variable iexpon : SIGNED(exponent_width-1 downto 0); -- exponents
variable expon : SIGNED(exponent_width downto 0); -- exponents
variable ufact : ufixed (0 downto arg'low);
variable fact : ufixed (2 downto -fraction_width); -- fraction
variable resb : ufixed (fact'high+1 downto fact'low);
begin -- square root
fptype := Classfp (arg, check_error);
classcase : case fptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan |
-- Return quiet NAN, IEEE754-1985-7.1,1
neg_normal | neg_denormal | neg_inf => -- sqrt (neg)
-- Return quiet NAN, IEEE754-1985-7.1.6
fpresult := qnanfp (fraction_width => fraction_width-guard,
exponent_width => exponent_width);
when pos_inf => -- Sqrt (inf), return infinity
fpresult := pos_inffp (fraction_width => fraction_width-guard,
exponent_width => exponent_width);
when pos_zero => -- return 0
fpresult := zerofp (fraction_width => fraction_width-guard,
exponent_width => exponent_width);
when neg_zero => -- IEEE754-1985-6.3 return -0
fpresult := neg_zerofp (fraction_width => fraction_width-guard,
exponent_width => exponent_width);
when others =>
break_number (arg => arg,
denormalize => denormalize,
check_error => false,
fract => ufact,
expon => iexpon,
sign => sign);
expon := resize (iexpon+1, expon'length); -- get exponent
fact := resize (ufact, fact'high, fact'low);
if (expon(0) = '1') then
fact := fact sla 1; -- * 2.0
end if;
expon := shift_right (expon, 1); -- exponent/2
-- Newton's iteration - root := (1 + arg) / 2
resb := (fact + 1) sra 1;
for j in 0 to fraction_width/4 loop
-- root := (root + (arg/root))/2
resb := resize (arg => (resb + (fact/resb)) sra 1,
left_index => resb'high,
right_index => resb'low,
round_style => fixed_truncate,
overflow_style => fixed_wrap);
end loop;
fpresult := normalize (fract => resb,
expon => expon-1,
sign => '0',
exponent_width => arg'high,
fraction_width => -arg'low,
round_style => round_style,
denormalize => denormalize,
nguard => guard);
end case classcase;
return fpresult;
end function sqrt;
function Is_Negative (arg : UNRESOLVED_float) return BOOLEAN is
-- Technically -0 should return "false", but I'm leaving that case out.
begin
return (to_x01(arg(arg'high)) = '1');
end function Is_Negative;
-- compare functions
-- =, /=, >=, <=, <, >
function eq ( -- equal =
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN is
variable lfptype, rfptype : valid_fpstate;
variable is_equal, is_unordered : BOOLEAN;
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- equal
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return false;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
if (lfptype = neg_zero or lfptype = pos_zero) and
(rfptype = neg_zero or rfptype = pos_zero) then
is_equal := true;
else
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
is_equal := (to_slv(lresize) = to_slv(rresize));
end if;
if (check_error) then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return is_equal and not is_unordered;
end function eq;
function lt ( -- less than <
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable expl, expr : UNSIGNED (exponent_width-1 downto 0);
variable fractl, fractr : UNSIGNED (fraction_width-1 downto 0);
variable is_less_than, is_unordered : BOOLEAN;
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
is_less_than := false;
else
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
if to_x01(l(l'high)) = to_x01(r(r'high)) then -- sign bits
expl := UNSIGNED(lresize(exponent_width-1 downto 0));
expr := UNSIGNED(rresize(exponent_width-1 downto 0));
if expl = expr then
fractl := UNSIGNED (to_slv(lresize(-1 downto -fraction_width)));
fractr := UNSIGNED (to_slv(rresize(-1 downto -fraction_width)));
if to_x01(l(l'high)) = '0' then -- positive number
is_less_than := (fractl < fractr);
else
is_less_than := (fractl > fractr); -- negative
end if;
else
if to_x01(l(l'high)) = '0' then -- positive number
is_less_than := (expl < expr);
else
is_less_than := (expl > expr); -- negative
end if;
end if;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
if (lfptype = neg_zero and rfptype = pos_zero) then
is_less_than := false; -- -0 < 0 returns false.
else
is_less_than := (to_x01(l(l'high)) > to_x01(r(r'high)));
end if;
end if;
end if;
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return is_less_than and not is_unordered;
end function lt;
function gt ( -- greater than >
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable expl, expr : UNSIGNED (exponent_width-1 downto 0);
variable fractl, fractr : UNSIGNED (fraction_width-1 downto 0);
variable is_greater_than : BOOLEAN;
variable is_unordered : BOOLEAN;
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- greater_than
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
is_greater_than := false;
else
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
if to_x01(l(l'high)) = to_x01(r(r'high)) then -- sign bits
expl := UNSIGNED(lresize(exponent_width-1 downto 0));
expr := UNSIGNED(rresize(exponent_width-1 downto 0));
if expl = expr then
fractl := UNSIGNED (to_slv(lresize(-1 downto -fraction_width)));
fractr := UNSIGNED (to_slv(rresize(-1 downto -fraction_width)));
if to_x01(l(l'high)) = '0' then -- positive number
is_greater_than := fractl > fractr;
else
is_greater_than := fractl < fractr; -- negative
end if;
else
if to_x01(l(l'high)) = '0' then -- positive number
is_greater_than := expl > expr;
else
is_greater_than := expl < expr; -- negative
end if;
end if;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
if (lfptype = pos_zero and rfptype = neg_zero) then
is_greater_than := false; -- 0 > -0 returns false.
else
is_greater_than := to_x01(l(l'high)) < to_x01(r(r'high));
end if;
end if;
end if;
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return is_greater_than and not is_unordered;
end function gt;
-- purpose: /= function
function ne ( -- not equal /=
l, r : UNRESOLVED_float;
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN is
variable is_equal, is_unordered : BOOLEAN;
begin
is_equal := eq (l => l,
r => r,
check_error => false,
denormalize => denormalize);
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return not (is_equal and not is_unordered);
end function ne;
function le ( -- less than or equal to <=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN is
variable is_greater_than, is_unordered : BOOLEAN;
begin
is_greater_than := gt (l => l,
r => r,
check_error => false,
denormalize => denormalize);
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return not is_greater_than and not is_unordered;
end function le;
function ge ( -- greater than or equal to >=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN is
variable is_less_than, is_unordered : BOOLEAN;
begin
is_less_than := lt (l => l,
r => r,
check_error => false,
denormalize => denormalize);
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return not is_less_than and not is_unordered;
end function ge;
function \?=\ (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable is_equal, is_unordered : STD_ULOGIC;
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- ?=
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
else
lfptype := classfp (l, float_check_error);
rfptype := classfp (r, float_check_error);
end if;
if (lfptype = neg_zero or lfptype = pos_zero) and
(rfptype = neg_zero or rfptype = pos_zero) then
is_equal := '1';
else
lresize := resize (arg => l,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => float_denormalize,
denormalize => float_denormalize);
rresize := resize (arg => r,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => float_denormalize,
denormalize => float_denormalize);
is_equal := \?=\ (to_sulv(lresize), to_sulv(rresize));
end if;
if (float_check_error) then
if (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan) then
is_unordered := '1';
else
is_unordered := '0';
end if;
else
is_unordered := '0';
end if;
return is_equal and not is_unordered;
end function \?=\;
function \?/=\ (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable is_equal, is_unordered : STD_ULOGIC;
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- ?/=
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
else
lfptype := classfp (l, float_check_error);
rfptype := classfp (r, float_check_error);
end if;
if (lfptype = neg_zero or lfptype = pos_zero) and
(rfptype = neg_zero or rfptype = pos_zero) then
is_equal := '1';
else
lresize := resize (arg => l,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => float_denormalize,
denormalize => float_denormalize);
rresize := resize (arg => r,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => float_denormalize,
denormalize => float_denormalize);
is_equal := \?=\ (to_sulv(lresize), to_sulv(rresize));
end if;
if (float_check_error) then
if (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan) then
is_unordered := '1';
else
is_unordered := '0';
end if;
else
is_unordered := '0';
end if;
return not (is_equal and not is_unordered);
end function \?/=\;
function \?>\ (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(l'low, r'low);
variable founddash : BOOLEAN := false;
begin
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
else
for i in L'range loop
if L(i) = '-' then
founddash := true;
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
founddash := true;
end if;
end loop;
if founddash then
report "float_pkg"
& " ""?>"": '-' found in compare string"
severity error;
return 'X';
elsif is_x(l) or is_x(r) then
return 'X';
elsif l > r then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
function \?>=\ (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(l'low, r'low);
variable founddash : BOOLEAN := false;
begin
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
else
for i in L'range loop
if L(i) = '-' then
founddash := true;
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
founddash := true;
end if;
end loop;
if founddash then
report "float_pkg"
& " ""?>="": '-' found in compare string"
severity error;
return 'X';
elsif is_x(l) or is_x(r) then
return 'X';
elsif l >= r then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
function \?<\ (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(l'low, r'low);
variable founddash : BOOLEAN := false;
begin
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
else
for i in L'range loop
if L(i) = '-' then
founddash := true;
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
founddash := true;
end if;
end loop;
if founddash then
report "float_pkg"
& " ""?<"": '-' found in compare string"
severity error;
return 'X';
elsif is_x(l) or is_x(r) then
return 'X';
elsif l < r then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
function \?<=\ (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(l'low, r'low);
variable founddash : BOOLEAN := false;
begin
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
else
for i in L'range loop
if L(i) = '-' then
founddash := true;
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
founddash := true;
end if;
end loop;
if founddash then
report "float_pkg"
& " ""?<="": '-' found in compare string"
severity error;
return 'X';
elsif is_x(l) or is_x(r) then
return 'X';
elsif l <= r then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
function std_match (L, R : UNRESOLVED_float) return BOOLEAN is
begin
if (L'high = R'high and L'low = R'low) then
return std_match(to_sulv(L), to_sulv(R));
else
report "float_pkg"
& "STD_MATCH: L'RANGE /= R'RANGE, returning FALSE"
severity warning;
return false;
end if;
end function std_match;
function find_rightmost (arg : UNRESOLVED_float; y : STD_ULOGIC) return INTEGER is
begin
for_loop : for i in arg'reverse_range loop
if \?=\ (arg(i), y) = '1' then
return i;
end if;
end loop;
return arg'high+1; -- return out of bounds 'high
end function find_rightmost;
function find_leftmost (arg : UNRESOLVED_float; y : STD_ULOGIC) return INTEGER is
begin
for_loop : for i in arg'range loop
if \?=\ (arg(i), y) = '1' then
return i;
end if;
end loop;
return arg'low-1; -- return out of bounds 'low
end function find_leftmost;
-- These override the defaults for the compare operators.
function "=" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return eq(l, r);
end function "=";
function "/=" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return ne(l, r);
end function "/=";
function ">=" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return ge(l, r);
end function ">=";
function "<=" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return le(l, r);
end function "<=";
function ">" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return gt(l, r);
end function ">";
function "<" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return lt(l, r);
end function "<";
-- purpose: maximum of two numbers (overrides default)
function maximum (
L, R : UNRESOLVED_float)
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin
if ((L'length < 1) or (R'length < 1)) then return NAFP;
end if;
lresize := resize (l, exponent_width, fraction_width);
rresize := resize (r, exponent_width, fraction_width);
if lresize > rresize then return lresize;
else return rresize;
end if;
end function maximum;
function minimum (
L, R : UNRESOLVED_float)
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin
if ((L'length < 1) or (R'length < 1)) then return NAFP;
end if;
lresize := resize (l, exponent_width, fraction_width);
rresize := resize (r, exponent_width, fraction_width);
if lresize > rresize then return rresize;
else return lresize;
end if;
end function minimum;
-----------------------------------------------------------------------------
-- conversion functions
-----------------------------------------------------------------------------
-- Converts a floating point number of one format into another format
function resize (
arg : UNRESOLVED_float; -- Floating point input
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant in_fraction_width : NATURAL := -arg'low; -- length of FP output fraction
constant in_exponent_width : NATURAL := arg'high; -- length of FP output exponent
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
-- result value
variable fptype : valid_fpstate;
variable expon_in : SIGNED (in_exponent_width-1 downto 0);
variable fract_in : UNSIGNED (in_fraction_width downto 0);
variable round : BOOLEAN;
variable expon_out : SIGNED (exponent_width-1 downto 0); -- output fract
variable fract_out : UNSIGNED (fraction_width downto 0); -- output fract
variable passguard : NATURAL;
begin
fptype := classfp(arg, check_error);
if ((fptype = pos_denormal or fptype = neg_denormal) and denormalize_in
and (in_exponent_width < exponent_width
or in_fraction_width < fraction_width))
or in_exponent_width > exponent_width
or in_fraction_width > fraction_width then
-- size reduction
classcase : case fptype is
when isx =>
result := (others => 'X');
when nan | quiet_nan =>
result := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf =>
result := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
when neg_inf =>
result := neg_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_zero | neg_zero =>
result := zerofp (fraction_width => fraction_width, -- hate -0
exponent_width => exponent_width);
when others =>
break_number (
arg => arg,
fptyp => fptype,
denormalize => denormalize_in,
fract => fract_in,
expon => expon_in);
if fraction_width > in_fraction_width and denormalize_in then
-- You only get here if you have a denormal input
fract_out := (others => '0'); -- pad with zeros
fract_out (fraction_width downto
fraction_width - in_fraction_width) := fract_in;
result := normalize (
fract => fract_out,
expon => expon_in,
sign => arg(arg'high),
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => 0);
else
result := normalize (
fract => fract_in,
expon => expon_in,
sign => arg(arg'high),
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => in_fraction_width - fraction_width);
end if;
end case classcase;
else -- size increase or the same size
if exponent_width > in_exponent_width then
expon_in := SIGNED(arg (in_exponent_width-1 downto 0));
if fptype = pos_zero or fptype = neg_zero then
result (exponent_width-1 downto 0) := (others => '0');
elsif expon_in = -1 then -- inf or nan (shorts out check_error)
result (exponent_width-1 downto 0) := (others => '1');
else
-- invert top BIT
expon_in(expon_in'high) := not expon_in(expon_in'high);
expon_out := resize (expon_in, expon_out'length); -- signed expand
-- Flip it back.
expon_out(expon_out'high) := not expon_out(expon_out'high);
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon_out);
end if;
result (exponent_width) := arg (in_exponent_width); -- sign
else -- exponent_width = in_exponent_width
result (exponent_width downto 0) := arg (in_exponent_width downto 0);
end if;
if fraction_width > in_fraction_width then
result (-1 downto -fraction_width) := (others => '0'); -- zeros
result (-1 downto -in_fraction_width) :=
arg (-1 downto -in_fraction_width);
else -- fraction_width = in_fraciton_width
result (-1 downto -fraction_width) :=
arg (-1 downto -in_fraction_width);
end if;
end if;
return result;
end function resize;
function resize (
arg : UNRESOLVED_float; -- floating point input
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := resize (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style,
check_error => check_error,
denormalize_in => denormalize_in,
denormalize => denormalize);
return result;
end if;
end function resize;
function to_float32 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float32 is
begin
return resize (arg => arg,
exponent_width => float32'high,
fraction_width => -float32'low,
round_style => round_style,
check_error => check_error,
denormalize_in => denormalize_in,
denormalize => denormalize);
end function to_float32;
function to_float64 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float64 is
begin
return resize (arg => arg,
exponent_width => float64'high,
fraction_width => -float64'low,
round_style => round_style,
check_error => check_error,
denormalize_in => denormalize_in,
denormalize => denormalize);
end function to_float64;
function to_float128 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float128 is
begin
return resize (arg => arg,
exponent_width => float128'high,
fraction_width => -float128'low,
round_style => round_style,
check_error => check_error,
denormalize_in => denormalize_in,
denormalize => denormalize);
end function to_float128;
-- to_float (Real)
-- typically not Synthesizable unless the input is a constant.
function to_float (
arg : REAL;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arg_real : REAL; -- Real version of argument
variable validfp : boundary_type; -- Check for valid results
variable exp : INTEGER; -- Integer version of exponent
variable expon : UNSIGNED (exponent_width - 1 downto 0);
-- Unsigned version of exp.
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable fract : UNSIGNED (fraction_width-1 downto 0);
variable frac : REAL; -- Real version of fraction
constant roundfrac : REAL := 2.0 ** (-2 - fract'high); -- used for rounding
variable round : BOOLEAN; -- to round or not to round
begin
result := (others => '0');
arg_real := arg;
if arg_real < 0.0 then
result (exponent_width) := '1';
arg_real := - arg_real; -- Make it positive.
else
result (exponent_width) := '0';
end if;
test_boundary (arg => arg_real,
fraction_width => fraction_width,
exponent_width => exponent_width,
denormalize => denormalize,
btype => validfp,
log2i => exp);
if validfp = zero then
return result; -- Result initialized to "0".
elsif validfp = infinity then
result (exponent_width - 1 downto 0) := (others => '1'); -- Exponent all "1"
-- return infinity.
return result;
else
if validfp = denormal then -- Exponent will default to "0".
expon := (others => '0');
frac := arg_real * (2.0 ** (to_integer(expon_base)-1));
else -- Number less than 1. "normal" number
expon := UNSIGNED (to_signed (exp-1, exponent_width));
expon(exponent_width-1) := not expon(exponent_width-1);
frac := (arg_real / 2.0 ** exp) - 1.0; -- Number less than 1.
end if;
for i in 0 to fract'high loop
if frac >= 2.0 ** (-1 - i) then
fract (fract'high - i) := '1';
frac := frac - 2.0 ** (-1 - i);
else
fract (fract'high - i) := '0';
end if;
end loop;
round := false;
case round_style is
when round_nearest =>
if frac > roundfrac or ((frac = roundfrac) and fract(0) = '1') then
round := true;
end if;
when round_inf =>
if frac /= 0.0 and result(exponent_width) = '0' then
round := true;
end if;
when round_neginf =>
if frac /= 0.0 and result(exponent_width) = '1' then
round := true;
end if;
when others =>
null; -- don't round
end case;
if (round) then
if and_reduce (fract) = '1' then -- fraction is all "1"
expon := expon + 1;
fract := (others => '0');
else
fract := resize(fract + 1, fract'length);
end if;
end if;
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);
result (-1 downto -fraction_width) := UNRESOLVED_float(fract);
return result;
end if;
end function to_float;
-- to_float (Integer)
function to_float (
arg : INTEGER;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arg_int : NATURAL; -- Natural version of argument
variable expon : SIGNED (exponent_width-1 downto 0);
variable exptmp : SIGNED (exponent_width-1 downto 0);
-- Unsigned version of exp.
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable fract : UNSIGNED (fraction_width-1 downto 0) := (others => '0');
variable fracttmp : UNSIGNED (fraction_width-1 downto 0);
variable round : BOOLEAN;
variable shift : NATURAL;
variable shiftr : NATURAL;
variable roundfrac : NATURAL; -- used in rounding
begin
if arg < 0 then
result (exponent_width) := '1';
arg_int := -arg; -- Make it positive.
else
result (exponent_width) := '0';
arg_int := arg;
end if;
if arg_int = 0 then
result := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
-- If the number is larger than we can represent in this number system
-- we need to return infinity.
shift := log2(arg_int);
if shift > to_integer(expon_base) then
-- worry about infinity
if result (exponent_width) = '0' then
result := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
-- return negative infinity.
result := neg_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
end if;
else -- Normal number (can't be denormal)
-- Compute Exponent
expon := to_signed (shift-1, expon'length); -- positive fraction.
-- Compute Fraction
arg_int := arg_int - 2**shift; -- Subtract off the 1.0
shiftr := shift;
for I in fract'high downto maximum (fract'high - shift + 1, 0) loop
shiftr := shiftr - 1;
if (arg_int >= 2**shiftr) then
arg_int := arg_int - 2**shiftr;
fract(I) := '1';
else
fract(I) := '0';
end if;
end loop;
-- Rounding routine
round := false;
if arg_int > 0 then
roundfrac := 2**(shiftr-1);
case round_style is
when round_nearest =>
if arg_int > roundfrac or
((arg_int = roundfrac) and fract(0) = '1') then
round := true;
end if;
when round_inf =>
if arg_int /= 0 and result (exponent_width) = '0' then
round := true;
end if;
when round_neginf =>
if arg_int /= 0 and result (exponent_width) = '1' then
round := true;
end if;
when others =>
null;
end case;
end if;
if round then
fp_round(fract_in => fract,
expon_in => expon,
fract_out => fracttmp,
expon_out => exptmp);
fract := fracttmp;
expon := exptmp;
end if;
-- Put the number together and return
expon(exponent_width-1) := not expon(exponent_width-1);
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);
result (-1 downto -fraction_width) := UNRESOLVED_float(fract);
end if;
end if;
return result;
end function to_float;
-- to_float (unsigned)
function to_float (
arg : UNSIGNED;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
variable sarg : SIGNED (ARG_LEFT+1 downto 0); -- signed version of arg
begin
if arg'length < 1 then
return NAFP;
end if;
sarg (XARG'range) := SIGNED (XARG);
sarg (sarg'high) := '0';
result := to_float (arg => sarg,
exponent_width => exponent_width,
fraction_width => fraction_width,
round_style => round_style);
return result;
end function to_float;
-- to_float (signed)
function to_float (
arg : SIGNED;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : SIGNED(ARG_LEFT downto 0) is ARG;
variable arg_int : UNSIGNED(xarg'range); -- Real version of argument
variable argb2 : UNSIGNED(xarg'high/2 downto 0); -- log2 of input
variable rexp : SIGNED (exponent_width - 1 downto 0);
variable exp : SIGNED (exponent_width - 1 downto 0);
-- signed version of exp.
variable expon : UNSIGNED (exponent_width - 1 downto 0);
-- Unsigned version of exp.
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable round : BOOLEAN;
variable fract : UNSIGNED (fraction_width-1 downto 0);
variable rfract : UNSIGNED (fraction_width-1 downto 0);
variable sign : STD_ULOGIC; -- sign bit
begin
if arg'length < 1 then
return NAFP;
end if;
if Is_X (xarg) then
result := (others => 'X');
elsif (xarg = 0) then
result := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else -- Normal number (can't be denormal)
sign := to_X01(xarg (xarg'high));
arg_int := UNSIGNED(abs (to_01(xarg)));
-- Compute Exponent
argb2 := to_unsigned(find_leftmost(arg_int, '1'), argb2'length); -- Log2
if argb2 > UNSIGNED(expon_base) then
result := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
result (exponent_width) := sign;
else
exp := SIGNED(resize(argb2, exp'length));
arg_int := shift_left (arg_int, arg_int'high-to_integer(exp));
if (arg_int'high > fraction_width) then
fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width));
round := check_round (
fract_in => fract (0),
sign => sign,
remainder => arg_int((arg_int'high-fraction_width-1)
downto 0),
round_style => round_style);
if round then
fp_round(fract_in => fract,
expon_in => exp,
fract_out => rfract,
expon_out => rexp);
else
rfract := fract;
rexp := exp;
end if;
else
rexp := exp;
rfract := (others => '0');
rfract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) :=
arg_int (arg_int'high-1 downto 0);
end if;
result (exponent_width) := sign;
expon := UNSIGNED (rexp-1);
expon(exponent_width-1) := not expon(exponent_width-1);
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);
result (-1 downto -fraction_width) := UNRESOLVED_float(rfract);
end if;
end if;
return result;
end function to_float;
-- std_logic_vector to float
function to_float (
arg : STD_ULOGIC_VECTOR;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction
return UNRESOLVED_float is
variable fpvar : UNRESOLVED_float (exponent_width downto -fraction_width);
begin
if arg'length < 1 then
return NAFP;
end if;
fpvar := UNRESOLVED_float(arg);
return fpvar;
end function to_float;
-- purpose: converts a ufixed to a floating point
function to_float (
arg : UNRESOLVED_ufixed; -- unsigned fixed point input
constant exponent_width : NATURAL := float_exponent_width; -- width of exponent
constant fraction_width : NATURAL := float_fraction_width; -- width of fraction
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions
return UNRESOLVED_float is
variable sarg : sfixed (arg'high+1 downto arg'low); -- Signed version of arg
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- function to_float
if (arg'length < 1) then
return NAFP;
end if;
sarg (arg'range) := sfixed (arg);
sarg (sarg'high) := '0';
result := to_float (arg => sarg,
exponent_width => exponent_width,
fraction_width => fraction_width,
round_style => round_style,
denormalize => denormalize);
return result;
end function to_float;
function to_float (
arg : UNRESOLVED_sfixed; -- signed fixed point
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- rounding option
return UNRESOLVED_float is
constant integer_width : INTEGER := arg'high;
constant in_fraction_width : INTEGER := arg'low;
variable xresult : sfixed (integer_width downto in_fraction_width);
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arg_int : UNSIGNED(integer_width - in_fraction_width
downto 0); -- unsigned version of argument
variable argx : SIGNED (integer_width - in_fraction_width downto 0);
variable exp, exptmp : SIGNED (exponent_width + 1 downto 0);
variable expon : UNSIGNED (exponent_width - 1 downto 0);
-- Unsigned version of exp.
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable fract, fracttmp : UNSIGNED (fraction_width-1 downto 0) :=
(others => '0');
variable round : BOOLEAN := false;
begin
if (arg'length < 1) then
return NAFP;
end if;
xresult := to_01(arg, 'X');
argx := SIGNED(to_slv(xresult));
if (Is_X (arg)) then
result := (others => 'X');
elsif (argx = 0) then
result := (others => '0');
else
result := (others => '0'); -- zero out the result
if argx(argx'left) = '1' then -- toss the sign bit
result (exponent_width) := '1'; -- Negative number
arg_int := UNSIGNED(to_x01(not STD_LOGIC_VECTOR (argx))) + 1; -- Make it positive with two's complement
else
result (exponent_width) := '0';
arg_int := UNSIGNED(to_x01(STD_LOGIC_VECTOR (argx))); -- new line: direct conversion to unsigned
end if;
-- Compute Exponent
exp := to_signed(find_leftmost(arg_int, '1'), exp'length); -- Log2
if exp + in_fraction_width > expon_base then -- return infinity
result (-1 downto -fraction_width) := (others => '0');
result (exponent_width -1 downto 0) := (others => '1');
return result;
elsif (denormalize and
(exp + in_fraction_width <= -resize(expon_base, exp'length))) then
exp := -resize(expon_base, exp'length);
-- shift by a constant
arg_int := shift_left (arg_int,
(arg_int'high + to_integer(expon_base)
+ in_fraction_width - 1));
if (arg_int'high > fraction_width) then
fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width));
round := check_round (
fract_in => arg_int(arg_int'high-fraction_width),
sign => result(result'high),
remainder => arg_int((arg_int'high-fraction_width-1)
downto 0),
round_style => round_style);
if (round) then
fp_round (fract_in => arg_int (arg_int'high-1 downto
(arg_int'high-fraction_width)),
expon_in => exp,
fract_out => fract,
expon_out => exptmp);
exp := exptmp;
end if;
else
fract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) :=
arg_int (arg_int'high-1 downto 0);
end if;
else
arg_int := shift_left (arg_int, arg_int'high-to_integer(exp));
exp := exp + in_fraction_width;
if (arg_int'high > fraction_width) then
fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width));
round := check_round (
fract_in => fract(0),
sign => result(result'high),
remainder => arg_int((arg_int'high-fraction_width-1)
downto 0),
round_style => round_style);
if (round) then
fp_round (fract_in => fract,
expon_in => exp,
fract_out => fracttmp,
expon_out => exptmp);
fract := fracttmp;
exp := exptmp;
end if;
else
fract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) :=
arg_int (arg_int'high-1 downto 0);
end if;
end if;
expon := UNSIGNED (resize(exp-1, exponent_width));
expon(exponent_width-1) := not expon(exponent_width-1);
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);
result (-1 downto -fraction_width) := UNRESOLVED_float(fract);
end if;
return result;
end function to_float;
-- size_res functions
-- Integer to float
function to_float (
arg : INTEGER;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style);
return result;
end if;
end function to_float;
-- real to float
function to_float (
arg : REAL;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style,
denormalize => denormalize);
return result;
end if;
end function to_float;
-- unsigned to float
function to_float (
arg : UNSIGNED;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style);
return result;
end if;
end function to_float;
-- signed to float
function to_float (
arg : SIGNED;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style);
return result;
end if;
end function to_float;
-- std_ulogic_vector to float
function to_float (
arg : STD_ULOGIC_VECTOR;
size_res : UNRESOLVED_float)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low);
return result;
end if;
end function to_float;
-- unsigned fixed point to float
function to_float (
arg : UNRESOLVED_ufixed; -- unsigned fixed point input
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style,
denormalize => denormalize);
return result;
end if;
end function to_float;
-- signed fixed point to float
function to_float (
arg : UNRESOLVED_sfixed;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- rounding option
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style,
denormalize => denormalize);
return result;
end if;
end function to_float;
-- to_integer (float)
function to_integer (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return INTEGER is
variable validfp : valid_fpstate; -- Valid FP state
variable frac : UNSIGNED (-arg'low downto 0); -- Fraction
variable fract : UNSIGNED (1-arg'low downto 0); -- Fraction
variable expon : SIGNED (arg'high-1 downto 0);
variable isign : STD_ULOGIC; -- internal version of sign
variable round : STD_ULOGIC; -- is rounding needed?
variable result : INTEGER;
variable base : INTEGER; -- Integer exponent
begin
validfp := classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan | pos_zero | neg_zero | pos_denormal | neg_denormal =>
result := 0; -- return 0
when pos_inf =>
result := INTEGER'high;
when neg_inf =>
result := INTEGER'low;
when others =>
break_number (
arg => arg,
fptyp => validfp,
denormalize => false,
fract => frac,
expon => expon);
fract (fract'high) := '0'; -- Add extra bit for 0.6 case
fract (fract'high-1 downto 0) := frac;
isign := to_x01 (arg (arg'high));
base := to_integer (expon) + 1;
if base < -1 then
result := 0;
elsif base >= frac'high then
result := to_integer (fract) * 2**(base - frac'high);
else -- We need to round
if base = -1 then -- trap for 0.6 case.
result := 0;
else
result := to_integer (fract (frac'high downto frac'high-base));
end if;
-- rounding routine
case round_style is
when round_nearest =>
if frac'high - base > 1 then
round := fract (frac'high - base - 1) and
(fract (frac'high - base)
or (or_reduce (fract (frac'high - base - 2 downto 0))));
else
round := fract (frac'high - base - 1) and
fract (frac'high - base);
end if;
when round_inf =>
round := fract(frac'high - base - 1) and not isign;
when round_neginf =>
round := fract(frac'high - base - 1) and isign;
when others =>
round := '0';
end case;
if round = '1' then
result := result + 1;
end if;
end if;
if isign = '1' then
result := - result;
end if;
end case classcase;
return result;
end function to_integer;
-- to_unsigned (float)
function to_unsigned (
arg : UNRESOLVED_float; -- floating point input
constant size : NATURAL; -- length of output
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNSIGNED is
variable validfp : valid_fpstate; -- Valid FP state
variable frac : UNSIGNED (size-1 downto 0); -- Fraction
variable sign : STD_ULOGIC; -- not used
begin
validfp := classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan =>
frac := (others => 'X');
when pos_zero | neg_inf | neg_zero | neg_normal | pos_denormal | neg_denormal =>
frac := (others => '0'); -- return 0
when pos_inf =>
frac := (others => '1');
when others =>
float_to_unsigned (
arg => arg,
frac => frac,
sign => sign,
denormalize => false,
bias => 0,
round_style => round_style);
end case classcase;
return (frac);
end function to_unsigned;
-- to_signed (float)
function to_signed (
arg : UNRESOLVED_float; -- floating point input
constant size : NATURAL; -- length of output
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return SIGNED is
variable sign : STD_ULOGIC; -- true if negative
variable validfp : valid_fpstate; -- Valid FP state
variable frac : UNSIGNED (size-1 downto 0); -- Fraction
variable result : SIGNED (size-1 downto 0);
begin
validfp := classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan =>
result := (others => 'X');
when pos_zero | neg_zero | pos_denormal | neg_denormal =>
result := (others => '0'); -- return 0
when pos_inf =>
result := (others => '1');
result (result'high) := '0';
when neg_inf =>
result := (others => '0');
result (result'high) := '1';
when others =>
float_to_unsigned (
arg => arg,
sign => sign,
frac => frac,
denormalize => false,
bias => 0,
round_style => round_style);
result (size-1) := '0';
result (size-2 downto 0) := SIGNED(frac (size-2 downto 0));
if sign = '1' then
-- Because the most negative signed number is 1 less than the most
-- positive signed number, we need this code.
if frac(frac'high) = '1' then -- return most negative number
result := (others => '0');
result (result'high) := '1';
else
result := -result;
end if;
else
if frac(frac'high) = '1' then -- return most positive number
result := (others => '1');
result (result'high) := '0';
end if;
end if;
end case classcase;
return result;
end function to_signed;
-- purpose: Converts a float to ufixed
function to_ufixed (
arg : UNRESOLVED_float; -- fp input
constant left_index : INTEGER; -- integer part
constant right_index : INTEGER; -- fraction part
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_ufixed is
constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : INTEGER := arg'high; -- length of FP output exponent
constant size : INTEGER := left_index - right_index + 4; -- unsigned size
variable expon_base : INTEGER; -- exponent offset
variable validfp : valid_fpstate; -- Valid FP state
variable exp : INTEGER; -- Exponent
variable expon : UNSIGNED (exponent_width-1 downto 0); -- Vectorized exponent
-- Base to divide fraction by
variable frac : UNSIGNED (size-1 downto 0) := (others => '0'); -- Fraction
variable frac_shift : UNSIGNED (size-1 downto 0); -- Fraction shifted
variable shift : INTEGER;
variable result_big : UNRESOLVED_ufixed (left_index downto right_index-3);
variable result : UNRESOLVED_ufixed (left_index downto right_index); -- result
begin -- function to_ufixed
validfp := classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan =>
frac := (others => 'X');
when pos_zero | neg_inf | neg_zero | neg_normal | neg_denormal =>
frac := (others => '0'); -- return 0
when pos_inf =>
frac := (others => '1'); -- always saturate
when others =>
expon_base := 2**(exponent_width-1) -1; -- exponent offset
-- Figure out the fraction
if (validfp = pos_denormal) and denormalize then
exp := -expon_base +1;
frac (frac'high) := '0'; -- Remove the "1.0".
else
-- exponent /= '0', normal floating point
expon := UNSIGNED(arg (exponent_width-1 downto 0));
expon(exponent_width-1) := not expon(exponent_width-1);
exp := to_integer (SIGNED(expon)) +1;
frac (frac'high) := '1'; -- Add the "1.0".
end if;
shift := (frac'high - 3 + right_index) - exp;
if fraction_width > frac'high then -- Can only use size-2 bits
frac (frac'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto
-frac'high)));
else -- can use all bits
frac (frac'high-1 downto frac'high-fraction_width) :=
UNSIGNED (to_slv (arg(-1 downto -fraction_width)));
end if;
frac_shift := frac srl shift;
if shift < 0 then -- Overflow
frac := (others => '1');
else
frac := frac_shift;
end if;
end case classcase;
result_big := to_ufixed (
arg => STD_ULOGIC_VECTOR(frac),
left_index => left_index,
right_index => (right_index-3));
result := resize (arg => result_big,
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_ufixed;
-- purpose: Converts a float to sfixed
function to_sfixed (
arg : UNRESOLVED_float; -- fp input
constant left_index : INTEGER; -- integer part
constant right_index : INTEGER; -- fraction part
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_sfixed is
constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : INTEGER := arg'high; -- length of FP output exponent
constant size : INTEGER := left_index - right_index + 4; -- unsigned size
variable expon_base : INTEGER; -- exponent offset
variable validfp : valid_fpstate; -- Valid FP state
variable exp : INTEGER; -- Exponent
variable sign : BOOLEAN; -- true if negative
variable expon : UNSIGNED (exponent_width-1 downto 0); -- Vectorized exponent
-- Base to divide fraction by
variable frac : UNSIGNED (size-2 downto 0) := (others => '0'); -- Fraction
variable frac_shift : UNSIGNED (size-2 downto 0); -- Fraction shifted
variable shift : INTEGER;
variable rsigned : SIGNED (size-1 downto 0); -- signed version of result
variable result_big : UNRESOLVED_sfixed (left_index downto right_index-3);
variable result : UNRESOLVED_sfixed (left_index downto right_index)
:= (others => '0'); -- result
begin -- function to_sfixed
validfp := classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan =>
result := (others => 'X');
when pos_zero | neg_zero =>
result := (others => '0'); -- return 0
when neg_inf =>
result (left_index) := '1'; -- return smallest negative number
when pos_inf =>
result := (others => '1'); -- return largest number
result (left_index) := '0';
when others =>
expon_base := 2**(exponent_width-1) -1; -- exponent offset
if arg(exponent_width) = '0' then
sign := false;
else
sign := true;
end if;
-- Figure out the fraction
if (validfp = pos_denormal or validfp = neg_denormal)
and denormalize then
exp := -expon_base +1;
frac (frac'high) := '0'; -- Add the "1.0".
else
-- exponent /= '0', normal floating point
expon := UNSIGNED(arg (exponent_width-1 downto 0));
expon(exponent_width-1) := not expon(exponent_width-1);
exp := to_integer (SIGNED(expon)) +1;
frac (frac'high) := '1'; -- Add the "1.0".
end if;
shift := (frac'high - 3 + right_index) - exp;
if fraction_width > frac'high then -- Can only use size-2 bits
frac (frac'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto
-frac'high)));
else -- can use all bits
frac (frac'high-1 downto frac'high-fraction_width) :=
UNSIGNED (to_slv (arg(-1 downto -fraction_width)));
end if;
frac_shift := frac srl shift;
if shift < 0 then -- Overflow
frac := (others => '1');
else
frac := frac_shift;
end if;
if not sign then
rsigned := SIGNED("0" & frac);
else
rsigned := -(SIGNED("0" & frac));
end if;
result_big := to_sfixed (
arg => STD_LOGIC_VECTOR(rsigned),
left_index => left_index,
right_index => (right_index-3));
result := resize (arg => result_big,
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
end case classcase;
return result;
end function to_sfixed;
-- size_res versions
-- float to unsigned
function to_unsigned (
arg : UNRESOLVED_float; -- floating point input
size_res : UNSIGNED;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNSIGNED is
variable result : UNSIGNED (size_res'range);
begin
if (SIZE_RES'length = 0) then
return result;
else
result := to_unsigned (
arg => arg,
size => size_res'length,
round_style => round_style,
check_error => check_error);
return result;
end if;
end function to_unsigned;
-- float to signed
function to_signed (
arg : UNRESOLVED_float; -- floating point input
size_res : SIGNED;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return SIGNED is
variable result : SIGNED (size_res'range);
begin
if (SIZE_RES'length = 0) then
return result;
else
result := to_signed (
arg => arg,
size => size_res'length,
round_style => round_style,
check_error => check_error);
return result;
end if;
end function to_signed;
-- purpose: Converts a float to unsigned fixed point
function to_ufixed (
arg : UNRESOLVED_float; -- fp input
size_res : UNRESOLVED_ufixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_ufixed (
arg => arg,
left_index => size_res'high,
right_index => size_res'low,
overflow_style => overflow_style,
round_style => round_style,
check_error => check_error,
denormalize => denormalize);
return result;
end if;
end function to_ufixed;
-- float to signed fixed point
function to_sfixed (
arg : UNRESOLVED_float; -- fp input
size_res : UNRESOLVED_sfixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_sfixed (
arg => arg,
left_index => size_res'high,
right_index => size_res'low,
overflow_style => overflow_style,
round_style => round_style,
check_error => check_error,
denormalize => denormalize);
return result;
end if;
end function to_sfixed;
-- to_real (float)
-- typically not Synthesizable unless the input is a constant.
function to_real (
arg : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return REAL is
constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : INTEGER := arg'high; -- length of FP output exponent
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable frac : REAL := 0.0; -- Fraction
variable validfp : valid_fpstate; -- Valid FP state
variable expon : UNSIGNED (exponent_width - 1 downto 0)
:= (others => '1'); -- Vectorized exponent
begin
validfp := classfp (arg, check_error);
classcase : case validfp is
when isx | pos_zero | neg_zero | nan | quiet_nan =>
return 0.0;
when neg_inf =>
return REAL'low; -- Negative infinity.
when pos_inf =>
return REAL'high; -- Positive infinity
when others =>
expon_base := 2**(exponent_width-1) -1;
if to_X01(arg(exponent_width)) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
-- Figure out the fraction
for i in 0 to fraction_width-1 loop
if to_X01(arg (-1 - i)) = '1' then
frac := frac + (2.0 **(-1 - i));
end if;
end loop; -- i
if validfp = pos_normal or validfp = neg_normal or not denormalize then
-- exponent /= '0', normal floating point
expon := UNSIGNED(arg (exponent_width-1 downto 0));
expon(exponent_width-1) := not expon(exponent_width-1);
exp := to_integer (SIGNED(expon)) +1;
sign := sign * (2.0 ** exp) * (1.0 + frac);
else -- exponent = '0', IEEE extended floating point
exp := 1 - expon_base;
sign := sign * (2.0 ** exp) * frac;
end if;
return sign;
end case classcase;
end function to_real;
-- For Verilog compatability
function realtobits (arg : REAL) return STD_ULOGIC_VECTOR is
variable result : float64; -- 64 bit floating point
begin
result := to_float (arg => arg,
exponent_width => float64'high,
fraction_width => -float64'low);
return to_sulv (result);
end function realtobits;
function bitstoreal (arg : STD_ULOGIC_VECTOR) return REAL is
variable arg64 : float64; -- arg converted to float
begin
arg64 := to_float (arg => arg,
exponent_width => float64'high,
fraction_width => -float64'low);
return to_real (arg64);
end function bitstoreal;
-- purpose: Removes meta-logical values from FP string
function to_01 (
arg : UNRESOLVED_float; -- floating point input
XMAP : STD_LOGIC := '0')
return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range);
begin -- function to_01
if (arg'length < 1) then
assert NO_WARNING
report "float_pkg"
& "TO_01: null detected, returning NULL"
severity warning;
return NAFP;
end if;
result := UNRESOLVED_float (STD_LOGIC_VECTOR(to_01(UNSIGNED(to_slv(arg)), XMAP)));
return result;
end function to_01;
function Is_X
(arg : UNRESOLVED_float)
return BOOLEAN is
begin
return Is_X (to_slv(arg));
end function Is_X;
function to_X01 (arg : UNRESOLVED_float) return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range);
begin
if (arg'length < 1) then
assert NO_WARNING
report "float_pkg"
& "TO_X01: null detected, returning NULL"
severity warning;
return NAFP;
else
result := UNRESOLVED_float (to_X01(to_slv(arg)));
return result;
end if;
end function to_X01;
function to_X01Z (arg : UNRESOLVED_float) return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range);
begin
if (arg'length < 1) then
assert NO_WARNING
report "float_pkg"
& "TO_X01Z: null detected, returning NULL"
severity warning;
return NAFP;
else
result := UNRESOLVED_float (to_X01Z(to_slv(arg)));
return result;
end if;
end function to_X01Z;
function to_UX01 (arg : UNRESOLVED_float) return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range);
begin
if (arg'length < 1) then
assert NO_WARNING
report "float_pkg"
& "TO_UX01: null detected, returning NULL"
severity warning;
return NAFP;
else
result := UNRESOLVED_float (to_UX01(to_slv(arg)));
return result;
end if;
end function to_UX01;
-- These allows the base math functions to use the default values
-- of their parameters. Thus they do full IEEE floating point.
function "+" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return add (l, r);
end function "+";
function "-" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return subtract (l, r);
end function "-";
function "*" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return multiply (l, r);
end function "*";
function "/" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return divide (l, r);
end function "/";
function "rem" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return remainder (l, r);
end function "rem";
function "mod" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return modulo (l, r);
end function "mod";
-- overloaded versions
function "+" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return add (l, r_float);
end function "+";
function "+" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return add (l_float, r);
end function "+";
function "+" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return add (l, r_float);
end function "+";
function "+" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return add (l_float, r);
end function "+";
function "-" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return subtract (l, r_float);
end function "-";
function "-" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return subtract (l_float, r);
end function "-";
function "-" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return subtract (l, r_float);
end function "-";
function "-" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return subtract (l_float, r);
end function "-";
function "*" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return multiply (l, r_float);
end function "*";
function "*" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return multiply (l_float, r);
end function "*";
function "*" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return multiply (l, r_float);
end function "*";
function "*" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return multiply (l_float, r);
end function "*";
function "/" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return divide (l, r_float);
end function "/";
function "/" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return divide (l_float, r);
end function "/";
function "/" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return divide (l, r_float);
end function "/";
function "/" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return divide (l_float, r);
end function "/";
function "rem" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return remainder (l, r_float);
end function "rem";
function "rem" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return remainder (l_float, r);
end function "rem";
function "rem" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return remainder (l, r_float);
end function "rem";
function "rem" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return remainder (l_float, r);
end function "rem";
function "mod" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return modulo (l, r_float);
end function "mod";
function "mod" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return modulo (l_float, r);
end function "mod";
function "mod" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return modulo (l, r_float);
end function "mod";
function "mod" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return modulo (l_float, r);
end function "mod";
function "=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return eq (l, r_float);
end function "=";
function "/=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return ne (l, r_float);
end function "/=";
function ">=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return ge (l, r_float);
end function ">=";
function "<=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return le (l, r_float);
end function "<=";
function ">" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return gt (l, r_float);
end function ">";
function "<" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return lt (l, r_float);
end function "<";
function "=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return eq (l_float, r);
end function "=";
function "/=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return ne (l_float, r);
end function "/=";
function ">=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return ge (l_float, r);
end function ">=";
function "<=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return le (l_float, r);
end function "<=";
function ">" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return gt (l_float, r);
end function ">";
function "<" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return lt (l_float, r);
end function "<";
function "=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return eq (l, r_float);
end function "=";
function "/=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return ne (l, r_float);
end function "/=";
function ">=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return ge (l, r_float);
end function ">=";
function "<=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return le (l, r_float);
end function "<=";
function ">" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return gt (l, r_float);
end function ">";
function "<" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return lt (l, r_float);
end function "<";
function "=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return eq (l_float, r);
end function "=";
function "/=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return ne (l_float, r);
end function "/=";
function ">=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return ge (l_float, r);
end function ">=";
function "<=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return le (l_float, r);
end function "<=";
function ">" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return gt (l_float, r);
end function ">";
function "<" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return lt (l_float, r);
end function "<";
-- ?= overloads
function \?=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?=\ (l, r_float);
end function \?=\;
function \?/=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?/=\ (l, r_float);
end function \?/=\;
function \?>\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?>\ (l, r_float);
end function \?>\;
function \?>=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?>=\ (l, r_float);
end function \?>=\;
function \?<\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?<\ (l, r_float);
end function \?<\;
function \?<=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?<=\ (l, r_float);
end function \?<=\;
-- real and float
function \?=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?=\ (l_float, r);
end function \?=\;
function \?/=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?/=\ (l_float, r);
end function \?/=\;
function \?>\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?>\ (l_float, r);
end function \?>\;
function \?>=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?>=\ (l_float, r);
end function \?>=\;
function \?<\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?<\ (l_float, r);
end function \?<\;
function \?<=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?<=\ (l_float, r);
end function \?<=\;
-- ?= overloads
function \?=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?=\ (l, r_float);
end function \?=\;
function \?/=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?/=\ (l, r_float);
end function \?/=\;
function \?>\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?>\ (l, r_float);
end function \?>\;
function \?>=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?>=\ (l, r_float);
end function \?>=\;
function \?<\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?<\ (l, r_float);
end function \?<\;
function \?<=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?<=\ (l, r_float);
end function \?<=\;
-- integer and float
function \?=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?=\ (l_float, r);
end function \?=\;
function \?/=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?/=\ (l_float, r);
end function \?/=\;
function \?>\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?>\ (l_float, r);
end function \?>\;
function \?>=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?>=\ (l_float, r);
end function \?>=\;
function \?<\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?<\ (l_float, r);
end function \?<\;
function \?<=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?<=\ (l_float, r);
end function \?<=\;
-- minimum and maximum overloads
function minimum (l : UNRESOLVED_float; r : REAL)
return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return minimum (l, r_float);
end function minimum;
function maximum (l : UNRESOLVED_float; r : REAL)
return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return maximum (l, r_float);
end function maximum;
function minimum (l : REAL; r : UNRESOLVED_float)
return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return minimum (l_float, r);
end function minimum;
function maximum (l : REAL; r : UNRESOLVED_float)
return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return maximum (l_float, r);
end function maximum;
function minimum (l : UNRESOLVED_float; r : INTEGER)
return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return minimum (l, r_float);
end function minimum;
function maximum (l : UNRESOLVED_float; r : INTEGER)
return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return maximum (l, r_float);
end function maximum;
function minimum (l : INTEGER; r : UNRESOLVED_float)
return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return minimum (l_float, r);
end function minimum;
function maximum (l : INTEGER; r : UNRESOLVED_float)
return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return maximum (l_float, r);
end function maximum;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (L : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
RESULT := not to_sulv(L);
return to_float (RESULT, L'high, -L'low);
end function "not";
function "and" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) and to_sulv(R);
else
assert NO_WARNING
report "float_pkg"
& """and"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "and";
function "or" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) or to_sulv(R);
else
assert NO_WARNING
report "float_pkg"
& """or"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "or";
function "nand" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nand to_sulv(R);
else
assert NO_WARNING
report "float_pkg"
& """nand"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "nand";
function "nor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nor to_sulv(R);
else
assert NO_WARNING
report "float_pkg"
& """nor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "nor";
function "xor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xor to_sulv(R);
else
assert NO_WARNING
report "float_pkg"
& """xor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "xor";
function "xnor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xnor to_sulv(R);
else
assert NO_WARNING
report "float_pkg"
& """xnor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "xnor";
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (R'range);
begin
for i in result'range loop
result(i) := L and R(i);
end loop;
return result;
end function "and";
function "and" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (L'range);
begin
for i in result'range loop
result(i) := L(i) and R;
end loop;
return result;
end function "and";
function "or" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (R'range);
begin
for i in result'range loop
result(i) := L or R(i);
end loop;
return result;
end function "or";
function "or" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (L'range);
begin
for i in result'range loop
result(i) := L(i) or R;
end loop;
return result;
end function "or";
function "nand" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (R'range);
begin
for i in result'range loop
result(i) := L nand R(i);
end loop;
return result;
end function "nand";
function "nand" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (L'range);
begin
for i in result'range loop
result(i) := L(i) nand R;
end loop;
return result;
end function "nand";
function "nor" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (R'range);
begin
for i in result'range loop
result(i) := L nor R(i);
end loop;
return result;
end function "nor";
function "nor" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (L'range);
begin
for i in result'range loop
result(i) := L(i) nor R;
end loop;
return result;
end function "nor";
function "xor" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (R'range);
begin
for i in result'range loop
result(i) := L xor R(i);
end loop;
return result;
end function "xor";
function "xor" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (L'range);
begin
for i in result'range loop
result(i) := L(i) xor R;
end loop;
return result;
end function "xor";
function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (R'range);
begin
for i in result'range loop
result(i) := L xnor R(i);
end loop;
return result;
end function "xnor";
function "xnor" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (L'range);
begin
for i in result'range loop
result(i) := L(i) xnor R;
end loop;
return result;
end function "xnor";
-- Reduction operator_reduces, same as numeric_std functions
function and_reduce (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return and_reduce (to_sulv(l));
end function and_reduce;
function nand_reduce (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return nand_reduce (to_sulv(l));
end function nand_reduce;
function or_reduce (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return or_reduce (to_sulv(l));
end function or_reduce;
function nor_reduce (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return nor_reduce (to_sulv(l));
end function nor_reduce;
function xor_reduce (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return xor_reduce (to_sulv(l));
end function xor_reduce;
function xnor_reduce (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return xnor_reduce (to_sulv(l));
end function xnor_reduce;
-----------------------------------------------------------------------------
-- Recommended Functions from the IEEE 754 Appendix
-----------------------------------------------------------------------------
-- returns x with the sign of y.
function Copysign (
x, y : UNRESOLVED_float) -- floating point input
return UNRESOLVED_float is
begin
return y(y'high) & x (x'high-1 downto x'low);
end function Copysign;
-- Returns y * 2**n for integral values of N without computing 2**n
function Scalb (
y : UNRESOLVED_float; -- floating point input
N : INTEGER; -- exponent to add
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(y'low, y'low); -- length of FP output fraction
constant exponent_width : NATURAL := y'high; -- length of FP output exponent
variable arg, result : UNRESOLVED_float (exponent_width downto -fraction_width); -- internal argument
variable expon : SIGNED (exponent_width-1 downto 0); -- Vectorized exp
variable exp : SIGNED (exponent_width downto 0);
variable ufract : UNSIGNED (fraction_width downto 0);
constant expon_base : SIGNED (exponent_width-1 downto 0)
:= gen_expon_base(exponent_width); -- exponent offset
variable fptype : valid_fpstate;
begin
-- This can be done by simply adding N to the exponent.
arg := to_01 (y, 'X');
fptype := classfp(arg, check_error);
classcase : case fptype is
when isx =>
result := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
result := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when others =>
break_number (
arg => arg,
fptyp => fptype,
denormalize => denormalize,
fract => ufract,
expon => expon);
exp := resize (expon, exp'length) + N;
result := normalize (
fract => ufract,
expon => exp,
sign => to_x01 (arg (arg'high)),
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => 0);
end case classcase;
return result;
end function Scalb;
-- Returns y * 2**n for integral values of N without computing 2**n
function Scalb (
y : UNRESOLVED_float; -- floating point input
N : SIGNED; -- exponent to add
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
variable n_int : INTEGER;
begin
n_int := to_integer(N);
return Scalb (y => y,
N => n_int,
round_style => round_style,
check_error => check_error,
denormalize => denormalize);
end function Scalb;
-- returns the unbiased exponent of x
function Logb (
x : UNRESOLVED_float) -- floating point input
return INTEGER is
constant fraction_width : NATURAL := -mine (x'low, x'low); -- length of FP output fraction
constant exponent_width : NATURAL := x'high; -- length of FP output exponent
variable result : INTEGER; -- result
variable arg : UNRESOLVED_float (exponent_width downto -fraction_width); -- internal argument
variable expon : SIGNED (exponent_width - 1 downto 0);
variable fract : UNSIGNED (fraction_width downto 0);
constant expon_base : INTEGER := 2**(exponent_width-1) -1; -- exponent
-- offset +1
variable fptype : valid_fpstate;
begin
-- Just return the exponent.
arg := to_01 (x, 'X');
fptype := classfp(arg);
classcase : case fptype is
when isx | nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
result := 0;
when pos_denormal | neg_denormal =>
fract (fraction_width) := '0';
fract (fraction_width-1 downto 0) :=
UNSIGNED (to_slv(arg(-1 downto -fraction_width)));
result := find_leftmost (fract, '1') -- Find the first "1"
- fraction_width; -- subtract the length we want
result := -expon_base + 1 + result;
when others =>
expon := SIGNED(arg (exponent_width - 1 downto 0));
expon(exponent_width-1) := not expon(exponent_width-1);
expon := expon + 1;
result := to_integer (expon);
end case classcase;
return result;
end function Logb;
-- returns the unbiased exponent of x
function Logb (
x : UNRESOLVED_float) -- floating point input
return SIGNED is
constant exponent_width : NATURAL := x'high; -- length of FP output exponent
variable result : SIGNED (exponent_width - 1 downto 0); -- result
begin
-- Just return the exponent.
result := to_signed (Logb (x), exponent_width);
return result;
end function Logb;
-- returns the next representable neighbor of x in the direction toward y
function Nextafter (
x, y : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(x'low, x'low); -- length of FP output fraction
constant exponent_width : NATURAL := x'high; -- length of FP output exponent
function "=" (
l, r : UNRESOLVED_float) -- inputs
return BOOLEAN is
begin -- function "="
return eq (l => l,
r => r,
check_error => false);
end function "=";
function ">" (
l, r : UNRESOLVED_float) -- inputs
return BOOLEAN is
begin -- function ">"
return gt (l => l,
r => r,
check_error => false);
end function ">";
variable fract : UNSIGNED (fraction_width-1 downto 0);
variable expon : UNSIGNED (exponent_width-1 downto 0);
variable sign : STD_ULOGIC;
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable validfpx, validfpy : valid_fpstate; -- Valid FP state
begin -- fp_Nextafter
-- If Y > X, add one to the fraction, otherwise subtract.
validfpx := classfp (x, check_error);
validfpy := classfp (y, check_error);
if validfpx = isx or validfpy = isx then
result := (others => 'X');
return result;
elsif (validfpx = nan or validfpy = nan) then
return nanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (validfpx = quiet_nan or validfpy = quiet_nan) then
return qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif x = y then -- Return X
return x;
else
fract := UNSIGNED (to_slv (x (-1 downto -fraction_width))); -- Fraction
expon := UNSIGNED (x (exponent_width - 1 downto 0)); -- exponent
sign := x(exponent_width); -- sign bit
if (y > x) then
-- Increase the number given
if validfpx = neg_inf then
-- return most negative number
expon := (others => '1');
expon (0) := '0';
fract := (others => '1');
elsif validfpx = pos_zero or validfpx = neg_zero then
-- return smallest denormal number
sign := '0';
expon := (others => '0');
fract := (others => '0');
fract(0) := '1';
elsif validfpx = pos_normal then
if and_reduce (fract) = '1' then -- fraction is all "1".
if and_reduce (expon (exponent_width-1 downto 1)) = '1'
and expon (0) = '0' then
-- Exponent is one away from infinity.
assert NO_WARNING
report "float_pkg"
& "FP_NEXTAFTER: NextAfter overflow"
severity warning;
return pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
expon := expon + 1;
fract := (others => '0');
end if;
else
fract := fract + 1;
end if;
elsif validfpx = pos_denormal then
if and_reduce (fract) = '1' then -- fraction is all "1".
-- return smallest possible normal number
expon := (others => '0');
expon(0) := '1';
fract := (others => '0');
else
fract := fract + 1;
end if;
elsif validfpx = neg_normal then
if or_reduce (fract) = '0' then -- fraction is all "0".
if or_reduce (expon (exponent_width-1 downto 1)) = '0' and
expon (0) = '1' then -- Smallest exponent
-- return the largest negative denormal number
expon := (others => '0');
fract := (others => '1');
else
expon := expon - 1;
fract := (others => '1');
end if;
else
fract := fract - 1;
end if;
elsif validfpx = neg_denormal then
if or_reduce (fract(fract'high downto 1)) = '0'
and fract (0) = '1' then -- Smallest possible fraction
return zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
fract := fract - 1;
end if;
end if;
else
-- Decrease the number
if validfpx = pos_inf then
-- return most positive number
expon := (others => '1');
expon (0) := '0';
fract := (others => '1');
elsif validfpx = pos_zero
or classfp (x) = neg_zero then
-- return smallest negative denormal number
sign := '1';
expon := (others => '0');
fract := (others => '0');
fract(0) := '1';
elsif validfpx = neg_normal then
if and_reduce (fract) = '1' then -- fraction is all "1".
if and_reduce (expon (exponent_width-1 downto 1)) = '1'
and expon (0) = '0' then
-- Exponent is one away from infinity.
assert NO_WARNING
report "float_pkg"
& "FP_NEXTAFTER: NextAfter overflow"
severity warning;
return neg_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
expon := expon + 1; -- Fraction overflow
fract := (others => '0');
end if;
else
fract := fract + 1;
end if;
elsif validfpx = neg_denormal then
if and_reduce (fract) = '1' then -- fraction is all "1".
-- return smallest possible normal number
expon := (others => '0');
expon(0) := '1';
fract := (others => '0');
else
fract := fract + 1;
end if;
elsif validfpx = pos_normal then
if or_reduce (fract) = '0' then -- fraction is all "0".
if or_reduce (expon (exponent_width-1 downto 1)) = '0' and
expon (0) = '1' then -- Smallest exponent
-- return the largest positive denormal number
expon := (others => '0');
fract := (others => '1');
else
expon := expon - 1;
fract := (others => '1');
end if;
else
fract := fract - 1;
end if;
elsif validfpx = pos_denormal then
if or_reduce (fract(fract'high downto 1)) = '0'
and fract (0) = '1' then -- Smallest possible fraction
return zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
fract := fract - 1;
end if;
end if;
end if;
result (-1 downto -fraction_width) := UNRESOLVED_float(fract);
result (exponent_width -1 downto 0) := UNRESOLVED_float(expon);
result (exponent_width) := sign;
return result;
end if;
end function Nextafter;
-- Returns True if X is unordered with Y.
function Unordered (
x, y : UNRESOLVED_float) -- floating point input
return BOOLEAN is
variable lfptype, rfptype : valid_fpstate;
begin
lfptype := classfp (x);
rfptype := classfp (y);
if (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan or
lfptype = isx or rfptype = isx) then
return true;
else
return false;
end if;
end function Unordered;
function Finite (
x : UNRESOLVED_float)
return BOOLEAN is
variable fp_state : valid_fpstate; -- fp state
begin
fp_state := Classfp (x);
if (fp_state = pos_inf) or (fp_state = neg_inf) then
return true;
else
return false;
end if;
end function Finite;
function Isnan (
x : UNRESOLVED_float)
return BOOLEAN is
variable fp_state : valid_fpstate; -- fp state
begin
fp_state := Classfp (x);
if (fp_state = nan) or (fp_state = quiet_nan) then
return true;
else
return false;
end if;
end function Isnan;
-- Function to return constants.
function zerofp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float is
constant result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
return result;
end function zerofp;
function nanfp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width-1 downto 0) := (others => '1');
-- Exponent all "1"
result (-1) := '1'; -- MSB of Fraction "1"
-- Note: From W. Khan "IEEE Standard 754 for Binary Floating Point"
-- The difference between a signaling NAN and a quiet NAN is that
-- the MSB of the Fraction is a "1" in a Signaling NAN, and is a
-- "0" in a quiet NAN.
return result;
end function nanfp;
function qnanfp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width-1 downto 0) := (others => '1');
-- Exponent all "1"
result (-fraction_width) := '1'; -- LSB of Fraction "1"
-- (Could have been any bit)
return result;
end function qnanfp;
function pos_inffp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width-1 downto 0) := (others => '1'); -- Exponent all "1"
return result;
end function pos_inffp;
function neg_inffp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width downto 0) := (others => '1'); -- top bits all "1"
return result;
end function neg_inffp;
function neg_zerofp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width) := '1';
return result;
end function neg_zerofp;
-- size_res versions
function zerofp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return zerofp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function zerofp;
function nanfp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return nanfp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function nanfp;
function qnanfp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return qnanfp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function qnanfp;
function pos_inffp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return pos_inffp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function pos_inffp;
function neg_inffp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return neg_inffp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function neg_inffp;
function neg_zerofp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return neg_zerofp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function neg_zerofp;
-- rtl_synthesis off
-- pragma synthesis_off
--%%% these functions are copied from std_logic_1164 (VHDL-200X edition)
-- Textio functions
-- purpose: writes float into a line (NOTE changed basetype)
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
constant NUS : STRING(2 to 1) := (others => ' ');
-- purpose: Skips white space
procedure skip_whitespace (
L : inout LINE) is
variable readOk : BOOLEAN;
variable c : CHARACTER;
begin
while L /= null and L.all'length /= 0 loop
if (L.all(1) = ' ' or L.all(1) = NBSP or L.all(1) = HT) then
read (l, c, readOk);
else
exit;
end if;
end loop;
end procedure skip_whitespace;
-- %%% Replicated textio functions
function to_ostring (value : STD_LOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+2)/3;
variable pad : STD_LOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
variable ivalue : STD_LOGIC_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : STD_LOGIC_VECTOR(0 to 2);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
tri := To_X01Z(ivalue(3*i to 3*i+2));
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
when "ZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_ostring;
-------------------------------------------------------------------
function to_hstring (value : STD_LOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_LOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_LOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_LOGIC_VECTOR(0 to 3);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_hstring;
procedure Char2TriBits (C : CHARACTER;
RESULT : out STD_LOGIC_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when 'Z' => result := "ZZZ"; good := true;
when 'X' => result := "XXX"; good := true;
when others =>
assert not ISSUE_ERROR
report "float_pkg"
& "OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
result := "UUU";
good := false;
end case;
end procedure Char2TriBits;
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_LOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- read into a null array
end if;
end procedure OREAD;
-- Hex Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2QuadBits (C : CHARACTER;
RESULT : out STD_LOGIC_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when 'Z' => result := "ZZZZ"; good := true;
when 'X' => result := "XXXX"; good := true;
when others =>
assert not ISSUE_ERROR
report "float_pkg"
& "HREAD Error: Read a '" & c &
"', expected a Hex character (0-F)."
severity error;
result := "UUUU";
good := false;
end case;
end procedure Char2QuadBits;
procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_LOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- Null input string, skips whitespace
end if;
end procedure HREAD;
-- %%% END replicated textio functions
-- purpose: Checks the punctuation in a line
procedure check_punctuation (
arg : in STRING;
colon : out BOOLEAN; -- There was a colon in the line
dot : out BOOLEAN; -- There was a dot in the line
good : out BOOLEAN; -- True if enough characters found
chars : in INTEGER) is
-- Examples. Legal inputs are "0000000", "0000.000", "0:000:000"
alias xarg : STRING (1 to arg'length) is arg; -- make it downto range
variable icolon, idot : BOOLEAN; -- internal
variable j : INTEGER := 0; -- charters read
begin
good := false;
icolon := false;
idot := false;
for i in 1 to arg'length loop
if xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT or j = chars then
exit;
elsif xarg(i) = ':' then
icolon := true;
elsif xarg(i) = '.' then
idot := true;
elsif xarg (i) /= '_' then
j := j + 1;
end if;
end loop;
if j = chars then
good := true; -- There are enough charactes to read
end if;
colon := icolon;
if idot and icolon then
dot := false;
else
dot := idot;
end if;
end procedure check_punctuation;
-- purpose: Searches a line for a ":" and replaces it with a ".".
procedure fix_colon (
arg : inout STRING;
chars : in integer) is
alias xarg : STRING (1 to arg'length) is arg; -- make it downto range
variable j : INTEGER := 0; -- charters read
begin
for i in 1 to arg'length loop
if xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT or j > chars then
exit;
elsif xarg(i) = ':' then
xarg (i) := '.';
elsif xarg (i) /= '_' then
j := j + 1;
end if;
end loop;
end procedure fix_colon;
procedure WRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_float; -- floating point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
variable s : STRING(1 to value'high - value'low +3);
variable sindx : INTEGER;
begin -- function write
s(1) := MVL9_to_char(STD_ULOGIC(VALUE(VALUE'high)));
s(2) := ':';
sindx := 3;
for i in VALUE'high-1 downto 0 loop
s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));
sindx := sindx + 1;
end loop;
s(sindx) := ':';
sindx := sindx + 1;
for i in -1 downto VALUE'low loop
s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));
sindx := sindx + 1;
end loop;
WRITE (L, s, JUSTIFIED, FIELD);
end procedure WRITE;
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float) is
-- Possible data: 0:0000:0000000
-- 000000000000
variable c : CHARACTER;
variable mv : UNRESOLVED_float (VALUE'range);
variable readOk : BOOLEAN;
variable lastu : BOOLEAN := false; -- last character was an "_"
variable i : INTEGER; -- index variable
begin -- READ
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
READ (l, c, readOk);
if VALUE'length > 0 then
i := value'high;
readloop : loop
if readOk = false then -- Bail out if there was a bad read
report "float_pkg"
& "READ(float): "
& "Error end of file encountered."
severity error;
return;
elsif c = ' ' or c = CR or c = HT then -- reading done.
if (i /= value'low) then
report "float_pkg"
& "READ(float): "
& "Warning: Value truncated."
severity warning;
return;
end if;
elsif c = '_' then
if i = value'high then -- Begins with an "_"
report "float_pkg"
& "READ(float): "
& "String begins with an ""_""" severity error;
return;
elsif lastu then -- "__" detected
report "float_pkg"
& "READ(float): "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif c = ':' or c = '.' then -- separator, ignore
if not (i = -1 or i = value'high-1) then
report "float_pkg"
& "READ(float): "
& "Warning: Separator point does not match number format: '"
& c & "' encountered at location " & INTEGER'image(i) & "."
severity warning;
end if;
lastu := false;
elsif (char_to_MVL9plus(c) = error) then
report "float_pkg"
& "READ(float): "
& "Error: Character '" & c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv (i) := char_to_MVL9(c);
i := i - 1;
if i < value'low then
VALUE := mv;
return;
end if;
lastu := false;
end if;
READ (l, c, readOk);
end loop readloop;
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is
-- Possible data: 0:0000:0000000
-- 000000000000
variable c : CHARACTER;
variable mv : UNRESOLVED_float (VALUE'range);
variable lastu : BOOLEAN := false; -- last character was an "_"
variable i : INTEGER; -- index variable
variable readOk : BOOLEAN;
begin -- READ
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
READ (l, c, readOk);
if VALUE'length > 0 then
i := value'high;
good := false;
readloop : loop
if readOk = false then -- Bail out if there was a bad read
return;
elsif c = ' ' or c = CR or c = HT then -- reading done
return;
elsif c = '_' then
if i = 0 then -- Begins with an "_"
return;
elsif lastu then -- "__" detected
return;
else
lastu := true;
end if;
elsif c = ':' or c = '.' then -- separator, ignore
-- good := (i = -1 or i = value'high-1);
lastu := false;
elsif (char_to_MVL9plus(c) = error) then
return;
else
mv (i) := char_to_MVL9(c);
i := i - 1;
if i < value'low then
good := true;
VALUE := mv;
return;
end if;
lastu := false;
end if;
READ (l, c, readOk);
end loop readloop;
else
good := true; -- read into a null array
end if;
end procedure READ;
procedure OWRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0) is -- width of field
begin
WRITE (L => L,
VALUE => to_ostring(VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure OWRITE;
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_float) is
constant ne : INTEGER := ((value'length+2)/3) * 3; -- pad
variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv
variable slvu : ufixed (VALUE'range); -- Unsigned fixed point
variable c : CHARACTER;
variable ok : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits
variable colon, dot : BOOLEAN;
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
check_punctuation (arg => L.all,
colon => colon,
dot => dot,
good => ok,
chars => ne/3);
if not ok then
report "float_pkg" & "OREAD: "
& "short string encounted: " & L.all
& " needs to have " & integer'image (ne/3)
& " valid octal characters."
severity error;
return;
elsif dot then
OREAD (L, slvu, ok); -- read it like a UFIXED number
if not ok then
report "float_pkg" & "OREAD: "
& "error encounted reading STRING " & L.all
severity error;
return;
else
VALUE := UNRESOLVED_float (slvu);
end if;
elsif colon then
OREAD (L, nybble, ok); -- read the sign bit
if not ok then
report "float_pkg" & "OREAD: "
& "End of string encountered"
severity error;
return;
elsif nybble (2 downto 1) /= "00" then
report "float_pkg" & "OREAD: "
& "Illegal sign bit STRING encounted "
severity error;
return;
end if;
read (l, c, ok); -- read the colon
fix_colon (L.all, ne/3); -- replaces the colon with a ".".
OREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number
if not ok then
report "float_pkg" & "OREAD: "
& "error encounted reading STRING " & L.all
severity error;
return;
else
slvu (slvu'high) := nybble (0);
VALUE := UNRESOLVED_float (slvu);
end if;
else
OREAD (L, slv, ok);
if not ok then
report "float_pkg" & "OREAD: "
& "Error encounted during read"
severity error;
return;
end if;
if (or_reduce (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then
report "float_pkg" & "OREAD: "
& "Vector truncated."
severity error;
return;
end if;
VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),
VALUE'high, -VALUE'low);
end if;
end if;
end procedure OREAD;
procedure OREAD(L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is
constant ne : INTEGER := ((value'length+2)/3) * 3; -- pad
variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv
variable slvu : ufixed (VALUE'range); -- Unsigned fixed point
variable c : CHARACTER;
variable ok : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits
variable colon, dot : BOOLEAN;
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
GOOD := false;
Skip_whitespace (L);
if VALUE'length > 0 then
check_punctuation (arg => L.all,
colon => colon,
dot => dot,
good => ok,
chars => ne/3);
if not ok then
return;
elsif dot then
OREAD (L, slvu, ok); -- read it like a UFIXED number
if not ok then
return;
else
VALUE := UNRESOLVED_float (slvu);
end if;
elsif colon then
OREAD (L, nybble, ok); -- read the sign bit
if not ok then
return;
elsif nybble (2 downto 1) /= "00" then
return;
end if;
read (l, c, ok); -- read the colon
fix_colon (L.all, ne/3); -- replaces the colon with a ".".
OREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number
if not ok then
return;
else
slvu (slvu'high) := nybble (0);
VALUE := UNRESOLVED_float (slvu);
end if;
else
OREAD (L, slv, ok);
if not ok then
return;
end if;
if (or_reduce (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then
return;
end if;
VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),
VALUE'high, -VALUE'low);
end if;
GOOD := true;
end if;
end procedure OREAD;
procedure HWRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0) is -- width of field
begin
WRITE (L => L,
VALUE => to_hstring(VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure HWRITE;
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float) is
constant ne : INTEGER := ((value'length+3)/4) * 4; -- pad
variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv
variable slvu : ufixed (VALUE'range); -- Unsigned fixed point
variable c : CHARACTER;
variable ok : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits
variable colon, dot : BOOLEAN;
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
check_punctuation (arg => L.all,
colon => colon,
dot => dot,
good => ok,
chars => ne/4);
if not ok then
report "float_pkg" & "HREAD: "
& "short string encounted: " & L.all
& " needs to have " & integer'image (ne/4)
& " valid hex characters."
severity error;
return;
elsif dot then
HREAD (L, slvu, ok); -- read it like a UFIXED number
if not ok then
report "float_pkg" & "HREAD: "
& "error encounted reading STRING " & L.all
severity error;
return;
else
VALUE := UNRESOLVED_float (slvu);
end if;
elsif colon then
HREAD (L, nybble, ok); -- read the sign bit
if not ok then
report "float_pkg" & "HREAD: "
& "End of string encountered"
severity error;
return;
elsif nybble (3 downto 1) /= "000" then
report "float_pkg" & "HREAD: "
& "Illegal sign bit STRING encounted "
severity error;
return;
end if;
read (l, c, ok); -- read the colon
fix_colon (L.all, ne/4); -- replaces the colon with a ".".
HREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number
if not ok then
report "float_pkg" & "HREAD: "
& "error encounted reading STRING " & L.all
severity error;
return;
else
slvu (slvu'high) := nybble (0);
VALUE := UNRESOLVED_float (slvu);
end if;
else
HREAD (L, slv, ok);
if not ok then
report "float_pkg" & "HREAD: "
& "Error encounted during read"
severity error;
return;
end if;
if (or_reduce (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then
report "float_pkg" & "HREAD: "
& "Vector truncated."
severity error;
return;
end if;
VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),
VALUE'high, -VALUE'low);
end if;
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is
constant ne : INTEGER := ((value'length+3)/4) * 4; -- pad
variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv
variable slvu : ufixed (VALUE'range); -- Unsigned fixed point
variable c : CHARACTER;
variable ok : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits
variable colon, dot : BOOLEAN;
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
GOOD := false;
Skip_whitespace (L);
if VALUE'length > 0 then
check_punctuation (arg => L.all,
colon => colon,
dot => dot,
good => ok,
chars => ne/4);
if not ok then
return;
elsif dot then
HREAD (L, slvu, ok); -- read it like a UFIXED number
if not ok then
return;
else
VALUE := UNRESOLVED_float (slvu);
end if;
elsif colon then
HREAD (L, nybble, ok); -- read the sign bit
if not ok then
return;
elsif nybble (3 downto 1) /= "000" then
return;
end if;
read (l, c, ok); -- read the colon
fix_colon (L.all, ne/4); -- replaces the colon with a ".".
HREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number
if not ok then
return;
else
slvu (slvu'high) := nybble (0);
VALUE := UNRESOLVED_float (slvu);
end if;
else
HREAD (L, slv, ok);
if not ok then
return;
end if;
if (or_reduce (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then
return;
end if;
VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),
VALUE'high, -VALUE'low);
end if;
GOOD := true;
end if;
end procedure HREAD;
function to_string (value : UNRESOLVED_float) return STRING is
variable s : STRING(1 to value'high - value'low +3);
variable sindx : INTEGER;
begin -- function write
s(1) := MVL9_to_char(STD_ULOGIC(VALUE(VALUE'high)));
s(2) := ':';
sindx := 3;
for i in VALUE'high-1 downto 0 loop
s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));
sindx := sindx + 1;
end loop;
s(sindx) := ':';
sindx := sindx + 1;
for i in -1 downto VALUE'low loop
s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));
sindx := sindx + 1;
end loop;
return s;
end function to_string;
function to_hstring (value : UNRESOLVED_float) return STRING is
variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0);
begin
floop : for i in slv'range loop
slv(i) := to_X01Z (value(i + value'low));
end loop floop;
return to_hstring (slv);
end function to_hstring;
function to_ostring (value : UNRESOLVED_float) return STRING is
variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0);
begin
floop : for i in slv'range loop
slv(i) := to_X01Z (value(i + value'low));
end loop floop;
return to_ostring (slv);
end function to_ostring;
function from_string (
bstring : STRING; -- binary string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
READ (L, result, good);
deallocate (L);
assert (good)
report "float_pkg"
& "from_string: Bad string " & bstring
severity error;
return result;
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
OREAD (L, result, good);
deallocate (L);
assert (good)
report "float_pkg"
& "from_ostring: Bad string " & ostring
severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
HREAD (L, result, good);
deallocate (L);
assert (good)
report "float_pkg"
& "from_hstring: Bad string " & hstring
severity error;
return result;
end function from_hstring;
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float is
begin
return from_string (bstring => bstring,
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float is
begin
return from_ostring (ostring => ostring,
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float is
begin
return from_hstring (hstring => hstring,
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function from_hstring;
-- rtl_synthesis on
-- pragma synthesis_on
function to_float (
arg : STD_LOGIC_VECTOR;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction
return UNRESOLVED_float is
begin
return to_float (
arg => std_ulogic_vector (arg),
exponent_width => exponent_width,
fraction_width => fraction_width);
end function to_float;
function to_float (
arg : STD_LOGIC_VECTOR;
size_res : UNRESOLVED_float)
return UNRESOLVED_float is
begin
return to_float (
arg => std_ulogic_vector (arg),
size_res => size_res);
end function to_float;
-- For Verilog compatability
function realtobits (arg : REAL) return STD_LOGIC_VECTOR is
variable result : float64; -- 64 bit floating point
begin
result := to_float (arg => arg,
exponent_width => float64'high,
fraction_width => -float64'low);
return to_slv (result);
end function realtobits;
function bitstoreal (arg : STD_LOGIC_VECTOR) return REAL is
variable arg64 : float64; -- arg converted to float
begin
arg64 := to_float (arg => arg,
exponent_width => float64'high,
fraction_width => -float64'low);
return to_real (arg64);
end function bitstoreal;
end package body float_pkg;
| gpl-3.0 | 78715945e4b95877719e9dd0a5a9e635 | 0.556163 | 4.216089 | false | false | false | false |
Feuerwerk/fpgaNES | videomem.vhd | 1 | 6,943 | -- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: videomem.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 18.0.0 Build 614 04/24/2018 SJ Lite Edition
-- ************************************************************
--Copyright (C) 2018 Intel Corporation. All rights reserved.
--Your use of Intel Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Intel Program License
--Subscription Agreement, the Intel Quartus Prime License Agreement,
--the Intel FPGA IP License Agreement, or other applicable license
--agreement, including, without limitation, that your use is for
--the sole purpose of programming logic devices manufactured by
--Intel and sold by Intel or its authorized distributors. Please
--refer to the applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY videomem IS
PORT
(
address : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rden : IN STD_LOGIC := '1';
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END videomem;
ARCHITECTURE SYN OF videomem IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "NORMAL",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone V",
lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=VRAM",
lpm_type => "altsyncram",
numwords_a => 2048,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => 11,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
clocken0 => clken,
data_a => data,
rden_a => rden,
wren_a => wren,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "1"
-- Retrieval info: PRIVATE: Clken NUMERIC "1"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "VRAM"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "videomem.hex"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "1"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=VRAM"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]"
-- Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC "clken"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL videomem.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL videomem.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL videomem.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL videomem.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL videomem_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-3.0 | 006fe4efe77a15d0fdd44e090f3cfb5f | 0.660809 | 3.519007 | false | false | false | false |
astoria-d/super-duper-nes | test/level_shift_test01/level_shift_test01.vhd | 1 | 3,114 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.conv_integer;
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_unsigned.all;
--
-- MOTO NES FPGA On DE0-CV Environment Virtual Cuicuit Board
-- All of the components are assembled and instanciated on this board.
--
entity level_shift_test01 is
port (
pi_base_clk : in std_logic;
pi_sw : in std_logic_vector(9 downto 0);
pi_btn_n : in std_logic_vector(3 downto 0);
po_led_r : out std_logic_vector(9 downto 0);
po_led_g : out std_logic_vector(7 downto 0);
pio_gpio0 : inout std_logic_vector(7 downto 0);
pio_gpio1 : inout std_logic_vector(7 downto 0)
);
end level_shift_test01;
architecture rtl of level_shift_test01 is
--slow down button update timing.
constant FREQ_DEVIDE : integer := 1000000;
signal reg_cnt_devider : integer range 0 to FREQ_DEVIDE;
signal reg_8bit_cnt : std_logic_vector(7 downto 0);
signal wr_rst_n : std_logic;
signal wr_direction : std_logic;
signal wr_dvd : std_logic;
begin
wr_rst_n <= pi_btn_n(0);
wr_direction <= pi_sw(9);
wr_dvd <= pi_sw(8);
gpio_p : process (wr_rst_n, pi_base_clk)
begin
if (wr_rst_n = '0') then
pio_gpio0 <= (others => 'Z');
pio_gpio1 <= (others => 'Z');
po_led_r <= (others => '0');
po_led_g <= (others => '0');
elsif (rising_edge(pi_base_clk)) then
if (wr_direction = '0') then
--case off = cp gpio 1 to 0
pio_gpio0 <= (others => 'Z');
pio_gpio1 <= pi_sw(7 downto 0);
po_led_r <= pi_sw;
po_led_g <= pio_gpio0;
else
--on = cp gpio 0 to 1
pio_gpio0 <= reg_8bit_cnt;
pio_gpio1 <= (others => 'Z');
po_led_r(7 downto 0) <= pio_gpio1;
po_led_r(9 downto 8) <= pi_sw(9 downto 8);
po_led_g <= reg_8bit_cnt;
end if;
end if;
end process;
--key3 button proc.
key3_cnt_p : process (wr_rst_n, pi_base_clk)
begin
if (wr_rst_n = '0') then
reg_8bit_cnt <= (others => '0');
elsif (rising_edge(pi_base_clk)) then
if (wr_dvd = '1') then
--slow down count up
if (pi_btn_n(3) = '0' and reg_cnt_devider = 0) then
reg_8bit_cnt <= reg_8bit_cnt + 1;
end if;
else
--clock speed count up.
if (pi_btn_n(3) = '0') then
reg_8bit_cnt <= reg_8bit_cnt + 1;
end if;
end if;
end if;
end process;
--
cnt_devide_p : process (wr_rst_n, pi_base_clk)
begin
if (wr_rst_n = '0') then
reg_cnt_devider <= 0;
elsif (rising_edge(pi_base_clk)) then
reg_cnt_devider <= reg_cnt_devider + 1;
end if;
end process;
end rtl;
| apache-2.0 | a4c37becf5bacf1c0f45dcf7c864fa94 | 0.495183 | 3.271008 | false | false | false | false |
natsutan/NPU | fpga_implement/npu8/npu8.srcs/sources_1/ip/mult_16_16/sim/mult_16_16.vhd | 1 | 4,813 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:mult_gen:12.0
-- IP Revision: 12
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY mult_gen_v12_0_12;
USE mult_gen_v12_0_12.mult_gen_v12_0_12;
ENTITY mult_16_16 IS
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
P : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END mult_16_16;
ARCHITECTURE mult_16_16_arch OF mult_16_16 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF mult_16_16_arch: ARCHITECTURE IS "yes";
COMPONENT mult_gen_v12_0_12 IS
GENERIC (
C_VERBOSITY : INTEGER;
C_MODEL_TYPE : INTEGER;
C_OPTIMIZE_GOAL : INTEGER;
C_XDEVICEFAMILY : STRING;
C_HAS_CE : INTEGER;
C_HAS_SCLR : INTEGER;
C_LATENCY : INTEGER;
C_A_WIDTH : INTEGER;
C_A_TYPE : INTEGER;
C_B_WIDTH : INTEGER;
C_B_TYPE : INTEGER;
C_OUT_HIGH : INTEGER;
C_OUT_LOW : INTEGER;
C_MULT_TYPE : INTEGER;
C_CE_OVERRIDES_SCLR : INTEGER;
C_CCM_IMP : INTEGER;
C_B_VALUE : STRING;
C_HAS_ZERO_DETECT : INTEGER;
C_ROUND_OUTPUT : INTEGER;
C_ROUND_PT : INTEGER
);
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
CE : IN STD_LOGIC;
SCLR : IN STD_LOGIC;
P : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT mult_gen_v12_0_12;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF A: SIGNAL IS "xilinx.com:signal:data:1.0 a_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF B: SIGNAL IS "xilinx.com:signal:data:1.0 b_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF P: SIGNAL IS "xilinx.com:signal:data:1.0 p_intf DATA";
BEGIN
U0 : mult_gen_v12_0_12
GENERIC MAP (
C_VERBOSITY => 0,
C_MODEL_TYPE => 0,
C_OPTIMIZE_GOAL => 1,
C_XDEVICEFAMILY => "kintexu",
C_HAS_CE => 0,
C_HAS_SCLR => 0,
C_LATENCY => 4,
C_A_WIDTH => 16,
C_A_TYPE => 0,
C_B_WIDTH => 16,
C_B_TYPE => 0,
C_OUT_HIGH => 31,
C_OUT_LOW => 24,
C_MULT_TYPE => 0,
C_CE_OVERRIDES_SCLR => 0,
C_CCM_IMP => 0,
C_B_VALUE => "10000001",
C_HAS_ZERO_DETECT => 0,
C_ROUND_OUTPUT => 0,
C_ROUND_PT => 0
)
PORT MAP (
CLK => CLK,
A => A,
B => B,
CE => '1',
SCLR => '0',
P => P
);
END mult_16_16_arch;
| bsd-3-clause | 0b67436e062f68302881097cff666f25 | 0.665282 | 3.570475 | false | false | false | false |
jakubcabal/uart-for-fpga | rtl/uart.vhd | 2 | 5,651 | --------------------------------------------------------------------------------
-- PROJECT: SIMPLE UART FOR FPGA
--------------------------------------------------------------------------------
-- AUTHORS: Jakub Cabal <[email protected]>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://github.com/jakubcabal/uart-for-fpga
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
-- SIMPLE UART FOR FPGA
-- ====================
-- UART FOR FPGA REQUIRES: 1 START BIT, 8 DATA BITS, 1 STOP BIT!!!
-- OTHER PARAMETERS CAN BE SET USING GENERICS.
entity UART is
Generic (
CLK_FREQ : integer := 50e6; -- system clock frequency in Hz
BAUD_RATE : integer := 115200; -- baud rate value
PARITY_BIT : string := "none"; -- type of parity: "none", "even", "odd", "mark", "space"
USE_DEBOUNCER : boolean := True -- enable/disable debouncer
);
Port (
-- CLOCK AND RESET
CLK : in std_logic; -- system clock
RST : in std_logic; -- high active synchronous reset
-- UART INTERFACE
UART_TXD : out std_logic; -- serial transmit data
UART_RXD : in std_logic; -- serial receive data
-- USER DATA INPUT INTERFACE
DIN : in std_logic_vector(7 downto 0); -- input data to be transmitted over UART
DIN_VLD : in std_logic; -- when DIN_VLD = 1, input data (DIN) are valid
DIN_RDY : out std_logic; -- when DIN_RDY = 1, transmitter is ready and valid input data will be accepted for transmiting
-- USER DATA OUTPUT INTERFACE
DOUT : out std_logic_vector(7 downto 0); -- output data received via UART
DOUT_VLD : out std_logic; -- when DOUT_VLD = 1, output data (DOUT) are valid (is assert only for one clock cycle)
FRAME_ERROR : out std_logic; -- when FRAME_ERROR = 1, stop bit was invalid (is assert only for one clock cycle)
PARITY_ERROR : out std_logic -- when PARITY_ERROR = 1, parity bit was invalid (is assert only for one clock cycle)
);
end entity;
architecture RTL of UART is
constant OS_CLK_DIV_VAL : integer := integer(real(CLK_FREQ)/real(16*BAUD_RATE));
constant UART_CLK_DIV_VAL : integer := integer(real(CLK_FREQ)/real(OS_CLK_DIV_VAL*BAUD_RATE));
signal os_clk_en : std_logic;
signal uart_rxd_meta_n : std_logic;
signal uart_rxd_synced_n : std_logic;
signal uart_rxd_debounced_n : std_logic;
signal uart_rxd_debounced : std_logic;
begin
-- -------------------------------------------------------------------------
-- UART OVERSAMPLING (~16X) CLOCK DIVIDER AND CLOCK ENABLE FLAG
-- -------------------------------------------------------------------------
os_clk_divider_i : entity work.UART_CLK_DIV
generic map(
DIV_MAX_VAL => OS_CLK_DIV_VAL,
DIV_MARK_POS => OS_CLK_DIV_VAL-1
)
port map (
CLK => CLK,
RST => RST,
CLEAR => RST,
ENABLE => '1',
DIV_MARK => os_clk_en
);
-- -------------------------------------------------------------------------
-- UART RXD CROSS DOMAIN CROSSING
-- -------------------------------------------------------------------------
uart_rxd_cdc_reg_p : process (CLK)
begin
if (rising_edge(CLK)) then
uart_rxd_meta_n <= not UART_RXD;
uart_rxd_synced_n <= uart_rxd_meta_n;
end if;
end process;
-- -------------------------------------------------------------------------
-- UART RXD DEBAUNCER
-- -------------------------------------------------------------------------
use_debouncer_g : if (USE_DEBOUNCER = True) generate
debouncer_i : entity work.UART_DEBOUNCER
generic map(
LATENCY => 4
)
port map (
CLK => CLK,
DEB_IN => uart_rxd_synced_n,
DEB_OUT => uart_rxd_debounced_n
);
end generate;
not_use_debouncer_g : if (USE_DEBOUNCER = False) generate
uart_rxd_debounced_n <= uart_rxd_synced_n;
end generate;
uart_rxd_debounced <= not uart_rxd_debounced_n;
-- -------------------------------------------------------------------------
-- UART RECEIVER
-- -------------------------------------------------------------------------
uart_rx_i: entity work.UART_RX
generic map (
CLK_DIV_VAL => UART_CLK_DIV_VAL,
PARITY_BIT => PARITY_BIT
)
port map (
CLK => CLK,
RST => RST,
-- UART INTERFACE
UART_CLK_EN => os_clk_en,
UART_RXD => uart_rxd_debounced,
-- USER DATA OUTPUT INTERFACE
DOUT => DOUT,
DOUT_VLD => DOUT_VLD,
FRAME_ERROR => FRAME_ERROR,
PARITY_ERROR => PARITY_ERROR
);
-- -------------------------------------------------------------------------
-- UART TRANSMITTER
-- -------------------------------------------------------------------------
uart_tx_i: entity work.UART_TX
generic map (
CLK_DIV_VAL => UART_CLK_DIV_VAL,
PARITY_BIT => PARITY_BIT
)
port map (
CLK => CLK,
RST => RST,
-- UART INTERFACE
UART_CLK_EN => os_clk_en,
UART_TXD => UART_TXD,
-- USER DATA INPUT INTERFACE
DIN => DIN,
DIN_VLD => DIN_VLD,
DIN_RDY => DIN_RDY
);
end architecture;
| mit | dc5e023da43ed7711fdf031d763944e5 | 0.456379 | 4.394246 | false | false | false | false |
sinkswim/DLX-Pro | DLX_simulation_cfg/a.b-DataPath.core/a.b.c-execute.vhd | 1 | 8,465 | library ieee;
use ieee.std_logic_1164.all;
-- Units present in this block (refer to DP schematic):
-- adder1
-- adder2
-- jreg_mux21
-- concatenate16
-- oprnd1_mux41
-- oprnd2_mux41
-- regaddr_mux21
-- forwarding unit
-- alusrc_mux21
-- ALU
-- plus4_adder
-- branch_circ
-- PSW
-- link_mux21
-- lhi_mux21
-- movs2i_mux21
entity execute is
port(
clk : in std_logic;
rst : in std_logic;
-- inputs from IDEX pipeline reg
controls_in : in std_logic_vector(21 downto 0); -- we have 22 signals: CU generates a total of 23 signals (including 5 ALUOP signals), but 1 signal (unsigned) is already exhausted in the DECODE stage
ext25_0 : in std_logic_vector(31 downto 0); -- bits 25_0 of instr. sign/unsign extended to 32 bits
nextPC : in std_logic_vector(31 downto 0);
op_A : in std_logic_vector(31 downto 0);
op_B : in std_logic_vector(31 downto 0);
ext15_0 : in std_logic_vector(31 downto 0); -- bits 15_0 of instr. sign/unsign extended to 32 bits
inst15_0 : in std_logic_vector(15 downto 0); -- bits 15_0 of instr.
rt_inst : in std_logic_vector(4 downto 0);
rd_inst : in std_logic_vector(4 downto 0);
rs_inst : in std_logic_vector(4 downto 0);
-- inputs from other sources
unaligned : in std_logic; -- from MMU, '1' when an unaligned access to memory has been done
forw_dataWB : in std_logic_vector(31 downto 0); -- data from WB stage that is used if forwarding needed
forw_dataMEM : in std_logic_vector(31 downto 0); -- data from MEM stage that is used if forwarding needed
RFaddr_WB : in std_logic_vector(4 downto 0); -- addr of RF from WB stage, goes to forwarding unit
RFaddr_MEM : in std_logic_vector(4 downto 0); -- addr of RF from MEM stage, goes to forwarding unit
regwriteWB : in std_logic; -- reg_write ctrl signal from WB stage
regwriteMEM : in std_logic; -- reg_write ctrl signal from MEM stage
-- outputs
controls_out : out std_logic_vector(10 downto 0); -- 11 control signals go to MEM stage (11 are exhausted in the EXE stage)
toPC1 : out std_logic_vector(31 downto 0);
toPC2 : out std_logic_vector(31 downto 0);
branchTaken : out std_logic;
addrMem : out std_logic_vector(31 downto 0);
writeData : out std_logic_vector(31 downto 0);
addrRF : out std_logic_vector(4 downto 0);
IDEX_rt : out std_logic_vector(4 downto 0); -- goes to hazard unit
IDEX_memread : out std_logic_vector(3 downto 0) -- goes to hazard unit
);
end execute;
architecture rtl of execute is
-- component declarations
component adder is
port(
a : in std_logic_vector(31 downto 0);
b : in std_logic_vector(31 downto 0);
res : out std_logic_vector(31 downto 0)
);
end component;
component ALU is
port(
-- inputs
alu_op : in std_logic_vector(4 downto 0); -- specifies alu operation to be performed (from CU in ID stage)
a : in std_logic_vector(31 downto 0); -- operand 1
b : in std_logic_vector(31 downto 0); -- operand 2
-- outputs
-- cout : out std_logic; -- cout of operation; to PSW
ovf : out std_logic; -- ovf of operation; to PSW
zero : out std_logic; -- zero when res is all 0s; to branch_circ
res : out std_logic_vector(31 downto 0) -- result of the arit-log operation on a and b
);
end component;
component branch_circ is
port(
branch_type : in std_logic; -- BNEZ is branch_type = '1', BEQZ is branch_type = '0'
zero : in std_logic; -- from ALU, 1 when the result of an operation yields zero
branch_taken : out std_logic -- 1 means the branch has to be taken
);
end component;
component concat16 is
port(
string16 : in std_logic_vector(15 downto 0);
string32 : out std_logic_vector(31 downto 0) -- this goes to lhi_mux21
);
end component;
component forward is
port(
rt_addr_IDEX : in std_logic_vector(4 downto 0);
rs_addr_IDEX : in std_logic_vector(4 downto 0);
rd_addr_EXMEM : in std_logic_vector(4 downto 0);
rd_addr_MEMWB : in std_logic_vector(4 downto 0);
regwrite_EXMEM : in std_logic;
regwrite_MEMWB : in std_logic;
forwardA : out std_logic_vector(1 downto 0); -- 00 from regfile, 01 from memwb, 10 from previous alu result
forwardB : out std_logic_vector(1 downto 0) -- as above
);
end component;
component mux21 is
generic(
NBIT : integer := 32
);
port (
a : in std_logic_vector(NBIT - 1 downto 0);
b : in std_logic_vector(NBIT - 1 downto 0);
s : in std_logic;
y : out std_logic_vector(NBIT - 1 downto 0)
);
end component;
component mux41 is
generic(
NBIT : integer := 32
);
port (
a : in std_logic_vector(NBIT - 1 downto 0);
b : in std_logic_vector(NBIT - 1 downto 0);
c : in std_logic_vector(NBIT - 1 downto 0);
s : in std_logic_vector(1 downto 0);
y : out std_logic_vector(NBIT - 1 downto 0)
);
end component;
component PSWreg is
port(
-- inputs
rst : in std_logic;
clk : in std_logic;
unaligned : in std_logic;
-- cout : in std_logic;
ovf : in std_logic;
-- outputs
status : out std_logic_vector(31 downto 0)
);
end component;
--signal declarations
signal lhi_value_i : std_logic_vector(31 downto 0); -- inst15_0 ## 0...0 for lhi instruction
signal zero_i : std_logic; -- driven by ALU: '0' when result of ALU operation is all 0s
signal psw_status_i : std_logic_vector(31 downto 0); -- content of PSW reg
signal ovf_i : std_logic; -- driven by ALU: '1' when operation had overflow
signal A_inALU_i : std_logic_vector(31 downto 0);
signal B_inALU_i : std_logic_vector(31 downto 0);
signal res_outALU_i : std_logic_vector(31 downto 0);
signal resAdd1_i : std_logic_vector(31 downto 0);
signal link_value_i : std_logic_vector(31 downto 0);
signal link2lhi_wire_i : std_logic_vector(31 downto 0); -- goes from link mux to lhi mux
signal lhi2mov_wire_i : std_logic_vector(31 downto 0); -- goes from lhi mux to movs2i mux
signal mux41B_wire_i : std_logic_vector(31 downto 0); -- goes from oprnd2_mux41 to alusrc_mux
signal forwardA_i : std_logic_vector(1 downto 0);
signal forwardB_i : std_logic_vector(1 downto 0);
begin
-- concurrent signal assignments
controls_out <= controls_in(21) & controls_in(18) & controls_in (13 downto 5); --- regwrite, link, sb, sw, lbu, lw, lhu, lb, memtoreg, jump, branch
writeData <= mux41B_wire_i; -- data that goes into Data Ram for writing
IDEX_rt <= rt_inst;
IDEX_memread <= controls_in(11 downto 8);
--component instantiations
adder1 : adder port map (ext25_0, nextPC, resAdd1_i);
adder2 : adder port map (nextPC, ext15_0, toPC2);
plus4_adder : adder port map(nextPC, X"00000004", link_value_i);
jreg_mux21 : mux21 generic map (32) port map (A_inALU_i, resAdd1_i, controls_in(20),toPC1);
link_mux21 : mux21 generic map (32) port map (link_value_i, res_outALU_i, controls_in(18), link2lhi_wire_i);
lhi_mux21 : mux21 generic map (32) port map (lhi_value_i, link2lhi_wire_i,controls_in(17), lhi2mov_wire_i);
regaddr_mux21 : mux21 generic map (5) port map (rd_inst, rt_inst, controls_in(16), addrRF);
movs2i_mux21 : mux21 generic map (32) port map (psw_status_i, lhi2mov_wire_i, controls_in(15), addrMem);
alusrc_mux21 : mux21 generic map (32) port map (ext15_0, mux41B_wire_i, controls_in(14), B_inALU_i);
oprnd1_mux41 : mux41 generic map (32) port map (op_A, forw_dataWB, forw_dataMEM, forwardA_i, A_inALU_i);
oprnd2_mux41 : mux41 generic map (32) port map (op_B, forw_dataWB, forw_dataMEM, forwardB_i, mux41B_wire_i);
concatenate16 : concat16 port map (inst15_0, lhi_value_i);
forwarding_unit : forward port map (rt_inst, rs_inst, RFaddr_MEM, RFaddr_WB, regwriteMEM, regwriteWB, forwardA_i, forwardB_i);
branch_circuit : branch_circ port map (controls_in(19), zero_i, branchTaken);
PSW : PSWreg port map (rst, clk, unaligned, ovf_i, psw_status_i);
EXALU : ALU port map (controls_in(4 downto 0), A_inALU_i, B_inALU_i, ovf_i, zero_i, res_outALU_i);
end rtl;
| mit | 8406ddfad5767518f5efa9d051392f3c | 0.632014 | 3.108704 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/LogicStart_MegaWing_Pinout.vhd | 13 | 11,130 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.3
-- \ \ Application :
-- / / Filename : xil_10080_19
-- /___/ /\ Timestamp : 02/08/2013 16:21:11
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
library board;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.zpu_config.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
entity LogicStart_MegaWing_Pinout is
port (
Audio : in std_logic;
Seg7_dot : in std_logic;
Seg7_enable : in std_logic_vector (3 downto 0);
Seg7_segdata : in std_logic_vector (6 downto 0);
-- VGA_Red : in std_logic_vector (2 downto 0);
-- VGA_Green : in std_logic_vector (2 downto 0);
-- VGA_Blue : in std_logic_vector (1 downto 0);
VGA_Red2 : in std_logic;
VGA_Red1 : in std_logic;
VGA_Red0 : in std_logic;
VGA_Green2 : in std_logic;
VGA_Green1 : in std_logic;
VGA_Green0 : in std_logic;
VGA_Blue1 : in std_logic;
VGA_Blue0 : in std_logic;
VGA_Hsync : in std_logic;
VGA_Vsync : in std_logic;
SPI_CLK : in std_logic;
SPI_MOSI : in std_logic;
SPI_MISO : out std_logic;
SPI_CS : in std_logic;
gpio_bus_in : out std_logic_vector(97 downto 0);
gpio_bus_out : in std_logic_vector(147 downto 0);
WING_AH0 : inout std_logic;
WING_AH1 : inout std_logic;
WING_AH2 : inout std_logic;
WING_AH3 : inout std_logic;
WING_AH4 : inout std_logic;
WING_AH5 : inout std_logic;
WING_AH6 : inout std_logic;
WING_AH7 : inout std_logic;
WING_AL0 : inout std_logic;
WING_AL1 : inout std_logic;
WING_AL2 : inout std_logic;
WING_AL3 : inout std_logic;
WING_AL4 : inout std_logic;
WING_AL5 : inout std_logic;
WING_AL6 : inout std_logic;
WING_AL7 : inout std_logic;
WING_BH0 : inout std_logic;
WING_BH1 : inout std_logic;
WING_BH2 : inout std_logic;
WING_BH3 : inout std_logic;
WING_BH4 : inout std_logic;
WING_BH5 : inout std_logic;
WING_BH6 : inout std_logic;
WING_BH7 : inout std_logic;
WING_BL0 : inout std_logic;
WING_BL1 : inout std_logic;
WING_BL2 : inout std_logic;
WING_BL3 : inout std_logic;
WING_BL4 : inout std_logic;
WING_BL5 : inout std_logic;
WING_BL6 : inout std_logic;
WING_BL7 : inout std_logic;
WING_CH0 : inout std_logic;
WING_CH1 : inout std_logic;
WING_CH2 : inout std_logic;
WING_CH3 : inout std_logic;
WING_CH4 : inout std_logic;
WING_CH5 : inout std_logic;
WING_CH6 : inout std_logic;
WING_CH7 : inout std_logic;
WING_CL0 : inout std_logic;
WING_CL1 : inout std_logic;
WING_CL2 : inout std_logic;
WING_CL3 : inout std_logic;
WING_CL4 : inout std_logic;
WING_CL5 : inout std_logic;
WING_CL6 : inout std_logic;
WING_CL7 : inout std_logic
);
end LogicStart_MegaWing_Pinout;
architecture BEHAVIORAL of LogicStart_MegaWing_Pinout is
-- signal gpio_o: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_t: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_i: std_logic_vector(zpuino_gpio_count-1 downto 0);
--
-- -- SPP signal is one more than GPIO count
-- signal gpio_spp_data: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_spp_read: std_logic_vector(zpuino_gpio_count-1 downto 0);
--
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
signal gpio_o: std_logic_vector(48 downto 0);
signal gpio_t: std_logic_vector(48 downto 0);
signal gpio_i: std_logic_vector(48 downto 0);
signal gpio_spp_data: std_logic_vector(48 downto 0);
signal gpio_spp_read: std_logic_vector(48 downto 0);
signal gpio_clk: std_logic;
begin
--gpio_bus_in(97 downto 49) <= gpio_spp_data;
--gpio_bus_in(48 downto 0) <= gpio_i;
gpio_clk <= gpio_bus_out(147);
gpio_o <= gpio_bus_out(146 downto 98);
gpio_t <= gpio_bus_out(97 downto 49);
gpio_spp_read <= gpio_bus_out(48 downto 0);
WING_BH2 <= Audio;
--7 Segment
WING_AL0 <= Seg7_enable(3);
WING_AL1 <= Seg7_dot;
WING_AL2 <= Seg7_enable(2);
WING_AL3 <= Seg7_segdata(4);
WING_AL4 <= Seg7_segdata(5);
WING_AL5 <= Seg7_segdata(2);
WING_AL6 <= Seg7_segdata(3);
WING_AL7 <= Seg7_segdata(0);
WING_AH0 <= Seg7_enable(1);
WING_AH1 <= Seg7_segdata(6);
WING_AH2 <= Seg7_segdata(1);
WING_AH3 <= Seg7_enable(0);
--VGA
WING_BL0 <= VGA_Vsync;
WING_BL1 <= VGA_Hsync;
WING_BL2 <= VGA_Blue0;
WING_BL3 <= VGA_Blue1;
WING_BL4 <= VGA_Green0;
WING_BL5 <= VGA_Green1;
WING_BL6 <= VGA_Green2;
WING_BL7 <= VGA_Red0;
WING_BH0 <= VGA_Red1;
WING_BH1 <= VGA_Red2;
--SPI ADC
WING_AH7 <= SPI_CLK;
WING_AH6 <= SPI_MOSI;
SPI_MISO <= WING_AH5;
--WING_AH4 <= SPI_CS;
-- pin00: IOPAD port map(I => gpio_o(0), O => gpio_i(0), T => gpio_t(0), C => gpio_clk,PAD => WING_AL0 );
-- pin01: IOPAD port map(I => gpio_o(1), O => gpio_i(1), T => gpio_t(1), C => gpio_clk,PAD => WING_AL1 );
-- pin02: IOPAD port map(I => gpio_o(2), O => gpio_i(2), T => gpio_t(2), C => gpio_clk,PAD => WING_AL2 );
-- pin03: IOPAD port map(I => gpio_o(3), O => gpio_i(3), T => gpio_t(3), C => gpio_clk,PAD => WING_AL3 );
-- pin04: IOPAD port map(I => gpio_o(4), O => gpio_i(4), T => gpio_t(4), C => gpio_clk,PAD => WING_AL4 );
-- pin05: IOPAD port map(I => gpio_o(5), O => gpio_i(5), T => gpio_t(5), C => gpio_clk,PAD => WING_AL5 );
-- pin06: IOPAD port map(I => gpio_o(6), O => gpio_i(6), T => gpio_t(6), C => gpio_clk,PAD => WING_AL6 );
-- pin07: IOPAD port map(I => gpio_o(7), O => gpio_i(7), T => gpio_t(7), C => gpio_clk,PAD => WING_AL7 );
-- pin08: IOPAD port map(I => gpio_o(8), O => gpio_i(8), T => gpio_t(8), C => gpio_clk,PAD => WING_AH0 );
-- pin09: IOPAD port map(I => gpio_o(9), O => gpio_i(9), T => gpio_t(9), C => gpio_clk,PAD => WING_AH1 );
-- pin10: IOPAD port map(I => gpio_o(10),O => gpio_i(10),T => gpio_t(10),C => gpio_clk,PAD => WING_AH2 );
-- pin11: IOPAD port map(I => gpio_o(11),O => gpio_i(11),T => gpio_t(11),C => gpio_clk,PAD => WING_AH3 );
pin12: IOPAD port map(I => gpio_o(12),O => gpio_i(12),T => gpio_t(12),C => gpio_clk,PAD => WING_AH4 );
-- pin13: IOPAD port map(I => gpio_o(13),O => gpio_i(13),T => gpio_t(13),C => gpio_clk,PAD => WING_AH5 );
-- pin14: IOPAD port map(I => gpio_o(14),O => gpio_i(14),T => gpio_t(14),C => gpio_clk,PAD => WING_AH6 );
-- pin15: IOPAD port map(I => gpio_o(15),O => gpio_i(15),T => gpio_t(15),C => gpio_clk,PAD => WING_AH7 );
-- pin16: IOPAD port map(I => gpio_o(16),O => gpio_i(16),T => gpio_t(16),C => gpio_clk,PAD => WING_BL0 );
-- pin17: IOPAD port map(I => gpio_o(17),O => gpio_i(17),T => gpio_t(17),C => gpio_clk,PAD => WING_BL1 );
-- pin18: IOPAD port map(I => gpio_o(18),O => gpio_i(18),T => gpio_t(18),C => gpio_clk,PAD => WING_BL2 );
-- pin19: IOPAD port map(I => gpio_o(19),O => gpio_i(19),T => gpio_t(19),C => gpio_clk,PAD => WING_BL3 );
-- pin20: IOPAD port map(I => gpio_o(20),O => gpio_i(20),T => gpio_t(20),C => gpio_clk,PAD => WING_BL4 );
-- pin21: IOPAD port map(I => gpio_o(21),O => gpio_i(21),T => gpio_t(21),C => gpio_clk,PAD => WING_BL5 );
-- pin22: IOPAD port map(I => gpio_o(22),O => gpio_i(22),T => gpio_t(22),C => gpio_clk,PAD => WING_BL6 );
-- pin23: IOPAD port map(I => gpio_o(23),O => gpio_i(23),T => gpio_t(23),C => gpio_clk,PAD => WING_BL7 );
-- pin24: IOPAD port map(I => gpio_o(24),O => gpio_i(24),T => gpio_t(24),C => gpio_clk,PAD => WING_BH0 );
-- pin25: IOPAD port map(I => gpio_o(25),O => gpio_i(25),T => gpio_t(25),C => gpio_clk,PAD => WING_BH1 );
-- pin26: IOPAD port map(I => gpio_o(26),O => gpio_i(26),T => gpio_t(26),C => gpio_clk,PAD => WING_BH2 );
pin27: IOPAD port map(I => gpio_o(27),O => gpio_bus_in(27),T => gpio_t(27),C => gpio_clk,PAD => WING_BH3 );
pin28: IOPAD port map(I => gpio_o(28),O => gpio_bus_in(28),T => gpio_t(28),C => gpio_clk,PAD => WING_BH4 );
pin29: IOPAD port map(I => gpio_o(29),O => gpio_bus_in(29),T => gpio_t(29),C => gpio_clk,PAD => WING_BH5 );
pin30: IOPAD port map(I => gpio_o(30),O => gpio_bus_in(30),T => gpio_t(30),C => gpio_clk,PAD => WING_BH6 );
pin31: IOPAD port map(I => gpio_o(31),O => gpio_bus_in(31),T => gpio_t(31),C => gpio_clk,PAD => WING_BH7 );
pin32: IOPAD port map(I => gpio_o(32),O => gpio_bus_in(32),T => gpio_t(32),C => gpio_clk,PAD => WING_CL0 );
pin33: IOPAD port map(I => gpio_o(33),O => gpio_bus_in(33),T => gpio_t(33),C => gpio_clk,PAD => WING_CL1 );
pin34: IOPAD port map(I => gpio_o(34),O => gpio_bus_in(34),T => gpio_t(34),C => gpio_clk,PAD => WING_CL2 );
pin35: IOPAD port map(I => gpio_o(35),O => gpio_bus_in(35),T => gpio_t(35),C => gpio_clk,PAD => WING_CL3 );
pin36: IOPAD port map(I => gpio_o(36),O => gpio_bus_in(36),T => gpio_t(36),C => gpio_clk,PAD => WING_CL4 );
pin37: IOPAD port map(I => gpio_o(37),O => gpio_bus_in(37),T => gpio_t(37),C => gpio_clk,PAD => WING_CL5 );
pin38: IOPAD port map(I => gpio_o(38),O => gpio_bus_in(38),T => gpio_t(38),C => gpio_clk,PAD => WING_CL6 );
pin39: IOPAD port map(I => gpio_o(39),O => gpio_bus_in(39),T => gpio_t(39),C => gpio_clk,PAD => WING_CL7 );
pin40: IOPAD port map(I => gpio_o(40),O => gpio_bus_in(40),T => gpio_t(40),C => gpio_clk,PAD => WING_CH0 );
pin41: IOPAD port map(I => gpio_o(41),O => gpio_bus_in(41),T => gpio_t(41),C => gpio_clk,PAD => WING_CH1 );
pin42: IOPAD port map(I => gpio_o(42),O => gpio_bus_in(42),T => gpio_t(42),C => gpio_clk,PAD => WING_CH2 );
pin43: IOPAD port map(I => gpio_o(43),O => gpio_bus_in(43),T => gpio_t(43),C => gpio_clk,PAD => WING_CH3 );
pin44: IOPAD port map(I => gpio_o(44),O => gpio_bus_in(44),T => gpio_t(44),C => gpio_clk,PAD => WING_CH4 );
pin45: IOPAD port map(I => gpio_o(45),O => gpio_bus_in(45),T => gpio_t(45),C => gpio_clk,PAD => WING_CH5 );
pin46: IOPAD port map(I => gpio_o(46),O => gpio_bus_in(46),T => gpio_t(46),C => gpio_clk,PAD => WING_CH6 );
pin47: IOPAD port map(I => gpio_o(47),O => gpio_bus_in(47),T => gpio_t(47),C => gpio_clk,PAD => WING_CH7 );
-- ospics: OPAD port map ( I => gpio_o(48), PAD => SPI_CS );
process(gpio_spp_read)
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
begin
-- gpio_spp_data <= (others => DontCareValue);
gpio_bus_in(97 downto 49) <= (others => DontCareValue);
end process;
end BEHAVIORAL;
| mit | d33fb7e50517e95e86807627668e65f0 | 0.568284 | 2.524955 | false | false | false | false |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/shadow_pixel_1/shadow_pixel_sim_netlist.vhdl | 1 | 48,783 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:31:20 2017
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/shadow_pixel_1/shadow_pixel_sim_netlist.vhdl
-- Design : shadow_pixel
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shadow_pixel_blk_mem_gen_prim_wrapper_init is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shadow_pixel_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end shadow_pixel_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of shadow_pixel_blk_mem_gen_prim_wrapper_init is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"1330133013301330133013301330133013301330133013301330133013301330",
INIT_01 => X"1330000013300000133000001330000013301330133013301330133013301330",
INIT_02 => X"1330000013300000133000001330000013300000133000001330000013300000",
INIT_03 => X"1330133013301330133013301330133013301330133013301330133013300000",
INIT_04 => X"1330133013301330133013301330133013301330133013301330133013301330",
INIT_05 => X"0000133000001330000013300000133000001330133013301330133013301330",
INIT_06 => X"0000133000001330000013300000133000001330000013300000133000001330",
INIT_07 => X"0000133000001330000013300000133000001330000013300000133000001330",
INIT_08 => X"1330133013301330133013301330133013301330133013301330133000001330",
INIT_09 => X"1330000013300000133000001330133013301330133013301330133013301330",
INIT_0A => X"1330000013300000133000001330000013300000133000001330000013300000",
INIT_0B => X"1330000013300000133000001330000013300000133000001330000013300000",
INIT_0C => X"1330000013300000133000001330000013300000133000001330000013300000",
INIT_0D => X"0000133013301330133013301330133013301330133013301330133013301330",
INIT_0E => X"0000133000001330000013300000133000001330000013300000133000001330",
INIT_0F => X"0000133000001330000013300000133000001330000013300000133000001330",
INIT_10 => X"0000133000001330000013300000133000001330000013300000133000001330",
INIT_11 => X"1330133013301330133013300000133000001330000013300000133000001330",
INIT_12 => X"1330000013300000133000001330000013300000133000001330133013301330",
INIT_13 => X"1330000013300000133000001330000013300000133000001330000013300000",
INIT_14 => X"1330000013300000133000001330000013300000133000001330000013300000",
INIT_15 => X"1330000013300000133000001330000013300000133000001330000013300000",
INIT_16 => X"0000133000001330000013300000133013301330133000001330000013300000",
INIT_17 => X"0000133000001330000013300000133000001330000013300000133000001330",
INIT_18 => X"0000133000001330000013300000133000001330000013300000133000001330",
INIT_19 => X"0000133000001330000013300000133000001330000013300000133000001330",
INIT_1A => X"1330133000001330000013300000133000001330000013300000133000001330",
INIT_1B => X"1330000013300000133000001330000013300000133000001330000013300000",
INIT_1C => X"1330000013300000133000001330000013300000133000001330000013300000",
INIT_1D => X"1330000013300000133000001330000013300000133000001330000013300000",
INIT_1E => X"1330000013300000133000001330000013300000133000001330000013300000",
INIT_1F => X"0000133000001330000013300000133013300000133000001330000013300000",
INIT_20 => X"0000133000001330000013300000133000001330000013300000133000001330",
INIT_21 => X"0000133000001330000013300000133000001330000013300000133000001330",
INIT_22 => X"0000133000001330000013300000133000001330000013300000133000001330",
INIT_23 => X"0000133000001330000013300000133000001330000013300000133000001330",
INIT_24 => X"1330000013300000133000001330000013300000133000001330000013300000",
INIT_25 => X"1330000013300000133000001330000013300000133000001330000013300000",
INIT_26 => X"1330000013300000133000001330000013300000133000001330000013300000",
INIT_27 => X"1330000013300000133000001330000013300000133000001330000013300000",
INIT_28 => X"0000133000001330000013300000133013300000133000001330000013300000",
INIT_29 => X"0000133000001330000013300000133000001330000013300000133000001330",
INIT_2A => X"0000133000001330000013300000133000001330000013300000133000001330",
INIT_2B => X"0000133000001330000013300000133000001330000013300000133000001330",
INIT_2C => X"1330133000001330000013300000133000001330000013300000133000001330",
INIT_2D => X"1330000013300000133000001330000013300000133000001330133013301330",
INIT_2E => X"1330000013300000133000001330000013300000133000001330000013300000",
INIT_2F => X"1330000013300000133000001330000013300000133000001330000013300000",
INIT_30 => X"1330000013300000133000001330000013300000133000001330000013300000",
INIT_31 => X"0000133000001330133013301330133013301330133000001330000013300000",
INIT_32 => X"0000133000001330000013300000133000001330000013300000133000001330",
INIT_33 => X"0000133000001330000013300000133000001330000013300000133000001330",
INIT_34 => X"0000133000001330000013300000133000001330000013300000133000001330",
INIT_35 => X"1330133013301330133013300000133000001330000013300000133000001330",
INIT_36 => X"1330000013300000133000001330133013301330133013301330133013301330",
INIT_37 => X"1330000013300000133000001330000013300000133000001330000013300000",
INIT_38 => X"1330000013300000133000001330000013300000133000001330000013300000",
INIT_39 => X"1330000013300000133000001330000013300000133000001330000013300000",
INIT_3A => X"1330133013301330133013301330133013301330133013301330133013301330",
INIT_3B => X"0000133000001330000013300000133000001330133013301330133013301330",
INIT_3C => X"0000133000001330000013300000133000001330000013300000133000001330",
INIT_3D => X"0000133000001330000013300000133000001330000013300000133000001330",
INIT_3E => X"1330133013301330133013301330133013301330133013301330133000001330",
INIT_3F => X"1330133013301330133013301330133013301330133013301330133013301330",
INIT_40 => X"1330000013300000133000001330000013301330133013301330133013301330",
INIT_41 => X"1330000013300000133000001330000013300000133000001330000013300000",
INIT_42 => X"1330133013301330133013301330133013301330133013301330133013300000",
INIT_43 => X"0000000000000000000000000000000013301330133013301330133013301330",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 18,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 18
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 4) => addra(10 downto 0),
ADDRARDADDR(3 downto 0) => B"1111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 14) => B"000000000000000000",
DIADI(13 downto 8) => dina(11 downto 6),
DIADI(7 downto 6) => B"00",
DIADI(5 downto 0) => dina(5 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 16) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 16),
DOADO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37\,
DOADO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38\,
DOADO(13 downto 8) => douta(11 downto 6),
DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\,
DOADO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46\,
DOADO(5 downto 0) => douta(5 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 2),
DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87\,
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shadow_pixel_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shadow_pixel_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end shadow_pixel_blk_mem_gen_prim_width;
architecture STRUCTURE of shadow_pixel_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.shadow_pixel_blk_mem_gen_prim_wrapper_init
port map (
addra(10 downto 0) => addra(10 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shadow_pixel_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shadow_pixel_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end shadow_pixel_blk_mem_gen_generic_cstr;
architecture STRUCTURE of shadow_pixel_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.shadow_pixel_blk_mem_gen_prim_width
port map (
addra(10 downto 0) => addra(10 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shadow_pixel_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shadow_pixel_blk_mem_gen_top : entity is "blk_mem_gen_top";
end shadow_pixel_blk_mem_gen_top;
architecture STRUCTURE of shadow_pixel_blk_mem_gen_top is
begin
\valid.cstr\: entity work.shadow_pixel_blk_mem_gen_generic_cstr
port map (
addra(10 downto 0) => addra(10 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shadow_pixel_blk_mem_gen_v8_3_5_synth is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shadow_pixel_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth";
end shadow_pixel_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of shadow_pixel_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.shadow_pixel_blk_mem_gen_top
port map (
addra(10 downto 0) => addra(10 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shadow_pixel_blk_mem_gen_v8_3_5 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 10 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 11 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 11 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 10 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 10 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 11;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 11;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of shadow_pixel_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of shadow_pixel_blk_mem_gen_v8_3_5 : entity is "1";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of shadow_pixel_blk_mem_gen_v8_3_5 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of shadow_pixel_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of shadow_pixel_blk_mem_gen_v8_3_5 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of shadow_pixel_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 2.5913 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of shadow_pixel_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of shadow_pixel_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of shadow_pixel_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of shadow_pixel_blk_mem_gen_v8_3_5 : entity is "shadow_pixel.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of shadow_pixel_blk_mem_gen_v8_3_5 : entity is "shadow_pixel.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 1080;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 1080;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of shadow_pixel_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of shadow_pixel_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of shadow_pixel_blk_mem_gen_v8_3_5 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 1080;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 1080;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of shadow_pixel_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of shadow_pixel_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of shadow_pixel_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of shadow_pixel_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shadow_pixel_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of shadow_pixel_blk_mem_gen_v8_3_5 : entity is "yes";
end shadow_pixel_blk_mem_gen_v8_3_5;
architecture STRUCTURE of shadow_pixel_blk_mem_gen_v8_3_5 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(11) <= \<const0>\;
doutb(10) <= \<const0>\;
doutb(9) <= \<const0>\;
doutb(8) <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.shadow_pixel_blk_mem_gen_v8_3_5_synth
port map (
addra(10 downto 0) => addra(10 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shadow_pixel is
port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of shadow_pixel : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of shadow_pixel : entity is "shadow_pixel,blk_mem_gen_v8_3_5,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of shadow_pixel : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of shadow_pixel : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4";
end shadow_pixel;
architecture STRUCTURE of shadow_pixel is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 11;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 11;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "1";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 2.5913 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "shadow_pixel.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "shadow_pixel.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 1080;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 1080;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 1080;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 1080;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.shadow_pixel_blk_mem_gen_v8_3_5
port map (
addra(10 downto 0) => addra(10 downto 0),
addrb(10 downto 0) => B"00000000000",
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(11 downto 0) => dina(11 downto 0),
dinb(11 downto 0) => B"000000000000",
douta(11 downto 0) => douta(11 downto 0),
doutb(11 downto 0) => NLW_U0_doutb_UNCONNECTED(11 downto 0),
eccpipece => '0',
ena => '0',
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(10 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(10 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(10 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(10 downto 0),
s_axi_rdata(11 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(11 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(11 downto 0) => B"000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
| gpl-3.0 | 2e0d8ef85e8c5dc9b0c910471140c17d | 0.706107 | 3.366434 | false | false | false | false |
Oblomov/pocl | examples/accel/rtl/vhdl/fu_aql_minimal.vhdl | 2 | 3,905 | -- Copyright (c) 2017 Tampere University of Technology.
--
-- This file is part of TTA-Based Codesign Environment (TCE).
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
-------------------------------------------------------------------------------
-- Title : LSU for AlmaIF Integrator
-- Project : Almarvi
-------------------------------------------------------------------------------
-- File : fu_lsu_32b.vhdl
-- Author : Kati Tervo
-- Company :
-- Created : 2019-05-28
-- Last update: 2019-05-28
-- Platform :
-------------------------------------------------------------------------------
-- Description: 32 bit wide LSU with parametric endianness
-- External ports:
-- | Signal | Comment
-- ---------------------------------------------------------------------------
-- | read_idx_out | Read index from the FU to the debug interface
-- ---------------------------------------------------------------------------
--
-- Revisions :
-- Date Version Author Description
-- 2019-05-28 1.0 katte Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity fu_aql_minimal is
port(
clk : in std_logic;
rstx : in std_logic;
glock : in std_logic;
-- External signals
read_idx_out : out std_logic_vector(64-1 downto 0);
read_idx_clear_in : in std_logic_vector(0 downto 0);
-- Architectural ports
t1_data_in : in std_logic_vector(32-1 downto 0);
t1_load_in : in std_logic;
t1_opcode_in : in std_logic_vector(0 downto 0);
r1_data_out : out std_logic_vector(32-1 downto 0)
);
end fu_aql_minimal;
architecture rtl of fu_aql_minimal is
constant OPC_GET_READ_IDX_LOW : std_logic_vector(t1_opcode_in'range) := "0";
constant OPC_INC_READ_IDX : std_logic_vector(t1_opcode_in'range) := "1";
signal read_idx_r : std_logic_vector(read_idx_out'range);
signal result_r : std_logic_vector(32 - 1 downto 0);
begin
read_idx_out <= read_idx_r;
r1_data_out <= result_r;
operation_logic : process(clk, rstx)
begin
if rstx = '0' then
read_idx_r <= (others => '0');
result_r <= (others => '0');
elsif rising_edge(clk) then
if read_idx_clear_in = "1" then
read_idx_r <= (others => '0');
end if;
if glock = '0' then
if t1_load_in = '1' then
case t1_opcode_in is
when OPC_GET_READ_IDX_LOW =>
result_r <= read_idx_r(result_r'range);
when others => -- Increment
read_idx_r <= std_logic_vector(unsigned(read_idx_r)
+ unsigned(t1_data_in));
end case;
end if;
end if;
end if;
end process operation_logic;
end rtl;
| mit | a9330b98b9fb4eb77a95fce071ed887c | 0.559283 | 3.928571 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/waveform_gen.vhd | 13 | 4,463 | ----------------------------------------------------------------------
-- --
-- THIS VHDL SOURCE CODE IS PROVIDED UNDER THE GNU PUBLIC LICENSE --
-- --
----------------------------------------------------------------------
-- --
-- Filename : waveform_gen.vhd --
-- --
-- Author : Simon Doherty --
-- Senior Design Consultant --
-- www.zipcores.com --
-- --
-- Date last modified : 23.10.2008 --
-- --
-- Description : NCO / Periodic Waveform Generator --
-- --
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity waveform_gen is
port (
-- system signals
clk : in std_logic;
reset : in std_logic;
-- NCO frequency control
phase_inc : in std_logic_vector(31 downto 0);
-- Output waveforms
sin_out : out std_logic_vector(11 downto 0);
cos_out : out std_logic_vector(11 downto 0);
squ_out : out std_logic_vector(11 downto 0);
saw_out : out std_logic_vector(11 downto 0) );
end entity;
architecture rtl of waveform_gen is
component sincos_lut
port (
clk : in std_logic;
addr : in std_logic_vector(11 downto 0);
sin_out : out std_logic_vector(11 downto 0);
cos_out : out std_logic_vector(11 downto 0));
end component;
signal phase_acc : std_logic_vector(31 downto 0);
signal lut_addr : std_logic_vector(11 downto 0);
signal lut_addr_reg : std_logic_vector(11 downto 0);
signal sin_out_reg : std_logic_vector(11 downto 0);
begin
--------------------------------------------------------------------------
-- Phase accumulator increments by 'phase_inc' every clock cycle --
-- Output frequency determined by formula: Phase_inc = (Fout/Fclk)*2^32 --
-- E.g. Fout = 36MHz, Fclk = 100MHz, Phase_inc = 36*2^32/100 --
-- Frequency resolution is 100MHz/2^32 = 0.00233Hz --
--------------------------------------------------------------------------
phase_acc_reg: process(clk, reset)
begin
if reset = '0' then
phase_acc <= (others => '0');
elsif clk'event and clk = '1' then
phase_acc <= unsigned(phase_acc) + unsigned(phase_inc);
-- sin_out <= signed(sin_out_reg) + 2047; --Modified to make it unsigned - jpg 10/6/2011
end if;
end process phase_acc_reg;
---------------------------------------------------------------------
-- use top 12-bits of phase accumulator to address the SIN/COS LUT --
---------------------------------------------------------------------
lut_addr <= phase_acc(31 downto 20);
----------------------------------------------------------------------
-- SIN/COS LUT is 4096 by 12-bit ROM --
-- 12-bit output allows sin/cos amplitudes between 2047 and -2047 --
-- (-2048 not used to keep the output signal perfectly symmetrical) --
-- Phase resolution is 2Pi/4096 = 0.088 degrees --
----------------------------------------------------------------------
lut: sincos_lut
port map (
clk => clk,
addr => lut_addr,
sin_out => sin_out,
cos_out => cos_out );
---------------------------------
-- Hide the latency of the LUT --
---------------------------------
delay_regs: process(clk)
begin
if clk'event and clk = '1' then
lut_addr_reg <= lut_addr;
end if;
end process delay_regs;
---------------------------------------------
-- Square output is msb of the accumulator --
---------------------------------------------
squ_out <= "011111111111" when lut_addr_reg(11) = '1' else "100000000000";
-------------------------------------------------------
-- Sawtooth output is top 12-bits of the accumulator --
-------------------------------------------------------
saw_out <= lut_addr_reg;
end rtl; | mit | 7bd98a8d45e28f49b7f38ed40bd85472 | 0.398835 | 4.673298 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Benchy/muldex.vhd | 13 | 5,375 | ----------------------------------------------------------------------------------
-- muldex.vhd
--
-- Copyright (C) 2011 Kinsa
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, data_wr to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Performs dynamic sample depth.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity muldex is
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (32 downto 0);
data_out : out std_logic_vector (32 downto 0);
data_rd : in std_logic;
data_wr : in std_logic;
mem_inp : in std_logic_vector (35 downto 0);
mem_out : out std_logic_vector (35 downto 0);
mem_rd : out std_logic;
mem_wr : out std_logic;
data_size : in std_logic_vector(1 downto 0);
rdstate : in std_logic;
data_ready : out std_logic
);
end muldex;
architecture behavioral of muldex is
component muldex_16
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (15 downto 0);
data_out : out std_logic_vector (15 downto 0);
data_wr : in std_logic;
data_rd : in std_logic;
mem_inp : in std_logic_vector (33 downto 0);
mem_out : out std_logic_vector (33 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
rle_in : in std_logic;
rle_out : out std_logic
);
end component;
component muldex_8
port(
clock : in std_logic;
reset : in std_logic;
data_inp : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (7 downto 0);
data_wr : in std_logic;
data_rd : in std_logic;
mem_inp : in std_logic_vector (35 downto 0);
mem_out : out std_logic_vector (35 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
rle_in : in std_logic;
rle_out : out std_logic
);
end component;
signal mem_wr_8, mem_rd_8, mem_wr_16, mem_rd_16, rle_in : std_logic;
signal data_out_8 : std_logic_vector (7 downto 0);
signal data_out_16 : std_logic_vector (15 downto 0);
signal mem_out_8 : std_logic_vector (35 downto 0);
signal mem_out_16 : std_logic_vector (33 downto 0);
signal rle_out_8, rle_out_16 : std_logic;
signal data_out_i : std_logic_vector (32 downto 0);
signal mem_wr_i, mem_rd_i : std_logic;
begin
-- generate data_ready after 3 clk cycles from data_rd
output_block: block
signal a : std_logic_vector (2 downto 0);
begin
process(clock)
begin
if rising_edge(clock) then
a <= a(1 downto 0) & data_rd;
data_ready <= a(2);
if a(2) = '1' then
data_out <= data_out_i;
end if;
end if;
end process;
end block;
-- generate extra mem_rd pulse when there is a previous mem_wr pulse
sync_mem_block: block
signal a, b : std_logic;
begin
mem_rd <= mem_rd_i or (not mem_wr_i and b) ;
mem_wr <= mem_wr_i;
process(clock)
begin
if rising_edge(clock) then
a <= rdstate;
-- check for rdstate rising edge
if a = '0' and rdstate = '1' then
b <= '1';
else
--extend only when dynamic sample depth is enabled
if b = '1' and (mem_wr_i = '1' or (mem_rd_i ='1' and data_size /= "00")) then
b <= '1';
else
b <= '0';
end if;
end if;
end if;
end process;
end block;
mem_out <=
mem_out_8 when data_size = "01" else
"00" & mem_out_16 when data_size = "10" else
"000" & data_inp when data_size = "00" else
(others => 'X');
mem_rd_i <=
mem_rd_8 when data_size = "01" else
mem_rd_16 when data_size = "10" else
data_rd when data_size = "00" else
'X';
mem_wr_i <=
mem_wr_8 when data_size = "01" else
mem_wr_16 when data_size = "10" else
data_wr when data_size = "00" else
'X';
data_out_i <=
rle_out_8 & x"000000" & data_out_8 when data_size = "01" else
rle_out_16 & x"0000" & data_out_16 when data_size = "10" else
mem_inp(32 downto 0) when data_size = "00" else
(others => 'X');
rle_in <= data_inp(32);
Inst_m16: muldex_16
port map(
clock => clock,
reset => reset,
data_inp => data_inp(15 downto 0),
data_out => data_out_16,
data_wr => data_wr,
data_rd => data_rd,
mem_inp => mem_inp(33 downto 0),
mem_out => mem_out_16,
mem_wr => mem_wr_16,
mem_rd => mem_rd_16,
rle_in => rle_in,
rle_out => rle_out_16
);
Inst_m8: muldex_8
port map(
clock => clock,
reset => reset,
data_inp => data_inp(7 downto 0),
data_out => data_out_8,
data_wr => data_wr,
data_rd => data_rd,
mem_inp => mem_inp,
mem_out => mem_out_8,
mem_wr => mem_wr_8,
mem_rd => mem_rd_8,
rle_in => rle_in,
rle_out => rle_out_8
);
end behavioral;
| mit | 0f0a0d2a59887f78158be8ec33217b3a | 0.603163 | 2.800938 | false | false | false | false |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/bg_pole/synth/bg_pole.vhd | 1 | 14,299 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY bg_pole IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END bg_pole;
ARCHITECTURE bg_pole_arch OF bg_pole IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bg_pole_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF bg_pole_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF bg_pole_arch : ARCHITECTURE IS "bg_pole,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF bg_pole_arch: ARCHITECTURE IS "bg_pole,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=bg_pole.mif" &
",C_INIT_FILE=bg_pole.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=12,C_READ_WIDTH_A=12,C_WRITE_DEPTH_A=104,C_READ_DEPTH_A=104,C_ADDRA_WIDTH=7,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=12,C_READ_WIDTH_B=12,C_WRITE_DEPTH_B=10" &
"4,C_READ_DEPTH_B=104,C_ADDRB_WIDTH=7,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_R" &
"ANGE=0,C_COUNT_36K_BRAM=0,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.7064499999999998 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "bg_pole.mif",
C_INIT_FILE => "bg_pole.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 12,
C_READ_WIDTH_A => 12,
C_WRITE_DEPTH_A => 104,
C_READ_DEPTH_A => 104,
C_ADDRA_WIDTH => 7,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 12,
C_READ_WIDTH_B => 12,
C_WRITE_DEPTH_B => 104,
C_READ_DEPTH_B => 104,
C_ADDRB_WIDTH => 7,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "0",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.7064499999999998 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 7)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END bg_pole_arch;
| gpl-3.0 | e6194d1eae9707aa1cae14d09d4e6ce6 | 0.624519 | 3.005886 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Benchy/trigger.vhd | 13 | 3,583 | ----------------------------------------------------------------------------------
-- trigger.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Complex 4 stage 32 channel trigger.
--
-- All commands are passed on to the stages. This file only maintains
-- the global trigger level and it outputs the run condition if it is set
-- by any of the stages.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity trigger is
port(
la_input : in std_logic_vector (31 downto 0);
la_inputReady : in std_logic;
data : in std_logic_vector (31 downto 0);
clock : in std_logic;
reset : in std_logic;
wrMask : in std_logic_vector (3 downto 0);
wrValue : in std_logic_vector (3 downto 0);
wrConfig : in std_logic_vector (3 downto 0);
arm : in std_logic;
demuxed : in std_logic;
run : out std_logic;
ExtTriggerIn : in std_logic
);
end trigger;
architecture behavioral of trigger is
component stage
port(
la_input : in std_logic_vector(31 downto 0);
la_inputReady : in std_logic;
data : in std_logic_vector(31 downto 0);
clock : in std_logic;
reset : in std_logic;
wrMask : in std_logic;
wrValue : in std_logic;
wrConfig : in std_logic;
arm : in std_logic;
level : in std_logic_vector(1 downto 0);
demuxed : in std_logic;
run : out std_logic;
match : out std_logic
);
end component;
signal stageMatch : std_logic_vector(3 downto 0);
signal stageRun : std_logic_vector(4 downto 0);
signal levelReg : std_logic_vector(1 downto 0);
begin
--Connect ExtTriggerIn to the last stageRun
--stageRun(4) <= ExtTriggerIn; --Disable external trigger
-- create stages
stages: for i in 0 to 3 generate
Inst_stage: stage
port map(
la_input => la_input,
la_inputReady => la_inputReady,
data => data,
clock => clock,
reset => reset,
wrMask => wrMask(i),
wrValue => wrValue(i),
wrConfig => wrConfig(i),
arm => arm,
level => levelReg,
demuxed => demuxed,
run => stageRun(i),
match => stageMatch(i)
);
end generate;
-- increase level on match
process(clock, arm)
variable tmp : std_logic;
begin
if arm = '1' then
levelReg <= "00";
elsif rising_edge(clock) then
tmp := stageMatch(0);
for i in 1 to 3 loop
tmp := tmp or stageMatch(i);
end loop;
if tmp = '1' then
levelReg <= levelReg + 1;
end if;
end if;
end process;
-- if any of the stages set run, capturing starts
process(stageRun)
variable tmp : std_logic;
begin
tmp := stageRun(0);
for i in 1 to 4 loop
tmp := tmp or stageRun(i);
end loop;
run <= tmp;
end process;
end behavioral;
| mit | da5e8a1286b7835f3860d52d754cdc58 | 0.630198 | 3.402659 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/sincos_lut.vhd | 13 | 68,473 | ----------------------------------------------------------------------
-- --
-- THIS VHDL SOURCE CODE IS PROVIDED UNDER THE GNU PUBLIC LICENSE --
-- --
----------------------------------------------------------------------
-- --
-- Filename : sincos_lut.vhd --
-- --
-- Author : Simon Doherty --
-- Senior Design Consultant --
-- www.zipcores.com --
-- --
-- Date last modified : 26.05.2008 --
-- --
-- Description : 4096 x 12-bit SIN/COS Look-up table --
-- --
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sincos_lut is
port (
clk : in std_logic;
addr : in std_logic_vector(11 downto 0);
sin_out : out std_logic_vector(11 downto 0);
cos_out : out std_logic_vector(11 downto 0)
);
end entity;
architecture rtl of sincos_lut is
type rom_type is array (0 to 4095) of std_logic_vector (11 downto 0);
constant SIN_ROM : rom_type :=
(
X"000", X"003", X"006", X"009", X"00d", X"010", X"013", X"016",
X"019", X"01c", X"01f", X"023", X"026", X"029", X"02c", X"02f",
X"032", X"035", X"039", X"03c", X"03f", X"042", X"045", X"048",
X"04b", X"04e", X"052", X"055", X"058", X"05b", X"05e", X"061",
X"064", X"068", X"06b", X"06e", X"071", X"074", X"077", X"07a",
X"07e", X"081", X"084", X"087", X"08a", X"08d", X"090", X"093",
X"097", X"09a", X"09d", X"0a0", X"0a3", X"0a6", X"0a9", X"0ac",
X"0b0", X"0b3", X"0b6", X"0b9", X"0bc", X"0bf", X"0c2", X"0c6",
X"0c9", X"0cc", X"0cf", X"0d2", X"0d5", X"0d8", X"0db", X"0df",
X"0e2", X"0e5", X"0e8", X"0eb", X"0ee", X"0f1", X"0f4", X"0f7",
X"0fb", X"0fe", X"101", X"104", X"107", X"10a", X"10d", X"110",
X"113", X"117", X"11a", X"11d", X"120", X"123", X"126", X"129",
X"12c", X"12f", X"133", X"136", X"139", X"13c", X"13f", X"142",
X"145", X"148", X"14b", X"14e", X"152", X"155", X"158", X"15b",
X"15e", X"161", X"164", X"167", X"16a", X"16d", X"171", X"174",
X"177", X"17a", X"17d", X"180", X"183", X"186", X"189", X"18c",
X"18f", X"192", X"196", X"199", X"19c", X"19f", X"1a2", X"1a5",
X"1a8", X"1ab", X"1ae", X"1b1", X"1b4", X"1b7", X"1ba", X"1bd",
X"1c1", X"1c4", X"1c7", X"1ca", X"1cd", X"1d0", X"1d3", X"1d6",
X"1d9", X"1dc", X"1df", X"1e2", X"1e5", X"1e8", X"1eb", X"1ee",
X"1f1", X"1f4", X"1f7", X"1fb", X"1fe", X"201", X"204", X"207",
X"20a", X"20d", X"210", X"213", X"216", X"219", X"21c", X"21f",
X"222", X"225", X"228", X"22b", X"22e", X"231", X"234", X"237",
X"23a", X"23d", X"240", X"243", X"246", X"249", X"24c", X"24f",
X"252", X"255", X"258", X"25b", X"25e", X"261", X"264", X"267",
X"26a", X"26d", X"270", X"273", X"276", X"279", X"27c", X"27f",
X"282", X"285", X"288", X"28b", X"28e", X"291", X"294", X"297",
X"29a", X"29d", X"2a0", X"2a3", X"2a6", X"2a9", X"2ac", X"2af",
X"2b2", X"2b5", X"2b8", X"2ba", X"2bd", X"2c0", X"2c3", X"2c6",
X"2c9", X"2cc", X"2cf", X"2d2", X"2d5", X"2d8", X"2db", X"2de",
X"2e1", X"2e4", X"2e7", X"2e9", X"2ec", X"2ef", X"2f2", X"2f5",
X"2f8", X"2fb", X"2fe", X"301", X"304", X"307", X"30a", X"30c",
X"30f", X"312", X"315", X"318", X"31b", X"31e", X"321", X"324",
X"327", X"329", X"32c", X"32f", X"332", X"335", X"338", X"33b",
X"33e", X"340", X"343", X"346", X"349", X"34c", X"34f", X"352",
X"354", X"357", X"35a", X"35d", X"360", X"363", X"366", X"368",
X"36b", X"36e", X"371", X"374", X"377", X"379", X"37c", X"37f",
X"382", X"385", X"387", X"38a", X"38d", X"390", X"393", X"396",
X"398", X"39b", X"39e", X"3a1", X"3a4", X"3a6", X"3a9", X"3ac",
X"3af", X"3b2", X"3b4", X"3b7", X"3ba", X"3bd", X"3bf", X"3c2",
X"3c5", X"3c8", X"3ca", X"3cd", X"3d0", X"3d3", X"3d6", X"3d8",
X"3db", X"3de", X"3e1", X"3e3", X"3e6", X"3e9", X"3eb", X"3ee",
X"3f1", X"3f4", X"3f6", X"3f9", X"3fc", X"3ff", X"401", X"404",
X"407", X"409", X"40c", X"40f", X"412", X"414", X"417", X"41a",
X"41c", X"41f", X"422", X"424", X"427", X"42a", X"42c", X"42f",
X"432", X"435", X"437", X"43a", X"43d", X"43f", X"442", X"444",
X"447", X"44a", X"44c", X"44f", X"452", X"454", X"457", X"45a",
X"45c", X"45f", X"462", X"464", X"467", X"469", X"46c", X"46f",
X"471", X"474", X"476", X"479", X"47c", X"47e", X"481", X"483",
X"486", X"489", X"48b", X"48e", X"490", X"493", X"496", X"498",
X"49b", X"49d", X"4a0", X"4a2", X"4a5", X"4a7", X"4aa", X"4ad",
X"4af", X"4b2", X"4b4", X"4b7", X"4b9", X"4bc", X"4be", X"4c1",
X"4c3", X"4c6", X"4c8", X"4cb", X"4cd", X"4d0", X"4d2", X"4d5",
X"4d7", X"4da", X"4dc", X"4df", X"4e1", X"4e4", X"4e6", X"4e9",
X"4eb", X"4ee", X"4f0", X"4f3", X"4f5", X"4f8", X"4fa", X"4fd",
X"4ff", X"502", X"504", X"506", X"509", X"50b", X"50e", X"510",
X"513", X"515", X"517", X"51a", X"51c", X"51f", X"521", X"524",
X"526", X"528", X"52b", X"52d", X"530", X"532", X"534", X"537",
X"539", X"53b", X"53e", X"540", X"543", X"545", X"547", X"54a",
X"54c", X"54e", X"551", X"553", X"555", X"558", X"55a", X"55c",
X"55f", X"561", X"563", X"566", X"568", X"56a", X"56d", X"56f",
X"571", X"573", X"576", X"578", X"57a", X"57d", X"57f", X"581",
X"583", X"586", X"588", X"58a", X"58d", X"58f", X"591", X"593",
X"596", X"598", X"59a", X"59c", X"59f", X"5a1", X"5a3", X"5a5",
X"5a7", X"5aa", X"5ac", X"5ae", X"5b0", X"5b3", X"5b5", X"5b7",
X"5b9", X"5bb", X"5bd", X"5c0", X"5c2", X"5c4", X"5c6", X"5c8",
X"5cb", X"5cd", X"5cf", X"5d1", X"5d3", X"5d5", X"5d7", X"5da",
X"5dc", X"5de", X"5e0", X"5e2", X"5e4", X"5e6", X"5e9", X"5eb",
X"5ed", X"5ef", X"5f1", X"5f3", X"5f5", X"5f7", X"5f9", X"5fb",
X"5fd", X"600", X"602", X"604", X"606", X"608", X"60a", X"60c",
X"60e", X"610", X"612", X"614", X"616", X"618", X"61a", X"61c",
X"61e", X"620", X"622", X"624", X"626", X"628", X"62a", X"62c",
X"62e", X"630", X"632", X"634", X"636", X"638", X"63a", X"63c",
X"63e", X"640", X"642", X"644", X"646", X"648", X"64a", X"64c",
X"64e", X"650", X"652", X"654", X"655", X"657", X"659", X"65b",
X"65d", X"65f", X"661", X"663", X"665", X"667", X"668", X"66a",
X"66c", X"66e", X"670", X"672", X"674", X"675", X"677", X"679",
X"67b", X"67d", X"67f", X"681", X"682", X"684", X"686", X"688",
X"68a", X"68b", X"68d", X"68f", X"691", X"693", X"694", X"696",
X"698", X"69a", X"69b", X"69d", X"69f", X"6a1", X"6a3", X"6a4",
X"6a6", X"6a8", X"6a9", X"6ab", X"6ad", X"6af", X"6b0", X"6b2",
X"6b4", X"6b6", X"6b7", X"6b9", X"6bb", X"6bc", X"6be", X"6c0",
X"6c1", X"6c3", X"6c5", X"6c6", X"6c8", X"6ca", X"6cb", X"6cd",
X"6cf", X"6d0", X"6d2", X"6d4", X"6d5", X"6d7", X"6d9", X"6da",
X"6dc", X"6dd", X"6df", X"6e1", X"6e2", X"6e4", X"6e5", X"6e7",
X"6e9", X"6ea", X"6ec", X"6ed", X"6ef", X"6f0", X"6f2", X"6f4",
X"6f5", X"6f7", X"6f8", X"6fa", X"6fb", X"6fd", X"6fe", X"700",
X"701", X"703", X"704", X"706", X"707", X"709", X"70a", X"70c",
X"70d", X"70f", X"710", X"712", X"713", X"715", X"716", X"718",
X"719", X"71a", X"71c", X"71d", X"71f", X"720", X"722", X"723",
X"724", X"726", X"727", X"729", X"72a", X"72b", X"72d", X"72e",
X"730", X"731", X"732", X"734", X"735", X"736", X"738", X"739",
X"73a", X"73c", X"73d", X"73e", X"740", X"741", X"742", X"744",
X"745", X"746", X"748", X"749", X"74a", X"74c", X"74d", X"74e",
X"74f", X"751", X"752", X"753", X"754", X"756", X"757", X"758",
X"759", X"75b", X"75c", X"75d", X"75e", X"760", X"761", X"762",
X"763", X"764", X"766", X"767", X"768", X"769", X"76a", X"76b",
X"76d", X"76e", X"76f", X"770", X"771", X"772", X"774", X"775",
X"776", X"777", X"778", X"779", X"77a", X"77b", X"77d", X"77e",
X"77f", X"780", X"781", X"782", X"783", X"784", X"785", X"786",
X"787", X"788", X"789", X"78a", X"78c", X"78d", X"78e", X"78f",
X"790", X"791", X"792", X"793", X"794", X"795", X"796", X"797",
X"798", X"799", X"79a", X"79b", X"79c", X"79d", X"79e", X"79e",
X"79f", X"7a0", X"7a1", X"7a2", X"7a3", X"7a4", X"7a5", X"7a6",
X"7a7", X"7a8", X"7a9", X"7aa", X"7aa", X"7ab", X"7ac", X"7ad",
X"7ae", X"7af", X"7b0", X"7b1", X"7b1", X"7b2", X"7b3", X"7b4",
X"7b5", X"7b6", X"7b7", X"7b7", X"7b8", X"7b9", X"7ba", X"7bb",
X"7bb", X"7bc", X"7bd", X"7be", X"7bf", X"7bf", X"7c0", X"7c1",
X"7c2", X"7c2", X"7c3", X"7c4", X"7c5", X"7c5", X"7c6", X"7c7",
X"7c8", X"7c8", X"7c9", X"7ca", X"7ca", X"7cb", X"7cc", X"7cd",
X"7cd", X"7ce", X"7cf", X"7cf", X"7d0", X"7d1", X"7d1", X"7d2",
X"7d3", X"7d3", X"7d4", X"7d5", X"7d5", X"7d6", X"7d6", X"7d7",
X"7d8", X"7d8", X"7d9", X"7d9", X"7da", X"7db", X"7db", X"7dc",
X"7dc", X"7dd", X"7de", X"7de", X"7df", X"7df", X"7e0", X"7e0",
X"7e1", X"7e1", X"7e2", X"7e2", X"7e3", X"7e3", X"7e4", X"7e5",
X"7e5", X"7e6", X"7e6", X"7e6", X"7e7", X"7e7", X"7e8", X"7e8",
X"7e9", X"7e9", X"7ea", X"7ea", X"7eb", X"7eb", X"7ec", X"7ec",
X"7ec", X"7ed", X"7ed", X"7ee", X"7ee", X"7ee", X"7ef", X"7ef",
X"7f0", X"7f0", X"7f0", X"7f1", X"7f1", X"7f1", X"7f2", X"7f2",
X"7f3", X"7f3", X"7f3", X"7f4", X"7f4", X"7f4", X"7f5", X"7f5",
X"7f5", X"7f5", X"7f6", X"7f6", X"7f6", X"7f7", X"7f7", X"7f7",
X"7f7", X"7f8", X"7f8", X"7f8", X"7f8", X"7f9", X"7f9", X"7f9",
X"7f9", X"7fa", X"7fa", X"7fa", X"7fa", X"7fb", X"7fb", X"7fb",
X"7fb", X"7fb", X"7fc", X"7fc", X"7fc", X"7fc", X"7fc", X"7fc",
X"7fd", X"7fd", X"7fd", X"7fd", X"7fd", X"7fd", X"7fd", X"7fd",
X"7fe", X"7fe", X"7fe", X"7fe", X"7fe", X"7fe", X"7fe", X"7fe",
X"7fe", X"7fe", X"7ff", X"7ff", X"7ff", X"7ff", X"7ff", X"7ff",
X"7ff", X"7ff", X"7ff", X"7ff", X"7ff", X"7ff", X"7ff", X"7ff",
X"7ff", X"7ff", X"7ff", X"7ff", X"7ff", X"7ff", X"7ff", X"7ff",
X"7ff", X"7ff", X"7ff", X"7ff", X"7ff", X"7ff", X"7ff", X"7fe",
X"7fe", X"7fe", X"7fe", X"7fe", X"7fe", X"7fe", X"7fe", X"7fe",
X"7fe", X"7fd", X"7fd", X"7fd", X"7fd", X"7fd", X"7fd", X"7fd",
X"7fd", X"7fc", X"7fc", X"7fc", X"7fc", X"7fc", X"7fc", X"7fb",
X"7fb", X"7fb", X"7fb", X"7fb", X"7fa", X"7fa", X"7fa", X"7fa",
X"7f9", X"7f9", X"7f9", X"7f9", X"7f8", X"7f8", X"7f8", X"7f8",
X"7f7", X"7f7", X"7f7", X"7f7", X"7f6", X"7f6", X"7f6", X"7f5",
X"7f5", X"7f5", X"7f5", X"7f4", X"7f4", X"7f4", X"7f3", X"7f3",
X"7f3", X"7f2", X"7f2", X"7f1", X"7f1", X"7f1", X"7f0", X"7f0",
X"7f0", X"7ef", X"7ef", X"7ee", X"7ee", X"7ee", X"7ed", X"7ed",
X"7ec", X"7ec", X"7ec", X"7eb", X"7eb", X"7ea", X"7ea", X"7e9",
X"7e9", X"7e8", X"7e8", X"7e7", X"7e7", X"7e6", X"7e6", X"7e6",
X"7e5", X"7e5", X"7e4", X"7e3", X"7e3", X"7e2", X"7e2", X"7e1",
X"7e1", X"7e0", X"7e0", X"7df", X"7df", X"7de", X"7de", X"7dd",
X"7dc", X"7dc", X"7db", X"7db", X"7da", X"7d9", X"7d9", X"7d8",
X"7d8", X"7d7", X"7d6", X"7d6", X"7d5", X"7d5", X"7d4", X"7d3",
X"7d3", X"7d2", X"7d1", X"7d1", X"7d0", X"7cf", X"7cf", X"7ce",
X"7cd", X"7cd", X"7cc", X"7cb", X"7ca", X"7ca", X"7c9", X"7c8",
X"7c8", X"7c7", X"7c6", X"7c5", X"7c5", X"7c4", X"7c3", X"7c2",
X"7c2", X"7c1", X"7c0", X"7bf", X"7bf", X"7be", X"7bd", X"7bc",
X"7bb", X"7bb", X"7ba", X"7b9", X"7b8", X"7b7", X"7b7", X"7b6",
X"7b5", X"7b4", X"7b3", X"7b2", X"7b1", X"7b1", X"7b0", X"7af",
X"7ae", X"7ad", X"7ac", X"7ab", X"7aa", X"7aa", X"7a9", X"7a8",
X"7a7", X"7a6", X"7a5", X"7a4", X"7a3", X"7a2", X"7a1", X"7a0",
X"79f", X"79e", X"79e", X"79d", X"79c", X"79b", X"79a", X"799",
X"798", X"797", X"796", X"795", X"794", X"793", X"792", X"791",
X"790", X"78f", X"78e", X"78d", X"78c", X"78a", X"789", X"788",
X"787", X"786", X"785", X"784", X"783", X"782", X"781", X"780",
X"77f", X"77e", X"77d", X"77b", X"77a", X"779", X"778", X"777",
X"776", X"775", X"774", X"772", X"771", X"770", X"76f", X"76e",
X"76d", X"76b", X"76a", X"769", X"768", X"767", X"766", X"764",
X"763", X"762", X"761", X"760", X"75e", X"75d", X"75c", X"75b",
X"759", X"758", X"757", X"756", X"754", X"753", X"752", X"751",
X"74f", X"74e", X"74d", X"74c", X"74a", X"749", X"748", X"746",
X"745", X"744", X"742", X"741", X"740", X"73e", X"73d", X"73c",
X"73a", X"739", X"738", X"736", X"735", X"734", X"732", X"731",
X"730", X"72e", X"72d", X"72b", X"72a", X"729", X"727", X"726",
X"724", X"723", X"722", X"720", X"71f", X"71d", X"71c", X"71a",
X"719", X"718", X"716", X"715", X"713", X"712", X"710", X"70f",
X"70d", X"70c", X"70a", X"709", X"707", X"706", X"704", X"703",
X"701", X"700", X"6fe", X"6fd", X"6fb", X"6fa", X"6f8", X"6f7",
X"6f5", X"6f4", X"6f2", X"6f0", X"6ef", X"6ed", X"6ec", X"6ea",
X"6e9", X"6e7", X"6e5", X"6e4", X"6e2", X"6e1", X"6df", X"6dd",
X"6dc", X"6da", X"6d9", X"6d7", X"6d5", X"6d4", X"6d2", X"6d0",
X"6cf", X"6cd", X"6cb", X"6ca", X"6c8", X"6c6", X"6c5", X"6c3",
X"6c1", X"6c0", X"6be", X"6bc", X"6bb", X"6b9", X"6b7", X"6b6",
X"6b4", X"6b2", X"6b0", X"6af", X"6ad", X"6ab", X"6a9", X"6a8",
X"6a6", X"6a4", X"6a3", X"6a1", X"69f", X"69d", X"69b", X"69a",
X"698", X"696", X"694", X"693", X"691", X"68f", X"68d", X"68b",
X"68a", X"688", X"686", X"684", X"682", X"681", X"67f", X"67d",
X"67b", X"679", X"677", X"675", X"674", X"672", X"670", X"66e",
X"66c", X"66a", X"668", X"667", X"665", X"663", X"661", X"65f",
X"65d", X"65b", X"659", X"657", X"655", X"654", X"652", X"650",
X"64e", X"64c", X"64a", X"648", X"646", X"644", X"642", X"640",
X"63e", X"63c", X"63a", X"638", X"636", X"634", X"632", X"630",
X"62e", X"62c", X"62a", X"628", X"626", X"624", X"622", X"620",
X"61e", X"61c", X"61a", X"618", X"616", X"614", X"612", X"610",
X"60e", X"60c", X"60a", X"608", X"606", X"604", X"602", X"600",
X"5fd", X"5fb", X"5f9", X"5f7", X"5f5", X"5f3", X"5f1", X"5ef",
X"5ed", X"5eb", X"5e9", X"5e6", X"5e4", X"5e2", X"5e0", X"5de",
X"5dc", X"5da", X"5d7", X"5d5", X"5d3", X"5d1", X"5cf", X"5cd",
X"5cb", X"5c8", X"5c6", X"5c4", X"5c2", X"5c0", X"5bd", X"5bb",
X"5b9", X"5b7", X"5b5", X"5b3", X"5b0", X"5ae", X"5ac", X"5aa",
X"5a7", X"5a5", X"5a3", X"5a1", X"59f", X"59c", X"59a", X"598",
X"596", X"593", X"591", X"58f", X"58d", X"58a", X"588", X"586",
X"583", X"581", X"57f", X"57d", X"57a", X"578", X"576", X"573",
X"571", X"56f", X"56d", X"56a", X"568", X"566", X"563", X"561",
X"55f", X"55c", X"55a", X"558", X"555", X"553", X"551", X"54e",
X"54c", X"54a", X"547", X"545", X"543", X"540", X"53e", X"53b",
X"539", X"537", X"534", X"532", X"530", X"52d", X"52b", X"528",
X"526", X"524", X"521", X"51f", X"51c", X"51a", X"517", X"515",
X"513", X"510", X"50e", X"50b", X"509", X"506", X"504", X"502",
X"4ff", X"4fd", X"4fa", X"4f8", X"4f5", X"4f3", X"4f0", X"4ee",
X"4eb", X"4e9", X"4e6", X"4e4", X"4e1", X"4df", X"4dc", X"4da",
X"4d7", X"4d5", X"4d2", X"4d0", X"4cd", X"4cb", X"4c8", X"4c6",
X"4c3", X"4c1", X"4be", X"4bc", X"4b9", X"4b7", X"4b4", X"4b2",
X"4af", X"4ad", X"4aa", X"4a7", X"4a5", X"4a2", X"4a0", X"49d",
X"49b", X"498", X"496", X"493", X"490", X"48e", X"48b", X"489",
X"486", X"483", X"481", X"47e", X"47c", X"479", X"476", X"474",
X"471", X"46f", X"46c", X"469", X"467", X"464", X"462", X"45f",
X"45c", X"45a", X"457", X"454", X"452", X"44f", X"44c", X"44a",
X"447", X"444", X"442", X"43f", X"43d", X"43a", X"437", X"435",
X"432", X"42f", X"42c", X"42a", X"427", X"424", X"422", X"41f",
X"41c", X"41a", X"417", X"414", X"412", X"40f", X"40c", X"409",
X"407", X"404", X"401", X"3ff", X"3fc", X"3f9", X"3f6", X"3f4",
X"3f1", X"3ee", X"3eb", X"3e9", X"3e6", X"3e3", X"3e1", X"3de",
X"3db", X"3d8", X"3d6", X"3d3", X"3d0", X"3cd", X"3ca", X"3c8",
X"3c5", X"3c2", X"3bf", X"3bd", X"3ba", X"3b7", X"3b4", X"3b2",
X"3af", X"3ac", X"3a9", X"3a6", X"3a4", X"3a1", X"39e", X"39b",
X"398", X"396", X"393", X"390", X"38d", X"38a", X"387", X"385",
X"382", X"37f", X"37c", X"379", X"377", X"374", X"371", X"36e",
X"36b", X"368", X"366", X"363", X"360", X"35d", X"35a", X"357",
X"354", X"352", X"34f", X"34c", X"349", X"346", X"343", X"340",
X"33e", X"33b", X"338", X"335", X"332", X"32f", X"32c", X"329",
X"327", X"324", X"321", X"31e", X"31b", X"318", X"315", X"312",
X"30f", X"30c", X"30a", X"307", X"304", X"301", X"2fe", X"2fb",
X"2f8", X"2f5", X"2f2", X"2ef", X"2ec", X"2e9", X"2e7", X"2e4",
X"2e1", X"2de", X"2db", X"2d8", X"2d5", X"2d2", X"2cf", X"2cc",
X"2c9", X"2c6", X"2c3", X"2c0", X"2bd", X"2ba", X"2b8", X"2b5",
X"2b2", X"2af", X"2ac", X"2a9", X"2a6", X"2a3", X"2a0", X"29d",
X"29a", X"297", X"294", X"291", X"28e", X"28b", X"288", X"285",
X"282", X"27f", X"27c", X"279", X"276", X"273", X"270", X"26d",
X"26a", X"267", X"264", X"261", X"25e", X"25b", X"258", X"255",
X"252", X"24f", X"24c", X"249", X"246", X"243", X"240", X"23d",
X"23a", X"237", X"234", X"231", X"22e", X"22b", X"228", X"225",
X"222", X"21f", X"21c", X"219", X"216", X"213", X"210", X"20d",
X"20a", X"207", X"204", X"201", X"1fe", X"1fb", X"1f7", X"1f4",
X"1f1", X"1ee", X"1eb", X"1e8", X"1e5", X"1e2", X"1df", X"1dc",
X"1d9", X"1d6", X"1d3", X"1d0", X"1cd", X"1ca", X"1c7", X"1c4",
X"1c1", X"1bd", X"1ba", X"1b7", X"1b4", X"1b1", X"1ae", X"1ab",
X"1a8", X"1a5", X"1a2", X"19f", X"19c", X"199", X"196", X"192",
X"18f", X"18c", X"189", X"186", X"183", X"180", X"17d", X"17a",
X"177", X"174", X"171", X"16d", X"16a", X"167", X"164", X"161",
X"15e", X"15b", X"158", X"155", X"152", X"14e", X"14b", X"148",
X"145", X"142", X"13f", X"13c", X"139", X"136", X"133", X"12f",
X"12c", X"129", X"126", X"123", X"120", X"11d", X"11a", X"117",
X"113", X"110", X"10d", X"10a", X"107", X"104", X"101", X"0fe",
X"0fb", X"0f7", X"0f4", X"0f1", X"0ee", X"0eb", X"0e8", X"0e5",
X"0e2", X"0df", X"0db", X"0d8", X"0d5", X"0d2", X"0cf", X"0cc",
X"0c9", X"0c6", X"0c2", X"0bf", X"0bc", X"0b9", X"0b6", X"0b3",
X"0b0", X"0ac", X"0a9", X"0a6", X"0a3", X"0a0", X"09d", X"09a",
X"097", X"093", X"090", X"08d", X"08a", X"087", X"084", X"081",
X"07e", X"07a", X"077", X"074", X"071", X"06e", X"06b", X"068",
X"064", X"061", X"05e", X"05b", X"058", X"055", X"052", X"04e",
X"04b", X"048", X"045", X"042", X"03f", X"03c", X"039", X"035",
X"032", X"02f", X"02c", X"029", X"026", X"023", X"01f", X"01c",
X"019", X"016", X"013", X"010", X"00d", X"009", X"006", X"003",
X"000", X"ffd", X"ffa", X"ff7", X"ff3", X"ff0", X"fed", X"fea",
X"fe7", X"fe4", X"fe1", X"fdd", X"fda", X"fd7", X"fd4", X"fd1",
X"fce", X"fcb", X"fc7", X"fc4", X"fc1", X"fbe", X"fbb", X"fb8",
X"fb5", X"fb2", X"fae", X"fab", X"fa8", X"fa5", X"fa2", X"f9f",
X"f9c", X"f98", X"f95", X"f92", X"f8f", X"f8c", X"f89", X"f86",
X"f82", X"f7f", X"f7c", X"f79", X"f76", X"f73", X"f70", X"f6d",
X"f69", X"f66", X"f63", X"f60", X"f5d", X"f5a", X"f57", X"f54",
X"f50", X"f4d", X"f4a", X"f47", X"f44", X"f41", X"f3e", X"f3a",
X"f37", X"f34", X"f31", X"f2e", X"f2b", X"f28", X"f25", X"f21",
X"f1e", X"f1b", X"f18", X"f15", X"f12", X"f0f", X"f0c", X"f09",
X"f05", X"f02", X"eff", X"efc", X"ef9", X"ef6", X"ef3", X"ef0",
X"eed", X"ee9", X"ee6", X"ee3", X"ee0", X"edd", X"eda", X"ed7",
X"ed4", X"ed1", X"ecd", X"eca", X"ec7", X"ec4", X"ec1", X"ebe",
X"ebb", X"eb8", X"eb5", X"eb2", X"eae", X"eab", X"ea8", X"ea5",
X"ea2", X"e9f", X"e9c", X"e99", X"e96", X"e93", X"e8f", X"e8c",
X"e89", X"e86", X"e83", X"e80", X"e7d", X"e7a", X"e77", X"e74",
X"e71", X"e6e", X"e6a", X"e67", X"e64", X"e61", X"e5e", X"e5b",
X"e58", X"e55", X"e52", X"e4f", X"e4c", X"e49", X"e46", X"e43",
X"e3f", X"e3c", X"e39", X"e36", X"e33", X"e30", X"e2d", X"e2a",
X"e27", X"e24", X"e21", X"e1e", X"e1b", X"e18", X"e15", X"e12",
X"e0f", X"e0c", X"e09", X"e05", X"e02", X"dff", X"dfc", X"df9",
X"df6", X"df3", X"df0", X"ded", X"dea", X"de7", X"de4", X"de1",
X"dde", X"ddb", X"dd8", X"dd5", X"dd2", X"dcf", X"dcc", X"dc9",
X"dc6", X"dc3", X"dc0", X"dbd", X"dba", X"db7", X"db4", X"db1",
X"dae", X"dab", X"da8", X"da5", X"da2", X"d9f", X"d9c", X"d99",
X"d96", X"d93", X"d90", X"d8d", X"d8a", X"d87", X"d84", X"d81",
X"d7e", X"d7b", X"d78", X"d75", X"d72", X"d6f", X"d6c", X"d69",
X"d66", X"d63", X"d60", X"d5d", X"d5a", X"d57", X"d54", X"d51",
X"d4e", X"d4b", X"d48", X"d46", X"d43", X"d40", X"d3d", X"d3a",
X"d37", X"d34", X"d31", X"d2e", X"d2b", X"d28", X"d25", X"d22",
X"d1f", X"d1c", X"d19", X"d17", X"d14", X"d11", X"d0e", X"d0b",
X"d08", X"d05", X"d02", X"cff", X"cfc", X"cf9", X"cf6", X"cf4",
X"cf1", X"cee", X"ceb", X"ce8", X"ce5", X"ce2", X"cdf", X"cdc",
X"cd9", X"cd7", X"cd4", X"cd1", X"cce", X"ccb", X"cc8", X"cc5",
X"cc2", X"cc0", X"cbd", X"cba", X"cb7", X"cb4", X"cb1", X"cae",
X"cac", X"ca9", X"ca6", X"ca3", X"ca0", X"c9d", X"c9a", X"c98",
X"c95", X"c92", X"c8f", X"c8c", X"c89", X"c87", X"c84", X"c81",
X"c7e", X"c7b", X"c79", X"c76", X"c73", X"c70", X"c6d", X"c6a",
X"c68", X"c65", X"c62", X"c5f", X"c5c", X"c5a", X"c57", X"c54",
X"c51", X"c4e", X"c4c", X"c49", X"c46", X"c43", X"c41", X"c3e",
X"c3b", X"c38", X"c36", X"c33", X"c30", X"c2d", X"c2a", X"c28",
X"c25", X"c22", X"c1f", X"c1d", X"c1a", X"c17", X"c15", X"c12",
X"c0f", X"c0c", X"c0a", X"c07", X"c04", X"c01", X"bff", X"bfc",
X"bf9", X"bf7", X"bf4", X"bf1", X"bee", X"bec", X"be9", X"be6",
X"be4", X"be1", X"bde", X"bdc", X"bd9", X"bd6", X"bd4", X"bd1",
X"bce", X"bcb", X"bc9", X"bc6", X"bc3", X"bc1", X"bbe", X"bbc",
X"bb9", X"bb6", X"bb4", X"bb1", X"bae", X"bac", X"ba9", X"ba6",
X"ba4", X"ba1", X"b9e", X"b9c", X"b99", X"b97", X"b94", X"b91",
X"b8f", X"b8c", X"b8a", X"b87", X"b84", X"b82", X"b7f", X"b7d",
X"b7a", X"b77", X"b75", X"b72", X"b70", X"b6d", X"b6a", X"b68",
X"b65", X"b63", X"b60", X"b5e", X"b5b", X"b59", X"b56", X"b53",
X"b51", X"b4e", X"b4c", X"b49", X"b47", X"b44", X"b42", X"b3f",
X"b3d", X"b3a", X"b38", X"b35", X"b33", X"b30", X"b2e", X"b2b",
X"b29", X"b26", X"b24", X"b21", X"b1f", X"b1c", X"b1a", X"b17",
X"b15", X"b12", X"b10", X"b0d", X"b0b", X"b08", X"b06", X"b03",
X"b01", X"afe", X"afc", X"afa", X"af7", X"af5", X"af2", X"af0",
X"aed", X"aeb", X"ae9", X"ae6", X"ae4", X"ae1", X"adf", X"adc",
X"ada", X"ad8", X"ad5", X"ad3", X"ad0", X"ace", X"acc", X"ac9",
X"ac7", X"ac5", X"ac2", X"ac0", X"abd", X"abb", X"ab9", X"ab6",
X"ab4", X"ab2", X"aaf", X"aad", X"aab", X"aa8", X"aa6", X"aa4",
X"aa1", X"a9f", X"a9d", X"a9a", X"a98", X"a96", X"a93", X"a91",
X"a8f", X"a8d", X"a8a", X"a88", X"a86", X"a83", X"a81", X"a7f",
X"a7d", X"a7a", X"a78", X"a76", X"a73", X"a71", X"a6f", X"a6d",
X"a6a", X"a68", X"a66", X"a64", X"a61", X"a5f", X"a5d", X"a5b",
X"a59", X"a56", X"a54", X"a52", X"a50", X"a4d", X"a4b", X"a49",
X"a47", X"a45", X"a43", X"a40", X"a3e", X"a3c", X"a3a", X"a38",
X"a35", X"a33", X"a31", X"a2f", X"a2d", X"a2b", X"a29", X"a26",
X"a24", X"a22", X"a20", X"a1e", X"a1c", X"a1a", X"a17", X"a15",
X"a13", X"a11", X"a0f", X"a0d", X"a0b", X"a09", X"a07", X"a05",
X"a03", X"a00", X"9fe", X"9fc", X"9fa", X"9f8", X"9f6", X"9f4",
X"9f2", X"9f0", X"9ee", X"9ec", X"9ea", X"9e8", X"9e6", X"9e4",
X"9e2", X"9e0", X"9de", X"9dc", X"9da", X"9d8", X"9d6", X"9d4",
X"9d2", X"9d0", X"9ce", X"9cc", X"9ca", X"9c8", X"9c6", X"9c4",
X"9c2", X"9c0", X"9be", X"9bc", X"9ba", X"9b8", X"9b6", X"9b4",
X"9b2", X"9b0", X"9ae", X"9ac", X"9ab", X"9a9", X"9a7", X"9a5",
X"9a3", X"9a1", X"99f", X"99d", X"99b", X"999", X"998", X"996",
X"994", X"992", X"990", X"98e", X"98c", X"98b", X"989", X"987",
X"985", X"983", X"981", X"97f", X"97e", X"97c", X"97a", X"978",
X"976", X"975", X"973", X"971", X"96f", X"96d", X"96c", X"96a",
X"968", X"966", X"965", X"963", X"961", X"95f", X"95d", X"95c",
X"95a", X"958", X"957", X"955", X"953", X"951", X"950", X"94e",
X"94c", X"94a", X"949", X"947", X"945", X"944", X"942", X"940",
X"93f", X"93d", X"93b", X"93a", X"938", X"936", X"935", X"933",
X"931", X"930", X"92e", X"92c", X"92b", X"929", X"927", X"926",
X"924", X"923", X"921", X"91f", X"91e", X"91c", X"91b", X"919",
X"917", X"916", X"914", X"913", X"911", X"910", X"90e", X"90c",
X"90b", X"909", X"908", X"906", X"905", X"903", X"902", X"900",
X"8ff", X"8fd", X"8fc", X"8fa", X"8f9", X"8f7", X"8f6", X"8f4",
X"8f3", X"8f1", X"8f0", X"8ee", X"8ed", X"8eb", X"8ea", X"8e8",
X"8e7", X"8e6", X"8e4", X"8e3", X"8e1", X"8e0", X"8de", X"8dd",
X"8dc", X"8da", X"8d9", X"8d7", X"8d6", X"8d5", X"8d3", X"8d2",
X"8d0", X"8cf", X"8ce", X"8cc", X"8cb", X"8ca", X"8c8", X"8c7",
X"8c6", X"8c4", X"8c3", X"8c2", X"8c0", X"8bf", X"8be", X"8bc",
X"8bb", X"8ba", X"8b8", X"8b7", X"8b6", X"8b4", X"8b3", X"8b2",
X"8b1", X"8af", X"8ae", X"8ad", X"8ac", X"8aa", X"8a9", X"8a8",
X"8a7", X"8a5", X"8a4", X"8a3", X"8a2", X"8a0", X"89f", X"89e",
X"89d", X"89c", X"89a", X"899", X"898", X"897", X"896", X"895",
X"893", X"892", X"891", X"890", X"88f", X"88e", X"88c", X"88b",
X"88a", X"889", X"888", X"887", X"886", X"885", X"883", X"882",
X"881", X"880", X"87f", X"87e", X"87d", X"87c", X"87b", X"87a",
X"879", X"878", X"877", X"876", X"874", X"873", X"872", X"871",
X"870", X"86f", X"86e", X"86d", X"86c", X"86b", X"86a", X"869",
X"868", X"867", X"866", X"865", X"864", X"863", X"862", X"862",
X"861", X"860", X"85f", X"85e", X"85d", X"85c", X"85b", X"85a",
X"859", X"858", X"857", X"856", X"856", X"855", X"854", X"853",
X"852", X"851", X"850", X"84f", X"84f", X"84e", X"84d", X"84c",
X"84b", X"84a", X"849", X"849", X"848", X"847", X"846", X"845",
X"845", X"844", X"843", X"842", X"841", X"841", X"840", X"83f",
X"83e", X"83e", X"83d", X"83c", X"83b", X"83b", X"83a", X"839",
X"838", X"838", X"837", X"836", X"836", X"835", X"834", X"833",
X"833", X"832", X"831", X"831", X"830", X"82f", X"82f", X"82e",
X"82d", X"82d", X"82c", X"82b", X"82b", X"82a", X"82a", X"829",
X"828", X"828", X"827", X"827", X"826", X"825", X"825", X"824",
X"824", X"823", X"822", X"822", X"821", X"821", X"820", X"820",
X"81f", X"81f", X"81e", X"81e", X"81d", X"81d", X"81c", X"81b",
X"81b", X"81a", X"81a", X"81a", X"819", X"819", X"818", X"818",
X"817", X"817", X"816", X"816", X"815", X"815", X"814", X"814",
X"814", X"813", X"813", X"812", X"812", X"812", X"811", X"811",
X"810", X"810", X"810", X"80f", X"80f", X"80f", X"80e", X"80e",
X"80d", X"80d", X"80d", X"80c", X"80c", X"80c", X"80b", X"80b",
X"80b", X"80b", X"80a", X"80a", X"80a", X"809", X"809", X"809",
X"809", X"808", X"808", X"808", X"808", X"807", X"807", X"807",
X"807", X"806", X"806", X"806", X"806", X"805", X"805", X"805",
X"805", X"805", X"804", X"804", X"804", X"804", X"804", X"804",
X"803", X"803", X"803", X"803", X"803", X"803", X"803", X"803",
X"802", X"802", X"802", X"802", X"802", X"802", X"802", X"802",
X"802", X"802", X"801", X"801", X"801", X"801", X"801", X"801",
X"801", X"801", X"801", X"801", X"801", X"801", X"801", X"801",
X"801", X"801", X"801", X"801", X"801", X"801", X"801", X"801",
X"801", X"801", X"801", X"801", X"801", X"801", X"801", X"802",
X"802", X"802", X"802", X"802", X"802", X"802", X"802", X"802",
X"802", X"803", X"803", X"803", X"803", X"803", X"803", X"803",
X"803", X"804", X"804", X"804", X"804", X"804", X"804", X"805",
X"805", X"805", X"805", X"805", X"806", X"806", X"806", X"806",
X"807", X"807", X"807", X"807", X"808", X"808", X"808", X"808",
X"809", X"809", X"809", X"809", X"80a", X"80a", X"80a", X"80b",
X"80b", X"80b", X"80b", X"80c", X"80c", X"80c", X"80d", X"80d",
X"80d", X"80e", X"80e", X"80f", X"80f", X"80f", X"810", X"810",
X"810", X"811", X"811", X"812", X"812", X"812", X"813", X"813",
X"814", X"814", X"814", X"815", X"815", X"816", X"816", X"817",
X"817", X"818", X"818", X"819", X"819", X"81a", X"81a", X"81a",
X"81b", X"81b", X"81c", X"81d", X"81d", X"81e", X"81e", X"81f",
X"81f", X"820", X"820", X"821", X"821", X"822", X"822", X"823",
X"824", X"824", X"825", X"825", X"826", X"827", X"827", X"828",
X"828", X"829", X"82a", X"82a", X"82b", X"82b", X"82c", X"82d",
X"82d", X"82e", X"82f", X"82f", X"830", X"831", X"831", X"832",
X"833", X"833", X"834", X"835", X"836", X"836", X"837", X"838",
X"838", X"839", X"83a", X"83b", X"83b", X"83c", X"83d", X"83e",
X"83e", X"83f", X"840", X"841", X"841", X"842", X"843", X"844",
X"845", X"845", X"846", X"847", X"848", X"849", X"849", X"84a",
X"84b", X"84c", X"84d", X"84e", X"84f", X"84f", X"850", X"851",
X"852", X"853", X"854", X"855", X"856", X"856", X"857", X"858",
X"859", X"85a", X"85b", X"85c", X"85d", X"85e", X"85f", X"860",
X"861", X"862", X"862", X"863", X"864", X"865", X"866", X"867",
X"868", X"869", X"86a", X"86b", X"86c", X"86d", X"86e", X"86f",
X"870", X"871", X"872", X"873", X"874", X"876", X"877", X"878",
X"879", X"87a", X"87b", X"87c", X"87d", X"87e", X"87f", X"880",
X"881", X"882", X"883", X"885", X"886", X"887", X"888", X"889",
X"88a", X"88b", X"88c", X"88e", X"88f", X"890", X"891", X"892",
X"893", X"895", X"896", X"897", X"898", X"899", X"89a", X"89c",
X"89d", X"89e", X"89f", X"8a0", X"8a2", X"8a3", X"8a4", X"8a5",
X"8a7", X"8a8", X"8a9", X"8aa", X"8ac", X"8ad", X"8ae", X"8af",
X"8b1", X"8b2", X"8b3", X"8b4", X"8b6", X"8b7", X"8b8", X"8ba",
X"8bb", X"8bc", X"8be", X"8bf", X"8c0", X"8c2", X"8c3", X"8c4",
X"8c6", X"8c7", X"8c8", X"8ca", X"8cb", X"8cc", X"8ce", X"8cf",
X"8d0", X"8d2", X"8d3", X"8d5", X"8d6", X"8d7", X"8d9", X"8da",
X"8dc", X"8dd", X"8de", X"8e0", X"8e1", X"8e3", X"8e4", X"8e6",
X"8e7", X"8e8", X"8ea", X"8eb", X"8ed", X"8ee", X"8f0", X"8f1",
X"8f3", X"8f4", X"8f6", X"8f7", X"8f9", X"8fa", X"8fc", X"8fd",
X"8ff", X"900", X"902", X"903", X"905", X"906", X"908", X"909",
X"90b", X"90c", X"90e", X"910", X"911", X"913", X"914", X"916",
X"917", X"919", X"91b", X"91c", X"91e", X"91f", X"921", X"923",
X"924", X"926", X"927", X"929", X"92b", X"92c", X"92e", X"930",
X"931", X"933", X"935", X"936", X"938", X"93a", X"93b", X"93d",
X"93f", X"940", X"942", X"944", X"945", X"947", X"949", X"94a",
X"94c", X"94e", X"950", X"951", X"953", X"955", X"957", X"958",
X"95a", X"95c", X"95d", X"95f", X"961", X"963", X"965", X"966",
X"968", X"96a", X"96c", X"96d", X"96f", X"971", X"973", X"975",
X"976", X"978", X"97a", X"97c", X"97e", X"97f", X"981", X"983",
X"985", X"987", X"989", X"98b", X"98c", X"98e", X"990", X"992",
X"994", X"996", X"998", X"999", X"99b", X"99d", X"99f", X"9a1",
X"9a3", X"9a5", X"9a7", X"9a9", X"9ab", X"9ac", X"9ae", X"9b0",
X"9b2", X"9b4", X"9b6", X"9b8", X"9ba", X"9bc", X"9be", X"9c0",
X"9c2", X"9c4", X"9c6", X"9c8", X"9ca", X"9cc", X"9ce", X"9d0",
X"9d2", X"9d4", X"9d6", X"9d8", X"9da", X"9dc", X"9de", X"9e0",
X"9e2", X"9e4", X"9e6", X"9e8", X"9ea", X"9ec", X"9ee", X"9f0",
X"9f2", X"9f4", X"9f6", X"9f8", X"9fa", X"9fc", X"9fe", X"a00",
X"a03", X"a05", X"a07", X"a09", X"a0b", X"a0d", X"a0f", X"a11",
X"a13", X"a15", X"a17", X"a1a", X"a1c", X"a1e", X"a20", X"a22",
X"a24", X"a26", X"a29", X"a2b", X"a2d", X"a2f", X"a31", X"a33",
X"a35", X"a38", X"a3a", X"a3c", X"a3e", X"a40", X"a43", X"a45",
X"a47", X"a49", X"a4b", X"a4d", X"a50", X"a52", X"a54", X"a56",
X"a59", X"a5b", X"a5d", X"a5f", X"a61", X"a64", X"a66", X"a68",
X"a6a", X"a6d", X"a6f", X"a71", X"a73", X"a76", X"a78", X"a7a",
X"a7d", X"a7f", X"a81", X"a83", X"a86", X"a88", X"a8a", X"a8d",
X"a8f", X"a91", X"a93", X"a96", X"a98", X"a9a", X"a9d", X"a9f",
X"aa1", X"aa4", X"aa6", X"aa8", X"aab", X"aad", X"aaf", X"ab2",
X"ab4", X"ab6", X"ab9", X"abb", X"abd", X"ac0", X"ac2", X"ac5",
X"ac7", X"ac9", X"acc", X"ace", X"ad0", X"ad3", X"ad5", X"ad8",
X"ada", X"adc", X"adf", X"ae1", X"ae4", X"ae6", X"ae9", X"aeb",
X"aed", X"af0", X"af2", X"af5", X"af7", X"afa", X"afc", X"afe",
X"b01", X"b03", X"b06", X"b08", X"b0b", X"b0d", X"b10", X"b12",
X"b15", X"b17", X"b1a", X"b1c", X"b1f", X"b21", X"b24", X"b26",
X"b29", X"b2b", X"b2e", X"b30", X"b33", X"b35", X"b38", X"b3a",
X"b3d", X"b3f", X"b42", X"b44", X"b47", X"b49", X"b4c", X"b4e",
X"b51", X"b53", X"b56", X"b59", X"b5b", X"b5e", X"b60", X"b63",
X"b65", X"b68", X"b6a", X"b6d", X"b70", X"b72", X"b75", X"b77",
X"b7a", X"b7d", X"b7f", X"b82", X"b84", X"b87", X"b8a", X"b8c",
X"b8f", X"b91", X"b94", X"b97", X"b99", X"b9c", X"b9e", X"ba1",
X"ba4", X"ba6", X"ba9", X"bac", X"bae", X"bb1", X"bb4", X"bb6",
X"bb9", X"bbc", X"bbe", X"bc1", X"bc3", X"bc6", X"bc9", X"bcb",
X"bce", X"bd1", X"bd4", X"bd6", X"bd9", X"bdc", X"bde", X"be1",
X"be4", X"be6", X"be9", X"bec", X"bee", X"bf1", X"bf4", X"bf7",
X"bf9", X"bfc", X"bff", X"c01", X"c04", X"c07", X"c0a", X"c0c",
X"c0f", X"c12", X"c15", X"c17", X"c1a", X"c1d", X"c1f", X"c22",
X"c25", X"c28", X"c2a", X"c2d", X"c30", X"c33", X"c36", X"c38",
X"c3b", X"c3e", X"c41", X"c43", X"c46", X"c49", X"c4c", X"c4e",
X"c51", X"c54", X"c57", X"c5a", X"c5c", X"c5f", X"c62", X"c65",
X"c68", X"c6a", X"c6d", X"c70", X"c73", X"c76", X"c79", X"c7b",
X"c7e", X"c81", X"c84", X"c87", X"c89", X"c8c", X"c8f", X"c92",
X"c95", X"c98", X"c9a", X"c9d", X"ca0", X"ca3", X"ca6", X"ca9",
X"cac", X"cae", X"cb1", X"cb4", X"cb7", X"cba", X"cbd", X"cc0",
X"cc2", X"cc5", X"cc8", X"ccb", X"cce", X"cd1", X"cd4", X"cd7",
X"cd9", X"cdc", X"cdf", X"ce2", X"ce5", X"ce8", X"ceb", X"cee",
X"cf1", X"cf4", X"cf6", X"cf9", X"cfc", X"cff", X"d02", X"d05",
X"d08", X"d0b", X"d0e", X"d11", X"d14", X"d17", X"d19", X"d1c",
X"d1f", X"d22", X"d25", X"d28", X"d2b", X"d2e", X"d31", X"d34",
X"d37", X"d3a", X"d3d", X"d40", X"d43", X"d46", X"d48", X"d4b",
X"d4e", X"d51", X"d54", X"d57", X"d5a", X"d5d", X"d60", X"d63",
X"d66", X"d69", X"d6c", X"d6f", X"d72", X"d75", X"d78", X"d7b",
X"d7e", X"d81", X"d84", X"d87", X"d8a", X"d8d", X"d90", X"d93",
X"d96", X"d99", X"d9c", X"d9f", X"da2", X"da5", X"da8", X"dab",
X"dae", X"db1", X"db4", X"db7", X"dba", X"dbd", X"dc0", X"dc3",
X"dc6", X"dc9", X"dcc", X"dcf", X"dd2", X"dd5", X"dd8", X"ddb",
X"dde", X"de1", X"de4", X"de7", X"dea", X"ded", X"df0", X"df3",
X"df6", X"df9", X"dfc", X"dff", X"e02", X"e05", X"e09", X"e0c",
X"e0f", X"e12", X"e15", X"e18", X"e1b", X"e1e", X"e21", X"e24",
X"e27", X"e2a", X"e2d", X"e30", X"e33", X"e36", X"e39", X"e3c",
X"e3f", X"e43", X"e46", X"e49", X"e4c", X"e4f", X"e52", X"e55",
X"e58", X"e5b", X"e5e", X"e61", X"e64", X"e67", X"e6a", X"e6e",
X"e71", X"e74", X"e77", X"e7a", X"e7d", X"e80", X"e83", X"e86",
X"e89", X"e8c", X"e8f", X"e93", X"e96", X"e99", X"e9c", X"e9f",
X"ea2", X"ea5", X"ea8", X"eab", X"eae", X"eb2", X"eb5", X"eb8",
X"ebb", X"ebe", X"ec1", X"ec4", X"ec7", X"eca", X"ecd", X"ed1",
X"ed4", X"ed7", X"eda", X"edd", X"ee0", X"ee3", X"ee6", X"ee9",
X"eed", X"ef0", X"ef3", X"ef6", X"ef9", X"efc", X"eff", X"f02",
X"f05", X"f09", X"f0c", X"f0f", X"f12", X"f15", X"f18", X"f1b",
X"f1e", X"f21", X"f25", X"f28", X"f2b", X"f2e", X"f31", X"f34",
X"f37", X"f3a", X"f3e", X"f41", X"f44", X"f47", X"f4a", X"f4d",
X"f50", X"f54", X"f57", X"f5a", X"f5d", X"f60", X"f63", X"f66",
X"f69", X"f6d", X"f70", X"f73", X"f76", X"f79", X"f7c", X"f7f",
X"f82", X"f86", X"f89", X"f8c", X"f8f", X"f92", X"f95", X"f98",
X"f9c", X"f9f", X"fa2", X"fa5", X"fa8", X"fab", X"fae", X"fb2",
X"fb5", X"fb8", X"fbb", X"fbe", X"fc1", X"fc4", X"fc7", X"fcb",
X"fce", X"fd1", X"fd4", X"fd7", X"fda", X"fdd", X"fe1", X"fe4",
X"fe7", X"fea", X"fed", X"ff0", X"ff3", X"ff7", X"ffa", X"ffd"
);
constant COS_ROM : rom_type :=
(
X"7ff", X"7ff", X"7ff", X"7ff", X"7ff", X"7ff", X"7ff", X"7ff",
X"7ff", X"7ff", X"7ff", X"7ff", X"7ff", X"7ff", X"7ff", X"7fe",
X"7fe", X"7fe", X"7fe", X"7fe", X"7fe", X"7fe", X"7fe", X"7fe",
X"7fe", X"7fd", X"7fd", X"7fd", X"7fd", X"7fd", X"7fd", X"7fd",
X"7fd", X"7fc", X"7fc", X"7fc", X"7fc", X"7fc", X"7fc", X"7fb",
X"7fb", X"7fb", X"7fb", X"7fb", X"7fa", X"7fa", X"7fa", X"7fa",
X"7f9", X"7f9", X"7f9", X"7f9", X"7f8", X"7f8", X"7f8", X"7f8",
X"7f7", X"7f7", X"7f7", X"7f7", X"7f6", X"7f6", X"7f6", X"7f5",
X"7f5", X"7f5", X"7f5", X"7f4", X"7f4", X"7f4", X"7f3", X"7f3",
X"7f3", X"7f2", X"7f2", X"7f1", X"7f1", X"7f1", X"7f0", X"7f0",
X"7f0", X"7ef", X"7ef", X"7ee", X"7ee", X"7ee", X"7ed", X"7ed",
X"7ec", X"7ec", X"7ec", X"7eb", X"7eb", X"7ea", X"7ea", X"7e9",
X"7e9", X"7e8", X"7e8", X"7e7", X"7e7", X"7e6", X"7e6", X"7e6",
X"7e5", X"7e5", X"7e4", X"7e3", X"7e3", X"7e2", X"7e2", X"7e1",
X"7e1", X"7e0", X"7e0", X"7df", X"7df", X"7de", X"7de", X"7dd",
X"7dc", X"7dc", X"7db", X"7db", X"7da", X"7d9", X"7d9", X"7d8",
X"7d8", X"7d7", X"7d6", X"7d6", X"7d5", X"7d5", X"7d4", X"7d3",
X"7d3", X"7d2", X"7d1", X"7d1", X"7d0", X"7cf", X"7cf", X"7ce",
X"7cd", X"7cd", X"7cc", X"7cb", X"7ca", X"7ca", X"7c9", X"7c8",
X"7c8", X"7c7", X"7c6", X"7c5", X"7c5", X"7c4", X"7c3", X"7c2",
X"7c2", X"7c1", X"7c0", X"7bf", X"7bf", X"7be", X"7bd", X"7bc",
X"7bb", X"7bb", X"7ba", X"7b9", X"7b8", X"7b7", X"7b7", X"7b6",
X"7b5", X"7b4", X"7b3", X"7b2", X"7b1", X"7b1", X"7b0", X"7af",
X"7ae", X"7ad", X"7ac", X"7ab", X"7aa", X"7aa", X"7a9", X"7a8",
X"7a7", X"7a6", X"7a5", X"7a4", X"7a3", X"7a2", X"7a1", X"7a0",
X"79f", X"79e", X"79e", X"79d", X"79c", X"79b", X"79a", X"799",
X"798", X"797", X"796", X"795", X"794", X"793", X"792", X"791",
X"790", X"78f", X"78e", X"78d", X"78c", X"78a", X"789", X"788",
X"787", X"786", X"785", X"784", X"783", X"782", X"781", X"780",
X"77f", X"77e", X"77d", X"77b", X"77a", X"779", X"778", X"777",
X"776", X"775", X"774", X"772", X"771", X"770", X"76f", X"76e",
X"76d", X"76b", X"76a", X"769", X"768", X"767", X"766", X"764",
X"763", X"762", X"761", X"760", X"75e", X"75d", X"75c", X"75b",
X"759", X"758", X"757", X"756", X"754", X"753", X"752", X"751",
X"74f", X"74e", X"74d", X"74c", X"74a", X"749", X"748", X"746",
X"745", X"744", X"742", X"741", X"740", X"73e", X"73d", X"73c",
X"73a", X"739", X"738", X"736", X"735", X"734", X"732", X"731",
X"730", X"72e", X"72d", X"72b", X"72a", X"729", X"727", X"726",
X"724", X"723", X"722", X"720", X"71f", X"71d", X"71c", X"71a",
X"719", X"718", X"716", X"715", X"713", X"712", X"710", X"70f",
X"70d", X"70c", X"70a", X"709", X"707", X"706", X"704", X"703",
X"701", X"700", X"6fe", X"6fd", X"6fb", X"6fa", X"6f8", X"6f7",
X"6f5", X"6f4", X"6f2", X"6f0", X"6ef", X"6ed", X"6ec", X"6ea",
X"6e9", X"6e7", X"6e5", X"6e4", X"6e2", X"6e1", X"6df", X"6dd",
X"6dc", X"6da", X"6d9", X"6d7", X"6d5", X"6d4", X"6d2", X"6d0",
X"6cf", X"6cd", X"6cb", X"6ca", X"6c8", X"6c6", X"6c5", X"6c3",
X"6c1", X"6c0", X"6be", X"6bc", X"6bb", X"6b9", X"6b7", X"6b6",
X"6b4", X"6b2", X"6b0", X"6af", X"6ad", X"6ab", X"6a9", X"6a8",
X"6a6", X"6a4", X"6a3", X"6a1", X"69f", X"69d", X"69b", X"69a",
X"698", X"696", X"694", X"693", X"691", X"68f", X"68d", X"68b",
X"68a", X"688", X"686", X"684", X"682", X"681", X"67f", X"67d",
X"67b", X"679", X"677", X"675", X"674", X"672", X"670", X"66e",
X"66c", X"66a", X"668", X"667", X"665", X"663", X"661", X"65f",
X"65d", X"65b", X"659", X"657", X"655", X"654", X"652", X"650",
X"64e", X"64c", X"64a", X"648", X"646", X"644", X"642", X"640",
X"63e", X"63c", X"63a", X"638", X"636", X"634", X"632", X"630",
X"62e", X"62c", X"62a", X"628", X"626", X"624", X"622", X"620",
X"61e", X"61c", X"61a", X"618", X"616", X"614", X"612", X"610",
X"60e", X"60c", X"60a", X"608", X"606", X"604", X"602", X"600",
X"5fd", X"5fb", X"5f9", X"5f7", X"5f5", X"5f3", X"5f1", X"5ef",
X"5ed", X"5eb", X"5e9", X"5e6", X"5e4", X"5e2", X"5e0", X"5de",
X"5dc", X"5da", X"5d7", X"5d5", X"5d3", X"5d1", X"5cf", X"5cd",
X"5cb", X"5c8", X"5c6", X"5c4", X"5c2", X"5c0", X"5bd", X"5bb",
X"5b9", X"5b7", X"5b5", X"5b3", X"5b0", X"5ae", X"5ac", X"5aa",
X"5a7", X"5a5", X"5a3", X"5a1", X"59f", X"59c", X"59a", X"598",
X"596", X"593", X"591", X"58f", X"58d", X"58a", X"588", X"586",
X"583", X"581", X"57f", X"57d", X"57a", X"578", X"576", X"573",
X"571", X"56f", X"56d", X"56a", X"568", X"566", X"563", X"561",
X"55f", X"55c", X"55a", X"558", X"555", X"553", X"551", X"54e",
X"54c", X"54a", X"547", X"545", X"543", X"540", X"53e", X"53b",
X"539", X"537", X"534", X"532", X"530", X"52d", X"52b", X"528",
X"526", X"524", X"521", X"51f", X"51c", X"51a", X"517", X"515",
X"513", X"510", X"50e", X"50b", X"509", X"506", X"504", X"502",
X"4ff", X"4fd", X"4fa", X"4f8", X"4f5", X"4f3", X"4f0", X"4ee",
X"4eb", X"4e9", X"4e6", X"4e4", X"4e1", X"4df", X"4dc", X"4da",
X"4d7", X"4d5", X"4d2", X"4d0", X"4cd", X"4cb", X"4c8", X"4c6",
X"4c3", X"4c1", X"4be", X"4bc", X"4b9", X"4b7", X"4b4", X"4b2",
X"4af", X"4ad", X"4aa", X"4a7", X"4a5", X"4a2", X"4a0", X"49d",
X"49b", X"498", X"496", X"493", X"490", X"48e", X"48b", X"489",
X"486", X"483", X"481", X"47e", X"47c", X"479", X"476", X"474",
X"471", X"46f", X"46c", X"469", X"467", X"464", X"462", X"45f",
X"45c", X"45a", X"457", X"454", X"452", X"44f", X"44c", X"44a",
X"447", X"444", X"442", X"43f", X"43d", X"43a", X"437", X"435",
X"432", X"42f", X"42c", X"42a", X"427", X"424", X"422", X"41f",
X"41c", X"41a", X"417", X"414", X"412", X"40f", X"40c", X"409",
X"407", X"404", X"401", X"3ff", X"3fc", X"3f9", X"3f6", X"3f4",
X"3f1", X"3ee", X"3eb", X"3e9", X"3e6", X"3e3", X"3e1", X"3de",
X"3db", X"3d8", X"3d6", X"3d3", X"3d0", X"3cd", X"3ca", X"3c8",
X"3c5", X"3c2", X"3bf", X"3bd", X"3ba", X"3b7", X"3b4", X"3b2",
X"3af", X"3ac", X"3a9", X"3a6", X"3a4", X"3a1", X"39e", X"39b",
X"398", X"396", X"393", X"390", X"38d", X"38a", X"387", X"385",
X"382", X"37f", X"37c", X"379", X"377", X"374", X"371", X"36e",
X"36b", X"368", X"366", X"363", X"360", X"35d", X"35a", X"357",
X"354", X"352", X"34f", X"34c", X"349", X"346", X"343", X"340",
X"33e", X"33b", X"338", X"335", X"332", X"32f", X"32c", X"329",
X"327", X"324", X"321", X"31e", X"31b", X"318", X"315", X"312",
X"30f", X"30c", X"30a", X"307", X"304", X"301", X"2fe", X"2fb",
X"2f8", X"2f5", X"2f2", X"2ef", X"2ec", X"2e9", X"2e7", X"2e4",
X"2e1", X"2de", X"2db", X"2d8", X"2d5", X"2d2", X"2cf", X"2cc",
X"2c9", X"2c6", X"2c3", X"2c0", X"2bd", X"2ba", X"2b8", X"2b5",
X"2b2", X"2af", X"2ac", X"2a9", X"2a6", X"2a3", X"2a0", X"29d",
X"29a", X"297", X"294", X"291", X"28e", X"28b", X"288", X"285",
X"282", X"27f", X"27c", X"279", X"276", X"273", X"270", X"26d",
X"26a", X"267", X"264", X"261", X"25e", X"25b", X"258", X"255",
X"252", X"24f", X"24c", X"249", X"246", X"243", X"240", X"23d",
X"23a", X"237", X"234", X"231", X"22e", X"22b", X"228", X"225",
X"222", X"21f", X"21c", X"219", X"216", X"213", X"210", X"20d",
X"20a", X"207", X"204", X"201", X"1fe", X"1fb", X"1f7", X"1f4",
X"1f1", X"1ee", X"1eb", X"1e8", X"1e5", X"1e2", X"1df", X"1dc",
X"1d9", X"1d6", X"1d3", X"1d0", X"1cd", X"1ca", X"1c7", X"1c4",
X"1c1", X"1bd", X"1ba", X"1b7", X"1b4", X"1b1", X"1ae", X"1ab",
X"1a8", X"1a5", X"1a2", X"19f", X"19c", X"199", X"196", X"192",
X"18f", X"18c", X"189", X"186", X"183", X"180", X"17d", X"17a",
X"177", X"174", X"171", X"16d", X"16a", X"167", X"164", X"161",
X"15e", X"15b", X"158", X"155", X"152", X"14e", X"14b", X"148",
X"145", X"142", X"13f", X"13c", X"139", X"136", X"133", X"12f",
X"12c", X"129", X"126", X"123", X"120", X"11d", X"11a", X"117",
X"113", X"110", X"10d", X"10a", X"107", X"104", X"101", X"0fe",
X"0fb", X"0f7", X"0f4", X"0f1", X"0ee", X"0eb", X"0e8", X"0e5",
X"0e2", X"0df", X"0db", X"0d8", X"0d5", X"0d2", X"0cf", X"0cc",
X"0c9", X"0c6", X"0c2", X"0bf", X"0bc", X"0b9", X"0b6", X"0b3",
X"0b0", X"0ac", X"0a9", X"0a6", X"0a3", X"0a0", X"09d", X"09a",
X"097", X"093", X"090", X"08d", X"08a", X"087", X"084", X"081",
X"07e", X"07a", X"077", X"074", X"071", X"06e", X"06b", X"068",
X"064", X"061", X"05e", X"05b", X"058", X"055", X"052", X"04e",
X"04b", X"048", X"045", X"042", X"03f", X"03c", X"039", X"035",
X"032", X"02f", X"02c", X"029", X"026", X"023", X"01f", X"01c",
X"019", X"016", X"013", X"010", X"00d", X"009", X"006", X"003",
X"000", X"ffd", X"ffa", X"ff7", X"ff3", X"ff0", X"fed", X"fea",
X"fe7", X"fe4", X"fe1", X"fdd", X"fda", X"fd7", X"fd4", X"fd1",
X"fce", X"fcb", X"fc7", X"fc4", X"fc1", X"fbe", X"fbb", X"fb8",
X"fb5", X"fb2", X"fae", X"fab", X"fa8", X"fa5", X"fa2", X"f9f",
X"f9c", X"f98", X"f95", X"f92", X"f8f", X"f8c", X"f89", X"f86",
X"f82", X"f7f", X"f7c", X"f79", X"f76", X"f73", X"f70", X"f6d",
X"f69", X"f66", X"f63", X"f60", X"f5d", X"f5a", X"f57", X"f54",
X"f50", X"f4d", X"f4a", X"f47", X"f44", X"f41", X"f3e", X"f3a",
X"f37", X"f34", X"f31", X"f2e", X"f2b", X"f28", X"f25", X"f21",
X"f1e", X"f1b", X"f18", X"f15", X"f12", X"f0f", X"f0c", X"f09",
X"f05", X"f02", X"eff", X"efc", X"ef9", X"ef6", X"ef3", X"ef0",
X"eed", X"ee9", X"ee6", X"ee3", X"ee0", X"edd", X"eda", X"ed7",
X"ed4", X"ed1", X"ecd", X"eca", X"ec7", X"ec4", X"ec1", X"ebe",
X"ebb", X"eb8", X"eb5", X"eb2", X"eae", X"eab", X"ea8", X"ea5",
X"ea2", X"e9f", X"e9c", X"e99", X"e96", X"e93", X"e8f", X"e8c",
X"e89", X"e86", X"e83", X"e80", X"e7d", X"e7a", X"e77", X"e74",
X"e71", X"e6e", X"e6a", X"e67", X"e64", X"e61", X"e5e", X"e5b",
X"e58", X"e55", X"e52", X"e4f", X"e4c", X"e49", X"e46", X"e43",
X"e3f", X"e3c", X"e39", X"e36", X"e33", X"e30", X"e2d", X"e2a",
X"e27", X"e24", X"e21", X"e1e", X"e1b", X"e18", X"e15", X"e12",
X"e0f", X"e0c", X"e09", X"e05", X"e02", X"dff", X"dfc", X"df9",
X"df6", X"df3", X"df0", X"ded", X"dea", X"de7", X"de4", X"de1",
X"dde", X"ddb", X"dd8", X"dd5", X"dd2", X"dcf", X"dcc", X"dc9",
X"dc6", X"dc3", X"dc0", X"dbd", X"dba", X"db7", X"db4", X"db1",
X"dae", X"dab", X"da8", X"da5", X"da2", X"d9f", X"d9c", X"d99",
X"d96", X"d93", X"d90", X"d8d", X"d8a", X"d87", X"d84", X"d81",
X"d7e", X"d7b", X"d78", X"d75", X"d72", X"d6f", X"d6c", X"d69",
X"d66", X"d63", X"d60", X"d5d", X"d5a", X"d57", X"d54", X"d51",
X"d4e", X"d4b", X"d48", X"d46", X"d43", X"d40", X"d3d", X"d3a",
X"d37", X"d34", X"d31", X"d2e", X"d2b", X"d28", X"d25", X"d22",
X"d1f", X"d1c", X"d19", X"d17", X"d14", X"d11", X"d0e", X"d0b",
X"d08", X"d05", X"d02", X"cff", X"cfc", X"cf9", X"cf6", X"cf4",
X"cf1", X"cee", X"ceb", X"ce8", X"ce5", X"ce2", X"cdf", X"cdc",
X"cd9", X"cd7", X"cd4", X"cd1", X"cce", X"ccb", X"cc8", X"cc5",
X"cc2", X"cc0", X"cbd", X"cba", X"cb7", X"cb4", X"cb1", X"cae",
X"cac", X"ca9", X"ca6", X"ca3", X"ca0", X"c9d", X"c9a", X"c98",
X"c95", X"c92", X"c8f", X"c8c", X"c89", X"c87", X"c84", X"c81",
X"c7e", X"c7b", X"c79", X"c76", X"c73", X"c70", X"c6d", X"c6a",
X"c68", X"c65", X"c62", X"c5f", X"c5c", X"c5a", X"c57", X"c54",
X"c51", X"c4e", X"c4c", X"c49", X"c46", X"c43", X"c41", X"c3e",
X"c3b", X"c38", X"c36", X"c33", X"c30", X"c2d", X"c2a", X"c28",
X"c25", X"c22", X"c1f", X"c1d", X"c1a", X"c17", X"c15", X"c12",
X"c0f", X"c0c", X"c0a", X"c07", X"c04", X"c01", X"bff", X"bfc",
X"bf9", X"bf7", X"bf4", X"bf1", X"bee", X"bec", X"be9", X"be6",
X"be4", X"be1", X"bde", X"bdc", X"bd9", X"bd6", X"bd4", X"bd1",
X"bce", X"bcb", X"bc9", X"bc6", X"bc3", X"bc1", X"bbe", X"bbc",
X"bb9", X"bb6", X"bb4", X"bb1", X"bae", X"bac", X"ba9", X"ba6",
X"ba4", X"ba1", X"b9e", X"b9c", X"b99", X"b97", X"b94", X"b91",
X"b8f", X"b8c", X"b8a", X"b87", X"b84", X"b82", X"b7f", X"b7d",
X"b7a", X"b77", X"b75", X"b72", X"b70", X"b6d", X"b6a", X"b68",
X"b65", X"b63", X"b60", X"b5e", X"b5b", X"b59", X"b56", X"b53",
X"b51", X"b4e", X"b4c", X"b49", X"b47", X"b44", X"b42", X"b3f",
X"b3d", X"b3a", X"b38", X"b35", X"b33", X"b30", X"b2e", X"b2b",
X"b29", X"b26", X"b24", X"b21", X"b1f", X"b1c", X"b1a", X"b17",
X"b15", X"b12", X"b10", X"b0d", X"b0b", X"b08", X"b06", X"b03",
X"b01", X"afe", X"afc", X"afa", X"af7", X"af5", X"af2", X"af0",
X"aed", X"aeb", X"ae9", X"ae6", X"ae4", X"ae1", X"adf", X"adc",
X"ada", X"ad8", X"ad5", X"ad3", X"ad0", X"ace", X"acc", X"ac9",
X"ac7", X"ac5", X"ac2", X"ac0", X"abd", X"abb", X"ab9", X"ab6",
X"ab4", X"ab2", X"aaf", X"aad", X"aab", X"aa8", X"aa6", X"aa4",
X"aa1", X"a9f", X"a9d", X"a9a", X"a98", X"a96", X"a93", X"a91",
X"a8f", X"a8d", X"a8a", X"a88", X"a86", X"a83", X"a81", X"a7f",
X"a7d", X"a7a", X"a78", X"a76", X"a73", X"a71", X"a6f", X"a6d",
X"a6a", X"a68", X"a66", X"a64", X"a61", X"a5f", X"a5d", X"a5b",
X"a59", X"a56", X"a54", X"a52", X"a50", X"a4d", X"a4b", X"a49",
X"a47", X"a45", X"a43", X"a40", X"a3e", X"a3c", X"a3a", X"a38",
X"a35", X"a33", X"a31", X"a2f", X"a2d", X"a2b", X"a29", X"a26",
X"a24", X"a22", X"a20", X"a1e", X"a1c", X"a1a", X"a17", X"a15",
X"a13", X"a11", X"a0f", X"a0d", X"a0b", X"a09", X"a07", X"a05",
X"a03", X"a00", X"9fe", X"9fc", X"9fa", X"9f8", X"9f6", X"9f4",
X"9f2", X"9f0", X"9ee", X"9ec", X"9ea", X"9e8", X"9e6", X"9e4",
X"9e2", X"9e0", X"9de", X"9dc", X"9da", X"9d8", X"9d6", X"9d4",
X"9d2", X"9d0", X"9ce", X"9cc", X"9ca", X"9c8", X"9c6", X"9c4",
X"9c2", X"9c0", X"9be", X"9bc", X"9ba", X"9b8", X"9b6", X"9b4",
X"9b2", X"9b0", X"9ae", X"9ac", X"9ab", X"9a9", X"9a7", X"9a5",
X"9a3", X"9a1", X"99f", X"99d", X"99b", X"999", X"998", X"996",
X"994", X"992", X"990", X"98e", X"98c", X"98b", X"989", X"987",
X"985", X"983", X"981", X"97f", X"97e", X"97c", X"97a", X"978",
X"976", X"975", X"973", X"971", X"96f", X"96d", X"96c", X"96a",
X"968", X"966", X"965", X"963", X"961", X"95f", X"95d", X"95c",
X"95a", X"958", X"957", X"955", X"953", X"951", X"950", X"94e",
X"94c", X"94a", X"949", X"947", X"945", X"944", X"942", X"940",
X"93f", X"93d", X"93b", X"93a", X"938", X"936", X"935", X"933",
X"931", X"930", X"92e", X"92c", X"92b", X"929", X"927", X"926",
X"924", X"923", X"921", X"91f", X"91e", X"91c", X"91b", X"919",
X"917", X"916", X"914", X"913", X"911", X"910", X"90e", X"90c",
X"90b", X"909", X"908", X"906", X"905", X"903", X"902", X"900",
X"8ff", X"8fd", X"8fc", X"8fa", X"8f9", X"8f7", X"8f6", X"8f4",
X"8f3", X"8f1", X"8f0", X"8ee", X"8ed", X"8eb", X"8ea", X"8e8",
X"8e7", X"8e6", X"8e4", X"8e3", X"8e1", X"8e0", X"8de", X"8dd",
X"8dc", X"8da", X"8d9", X"8d7", X"8d6", X"8d5", X"8d3", X"8d2",
X"8d0", X"8cf", X"8ce", X"8cc", X"8cb", X"8ca", X"8c8", X"8c7",
X"8c6", X"8c4", X"8c3", X"8c2", X"8c0", X"8bf", X"8be", X"8bc",
X"8bb", X"8ba", X"8b8", X"8b7", X"8b6", X"8b4", X"8b3", X"8b2",
X"8b1", X"8af", X"8ae", X"8ad", X"8ac", X"8aa", X"8a9", X"8a8",
X"8a7", X"8a5", X"8a4", X"8a3", X"8a2", X"8a0", X"89f", X"89e",
X"89d", X"89c", X"89a", X"899", X"898", X"897", X"896", X"895",
X"893", X"892", X"891", X"890", X"88f", X"88e", X"88c", X"88b",
X"88a", X"889", X"888", X"887", X"886", X"885", X"883", X"882",
X"881", X"880", X"87f", X"87e", X"87d", X"87c", X"87b", X"87a",
X"879", X"878", X"877", X"876", X"874", X"873", X"872", X"871",
X"870", X"86f", X"86e", X"86d", X"86c", X"86b", X"86a", X"869",
X"868", X"867", X"866", X"865", X"864", X"863", X"862", X"862",
X"861", X"860", X"85f", X"85e", X"85d", X"85c", X"85b", X"85a",
X"859", X"858", X"857", X"856", X"856", X"855", X"854", X"853",
X"852", X"851", X"850", X"84f", X"84f", X"84e", X"84d", X"84c",
X"84b", X"84a", X"849", X"849", X"848", X"847", X"846", X"845",
X"845", X"844", X"843", X"842", X"841", X"841", X"840", X"83f",
X"83e", X"83e", X"83d", X"83c", X"83b", X"83b", X"83a", X"839",
X"838", X"838", X"837", X"836", X"836", X"835", X"834", X"833",
X"833", X"832", X"831", X"831", X"830", X"82f", X"82f", X"82e",
X"82d", X"82d", X"82c", X"82b", X"82b", X"82a", X"82a", X"829",
X"828", X"828", X"827", X"827", X"826", X"825", X"825", X"824",
X"824", X"823", X"822", X"822", X"821", X"821", X"820", X"820",
X"81f", X"81f", X"81e", X"81e", X"81d", X"81d", X"81c", X"81b",
X"81b", X"81a", X"81a", X"81a", X"819", X"819", X"818", X"818",
X"817", X"817", X"816", X"816", X"815", X"815", X"814", X"814",
X"814", X"813", X"813", X"812", X"812", X"812", X"811", X"811",
X"810", X"810", X"810", X"80f", X"80f", X"80f", X"80e", X"80e",
X"80d", X"80d", X"80d", X"80c", X"80c", X"80c", X"80b", X"80b",
X"80b", X"80b", X"80a", X"80a", X"80a", X"809", X"809", X"809",
X"809", X"808", X"808", X"808", X"808", X"807", X"807", X"807",
X"807", X"806", X"806", X"806", X"806", X"805", X"805", X"805",
X"805", X"805", X"804", X"804", X"804", X"804", X"804", X"804",
X"803", X"803", X"803", X"803", X"803", X"803", X"803", X"803",
X"802", X"802", X"802", X"802", X"802", X"802", X"802", X"802",
X"802", X"802", X"801", X"801", X"801", X"801", X"801", X"801",
X"801", X"801", X"801", X"801", X"801", X"801", X"801", X"801",
X"801", X"801", X"801", X"801", X"801", X"801", X"801", X"801",
X"801", X"801", X"801", X"801", X"801", X"801", X"801", X"802",
X"802", X"802", X"802", X"802", X"802", X"802", X"802", X"802",
X"802", X"803", X"803", X"803", X"803", X"803", X"803", X"803",
X"803", X"804", X"804", X"804", X"804", X"804", X"804", X"805",
X"805", X"805", X"805", X"805", X"806", X"806", X"806", X"806",
X"807", X"807", X"807", X"807", X"808", X"808", X"808", X"808",
X"809", X"809", X"809", X"809", X"80a", X"80a", X"80a", X"80b",
X"80b", X"80b", X"80b", X"80c", X"80c", X"80c", X"80d", X"80d",
X"80d", X"80e", X"80e", X"80f", X"80f", X"80f", X"810", X"810",
X"810", X"811", X"811", X"812", X"812", X"812", X"813", X"813",
X"814", X"814", X"814", X"815", X"815", X"816", X"816", X"817",
X"817", X"818", X"818", X"819", X"819", X"81a", X"81a", X"81a",
X"81b", X"81b", X"81c", X"81d", X"81d", X"81e", X"81e", X"81f",
X"81f", X"820", X"820", X"821", X"821", X"822", X"822", X"823",
X"824", X"824", X"825", X"825", X"826", X"827", X"827", X"828",
X"828", X"829", X"82a", X"82a", X"82b", X"82b", X"82c", X"82d",
X"82d", X"82e", X"82f", X"82f", X"830", X"831", X"831", X"832",
X"833", X"833", X"834", X"835", X"836", X"836", X"837", X"838",
X"838", X"839", X"83a", X"83b", X"83b", X"83c", X"83d", X"83e",
X"83e", X"83f", X"840", X"841", X"841", X"842", X"843", X"844",
X"845", X"845", X"846", X"847", X"848", X"849", X"849", X"84a",
X"84b", X"84c", X"84d", X"84e", X"84f", X"84f", X"850", X"851",
X"852", X"853", X"854", X"855", X"856", X"856", X"857", X"858",
X"859", X"85a", X"85b", X"85c", X"85d", X"85e", X"85f", X"860",
X"861", X"862", X"862", X"863", X"864", X"865", X"866", X"867",
X"868", X"869", X"86a", X"86b", X"86c", X"86d", X"86e", X"86f",
X"870", X"871", X"872", X"873", X"874", X"876", X"877", X"878",
X"879", X"87a", X"87b", X"87c", X"87d", X"87e", X"87f", X"880",
X"881", X"882", X"883", X"885", X"886", X"887", X"888", X"889",
X"88a", X"88b", X"88c", X"88e", X"88f", X"890", X"891", X"892",
X"893", X"895", X"896", X"897", X"898", X"899", X"89a", X"89c",
X"89d", X"89e", X"89f", X"8a0", X"8a2", X"8a3", X"8a4", X"8a5",
X"8a7", X"8a8", X"8a9", X"8aa", X"8ac", X"8ad", X"8ae", X"8af",
X"8b1", X"8b2", X"8b3", X"8b4", X"8b6", X"8b7", X"8b8", X"8ba",
X"8bb", X"8bc", X"8be", X"8bf", X"8c0", X"8c2", X"8c3", X"8c4",
X"8c6", X"8c7", X"8c8", X"8ca", X"8cb", X"8cc", X"8ce", X"8cf",
X"8d0", X"8d2", X"8d3", X"8d5", X"8d6", X"8d7", X"8d9", X"8da",
X"8dc", X"8dd", X"8de", X"8e0", X"8e1", X"8e3", X"8e4", X"8e6",
X"8e7", X"8e8", X"8ea", X"8eb", X"8ed", X"8ee", X"8f0", X"8f1",
X"8f3", X"8f4", X"8f6", X"8f7", X"8f9", X"8fa", X"8fc", X"8fd",
X"8ff", X"900", X"902", X"903", X"905", X"906", X"908", X"909",
X"90b", X"90c", X"90e", X"910", X"911", X"913", X"914", X"916",
X"917", X"919", X"91b", X"91c", X"91e", X"91f", X"921", X"923",
X"924", X"926", X"927", X"929", X"92b", X"92c", X"92e", X"930",
X"931", X"933", X"935", X"936", X"938", X"93a", X"93b", X"93d",
X"93f", X"940", X"942", X"944", X"945", X"947", X"949", X"94a",
X"94c", X"94e", X"950", X"951", X"953", X"955", X"957", X"958",
X"95a", X"95c", X"95d", X"95f", X"961", X"963", X"965", X"966",
X"968", X"96a", X"96c", X"96d", X"96f", X"971", X"973", X"975",
X"976", X"978", X"97a", X"97c", X"97e", X"97f", X"981", X"983",
X"985", X"987", X"989", X"98b", X"98c", X"98e", X"990", X"992",
X"994", X"996", X"998", X"999", X"99b", X"99d", X"99f", X"9a1",
X"9a3", X"9a5", X"9a7", X"9a9", X"9ab", X"9ac", X"9ae", X"9b0",
X"9b2", X"9b4", X"9b6", X"9b8", X"9ba", X"9bc", X"9be", X"9c0",
X"9c2", X"9c4", X"9c6", X"9c8", X"9ca", X"9cc", X"9ce", X"9d0",
X"9d2", X"9d4", X"9d6", X"9d8", X"9da", X"9dc", X"9de", X"9e0",
X"9e2", X"9e4", X"9e6", X"9e8", X"9ea", X"9ec", X"9ee", X"9f0",
X"9f2", X"9f4", X"9f6", X"9f8", X"9fa", X"9fc", X"9fe", X"a00",
X"a03", X"a05", X"a07", X"a09", X"a0b", X"a0d", X"a0f", X"a11",
X"a13", X"a15", X"a17", X"a1a", X"a1c", X"a1e", X"a20", X"a22",
X"a24", X"a26", X"a29", X"a2b", X"a2d", X"a2f", X"a31", X"a33",
X"a35", X"a38", X"a3a", X"a3c", X"a3e", X"a40", X"a43", X"a45",
X"a47", X"a49", X"a4b", X"a4d", X"a50", X"a52", X"a54", X"a56",
X"a59", X"a5b", X"a5d", X"a5f", X"a61", X"a64", X"a66", X"a68",
X"a6a", X"a6d", X"a6f", X"a71", X"a73", X"a76", X"a78", X"a7a",
X"a7d", X"a7f", X"a81", X"a83", X"a86", X"a88", X"a8a", X"a8d",
X"a8f", X"a91", X"a93", X"a96", X"a98", X"a9a", X"a9d", X"a9f",
X"aa1", X"aa4", X"aa6", X"aa8", X"aab", X"aad", X"aaf", X"ab2",
X"ab4", X"ab6", X"ab9", X"abb", X"abd", X"ac0", X"ac2", X"ac5",
X"ac7", X"ac9", X"acc", X"ace", X"ad0", X"ad3", X"ad5", X"ad8",
X"ada", X"adc", X"adf", X"ae1", X"ae4", X"ae6", X"ae9", X"aeb",
X"aed", X"af0", X"af2", X"af5", X"af7", X"afa", X"afc", X"afe",
X"b01", X"b03", X"b06", X"b08", X"b0b", X"b0d", X"b10", X"b12",
X"b15", X"b17", X"b1a", X"b1c", X"b1f", X"b21", X"b24", X"b26",
X"b29", X"b2b", X"b2e", X"b30", X"b33", X"b35", X"b38", X"b3a",
X"b3d", X"b3f", X"b42", X"b44", X"b47", X"b49", X"b4c", X"b4e",
X"b51", X"b53", X"b56", X"b59", X"b5b", X"b5e", X"b60", X"b63",
X"b65", X"b68", X"b6a", X"b6d", X"b70", X"b72", X"b75", X"b77",
X"b7a", X"b7d", X"b7f", X"b82", X"b84", X"b87", X"b8a", X"b8c",
X"b8f", X"b91", X"b94", X"b97", X"b99", X"b9c", X"b9e", X"ba1",
X"ba4", X"ba6", X"ba9", X"bac", X"bae", X"bb1", X"bb4", X"bb6",
X"bb9", X"bbc", X"bbe", X"bc1", X"bc3", X"bc6", X"bc9", X"bcb",
X"bce", X"bd1", X"bd4", X"bd6", X"bd9", X"bdc", X"bde", X"be1",
X"be4", X"be6", X"be9", X"bec", X"bee", X"bf1", X"bf4", X"bf7",
X"bf9", X"bfc", X"bff", X"c01", X"c04", X"c07", X"c0a", X"c0c",
X"c0f", X"c12", X"c15", X"c17", X"c1a", X"c1d", X"c1f", X"c22",
X"c25", X"c28", X"c2a", X"c2d", X"c30", X"c33", X"c36", X"c38",
X"c3b", X"c3e", X"c41", X"c43", X"c46", X"c49", X"c4c", X"c4e",
X"c51", X"c54", X"c57", X"c5a", X"c5c", X"c5f", X"c62", X"c65",
X"c68", X"c6a", X"c6d", X"c70", X"c73", X"c76", X"c79", X"c7b",
X"c7e", X"c81", X"c84", X"c87", X"c89", X"c8c", X"c8f", X"c92",
X"c95", X"c98", X"c9a", X"c9d", X"ca0", X"ca3", X"ca6", X"ca9",
X"cac", X"cae", X"cb1", X"cb4", X"cb7", X"cba", X"cbd", X"cc0",
X"cc2", X"cc5", X"cc8", X"ccb", X"cce", X"cd1", X"cd4", X"cd7",
X"cd9", X"cdc", X"cdf", X"ce2", X"ce5", X"ce8", X"ceb", X"cee",
X"cf1", X"cf4", X"cf6", X"cf9", X"cfc", X"cff", X"d02", X"d05",
X"d08", X"d0b", X"d0e", X"d11", X"d14", X"d17", X"d19", X"d1c",
X"d1f", X"d22", X"d25", X"d28", X"d2b", X"d2e", X"d31", X"d34",
X"d37", X"d3a", X"d3d", X"d40", X"d43", X"d46", X"d48", X"d4b",
X"d4e", X"d51", X"d54", X"d57", X"d5a", X"d5d", X"d60", X"d63",
X"d66", X"d69", X"d6c", X"d6f", X"d72", X"d75", X"d78", X"d7b",
X"d7e", X"d81", X"d84", X"d87", X"d8a", X"d8d", X"d90", X"d93",
X"d96", X"d99", X"d9c", X"d9f", X"da2", X"da5", X"da8", X"dab",
X"dae", X"db1", X"db4", X"db7", X"dba", X"dbd", X"dc0", X"dc3",
X"dc6", X"dc9", X"dcc", X"dcf", X"dd2", X"dd5", X"dd8", X"ddb",
X"dde", X"de1", X"de4", X"de7", X"dea", X"ded", X"df0", X"df3",
X"df6", X"df9", X"dfc", X"dff", X"e02", X"e05", X"e09", X"e0c",
X"e0f", X"e12", X"e15", X"e18", X"e1b", X"e1e", X"e21", X"e24",
X"e27", X"e2a", X"e2d", X"e30", X"e33", X"e36", X"e39", X"e3c",
X"e3f", X"e43", X"e46", X"e49", X"e4c", X"e4f", X"e52", X"e55",
X"e58", X"e5b", X"e5e", X"e61", X"e64", X"e67", X"e6a", X"e6e",
X"e71", X"e74", X"e77", X"e7a", X"e7d", X"e80", X"e83", X"e86",
X"e89", X"e8c", X"e8f", X"e93", X"e96", X"e99", X"e9c", X"e9f",
X"ea2", X"ea5", X"ea8", X"eab", X"eae", X"eb2", X"eb5", X"eb8",
X"ebb", X"ebe", X"ec1", X"ec4", X"ec7", X"eca", X"ecd", X"ed1",
X"ed4", X"ed7", X"eda", X"edd", X"ee0", X"ee3", X"ee6", X"ee9",
X"eed", X"ef0", X"ef3", X"ef6", X"ef9", X"efc", X"eff", X"f02",
X"f05", X"f09", X"f0c", X"f0f", X"f12", X"f15", X"f18", X"f1b",
X"f1e", X"f21", X"f25", X"f28", X"f2b", X"f2e", X"f31", X"f34",
X"f37", X"f3a", X"f3e", X"f41", X"f44", X"f47", X"f4a", X"f4d",
X"f50", X"f54", X"f57", X"f5a", X"f5d", X"f60", X"f63", X"f66",
X"f69", X"f6d", X"f70", X"f73", X"f76", X"f79", X"f7c", X"f7f",
X"f82", X"f86", X"f89", X"f8c", X"f8f", X"f92", X"f95", X"f98",
X"f9c", X"f9f", X"fa2", X"fa5", X"fa8", X"fab", X"fae", X"fb2",
X"fb5", X"fb8", X"fbb", X"fbe", X"fc1", X"fc4", X"fc7", X"fcb",
X"fce", X"fd1", X"fd4", X"fd7", X"fda", X"fdd", X"fe1", X"fe4",
X"fe7", X"fea", X"fed", X"ff0", X"ff3", X"ff7", X"ffa", X"ffd",
X"000", X"003", X"006", X"009", X"00d", X"010", X"013", X"016",
X"019", X"01c", X"01f", X"023", X"026", X"029", X"02c", X"02f",
X"032", X"035", X"039", X"03c", X"03f", X"042", X"045", X"048",
X"04b", X"04e", X"052", X"055", X"058", X"05b", X"05e", X"061",
X"064", X"068", X"06b", X"06e", X"071", X"074", X"077", X"07a",
X"07e", X"081", X"084", X"087", X"08a", X"08d", X"090", X"093",
X"097", X"09a", X"09d", X"0a0", X"0a3", X"0a6", X"0a9", X"0ac",
X"0b0", X"0b3", X"0b6", X"0b9", X"0bc", X"0bf", X"0c2", X"0c6",
X"0c9", X"0cc", X"0cf", X"0d2", X"0d5", X"0d8", X"0db", X"0df",
X"0e2", X"0e5", X"0e8", X"0eb", X"0ee", X"0f1", X"0f4", X"0f7",
X"0fb", X"0fe", X"101", X"104", X"107", X"10a", X"10d", X"110",
X"113", X"117", X"11a", X"11d", X"120", X"123", X"126", X"129",
X"12c", X"12f", X"133", X"136", X"139", X"13c", X"13f", X"142",
X"145", X"148", X"14b", X"14e", X"152", X"155", X"158", X"15b",
X"15e", X"161", X"164", X"167", X"16a", X"16d", X"171", X"174",
X"177", X"17a", X"17d", X"180", X"183", X"186", X"189", X"18c",
X"18f", X"192", X"196", X"199", X"19c", X"19f", X"1a2", X"1a5",
X"1a8", X"1ab", X"1ae", X"1b1", X"1b4", X"1b7", X"1ba", X"1bd",
X"1c1", X"1c4", X"1c7", X"1ca", X"1cd", X"1d0", X"1d3", X"1d6",
X"1d9", X"1dc", X"1df", X"1e2", X"1e5", X"1e8", X"1eb", X"1ee",
X"1f1", X"1f4", X"1f7", X"1fb", X"1fe", X"201", X"204", X"207",
X"20a", X"20d", X"210", X"213", X"216", X"219", X"21c", X"21f",
X"222", X"225", X"228", X"22b", X"22e", X"231", X"234", X"237",
X"23a", X"23d", X"240", X"243", X"246", X"249", X"24c", X"24f",
X"252", X"255", X"258", X"25b", X"25e", X"261", X"264", X"267",
X"26a", X"26d", X"270", X"273", X"276", X"279", X"27c", X"27f",
X"282", X"285", X"288", X"28b", X"28e", X"291", X"294", X"297",
X"29a", X"29d", X"2a0", X"2a3", X"2a6", X"2a9", X"2ac", X"2af",
X"2b2", X"2b5", X"2b8", X"2ba", X"2bd", X"2c0", X"2c3", X"2c6",
X"2c9", X"2cc", X"2cf", X"2d2", X"2d5", X"2d8", X"2db", X"2de",
X"2e1", X"2e4", X"2e7", X"2e9", X"2ec", X"2ef", X"2f2", X"2f5",
X"2f8", X"2fb", X"2fe", X"301", X"304", X"307", X"30a", X"30c",
X"30f", X"312", X"315", X"318", X"31b", X"31e", X"321", X"324",
X"327", X"329", X"32c", X"32f", X"332", X"335", X"338", X"33b",
X"33e", X"340", X"343", X"346", X"349", X"34c", X"34f", X"352",
X"354", X"357", X"35a", X"35d", X"360", X"363", X"366", X"368",
X"36b", X"36e", X"371", X"374", X"377", X"379", X"37c", X"37f",
X"382", X"385", X"387", X"38a", X"38d", X"390", X"393", X"396",
X"398", X"39b", X"39e", X"3a1", X"3a4", X"3a6", X"3a9", X"3ac",
X"3af", X"3b2", X"3b4", X"3b7", X"3ba", X"3bd", X"3bf", X"3c2",
X"3c5", X"3c8", X"3ca", X"3cd", X"3d0", X"3d3", X"3d6", X"3d8",
X"3db", X"3de", X"3e1", X"3e3", X"3e6", X"3e9", X"3eb", X"3ee",
X"3f1", X"3f4", X"3f6", X"3f9", X"3fc", X"3ff", X"401", X"404",
X"407", X"409", X"40c", X"40f", X"412", X"414", X"417", X"41a",
X"41c", X"41f", X"422", X"424", X"427", X"42a", X"42c", X"42f",
X"432", X"435", X"437", X"43a", X"43d", X"43f", X"442", X"444",
X"447", X"44a", X"44c", X"44f", X"452", X"454", X"457", X"45a",
X"45c", X"45f", X"462", X"464", X"467", X"469", X"46c", X"46f",
X"471", X"474", X"476", X"479", X"47c", X"47e", X"481", X"483",
X"486", X"489", X"48b", X"48e", X"490", X"493", X"496", X"498",
X"49b", X"49d", X"4a0", X"4a2", X"4a5", X"4a7", X"4aa", X"4ad",
X"4af", X"4b2", X"4b4", X"4b7", X"4b9", X"4bc", X"4be", X"4c1",
X"4c3", X"4c6", X"4c8", X"4cb", X"4cd", X"4d0", X"4d2", X"4d5",
X"4d7", X"4da", X"4dc", X"4df", X"4e1", X"4e4", X"4e6", X"4e9",
X"4eb", X"4ee", X"4f0", X"4f3", X"4f5", X"4f8", X"4fa", X"4fd",
X"4ff", X"502", X"504", X"506", X"509", X"50b", X"50e", X"510",
X"513", X"515", X"517", X"51a", X"51c", X"51f", X"521", X"524",
X"526", X"528", X"52b", X"52d", X"530", X"532", X"534", X"537",
X"539", X"53b", X"53e", X"540", X"543", X"545", X"547", X"54a",
X"54c", X"54e", X"551", X"553", X"555", X"558", X"55a", X"55c",
X"55f", X"561", X"563", X"566", X"568", X"56a", X"56d", X"56f",
X"571", X"573", X"576", X"578", X"57a", X"57d", X"57f", X"581",
X"583", X"586", X"588", X"58a", X"58d", X"58f", X"591", X"593",
X"596", X"598", X"59a", X"59c", X"59f", X"5a1", X"5a3", X"5a5",
X"5a7", X"5aa", X"5ac", X"5ae", X"5b0", X"5b3", X"5b5", X"5b7",
X"5b9", X"5bb", X"5bd", X"5c0", X"5c2", X"5c4", X"5c6", X"5c8",
X"5cb", X"5cd", X"5cf", X"5d1", X"5d3", X"5d5", X"5d7", X"5da",
X"5dc", X"5de", X"5e0", X"5e2", X"5e4", X"5e6", X"5e9", X"5eb",
X"5ed", X"5ef", X"5f1", X"5f3", X"5f5", X"5f7", X"5f9", X"5fb",
X"5fd", X"600", X"602", X"604", X"606", X"608", X"60a", X"60c",
X"60e", X"610", X"612", X"614", X"616", X"618", X"61a", X"61c",
X"61e", X"620", X"622", X"624", X"626", X"628", X"62a", X"62c",
X"62e", X"630", X"632", X"634", X"636", X"638", X"63a", X"63c",
X"63e", X"640", X"642", X"644", X"646", X"648", X"64a", X"64c",
X"64e", X"650", X"652", X"654", X"655", X"657", X"659", X"65b",
X"65d", X"65f", X"661", X"663", X"665", X"667", X"668", X"66a",
X"66c", X"66e", X"670", X"672", X"674", X"675", X"677", X"679",
X"67b", X"67d", X"67f", X"681", X"682", X"684", X"686", X"688",
X"68a", X"68b", X"68d", X"68f", X"691", X"693", X"694", X"696",
X"698", X"69a", X"69b", X"69d", X"69f", X"6a1", X"6a3", X"6a4",
X"6a6", X"6a8", X"6a9", X"6ab", X"6ad", X"6af", X"6b0", X"6b2",
X"6b4", X"6b6", X"6b7", X"6b9", X"6bb", X"6bc", X"6be", X"6c0",
X"6c1", X"6c3", X"6c5", X"6c6", X"6c8", X"6ca", X"6cb", X"6cd",
X"6cf", X"6d0", X"6d2", X"6d4", X"6d5", X"6d7", X"6d9", X"6da",
X"6dc", X"6dd", X"6df", X"6e1", X"6e2", X"6e4", X"6e5", X"6e7",
X"6e9", X"6ea", X"6ec", X"6ed", X"6ef", X"6f0", X"6f2", X"6f4",
X"6f5", X"6f7", X"6f8", X"6fa", X"6fb", X"6fd", X"6fe", X"700",
X"701", X"703", X"704", X"706", X"707", X"709", X"70a", X"70c",
X"70d", X"70f", X"710", X"712", X"713", X"715", X"716", X"718",
X"719", X"71a", X"71c", X"71d", X"71f", X"720", X"722", X"723",
X"724", X"726", X"727", X"729", X"72a", X"72b", X"72d", X"72e",
X"730", X"731", X"732", X"734", X"735", X"736", X"738", X"739",
X"73a", X"73c", X"73d", X"73e", X"740", X"741", X"742", X"744",
X"745", X"746", X"748", X"749", X"74a", X"74c", X"74d", X"74e",
X"74f", X"751", X"752", X"753", X"754", X"756", X"757", X"758",
X"759", X"75b", X"75c", X"75d", X"75e", X"760", X"761", X"762",
X"763", X"764", X"766", X"767", X"768", X"769", X"76a", X"76b",
X"76d", X"76e", X"76f", X"770", X"771", X"772", X"774", X"775",
X"776", X"777", X"778", X"779", X"77a", X"77b", X"77d", X"77e",
X"77f", X"780", X"781", X"782", X"783", X"784", X"785", X"786",
X"787", X"788", X"789", X"78a", X"78c", X"78d", X"78e", X"78f",
X"790", X"791", X"792", X"793", X"794", X"795", X"796", X"797",
X"798", X"799", X"79a", X"79b", X"79c", X"79d", X"79e", X"79e",
X"79f", X"7a0", X"7a1", X"7a2", X"7a3", X"7a4", X"7a5", X"7a6",
X"7a7", X"7a8", X"7a9", X"7aa", X"7aa", X"7ab", X"7ac", X"7ad",
X"7ae", X"7af", X"7b0", X"7b1", X"7b1", X"7b2", X"7b3", X"7b4",
X"7b5", X"7b6", X"7b7", X"7b7", X"7b8", X"7b9", X"7ba", X"7bb",
X"7bb", X"7bc", X"7bd", X"7be", X"7bf", X"7bf", X"7c0", X"7c1",
X"7c2", X"7c2", X"7c3", X"7c4", X"7c5", X"7c5", X"7c6", X"7c7",
X"7c8", X"7c8", X"7c9", X"7ca", X"7ca", X"7cb", X"7cc", X"7cd",
X"7cd", X"7ce", X"7cf", X"7cf", X"7d0", X"7d1", X"7d1", X"7d2",
X"7d3", X"7d3", X"7d4", X"7d5", X"7d5", X"7d6", X"7d6", X"7d7",
X"7d8", X"7d8", X"7d9", X"7d9", X"7da", X"7db", X"7db", X"7dc",
X"7dc", X"7dd", X"7de", X"7de", X"7df", X"7df", X"7e0", X"7e0",
X"7e1", X"7e1", X"7e2", X"7e2", X"7e3", X"7e3", X"7e4", X"7e5",
X"7e5", X"7e6", X"7e6", X"7e6", X"7e7", X"7e7", X"7e8", X"7e8",
X"7e9", X"7e9", X"7ea", X"7ea", X"7eb", X"7eb", X"7ec", X"7ec",
X"7ec", X"7ed", X"7ed", X"7ee", X"7ee", X"7ee", X"7ef", X"7ef",
X"7f0", X"7f0", X"7f0", X"7f1", X"7f1", X"7f1", X"7f2", X"7f2",
X"7f3", X"7f3", X"7f3", X"7f4", X"7f4", X"7f4", X"7f5", X"7f5",
X"7f5", X"7f5", X"7f6", X"7f6", X"7f6", X"7f7", X"7f7", X"7f7",
X"7f7", X"7f8", X"7f8", X"7f8", X"7f8", X"7f9", X"7f9", X"7f9",
X"7f9", X"7fa", X"7fa", X"7fa", X"7fa", X"7fb", X"7fb", X"7fb",
X"7fb", X"7fb", X"7fc", X"7fc", X"7fc", X"7fc", X"7fc", X"7fc",
X"7fd", X"7fd", X"7fd", X"7fd", X"7fd", X"7fd", X"7fd", X"7fd",
X"7fe", X"7fe", X"7fe", X"7fe", X"7fe", X"7fe", X"7fe", X"7fe",
X"7fe", X"7fe", X"7ff", X"7ff", X"7ff", X"7ff", X"7ff", X"7ff",
X"7ff", X"7ff", X"7ff", X"7ff", X"7ff", X"7ff", X"7ff", X"7ff"
);
begin
rom_select: process (clk)
begin
if clk'event and clk = '1' then
sin_out <= SIN_ROM(conv_integer(addr)) + 2048;
cos_out <= COS_ROM(conv_integer(addr)) + 2048;
end if;
end process rom_select;
end rtl; | mit | e042b3f9cd830a411842eed1182ff8ae | 0.487973 | 1.60317 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/tx_unit.vhd | 15 | 6,083 | ------------------------------------------------------------------------------
---- ----
---- RS-232 simple Tx module ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- Implements a simple 8N1 tx module for RS-232. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Philippe Carton, philippe.carton2 libertysurf.fr ----
---- - Juan Pablo Daniel Borgna, jpdborgna gmail.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2001-2003 Philippe Carton ----
---- Copyright (c) 2005 Juan Pablo Daniel Borgna ----
---- Copyright (c) 2005-2008 Salvador E. Tropea ----
---- Copyright (c) 2005-2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the GPL license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: TxUnit(Behaviour) (Entity and architecture) ----
---- File name: Txunit.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- zpu.UART ----
---- Target FPGA: Spartan ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity TxUnit is
port (
clk_i : in std_logic; -- Clock signal
reset_i : in std_logic; -- Reset input
enable_i : in std_logic; -- Enable input
load_i : in std_logic; -- Load input
txd_o : out std_logic; -- RS-232 data output
busy_o : out std_logic; -- Tx Busy
intx_o : out std_logic; -- In transmit
datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit
end entity TxUnit;
architecture Behaviour of TxUnit is
signal tbuff_r : std_logic_vector(7 downto 0); -- transmit buffer
signal t_r : std_logic_vector(7 downto 0); -- transmit register
signal loaded_r : std_logic:='0'; -- Buffer loaded
signal txd_r : std_logic:='1'; -- Tx buffer ready
signal idle : std_logic;
begin
busy_o <= load_i or loaded_r;
txd_o <= txd_r;
-- Tx process
TxProc:
process (clk_i)
variable bitpos : integer range 0 to 10; -- Bit position in the frame
begin
if rising_edge(clk_i) then
if reset_i='1' then
loaded_r <= '0';
bitpos:=0;
txd_r <= '1';
intx_o <= '0';
idle <= '1';
else -- reset_i='0'
if load_i='1' then
tbuff_r <= datai_i;
loaded_r <= '1';
end if;
if enable_i='1' then
case bitpos is
when 0 => -- idle or stop bit
txd_r <= '1';
if loaded_r='1' then -- start transmit. next is start bit
t_r <= tbuff_r;
loaded_r <= '0';
intx_o <= '1';
bitpos:=1;
idle <= '0';
else
if idle='0' then
idle<='1';
end if;
if idle='1' then
intx_o <= '0';
end if;
end if;
when 1 => -- Start bit
txd_r <= '0';
bitpos:=2;
when others =>
txd_r <= t_r(bitpos-2); -- Serialisation of t_r
bitpos:=bitpos+1;
end case;
if bitpos=10 then -- bit8. next is stop bit
bitpos:=0;
end if;
end if; -- enable_i='1'
end if; -- reset_i='0'
end if; -- rising_edge(clk_i)
end process TxProc;
end architecture Behaviour;
| mit | 255236036a100677dce1ce9bcd09c873 | 0.294591 | 5.490072 | false | false | false | false |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/KeyboardCtrl_0/KeyboardCtrl_0_sim_netlist.vhdl | 1 | 78,353 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.2 (win64) Build 1577090 Thu Jun 2 16:32:40 MDT 2016
-- Date : Tue Dec 13 22:50:05 2016
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- d:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/KeyboardCtrl_0/KeyboardCtrl_0_sim_netlist.vhdl
-- Design : KeyboardCtrl_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity KeyboardCtrl_0_Ps2Interface is
port (
rx_valid : out STD_LOGIC;
err : out STD_LOGIC;
is_extend_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
tx_valid : out STD_LOGIC;
is_break_reg : out STD_LOGIC;
valid_reg : out STD_LOGIC;
PS2_CLK : inout STD_LOGIC;
PS2_DATA : inout STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
is_extend : in STD_LOGIC;
tx_valid_reg : in STD_LOGIC;
\tx_data_reg[2]\ : in STD_LOGIC;
\tx_data_reg[7]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of KeyboardCtrl_0_Ps2Interface : entity is "Ps2Interface";
end KeyboardCtrl_0_Ps2Interface;
architecture STRUCTURE of KeyboardCtrl_0_Ps2Interface is
signal \FSM_onehot_state[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[0]_i_2_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[0]_i_3_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[0]_i_4_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[0]_i_5_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[10]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[10]_i_2_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[10]_i_3_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[11]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[11]_i_2_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[11]_i_3_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[12]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[12]_i_2_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[13]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[14]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[14]_i_2_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[2]_i_2_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[3]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[4]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[4]_i_2_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[5]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[5]_i_2_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[5]_i_3_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[5]_i_4_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[6]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[6]_i_2_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[6]_i_3_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[6]_i_4_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[7]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[8]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[8]_i_2_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[8]_i_3_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[8]_i_4_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[8]_i_5_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[8]_i_6_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[9]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state_reg_n_0_[0]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[0]\ : signal is "yes";
signal \FSM_onehot_state_reg_n_0_[10]\ : STD_LOGIC;
attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[10]\ : signal is "yes";
signal \FSM_onehot_state_reg_n_0_[11]\ : STD_LOGIC;
attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[11]\ : signal is "yes";
signal \FSM_onehot_state_reg_n_0_[12]\ : STD_LOGIC;
attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[12]\ : signal is "yes";
signal \FSM_onehot_state_reg_n_0_[13]\ : STD_LOGIC;
attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[13]\ : signal is "yes";
signal \FSM_onehot_state_reg_n_0_[14]\ : STD_LOGIC;
attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[14]\ : signal is "yes";
signal \FSM_onehot_state_reg_n_0_[1]\ : STD_LOGIC;
attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[1]\ : signal is "yes";
signal \FSM_onehot_state_reg_n_0_[2]\ : STD_LOGIC;
attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[2]\ : signal is "yes";
signal \FSM_onehot_state_reg_n_0_[3]\ : STD_LOGIC;
attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[3]\ : signal is "yes";
signal \FSM_onehot_state_reg_n_0_[4]\ : STD_LOGIC;
attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[4]\ : signal is "yes";
signal \FSM_onehot_state_reg_n_0_[5]\ : STD_LOGIC;
attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[5]\ : signal is "yes";
signal \FSM_onehot_state_reg_n_0_[6]\ : STD_LOGIC;
attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[6]\ : signal is "yes";
signal \FSM_onehot_state_reg_n_0_[7]\ : STD_LOGIC;
attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[7]\ : signal is "yes";
signal \FSM_onehot_state_reg_n_0_[9]\ : STD_LOGIC;
attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[9]\ : signal is "yes";
signal \FSM_sequential_state[0]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_state[0]_i_3_n_0\ : STD_LOGIC;
signal \FSM_sequential_state[1]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_state[1]_i_3_n_0\ : STD_LOGIC;
signal \FSM_sequential_state[2]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_state[2]_i_3_n_0\ : STD_LOGIC;
signal \FSM_sequential_state[2]_i_6_n_0\ : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal T0 : STD_LOGIC;
signal bits_count : STD_LOGIC;
signal \bits_count[0]_i_1_n_0\ : STD_LOGIC;
signal \bits_count[1]_i_1_n_0\ : STD_LOGIC;
signal \bits_count[2]_i_1_n_0\ : STD_LOGIC;
signal \bits_count[3]_i_2_n_0\ : STD_LOGIC;
signal \bits_count_reg_n_0_[0]\ : STD_LOGIC;
signal \bits_count_reg_n_0_[1]\ : STD_LOGIC;
signal \bits_count_reg_n_0_[2]\ : STD_LOGIC;
signal \bits_count_reg_n_0_[3]\ : STD_LOGIC;
signal clk_count : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \clk_count[0]_i_1_n_0\ : STD_LOGIC;
signal \clk_count[1]_i_1_n_0\ : STD_LOGIC;
signal \clk_count[2]_i_1_n_0\ : STD_LOGIC;
signal \clk_count[3]_i_1_n_0\ : STD_LOGIC;
signal clk_inter : STD_LOGIC;
signal counter : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \counter[0]_i_2_n_0\ : STD_LOGIC;
signal \counter[0]_i_3_n_0\ : STD_LOGIC;
signal \counter[0]_i_4_n_0\ : STD_LOGIC;
signal \counter[0]_i_5_n_0\ : STD_LOGIC;
signal \counter[0]_i_6_n_0\ : STD_LOGIC;
signal \counter[10]_i_2_n_0\ : STD_LOGIC;
signal \counter[11]_i_2_n_0\ : STD_LOGIC;
signal \counter[12]_i_2_n_0\ : STD_LOGIC;
signal \counter[13]_i_10_n_0\ : STD_LOGIC;
signal \counter[13]_i_11_n_0\ : STD_LOGIC;
signal \counter[13]_i_12_n_0\ : STD_LOGIC;
signal \counter[13]_i_2_n_0\ : STD_LOGIC;
signal \counter[13]_i_3_n_0\ : STD_LOGIC;
signal \counter[13]_i_4_n_0\ : STD_LOGIC;
signal \counter[13]_i_6_n_0\ : STD_LOGIC;
signal \counter[13]_i_7_n_0\ : STD_LOGIC;
signal \counter[13]_i_8_n_0\ : STD_LOGIC;
signal \counter[1]_i_2_n_0\ : STD_LOGIC;
signal \counter[2]_i_2_n_0\ : STD_LOGIC;
signal \counter[3]_i_2_n_0\ : STD_LOGIC;
signal \counter[4]_i_2_n_0\ : STD_LOGIC;
signal \counter[5]_i_2_n_0\ : STD_LOGIC;
signal \counter[6]_i_2_n_0\ : STD_LOGIC;
signal \counter[7]_i_2_n_0\ : STD_LOGIC;
signal \counter[8]_i_2_n_0\ : STD_LOGIC;
signal \counter[9]_i_2_n_0\ : STD_LOGIC;
signal counter_next : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \counter_reg[12]_i_3_n_0\ : STD_LOGIC;
signal \counter_reg[12]_i_3_n_1\ : STD_LOGIC;
signal \counter_reg[12]_i_3_n_2\ : STD_LOGIC;
signal \counter_reg[12]_i_3_n_3\ : STD_LOGIC;
signal \counter_reg[4]_i_3_n_0\ : STD_LOGIC;
signal \counter_reg[4]_i_3_n_1\ : STD_LOGIC;
signal \counter_reg[4]_i_3_n_2\ : STD_LOGIC;
signal \counter_reg[4]_i_3_n_3\ : STD_LOGIC;
signal \counter_reg[8]_i_3_n_0\ : STD_LOGIC;
signal \counter_reg[8]_i_3_n_1\ : STD_LOGIC;
signal \counter_reg[8]_i_3_n_2\ : STD_LOGIC;
signal \counter_reg[8]_i_3_n_3\ : STD_LOGIC;
signal data1 : STD_LOGIC_VECTOR ( 13 downto 1 );
signal data_count : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \data_count[0]_i_1_n_0\ : STD_LOGIC;
signal \data_count[1]_i_1_n_0\ : STD_LOGIC;
signal \data_count[2]_i_1_n_0\ : STD_LOGIC;
signal \data_count[3]_i_1_n_0\ : STD_LOGIC;
signal data_inter : STD_LOGIC;
signal \^err\ : STD_LOGIC;
signal err_i_2_n_0 : STD_LOGIC;
signal err_i_3_n_0 : STD_LOGIC;
signal err_next : STD_LOGIC;
signal \frame[10]_i_1_n_0\ : STD_LOGIC;
signal \frame_reg_n_0_[0]\ : STD_LOGIC;
signal \frame_reg_n_0_[10]\ : STD_LOGIC;
signal \frame_reg_n_0_[1]\ : STD_LOGIC;
signal \frame_reg_n_0_[2]\ : STD_LOGIC;
signal \frame_reg_n_0_[3]\ : STD_LOGIC;
signal \frame_reg_n_0_[4]\ : STD_LOGIC;
signal \frame_reg_n_0_[5]\ : STD_LOGIC;
signal \frame_reg_n_0_[6]\ : STD_LOGIC;
signal \frame_reg_n_0_[7]\ : STD_LOGIC;
signal \frame_reg_n_0_[8]\ : STD_LOGIC;
signal \frame_reg_n_0_[9]\ : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 10 downto 0 );
signal p_1_in_0 : STD_LOGIC;
attribute RTL_KEEP of p_1_in_0 : signal is "yes";
signal ps2_clk_en_next : STD_LOGIC;
signal ps2_clk_in : STD_LOGIC;
signal ps2_clk_out : STD_LOGIC;
signal ps2_clk_out_i_2_n_0 : STD_LOGIC;
signal ps2_clk_out_next : STD_LOGIC;
signal ps2_clk_s : STD_LOGIC;
signal ps2_clk_s_i_1_n_0 : STD_LOGIC;
signal ps2_data_en_inv_i_2_n_0 : STD_LOGIC;
signal ps2_data_en_next : STD_LOGIC;
signal ps2_data_en_reg_inv_n_0 : STD_LOGIC;
signal ps2_data_in : STD_LOGIC;
signal ps2_data_out : STD_LOGIC;
signal ps2_data_out_next : STD_LOGIC;
signal ps2_data_s : STD_LOGIC;
signal ps2_data_s_i_1_n_0 : STD_LOGIC;
signal ps2_data_s_reg_n_0 : STD_LOGIC;
signal \rx_data[7]_i_2_n_0\ : STD_LOGIC;
signal rx_finish : STD_LOGIC;
signal \^rx_valid\ : STD_LOGIC;
signal state1 : STD_LOGIC;
signal state110_out : STD_LOGIC;
signal state17_out : STD_LOGIC;
signal state_next1 : STD_LOGIC;
signal valid_i_2_n_0 : STD_LOGIC;
signal valid_i_3_n_0 : STD_LOGIC;
signal \NLW_counter_reg[13]_i_5_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_counter_reg[13]_i_5_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \FSM_onehot_state[10]_i_3\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \FSM_onehot_state[11]_i_2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \FSM_onehot_state[4]_i_2\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \FSM_onehot_state[5]_i_4\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \FSM_onehot_state[6]_i_3\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \FSM_onehot_state[6]_i_4\ : label is "soft_lutpair3";
attribute KEEP : string;
attribute KEEP of \FSM_onehot_state_reg[0]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[10]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[11]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[12]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[13]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[14]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[1]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[2]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[3]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[4]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[5]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[6]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[7]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[8]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[9]\ : label is "yes";
attribute SOFT_HLUTNM of \FSM_sequential_state[0]_i_3\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \FSM_sequential_state[1]_i_3\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \FSM_sequential_state[1]_i_4\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \FSM_sequential_state[2]_i_6\ : label is "soft_lutpair1";
attribute BOX_TYPE : string;
attribute BOX_TYPE of IOBUF_inst_0 : label is "PRIMITIVE";
attribute BOX_TYPE of IOBUF_inst_1 : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \counter[0]_i_5\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \counter[0]_i_6\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \counter[13]_i_12\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of err_i_2 : label is "soft_lutpair6";
attribute SOFT_HLUTNM of is_break_i_1 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of is_extend_i_1 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of valid_i_2 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of valid_i_3 : label is "soft_lutpair1";
begin
Q(7 downto 0) <= \^q\(7 downto 0);
err <= \^err\;
rx_valid <= \^rx_valid\;
\FSM_onehot_state[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEAEFFFFEEAAEEAA"
)
port map (
I0 => \FSM_onehot_state[0]_i_2_n_0\,
I1 => state_next1,
I2 => \FSM_onehot_state[0]_i_3_n_0\,
I3 => \FSM_onehot_state[0]_i_4_n_0\,
I4 => \FSM_onehot_state[0]_i_5_n_0\,
I5 => \FSM_onehot_state[12]_i_2_n_0\,
O => \FSM_onehot_state[0]_i_1_n_0\
);
\FSM_onehot_state[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000100"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[2]\,
I1 => \FSM_onehot_state_reg_n_0_[0]\,
I2 => \FSM_onehot_state_reg_n_0_[3]\,
I3 => \FSM_onehot_state_reg_n_0_[4]\,
I4 => \FSM_onehot_state[4]_i_2_n_0\,
O => \FSM_onehot_state[0]_i_2_n_0\
);
\FSM_onehot_state[0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[10]\,
I1 => \FSM_onehot_state_reg_n_0_[12]\,
O => \FSM_onehot_state[0]_i_3_n_0\
);
\FSM_onehot_state[0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[0]\,
I1 => tx_valid_reg,
O => \FSM_onehot_state[0]_i_4_n_0\
);
\FSM_onehot_state[0]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[13]\,
I1 => \FSM_onehot_state_reg_n_0_[10]\,
I2 => \FSM_onehot_state_reg_n_0_[12]\,
I3 => \FSM_onehot_state_reg_n_0_[14]\,
O => \FSM_onehot_state[0]_i_5_n_0\
);
\FSM_onehot_state[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888888888F88888"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[10]\,
I1 => \FSM_onehot_state[14]_i_2_n_0\,
I2 => \FSM_onehot_state[11]_i_3_n_0\,
I3 => \bits_count_reg_n_0_[0]\,
I4 => \FSM_onehot_state[10]_i_2_n_0\,
I5 => \FSM_onehot_state[10]_i_3_n_0\,
O => \FSM_onehot_state[10]_i_1_n_0\
);
\FSM_onehot_state[10]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[9]\,
I1 => p_1_in_0,
O => \FSM_onehot_state[10]_i_2_n_0\
);
\FSM_onehot_state[10]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => \bits_count_reg_n_0_[3]\,
I1 => \bits_count_reg_n_0_[2]\,
I2 => \bits_count_reg_n_0_[1]\,
O => \FSM_onehot_state[10]_i_3_n_0\
);
\FSM_onehot_state[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"080A080000000000"
)
port map (
I0 => state_next1,
I1 => \FSM_onehot_state[11]_i_2_n_0\,
I2 => p_1_in_0,
I3 => \FSM_onehot_state_reg_n_0_[9]\,
I4 => \FSM_onehot_state_reg_n_0_[11]\,
I5 => \FSM_onehot_state[11]_i_3_n_0\,
O => \FSM_onehot_state[11]_i_1_n_0\
);
\FSM_onehot_state[11]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \bits_count_reg_n_0_[1]\,
I1 => \bits_count_reg_n_0_[2]\,
I2 => \bits_count_reg_n_0_[3]\,
I3 => \bits_count_reg_n_0_[0]\,
O => \FSM_onehot_state[11]_i_2_n_0\
);
\FSM_onehot_state[11]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \FSM_onehot_state[8]_i_3_n_0\,
I1 => \FSM_onehot_state_reg_n_0_[7]\,
I2 => \FSM_onehot_state_reg_n_0_[6]\,
O => \FSM_onehot_state[11]_i_3_n_0\
);
\FSM_onehot_state[12]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A800"
)
port map (
I0 => state_next1,
I1 => \FSM_onehot_state_reg_n_0_[10]\,
I2 => \FSM_onehot_state_reg_n_0_[12]\,
I3 => \FSM_onehot_state[12]_i_2_n_0\,
O => \FSM_onehot_state[12]_i_1_n_0\
);
\FSM_onehot_state[12]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \FSM_onehot_state[11]_i_3_n_0\,
I1 => \FSM_onehot_state_reg_n_0_[11]\,
I2 => p_1_in_0,
I3 => \FSM_onehot_state_reg_n_0_[9]\,
O => \FSM_onehot_state[12]_i_2_n_0\
);
\FSM_onehot_state[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000044C0"
)
port map (
I0 => ps2_data_s_reg_n_0,
I1 => \FSM_onehot_state[14]_i_2_n_0\,
I2 => \FSM_onehot_state_reg_n_0_[13]\,
I3 => \FSM_onehot_state_reg_n_0_[12]\,
I4 => \FSM_onehot_state_reg_n_0_[10]\,
O => \FSM_onehot_state[13]_i_1_n_0\
);
\FSM_onehot_state[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00008888000000C0"
)
port map (
I0 => ps2_data_s_reg_n_0,
I1 => \FSM_onehot_state[14]_i_2_n_0\,
I2 => \FSM_onehot_state_reg_n_0_[14]\,
I3 => \FSM_onehot_state_reg_n_0_[13]\,
I4 => \FSM_onehot_state_reg_n_0_[10]\,
I5 => \FSM_onehot_state_reg_n_0_[12]\,
O => \FSM_onehot_state[14]_i_1_n_0\
);
\FSM_onehot_state[14]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000100"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[9]\,
I1 => p_1_in_0,
I2 => \FSM_onehot_state_reg_n_0_[11]\,
I3 => \FSM_onehot_state[11]_i_3_n_0\,
I4 => state_next1,
O => \FSM_onehot_state[14]_i_2_n_0\
);
\FSM_onehot_state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88F88888"
)
port map (
I0 => tx_valid_reg,
I1 => \FSM_onehot_state_reg_n_0_[0]\,
I2 => \FSM_onehot_state_reg_n_0_[1]\,
I3 => \FSM_onehot_state[5]_i_3_n_0\,
I4 => \FSM_onehot_state[5]_i_2_n_0\,
O => \FSM_onehot_state[1]_i_1_n_0\
);
\FSM_onehot_state[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0022002200F20022"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[0]\,
I1 => tx_valid_reg,
I2 => \FSM_onehot_state[4]_i_2_n_0\,
I3 => state_next1,
I4 => \FSM_onehot_state_reg_n_0_[4]\,
I5 => \FSM_onehot_state[2]_i_2_n_0\,
O => \FSM_onehot_state[2]_i_1_n_0\
);
\FSM_onehot_state[2]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[2]\,
I1 => \FSM_onehot_state_reg_n_0_[0]\,
I2 => \FSM_onehot_state_reg_n_0_[3]\,
O => \FSM_onehot_state[2]_i_2_n_0\
);
\FSM_onehot_state[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2232"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[2]\,
I1 => \FSM_onehot_state_reg_n_0_[0]\,
I2 => \FSM_onehot_state_reg_n_0_[3]\,
I3 => state_next1,
O => \FSM_onehot_state[3]_i_1_n_0\
);
\FSM_onehot_state[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"1010100010001000"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[0]\,
I1 => \FSM_onehot_state_reg_n_0_[2]\,
I2 => state_next1,
I3 => \FSM_onehot_state_reg_n_0_[3]\,
I4 => \FSM_onehot_state[4]_i_2_n_0\,
I5 => \FSM_onehot_state_reg_n_0_[4]\,
O => \FSM_onehot_state[4]_i_1_n_0\
);
\FSM_onehot_state[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"DFFF"
)
port map (
I0 => \bits_count_reg_n_0_[1]\,
I1 => \bits_count_reg_n_0_[2]\,
I2 => \bits_count_reg_n_0_[3]\,
I3 => \bits_count_reg_n_0_[0]\,
O => \FSM_onehot_state[4]_i_2_n_0\
);
\FSM_onehot_state[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"005C0050"
)
port map (
I0 => \FSM_onehot_state[5]_i_2_n_0\,
I1 => \FSM_onehot_state_reg_n_0_[5]\,
I2 => \FSM_onehot_state_reg_n_0_[1]\,
I3 => \FSM_onehot_state[5]_i_3_n_0\,
I4 => \FSM_onehot_state[6]_i_3_n_0\,
O => \FSM_onehot_state[5]_i_1_n_0\
);
\FSM_onehot_state[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \counter[13]_i_2_n_0\,
I1 => \FSM_onehot_state[5]_i_4_n_0\,
I2 => counter(1),
I3 => counter(0),
I4 => counter(3),
I5 => counter(2),
O => \FSM_onehot_state[5]_i_2_n_0\
);
\FSM_onehot_state[5]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[3]\,
I1 => \FSM_onehot_state_reg_n_0_[0]\,
I2 => \FSM_onehot_state_reg_n_0_[2]\,
I3 => \FSM_onehot_state_reg_n_0_[4]\,
O => \FSM_onehot_state[5]_i_3_n_0\
);
\FSM_onehot_state[5]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"DFFF"
)
port map (
I0 => counter(8),
I1 => counter(5),
I2 => counter(10),
I3 => counter(9),
O => \FSM_onehot_state[5]_i_4_n_0\
);
\FSM_onehot_state[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \FSM_onehot_state[6]_i_2_n_0\,
I1 => \FSM_onehot_state_reg_n_0_[5]\,
I2 => \FSM_onehot_state[6]_i_3_n_0\,
O => \FSM_onehot_state[6]_i_1_n_0\
);
\FSM_onehot_state[6]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[4]\,
I1 => \FSM_onehot_state_reg_n_0_[2]\,
I2 => \FSM_onehot_state_reg_n_0_[0]\,
I3 => \FSM_onehot_state_reg_n_0_[3]\,
I4 => \FSM_onehot_state_reg_n_0_[1]\,
O => \FSM_onehot_state[6]_i_2_n_0\
);
\FSM_onehot_state[6]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFFF"
)
port map (
I0 => \FSM_onehot_state[8]_i_5_n_0\,
I1 => \FSM_onehot_state[6]_i_4_n_0\,
I2 => counter(7),
I3 => counter(6),
O => \FSM_onehot_state[6]_i_3_n_0\
);
\FSM_onehot_state[6]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => counter(2),
I1 => counter(3),
I2 => counter(0),
I3 => counter(1),
I4 => \FSM_onehot_state[5]_i_4_n_0\,
O => \FSM_onehot_state[6]_i_4_n_0\
);
\FSM_onehot_state[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"C888"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[6]\,
I1 => \FSM_onehot_state[8]_i_3_n_0\,
I2 => \FSM_onehot_state_reg_n_0_[7]\,
I3 => \FSM_onehot_state[8]_i_2_n_0\,
O => \FSM_onehot_state[7]_i_1_n_0\
);
\FSM_onehot_state[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"004C0040"
)
port map (
I0 => \FSM_onehot_state[8]_i_2_n_0\,
I1 => \FSM_onehot_state[8]_i_3_n_0\,
I2 => \FSM_onehot_state_reg_n_0_[7]\,
I3 => \FSM_onehot_state_reg_n_0_[6]\,
I4 => \FSM_onehot_state[8]_i_4_n_0\,
O => \FSM_onehot_state[8]_i_1_n_0\
);
\FSM_onehot_state[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFBFFFFFFF"
)
port map (
I0 => \FSM_onehot_state[8]_i_5_n_0\,
I1 => counter(1),
I2 => counter(0),
I3 => counter(3),
I4 => counter(2),
I5 => \FSM_onehot_state[8]_i_6_n_0\,
O => \FSM_onehot_state[8]_i_2_n_0\
);
\FSM_onehot_state[8]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[1]\,
I1 => \FSM_onehot_state_reg_n_0_[3]\,
I2 => \FSM_onehot_state_reg_n_0_[0]\,
I3 => \FSM_onehot_state_reg_n_0_[2]\,
I4 => \FSM_onehot_state_reg_n_0_[4]\,
I5 => \FSM_onehot_state_reg_n_0_[5]\,
O => \FSM_onehot_state[8]_i_3_n_0\
);
\FSM_onehot_state[8]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0004"
)
port map (
I0 => state_next1,
I1 => \FSM_onehot_state_reg_n_0_[11]\,
I2 => \FSM_onehot_state_reg_n_0_[9]\,
I3 => p_1_in_0,
O => \FSM_onehot_state[8]_i_4_n_0\
);
\FSM_onehot_state[8]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFD"
)
port map (
I0 => counter(4),
I1 => counter(11),
I2 => counter(12),
I3 => counter(13),
O => \FSM_onehot_state[8]_i_5_n_0\
);
\FSM_onehot_state[8]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFEFF"
)
port map (
I0 => counter(9),
I1 => counter(10),
I2 => counter(8),
I3 => counter(5),
I4 => state_next1,
I5 => \counter[0]_i_6_n_0\,
O => \FSM_onehot_state[8]_i_6_n_0\
);
\FSM_onehot_state[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8C888888"
)
port map (
I0 => p_1_in_0,
I1 => \FSM_onehot_state[11]_i_3_n_0\,
I2 => state_next1,
I3 => \FSM_onehot_state_reg_n_0_[9]\,
I4 => \FSM_onehot_state[11]_i_2_n_0\,
O => \FSM_onehot_state[9]_i_1_n_0\
);
\FSM_onehot_state_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \FSM_onehot_state[0]_i_1_n_0\,
PRE => rst,
Q => \FSM_onehot_state_reg_n_0_[0]\
);
\FSM_onehot_state_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => rst,
D => \FSM_onehot_state[10]_i_1_n_0\,
Q => \FSM_onehot_state_reg_n_0_[10]\
);
\FSM_onehot_state_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => rst,
D => \FSM_onehot_state[11]_i_1_n_0\,
Q => \FSM_onehot_state_reg_n_0_[11]\
);
\FSM_onehot_state_reg[12]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => rst,
D => \FSM_onehot_state[12]_i_1_n_0\,
Q => \FSM_onehot_state_reg_n_0_[12]\
);
\FSM_onehot_state_reg[13]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => rst,
D => \FSM_onehot_state[13]_i_1_n_0\,
Q => \FSM_onehot_state_reg_n_0_[13]\
);
\FSM_onehot_state_reg[14]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => rst,
D => \FSM_onehot_state[14]_i_1_n_0\,
Q => \FSM_onehot_state_reg_n_0_[14]\
);
\FSM_onehot_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => rst,
D => \FSM_onehot_state[1]_i_1_n_0\,
Q => \FSM_onehot_state_reg_n_0_[1]\
);
\FSM_onehot_state_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => rst,
D => \FSM_onehot_state[2]_i_1_n_0\,
Q => \FSM_onehot_state_reg_n_0_[2]\
);
\FSM_onehot_state_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => rst,
D => \FSM_onehot_state[3]_i_1_n_0\,
Q => \FSM_onehot_state_reg_n_0_[3]\
);
\FSM_onehot_state_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => rst,
D => \FSM_onehot_state[4]_i_1_n_0\,
Q => \FSM_onehot_state_reg_n_0_[4]\
);
\FSM_onehot_state_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => rst,
D => \FSM_onehot_state[5]_i_1_n_0\,
Q => \FSM_onehot_state_reg_n_0_[5]\
);
\FSM_onehot_state_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => rst,
D => \FSM_onehot_state[6]_i_1_n_0\,
Q => \FSM_onehot_state_reg_n_0_[6]\
);
\FSM_onehot_state_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => rst,
D => \FSM_onehot_state[7]_i_1_n_0\,
Q => \FSM_onehot_state_reg_n_0_[7]\
);
\FSM_onehot_state_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => rst,
D => \FSM_onehot_state[8]_i_1_n_0\,
Q => p_1_in_0
);
\FSM_onehot_state_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => rst,
D => \FSM_onehot_state[9]_i_1_n_0\,
Q => \FSM_onehot_state_reg_n_0_[9]\
);
\FSM_sequential_state[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0FFF000F077F077"
)
port map (
I0 => \out\(0),
I1 => \FSM_onehot_state_reg_n_0_[0]\,
I2 => \FSM_sequential_state[0]_i_2_n_0\,
I3 => \out\(2),
I4 => \FSM_sequential_state[0]_i_3_n_0\,
I5 => \out\(1),
O => D(0)
);
\FSM_sequential_state[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000550202"
)
port map (
I0 => \^rx_valid\,
I1 => \^q\(4),
I2 => valid_i_2_n_0,
I3 => \^err\,
I4 => \out\(0),
I5 => \out\(1),
O => \FSM_sequential_state[0]_i_2_n_0\
);
\FSM_sequential_state[0]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"0F001010"
)
port map (
I0 => \^err\,
I1 => state1,
I2 => \out\(0),
I3 => state110_out,
I4 => \^rx_valid\,
O => \FSM_sequential_state[0]_i_3_n_0\
);
\FSM_sequential_state[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8BBB888B888B888"
)
port map (
I0 => \FSM_sequential_state[1]_i_2_n_0\,
I1 => \out\(2),
I2 => \FSM_sequential_state[1]_i_3_n_0\,
I3 => \out\(1),
I4 => \FSM_onehot_state_reg_n_0_[0]\,
I5 => \out\(0),
O => D(1)
);
\FSM_sequential_state[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FF0100"
)
port map (
I0 => \^rx_valid\,
I1 => \^err\,
I2 => \out\(0),
I3 => \out\(1),
I4 => state17_out,
O => \FSM_sequential_state[1]_i_2_n_0\
);
\FSM_sequential_state[1]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"30003077"
)
port map (
I0 => state1,
I1 => \out\(0),
I2 => state110_out,
I3 => \^rx_valid\,
I4 => \^err\,
O => \FSM_sequential_state[1]_i_3_n_0\
);
\FSM_sequential_state[1]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000008"
)
port map (
I0 => \^rx_valid\,
I1 => \^q\(4),
I2 => \^q\(3),
I3 => \^q\(1),
I4 => valid_i_3_n_0,
O => state17_out
);
\FSM_sequential_state[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"F4040000"
)
port map (
I0 => state110_out,
I1 => \^rx_valid\,
I2 => \out\(0),
I3 => state1,
I4 => \out\(1),
O => \FSM_sequential_state[2]_i_2_n_0\
);
\FSM_sequential_state[2]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"5F13"
)
port map (
I0 => \out\(1),
I1 => \^err\,
I2 => \out\(0),
I3 => \^rx_valid\,
O => \FSM_sequential_state[2]_i_3_n_0\
);
\FSM_sequential_state[2]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => \tx_data_reg[2]\,
I1 => \tx_data_reg[7]\,
I2 => \^q\(4),
I3 => \^q\(3),
I4 => \^q\(1),
I5 => valid_i_3_n_0,
O => state110_out
);
\FSM_sequential_state[2]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000002000000"
)
port map (
I0 => \^rx_valid\,
I1 => \^q\(6),
I2 => \^q\(4),
I3 => \^q\(3),
I4 => \^q\(1),
I5 => \FSM_sequential_state[2]_i_6_n_0\,
O => state1
);
\FSM_sequential_state[2]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFFF"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(7),
I3 => \^q\(5),
O => \FSM_sequential_state[2]_i_6_n_0\
);
\FSM_sequential_state_reg[2]_i_1\: unisim.vcomponents.MUXF7
port map (
I0 => \FSM_sequential_state[2]_i_2_n_0\,
I1 => \FSM_sequential_state[2]_i_3_n_0\,
O => D(2),
S => \out\(2)
);
IOBUF_inst_0: unisim.vcomponents.IOBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => ps2_clk_out,
IO => PS2_CLK,
O => ps2_clk_in,
T => T0
);
IOBUF_inst_1: unisim.vcomponents.IOBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => ps2_data_out,
IO => PS2_DATA,
O => ps2_data_in,
T => ps2_data_en_reg_inv_n_0
);
\bits_count[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[0]\,
I1 => \bits_count_reg_n_0_[0]\,
O => \bits_count[0]_i_1_n_0\
);
\bits_count[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"06"
)
port map (
I0 => \bits_count_reg_n_0_[1]\,
I1 => \bits_count_reg_n_0_[0]\,
I2 => \FSM_onehot_state_reg_n_0_[0]\,
O => \bits_count[1]_i_1_n_0\
);
\bits_count[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"006A"
)
port map (
I0 => \bits_count_reg_n_0_[2]\,
I1 => \bits_count_reg_n_0_[0]\,
I2 => \bits_count_reg_n_0_[1]\,
I3 => \FSM_onehot_state_reg_n_0_[0]\,
O => \bits_count[2]_i_1_n_0\
);
\bits_count[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[0]\,
I1 => p_1_in_0,
I2 => \FSM_onehot_state_reg_n_0_[2]\,
O => bits_count
);
\bits_count[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"000078F0"
)
port map (
I0 => \bits_count_reg_n_0_[1]\,
I1 => \bits_count_reg_n_0_[0]\,
I2 => \bits_count_reg_n_0_[3]\,
I3 => \bits_count_reg_n_0_[2]\,
I4 => \FSM_onehot_state_reg_n_0_[0]\,
O => \bits_count[3]_i_2_n_0\
);
\bits_count_reg[0]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => bits_count,
CLR => rst,
D => \bits_count[0]_i_1_n_0\,
Q => \bits_count_reg_n_0_[0]\
);
\bits_count_reg[1]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => bits_count,
CLR => rst,
D => \bits_count[1]_i_1_n_0\,
Q => \bits_count_reg_n_0_[1]\
);
\bits_count_reg[2]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => bits_count,
CLR => rst,
D => \bits_count[2]_i_1_n_0\,
Q => \bits_count_reg_n_0_[2]\
);
\bits_count_reg[3]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => bits_count,
CLR => rst,
D => \bits_count[3]_i_2_n_0\,
Q => \bits_count_reg_n_0_[3]\
);
\clk_count[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9000999900009999"
)
port map (
I0 => ps2_clk_in,
I1 => clk_inter,
I2 => clk_count(3),
I3 => clk_count(2),
I4 => clk_count(0),
I5 => clk_count(1),
O => \clk_count[0]_i_1_n_0\
);
\clk_count[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9000999999990000"
)
port map (
I0 => ps2_clk_in,
I1 => clk_inter,
I2 => clk_count(3),
I3 => clk_count(2),
I4 => clk_count(0),
I5 => clk_count(1),
O => \clk_count[1]_i_1_n_0\
);
\clk_count[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9099990099009900"
)
port map (
I0 => ps2_clk_in,
I1 => clk_inter,
I2 => clk_count(3),
I3 => clk_count(2),
I4 => clk_count(0),
I5 => clk_count(1),
O => \clk_count[2]_i_1_n_0\
);
\clk_count[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9990909090909090"
)
port map (
I0 => ps2_clk_in,
I1 => clk_inter,
I2 => clk_count(3),
I3 => clk_count(2),
I4 => clk_count(0),
I5 => clk_count(1),
O => \clk_count[3]_i_1_n_0\
);
\clk_count_reg[0]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => rst,
D => \clk_count[0]_i_1_n_0\,
Q => clk_count(0)
);
\clk_count_reg[1]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => rst,
D => \clk_count[1]_i_1_n_0\,
Q => clk_count(1)
);
\clk_count_reg[2]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => rst,
D => \clk_count[2]_i_1_n_0\,
Q => clk_count(2)
);
\clk_count_reg[3]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => rst,
D => \clk_count[3]_i_1_n_0\,
Q => clk_count(3)
);
clk_inter_reg: unisim.vcomponents.FDPE
port map (
C => clk,
CE => '1',
D => ps2_clk_in,
PRE => rst,
Q => clk_inter
);
\counter[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF5D00"
)
port map (
I0 => counter(0),
I1 => state_next1,
I2 => \counter[0]_i_2_n_0\,
I3 => \FSM_onehot_state_reg_n_0_[7]\,
I4 => \counter[0]_i_3_n_0\,
I5 => \counter[0]_i_4_n_0\,
O => counter_next(0)
);
\counter[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEFFFFFFFFFFF"
)
port map (
I0 => \FSM_onehot_state[8]_i_5_n_0\,
I1 => \counter[0]_i_5_n_0\,
I2 => counter(2),
I3 => counter(3),
I4 => \counter[0]_i_6_n_0\,
I5 => counter(1),
O => \counter[0]_i_2_n_0\
);
\counter[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00FF00BF00000000"
)
port map (
I0 => \FSM_onehot_state[8]_i_5_n_0\,
I1 => counter(6),
I2 => counter(7),
I3 => counter(0),
I4 => \counter[13]_i_3_n_0\,
I5 => \FSM_onehot_state_reg_n_0_[5]\,
O => \counter[0]_i_3_n_0\
);
\counter[0]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"3200"
)
port map (
I0 => \counter[13]_i_2_n_0\,
I1 => counter(0),
I2 => \counter[13]_i_3_n_0\,
I3 => \FSM_onehot_state_reg_n_0_[1]\,
O => \counter[0]_i_4_n_0\
);
\counter[0]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFD"
)
port map (
I0 => counter(5),
I1 => counter(8),
I2 => counter(10),
I3 => counter(9),
O => \counter[0]_i_5_n_0\
);
\counter[0]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => counter(6),
I1 => counter(7),
O => \counter[0]_i_6_n_0\
);
\counter[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFF00FF00FF00"
)
port map (
I0 => \counter[13]_i_2_n_0\,
I1 => counter(0),
I2 => \counter[13]_i_3_n_0\,
I3 => \counter[10]_i_2_n_0\,
I4 => \FSM_onehot_state_reg_n_0_[1]\,
I5 => data1(10),
O => counter_next(10)
);
\counter[10]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"F8880000"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[5]\,
I1 => \counter[13]_i_7_n_0\,
I2 => \FSM_onehot_state_reg_n_0_[7]\,
I3 => \counter[13]_i_8_n_0\,
I4 => data1(10),
O => \counter[10]_i_2_n_0\
);
\counter[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFF00FF00FF00"
)
port map (
I0 => \counter[13]_i_2_n_0\,
I1 => counter(0),
I2 => \counter[13]_i_3_n_0\,
I3 => \counter[11]_i_2_n_0\,
I4 => \FSM_onehot_state_reg_n_0_[1]\,
I5 => data1(11),
O => counter_next(11)
);
\counter[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"F8880000"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[5]\,
I1 => \counter[13]_i_7_n_0\,
I2 => \FSM_onehot_state_reg_n_0_[7]\,
I3 => \counter[13]_i_8_n_0\,
I4 => data1(11),
O => \counter[11]_i_2_n_0\
);
\counter[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFF00FF00FF00"
)
port map (
I0 => \counter[13]_i_2_n_0\,
I1 => counter(0),
I2 => \counter[13]_i_3_n_0\,
I3 => \counter[12]_i_2_n_0\,
I4 => \FSM_onehot_state_reg_n_0_[1]\,
I5 => data1(12),
O => counter_next(12)
);
\counter[12]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"F8880000"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[5]\,
I1 => \counter[13]_i_7_n_0\,
I2 => \FSM_onehot_state_reg_n_0_[7]\,
I3 => \counter[13]_i_8_n_0\,
I4 => data1(12),
O => \counter[12]_i_2_n_0\
);
\counter[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFF00FF00FF00"
)
port map (
I0 => \counter[13]_i_2_n_0\,
I1 => counter(0),
I2 => \counter[13]_i_3_n_0\,
I3 => \counter[13]_i_4_n_0\,
I4 => \FSM_onehot_state_reg_n_0_[1]\,
I5 => data1(13),
O => counter_next(13)
);
\counter[13]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFF7FFFFFFFF"
)
port map (
I0 => counter(7),
I1 => counter(6),
I2 => counter(13),
I3 => counter(12),
I4 => counter(11),
I5 => counter(4),
O => \counter[13]_i_10_n_0\
);
\counter[13]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEF"
)
port map (
I0 => counter(3),
I1 => counter(2),
I2 => counter(8),
I3 => counter(5),
O => \counter[13]_i_11_n_0\
);
\counter[13]_i_12\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => counter(2),
I1 => counter(3),
O => \counter[13]_i_12_n_0\
);
\counter[13]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFDFF"
)
port map (
I0 => counter(13),
I1 => counter(6),
I2 => counter(7),
I3 => counter(4),
I4 => counter(11),
I5 => counter(12),
O => \counter[13]_i_2_n_0\
);
\counter[13]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFB"
)
port map (
I0 => counter(5),
I1 => counter(8),
I2 => counter(2),
I3 => counter(3),
I4 => counter(1),
I5 => \counter[13]_i_6_n_0\,
O => \counter[13]_i_3_n_0\
);
\counter[13]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"F8880000"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[5]\,
I1 => \counter[13]_i_7_n_0\,
I2 => \FSM_onehot_state_reg_n_0_[7]\,
I3 => \counter[13]_i_8_n_0\,
I4 => data1(13),
O => \counter[13]_i_4_n_0\
);
\counter[13]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => counter(9),
I1 => counter(10),
O => \counter[13]_i_6_n_0\
);
\counter[13]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFFFFFFFFFFFF"
)
port map (
I0 => \counter[13]_i_10_n_0\,
I1 => counter(0),
I2 => \counter[13]_i_11_n_0\,
I3 => counter(1),
I4 => counter(9),
I5 => counter(10),
O => \counter[13]_i_7_n_0\
);
\counter[13]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFDFFFFFFFF"
)
port map (
I0 => counter(1),
I1 => \counter[0]_i_6_n_0\,
I2 => \counter[13]_i_12_n_0\,
I3 => \counter[0]_i_5_n_0\,
I4 => \FSM_onehot_state[8]_i_5_n_0\,
I5 => counter(0),
O => \counter[13]_i_8_n_0\
);
\counter[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFF00FF00FF00"
)
port map (
I0 => \counter[13]_i_2_n_0\,
I1 => counter(0),
I2 => \counter[13]_i_3_n_0\,
I3 => \counter[1]_i_2_n_0\,
I4 => \FSM_onehot_state_reg_n_0_[1]\,
I5 => data1(1),
O => counter_next(1)
);
\counter[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800F8F0F8008800"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[5]\,
I1 => \counter[13]_i_7_n_0\,
I2 => \FSM_onehot_state_reg_n_0_[7]\,
I3 => data1(1),
I4 => \counter[13]_i_8_n_0\,
I5 => state_next1,
O => \counter[1]_i_2_n_0\
);
\counter[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFF00FF00FF00"
)
port map (
I0 => \counter[13]_i_2_n_0\,
I1 => counter(0),
I2 => \counter[13]_i_3_n_0\,
I3 => \counter[2]_i_2_n_0\,
I4 => \FSM_onehot_state_reg_n_0_[1]\,
I5 => data1(2),
O => counter_next(2)
);
\counter[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800F8F0F8008800"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[5]\,
I1 => \counter[13]_i_7_n_0\,
I2 => \FSM_onehot_state_reg_n_0_[7]\,
I3 => data1(2),
I4 => \counter[13]_i_8_n_0\,
I5 => state_next1,
O => \counter[2]_i_2_n_0\
);
\counter[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFF00FF00FF00"
)
port map (
I0 => \counter[13]_i_2_n_0\,
I1 => counter(0),
I2 => \counter[13]_i_3_n_0\,
I3 => \counter[3]_i_2_n_0\,
I4 => \FSM_onehot_state_reg_n_0_[1]\,
I5 => data1(3),
O => counter_next(3)
);
\counter[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800F8F0F8008800"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[5]\,
I1 => \counter[13]_i_7_n_0\,
I2 => \FSM_onehot_state_reg_n_0_[7]\,
I3 => data1(3),
I4 => \counter[13]_i_8_n_0\,
I5 => state_next1,
O => \counter[3]_i_2_n_0\
);
\counter[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFF00FF00FF00"
)
port map (
I0 => \counter[13]_i_2_n_0\,
I1 => counter(0),
I2 => \counter[13]_i_3_n_0\,
I3 => \counter[4]_i_2_n_0\,
I4 => \FSM_onehot_state_reg_n_0_[1]\,
I5 => data1(4),
O => counter_next(4)
);
\counter[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800F8F0F8008800"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[5]\,
I1 => \counter[13]_i_7_n_0\,
I2 => \FSM_onehot_state_reg_n_0_[7]\,
I3 => data1(4),
I4 => \counter[13]_i_8_n_0\,
I5 => state_next1,
O => \counter[4]_i_2_n_0\
);
\counter[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFF00FF00FF00"
)
port map (
I0 => \counter[13]_i_2_n_0\,
I1 => counter(0),
I2 => \counter[13]_i_3_n_0\,
I3 => \counter[5]_i_2_n_0\,
I4 => \FSM_onehot_state_reg_n_0_[1]\,
I5 => data1(5),
O => counter_next(5)
);
\counter[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800F8F0F8008800"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[5]\,
I1 => \counter[13]_i_7_n_0\,
I2 => \FSM_onehot_state_reg_n_0_[7]\,
I3 => data1(5),
I4 => \counter[13]_i_8_n_0\,
I5 => state_next1,
O => \counter[5]_i_2_n_0\
);
\counter[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFF00FF00FF00"
)
port map (
I0 => \counter[13]_i_2_n_0\,
I1 => counter(0),
I2 => \counter[13]_i_3_n_0\,
I3 => \counter[6]_i_2_n_0\,
I4 => \FSM_onehot_state_reg_n_0_[1]\,
I5 => data1(6),
O => counter_next(6)
);
\counter[6]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"F8880000"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[5]\,
I1 => \counter[13]_i_7_n_0\,
I2 => \FSM_onehot_state_reg_n_0_[7]\,
I3 => \counter[13]_i_8_n_0\,
I4 => data1(6),
O => \counter[6]_i_2_n_0\
);
\counter[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFF00FF00FF00"
)
port map (
I0 => \counter[13]_i_2_n_0\,
I1 => counter(0),
I2 => \counter[13]_i_3_n_0\,
I3 => \counter[7]_i_2_n_0\,
I4 => \FSM_onehot_state_reg_n_0_[1]\,
I5 => data1(7),
O => counter_next(7)
);
\counter[7]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"F8880000"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[5]\,
I1 => \counter[13]_i_7_n_0\,
I2 => \FSM_onehot_state_reg_n_0_[7]\,
I3 => \counter[13]_i_8_n_0\,
I4 => data1(7),
O => \counter[7]_i_2_n_0\
);
\counter[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFF00FF00FF00"
)
port map (
I0 => \counter[13]_i_2_n_0\,
I1 => counter(0),
I2 => \counter[13]_i_3_n_0\,
I3 => \counter[8]_i_2_n_0\,
I4 => \FSM_onehot_state_reg_n_0_[1]\,
I5 => data1(8),
O => counter_next(8)
);
\counter[8]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"F8880000"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[5]\,
I1 => \counter[13]_i_7_n_0\,
I2 => \FSM_onehot_state_reg_n_0_[7]\,
I3 => \counter[13]_i_8_n_0\,
I4 => data1(8),
O => \counter[8]_i_2_n_0\
);
\counter[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFF00FF00FF00"
)
port map (
I0 => \counter[13]_i_2_n_0\,
I1 => counter(0),
I2 => \counter[13]_i_3_n_0\,
I3 => \counter[9]_i_2_n_0\,
I4 => \FSM_onehot_state_reg_n_0_[1]\,
I5 => data1(9),
O => counter_next(9)
);
\counter[9]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"F8880000"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[5]\,
I1 => \counter[13]_i_7_n_0\,
I2 => \FSM_onehot_state_reg_n_0_[7]\,
I3 => \counter[13]_i_8_n_0\,
I4 => data1(9),
O => \counter[9]_i_2_n_0\
);
\counter_reg[0]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => rst,
D => counter_next(0),
Q => counter(0)
);
\counter_reg[10]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => rst,
D => counter_next(10),
Q => counter(10)
);
\counter_reg[11]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => rst,
D => counter_next(11),
Q => counter(11)
);
\counter_reg[12]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => rst,
D => counter_next(12),
Q => counter(12)
);
\counter_reg[12]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[8]_i_3_n_0\,
CO(3) => \counter_reg[12]_i_3_n_0\,
CO(2) => \counter_reg[12]_i_3_n_1\,
CO(1) => \counter_reg[12]_i_3_n_2\,
CO(0) => \counter_reg[12]_i_3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => data1(12 downto 9),
S(3 downto 0) => counter(12 downto 9)
);
\counter_reg[13]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => rst,
D => counter_next(13),
Q => counter(13)
);
\counter_reg[13]_i_5\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[12]_i_3_n_0\,
CO(3 downto 0) => \NLW_counter_reg[13]_i_5_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => \NLW_counter_reg[13]_i_5_O_UNCONNECTED\(3 downto 1),
O(0) => data1(13),
S(3 downto 1) => B"000",
S(0) => counter(13)
);
\counter_reg[1]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => rst,
D => counter_next(1),
Q => counter(1)
);
\counter_reg[2]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => rst,
D => counter_next(2),
Q => counter(2)
);
\counter_reg[3]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => rst,
D => counter_next(3),
Q => counter(3)
);
\counter_reg[4]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => rst,
D => counter_next(4),
Q => counter(4)
);
\counter_reg[4]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \counter_reg[4]_i_3_n_0\,
CO(2) => \counter_reg[4]_i_3_n_1\,
CO(1) => \counter_reg[4]_i_3_n_2\,
CO(0) => \counter_reg[4]_i_3_n_3\,
CYINIT => counter(0),
DI(3 downto 0) => B"0000",
O(3 downto 0) => data1(4 downto 1),
S(3 downto 0) => counter(4 downto 1)
);
\counter_reg[5]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => rst,
D => counter_next(5),
Q => counter(5)
);
\counter_reg[6]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => rst,
D => counter_next(6),
Q => counter(6)
);
\counter_reg[7]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => rst,
D => counter_next(7),
Q => counter(7)
);
\counter_reg[8]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => rst,
D => counter_next(8),
Q => counter(8)
);
\counter_reg[8]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[4]_i_3_n_0\,
CO(3) => \counter_reg[8]_i_3_n_0\,
CO(2) => \counter_reg[8]_i_3_n_1\,
CO(1) => \counter_reg[8]_i_3_n_2\,
CO(0) => \counter_reg[8]_i_3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => data1(8 downto 5),
S(3 downto 0) => counter(8 downto 5)
);
\counter_reg[9]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => rst,
D => counter_next(9),
Q => counter(9)
);
\data_count[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9000999900009999"
)
port map (
I0 => ps2_data_in,
I1 => data_inter,
I2 => data_count(3),
I3 => data_count(2),
I4 => data_count(0),
I5 => data_count(1),
O => \data_count[0]_i_1_n_0\
);
\data_count[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9000999999990000"
)
port map (
I0 => ps2_data_in,
I1 => data_inter,
I2 => data_count(3),
I3 => data_count(2),
I4 => data_count(0),
I5 => data_count(1),
O => \data_count[1]_i_1_n_0\
);
\data_count[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9099990099009900"
)
port map (
I0 => ps2_data_in,
I1 => data_inter,
I2 => data_count(3),
I3 => data_count(2),
I4 => data_count(0),
I5 => data_count(1),
O => \data_count[2]_i_1_n_0\
);
\data_count[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9990909090909090"
)
port map (
I0 => ps2_data_in,
I1 => data_inter,
I2 => data_count(3),
I3 => data_count(2),
I4 => data_count(0),
I5 => data_count(1),
O => \data_count[3]_i_1_n_0\
);
\data_count_reg[0]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => rst,
D => \data_count[0]_i_1_n_0\,
Q => data_count(0)
);
\data_count_reg[1]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => rst,
D => \data_count[1]_i_1_n_0\,
Q => data_count(1)
);
\data_count_reg[2]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => rst,
D => \data_count[2]_i_1_n_0\,
Q => data_count(2)
);
\data_count_reg[3]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => rst,
D => \data_count[3]_i_1_n_0\,
Q => data_count(3)
);
data_inter_reg: unisim.vcomponents.FDPE
port map (
C => clk,
CE => '1',
D => ps2_data_in,
PRE => rst,
Q => data_inter
);
err_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF800880088008"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[4]\,
I1 => err_i_2_n_0,
I2 => \frame_reg_n_0_[9]\,
I3 => err_i_3_n_0,
I4 => \FSM_onehot_state_reg_n_0_[14]\,
I5 => state_next1,
O => err_next
);
err_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => \bits_count_reg_n_0_[3]\,
I1 => \bits_count_reg_n_0_[2]\,
I2 => \bits_count_reg_n_0_[1]\,
I3 => \bits_count_reg_n_0_[0]\,
O => err_i_2_n_0
);
err_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \frame_reg_n_0_[2]\,
I1 => \frame_reg_n_0_[1]\,
I2 => \rx_data[7]_i_2_n_0\,
O => err_i_3_n_0
);
err_reg: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => rst,
D => err_next,
Q => \^err\
);
\frame[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"70"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[0]\,
I1 => tx_valid_reg,
I2 => \frame_reg_n_0_[1]\,
O => p_1_in(0)
);
\frame[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FEEE"
)
port map (
I0 => p_1_in_0,
I1 => \FSM_onehot_state_reg_n_0_[2]\,
I2 => \FSM_onehot_state_reg_n_0_[0]\,
I3 => tx_valid_reg,
O => \frame[10]_i_1_n_0\
);
\frame[10]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"EA"
)
port map (
I0 => ps2_data_s_reg_n_0,
I1 => \FSM_onehot_state_reg_n_0_[0]\,
I2 => tx_valid_reg,
O => p_1_in(10)
);
\frame[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EA2A"
)
port map (
I0 => \frame_reg_n_0_[2]\,
I1 => tx_valid_reg,
I2 => \FSM_onehot_state_reg_n_0_[0]\,
I3 => \tx_data_reg[2]\,
O => p_1_in(1)
);
\frame[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EA2A"
)
port map (
I0 => \frame_reg_n_0_[3]\,
I1 => tx_valid_reg,
I2 => \FSM_onehot_state_reg_n_0_[0]\,
I3 => \tx_data_reg[2]\,
O => p_1_in(2)
);
\frame[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EA2A"
)
port map (
I0 => \frame_reg_n_0_[4]\,
I1 => tx_valid_reg,
I2 => \FSM_onehot_state_reg_n_0_[0]\,
I3 => \tx_data_reg[2]\,
O => p_1_in(3)
);
\frame[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EA2A"
)
port map (
I0 => \frame_reg_n_0_[5]\,
I1 => tx_valid_reg,
I2 => \FSM_onehot_state_reg_n_0_[0]\,
I3 => \tx_data_reg[7]\,
O => p_1_in(4)
);
\frame[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EA2A"
)
port map (
I0 => \frame_reg_n_0_[6]\,
I1 => tx_valid_reg,
I2 => \FSM_onehot_state_reg_n_0_[0]\,
I3 => \tx_data_reg[7]\,
O => p_1_in(5)
);
\frame[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EA2A"
)
port map (
I0 => \frame_reg_n_0_[7]\,
I1 => tx_valid_reg,
I2 => \FSM_onehot_state_reg_n_0_[0]\,
I3 => \tx_data_reg[7]\,
O => p_1_in(6)
);
\frame[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EA2A"
)
port map (
I0 => \frame_reg_n_0_[8]\,
I1 => tx_valid_reg,
I2 => \FSM_onehot_state_reg_n_0_[0]\,
I3 => \tx_data_reg[7]\,
O => p_1_in(7)
);
\frame[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EA2A"
)
port map (
I0 => \frame_reg_n_0_[9]\,
I1 => tx_valid_reg,
I2 => \FSM_onehot_state_reg_n_0_[0]\,
I3 => \tx_data_reg[7]\,
O => p_1_in(8)
);
\frame[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EA2A2AEA"
)
port map (
I0 => \frame_reg_n_0_[10]\,
I1 => tx_valid_reg,
I2 => \FSM_onehot_state_reg_n_0_[0]\,
I3 => \tx_data_reg[2]\,
I4 => \tx_data_reg[7]\,
O => p_1_in(9)
);
\frame_reg[0]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => \frame[10]_i_1_n_0\,
CLR => rst,
D => p_1_in(0),
Q => \frame_reg_n_0_[0]\
);
\frame_reg[10]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => \frame[10]_i_1_n_0\,
CLR => rst,
D => p_1_in(10),
Q => \frame_reg_n_0_[10]\
);
\frame_reg[1]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => \frame[10]_i_1_n_0\,
CLR => rst,
D => p_1_in(1),
Q => \frame_reg_n_0_[1]\
);
\frame_reg[2]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => \frame[10]_i_1_n_0\,
CLR => rst,
D => p_1_in(2),
Q => \frame_reg_n_0_[2]\
);
\frame_reg[3]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => \frame[10]_i_1_n_0\,
CLR => rst,
D => p_1_in(3),
Q => \frame_reg_n_0_[3]\
);
\frame_reg[4]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => \frame[10]_i_1_n_0\,
CLR => rst,
D => p_1_in(4),
Q => \frame_reg_n_0_[4]\
);
\frame_reg[5]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => \frame[10]_i_1_n_0\,
CLR => rst,
D => p_1_in(5),
Q => \frame_reg_n_0_[5]\
);
\frame_reg[6]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => \frame[10]_i_1_n_0\,
CLR => rst,
D => p_1_in(6),
Q => \frame_reg_n_0_[6]\
);
\frame_reg[7]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => \frame[10]_i_1_n_0\,
CLR => rst,
D => p_1_in(7),
Q => \frame_reg_n_0_[7]\
);
\frame_reg[8]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => \frame[10]_i_1_n_0\,
CLR => rst,
D => p_1_in(8),
Q => \frame_reg_n_0_[8]\
);
\frame_reg[9]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => \frame[10]_i_1_n_0\,
CLR => rst,
D => p_1_in(9),
Q => \frame_reg_n_0_[9]\
);
is_break_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0803"
)
port map (
I0 => \^rx_valid\,
I1 => \out\(2),
I2 => \out\(0),
I3 => \out\(1),
O => is_break_reg
);
is_extend_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"F8000800"
)
port map (
I0 => \out\(0),
I1 => \^rx_valid\,
I2 => \out\(1),
I3 => \out\(2),
I4 => is_extend,
O => is_extend_reg
);
ps2_clk_en_inv_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[1]\,
I1 => \FSM_onehot_state_reg_n_0_[5]\,
O => ps2_clk_en_next
);
ps2_clk_en_reg_inv: unisim.vcomponents.FDPE
port map (
C => clk,
CE => '1',
D => ps2_clk_en_next,
PRE => rst,
Q => T0
);
ps2_clk_out_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[6]\,
I1 => \FSM_onehot_state_reg_n_0_[7]\,
I2 => \FSM_onehot_state[5]_i_3_n_0\,
I3 => \FSM_onehot_state[0]_i_5_n_0\,
I4 => ps2_clk_out_i_2_n_0,
O => ps2_clk_out_next
);
ps2_clk_out_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[9]\,
I1 => p_1_in_0,
I2 => \FSM_onehot_state_reg_n_0_[11]\,
O => ps2_clk_out_i_2_n_0
);
ps2_clk_out_reg: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => rst,
D => ps2_clk_out_next,
Q => ps2_clk_out
);
ps2_clk_s_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FD80"
)
port map (
I0 => ps2_clk_s,
I1 => ps2_clk_in,
I2 => clk_inter,
I3 => state_next1,
O => ps2_clk_s_i_1_n_0
);
ps2_clk_s_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => clk_count(3),
I1 => clk_count(2),
I2 => clk_count(0),
I3 => clk_count(1),
O => ps2_clk_s
);
ps2_clk_s_reg: unisim.vcomponents.FDPE
port map (
C => clk,
CE => '1',
D => ps2_clk_s_i_1_n_0,
PRE => rst,
Q => state_next1
);
ps2_data_en_inv_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000007"
)
port map (
I0 => \FSM_onehot_state[11]_i_2_n_0\,
I1 => \FSM_onehot_state_reg_n_0_[9]\,
I2 => p_1_in_0,
I3 => \FSM_onehot_state_reg_n_0_[11]\,
I4 => ps2_data_en_inv_i_2_n_0,
I5 => \FSM_onehot_state_reg_n_0_[5]\,
O => ps2_data_en_next
);
ps2_data_en_inv_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[6]\,
I1 => \FSM_onehot_state_reg_n_0_[7]\,
O => ps2_data_en_inv_i_2_n_0
);
ps2_data_en_reg_inv: unisim.vcomponents.FDPE
port map (
C => clk,
CE => '1',
D => ps2_data_en_next,
PRE => rst,
Q => ps2_data_en_reg_inv_n_0
);
ps2_data_out_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFEAAAA"
)
port map (
I0 => \FSM_onehot_state[0]_i_5_n_0\,
I1 => \FSM_onehot_state_reg_n_0_[11]\,
I2 => p_1_in_0,
I3 => \FSM_onehot_state_reg_n_0_[9]\,
I4 => \frame_reg_n_0_[0]\,
I5 => \FSM_onehot_state[6]_i_2_n_0\,
O => ps2_data_out_next
);
ps2_data_out_reg: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => rst,
D => ps2_data_out_next,
Q => ps2_data_out
);
ps2_data_s_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FD80"
)
port map (
I0 => ps2_data_s,
I1 => ps2_data_in,
I2 => data_inter,
I3 => ps2_data_s_reg_n_0,
O => ps2_data_s_i_1_n_0
);
ps2_data_s_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => data_count(3),
I1 => data_count(2),
I2 => data_count(0),
I3 => data_count(1),
O => ps2_data_s
);
ps2_data_s_reg: unisim.vcomponents.FDPE
port map (
C => clk,
CE => '1',
D => ps2_data_s_i_1_n_0,
PRE => rst,
Q => ps2_data_s_reg_n_0
);
\rx_data[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"2882822800000000"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[4]\,
I1 => \frame_reg_n_0_[9]\,
I2 => \frame_reg_n_0_[2]\,
I3 => \frame_reg_n_0_[1]\,
I4 => \rx_data[7]_i_2_n_0\,
I5 => err_i_2_n_0,
O => rx_finish
);
\rx_data[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \frame_reg_n_0_[4]\,
I1 => \frame_reg_n_0_[3]\,
I2 => \frame_reg_n_0_[7]\,
I3 => \frame_reg_n_0_[8]\,
I4 => \frame_reg_n_0_[5]\,
I5 => \frame_reg_n_0_[6]\,
O => \rx_data[7]_i_2_n_0\
);
\rx_data_reg[0]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => rx_finish,
CLR => rst,
D => \frame_reg_n_0_[1]\,
Q => \^q\(0)
);
\rx_data_reg[1]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => rx_finish,
CLR => rst,
D => \frame_reg_n_0_[2]\,
Q => \^q\(1)
);
\rx_data_reg[2]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => rx_finish,
CLR => rst,
D => \frame_reg_n_0_[3]\,
Q => \^q\(2)
);
\rx_data_reg[3]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => rx_finish,
CLR => rst,
D => \frame_reg_n_0_[4]\,
Q => \^q\(3)
);
\rx_data_reg[4]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => rx_finish,
CLR => rst,
D => \frame_reg_n_0_[5]\,
Q => \^q\(4)
);
\rx_data_reg[5]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => rx_finish,
CLR => rst,
D => \frame_reg_n_0_[6]\,
Q => \^q\(5)
);
\rx_data_reg[6]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => rx_finish,
CLR => rst,
D => \frame_reg_n_0_[7]\,
Q => \^q\(6)
);
\rx_data_reg[7]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => rx_finish,
CLR => rst,
D => \frame_reg_n_0_[8]\,
Q => \^q\(7)
);
rx_valid_reg: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => rst,
D => rx_finish,
Q => \^rx_valid\
);
tx_valid_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0040"
)
port map (
I0 => \out\(1),
I1 => \FSM_onehot_state_reg_n_0_[0]\,
I2 => \out\(0),
I3 => \out\(2),
O => tx_valid
);
valid_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0A88A800000000"
)
port map (
I0 => \^rx_valid\,
I1 => valid_i_2_n_0,
I2 => \out\(0),
I3 => \^q\(4),
I4 => \out\(1),
I5 => \out\(2),
O => valid_reg
);
valid_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => valid_i_3_n_0,
O => valid_i_2_n_0
);
valid_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF7FFFF"
)
port map (
I0 => \^q\(5),
I1 => \^q\(7),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(6),
O => valid_i_3_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity KeyboardCtrl_0_KeyboardCtrl is
port (
err : out STD_LOGIC;
key_in : out STD_LOGIC_VECTOR ( 7 downto 0 );
is_break : out STD_LOGIC;
valid : out STD_LOGIC;
is_extend : out STD_LOGIC;
PS2_CLK : inout STD_LOGIC;
PS2_DATA : inout STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of KeyboardCtrl_0_KeyboardCtrl : entity is "KeyboardCtrl";
end KeyboardCtrl_0_KeyboardCtrl;
architecture STRUCTURE of KeyboardCtrl_0_KeyboardCtrl is
signal Ps2Interface_i_n_11 : STD_LOGIC;
signal Ps2Interface_i_n_12 : STD_LOGIC;
signal Ps2Interface_i_n_13 : STD_LOGIC;
signal Ps2Interface_i_n_15 : STD_LOGIC;
signal Ps2Interface_i_n_16 : STD_LOGIC;
signal Ps2Interface_i_n_2 : STD_LOGIC;
signal \^is_extend\ : STD_LOGIC;
signal rx_data : STD_LOGIC_VECTOR ( 7 downto 0 );
signal rx_valid : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of state : signal is "yes";
signal \tx_data[2]_i_1_n_0\ : STD_LOGIC;
signal \tx_data[7]_i_1_n_0\ : STD_LOGIC;
signal \tx_data_reg_n_0_[2]\ : STD_LOGIC;
signal \tx_data_reg_n_0_[7]\ : STD_LOGIC;
signal tx_valid : STD_LOGIC;
signal tx_valid_reg_n_0 : STD_LOGIC;
attribute KEEP : string;
attribute KEEP of \FSM_sequential_state_reg[0]\ : label is "yes";
attribute KEEP of \FSM_sequential_state_reg[1]\ : label is "yes";
attribute KEEP of \FSM_sequential_state_reg[2]\ : label is "yes";
begin
is_extend <= \^is_extend\;
\FSM_sequential_state_reg[0]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => rst,
D => Ps2Interface_i_n_13,
Q => state(0)
);
\FSM_sequential_state_reg[1]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => rst,
D => Ps2Interface_i_n_12,
Q => state(1)
);
\FSM_sequential_state_reg[2]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => rst,
D => Ps2Interface_i_n_11,
Q => state(2)
);
Ps2Interface_i: entity work.KeyboardCtrl_0_Ps2Interface
port map (
D(2) => Ps2Interface_i_n_11,
D(1) => Ps2Interface_i_n_12,
D(0) => Ps2Interface_i_n_13,
PS2_CLK => PS2_CLK,
PS2_DATA => PS2_DATA,
Q(7 downto 0) => rx_data(7 downto 0),
clk => clk,
err => err,
is_break_reg => Ps2Interface_i_n_15,
is_extend => \^is_extend\,
is_extend_reg => Ps2Interface_i_n_2,
\out\(2 downto 0) => state(2 downto 0),
rst => rst,
rx_valid => rx_valid,
\tx_data_reg[2]\ => \tx_data_reg_n_0_[2]\,
\tx_data_reg[7]\ => \tx_data_reg_n_0_[7]\,
tx_valid => tx_valid,
tx_valid_reg => tx_valid_reg_n_0,
valid_reg => Ps2Interface_i_n_16
);
is_break_reg: unisim.vcomponents.FDPE
port map (
C => clk,
CE => '1',
D => Ps2Interface_i_n_15,
PRE => rst,
Q => is_break
);
is_extend_reg: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => rst,
D => Ps2Interface_i_n_2,
Q => \^is_extend\
);
\key_in_reg[0]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => rx_valid,
CLR => rst,
D => rx_data(0),
Q => key_in(0)
);
\key_in_reg[1]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => rx_valid,
CLR => rst,
D => rx_data(1),
Q => key_in(1)
);
\key_in_reg[2]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => rx_valid,
CLR => rst,
D => rx_data(2),
Q => key_in(2)
);
\key_in_reg[3]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => rx_valid,
CLR => rst,
D => rx_data(3),
Q => key_in(3)
);
\key_in_reg[4]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => rx_valid,
CLR => rst,
D => rx_data(4),
Q => key_in(4)
);
\key_in_reg[5]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => rx_valid,
CLR => rst,
D => rx_data(5),
Q => key_in(5)
);
\key_in_reg[6]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => rx_valid,
CLR => rst,
D => rx_data(6),
Q => key_in(6)
);
\key_in_reg[7]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => rx_valid,
CLR => rst,
D => rx_data(7),
Q => key_in(7)
);
\tx_data[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FF01"
)
port map (
I0 => state(1),
I1 => state(0),
I2 => state(2),
I3 => \tx_data_reg_n_0_[2]\,
O => \tx_data[2]_i_1_n_0\
);
\tx_data[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FF01"
)
port map (
I0 => state(1),
I1 => state(0),
I2 => state(2),
I3 => \tx_data_reg_n_0_[7]\,
O => \tx_data[7]_i_1_n_0\
);
\tx_data_reg[2]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => rst,
D => \tx_data[2]_i_1_n_0\,
Q => \tx_data_reg_n_0_[2]\
);
\tx_data_reg[7]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => rst,
D => \tx_data[7]_i_1_n_0\,
Q => \tx_data_reg_n_0_[7]\
);
tx_valid_reg: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => rst,
D => tx_valid,
Q => tx_valid_reg_n_0
);
valid_reg: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => rst,
D => Ps2Interface_i_n_16,
Q => valid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity KeyboardCtrl_0 is
port (
key_in : out STD_LOGIC_VECTOR ( 7 downto 0 );
is_extend : out STD_LOGIC;
is_break : out STD_LOGIC;
valid : out STD_LOGIC;
err : out STD_LOGIC;
PS2_DATA : inout STD_LOGIC;
PS2_CLK : inout STD_LOGIC;
rst : in STD_LOGIC;
clk : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of KeyboardCtrl_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of KeyboardCtrl_0 : entity is "KeyboardCtrl_0,KeyboardCtrl,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of KeyboardCtrl_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of KeyboardCtrl_0 : entity is "KeyboardCtrl,Vivado 2016.2";
end KeyboardCtrl_0;
architecture STRUCTURE of KeyboardCtrl_0 is
begin
inst: entity work.KeyboardCtrl_0_KeyboardCtrl
port map (
PS2_CLK => PS2_CLK,
PS2_DATA => PS2_DATA,
clk => clk,
err => err,
is_break => is_break,
is_extend => is_extend,
key_in(7 downto 0) => key_in(7 downto 0),
rst => rst,
valid => valid
);
end STRUCTURE;
| gpl-3.0 | 1da8abf00ea5357671cb8b41c16bebe1 | 0.509795 | 2.650643 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Benchy/eia232.vhd | 13 | 4,325 | ----------------------------------------------------------------------------------
-- eia232.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- EIA232 aka RS232 interface.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity eia232 is
generic (
FREQ : integer;
SCALE : integer;
RATE : integer
);
Port (
clock : in STD_LOGIC;
reset : in std_logic;
speed : in std_logic_vector (1 downto 0);
rx : in STD_LOGIC;
tx : out STD_LOGIC;
cmd : out STD_LOGIC_VECTOR (39 downto 0);
execute : out STD_LOGIC;
data : in STD_LOGIC_VECTOR (31 downto 0);
send : in STD_LOGIC;
busy : out STD_LOGIC
);
end eia232;
architecture Behavioral of eia232 is
COMPONENT sump_prescaler
generic (
SCALE : integer
);
PORT(
clock : IN std_logic;
reset : IN std_logic;
div : IN std_logic_vector(1 downto 0);
scaled : OUT std_logic
);
END COMPONENT;
COMPONENT receiver
generic (
FREQ : integer;
RATE : integer
);
PORT(
rx : IN std_logic;
clock : IN std_logic;
trxClock : IN std_logic;
reset : in STD_LOGIC;
op : out std_logic_vector(7 downto 0);
data : out std_logic_vector(31 downto 0);
execute : out STD_LOGIC
);
END COMPONENT;
COMPONENT transmitter
generic (
FREQ : integer;
RATE : integer
);
PORT(
data : IN std_logic_vector(31 downto 0);
disabledGroups : in std_logic_vector (3 downto 0);
write : IN std_logic;
id : in std_logic;
xon : in std_logic;
xoff : in std_logic;
clock : IN std_logic;
trxClock : IN std_logic;
reset : in std_logic;
tx : OUT std_logic;
busy : out std_logic
);
END COMPONENT;
constant TRXFREQ : integer := FREQ / SCALE; -- reduced rx & tx clock for receiver and transmitter
signal trxClock, executeReg, executePrev, id, xon, xoff, wrFlags : std_logic;
signal disabledGroupsReg : std_logic_vector(3 downto 0);
signal opcode : std_logic_vector(7 downto 0);
signal opdata : std_logic_vector(31 downto 0);
begin
cmd <= opdata & opcode;
execute <= executeReg;
-- process special uart commands that do not belong in core decoder
process(clock)
begin
if rising_edge(clock) then
id <= '0'; xon <= '0'; xoff <= '0'; wrFlags <= '0';
executePrev <= executeReg;
if executePrev = '0' and executeReg = '1' then
case opcode is
when x"02" => id <= '1';
when x"11" => xon <= '1';
when x"13" => xoff <= '1';
when x"82" => wrFlags <= '1';
when others =>
end case;
end if;
end if;
end process;
process(clock)
begin
if rising_edge(clock) then
if wrFlags = '1' then
disabledGroupsReg <= opdata(5 downto 2);
end if;
end if;
end process;
Inst_sump_prescaler: sump_prescaler
generic map (
SCALE => SCALE
)
PORT MAP(
clock => clock,
reset => reset,
div => speed,
scaled => trxClock
);
Inst_receiver: receiver
generic map (
FREQ => TRXFREQ,
RATE => RATE
)
PORT MAP(
rx => rx,
clock => clock,
trxClock => trxClock,
reset => reset,
op => opcode,
data => opdata,
execute => executeReg
);
Inst_transmitter: transmitter
generic map (
FREQ => TRXFREQ,
RATE => RATE
)
PORT MAP(
data => data,
disabledGroups => disabledGroupsReg,
write => send,
id => id,
xon => xon,
xoff => xoff,
clock => clock,
trxClock => trxClock,
reset => reset,
tx => tx,
busy => busy
);
end Behavioral;
| mit | 99067f32db7430c8233195ec34332936 | 0.614798 | 3.256777 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/board_Papilio_Pro/zpupkg.vhd | 39 | 11,171 | -- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
package zpupkg is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := maxAddrBitBRAM;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg;
| mit | 2c968fe23faecb389b933604be7c260f | 0.665115 | 3.056361 | false | false | false | false |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/crash_pixel/synth/crash_pixel.vhd | 1 | 14,357 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY crash_pixel IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END crash_pixel;
ARCHITECTURE crash_pixel_arch OF crash_pixel IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF crash_pixel_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF crash_pixel_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF crash_pixel_arch : ARCHITECTURE IS "crash_pixel,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF crash_pixel_arch: ARCHITECTURE IS "crash_pixel,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=crash_p" &
"ixel.mif,C_INIT_FILE=crash_pixel.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=12,C_READ_WIDTH_A=12,C_WRITE_DEPTH_A=2703,C_READ_DEPTH_A=2703,C_ADDRA_WIDTH=12,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=12,C_READ_WIDTH_B=12,C_W" &
"RITE_DEPTH_B=2703,C_READ_DEPTH_B=2703,C_ADDRB_WIDTH=12,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_" &
"DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 3.822999 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "crash_pixel.mif",
C_INIT_FILE => "crash_pixel.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 12,
C_READ_WIDTH_A => 12,
C_WRITE_DEPTH_A => 2703,
C_READ_DEPTH_A => 2703,
C_ADDRA_WIDTH => 12,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 12,
C_READ_WIDTH_B => 12,
C_WRITE_DEPTH_B => 2703,
C_READ_DEPTH_B => 2703,
C_ADDRB_WIDTH => 12,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 3.822999 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END crash_pixel_arch;
| gpl-3.0 | e23d8029991bf343129b56a26f4eb5f1 | 0.626036 | 3.013644 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/zpuino_crc16.vhd | 13 | 2,754 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_crc16 is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIOBit downto minIOBit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic
);
end entity zpuino_crc16;
architecture behave of zpuino_crc16 is
signal crc_q: std_logic_vector(15 downto 0);
signal crcA_q: std_logic_vector(15 downto 0);
signal crcB_q: std_logic_vector(15 downto 0);
signal poly_q: std_logic_vector(15 downto 0);
signal data_q: std_logic_vector(7 downto 0);
signal count_q: integer range 0 to 7;
signal ready_q: std_logic;
begin
wb_ack_o<='1' when ready_q='1' and ( wb_cyc_i='1' and wb_stb_i='1') else '0';
wb_inta_o <= '0';
process(wb_adr_i,crc_q,poly_q, crcA_q, crcB_q)
begin
case wb_adr_i(4 downto 2) is
when "000" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= crc_q;
when "001" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= poly_q;
when "100" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= crcA_q;
when "101" =>
wb_dat_o(31 downto 16) <= (others => Undefined);
wb_dat_o(15 downto 0) <= crcB_q;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
poly_q <= x"A001";
crc_q <= x"FFFF";
ready_q <= '1';
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' and ready_q='1' then
case wb_adr_i(4 downto 2) is
when "000" =>
crc_q <= wb_dat_i(15 downto 0);
when "001" =>
poly_q <= wb_dat_i(15 downto 0);
when "010" =>
ready_q <= '0';
count_q <= 0;
data_q <= wb_dat_i(7 downto 0);
crcA_q <= crc_q;
crcB_q <= crcA_q;
when others =>
end case;
end if;
if ready_q='0' then
if (crc_q(0) xor data_q(0))='1' then
crc_q <= ( '0' & crc_q(15 downto 1)) xor poly_q;
else
crc_q <= '0' & crc_q(15 downto 1);
end if;
data_q <= '0' & data_q(7 downto 1);
if count_q=7 then
count_q <= 0;
ready_q <= '1';
else
count_q <= count_q + 1;
end if;
end if;
end if;
end if;
end process;
end behave;
| mit | 76665df95521168585ae312756886a53 | 0.549383 | 2.715976 | false | false | false | false |
sinkswim/DLX-Pro | synthesis/DLX_synthesis_cfg/a.b-DataPath.core/a.b.f-IF_ID_Reg.vhd | 1 | 2,812 | --------------------------------------------------------------------------------------------
-- IF/ID Pipeline register
-- It recieves as input data coming from the fetch stage:
-- - PC +4
-- - Instruction fetched
-- Then flush signal in case it has been requested to flush the pipeline, the IFDWrite
-- driven by the Hazard Detection Unit (it is used to freeze the regiter in case of stall)
-- The reset is synchronous with respect to the clock, whereas the flush is asynchronous
--------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.globals.all;
--------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------
entity ifid_reg is
port (
-- INPUTS
pc_4 : in std_logic_vector(31 downto 0); -- PC + 4 coming from the fetch stage
instruction_fetch : in std_logic_vector(31 downto 0); -- Instruction to be decoded
flush : in std_logic; -- flush control signal
ifid_write : in std_logic; -- write enable
clk : in std_logic; -- clock signal
rst : in std_logic; -- reset signal
-- OUTPUTS
instruction_decode : out std_logic_vector(31 downto 0); -- Instruction for the decode stage
new_pc : out std_logic_vector(31 downto 0) -- PC + 4 directed to the next pipeline register
);
end ifid_reg;
--------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------
architecture behavioral of ifid_reg is
begin
----------------------------
-- Name: Reg_Proc
-- Type: Sequential
-- Purpose: Implement the
-- behavior of the pipeline
-- register. Reset is
-- synchronous.
----------------------------
Reg_proc:process(clk, flush)
begin
if (flush = '1') then
new_pc <= (others => '0'); -- the value is not important since we are forcing a nop, thus this value will be never used
instruction_decode <= N_TYPE_NOP & "00000000000000000000000000";
elsif (clk = '1' and clk'event) then
if (rst = '1') then
new_pc <= (others => '0');
instruction_decode <= N_TYPE_NOP & "00000000000000000000000000";
elsif (ifid_write = '1') then
new_pc <= pc_4;
instruction_decode <= instruction_fetch;
end if;
end if;
end process;
end behavioral;
| mit | 6e71689eb93634d2c025f5283c6e8270 | 0.442034 | 5.207407 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/zpuino_debug_core_hyperion.vhd | 13 | 5,403 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
entity zpuino_debug_core_hyperion is
port (
clk: in std_logic;
rst: in std_logic;
dbg_in: in zpu_dbg_out_type;
dbg_out: out zpu_dbg_in_type;
dbg_reset: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end entity;
architecture behave of zpuino_debug_core_hyperion is
signal enter_ss: std_logic :='0';
signal step: std_logic := '0';
signal status_injection_ready: std_logic;
signal status_injectmode: std_logic;
type state_type is (
state_idle,
state_debug,
state_enter_inject,
state_flush,
state_inject,
state_leave_inject,
state_step
);
type dbgregs_type is record
state: state_type;
step: std_logic;
inject: std_logic;
freeze: std_logic;
injectmode: std_logic;
reset: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
signal dbgr: dbgregs_type;
signal injected: std_logic;
signal inject_q_in: std_logic := '0';
signal inject_q: std_logic := '0';
alias jtag_debug: std_logic is jtag_ctrl_chain_in(0);
alias jtag_inject: std_logic is jtag_ctrl_chain_in(1);
alias jtag_step: std_logic is jtag_ctrl_chain_in(2);
alias jtag_reset: std_logic is jtag_ctrl_chain_in(3);
alias jtag_opcode: std_logic_vector(7 downto 0) is jtag_ctrl_chain_in(11 downto 4);
signal pc_i: std_logic_vector(wordSize-1 downto 0);
signal sp_i: std_logic_vector(wordSize-1 downto 0);
begin
pc_i(wordSize-1 downto dbg_in.pc'high+1) <= (others => '0');
pc_i(dbg_in.pc'high downto dbg_in.pc'low) <= dbg_in.pc;
sp_i(wordSize-1 downto dbg_in.sp'high+1) <= (others => '0');
sp_i(dbg_in.sp'high downto dbg_in.sp'low) <= dbg_in.sp;
sp_i(dbg_in.sp'low-1 downto 0) <= (others => '0');
-- jtag chain output
jtag_data_chain_out <=
dbg_in.idim &
sp_i &
dbg_in.stacka &
pc_i &
dbg_in.brk &
status_injection_ready
;
status_injection_ready <= '1' when dbgr.state = state_debug else '0';
process(clk, rst, dbgr, dbg_in.valid, jtag_debug, jtag_opcode,
inject_q, dbg_in.ready, dbg_in.pc, dbg_in.idim, jtag_ctrl_chain_in)
variable w: dbgregs_type;
begin
w := dbgr;
if rst='1' then
w.state := state_idle;
w.reset := '0';
w.flush := '0';
w.injectmode := '0';
w.inject := '0';
w.step := '0';
w.freeze := '0';
injected <= '0';
else
injected <= '0';
case dbgr.state is
when state_idle =>
w.freeze := '0';
--if jtag_debug='1' then
-- w.freeze := '1';
-- w.state := state_debug;
--end if;
if jtag_debug='1' then
--if dbg_ready='1' then
w.injectmode := '1';
--w.opcode := jtag_opcode;
-- end if;
-- Wait for pipeline to finish
if dbg_in.valid='0' and dbg_in.ready='1' then
--report "Enter PC " & hstr(dbg_pc) & " IDIM flag " & chr(dbg_idim) severity note;
w.state:=state_debug;
end if;
--end if;
end if;
when state_debug =>
w.step := '0';
if inject_q='1' then
w.state := state_enter_inject;
w.injectmode := '1';
w.opcode := jtag_opcode;
elsif jtag_debug='0' then
w.flush:='1';
w.state := state_leave_inject;
end if;
when state_leave_inject =>
w.flush := '0';
w.injectmode:='0';
w.state := state_idle;
when state_enter_inject =>
-- w.state := state_flush;
w.state := state_inject;
when state_flush =>
w.flush := '1';
w.state := state_inject;
when state_inject =>
w.inject := '1';
w.flush := '0';
-- Here ?
injected <= '1';
w.state := state_step;
when state_step =>
injected <= '0';
w.inject := '0';
if dbg_in.valid='1' then
-- w.step := '1';
w.state := state_debug;
end if;
when others =>
end case;
end if;
if rising_edge(clk) then
dbgr <= w;
end if;
end process;
dbg_out.freeze <= dbgr.freeze;
--dbg_reset <= dbgr.reset;
dbg_out.inject <= dbgr.inject;
dbg_out.injectmode <= dbgr.injectmode;-- and dbg_ready;
dbg_out.step <= dbgr.step;
dbg_out.flush <= dbgr.flush;
dbg_out.opcode <= dbgr.opcode;
process(clk)
begin
if rising_edge(clk) then
dbg_reset <= jtag_ctrl_chain_in(3);
end if;
end process;
-- Synchronization stuff
process(jtag_inject, clk, injected, inject_q_in)
begin
if injected='1' then
inject_q <= '0';
inject_q_in <= '0';
else
if rising_edge(jtag_inject) then
inject_q_in <= '1';
--else
-- inject_q_in <= inject_q_in;
end if;
if rising_edge(clk) then
inject_q <= inject_q_in;
end if;
end if;
end process;
end behave;
| mit | 28abc138a64d51751be9e046473dda50 | 0.540626 | 3.183854 | false | false | false | false |
chcbaram/FPGA | ZPUino_miniSpartan6_plus/ipcore_dir/I2C/i2c_master_byte_ctrl.vhdl | 1 | 19,994 | ------------------------------------------------------------------------------
---- ----
---- I2C Master Core (Byte Controller) ----
---- ----
---- Internal file, can't be downloaded. ----
---- Based on code from: http://www.opencores.org/projects/i2c/ ----
---- ----
---- Description: ----
---- I2C master peripheral for the Wishbone bus. ----
---- Byte controller stuff. That's almost the same code from OpenCores. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Authors: ----
---- - Richard Herveille, [email protected] ----
---- - Salvador E. Tropea, salvador en inti gov ar (small changes) ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2005 Salvador E. Tropea <salvador en inti gov ar> ----
---- Copyright (c) 2005 Instituto Nacional de Tecnología Industrial ----
---- Copyright (c) 2000 Richard Herveille <[email protected]> ----
---- ----
---- Covered by the GPL license. ----
---- ----
---- Original distribution policy: ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: I2C_MasterByteCtrl(Structural) (Entity and arch.) ----
---- File name: i2c_master_byte_ctrl.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: i2c_mwb ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA: Spartan II (XC2S100-5-PQ208) ----
---- Language: VHDL ----
---- Wishbone: None ----
---- Synthesis tools: Xilinx Release 6.2.03i - xst G.31a ----
---- Simulation tools: GHDL [Sokcho edition] (0.1x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
--
-- CVS Log
--
-- $Id: i2c_master_byte_ctrl.vhdl,v 1.8 2006/04/17 19:44:43 salvador Exp $
--
-- $Date: 2006/04/17 19:44:43 $
-- $Revision: 1.8 $
-- $Author: salvador $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: i2c_master_byte_ctrl.vhdl,v $
-- Revision 1.8 2006/04/17 19:44:43 salvador
-- * Modified: License to GPL.
--
-- Revision 1.7 2005/05/20 14:39:05 salvador
-- * Modificado: Mejorado el indentado usando bakalint 0.3.7.
--
-- Revision 1.6 2005/05/18 14:50:19 salvador
-- * Modificado: Los encabezados de los archivos para que cumplan con nuestras
-- recomendaciones.
--
-- Revision 1.5 2005/05/11 22:39:17 salvador
-- * Modificado: Pasado por el bakalint 0.3.5.
--
-- Revision 1.4 2005/03/29 20:35:44 salvador
-- * Modificado: Encerrado con "translate off/on" el código de simulación para
-- que el XST no moleste.
-- * Agregado: Un generic para que las interrupciones esten siempre
-- habilitadas.
-- * Agregado: Default para wb_cyc_i de manera tal que no sea necesario
-- conectarlo.
-- * Modificado: Para ahorrar algunos F/F en registros que tienen bits sin
-- usar. A consecuencia de esto el bit "iack" se corrió.
--
-- Revision 1.3 2005/03/10 19:40:07 salvador
-- * Modificado: Para usar "rising_edge" que hace más legible el código.
-- * Agregado: MUX_BETTER para elegir que use muxs en lugar de tri-states.
-- Por defecto es falso con lo que ahorra unos 12 slice.
-- * Agregado: FULL_SYNC para lograr el comportamiento original con 1 WS.
-- * Agregado: FIXED_PRER con lo que se puede fijar el valor del prescaler lo
-- que ahorra unos 11 slice.
-- * Modificado: Los case de lectura/escritura de los registros por if/elsif
-- que permite controlar mejor el uso de los generic.
-- * Modificado: El testbench para que soporte FIXED_PRER.
--
-- Revision 1.2 2005/03/09 17:41:16 salvador
-- * Agregado: Hojas de datos del 24LC02B.
-- * Modificado: Reemplazo de Report por Assert porque las herramientas de
-- Xilinx no lo soportan.
-- * Modificado: Comentado los printf en core porque no tengo el equivalente
-- para Xilinx.
-- * Corregido: El TB de la memoria no contestaba ACK luego de la escritura.
-- Ahora si y además el TB verifica que no falten ACKs.
--
-- Revision 1.1 2005/03/08 15:57:36 salvador
-- * Movido al repositorio CVS.
-- * Agregado: TestBench en VHDL.
--
-- Revision 1.5 2004/02/18 11:41:48 rherveille
-- Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command.
--
-- Revision 1.4 2003/08/09 07:01:13 rherveille
-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
-- Fixed a potential bug in the byte controller's host-acknowledge generation.
--
-- Revision 1.3 2002/12/26 16:05:47 rherveille
-- Core is now a Multimaster I2C controller.
--
-- Revision 1.2 2002/11/30 22:24:37 rherveille
-- Cleaned up code
--
-- Revision 1.1 2001/11/05 12:02:33 rherveille
-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
-- Code updated, is now up-to-date to doc. rev.0.4.
-- Added headers.
--
--
------------------------------------------
-- Byte controller section
------------------------------------------
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity I2C_MasterByteCtrl is
port (
wb_clk_i : in std_logic;
wb_rst_i : in std_logic; -- synchronous active high reset (WISHBONE compatible)
nreset_i : in std_logic; -- asynchornous active low reset (FPGA compatible)
ena_i : in std_logic; -- core enable signal
clk_cnt_i : in unsigned(15 downto 0); -- 4x SCL
-- input signals
start_i : in std_logic;
stop_i : in std_logic;
read_i : in std_logic;
write_i : in std_logic;
ack_in_i : in std_logic;
din_i : in std_logic_vector(7 downto 0);
-- output signals
cmd_ack_o : out std_logic; -- command done
ack_out_o : out std_logic;
i2c_busy_o : out std_logic; -- arbitration lost
i2c_al_o : out std_logic; -- i2c bus busy
dout_o : out std_logic_vector(7 downto 0);
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen_o : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen_o : out std_logic -- i2c data line output enable, active low
);
end entity I2C_MasterByteCtrl;
architecture Structural of I2C_MasterByteCtrl is
component I2C_MasterBitCtrl is
port (
wb_clk_i : in std_logic;
wb_rst_i : in std_logic;
nreset_i : in std_logic;
ena_i : in std_logic; -- core enable signal
clk_cnt_i : in unsigned(15 downto 0); -- clock prescale value
cmd_i : in std_logic_vector(3 downto 0);
cmd_ack_o : out std_logic; -- command done
busy_o : out std_logic; -- i2c bus busy
al_o : out std_logic; -- arbitration lost
din_i : in std_logic;
dout_o : out std_logic;
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen_o : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen_o : out std_logic -- i2c data line output enable, active low
);
end component I2C_MasterBitCtrl;
-- commands for bit_controller block
constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";
constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";
constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";
constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100";
constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000";
-- signals for bit_controller
signal core_cmd : std_logic_vector(3 downto 0);
signal core_ack : std_logic;
signal core_txd : std_logic;
signal core_rxd : std_logic;
signal al_o : std_logic;
-- signals for shift register
signal sr : std_logic_vector(7 downto 0); -- 8bit shift register
signal shift, ld : std_logic;
-- signals for state machine
signal go, host_ack : std_logic;
signal dcnt : unsigned(2 downto 0); -- data counter
signal cnt_done : std_logic;
begin
-- hookup bit_controller
bit_ctrl: I2C_MasterBitCtrl
port map(
wb_clk_i=> wb_clk_i,
wb_rst_i=> wb_rst_i,
nreset_i=> nreset_i,
ena_i => ena_i,
clk_cnt_i=> clk_cnt_i,
cmd_i => core_cmd,
cmd_ack_o=> core_ack,
busy_o => i2c_busy_o,
al_o => al_o,
din_i => core_txd,
dout_o => core_rxd,
scl_i => scl_i,
scl_o => scl_o,
scl_oen_o=> scl_oen_o,
sda_i => sda_i,
sda_o => sda_o,
sda_oen_o=> sda_oen_o );
i2c_al_o<= al_o;
-- generate host-command-acknowledge
cmd_ack_o<= host_ack;
-- generate go-signal
go <= (read_i or write_i or stop_i) and not host_ack;
-- assign Dout output to shift-register
dout_o<= sr;
-- generate shift register
shift_register:
process(wb_clk_i, nreset_i)
begin
if (nreset_i= '0') then
sr <= (others => '0');
elsif rising_edge(wb_clk_i) then
if (wb_rst_i= '1') then
sr <= (others => '0');
elsif (ld = '1') then
sr <= din_i;
elsif (shift = '1') then
sr <= (sr(6 downto 0) & core_rxd);
end if;
end if;
end process shift_register;
-- generate data-counter
data_cnt:
process(wb_clk_i, nreset_i)
begin
if (nreset_i= '0') then
dcnt <= (others => '0');
elsif rising_edge(wb_clk_i) then
if (wb_rst_i= '1') then
dcnt <= (others => '0');
elsif (ld = '1') then
dcnt <= (others => '1'); -- load counter with 7
elsif (shift = '1') then
dcnt <= dcnt -1;
end if;
end if;
end process data_cnt;
cnt_done <= '1' when (dcnt = 0) else '0';
--
-- state machine
--
statemachine:
block
type states is (st_idle, st_start, st_read, st_write, st_ack, st_stop);
signal c_state : states;
begin
--
-- command interpreter, translate complex commands into simpler I2C commands
--
nxt_state_decoder:
process(wb_clk_i, nreset_i)
begin
if (nreset_i= '0') then
core_cmd <= I2C_CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
host_ack <= '0';
c_state <= st_idle;
ack_out_o<= '0';
elsif rising_edge(wb_clk_i) then
if (wb_rst_i= '1' or al_o= '1') then
core_cmd <= I2C_CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
host_ack <= '0';
c_state <= st_idle;
ack_out_o<= '0';
else
-- initialy reset all signal
core_txd <= sr(7);
shift <= '0';
ld <= '0';
host_ack <= '0';
case c_state is
when st_idle =>
if (go = '1') then
if (start_i= '1') then
c_state <= st_start;
core_cmd <= I2C_CMD_START;
elsif (read_i= '1') then
c_state <= st_read;
core_cmd <= I2C_CMD_READ;
elsif (write_i= '1') then
c_state <= st_write;
core_cmd <= I2C_CMD_WRITE;
else -- stop
c_state <= st_stop;
core_cmd <= I2C_CMD_STOP;
end if;
ld <= '1';
end if;
when st_start =>
if (core_ack = '1') then
if (read_i= '1') then
c_state <= st_read;
core_cmd <= I2C_CMD_READ;
else
c_state <= st_write;
core_cmd <= I2C_CMD_WRITE;
end if;
ld <= '1';
end if;
when st_write =>
if (core_ack = '1') then
if (cnt_done = '1') then
c_state <= st_ack;
core_cmd <= I2C_CMD_READ;
else
c_state <= st_write; -- stay in same state
core_cmd <= I2C_CMD_WRITE; -- write next bit
shift <= '1';
end if;
end if;
when st_read =>
if (core_ack = '1') then
if (cnt_done = '1') then
c_state <= st_ack;
core_cmd <= I2C_CMD_WRITE;
else
c_state <= st_read; -- stay in same state
core_cmd <= I2C_CMD_READ; -- read next bit
end if;
shift <= '1';
core_txd <= ack_in_i;
end if;
when st_ack =>
if (core_ack = '1') then
-- check for stop; Should a STOP command be generated ?
if (stop_i= '1') then
c_state <= st_stop;
core_cmd <= I2C_CMD_STOP;
else
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
-- generate command acknowledge signal
host_ack <= '1';
end if;
-- assign ack_out output to core_rxd (contains last received bit)
ack_out_o<= core_rxd;
core_txd <= '1';
else
core_txd <= ack_in_i;
end if;
when st_stop =>
if (core_ack = '1') then
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
-- generate command acknowledge signal
host_ack <= '1';
end if;
when others => -- illegal states
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
--synopsys translate off
assert false
report "Byte controller entered illegal state."
severity failure;
--synopsys translate on
end case;
end if;
end if;
end process nxt_state_decoder;
end block statemachine;
end architecture Structural;
| mit | 96afc22545cd41268f89c694d49015e5 | 0.415475 | 4.318359 | false | false | false | false |
bsmerbeckuri/SHA512Optimization | CPU_System/Rhody_CPU_pipelinev11.vhd | 1 | 37,085 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Rhody_CPU_pipelinev11 is
port ( clk : in std_logic;
rst : in std_logic;
MEM_ADR : out std_logic_vector(31 downto 0);
MEM_IN : in std_logic_vector(31 downto 0);
MEM_OUT : out std_logic_vector(31 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
key : in std_logic;
LEDR : out std_logic_vector(3 downto 0)
);
end;
architecture Structural of Rhody_CPU_pipelinev11 is
-- state machine: CPU_state
type State_type is (S1, S2);
signal update, stage1, stage2, stage3, stage4, stage5, stage6, stage7, stage8, stage9, stage10, stage11, stage12,
stage13, stage14, stage15, stage16, stage17: State_type;
-- Register File: 8x32
type reg_file_type is array (0 to 7) of std_logic_vector(31 downto 0);
signal register_file : reg_file_type;
-- Internal registers
signal MDR_in, MDR_out, MAR, PSW: std_logic_vector(31 downto 0);
signal PC, SP: unsigned(31 downto 0); --unsigned for arithemtic operations
-- Internal control signals
signal operand0, operand1, ALU_out : std_logic_vector(31 downto 0);
signal carry, overflow, zero : std_logic;
-- Pipeline Istruction registers
signal stall: Boolean;
signal IR2, IR3, IR4, IR5, IR6, IR7, IR8, IR9, IR10, IR11, IR12, IR13, IR14, IR15 ,IR16, IR17: std_logic_vector(31 downto 0);
--Rhody Instruction Format
alias Opcode2: std_logic_vector(5 downto 0) is IR2(31 downto 26);
alias Opcode3: std_logic_vector(5 downto 0) is IR3(31 downto 26);
alias Opcode4: std_logic_vector(5 downto 0) is IR4(31 downto 26);
alias Opcode5: std_logic_vector(5 downto 0) is IR5(31 downto 26);
alias Opcode6: std_logic_vector(5 downto 0) is IR6(31 downto 26);
alias Opcode7: std_logic_vector(5 downto 0) is IR7(31 downto 26);
alias Opcode8: std_logic_vector(5 downto 0) is IR8(31 downto 26);
alias Opcode9: std_logic_vector(5 downto 0) is IR9(31 downto 26);
alias Opcode10: std_logic_vector(5 downto 0) is IR10(31 downto 26);
alias Opcode11: std_logic_vector(5 downto 0) is IR11(31 downto 26);
alias Opcode12: std_logic_vector(5 downto 0) is IR12(31 downto 26);
alias Opcode13: std_logic_vector(5 downto 0) is IR13(31 downto 26);
alias Opcode14: std_logic_vector(5 downto 0) is IR14(31 downto 26);
alias Opcode15: std_logic_vector(5 downto 0) is IR15(31 downto 26);
alias Opcode16: std_logic_vector(5 downto 0) is IR16(31 downto 26);
alias Opcode17: std_logic_vector(5 downto 0) is IR17(31 downto 26);
alias RX2 : std_logic_vector(2 downto 0) is IR2(25 downto 23);
alias RX3 : std_logic_vector(2 downto 0) is IR3(25 downto 23);
alias RY2 : std_logic_vector(2 downto 0) is IR2(22 downto 20);
alias RZ2 : std_logic_vector(2 downto 0) is IR2(19 downto 17);
alias RA2 : std_logic_vector(2 downto 0) is IR2(16 downto 14);
alias RB2 : std_logic_vector(2 downto 0) is IR2(13 downto 11);
alias RB3 : std_logic_vector(2 downto 0) is IR2(13 downto 11);
alias RC2 : std_logic_vector(2 downto 0) is IR2(10 downto 8);
alias RC3 : std_logic_vector(2 downto 0) is IR2(10 downto 8);
alias RD2 : std_logic_vector(2 downto 0) is IR2(7 downto 5);
alias RE2 : std_logic_vector(2 downto 0) is IR2(4 downto 2);
alias I2 : std_logic_vector(15 downto 0) is IR2(15 downto 0);
alias M2 : std_logic_vector(19 downto 0) is IR2(19 downto 0);
alias M3 : std_logic_vector(19 downto 0) is IR3(19 downto 0);
-- Temporary control signals
signal tmpx, tmpy, tmpz, tmpa: std_logic_vector(31 downto 0);
--Condition Codes
alias Z: std_logic is PSW(0);
alias C: std_logic is PSW(1);
alias S: std_logic is PSW(2);
alias V: std_logic is PSW(3);
--Instruction Opcodes
constant NOP : std_logic_vector(5 downto 0) := "000000";
--constant ADD64: std_logic_vector(5 downto 0) := "000001";
--constant T2 : std_logic_vector(5 downto 0) := "000010";
constant LDM : std_logic_vector(5 downto 0) := "000100";
constant LDR : std_logic_vector(5 downto 0) := "000101";
constant LDIX : std_logic_vector(5 downto 0) := "000110";
constant STIX : std_logic_vector(5 downto 0) := "000111";
constant LDH : std_logic_vector(5 downto 0) := "001000";
constant LDL : std_logic_vector(5 downto 0) := "001001";
constant LDI : std_logic_vector(5 downto 0) := "001010";
constant MOV : std_logic_vector(5 downto 0) := "001011";
constant STM : std_logic_vector(5 downto 0) := "001100";
constant STR : std_logic_vector(5 downto 0) := "001101";
constant ADD : std_logic_vector(5 downto 0) := "010000";
constant ADI : std_logic_vector(5 downto 0) := "010001";
constant SUB : std_logic_vector(5 downto 0) := "010010";
constant MUL : std_logic_vector(5 downto 0) := "010011";
constant IAND : std_logic_vector(5 downto 0) := "010100"; --avoid keyword
constant IOR : std_logic_vector(5 downto 0) := "010101"; --avoid keyword
constant IXOR : std_logic_vector(5 downto 0) := "010110"; --avoid keyword
constant IROR : std_logic_vector(5 downto 0) := "010111"; --avoid keyword
constant JNZ : std_logic_vector(5 downto 0) := "100000";
constant JNS : std_logic_vector(5 downto 0) := "100001";
constant JNV : std_logic_vector(5 downto 0) := "100010";
constant JNC : std_logic_vector(5 downto 0) := "100011";
constant JZ : std_logic_vector(5 downto 0) := "100100";
constant JS : std_logic_vector(5 downto 0) := "100101";
constant JV : std_logic_vector(5 downto 0) := "100110";
constant JC : std_logic_vector(5 downto 0) := "100111";
constant JMP : std_logic_vector(5 downto 0) := "101000";
constant CMP : std_logic_vector(5 downto 0) := "101010";
--constant T11 : std_logic_vector(5 downto 0) := "101110";
--constant T12 : std_logic_vector(5 downto 0) := "101111";
constant CALL : std_logic_vector(5 downto 0) := "110000";
constant CMPI : std_logic_vector(5 downto 0) := "110010";
constant RET : std_logic_vector(5 downto 0) := "110100";
constant RETI : std_logic_vector(5 downto 0) := "110101";
constant PUSH : std_logic_vector(5 downto 0) := "111000";
constant POP : std_logic_vector(5 downto 0) := "111001";
constant SYS : std_logic_vector(5 downto 0) := "111100";
--constant SIG0 : std_logic_vector(5 downto 0) := "111110";
--constant SIG1 : std_logic_vector(5 downto 0) := "111111";
constant MLOAD0 : std_logic_vector(5 downto 0) := "011001";
constant MLOAD1 : std_logic_vector(5 downto 0) := "011010";
constant MLOAD2 : std_logic_vector(5 downto 0) := "011011";
constant MLOAD3 : std_logic_vector(5 downto 0) := "011100";
--constant WLOAD : std_logic_vector(5 downto 0) := "011101";
constant ROUND1 : std_logic_vector(5 downto 0) := "101100";
constant FIN : std_logic_vector(5 downto 0) := "101101";
constant MSTM0 : std_logic_vector(5 downto 0) := "101001";
constant MSTM1 : std_logic_vector(5 downto 0) := "101011";
constant LDMD : std_logic_vector(5 downto 0) := "111010";
constant WPAD : std_logic_vector(5 downto 0) := "111011";
constant WORD_BITS : integer := 64;
subtype WORD_TYPE is std_logic_vector(63 downto 0);
type WORD_VECTOR is array (INTEGER range <>) of WORD_TYPE;
constant WORD_NULL : WORD_TYPE := (others => '0');
--shared variable w_80 : WORD_VECTOR(0 to 79);
----------------------------------------------------------------
constant K_TABLE : WORD_VECTOR(0 to 79) := (
0 => To_StdLogicVector(bit_vector'(X"428a2f98d728ae22")),
1 => To_StdLogicVector(bit_vector'(X"7137449123ef65cd")),
2 => To_StdLogicVector(bit_vector'(X"b5c0fbcfec4d3b2f")),
3 => To_StdLogicVector(bit_vector'(X"e9b5dba58189dbbc")),
4 => To_StdLogicVector(bit_vector'(X"3956c25bf348b538")),
5 => To_StdLogicVector(bit_vector'(X"59f111f1b605d019")),
6 => To_StdLogicVector(bit_vector'(X"923f82a4af194f9b")),
7 => To_StdLogicVector(bit_vector'(X"ab1c5ed5da6d8118")),
8 => To_StdLogicVector(bit_vector'(X"d807aa98a3030242")),
9 => To_StdLogicVector(bit_vector'(X"12835b0145706fbe")),
10 => To_StdLogicVector(bit_vector'(X"243185be4ee4b28c")),
11 => To_StdLogicVector(bit_vector'(X"550c7dc3d5ffb4e2")),
12 => To_StdLogicVector(bit_vector'(X"72be5d74f27b896f")),
13 => To_StdLogicVector(bit_vector'(X"80deb1fe3b1696b1")),
14 => To_StdLogicVector(bit_vector'(X"9bdc06a725c71235")),
15 => To_StdLogicVector(bit_vector'(X"c19bf174cf692694")),
16 => To_StdLogicVector(bit_vector'(X"e49b69c19ef14ad2")),
17 => To_StdLogicVector(bit_vector'(X"efbe4786384f25e3")),
18 => To_StdLogicVector(bit_vector'(X"0fc19dc68b8cd5b5")),
19 => To_StdLogicVector(bit_vector'(X"240ca1cc77ac9c65")),
20 => To_StdLogicVector(bit_vector'(X"2de92c6f592b0275")),
21 => To_StdLogicVector(bit_vector'(X"4a7484aa6ea6e483")),
22 => To_StdLogicVector(bit_vector'(X"5cb0a9dcbd41fbd4")),
23 => To_StdLogicVector(bit_vector'(X"76f988da831153b5")),
24 => To_StdLogicVector(bit_vector'(X"983e5152ee66dfab")),
25 => To_StdLogicVector(bit_vector'(X"a831c66d2db43210")),
26 => To_StdLogicVector(bit_vector'(X"b00327c898fb213f")),
27 => To_StdLogicVector(bit_vector'(X"bf597fc7beef0ee4")),
28 => To_StdLogicVector(bit_vector'(X"c6e00bf33da88fc2")),
29 => To_StdLogicVector(bit_vector'(X"d5a79147930aa725")),
30 => To_StdLogicVector(bit_vector'(X"06ca6351e003826f")),
31 => To_StdLogicVector(bit_vector'(X"142929670a0e6e70")),
32 => To_StdLogicVector(bit_vector'(X"27b70a8546d22ffc")),
33 => To_StdLogicVector(bit_vector'(X"2e1b21385c26c926")),
34 => To_StdLogicVector(bit_vector'(X"4d2c6dfc5ac42aed")),
35 => To_StdLogicVector(bit_vector'(X"53380d139d95b3df")),
36 => To_StdLogicVector(bit_vector'(X"650a73548baf63de")),
37 => To_StdLogicVector(bit_vector'(X"766a0abb3c77b2a8")),
38 => To_StdLogicVector(bit_vector'(X"81c2c92e47edaee6")),
39 => To_StdLogicVector(bit_vector'(X"92722c851482353b")),
40 => To_StdLogicVector(bit_vector'(X"a2bfe8a14cf10364")),
41 => To_StdLogicVector(bit_vector'(X"a81a664bbc423001")),
42 => To_StdLogicVector(bit_vector'(X"c24b8b70d0f89791")),
43 => To_StdLogicVector(bit_vector'(X"c76c51a30654be30")),
44 => To_StdLogicVector(bit_vector'(X"d192e819d6ef5218")),
45 => To_StdLogicVector(bit_vector'(X"d69906245565a910")),
46 => To_StdLogicVector(bit_vector'(X"f40e35855771202a")),
47 => To_StdLogicVector(bit_vector'(X"106aa07032bbd1b8")),
48 => To_StdLogicVector(bit_vector'(X"19a4c116b8d2d0c8")),
49 => To_StdLogicVector(bit_vector'(X"1e376c085141ab53")),
50 => To_StdLogicVector(bit_vector'(X"2748774cdf8eeb99")),
51 => To_StdLogicVector(bit_vector'(X"34b0bcb5e19b48a8")),
52 => To_StdLogicVector(bit_vector'(X"391c0cb3c5c95a63")),
53 => To_StdLogicVector(bit_vector'(X"4ed8aa4ae3418acb")),
54 => To_StdLogicVector(bit_vector'(X"5b9cca4f7763e373")),
55 => To_StdLogicVector(bit_vector'(X"682e6ff3d6b2b8a3")),
56 => To_StdLogicVector(bit_vector'(X"748f82ee5defb2fc")),
57 => To_StdLogicVector(bit_vector'(X"78a5636f43172f60")),
58 => To_StdLogicVector(bit_vector'(X"84c87814a1f0ab72")),
59 => To_StdLogicVector(bit_vector'(X"8cc702081a6439ec")),
60 => To_StdLogicVector(bit_vector'(X"90befffa23631e28")),
61 => To_StdLogicVector(bit_vector'(X"a4506cebde82bde9")),
62 => To_StdLogicVector(bit_vector'(X"bef9a3f7b2c67915")),
63 => To_StdLogicVector(bit_vector'(X"c67178f2e372532b")),
64 => To_StdLogicVector(bit_vector'(X"ca273eceea26619c")),
65 => To_StdLogicVector(bit_vector'(X"d186b8c721c0c207")),
66 => To_StdLogicVector(bit_vector'(X"eada7dd6cde0eb1e")),
67 => To_StdLogicVector(bit_vector'(X"f57d4f7fee6ed178")),
68 => To_StdLogicVector(bit_vector'(X"06f067aa72176fba")),
69 => To_StdLogicVector(bit_vector'(X"0a637dc5a2c898a6")),
70 => To_StdLogicVector(bit_vector'(X"113f9804bef90dae")),
71 => To_StdLogicVector(bit_vector'(X"1b710b35131c471b")),
72 => To_StdLogicVector(bit_vector'(X"28db77f523047d84")),
73 => To_StdLogicVector(bit_vector'(X"32caab7b40c72493")),
74 => To_StdLogicVector(bit_vector'(X"3c9ebe0a15c9bebc")),
75 => To_StdLogicVector(bit_vector'(X"431d67c49c100d4c")),
76 => To_StdLogicVector(bit_vector'(X"4cc5d4becb3e42b6")),
77 => To_StdLogicVector(bit_vector'(X"597f299cfc657e2a")),
78 => To_StdLogicVector(bit_vector'(X"5fcb6fab3ad6faec")),
79 => To_StdLogicVector(bit_vector'(X"6c44198c4a475817"))
);
constant H0_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"6a09e667f3bcc908"));
constant H1_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"bb67ae8584caa73b"));
constant H2_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"3c6ef372fe94f82b"));
constant H3_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"a54ff53a5f1d36f1"));
constant H4_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"510e527fade682d1"));
constant H5_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"9b05688c2b3e6c1f"));
constant H6_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"1f83d9abfb41bd6b"));
constant H7_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"5be0cd19137e2179"));
-------------------------------------------------------------------------
signal dm0 : std_logic_vector(63 downto 0);
signal dm1 : std_logic_vector(63 downto 0);
signal dm2 : std_logic_vector(63 downto 0);
signal dm3 : std_logic_vector(63 downto 0);
signal dm4 : std_logic_vector(63 downto 0);
signal dm5 : std_logic_vector(63 downto 0);
signal dm6 : std_logic_vector(63 downto 0);
signal dm7 : std_logic_vector(63 downto 0);
signal dm8 : std_logic_vector(63 downto 0);
signal dm9 : std_logic_vector(63 downto 0);
signal dm10 : std_logic_vector(63 downto 0);
signal dm11 : std_logic_vector(63 downto 0);
signal dm12 : std_logic_vector(63 downto 0);
signal dm13 : std_logic_vector(63 downto 0);
signal dm14 : std_logic_vector(63 downto 0);
signal dm15 : std_logic_vector(63 downto 0);
-- a,b,c,d,e,f,g,h
signal wva : WORD_TYPE;
signal wvb : WORD_TYPE;
signal wvc : WORD_TYPE;
signal wvd : WORD_TYPE;
signal wve : WORD_TYPE;
signal wvf : WORD_TYPE;
signal wvg : WORD_TYPE;
signal wvh : WORD_TYPE;
signal t1_val : WORD_TYPE;
signal t2_val : WORD_TYPE;
signal rcount: integer := 0;
-- H0,H1,H2,H3,H4,H5,H6,H7
signal h0 : WORD_TYPE;
signal h1 : WORD_TYPE;
signal h2 : WORD_TYPE;
signal h3 : WORD_TYPE;
signal h4 : WORD_TYPE;
signal h5 : WORD_TYPE;
signal h6 : WORD_TYPE;
signal h7 : WORD_TYPE;
signal tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7: std_logic_vector(63 downto 0);
signal mvect : WORD_VECTOR(0 to 15);
signal wout: std_logic_vector(63 downto 0);
begin
--Display condition code on LEDR for debugging purpose
LEDR(3) <= Z when key='0' else '0';
LEDR(2) <= C when key='0' else '0';
LEDR(1) <= S when key='0' else '0';
LEDR(0) <= V when key='0' else '0';
--CPU bus interface
MEM_OUT <= MDR_out; --Outgoing data bus
MEM_ADR <= MAR; --Address bus
--One clock cycle delay in obtaining CPU_state, e.g. S1->S2
mem_rd <= '1' when ((Opcode2=LDM or Opcode2=LDR or Opcode2 = LDIX or Opcode2=LDMD) and stage2=S2) else
'1' when (Opcode3 = LDMD and stage3=S2) else
'1' when (Opcode4 = LDMD and stage4=S2) else
'1' when (Opcode5 = LDMD and stage5=S2) else
'1' when (Opcode6 = LDMD and stage6=S2) else
'1' when (Opcode7 = LDMD and stage7=S2) else
'1' when (Opcode8 = LDMD and stage8=S2) else
'1' when (Opcode9 = LDMD and stage9=S2) else
'1' when (Opcode10 = LDMD and stage10=S2) else
'1' when (Opcode11 = LDMD and stage11=S2) else
'1' when (Opcode12 = LDMD and stage12=S2) else
'1' when (Opcode13 = LDMD and stage13=S2) else
'1' when (Opcode14 = LDMD and stage14=S2) else
'1' when (Opcode15 = LDMD and stage15=S2) else
'1' when (Opcode16 = LDMD and stage16=S2) else
'1' when (Opcode17 = LDMD and stage17=S2) else
'1' when (stage1=S2 and not stall) else
'1' when ((Opcode2=POP or Opcode2=RET) and stage2=S2) else
'1' when (Opcode2=RETI and stage2=S2) else
'1' when (Opcode3=RETI and stage3=S2) else
'0'; --Memory read control signal
mem_wr <= '1' when ((Opcode3=STM or Opcode3=STR or Opcode3=STIX) and stage3=S1) else
'1' when ((Opcode3=PUSH or Opcode3=CALL) and stage3=S2) else
'1' when (Opcode3=SYS and stage3=S2) else
'1' when (Opcode4=SYS and stage4=S2) else
'0'; --Memory write control signal
stall <= true when(Opcode2=LDM or Opcode2=LDR or Opcode2 = LDIX or Opcode2 = LDMD or Opcode2=STM or Opcode2=STR or Opcode2=STIX or Opcode2=WPAD) else
true when(Opcode2=CALL or Opcode2=PUSH or Opcode2=POP or Opcode2=RET
or Opcode2=SYS or Opcode2=RETI) else
true when(Opcode3 = LDMD or Opcode3=CALL or Opcode3=RET or Opcode3=PUSH
or Opcode3=SYS or Opcode3=RETI) else
true when(Opcode4=SYS or Opcode4=RETI or Opcode4 = LDMD) else
true when(Opcode5=SYS or Opcode4=RETI or Opcode5 = LDMD) else
true when(Opcode6 = LDMD) else
true when(Opcode7 = LDMD) else
true when(Opcode8 = LDMD) else
true when(Opcode9 = LDMD) else
true when(Opcode10 = LDMD) else
true when(Opcode11 = LDMD) else
true when(Opcode12 = LDMD) else
true when(Opcode13 = LDMD) else
true when(Opcode14 = LDMD) else
true when(Opcode15 = LDMD) else
true when(Opcode16 = LDMD) else
true when(Opcode17 = LDMD) else
false;
--The state machine that is CPU
CPU_State_Machine: process (clk, rst)
begin
if rst='1' then
update <= S1;
stage1 <= S1;
stage2 <= S1;
stage3 <= S1;
stage4 <= S1;
PC <= x"00000000"; --initialize PC
SP <= x"000FF7FF"; --initialize SP
IR2 <= x"00000000";
IR3 <= x"00000000";
IR4 <= x"00000000";
IR5 <= x"00000000";
IR6 <= x"00000000";
IR7 <= x"00000000";
IR8 <= x"00000000";
IR9 <= x"00000000";
IR10 <= x"00000000";
IR11 <= x"00000000";
IR12 <= x"00000000";
IR13 <= x"00000000";
IR14 <= x"00000000";
IR15 <= x"00000000";
IR16 <= x"00000000";
IR17 <= x"00000000";
elsif clk'event and clk = '1' then
case update is
when S1 =>
update <= S2;
when S2 =>
if (stall or
(Opcode2=JNZ and Z='1') or (Opcode2=JZ and Z='0') or
(Opcode2=JNS and S='1') or (Opcode2=JS and S='0') or
(Opcode2=JNV and V='1') or (Opcode2=JV and V='0') or
(Opcode2=JNC and C='1') or (Opcode2=JC and C='0') ) then
IR2 <= x"00000000"; --insert NOP
else
IR2 <= MEM_in;
end if;
IR3 <= IR2;
IR4 <= IR3;
update <= S1;
when others =>
null;
end case;
case stage1 is
when S1 =>
if (not stall) then
if(Opcode2=JMP or Opcode2=JNZ or Opcode2=JZ or Opcode2=JNS or
Opcode2=JS or Opcode2=JNV or Opcode2=JV or
Opcode2=JNC or Opcode2=JC) then
MAR <= x"000" & M2;
else
MAR <= std_logic_vector(PC);
end if;
end if;
stage1 <= S2;
when S2 =>
if (not stall) then
if (Opcode2=JMP or
(Opcode2=JNZ and Z='0') or (Opcode2=JZ and Z='1') or
(Opcode2=JNS and S='0') or (Opcode2=JS and S='1') or
(Opcode2=JNV and V='0') or (Opcode2=JV and V='1') or
(Opcode2=JNC and C='0') or (Opcode2=JC and C='1') ) then
PC <= (x"000" & unsigned(M2))+1;
elsif ((Opcode2=JNZ and Z='1') or (Opcode2=JZ and Z = '0') or
(Opcode2=JNS and S = '1')or (Opcode2=JS and S = '0') or
(Opcode2=JNV and V = '1') or (Opcode2=JV and V = '0') or
(Opcode2=JNC and C = '1') or (Opcode2=JC and C = '0')) then
null;
else
PC <= PC + 1;
end if;
end if;
stage1 <= S1;
when others =>
null;
end case;
case stage2 is
when S1 =>
if (Opcode2=LDI) then
register_file(to_integer(unsigned(RX2)))<=(31 downto 16=>I2(15)) & I2;
elsif (Opcode2=LDH) then
register_file(to_integer(unsigned(RX2)))
<= I2 & register_file(to_integer(unsigned(RX2)))(15 downto 0);
--(31 downto 16)<= I2;
elsif (Opcode2=LDL) then
register_file(to_integer(unsigned(RX2)))
<= register_file(to_integer(unsigned(RX2)))(31 downto 16) & I2;
--(15 downto 0)<= I2;
elsif (Opcode2=MOV) then
register_file(to_integer(unsigned(RX2)))<=register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=ADD or Opcode2=SUB or Opcode2=MUL or Opcode2=CMP or
Opcode2=IAND or Opcode2=IOR or Opcode2=IXOR) then
operand1 <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=IROR) then
null;
elsif (Opcode2=ADI or Opcode2=CMPI) then
operand1 <= (31 downto 16=>I2(15)) & I2;
elsif (Opcode2=LDM) then
MAR <= x"000" & M2;
elsif (Opcode2=LDR) then
MAR <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=LDIX) then
MAR <= std_logic_vector(unsigned(
register_file(to_integer(unsigned(RY2))))
+ unsigned(M2));
elsif (Opcode2=STM) then
MAR <= x"000" & M2; MDR_out <= register_file(to_integer(unsigned(RX2)));
elsif (Opcode2=STR) then
MAR <= register_file(to_integer(unsigned(RX2)));
MDR_out <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=STIX) then
MAR <= std_logic_vector(unsigned(
register_file(to_integer(unsigned(RX2))))
+ unsigned(M2));
MDR_out <=
register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=JMP or
(Opcode2=JNZ and Z='0') or (Opcode2=JZ and Z='1') or
(Opcode2=JNS and S='0') or (Opcode2=JS and S='1') or
(Opcode2=JNV and V='0') or (Opcode2=JV and V='1') or
(Opcode2=JNC and C='0') or (Opcode2=JC and C='1') ) then
PC <= x"000" & unsigned(M2);
elsif (Opcode2=CALL or Opcode2=PUSH or Opcode2=SYS) then
SP <= SP + 1;
elsif (Opcode2=RET or Opcode2=RETI or Opcode2=POP) then
MAR <= std_logic_vector(SP);
elsif (Opcode2 = WPAD) then
if (rcount < 1) then
h0 <= H0_INIT;
h1 <= H1_INIT;
h2 <= H2_INIT;
h3 <= H3_INIT;
h4 <= H4_INIT;
h5 <= H5_INIT;
h6 <= H6_INIT;
h7 <= H7_INIT;
wva <= H0_INIT;
wvb <= H1_INIT;
wvc <= H2_INIT;
wvd <= H3_INIT;
wve <= H4_INIT;
wvf <= H5_INIT;
wvg <= H6_INIT;
wvh <= H7_INIT;
elsif (rcount < 16) then
wout <= std_logic_vector(mvect(rcount));
else
wout <= std_Logic_vector(
unsigned(unsigned(rotate_right(unsigned(mvect(14)),19)) xor unsigned(rotate_right(unsigned(mvect(14)),61)) xor unsigned(shift_right(unsigned(mvect(14)),6))) +
unsigned(mvect(9)) +
unsigned(unsigned(rotate_right(unsigned(mvect(1)),1)) xor unsigned(rotate_right(unsigned(mvect(1)),8)) xor unsigned(shift_right(unsigned(mvect(1)),7))) +
unsigned(mvect(0)));
end if;
elsif (Opcode2= MLOAD0) then
mvect(0) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(1) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(2) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(3) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD1) then
mvect(4) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(5) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(6) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(7) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD2) then
mvect(8) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(9) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(10) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(11) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD3) then
mvect(12) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(13) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(14) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(15) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2 = MSTM0) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(unsigned(dm0))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(unsigned(dm0))(31 downto 0);
register_file(to_integer(unsigned(RZ2))) <= std_logic_vector(unsigned(dm1))(63 downto 32);
register_file(to_integer(unsigned(RA2))) <= std_logic_vector(unsigned(dm1))(31 downto 0);
register_file(to_integer(unsigned(RB2))) <= std_logic_vector(unsigned(dm2))(63 downto 32);
register_file(to_integer(unsigned(RC2))) <= std_logic_vector(unsigned(dm2))(31 downto 0);
register_file(to_integer(unsigned(RD2))) <= std_logic_vector(unsigned(dm3))(63 downto 32);
register_file(to_integer(unsigned(RE2))) <= std_logic_vector(unsigned(dm3))(31 downto 0);
elsif (Opcode2 = MSTM1) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(unsigned(dm4))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(unsigned(dm4))(31 downto 0);
register_file(to_integer(unsigned(RZ2))) <= std_logic_vector(unsigned(dm5))(63 downto 32);
register_file(to_integer(unsigned(RA2))) <= std_logic_vector(unsigned(dm5))(31 downto 0);
register_file(to_integer(unsigned(RB2))) <= std_logic_vector(unsigned(dm6))(63 downto 32);
register_file(to_integer(unsigned(RC2))) <= std_logic_vector(unsigned(dm6))(31 downto 0);
register_file(to_integer(unsigned(RD2))) <= std_logic_vector(unsigned(dm7))(63 downto 32);
register_file(to_integer(unsigned(RE2))) <= std_logic_vector(unsigned(dm7))(31 downto 0);
elsif (Opcode2 = FIN) then
dm0 <= std_logic_vector(unsigned(wva) + unsigned(h0));
dm1 <= std_logic_vector(unsigned(wvb) + unsigned(h1));
dm2 <= std_logic_vector(unsigned(wvc) + unsigned(h2));
dm3 <= std_logic_vector(unsigned(wvd) + unsigned(h3));
dm4 <= std_logic_vector(unsigned(wve) + unsigned(h4));
dm5 <= std_logic_vector(unsigned(wvf) + unsigned(h5));
dm6 <= std_logic_vector(unsigned(wvg) + unsigned(h6));
dm7 <= std_logic_vector(unsigned(wvh) + unsigned(h7));
elsif (Opcode2 = LDMD) then
MAR <= x"000" & M2;
end if;
stage2 <= S2;
when S2 =>
if (Opcode2=ADD or Opcode2=SUB or Opcode2=IROR or Opcode2=IAND or
Opcode2=MUL or Opcode2=IOR or Opcode2=IXOR or Opcode2=ADI) then
register_file(to_integer(unsigned(RX2))) <= ALU_out;
Z <= zero; S <= ALU_out(31); V <= overflow; C <= carry; --update CC
elsif (Opcode2=CMP or Opcode2=CMPI) then
Z <= zero; S <= ALU_out(31); V <= overflow; C <= carry; --update CC only
elsif (Opcode2=LDM or Opcode2=LDR or Opcode2=LDIX) then
MDR_in <= MEM_in;
elsif (Opcode2=STM or Opcode2=STR or Opcode2=STIX) then
null;
elsif (Opcode2=CALL or Opcode2=SYS) then
MAR <= std_logic_vector(SP);
MDR_out <= std_logic_vector(PC);
elsif (Opcode2=RET or Opcode2=RETI or Opcode2=POP) then
MDR_in <= MEM_IN; SP <= SP - 1;
elsif (Opcode2=PUSH) then
MAR <= std_logic_vector(SP);
MDR_out <= register_file(to_integer(unsigned(RX2)));
elsif (Opcode2 = WPAD) then
if (rcount < 16) then
t1_val <= std_logic_vector(
(unsigned(wvh) +
(unsigned(rotate_right(unsigned(wve), 14)) xor unsigned(rotate_right(unsigned(wve), 18)) xor unsigned(rotate_right(unsigned(wve), 41))) +
((unsigned(wve) and unsigned(wvf)) xor (not(unsigned(wve)) and unsigned(wvg))) +
(unsigned(K_TABLE(rcount)) + unsigned(wout))
));
t2_val <= std_logic_vector(
(unsigned(rotate_right(unsigned(wva), 28)) xor unsigned(rotate_right(unsigned(wva), 34)) xor unsigned(rotate_right(unsigned(wva), 39))) +
(((unsigned(wva)) and (unsigned(wvb))) xor ((unsigned(wva)) and (unsigned(wvc))) xor ((unsigned(wvb)) and (unsigned(wvc))))
);
else
t1_val <= std_logic_vector(
(unsigned(wvh) +
(unsigned(rotate_right(unsigned(wve), 14)) xor unsigned(rotate_right(unsigned(wve), 18)) xor unsigned(rotate_right(unsigned(wve), 41))) +
((unsigned(wve) and unsigned(wvf)) xor (not(unsigned(wve)) and unsigned(wvg))) +
(unsigned(K_TABLE(rcount)) + unsigned(wout))
));
t2_val <= std_logic_vector(
(unsigned(rotate_right(unsigned(wva), 28)) xor unsigned(rotate_right(unsigned(wva), 34)) xor unsigned(rotate_right(unsigned(wva), 39))) +
(((unsigned(wva)) and (unsigned(wvb))) xor ((unsigned(wva)) and (unsigned(wvc))) xor ((unsigned(wvb)) and (unsigned(wvc))))
);
end if;
elsif (Opcode2 = LDMD) then
mvect(0) <= MEM_in;
end if;
stage2 <= S1;
when others =>
null;
end case;
case stage3 is
when S1 =>
if (Opcode3=LDM or Opcode3=LDR or Opcode3=LDIX) then
register_file(to_integer(unsigned(RX3))) <= MDR_in;
elsif (Opcode3=STM or Opcode3=STR or Opcode3=STIX) then
null;
elsif (Opcode3=CALL) then
PC <= x"000" & unsigned(M3);
elsif (Opcode3=POP) then
register_file(to_integer(unsigned(RX3))) <= MDR_in;
elsif (Opcode3=RET) then
PC <= unsigned(MDR_in);
elsif (Opcode3=RETI) then
PSW <= MDR_in; MAR <= std_logic_vector(SP);
elsif (Opcode3=PUSH) then
null;
elsif (Opcode3=SYS) then
SP <= SP + 1;
elsif(Opcode3 = WPAD) then
if (rcount < 16) then
wvh <= wvg;
wvg <= wvf;
wvf <= wve;
wve <= std_logic_vector(unsigned(wvd) + unsigned(t1_val));
wvd <= wvc;
wvc <= wvb;
wvb <= wva;
wva <= std_logic_vector(unsigned(t1_val) + unsigned(t2_val));
rcount <= rcount + 1;
else
wvh <= wvg;
wvg <= wvf;
wvf <= wve;
wve <= std_logic_vector(unsigned(wvd) + unsigned(t1_val));
wvd <= wvc;
wvc <= wvb;
wvb <= wva;
wva <= std_logic_vector(unsigned(t1_val) + unsigned(t2_val));
mvect(0) <= mvect(1);
mvect(1) <= mvect(2);
mvect(2) <= mvect(3);
mvect(3) <= mvect(4);
mvect(4) <= mvect(5);
mvect(5) <= mvect(6);
mvect(6) <= mvect(7);
mvect(7) <= (mvect(8));
mvect(8) <= (mvect(9));
mvect(9) <= (mvect(10));
mvect(10) <= (mvect(11));
mvect(11) <= (mvect(12));
mvect(12) <= (mvect(13));
mvect(13) <= (mvect(14));
mvect(14) <= (mvect(15));
mvect(15) <= wout;
rcount <= rcount + 1;
end if;
elsif (Opcode3 = LDMD) then
MAR <= x"000" & std_logic_vector(unsigned(M2) + 1);
end if;
stage3 <= S2;
when S2 =>
if (Opcode3=RETI) then
MDR_in <= MEM_IN; sp <= sp - 1;
elsif (Opcode3=SYS) then
MAR <= std_logic_vector(SP);
MDR_out <= PSW;
elsif (Opcode3 = LDMD) then
mvect(1) <= MEM_in;
end if;
stage3 <= S1;
when others =>
null;
end case;
case stage4 is
when S1 =>
if (Opcode4=RETI) then
PC <= unsigned(MDR_in);
elsif (Opcode4=SYS) then
PC <= X"000FFC0"&unsigned(IR4(3 downto 0));
elsif (Opcode4 = LDMD) then
MAR <= x"000" & std_logic_vector(unsigned(M2) + 2);
end if;
stage4 <= S2;
when S2 =>
if (Opcode4 = LDMD) then
mvect(2) <= MEM_in;
end if;
stage4 <= S1;
when others =>
null;
end case;
case stage5 is
when S1 =>
if(Opcode5 = LDMD) then
MAR <= x"000" & std_logic_vector(unsigned(M2) + 3);
end if;
stage5 <= S2;
when S2 =>
if (Opcode5 = LDMD) then
mvect(3) <= MEM_in;
end if;
stage5 <= S1;
when others =>
null;
end case;
case stage6 is
when S1 =>
if(Opcode6 = LDMD) then
MAR <= x"000" & std_logic_vector(unsigned(M2) + 4);
end if;
stage6 <= S2;
when S2 =>
if (Opcode6 = LDMD) then
mvect(4) <= MEM_in;
end if;
stage6 <= S1;
when others =>
null;
end case;
case stage7 is
when S1 =>
if(Opcode7 = LDMD) then
MAR <= x"000" & std_logic_vector(unsigned(M2) + 5);
end if;
stage7 <= S2;
when S2 =>
if (Opcode7 = LDMD) then
mvect(5) <= MEM_in;
end if;
stage7 <= S1;
when others =>
null;
end case;
case stage8 is
when S1 =>
if(Opcode8 = LDMD) then
MAR <= x"000" & std_logic_vector(unsigned(M2) + 6);
end if;
stage8 <= S2;
when S2 =>
if (Opcode8 = LDMD) then
mvect(6) <= MEM_in;
end if;
stage8 <= S1;
when others =>
null;
end case;
case stage9 is
when S1 =>
if(Opcode9 = LDMD) then
MAR <= x"000" & std_logic_vector(unsigned(M2) + 7);
end if;
stage9 <= S2;
when S2 =>
if (Opcode9 = LDMD) then
mvect(7) <= MEM_in;
end if;
stage9 <= S1;
when others =>
null;
end case;
case stage10 is
when S1 =>
if(Opcode10 = LDMD) then
MAR <= x"000" & std_logic_vector(unsigned(M2) + 8);
end if;
stage10 <= S2;
when S2 =>
if (Opcode10 = LDMD) then
mvect(8) <= MEM_in;
end if;
stage10 <= S1;
when others =>
null;
end case;
case stage11 is
when S1 =>
if(Opcode11 = LDMD) then
MAR <= x"000" & std_logic_vector(unsigned(M2) + 9);
end if;
stage11 <= S2;
when S2 =>
if (Opcode11 = LDMD) then
mvect(9) <= MEM_in;
end if;
stage11 <= S1;
when others =>
null;
end case;
case stage12 is
when S1 =>
if(Opcode12 = LDMD) then
MAR <= x"000" & std_logic_vector(unsigned(M2) + 10);
end if;
stage12 <= S2;
when S2 =>
if (Opcode12 = LDMD) then
mvect(10) <= MEM_in;
end if;
stage12 <= S1;
when others =>
null;
end case;
case stage13 is
when S1 =>
if(Opcode13 = LDMD) then
MAR <= x"000" & std_logic_vector(unsigned(M2) + 11);
end if;
stage13 <= S2;
when S2 =>
if (Opcode13 = LDMD) then
mvect(11) <= MEM_in;
end if;
stage13 <= S1;
when others =>
null;
end case;
case stage14 is
when S1 =>
if(Opcode14 = LDMD) then
MAR <= x"000" & std_logic_vector(unsigned(M2) + 12);
end if;
stage14 <= S2;
when S2 =>
if (Opcode14 = LDMD) then
mvect(12) <= MEM_in;
end if;
stage14 <= S1;
when others =>
null;
end case;
case stage15 is
when S1 =>
if(Opcode15 = LDMD) then
MAR <= x"000" & std_logic_vector(unsigned(M2) + 13);
end if;
stage15 <= S2;
when S2 =>
if (Opcode15 = LDMD) then
mvect(13) <= MEM_in;
end if;
stage15 <= S1;
when others =>
null;
end case;
case stage16 is
when S1 =>
if(Opcode16 = LDMD) then
MAR <= x"000" & std_logic_vector(unsigned(M2) + 14);
end if;
stage16 <= S2;
when S2 =>
if (Opcode16 = LDMD) then
mvect(14) <= MEM_in;
end if;
stage16 <= S1;
when others =>
null;
end case;
case stage17 is
when S1 =>
if(Opcode17 = LDMD) then
MAR <= x"000" & std_logic_vector(unsigned(M2) + 15);
end if;
stage17 <= S2;
when S2 =>
if (Opcode17 = LDMD) then
mvect(15) <= MEM_in;
end if;
stage17 <= S1;
when others =>
null;
end case;
end if;
end process;
--------------------ALU----------------------------
Rhody_ALU: entity work.alu port map(
alu_op => IR2(28 downto 26),
operand0 => operand0,
operand1 => operand1,
n => IR2(4 downto 0),
alu_out => ALU_out,
carry => carry,
overflow => overflow);
zero <= '1' when alu_out = X"00000000" else '0';
operand0 <= register_file(to_integer(unsigned(RX2)));
-----------------------------------------------------
end Structural;
| gpl-3.0 | 1a0d5d130b4d6e70cb23c893b219d189 | 0.618067 | 2.790024 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/fifo.vhd | 14 | 3,063 | --
-- General-purpose FIFO for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity fifo is
generic (
bits: integer := 11
);
port (
clk: in std_logic;
rst: in std_logic;
wr: in std_logic;
rd: in std_logic;
write: in std_logic_vector(7 downto 0);
read : out std_logic_vector(7 downto 0);
full: out std_logic;
empty: out std_logic
);
end entity fifo;
architecture behave of fifo is
type mem_t is array (0 to ((2**bits)-1)) of std_logic_vector(7 downto 0);
signal memory: mem_t;
signal wraddr: unsigned(bits-1 downto 0);
signal rdaddr: unsigned(bits-1 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
read <= memory( conv_integer(std_logic_vector(rdaddr)) );
end if;
end process;
process(clk,rdaddr,wraddr,rst)
variable full_v: std_logic;
variable empty_v: std_logic;
begin
if rdaddr=wraddr then
empty_v:='1';
else
empty_v:='0';
end if;
if wraddr=rdaddr-1 then
full_v:='1';
else
full_v:='0';
end if;
if rising_edge(clk) then
if rst='1' then
wraddr <= (others => '0');
rdaddr <= (others => '0');
else
if wr='1' and full_v='0' then
memory(conv_integer(std_logic_vector(wraddr) ) ) <= write;
wraddr <= wraddr+1;
end if;
if rd='1' and empty_v='0' then
rdaddr <= rdaddr+1;
end if;
end if;
full <= full_v;
empty <= empty_v;
end if;
end process;
end behave;
| mit | caf2ef529bdf7a40451c05bb146cdb8c | 0.642507 | 3.668263 | false | false | false | false |
chcbaram/FPGA | ZPUino_miniSpartan6_plus/ipcore_dir/Clock/simulation/Clock_tb.vhd | 1 | 6,298 | -- file: Clock_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity Clock_tb is
end Clock_tb;
architecture test of Clock_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 20.0 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bits of the sampling counters
signal COUNT : std_logic_vector(4 downto 1);
-- Status and control signals
signal LOCKED : std_logic;
signal COUNTER_RESET : std_logic := '0';
-- signal defined to stop mti simulation without severity failure in the report
signal end_of_sim : std_logic := '0';
signal CLK_OUT : std_logic_vector(4 downto 1);
--Freq Check using the M & D values setting and actual Frequency generated
component Clock_exdes
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(4 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic_vector(4 downto 1);
-- Status and control signals
LOCKED : out std_logic
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
procedure simfreqprint (period : time; clk_num : integer) is
variable outputline : LINE;
variable str1 : string(1 to 16);
variable str2 : integer;
variable str3 : string(1 to 2);
variable str4 : integer;
variable str5 : string(1 to 4);
begin
str1 := "Freq of CLK_OUT(";
str2 := clk_num;
str3 := ") ";
str4 := 1000000 ps/period ;
str5 := " MHz" ;
write(outputline, str1 );
write(outputline, str2);
write(outputline, str3);
write(outputline, str4);
write(outputline, str5);
writeline(output, outputline);
end simfreqprint;
begin
wait until LOCKED = '1';
COUNTER_RESET <= '1';
wait for (PER1*20);
COUNTER_RESET <= '0';
wait for (PER1*COUNT_PHASE);
simtimeprint;
end_of_sim <= '1';
wait for 1 ps;
report "Simulation Stopped." severity failure;
wait;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : Clock_exdes
generic map (
TCQ => TCQ)
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
CLK_OUT => CLK_OUT,
-- High bits of the counters
COUNT => COUNT,
-- Status and control signals
LOCKED => LOCKED);
-- Freq Check
end test;
| mit | 6d90ffcb891e2d6fea8fb68a26fe8283 | 0.636075 | 4.319616 | false | false | false | false |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/bg_pole/bg_pole_sim_netlist.vhdl | 1 | 42,153 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:33:47 2017
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/bg_pole/bg_pole_sim_netlist.vhdl
-- Design : bg_pole
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_pole_blk_mem_gen_prim_wrapper_init is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 6 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_pole_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end bg_pole_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of bg_pole_blk_mem_gen_prim_wrapper_init is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_1\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_10\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_11\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_12\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_16\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_17\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_18\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_19\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_2\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_20\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_24\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_25\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_26\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_27\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_28\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_3\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_4\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_8\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_9\ : STD_LOGIC;
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000006050607040603010000000000000000030506070706010000000000",
INIT_01 => X"0000020007060100040603010000000000000000060506070706010000000000",
INIT_02 => X"0000000004060301070601000004000000000000060506070406030100000000",
INIT_03 => X"0000000006050607040603010000000000000000030506070706010000000000",
INIT_04 => X"0000000006050607070601000000000000000000050606060406030100040000",
INIT_05 => X"0000000004060301070601000004000000000000060506070406030100000000",
INIT_06 => X"0000000003050607070601000000000000000000060506070406030100040000",
INIT_07 => X"0000000006050607070601000000000000000000050606060406030100040000",
INIT_08 => X"0000000006050607040603010000000000000200070601000406030100000000",
INIT_09 => X"0000000003050607070601000000000000000000060506070406030100040000",
INIT_0A => X"0000000005060606040603010004000000000000060506070406030100000000",
INIT_0B => X"0000000006050607040603010000000000000200070601000406030100000000",
INIT_0C => X"0000000006050607040603010004000000000000040603010706010000040000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 18,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 18
)
port map (
ADDRARDADDR(13 downto 12) => B"00",
ADDRARDADDR(11 downto 5) => addra(6 downto 0),
ADDRARDADDR(4 downto 0) => B"00000",
ADDRBWRADDR(13 downto 12) => B"00",
ADDRBWRADDR(11 downto 5) => addra(6 downto 0),
ADDRBWRADDR(4 downto 0) => B"10000",
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15 downto 11) => B"00000",
DIADI(10 downto 8) => dina(5 downto 3),
DIADI(7 downto 3) => B"00000",
DIADI(2 downto 0) => dina(2 downto 0),
DIBDI(15 downto 11) => B"00000",
DIBDI(10 downto 8) => dina(11 downto 9),
DIBDI(7 downto 3) => B"00000",
DIBDI(2 downto 0) => dina(8 downto 6),
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_0\,
DOADO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_1\,
DOADO(13) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_2\,
DOADO(12) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_3\,
DOADO(11) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_4\,
DOADO(10 downto 8) => douta(5 downto 3),
DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_8\,
DOADO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_9\,
DOADO(5) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_10\,
DOADO(4) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_11\,
DOADO(3) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_12\,
DOADO(2 downto 0) => douta(2 downto 0),
DOBDO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_16\,
DOBDO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_17\,
DOBDO(13) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_18\,
DOBDO(12) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_19\,
DOBDO(11) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_20\,
DOBDO(10 downto 8) => douta(11 downto 9),
DOBDO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_24\,
DOBDO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_25\,
DOBDO(5) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_26\,
DOBDO(4) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_27\,
DOBDO(3) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_28\,
DOBDO(2 downto 0) => douta(8 downto 6),
DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32\,
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33\,
DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34\,
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35\,
ENARDEN => '1',
ENBWREN => '1',
REGCEAREGCE => '1',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 2) => B"00",
WEBWE(1) => wea(0),
WEBWE(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_pole_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 6 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_pole_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end bg_pole_blk_mem_gen_prim_width;
architecture STRUCTURE of bg_pole_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.bg_pole_blk_mem_gen_prim_wrapper_init
port map (
addra(6 downto 0) => addra(6 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_pole_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 6 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_pole_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end bg_pole_blk_mem_gen_generic_cstr;
architecture STRUCTURE of bg_pole_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.bg_pole_blk_mem_gen_prim_width
port map (
addra(6 downto 0) => addra(6 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_pole_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 6 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_pole_blk_mem_gen_top : entity is "blk_mem_gen_top";
end bg_pole_blk_mem_gen_top;
architecture STRUCTURE of bg_pole_blk_mem_gen_top is
begin
\valid.cstr\: entity work.bg_pole_blk_mem_gen_generic_cstr
port map (
addra(6 downto 0) => addra(6 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_pole_blk_mem_gen_v8_3_5_synth is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 6 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_pole_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth";
end bg_pole_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of bg_pole_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.bg_pole_blk_mem_gen_top
port map (
addra(6 downto 0) => addra(6 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_pole_blk_mem_gen_v8_3_5 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 6 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 6 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 11 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 11 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 6 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of bg_pole_blk_mem_gen_v8_3_5 : entity is 7;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of bg_pole_blk_mem_gen_v8_3_5 : entity is 7;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of bg_pole_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of bg_pole_blk_mem_gen_v8_3_5 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of bg_pole_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of bg_pole_blk_mem_gen_v8_3_5 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of bg_pole_blk_mem_gen_v8_3_5 : entity is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of bg_pole_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of bg_pole_blk_mem_gen_v8_3_5 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of bg_pole_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of bg_pole_blk_mem_gen_v8_3_5 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of bg_pole_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 2.7064499999999998 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of bg_pole_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of bg_pole_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of bg_pole_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of bg_pole_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of bg_pole_blk_mem_gen_v8_3_5 : entity is "bg_pole.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of bg_pole_blk_mem_gen_v8_3_5 : entity is "bg_pole.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of bg_pole_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of bg_pole_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of bg_pole_blk_mem_gen_v8_3_5 : entity is 104;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of bg_pole_blk_mem_gen_v8_3_5 : entity is 104;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of bg_pole_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of bg_pole_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of bg_pole_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of bg_pole_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of bg_pole_blk_mem_gen_v8_3_5 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of bg_pole_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of bg_pole_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of bg_pole_blk_mem_gen_v8_3_5 : entity is 104;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of bg_pole_blk_mem_gen_v8_3_5 : entity is 104;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of bg_pole_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of bg_pole_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of bg_pole_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of bg_pole_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of bg_pole_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_pole_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of bg_pole_blk_mem_gen_v8_3_5 : entity is "yes";
end bg_pole_blk_mem_gen_v8_3_5;
architecture STRUCTURE of bg_pole_blk_mem_gen_v8_3_5 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(11) <= \<const0>\;
doutb(10) <= \<const0>\;
doutb(9) <= \<const0>\;
doutb(8) <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.bg_pole_blk_mem_gen_v8_3_5_synth
port map (
addra(6 downto 0) => addra(6 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_pole is
port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 6 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of bg_pole : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of bg_pole : entity is "bg_pole,blk_mem_gen_v8_3_5,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of bg_pole : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of bg_pole : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4";
end bg_pole;
architecture STRUCTURE of bg_pole is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 6 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 6 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 7;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 7;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "0";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 2.7064499999999998 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "bg_pole.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "bg_pole.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 104;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 104;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 104;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 104;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.bg_pole_blk_mem_gen_v8_3_5
port map (
addra(6 downto 0) => addra(6 downto 0),
addrb(6 downto 0) => B"0000000",
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(11 downto 0) => dina(11 downto 0),
dinb(11 downto 0) => B"000000000000",
douta(11 downto 0) => douta(11 downto 0),
doutb(11 downto 0) => NLW_U0_doutb_UNCONNECTED(11 downto 0),
eccpipece => '0',
ena => '0',
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(6 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(6 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(6 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(6 downto 0),
s_axi_rdata(11 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(11 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(11 downto 0) => B"000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
| gpl-3.0 | e629015e6b3fea4ad275d1e7adb1a03d | 0.681209 | 3.174172 | false | false | false | false |
sinkswim/DLX-Pro | DLX_simulation_cfg/a.b-DataPath.core/a.b.a-fetch.core/a.b.a.e-PC.vhd | 1 | 2,050 | ------------------------------------------------------------------------------
-- PC
-- This unit is the PC register. It is sensitive to the rising edge of the
-- clokc signal. The reset signal is synchronous with respect to the clock
-- The signal PCWrite tells whether the register should load or not the
-- value at the input port or retain the past value. This signal is
-- synchronuos to the clock.
-- PCWrite comes from the Hazard Detection Unit in Decode stage.
-- The output of the register feeds the IRAM_block.
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.globals.all;
----------------------------------------------------------------------------
----------------------------------------------------------------------------
entity pc is
port (
-- INPUTS
from_mux_jump : in std_logic_vector(31 downto 0); -- address coming from the MUX_jump
pcwrite : in std_logic; -- control signal coming from Hazard Detection Unit
clk : in std_logic; -- Global clock signal
rst : in std_logic; -- Global reset signal
-- OUTPUTS
to_iram_block : out std_logic_vector(31 downto 0) -- Address to the IRAM_block
);
end pc;
----------------------------------------------------------------------------
----------------------------------------------------------------------------
architecture behavioral of pc is
begin
-------------------------------------
-- Name: PC_Reg
-- Type: Sequential
-- Purpose: Describe the behavior of
-- the PC register
-------------------------------------
PC_Reg:process(clk)
begin
if(clk = '1' and clk'event) then
if (rst = '1') then
to_iram_block <= (others => '0');
elsif (pcwrite = '1') then
to_iram_block <= from_mux_jump;
end if;
end if;
end process;
end behavioral;
| mit | bbdd0d8e090983e0a656d3062fd5de02 | 0.437073 | 5.099502 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/ZPUino_Papilio_One_V1_hyperion.vhd | 13 | 42,740 | --
-- ZPUINO implementation on Gadget Factory 'Papilio One' Board
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
library unisim;
use unisim.vcomponents.all;
entity ZPUino_Papilio_One_V1_hyperion is
port (
--32Mhz input clock is converted to a 96Mhz clock
CLK: in std_logic;
--RST: in std_logic; -- No reset on papilio
--Clock outputs to be used in schematic
clk_96Mhz: out std_logic; --This is the clock that the system runs on.
clk_1Mhz: out std_logic; --This is a 1Mhz clock for symbols like the C64 SID chip.
clk_osc_32Mhz: out std_logic; --This is the 32Mhz clock from external oscillator.
-- Connection to the main SPI flash
SPI_FLASH_SCK: out std_logic;
SPI_FLASH_MISO: in std_logic;
SPI_FLASH_MOSI: out std_logic;
SPI_FLASH_CS: inout std_logic;
gpio_bus_in : in std_logic_vector(97 downto 0);
gpio_bus_out : out std_logic_vector(147 downto 0);
-- UART (FTDI) connection
TXD: out std_logic;
RXD: in std_logic;
--There are more bits in the address for this wishbone connection
wishbone_slot_video_in : in std_logic_vector(63 downto 0);
wishbone_slot_video_out : out std_logic_vector(33 downto 0);
vgaclkout: out std_logic;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type wishbone_bus_in_type is record
-- wb_clk_i: std_logic; -- Wishbone clock
-- wb_rst_i: std_logic; -- Wishbone reset (synchronous)
-- wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
-- wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
-- wb_we_i: std_logic; -- Wishbone write enable signal
-- wb_cyc_i: std_logic; -- Wishbone cycle signal
-- wb_stb_i: std_logic; -- Wishbone strobe signal
-- end record;
--
-- type wishbone_bus_out_type is record
-- wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
-- wb_ack_o: std_logic; -- Wishbone acknowledge out signal
-- wb_inta_o: std_logic;
-- end record;
--
-- Turning them into an array looks like this:
--
-- wishbone_in : in std_logic_vector(61 downto 0);
--
-- wishbone_in_record.wb_clk_i <= wishbone_in(61);
-- wishbone_in_record.wb_rst_i <= wishbone_in(60);
-- wishbone_in_record.wb_dat_i <= wishbone_in(59 downto 28);
-- wishbone_in_record.wb_adr_i <= wishbone_in(27 downto 3);
-- wishbone_in_record.wb_we_i <= wishbone_in(2);
-- wishbone_in_record.wb_cyc_i <= wishbone_in(1);
-- wishbone_in_record.wb_stb_i <= wishbone_in(0);
--
-- wishbone_out : out std_logic_vector(33 downto 0);
--
-- wishbone_out(33 downto 2) <= wishbone_out_record.wb_dat_o;
-- wishbone_out(1) <= wishbone_out_record.wb_ack_o;
-- wishbone_out(0) <= wishbone_out_record.wb_inta_o;
--Input and output reversed for the master
wishbone_slot_5_in : out std_logic_vector(61 downto 0);
wishbone_slot_5_out : in std_logic_vector(33 downto 0);
wishbone_slot_6_in : out std_logic_vector(61 downto 0);
wishbone_slot_6_out : in std_logic_vector(33 downto 0);
wishbone_slot_8_in : out std_logic_vector(61 downto 0);
wishbone_slot_8_out : in std_logic_vector(33 downto 0);
wishbone_slot_9_in : out std_logic_vector(61 downto 0);
wishbone_slot_9_out : in std_logic_vector(33 downto 0);
wishbone_slot_10_in : out std_logic_vector(61 downto 0);
wishbone_slot_10_out : in std_logic_vector(33 downto 0);
wishbone_slot_11_in : out std_logic_vector(61 downto 0);
wishbone_slot_11_out : in std_logic_vector(33 downto 0);
wishbone_slot_12_in : out std_logic_vector(61 downto 0);
wishbone_slot_12_out : in std_logic_vector(33 downto 0);
wishbone_slot_13_in : out std_logic_vector(61 downto 0);
wishbone_slot_13_out : in std_logic_vector(33 downto 0);
wishbone_slot_14_in : out std_logic_vector(61 downto 0);
wishbone_slot_14_out : in std_logic_vector(33 downto 0);
wishbone_slot_15_in : out std_logic_vector(61 downto 0);
wishbone_slot_15_out : in std_logic_vector(33 downto 0)
);
-- attribute LOC: string;
-- attribute LOC of CLK: signal is "P89";
-- attribute LOC of RXD: signal is "P88";
-- attribute LOC of TXD: signal is "P90";
-- attribute LOC of SPI_FLASH_CS: signal is "P24";
-- attribute LOC of SPI_FLASH_SCK: signal is "P50";
-- attribute LOC of SPI_FLASH_MISO: signal is "P44";
-- attribute LOC of SPI_FLASH_MOSI: signal is "P27";
--
-- attribute IOSTANDARD: string;
-- attribute IOSTANDARD of CLK: signal is "LVCMOS33";
-- attribute IOSTANDARD of RXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of TXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_CS: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_SCK: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MISO: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MOSI: signal is "LVCMOS33";
--
-- attribute PERIOD: string;
-- attribute PERIOD of CLK: signal is "31.00ns";
end entity ZPUino_Papilio_One_V1_hyperion;
architecture behave of ZPUino_Papilio_One_V1_hyperion is
component clkgen_hyperion is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end component clkgen_hyperion;
component zpuino_serialreset is
generic (
SYSTEM_CLOCK_MHZ: integer := 96
);
port (
clk: in std_logic;
rx: in std_logic;
rstin: in std_logic;
rstout: out std_logic
);
end component zpuino_serialreset;
signal sysrst: std_logic;
signal sysclk: std_logic;
signal sysclk_1mhz: std_logic;
signal dbg_reset: std_logic;
signal clkgen_rst: std_logic;
signal gpio_o_reg: std_logic_vector(zpuino_gpio_count-1 downto 0);
signal rx: std_logic;
signal tx: std_logic;
constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- I/O Signals
signal slot_cyc: slot_std_logic_type;
signal slot_we: slot_std_logic_type;
signal slot_stb: slot_std_logic_type;
signal slot_read: slot_cpuword_type;
signal slot_write: slot_cpuword_type;
signal slot_address: slot_address_type;
signal slot_ack: slot_std_logic_type;
signal slot_interrupt: slot_std_logic_type;
signal spi_enabled: std_logic;
signal uart_enabled: std_logic;
signal timers_interrupt: std_logic_vector(1 downto 0);
signal timers_pwm: std_logic_vector(1 downto 0);
signal ivecs, sigmadelta_raw: std_logic_vector(17 downto 0);
signal sigmadelta_spp_en: std_logic_vector(1 downto 0);
signal sigmadelta_spp_data: std_logic_vector(1 downto 0);
-- For busy-implementation
signal addr_save_q: std_logic_vector(maxAddrBitIncIO downto 0);
signal write_save_q: std_logic_vector(wordSize-1 downto 0);
signal spi_pf_miso: std_logic;
signal spi_pf_mosi: std_logic;
signal spi_pf_sck: std_logic;
signal adc_mosi: std_logic;
signal adc_miso: std_logic;
signal adc_sck: std_logic;
signal adc_seln: std_logic;
signal adc_enabled: std_logic;
signal wb_clk_i: std_logic;
signal wb_rst_i: std_logic;
signal uart2_tx, uart2_rx: std_logic;
signal jtag_data_chain_out: std_logic_vector(98 downto 0);
signal jtag_ctrl_chain_in: std_logic_vector(11 downto 0);
signal wishbone_slot_video_in_record : wishbone_bus_in_type;
signal wishbone_slot_video_out_record : wishbone_bus_out_type;
signal wishbone_slot_5_in_record : wishbone_bus_in_type;
signal wishbone_slot_5_out_record : wishbone_bus_out_type;
signal wishbone_slot_6_in_record : wishbone_bus_in_type;
signal wishbone_slot_6_out_record : wishbone_bus_out_type;
signal wishbone_slot_8_in_record : wishbone_bus_in_type;
signal wishbone_slot_8_out_record : wishbone_bus_out_type;
signal wishbone_slot_9_in_record : wishbone_bus_in_type;
signal wishbone_slot_9_out_record : wishbone_bus_out_type;
signal wishbone_slot_10_in_record : wishbone_bus_in_type;
signal wishbone_slot_10_out_record : wishbone_bus_out_type;
signal wishbone_slot_11_in_record : wishbone_bus_in_type;
signal wishbone_slot_11_out_record : wishbone_bus_out_type;
signal wishbone_slot_12_in_record : wishbone_bus_in_type;
signal wishbone_slot_12_out_record : wishbone_bus_out_type;
signal wishbone_slot_13_in_record : wishbone_bus_in_type;
signal wishbone_slot_13_out_record : wishbone_bus_out_type;
signal wishbone_slot_14_in_record : wishbone_bus_in_type;
signal wishbone_slot_14_out_record : wishbone_bus_out_type;
signal wishbone_slot_15_in_record : wishbone_bus_in_type;
signal wishbone_slot_15_out_record : wishbone_bus_out_type;
signal gpio_bus_in_record : gpio_bus_in_type;
signal gpio_bus_out_record : gpio_bus_out_type;
component zpuino_debug_spartan3e is
port (
TCK: out std_logic;
TDI: out std_logic;
CAPTUREIR: out std_logic;
UPDATEIR: out std_logic;
SHIFTIR: out std_logic;
CAPTUREDR: out std_logic;
UPDATEDR: out std_logic;
SHIFTDR: out std_logic;
TLR: out std_logic;
TDO_IR: in std_logic;
TDO_DR: in std_logic
);
end component;
begin
-- Unpack the wishbone array into a record so the modules code is not confusing.
-- These are backwards for the master.
-- wishbone_slot_video_in_record.wb_clk_i <= wishbone_slot_video_in(61);
-- wishbone_slot_video_in_record.wb_rst_i <= wishbone_slot_video_in(60);
-- wishbone_slot_video_in_record.wb_dat_i <= wishbone_slot_video_in(59 downto 28);
-- wishbone_slot_video_in_record.wb_adr_i <= wishbone_slot_video_in(27 downto 3);
-- wishbone_slot_video_in_record.wb_we_i <= wishbone_slot_video_in(2);
-- wishbone_slot_video_in_record.wb_cyc_i <= wishbone_slot_video_in(1);
-- wishbone_slot_video_in_record.wb_stb_i <= wishbone_slot_video_in(0);
-- wishbone_slot_video_out(33 downto 2) <= wishbone_slot_video_out_record.wb_dat_o;
-- wishbone_slot_video_out(1) <= wishbone_slot_video_out_record.wb_ack_o;
-- wishbone_slot_video_out(0) <= wishbone_slot_video_out_record.wb_inta_o;
wishbone_slot_5_in(61) <= wishbone_slot_5_in_record.wb_clk_i;
wishbone_slot_5_in(60) <= wishbone_slot_5_in_record.wb_rst_i;
wishbone_slot_5_in(59 downto 28) <= wishbone_slot_5_in_record.wb_dat_i;
wishbone_slot_5_in(27 downto 3) <= wishbone_slot_5_in_record.wb_adr_i;
wishbone_slot_5_in(2) <= wishbone_slot_5_in_record.wb_we_i;
wishbone_slot_5_in(1) <= wishbone_slot_5_in_record.wb_cyc_i;
wishbone_slot_5_in(0) <= wishbone_slot_5_in_record.wb_stb_i;
wishbone_slot_5_out_record.wb_dat_o <= wishbone_slot_5_out(33 downto 2);
wishbone_slot_5_out_record.wb_ack_o <= wishbone_slot_5_out(1);
wishbone_slot_5_out_record.wb_inta_o <= wishbone_slot_5_out(0);
wishbone_slot_6_in(61) <= wishbone_slot_6_in_record.wb_clk_i;
wishbone_slot_6_in(60) <= wishbone_slot_6_in_record.wb_rst_i;
wishbone_slot_6_in(59 downto 28) <= wishbone_slot_6_in_record.wb_dat_i;
wishbone_slot_6_in(27 downto 3) <= wishbone_slot_6_in_record.wb_adr_i;
wishbone_slot_6_in(2) <= wishbone_slot_6_in_record.wb_we_i;
wishbone_slot_6_in(1) <= wishbone_slot_6_in_record.wb_cyc_i;
wishbone_slot_6_in(0) <= wishbone_slot_6_in_record.wb_stb_i;
wishbone_slot_6_out_record.wb_dat_o <= wishbone_slot_6_out(33 downto 2);
wishbone_slot_6_out_record.wb_ack_o <= wishbone_slot_6_out(1);
wishbone_slot_6_out_record.wb_inta_o <= wishbone_slot_6_out(0);
wishbone_slot_8_in(61) <= wishbone_slot_8_in_record.wb_clk_i;
wishbone_slot_8_in(60) <= wishbone_slot_8_in_record.wb_rst_i;
wishbone_slot_8_in(59 downto 28) <= wishbone_slot_8_in_record.wb_dat_i;
wishbone_slot_8_in(27 downto 3) <= wishbone_slot_8_in_record.wb_adr_i;
wishbone_slot_8_in(2) <= wishbone_slot_8_in_record.wb_we_i;
wishbone_slot_8_in(1) <= wishbone_slot_8_in_record.wb_cyc_i;
wishbone_slot_8_in(0) <= wishbone_slot_8_in_record.wb_stb_i;
wishbone_slot_8_out_record.wb_dat_o <= wishbone_slot_8_out(33 downto 2);
wishbone_slot_8_out_record.wb_ack_o <= wishbone_slot_8_out(1);
wishbone_slot_8_out_record.wb_inta_o <= wishbone_slot_8_out(0);
wishbone_slot_9_in(61) <= wishbone_slot_9_in_record.wb_clk_i;
wishbone_slot_9_in(60) <= wishbone_slot_9_in_record.wb_rst_i;
wishbone_slot_9_in(59 downto 28) <= wishbone_slot_9_in_record.wb_dat_i;
wishbone_slot_9_in(27 downto 3) <= wishbone_slot_9_in_record.wb_adr_i;
wishbone_slot_9_in(2) <= wishbone_slot_9_in_record.wb_we_i;
wishbone_slot_9_in(1) <= wishbone_slot_9_in_record.wb_cyc_i;
wishbone_slot_9_in(0) <= wishbone_slot_9_in_record.wb_stb_i;
wishbone_slot_9_out_record.wb_dat_o <= wishbone_slot_9_out(33 downto 2);
wishbone_slot_9_out_record.wb_ack_o <= wishbone_slot_9_out(1);
wishbone_slot_9_out_record.wb_inta_o <= wishbone_slot_9_out(0);
wishbone_slot_10_in(61) <= wishbone_slot_10_in_record.wb_clk_i;
wishbone_slot_10_in(60) <= wishbone_slot_10_in_record.wb_rst_i;
wishbone_slot_10_in(59 downto 28) <= wishbone_slot_10_in_record.wb_dat_i;
wishbone_slot_10_in(27 downto 3) <= wishbone_slot_10_in_record.wb_adr_i;
wishbone_slot_10_in(2) <= wishbone_slot_10_in_record.wb_we_i;
wishbone_slot_10_in(1) <= wishbone_slot_10_in_record.wb_cyc_i;
wishbone_slot_10_in(0) <= wishbone_slot_10_in_record.wb_stb_i;
wishbone_slot_10_out_record.wb_dat_o <= wishbone_slot_10_out(33 downto 2);
wishbone_slot_10_out_record.wb_ack_o <= wishbone_slot_10_out(1);
wishbone_slot_10_out_record.wb_inta_o <= wishbone_slot_10_out(0);
wishbone_slot_11_in(61) <= wishbone_slot_11_in_record.wb_clk_i;
wishbone_slot_11_in(60) <= wishbone_slot_11_in_record.wb_rst_i;
wishbone_slot_11_in(59 downto 28) <= wishbone_slot_11_in_record.wb_dat_i;
wishbone_slot_11_in(27 downto 3) <= wishbone_slot_11_in_record.wb_adr_i;
wishbone_slot_11_in(2) <= wishbone_slot_11_in_record.wb_we_i;
wishbone_slot_11_in(1) <= wishbone_slot_11_in_record.wb_cyc_i;
wishbone_slot_11_in(0) <= wishbone_slot_11_in_record.wb_stb_i;
wishbone_slot_11_out_record.wb_dat_o <= wishbone_slot_11_out(33 downto 2);
wishbone_slot_11_out_record.wb_ack_o <= wishbone_slot_11_out(1);
wishbone_slot_11_out_record.wb_inta_o <= wishbone_slot_11_out(0);
wishbone_slot_12_in(61) <= wishbone_slot_12_in_record.wb_clk_i;
wishbone_slot_12_in(60) <= wishbone_slot_12_in_record.wb_rst_i;
wishbone_slot_12_in(59 downto 28) <= wishbone_slot_12_in_record.wb_dat_i;
wishbone_slot_12_in(27 downto 3) <= wishbone_slot_12_in_record.wb_adr_i;
wishbone_slot_12_in(2) <= wishbone_slot_12_in_record.wb_we_i;
wishbone_slot_12_in(1) <= wishbone_slot_12_in_record.wb_cyc_i;
wishbone_slot_12_in(0) <= wishbone_slot_12_in_record.wb_stb_i;
wishbone_slot_12_out_record.wb_dat_o <= wishbone_slot_12_out(33 downto 2);
wishbone_slot_12_out_record.wb_ack_o <= wishbone_slot_12_out(1);
wishbone_slot_12_out_record.wb_inta_o <= wishbone_slot_12_out(0);
wishbone_slot_13_in(61) <= wishbone_slot_13_in_record.wb_clk_i;
wishbone_slot_13_in(60) <= wishbone_slot_13_in_record.wb_rst_i;
wishbone_slot_13_in(59 downto 28) <= wishbone_slot_13_in_record.wb_dat_i;
wishbone_slot_13_in(27 downto 3) <= wishbone_slot_13_in_record.wb_adr_i;
wishbone_slot_13_in(2) <= wishbone_slot_13_in_record.wb_we_i;
wishbone_slot_13_in(1) <= wishbone_slot_13_in_record.wb_cyc_i;
wishbone_slot_13_in(0) <= wishbone_slot_13_in_record.wb_stb_i;
wishbone_slot_13_out_record.wb_dat_o <= wishbone_slot_13_out(33 downto 2);
wishbone_slot_13_out_record.wb_ack_o <= wishbone_slot_13_out(1);
wishbone_slot_13_out_record.wb_inta_o <= wishbone_slot_13_out(0);
wishbone_slot_14_in(61) <= wishbone_slot_14_in_record.wb_clk_i;
wishbone_slot_14_in(60) <= wishbone_slot_14_in_record.wb_rst_i;
wishbone_slot_14_in(59 downto 28) <= wishbone_slot_14_in_record.wb_dat_i;
wishbone_slot_14_in(27 downto 3) <= wishbone_slot_14_in_record.wb_adr_i;
wishbone_slot_14_in(2) <= wishbone_slot_14_in_record.wb_we_i;
wishbone_slot_14_in(1) <= wishbone_slot_14_in_record.wb_cyc_i;
wishbone_slot_14_in(0) <= wishbone_slot_14_in_record.wb_stb_i;
wishbone_slot_14_out_record.wb_dat_o <= wishbone_slot_14_out(33 downto 2);
wishbone_slot_14_out_record.wb_ack_o <= wishbone_slot_14_out(1);
wishbone_slot_14_out_record.wb_inta_o <= wishbone_slot_14_out(0);
wishbone_slot_15_in(61) <= wishbone_slot_15_in_record.wb_clk_i;
wishbone_slot_15_in(60) <= wishbone_slot_15_in_record.wb_rst_i;
wishbone_slot_15_in(59 downto 28) <= wishbone_slot_15_in_record.wb_dat_i;
wishbone_slot_15_in(27 downto 3) <= wishbone_slot_15_in_record.wb_adr_i;
wishbone_slot_15_in(2) <= wishbone_slot_15_in_record.wb_we_i;
wishbone_slot_15_in(1) <= wishbone_slot_15_in_record.wb_cyc_i;
wishbone_slot_15_in(0) <= wishbone_slot_15_in_record.wb_stb_i;
wishbone_slot_15_out_record.wb_dat_o <= wishbone_slot_15_out(33 downto 2);
wishbone_slot_15_out_record.wb_ack_o <= wishbone_slot_15_out(1);
wishbone_slot_15_out_record.wb_inta_o <= wishbone_slot_15_out(0);
gpio_bus_in_record.gpio_spp_data <= gpio_bus_in(97 downto 49);
gpio_bus_in_record.gpio_i <= gpio_bus_in(48 downto 0);
gpio_bus_out(147) <= gpio_bus_out_record.gpio_clk;
gpio_bus_out(146 downto 98) <= gpio_bus_out_record.gpio_o;
gpio_bus_out(97 downto 49) <= gpio_bus_out_record.gpio_t;
gpio_bus_out(48 downto 0) <= gpio_bus_out_record.gpio_spp_read;
gpio_bus_out_record.gpio_o <= gpio_o_reg;
gpio_bus_out_record.gpio_clk <= sysclk;
wb_clk_i <= sysclk;
wb_rst_i <= sysrst;
--Wishbone 5
wishbone_slot_5_in_record.wb_clk_i <= sysclk;
wishbone_slot_5_in_record.wb_rst_i <= sysrst;
slot_read(5) <= wishbone_slot_5_out_record.wb_dat_o;
wishbone_slot_5_in_record.wb_dat_i <= slot_write(5);
wishbone_slot_5_in_record.wb_adr_i <= slot_address(5);
wishbone_slot_5_in_record.wb_we_i <= slot_we(5);
wishbone_slot_5_in_record.wb_cyc_i <= slot_cyc(5);
wishbone_slot_5_in_record.wb_stb_i <= slot_stb(5);
slot_ack(5) <= wishbone_slot_5_out_record.wb_ack_o;
slot_interrupt(5) <= wishbone_slot_5_out_record.wb_inta_o;
--Wishbone 6
wishbone_slot_6_in_record.wb_clk_i <= sysclk;
wishbone_slot_6_in_record.wb_rst_i <= sysrst;
slot_read(6) <= wishbone_slot_6_out_record.wb_dat_o;
wishbone_slot_6_in_record.wb_dat_i <= slot_write(6);
wishbone_slot_6_in_record.wb_adr_i <= slot_address(6);
wishbone_slot_6_in_record.wb_we_i <= slot_we(6);
wishbone_slot_6_in_record.wb_cyc_i <= slot_cyc(6);
wishbone_slot_6_in_record.wb_stb_i <= slot_stb(6);
slot_ack(6) <= wishbone_slot_6_out_record.wb_ack_o;
slot_interrupt(6) <= wishbone_slot_6_out_record.wb_inta_o;
--Wishbone 8
wishbone_slot_8_in_record.wb_clk_i <= sysclk;
wishbone_slot_8_in_record.wb_rst_i <= sysrst;
slot_read(8) <= wishbone_slot_8_out_record.wb_dat_o;
wishbone_slot_8_in_record.wb_dat_i <= slot_write(8);
wishbone_slot_8_in_record.wb_adr_i <= slot_address(8);
wishbone_slot_8_in_record.wb_we_i <= slot_we(8);
wishbone_slot_8_in_record.wb_cyc_i <= slot_cyc(8);
wishbone_slot_8_in_record.wb_stb_i <= slot_stb(8);
slot_ack(8) <= wishbone_slot_8_out_record.wb_ack_o;
slot_interrupt(8) <= wishbone_slot_8_out_record.wb_inta_o;
--Wishbone 9
wishbone_slot_9_in_record.wb_clk_i <= sysclk;
wishbone_slot_9_in_record.wb_rst_i <= sysrst;
slot_read(9) <= wishbone_slot_9_out_record.wb_dat_o;
wishbone_slot_9_in_record.wb_dat_i <= slot_write(9);
wishbone_slot_9_in_record.wb_adr_i <= slot_address(9);
wishbone_slot_9_in_record.wb_we_i <= slot_we(9);
wishbone_slot_9_in_record.wb_cyc_i <= slot_cyc(9);
wishbone_slot_9_in_record.wb_stb_i <= slot_stb(9);
slot_ack(9) <= wishbone_slot_9_out_record.wb_ack_o;
slot_interrupt(9) <= wishbone_slot_9_out_record.wb_inta_o;
--Wishbone 10
wishbone_slot_10_in_record.wb_clk_i <= sysclk;
wishbone_slot_10_in_record.wb_rst_i <= sysrst;
slot_read(10) <= wishbone_slot_10_out_record.wb_dat_o;
wishbone_slot_10_in_record.wb_dat_i <= slot_write(10);
wishbone_slot_10_in_record.wb_adr_i <= slot_address(10);
wishbone_slot_10_in_record.wb_we_i <= slot_we(10);
wishbone_slot_10_in_record.wb_cyc_i <= slot_cyc(10);
wishbone_slot_10_in_record.wb_stb_i <= slot_stb(10);
slot_ack(10) <= wishbone_slot_10_out_record.wb_ack_o;
slot_interrupt(10) <= wishbone_slot_10_out_record.wb_inta_o;
--Wishbone 11
wishbone_slot_11_in_record.wb_clk_i <= sysclk;
wishbone_slot_11_in_record.wb_rst_i <= sysrst;
slot_read(11) <= wishbone_slot_11_out_record.wb_dat_o;
wishbone_slot_11_in_record.wb_dat_i <= slot_write(11);
wishbone_slot_11_in_record.wb_adr_i <= slot_address(11);
wishbone_slot_11_in_record.wb_we_i <= slot_we(11);
wishbone_slot_11_in_record.wb_cyc_i <= slot_cyc(11);
wishbone_slot_11_in_record.wb_stb_i <= slot_stb(11);
slot_ack(11) <= wishbone_slot_11_out_record.wb_ack_o;
slot_interrupt(11) <= wishbone_slot_11_out_record.wb_inta_o;
--Wishbone 12
wishbone_slot_12_in_record.wb_clk_i <= sysclk;
wishbone_slot_12_in_record.wb_rst_i <= sysrst;
slot_read(12) <= wishbone_slot_12_out_record.wb_dat_o;
wishbone_slot_12_in_record.wb_dat_i <= slot_write(12);
wishbone_slot_12_in_record.wb_adr_i <= slot_address(12);
wishbone_slot_12_in_record.wb_we_i <= slot_we(12);
wishbone_slot_12_in_record.wb_cyc_i <= slot_cyc(12);
wishbone_slot_12_in_record.wb_stb_i <= slot_stb(12);
slot_ack(12) <= wishbone_slot_12_out_record.wb_ack_o;
slot_interrupt(12) <= wishbone_slot_12_out_record.wb_inta_o;
--Wishbone 13
wishbone_slot_13_in_record.wb_clk_i <= sysclk;
wishbone_slot_13_in_record.wb_rst_i <= sysrst;
slot_read(13) <= wishbone_slot_13_out_record.wb_dat_o;
wishbone_slot_13_in_record.wb_dat_i <= slot_write(13);
wishbone_slot_13_in_record.wb_adr_i <= slot_address(13);
wishbone_slot_13_in_record.wb_we_i <= slot_we(13);
wishbone_slot_13_in_record.wb_cyc_i <= slot_cyc(13);
wishbone_slot_13_in_record.wb_stb_i <= slot_stb(13);
slot_ack(13) <= wishbone_slot_13_out_record.wb_ack_o;
slot_interrupt(13) <= wishbone_slot_13_out_record.wb_inta_o;
--Wishbone 14
wishbone_slot_14_in_record.wb_clk_i <= sysclk;
wishbone_slot_14_in_record.wb_rst_i <= sysrst;
slot_read(14) <= wishbone_slot_14_out_record.wb_dat_o;
wishbone_slot_14_in_record.wb_dat_i <= slot_write(14);
wishbone_slot_14_in_record.wb_adr_i <= slot_address(14);
wishbone_slot_14_in_record.wb_we_i <= slot_we(14);
wishbone_slot_14_in_record.wb_cyc_i <= slot_cyc(14);
wishbone_slot_14_in_record.wb_stb_i <= slot_stb(14);
slot_ack(14) <= wishbone_slot_14_out_record.wb_ack_o;
slot_interrupt(14) <= wishbone_slot_14_out_record.wb_inta_o;
--Wishbone 15
wishbone_slot_15_in_record.wb_clk_i <= sysclk;
wishbone_slot_15_in_record.wb_rst_i <= sysrst;
slot_read(15) <= wishbone_slot_15_out_record.wb_dat_o;
wishbone_slot_15_in_record.wb_dat_i <= slot_write(15);
wishbone_slot_15_in_record.wb_adr_i <= slot_address(15);
wishbone_slot_15_in_record.wb_we_i <= slot_we(15);
wishbone_slot_15_in_record.wb_cyc_i <= slot_cyc(15);
wishbone_slot_15_in_record.wb_stb_i <= slot_stb(15);
slot_ack(15) <= wishbone_slot_15_out_record.wb_ack_o;
slot_interrupt(15) <= wishbone_slot_15_out_record.wb_inta_o;
rstgen: zpuino_serialreset
generic map (
SYSTEM_CLOCK_MHZ => 96
)
port map (
clk => sysclk,
rx => rx,
rstin => clkgen_rst,
rstout => sysrst
);
--sysrst <= clkgen_rst;
clkgen_inst: clkgen_hyperion
port map (
clkin => clk,
rstin => dbg_reset,
clkout => sysclk,
vgaclkout => vgaclkout,
clkout_1mhz => clk_1Mhz,
clk_osc_32Mhz => clk_osc_32Mhz,
rstout => clkgen_rst
);
clk_96Mhz <= sysclk;
zpuino:zpuino_top_hyperion
port map (
clk => sysclk,
rst => sysrst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt,
--Be careful the order for this is different then the other wishbone bus connections.
--The address array is bigger so we moved the single signals to the top of the array.
m_wb_dat_o => wishbone_slot_video_out(33 downto 2),
m_wb_dat_i => wishbone_slot_video_in(59 downto 28),
m_wb_adr_i => wishbone_slot_video_in(27 downto 0),
m_wb_we_i => wishbone_slot_video_in(62),
m_wb_cyc_i => wishbone_slot_video_in(61),
m_wb_stb_i => wishbone_slot_video_in(60),
m_wb_ack_o => wishbone_slot_video_out(1),
dbg_reset => dbg_reset,
jtag_data_chain_out => open,--jtag_data_chain_out,
jtag_ctrl_chain_in => (others=>'0')--jtag_ctrl_chain_in
);
--
--
-- ---------------- I/O connection to devices --------------------
--
--
--
-- IO SLOT 0 For SPI FLash
--
slot0: zpuino_spi
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(0),
wb_dat_i => slot_write(0),
wb_adr_i => slot_address(0),
wb_we_i => slot_we(0),
wb_cyc_i => slot_cyc(0),
wb_stb_i => slot_stb(0),
wb_ack_o => slot_ack(0),
wb_inta_o => slot_interrupt(0),
mosi => spi_pf_mosi,
miso => spi_pf_miso,
sck => spi_pf_sck,
enabled => spi_enabled
);
--
-- IO SLOT 1
--
uart_inst: zpuino_uart
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(1),
wb_dat_i => slot_write(1),
wb_adr_i => slot_address(1),
wb_we_i => slot_we(1),
wb_cyc_i => slot_cyc(1),
wb_stb_i => slot_stb(1),
wb_ack_o => slot_ack(1),
wb_inta_o => slot_interrupt(1),
enabled => uart_enabled,
tx => tx,
rx => rx
);
--
-- IO SLOT 2
--
gpio_inst: zpuino_gpio
generic map (
gpio_count => zpuino_gpio_count
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(2),
wb_dat_i => slot_write(2),
wb_adr_i => slot_address(2),
wb_we_i => slot_we(2),
wb_cyc_i => slot_cyc(2),
wb_stb_i => slot_stb(2),
wb_ack_o => slot_ack(2),
wb_inta_o => slot_interrupt(2),
spp_data => gpio_bus_in_record.gpio_spp_data,
spp_read => gpio_bus_out_record.gpio_spp_read,
gpio_i => gpio_bus_in_record.gpio_i,
gpio_t => gpio_bus_out_record.gpio_t,
gpio_o => gpio_o_reg,
spp_cap_in => spp_cap_in,
spp_cap_out => spp_cap_out
);
--
-- IO SLOT 3
--
timers_inst: zpuino_timers
generic map (
A_TSCENABLED => true,
A_PWMCOUNT => 1,
A_WIDTH => 16,
A_PRESCALER_ENABLED => true,
A_BUFFERS => true,
B_TSCENABLED => false,
B_PWMCOUNT => 1,
B_WIDTH => 8,
B_PRESCALER_ENABLED => false,
B_BUFFERS => false
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(3),
wb_dat_i => slot_write(3),
wb_adr_i => slot_address(3),
wb_we_i => slot_we(3),
wb_cyc_i => slot_cyc(3),
wb_stb_i => slot_stb(3),
wb_ack_o => slot_ack(3),
wb_inta_o => slot_interrupt(3), -- We use two interrupt lines
wb_intb_o => slot_interrupt(4), -- so we borrow intr line from slot 4
pwm_a_out => timers_pwm(0 downto 0),
pwm_b_out => timers_pwm(1 downto 1)
);
--
-- IO SLOT 4 - DO NOT USE (it's already mapped to Interrupt Controller)
--
--
-- IO SLOT 5
--
--
-- sigmadelta_inst: zpuino_sigmadelta
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(5),
-- wb_dat_i => slot_write(5),
-- wb_adr_i => slot_address(5),
-- wb_we_i => slot_we(5),
-- wb_cyc_i => slot_cyc(5),
-- wb_stb_i => slot_stb(5),
-- wb_ack_o => slot_ack(5),
-- wb_inta_o => slot_interrupt(5),
--
-- raw_out => sigmadelta_raw,
-- spp_data => sigmadelta_spp_data,
-- spp_en => sigmadelta_spp_en,
-- sync_in => '1'
-- );
--
-- IO SLOT 6
--
-- slot1: zpuino_spi
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(6),
-- wb_dat_i => slot_write(6),
-- wb_adr_i => slot_address(6),
-- wb_we_i => slot_we(6),
-- wb_cyc_i => slot_cyc(6),
-- wb_stb_i => slot_stb(6),
-- wb_ack_o => slot_ack(6),
-- wb_inta_o => slot_interrupt(6),
--
-- mosi => spi2_mosi,
-- miso => spi2_miso,
-- sck => spi2_sck,
-- enabled => open
-- );
--
--
--
--
-- IO SLOT 7
--
crc16_inst: zpuino_crc16
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(7),
wb_dat_i => slot_write(7),
wb_adr_i => slot_address(7),
wb_we_i => slot_we(7),
wb_cyc_i => slot_cyc(7),
wb_stb_i => slot_stb(7),
wb_ack_o => slot_ack(7),
wb_inta_o => slot_interrupt(7)
);
--
-- IO SLOT 8 (optional)
--
-- adc_inst: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(8),
-- wb_dat_i => slot_write(8),
-- wb_adr_i => slot_address(8),
-- wb_we_i => slot_we(8),
-- wb_cyc_i => slot_cyc(8),
-- wb_stb_i => slot_stb(8),
-- wb_ack_o => slot_ack(8),
-- wb_inta_o => slot_interrupt(8)
-- );
--
-- --
-- -- IO SLOT 9
-- --
--
-- slot9: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(9),
-- wb_dat_i => slot_write(9),
-- wb_adr_i => slot_address(9),
-- wb_we_i => slot_we(9),
-- wb_cyc_i => slot_cyc(9),
-- wb_stb_i => slot_stb(9),
-- wb_ack_o => slot_ack(9),
-- wb_inta_o => slot_interrupt(9)
-- );
--
-- --
-- -- IO SLOT 10
-- --
--
-- slot10: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(10),
-- wb_dat_i => slot_write(10),
-- wb_adr_i => slot_address(10),
-- wb_we_i => slot_we(10),
-- wb_cyc_i => slot_cyc(10),
-- wb_stb_i => slot_stb(10),
-- wb_ack_o => slot_ack(10),
-- wb_inta_o => slot_interrupt(10)
-- );
--
-- --
-- -- IO SLOT 11
-- --
--
-- slot11: zpuino_empty_device
---- generic map (
---- bits => 4
---- )
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(11),
-- wb_dat_i => slot_write(11),
-- wb_adr_i => slot_address(11),
-- wb_we_i => slot_we(11),
-- wb_cyc_i => slot_cyc(11),
-- wb_stb_i => slot_stb(11),
-- wb_ack_o => slot_ack(11),
--
-- wb_inta_o => slot_interrupt(11)
--
---- tx => uart2_tx,
---- rx => uart2_rx
-- );
--
-- --
-- -- IO SLOT 12
-- --
--
-- slot12: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(12),
-- wb_dat_i => slot_write(12),
-- wb_adr_i => slot_address(12),
-- wb_we_i => slot_we(12),
-- wb_cyc_i => slot_cyc(12),
-- wb_stb_i => slot_stb(12),
-- wb_ack_o => slot_ack(12),
-- wb_inta_o => slot_interrupt(12)
-- );
--
-- --
-- -- IO SLOT 13
-- --
--
-- slot13: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(13),
-- wb_dat_i => slot_write(13),
-- wb_adr_i => slot_address(13),
-- wb_we_i => slot_we(13),
-- wb_cyc_i => slot_cyc(13),
-- wb_stb_i => slot_stb(13),
-- wb_ack_o => slot_ack(13),
-- wb_inta_o => slot_interrupt(13)
--
---- data_out => ym2149_audio_data
-- );
--
-- --
-- -- IO SLOT 14
-- --
--
-- slot14: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(14),
-- wb_dat_i => slot_write(14),
-- wb_adr_i => slot_address(14),
-- wb_we_i => slot_we(14),
-- wb_cyc_i => slot_cyc(14),
-- wb_stb_i => slot_stb(14),
-- wb_ack_o => slot_ack(14),
-- wb_inta_o => slot_interrupt(14)
--
---- clk_1MHZ => sysclk_1mhz,
---- audio_data => sid_audio_data
--
-- );
--
-- --
-- -- IO SLOT 15
-- --
--
-- slot15: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(15),
-- wb_dat_i => slot_write(15),
-- wb_adr_i => slot_address(15),
-- wb_we_i => slot_we(15),
-- wb_cyc_i => slot_cyc(15),
-- wb_stb_i => slot_stb(15),
-- wb_ack_o => slot_ack(15),
-- wb_inta_o => slot_interrupt(15)
-- );
-- -- Audio for SID
-- sid_sd: simple_sigmadelta
-- generic map (
-- BITS => 18
-- )
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- data_in => sid_audio_data,
-- data_out => sid_audio
-- );
-- Audio output for devices
-- ym2149_audio_dac <= ym2149_audio_data & "0000000000";
--
-- mixer: zpuino_io_audiomixer
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- ena => '1',
--
-- data_in1 => sid_audio_data,
-- data_in2 => ym2149_audio_dac,
-- data_in3 => sigmadelta_raw,
--
-- audio_out => platform_audio_sd
-- );
-- pin00: IOPAD port map(I => gpio_o(0), O => gpio_i(0), T => gpio_t(0), C => sysclk,PAD => WING_A(0) );
-- pin01: IOPAD port map(I => gpio_o(1), O => gpio_i(1), T => gpio_t(1), C => sysclk,PAD => WING_A(1) );
-- pin02: IOPAD port map(I => gpio_o(2), O => gpio_i(2), T => gpio_t(2), C => sysclk,PAD => WING_A(2) );
-- pin03: IOPAD port map(I => gpio_o(3), O => gpio_i(3), T => gpio_t(3), C => sysclk,PAD => WING_A(3) );
-- pin04: IOPAD port map(I => gpio_o(4), O => gpio_i(4), T => gpio_t(4), C => sysclk,PAD => WING_A(4) );
-- pin05: IOPAD port map(I => gpio_o(5), O => gpio_i(5), T => gpio_t(5), C => sysclk,PAD => WING_A(5) );
-- pin06: IOPAD port map(I => gpio_o(6), O => gpio_i(6), T => gpio_t(6), C => sysclk,PAD => WING_A(6) );
-- pin07: IOPAD port map(I => gpio_o(7), O => gpio_i(7), T => gpio_t(7), C => sysclk,PAD => WING_A(7) );
-- pin08: IOPAD port map(I => gpio_o(8), O => gpio_i(8), T => gpio_t(8), C => sysclk,PAD => WING_A(8) );
-- pin09: IOPAD port map(I => gpio_o(9), O => gpio_i(9), T => gpio_t(9), C => sysclk,PAD => WING_A(9) );
-- pin10: IOPAD port map(I => gpio_o(10),O => gpio_i(10),T => gpio_t(10),C => sysclk,PAD => WING_A(10) );
-- pin11: IOPAD port map(I => gpio_o(11),O => gpio_i(11),T => gpio_t(11),C => sysclk,PAD => WING_A(11) );
-- pin12: IOPAD port map(I => gpio_o(12),O => gpio_i(12),T => gpio_t(12),C => sysclk,PAD => WING_A(12) );
-- pin13: IOPAD port map(I => gpio_o(13),O => gpio_i(13),T => gpio_t(13),C => sysclk,PAD => WING_A(13) );
-- pin14: IOPAD port map(I => gpio_o(14),O => gpio_i(14),T => gpio_t(14),C => sysclk,PAD => WING_A(14) );
-- pin15: IOPAD port map(I => gpio_o(15),O => gpio_i(15),T => gpio_t(15),C => sysclk,PAD => WING_A(15) );
--
-- pin16: IOPAD port map(I => gpio_o(16),O => gpio_i(16),T => gpio_t(16),C => sysclk,PAD => WING_B(0) );
-- pin17: IOPAD port map(I => gpio_o(17),O => gpio_i(17),T => gpio_t(17),C => sysclk,PAD => WING_B(1) );
-- pin18: IOPAD port map(I => gpio_o(18),O => gpio_i(18),T => gpio_t(18),C => sysclk,PAD => WING_B(2) );
-- pin19: IOPAD port map(I => gpio_o(19),O => gpio_i(19),T => gpio_t(19),C => sysclk,PAD => WING_B(3) );
-- pin20: IOPAD port map(I => gpio_o(20),O => gpio_i(20),T => gpio_t(20),C => sysclk,PAD => WING_B(4) );
-- pin21: IOPAD port map(I => gpio_o(21),O => gpio_i(21),T => gpio_t(21),C => sysclk,PAD => WING_B(5) );
-- pin22: IOPAD port map(I => gpio_o(22),O => gpio_i(22),T => gpio_t(22),C => sysclk,PAD => WING_B(6) );
-- pin23: IOPAD port map(I => gpio_o(23),O => gpio_i(23),T => gpio_t(23),C => sysclk,PAD => WING_B(7) );
-- pin24: IOPAD port map(I => gpio_o(24),O => gpio_i(24),T => gpio_t(24),C => sysclk,PAD => WING_B(8) );
-- pin25: IOPAD port map(I => gpio_o(25),O => gpio_i(25),T => gpio_t(25),C => sysclk,PAD => WING_B(9) );
-- pin26: IOPAD port map(I => gpio_o(26),O => gpio_i(26),T => gpio_t(26),C => sysclk,PAD => WING_B(10) );
-- pin27: IOPAD port map(I => gpio_o(27),O => gpio_i(27),T => gpio_t(27),C => sysclk,PAD => WING_B(11) );
-- pin28: IOPAD port map(I => gpio_o(28),O => gpio_i(28),T => gpio_t(28),C => sysclk,PAD => WING_B(12) );
-- pin29: IOPAD port map(I => gpio_o(29),O => gpio_i(29),T => gpio_t(29),C => sysclk,PAD => WING_B(13) );
-- pin30: IOPAD port map(I => gpio_o(30),O => gpio_i(30),T => gpio_t(30),C => sysclk,PAD => WING_B(14) );
-- pin31: IOPAD port map(I => gpio_o(31),O => gpio_i(31),T => gpio_t(31),C => sysclk,PAD => WING_B(15) );
--
-- pin32: IOPAD port map(I => gpio_o(32),O => gpio_i(32),T => gpio_t(32),C => sysclk,PAD => WING_C(0) );
-- pin33: IOPAD port map(I => gpio_o(33),O => gpio_i(33),T => gpio_t(33),C => sysclk,PAD => WING_C(1) );
-- pin34: IOPAD port map(I => gpio_o(34),O => gpio_i(34),T => gpio_t(34),C => sysclk,PAD => WING_C(2) );
-- pin35: IOPAD port map(I => gpio_o(35),O => gpio_i(35),T => gpio_t(35),C => sysclk,PAD => WING_C(3) );
-- pin36: IOPAD port map(I => gpio_o(36),O => gpio_i(36),T => gpio_t(36),C => sysclk,PAD => WING_C(4) );
-- pin37: IOPAD port map(I => gpio_o(37),O => gpio_i(37),T => gpio_t(37),C => sysclk,PAD => WING_C(5) );
-- pin38: IOPAD port map(I => gpio_o(38),O => gpio_i(38),T => gpio_t(38),C => sysclk,PAD => WING_C(6) );
-- pin39: IOPAD port map(I => gpio_o(39),O => gpio_i(39),T => gpio_t(39),C => sysclk,PAD => WING_C(7) );
-- pin40: IOPAD port map(I => gpio_o(40),O => gpio_i(40),T => gpio_t(40),C => sysclk,PAD => WING_C(8) );
-- pin41: IOPAD port map(I => gpio_o(41),O => gpio_i(41),T => gpio_t(41),C => sysclk,PAD => WING_C(9) );
-- pin42: IOPAD port map(I => gpio_o(42),O => gpio_i(42),T => gpio_t(42),C => sysclk,PAD => WING_C(10) );
-- pin43: IOPAD port map(I => gpio_o(43),O => gpio_i(43),T => gpio_t(43),C => sysclk,PAD => WING_C(11) );
-- pin44: IOPAD port map(I => gpio_o(44),O => gpio_i(44),T => gpio_t(44),C => sysclk,PAD => WING_C(12) );
-- pin45: IOPAD port map(I => gpio_o(45),O => gpio_i(45),T => gpio_t(45),C => sysclk,PAD => WING_C(13) );
-- pin46: IOPAD port map(I => gpio_o(46),O => gpio_i(46),T => gpio_t(46),C => sysclk,PAD => WING_C(14) );
-- pin47: IOPAD port map(I => gpio_o(47),O => gpio_i(47),T => gpio_t(47),C => sysclk,PAD => WING_C(15) );
-- Other ports are special, we need to avoid outputs on input-only pins
ibufrx: IPAD port map ( PAD => RXD, O => rx, C => sysclk );
ibufmiso: IPAD port map ( PAD => SPI_FLASH_MISO, O => spi_pf_miso, C => sysclk );
obuftx: OPAD port map ( I => tx, PAD => TXD );
ospiclk: OPAD port map ( I => spi_pf_sck, PAD => SPI_FLASH_SCK );
ospics: OPAD port map ( I => gpio_o_reg(48), PAD => SPI_FLASH_CS );
ospimosi: OPAD port map ( I => spi_pf_mosi, PAD => SPI_FLASH_MOSI );
-- process(gpio_spp_read,
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
-- begin
--
-- gpio_spp_data <= (others => DontCareValue);
--
---- gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
---- gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
---- gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_spp_read(0); -- PPS0 : USPI MISO
---- uart2_rx <= gpio_spp_read(1); -- PPS0 : USPI MISO
--
-- end process;
end behave;
| mit | 794b6e1a9bc2c5c1e4955242165ab517 | 0.605147 | 2.630154 | false | false | false | false |
purisc-group/purisc | Compute_Group/CORE/execute_stage.vhd | 1 | 1,470 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity execute_stage is
port(
clk : in std_logic;
reset_n : in std_logic;
stall : in std_logic;
a_in : in std_logic_vector(31 downto 0);
b_in : in std_logic_vector(31 downto 0);
c_in : in std_logic_vector(31 downto 0);
da_in : in std_logic_vector(31 downto 0);
db_in : in std_logic_vector(31 downto 0);
next_pc : in std_logic_vector(31 downto 0);
noop_in : in std_logic;
b_out : out std_logic_vector(31 downto 0);
c_out : out std_logic_vector(31 downto 0);
db_out : out std_logic_vector(31 downto 0);
cbranch : out std_logic;
noop_out : out std_logic
);
end entity;
architecture a1 of execute_stage is
--signals
--components
begin
-- c may change (check that it always has a value)
-- db always changes
process(clk) begin
if(reset_n = '0') then
--initial values
noop_out <= '1';
cbranch <= '0';
elsif (rising_edge(clk)) then
if(stall = '0') then
-- SUB
db_out <= std_logic_vector(signed(db_in) - signed(da_in));
-- BLEQ --not testing the 'equal to zero' condition because that was done in the RD stage
if((signed(db_in) - signed(da_in)) < 0 and noop_in = '0' and not(c_in = next_pc)) then
cbranch <= '1';
else
cbranch <= '0';
end if;
b_out <= b_in;
c_out <= c_in;
noop_out <= noop_in;
else
--hold previous outputs on stall (automatic)
end if;
end if;
end process;
end architecture; | gpl-2.0 | a42cab66c25922c7294c7b027e254920 | 0.630612 | 2.763158 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/zpuino_top_icache.vhd | 13 | 15,630 | --
-- Top module for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.wishbonepkg.all;
entity zpuino_top_icache is
port (
clk: in std_logic;
rst: in std_logic;
-- Connection to board IO module
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type;
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type;
slot_interrupt: in slot_std_logic_type;
dbg_reset: out std_logic;
memory_enable: out std_logic;
-- Memory accesses (for DMA)
-- This is a master interface
m_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
m_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
m_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
m_wb_stall_o: out std_logic;
-- Memory connection
ram_wb_ack_i: in std_logic;
ram_wb_stall_i: in std_logic;
ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
ram_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
ram_wb_cyc_o: out std_logic;
ram_wb_stb_o: out std_logic;
ram_wb_sel_o: out std_logic_vector(3 downto 0);
ram_wb_we_o: out std_logic;
rom_wb_ack_i: in std_logic;
rom_wb_stall_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stb_o: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end entity zpuino_top_icache;
architecture behave of zpuino_top_icache is
component zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out std_logic_vector(wordSize-1 downto 0);
stack_a_write: in std_logic_vector(wordSize-1 downto 0);
stack_b_write: in std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: in std_logic_vector(3 downto 0);
stack_a_enable: in std_logic;
stack_b_writeenable: in std_logic_vector(3 downto 0);
stack_b_enable: in std_logic;
stack_a_addr: in std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: in std_logic_vector(stackSize_bits-1 downto 2)
);
end component zpuino_stack;
component wbarb2_1 is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master 0 signals
m0_wb_dat_o: out std_logic_vector(31 downto 0);
m0_wb_dat_i: in std_logic_vector(31 downto 0);
m0_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m0_wb_sel_i: in std_logic_vector(3 downto 0);
m0_wb_cti_i: in std_logic_vector(2 downto 0);
m0_wb_we_i: in std_logic;
m0_wb_cyc_i: in std_logic;
m0_wb_stb_i: in std_logic;
m0_wb_ack_o: out std_logic;
m0_wb_stall_o: out std_logic;
-- Master 1 signals
m1_wb_dat_o: out std_logic_vector(31 downto 0);
m1_wb_dat_i: in std_logic_vector(31 downto 0);
m1_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m1_wb_sel_i: in std_logic_vector(3 downto 0);
m1_wb_cti_i: in std_logic_vector(2 downto 0);
m1_wb_we_i: in std_logic;
m1_wb_cyc_i: in std_logic;
m1_wb_stb_i: in std_logic;
m1_wb_ack_o: out std_logic;
m1_wb_stall_o: out std_logic;
-- Slave signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic;
s0_wb_stall_i: in std_logic
);
end component;
component zpuino_debug_core is
port (
clk: in std_logic;
rst: in std_logic;
dbg_in: in zpu_dbg_out_type;
dbg_out: out zpu_dbg_in_type;
dbg_reset: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end component;
component wbmux2 is
generic (
select_line: integer;
address_high: integer:=31;
address_low: integer:=2
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_adr_i: in std_logic_vector(address_high downto address_low);
m_wb_sel_i: in std_logic_vector(3 downto 0);
m_wb_cti_i: in std_logic_vector(2 downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
-- Slave 0 signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(address_high downto address_low);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic;
-- Slave 1 signals
s1_wb_dat_i: in std_logic_vector(31 downto 0);
s1_wb_dat_o: out std_logic_vector(31 downto 0);
s1_wb_adr_o: out std_logic_vector(address_high downto address_low);
s1_wb_sel_o: out std_logic_vector(3 downto 0);
s1_wb_cti_o: out std_logic_vector(2 downto 0);
s1_wb_we_o: out std_logic;
s1_wb_cyc_o: out std_logic;
s1_wb_stb_o: out std_logic;
s1_wb_ack_i: in std_logic
);
end component wbmux2;
signal io_read: std_logic_vector(wordSize-1 downto 0);
signal io_write: std_logic_vector(wordSize-1 downto 0);
signal io_address: std_logic_vector(maxAddrBitIncIO downto 0);
signal io_stb: std_logic;
signal io_cyc: std_logic;
signal io_we: std_logic;
signal io_ack: std_logic;
signal wb_read: std_logic_vector(wordSize-1 downto 0);
signal wb_write: std_logic_vector(wordSize-1 downto 0);
signal wb_address: std_logic_vector(maxAddrBitIncIO downto 0);
signal wb_stb: std_logic;
signal wb_cyc: std_logic;
signal wb_sel: std_logic_vector(3 downto 0);
signal wb_we: std_logic;
signal wb_ack: std_logic;
signal interrupt: std_logic;
signal poppc_inst: std_logic;
signal dbg_pc: std_logic_vector(maxAddrBit downto 0);
signal dbg_opcode: std_logic_vector(7 downto 0);
signal dbg_opcode_in: std_logic_vector(7 downto 0);
signal dbg_sp: std_logic_vector(10 downto 2);
signal dbg_brk: std_logic;
signal dbg_stacka: std_logic_vector(wordSize-1 downto 0);
signal dbg_stackb: std_logic_vector(wordSize-1 downto 0);
signal dbg_step: std_logic := '0';
signal dbg_freeze: std_logic;
signal dbg_flush: std_logic;
signal dbg_valid: std_logic;
signal dbg_ready: std_logic;
signal dbg_inject: std_logic;
signal dbg_injectmode: std_logic;
signal dbg_idim: std_logic;
signal stack_a_addr,stack_b_addr: std_logic_vector(stackSize_bits-1 downto 2);
signal stack_a_writeenable, stack_b_writeenable: std_logic_vector(3 downto 0);
signal stack_a_enable,stack_b_enable: std_logic;
signal stack_a_write,stack_b_write: std_logic_vector(31 downto 0);
signal stack_a_read,stack_b_read: std_logic_vector(31 downto 0);
signal stack_clk: std_logic;
signal cache_flush: std_logic;
--signal memory_enable: std_logic;
signal cpu_ram_wb_clk_i: std_logic;
signal cpu_ram_wb_rst_i: std_logic;
signal cpu_ram_wb_ack_o: std_logic;
signal cpu_ram_wb_stall_o: std_logic;
signal cpu_ram_wb_dat_i: std_logic_vector(wordSize-1 downto 0);
signal cpu_ram_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal cpu_ram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal cpu_ram_wb_cyc_i: std_logic;
signal cpu_ram_wb_stb_i: std_logic;
signal cpu_ram_wb_sel_i: std_logic_vector(3 downto 0);
signal cpu_ram_wb_we_i: std_logic;
signal dbg_to_zpu: zpu_dbg_in_type;
signal dbg_from_zpu: zpu_dbg_out_type;
begin
core: zpu_core_extreme_icache
port map (
wb_clk_i => clk,
wb_rst_i => rst,
wb_ack_i => wb_ack,
wb_dat_i => wb_read,
wb_dat_o => wb_write,
wb_adr_o => wb_address,
wb_cyc_o => wb_cyc,
wb_stb_o => wb_stb,
wb_sel_o => wb_sel,
wb_we_o => wb_we,
wb_inta_i => interrupt,
poppc_inst => poppc_inst,
break => open,
cache_flush => cache_flush,
stack_clk => stack_clk,
stack_a_read => stack_a_read,
stack_b_read => stack_b_read,
stack_a_write => stack_a_write,
stack_b_write => stack_b_write,
stack_a_writeenable => stack_a_writeenable,
stack_b_writeenable => stack_b_writeenable,
stack_a_enable => stack_a_enable,
stack_b_enable => stack_b_enable,
stack_a_addr => stack_a_addr,
stack_b_addr => stack_b_addr,
rom_wb_ack_i => rom_wb_ack_i,
rom_wb_dat_i => rom_wb_dat_i,
rom_wb_adr_o => rom_wb_adr_o(maxAddrBit downto 0),
rom_wb_cyc_o => rom_wb_cyc_o,
rom_wb_stb_o => rom_wb_stb_o,
rom_wb_cti_o => rom_wb_cti_o,
rom_wb_stall_i => rom_wb_stall_i,
dbg_in => dbg_to_zpu,
dbg_out => dbg_from_zpu
);
stack: zpuino_stack
port map (
stack_clk => stack_clk,
stack_a_read => stack_a_read,
stack_b_read => stack_b_read,
stack_a_write => stack_a_write,
stack_b_write => stack_b_write,
stack_a_writeenable => stack_a_writeenable,
stack_b_writeenable => stack_b_writeenable,
stack_a_enable => stack_a_enable,
stack_b_enable => stack_b_enable,
stack_a_addr => stack_a_addr,
stack_b_addr => stack_b_addr
);
dbg: zpuino_debug_core
port map (
clk => clk,
rst => rst,
dbg_out => dbg_to_zpu,
dbg_in => dbg_from_zpu,
dbg_reset => dbg_reset,
jtag_data_chain_out => jtag_data_chain_out,
jtag_ctrl_chain_in => jtag_ctrl_chain_in
);
io: zpuino_io
port map (
wb_clk_i => clk,
wb_rst_i => rst,
wb_dat_o => io_read,
wb_dat_i => io_write,
wb_adr_i => io_address,
wb_cyc_i => io_cyc,
wb_stb_i => io_stb,
wb_ack_o => io_ack,
wb_we_i => io_we,
wb_inta_o => interrupt,
intready => poppc_inst,
cache_flush => cache_flush,
memory_enable => memory_enable,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt
);
iomemmux: wbmux2
generic map (
select_line => maxAddrBitIncIO,
address_high =>maxAddrBitIncIO,
address_low=>0
)
port map (
wb_clk_i => clk,
wb_rst_i => rst,
-- Master
m_wb_dat_o => wb_read,
m_wb_dat_i => wb_write,
m_wb_adr_i => wb_address,
m_wb_sel_i => wb_sel,
m_wb_cti_i => CTI_CYCLE_CLASSIC,--wb_cti,
m_wb_we_i => wb_we,
m_wb_cyc_i => wb_cyc,
m_wb_stb_i => wb_stb,
m_wb_ack_o => wb_ack,
-- Slave 0 signals
s0_wb_dat_i => cpu_ram_wb_dat_o,
s0_wb_dat_o => cpu_ram_wb_dat_i,
s0_wb_adr_o => cpu_ram_wb_adr_i,
s0_wb_sel_o => cpu_ram_wb_sel_i,
s0_wb_cti_o => open,--cpu_ram_wb_sel_i,
s0_wb_we_o => cpu_ram_wb_we_i,
s0_wb_cyc_o => cpu_ram_wb_cyc_i,
s0_wb_stb_o => cpu_ram_wb_stb_i,
s0_wb_ack_i => cpu_ram_wb_ack_o,
-- Slave 1 signals
s1_wb_dat_i => io_read,
s1_wb_dat_o => io_write,
s1_wb_adr_o => io_address,
s1_wb_sel_o => open,
s1_wb_cti_o => open,
s1_wb_we_o => io_we,
s1_wb_cyc_o => io_cyc,
s1_wb_stb_o => io_stb,
s1_wb_ack_i => io_ack
);
memarb: wbarb2_1
generic map (
ADDRESS_HIGH => maxAddrBit,
ADDRESS_LOW => 0
)
port map (
wb_clk_i => clk,
wb_rst_i => rst,
-- Master 0 signals (CPU)
m0_wb_dat_o => cpu_ram_wb_dat_o,
m0_wb_dat_i => cpu_ram_wb_dat_i,
m0_wb_adr_i => cpu_ram_wb_adr_i(maxAddrBit downto 0),
m0_wb_sel_i => cpu_ram_wb_sel_i,
m0_wb_cti_i => CTI_CYCLE_CLASSIC,
m0_wb_we_i => cpu_ram_wb_we_i,
m0_wb_cyc_i => cpu_ram_wb_cyc_i,
m0_wb_stb_i => cpu_ram_wb_stb_i,
m0_wb_ack_o => cpu_ram_wb_ack_o,
m0_wb_stall_o => cpu_ram_wb_stall_o,
-- Master 1 signals
m1_wb_dat_o => m_wb_dat_o,
m1_wb_dat_i => m_wb_dat_i,
m1_wb_adr_i => m_wb_adr_i(maxAddrBit downto 0),
m1_wb_sel_i => (others => '1'),
m1_wb_cti_i => CTI_CYCLE_CLASSIC,
m1_wb_we_i => m_wb_we_i,
m1_wb_cyc_i => m_wb_cyc_i,
m1_wb_stb_i => m_wb_stb_i,
m1_wb_ack_o => m_wb_ack_o,
m1_wb_stall_o => m_wb_stall_o,
-- Slave signals
s0_wb_dat_i => ram_wb_dat_i,
s0_wb_dat_o => ram_wb_dat_o,
s0_wb_adr_o => ram_wb_adr_o(maxAddrBit downto 0),
s0_wb_sel_o => ram_wb_sel_o,
s0_wb_cti_o => open,
s0_wb_we_o => ram_wb_we_o,
s0_wb_cyc_o => ram_wb_cyc_o,
s0_wb_stb_o => ram_wb_stb_o,
s0_wb_ack_i => ram_wb_ack_i,
s0_wb_stall_i => ram_wb_stall_i
);
end behave;
| mit | 6295ee74ce4be0bcc859e98349d053db | 0.602431 | 2.720153 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/sid_filters.vhd | 13 | 6,581 | --
-- (C) Alvaro Lopes <[email protected]> All Rights Reserved
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sid_filters is
port (
clk: in std_logic; -- At least 12Mhz
rst: in std_logic;
-- SID registers.
Fc_lo: in std_logic_vector(7 downto 0);
Fc_hi: in std_logic_vector(7 downto 0);
Res_Filt: in std_logic_vector(7 downto 0);
Mode_Vol: in std_logic_vector(7 downto 0);
-- Voices - resampled to 13 bit
voice1: in signed(12 downto 0);
voice2: in signed(12 downto 0);
voice3: in signed(12 downto 0);
--
input_valid: in std_logic;
ext_in: in signed(12 downto 0);
sound: out signed(18 downto 0);
valid: out std_logic
);
end entity;
architecture beh of sid_filters is
alias filt: std_logic_vector(3 downto 0) is Res_Filt(3 downto 0);
alias res: std_logic_vector(3 downto 0) is Res_Filt(7 downto 4);
alias voice3off: std_logic is Mode_Vol(7);
alias volume: std_logic_vector(3 downto 0) is Mode_Vol(3 downto 0);
alias hp_bp_lp: std_logic_vector(2 downto 0) is Mode_Vol(6 downto 4);
constant mixer_DC: integer := -475; -- NOTE to self: this might be wrong.
component sid_coeffs is
port (
clk: in std_logic;
addr: in integer range 0 to 2047;
val: out std_logic_vector(15 downto 0)
);
end component;
type regs_type is record
Vhp: signed(17 downto 0);
Vbp: signed(17 downto 0);
dVbp: signed(17 downto 0);
Vlp: signed(17 downto 0);
dVlp: signed(17 downto 0);
Vi: signed(17 downto 0);
Vnf: signed(17 downto 0);
Vf: signed(17 downto 0);
w0: signed(17 downto 0);
q: signed(17 downto 0);
vout:signed(18 downto 0);
state: integer;
done: std_logic;
end record;
signal dVhp_debug: signed(31 downto 0);
signal dVbp_debug: signed(31 downto 0);
signal addr: integer range 0 to 2047;
signal val: std_logic_vector(15 downto 0);
type divmul_t is array(0 to 15) of integer;
constant divmul: divmul_t := (
1448, 1323, 1218, 1128, 1051, 984, 925, 872, 825, 783, 745, 710, 679, 650, 624, 599
);
signal r: regs_type;
signal mula: signed(17 downto 0);
signal mulb: signed(17 downto 0);
signal mulr: signed(35 downto 0);
signal mulen: std_logic;
function s13_to_18(a: in signed(12 downto 0)) return signed is
variable r: signed(17 downto 0);
begin
r(12 downto 0):=a;
r(13):=a(12);
r(14):=a(12);
r(15):=a(12);
r(16):=a(12);
r(17):=a(12);
return r;
end function;
-- Debugging
signal dbg_Vlp, dbg_Vhp, dbg_Vbp: signed(17 downto 0);
signal fc: std_logic_vector(10 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if mulen='1' then
mulr <= mula * mulb;
end if;
end if;
end process;
fc <= Fc_hi & Fc_lo(2 downto 0);
c: sid_coeffs
port map (
clk => clk,
addr => addr,
val => val
);
addr <= to_integer(unsigned(fc));
process(clk, rst, r, input_valid, val, filt, voice1, voice2, voice3, voice3off, mulr, ext_in, hp_bp_lp, Mode_Vol)
variable w: regs_type;
begin
w:=r;
mula <= (others => 'X');
mulb <= (others => 'X');
mulen <= '0';
case r.state is
when 0 =>
w.done := '0';
if input_valid = '1' then
w.state := 1;
-- Reset Vin, Vnf
w.vi := (others => '0');
w.vnf := (others => '0');
end if;
when 1 =>
-- already have W0 ready. Always positive
w.w0 := "00" & signed(val);
-- 1st accumulation
if filt(0)='1' then
w.vi := r.vi + s13_to_18(voice1);
else
w.vnf := r.vnf + s13_to_18(voice1);
end if;
w.state := 2;
when 2 =>
-- 2nd accumulation
if filt(1)='1' then
w.vi := r.vi + s13_to_18(voice2);
else
w.vnf := r.vnf + s13_to_18(voice2);
end if;
-- Mult
mula <= r.w0;
mulb <= r.vhp;
mulen <= '1';
w.state := 3;
when 3 =>
-- 3rd accumulation
if filt(2)='1' then
w.vi := r.vi + s13_to_18(voice3);
else
if voice3off='0' then
w.vnf := r.vnf + s13_to_18(voice3);
end if;
end if;
-- Mult
mula <= r.w0;
mulb <= r.vbp;
mulen <= '1';
w.dVbp := mulr(35) & mulr(35 downto 19);
w.state := 4;
when 4 =>
-- 4th accumulation
if filt(3)='1' then
w.vi := r.vi + s13_to_18(ext_in);
else
w.vnf := r.vnf + s13_to_18(ext_in);
end if;
w.dVlp := mulr(35) & mulr(35 downto 19);
w.Vbp := r.Vbp - r.dVbp;
-- Get Q, synchronous.
w.q := to_signed(divmul(to_integer(unsigned(res))), 18);
w.state := 5;
when 5 =>
-- Ok, we have all summed. We performed multiplications for dVbp and dVlp.
-- new Vbp already computed.
mulen <= '1';
mula <= r.q;
mulb <= r.Vbp;
w.vlp := r.Vlp - r.dVlp;
-- Start computing output;
if hp_bp_lp(1)='1' then
w.Vf := r.Vbp;
else
w.Vf := (others => '0');
end if;
w.state := 6;
when 6 =>
-- Adjust Vbp*Q, shift by 10
w.Vhp := (mulr(35)&mulr(35)&mulr(25 downto 10)) - r.vlp;
if hp_bp_lp(0)='1' then
w.Vf := r.Vf + r.Vlp;
end if;
w.state := 7;
when 7 =>
w.Vhp := r.Vhp - r.Vi;
w.state := 8;
when 8 =>
if hp_bp_lp(2)='1' then
w.Vf := r.Vf + r.Vhp;
end if;
w.state := 9;
when 9 =>
w.Vf := r.Vf + r.Vnf;
w.state := 10;
when 10 =>
-- Add mixer DC
w.Vf := r.Vf + to_signed(mixer_DC, r.Vf'LENGTH);
w.state := 11;
when 11 =>
-- Process volume
mulen <= '1';
mula <= r.Vf;
mulb <= (others => '0');
mulb(3 downto 0) <= signed(volume);
w.state := 12;
when 12 =>
w.done := '1';
w.vout(18) := mulr(35);
w.vout(17 downto 0) := mulr(17 downto 0);
w.state := 0;
when others =>
end case;
if rst='1' then
w.done := '0';
w.state := 0;
w.Vlp := (others => '0');
w.Vbp := (others => '0');
w.Vhp := (others => '0');
end if;
if rising_edge(clk) then
r<=w;
if r.state=8 then
dbg_Vbp <= r.vbp;
dbg_Vhp <= r.vhp;
dbg_Vlp <= r.vlp;
end if;
end if;
end process;
sound <= r.vout;
valid <= r.done;
end beh;
| mit | 5aeb98472106a478b65dd47da36d230d | 0.513296 | 3.031322 | false | false | false | false |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/pikachu_pixel_1/pikachu_pixel_sim_netlist.vhdl | 1 | 92,798 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:31:21 2017
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/pikachu_pixel_1/pikachu_pixel_sim_netlist.vhdl
-- Design : pikachu_pixel
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pikachu_pixel_blk_mem_gen_mux is
port (
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
addra : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
DOADO : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of pikachu_pixel_blk_mem_gen_mux : entity is "blk_mem_gen_mux";
end pikachu_pixel_blk_mem_gen_mux;
architecture STRUCTURE of pikachu_pixel_blk_mem_gen_mux is
signal sel_pipe : STD_LOGIC;
signal sel_pipe_d1 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \douta[10]_INST_0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \douta[11]_INST_0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \douta[4]_INST_0\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \douta[5]_INST_0\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \douta[6]_INST_0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \douta[7]_INST_0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \douta[8]_INST_0\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \douta[9]_INST_0\ : label is "soft_lutpair2";
begin
\douta[10]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => DOADO(6),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(6),
I2 => sel_pipe_d1,
O => douta(6)
);
\douta[11]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => DOADO(7),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(7),
I2 => sel_pipe_d1,
O => douta(7)
);
\douta[4]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => DOADO(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(0),
I2 => sel_pipe_d1,
O => douta(0)
);
\douta[5]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => DOADO(1),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(1),
I2 => sel_pipe_d1,
O => douta(1)
);
\douta[6]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => DOADO(2),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(2),
I2 => sel_pipe_d1,
O => douta(2)
);
\douta[7]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => DOADO(3),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(3),
I2 => sel_pipe_d1,
O => douta(3)
);
\douta[8]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => DOADO(4),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(4),
I2 => sel_pipe_d1,
O => douta(4)
);
\douta[9]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => DOADO(5),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(5),
I2 => sel_pipe_d1,
O => douta(5)
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => sel_pipe,
Q => sel_pipe_d1,
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => addra(0),
Q => sel_pipe,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pikachu_pixel_blk_mem_gen_prim_wrapper_init is
port (
douta : out STD_LOGIC_VECTOR ( 3 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of pikachu_pixel_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end pikachu_pixel_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of pikachu_pixel_blk_mem_gen_prim_wrapper_init is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 4 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000001000000000000000000000",
INIT_09 => X"0000000000000000000000000210000000000000000000000000000000000000",
INIT_0A => X"0000000001100000001100000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000001200000000000000000000000000000000",
INIT_0C => X"0000000000000100000000000000000000000000000000000000000000111100",
INIT_0D => X"0000000000000000000000000000000000000000001110000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000174000000000000000000000000000000000000000",
INIT_11 => X"000002FA00000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"00000000000000000000000000000000000000000000000000002F9000011000",
INIT_14 => X"0000000000000000000000000000000000027400001000000000000000000000",
INIT_15 => X"0000000000000000011000000000000000000000000000000000000000000000",
INIT_16 => X"0000100000000000000000000000000000000000000011000000000000000000",
INIT_17 => X"0000000000000000000000000000110000000000000000000000000000000000",
INIT_18 => X"0000000000011000000000000000000000000000000000000001000000000100",
INIT_19 => X"0000000000000000000000000000000000000000000010000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000001100000000000000000000000000000000000000",
INIT_20 => X"0000000110000000000000000000000000001000000000000000000000000000",
INIT_21 => X"0000000000000000000210000000000000000000000000000000000000000000",
INIT_22 => X"0001100000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000011000000000000",
INIT_25 => X"0000002100000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000033000000",
INIT_28 => X"0000000000000000000000000000000000000000310000000000000000000000",
INIT_29 => X"0000000000010000000000001000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000001200000",
INIT_2C => X"0000000000000000000000000000000000000001200000000000000000000000",
INIT_2D => X"0000000000000000000011000000000000000000000000000000000000000000",
INIT_2E => X"0000200000000000000000010000000000000000000000000000000000000000",
INIT_2F => X"0000001000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000011000000000000",
INIT_34 => X"0000000000000000000000000000001102300000000000001100000000000000",
INIT_35 => X"0000000000000000000000000000000001000000000000000000000000000000",
INIT_36 => X"0000000000000000110000000000000000000000000000021000000000000000",
INIT_37 => X"1100000000000000000000000000000000000000000000000000001000000000",
INIT_38 => X"0000000000000000000000000000000000000210000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000100000000000000",
INIT_3A => X"0000000000000000000000000000000010000000000000200000000000001100",
INIT_3B => X"0000000000000000000000000000110000000000000010000000000000000000",
INIT_3C => X"0100000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000010000000000000000000000000000000",
INIT_3E => X"0000110000000001000000000000000000000000000000001100000000000000",
INIT_3F => X"0000000000000000000000000000000011000000000000000000000000000000",
INIT_40 => X"0000000000000000010000000000000000000000000000000002300000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000001000001000000000000000000000000000000000",
INIT_45 => X"0000000100001100000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000110000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000001100000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000045000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"00000000000000000000000000000000000000000000000000000000000006A1",
INIT_54 => X"0000000000000000000000000000000000000000000033000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000020000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"1100010000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000001100000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000011000000000000000000000100000",
INIT_64 => X"0000000000000000000110000000000000000000010000000000000010000000",
INIT_65 => X"0001000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000001011000000000000000000000000000000000000000000",
INIT_67 => X"1202200000000000000000000000000000000000000000000000010000100000",
INIT_68 => X"0000000000000000000000000000000000001100110000000000000000000000",
INIT_69 => X"0000000000000000000022200000000000000000000000210000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 4,
READ_WIDTH_B => 4,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 4,
WRITE_WIDTH_B => 4
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 2) => addra(12 downto 0),
ADDRARDADDR(1 downto 0) => B"11",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 4) => B"0000000000000000000000000000",
DIADI(3 downto 0) => dina(3 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 4) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 4),
DOADO(3 downto 0) => douta(3 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \pikachu_pixel_blk_mem_gen_prim_wrapper_init__parameterized0\ is
port (
\douta[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \pikachu_pixel_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init";
end \pikachu_pixel_blk_mem_gen_prim_wrapper_init__parameterized0\;
architecture STRUCTURE of \pikachu_pixel_blk_mem_gen_prim_wrapper_init__parameterized0\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal ena_array : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_01 => X"4F4F4F4F4F4F4F4F4F4F0000000000000000004F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_02 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_03 => X"7777000000000000004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_04 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F000000000000337777",
INIT_05 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_06 => X"4F4F4F4F4F4F00000000001199FFFFFFEE33111111111111114F4F4F4F4F4F4F",
INIT_07 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_08 => X"EEDDDDDDDDDDDD660000000000004F4F4F4F00000000000000000000004F4F4F",
INIT_09 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F00000011DDFFFFFFFFFF",
INIT_0A => X"00667777777777777777774400004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_0B => X"4F4F4F4F4F4F000011888899FFFFFFFFFFFFFFFFFFFFCC778888770000000000",
INIT_0C => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_0D => X"FFFFFFFFFFFFFFFFEEDD110011111133FFFFFFFFFFFFFFFFFFFF881111114F4F",
INIT_0E => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F000000CCFFFFFFFF",
INIT_0F => X"FFFFFFFFFFFFFFFFFFEEDDDD660000004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_10 => X"4F4F4F4F4F4F4F4F4F4F1199FFFFFFFFFFFFFFFFFFFF2211000066DDDDDDEEFF",
INIT_11 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_12 => X"CC8877777766666677CCFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCC77774400",
INIT_13 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F000000000000004F4F4F005599FFFFFFFF",
INIT_14 => X"FFFFFFFFFFFFFFFFFFFFFFFFFF88114F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_15 => X"00001111114F4F4F4F0000CCEEEEEE6600000022FFFFFFFFFFFFFFFFFFFFFFFF",
INIT_16 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F000000",
INIT_17 => X"CCDDEEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEECC0000",
INIT_18 => X"4F4F4F4F4F4F4F4F4F4F4F000000000000CCDDCC000000000000001111110000",
INIT_19 => X"FFFFFFFFFFFFFFFFFFFFFFFFFF8844004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_1A => X"FFFFFF887777777777666666667788FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1B => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F000000004499",
INIT_1C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEEEEFFFF77004F",
INIT_1D => X"4F4F4F4F4F4F4F4F4F4F00000077FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1E => X"FFFFFFFFFFFFFFEE1188FFFF77004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_1F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_20 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F001133FFFF",
INIT_21 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBB77666688FFBB77114F4F",
INIT_22 => X"4F4F4F4F4F4F4F4F4F4F00000077CCFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_23 => X"FFFFFFFF6600FF7700DDFFEE11004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_24 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_25 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F0077EEFF",
INIT_26 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF6611FF8800DDFFDD00004F4F4F",
INIT_27 => X"4F4F4F4F4F4F4F4F4F4F4F4F1133FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_28 => X"FFFF7700773311EEFFEE884400004F4F0000004F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_29 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2A => X"0000004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F000077CCFF",
INIT_2B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7700000011EEFFFFFF881111114F00",
INIT_2C => X"4F4F4F4F4F4F4F4F4F4F00000077EEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2D => X"7700000011EEFFFFFFEEDDDD770000111100004F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_2E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2F => X"0000004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F1133EEFF",
INIT_30 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7700000011EEFFFFFFFFFFFF88000088CC",
INIT_31 => X"4F4F4F4F4F4F4F4F4F4F4F0011EEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_32 => X"000033EEFFFFFFFFFFFF77000099FF8833000000004F4F4F4F4F4F4F4F4F4F4F",
INIT_33 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8811",
INIT_34 => X"111100004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F0011EEFFFFFF",
INIT_35 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFEEBB0055EEFFFFFFFFFFFFFF77000088FFFF88",
INIT_36 => X"4F4F4F4F4F4F4F4F4F0011EEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_37 => X"FFFFFFFFFFFFFFFF77000088FFFFEEDDDD660000004F4F4F4F4F4F4F4F4F4F4F",
INIT_38 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF89BC",
INIT_39 => X"CC77774400004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F005588EEFFFFFFFFFF",
INIT_3A => X"FFFFFFFFFFFFFFFFFFFFFEFEFEFFFFFFFFFFFFFFFFFFFF7700005599FFFFFFFF",
INIT_3B => X"4F4F4F4F4F4F0088FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3C => X"FFFFFFFFFFFF77004F0011EEFFFFFFFFFFFF881100004F4F4F4F4F4F4F4F4F4F",
INIT_3D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3F1F2F2F9FFFF",
INIT_3E => X"FFEECC00000000004F4F4F4F4F4F4F4F4F4F4F4F4F0088FFFFFFFFFFFFFFFFFF",
INIT_3F => X"FFFFFFFFFFFFFBF7F0F0F0F0F3F9FFFFFFFFFFFFFF88004F0011EEFFFFFFFFFF",
INIT_40 => X"4F4F4F4F0088FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_41 => X"FFFFFFEE77004F0022EEFFFFFFFFFFFFFFFF887766000000004F4F4F4F4F4F4F",
INIT_42 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7F0F0F0F0F0F0F1FEFFFF",
INIT_43 => X"FFFFFFEE33111100004F4F4F4F4F4F4F4F4F4F0077EEFFFFFFFFFFFFFFFFFFFF",
INIT_44 => X"FFFFFFFFF7F0F0F0F0F0F0F1FEFFFFFFFFFF33114F4F0011CCFFFFFFFFFFFFFF",
INIT_45 => X"4F4F4F1133EEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_46 => X"7700004F4F4F4F1199FFFFFFFFFFFFFFFFFFFFEEDDCC0000004F4F4F4F4F4F4F",
INIT_47 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7F0F0F0F0F0F0F1FEFFFFFFCC",
INIT_48 => X"FFFFFFFFFF887766114F4F4F4F4F4F4F4F4F0011EEFFFFFFFFFFFFFFFFFFFFFF",
INIT_49 => X"FFFFF7F0F0F0F0F0F0F1FEFFFFEE660000004F4F4F4F00448888CCFFFFFFFFFF",
INIT_4A => X"4F0011EEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_4B => X"004F4F4F4F4F00000077EEFFFFFFFFFFFFFFFFFFFFFFEE11004F4F4F4F4F4F4F",
INIT_4C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7F0F0F0F0F0F0F1FEFFEE22000000",
INIT_4D => X"FFFFFFFFFFEE11004F4F4F4F4F4F4F4F0011EEFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_4E => X"FBF6F0F0F0F0F3F8FEFFEE77330000004F4F4F4F4F4F4F4F1133FFFFFFFFFFFF",
INIT_4F => X"22EEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_50 => X"4F4F4F4F4F4F4F4F0077CCFFFFFFFFFFFFFFFFBB7711004F4F4F4F4F4F4F4F00",
INIT_51 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEF3F1F1F1F9FFFFFFFFFF88004F4F4F",
INIT_52 => X"FFFF77004F4F4F4F4F4F4F4F4F4F0011CCFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_53 => X"FEFDFDFDFFFFFFFFFFFF88004F4F4F4F4F4F4F4F4F4F4F4F0077FFFFFFFFFFFF",
INIT_54 => X"99FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_55 => X"4F4F4F4F4F4F4F0088FFFFFFFFFFFFFFFF77004F4F4F4F4F4F4F4F4F4F4F4F11",
INIT_56 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9955004F4F4F4F4F",
INIT_57 => X"88004F4F4F4F4F4F4F4F4F4F4F4F0063D8C8ECFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_58 => X"FFFFFFFFFFFFCC00004F4F4F4F4F4F4F4F4F4F4F4F4F005599FFFFFFFFFFFFFF",
INIT_59 => X"90C6FEFEFEFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5A => X"4F4F4F4F4F4F0000CCFFFFFFFFFFEE66004F4F4F4F4F4F4F4F4F4F4F4F004090",
INIT_5B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF99114F4F4F4F4F4F4F4F4F4F",
INIT_5C => X"4F4F4F4F4F4F4F4F4F4F4F4F4F012180A0A1A1A1B3FFFFFFFFFFFFFFFFFFFFFF",
INIT_5D => X"FFEE9944004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F1199FFFFFFEE330000",
INIT_5E => X"90909090C7C8D9FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5F => X"4F4F4F4F4F4F0077FFFFFFDD0000004F4F4F4F4F4F4F4F4F4F4F4F4F010180A0",
INIT_60 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDD00004F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_61 => X"4F4F4F4F4F4F4F4F4F4F4F001080A0909090909090A0ECFFFFFFFFFFFFFFFFFF",
INIT_62 => X"00004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F0088FFFFFFDD11004F4F4F",
INIT_63 => X"A0A0909090A1D9FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDD",
INIT_64 => X"4F4F4F4F0088FFFFFFDD0000004F4F4F4F4F4F4F4F4F4F4F4F4F001080A09090",
INIT_65 => X"FFAA77FFFFFFFFFFFFFFFFFFFFFFEE8844004F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_66 => X"4F4F4F4F4F4F4F4F4F0010B6D7C7C7734080908080C7FFFFFFFFFFFFFFFFFFFF",
INIT_67 => X"114F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F0077FFFFFFEE8877660000004F",
INIT_68 => X"91A385A1D8FFFFFFFFFFFFFFFFFFFFFF7711CCEEFFFFFFFFFFFFFFFFFFFFFF88",
INIT_69 => X"4F4F1199FFFFFFFFFFFFEE3311114F4F4F4F4F4F4F4F4F4F0012EEFFFFFF7811",
INIT_6A => X"BB1188FFFFFFFFFFFFFFFFFFFFFFEECC11004F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_6B => X"4F4F4F4F4F4F4F0011EEFFFFFFEEDDFDFEEEFDFEFFFFFFFFFFFFFFFFFFFFFFEE",
INIT_6C => X"004F4F4F4F4F4F4F4F4F4F4F4F4F4F0000CCEEFFFFFFFFFFFFFFEEDDCC000000",
INIT_6D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF775577FFFFFFFFFFFFFFFFFFFFFFEE11",
INIT_6E => X"FFFFFFFFFFFFFFFFFFFFFFFF996430004F4F4F4F4F4F0011EEFFFFFFFFFFFFFF",
INIT_6F => X"7711CCEEFFFFFFFFFFFFFFFFFFDD11004F4F4F4F4F4F4F4F4F4F4F4F4F005599",
INIT_70 => X"4F4F4F4F4F0011EEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_71 => X"4F4F4F4F4F4F4F4F4F4F4F4F0077FFFFFFFFFFFFFFFFFFFFFFFFFFFFD7801000",
INIT_72 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEEBB1188FFFFFFFFFFFFFFFFFFDD00004F",
INIT_73 => X"FFFFFFFFFFFFFFFFFFFFB3B09011014F4F4F4F4F0011EEFFFFFFFFFFFFFFFFFF",
INIT_74 => X"775577FFFFFFFFFFFFFFFFEE8844004F4F4F4F4F4F4F4F4F4F4F4F4F1133FFFF",
INIT_75 => X"4F4F005588EEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_76 => X"4F4F4F4F4F4F4F4F4F4F4F4F00778899FFFFFFFFFFFFFFECC7A0704101014F4F",
INIT_77 => X"FFFFFFFFEEEEEEFFFFFFFFFFFFFFFFFF7711CCEEFFFFFFFFFFFFFFFF88004F4F",
INIT_78 => X"EEEEFFFFFFFEC690A0410100004F4F4F4F0088FFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_79 => X"BB1188FFFFFFFFFFFFFFFF77004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F000000CC",
INIT_7A => X"0088FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF88111199FFFFFFFFFFFFFFFFEE",
INIT_7B => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F111133FFFFFFB390A0A040004F4F4F4F4F4F",
INIT_7C => X"FFFFBB66666677777799FFFFFFFFFFFF775577FFFFFFFFFFFFFF77004F4F4F4F",
INIT_7D => X"77B8D7A08091A040004F4F4F4F00000088FFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7E => X"7711CCEEFFFFFFFFFF77004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F000000",
INIT_7F => X"FEFEFEFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8800000000CCFFFFFFFFFFFF",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[11]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => addra(12),
O => ena_array(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \pikachu_pixel_blk_mem_gen_prim_wrapper_init__parameterized1\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \pikachu_pixel_blk_mem_gen_prim_wrapper_init__parameterized1\ : entity is "blk_mem_gen_prim_wrapper_init";
end \pikachu_pixel_blk_mem_gen_prim_wrapper_init__parameterized1\;
architecture STRUCTURE of \pikachu_pixel_blk_mem_gen_prim_wrapper_init__parameterized1\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F0000003090A09283A040004F4F4F4F00000077",
INIT_01 => X"FFFFFFEEDDDD55000099FFFFFFFFFFEEBB1188FFFFFFFFFF77004F4F4F4F4F4F",
INIT_02 => X"2090A0A0A0410100004F4F00000051B1A1A1B3FFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_03 => X"886677EEFFFFFF77004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F0000",
INIT_04 => X"9090C7ECFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCC77666677FFFFFFFFFFFF",
INIT_05 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F0000004050509070410000004F000040709090",
INIT_06 => X"FFFFFFFFFFFFFF7711CCEEFFFFFFFFEE6611EEFFFFFF88004F4F4F4F4F4F4F4F",
INIT_07 => X"020180B0902000004F001090A09090909090C6FEFEFFFFFFFFFFFFFFFFFFFFFF",
INIT_08 => X"DDFFFFFFFF88114F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F000001",
INIT_09 => X"9090A191D8FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEEBB1188FFFFFFEE2266",
INIT_0A => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F02017090A090300000001080A090909090",
INIT_0B => X"FFFFFFFFFFFFFF77667777777766BBFFFFFFFFFF88114F4F4F4F4F4F4F4F4F4F",
INIT_0C => X"3170A0A0704000001080A090909090C6C7C6C6EBFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0D => X"FFFFFF88114F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F0001",
INIT_0E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8800000022FFFFFFFF",
INIT_0F => X"4F4F4F4F4F4F4F4F4F4F4F4F4F000001419090A09020011180A090A1A1B3FFFF",
INIT_10 => X"FFFFFFFFFFFFEEDDDDDDEEFFFFFFFFFFFFFF88114F4F4F4F4F4F4F4F4F4F4F4F",
INIT_11 => X"2190A0909030008090A0ECFDFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_12 => X"FF99114F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F0001",
INIT_13 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_14 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F0001014080B0B04001B7D8E9FFFFFFFFFFFFFF",
INIT_15 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEE88114F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_16 => X"4090903023DDEFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_17 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F00",
INIT_18 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEE5544",
INIT_19 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F00101150A0B15233EEFFFFFFFFFFFFFFFF",
INIT_1A => X"FFFFFFFFFFFFFFFFFFFFFFFFEE33114F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_1B => X"012160A03001DEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1C => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F00",
INIT_1D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDD44004F4F",
INIT_1E => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F000001803011EEFFFFFFFFFFFFFFFFFFFF",
INIT_1F => X"FFFFFFFFFFFFFFFFFF9933774F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_20 => X"00100011EEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_21 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F00",
INIT_22 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF88004F4F4F4F4F4F",
INIT_23 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F105455002388EEFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_24 => X"FFFFFFFFFFFFFF88114F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_25 => X"88FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_26 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F1076AA22",
INIT_27 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF99114F4F4F4F4F4F4F4F",
INIT_28 => X"4F4F4F4F4F4F4F4F4F4F4F4F1022CCEEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_29 => X"FFFFFFFF9966334F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_2A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2B => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F004488FFFFFF",
INIT_2C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEE44334F4F4F4F4F4F4F4F4F4F4F",
INIT_2D => X"4F4F4F4F4F4F4F4F4F1199FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2E => X"FFFFEE660000004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_2F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_30 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F0011CCFFFFFFFFFFFFFF",
INIT_31 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBB777744004F4F4F4F4F4F4F4F4F",
INIT_32 => X"4F4F4F4F4F0022FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_33 => X"FFFFFFFF88004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_34 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_35 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F0011EEFFFFFFFFFFFFFFFFFF",
INIT_36 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF88004F4F4F4F4F4F4F4F4F4F4F",
INIT_37 => X"4F4F4F0022EEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_38 => X"EE9955004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_39 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3A => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F001177CCFFFFFFFFFFFFFFFFFFFF",
INIT_3B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDD00004F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_3C => X"4F4F4F0077EEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3D => X"004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_3E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEE11",
INIT_3F => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F1133FFFFFFFFFFFFFFFFFFFFFF",
INIT_40 => X"FFFFFFFFFFFFFFFFFFFFFFFFCC7711004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_41 => X"4F4F000077CCFFFFFFFFFFFFFFFFCC8888888888888888888888CCFFFFFFFFFF",
INIT_42 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_43 => X"00000000000000000066EEEEEEEEFFFFFFFFFFFFFFFFFFFFFFFFEE66004F4F4F",
INIT_44 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F00000066EEFFFFFFFFFFFFEE660000",
INIT_45 => X"FFFFFFFFFFFFFFFFFF33114F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_46 => X"4F4F000033FFFFFFFFFFEE33114F4F4F4F4F4F4F4F4F4F000011111133FFFFFF",
INIT_47 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_48 => X"4F4F4F4F4F4F00000000000077888888CCFFFFFFFF998877004F4F4F4F4F4F4F",
INIT_49 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F00000077CCFFFFFFDD0000004F4F4F",
INIT_4A => X"EEFFFFCC0000004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_4B => X"4F00000066EEEEFFEE3300004F4F4F4F4F4F4F4F4F4F4F4F4F00000000000077",
INIT_4C => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_4D => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F1144FF99114F00004F4F4F4F4F4F4F4F4F4F",
INIT_4E => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F0000111199FFFF77004F4F4F4F4F",
INIT_4F => X"55004F00004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_50 => X"4F0000000044889944004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F0077",
INIT_51 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_52 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F00004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_53 => X"4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F00000000004F4F4F4F4F4F4F",
INIT_54 => X"0000000000000000000000004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => DOADO(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => addra(12),
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pikachu_pixel_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 3 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of pikachu_pixel_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end pikachu_pixel_blk_mem_gen_prim_width;
architecture STRUCTURE of pikachu_pixel_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.pikachu_pixel_blk_mem_gen_prim_wrapper_init
port map (
addra(12 downto 0) => addra(12 downto 0),
clka => clka,
dina(3 downto 0) => dina(3 downto 0),
douta(3 downto 0) => douta(3 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \pikachu_pixel_blk_mem_gen_prim_width__parameterized0\ is
port (
\douta[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \pikachu_pixel_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \pikachu_pixel_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \pikachu_pixel_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_init.ram\: entity work.\pikachu_pixel_blk_mem_gen_prim_wrapper_init__parameterized0\
port map (
addra(12 downto 0) => addra(12 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[11]\(7 downto 0) => \douta[11]\(7 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \pikachu_pixel_blk_mem_gen_prim_width__parameterized1\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \pikachu_pixel_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \pikachu_pixel_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \pikachu_pixel_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_init.ram\: entity work.\pikachu_pixel_blk_mem_gen_prim_wrapper_init__parameterized1\
port map (
DOADO(7 downto 0) => DOADO(7 downto 0),
addra(12 downto 0) => addra(12 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pikachu_pixel_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of pikachu_pixel_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end pikachu_pixel_blk_mem_gen_generic_cstr;
architecture STRUCTURE of pikachu_pixel_blk_mem_gen_generic_cstr is
signal \ramloop[1].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_7\ : STD_LOGIC;
begin
\has_mux_a.A\: entity work.pikachu_pixel_blk_mem_gen_mux
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(7) => \ramloop[1].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(6) => \ramloop[1].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(5) => \ramloop[1].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(4) => \ramloop[1].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(3) => \ramloop[1].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(2) => \ramloop[1].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(1) => \ramloop[1].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(0) => \ramloop[1].ram.r_n_7\,
DOADO(7) => \ramloop[2].ram.r_n_0\,
DOADO(6) => \ramloop[2].ram.r_n_1\,
DOADO(5) => \ramloop[2].ram.r_n_2\,
DOADO(4) => \ramloop[2].ram.r_n_3\,
DOADO(3) => \ramloop[2].ram.r_n_4\,
DOADO(2) => \ramloop[2].ram.r_n_5\,
DOADO(1) => \ramloop[2].ram.r_n_6\,
DOADO(0) => \ramloop[2].ram.r_n_7\,
addra(0) => addra(12),
clka => clka,
douta(7 downto 0) => douta(11 downto 4)
);
\ramloop[0].ram.r\: entity work.pikachu_pixel_blk_mem_gen_prim_width
port map (
addra(12 downto 0) => addra(12 downto 0),
clka => clka,
dina(3 downto 0) => dina(3 downto 0),
douta(3 downto 0) => douta(3 downto 0),
wea(0) => wea(0)
);
\ramloop[1].ram.r\: entity work.\pikachu_pixel_blk_mem_gen_prim_width__parameterized0\
port map (
addra(12 downto 0) => addra(12 downto 0),
clka => clka,
dina(7 downto 0) => dina(11 downto 4),
\douta[11]\(7) => \ramloop[1].ram.r_n_0\,
\douta[11]\(6) => \ramloop[1].ram.r_n_1\,
\douta[11]\(5) => \ramloop[1].ram.r_n_2\,
\douta[11]\(4) => \ramloop[1].ram.r_n_3\,
\douta[11]\(3) => \ramloop[1].ram.r_n_4\,
\douta[11]\(2) => \ramloop[1].ram.r_n_5\,
\douta[11]\(1) => \ramloop[1].ram.r_n_6\,
\douta[11]\(0) => \ramloop[1].ram.r_n_7\,
wea(0) => wea(0)
);
\ramloop[2].ram.r\: entity work.\pikachu_pixel_blk_mem_gen_prim_width__parameterized1\
port map (
DOADO(7) => \ramloop[2].ram.r_n_0\,
DOADO(6) => \ramloop[2].ram.r_n_1\,
DOADO(5) => \ramloop[2].ram.r_n_2\,
DOADO(4) => \ramloop[2].ram.r_n_3\,
DOADO(3) => \ramloop[2].ram.r_n_4\,
DOADO(2) => \ramloop[2].ram.r_n_5\,
DOADO(1) => \ramloop[2].ram.r_n_6\,
DOADO(0) => \ramloop[2].ram.r_n_7\,
addra(12 downto 0) => addra(12 downto 0),
clka => clka,
dina(7 downto 0) => dina(11 downto 4),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pikachu_pixel_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of pikachu_pixel_blk_mem_gen_top : entity is "blk_mem_gen_top";
end pikachu_pixel_blk_mem_gen_top;
architecture STRUCTURE of pikachu_pixel_blk_mem_gen_top is
begin
\valid.cstr\: entity work.pikachu_pixel_blk_mem_gen_generic_cstr
port map (
addra(12 downto 0) => addra(12 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pikachu_pixel_blk_mem_gen_v8_3_5_synth is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of pikachu_pixel_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth";
end pikachu_pixel_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of pikachu_pixel_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.pikachu_pixel_blk_mem_gen_top
port map (
addra(12 downto 0) => addra(12 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pikachu_pixel_blk_mem_gen_v8_3_5 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 12 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 11 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 11 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 12 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 12 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 13;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 13;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is "3";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 5.016775 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is "pikachu_pixel.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is "pikachu_pixel.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 6804;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 6804;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 6804;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 6804;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of pikachu_pixel_blk_mem_gen_v8_3_5 : entity is "yes";
end pikachu_pixel_blk_mem_gen_v8_3_5;
architecture STRUCTURE of pikachu_pixel_blk_mem_gen_v8_3_5 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(11) <= \<const0>\;
doutb(10) <= \<const0>\;
doutb(9) <= \<const0>\;
doutb(8) <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(12) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(12) <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.pikachu_pixel_blk_mem_gen_v8_3_5_synth
port map (
addra(12 downto 0) => addra(12 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pikachu_pixel is
port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of pikachu_pixel : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of pikachu_pixel : entity is "pikachu_pixel,blk_mem_gen_v8_3_5,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of pikachu_pixel : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of pikachu_pixel : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4";
end pikachu_pixel;
architecture STRUCTURE of pikachu_pixel is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 12 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 12 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 13;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 13;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "3";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 5.016775 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "pikachu_pixel.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "pikachu_pixel.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 6804;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 6804;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 6804;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 6804;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.pikachu_pixel_blk_mem_gen_v8_3_5
port map (
addra(12 downto 0) => addra(12 downto 0),
addrb(12 downto 0) => B"0000000000000",
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(11 downto 0) => dina(11 downto 0),
dinb(11 downto 0) => B"000000000000",
douta(11 downto 0) => douta(11 downto 0),
doutb(11 downto 0) => NLW_U0_doutb_UNCONNECTED(11 downto 0),
eccpipece => '0',
ena => '0',
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(12 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(12 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(12 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(12 downto 0),
s_axi_rdata(11 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(11 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(11 downto 0) => B"000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
| gpl-3.0 | 555c913d592a44521e193349d66c29b6 | 0.721158 | 3.178231 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/AUDIO_zpuino_wb_sid6581.vhd | 13 | 5,561 | --
-- ZPUino WB wrapper around NetSID.
--
-- Copyright 2010-2012 Alvaro Lopes - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
entity AUDIO_zpuino_wb_sid6581 is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
clk_1MHZ: in std_logic;
audio_data: out std_logic_vector(17 downto 0)
);
end entity AUDIO_zpuino_wb_sid6581;
architecture rtl of AUDIO_zpuino_wb_sid6581 is
component sid6581 is
port (
clk_1MHz : in std_logic; -- main SID clock signal
clk32 : in std_logic; -- main clock signal
clk_DAC : in std_logic; -- DAC clock signal, must be as high as possible for the best results
reset : in std_logic; -- high active signal (reset when reset = '1')
cs : in std_logic; -- "chip select", when this signal is '1' this model can be accessed
we : in std_logic; -- when '1' this model can be written to, otherwise access is considered as read
addr : in std_logic_vector(4 downto 0); -- address lines
di : in std_logic_vector(7 downto 0); -- data in (to chip)
do : out std_logic_vector(7 downto 0); -- data out (from chip)
pot_x : in std_logic; -- paddle input-X
pot_y : in std_logic; -- paddle input-Y
audio_out : out std_logic; -- this line holds the audio-signal in PWM format
audio_data : out std_logic_vector(17 downto 0)
);
end component;
signal cs: std_logic;
signal addr: std_logic_vector(4 downto 0);
signal di: std_logic_vector(7 downto 0);
signal do: std_logic_vector(7 downto 0);
signal ack_i: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
wb_dat_o(wordSize-1 downto 8) <= (others => '0');
wb_dat_o(7 downto 0) <= do;
cs <= (wb_stb_i and wb_cyc_i) and not ack_i;
di <= wb_dat_i(7 downto 0);
addr <= wb_adr_i(6 downto 2);
wb_ack_o <= ack_i;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
ack_i<='0';
else
ack_i<='0';
if ack_i='0' then
if wb_stb_i='1' and wb_cyc_i='1' then
ack_i <= '1';
end if;
end if;
end if;
end if;
end process;
sid: sid6581
port map (
clk_1MHz => clk_1MHz,
clk32 => wb_clk_i,
clk_DAC => '0',
reset => wb_rst_i,
cs => cs,
we => wb_we_i,
addr => addr,
di => di,
do => do,
pot_x => 'X',
pot_y => 'X',
audio_out => open,
audio_data => audio_data
);
end rtl;
| mit | b345f76d71e673959d0b753971fb1860 | 0.62237 | 3.449752 | false | false | false | false |
chcbaram/FPGA | ZPUino_miniSpartan6_plus/ipcore_dir/bootloader.vhd | 1 | 13,707 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity bootloader_dp_32 is
port (
CLK: in std_logic;
WEA: in std_logic;
ENA: in std_logic;
MASKA: in std_logic_vector(3 downto 0);
ADDRA: in std_logic_vector(11 downto 2);
DIA: in std_logic_vector(31 downto 0);
DOA: out std_logic_vector(31 downto 0);
WEB: in std_logic;
ENB: in std_logic;
ADDRB: in std_logic_vector(11 downto 2);
DIB: in std_logic_vector(31 downto 0);
MASKB: in std_logic_vector(3 downto 0);
DOB: out std_logic_vector(31 downto 0)
);
end entity bootloader_dp_32;
architecture behave of bootloader_dp_32 is
subtype RAM_WORD is STD_LOGIC_VECTOR (31 downto 0);
type RAM_TABLE is array (0 to 1023) of RAM_WORD;
shared variable RAM: RAM_TABLE := RAM_TABLE'(
x"0b0b0b98",x"c0040000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"0b0b0b98",x"a1040000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"71fd0608",x"72830609",x"81058205",x"832b2a83",x"ffff0652",x"04000000",x"00000000",x"00000000",x"71fd0608",x"83ffff73",x"83060981",x"05820583",x"2b2b0906",x"7383ffff",x"0b0b0b0b",x"83a70400",x"72098105",x"72057373",x"09060906",x"73097306",x"070a8106",x"53510400",x"00000000",x"00000000",x"72722473",x"732e0753",x"51040000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"71737109",x"71068106",x"30720a10",x"0a720a10",x"0a31050a",x"81065151",x"53510400",x"00000000",x"72722673",x"732e0753",x"51040000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"0b0b0b88",x"cc040000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"720a722b",x"0a535104",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"72729f06",x"0981050b",x"0b0b88af",x"05040000",x"00000000",x"00000000",x"00000000",x"00000000",x"72722aff",x"739f062a",x"0974090a",x"8106ff05",x"06075351",x"04000000",x"00000000",x"00000000",x"71715351",x"020d0406",x"73830609",x"81058205",x"832b0b2b",x"0772fc06",x"0c515104",x"00000000",x"72098105",x"72050970",x"81050906",x"0a810653",x"51040000",x"00000000",x"00000000",x"00000000",x"72098105",x"72050970",x"81050906",x"0a098106",x"53510400",x"00000000",x"00000000",x"00000000",x"71098105",x"52040000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"72720981",x"05055351",x"04000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"72097206",x"73730906",x"07535104",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"71fc0608",x"72830609",x"81058305",x"1010102a",x"81ff0652",x"04000000",x"00000000",x"00000000",x"71fc0608",x"0b0b0b9e",x"ec738306",x"10100508",x"060b0b0b",x"88b20400",x"00000000",x"00000000",x"0b0b0b89",x"80040000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"0b0b0b88",x"e8040000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"72097081",x"0509060a",x"8106ff05",x"70547106",x"73097274",x"05ff0506",x"07515151",x"04000000",x"72097081",x"0509060a",x"098106ff",x"05705471",x"06730972",x"7405ff05",x"06075151",x"51040000",x"05ff0504",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"810b0b0b",x"0b9fb40c",x"51040000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"71810552",x"04000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"02840572",x"10100552",x"04000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"717105ff",x"05715351",x"020d0400",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"81dd3f96",x"ba3f0400",x"00000000",x"00000000",x"10101010",x"10101010",x"10101010",x"10101010",x"10101010",x"10101010",x"10101010",x"10101053",x"51047381",x"ff067383",x"06098105",x"83051010",x"102b0772",x"fc060c51",x"51043c04",x"72728072",x"8106ff05",x"09720605",x"71105272",x"0a100a53",x"72ed3851",x"51535104",x"88088c08",x"90087575",x"99ed2d50",x"50880856",x"900c8c0c",x"880c5104",x"88088c08",x"90087575",x"99a92d50",x"50880856",x"900c8c0c",x"880c5104",x"88088c08",x"90088dff",x"2d900c8c",x"0c880c04",x"ff3d0d0b",x"0b0b9fc4",x"335170a6",x"389fc008",x"70085252",x"70802e92",x"3884129f",x"c00c702d",x"9fc00870",x"08525270",x"f038810b",x"0b0b0b9f",x"c434833d",x"0d040480",x"3d0d0b0b",x"0b9ff008",x"802e8e38",x"0b0b0b0b",x"800b802e",x"09810685",x"38823d0d",x"040b0b0b",x"9ff0510b",x"0b0bf5f8",x"3f823d0d",x"0404ff3d",x"0d80c480",x"80845271",x"0870822a",x"70810651",x"515170f3",x"38833d0d",x"04ff3d0d",x"80c48080",x"84527108",x"70812a70",x"81065151",x"5170f338",x"7382900a",x"0c833d0d",x"04fe3d0d",x"747080dc",x"8080880c",x"7081ff06",x"ff831154",x"51537181",x"268d3880",x"fd518aa9",x"2d72a032",x"51833972",x"518aa92d",x"843d0d04",x"803d0d83",x"ffff0b83",x"d00a0c80",x"fe518aa9",x"2d823d0d",x"04ff3d0d",x"83d00a08",x"70882a52",x"528ac92d",x"7181ff06",x"518ac92d",x"80fe518a",x"a92d833d",x"0d0482f6",x"ff0b80cc",x"8080880c",x"800b80cc",x"8080840c",x"9f0b8390",x"0a0c04ff",x"3d0d7370",x"08515180",x"c8808084",x"70087084",x"80800772",x"0c525283",x"3d0d04ff",x"3d0d80c8",x"80808470",x"0870fbff",x"ff06720c",x"5252833d",x"0d04a090",x"0ba0800c",x"9fc80ba0",x"840c98d9",x"2dff3d0d",x"73518b71",x"0c901152",x"b4808072",x"0c80720c",x"700883ff",x"ff06880c",x"833d0d04",x"fa3d0d78",x"7a7dff1e",x"57575853",x"73ff2ea7",x"38805684",x"5275730c",x"72088818",x"0cff1252",x"71f33874",x"84167408",x"720cff16",x"56565273",x"ff2e0981",x"06dd3888",x"3d0d04f8",x"3d0d80c0",x"80808457",x"83d00a59",x"8be32d76",x"518c892d",x"9fc87088",x"081010b4",x"80840571",x"70840553",x"0c5656fb",x"8084a1ad",x"750c9fa4",x"0b88170c",x"8070780c",x"770c7608",x"83ffff06",x"5683ffdf",x"800b8808",x"278338ff",x"3983ffff",x"790ca080",x"54880853",x"78527651",x"8ca82d76",x"518bc72d",x"78085574",x"762e8938",x"80c3518a",x"a92dff39",x"a0840855",x"74faa090",x"ae802e89",x"3880c251",x"8aa92dff",x"39900a70",x"0870ffbf",x"06720c56",x"568a8e2d",x"8bfa2dff",x"3d0d9fd4",x"0881119f",x"d40c5183",x"900a7008",x"70feff06",x"720c5252",x"833d0d04",x"803d0d8a",x"f82d7281",x"8007518a",x"c92d8b8d",x"2d823d0d",x"04fe3d0d",x"80c08080",x"84538be3",x"2d85730c",x"80730c72",x"087081ff",x"06745351",x"528bc72d",x"71880c84",x"3d0d04fc",x"3d0d7681",x"11338212",x"33718180",x"0a297184",x"80802905",x"83143370",x"82802912",x"84163352",x"7105a080",x"05861685",x"17335752",x"53535557",x"5553ff13",x"5372ff2e",x"91387370",x"81055533",x"52717570",x"81055734",x"e9398951",x"8e9c2d86",x"3d0d04f9",x"3d0d7957",x"80c08080",x"84568be3",x"2d811733",x"82183371",x"82802905",x"53537180",x"2e943885",x"17725553",x"72708105",x"5433760c",x"ff145473",x"f3388317",x"33841833",x"71828029",x"05565280",x"54737527",x"97387358",x"77760c73",x"17760853",x"53717334",x"81145474",x"7426ed38",x"75518bc7",x"2d8af82d",x"8184518a",x"c92d7488",x"2a518ac9",x"2d74518a",x"c92d8054",x"7375278f",x"38731770",x"3352528a",x"c92d8114",x"54ee398b",x"8d2d893d",x"0d04f93d",x"0d795680",x"c0808084",x"558be32d",x"86750c74",x"518bc72d",x"8be32d81",x"ad70760c",x"81173382",x"18337182",x"80290583",x"1933780c",x"84193378",x"0c851933",x"780c5953",x"53805473",x"7727b338",x"72587380",x"2e87388b",x"e32d7775",x"0c731686",x"1133760c",x"87113376",x"0c527451",x"8bc72d8e",x"b12d8808",x"81065271",x"f6388214",x"54767426",x"d1388be3",x"2d84750c",x"74518bc7",x"2d8af82d",x"8187518a",x"c92d8b8d",x"2d893d0d",x"04fc3d0d",x"76811133",x"82123371",x"902b7188",x"2b078314",x"33707207",x"882b8416",x"33710751",x"52535757",x"54528851",x"8e9c2d81",x"ff518aa9",x"2d80c480",x"80845372",x"0870812a",x"70810651",x"515271f3",x"38738480",x"800780c4",x"8080840c",x"863d0d04",x"fe3d0d8e",x"b12d8808",x"88088106",x"535371f3",x"388af82d",x"8183518a",x"c92d7251",x"8ac92d8b",x"8d2d843d",x"0d04fe3d",x"0d800b9f",x"d40c8af8",x"2d818151",x"8ac92d9f",x"a4538f52",x"72708105",x"5433518a",x"c92dff12",x"5271ff2e",x"098106ec",x"388b8d2d",x"843d0d04",x"fe3d0d80",x"0b9fd40c",x"8af82d81",x"82518ac9",x"2d80c080",x"8084528b",x"e32d81f9",x"0a0b80c0",x"80809c0c",x"71087252",x"538bc72d",x"729fdc0c",x"72902a51",x"8ac92d9f",x"dc08882a",x"518ac92d",x"9fdc0851",x"8ac92d8e",x"b12d8808",x"518ac92d",x"8b8d2d84",x"3d0d0480",x"3d0d810b",x"9fd80c80",x"0b83900a",x"0c85518e",x"9c2d823d",x"0d04803d",x"0d800b9f",x"d80c8bae",x"2d86518e",x"9c2d823d",x"0d04fd3d",x"0d80c080",x"8084548a",x"518e9c2d",x"8be32d9f",x"c8745253",x"8c892d72",x"88081010",x"b4808405",x"71708405",x"530c52fb",x"8084a1ad",x"720c9fa4",x"0b88140c",x"73518bc7",x"2d8a8e2d",x"8bfa2dfc",x"3d0d80c0",x"80808470",x"52558bc7",x"2d8be32d",x"8b750c76",x"80c08080",x"940c8075",x"0ca08054",x"775383d0",x"0a527451",x"8ca82d74",x"518bc72d",x"8a8e2d8b",x"fa2dffab",x"3d0d800b",x"9fd80c80",x"0b9fd40c",x"800b8dff",x"0ba0800c",x"5780c480",x"80845584",x"80b3750c",x"80c88080",x"a453fbff",x"ff730870",x"7206750c",x"535480c8",x"80809470",x"08707606",x"720c5353",x"a8709aa5",x"71708405",x"530c9b82",x"710c539c",x"9b0b8812",x"0c9daa0b",x"8c120c94",x"bb0b9012",x"0c53880b",x"80d08080",x"840c80d0",x"0a538173",x"0c8bae2d",x"8288880b",x"80dc8080",x"840c81f2",x"0b900a0c",x"80c08080",x"84705252",x"8bc72d8b",x"e32d7151",x"8bc72d8b",x"e32d8472",x"0c71518b",x"c72d7677",x"7675933d",x"41415b5b",x"5b83d00a",x"5c780870",x"81065152",x"719d389f",x"d8085372",x"f0389fd4",x"085287e8",x"7227e638",x"727e0c72",x"83900a0c",x"98d12d82",x"900a0853",x"79802e81",x"b4387280",x"fe2e0981",x"0680f438",x"76802ec1",x"38807d78",x"58565a82",x"7727ffb5",x"3883ffff",x"7c0c79fe",x"18535379",x"72279838",x"80dc8080",x"88725558",x"72157033",x"790c5281",x"13537373",x"26f238ff",x"16751154",x"7505ff05",x"70337433",x"7072882b",x"077f0853",x"51555152",x"71732e09",x"8106feed",x"38743353",x"728a26fe",x"e4387210",x"109ef805",x"75527008",x"5152712d",x"fed33972",x"80fd2e09",x"81068638",x"815bfec5",x"3976829f",x"269e387a",x"802e8738",x"8073a032",x"545b80d7",x"3d7705fd",x"e0055272",x"72348117",x"57fea239",x"805afe9d",x"397280fe",x"2e098106",x"fe933879",x"5783ffff",x"7c0c8177",x"5c5afe85",x"39803d0d",x"88088c08",x"9008a080",x"0851702d",x"900c8c0c",x"8a0c810b",x"80d00a0c",x"823d0d04",x"ff3d0d98",x"fd2d8052",x"805194f2",x"2d833d0d",x"0483ffff",x"f80d8ce3",x"0483ffff",x"f80da088",x"04000000",x"00000000",x"00000000",x"00000000",x"820b80d0",x"8080900c",x"0b0b0b04",x"0083f00a",x"0b800ba0",x"80721208",x"720c8412",x"5271712e",x"ff05f238",x"028c050d",x"98f00400",x"00000000",x"00000000",x"00000000",x"00fb3d0d",x"77795555",x"80567575",x"24ab3880",x"74249d38",x"80537352",x"745180e1",x"3f880854",x"75802e85",x"38880830",x"5473880c",x"873d0d04",x"73307681",x"325754dc",x"39743055",x"81567380",x"25d238ec",x"39fa3d0d",x"787a5755",x"80577675",x"24a43875",x"9f2c5481",x"53757432",x"74315274",x"519b3f88",x"08547680",x"2e853888",x"08305473",x"880c883d",x"0d047430",x"558157d7",x"39fc3d0d",x"76785354",x"81538074",x"73265255",x"72802e98",x"3870802e",x"a9388072",x"24a43871",x"10731075",x"72265354",x"5272ea38",x"73517883",x"38745170",x"880c863d",x"0d047281",x"2a72812a",x"53537280",x"2ee63871",x"7426ef38",x"73723175",x"74077481",x"2a74812a",x"55555654",x"e539fc3d",x"0d767079",x"7b555555",x"558f7227",x"8c387275",x"07830651",x"70802ea7",x"38ff1252",x"71ff2e98",x"38727081",x"05543374",x"70810556",x"34ff1252",x"71ff2e09",x"8106ea38",x"74880c86",x"3d0d0474",x"51727084",x"05540871",x"70840553",x"0c727084",x"05540871",x"70840553",x"0c727084",x"05540871",x"70840553",x"0c727084",x"05540871",x"70840553",x"0cf01252",x"718f26c9",x"38837227",x"95387270",x"84055408",x"71708405",x"530cfc12",x"52718326",x"ed387054",x"ff8339fc",x"3d0d7679",x"71028c05",x"9f053357",x"55535583",x"72278a38",x"74830651",x"70802ea2",x"38ff1252",x"71ff2e93",x"38737370",x"81055534",x"ff125271",x"ff2e0981",x"06ef3874",x"880c863d",x"0d047474",x"882b7507",x"7071902b",x"07515451",x"8f7227a5",x"38727170",x"8405530c",x"72717084",x"05530c72",x"71708405",x"530c7271",x"70840553",x"0cf01252",x"718f26dd",x"38837227",x"90387271",x"70840553",x"0cfc1252",x"718326f2",x"387053ff",x"9039fb3d",x"0d777970",x"72078306",x"53545270",x"93387173",x"73085456",x"54717308",x"2e80c438",x"73755452",x"71337081",x"ff065254",x"70802e9d",x"38723355",x"70752e09",x"81069538",x"81128114",x"71337081",x"ff065456",x"545270e5",x"38723355",x"7381ff06",x"7581ff06",x"71713188",x"0c525287",x"3d0d0471",x"0970f7fb",x"fdff1406",x"70f88482",x"81800651",x"51517097",x"38841484",x"16710854",x"56547175",x"082edc38",x"73755452",x"ff963980",x"0b880c87",x"3d0d04ff",x"3d0d9fe4",x"0bfc0570",x"08525270",x"ff2e9138",x"702dfc12",x"70085252",x"70ff2e09",x"8106f138",x"833d0d04",x"04eac13f",x"04000000",x"00ffffff",x"ff00ffff",x"ffff00ff",x"ffffff00",x"00000946",x"00000978",x"00000920",x"000007ab",x"000009cf",x"000009e6",x"0000083e",x"000008cd",x"00000757",x"000009fa",x"01090d00",x"007fef80",x"05b8d800",x"a4041700",x"00000000",x"00000000",x"00000000",x"00000fec",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"ffffffff",x"00000000",x"ffffffff",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000");
begin
process (clk)
begin
if rising_edge(clk) then
if ENA='1' then
if WEA='1' then
RAM(conv_integer(ADDRA) ) := DIA;
end if;
DOA <= RAM(conv_integer(ADDRA)) ;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if ENB='1' then
if WEB='1' then
RAM( conv_integer(ADDRB) ) := DIB;
end if;
DOB <= RAM(conv_integer(ADDRB)) ;
end if;
end if;
end process;
end behave;
| mit | 008ff98f34360a013ae375d1c322fc0e | 0.732764 | 1.966289 | false | false | false | false |
bsmerbeckuri/SHA512Optimization | CPU_System/Rhody_CPU_pipelinev2.vhd | 1 | 27,076 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Rhody_CPU_pipelinev2 is
port ( clk : in std_logic;
rst : in std_logic;
MEM_ADR : out std_logic_vector(31 downto 0);
MEM_IN : in std_logic_vector(31 downto 0);
MEM_OUT : out std_logic_vector(31 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
key : in std_logic;
LEDR : out std_logic_vector(3 downto 0)
);
end;
architecture Structural of Rhody_CPU_pipelinev2 is
-- state machine: CPU_state
type State_type is (S1, S2);
signal update, stage1, stage2, stage3, stage4: State_type;
-- Register File: 8x32
type reg_file_type is array (0 to 7) of std_logic_vector(31 downto 0);
signal register_file : reg_file_type;
-- Internal registers
signal MDR_in, MDR_out, MAR, PSW: std_logic_vector(31 downto 0);
signal PC, SP: unsigned(31 downto 0); --unsigned for arithemtic operations
-- Internal control signals
signal operand0, operand1, ALU_out : std_logic_vector(31 downto 0);
signal carry, overflow, zero : std_logic;
-- Pipeline Istruction registers
signal stall: Boolean;
signal IR2, IR3, IR4: std_logic_vector(31 downto 0);
--Rhody Instruction Format
alias Opcode2: std_logic_vector(5 downto 0) is IR2(31 downto 26);
alias Opcode3: std_logic_vector(5 downto 0) is IR3(31 downto 26);
alias Opcode4: std_logic_vector(5 downto 0) is IR4(31 downto 26);
alias RX2 : std_logic_vector(2 downto 0) is IR2(25 downto 23);
alias RX3 : std_logic_vector(2 downto 0) is IR3(25 downto 23);
alias RY2 : std_logic_vector(2 downto 0) is IR2(22 downto 20);
alias RZ2 : std_logic_vector(2 downto 0) is IR2(19 downto 17);
alias RA2 : std_logic_vector(2 downto 0) is IR2(16 downto 14);
alias RB2 : std_logic_vector(2 downto 0) is IR2(13 downto 11);
alias RB3 : std_logic_vector(2 downto 0) is IR2(13 downto 11);
alias RC2 : std_logic_vector(2 downto 0) is IR2(10 downto 8);
alias RC3 : std_logic_vector(2 downto 0) is IR2(10 downto 8);
alias RD2 : std_logic_vector(2 downto 0) is IR2(7 downto 5);
alias RE2 : std_logic_vector(2 downto 0) is IR2(4 downto 2);
alias I2 : std_logic_vector(15 downto 0) is IR2(15 downto 0);
alias M2 : std_logic_vector(19 downto 0) is IR2(19 downto 0);
alias M3 : std_logic_vector(19 downto 0) is IR3(19 downto 0);
-- Temporary control signals
signal tmp1, tmp2, tmp3: unsigned(63 downto 0);
signal tmpx, tmpy, tmpz, tmpa: std_logic_vector(31 downto 0);
--Condition Codes
alias Z: std_logic is PSW(0);
alias C: std_logic is PSW(1);
alias S: std_logic is PSW(2);
alias V: std_logic is PSW(3);
--Instruction Opcodes
constant NOP : std_logic_vector(5 downto 0) := "000000";
constant LDM : std_logic_vector(5 downto 0) := "000100";
constant LDR : std_logic_vector(5 downto 0) := "000101";
constant LDH : std_logic_vector(5 downto 0) := "001000";
constant LDL : std_logic_vector(5 downto 0) := "001001";
constant LDI : std_logic_vector(5 downto 0) := "001010";
constant MOV : std_logic_vector(5 downto 0) := "001011";
constant STM : std_logic_vector(5 downto 0) := "001100";
constant STR : std_logic_vector(5 downto 0) := "001101";
constant ADD : std_logic_vector(5 downto 0) := "010000";
constant ADI : std_logic_vector(5 downto 0) := "010001";
constant SUB : std_logic_vector(5 downto 0) := "010010";
constant MUL : std_logic_vector(5 downto 0) := "010011";
constant IAND : std_logic_vector(5 downto 0) := "010100"; --avoid keyword
constant IOR : std_logic_vector(5 downto 0) := "010101"; --avoid keyword
constant IXOR : std_logic_vector(5 downto 0) := "010110"; --avoid keyword
constant IROR : std_logic_vector(5 downto 0) := "010111"; --avoid keyword
constant CMP : std_logic_vector(5 downto 0) := "101010";
constant CMPI : std_logic_vector(5 downto 0) := "110010";
constant JNZ : std_logic_vector(5 downto 0) := "100000";
constant JNS : std_logic_vector(5 downto 0) := "100001";
constant JNC : std_logic_vector(5 downto 0) := "100011";
constant JNV : std_logic_vector(5 downto 0) := "100010";
constant JZ : std_logic_vector(5 downto 0) := "100100";
constant JS : std_logic_vector(5 downto 0) := "100101";
constant JC : std_logic_vector(5 downto 0) := "100111";
constant JV : std_logic_vector(5 downto 0) := "100110";
constant JMP : std_logic_vector(5 downto 0) := "101000";
constant CALL : std_logic_vector(5 downto 0) := "110000";
constant RET : std_logic_vector(5 downto 0) := "110100";
constant RETI : std_logic_vector(5 downto 0) := "110101";
constant PUSH : std_logic_vector(5 downto 0) := "111000";
constant POP : std_logic_vector(5 downto 0) := "111001";
constant SYS : std_logic_vector(5 downto 0) := "111100";
constant CH : std_logic_vector(5 downto 0) := "011001";
--constant MAJ : std_logic_vector(5 downto 0) := "011010";
--constant SUM0 : std_logic_vector(5 downto 0) := "011011";
constant SUM1 : std_logic_vector(5 downto 0) := "111101";
constant SIG0 : std_logic_vector(5 downto 0) := "111110";
constant SIG1 : std_logic_vector(5 downto 0) := "111111";
constant ADD64: std_logic_vector(5 downto 0) := "000001";
constant LDIX : std_logic_vector(5 downto 0) := "000110";
constant STIX : std_logic_vector(5 downto 0) := "000111";
constant T2 : std_logic_vector(5 downto 0) := "000010";
constant T11 : std_logic_vector(5 downto 0) := "101110";
constant T12 : std_logic_vector(5 downto 0) := "101111";
constant STIX64: std_logic_vector(5 downto 0) := "110001";
begin
--Display condition code on LEDR for debugging purpose
LEDR(3) <= Z when key='0' else '0';
LEDR(2) <= C when key='0' else '0';
LEDR(1) <= S when key='0' else '0';
LEDR(0) <= V when key='0' else '0';
--CPU bus interface
MEM_OUT <= MDR_out; --Outgoing data bus
MEM_ADR <= MAR; --Address bus
--One clock cycle delay in obtaining CPU_state, e.g. S1->S2
mem_rd <= '1' when ((Opcode2=LDM or Opcode2=LDR or Opcode2 = LDIX) and stage2=S2) else
'1' when (stage1=S2 and not stall) else
'1' when ((Opcode2=POP or Opcode2=RET) and stage2=S2) else
'1' when (Opcode2=RETI and stage2=S2) else
'1' when (Opcode3=RETI and stage3=S2) else
'0'; --Memory read control signal
mem_wr <= '1' when ((Opcode3=STM or Opcode3=STR or Opcode3=STIX or Opcode3 = STIX64) and stage3=S1) else
'1' when ((Opcode3=PUSH or Opcode3=CALL) and stage3=S2) else
'1' when (Opcode3=SYS and stage3=S2) else
--'1' when (Opcode4=SYS and stage4=S2) else
'0'; --Memory write control signal
stall <= true when(Opcode2=LDM or Opcode2=LDR or Opcode2 = LDIX or Opcode2=STM or Opcode2=STR or Opcode2=STIX or Opcode2 = STIX64) else
true when(Opcode2=JMP or Opcode2=JNZ or Opcode2=JNS or Opcode2=JNC
or Opcode2=JNV or Opcode2=JZ or Opcode2=JS
or Opcode2=JC or Opcode2=JV) else
true when(Opcode2=CALL or Opcode2=PUSH or Opcode2=POP or Opcode2=RET
or Opcode2=SYS or Opcode2=RETI) else
true when(Opcode3=CALL or Opcode3=RET or Opcode3=PUSH
or Opcode3=SYS or Opcode3=RETI) else
--true when(Opcode4=SYS or Opcode4=RETI) else
false;
--The state machine that is CPU
CPU_State_Machine: process (clk, rst)
begin
if rst='1' then
update <= S1;
stage1 <= S1;
stage2 <= S1;
stage3 <= S1;
stage4 <= S1;
PC <= x"00000000"; --initialize PC
SP <= x"000FF7FF"; --initialize SP
IR2 <= x"00000000";
IR3 <= x"00000000";
IR4 <= x"00000000";
elsif clk'event and clk = '1' then
case update is
when S1 =>
update <= S2;
when S2 =>
if (stall) then
IR2 <= x"00000000"; --insert NOP
else
IR2 <= MEM_in;
end if;
IR3 <= IR2;
IR4 <= IR3;
update <= S1;
when others =>
null;
end case;
case stage1 is
when S1 =>
if (not stall) then
MAR <= std_logic_vector(PC);
end if;
stage1 <= S2;
when S2 =>
if (not stall) then
PC <= PC + 1;
end if;
stage1 <= S1;
when others =>
null;
end case;
case stage2 is
when S1 =>
if (Opcode2=LDI) then
register_file(to_integer(unsigned(RX2)))<=(31 downto 16=>I2(15)) & I2;
elsif (Opcode2=LDH) then
register_file(to_integer(unsigned(RX2)))
<= I2 & register_file(to_integer(unsigned(RX2)))(15 downto 0);
--(31 downto 16)<= I2;
elsif (Opcode2=LDL) then
register_file(to_integer(unsigned(RX2)))
<= register_file(to_integer(unsigned(RX2)))(31 downto 16) & I2;
--(15 downto 0)<= I2;
elsif (Opcode2=MOV) then
register_file(to_integer(unsigned(RX2)))<=register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=ADD or Opcode2=SUB or Opcode2=MUL or Opcode2=CMP or
Opcode2=IAND or Opcode2=IOR or Opcode2=IXOR) then
operand1 <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=IROR) then
null;
elsif (Opcode2=ADI or Opcode2=CMPI) then
operand1 <= (31 downto 16=>I2(15)) & I2;
elsif (Opcode2=LDM) then
MAR <= x"000" & M2;
elsif (Opcode2=LDR) then
MAR <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=LDIX) then
MAR <= std_logic_vector(unsigned(
register_file(to_integer(unsigned(RY2))))
+ unsigned(M2));
elsif (Opcode2=STM) then
MAR <= x"000" & M2; MDR_out <= register_file(to_integer(unsigned(RX2)));
elsif (Opcode2=STR) then
MAR <= register_file(to_integer(unsigned(RX2)));
MDR_out <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=STIX) then
MAR <= std_logic_vector(unsigned(
register_file(to_integer(unsigned(RX2))))
+ unsigned(M2));
MDR_out <=
register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=STIX64) then
MAR <= std_logic_vector(unsigned(
register_file(to_integer(unsigned(RX2))))
+ unsigned(M2));
MDR_out <=
register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=JMP or
(Opcode2=JNZ and Z='0') or (Opcode2=JZ and Z='1') or
(Opcode2=JNS and S='0') or (Opcode2=JS and S='1') or
(Opcode2=JNV and V='0') or (Opcode2=JV and V='1') or
(Opcode2=JNC and C='0') or (Opcode2=JC and C='1') ) then
PC <= x"000" & unsigned(M2);
elsif (Opcode2=CALL or Opcode2=PUSH or Opcode2=SYS) then
SP <= SP + 1;
elsif (Opcode2=RET or Opcode2=RETI or Opcode2=POP) then
MAR <= std_logic_vector(SP);
elsif (Opcode2=CH) then
-- register_file(to_integer(unsigned(RX2))) <=
-- (register_file(to_integer(unsigned(RX2))) and register_file(to_integer(unsigned(RZ2))))xor
-- (not register_file(to_integer(unsigned(RX2))) and register_file(to_integer(unsigned(RB2))));
-- register_file(to_integer(unsigned(RY2))) <=
-- (register_file(to_integer(unsigned(RY2))) and register_file(to_integer(unsigned(RA2))))xor
-- (not register_file(to_integer(unsigned(RY2))) and register_file(to_integer(unsigned(RC2))));
register_file(to_integer(unsigned(RX2))) <=
std_logic_vector(((register_file(to_integer(unsigned(RB2)))& register_file(to_integer(unsigned(RC2)))) xor ((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and ((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) xor (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2))))))))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <=
std_logic_vector(((register_file(to_integer(unsigned(RB2)))& register_file(to_integer(unsigned(RC2)))) xor ((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and ((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) xor (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2))))))))(31 downto 0);
-- elsif (Opcode2=MAJ) then
--
---- (register_file(to_integer(unsigned(RX2))) and register_file(to_integer(unsigned(RZ2))))xor
---- (register_file(to_integer(unsigned(RX2))) and register_file(to_integer(unsigned(RB2))))xor
---- (register_file(to_integer(unsigned(RZ2))) and register_file(to_integer(unsigned(RB2))));
---- register_file(to_integer(unsigned(RY2))) <=
---- (register_file(to_integer(unsigned(RY2))) and register_file(to_integer(unsigned(RA2))))xor
---- (register_file(to_integer(unsigned(RY2))) and register_file(to_integer(unsigned(RC2))))xor
---- (register_file(to_integer(unsigned(RA2))) and register_file(to_integer(unsigned(RC2))));
-- register_file(to_integer(unsigned(RX2))) <=
-- std_logic_vector(((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))))xor
-- ((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))xor
-- ((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2))))))(63 downto 32);
-- register_file(to_integer(unsigned(RY2))) <=
-- std_logic_vector(((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))))xor
-- ((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))xor
-- ((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2))))))(31 downto 0);
-- elsif (Opcode2=SUM0) then
-- register_file(to_integer(unsigned(RX2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),28)) xor
-- std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),34)) xor
-- std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),39)))(63 downto 32);
-- register_file(to_integer(unsigned(RY2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),28)) xor
-- std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),34)) xor
-- std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),39)))(31 downto 0);
elsif (Opcode2=SUM1) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),14)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),18)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),41)))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),14)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),18)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),41)))(31 downto 0);
elsif (Opcode2=SIG0) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),1)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),8)) xor
std_logic_vector(shift_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),7)))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),1)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),8)) xor
std_logic_vector(shift_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),7)))(31 downto 0);
elsif (Opcode2=SIG1) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),19)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),61)) xor
std_logic_vector(shift_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),6)))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),19)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),61)) xor
std_logic_vector(shift_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),6)))(31 downto 0);
elsif (Opcode2 = ADD64) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector((unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2))))) + (unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2))))))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector((unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2))))) + (unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2))))))(31 downto 0);
elsif (Opcode2 = T11) then
register_file(to_integer(unsigned(RX2))) <=
std_logic_vector(unsigned(((register_file(to_integer(unsigned(RB2)))& register_file(to_integer(unsigned(RC2)))) xor ((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and ((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) xor (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))))) +
unsigned(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),14)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),18)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),41)))
+ (unsigned(register_file(to_integer(unsigned(RD2)))) & unsigned(register_file(to_integer(unsigned(RE2)))) + 0))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <=
std_logic_vector(unsigned(((register_file(to_integer(unsigned(RB2)))& register_file(to_integer(unsigned(RC2)))) xor ((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and ((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) xor (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))))) +
unsigned(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),14)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),18)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),41)))
+ (unsigned(register_file(to_integer(unsigned(RD2)))) & unsigned(register_file(to_integer(unsigned(RE2)))) + 0))(31 downto 0);
tmpx <= std_logic_vector(register_file(to_integer(unsigned(RX2))));
tmpy <= std_logic_vector(register_file(to_integer(unsigned(RY2))));
elsif (Opcode2 = T12) then
register_file(to_integer(unsigned(RX2))) <=
std_logic_vector((unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2))))) +
(unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2))))) +
(unsigned(register_file(to_integer(unsigned(RB2)))) & unsigned(register_file(to_integer(unsigned(RC2))))))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <=
std_logic_vector((unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2))))) +
(unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2))))) +
(unsigned(register_file(to_integer(unsigned(RB2)))) & unsigned(register_file(to_integer(unsigned(RC2))))))(31 downto 0);
elsif (Opcode2 = T2) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector((unsigned(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),28)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),34)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),39))) +
unsigned(((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))))xor
((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))xor
((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2))))))))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector((unsigned(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),28)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),34)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),39))) +
unsigned(((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))))xor
((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))xor
((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2))))))))(31 downto 0);
end if;
stage2 <= S2;
when S2 =>
if (Opcode2=ADD or Opcode2=SUB or Opcode2=IROR or Opcode2=IAND or
Opcode2=MUL or Opcode2=IOR or Opcode2=IXOR or Opcode2=ADI) then
register_file(to_integer(unsigned(RX2))) <= ALU_out;
Z <= zero; S <= ALU_out(31); V <= overflow; C <= carry; --update CC
elsif (Opcode2=CMP or Opcode2=CMPI) then
Z <= zero; S <= ALU_out(31); V <= overflow; C <= carry; --update CC only
elsif (Opcode2=LDM or Opcode2=LDR or Opcode2=LDIX) then
MDR_in <= MEM_in;
elsif (Opcode2=STM or Opcode2=STR or Opcode2=STIX) then
null;
elsif (Opcode2=CALL or Opcode2=SYS) then
MAR <= std_logic_vector(SP);
MDR_out <= std_logic_vector(PC);
elsif (Opcode2=RET or Opcode2=RETI or Opcode2=POP) then
MDR_in <= MEM_IN; SP <= SP - 1;
elsif (Opcode2=PUSH) then
MAR <= std_logic_vector(SP);
MDR_out <= register_file(to_integer(unsigned(RX2)));
elsif (Opcode2 = T11) then
register_file(to_integer(unsigned(RD2))) <= std_logic_vector(tmpx);
register_file(to_integer(unsigned(RE2))) <= std_logic_vector(tmpy);
elsif (Opcode2=STIX64) then
MAR <= std_logic_vector(unsigned(
register_file(to_integer(unsigned(RX2))))
+ (unsigned(M2)+1)); MDR_out <= register_file(to_integer(unsigned(RZ2)));
end if;
stage2 <= S1;
when others =>
null;
end case;
case stage3 is
when S1 =>
if (Opcode3=LDM or Opcode3=LDR or Opcode3=LDIX) then
register_file(to_integer(unsigned(RX3))) <= MDR_in;
elsif (Opcode3=STM or Opcode3=STR or Opcode3=STIX or Opcode3=STIX64) then
null;
elsif (Opcode3=CALL) then
PC <= x"000" & unsigned(M3);
elsif (Opcode3=POP) then
register_file(to_integer(unsigned(RX3))) <= MDR_in;
elsif (Opcode3=RET) then
PC <= unsigned(MDR_in);
elsif (Opcode3=RETI) then
PSW <= MDR_in; MAR <= std_logic_vector(SP);
elsif (Opcode3=PUSH) then
null;
elsif (Opcode3=SYS) then
SP <= SP + 1;
end if;
stage3 <= S2;
when S2 =>
if (Opcode3=RETI) then
MDR_in <= MEM_IN; sp <= sp - 1;
elsif (Opcode3=SYS) then
MAR <= std_logic_vector(SP);
MDR_out <= PSW;
PC <= X"000FFC0"&unsigned(IR4(3 downto 0));
end if;
stage3 <= S1;
when others =>
null;
end case;
-- case stage4 is
-- when S1 =>
-- if (Opcode4=RETI) then
-- PC <= unsigned(MDR_in);
-- elsif (Opcode4=SYS) then
-- PC <= X"000FFC0"&unsigned(IR4(3 downto 0));
-- else stage4 <= S2;
-- end if;
-- stage4 <= S2;
-- when S2 =>
-- stage4 <= S1;
-- when others =>
-- null;
-- end case;
end if;
end process;
--------------------ALU----------------------------
Rhody_ALU: entity work.alu port map(
alu_op => IR2(28 downto 26),
operand0 => operand0,
operand1 => operand1,
n => IR2(4 downto 0),
alu_out => ALU_out,
carry => carry,
overflow => overflow);
zero <= '1' when alu_out = X"00000000" else '0';
operand0 <= register_file(to_integer(unsigned(RX2)));
-----------------------------------------------------
end Structural;
| gpl-3.0 | 24613b5e4bcabee16c1adbe65eed96f5 | 0.674398 | 2.957833 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/BENCHY_zpuino_wb_waveform_generator.vhd | 13 | 7,433 | ----------------------------------------------------------------------------------
-- Company: Gadget Factory
-- Engineer: Alvaro Lopes
--
-- Create Date: 13:56:50 12/10/2013
-- Design Name:
-- Module Name: TEMPLATE_zpuino_wb_Wishbone - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- This is an example template to use for your own Wishbone Peripherals.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
-- This example uses asynchronous outputs.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity BENCHY_zpuino_wb_waveform_generator is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
clk_in : in STD_LOGIC;
sin_out : OUT std_logic_vector(11 downto 0);
cos_out : OUT std_logic_vector(11 downto 0);
--squ_out : OUT std_logic_vector(11 downto 0);
saw_out : OUT std_logic_vector(11 downto 0);
sin_dac_out : OUT std_logic;
cos_dac_out : OUT std_logic;
squ_dac_out : OUT std_logic;
saw_dac_out : OUT std_logic
--all_dac_out : OUT std_logic
);
end entity BENCHY_zpuino_wb_waveform_generator;
architecture rtl of BENCHY_zpuino_wb_waveform_generator is
COMPONENT waveform_gen
PORT(
clk : IN std_logic;
reset : IN std_logic;
phase_inc : IN std_logic_vector(31 downto 0);
sin_out : OUT std_logic_vector(11 downto 0);
cos_out : OUT std_logic_vector(11 downto 0);
squ_out : OUT std_logic_vector(11 downto 0);
saw_out : OUT std_logic_vector(11 downto 0)
);
END COMPONENT;
COMPONENT AUDIO_zpuino_sa_sigmadeltaDAC
generic (
BITS: integer := 12
);
port (
clk_96Mhz: in std_logic;
--rst: in std_logic;
data_in: in std_logic_vector(BITS-1 downto 0);
audio_out: out std_logic
);
end COMPONENT;
--Define your registers here
signal phase_inc_r : std_logic_vector(31 downto 0) := x"028c1980"; --x"028c1980" should give an output of 1Mhz. Wofram Alpha: x=10,y=(x*2^32)/(100 + .5)
-- signal waveform_sel: std_logic_vector(7 downto 0) := "00000010"; --Default to sine wave output
signal dac_in_s: std_logic_vector(11 downto 0);
signal sin_out_s: std_logic_vector(11 downto 0);
signal cos_out_s: std_logic_vector(11 downto 0);
signal squ_out_s: std_logic_vector(11 downto 0);
signal saw_out_s: std_logic_vector(11 downto 0);
-- signal register0: std_logic_vector(31 downto 0); -- Register 0 (32 bits)
-- signal register1: std_logic_vector(31 downto 0); -- Register 1 (32 bits)
-- signal register2: std_logic_vector(7 downto 0); -- Register 2 (8 bits)
--signal nReset : std_logic;
--Wishbone signals - Don't touch.
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- End unpacking Wishbone signals
--nReset <= not wb_rst_i;
-- Asynchronous acknowledge
wb_ack_o <= '1' when wb_cyc_i='1' and wb_stb_i='1' else '0';
-- Multiplex the data output (asynchronous)
process(phase_inc_r, wb_adr_i)
begin
-- Multiplex the read depending on the address. Use only the 2 lowest bits of addr
case wb_adr_i(3 downto 2) is
when "00" =>
wb_dat_o <= phase_inc_r; -- Output register0
-- when "01" =>
-- wb_dat_o(31 downto 0) <= (others => '0'); -- We put all upper 24 bits to zero
-- wb_dat_o(7 downto 0) <= waveform_sel; -- since register1 only has 8 bits
-- when "10" =>
-- wb_dat_o(31 downto 0) <= (others => '0'); -- We put all upper 24 bits to zero
-- wb_dat_o(7 downto 0) <= register2; -- since register2 only has 8 bits
when others =>
wb_dat_o <= (others => 'X'); -- Return undefined for all other addresses
end case;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock
if wb_rst_i='1' then
-- Reset request, put register1 and register2 with zeroes,
-- put register 3 with binary 10101010b
phase_inc_r <= (others => '0');
--waveform_sel <= (others => '0');
-- register2 <= "10101010";
else -- Not reset
-- Check if someone is writing
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
-- Yes, it's a write. See for which register based on address
case wb_adr_i(3 downto 2) is
when "00" =>
phase_inc_r <= wb_dat_i; -- Set register0
-- when "01" =>
-- waveform_sel <= wb_dat_i(7 downto 0); -- Set register1
-- when "10" =>
-- register2 <= wb_dat_i(7 downto 0); -- Only lower 8 bits for register2
when others =>
null; -- Nothing to do for other addresses
end case;
end if;
end if;
end if;
end process;
sin_out <= sin_out_s;
cos_out <= cos_out_s;
--squ_out <= squ_out_s;
saw_out <= saw_out_s;
Inst_waveform_gen: waveform_gen PORT MAP(
clk => wb_clk_i,
reset => '1',
phase_inc => phase_inc_r,
sin_out => sin_out_s,
cos_out => cos_out_s,
squ_out => squ_out_s,
saw_out => saw_out_s
);
Inst_dac1: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => sin_dac_out,
data_in => sin_out_s,
clk_96Mhz => clk_in
);
Inst_dac2: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => cos_dac_out,
data_in => cos_out_s,
clk_96Mhz => clk_in
);
Inst_dac3: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => squ_dac_out,
data_in => squ_out_s,
clk_96Mhz => clk_in
);
Inst_dac4: AUDIO_zpuino_sa_sigmadeltaDAC
generic MAP (
BITS => 12
)
PORT MAP(
audio_out => saw_dac_out,
data_in => saw_out_s,
clk_96Mhz => clk_in
);
-- process (waveform_sel,sin_out_s,cos_out_s,squ_out_s,saw_out_s)
-- begin
-- case waveform_sel(1 downto 0) is
-- when "00" => dac_in_s <= sin_out_s;
-- when "01" => dac_in_s <= cos_out_s;
-- when "10" => dac_in_s <= squ_out_s;
-- when "11" => dac_in_s <= saw_out_s;
-- when others => dac_in_s <= squ_out_s;
-- end case;
-- end process;
end rtl;
| mit | 027df4676da19777546c76ddf52c33a2 | 0.591148 | 3.009312 | false | false | false | false |
sinkswim/DLX-Pro | DLX_simulation_cfg/a.b-DataPath.core/a.b.b-decode.vhd | 1 | 9,155 | --------------------------------------------------------------------------------
-- Decode Unit
-- This unit implements the decode unit. Sub-units which are contained are:
-- - Hazard Detection Unit
-- - Register File
-- - Sign-Extension
-- - Extender
-- - Mux Stall
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.globals.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity decode_unit is
port (
-- INPUTS
address_write : in std_logic_vector(4 downto 0); -- register address that should be written
data_write : in std_logic_vector(31 downto 0); -- data to be written in the reg file
pc_4_from_dec : in std_logic_vector(31 downto 0); -- Program counter incremented by 4
instruction : in std_logic_vector(31 downto 0); -- instruction fetched
idex_rt : in std_logic_vector(4 downto 0); -- Rt register coming from the ex stage
clk : in std_logic; -- global clock
rst : in std_logic; -- global reset signal
reg_write : in std_logic; -- Reg Write signal to enable the write operation
idex_mem_read : in std_logic_vector(3 downto 0); -- control signals for Mem Read (lb,lhu, lw, lbu)
cw : in std_logic_vector((CW_SIZE+ALUOP_SIZE)-1 downto 0); -- control word + alu operation produced by the CU
-- OUTPUTS
cw_to_ex : out std_logic_vector((CW_SIZE+ALUOP_SIZE)-2 downto 0); -- control word + alu operation for the ex stage (-2 since unsigned control signal used i the decode stage)
jump_address : out std_logic_vector(31 downto 0); -- jump address sign-extended
pc_4_to_ex : out std_logic_vector(31 downto 0); -- Program counter incremented by 4 directed to the ex stage
data_read_1 : out std_logic_vector(31 downto 0); -- Output of read port 1 of reg file
data_read_2 : out std_logic_vector(31 downto 0); -- Output of read port 2 of reg file
immediate_ext : out std_logic_vector(31 downto 0); -- Immediate field signe-exntended
immediate : out std_logic_vector(15 downto 0); -- Immediate filed not sign extended (for LUI instruction)
rt : out std_logic_Vector(4 downto 0); -- rt address (instruction 20-16)
rd : out std_logic_vector(4 downto 0); -- rd address (instruction 15-11)
rs : out std_logic_vector(4 downto 0); -- rs address (instruction 25-21)
opcode : out std_logic_vector(OPCODE_SIZE-1 downto 0); -- opcode for the CU, instruction (31-26)
func : out std_logic_vector(FUNC_SIZE-1 downto 0); -- func field of instruction (10-0) to the CU
pcwrite : out std_logic; -- write enable generated by the Hazard Detection Unit for the PC
ifid_write : out std_logic -- write enable generated by the Hazard Detection Unit for the IF/ID pipeline register
);
end decode_unit;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
architecture structural of decode_unit is
-- Component Declarations
component reg_file is
port (
-- INPUTS
read_address_1 : in std_logic_vector(4 downto 0); -- address of reg 1 to be read(instruction 25-21)
read_address_2 : in std_logic_vector(4 downto 0); -- address of reg 2 to be read(instruction 20-16)
write_address : in std_logic_vector(4 downto 0); -- address of reg to be written
write_data : in std_logic_vector(31 downto 0); -- data to be written at the address specified in wirte_address
reg_write : in std_logic;
rst : in std_logic;
-- OUTPUTS
data_reg_1 : out std_logic_vector(31 downto 0); -- data from read port 1
data_reg_2 : out std_logic_vector(31 downto 0) -- data from read port 2
);
end component;
component extender is
port (
-- INPUTS
immediate : in std_logic_vector(15 downto 0); -- immediate filed (instruction 15 -0)
unsigned_value : in std_logic; -- control signal generated by the CU
-- OUTPUTS
extended : out std_logic_vector(31 downto 0) -- extended value
);
end component;
component sign_extender is
port (
-- INPUTS
immediate_jump : in std_logic_vector(25 downto 0); -- instructon (25-0)
-- OUTPUTS
extended_jump : out std_logic_vector(31 downto 0) -- sign-extended jump immediate
);
end component;
component mux_stall is
port (
-- INPUTS
cw_from_cu : in std_logic_vector((CW_SIZE + ALUOP_SIZE)-1 downto 0); -- control word produced by the CU
mux_op : in std_logic; -- control signal produced by the hazard detection unit
-- OUTPUTS
cw_from_mux : out std_logic_vector((CW_SIZE+ALUOP_SIZE)-1 downto 0) -- control word produced by the mux
);
end component;
component hdu is
port (
-- INPUTS
clk : in std_logic; -- global clock signal
rst : in std_logic; -- global reset signal
idex_mem_read : in std_logic_vector(3 downto 0); -- ID/EX MemRead control signals (lbu, lw, lhu, lb)
idex_rt : in std_logic_vector(4 downto 0); -- ID/EX Rt address
rs : in std_logic_vector(4 downto 0); -- Rs address instruction (25-21)
rt : in std_logic_vector(4 downto 0); -- Rt address instruction (20-16)
-- OUTPUTS
pcwrite : out std_logic; -- control signal write enable for the PC register
ifidwrite : out std_logic; -- control signal write enable for the pipeline register IF/ID
mux_op : out std_logic -- control signal directed to the mux stall
);
end component;
-- Internal Signals
signal unsigned_value_i : std_logic;
signal cw_i : std_logic_vector((CW_SIZE+ALUOP_SIZE)-1 downto 0);
signal mux_op_i : std_logic;
begin
-- Cuncurrent statements
-- Extract from the control word the unsigned control signal and re-arrenge the Cw itself
cw_to_ex <= cw_i((CW_SIZE+ALUOP_SIZE)-1) & cw_i((CW_SIZE+ALUOP_SIZE)-3 downto 0);
unsigned_value_i <= cw_i((CW_SIZE+ALUOP_SIZE)-2);
-- Output assignmet
opcode <= instruction(31 downto 26);
func <= instruction(10 downto 0);
pc_4_to_ex <= pc_4_from_dec;
immediate <= instruction(15 downto 0);
rt <= instruction(20 downto 16);
rd <= instruction(15 downto 11);
rs <= instruction(25 downto 21);
-- Components instantiation
hdu_0: hdu port map (
clk => clk,
rst => rst,
idex_mem_read => idex_mem_read,
idex_rt => idex_rt,
rs => instruction(25 downto 21),
rt => instruction(20 downto 16),
pcwrite => pcwrite,
ifidwrite => ifid_write,
mux_op => mux_op_i
);
mux_stall0: mux_stall port map(
cw_from_cu => cw,
mux_op => mux_op_i,
cw_from_mux => cw_i
);
sign_extender0: sign_extender port map(
immediate_jump => instruction(25 downto 0),
extended_jump => jump_address
);
extender0: extender port map (
immediate => instruction(15 downto 0),
unsigned_value => unsigned_value_i,
extended => immediate_ext
);
reg_file0: reg_file port map (
read_address_1 => instruction(25 downto 21),
read_address_2 => instruction(20 downto 16),
write_address => address_write,
write_data => data_write,
reg_write => reg_write,
rst => rst,
data_reg_1 => data_read_1,
data_reg_2 => data_read_2
);
end structural;
| mit | a58d4df9887b447268233dc1a1b74214 | 0.493829 | 4.414176 | false | false | false | false |
algebrato/eldig | Cont_4_cfr/Cont_4_cfr.vhd | 1 | 2,407 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:01:12 05/08/2015
-- Design Name:
-- Module Name: Contatore_4_cifre - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Contatore_4_cifre is
PORT (Clock_in, Enable, Reset, Preset, UpDown : in std_logic;
N0_preset, N1_preset, N2_preset, N3_preset : in std_logic_vector(3 downto 0);
N0, N1, N2, N3 : out std_logic_vector(3 downto 0));
end Contatore_4_cifre;
architecture V1 of Contatore_4_cifre is
signal enable_0_to_1, enable_1_to_2, enable_2_to_3 : std_logic;
COMPONENT Contatore_1_cifra
PORT(
Clock : IN std_logic;
Enable_in : IN std_logic;
UpDown : IN std_logic;
Reset : IN std_logic;
Preset : IN std_logic;
N_preset : IN std_logic_vector(3 downto 0);
N : OUT std_logic_vector(3 downto 0);
Enable_out : OUT std_logic
);
END COMPONENT;
begin
A_Inst_Contatore_1_cifra: Contatore_1_cifra PORT MAP(
Clock => Clock_in,
Enable_in => Enable,
UpDown => UpDown,
Reset => Reset,
Preset => Preset,
N_preset => N0_preset,
N => N0,
Enable_out => enable_0_to_1);
B_Inst_Contatore_1_cifra: Contatore_1_cifra PORT MAP(
Clock => Clock_in,
Enable_in => enable_0_to_1,
UpDown => UpDown,
Reset => Reset,
Preset => Preset,
N_preset => N1_preset,
N => N1,
Enable_out => enable_1_to_2);
C_Inst_Contatore_1_cifra: Contatore_1_cifra PORT MAP(
Clock => Clock_in,
Enable_in => enable_1_to_2,
UpDown => UpDown,
Reset => Reset,
Preset => Preset,
N_preset => N2_preset,
N => N2,
Enable_out => enable_2_to_3);
D_Inst_Contatore_1_cifra: Contatore_1_cifra PORT MAP(
Clock => Clock_in,
Enable_in => enable_2_to_3,
UpDown => UpDown,
Reset => Reset,
Preset => Preset,
N_preset => N3_preset,
N => N3,
Enable_out => open);
end V1; | gpl-3.0 | 1ed862441a940255a4dd7298e0762d3e | 0.612381 | 2.85867 | false | false | false | false |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/bg_rp/synth/bg_rp.vhd | 1 | 14,247 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY bg_rp IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END bg_rp;
ARCHITECTURE bg_rp_arch OF bg_rp IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bg_rp_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF bg_rp_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF bg_rp_arch : ARCHITECTURE IS "bg_rp,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF bg_rp_arch: ARCHITECTURE IS "bg_rp,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=bg_rp.mif,C_I" &
"NIT_FILE=bg_rp.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=12,C_READ_WIDTH_A=12,C_WRITE_DEPTH_A=156,C_READ_DEPTH_A=156,C_ADDRA_WIDTH=8,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=12,C_READ_WIDTH_B=12,C_WRITE_DEPTH_B=156,C_RE" &
"AD_DEPTH_B=156,C_ADDRB_WIDTH=8,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0" &
",C_COUNT_36K_BRAM=0,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.70645 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "bg_rp.mif",
C_INIT_FILE => "bg_rp.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 12,
C_READ_WIDTH_A => 12,
C_WRITE_DEPTH_A => 156,
C_READ_DEPTH_A => 156,
C_ADDRA_WIDTH => 8,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 12,
C_READ_WIDTH_B => 12,
C_WRITE_DEPTH_B => 156,
C_READ_DEPTH_B => 156,
C_ADDRB_WIDTH => 8,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "0",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.70645 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END bg_rp_arch;
| gpl-3.0 | 39d251e939f5a62c471c33b9755797c9 | 0.623149 | 2.997475 | false | false | false | false |
algebrato/eldig | Decoder_7_segmenti/Decoder_7_segmenti.vhd | 1 | 1,403 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Decoder_7_segmenti is
PORT(
U_NUMBER : in UNSIGNED(3 downto 0);
SEGMENTS : out std_logic_vector (0 to 6)
);
end Decoder_7_segmenti;
architecture Decoder of Decoder_7_segmenti is
begin
SEGMENTS(0)<='0' when U_NUMBER=0 or U_NUMBER=2 or U_NUMBER=3 or U_NUMBER>4 else '1';
SEGMENTS(1)<='0' when U_NUMBER=0 or U_NUMBER=1 or U_NUMBER=2 or U_NUMBER=3 or U_NUMBER=4 or U_NUMBER=7 or U_NUMBER=8 or U_NUMBER=9 else '1';
SEGMENTS(2)<='0' when U_NUMBER=0 or U_NUMBER=1 or U_NUMBER=3 or U_NUMBER=4 or U_NUMBER=5 or U_NUMBER=6 or U_NUMBER=7 or U_NUMBER=8 or U_NUMBER=9 else '1';
SEGMENTS(3)<='0' when U_NUMBER=0 or U_NUMBER=2 or U_NUMBER=3 or U_NUMBER=5 or U_NUMBER=6 or U_NUMBER=8 or U_NUMBER>9 else '1';
SEGMENTS(4)<='0' when U_NUMBER=0 or U_NUMBER=2 or U_NUMBER=6 or U_NUMBER=8 or U_NUMBER>9 else '1';
SEGMENTS(5)<='0' when U_NUMBER=0 or U_NUMBER=4 or U_NUMBER=5 or U_NUMBER=6 or U_NUMBER=8 or U_NUMBER>8 else '1';
SEGMENTS(6)<='0' when U_NUMBER=2 or U_NUMBER=3 or U_NUMBER=4 or U_NUMBER=5 or U_NUMBER=6 or U_NUMBER=8 or U_NUMBER>8 else '1';
end Decoder;
| gpl-3.0 | a48073e658eaf8b858d04c28ab0ca891 | 0.71062 | 2.698077 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/zpuino_timers.vhd | 13 | 6,137 | --
-- Timers for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_timers is
generic (
A_TSCENABLED: boolean := false;
A_PWMCOUNT: integer range 1 to 8 := 2;
A_WIDTH: integer range 1 to 32 := 16;
A_PRESCALER_ENABLED: boolean := true;
A_BUFFERS: boolean :=true;
B_TSCENABLED: boolean := false;
B_PWMCOUNT: integer range 1 to 8 := 2;
B_WIDTH: integer range 1 to 32 := 16;
B_PRESCALER_ENABLED: boolean := false;
B_BUFFERS: boolean := false
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
wb_intb_o:out std_logic;
pwm_A_out: out std_logic_vector(A_PWMCOUNT-1 downto 0);
pwm_B_out: out std_logic_vector(B_PWMCOUNT-1 downto 0)
);
end entity zpuino_timers;
architecture behave of zpuino_timers is
component timer is
generic (
TSCENABLED: boolean := false;
PWMCOUNT: integer range 1 to 8 := 2;
WIDTH: integer range 1 to 32 := 16;
PRESCALER_ENABLED: boolean := true;
BUFFERS: boolean := true
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(5 downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o: out std_logic;
pwm_out: out std_logic_vector(PWMCOUNT-1 downto 0)
);
end component timer;
signal timer0_read: std_logic_vector(wordSize-1 downto 0);
signal timer0_stb: std_logic;
signal timer0_cyc: std_logic;
signal timer0_we: std_logic;
signal timer0_interrupt: std_logic;
signal timer0_ack: std_logic;
signal timer1_read: std_logic_vector(wordSize-1 downto 0);
signal timer1_stb: std_logic;
signal timer1_cyc: std_logic;
signal timer1_we: std_logic;
signal timer1_interrupt: std_logic;
signal timer1_ack: std_logic;
begin
wb_inta_o <= timer0_interrupt;
wb_intb_o <= timer1_interrupt;
--comp <= timer0_comp;
timer0_inst: timer
generic map (
TSCENABLED => A_TSCENABLED,
PWMCOUNT => A_PWMCOUNT,
WIDTH => A_WIDTH,
PRESCALER_ENABLED => A_PRESCALER_ENABLED,
BUFFERS => A_BUFFERS
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => timer0_read,
wb_dat_i => wb_dat_i,
wb_adr_i => wb_adr_i(7 downto 2),
wb_cyc_i => timer0_cyc,
wb_stb_i => timer0_stb,
wb_we_i => timer0_we,
wb_ack_o => timer0_ack,
wb_inta_o => timer0_interrupt,
pwm_out => pwm_A_out
);
timer1_inst: timer
generic map (
TSCENABLED => B_TSCENABLED,
PWMCOUNT => B_PWMCOUNT,
WIDTH => B_WIDTH,
PRESCALER_ENABLED => B_PRESCALER_ENABLED,
BUFFERS => B_BUFFERS
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => timer1_read,
wb_dat_i => wb_dat_i,
wb_adr_i => wb_adr_i(7 downto 2),
wb_cyc_i => timer1_cyc,
wb_stb_i => timer1_stb,
wb_we_i => timer1_we,
wb_ack_o => timer1_ack,
wb_inta_o => timer1_interrupt,
pwm_out => pwm_B_out
);
process(wb_adr_i,timer0_read,timer1_read)
begin
wb_dat_o <= (others => '0');
case wb_adr_i(8) is
when '0' =>
wb_dat_o <= timer0_read;
when '1' =>
wb_dat_o <= timer1_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
timer0_cyc <= wb_cyc_i when wb_adr_i(8)='0' else '0';
timer1_cyc <= wb_cyc_i when wb_adr_i(8)='1' else '0';
timer0_stb <= wb_stb_i when wb_adr_i(8)='0' else '0';
timer1_stb <= wb_stb_i when wb_adr_i(8)='1' else '0';
timer0_we <= wb_we_i when wb_adr_i(8)='0' else '0';
timer1_we <= wb_we_i when wb_adr_i(8)='1' else '0';
wb_ack_o <= timer0_ack or timer1_ack;
--spp_data(0) <= timer0_spp_data;
--spp_data(1) <= timer1_spp_data;
--spp_en(0) <= timer0_spp_en;
--spp_en(1) <= timer1_spp_en;
end behave;
| mit | f1a974932ff278d54571d95104c74a74 | 0.612514 | 3.050199 | false | false | false | false |
chcbaram/FPGA | ZPUino_miniSpartan6_plus/ipcore_dir/Clock.vhd | 1 | 6,989 | -- file: Clock.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___100.000______0.000______50.0______400.000____150.000
-- CLK_OUT2____50.000______0.000______50.0______200.000____150.000
-- CLK_OUT3____25.000______0.000______50.0______300.000____150.000
-- CLK_OUT4____10.000______0.000______50.0_____2200.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary______________50____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity Clock is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_100M : out std_logic;
CLK_50M : out std_logic;
CLK_25M : out std_logic;
CLK_10M : out std_logic;
-- Status and control signals
LOCKED : out std_logic
);
end Clock;
architecture xilinx of Clock is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "Clock,clk_wiz_v3_6,{component_name=Clock,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=4,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clk_out1_internal : std_logic;
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clk2x : std_logic;
signal clkfx : std_logic;
signal clkdv : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN1);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 10,
CLKFX_MULTIPLY => 2,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 20.0,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "2X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => clk2x,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => clkdv,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
LOCKED <= locked_internal;
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfb,
I => clk2x);
clkout1_buf : BUFG
port map
(O => clk_out1_internal,
I => clk2x);
CLK_100M <= clk_out1_internal;
clkout2_buf : BUFG
port map
(O => CLK_50M,
I => clk0);
clkout3_buf : BUFG
port map
(O => CLK_25M,
I => clkdv);
clkout4_buf : BUFG
port map
(O => CLK_10M,
I => clkfx);
end xilinx;
| mit | 4e9bb2aa2c941cf7af914351a22af508 | 0.563457 | 4.120873 | false | false | false | false |
sinkswim/DLX-Pro | synthesis/DLX_synthesis_cfg/a.b-DataPath.core/a.b.c-execute.core/a.b.c.f-mux21.vhd | 1 | 416 | library ieee;
use ieee.std_logic_1164.all;
-- a goes through with s = '1', b with s = '0'
entity mux21 is
generic(
NBIT : integer := 32
);
Port (
a: in std_logic_vector(NBIT - 1 downto 0);
b: in std_logic_vector(NBIT - 1 downto 0);
s: in std_logic;
y: out std_logic_vector(NBIT - 1 downto 0)
);
end mux21;
architecture beh of mux21 is
begin
y <= a when S='1' else b;
end beh;
| mit | 62141bd7de26b0f5abb59d68857126c2 | 0.600962 | 2.506024 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/MISC_zpuino_wb_SevenSeg.vhd | 13 | 7,180 | --
-- 7 segment driver for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity MISC_zpuino_wb_SevenSeg is
generic (
BITS: integer := 2;
EXTRASIZE: integer := 32;
FREQ_PER_DISPLAY: integer := 120;
MHZ: integer := 96;
INVERT: boolean := true
);
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
segdata: out std_logic_vector(6 downto 0);
dot: out std_logic;
extra: out std_logic_vector(EXTRASIZE-1 downto 0);
enable: out std_logic_vector((2**BITS)-1 downto 0)
);
end entity MISC_zpuino_wb_SevenSeg;
architecture behave of MISC_zpuino_wb_SevenSeg is
-- Timer
constant COUNT: integer := 2**BITS;
constant DELAY: integer := (MHZ*1000000 / (FREQ_PER_DISPLAY*COUNT*16)) - 1; -- 16 is for brightness control
signal counter: integer range 0 to DELAY;
signal enabled: std_logic_vector(COUNT-1 downto 0) := (others => '0');
subtype segvaltype is std_logic_vector(7 downto 0);
type segstype is array(COUNT-1 downto 0) of segvaltype;
signal segs: segstype;
signal current_display: integer range 0 to COUNT-1; -- same as enashift
signal ack_q: std_logic;
signal extra_q: std_logic_vector(EXTRASIZE-1 downto 0);
signal brightctl: unsigned(3 downto 0);
signal brightcount: unsigned(3 downto 0);
signal pwm: std_logic;
signal invsig: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
invsig <= '1' when INVERT=true else '0';
enloop: for i in 0 to COUNT-1 generate
enable(i) <= (enabled(i) and pwm) xor invsig when current_display=i else invsig;
end generate;
pwm <= '1' when brightcount >= brightctl else '0';
outdata: for i in 0 to 6 generate
segdata(i) <= segs(current_display)(i) xor invsig;
end generate;
dot <= segs(current_display)(7) xor invsig;
wb_ack_o <= ack_q;
wb_inta_o <= '0';
extra <= extra_q when current_display=0 and pwm='1' else (others => '0');
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
counter <= DELAY;
current_display<=0;
brightcount <= "1111";
else
if counter=0 then
counter <= DELAY;
if brightcount="0000" then
brightcount <= "1111";
if current_display=0 then
current_display <= COUNT-1;
else
current_display <= current_display - 1;
end if;
else
brightcount <= brightcount - 1;
end if;
else
counter <= counter - 1;
end if;
end if;
end if;
end process;
process(wb_clk_i)
variable idx: std_logic_vector(BITS-1 downto 0);
variable int_idx: integer range 0 to COUNT-1;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
ack_q<='0';
enabled <= (others => '1');
else
ack_q <= '0';
-- Wishbone write
if wb_stb_i='1' and wb_cyc_i='1' and wb_we_i='1' and ack_q='0' then
ack_q<='1';
if wb_adr_i(BITS+2)='1' then
-- Display access --
idx := wb_adr_i(BITS+1 downto 2);
int_idx := conv_integer(idx);
segs(int_idx) <= wb_dat_i(segvaltype'RANGE);
else
case wb_adr_i(2) is
when '0' =>
enabled <= wb_dat_i(enabled'RANGE);
brightctl <= unsigned(wb_dat_i(16+brightctl'HIGH downto 16));
when '1' =>
extra_q <= wb_dat_i(extra_q'RANGE);
when others =>
null;
end case;
end if;
end if;
end if;
end if;
end process;
-- REad
process(wb_adr_i,enabled,brightctl,extra_q)
variable idx: std_logic_vector(BITS-1 downto 0);
variable int_idx: integer range 0 to COUNT-1;
begin
wb_dat_o <= (others => DontCareValue);
if wb_adr_i(BITS+2)='1' then
-- Display access --
idx := wb_adr_i(BITS+1 downto 2);
int_idx := conv_integer(idx);
wb_dat_o(segvaltype'RANGE)<=segs(int_idx);
else
case wb_adr_i(2) is
when '0' =>
wb_dat_o(enabled'RANGE) <= enabled;
wb_dat_o(16+brightctl'HIGH downto 16) <= std_logic_vector(brightctl);
when '1' =>
wb_dat_o(extra_q'RANGE) <= extra_q;
when others =>
null;
end case;
end if;
end process;
end behave;
| mit | 2ed5d42abf5392eb8d5d4e6d7ba8beb6 | 0.612953 | 3.448607 | false | false | false | false |
huukit/logicsynth | excercises/syn/lpm_constant0.vhd | 1 | 3,474 | -- megafunction wizard: %LPM_CONSTANT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_CONSTANT
-- ============================================================
-- File Name: lpm_constant0.vhd
-- Megafunction Name(s):
-- LPM_CONSTANT
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.1 Build 243 01/31/2013 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_constant0 IS
PORT
(
result : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END lpm_constant0;
ARCHITECTURE SYN OF lpm_constant0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT lpm_constant
GENERIC (
lpm_cvalue : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
result : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(0 DOWNTO 0);
LPM_CONSTANT_component : LPM_CONSTANT
GENERIC MAP (
lpm_cvalue => 1,
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "LPM_CONSTANT",
lpm_width => 1
)
PORT MAP (
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: Value NUMERIC "1"
-- Retrieval info: PRIVATE: nBit NUMERIC "1"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "1"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
-- Retrieval info: USED_PORT: result 0 0 1 0 OUTPUT NODEFVAL "result[0..0]"
-- Retrieval info: CONNECT: result 0 0 1 0 @result 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
| gpl-2.0 | 44190b11914e4c0b648efcf872c55739 | 0.645078 | 3.825991 | false | false | false | false |
ordepmalo/matrizled | rtl/vhdl/interface/interface.vhd | 1 | 3,840 | -------------------------------------------------------------------------------
-- Title : Interface to Hardware
-- Project :
-------------------------------------------------------------------------------
-- File : interface.vhd
-- Author : Pedro Messias Jose da Cunha Bastos
-- Company :
-- Created : 2015-04-17
-- Last update : 2015-05-19
-- Target Device :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description : Interface Implementation
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2015-04-17 1.0 Ordep Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.functions_pkg.all;
entity interface is
generic (
MAX_VALUE : natural := 32;
MAX_VALUE_BITS : natural := 5
);
port (
sysclk : in std_logic; -- clock global module DE2
reset_n : in std_logic; -- reset global
en_i : in std_logic; -- signal do clk_divider
ctrl_o : out std_logic_vector(MAX_VALUE_BITS - 1 downto 0); -- signal que vai para o sel_i
stb_o : out std_logic;
clk : out std_logic
);
end interface;
architecture interface_rtl of interface is
type INTERFACE_ST_TYPE is (ST_INIT, ST_SET_CLK, ST_SET_CLK_LOW, ST_VERIFY, ST_SET_STB, ST_SET_STB_LOW);
attribute syn_enconding : string;
attribute syn_enconding of INTERFACE_ST_TYPE : type is "safe"; -- FSM para n
signal state_reg : INTERFACE_ST_TYPE;
signal state_next : INTERFACE_ST_TYPE;
signal count_reg : unsigned(MAX_VALUE_BITS - 1 downto 0);
signal count_next : unsigned(MAX_VALUE_BITS - 1 downto 0);
signal clk_reg : std_logic;
signal clk_next : std_logic;
signal stb_reg : std_logic;
signal stb_next : std_logic;
begin
ctrl_o <= std_logic_vector(count_reg);
clk <= clk_reg;
stb_o <= stb_reg;
process(reset_n, sysclk)
begin
if reset_n = '0' then
state_reg <= ST_INIT;
count_reg <= (others => '0');
clk_reg <= '0';
stb_reg <= '0';
elsif rising_edge(sysclk) then -- sysclk = 50.000.000 (frequency of FPGA on DE2 module)
state_reg <= state_next;
count_reg <= count_next;
clk_reg <= clk_next;
stb_reg <= stb_next;
end if;
end process;
process(clk_reg, count_reg, en_i, state_reg, stb_reg)
begin
state_next <= state_reg;
count_next <= count_reg;
clk_next <= clk_reg;
stb_next <= stb_reg;
case state_reg is
when ST_INIT =>
state_next <= ST_SET_CLK;
count_next <= (others => '0'); -- zerar o contador
clk_next <= '0';
stb_next <= '0';
when ST_SET_CLK =>
if en_i = '1' then
clk_next <= '1';
state_next <= ST_SET_CLK_LOW;
end if;
when ST_SET_CLK_LOW =>
if en_i = '1' then
state_next <= ST_VERIFY;
clk_next <= '0';
end if;
when ST_VERIFY =>
if count_reg = MAX_VALUE - 1 then
state_next <= ST_SET_STB;
else
count_next <= count_reg + 1;
state_next <= ST_SET_CLK;
end if;
when ST_SET_STB =>
if en_i = '1' then
stb_next <= '1';
state_next <= ST_SET_STB_LOW;
end if;
when ST_SET_STB_LOW =>
if en_i = '1' then
stb_next <= '0';
state_next <= ST_INIT;
end if;
end case;
end process;
end interface_rtl;
| mit | 7c1cbb19f519ca4d61dae62e267b4735 | 0.477083 | 3.65019 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Benchy/stage.vhd | 13 | 6,197 | ----------------------------------------------------------------------------------
-- stage.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Programmable 32 channel trigger stage. It can operate in serial
-- and parallel mode. In serial mode any of the la_input channels
-- can be used as la_input for the 32bit shift register. Comparison
-- is done using the value and mask registers on the la_input in
-- parallel mode and on the shift register in serial mode.
-- If armed and 'level' has reached the configured minimum value,
-- the stage will start to check for a match.
-- The match and run output signal delay can be configured.
-- The stage will disarm itself after a match occured or when reset is set.
--
-- The stage supports "high speed demux" operation in serial and parallel
-- mode. (Lower and upper 16 channels contain a 16bit sample each.)
--
-- Matching is done using a pipeline. This should not increase the minimum
-- time needed between two dependend trigger stage matches, because the
-- dependence is evaluated in the last pipeline step.
-- It does however increase the delay for the capturing process, but this
-- can easily be compensated by software.
-- (By adjusting the before/after ratio.)
--
-- Changes: Synchronous reset.
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity stage is
port(
la_input : in std_logic_vector (31 downto 0);
la_inputReady : in std_logic;
data : in std_logic_vector (31 downto 0);
clock : in std_logic;
reset : in std_logic;
wrMask : in std_logic;
wrValue : in std_logic;
wrConfig : in std_logic;
arm : in std_logic;
level : in std_logic_vector (1 downto 0);
demuxed : in std_logic;
run : out std_logic;
match : out std_logic
);
end stage;
architecture behavioral of stage is
type STATES is (OFF, ARMED, MATCHED);
signal maskRegister, valueRegister : std_logic_vector (31 downto 0);
signal intermediateRegister, shiftRegister : std_logic_vector (31 downto 0);
signal testValue: std_logic_vector (31 downto 0);
signal cfgStart, cfgSerial : std_logic;
signal cfgChannel : std_logic_vector(4 downto 0);
signal cfgLevel : std_logic_vector(1 downto 0);
signal counter, cfgDelay : std_logic_vector(15 downto 0);
signal matchL16, matchH16, match32Register : std_logic;
signal state : STATES;
signal serialChannelL16, serialChannelH16 : std_logic;
begin
-- use shift register or la_input depending on configuration
testValue <= shiftRegister when cfgSerial = '1' else la_input;
-- apply mask and value and create a additional pipeline step
process(clock)
begin
if rising_edge(clock) then
intermediateRegister <= (testValue xor valueRegister) and maskRegister;
end if;
end process;
-- match upper and lower word separately
matchL16 <= '1' when intermediateRegister(15 downto 0) = "0000000000000000" else '0';
matchH16 <= '1' when intermediateRegister(31 downto 16) = "0000000000000000" else '0';
-- in demux mode only one half must match, in normal mode both words must match
process(clock)
begin
if rising_edge(clock) then
if demuxed = '1' then
match32Register <= matchL16 or matchH16;
else
match32Register <= matchL16 and matchH16;
end if;
end if;
end process;
-- select serial channel based on cfgChannel
process(la_input, cfgChannel)
begin
for i in 0 to 15 loop
if conv_integer(cfgChannel(3 downto 0)) = i then
serialChannelL16 <= la_input(i);
serialChannelH16 <= la_input(i + 16);
end if;
end loop;
end process;
-- shift in bit from selected channel whenever la_input is ready
process(clock)
begin
if rising_edge(clock) then
if la_inputReady = '1' then
if demuxed = '1' then -- in demux mode two bits come in per sample
shiftRegister <= shiftRegister(29 downto 0) & serialChannelH16 & serialChannelL16;
elsif cfgChannel(4) = '1' then
shiftRegister <= shiftRegister(30 downto 0) & serialChannelH16;
else
shiftRegister <= shiftRegister(30 downto 0) & serialChannelL16;
end if;
end if;
end if;
end process;
-- trigger state machine
process(clock, reset)
begin
if rising_edge(clock) then
if reset = '1' then
state <= OFF;
else
run <= '0';
match <= '0';
case state is
when OFF =>
if arm = '1' then
state <= ARMED;
end if;
when ARMED =>
if match32Register = '1' and level >= cfgLevel then
counter <= cfgDelay;
state <= MATCHED;
end if;
when MATCHED =>
if la_inputReady = '1' then
if counter = "0000000000000000" then
run <= cfgStart;
match <= not cfgStart;
state <= OFF;
else
counter <= counter - 1;
end if;
end if;
end case;
end if;
end if;
end process;
-- handle mask, value & config register write requests
process(clock)
begin
if rising_edge(clock) then
if wrMask = '1' then
maskRegister <= data;
end if;
if wrValue = '1' then
valueRegister <= data;
end if;
if wrConfig = '1' then
cfgStart <= data(27);
cfgSerial <= data(26);
cfgChannel <= data(24 downto 20);
cfgLevel <= data(17 downto 16);
cfgDelay <= data(15 downto 0);
end if;
end if;
end process;
end behavioral;
| mit | 5b854a305ca7ca39328c75329a072296 | 0.666936 | 3.630346 | false | false | false | false |
purisc-group/purisc | Compute_Group/CORE/read_instruction_stage.vhd | 1 | 1,473 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- This stage just updates the PC and requests the proper address from memory.
-- Memory sends the result directly to the next stage
entity read_instruction_stage is
port(
clk : in std_logic;
reset_n : in std_logic;
stall : in std_logic;
cbranch : in std_logic;
cbranch_address : in std_logic_vector(31 downto 0);
ubranch : in std_logic;
ubranch_address : in std_logic_vector(31 downto 0);
--outputs
next_pc : out std_logic_vector(31 downto 0);
--memory
r_addr_inst : out std_logic_vector(31 downto 0)
);
end entity;
architecture a1 of read_instruction_stage is
signal pc : std_logic_vector(31 downto 0);
begin
r_addr_inst <= pc;
process(clk, reset_n) begin
if (reset_n = '0') then
pc <= "00000000000000000000000000000000";
next_pc <= "00000000000000000000000000000011";
elsif (rising_edge(clk)) then
if(stall = '0') then
if (cbranch = '1') then
pc <= cbranch_address;
next_pc <= std_logic_vector(unsigned(cbranch_address) + to_unsigned(3,32));
elsif (ubranch = '1') then
pc <= ubranch_address;
next_pc <= std_logic_vector(unsigned(ubranch_address) + to_unsigned(3,32));
else
pc <= std_logic_vector(unsigned(pc) + to_unsigned(3,32));
next_pc <= std_logic_vector(unsigned(pc) + to_unsigned(6,32));
end if;
else
--hold previous value on stall (automatic)
end if;
end if;
end process;
end architecture; | gpl-2.0 | 4cf2d9f44dcef0b4fb7ff9b894806785 | 0.675492 | 3.01227 | false | false | false | false |
chcbaram/FPGA | ZPUino_miniSpartan6_plus/ipcore_dir/I2C/i2c_master_top.vhdl | 1 | 27,032 | ------------------------------------------------------------------------------
---- ----
---- I2C Master Core (Top Level) ----
---- ----
---- Internal file, can't be downloaded. ----
---- Based on code from: http://www.opencores.org/projects/i2c/ ----
---- ----
---- Description: ----
---- I2C master peripheral for the Wishbone bus. ----
---- Top level of the core. ----
---- I added various generics to customize the core: ----
---- * DEBUG enable debug registers ----
---- * MUX_BETTER true if using MUX is better than using tri-states ----
---- * FULL_SYNC true if you need full synchronous behavior, ----
---- introduces 1 WS ----
---- * FIXED_PRER assigning a value removes the PRER and uses it as ----
---- pre-scaler ----
---- * USE_IEN false if interrupts are always enabled (masked in ----
---- another component) ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Authors: ----
---- - Richard Herveille, [email protected] ----
---- - Salvador E. Tropea, salvador en inti gov ar (additions & optim.)----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2005 Salvador E. Tropea <salvador en inti gov ar> ----
---- Copyright (c) 2005 Instituto Nacional de Tecnolog Industrial ----
---- Copyright (c) 2000 Richard Herveille <[email protected]> ----
---- ----
---- Covered by the GPL license. ----
---- ----
---- Original distribution policy: ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: I2C_MasterTop(Structural) (Entity and architecture)----
---- File name: i2c_master_top.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: i2c_mwb ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- c.stdio_h ----
---- Target FPGA: Spartan II (XC2S100-5-PQ208) ----
---- Language: VHDL ----
---- Wishbone: SLAVE (rev B.2) ----
---- Synthesis tools: Xilinx Release 6.2.03i - xst G.31a ----
---- Simulation tools: GHDL [Sokcho edition] (0.1x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
--
-- CVS Log
--
-- $Id: i2c_master_top.vhdl,v 1.12 2006/04/18 13:37:08 salvador Exp $
--
-- $Date: 2006/04/18 13:37:08 $
-- $Revision: 1.12 $
-- $Author: salvador $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: i2c_master_top.vhdl,v $
-- Revision 1.12 2006/04/18 13:37:08 salvador
-- * Modificado: Peques retoques al indentado.
--
-- Revision 1.11 2006/04/17 19:44:43 salvador
-- * Modified: License to GPL.
--
-- Revision 1.10 2005/05/20 14:39:05 salvador
-- * Modificado: Mejorado el indentado usando bakalint 0.3.7.
--
-- Revision 1.9 2005/05/18 14:50:19 salvador
-- * Modificado: Los encabezados de los archivos para que cumplan con nuestras
-- recomendaciones.
--
-- Revision 1.8 2005/05/11 22:39:18 salvador
-- * Modificado: Pasado por el bakalint 0.3.5.
--
-- Revision 1.7 2005/03/29 20:35:44 salvador
-- * Modificado: Encerrado con "translate off/on" el cigo de simulaci para
-- que el XST no moleste.
-- * Agregado: Un generic para que las interrupciones esten siempre
-- habilitadas.
-- * Agregado: Default para wb_cyc_i de manera tal que no sea necesario
-- conectarlo.
-- * Modificado: Para ahorrar algunos F/F en registros que tienen bits sin
-- usar. A consecuencia de esto el bit "iack" se corri
--
-- Revision 1.6 2005/03/10 19:40:07 salvador
-- * Modificado: Para usar "rising_edge" que hace m legible el cigo.
-- * Agregado: MUX_BETTER para elegir que use muxs en lugar de tri-states.
-- Por defecto es falso con lo que ahorra unos 12 slice.
-- * Agregado: FULL_SYNC para lograr el comportamiento original con 1 WS.
-- * Agregado: FIXED_PRER con lo que se puede fijar el valor del prescaler lo
-- que ahorra unos 11 slice.
-- * Modificado: Los case de lectura/escritura de los registros por if/elsif
-- que permite controlar mejor el uso de los generic.
-- * Modificado: El testbench para que soporte FIXED_PRER.
--
-- Revision 1.5 2005/03/09 20:32:24 salvador
-- * Arreglado: Colisi entre los nombres de las constantes y las seles.
-- XST tiene un bug que lo hace volverse loco con esto.
--
-- Revision 1.4 2005/03/09 19:24:32 salvador
-- * Agregado: Script para generar un .h y un .inc a partir del package
-- exportando los neros de los registros.
-- * Modificado: Para que los registros PRER_LO/HI no sean 0 y 1 sino 3 y 4.
-- * Corregido: El core para no usar "magics" sino los valores definidos en
-- el package para los neros de registros.
-- * Verificado con el testbench del core y del PIC.
--
-- Revision 1.3 2005/03/09 17:41:16 salvador
-- * Agregado: Hojas de datos del 24LC02B.
-- * Modificado: Reemplazo de Report por Assert porque las herramientas de
-- Xilinx no lo soportan.
-- * Modificado: Comentado los printf en core porque no tengo el equivalente
-- para Xilinx.
-- * Corregido: El TB de la memoria no contestaba ACK luego de la escritura.
-- Ahora si y adem el TB verifica que no falten ACKs.
--
-- Revision 1.2 2005/03/08 20:42:40 salvador
-- * Corregido: El core I2C insertaba un estado de espera en el Wishbone,
-- eliminado. Al mismo tiempo la sel TIP estaba siendo generada con un F/F
-- en lugar de ser combinacional (no es necesario ya que CR se borra con RST).
-- Ambos cambios hacen que el core use so 1 clock para Wishbone y reducen
-- en 2 F/F el uso (estimado, no verificado).
-- * Agregado: Generic DEBUG al core y que cuando esthabilitado informe las
-- lecturas y escrituras Wishbone.
--
-- Revision 1.1 2005/03/08 15:57:36 salvador
-- * Movido al repositorio CVS.
-- * Agregado: TestBench en VHDL.
--
-- Revision 1.7 2004/03/14 10:17:03 rherveille
-- Fixed simulation issue when writing to CR register
--
-- Revision 1.6 2003/08/09 07:01:13 rherveille
-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
-- Fixed a potential bug in the byte controller's host-acknowledge generation.
--
-- Revision 1.5 2003/02/01 02:03:06 rherveille
-- Fixed a few 'arbitration lost' bugs. VHDL version only.
--
-- Revision 1.4 2002/12/26 16:05:47 rherveille
-- Core is now a Multimaster I2C controller.
--
-- Revision 1.3 2002/11/30 22:24:37 rherveille
-- Cleaned up code
--
-- Revision 1.2 2001/11/10 10:52:44 rherveille
-- Changed PRER reset value from 0x0000 to 0xffff, conform specs.
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.I2C_Master.all;
--synopsys translate off
library c;
use c.stdio_h.all;
--synopsys translate on
entity I2C_MasterTop is
generic(
ARST_LVL : std_logic := '0'; -- asynchronous reset level
DEBUG : boolean := false; -- enable debug registers
MUX_BETTER : boolean := false; -- true if using MUX is better than using tri-states
FULL_SYNC : boolean := false; -- true if you need full synchronous behavior, introduces 1 WS
FIXED_PRER : integer := -1; -- assigning a value removes the PRER and uses it as pre-scaler
USE_IEN : boolean := true -- false if interrupts are always enabled (masked in another component)
);
port (
-- wishbone signals
wb_clk_i : in std_logic; -- master clock input
wb_rst_i : in std_logic := '0'; -- synchronous active high reset
arst_i : in std_logic := not ARST_LVL; -- asynchronous reset
wb_adr_i : in unsigned(2 downto 0); -- lower address bits
wb_dat_i : in std_logic_vector(7 downto 0); -- Databus input
wb_dat_o : out std_logic_vector(7 downto 0); -- Databus output
wb_we_i : in std_logic; -- Write enable input
wb_stb_i : in std_logic; -- Strobe signals / core select signal
wb_cyc_i : in std_logic:='1'; -- Valid bus cycle input. Optional. Needed?
wb_ack_o : out std_logic; -- Bus cycle acknowledge output
wb_inta_o : out std_logic; -- interrupt request output signal
-- i2c lines
scl_pad_i : in std_logic; -- i2c clock line input
scl_pad_o : out std_logic; -- i2c clock line output
scl_padoen_o : out std_logic; -- i2c clock line output enable, active low
sda_pad_i : in std_logic; -- i2c data line input
sda_pad_o : out std_logic; -- i2c data line output
sda_padoen_o : out std_logic -- i2c data line output enable, active low
);
end entity I2C_MasterTop;
architecture Structural of I2C_MasterTop is
component I2C_MasterByteCtrl is
port (
wb_clk_i : in std_logic;
wb_rst_i : in std_logic; -- synchronous active high reset (WISHBONE compatible)
nreset_i : in std_logic; -- asynchornous active low reset (FPGA compatible)
ena_i : in std_logic; -- core enable signal
clk_cnt_i : in unsigned(15 downto 0); -- 4x SCL
-- input signals
start_i,
stop_i,
read_i,
write_i,
ack_in_i : in std_logic;
din_i : in std_logic_vector(7 downto 0);
-- output signals
cmd_ack_o : out std_logic;
ack_out_o : out std_logic;
i2c_busy_o : out std_logic;
i2c_al_o : out std_logic;
dout_o : out std_logic_vector(7 downto 0);
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen_o : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen_o : out std_logic -- i2c data line output enable, active low
);
end component I2C_MasterByteCtrl;
-- registers
signal prer : unsigned(15 downto 0); -- clock prescale register
signal ctr : std_logic_vector(7 downto 6); -- control register
signal txr : std_logic_vector(7 downto 0); -- transmit register
signal rxr : std_logic_vector(7 downto 0); -- receive register
signal cr : std_logic_vector(7 downto 2); -- command register
signal sr : std_logic_vector(7 downto 0); -- status register
-- internal reset signal
signal irst_i : std_logic;
-- wishbone write access
signal wb_wacc : std_logic;
-- internal acknowledge signal
signal iack_o : std_logic;
-- done signal: command completed, clear command register
signal done : std_logic;
-- command register signals
signal sta : std_logic;
signal sto : std_logic;
signal rd : std_logic;
signal wr : std_logic;
signal ack : std_logic;
signal iack : std_logic;
signal core_en : std_logic; -- core enable signal
signal ien : std_logic; -- interrupt enable signal
-- status register signals
signal irxack, rxack : std_logic; -- received aknowledge from slave
signal tip : std_logic; -- transfer in progress
signal irq_flag : std_logic; -- interrupt pending flag
signal i2c_busy_o : std_logic; -- i2c bus busy (start signal detected)
signal i2c_al_o, al_o : std_logic; -- arbitration lost
begin
-- generate internal reset signal
irst_i <= arst_i xor ARST_LVL;
-- generate acknowledge output signal
gen_ack_o_ws:
if FULL_SYNC generate
gen_ack_o:
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
iack_o <= wb_cyc_i and wb_stb_i and not iack_o; -- because timing is always honored
end if;
end process gen_ack_o;
end generate gen_ack_o_ws;
gen_ack_o:
if not(FULL_SYNC) generate
-- SET: The above code generates 1 WS in the Wishbone bus.
-- The following should be enough.
iack_o <= wb_cyc_i and wb_stb_i;
end generate gen_ack_o;
wb_ack_o <= iack_o;
-- end of acknowledge output signal
-- generate wishbone write access signal
wb_wacc <= wb_cyc_i and wb_stb_i and wb_we_i;
-- pre-scaler register
-- when FIXED_PRER is assigned we use it as divisor
fixed_prer_assign:
if not(FIXED_PRER=-1) generate
prer <= to_unsigned(FIXED_PRER,16);
end generate fixed_prer_assign;
-- generate pre-scaler register
prer_assign:
if FIXED_PRER=-1 generate
gen_prer:
process(irst_i, wb_clk_i)
begin
if (irst_i = '0') then
prer <= (others => '1');
elsif rising_edge(wb_clk_i) then
if (wb_rst_i = '1') then
prer <= (others => '1');
elsif (wb_wacc = '1') then
if wb_adr_i=I2C_UPRER_LO then
prer(7 downto 0) <= unsigned(wb_dat_i);
elsif wb_adr_i=I2C_UPRER_HI then
prer(15 downto 8) <= unsigned(wb_dat_i);
end if;
end if;
end if;
end process gen_prer;
end generate prer_assign;
-- end of pre-scaler register
-------------------------------------------------------------------------
-- Register decoding. Two versions one for tri-states (less cells for
-- FPGAs) and another using muxs.
-------------------------------------------------------------------------
reg_decoder_bus:
if not(MUX_BETTER) generate
wb_dat_o <= std_logic_vector(prer( 7 downto 0))
when wb_adr_i=I2C_UPRER_LO and FIXED_PRER=-1
else (others => 'Z');
wb_dat_o <= std_logic_vector(prer(15 downto 8))
when wb_adr_i=I2C_UPRER_HI and FIXED_PRER=-1
else (others => 'Z');
wb_dat_o(ctr'range) <= ctr
when wb_adr_i=I2C_UCTR
else (others => 'Z');
wb_dat_o <= rxr
when wb_adr_i=I2C_URXR
else (others => 'Z');
wb_dat_o <= sr(7 downto 5) & "000" & sr(1 downto 0)
when wb_adr_i=I2C_USR
else (others => 'Z');
wb_dat_o <= txr
when wb_adr_i=I2C_UTXR_R and DEBUG
else (others => 'Z');
wb_dat_o(cr'range) <= cr
when wb_adr_i=I2C_UCR_R and DEBUG
else (others => 'Z');
end generate reg_decoder_bus;
reg_decoder_mux:
if MUX_BETTER generate
-- assign wb_dat_o
assign_dato:
process(wb_clk_i)
variable dat_o : std_logic_vector(7 downto 0);
begin
if rising_edge(wb_clk_i) then
dat_o := (others => '0');
if wb_adr_i=I2C_UPRER_LO and FIXED_PRER=-1 then
dat_o := std_logic_vector(prer(7 downto 0));
elsif wb_adr_i=I2C_UPRER_HI and FIXED_PRER=-1 then
dat_o := std_logic_vector(prer(15 downto 8));
elsif wb_adr_i=I2C_UCTR then
dat_o(ctr'range) := ctr;
elsif wb_adr_i=I2C_URXR then
dat_o := rxr; -- write is transmit register TxR
elsif wb_adr_i=I2C_USR then
dat_o := sr(7 downto 5) & "000" & sr(1 downto 0); -- write is command register CR
-- Debugging registers:
-- These registers are not documented.
-- Functionality could change in future releases
elsif wb_adr_i=I2C_UTXR_R and DEBUG then
dat_o := txr;
elsif wb_adr_i=I2C_UCR_R and DEBUG then
dat_o(cr'range) := cr;
elsif wb_adr_i=I2C_UXXX_R and DEBUG then
dat_o := (others => '0');
else
dat_o := (others => 'X'); -- for simulation only
end if;
end if;
wb_dat_o <= dat_o;
--synopsys translate off
if DEBUG and wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='0' then
printf("Reading register %d ",to_integer(unsigned(wb_adr_i)));
printf("(=0x%X)\n",to_integer(unsigned(dat_o)));
end if;
--synopsys translate on
end process assign_dato;
end generate reg_decoder_mux;
-- end of register decoding
-- generate registers (CR, SR see below)
gen_regs:
process(irst_i, wb_clk_i)
begin
if (irst_i = '0') then
ctr <= (others => '0');
txr <= (others => '0');
elsif rising_edge(wb_clk_i) then
if (wb_rst_i = '1') then
ctr <= (others => '0');
txr <= (others => '0');
elsif (wb_wacc = '1') then
if wb_adr_i=I2C_UPRER_LO and FIXED_PRER=-1 then
null; --write to CR, avoid executing the others clause
elsif wb_adr_i=I2C_UPRER_HI and FIXED_PRER=-1 then
null; --write to PRER, avoid executing the others clause
elsif wb_adr_i=I2C_UCTR then
ctr <= wb_dat_i(ctr'range);
elsif wb_adr_i=I2C_UTXR then
txr <= wb_dat_i;
elsif wb_adr_i=I2C_UCR then
null; --write to CR, avoid executing the others clause
else -- illegal cases, for simulation only
--synopsys translate off
assert false
report "Illegal write address, setting all registers to unknown."
severity failure;
--synopsys translate on
ctr <= (others => 'X');
txr <= (others => 'X');
end if;
--synopsys translate off
if DEBUG then
printf("Writing register %d ",to_integer(unsigned(wb_adr_i)));
printf(" with 0x%X\n",to_integer(unsigned(wb_dat_i)));
end if;
--synopsys translate on
end if;
end if;
end process gen_regs;
-- generate command register
gen_cr:
process(irst_i, wb_clk_i)
begin
if (irst_i = '0') then
cr <= (others => '0');
elsif rising_edge(wb_clk_i) then
if (wb_rst_i = '1') then
cr <= (others => '0');
elsif (wb_wacc = '1') then
if ( (core_en = '1') and (wb_adr_i = I2C_UCR) ) then
-- only take new commands when i2c core enabled
-- pending commands are finished
cr <= wb_dat_i(cr'range);
end if;
else
if (done = '1' or i2c_al_o= '1') then
cr(7 downto 4) <= (others => '0'); -- clear command bits when command done or arbitration lost
end if;
cr(2) <= '0'; -- clear IRQ_ACK bit
end if;
end if;
end process gen_cr;
-- decode command register
sta <= cr(7);
sto <= cr(6);
rd <= cr(5);
wr <= cr(4);
ack <= cr(3);
iack <= cr(2);
-- TIP bit generation
gen_tip:
if not(FULL_SYNC) generate
-- SET: tip is just (rd or wr), the reset signals affects cr, we don't
-- need to generate another F/F for it.
tip <= (rd or wr);
end generate gen_tip;
gen_tip_sync:
if FULL_SYNC generate
gen_tip_proc:
process (wb_clk_i, irst_i)
begin
if (irst_i = '0') then
tip <= '0';
elsif rising_edge(wb_clk_i) then
if (wb_rst_i = '1') then
tip <= '0';
else
tip <= (rd or wr);
end if;
end if;
end process gen_tip_proc;
end generate gen_tip_sync;
-- end of TIP bit generation
-- decode control register
core_en <= ctr(7);
ien <= ctr(6) when USE_IEN else '1';
-- hookup byte controller block
byte_ctrl: I2C_MasterByteCtrl
port map(
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
nreset_i => irst_i,
ena_i => core_en,
clk_cnt_i=> prer,
start_i => sta,
stop_i => sto,
read_i => rd,
write_i => wr,
ack_in_i => ack,
i2c_busy_o=> i2c_busy_o,
i2c_al_o => i2c_al_o,
din_i => txr,
cmd_ack_o=> done,
ack_out_o=> irxack,
dout_o => rxr,
scl_i => scl_pad_i,
scl_o => scl_pad_o,
scl_oen_o=> scl_padoen_o,
sda_i => sda_pad_i,
sda_o => sda_pad_o,
sda_oen_o=> sda_padoen_o
);
-- status register block + interrupt request signal
st_irq_block:
block
begin
-- generate status register bits
gen_sr_bits:
process (wb_clk_i, irst_i)
begin
if (irst_i = '0') then
al_o <= '0';
rxack <= '0';
irq_flag <= '0';
elsif rising_edge(wb_clk_i) then
if (wb_rst_i = '1') then
al_o <= '0';
rxack <= '0';
irq_flag <= '0';
else
al_o <= i2c_al_o or (al_o and not sta);
rxack <= irxack;
-- interrupt request flag is always generated
irq_flag <= (done or i2c_al_o or irq_flag) and not iack;
end if;
end if;
end process gen_sr_bits;
-- generate interrupt request signals
gen_irq:
process (wb_clk_i, irst_i)
begin
if (irst_i = '0') then
wb_inta_o <= '0';
elsif rising_edge(wb_clk_i) then
if (wb_rst_i = '1') then
wb_inta_o <= '0';
else
-- interrupt signal is only generated when IEN (interrupt enable bit) is set
wb_inta_o <= irq_flag and ien;
end if;
end if;
end process gen_irq;
-- assign status register bits
sr(7) <= rxack;
sr(6) <= i2c_busy_o;
sr(5) <= al_o;
--sr(4 downto 2) <= (others => '0'); -- reserved
sr(1) <= tip;
sr(0) <= irq_flag;
end block st_irq_block;
end architecture Structural;
| mit | 74530b00abf8ddadce046edac30b88b5 | 0.473809 | 3.982909 | false | false | false | false |
chcbaram/FPGA | ZPUino_miniSpartan6_plus/ipcore_dir/zpuino_debug_core.vhd | 1 | 5,362 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
use work.zpuinopkg.all;
use work.zpuino_config.all;
entity zpuino_debug_core is
port (
clk: in std_logic;
rst: in std_logic;
dbg_in: in zpu_dbg_out_type;
dbg_out: out zpu_dbg_in_type;
dbg_reset: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end entity;
architecture behave of zpuino_debug_core is
signal enter_ss: std_logic :='0';
signal step: std_logic := '0';
signal status_injection_ready: std_logic;
signal status_injectmode: std_logic;
type state_type is (
state_idle,
state_debug,
state_enter_inject,
state_flush,
state_inject,
state_leave_inject,
state_step
);
type dbgregs_type is record
state: state_type;
step: std_logic;
inject: std_logic;
freeze: std_logic;
injectmode: std_logic;
reset: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
signal dbgr: dbgregs_type;
signal injected: std_logic;
signal inject_q_in: std_logic := '0';
signal inject_q: std_logic := '0';
alias jtag_debug: std_logic is jtag_ctrl_chain_in(0);
alias jtag_inject: std_logic is jtag_ctrl_chain_in(1);
alias jtag_step: std_logic is jtag_ctrl_chain_in(2);
alias jtag_reset: std_logic is jtag_ctrl_chain_in(3);
alias jtag_opcode: std_logic_vector(7 downto 0) is jtag_ctrl_chain_in(11 downto 4);
signal pc_i: std_logic_vector(wordSize-1 downto 0);
signal sp_i: std_logic_vector(wordSize-1 downto 0);
begin
pc_i(wordSize-1 downto dbg_in.pc'high+1) <= (others => '0');
pc_i(dbg_in.pc'high downto dbg_in.pc'low) <= dbg_in.pc;
sp_i(wordSize-1 downto dbg_in.sp'high+1) <= (others => '0');
sp_i(dbg_in.sp'high downto dbg_in.sp'low) <= dbg_in.sp;
sp_i(dbg_in.sp'low-1 downto 0) <= (others => '0');
-- jtag chain output
jtag_data_chain_out <=
dbg_in.idim &
sp_i &
dbg_in.stacka &
pc_i &
dbg_in.brk &
status_injection_ready
;
status_injection_ready <= '1' when dbgr.state = state_debug else '0';
process(clk, rst, dbgr, dbg_in.valid, jtag_debug, jtag_opcode,
inject_q, dbg_in.ready, dbg_in.pc, dbg_in.idim, jtag_ctrl_chain_in)
variable w: dbgregs_type;
begin
w := dbgr;
if rst='1' then
w.state := state_idle;
w.reset := '0';
w.flush := '0';
w.injectmode := '0';
w.inject := '0';
w.step := '0';
w.freeze := '0';
injected <= '0';
else
injected <= '0';
case dbgr.state is
when state_idle =>
w.freeze := '0';
--if jtag_debug='1' then
-- w.freeze := '1';
-- w.state := state_debug;
--end if;
if jtag_debug='1' then
--if dbg_ready='1' then
w.injectmode := '1';
--w.opcode := jtag_opcode;
-- end if;
-- Wait for pipeline to finish
if dbg_in.valid='0' and dbg_in.ready='1' then
--report "Enter PC " & hstr(dbg_pc) & " IDIM flag " & chr(dbg_idim) severity note;
w.state:=state_debug;
end if;
--end if;
end if;
when state_debug =>
w.step := '0';
if inject_q='1' then
w.state := state_enter_inject;
w.injectmode := '1';
w.opcode := jtag_opcode;
elsif jtag_debug='0' then
w.flush:='1';
w.state := state_leave_inject;
end if;
when state_leave_inject =>
w.flush := '0';
w.injectmode:='0';
w.state := state_idle;
when state_enter_inject =>
-- w.state := state_flush;
w.state := state_inject;
when state_flush =>
w.flush := '1';
w.state := state_inject;
when state_inject =>
w.inject := '1';
w.flush := '0';
-- Here ?
injected <= '1';
w.state := state_step;
when state_step =>
injected <= '0';
w.inject := '0';
if dbg_in.valid='1' then
-- w.step := '1';
w.state := state_debug;
end if;
when others =>
end case;
end if;
if rising_edge(clk) then
dbgr <= w;
end if;
end process;
dbg_out.freeze <= dbgr.freeze;
--dbg_reset <= dbgr.reset;
dbg_out.inject <= dbgr.inject;
dbg_out.injectmode <= dbgr.injectmode;-- and dbg_ready;
dbg_out.step <= dbgr.step;
dbg_out.flush <= dbgr.flush;
dbg_out.opcode <= dbgr.opcode;
process(clk)
begin
if rising_edge(clk) then
dbg_reset <= jtag_ctrl_chain_in(3);
end if;
end process;
-- Synchronization stuff
process(jtag_inject, clk, injected, inject_q_in)
begin
if injected='1' then
inject_q <= '0';
inject_q_in <= '0';
else
if rising_edge(jtag_inject) then
inject_q_in <= '1';
--else
-- inject_q_in <= inject_q_in;
end if;
if rising_edge(clk) then
inject_q <= inject_q_in;
end if;
end if;
end process;
end behave;
| mit | b8fcde36ae989584d6c6dd0bc3c83bb5 | 0.537859 | 3.189768 | false | false | false | false |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/pikachu_down_pixel/synth/pikachu_down_pixel.vhd | 1 | 14,462 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY pikachu_down_pixel IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END pikachu_down_pixel;
ARCHITECTURE pikachu_down_pixel_arch OF pikachu_down_pixel IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF pikachu_down_pixel_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(12 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF pikachu_down_pixel_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF pikachu_down_pixel_arch : ARCHITECTURE IS "pikachu_down_pixel,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF pikachu_down_pixel_arch: ARCHITECTURE IS "pikachu_down_pixel,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=" &
"pikachu_down_pixel.mif,C_INIT_FILE=pikachu_down_pixel.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=12,C_READ_WIDTH_A=12,C_WRITE_DEPTH_A=5589,C_READ_DEPTH_A=5589,C_ADDRA_WIDTH=13,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=12," &
"C_READ_WIDTH_B=12,C_WRITE_DEPTH_B=5589,C_READ_DEPTH_B=5589,C_ADDRB_WIDTH=13,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0" &
",C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=2,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 4.681258 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "pikachu_down_pixel.mif",
C_INIT_FILE => "pikachu_down_pixel.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 12,
C_READ_WIDTH_A => 12,
C_WRITE_DEPTH_A => 5589,
C_READ_DEPTH_A => 5589,
C_ADDRA_WIDTH => 13,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 12,
C_READ_WIDTH_B => 12,
C_WRITE_DEPTH_B => 5589,
C_READ_DEPTH_B => 5589,
C_ADDRB_WIDTH => 13,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "2",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 4.681258 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 13)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END pikachu_down_pixel_arch;
| gpl-3.0 | f25ea9d94c2f2b7177562f5932728015 | 0.627714 | 3.004779 | false | false | false | false |
sinkswim/DLX-Pro | DLX_simulation_cfg/a.b-DataPath.core/a.b.b-decode.core/a.b.b.a-Reg_File.vhd | 1 | 3,548 | -------------------------------------------------------------------------
-- Register File
-- Register File, clocked with the write signal RegWrite. There are
-- two read ports, and 1 write port. Internally it has been added a
-- forwarding logic to prevent data corruption whenever two instructions
-- are writing and reading the same register.
-------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.globals.all;
-------------------------------------------------------------------------
-------------------------------------------------------------------------
entity reg_file is
port (
-- INPUTS
read_address_1 : in std_logic_vector(4 downto 0); -- address of reg 1 to be read(instruction 25-21)
read_address_2 : in std_logic_vector(4 downto 0); -- address of reg 2 to be read(instruction 20-16)
write_address : in std_logic_vector(4 downto 0); -- address of reg to be written
write_data : in std_logic_vector(31 downto 0); -- data to be written at the address specified in wirte_address
reg_write : in std_logic;
rst : in std_logic;
-- OUTPUTS
data_reg_1 : out std_logic_vector(31 downto 0); -- data from read port 1
data_reg_2 : out std_logic_vector(31 downto 0) -- data from read port 2
);
end reg_file;
-------------------------------------------------------------------------
-------------------------------------------------------------------------
architecture behavioral of reg_file is
-- Sub-type declaration
type bank is array (integer range 0 to 31) of std_logic_vector(31 downto 0); -- bank of register
-- Internal signals
signal bank_register : bank;
begin
-------------------------------------
-- Name: Write Process
-- Type: Sequential
-- Reset: Asynchronous
-- It implements the
-- write operations
-- on the register
-- file
--------------------------------------
write_process:process(rst, reg_write, write_address, write_data)
begin
if (rst = '1') then
bank_register <= (others => (others => '0'));
elsif (reg_write = '1') then
-- Writing register 0 is forbidded
if ( not(to_integer(unsigned(write_address)) = 0) ) then
bank_register(to_integer(unsigned(write_address))) <= write_data;
end if;
end if;
end process;
--------------------------------------
-- Name: Read Process
-- Type: Combinational
-- It implement read operations and
-- the forwarding logic
--------------------------------------
read_process:process(read_address_1, read_address_2, reg_write, write_data, write_address)
begin
-- Forwarding logic: the forwarding should be activated if and only if
-- the reg_write signal is asserted and there is a conflict (same address)
if ( (reg_write = '1') and (read_address_1 = write_address)) then
data_reg_1 <= write_data;
data_reg_2 <= bank_register(to_integer(unsigned(read_address_2)));
elsif ( (reg_write = '1') and (read_address_2 = write_address) ) then
data_reg_2 <= write_data;
data_reg_1 <= bank_register(to_integer(unsigned(read_address_1)));
else
data_reg_1 <= bank_register(to_integer(unsigned(read_address_1)));
data_reg_2 <= bank_register(to_integer(unsigned(read_address_2)));
end if;
end process;
end behavioral;
| mit | fa5816266fc66f7e16a81d942ec1fe86 | 0.524803 | 4.279855 | false | false | false | false |
feddischson/soc_maker | examples/or1200_test/xilinx_s3starter/or1200_test_top.vhd | 1 | 7,178 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity or1200_test_top is
Port ( CLK_50M : in STD_LOGIC;
BTN_SOUTH : in STD_LOGIC;
RS232_DCE_RXD : in STD_LOGIC;
RS232_DCE_TXD : out STD_LOGIC
);
end or1200_test_top;
architecture Behavioral of or1200_test_top is
constant VPI_TAP : boolean := false;
component dbg_comm_vpi is
Port(
SYS_CLK : out STD_LOGIC;
SYS_RST : out STD_LOGIC;
P_TMS : out STD_LOGIC;
P_TCK : out STD_LOGIC;
P_TRST : out STD_LOGIC;
P_TDI : out STD_LOGIC;
P_TDO : in STD_LOGIC
);
end component;
signal P_TMS : STD_LOGIC;
signal P_TCK : STD_LOGIC;
signal P_TRST : STD_LOGIC;
signal P_TDI : STD_LOGIC;
signal P_TDO : STD_LOGIC;
component or1200_test is
port(
clk_i : in std_logic ;
rst_i : in std_logic ;
tck_i : in std_logic ;
tdi_i : in std_logic ;
tdo_o : out std_logic ;
debug_rst_i : in std_logic ;
shift_dr_i : in std_logic ;
pause_dr_i : in std_logic ;
update_dr_i : in std_logic ;
capture_dr_i : in std_logic ;
debug_select_i : in std_logic;
stx_pad_o : out std_logic ;
srx_pad_i : in std_logic ;
rts_pad_o : out std_logic ;
cts_pad_i : in std_logic ;
dtr_pad_o : out std_logic ;
dsr_pad_i : in std_logic ;
ri_pad_i : in std_logic ;
dcd_pad_i : in std_logic
);
end component;
component tap_top is
port (
-- JTAG pads
signal tms_pad_i : in std_logic;
signal tck_pad_i : in std_logic;
signal trstn_pad_i : in std_logic;
signal tdi_pad_i : in std_logic;
signal tdo_pad_o : out std_logic;
signal tdo_padoe_o : out std_logic;
-- TAP states
signal test_logic_reset_o : out std_logic;
signal run_test_idle_o : out std_logic;
signal shift_dr_o : out std_logic;
signal pause_dr_o : out std_logic;
signal update_dr_o : out std_logic;
signal capture_dr_o : out std_logic;
-- Select signals for boundary scan or mbist
signal extest_select_o : out std_logic;
signal sample_preload_select_o : out std_logic;
signal mbist_select_o : out std_logic;
signal debug_select_o : out std_logic;
-- TDO signal that is connected to TDI of sub-modules.
signal tdi_o : out std_logic;
-- TDI signals from sub-modules
signal debug_tdo_i : in std_logic; -- from debug module
signal bs_chain_tdo_i : in std_logic; -- from Boundary Scan Chain
signal mbist_tdo_i : in std_logic -- from Mbist Chain
);
end component;
component xilinx_internal_jtag is
port(
signal tck_o : out std_logic;
signal debug_tdo_i : in std_logic;
signal tdi_o : out std_logic;
signal test_logic_reset_o : out std_logic;
signal run_test_idle_o : out std_logic;
signal shift_dr_o : out std_logic;
signal capture_dr_o : out std_logic;
signal pause_dr_o : out std_logic;
signal update_dr_o : out std_logic;
signal debug_select_o : out std_logic
);
end component;
signal clk_i : std_logic ;
signal rst_i : std_logic ;
signal n_rst_i : std_logic ;
signal tck_i : std_logic ;
signal tdi_i : std_logic ;
signal tdo_o : std_logic ;
signal shift_dr_i : std_logic ;
signal pause_dr_i : std_logic ;
signal update_dr_i : std_logic ;
signal capture_dr_i : std_logic ;
signal debug_select_i : std_logic ;
signal debug_rst_i : std_logic ;
signal stx_pad_o : std_logic ;
signal srx_pad_i : std_logic ;
signal rts_pad_o : std_logic ;
signal cts_pad_i : std_logic ;
signal dtr_pad_o : std_logic ;
signal dsr_pad_i : std_logic ;
signal ri_pad_i : std_logic ;
signal dcd_pad_i : std_logic ;
signal gnd : std_logic;
signal VPI_CLK : std_logic;
begin
gnd <= '0';
srx_pad_i <= RS232_DCE_RXD;
RS232_DCE_TXD <= stx_pad_o;
cts_pad_i <= '0';
dsr_pad_i <= '0';
dcd_pad_i <= '0';
ri_pad_i <= '0';
--
-- Simulation Part:
-- The VPI and Standard JTAG TAP is used
--
VPI_SEL : if VPI_TAP = true generate
-- clk_i <= CLK_50M;
rst_i <= BTN_SOUTH;
n_rst_i <= not rst_i;
--
-- Debug VPI
--
vpi : dbg_comm_vpi
port map(
SYS_CLK => clk_i,
P_TMS => P_TMS ,
P_TCK => P_TCK ,
P_TRST => P_TRST ,
P_TDI => P_TDI ,
P_TDO => P_TDO );
--
-- Standard JTAG TAP
--
tap_inst : tap_top
port map(
-- JTAG pads: this 6 signals simulates
-- the physical connection to the tap
tms_pad_i => P_TMS,
tck_pad_i => P_TCK,
trstn_pad_i => n_rst_i,
tdi_pad_i => P_TDI,
tdo_pad_o => P_TDO,
tdo_padoe_o => open,
-- TAP states
test_logic_reset_o => debug_rst_i,
run_test_idle_o => open,
shift_dr_o => shift_dr_i,
pause_dr_o => pause_dr_i,
update_dr_o => update_dr_i,
capture_dr_o => capture_dr_i,
-- Select signals for boundary scan or mbist
extest_select_o => open,
sample_preload_select_o => open,
mbist_select_o => open,
debug_select_o => debug_select_i,
-- TDO signal that is connected to TDI of sub-modules.
tdi_o => tdi_i,
-- TDI signals from sub-modules
debug_tdo_i => tdo_o,
bs_chain_tdo_i => gnd,
mbist_tdo_i => gnd
);
tck_i <= P_TCK;
end generate VPI_SEL;
--
-- Synthesis Part:
-- The FPGA internal Xilinx TAP is used
--
NO_VPI_SEL : if VPI_TAP = false generate
clk_i <= CLK_50M;
rst_i <= BTN_SOUTH;
n_rst_i <= not rst_i;
tap_inst_xilinx : xilinx_internal_jtag
port map(
tck_o => tck_i,
debug_tdo_i => tdo_o,
tdi_o => tdi_i,
test_logic_reset_o => debug_rst_i,
run_test_idle_o => open,
shift_dr_o => shift_dr_i,
capture_dr_o => capture_dr_i,
pause_dr_o => pause_dr_i,
update_dr_o => update_dr_i,
debug_select_o => debug_select_i
);
end generate NO_VPI_SEL;
--
-- The SOC instance
--
top : or1200_test
port map(
clk_i => clk_i ,
rst_i => rst_i ,
tck_i => tck_i ,
tdi_i => tdi_i ,
tdo_o => tdo_o ,
debug_rst_i => debug_rst_i ,
shift_dr_i => shift_dr_i ,
pause_dr_i => pause_dr_i ,
update_dr_i => update_dr_i ,
capture_dr_i => capture_dr_i ,
debug_select_i => debug_select_i ,
stx_pad_o => stx_pad_o ,
srx_pad_i => srx_pad_i ,
rts_pad_o => rts_pad_o ,
cts_pad_i => cts_pad_i ,
dtr_pad_o => dtr_pad_o ,
dsr_pad_i => dsr_pad_i ,
ri_pad_i => ri_pad_i ,
dcd_pad_i => dcd_pad_i
);
end Behavioral;
| gpl-3.0 | c0359464ac56ad8dc0bcf01462f8a06e | 0.525355 | 2.90725 | false | true | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/zpuino_top.vhd | 13 | 16,382 | --
-- Top module for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.wishbonepkg.all;
entity zpuino_top is
port (
clk: in std_logic;
rst: in std_logic;
-- Connection to board IO module
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type;
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type;
slot_interrupt: in slot_std_logic_type;
dbg_reset: out std_logic;
-- Memory accesses (for DMA)
-- This is a master interface
m_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
m_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
m_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end entity zpuino_top;
architecture behave of zpuino_top is
component zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out std_logic_vector(wordSize-1 downto 0);
stack_a_write: in std_logic_vector(wordSize-1 downto 0);
stack_b_write: in std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: in std_logic;
stack_a_enable: in std_logic;
stack_b_writeenable: in std_logic;
stack_b_enable: in std_logic;
stack_a_addr: in std_logic_vector(stackSize_bits-1 downto 0);
stack_b_addr: in std_logic_vector(stackSize_bits-1 downto 0)
);
end component zpuino_stack;
component wbarb2_1 is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master 0 signals
m0_wb_dat_o: out std_logic_vector(31 downto 0);
m0_wb_dat_i: in std_logic_vector(31 downto 0);
m0_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m0_wb_sel_i: in std_logic_vector(3 downto 0);
m0_wb_cti_i: in std_logic_vector(2 downto 0);
m0_wb_we_i: in std_logic;
m0_wb_cyc_i: in std_logic;
m0_wb_stb_i: in std_logic;
m0_wb_ack_o: out std_logic;
-- Master 1 signals
m1_wb_dat_o: out std_logic_vector(31 downto 0);
m1_wb_dat_i: in std_logic_vector(31 downto 0);
m1_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m1_wb_sel_i: in std_logic_vector(3 downto 0);
m1_wb_cti_i: in std_logic_vector(2 downto 0);
m1_wb_we_i: in std_logic;
m1_wb_cyc_i: in std_logic;
m1_wb_stb_i: in std_logic;
m1_wb_ack_o: out std_logic;
-- Slave signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic
);
end component;
component zpuino_debug_core is
port (
clk: in std_logic;
rst: in std_logic;
dbg_in: in zpu_dbg_out_type;
dbg_out: out zpu_dbg_in_type;
dbg_reset: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end component;
component wb_rom_ram is
port (
ram_wb_clk_i: in std_logic;
ram_wb_rst_i: in std_logic;
ram_wb_ack_o: out std_logic;
ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
ram_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
ram_wb_cyc_i: in std_logic;
ram_wb_stb_i: in std_logic;
ram_wb_we_i: in std_logic;
rom_wb_clk_i: in std_logic;
rom_wb_rst_i: in std_logic;
rom_wb_ack_o: out std_logic;
rom_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
rom_wb_cyc_i: in std_logic;
rom_wb_stb_i: in std_logic;
rom_wb_cti_i: in std_logic_vector(2 downto 0)
);
end component wb_rom_ram;
component wbmux2 is
generic (
select_line: integer;
address_high: integer:=31;
address_low: integer:=2
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_adr_i: in std_logic_vector(address_high downto address_low);
m_wb_sel_i: in std_logic_vector(3 downto 0);
m_wb_cti_i: in std_logic_vector(2 downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
-- Slave 0 signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(address_high downto address_low);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic;
-- Slave 1 signals
s1_wb_dat_i: in std_logic_vector(31 downto 0);
s1_wb_dat_o: out std_logic_vector(31 downto 0);
s1_wb_adr_o: out std_logic_vector(address_high downto address_low);
s1_wb_sel_o: out std_logic_vector(3 downto 0);
s1_wb_cti_o: out std_logic_vector(2 downto 0);
s1_wb_we_o: out std_logic;
s1_wb_cyc_o: out std_logic;
s1_wb_stb_o: out std_logic;
s1_wb_ack_i: in std_logic
);
end component wbmux2;
signal io_read: std_logic_vector(wordSize-1 downto 0);
signal io_write: std_logic_vector(wordSize-1 downto 0);
signal io_address: std_logic_vector(maxAddrBitIncIO downto 0);
signal io_stb: std_logic;
signal io_cyc: std_logic;
signal io_we: std_logic;
signal io_ack: std_logic;
signal wb_read: std_logic_vector(wordSize-1 downto 0);
signal wb_write: std_logic_vector(wordSize-1 downto 0);
signal wb_address: std_logic_vector(maxAddrBitIncIO downto 0);
signal wb_stb: std_logic;
signal wb_cyc: std_logic;
signal wb_we: std_logic;
signal wb_ack: std_logic;
signal interrupt: std_logic;
signal poppc_inst: std_logic;
signal dbg_pc: std_logic_vector(maxAddrBit downto 0);
signal dbg_opcode: std_logic_vector(7 downto 0);
signal dbg_opcode_in: std_logic_vector(7 downto 0);
signal dbg_sp: std_logic_vector(10 downto 2);
signal dbg_brk: std_logic;
signal dbg_stacka: std_logic_vector(wordSize-1 downto 0);
signal dbg_stackb: std_logic_vector(wordSize-1 downto 0);
signal dbg_step: std_logic := '0';
signal dbg_freeze: std_logic;
signal dbg_flush: std_logic;
signal dbg_valid: std_logic;
signal dbg_ready: std_logic;
signal dbg_inject: std_logic;
signal dbg_injectmode: std_logic;
signal dbg_idim: std_logic;
signal stack_a_addr,stack_b_addr: std_logic_vector(stackSize_bits+1 downto 2);
signal stack_a_writeenable, stack_b_writeenable, stack_a_enable,stack_b_enable: std_logic;
signal stack_a_write,stack_b_write: std_logic_vector(31 downto 0);
signal stack_a_read,stack_b_read: std_logic_vector(31 downto 0);
signal stack_clk: std_logic;
signal ram_wb_clk_i: std_logic;
signal ram_wb_rst_i: std_logic;
signal ram_wb_ack_o: std_logic;
signal ram_wb_dat_i: std_logic_vector(wordSize-1 downto 0);
signal ram_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal ram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal ram_wb_cyc_i: std_logic;
signal ram_wb_stb_i: std_logic;
signal ram_wb_we_i: std_logic;
signal cpu_ram_wb_clk_i: std_logic;
signal cpu_ram_wb_rst_i: std_logic;
signal cpu_ram_wb_ack_o: std_logic;
signal cpu_ram_wb_dat_i: std_logic_vector(wordSize-1 downto 0);
signal cpu_ram_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal cpu_ram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal cpu_ram_wb_cyc_i: std_logic;
signal cpu_ram_wb_stb_i: std_logic;
signal cpu_ram_wb_we_i: std_logic;
signal rom_wb_clk_i: std_logic;
signal rom_wb_rst_i: std_logic;
signal rom_wb_ack_o: std_logic;
signal rom_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal rom_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal rom_wb_cyc_i: std_logic;
signal rom_wb_stb_i: std_logic;
signal rom_wb_cti_i: std_logic_vector(2 downto 0);
signal dbg_to_zpu: zpu_dbg_in_type;
signal dbg_from_zpu: zpu_dbg_out_type;
begin
core: zpu_core_extreme
port map (
wb_clk_i => clk,
wb_rst_i => rst,
wb_ack_i => wb_ack,
wb_dat_i => wb_read,
wb_dat_o => wb_write,
wb_adr_o => wb_address,
wb_cyc_o => wb_cyc,
wb_stb_o => wb_stb,
wb_we_o => wb_we,
wb_inta_i => interrupt,
poppc_inst => poppc_inst,
break => open,
stack_clk => stack_clk,
stack_a_read => stack_a_read,
stack_b_read => stack_b_read,
stack_a_write => stack_a_write,
stack_b_write => stack_b_write,
stack_a_writeenable => stack_a_writeenable,
stack_b_writeenable => stack_b_writeenable,
stack_a_enable => stack_a_enable,
stack_b_enable => stack_b_enable,
stack_a_addr => stack_a_addr,
stack_b_addr => stack_b_addr,
rom_wb_ack_i => rom_wb_ack_o,
rom_wb_dat_i => rom_wb_dat_o,
rom_wb_adr_o => rom_wb_adr_i(maxAddrBit downto 0),
rom_wb_cyc_o => rom_wb_cyc_i,
rom_wb_stb_o => rom_wb_stb_i,
rom_wb_cti_o => rom_wb_cti_i,
rom_wb_stall_i => '0',
dbg_in => dbg_to_zpu,
dbg_out => dbg_from_zpu
);
stack: zpuino_stack
port map (
stack_clk => stack_clk,
stack_a_read => stack_a_read,
stack_b_read => stack_b_read,
stack_a_write => stack_a_write,
stack_b_write => stack_b_write,
stack_a_writeenable => stack_a_writeenable,
stack_b_writeenable => stack_b_writeenable,
stack_a_enable => stack_a_enable,
stack_b_enable => stack_b_enable,
stack_a_addr => stack_a_addr,
stack_b_addr => stack_b_addr
);
memory: wb_rom_ram
port map (
ram_wb_clk_i => clk,
ram_wb_rst_i => rst,
ram_wb_ack_o => ram_wb_ack_o,
ram_wb_dat_i => ram_wb_dat_i,
ram_wb_dat_o => ram_wb_dat_o,
ram_wb_adr_i => ram_wb_adr_i,
ram_wb_cyc_i => ram_wb_cyc_i,
ram_wb_stb_i => ram_wb_stb_i,
ram_wb_we_i => ram_wb_we_i,
rom_wb_clk_i => clk,
rom_wb_rst_i => rst,
rom_wb_ack_o => rom_wb_ack_o,
rom_wb_dat_o => rom_wb_dat_o,
rom_wb_adr_i => rom_wb_adr_i,
rom_wb_cyc_i => rom_wb_cyc_i,
rom_wb_stb_i => rom_wb_stb_i,
rom_wb_cti_i => rom_wb_cti_i
);
dbg: zpuino_debug_core
port map (
clk => clk,
rst => rst,
dbg_out => dbg_to_zpu,
dbg_in => dbg_from_zpu,
dbg_reset => dbg_reset,
jtag_data_chain_out => jtag_data_chain_out,
jtag_ctrl_chain_in => jtag_ctrl_chain_in
);
io: zpuino_io
port map (
wb_clk_i => clk,
wb_rst_i => rst,
wb_dat_o => io_read,
wb_dat_i => io_write,
wb_adr_i => io_address,
wb_cyc_i => io_cyc,
wb_stb_i => io_stb,
wb_ack_o => io_ack,
wb_we_i => io_we,
wb_inta_o => interrupt,
intready => poppc_inst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt
);
iomemmux: wbmux2
generic map (
select_line => maxAddrBitIncIO,
address_high =>maxAddrBitIncIO,
address_low=>0
)
port map (
wb_clk_i => clk,
wb_rst_i => rst,
-- Master
m_wb_dat_o => wb_read,
m_wb_dat_i => wb_write,
m_wb_adr_i => wb_address,
m_wb_sel_i => "1111",--wb_sel,
m_wb_cti_i => CTI_CYCLE_CLASSIC,--wb_cti,
m_wb_we_i => wb_we,
m_wb_cyc_i => wb_cyc,
m_wb_stb_i => wb_stb,
m_wb_ack_o => wb_ack,
-- Slave 0 signals
s0_wb_dat_i => cpu_ram_wb_dat_o,
s0_wb_dat_o => cpu_ram_wb_dat_i,
s0_wb_adr_o => cpu_ram_wb_adr_i,
s0_wb_sel_o => open, --ram_wb_sel_i,
s0_wb_cti_o => open, --ram_wb_cti_i,
s0_wb_we_o => cpu_ram_wb_we_i,
s0_wb_cyc_o => cpu_ram_wb_cyc_i,
s0_wb_stb_o => cpu_ram_wb_stb_i,
s0_wb_ack_i => cpu_ram_wb_ack_o,
-- Slave 1 signals
s1_wb_dat_i => io_read,
s1_wb_dat_o => io_write,
s1_wb_adr_o => io_address,
s1_wb_sel_o => open,
s1_wb_cti_o => open,
s1_wb_we_o => io_we,
s1_wb_cyc_o => io_cyc,
s1_wb_stb_o => io_stb,
s1_wb_ack_i => io_ack
);
memarb: wbarb2_1
generic map (
ADDRESS_HIGH => maxAddrBitIncIO,
ADDRESS_LOW => 0
)
port map (
wb_clk_i => clk,
wb_rst_i => rst,
-- Master 0 signals (CPU)
m0_wb_dat_o => cpu_ram_wb_dat_o,
m0_wb_dat_i => cpu_ram_wb_dat_i,
m0_wb_adr_i => cpu_ram_wb_adr_i,
m0_wb_sel_i => (others => '1'),
m0_wb_cti_i => CTI_CYCLE_CLASSIC,
m0_wb_we_i => cpu_ram_wb_we_i,
m0_wb_cyc_i => cpu_ram_wb_cyc_i,
m0_wb_stb_i => cpu_ram_wb_stb_i,
m0_wb_ack_o => cpu_ram_wb_ack_o,
-- Master 1 signals
m1_wb_dat_o => m_wb_dat_o,
m1_wb_dat_i => m_wb_dat_i,
m1_wb_adr_i => m_wb_adr_i,
m1_wb_sel_i => (others => '1'),
m1_wb_cti_i => CTI_CYCLE_CLASSIC,
m1_wb_we_i => m_wb_we_i,
m1_wb_cyc_i => m_wb_cyc_i,
m1_wb_stb_i => m_wb_stb_i,
m1_wb_ack_o => m_wb_ack_o,
-- Slave signals
s0_wb_dat_i => ram_wb_dat_o,
s0_wb_dat_o => ram_wb_dat_i,
s0_wb_adr_o => ram_wb_adr_i,
s0_wb_sel_o => open,
s0_wb_cti_o => open,
s0_wb_we_o => ram_wb_we_i,
s0_wb_cyc_o => ram_wb_cyc_i,
s0_wb_stb_o => ram_wb_stb_i,
s0_wb_ack_i => ram_wb_ack_o
);
end behave;
| mit | 8fee8d24325fe450ea1a7e4b119796c5 | 0.594311 | 2.697069 | false | false | false | false |
sinkswim/DLX-Pro | synthesis/DLX_synthesis_cfg/a.b-DataPath.core/a.b.c-execute.core/a.b.c.c-branch_circ.vhd | 1 | 887 | library ieee;
use ieee.std_logic_1164.all;
-- determines wether a branch is to be taken:
-- if we have BEQZ and ALU result is zero then output = 1
-- also if we have BNEZ and ALU result is not zero then output = 1
-- in all other cases out = 0
entity branch_circ is
port(
-- inputs
branch_type : in std_logic; -- BNEZ is branch_type = '1', BEQZ is branch_type = '0'
zero : in std_logic; -- from ALU, 1 when the result of an operation yields zero
-- outputs
branch_taken : out std_logic -- 1 means the branch has to be taken
);
end branch_circ;
architecture rtl of branch_circ is
begin
process(branch_type, zero)
begin
if((branch_type = '0' and zero = '1') or (branch_type = '1' and zero = '0')) then
branch_taken <= '1';
else
branch_taken <= '0';
end if;
end process;
end rtl;
| mit | 60d5718484315bad32a3abcb4e7800f3 | 0.607666 | 3.398467 | false | false | false | false |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/pikachu_pixel_1/synth/pikachu_pixel.vhd | 1 | 14,387 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY pikachu_pixel IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END pikachu_pixel;
ARCHITECTURE pikachu_pixel_arch OF pikachu_pixel IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF pikachu_pixel_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(12 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF pikachu_pixel_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF pikachu_pixel_arch : ARCHITECTURE IS "pikachu_pixel,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF pikachu_pixel_arch: ARCHITECTURE IS "pikachu_pixel,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=pikac" &
"hu_pixel.mif,C_INIT_FILE=pikachu_pixel.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=12,C_READ_WIDTH_A=12,C_WRITE_DEPTH_A=6804,C_READ_DEPTH_A=6804,C_ADDRA_WIDTH=13,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=12,C_READ_WIDTH_B=" &
"12,C_WRITE_DEPTH_B=6804,C_READ_DEPTH_B=6804,C_ADDRB_WIDTH=13,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CK" &
"T=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=3,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 5.016775 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "pikachu_pixel.mif",
C_INIT_FILE => "pikachu_pixel.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 12,
C_READ_WIDTH_A => 12,
C_WRITE_DEPTH_A => 6804,
C_READ_DEPTH_A => 6804,
C_ADDRA_WIDTH => 13,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 12,
C_READ_WIDTH_B => 12,
C_WRITE_DEPTH_B => 6804,
C_READ_DEPTH_B => 6804,
C_ADDRB_WIDTH => 13,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "3",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 5.016775 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 13)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END pikachu_pixel_arch;
| gpl-3.0 | cea627fdac37b46310174a659242fd05 | 0.626816 | 3.006059 | false | false | false | false |
sh-chris110/chris | FPGA/chris.sdram.ok/Qsys/soc_design/soc_design_inst.vhd | 1 | 2,133 | component soc_design is
port (
dram_addr : out std_logic_vector(12 downto 0); -- addr
dram_ba : out std_logic_vector(1 downto 0); -- ba
dram_cas_n : out std_logic; -- cas_n
dram_cke : out std_logic; -- cke
dram_cs_n : out std_logic; -- cs_n
dram_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq
dram_dqm : out std_logic_vector(1 downto 0); -- dqm
dram_ras_n : out std_logic; -- ras_n
dram_we_n : out std_logic; -- we_n
dram_clk_clk : out std_logic; -- clk
fpga_reset_n : in std_logic := 'X'; -- reset_n
ref_clk : in std_logic := 'X'; -- clk
uart_RXD : in std_logic := 'X'; -- RXD
uart_TXD : out std_logic -- TXD
);
end component soc_design;
u0 : component soc_design
port map (
dram_addr => CONNECTED_TO_dram_addr, -- dram.addr
dram_ba => CONNECTED_TO_dram_ba, -- .ba
dram_cas_n => CONNECTED_TO_dram_cas_n, -- .cas_n
dram_cke => CONNECTED_TO_dram_cke, -- .cke
dram_cs_n => CONNECTED_TO_dram_cs_n, -- .cs_n
dram_dq => CONNECTED_TO_dram_dq, -- .dq
dram_dqm => CONNECTED_TO_dram_dqm, -- .dqm
dram_ras_n => CONNECTED_TO_dram_ras_n, -- .ras_n
dram_we_n => CONNECTED_TO_dram_we_n, -- .we_n
dram_clk_clk => CONNECTED_TO_dram_clk_clk, -- dram_clk.clk
fpga_reset_n => CONNECTED_TO_fpga_reset_n, -- fpga.reset_n
ref_clk => CONNECTED_TO_ref_clk, -- ref.clk
uart_RXD => CONNECTED_TO_uart_RXD, -- uart.RXD
uart_TXD => CONNECTED_TO_uart_TXD -- .TXD
);
| gpl-2.0 | c21ed5699276898e73a13cd070ca958b | 0.409283 | 3.34326 | false | false | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/board_Papilio_One_500k/zpuino_config.vhd | 13 | 2,502 | --
-- Configuration file for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
package zpuino_config is
-- General ZPUino configuration
type zpu_core_type is (
small,
large
);
-- ZPUino large is buggy, don't use it.
constant zpuinocore: zpu_core_type := small;
-- Set iobusyinput to 'true' to allow registered input to IO core. This also allows for IO
-- to become busy without needing to register its inputs. However, an extra clock-cycle is
-- required to access IO if this is used.
constant zpuino_iobusyinput: boolean := true;
-- For SPI blocking operation, you need to define also iobusyinput
constant zpuino_spiblocking: boolean := true;
-- Number of GPIO to map (number of FPGA pins)
constant zpuino_gpio_count: integer := 49;
-- Peripheral Pin Select
constant zpuino_pps_enabled: boolean := false;
-- Internal SPI ADC
constant zpuino_adc_enabled: boolean := false;
constant zpuino_number_io_select_bits: integer := 4;
end package zpuino_config;
| mit | 07abf0777796f1b30098b417fb2c3b93 | 0.726619 | 3.87907 | false | true | false | false |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/clk_32to50_dcm.vhd | 13 | 6,302 | -- file: clk_32to50_dcm.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____50.000______0.000______50.0______600.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to50_dcm is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to50_dcm;
architecture xilinx of clk_32to50_dcm is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to50_dcm,clk_wiz_v3_6,{component_name=clk_32to50_dcm,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=31.25,clkin2_period=31.25,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
--clkin1 <= CLK_IN1;
clkin2_inst: BUFG
port map (
I => CLK_IN1,
O => clkin1
);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 16,
CLKFX_MULTIPLY => 25,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
-- no phase alignment active, connect to ground
clkfb <= '0';
-- clkout1_buf : BUFG
-- port map
-- (O => CLK_OUT1,
-- I => clkfx);
CLK_OUT1 <= clkfx;
end xilinx;
| mit | 3aed7ac84e73877667c3eef03c2c883a | 0.574738 | 4.240915 | false | false | false | false |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/title2_1/title2_sim_netlist.vhdl | 1 | 126,817 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:33:54 2017
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/title2_1/title2_sim_netlist.vhdl
-- Design : title2
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity title2_bindec is
port (
ena_array : out STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of title2_bindec : entity is "bindec";
end title2_bindec;
architecture STRUCTURE of title2_bindec is
begin
\/i_\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => addra(1),
I1 => addra(0),
O => ena_array(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity title2_blk_mem_gen_mux is
port (
douta : out STD_LOGIC_VECTOR ( 8 downto 0 );
addra : in STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
DOADO : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
DOPADOP : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of title2_blk_mem_gen_mux : entity is "blk_mem_gen_mux";
end title2_blk_mem_gen_mux;
architecture STRUCTURE of title2_blk_mem_gen_mux is
signal sel_pipe : STD_LOGIC_VECTOR ( 1 downto 0 );
signal sel_pipe_d1 : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
\douta[10]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A0ACFC0"
)
port map (
I0 => DOADO(7),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(7),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(7),
I4 => sel_pipe_d1(0),
O => douta(7)
);
\douta[11]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A0ACFC0"
)
port map (
I0 => DOPADOP(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(0),
I4 => sel_pipe_d1(0),
O => douta(8)
);
\douta[3]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A0ACFC0"
)
port map (
I0 => DOADO(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(0),
I4 => sel_pipe_d1(0),
O => douta(0)
);
\douta[4]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A0ACFC0"
)
port map (
I0 => DOADO(1),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(1),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(1),
I4 => sel_pipe_d1(0),
O => douta(1)
);
\douta[5]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A0ACFC0"
)
port map (
I0 => DOADO(2),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(2),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(2),
I4 => sel_pipe_d1(0),
O => douta(2)
);
\douta[6]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A0ACFC0"
)
port map (
I0 => DOADO(3),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(3),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(3),
I4 => sel_pipe_d1(0),
O => douta(3)
);
\douta[7]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A0ACFC0"
)
port map (
I0 => DOADO(4),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(4),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(4),
I4 => sel_pipe_d1(0),
O => douta(4)
);
\douta[8]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A0ACFC0"
)
port map (
I0 => DOADO(5),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(5),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(5),
I4 => sel_pipe_d1(0),
O => douta(5)
);
\douta[9]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A0ACFC0"
)
port map (
I0 => DOADO(6),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(6),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(6),
I4 => sel_pipe_d1(0),
O => douta(6)
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => sel_pipe(0),
Q => sel_pipe_d1(0),
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => sel_pipe(1),
Q => sel_pipe_d1(1),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => addra(0),
Q => sel_pipe(0),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => addra(1),
Q => sel_pipe(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity title2_blk_mem_gen_prim_wrapper_init is
port (
douta : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of title2_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end title2_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of title2_blk_mem_gen_prim_wrapper_init is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000004000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(13 downto 0) => addra(13 downto 0),
ADDRBWRADDR(13 downto 0) => B"00000000000000",
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15 downto 1) => B"000000000000000",
DIADI(0) => dina(0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 1),
DOADO(0) => douta(0),
DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => '1',
ENBWREN => '0',
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \title2_blk_mem_gen_prim_wrapper_init__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \title2_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init";
end \title2_blk_mem_gen_prim_wrapper_init__parameterized0\;
architecture STRUCTURE of \title2_blk_mem_gen_prim_wrapper_init__parameterized0\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000003000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \title2_blk_mem_gen_prim_wrapper_init__parameterized1\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \title2_blk_mem_gen_prim_wrapper_init__parameterized1\ : entity is "blk_mem_gen_prim_wrapper_init";
end \title2_blk_mem_gen_prim_wrapper_init__parameterized1\;
architecture STRUCTURE of \title2_blk_mem_gen_prim_wrapper_init__parameterized1\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000060000000000000000000000000800000000000000",
INITP_01 => X"00000078001F80000000000000000001800078000000000000000000040001E0",
INITP_02 => X"00000C00000000000003E001FC0000300000000000001F0007E0000000000000",
INITP_03 => X"0000000FF00FF80007E00000000000003F803FE0000F80000000000000FC007F",
INITP_04 => X"FC03FFC0000000000000FFC0FFE003FE00000000000003FE03FF8007F8000000",
INITP_05 => X"00000001FFE7FFE0FFFC00000000000007FF0FFF80FFF00000000000001FF83F",
INITP_06 => X"FFFFFFF00000000000001FFFFFFFFFFFC00000000000007FFDFFFC3FFF000000",
INITP_07 => X"0001F0007FFFFFFFFFFF00078000070001FFFFFFFFFFFC00070000200007FFFF",
INITP_08 => X"FFFFFFFE0FFC00001FF807FFFFFFFFFFF00FF000007F801FFFFFFFFFFFC00FE0",
INITP_09 => X"00003FFFCFFFFFFFFFFFFFFFC00000FFF87FFFFFFFFFFF8FFF000003FF81FFFF",
INITP_0A => X"FFFFFFFFFFFC000001FFFFFFFFFFFFFFFFFFF8000007FFFBFFFFFFFFFFFFFFF0",
INITP_0B => X"000001FFF9FFFFFFFFFFFFFFC000000FFFE7FFFFFFFFFFFFFF0000007FFFFFFF",
INITP_0C => X"FFFFFFFFFFFC0000001FFF3FFFFFFFFFFFFFF00000007FFE7FFFFFFFFFFFFFE0",
INITP_0D => X"0000001FFCFF8EFFFFFFFFFF80000000FFFBFFFFFFFFFFFFFF00000003FFC7FE",
INITP_0E => X"F79FFFFFFFFFFC000001FFDFF79CFFFFFFFFFFC0000007FF3FE1BFFFFFFFFFE0",
INITP_0F => X"FFFF03FFFE3FE3F9BFFFFFFFFFFFF003FFF9FF1FC7FFFFFFFFFFFF0001FFF7FC",
INIT_00 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_01 => X"9E9E9E9EE09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_02 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_03 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_04 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_05 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9EE0E09E",
INIT_06 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_07 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_08 => X"9E9E9E9E9EE09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9EE0E0E0E09E9E9E9E9E",
INIT_09 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_0A => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_0B => X"E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9EE0E0E0E09E9E9E9E9E9E9E9E9E9E9E",
INIT_0C => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9EE0",
INIT_0D => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_0E => X"9E9E9E9E9E9E9E9E9E9E9EE0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_0F => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9EE0E0E0E09E9E9E",
INIT_10 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_11 => X"9E9E00009EE0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_12 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9EE0E0E0E0E09E9E9E9E9E9E9E9E",
INIT_13 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_14 => X"E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9EE0E09E9E9E9E",
INIT_15 => X"9E9E9E9E9E9E9E9E9E9E009E9E9EE0E0E0E0E09E9E9E9E9E9E9E9E9E000000E0",
INIT_16 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_17 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9EE0E09E9E9E9E9E9E9E9E9E9E",
INIT_18 => X"9E9E9E9E00009E9EE0E0E0E0E0E09E9E9E9E9E9E9E00000000E0E0E0E0E0E0E0",
INIT_19 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_1A => X"9E9E9E9E9E9E9E9E9E9E9E9EE0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_1B => X"0000E0E0E0E0E0E0E09E9E9E9E9E9E000000E0E0E0E0E0E0E0E0E09E9E9E9E9E",
INIT_1C => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0000",
INIT_1D => X"9E9E9E9E9EE0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_1E => X"E0E0E0E09E9E9E9E9E000000E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E",
INIT_1F => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E00000000E0E0E0E0",
INIT_20 => X"E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_21 => X"9E9E9E000000E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9EE0E0E0",
INIT_22 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E000000E0E0E0E0E0E0E0E0E09E",
INIT_23 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_24 => X"E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9EE0E0E0E0E0E0E0E0E09E",
INIT_25 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E000000E0E0E0E0E0E0E0E0E0E09E9E9E000000",
INIT_26 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_27 => X"E0E0E0E0E0E09E9E9E9E9E9E9E9EE0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E",
INIT_28 => X"9E9E9E9E9E9E9E00000000E0E0E0E0E0E0E0E0E0E09E9E000000E0E0E0E0E0E0",
INIT_29 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_2A => X"E09E9E9E9E9E9E9EE0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E",
INIT_2B => X"9E00000000E0E0E0E0E0E0E0E0E0E0E09E000000E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_2C => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_2D => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_2E => X"E0E0E0E0E0E0E0E0E0E0E00000E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E",
INIT_2F => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E00000000E0",
INIT_30 => X"E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_31 => X"E0E0E0E0E0E000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9EE0E0E0E0E0E0",
INIT_32 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E00000000E0E0E0E0E0E0E0",
INIT_33 => X"E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_34 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_35 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E00000000E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_36 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_37 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E",
INIT_38 => X"9E9E9E9E9E9E9E9E9E00000000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_39 => X"9E9E9E9E9EE0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9EE09E9E9E9E9E",
INIT_3A => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E",
INIT_3B => X"9E9E9E00000000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_3C => X"E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9EE0E0E09E9E9E9E9E9E9E9E",
INIT_3D => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9EE0E0E0",
INIT_3E => X"00E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_3F => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9EE0E0E0E0E09E9E9E9E9E9E9E9E9E000000",
INIT_40 => X"E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9EE0E0E0E0E0E0E09E9E9E9E9E",
INIT_41 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_42 => X"9E9E9E9E9E9E9E9E9EE0E0E0E0E0E0E0E09E9E9E9E9E9E00000000E0E0E0E0E0",
INIT_43 => X"E0E0E0E09E9E9E9E9E9E9E9EE0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E",
INIT_44 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_45 => X"9E9E9EE0E0E0E0E0E0E0E0E0E09E9E9E9E00000000E0E0E0E0E0E0E0E0E0E0E0",
INIT_46 => X"9E9E9E9EE0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E00",
INIT_47 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E",
INIT_48 => X"E0E0E0E0E0E0E0E0E09E9E9E000000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_49 => X"E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E00000000E0E0",
INIT_4A => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9EE0E0E0E0",
INIT_4B => X"E0E0E0E0E09E000000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_4C => X"E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E00000000E0E0E0E0E0E0E0E0",
INIT_4D => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_4E => X"E0E00000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_4F => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E00000000E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_50 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E",
INIT_51 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_52 => X"9E9E9E9E9E9E9E9E0000000000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E000E0E0",
INIT_53 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E",
INIT_54 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_55 => X"9E9E9E00000000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0FEE0E0E0E0E0E0",
INIT_56 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_57 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_58 => X"00E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0FEFEE0E0E0E0E0E0E0E0E0E0E0",
INIT_59 => X"E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E000000",
INIT_5A => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_5B => X"E0E0E0E0E0E0E0E0E0E0E00000FEFEFEE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_5C => X"E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0000000000E0E0E0E0",
INIT_5D => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_5E => X"E0E0E0E0E00000FEFEFEFEE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_5F => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0000000000E0E0E0E0E0E0E0E0E0",
INIT_60 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E",
INIT_61 => X"00FEFEFEE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_62 => X"9E9E9E9E9E9E9E9E9E9E9E9E0000000000E0E0E0E0E0E0E0E0E0E0E0E0E0E000",
INIT_63 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E",
INIT_64 => X"E0E0E0E0E0E0E0FEE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_65 => X"9E9E9E9E9E9E0000000000E0E0E0E0E0E0E0E0E0E0E0E0E00000FEFEFEFEE0E0",
INIT_66 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_67 => X"E0FEFEE0FEFEFEE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_68 => X"9E0000000000E0E0E0E0E0E0E0E0E0E0E0E0000000FEFEE0E0E0E0E0E0E0E000",
INIT_69 => X"E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_6A => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_6B => X"E0E0E0E0E0E0E0E0E0E0E0E0E000FEFEFEE0E0E0E0E0E0E0E0FEFEFEFEFEFEFE",
INIT_6C => X"E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0000000000",
INIT_6D => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_6E => X"E0E0E0E0E0E00000FEFEFEE0E0E0E0E0E0000000FEFEFE00FEFEE0E0E0E0E0E0",
INIT_6F => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0000000000E0E0E0E0E0",
INIT_70 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E",
INIT_71 => X"0000FEFEFEE0E0E0E0E0E000000000FEFE00FEFEE0E0FEFEE0E0E0E0E0E0E0E0",
INIT_72 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0000000000E0E0E0E0E0E0E0E0E0E0E0",
INIT_73 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E",
INIT_74 => X"E0E0E0E000FEFEFEFE0000FEFEFE0000FEFEFEE0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_75 => X"9E9E9E9E9E9E9E9E9E9E9E00000000E0E0E0E0E0E0E0E0E0E0E000FEFEFEFEE0",
INIT_76 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E",
INIT_77 => X"FEFEFEFE00FEFEE0E00000FEFEE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_78 => X"9E9E9E9E9E0000E0E0E0E0E0E0E0E0E0E0E0E0E000FEFEFEE0E0E0E0E0E00000",
INIT_79 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E",
INIT_7A => X"FEFE000000FEFEE0E0FEFEFEE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_7B => X"E0E0E0E0E0E0E0E0E0E0E0E0E00000FEFEFEE0E0E0E0E0E0000000FEFEFEFEFE",
INIT_7C => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9EE0E0",
INIT_7D => X"FE00FEFEFEFEE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_7E => X"E0E0E0E0E0E0E0000000FEFEE0E0E0E0E0E0E0000000FEFEFEFEFEE0E00000FE",
INIT_7F => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9EE0E0E0E0E0E0E0E0E0E0",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[10]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \douta[11]\(0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \title2_blk_mem_gen_prim_wrapper_init__parameterized2\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 );
DOPADOP : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \title2_blk_mem_gen_prim_wrapper_init__parameterized2\ : entity is "blk_mem_gen_prim_wrapper_init";
end \title2_blk_mem_gen_prim_wrapper_init__parameterized2\;
architecture STRUCTURE of \title2_blk_mem_gen_prim_wrapper_init__parameterized2\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0_n_0\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"7BFF5FFFFFFFFFFF80FFFFFFFFC7F1FFFFFFFFFFFFC3FFFFDFFC3EEFFFFFFFFF",
INITP_01 => X"FFF001FFFF7FF3F98F7FFFFFFFFFE00FFFFFFF8DE7F3FFFFFFFFFFC03FFFFFFE",
INITP_02 => X"C7C7E7F3FFFFFFF80007FFF1FF3F9FDFEFFFFFFFF0003FFFCFFCDE63FFFFFFFF",
INITP_03 => X"FF000007FFFFCE7CE7FFBFFFFFFC00003FFFFFF9F39EFEFFFFFFFC0001FFFE7F",
INITP_04 => X"1FFE79F0FFCFFFC000003FFFFCFFF1E787FF7FFF000001FFFFF3FE3DBEFFFFFF",
INITP_05 => X"FFFE00007FFFF8E71FFFDCFCFFFFC00001FFFFE719EFFE7FF3FFFC000007FFFF",
INITP_06 => X"FFC79BFC7EE3FFFFFC001FFFFFFE3C7DFBE13FFFFFC0003FFFFFF8E1EFE70FFF",
INITP_07 => X"FFFFFC01FFFFFFFE19C7CFF3C7FFFFF803FFFFFFF9E77F3FFC7FFFFF8007FFFF",
INITP_08 => X"FFFFEFFF33CFFFFFFE003FFFFFFFFF3FFCEF3F9FFFFC007FFFFFFFC6F9F3CCF0",
INITP_09 => X"FFF80007FFFFFFFFFFFFF73C7FFFFC000FFFFFFFFFF9FF8CF1FFFFFC001FFFFF",
INITP_0A => X"FFFFFFFF3FCFFFF800003FFFFFFFFFFFFE7FFFDFFC0001FFFFFFFFFFFFF9CF9F",
INITP_0B => X"FFFC0000007FFFFFFFFFF8F8EFFFE000000FFFFFFFFFFFC7F7FFFF0000007FFF",
INITP_0C => X"FFFFFFFFFCFF3FFFF0000000FFFFFFFFFFF3FCFFFF80000007FFFFFFFFFE1E33",
INITP_0D => X"3FFFFC000003FFFFFFFFFFFFF8FFFFC000000FFFFFFFFFFFFFC3FFFE0000003F",
INITP_0E => X"FFFFFFFFFFFFF1FFFFF000007FFFFFFFFFFFFFCFFFFF000001FFFFFFFFFFFFFF",
INITP_0F => X"FFFFFFF00001FFFFFFFFFFFFFFBFFFFFC00007FFFFFFFFFFFFFE7FFFFC00001F",
INIT_00 => X"E0FEE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_01 => X"E0E000E0E0E0E0E0E0E0E0E0E0FE00000000FEFEFEFEE000FEE0FE00FEFEFEFE",
INIT_02 => X"E0E0E0E0E0E0E0E0E0E09E9E9E9EE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_03 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_04 => X"E0E0E0E0E0E0E0E0FEFE000000FEFEFEFEFEFEFE000000FEFEFEFEFEFEE0E0E0",
INIT_05 => X"E09E9E9E9E9E9E9EE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_06 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_07 => X"00FEFEFEFE00FEFEFEFEFEFEFEFEFEFE00FE00FEFEFEFEFEE0E0E0E0E0E0E0E0",
INIT_08 => X"9E9EE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E000",
INIT_09 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E",
INIT_0A => X"FEFEFE0000FEFEFEFEFEFEE00000FEFEFEE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_0B => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0FEE0E0E0E0E0E0E0E0000000FEFE00FE",
INIT_0C => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0009E9E9E9E9E9E9E00E0E0E0E0",
INIT_0D => X"FE000000FEFEFEFE00FEE0E0E0E0E0E0E0FEE0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_0E => X"E0E0E0E0E0E0E0E000E0FEFEFEE0E0E0E0E0E0E00000FEFEFEFEFEFEFE0000FE",
INIT_0F => X"E0E0E0E0E0E0E0E0E0E0E0E000009E9E9E9E9E00000000E0E0E0E0E0E0E0E0E0",
INIT_10 => X"FEFEFEE0E0E0E0E0E0E0E0E0FEE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_11 => X"E0E00000FEFEFEE0E0E0E0E0E0E00000FEFE00FEFEFEE00000FEFE000000FEFE",
INIT_12 => X"E0E0E0E000009E9E9E9E9E9E9E0000000000E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_13 => X"E0E0E000FEFEFEFEE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_14 => X"FEE0E0E0E0E0E0E00000FEFEFEFEFEE0E00000FEFEFEFEFEFEFE00FEFEFEE0E0",
INIT_15 => X"9E9E9E9E9E9E00000000000000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0000000FE",
INIT_16 => X"FEE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0009E9E",
INIT_17 => X"FEE0000000FEFEFEFEE0000000FEFEFEFEFEFE0000FEFEFEE0E0E0E00000FEFE",
INIT_18 => X"9E000000000000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E00000E0E0E0E0E0E0E0",
INIT_19 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E000009E9E9E9E9E9E9E9E",
INIT_1A => X"FEFEFEE00000FEFEFE0000FEFEFEFE00FEFEE0E0E0E0E000FEFEFEE0E0E0E0E0",
INIT_1B => X"0000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0FEFE0000FE",
INIT_1C => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E000009E9E9E9E9E9E9E9E9E9E9E9E00000000",
INIT_1D => X"FEFEFE0000FEFEFEFEFEFEFEE0E0E0FEFE00FEFEE0E0E0E0E0E0E0E0E0E0E0E0",
INIT_1E => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E00000FEFEFE0000FEFEFEFEE00000",
INIT_1F => X"E0E0E0E0E0E0E0E0009E9E9E9E9E9E9E9E9E9E9E9E9E9E000000000000E0E0E0",
INIT_20 => X"FE00FEFEFEFEE000E0FEFEFEFEFEFEE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_21 => X"E0E0E0E0E0E0E0E0E0E0E0E00000FEFEFEFEFEFEFEFEE0000000FEFEFEFE00FE",
INIT_22 => X"00009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0000000000E0E0E0E0E0E0E0E0E0",
INIT_23 => X"E000000000FEFEFEE0E0E0E0E0E0E0E000E0E0FEE0E0E0E0E0E0E0E0E0E0E0E0",
INIT_24 => X"E0E0E0E0E0E00000FEFEFEFEFEFEFEFEE0E0FEFE000000FEFEFEFE0000FEFEE0",
INIT_25 => X"9E9E9E9E9E9E9E9E9E9E9E9E000000000000E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_26 => X"FEFEFEFEE0E0E0E0E0E00000FEFEFEE0E0E0E0E0E0E0E0E0E0E0009E9E9E9E9E",
INIT_27 => X"000000FEFEFEFEFEFEFEFEE0FEFEFE0000FEFEFEFE0000FEFEE0E0E000000000",
INIT_28 => X"9E9E9E9E9E9E9E000000000000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_29 => X"E0E0FEE00000FEFEFEE0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E",
INIT_2A => X"000000FEFE0000FEFEFEFE00FEFEFEFEFEFEFEE0E0E0E00000FEFEFEFEFEFEFE",
INIT_2B => X"9E9E0000000000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E00000FEFEFE",
INIT_2C => X"FEFEE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_2D => X"000000FEFEFEFEFEFEFEFEFEFEE0E0E0E0E000FEFEFE0000FEFEFEE0FEFE0000",
INIT_2E => X"00E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0000000E0E0E00000FEFEFE",
INIT_2F => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E00000000",
INIT_30 => X"FEFEFE00FEFEFEE0E0E0E00000FEFEE000000000FEFEFEFEFEFEFEFEE0E0E0E0",
INIT_31 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0000000FEFEFE00000000FE",
INIT_32 => X"E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E000000E0E0E0E0E0E0",
INIT_33 => X"FEE0E0E0E000FEFEFEFEE000000000FE0000FEFEFEFEE0E0E0E0E0E0E0E0E0E0",
INIT_34 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0000000FEFEFEE0000000FEFEFEFEFE00FE",
INIT_35 => X"E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E0000E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_36 => X"00FEFEE0E0E0E000E0E0FE000000FEFEFEFEE0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_37 => X"E0E0E0E0E0E0E0E0E0E0000000FEFEE0E00000FEFE00FEFEFEFEE0E0E0E00000",
INIT_38 => X"E09E9E9E9E9E9E9E9E9E9E9E00E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_39 => X"E0E0E0E0FEFE000000FEFEFEFEE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_3A => X"E0E0E0E0E00000FEFEFEFE0000FEFEFE00FEFEFEFEE0E0E00000FEFEFEE0E0E0",
INIT_3B => X"9E9E9E9E9E9EE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_3C => X"E0E0000000FEFEFEFEE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E",
INIT_3D => X"000000FEFE0000FEFEE0000000E0FEE0E0E00000FEFEFEE0E0E0FEFE0000FEFE",
INIT_3E => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E000",
INIT_3F => X"FEFEFEE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9EE0",
INIT_40 => X"FEFEFEE0E00000E0E0E0E0E00000FEFEE0E00000FEFE0000FEFEFEE000000000",
INIT_41 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0000000FEE000",
INIT_42 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E00E0E0E0E0E0E0E0",
INIT_43 => X"E0E0E0E0E0E00000FEFEE000FEFEFEFE0000FEFEFEE0E0E0E00000E0E0E0E0E0",
INIT_44 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E00000FEFEFEE0E0E0",
INIT_45 => X"E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9EE0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_46 => X"0000FEFE0000FEFEFEFE0000FEFEFEE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_47 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E000FEFEFEE0E0E0E0E0E0E0E0E0",
INIT_48 => X"00009E9E9E9E9E9E9E9E9EE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_49 => X"FEFEE0E0000000FEFEE0E0FEFEFEE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E00000",
INIT_4A => X"E0E0E0E0E0E0E0E0E0E0E0E0E00000E0E0E0E0E0E0E0E0E0E0000000FEFE0000",
INIT_4B => X"9E9E9E9EE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_4C => X"00FEFEFEFEFEFEFEFEE0E0E0E0E0E0E0E0E0E0E0E0E000000000009E9E9E9E9E",
INIT_4D => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E000FEFEFE0000FEFEE0E00000",
INIT_4E => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_4F => X"FEFEFEE0E0E0E0E0E0E0E0E0E000000000009E9E9E9E9E9E9E9E9E9E9EE0E0E0",
INIT_50 => X"E0E0E0E0E0E0E0E0E0E0E0E0E00000FEFEE00000E0E0E0E0E00000FEFEFEFEFE",
INIT_51 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_52 => X"E0E0E0E0E0E00000000000009E9E9E9E9E9E9E9E9E9E00E0E0E0E0E0E0E0E0E0",
INIT_53 => X"E0E0E0E0E0E0E00000FEFEE0E0E0E0E0E0E0E0FEFEFEFEFEFEFE00E0E0E0E0E0",
INIT_54 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_55 => X"00009E9E9E9E9E9E9E9E9E9E9E9E9E9E0000E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_56 => X"0000FEFEFEE0E0E0E0E00000FEFEFEFEFEFEE0E0E0E0E0E0E0E0E0E0E0000000",
INIT_57 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_58 => X"9E9E9E9E9E9E9E9E000000000000000000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_59 => X"E0E0E0E000FEFEFEFEFEFEFEE0E0E0E0E0E0E0E0E0E0E0E00000009E9E9E9E9E",
INIT_5A => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0000000FEFEFE",
INIT_5B => X"9E9E00000000000000000000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_5C => X"FEFEFE00FEFEFEE0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_5D => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0000000FEFEFEFEE0000000",
INIT_5E => X"000000000000000000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_5F => X"FEE0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E00000000",
INIT_60 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E000000000FEFEFEE0000000E0FE0000FEFE",
INIT_61 => X"0000000000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_62 => X"E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E000000000000000000",
INIT_63 => X"E0E0E0E0E0E0E0E0E0E0E0E00000E0E0E0E0E0E0E0E00000FEFEFEE0E0E0E0E0",
INIT_64 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_65 => X"E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E00000000000000000000",
INIT_66 => X"E0E0E0E0E0E00000E0E0E0E0E0E0E0E00000FEFEFEFEE0E0E0E0E0E0E0E0E0E0",
INIT_67 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_68 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E000000000000000000E0E0E0E0E0E0",
INIT_69 => X"E0E0E0E0E0E0E0E0E0E000000000FEFEE0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E",
INIT_6A => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_6B => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E000000000000E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_6C => X"E0E0E0E0E0000000FEFEE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E",
INIT_6D => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_6E => X"9E9E9E9E9E9E9E9E9E9E00000000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_6F => X"0000FEFEFEE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E",
INIT_70 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_71 => X"9E9E9E9E9E0000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_72 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_73 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E00000FEFEFEE0",
INIT_74 => X"00E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_75 => X"E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E00",
INIT_76 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0000000FEFEFEE0E0E0E0E0E0",
INIT_77 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_78 => X"E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0000E0E0E0E0E0",
INIT_79 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E00000FEE0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_7A => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_7B => X"E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0000E0E0E0E0E0E0E0E0E0E0E0",
INIT_7C => X"E0E0E0E0E0E0E0E0E000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_7D => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_7E => X"9E9E9E9E9E9E9E9E9E9E9E9E000000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_7F => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => DOADO(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => DOPADOP(0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => addra(12),
I1 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \title2_blk_mem_gen_prim_wrapper_init__parameterized3\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \title2_blk_mem_gen_prim_wrapper_init__parameterized3\ : entity is "blk_mem_gen_prim_wrapper_init";
end \title2_blk_mem_gen_prim_wrapper_init__parameterized3\;
architecture STRUCTURE of \title2_blk_mem_gen_prim_wrapper_init__parameterized3\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"FFFFFFFFFFFFFFFF000000003FFFFFFFFFFFFFFFF8000000007FFFFFFFFFFFFF",
INITP_01 => X"FFFE00000000FE0FFFFFFFFFFFFFF000000003FE7FFFFFFFFFFFFFC00000000F",
INITP_02 => X"003FFF1FFFFFFFFFF00000001E00FFFFFFFFFFFFFF800000007C03FFFFFFFFFF",
INITP_03 => X"C07FE00000000003FFC1FFFFFF87FF80000000000FFF87FFFFFEFFFC00000000",
INITP_04 => X"000FE001FF07FC001F00000000003FE007FE3FF003FC0000000000FFE03FFCFF",
INITP_05 => X"E000000000000000F80007E01FC000480000000003E0003F80FF0000E0000000",
INITP_06 => X"000000000C000C0000000000000008000038003800000000000000380001F003",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_01 => X"9E9E9E9E9E9E000000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_02 => X"E0E0E0E0E000000000000000000000009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_03 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_04 => X"0000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_05 => X"00000000000000000000009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_06 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_07 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_08 => X"0000000000009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0000E0E0E0E0",
INIT_09 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0000000000000",
INIT_0A => X"00E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_0B => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E000000E0E0E0E0E0E0E0E0E000",
INIT_0C => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0000000000000000000000000",
INIT_0D => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_0E => X"9E9E9E9E9E9E9E9E9E9E9E9E9E000000E0E0E0E0E0E0E00000000000E0E0E0E0",
INIT_0F => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_10 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_11 => X"9E9E9E9E9E9E9E0000E0E0E0E0E00000000000000000E0E0E0E0E0E0E0E0E0E0",
INIT_12 => X"E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_13 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_14 => X"9E0000E0E0E0E0000000000000000000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_15 => X"E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_16 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_17 => X"0000009E9E9E00000000E0E0E0E0E0E0E0E0E0E0E0E0E0E0000000E0E0E0E0E0",
INIT_18 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0000000000",
INIT_19 => X"E0E0E0E0E0E0E0E0E0E0E0E0E0E0E000E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E",
INIT_1A => X"9E000000E0E0E0E0E0E0E0E0E0E0E0E0E000000000E0E0E0E0E0E0E0E0E0E0E0",
INIT_1B => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E000000000000009E9E9E9E",
INIT_1C => X"E0E0E0E0E0E0E0E0E000000000E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E",
INIT_1D => X"E0E0E0E0E0E0E0E0E0E00000000000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0",
INIT_1E => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E00000000009E9E9E9E9E9E9E9E000000E0E0",
INIT_1F => X"E0E000000000000000E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_20 => X"E0E0E000000000000000E0E0E0E0E0E0E0E0E0E0E0E00000E0E0E0E0E0E0E0E0",
INIT_21 => X"9E9E9E9E9E9E9E9E0000009E9E9E9E9E9E9E9E9E9E000000E0E0E0E0E0E0E0E0",
INIT_22 => X"000000000000E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_23 => X"0000000000E0E0E0E0E0E0E0E0E0E0000000E0E0E0E0E0E0E0E0E0E000000000",
INIT_24 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E000000E0E0E0E0E0E0E0E0E000009E0000",
INIT_25 => X"000000E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_26 => X"E0E0E0E0E0E0E0E00000000000E0E0E0E0E0E0E0E0E000000000000000000000",
INIT_27 => X"9E9E9E9E9E9E9E9E9E000000E0E0E0E0E0E0E000009E9E9E00000000000000E0",
INIT_28 => X"E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_29 => X"E000000000000000E0E0E0E0E0E0E0E09E9E0000000000000000000000000000",
INIT_2A => X"9E9E9E000000E0E0E0E0E0000000009E9E9E9E00000000000000E0E0E0E0E0E0",
INIT_2B => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_2C => X"000000E0E0E0E0E0E0E09E9E9E9E0000000000000000000000FF9E9EE09E9E9E",
INIT_2D => X"E0E0E0E0E000009E9E9E9E9E9E9E9E000000000000E0E0E0E0E0E09E9E000000",
INIT_2E => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E000000",
INIT_2F => X"E0E0E09E9E9E9E9E9E00000000000000000000009E9E9E9E9E9E9E9E9E9E9E9E",
INIT_30 => X"9E9E9E9E9E9E9E9E9E000000000000E0E0E0E0E09E9E9E00000000000000E0E0",
INIT_31 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E000000E0E0E000009E",
INIT_32 => X"9E9E9E9E9E9E0000000000000000009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_33 => X"9E9E9E9E9E0000000000E0E0E09E9E9E9E9E0000000000000000E0E0E09E9E9E",
INIT_34 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E000000E000009E9E9E9E9E9E9E9E9E",
INIT_35 => X"9E9E9E0000000000009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_36 => X"00000000E0E09E9E9E9E9E9E9E00000000000000E0E09E9E9E9E9E9E9E9E9E9E",
INIT_37 => X"9E9E9E9E9E9E9E9E9E9E9E00000000009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E00",
INIT_38 => X"9E9E009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_39 => X"9E9E9E9E9E9E9E9E0000000000009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_3A => X"9E9E9E9E9E0000009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E000000000000",
INIT_3B => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_3C => X"9E9E9E00000000009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_3D => X"009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E00000000009E9E9E9E9E9E9E",
INIT_3E => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E00",
INIT_3F => X"00009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_40 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E00009E9E9E9E9E9E9E9E9E9E9E9E9E0000",
INIT_41 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_42 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_43 => X"9E9E9E9E9E9E9E9E9E00009E9E9E9E9E9E9E9E9E9E9E9E9E0000009E9E9E9E9E",
INIT_44 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_45 => X"000000000000000000000000000000000000000000000000000000009E9E9E9E",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[10]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \douta[11]\(0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => addra(13),
I1 => addra(12),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity title2_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of title2_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end title2_blk_mem_gen_prim_width;
architecture STRUCTURE of title2_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.title2_blk_mem_gen_prim_wrapper_init
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(0) => dina(0),
douta(0) => douta(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \title2_blk_mem_gen_prim_width__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \title2_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \title2_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \title2_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_init.ram\: entity work.\title2_blk_mem_gen_prim_wrapper_init__parameterized0\
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(1 downto 0) => dina(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \title2_blk_mem_gen_prim_width__parameterized1\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \title2_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \title2_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \title2_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_init.ram\: entity work.\title2_blk_mem_gen_prim_wrapper_init__parameterized1\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
\douta[10]\(7 downto 0) => \douta[10]\(7 downto 0),
\douta[11]\(0) => \douta[11]\(0),
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \title2_blk_mem_gen_prim_width__parameterized2\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 );
DOPADOP : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \title2_blk_mem_gen_prim_width__parameterized2\ : entity is "blk_mem_gen_prim_width";
end \title2_blk_mem_gen_prim_width__parameterized2\;
architecture STRUCTURE of \title2_blk_mem_gen_prim_width__parameterized2\ is
begin
\prim_init.ram\: entity work.\title2_blk_mem_gen_prim_wrapper_init__parameterized2\
port map (
DOADO(7 downto 0) => DOADO(7 downto 0),
DOPADOP(0) => DOPADOP(0),
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \title2_blk_mem_gen_prim_width__parameterized3\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \title2_blk_mem_gen_prim_width__parameterized3\ : entity is "blk_mem_gen_prim_width";
end \title2_blk_mem_gen_prim_width__parameterized3\;
architecture STRUCTURE of \title2_blk_mem_gen_prim_width__parameterized3\ is
begin
\prim_init.ram\: entity work.\title2_blk_mem_gen_prim_wrapper_init__parameterized3\
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
\douta[10]\(7 downto 0) => \douta[10]\(7 downto 0),
\douta[11]\(0) => \douta[11]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity title2_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
clka : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of title2_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end title2_blk_mem_gen_generic_cstr;
architecture STRUCTURE of title2_blk_mem_gen_generic_cstr is
signal ena_array : STD_LOGIC_VECTOR ( 0 to 0 );
signal \ramloop[2].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_8\ : STD_LOGIC;
begin
\bindec_a.bindec_inst_a\: entity work.title2_bindec
port map (
addra(1 downto 0) => addra(13 downto 12),
ena_array(0) => ena_array(0)
);
\has_mux_a.A\: entity work.title2_blk_mem_gen_mux
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(7) => \ramloop[4].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(6) => \ramloop[4].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(5) => \ramloop[4].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(4) => \ramloop[4].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(3) => \ramloop[4].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(2) => \ramloop[4].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(1) => \ramloop[4].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(0) => \ramloop[4].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(7) => \ramloop[2].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(6) => \ramloop[2].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(5) => \ramloop[2].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(4) => \ramloop[2].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(3) => \ramloop[2].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(2) => \ramloop[2].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(1) => \ramloop[2].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(0) => \ramloop[2].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(0) => \ramloop[4].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(0) => \ramloop[2].ram.r_n_8\,
DOADO(7) => \ramloop[3].ram.r_n_0\,
DOADO(6) => \ramloop[3].ram.r_n_1\,
DOADO(5) => \ramloop[3].ram.r_n_2\,
DOADO(4) => \ramloop[3].ram.r_n_3\,
DOADO(3) => \ramloop[3].ram.r_n_4\,
DOADO(2) => \ramloop[3].ram.r_n_5\,
DOADO(1) => \ramloop[3].ram.r_n_6\,
DOADO(0) => \ramloop[3].ram.r_n_7\,
DOPADOP(0) => \ramloop[3].ram.r_n_8\,
addra(1 downto 0) => addra(13 downto 12),
clka => clka,
douta(8 downto 0) => douta(11 downto 3)
);
\ramloop[0].ram.r\: entity work.title2_blk_mem_gen_prim_width
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(0) => dina(0),
douta(0) => douta(0),
wea(0) => wea(0)
);
\ramloop[1].ram.r\: entity work.\title2_blk_mem_gen_prim_width__parameterized0\
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(1 downto 0) => dina(2 downto 1),
douta(1 downto 0) => douta(2 downto 1),
wea(0) => wea(0)
);
\ramloop[2].ram.r\: entity work.\title2_blk_mem_gen_prim_width__parameterized1\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(11 downto 3),
\douta[10]\(7) => \ramloop[2].ram.r_n_0\,
\douta[10]\(6) => \ramloop[2].ram.r_n_1\,
\douta[10]\(5) => \ramloop[2].ram.r_n_2\,
\douta[10]\(4) => \ramloop[2].ram.r_n_3\,
\douta[10]\(3) => \ramloop[2].ram.r_n_4\,
\douta[10]\(2) => \ramloop[2].ram.r_n_5\,
\douta[10]\(1) => \ramloop[2].ram.r_n_6\,
\douta[10]\(0) => \ramloop[2].ram.r_n_7\,
\douta[11]\(0) => \ramloop[2].ram.r_n_8\,
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
\ramloop[3].ram.r\: entity work.\title2_blk_mem_gen_prim_width__parameterized2\
port map (
DOADO(7) => \ramloop[3].ram.r_n_0\,
DOADO(6) => \ramloop[3].ram.r_n_1\,
DOADO(5) => \ramloop[3].ram.r_n_2\,
DOADO(4) => \ramloop[3].ram.r_n_3\,
DOADO(3) => \ramloop[3].ram.r_n_4\,
DOADO(2) => \ramloop[3].ram.r_n_5\,
DOADO(1) => \ramloop[3].ram.r_n_6\,
DOADO(0) => \ramloop[3].ram.r_n_7\,
DOPADOP(0) => \ramloop[3].ram.r_n_8\,
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(8 downto 0) => dina(11 downto 3),
wea(0) => wea(0)
);
\ramloop[4].ram.r\: entity work.\title2_blk_mem_gen_prim_width__parameterized3\
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(8 downto 0) => dina(11 downto 3),
\douta[10]\(7) => \ramloop[4].ram.r_n_0\,
\douta[10]\(6) => \ramloop[4].ram.r_n_1\,
\douta[10]\(5) => \ramloop[4].ram.r_n_2\,
\douta[10]\(4) => \ramloop[4].ram.r_n_3\,
\douta[10]\(3) => \ramloop[4].ram.r_n_4\,
\douta[10]\(2) => \ramloop[4].ram.r_n_5\,
\douta[10]\(1) => \ramloop[4].ram.r_n_6\,
\douta[10]\(0) => \ramloop[4].ram.r_n_7\,
\douta[11]\(0) => \ramloop[4].ram.r_n_8\,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity title2_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
clka : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of title2_blk_mem_gen_top : entity is "blk_mem_gen_top";
end title2_blk_mem_gen_top;
architecture STRUCTURE of title2_blk_mem_gen_top is
begin
\valid.cstr\: entity work.title2_blk_mem_gen_generic_cstr
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity title2_blk_mem_gen_v8_3_5_synth is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
clka : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of title2_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth";
end title2_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of title2_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.title2_blk_mem_gen_top
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity title2_blk_mem_gen_v8_3_5 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 11 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 11 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of title2_blk_mem_gen_v8_3_5 : entity is 14;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of title2_blk_mem_gen_v8_3_5 : entity is 14;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of title2_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of title2_blk_mem_gen_v8_3_5 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of title2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of title2_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of title2_blk_mem_gen_v8_3_5 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of title2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of title2_blk_mem_gen_v8_3_5 : entity is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of title2_blk_mem_gen_v8_3_5 : entity is "4";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of title2_blk_mem_gen_v8_3_5 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of title2_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of title2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of title2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of title2_blk_mem_gen_v8_3_5 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of title2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of title2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of title2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of title2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of title2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of title2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of title2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of title2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of title2_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 6.227751 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of title2_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of title2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of title2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of title2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of title2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of title2_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of title2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of title2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of title2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of title2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of title2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of title2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of title2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of title2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of title2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of title2_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of title2_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of title2_blk_mem_gen_v8_3_5 : entity is "title2.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of title2_blk_mem_gen_v8_3_5 : entity is "title2.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of title2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of title2_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of title2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of title2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of title2_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of title2_blk_mem_gen_v8_3_5 : entity is 10404;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of title2_blk_mem_gen_v8_3_5 : entity is 10404;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of title2_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of title2_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of title2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of title2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of title2_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of title2_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of title2_blk_mem_gen_v8_3_5 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of title2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of title2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of title2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of title2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of title2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of title2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of title2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of title2_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of title2_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of title2_blk_mem_gen_v8_3_5 : entity is 10404;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of title2_blk_mem_gen_v8_3_5 : entity is 10404;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of title2_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of title2_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of title2_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of title2_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of title2_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of title2_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of title2_blk_mem_gen_v8_3_5 : entity is "yes";
end title2_blk_mem_gen_v8_3_5;
architecture STRUCTURE of title2_blk_mem_gen_v8_3_5 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(11) <= \<const0>\;
doutb(10) <= \<const0>\;
doutb(9) <= \<const0>\;
doutb(8) <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(13) <= \<const0>\;
rdaddrecc(12) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(13) <= \<const0>\;
s_axi_rdaddrecc(12) <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.title2_blk_mem_gen_v8_3_5_synth
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity title2 is
port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of title2 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of title2 : entity is "title2,blk_mem_gen_v8_3_5,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of title2 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of title2 : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4";
end title2;
architecture STRUCTURE of title2 is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 14;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 14;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "4";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 6.227751 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "title2.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "title2.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 10404;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 10404;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 10404;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 10404;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.title2_blk_mem_gen_v8_3_5
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => B"00000000000000",
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(11 downto 0) => dina(11 downto 0),
dinb(11 downto 0) => B"000000000000",
douta(11 downto 0) => douta(11 downto 0),
doutb(11 downto 0) => NLW_U0_doutb_UNCONNECTED(11 downto 0),
eccpipece => '0',
ena => '0',
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(13 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(13 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(13 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(13 downto 0),
s_axi_rdata(11 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(11 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(11 downto 0) => B"000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
| gpl-3.0 | bc662ffac0755b7e5d22032b9a93579a | 0.721615 | 2.641471 | false | false | false | false |
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