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dangpzanco/sistemas-digitais | topocalc.vhd | 1 | 7,111 | -- Alunos: Janaína Januário Philippi
-- Daniel Gomes de Pinho Zanco
library ieee;
use ieee.std_logic_1164.all;
entity topocalc is
port ( SW : IN STD_LOGIC_VECTOR(17 downto 0);
KEY : IN STD_LOGIC_VECTOR(1 downto 0);
CLOCK_50 : IN STD_logic;
HEX0, HEX1: out std_logic_vector(0 to 6);
LEDR : OUT STD_LOGIC_VECTOR(3 downto 0);
LEDG : OUT STD_LOGIC_VECTOR(7 downto 0);
LCD_DATA: OUT STD_LOGIC_VECTOR(7 downto 0);
LCD_BLON, LCD_ON, LCD_RW, LCD_RS, LCD_EN: OUT STD_LOGIC
);
end topocalc;
architecture topo_estru of topocalc is
signal EN, SEL: std_logic_vector (1 downto 0); --signal G1 : std_logic_vector (7 downto 0);
signal F, F1, F2, F3, F4, G1, G2, SD0, SD1, SD2, P: std_logic_vector (7 downto 0); -- SD0, SD1, SD0 são os fios que irão para os Bin2BCD
signal sub, sum, FlagD, FlagM, FlagSB, FlagSM: std_LOGIC_VECTOR (3 downto 0);
signal A0,A1, A2, A3, B0, B1, B2, D0, D1, D2: std_logic_vector (3 downto 0); --- fios que vão de B2BCD para os B2A
signal h1,h2,h3,t1,t2,t3,u1,u2,u3: std_logic_vector (7 downto 0); --- fios dos Ascii para o mux
signal selection: std_logic_vector(4 downto 0);
signal sign: std_logic;
component desloca_esquerda
port (
CLK, RST, EN: in std_logic;
sr_in: in std_logic_vector(7 downto 0);
sr_out: out std_logic_vector(7 downto 0);
FlagM: out std_logic_vector(3 downto 0)
);
end component;
component desloca_direita
port (
CLK, RST, EN: in std_logic;
sr_in: in std_logic_vector(7 downto 0);
sr_out: out std_logic_vector(7 downto 0);
FlagD: out std_logic_vector(3 downto 0)
);
end component;
component mux4x1
port (w, x, y, z: in std_logic_vector(7 downto 0);
s: in std_logic_vector(1 downto 0);
m: out std_logic_vector(7 downto 0)
);
end component;
component DecodeHEX
port (I: in std_logic_vector(3 downto 0);
O: out std_logic_vector(6 downto 0)
);
end component;
component flipf
port (CLK, RST, EN: in std_logic;
D: in std_logic_vector(7 downto 0);
Q: out std_logic_vector(7 downto 0)
); -- a saída Q, vai para o LEDG e também para o bin2bcd. Fazer o que com os fios?
end component;
component FSM
port ( Clk, Rst, Enter : in std_logic;
Operacao: in std_logic_vector(1 downto 0);
Sel: out std_logic_vector(1 downto 0);
Enable_1, Enable_2: out std_logic
);
end component;
component SOMA
port (A, B: in std_logic_vector(7 downto 0);
F : out std_logic_vector(7 downto 0);
Flag: out std_logic_vector(3 downto 0)
);
end component;
component SUBT is
port (A, B: in std_logic_vector(7 downto 0);
F : out std_logic_vector(7 downto 0);
Flag: out std_logic_vector(3 downto 0)
);
end component;
component complemento2
port (entrada: in std_logic_vector(7 downto 0);
saida: out std_logic_vector(7 downto 0)
);
end component;
component bin2bcd
port (CLK, RST: in std_logic;
D : in std_logic_vector(7 downto 0);
U, T, H : out std_logic_vector(3 downto 0)
);
end component;
component B2A
port ( D : in std_logic_vector(3 downto 0);
A : out std_logic_vector(7 downto 0)
);
end component;
component mux19x1
port (H1, T1, U1, H2, T2, U2, H3, T3, U3, CTRL1, CTRL2, CTRL3: in std_logic_vector(7 downto 0);
mais, menos, vezes, barra, igual, dois, CTRLf: in std_logic_vector(7 downto 0);
s: in std_logic_vector(4 downto 0);
m: out std_logic_vector(7 downto 0)
);
end component;
component muxsign
port (w, x, y: in std_logic;
selection: in std_logic_vector(4 downto 0);
m: out std_logic
);
end component;
component FSM_LCD
port (
Clock, RST, Sign : in std_logic;
Operation : in std_logic_vector(1 downto 0);
Selection : out std_logic_vector(4 downto 0);
RS, EN : out std_logic
);
end component;
component muxLEDR is
port (w, x, y, z: in std_logic_vector(3 downto 0);
s: in std_logic_vector(1 downto 0);
m: out std_logic_vector(3 downto 0)
);
end component;
begin
--LEDR <= sub when SW(17 downto 16) = "01" else
--sum when SW(17 downto 16) = "00";
FSM1: FSM_LCD port map (CLOCK_50,KEY(0), sign, SW(17 downto 16), selection, LCD_RS, LCD_EN);
M2: muxLEDR port map (FlagSM, FlagSB, FlagD, FlagM, SW(17 downto 16), LEDR(3 downto 0)); -- FLAGS
M1: muxsign port map (SD0(7), SD1(7), SD2(7), selection, sign);-- sign é o sinal que vai do mux pro LCD_FSM
M0: mux19x1 port map (h1,t1,u1,h2,t2,u2,h3,t3,u3,"00111000","00001110","00000110","00101011","00101100","00101010","00101111","00111101","00110010","00000001", selection , LCD_DATA); --Lcd fio de saída para o LCD
--- select é a entrada para a seleção do mux, que vem da FSM 2/ deixei o 0EH!!
ASCII0: B2A port map (A0,h1); -- vem do BCD 0 vai para o mux19x1
ASCII1: B2A port map (B0,t1);
ASCII2: B2A port map (D0,u1);
ASCII3: B2A port map (A1,h2); -- vem do BCD 1 vai para o mux19x1
ASCII4: B2A port map (B1,t2);
ASCII5: B2A port map (D1,u2);
ASCII6: B2A port map (A2,h3); -- vem do BCD 2 vai para o mux19x1
ASCII7: B2A port map (B2,t3);
ASCII8: B2A port map (D2,u3);
Bcd0: bin2bcd port map (CLOCK_50, KEY(0), SD0, A0, B0, D0); -- A, B, C tem 4 bits são saídas para b2A
Bcd1: bin2bcd port map (CLOCK_50, KEY(0), SD1, A1, B1, D1);
Bcd2: bin2bcd port map (CLOCK_50, KEY(0), SD2, A2, B2, D2);
C0: complemento2 port map (P, SD0); -- registrador R3 que vai pro ledG
C1: complemento2 port map (G2, SD1); -- registrador R0 que vai para as operações
C2: complemento2 port map (SW(7 downto 0), SD2); -- entrada nas chaves
L0: FSM port map (CLOCK_50, KEY(0), KEY(1), SW(17 downto 16), SEL, EN(0), EN(1));
L1: SOMA port map (SW(7 downto 0), G2, F1, FlagSM);
L2: SUBT port map (SW(7 downto 0), G2, F2, FlagSB);
L3: desloca_direita port map (CLOCK_50, KEY(0), KEY(1), SW(7 downto 0), F3, FlagD);
L4: desloca_esquerda port map (CLOCK_50, KEY(0), KEY(1), SW(7 downto 0), F4, FlagM);
L5: mux4x1 port map (F1, F2, F3, F4, SEL, F);
R0: flipf port map (CLOCK_50, KEY(0), EN(0), SW(7 downto 0), G2);
R1: flipf port map (CLOCK_50, KEY(0), EN(1), F, G1); --a sugestão da aula 6 era usar 3 flipflops, utilizamos um de 8bit no lugar de 2 de 4bit
R3: flipf port map (CLOCK_50, KEY(0), EN(1), F, P); -- P = saída do registrador pro bin2bcd
L6: DecodeHEX port map (G1(3 downto 0), HEX0);
L7: DecodeHEX port map (G1(7 downto 4), HEX1);
LEDG(7 downto 0) <= P; -- tirei o LEDG como sinal de saída no R3, e coloquei P, pois preciso do sinal de saída para o bin2BCD
end topo_estru;
| mit | 0373100a0e5a1b6481af868068588928 | 0.595262 | 2.877841 | false | false | false | false |
FinnK/lems2hdl | work/N1_iafRefCell/ISIM_output/top_synth.vhdl | 1 | 13,007 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.fixed_float_types.ALL;
use std.textio.all;
use ieee.std_logic_textio.all; -- if you're saving this type of signal
use IEEE.numeric_std.all;
entity top_synth is
Port ( clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model: in STD_LOGIC; --SYNCHRONOUS RESET
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
step_once_complete : out STD_LOGIC; --signals to the core that a time step has finished
eventport_in_spike_aggregate : in STD_LOGIC_VECTOR(511 downto 0);
neuron_model_eventport_out_spike : out STD_LOGIC;
neuron_model_current_regimeRESTORE_stdlv : in STD_LOGIC_VECTOR(1 downto 0);
neuron_model_current_regimeCurrent_stdlv : out STD_LOGIC_VECTOR(1 downto 0);
neuron_model_param_time_refract : in sfixed (6 downto -18);
neuron_model_param_conductance_leakConductance : in sfixed (-22 downto -53);
neuron_model_param_voltage_leakReversal : in sfixed (2 downto -22);
neuron_model_param_voltage_thresh : in sfixed (2 downto -22);
neuron_model_param_voltage_reset : in sfixed (2 downto -22);
neuron_model_param_capacitance_C : in sfixed (-33 downto -47);
neuron_model_param_capacitance_inv_C_inv : in sfixed (47 downto 33);
neuron_model_exposure_voltage_v : out sfixed (2 downto -22);
neuron_model_stateCURRENT_voltage_v : out sfixed (2 downto -22);
neuron_model_stateRESTORE_voltage_v : in sfixed (2 downto -22);
neuron_model_stateCURRENT_time_lastSpikeTime : out sfixed (6 downto -18);
neuron_model_stateRESTORE_time_lastSpikeTime : in sfixed (6 downto -18);
neuron_model_param_time_SynapseModel_tauDecay : in sfixed (6 downto -18);
neuron_model_param_conductance_SynapseModel_gbase : in sfixed (-22 downto -53);
neuron_model_param_voltage_SynapseModel_erev : in sfixed (2 downto -22);
neuron_model_param_time_inv_SynapseModel_tauDecay_inv : in sfixed (18 downto -6);
neuron_model_exposure_current_SynapseModel_i : out sfixed (-28 downto -53);
neuron_model_exposure_conductance_SynapseModel_g : out sfixed (-22 downto -53);
neuron_model_stateCURRENT_conductance_SynapseModel_g : out sfixed (-22 downto -53);
neuron_model_stateRESTORE_conductance_SynapseModel_g : in sfixed (-22 downto -53);
neuron_model_stateCURRENT_current_SynapseModel_i : out sfixed (-28 downto -53);
neuron_model_stateRESTORE_current_SynapseModel_i : in sfixed (-28 downto -53);
sysparam_time_timestep : sfixed (-6 downto -22);
sysparam_time_simtime : sfixed (6 downto -22)
);
end top_synth;
architecture top of top_synth is
signal step_once_complete_int : STD_LOGIC;
signal seven_steps_done : STD_LOGIC;
signal step_once_go_int : STD_LOGIC := '0';
signal seven_steps_done_shot_done : STD_LOGIC;
signal seven_steps_done_shot : STD_LOGIC;
signal seven_steps_done_shot2 : STD_LOGIC;
signal COUNT : unsigned(2 downto 0) := "110";
signal seven_steps_done_next : STD_LOGIC;
signal COUNT_next : unsigned(2 downto 0) := "110";
signal step_once_go_int_next : STD_LOGIC := '0';
signal neuron_model_eventport_out_spike_int : STD_LOGIC;
signal neuron_model_eventport_out_spike_int2 : STD_LOGIC;
signal neuron_model_eventport_out_spike_int3 : STD_LOGIC;
component neuron_model
Port ( clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model: in STD_LOGIC; --SYNCHRONOUS RESET
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
step_once_complete : out STD_LOGIC; --signals to the core that a time step has finished
eventport_in_spike_aggregate : in STD_LOGIC_VECTOR(511 downto 0);
eventport_out_spike : out STD_LOGIC;
current_regime_in_stdlv : in STD_LOGIC_VECTOR(1 downto 0);
current_regime_out_stdlv : out STD_LOGIC_VECTOR(1 downto 0);
param_time_refract : in sfixed (6 downto -18);
param_conductance_leakConductance : in sfixed (-22 downto -53);
param_voltage_leakReversal : in sfixed (2 downto -22);
param_voltage_thresh : in sfixed (2 downto -22);
param_voltage_reset : in sfixed (2 downto -22);
param_capacitance_C : in sfixed (-33 downto -47);
param_capacitance_inv_C_inv : in sfixed (47 downto 33);
exposure_voltage_v : out sfixed (2 downto -22);
statevariable_voltage_v_out : out sfixed (2 downto -22);
statevariable_voltage_v_in : in sfixed (2 downto -22);
statevariable_time_lastSpikeTime_out : out sfixed (6 downto -18);
statevariable_time_lastSpikeTime_in : in sfixed (6 downto -18);
param_time_SynapseModel_tauDecay : in sfixed (6 downto -18);
param_conductance_SynapseModel_gbase : in sfixed (-22 downto -53);
param_voltage_SynapseModel_erev : in sfixed (2 downto -22);
param_time_inv_SynapseModel_tauDecay_inv : in sfixed (18 downto -6);
exposure_current_SynapseModel_i : out sfixed (-28 downto -53);
exposure_conductance_SynapseModel_g : out sfixed (-22 downto -53);
statevariable_conductance_SynapseModel_g_out : out sfixed (-22 downto -53);
statevariable_conductance_SynapseModel_g_in : in sfixed (-22 downto -53);
derivedvariable_current_SynapseModel_i_out : out sfixed (-28 downto -53);
derivedvariable_current_SynapseModel_i_in : in sfixed (-28 downto -53);
sysparam_time_timestep : sfixed (-6 downto -22);
sysparam_time_simtime : sfixed (6 downto -22)
);
end component;
signal neuron_model_eventport_out_spike_out : STD_LOGIC := '0';
signal neuron_model_current_regime_in_stdlv_int : STD_LOGIC_VECTOR(1 downto 0);
signal neuron_model_current_regime_out_stdlv_int : STD_LOGIC_VECTOR(1 downto 0);
signal neuron_model_statevariable_voltage_v_out_int : sfixed (2 downto -22);signal neuron_model_statevariable_voltage_v_in_int : sfixed (2 downto -22);signal neuron_model_statevariable_time_lastSpikeTime_out_int : sfixed (6 downto -18);signal neuron_model_statevariable_time_lastSpikeTime_in_int : sfixed (6 downto -18);signal neuron_model_statevariable_conductance_SynapseModel_g_out_int : sfixed (-22 downto -53);signal neuron_model_statevariable_conductance_SynapseModel_g_in_int : sfixed (-22 downto -53);signal neuron_model_derivedvariable_current_SynapseModel_i_out_int : sfixed (-28 downto -53);signal neuron_model_derivedvariable_current_SynapseModel_i_in_int : sfixed (-28 downto -53);
begin
neuron_model_uut : neuron_model
port map ( clk => clk,
init_model=> init_model,
step_once_go => step_once_go_int,
step_once_complete => step_once_complete_int,
eventport_in_spike_aggregate => eventport_in_spike_aggregate,
eventport_out_spike => neuron_model_eventport_out_spike_int ,
current_regime_in_stdlv => neuron_model_current_regime_in_stdlv_int,
current_regime_out_stdlv => neuron_model_current_regime_out_stdlv_int,
param_time_refract => neuron_model_param_time_refract ,
param_conductance_leakConductance => neuron_model_param_conductance_leakConductance ,
param_voltage_leakReversal => neuron_model_param_voltage_leakReversal ,
param_voltage_thresh => neuron_model_param_voltage_thresh ,
param_voltage_reset => neuron_model_param_voltage_reset ,
param_capacitance_C => neuron_model_param_capacitance_C ,
param_capacitance_inv_C_inv => neuron_model_param_capacitance_inv_C_inv ,
statevariable_voltage_v_out => neuron_model_statevariable_voltage_v_out_int,
statevariable_voltage_v_in => neuron_model_statevariable_voltage_v_in_int,
statevariable_time_lastSpikeTime_out => neuron_model_statevariable_time_lastSpikeTime_out_int,
statevariable_time_lastSpikeTime_in => neuron_model_statevariable_time_lastSpikeTime_in_int,
param_time_SynapseModel_tauDecay => neuron_model_param_time_SynapseModel_tauDecay ,
param_conductance_SynapseModel_gbase => neuron_model_param_conductance_SynapseModel_gbase ,
param_voltage_SynapseModel_erev => neuron_model_param_voltage_SynapseModel_erev ,
param_time_inv_SynapseModel_tauDecay_inv => neuron_model_param_time_inv_SynapseModel_tauDecay_inv ,
statevariable_conductance_SynapseModel_g_out => neuron_model_statevariable_conductance_SynapseModel_g_out_int,
statevariable_conductance_SynapseModel_g_in => neuron_model_statevariable_conductance_SynapseModel_g_in_int,
derivedvariable_current_SynapseModel_i_out => neuron_model_derivedvariable_current_SynapseModel_i_out_int,
derivedvariable_current_SynapseModel_i_in => neuron_model_derivedvariable_current_SynapseModel_i_in_int,
sysparam_time_timestep => sysparam_time_timestep,
sysparam_time_simtime => sysparam_time_simtime
);
count_proc_comb:process(init_model,step_once_complete_int,COUNT,step_once_go)
begin
seven_steps_done_next <= '0';
COUNT_next <= COUNT;
step_once_go_int_next <= '0';
if (init_model='1') then
seven_steps_done_next <= '0';
COUNT_next <= "110";
step_once_go_int_next <= '0';
else
if step_once_complete_int = '1' then
if (COUNT = "110") then
seven_steps_done_next <= '1';
COUNT_next <= "110";
step_once_go_int_next <= '0';
else
seven_steps_done_next <= '0';
COUNT_next <= COUNT + 1;
step_once_go_int_next <= '1';
end if;
elsif step_once_go = '1' then
seven_steps_done_next <= '0';
COUNT_next <= "000";
step_once_go_int_next <= '1';
else
seven_steps_done_next <= '0';
COUNT_next <= COUNT;
step_once_go_int_next <= '0';
end if;
end if;
end process count_proc_comb;
count_proc_syn:process(clk)
begin
if rising_edge(clk) then
if init_model = '1' then
COUNT <= "110";
seven_steps_done <= '1';
step_once_go_int <= '0';
else
COUNT <= COUNT_next;
seven_steps_done <= seven_steps_done_next;
step_once_go_int <= step_once_go_int_next;
end if; end if;
end process count_proc_syn;
shot_process:process(clk)
begin
if rising_edge(clk) then
if (init_model='1') then
seven_steps_done_shot <= '0';
seven_steps_done_shot_done <= '1';
else
if seven_steps_done = '1' and seven_steps_done_shot_done = '0' then
seven_steps_done_shot <= '1';
seven_steps_done_shot_done <= '1';
elsif seven_steps_done_shot = '1' then
seven_steps_done_shot <= '0';
elsif seven_steps_done = '0' then
seven_steps_done_shot <= '0';
seven_steps_done_shot_done <= '0';
end if;
end if;
end if;
end process shot_process;
store_state: process (clk)
begin
if rising_edge(clk) then
neuron_model_eventport_out_spike_int2 <= neuron_model_eventport_out_spike_int; neuron_model_eventport_out_spike_int3 <= neuron_model_eventport_out_spike_int2; seven_steps_done_shot2 <= seven_steps_done_shot; if (init_model='1') then
neuron_model_current_regime_in_stdlv_int <= neuron_model_current_regimeRESTORE_stdlv;
neuron_model_statevariable_voltage_v_in_int <= neuron_model_stateRESTORE_voltage_v;
neuron_model_statevariable_time_lastSpikeTime_in_int <= neuron_model_stateRESTORE_time_lastSpikeTime;
neuron_model_statevariable_conductance_SynapseModel_g_in_int <= neuron_model_stateRESTORE_conductance_SynapseModel_g;
neuron_model_derivedvariable_current_SynapseModel_i_in_int <= neuron_model_stateRESTORE_current_SynapseModel_i;
neuron_model_eventport_out_spike_out <= '0';
elsif (seven_steps_done_shot='1') then
neuron_model_eventport_out_spike_out <= neuron_model_eventport_out_spike_int3 ;
neuron_model_current_regime_in_stdlv_int <= neuron_model_current_regime_out_stdlv_int;
neuron_model_statevariable_voltage_v_in_int <= neuron_model_statevariable_voltage_v_out_int;
neuron_model_statevariable_time_lastSpikeTime_in_int <= neuron_model_statevariable_time_lastSpikeTime_out_int;
neuron_model_statevariable_conductance_SynapseModel_g_in_int <= neuron_model_statevariable_conductance_SynapseModel_g_out_int;
neuron_model_derivedvariable_current_SynapseModel_i_in_int <= neuron_model_derivedvariable_current_SynapseModel_i_out_int;
else
neuron_model_eventport_out_spike_out <= '0';
end if;
end if;
end process store_state;
neuron_model_current_regimeCurrent_stdlv <= neuron_model_current_regime_in_stdlv_int;
neuron_model_stateCURRENT_voltage_v <= neuron_model_statevariable_voltage_v_in_int;
neuron_model_stateCURRENT_time_lastSpikeTime <= neuron_model_statevariable_time_lastSpikeTime_in_int;
neuron_model_stateCURRENT_conductance_SynapseModel_g <= neuron_model_statevariable_conductance_SynapseModel_g_in_int;
neuron_model_stateCURRENT_current_SynapseModel_i <= neuron_model_derivedvariable_current_SynapseModel_i_in_int;
neuron_model_eventport_out_spike <= neuron_model_eventport_out_spike_out;
step_once_complete <= seven_steps_done_shot2;
end top; | lgpl-3.0 | 425ecfcf4eaf0ff2627f7e43600ad1f4 | 0.718229 | 3.091752 | false | false | false | false |
FinnK/lems2hdl | work/N1_iafRefCell/ISIM_output/testbench.vhdl | 1 | 8,996 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.fixed_float_types.ALL;
use std.textio.all;
use ieee.std_logic_textio.all; -- if you're saving this type of signal
entity tb_simulation is
end tb_simulation;
architecture tb of tb_simulation is
FILE test_out_data: TEXT open WRITE_MODE is "VHDLoutput.csv";component top_synth
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC; --SYNCHRONOUS RESET
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
step_once_complete : out STD_LOGIC; --signals to the core that a time step has finished
eventport_in_spike_aggregate : in STD_LOGIC_VECTOR(511 downto 0);
neuron_model_eventport_out_spike : out STD_LOGIC;
neuron_model_current_regimeRESTORE_stdlv : in STD_LOGIC_VECTOR(1 downto 0);
neuron_model_current_regimeCurrent_stdlv : out STD_LOGIC_VECTOR(1 downto 0);
neuron_model_param_time_refract : in sfixed (6 downto -18);
neuron_model_param_conductance_leakConductance : in sfixed (-22 downto -53);
neuron_model_param_voltage_leakReversal : in sfixed (2 downto -22);
neuron_model_param_voltage_thresh : in sfixed (2 downto -22);
neuron_model_param_voltage_reset : in sfixed (2 downto -22);
neuron_model_param_capacitance_C : in sfixed (-33 downto -47);
neuron_model_param_capacitance_inv_C_inv : in sfixed (47 downto 33);
neuron_model_exposure_voltage_v : out sfixed (2 downto -22);
neuron_model_stateCURRENT_voltage_v : out sfixed (2 downto -22);
neuron_model_stateRESTORE_voltage_v : in sfixed (2 downto -22);
neuron_model_stateCURRENT_time_lastSpikeTime : out sfixed (6 downto -18);
neuron_model_stateRESTORE_time_lastSpikeTime : in sfixed (6 downto -18);
neuron_model_param_time_SynapseModel_tauDecay : in sfixed (6 downto -18);
neuron_model_param_conductance_SynapseModel_gbase : in sfixed (-22 downto -53);
neuron_model_param_voltage_SynapseModel_erev : in sfixed (2 downto -22);
neuron_model_param_time_inv_SynapseModel_tauDecay_inv : in sfixed (18 downto -6);
neuron_model_exposure_current_SynapseModel_i : out sfixed (-28 downto -53);
neuron_model_exposure_conductance_SynapseModel_g : out sfixed (-22 downto -53);
neuron_model_stateCURRENT_conductance_SynapseModel_g : out sfixed (-22 downto -53);
neuron_model_stateRESTORE_conductance_SynapseModel_g : in sfixed (-22 downto -53);
neuron_model_stateCURRENT_current_SynapseModel_i : out sfixed (-28 downto -53);
neuron_model_stateRESTORE_current_SynapseModel_i : in sfixed (-28 downto -53);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end component;
signal clk : std_logic := '0';
signal eog : std_logic := '0';
signal init_model : std_logic := '1';
signal step_once_go : std_logic := '0';
signal step_once_complete : std_logic := '0';
signal eventport_in_spike_aggregate : STD_LOGIC_VECTOR(511 downto 0);
signal sysparam_time_simtime : sfixed ( 6 downto -22) := to_sfixed (0.0,6 , -22);
signal Errors : integer;
signal sysparam_time_timestep : sfixed (-6 downto -22) := to_sfixed( 5.0E-5 ,-6,-22);
signal neuron_model_stateCURRENT_voltage_v_int : sfixed (2 downto -22);signal neuron_model_stateCURRENT_time_lastSpikeTime_int : sfixed (6 downto -18);signal neuron_model_eventport_out_spike_internal : std_logic; signal neuron_model_stateCURRENT_conductance_SynapseModel_g_int : sfixed (-22 downto -53);signal neuron_model_stateCURRENT_current_SynapseModel_i_int : sfixed (-28 downto -53);signal neuron_model_eventport_in_SynapseModel_in_internal : std_logic; signal neuron_model_current_regimeCurrent_stdlv_internal : STD_LOGIC_VECTOR(1 downto 0);
file stimulus: TEXT open read_mode is "stimulus.csv";
begin
top_synth_uut : top_synth
port map ( clk => clk,
init_model => init_model,
step_once_go => step_once_go,
step_once_complete => step_once_complete,
eventport_in_spike_aggregate => eventport_in_spike_aggregate,
neuron_model_eventport_out_spike => neuron_model_eventport_out_spike_internal ,
neuron_model_current_regimeRESTORE_stdlv => (others => '0'),
neuron_model_current_regimeCurrent_stdlv => neuron_model_current_regimeCurrent_stdlv_internal
, neuron_model_param_time_refract => to_sfixed (0.01,6 , -18),
neuron_model_param_conductance_leakConductance => to_sfixed (3.0E-11,-22 , -53),
neuron_model_param_voltage_leakReversal => to_sfixed (-0.07,2 , -22),
neuron_model_param_voltage_thresh => to_sfixed (-0.055,2 , -22),
neuron_model_param_voltage_reset => to_sfixed (-0.07,2 , -22),
neuron_model_param_capacitance_C => to_sfixed (4.0E-12,-33 , -47),
neuron_model_param_capacitance_inv_C_inv => to_sfixed (2.49999999E11,47 , 33),
neuron_model_stateCURRENT_voltage_v => neuron_model_stateCURRENT_voltage_v_int,
neuron_model_stateRESTORE_voltage_v => to_sfixed (-0.07,2 , -22),
neuron_model_stateCURRENT_time_lastSpikeTime => neuron_model_stateCURRENT_time_lastSpikeTime_int,
neuron_model_stateRESTORE_time_lastSpikeTime => to_sfixed (0.0,6 , -18),
neuron_model_param_time_SynapseModel_tauDecay => to_sfixed (0.003,6 , -18),
neuron_model_param_conductance_SynapseModel_gbase => to_sfixed (2.5E-10,-22 , -53),
neuron_model_param_voltage_SynapseModel_erev => to_sfixed (0.0,2 , -22),
neuron_model_param_time_inv_SynapseModel_tauDecay_inv => to_sfixed (333.33334,18 , -6),
neuron_model_stateCURRENT_conductance_SynapseModel_g => neuron_model_stateCURRENT_conductance_SynapseModel_g_int,
neuron_model_stateRESTORE_conductance_SynapseModel_g => to_sfixed (0.0,-22 , -53),
neuron_model_stateCURRENT_current_SynapseModel_i => neuron_model_stateCURRENT_current_SynapseModel_i_int,
neuron_model_stateRESTORE_current_SynapseModel_i => to_sfixed (0.0,-28 , -53),
sysparam_time_timestep => sysparam_time_timestep,
sysparam_time_simtime => sysparam_time_simtime
);
receive_data: process
variable l: line;
variable char : character;
variable s : STD_LOGIC_VECTOR(0 downto 0);
begin
-- wait for Reset to complete
-- wait until init_model='1';
wait until init_model='0';
while not endfile(stimulus) loop
-- read digital data from input file
readline(stimulus, l);
read(l, s);
eventport_in_spike_aggregate(0) <= s(0);
wait until step_once_go = '1';
end loop;
assert false report "end of simulation" severity failure;
end process receive_data;
process
variable L1 : LINE;
begin
write(L1, "SimulationTime " );
write(L1, "neuron_model_spike " );
write(L1, "neuron_model_stateCURRENT_voltage_v" );
write(L1, " ");
write(L1, "neuron_model_stateCURRENT_time_lastSpikeTime" );
write(L1, " ");
write(L1, "neuron_model_stateCURRENT_conductance_SynapseModel_g" );
write(L1, " ");
write(L1, "neuron_model_stateCURRENT_current_SynapseModel_i" );
write(L1, " ");
writeline(test_out_data, L1); -- write row to output file
Wait;
end process;
clk <= not(clk) after 10 ns;
step_once_go_proc: process
begin
-- wait for Reset to complete
-- wait until init_model='1';
wait until init_model='0';
wait for 180 ns;
while 1 = 1 loop
step_once_go <= '1';
wait for 20 ns;
step_once_go <= '0';
wait until step_once_complete = '1';
wait until step_once_complete = '0';
end loop;
end process step_once_go_proc;
process
begin
wait for 20 ns;
init_model <= '1';
wait for 20 ns;
init_model <= '0';
wait;
end process ;
--
-- Print the results at each clock tick.
--
process(step_once_complete)
variable L1 : LINE;
begin
if (init_model = '1') then
sysparam_time_simtime <= to_sfixed (0.0,6, -22);
else
if (step_once_complete'event and step_once_complete = '1' and init_model = '0') then
sysparam_time_simtime <= resize(sysparam_time_simtime + sysparam_time_timestep,6, -22);
write(L1, real'image(to_real( sysparam_time_simtime ))); -- nth value in row
write(L1, " ");
if ( neuron_model_eventport_out_spike_internal = '1') then
write(L1, "1 " );
else
write(L1, "0 " );
end if;
write(L1, real'image(to_real(neuron_model_stateCURRENT_voltage_v_int)) );
write(L1, " ");
write(L1, real'image(to_real(neuron_model_stateCURRENT_time_lastSpikeTime_int)) );
write(L1, " ");
write(L1, real'image(to_real(neuron_model_stateCURRENT_conductance_SynapseModel_g_int)) );
write(L1, " ");
write(L1, real'image(to_real(neuron_model_stateCURRENT_current_SynapseModel_i_int)) );
write(L1, " ");
writeline(test_out_data, L1); -- write row to output file
end if;
end if;
end process;
end tb;
| lgpl-3.0 | 1a3c1251c8e93a40fc11c29ec13ae974 | 0.687528 | 3.026918 | false | false | false | false |
hoglet67/AtomGodilVideo | src/SID/sid_components.vhd | 1 | 2,746 | -------------------------------------------------------------------------------
--
-- SID 6581 (voice)
--
-- This piece of VHDL code describes a single SID voice (sound channel)
--
-------------------------------------------------------------------------------
-- to do: - better resolution of result signal voice, this is now only 10bits,
-- but it could be 20 !! Problem, it does not fit the PWM-dac
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
--
-- Delta-Sigma DAC
--
-- Refer to Xilinx Application Note XAPP154.
--
-- This DAC requires an external RC low-pass filter:
--
-- dac_o 0---XXXXX---+---0 analog audio
-- 3k3 |
-- === 4n7
-- |
-- GND
--
-------------------------------------------------------------------------------
--Implementation Digital to Analog converter
entity pwm_sddac is
generic (
msbi_g : integer := 9
);
port (
clk_i : in std_logic;
reset : in std_logic;
dac_i : in std_logic_vector(msbi_g downto 0);
dac_o : out std_logic
);
end pwm_sddac;
architecture rtl of pwm_sddac is
signal sig_in : unsigned(msbi_g+2 downto 0) := (others => '0');
signal dac_o_int : std_logic;
begin
seq: process (clk_i, reset)
begin
-- Disabling reset as the DC offset causes a noticable click
-- if reset = '1' then
-- sig_in <= to_unsigned(2**(msbi_g+1), sig_in'length);
-- dac_o_int <= not dac_o_int;
-- els
if rising_edge(clk_i) then
sig_in <= sig_in + unsigned(sig_in(msbi_g+2) & sig_in(msbi_g+2) & dac_i);
dac_o_int <= sig_in(msbi_g+2);
end if;
end process seq;
dac_o <= dac_o_int;
end rtl;
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
entity pwm_sdadc is
port (
clk : in std_logic; -- main clock signal (the higher the better)
reset : in std_logic; --
ADC_out : out std_logic_vector(7 downto 0); -- binary input of signal to be converted
ADC_in : in std_logic -- "analog" paddle input pin
);
end pwm_sdadc;
-- Dummy implementation (no real A/D conversion performed)
architecture rtl of pwm_sdadc is
begin
process (clk, ADC_in)
begin
if ADC_in = '1' then
ADC_out <= (others => '1');
else
ADC_out <= (others => '0');
end if;
end process;
end rtl;
| apache-2.0 | 9102ab7ba47908c6e76bbe7f41712436 | 0.475601 | 3.44542 | false | false | false | false |
sergev/vak-opensource | hardware/dlx/images-body.vhdl | 1 | 4,589 | --------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: images-body.vhdl,v $ $Revision: 1.1 $ $Date: 1993/10/25 20:46:18 $
--
--------------------------------------------------------------------------
--
-- Images package body.
--
-- Functions that return the string image of values.
-- Each image is a correctly formed literal according to the
-- rules of VHDL-93.
--
--------------------------------------------------------------------------
package body images is
-- Image of bit vector as binary bit string literal
-- (in the format B"...")
-- Length of result is bv'length + 3
function image (bv : in bit_vector) return string is
alias bv_norm : bit_vector(1 to bv'length) is bv;
variable result : string(1 to bv'length + 3);
begin
result(1) := 'B';
result(2) := '"';
for index in bv_norm'range loop
if bv_norm(index) = '0' then
result(index + 2) := '0';
else
result(index + 2) := '1';
end if;
end loop;
result(bv'length + 3) := '"';
return result;
end image;
----------------------------------------------------------------
-- Image of bit vector as octal bit string literal
-- (in the format O"...")
-- Length of result is (bv'length+2)/3 + 3
function image_octal (bv : in bit_vector) return string is
constant nr_digits : natural := (bv'length + 2) / 3;
variable result : string(1 to nr_digits + 3);
variable bits : bit_vector(0 to 3*nr_digits - 1) := (others => '0');
variable three_bits : bit_vector(0 to 2);
variable digit : character;
begin
result(1) := 'O';
result(2) := '"';
bits(bits'right - bv'length + 1 to bits'right) := bv;
for index in 0 to nr_digits - 1 loop
three_bits := bits(3*index to 3*index + 2);
case three_bits is
when b"000" =>
digit := '0';
when b"001" =>
digit := '1';
when b"010" =>
digit := '2';
when b"011" =>
digit := '3';
when b"100" =>
digit := '4';
when b"101" =>
digit := '5';
when b"110" =>
digit := '6';
when b"111" =>
digit := '7';
end case;
result(index + 3) := digit;
end loop;
result(nr_digits + 3) := '"';
return result;
end image_octal;
----------------------------------------------------------------
-- Image of bit vector as hex bit string literal
-- (in the format X"...")
-- Length of result is (bv'length+3)/4 + 3
function image_hex (bv : in bit_vector) return string is
constant nr_digits : natural := (bv'length + 3) / 4;
variable result : string(1 to nr_digits + 3);
variable bits : bit_vector(0 to 4*nr_digits - 1) := (others => '0');
variable four_bits : bit_vector(0 to 3);
variable digit : character;
begin
result(1) := 'X';
result(2) := '"';
bits(bits'right - bv'length + 1 to bits'right) := bv;
for index in 0 to nr_digits - 1 loop
four_bits := bits(4*index to 4*index + 3);
case four_bits is
when b"0000" =>
digit := '0';
when b"0001" =>
digit := '1';
when b"0010" =>
digit := '2';
when b"0011" =>
digit := '3';
when b"0100" =>
digit := '4';
when b"0101" =>
digit := '5';
when b"0110" =>
digit := '6';
when b"0111" =>
digit := '7';
when b"1000" =>
digit := '8';
when b"1001" =>
digit := '9';
when b"1010" =>
digit := 'A';
when b"1011" =>
digit := 'B';
when b"1100" =>
digit := 'C';
when b"1101" =>
digit := 'D';
when b"1110" =>
digit := 'E';
when b"1111" =>
digit := 'F';
end case;
result(index + 3) := digit;
end loop;
result(nr_digits + 3) := '"';
return result;
end image_hex;
end images;
| apache-2.0 | 13e8544b62464ba52faea6c70133a49a | 0.532142 | 3.424627 | false | false | false | false |
ShepardSiegel/ocpi | libsrc/hdl/vhd/bias_vhdl_impl.vhd | 1 | 28,038 | -- THIS FILE WAS GENERATED ON Tue Oct 30 13:46:44 2012 EDT
-- BASED ON THE FILE: bias_vhdl.xml
-- YOU PROBABLY SHOULD NOT EDIT IT
-- This file contains the implementation declarations for worker bias_vhdl
-- Interface definition signal names defined with pattern rule: "%s_"
-- OCP-based Control Interface, based on the WCI profile,
-- used for clk/reset, control and configuration
-- /\
-- /--\
-- +--------------------OCP----||----OCP---------------------------+
-- | \--/ |
-- | \/ |
-- | Entity: <worker> |
-- | |
-- O +------------------------------------------------------+ O
-- C | Entity: <worker>_worker | C
-- P | | P
-- | | This "inner layer" is the code you write, based | |
-- Data Input |\ | on definitions the in <worker>_worker_defs package, | |\ Data Output
-- Port based ==| \ | and the <worker>_worker entity, both in this file, | =| \ Port based
-- on the WSI ==| / | both in the "work" library. | =| / on the WSI
-- OCP Profile |/ | Package and entity declaration is this | |/ OCP Profile
-- O | <worker>_impl.vhd file. Architeture is in your | |
-- O | <worker>.vhd file | O
-- C | | C
-- P +------------------------------------------------------+ P
-- | |
-- | This outer layer is the "worker shell" code which |
-- | is automatically generated. The "worker shell" is |
-- | defined as the <worker> entity using definitions in |
-- | the <worker>_defs package. The worker shell is also |
-- | defined as a VHDL component in the <worker>_defs package, |
-- | as declared in the <worker>_defs.vhd file. |
-- | The worker shell "architecture" is also in this file, |
-- | as well as some subsidiary modules. |
-- +---------------------------------------------------------------+
-- This package defines types needed for the inner worker entity's generics or ports
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library ocpi;
use ocpi.all; use ocpi.types.all;
package bias_vhdl_worker_defs is
-- The following record is for the writable properties of worker "bias_vhdl"
type worker_props_write_t is record
biasValue : ULong_t;
biasValue_written : Bool_t;
end record worker_props_write_t;
-- The following two records are for the inner/worker interfaces for port "ctl"
type worker_ctl_in_t is record
clk : std_logic; -- clock for this worker
reset : Bool_t; -- reset for this worker, at least 16 clocks long
control_op : wci.control_op_t; -- control op in progress, or no_op_e
state : wci.state_t; -- wci state: see state_t
is_operating : Bool_t; -- shorthand for state = operating_e
abort_control_op : Bool_t; -- demand that slow control op finish now
is_big_endian : Bool_t; -- for endian-switchable workers
end record worker_ctl_in_t;
type worker_ctl_out_t is record
done : Bool_t; -- is the pending prop access/config op done?
attention : Bool_t; -- worker wants attention
end record worker_ctl_out_t;
-- The following two records are for the inner/worker interfaces for port "in"
type worker_in_in_t is record
reset : Bool_t; -- this port is being reset from the outside peer
ready : Bool_t; -- this port is ready for data to be taken
-- one or more of: som, eom, valid are true
data : std_logic_vector(31 downto 0);
byte_enable : std_logic_vector(3 downto 0);
som, eom, valid : Bool_t; -- valid means data and byte_enable are present
end record worker_in_in_t;
type worker_in_out_t is record
take : Bool_t; -- take data now from this port
-- can be asserted when ready is true
end record worker_in_out_t;
-- The following two records are for the inner/worker interfaces for port "out"
type worker_out_in_t is record
reset : Bool_t; -- this port is being reset from the outside peer
ready : Bool_t; -- this port is ready for data to be given
end record worker_out_in_t;
type worker_out_out_t is record
give : Bool_t; -- give data now to this port
-- can be asserted when ready is true
data : std_logic_vector(31 downto 0);
byte_enable : std_logic_vector(3 downto 0);
som, eom, valid : Bool_t; -- one or more must be true when 'give' is asserted
end record worker_out_out_t;
end package bias_vhdl_worker_defs;
-- This is the entity to be implemented, depending on the above record types.
library ocpi; use ocpi.types.all;
library work; use work.bias_vhdl_worker_defs.all;
entity bias_vhdl_worker is
port(
-- Signals for control and configuration. See record types above.
ctl_in : in worker_ctl_in_t;
ctl_out : out worker_ctl_out_t;
-- Input values and strobes for this worker's writable properties
props_write : in worker_props_write_t;
-- Signals for WSI input port named "in". See record types above.
in_in : in worker_in_in_t;
in_out : out worker_in_out_t;
-- Signals for WSI output port named "out". See record types above.
out_in : in worker_out_in_t;
out_out : out worker_out_out_t);
end entity bias_vhdl_worker;
-- The rest of the file below here is the implementation of the worker shell
-- which surrounds the entity to be implemented, above.
-- Worker-specific definitions that are needed outside entities below
package body bias_vhdl_defs is
constant worker : ocpi.wci.worker_t := (5, "00000100");
constant properties : ocpi.wci.properties_t := (
0 => (32, 0, 3, 0, 1, true, true, false, false)
);
end bias_vhdl_defs;
-- This is the entity declaration that the worker developer will implement
-- The achitecture for this entity will be in the implementation file
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library ocpi;
use ocpi.all; use ocpi.types.all;
library work;
use work.all;
use work.bias_vhdl_defs.all;
entity bias_vhdl is
port (
-- The WCI interface named "ctl", with "bias_vhdl" acting as OCP slave:
-- WIP attributes for this WCI interface are:
-- Clock: this interface has its own clock, named "ctl_Clk"
-- SizeOfConfigSpace: 4 (0x4)
-- WritableConfigProperties: true
-- ReadableConfigProperties: true
-- Sub32BitConfigProperties: false
-- ControlOperations (in addition to the required "start"):
-- ResetWhileSuspended: true
ctl_Clk : in std_logic;
ctl_MAddr : in std_logic_vector(4 downto 0);
ctl_MAddrSpace : in std_logic_vector(0 downto 0);
ctl_MCmd : in std_logic_vector(2 downto 0);
ctl_MData : in std_logic_vector(31 downto 0);
ctl_MFlag : in std_logic_vector(1 downto 0);
ctl_MReset_n : in std_logic;
ctl_SData : out std_logic_vector(31 downto 0);
ctl_SFlag : out std_logic_vector(1 downto 0);
ctl_SResp : out std_logic_vector(1 downto 0);
ctl_SThreadBusy : out std_logic_vector(0 downto 0);
-- The WSI consumer interface named "in", with "bias_vhdl" acting as OCP slave:
-- WIP attributes for this WSI interface are:
-- Clock: uses the clock from interface named "ctl"
-- Protocol: "stream32"
-- DataValueWidth: 8
-- DataValueGranularity: 1
-- DiverseDataSizes: false
-- MaxMessageValues: 16380
-- NumberOfOpcodes: 256
-- Producer: false
-- VariableMessageLength: true
-- ZeroLengthMessages: true
-- Continuous: false
-- DataWidth: 32
-- ByteWidth: 8
-- ImpreciseBurst: true
-- Preciseburst: true
-- Abortable: false
-- EarlyRequest: false
-- No Clk signal here. The "in" interface uses "ctl_Clk" as clock
in_MBurstLength : in std_logic_vector(11 downto 0);
in_MByteEn : in std_logic_vector(3 downto 0);
in_MCmd : in std_logic_vector(2 downto 0);
in_MData : in std_logic_vector(31 downto 0);
in_MBurstPrecise : in std_logic;
in_MReqInfo : in std_logic_vector(7 downto 0);
in_MReqLast : in std_logic;
in_MReset_n : in std_logic;
in_SReset_n : out std_logic;
in_SThreadBusy : out std_logic_vector(0 downto 0);
-- The WSI producer interface named "out", with "bias_vhdl" acting as OCP master:
-- WIP attributes for this WSI interface are:
-- Clock: uses the clock from interface named "ctl"
-- Protocol: "stream32"
-- DataValueWidth: 8
-- DataValueGranularity: 1
-- DiverseDataSizes: false
-- MaxMessageValues: 16380
-- NumberOfOpcodes: 256
-- Producer: true
-- VariableMessageLength: true
-- ZeroLengthMessages: true
-- Continuous: false
-- DataWidth: 32
-- ByteWidth: 8
-- ImpreciseBurst: true
-- Preciseburst: true
-- Abortable: false
-- EarlyRequest: false
-- No Clk signal here. The "out" interface uses "ctl_Clk" as clock
out_SReset_n : in std_logic;
out_SThreadBusy : in std_logic_vector(0 downto 0);
out_MBurstLength : out std_logic_vector(11 downto 0);
out_MByteEn : out std_logic_vector(3 downto 0);
out_MCmd : out std_logic_vector(2 downto 0);
out_MData : out std_logic_vector(31 downto 0);
out_MBurstPrecise : out std_logic;
out_MReqInfo : out std_logic_vector(7 downto 0);
out_MReqLast : out std_logic;
out_MReset_n : out std_logic
);
-- Aliases for WCI interface "ctl"
alias ctl_Terminate : std_logic is ctl_MFlag(0);
alias ctl_Endian : std_logic is ctl_MFlag(1);
alias ctl_Config : std_logic is ctl_MAddrSpace(0);
alias ctl_Attention : std_logic is ctl_SFlag(0);
-- Constants for bias_vhdl's property addresses
subtype Property_t is std_logic_vector(4 downto 0);
constant biasValue : Property_t := b"00000"; -- 0x00
-- Aliases for interface "in"
subtype in_OpCode_t is std_logic_vector(7 downto 0);
alias in_Opcode: in_OpCode_t is in_MReqInfo(7 downto 0);
-- Opcode/operation value declarations for protocol "stream32" on interface "in"
constant in_data_Op : in_Opcode_t := b"00000000"; -- 0x00
-- Aliases for interface "out"
subtype out_OpCode_t is std_logic_vector(7 downto 0);
alias out_Opcode: out_OpCode_t is out_MReqInfo(7 downto 0);
-- Opcode/operation value declarations for protocol "stream32" on interface "out"
constant out_data_Op : out_Opcode_t := b"00000000"; -- 0x00
signal wci_reset : bool_t;
-- these signals provide the values of writable properties
signal biasValue_value : ULong_t;
signal biasValue_written : Bool_t;
signal wci_attention, wci_is_operating: Bool_t;
signal wci_is_big_endian, wci_abort_control_op, wci_done : Bool_t;
signal wci_control_op : wci.control_op_t;
signal wci_state : wci.state_t;
signal in_take : Bool_t;
signal in_ready : Bool_t;
signal in_reset : Bool_t; -- this port is being reset from the outside
signal in_data : std_logic_vector(31 downto 0);
signal in_byte_enable: std_logic_vector(3 downto 0);
signal in_som : Bool_t; -- valid eom
signal in_eom : Bool_t; -- valid som
signal in_valid : Bool_t; -- valid data
signal out_give : Bool_t;
signal out_ready : Bool_t;
signal out_reset : Bool_t; -- this port is being reset from the outside
signal out_data : std_logic_vector(31 downto 0);
signal out_byte_enable: std_logic_vector(3 downto 0);
signal out_som : Bool_t; -- valid eom
signal out_eom : Bool_t; -- valid som
signal out_valid : Bool_t; -- valid data
end entity bias_vhdl;
-- Here we define and implement the WCI interface module for this worker,
-- which can be used by the worker implementer to avoid all the OCP/WCI issues
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library ocpi;
use ocpi.all; use ocpi.types.all;
library work;
use work.all; use work.bias_vhdl_defs.all;
entity bias_vhdl_wci is
port(
inputs : in ctl_in_t; -- signal bundle from wci interface
done : in bool_t := btrue; -- worker uses this to delay completion
attention : in bool_t := bfalse; -- worker indicates an attention condition
outputs : out wci.out_t; -- signal bundle to wci interface
reset : out bool_t; -- wci reset for worker
control_op : out wci.control_op_t; -- control op in progress, or no_op_e
state : out wci.state_t; -- wci state: see state_t
is_operating : out bool_t; -- shorthand for state==operating_e
is_big_endian : out bool_t; -- for endian-switchable workers
abort_control_op : out bool_t; -- forcible abort a control-op when
-- worker uses 'done' to delay it
-- Outputs for this worker's writable properties
biasValue_value : out ULong_t;
biasValue_written : out Bool_t
);
end entity;
architecture rtl of bias_vhdl_wci is
signal my_reset : bool_t; -- internal usage of output
-- signals for property reads and writes
signal offsets : wci.offset_a_t(0 to 0); -- offsets within each property
signal indices : wci.offset_a_t(0 to 0); -- array index for array properties
signal hi32 : bool_t; -- high word of 64 bit value
signal nbytes_1 : types.byte_offset_t; -- # bytes minus one being read/written
-- signals between the decoder and the writable property registers
signal write_enables : bool_array_t(0 to 0);
signal data : wci.data_a_t (0 to 0); -- data being written, right justified
-- signals between the decoder and the readback mux
signal read_enables : bool_array_t(0 to 0);
signal readback_data : wci.data_a_t(bias_vhdl_defs.properties'range);
-- internal signals between property registers and the readback mux
-- for those that are writable, readable, and not volatile
signal my_biasValue_value : ULong_t;
-- temp signal to workaround isim/fuse crash bug
signal wciAddr : std_logic_vector(31 downto 0);
begin
wciAddr(inputs.MAddr'range) <= inputs.MAddr;
wciAddr(31 downto inputs.MAddr'length) <= (others => '0');
outputs.SFlag(0) <= '1' when its(attention) else '0';
outputs.SFlag(1) <= '1'; -- worker is present
outputs.SThreadBusy(0) <= '0' when its(done) else '1';
my_reset <= to_bool(inputs.MReset_n = '0');
reset <= my_reset;
x : component wci.decoder
generic map(worker => bias_vhdl_defs.worker,
properties => bias_vhdl_defs.properties)
port map( ocp_in.Clk => inputs.Clk,
ocp_in.Maddr => wciAddr,
ocp_in.MAddrSpace(0) => inputs.MAddrSpace(0),
ocp_in.MByteEn => "0000",
ocp_in.MCmd => inputs.MCmd,
ocp_in.MData => inputs.MData,
ocp_in.MFlag => inputs.MFlag,
ocp_in.MReset_n => inputs.MReset_n,
done => done,
resp => outputs.SResp,
write_enables => write_enables,
read_enables => read_enables,
offsets => offsets,
indices => indices,
hi32 => hi32,
nbytes_1 => nbytes_1,
data_outputs => data,
control_op => control_op,
state => state,
is_operating => is_operating,
abort_control_op => abort_control_op,
is_big_endian => is_big_endian);
readback : component wci.readback
generic map(bias_vhdl_defs.properties)
port map( read_enables => read_enables,
data_inputs => readback_data,
data_output => outputs.SData);
biasValue : component ocpi.props.ULong_property
generic map(worker => bias_vhdl_defs.worker,
property => bias_vhdl_defs.properties(0))
port map( clk => inputs.Clk,
reset => my_reset,
write_enable => write_enables(0),
data => data(0)(31 downto 0),
value => my_biasValue_value,
written => biasValue_written);
biasValue_value <= my_biasValue_value;
biasValue_readback : component ocpi.props.read_ULong_property
generic map(worker => bias_vhdl_defs.worker,
property => bias_vhdl_defs.properties(0))
port map( value => my_biasValue_value,
data_out => readback_data(0));
end architecture rtl;
library IEEE; use IEEE.std_logic_1164.ALL; use IEEE.numeric_std.ALL;
library ocpi; use ocpi.types.all;
library work; use work.bias_vhdl_defs.all;
entity bias_vhdl_in_wsi is
port (-- Exterior OCP signals
ocp_in : in in_in_t;
ocp_out : out in_out_t;
-- Signals connected from the worker's WCI to this interface;
wci_clk : in std_logic;
wci_reset : in Bool_t;
-- Interior signals used by worker logic
reset : out Bool_t; -- this port is being reset from outside/peer
ready : out Bool_t; -- data can be taken
take : in Bool_t;
data : out std_logic_vector(31 downto 0);
byte_enable : out std_logic_vector(3 downto 0);
som, eom, valid : out Bool_t);
end entity;
architecture rtl of bias_vhdl_in_wsi is
signal fifo_full_n, fifo_empty_n : std_logic;
signal my_take, my_reset_n, my_enq : std_logic;
component FIFO2
generic (width : natural := 1; \guarded\ : natural := 1);
port( CLK : in std_logic;
RST : in std_logic;
D_IN : in std_logic_vector(width - 1 downto 0);
ENQ : in std_logic;
DEQ : in std_logic;
CLR : in std_logic;
FULL_N : out std_logic;
EMPTY_N : out std_logic;
D_OUT : out std_logic_vector(width - 1 downto 0));
end component FIFO2;
begin
my_take <= '1' when its(take) else '0';
my_enq <= '1' when ocp_in.MCmd = ocpi.ocp.MCmd_WRITE else '0';
my_reset_n <= '0' when wci_reset or (ocp_in.MReset_n = '0') else '1';
ready <= btrue when fifo_empty_n = '1' else bfalse;
fifo : FIFO2
generic map(width => 32)
port map( clk => wci_clk,
rst => my_reset_n,
d_in => ocp_in.MData,
enq => my_enq,
full_n => fifo_full_n,
d_out => data,
deq => my_take,
empty_n => fifo_empty_n,
clr => '0');
end architecture rtl;
library IEEE; use IEEE.std_logic_1164.ALL; use IEEE.numeric_std.ALL;
library ocpi; use ocpi.types.all;
library work; use work.bias_vhdl_defs.all;
entity bias_vhdl_out_wsi is
port (-- Exterior OCP signals
ocp_in : in out_in_t;
ocp_out : out out_out_t;
-- Signals connected from the worker's WCI to this interface;
wci_clk : in std_logic;
wci_reset : in Bool_t;
-- Interior signals used by worker logic
reset : out Bool_t; -- this port is being reset from outside/peer
ready : out Bool_t; -- data can be given
give : in Bool_t;
data : in std_logic_vector(31 downto 0);
byte_enable : in std_logic_vector(3 downto 0);
som, eom, valid : in Bool_t);
end entity;
architecture rtl of bias_vhdl_out_wsi is
signal my_reset : Bool_t;
begin
my_reset <= wci_reset or (ocp_in.SReset_n = '0');
reset <= my_reset;
reg: process(wci_clk) is begin
if rising_edge(wci_clk) then
if its(my_reset) then
ready <= bfalse;
else
ready <= not to_bool(ocp_in.SThreadBusy(0));
end if;
end if;
end process;
ocp_out.MCmd <= ocpi.ocp.MCmd_WRITE when its(give) else ocpi.ocp.MCmd_IDLE;
ocp_out.MData <= data;
ocp_out.MReqLast <= '1' when its(eom) else '0';
ocp_out.MBurstLength <=
std_logic_vector(to_unsigned(1,ocp_out.MBurstLength'length)) when its(eom)
else std_logic_vector(to_unsigned(2, ocp_out.MBurstLength'length));
ocp_out.MByteEn <= byte_enable;
end architecture rtl;
library IEEE; use IEEE.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.types.all; -- remove this to avoid all ocpi name collisions
architecture rtl of bias_vhdl is
signal unused : std_logic_vector(3 downto 0);
begin
-- This instantiates the WCI/Control module/entity generated in the *_impl.vhd file
-- With no user logic at all, this implements writable properties.
wci : entity bias_vhdl_wci
port map(-- These first signals are just for use by the wci module, not the worker
inputs.Clk => ctl_Clk,
inputs.MAddr => ctl_MAddr,
inputs.MAddrSpace => ctl_MAddrSpace,
inputs.MCmd => ctl_MCmd,
inputs.MData => ctl_MData,
inputs.MFlag => ctl_MFlag,
inputs.MReset_n => ctl_MReset_n,
outputs.SData => ctl_SData, outputs.SResp => ctl_SResp,
outputs.SFlag => ctl_SFlag, outputs.SThreadBusy => ctl_SThreadBusy,
-- These are outputs used by the worker logic
reset => wci_reset, -- OCP guarantees 16 clocks of reset
control_op => wci_control_op,
state => wci_state,
is_operating => wci_is_operating,
is_big_endian => wci_is_big_endian,
done => wci_done,
attention => wci_attention,
abort_control_op => wci_abort_control_op, -- use this to know when we are running
-- These are outputs to the worker for writable property values.
biasValue_value => biasValue_value,
biasValue_written => biasValue_written
);
--
-- The WSI interface helper component instance for port "in"
in_port : entity bias_vhdl_in_wsi
port map(-- These signals connect this component to the external OCP interface
ocp_in.MBurstLength => in_MBurstLength,
ocp_in.MBurstPrecise => in_MBurstPrecise,
ocp_in.MByteEn => in_MByteEn,
ocp_in.MCmd => in_MCmd,
ocp_in.MData => in_MData,
ocp_in.MReqInfo => in_MReqInfo,
ocp_in.MReqLast => in_MReqLast,
ocp_in.MReset_n => in_MReset_n,
ocp_out.SReset_n => in_SReset_n,
ocp_out.SThreadBusy => in_SThreadBusy,
-- These signals are just connected to the WCI
wci_clk => ctl_Clk,
wci_reset => wci_reset,
-- This signal is the only input from worker code
take => in_take,
-- Output signals from this component into the worker
reset => in_reset, -- this port is being reset from the outside
ready => in_ready,
data => in_data,
byte_enable => in_byte_enable,
som => in_som, -- valid eom
eom => in_eom, -- valid som
valid => in_valid); -- valid data
--
-- The WSI interface helper component instance for port "out"
out_port : entity bias_vhdl_out_wsi
port map(-- These signals connect this component to the external OCP interface
ocp_in.SReset_n => out_SReset_n,
ocp_in.SThreadBusy => out_SThreadBusy,
ocp_out.MBurstLength => out_MBurstLength,
ocp_out.MBurstPrecise => out_MBurstPrecise,
ocp_out.MByteEn => out_MByteEn,
ocp_out.MCmd => out_MCmd,
ocp_out.MData => out_MData,
ocp_out.MReqInfo => out_MReqInfo,
ocp_out.MReqLast => out_MReqLast,
ocp_out.MReset_n => out_MReset_n,
-- These signals are just connected to the WCI
wci_clk => ctl_Clk,
wci_reset => wci_reset,
-- This signal is the control input from worker code
give => out_give,
-- Output signals from this component into the worker
reset => out_reset, -- this port is being reset from the outside
ready => out_ready,
data => out_data,
byte_enable => out_byte_enable,
som => out_som, -- valid eom
eom => out_eom, -- valid som
valid => out_valid); -- valid data
bias_vhdl : entity bias_vhdl_worker
port map(
ctl_in.clk => ctl_Clk, ctl_in.reset => wci_reset,
ctl_in.control_op => wci_control_op,
ctl_in.state => wci_state,
ctl_in.is_operating => wci_is_operating,
ctl_in.abort_control_op => wci_abort_control_op,
ctl_in.is_big_endian => wci_is_big_endian,
ctl_out.done => wci_done, ctl_out.attention => wci_attention,
in_in.reset => in_reset,
in_in.ready => in_ready,
in_in.data => in_data,
in_in.byte_enable => in_byte_enable,
in_in.som => in_som,
in_in.eom => in_eom,
in_in.valid => in_valid,
in_out.take => in_take,
out_in.reset => out_reset,
out_in.ready => out_ready,
out_out.give => out_give, out_out.data => out_data,
out_out.byte_enable => out_byte_enable,
out_out.som => out_som,
out_out.eom => out_eom,
out_out.valid => out_valid,
props_write.biasValue => biasValue_value,
props_write.biasValue_written => biasValue_written);
end rtl;
| lgpl-3.0 | d539203212068ac41a39c82d63fa8ea0 | 0.544832 | 3.640826 | false | false | false | false |
Rookfighter/fft-spartan6 | fft/whole_design_tb.vhd | 1 | 6,043 | -- whole_design_tb.vhd
--
-- Created on: 17 Jul 2017
-- Author: Fabian Meyer
library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.fft_helpers.all;
entity whole_design_tb is
end entity;
architecture behavioral of whole_design_tb is
-- Component Declaration for the Unit Under Test (UUT)
component whole_design
generic(RSTDEF: std_logic := '0');
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
sda: inout std_logic; -- serial data of I2C
scl: inout std_logic); -- serial clock of I2C
end component;
-- Clock period definitions
constant clk_period: time := 10 ns;
constant BYTES: natural := 3;
constant SAMPLES: natural := 16;
constant test_data: complex_arr(0 to 15) := (
to_complex(0.0,0.0),
to_complex(1.0,0.0),
to_complex(2.0,0.0),
to_complex(3.0,0.0),
to_complex(4.0,0.0),
to_complex(5.0,0.0),
to_complex(6.0,0.0),
to_complex(7.0,0.0),
to_complex(8.0,0.0),
to_complex(9.0,0.0),
to_complex(10.0,0.0),
to_complex(11.0,0.0),
to_complex(12.0,0.0),
to_complex(13.0,0.0),
to_complex(14.0,0.0),
to_complex(15.0,0.0)
);
-- Generics
constant RSTDEF: std_logic := '0';
-- Inputs
signal rst: std_logic := RSTDEF;
signal clk: std_logic := '0';
--BiDirs
signal sda: std_logic := '1';
signal scl: std_logic := '1';
begin
-- Instantiate the Unit Under Test (UUT)
uut: whole_design
generic map(RSTDEF => RSTDEF)
port map(rst => rst,
clk => clk,
sda => sda,
scl => scl);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
-- sends a single bit over I2C
procedure send_bit(tosend: std_logic) is
begin
scl <= '0';
wait for clk_period;
sda <= tosend;
-- wait for delay element to take over new value
wait for 2*24*clk_period;
-- allow slave to read
scl <= '1';
wait for 2*clk_period;
end procedure;
-- receive a single bit over I2C
procedure recv_bit is
begin
scl <= '0';
sda <= 'Z';
wait for 2*clk_period;
scl <= '1';
wait for 2*clk_period;
end procedure;
-- sends start / repeated start condition over I2C
procedure send_start is
begin
send_bit('1');
-- rise sda without changing clk
sda <= '0';
wait for 2*25*clk_period;
end procedure;
-- sends stop condition over I2C
procedure send_stop is
begin
send_bit('0');
-- rise sda without changing clk
sda <= '1';
wait for 2*25*clk_period;
end procedure;
-- wait for an ack from slave over I2C
procedure wait_ack is
begin
send_bit('Z');
-- wait additional cycle for slave to release SDA again
scl <= '0';
wait for 2*clk_period;
end procedure;
-- send ack to slave
procedure send_ack is
begin
send_bit('0');
end procedure;
-- send nack to slave
procedure send_nack is
begin
send_bit('1');
end procedure;
procedure send_byte(data: std_logic_vector(7 downto 0)) is
begin
for i in 7 downto 0 loop
send_bit(data(i));
end loop;
wait_ack;
end;
procedure send_sample(data: signed(FIXLEN-1 downto 0)) is
variable byte_start: natural := 0;
variable byte_end: natural := 0;
begin
for i in 0 to BYTES-1 loop
byte_start := FIXLEN - (i * 8) - 1;
byte_end := FIXLEN - (i * 8) - 8;
send_byte(std_logic_vector(data(byte_start downto byte_end)));
end loop;
end;
begin
-- hold reset state for 100 ns.
wait for clk_period*10;
rst <= not RSTDEF;
-- init transmission
send_start;
-- send correct address
send_byte("01000000");
-- send OP code for reading
send_byte("00000001");
-- send samples
for i in 0 to 15 loop
send_sample(test_data(i).r);
end loop;
-- terminate transmission
send_stop;
wait for 10*clk_period;
-- init transmission
send_start;
-- send correct address
send_byte("01000000");
-- send OP code for running FFT
send_byte("00000010");
-- terminate transmission
send_stop;
wait for 50*clk_period;
-- init transmission
send_start;
-- send correct address
send_byte("01000000");
-- send OP code for reading results
send_byte("00000011");
-- repeated start
send_start;
-- send correct address with read bit
send_byte("01000001");
-- receive results
for i in 0 to 15 loop
for j in 0 to BYTES-1 loop
recv_bit; -- data bit 1
recv_bit; -- data bit 2
recv_bit; -- data bit 3
recv_bit; -- data bit 4
recv_bit; -- data bit 5
recv_bit; -- data bit 6
recv_bit; -- data bit 7
recv_bit; -- data bit 8
send_ack;
end loop;
end loop;
send_stop;
wait;
end process;
end;
| mit | a92a50419128731ac7d4456badf84566 | 0.49578 | 4.050268 | false | false | false | false |
kristofferkoch/ethersound | tb_rxsync.vhd | 1 | 5,517 | -----------------------------------------------------------------------------
-- Testbench for rxsync
--
-- Authors:
-- -- Kristoffer E. Koch
-----------------------------------------------------------------------------
-- Copyright 2008 Authors
--
-- This file is part of hwpulse.
--
-- hwpulse is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- hwpulse is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with hwpulse. If not, see <http://www.gnu.org/licenses/>.
-----------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY tb_rxsync IS
END tb_rxsync;
ARCHITECTURE behavior OF tb_rxsync IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT rxsync
PORT(
sysclk : IN std_logic;
reset : IN std_logic;
rx_clk : IN std_logic;
rxd : IN std_logic_vector(3 downto 0);
rx_dv : IN std_logic;
data : OUT std_logic_vector(7 downto 0);
data_end : OUT std_logic;
data_err : OUT std_logic;
data_dv : OUT std_logic;
debug:out std_logic_vector(7 downto 0)
);
END COMPONENT;
COMPONENT rxdecode
Port ( sysclk : in STD_LOGIC;
reset : in STD_LOGIC;
data : in STD_LOGIC_VECTOR (7 downto 0);
data_dv : in STD_LOGIC;
data_end : in STD_LOGIC;
data_err : in STD_LOGIC;
audio : out STD_LOGIC_VECTOR (23 downto 0);
audio_dv : out STD_LOGIC;
debug:out std_logic_vector(7 downto 0));
END COMPONENT;
COMPONENT deltasigmadac
PORT(
sysclk : IN std_logic;
reset : IN std_logic;
audio : IN std_logic_vector(23 downto 0);
audio_dv : IN std_logic;
audio_left : OUT std_logic;
audio_right : OUT std_logic
);
END COMPONENT;
--Inputs
signal sysclk : std_logic := '0';
signal reset : std_logic := '0';
signal rx_clk : std_logic := '0';
signal rxd : std_logic_vector(3 downto 0) := (others => '0');
signal rx_dv : std_logic := '0';
--Outputs
signal data : std_logic_vector(7 downto 0);
signal data_end : std_logic;
signal data_err : std_logic;
signal data_dv : std_logic;
-- Clock period definitions
constant sysclk_period : time := 20 ns;
constant rx_clk_period : time := 40 ns;
signal audio:std_logic_vector(23 downto 0);
signal audio_dv,audio_left, audio_right:std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: rxsync PORT MAP (
sysclk => sysclk,
reset => reset,
rx_clk => rx_clk,
rxd => rxd,
rx_dv => rx_dv,
data => data,
data_end => data_end,
data_err => data_err,
data_dv => data_dv,
debug => open
);
uut2:rxdecode PORT MAP (
sysclk => sysclk,
reset => reset,
data => data,
data_dv => data_dv,
data_end => data_end,
data_err => data_err,
audio => audio,
audio_dv => audio_dv,
debug => open
);
uut3: deltasigmadac PORT MAP (
sysclk => sysclk,
reset => reset,
audio => audio,
audio_dv => audio_dv,
audio_left => audio_left,
audio_right => audio_right
);
-- Clock process definitions
sysclk_process :process
begin
sysclk <= '0';
wait for sysclk_period/2;
sysclk <= '1';
wait for sysclk_period/2;
end process;
rx_clk_process :process
begin
rx_clk <= '0';
wait for rx_clk_period/2;
rx_clk <= '1';
wait for rx_clk_period/2;
end process;
-- Stimulus process
stim_proc: process
variable v:std_logic_vector(23 downto 0);
begin
reset <= '1';
wait for rx_clk_period*10;
reset <= '0';
wait for rx_clk_period;
rx_dv <= '1';
-- Preamble:
rxd <= x"5";wait for rx_clk_period;
rxd <= x"d";wait for rx_clk_period;
-- dest MAC:
for i in 0 to 11 loop
rxd <= x"F";wait for rx_clk_period;
end loop;
-- source MAC:
for i in 0 to 11 loop
rxd <= x"0";wait for rx_clk_period;
end loop;
-- type:
rxd <= x"8";wait for rx_clk_period;
rxd <= x"8";wait for rx_clk_period;
rxd <= x"5";wait for rx_clk_period;
rxd <= x"b";wait for rx_clk_period;
-- End command:
rxd <= x"0";wait for rx_clk_period;
rxd <= x"0";wait for rx_clk_period;
-- "Audio" data:
for c in 64 to 127 loop
v := std_logic_vector(to_unsigned(c, 7)) & "00000000000000000";
report "Sending " & integer'image(c);
rxd <= v(19 downto 16);wait for rx_clk_period;
rxd <= v(23 downto 20);wait for rx_clk_period;
rxd <= v(11 downto 8);wait for rx_clk_period;
rxd <= v(15 downto 12);wait for rx_clk_period;
rxd <= v(3 downto 0);wait for rx_clk_period;
rxd <= v(7 downto 4);wait for rx_clk_period;
end loop;
report "Sender crc";
-- "CRC":
for i in 0 to 7 loop
rxd <= x"F";wait for rx_clk_period;
end loop;
rx_dv <= '0';
report "Ferdii med sending";
wait;
end process;
END;
| gpl-3.0 | 4088ad7b330a4d6b64bf83769ca02e89 | 0.562806 | 3.347694 | false | false | false | false |
hoglet67/AtomGodilVideo | src/pointer/PointerRamBlack.vhd | 2 | 6,555 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity PointerRamBlack is
port (
clka : in std_logic;
wea : in std_logic;
addra : in std_logic_vector(7 downto 0);
dina : in std_logic_vector(7 downto 0);
douta : out std_logic_vector(7 downto 0);
clkb : in std_logic;
web : in std_logic;
addrb : in std_logic_vector(7 downto 0);
dinb : in std_logic_vector(7 downto 0);
doutb : out std_logic_vector(7 downto 0)
);
end PointerRamBlack;
architecture BEHAVIORAL of PointerRamBlack is
-- Shared memory
type ram_type is array (0 to 255) of std_logic_vector (7 downto 0);
shared variable RAM : ram_type := (
"11111111",
"10000010",
"10000100",
"10000100",
"10000010",
"10110001",
"11001010",
"10000100",
"11100000",
"10100000",
"11100000",
"00000000",
"00000000",
"00000000",
"00000000",
"00000000",
"00111100",
"01010010",
"10010001",
"10010001",
"10011101",
"10000001",
"01000010",
"00111100",
"11111111",
"10000001",
"10111111",
"10100000",
"10100000",
"10100000",
"10100000",
"11100000",
"00010000",
"00101000",
"01000100",
"11000110",
"01000100",
"01000100",
"01000100",
"01111100",
"01111100",
"01000100",
"01000100",
"01000100",
"11000110",
"01000100",
"00101000",
"00010000",
"00001000",
"11111100",
"10000010",
"10000001",
"10000010",
"11111100",
"00001000",
"00000000",
"00010000",
"00111111",
"01000001",
"10000001",
"01000001",
"00111111",
"00010000",
"00000000",
"00111100",
"01000110",
"10001101",
"10001101",
"10011001",
"10011001",
"01110010",
"00111100",
"00111000",
"01000100",
"01010100",
"01110100",
"00101000",
"00111000",
"00101000",
"00111000",
"01111100",
"01000100",
"01101100",
"00101000",
"00101000",
"01101100",
"01000100",
"01111100",
"00111000",
"00101000",
"11101110",
"10000010",
"11101110",
"00101000",
"00111000",
"00000000",
"01000000",
"10100000",
"10100000",
"10111110",
"10101011",
"10000001",
"11111111",
"01111110",
"01111110",
"11111111",
"10000001",
"10101011",
"10111110",
"10100000",
"10100000",
"01000000",
"01111110",
"11000001",
"11011110",
"11001000",
"11011000",
"11001000",
"11011000",
"01110000",
"01111110",
"10000011",
"01111011",
"00010011",
"00011011",
"00010011",
"00011011",
"00001110",
"11111111",
"01000010",
"00100100",
"00011000",
"00011000",
"00100100",
"01000010",
"11111111",
"11111111",
"01000010",
"00100100",
"00011000",
"00011000",
"00100100",
"01011010",
"11111111",
"11111111",
"01000010",
"00100100",
"00011000",
"00011000",
"00100100",
"01111110",
"11111111",
"11111111",
"01000010",
"00100100",
"00011000",
"00011000",
"00111100",
"01111110",
"11111111",
"11100000",
"10011000",
"01000110",
"00110001",
"01101011",
"01010101",
"00101001",
"00011110",
"00000111",
"00011001",
"01100010",
"10001100",
"11010110",
"10101010",
"10010100",
"01111000",
"00011110",
"00101001",
"01010101",
"01101011",
"00110001",
"01000110",
"10011000",
"11100000",
"01111000",
"10010100",
"10101010",
"11010110",
"10001100",
"01100010",
"00011001",
"00000111",
"01100110",
"10011001",
"10011001",
"11011101",
"11011101",
"10011001",
"10011001",
"01100110",
"01100110",
"11111111",
"11111111",
"10011001",
"10011001",
"10011001",
"10011001",
"01100110",
"01100110",
"10011001",
"10011001",
"10111011",
"10111011",
"10011001",
"10011001",
"01100110",
"01100110",
"10011001",
"10011001",
"10011001",
"10011001",
"11111111",
"11111111",
"01100110",
"11111111",
"10000010",
"10000100",
"10001000",
"10010000",
"10100000",
"11000000",
"10000000",
"10000000",
"11000000",
"10100000",
"10010000",
"10001000",
"10000100",
"10000010",
"11111111",
"00000001",
"00000011",
"00000101",
"00001001",
"00010001",
"00100001",
"01000001",
"11111111",
"11111111",
"01000001",
"00100001",
"00010001",
"00001001",
"00000101",
"00000011",
"00000001"
);
--attribute RAM_STYLE : string;
--attribute RAM_STYLE of RAM: signal is "BLOCK";
begin
process (clka)
begin
if rising_edge(clka) then
if (wea = '1') then
RAM(conv_integer(addra(7 downto 0))) := dina;
end if;
douta <= RAM(conv_integer(addra(7 downto 0)));
end if;
end process;
process (clkb)
begin
if rising_edge(clkb) then
if (web = '1') then
RAM(conv_integer(addrb(7 downto 0))) := dinb;
end if;
doutb <= RAM(conv_integer(addrb(7 downto 0)));
end if;
end process;
end BEHAVIORAL;
| apache-2.0 | de40335e403840685083daa570a9674d | 0.433105 | 4.62597 | false | false | false | false |
sergev/vak-opensource | hardware/dlx/memory_test-bench.vhdl | 1 | 10,707 | --------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: memory_test-bench.vhdl,v $ $Revision: 2.1 $ $Date: 1993/10/31 21:10:12 $
--
--------------------------------------------------------------------------
--
-- Architecture for test bench for behavioural architecture of memory
--
use std.textio.all,
work.dlx_types.all,
work.mem_types.all,
work.bv_arithmetic.bv_addu,
work.images.image_hex;
architecture bench of memory_test is
component clock_gen
port (phi1, phi2 : out bit;
reset : out bit);
end component;
component memory
port (phi1, phi2 : in bit;
a : in dlx_address;
d : inout dlx_word_bus bus;
width : in mem_width;
write_enable : in bit;
burst : in bit;
mem_enable : in bit;
ready : out bit);
end component;
for cg : clock_gen
use entity work.clock_gen(behaviour)
generic map (Tpw => 8 ns, Tps => 2 ns);
for mem : memory
use entity work.memory(behaviour)
generic map (mem_size => 65536,
Tac1 => 95 ns, Tacb => 15 ns, Tpd_clk_out => 2 ns);
signal phi1, phi2, reset : bit;
signal a : dlx_address;
signal d : dlx_word_bus bus;
signal width : mem_width;
signal write_enable, mem_enable, burst, ifetch, ready : bit;
begin
cg : clock_gen
port map (phi1, phi2, reset);
mem : memory
port map (phi1, phi2, a, d, width, write_enable, burst, mem_enable, ready);
test: process
variable data_word : dlx_word;
variable L : line;
VARIABLE blk : dlx_word_array(1 to 4);
procedure write (address : in dlx_address;
data_width : in mem_width;
data : in dlx_word;
Tpd_clk_out : in time -- clock to output delay
) is
begin -- write
wait until phi1 = '1';
if reset = '1' then
return;
end if;
a <= address after Tpd_clk_out;
width <= data_width after Tpd_clk_out;
d <= data after Tpd_clk_out;
write_enable <= '1' after Tpd_clk_out;
burst <= '0' after Tpd_Clk_Out;
mem_enable <= '1' after Tpd_clk_out;
ifetch <= '0' after Tpd_clk_out;
loop
wait until phi2 = '0';
exit when ready = '1' or reset = '1';
end loop;
d <= null after Tpd_clk_out;
write_enable <= '0' after Tpd_clk_out;
mem_enable <= '0' after Tpd_clk_out;
end write;
procedure read (address : in dlx_address;
data_width : in mem_width;
instr_fetch : in boolean;
data : out dlx_word;
Tpd_clk_out : in time -- clock to output delay
) is
begin -- read
wait until phi1 = '1';
if reset = '1' then
return;
end if;
a <= address after Tpd_clk_out;
width <= data_width after Tpd_clk_out;
write_enable <= '0' after Tpd_clk_out;
burst <= '0' after Tpd_Clk_Out;
mem_enable <= '1' after Tpd_clk_out;
ifetch <= bit'val(boolean'pos(instr_fetch)) after Tpd_clk_out;
loop
wait until phi2 = '0';
exit when ready = '1' or reset = '1';
end loop;
data := d;
mem_enable <= '0' after Tpd_clk_out;
end read;
procedure write_burst (address : in dlx_address;
data : in dlx_word_array;
Tpd_clk_out : in time -- clock to output delay
) is
VARIABLE next_address : dlx_address := address;
VARIABLE ignore_overflow : boolean;
VARIABLE index : natural;
begin -- write_burst
wait until phi1 = '1';
if reset = '1' then
return;
end if;
width <= width_word after Tpd_clk_out;
write_enable <= '1' after Tpd_clk_out;
mem_enable <= '1' after Tpd_clk_out;
ifetch <= '0' after Tpd_clk_out;
burst <= '1' after Tpd_Clk_Out;
index := data'left;
burst_loop : LOOP
IF (index = data'right) THEN
burst <= '0' after Tpd_Clk_Out;
END IF;
a <= next_address after Tpd_clk_out;
d <= data(index) after Tpd_clk_out;
wait_loop : LOOP
WAIT UNTIL phi2 = '0';
EXIT burst_loop WHEN reset = '1' OR (ready = '1' AND index = data'right);
EXIT wait_loop WHEN ready = '1';
END LOOP wait_loop;
index := index + 1;
bv_addu(next_address, X"00000004", next_address, ignore_overflow);
END LOOP burst_loop;
d <= null after Tpd_clk_out;
write_enable <= '0' after Tpd_clk_out;
mem_enable <= '0' after Tpd_clk_out;
end write_burst;
procedure read_burst (address : in dlx_address;
data : out dlx_word_array;
Tpd_clk_out : in time -- clock to output delay
) is
VARIABLE next_address : dlx_address := address;
VARIABLE ignore_overflow : boolean;
VARIABLE index : natural;
begin -- read_burst
wait until phi1 = '1';
if reset = '1' then
return;
end if;
width <= width_word after Tpd_clk_out;
write_enable <= '0' after Tpd_clk_out;
mem_enable <= '1' after Tpd_clk_out;
ifetch <= '0' after Tpd_clk_out;
burst <= '1' after Tpd_Clk_Out;
index := data'left;
burst_loop : LOOP
IF (index = data'right) THEN
burst <= '0' after Tpd_Clk_Out;
END IF;
a <= next_address after Tpd_clk_out;
wait_loop : LOOP
WAIT UNTIL phi2 = '0';
data(index) := d;
EXIT burst_loop WHEN reset = '1' OR (ready = '1' AND index = data'right);
EXIT wait_loop WHEN ready = '1';
END LOOP wait_loop;
index := index + 1;
bv_addu(next_address, X"00000004", next_address, ignore_overflow);
END LOOP burst_loop;
mem_enable <= '0' after Tpd_clk_out;
end read_burst;
begin
wait until reset = '0';
write(L, string'("Write word X""00000004"" to 4:"));
writeline(output, L);
write(X"0000_0004", width_word, X"00000004", 2 ns);
--
write(L, string'("Read word from X""00000004"":"));
writeline(output, L);
data_word := X"0000_0000";
read(X"0000_0004", width_word, false, data_word, 2 ns);
write(L, string'(" result:"));
write(L, image_hex(data_word));
writeline(output, L);
--
write(L, string'("Write halfword X""2222"" to 0:"));
writeline(output, L);
write(X"0000_0000", width_halfword, X"2222_0000", 2 ns);
--
write(L, string'("Write halfword X""3333"" to 2:"));
writeline(output, L);
write(X"0000_0002", width_halfword, X"0000_3333", 2 ns);
--
write(L, string'("Read word from X""00000000"":"));
writeline(output, L);
data_word := X"0000_0000";
read(X"0000_0000", width_word, false, data_word, 2 ns);
write(L, string'(" result:"));
write(L, image_hex(data_word));
writeline(output, L);
--
write(L, string'("Read halfword from X""00000003"":"));
writeline(output, L);
data_word := X"0000_0000";
read(X"0000_0003", width_halfword, false, data_word, 2 ns);
write(L, string'(" result:"));
write(L, image_hex(data_word));
writeline(output, L);
--
write(L, string'("Write bytes X""44"" to 4, X""55"" to 5, X""66"" to 6, X""77"" to 7:"));
writeline(output, L);
write(X"0000_0004", width_byte, X"44_00_00_00", 2 ns);
write(X"0000_0005", width_byte, X"00_55_00_00", 2 ns);
write(X"0000_0006", width_byte, X"00_00_66_00", 2 ns);
write(X"0000_0007", width_byte, X"00_00_00_77", 2 ns);
--
write(L, string'("Read word from X""00000004"":"));
writeline(output, L);
data_word := X"0000_0000";
read(X"0000_0004", width_word, false, data_word, 2 ns);
write(L, string'(" result:"));
write(L, image_hex(data_word));
writeline(output, L);
--
write(L, string'("Read byte from X""00000004"":"));
writeline(output, L);
data_word := X"0000_0000";
read(X"0000_0004", width_byte, false, data_word, 2 ns);
write(L, string'(" result:"));
write(L, image_hex(data_word));
writeline(output, L);
--
write(L, string'("Read byte from X""00000005"":"));
writeline(output, L);
data_word := X"0000_0000";
read(X"0000_0005", width_byte, false, data_word, 2 ns);
write(L, string'(" result:"));
write(L, image_hex(data_word));
writeline(output, L);
--
write(L, string'("Read byte from X""00000006"":"));
writeline(output, L);
data_word := X"0000_0000";
read(X"0000_0006", width_byte, false, data_word, 2 ns);
write(L, string'(" result:"));
write(L, image_hex(data_word));
writeline(output, L);
--
write(L, string'("Read byte from X""00000007"":"));
writeline(output, L);
data_word := X"0000_0000";
read(X"0000_0007", width_byte, false, data_word, 2 ns);
write(L, string'(" result:"));
write(L, image_hex(data_word));
writeline(output, L);
--
write(L, string'("Write burst to 8..11:"));
writeline(output, L);
blk := (X"88888888", X"99999999", X"AAAAAAAA", X"BBBBBBBB");
write_burst(X"0000_0008", blk, 2 ns);
--
write(L, string'("Read burst from 8..11:"));
writeline(output, L);
blk := (OTHERS => X"0000_0000");
read_burst(X"0000_0008", blk, 2 ns);
write(L, string'(" result: ("));
FOR i IN blk'range LOOP
write(L, image_hex(blk(i)));
IF (i /= blk'right) THEN
write(L, string'(", "));
END IF;
END LOOP; -- i
write(L, ')');
writeline(output, L);
--
-- This should hang
write(L, string'("Read word from X""00100000"":"));
writeline(output, L);
data_word := X"0000_0000";
read(X"0010_0000", width_word, false, data_word, 2 ns);
write(L, string'(" result:"));
write(L, data_word);
writeline(output, L);
--
end process test;
end bench;
| apache-2.0 | 90592fb3803493b5628868319b2e6195 | 0.56337 | 3.402288 | false | false | false | false |
hoglet67/AtomGodilVideo | src/MC6847/CharRom.vhd | 2 | 48,459 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity CharRom is
port (
CLK : in std_logic;
ADDR : in std_logic_vector(10 downto 0);
DATA : out std_logic_vector(7 downto 0)
);
end;
architecture BEHAVIOURAL of CharRom is
signal rom_addr : std_logic_vector(9 downto 0);
begin
p_addr : process(ADDR)
begin
rom_addr <= (others => '0');
rom_addr(9 downto 0) <= ADDR(9 downto 0);
end process;
p_rom : process
begin
wait until rising_edge(CLK);
DATA <= (others => '0');
if rom_addr(9 downto 8) = "00" then
case rom_addr(7 downto 0) is
when x"00" => DATA <= x"00";
when x"01" => DATA <= x"00";
when x"02" => DATA <= x"00";
when x"03" => DATA <= x"1C";
when x"04" => DATA <= x"22";
when x"05" => DATA <= x"02";
when x"06" => DATA <= x"1A";
when x"07" => DATA <= x"2A";
when x"08" => DATA <= x"2A";
when x"09" => DATA <= x"1C";
when x"0A" => DATA <= x"00";
when x"0B" => DATA <= x"00";
when x"0C" => DATA <= x"00";
when x"0D" => DATA <= x"00";
when x"0E" => DATA <= x"00";
when x"0F" => DATA <= x"00";
when x"10" => DATA <= x"00";
when x"11" => DATA <= x"00";
when x"12" => DATA <= x"00";
when x"13" => DATA <= x"08";
when x"14" => DATA <= x"14";
when x"15" => DATA <= x"22";
when x"16" => DATA <= x"22";
when x"17" => DATA <= x"3E";
when x"18" => DATA <= x"22";
when x"19" => DATA <= x"22";
when x"1A" => DATA <= x"00";
when x"1B" => DATA <= x"00";
when x"1C" => DATA <= x"00";
when x"1D" => DATA <= x"00";
when x"1E" => DATA <= x"00";
when x"1F" => DATA <= x"00";
when x"20" => DATA <= x"00";
when x"21" => DATA <= x"00";
when x"22" => DATA <= x"00";
when x"23" => DATA <= x"3C";
when x"24" => DATA <= x"12";
when x"25" => DATA <= x"12";
when x"26" => DATA <= x"1C";
when x"27" => DATA <= x"12";
when x"28" => DATA <= x"12";
when x"29" => DATA <= x"3C";
when x"2A" => DATA <= x"00";
when x"2B" => DATA <= x"00";
when x"2C" => DATA <= x"00";
when x"2D" => DATA <= x"00";
when x"2E" => DATA <= x"00";
when x"2F" => DATA <= x"00";
when x"30" => DATA <= x"00";
when x"31" => DATA <= x"00";
when x"32" => DATA <= x"00";
when x"33" => DATA <= x"1C";
when x"34" => DATA <= x"22";
when x"35" => DATA <= x"20";
when x"36" => DATA <= x"20";
when x"37" => DATA <= x"20";
when x"38" => DATA <= x"22";
when x"39" => DATA <= x"1C";
when x"3A" => DATA <= x"00";
when x"3B" => DATA <= x"00";
when x"3C" => DATA <= x"00";
when x"3D" => DATA <= x"00";
when x"3E" => DATA <= x"00";
when x"3F" => DATA <= x"00";
when x"40" => DATA <= x"00";
when x"41" => DATA <= x"00";
when x"42" => DATA <= x"00";
when x"43" => DATA <= x"3C";
when x"44" => DATA <= x"12";
when x"45" => DATA <= x"12";
when x"46" => DATA <= x"12";
when x"47" => DATA <= x"12";
when x"48" => DATA <= x"12";
when x"49" => DATA <= x"3C";
when x"4A" => DATA <= x"00";
when x"4B" => DATA <= x"00";
when x"4C" => DATA <= x"00";
when x"4D" => DATA <= x"00";
when x"4E" => DATA <= x"00";
when x"4F" => DATA <= x"00";
when x"50" => DATA <= x"00";
when x"51" => DATA <= x"00";
when x"52" => DATA <= x"00";
when x"53" => DATA <= x"3E";
when x"54" => DATA <= x"20";
when x"55" => DATA <= x"20";
when x"56" => DATA <= x"38";
when x"57" => DATA <= x"20";
when x"58" => DATA <= x"20";
when x"59" => DATA <= x"3E";
when x"5A" => DATA <= x"00";
when x"5B" => DATA <= x"00";
when x"5C" => DATA <= x"00";
when x"5D" => DATA <= x"00";
when x"5E" => DATA <= x"00";
when x"5F" => DATA <= x"00";
when x"60" => DATA <= x"00";
when x"61" => DATA <= x"00";
when x"62" => DATA <= x"00";
when x"63" => DATA <= x"3E";
when x"64" => DATA <= x"20";
when x"65" => DATA <= x"20";
when x"66" => DATA <= x"38";
when x"67" => DATA <= x"20";
when x"68" => DATA <= x"20";
when x"69" => DATA <= x"20";
when x"6A" => DATA <= x"00";
when x"6B" => DATA <= x"00";
when x"6C" => DATA <= x"00";
when x"6D" => DATA <= x"00";
when x"6E" => DATA <= x"00";
when x"6F" => DATA <= x"00";
when x"70" => DATA <= x"00";
when x"71" => DATA <= x"00";
when x"72" => DATA <= x"00";
when x"73" => DATA <= x"1E";
when x"74" => DATA <= x"20";
when x"75" => DATA <= x"20";
when x"76" => DATA <= x"26";
when x"77" => DATA <= x"22";
when x"78" => DATA <= x"22";
when x"79" => DATA <= x"1E";
when x"7A" => DATA <= x"00";
when x"7B" => DATA <= x"00";
when x"7C" => DATA <= x"00";
when x"7D" => DATA <= x"00";
when x"7E" => DATA <= x"00";
when x"7F" => DATA <= x"00";
when x"80" => DATA <= x"00";
when x"81" => DATA <= x"00";
when x"82" => DATA <= x"00";
when x"83" => DATA <= x"22";
when x"84" => DATA <= x"22";
when x"85" => DATA <= x"22";
when x"86" => DATA <= x"3E";
when x"87" => DATA <= x"22";
when x"88" => DATA <= x"22";
when x"89" => DATA <= x"22";
when x"8A" => DATA <= x"00";
when x"8B" => DATA <= x"00";
when x"8C" => DATA <= x"00";
when x"8D" => DATA <= x"00";
when x"8E" => DATA <= x"00";
when x"8F" => DATA <= x"00";
when x"90" => DATA <= x"00";
when x"91" => DATA <= x"00";
when x"92" => DATA <= x"00";
when x"93" => DATA <= x"1C";
when x"94" => DATA <= x"08";
when x"95" => DATA <= x"08";
when x"96" => DATA <= x"08";
when x"97" => DATA <= x"08";
when x"98" => DATA <= x"08";
when x"99" => DATA <= x"1C";
when x"9A" => DATA <= x"00";
when x"9B" => DATA <= x"00";
when x"9C" => DATA <= x"00";
when x"9D" => DATA <= x"00";
when x"9E" => DATA <= x"00";
when x"9F" => DATA <= x"00";
when x"A0" => DATA <= x"00";
when x"A1" => DATA <= x"00";
when x"A2" => DATA <= x"00";
when x"A3" => DATA <= x"02";
when x"A4" => DATA <= x"02";
when x"A5" => DATA <= x"02";
when x"A6" => DATA <= x"02";
when x"A7" => DATA <= x"22";
when x"A8" => DATA <= x"22";
when x"A9" => DATA <= x"1C";
when x"AA" => DATA <= x"00";
when x"AB" => DATA <= x"00";
when x"AC" => DATA <= x"00";
when x"AD" => DATA <= x"00";
when x"AE" => DATA <= x"00";
when x"AF" => DATA <= x"00";
when x"B0" => DATA <= x"00";
when x"B1" => DATA <= x"00";
when x"B2" => DATA <= x"00";
when x"B3" => DATA <= x"22";
when x"B4" => DATA <= x"24";
when x"B5" => DATA <= x"28";
when x"B6" => DATA <= x"30";
when x"B7" => DATA <= x"28";
when x"B8" => DATA <= x"24";
when x"B9" => DATA <= x"22";
when x"BA" => DATA <= x"00";
when x"BB" => DATA <= x"00";
when x"BC" => DATA <= x"00";
when x"BD" => DATA <= x"00";
when x"BE" => DATA <= x"00";
when x"BF" => DATA <= x"00";
when x"C0" => DATA <= x"00";
when x"C1" => DATA <= x"00";
when x"C2" => DATA <= x"00";
when x"C3" => DATA <= x"20";
when x"C4" => DATA <= x"20";
when x"C5" => DATA <= x"20";
when x"C6" => DATA <= x"20";
when x"C7" => DATA <= x"20";
when x"C8" => DATA <= x"20";
when x"C9" => DATA <= x"3E";
when x"CA" => DATA <= x"00";
when x"CB" => DATA <= x"00";
when x"CC" => DATA <= x"00";
when x"CD" => DATA <= x"00";
when x"CE" => DATA <= x"00";
when x"CF" => DATA <= x"00";
when x"D0" => DATA <= x"00";
when x"D1" => DATA <= x"00";
when x"D2" => DATA <= x"00";
when x"D3" => DATA <= x"22";
when x"D4" => DATA <= x"36";
when x"D5" => DATA <= x"2A";
when x"D6" => DATA <= x"2A";
when x"D7" => DATA <= x"22";
when x"D8" => DATA <= x"22";
when x"D9" => DATA <= x"22";
when x"DA" => DATA <= x"00";
when x"DB" => DATA <= x"00";
when x"DC" => DATA <= x"00";
when x"DD" => DATA <= x"00";
when x"DE" => DATA <= x"00";
when x"DF" => DATA <= x"00";
when x"E0" => DATA <= x"00";
when x"E1" => DATA <= x"00";
when x"E2" => DATA <= x"00";
when x"E3" => DATA <= x"22";
when x"E4" => DATA <= x"32";
when x"E5" => DATA <= x"2A";
when x"E6" => DATA <= x"26";
when x"E7" => DATA <= x"22";
when x"E8" => DATA <= x"22";
when x"E9" => DATA <= x"22";
when x"EA" => DATA <= x"00";
when x"EB" => DATA <= x"00";
when x"EC" => DATA <= x"00";
when x"ED" => DATA <= x"00";
when x"EE" => DATA <= x"00";
when x"EF" => DATA <= x"00";
when x"F0" => DATA <= x"00";
when x"F1" => DATA <= x"00";
when x"F2" => DATA <= x"00";
when x"F3" => DATA <= x"3E";
when x"F4" => DATA <= x"22";
when x"F5" => DATA <= x"22";
when x"F6" => DATA <= x"22";
when x"F7" => DATA <= x"22";
when x"F8" => DATA <= x"22";
when x"F9" => DATA <= x"3E";
when x"FA" => DATA <= x"00";
when x"FB" => DATA <= x"00";
when x"FC" => DATA <= x"00";
when x"FD" => DATA <= x"00";
when x"FE" => DATA <= x"00";
when x"FF" => DATA <= x"00";
when others => DATA <= (others => '0');
end case;
end if;
if rom_addr(9 downto 8) = "01" then
case rom_addr(7 downto 0) is
when x"00" => DATA <= x"00";
when x"01" => DATA <= x"00";
when x"02" => DATA <= x"00";
when x"03" => DATA <= x"3C";
when x"04" => DATA <= x"22";
when x"05" => DATA <= x"22";
when x"06" => DATA <= x"3C";
when x"07" => DATA <= x"20";
when x"08" => DATA <= x"20";
when x"09" => DATA <= x"20";
when x"0A" => DATA <= x"00";
when x"0B" => DATA <= x"00";
when x"0C" => DATA <= x"00";
when x"0D" => DATA <= x"00";
when x"0E" => DATA <= x"00";
when x"0F" => DATA <= x"00";
when x"10" => DATA <= x"00";
when x"11" => DATA <= x"00";
when x"12" => DATA <= x"00";
when x"13" => DATA <= x"1C";
when x"14" => DATA <= x"22";
when x"15" => DATA <= x"22";
when x"16" => DATA <= x"22";
when x"17" => DATA <= x"2A";
when x"18" => DATA <= x"24";
when x"19" => DATA <= x"1A";
when x"1A" => DATA <= x"00";
when x"1B" => DATA <= x"00";
when x"1C" => DATA <= x"00";
when x"1D" => DATA <= x"00";
when x"1E" => DATA <= x"00";
when x"1F" => DATA <= x"00";
when x"20" => DATA <= x"00";
when x"21" => DATA <= x"00";
when x"22" => DATA <= x"00";
when x"23" => DATA <= x"3C";
when x"24" => DATA <= x"22";
when x"25" => DATA <= x"22";
when x"26" => DATA <= x"3C";
when x"27" => DATA <= x"28";
when x"28" => DATA <= x"24";
when x"29" => DATA <= x"22";
when x"2A" => DATA <= x"00";
when x"2B" => DATA <= x"00";
when x"2C" => DATA <= x"00";
when x"2D" => DATA <= x"00";
when x"2E" => DATA <= x"00";
when x"2F" => DATA <= x"00";
when x"30" => DATA <= x"00";
when x"31" => DATA <= x"00";
when x"32" => DATA <= x"00";
when x"33" => DATA <= x"1C";
when x"34" => DATA <= x"22";
when x"35" => DATA <= x"10";
when x"36" => DATA <= x"08";
when x"37" => DATA <= x"04";
when x"38" => DATA <= x"22";
when x"39" => DATA <= x"1C";
when x"3A" => DATA <= x"00";
when x"3B" => DATA <= x"00";
when x"3C" => DATA <= x"00";
when x"3D" => DATA <= x"00";
when x"3E" => DATA <= x"00";
when x"3F" => DATA <= x"00";
when x"40" => DATA <= x"00";
when x"41" => DATA <= x"00";
when x"42" => DATA <= x"00";
when x"43" => DATA <= x"3E";
when x"44" => DATA <= x"08";
when x"45" => DATA <= x"08";
when x"46" => DATA <= x"08";
when x"47" => DATA <= x"08";
when x"48" => DATA <= x"08";
when x"49" => DATA <= x"08";
when x"4A" => DATA <= x"00";
when x"4B" => DATA <= x"00";
when x"4C" => DATA <= x"00";
when x"4D" => DATA <= x"00";
when x"4E" => DATA <= x"00";
when x"4F" => DATA <= x"00";
when x"50" => DATA <= x"00";
when x"51" => DATA <= x"00";
when x"52" => DATA <= x"00";
when x"53" => DATA <= x"22";
when x"54" => DATA <= x"22";
when x"55" => DATA <= x"22";
when x"56" => DATA <= x"22";
when x"57" => DATA <= x"22";
when x"58" => DATA <= x"22";
when x"59" => DATA <= x"1C";
when x"5A" => DATA <= x"00";
when x"5B" => DATA <= x"00";
when x"5C" => DATA <= x"00";
when x"5D" => DATA <= x"00";
when x"5E" => DATA <= x"00";
when x"5F" => DATA <= x"00";
when x"60" => DATA <= x"00";
when x"61" => DATA <= x"00";
when x"62" => DATA <= x"00";
when x"63" => DATA <= x"22";
when x"64" => DATA <= x"22";
when x"65" => DATA <= x"22";
when x"66" => DATA <= x"14";
when x"67" => DATA <= x"14";
when x"68" => DATA <= x"08";
when x"69" => DATA <= x"08";
when x"6A" => DATA <= x"00";
when x"6B" => DATA <= x"00";
when x"6C" => DATA <= x"00";
when x"6D" => DATA <= x"00";
when x"6E" => DATA <= x"00";
when x"6F" => DATA <= x"00";
when x"70" => DATA <= x"00";
when x"71" => DATA <= x"00";
when x"72" => DATA <= x"00";
when x"73" => DATA <= x"22";
when x"74" => DATA <= x"22";
when x"75" => DATA <= x"22";
when x"76" => DATA <= x"2A";
when x"77" => DATA <= x"2A";
when x"78" => DATA <= x"36";
when x"79" => DATA <= x"22";
when x"7A" => DATA <= x"00";
when x"7B" => DATA <= x"00";
when x"7C" => DATA <= x"00";
when x"7D" => DATA <= x"00";
when x"7E" => DATA <= x"00";
when x"7F" => DATA <= x"00";
when x"80" => DATA <= x"00";
when x"81" => DATA <= x"00";
when x"82" => DATA <= x"00";
when x"83" => DATA <= x"22";
when x"84" => DATA <= x"22";
when x"85" => DATA <= x"14";
when x"86" => DATA <= x"08";
when x"87" => DATA <= x"14";
when x"88" => DATA <= x"22";
when x"89" => DATA <= x"22";
when x"8A" => DATA <= x"00";
when x"8B" => DATA <= x"00";
when x"8C" => DATA <= x"00";
when x"8D" => DATA <= x"00";
when x"8E" => DATA <= x"00";
when x"8F" => DATA <= x"00";
when x"90" => DATA <= x"00";
when x"91" => DATA <= x"00";
when x"92" => DATA <= x"00";
when x"93" => DATA <= x"22";
when x"94" => DATA <= x"22";
when x"95" => DATA <= x"14";
when x"96" => DATA <= x"08";
when x"97" => DATA <= x"08";
when x"98" => DATA <= x"08";
when x"99" => DATA <= x"08";
when x"9A" => DATA <= x"00";
when x"9B" => DATA <= x"00";
when x"9C" => DATA <= x"00";
when x"9D" => DATA <= x"00";
when x"9E" => DATA <= x"00";
when x"9F" => DATA <= x"00";
when x"A0" => DATA <= x"00";
when x"A1" => DATA <= x"00";
when x"A2" => DATA <= x"00";
when x"A3" => DATA <= x"3E";
when x"A4" => DATA <= x"02";
when x"A5" => DATA <= x"04";
when x"A6" => DATA <= x"08";
when x"A7" => DATA <= x"10";
when x"A8" => DATA <= x"20";
when x"A9" => DATA <= x"3E";
when x"AA" => DATA <= x"00";
when x"AB" => DATA <= x"00";
when x"AC" => DATA <= x"00";
when x"AD" => DATA <= x"00";
when x"AE" => DATA <= x"00";
when x"AF" => DATA <= x"00";
when x"B0" => DATA <= x"00";
when x"B1" => DATA <= x"00";
when x"B2" => DATA <= x"00";
when x"B3" => DATA <= x"38";
when x"B4" => DATA <= x"20";
when x"B5" => DATA <= x"20";
when x"B6" => DATA <= x"20";
when x"B7" => DATA <= x"20";
when x"B8" => DATA <= x"20";
when x"B9" => DATA <= x"38";
when x"BA" => DATA <= x"00";
when x"BB" => DATA <= x"00";
when x"BC" => DATA <= x"00";
when x"BD" => DATA <= x"00";
when x"BE" => DATA <= x"00";
when x"BF" => DATA <= x"00";
when x"C0" => DATA <= x"00";
when x"C1" => DATA <= x"00";
when x"C2" => DATA <= x"00";
when x"C3" => DATA <= x"20";
when x"C4" => DATA <= x"20";
when x"C5" => DATA <= x"10";
when x"C6" => DATA <= x"08";
when x"C7" => DATA <= x"04";
when x"C8" => DATA <= x"02";
when x"C9" => DATA <= x"02";
when x"CA" => DATA <= x"00";
when x"CB" => DATA <= x"00";
when x"CC" => DATA <= x"00";
when x"CD" => DATA <= x"00";
when x"CE" => DATA <= x"00";
when x"CF" => DATA <= x"00";
when x"D0" => DATA <= x"00";
when x"D1" => DATA <= x"00";
when x"D2" => DATA <= x"00";
when x"D3" => DATA <= x"0E";
when x"D4" => DATA <= x"02";
when x"D5" => DATA <= x"02";
when x"D6" => DATA <= x"02";
when x"D7" => DATA <= x"02";
when x"D8" => DATA <= x"02";
when x"D9" => DATA <= x"0E";
when x"DA" => DATA <= x"00";
when x"DB" => DATA <= x"00";
when x"DC" => DATA <= x"00";
when x"DD" => DATA <= x"00";
when x"DE" => DATA <= x"00";
when x"DF" => DATA <= x"00";
when x"E0" => DATA <= x"00";
when x"E1" => DATA <= x"00";
when x"E2" => DATA <= x"00";
when x"E3" => DATA <= x"08";
when x"E4" => DATA <= x"1C";
when x"E5" => DATA <= x"2A";
when x"E6" => DATA <= x"08";
when x"E7" => DATA <= x"08";
when x"E8" => DATA <= x"08";
when x"E9" => DATA <= x"08";
when x"EA" => DATA <= x"00";
when x"EB" => DATA <= x"00";
when x"EC" => DATA <= x"00";
when x"ED" => DATA <= x"00";
when x"EE" => DATA <= x"00";
when x"EF" => DATA <= x"00";
when x"F0" => DATA <= x"00";
when x"F1" => DATA <= x"00";
when x"F2" => DATA <= x"00";
when x"F3" => DATA <= x"00";
when x"F4" => DATA <= x"08";
when x"F5" => DATA <= x"10";
when x"F6" => DATA <= x"3E";
when x"F7" => DATA <= x"10";
when x"F8" => DATA <= x"08";
when x"F9" => DATA <= x"00";
when x"FA" => DATA <= x"00";
when x"FB" => DATA <= x"00";
when x"FC" => DATA <= x"00";
when x"FD" => DATA <= x"00";
when x"FE" => DATA <= x"00";
when x"FF" => DATA <= x"00";
when others => DATA <= (others => '0');
end case;
end if;
if rom_addr(9 downto 8) = "10" then
case rom_addr(7 downto 0) is
when x"00" => DATA <= x"00";
when x"01" => DATA <= x"00";
when x"02" => DATA <= x"00";
when x"03" => DATA <= x"00";
when x"04" => DATA <= x"00";
when x"05" => DATA <= x"00";
when x"06" => DATA <= x"00";
when x"07" => DATA <= x"00";
when x"08" => DATA <= x"00";
when x"09" => DATA <= x"00";
when x"0A" => DATA <= x"00";
when x"0B" => DATA <= x"00";
when x"0C" => DATA <= x"00";
when x"0D" => DATA <= x"00";
when x"0E" => DATA <= x"00";
when x"0F" => DATA <= x"00";
when x"10" => DATA <= x"00";
when x"11" => DATA <= x"00";
when x"12" => DATA <= x"00";
when x"13" => DATA <= x"08";
when x"14" => DATA <= x"08";
when x"15" => DATA <= x"08";
when x"16" => DATA <= x"08";
when x"17" => DATA <= x"08";
when x"18" => DATA <= x"00";
when x"19" => DATA <= x"08";
when x"1A" => DATA <= x"00";
when x"1B" => DATA <= x"00";
when x"1C" => DATA <= x"00";
when x"1D" => DATA <= x"00";
when x"1E" => DATA <= x"00";
when x"1F" => DATA <= x"00";
when x"20" => DATA <= x"00";
when x"21" => DATA <= x"00";
when x"22" => DATA <= x"00";
when x"23" => DATA <= x"14";
when x"24" => DATA <= x"14";
when x"25" => DATA <= x"14";
when x"26" => DATA <= x"00";
when x"27" => DATA <= x"00";
when x"28" => DATA <= x"00";
when x"29" => DATA <= x"00";
when x"2A" => DATA <= x"00";
when x"2B" => DATA <= x"00";
when x"2C" => DATA <= x"00";
when x"2D" => DATA <= x"00";
when x"2E" => DATA <= x"00";
when x"2F" => DATA <= x"00";
when x"30" => DATA <= x"00";
when x"31" => DATA <= x"00";
when x"32" => DATA <= x"00";
when x"33" => DATA <= x"14";
when x"34" => DATA <= x"14";
when x"35" => DATA <= x"36";
when x"36" => DATA <= x"00";
when x"37" => DATA <= x"36";
when x"38" => DATA <= x"14";
when x"39" => DATA <= x"14";
when x"3A" => DATA <= x"00";
when x"3B" => DATA <= x"00";
when x"3C" => DATA <= x"00";
when x"3D" => DATA <= x"00";
when x"3E" => DATA <= x"00";
when x"3F" => DATA <= x"00";
when x"40" => DATA <= x"00";
when x"41" => DATA <= x"00";
when x"42" => DATA <= x"00";
when x"43" => DATA <= x"08";
when x"44" => DATA <= x"1E";
when x"45" => DATA <= x"20";
when x"46" => DATA <= x"1C";
when x"47" => DATA <= x"02";
when x"48" => DATA <= x"3C";
when x"49" => DATA <= x"08";
when x"4A" => DATA <= x"00";
when x"4B" => DATA <= x"00";
when x"4C" => DATA <= x"00";
when x"4D" => DATA <= x"00";
when x"4E" => DATA <= x"00";
when x"4F" => DATA <= x"00";
when x"50" => DATA <= x"00";
when x"51" => DATA <= x"00";
when x"52" => DATA <= x"00";
when x"53" => DATA <= x"32";
when x"54" => DATA <= x"32";
when x"55" => DATA <= x"04";
when x"56" => DATA <= x"08";
when x"57" => DATA <= x"10";
when x"58" => DATA <= x"26";
when x"59" => DATA <= x"26";
when x"5A" => DATA <= x"00";
when x"5B" => DATA <= x"00";
when x"5C" => DATA <= x"00";
when x"5D" => DATA <= x"00";
when x"5E" => DATA <= x"00";
when x"5F" => DATA <= x"00";
when x"60" => DATA <= x"00";
when x"61" => DATA <= x"00";
when x"62" => DATA <= x"00";
when x"63" => DATA <= x"10";
when x"64" => DATA <= x"28";
when x"65" => DATA <= x"28";
when x"66" => DATA <= x"10";
when x"67" => DATA <= x"2A";
when x"68" => DATA <= x"24";
when x"69" => DATA <= x"1A";
when x"6A" => DATA <= x"00";
when x"6B" => DATA <= x"00";
when x"6C" => DATA <= x"00";
when x"6D" => DATA <= x"00";
when x"6E" => DATA <= x"00";
when x"6F" => DATA <= x"00";
when x"70" => DATA <= x"00";
when x"71" => DATA <= x"00";
when x"72" => DATA <= x"00";
when x"73" => DATA <= x"18";
when x"74" => DATA <= x"18";
when x"75" => DATA <= x"18";
when x"76" => DATA <= x"00";
when x"77" => DATA <= x"00";
when x"78" => DATA <= x"00";
when x"79" => DATA <= x"00";
when x"7A" => DATA <= x"00";
when x"7B" => DATA <= x"00";
when x"7C" => DATA <= x"00";
when x"7D" => DATA <= x"00";
when x"7E" => DATA <= x"00";
when x"7F" => DATA <= x"00";
when x"80" => DATA <= x"00";
when x"81" => DATA <= x"00";
when x"82" => DATA <= x"00";
when x"83" => DATA <= x"08";
when x"84" => DATA <= x"10";
when x"85" => DATA <= x"20";
when x"86" => DATA <= x"20";
when x"87" => DATA <= x"20";
when x"88" => DATA <= x"10";
when x"89" => DATA <= x"08";
when x"8A" => DATA <= x"00";
when x"8B" => DATA <= x"00";
when x"8C" => DATA <= x"00";
when x"8D" => DATA <= x"00";
when x"8E" => DATA <= x"00";
when x"8F" => DATA <= x"00";
when x"90" => DATA <= x"00";
when x"91" => DATA <= x"00";
when x"92" => DATA <= x"00";
when x"93" => DATA <= x"08";
when x"94" => DATA <= x"04";
when x"95" => DATA <= x"02";
when x"96" => DATA <= x"02";
when x"97" => DATA <= x"02";
when x"98" => DATA <= x"04";
when x"99" => DATA <= x"08";
when x"9A" => DATA <= x"00";
when x"9B" => DATA <= x"00";
when x"9C" => DATA <= x"00";
when x"9D" => DATA <= x"00";
when x"9E" => DATA <= x"00";
when x"9F" => DATA <= x"00";
when x"A0" => DATA <= x"00";
when x"A1" => DATA <= x"00";
when x"A2" => DATA <= x"00";
when x"A3" => DATA <= x"00";
when x"A4" => DATA <= x"08";
when x"A5" => DATA <= x"1C";
when x"A6" => DATA <= x"3E";
when x"A7" => DATA <= x"1C";
when x"A8" => DATA <= x"08";
when x"A9" => DATA <= x"00";
when x"AA" => DATA <= x"00";
when x"AB" => DATA <= x"00";
when x"AC" => DATA <= x"00";
when x"AD" => DATA <= x"00";
when x"AE" => DATA <= x"00";
when x"AF" => DATA <= x"00";
when x"B0" => DATA <= x"00";
when x"B1" => DATA <= x"00";
when x"B2" => DATA <= x"00";
when x"B3" => DATA <= x"00";
when x"B4" => DATA <= x"08";
when x"B5" => DATA <= x"08";
when x"B6" => DATA <= x"3E";
when x"B7" => DATA <= x"08";
when x"B8" => DATA <= x"08";
when x"B9" => DATA <= x"00";
when x"BA" => DATA <= x"00";
when x"BB" => DATA <= x"00";
when x"BC" => DATA <= x"00";
when x"BD" => DATA <= x"00";
when x"BE" => DATA <= x"00";
when x"BF" => DATA <= x"00";
when x"C0" => DATA <= x"00";
when x"C1" => DATA <= x"00";
when x"C2" => DATA <= x"00";
when x"C3" => DATA <= x"00";
when x"C4" => DATA <= x"00";
when x"C5" => DATA <= x"00";
when x"C6" => DATA <= x"30";
when x"C7" => DATA <= x"30";
when x"C8" => DATA <= x"10";
when x"C9" => DATA <= x"20";
when x"CA" => DATA <= x"00";
when x"CB" => DATA <= x"00";
when x"CC" => DATA <= x"00";
when x"CD" => DATA <= x"00";
when x"CE" => DATA <= x"00";
when x"CF" => DATA <= x"00";
when x"D0" => DATA <= x"00";
when x"D1" => DATA <= x"00";
when x"D2" => DATA <= x"00";
when x"D3" => DATA <= x"00";
when x"D4" => DATA <= x"00";
when x"D5" => DATA <= x"00";
when x"D6" => DATA <= x"3E";
when x"D7" => DATA <= x"00";
when x"D8" => DATA <= x"00";
when x"D9" => DATA <= x"00";
when x"DA" => DATA <= x"00";
when x"DB" => DATA <= x"00";
when x"DC" => DATA <= x"00";
when x"DD" => DATA <= x"00";
when x"DE" => DATA <= x"00";
when x"DF" => DATA <= x"00";
when x"E0" => DATA <= x"00";
when x"E1" => DATA <= x"00";
when x"E2" => DATA <= x"00";
when x"E3" => DATA <= x"00";
when x"E4" => DATA <= x"00";
when x"E5" => DATA <= x"00";
when x"E6" => DATA <= x"00";
when x"E7" => DATA <= x"00";
when x"E8" => DATA <= x"30";
when x"E9" => DATA <= x"30";
when x"EA" => DATA <= x"00";
when x"EB" => DATA <= x"00";
when x"EC" => DATA <= x"00";
when x"ED" => DATA <= x"00";
when x"EE" => DATA <= x"00";
when x"EF" => DATA <= x"00";
when x"F0" => DATA <= x"00";
when x"F1" => DATA <= x"00";
when x"F2" => DATA <= x"00";
when x"F3" => DATA <= x"02";
when x"F4" => DATA <= x"02";
when x"F5" => DATA <= x"04";
when x"F6" => DATA <= x"08";
when x"F7" => DATA <= x"10";
when x"F8" => DATA <= x"20";
when x"F9" => DATA <= x"20";
when x"FA" => DATA <= x"00";
when x"FB" => DATA <= x"00";
when x"FC" => DATA <= x"00";
when x"FD" => DATA <= x"00";
when x"FE" => DATA <= x"00";
when x"FF" => DATA <= x"00";
when others => DATA <= (others => '0');
end case;
end if;
if rom_addr(9 downto 8) = "11" then
case rom_addr(7 downto 0) is
when x"00" => DATA <= x"00";
when x"01" => DATA <= x"00";
when x"02" => DATA <= x"00";
when x"03" => DATA <= x"18";
when x"04" => DATA <= x"24";
when x"05" => DATA <= x"24";
when x"06" => DATA <= x"24";
when x"07" => DATA <= x"24";
when x"08" => DATA <= x"24";
when x"09" => DATA <= x"18";
when x"0A" => DATA <= x"00";
when x"0B" => DATA <= x"00";
when x"0C" => DATA <= x"00";
when x"0D" => DATA <= x"00";
when x"0E" => DATA <= x"00";
when x"0F" => DATA <= x"00";
when x"10" => DATA <= x"00";
when x"11" => DATA <= x"00";
when x"12" => DATA <= x"00";
when x"13" => DATA <= x"08";
when x"14" => DATA <= x"18";
when x"15" => DATA <= x"08";
when x"16" => DATA <= x"08";
when x"17" => DATA <= x"08";
when x"18" => DATA <= x"08";
when x"19" => DATA <= x"1C";
when x"1A" => DATA <= x"00";
when x"1B" => DATA <= x"00";
when x"1C" => DATA <= x"00";
when x"1D" => DATA <= x"00";
when x"1E" => DATA <= x"00";
when x"1F" => DATA <= x"00";
when x"20" => DATA <= x"00";
when x"21" => DATA <= x"00";
when x"22" => DATA <= x"00";
when x"23" => DATA <= x"1C";
when x"24" => DATA <= x"22";
when x"25" => DATA <= x"02";
when x"26" => DATA <= x"1C";
when x"27" => DATA <= x"20";
when x"28" => DATA <= x"20";
when x"29" => DATA <= x"3E";
when x"2A" => DATA <= x"00";
when x"2B" => DATA <= x"00";
when x"2C" => DATA <= x"00";
when x"2D" => DATA <= x"00";
when x"2E" => DATA <= x"00";
when x"2F" => DATA <= x"00";
when x"30" => DATA <= x"00";
when x"31" => DATA <= x"00";
when x"32" => DATA <= x"00";
when x"33" => DATA <= x"1C";
when x"34" => DATA <= x"22";
when x"35" => DATA <= x"02";
when x"36" => DATA <= x"04";
when x"37" => DATA <= x"02";
when x"38" => DATA <= x"22";
when x"39" => DATA <= x"1C";
when x"3A" => DATA <= x"00";
when x"3B" => DATA <= x"00";
when x"3C" => DATA <= x"00";
when x"3D" => DATA <= x"00";
when x"3E" => DATA <= x"00";
when x"3F" => DATA <= x"00";
when x"40" => DATA <= x"00";
when x"41" => DATA <= x"00";
when x"42" => DATA <= x"00";
when x"43" => DATA <= x"04";
when x"44" => DATA <= x"0C";
when x"45" => DATA <= x"14";
when x"46" => DATA <= x"3E";
when x"47" => DATA <= x"04";
when x"48" => DATA <= x"04";
when x"49" => DATA <= x"04";
when x"4A" => DATA <= x"00";
when x"4B" => DATA <= x"00";
when x"4C" => DATA <= x"00";
when x"4D" => DATA <= x"00";
when x"4E" => DATA <= x"00";
when x"4F" => DATA <= x"00";
when x"50" => DATA <= x"00";
when x"51" => DATA <= x"00";
when x"52" => DATA <= x"00";
when x"53" => DATA <= x"3E";
when x"54" => DATA <= x"20";
when x"55" => DATA <= x"3C";
when x"56" => DATA <= x"02";
when x"57" => DATA <= x"02";
when x"58" => DATA <= x"22";
when x"59" => DATA <= x"1C";
when x"5A" => DATA <= x"00";
when x"5B" => DATA <= x"00";
when x"5C" => DATA <= x"00";
when x"5D" => DATA <= x"00";
when x"5E" => DATA <= x"00";
when x"5F" => DATA <= x"00";
when x"60" => DATA <= x"00";
when x"61" => DATA <= x"00";
when x"62" => DATA <= x"00";
when x"63" => DATA <= x"1C";
when x"64" => DATA <= x"20";
when x"65" => DATA <= x"20";
when x"66" => DATA <= x"3C";
when x"67" => DATA <= x"22";
when x"68" => DATA <= x"22";
when x"69" => DATA <= x"1C";
when x"6A" => DATA <= x"00";
when x"6B" => DATA <= x"00";
when x"6C" => DATA <= x"00";
when x"6D" => DATA <= x"00";
when x"6E" => DATA <= x"00";
when x"6F" => DATA <= x"00";
when x"70" => DATA <= x"00";
when x"71" => DATA <= x"00";
when x"72" => DATA <= x"00";
when x"73" => DATA <= x"3E";
when x"74" => DATA <= x"02";
when x"75" => DATA <= x"04";
when x"76" => DATA <= x"08";
when x"77" => DATA <= x"10";
when x"78" => DATA <= x"20";
when x"79" => DATA <= x"20";
when x"7A" => DATA <= x"00";
when x"7B" => DATA <= x"00";
when x"7C" => DATA <= x"00";
when x"7D" => DATA <= x"00";
when x"7E" => DATA <= x"00";
when x"7F" => DATA <= x"00";
when x"80" => DATA <= x"00";
when x"81" => DATA <= x"00";
when x"82" => DATA <= x"00";
when x"83" => DATA <= x"1C";
when x"84" => DATA <= x"22";
when x"85" => DATA <= x"22";
when x"86" => DATA <= x"1C";
when x"87" => DATA <= x"22";
when x"88" => DATA <= x"22";
when x"89" => DATA <= x"1C";
when x"8A" => DATA <= x"00";
when x"8B" => DATA <= x"00";
when x"8C" => DATA <= x"00";
when x"8D" => DATA <= x"00";
when x"8E" => DATA <= x"00";
when x"8F" => DATA <= x"00";
when x"90" => DATA <= x"00";
when x"91" => DATA <= x"00";
when x"92" => DATA <= x"00";
when x"93" => DATA <= x"1C";
when x"94" => DATA <= x"22";
when x"95" => DATA <= x"22";
when x"96" => DATA <= x"1E";
when x"97" => DATA <= x"02";
when x"98" => DATA <= x"02";
when x"99" => DATA <= x"1C";
when x"9A" => DATA <= x"00";
when x"9B" => DATA <= x"00";
when x"9C" => DATA <= x"00";
when x"9D" => DATA <= x"00";
when x"9E" => DATA <= x"00";
when x"9F" => DATA <= x"00";
when x"A0" => DATA <= x"00";
when x"A1" => DATA <= x"00";
when x"A2" => DATA <= x"00";
when x"A3" => DATA <= x"00";
when x"A4" => DATA <= x"18";
when x"A5" => DATA <= x"18";
when x"A6" => DATA <= x"00";
when x"A7" => DATA <= x"18";
when x"A8" => DATA <= x"18";
when x"A9" => DATA <= x"00";
when x"AA" => DATA <= x"00";
when x"AB" => DATA <= x"00";
when x"AC" => DATA <= x"00";
when x"AD" => DATA <= x"00";
when x"AE" => DATA <= x"00";
when x"AF" => DATA <= x"00";
when x"B0" => DATA <= x"00";
when x"B1" => DATA <= x"00";
when x"B2" => DATA <= x"00";
when x"B3" => DATA <= x"18";
when x"B4" => DATA <= x"18";
when x"B5" => DATA <= x"00";
when x"B6" => DATA <= x"18";
when x"B7" => DATA <= x"18";
when x"B8" => DATA <= x"08";
when x"B9" => DATA <= x"10";
when x"BA" => DATA <= x"00";
when x"BB" => DATA <= x"00";
when x"BC" => DATA <= x"00";
when x"BD" => DATA <= x"00";
when x"BE" => DATA <= x"00";
when x"BF" => DATA <= x"00";
when x"C0" => DATA <= x"00";
when x"C1" => DATA <= x"00";
when x"C2" => DATA <= x"00";
when x"C3" => DATA <= x"04";
when x"C4" => DATA <= x"08";
when x"C5" => DATA <= x"10";
when x"C6" => DATA <= x"20";
when x"C7" => DATA <= x"10";
when x"C8" => DATA <= x"08";
when x"C9" => DATA <= x"04";
when x"CA" => DATA <= x"00";
when x"CB" => DATA <= x"00";
when x"CC" => DATA <= x"00";
when x"CD" => DATA <= x"00";
when x"CE" => DATA <= x"00";
when x"CF" => DATA <= x"00";
when x"D0" => DATA <= x"00";
when x"D1" => DATA <= x"00";
when x"D2" => DATA <= x"00";
when x"D3" => DATA <= x"00";
when x"D4" => DATA <= x"00";
when x"D5" => DATA <= x"3E";
when x"D6" => DATA <= x"00";
when x"D7" => DATA <= x"3E";
when x"D8" => DATA <= x"00";
when x"D9" => DATA <= x"00";
when x"DA" => DATA <= x"00";
when x"DB" => DATA <= x"00";
when x"DC" => DATA <= x"00";
when x"DD" => DATA <= x"00";
when x"DE" => DATA <= x"00";
when x"DF" => DATA <= x"00";
when x"E0" => DATA <= x"00";
when x"E1" => DATA <= x"00";
when x"E2" => DATA <= x"00";
when x"E3" => DATA <= x"10";
when x"E4" => DATA <= x"08";
when x"E5" => DATA <= x"04";
when x"E6" => DATA <= x"02";
when x"E7" => DATA <= x"04";
when x"E8" => DATA <= x"08";
when x"E9" => DATA <= x"10";
when x"EA" => DATA <= x"00";
when x"EB" => DATA <= x"00";
when x"EC" => DATA <= x"00";
when x"ED" => DATA <= x"00";
when x"EE" => DATA <= x"00";
when x"EF" => DATA <= x"00";
when x"F0" => DATA <= x"00";
when x"F1" => DATA <= x"00";
when x"F2" => DATA <= x"00";
when x"F3" => DATA <= x"18";
when x"F4" => DATA <= x"24";
when x"F5" => DATA <= x"04";
when x"F6" => DATA <= x"08";
when x"F7" => DATA <= x"08";
when x"F8" => DATA <= x"00";
when x"F9" => DATA <= x"08";
when x"FA" => DATA <= x"00";
when x"FB" => DATA <= x"00";
when x"FC" => DATA <= x"00";
when x"FD" => DATA <= x"00";
when x"FE" => DATA <= x"00";
when x"FF" => DATA <= x"00";
when others => DATA <= (others => '0');
end case;
end if;
end process;
end BEHAVIOURAL;
| apache-2.0 | 009a84f95c00d25c2b36ced96835499e | 0.309726 | 3.173893 | false | false | false | false |
sergev/vak-opensource | hardware/dlx/dlx-instrumented.vhdl | 1 | 26,403 | --------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: dlx-instrumented.vhdl,v $ $Revision: 2.1 $ $Date: 1993/11/02 18:36:01 $
--
--------------------------------------------------------------------------
--
-- Instrumented behavioural architecture for DLX, that generates
-- a files of instruction execution frequencies for a program.
--
use work.dlx_instr.all,
work.bv_arithmetic.all,
std.textio.all;
architecture instrumented of dlx is
begin -- instrumented
interpreter: process
type reg_array is array (reg_index) of dlx_word;
variable reg : reg_array;
variable fp_reg : reg_array;
variable PC : dlx_word;
variable user_mode : boolean;
variable overflow, div_by_zero : boolean;
constant PC_incr : dlx_word := X"0000_0004";
variable IR : dlx_word;
alias IR_opcode : dlx_opcode is IR(0 to 5);
alias IR_sp_func : dlx_sp_func is IR(26 to 31);
alias IR_fp_func : dlx_fp_func is IR(27 to 31);
alias IR_rs1 : dlx_reg_addr is IR(6 to 10);
alias IR_rs2 : dlx_reg_addr is IR(11 to 15);
alias IR_Itype_rd : dlx_reg_addr is IR(11 to 15);
alias IR_Rtype_rd : dlx_reg_addr is IR(16 to 20);
alias IR_immed16 : dlx_immed16 is IR(16 to 31);
alias IR_immed26 : dlx_immed26 is IR(6 to 31);
variable IR_opcode_num : dlx_opcode_num;
variable IR_sp_func_num : dlx_sp_func_num;
variable IR_fp_func_num : dlx_fp_func_num;
variable rs1, rs2, Itype_rd, Rtype_rd : reg_index;
variable mem_addr : dlx_address;
variable mem_data : dlx_word;
subtype ls_2_addr_bits is bit_vector(1 downto 0);
file data : text is out "dlx_instruction_counts";
variable L : line;
---------------------------------------------------------------------------
-- instrumentation: array of counters, one per instruction
---------------------------------------------------------------------------
type opcode_count_array is array (dlx_opcode_num) of natural;
type sp_func_count_array is array (dlx_sp_func_num) of natural;
type fp_func_count_array is array (dlx_fp_func_num) of natural;
variable op_count : opcode_count_array := (others => 0);
variable sp_func_count : sp_func_count_array := (others => 0);
variable fp_func_count : fp_func_count_array := (others => 0);
variable instr_count : natural := 0;
---------------------------------------------------------------------------
-- instrumentation: procedure to dump counter values
---------------------------------------------------------------------------
procedure instrumentation_dump is
variable L : line;
begin
for op in dlx_opcode_num loop
write(L, opcode_names(op));
write(L, ' ');
write(L, op_count(op));
writeline(data, L);
end loop;
for sp_func in dlx_sp_func_num loop
write(L, sp_func_names(sp_func));
write(L, ' ');
write(L, sp_func_count(sp_func));
writeline(data, L);
end loop;
for fp_func in dlx_fp_func_num loop
write(L, fp_func_names(fp_func));
write(L, ' ');
write(L, fp_func_count(fp_func));
writeline(data, L);
end loop;
end instrumentation_dump;
---------------------------------------------------------------------------
procedure write (address : in dlx_address;
data_width : in mem_width;
data : in dlx_word;
signal phi1, phi2 : in bit; -- 2-phase non-overlapping clks
signal reset : in bit; -- synchronous reset input
signal a : out dlx_address; -- address bus output
signal d : inout dlx_word_bus; -- bidirectional data bus
signal width : out mem_width; -- byte/halfword/word
signal write_enable : out bit; -- selects read/write cycle
signal mem_enable : out bit; -- starts memory cycle
signal ifetch : out bit; -- indicates instruction fetch
signal ready : in bit; -- status from memory system
Tpd_clk_out : in time -- clock to output delay
) is
begin
wait until phi1 = '1';
if reset = '1' then
return;
end if;
a <= address after Tpd_clk_out;
width <= data_width after Tpd_clk_out;
d <= data after Tpd_clk_out;
write_enable <= '1' after Tpd_clk_out;
mem_enable <= '1' after Tpd_clk_out;
ifetch <= '0' after Tpd_clk_out;
loop
wait until phi2 = '0';
exit when ready = '1' or reset = '1';
end loop;
d <= null after Tpd_clk_out;
write_enable <= '0' after Tpd_clk_out;
mem_enable <= '0' after Tpd_clk_out;
end write;
procedure bus_read (address : in dlx_address;
data_width : in mem_width;
instr_fetch : in boolean;
data : out dlx_word;
signal phi1, phi2 : in bit; -- 2-phase non-overlapping clks
signal reset : in bit; -- synchronous reset input
signal a : out dlx_address; -- address bus output
signal d : inout dlx_word_bus; -- bidirectional data bus
signal width : out mem_width; -- byte/halfword/word
signal write_enable : out bit; -- selects read/write cycle
signal mem_enable : out bit; -- starts memory cycle
signal ifetch : out bit; -- indicates instruction eftch
signal ready : in bit; -- status from memory system
Tpd_clk_out : in time -- clock to output delay
) is
begin
wait until phi1 = '1';
if reset = '1' then
return;
end if;
a <= address after Tpd_clk_out;
width <= data_width after Tpd_clk_out;
mem_enable <= '1' after Tpd_clk_out;
ifetch <= bit'val(boolean'pos(instr_fetch)) after Tpd_clk_out;
loop
wait until phi2 = '0';
exit when ready = '1' or reset = '1';
end loop;
data := d;
mem_enable <= '0' after Tpd_clk_out;
end bus_read;
begin -- interpreter
--
-- reset the processor
--
d <= null;
halt <= '0';
write_enable <= '0';
mem_enable <= '0';
reg(0) := X"0000_0000";
PC := X"0000_0000";
user_mode := false;
--
-- fetch-decode-execute loop
--
loop
--
-- fetch next instruction
--
if debug then
write(L, tag);
write(L, string'(": fetching instruction..."));
writeline(output, L);
end if;
--
bus_read(PC, width_word, true, IR,
phi1, phi2, reset, a, d, width, write_enable, mem_enable, ifetch, ready,
Tpd_clk_out);
exit when reset = '1';
--
-- increment the PC to point to the following instruction
--
if debug then
write(L, tag);
write(L, string'(": incrementing PC..."));
writeline(output, L);
end if;
--
bv_add(PC, PC_incr, PC, overflow);
--
-- decode the instruction
--
if debug then
write(L, tag);
write(L, string'(": decoding instruction..."));
writeline(output, L);
end if;
--
IR_opcode_num := bv_to_natural(IR_opcode);
IR_sp_func_num := bv_to_natural(IR_sp_func);
IR_fp_func_num := bv_to_natural(IR_fp_func);
rs1 := bv_to_natural(IR_rs1);
rs2 := bv_to_natural(IR_rs2);
Itype_rd := bv_to_natural(IR_Itype_rd);
Rtype_rd := bv_to_natural(IR_Rtype_rd);
--
-------------------------------------------------------------------------
-- instrumentation: increment counter for decoded instruction
-------------------------------------------------------------------------
--
op_count(IR_opcode_num) := op_count(IR_opcode_num) + 1;
if IR_opcode = op_special then
sp_func_count(IR_sp_func_num) := sp_func_count(IR_sp_func_num) + 1;
elsif IR_opcode = op_fparith then
fp_func_count(IR_fp_func_num) := fp_func_count(IR_fp_func_num) + 1;
end if;
instr_count := instr_count + 1;
--
-------------------------------------------------------------------------
--
-- exectute
--
if debug then
write(L, tag);
write(L, string'(": executing instruction..."));
writeline(output, L);
end if;
--
case IR_opcode is
when op_special =>
case IR_sp_func is
WHEN sp_func_nop =>
null;
when sp_func_sll =>
reg(Rtype_rd) := bv_sll(reg(rs1), bv_to_natural(reg(rs2)(27 to 31)));
when sp_func_srl =>
reg(Rtype_rd) := bv_srl(reg(rs1), bv_to_natural(reg(rs2)(27 to 31)));
when sp_func_sra =>
reg(Rtype_rd) := bv_sra(reg(rs1), bv_to_natural(reg(rs2)(27 to 31)));
when sp_func_sequ =>
if reg(rs1) = reg(rs2) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_sneu =>
if reg(rs1) /= reg(rs2) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_sltu =>
if reg(rs1) < reg(rs2) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_sgtu =>
if reg(rs1) > reg(rs2) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_sleu =>
if reg(rs1) <= reg(rs2) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_sgeu =>
if reg(rs1) >= reg(rs2) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_add =>
bv_add(reg(rs1), reg(rs2), reg(Rtype_rd), overflow);
when sp_func_addu =>
bv_addu(reg(rs1), reg(rs2), reg(Rtype_rd), overflow);
when sp_func_sub =>
bv_sub(reg(rs1), reg(rs2), reg(Rtype_rd), overflow);
when sp_func_subu =>
bv_subu(reg(rs1), reg(rs2), reg(Rtype_rd), overflow);
when sp_func_and =>
reg(Rtype_rd) := reg(rs1) and reg(rs2);
when sp_func_or =>
reg(Rtype_rd) := reg(rs1) or reg(rs2);
when sp_func_xor =>
reg(Rtype_rd) := reg(rs1) xor reg(rs2);
when sp_func_seq =>
if reg(rs1) = reg(rs2) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_sne =>
if reg(rs1) /= reg(rs2) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_slt =>
if bv_lt(reg(rs1), reg(rs2)) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_sgt =>
if bv_gt(reg(rs1), reg(rs2)) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_sle =>
if bv_le(reg(rs1), reg(rs2)) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_sge =>
if bv_ge(reg(rs1), reg(rs2)) then
reg(Rtype_rd) := X"0000_0001";
else
reg(Rtype_rd) := X"0000_0000";
end if;
when sp_func_movi2s =>
assert false
report "MOVI2S instruction not implemented" severity warning;
when sp_func_movs2i =>
assert false
report "MOVS2I instruction not implemented" severity warning;
when sp_func_movf =>
assert false
report "MOVF instruction not implemented" severity warning;
when sp_func_movd =>
assert false
report "MOVD instruction not implemented" severity warning;
when sp_func_movfp2i =>
reg(Rtype_rd) := fp_reg(rs1);
when sp_func_movi2fp =>
fp_reg(Rtype_rd) := reg(rs1);
when others =>
assert false
report "undefined special instruction function" severity error;
end case;
when op_fparith =>
case IR_fp_func is
when fp_func_mult =>
bv_mult(fp_reg(rs1), fp_reg(rs2), fp_reg(Rtype_rd), overflow);
when fp_func_multu =>
bv_multu(fp_reg(rs1), fp_reg(rs2), fp_reg(Rtype_rd), overflow);
when fp_func_div =>
bv_div(fp_reg(rs1), fp_reg(rs2), fp_reg(Rtype_rd), div_by_zero, overflow);
when fp_func_divu =>
bv_divu(fp_reg(rs1), fp_reg(rs2), fp_reg(Rtype_rd), div_by_zero);
when fp_func_addf | fp_func_subf | fp_func_multf | fp_func_divf |
fp_func_addd | fp_func_subd | fp_func_multd | fp_func_divd |
fp_func_cvtf2d | fp_func_cvtf2i | fp_func_cvtd2f |
fp_func_cvtd2i | fp_func_cvti2f | fp_func_cvti2d |
fp_func_eqf | fp_func_nef | fp_func_ltf | fp_func_gtf |
fp_func_lef | fp_func_gef | fp_func_eqd | fp_func_ned |
fp_func_ltd | fp_func_gtd | fp_func_led | fp_func_ged =>
assert false
report "floating point instructions not implemented" severity warning;
when others =>
assert false
report "undefined floating point instruction function" severity error;
end case;
when op_j =>
bv_add(PC, bv_sext(IR_immed26, 32), PC, overflow);
when op_jal =>
reg(link_reg) := PC;
bv_add(PC, bv_sext(IR_immed26, 32), PC, overflow);
when op_beqz =>
if reg(rs1) = X"0000_0000" then
bv_add(PC, bv_sext(IR_immed16, 32), PC, overflow);
end if;
when op_bnez =>
if reg(rs1) /= X"0000_0000" then
bv_add(PC, bv_sext(IR_immed16, 32), PC, overflow);
end if;
when op_bfpt =>
assert false
report "BFPT instruction not implemented" severity warning;
when op_bfpf =>
assert false
report "BFPF instruction not implemented" severity warning;
when op_addi =>
bv_add(reg(rs1), bv_sext(IR_immed16, 32), reg(Itype_rd), overflow);
when op_addui =>
bv_addu(reg(rs1), bv_zext(IR_immed16, 32), reg(Itype_rd), overflow);
when op_subi =>
bv_sub(reg(rs1), bv_sext(IR_immed16, 32), reg(Itype_rd), overflow);
when op_subui =>
bv_subu(reg(rs1), bv_zext(IR_immed16, 32), reg(Itype_rd), overflow);
when op_slli =>
reg(Itype_rd) := bv_sll(reg(rs1), bv_to_natural(IR_immed16(11 to 15)));
when op_srli =>
reg(Itype_rd) := bv_srl(reg(rs1), bv_to_natural(IR_immed16(11 to 15)));
when op_srai =>
reg(Itype_rd) := bv_sra(reg(rs1), bv_to_natural(IR_immed16(11 to 15)));
when op_andi =>
reg(Itype_rd) := reg(rs1) and bv_zext(IR_immed16, 32);
when op_ori =>
reg(Itype_rd) := reg(rs1) or bv_zext(IR_immed16, 32);
when op_xori =>
reg(Itype_rd) := reg(rs1) xor bv_zext(IR_immed16, 32);
when op_lhi =>
reg(Itype_rd) := IR_immed16 & X"0000";
when op_rfe =>
assert false
report "RFE instruction not implemented" severity warning;
when op_trap =>
assert false
report "TRAP instruction encountered, execution halted"
severity note;
halt <= '1' after Tpd_clk_out;
---------------------------------------------------------------------
-- instrumentation: dump counters
---------------------------------------------------------------------
instrumentation_dump;
---------------------------------------------------------------------
wait until reset = '1';
exit;
when op_jr =>
PC := reg(rs1);
when op_jalr =>
reg(link_reg) := PC;
PC := reg(rs1);
when op_seqi =>
if reg(rs1) = bv_sext(IR_immed16, 32) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when op_snei =>
if reg(rs1) /= bv_sext(IR_immed16, 32) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when op_slti =>
if bv_lt(reg(rs1), bv_sext(IR_immed16, 32)) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when op_sgti =>
if bv_gt(reg(rs1), bv_sext(IR_immed16, 32)) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when op_slei =>
if bv_le(reg(rs1), bv_sext(IR_immed16, 32)) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when op_sgei =>
if bv_ge(reg(rs1), bv_sext(IR_immed16, 32)) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when op_lb =>
bv_add(reg(rs1), bv_sext(IR_immed16, 32), mem_addr, overflow);
bus_read(mem_addr, width_byte, false, mem_data,
phi1, phi2, reset, a, d, width, write_enable, mem_enable, ifetch, ready,
Tpd_clk_out);
exit when reset = '1';
case ls_2_addr_bits'(mem_addr(1 downto 0)) is
when B"00" =>
reg(Itype_rd) := bv_sext(mem_data(0 to 7), 32);
when B"01" =>
reg(Itype_rd) := bv_sext(mem_data(8 to 15), 32);
when B"10" =>
reg(Itype_rd) := bv_sext(mem_data(16 to 23), 32);
when B"11" =>
reg(Itype_rd) := bv_sext(mem_data(24 to 31), 32);
end case;
when op_lh =>
bv_add(reg(rs1), bv_sext(IR_immed16, 32), mem_addr, overflow);
bus_read(mem_addr, width_halfword, false, mem_data,
phi1, phi2, reset, a, d, width, write_enable, mem_enable, ifetch, ready,
Tpd_clk_out);
exit when reset = '1';
if mem_addr(1) = '0' then
reg(Itype_rd) := bv_sext(mem_data(0 to 15), 32);
else
reg(Itype_rd) := bv_sext(mem_data(16 to 31), 32);
end if;
when op_lw =>
bv_add(reg(rs1), bv_sext(IR_immed16, 32), mem_addr, overflow);
bus_read(mem_addr, width_word, false, mem_data,
phi1, phi2, reset, a, d, width, write_enable, mem_enable, ifetch, ready,
Tpd_clk_out);
exit when reset = '1';
reg(Itype_rd) := mem_data;
when op_lbu =>
bv_add(reg(rs1), bv_sext(IR_immed16, 32), mem_addr, overflow);
bus_read(mem_addr, width_byte, false, mem_data,
phi1, phi2, reset, a, d, width, write_enable, mem_enable, ifetch, ready,
Tpd_clk_out);
exit when reset = '1';
case ls_2_addr_bits'(mem_addr(1 downto 0)) is
when B"00" =>
reg(Itype_rd) := bv_zext(mem_data(0 to 7), 32);
when B"01" =>
reg(Itype_rd) := bv_zext(mem_data(8 to 15), 32);
when B"10" =>
reg(Itype_rd) := bv_zext(mem_data(16 to 23), 32);
when B"11" =>
reg(Itype_rd) := bv_zext(mem_data(24 to 31), 32);
end case;
when op_lhu =>
bv_add(reg(rs1), bv_sext(IR_immed16, 32), mem_addr, overflow);
bus_read(mem_addr, width_halfword, false, mem_data,
phi1, phi2, reset, a, d, width, write_enable, mem_enable, ifetch, ready,
Tpd_clk_out);
exit when reset = '1';
if mem_addr(1) = '0' then
reg(Itype_rd) := bv_zext(mem_data(0 to 15), 32);
else
reg(Itype_rd) := bv_zext(mem_data(16 to 31), 32);
end if;
when op_lf =>
assert false
report "LF instruction not implemented" severity warning;
when op_ld =>
assert false
report "LD instruction not implemented" severity warning;
when op_sb =>
bv_add(reg(rs1), bv_sext(IR_immed16, 32), mem_addr, overflow);
mem_data := X"0000_0000";
case ls_2_addr_bits'(mem_addr(1 downto 0)) is
when B"00" =>
mem_data(0 to 7) := reg(Itype_rd)(0 to 7);
when B"01" =>
mem_data(8 to 15) := reg(Itype_rd)(0 to 7);
when B"10" =>
mem_data(16 to 23) := reg(Itype_rd)(0 to 7);
when B"11" =>
mem_data(24 to 31) := reg(Itype_rd)(0 to 7);
end case;
write(mem_addr, width_halfword, mem_data,
phi1, phi2, reset, a, d, width, write_enable, mem_enable, ifetch, ready,
Tpd_clk_out);
exit when reset = '1';
when op_sh =>
bv_add(reg(rs1), bv_sext(IR_immed16, 32), mem_addr, overflow);
mem_data := X"0000_0000";
if mem_addr(1) = '0' then
mem_data(0 to 15) := reg(Itype_rd)(0 to 15);
else
mem_data(16 to 31) := reg(Itype_rd)(0 to 15);
end if;
write(mem_addr, width_halfword, mem_data,
phi1, phi2, reset, a, d, width, write_enable, mem_enable, ifetch, ready,
Tpd_clk_out);
exit when reset = '1';
when op_sw =>
bv_add(reg(rs1), bv_sext(IR_immed16, 32), mem_addr, overflow);
mem_data := reg(Itype_rd);
write(mem_addr, width_word, mem_data,
phi1, phi2, reset, a, d, width, write_enable, mem_enable, ifetch, ready,
Tpd_clk_out);
exit when reset = '1';
when op_sf =>
assert false
report "SF instruction not implemented" severity warning;
when op_sd =>
assert false
report "SD instruction not implemented" severity warning;
when op_sequi =>
if reg(rs1) = bv_zext(IR_immed16, 32) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when op_sneui =>
if reg(rs1) /= bv_zext(IR_immed16, 32) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when op_sltui =>
if reg(rs1) < bv_zext(IR_immed16, 32) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when op_sgtui =>
if reg(rs1) > bv_zext(IR_immed16, 32) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when op_sleui =>
if reg(rs1) <= bv_zext(IR_immed16, 32) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when op_sgeui =>
if reg(rs1) >= bv_zext(IR_immed16, 32) then
reg(Itype_rd) := X"0000_0001";
else
reg(Itype_rd) := X"0000_0000";
end if;
when others =>
assert false
report "undefined instruction" severity error;
end case;
--
-- fix up R0 in case it was overwritten
--
reg(0) := X"0000_0000";
--
if debug then
write(L, tag);
write(L, string'(": end of execution"));
writeline(output, L);
end if;
if instr_count mod 100 = 0 then
write(L, tag);
write(L, string'(": executed "));
write(L, instr_count);
write(L, string'(" instructions"));
writeline(output, L);
end if;
--
end loop;
--
-- loop is only exited when reset active: wait until it goes inactive
--
assert reset = '1'
report "reset code reached with reset = '0'" severity error;
wait until phi2 = '0' and reset = '0';
--
-- process interpreter now starts again from beginning
--
end process interpreter;
end instrumented;
| apache-2.0 | 5fc978e53eff1c37c1fb0e197501b97c | 0.48396 | 3.691695 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/boards/terasic-de2-115/mn-single-hostif-gpio/quartus/toplevel.vhd | 2 | 9,437 | -------------------------------------------------------------------------------
--! @file toplevel.vhd
--
--! @brief Toplevel of Nios MN design Host part
--
--! @details This is the toplevel of the Nios MN FPGA Host design for the
--! INK DE2-115 Evaluation Board.
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity toplevel is
port (
-- 50 MHZ CLK IN
EXT_CLK : in std_logic;
-- EPCS
EPCS_DCLK : out std_logic;
EPCS_SCE : out std_logic;
EPCS_SDO : out std_logic;
EPCS_DATA0 : in std_logic;
-- 64 MBx2 SDRAM
SDRAM_CLK : out std_logic;
SDRAM_CAS_n : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CS_n : out std_logic;
SDRAM_RAS_n : out std_logic;
SDRAM_WE_n : out std_logic;
SDRAM_ADDR : out std_logic_vector(12 downto 0);
SDRAM_BA : out std_logic_vector(1 downto 0);
SDRAM_DQM : out std_logic_vector(3 downto 0);
SDRAM_DQ : inout std_logic_vector(31 downto 0);
-- LED green
LEDG : out std_logic_vector(1 downto 0);
-- LCD
LCD_ON : out std_logic;
LCD_BLON : out std_logic;
LCD_DQ : inout std_logic_vector(7 downto 0);
LCD_E : out std_logic;
LCD_RS : out std_logic;
LCD_RW : out std_logic;
-- HOST Interface
HOSTIF_AD : inout std_logic_vector(15 downto 0);
HOSTIF_BE : out std_logic_vector(1 downto 0);
HOSTIF_CS_n : out std_logic;
HOSTIF_WR_n : out std_logic;
HOSTIF_ALE_n : out std_logic;
HOSTIF_RD_n : out std_logic;
HOSTIF_ACK_n : in std_logic;
HOSTIF_IRQ_n : in std_logic
);
end toplevel;
architecture rtl of toplevel is
component mnSingleHostifGpio is
port (
clk25_clk : in std_logic;
clk50_clk : in std_logic := 'X';
clk100_clk : in std_logic;
reset_reset_n : in std_logic := 'X';
host_0_benchmark_pio_export : out std_logic_vector(7 downto 0);
status_led_pio_export : out std_logic_vector(1 downto 0);
epcs_flash_dclk : out std_logic;
epcs_flash_sce : out std_logic;
epcs_flash_sdo : out std_logic;
epcs_flash_data0 : in std_logic := 'X';
host_0_sdram_0_addr : out std_logic_vector(12 downto 0);
host_0_sdram_0_ba : out std_logic_vector(1 downto 0);
host_0_sdram_0_cas_n : out std_logic;
host_0_sdram_0_cke : out std_logic;
host_0_sdram_0_cs_n : out std_logic;
host_0_sdram_0_dq : inout std_logic_vector(31 downto 0) := (others => 'X');
host_0_sdram_0_dqm : out std_logic_vector(3 downto 0);
host_0_sdram_0_ras_n : out std_logic;
host_0_sdram_0_we_n : out std_logic;
multiplexedadbus_0_cs : out std_logic;
multiplexedadbus_0_ad : inout std_logic_vector(15 downto 0) := (others => 'X');
multiplexedadbus_0_be : out std_logic_vector(1 downto 0);
multiplexedadbus_0_ale : out std_logic;
multiplexedadbus_0_wr : out std_logic;
multiplexedadbus_0_rd : out std_logic;
multiplexedadbus_0_ack : in std_logic := 'X';
host_0_irq_irq : in std_logic := 'X';
lcd_data : inout std_logic_vector(7 downto 0) := (others => 'X');
lcd_E : out std_logic;
lcd_RS : out std_logic;
lcd_RW : out std_logic
);
end component mnSingleHostifGpio;
-- PLL component
component pll
port (
inclk0 : in std_logic;
c0 : out std_logic;
c1 : out std_logic;
c2 : out std_logic;
c3 : out std_logic;
locked : out std_logic
);
end component;
signal clk25 : std_logic;
signal clk50 : std_logic;
signal clk100 : std_logic;
signal clk100_p : std_logic;
signal pllLocked : std_logic;
signal hostifCs : std_logic;
signal hostifWr : std_logic;
signal hostifRd : std_logic;
signal hostifAle : std_logic;
signal hostifAck : std_logic;
signal hostifIrq : std_logic;
begin
LCD_ON <= '1';
LCD_BLON <= '1';
SDRAM_CLK <= clk100_p;
HOSTIF_CS_n <= not hostifCs;
HOSTIF_WR_n <= not hostifWr;
HOSTIF_RD_n <= not hostifRd;
HOSTIF_ALE_n <= not hostifAle;
hostifAck <= not HOSTIF_ACK_n;
hostifIrq <= not HOSTIF_IRQ_n;
inst : component mnSingleHostifGpio
port map (
clk25_clk => clk25,
clk50_clk => clk50,
clk100_clk => clk100,
reset_reset_n => pllLocked,
status_led_pio_export => LEDG,
host_0_benchmark_pio_export => open,
epcs_flash_dclk => EPCS_DCLK,
epcs_flash_sce => EPCS_SCE,
epcs_flash_sdo => EPCS_SDO,
epcs_flash_data0 => EPCS_DATA0,
host_0_sdram_0_addr => SDRAM_ADDR,
host_0_sdram_0_ba => SDRAM_BA,
host_0_sdram_0_cas_n => SDRAM_CAS_n,
host_0_sdram_0_cke => SDRAM_CKE,
host_0_sdram_0_cs_n => SDRAM_CS_n,
host_0_sdram_0_dq => SDRAM_DQ,
host_0_sdram_0_dqm => SDRAM_DQM,
host_0_sdram_0_ras_n => SDRAM_RAS_n,
host_0_sdram_0_we_n => SDRAM_WE_n,
multiplexedadbus_0_cs => hostifCs,
multiplexedadbus_0_ad => HOSTIF_AD,
multiplexedadbus_0_be => HOSTIF_BE,
multiplexedadbus_0_ale => hostifAle,
multiplexedadbus_0_wr => hostifWr,
multiplexedadbus_0_rd => hostifRd,
multiplexedadbus_0_ack => hostifAck,
host_0_irq_irq => hostifIrq,
lcd_data => LCD_DQ,
lcd_E => LCD_E,
lcd_RS => LCD_RS,
lcd_RW => LCD_RW
);
-- Pll Instance
pllInst : pll
port map (
inclk0 => EXT_CLK,
c0 => clk50,
c1 => clk100,
c2 => clk25,
c3 => clk100_p,
locked => pllLocked
);
end rtl;
| gpl-2.0 | d4df79ee52cfe24a5a09efdd061cca4b | 0.469111 | 4.111983 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/altera/lib/src/dpRamSplx-rtl-a.vhd | 2 | 3,526 | --! @file dpRamSplx-rtl-a.vhd
--
--! @brief Simplex Dual Port Ram Register Transfer Level Architecture
--
--! @details This is the Simplex DPRAM intended for synthesis on Altera
--! platforms only.
--! Timing as follows [clk-cycles]: write=0 / read=1
--
-------------------------------------------------------------------------------
-- Architecture : rtl
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! use altera_mf library
library altera_mf;
use altera_mf.altera_mf_components.all;
architecture rtl of dpRamSplx is
begin
altsyncram_component : altsyncram
generic map (
operation_mode => "DUAL_PORT",
intended_device_family => "Cyclone IV",
init_file => gInitFile,
numwords_a => gNumberOfWordsA,
numwords_b => gNumberOfWordsB,
widthad_a => logDualis(gNumberOfWordsA),
widthad_b => logDualis(gNumberOfWordsB),
width_a => gWordWidthA,
width_b => gWordWidthB,
width_byteena_a => gByteenableWidthA,
width_byteena_b => gByteenableWidthA
)
port map (
clock0 => iClk_A,
clocken0 => iEnable_A,
wren_a => iWriteEnable_A,
address_a => iAddress_A,
byteena_a => iByteenable_A,
data_a => iWritedata_A,
clock1 => iClk_B,
clocken1 => iEnable_B,
address_b => iAddress_B,
q_b => oReaddata_B
);
end architecture rtl;
| gpl-2.0 | 9b28ba449c7bbb2f849e52fac5bcfc20 | 0.579977 | 4.771313 | false | false | false | false |
Rookfighter/fft-spartan6 | fft/tf16.vhd | 1 | 1,692 | -- tf16.vhd
--
-- Created on: 17 Jul 2017
-- Author: Fabian Meyer
--
-- Clock synchronous twiddle factor provider for 16-point FFT.
library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.fft_helpers.all;
entity tf16 is
generic(RSTDEF: std_logic := '0';
FFTEXP: natural := 4);
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
swrst: in std_logic; -- software reset, RSTDEF active
en: in std_logic; -- enable, high active
addr: in std_logic_vector(FFTEXP-2 downto 0); -- address of twiddle factor
w: out complex); -- twiddle factor
end tf16;
architecture behavioral of tf16 is
-- twiddle factors for 16-Point FFT
constant WFACS: complex_arr(0 to (2**(FFTEXP-1))-1) := (
to_complex(1.0, 0.0),
to_complex(0.9239, 0.3827),
to_complex(0.7071, 0.7071),
to_complex(0.3827, 0.9239),
to_complex(0.0, 1.0),
to_complex(-0.3827, 0.9239),
to_complex(-0.7071, 0.7071),
to_complex(-0.9239, 0.3827)
);
signal w_tmp: complex := COMPZERO;
begin
w <= w_tmp;
process(rst, clk) is
begin
if rst = RSTDEF then
w_tmp <= COMPZERO;
elsif rising_edge(clk) then
if swrst = RSTDEF then
w_tmp <= COMPZERO;
elsif en = '1' then
w_tmp <= WFACS(to_integer(unsigned(addr)));
end if;
end if;
end process;
end architecture;
| mit | 30036e16bcb5e2db891cad4521b0b3f6 | 0.521868 | 3.554622 | false | false | false | false |
FinnK/lems2hdl | work/N3_pointCellCondBased/ISIM_output/passive.vhdl | 1 | 9,465 |
---------------------------------------------------------------------
-- Standard Library bits
---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- For Modelsim
--use ieee.fixed_pkg.all;
--use ieee.fixed_float_types.ALL;
-- For ISE
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.fixed_float_types.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Entity Description
---------------------------------------------------------------------
entity passive is
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC; --SYNCHRONOUS RESET
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
component_done : out STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_conductance_conductance : in sfixed (-22 downto -53);
exposure_conductance_g : out sfixed (-22 downto -53);
derivedvariable_conductance_g_out : out sfixed (-22 downto -53);
derivedvariable_conductance_g_in : in sfixed (-22 downto -53);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end passive;
---------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-- Architecture Begins
-------------------------------------------------------------------------------------------
architecture RTL of passive is
signal COUNT : unsigned(2 downto 0) := "000";
signal childrenCombined_Component_done_single_shot_fired : STD_LOGIC := '0';
signal childrenCombined_Component_done_single_shot : STD_LOGIC := '0';
signal childrenCombined_Component_done : STD_LOGIC := '0';
signal Component_done_int : STD_LOGIC := '0';
signal subprocess_der_int_pre_ready : STD_LOGIC := '0';
signal subprocess_der_int_ready : STD_LOGIC := '0';
signal subprocess_der_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_pre_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_ready : STD_LOGIC := '0';
signal subprocess_dyn_ready : STD_LOGIC := '0';
signal subprocess_model_ready : STD_LOGIC := '1';
signal subprocess_all_ready_shotdone : STD_LOGIC := '1';
signal subprocess_all_ready_shot : STD_LOGIC := '0';
signal subprocess_all_ready : STD_LOGIC := '0';
---------------------------------------------------------------------
-- Derived Variables and parameters
---------------------------------------------------------------------
signal DerivedVariable_none_fopen : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_none_fopen_next : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_conductance_g : sfixed (-22 downto -53) := to_sfixed(0.0 ,-22,-53);
signal DerivedVariable_conductance_g_next : sfixed (-22 downto -53) := to_sfixed(0.0 ,-22,-53);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState internal Variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Output Port internal Variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Child Components
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Begin Internal Processes
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Child EDComponent Instantiations and corresponding internal variables
---------------------------------------------------------------------
derived_variable_pre_process_comb :process ( sysparam_time_timestep, param_conductance_conductance )
begin
end process derived_variable_pre_process_comb;
derived_variable_pre_process_syn :process ( clk, init_model )
begin
subprocess_der_int_pre_ready <= '1';
end process derived_variable_pre_process_syn;
--no complex steps in derived variables
subprocess_der_int_ready <= '1';
derived_variable_process_comb :process ( sysparam_time_timestep, param_conductance_conductance )
begin
derivedvariable_none_fopen_next <= resize(( to_sfixed ( 1 ,1 , -1 ) ),18,-13);
derivedvariable_conductance_g_next <= resize(( param_conductance_conductance ),-22,-53);
subprocess_der_ready <= '1';
end process derived_variable_process_comb;
derived_variable_process_syn :process ( clk,init_model )
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
derivedvariable_none_fopen <= derivedvariable_none_fopen_next;
derivedvariable_conductance_g <= derivedvariable_conductance_g_next;
end if;
end if;
end process derived_variable_process_syn;
---------------------------------------------------------------------
dynamics_pre_process_comb :process ( sysparam_time_timestep )
begin
end process dynamics_pre_process_comb;
dynamics_pre_process_syn :process ( clk, init_model )
begin
subprocess_dyn_int_pre_ready <= '1';
end process dynamics_pre_process_syn;
--No dynamics with complex equations found
subprocess_dyn_int_ready <= '1';
state_variable_process_dynamics_comb :process (sysparam_time_timestep)
begin
subprocess_dyn_ready <= '1';
end process state_variable_process_dynamics_comb;
state_variable_process_dynamics_syn :process (CLK,init_model)
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
end if;
end if;
end process state_variable_process_dynamics_syn;
------------------------------------------------------------------------------------------------------
-- EDState Variable Drivers
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to exposures
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to output state variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign derived variables to exposures
---------------------------------------------------------------------
exposure_conductance_g <= derivedvariable_conductance_g_in;derivedvariable_conductance_g_out <= derivedvariable_conductance_g;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Subprocess ready process
---------------------------------------------------------------------
subprocess_all_ready_process: process(step_once_go,subprocess_der_int_ready,subprocess_der_int_pre_ready,subprocess_der_ready,subprocess_dyn_int_pre_ready,subprocess_dyn_int_ready,subprocess_dyn_ready,subprocess_model_ready)
begin
if step_once_go = '0' and subprocess_der_int_ready = '1' and subprocess_der_int_pre_ready = '1'and subprocess_der_ready ='1' and subprocess_dyn_int_ready = '1' and subprocess_dyn_int_pre_ready = '1' and subprocess_dyn_ready = '1' and subprocess_model_ready = '1' then
subprocess_all_ready <= '1';
else
subprocess_all_ready <= '0';
end if;
end process subprocess_all_ready_process;
subprocess_all_ready_shot_process : process(clk)
begin
if rising_edge(clk) then
if (init_model='1') then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '1';
else
if subprocess_all_ready = '1' and subprocess_all_ready_shotdone = '0' then
subprocess_all_ready_shot <= '1';
subprocess_all_ready_shotdone <= '1';
elsif subprocess_all_ready_shot = '1' then
subprocess_all_ready_shot <= '0';
elsif subprocess_all_ready = '0' then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '0';
end if;
end if;
end if;
end process subprocess_all_ready_shot_process;
---------------------------------------------------------------------
count_proc:process(clk)
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then COUNT <= "001";
component_done_int <= '1';
else if step_once_go = '1' then
COUNT <= "000";
component_done_int <= '0';
elsif COUNT = "001" then
component_done_int <= '1';
elsif subprocess_all_ready_shot = '1' then
COUNT <= COUNT + 1;
component_done_int <= '0';
end if;
end if;
end if;
end process count_proc;
component_done <= component_done_int;
end RTL;
| lgpl-3.0 | 44070a5480105c5ad58a43e958a532fb | 0.487586 | 4.36779 | false | false | false | false |
sergev/vak-opensource | hardware/dlx/dlx_test_cache.vhdl | 1 | 2,504 | --------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: dlx_test_cache.vhdl,v $ $Revision: 2.1 $ $Date: 1993/11/02 22:16:15 $
--
--------------------------------------------------------------------------
--
-- Configuration of test bench for DLX and cache,
-- using behavioural architectures.
--
configuration dlx_test_cache of dlx_test is
for bench_cache
use work.cache_types.all;
for cg : clock_gen
use entity work.clock_gen(behaviour)
generic map (Tpw => 8 ns, Tps => 2 ns);
end for;
for mem : memory
use entity work.memory(behaviour)
generic map (mem_size => 65536,
Tac1 => 95 ns, Tacb => 35 ns, Tpd_clk_out => 2 ns);
end for;
for the_cache : cache
use entity work.cache(behaviour)
generic map (cache_size => 4096, line_size => 16,
associativity => 2, write_strategy => write_through,
Tpd_clk_out => 2 ns);
end for;
for cpu_cache_monitor : dlx_bus_monitor
use entity work.dlx_bus_monitor(behaviour)
generic map (enable => true, verbose => false, tag => "cpu cache monitor");
end for;
for cache_mem_monitor : dlx_bus_monitor
use entity work.dlx_bus_monitor(behaviour)
generic map (enable => true, verbose => false, tag => "cache mem monitor");
end for;
for proc : dlx
use entity work.dlx(behaviour)
generic map (Tpd_clk_out => 2 ns, debug => false, tag => "proc");
end for;
end for;
end dlx_test_cache;
| apache-2.0 | 38a6056cda770fb557a33a851d7c05bd | 0.582668 | 3.955766 | false | true | false | false |
paulino/digilentinc-peripherals | rtl/port_display_dig.vhd | 1 | 3,582 | -------------------------------------------------------------------------------
-- Copyright 2014 Paulino Ruiz de Clavijo Vázquez <[email protected]>
-- This file is part of the Digilentinc-peripherals project.
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- You can get more info at http://www.dte.us.es/id2
--
--*------------------------------- End auto header, don't touch this line --*--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
entity port_display_dig is port ( clk : in std_logic;
enable : in std_logic;
digit_in : in std_logic_vector (7 downto 0);
w_msb : in std_logic;
w_lsb : in std_logic;
seg_out : out std_logic_vector (6 downto 0);
dp_out : out std_logic;
an_out : out std_logic_vector (3 downto 0));
end port_display_dig;
architecture Behavioral of port_display_dig is
signal counter : unsigned (23 downto 0);
signal counter4: unsigned (1 downto 0);
signal digit_lsb : std_logic_vector (7 downto 0);
signal digit_msb : std_logic_vector (7 downto 0);
signal conv_in : std_logic_vector (3 downto 0);
signal divider : std_logic;
begin
-- Writer process
write_proc : process (clk,enable)
begin
if falling_edge(clk) and enable='1' then
if w_msb='1' then
digit_msb <= digit_in;
end if;
if w_lsb='1' then
digit_lsb <= digit_in;
end if;
end if;
end process;
-- Clock divider process
div_proc : process (clk,counter)
begin
if falling_edge(clk) then
if(counter > x"0000ffff") then
counter <= x"000000";
divider <= '1';
else
counter <= counter + 1;
divider <= '0';
end if;
end if;
end process;
div2_proc : process(clk,divider)
begin
if falling_edge(clk) then
if divider='1' then
counter4 <= counter4 +1;
end if;
end if;
end process;
-- Anode control
mux_proc: process (counter4,digit_lsb,digit_msb)
begin
case counter4 is
when "00" =>
an_out <= "1110";
conv_in <= digit_lsb(3 downto 0);
when "01" =>
an_out <= "1101";
conv_in <= digit_lsb(7 downto 4);
when "10" =>
an_out <= "1011";
conv_in <= digit_msb(3 downto 0);
when others =>
an_out <= "0111";
conv_in <= digit_msb(7 downto 4);
end case;
end process;
-- Binary to seven seg converter
with conv_in select
seg_out <= "1000000" when "0000", --0
"1111001" when "0001", --1
"0100100" when "0010", --2
"0110000" when "0011", --3
"0011001" when "0100", --4
"0010010" when "0101", --5
"0000010" when "0110", --6
"1111000" when "0111", --7
"0000000" when "1000", --8
"0010000" when "1001", --9
"0001000" when "1010", --A
"0000011" when "1011", --b
"1000110" when "1100", --C
"0100001" when "1101", --d
"0000110" when "1110", --E
"0001110" when others; --F
dp_out <= '1';
end Behavioral;
| apache-2.0 | b3662fffa99c6d66c34ea8780724def0 | 0.572187 | 3.459903 | false | false | false | false |
s-kostyuk/course_project_csch | pilot_processor_signed_div/operational_unit.vhd | 1 | 2,207 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_logic_arith.all;
entity operational_unit is
generic(
N: integer := 4
);
port(
clk,rst : in STD_LOGIC;
y : in STD_LOGIC_VECTOR(16 downto 1);
d1 : in STD_LOGIC_VECTOR(2*N-1 downto 0);
d2 : in STD_LOGIC_VECTOR(N-1 downto 0);
r:out STD_LOGIC_VECTOR(N-1 downto 0);
x:out STD_LOGIC_vector(8 downto 1);
IRQ1, IRQ2: out std_logic
);
end operational_unit;
architecture operational_unit of operational_unit is
signal A,Ain: STD_LOGIC_VECTOR(2*N-1 downto 0) ;
signal B,Bin: STD_LOGIC_VECTOR(N downto 0) ;
signal TgS, TgSin: std_logic;
signal CnT, CnTin: std_logic_vector(7 downto 0);
signal C, Cin: STD_LOGIC_VECTOR(N-1 downto 0) ;
begin
process(clk,rst)is
begin
if rst='0' then
a<=(others=>'0');
b<=(others=>'0');
TgS<='0';
CnT<=(others=>'0');
elsif rising_edge(clk)then
A<=Ain;B<=Bin ;CnT <= CnTin; C <= Cin; TgS <= TgSin;
end if;
end process;
ain<= D1 when y(1)='1'
else (A(2*N-1 downto N-1) + not B + 1) & A(N-2 downto 0) when y(5)='1'
else (A(2*N-1 downto N-1) + B) & A(N-2 downto 0) when y(6)='1'
else A(2*N-2 downto 0) & '0' when y(12) = '1'
else a;
bin<= D2(N-1 downto 0) & '0' when y(2) = '1'
else B(N) & B(N downto 1) when y(4) = '1'
else b;
Cin <= (others=>'0') when y(7)='1'
else C(N-2 downto 0) & '1' when y(9)='1'
else C(N-2 downto 0) & '0' when y(10)='1'
else C + 1 when y(13) = '1'
else C;
IRQ1 <= y(15);
IRQ2 <= y(16);
CnTin <= conv_std_logic_vector(N, 8) when y(8) = '1'
else CnT - 1 when y(11) = '1'
else CnT;
r <= C when y(14) = '1'
else (others => 'Z');
TgSin <= A(2*N-1) when y(3) = '1'
else TgS;
x(1) <= '1' when B = 0 else '0';
x(2) <= '1' when (A(2*N-1) xor B(N)) = '1' else '0';
x(3) <= '1' when CnT = 0 else '0';
x(4) <= '1' when (A(2*N-1) xor TgS) = '1' else '0';
--x(4) <= '0';
--x(4) <= '1' when (TgS xor B(N)) = '1' else '0';
x(5) <= '1' when B(N) = '1' else '0';
x(6) <= '1' when (B(N) xor TgS) = '1' else '0';
x(7) <= '1' when TgS = '1' else '0';
x(8) <= '1' when A = 0 else '0';
end operational_unit; | mit | 35554d33486e625f2150a9d3b0b87103 | 0.536475 | 2.209209 | false | false | false | false |
dqydj/VGAtonic | Hardware_Rev_B/CPLD Firmware/SPI_Slave.vhd | 2 | 5,245 | -----------------------------------------------------------------------------------
-- Top SPI Speed Calculation (Please check my math - no warranties implied)
-- To determine top speed, look at worst case and count user clocks
-- 1) SPI_CACHE_FULL_FLAG goes high too late for tSU to react
-- 2) CACHE_FULL_FLAG = '1' (Single buffered read to cross domain)
-- 3) CACHE_FULL_FLAG & SPI_CACHE_FULL_FLAG. User Logic sends reset signal.
--
--
-- We can accept up to 7 bits of the full SPI (plus a half clock minus setup
-- time, actually, due to "if (ACK_SPI_BYTE = '1')") based on our code -
-- so 7.5 clocks of SPI cannot be faster than 3 clocks of User Logic. We write
-- the inverse to convert to time, as time is 1/frequency:
--
-- (3/7.5)tUSER < tSPI
--
-- "How much" less is determined by the setup time on the user logic flip flop,
-- so we can constrain it further, and add back the setup time factor:
--
-- (7.5 * tSPI) > (3 * tUSER) + tSU + tSU
-- tSPI > (3*tUSER + 2*tSU)/7.5
--
-- Example: For a 25.125 MHz User Clock and a Xilinx XC95144XL-10 with an internal
-- logic setup time of 3.0 ns:
--
-- tSPI > ((3 * 39.801) +(3.0 + 3.0))/7.5 = 16.7204 ns
-- For that part combination and our code, SPI speed shouldn't exceed
-- 59.807 MHz... But in practice, I'm running at 62.5 MHz without problems. YMMV.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity SPI_Slave is
Port (
--------------------------------------------------------
-- SPI Declarations --
--------------------------------------------------------
SEL_SPI : in STD_LOGIC;
-- SPI Pins from World
EXT_SCK : in STD_LOGIC;
EXT_SEL : in STD_LOGIC;
EXT_MOSI : in STD_LOGIC;
EXT_MISO : out STD_LOGIC;
-- SPI Pins from AVR
AVR_SCK : in STD_LOGIC;
AVR_SEL : in STD_LOGIC;
AVR_MOSI : in STD_LOGIC;
-- AVR_MISO : out STD_LOGIC; -- No need for MISO; the board is backwards here so leave it off.
-- One byte FIFO
SPI_DATA_CACHE : out STD_LOGIC_VECTOR(7 downto 0) := "00000000";
-- Asynchronous flags for signals sent to display logic
SPI_CACHE_FULL_FLAG : out STD_LOGIC := '0';
SPI_CMD_RESET_FLAG : out STD_LOGIC := '0';
-- Async Flags returned from user logic
ACK_USER_RESET : in STD_LOGIC;
ACK_SPI_BYTE : in STD_LOGIC
);
end SPI_Slave;
architecture Behavioral of SPI_Slave is
-- Temporary Storage for SPI (Sneaky: cheat by one bit out of 8 to save a flip-flop!)
signal SPI_DATA_REG : STD_LOGIC_VECTOR(6 downto 0) := "0000000";
-- Counter for our receiver
signal SCK_COUNTER : STD_LOGIC_VECTOR(2 downto 0) := "000";
signal SCK : STD_LOGIC := '0';
signal SEL : STD_LOGIC := '0';
signal MOSI : STD_LOGIC := '0';
begin
-- Code for SPI receiver
SPI_Logic: process (SEL_SPI, SCK, SEL, ACK_USER_RESET, ACK_SPI_BYTE)
begin
if (SEL_SPI = '1') then
SEL <= AVR_SEL;
SCK <= AVR_SCK;
MOSI <= AVR_MOSI;
else
SEL <= EXT_SEL;
SCK <= EXT_SCK;
MOSI <= EXT_MOSI;
end if;
-- Code to handle 'Mode Reset' in the User Logic
if (ACK_USER_RESET = '1') then -- User Logic acknowledges it was reset
SPI_CMD_RESET_FLAG <= '0';
else -- User doesn't currently acknowledge a reset
if (rising_edge(SEL)) then -- CPLD was just deselected
SPI_CMD_RESET_FLAG <= '1';
end if;
end if;
-- Code to handle our SPI arbitration, reading, and clocking
if (ACK_SPI_BYTE = '1') then -- User Logic acknowledges receiving a byte
-- Lower the Cache Full flag
SPI_CACHE_FULL_FLAG <= '0';
-- If we continue clocking while the user logic is reacting,
-- put it into our data register. This is the logic
-- which limits the top speed of the logic - but usually you'll be
-- hardware limited.
if (rising_edge(SCK)) then
if (SEL = '0') then
SPI_DATA_REG <= SPI_DATA_REG(5 downto 0) & MOSI;
SCK_COUNTER <= STD_LOGIC_VECTOR(unsigned(SCK_COUNTER) + 1);
end if;
end if;
else -- NOT currently acknowledging a byte received RISING EDGE
-- Normal, conventional, everyday, typical, average SPI logic begins.
if (rising_edge(SCK)) then
-- Our CPLD is selected
if (SEL = '0') then
-- If we've just received a whole byte...
if (SCK_COUNTER = "111") then
SCK_COUNTER <= "000";
SPI_DATA_REG <= "0000000";
-- Put the received byte into the single entry FIFO
SPI_DATA_CACHE <= SPI_DATA_REG(6 downto 0) & MOSI;
-- To: User Logic... "You've got mail."
SPI_CACHE_FULL_FLAG <= '1';
-- We're not full yet so the bits will keep coming
else
SPI_DATA_REG <= SPI_DATA_REG(5 downto 0) & MOSI;
SCK_COUNTER <= STD_LOGIC_VECTOR(unsigned(SCK_COUNTER) + 1);
end if;
-- CPLD is NOT selected
else
-- Reset counter, register
SCK_COUNTER <= "000";
SPI_DATA_REG <= "0000000";
end if; -- End CPLD Selected
end if; -- End Rising SCK edge
end if; -- end Byte Received
end process; -- end SPI
end Behavioral; | mit | c23093cd0716967505ecd5ec8abce008 | 0.578837 | 3.304978 | false | false | false | false |
paulino/digilentinc-peripherals | examples/test2-picoblaze-basys2/digilent_peripherals_picoblaze_demo.vhd | 1 | 6,718 | -------------------------------------------------------------------------------
-- Copyright 2014 Paulino Ruiz de Clavijo Vázquez <[email protected]>
-- This file is part of the Digilentinc-peripherals project.
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- You can get more info at http://www.dte.us.es/id2
--
--*------------------------------- End auto header, don't touch this line --*--
-- Description: picoblaze demo
-- Port conections using one hot code:
-- + SPI write conf => in port 01h
-- + SPI write data => in port 02h
-- + SPI read status => in port 01h
-- + SPI read data => in port 02h
-- + Leds peripheral => out port 04h
-- + Display LSB => out port 08h
-- + Display MSB => out port 10h
-- + Switches => in port 00h
-- + Buttons => in port 03h
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.digilent_peripherals_pk.all;
entity dig_peripherals_demo is port(
clk : in std_logic;
leds_out : out std_logic_vector (7 downto 0);
seg_out : out std_logic_vector (6 downto 0);
dp_out : out std_logic;
an_out : out std_logic_vector (3 downto 0);
sw_in : in std_logic_vector (7 downto 0);
btn_in : in std_logic_vector (3 downto 0);
miso : in std_logic; -- PMOD SD
mosi : out std_logic;
sclk : out std_logic;
ss : out std_logic);
end dig_peripherals_demo;
architecture behavioral of dig_peripherals_demo is
-- declaration of KCPSM3
--
component kcpsm3
port ( address : out std_logic_vector(9 downto 0);
instruction : in std_logic_vector(17 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0);
interrupt : in std_logic;
interrupt_ack : out std_logic;
reset : in std_logic;
clk : in std_logic);
end component;
component asmcode
Port ( address : in std_logic_vector(9 downto 0);
instruction : out std_logic_vector(17 downto 0);
clk : in std_logic);
end component;
------------------------------------------------------------------------------------
--
-- Signals used to connect KCPSM3 to program ROM and I/O logic
--
signal address : std_logic_vector(9 downto 0);
signal instruction : std_logic_vector(17 downto 0);
signal port_id : std_logic_vector(7 downto 0);
signal out_port : std_logic_vector(7 downto 0);
signal in_port : std_logic_vector(7 downto 0);
signal write_strobe : std_logic;
signal read_strobe : std_logic;
signal interrupt : std_logic;
signal interrupt_ack : std_logic;
signal port_display : std_logic;
signal port_display_wlsb : std_logic;
signal port_display_wmsb : std_logic;
-- SPI port signals
signal port_spi_enable : std_logic;
signal port_spi_op : std_logic; -- select config/status or data io
-- Input ports multiplexer
signal port_switches : std_logic_vector(7 downto 0);
signal port_buttons : std_logic_vector(7 downto 0);
signal port_spi : std_logic_vector(7 downto 0);
begin
u_processor: kcpsm3
port map( address => address,
instruction => instruction,
port_id => port_id,
write_strobe => write_strobe,
out_port => out_port,
read_strobe => read_strobe,
in_port => in_port,
interrupt => interrupt,
interrupt_ack => interrupt_ack,
reset => '0',
clk => clk);
u_asmcode: asmcode
port map( address => address,
instruction => instruction,
clk => clk);
--------------------------------------------
-- Picoblaze out ports
-- Leds connected to port 4
u_leds: port_leds_dig
Port map (
w => write_strobe,
enable => port_id(2),
clk => clk,
port_in => out_port,
leds_out => leds_out);
-- Display needs two ports: LSB and MSB digit. Port 8 and 16
port_display <= port_id(3) or port_id(4);
port_display_wlsb <= port_id (3) and write_strobe;
port_display_wmsb <= port_id (4) and write_strobe;
u_display : port_display_dig
port map (
clk => clk,
enable => port_display,
digit_in => out_port,
w_msb => port_display_wmsb,
w_lsb => port_display_wlsb,
seg_out => seg_out,
dp_out => dp_out,
an_out => an_out
);
----------------------------------------
-- Picoblaze input ports
with port_id(1 downto 0) select
in_port <= port_switches when "00",
port_buttons when "11",
port_spi when others;
-- Switches connected to input port 0
u_switches : port_switches_dig
port map(
r => read_strobe,
clk => clk,
enable => '1',
port_out => port_switches,
switches_in => sw_in);
-- Buttons on input port 3
u_buttons : port_buttons_dig
port map(
r => read_strobe,
clk => clk,
enable => '1',
port_out => port_buttons,
buttons_in => btn_in);
-- SPI component for PMOD SD
-- Two ports are used: config (at port 1) and data (at port 2)
port_spi_enable <= port_id(0) or port_id(1); -- data/conf selector
port_spi_op <= port_id(1); -- Write mode
u_spi: port_spi_dig
port map (
clk => clk,
data_in => out_port,
data_out => port_spi,
enable => port_spi_enable,
rw => write_strobe,
cfst_data => port_spi_op,
miso => miso,
mosi => mosi,
sclk => sclk,
ss => ss);
end behavioral;
| apache-2.0 | dace940be48dda897c74145b4de2c29f | 0.527914 | 3.739978 | false | false | false | false |
ShepardSiegel/ocpi | libsrc/hdl/vhd/ocpi_types.vhd | 1 | 6,027 |
library ieee; use IEEE.std_logic_1164.all; use ieee.numeric_std.all;
--library std;
--use std.all;
package types is
--
-- Miscellaneous type declarations not related to OpenCPI types
--
subtype word_t is std_logic_vector(31 downto 0);
subtype byte_offset_t is unsigned(1 downto 0);
-- These types are the mapping of the OpenCPI scalar types to VHDL.
-- We use std_logic vector types and avoid native types.
-- These ranges match the IDL specification
--
-- boolean type, convertible to/from vhdl native boolean
--
-- THESE ARE DEFINITIONS WHEN Bool_t is BOOLEAN
--subtype Bool_t is boolean;
-- THESE ARE DEFINITIONS WHEN Bool_t is std_logic
subtype Bool_t is std_logic;
function "and" ( l : bool_t; r : bool_t ) return boolean;
function "nand" ( l : bool_t; r : bool_t ) return boolean;
function "or" ( l : bool_t; r : bool_t ) return boolean;
function "nor" ( l : bool_t; r : bool_t ) return boolean;
function "xor" ( l : bool_t; r : bool_t ) return boolean;
function "xnor" ( l : bool_t; r : bool_t ) return boolean;
----function "and" ( l : bool_t; r : boolean ) return boolean;
function "nand" ( l : bool_t; r : boolean ) return boolean;
function "or" ( l : bool_t; r : boolean ) return boolean;
function "nor" ( l : bool_t; r : boolean ) return boolean;
function "xor" ( l : bool_t; r : boolean ) return boolean;
function "xnor" ( l : bool_t; r : boolean ) return boolean;
function "and" ( l : boolean; r : bool_t ) return boolean;
function "nand" ( l : boolean; r : bool_t ) return boolean;
function "or" ( l : boolean; r : bool_t ) return boolean;
function "nor" ( l : boolean; r : bool_t ) return boolean;
function "xor" ( l : boolean; r : bool_t ) return boolean;
function "xnor" ( l : boolean; r : bool_t ) return boolean;
function "or" ( l : bool_t; r : boolean ) return bool_t;
function "not" ( l : bool_t ) return boolean;
-- THESE ARE Bool_t related definitions independent of whether bool_t is boolean or std_logic
type bool_array_t is array (natural range <>) of bool_t;
function To_boolean (b : Bool_t) return boolean;
function To_bool(b : std_logic) return Bool_t;
function To_bool(b : std_logic_vector) return Bool_t;
function To_bool(b : boolean) return Bool_t;
function from_bool(b : bool_t) return std_logic_vector;
function btrue return bool_t;
function bfalse return bool_t;
function its(b : bool_t) return boolean;
--
-- char type, convertible to/from vhdl native character, and integer (due to numeric_std)
--
subtype char_t is signed (7 downto 0);
type char_array_t is array (natural range <>) of char_t;
constant char_min : char_t := to_signed(-128,8);
constant char_max : char_t := to_signed(127,8);
function To_character (c : Char_t) return character;
function To_char (c: Character) return char_t;
function To_char (c: integer) return char_t;
function from_char (c: char_t) return std_logic_vector;
--
-- double type - no VHDL conversions defined
--
subtype double_t is std_logic_vector (63 downto 0);
type double_array_t is array (natural range <>) of double_t;
constant double_min : double_t := x"0010_0000_0000_0000"; -- 2.2250738585072014e-308
constant double_max : double_t := x"7fef_ffff_ffff_ffff"; -- 1.7976931348623157e+308
--
-- float type - no VHDL conversions defined
--
subtype float_t is std_logic_vector (31 downto 0);
type float_array_t is array (natural range <>) of float_t;
constant float_min : float_t := x"0080_0000"; -- 1.17549435e-38
constant float_max : float_t := x"7f7f_ffff"; -- 3.40282347e+38
--
-- short type - convertible to/from vhdl native integer
--
subtype short_t is signed (15 downto 0);
type short_array_t is array (natural range <>) of short_t;
constant short_min : short_t := x"8000";
constant short_max : short_t := x"7fff";
function To_short (c: integer) return short_t;
--
-- long type - convertible to/from vhdl native integer
--
subtype long_t is signed (31 downto 0);
type long_array_t is array (natural range <>) of long_t;
constant long_min : long_t := x"8000_0000";
constant long_max : long_t := x"7fff_ffff";
function To_long (c: integer) return long_t;
--
-- uchar type - convertible to/from vhdl native natural
--
subtype uchar_t is unsigned (7 downto 0);
type uchar_array_t is array (natural range <>) of uchar_t;
constant uchar_max : uchar_t := to_unsigned(255, 8);
function To_uchar (c: natural) return uchar_t;
--
-- ulong type - convertible to/from vhdl native natural
--
subtype ulong_t is unsigned (31 downto 0);
type ulong_array_t is array (natural range <>) of ulong_t;
constant ulong_max : ulong_t := x"ffff_ffff";
function To_ulong (c: natural) return ulong_t;
--
-- ushort type - convertible to/from vhdl native natural
--
subtype ushort_t is unsigned (15 downto 0);
type ushort_array_t is array (natural range <>) of ushort_t;
constant ushort_max : ushort_t := x"ffff";
function To_ushort (c: natural) return ushort_t;
--
-- longlong type - convertible to/from vhdl native integer (perhaps)
--
subtype longlong_t is signed (63 downto 0);
type longlong_array_t is array (natural range <>) of longlong_t;
constant longlong_min : longlong_t := x"8000_0000_0000_0000";
constant longlong_max : longlong_t := x"7fff_ffff_ffff_ffff";
--
-- ulong type - convertible to/from vhdl native natural
--
subtype ulonglong_t is unsigned (63 downto 0);
type ulonglong_array_t is array (natural range <>) of ulonglong_t;
constant ulonglong_max : ulonglong_t := x"ffff_ffff_ffff_ffff";
--
-- string type - array of char
--
type string_t is array (natural range <>) of char_t;
type string_array_t is array (natural range <>,natural range <>) of char_t;
subtype wordstring_t is string_t(0 to 3);
function to_string(inword : word_t) return wordstring_t;
function from_string(s : string_t; offset : unsigned) return word_t; --std_logic_vector;
function from_bool_array(ba : bool_array_t; index, nbytes_1, byte_offset : unsigned) return word_t;
end package types;
| lgpl-3.0 | d34a3465e935446a18df876c78dbccf6 | 0.683425 | 2.964584 | false | false | false | false |
paulino/digilentinc-peripherals | rtl/port_spi_dig.vhd | 1 | 4,663 | -------------------------------------------------------------------------------
-- Copyright 2014 Paulino Ruiz de Clavijo Vázquez <[email protected]>
-- This file is part of the Digilentinc-peripherals project.
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- You can get more info at http://www.dte.us.es/id2
--
--*------------------------------- End auto header, don't touch this line --*--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
entity port_spi_dig is port (
clk : in std_logic;
enable : in std_logic;
data_in : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (7 downto 0);
rw : in std_logic; -- 0: read / 1: write
cfst_data: in std_logic; -- 0: cfg/status access, 1: data access
miso : in std_logic;
mosi : out std_logic;
sclk : out std_logic;
ss : out std_logic);
end port_spi_dig;
architecture behavioral of port_spi_dig is
-- Configuration/control flags
constant SS_F : positive := 7; -- bit 7
constant CDIV_MSB_F : positive := 2; -- bits 2 - 0
signal clkdiv_flag : std_logic_vector (CDIV_MSB_F downto 0);
signal ss_flag : std_logic;
-- Status flags for reading
constant SND_F : positive := 7; -- Sending flag: bit 7
constant DR_F : positive := 6; -- Dataready flag: bit 6
constant SCLK_F : positive := 5; -- SCLK flag: bit 5
signal sending_flag : std_logic;
signal dready_flag : std_logic;
signal sclk_flag : std_logic;
-- IO regs
signal data_out_reg : std_logic_vector (7 downto 0);
signal data_in_reg : std_logic_vector (7 downto 0);
-- internal decoded signals
signal w_conf : std_logic;
signal w_data : std_logic;
signal r_data : std_logic;
signal r_status : std_logic;
-- Internal counters
signal counter8 : unsigned (2 downto 0); -- bit send counter
signal counter_div : unsigned (7 downto 0); -- CLK Divider
begin
-- Decoding internal signals
w_conf <= enable and not cfst_data and rw;
r_status <= enable and not cfst_data and not rw;
w_data <= enable and cfst_data and rw;
r_data <= enable and cfst_data and not rw;
-- IO Conections
mosi <= data_out_reg(7);
ss <= ss_flag;
sclk <= sclk_flag;
-- Sending process
send_proc : process (clk)
begin
if falling_edge(clk) then
-- Read, after read data ready flag is cleared
if r_status = '1' then
data_out(SND_F) <= sending_flag;
data_out(DR_F) <= dready_flag;
data_out(SCLK_F) <= sclk_flag;
elsif r_data = '1' then
data_out <= data_in_reg;
dready_flag <= '0';
end if;
-- Sending process;
if w_conf='1' then -- Writing config, break current sending process
sending_flag <= '0';
dready_flag <= '0';
clkdiv_flag <= data_in(CDIV_MSB_F downto 0);
ss_flag <= data_in(SS_F);
sclk_flag <='1';
counter8 <= "000";
counter_div <= "00000000";
data_out_reg <= "00000000";
elsif w_data='1' then
data_out_reg <= data_in;
sending_flag <= '1';
dready_flag <= '0';
counter8 <= "000";
counter_div <= "00000000";
sclk_flag <= '0'; -- start clock
elsif sending_flag='1' then
counter_div <= counter_div + 1;
if (clkdiv_flag(2)='1' and counter_div(6)='1') or
(clkdiv_flag(1)='1' and counter_div(2)='1') or
(clkdiv_flag(0)='1' and counter_div(0)='1') then
counter_div <= "00000000";
if sclk_flag='0' then -- Data is captured by slave at rising edge
data_in_reg <= data_in_reg(6 downto 0) & miso;
sclk_flag <='1';
else
if counter8 = "111" then
sending_flag <= '0';
dready_flag <= '1';
sclk_flag <='1';
else
sclk_flag <='0';
end if;
counter8 <= counter8 + 1;
data_out_reg <= data_out_reg(6 downto 0) & data_out_reg(0);
end if;
end if;
end if;
end if;
end process;
end behavioral;
| apache-2.0 | be941122eb1b1d4fee7829c298f32b1f | 0.571214 | 3.395484 | false | false | false | false |
Rookfighter/fft-spartan6 | fft/i2c_slave_write_tb.vhd | 1 | 7,129 | -- i2c_slave_tb.vhd
--
-- Created on: 08 Jun 2017
-- Author: Fabian Meyer
library ieee;
use ieee.std_logic_1164.all;
entity i2c_slave_write_tb is
end entity;
architecture behavior of i2c_slave_write_tb is
-- Component Declaration for the Unit Under Test (UUT)
component i2c_slave
generic(RSTDEF: std_logic := '0';
ADDRDEF: std_logic_vector(6 downto 0) := "0100000");
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
swrst: in std_logic; -- software reset, RSTDEF active
en: in std_logic; -- enable, high active
tx_data: in std_logic_vector(7 downto 0); -- tx, data to send
tx_sent: out std_logic := '0'; -- tx was sent, high active
rx_data: out std_logic_vector(7 downto 0) := (others => '0'); -- rx, data received
rx_recv: out std_logic := '0'; -- rx received, high active
busy: out std_logic := '0'; -- busy, high active
sda: inout std_logic := 'Z'; -- serial data of I2C
scl: inout std_logic := 'Z'); -- serial clock of I2C
end component;
constant RSTDEF: std_logic := '0';
--Inputs
signal rst: std_logic := RSTDEF;
signal clk: std_logic := '0';
signal swrst: std_logic := RSTDEF;
signal en: std_logic := '0';
signal tx_data: std_logic_vector(7 downto 0) := (others => '0');
--BiDirs
signal sda: std_logic := '1';
signal scl: std_logic := '1';
--Outputs
signal tx_sent: std_logic;
signal rx_data: std_logic_vector(7 downto 0);
signal rx_recv: std_logic;
signal busy: std_logic;
-- Clock period definitions
constant clk_period: time := 10 ns;
begin
-- Instantiate the Unit Under Test (UUT)
uut: i2c_slave
generic map(RSTDEF => '0',
ADDRDEF => "0010111") -- address 0x17
port map(rst => rst,
clk => clk,
swrst => swrst,
en => en,
tx_data => tx_data,
tx_sent => tx_sent,
rx_data => rx_data,
rx_recv => rx_recv,
busy => busy,
sda => sda,
scl => scl);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
-- sends a single bit over I2C
procedure send_bit(tosend: std_logic) is
begin
scl <= '0';
sda <= tosend;
-- wait for delay element to take over new value
wait for 25*clk_period;
-- allow slave to read
scl <= '1';
wait for clk_period;
end procedure;
-- receive a single bit over I2C
procedure recv_bit is
begin
scl <= '0';
sda <= 'Z';
wait for clk_period;
scl <= '1';
wait for clk_period;
end procedure;
-- sends start / repeated start condition over I2C
procedure send_start is
begin
send_bit('1');
-- rise sda without changing clk
sda <= '0';
wait for 25*clk_period;
end procedure;
-- sends stop condition over I2C
procedure send_stop is
begin
send_bit('0');
-- rise sda without changing clk
sda <= '1';
wait for 25*clk_period;
end procedure;
-- wait for an ack from slave over I2C
procedure wait_ack is
begin
send_bit('Z');
-- wait additional cycle for slave to release SDA again
scl <= '0';
wait for clk_period;
end procedure;
-- send ack to slave
procedure send_ack is
begin
send_bit('0');
end procedure;
-- send nack to slave
procedure send_nack is
begin
send_bit('1');
end procedure;
begin
-- hold reset state for 100 ns.
wait for clk_period*10;
rst <= not RSTDEF;
swrst <= not RSTDEF;
en <= '1';
-- init transmission
send_start;
-- send correct address
send_bit('0'); -- address bit 1
send_bit('0'); -- address bit 2
send_bit('1'); -- address bit 3
send_bit('0'); -- address bit 4
send_bit('1'); -- address bit 5
send_bit('1'); -- address bit 6
send_bit('1'); -- address bit 7
send_bit('0'); -- direction bit
-- slave should send ack
wait_ack;
-- send data
send_bit('1'); -- data bit 1
send_bit('1'); -- data bit 2
send_bit('0'); -- data bit 3
send_bit('0'); -- data bit 4
send_bit('1'); -- data bit 5
send_bit('1'); -- data bit 6
send_bit('0'); -- data bit 7
send_bit('1'); -- data bit 8
-- rx_data should be "11001101"
-- rx_recv should '1' for one cylce
-- slave should send ack
wait_ack;
-- send data
send_bit('1'); -- data bit 1
send_bit('0'); -- data bit 2
send_bit('1'); -- data bit 3
send_bit('0'); -- data bit 4
send_bit('0'); -- data bit 5
send_bit('1'); -- data bit 6
send_bit('1'); -- data bit 7
send_bit('0'); -- data bit 8
-- rx_data should be "10100110"
-- rx_recv should '1' for one cylce
-- slave should send ack
wait_ack;
-- terminate transmission
send_stop;
-- init next transmission
send_start;
-- send wrong address 0x13
send_bit('0'); -- address bit 1
send_bit('0'); -- address bit 2
send_bit('1'); -- address bit 3
send_bit('0'); -- address bit 4
send_bit('0'); -- address bit 5
send_bit('1'); -- address bit 6
send_bit('1'); -- address bit 7
send_bit('0'); -- direction bit
-- slave should send no ack and go back to idle mode
wait_ack;
-- send data
-- slave should not record it
send_bit('0'); -- data bit 1
send_bit('0'); -- data bit 2
send_bit('1'); -- data bit 3
send_bit('0'); -- data bit 4
send_bit('0'); -- data bit 5
send_bit('1'); -- data bit 6
send_bit('0'); -- data bit 7
send_bit('1'); -- data bit 8
-- slave should send no ack and go back to idle mode
wait_ack;
-- terminate transmission
send_stop;
wait for clk_period*10;
wait;
end process;
end;
| mit | 5c5e379909db6c65539a36391b4995d0 | 0.471595 | 4.130359 | false | false | false | false |
dangpzanco/sistemas-digitais | mux19x1.vhd | 1 | 956 | library IEEE;
use IEEE.Std_Logic_1164.all;
entity mux19x1 is
port (H1, T1, U1, H2, T2, U2, H3, T3, U3, CTRL1, CTRL2, CTRL3: in std_logic_vector(7 downto 0);
mais, menos, vezes, barra, igual, dois, CTRLf: in std_logic_vector(7 downto 0);
s: in std_logic_vector(4 downto 0);
m: out std_logic_vector(7 downto 0)
);
end mux19x1;
architecture mux_estr of mux19x1 is
begin
m <= H1 when s = "00000" else
T1 when s = "00001" else
U1 when s = "00010" else
H2 when s = "00011" else
T2 when s = "00100" else
U2 when s = "00101" else
H3 when s = "00110" else
T3 when s = "00111" else
U3 when s = "01000" else
CTRL1 when s = "01001" else
CTRL2 when s = "01010" else
CTRL3 when s = "01011" else
mais when s = "01100" else
menos when s = "01101" else
vezes when s = "01110" else
barra when s = "01111" else
igual when s = "10000" else
dois when s = "10001" else
CTRLf;
end mux_estr; | mit | 5dd7e8475b404dccb7c1ad418f8fc6ed | 0.618201 | 2.438776 | false | false | false | false |
dangpzanco/sistemas-digitais | SOMA.vhd | 1 | 1,315 | library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity SOMA is
port (A, B: in std_logic_vector(7 downto 0);
F : out std_logic_vector(7 downto 0);
Flag: out std_logic_vector(3 downto 0)
);
end SOMA;
architecture c1_estr of SOMA is
signal c, Bin, S: std_logic_vector(7 downto 0);
component fulladder
port (a, b, c: in std_logic;
soma, carry: out std_logic);
end component;
begin
Bin(0) <= B(0) xor '0';
Bin(1) <= B(1) xor '0';
Bin(2) <= B(2) xor '0';
Bin(3) <= B(3) xor '0';
Bin(4) <= B(4) xor '0';
Bin(5) <= B(5) xor '0';
Bin(6) <= B(6) xor '0';
Bin(7) <= B(7) xor '0';
A0: fulladder port map (A(0), Bin(0), '0', S(0), c(0));
A1: fulladder port map (A(1), Bin(1), c(0), S(1), c(1));
A2: fulladder port map (A(2), Bin(2), c(1), S(2), c(2));
A3: fulladder port map (A(3), Bin(3), c(2), S(3), c(3));
A4: fulladder port map (A(4), Bin(4), c(3), S(4), c(4));
A5: fulladder port map (A(5), Bin(5), c(4), S(5), c(5));
A6: fulladder port map (A(6), Bin(6), c(5), S(6), c(6));
A7: fulladder port map (A(7), Bin(7), c(6), S(7), c(7));
Flag(3) <= not (S(7) or S(6) or S(5) or S(4) or S(3) or S(2) or S(1) or S(0));--zero
Flag(2) <= c(7) xor c(6);--overflow
Flag(1) <= c(7);--carryout
Flag(0) <= S(7);--negativo
F <= S;
end c1_estr;
| mit | e9308a81a53f26247db799c2a343ced2 | 0.544487 | 2.148693 | false | false | false | false |
kristofferkoch/ethersound | deltasigmachannel.vhd | 1 | 1,960 | -----------------------------------------------------------------------------
-- Delta-sigma modulator
--
-- Authors:
-- -- Kristoffer E. Koch
-----------------------------------------------------------------------------
-- Copyright 2008 Authors
--
-- This file is part of hwpulse.
--
-- hwpulse is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- hwpulse is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with hwpulse. If not, see <http://www.gnu.org/licenses/>.
-----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
entity deltasigmachannel is
Generic(N:integer:=10);
Port ( sysclk : in STD_LOGIC;
reset : in STD_LOGIC;
data : in STD_LOGIC_VECTOR (N-1 downto 0);
ds : out STD_LOGIC);
end deltasigmachannel;
architecture Behavioral of deltasigmachannel is
signal deltaAdder, sigmaAdder, sigmaReg, deltaB:unsigned(N+1 downto 0);
constant zeros:std_logic_vector(N-1 downto 0):= (OTHERS => '0');
signal hbit:std_logic;
begin
hbit <= sigmaReg(N+1);
deltaB <= unsigned(hbit & hbit & zeros);
deltaAdder <= unsigned(data) + deltaB;
sigmaAdder <= deltaAdder + sigmaReg;
process(sysclk) is
begin
if rising_edge(sysclk) then
if reset = '1' then
ds <= '0';
sigmaReg <= unsigned("01" & zeros);
else
sigmaReg <= sigmaAdder;
ds <= sigmaReg(N+1);
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | d62bdf6509581285c0b407c3243d52c5 | 0.591837 | 3.761996 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/common/lib/src/syncTog-rtl-ea.vhd | 2 | 4,792 | -------------------------------------------------------------------------------
--! @file syncTog-rtl-ea.vhd
--
--! @brief Synchronizer with toggling signal
--
--! @details This is a synchronizer that transfers an incoming signal to the
--! target clock domain with toggling signal levels.
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.global.all;
entity syncTog is
generic (
--! Stages
gStages : natural := 2;
--! Initialization level
gInit : std_logic := cInactivated
);
port (
--! Source reset
iSrc_rst : in std_logic;
--! Source clock
iSrc_clk : in std_logic;
--! Source data
iSrc_data : in std_logic;
--! Destination reset
iDst_rst : in std_logic;
--! Destination clock
iDst_clk : in std_logic;
--! Destination data
oDst_data : out std_logic
);
end syncTog;
architecture rtl of syncTog is
--! Source pulse
signal srcPulse : std_logic;
--! Transfer toggle
signal metaToggle : std_logic;
--! Transferred toggle
signal toggle : std_logic;
--! Destination pulse
signal dstPulse : std_logic;
begin
-- Output map
oDst_data <= dstPulse;
--! This is the first edge detector generating a single pulse.
FIRST_EDGE : entity work.edgedetector
port map (
iArst => iSrc_rst,
iClk => iSrc_clk,
iEnable => cActivated,
iData => iSrc_data,
oRising => srcPulse,
oFalling => open,
oAny => open
);
--! This process generates a toggling signal, controled by the rising edge
--! of the first edge detector.
GEN_TOGGLE : process(iSrc_rst, iSrc_clk)
begin
if iSrc_rst = cActivated then
metaToggle <= cInactivated;
elsif rising_edge(iSrc_clk) then
if srcPulse = cActivated then
metaToggle <= not metaToggle;
end if;
end if;
end process GEN_TOGGLE;
--! This synchronizer transfers the metaToggle to the destination clock
--! domain.
SYNC : entity work.synchronizer
generic map (
gStages => gStages,
gInit => gInit
)
port map (
iArst => iDst_rst,
iClk => iDst_clk,
iAsync => metaToggle,
oSync => toggle
);
--! The second edge detector detects any edge of the synchronized toggle.
SECOND_EDGE : entity work.edgedetector
port map (
iArst => iDst_rst,
iClk => iDst_clk,
iEnable => cActivated,
iData => toggle,
oRising => open,
oFalling => open,
oAny => dstPulse
);
end rtl;
| gpl-2.0 | 05799fc9b43f4c1b97daa5d1dde4bdc1 | 0.571369 | 4.768159 | false | false | false | false |
sergev/vak-opensource | hardware/vhd2vl/examples/for.vhd | 1 | 956 | library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
entity forp is port(
reset, sysclk : in std_logic
);
end forp;
architecture rtl of forp is
signal selection : std_logic;
signal egg_timer : std_logic_vector(6 downto 0);
begin
TIMERS :
process(reset, sysclk)
variable timer_var : integer:= 0;
variable a, i, j, k : integer;
variable zz5 : std_logic_vector(31 downto 0);
variable zz : std_logic_vector(511 downto 0);
begin
if reset = '1' then
selection <= '1';
timer_var := 2;
egg_timer <= (others => '0');
elsif sysclk'event and sysclk = '1' then
-- pulse only lasts for once cycle
selection <= '0';
egg_timer <= (others => '1');
for i in 0 to j*k loop
a := a + i;
for k in a-9 downto -14 loop
zz5 := zz(31+k downto k);
end loop; -- k
end loop; -- i
end if;
end process;
end rtl;
| apache-2.0 | 97b5b7e01dacebd908809dbbf159bec3 | 0.588912 | 3.208054 | false | false | false | false |
dqydj/VGAtonic | ColorTest/CPLD_ColorTest.vhd | 1 | 7,674 | ------------------------------------------------------------------------------------------------
-- VGAtonic Color Bar Test --
-- --
-- This code demonstrates VGA and NTSC from the same source clock, a 3.5795454 MHz --
-- colorburst signal for NTSC. Using a PLL, we multiply that source by 7 to get 25.0568 --
-- MHz - a 0.47% error from the VGA standard 25.175 MHz clock (Doing it in the reverse --
-- direction - dividing 25.175 MHz by 7 - gives a rainbow pattern for a single phase... --
-- no good) --
-- --
-- License: MIT (see root directory). --
------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity video is
Port ( CLK : in STD_LOGIC;
-- Output to PLL
CLK_OUT : out STD_LOGIC;
-- Input from a switch (go between NTSC/VGA)
MODE : in STD_LOGIC;
-- VGA Signals
PIXEL : out unsigned(7 downto 0) := "00000000";
HSYNC : out STD_LOGIC;
VSYNC : out STD_LOGIC;
-- NTSC Signals
COLORBURST : out std_logic := '0';
SYNC : out std_logic := '1';
LUMA : out unsigned(3 downto 0) := "0000";
CLK_COUNTER : inout unsigned(10 downto 0) := (others => '0');
ROW_COUNTER : inout unsigned(9 downto 0) := (others => '0')
);
end video;
architecture Behavioral of video is
-- This ring counter pulls double duty.
-- First, it divides our PLL output by 7 for the feedback (to get 25 and change MHz out of 3.5795454
-- - division here becomes multiplication)
-- Second, we have 14 phases of 3.5795454 at the same time - all the positions in the ring counter,
-- and all the 'nots'.
signal PHASE_SHIFTER : unsigned(6 downto 0) := "1111111";
begin
-- For this PLL, position (4) worked best achieving lock - you should experiment
CLK_OUT <= not PHASE_SHIFTER(4);
process (CLK, PHASE_SHIFTER, MODE)
begin
-- Got a ring counter to divide our clock into two for ~ 3.5795454 MHz colorbursts
-- Note that 'EVENT means a double edged flip flop is necessary.
if (CLK'EVENT) then
PHASE_SHIFTER <= unsigned(PHASE_SHIFTER (5 downto 0)) & not PHASE_SHIFTER(6);
end if;
-- Video generation code.
if (rising_edge(CLK)) then
if (MODE = '1') then -- NTSC Mode = '1'. Technically, NTSC-J, fine - but show me a recent TV that cares.
-- Zero out VGA signal while driving NTSC
PIXEL <= "00000000";
HSYNC <= '0';
VSYNC <= '0';
if ( (ROW_COUNTER = "0000000100") or (ROW_COUNTER = "0000000101") or (ROW_COUNTER = "0000000110")) then
-- Sync is reversed on a VSYNC line
if (CLK_COUNTER = "11000110111") then
CLK_COUNTER <= "00000000000";
-- Add another line to row counter
ROW_COUNTER <= row_counter + 1;
-- Kick off our line
SYNC <= '0';
COLORBURST <= '0';
else
CLK_COUNTER <= CLK_COUNTER + 1;
COLORBURST <= '0';
end if;
-- Front porch 0 - 38 cycles
if (clk_counter = 38) then
SYNC <= '1';
COLORBURST <= '0';
end if;
-- Sync end after 155 cycles
if (clk_counter = 156) then
SYNC <= '0';
COLORBURST <= '0';
end if;
else -- Normal, non-VSync lines with a normal reverse sync
if (clk_counter = "11000110111") then
clk_counter <= "00000000000";
if (row_counter = "0100000110") then
row_counter <= "0000000000";
else
-- Add another line to row counter
row_counter <= row_counter + 1;
end if;
-- Kick off our line
SYNC <= '1';
LUMA <= "0000";
COLORBURST <= '0';
else
clk_counter <= clk_counter + 1;
end if;
-- Front porch 0 - 38
if (clk_counter = 38) then
SYNC <= '0';
end if;
-- Sync end after 155
if (clk_counter = 156) then
SYNC <= '1';
end if;
-- After 273, real picture drawing can begin
-- Can only draw picture with row counter above 19
if (row_counter > 19) then
--Color burst - 182 to 245
if (CLK_COUNTER >= 182 and CLK_COUNTER < 245) then
COLORBURST <= PHASE_SHIFTER(0);
elsif (clk_counter >= 244 and CLK_COUNTER < 273) then
-- Voltage Ramp ?
LUMA <= "0000";
COLORBURST <= '0';
end if;
if (CLK_COUNTER >= 300 and CLK_COUNTER < 1590) then
-- Luma is the brightness of the color being sent to the screen.
-- On one of my screens (camera reverse monitor), I could see all
-- 16 steps - but the TVs didn't show the difference in the LSBs.
LUMA <= ROW_COUNTER(6 downto 3);
-- All I'm doing here is assigning colors randomly to these 4 digits of the
-- clock counter. This is your chrominance.
CASE CLK_COUNTER(9 downto 6) IS
WHEN "0000" => COLORBURST <= PHASE_SHIFTER(0);
WHEN "0001" => COLORBURST <= PHASE_SHIFTER(1);
WHEN "0010" => COLORBURST <= PHASE_SHIFTER(2);
WHEN "0011" => COLORBURST <= PHASE_SHIFTER(3);
WHEN "0100" => COLORBURST <= PHASE_SHIFTER(4);
WHEN "0101" => COLORBURST <= PHASE_SHIFTER(5);
WHEN "0110" => COLORBURST <= PHASE_SHIFTER(6);
WHEN "0111" => COLORBURST <= not PHASE_SHIFTER(0);
WHEN "1000" => COLORBURST <= not PHASE_SHIFTER(1);
WHEN "1001" => COLORBURST <= not PHASE_SHIFTER(2);
WHEN "1010" => COLORBURST <= not PHASE_SHIFTER(3);
WHEN "1011" => COLORBURST <= not PHASE_SHIFTER(4);
WHEN "1100" => COLORBURST <= not PHASE_SHIFTER(5);
WHEN "1101" => COLORBURST <= not PHASE_SHIFTER(6);
WHEN OTHERS => COLORBURST <= '0';
END CASE;
elsif clk_counter > 1590 then
LUMA <= "0000";
COLORBURST <= '0';
end if;
end if; -- End of row counter above 19
end if; -- end our 'if not lines 1-9
else -- mode = '0', so do VGA
-- Zero out control signals for NTSC
LUMA <= "0000";
COLORBURST <= '0';
SYNC <= '0';
-- Now clock counter is used to count VGA rows.
if (CLK_COUNTER = "01100100000") then
CLK_COUNTER <= "00000000000";
if (ROW_COUNTER = "1000001100") then
ROW_COUNTER <= "0000000000";
else
ROW_COUNTER <= ROW_COUNTER + 1;
end if;
else
CLK_COUNTER <= CLK_COUNTER + 1;
end if;
-- VGA sync timing
if (CLK_COUNTER >= 656 and CLK_COUNTER < 752) then
HSync <= '0';
else
HSync <= '1';
end if;
if (ROW_COUNTER = 490 or ROW_COUNTER = 491) then
VSync <= '0';
else
VSync <= '1';
end if;
-- Wow, VGA is much easier than NTSC with the color test patterns, eh?
if (ROW_COUNTER < 480 and CLK_COUNTER < 640) then
-- color
PIXEL <= ROW_COUNTER (7 downto 4) & CLK_COUNTER (7 downto 4);
else
-- color
PIXEL <= "00000000";
end if;
end if; -- End MODE Check
end if; -- end clock rising edge
end process;
end Behavioral;
| mit | 8a1f8cd9d20b2e3c43ddee3eadf0618c | 0.51264 | 3.728863 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/common/lib/src/cntRtl.vhd | 2 | 3,792 | -------------------------------------------------------------------------------
--! @file cntRtl.vhd
--
--! @brief Terminal Counter
--
--! @details The terminal counter is a synchronous counter configured
--! by several generics.
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! use global library
use work.global.all;
entity cnt is
generic (
--! Width of counter
gCntWidth : natural := 32;
--! Value that triggers the counter reset
gTcntVal : natural := 1000
);
port (
iArst : in std_logic;
iClk : in std_logic;
iEnable : in std_logic;
iSrst : in std_logic;
oCnt : out std_logic_vector(gCntWidth-1 downto 0);
oTcnt : out std_logic
);
end entity;
architecture rtl of cnt is
constant cTcntVal : std_logic_vector(gCntWidth-1 downto 0) :=
std_logic_vector(to_unsigned(gTcntVal, gCntWidth));
signal cnt, cnt_next : std_logic_vector(gCntWidth-1 downto 0);
signal tc : std_logic;
begin
-- handle wrong generics
assert (gTcntVal > 0)
report "Terminal count value of 0 makes no sense!"
severity failure;
regClk : process(iArst, iClk)
begin
if iArst = cActivated then
cnt <= (others => cInactivated);
elsif rising_edge(iClk) then
cnt <= cnt_next;
end if;
end process;
tc <= cActivated when cnt = cTcntVal else
cInactivated;
oCnt <= cnt;
oTcnt <= tc;
comb : process(iSrst, iEnable, cnt, tc)
begin
--default
cnt_next <= cnt;
if iSrst = cActivated then
cnt_next <= (others => cInactivated);
elsif iEnable = cActivated then
if tc = cActivated then
cnt_next <= (others => cInactivated);
else
cnt_next <= std_logic_vector(unsigned(cnt) + 1);
end if;
end if;
end process;
end architecture;
| gpl-2.0 | e26306b8006cddef2d8f0a51b3b95f7b | 0.607859 | 4.503563 | false | false | false | false |
hoglet67/AtomGodilVideo | src/mouse/resolution_mouse_informer.vhd | 1 | 8,237 | ------------------------------------------------------------------------
-- resolution_mouse_informer.vhd
------------------------------------------------------------------------
-- Author : Ulrich Zoltn
-- Copyright 2006 Digilent, Inc.
------------------------------------------------------------------------
-- Software version : Xilinx ISE 7.1.04i
-- WebPack
-- Device : 3s200ft256-4
------------------------------------------------------------------------
-- This file contains the logic that send the mouse_controller new
-- position of the mouse and new maximum values for the position
-- when resolution changes, so that the mouse will be centered on the
-- screen and the bounds for the new resolution are properly set.
------------------------------------------------------------------------
-- Behavioral description
------------------------------------------------------------------------
-- This module implements the logic that sets the position of the mouse
-- when the fpga is powered-up and when the resolution changes. It
-- also sets the bounds of the mouse corresponding to the currently used
-- resolution.
-- The mouse is centered for the currently selected resolution and the
-- bounds are set appropriately. This way the mouse will first appear
-- in the center in the screen at start-up and when resolution is
-- changed and cannot leave the screen.
-- The position (and similarly the bounds) is set by placing and number
-- representing the middle of the screen dimension on the value output
-- and activation the corresponding set signal (setx for horizontal
-- position, sety for vertical position, setmax_x for horizontal
-- maximum value, setmax_y for the veritcal maximum value).
------------------------------------------------------------------------
-- Port definitions
------------------------------------------------------------------------
-- clk - global clock signal
-- rst - reset signal
-- resolution - input pin, from resolution_switcher
-- - 0 for 640x480 selected resolution
-- - 1 for 800x600 selected resolution
-- switch - input pin, from resolution_switcher
-- - active for one clock period when resolution changes
-- value - output pin, 10 bits, to mouse_controller
-- - position on x or y, max value for x or y
-- - that is sent to the mouse_controller
-- setx - output pin, to mouse_controller
-- - active for one clock period when the horizontal
-- - position of the mouse cursor is valid on value output
-- sety - output pin, to mouse_controller
-- - active for one clock period when the vertical
-- - position of the mouse cursor is valid on value output
-- setmax_x - output pin, to mouse_controller
-- - active for one clock period when the horizontal
-- - maximum position of the mouse cursor is valid on
-- - value output
-- setmax_y - output pin, to mouse_controller
-- - active for one clock period when the vertical
-- - maximum position of the mouse cursor is valid on
-- - value output
------------------------------------------------------------------------
-- Revision History:
-- 09/18/2006(UlrichZ): created
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- simulation library
--library UNISIM;
--use UNISIM.VComponents.all;
-- the resolution_mouse_informer entity declaration
-- read above for behavioral description and port definitions.
entity resolution_mouse_informer is
port (
clk : in std_logic;
rst : in std_logic;
resolution : in std_logic;
switch : in std_logic;
value : out std_logic_vector(9 downto 0);
setx : out std_logic;
sety : out std_logic;
setmax_x : out std_logic;
setmax_y : out std_logic
);
end resolution_mouse_informer;
architecture Behavioral of resolution_mouse_informer is
------------------------------------------------------------------------
-- CONSTANTS
------------------------------------------------------------------------
-- center horizontal position of the mouse for 640x480 and 256x192
constant POS_X_640: std_logic_vector(9 downto 0) := "0101000000"; -- 320
constant POS_X_800: std_logic_vector(9 downto 0) := "0010000000"; -- 128
-- center vertical position of the mouse for 640x480 and 800x600
constant POS_Y_640: std_logic_vector(9 downto 0) := "0011110000"; -- 240
constant POS_Y_800: std_logic_vector(9 downto 0) := "0001100000"; -- 96
-- maximum horizontal position of the mouse for 640x480 and 800x600
constant MAX_X_640: std_logic_vector(9 downto 0) := "1001111111"; -- 639
constant MAX_X_800: std_logic_vector(9 downto 0) := "0011111111"; -- 255
-- maximum vertical position of the mouse for 640x480 and 800x600
constant MAX_Y_640: std_logic_vector(9 downto 0) := "0111011111"; -- 479
constant MAX_Y_800: std_logic_vector(9 downto 0) := "0010111111"; -- 191
constant RES_640 : std_logic := '0';
constant RES_800 : std_logic := '1';
------------------------------------------------------------------------
-- SIGNALS
------------------------------------------------------------------------
type fsm_state is (sReset,sIdle,sSetX,sSetY,sSetMaxX,sSetMaxY);
-- signal that holds the current state of the FSM
signal state: fsm_state := sIdle;
begin
-- value receives the horizontal position of the mouse, the vertical
-- position, the maximum horizontal value and maximum vertical
-- value for the active resolution when in the apropriate state
value <= POS_X_640 when state = sSetX and resolution = RES_640 else
POS_X_800 when state = sSetX and resolution = RES_800 else
POS_Y_640 when state = sSetY and resolution = RES_640 else
POS_Y_800 when state = sSetY and resolution = RES_800 else
MAX_X_640 when state = sSetMaxX and resolution = RES_640 else
MAX_X_800 when state = sSetMaxX and resolution = RES_800 else
MAX_Y_640 when state = sSetMaxY and resolution = RES_640 else
MAX_Y_800 when state = sSetMaxY and resolution = RES_800 else
(others => '0');
-- when in state sSetX, set the horizontal value for the mouse
setx <= '1' when state = sSetX else '0';
-- when in state sSetY, set the vertical value for the mouse
sety <= '1' when state = sSetY else '0';
-- when in state sSetMaxX, set the horizontal max value for the mouse
setmax_x <= '1' when state = sSetMaxX else '0';
-- when in state sSetMaxX, set the vertical max value for the mouse
setmax_y <= '1' when state = sSetMaxY else '0';
-- when a resolution switch occurs (even to the same resolution)
-- leave the idle state
-- if just powered up or reset occures go to reset state and
-- from there set the position and bounds for the mouse
manage_fsm: process(clk,rst)
begin
if(rst = '1') then
state <= sReset;
elsif(rising_edge(clk)) then
case state is
-- when reset occurs (or power-up) set the position
-- and bounds for the mouse.
when sReset =>
state <= sSetX;
-- remain in idle while switch is not active.
when sIdle =>
if(switch = '1') then
state <= sSetX;
else
state <= sIdle;
end if;
when sSetX =>
state <= sSetY;
when sSetY =>
state <= sSetMaxX;
when sSetMaxX =>
state <= sSetMaxY;
when sSetMaxY =>
state <= sIdle;
when others =>
state <= sIdle;
end case;
end if;
end process;
end Behavioral;
| apache-2.0 | 51ba7b0c4c4ca28d036bd51c3d43cc3c | 0.544737 | 4.571032 | false | false | false | false |
Rookfighter/fft-spartan6 | fft/membank.vhd | 1 | 2,495 | -- membank.vhd
--
-- Created on: 15 Jul 2017
-- Author: Fabian Meyer
--
-- 2 port memory bank component.
library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.fft_helpers.all;
entity membank is
generic(RSTDEF: std_logic := '0';
FFTEXP: natural := 4);
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
swrst: in std_logic; -- software reset, RSTDEF active
en: in std_logic; -- enable, high active
addr1: in std_logic_vector(FFTEXP-1 downto 0); -- address1
addr2: in std_logic_vector(FFTEXP-1 downto 0); -- address2
en_wrt: in std_logic; -- write enable for bank1, high active
din1: in complex; -- input1 that will be stored
din2: in complex; -- input2 that will be stored
dout1: out complex; -- output1 that is read from memory
dout2: out complex); -- output2 that is read from memory
end membank;
architecture behavioral of membank is
-- memory bank of data
signal bank: complex_arr(0 to (2**FFTEXP)-1) := (others => COMPZERO);
signal addr1_u: unsigned(FFTEXP-1 downto 0);
signal addr2_u: unsigned(FFTEXP-1 downto 0);
begin
addr1_u <= unsigned(addr1);
addr2_u <= unsigned(addr2);
process (rst, clk) is
-- reset this component
procedure reset is
begin
bank <= (others => COMPZERO);
dout1 <= COMPZERO;
dout2 <= COMPZERO;
end;
begin
if rst = RSTDEF then
reset;
elsif rising_edge(clk) then
if swrst = RSTDEF then
-- software reset to reinitialize component
-- if needed
reset;
elsif en = '1' then
-- check if write bit is set for bank1
if en_wrt = '1' then
bank(to_integer(addr1_u)) <= din1;
bank(to_integer(addr2_u)) <= din2;
else
dout1 <= bank(to_integer(addr1_u));
dout2 <= bank(to_integer(addr2_u));
end if;
end if;
end if;
end process;
end behavioral;
| mit | 0266ef5dbafea055d3986f3817b0ebb4 | 0.49499 | 4.110379 | false | false | false | false |
Wynjones1/VHDL-Build | example/vga/top.vhd | 1 | 2,369 | library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
entity top is
port( clk : in std_logic;
reset : in std_logic;
red : out std_logic_vector(2 downto 0);
green : out std_logic_vector(2 downto 0);
blue : out std_logic_vector(1 downto 0);
hs : out std_logic;
vs : out std_logic);
end top;
architecture rtl of top is
component clk_gen is
generic( CLOCK_SPEED : integer := 50_000_000;
REQUIRED_HZ : integer := 1);
port( clk : in std_logic;
reset : in std_logic;
clk_out : out std_logic);
end component;
component vga is
port(clk : in std_logic;
reset : in std_logic;
en : out std_logic;
HS : out std_logic;
VS : out std_logic;
pix_x : out integer;
pix_y : out integer);
end component;
constant CLK_HZ : integer := 50_000_000;
signal vga_clk_s : std_logic;
signal hz_clk_s : std_logic;
signal colour_s : integer range 0 to 2;
signal next_colour_s : integer range 0 to 2;
signal out_col_s : std_logic_vector(7 downto 0);
signal vga_en_s : std_logic;
begin
gen_vga_clk : clk_gen
generic map (REQUIRED_HZ => 25_000_000)
port map (clk, reset, vga_clk_s);
gen_hz_clk : clk_gen
generic map (REQUIRED_HZ => 1)
port map (clk, reset, hz_clk_s);
vga0 : vga
port map(vga_clk_s, reset, vga_en_s, hs, vs, open, open);
combinatoral:
process(colour_s)
begin
next_colour_s <= (colour_s + 1) mod 3;
if vga_en_s = '1' then
case colour_s is
when 0 => out_col_s <= "11100000";
when 1 => out_col_s <= "00011100";
when 2 => out_col_s <= "00000011";
end case;
else
out_col_s <= (others => '0');
end if;
red <= out_col_s(7 downto 5);
green <= out_col_s(4 downto 2);
blue <= out_col_s(1 downto 0);
end process;
sequential:
process(hz_clk_s, reset)
begin
if reset = '1' then
colour_s <= 0;
elsif rising_edge(hz_clk_s) then
colour_s <= next_colour_s;
end if;
end process;
end rtl;
| mit | 2e8b046e11e1e96d10278e4814de38ee | 0.506543 | 3.433333 | false | false | false | false |
ShepardSiegel/ocpi | libsrc/hdl/vhd/ocpi_props_impl.vhd | 1 | 48,781 | --
-- implementation of registered bool property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity bool_property is
generic(worker : worker_t; property : property_t; default : bool_t := bfalse);
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(0 downto 0);
value : out bool_t;
written : out bool_t
);
end entity;
architecture rtl of bool_property is begin
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
value <= default;
written <= bfalse;
elsif its(write_enable) then
value <= to_bool(data);
written <= btrue;
else
written <= bfalse;
end if;
end if;
end process;
end rtl;
--
-- implementation of registered bool property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity bool_array_property is
generic(worker : worker_t; property : property_t; default : bool_t := bfalse);
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out bool_array_t(0 to property.nitems-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
nbytes_1 : in byte_offset_t);
end entity;
architecture rtl of bool_array_property is
signal base : natural;begin
base <= to_integer(index);
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
value <= (others => default);
written <= bfalse;
any_written <= bfalse;
elsif its(write_enable) then
value(base) <= to_bool(data(0));
if nbytes_1 > 0 and property.nitems > 1 then
value(base+1) <= to_bool(data(8));
if nbytes_1 > 1 and property.nitems > 2 then
value(base+2) <= to_bool(data(16));
if nbytes_1 > 2 and property.nitems > 3 then
value(base+3) <= to_bool(data(24));
end if;
end if;
end if;
any_written <= btrue;
if base = 0 then written <= btrue; end if;
else
any_written <= bfalse;
written <= bfalse;
end if;
end if;
end process;
end rtl;
--
-- readback scalar <=32 property
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_bool_property is
generic (worker : worker_t; property : property_t);
port (value : in bool_t;
data_out : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of read_bool_property is begin
data_out <= std_logic_vector(resize(shift_left(unsigned(from_bool(value)),
(property.offset rem 4)*8),
32));
end rtl;
--v
-- readback 1 bit property array
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_bool_array_property is
generic (worker : worker_t; property : property_t);
port (value : in bool_array_t(0 to property.nitems-1);
data_out : out std_logic_vector(31 downto 0);
index : in unsigned(worker.decode_width-1 downto 0);
nbytes_1 : in byte_offset_t);
end entity;
architecture rtl of read_bool_array_property is
signal byte_offset : byte_offset_t;
begin
byte_offset <= resize(property.offset + index, byte_offset_t'length);
data_out <= from_bool_array(value,index,nbytes_1,byte_offset);
end rtl;
--
-- implementation of registered char property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity char_property is
generic(worker : worker_t; property : property_t; default : char_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(char_t'range);
value : out char_t;
written : out bool_t
);
end entity;
architecture rtl of char_property is begin
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
value <= default;
written <= bfalse;
elsif its(write_enable) then
value <= char_t(data);
written <= btrue;
else
written <= bfalse;
end if;
end if;
end process;
end rtl;
--
-- implementation of registered char property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity char_array_property is
generic(worker : worker_t; property : property_t; default : char_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out char_array_t(0 to property.nitems-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
nbytes_1 : in byte_offset_t);
end entity;
architecture rtl of char_array_property is
signal base : natural;
begin
base <= to_integer(index);
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
value <= (others => default);
written <= bfalse;
any_written <= bfalse;
elsif its(write_enable) then
value(base) <= char_t(data(7 downto 0));
if nbytes_1 > 0 and property.nitems > 1 then
value(base+1) <= char_t(data(15 downto 8));
if nbytes_1 > 1 and property.nitems > 2 then
value(base+2) <= char_t(data(23 downto 16));
if nbytes_1 > 2 and property.nitems > 3 then
value(base+3) <= char_t(data(31 downto 24));
end if;
end if;
end if;
any_written <= btrue;
if base = 0 then written <= btrue; end if;
else
written <= bfalse;
any_written <= bfalse;
end if;
end if;
end process;
end rtl;
--
-- readback scalar <=32 property
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_char_property is
generic (worker : worker_t; property : property_t);
port (value : in char_t;
data_out : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of read_char_property is begin
data_out <= std_logic_vector(resize(shift_left(unsigned((value)),
(property.offset rem 4)*8),
32));
end rtl;
--
-- readback scalar 8 bit property
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_char_array_property is
generic (worker : worker_t; property : property_t);
port (value : in char_array_t(0 to property.nitems-1);
data_out : out std_logic_vector(31 downto 0);
index : in unsigned(worker.decode_width-1 downto 0);
nbytes_1 : in byte_offset_t);
end entity;
architecture rtl of read_char_array_property is
signal i : natural;
signal word : word_t;
begin
i <= to_integer(index);
word <=
x"000000" & std_logic_vector(value(i)) when nbytes_1 = 0 else
x"0000" & std_logic_vector(value(i+1)) & std_logic_vector(value(i)) when nbytes_1 = 1 else
x"00" & std_logic_vector(value(i+2)) &
std_logic_vector(value(i+1)) & std_logic_vector(value(i)) when nbytes_1 = 2 else
std_logic_vector(value(i+3)) & std_logic_vector(value(i+2)) &
std_logic_vector(value(i+1)) & std_logic_vector(value(i));
data_out <= word_t(shift_left(unsigned(word),
((property.offset+to_integer(index)) rem 4) *8));
end rtl;
--
-- implementation of registered double property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity double_property is
generic(worker : worker_t; property : property_t; default : double_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out double_t;
written : out bool_t;
hi32 : in bool_t);
end entity;
architecture rtl of double_property is begin
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
value <= default;
written <= bfalse;
elsif its(write_enable) then
if its(hi32) then
value(63 downto 32) <= (data);
written <= btrue;
else
value(31 downto 0) <= (data);
end if;
else
written <= bfalse;
end if;
end if;
end process; end rtl;
--
-- implementation of registered double property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity double_array_property is
generic(worker : worker_t; property : property_t; default : double_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out double_array_t(0 to property.nitems-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
hi32 : in bool_t);
end entity;
architecture rtl of double_array_property is
signal base : natural;begin
base <= to_integer(index);
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
value <= (others => default);
written <= bfalse;
any_written <= bfalse;
elsif its(write_enable) then
if its(hi32) then
value(base)(63 downto 32) <= (data);
-- for little endian machines that do a store64
if base = 0 then written <= btrue; end if;
else
value(base)(31 downto 0) <= (data);
end if;
any_written <= btrue;
else
written <= bfalse;
any_written <= bfalse;
end if;
end if;
end process;
end rtl;
--
-- readback scalar >32 property
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_double_property is
generic (worker : worker_t; property : property_t);
port (value : in double_t;
hi32 : in bool_t;
data_out : out std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of read_double_property is begin
data_out <= std_logic_vector(value(63 downto 32)) when its(hi32)
else std_logic_vector(value(31 downto 0));
end rtl;
--
-- readback scalar 64 bit property
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_double_array_property is
generic (worker : worker_t; property : property_t);
port (value : in double_array_t(0 to property.nitems-1);
data_out : out std_logic_vector(31 downto 0);
index : in unsigned(worker.decode_width-1 downto 0);
hi32 : in bool_t);
end entity;
architecture rtl of read_double_array_property is
signal i : natural;
begin
i <= to_integer(index);
data_out <= std_logic_vector(value(i)(63 downto 32)) when its(hi32) else
std_logic_vector(value(i)(31 downto 0));
end rtl;
--
-- implementation of registered float property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity float_property is
generic(worker : worker_t; property : property_t; default : float_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(float_t'range);
value : out float_t;
written : out bool_t
);
end entity;
architecture rtl of float_property is begin
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
value <= default;
written <= bfalse;
elsif its(write_enable) then
value <= float_t(data);
written <= btrue;
else
written <= bfalse;
end if;
end if;
end process;
end rtl;
--
-- implementation of registered float property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity float_array_property is
generic(worker : worker_t; property : property_t; default : float_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out float_array_t(0 to property.nitems-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
nbytes_1 : in byte_offset_t);
end entity;
architecture rtl of float_array_property is
signal base : natural;
begin
base <= to_integer(index);
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
value <= (others => default);
written <= bfalse;
any_written <= bfalse;
elsif its(write_enable) then
value(base) <= float_t(data);
any_written <= btrue;
if base = 0 then written <= btrue; end if;
else
written <= bfalse;
any_written <= bfalse;
end if;
end if;
end process;
end rtl;
--
-- readback scalar <=32 property
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_float_property is
generic (worker : worker_t; property : property_t);
port (value : in float_t;
data_out : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of read_float_property is begin
data_out <= std_logic_vector(resize(shift_left(unsigned((value)),
(property.offset rem 4)*8),
32));
end rtl;
--
-- readback scalar 16 bit property
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_float_array_property is
generic (worker : worker_t; property : property_t);
port (value : in float_array_t(0 to property.nitems-1);
data_out : out std_logic_vector(31 downto 0);
index : in unsigned(worker.decode_width-1 downto 0);
nbytes_1 : in byte_offset_t);
end entity;
architecture rtl of read_float_array_property is
begin
data_out <= std_logic_vector(value(to_integer(index)));
end rtl;
--
-- implementation of registered short property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity short_property is
generic(worker : worker_t; property : property_t; default : short_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(short_t'range);
value : out short_t;
written : out bool_t
);
end entity;
architecture rtl of short_property is begin
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
value <= default;
written <= bfalse;
elsif its(write_enable) then
value <= short_t(data);
written <= btrue;
else
written <= bfalse;
end if;
end if;
end process;
end rtl;
--
-- implementation of registered short property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity short_array_property is
generic(worker : worker_t; property : property_t; default : short_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out short_array_t(0 to property.nitems-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
nbytes_1 : in byte_offset_t);
end entity;
architecture rtl of short_array_property is
signal base : natural;
begin
base <= to_integer(index);
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
value <= (others => default);
written <= bfalse;
any_written <= bfalse;
elsif its(write_enable) then
value(base) <= short_t(data(15 downto 0));
if nbytes_1 > 1 and property.nitems > 1 then
value(base+1) <= short_t(data(31 downto 16));
end if;
any_written <= btrue;
if base = 0 then written <= btrue; end if;
else
written <= bfalse;
any_written <= bfalse;
end if;
end if;
end process;
end rtl;
--
-- readback scalar <=32 property
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_short_property is
generic (worker : worker_t; property : property_t);
port (value : in short_t;
data_out : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of read_short_property is begin
data_out <= std_logic_vector(resize(shift_left(unsigned((value)),
(property.offset rem 4)*8),
32));
end rtl;
--
-- readback scalar 16 bit property
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_short_array_property is
generic (worker : worker_t; property : property_t);
port (value : in short_array_t(0 to property.nitems-1);
data_out : out std_logic_vector(31 downto 0);
index : in unsigned(worker.decode_width-1 downto 0);
nbytes_1 : in byte_offset_t);
end entity;
architecture rtl of read_short_array_property is
signal i : natural;
begin
i <= to_integer(index);
data_out <=
std_logic_vector(value(i)) & x"0000" when (to_integer(index) + property.offset/2) rem 2 = 1 else
x"0000" & std_logic_vector(value(i)) when nbytes_1 = 1 else
std_logic_vector(value(i+1)) & std_logic_vector(value(i));
end rtl;
--
-- implementation of registered long property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity long_property is
generic(worker : worker_t; property : property_t; default : long_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(long_t'range);
value : out long_t;
written : out bool_t
);
end entity;
architecture rtl of long_property is begin
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
value <= default;
written <= bfalse;
elsif its(write_enable) then
value <= long_t(data);
written <= btrue;
else
written <= bfalse;
end if;
end if;
end process;
end rtl;
--
-- implementation of registered long property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity long_array_property is
generic(worker : worker_t; property : property_t; default : long_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out long_array_t(0 to property.nitems-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
nbytes_1 : in byte_offset_t);
end entity;
architecture rtl of long_array_property is
signal base : natural;
begin
base <= to_integer(index);
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
value <= (others => default);
written <= bfalse;
any_written <= bfalse;
elsif its(write_enable) then
value(base) <= long_t(data);
any_written <= btrue;
if base = 0 then written <= btrue; end if;
else
written <= bfalse;
any_written <= bfalse;
end if;
end if;
end process;
end rtl;
--
-- readback scalar <=32 property
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_long_property is
generic (worker : worker_t; property : property_t);
port (value : in long_t;
data_out : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of read_long_property is begin
data_out <= std_logic_vector(resize(shift_left(unsigned((value)),
(property.offset rem 4)*8),
32));
end rtl;
--
-- readback scalar 16 bit property
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_long_array_property is
generic (worker : worker_t; property : property_t);
port (value : in long_array_t(0 to property.nitems-1);
data_out : out std_logic_vector(31 downto 0);
index : in unsigned(worker.decode_width-1 downto 0);
nbytes_1 : in byte_offset_t);
end entity;
architecture rtl of read_long_array_property is
begin
data_out <= std_logic_vector(value(to_integer(index)));
end rtl;
--
-- implementation of registered uchar property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity uchar_property is
generic(worker : worker_t; property : property_t; default : uchar_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(uchar_t'range);
value : out uchar_t;
written : out bool_t
);
end entity;
architecture rtl of uchar_property is begin
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
value <= default;
written <= bfalse;
elsif its(write_enable) then
value <= uchar_t(data);
written <= btrue;
else
written <= bfalse;
end if;
end if;
end process;
end rtl;
--
-- implementation of registered uchar property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity uchar_array_property is
generic(worker : worker_t; property : property_t; default : uchar_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out uchar_array_t(0 to property.nitems-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
nbytes_1 : in byte_offset_t);
end entity;
architecture rtl of uchar_array_property is
signal base : natural;
begin
base <= to_integer(index);
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
value <= (others => default);
written <= bfalse;
any_written <= bfalse;
elsif its(write_enable) then
value(base) <= uchar_t(data(7 downto 0));
if nbytes_1 > 0 and property.nitems > 1 then
value(base+1) <= uchar_t(data(15 downto 8));
if nbytes_1 > 1 and property.nitems > 2 then
value(base+2) <= uchar_t(data(23 downto 16));
if nbytes_1 > 2 and property.nitems > 3 then
value(base+3) <= uchar_t(data(31 downto 24));
end if;
end if;
end if;
any_written <= btrue;
if base = 0 then written <= btrue; end if;
else
written <= bfalse;
any_written <= bfalse;
end if;
end if;
end process;
end rtl;
--
-- readback scalar <=32 property
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_uchar_property is
generic (worker : worker_t; property : property_t);
port (value : in uchar_t;
data_out : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of read_uchar_property is begin
data_out <= std_logic_vector(resize(shift_left(unsigned((value)),
(property.offset rem 4)*8),
32));
end rtl;
--
-- readback scalar 8 bit property
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_uchar_array_property is
generic (worker : worker_t; property : property_t);
port (value : in uchar_array_t(0 to property.nitems-1);
data_out : out std_logic_vector(31 downto 0);
index : in unsigned(worker.decode_width-1 downto 0);
nbytes_1 : in byte_offset_t);
end entity;
architecture rtl of read_uchar_array_property is
signal i : natural;
signal word : word_t;
begin
i <= to_integer(index);
word <=
x"000000" & std_logic_vector(value(i)) when nbytes_1 = 0 else
x"0000" & std_logic_vector(value(i+1)) & std_logic_vector(value(i)) when nbytes_1 = 1 else
x"00" & std_logic_vector(value(i+2)) &
std_logic_vector(value(i+1)) & std_logic_vector(value(i)) when nbytes_1 = 2 else
std_logic_vector(value(i+3)) & std_logic_vector(value(i+2)) &
std_logic_vector(value(i+1)) & std_logic_vector(value(i));
data_out <= word_t(shift_left(unsigned(word),
((property.offset+to_integer(index)) rem 4) *8));
end rtl;
--
-- implementation of registered ulong property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity ulong_property is
generic(worker : worker_t; property : property_t; default : ulong_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(ulong_t'range);
value : out ulong_t;
written : out bool_t
);
end entity;
architecture rtl of ulong_property is begin
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
value <= default;
written <= bfalse;
elsif its(write_enable) then
value <= ulong_t(data);
written <= btrue;
else
written <= bfalse;
end if;
end if;
end process;
end rtl;
--
-- implementation of registered ulong property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity ulong_array_property is
generic(worker : worker_t; property : property_t; default : ulong_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out ulong_array_t(0 to property.nitems-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
nbytes_1 : in byte_offset_t);
end entity;
architecture rtl of ulong_array_property is
signal base : natural;
begin
base <= to_integer(index);
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
value <= (others => default);
written <= bfalse;
any_written <= bfalse;
elsif its(write_enable) then
value(base) <= ulong_t(data);
any_written <= btrue;
if base = 0 then written <= btrue; end if;
else
written <= bfalse;
any_written <= bfalse;
end if;
end if;
end process;
end rtl;
--
-- readback scalar <=32 property
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_ulong_property is
generic (worker : worker_t; property : property_t);
port (value : in ulong_t;
data_out : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of read_ulong_property is begin
data_out <= std_logic_vector(resize(shift_left(unsigned((value)),
(property.offset rem 4)*8),
32));
end rtl;
--
-- readback scalar 16 bit property
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_ulong_array_property is
generic (worker : worker_t; property : property_t);
port (value : in ulong_array_t(0 to property.nitems-1);
data_out : out std_logic_vector(31 downto 0);
index : in unsigned(worker.decode_width-1 downto 0);
nbytes_1 : in byte_offset_t);
end entity;
architecture rtl of read_ulong_array_property is
begin
data_out <= std_logic_vector(value(to_integer(index)));
end rtl;
--
-- implementation of registered ushort property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity ushort_property is
generic(worker : worker_t; property : property_t; default : ushort_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(ushort_t'range);
value : out ushort_t;
written : out bool_t
);
end entity;
architecture rtl of ushort_property is begin
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
value <= default;
written <= bfalse;
elsif its(write_enable) then
value <= ushort_t(data);
written <= btrue;
else
written <= bfalse;
end if;
end if;
end process;
end rtl;
--
-- implementation of registered ushort property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity ushort_array_property is
generic(worker : worker_t; property : property_t; default : ushort_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out ushort_array_t(0 to property.nitems-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
nbytes_1 : in byte_offset_t);
end entity;
architecture rtl of ushort_array_property is
signal base : natural;
begin
base <= to_integer(index);
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
value <= (others => default);
written <= bfalse;
any_written <= bfalse;
elsif its(write_enable) then
value(base) <= ushort_t(data(15 downto 0));
if nbytes_1 > 1 and property.nitems > 1 then
value(base+1) <= ushort_t(data(31 downto 16));
end if;
any_written <= btrue;
if base = 0 then written <= btrue; end if;
else
written <= bfalse;
any_written <= bfalse;
end if;
end if;
end process;
end rtl;
--
-- readback scalar <=32 property
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_ushort_property is
generic (worker : worker_t; property : property_t);
port (value : in ushort_t;
data_out : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of read_ushort_property is begin
data_out <= std_logic_vector(resize(shift_left(unsigned((value)),
(property.offset rem 4)*8),
32));
end rtl;
--
-- readback scalar 16 bit property
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_ushort_array_property is
generic (worker : worker_t; property : property_t);
port (value : in ushort_array_t(0 to property.nitems-1);
data_out : out std_logic_vector(31 downto 0);
index : in unsigned(worker.decode_width-1 downto 0);
nbytes_1 : in byte_offset_t);
end entity;
architecture rtl of read_ushort_array_property is
signal i : natural;
begin
i <= to_integer(index);
data_out <=
std_logic_vector(value(i)) & x"0000" when (to_integer(index) + property.offset/2) rem 2 = 1 else
x"0000" & std_logic_vector(value(i)) when nbytes_1 = 1 else
std_logic_vector(value(i+1)) & std_logic_vector(value(i));
end rtl;
--
-- implementation of registered longlong property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity longlong_property is
generic(worker : worker_t; property : property_t; default : longlong_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out longlong_t;
written : out bool_t;
hi32 : in bool_t);
end entity;
architecture rtl of longlong_property is begin
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
value <= default;
written <= bfalse;
elsif its(write_enable) then
if its(hi32) then
value(63 downto 32) <= signed(data);
written <= btrue;
else
value(31 downto 0) <= signed(data);
end if;
else
written <= bfalse;
end if;
end if;
end process; end rtl;
--
-- implementation of registered longlong property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity longlong_array_property is
generic(worker : worker_t; property : property_t; default : longlong_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out longlong_array_t(0 to property.nitems-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
hi32 : in bool_t);
end entity;
architecture rtl of longlong_array_property is
signal base : natural;begin
base <= to_integer(index);
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
value <= (others => default);
written <= bfalse;
any_written <= bfalse;
elsif its(write_enable) then
if its(hi32) then
value(base)(63 downto 32) <= signed(data);
-- for little endian machines that do a store64
if base = 0 then written <= btrue; end if;
else
value(base)(31 downto 0) <= signed(data);
end if;
any_written <= btrue;
else
written <= bfalse;
any_written <= bfalse;
end if;
end if;
end process;
end rtl;
--
-- readback scalar >32 property
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_longlong_property is
generic (worker : worker_t; property : property_t);
port (value : in longlong_t;
hi32 : in bool_t;
data_out : out std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of read_longlong_property is begin
data_out <= std_logic_vector(value(63 downto 32)) when its(hi32)
else std_logic_vector(value(31 downto 0));
end rtl;
--
-- readback scalar 64 bit property
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_longlong_array_property is
generic (worker : worker_t; property : property_t);
port (value : in longlong_array_t(0 to property.nitems-1);
data_out : out std_logic_vector(31 downto 0);
index : in unsigned(worker.decode_width-1 downto 0);
hi32 : in bool_t);
end entity;
architecture rtl of read_longlong_array_property is
signal i : natural;
begin
i <= to_integer(index);
data_out <= std_logic_vector(value(i)(63 downto 32)) when its(hi32) else
std_logic_vector(value(i)(31 downto 0));
end rtl;
--
-- implementation of registered ulonglong property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity ulonglong_property is
generic(worker : worker_t; property : property_t; default : ulonglong_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out ulonglong_t;
written : out bool_t;
hi32 : in bool_t);
end entity;
architecture rtl of ulonglong_property is begin
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
value <= default;
written <= bfalse;
elsif its(write_enable) then
if its(hi32) then
value(63 downto 32) <= unsigned(data);
written <= btrue;
else
value(31 downto 0) <= unsigned(data);
end if;
else
written <= bfalse;
end if;
end if;
end process; end rtl;
--
-- implementation of registered ulonglong property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity ulonglong_array_property is
generic(worker : worker_t; property : property_t; default : ulonglong_t := (others => '0'));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out ulonglong_array_t(0 to property.nitems-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
hi32 : in bool_t);
end entity;
architecture rtl of ulonglong_array_property is
signal base : natural;begin
base <= to_integer(index);
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
value <= (others => default);
written <= bfalse;
any_written <= bfalse;
elsif its(write_enable) then
if its(hi32) then
value(base)(63 downto 32) <= unsigned(data);
-- for little endian machines that do a store64
if base = 0 then written <= btrue; end if;
else
value(base)(31 downto 0) <= unsigned(data);
end if;
any_written <= btrue;
else
written <= bfalse;
any_written <= bfalse;
end if;
end if;
end process;
end rtl;
--
-- readback scalar >32 property
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_ulonglong_property is
generic (worker : worker_t; property : property_t);
port (value : in ulonglong_t;
hi32 : in bool_t;
data_out : out std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of read_ulonglong_property is begin
data_out <= std_logic_vector(value(63 downto 32)) when its(hi32)
else std_logic_vector(value(31 downto 0));
end rtl;
--
-- readback scalar 64 bit property
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_ulonglong_array_property is
generic (worker : worker_t; property : property_t);
port (value : in ulonglong_array_t(0 to property.nitems-1);
data_out : out std_logic_vector(31 downto 0);
index : in unsigned(worker.decode_width-1 downto 0);
hi32 : in bool_t);
end entity;
architecture rtl of read_ulonglong_array_property is
signal i : natural;
begin
i <= to_integer(index);
data_out <= std_logic_vector(value(i)(63 downto 32)) when its(hi32) else
std_logic_vector(value(i)(31 downto 0));
end rtl;
--
-- implementation of registered string property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity string_property is
generic(worker : worker_t; property : property_t; default : string_t := ("00000000","00000000"));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out string_t(0 to property.string_length);
written : out bool_t;
offset : in unsigned(worker.decode_width-1 downto 0));
end entity;
architecture rtl of string_property is
signal base : natural;begin
base <= to_integer(offset);
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
value <= (others => to_signed(0,char_t'length));
written <= bfalse;
elsif its(write_enable) then
value (base to base + 3) <= to_string(data);
written <= btrue;
else
written <= bfalse;
end if;
end if;
end process;
end rtl;
--
-- implementation of registered string property value, with write pulse
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity string_array_property is
generic(worker : worker_t; property : property_t; default : string_array_t := (("00000000","00000000"),("00000000","00000000")));
port (clk : in std_logic;
reset : in bool_t;
write_enable : in bool_t;
data : in std_logic_vector(31 downto 0);
value : out string_array_t(0 to property.nitems-1,
0 to (property.string_length+4)/4*4-1);
written : out bool_t;
index : in unsigned(worker.decode_width-1 downto 0);
any_written : out bool_t;
offset : in unsigned(worker.decode_width-1 downto 0));
end entity;
--
-- readback string property
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_string_property is
generic (worker : worker_t; property : property_t);
port (value : in string_t;
data_out : out std_logic_vector(31 downto 0);
offset : in unsigned(worker.decode_width-1 downto 0));
end entity;
architecture rtl of read_string_property is begin
data_out <= from_string(value, offset);
end rtl;
--
-- readback scalar string property
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all; use ocpi.ocp.all;
entity read_string_array_property is
generic (worker : worker_t; property : property_t);
port (value : in string_array_t(0 to property.nitems-1,
0 to (property.string_length+4)/4*4-1);
data_out : out std_logic_vector(31 downto 0);
offset : in unsigned(worker.decode_width-1 downto 0));
end entity;
architecture rtl of string_array_property is
constant nwords : natural := (property.string_length+4)/4;
subtype string_words_t is data_a_t(0 to nwords * property.nitems-1);
signal string_words : string_words_t;
begin
gen: for i in 0 to property.nitems-1 generate -- properties'left to 0 generate
gen1: for j in 0 to nwords-1 generate
gen2: for k in 0 to 3 generate
value(i,j*4+k) <= signed(string_words(i*nwords + j)(k*8+7 downto k*8));
end generate gen2;
end generate gen1;
end generate gen;
reg: process(Clk) is
begin
if rising_edge(clk) then
if its(reset) then
string_words(0) <= (others => '0');
written <= bfalse;
any_written <= bfalse;
elsif its(write_enable) then
string_words(to_integer(offset) / 4) <= data;
written <= btrue;
if to_integer(offset) = 0 then
any_written <= btrue;
end if;
else
written <= bfalse;
any_written <= bfalse;
end if;
end if;
end process;
end rtl;
architecture rtl of read_string_array_property is
constant nwords : natural := (property.string_length+4)/4;
subtype string_words_t is data_a_t(0 to nwords * property.nitems-1);
signal string_words : string_words_t;
begin
gen: for i in 0 to property.nitems-1 generate -- properties'left to 0 generate
gen1: for j in 0 to nwords-1 generate
gen2: for k in 0 to 3 generate
string_words(i*nwords + j)(k*8+7 downto k*8) <= std_logic_vector(value(i,j*4+k));
end generate gen2;
end generate gen1;
end generate gen;
data_out <= string_words(to_integer(offset)/4);
end rtl;
| lgpl-3.0 | fb01ca7b43b7a9e5f03262029ed9ef84 | 0.608885 | 3.332718 | false | false | false | false |
sergev/vak-opensource | hardware/dlx/bv_test-bench.vhdl | 1 | 34,607 | --------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: bv_test-bench.vhdl,v $ $Revision: 2.1 $ $Date: 1993/10/31 20:13:16 $
--
--------------------------------------------------------------------------
--
-- Architecture for test bench for bit vector arithmetic package.
--
use std.textio.all, work.bv_arithmetic.all;
architecture bench of bv_test is
begin
process
variable L : line;
variable byte : bit_vector(0 to 7);
variable word : bit_vector(1 to 32);
variable half_byte : bit_vector(1 to 4);
variable overflow, div_by_zero, result : boolean;
begin
WAIT for 1 ns;
----------------------------------------------------------------
----------------------------------------------------------------
-- test bit_vector to numeric conversions
----------------------------------------------------------------
----------------------------------------------------------------
write(L, string'("Testing bv_to_natural:"));
writeline(output, L);
write(L, string'(" bv_to_natural(X""02"") = "));
write(L, bv_to_natural(X"02"));
writeline(output, L);
assert bv_to_natural(X"02") = 2;
write(L, string'(" bv_to_natural(X""FE"") = "));
write(L, bv_to_natural(X"FE"));
writeline(output, L);
assert bv_to_natural(X"FE") = 254;
----------------------------------------------------------------
write(L, string'("Testing natural_to_bv:"));
writeline(output, L);
write(L, string'(" natural_to_bv(2) = "));
write(L, natural_to_bv(2, 8));
writeline(output, L);
assert natural_to_bv(2, 8) = X"02";
write(L, string'(" natural_to_bv(254) = "));
write(L, natural_to_bv(254, 8));
writeline(output, L);
assert natural_to_bv(254, 8) = X"FE";
----------------------------------------------------------------
write(L, string'("Testing bv_to_integer:"));
writeline(output, L);
write(L, string'(" bv_to_integer(X""02"") = "));
write(L, bv_to_integer(X"02"));
writeline(output, L);
assert bv_to_integer(X"02") = 2;
write(L, string'(" bv_to_integer(X""FE"") = "));
write(L, bv_to_integer(X"FE"));
writeline(output, L);
assert bv_to_integer(X"FE") = -2;
----------------------------------------------------------------
write(L, string'("Testing integer_to_bv:"));
writeline(output, L);
write(L, string'(" integer_to_bv(2) = "));
write(L, integer_to_bv(2, 8));
writeline(output, L);
assert integer_to_bv(2, 8) = X"02";
write(L, string'(" integer_to_bv(-2) = "));
write(L, integer_to_bv(-2, 8));
writeline(output, L);
assert integer_to_bv(-2, 8) = X"FE";
----------------------------------------------------------------
----------------------------------------------------------------
-- Arithmetic operations
----------------------------------------------------------------
----------------------------------------------------------------
----------------------------------------------------------------
-- bv_add: Signed addition with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_add with overflow:"));
writeline(output, L);
write(L, string'(" 2+2 = "));
bv_add(X"02", X"02", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"04" and not overflow;
write(L, string'(" 2+(-3) = "));
bv_add(X"02", X"FD", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"FF" and not overflow;
write(L, string'(" 64+64 = "));
bv_add(X"40", X"40", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and overflow;
write(L, string'(" -64+(-64) = "));
bv_add(X"C0", X"C0", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not overflow;
----------------------------------------------------------------
-- "+": Signed addition without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing ""+"" without overflow:"));
writeline(output, L);
write(L, string'(" 2+2 = "));
byte := X"02" + X"02";
write(L, byte);
writeline(output, L);
assert byte = X"04";
write(L, string'(" 2+(-3) = "));
byte := X"02" + X"FD";
write(L, byte);
writeline(output, L);
assert byte = X"FF";
write(L, string'(" 64+64 = "));
byte := X"40" + X"40";
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" -64+(-64) = "));
byte := X"C0" + X"C0";
write(L, byte);
writeline(output, L);
assert byte = X"80";
----------------------------------------------------------------
-- bv_sub: Signed subtraction with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_sub with overflow:"));
writeline(output, L);
write(L, string'(" 2-2 = "));
bv_sub(X"02", X"02", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and not overflow;
write(L, string'(" 2-(-3) = "));
bv_sub(X"02", X"FD", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"05" and not overflow;
write(L, string'(" 64-(-64) = "));
bv_sub(X"40", X"C0", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and overflow;
write(L, string'(" -64-64 = "));
bv_sub(X"C0", X"40", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not overflow;
----------------------------------------------------------------
-- "-": Signed subtraction without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing ""-"" without overflow:"));
writeline(output, L);
write(L, string'(" 2-2 = "));
byte := X"02" - X"02";
write(L, byte);
writeline(output, L);
assert byte = X"00";
write(L, string'(" 2-(-3) = "));
byte := X"02" - X"FD";
write(L, byte);
writeline(output, L);
assert byte = X"05";
write(L, string'(" 64-(-64) = "));
byte := X"40" - X"C0";
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" -64-64 = "));
byte := X"C0" - X"40";
write(L, byte);
writeline(output, L);
assert byte = X"80";
----------------------------------------------------------------
-- bv_addu: Unsigned addition with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_addu with overflow:"));
writeline(output, L);
write(L, string'(" 2+2 = "));
bv_addu(X"02", X"02", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"04" and not overflow;
write(L, string'(" 64+64 = "));
bv_addu(X"40", X"40", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not overflow;
write(L, string'(" 128+128 = "));
bv_addu(X"80", X"80", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and overflow;
----------------------------------------------------------------
-- bv_addu: Unsigned addition without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_addu without overflow:"));
writeline(output, L);
write(L, string'(" 2+2 = "));
bv_addu(X"02", X"02", byte);
write(L, byte);
writeline(output, L);
assert byte = X"04";
write(L, string'(" 64+64 = "));
bv_addu(X"40", X"40", byte);
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" 128+128 = "));
bv_addu(X"80", X"80", byte);
write(L, byte);
writeline(output, L);
assert byte = X"00";
----------------------------------------------------------------
-- bv_subu: Unsigned subtraction with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_subu with overflow:"));
writeline(output, L);
write(L, string'(" 3-2 = "));
bv_subu(X"03", X"02", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"01" and not overflow;
write(L, string'(" 64-64 = "));
bv_subu(X"40", X"40", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and not overflow;
write(L, string'(" 64-128 = "));
bv_subu(X"40", X"80", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"C0" and overflow;
----------------------------------------------------------------
-- bv_subu: Unsigned subtraction without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_subu without overflow:"));
writeline(output, L);
write(L, string'(" 3-2 = "));
bv_subu(X"03", X"02", byte);
write(L, byte);
writeline(output, L);
assert byte = X"01";
write(L, string'(" 64-64 = "));
bv_subu(X"40", X"40", byte);
write(L, byte);
writeline(output, L);
assert byte = X"00";
write(L, string'(" 64-128 = "));
bv_subu(X"40", X"80", byte);
write(L, byte);
writeline(output, L);
assert byte = X"C0";
----------------------------------------------------------------
-- bv_neg: Signed negation with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_neg with overflow:"));
writeline(output, L);
write(L, string'(" -(3) = "));
bv_neg(X"03", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"FD" and not overflow;
write(L, string'(" -(-3) = "));
bv_neg(X"FD", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"03" and not overflow;
write(L, string'(" -(127) = "));
bv_neg(X"7F", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"81" and not overflow;
write(L, string'(" -(-128) = "));
bv_neg(X"80", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and overflow;
----------------------------------------------------------------
-- "-": Signed negation without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing ""-"" without overflow:"));
writeline(output, L);
write(L, string'(" -(3) = "));
byte := - X"03";
write(L, byte);
writeline(output, L);
assert byte = X"FD";
write(L, string'(" -(-3) = "));
byte := - X"FD";
write(L, byte);
writeline(output, L);
assert byte = X"03";
write(L, string'(" -(127) = "));
byte := - X"7F";
write(L, byte);
writeline(output, L);
assert byte = X"81";
write(L, string'(" -(-128) = "));
byte := - X"80";
write(L, byte);
writeline(output, L);
assert byte = X"80";
----------------------------------------------------------------
-- bv_mult: Signed multiplication with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_mult with overflow:"));
writeline(output, L);
write(L, string'(" 5*(-3) = "));
bv_mult(X"05", X"FD", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"F1" and not overflow;
write(L, string'(" (-5)*(-3) = "));
bv_mult(X"FB", X"FD", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"0F" and not overflow;
write(L, string'(" 16*8 = "));
bv_mult(X"10", X"08", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and overflow;
write(L, string'(" 16*16 = "));
bv_mult(X"10", X"10", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and overflow;
write(L, string'(" 16*(-8) = "));
bv_mult(X"10", X"F8", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not overflow;
write(L, string'(" 16*(-16) = "));
bv_mult(X"10", X"F0", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and overflow;
----------------------------------------------------------------
-- "*": Signed multiplication without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing ""*"" without overflow:"));
writeline(output, L);
write(L, string'(" 5*(-3) = "));
byte := X"05" * X"FD";
write(L, byte);
writeline(output, L);
assert byte = X"F1";
write(L, string'(" (-5)*(-3) = "));
byte := X"FB" * X"FD";
write(L, byte);
writeline(output, L);
assert byte = X"0F";
write(L, string'(" 16*8 = "));
byte := X"10" * X"08";
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" 16*16 = "));
byte := X"10" * X"10";
write(L, byte);
writeline(output, L);
assert byte = X"00";
write(L, string'(" 16*(-8) = "));
byte := X"10" * X"F8";
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" 16*(-16) = "));
byte := X"10" * X"F0";
write(L, byte);
writeline(output, L);
assert byte = X"00";
----------------------------------------------------------------
-- bv_multu: Unsigned multiplication with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_multu with overflow:"));
writeline(output, L);
write(L, string'(" 5*7 = "));
bv_multu(X"05", X"07", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"23" and not overflow;
write(L, string'(" 16*8 = "));
bv_multu(X"10", X"08", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not overflow;
write(L, string'(" 16*16 = "));
bv_multu(X"10", X"10", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and overflow;
----------------------------------------------------------------
-- bv_multu: Unsigned multiplication without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_multu without overflow:"));
writeline(output, L);
write(L, string'(" 5*7 = "));
bv_multu(X"05", X"07", byte);
write(L, byte);
writeline(output, L);
assert byte = X"23";
write(L, string'(" 16*8 = "));
bv_multu(X"10", X"08", byte);
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" 16*16 = "));
bv_multu(X"10", X"10", byte);
write(L, byte);
writeline(output, L);
assert byte = X"00";
----------------------------------------------------------------
-- bv_div: Signed division with divide by zero and overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_div with flags:"));
writeline(output, L);
write(L, string'(" 7/2 = "));
bv_div(X"07", X"02", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"03" and not div_by_zero and not overflow;
write(L, string'(" -7/2 = "));
bv_div(X"F9", X"02", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"FD" and not div_by_zero and not overflow;
write(L, string'(" 7/-2 = "));
bv_div(X"07", X"FE", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"FD" and not div_by_zero and not overflow;
write(L, string'(" -7/-2 = "));
bv_div(X"F9", X"FE", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"03" and not div_by_zero and not overflow;
write(L, string'(" -128/1 = "));
bv_div(X"80", X"01", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not div_by_zero and not overflow;
write(L, string'(" -128/-1 = "));
bv_div(X"80", X"FF", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not div_by_zero and overflow;
write(L, string'(" -16/0 = "));
bv_div(X"F0", X"00", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and div_by_zero and not overflow;
----------------------------------------------------------------
-- "/": Signed division without divide by zero and overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing ""/"" without flags:"));
writeline(output, L);
write(L, string'(" 7/2 = "));
byte := X"07" / X"02";
write(L, byte);
writeline(output, L);
assert byte = X"03";
write(L, string'(" -7/2 = "));
byte := X"F9" / X"02";
write(L, byte);
writeline(output, L);
assert byte = X"FD";
write(L, string'(" 7/-2 = "));
byte := X"07" / X"FE";
write(L, byte);
writeline(output, L);
assert byte = X"FD";
write(L, string'(" -7/-2 = "));
byte := X"F9" / X"FE";
write(L, byte);
writeline(output, L);
assert byte = X"03";
write(L, string'(" -128/1 = "));
byte := X"80" / X"01";
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" -128/-1 = "));
byte := X"80" / X"FF";
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" -16/0 = "));
byte := X"F0" / X"00";
write(L, byte);
writeline(output, L);
assert byte = X"00";
----------------------------------------------------------------
-- bv_divu: Unsigned division with divide by zero detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_divu with flag:"));
writeline(output, L);
write(L, string'(" 7/2 = "));
bv_divu(X"07", X"02", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"03" and not div_by_zero;
write(L, string'(" 14/7 = "));
bv_divu(X"0E", X"07", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"02" and not div_by_zero;
write(L, string'(" 16/1 = "));
bv_divu(X"10", X"01", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"10" and not div_by_zero;
write(L, string'(" 16/0 = "));
bv_divu(X"10", X"00", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"10" and div_by_zero;
write(L, string'(" 16/16 = "));
bv_divu(X"10", X"10", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"01" and not div_by_zero;
write(L, string'(" 1/16 = "));
bv_divu(X"01", X"10", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"00" and not div_by_zero;
write(L, string'(" 255/1 = "));
bv_divu(X"FF", X"01", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"FF" and not div_by_zero;
----------------------------------------------------------------
-- bv_divu: Unsigned division without divide by zero detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_divu without flag:"));
writeline(output, L);
write(L, string'(" 7/2 = "));
bv_divu(X"07", X"02", byte);
write(L, byte);
writeline(output, L);
assert byte = X"03";
write(L, string'(" 14/7 = "));
bv_divu(X"0E", X"07", byte);
write(L, byte);
writeline(output, L);
assert byte = X"02";
write(L, string'(" 16/1 = "));
bv_divu(X"10", X"01", byte);
write(L, byte);
writeline(output, L);
assert byte = X"10";
write(L, string'(" 16/0 = "));
bv_divu(X"10", X"00", byte);
write(L, byte);
writeline(output, L);
assert byte = X"10";
write(L, string'(" 16/16 = "));
bv_divu(X"10", X"10", byte);
write(L, byte);
writeline(output, L);
assert byte = X"01";
write(L, string'(" 1/16 = "));
bv_divu(X"01", X"10", byte);
write(L, byte);
writeline(output, L);
assert byte = X"00";
write(L, string'(" 255/1 = "));
bv_divu(X"FF", X"01", byte);
write(L, byte);
writeline(output, L);
assert byte = X"FF";
----------------------------------------------------------------
----------------------------------------------------------------
-- Logical operators
-- (Provided for VHDL-87, built in for VHDL-93)
----------------------------------------------------------------
----------------------------------------------------------------
----------------------------------------------------------------
-- bv_sll: Shift left logical (fill with '0' bits)
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_sll:"));
writeline(output, L);
write(L, string'(" 10100101 sll 4 = "));
byte := bv_sll(B"10100101", 4);
write(L, byte);
writeline(output, L);
assert byte = B"01010000";
----------------------------------------------------------------
-- bv_srl: Shift right logical (fill with '0' bits)
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_srl:"));
writeline(output, L);
write(L, string'(" 10100101 srl 4 = "));
byte := bv_srl(B"10100101", 4);
write(L, byte);
writeline(output, L);
assert byte = B"00001010";
----------------------------------------------------------------
-- bv_sra: Shift right arithmetic (fill with copy of sign bit)
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_sra:"));
writeline(output, L);
write(L, string'(" 01011010 sra 4 = "));
byte := bv_sra(B"01011010", 4);
write(L, byte);
writeline(output, L);
assert byte = B"00000101";
write(L, string'(" 10100101 sra 4 = "));
byte := bv_sra(B"10100101", 4);
write(L, byte);
writeline(output, L);
assert byte = B"11111010";
----------------------------------------------------------------
-- bv_rol: Rotate left
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_rol:"));
writeline(output, L);
write(L, string'(" 10100101 rol 3 = "));
byte := bv_rol(B"10100101", 3);
write(L, byte);
writeline(output, L);
assert byte = B"00101101";
----------------------------------------------------------------
-- bv_rol: Rotate right
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_ror:"));
writeline(output, L);
write(L, string'(" 10100101 ror 3 = "));
byte := bv_ror(B"10100101", 3);
write(L, byte);
writeline(output, L);
assert byte = B"10110100";
----------------------------------------------------------------
----------------------------------------------------------------
-- Arithmetic comparison operators.
----------------------------------------------------------------
----------------------------------------------------------------
----------------------------------------------------------------
-- bv_lt: Signed less than comparison
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_lt:"));
writeline(output, L);
write(L, string'(" 2 < 2 = "));
result := bv_lt(X"02", X"02");
write(L, result);
writeline(output, L);
assert NOT result;
write(L, string'(" 2 < 3 = "));
result := bv_lt(X"02", X"03");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" -2 < 2 = "));
result := bv_lt(X"FE", X"02");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" 2 < -3 = "));
result := bv_lt(X"02", X"FD");
write(L, result);
writeline(output, L);
assert NOT result;
----------------------------------------------------------------
-- bv_le: Signed less than or equal comparison
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_le:"));
writeline(output, L);
write(L, string'(" 2 <= 2 = "));
result := bv_le(X"02", X"02");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" 2 <= 3 = "));
result := bv_le(X"02", X"03");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" -2 <= 2 = "));
result := bv_le(X"FE", X"02");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" 2 <= -3 = "));
result := bv_le(X"02", X"FD");
write(L, result);
writeline(output, L);
assert NOT result;
----------------------------------------------------------------
-- bv_gt: Signed greater than comparison
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_gt:"));
writeline(output, L);
write(L, string'(" 2 > 2 = "));
result := bv_gt(X"02", X"02");
write(L, result);
writeline(output, L);
assert NOT result;
write(L, string'(" 3 > 2 = "));
result := bv_gt(X"03", X"02");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" 2 > -2 = "));
result := bv_gt(X"02", X"FE");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" -3 > 2 = "));
result := bv_gt(X"FD", X"02");
write(L, result);
writeline(output, L);
assert NOT result;
----------------------------------------------------------------
-- bv_ge: Signed greater than or equal comparison
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_ge:"));
writeline(output, L);
write(L, string'(" 2 >= 2 = "));
result := bv_ge(X"02", X"02");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" 3 >= 2 = "));
result := bv_ge(X"03", X"02");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" 2 >= -2 = "));
result := bv_ge(X"02", X"FE");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" -3 >= 2 = "));
result := bv_ge(X"FD", X"02");
write(L, result);
writeline(output, L);
assert NOT result;
----------------------------------------------------------------
----------------------------------------------------------------
-- Extension operators - convert a bit vector to a longer one
----------------------------------------------------------------
----------------------------------------------------------------
----------------------------------------------------------------
-- bv_sext: Sign extension
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_sext:"));
writeline(output, L);
write(L, string'(" sext(X""02"", 32) = "));
word := bv_sext(X"02", 32);
write(L, word);
writeline(output, L);
assert word = X"00000002";
write(L, string'(" sext(X""FE"", 32) = "));
word := bv_sext(X"FE", 32);
write(L, word);
writeline(output, L);
assert word = X"FFFFFFFE";
write(L, string'(" sext(X""02"", 8) = "));
byte := bv_sext(X"02", 8);
write(L, byte);
writeline(output, L);
assert byte = X"02";
write(L, string'(" sext(X""FE"", 8) = "));
byte := bv_sext(X"FE", 8);
write(L, byte);
writeline(output, L);
assert byte = X"FE";
write(L, string'(" sext(X""02"", 4) = "));
half_byte := bv_sext(X"02", 4);
write(L, half_byte);
writeline(output, L);
assert half_byte = X"2";
write(L, string'(" sext(X""FE"", 4) = "));
half_byte := bv_sext(X"FE", 4);
write(L, half_byte);
writeline(output, L);
assert half_byte = X"E";
----------------------------------------------------------------
-- bv_zext" Zero extension
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_zext:"));
writeline(output, L);
write(L, string'(" zext(X""02"", 32) = "));
word := bv_zext(X"02", 32);
write(L, word);
writeline(output, L);
assert word = X"00000002";
write(L, string'(" zext(X""FE"", 32) = "));
word := bv_zext(X"FE", 32);
write(L, word);
writeline(output, L);
assert word = X"000000FE";
write(L, string'(" zext(X""02"", 8) = "));
byte := bv_zext(X"02", 8);
write(L, byte);
writeline(output, L);
assert byte = X"02";
write(L, string'(" zext(X""FE"", 8) = "));
byte := bv_zext(X"FE", 8);
write(L, byte);
writeline(output, L);
assert byte = X"FE";
write(L, string'(" zext(X""02"", 4) = "));
half_byte := bv_zext(X"02", 4);
write(L, half_byte);
writeline(output, L);
assert half_byte = X"2";
write(L, string'(" zext(X""FE"", 4) = "));
half_byte := bv_zext(X"FE", 4);
write(L, half_byte);
writeline(output, L);
assert half_byte = X"E";
wait;
end process;
end bench;
| apache-2.0 | 6969af18f3e64b0642ffadbfdf60b688 | 0.458058 | 3.683163 | false | false | false | false |
s-kostyuk/course_project_csch | pilot_processor_signed_mul/control_unit.vhd | 1 | 1,662 | library IEEE;
use IEEE.std_logic_1164.all;
entity control_unit is
port ( Clk: in STD_LOGIC; Reset: in STD_LOGIC;
X: in STD_LOGIC_vector(4 downto 1);
Y: out STD_LOGIC_vector(12 downto 1));
end control_unit;
architecture control_unit of control_unit is
-- Òèï, èñïîëüçóþùèé ñèìâîëüíîå êîäèðîâàíèå ñîñòîÿíèé àâòîìàòà
type State_type is (a1, a2, a3, a4, a5, a6);
signal State, NextState: State_type;
begin
-- NextState logic (combinatorial)
Sreg0_NextState: process (State, x)
begin
-- èíèöèàëèçàöèÿ çíà÷åíèé âûõîäîâ
y <= (others => '0');
case State is
when a1 =>
NextState <= a2;
y(1) <= '1';
y(2) <= '1';
y(3) <= '1';
y(4) <= '1';
when a2=>
NextState <= a3;
if x(1) = '1' then
y(5) <= '1';
end if;
when a3=>
NextState <= a4;
y(6) <= '1';
y(7) <= '1';
y(8) <= '1';
when a4=>
NextState <= a5;
if x(2) = '1' then
y(9) <= '1';
else
y(10) <= '1';
end if;
when a5=>
if x(3) = '0' then
NextState <= a2;
elsif x(4) = '1' then
NextState <= a6;
y(11) <= '1';
else
NextState <= a6;
end if;
when a6=>
NextState <= a1;
y(12) <= '1';
when others => NextState <= a1;
-- ïðèñâîåíèå çíà÷åíèé âûõîäàì äëÿ ñîñòîÿíèÿ ïî óìîë÷àíèþ
--Óñòàíîâêà àâòîìàòà â íà÷àëüíîå ñîñòîÿíèå
end case;
end process;
Sreg0_CurrentState: process (Clk, reset)
begin
if Reset='0' then
State <= a1; -- íà÷àëüíîå ñîñòîÿíèå
elsif rising_edge(clk) then
State <= NextState;
end if;
end process;
end control_unit; | mit | e2363e4c741824d9cf89d27527c50962 | 0.534898 | 2.422741 | false | false | false | false |
sergev/vak-opensource | hardware/vhd2vl/examples/genericmap.vhd | 1 | 2,133 | LIBRARY IEEE;
USE IEEE.std_logic_1164.all, IEEE.std_logic_arith.all, IEEE.std_logic_unsigned.all;
entity test is
generic(
rst_val : std_logic := '0';
thing_size: integer := 201;
bus_width : integer := 201 mod 32);
port(
clk, rstn : in std_logic;
en, start_dec : in std_logic;
addr : in std_logic_vector(2 downto 0);
din : in std_logic_vector(25 downto 0);
we : in std_logic;
pixel_in : in std_logic_vector(7 downto 0);
pix_req : in std_logic;
config, bip : in std_logic;
a, b : in std_logic_vector(7 downto 0);
c, load : in std_logic_vector(7 downto 0);
pack : in std_logic_vector(6 downto 0);
base : in std_logic_vector(2 downto 0);
qtd : in std_logic_vector(21 downto 0);
-- Outputs
dout : out std_logic_vector(25 downto 0);
pixel_out : out std_logic_vector(7 downto 0);
pixel_valid : out std_logic;
code : out std_logic_vector(9 downto 0);
complex : out std_logic_vector(23 downto 0);
eno : out std_logic
);
end test;
architecture rtl of test is
component dsp
generic(
rst_val : std_logic := '0';
thing_size: integer := 201;
bus_width : integer := 22);
port(
-- Inputs
clk, rstn : in std_logic;
-- Outputs
dout : out std_logic_vector(bus_width downto 0);
memaddr : out std_logic_vector(5 downto 0);
memdout : out std_logic_vector(13 downto 0)
);
end component;
signal param : std_logic_vector(7 downto 0);
signal selection : std_logic;
signal start, enf : std_logic; -- Start and enable signals
signal memdin : std_logic_vector(13 downto 0);
signal memaddr : std_logic_vector(5 downto 0);
signal memdout : std_logic_vector(13 downto 0);
signal colour : std_logic_vector(1 downto 0);
begin
dsp_inst0 : dsp
port map(
-- Inputs
clk => clk,
rstn => rstn,
-- Outputs
dout => dout,
memaddr => memaddr,
memdout => memdout
);
dsp_inst1 : dsp
generic map(
rst_val => '1',
bus_width => 16)
port map(
-- Inputs
clk => clk,
rstn => rstn,
-- Outputs
dout => dout,
memaddr => memaddr,
memdout => memdout
);
end rtl;
| apache-2.0 | 6d5de2d8fcd439058d00c04e3d568a1a | 0.618378 | 3.236722 | false | false | false | false |
FinnK/lems2hdl | work/N2_Izhikevich/ISIM_output/top_synth.vhdl | 1 | 10,692 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.fixed_float_types.ALL;
use std.textio.all;
use ieee.std_logic_textio.all; -- if you're saving this type of signal
use IEEE.numeric_std.all;
entity top_synth is
Port ( clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model: in STD_LOGIC; --SYNCHRONOUS RESET
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
step_once_complete : out STD_LOGIC; --signals to the core that a time step has finished
eventport_in_spike_aggregate : in STD_LOGIC_VECTOR(511 downto 0);
neuron_model_eventport_out_spike : out STD_LOGIC;
neuron_model_param_voltage_v0 : in sfixed (2 downto -22);
neuron_model_param_none_a : in sfixed (18 downto -13);
neuron_model_param_none_b : in sfixed (18 downto -13);
neuron_model_param_none_c : in sfixed (18 downto -13);
neuron_model_param_none_d : in sfixed (18 downto -13);
neuron_model_param_voltage_thresh : in sfixed (2 downto -22);
neuron_model_param_time_MSEC : in sfixed (6 downto -18);
neuron_model_param_voltage_MVOLT : in sfixed (2 downto -22);
neuron_model_param_time_inv_MSEC_inv : in sfixed (18 downto -6);
neuron_model_param_voltage_inv_MVOLT_inv : in sfixed (22 downto -2);
neuron_model_param_none_div_voltage_b_div_MVOLT : in sfixed (18 downto -13);
neuron_model_exposure_voltage_v : out sfixed (2 downto -22);
neuron_model_exposure_none_U : out sfixed (18 downto -13);
neuron_model_stateCURRENT_voltage_v : out sfixed (2 downto -22);
neuron_model_stateRESTORE_voltage_v : in sfixed (2 downto -22);
neuron_model_stateCURRENT_none_U : out sfixed (18 downto -13);
neuron_model_stateRESTORE_none_U : in sfixed (18 downto -13);
neuron_model_param_time_i1_delay : in sfixed (6 downto -18);
neuron_model_param_time_i1_duration : in sfixed (6 downto -18);
neuron_model_param_none_i1_amplitude : in sfixed (18 downto -13);
neuron_model_exposure_none_i1_I : out sfixed (18 downto -13);
neuron_model_stateCURRENT_none_i1_I : out sfixed (18 downto -13);
neuron_model_stateRESTORE_none_i1_I : in sfixed (18 downto -13);
sysparam_time_timestep : sfixed (-6 downto -22);
sysparam_time_simtime : sfixed (6 downto -22)
);
end top_synth;
architecture top of top_synth is
signal step_once_complete_int : STD_LOGIC;
signal seven_steps_done : STD_LOGIC;
signal step_once_go_int : STD_LOGIC := '0';
signal seven_steps_done_shot_done : STD_LOGIC;
signal seven_steps_done_shot : STD_LOGIC;
signal seven_steps_done_shot2 : STD_LOGIC;
signal COUNT : unsigned(2 downto 0) := "110";
signal seven_steps_done_next : STD_LOGIC;
signal COUNT_next : unsigned(2 downto 0) := "110";
signal step_once_go_int_next : STD_LOGIC := '0';
signal neuron_model_eventport_out_spike_int : STD_LOGIC;
signal neuron_model_eventport_out_spike_int2 : STD_LOGIC;
signal neuron_model_eventport_out_spike_int3 : STD_LOGIC;
component neuron_model
Port ( clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model: in STD_LOGIC; --SYNCHRONOUS RESET
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
step_once_complete : out STD_LOGIC; --signals to the core that a time step has finished
eventport_in_spike_aggregate : in STD_LOGIC_VECTOR(511 downto 0);
eventport_out_spike : out STD_LOGIC;
param_voltage_v0 : in sfixed (2 downto -22);
param_none_a : in sfixed (18 downto -13);
param_none_b : in sfixed (18 downto -13);
param_none_c : in sfixed (18 downto -13);
param_none_d : in sfixed (18 downto -13);
param_voltage_thresh : in sfixed (2 downto -22);
param_time_MSEC : in sfixed (6 downto -18);
param_voltage_MVOLT : in sfixed (2 downto -22);
param_time_inv_MSEC_inv : in sfixed (18 downto -6);
param_voltage_inv_MVOLT_inv : in sfixed (22 downto -2);
param_none_div_voltage_b_div_MVOLT : in sfixed (18 downto -13);
exposure_voltage_v : out sfixed (2 downto -22);
exposure_none_U : out sfixed (18 downto -13);
statevariable_voltage_v_out : out sfixed (2 downto -22);
statevariable_voltage_v_in : in sfixed (2 downto -22);
statevariable_none_U_out : out sfixed (18 downto -13);
statevariable_none_U_in : in sfixed (18 downto -13);
param_time_i1_delay : in sfixed (6 downto -18);
param_time_i1_duration : in sfixed (6 downto -18);
param_none_i1_amplitude : in sfixed (18 downto -13);
exposure_none_i1_I : out sfixed (18 downto -13);
statevariable_none_i1_I_out : out sfixed (18 downto -13);
statevariable_none_i1_I_in : in sfixed (18 downto -13);
sysparam_time_timestep : sfixed (-6 downto -22);
sysparam_time_simtime : sfixed (6 downto -22)
);
end component;
signal neuron_model_eventport_out_spike_out : STD_LOGIC := '0';
signal neuron_model_statevariable_voltage_v_out_int : sfixed (2 downto -22);signal neuron_model_statevariable_voltage_v_in_int : sfixed (2 downto -22);signal neuron_model_statevariable_none_U_out_int : sfixed (18 downto -13);signal neuron_model_statevariable_none_U_in_int : sfixed (18 downto -13);signal neuron_model_statevariable_none_i1_I_out_int : sfixed (18 downto -13);signal neuron_model_statevariable_none_i1_I_in_int : sfixed (18 downto -13);
begin
neuron_model_uut : neuron_model
port map ( clk => clk,
init_model=> init_model,
step_once_go => step_once_go_int,
step_once_complete => step_once_complete_int,
eventport_in_spike_aggregate => eventport_in_spike_aggregate,
eventport_out_spike => neuron_model_eventport_out_spike_int ,
param_voltage_v0 => neuron_model_param_voltage_v0 ,
param_none_a => neuron_model_param_none_a ,
param_none_b => neuron_model_param_none_b ,
param_none_c => neuron_model_param_none_c ,
param_none_d => neuron_model_param_none_d ,
param_voltage_thresh => neuron_model_param_voltage_thresh ,
param_time_MSEC => neuron_model_param_time_MSEC ,
param_voltage_MVOLT => neuron_model_param_voltage_MVOLT ,
param_time_inv_MSEC_inv => neuron_model_param_time_inv_MSEC_inv ,
param_voltage_inv_MVOLT_inv => neuron_model_param_voltage_inv_MVOLT_inv ,
param_none_div_voltage_b_div_MVOLT => neuron_model_param_none_div_voltage_b_div_MVOLT ,
statevariable_voltage_v_out => neuron_model_statevariable_voltage_v_out_int,
statevariable_voltage_v_in => neuron_model_statevariable_voltage_v_in_int,
statevariable_none_U_out => neuron_model_statevariable_none_U_out_int,
statevariable_none_U_in => neuron_model_statevariable_none_U_in_int,
param_time_i1_delay => neuron_model_param_time_i1_delay ,
param_time_i1_duration => neuron_model_param_time_i1_duration ,
param_none_i1_amplitude => neuron_model_param_none_i1_amplitude ,
statevariable_none_i1_I_out => neuron_model_statevariable_none_i1_I_out_int,
statevariable_none_i1_I_in => neuron_model_statevariable_none_i1_I_in_int,
sysparam_time_timestep => sysparam_time_timestep,
sysparam_time_simtime => sysparam_time_simtime
);
count_proc_comb:process(init_model,step_once_complete_int,COUNT,step_once_go)
begin
seven_steps_done_next <= '0';
COUNT_next <= COUNT;
step_once_go_int_next <= '0';
if (init_model='1') then
seven_steps_done_next <= '0';
COUNT_next <= "110";
step_once_go_int_next <= '0';
else
if step_once_complete_int = '1' then
if (COUNT = "110") then
seven_steps_done_next <= '1';
COUNT_next <= "110";
step_once_go_int_next <= '0';
else
seven_steps_done_next <= '0';
COUNT_next <= COUNT + 1;
step_once_go_int_next <= '1';
end if;
elsif step_once_go = '1' then
seven_steps_done_next <= '0';
COUNT_next <= "000";
step_once_go_int_next <= '1';
else
seven_steps_done_next <= '0';
COUNT_next <= COUNT;
step_once_go_int_next <= '0';
end if;
end if;
end process count_proc_comb;
count_proc_syn:process(clk)
begin
if rising_edge(clk) then
if init_model = '1' then
COUNT <= "110";
seven_steps_done <= '1';
step_once_go_int <= '0';
else
COUNT <= COUNT_next;
seven_steps_done <= seven_steps_done_next;
step_once_go_int <= step_once_go_int_next;
end if; end if;
end process count_proc_syn;
shot_process:process(clk)
begin
if rising_edge(clk) then
if (init_model='1') then
seven_steps_done_shot <= '0';
seven_steps_done_shot_done <= '1';
else
if seven_steps_done = '1' and seven_steps_done_shot_done = '0' then
seven_steps_done_shot <= '1';
seven_steps_done_shot_done <= '1';
elsif seven_steps_done_shot = '1' then
seven_steps_done_shot <= '0';
elsif seven_steps_done = '0' then
seven_steps_done_shot <= '0';
seven_steps_done_shot_done <= '0';
end if;
end if;
end if;
end process shot_process;
store_state: process (clk)
begin
if rising_edge(clk) then
neuron_model_eventport_out_spike_int2 <= neuron_model_eventport_out_spike_int; neuron_model_eventport_out_spike_int3 <= neuron_model_eventport_out_spike_int2; seven_steps_done_shot2 <= seven_steps_done_shot; if (init_model='1') then
neuron_model_statevariable_voltage_v_in_int <= neuron_model_stateRESTORE_voltage_v;
neuron_model_statevariable_none_U_in_int <= neuron_model_stateRESTORE_none_U;
neuron_model_statevariable_none_i1_I_in_int <= neuron_model_stateRESTORE_none_i1_I;
neuron_model_eventport_out_spike_out <= '0';
elsif (seven_steps_done_shot='1') then
neuron_model_eventport_out_spike_out <= neuron_model_eventport_out_spike_int3 ;
neuron_model_statevariable_voltage_v_in_int <= neuron_model_statevariable_voltage_v_out_int;
neuron_model_statevariable_none_U_in_int <= neuron_model_statevariable_none_U_out_int;
neuron_model_statevariable_none_i1_I_in_int <= neuron_model_statevariable_none_i1_I_out_int;
else
neuron_model_eventport_out_spike_out <= '0';
end if;
end if;
end process store_state;
neuron_model_stateCURRENT_voltage_v <= neuron_model_statevariable_voltage_v_in_int;
neuron_model_stateCURRENT_none_U <= neuron_model_statevariable_none_U_in_int;
neuron_model_stateCURRENT_none_i1_I <= neuron_model_statevariable_none_i1_I_in_int;
neuron_model_eventport_out_spike <= neuron_model_eventport_out_spike_out;
step_once_complete <= seven_steps_done_shot2;
end top; | lgpl-3.0 | 2cd520e79281ba473b866e3a9c075bdc | 0.683689 | 2.989097 | false | false | false | false |
ShepardSiegel/ocpi | libsrc/hdl/vhd/ocpi_ocp.vhd | 1 | 771 | -- this sub-package is the OpenCPI definitions from the OCP spec
-- the OCP signal names are left in their "native" case to make it clear
-- that they are for those specific signals
library ieee; use IEEE.std_logic_1164.all; use ieee.numeric_std.all;
package ocp is
-- Address Space Operations
subtype MCmd_t IS std_logic_vector(2 DOWNTO 0);
constant MCmd_IDLE : MCmd_t := "000";
constant MCmd_WRITE : MCmd_t := "001";
constant MCmd_READ : MCmd_t := "010";
-- Address Space Operation Responses
subtype SResp_t IS std_logic_vector(1 DOWNTO 0);
constant SResp_NULL : SResp_t := "00";
constant SResp_DVA : SResp_t := "01";
constant SResp_FAIL : SResp_t := "10";
constant SResp_ERR : SResp_t := "11";
end package ocp;
| lgpl-3.0 | d7a2a6d341ebe6a7595433af6f16685c | 0.66537 | 3.19917 | false | false | false | false |
matbur95/ucisw-pro | pro4/master.vhd | 1 | 3,773 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:03:57 04/05/2017
-- Design Name:
-- Module Name: master - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MASTER is
Port ( ADC_DOA : in STD_LOGIC_VECTOR (13 downto 0);
ADC_DOB : in STD_LOGIC_VECTOR (13 downto 0);
ADC_BUSY : in STD_LOGIC;
CLK : in STD_LOGIC;
POS : in STD_LOGIC_VECTOR(19 downto 0);
DATA : in STD_LOGIC;
Line : out STD_LOGIC_VECTOR (63 downto 0);
Blank : out STD_LOGIC_VECTOR (15 downto 0);
ADDR : out STD_LOGIC_VECTOR (13 downto 0);
VGA_COLOR : out STD_LOGIC_VECTOR(2 downto 0);
AMP_WE : out STD_LOGIC;
ADC_Start : out STD_LOGIC;
AMP_DI : out STD_LOGIC_VECTOR (7 downto 0));
end MASTER;
architecture Behavioral of MASTER is
-- constant SIDE : integer := 50;
constant SIDE : signed ( 10 downto 0 ) := to_signed( 50, 11);
constant VMAX : signed ( 10 downto 0 ) := to_signed( 600, 11);
constant HMAX : signed ( 10 downto 0 ) := to_signed( 800, 11);
-- constant HMAX : integer := 800;
-- signal BOX_HPOS : integer range -100 to 1000 := 400;
signal BOX_HPOS : signed( 10 downto 0) := to_signed( 400, 11 );
signal BOX_VPOS : signed( 10 downto 0) := to_signed( 300, 11 );
-- signal BOX_VPOS : integer range -100 to 1000 := 300;
signal HPOS : signed( 10 downto 0) := to_signed( 0, 11 );
signal VPOS : signed( 10 downto 0) := to_signed( 0, 11 );
-- signal HPOS : integer range 0 to 800 := 0;
-- signal VPOS : integer range 0 to 600 := 0;
begin
HPOS <= signed('0' & POS(19 downto 10));
VPOS <= signed('0' & POS(9 downto 0));
AMP_WE <= '1' when HPOS = 0 and VPOS = 0 else '0';
AMP_DI <= X"11";
ADC_Start <= '1' when HPOS = HMAX and VPOS = VMAX else '0';
Blank <= X"0F0F";
Line <= "00" & ADC_DOA & X"0000" & "00" & ADC_DOB & X"0000";
BOX: process (CLK, HPOS, VPOS)
begin
if rising_edge(CLK) then
if HPOS = 0 and VPOS = 0 then
BOX_HPOS <= BOX_HPOS - signed(ADC_DOA(13 downto 11));
BOX_VPOS <= BOX_VPOS + signed(ADC_DOB(13 downto 11));
end if;
if BOX_HPOS < 0 then
BOX_HPOS <= to_signed(0, 11);
elsif BOX_HPOS > HMAX - SIDE then
BOX_HPOS <= HMAX - SIDE;
end if;
if BOX_VPOS < 0 then
BOX_VPOS <= to_signed(0, 11);
elsif BOX_VPOS > VMAX - SIDE then
BOX_VPOS <= VMAX - SIDE;
end if;
-- if HPOS > BOX_HPOS and HPOS < BOX_HPOS + SIDE and VPOS > BOX_VPOS and VPOS < BOX_VPOS + SIDE then
-- VGA_COLOR <= B"101";
-- else
-- VGA_COLOR <= B"001";
-- end if;
end if;
end process BOX;
-- BOX_HPOS <= BOX_HPOS + to_integer(signed(ADC_DOA(13 downto 12)));
ADDR <= STD_LOGIC_VECTOR(VPOS(9 downto 3)) & STD_LOGIC_VECTOR(HPOS(9 downto 3));
VGA_COLOR <= B"101" when HPOS > BOX_HPOS and HPOS < BOX_HPOS + SIDE and VPOS > BOX_VPOS and VPOS < BOX_VPOS + SIDE else DATA & DATA & not DATA;
end Behavioral;
| mit | 683f7ebe3d2e433b9a52e35152f58812 | 0.551285 | 3.43938 | false | false | false | false |
Wynjones1/VHDL-Build | example/text_display/top.vhd | 1 | 3,028 | library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
use work.display_comp.all;
use work.text_display_comp.all;
entity top is
port( clk : in std_logic;
reset : in std_logic;
red : out std_logic_vector(2 downto 0);
green : out std_logic_vector(2 downto 0);
blue : out std_logic_vector(1 downto 0);
hs : out std_logic;
vs : out std_logic);
end top;
architecture rtl of top is
-- components
component text_display is
port( clk : in std_logic;
reset : in std_logic;
input : in text_display_in_t;
output : out text_display_out_t);
end component;
component clk_gen is
generic( CLOCK_SPEED : integer := 50_000_000;
REQUIRED_HZ : integer := 1);
port( clk : in std_logic;
reset : in std_logic;
clk_out : out std_logic);
end component;
-- function
function next_char(c : character_t) return character_t is
begin
if c = PRINTABLE_END - 1 then
return PRINTABLE_START;
else
return c + 1;
end if;
end function;
function next_pix(a : integer; m : integer) return integer is
begin
if a = m - 1 then
return 0;
else
return a + 1;
end if;
end function;
signal text_display_in_s : text_display_in_t;
signal text_display_out_s : text_display_out_t;
signal x : natural range 0 to TEXT_WIDTH - 1;
signal y : natural range 0 to TEXT_HEIGHT - 1;
signal x_next : natural range 0 to TEXT_WIDTH - 1;
signal y_next : natural range 0 to TEXT_HEIGHT - 1;
signal c : character_t;
signal c_next : character_t;
signal clk_1hz_s : std_logic;
begin
gen_1hz : clk_gen
generic map (REQUIRED_HZ => (640 * 480) / 64)
port map (clk, reset, clk_1hz_s);
text_display_0: text_display
port map (clk, reset, text_display_in_s, text_display_out_s);
comb: process(x, y, c, reset, text_display_out_s)
begin
x_next <= next_pix(x, TEXT_WIDTH);
if x = TEXT_WIDTH - 1 then
y_next <= next_pix(y, TEXT_HEIGHT);
else
y_next <= y;
end if;
c_next <= next_char(c);
text_display_in_s <= (x, y, not reset, c);
hs <= text_display_out_s.hs;
vs <= text_display_out_s.vs;
red <= text_display_out_s.colour(7 downto 5);
green <= text_display_out_s.colour(4 downto 2);
blue <= text_display_out_s.colour(1 downto 0);
end process;
seq: process(clk_1hz_s, reset)
begin
if reset = '1' then
x <= 0;
y <= 0;
c <= 64;
elsif rising_edge(clk_1hz_s) then
x <= x_next;
y <= y_next;
c <= c_next;
end if;
end process;
end rtl;
| mit | 9c619493912c0c295a3eea93272577d0 | 0.517503 | 3.50463 | false | false | false | false |
dangpzanco/sistemas-digitais | muxSIGN.vhd | 1 | 446 | library IEEE;
use IEEE.Std_Logic_1164.all;
entity muxsign is
port (w, x, y: in std_logic;
selection: in std_logic_vector(4 downto 0);
m: out std_logic
);
end muxsign;
architecture mux_estr of muxsign is
begin
m <= w when selection = "10011" else
x when selection = "10100" else
y when selection = "10101" else
'0';
end mux_estr;
--- w <= SD0
--- x <= SD1
--- y <= SD2
--- selection <= selection
--- sign <= m | mit | 6e52cb391beb1ca4f22f9db25d8d90f4 | 0.607623 | 2.915033 | false | false | false | false |
julioamerico/OpenCRC | src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@m@s@s_@a@p@b_@f060/_primary.vhd | 3 | 9,447 | library verilog;
use verilog.vl_types.all;
entity MSS_APB_F060 is
generic(
ACT_CONFIG : integer := 0;
ACT_FCLK : integer := 0;
ACT_DIE : string := "";
ACT_PKG : string := "";
VECTFILE : string := "test.vec"
);
port(
MSSPADDR : out vl_logic_vector(19 downto 0);
MSSPWDATA : out vl_logic_vector(31 downto 0);
MSSPWRITE : out vl_logic;
MSSPSEL : out vl_logic;
MSSPENABLE : out vl_logic;
MSSPRDATA : in vl_logic_vector(31 downto 0);
MSSPREADY : in vl_logic;
MSSPSLVERR : in vl_logic;
FABPADDR : in vl_logic_vector(31 downto 0);
FABPWDATA : in vl_logic_vector(31 downto 0);
FABPWRITE : in vl_logic;
FABPSEL : in vl_logic;
FABPENABLE : in vl_logic;
FABPRDATA : out vl_logic_vector(31 downto 0);
FABPREADY : out vl_logic;
FABPSLVERR : out vl_logic;
SYNCCLKFDBK : in vl_logic;
CALIBOUT : out vl_logic;
CALIBIN : in vl_logic;
FABINT : in vl_logic;
MSSINT : out vl_logic_vector(7 downto 0);
WDINT : out vl_logic;
F2MRESETn : in vl_logic;
DMAREADY : in vl_logic_vector(1 downto 0);
RXEV : in vl_logic;
VRON : in vl_logic;
M2FRESETn : out vl_logic;
DEEPSLEEP : out vl_logic;
SLEEP : out vl_logic;
TXEV : out vl_logic;
UART0CTSn : in vl_logic;
UART0DSRn : in vl_logic;
UART0RIn : in vl_logic;
UART0DCDn : in vl_logic;
UART0RTSn : out vl_logic;
UART0DTRn : out vl_logic;
UART1CTSn : in vl_logic;
UART1DSRn : in vl_logic;
UART1RIn : in vl_logic;
UART1DCDn : in vl_logic;
UART1RTSn : out vl_logic;
UART1DTRn : out vl_logic;
I2C0SMBUSNI : in vl_logic;
I2C0SMBALERTNI : in vl_logic;
I2C0BCLK : in vl_logic;
I2C0SMBUSNO : out vl_logic;
I2C0SMBALERTNO : out vl_logic;
I2C1SMBUSNI : in vl_logic;
I2C1SMBALERTNI : in vl_logic;
I2C1BCLK : in vl_logic;
I2C1SMBUSNO : out vl_logic;
I2C1SMBALERTNO : out vl_logic;
MACM2FTXD : out vl_logic_vector(1 downto 0);
MACF2MRXD : in vl_logic_vector(1 downto 0);
MACM2FTXEN : out vl_logic;
MACF2MCRSDV : in vl_logic;
MACF2MRXER : in vl_logic;
MACF2MMDI : in vl_logic;
MACM2FMDO : out vl_logic;
MACM2FMDEN : out vl_logic;
MACM2FMDC : out vl_logic;
FABSDD0D : in vl_logic;
FABSDD1D : in vl_logic;
FABSDD2D : in vl_logic;
FABSDD0CLK : in vl_logic;
FABSDD1CLK : in vl_logic;
FABSDD2CLK : in vl_logic;
FABACETRIG : in vl_logic;
ACEFLAGS : out vl_logic_vector(31 downto 0);
CMP0 : out vl_logic;
CMP1 : out vl_logic;
CMP2 : out vl_logic;
CMP3 : out vl_logic;
CMP4 : out vl_logic;
CMP5 : out vl_logic;
CMP6 : out vl_logic;
CMP7 : out vl_logic;
CMP8 : out vl_logic;
CMP9 : out vl_logic;
CMP10 : out vl_logic;
CMP11 : out vl_logic;
LVTTL0EN : in vl_logic;
LVTTL1EN : in vl_logic;
LVTTL2EN : in vl_logic;
LVTTL3EN : in vl_logic;
LVTTL4EN : in vl_logic;
LVTTL5EN : in vl_logic;
LVTTL6EN : in vl_logic;
LVTTL7EN : in vl_logic;
LVTTL8EN : in vl_logic;
LVTTL9EN : in vl_logic;
LVTTL10EN : in vl_logic;
LVTTL11EN : in vl_logic;
LVTTL0 : out vl_logic;
LVTTL1 : out vl_logic;
LVTTL2 : out vl_logic;
LVTTL3 : out vl_logic;
LVTTL4 : out vl_logic;
LVTTL5 : out vl_logic;
LVTTL6 : out vl_logic;
LVTTL7 : out vl_logic;
LVTTL8 : out vl_logic;
LVTTL9 : out vl_logic;
LVTTL10 : out vl_logic;
LVTTL11 : out vl_logic;
PUFABn : out vl_logic;
VCC15GOOD : out vl_logic;
VCC33GOOD : out vl_logic;
FCLK : in vl_logic;
MACCLKCCC : in vl_logic;
RCOSC : in vl_logic;
MACCLK : in vl_logic;
PLLLOCK : in vl_logic;
MSSRESETn : in vl_logic;
GPI : in vl_logic_vector(31 downto 0);
GPO : out vl_logic_vector(31 downto 0);
GPOE : out vl_logic_vector(31 downto 0);
SPI0DO : out vl_logic;
SPI0DOE : out vl_logic;
SPI0DI : in vl_logic;
SPI0CLKI : in vl_logic;
SPI0CLKO : out vl_logic;
SPI0MODE : out vl_logic;
SPI0SSI : in vl_logic;
SPI0SSO : out vl_logic_vector(7 downto 0);
UART0TXD : out vl_logic;
UART0RXD : in vl_logic;
I2C0SDAI : in vl_logic;
I2C0SDAO : out vl_logic;
I2C0SCLI : in vl_logic;
I2C0SCLO : out vl_logic;
SPI1DO : out vl_logic;
SPI1DOE : out vl_logic;
SPI1DI : in vl_logic;
SPI1CLKI : in vl_logic;
SPI1CLKO : out vl_logic;
SPI1MODE : out vl_logic;
SPI1SSI : in vl_logic;
SPI1SSO : out vl_logic_vector(7 downto 0);
UART1TXD : out vl_logic;
UART1RXD : in vl_logic;
I2C1SDAI : in vl_logic;
I2C1SDAO : out vl_logic;
I2C1SCLI : in vl_logic;
I2C1SCLO : out vl_logic;
MACTXD : out vl_logic_vector(1 downto 0);
MACRXD : in vl_logic_vector(1 downto 0);
MACTXEN : out vl_logic;
MACCRSDV : in vl_logic;
MACRXER : in vl_logic;
MACMDI : in vl_logic;
MACMDO : out vl_logic;
MACMDEN : out vl_logic;
MACMDC : out vl_logic;
EMCCLK : out vl_logic;
EMCCLKRTN : in vl_logic;
EMCRDB : in vl_logic_vector(15 downto 0);
EMCAB : out vl_logic_vector(25 downto 0);
EMCWDB : out vl_logic_vector(15 downto 0);
EMCRWn : out vl_logic;
EMCCS0n : out vl_logic;
EMCCS1n : out vl_logic;
EMCOEN0n : out vl_logic;
EMCOEN1n : out vl_logic;
EMCBYTEN : out vl_logic_vector(1 downto 0);
EMCDBOE : out vl_logic;
ADC0 : in vl_logic;
ADC1 : in vl_logic;
ADC2 : in vl_logic;
ADC3 : in vl_logic;
ADC4 : in vl_logic;
ADC5 : in vl_logic;
ADC6 : in vl_logic;
ADC7 : in vl_logic;
ADC8 : in vl_logic;
ADC9 : in vl_logic;
ADC10 : in vl_logic;
ADC11 : in vl_logic;
ADC12 : in vl_logic;
ADC13 : in vl_logic;
ADC14 : in vl_logic;
ADC15 : in vl_logic;
ADC16 : in vl_logic;
ADC17 : in vl_logic;
ADC18 : in vl_logic;
ADC19 : in vl_logic;
ADC20 : in vl_logic;
ADC21 : in vl_logic;
ADC22 : in vl_logic;
ADC23 : in vl_logic;
ADC24 : in vl_logic;
ADC25 : in vl_logic;
SDD0 : out vl_logic;
ABPS0 : in vl_logic;
ABPS1 : in vl_logic;
TM0 : in vl_logic;
CM0 : in vl_logic;
GNDTM0 : in vl_logic;
VAREF0 : in vl_logic;
VAREFOUT : out vl_logic;
GNDVAREF : in vl_logic;
PUn : in vl_logic
);
end MSS_APB_F060;
| gpl-3.0 | 006cabf1db131ac9214535f801bb26e1 | 0.404255 | 3.663048 | false | false | false | false |
matbur95/ucisw-pro | src/vga_init.vhd | 1 | 4,174 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:38:12 03/08/2017
-- Design Name:
-- Module Name: vga_init - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity vga_init is
Port ( CLK : in STD_LOGIC;
ADC_DOA : in STD_LOGIC_VECTOR(13 downto 0);
ADC_DOB : in STD_LOGIC_VECTOR(13 downto 0);
ADC_Busy : in STD_LOGIC;
VGA_R : out STD_LOGIC;
VGA_G : out STD_LOGIC;
VGA_B : out STD_LOGIC;
VGA_HS : out STD_LOGIC;
VGA_VS : out STD_LOGIC;
AMP_WE : out STD_LOGIC;
AMP_DI : out STD_LOGIC_VECTOR(7 downto 0);
ADC_Start : out STD_LOGIC;
Line : out STD_LOGIC_VECTOR(63 downto 0);
Blank : out STD_LOGIC_VECTOR(15 downto 0));
end vga_init;
architecture Behavioral of vga_init is
-- x = HPOS, y = VPOS
constant HPOS_MAX : integer := 1039;
constant VPOS_MAX : integer := 665;
-- constant HT_S : integer := 1040;
constant HT_DISP : integer := 800;
constant HT_PW : integer := 120;
constant HT_FP : integer := 64;
constant HT_BP : integer := 56;
-- constant VT_S : integer := 666;
constant VT_DISP : integer := 600;
constant VT_PW : integer := 6;
constant VT_FP : integer := 37;
constant VT_BP : integer := 23;
constant NUM0 : integer := 0;
constant NUM3 : integer := 3;
constant NUM97 : integer := 97;
signal HPOS : integer range 0 to HPOS_MAX := 0;
signal VPOS : integer range 0 to VPOS_MAX := 0;
constant BLUE : STD_LOGIC_VECTOR(0 to 2) := "001";
constant YELLOW : STD_LOGIC_VECTOR(0 to 2) := "110";
constant SIDE : integer := 50;
signal BOX_HPOS : integer range -100 to HT_DISP := 400;
signal BOX_VPOS : integer range -100 to VT_DISP := 300;
begin
HPOS_CNT: process (CLK)
begin
if rising_edge(CLK) then
if HPOS = HPOS_MAX then
HPOS <= 0;
else
HPOS <= HPOS + 1;
end if;
end if;
end process HPOS_CNT;
VPOS_CNT: process (CLK)
begin
if rising_edge(CLK) and HPOS = HPOS_MAX then
if VPOS = VPOS_MAX then
VPOS <= 0;
else
VPOS <= VPOS + 1;
end if;
end if;
end process VPOS_CNT;
VGA_HS <= '1' when HPOS >= HT_DISP + HT_FP and HPOS < HPOS_MAX - HT_BP else '0';
VGA_VS <= '1' when VPOS >= VT_DISP + VT_FP and VPOS < VPOS_MAX - VT_BP else '0';
VGA_R <= '1' when HPOS < HT_DISP and VPOS < VT_DISP else '0';
VGA_G <= '1' when HPOS > BOX_HPOS and HPOS < BOX_HPOS + SIDE and VPOS > 300 and VPOS < 300 + SIDE else '0';
AMP_WE <= '1' when HPOS = 0 and VPOS = 0 else '0';
AMP_DI <= X"11";
ADC_Start <= '1' when HPOS = HT_DISP and VPOS = VT_DISP else '0';
Blank <= X"0F0F";
Line <= "00" & ADC_DOA & X"0000" & "00" & ADC_DOB & X"0000";
BOX: process (HPOS, VPOS)
begin
if HPOS = 0 and VPOS = 0 then
BOX_HPOS <= BOX_HPOS + to_integer(signed(ADC_DOA(13 downto 11)));
BOX_VPOS <= BOX_VPOS + to_integer(signed(ADC_DOB(13 downto 11)));
end if;
if BOX_HPOS < 0 then
BOX_HPOS <= 0;
elsif BOX_HPOS > HT_DISP - SIDE then
BOX_HPOS <= HT_DISP - SIDE;
end if;
if BOX_VPOS < 0 then
BOX_VPOS <= 0;
elsif BOX_VPOS > VT_DISP - SIDE then
BOX_VPOS <= VT_DISP - SIDE;
end if;
end process BOX;
-- BOX_HPOS <= BOX_HPOS + to_integer(signed(ADC_DOA(13 downto 12)));
end Behavioral;
| mit | 18c334e85d9590676fff9729389b8c06 | 0.547197 | 3.466777 | false | false | false | false |
qynvi/rtl-hamweight | hamweight.vhd | 1 | 782 | -- William Fan
-- 01/24/2011
-- Hamming Weight RTL
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity hamweight is
generic (N: positive := 7);
port (x: in bit_vector(N downto 0);
y: out bit_vector(6 downto 0));
end entity;
architecture hw of hamweight is
type matrix is array (0 to N+1) of integer range 0 to N+1;
signal count: matrix;
begin
count(0) <= 0;
gen: for i in 0 to N generate
count(i+1) <= count(i) + 1 WHEN x(i)='1' ELSE count(i);
end generate;
WITH count(N) SELECT
y <= "0000001" when 0,
"1001111" when 1,
"0010010" when 2,
"0000110" when 3,
"1001100" when 4,
"0100100" when 5,
"0100000" when 6,
"0001111" when 7,
"0000000" when 8,
"0110000" when others;
end architecture;
| mit | 37a132c0f000db1a7c8dd7971dd45922 | 0.629156 | 2.91791 | false | false | false | false |
s-kostyuk/course_project_csch | pilot_processor_combined/adder_top.vhd | 3 | 773 | library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder is
generic(
N: integer := 4
);
port(A, B: in std_logic_vector(N-1 downto 0);
Cin: in std_logic;
S: out std_logic_vector(N-1 downto 0);
Cout: out std_logic;
overflow: out std_logic);
end entity;
architecture adder_struct of adder is
component full_adder is
port(
A, B, Cin: in std_logic;
S, Cout: out std_logic
);
end component;
signal C: std_logic_vector(0 to N);
begin
C(0) <= Cin;
Cout <= C(N);
overflow <= C(N-1) xor C(N);
gen_adders:
for I in 0 to N-1 generate
gen_fa : full_adder port map(
A => A(I), B => B(I), Cin => C(I),
S => S(I), Cout => C(I+1)
);
end generate;
end architecture; | mit | 693da25d0bea681a2c9ac65da02ba7a0 | 0.587322 | 2.585284 | false | false | false | false |
Rookfighter/fft-spartan6 | fft/fft16.vhd | 1 | 24,675 | -- fft16.vhd
--
-- Created on: 15 Jul 2017
-- Author: Fabian Meyer
--
-- Integration component for 16-point FFT. Implements pipelining of data and timing between components.
-- This architecture is based on the paper of George Slade:
-- https://www.researchgate.net/publication/235995761_The_Fast_Fourier_Transform_in_Hardware_A_Tutorial_Based_on_an_FPGA_Implementation
library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.fft_helpers.all;
entity fft16 is
generic(RSTDEF: std_logic := '0');
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
swrst: in std_logic; -- software reset, RSTDEF active
en: in std_logic; -- enable, high active
start: in std_logic; -- start FFT, high active
set: in std_logic; -- load FFT with values, high active
get: in std_logic; -- read FFT results, high active
din: in complex; -- datain for loading FFT
done: out std_logic; -- FFT is done, active high
dout: out complex); -- data out for reading results
end fft16;
architecture behavioral of fft16 is
-- import addr_gen component
component addr_gen
generic(RSTDEF: std_logic := '0';
FFTEXP: natural := 4);
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
swrst: in std_logic; -- software reset, RSTDEF active
en: in std_logic; -- enable, high active
lvl: in std_logic_vector(FFTEXP-2 downto 0); -- iteration level of butterflies
bfno: in std_logic_vector(FFTEXP-2 downto 0); -- butterfly number in current level
addra1: out std_logic_vector(FFTEXP-1 downto 0); -- address1 for membank A
addra2: out std_logic_vector(FFTEXP-1 downto 0); -- address2 for membank A
en_wrta: out std_logic; -- write enable for membank A, high active
addrb1: out std_logic_vector(FFTEXP-1 downto 0); -- address1 for membank B
addrb2: out std_logic_vector(FFTEXP-1 downto 0); -- address2 for membank B
en_wrtb: out std_logic; -- write enable for membank B, high active
addrtf: out std_logic_vector(FFTEXP-2 downto 0)); -- twiddle factor address
end component;
-- import membank component
component membank
generic(RSTDEF: std_logic := '0';
FFTEXP: natural := 4);
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
swrst: in std_logic; -- software reset, RSTDEF active
en: in std_logic; -- enable, high active
addr1: in std_logic_vector(FFTEXP-1 downto 0); -- address1
addr2: in std_logic_vector(FFTEXP-1 downto 0); -- address2
en_wrt: in std_logic; -- write enable for bank1, high active
din1: in complex; -- input1 that will be stored
din2: in complex; -- input2 that will be stored
dout1: out complex; -- output1 that is read from memory
dout2: out complex); -- output2 that is read from memory
end component;
-- import butterfly component
component butterfly
generic(RSTDEF: std_logic := '0');
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
swrst: in std_logic; -- software reset, RSTDEF active
en: in std_logic; -- enable, high active
din1: in complex; -- first complex in val
din2: in complex; -- second complex in val
w: in complex; -- twiddle factor
dout1: out complex; -- first complex out val
dout2: out complex); -- second complex out val
end component;
-- import delay elemnt for logic vectors
component delay_vec
generic(RSTDEF: std_logic := '0';
DATALEN: natural := 8;
DELAYLEN: natural := 8);
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
swrst: in std_logic; -- software reset, RSTDEF active
en: in std_logic; -- enable, high active
din: in std_logic_vector(DATALEN-1 downto 0); -- data in
dout: out std_logic_vector(DATALEN-1 downto 0)); -- data out
end component;
-- import delay element for bits
component delay_bit
generic(RSTDEF: std_logic := '0';
DELAYLEN: natural := 8);
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
swrst: in std_logic; -- software reset, RSTDEF active
en: in std_logic; -- enable, high active
din: in std_logic; -- data in
dout: out std_logic); -- data out
end component;
-- import twiddle factor component
component tf16
generic(RSTDEF: std_logic := '0';
FFTEXP: natural := 4);
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
swrst: in std_logic; -- software reset, RSTDEF active
en: in std_logic; -- enable, high active
addr: in std_logic_vector(FFTEXP-2 downto 0); -- address of twiddle factor
w: out complex); -- twiddle factor
end component;
-- define this FFT as 16-point (exponent = 4)
constant FFTEXP: natural := 4;
-- delay write address by 3 cycles
constant DELWADDR: natural := 3;
constant DELENAGU: natural := 3;
constant DELENDFFT: natural := 1;
-- INTERNALS
-- =========
-- define states for FSM of FFT
type TState is (SIDLE, SSET, SGET, SRUN);
signal state: TState := SIDLE;
-- intermediate signal for dout; used for muxing
signal dout_tmp: complex := COMPZERO;
-- signal to control enable of agu; used for muxing
signal en_agu_con: std_logic := '0';
-- signal to control software reset of agu; used for muxing
signal swrst_agu_con: std_logic := not RSTDEF;
-- address counter for get and set
signal addr_cnt: unsigned(FFTEXP downto 0) := (others => '0');
-- bit reversed address; async set from addr_cnt
signal addr_rev: std_logic_vector(FFTEXP-1 downto 0);
-- ======
-- INPUTS
-- ======
-- data in port of delay for end fft signal
signal din_end_fft: std_logic := '0';
-- enable signal for agu
signal en_agu: std_logic := '0';
-- current FFT stage / level for agu
signal lvl_agu: std_logic_vector(FFTEXP-2 downto 0) := (others => '0');
-- current butterfly number within current stage for agu
signal bfno_agu: std_logic_vector(FFTEXP-2 downto 0) := (others => '0');
-- address signals for membank A
signal addr1_mema: std_logic_vector(FFTEXP-1 downto 0) := (others => '0');
signal addr2_mema: std_logic_vector(FFTEXP-1 downto 0) := (others => '0');
-- write signal for membank A
signal en_wrt_mema: std_logic := '0';
-- data in ports for membank A
signal din1_mema: complex := COMPZERO;
signal din2_mema: complex := COMPZERO;
-- address signals for membank B
signal addr1_memb: std_logic_vector(FFTEXP-1 downto 0) := (others => '0');
signal addr2_memb: std_logic_vector(FFTEXP-1 downto 0) := (others => '0');
-- write signal for membank B
signal en_wrt_memb: std_logic := '0';
-- data in ports for membank B
signal din1_memb: complex := COMPZERO;
signal din2_memb: complex := COMPZERO;
-- data in ports for butterfly
signal din1_bf: complex := COMPZERO;
signal din2_bf: complex := COMPZERO;
-- twiddle factor for butterfly
signal w_bf: complex := COMPZERO;
-- address signal for twiddle factor unit
signal addr_tf: std_logic_vector(FFTEXP-2 downto 0) := (others => '0');
-- data in ports for write address delay
signal din_waddr1: std_logic_vector(FFTEXP-1 downto 0) := (others => '0');
signal din_waddr2: std_logic_vector(FFTEXP-1 downto 0) := (others => '0');
-- data in port for enable agu delay
signal din_enagu: std_logic := '0';
-- =======
-- OUTPUTS
-- =======
-- data out port of delay for end fft signal
signal dout_end_fft: std_logic;
-- address signals from agu for membank A
signal addra1_agu: std_logic_vector(FFTEXP-1 downto 0);
signal addra2_agu: std_logic_vector(FFTEXP-1 downto 0);
signal en_wrta_agu: std_logic;
-- address signals from agu for membank B
signal addrb1_agu: std_logic_vector(FFTEXP-1 downto 0);
signal addrb2_agu: std_logic_vector(FFTEXP-1 downto 0);
signal en_wrtb_agu: std_logic;
-- address signal for twiddle factor
signal addrtf_agu: std_logic_vector(FFTEXP-2 downto 0);
-- software reset signal for agu
signal swrst_agu: std_logic;
--data out ports for membank A
signal dout1_mema: complex;
signal dout2_mema: complex;
--data out ports for membank B
signal dout1_memb: complex;
signal dout2_memb: complex;
-- data out ports for butterfly
signal dout1_bf: complex;
signal dout2_bf: complex;
-- data out port for twiddle factor unit
signal w_tf: complex;
-- data out ports for write address delay
signal dout_waddr1: std_logic_vector(FFTEXP-1 downto 0);
signal dout_waddr2: std_logic_vector(FFTEXP-1 downto 0);
-- data out port for enable agu delay
signal dout_enagu: std_logic;
begin
dout <= dout_tmp;
-- done is set if we are in IDLE state
done <= '1' when state = SIDLE else '0';
-- multiplex enable signal for agu
en_agu <= '0' when en = '0' else en_agu_con;
-- multiplex swrst signal for agu
swrst_agu <= swrst when swrst = RSTDEF else swrst_agu_con;
-- calc bit reversed address
gen_rev: for i in 0 to FFTEXP-1 generate
addr_rev(i) <= std_logic(addr_cnt(FFTEXP-1 - i));
end generate;
process(clk, rst) is
-- reset this component
procedure reset is
begin
state <= SIDLE;
-- reset agu
lvl_agu <= (others => '0');
bfno_agu <= (others => '0');
en_agu_con <= '0';
swrst_agu_con <= not RSTDEF;
-- reset membank A
addr1_mema <= (others => '0');
addr2_mema <= (others => '0');
din1_mema <= COMPZERO;
din2_mema <= COMPZERO;
en_wrt_mema <= '0';
-- reset membank B
addr1_memb <= (others => '0');
addr2_memb <= (others => '0');
din1_memb <= COMPZERO;
din2_memb <= COMPZERO;
en_wrt_memb <= '0';
-- reset butterfly
din1_bf <= COMPZERO;
din2_bf <= COMPZERO;
w_bf <= COMPZERO;
-- reset twiddle factor unit
addr_tf <= (others => '0');
-- reset write address delay element
din_waddr1 <= (others => '0');
din_waddr2 <= (others => '0');
-- reset enable agu delay element
din_enagu <= '0';
--reset address counter
addr_cnt <= (others => '0');
-- reset delay for end_fft
din_end_fft <= '0';
end;
begin
if rst = RSTDEF then
reset;
elsif rising_edge(clk) then
if swrst = RSTDEF then
reset;
elsif en = '1' then
-- process state machine
case state is
when SIDLE =>
if set = '1' then
-- "set" signal received
state <= SSET;
-- store transmitted values in membank A in
-- bit reversed order
-- already store first value from din
addr_cnt <= addr_cnt + 1;
addr1_mema <= addr_rev;
din1_mema <= din;
-- also set addr2 and din2 and leave them so they
-- will not overwrite any values in the process
addr2_mema <= addr_rev;
din2_mema <= din;
-- enable write mode for membank A
en_wrt_mema <= '1';
elsif get = '1' then
-- "get" signal received
state <= SGET;
-- read values from membank A in normal order
-- addr_cnt defines address to be read
-- membanks should always be in read mode when
-- FSM is idle
addr_cnt <= addr_cnt + 1;
addr1_mema <= std_logic_vector(addr_cnt(FFTEXP-1 downto 0));
elsif start = '1' then
-- "start" signal received
state <= SRUN;
-- enable agu
en_agu_con <= '1';
end if;
when SSET =>
-- increment address count
-- bit reversed address will be updated automatically
addr_cnt <= addr_cnt + 1;
addr1_mema <= addr_rev;
din1_mema <= din;
-- if counter had overflow go back to idle state
-- and reset all used resources
if addr_cnt(FFTEXP) = '1' then
-- reset membank addresses and data in ports
addr1_mema <= (others => '0');
din1_mema <= COMPZERO;
addr2_mema <= (others => '0');
din2_mema <= COMPZERO;
-- disable write mode on membank A
en_wrt_mema <= '0';
-- reset addr_cnt
addr_cnt <= (others => '0');
-- go back to idle mode
state <= SIDLE;
end if;
when SGET =>
-- increment address count
-- this is the address that we read from
addr_cnt <= addr_cnt + 1;
addr1_mema <= std_logic_vector(addr_cnt(FFTEXP-1 downto 0));
dout_tmp <= dout1_mema;
-- if counter had overflow go back to idle state
-- and reset all used resources
if addr_cnt(FFTEXP) = '1' and addr_cnt(0) = '1' then
-- reset addr1 of membank A
addr1_mema <= (others => '0');
-- reset addr_cnt
addr_cnt <= (others => '0');
-- go back to idle mode
state <= SIDLE;
end if;
when SRUN =>
-- ================
-- BEGIN execute pipeline
-- apply write enables from agu
en_wrt_mema <= en_wrta_agu;
en_wrt_memb <= en_wrtb_agu;
-- apply address twiddle factor
addr_tf <= addrtf_agu;
-- apply twiddle factor
w_bf <= w_tf;
-- apply addresses for membanks and
-- values from membanks
if en_wrta_agu = '1' then
-- membank A is in write mode
-- feed address of A into delay element
din_waddr1 <= addra1_agu;
din_waddr2 <= addra2_agu;
-- get address for A from delay element
addr1_mema <= dout_waddr1;
addr2_mema <= dout_waddr2;
-- get address directly from AGU
addr1_memb <= addrb1_agu;
addr2_memb <= addrb2_agu;
-- apply values from membank B to butterfly
din1_bf <= dout1_memb;
din2_bf <= dout2_memb;
-- apply values from butterfly to membank A
din1_mema <= dout1_bf;
din2_mema <= dout2_bf;
else
-- membank B is in write mode
-- feed address of B into delay element
din_waddr1 <= addrb1_agu;
din_waddr2 <= addrb2_agu;
-- get address for mema from delay element
addr1_memb <= dout_waddr1;
addr2_memb <= dout_waddr2;
-- get address directly from AGU
addr1_mema <= addra1_agu;
addr2_mema <= addra2_agu;
-- apply values from membank A to butterfly
din1_bf <= dout1_mema;
din2_bf <= dout2_mema;
-- apply values from butterfly to membank B
din1_memb <= dout1_bf;
din2_memb <= dout2_bf;
end if;
-- END execute pipeline
-- ====================
-- din_enagu only stays high for one cycle
din_enagu <= '0';
-- din_end_fft only stays high for one cycle
din_end_fft <= '0';
-- if agu is still enabled keep incrementing butterflies
if en_agu_con = '1' then
bfno_agu <= std_logic_vector(unsigned(bfno_agu) + 1);
end if;
-- if we have reached last butterfly wait for pipeline
-- to finish
if bfno_agu = "111" then
en_agu_con <= '0';
din_enagu <= '1';
end if;
-- this will only be the case if we have reached last butterfly
-- and agu was disabled
if dout_enagu = '1' then
-- reset butterfly number
bfno_agu <= (others => '0');
if lvl_agu = "011" then
-- set end_fft
din_end_fft <= '1';
--swrst_agu_con <= RSTDEF;
else
-- go to next level
-- enable agu again
lvl_agu <= std_logic_vector(unsigned(lvl_agu) + 1);
en_agu_con <= '1';
end if;
end if;
-- this will only be the case if we have reached last butterfly
-- and last level
if dout_end_fft = '1' then
-- final level was reached: we are done
-- reset all internal states
-- membanks not included!
state <= SIDLE;
reset;
end if;
end case;
end if;
end if;
end process;
-- create instance of address generation unit
agu: addr_gen
generic map(RSTDEF => RSTDEF,
FFTEXP => FFTEXP)
port map(rst => rst,
clk => clk,
swrst => swrst_agu,
en => en_agu,
lvl => lvl_agu,
bfno => bfno_agu,
addra1 => addra1_agu,
addra2 => addra2_agu,
en_wrta => en_wrta_agu,
addrb1 => addrb1_agu,
addrb2 => addrb2_agu,
en_wrtb => en_wrtb_agu,
addrtf => addrtf_agu);
-- create instance of twiddle factor unit
tfu: tf16
generic map(RSTDEF => RSTDEF,
FFTEXP => FFTEXP)
port map(rst => rst,
clk => clk,
swrst => swrst,
en => en,
addr => addr_tf,
w => w_tf);
-- create instance of memory bank A
mem_a: membank
generic map(RSTDEF => RSTDEF,
FFTEXP => FFTEXP)
port map(rst => rst,
clk => clk,
swrst => swrst,
en => en,
addr1 => addr1_mema,
addr2 => addr2_mema,
en_wrt => en_wrt_mema,
din1 => din1_mema,
din2 => din2_mema,
dout1 => dout1_mema,
dout2 => dout2_mema);
-- create instance of memory bank B
mem_b: membank
generic map(RSTDEF => RSTDEF,
FFTEXP => FFTEXP)
port map(rst => rst,
clk => clk,
swrst => swrst,
en => en,
addr1 => addr1_memb,
addr2 => addr2_memb,
en_wrt => en_wrt_memb,
din1 => din1_memb,
din2 => din2_memb,
dout1 => dout1_memb,
dout2 => dout2_memb);
-- create instance of butterfly unit
bfu: butterfly
generic map(RSTDEF => RSTDEF)
port map(rst => rst,
clk => clk,
swrst => swrst,
en => en,
din1 => din1_bf,
din2 => din2_bf,
w => w_bf,
dout1 => dout1_bf,
dout2 => dout2_bf);
-- create instance of delay unit for write address 1
del_waddr1: delay_vec
generic map(RSTDEF => RSTDEF,
DATALEN => FFTEXP,
DELAYLEN => DELWADDR)
port map(rst => rst,
clk => clk,
swrst => swrst,
en => en,
din => din_waddr1,
dout => dout_waddr1);
-- create instance of delay unit for write address 1
del_waddr2: delay_vec
generic map(RSTDEF => RSTDEF,
DATALEN => FFTEXP,
DELAYLEN => DELWADDR)
port map(rst => rst,
clk => clk,
swrst => swrst,
en => en,
din => din_waddr2,
dout => dout_waddr2);
-- create instance of delay unit for enable signal of agu
del_enagu: delay_bit
generic map(RSTDEF => RSTDEF,
DELAYLEN => DELENAGU)
port map(rst => rst,
clk => clk,
swrst => swrst,
en => en,
din => din_enagu,
dout => dout_enagu);
del_end_fft: delay_bit
generic map(RSTDEF => RSTDEF,
DELAYLEN => DELENDFFT)
port map(rst => rst,
clk => clk,
swrst => swrst,
en => en,
din => din_end_fft,
dout => dout_end_fft);
end;
| mit | 7ec870b52030467f046ffa855d2424c4 | 0.457062 | 4.434759 | false | false | false | false |
sergev/vak-opensource | hardware/s3esk-startup/control.vhd | 1 | 24,510 | --
-- Definition of a dual port ROM for KCPSM2 or KCPSM3 program defined by control.psm
-- and assmbled using KCPSM2 or KCPSM3 assembler.
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
--
entity control is
Port ( address : in std_logic_vector(9 downto 0);
instruction : out std_logic_vector(17 downto 0);
proc_reset : out std_logic;
clk : in std_logic);
end control;
--
architecture low_level_definition of control is
--
-- Declare signals internal to this module
--
signal jaddr : std_logic_vector(10 downto 0);
signal jparity : std_logic_vector(0 downto 0);
signal jdata : std_logic_vector(7 downto 0);
signal doa : std_logic_vector(7 downto 0);
signal dopa : std_logic_vector(0 downto 0);
signal tdo1 : std_logic;
signal tdo2 : std_logic;
signal update : std_logic;
signal shift : std_logic;
signal reset : std_logic;
signal tdi : std_logic;
signal sel1 : std_logic;
signal drck1 : std_logic;
signal drck1_buf : std_logic;
signal sel2 : std_logic;
signal drck2 : std_logic;
signal capture : std_logic;
signal tap5 : std_logic;
signal tap11 : std_logic;
signal tap17 : std_logic;
--
-- Attributes to define ROM contents during implementation synthesis.
-- The information is repeated in the generic map for functional simulation
--
attribute INIT_00 : string;
attribute INIT_01 : string;
attribute INIT_02 : string;
attribute INIT_03 : string;
attribute INIT_04 : string;
attribute INIT_05 : string;
attribute INIT_06 : string;
attribute INIT_07 : string;
attribute INIT_08 : string;
attribute INIT_09 : string;
attribute INIT_0A : string;
attribute INIT_0B : string;
attribute INIT_0C : string;
attribute INIT_0D : string;
attribute INIT_0E : string;
attribute INIT_0F : string;
attribute INIT_10 : string;
attribute INIT_11 : string;
attribute INIT_12 : string;
attribute INIT_13 : string;
attribute INIT_14 : string;
attribute INIT_15 : string;
attribute INIT_16 : string;
attribute INIT_17 : string;
attribute INIT_18 : string;
attribute INIT_19 : string;
attribute INIT_1A : string;
attribute INIT_1B : string;
attribute INIT_1C : string;
attribute INIT_1D : string;
attribute INIT_1E : string;
attribute INIT_1F : string;
attribute INIT_20 : string;
attribute INIT_21 : string;
attribute INIT_22 : string;
attribute INIT_23 : string;
attribute INIT_24 : string;
attribute INIT_25 : string;
attribute INIT_26 : string;
attribute INIT_27 : string;
attribute INIT_28 : string;
attribute INIT_29 : string;
attribute INIT_2A : string;
attribute INIT_2B : string;
attribute INIT_2C : string;
attribute INIT_2D : string;
attribute INIT_2E : string;
attribute INIT_2F : string;
attribute INIT_30 : string;
attribute INIT_31 : string;
attribute INIT_32 : string;
attribute INIT_33 : string;
attribute INIT_34 : string;
attribute INIT_35 : string;
attribute INIT_36 : string;
attribute INIT_37 : string;
attribute INIT_38 : string;
attribute INIT_39 : string;
attribute INIT_3A : string;
attribute INIT_3B : string;
attribute INIT_3C : string;
attribute INIT_3D : string;
attribute INIT_3E : string;
attribute INIT_3F : string;
attribute INITP_00 : string;
attribute INITP_01 : string;
attribute INITP_02 : string;
attribute INITP_03 : string;
attribute INITP_04 : string;
attribute INITP_05 : string;
attribute INITP_06 : string;
attribute INITP_07 : string;
--
-- Attributes to define ROM contents during implementation synthesis.
--
attribute INIT_00 of ram_1024_x_18 : label is "200240010EF40F01ED030DFFE00200080065010C052E003A010C0510C00100F6";
attribute INIT_01 of ram_1024_x_18 : label is "CE0100A4ED03EDFF400C01165C0EEF00CE0100A4102C4DFF10294D006D03541C";
attribute INIT_02 of ram_1024_x_18 : label is "5037208060006A02A000C0804000400E541E200240010EF40F0101165C25EF00";
attribute INIT_03 of ram_1024_x_18 : label is "00CC054100CC055000CC0553A000CA80EA020A0C40370A0250362001E000A07F";
attribute INIT_04 of ram_1024_x_18 : label is "0553009800CC054500CC053300CC052D00CC054E00CC054100CC055400CC0552";
attribute INIT_05 of ram_1024_x_18 : label is "00CC054B009800CC055200CC054500CC055400CC055200CC054100CC055400CC";
attribute INIT_06 of ram_1024_x_18 : label is "056900CC057800CC052E00CC057700CC057700CC0577A00000CC055400CC0549";
attribute INIT_07 of ram_1024_x_18 : label is "056D00CC056F00CC056300CC052E00CC057800CC056E00CC056900CC056C00CC";
attribute INIT_08 of ram_1024_x_18 : label is "057200CC056100CC057400CC057300CC056500CC053300CC057300CC052F00CC";
attribute INIT_09 of ram_1024_x_18 : label is "0128A000549CC001000BA00000CC0520A00000CC057200CC056500CC057400CC";
attribute INIT_0A of ram_1024_x_18 : label is "00A90432A00054AAC30100A40314A00054A5C201009F0219A00054A0C101009B";
attribute INIT_0B of ram_1024_x_18 : label is "C408A4F01450A00000B3C440A4F8A000C440E401009BC440E401A00054AFC401";
attribute INIT_0C of ram_1024_x_18 : label is "C440C40CA4F01450A000C44004F0009F00B904060406040604071450009B00B9";
attribute INIT_0D of ram_1024_x_18 : label is "E401C440040EA000C44004F0009F00B3C44004060406040704071450009B00B3";
attribute INIT_0E of ram_1024_x_18 : label is "000E000E000EA5F0C440E4014002009BC440E401009BC440E4014502009BC440";
attribute INIT_0F of ram_1024_x_18 : label is "00B90420009F00B900A400B900A900B9043000A9A000009FC4400404D500000E";
attribute INIT_10 of ram_1024_x_18 : label is "C580A50F51122510A00000A400A400BD050100BD050C00BD050600BD0528009F";
attribute INIT_11 of ram_1024_x_18 : label is "E000C0804001512040006003E001A00000BD0518A00000BDC5C0A50FA00000BD";
attribute INIT_12 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000080016001";
attribute INIT_13 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_14 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_15 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_16 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_17 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_18 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_19 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_20 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_21 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_22 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_23 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_24 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_25 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_26 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_27 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_28 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_29 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_30 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_31 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_32 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_33 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_34 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_35 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_36 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_37 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_38 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_39 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3F of ram_1024_x_18 : label is "4119000000000000000000000000000000000000000000000000000000000000";
attribute INITP_00 of ram_1024_x_18 : label is "33333333333332CCCF3333333CCCCCCCCCCAAED8D0A3D03D78FD7DD34088F3CF";
attribute INITP_01 of ram_1024_x_18 : label is "CFFF3B82A8838E0E228FAA8F80A3EA8F02E28E2DCB72DCB72D2CB33333333333";
attribute INITP_02 of ram_1024_x_18 : label is "00000000000000000000000000000000000000000000000C834ACB0B0DBF3333";
attribute INITP_03 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_04 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_05 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_06 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_07 of ram_1024_x_18 : label is "C000000000000000000000000000000000000000000000000000000000000000";
--
begin
--
--Instantiate the Xilinx primitive for a block RAM
ram_1024_x_18: RAMB16_S9_S18
--synthesis translate_off
--INIT values repeated to define contents for functional simulation
generic map (INIT_00 => X"200240010EF40F01ED030DFFE00200080065010C052E003A010C0510C00100F6",
INIT_01 => X"CE0100A4ED03EDFF400C01165C0EEF00CE0100A4102C4DFF10294D006D03541C",
INIT_02 => X"5037208060006A02A000C0804000400E541E200240010EF40F0101165C25EF00",
INIT_03 => X"00CC054100CC055000CC0553A000CA80EA020A0C40370A0250362001E000A07F",
INIT_04 => X"0553009800CC054500CC053300CC052D00CC054E00CC054100CC055400CC0552",
INIT_05 => X"00CC054B009800CC055200CC054500CC055400CC055200CC054100CC055400CC",
INIT_06 => X"056900CC057800CC052E00CC057700CC057700CC0577A00000CC055400CC0549",
INIT_07 => X"056D00CC056F00CC056300CC052E00CC057800CC056E00CC056900CC056C00CC",
INIT_08 => X"057200CC056100CC057400CC057300CC056500CC053300CC057300CC052F00CC",
INIT_09 => X"0128A000549CC001000BA00000CC0520A00000CC057200CC056500CC057400CC",
INIT_0A => X"00A90432A00054AAC30100A40314A00054A5C201009F0219A00054A0C101009B",
INIT_0B => X"C408A4F01450A00000B3C440A4F8A000C440E401009BC440E401A00054AFC401",
INIT_0C => X"C440C40CA4F01450A000C44004F0009F00B904060406040604071450009B00B9",
INIT_0D => X"E401C440040EA000C44004F0009F00B3C44004060406040704071450009B00B3",
INIT_0E => X"000E000E000EA5F0C440E4014002009BC440E401009BC440E4014502009BC440",
INIT_0F => X"00B90420009F00B900A400B900A900B9043000A9A000009FC4400404D500000E",
INIT_10 => X"C580A50F51122510A00000A400A400BD050100BD050C00BD050600BD0528009F",
INIT_11 => X"E000C0804001512040006003E001A00000BD0518A00000BDC5C0A50FA00000BD",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000080016001",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"4119000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"33333333333332CCCF3333333CCCCCCCCCCAAED8D0A3D03D78FD7DD34088F3CF",
INITP_01 => X"CFFF3B82A8838E0E228FAA8F80A3EA8F02E28E2DCB72DCB72D2CB33333333333",
INITP_02 => X"00000000000000000000000000000000000000000000000C834ACB0B0DBF3333",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"C000000000000000000000000000000000000000000000000000000000000000")
--synthesis translate_on
port map( DIB => "0000000000000000",
DIPB => "00",
ENB => '1',
WEB => '0',
SSRB => '0',
CLKB => clk,
ADDRB => address,
DOB => instruction(15 downto 0),
DOPB => instruction(17 downto 16),
DIA => jdata,
DIPA => jparity,
ENA => sel1,
WEA => '1',
SSRA => '0',
CLKA => update,
ADDRA=> jaddr,
DOA => doa(7 downto 0),
DOPA => dopa);
v2_bscan: BSCAN_VIRTEX2
port map( TDO1 => tdo1,
TDO2 => tdo2,
UPDATE => update,
SHIFT => shift,
RESET => reset,
TDI => tdi,
SEL1 => sel1,
DRCK1 => drck1,
SEL2 => sel2,
DRCK2 => drck2,
CAPTURE => capture);
--buffer signal used as a clock
upload_clock: BUFG
port map( I => drck1,
O => drck1_buf);
-- Assign the reset to be active whenever the uploading subsystem is active
proc_reset <= sel1;
srlC1: SRLC16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => tdi,
CE => '1',
CLK => drck1_buf,
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '1',
Q => jaddr(10),
Q15 => jaddr(8));
flop1: FD
port map ( D => jaddr(10),
Q => jaddr(9),
C => drck1_buf);
srlC2: SRLC16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => jaddr(8),
CE => '1',
CLK => drck1_buf,
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '1',
Q => jaddr(7),
Q15 => tap5);
flop2: FD
port map ( D => jaddr(7),
Q => jaddr(6),
C => drck1_buf);
srlC3: SRLC16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => tap5,
CE => '1',
CLK => drck1_buf,
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '1',
Q => jaddr(5),
Q15 => jaddr(3));
flop3: FD
port map ( D => jaddr(5),
Q => jaddr(4),
C => drck1_buf);
srlC4: SRLC16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => jaddr(3),
CE => '1',
CLK => drck1_buf,
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '1',
Q => jaddr(2),
Q15 => tap11);
flop4: FD
port map ( D => jaddr(2),
Q => jaddr(1),
C => drck1_buf);
srlC5: SRLC16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => tap11,
CE => '1',
CLK => drck1_buf,
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '1',
Q => jaddr(0),
Q15 => jdata(7));
flop5: FD
port map ( D => jaddr(0),
Q => jparity(0),
C => drck1_buf);
srlC6: SRLC16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => jdata(7),
CE => '1',
CLK => drck1_buf,
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '1',
Q => jdata(6),
Q15 => tap17);
flop6: FD
port map ( D => jdata(6),
Q => jdata(5),
C => drck1_buf);
srlC7: SRLC16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => tap17,
CE => '1',
CLK => drck1_buf,
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '1',
Q => jdata(4),
Q15 => jdata(2));
flop7: FD
port map ( D => jdata(4),
Q => jdata(3),
C => drck1_buf);
srlC8: SRLC16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => jdata(2),
CE => '1',
CLK => drck1_buf,
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '1',
Q => jdata(1),
Q15 => tdo1);
flop8: FD
port map ( D => jdata(1),
Q => jdata(0),
C => drck1_buf);
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- END OF FILE control.vhd
--
------------------------------------------------------------------------------------
| apache-2.0 | 123f5fdf0ef6e912171c82175f315f64 | 0.689147 | 4.16695 | false | false | false | false |
sergev/vak-opensource | hardware/vhdl/adder_tb.vhdl | 1 | 1,964 | -- A testbench has no ports.
entity adder_tb is
end adder_tb;
architecture behav of adder_tb is
-- Declaration of the component that will be instantiated.
component adder
port (i0, i1 : in bit; ci : in bit; s : out bit; co : out bit);
end component;
-- Specifies which entity is bound with the component.
for adder_0: adder use entity work.adder;
signal i0, i1, ci, s, co : bit;
begin
-- Component instantiation.
adder_0: adder port map (i0 => i0, i1 => i1, ci => ci,
s => s, co => co);
-- This process does the real job.
process
type pattern_type is record
-- The inputs of the adder.
i0, i1, ci : bit;
-- The expected outputs of the adder.
s, co : bit;
end record;
-- The patterns to apply.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array :=
(('0', '0', '0', '0', '0'),
('0', '0', '1', '1', '0'),
('0', '1', '0', '1', '0'),
('0', '1', '1', '0', '1'),
('1', '0', '0', '1', '0'),
('1', '0', '1', '0', '1'),
('1', '1', '0', '0', '1'),
('1', '1', '1', '1', '1'));
begin
-- Check each pattern.
for i in patterns'range loop
-- Set the inputs.
i0 <= patterns(i).i0;
i1 <= patterns(i).i1;
ci <= patterns(i).ci;
-- Wait for the results.
wait for 1 ns;
-- Check the outputs.
assert s = patterns(i).s
report "bad sum value" severity error;
assert co = patterns(i).co
report "bad carray out value" severity error;
end loop;
assert false report "end of test" severity note;
-- Wait forever; this will finish the simulation.
wait;
end process;
end behav;
| apache-2.0 | 5c865a407db833eeff46ae4a786ccd9b | 0.479124 | 3.677903 | false | false | false | false |
ShepardSiegel/ocpi | vhdl/ocpiTypes.vhd | 1 | 2,326 | -- ocpiTypes.vhd
-- Copyright (c) 2009 Atomic Rules LLC - ALL RIGHTS RESERVED
--
-- 2009-07-13 ssiegel creation from names in OCWip.bsv
library IEEE;
use IEEE.std_logic_1164.all;
package ocpiTypes is
subtype wciCtlOpT is std_logic_vector(2 downto 0);
constant wciCtlOp_Initialize : wciCtlOpT := "000";
constant wciCtlOp_Start : wciCtlOpT := "001";
constant wciCtlOp_Stop : wciCtlOpT := "010";
constant wciCtlOp_Release : wciCtlOpT := "011";
constant wciCtlOp_Test : wciCtlOpT := "100";
constant wciCtlOp_BeforeQuery : wciCtlOpT := "101";
constant wciCtlOp_AfterConfig : wciCtlOpT := "110";
constant wciCtlOp_Rsvd7 : wciCtlOpT := "111";
subtype wciCtlStT is std_logic_vector(2 downto 0);
constant wciCtlSt_Exists : wciCtlStT := "000";
constant wciCtlSt_Initialized : wciCtlStT := "001";
constant wciCtlSt_Operating : wciCtlStT := "010";
constant wciCtlSt_Suspended : wciCtlStT := "011";
constant wciCtlSt_Unusable : wciCtlStT := "100";
constant wciCtlSt_Rsvd5 : wciCtlStT := "101";
constant wciCtlSt_Rsvd6 : wciCtlStT := "110";
constant wciCtlSt_Rsvd7 : wciCtlStT := "111";
subtype wciRespT is std_logic_vector(31 downto 0);
constant wciResp_OK : wciRespT := X"C0DE_4201";
constant wciResp_Error : wciRespT := X"C0DE_4202";
constant wciResp_Timeout : wciRespT := X"C0DE_4203";
constant wciResp_Reset : wciRespT := X"C0DE_4204";
subtype ocpCmdT is std_logic_vector(2 downto 0);
constant ocpCmd_IDLE : ocpCmdT := "000";
constant ocpCmd_WR : ocpCmdT := "001";
constant ocpCmd_RD : ocpCmdT := "010";
subtype ocpRespT is std_logic_vector(1 downto 0);
constant ocpResp_NULL : ocpRespT := "00";
constant ocpResp_DVA : ocpRespT := "01";
constant ocpResp_FAIL : ocpRespT := "10";
constant ocpResp_ERR : ocpRespT := "11";
function to_std_logic(bool:boolean) return std_logic;
end package ocpiTypes;
package body ocpiTypes is
function to_std_logic (bool:boolean) return std_logic is begin
if (bool) then return '1'; else return '0'; end if;
end function to_std_logic;
end package body ocpiTypes;
| lgpl-3.0 | 636248de176b02cdb10589f39fb2592f | 0.628547 | 2.978233 | false | false | false | false |
FinnK/lems2hdl | work/N3_pointCellCondBased/ISIM_output/forwardRateh1.vhdl | 1 | 10,652 |
---------------------------------------------------------------------
-- Standard Library bits
---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- For Modelsim
--use ieee.fixed_pkg.all;
--use ieee.fixed_float_types.ALL;
-- For ISE
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.fixed_float_types.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Entity Description
---------------------------------------------------------------------
entity forwardRateh1 is
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC; --SYNCHRONOUS RESET
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
component_done : out STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_per_time_rate : in sfixed (18 downto -2);
param_voltage_midpoint : in sfixed (2 downto -22);
param_voltage_scale : in sfixed (2 downto -22);
param_voltage_inv_scale_inv : in sfixed (22 downto -2);
exposure_per_time_r : out sfixed (18 downto -2);
derivedvariable_per_time_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_r_in : in sfixed (18 downto -2);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end forwardRateh1;
---------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-- Architecture Begins
-------------------------------------------------------------------------------------------
architecture RTL of forwardRateh1 is
signal COUNT : unsigned(2 downto 0) := "000";
signal childrenCombined_Component_done_single_shot_fired : STD_LOGIC := '0';
signal childrenCombined_Component_done_single_shot : STD_LOGIC := '0';
signal childrenCombined_Component_done : STD_LOGIC := '0';
signal Component_done_int : STD_LOGIC := '0';
signal subprocess_der_int_pre_ready : STD_LOGIC := '0';
signal subprocess_der_int_ready : STD_LOGIC := '0';
signal subprocess_der_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_pre_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_ready : STD_LOGIC := '0';
signal subprocess_dyn_ready : STD_LOGIC := '0';
signal subprocess_model_ready : STD_LOGIC := '1';
signal subprocess_all_ready_shotdone : STD_LOGIC := '1';
signal subprocess_all_ready_shot : STD_LOGIC := '0';
signal subprocess_all_ready : STD_LOGIC := '0';signal pre_exp_r_exponential_result1 : sfixed(18 downto -13);
signal pre_exp_r_exponential_result1_next : sfixed(18 downto -13);
signal exp_r_exponential_result1 : sfixed(18 downto -13);
Component ParamExp is
generic(
BIT_TOP : integer := 20;
BIT_BOTTOM : integer := -20);
port(
clk : In Std_logic;
init_model : In Std_logic;
Start : In Std_logic;
Done : Out Std_logic;
X : In sfixed(BIT_TOP downto BIT_BOTTOM);
Output : Out sfixed(BIT_TOP downto BIT_BOTTOM)
);
end Component;
---------------------------------------------------------------------
-- Derived Variables and parameters
---------------------------------------------------------------------
signal DerivedVariable_per_time_r : sfixed (18 downto -2) := to_sfixed(0.0 ,18,-2);
signal DerivedVariable_per_time_r_next : sfixed (18 downto -2) := to_sfixed(0.0 ,18,-2);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState internal Variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Output Port internal Variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Child Components
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Begin Internal Processes
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Child EDComponent Instantiations and corresponding internal variables
---------------------------------------------------------------------
derived_variable_pre_process_comb :process ( sysparam_time_timestep, param_voltage_midpoint, param_voltage_scale, requirement_voltage_v , param_per_time_rate,param_voltage_inv_scale_inv,exp_r_exponential_result1 )
begin
pre_exp_r_exponential_result1_next <= resize( ( ( requirement_voltage_v - param_voltage_midpoint ) * param_voltage_inv_scale_inv ) ,18,-13);
end process derived_variable_pre_process_comb;
derived_variable_pre_process_syn :process ( clk, init_model )
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then
pre_exp_r_exponential_result1 <= to_sfixed(0,18,-13);
else
if subprocess_all_ready_shot = '1' then
pre_exp_r_exponential_result1 <= pre_exp_r_exponential_result1_next;
end if;
end if;
end if;
subprocess_der_int_pre_ready <= '1';
end process derived_variable_pre_process_syn;
ParamExp_r_exponential_result1 : ParamExp
generic map(
BIT_TOP => 18,
BIT_BOTTOM => -13
)
port map ( clk => clk,
init_model => init_model,
Start => step_once_go,
Done => subprocess_der_int_ready,
X => pre_exp_r_exponential_result1 ,
Output => exp_r_exponential_result1
);
derived_variable_process_comb :process ( sysparam_time_timestep, param_voltage_midpoint, param_voltage_scale, requirement_voltage_v , param_per_time_rate,param_voltage_inv_scale_inv,exp_r_exponential_result1 )
begin
derivedvariable_per_time_r_next <= resize(( param_per_time_rate * exp_r_exponential_result1 ),18,-2);
subprocess_der_ready <= '1';
end process derived_variable_process_comb;
derived_variable_process_syn :process ( clk,init_model )
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
derivedvariable_per_time_r <= derivedvariable_per_time_r_next;
end if;
end if;
end process derived_variable_process_syn;
---------------------------------------------------------------------
dynamics_pre_process_comb :process ( sysparam_time_timestep )
begin
end process dynamics_pre_process_comb;
dynamics_pre_process_syn :process ( clk, init_model )
begin
subprocess_dyn_int_pre_ready <= '1';
end process dynamics_pre_process_syn;
--No dynamics with complex equations found
subprocess_dyn_int_ready <= '1';
state_variable_process_dynamics_comb :process (sysparam_time_timestep)
begin
subprocess_dyn_ready <= '1';
end process state_variable_process_dynamics_comb;
state_variable_process_dynamics_syn :process (CLK,init_model)
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
end if;
end if;
end process state_variable_process_dynamics_syn;
------------------------------------------------------------------------------------------------------
-- EDState Variable Drivers
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to exposures
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to output state variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign derived variables to exposures
---------------------------------------------------------------------
exposure_per_time_r <= derivedvariable_per_time_r_in;derivedvariable_per_time_r_out <= derivedvariable_per_time_r;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Subprocess ready process
---------------------------------------------------------------------
subprocess_all_ready_process: process(step_once_go,subprocess_der_int_ready,subprocess_der_int_pre_ready,subprocess_der_ready,subprocess_dyn_int_pre_ready,subprocess_dyn_int_ready,subprocess_dyn_ready,subprocess_model_ready)
begin
if step_once_go = '0' and subprocess_der_int_ready = '1' and subprocess_der_int_pre_ready = '1'and subprocess_der_ready ='1' and subprocess_dyn_int_ready = '1' and subprocess_dyn_int_pre_ready = '1' and subprocess_dyn_ready = '1' and subprocess_model_ready = '1' then
subprocess_all_ready <= '1';
else
subprocess_all_ready <= '0';
end if;
end process subprocess_all_ready_process;
subprocess_all_ready_shot_process : process(clk)
begin
if rising_edge(clk) then
if (init_model='1') then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '1';
else
if subprocess_all_ready = '1' and subprocess_all_ready_shotdone = '0' then
subprocess_all_ready_shot <= '1';
subprocess_all_ready_shotdone <= '1';
elsif subprocess_all_ready_shot = '1' then
subprocess_all_ready_shot <= '0';
elsif subprocess_all_ready = '0' then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '0';
end if;
end if;
end if;
end process subprocess_all_ready_shot_process;
---------------------------------------------------------------------
count_proc:process(clk)
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then COUNT <= "001";
component_done_int <= '1';
else if step_once_go = '1' then
COUNT <= "000";
component_done_int <= '0';
elsif COUNT = "001" then
component_done_int <= '1';
elsif subprocess_all_ready_shot = '1' then
COUNT <= COUNT + 1;
component_done_int <= '0';
end if;
end if;
end if;
end process count_proc;
component_done <= component_done_int;
end RTL;
| lgpl-3.0 | 331ea069e6b2ea55b832f74381be47e7 | 0.506947 | 4.08906 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/xilinx/openmac/src/ipifMasterHandler-rtl-ea.vhd | 2 | 12,548 | -------------------------------------------------------------------------------
--! @file ipifMasterHandler-rtl-ea.vhd
--
--! @brief IPIF Master handler
--
--! @details This is the IPIF master handler converting generic master interface
--! to IPIF.
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
--! use global library
use work.global.all;
entity ipifMasterHandler is
generic (
--! Master address width
gMasterAddrWidth : natural := 31;
--! Master burst count width
gMasterBurstCountWidth : natural := 4;
--! IPIF address width
gIpifAddrWidth : natural := 32;
--! IPIF length width
gIpifLength : natural := 12
);
port (
--TODO: Add doxygen comments!
-- Common clock and reset
iRst : in std_logic;
iClk : in std_logic;
-- IPIF Master
iIpif_cmdAck : in std_logic;
iIpif_cmplt : in std_logic;
iIpif_error : in std_logic; --FIXME: Unused input
iIpif_rearbitrate : in std_logic; --FIXME: Unused input
iIpif_cmdTimeout : in std_logic; --FIXME: Unused input
oIpif_type : out std_logic;
oIpif_addr : out std_logic_vector(gIpifAddrWidth-1 downto 0);
oIpif_length : out std_logic_vector(gIpifLength-1 downto 0);
oIpif_be : out std_logic_vector(3 downto 0);
oIpif_lock : out std_logic;
oIpif_reset : out std_logic;
iIpif_rdData : in std_logic_vector(31 downto 0);
iIpif_rdRem : in std_logic_vector(3 downto 0); --FIXME: Unused input
oIpif_rdReq : out std_logic;
inIpif_rdSof : in std_logic;
inIpif_rdEof : in std_logic;
inIpif_rdSrcRdy : in std_logic;
inIpif_rdSrcDsc : in std_logic; --FIXME: Unused input
onIpif_rdDstRdy : out std_logic;
onIpif_rdDstDsc : out std_logic;
oIpif_wrData : out std_logic_vector(31 downto 0);
oIpif_wrRem : out std_logic_vector(3 downto 0);
oIpif_wrReq : out std_logic;
onIpif_wrSof : out std_logic;
onIpif_wrEof : out std_logic;
onIpif_wrSrcRdy : out std_logic;
onIpif_wrSrcDsc : out std_logic;
inIpif_wrDstRdy : in std_logic;
inIpif_wrDstDsc : in std_logic; --FIXME: Unused input
-- Generic master interface
iMasterRead : in std_logic;
iMasterWrite : in std_logic;
iMasterAddress : in std_logic_vector(gMasterAddrWidth-1 downto 0);
iMasterWritedata : in std_logic_vector(31 downto 0);
iMasterBurstcount : in std_logic_vector(gMasterBurstCountWidth-1 downto 0);
iMasterBurstcounter : in std_logic_vector(gMasterBurstCountWidth-1 downto 0);
oMasterReaddata : out std_logic_vector(31 downto 0);
oMasterWaitrequest : out std_logic;
oMasterReaddatavalid : out std_logic
);
end ipifMasterHandler;
architecture rtl of ipifMasterHandler is
--signals for requesting transfers
signal masterWrite : std_logic;
signal masterRead : std_logic;
signal nMasterEnable : std_logic;
signal masterWrite_l : std_logic;
signal masterRead_l : std_logic;
signal masterWrite_rise : std_logic;
signal masterRead_rise : std_logic;
signal masterWrite_fall : std_logic;
signal masterRead_fall : std_logic;
signal ipifWriteReq_reg : std_logic;
signal ipifWriteReq_next : std_logic;
signal ipifReadReq_reg : std_logic;
signal ipifReadReq_next : std_logic;
signal ipif_rdDstRdy : std_logic;
--signals for the transfer
type tTfState is (
sIdle,
sSof, sTf, sEof,
sSEof, --start/end of frame (single beat)
sWaitForCmplt
);
signal writeTf_reg : tTfState;
signal writeTf_next : tTfState;
signal readTf : tTfState;
begin
masterWrite <= iMasterWrite and not nMasterEnable;
masterRead <= iMasterRead and not nMasterEnable;
--reserved
oIpif_lock <= cInactivated;
oIpif_reset <= cInactivated;
--delay some signals..
del_proc : process(iClk, iRst)
begin
if iRst = cActivated then
masterWrite_l <= cInactivated;
masterRead_l <= cInactivated;
nMasterEnable <= cnActivated;
elsif rising_edge(iClk) then
masterWrite_l <= masterWrite;
masterRead_l <= masterRead;
if iIpif_cmplt = cActivated then
nMasterEnable <= cnActivated;
elsif masterWrite_fall = cActivated or masterRead_fall = cActivated then
nMasterEnable <= cnInactivated; --write/read done, wait for Mst_Cmplt
end if;
end if;
end process;
--generate pulse if write/read is asserted
masterWrite_rise <= cActivated when masterWrite_l = cInactivated and masterWrite = cActivated else
cInactivated;
masterRead_rise <= cActivated when masterRead_l = cInactivated and masterRead = cActivated else
cInactivated;
masterWrite_fall <= cActivated when masterWrite_l = cActivated and masterWrite = cInactivated else
cInactivated;
masterRead_fall <= cActivated when masterRead_l = cActivated and masterRead = cInactivated else
cInactivated;
--generate req qualifiers
req_proc : process(iClk, iRst)
begin
if iRst = cActivated then
ipifWriteReq_reg <= cInactivated;
ipifReadReq_reg <= cInactivated;
ipif_rdDstRdy <= cInactivated;
elsif rising_edge(iClk) then
ipifWriteReq_reg <= ipifWriteReq_next;
ipifReadReq_reg <= ipifReadReq_next;
if masterRead = cActivated then
ipif_rdDstRdy <= cActivated;
elsif readTf = sEof and inIpif_rdSrcRdy = cnActivated then
ipif_rdDstRdy <= cInactivated;
end if;
end if;
end process;
onIpif_rdDstRdy <= not ipif_rdDstRdy;
oIpif_rdReq <= ipifReadReq_reg;
oIpif_wrReq <= ipifWriteReq_reg;
oIpif_type <= cInactivated when iMasterBurstcount < 2 else --single beat
ipifReadReq_reg or ipifWriteReq_reg; --we are talking about bursts..
ipifWriteReq_next <= cInactivated when ipifWriteReq_reg = cActivated and iIpif_cmdAck = cActivated else
cActivated when ipifWriteReq_reg = cInactivated and masterWrite_rise = cActivated else
ipifWriteReq_reg;
ipifReadReq_next <= cInactivated when ipifReadReq_reg = cActivated and iIpif_cmdAck = cActivated else
cActivated when ipifReadReq_reg = cInactivated and masterRead_rise = cActivated else
ipifReadReq_reg;
--assign address, byteenable and burst size
comb_addrZeroPad : process(iMasterAddress)
begin
for i in oIpif_addr'range loop
if i <= iMasterAddress'high then
oIpif_addr(i) <= iMasterAddress(i);
else
oIpif_addr(i) <= cInactivated; --zero padding
end if;
end loop;
end process;
oIpif_be <= "1111";
oIpif_length <= conv_std_logic_vector(conv_integer(iMasterBurstcount),
oIpif_length'length - 2) & "00"; -- dword x 4 = byte
--write/read link
wrd_proc : process(iClk, iRst)
begin
if iRst = cActivated then
writeTf_reg <= sIdle;
elsif rising_edge(iClk) then
writeTf_reg <= writeTf_next;
end if;
end process;
--generate fsm for write and read transfers
writeTf_next <= sSEof when writeTf_reg = sIdle and ipifWriteReq_next = cActivated and (iMasterBurstcount <= 1 or iMasterBurstcount'length = 1) else
sSof when writeTf_reg = sIdle and ipifWriteReq_next = cActivated and iMasterBurstcount'length > 1 else
sEof when writeTf_reg = sSof and inIpif_wrDstRdy = cnActivated and iMasterBurstcount = 2 and iMasterBurstcount'length > 1 else
sTf when writeTf_reg = sSof and inIpif_wrDstRdy = cnActivated and iMasterBurstcount'length > 1 else
sEof when writeTf_reg = sTf and iMasterBurstcounter <= 2 and inIpif_wrDstRdy = cnActivated and iMasterBurstcount'length > 1 else
sWaitForCmplt when (writeTf_reg = sEof or writeTf_reg = sSEof) and inIpif_wrDstRdy = cnActivated else
sIdle when writeTf_reg = sWaitForCmplt and iIpif_cmplt = cActivated else
writeTf_reg;
readTf <= sSEof when inIpif_rdSof = cnActivated and inIpif_rdEof = cnActivated else
sSof when inIpif_rdSof = cnActivated else
sEof when inIpif_rdEof = cnActivated else
sTf when inIpif_rdSrcRdy = cnActivated else
sIdle;
--set write qualifiers
onIpif_wrSof <= cnActivated when writeTf_reg = sSof or writeTf_reg = sSEof else
cnInactivated;
onIpif_wrEof <= cnActivated when writeTf_reg = sEof or writeTf_reg = sSEof else
cnInactivated;
onIpif_wrSrcRdy <= cnActivated when writeTf_reg /= sIdle and writeTf_reg /= sWaitForCmplt else
cnInactivated;
onIpif_wrSrcDsc <= cnInactivated; --no support
oIpif_wrRem <= (others => cInactivated); --no support
--set read qualifiers
onIpif_rdDstDsc <= cnInactivated; --no support
--connect ipif with generic master
oMasterWaitrequest <= not iMasterWrite when inIpif_wrDstRdy = cnActivated else
not iMasterRead when ipifReadReq_reg = cActivated and iIpif_cmdAck = cActivated else cActivated;
oMasterReaddatavalid <= not inIpif_rdSrcRdy;
oIpif_wrData <= iMasterWritedata;
oMasterReaddata <= iIpif_rdData;
end rtl;
| gpl-2.0 | 0379965537e7de783468793ad8cba652 | 0.587584 | 4.776551 | false | false | false | false |
ShepardSiegel/ocpi | libsrc/hdl/vhd/ocpi_wci_impl.vhd | 1 | 11,996 | -- per-property decoder - purely combinatorial
-- result is write_enable, offset-in-array, and aligned data output
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all;
entity property_decoder is
generic (
property : property_t; -- property type
decode_width : natural); -- decoder width in bits
port (
reset : in bool_t; -- active-low WCI worker reset
offset_in : in unsigned(decode_width-1 downto 0); -- offset in Bytes
top : in natural; -- High order bit position of datatype
access_in : in access_t; -- Enumerated WCI access type
data_in : in std_logic_vector(31 downto 0); -- WCI slave data
write_enable : out bool_t; -- active-high write pulse
read_enable : out bool_t; -- active-high read pulse
offset_out : out unsigned(decode_width-1 downto 0); --
index_out : out unsigned(decode_width-1 downto 0); --
data_out : out std_logic_vector(data_out_top(property) downto 0)); --
end entity property_decoder;
architecture rtl of property_decoder is
subtype decode_t is unsigned (decode_width-1 downto 0);
signal my_offset : decode_t;
signal byte_offset : byte_offset_t;
function element_bytes(property : property_t) return decode_t is
variable bytes : natural;
begin
if property.string_length /= 0 then
bytes := ((property.string_length + 4)/4) * 4;
else
bytes := (property.data_width+7)/8;
end if;
return to_unsigned(bytes, decode_t'length);
end element_bytes;
-- I tried to use offset_in directly, not an argument, and isim generated a wierd warning...
impure function my_decode (input: unsigned) return boolean is
begin
return not reset and
input >= property.offset and
(my_offset = 0 or
(property.data_width > 32 and my_offset = 4) or
(property.nitems > 1 and my_offset > 0 and my_offset <= property.bytes_1));
end my_decode;
begin
byte_offset <= offset_in(1 downto 0);
my_offset <= offset_in - property.offset;
write_enable <= to_bool(access_in = write_e and property.writable and my_decode(offset_in));
read_enable <= to_bool(access_in = read_e and property.readable and my_decode(offset_in));
offset_out <= (others => '0') when property.nitems <= 1 else my_offset;
data_out <=
data_in(data_out_top(property) downto 0) when property.nitems <= 1 else
data_in(31 downto 0) when property.data_width >= 32 else
resize(data_in(top downto 0), data_out'length) when byte_offset = 0 else
resize(data_in(15 downto 8), data_out'length) when byte_offset = 1 else
resize(data_in(top downto 16), data_out'length) when byte_offset = 2 else
resize(data_in(31 downto 24), data_out'length);
index_out <=
to_unsigned(0,index_out'length) when property.nitems <= 1 else
my_offset/element_bytes(property); -- this won't be used for strings so no
-- non-power of 2 math needed.
end rtl;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all;
entity decoder is
generic (
worker : worker_t;
properties : properties_t);
port (
ocp_in : in in_t;
done : in bool_t := btrue;
resp : out ocp.SResp_t;
write_enables : out bool_array_t(properties'range);
read_enables : out bool_array_t(properties'range);
offsets : out offset_a_t(properties'range);
indices : out offset_a_t(properties'range);
hi32 : out bool_t;
nbytes_1 : out byte_offset_t;
data_outputs : out data_a_t(properties'range);
control_op : out control_op_t;
state : out state_t;
is_operating : out bool_t; -- just a convenience for state = operating_e
abort_control_op : out bool_t;
is_big_endian : out bool_t -- for runtime dynamic endian
);
end entity;
architecture rtl of decoder is
signal beoffset : unsigned(1 downto 0);
signal offset : unsigned(worker.decode_width-1 downto 0);
signal my_access : access_t;
signal control_op_in : control_op_t;
signal my_write_enables, my_read_enables : bool_array_t(properties'range);
signal my_control_op : control_op_t;
type my_offset_a_t is array(properties'range) of unsigned (worker.decode_width -1 downto 0);
signal my_offsets : my_offset_a_t;
signal my_state : state_t;
-- convert byte enables to low order address bytes
function be2offset(input: in_t) return byte_offset_t is begin
case input.MByteEn is
when b"0010" => return b"01";
when b"0100" | b"1100" => return b"10";
when b"1000" => return b"11";
when others => return b"00";
end case;
end be2offset;
function top_bit(input: in_t) return natural is begin
case input.MByteEn is
when b"0001" => return 7;
when b"0010" | b"0011" => return 15;
when b"0100" => return 23;
when b"1000" | b"1100" | b"1111" => return 31;
when others => return 31;
end case;
end top_bit;
function num_bytes_1(input : in_t) return byte_offset_t is begin
case input.MByteEn is
when b"0001" | b"0010" | b"0100" | b"1000" => return b"00";
when b"1100" | b"0011" => return b"01";
when b"1111" => return b"11";
when others => return b"11";
end case;
end num_bytes_1;
begin
-- combinatorial signals used in various places
state <= my_state;
nbytes_1 <= num_bytes_1(ocp_in);
is_big_endian <= to_bool(ocp_in.MFlag(1) = '1');
abort_control_op <= to_bool(ocp_in.MFlag(0) = '1');
beoffset <= be2offset(ocp_in);
offset <= unsigned(ocp_in.MAddr(worker.decode_width-1 downto 2)) & beoffset;
my_access <= decode_access(ocp_in);
control_op_in <= ocpi.wci.to_control_op(ocp_in.MAddr(4 downto 2));
hi32 <= to_bool(ocp_in.MAddr(2) = '1');
-- generate property instances for each property
-- they are all combinatorial by design
gen: for i in 0 to properties'right generate -- properties'left to 0 generate
prop: entity ocpi.property_decoder
generic map (properties(i), worker.decode_width)
port map(reset => to_bool(ocp_in.MReset_n),
offset_in => offset,
top => top_bit(ocp_in),
access_in => my_access,
data_in => ocp_in.MData,
write_enable => my_write_enables(i),
read_enable => my_read_enables(i),
offset_out => my_offsets(i),
index_out => indices(i)(worker.decode_width-1 downto 0),
data_out => data_outputs(i)(data_out_top(properties(i)) downto 0));
offsets(i) <= resize(my_offsets(i),offsets(i)'length); -- resize to 32 bits for VHDL language reasons
end generate gen;
write_enables <= my_write_enables;
read_enables <= my_read_enables;
control_op <= my_control_op;
-- manage state during control ops and manage the WCI/OCP SResp.
-- remember that since we have no SCmdAccept signal, any command is only
-- valid for one clock, but is finished when we assert SResp non-NULL
reg: process(ocp_in.Clk) is
-- a mask of allowable operations in the current state
variable allowed_ops : control_op_mask_t;
variable next_op : control_op_t;
-- FIXME check that this synthesizes properly - may have to revert to logic...
function any_true(bools : bool_array_t) return boolean is
variable result: boolean := false;
begin
for i in bools'range loop
if its(bools(i)) then result := true; end if;
end loop;
return result;
end any_true;
begin
if rising_edge(ocp_in.Clk) then
-- default value of the SResp output, which is a register
resp <= ocp.SResp_NULL;
if ocp_in.MReset_n = '0' then
is_operating <= bfalse;
my_control_op <= NO_OP_e;
if worker.allowed_ops(control_op_t'pos(initialize_e)) = '1' then
my_state <= exists_e;
else
my_state <= initialized_e;
end if;
allowed_ops := next_ops(state_t'pos(my_state));
elsif my_control_op /= NO_OP_e then
if its(done) then -- FIXME done should also control config i/o
-- finish the control by setting the state
is_operating <= bfalse;
case my_control_op is
when INITIALIZE_e =>
my_state <= initialized_e;
when START_e =>
my_state <= operating_e;
is_operating <= btrue;
when STOP_e =>
my_state <= suspended_e;
when RELEASE_e =>
my_state <= unusable_e;
when others => null;
end case;
end if;
else
case my_access is
when Error_e =>
resp <= ocp.SResp_ERR; -- we don't support read yet
when Read_e =>
if any_true(my_read_enables) then
resp <= ocp.SResp_DVA; -- assume there is no delay for property capture
else
resp <= ocp.SResp_ERR; -- a write that no property accepted...
end if;
when Write_e =>
if any_true(my_write_enables) then
resp <= ocp.SResp_DVA; -- assume there is no delay for property capture
else
resp <= ocp.SResp_ERR; -- a write that no property accepted...
end if;
when Control_e =>
if my_control_op /= no_op_e or -- prevented by control plane
worker.allowed_ops(control_op_t'pos(control_op_in)) = '0' or -- prevented by software
next_ops(state_t'pos(my_state))(control_op_t'pos(control_op_in)) = '0'
then -- prevented by software
-- This would only happen if the control plane or software is broken
resp <= ocp.SResp_ERR;
else
my_control_op <= control_op_in;
end if;
when None_e => null;
end case;
end if;
end if;
end process;
end rtl;
--
-- The readback multiplexer for those properties that have readback
--
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all; use ocpi.wci.all;
entity readback is
generic (properties : properties_t);
port (
read_enables : in bool_array_t(properties'range);
data_inputs : in data_a_t(properties'range);
data_output : out std_logic_vector(31 downto 0)
);
end entity readback;
architecture rtl of readback is
subtype index_t is natural range properties'range;
function first_true(bools : bool_array_t(properties'range)) return index_t is
begin
for i in 0 to properties'right loop
if its(bools(i)) then return i; end if;
end loop;
return 0;
end first_true;
begin
data_output <= data_inputs(first_true(read_enables));
end rtl;
| lgpl-3.0 | 6e750469d7b944513c58acc0494c8330 | 0.562437 | 3.747579 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/common/fifo/src/fifoWrite-rtl-ea.vhd | 2 | 5,782 | -------------------------------------------------------------------------------
--! @file fifoWrite-rtl-ea.vhd
--
--! @brief FIFO write controller
--
--! @details This is a FIFO write controller.
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
--! use global library
use work.global.all;
entity fifoWrite is
generic (
gAddrWidth : natural := 4
);
port (
iClk : in std_logic;
iRst : in std_logic;
iWrite : in std_logic;
iRdPointer : in std_logic_vector(gAddrWidth downto 0);
oFull : out std_logic;
oEmpty : out std_logic;
oPointer : out std_logic_vector(gAddrWidth downto 0);
oAddress : out std_logic_vector(gAddrWidth-1 downto 0);
oUsedWord : out std_logic_vector(gAddrWidth-1 downto 0)
);
end fifoWrite;
architecture rtl of fifoWrite is
signal w_ptr_reg : std_logic_vector(gAddrWidth downto 0);
signal w_ptr_next : std_logic_vector(gAddrWidth downto 0);
signal gray1 : std_logic_vector(gAddrWidth downto 0);
signal bin : std_logic_vector(gAddrWidth downto 0);
signal bin1 : std_logic_vector(gAddrWidth downto 0);
signal waddr_all : std_logic_vector(gAddrWidth-1 downto 0);
signal waddr_msb : std_logic;
signal raddr_msb : std_logic;
signal full_flag : std_logic;
signal empty_flag : std_logic;
signal w_elements_wr : std_logic_vector(gAddrWidth downto 0);
signal w_elements_rd : std_logic_vector(gAddrWidth downto 0);
signal w_elements_diff : std_logic_vector(gAddrWidth downto 0);
signal w_elements_reg : std_logic_vector(gAddrWidth-1 downto 0);
signal w_elements_next : std_logic_vector(gAddrWidth-1 downto 0);
begin
--! Clock process for registers.
regProc : process(iClk, iRst)
begin
if iRst = cActivated then
w_ptr_reg <= (others => cInactivated);
w_elements_reg <= (others => cInactivated);
elsif rising_edge(iClk) then
w_ptr_reg <= w_ptr_next;
w_elements_reg <= w_elements_next;
end if;
end process;
-- (gAddrWidth+1)-bit Gray counter
bin <= w_ptr_reg xor (cInactivated & bin(gAddrWidth downto 1));
bin1 <= std_logic_vector(unsigned(bin) + 1);
gray1 <= bin1 xor (cInactivated & bin1(gAddrWidth downto 1));
-- update write pointer
w_ptr_next <= gray1 when iWrite = cActivated and full_flag = cInactivated else
w_ptr_reg;
-- gAddrWidth-bit Gray counter
waddr_msb <= w_ptr_reg(gAddrWidth) xor w_ptr_reg(gAddrWidth-1);
waddr_all <= waddr_msb & w_ptr_reg(gAddrWidth-2 downto 0);
raddr_msb <= iRdPointer(gAddrWidth) xor iRdPointer(gAddrWidth-1);
-- check for FIFO write empty
empty_flag <= cActivated when iRdPointer(gAddrWidth) = w_ptr_reg(gAddrWidth) and
iRdPointer(gAddrWidth-2 downto 0) = w_ptr_reg(gAddrWidth-2 downto 0) and
raddr_msb = waddr_msb else
cInactivated;
-- check for FIFO write full
full_flag <= cActivated when iRdPointer(gAddrWidth) /= w_ptr_reg(gAddrWidth) and
iRdPointer(gAddrWidth-2 downto 0) = w_ptr_reg(gAddrWidth-2 downto 0) and
raddr_msb = waddr_msb else
cInactivated;
-- convert gray value to bin and obtain difference
w_elements_wr <= bin;
w_elements_rd <= iRdPointer xor (cInactivated & w_elements_rd(gAddrWidth downto 1));
w_elements_diff <= std_logic_vector(unsigned(w_elements_wr) - unsigned(w_elements_rd));
w_elements_next <= w_elements_diff(w_elements_next'range);
-- output
oAddress <= waddr_all;
oPointer <= w_ptr_reg;
oUsedWord <= w_elements_reg;
oEmpty <= empty_flag;
oFull <= full_flag;
end rtl;
| gpl-2.0 | f3482ee1c81532cf7df644b408ebfa94 | 0.618471 | 4.144803 | false | false | false | false |
paulino/digilentinc-peripherals | bench/port_spi_dib_tb.vhd | 1 | 3,872 | -------------------------------------------------------------------------------
-- Copyright 2014 Paulino Ruiz de Clavijo Vázquez <[email protected]>
-- This file is part of the Digilentinc-peripherals project.
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- You can get more info at http://www.dte.us.es/id2
--
--*------------------------------- End auto header, don't touch this line --*--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use work.digilent_peripherals_pk.all;
ENTITY port_spi_basys2_tb IS
END port_spi_basys2_tb;
ARCHITECTURE behavior OF port_spi_basys2_tb IS
-- Component Declaration for the Unit Under Test (UUT)
-- Inputs
signal clk : std_logic := '0';
signal enable : std_logic := '0';
signal data_in : std_logic_vector(7 downto 0) := (others => '0');
signal cfst_data : std_logic := '0';
signal rw : std_logic;
signal miso : std_logic := '0';
--Outputs
signal data_out : std_logic_vector(7 downto 0);
signal mosi : std_logic;
signal sclk : std_logic;
signal ss : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: port_spi_basys2 PORT MAP (
clk => clk,
enable => enable,
data_in => data_in,
data_out => data_out,
cfst_data => cfst_data,
rw => rw,
miso => miso,
mosi => mosi,
sclk => sclk,
ss => ss
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
data_in <= "00000000"; -- set clock to ext_clk/2
enable <= '0';
cfst_data <= '0';
rw <= '0';
miso <= '0';
enable <= '0';
wait for clk_period*10;
-- writing config
wait until rising_edge(clk);
data_in <= "10000001"; -- set clock to ext_clk/2, rise ss
enable <= '0';
miso <= '0';
enable <= '1';
rw <= '1';
cfst_data <= '0';
wait until rising_edge(clk);
enable <= '0';
wait until rising_edge(clk);
wait for clk_period*8;
-- Try fall ss
wait until rising_edge(clk);
data_in(7) <= '0';
enable <= '1';
rw <= '1';
cfst_data <= '0';
wait until rising_edge(clk);
enable <= '0';
wait for clk_period*10;
-- Sendind data
wait until rising_edge(clk);
data_in <= "10011001";
enable <= '1'; --
cfst_data <= '1'; -- write data
rw <= '1';
wait until rising_edge(clk);
enable <= '0';
rw <= '0'; -- Data written
wait until rising_edge(clk);
miso <= '1';
wait until rising_edge(clk);
enable <='0';
wait until rising_edge(clk);
miso <= '0';
wait until rising_edge(clk);
miso <= '1';
wait until rising_edge(clk);
miso <= '1';
wait for clk_period*50; -- reading data in
wait until rising_edge(clk);
enable <= '1'; --
cfst_data <= '1'; -- data access
rw <= '0';
wait until rising_edge(clk);
enable <= '0';
rw <= '0'; -- readed
wait;
end process;
END;
| apache-2.0 | df5d36fcf382968d475df01209489305 | 0.538621 | 3.354419 | false | false | false | false |
dangpzanco/sistemas-digitais | add3.vhd | 1 | 532 | library ieee;
use ieee.std_logic_1164.all;
entity add3 is
port ( Num : in std_logic_vector(3 downto 0);
Sum : out std_logic_vector(3 downto 0)
);
end add3;
architecture sum_estru of add3 is
begin
Sum <= Num when Num = "0000" else
Num when Num = "0001" else
Num when Num = "0010" else
Num when Num = "0011" else
Num when Num = "0100" else
"1000" when Num = "0101" else
"1001" when Num = "0110" else
"1010" when Num = "0111" else
"1011" when Num = "1000" else
"1100";
end sum_estru; | mit | 6752980e44ae95d07de2498fd27f7960 | 0.616541 | 2.770833 | false | false | false | false |
hoglet67/AtomGodilVideo | src/mouse/ps2interface.vhd | 1 | 33,237 | ------------------------------------------------------------------------
-- ps2interface.vhd
------------------------------------------------------------------------
-- Author : Ulrich Zoltn
-- Copyright 2006 Digilent, Inc.
------------------------------------------------------------------------
-- Software version : Xilinx ISE 7.1.04i
-- WebPack
-- Device : 3s200ft256-4
------------------------------------------------------------------------
-- This file contains the implementation of a generic bidirectional
-- ps/2 interface.
------------------------------------------------------------------------
-- Behavioral description
------------------------------------------------------------------------
-- Please read the following article on the web for understanding how
-- the ps/2 protocol works.
-- http://www.computer-engineering.org/ps2protocol/
-- This module implements a generic bidirectional ps/2 interface. It can
-- be used with any ps/2 compatible device. It offers its clients a
-- convenient way to exchange data with the device. The interface
-- transparently wraps the byte to be sent into a ps/2 frame, generates
-- parity for byte and sends the frame one bit at a time to the device.
-- Similarly, when receiving data from the ps2 device, the interface
-- receives the frame, checks for parity, and extract the usefull data
-- and forwards it to the client. If an error occurs during receiving
-- or sending a byte, the client is informed by settings the err output
-- line high. This way, the client can resend the data or can issue
-- a resend command to the device.
-- The physical ps/2 interface uses 4 lines
-- For the 6-pin connector pins are assigned as follows:
-- 1 - Data
-- 2 - Not Implemented
-- 3 - Ground
-- 4 - Vcc (+5V)
-- 5 - Clock
-- 6 - Not Implemented
-- The clock line carries the device generated clock which has a
-- frequency in range 10 - 16.7 kHz (30 to 50us). When line is idle
-- it is placed in high impedance. The clock is only generated when
-- device is sending or receiving data.
-- The Data and Clock lines are both open-collector with pullup
-- resistors to Vcc. An "open-collector" interface has two possible
-- states: low('0') or high impedance('Z').
-- When device wants to send a byte, it pulls the clock line low and the
-- host(i.e. this interfaces) recognizes that the device is sending data
-- When the host wants to send data, it maeks a request to send. This
-- is done by holding the clock line low for at least 100us, then with
-- the clock line low, the data line is brought low. Next the clock line
-- is released (placed in high impedance). The devices begins generating
-- clock signal on clock line.
-- When receiving data, bits are read from the data line (ps2_data) on
-- the falling edge of the clock (ps2_clk). When sending data, the
-- device reads the bits from the data line on the rising edge of the
-- clock.
-- A frame for sending a byte is comprised of 11 bits as shown bellow:
-- bits 10 9 8 7 6 5 4 3 2 1 0
-- -------------------------------------------------------------
-- | STOP| PAR | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | START |
-- -------------------------------------------------------------
-- STOP - stop bit, always '1'
-- PAR - parity bit, odd parity for the 8 data bits.
-- - select in such way that the number of bits of '1' in the data
-- - bits together with parity bit is odd.
-- D0-7 - data bits.
-- START - start bit, always '0'
--
-- Frame is sent bit by bit starting with the least significant bit
-- (starting bit) and is received the same way. This is done, when
-- receiving, by shifting the frame register to the left when a bit
-- is available and placing the bit on data line on the most significant
-- bit. This way the first bit sent will reach the least significant bit
-- of the frame when all the bits have been received. When sending data
-- the least significant bit of the frame is placed on the data line
-- and the frame is shifted to the right when another bit needs to be
-- sent. During the request to send, when releasing the clock line,
-- the device reads the data line and interprets the data on it as the
-- first bit of the frame. Data line is low at that time, at this is the
-- way the start bit('0') is sent. Because of this, when sending, only
-- 10 shifts of the frame will be made.
-- While the interface is sending or receiving data, the busy output
-- signal goes high. When interface is idle, busy is low.
-- After sending all the bits in the frame, the device must acknowledge
-- the data sent. This is done by the host releasing and data line
-- (clock line is already released) after the last bit is sent. The
-- devices brings the data line and the clock line low, in this order,
-- to acknowledge the data. If data line is high when clock line goes
-- low after last bit, the device did not acknowledge the data and
-- err output is set.
-- A FSM is used to manage the transitions the set all the command
-- signals. States that begin with "rx_" are used to receive data
-- from device and states begining with "tx_" are used to send data
-- to the device.
-- For the parity bit, a ROM holds the parity bit for all possible
-- data (256 possible values, since 8 bits of data). The ROM has
-- dimensions 256x1bit. For obtaining the parity bit of a value,
-- the bit at the data value address is read. Ex: to find the parity
-- bit of 174, the bit at address 174 is read.
-- For generating the necessary delay, counters are used. For example,
-- to generate the 100us delay a 14 bit counter is used that has the
-- upper limit for counting 10000. The interface is designed to run
-- at 100MHz. Thus, 10000x10ns = 100us.
-----------------------------------------------------------------------
-- If using the interface at different frequency than 100MHz, adjusting
-- the delay counters is necessary!!!
-----------------------------------------------------------------------
-- Clock line(ps2_clk) and data line(ps2_data) are passed through a
-- debouncer for the transitions of the clock and data to be clean.
-- Also, ps2_clk_s and ps2_data_s hold the debounced and synchronized
-- value of the clock and data line to the system clock(clk).
------------------------------------------------------------------------
-- Port definitions
------------------------------------------------------------------------
-- ps2_clk - inout pin, clock line of the ps/2 interface
-- ps2_data - inout pin, clock line of the ps/2 interface
-- clk - input pin, system clock signal
-- rst - input pin, system reset signal
-- tx_data - input pin, 8 bits, from client
-- - data to be sent to the device
-- write - input pin, from client
-- - should be active for one clock period when then
-- - client wants to send data to the device and
-- - data to be sent is valid on tx_data
-- rx_data - output pin, 8 bits, to client
-- - data received from device
-- read - output pin, to client
-- - active for one clock period when new data is
-- - available from device
-- busy - output pin, to client
-- - active while sending or receiving data.
-- err - output pin, to client
-- - active for one clock period when an error occurred
-- - during sending or receiving.
------------------------------------------------------------------------
-- Revision History:
-- 09/18/2006(UlrichZ): created
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- simulation library
--library UNISIM;
--use UNISIM.VComponents.all;
-- the ps2interface entity declaration
-- read above for behavioral description and port definitions.
entity ps2interface is
generic (
MainClockSpeed : integer
);
port(
ps2_clk : inout std_logic;
ps2_data : inout std_logic;
clk : in std_logic;
rst : in std_logic;
tx_data : in std_logic_vector(7 downto 0);
write : in std_logic;
rx_data : out std_logic_vector(7 downto 0);
read : out std_logic;
busy : out std_logic;
err : out std_logic
);
-- forces the extraction of distributed ram for
-- the parityrom memory.
-- please remove if block ram is preffered.
attribute rom_extract : string;
attribute rom_extract of ps2interface: entity is "yes";
attribute rom_style : string;
attribute rom_style of ps2interface: entity is "distributed";
end ps2interface;
architecture Behavioral of ps2interface is
------------------------------------------------------------------------
-- CONSTANTS
------------------------------------------------------------------------
-- Values are valid for a 49.152MHz clk. Please adjust for other
-- frequencies if necessary!
-- upper limit for 100us delay counter.
-- 4915 * 20.34ns = 100us
--constant DELAY_100US : std_logic_vector(13 downto 0):= "01001100110011";
constant DELAY_100US : std_logic_vector(13 downto 0):= std_logic_vector(to_unsigned(MainClockSpeed * 100 / 1000000, 14));
-- upper limit for 20us delay counter.
-- 983 * 20.34ns = 20us
-- constant DELAY_20US : std_logic_vector(10 downto 0) := "01111010111";
constant DELAY_20US : std_logic_vector(10 downto 0) := std_logic_vector(to_unsigned(MainClockSpeed * 20 / 1000000, 11));
-- upper limit for 63clk delay counter.
constant DELAY_63CLK : std_logic_vector(5 downto 0) := "111111";
-- 63 clock periods
-- delay from debouncing ps2_clk and ps2_data signals
constant DEBOUNCE_DELAY : std_logic_vector(3 downto 0) := "1111";
-- number of bits in a frame
constant NUMBITS: std_logic_vector(3 downto 0) := "1011"; -- 11
-- parity bit position in frame
constant PARITY_BIT: positive := 9;
-- (odd) parity bit ROM
-- Used instead of logic because this way speed is far greater
-- 256x1bit rom
-- If the odd parity bit for a 8 bits number, x, is needed
-- the bit at address x is the parity bit.
type ROM is array(0 to 255) of std_logic;
constant parityrom : ROM := (
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1'
);
------------------------------------------------------------------------
-- SIGNALS
------------------------------------------------------------------------
-- 14 bits counter
-- max value DELAY_100US
-- used to wait 100us
signal delay_100us_count: std_logic_vector(13 downto 0) :=
(others => '0');
-- 11 bits counter
-- max value DELAY_20US
-- used to wait 20us
signal delay_20us_count: std_logic_vector(10 downto 0) :=
(others => '0');
-- 11 bits counter
-- max value DELAY_63CLK
-- used to wait 63 clock periods
signal delay_63clk_count: std_logic_vector(5 downto 0) :=
(others => '0');
-- done signal for the couters above
-- when a counter reaches max value,the corresponding done signal is set
signal delay_100us_done, delay_20us_done, delay_63clk_done: std_logic;
-- enable signal for 100us delay counter
signal delay_100us_counter_enable: std_logic := '0';
-- enable signal for 20us delay counter
signal delay_20us_counter_enable : std_logic := '0';
-- enable signal for 63clk delay counter
signal delay_63clk_counter_enable: std_logic := '0';
-- synchronzed input for ps2_clk and ps2_data
signal ps2_clk_s,ps2_data_s: std_logic := '1';
-- control the output of ps2_clk and ps2_data
-- if 1 then corresponding signal (ps2_clk or ps2_data) is
-- put in high impedance ('Z').
signal ps2_clk_h,ps2_data_h: std_logic := '1';
-- states of the FSM for controlling the communcation with the device
-- states that begin with "rx_" are used when receiving data
-- states that begin with "tx_" are used when transmiting data
type fsm_state is
(
idle,rx_clk_h,rx_clk_l,rx_down_edge,rx_error_parity,rx_data_ready,
tx_force_clk_l,tx_bring_data_down,tx_release_clk,
tx_first_wait_down_edge,tx_clk_l,tx_wait_up_edge,tx_clk_h,
tx_wait_up_edge_before_ack,tx_wait_ack,tx_received_ack,
tx_error_no_ack
);
-- the signal that holds the current state of the FSM
-- implicitly state is idle.
signal state: fsm_state := idle;
-- register that holds the frame received or the one to be sent.
-- Its contents are shifted in from the bus one bit at a time
-- from left to right when receiving data and are shifted on the
-- bus (ps2_data) one bit at a time to the right when sending data
signal frame: std_logic_vector(10 downto 0) := (others => '0');
-- how many bits have been sent or received.
signal bit_count: std_logic_vector(3 downto 0) := (others => '0');
-- when active the bit counter is reset.
signal reset_bit_count: std_logic := '0';
-- when active the contents of the frame is shifted to the right
-- and the most significant bit of frame is loaded with ps2_data.
signal shift_frame: std_logic := '0';
-- parity of the byte that was received from the device.
-- must match the parity bit received, else error occurred.
signal rx_parity: std_logic := '0';
-- parity bit that is sent with the frame, representing the
-- odd parity of the byte currently being sent
signal tx_parity: std_logic := '0';
-- when active, frame is loaded with the start bit, data on
-- tx_data, parity bit (tx_parity) and stop bit
-- this frame will be sent to the device.
signal load_tx_data: std_logic := '0';
-- when active bits 8 downto 1 from frame are loaded into
-- rx_data register. This is the byte received from the device.
signal load_rx_data: std_logic := '0';
-- intermediary signals used to debounce the inputs ps2_clk and ps2_data
signal ps2_clk_clean,ps2_data_clean: std_logic := '1';
-- debounce counter for the ps2_clk input and the ps2_data input.
signal clk_count,data_count: std_logic_vector(3 downto 0);
-- last value on ps2_clk and ps2_data.
signal clk_inter,data_inter: std_logic := '1';
begin
---------------------------------------------------------------------
-- FLAGS and PS2 CLOCK AND DATA LINES
---------------------------------------------------------------------
-- clean ps2_clk signal (debounce)
-- note that this introduces a delay in ps2_clk of
-- DEBOUNCE_DELAY clocks
process(clk)
begin
if(rising_edge(clk)) then
-- if the current bit on ps2_clk is different
-- from the last value, then reset counter
-- and retain value
if(ps2_clk /= clk_inter) then
clk_inter <= ps2_clk;
clk_count <= (others => '0');
-- if counter reached upper limit, then
-- the signal is clean
elsif(clk_count = DEBOUNCE_DELAY) then
ps2_clk_clean <= clk_inter;
-- ps2_clk did not change, but counter did not
-- reach limit. Increment counter
else
clk_count <= clk_count + 1;
end if;
end if;
end process;
-- clean ps2_data signal (debounce)
-- note that this introduces a delay in ps2_data of
-- DEBOUNCE_DELAY clocks
process(clk)
begin
if(rising_edge(clk)) then
-- if the current bit on ps2_data is different
-- from the last value, then reset counter
-- and retain value
if(ps2_data /= data_inter) then
data_inter <= ps2_data;
data_count <= (others => '0');
-- if counter reached upper limit, then
-- the signal is clean
elsif(data_count = DEBOUNCE_DELAY) then
ps2_data_clean <= data_inter;
-- ps2_data did not change, but counter did not
-- reach limit. Increment counter
else
data_count <= data_count + 1;
end if;
end if;
end process;
-- Synchronize ps2 entries
ps2_clk_s <= ps2_clk_clean when rising_edge(clk);
ps2_data_s <= ps2_data_clean when rising_edge(clk);
-- Assign parity from frame bits 8 downto 1, this is the parity
-- that should be received inside the frame on PARITY_BIT position
rx_parity <= parityrom(conv_integer(frame(8 downto 1)))
when rising_edge(clk);
-- The parity for the data to be sent
tx_parity <= parityrom(conv_integer(tx_data)) when rising_edge(clk);
-- Force ps2_clk to '0' if ps2_clk_h = '0', else release the line
-- ('Z' = +5Vcc because of pull-ups)
ps2_clk <= 'Z' when ps2_clk_h = '1' else '0';
-- Force ps2_data to '0' if ps2_data_h = '0', else release the line
-- ('Z' = +5Vcc because of pull-ups)
ps2_data <= 'Z' when ps2_data_h = '1' else '0';
-- Control busy flag. Interface is not busy while in idle state.
busy <= '0' when state = idle else '1';
-- reset the bit counter when in idle state.
reset_bit_count <= '1' when state = idle else '0';
-- Control shifting of the frame
-- When receiving from device, data is read
-- on the falling edge of ps2_clk
-- When sending to device, data is read by device
-- on the rising edge of ps2_clk
shift_frame <= '1' when state = rx_down_edge or
state = tx_clk_l else
'0';
---------------------------------------------------------------------
-- FINITE STATE MACHINE
---------------------------------------------------------------------
-- For the current state establish next state
-- and give necessary commands
manage_fsm: process(clk,rst,state,ps2_clk_s,ps2_data_s,write,tx_data,
bit_count,rx_parity,frame,delay_100us_done,
delay_20us_done,delay_63clk_done)
begin
-- if reset occurs, go to idle state.
if(rst = '1') then
state <= idle;
elsif(rising_edge(clk)) then
-- default values for these signals
-- ensures signals are reset to default value
-- when coditions for their activation are no
-- longer applied (transition to other state,
-- where signal should not be active)
-- Idle value for ps2_clk and ps2_data is 'Z'
ps2_clk_h <= '1';
ps2_data_h <= '1';
load_tx_data <= '0';
load_rx_data <= '0';
read <= '0';
err <= '0';
case state is
-- wait for the device to begin a transmission
-- by pulling the clock line low and go to state
-- rx_down_edge or, if write is high, the
-- client of this interface wants to send a byte
-- to the device and a transition is made to state
-- tx_force_clk_l
when idle =>
if(ps2_clk_s = '0') then
state <= rx_down_edge;
elsif(write = '1') then
state <= tx_force_clk_l;
else
state <= idle;
end if;
-- ps2_clk is high, check if all the bits have been read
-- if, last bit read, check parity, and if parity ok
-- load received data into rx_data.
-- else if more bits left, then wait for the ps2_clk to
-- go low
when rx_clk_h =>
if(bit_count = NUMBITS) then
if(not (rx_parity = frame(PARITY_BIT))) then
state <= rx_error_parity;
else
load_rx_data <= '1';
state <= rx_data_ready;
end if;
elsif(ps2_clk_s = '0') then
state <= rx_down_edge;
else
state <= rx_clk_h;
end if;
-- data must be read into frame in this state
-- the ps2_clk just transitioned from high to low
when rx_down_edge =>
state <= rx_clk_l;
-- ps2_clk line is low, wait for it to go high
when rx_clk_l =>
if(ps2_clk_s = '1') then
state <= rx_clk_h;
else
state <= rx_clk_l;
end if;
-- parity bit received is invalid
-- signal error and go back to idle.
when rx_error_parity =>
err <= '1';
state <= idle;
-- parity bit received was good
-- set read signal for the client to know
-- a new byte was received and is available on rx_data
when rx_data_ready =>
read <= '1';
state <= idle;
-- the client wishes to transmit a byte to the device
-- this is done by holding ps2_clk down for at least 100us
-- bringing down ps2_data, wait 20us and then releasing
-- the ps2_clk.
-- This constitutes a request to send command.
-- In this state, the ps2_clk line is held down and
-- the counter for waiting 100us is eanbled.
-- when the counter reached upper limit, transition
-- to tx_bring_data_down
when tx_force_clk_l =>
load_tx_data <= '1';
ps2_clk_h <= '0';
if(delay_100us_done = '1') then
state <= tx_bring_data_down;
else
state <= tx_force_clk_l;
end if;
-- with the ps2_clk line low bring ps2_data low
-- wait for 20us and then go to tx_release_clk
when tx_bring_data_down =>
-- keep clock line low
ps2_clk_h <= '0';
-- set data line low
-- when clock is released in the next state
-- the device will read bit 0 on data line
-- and this bit represents the start bit.
ps2_data_h <= '0'; -- start bit = '0'
if(delay_20us_done = '1') then
state <= tx_release_clk;
else
state <= tx_bring_data_down;
end if;
-- release the ps2_clk line
-- keep holding data line low
when tx_release_clk =>
ps2_clk_h <= '1';
-- must maintain data low,
-- otherwise will be released by default value
ps2_data_h <= '0';
state <= tx_first_wait_down_edge;
-- state is necessary because the clock signal
-- is not released instantaneously and, because of debounce,
-- delay is even greater.
-- Wait 63 clock periods for the clock line to release
-- then if clock is low then go to tx_clk_l
-- else wait until ps2_clk goes low.
when tx_first_wait_down_edge =>
ps2_data_h <= '0';
if(delay_63clk_done = '1') then
if(ps2_clk_s = '0') then
state <= tx_clk_l;
else
state <= tx_first_wait_down_edge;
end if;
else
state <= tx_first_wait_down_edge;
end if;
-- place the least significant bit from frame
-- on the data line
-- During this state the frame is shifted one
-- bit to the right
when tx_clk_l =>
ps2_data_h <= frame(0);
state <= tx_wait_up_edge;
-- wait for the clock to go high
-- this is the edge on which the device reads the data
-- on ps2_data.
-- keep holding ps2_data on frame(0) because else
-- will be released by default value.
-- Check if sent the last bit and if so, release data line
-- and go to state that wait for acknowledge
when tx_wait_up_edge =>
ps2_data_h <= frame(0);
-- NUMBITS - 1 because first (start bit = 0) bit was read
-- when the clock line was released in the request to
-- send command (see tx_bring_data_down state).
if(bit_count = NUMBITS-1) then
ps2_data_h <= '1';
state <= tx_wait_up_edge_before_ack;
-- if more bits to send, wait for the up edge
-- of ps2_clk
elsif(ps2_clk_s = '1') then
state <= tx_clk_h;
else
state <= tx_wait_up_edge;
end if;
-- ps2_clk is released, wait for down edge
-- and go to tx_clk_l when arrived
when tx_clk_h =>
ps2_data_h <= frame(0);
if(ps2_clk_s = '0') then
state <= tx_clk_l;
else
state <= tx_clk_h;
end if;
-- release ps2_data and wait for rising edge of ps2_clk
-- once this occurs, transition to tx_wait_ack
when tx_wait_up_edge_before_ack =>
ps2_data_h <= '1';
if(ps2_clk_s = '1') then
state <= tx_wait_ack;
else
state <= tx_wait_up_edge_before_ack;
end if;
-- wait for the falling edge of the clock line
-- if data line is low when this occurs, the
-- ack is received
-- else if data line is high, the device did not
-- acknowledge the transimission
when tx_wait_ack =>
if(ps2_clk_s = '0') then
if(ps2_data_s = '0') then
-- acknowledge received
state <= tx_received_ack;
else
-- acknowledge not received
state <= tx_error_no_ack;
end if;
else
state <= tx_wait_ack;
end if;
-- wait for ps2_clk to be released together with ps2_data
-- (bus to be idle) and go back to idle state
when tx_received_ack =>
if(ps2_clk_s = '1' and ps2_data_s = '1') then
state <= idle;
else
state <= tx_received_ack;
end if;
-- wait for ps2_clk to be released together with ps2_data
-- (bus to be idle) and go back to idle state
-- signal error for not receiving ack
when tx_error_no_ack =>
if(ps2_clk_s = '1' and ps2_data_s = '1') then
err <= '1';
state <= idle;
else
state <= tx_error_no_ack;
end if;
-- if invalid transition occurred, signal error and
-- go back to idle state
when others =>
err <= '1';
state <= idle;
end case;
end if;
end process manage_fsm;
---------------------------------------------------------------------
-- DELAY COUNTERS
---------------------------------------------------------------------
-- Enable the 100us counter only when state is tx_force_clk_l
delay_100us_counter_enable <= '1' when state = tx_force_clk_l else '0';
-- Counter for a 100us delay
-- after done counting, done signal remains active until
-- enable counter is reset.
delay_100us_counter: process(clk)
begin
if(rising_edge(clk)) then
if(delay_100us_counter_enable = '1') then
if(delay_100us_count = (DELAY_100US)) then
delay_100us_count <= delay_100us_count;
delay_100us_done <= '1';
else
delay_100us_count <= delay_100us_count + 1;
delay_100us_done <= '0';
end if;
else
delay_100us_count <= (others => '0');
delay_100us_done <= '0';
end if;
end if;
end process delay_100us_counter;
-- Enable the 20us counter only when state is tx_bring_data_down
delay_20us_counter_enable <= '1' when state = tx_bring_data_down else '0';
-- Counter for a 20us delay
-- after done counting, done signal remains active until
-- enable counter is reset.
delay_20us_counter: process(clk)
begin
if(rising_edge(clk)) then
if(delay_20us_counter_enable = '1') then
if(delay_20us_count = (DELAY_20US)) then
delay_20us_count <= delay_20us_count;
delay_20us_done <= '1';
else
delay_20us_count <= delay_20us_count + 1;
delay_20us_done <= '0';
end if;
else
delay_20us_count <= (others => '0');
delay_20us_done <= '0';
end if;
end if;
end process delay_20us_counter;
-- Enable the 63clk counter only when state is tx_first_wait_down_edge
delay_63clk_counter_enable <= '1' when state = tx_first_wait_down_edge else '0';
-- Counter for a 63 clock periods delay
-- after done counting, done signal remains active until
-- enable counter is reset.
delay_63clk_counter: process(clk)
begin
if(rising_edge(clk)) then
if(delay_63clk_counter_enable = '1') then
if(delay_63clk_count = (DELAY_63CLK)) then
delay_63clk_count <= delay_63clk_count;
delay_63clk_done <= '1';
else
delay_63clk_count <= delay_63clk_count + 1;
delay_63clk_done <= '0';
end if;
else
delay_63clk_count <= (others => '0');
delay_63clk_done <= '0';
end if;
end if;
end process delay_63clk_counter;
---------------------------------------------------------------------
-- BIT COUNTER AND FRAME SHIFTING LOGIC
---------------------------------------------------------------------
-- counts the number of bits shifted into the frame
-- or out of the frame.
bit_counter: process(clk)
begin
if(rising_edge(clk)) then
if(reset_bit_count = '1') then
bit_count <= (others => '0');
elsif(shift_frame = '1') then
bit_count <= bit_count + 1;
end if;
end if;
end process bit_counter;
-- shifts frame with one bit to right when shift_frame is acitve
-- and loads data into frame from tx_data then load_tx_data is high
load_tx_data_into_frame: process(clk)
begin
if(rising_edge(clk)) then
if(load_tx_data = '1') then
frame(8 downto 1) <= tx_data; -- byte to send
frame(0) <= '0'; -- start bit
frame(10) <= '1'; -- stop bit
frame(9) <= tx_parity; -- parity bit
elsif(shift_frame = '1') then
-- shift right 1 bit
frame(9 downto 0) <= frame(10 downto 1);
-- shift in from the ps2_data line
frame(10) <= ps2_data_s;
end if;
end if;
end process load_tx_data_into_frame;
-- Loads data from frame into rx_data output when data is ready
do_load_rx_data: process(clk)
begin
if(rising_edge(clk)) then
if(load_rx_data = '1') then
rx_data <= frame(8 downto 1);
end if;
end if;
end process do_load_rx_data;
end Behavioral;
| apache-2.0 | 734d93cc266ab21b2cae6aa9b75c55f0 | 0.526401 | 3.927331 | false | false | false | false |
dqydj/VGAtonic | Hardware_Rev_B/CPLD Firmware/Display_Controller.vhd | 2 | 16,020 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Display_Controller is
Port (
-- User logic clock
CLK : in STD_LOGIC; -- 50 (and change) Mhz Clock
-- Display Outputs:
PIXEL : inout STD_LOGIC_VECTOR(8 downto 0) := "111100110";
HSYNC : inout STD_LOGIC := '0';
VSYNC : inout STD_LOGIC := '0';
-- Memory Interface:
ADDR : out STD_LOGIC_VECTOR(18 downto 0) := (others => '0');
DATA : inout STD_LOGIC_VECTOR(7 downto 0);
OE_LOW : out STD_LOGIC := '1';
WE_LOW : out STD_LOGIC := '1';
CE_LOW : out STD_LOGIC := '1';
----------------------------------------------------------------------------------
-- VGAtonic Internal --
----------------------------------------------------------------------------------
-- Inputs from SPI
SPI_DATA_CACHE : in STD_LOGIC_VECTOR(7 downto 0);
SPI_CACHE_FULL_FLAG : in STD_LOGIC;
SPI_CMD_RESET_FLAG : in STD_LOGIC;
-- Acknowledges to SPI
ACK_USER_RESET : inout STD_LOGIC := '0';
ACK_SPI_BYTE : out STD_LOGIC := '0'
);
end Display_Controller;
architecture Behavioral of Display_Controller is
-- Next Write
signal WRITE_DATA : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
-- READ for our constant refresh out the VGA port - 800x525@ 60 FPS
signal VGA_ROW_COUNT : STD_LOGIC_VECTOR(9 downto 0) := (others => '0');
signal VGA_PIXEL_COUNT : STD_LOGIC_VECTOR(9 downto 0) := (others => '0');
-- WRITE for our constant refresh out the VGA port (input from SPI) - 800x525@ 60 FPS
signal WRITE_ROW : STD_LOGIC_VECTOR(9 downto 0) := (others => '1');
signal WRITE_COLUMN : STD_LOGIC_VECTOR(9 downto 0) := (others => '1');
-- Bring Async signals into our clock domain
signal CACHE_FULL_FLAG : STD_LOGIC := '0';
signal CACHE_RESET_FLAG : STD_LOGIC := '0';
-- Write or Read cycle?
signal CYCLE : STD_LOGIC := '0';
-- Do we need to write? Should we reset write address?
signal WRITE_READY : STD_LOGIC := '0';
signal RESET_NEXT : STD_LOGIC := '0';
-- What resolution are we in?
-- 00 - 640x480
-- 01 - 320x240
-- 10 - 160x120
-- 11 - 80 x60
signal USER_RES : STD_LOGIC_VECTOR(1 downto 0) := "00";
-- What bit depth are we in?
-- 00 - 8 bpp (256 Colors)
-- 01 - 4 bpp (16 Colors)
-- 10 - 2 bpp (4 Colors (B,W,GL,GH))
-- 11 - 1 bpp (2 Colors (B,W))
signal USER_BPP : STD_LOGIC_VECTOR(1 downto 0) := "00";
-- We treat masked off addresses as don't cares - unless we are muxing multiple
-- pixels from the same data
signal ADDR_MASK : STD_LOGIC_VECTOR(5 downto 0) := "000000";
-- Blanking periods, to avoid a ton of pterms
signal VBLANK : STD_LOGIC := '0';
signal HBLANK : STD_LOGIC := '0';
Function DecodeAddress
(
USER_RES : STD_LOGIC_VECTOR(1 downto 0);
VGA_ROW_COUNT : STD_LOGIC_VECTOR(9 downto 0);
ADDR_MASK : STD_LOGIC_VECTOR(5 downto 0);
VGA_PIXEL_COUNT : STD_LOGIC_VECTOR(9 downto 0)
) return STD_LOGIC_VECTOR IS
variable tempAddress : STD_LOGIC_VECTOR(18 downto 0);
begin
tempAddress(18 downto 13) := VGA_ROW_COUNT(8 downto 3);
-- Handle multiple resolutions by changing it per user mode.
-- 640x480
-- case USER_RES is
-- WHEN "00" => tempAddress(12 downto 10) := VGA_ROW_COUNT(2 downto 0);
-- WHEN "01" => tempAddress(12 downto 10) := VGA_ROW_COUNT(2 downto 1) & '0';
-- WHEN "10" => tempAddress(12 downto 10) := VGA_ROW_COUNT(2) & "00";
-- WHEN others => tempAddress(12 downto 10) := "000";
-- end case;
tempAddress(12) := (USER_RES(1) nand USER_RES(0)) and VGA_ROW_COUNT(2);
tempAddress(11) := (not USER_RES(1)) and VGA_ROW_COUNT(1);
tempAddress(10) := (USER_RES(1) nor USER_RES(0)) and VGA_ROW_COUNT(0);
tempAddress(9 downto 6) := VGA_PIXEL_COUNT(9 downto 6);
tempAddress(5 downto 0) := VGA_PIXEL_COUNT(5 downto 0) and ADDR_MASK;
return tempAddress;
end FUNCTION DecodeAddress;
begin
-- Our Write/Read Logic
-- Be very careful here since this controls writing/reading from the memory!
CE_LOW <= '0';
OE_LOW <= (not CYCLE);
WE_LOW <= CYCLE or CLK or (not WRITE_READY);
-- Should *only* output on the data bus if we're doing a write.
Write_Data_On_Bus: process (CLK, CYCLE, WRITE_READY, WRITE_DATA, WRITE_ROW)
begin
if ( (CYCLE or CLK) = '1' or WRITE_READY = '0') then
-- Normally be in High-Z mode, since the memory will be controlling the bus at this stage
DATA <= "ZZZZZZZZ";
else
-- Only when in the right clock cycle and we have a write ready
DATA <= WRITE_DATA;
end if;
-- As for address - we flip it every cycle (2 master clocks)
if (CYCLE = '0' and WRITE_READY = '1') then
-- We're about to write
ADDR <= WRITE_ROW(8 downto 0) & WRITE_COLUMN;
else
-- We're doing normal bus reads
ADDR <= DecodeAddress(USER_RES, VGA_ROW_COUNT, ADDR_MASK, VGA_PIXEL_COUNT);
end if;
-- And our lowest blue lonely pixel - have it follow the middle blue bit so we can get true grays.
-- This tradeoff is better than yellow and pink grays.
PIXEL(0) <= PIXEL(1);
end process;
-- Code for Display Logic - Store the mask which we will use to decide our MSB while writing.
-- This is what gives us, effectively, hardware acceleration for lower BPP and resolution.
Display_Logic: process (CLK, ACK_USER_RESET)
Function GetAddressMask
(
DATA : STD_LOGIC_VECTOR(7 downto 0)
) return STD_LOGIC_VECTOR IS
variable tempAddress : STD_LOGIC_VECTOR(5 downto 0);
begin
case DATA(3 downto 0) is
when "0000" => tempAddress := "111111";
when "0100" | "0001" => tempAddress := "111110";
when "1000" | "0010" | "0101" => tempAddress := "111100";
when "1010" | "1101" | "0111" => tempAddress := "110000";
when "1110" | "1011" => tempAddress := "100000";
when "1111" => tempAddress := "000000";
when others => tempAddress := "111000"; -- "1001" | "0110" | "1100" | "0011"
end case;
return tempAddress;
end FUNCTION GetAddressMask;
-- How much to 'increase' the line. For 640x480x8bpp, this is 1, all the way to
-- 80x60x1bpp, which will be increased by 64. That is also the effective speedup.
function getAdditionFactor
(
ADDR_MASK : in STD_LOGIC_VECTOR(5 downto 0)
) return integer is
variable OUTPUT: integer;
begin
-- Not enough pterms to do it will addition; use a LUT
-- OUTPUT := to_integer(unsigned(not ADDR_MASK)) + 1;
case ADDR_MASK is
when "000000" => OUTPUT := 64;
when "100000" => OUTPUT := 32;
when "110000" => OUTPUT := 16;
when "111000" => OUTPUT := 8;
when "111100" => OUTPUT := 4;
when "111110" => OUTPUT := 2;
when others => OUTPUT := 1;
end case;
return OUTPUT;
end getAdditionFactor;
begin
if (rising_edge(CLK)) then -- 50 and change MHz
-- This is our user logic clock now, not SPI anymore
-- Cyle back and forth between read/write, forever
CYCLE <= not CYCLE;
-------------------------------------------------------------------------------------
-- Framebuffer Write/Memory Management Code --
-------------------------------------------------------------------------------------
-- If the cache is full, we need to read it into our working register
if (CACHE_FULL_FLAG = '1' and SPI_CACHE_FULL_FLAG = '1') then
CACHE_FULL_FLAG <= '0';
WRITE_DATA <= SPI_DATA_CACHE;
-- The first digits will 'look like' 639, and the end will equal our shift.
if ( WRITE_COLUMN = "1001" & ADDR_MASK
or WRITE_COLUMN = "1111111111"
) then -- 640 pixels
if (WRITE_ROW(9) = '1') then WRITE_ROW <= "0000000000"; -- End of the line
else
-- Again, not enough pterms to do math, so instead use a LUT
-- WRITE_ROW <= STD_LOGIC_VECTOR(unsigned(WRITE_ROW) + unsigned'("0001") sll to_integer(unsigned(USER_RES)));
case USER_RES is
when "00" => WRITE_ROW <= STD_LOGIC_VECTOR(unsigned(WRITE_ROW) + 1);
when "01" => WRITE_ROW <= STD_LOGIC_VECTOR(unsigned(WRITE_ROW) + 2);
when "10" => WRITE_ROW <= STD_LOGIC_VECTOR(unsigned(WRITE_ROW) + 4);
when others => WRITE_ROW <= STD_LOGIC_VECTOR(unsigned(WRITE_ROW) + 8);
end case;
end if;
WRITE_COLUMN <= "0000000000";
else
WRITE_COLUMN <= STD_LOGIC_VECTOR(unsigned(WRITE_COLUMN) + getAdditionFactor(ADDR_MASK));
end if;
-- ACK back to the SPI logic so it can reset the flag
ACK_SPI_BYTE <= '1';
WRITE_READY <= '1';
else
-- If the cache isn't full, keep checking the flag - but don't change
-- our currently active data
CACHE_FULL_FLAG <= SPI_CACHE_FULL_FLAG;
PIXEL(8 downto 1) <= PIXEL(8 downto 1); -- This doesn't change
ACK_SPI_BYTE <= '0';
end if; -- End Cache Full
if ( CACHE_RESET_FLAG = '1' and SPI_CMD_RESET_FLAG = '1') then
-- If the mode reset flag is full, we need to set the mode back to
-- whatever the initial state is
RESET_NEXT <= '1'; -- Reset next time you get a chance
CACHE_RESET_FLAG <= '0';
ACK_USER_RESET <= '1';
--WRITE_ROW <= (others => '1');
--WRITE_COLUMN <= (others => '1');
else
-- No reset flag up, so do whatever you want with the mode in your code
--if (SPI_CMD_RESET_FLAG = '1') then
CACHE_RESET_FLAG <= SPI_CMD_RESET_FLAG;
--end if;
end if; -- End Cache Full
-- Following this line is code which executes every other clock.
-------------------------------------------------------------------------------------
-- Framebuffer Pixel Code --
-------------------------------------------------------------------------------------
if (CYCLE = '1') then -- First clock, do display things
-- It helps to write this out on paper. This section took probably 15 hours to perfect.
if (VBLANK = '0' and HBLANK = '0') then -- then
--PIXEL <= DATA;
if (USER_BPP = "00") then
PIXEL(8 downto 1) <= DATA;
elsif (USER_BPP = "01") then
PIXEL(8 downto 1) <= ( DATA( to_integer(unsigned'(not VGA_PIXEL_COUNT(to_integer(unsigned(USER_RES))) & "11")) ),
DATA( to_integer(unsigned'(not VGA_PIXEL_COUNT(to_integer(unsigned(USER_RES))) & "00")) ),
DATA( to_integer(unsigned'(not VGA_PIXEL_COUNT(to_integer(unsigned(USER_RES))) & "00")) ),
DATA( to_integer(unsigned'(not VGA_PIXEL_COUNT(to_integer(unsigned(USER_RES))) & "10")) ),
DATA( to_integer(unsigned'(not VGA_PIXEL_COUNT(to_integer(unsigned(USER_RES))) & "00")) ),
DATA( to_integer(unsigned'(not VGA_PIXEL_COUNT(to_integer(unsigned(USER_RES))) & "00")) ),
DATA( to_integer(unsigned'(not VGA_PIXEL_COUNT(to_integer(unsigned(USER_RES))) & "01")) ),
DATA( to_integer(unsigned'(not VGA_PIXEL_COUNT(to_integer(unsigned(USER_RES))) & "00")) )
);
elsif (USER_BPP = "10") then
PIXEL(8 downto 1) <= ( 8 | 5 | 2 => DATA( to_integer(not unsigned(VGA_PIXEL_COUNT(to_integer(unsigned(USER_RES))+1 downto to_integer(unsigned(USER_RES))) & '1'))),
others => DATA( to_integer(not unsigned(VGA_PIXEL_COUNT(to_integer(unsigned(USER_RES))+1 downto to_integer(unsigned(USER_RES))) & '0')))
) ;
else
PIXEL(8 downto 1) <= (others => DATA(to_integer( unsigned(not VGA_PIXEL_COUNT(to_integer(unsigned(USER_RES))+2 downto to_integer(unsigned(USER_RES))))) ));
--PIXEL(8 downto 1) <= (others => DATA( to_integer(unsigned( not VGA_PIXEL_COUNT(2 downto 0) ) )) );
end if;
else
PIXEL(8 downto 1) <= "00000000";
end if;
-------------------------------------------------------------------------------------
-- Normal VGA Control Code - Syncs, Blanking Periods --
-------------------------------------------------------------------------------------
-- VBLANK
if (unsigned(VGA_ROW_COUNT) = 479) then
VBLANK <= '1';
elsif (unsigned(VGA_ROW_COUNT) = 0) then
VBLANK <= '0';
end if;
-- HBLANK
if (unsigned(VGA_PIXEL_COUNT) = 639) then
HBLANK <= '1';
elsif (unsigned(VGA_PIXEL_COUNT) = 0) then
HBLANK <= '0';
end if;
-- Carefully timed HSync
if (unsigned(VGA_PIXEL_COUNT) = 655) then
HSYNC <= '0';
elsif (unsigned(VGA_PIXEL_COUNT) = 751) then
HSYNC <= '1';
end if;
-- Carefully timed VSync
if (unsigned(VGA_ROW_COUNT) = 490 or unsigned(VGA_ROW_COUNT) = 491 or unsigned(VGA_ROW_COUNT) = 489) then
VSYNC <= '0';
else
VSYNC <= '1';
end if;
-- Code for the end of a column and/or the end of a row.
if (VGA_PIXEL_COUNT = "1100011111") then -- 799
-- Column 800 - increase row
VGA_PIXEL_COUNT <= "0000000000";
if (VGA_ROW_COUNT = "1000001100") then -- 524
-- Row 525, reset to 0,0
VGA_ROW_COUNT <= "0000000000";
else
VGA_ROW_COUNT <= STD_LOGIC_VECTOR(UNSIGNED(VGA_ROW_COUNT) + 1);
end if;
else
VGA_PIXEL_COUNT <= STD_LOGIC_VECTOR(UNSIGNED(VGA_PIXEL_COUNT) + 1);
end if;
-- Now the second part of our cycle. Since we are off the bus now, any writes that are queued up will happen here.
else -- CYCLE = '0'
if (ACK_USER_RESET = '1') then
-- Let's reset next time
RESET_NEXT <= '1';
end if;
if (RESET_NEXT = '1') then
-- Our resetting code - basically, set counters to all 1s (so +1 would be at 0,0)
RESET_NEXT <= '0';
WRITE_ROW <= (others => '1');
WRITE_COLUMN <= (others => '1');
ACK_USER_RESET <= '0';
-------------------------------------------------------------------------------------
-- VGATonic Control Code - Mode changes, HW Acceleration --
-------------------------------------------------------------------------------------
-- If we *only* wrote 1 pixel, that's a mode change or a 'move'
-- Easy to check - We would be at address '0' since we were reset here from all 1s.
if( ("0000000000" = WRITE_COLUMN and "0000000000" = WRITE_ROW) ) then
if (WRITE_DATA(7) = '1') then
-- Hardware acceleration! Just put 6 downto 0 bits into our write address.
-- Seriously, that's all we need.
WRITE_ROW <= '0' & -- 9
WRITE_DATA(6 downto 0) & -- 8, 7, 6, 5, 4, 3, 2
"00"; -- 1, 0
-- Only do one at a time - you can do one after another though, as long as you do
-- mode setting first.
else
-- Our 'Mode Change' Packets:
-- 6-4: Reserved (good luck fitting something!)
-- 3-2: User bitdepth (8, 4, 2, 1)
-- 1-0: User Resolution (640x480, 320x240, 160x120, 80x60)
USER_BPP <= WRITE_DATA(3 downto 2);
USER_RES <= WRITE_DATA(1 downto 0);
ADDR_MASK <= GetAddressMask(WRITE_DATA);
end if;
end if;
end if;
if (WRITE_READY = '1') then
-- Reset our write so we don't write every cycle.
WRITE_READY <= '0';
end if;
-- Pixel, VSYNC, and HSYNC shouldn't change just because we're in the
-- writing portion - keep them constant.
PIXEL(8 downto 1) <= PIXEL(8 downto 1);
HSYNC <= HSYNC;
VSYNC <= VSYNC;
end if;
end if; -- End rising edge user logicclock
end process;
-- Framebuffer Core
end Behavioral; | mit | 0f3c40378ba31c939290f754bd8a32c3 | 0.543508 | 3.399109 | false | false | false | false |
FinnK/lems2hdl | work/N3_pointCellCondBased/ISIM_output/n.vhdl | 1 | 20,346 |
---------------------------------------------------------------------
-- Standard Library bits
---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- For Modelsim
--use ieee.fixed_pkg.all;
--use ieee.fixed_float_types.ALL;
-- For ISE
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.fixed_float_types.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Entity Description
---------------------------------------------------------------------
entity n is
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC; --SYNCHRONOUS RESET
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
component_done : out STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_none_instances : in sfixed (18 downto -13);
exposure_none_fcond : out sfixed (18 downto -13);
exposure_none_q : out sfixed (18 downto -13);
statevariable_none_q_out : out sfixed (18 downto -13);
statevariable_none_q_in : in sfixed (18 downto -13);
derivedvariable_none_fcond_out : out sfixed (18 downto -13);
derivedvariable_none_fcond_in : in sfixed (18 downto -13);
param_per_time_forwardRaten1_rate : in sfixed (18 downto -2);
param_voltage_forwardRaten1_midpoint : in sfixed (2 downto -22);
param_voltage_forwardRaten1_scale : in sfixed (2 downto -22);
param_voltage_inv_forwardRaten1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_forwardRaten1_r : out sfixed (18 downto -2);
derivedvariable_per_time_forwardRaten1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_forwardRaten1_r_in : in sfixed (18 downto -2);
param_per_time_reverseRaten1_rate : in sfixed (18 downto -2);
param_voltage_reverseRaten1_midpoint : in sfixed (2 downto -22);
param_voltage_reverseRaten1_scale : in sfixed (2 downto -22);
param_voltage_inv_reverseRaten1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_reverseRaten1_r : out sfixed (18 downto -2);
derivedvariable_per_time_reverseRaten1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_reverseRaten1_r_in : in sfixed (18 downto -2);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end n;
---------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-- Architecture Begins
-------------------------------------------------------------------------------------------
architecture RTL of n is
signal COUNT : unsigned(2 downto 0) := "000";
signal childrenCombined_Component_done_single_shot_fired : STD_LOGIC := '0';
signal childrenCombined_Component_done_single_shot : STD_LOGIC := '0';
signal childrenCombined_Component_done : STD_LOGIC := '0';
signal Component_done_int : STD_LOGIC := '0';
signal subprocess_der_int_pre_ready : STD_LOGIC := '0';
signal subprocess_der_int_ready : STD_LOGIC := '0';
signal subprocess_der_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_pre_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_ready : STD_LOGIC := '0';
signal subprocess_dyn_ready : STD_LOGIC := '0';
signal subprocess_model_ready : STD_LOGIC := '1';
signal subprocess_all_ready_shotdone : STD_LOGIC := '1';
signal subprocess_all_ready_shot : STD_LOGIC := '0';
signal subprocess_all_ready : STD_LOGIC := '0';signal pre_pow_fcond_power_result1_A : sfixed(18 downto -13);
signal pre_pow_fcond_power_result1_A_next : sfixed(18 downto -13);
signal pre_pow_fcond_power_result1_X : sfixed(18 downto -13);
signal pre_pow_fcond_power_result1_X_next : sfixed(18 downto -13);
signal pow_fcond_power_result1 : sfixed(18 downto -13);
signal statevariable_none_noregime_q_temp_1 : sfixed (18 downto -13);
signal statevariable_none_noregime_q_temp_1_next : sfixed (18 downto -13);
component delayDone is
generic(
Steps : integer := 10);
port(
clk : In Std_logic;
init_model : In Std_logic;
Start : In Std_logic;
Done : Out Std_logic
);
end component;
Component ParamPow is
generic(
BIT_TOP : integer := 11;
BIT_BOTTOM : integer := -12);
port(
clk : In Std_logic;
init_model : In Std_logic;
Start : In Std_logic;
Done : Out Std_logic;
X : In sfixed(BIT_TOP downto BIT_BOTTOM);
A : In sfixed(BIT_TOP downto BIT_BOTTOM);
Output : Out sfixed(BIT_TOP downto BIT_BOTTOM)
);
end Component;
---------------------------------------------------------------------
-- Derived Variables and parameters
---------------------------------------------------------------------
signal DerivedVariable_none_rateScale : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_none_rateScale_next : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_per_time_alpha : sfixed (18 downto -2) := to_sfixed(0.0 ,18,-2);
signal DerivedVariable_per_time_alpha_next : sfixed (18 downto -2) := to_sfixed(0.0 ,18,-2);
signal DerivedVariable_per_time_beta : sfixed (18 downto -2) := to_sfixed(0.0 ,18,-2);
signal DerivedVariable_per_time_beta_next : sfixed (18 downto -2) := to_sfixed(0.0 ,18,-2);
signal DerivedVariable_none_fcond : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_none_fcond_next : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_none_inf : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_none_inf_next : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_time_tau : sfixed (6 downto -18) := to_sfixed(0.0 ,6,-18);
signal DerivedVariable_time_tau_next : sfixed (6 downto -18) := to_sfixed(0.0 ,6,-18);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState internal Variables
---------------------------------------------------------------------
signal statevariable_none_q_next : sfixed (18 downto -13);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Output Port internal Variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Child Components
---------------------------------------------------------------------
component forwardRaten1
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC;
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
Component_done : out STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_per_time_rate : in sfixed (18 downto -2);
param_voltage_midpoint : in sfixed (2 downto -22);
param_voltage_scale : in sfixed (2 downto -22);
param_voltage_inv_scale_inv : in sfixed (22 downto -2);
exposure_per_time_r : out sfixed (18 downto -2);
derivedvariable_per_time_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_r_in : in sfixed (18 downto -2);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end component;
signal forwardRaten1_Component_done : STD_LOGIC ; signal Exposure_per_time_forwardRaten1_r_internal : sfixed (18 downto -2);
---------------------------------------------------------------------
component reverseRaten1
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC;
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
Component_done : out STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_per_time_rate : in sfixed (18 downto -2);
param_voltage_midpoint : in sfixed (2 downto -22);
param_voltage_scale : in sfixed (2 downto -22);
param_voltage_inv_scale_inv : in sfixed (22 downto -2);
exposure_per_time_r : out sfixed (18 downto -2);
derivedvariable_per_time_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_r_in : in sfixed (18 downto -2);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end component;
signal reverseRaten1_Component_done : STD_LOGIC ; signal Exposure_per_time_reverseRaten1_r_internal : sfixed (18 downto -2);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Begin Internal Processes
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Child EDComponent Instantiations and corresponding internal variables
---------------------------------------------------------------------
forwardRaten1_uut : forwardRaten1
port map (
clk => clk,
init_model => init_model,
step_once_go => step_once_go,
Component_done => forwardRaten1_Component_done,
param_per_time_rate => param_per_time_forwardRaten1_rate,
param_voltage_midpoint => param_voltage_forwardRaten1_midpoint,
param_voltage_scale => param_voltage_forwardRaten1_scale,
param_voltage_inv_scale_inv => param_voltage_inv_forwardRaten1_scale_inv,
requirement_voltage_v => requirement_voltage_v,
Exposure_per_time_r => Exposure_per_time_forwardRaten1_r_internal,
derivedvariable_per_time_r_out => derivedvariable_per_time_forwardRaten1_r_out,
derivedvariable_per_time_r_in => derivedvariable_per_time_forwardRaten1_r_in,
sysparam_time_timestep => sysparam_time_timestep,
sysparam_time_simtime => sysparam_time_simtime
);
Exposure_per_time_forwardRaten1_r <= Exposure_per_time_forwardRaten1_r_internal;
reverseRaten1_uut : reverseRaten1
port map (
clk => clk,
init_model => init_model,
step_once_go => step_once_go,
Component_done => reverseRaten1_Component_done,
param_per_time_rate => param_per_time_reverseRaten1_rate,
param_voltage_midpoint => param_voltage_reverseRaten1_midpoint,
param_voltage_scale => param_voltage_reverseRaten1_scale,
param_voltage_inv_scale_inv => param_voltage_inv_reverseRaten1_scale_inv,
requirement_voltage_v => requirement_voltage_v,
Exposure_per_time_r => Exposure_per_time_reverseRaten1_r_internal,
derivedvariable_per_time_r_out => derivedvariable_per_time_reverseRaten1_r_out,
derivedvariable_per_time_r_in => derivedvariable_per_time_reverseRaten1_r_in,
sysparam_time_timestep => sysparam_time_timestep,
sysparam_time_simtime => sysparam_time_simtime
);
Exposure_per_time_reverseRaten1_r <= Exposure_per_time_reverseRaten1_r_internal;
derived_variable_pre_process_comb :process ( sysparam_time_timestep,exposure_per_time_forwardRaten1_r_internal,exposure_per_time_reverseRaten1_r_internal, param_none_instances, statevariable_none_q_in ,pow_fcond_power_result1, derivedvariable_per_time_alpha_next , derivedvariable_per_time_beta_next , derivedvariable_none_rateScale_next , derivedvariable_per_time_alpha_next , derivedvariable_per_time_beta_next )
begin
pre_pow_fcond_power_result1_A_next <= resize( statevariable_none_q_in ,18,-13);
pre_pow_fcond_power_result1_X_next <= resize( param_none_instances ,18,-13);
end process derived_variable_pre_process_comb;
derived_variable_pre_process_syn :process ( clk, init_model )
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then
pre_pow_fcond_power_result1_A <= to_sfixed(0,18,-13);
pre_pow_fcond_power_result1_X <= to_sfixed(0,18,-13);
else
if subprocess_all_ready_shot = '1' then
pre_pow_fcond_power_result1_A <= pre_pow_fcond_power_result1_A_next ;
pre_pow_fcond_power_result1_X <= pre_pow_fcond_power_result1_X_next ;
end if;
end if;end if; subprocess_der_int_pre_ready <= '1';
end process derived_variable_pre_process_syn;
ParamPow_fcond_power_result1 : ParamPow
generic map(
BIT_TOP => 18,
BIT_BOTTOM => -13
)
port map ( clk => clk,
init_model => init_model,
Start => step_once_go,
Done => subprocess_der_int_ready,
X => pre_pow_fcond_power_result1_X ,
A => pre_pow_fcond_power_result1_A ,
Output => pow_fcond_power_result1
);
derived_variable_process_comb :process ( sysparam_time_timestep,exposure_per_time_forwardRaten1_r_internal,exposure_per_time_reverseRaten1_r_internal, param_none_instances, statevariable_none_q_in ,pow_fcond_power_result1, derivedvariable_per_time_alpha_next , derivedvariable_per_time_beta_next , derivedvariable_none_rateScale_next , derivedvariable_per_time_alpha_next , derivedvariable_per_time_beta_next )
begin
derivedvariable_per_time_alpha_next <= resize(( exposure_per_time_forwardRaten1_r_internal ),18,-2);
derivedvariable_per_time_beta_next <= resize(( exposure_per_time_reverseRaten1_r_internal ),18,-2);
derivedvariable_none_fcond_next <= resize((pow_fcond_power_result1),18,-13);
derivedvariable_none_inf_next <= resize(( derivedvariable_per_time_alpha_next / ( derivedvariable_per_time_alpha_next + derivedvariable_per_time_beta_next ) ),18,-13);
derivedvariable_time_tau_next <= resize(( to_sfixed ( 1 ,1 , -1 ) / ( ( derivedvariable_per_time_alpha_next + derivedvariable_per_time_beta_next ) ) ),6,-18);
end process derived_variable_process_comb;
uut_delayDone_derivedvariable_n : delayDone GENERIC MAP(
Steps => 2
)
PORT MAP(
clk => clk,
init_model => init_model,
Start => step_once_go,
Done => subprocess_der_ready
);
derived_variable_process_syn :process ( clk,init_model )
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
derivedvariable_per_time_alpha <= derivedvariable_per_time_alpha_next;
derivedvariable_per_time_beta <= derivedvariable_per_time_beta_next;
derivedvariable_none_fcond <= derivedvariable_none_fcond_next;
derivedvariable_none_inf <= derivedvariable_none_inf_next;
derivedvariable_time_tau <= derivedvariable_time_tau_next;
end if;
end if;
end process derived_variable_process_syn;
---------------------------------------------------------------------
dynamics_pre_process_comb :process ( sysparam_time_timestep, statevariable_none_q_in , derivedvariable_time_tau , derivedvariable_none_inf )
begin
end process dynamics_pre_process_comb;
dynamics_pre_process_syn :process ( clk, init_model )
begin
subprocess_dyn_int_pre_ready <= '1';
end process dynamics_pre_process_syn;
--No dynamics with complex equations found
subprocess_dyn_int_ready <= '1';
state_variable_process_dynamics_comb :process (sysparam_time_timestep, statevariable_none_q_in , derivedvariable_time_tau , derivedvariable_none_inf ,statevariable_none_q_in)
begin
statevariable_none_noregime_q_temp_1_next <= resize(statevariable_none_q_in + ( ( derivedvariable_none_inf - statevariable_none_q_in ) / derivedvariable_time_tau ) * sysparam_time_timestep,18,-13);
end process state_variable_process_dynamics_comb;
uut_delayDone_statevariable_n : delayDone GENERIC MAP(
Steps => 2
)
PORT MAP(
clk => clk,
init_model => init_model,
Start => step_once_go,
Done => subprocess_dyn_ready
);state_variable_process_dynamics_syn :process (CLK,init_model)
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
statevariable_none_noregime_q_temp_1 <= statevariable_none_noregime_q_temp_1_next;
end if;
end if;
end process state_variable_process_dynamics_syn;
------------------------------------------------------------------------------------------------------
-- EDState Variable Drivers
------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState variable: $par.name Driver Process
---------------------------------------------------------------------
state_variable_process_comb_0 :process (sysparam_time_timestep,init_model,derivedvariable_none_inf,statevariable_none_noregime_q_temp_1,statevariable_none_q_in,derivedvariable_time_tau,derivedvariable_none_inf)
variable statevariable_none_q_temp_1 : sfixed (18 downto -13);
begin
statevariable_none_q_temp_1 := statevariable_none_noregime_q_temp_1; statevariable_none_q_next <= statevariable_none_q_temp_1;
end process;
---------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to exposures
---------------------------------------------------------------------
exposure_none_q <= statevariable_none_q_in;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to output state variables
---------------------------------------------------------------------
statevariable_none_q_out <= statevariable_none_q_next;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign derived variables to exposures
---------------------------------------------------------------------
exposure_none_fcond <= derivedvariable_none_fcond_in;derivedvariable_none_fcond_out <= derivedvariable_none_fcond;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Subprocess ready process
---------------------------------------------------------------------
subprocess_all_ready_process: process(step_once_go,subprocess_der_int_ready,subprocess_der_int_pre_ready,subprocess_der_ready,subprocess_dyn_int_pre_ready,subprocess_dyn_int_ready,subprocess_dyn_ready,subprocess_model_ready)
begin
if step_once_go = '0' and subprocess_der_int_ready = '1' and subprocess_der_int_pre_ready = '1'and subprocess_der_ready ='1' and subprocess_dyn_int_ready = '1' and subprocess_dyn_int_pre_ready = '1' and subprocess_dyn_ready = '1' and subprocess_model_ready = '1' then
subprocess_all_ready <= '1';
else
subprocess_all_ready <= '0';
end if;
end process subprocess_all_ready_process;
subprocess_all_ready_shot_process : process(clk)
begin
if rising_edge(clk) then
if (init_model='1') then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '1';
else
if subprocess_all_ready = '1' and subprocess_all_ready_shotdone = '0' then
subprocess_all_ready_shot <= '1';
subprocess_all_ready_shotdone <= '1';
elsif subprocess_all_ready_shot = '1' then
subprocess_all_ready_shot <= '0';
elsif subprocess_all_ready = '0' then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '0';
end if;
end if;
end if;
end process subprocess_all_ready_shot_process;
---------------------------------------------------------------------
count_proc:process(clk)
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then COUNT <= "001";
component_done_int <= '1';
else if step_once_go = '1' then
COUNT <= "000";
component_done_int <= '0';
elsif COUNT = "001" then
component_done_int <= '1';
elsif subprocess_all_ready_shot = '1' then
COUNT <= COUNT + 1;
component_done_int <= '0';
end if;
end if;
end if;
end process count_proc;
childrenCombined_component_done_process:process(forwardRaten1_component_done,reverseRaten1_component_done,CLK)
begin
if (forwardRaten1_component_done = '1' and reverseRaten1_component_done = '1') then
childrenCombined_component_done <= '1';
else
childrenCombined_component_done <= '0';
end if;
end process childrenCombined_component_done_process;
component_done <= component_done_int and childrenCombined_component_done;
end RTL;
| lgpl-3.0 | 5bb51a53bd44a7f71ff8539e8d4720ac | 0.604443 | 3.550785 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/boards/terasic-de2-115/cn-single-gpio/quartus/toplevel.vhd | 2 | 13,356 | -------------------------------------------------------------------------------
--! @file toplevel.vhd
--
--! @brief Toplevel of Nios CN FPGA directIO part
--
--! @details This is the toplevel of the Nios CN FPGA directIO design for the
--! INK DE2-115 Evaluation Board.
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity toplevel is
port (
-- 50 MHZ CLK IN
EXT_CLK : in std_logic;
-- PHY Interfaces
PHY_GXCLK : out std_logic_vector(1 downto 0);
PHY_RXCLK : in std_logic_vector(1 downto 0);
PHY_RXER : in std_logic_vector(1 downto 0);
PHY_RXDV : in std_logic_vector(1 downto 0);
PHY_RXD : in std_logic_vector(7 downto 0);
PHY_TXCLK : in std_logic_vector(1 downto 0);
PHY_TXER : out std_logic_vector(1 downto 0);
PHY_TXEN : out std_logic_vector(1 downto 0);
PHY_TXD : out std_logic_vector(7 downto 0);
PHY_MDIO : inout std_logic_vector(1 downto 0);
PHY_MDC : out std_logic_vector(1 downto 0);
PHY_RESET_n : out std_logic_vector(1 downto 0);
-- EPCS
EPCS_DCLK : out std_logic;
EPCS_SCE : out std_logic;
EPCS_SDO : out std_logic;
EPCS_DATA0 : in std_logic;
-- 2 MB SRAM
SRAM_CE_n : out std_logic;
SRAM_OE_n : out std_logic;
SRAM_WE_n : out std_logic;
SRAM_ADDR : out std_logic_vector(20 downto 1);
SRAM_BE_n : out std_logic_vector(1 downto 0);
SRAM_DQ : inout std_logic_vector(15 downto 0);
-- NODE_SWITCH
NODE_SWITCH : in std_logic_vector(7 downto 0);
-- KEY
KEY : in std_logic_vector(3 downto 0);
-- LED
LEDG : out std_logic_vector(7 downto 0);
LEDR : out std_logic_vector(15 downto 0);
-- HEX LED
HEX0 : out std_logic_vector(6 downto 0);
HEX1 : out std_logic_vector(6 downto 0);
HEX2 : out std_logic_vector(6 downto 0);
HEX3 : out std_logic_vector(6 downto 0);
HEX4 : out std_logic_vector(6 downto 0);
HEX5 : out std_logic_vector(6 downto 0);
HEX6 : out std_logic_vector(6 downto 0);
HEX7 : out std_logic_vector(6 downto 0);
-- BENCHMARK_OUT
BENCHMARK : out std_logic_vector(7 downto 0);
-- LCD
LCD_ON : out std_logic;
LCD_BLON : out std_logic;
LCD_DQ : inout std_logic_vector(7 downto 0);
LCD_E : out std_logic;
LCD_RS : out std_logic;
LCD_RW : out std_logic
);
end toplevel;
architecture rtl of toplevel is
component cnSingleGpio is
port (
clk25_clk : in std_logic := 'X';
clk50_clk : in std_logic := 'X';
reset_reset_n : in std_logic := 'X';
clk100_clk : in std_logic := 'X';
-- SRAM
tri_state_0_tcm_address_out : out std_logic_vector(20 downto 0);
tri_state_0_tcm_byteenable_n_out : out std_logic_vector(1 downto 0);
tri_state_0_tcm_read_n_out : out std_logic;
tri_state_0_tcm_write_n_out : out std_logic;
tri_state_0_tcm_data_out : inout std_logic_vector(15 downto 0) := (others => 'X');
tri_state_0_tcm_chipselect_n_out : out std_logic;
-- OPENMAC
openmac_0_mii_txEnable : out std_logic_vector(1 downto 0);
openmac_0_mii_txData : out std_logic_vector(7 downto 0);
openmac_0_mii_txClk : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_mii_rxError : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_mii_rxDataValid : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_mii_rxData : in std_logic_vector(7 downto 0) := (others => 'X');
openmac_0_mii_rxClk : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_smi_nPhyRst : out std_logic_vector(1 downto 0);
openmac_0_smi_clk : out std_logic_vector(1 downto 0);
openmac_0_smi_dio : inout std_logic_vector(1 downto 0) := (others => 'X');
-- BENCHMARK
pcp_0_benchmark_pio_export : out std_logic_vector(7 downto 0);
-- EPCS
epcs_flash_dclk : out std_logic;
epcs_flash_sce : out std_logic;
epcs_flash_sdo : out std_logic;
epcs_flash_data0 : in std_logic := 'X';
-- LCD
lcd_data : inout std_logic_vector(7 downto 0) := (others => 'X');
lcd_E : out std_logic;
lcd_RS : out std_logic;
lcd_RW : out std_logic;
-- NODE SWITCH
node_switch_pio_export : in std_logic_vector(7 downto 0) := (others => 'X');
-- STATUS ERROR LED
status_led_pio_export : out std_logic_vector(1 downto 0);
-- HEX
hex_pio_export : out std_logic_vector(31 downto 0);
-- LEDR
ledr_pio_export : out std_logic_vector(15 downto 0);
-- KEY
key_pio_export : in std_logic_vector(3 downto 0) := (others => 'X')
);
end component cnSingleGpio;
-- PLL component
component pll
port (
inclk0 : in std_logic;
c0 : out std_logic;
c1 : out std_logic;
c2 : out std_logic;
c3 : out std_logic;
locked : out std_logic
);
end component;
signal clk25 : std_logic;
signal clk50 : std_logic;
signal clk100 : std_logic;
signal pllLocked : std_logic;
signal sramAddr : std_logic_vector(SRAM_ADDR'high downto 0);
signal plk_status_error : std_logic_vector(1 downto 0);
type tSevenSegArray is array (natural range <>) of std_logic_vector(6 downto 0);
constant cNumberOfHex : natural := 8;
signal hex : std_logic_vector(cNumberOfHex*4-1 downto 0);
signal sevenSegArray : tSevenSegArray(cNumberOfHex-1 downto 0);
begin
SRAM_ADDR <= sramAddr(SRAM_ADDR'range);
PHY_GXCLK <= (others => '0');
PHY_TXER <= (others => '0');
LCD_ON <= '1';
LCD_BLON <= '1';
LEDG <= "000000" & plk_status_error;
inst : component cnSingleGpio
port map (
clk25_clk => clk25,
clk50_clk => clk50,
clk100_clk => clk100,
reset_reset_n => pllLocked,
openmac_0_mii_txEnable => PHY_TXEN,
openmac_0_mii_txData => PHY_TXD,
openmac_0_mii_txClk => PHY_TXCLK,
openmac_0_mii_rxError => PHY_RXER,
openmac_0_mii_rxDataValid => PHY_RXDV,
openmac_0_mii_rxData => PHY_RXD,
openmac_0_mii_rxClk => PHY_RXCLK,
openmac_0_smi_nPhyRst => PHY_RESET_n,
openmac_0_smi_clk => PHY_MDC,
openmac_0_smi_dio => PHY_MDIO,
tri_state_0_tcm_address_out => sramAddr,
tri_state_0_tcm_read_n_out => SRAM_OE_n,
tri_state_0_tcm_byteenable_n_out => SRAM_BE_n,
tri_state_0_tcm_write_n_out => SRAM_WE_n,
tri_state_0_tcm_data_out => SRAM_DQ,
tri_state_0_tcm_chipselect_n_out => SRAM_CE_n,
pcp_0_benchmark_pio_export => BENCHMARK,
epcs_flash_dclk => EPCS_DCLK,
epcs_flash_sce => EPCS_SCE,
epcs_flash_sdo => EPCS_SDO,
epcs_flash_data0 => EPCS_DATA0,
node_switch_pio_export => NODE_SWITCH,
status_led_pio_export => plk_status_error,
lcd_data => LCD_DQ,
lcd_E => LCD_E,
lcd_RS => LCD_RS,
lcd_RW => LCD_RW,
hex_pio_export => hex,
ledr_pio_export => LEDR,
key_pio_export => KEY
);
-- Pll Instance
pllInst : pll
port map (
inclk0 => EXT_CLK,
c0 => clk50,
c1 => clk100,
c2 => clk25,
c3 => open,
locked => pllLocked
);
-- bcd to 7 segment
genBcdTo7Seg : for i in cNumberOfHex-1 downto 0 generate
signal tmpHex : std_logic_vector(3 downto 0);
signal tmpSev : std_logic_vector(6 downto 0);
begin
tmpHex <= hex((i+1)*4-1 downto i*4);
sevenSegArray(i) <= tmpSev;
bcdTo7Seg0 : entity work.bcd2led
port map (
iBcdVal => tmpHex,
oLed => open,
onLed => tmpSev
);
end generate genBcdTo7Seg;
-- assign outports to array
HEX0 <= sevenSegArray(0);
HEX1 <= sevenSegArray(1);
HEX2 <= sevenSegArray(2);
HEX3 <= sevenSegArray(3);
HEX4 <= sevenSegArray(4);
HEX5 <= sevenSegArray(5);
HEX6 <= sevenSegArray(6);
HEX7 <= sevenSegArray(7);
end rtl;
| gpl-2.0 | f71bc14054441c057d628f65e8307044 | 0.437931 | 4.410832 | false | false | false | false |
julioamerico/OpenCRC | src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@m@s@s_@a@h@b/_primary.vhd | 3 | 10,201 | library verilog;
use verilog.vl_types.all;
entity MSS_AHB is
generic(
ACT_CONFIG : integer := 0;
ACT_FCLK : integer := 0;
ACT_DIE : string := "";
ACT_PKG : string := "";
VECTFILE : string := "test.vec"
);
port(
MSSHADDR : out vl_logic_vector(19 downto 0);
MSSHWDATA : out vl_logic_vector(31 downto 0);
MSSHTRANS : out vl_logic_vector(1 downto 0);
MSSHSIZE : out vl_logic_vector(1 downto 0);
MSSHLOCK : out vl_logic;
MSSHWRITE : out vl_logic;
MSSHRDATA : in vl_logic_vector(31 downto 0);
MSSHREADY : in vl_logic;
MSSHRESP : in vl_logic;
FABHADDR : in vl_logic_vector(31 downto 0);
FABHWDATA : in vl_logic_vector(31 downto 0);
FABHTRANS : in vl_logic_vector(1 downto 0);
FABHSIZE : in vl_logic_vector(1 downto 0);
FABHMASTLOCK : in vl_logic;
FABHWRITE : in vl_logic;
FABHSEL : in vl_logic;
FABHREADY : in vl_logic;
FABHRDATA : out vl_logic_vector(31 downto 0);
FABHREADYOUT : out vl_logic;
FABHRESP : out vl_logic;
SYNCCLKFDBK : in vl_logic;
CALIBOUT : out vl_logic;
CALIBIN : in vl_logic;
FABINT : in vl_logic;
MSSINT : out vl_logic_vector(7 downto 0);
WDINT : out vl_logic;
F2MRESETn : in vl_logic;
DMAREADY : in vl_logic_vector(1 downto 0);
RXEV : in vl_logic;
VRON : in vl_logic;
M2FRESETn : out vl_logic;
DEEPSLEEP : out vl_logic;
SLEEP : out vl_logic;
TXEV : out vl_logic;
UART0CTSn : in vl_logic;
UART0DSRn : in vl_logic;
UART0RIn : in vl_logic;
UART0DCDn : in vl_logic;
UART0RTSn : out vl_logic;
UART0DTRn : out vl_logic;
UART1CTSn : in vl_logic;
UART1DSRn : in vl_logic;
UART1RIn : in vl_logic;
UART1DCDn : in vl_logic;
UART1RTSn : out vl_logic;
UART1DTRn : out vl_logic;
I2C0SMBUSNI : in vl_logic;
I2C0SMBALERTNI : in vl_logic;
I2C0BCLK : in vl_logic;
I2C0SMBUSNO : out vl_logic;
I2C0SMBALERTNO : out vl_logic;
I2C1SMBUSNI : in vl_logic;
I2C1SMBALERTNI : in vl_logic;
I2C1BCLK : in vl_logic;
I2C1SMBUSNO : out vl_logic;
I2C1SMBALERTNO : out vl_logic;
MACM2FTXD : out vl_logic_vector(1 downto 0);
MACF2MRXD : in vl_logic_vector(1 downto 0);
MACM2FTXEN : out vl_logic;
MACF2MCRSDV : in vl_logic;
MACF2MRXER : in vl_logic;
MACF2MMDI : in vl_logic;
MACM2FMDO : out vl_logic;
MACM2FMDEN : out vl_logic;
MACM2FMDC : out vl_logic;
FABSDD0D : in vl_logic;
FABSDD1D : in vl_logic;
FABSDD2D : in vl_logic;
FABSDD0CLK : in vl_logic;
FABSDD1CLK : in vl_logic;
FABSDD2CLK : in vl_logic;
FABACETRIG : in vl_logic;
ACEFLAGS : out vl_logic_vector(31 downto 0);
CMP0 : out vl_logic;
CMP1 : out vl_logic;
CMP2 : out vl_logic;
CMP3 : out vl_logic;
CMP4 : out vl_logic;
CMP5 : out vl_logic;
CMP6 : out vl_logic;
CMP7 : out vl_logic;
CMP8 : out vl_logic;
CMP9 : out vl_logic;
CMP10 : out vl_logic;
CMP11 : out vl_logic;
LVTTL0EN : in vl_logic;
LVTTL1EN : in vl_logic;
LVTTL2EN : in vl_logic;
LVTTL3EN : in vl_logic;
LVTTL4EN : in vl_logic;
LVTTL5EN : in vl_logic;
LVTTL6EN : in vl_logic;
LVTTL7EN : in vl_logic;
LVTTL8EN : in vl_logic;
LVTTL9EN : in vl_logic;
LVTTL10EN : in vl_logic;
LVTTL11EN : in vl_logic;
LVTTL0 : out vl_logic;
LVTTL1 : out vl_logic;
LVTTL2 : out vl_logic;
LVTTL3 : out vl_logic;
LVTTL4 : out vl_logic;
LVTTL5 : out vl_logic;
LVTTL6 : out vl_logic;
LVTTL7 : out vl_logic;
LVTTL8 : out vl_logic;
LVTTL9 : out vl_logic;
LVTTL10 : out vl_logic;
LVTTL11 : out vl_logic;
PUFABn : out vl_logic;
VCC15GOOD : out vl_logic;
VCC33GOOD : out vl_logic;
FCLK : in vl_logic;
MACCLKCCC : in vl_logic;
RCOSC : in vl_logic;
MACCLK : in vl_logic;
PLLLOCK : in vl_logic;
MSSRESETn : in vl_logic;
GPI : in vl_logic_vector(31 downto 0);
GPO : out vl_logic_vector(31 downto 0);
GPOE : out vl_logic_vector(31 downto 0);
SPI0DO : out vl_logic;
SPI0DOE : out vl_logic;
SPI0DI : in vl_logic;
SPI0CLKI : in vl_logic;
SPI0CLKO : out vl_logic;
SPI0MODE : out vl_logic;
SPI0SSI : in vl_logic;
SPI0SSO : out vl_logic_vector(7 downto 0);
UART0TXD : out vl_logic;
UART0RXD : in vl_logic;
I2C0SDAI : in vl_logic;
I2C0SDAO : out vl_logic;
I2C0SCLI : in vl_logic;
I2C0SCLO : out vl_logic;
SPI1DO : out vl_logic;
SPI1DOE : out vl_logic;
SPI1DI : in vl_logic;
SPI1CLKI : in vl_logic;
SPI1CLKO : out vl_logic;
SPI1MODE : out vl_logic;
SPI1SSI : in vl_logic;
SPI1SSO : out vl_logic_vector(7 downto 0);
UART1TXD : out vl_logic;
UART1RXD : in vl_logic;
I2C1SDAI : in vl_logic;
I2C1SDAO : out vl_logic;
I2C1SCLI : in vl_logic;
I2C1SCLO : out vl_logic;
MACTXD : out vl_logic_vector(1 downto 0);
MACRXD : in vl_logic_vector(1 downto 0);
MACTXEN : out vl_logic;
MACCRSDV : in vl_logic;
MACRXER : in vl_logic;
MACMDI : in vl_logic;
MACMDO : out vl_logic;
MACMDEN : out vl_logic;
MACMDC : out vl_logic;
EMCCLK : out vl_logic;
EMCCLKRTN : in vl_logic;
EMCRDB : in vl_logic_vector(15 downto 0);
EMCAB : out vl_logic_vector(25 downto 0);
EMCWDB : out vl_logic_vector(15 downto 0);
EMCRWn : out vl_logic;
EMCCS0n : out vl_logic;
EMCCS1n : out vl_logic;
EMCOEN0n : out vl_logic;
EMCOEN1n : out vl_logic;
EMCBYTEN : out vl_logic_vector(1 downto 0);
EMCDBOE : out vl_logic;
ADC0 : in vl_logic;
ADC1 : in vl_logic;
ADC2 : in vl_logic;
ADC3 : in vl_logic;
ADC4 : in vl_logic;
ADC5 : in vl_logic;
ADC6 : in vl_logic;
ADC7 : in vl_logic;
ADC8 : in vl_logic;
ADC9 : in vl_logic;
ADC10 : in vl_logic;
ADC11 : in vl_logic;
SDD0 : out vl_logic;
SDD1 : out vl_logic;
SDD2 : out vl_logic;
ABPS0 : in vl_logic;
ABPS1 : in vl_logic;
ABPS2 : in vl_logic;
ABPS3 : in vl_logic;
ABPS4 : in vl_logic;
ABPS5 : in vl_logic;
ABPS6 : in vl_logic;
ABPS7 : in vl_logic;
ABPS8 : in vl_logic;
ABPS9 : in vl_logic;
ABPS10 : in vl_logic;
ABPS11 : in vl_logic;
TM0 : in vl_logic;
TM1 : in vl_logic;
TM2 : in vl_logic;
TM3 : in vl_logic;
TM4 : in vl_logic;
TM5 : in vl_logic;
CM0 : in vl_logic;
CM1 : in vl_logic;
CM2 : in vl_logic;
CM3 : in vl_logic;
CM4 : in vl_logic;
CM5 : in vl_logic;
GNDTM0 : in vl_logic;
GNDTM1 : in vl_logic;
GNDTM2 : in vl_logic;
VAREF0 : in vl_logic;
VAREF1 : in vl_logic;
VAREF2 : in vl_logic;
VAREFOUT : out vl_logic;
GNDVAREF : in vl_logic;
PUn : in vl_logic
);
end MSS_AHB;
| gpl-3.0 | ed05f6e085bcfeb96793ab8715e1a4de | 0.401235 | 3.677361 | false | false | false | false |
matbur95/ucisw-pro | pro5a/example2.vhd | 6 | 2,550 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:08:06 03/08/2017
-- Design Name:
-- Module Name: example2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity clockmodule is
port(clk50_in : in std_logic;
red_out : out std_logic;
green_out : out std_logic;
blue_out : out std_logic;
hs_out : out std_logic;
vs_out : out std_logic);
end clockmodule;
architecture Behavioral of clockmodule is
signal horizontal_counter : unsigned (9 downto 0);
signal vertical_counter : unsigned (9 downto 0);
begin
process (clk50_in)
begin
if rising_edge(clk50_in) then
if (horizontal_counter >= "0010010000" ) -- 144
and (horizontal_counter < "1100010000" ) -- 784
and (vertical_counter >= "0000100111" ) -- 39
and (vertical_counter < "1000000111" ) -- 519
then
red_out <= horizontal_counter(3)
and vertical_counter(3);
green_out <= horizontal_counter(4)
and vertical_counter(4);
blue_out <= horizontal_counter(5)
and vertical_counter(5);
else
red_out <= '0';
green_out <= '0';
blue_out <= '0';
end if;
if (horizontal_counter > "0000000000" )
and (horizontal_counter < "0001100001" ) -- 96+1
then
hs_out <= '0';
else
hs_out <= '1';
end if;
if (vertical_counter > "0000000000" )
and (vertical_counter < "0000000011" ) -- 2+1
then
vs_out <= '0';
else
vs_out <= '1';
end if;
horizontal_counter <= horizontal_counter+"0000000001";
if (horizontal_counter="1100100000") then
vertical_counter <= vertical_counter+"0000000001";
horizontal_counter <= "0000000000";
end if;
if (vertical_counter="1000001001") then
vertical_counter <= "0000000000";
end if;
end if;
end process;
end Behavioral;
| mit | c4a6202ad3ee70e6345b68a55d5c58dd | 0.587451 | 3.811659 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/altera/hostinterface/src/alteraHostInterfaceRtl.vhd | 2 | 14,774 | -------------------------------------------------------------------------------
--! @file alteraHostInterface.vhd
--
--! @brief toplevel of host interface for Altera FPGA
--
--! @details This toplevel interfaces to Altera specific implementation.
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! use global library
use work.global.all;
entity alteraHostInterface is
generic (
--! Version major
gVersionMajor : natural := 16#FF#;
--! Version minor
gVersionMinor : natural := 16#FF#;
--! Version revision
gVersionRevision : natural := 16#FF#;
--! Version count
gVersionCount : natural := 0;
-- Base address mapping
--! Base address Dynamic Buffer 0
gBaseDynBuf0 : natural := 16#00800#;
--! Base address Dynamic Buffer 1
gBaseDynBuf1 : natural := 16#01000#;
--! Base address Error Counter
gBaseErrCntr : natural := 16#01800#;
--! Base address TX NMT Queue
gBaseTxNmtQ : natural := 16#02800#;
--! Base address TX Generic Queue
gBaseTxGenQ : natural := 16#03800#;
--! Base address TX SyncRequest Queue
gBaseTxSynQ : natural := 16#04800#;
--! Base address TX Virtual Ethernet Queue
gBaseTxVetQ : natural := 16#05800#;
--! Base address RX Virtual Ethernet Queue
gBaseRxVetQ : natural := 16#06800#;
--! Base address Kernel-to-User Queue
gBaseK2UQ : natural := 16#07000#;
--! Base address User-to-Kernel Queue
gBaseU2KQ : natural := 16#09000#;
--! Base address Tpdo
gBaseTpdo : natural := 16#0B000#;
--! Base address Rpdo
gBaseRpdo : natural := 16#0E000#;
--! Base address Reserved (-1 = high address of Rpdo)
gBaseRes : natural := 16#14000#;
--! Select Host Interface Type (0 = Avalon, 1 = Parallel)
gHostIfType : natural := 0;
--! Data width of parallel interface (16/32)
gParallelDataWidth : natural := 16;
--! Address and Data bus are multiplexed (0 = FALSE, otherwise = TRUE)
gParallelMultiplex : natural := 0
);
port (
--! Clock Source input
csi_c0_clock : in std_logic;
--! Reset Source input
rsi_r0_reset : in std_logic;
-- Avalon Memory Mapped Slave for Host
--! Avalon-MM slave host address
avs_host_address : in std_logic_vector(16 downto 2);
--! Avalon-MM slave host byteenable
avs_host_byteenable : in std_logic_vector(3 downto 0);
--! Avalon-MM slave host read
avs_host_read : in std_logic;
--! Avalon-MM slave host readdata
avs_host_readdata : out std_logic_vector(31 downto 0);
--! Avalon-MM slave host write
avs_host_write : in std_logic;
--! Avalon-MM slave host writedata
avs_host_writedata : in std_logic_vector(31 downto 0);
--! Avalon-MM slave host waitrequest
avs_host_waitrequest : out std_logic;
-- Avalon Memory Mapped Slave for PCP
--! Avalon-MM slave pcp address
avs_pcp_address : in std_logic_vector(10 downto 2);
--! Avalon-MM slave pcp byteenable
avs_pcp_byteenable : in std_logic_vector(3 downto 0);
--! Avalon-MM slave pcp read
avs_pcp_read : in std_logic;
--! Avalon-MM slave pcp readdata
avs_pcp_readdata : out std_logic_vector(31 downto 0);
--! Avalon-MM slave pcp write
avs_pcp_write : in std_logic;
--! Avalon-MM slave pcp writedata
avs_pcp_writedata : in std_logic_vector(31 downto 0);
--! Avalon-MM slave pcp waitrequest
avs_pcp_waitrequest : out std_logic;
-- Avalon Memory Mapped Master for Host via Magic Bridge
--! Avalon-MM master hostBridge address
avm_hostBridge_address : out std_logic_vector(29 downto 0);
--! Avalon-MM master hostBridge byteenable
avm_hostBridge_byteenable : out std_logic_vector(3 downto 0);
--! Avalon-MM master hostBridge read
avm_hostBridge_read : out std_logic;
--! Avalon-MM master hostBridge readdata
avm_hostBridge_readdata : in std_logic_vector(31 downto 0);
--! Avalon-MM master hostBridge write
avm_hostBridge_write : out std_logic;
--! Avalon-MM master hostBridge writedata
avm_hostBridge_writedata : out std_logic_vector(31 downto 0);
--! Avalon-MM master hostBridge waitrequest
avm_hostBridge_waitrequest : in std_logic;
--! Interrupt receiver
inr_irqSync_irq : in std_logic;
--! Interrupt sender
ins_irqOut_irq : out std_logic;
--! External Sync Source
coe_ExtSync_exsync : in std_logic;
--! Node Id
coe_NodeId_nodeid : in std_logic_vector(7 downto 0);
--! POWERLINK Error LED
coe_PlkLed_lederr : out std_logic;
--! POWERLINK Status LED
coe_PlkLed_ledst : out std_logic;
-- Parallel Host Interface
--! Chipselect
coe_parHost_chipselect : in std_logic;
--! Read strobe
coe_parHost_read : in std_logic;
--! Write strobe
coe_parHost_write : in std_logic;
--! Address Latch enable (Multiplexed only)
coe_parHost_addressLatchEnable : in std_logic;
--! High active Acknowledge
coe_parHost_acknowledge : out std_logic;
--! Byteenables
coe_parHost_byteenable : in std_logic_vector(gParallelDataWidth/8-1 downto 0);
--! Address bus (Demultiplexed, word-address)
coe_parHost_address : in std_logic_vector(15 downto 0);
--! Data bus (Demultiplexed)
coe_parHost_data : inout std_logic_vector(gParallelDataWidth-1 downto 0);
--! Address/Data bus (Multiplexed, word-address))
coe_parHost_addressData : inout std_logic_vector(gParallelDataWidth-1 downto 0)
);
end alteraHostInterface;
architecture rtl of alteraHostInterface is
--! The bridge translation lut is implemented in memory blocks to save logic resources.
--! If no M9K shall be used, set this constant to 0.
constant cBridgeUseMemBlock : natural := 1;
signal host_address : std_logic_vector(16 downto 2);
signal host_byteenable : std_logic_vector(3 downto 0);
signal host_read : std_logic;
signal host_readdata : std_logic_vector(31 downto 0);
signal host_write : std_logic;
signal host_writedata : std_logic_vector(31 downto 0);
signal host_waitrequest : std_logic;
begin
--! Assign the host side to Avalon
genAvalon : if gHostIfType = 0 generate
begin
host_address <= avs_host_address;
host_byteenable <= avs_host_byteenable;
host_read <= avs_host_read;
avs_host_readdata <= host_readdata;
host_write <= avs_host_write;
host_writedata <= avs_host_writedata;
avs_host_waitrequest <= host_waitrequest;
end generate;
--! Assign the host side to Parallel
genParallel : if gHostIfType = 1 generate
signal hostData_i : std_logic_vector(gParallelDataWidth-1 downto 0);
signal hostData_o : std_logic_vector(gParallelDataWidth-1 downto 0);
signal hostData_en : std_logic;
signal hostAddressData_i : std_logic_vector(gParallelDataWidth-1 downto 0);
signal hostAddressData_o : std_logic_vector(gParallelDataWidth-1 downto 0);
signal hostAddressData_en : std_logic;
begin
-- not used signals are set to inactive
avs_host_readdata <= (others => cInactivated);
avs_host_waitrequest <= cInactivated;
theParallelInterface : entity work.parallelInterface
generic map (
gDataWidth => gParallelDataWidth,
gMultiplex => gParallelMultiplex
)
port map (
iParHostChipselect => coe_parHost_chipselect,
iParHostRead => coe_parHost_read,
iParHostWrite => coe_parHost_write,
iParHostAddressLatchEnable => coe_parHost_addressLatchEnable,
oParHostAcknowledge => coe_parHost_acknowledge,
iParHostByteenable => coe_parHost_byteenable,
iParHostAddress => coe_parHost_address,
oParHostData => hostData_o,
iParHostData => hostData_i,
oParHostDataEnable => hostData_en,
oParHostAddressData => hostAddressData_o,
iParHostAddressData => hostAddressData_i,
oParHostAddressDataEnable => hostAddressData_en,
iClk => csi_c0_clock,
iRst => rsi_r0_reset,
oHostAddress => host_address,
oHostByteenable => host_byteenable,
oHostRead => host_read,
iHostReaddata => host_readdata,
oHostWrite => host_write,
oHostWritedata => host_writedata,
iHostWaitrequest => host_waitrequest
);
-- tri-state buffers
coe_parHost_data <= hostData_o when hostData_en = cActivated else
(others => 'Z');
hostData_i <= coe_parHost_data;
coe_parHost_addressData <= hostAddressData_o when hostAddressData_en = cActivated else
(others => 'Z');
hostAddressData_i <= coe_parHost_addressData;
end generate;
--! The host interface
theHostInterface: entity work.hostInterface
generic map (
gVersionMajor => gVersionMajor,
gVersionMinor => gVersionMinor,
gVersionRevision => gVersionRevision,
gVersionCount => gVersionCount,
gBridgeUseMemBlock => cBridgeUseMemBlock,
gBaseDynBuf0 => gBaseDynBuf0,
gBaseDynBuf1 => gBaseDynBuf1,
gBaseErrCntr => gBaseErrCntr,
gBaseTxNmtQ => gBaseTxNmtQ,
gBaseTxGenQ => gBaseTxGenQ,
gBaseTxSynQ => gBaseTxSynQ,
gBaseTxVetQ => gBaseTxVetQ,
gBaseRxVetQ => gBaseRxVetQ,
gBaseK2UQ => gBaseK2UQ,
gBaseU2KQ => gBaseU2KQ,
gBaseTpdo => gBaseTpdo,
gBaseRpdo => gBaseRpdo,
gBaseRes => gBaseRes
)
port map (
iClk => csi_c0_clock,
iRst => rsi_r0_reset,
iHostAddress => host_address,
iHostByteenable => host_byteenable,
iHostRead => host_read,
oHostReaddata => host_readdata,
iHostWrite => host_write,
iHostWritedata => host_writedata,
oHostWaitrequest => host_waitrequest,
iPcpAddress => avs_pcp_address,
iPcpByteenable => avs_pcp_byteenable,
iPcpRead => avs_pcp_read,
oPcpReaddata => avs_pcp_readdata,
iPcpWrite => avs_pcp_write,
iPcpWritedata => avs_pcp_writedata,
oPcpWaitrequest => avs_pcp_waitrequest,
oHostBridgeAddress => avm_hostBridge_address,
oHostBridgeByteenable => avm_hostBridge_byteenable,
oHostBridgeRead => avm_hostBridge_read,
iHostBridgeReaddata => avm_hostBridge_readdata,
oHostBridgeWrite => avm_hostBridge_write,
oHostBridgeWritedata => avm_hostBridge_writedata,
iHostBridgeWaitrequest => avm_hostBridge_waitrequest,
iIrqIntSync => inr_irqSync_irq,
iIrqExtSync => coe_ExtSync_exsync,
oIrq => ins_irqOut_irq,
iNodeId => coe_NodeId_nodeid,
oPlkLedError => coe_PlkLed_lederr,
oPlkLedStatus => coe_PlkLed_ledst
);
end rtl;
| gpl-2.0 | 1f73b5f657c8bcc113e435caed0efbca | 0.555232 | 4.867875 | false | false | false | false |
dangpzanco/sistemas-digitais | desloca_direita.vhd | 1 | 755 | library ieee;
use ieee.std_logic_1164.all;
entity desloca_direita is port (
CLK, RST, EN: in std_logic;
sr_in: in std_logic_vector(7 downto 0);
sr_out: out std_logic_vector(7 downto 0);
FlagD: out std_logic_vector(3 downto 0)
);
end desloca_direita;
architecture behv of desloca_direita is
signal sr: std_logic_vector(7 downto 0);
begin
process(CLK, EN, sr_in)
begin
if RST = '0' then
sr <= (others => '0');
elsif (CLK'event and CLK = '1') then
if EN = '1' then
sr(6 downto 0) <= sr_in(7 downto 1);
sr(7) <= '0';
end if;
end if;
end process;
FlagD(3) <= not (sr(7) or sr(6) or sr(5) or sr(4) or sr(3) or sr(2) or sr(1) or sr(0));
FlagD(2) <= '0';
FlagD(1) <= '0';
FlagD(0) <= sr(7);
sr_out <= sr;
end behv; | mit | 0494fd33efa95a6f01490bf09c54c765 | 0.601325 | 2.366771 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/common/openmac/src/mmSlaveConv-rtl-ea.vhd | 2 | 13,860 | -------------------------------------------------------------------------------
--! @file mmSlaveConv-rtl-ea.vhd
--
--! @brief Memory mapped slave interface converter
--
--! @details The slave interface converter is fixed to a 16 bit memory mapped
--! slave, connected to a 32 bit master. The conversion also considers
--! little/big endian (gEndian).
--! Note: Tested with openmacTop entity only!
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
--! use global library
use work.global.all;
entity mmSlaveConv is
generic (
--! Endianness of interconnect
gEndian : string := "little";
--! Memory mapped master address width
gMasterAddrWidth : natural := 10
);
port (
--! Reset
iRst : in std_logic;
--! Clock
iClk : in std_logic;
-- Memory mapped master input
--! Master select
iMaster_select : in std_logic;
--! Master write
iMaster_write : in std_logic;
--! Master read
iMaster_read : in std_logic;
--! Master byteenable
iMaster_byteenable : in std_logic_vector(3 downto 0);
--! Master writedata
iMaster_writedata : in std_logic_vector(31 downto 0);
--! Master readdata
oMaster_readdata : out std_logic_vector(31 downto 0);
--! Master address (byte address)
iMaster_address : in std_logic_vector(gMasterAddrWidth-1 downto 0);
--! Master write acknowledge
oMaster_WriteAck : out std_logic;
--! Master read acknowledge
oMaster_ReadAck : out std_logic;
-- Memory mapped slave output
--! Slave select
oSlave_select : out std_logic;
--! Slave write
oSlave_write : out std_logic;
--! Slave read
oSlave_read : out std_logic;
--! Slave address (word address)
oSlave_address : out std_logic_vector(gMasterAddrWidth-1 downto 0);
--! Slave byteenable
oSlave_byteenable : out std_logic_vector(1 downto 0);
--! Slave readdata
iSlave_readdata : in std_logic_vector(15 downto 0);
--! Slave writedata
oSlave_writedata : out std_logic_vector(15 downto 0);
--! Slave acknowledge
iSlave_ack : in std_logic
);
end mmSlaveConv;
architecture rtl of mmSlaveConv is
--! Access fsm_reg type
type tAccessFsm is (
sIdle,
sDoAccess
);
--! Access type
type tAccess is (
sNone,
sDword,
sWord
);
--! Access fsm_reg current state
signal fsm_reg : tAccessFsm;
--! Access fsm_reg next state
signal fsm_next : tAccessFsm;
--! Current master access type
signal masterAccess : tAccess;
--! Counter width
constant cCounterWidth : natural := 2;
--! Counter register
signal counter_reg : std_logic_vector(cCounterWidth-1 downto 0);
--! Next counter register
signal counter_next : std_logic_vector(cCounterWidth-1 downto 0);
--! Counter register load value
signal counter_loadValue : std_logic_vector(cCounterWidth-1 downto 0);
--! Load counter register with counter_loadValue
signal counter_load : std_logic;
--! Decrement counter value by one
signal counter_decrement : std_logic;
--! counter_reg is zero
signal counter_isZero : std_logic;
--! counter_reg is one
signal counter_isOne : std_logic;
--! counter_reg is two
signal counter_isTwo : std_logic;
--! Master acknowledge
signal masterAck : std_logic;
--! Register to store slave readdata word
signal wordStore_reg : std_logic_vector(iSlave_readdata'range);
--! Next value of slave readdata word register
signal wordStore_next : std_logic_vector(wordStore_reg'range);
begin
---------------------------------------------------------------------------
-- Assign outputs
---------------------------------------------------------------------------
oSlave_select <= iMaster_select;
oSlave_write <= iMaster_write and iMaster_select;
oSlave_read <= iMaster_read and iMaster_select;
oMaster_WriteAck <= masterAck and iMaster_write and iMaster_select;
oMaster_ReadAck <= masterAck and iMaster_read and iMaster_select;
--! This process assigns the master readdata port controlled by the current
--! conversion state.
assignMasterPath : process (
iSlave_readdata, wordStore_reg,
masterAccess
)
begin
if masterAccess = sDword then
oMaster_readdata <= iSlave_readdata & wordStore_reg;
else
oMaster_readdata <= iSlave_readdata & iSlave_readdata;
end if;
end process assignMasterPath;
--! This process assigns the slave address, byteenable and writedata controlled
--! by the current conversion state.
assignSlavePath : process (
iMaster_address, iMaster_byteenable, iMaster_writedata,
counter_reg, counter_isOne,
masterAccess
)
begin
-----------------------------------------------------------------------
-- Slave address
-----------------------------------------------------------------------
--default assignment
oSlave_address <= iMaster_address;
if masterAccess = sDword then
case to_integer(unsigned(counter_reg)) is
when 0 | 2 =>
-- First word of dword access
if gEndian = "little" then
oSlave_address(1) <= cInactivated;
else
oSlave_address(1) <= cActivated;
end if;
when 1 =>
-- Second word of dword access
if gEndian = "little" then
oSlave_address(1) <= cActivated;
else
oSlave_address(1) <= cInactivated;
end if;
when others =>
null; --allowed due to default assignment
end case;
end if;
-----------------------------------------------------------------------
-- Slave byteenable
-----------------------------------------------------------------------
if masterAccess = sDword then
oSlave_byteenable <= (others => cActivated);
else
oSlave_byteenable <= iMaster_byteenable(3 downto 2) or iMaster_byteenable(1 downto 0);
end if;
-----------------------------------------------------------------------
-- Slave writedata
-----------------------------------------------------------------------
if (masterAccess = sDword and counter_isOne = cActivated) or iMaster_address(1) = cActivated then
oSlave_writedata <= iMaster_writedata(31 downto 16);
else
oSlave_writedata <= iMaster_writedata(15 downto 0);
end if;
end process assignSlavePath;
--! This process assigns the registers.
regProc : process(iRst, iClk)
begin
if iRst = cActivated then
counter_reg <= (others => cInactivated);
fsm_reg <= sIdle;
wordStore_reg <= (others => cInactivated);
elsif rising_edge(iClk) then
counter_reg <= counter_next;
fsm_reg <= fsm_next;
wordStore_reg <= wordStore_next;
end if;
end process;
--! This process assigns the register next signals.
assignRegNext : process (
iSlave_readdata, iSlave_ack,
wordStore_reg, fsm_reg, counter_reg,
counter_load, counter_loadValue, counter_decrement, counter_isZero,
counter_isTwo, masterAccess
)
begin
-- default assignments
wordStore_next <= wordStore_reg;
fsm_next <= fsm_reg;
counter_next <= counter_reg;
-----------------------------------------------------------------------
-- Counter
-----------------------------------------------------------------------
if counter_load = cActivated then
counter_next <= counter_loadValue;
elsif counter_decrement = cActivated and masterAccess = sDword then
counter_next <= std_logic_vector(unsigned(counter_reg) - 1);
end if;
-----------------------------------------------------------------------
-- Access FSM
-----------------------------------------------------------------------
if counter_isZero = cActivated then
case fsm_reg is
when sIdle =>
if masterAccess = sDword then
fsm_next <= sDoAccess;
end if;
when sDoAccess =>
if masterAccess = sNone then
fsm_next <= sIdle;
end if;
end case;
end if;
-----------------------------------------------------------------------
-- Store slave readdata word
-----------------------------------------------------------------------
if iSlave_ack = cActivated and masterAccess = sDword and counter_isTwo = cActivated then
wordStore_next <= iSlave_readdata;
end if;
end process assignRegNext;
counter_decrement <= iSlave_ack and iMaster_select;
--! This process assigns internal control signals.
assignInternal : process (
iSlave_ack,
iMaster_select, iMaster_byteenable, iMaster_read,
counter_reg, counter_isOne, masterAccess, fsm_reg, fsm_next
)
begin
-----------------------------------------------------------------------
-- Master acknowledge
-----------------------------------------------------------------------
if iSlave_ack = cActivated and masterAccess = sDword and counter_isOne = cActivated then
masterAck <= cActivated;
elsif iSlave_ack = cActivated and masterAccess = sWord then
masterAck <= cActivated;
else
masterAck <= cInactivated;
end if;
-----------------------------------------------------------------------
-- Master access state
-----------------------------------------------------------------------
if iMaster_select = cInactivated then
masterAccess <= sNone;
elsif iMaster_byteenable = "1111" then
masterAccess <= sDword;
else
masterAccess <= sWord;
end if;
-----------------------------------------------------------------------
-- Counter
-----------------------------------------------------------------------
--default
counter_isZero <= cInactivated;
counter_isOne <= cInactivated;
counter_isTwo <= cInactivated;
-- assign counter_is* signals
case to_integer(unsigned(counter_reg)) is
when 0 =>
counter_isZero <= cActivated;
when 1 =>
counter_isOne <= cActivated;
when 2 =>
counter_isTwo <= cActivated;
when others =>
null; --is allowed due to default assignment
end case;
-- assign counter load
if fsm_next = sDoAccess and fsm_reg = sIdle then
counter_load <= cActivated;
else
counter_load <= cInactivated;
end if;
-- assign counter load value
if iMaster_byteenable = "1111" and iMaster_read = cActivated then
counter_loadValue <= "10";
else
counter_loadValue <= "01";
end if;
end process assignInternal;
end rtl;
| gpl-2.0 | 86ffc450ee3110fddf895653210ea63d | 0.50938 | 5.372093 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/common/hostinterface/src/hostInterfaceRtl.vhd | 2 | 20,653 | -------------------------------------------------------------------------------
--! @file hostInterface.vhd
--
--! @brief toplevel of host interface
--
--! @details The toplevel instantiates the necessary components for the
--! host interface like the Dynamic Bridge and the Status-/Control Registers.
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! use global library
use work.global.all;
--! use host interface package for specific types
use work.hostInterfacePkg.all;
entity hostInterface is
generic (
--! Version major
gVersionMajor : natural := 16#FF#;
--! Version minor
gVersionMinor : natural := 16#FF#;
--! Version revision
gVersionRevision : natural := 16#FF#;
--! Version count
gVersionCount : natural := 0;
--! Use memory blocks or registers for translation address storage (registers = 0, memory blocks /= 0)
gBridgeUseMemBlock : natural := 0;
-- Base address mapping
--! Base address Dynamic Buffer 0
gBaseDynBuf0 : natural := 16#00800#;
--! Base address Dynamic Buffer 1
gBaseDynBuf1 : natural := 16#01000#;
--! Base address Error Counter
gBaseErrCntr : natural := 16#01800#;
--! Base address TX NMT Queue
gBaseTxNmtQ : natural := 16#02800#;
--! Base address TX Generic Queue
gBaseTxGenQ : natural := 16#03800#;
--! Base address TX SyncRequest Queue
gBaseTxSynQ : natural := 16#04800#;
--! Base address TX Virtual Ethernet Queue
gBaseTxVetQ : natural := 16#05800#;
--! Base address RX Virtual Ethernet Queue
gBaseRxVetQ : natural := 16#06800#;
--! Base address Kernel-to-User Queue
gBaseK2UQ : natural := 16#07000#;
--! Base address User-to-Kernel Queue
gBaseU2KQ : natural := 16#09000#;
--! Base address Tpdo
gBaseTpdo : natural := 16#0B000#;
--! Base address Rpdo
gBaseRpdo : natural := 16#0E000#;
--! Base address Reserved (-1 = high address of Rpdo)
gBaseRes : natural := 16#14000#
);
port (
--! Clock Source input
iClk : in std_logic;
--! Reset Source input
iRst : in std_logic;
-- Memory Mapped Slave for Host
--! MM slave host address
iHostAddress : in std_logic_vector(16 downto 2);
--! MM slave host byteenable
iHostByteenable : in std_logic_vector(3 downto 0);
--! MM slave host read
iHostRead : in std_logic;
--! MM slave host readdata
oHostReaddata : out std_logic_vector(31 downto 0);
--! MM slave host write
iHostWrite : in std_logic;
--! MM slave host writedata
iHostWritedata : in std_logic_vector(31 downto 0);
--! MM slave host waitrequest
oHostWaitrequest : out std_logic;
-- Memory Mapped Slave for PCP
--! MM slave pcp address
iPcpAddress : in std_logic_vector(10 downto 2);
--! MM slave pcp byteenable
iPcpByteenable : in std_logic_vector(3 downto 0);
--! MM slave pcp read
iPcpRead : in std_logic;
--! MM slave pcp readdata
oPcpReaddata : out std_logic_vector(31 downto 0);
--! MM slave pcp write
iPcpWrite : in std_logic;
--! MM slave pcp writedata
iPcpWritedata : in std_logic_vector(31 downto 0);
--! MM slave pcp waitrequest
oPcpWaitrequest : out std_logic;
-- Memory Mapped Master for Host via Dynamic Bridge
--! MM master hostBridge address
oHostBridgeAddress : out std_logic_vector(29 downto 0);
--! MM master hostBridge byteenable
oHostBridgeByteenable : out std_logic_vector(3 downto 0);
--! MM master hostBridge read
oHostBridgeRead : out std_logic;
--! MM master hostBridge readdata
iHostBridgeReaddata : in std_logic_vector(31 downto 0);
--! MM master hostBridge write
oHostBridgeWrite : out std_logic;
--! MM master hostBridge writedata
oHostBridgeWritedata : out std_logic_vector(31 downto 0);
--! MM master hostBridge waitrequest
iHostBridgeWaitrequest : in std_logic;
--! Interrupt internal sync signal (from openMAC)
iIrqIntSync : in std_logic;
--! External sync source
iIrqExtSync : in std_logic;
--! Interrupt output signal
oIrq : out std_logic;
--! Node Id
iNodeId : in std_logic_vector(7 downto 0);
--! POWERLINK Error LED
oPlkLedError : out std_logic;
--! POWERLINK Status LED
oPlkLedStatus : out std_logic
);
end hostInterface;
architecture Rtl of hostInterface is
--! Magic
constant cMagic : natural := 16#504C4B00#;
--! Base address array
constant cBaseAddressArray : tArrayStd32 := (
std_logic_vector(to_unsigned(gBaseDynBuf0, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseDynBuf1, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseErrCntr, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseTxNmtQ, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseTxGenQ, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseTxSynQ, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseTxVetQ, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseRxVetQ, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseK2UQ, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseU2KQ, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseTpdo, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseRpdo, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseRes, cArrayStd32ElementSize))
);
--! Base address array count
constant cBaseAddressArrayCount : natural := cBaseAddressArray'length;
--! Base address set by host
constant cBaseAddressHostCount : natural := 2;
--! Base address set by pcp
constant cBaseAddressPcpCount : natural := cBaseAddressArrayCount-cBaseAddressHostCount;
--! Number of interrupt sources (sync not included)
constant cIrqSourceCount : natural := 3;
--! Bridge fsm type
type tFsm is (
sIdle,
sReqAddr,
sAccess,
sDone
);
--! select the bridge logic
signal bridgeSel : std_logic;
--! invalid address range selected
signal invalidSel : std_logic;
--! select status control registers
signal statCtrlSel : std_logic;
--! write status control register
signal statCtrlWrite : std_logic;
--! read status control register
signal statCtrlRead : std_logic;
--! waitrequest from status/control
signal statCtrlWaitrequest : std_logic;
--! readdata from status/control
signal statCtrlReaddata : std_logic_vector(oHostReaddata'range);
--! Bridge request signal
signal bridgeRequest : std_logic;
--! Bridge enable control
signal bridgeEnable : std_logic;
--! Bridge address is valid
signal bridgeAddrValid : std_logic;
--! LED from status/control registers
signal statCtrlLed : std_logic_vector(1 downto 0);
--! The magic bridge outputs the dword address
signal hostBridgeAddress_dword : std_logic_vector(oHostBridgeAddress'length-1 downto 2);
--! Bridge transfer done strobe
signal bridgeTfDone : std_logic;
--! Bridge read data
signal bridgeReaddata : std_logic_vector(iHostBridgeReaddata'range);
--! Bridge state machine
signal fsm : tFsm;
--! Bridge state machine, next state
signal fsm_next : tFsm;
-- base set signals
--! BaseSet Write
signal baseSetWrite : std_logic;
--! BaseSet Read
signal baseSetRead : std_logic;
--! BaseSet byteenable
signal baseSetByteenable : std_logic_vector(3 downto 0);
--! BaseSet Writedata
signal baseSetWritedata : std_logic_vector(hostBridgeAddress_dword'range);
--! BaseSet Readdata
signal baseSetReaddata : std_logic_vector(hostBridgeAddress_dword'range);
--! BaseSet Address
signal baseSetAddress : std_logic_vector(logDualis(cBaseAddressArrayCount)-1 downto 0);
--! BaseSet acknowledge
signal baseSetAck : std_logic;
-- interrupt signals
--! Irq master enable
signal irqMasterEnable : std_logic;
--! Irq source enable
signal irqSourceEnable : std_logic_vector(cIrqSourceCount downto 0);
--! Irq acknowledge
signal irqAcknowledge : std_logic_vector(cIrqSourceCount downto 0);
--! Irq source pending
signal irqSourcePending : std_logic_vector(cIrqSourceCount downto 0);
--! Irq source set (no sync!)
signal irqSourceSet : std_logic_vector(cIrqSourceCount downto 1);
--! sync signal
signal syncSig : std_logic;
--! synchronized ext sync
signal extSync_sync : std_logic;
--! external sync signal
signal extSyncEnable : std_logic;
--! external sync config
signal extSyncConfig : std_logic_vector(cExtSyncEdgeConfigWidth-1 downto 0);
--! external sync signal detected rising edge
signal extSync_rising : std_logic;
--! external sync signal detected falling edge
signal extSync_falling : std_logic;
--! external sync signal detected any edge
signal extSync_any : std_logic;
begin
-- select status/control registers if host address is below 2 kB
statCtrlSel <= cActivated when iHostAddress < cBaseAddressArray(0)(iHostAddress'range) else
cInactivated;
-- select invalid address
invalidSel <= cActivated when iHostAddress >= cBaseAddressArray(cBaseAddressArrayCount-1)(iHostAddress'range) else
cInactivated;
-- bridge is selected if status/control registers are not accessed
bridgeSel <= cInactivated when bridgeEnable = cInactivated else
cInactivated when invalidSel = cActivated else
cInactivated when statCtrlSel = cActivated else
cActivated;
-- create write and read strobe for status/control registers
statCtrlWrite <= iHostWrite and statCtrlSel;
statCtrlRead <= iHostRead and statCtrlSel;
-- host waitrequest from status/control, bridge or invalid
oHostWaitrequest <= statCtrlWaitrequest when statCtrlSel = cActivated else
cInactivated when bridgeEnable = cInactivated else
not bridgeTfDone when bridgeSel = cActivated else
not invalidSel;
-- host readdata from status/control or bridge
oHostReaddata <= bridgeReaddata when bridgeSel = cActivated else
statCtrlReaddata when statCtrlSel = cActivated else
(others => cInactivated);
-- select external sync if enabled, otherwise rx irq signal
syncSig <= iIrqIntSync when extSyncEnable /= cActivated else
extSync_rising when extSyncConfig = cExtSyncEdgeRis else
extSync_falling when extSyncConfig = cExtSyncEdgeFal else
extSync_any when extSyncConfig = cExtSyncEdgeAny else
cInactivated;
--! The bridge state machine handles the address translation of
--! dynamicBridge and finalizes the access to the host bridge master.
theFsmCom : process (
fsm,
bridgeSel,
bridgeAddrValid,
iHostRead,
iHostWrite,
iHostBridgeWaitrequest
)
begin
--default
fsm_next <= fsm;
case fsm is
when sIdle =>
if ( (iHostRead = cActivated or iHostWrite = cActivated) and
bridgeSel = cActivated) then
fsm_next <= sReqAddr;
end if;
when sReqAddr =>
if bridgeAddrValid = cActivated then
fsm_next <= sAccess;
end if;
when sAccess =>
if iHostBridgeWaitrequest = cInactivated then
fsm_next <= sDone;
end if;
when sDone =>
fsm_next <= sIdle;
end case;
end process;
bridgeRequest <= cActivated when fsm = sReqAddr else cInactivated;
bridgeTfDone <= cActivated when fsm = sDone else cInactivated;
--! Clock process to assign registers.
theClkPro : process(iRst, iClk)
begin
if iRst = cActivated then
fsm <= sIdle;
oHostBridgeAddress <= (others => cInactivated);
oHostBridgeByteenable <= (others => cInactivated);
oHostBridgeRead <= cInactivated;
oHostBridgeWrite <= cInactivated;
oHostBridgeWritedata <= (others => cInactivated);
elsif rising_edge(iClk) then
fsm <= fsm_next;
if iHostBridgeWaitrequest = cInactivated then
oHostBridgeRead <= cInactivated;
oHostBridgeWrite <= cInactivated;
bridgeReaddata <= iHostBridgeReaddata;
end if;
if bridgeAddrValid = cActivated then
oHostBridgeAddress <= hostBridgeAddress_dword & "00";
oHostBridgeByteenable <= iHostByteenable;
oHostBridgeRead <= iHostRead;
oHostBridgeWrite <= iHostWrite;
oHostBridgeWritedata <= iHostWritedata;
end if;
end if;
end process;
--! The synchronizer which protects us from crazy effects!
theSynchronizer : entity work.synchronizer
generic map (
gStages => 2,
gInit => cInactivated
)
port map (
iArst => iRst,
iClk => iClk,
iAsync => iIrqExtSync,
oSync => extSync_sync
);
--! The Edge Detector for external sync
theExtSyncEdgeDet : entity work.edgedetector
port map (
iArst => iRst,
iClk => iClk,
iEnable => cActivated,
iData => extSync_sync,
oRising => extSync_rising,
oFalling => extSync_falling,
oAny => extSync_any
);
--! The Dynamic Bridge
theDynamicBridge : entity work.dynamicBridge
generic map (
gAddressSpaceCount => cBaseAddressArrayCount-1,
gUseMemBlock => gBridgeUseMemBlock,
gBaseAddressArray => cBaseAddressArray
)
port map (
iClk => iClk,
iRst => iRst,
iBridgeAddress => iHostAddress,
iBridgeRequest => bridgeRequest,
oBridgeAddress => hostBridgeAddress_dword,
oBridgeSelectAny => open,
oBridgeSelect => open,
oBridgeValid => bridgeAddrValid,
iBaseSetWrite => baseSetWrite,
iBaseSetRead => baseSetRead,
iBaseSetByteenable => baseSetByteenable,
iBaseSetAddress => baseSetAddress,
iBaseSetData => baseSetWritedata,
oBaseSetData => baseSetReaddata,
oBaseSetAck => basesetAck
);
--! The Irq Generator
theIrqGen : entity work.irqGen
generic map (
gIrqSourceCount => cIrqSourceCount
)
port map (
iClk => iClk,
iRst => iRst,
iSync => syncSig,
iIrqSource => irqSourceSet,
oIrq => oIrq,
iIrqMasterEnable => irqMasterEnable,
iIrqSourceEnable => irqSourceEnable,
iIrqAcknowledge => irqAcknowledge,
oIrgPending => irqSourcePending
);
--! The Status-/Control Registers
theStCtrlReg : entity work.statusControlReg
generic map (
gMagic => cMagic,
gVersionMajor => gVersionMajor,
gVersionMinor => gVersionMinor,
gVersionRevision => gVersionRevision,
gVersionCount => gVersionCount,
gHostBaseSet => cBaseAddressHostCount,
gPcpBaseSet => cBaseAddressPcpCount,
gIrqSourceCount => cIrqSourceCount
)
port map (
iClk => iClk,
iRst => iRst,
iHostRead => statCtrlRead,
iHostWrite => statCtrlWrite,
iHostByteenable => iHostByteenable,
iHostAddress => iHostAddress(10 downto 2),
oHostReaddata => statCtrlReaddata,
iHostWritedata => iHostWritedata,
oHostWaitrequest => statCtrlWaitrequest,
iPcpRead => iPcpRead,
iPcpWrite => iPcpWrite,
iPcpByteenable => iPcpByteenable,
iPcpAddress => iPcpAddress,
oPcpReaddata => oPcpReaddata,
iPcpWritedata => iPcpWritedata,
oPcpWaitrequest => oPcpWaitrequest,
oBaseSetWrite => baseSetWrite,
oBaseSetRead => baseSetRead,
oBaseSetByteenable => baseSetByteenable,
oBaseSetAddress => baseSetAddress,
iBaseSetData => baseSetReaddata,
oBaseSetData => baseSetWritedata,
iBaseSetAck => basesetAck,
oIrqMasterEnable => irqMasterEnable,
oIrqSourceEnable => irqSourceEnable,
oIrqAcknowledge => irqAcknowledge,
oIrqSet => irqSourceSet,
iIrqPending => irqSourcePending,
oExtSyncEnable => extSyncEnable,
oExtSyncConfig => extSyncConfig,
iNodeId => iNodeId,
oPLed => statCtrlLed,
oBridgeEnable => bridgeEnable
);
oPlkLedStatus <= statCtrlLed(0);
oPlkLedError <= statCtrlLed(1);
end Rtl;
| gpl-2.0 | adefea2728e3f6cb4f9251ee3876ccfc | 0.584031 | 5.232582 | false | false | false | false |
FinnK/lems2hdl | work/N2_Izhikevich/ISIM_output/testbench.vhdl | 1 | 7,843 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.fixed_float_types.ALL;
use std.textio.all;
use ieee.std_logic_textio.all; -- if you're saving this type of signal
entity tb_simulation is
end tb_simulation;
architecture tb of tb_simulation is
FILE test_out_data: TEXT open WRITE_MODE is "VHDLoutput.csv";component top_synth
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC; --SYNCHRONOUS RESET
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
step_once_complete : out STD_LOGIC; --signals to the core that a time step has finished
eventport_in_spike_aggregate : in STD_LOGIC_VECTOR(511 downto 0);
neuron_model_eventport_out_spike : out STD_LOGIC;
neuron_model_param_voltage_v0 : in sfixed (2 downto -22);
neuron_model_param_none_a : in sfixed (18 downto -13);
neuron_model_param_none_b : in sfixed (18 downto -13);
neuron_model_param_none_c : in sfixed (18 downto -13);
neuron_model_param_none_d : in sfixed (18 downto -13);
neuron_model_param_voltage_thresh : in sfixed (2 downto -22);
neuron_model_param_time_MSEC : in sfixed (6 downto -18);
neuron_model_param_voltage_MVOLT : in sfixed (2 downto -22);
neuron_model_param_time_inv_MSEC_inv : in sfixed (18 downto -6);
neuron_model_param_voltage_inv_MVOLT_inv : in sfixed (22 downto -2);
neuron_model_param_none_div_voltage_b_div_MVOLT : in sfixed (18 downto -13);
neuron_model_exposure_voltage_v : out sfixed (2 downto -22);
neuron_model_exposure_none_U : out sfixed (18 downto -13);
neuron_model_stateCURRENT_voltage_v : out sfixed (2 downto -22);
neuron_model_stateRESTORE_voltage_v : in sfixed (2 downto -22);
neuron_model_stateCURRENT_none_U : out sfixed (18 downto -13);
neuron_model_stateRESTORE_none_U : in sfixed (18 downto -13);
neuron_model_param_time_i1_delay : in sfixed (6 downto -18);
neuron_model_param_time_i1_duration : in sfixed (6 downto -18);
neuron_model_param_none_i1_amplitude : in sfixed (18 downto -13);
neuron_model_exposure_none_i1_I : out sfixed (18 downto -13);
neuron_model_stateCURRENT_none_i1_I : out sfixed (18 downto -13);
neuron_model_stateRESTORE_none_i1_I : in sfixed (18 downto -13);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end component;
signal clk : std_logic := '0';
signal eog : std_logic := '0';
signal init_model : std_logic := '1';
signal step_once_go : std_logic := '0';
signal step_once_complete : std_logic := '0';
signal eventport_in_spike_aggregate : STD_LOGIC_VECTOR(511 downto 0);
signal sysparam_time_simtime : sfixed ( 6 downto -22) := to_sfixed (0.0,6 , -22);
signal Errors : integer;
signal sysparam_time_timestep : sfixed (-6 downto -22) := to_sfixed( 5.0E-5 ,-6,-22);
signal neuron_model_stateCURRENT_voltage_v_int : sfixed (2 downto -22);signal neuron_model_stateCURRENT_none_U_int : sfixed (18 downto -13);signal neuron_model_eventport_out_spike_internal : std_logic; signal neuron_model_stateCURRENT_none_i1_I_int : sfixed (18 downto -13);signal neuron_model_eventport_in_i1_in_internal : std_logic;
file stimulus: TEXT open read_mode is "stimulus.csv";
begin
top_synth_uut : top_synth
port map ( clk => clk,
init_model => init_model,
step_once_go => step_once_go,
step_once_complete => step_once_complete,
eventport_in_spike_aggregate => eventport_in_spike_aggregate,
neuron_model_eventport_out_spike => neuron_model_eventport_out_spike_internal ,
neuron_model_param_voltage_v0 => to_sfixed (-0.07,2 , -22),
neuron_model_param_none_a => to_sfixed (0.02,18 , -13),
neuron_model_param_none_b => to_sfixed (0.2,18 , -13),
neuron_model_param_none_c => to_sfixed (-50.0,18 , -13),
neuron_model_param_none_d => to_sfixed (2.0,18 , -13),
neuron_model_param_voltage_thresh => to_sfixed (0.03,2 , -22),
neuron_model_param_time_MSEC => to_sfixed (0.001,6 , -18),
neuron_model_param_voltage_MVOLT => to_sfixed (0.001,2 , -22),
neuron_model_param_time_inv_MSEC_inv => to_sfixed (1000.0,18 , -6),
neuron_model_param_voltage_inv_MVOLT_inv => to_sfixed (1000.0,22 , -2),
neuron_model_param_none_div_voltage_b_div_MVOLT => to_sfixed (200.0,18 , -13),
neuron_model_stateCURRENT_voltage_v => neuron_model_stateCURRENT_voltage_v_int,
neuron_model_stateRESTORE_voltage_v => to_sfixed (-0.07,2 , -22),
neuron_model_stateCURRENT_none_U => neuron_model_stateCURRENT_none_U_int,
neuron_model_stateRESTORE_none_U => to_sfixed (-14.0,18 , -13),
neuron_model_param_time_i1_delay => to_sfixed (0.022,6 , -18),
neuron_model_param_time_i1_duration => to_sfixed (2.0,6 , -18),
neuron_model_param_none_i1_amplitude => to_sfixed (15.0,18 , -13),
neuron_model_stateCURRENT_none_i1_I => neuron_model_stateCURRENT_none_i1_I_int,
neuron_model_stateRESTORE_none_i1_I => to_sfixed (0.0,18 , -13),
sysparam_time_timestep => sysparam_time_timestep,
sysparam_time_simtime => sysparam_time_simtime
);
receive_data: process
variable l: line;
variable char : character;
variable s : STD_LOGIC_VECTOR(0 downto 0);
begin
-- wait for Reset to complete
-- wait until init_model='1';
wait until init_model='0';
while not endfile(stimulus) loop
-- read digital data from input file
readline(stimulus, l);
read(l, s);
eventport_in_spike_aggregate(0) <= s(0);
wait until step_once_go = '1';
end loop;
assert false report "end of simulation" severity failure;
end process receive_data;
process
variable L1 : LINE;
begin
write(L1, "SimulationTime " );
write(L1, "neuron_model_spike " );
write(L1, "neuron_model_stateCURRENT_voltage_v" );
write(L1, " ");
write(L1, "neuron_model_stateCURRENT_none_U" );
write(L1, " ");
write(L1, "neuron_model_stateCURRENT_none_i1_I" );
write(L1, " ");
writeline(test_out_data, L1); -- write row to output file
Wait;
end process;
clk <= not(clk) after 10 ns;
step_once_go_proc: process
begin
-- wait for Reset to complete
-- wait until init_model='1';
wait until init_model='0';
wait for 180 ns;
while 1 = 1 loop
step_once_go <= '1';
wait for 20 ns;
step_once_go <= '0';
wait until step_once_complete = '1';
wait until step_once_complete = '0';
end loop;
end process step_once_go_proc;
process
begin
wait for 20 ns;
init_model <= '1';
wait for 20 ns;
init_model <= '0';
wait;
end process ;
--
-- Print the results at each clock tick.
--
process(step_once_complete)
variable L1 : LINE;
begin
if (init_model = '1') then
sysparam_time_simtime <= to_sfixed (0.0,6, -22);
else
if (step_once_complete'event and step_once_complete = '1' and init_model = '0') then
sysparam_time_simtime <= resize(sysparam_time_simtime + sysparam_time_timestep,6, -22);
write(L1, real'image(to_real( sysparam_time_simtime ))); -- nth value in row
write(L1, " ");
if ( neuron_model_eventport_out_spike_internal = '1') then
write(L1, "1 " );
else
write(L1, "0 " );
end if;
write(L1, real'image(to_real(neuron_model_stateCURRENT_voltage_v_int)) );
write(L1, " ");
write(L1, real'image(to_real(neuron_model_stateCURRENT_none_U_int)) );
write(L1, " ");
write(L1, real'image(to_real(neuron_model_stateCURRENT_none_i1_I_int)) );
write(L1, " ");
writeline(test_out_data, L1); -- write row to output file
end if;
end if;
end process;
end tb;
| lgpl-3.0 | d55cd5bfbd958a67c9351d6785e72cf8 | 0.661737 | 2.936353 | false | false | false | false |
sergev/vak-opensource | hardware/dlx/reg_2_1_out-behaviour.vhdl | 1 | 1,796 | --------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: reg_2_1_out-behaviour.vhdl,v $ $Revision: 2.1 $ $Date: 1993/11/02 19:06:59 $
--
--------------------------------------------------------------------------
--
-- Behavioural architecture of register with two tri-state
-- outputs and one ordinary output.
--
architecture behaviour of reg_2_1_out is
begin
reg: process (d, latch_en, out_en1, out_en2)
variable latched_value : dlx_word;
begin
if latch_en = '1' then
latched_value := d;
end if;
if out_en1 = '1' then
q1 <= latched_value after Tpd;
else
q1 <= null after Tpd;
end if;
if out_en2 = '1' then
q2 <= latched_value after Tpd;
else
q2 <= null after Tpd;
end if;
q3 <= latched_value after Tpd;
end process reg;
end behaviour;
| apache-2.0 | 719d595c54b12cd064a8ae33b0a6d1f6 | 0.586303 | 3.78903 | false | false | false | false |
kristofferkoch/ethersound | packetgen.vhd | 1 | 4,488 | -----------------------------------------------------------------------------
-- Packet generator for hwpulse
--
-- Authors:
-- -- Kristoffer E. Koch
-----------------------------------------------------------------------------
-- Copyright 2008 Authors
--
-- This file is part of hwpulse.
--
-- hwpulse is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- hwpulse is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with hwpulse. If not, see <http://www.gnu.org/licenses/>.
-----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
entity packetgen is
Port ( sysclk : in STD_LOGIC;
reset : in STD_LOGIC;
rate_pulse : in STD_LOGIC;
edata_o : out STD_LOGIC_VECTOR (7 downto 0);
edata_o_v : out STD_LOGIC;
edata_o_req : in STD_LOGIC;
debug : out STD_LOGIC_VECTOR (7 downto 0));
end packetgen;
architecture RTL of packetgen is
type state_t is (Idle, txDest, txSource, txType, txCmd, txCmdLen, txCmdParam, Pad, stWait);
signal state, retstate:state_t;
signal framecounter,fcnt_buf:unsigned(63 downto 0);
signal sendcount:integer range 0 to 511;
signal cnt:integer range 0 to 7;
signal remain:integer range 0 to 45;
constant MAC:std_logic_vector(47 downto 0):=x"000a35002201";
begin
fcnt:process(sysclk) is
begin
if rising_edge(sysclk) then
if reset = '1' then
framecounter <= to_unsigned(0, 64);
sendcount <= 0;
else
if rate_pulse = '1' then
framecounter <= framecounter + 1;
if sendcount = 511 then
sendcount <= 0;
else
sendcount <= sendcount + 1;
end if;
end if;
end if;
end if;
end process;
fsm:process(sysclk) is
begin
if rising_edge(sysclk) then
if reset = '1' then
state <= Idle;
edata_o_v <= '0';
edata_o <= (OTHERS => '0');
else
case state is
when Idle =>
if edata_o_req = '1' then
edata_o_v <= '0';
end if;
if sendcount = 0 then
state <= txDest;
end if;
remain <= 45;
cnt <= 5;
when txDest =>
if edata_o_req = '1' then
edata_o_v <= '1';
edata_o <= x"ff";
if cnt = 0 then
retstate <= txSource;
cnt <= 5;
else
cnt <= cnt - 1;
retstate <= state;
end if;
state <= stWait;
end if;
when stWait =>
state <= retstate;
when txSource =>
if edata_o_req = '1' then
edata_o_v <= '1';
edata_o <= MAC(cnt*8+7 downto cnt*8);
if cnt = 0 then
state <= txType;
cnt <= 1;
else
cnt <= cnt - 1;
end if;
end if;
when txType =>
if edata_o_req = '1' then
edata_o_v <= '1';
if cnt = 0 then
edata_o <= x"b5";
state <= txCmd;
else
edata_o <= x"88";
cnt <= cnt - 1;
end if;
end if;
when txCmd =>
if edata_o_req = '1' then
edata_o_v <= '1';
edata_o <= x"01";
state <= txCmdLen;
remain <= remain - 1;
end if;
when txCmdLen =>
if edata_o_req = '1' then
edata_o_v <= '1';
edata_o <= x"08";
cnt <= 7;
state <= txCmdParam;
fcnt_buf <= framecounter;
remain <= remain - 1;
end if;
when txCmdParam =>
if edata_o_req = '1' then
edata_o_v <= '1';
remain <= remain - 1;
edata_o <= std_logic_vector(fcnt_buf(cnt*8+7 downto cnt*8));
if cnt = 0 then
if remain /= 0 then
state <= Pad;
else
state <= Idle;
end if;
else
cnt <= cnt - 1;
end if;
end if;
when Pad =>
if edata_o_req = '1' then
edata_o_v <= '1';
edata_o <= x"00";
if remain = 0 then
state <= Idle;
else
remain <= remain - 1;
end if;
end if;
end case;
end if;
end if;
end process;
end RTL;
| gpl-3.0 | dbe48df2242dc87b6b16aeacccdeda38 | 0.512701 | 3.302428 | false | false | false | false |
matbur95/ucisw-pro | pro4a/master.vhd | 1 | 4,696 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:03:57 04/05/2017
-- Design Name:
-- Module Name: master - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MASTER is
Port ( ADC_DOA : in STD_LOGIC_VECTOR (13 downto 0);
ADC_DOB : in STD_LOGIC_VECTOR (13 downto 0);
ADC_BUSY : in STD_LOGIC;
CLK : in STD_LOGIC;
POS : in STD_LOGIC_VECTOR(19 downto 0);
DATA : in STD_LOGIC;
Line : out STD_LOGIC_VECTOR (63 downto 0);
Blank : out STD_LOGIC_VECTOR (15 downto 0);
ADDR : out STD_LOGIC_VECTOR (13 downto 0);
VGA_COLOR : out STD_LOGIC_VECTOR(2 downto 0);
AMP_WE : out STD_LOGIC;
ADC_Start : out STD_LOGIC;
AMP_DI : out STD_LOGIC_VECTOR (7 downto 0));
end MASTER;
architecture Behavioral of MASTER is
-- constant SIDE : integer := 50;
constant SIDE : signed ( 10 downto 0 ) := to_signed( 20, 11);
constant VMAX : signed ( 10 downto 0 ) := to_signed( 600, 11);
constant HMAX : signed ( 10 downto 0 ) := to_signed( 800, 11);
-- constant HMAX : integer := 800;
-- signal BOX_HPOS : integer range -100 to 1000 := 400;
signal BOX_HPOS : signed( 10 downto 0) := to_signed( 0, 11 );
signal BOX_VPOS : signed( 10 downto 0) := to_signed( 550, 11 );
constant BOX_VPOS_INIT : signed ( 10 downto 0 ) := to_signed( 550, 11);
constant BOX_HPOS_INIT : signed ( 10 downto 0 ) := to_signed( 0, 11);
-- signal BOX_VPOS : integer range -100 to 1000 := 300;
signal HPOS : signed( 10 downto 0) := to_signed( 0, 11 );
signal VPOS : signed( 10 downto 0) := to_signed( 0, 11 );
-- signal HPOS : integer range 0 to 800 := 0;
-- signal VPOS : integer range 0 to 600 := 0;
signal VGA_COLOR_INT : STD_LOGIC_VECTOR(2 downto 0);
begin
HPOS <= signed('0' & POS(19 downto 10));
VPOS <= signed('0' & POS(9 downto 0));
AMP_WE <= '1' when HPOS = 0 and VPOS = 0 else '0';
AMP_DI <= X"11";
ADC_Start <= '1' when HPOS = HMAX and VPOS = VMAX else '0';
Blank <= X"0F0F";
Line <= "00" & ADC_DOA & X"0000" & "00" & ADC_DOB & X"0000";
BOX: process (CLK, HPOS, VPOS)
begin
if rising_edge(CLK) then
if HPOS = 0 and VPOS = 0 then
BOX_HPOS <= BOX_HPOS - signed(ADC_DOA(13 downto 11));
BOX_VPOS <= BOX_VPOS + signed(ADC_DOB(13 downto 11));
end if;
if BOX_HPOS < 0 then
BOX_HPOS <= to_signed(0, 11);
elsif BOX_HPOS > HMAX - SIDE then
BOX_HPOS <= HMAX - SIDE;
end if;
if BOX_VPOS < 0 then
BOX_VPOS <= to_signed(0, 11);
elsif BOX_VPOS > VMAX - SIDE then
BOX_VPOS <= VMAX - SIDE;
end if;
if DATA = '0' and
HPOS > BOX_HPOS and HPOS < BOX_HPOS + SIDE and
VPOS > BOX_VPOS and VPOS < BOX_VPOS + SIDE then
BOX_HPOS <= BOX_HPOS_INIT;
BOX_VPOS <= BOX_VPOS_INIT;
end if;
-- if HPOS > BOX_HPOS and HPOS < BOX_HPOS + SIDE and VPOS > BOX_VPOS and VPOS < BOX_VPOS + SIDE then
-- VGA_COLOR_INT <= B"101";
-- else
-- VGA_COLOR_INT <= DATA & DATA & not DATA;
-- end if;
-- VGA_COLOR_INT <= B"101" when HPOS > BOX_HPOS and HPOS < BOX_HPOS + SIDE and VPOS > BOX_VPOS and VPOS < BOX_VPOS + SIDE else ;
-- if HPOS > BOX_HPOS and HPOS < BOX_HPOS + SIDE and VPOS > BOX_VPOS and VPOS < BOX_VPOS + SIDE then
-- VGA_COLOR <= B"101";
-- else
-- VGA_COLOR <= B"001";
-- end if;
end if;
end process BOX;
-- BOX_HPOS <= BOX_HPOS + to_integer(signed(ADC_DOA(13 downto 12)));
ADDR <= STD_LOGIC_VECTOR(VPOS(9 downto 3)) & STD_LOGIC_VECTOR(HPOS(9 downto 3));
VGA_COLOR_INT <= B"101" when HPOS > BOX_HPOS and HPOS < BOX_HPOS + SIDE and VPOS > BOX_VPOS and VPOS < BOX_VPOS + SIDE else DATA & DATA & not DATA;
-- VGA_COLOR_INT <= DATA & DATA & not DATA;
VGA_COLOR <= VGA_COLOR_INT;
end Behavioral;
| mit | 07240e0e07ae12f3dfac6436eb354383 | 0.548126 | 3.388167 | false | false | false | false |
kristofferkoch/ethersound | s3an_top.vhd | 1 | 8,137 | -----------------------------------------------------------------------------
-- Top module for implementing hwpulse on Xilinx Spartan 3 Starter Kit
--
-- Authors:
-- -- Kristoffer E. Koch
-----------------------------------------------------------------------------
-- Copyright 2008 Authors
--
-- This file is part of hwpulse.
--
-- hwpulse is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- hwpulse is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with hwpulse. If not, see <http://www.gnu.org/licenses/>.
-----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity s3an_top is
-- generic(
-- MAC:std_logic_vector(47 downto 0):=x"010B5E000000"
-- );
port (
-- Clock-input from crystal osc
clk_50m : in std_logic;
-- Leds on the board. Nice for debugging.
led : out std_logic_vector(7 downto 0);
-- Pins for MDIO-interfacing the PHY
e_nrst : out std_logic;
e_mdc : out std_logic;
e_mdio : inout std_logic;
-- Pins for receiving data from the PHY
e_rx_clk : in std_logic;
e_rxd : in std_logic_vector(3 downto 0);
e_rx_dv : in std_logic;
-- Pins for sending data to the PHY
e_tx_clk : in std_logic;
e_txd : out std_logic_vector(3 downto 0);
e_tx_en : out std_logic;
-- Button used as a reset-button
btn_south : in std_logic;
-- Rudimentary delta-sigma modulated digital sound outputs.
-- Without analog lowpass-filter.
-- Sounds like crap, but is easy to plug headphones into.
aud_l:out std_logic;
aud_r:out std_logic
);
end s3an_top;
architecture Behavioral of s3an_top is
component miim
generic (
DIVISOR : integer;
PHYADDR : std_logic_vector(4 downto 0)
);
port (
sysclk : in std_logic;
reset : in std_logic;
addr : in std_logic_vector(4 downto 0);
data_i : in std_logic_vector(15 downto 0);
data_i_e : in std_logic;
data_o : out std_logic_vector(15 downto 0);
data_o_e : in std_logic;
busy : out std_logic;
miim_clk : out std_logic;
miim_d : inout std_logic
);
end component;
component phy_ctrl
port (
sysclk : in std_logic;
reset : in std_logic;
data_i : in std_logic_vector(7 downto 0);
data_i_v : in std_logic;
miim_addr : out std_logic_vector(4 downto 0);
miim_data_i : out std_logic_vector(15 downto 0);
miim_data_i_e : out std_logic;
miim_data_o : in std_logic_vector(15 downto 0);
miim_data_o_e : out std_logic;
miim_busy : in std_logic
);
end component;
COMPONENT txsync
PORT(
sysclk : IN std_logic;
reset : IN std_logic;
tx_clk : IN std_logic;
txd : OUT std_logic_vector(3 downto 0);
tx_dv : OUT std_logic;
data : IN std_logic_vector(7 downto 0);
data_send : IN std_logic;
data_req : OUT std_logic;
debug:out std_logic_vector(7 downto 0)
);
END COMPONENT;
component packetgen is
Port ( sysclk : in STD_LOGIC;
reset : in STD_LOGIC;
rate_pulse : in STD_LOGIC;
edata_o : out STD_LOGIC_VECTOR (7 downto 0);
edata_o_v : out STD_LOGIC;
edata_o_req : in STD_LOGIC;
debug : out STD_LOGIC_VECTOR (7 downto 0));
end component;
COMPONENT rxsync
PORT(
sysclk : IN std_logic;
reset : IN std_logic;
rx_clk : IN std_logic;
rxd : IN std_logic_vector(3 downto 0);
rx_dv : IN std_logic;
data : OUT std_logic_vector(7 downto 0);
data_end : OUT std_logic;
data_err : OUT std_logic;
data_dv : OUT std_logic;
debug: out std_logic_vector(7 downto 0)
);
END COMPONENT;
COMPONENT rxdecode
Port ( sysclk : in STD_LOGIC;
reset : in STD_LOGIC;
data : in STD_LOGIC_VECTOR (7 downto 0);
data_dv : in STD_LOGIC;
data_end : in STD_LOGIC;
data_err : in STD_LOGIC;
audio : out STD_LOGIC_VECTOR (23 downto 0);
audio_dv : out STD_LOGIC;
debug: out std_logic_vector(7 downto 0)
);
END COMPONENT;
COMPONENT deltasigmadac
PORT(
sysclk : IN std_logic;
reset : IN std_logic;
audio : IN std_logic_vector(23 downto 0);
audio_dv : IN std_logic;
audio_left : OUT std_logic;
audio_right : OUT std_logic;
rate_pulse:out std_logic;
debug: out std_logic_vector(7 downto 0)
);
END COMPONENT;
component clocking is
Port (
clk_in : in std_logic;
rst : in std_logic;
clk1x : out std_logic;
clk_div : out std_logic;
lock : out std_logic
);
end component;
--Signals for clock and reset logic. lock comes when the DCM thinks it is stable
signal sysclk, lock, nreset, reset:std_logic;
signal e_mdc_s:std_logic:='0';
signal miim_addr:std_logic_vector(4 downto 0):=(OTHERS => '0');
signal miim_data_i, miim_data_o:std_logic_vector(15 downto 0):=(OTHERS => '0');
signal miim_data_i_e, miim_data_o_e, miim_busy:std_logic:='0';
signal rx_data_o:std_logic_vector(7 downto 0):=(OTHERS => '0');
signal rx_data_v, rx_frame_end, rx_frame_err:std_logic:='0';
signal audio:std_logic_vector(23 downto 0);
signal audio_dv,rate_pulse:std_logic;
signal ctrl_data:std_logic_vector(7 downto 0):=(OTHERS => '0');
signal ctrl_data_v:std_logic:='0';
signal edata_o:std_logic_vector(7 downto 0);
signal edata_o_v, edata_o_req:std_logic;
begin
e_mdc <= e_mdc_s;
reset <= not lock or btn_south;-- or btn_south;
nreset <= not reset;
e_nrst <= nreset;
clocking_inst : clocking port map (
clk_in => clk_50m,
rst => btn_south,
clk1x => sysclk,
clk_div => open,
lock => lock
);
miim_inst : miim generic map(
DIVISOR => 21,--50000,
PHYADDR => "00000"
) port map (
sysclk => sysclk,
reset => reset,
addr => miim_addr,
data_i => miim_data_i,
data_i_e => miim_data_i_e,
data_o => miim_data_o,
data_o_e => miim_data_o_e,
busy => miim_busy,
miim_clk => e_mdc_s,
miim_d => e_mdio
);
rxsyncer : rxsync port map (
sysclk => sysclk,
reset => reset,
rx_clk => e_rx_clk,
rxd => e_rxd,
rx_dv => e_rx_dv,
--phy_rx_err : in std_logic;
data => rx_data_o,
data_dv => rx_data_v,
data_end => rx_frame_end,
data_err => rx_frame_err,
debug => open
);
rxdecoder:rxdecode PORT MAP (
sysclk => sysclk,
reset => reset,
data => rx_data_o,
data_dv => rx_data_v,
data_end => rx_frame_end,
data_err => rx_frame_err,
audio => audio,
audio_dv => audio_dv,
debug => open
);
phy_ctrl_inst : phy_ctrl port map (
sysclk => sysclk,
reset => reset,
data_i => ctrl_data,
data_i_v => ctrl_data_v,
miim_addr => miim_addr,
miim_data_i => miim_data_i,
miim_data_i_e => miim_data_i_e,
miim_data_o => miim_data_o,
miim_data_o_e => miim_data_o_e,
miim_busy => miim_busy
);
dac: deltasigmadac PORT MAP (
sysclk => sysclk,
reset => reset,
audio => audio,
audio_dv => audio_dv,
audio_left => aud_l,
audio_right => aud_r,
rate_pulse => rate_pulse,
debug => open
);
txsyncer:txsync port map (
sysclk => sysclk,
reset => reset,
tx_clk => e_tx_clk,
txd => e_txd,
tx_dv => e_tx_en,
data => edata_o,
data_send => edata_o_v,
data_req => edata_o_req,
debug => led
);
gen: packetgen port map (
sysclk => sysclk,
reset => reset,
rate_pulse => rate_pulse,
edata_o => edata_o,
edata_o_v => edata_o_v,
edata_o_req => edata_o_req,
debug => open
);
end Behavioral;
| gpl-3.0 | 30c126f46543c0521d9c07131ca3c1a0 | 0.578592 | 2.91127 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/xilinx/lib/src/dpRamSplx-rtl-a.vhd | 2 | 6,906 | --! @file dpRamSplx-rtl-a.vhd
--
--! @brief Simplex Dual Port Ram Register Transfer Level Architecture
--
--! @details This is the Simplex DPRAM intended for synthesis on Xilinx
--! platforms only.
--! Timing as follows [clk-cycles]: write=0 / read=1
--
-------------------------------------------------------------------------------
-- Architecture : rtl
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
--! use global library
use work.global.all;
architecture rtl of dpRamSplx is
--! Width configuration type
type tWidthConfig is (
sUnsupported,
sAsym_16_32,
sAsym_32_16,
sSym
);
--! Function to return width configuration.
function getWidthConfig (
wordWidthA : natural;
byteEnableWidthA : natural;
wordWidthB : natural
) return tWidthConfig is
begin
if wordWidthA = 16 and wordWidthB = 32 and byteEnableWidthA = 2 then
return sAsym_16_32;
elsif wordWidthA = 32 and wordWidthB = 16 and byteEnableWidthA = 4 then
return sAsym_32_16;
elsif wordWidthA = wordWidthB and byteEnableWidthA = wordWidthA/cByteLength then
return sSym;
else
return sUnsupported;
end if;
end function;
--! Width configuration
constant cWidthConfig : tWidthConfig := getWidthConfig(gWordWidthA, gByteenableWidthA, gWordWidthB);
--! Words of dpram
constant cDprWords : natural := minimum(gNumberOfWordsA, gNumberOfWordsB);
--! Word width of dpram
constant cDprWordWidth : natural := maximum(gWordWidthA, gWordWidthB);
--! Dpr write port address
signal writeAddress : std_logic_vector(logDualis(cDprWords)-1 downto 0);
--! Dpr write port enables
signal writeByteenable : std_logic_vector(cDprWordWidth/cByteLength-1 downto 0);
--! Dpr write port
signal writedata : std_logic_vector(cDprWordWidth-1 downto 0);
--! Dpr read port address
signal readAddress : std_logic_vector(logDualis(cDprWords)-1 downto 0);
--! Dpr read port
signal readdata : std_logic_vector(cDprWordWidth-1 downto 0);
begin
assert (cWidthConfig /= sUnsupported)
report "The width configuration is not supported!"
severity failure;
assert (gInitFile = "UNUSED")
report "Memory initialization is not supported in this architecture!"
severity warning;
assert (gWordWidthA*gNumberOfWordsA = gWordWidthB*gNumberOfWordsB)
report "Memory size of port A and B are different!"
severity failure;
--! Instantiate true dual ported ram entity
TRUEDPRAM : entity work.dpRam
generic map (
gWordWidth => cDprWordWidth,
gNumberOfWords => cDprWords,
gInitFile => "unused"
)
port map (
iClk_A => iClk_A,
iEnable_A => iEnable_A,
iWriteEnable_A => iWriteEnable_A,
iAddress_A => writeAddress,
iByteenable_A => writeByteenable,
iWritedata_A => writedata,
oReaddata_A => open,
iClk_B => iClk_B,
iEnable_B => iEnable_B,
iWriteEnable_B => cInactivated,
iByteenable_B => (others => cInactivated),
iAddress_B => readAddress,
iWritedata_B => (others => cInactivated),
oReaddata_B => readdata
);
--! This generate block assigns the 16 bit write port and
--! the 32 bit read port.
WIDTHCFG_16_32 : if cWidthConfig = sAsym_16_32 generate
writeAddress <= iAddress_A(iAddress_A'left downto 1);
writeByteenable(3) <= iByteenable_A(1) and iAddress_A(0);
writeByteenable(2) <= iByteenable_A(0) and iAddress_A(0);
writeByteenable(1) <= iByteenable_A(1) and not iAddress_A(0);
writeByteenable(0) <= iByteenable_A(0) and not iAddress_A(0);
writedata <= iWritedata_A & iWritedata_A;
readAddress <= iAddress_B;
oReaddata_B <= readdata;
end generate WIDTHCFG_16_32;
--! This generate block assigns the 32 bit write port and
--! the 16 bit read port.
WIDTHCFG_32_16 : if cWidthConfig = sAsym_32_16 generate
writeAddress <= iAddress_A;
writeByteenable <= iByteenable_A;
writedata <= iWritedata_A;
readAddress <= iAddress_B(iAddress_B'left downto 1);
oReaddata_B <= readdata(31 downto 16) when iAddress_B(0) = cActivated else
readdata(15 downto 0);
end generate WIDTHCFG_32_16;
--! This generate block assigns the symmetric write and read ports.
WIDTHCFG_SYM : if cWidthConfig = sSym generate
writeAddress <= iAddress_A;
writeByteenable <= iByteenable_A;
writedata <= iWritedata_A;
readAddress <= iAddress_B;
oReaddata_B <= readdata;
end generate WIDTHCFG_SYM;
end architecture rtl;
| gpl-2.0 | 0183884c1373ead912d405d9b96088e1 | 0.618593 | 4.59481 | false | true | false | false |
hoglet67/AtomGodilVideo | src/MC6847/mc6847_ntsc.vhd | 2 | 48,451 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mc6847_ntsc is
port (
CLK : in std_logic;
ADDR : in std_logic_vector(10 downto 0);
DATA : out std_logic_vector(7 downto 0)
);
end;
architecture RTL of mc6847_ntsc is
signal rom_addr : std_logic_vector(9 downto 0);
begin
p_addr : process(ADDR)
begin
rom_addr <= (others => '0');
rom_addr(9 downto 0) <= ADDR(9 downto 0);
end process;
p_rom : process
begin
wait until rising_edge(CLK);
DATA <= (others => '0');
if rom_addr(9 downto 8) = "00" then
case rom_addr(7 downto 0) is
when x"00" => DATA <= x"00";
when x"01" => DATA <= x"00";
when x"02" => DATA <= x"00";
when x"03" => DATA <= x"1C";
when x"04" => DATA <= x"22";
when x"05" => DATA <= x"02";
when x"06" => DATA <= x"1A";
when x"07" => DATA <= x"2A";
when x"08" => DATA <= x"2A";
when x"09" => DATA <= x"1C";
when x"0A" => DATA <= x"00";
when x"0B" => DATA <= x"00";
when x"0C" => DATA <= x"00";
when x"0D" => DATA <= x"00";
when x"0E" => DATA <= x"00";
when x"0F" => DATA <= x"00";
when x"10" => DATA <= x"00";
when x"11" => DATA <= x"00";
when x"12" => DATA <= x"00";
when x"13" => DATA <= x"08";
when x"14" => DATA <= x"14";
when x"15" => DATA <= x"22";
when x"16" => DATA <= x"22";
when x"17" => DATA <= x"3E";
when x"18" => DATA <= x"22";
when x"19" => DATA <= x"22";
when x"1A" => DATA <= x"00";
when x"1B" => DATA <= x"00";
when x"1C" => DATA <= x"00";
when x"1D" => DATA <= x"00";
when x"1E" => DATA <= x"00";
when x"1F" => DATA <= x"00";
when x"20" => DATA <= x"00";
when x"21" => DATA <= x"00";
when x"22" => DATA <= x"00";
when x"23" => DATA <= x"3C";
when x"24" => DATA <= x"12";
when x"25" => DATA <= x"12";
when x"26" => DATA <= x"1C";
when x"27" => DATA <= x"12";
when x"28" => DATA <= x"12";
when x"29" => DATA <= x"3C";
when x"2A" => DATA <= x"00";
when x"2B" => DATA <= x"00";
when x"2C" => DATA <= x"00";
when x"2D" => DATA <= x"00";
when x"2E" => DATA <= x"00";
when x"2F" => DATA <= x"00";
when x"30" => DATA <= x"00";
when x"31" => DATA <= x"00";
when x"32" => DATA <= x"00";
when x"33" => DATA <= x"1C";
when x"34" => DATA <= x"22";
when x"35" => DATA <= x"20";
when x"36" => DATA <= x"20";
when x"37" => DATA <= x"20";
when x"38" => DATA <= x"22";
when x"39" => DATA <= x"1C";
when x"3A" => DATA <= x"00";
when x"3B" => DATA <= x"00";
when x"3C" => DATA <= x"00";
when x"3D" => DATA <= x"00";
when x"3E" => DATA <= x"00";
when x"3F" => DATA <= x"00";
when x"40" => DATA <= x"00";
when x"41" => DATA <= x"00";
when x"42" => DATA <= x"00";
when x"43" => DATA <= x"3C";
when x"44" => DATA <= x"12";
when x"45" => DATA <= x"12";
when x"46" => DATA <= x"12";
when x"47" => DATA <= x"12";
when x"48" => DATA <= x"12";
when x"49" => DATA <= x"3C";
when x"4A" => DATA <= x"00";
when x"4B" => DATA <= x"00";
when x"4C" => DATA <= x"00";
when x"4D" => DATA <= x"00";
when x"4E" => DATA <= x"00";
when x"4F" => DATA <= x"00";
when x"50" => DATA <= x"00";
when x"51" => DATA <= x"00";
when x"52" => DATA <= x"00";
when x"53" => DATA <= x"3E";
when x"54" => DATA <= x"20";
when x"55" => DATA <= x"20";
when x"56" => DATA <= x"38";
when x"57" => DATA <= x"20";
when x"58" => DATA <= x"20";
when x"59" => DATA <= x"3E";
when x"5A" => DATA <= x"00";
when x"5B" => DATA <= x"00";
when x"5C" => DATA <= x"00";
when x"5D" => DATA <= x"00";
when x"5E" => DATA <= x"00";
when x"5F" => DATA <= x"00";
when x"60" => DATA <= x"00";
when x"61" => DATA <= x"00";
when x"62" => DATA <= x"00";
when x"63" => DATA <= x"3E";
when x"64" => DATA <= x"20";
when x"65" => DATA <= x"20";
when x"66" => DATA <= x"38";
when x"67" => DATA <= x"20";
when x"68" => DATA <= x"20";
when x"69" => DATA <= x"20";
when x"6A" => DATA <= x"00";
when x"6B" => DATA <= x"00";
when x"6C" => DATA <= x"00";
when x"6D" => DATA <= x"00";
when x"6E" => DATA <= x"00";
when x"6F" => DATA <= x"00";
when x"70" => DATA <= x"00";
when x"71" => DATA <= x"00";
when x"72" => DATA <= x"00";
when x"73" => DATA <= x"1E";
when x"74" => DATA <= x"20";
when x"75" => DATA <= x"20";
when x"76" => DATA <= x"26";
when x"77" => DATA <= x"22";
when x"78" => DATA <= x"22";
when x"79" => DATA <= x"1E";
when x"7A" => DATA <= x"00";
when x"7B" => DATA <= x"00";
when x"7C" => DATA <= x"00";
when x"7D" => DATA <= x"00";
when x"7E" => DATA <= x"00";
when x"7F" => DATA <= x"00";
when x"80" => DATA <= x"00";
when x"81" => DATA <= x"00";
when x"82" => DATA <= x"00";
when x"83" => DATA <= x"22";
when x"84" => DATA <= x"22";
when x"85" => DATA <= x"22";
when x"86" => DATA <= x"3E";
when x"87" => DATA <= x"22";
when x"88" => DATA <= x"22";
when x"89" => DATA <= x"22";
when x"8A" => DATA <= x"00";
when x"8B" => DATA <= x"00";
when x"8C" => DATA <= x"00";
when x"8D" => DATA <= x"00";
when x"8E" => DATA <= x"00";
when x"8F" => DATA <= x"00";
when x"90" => DATA <= x"00";
when x"91" => DATA <= x"00";
when x"92" => DATA <= x"00";
when x"93" => DATA <= x"1C";
when x"94" => DATA <= x"08";
when x"95" => DATA <= x"08";
when x"96" => DATA <= x"08";
when x"97" => DATA <= x"08";
when x"98" => DATA <= x"08";
when x"99" => DATA <= x"1C";
when x"9A" => DATA <= x"00";
when x"9B" => DATA <= x"00";
when x"9C" => DATA <= x"00";
when x"9D" => DATA <= x"00";
when x"9E" => DATA <= x"00";
when x"9F" => DATA <= x"00";
when x"A0" => DATA <= x"00";
when x"A1" => DATA <= x"00";
when x"A2" => DATA <= x"00";
when x"A3" => DATA <= x"02";
when x"A4" => DATA <= x"02";
when x"A5" => DATA <= x"02";
when x"A6" => DATA <= x"02";
when x"A7" => DATA <= x"22";
when x"A8" => DATA <= x"22";
when x"A9" => DATA <= x"1C";
when x"AA" => DATA <= x"00";
when x"AB" => DATA <= x"00";
when x"AC" => DATA <= x"00";
when x"AD" => DATA <= x"00";
when x"AE" => DATA <= x"00";
when x"AF" => DATA <= x"00";
when x"B0" => DATA <= x"00";
when x"B1" => DATA <= x"00";
when x"B2" => DATA <= x"00";
when x"B3" => DATA <= x"22";
when x"B4" => DATA <= x"24";
when x"B5" => DATA <= x"28";
when x"B6" => DATA <= x"30";
when x"B7" => DATA <= x"28";
when x"B8" => DATA <= x"24";
when x"B9" => DATA <= x"22";
when x"BA" => DATA <= x"00";
when x"BB" => DATA <= x"00";
when x"BC" => DATA <= x"00";
when x"BD" => DATA <= x"00";
when x"BE" => DATA <= x"00";
when x"BF" => DATA <= x"00";
when x"C0" => DATA <= x"00";
when x"C1" => DATA <= x"00";
when x"C2" => DATA <= x"00";
when x"C3" => DATA <= x"20";
when x"C4" => DATA <= x"20";
when x"C5" => DATA <= x"20";
when x"C6" => DATA <= x"20";
when x"C7" => DATA <= x"20";
when x"C8" => DATA <= x"20";
when x"C9" => DATA <= x"3E";
when x"CA" => DATA <= x"00";
when x"CB" => DATA <= x"00";
when x"CC" => DATA <= x"00";
when x"CD" => DATA <= x"00";
when x"CE" => DATA <= x"00";
when x"CF" => DATA <= x"00";
when x"D0" => DATA <= x"00";
when x"D1" => DATA <= x"00";
when x"D2" => DATA <= x"00";
when x"D3" => DATA <= x"22";
when x"D4" => DATA <= x"36";
when x"D5" => DATA <= x"2A";
when x"D6" => DATA <= x"2A";
when x"D7" => DATA <= x"22";
when x"D8" => DATA <= x"22";
when x"D9" => DATA <= x"22";
when x"DA" => DATA <= x"00";
when x"DB" => DATA <= x"00";
when x"DC" => DATA <= x"00";
when x"DD" => DATA <= x"00";
when x"DE" => DATA <= x"00";
when x"DF" => DATA <= x"00";
when x"E0" => DATA <= x"00";
when x"E1" => DATA <= x"00";
when x"E2" => DATA <= x"00";
when x"E3" => DATA <= x"22";
when x"E4" => DATA <= x"32";
when x"E5" => DATA <= x"2A";
when x"E6" => DATA <= x"26";
when x"E7" => DATA <= x"22";
when x"E8" => DATA <= x"22";
when x"E9" => DATA <= x"22";
when x"EA" => DATA <= x"00";
when x"EB" => DATA <= x"00";
when x"EC" => DATA <= x"00";
when x"ED" => DATA <= x"00";
when x"EE" => DATA <= x"00";
when x"EF" => DATA <= x"00";
when x"F0" => DATA <= x"00";
when x"F1" => DATA <= x"00";
when x"F2" => DATA <= x"00";
when x"F3" => DATA <= x"3E";
when x"F4" => DATA <= x"22";
when x"F5" => DATA <= x"22";
when x"F6" => DATA <= x"22";
when x"F7" => DATA <= x"22";
when x"F8" => DATA <= x"22";
when x"F9" => DATA <= x"3E";
when x"FA" => DATA <= x"00";
when x"FB" => DATA <= x"00";
when x"FC" => DATA <= x"00";
when x"FD" => DATA <= x"00";
when x"FE" => DATA <= x"00";
when x"FF" => DATA <= x"00";
when others => DATA <= (others => '0');
end case;
end if;
if rom_addr(9 downto 8) = "01" then
case rom_addr(7 downto 0) is
when x"00" => DATA <= x"00";
when x"01" => DATA <= x"00";
when x"02" => DATA <= x"00";
when x"03" => DATA <= x"3C";
when x"04" => DATA <= x"22";
when x"05" => DATA <= x"22";
when x"06" => DATA <= x"3C";
when x"07" => DATA <= x"20";
when x"08" => DATA <= x"20";
when x"09" => DATA <= x"20";
when x"0A" => DATA <= x"00";
when x"0B" => DATA <= x"00";
when x"0C" => DATA <= x"00";
when x"0D" => DATA <= x"00";
when x"0E" => DATA <= x"00";
when x"0F" => DATA <= x"00";
when x"10" => DATA <= x"00";
when x"11" => DATA <= x"00";
when x"12" => DATA <= x"00";
when x"13" => DATA <= x"1C";
when x"14" => DATA <= x"22";
when x"15" => DATA <= x"22";
when x"16" => DATA <= x"22";
when x"17" => DATA <= x"2A";
when x"18" => DATA <= x"24";
when x"19" => DATA <= x"1A";
when x"1A" => DATA <= x"00";
when x"1B" => DATA <= x"00";
when x"1C" => DATA <= x"00";
when x"1D" => DATA <= x"00";
when x"1E" => DATA <= x"00";
when x"1F" => DATA <= x"00";
when x"20" => DATA <= x"00";
when x"21" => DATA <= x"00";
when x"22" => DATA <= x"00";
when x"23" => DATA <= x"3C";
when x"24" => DATA <= x"22";
when x"25" => DATA <= x"22";
when x"26" => DATA <= x"3C";
when x"27" => DATA <= x"28";
when x"28" => DATA <= x"24";
when x"29" => DATA <= x"22";
when x"2A" => DATA <= x"00";
when x"2B" => DATA <= x"00";
when x"2C" => DATA <= x"00";
when x"2D" => DATA <= x"00";
when x"2E" => DATA <= x"00";
when x"2F" => DATA <= x"00";
when x"30" => DATA <= x"00";
when x"31" => DATA <= x"00";
when x"32" => DATA <= x"00";
when x"33" => DATA <= x"1C";
when x"34" => DATA <= x"22";
when x"35" => DATA <= x"10";
when x"36" => DATA <= x"08";
when x"37" => DATA <= x"04";
when x"38" => DATA <= x"22";
when x"39" => DATA <= x"1C";
when x"3A" => DATA <= x"00";
when x"3B" => DATA <= x"00";
when x"3C" => DATA <= x"00";
when x"3D" => DATA <= x"00";
when x"3E" => DATA <= x"00";
when x"3F" => DATA <= x"00";
when x"40" => DATA <= x"00";
when x"41" => DATA <= x"00";
when x"42" => DATA <= x"00";
when x"43" => DATA <= x"3E";
when x"44" => DATA <= x"08";
when x"45" => DATA <= x"08";
when x"46" => DATA <= x"08";
when x"47" => DATA <= x"08";
when x"48" => DATA <= x"08";
when x"49" => DATA <= x"08";
when x"4A" => DATA <= x"00";
when x"4B" => DATA <= x"00";
when x"4C" => DATA <= x"00";
when x"4D" => DATA <= x"00";
when x"4E" => DATA <= x"00";
when x"4F" => DATA <= x"00";
when x"50" => DATA <= x"00";
when x"51" => DATA <= x"00";
when x"52" => DATA <= x"00";
when x"53" => DATA <= x"22";
when x"54" => DATA <= x"22";
when x"55" => DATA <= x"22";
when x"56" => DATA <= x"22";
when x"57" => DATA <= x"22";
when x"58" => DATA <= x"22";
when x"59" => DATA <= x"1C";
when x"5A" => DATA <= x"00";
when x"5B" => DATA <= x"00";
when x"5C" => DATA <= x"00";
when x"5D" => DATA <= x"00";
when x"5E" => DATA <= x"00";
when x"5F" => DATA <= x"00";
when x"60" => DATA <= x"00";
when x"61" => DATA <= x"00";
when x"62" => DATA <= x"00";
when x"63" => DATA <= x"22";
when x"64" => DATA <= x"22";
when x"65" => DATA <= x"22";
when x"66" => DATA <= x"14";
when x"67" => DATA <= x"14";
when x"68" => DATA <= x"08";
when x"69" => DATA <= x"08";
when x"6A" => DATA <= x"00";
when x"6B" => DATA <= x"00";
when x"6C" => DATA <= x"00";
when x"6D" => DATA <= x"00";
when x"6E" => DATA <= x"00";
when x"6F" => DATA <= x"00";
when x"70" => DATA <= x"00";
when x"71" => DATA <= x"00";
when x"72" => DATA <= x"00";
when x"73" => DATA <= x"22";
when x"74" => DATA <= x"22";
when x"75" => DATA <= x"22";
when x"76" => DATA <= x"2A";
when x"77" => DATA <= x"2A";
when x"78" => DATA <= x"36";
when x"79" => DATA <= x"22";
when x"7A" => DATA <= x"00";
when x"7B" => DATA <= x"00";
when x"7C" => DATA <= x"00";
when x"7D" => DATA <= x"00";
when x"7E" => DATA <= x"00";
when x"7F" => DATA <= x"00";
when x"80" => DATA <= x"00";
when x"81" => DATA <= x"00";
when x"82" => DATA <= x"00";
when x"83" => DATA <= x"22";
when x"84" => DATA <= x"22";
when x"85" => DATA <= x"14";
when x"86" => DATA <= x"08";
when x"87" => DATA <= x"14";
when x"88" => DATA <= x"22";
when x"89" => DATA <= x"22";
when x"8A" => DATA <= x"00";
when x"8B" => DATA <= x"00";
when x"8C" => DATA <= x"00";
when x"8D" => DATA <= x"00";
when x"8E" => DATA <= x"00";
when x"8F" => DATA <= x"00";
when x"90" => DATA <= x"00";
when x"91" => DATA <= x"00";
when x"92" => DATA <= x"00";
when x"93" => DATA <= x"22";
when x"94" => DATA <= x"22";
when x"95" => DATA <= x"14";
when x"96" => DATA <= x"08";
when x"97" => DATA <= x"08";
when x"98" => DATA <= x"08";
when x"99" => DATA <= x"08";
when x"9A" => DATA <= x"00";
when x"9B" => DATA <= x"00";
when x"9C" => DATA <= x"00";
when x"9D" => DATA <= x"00";
when x"9E" => DATA <= x"00";
when x"9F" => DATA <= x"00";
when x"A0" => DATA <= x"00";
when x"A1" => DATA <= x"00";
when x"A2" => DATA <= x"00";
when x"A3" => DATA <= x"3E";
when x"A4" => DATA <= x"02";
when x"A5" => DATA <= x"04";
when x"A6" => DATA <= x"08";
when x"A7" => DATA <= x"10";
when x"A8" => DATA <= x"20";
when x"A9" => DATA <= x"3E";
when x"AA" => DATA <= x"00";
when x"AB" => DATA <= x"00";
when x"AC" => DATA <= x"00";
when x"AD" => DATA <= x"00";
when x"AE" => DATA <= x"00";
when x"AF" => DATA <= x"00";
when x"B0" => DATA <= x"00";
when x"B1" => DATA <= x"00";
when x"B2" => DATA <= x"00";
when x"B3" => DATA <= x"38";
when x"B4" => DATA <= x"20";
when x"B5" => DATA <= x"20";
when x"B6" => DATA <= x"20";
when x"B7" => DATA <= x"20";
when x"B8" => DATA <= x"20";
when x"B9" => DATA <= x"38";
when x"BA" => DATA <= x"00";
when x"BB" => DATA <= x"00";
when x"BC" => DATA <= x"00";
when x"BD" => DATA <= x"00";
when x"BE" => DATA <= x"00";
when x"BF" => DATA <= x"00";
when x"C0" => DATA <= x"00";
when x"C1" => DATA <= x"00";
when x"C2" => DATA <= x"00";
when x"C3" => DATA <= x"20";
when x"C4" => DATA <= x"20";
when x"C5" => DATA <= x"10";
when x"C6" => DATA <= x"08";
when x"C7" => DATA <= x"04";
when x"C8" => DATA <= x"02";
when x"C9" => DATA <= x"02";
when x"CA" => DATA <= x"00";
when x"CB" => DATA <= x"00";
when x"CC" => DATA <= x"00";
when x"CD" => DATA <= x"00";
when x"CE" => DATA <= x"00";
when x"CF" => DATA <= x"00";
when x"D0" => DATA <= x"00";
when x"D1" => DATA <= x"00";
when x"D2" => DATA <= x"00";
when x"D3" => DATA <= x"0E";
when x"D4" => DATA <= x"02";
when x"D5" => DATA <= x"02";
when x"D6" => DATA <= x"02";
when x"D7" => DATA <= x"02";
when x"D8" => DATA <= x"02";
when x"D9" => DATA <= x"0E";
when x"DA" => DATA <= x"00";
when x"DB" => DATA <= x"00";
when x"DC" => DATA <= x"00";
when x"DD" => DATA <= x"00";
when x"DE" => DATA <= x"00";
when x"DF" => DATA <= x"00";
when x"E0" => DATA <= x"00";
when x"E1" => DATA <= x"00";
when x"E2" => DATA <= x"00";
when x"E3" => DATA <= x"08";
when x"E4" => DATA <= x"1C";
when x"E5" => DATA <= x"2A";
when x"E6" => DATA <= x"08";
when x"E7" => DATA <= x"08";
when x"E8" => DATA <= x"08";
when x"E9" => DATA <= x"08";
when x"EA" => DATA <= x"00";
when x"EB" => DATA <= x"00";
when x"EC" => DATA <= x"00";
when x"ED" => DATA <= x"00";
when x"EE" => DATA <= x"00";
when x"EF" => DATA <= x"00";
when x"F0" => DATA <= x"00";
when x"F1" => DATA <= x"00";
when x"F2" => DATA <= x"00";
when x"F3" => DATA <= x"00";
when x"F4" => DATA <= x"08";
when x"F5" => DATA <= x"10";
when x"F6" => DATA <= x"3E";
when x"F7" => DATA <= x"10";
when x"F8" => DATA <= x"08";
when x"F9" => DATA <= x"00";
when x"FA" => DATA <= x"00";
when x"FB" => DATA <= x"00";
when x"FC" => DATA <= x"00";
when x"FD" => DATA <= x"00";
when x"FE" => DATA <= x"00";
when x"FF" => DATA <= x"00";
when others => DATA <= (others => '0');
end case;
end if;
if rom_addr(9 downto 8) = "10" then
case rom_addr(7 downto 0) is
when x"00" => DATA <= x"00";
when x"01" => DATA <= x"00";
when x"02" => DATA <= x"00";
when x"03" => DATA <= x"00";
when x"04" => DATA <= x"00";
when x"05" => DATA <= x"00";
when x"06" => DATA <= x"00";
when x"07" => DATA <= x"00";
when x"08" => DATA <= x"00";
when x"09" => DATA <= x"00";
when x"0A" => DATA <= x"00";
when x"0B" => DATA <= x"00";
when x"0C" => DATA <= x"00";
when x"0D" => DATA <= x"00";
when x"0E" => DATA <= x"00";
when x"0F" => DATA <= x"00";
when x"10" => DATA <= x"00";
when x"11" => DATA <= x"00";
when x"12" => DATA <= x"00";
when x"13" => DATA <= x"08";
when x"14" => DATA <= x"08";
when x"15" => DATA <= x"08";
when x"16" => DATA <= x"08";
when x"17" => DATA <= x"08";
when x"18" => DATA <= x"00";
when x"19" => DATA <= x"08";
when x"1A" => DATA <= x"00";
when x"1B" => DATA <= x"00";
when x"1C" => DATA <= x"00";
when x"1D" => DATA <= x"00";
when x"1E" => DATA <= x"00";
when x"1F" => DATA <= x"00";
when x"20" => DATA <= x"00";
when x"21" => DATA <= x"00";
when x"22" => DATA <= x"00";
when x"23" => DATA <= x"14";
when x"24" => DATA <= x"14";
when x"25" => DATA <= x"14";
when x"26" => DATA <= x"00";
when x"27" => DATA <= x"00";
when x"28" => DATA <= x"00";
when x"29" => DATA <= x"00";
when x"2A" => DATA <= x"00";
when x"2B" => DATA <= x"00";
when x"2C" => DATA <= x"00";
when x"2D" => DATA <= x"00";
when x"2E" => DATA <= x"00";
when x"2F" => DATA <= x"00";
when x"30" => DATA <= x"00";
when x"31" => DATA <= x"00";
when x"32" => DATA <= x"00";
when x"33" => DATA <= x"14";
when x"34" => DATA <= x"14";
when x"35" => DATA <= x"36";
when x"36" => DATA <= x"00";
when x"37" => DATA <= x"36";
when x"38" => DATA <= x"14";
when x"39" => DATA <= x"14";
when x"3A" => DATA <= x"00";
when x"3B" => DATA <= x"00";
when x"3C" => DATA <= x"00";
when x"3D" => DATA <= x"00";
when x"3E" => DATA <= x"00";
when x"3F" => DATA <= x"00";
when x"40" => DATA <= x"00";
when x"41" => DATA <= x"00";
when x"42" => DATA <= x"00";
when x"43" => DATA <= x"08";
when x"44" => DATA <= x"1E";
when x"45" => DATA <= x"20";
when x"46" => DATA <= x"1C";
when x"47" => DATA <= x"02";
when x"48" => DATA <= x"3C";
when x"49" => DATA <= x"08";
when x"4A" => DATA <= x"00";
when x"4B" => DATA <= x"00";
when x"4C" => DATA <= x"00";
when x"4D" => DATA <= x"00";
when x"4E" => DATA <= x"00";
when x"4F" => DATA <= x"00";
when x"50" => DATA <= x"00";
when x"51" => DATA <= x"00";
when x"52" => DATA <= x"00";
when x"53" => DATA <= x"32";
when x"54" => DATA <= x"32";
when x"55" => DATA <= x"04";
when x"56" => DATA <= x"08";
when x"57" => DATA <= x"10";
when x"58" => DATA <= x"26";
when x"59" => DATA <= x"26";
when x"5A" => DATA <= x"00";
when x"5B" => DATA <= x"00";
when x"5C" => DATA <= x"00";
when x"5D" => DATA <= x"00";
when x"5E" => DATA <= x"00";
when x"5F" => DATA <= x"00";
when x"60" => DATA <= x"00";
when x"61" => DATA <= x"00";
when x"62" => DATA <= x"00";
when x"63" => DATA <= x"10";
when x"64" => DATA <= x"28";
when x"65" => DATA <= x"28";
when x"66" => DATA <= x"10";
when x"67" => DATA <= x"2A";
when x"68" => DATA <= x"24";
when x"69" => DATA <= x"1A";
when x"6A" => DATA <= x"00";
when x"6B" => DATA <= x"00";
when x"6C" => DATA <= x"00";
when x"6D" => DATA <= x"00";
when x"6E" => DATA <= x"00";
when x"6F" => DATA <= x"00";
when x"70" => DATA <= x"00";
when x"71" => DATA <= x"00";
when x"72" => DATA <= x"00";
when x"73" => DATA <= x"18";
when x"74" => DATA <= x"18";
when x"75" => DATA <= x"18";
when x"76" => DATA <= x"00";
when x"77" => DATA <= x"00";
when x"78" => DATA <= x"00";
when x"79" => DATA <= x"00";
when x"7A" => DATA <= x"00";
when x"7B" => DATA <= x"00";
when x"7C" => DATA <= x"00";
when x"7D" => DATA <= x"00";
when x"7E" => DATA <= x"00";
when x"7F" => DATA <= x"00";
when x"80" => DATA <= x"00";
when x"81" => DATA <= x"00";
when x"82" => DATA <= x"00";
when x"83" => DATA <= x"08";
when x"84" => DATA <= x"10";
when x"85" => DATA <= x"20";
when x"86" => DATA <= x"20";
when x"87" => DATA <= x"20";
when x"88" => DATA <= x"10";
when x"89" => DATA <= x"08";
when x"8A" => DATA <= x"00";
when x"8B" => DATA <= x"00";
when x"8C" => DATA <= x"00";
when x"8D" => DATA <= x"00";
when x"8E" => DATA <= x"00";
when x"8F" => DATA <= x"00";
when x"90" => DATA <= x"00";
when x"91" => DATA <= x"00";
when x"92" => DATA <= x"00";
when x"93" => DATA <= x"08";
when x"94" => DATA <= x"04";
when x"95" => DATA <= x"02";
when x"96" => DATA <= x"02";
when x"97" => DATA <= x"02";
when x"98" => DATA <= x"04";
when x"99" => DATA <= x"08";
when x"9A" => DATA <= x"00";
when x"9B" => DATA <= x"00";
when x"9C" => DATA <= x"00";
when x"9D" => DATA <= x"00";
when x"9E" => DATA <= x"00";
when x"9F" => DATA <= x"00";
when x"A0" => DATA <= x"00";
when x"A1" => DATA <= x"00";
when x"A2" => DATA <= x"00";
when x"A3" => DATA <= x"00";
when x"A4" => DATA <= x"08";
when x"A5" => DATA <= x"1C";
when x"A6" => DATA <= x"3E";
when x"A7" => DATA <= x"1C";
when x"A8" => DATA <= x"08";
when x"A9" => DATA <= x"00";
when x"AA" => DATA <= x"00";
when x"AB" => DATA <= x"00";
when x"AC" => DATA <= x"00";
when x"AD" => DATA <= x"00";
when x"AE" => DATA <= x"00";
when x"AF" => DATA <= x"00";
when x"B0" => DATA <= x"00";
when x"B1" => DATA <= x"00";
when x"B2" => DATA <= x"00";
when x"B3" => DATA <= x"00";
when x"B4" => DATA <= x"08";
when x"B5" => DATA <= x"08";
when x"B6" => DATA <= x"3E";
when x"B7" => DATA <= x"08";
when x"B8" => DATA <= x"08";
when x"B9" => DATA <= x"00";
when x"BA" => DATA <= x"00";
when x"BB" => DATA <= x"00";
when x"BC" => DATA <= x"00";
when x"BD" => DATA <= x"00";
when x"BE" => DATA <= x"00";
when x"BF" => DATA <= x"00";
when x"C0" => DATA <= x"00";
when x"C1" => DATA <= x"00";
when x"C2" => DATA <= x"00";
when x"C3" => DATA <= x"00";
when x"C4" => DATA <= x"00";
when x"C5" => DATA <= x"00";
when x"C6" => DATA <= x"30";
when x"C7" => DATA <= x"30";
when x"C8" => DATA <= x"10";
when x"C9" => DATA <= x"20";
when x"CA" => DATA <= x"00";
when x"CB" => DATA <= x"00";
when x"CC" => DATA <= x"00";
when x"CD" => DATA <= x"00";
when x"CE" => DATA <= x"00";
when x"CF" => DATA <= x"00";
when x"D0" => DATA <= x"00";
when x"D1" => DATA <= x"00";
when x"D2" => DATA <= x"00";
when x"D3" => DATA <= x"00";
when x"D4" => DATA <= x"00";
when x"D5" => DATA <= x"00";
when x"D6" => DATA <= x"3E";
when x"D7" => DATA <= x"00";
when x"D8" => DATA <= x"00";
when x"D9" => DATA <= x"00";
when x"DA" => DATA <= x"00";
when x"DB" => DATA <= x"00";
when x"DC" => DATA <= x"00";
when x"DD" => DATA <= x"00";
when x"DE" => DATA <= x"00";
when x"DF" => DATA <= x"00";
when x"E0" => DATA <= x"00";
when x"E1" => DATA <= x"00";
when x"E2" => DATA <= x"00";
when x"E3" => DATA <= x"00";
when x"E4" => DATA <= x"00";
when x"E5" => DATA <= x"00";
when x"E6" => DATA <= x"00";
when x"E7" => DATA <= x"00";
when x"E8" => DATA <= x"30";
when x"E9" => DATA <= x"30";
when x"EA" => DATA <= x"00";
when x"EB" => DATA <= x"00";
when x"EC" => DATA <= x"00";
when x"ED" => DATA <= x"00";
when x"EE" => DATA <= x"00";
when x"EF" => DATA <= x"00";
when x"F0" => DATA <= x"00";
when x"F1" => DATA <= x"00";
when x"F2" => DATA <= x"00";
when x"F3" => DATA <= x"02";
when x"F4" => DATA <= x"02";
when x"F5" => DATA <= x"04";
when x"F6" => DATA <= x"08";
when x"F7" => DATA <= x"10";
when x"F8" => DATA <= x"20";
when x"F9" => DATA <= x"20";
when x"FA" => DATA <= x"00";
when x"FB" => DATA <= x"00";
when x"FC" => DATA <= x"00";
when x"FD" => DATA <= x"00";
when x"FE" => DATA <= x"00";
when x"FF" => DATA <= x"00";
when others => DATA <= (others => '0');
end case;
end if;
if rom_addr(9 downto 8) = "11" then
case rom_addr(7 downto 0) is
when x"00" => DATA <= x"00";
when x"01" => DATA <= x"00";
when x"02" => DATA <= x"00";
when x"03" => DATA <= x"18";
when x"04" => DATA <= x"24";
when x"05" => DATA <= x"24";
when x"06" => DATA <= x"24";
when x"07" => DATA <= x"24";
when x"08" => DATA <= x"24";
when x"09" => DATA <= x"18";
when x"0A" => DATA <= x"00";
when x"0B" => DATA <= x"00";
when x"0C" => DATA <= x"00";
when x"0D" => DATA <= x"00";
when x"0E" => DATA <= x"00";
when x"0F" => DATA <= x"00";
when x"10" => DATA <= x"00";
when x"11" => DATA <= x"00";
when x"12" => DATA <= x"00";
when x"13" => DATA <= x"08";
when x"14" => DATA <= x"18";
when x"15" => DATA <= x"08";
when x"16" => DATA <= x"08";
when x"17" => DATA <= x"08";
when x"18" => DATA <= x"08";
when x"19" => DATA <= x"1C";
when x"1A" => DATA <= x"00";
when x"1B" => DATA <= x"00";
when x"1C" => DATA <= x"00";
when x"1D" => DATA <= x"00";
when x"1E" => DATA <= x"00";
when x"1F" => DATA <= x"00";
when x"20" => DATA <= x"00";
when x"21" => DATA <= x"00";
when x"22" => DATA <= x"00";
when x"23" => DATA <= x"1C";
when x"24" => DATA <= x"22";
when x"25" => DATA <= x"02";
when x"26" => DATA <= x"1C";
when x"27" => DATA <= x"20";
when x"28" => DATA <= x"20";
when x"29" => DATA <= x"3E";
when x"2A" => DATA <= x"00";
when x"2B" => DATA <= x"00";
when x"2C" => DATA <= x"00";
when x"2D" => DATA <= x"00";
when x"2E" => DATA <= x"00";
when x"2F" => DATA <= x"00";
when x"30" => DATA <= x"00";
when x"31" => DATA <= x"00";
when x"32" => DATA <= x"00";
when x"33" => DATA <= x"1C";
when x"34" => DATA <= x"22";
when x"35" => DATA <= x"02";
when x"36" => DATA <= x"04";
when x"37" => DATA <= x"02";
when x"38" => DATA <= x"22";
when x"39" => DATA <= x"1C";
when x"3A" => DATA <= x"00";
when x"3B" => DATA <= x"00";
when x"3C" => DATA <= x"00";
when x"3D" => DATA <= x"00";
when x"3E" => DATA <= x"00";
when x"3F" => DATA <= x"00";
when x"40" => DATA <= x"00";
when x"41" => DATA <= x"00";
when x"42" => DATA <= x"00";
when x"43" => DATA <= x"04";
when x"44" => DATA <= x"0C";
when x"45" => DATA <= x"14";
when x"46" => DATA <= x"3E";
when x"47" => DATA <= x"04";
when x"48" => DATA <= x"04";
when x"49" => DATA <= x"04";
when x"4A" => DATA <= x"00";
when x"4B" => DATA <= x"00";
when x"4C" => DATA <= x"00";
when x"4D" => DATA <= x"00";
when x"4E" => DATA <= x"00";
when x"4F" => DATA <= x"00";
when x"50" => DATA <= x"00";
when x"51" => DATA <= x"00";
when x"52" => DATA <= x"00";
when x"53" => DATA <= x"3E";
when x"54" => DATA <= x"20";
when x"55" => DATA <= x"3C";
when x"56" => DATA <= x"02";
when x"57" => DATA <= x"02";
when x"58" => DATA <= x"22";
when x"59" => DATA <= x"1C";
when x"5A" => DATA <= x"00";
when x"5B" => DATA <= x"00";
when x"5C" => DATA <= x"00";
when x"5D" => DATA <= x"00";
when x"5E" => DATA <= x"00";
when x"5F" => DATA <= x"00";
when x"60" => DATA <= x"00";
when x"61" => DATA <= x"00";
when x"62" => DATA <= x"00";
when x"63" => DATA <= x"1C";
when x"64" => DATA <= x"20";
when x"65" => DATA <= x"20";
when x"66" => DATA <= x"3C";
when x"67" => DATA <= x"22";
when x"68" => DATA <= x"22";
when x"69" => DATA <= x"1C";
when x"6A" => DATA <= x"00";
when x"6B" => DATA <= x"00";
when x"6C" => DATA <= x"00";
when x"6D" => DATA <= x"00";
when x"6E" => DATA <= x"00";
when x"6F" => DATA <= x"00";
when x"70" => DATA <= x"00";
when x"71" => DATA <= x"00";
when x"72" => DATA <= x"00";
when x"73" => DATA <= x"3E";
when x"74" => DATA <= x"02";
when x"75" => DATA <= x"04";
when x"76" => DATA <= x"08";
when x"77" => DATA <= x"10";
when x"78" => DATA <= x"20";
when x"79" => DATA <= x"20";
when x"7A" => DATA <= x"00";
when x"7B" => DATA <= x"00";
when x"7C" => DATA <= x"00";
when x"7D" => DATA <= x"00";
when x"7E" => DATA <= x"00";
when x"7F" => DATA <= x"00";
when x"80" => DATA <= x"00";
when x"81" => DATA <= x"00";
when x"82" => DATA <= x"00";
when x"83" => DATA <= x"1C";
when x"84" => DATA <= x"22";
when x"85" => DATA <= x"22";
when x"86" => DATA <= x"1C";
when x"87" => DATA <= x"22";
when x"88" => DATA <= x"22";
when x"89" => DATA <= x"1C";
when x"8A" => DATA <= x"00";
when x"8B" => DATA <= x"00";
when x"8C" => DATA <= x"00";
when x"8D" => DATA <= x"00";
when x"8E" => DATA <= x"00";
when x"8F" => DATA <= x"00";
when x"90" => DATA <= x"00";
when x"91" => DATA <= x"00";
when x"92" => DATA <= x"00";
when x"93" => DATA <= x"1C";
when x"94" => DATA <= x"22";
when x"95" => DATA <= x"22";
when x"96" => DATA <= x"1E";
when x"97" => DATA <= x"02";
when x"98" => DATA <= x"02";
when x"99" => DATA <= x"1C";
when x"9A" => DATA <= x"00";
when x"9B" => DATA <= x"00";
when x"9C" => DATA <= x"00";
when x"9D" => DATA <= x"00";
when x"9E" => DATA <= x"00";
when x"9F" => DATA <= x"00";
when x"A0" => DATA <= x"00";
when x"A1" => DATA <= x"00";
when x"A2" => DATA <= x"00";
when x"A3" => DATA <= x"00";
when x"A4" => DATA <= x"18";
when x"A5" => DATA <= x"18";
when x"A6" => DATA <= x"00";
when x"A7" => DATA <= x"18";
when x"A8" => DATA <= x"18";
when x"A9" => DATA <= x"00";
when x"AA" => DATA <= x"00";
when x"AB" => DATA <= x"00";
when x"AC" => DATA <= x"00";
when x"AD" => DATA <= x"00";
when x"AE" => DATA <= x"00";
when x"AF" => DATA <= x"00";
when x"B0" => DATA <= x"00";
when x"B1" => DATA <= x"00";
when x"B2" => DATA <= x"00";
when x"B3" => DATA <= x"18";
when x"B4" => DATA <= x"18";
when x"B5" => DATA <= x"00";
when x"B6" => DATA <= x"18";
when x"B7" => DATA <= x"18";
when x"B8" => DATA <= x"08";
when x"B9" => DATA <= x"10";
when x"BA" => DATA <= x"00";
when x"BB" => DATA <= x"00";
when x"BC" => DATA <= x"00";
when x"BD" => DATA <= x"00";
when x"BE" => DATA <= x"00";
when x"BF" => DATA <= x"00";
when x"C0" => DATA <= x"00";
when x"C1" => DATA <= x"00";
when x"C2" => DATA <= x"00";
when x"C3" => DATA <= x"04";
when x"C4" => DATA <= x"08";
when x"C5" => DATA <= x"10";
when x"C6" => DATA <= x"20";
when x"C7" => DATA <= x"10";
when x"C8" => DATA <= x"08";
when x"C9" => DATA <= x"04";
when x"CA" => DATA <= x"00";
when x"CB" => DATA <= x"00";
when x"CC" => DATA <= x"00";
when x"CD" => DATA <= x"00";
when x"CE" => DATA <= x"00";
when x"CF" => DATA <= x"00";
when x"D0" => DATA <= x"00";
when x"D1" => DATA <= x"00";
when x"D2" => DATA <= x"00";
when x"D3" => DATA <= x"00";
when x"D4" => DATA <= x"00";
when x"D5" => DATA <= x"3E";
when x"D6" => DATA <= x"00";
when x"D7" => DATA <= x"3E";
when x"D8" => DATA <= x"00";
when x"D9" => DATA <= x"00";
when x"DA" => DATA <= x"00";
when x"DB" => DATA <= x"00";
when x"DC" => DATA <= x"00";
when x"DD" => DATA <= x"00";
when x"DE" => DATA <= x"00";
when x"DF" => DATA <= x"00";
when x"E0" => DATA <= x"00";
when x"E1" => DATA <= x"00";
when x"E2" => DATA <= x"00";
when x"E3" => DATA <= x"10";
when x"E4" => DATA <= x"08";
when x"E5" => DATA <= x"04";
when x"E6" => DATA <= x"02";
when x"E7" => DATA <= x"04";
when x"E8" => DATA <= x"08";
when x"E9" => DATA <= x"10";
when x"EA" => DATA <= x"00";
when x"EB" => DATA <= x"00";
when x"EC" => DATA <= x"00";
when x"ED" => DATA <= x"00";
when x"EE" => DATA <= x"00";
when x"EF" => DATA <= x"00";
when x"F0" => DATA <= x"00";
when x"F1" => DATA <= x"00";
when x"F2" => DATA <= x"00";
when x"F3" => DATA <= x"18";
when x"F4" => DATA <= x"24";
when x"F5" => DATA <= x"04";
when x"F6" => DATA <= x"08";
when x"F7" => DATA <= x"08";
when x"F8" => DATA <= x"00";
when x"F9" => DATA <= x"08";
when x"FA" => DATA <= x"00";
when x"FB" => DATA <= x"00";
when x"FC" => DATA <= x"00";
when x"FD" => DATA <= x"00";
when x"FE" => DATA <= x"00";
when x"FF" => DATA <= x"00";
when others => DATA <= (others => '0');
end case;
end if;
end process;
end RTL;
| apache-2.0 | 33fd19bc0626d2b20bb5fae12eaebafd | 0.30957 | 3.173369 | false | false | false | false |
FinnK/lems2hdl | work/N3_pointCellCondBased/ISIM_output/forwardRaten1.vhdl | 1 | 12,001 |
---------------------------------------------------------------------
-- Standard Library bits
---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- For Modelsim
--use ieee.fixed_pkg.all;
--use ieee.fixed_float_types.ALL;
-- For ISE
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.fixed_float_types.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Entity Description
---------------------------------------------------------------------
entity forwardRaten1 is
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC; --SYNCHRONOUS RESET
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
component_done : out STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_per_time_rate : in sfixed (18 downto -2);
param_voltage_midpoint : in sfixed (2 downto -22);
param_voltage_scale : in sfixed (2 downto -22);
param_voltage_inv_scale_inv : in sfixed (22 downto -2);
exposure_per_time_r : out sfixed (18 downto -2);
derivedvariable_per_time_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_r_in : in sfixed (18 downto -2);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end forwardRaten1;
---------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-- Architecture Begins
-------------------------------------------------------------------------------------------
architecture RTL of forwardRaten1 is
signal COUNT : unsigned(2 downto 0) := "000";
signal childrenCombined_Component_done_single_shot_fired : STD_LOGIC := '0';
signal childrenCombined_Component_done_single_shot : STD_LOGIC := '0';
signal childrenCombined_Component_done : STD_LOGIC := '0';
signal Component_done_int : STD_LOGIC := '0';
signal subprocess_der_int_pre_ready : STD_LOGIC := '0';
signal subprocess_der_int_ready : STD_LOGIC := '0';
signal subprocess_der_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_pre_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_ready : STD_LOGIC := '0';
signal subprocess_dyn_ready : STD_LOGIC := '0';
signal subprocess_model_ready : STD_LOGIC := '1';
signal subprocess_all_ready_shotdone : STD_LOGIC := '1';
signal subprocess_all_ready_shot : STD_LOGIC := '0';
signal subprocess_all_ready : STD_LOGIC := '0';signal pre_exp_r_exponential_result1 : sfixed(18 downto -13);
signal pre_exp_r_exponential_result1_next : sfixed(18 downto -13);
signal exp_r_exponential_result1 : sfixed(18 downto -13);
Component ParamExp is
generic(
BIT_TOP : integer := 20;
BIT_BOTTOM : integer := -20);
port(
clk : In Std_logic;
init_model : In Std_logic;
Start : In Std_logic;
Done : Out Std_logic;
X : In sfixed(BIT_TOP downto BIT_BOTTOM);
Output : Out sfixed(BIT_TOP downto BIT_BOTTOM)
);
end Component;
component delayDone is
generic(
Steps : integer := 10);
port(
clk : In Std_logic;
init_model : In Std_logic;
Start : In Std_logic;
Done : Out Std_logic
);
end component;
---------------------------------------------------------------------
-- Derived Variables and parameters
---------------------------------------------------------------------
signal DerivedVariable_none_x : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_none_x_next : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_per_time_r : sfixed (18 downto -2) := to_sfixed(0.0 ,18,-2);
signal DerivedVariable_per_time_r_next : sfixed (18 downto -2) := to_sfixed(0.0 ,18,-2);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState internal Variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Output Port internal Variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Child Components
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Begin Internal Processes
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Child EDComponent Instantiations and corresponding internal variables
---------------------------------------------------------------------
derived_variable_pre_process_comb :process ( sysparam_time_timestep, param_voltage_midpoint, param_voltage_scale, requirement_voltage_v ,param_voltage_inv_scale_inv, derivedvariable_none_x , param_per_time_rate,exp_r_exponential_result1, derivedvariable_none_x , param_per_time_rate, derivedvariable_none_x )
begin
pre_exp_r_exponential_result1_next <= resize( ( to_sfixed ( 0 ,0 , -1 ) - derivedvariable_none_x ) ,18,-13);
end process derived_variable_pre_process_comb;
derived_variable_pre_process_syn :process ( clk, init_model )
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then
pre_exp_r_exponential_result1 <= to_sfixed(0,18,-13);
else
if subprocess_all_ready_shot = '1' then
pre_exp_r_exponential_result1 <= pre_exp_r_exponential_result1_next;
end if;
end if;
end if;
subprocess_der_int_pre_ready <= '1';
end process derived_variable_pre_process_syn;
ParamExp_0_exponential_result1 : ParamExp
generic map(
BIT_TOP => 18,
BIT_BOTTOM => -13
)
port map ( clk => clk,
init_model => init_model,
Start => step_once_go,
Done => subprocess_der_int_ready,
X => pre_exp_r_exponential_result1 ,
Output => exp_r_exponential_result1
);
derived_variable_process_comb :process ( sysparam_time_timestep, param_voltage_midpoint, param_voltage_scale, requirement_voltage_v ,param_voltage_inv_scale_inv, derivedvariable_none_x , param_per_time_rate,exp_r_exponential_result1, derivedvariable_none_x , param_per_time_rate, derivedvariable_none_x )
begin
derivedvariable_none_x_next <= resize(( ( requirement_voltage_v - param_voltage_midpoint ) * param_voltage_inv_scale_inv ),18,-13);
if To_slv ( resize ( derivedvariable_none_x - ( to_sfixed ( 0 ,0 , -1 ) ) ,2,-18)) /= (20 downto 0 => '0') then
derivedvariable_per_time_r_next <= resize(( param_per_time_rate * derivedvariable_none_x / ( to_sfixed ( 1 ,1 , -1 ) - exp_r_exponential_result1 ) ),18,-2);
end if;
if To_slv ( resize ( derivedvariable_none_x - ( to_sfixed ( 0 ,0 , -1 ) ) ,2,-18)) = (20 downto 0 => '0') then
derivedvariable_per_time_r_next <= resize(( param_per_time_rate ),18,-2);
end if;
end process derived_variable_process_comb;
uut_delayDone_derivedvariable_forwardRaten1 : delayDone GENERIC MAP(
Steps => 2
)
PORT MAP(
clk => clk,
init_model => init_model,
Start => step_once_go,
Done => subprocess_der_ready
);
derived_variable_process_syn :process ( clk,init_model )
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
derivedvariable_none_x <= derivedvariable_none_x_next;
derivedvariable_per_time_r <= derivedvariable_per_time_r_next;
derivedvariable_per_time_r <= derivedvariable_per_time_r_next;
end if;
end if;
end process derived_variable_process_syn;
---------------------------------------------------------------------
dynamics_pre_process_comb :process ( sysparam_time_timestep )
begin
end process dynamics_pre_process_comb;
dynamics_pre_process_syn :process ( clk, init_model )
begin
subprocess_dyn_int_pre_ready <= '1';
end process dynamics_pre_process_syn;
--No dynamics with complex equations found
subprocess_dyn_int_ready <= '1';
state_variable_process_dynamics_comb :process (sysparam_time_timestep)
begin
subprocess_dyn_ready <= '1';
end process state_variable_process_dynamics_comb;
state_variable_process_dynamics_syn :process (CLK,init_model)
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
end if;
end if;
end process state_variable_process_dynamics_syn;
------------------------------------------------------------------------------------------------------
-- EDState Variable Drivers
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to exposures
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to output state variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign derived variables to exposures
---------------------------------------------------------------------
exposure_per_time_r <= derivedvariable_per_time_r_in;derivedvariable_per_time_r_out <= derivedvariable_per_time_r;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Subprocess ready process
---------------------------------------------------------------------
subprocess_all_ready_process: process(step_once_go,subprocess_der_int_ready,subprocess_der_int_pre_ready,subprocess_der_ready,subprocess_dyn_int_pre_ready,subprocess_dyn_int_ready,subprocess_dyn_ready,subprocess_model_ready)
begin
if step_once_go = '0' and subprocess_der_int_ready = '1' and subprocess_der_int_pre_ready = '1'and subprocess_der_ready ='1' and subprocess_dyn_int_ready = '1' and subprocess_dyn_int_pre_ready = '1' and subprocess_dyn_ready = '1' and subprocess_model_ready = '1' then
subprocess_all_ready <= '1';
else
subprocess_all_ready <= '0';
end if;
end process subprocess_all_ready_process;
subprocess_all_ready_shot_process : process(clk)
begin
if rising_edge(clk) then
if (init_model='1') then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '1';
else
if subprocess_all_ready = '1' and subprocess_all_ready_shotdone = '0' then
subprocess_all_ready_shot <= '1';
subprocess_all_ready_shotdone <= '1';
elsif subprocess_all_ready_shot = '1' then
subprocess_all_ready_shot <= '0';
elsif subprocess_all_ready = '0' then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '0';
end if;
end if;
end if;
end process subprocess_all_ready_shot_process;
---------------------------------------------------------------------
count_proc:process(clk)
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then COUNT <= "001";
component_done_int <= '1';
else if step_once_go = '1' then
COUNT <= "000";
component_done_int <= '0';
elsif COUNT = "001" then
component_done_int <= '1';
elsif subprocess_all_ready_shot = '1' then
COUNT <= COUNT + 1;
component_done_int <= '0';
end if;
end if;
end if;
end process count_proc;
component_done <= component_done_int;
end RTL;
| lgpl-3.0 | 0af8f6eaffb3f44c95d0ab33ddc44eca | 0.522873 | 3.907848 | false | false | false | false |
Wynjones1/VHDL-Build | example/text_display/text_ram.vhd | 1 | 1,577 | library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
use work.display_comp.all;
package text_ram_comp is
type text_ram_in_t is
record
we : std_logic;
wd : character_t;
wx : natural range 0 to TEXT_WIDTH - 1;
wy : natural range 0 to TEXT_HEIGHT - 1;
rx : natural range 0 to TEXT_WIDTH - 1;
ry : natural range 0 to TEXT_HEIGHT - 1;
end record;
type text_ram_out_t is
record
data : character_t;
end record;
end package;
library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
use work.text_ram_comp.all;
use work.display_comp.all;
entity text_ram is
port(clk : in std_logic;
reset : in std_logic;
input : in text_ram_in_t;
output : out text_ram_out_t);
end text_ram;
architecture rtl of text_ram is
type ram_t is array(0 to TEXT_WIDTH * TEXT_HEIGHT - 1) of character_t;
subtype index_t is natural range 0 to TEXT_WIDTH * TEXT_HEIGHT - 1;
signal write_idx : index_t;
signal read_idx : index_t;
signal ram_s : ram_t;
begin
comb : process(input)
begin
write_idx <= input.wy * TEXT_WIDTH + input.wx;
read_idx <= input.ry * TEXT_WIDTH + input.rx;
end process;
seq : process(clk, reset)
begin
if rising_edge(clk) then
if input.we = '1' then
ram_s(write_idx) <= input.wd;
end if;
output.data <= ram_s(read_idx);
end if;
end process;
end architecture;
| mit | 22297619cf98d6dc3fd3447026c9c171 | 0.576411 | 3.313025 | false | false | false | false |
DomBlack/mal | vhdl/step8_macros.vhdl | 13 | 14,182 | entity step8_macros is
end entity step8_macros;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
use WORK.env.all;
use WORK.core.all;
architecture test of step8_macros is
shared variable repl_env: env_ptr;
procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is
begin
read_str(str, ast, err);
end procedure mal_READ;
procedure is_pair(ast: inout mal_val_ptr; pair: out boolean) is
begin
pair := is_sequential_type(ast.val_type) and ast.seq_val'length > 0;
end procedure is_pair;
procedure quasiquote(ast: inout mal_val_ptr; result: out mal_val_ptr) is
variable ast_pair, a0_pair: boolean;
variable seq: mal_seq_ptr;
variable a0, rest: mal_val_ptr;
begin
is_pair(ast, ast_pair);
if not ast_pair then
seq := new mal_seq(0 to 1);
new_symbol("quote", seq(0));
seq(1) := ast;
new_seq_obj(mal_list, seq, result);
return;
end if;
a0 := ast.seq_val(0);
if a0.val_type = mal_symbol and a0.string_val.all = "unquote" then
result := ast.seq_val(1);
else
is_pair(a0, a0_pair);
if a0_pair and a0.seq_val(0).val_type = mal_symbol and a0.seq_val(0).string_val.all = "splice-unquote" then
seq := new mal_seq(0 to 2);
new_symbol("concat", seq(0));
seq(1) := a0.seq_val(1);
seq_drop_prefix(ast, 1, rest);
quasiquote(rest, seq(2));
new_seq_obj(mal_list, seq, result);
else
seq := new mal_seq(0 to 2);
new_symbol("cons", seq(0));
quasiquote(a0, seq(1));
seq_drop_prefix(ast, 1, rest);
quasiquote(rest, seq(2));
new_seq_obj(mal_list, seq, result);
end if;
end if;
end procedure quasiquote;
-- Forward declaration
procedure EVAL(in_ast: inout mal_val_ptr; in_env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr);
procedure apply_func(fn: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr);
procedure is_macro_call(ast: inout mal_val_ptr; env: inout env_ptr; is_macro: out boolean) is
variable f, env_err: mal_val_ptr;
begin
is_macro := false;
if ast.val_type = mal_list and
ast.seq_val'length > 0 and
ast.seq_val(0).val_type = mal_symbol then
env_get(env, ast.seq_val(0), f, env_err);
if env_err = null and f /= null and
f.val_type = mal_fn and f.func_val.f_is_macro then
is_macro := true;
end if;
end if;
end procedure is_macro_call;
procedure macroexpand(in_ast: inout mal_val_ptr; env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable ast, macro_fn, call_args, macro_err: mal_val_ptr;
variable is_macro: boolean;
begin
ast := in_ast;
is_macro_call(ast, env, is_macro);
while is_macro loop
env_get(env, ast.seq_val(0), macro_fn, macro_err);
seq_drop_prefix(ast, 1, call_args);
apply_func(macro_fn, call_args, ast, macro_err);
if macro_err /= null then
err := macro_err;
return;
end if;
is_macro_call(ast, env, is_macro);
end loop;
result := ast;
end procedure macroexpand;
procedure fn_eval(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
EVAL(args.seq_val(0), repl_env, result, err);
end procedure fn_eval;
procedure fn_swap(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable atom: mal_val_ptr := args.seq_val(0);
variable fn: mal_val_ptr := args.seq_val(1);
variable call_args_seq: mal_seq_ptr;
variable call_args, eval_res, sub_err: mal_val_ptr;
begin
call_args_seq := new mal_seq(0 to args.seq_val'length - 2);
call_args_seq(0) := atom.seq_val(0);
call_args_seq(1 to call_args_seq'length - 1) := args.seq_val(2 to args.seq_val'length - 1);
new_seq_obj(mal_list, call_args_seq, call_args);
apply_func(fn, call_args, eval_res, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
atom.seq_val(0) := eval_res;
result := eval_res;
end procedure fn_swap;
procedure apply_native_func(func_sym: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
if func_sym.string_val.all = "eval" then
fn_eval(args, result, err);
elsif func_sym.string_val.all = "swap!" then
fn_swap(args, result, err);
else
eval_native_func(func_sym, args, result, err);
end if;
end procedure apply_native_func;
procedure apply_func(fn: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable fn_env: env_ptr;
begin
case fn.val_type is
when mal_nativefn =>
apply_native_func(fn, args, result, err);
when mal_fn =>
new_env(fn_env, fn.func_val.f_env, fn.func_val.f_args, args);
EVAL(fn.func_val.f_body, fn_env, result, err);
when others =>
new_string("not a function", err);
return;
end case;
end procedure apply_func;
procedure eval_ast_seq(ast_seq: inout mal_seq_ptr; env: inout env_ptr; result: inout mal_seq_ptr; err: out mal_val_ptr) is
variable eval_err: mal_val_ptr;
begin
result := new mal_seq(0 to ast_seq'length - 1);
for i in result'range loop
EVAL(ast_seq(i), env, result(i), eval_err);
if eval_err /= null then
err := eval_err;
return;
end if;
end loop;
end procedure eval_ast_seq;
procedure eval_ast(ast: inout mal_val_ptr; env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable key, val, eval_err, env_err: mal_val_ptr;
variable new_seq: mal_seq_ptr;
variable i: integer;
begin
case ast.val_type is
when mal_symbol =>
env_get(env, ast, val, env_err);
if env_err /= null then
err := env_err;
return;
end if;
result := val;
return;
when mal_list | mal_vector | mal_hashmap =>
eval_ast_seq(ast.seq_val, env, new_seq, eval_err);
if eval_err /= null then
err := eval_err;
return;
end if;
new_seq_obj(ast.val_type, new_seq, result);
return;
when others =>
result := ast;
return;
end case;
end procedure eval_ast;
procedure EVAL(in_ast: inout mal_val_ptr; in_env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable i: integer;
variable ast, evaled_ast, a0, call_args, val, vars, sub_err, fn: mal_val_ptr;
variable env, let_env, fn_env: env_ptr;
begin
ast := in_ast;
env := in_env;
loop
if ast.val_type /= mal_list then
eval_ast(ast, env, result, err);
return;
end if;
macroexpand(ast, env, ast, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
if ast.val_type /= mal_list then
eval_ast(ast, env, result, err);
return;
end if;
if ast.seq_val'length = 0 then
result := ast;
return;
end if;
a0 := ast.seq_val(0);
if a0.val_type = mal_symbol then
if a0.string_val.all = "def!" then
EVAL(ast.seq_val(2), env, val, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
env_set(env, ast.seq_val(1), val);
result := val;
return;
elsif a0.string_val.all = "let*" then
vars := ast.seq_val(1);
new_env(let_env, env);
i := 0;
while i < vars.seq_val'length loop
EVAL(vars.seq_val(i + 1), let_env, val, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
env_set(let_env, vars.seq_val(i), val);
i := i + 2;
end loop;
env := let_env;
ast := ast.seq_val(2);
next; -- TCO
elsif a0.string_val.all = "quote" then
result := ast.seq_val(1);
return;
elsif a0.string_val.all = "quasiquote" then
quasiquote(ast.seq_val(1), ast);
next; -- TCO
elsif a0.string_val.all = "defmacro!" then
EVAL(ast.seq_val(2), env, val, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
val.func_val.f_is_macro := true;
env_set(env, ast.seq_val(1), val);
result := val;
return;
elsif a0.string_val.all = "macroexpand" then
macroexpand(ast.seq_val(1), env, result, err);
return;
elsif a0.string_val.all = "do" then
for i in 1 to ast.seq_val'high - 1 loop
EVAL(ast.seq_val(i), env, result, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
end loop;
ast := ast.seq_val(ast.seq_val'high);
next; -- TCO
elsif a0.string_val.all = "if" then
EVAL(ast.seq_val(1), env, val, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
if val.val_type = mal_nil or val.val_type = mal_false then
if ast.seq_val'length > 3 then
ast := ast.seq_val(3);
else
new_nil(result);
return;
end if;
else
ast := ast.seq_val(2);
end if;
next; -- TCO
elsif a0.string_val.all = "fn*" then
new_fn(ast.seq_val(2), ast.seq_val(1), env, result);
return;
end if;
end if;
eval_ast(ast, env, evaled_ast, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
seq_drop_prefix(evaled_ast, 1, call_args);
fn := evaled_ast.seq_val(0);
case fn.val_type is
when mal_nativefn =>
apply_native_func(fn, call_args, result, err);
return;
when mal_fn =>
new_env(fn_env, fn.func_val.f_env, fn.func_val.f_args, call_args);
env := fn_env;
ast := fn.func_val.f_body;
next; -- TCO
when others =>
new_string("not a function", err);
return;
end case;
end loop;
end procedure EVAL;
procedure mal_PRINT(exp: inout mal_val_ptr; result: out line) is
begin
pr_str(exp, true, result);
end procedure mal_PRINT;
procedure RE(str: in string; env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable ast, read_err: mal_val_ptr;
begin
mal_READ(str, ast, read_err);
if read_err /= null then
err := read_err;
result := null;
return;
end if;
if ast = null then
result := null;
return;
end if;
EVAL(ast, env, result, err);
end procedure RE;
procedure REP(str: in string; env: inout env_ptr; result: out line; err: out mal_val_ptr) is
variable eval_res, eval_err: mal_val_ptr;
begin
RE(str, env, eval_res, eval_err);
if eval_err /= null then
err := eval_err;
result := null;
return;
end if;
mal_PRINT(eval_res, result);
end procedure REP;
procedure set_argv(e: inout env_ptr; program_file: inout line) is
variable argv_var_name: string(1 to 6) := "*ARGV*";
variable argv_sym, argv_list: mal_val_ptr;
file f: text;
variable status: file_open_status;
variable one_line: line;
variable seq: mal_seq_ptr;
variable element: mal_val_ptr;
begin
program_file := null;
seq := new mal_seq(0 to -1);
file_open(status, f, external_name => "vhdl_argv.tmp", open_kind => read_mode);
if status = open_ok then
if not endfile(f) then
readline(f, program_file);
while not endfile(f) loop
readline(f, one_line);
new_string(one_line.all, element);
seq := new mal_seq'(seq.all & element);
end loop;
end if;
file_close(f);
end if;
new_seq_obj(mal_list, seq, argv_list);
new_symbol(argv_var_name, argv_sym);
env_set(e, argv_sym, argv_list);
end procedure set_argv;
procedure repl is
variable is_eof: boolean;
variable program_file, input_line, result: line;
variable eval_sym, eval_fn, dummy_val, err: mal_val_ptr;
variable outer: env_ptr;
variable eval_func_name: string(1 to 4) := "eval";
begin
outer := null;
new_env(repl_env, outer);
-- core.EXT: defined using VHDL (see core.vhdl)
define_core_functions(repl_env);
new_symbol(eval_func_name, eval_sym);
new_nativefn(eval_func_name, eval_fn);
env_set(repl_env, eval_sym, eval_fn);
set_argv(repl_env, program_file);
-- core.mal: defined using the language itself
RE("(def! not (fn* (a) (if a false true)))", repl_env, dummy_val, err);
RE("(def! load-file (fn* (f) (eval (read-string (str " & '"' & "(do " & '"' & " (slurp f) " & '"' & ")" & '"' & ")))))", repl_env, dummy_val, err);
RE("(defmacro! cond (fn* (& xs) (if (> (count xs) 0) (list 'if (first xs) (if (> (count xs) 1) (nth xs 1) (throw " & '"' & "odd number of forms to cond" & '"' & ")) (cons 'cond (rest (rest xs)))))))", repl_env, dummy_val, err);
RE("(defmacro! or (fn* (& xs) (if (empty? xs) nil (if (= 1 (count xs)) (first xs) `(let* (or_FIXME ~(first xs)) (if or_FIXME or_FIXME (or ~@(rest xs))))))))", repl_env, dummy_val, err);
if program_file /= null then
REP("(load-file " & '"' & program_file.all & '"' & ")", repl_env, result, err);
return;
end if;
loop
mal_readline("user> ", is_eof, input_line);
exit when is_eof;
next when input_line'length = 0;
REP(input_line.all, repl_env, result, err);
if err /= null then
pr_str(err, false, result);
result := new string'("Error: " & result.all);
end if;
if result /= null then
mal_printline(result.all);
end if;
deallocate(result);
deallocate(err);
end loop;
mal_printline("");
end procedure repl;
begin
repl;
end architecture test;
| mpl-2.0 | ce09b9f0b9e852a276f2459430e6084d | 0.568749 | 3.163507 | false | false | false | false |
kristofferkoch/ethersound | tb_timer.vhd | 1 | 1,551 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY tb_timer IS
END tb_timer;
ARCHITECTURE behavior OF tb_timer IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT timer
PORT(
reset : IN std_logic;
sysclk : IN std_logic;
load : IN unsigned(63 downto 0);
load_en : IN std_logic;
time_o : OUT unsigned(63 downto 0);
ppm : IN signed(9 downto 0)
);
END COMPONENT;
--Inputs
signal reset : std_logic := '0';
signal sysclk : std_logic := '0';
signal load : unsigned(63 downto 0) := (others => '0');
signal load_en : std_logic := '0';
signal ppm : signed(9 downto 0) := (others => '0');
--Outputs
signal time_o : unsigned(63 downto 0);
-- Clock period definitions
constant sysclk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: timer PORT MAP (
reset => reset,
sysclk => sysclk,
load => load,
load_en => load_en,
time_o => time_o,
ppm => ppm
);
-- Clock process definitions
sysclk_process :process
begin
sysclk <= '0';
wait for sysclk_period/2;
sysclk <= '1';
wait for sysclk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
reset <= '1';
ppm <= to_signed(-1, 10);
load_en <= '0';
wait for 100 ns;
reset <= '0';
wait for sysclk_period*10;
-- insert stimulus here
wait;
end process;
END;
| gpl-3.0 | cffd46bb05af13e8444561a4b251b1f7 | 0.559639 | 3.623832 | false | false | false | false |
sergev/vak-opensource | hardware/s3esk-startup/startup.vhd | 1 | 13,504 | --
-- Reference design - Initial design for Spartan-3E Starter Kit when delivered.
--
-- Ken Chapman - Xilinx Ltd - January 2006
--
-- Constantly scroll the text "SPARTAN-3E STARTER KIT" and "www.xilinx.com/s3estarter" across the LCD.
--
-- SW0 turns on LD0
-- SW1 turns on LD1 Single LED is moved left or
-- SW2 turns on LD2 right by rotation of control.
-- SW3 turns on LD3 OR
-- BTN East turns on LD4 by pressing centre
-- BTN South turns on LD5 button of rotary encoder
-- BTN North turns on LD6 toggle mode
-- BTN West turns on LD7
--
-- PicoBlaze provides full control over the LCD display.
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright Xilinx, Inc. 2006. This code may be contain portions patented by other
-- third parties. By providing this core as one possible implementation of a standard,
-- Xilinx is making no representation that the provided implementation of this standard
-- is free from any claims of infringement by any third party. Xilinx expressly
-- disclaims any warranty with respect to the adequacy of the implementation, including
-- but not limited to any warranty or representation that the implementation is free
-- from claims of any third party. Furthermore, Xilinx is providing this core as a
-- courtesy to you and suggests that you contact all third parties to obtain the
-- necessary rights to use this implementation.
--
------------------------------------------------------------------------------------
--
-- Library declarations
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
------------------------------------------------------------------------------------
--
--
entity s3esk_startup is
Port ( led : out std_logic_vector(7 downto 0);
strataflash_oe : out std_logic;
strataflash_ce : out std_logic;
strataflash_we : out std_logic;
switch : in std_logic_vector(3 downto 0);
btn_north : in std_logic;
btn_east : in std_logic;
btn_south : in std_logic;
btn_west : in std_logic;
lcd_d : inout std_logic_vector(7 downto 4);
lcd_rs : out std_logic;
lcd_rw : out std_logic;
lcd_e : out std_logic;
rotary_a : in std_logic;
rotary_b : in std_logic;
rotary_press : in std_logic;
clk : in std_logic);
end s3esk_startup;
--
------------------------------------------------------------------------------------
--
-- Start of test architecture
--
architecture Behavioral of s3esk_startup is
--
------------------------------------------------------------------------------------
--
-- declaration of KCPSM3
--
component kcpsm3
Port ( address : out std_logic_vector(9 downto 0);
instruction : in std_logic_vector(17 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0);
interrupt : in std_logic;
interrupt_ack : out std_logic;
reset : in std_logic;
clk : in std_logic);
end component;
--
-- declaration of program ROM
--
component control
Port ( address : in std_logic_vector(9 downto 0);
instruction : out std_logic_vector(17 downto 0);
proc_reset : out std_logic; --JTAG Loader version
clk : in std_logic);
end component;
--
------------------------------------------------------------------------------------
--
-- Signals used to connect KCPSM3 to program ROM and I/O logic
--
signal address : std_logic_vector(9 downto 0);
signal instruction : std_logic_vector(17 downto 0);
signal port_id : std_logic_vector(7 downto 0);
signal out_port : std_logic_vector(7 downto 0);
signal in_port : std_logic_vector(7 downto 0);
signal write_strobe : std_logic;
signal read_strobe : std_logic;
signal interrupt : std_logic :='0';
signal interrupt_ack : std_logic;
signal kcpsm3_reset : std_logic;
--
--
-- Signals for LCD operation
--
-- Tri-state output requires internal signals
-- 'lcd_drive' is used to differentiate between LCD and StrataFLASH communications
-- which share the same data bits.
--
signal lcd_rw_control : std_logic;
signal lcd_output_data : std_logic_vector(7 downto 4);
signal lcd_drive : std_logic;
--
--
-- Signals used to interface to rotary encoder
--
signal rotary_a_in : std_logic;
signal rotary_b_in : std_logic;
signal rotary_press_in : std_logic;
signal rotary_in : std_logic_vector(1 downto 0);
signal rotary_q1 : std_logic;
signal rotary_q2 : std_logic;
signal delay_rotary_q1 : std_logic;
signal rotary_event : std_logic;
signal rotary_left : std_logic;
--
--
------------------------------------------------------------------------------------------------------------------------------------------------------------------------
--
-- Start of circuit description
--
begin
--
----------------------------------------------------------------------------------------------------------------------------------
-- Disable unused components
----------------------------------------------------------------------------------------------------------------------------------
--
--StrataFLASH must be disabled to prevent it conflicting with the LCD display
--
strataflash_oe <= '1';
strataflash_ce <= '1';
strataflash_we <= '1';
--
--
----------------------------------------------------------------------------------------------------------------------------------
-- KCPSM3 and the program memory
----------------------------------------------------------------------------------------------------------------------------------
--
processor: kcpsm3
port map( address => address,
instruction => instruction,
port_id => port_id,
write_strobe => write_strobe,
out_port => out_port,
read_strobe => read_strobe,
in_port => in_port,
interrupt => interrupt,
interrupt_ack => interrupt_ack,
reset => kcpsm3_reset,
clk => clk);
program_rom: control
port map( address => address,
instruction => instruction,
proc_reset => kcpsm3_reset, --JTAG Loader version
clk => clk);
--
----------------------------------------------------------------------------------------------------------------------------------
-- Interrupt
----------------------------------------------------------------------------------------------------------------------------------
--
--
-- Interrupt is used to detect rotation of the rotary encoder.
-- It is anticipated that the processor will respond to interrupts at a far higher
-- rate that the rotary control can be operated and hence events will not be missed.
--
interrupt_control: process(clk)
begin
if clk'event and clk='1' then
-- processor interrupt waits for an acknowledgement
if interrupt_ack='1' then
interrupt <= '0';
elsif rotary_event='1' then
interrupt <= '1';
else
interrupt <= interrupt;
end if;
end if;
end process interrupt_control;
--
----------------------------------------------------------------------------------------------------------------------------------
-- KCPSM3 input ports
----------------------------------------------------------------------------------------------------------------------------------
--
--
-- The inputs connect via a pipelined multiplexer
--
input_ports: process(clk)
begin
if clk'event and clk='1' then
case port_id(1 downto 0) is
-- read simple toggle switches and buttons at address 00 hex
when "00" => in_port <= btn_west & btn_north & btn_south & btn_east & switch;
-- read rotary control signals at address 01 hex
when "01" => in_port <= "000000" & rotary_press_in & rotary_left ;
-- read LCD data at address 02 hex
when "10" => in_port <= lcd_d & "0000";
-- Don't care used for all other addresses to ensure minimum logic implementation
when others => in_port <= "XXXXXXXX";
end case;
end if;
end process input_ports;
--
----------------------------------------------------------------------------------------------------------------------------------
-- KCPSM3 output ports
----------------------------------------------------------------------------------------------------------------------------------
--
-- adding the output registers to the processor
output_ports: process(clk)
begin
if clk'event and clk='1' then
if write_strobe='1' then
-- Write to LEDs at address 80 hex.
if port_id(7)='1' then
led <= out_port;
end if;
-- LCD data output and controls at address 40 hex.
if port_id(6)='1' then
lcd_output_data <= out_port(7 downto 4);
lcd_drive <= out_port(3);
lcd_rs <= out_port(2);
lcd_rw_control <= out_port(1);
lcd_e <= out_port(0);
end if;
end if;
end if;
end process output_ports;
--
----------------------------------------------------------------------------------------------------------------------------------
-- LCD interface
----------------------------------------------------------------------------------------------------------------------------------
--
-- The 4-bit data port is bidirectional.
-- lcd_rw is '1' for read and '0' for write
-- lcd_drive is like a master enable signal which prevents either the
-- FPGA outputs or the LCD display driving the data lines.
--
--Control of read and write signal
lcd_rw <= lcd_rw_control and lcd_drive;
--use read/write control to enable output buffers.
lcd_d <= lcd_output_data when (lcd_rw_control='0' and lcd_drive='1') else "ZZZZ";
----------------------------------------------------------------------------------------------------------------------------------
-- Interface to rotary encoder.
-- Detection of movement and direction.
----------------------------------------------------------------------------------------------------------------------------------
--
-- The rotary switch contacts are filtered using their offset (one-hot) style to
-- clean them. Circuit concept by Peter Alfke.
-- Note that the clock rate is fast compared with the switch rate.
rotary_filter: process(clk)
begin
if clk'event and clk='1' then
--Synchronise inputs to clock domain using flip-flops in input/output blocks.
rotary_a_in <= rotary_a;
rotary_b_in <= rotary_b;
rotary_press_in <= rotary_press;
--concatinate rotary input signals to form vector for case construct.
rotary_in <= rotary_b_in & rotary_a_in;
case rotary_in is
when "00" => rotary_q1 <= '0';
rotary_q2 <= rotary_q2;
when "01" => rotary_q1 <= rotary_q1;
rotary_q2 <= '0';
when "10" => rotary_q1 <= rotary_q1;
rotary_q2 <= '1';
when "11" => rotary_q1 <= '1';
rotary_q2 <= rotary_q2;
when others => rotary_q1 <= rotary_q1;
rotary_q2 <= rotary_q2;
end case;
end if;
end process rotary_filter;
--
-- The rising edges of 'rotary_q1' indicate that a rotation has occurred and the
-- state of 'rotary_q2' at that time will indicate the direction.
--
direction: process(clk)
begin
if clk'event and clk='1' then
delay_rotary_q1 <= rotary_q1;
if rotary_q1='1' and delay_rotary_q1='0' then
rotary_event <= '1';
rotary_left <= rotary_q2;
else
rotary_event <= '0';
rotary_left <= rotary_left;
end if;
end if;
end process direction;
--
----------------------------------------------------------------------------------------------------------------------------------
--
--
--
--
end Behavioral;
------------------------------------------------------------------------------------------------------------------------------------
--
-- END OF FILE s3esk_startup.vhd
--
------------------------------------------------------------------------------------------------------------------------------------
| apache-2.0 | 9f8aca2c4bbbaed55c9d832a60798187 | 0.442239 | 4.862802 | false | false | false | false |
FinnK/lems2hdl | work/N3_pointCellCondBased/ISIM_output/forwardRatem1.vhdl | 1 | 12,001 |
---------------------------------------------------------------------
-- Standard Library bits
---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- For Modelsim
--use ieee.fixed_pkg.all;
--use ieee.fixed_float_types.ALL;
-- For ISE
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.fixed_float_types.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Entity Description
---------------------------------------------------------------------
entity forwardRatem1 is
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC; --SYNCHRONOUS RESET
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
component_done : out STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_per_time_rate : in sfixed (18 downto -2);
param_voltage_midpoint : in sfixed (2 downto -22);
param_voltage_scale : in sfixed (2 downto -22);
param_voltage_inv_scale_inv : in sfixed (22 downto -2);
exposure_per_time_r : out sfixed (18 downto -2);
derivedvariable_per_time_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_r_in : in sfixed (18 downto -2);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end forwardRatem1;
---------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-- Architecture Begins
-------------------------------------------------------------------------------------------
architecture RTL of forwardRatem1 is
signal COUNT : unsigned(2 downto 0) := "000";
signal childrenCombined_Component_done_single_shot_fired : STD_LOGIC := '0';
signal childrenCombined_Component_done_single_shot : STD_LOGIC := '0';
signal childrenCombined_Component_done : STD_LOGIC := '0';
signal Component_done_int : STD_LOGIC := '0';
signal subprocess_der_int_pre_ready : STD_LOGIC := '0';
signal subprocess_der_int_ready : STD_LOGIC := '0';
signal subprocess_der_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_pre_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_ready : STD_LOGIC := '0';
signal subprocess_dyn_ready : STD_LOGIC := '0';
signal subprocess_model_ready : STD_LOGIC := '1';
signal subprocess_all_ready_shotdone : STD_LOGIC := '1';
signal subprocess_all_ready_shot : STD_LOGIC := '0';
signal subprocess_all_ready : STD_LOGIC := '0';signal pre_exp_r_exponential_result1 : sfixed(18 downto -13);
signal pre_exp_r_exponential_result1_next : sfixed(18 downto -13);
signal exp_r_exponential_result1 : sfixed(18 downto -13);
Component ParamExp is
generic(
BIT_TOP : integer := 20;
BIT_BOTTOM : integer := -20);
port(
clk : In Std_logic;
init_model : In Std_logic;
Start : In Std_logic;
Done : Out Std_logic;
X : In sfixed(BIT_TOP downto BIT_BOTTOM);
Output : Out sfixed(BIT_TOP downto BIT_BOTTOM)
);
end Component;
component delayDone is
generic(
Steps : integer := 10);
port(
clk : In Std_logic;
init_model : In Std_logic;
Start : In Std_logic;
Done : Out Std_logic
);
end component;
---------------------------------------------------------------------
-- Derived Variables and parameters
---------------------------------------------------------------------
signal DerivedVariable_none_x : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_none_x_next : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_per_time_r : sfixed (18 downto -2) := to_sfixed(0.0 ,18,-2);
signal DerivedVariable_per_time_r_next : sfixed (18 downto -2) := to_sfixed(0.0 ,18,-2);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState internal Variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Output Port internal Variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Child Components
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Begin Internal Processes
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Child EDComponent Instantiations and corresponding internal variables
---------------------------------------------------------------------
derived_variable_pre_process_comb :process ( sysparam_time_timestep, param_voltage_midpoint, param_voltage_scale, requirement_voltage_v ,param_voltage_inv_scale_inv, derivedvariable_none_x , param_per_time_rate,exp_r_exponential_result1, derivedvariable_none_x , param_per_time_rate, derivedvariable_none_x )
begin
pre_exp_r_exponential_result1_next <= resize( ( to_sfixed ( 0 ,0 , -1 ) - derivedvariable_none_x ) ,18,-13);
end process derived_variable_pre_process_comb;
derived_variable_pre_process_syn :process ( clk, init_model )
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then
pre_exp_r_exponential_result1 <= to_sfixed(0,18,-13);
else
if subprocess_all_ready_shot = '1' then
pre_exp_r_exponential_result1 <= pre_exp_r_exponential_result1_next;
end if;
end if;
end if;
subprocess_der_int_pre_ready <= '1';
end process derived_variable_pre_process_syn;
ParamExp_0_exponential_result1 : ParamExp
generic map(
BIT_TOP => 18,
BIT_BOTTOM => -13
)
port map ( clk => clk,
init_model => init_model,
Start => step_once_go,
Done => subprocess_der_int_ready,
X => pre_exp_r_exponential_result1 ,
Output => exp_r_exponential_result1
);
derived_variable_process_comb :process ( sysparam_time_timestep, param_voltage_midpoint, param_voltage_scale, requirement_voltage_v ,param_voltage_inv_scale_inv, derivedvariable_none_x , param_per_time_rate,exp_r_exponential_result1, derivedvariable_none_x , param_per_time_rate, derivedvariable_none_x )
begin
derivedvariable_none_x_next <= resize(( ( requirement_voltage_v - param_voltage_midpoint ) * param_voltage_inv_scale_inv ),18,-13);
if To_slv ( resize ( derivedvariable_none_x - ( to_sfixed ( 0 ,0 , -1 ) ) ,2,-18)) /= (20 downto 0 => '0') then
derivedvariable_per_time_r_next <= resize(( param_per_time_rate * derivedvariable_none_x / ( to_sfixed ( 1 ,1 , -1 ) - exp_r_exponential_result1 ) ),18,-2);
end if;
if To_slv ( resize ( derivedvariable_none_x - ( to_sfixed ( 0 ,0 , -1 ) ) ,2,-18)) = (20 downto 0 => '0') then
derivedvariable_per_time_r_next <= resize(( param_per_time_rate ),18,-2);
end if;
end process derived_variable_process_comb;
uut_delayDone_derivedvariable_forwardRatem1 : delayDone GENERIC MAP(
Steps => 2
)
PORT MAP(
clk => clk,
init_model => init_model,
Start => step_once_go,
Done => subprocess_der_ready
);
derived_variable_process_syn :process ( clk,init_model )
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
derivedvariable_none_x <= derivedvariable_none_x_next;
derivedvariable_per_time_r <= derivedvariable_per_time_r_next;
derivedvariable_per_time_r <= derivedvariable_per_time_r_next;
end if;
end if;
end process derived_variable_process_syn;
---------------------------------------------------------------------
dynamics_pre_process_comb :process ( sysparam_time_timestep )
begin
end process dynamics_pre_process_comb;
dynamics_pre_process_syn :process ( clk, init_model )
begin
subprocess_dyn_int_pre_ready <= '1';
end process dynamics_pre_process_syn;
--No dynamics with complex equations found
subprocess_dyn_int_ready <= '1';
state_variable_process_dynamics_comb :process (sysparam_time_timestep)
begin
subprocess_dyn_ready <= '1';
end process state_variable_process_dynamics_comb;
state_variable_process_dynamics_syn :process (CLK,init_model)
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
end if;
end if;
end process state_variable_process_dynamics_syn;
------------------------------------------------------------------------------------------------------
-- EDState Variable Drivers
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to exposures
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to output state variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign derived variables to exposures
---------------------------------------------------------------------
exposure_per_time_r <= derivedvariable_per_time_r_in;derivedvariable_per_time_r_out <= derivedvariable_per_time_r;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Subprocess ready process
---------------------------------------------------------------------
subprocess_all_ready_process: process(step_once_go,subprocess_der_int_ready,subprocess_der_int_pre_ready,subprocess_der_ready,subprocess_dyn_int_pre_ready,subprocess_dyn_int_ready,subprocess_dyn_ready,subprocess_model_ready)
begin
if step_once_go = '0' and subprocess_der_int_ready = '1' and subprocess_der_int_pre_ready = '1'and subprocess_der_ready ='1' and subprocess_dyn_int_ready = '1' and subprocess_dyn_int_pre_ready = '1' and subprocess_dyn_ready = '1' and subprocess_model_ready = '1' then
subprocess_all_ready <= '1';
else
subprocess_all_ready <= '0';
end if;
end process subprocess_all_ready_process;
subprocess_all_ready_shot_process : process(clk)
begin
if rising_edge(clk) then
if (init_model='1') then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '1';
else
if subprocess_all_ready = '1' and subprocess_all_ready_shotdone = '0' then
subprocess_all_ready_shot <= '1';
subprocess_all_ready_shotdone <= '1';
elsif subprocess_all_ready_shot = '1' then
subprocess_all_ready_shot <= '0';
elsif subprocess_all_ready = '0' then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '0';
end if;
end if;
end if;
end process subprocess_all_ready_shot_process;
---------------------------------------------------------------------
count_proc:process(clk)
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then COUNT <= "001";
component_done_int <= '1';
else if step_once_go = '1' then
COUNT <= "000";
component_done_int <= '0';
elsif COUNT = "001" then
component_done_int <= '1';
elsif subprocess_all_ready_shot = '1' then
COUNT <= COUNT + 1;
component_done_int <= '0';
end if;
end if;
end if;
end process count_proc;
component_done <= component_done_int;
end RTL;
| lgpl-3.0 | 1ccdebb2db085de1031911545e4bfa36 | 0.522873 | 3.907848 | false | false | false | false |
dangpzanco/sistemas-digitais | FSM.vhd | 1 | 2,297 | library ieee;
use ieee.std_logic_1164.all;
entity FSM is
port (
Clk, Rst, Enter : in std_logic;
Operacao: in std_logic_vector(1 downto 0);
Sel: out std_logic_vector(1 downto 0);
Enable_1, Enable_2: out std_logic
);
end FSM;
architecture FSM_beh of FSM is
type states is (S0, S1, S2, S3, S4, S5, S6, S7);
signal EA: states;
signal last_sel, last_EN: std_logic_vector(1 downto 0);
begin
P1: process (Clk, Rst, Enter, Operacao)
begin
-- não esquecer do end if;
if Rst = '0' then
EA <= S0;
elsif Clk'event and Clk = '1' then
case EA is
when S0 =>
if Enter = '0' then
EA <= S1;
else
EA <= S0;
end if;
when S1 =>
if Enter = '0' then
EA <= S1;
else
EA <= S2;
end if;
when S2 =>
if Operacao = "00" then
EA <= S3; -- Fazer SOMA
elsif Operacao = "01" then
EA <= S4; -- Fazer SUB
elsif Operacao = "10" then
EA <= S5; -- Fazer /2
else
EA <= S6; -- Fazer *2
end if;
when S3 => --SOMA
if Enter = '1' then
EA <= S3;
else
EA <= S7;
end if;
when S4 => --SUB
if Enter = '1' then
EA <= S4;
else
EA <= S7;
end if;
when S5 => --/2
EA <= S0;
when S6 => --*2
EA <= S0;
when S7 =>
if Enter = '0' then
EA <= S7;
else
EA <= S0;
end if;
end case;
end if;
end process;
P2: process(EA)
begin
case EA is
when S0 =>
Enable_1 <= '0';
Enable_2 <= '0';
when S1 =>
Enable_1 <= '1';
Enable_2 <= '0';
when S2 =>
Enable_1 <= '0';
Enable_2 <= '0';
last_sel <= Operacao;
when S3 => --SOMA
--Enable_1 <= '0';
--Enable_2 <= '0';
Sel <= last_sel;
when S4 => --SUB
--Enable_1 <= '0';
--Enable_2 <= '0';
Sel <= last_sel;
when S5 => --/2
Enable_1 <= '0';
Enable_2 <= '1';
Sel <= last_sel;
when S6 => --*2
Enable_1 <= '0';
Enable_2 <= '1';
Sel <= last_sel;
when S7 =>
Enable_1 <= '0';
Enable_2 <= '1';
Sel <= last_sel;
end case;
end process;
end FSM_beh;
| mit | 598e1f41e03b9560cad0eb976653b040 | 0.439895 | 2.746411 | false | false | false | false |
FinnK/lems2hdl | work/N3_pointCellCondBased/ISIM_output/na.vhdl | 1 | 23,238 |
---------------------------------------------------------------------
-- Standard Library bits
---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- For Modelsim
--use ieee.fixed_pkg.all;
--use ieee.fixed_float_types.ALL;
-- For ISE
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.fixed_float_types.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Entity Description
---------------------------------------------------------------------
entity na is
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC; --SYNCHRONOUS RESET
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
component_done : out STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_conductance_conductance : in sfixed (-22 downto -53);
exposure_conductance_g : out sfixed (-22 downto -53);
derivedvariable_conductance_g_out : out sfixed (-22 downto -53);
derivedvariable_conductance_g_in : in sfixed (-22 downto -53);
param_none_m_instances : in sfixed (18 downto -13);
exposure_none_m_fcond : out sfixed (18 downto -13);
exposure_none_m_q : out sfixed (18 downto -13);
statevariable_none_m_q_out : out sfixed (18 downto -13);
statevariable_none_m_q_in : in sfixed (18 downto -13);
derivedvariable_none_m_fcond_out : out sfixed (18 downto -13);
derivedvariable_none_m_fcond_in : in sfixed (18 downto -13);
param_per_time_m_forwardRatem1_rate : in sfixed (18 downto -2);
param_voltage_m_forwardRatem1_midpoint : in sfixed (2 downto -22);
param_voltage_m_forwardRatem1_scale : in sfixed (2 downto -22);
param_voltage_inv_m_forwardRatem1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_m_forwardRatem1_r : out sfixed (18 downto -2);
derivedvariable_per_time_m_forwardRatem1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_m_forwardRatem1_r_in : in sfixed (18 downto -2);
param_per_time_m_reverseRatem1_rate : in sfixed (18 downto -2);
param_voltage_m_reverseRatem1_midpoint : in sfixed (2 downto -22);
param_voltage_m_reverseRatem1_scale : in sfixed (2 downto -22);
param_voltage_inv_m_reverseRatem1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_m_reverseRatem1_r : out sfixed (18 downto -2);
derivedvariable_per_time_m_reverseRatem1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_m_reverseRatem1_r_in : in sfixed (18 downto -2);
param_none_h_instances : in sfixed (18 downto -13);
exposure_none_h_fcond : out sfixed (18 downto -13);
exposure_none_h_q : out sfixed (18 downto -13);
statevariable_none_h_q_out : out sfixed (18 downto -13);
statevariable_none_h_q_in : in sfixed (18 downto -13);
derivedvariable_none_h_fcond_out : out sfixed (18 downto -13);
derivedvariable_none_h_fcond_in : in sfixed (18 downto -13);
param_per_time_h_forwardRateh1_rate : in sfixed (18 downto -2);
param_voltage_h_forwardRateh1_midpoint : in sfixed (2 downto -22);
param_voltage_h_forwardRateh1_scale : in sfixed (2 downto -22);
param_voltage_inv_h_forwardRateh1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_h_forwardRateh1_r : out sfixed (18 downto -2);
derivedvariable_per_time_h_forwardRateh1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_h_forwardRateh1_r_in : in sfixed (18 downto -2);
param_per_time_h_reverseRateh1_rate : in sfixed (18 downto -2);
param_voltage_h_reverseRateh1_midpoint : in sfixed (2 downto -22);
param_voltage_h_reverseRateh1_scale : in sfixed (2 downto -22);
param_voltage_inv_h_reverseRateh1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_h_reverseRateh1_r : out sfixed (18 downto -2);
derivedvariable_per_time_h_reverseRateh1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_h_reverseRateh1_r_in : in sfixed (18 downto -2);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end na;
---------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-- Architecture Begins
-------------------------------------------------------------------------------------------
architecture RTL of na is
signal COUNT : unsigned(2 downto 0) := "000";
signal childrenCombined_Component_done_single_shot_fired : STD_LOGIC := '0';
signal childrenCombined_Component_done_single_shot : STD_LOGIC := '0';
signal childrenCombined_Component_done : STD_LOGIC := '0';
signal Component_done_int : STD_LOGIC := '0';
signal subprocess_der_int_pre_ready : STD_LOGIC := '0';
signal subprocess_der_int_ready : STD_LOGIC := '0';
signal subprocess_der_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_pre_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_ready : STD_LOGIC := '0';
signal subprocess_dyn_ready : STD_LOGIC := '0';
signal subprocess_model_ready : STD_LOGIC := '1';
signal subprocess_all_ready_shotdone : STD_LOGIC := '1';
signal subprocess_all_ready_shot : STD_LOGIC := '0';
signal subprocess_all_ready : STD_LOGIC := '0';
---------------------------------------------------------------------
-- Derived Variables and parameters
---------------------------------------------------------------------
signal DerivedVariable_none_conductanceScale : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_none_conductanceScale_next : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_none_fopenHHrates : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_none_fopenHHrates_next : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_none_fopenHHtauInf : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_none_fopenHHtauInf_next : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_none_fopenHHratesTau : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_none_fopenHHratesTau_next : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_none_fopenHHratesInf : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_none_fopenHHratesInf_next : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_none_fopenHHratesTauInf : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_none_fopenHHratesTauInf_next : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_none_fopen : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_none_fopen_next : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_conductance_g : sfixed (-22 downto -53) := to_sfixed(0.0 ,-22,-53);
signal DerivedVariable_conductance_g_next : sfixed (-22 downto -53) := to_sfixed(0.0 ,-22,-53);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState internal Variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Output Port internal Variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Child Components
---------------------------------------------------------------------
component m
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC;
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
Component_done : out STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_none_instances : in sfixed (18 downto -13);
exposure_none_fcond : out sfixed (18 downto -13);
exposure_none_q : out sfixed (18 downto -13);
statevariable_none_q_out : out sfixed (18 downto -13);
statevariable_none_q_in : in sfixed (18 downto -13);
derivedvariable_none_fcond_out : out sfixed (18 downto -13);
derivedvariable_none_fcond_in : in sfixed (18 downto -13);
param_per_time_forwardRatem1_rate : in sfixed (18 downto -2);
param_voltage_forwardRatem1_midpoint : in sfixed (2 downto -22);
param_voltage_forwardRatem1_scale : in sfixed (2 downto -22);
param_voltage_inv_forwardRatem1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_forwardRatem1_r : out sfixed (18 downto -2);
derivedvariable_per_time_forwardRatem1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_forwardRatem1_r_in : in sfixed (18 downto -2);
param_per_time_reverseRatem1_rate : in sfixed (18 downto -2);
param_voltage_reverseRatem1_midpoint : in sfixed (2 downto -22);
param_voltage_reverseRatem1_scale : in sfixed (2 downto -22);
param_voltage_inv_reverseRatem1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_reverseRatem1_r : out sfixed (18 downto -2);
derivedvariable_per_time_reverseRatem1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_reverseRatem1_r_in : in sfixed (18 downto -2);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end component;
signal m_Component_done : STD_LOGIC ; signal Exposure_none_m_fcond_internal : sfixed (18 downto -13);
signal Exposure_none_m_q_internal : sfixed (18 downto -13);
signal Exposure_per_time_m_forwardRatem1_r_internal : sfixed (18 downto -2);
signal Exposure_per_time_m_reverseRatem1_r_internal : sfixed (18 downto -2);
---------------------------------------------------------------------
component h
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC;
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
Component_done : out STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_none_instances : in sfixed (18 downto -13);
exposure_none_fcond : out sfixed (18 downto -13);
exposure_none_q : out sfixed (18 downto -13);
statevariable_none_q_out : out sfixed (18 downto -13);
statevariable_none_q_in : in sfixed (18 downto -13);
derivedvariable_none_fcond_out : out sfixed (18 downto -13);
derivedvariable_none_fcond_in : in sfixed (18 downto -13);
param_per_time_forwardRateh1_rate : in sfixed (18 downto -2);
param_voltage_forwardRateh1_midpoint : in sfixed (2 downto -22);
param_voltage_forwardRateh1_scale : in sfixed (2 downto -22);
param_voltage_inv_forwardRateh1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_forwardRateh1_r : out sfixed (18 downto -2);
derivedvariable_per_time_forwardRateh1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_forwardRateh1_r_in : in sfixed (18 downto -2);
param_per_time_reverseRateh1_rate : in sfixed (18 downto -2);
param_voltage_reverseRateh1_midpoint : in sfixed (2 downto -22);
param_voltage_reverseRateh1_scale : in sfixed (2 downto -22);
param_voltage_inv_reverseRateh1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_reverseRateh1_r : out sfixed (18 downto -2);
derivedvariable_per_time_reverseRateh1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_reverseRateh1_r_in : in sfixed (18 downto -2);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end component;
signal h_Component_done : STD_LOGIC ; signal Exposure_none_h_fcond_internal : sfixed (18 downto -13);
signal Exposure_none_h_q_internal : sfixed (18 downto -13);
signal Exposure_per_time_h_forwardRateh1_r_internal : sfixed (18 downto -2);
signal Exposure_per_time_h_reverseRateh1_r_internal : sfixed (18 downto -2);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Begin Internal Processes
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Child EDComponent Instantiations and corresponding internal variables
---------------------------------------------------------------------
m_uut : m
port map (
clk => clk,
init_model => init_model,
step_once_go => step_once_go,
Component_done => m_Component_done,
param_none_instances => param_none_m_instances,
requirement_voltage_v => requirement_voltage_v,
Exposure_none_fcond => Exposure_none_m_fcond_internal,
Exposure_none_q => Exposure_none_m_q_internal,
statevariable_none_q_out => statevariable_none_m_q_out,
statevariable_none_q_in => statevariable_none_m_q_in,
derivedvariable_none_fcond_out => derivedvariable_none_m_fcond_out,
derivedvariable_none_fcond_in => derivedvariable_none_m_fcond_in,
param_per_time_forwardRatem1_rate => param_per_time_m_forwardRatem1_rate,
param_voltage_forwardRatem1_midpoint => param_voltage_m_forwardRatem1_midpoint,
param_voltage_forwardRatem1_scale => param_voltage_m_forwardRatem1_scale,
param_voltage_inv_forwardRatem1_scale_inv => param_voltage_inv_m_forwardRatem1_scale_inv,
Exposure_per_time_forwardRatem1_r => Exposure_per_time_m_forwardRatem1_r_internal,
derivedvariable_per_time_forwardRatem1_r_out => derivedvariable_per_time_m_forwardRatem1_r_out,
derivedvariable_per_time_forwardRatem1_r_in => derivedvariable_per_time_m_forwardRatem1_r_in,
param_per_time_reverseRatem1_rate => param_per_time_m_reverseRatem1_rate,
param_voltage_reverseRatem1_midpoint => param_voltage_m_reverseRatem1_midpoint,
param_voltage_reverseRatem1_scale => param_voltage_m_reverseRatem1_scale,
param_voltage_inv_reverseRatem1_scale_inv => param_voltage_inv_m_reverseRatem1_scale_inv,
Exposure_per_time_reverseRatem1_r => Exposure_per_time_m_reverseRatem1_r_internal,
derivedvariable_per_time_reverseRatem1_r_out => derivedvariable_per_time_m_reverseRatem1_r_out,
derivedvariable_per_time_reverseRatem1_r_in => derivedvariable_per_time_m_reverseRatem1_r_in,
sysparam_time_timestep => sysparam_time_timestep,
sysparam_time_simtime => sysparam_time_simtime
);
Exposure_none_m_fcond <= Exposure_none_m_fcond_internal;
Exposure_none_m_q <= Exposure_none_m_q_internal;
h_uut : h
port map (
clk => clk,
init_model => init_model,
step_once_go => step_once_go,
Component_done => h_Component_done,
param_none_instances => param_none_h_instances,
requirement_voltage_v => requirement_voltage_v,
Exposure_none_fcond => Exposure_none_h_fcond_internal,
Exposure_none_q => Exposure_none_h_q_internal,
statevariable_none_q_out => statevariable_none_h_q_out,
statevariable_none_q_in => statevariable_none_h_q_in,
derivedvariable_none_fcond_out => derivedvariable_none_h_fcond_out,
derivedvariable_none_fcond_in => derivedvariable_none_h_fcond_in,
param_per_time_forwardRateh1_rate => param_per_time_h_forwardRateh1_rate,
param_voltage_forwardRateh1_midpoint => param_voltage_h_forwardRateh1_midpoint,
param_voltage_forwardRateh1_scale => param_voltage_h_forwardRateh1_scale,
param_voltage_inv_forwardRateh1_scale_inv => param_voltage_inv_h_forwardRateh1_scale_inv,
Exposure_per_time_forwardRateh1_r => Exposure_per_time_h_forwardRateh1_r_internal,
derivedvariable_per_time_forwardRateh1_r_out => derivedvariable_per_time_h_forwardRateh1_r_out,
derivedvariable_per_time_forwardRateh1_r_in => derivedvariable_per_time_h_forwardRateh1_r_in,
param_per_time_reverseRateh1_rate => param_per_time_h_reverseRateh1_rate,
param_voltage_reverseRateh1_midpoint => param_voltage_h_reverseRateh1_midpoint,
param_voltage_reverseRateh1_scale => param_voltage_h_reverseRateh1_scale,
param_voltage_inv_reverseRateh1_scale_inv => param_voltage_inv_h_reverseRateh1_scale_inv,
Exposure_per_time_reverseRateh1_r => Exposure_per_time_h_reverseRateh1_r_internal,
derivedvariable_per_time_reverseRateh1_r_out => derivedvariable_per_time_h_reverseRateh1_r_out,
derivedvariable_per_time_reverseRateh1_r_in => derivedvariable_per_time_h_reverseRateh1_r_in,
sysparam_time_timestep => sysparam_time_timestep,
sysparam_time_simtime => sysparam_time_simtime
);
Exposure_none_h_fcond <= Exposure_none_h_fcond_internal;
Exposure_none_h_q <= Exposure_none_h_q_internal;
derived_variable_pre_process_comb :process ( sysparam_time_timestep,exposure_none_m_fcond_internal,exposure_none_h_fcond_internal, derivedvariable_none_fopenHHratesTauInf_next , derivedvariable_none_conductanceScale_next , derivedvariable_none_fopenHHratesInf_next , derivedvariable_none_fopenHHratesTau_next , derivedvariable_none_fopenHHtauInf_next , derivedvariable_none_fopenHHrates_next , param_conductance_conductance, derivedvariable_none_fopen_next )
begin
end process derived_variable_pre_process_comb;
derived_variable_pre_process_syn :process ( clk, init_model )
begin
subprocess_der_int_pre_ready <= '1';
end process derived_variable_pre_process_syn;
--no complex steps in derived variables
subprocess_der_int_ready <= '1';
derived_variable_process_comb :process ( sysparam_time_timestep,exposure_none_m_fcond_internal,exposure_none_h_fcond_internal, derivedvariable_none_fopenHHratesTauInf_next , derivedvariable_none_conductanceScale_next , derivedvariable_none_fopenHHratesInf_next , derivedvariable_none_fopenHHratesTau_next , derivedvariable_none_fopenHHtauInf_next , derivedvariable_none_fopenHHrates_next , param_conductance_conductance, derivedvariable_none_fopen_next )
begin
derivedvariable_none_fopenHHrates_next <= resize(( ( exposure_none_m_fcond_internal * exposure_none_h_fcond_internal ) ),18,-13);
derivedvariable_none_fopen_next <= resize(( derivedvariable_none_fopenHHrates_next ),18,-13);
derivedvariable_conductance_g_next <= resize(( param_conductance_conductance * derivedvariable_none_fopen_next ),-22,-53);
subprocess_der_ready <= '1';
end process derived_variable_process_comb;
derived_variable_process_syn :process ( clk,init_model )
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
derivedvariable_none_fopenHHrates <= derivedvariable_none_fopenHHrates_next;
derivedvariable_none_fopen <= derivedvariable_none_fopen_next;
derivedvariable_conductance_g <= derivedvariable_conductance_g_next;
end if;
end if;
end process derived_variable_process_syn;
---------------------------------------------------------------------
dynamics_pre_process_comb :process ( sysparam_time_timestep )
begin
end process dynamics_pre_process_comb;
dynamics_pre_process_syn :process ( clk, init_model )
begin
subprocess_dyn_int_pre_ready <= '1';
end process dynamics_pre_process_syn;
--No dynamics with complex equations found
subprocess_dyn_int_ready <= '1';
state_variable_process_dynamics_comb :process (sysparam_time_timestep)
begin
subprocess_dyn_ready <= '1';
end process state_variable_process_dynamics_comb;
state_variable_process_dynamics_syn :process (CLK,init_model)
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
end if;
end if;
end process state_variable_process_dynamics_syn;
------------------------------------------------------------------------------------------------------
-- EDState Variable Drivers
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to exposures
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to output state variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign derived variables to exposures
---------------------------------------------------------------------
exposure_conductance_g <= derivedvariable_conductance_g_in;derivedvariable_conductance_g_out <= derivedvariable_conductance_g;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Subprocess ready process
---------------------------------------------------------------------
subprocess_all_ready_process: process(step_once_go,subprocess_der_int_ready,subprocess_der_int_pre_ready,subprocess_der_ready,subprocess_dyn_int_pre_ready,subprocess_dyn_int_ready,subprocess_dyn_ready,subprocess_model_ready)
begin
if step_once_go = '0' and subprocess_der_int_ready = '1' and subprocess_der_int_pre_ready = '1'and subprocess_der_ready ='1' and subprocess_dyn_int_ready = '1' and subprocess_dyn_int_pre_ready = '1' and subprocess_dyn_ready = '1' and subprocess_model_ready = '1' then
subprocess_all_ready <= '1';
else
subprocess_all_ready <= '0';
end if;
end process subprocess_all_ready_process;
subprocess_all_ready_shot_process : process(clk)
begin
if rising_edge(clk) then
if (init_model='1') then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '1';
else
if subprocess_all_ready = '1' and subprocess_all_ready_shotdone = '0' then
subprocess_all_ready_shot <= '1';
subprocess_all_ready_shotdone <= '1';
elsif subprocess_all_ready_shot = '1' then
subprocess_all_ready_shot <= '0';
elsif subprocess_all_ready = '0' then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '0';
end if;
end if;
end if;
end process subprocess_all_ready_shot_process;
---------------------------------------------------------------------
count_proc:process(clk)
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then COUNT <= "001";
component_done_int <= '1';
else if step_once_go = '1' then
COUNT <= "000";
component_done_int <= '0';
elsif COUNT = "001" then
component_done_int <= '1';
elsif subprocess_all_ready_shot = '1' then
COUNT <= COUNT + 1;
component_done_int <= '0';
end if;
end if;
end if;
end process count_proc;
childrenCombined_component_done_process:process(m_component_done,h_component_done,CLK)
begin
if (m_component_done = '1' and h_component_done = '1') then
childrenCombined_component_done <= '1';
else
childrenCombined_component_done <= '0';
end if;
end process childrenCombined_component_done_process;
component_done <= component_done_int and childrenCombined_component_done;
end RTL;
| lgpl-3.0 | 02d11a76a5617d608ad2c35a1b8fdd77 | 0.637318 | 3.416348 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/boards/terasic-de2-115/mn-single-hostif-drv/quartus/toplevel.vhd | 2 | 11,219 | -------------------------------------------------------------------------------
--! @file toplevel.vhd
--
--! @brief Toplevel of Nios MN design Pcp part
--
--! @details This is the toplevel of the Nios MN FPGA Pcp design for the
--! INK DE2-115 Evaluation Board.
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity toplevel is
port (
-- 50 MHZ CLK IN
EXT_CLK : in std_logic;
-- PHY Interfaces
PHY_GXCLK : out std_logic_vector(1 downto 0);
PHY_RXCLK : in std_logic_vector(1 downto 0);
PHY_RXER : in std_logic_vector(1 downto 0);
PHY_RXDV : in std_logic_vector(1 downto 0);
PHY_RXD : in std_logic_vector(7 downto 0);
PHY_TXCLK : in std_logic_vector(1 downto 0);
PHY_TXER : out std_logic_vector(1 downto 0);
PHY_TXEN : out std_logic_vector(1 downto 0);
PHY_TXD : out std_logic_vector(7 downto 0);
PHY_MDIO : inout std_logic_vector(1 downto 0);
PHY_MDC : out std_logic_vector(1 downto 0);
PHY_RESET_n : out std_logic_vector(1 downto 0);
-- EPCS
EPCS_DCLK : out std_logic;
EPCS_SCE : out std_logic;
EPCS_SDO : out std_logic;
EPCS_DATA0 : in std_logic;
-- 2 MB SRAM
SRAM_CE_n : out std_logic;
SRAM_OE_n : out std_logic;
SRAM_WE_n : out std_logic;
SRAM_ADDR : out std_logic_vector(20 downto 1);
SRAM_BE_n : out std_logic_vector(1 downto 0);
SRAM_DQ : inout std_logic_vector(15 downto 0);
-- HOST Interface
HOSTIF_AD : inout std_logic_vector(15 downto 0);
HOSTIF_BE : in std_logic_vector(1 downto 0);
HOSTIF_CS_n : in std_logic;
HOSTIF_WR_n : in std_logic;
HOSTIF_RD_n : in std_logic;
HOSTIF_ALE_n : in std_logic;
HOSTIF_ACK_n : out std_logic;
HOSTIF_IRQ_n : out std_logic
);
end toplevel;
architecture rtl of toplevel is
component mnSingleHostifDrv is
port (
clk25_clk : in std_logic;
clk50_clk : in std_logic := 'X';
clk100_clk : in std_logic;
reset_reset_n : in std_logic := 'X';
tri_state_0_tcm_address_out : out std_logic_vector(20 downto 0);
tri_state_0_tcm_byteenable_n_out : out std_logic_vector(1 downto 0);
tri_state_0_tcm_read_n_out : out std_logic;
tri_state_0_tcm_write_n_out : out std_logic;
tri_state_0_tcm_data_out : inout std_logic_vector(15 downto 0) := (others => 'X');
tri_state_0_tcm_chipselect_n_out : out std_logic;
pcp_0_benchmark_pio_export : out std_logic_vector(7 downto 0);
-- OPENMAC
openmac_0_mii_txEnable : out std_logic_vector(1 downto 0);
openmac_0_mii_txData : out std_logic_vector(7 downto 0);
openmac_0_mii_txClk : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_mii_rxError : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_mii_rxDataValid : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_mii_rxData : in std_logic_vector(7 downto 0) := (others => 'X');
openmac_0_mii_rxClk : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_smi_nPhyRst : out std_logic_vector(1 downto 0);
openmac_0_smi_clk : out std_logic_vector(1 downto 0);
openmac_0_smi_dio : inout std_logic_vector(1 downto 0) := (others => 'X');
epcs_flash_dclk : out std_logic;
epcs_flash_sce : out std_logic;
epcs_flash_sdo : out std_logic;
epcs_flash_data0 : in std_logic := 'X';
hostinterface_0_irqout_irq : out std_logic;
hostinterface_0_parhost_chipselect : in std_logic := 'X';
hostinterface_0_parhost_read : in std_logic := 'X';
hostinterface_0_parhost_write : in std_logic := 'X';
hostinterface_0_parhost_addressLatchEnable : in std_logic := 'X';
hostinterface_0_parhost_acknowledge : out std_logic;
hostinterface_0_parhost_byteenable : in std_logic_vector(1 downto 0) := (others => 'X');
hostinterface_0_parhost_addressData : inout std_logic_vector(15 downto 0) := (others => 'X')
);
end component mnSingleHostifDrv;
-- PLL component
component pll
port (
inclk0 : in std_logic;
c0 : out std_logic;
c1 : out std_logic;
c2 : out std_logic;
c3 : out std_logic;
locked : out std_logic
);
end component;
signal clk25 : std_logic;
signal clk50 : std_logic;
signal clk100 : std_logic;
signal clk100_p : std_logic;
signal pllLocked : std_logic;
signal sramAddr : std_logic_vector(SRAM_ADDR'high downto 0);
signal parHost_chipselect : std_logic;
signal parHost_read : std_logic;
signal parHost_write : std_logic;
signal parHost_addressLatchEnable : std_logic;
signal parHost_acknowledge : std_logic;
signal host_irq : std_logic;
begin
SRAM_ADDR <= sramAddr(SRAM_ADDR'range);
PHY_GXCLK <= (others => '0');
PHY_TXER <= (others => '0');
HOSTIF_ACK_n <= not parHost_acknowledge;
HOSTIF_IRQ_n <= not host_irq;
parHost_chipselect <= not HOSTIF_CS_n;
parHost_write <= not HOSTIF_WR_n;
parHost_read <= not HOSTIF_RD_n;
parHost_addressLatchEnable <= not HOSTIF_ALE_n;
inst : component mnSingleHostifDrv
port map (
clk25_clk => clk25,
clk50_clk => clk50,
clk100_clk => clk100,
reset_reset_n => pllLocked,
openmac_0_mii_txEnable => PHY_TXEN,
openmac_0_mii_txData => PHY_TXD,
openmac_0_mii_txClk => PHY_TXCLK,
openmac_0_mii_rxError => PHY_RXER,
openmac_0_mii_rxDataValid => PHY_RXDV,
openmac_0_mii_rxData => PHY_RXD,
openmac_0_mii_rxClk => PHY_RXCLK,
openmac_0_smi_nPhyRst => PHY_RESET_n,
openmac_0_smi_clk => PHY_MDC,
openmac_0_smi_dio => PHY_MDIO,
tri_state_0_tcm_address_out => sramAddr,
tri_state_0_tcm_read_n_out => SRAM_OE_n,
tri_state_0_tcm_byteenable_n_out => SRAM_BE_n,
tri_state_0_tcm_write_n_out => SRAM_WE_n,
tri_state_0_tcm_data_out => SRAM_DQ,
tri_state_0_tcm_chipselect_n_out => SRAM_CE_n,
pcp_0_benchmark_pio_export => open,
epcs_flash_dclk => EPCS_DCLK,
epcs_flash_sce => EPCS_SCE,
epcs_flash_sdo => EPCS_SDO,
epcs_flash_data0 => EPCS_DATA0,
hostinterface_0_irqout_irq => host_irq,
hostinterface_0_parhost_chipselect => parHost_chipselect,
hostinterface_0_parhost_read => parHost_read,
hostinterface_0_parhost_write => parHost_write,
hostinterface_0_parhost_addressLatchEnable => parHost_addressLatchEnable,
hostinterface_0_parhost_acknowledge => parHost_acknowledge,
hostinterface_0_parhost_byteenable => HOSTIF_BE,
hostinterface_0_parhost_addressData => HOSTIF_AD
);
-- Pll Instance
pllInst : pll
port map (
inclk0 => EXT_CLK,
c0 => clk50,
c1 => clk100,
c2 => clk25,
c3 => open,
locked => pllLocked
);
end rtl;
| gpl-2.0 | 5a5c01cd565dd66b2520154474d1382f | 0.480702 | 4.212918 | false | false | false | false |
s-kostyuk/course_project_csch | pilot_processor_combined/operational_unit.vhd | 1 | 3,520 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_signed.all;
use IEEE.STD_logic_arith.all;
entity operational_unit is
generic(
N: integer := 4;
M: integer := 8
);
port(
clk,rst : in STD_LOGIC;
y : in STD_LOGIC_VECTOR(25 downto 1);
COP : in std_logic;
d1 : in STD_LOGIC_VECTOR(2*N-1 downto 0);
d2 : in STD_LOGIC_VECTOR(N-1 downto 0);
rl, rh : out STD_LOGIC_VECTOR(N-1 downto 0);
x : out STD_LOGIC_vector(10 downto 0);
IRQ1, IRQ2 : out std_logic
);
end operational_unit;
architecture operational_unit of operational_unit is
signal A,Ain: STD_LOGIC_VECTOR(2*N-1 downto 0) ;
signal B1,B1in: STD_LOGIC_VECTOR(N-1 downto 0) ;
signal B2,B2in: STD_LOGIC_VECTOR(N downto 0) ;
signal CnT, CnTin: std_logic_vector(M-1 downto 0);
signal C, Cin: STD_LOGIC_VECTOR(N-1 downto 0) ;
signal overflow, carry: std_logic;
signal of_in, cf_in: std_logic;
signal of_sum, cf_sum: std_logic;
signal TgS, TgSin: std_logic;
signal sum_result: std_logic_vector(N-1 downto 0);
component adder is
generic(
N: integer := 4
);
port(A, B: in std_logic_vector(N-1 downto 0);
Cin: in std_logic;
S: out std_logic_vector(N-1 downto 0);
Cout: out std_logic;
overflow: out std_logic);
end component;
begin
process(clk,rst)is
begin
if rst='0' then
A <= (others=>'0');
B1 <= (others=>'0');
B2 <= (others=>'0');
TgS <= '0';
Overflow <= '0';
Carry <= '0';
CnT <= (others=>'0');
elsif rising_edge(clk)then
A <= Ain;
B1 <= B1in;
B2 <= B2in;
TgS <= TgSin;
CnT <= CnTin;
C <= Cin;
Overflow <= of_in;
Carry <= cf_in;
end if;
end process;
-- Ïîäêëþ÷åíèå ñóììàòîðà
SUM : adder port map(A => C, B => A(N-1 downto 0), Cin => '0', Cout => cf_sum, overflow => of_sum, S => sum_result);
-- Ðåàëèçàöèÿ ìèêðîîïåðàöèé
Ain <= D1 when y(1)='1'
else (A(2*N-1 downto N-1) + not B2 + 1) & A(N-2 downto 0) when y(17) = '1'
else (A(2*N-1 downto N-1) + B2) & A(N-2 downto 0) when y(18) = '1'
else A(2*N-2 downto 0) & '0' when y(21) = '1'
else A;
B1in <= D2 when y(2) = '1'
else C(0) & B1(N-1 downto 1) when y(7) = '1'
else B1;
Cin <= (others => '0') when y(3) = '1'
else sum_result when y(5) = '1'
else carry & C(N-1 downto 1) when y(9) = '1'
else C(N-1)& C(N-1 downto 1) when y(10) = '1'
else C + not A(N-1 downto 0) + 1 when y(11) = '1'
else C(N-2 downto 0) & '1' when y(19) = '1'
else C(N-2 downto 0) & '0' when y(20) = '1'
else C + 1 when y(22) = '1'
else C;
cf_in <= cf_sum when y(5) = '1'
else carry;
of_in <= of_sum when y(5) = '1'
else overflow;
CnTin <= conv_std_logic_vector(N, M) when y(3) = '1'
else CnT - 1 when y(8) = '1'
else CnT;
TgSin <= B1(0) when y(6) = '1'
else A(2*N-1) when y(15) = '1'
else TgS;
RL <= B1 when y(12) = '1'
else C when y(23) = '1'
else (others => 'Z');
RH <= C when y(13) = '1'
else (others => 'Z');
B2in <= D2 & '0' when y(14) = '1'
else B2(N) & B2(N downto 1) when y(16) = '1'
else B2;
IRQ1 <= '1' when y(24) = '1'
else '0';
IRQ2 <= '1' when y(25) = '1'
else '0';
-- Îñâåäîìèòåëüíûå ñèãíàëû
x(0) <= COP;
x(1) <= B1(0);
x(2) <= overflow;
x(3) <= '1' when CnT = 0 else '0';
x(4) <= TgS;
x(5) <= '1' when B2 = 0 else '0';
x(6) <= A(2*N-1) xor B2(N);
x(7) <= A(2*N-1) xor TgS;
x(8) <= B2(N);
x(9) <= B2(N) xor TgS;
x(10) <= '1' when A = 0 else '0';
end operational_unit; | mit | a135126107e9c89e424ada6be2c2b87b | 0.540625 | 2.222222 | false | false | false | false |
dangpzanco/sistemas-digitais | flipf.vhd | 1 | 417 | library ieee;
use ieee.std_logic_1164.all;
entity flipf is port (
CLK, RST, EN: in std_logic;
D: in std_logic_vector(7 downto 0);
Q: out std_logic_vector(7 downto 0)
);
end flipf;
architecture behv of flipf is
begin
process(CLK,D,EN)
begin
if RST = '0' then
Q <= (others => '0');
elsif (CLK'event and CLK = '1') then
if EN = '1' then
Q <= D;
end if;
end if;
end process;
end behv; | mit | b7fd6d3bab71306b1e03d6a68610c703 | 0.611511 | 2.590062 | false | false | false | false |
sergev/vak-opensource | hardware/dlx/reg_1_out-behaviour.vhdl | 1 | 1,602 | --------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: reg_1_out-behaviour.vhdl,v $ $Revision: 2.1 $ $Date: 1993/11/02 19:04:21 $
--
--------------------------------------------------------------------------
--
-- Behavioural architecture of register with one tri-state output.
--
architecture behaviour of reg_1_out is
begin
reg: process (d, latch_en, out_en)
variable latched_value : dlx_word;
begin
if latch_en = '1' then
latched_value := d;
end if;
if out_en = '1' then
q <= latched_value after Tpd;
else
q <= null after Tpd;
end if;
end process reg;
end behaviour;
| apache-2.0 | e254f74b84340613f2a67e45f51e18f2 | 0.586767 | 3.926471 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/common/openmac/src/openMAC_DMAmaster.vhd | 2 | 20,614 | -------------------------------------------------------------------------------
-- Entity : openMAC_DMAmaster
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.log2;
use ieee.math_real.ceil;
library work;
use work.global.all;
entity openMAC_DMAmaster is
generic(
simulate : boolean := false;
dma_highadr_g : integer := 31;
gen_tx_fifo_g : boolean := true;
gen_rx_fifo_g : boolean := true;
m_burstcount_width_g : integer := 4;
m_burstcount_const_g : boolean := true;
m_tx_burst_size_g : integer := 16;
m_rx_burst_size_g : integer := 16;
tx_fifo_word_size_g : integer := 32;
rx_fifo_word_size_g : integer := 32;
fifo_data_width_g : integer := 16;
gen_dma_observer_g : boolean := true
);
port(
dma_clk : in std_logic;
dma_req_overflow : in std_logic;
dma_req_rd : in std_logic;
dma_req_wr : in std_logic;
m_clk : in std_logic;
m_readdatavalid : in std_logic;
m_waitrequest : in std_logic;
mac_rx_off : in std_logic;
mac_tx_off : in std_logic;
rst : in std_logic;
dma_addr : in std_logic_vector(dma_highadr_g downto 1);
dma_dout : in std_logic_vector(15 downto 0);
dma_rd_len : in std_logic_vector(11 downto 0);
m_readdata : in std_logic_vector(fifo_data_width_g-1 downto 0);
dma_ack_rd : out std_logic;
dma_ack_wr : out std_logic;
dma_rd_err : out std_logic;
dma_wr_err : out std_logic;
m_read : out std_logic;
m_write : out std_logic;
dma_din : out std_logic_vector(15 downto 0);
m_address : out std_logic_vector(dma_highadr_g downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(fifo_data_width_g/8-1 downto 0);
m_writedata : out std_logic_vector(fifo_data_width_g-1 downto 0)
);
end openMAC_DMAmaster;
architecture strct of openMAC_DMAmaster is
---- Component declarations -----
component dma_handler
generic(
dma_highadr_g : integer := 31;
gen_dma_observer_g : boolean := true;
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
rx_fifo_word_size_log2_g : natural := 5;
tx_fifo_word_size_log2_g : natural := 5
);
port (
dma_addr : in std_logic_vector(dma_highadr_g downto 1);
dma_clk : in std_logic;
dma_rd_len : in std_logic_vector(11 downto 0);
dma_req_overflow : in std_logic;
dma_req_rd : in std_logic;
dma_req_wr : in std_logic;
mac_rx_off : in std_logic;
mac_tx_off : in std_logic;
rst : in std_logic;
rx_wr_clk : in std_logic;
rx_wr_empty : in std_logic;
rx_wr_full : in std_logic;
rx_wr_usedw : in std_logic_vector(rx_fifo_word_size_log2_g-1 downto 0);
tx_rd_clk : in std_logic;
tx_rd_empty : in std_logic;
tx_rd_full : in std_logic;
tx_rd_usedw : in std_logic_vector(tx_fifo_word_size_log2_g-1 downto 0);
dma_ack_rd : out std_logic;
dma_ack_wr : out std_logic;
dma_addr_out : out std_logic_vector(dma_highadr_g downto 1);
dma_new_addr_rd : out std_logic;
dma_new_addr_wr : out std_logic;
dma_new_len : out std_logic;
dma_rd_err : out std_logic;
dma_rd_len_out : out std_logic_vector(11 downto 0);
dma_wr_err : out std_logic;
rx_aclr : out std_logic;
rx_wr_req : out std_logic;
tx_rd_req : out std_logic
);
end component;
component master_handler
generic(
dma_highadr_g : integer := 31;
fifo_data_width_g : integer := 16;
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
m_burst_wr_const_g : boolean := true;
m_burstcount_width_g : integer := 4;
m_rx_burst_size_g : integer := 16;
m_tx_burst_size_g : integer := 16;
rx_fifo_word_size_log2_g : natural := 5;
tx_fifo_word_size_log2_g : natural := 5
);
port (
dma_addr_in : in std_logic_vector(dma_highadr_g downto 1);
dma_len_rd : in std_logic_vector(11 downto 0);
dma_new_addr_rd : in std_logic;
dma_new_addr_wr : in std_logic;
dma_new_len_rd : in std_logic;
m_clk : in std_logic;
m_readdatavalid : in std_logic;
m_waitrequest : in std_logic;
mac_rx_off : in std_logic;
mac_tx_off : in std_logic;
rst : in std_logic;
rx_rd_clk : in std_logic;
rx_rd_empty : in std_logic;
rx_rd_full : in std_logic;
rx_rd_usedw : in std_logic_vector(rx_fifo_word_size_log2_g-1 downto 0);
tx_wr_clk : in std_logic;
tx_wr_empty : in std_logic;
tx_wr_full : in std_logic;
tx_wr_usedw : in std_logic_vector(tx_fifo_word_size_log2_g-1 downto 0);
m_address : out std_logic_vector(dma_highadr_g downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(fifo_data_width_g/8-1 downto 0);
m_read : out std_logic;
m_write : out std_logic;
rx_rd_req : out std_logic;
tx_aclr : out std_logic;
tx_wr_req : out std_logic
);
end component;
---- Architecture declarations -----
--constants
constant tx_fifo_word_size_c : natural := natural(tx_fifo_word_size_g);
constant tx_fifo_word_size_log2_c : natural := natural(ceil(log2(real(tx_fifo_word_size_c))));
constant rx_fifo_word_size_c : natural := natural(rx_fifo_word_size_g);
constant rx_fifo_word_size_log2_c : natural := natural(ceil(log2(real(rx_fifo_word_size_c))));
---- Signal declarations used on the diagram ----
signal dma_new_addr_rd : std_logic;
signal dma_new_addr_wr : std_logic;
signal dma_new_rd_len : std_logic;
signal m_dma_new_addr_rd : std_logic;
signal m_dma_new_addr_wr : std_logic;
signal m_dma_new_rd_len : std_logic;
signal m_mac_rx_off : std_logic;
signal m_mac_tx_off : std_logic;
signal rx_aclr : std_logic;
signal rx_rd_clk : std_logic;
signal rx_rd_empty : std_logic;
signal rx_rd_full : std_logic;
signal rx_rd_req : std_logic;
signal rx_wr_clk : std_logic;
signal rx_wr_empty : std_logic;
signal rx_wr_full : std_logic;
signal rx_wr_req : std_logic;
signal rx_wr_req_s : std_logic;
signal tx_aclr : std_logic;
signal tx_rd_clk : std_logic;
signal tx_rd_empty : std_logic;
signal tx_rd_empty_s : std_logic;
signal tx_rd_empty_s_l : std_logic;
signal tx_rd_full : std_logic;
signal tx_rd_req : std_logic;
signal tx_rd_req_s : std_logic;
signal tx_rd_sel_word : std_logic;
signal tx_wr_clk : std_logic;
signal tx_wr_empty : std_logic;
signal tx_wr_full : std_logic;
signal tx_wr_req : std_logic;
signal dma_addr_trans : std_logic_vector (dma_highadr_g downto 1);
signal dma_rd_len_trans : std_logic_vector (11 downto 0);
signal rd_data : std_logic_vector (fifo_data_width_g-1 downto 0);
signal rx_rd_usedw : std_logic_vector (rx_fifo_word_size_log2_c-1 downto 0);
signal rx_wr_usedw : std_logic_vector (rx_fifo_word_size_log2_c-1 downto 0);
signal tx_rd_usedw : std_logic_vector (tx_fifo_word_size_log2_c-1 downto 0);
signal tx_wr_usedw : std_logic_vector (tx_fifo_word_size_log2_c-1 downto 0);
signal wr_data : std_logic_vector (fifo_data_width_g-1 downto 0);
signal wr_data_s : std_logic_vector (fifo_data_width_g/2-1 downto 0);
begin
---- Component instantiations ----
THE_DMA_HANDLER : dma_handler
generic map (
dma_highadr_g => dma_highadr_g,
gen_dma_observer_g => gen_dma_observer_g,
gen_rx_fifo_g => gen_rx_fifo_g,
gen_tx_fifo_g => gen_tx_fifo_g,
rx_fifo_word_size_log2_g => rx_fifo_word_size_log2_c,
tx_fifo_word_size_log2_g => tx_fifo_word_size_log2_c
)
port map(
dma_ack_rd => dma_ack_rd,
dma_ack_wr => dma_ack_wr,
dma_addr => dma_addr( dma_highadr_g downto 1 ),
dma_addr_out => dma_addr_trans( dma_highadr_g downto 1 ),
dma_clk => dma_clk,
dma_new_addr_rd => dma_new_addr_rd,
dma_new_addr_wr => dma_new_addr_wr,
dma_new_len => dma_new_rd_len,
dma_rd_err => dma_rd_err,
dma_rd_len => dma_rd_len,
dma_rd_len_out => dma_rd_len_trans,
dma_req_overflow => dma_req_overflow,
dma_req_rd => dma_req_rd,
dma_req_wr => dma_req_wr,
dma_wr_err => dma_wr_err,
mac_rx_off => mac_rx_off,
mac_tx_off => mac_tx_off,
rst => rst,
rx_aclr => rx_aclr,
rx_wr_clk => rx_wr_clk,
rx_wr_empty => rx_wr_empty,
rx_wr_full => rx_wr_full,
rx_wr_req => rx_wr_req,
rx_wr_usedw => rx_wr_usedw( rx_fifo_word_size_log2_c-1 downto 0 ),
tx_rd_clk => tx_rd_clk,
tx_rd_empty => tx_rd_empty,
tx_rd_full => tx_rd_full,
tx_rd_req => tx_rd_req,
tx_rd_usedw => tx_rd_usedw( tx_fifo_word_size_log2_c-1 downto 0 )
);
THE_MASTER_HANDLER : master_handler
generic map (
dma_highadr_g => dma_highadr_g,
fifo_data_width_g => fifo_data_width_g,
gen_rx_fifo_g => gen_rx_fifo_g,
gen_tx_fifo_g => gen_tx_fifo_g,
m_burst_wr_const_g => m_burstcount_const_g,
m_burstcount_width_g => m_burstcount_width_g,
m_rx_burst_size_g => m_rx_burst_size_g,
m_tx_burst_size_g => m_tx_burst_size_g,
rx_fifo_word_size_log2_g => rx_fifo_word_size_log2_c,
tx_fifo_word_size_log2_g => tx_fifo_word_size_log2_c
)
port map(
dma_addr_in => dma_addr_trans( dma_highadr_g downto 1 ),
dma_len_rd => dma_rd_len_trans,
dma_new_addr_rd => m_dma_new_addr_rd,
dma_new_addr_wr => m_dma_new_addr_wr,
dma_new_len_rd => m_dma_new_rd_len,
m_address => m_address( dma_highadr_g downto 0 ),
m_burstcount => m_burstcount( m_burstcount_width_g-1 downto 0 ),
m_burstcounter => m_burstcounter( m_burstcount_width_g-1 downto 0 ),
m_byteenable => m_byteenable( fifo_data_width_g/8-1 downto 0 ),
m_clk => m_clk,
m_read => m_read,
m_readdatavalid => m_readdatavalid,
m_waitrequest => m_waitrequest,
m_write => m_write,
mac_rx_off => m_mac_rx_off,
mac_tx_off => m_mac_tx_off,
rst => rst,
rx_rd_clk => rx_rd_clk,
rx_rd_empty => rx_rd_empty,
rx_rd_full => rx_rd_full,
rx_rd_req => rx_rd_req,
rx_rd_usedw => rx_rd_usedw( rx_fifo_word_size_log2_c-1 downto 0 ),
tx_aclr => tx_aclr,
tx_wr_clk => tx_wr_clk,
tx_wr_empty => tx_wr_empty,
tx_wr_full => tx_wr_full,
tx_wr_req => tx_wr_req,
tx_wr_usedw => tx_wr_usedw( tx_fifo_word_size_log2_c-1 downto 0 )
);
rx_rd_clk <= m_clk;
tx_rd_clk <= dma_clk;
rx_wr_clk <= dma_clk;
tx_wr_clk <= m_clk;
sync1 : entity work.syncTog
generic map (
gStages => 2,
gInit => cInactivated
)
port map (
iSrc_rst => rst,
iSrc_clk => dma_clk,
iSrc_data => mac_tx_off,
iDst_rst => rst,
iDst_clk => m_clk,
oDst_data => m_mac_tx_off
);
sync2 : entity work.syncTog
generic map (
gStages => 2,
gInit => cInactivated
)
port map (
iSrc_rst => rst,
iSrc_clk => dma_clk,
iSrc_data => mac_rx_off,
iDst_rst => rst,
iDst_clk => m_clk,
oDst_data => m_mac_rx_off
);
---- Generate statements ----
gen16bitFifo : if fifo_data_width_g = 16 generate
begin
txFifoGen : if gen_tx_fifo_g generate
begin
TX_FIFO_16 : entity work.asyncFifo
generic map (
gDataWidth => fifo_data_width_g,
gWordSize => tx_fifo_word_size_c,
gSyncStages => 2,
gMemRes => "ON"
)
port map(
iAclr => tx_aclr,
iWrClk => tx_wr_clk,
iWrReq => tx_wr_req,
iWrData => m_readdata,
oWrEmpty => tx_wr_empty,
oWrFull => tx_wr_full,
oWrUsedw => tx_wr_usedw,
iRdClk => tx_rd_clk,
iRdReq => tx_rd_req,
oRdData => rd_data,
oRdEmpty => tx_rd_empty_s,
oRdFull => tx_rd_full,
oRdUsedw => tx_rd_usedw
);
tx_rd_empty_proc :
process(tx_aclr, tx_rd_clk)
begin
if tx_aclr = '1' then
tx_rd_empty_s_l <= '0';
elsif rising_edge(tx_rd_clk) then
if mac_tx_off = '1' then
tx_rd_empty_s_l <= '0';
elsif tx_rd_req = '1' then
if tx_rd_empty_s = '0' then
tx_rd_empty_s_l <= '1';
else
tx_rd_empty_s_l <= '0';
end if;
end if;
end if;
end process;
tx_rd_empty <= tx_rd_empty_s when tx_rd_empty_s_l = '0' else '0';
end generate txFifoGen;
rxFifoGen : if gen_rx_fifo_g generate
begin
RX_FIFO_16 : entity work.asyncFifo
generic map (
gDataWidth => fifo_data_width_g,
gWordSize => rx_fifo_word_size_c,
gSyncStages => 2,
gMemRes => "ON"
)
port map(
iAclr => rx_aclr,
iWrClk => rx_wr_clk,
iWrReq => rx_wr_req,
iWrData => wr_data,
oWrEmpty => rx_wr_empty,
oWrFull => rx_wr_full,
oWrUsedw => rx_wr_usedw,
iRdClk => rx_rd_clk,
iRdReq => rx_rd_req,
oRdData => m_writedata,
oRdEmpty => rx_rd_empty,
oRdFull => rx_rd_full,
oRdUsedw => rx_rd_usedw
);
end generate rxFifoGen;
wr_data <= dma_dout;
dma_din <= rd_data;
end generate gen16bitFifo;
genRxAddrSync : if gen_rx_fifo_g generate
begin
sync4 : entity work.syncTog
generic map (
gStages => 2,
gInit => cInactivated
)
port map (
iSrc_rst => rst,
iSrc_clk => dma_clk,
iSrc_data => dma_new_addr_wr,
iDst_rst => rst,
iDst_clk => m_clk,
oDst_data => m_dma_new_addr_wr
);
end generate genRxAddrSync;
genTxAddrSync : if gen_tx_fifo_g generate
begin
sync5 : entity work.syncTog
generic map (
gStages => 2,
gInit => cInactivated
)
port map(
iSrc_rst => rst,
iSrc_clk => dma_clk,
iSrc_data => dma_new_addr_rd,
iDst_rst => rst,
iDst_clk => m_clk,
oDst_data => m_dma_new_addr_rd
);
sync6 : entity work.syncTog
generic map (
gStages => 2,
gInit => cInactivated
)
port map(
iSrc_rst => rst,
iSrc_clk => dma_clk,
iSrc_data => dma_new_rd_len,
iDst_rst => rst,
iDst_clk => m_clk,
oDst_data => m_dma_new_rd_len
);
end generate genTxAddrSync;
gen32bitFifo : if fifo_data_width_g = 32 generate
begin
txFifoGen32 : if gen_tx_fifo_g generate
begin
TX_FIFO_32 : entity work.asyncFifo
generic map (
gDataWidth => fifo_data_width_g,
gWordSize => tx_fifo_word_size_c,
gSyncStages => 2,
gMemRes => "ON"
)
port map(
iAclr => tx_aclr,
iWrClk => tx_wr_clk,
iWrReq => tx_wr_req,
iWrData => m_readdata,
oWrEmpty => tx_wr_empty,
oWrFull => tx_wr_full,
oWrUsedw => tx_wr_usedw,
iRdClk => tx_rd_clk,
iRdReq => tx_rd_req_s,
oRdData => rd_data,
oRdEmpty => tx_rd_empty_s,
oRdFull => tx_rd_full,
oRdUsedw => tx_rd_usedw
);
tx_rd_proc :
process (tx_rd_clk, rst)
begin
if rst = '1' then
tx_rd_sel_word <= '0';
tx_rd_empty_s_l <= '0';
elsif rising_edge(tx_rd_clk) then
if mac_tx_off = '1' then
tx_rd_sel_word <= '0';
tx_rd_empty_s_l <= '0';
elsif tx_rd_req = '1' then
if tx_rd_sel_word = '0' then
tx_rd_sel_word <= '1';
else
tx_rd_sel_word <= '0';
--workaround...
if tx_rd_empty_s = '0' then
tx_rd_empty_s_l <= '1';
else
tx_rd_empty_s_l <= '0';
end if;
end if;
end if;
end if;
end process;
tx_rd_req_s <= tx_rd_req when tx_rd_sel_word = '0' else '0';
tx_rd_empty <= tx_rd_empty_s when tx_rd_empty_s_l = '0' else '0';
dma_din <= rd_data(15 downto 0) when tx_rd_sel_word = '1' else
rd_data(31 downto 16);
end generate txFifoGen32;
rxFifoGen32 : if gen_rx_fifo_g generate
begin
RX_FIFO_32 : entity work.asyncFifo
generic map (
gDataWidth => fifo_data_width_g,
gWordSize => rx_fifo_word_size_c,
gSyncStages => rx_fifo_word_size_log2_c,
gMemRes => "ON"
)
port map(
iAclr => rx_aclr,
iWrClk => rx_wr_clk,
iWrReq => rx_wr_req_s,
iWrData => wr_data,
oWrEmpty => rx_wr_empty,
oWrFull => rx_wr_full,
oWrUsedw => rx_wr_usedw,
iRdClk => rx_rd_clk,
iRdReq => rx_rd_req,
oRdData => m_writedata,
oRdEmpty => rx_rd_empty,
oRdFull => rx_rd_full,
oRdUsedw => rx_rd_usedw
);
rx_wr_proc :
process (rx_wr_clk, rst)
variable toggle : std_logic;
begin
if rst = '1' then
wr_data_s <= (others => '0');
toggle := '0';
rx_wr_req_s <= '0';
elsif rising_edge(rx_wr_clk) then
rx_wr_req_s <= '0';
if mac_rx_off = '1' then
if toggle = '1' then
rx_wr_req_s <= '1';
end if;
toggle := '0';
elsif rx_wr_req = '1' then
if toggle = '0' then
--capture data
wr_data_s <= dma_dout;
toggle := '1';
else
rx_wr_req_s <= '1';
toggle := '0';
end if;
end if;
end if;
end process;
wr_data <= dma_dout & wr_data_s;
end generate rxFifoGen32;
end generate gen32bitFifo;
end strct;
| gpl-2.0 | b4cfe89e162e7d78b5e3b0bf9e0aaf3a | 0.542059 | 3.237632 | false | false | false | false |
hoglet67/AtomGodilVideo | src/AtomGodilVideo.vhd | 1 | 40,266 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:
-- Design Name:
-- Module Name:
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity AtomGodilVideo is
generic (
CImplGraphicsExt : boolean;
CImplSoftChar : boolean;
CImplSID : boolean;
CImplVGA80x40 : boolean;
CImplHWScrolling : boolean;
CImplMouse : boolean;
CImplUart : boolean;
CImplDoubleVideo : boolean;
MainClockSpeed : integer;
DefaultBaud : integer
);
port (
-- clock_vga is a full speed VGA clock (25MHz ish)
clock_vga : in std_logic;
-- clock_main is the main clock
clock_main : in std_logic;
-- A fixed 32MHz clock for the SID
clock_sid_32MHz : in std_logic;
-- As fast a clock as possible for the SID DAC
clock_sid_dac : in std_logic;
-- Reset signal (active high)
reset : in std_logic;
-- Reset signal to 6847 (active high), not currently used
reset_vid : in std_logic;
-- Main Address / Data Bus signals
din : in std_logic_vector (7 downto 0);
dout : out std_logic_vector (7 downto 0);
addr : in std_logic_vector (12 downto 0);
-- 6847 signals
CSS : in std_logic;
AG : in std_logic;
GM : in std_logic_vector (2 downto 0);
nFS : out std_logic;
-- RAM signals
ram_we : in std_logic;
-- SID signals
reg_cs : in std_logic;
reg_we : in std_logic;
-- SID signals
sid_cs : in std_logic;
sid_we : in std_logic;
sid_audio : out std_logic;
sid_audio_d : out std_logic_vector(17 downto 0);
-- PS/2 Mouse signals
PS2_CLK : inout std_logic;
PS2_DATA : inout std_logic;
-- UART signals
uart_cs : in std_logic;
uart_we : in std_logic;
uart_RxD : in std_logic;
uart_TxD : out std_logic;
uart_escape : out std_logic;
uart_break : out std_logic;
-- VGA Signals
final_red : out std_logic;
final_green1 : out std_logic;
final_green0 : out std_logic;
final_blue : out std_logic;
final_vsync : out std_logic;
final_hsync : out std_logic;
final_blank : out std_logic;
-- Default CharSet
charSet : in std_logic;
-- Uart interrupt
uart_irq_n : out std_logic
);
end AtomGodilVideo;
architecture BEHAVIORAL of AtomGodilVideo is
constant MAJOR_VERSION : std_logic_vector(3 downto 0) := "0001";
constant MINOR_VERSION : std_logic_vector(3 downto 0) := "0100";
-- Set this to 0 if you want dark green/dark orange background on text
-- Set this to 1 if you want black background on text (authentic Atom)
constant BLACK_BACKGND : std_logic := '1';
signal clock_vga_en : std_logic;
-- Internal 1MHz clocks for SID
signal div32 : std_logic_vector (4 downto 0);
signal clock_sid_1MHz : std_logic;
-- VGA colour signals out of mc6847, only top 2 bits are used
signal vga_red : std_logic_vector (7 downto 0);
signal vga_green : std_logic_vector (7 downto 0);
signal vga_blue : std_logic_vector (7 downto 0);
signal vga_vsync : std_logic;
signal vga_hsync : std_logic;
signal vga_blank : std_logic;
signal vga_vblank : std_logic;
signal vga_hblank : std_logic;
-- 8Kx8 Dual port video RAM signals
-- Port A connects to Atom and is read/write
-- Port B connects to MC6847 and is read only
signal douta : std_logic_vector (7 downto 0);
signal addrb : std_logic_vector (12 downto 0);
signal doutb : std_logic_vector (7 downto 0);
-- Masked (by nRST) version of the mode control signals
signal mask : std_logic;
signal gm_masked : std_logic_vector (2 downto 0);
signal ag_masked : std_logic;
signal css_masked : std_logic;
-- SID signals
signal sid_do : std_logic_vector (7 downto 0);
-- Atom extension register signals
signal reg_addr : std_logic_vector (4 downto 0);
signal reg_do : std_logic_vector (7 downto 0);
signal extensions : std_logic_vector (7 downto 0);
signal char_addr : std_logic_vector (7 downto 0);
signal ocrx : std_logic_vector (7 downto 0);
signal ocry : std_logic_vector (7 downto 0);
signal octl : std_logic_vector (7 downto 0);
signal octl2 : std_logic_vector (7 downto 0);
signal char_we : std_logic;
signal char_reg : std_logic_vector (7 downto 0);
signal mc6847_an_s : std_logic;
signal mc6847_intn_ext : std_logic;
signal mc6847_inv : std_logic;
signal mc6847_css : std_logic;
signal mc6847_d_final : std_logic_vector (7 downto 0);
signal mc6847_d : std_logic_vector (7 downto 0);
signal mc6847_d_with_pointer : std_logic_vector (7 downto 0);
signal mc6847_char_a : std_logic_vector (10 downto 0);
signal mc6847_addrb : std_logic_vector (12 downto 0);
signal mc6847_addrb_hw : std_logic_vector (12 downto 0);
signal char_d_o : std_logic_vector (7 downto 0);
signal pointer_nr : std_logic_vector (7 downto 0);
signal pointer_nr_rd : std_logic_vector (7 downto 0);
signal pointer_x : std_logic_vector (7 downto 0);
signal pointer_y : std_logic_vector (7 downto 0);
signal pointer_y_inv : std_logic_vector (7 downto 0);
signal pointer_left : std_logic;
signal pointer_middle : std_logic;
signal pointer_right : std_logic;
signal hwscrollmode : std_logic;
signal scroll_left : std_logic_vector (7 downto 0);
signal scroll_right : std_logic_vector (7 downto 0);
signal scroll_h : std_logic_vector (7 downto 0);
signal scroll_top : std_logic_vector (7 downto 0);
signal scroll_bottom : std_logic_vector (7 downto 0);
signal scroll_v : std_logic_vector (7 downto 0);
signal width32 : std_logic;
signal lines : std_logic_vector (7 downto 0);
signal vga80x40mode : std_logic;
signal int_char_a : std_logic_vector (10 downto 0);
signal final_char_a : std_logic_vector (10 downto 0);
signal vga80_R : std_logic;
signal vga80_G : std_logic;
signal vga80_B : std_logic;
signal vga80_vsync : std_logic;
signal vga80_hsync : std_logic;
signal vga80_blank : std_logic;
signal vga80_invert : std_logic;
signal vga80_char_a : std_logic_vector (10 downto 0);
signal vga80_char_d : std_logic_vector (7 downto 0);
signal vga80_addrb : std_logic_vector (12 downto 0);
signal vga80_addrb_hw: std_logic_vector (12 downto 0);
signal uart_do : std_logic_vector (7 downto 0);
signal bank0_douta : std_logic_vector (7 downto 0);
signal bank0_doutb : std_logic_vector (7 downto 0);
signal bank0_we : std_logic;
signal bank1_douta : std_logic_vector (7 downto 0);
signal bank1_doutb : std_logic_vector (7 downto 0);
signal bank1_we : std_logic;
signal bank_sela : std_logic;
signal bank_selb : std_logic;
signal fs_n : std_logic;
signal hs_n : std_logic;
signal hs_n1 : std_logic;
signal CSS1 : std_logic;
signal CSS2 : std_logic;
signal CSS3 : std_logic;
signal AG1 : std_logic;
signal AG2 : std_logic;
signal AG3 : std_logic;
signal GM1 : std_logic_vector (2 downto 0);
signal GM2 : std_logic_vector (2 downto 0);
signal GM3 : std_logic_vector (2 downto 0);
function truncate(x: in std_logic_vector; constant length: in integer)
return std_logic_vector is
variable result : std_logic_vector(length-1 downto 0);
begin
result := x(length-1 downto 0);
return result;
end function;
function modulo5 (x : std_logic_vector(7 downto 0))
return std_logic_vector is
variable tmp1 : std_logic_vector(4 downto 0);
variable tmp2 : std_logic_vector(3 downto 0);
begin
-- uses some tricks from here:
-- http://homepage.cs.uiowa.edu/~jones/bcd/mod.shtml
-- calculate modulo 15
tmp1 := ('0' & X(7 downto 4)) + ('0' & X(3 downto 0));
if (tmp1 = 30) then
tmp1 := "00000";
elsif (tmp1 >= 15) then
tmp1 := tmp1 - 15;
end if;
-- calculate modulo 5
tmp2 := tmp1(3 downto 0);
if (tmp2 >= 10) then
tmp2 := tmp2 - 5;
end if;
if (tmp2 >= 5) then
tmp2 := tmp2 - 5;
end if;
return tmp2(2 downto 0);
end modulo5;
begin
-----------------------------------------------------------------------------
-- Core
-----------------------------------------------------------------------------
-- Motorola MC6847
-- Original version: https://svn.pacedev.net/repos/pace/sw/src/component/video/mc6847.vhd
-- Updated by AlanD for his Atom FPGA: http://stardot.org.uk/forums/viewtopic.php?f=3&t=6313
-- A further few bugs fixed by myself
Inst_mc6847 : entity work.mc6847
port map (
clk => clock_vga,
clk_ena => clock_vga_en,
reset => reset_vid,
da0 => open,
videoaddr => mc6847_addrb,
dd => mc6847_d_final,
hs_n => hs_n,
fs_n => fs_n,
an_g => ag_masked,
an_s => mc6847_an_s,
intn_ext => mc6847_intn_ext,
gm => gm_masked,
css => mc6847_css,
inv => mc6847_inv,
red => vga_red,
green => vga_green,
blue => vga_blue,
hsync => vga_hsync,
vsync => vga_vsync,
artifact_en => '0',
artifact_set => '0',
artifact_phase => '0',
hblank => vga_hblank,
vblank => vga_vblank,
cvbs => open,
black_backgnd => BLACK_BACKGND,
char_a => mc6847_char_a,
char_d_o => char_d_o
);
vga_blank <= vga_vblank or vga_hblank;
nFS <= fs_n;
mc6847_d_final <= mc6847_d_with_pointer when CImplMouse else mc6847_d;
Optional_not_DoubleVideo: if not CImplDoubleVideo generate
-- 8Kx8 Dual port video RAM
-- Port A connects to Atom and is read/write
-- Port B connects to MC6847 and is read only
Inst_VideoRam : entity work.VideoRam
port map (
clka => clock_main,
wea => ram_we,
addra => addr,
dina => din,
douta => douta,
clkb => clock_vga,
web => '0',
addrb => addrb,
dinb => (others => '0'),
doutb => doutb
);
end generate;
Optional_DoubleVideo: if CImplDoubleVideo generate
-- Double Buffered 8Kx8 Dual port video RAM
-- Port A connects to Atom and is read/write
-- Port B connects to MC6847 and is read only
Inst_VideoRam0 : entity work.VideoRam
port map (
clka => clock_main,
wea => bank0_we,
addra => addr,
dina => din,
douta => bank0_douta,
clkb => clock_vga,
web => '0',
addrb => addrb,
dinb => (others => '0'),
doutb => bank0_doutb
);
Inst_VideoRam1 : entity work.VideoRam
port map (
clka => clock_main,
wea => bank1_we,
addra => addr,
dina => din,
douta => bank1_douta,
clkb => clock_vga,
web => '0',
addrb => addrb,
dinb => (others => '0'),
doutb => bank1_doutb
);
bank0_we <= ram_we when bank_sela = '0' else '0';
bank1_we <= ram_we when bank_sela = '1' else '0';
douta <= bank1_douta when bank_sela = '1' else bank0_douta;
doutb <= bank1_doutb when bank_selb = '1' else bank0_doutb;
end generate;
bank_sela <= extensions(4) when CImplDoubleVideo else '0';
bank_selb <= extensions(5) when CImplDoubleVideo else '0';
hwscrollmode <= extensions(6) when CImplHWScrolling else '0';
addrb <= mc6847_addrb when vga80x40mode = '0' and hwscrollmode = '0' else
mc6847_addrb_hw when vga80x40mode = '0' and hwscrollmode = '1' else
vga80_addrb when hwscrollmode = '0' else
vga80_addrb_hw;
-- VGA Multiplexing between two controllers
vga80x40mode <= extensions(7) when CImplVGA80x40 else '0';
final_red <= vga_red(7) when vga80x40mode = '0' else vga80_R;
final_green1 <= vga_green(7) when vga80x40mode = '0' else vga80_G;
final_green0 <= vga_green(6) when vga80x40mode = '0' else vga80_G;
final_blue <= vga_blue(7) when vga80x40mode = '0' else vga80_B;
final_vsync <= vga_vsync when vga80x40mode = '0' else vga80_vsync;
final_hsync <= vga_hsync when vga80x40mode = '0' else vga80_hsync;
final_blank <= vga_blank when vga80x40mode = '0' else vga80_blank;
-- int_char_a(10 downto 4) select character 0..127
-- int_chat_a( 3 downto 0) select row 0..11
int_char_a <= mc6847_char_a when vga80x40mode = '0' else vga80_char_a;
final_char_a <= int_char_a when extensions(3) = '0' or int_char_a(10) = '1' else
int_char_a(9 downto 4) & "01100" when int_char_a(3 downto 0) = "0010" else
int_char_a(9 downto 4) & "01101" when int_char_a(3 downto 0) = "0011" else
int_char_a(9 downto 4) & "01110" when int_char_a(3 downto 0) = "0100" else
int_char_a(9 downto 4) & "01111" when int_char_a(3 downto 0) = "0101" else
int_char_a(9 downto 4) & "11100" when int_char_a(3 downto 0) = "0110" else
int_char_a(9 downto 4) & "11101" when int_char_a(3 downto 0) = "0111" else
int_char_a(9 downto 4) & "11110" when int_char_a(3 downto 0) = "1000" else
int_char_a(9 downto 4) & "11111" when int_char_a(3 downto 0) = "1001" else
"00000000000";
-- Hold internal reset low for two frames after nRST released
-- This avoids any diaplay glitches
process (clock_vga)
variable state : std_logic_vector(2 downto 0);
begin
if rising_edge(clock_vga) then
if (reset = '1') then
state := "000";
elsif (state = "000" and vga_vsync = '0') then
state := "001";
elsif (state = "001" and vga_vsync = '1') then
state := "010";
elsif (state = "010" and vga_vsync = '0') then
state := "011";
elsif (state = "011" and vga_vsync = '1') then
state := "100";
end if;
mask <= state(2);
end if;
end process;
process (clock_vga)
begin
if rising_edge(clock_vga) then
-- Sample the mode inputs, so we can later use a majority vote system
-- This is necessary to make these imputs more robust to noise
CSS1 <= CSS;
CSS2 <= CSS1;
CSS3 <= CSS2;
AG1 <= AG;
AG2 <= AG1;
AG3 <= AG2;
GM1 <= GM;
GM2 <= GM1;
GM3 <= GM2;
clock_vga_en <= not clock_vga_en;
hs_n1 <= hs_n;
-- Sample the mode inputs only during the active part of the display
if (hs_n = '0' and hs_n1 = '1' and fs_n = '1') then
-- During reset, force the 6847 mode select inputs low
-- (this is necessary to stop the mode changing during reset, as the GODIL has 1.5K pullups)
if (mask = '1') then
gm_masked(0) <= (GM1(0) and GM2(0)) or (GM2(0) and GM3(0)) or (GM1(0) and GM3(0));
gm_masked(1) <= (GM1(1) and GM2(1)) or (GM2(1) and GM3(1)) or (GM1(1) and GM3(1));
gm_masked(2) <= (GM1(2) and GM2(2)) or (GM2(2) and GM3(2)) or (GM1(2) and GM3(2));
ag_masked <= (AG1 and AG2) or (AG2 and AG3) or (AG1 and AG3);
css_masked <= (CSS1 and CSS2) or (CSS2 and CSS3) or (CSS1 and CSS3);
else
gm_masked <= (others => '0');
ag_masked <= '0';
css_masked <= '0';
end if;
end if;
end if;
end process;
reg_addr <= addr(4 downto 0);
reg_do <= extensions when reg_addr = "00000" and (CImplGraphicsExt or CImplVGA80x40 or CImplHWScrolling or CImplDoubleVideo) else
char_addr when reg_addr = "00001" and CImplSoftChar else
ocrx when reg_addr = "00010" and CImplVGA80x40 else
ocry when reg_addr = "00011" and CImplVGA80x40 else
octl when reg_addr = "00100" and CImplVGA80x40 else
octl2 when reg_addr = "00101" and CImplVGA80x40 else
scroll_h when reg_addr = "00110" and CImplHWScrolling else
scroll_v when reg_addr = "00111" and CImplHWScrolling else
pointer_x when reg_addr = "01000" and CImplMouse else
pointer_y_inv when reg_addr = "01001" and CImplMouse else
pointer_nr_rd when reg_addr = "01010" and CImplMouse else
scroll_left when reg_addr = "01011" and CImplHWScrolling else
scroll_right when reg_addr = "01100" and CImplHWScrolling else
scroll_top when reg_addr = "01101" and CImplHWScrolling else
scroll_bottom when reg_addr = "01110" and CImplHWScrolling else
MAJOR_VERSION & MINOR_VERSION when reg_addr = "01111" else
char_reg when CImplSoftChar else
x"f1";
dout <= sid_do when sid_cs = '1' and CimplSID else
uart_do when uart_cs = '1' and CimplUart else
reg_do when reg_cs = '1' else
douta;
-----------------------------------------------------------------------------
-- Optional Soft Character Set
-----------------------------------------------------------------------------
Optional_SoftChar: if CImplSoftChar generate
-- A register to control extra 6847 features
process (clock_main)
begin
if rising_edge(clock_main) then
if (reset = '1') then
char_addr <= (others => '0');
elsif (reg_cs = '1' and reg_we = '1') then
case reg_addr is
-- char_addr register
when "00001" =>
char_addr <= din;
when others =>
end case;
end if;
end if;
end process;
char_we <= '1' when reg_cs = '1' and reg_we = '1' and char_addr(7) = '1' and reg_addr(4) = '1' else '0';
---- ram for char generator
charrom_inst : entity work.CharRam
port map(
clka => clock_main,
wea => char_we,
addra(10 downto 4) => char_addr(6 downto 0),
addra(3 downto 0) => addr(3 downto 0),
dina => din,
douta => char_reg,
clkb => clock_vga,
web => '0',
addrb => final_char_a,
dinb => (others => '0'),
doutb => char_d_o
);
end generate;
Optional_Not_SoftChar: if not CImplSoftChar generate
---- ram for char generator
charrom_inst : entity work.CharRom
port map(
CLK => clock_vga,
ADDR => final_char_a,
DATA => char_d_o
);
end generate;
-----------------------------------------------------------------------------
-- Graphics Extension Register
-- shared by several optional functions
-----------------------------------------------------------------------------
Optional_GraphicsExtReg: if CImplGraphicsExt or CImplVGA80x40 or CImplHWScrolling generate
-- A register to control extra 6847 features
process (clock_main)
begin
if rising_edge(clock_main) then
if (reset = '1') then
extensions <= (others => '0');
extensions(3) <= charSet;
elsif (reg_cs = '1' and reg_we = '1') then
case reg_addr is
-- extensions register
when "00000" =>
extensions <= din;
when others =>
end case;
end if;
end if;
end process;
end generate;
-----------------------------------------------------------------------------
-- Optional Graphics Modes
-----------------------------------------------------------------------------
Optional_GraphicsExt: if CImplGraphicsExt generate
-- Adjust the inputs to the 6847 based on the extensions register
process (extensions, doutb, css_masked, ag_masked)
begin
case extensions(2 downto 0) is
-- Text plus 8 Colour Semigraphics 4
when "001" =>
mc6847_an_s <= doutb(6);
mc6847_intn_ext <= '0';
mc6847_inv <= doutb(7);
-- Replace the 64-127 and 192-255 blocks with Semigraphics 4
-- Only tweak the data bus when actually displaying semigraphics
if (ag_masked = '0' and doutb(6) = '1') then
mc6847_d <= '0' & doutb(7) & doutb(5 downto 0);
else
mc6847_d <= doutb;
end if;
mc6847_css <= css_masked;
-- 2 Colour Text Only
when "010" =>
mc6847_an_s <= '0';
mc6847_intn_ext <= '0';
mc6847_inv <= doutb(7);
if (ag_masked = '0' and doutb(6) = '1') then
mc6847_d <= "00" & doutb(5 downto 0);
else
mc6847_d <= doutb;
end if;
mc6847_css <= doutb(6) xor css_masked;
-- 4 Colour Semigraphics 6 Only
when "011" =>
mc6847_an_s <= '1';
mc6847_intn_ext <= '1';
mc6847_inv <= doutb(7);
mc6847_d <= doutb;
mc6847_css <= css_masked;
-- Extended character set, lower case replaces Red Semigraphics
-- 00-3F - Normal Upper Case
-- 40-7F - Yellow Semigraphics 6
-- 80-BF - Inverse Upper Case
-- C0-FF - Normal Lower Case
when "100" =>
mc6847_an_s <= doutb(6) and not doutb(7);
mc6847_intn_ext <= doutb(6);
mc6847_inv <= not doutb(6) and doutb(7);
mc6847_d <= doutb;
mc6847_css <= css_masked;
-- Extended character set, lower case replaces Red and Yello Semigraphics
-- 00-3F - Normal Upper Case
-- 40-7F - Normal Lower Case
-- 80-BF - Inverse Upper Case
-- C0-FF - Inverse Lower Case
when "101" =>
mc6847_an_s <= '0';
mc6847_intn_ext <= '0';
mc6847_inv <= doutb(7);
mc6847_d <= doutb;
mc6847_css <= css_masked;
-- Extended character set, lower case replaces inverse
-- 00-3F - Normal Upper Case
-- 40-7F - Yellow Semigraphics 6 -- Blue
-- 80-BF - Normal Lower Case
-- C0-FF - Red Semigraphics 6
when "110" =>
mc6847_an_s <= doutb(6);
mc6847_intn_ext <= doutb(6);
mc6847_inv <= '0';
if (ag_masked = '0' and doutb(7 downto 6) = "10") then
mc6847_d <= "01" & doutb(5 downto 0);
else
mc6847_d <= doutb;
end if;
mc6847_css <= css_masked;
-- Just replace inverse upper case (32 chars) with lower case
-- 00-3F - Normal Upper Case
-- 40-7F - Yellow Semigraphics 6
-- 80-BF - Lower Case/Inverse Upper Case
-- C0-FF - Red Semigraphics 6
when "111" =>
mc6847_an_s <= doutb(6);
mc6847_intn_ext <= doutb(6);
mc6847_inv <= doutb(7) and doutb(5);
if (ag_masked = '0' and doutb(7 downto 5) = "100") then
mc6847_d <= "01" & doutb(5 downto 0);
else
mc6847_d <= doutb;
end if;
mc6847_css <= css_masked;
-- Default Atom Behaviour
-- 00-3F - Normal Upper Case
-- 40-7F - Yellow Semigraphics 6
-- 80-BF - Inverse Upper Case
-- C0-FF - Red Semigraphics 6
when others =>
mc6847_an_s <= doutb(6);
mc6847_intn_ext <= doutb(6);
mc6847_inv <= doutb(7);
mc6847_d <= doutb;
mc6847_css <= css_masked;
end case;
end process;
end generate;
Optional_Not_GraphicsExt: if not CImplGraphicsExt generate
mc6847_an_s <= doutb(6);
mc6847_intn_ext <= doutb(6);
mc6847_inv <= doutb(7);
mc6847_d <= doutb;
mc6847_css <= css_masked;
end generate;
-----------------------------------------------------------------------------
-- Optional SID
-----------------------------------------------------------------------------
Optional_SID: if CImplSID generate
Inst_sid6581: entity work.sid6581
port map (
clk_1MHz => clock_sid_1MHz,
clk32 => clock_sid_32MHz,
clk_DAC => clock_sid_dac,
reset => reset,
cs => sid_cs,
we => sid_we,
addr => reg_addr,
di => din,
do => sid_do,
pot_x => '0',
pot_y => '0',
audio_out => sid_audio,
audio_data => sid_audio_d
);
-- Clock_Sid_1MHz is derived by dividing down thw 32MHz clock
process (clock_sid_32MHz)
begin
if rising_edge(clock_sid_32MHz) then
div32 <= div32 + 1;
end if;
end process;
clock_sid_1MHz <= div32(4);
end generate;
-----------------------------------------------------------------------------
-- Optional VGA80x40 Mode
-----------------------------------------------------------------------------
Optional_VGA80x40: if CImplVGA80x40 generate
-- A register to control extra 6847 features
process (clock_main)
begin
if rising_edge(clock_main) then
if (reset = '1') then
ocrx <= (others => '0');
ocry <= (others => '0');
-- Default to Green Foreground
octl <= "10000010";
-- Default to Black Background
octl2 <= "00000000";
elsif (reg_cs = '1' and reg_we = '1') then
case reg_addr is
when "00010" =>
ocrx <= din;
when "00011" =>
ocry <= din;
when "00100" =>
octl <= din;
when "00101" =>
octl2 <= din;
when others =>
end case;
end if;
end if;
end process;
Inst_vga80x40: entity work.vga80x40 PORT MAP(
reset => reset_vid,
clk25MHz => clock_vga,
TEXT_A => vga80_addrb,
TEXT_D => mc6847_d,
FONT_A(10 downto 0) => vga80_char_a,
FONT_A(11) => vga80_invert,
FONT_D => vga80_char_d,
ocrx => ocrx,
ocry => ocry,
octl => octl,
octl2 => octl2,
R => vga80_R,
G => vga80_G,
B => vga80_B,
hsync => vga80_hsync,
vsync => vga80_vsync,
blank => vga80_blank
);
vga80_char_d <= char_d_o when vga80_invert='0' else char_d_o xor "11111111";
end generate;
-----------------------------------------------------------------------------
-- Optional HW Scrolling of Atom Modes
-----------------------------------------------------------------------------
Optional_HWScrolling_Atom: if CImplHWScrolling generate
-- A register to control extra 6847 features
process (clock_main)
begin
if rising_edge(clock_main) then
if (reset = '1') then
scroll_h <= (others => '0');
scroll_left <= (others => '0');
scroll_right <= (others => '0');
scroll_v <= (others => '0');
scroll_top <= (others => '0');
scroll_bottom <= (others => '0');
elsif (reg_cs = '1' and reg_we = '1') then
case reg_addr is
when "00110" =>
scroll_h <= din;
when "00111" =>
scroll_v <= din;
when "01011" =>
scroll_left <= din;
when "01100" =>
scroll_right <= din;
when "01101" =>
scroll_top <= din;
when "01110" =>
scroll_bottom <= din;
when others =>
end case;
end if;
end if;
end process;
-- 32 bytes wide in Modes 0, 2a, 3a, 4a, 4
-- 16 bytes wide in Modes 1a, 1, 2, 3
width32 <= '1' when ag_masked = '0' or
gm_masked = "010" or gm_masked = "100" or
gm_masked = "110" or gm_masked = "111" else '0';
lines <= "00010000" when ag_masked = '0' else
"01000000" when gm_masked = "000" or gm_masked = "001" or gm_masked = "010" else
"01100000" when gm_masked = "011" or gm_masked = "100" else
"11000000";
-- Hardware Scrolling of atom modes
-- mc6847_addrb -> mc6847_addrb_hw
process (lines, width32, scroll_left, scroll_right, scroll_h, scroll_top, scroll_bottom, scroll_v, mc6847_addrb)
variable x : std_logic_vector(5 downto 0);
variable y : std_logic_vector(8 downto 0);
variable scroll_h_min : std_logic_vector(7 downto 0);
variable scroll_h_max : std_logic_vector(7 downto 0);
variable scroll_v_min : std_logic_vector(7 downto 0);
variable scroll_v_max : std_logic_vector(7 downto 0);
begin
scroll_h_min := scroll_left;
scroll_v_min := scroll_top;
scroll_v_max := lines - scroll_bottom;
if (width32 = '0') then
x := "00" & mc6847_addrb(3 downto 0);
y := "0" & mc6847_addrb(11 downto 4);
scroll_h_max := 16 - scroll_right;
else
x := "0" & mc6847_addrb(4 downto 0);
y := "0" & mc6847_addrb(12 downto 5);
scroll_h_max := 32 - scroll_right;
end if;
if (x >= scroll_h_min and x < scroll_h_max) and (y >= scroll_v_min and y < scroll_v_max) then
x := truncate(x + scroll_h, 6);
if (x >= scroll_h_max) then
x := truncate(x - (scroll_h_max - scroll_h_min), 6);
end if;
y := y + scroll_v;
if (y >= scroll_v_max) then
y := y - (scroll_v_max - scroll_v_min);
end if;
end if;
if (width32 = '0') then
mc6847_addrb_hw(3 downto 0) <= x(3 downto 0);
mc6847_addrb_hw(12 downto 4) <= y;
else
mc6847_addrb_hw(4 downto 0) <= x(4 downto 0);
mc6847_addrb_hw(12 downto 5) <= y(7 downto 0);
end if;
end process;
end generate;
-----------------------------------------------------------------------------
-- Optional HW Scrolling of VGA80x40 Modes
-----------------------------------------------------------------------------
Optional_HWScrolling_VGA80x40: if CImplHWScrolling and CImplVGA80x40 generate
-- Hardware Scrolling of vga80x40 mode
-- vga80_addrb -> vga80_addrb_hw
process (scroll_h, scroll_v, vga80_addrb)
variable addr1 : std_logic_vector(11 downto 0);
variable addr2 : std_logic_vector(13 downto 0);
variable attr : std_logic;
variable display_start : std_logic_vector(11 downto 0);
variable x1 : std_logic_vector(6 downto 0);
variable x2 : std_logic_vector(7 downto 0);
begin
-- determine if this is an attribute access or not
if (vga80_addrb < 3200) then
attr := '0';
else
attr := '1';
end if;
-- calculate an address in the range 0..3199 regardless of whether char or attr being accessed
if (attr = '0') then
addr1 := vga80_addrb(11 downto 0);
else
addr1 := truncate(vga80_addrb - 3200, 12);
end if;
-- calculate x from the address modulo 80
x1 := modulo5(addr1(11 downto 4)) & addr1(3 downto 0);
-- calculate the new x after the scroll_h has been added, modulo 80
x2 := truncate(('0' & x1) + ('0' & scroll_h), 8);
if (x2 >= 80) then
x2 := x2 - 80;
end if;
-- calculate the display start as 80 * scroll_v
display_start := (scroll_v(5 downto 0) & "000000") + ("00" & scroll_v(5 downto 0) & "0000");
-- calculate the new screen start address, extending the precision by one bit
addr2 := ('0' & vga80_addrb) + ("00" & display_start) - ("0000000" & x1) + ("0000000" & x2(6 downto 0));
-- detect wrapping in wrapping in the character and attributevregions
if ((attr = '0' and addr2 >= 3200) or addr2 >= 6400) then
vga80_addrb_hw <= truncate(addr2 - 3200, 13);
else
vga80_addrb_hw <= addr2(12 downto 0);
end if;
end process;
end generate;
-----------------------------------------------------------------------------
-- Optional Mouse
-----------------------------------------------------------------------------
Optional_Mouse: if CImplMouse generate
Inst_Pointer: entity work.Pointer PORT MAP (
CLK => clock_vga,
PO => not pointer_nr(7),
PS => pointer_nr(4 downto 0),
X => pointer_x,
Y => pointer_y,
ADDR => mc6847_addrb,
DIN => mc6847_d,
DOUT => mc6847_d_with_pointer
);
Inst_MouseRefComp: entity work.MouseRefComp
generic map (
MainClockSpeed => MainClockSpeed
)
PORT MAP (
CLK => clock_main,
RESOLUTION => '1', -- select 256x192 resolution
RST => reset,
SWITCH => '0',
LEFT => pointer_left,
MIDDLE => pointer_middle,
NEW_EVENT => open,
RIGHT => pointer_right,
XPOS(7 downto 0) => pointer_x,
XPOS(9 downto 8) => open,
YPOS(7 downto 0) => pointer_y,
YPOS(9 downto 8) => open,
ZPOS => open,
PS2_CLK => PS2_CLK,
PS2_DATA => PS2_DATA
);
pointer_nr_rd <= pointer_nr(7) & "1111" & not pointer_middle & not pointer_right & not pointer_left;
pointer_y_inv <= pointer_y xor "11111111";
process (clock_main)
begin
if rising_edge(clock_main) then
if (reset = '1') then
pointer_nr <= "10000000";
elsif (reg_cs = '1' and reg_we = '1') then
case reg_addr is
when "01010" =>
pointer_nr <= din;
when others =>
end case;
end if;
end if;
end process;
end generate;
-----------------------------------------------------------------------------
-- Optional Mouse
-----------------------------------------------------------------------------
Optional_Uart: if CImplUart generate
inst_miniuart: entity work.miniuart
generic map (
MainClockSpeed => MainClockSpeed,
DefaultBaud => DefaultBaud
)
port map (
wb_clk_i => clock_main,
wb_rst_i => reset,
wb_adr_i => addr(1 downto 0),
wb_dat_i => din,
wb_dat_o => uart_do,
wb_we_i => uart_we,
wb_stb_i => uart_cs,
wb_ack_o => open,
inttx_o => open,
intrx_o => open,
br_clk_i => clock_main,
txd_pad_o => uart_TxD,
rxd_pad_i => uart_RxD,
esc_o => uart_escape,
break_o => uart_break,
uart_irq_n => uart_irq_n
);
end generate;
Optional_Not_Uart: if not CImplUart generate
uart_TxD <= '1';
uart_escape <= '1';
uart_break <= '1';
end generate;
end BEHAVIORAL;
| apache-2.0 | 0b00c316c3dccf504e3b89f89e2ce07b | 0.463046 | 4.082531 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/common/fifo/src/fifoRead-rtl-ea.vhd | 2 | 5,772 | -------------------------------------------------------------------------------
--! @file fifoRead-rtl-ea.vhd
--
--! @brief FIFO read controller
--
--! @details This is a FIFO read controller.
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
--! use global library
use work.global.all;
entity fifoRead is
generic (
gAddrWidth : natural := 4
);
port (
iClk : in std_logic;
iRst : in std_logic;
iRead : in std_logic;
iWrPointer : in std_logic_vector(gAddrWidth downto 0);
oEmpty : out std_logic;
oFull : out std_logic;
oPointer : out std_logic_vector(gAddrWidth downto 0);
oAddress : out std_logic_vector(gAddrWidth-1 downto 0);
oUsedWord : out std_logic_vector(gAddrWidth-1 downto 0)
);
end fifoRead;
architecture rtl of fifoRead is
signal r_ptr_reg : std_logic_vector(gAddrWidth downto 0);
signal r_ptr_next : std_logic_vector(gAddrWidth downto 0);
signal gray1 : std_logic_vector(gAddrWidth downto 0);
signal bin : std_logic_vector(gAddrWidth downto 0);
signal bin1 : std_logic_vector(gAddrWidth downto 0);
signal raddr_all : std_logic_vector(gAddrWidth-1 downto 0);
signal raddr_msb : std_logic;
signal waddr_msb : std_logic;
signal empty_flag : std_logic;
signal full_flag : std_logic;
signal r_elements_wr : std_logic_vector(gAddrWidth downto 0);
signal r_elements_rd : std_logic_vector(gAddrWidth downto 0);
signal r_elements_diff : std_logic_vector(gAddrWidth downto 0);
signal r_elements_reg : std_logic_vector(gAddrWidth-1 downto 0);
signal r_elements_next : std_logic_vector(gAddrWidth-1 downto 0);
begin
--! Clock process for registers.
regProc : process(iRst, iClk)
begin
if iRst = cActivated then
r_ptr_reg <= (others => cInactivated);
r_elements_reg <= (others => cInactivated);
elsif rising_edge(iClk) then
r_ptr_reg <= r_ptr_next;
r_elements_reg <= r_elements_next;
end if;
end process;
-- (gAddrWidth+1)-bit Gray counter
bin <= r_ptr_reg xor (cInactivated & bin(gAddrWidth downto 1));
bin1 <= std_logic_vector(unsigned(bin) + 1);
gray1 <= bin1 xor (cInactivated & bin1(gAddrWidth downto 1));
-- update read pointer
r_ptr_next <= gray1 when iRead = cActivated and empty_flag = cInactivated else
r_ptr_reg;
-- gAddrWidth-bit Gray counter
raddr_msb <= r_ptr_reg(gAddrWidth) xor r_ptr_reg(gAddrWidth-1);
raddr_all <= raddr_msb & r_ptr_reg(gAddrWidth-2 downto 0);
waddr_msb <= iWrPointer(gAddrWidth) xor iWrPointer(gAddrWidth-1);
-- check for FIFO read empty
empty_flag <= cActivated when iWrPointer(gAddrWidth) = r_ptr_reg(gAddrWidth) and
iWrPointer(gAddrWidth-2 downto 0) = r_ptr_reg(gAddrWidth-2 downto 0) and
raddr_msb = waddr_msb else
cInactivated;
-- check for FIFO read full
full_flag <= cActivated when iWrPointer(gAddrWidth) /= r_ptr_reg(gAddrWidth) and
iWrPointer(gAddrWidth-2 downto 0) = r_ptr_reg(gAddrWidth-2 downto 0) and
raddr_msb = waddr_msb else
cInactivated;
-- convert gray value to bin and obtain difference
r_elements_wr <= bin;
r_elements_rd <= iWrPointer xor (cInactivated & r_elements_rd(gAddrWidth downto 1));
r_elements_diff <= std_logic_vector(unsigned(r_elements_rd) - unsigned(r_elements_wr));
r_elements_next <= r_elements_diff(r_elements_next'range);
-- output
oAddress <= raddr_all;
oPointer <= r_ptr_reg;
oUsedWord <= r_elements_reg;
oEmpty <= empty_flag;
oFull <= full_flag;
end rtl;
| gpl-2.0 | aee8e72d4b3ea76169a715a78caac3d0 | 0.61781 | 4.137634 | false | false | false | false |
hoglet67/AtomGodilVideo | src/MINIUART/miniuart.vhd | 1 | 9,944 | -------------------------------------------------------------------------------
-- Title : UART
-- Project : UART
-------------------------------------------------------------------------------
-- File : MiniUart.vhd
-- Author : Philippe CARTON
-- ([email protected])
-- Organization:
-- Created : 15/12/2001
-- Last update : 8/1/2003
-- Platform : Foundation 3.1i
-- Simulators : ModelSim 5.5b
-- Synthesizers: Xilinx Synthesis
-- Targets : Xilinx Spartan
-- Dependency : IEEE std_logic_1164, Rxunit.vhd, Txunit.vhd, utils.vhd
-------------------------------------------------------------------------------
-- Description: Uart (Universal Asynchronous Receiver Transmitter) for SoC.
-- Wishbone compatable.
-------------------------------------------------------------------------------
-- Copyright (c) notice
-- This core adheres to the GNU public license
--
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number :
-- Version :
-- Date :
-- Modifier : name <email>
-- Description :
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity MINIUART is
generic (
MainClockSpeed : integer;
DefaultBaud : integer
);
port (
-- Wishbone signals
WB_CLK_I : in std_logic; -- clock
WB_RST_I : in std_logic; -- Reset input
WB_ADR_I : in std_logic_vector(1 downto 0); -- Adress bus
WB_DAT_I : in std_logic_vector(7 downto 0); -- DataIn Bus
WB_DAT_O : out std_logic_vector(7 downto 0); -- DataOut Bus
WB_WE_I : in std_logic; -- Write Enable
WB_STB_I : in std_logic; -- Strobe
WB_ACK_O : out std_logic; -- Acknowledge
-- process signals
IntTx_O : out std_logic; -- Transmit interrupt: indicate waiting for Byte
IntRx_O : out std_logic; -- Receive interrupt: indicate Byte received
BR_Clk_I : in std_logic; -- Clock used for Transmit/Receive
TxD_PAD_O : out std_logic; -- Tx RS232 Line
RxD_PAD_I : in std_logic; -- Rx RS232 Line
ESC_O : out std_logic;
BREAK_O : out std_logic;
uart_irq_n: out std_logic); -- Serial interrupt to CPU core
end MINIUART;
-- Architecture for UART for synthesis
architecture Behaviour of MINIUART is
component Counter
port (
Clk : in std_logic; -- Clock
Reset : in std_logic; -- Reset input
CE : in std_logic; -- Chip Enable
Count : in std_logic_vector (15 downto 0); -- Count revolution
O : out std_logic); -- Output
end component;
component RxUnit
port (
Clk : in std_logic; -- system clock signal
Reset : in std_logic; -- Reset input
Enable : in std_logic; -- Enable input
ReadA : in std_logic; -- Async Read Received Byte
RxD : in std_logic; -- RS-232 data input
RxAv : out std_logic; -- Byte available
DataO : out std_logic_vector(7 downto 0) -- Byte received
);
end component;
component TxUnit
port (
Clk : in std_logic; -- Clock signal
Reset : in std_logic; -- Reset input
Enable : in std_logic; -- Enable input
LoadA : in std_logic; -- Asynchronous Load
TxD : out std_logic; -- RS-232 data output
Busy : out std_logic; -- Tx Busy
DataI : in std_logic_vector(7 downto 0) -- Byte to transmit
);
end component;
signal RxData : std_logic_vector(7 downto 0); -- Last Byte received
signal RxData1 : std_logic_vector(7 downto 0);
signal TxData : std_logic_vector(7 downto 0); -- Last bytes transmitted
signal SReg : std_logic_vector(3 downto 0); -- Status register
signal CReg : std_logic_vector(7 downto 4); -- Control register
signal EnabRx : std_logic; -- Enable RX unit
signal EnabTx : std_logic; -- Enable TX unit
signal RxAv : std_logic; -- Data Received
signal TxBusy : std_logic; -- Transmiter Busy
signal ReadA : std_logic; -- Async Read receive buffer
signal LoadA : std_logic; -- Async Load transmit buffer
signal Sig0 : std_logic; -- gnd signal
signal Sig1 : std_logic; -- vcc signal
signal Divisor : std_logic_vector(15 downto 0); -- Baud Rate
signal TxBusy_last : std_logic;
signal RxAv_last : std_logic;
begin
sig0 <= '0';
sig1 <= '1';
Uart_Rxrate : Counter -- Baud Rate adjust
port map (BR_CLK_I, sig0, sig1, Divisor, EnabRx);
Uart_Txrate : Counter -- 4 Divider for Tx
port map (BR_CLK_I, Sig0, EnabRx, std_logic_vector(to_unsigned(4, 16)), EnabTx);
-- Uart_TxUnit : TxUnit
-- port map (BR_CLK_I, WB_RST_I, EnabTX, LoadA, TxD_PAD_O, TxBusy, TxData, IntTxFlag, IntTxEn);
Uart_TxUnit : TxUnit
port map (
Clk => BR_CLK_I, -- Clock signal
Reset => WB_RST_I, -- Reset input
Enable => EnabTX, -- Enable input
LoadA => LoadA, -- Asynchronous Load
TxD => TxD_PAD_O, -- RS-232 data output
Busy => TxBusy, -- Tx Busy
DataI => TxData -- Byte to transmit
);
-- Uart_RxUnit : RxUnit
-- port map (BR_CLK_I, WB_RST_I, EnabRX, ReadA, RxD_PAD_I, RxAv, RxData, IntRxFlag, IntRxEn);
Uart_RxUnit : RxUnit
port map (
Clk => BR_CLK_I, -- system clock signal
Reset => WB_RST_I, -- Reset input
Enable => EnabRX, -- Enable input
ReadA => ReadA, -- Async Read Received Byte
RxD => RxD_PAD_I, -- RS-232 data input
RxAv => RxAv, -- Byte available
DataO => RxData -- Byte received
);
SReg(0) <= not TxBusy;
SReg(1) <= RxAv;
-- 16MHz x 1M = 64ms
-- ESCctrl: process(WB_CLK_I)
-- variable count : unsigned(19 downto 0);
-- begin
-- if Rising_Edge(WB_CLK_I) then
-- if (WB_RST_I = '1') then
-- ESC_O <= '1';
-- count := (others => '0');
-- elsif RxData = X"1B" then
-- ESC_O <= '0';
-- count := (others => '1');
-- elsif count > 0 then
-- count := count - 1;
-- else
-- ESC_O <= '1';
-- end if;
-- end if;
-- end process;
BREAKctrl: process(WB_CLK_I)
variable count : unsigned(7 downto 0);
begin
if Rising_Edge(WB_CLK_I) then
RxData1 <= RxData;
if (WB_RST_I = '1') then
BREAK_O <= '1';
count := (others => '0');
elsif RxData1 /= X"1A" and RxData = X"1A" and CReg(7) = '1' then
BREAK_O <= '0';
count := (others => '1');
elsif count > 0 then
count := count - 1;
else
BREAK_O <= '1';
end if;
end if;
end process;
ESC_O <= '0' when RxData = X"1B" and CReg(6) = '1' else '1';
-- Implements WishBone data exchange.
-- Clocked on rising edge. Synchronous Reset RST_I
WBctrl : process(WB_CLK_I, WB_RST_I, WB_STB_I, WB_WE_I, WB_ADR_I)
variable StatM : std_logic_vector(4 downto 0);
begin
if Rising_Edge(WB_CLK_I) then
if (WB_RST_I = '1') then
ReadA <= '0';
LoadA <= '0';
Divisor <= std_logic_vector(to_unsigned(MainClockSpeed / 4 / DefaultBaud, 16));
CReg(7 downto 4) <= "0000";
SReg(2) <= '0';
SReg(3) <= '0';
else
-- Set TX Interrupt flag if enabled on falling edge of TxBusy
if TxBusy_last = '1' and TxBusy = '0' then
if CReg(4) = '1' then
SReg(2) <= '1'; -- not TxBusy;
else
SReg(2) <= '0';
end if;
end if;
TxBusy_last <= TxBusy;
-- Set RX Interrupt flag if enabled on riding edge of RxAv
if RxAv_last = '0' and RxAv = '1' then
if CReg(5) = '1' then
SReg(3) <= '1'; -- RxAv
else
SReg(3) <= '0';
end if;
end if;
RxAv_last <= RxAv;
if (WB_STB_I = '1' and WB_WE_I = '1' and WB_ADR_I = "00") then -- Write Byte to Tx
TxData <= WB_DAT_I;
LoadA <= '1'; -- Load signal
else LoadA <= '0';
end if;
if (WB_STB_I = '1' and WB_WE_I = '0' and WB_ADR_I = "00") then -- Read Byte from Rx
ReadA <= '1'; -- Read signal
else ReadA <= '0';
end if;
if (WB_STB_I = '1' and WB_WE_I = '1' and WB_ADR_I = "01") then -- Write Control
CReg <= WB_DAT_I(7 downto 4);
SReg(2) <= '0';
SReg(3) <= '0';
end if;
if (WB_STB_I = '1' and WB_WE_I = '1' and WB_ADR_I = "10") then -- Write Divisor Low
Divisor(7 downto 0) <= WB_DAT_I;
end if;
if (WB_STB_I = '1' and WB_WE_I = '1' and WB_ADR_I = "11") then -- Write Divisor High
Divisor(15 downto 8) <= WB_DAT_I;
end if;
end if;
end if;
end process;
WB_ACK_O <= WB_STB_I;
WB_DAT_O <=
RxData when WB_ADR_I = "00" else -- Read Byte from Rx
CReg & SReg when WB_ADR_I = "01" else -- Read Control/Status Reg
Divisor(7 downto 0) when WB_ADR_I = "10" else -- Read Divisor Low
Divisor(15 downto 8) when WB_ADR_I = "11" else -- Read Divisor Low
"00000000";
uart_irq_n <= not(SReg(2) or SReg(3));
end Behaviour;
| apache-2.0 | 06d861b7d8883a464e8e4f085c13bcee | 0.485821 | 3.562881 | false | false | false | false |
sergev/vak-opensource | hardware/dlx/memory-behaviour.vhdl | 1 | 6,825 | --------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: memory-behaviour.vhdl,v $ $Revision: 2.1 $ $Date: 1993/10/31 21:09:45 $
--
--------------------------------------------------------------------------
--
-- Behavioural architecture for memory model
--
use work.bv_arithmetic.bv_to_natural,
work.bv_arithmetic.natural_to_bv,
work.images.image_hex,
std.textio.all;
architecture behaviour of memory is
begin
mem : process
constant low_address : natural := 0;
constant high_address : natural := mem_size - 1;
subtype byte is bit_vector(0 to 7);
subtype ls_2_bits is bit_vector(1 downto 0);
type memory_array is
array (natural range low_address to high_address) of byte;
variable mem : memory_array;
variable aligned_a : dlx_address;
variable address : natural;
variable L : line;
procedure load(mem : out memory_array) is
file binary_file : text is in "dlx.out";
variable L : line;
variable addr : natural;
variable word : dlx_word;
procedure read_hex_natural(L : inout line; addr : out natural) is
variable result : natural := 0;
variable ch : character;
begin
for i in 1 to 8 loop
read(L, ch);
if ('0' <= ch and ch <= '9') then
result := result*16 + character'pos(ch) - character'pos('0');
else
result := result*16 + character'pos(ch) - character'pos('a') + 10;
end if;
end loop;
addr := result;
end read_hex_natural;
procedure read_hex_word(L : inout line; word : out dlx_word) is
variable result : dlx_word;
variable digit, r : natural := 0;
variable ch : character;
begin
read(L, ch); -- the space between addr and data
for i in 10 to 17 loop
read(L, ch);
if ('0' <= ch and ch <= '9') then
digit := character'pos(ch) - character'pos('0');
else
digit := character'pos(ch) - character'pos('a') + 10;
end if;
result(r to r+3) := natural_to_bv(digit, 4);
r := r + 4;
end loop;
word := result;
end read_hex_word;
begin
while not endfile(binary_file) loop
readline(binary_file, L);
read_hex_natural(L, addr);
read_hex_word(L, word);
--
write(L, addr);
write(L, ' ');
write(L, image_hex(word));
writeline(output, L);
--
mem(addr) := word(0 to 7);
mem(addr+1) := word(8 to 15);
mem(addr+2) := word(16 to 23);
mem(addr+3) := word(24 to 31);
end loop;
end load;
procedure do_write is
begin
--
-- align address to accessed unit
--
aligned_a := a;
case width is
when width_word =>
aligned_a(1 downto 0) := b"00";
when width_halfword =>
aligned_a(0) := '0';
when width_byte =>
null;
end case;
address := bv_to_natural(aligned_a);
case width is
when width_word =>
mem(address) := d(0 to 7);
mem(address+1) := d(8 to 15);
mem(address+2) := d(16 to 23);
mem(address+3) := d(24 to 31);
when width_halfword =>
if a(1) = '0' then -- ms half word
mem(address) := d(0 to 7);
mem(address+1) := d(8 to 15);
else -- ls half word
mem(address) := d(16 to 23);
mem(address+1) := d(24 to 31);
end if;
when width_byte =>
case ls_2_bits'(a(1 downto 0)) is
when b"00" =>
mem(address) := d(0 to 7);
when b"01" =>
mem(address) := d(8 to 15);
when b"10" =>
mem(address) := d(16 to 23);
when b"11" =>
mem(address) := d(24 to 31);
end case;
end case;
end do_write;
procedure do_read is
begin
aligned_a := a;
aligned_a(1 downto 0) := b"00";
address := bv_to_natural(aligned_a);
d <= mem(address) & mem(address+1) & mem(address+2) & mem(address+3);
end do_read;
begin
load(mem);
-- initialize outputs
--
d <= null;
ready <= '0';
--
-- process memory cycles
--
loop
--
-- wait for a command, valid on leading edge of phi2
--
wait until phi2 = '1' and mem_enable = '1';
--
-- decode address and perform command if selected
--
address := bv_to_natural(a);
if address >= low_address and address <= high_address then
if write_enable = '1' then -- write cycle
do_write;
wait for Tac1; -- write access time, 1st cycle
else -- read cycle
wait for Tac1; -- read access time, 1st cycle
do_read;
end if;
-- ready synchronous with phi2
wait until phi2 = '1';
ready <= '1' after Tpd_clk_out;
wait until phi2 = '0';
ready <= '0' after Tpd_clk_out;
-- do subsequent cycles in burst
while burst = '1' loop
wait until phi2 = '1';
if write_enable = '1' then -- write cycle
do_write;
wait for Tacb; -- write access time, burst cycle
else -- read cycle
wait for Tacb; -- read access time, burst cycle
do_read;
end if;
-- ready synchronous with phi2
wait until phi2 = '1';
ready <= '1' after Tpd_clk_out;
wait until phi2 = '0';
ready <= '0' after Tpd_clk_out;
end loop;
if write_enable = '0' then -- was read
d <= null after Tpd_clk_out;
end if;
end if;
end loop;
end process;
end behaviour;
| apache-2.0 | 94b4f5d4162984fab274bc048507c870 | 0.515018 | 3.821389 | false | false | false | false |
hoglet67/AtomGodilVideo | src/DCM/DCMSID1.vhd | 1 | 2,127 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity DCMSID1 is
port (CLKIN_IN : in std_logic;
RST : in std_logic := '0';
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic;
LOCKED : out std_logic
);
end DCMSID1;
architecture BEHAVIORAL of DCMSID1 is
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLK0_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 4.0,
CLKFX_DIVIDE => 12,
CLKFX_MULTIPLY => 25,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 65.1,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => GND_BIT,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => RST,
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => open,
CLK2X => CLK2X_OUT,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => LOCKED,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;
| apache-2.0 | 29bbfbebb6e10233f8871ca7799d7fc2 | 0.402915 | 4.305668 | false | false | false | false |
paulino/digilentinc-peripherals | rtl/port_display32_dig.vhd | 1 | 5,059 | -------------------------------------------------------------------------------
-- Copyright 2014 Paulino Ruiz de Clavijo Vázquez <[email protected]>
-- This file is part of the Digilentinc-peripherals project.
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- You can get more info at http://www.dte.us.es/id2
--
--*------------------------------- End auto header, don't touch this line --*--
-- Nexyys4 brings a dual display where 4 bytes can be displayes
-- This module defines a 8+2 bits inputs
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use work.digilent_peripherals_pk.all;
entity port_display32_dig is port (
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
w : in std_logic;
digit_in : in std_logic_vector (7 downto 0);
dp_in : in std_logic_vector (1 downto 0);
byte_sel : in std_logic_vector (1 downto 0);
seg_out : out std_logic_vector (6 downto 0);
dp_out : out std_logic;
an_out : out std_logic_vector (7 downto 0));
end port_display32_dig;
architecture Behavioral of port_display32_dig is
signal counter : unsigned (23 downto 0);
signal counter8 : unsigned (2 downto 0);
signal digits : std_logic_vector (31 downto 0);
signal dps : std_logic_vector (7 downto 0);
signal conv_in : std_logic_vector (3 downto 0);
signal divider : std_logic;
signal dp_inter_out : std_logic;
begin
dp_out <= not dp_inter_out;
-- Writer process
write_proc : process (clk,enable,byte_sel,w)
begin
if falling_edge(clk) and enable='1' and w='1' then
case byte_sel is
when "00" =>
digits(7 downto 0) <= digit_in(7 downto 0);
dps(1 downto 0) <= dp_in;
when "01" =>
digits(15 downto 8) <= digit_in(7 downto 0);
dps(3 downto 2) <= dp_in;
when "10" =>
digits(23 downto 16)<= digit_in(7 downto 0);
dps(5 downto 4) <= dp_in;
when others =>
digits(31 downto 24)<= digit_in(7 downto 0);
dps(7 downto 6) <= dp_in;
end case;
end if;
end process;
-- Clock divider process
div_proc : process (clk,counter,reset)
begin
if falling_edge(clk) then
if counter > NEXYS4_DIVIDER or reset = '1' then
counter <= x"000000";
divider <= '1';
else
counter <= counter + 1;
divider <= '0';
end if;
end if;
end process;
div2_proc : process(clk,divider,reset)
begin
if falling_edge(clk) then
if reset = '1' then
counter8 <= "000";
elsif divider='1' then
counter8 <= counter8 +1;
end if;
end if;
end process;
mux_anod : process (counter8)
begin
case counter8 is
when "000" =>
conv_in <= digits(3 downto 0);
dp_inter_out <= dps(0);
an_out <= "11111110";
when "001" =>
conv_in <= digits(7 downto 4);
dp_inter_out <= dps(1);
an_out <= "11111101";
when "010" =>
conv_in <= digits(11 downto 8);
dp_inter_out <= dps(2);
an_out <= "11111011";
when "011" =>
conv_in <= digits(15 downto 12);
dp_inter_out <= dps(3);
an_out <= "11110111";
when "100" =>
conv_in <= digits(19 downto 16);
dp_inter_out <= dps(4);
an_out <= "11101111";
when "101" =>
conv_in <= digits(23 downto 20);
dp_inter_out <= dps(5);
an_out <= "11011111";
when "110" =>
conv_in <= digits(27 downto 24);
dp_inter_out <= dps(6);
an_out <= "10111111";
when others =>
conv_in <= digits(31 downto 28);
dp_inter_out <= dps(7);
an_out <= "01111111";
end case;
end process;
-- Binary to seven seg converter
with conv_in select
seg_out <= "1000000" when "0000", --0
"1111001" when "0001", --1
"0100100" when "0010", --2
"0110000" when "0011", --3
"0011001" when "0100", --4
"0010010" when "0101", --5
"0000010" when "0110", --6
"1111000" when "0111", --7
"0000000" when "1000", --8
"0010000" when "1001", --9
"0001000" when "1010", --A
"0000011" when "1011", --b
"1000110" when "1100", --C
"0100001" when "1101", --d
"0000110" when "1110", --E
"0001110" when others; --F
end Behavioral;
| apache-2.0 | 6101cf72c3f278bb9f3263f06817e6aa | 0.5431 | 3.534591 | false | false | false | false |
s-kostyuk/course_project_csch | pilot_processor_signed_mul/top.vhd | 1 | 1,074 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity top is
generic(
N: integer := 4
);
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
d1 : in STD_LOGIC_VECTOR(N-1 downto 0);
d2 : in STD_LOGIC_VECTOR(N-1 downto 0);
r : out STD_LOGIC_VECTOR(2*N-1 downto 0)
);
end top;
architecture top of top is
component control_unit
port (
clk,reset : in STD_LOGIC;
X: in STD_LOGIC_vector(4 downto 1);
Y: out STD_LOGIC_vector(12 downto 1)
);
end component;
component operational_unit port(
clk,rst : in STD_LOGIC;
y : in STD_LOGIC_VECTOR(12 downto 1);
d1 : in STD_LOGIC_VECTOR(N-1 downto 0);
d2 : in STD_LOGIC_VECTOR(N-1 downto 0);
r:out STD_LOGIC_VECTOR(2*N-1 downto 0);
x:out STD_LOGIC_vector(4 downto 1)
);
end component;
signal y : std_logic_vector(12 downto 1);
signal x : std_logic_vector(4 downto 1);
begin
dd1:control_unit port map (clk,reset,x,y);
dd2:operational_unit port map (clk => clk ,rst => reset,d1 => d1, d2 =>d2, y=>y, x=>x, r =>r);
end top; | mit | f6845f46ee00ab3aba86ad6f45a5a9fe | 0.607076 | 2.698492 | false | false | false | false |
FinnK/lems2hdl | work/N3_pointCellCondBased/ISIM_output/k.vhdl | 1 | 17,452 |
---------------------------------------------------------------------
-- Standard Library bits
---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- For Modelsim
--use ieee.fixed_pkg.all;
--use ieee.fixed_float_types.ALL;
-- For ISE
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.fixed_float_types.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Entity Description
---------------------------------------------------------------------
entity k is
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC; --SYNCHRONOUS RESET
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
component_done : out STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_conductance_conductance : in sfixed (-22 downto -53);
exposure_conductance_g : out sfixed (-22 downto -53);
derivedvariable_conductance_g_out : out sfixed (-22 downto -53);
derivedvariable_conductance_g_in : in sfixed (-22 downto -53);
param_none_n_instances : in sfixed (18 downto -13);
exposure_none_n_fcond : out sfixed (18 downto -13);
exposure_none_n_q : out sfixed (18 downto -13);
statevariable_none_n_q_out : out sfixed (18 downto -13);
statevariable_none_n_q_in : in sfixed (18 downto -13);
derivedvariable_none_n_fcond_out : out sfixed (18 downto -13);
derivedvariable_none_n_fcond_in : in sfixed (18 downto -13);
param_per_time_n_forwardRaten1_rate : in sfixed (18 downto -2);
param_voltage_n_forwardRaten1_midpoint : in sfixed (2 downto -22);
param_voltage_n_forwardRaten1_scale : in sfixed (2 downto -22);
param_voltage_inv_n_forwardRaten1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_n_forwardRaten1_r : out sfixed (18 downto -2);
derivedvariable_per_time_n_forwardRaten1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_n_forwardRaten1_r_in : in sfixed (18 downto -2);
param_per_time_n_reverseRaten1_rate : in sfixed (18 downto -2);
param_voltage_n_reverseRaten1_midpoint : in sfixed (2 downto -22);
param_voltage_n_reverseRaten1_scale : in sfixed (2 downto -22);
param_voltage_inv_n_reverseRaten1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_n_reverseRaten1_r : out sfixed (18 downto -2);
derivedvariable_per_time_n_reverseRaten1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_n_reverseRaten1_r_in : in sfixed (18 downto -2);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end k;
---------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-- Architecture Begins
-------------------------------------------------------------------------------------------
architecture RTL of k is
signal COUNT : unsigned(2 downto 0) := "000";
signal childrenCombined_Component_done_single_shot_fired : STD_LOGIC := '0';
signal childrenCombined_Component_done_single_shot : STD_LOGIC := '0';
signal childrenCombined_Component_done : STD_LOGIC := '0';
signal Component_done_int : STD_LOGIC := '0';
signal subprocess_der_int_pre_ready : STD_LOGIC := '0';
signal subprocess_der_int_ready : STD_LOGIC := '0';
signal subprocess_der_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_pre_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_ready : STD_LOGIC := '0';
signal subprocess_dyn_ready : STD_LOGIC := '0';
signal subprocess_model_ready : STD_LOGIC := '1';
signal subprocess_all_ready_shotdone : STD_LOGIC := '1';
signal subprocess_all_ready_shot : STD_LOGIC := '0';
signal subprocess_all_ready : STD_LOGIC := '0';
---------------------------------------------------------------------
-- Derived Variables and parameters
---------------------------------------------------------------------
signal DerivedVariable_none_conductanceScale : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_none_conductanceScale_next : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_none_fopenHHrates : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_none_fopenHHrates_next : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_none_fopenHHtauInf : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_none_fopenHHtauInf_next : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_none_fopenHHratesTau : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_none_fopenHHratesTau_next : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_none_fopenHHratesInf : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_none_fopenHHratesInf_next : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_none_fopenHHratesTauInf : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_none_fopenHHratesTauInf_next : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_none_fopen : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_none_fopen_next : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_conductance_g : sfixed (-22 downto -53) := to_sfixed(0.0 ,-22,-53);
signal DerivedVariable_conductance_g_next : sfixed (-22 downto -53) := to_sfixed(0.0 ,-22,-53);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState internal Variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Output Port internal Variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Child Components
---------------------------------------------------------------------
component n
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC;
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
Component_done : out STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_none_instances : in sfixed (18 downto -13);
exposure_none_fcond : out sfixed (18 downto -13);
exposure_none_q : out sfixed (18 downto -13);
statevariable_none_q_out : out sfixed (18 downto -13);
statevariable_none_q_in : in sfixed (18 downto -13);
derivedvariable_none_fcond_out : out sfixed (18 downto -13);
derivedvariable_none_fcond_in : in sfixed (18 downto -13);
param_per_time_forwardRaten1_rate : in sfixed (18 downto -2);
param_voltage_forwardRaten1_midpoint : in sfixed (2 downto -22);
param_voltage_forwardRaten1_scale : in sfixed (2 downto -22);
param_voltage_inv_forwardRaten1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_forwardRaten1_r : out sfixed (18 downto -2);
derivedvariable_per_time_forwardRaten1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_forwardRaten1_r_in : in sfixed (18 downto -2);
param_per_time_reverseRaten1_rate : in sfixed (18 downto -2);
param_voltage_reverseRaten1_midpoint : in sfixed (2 downto -22);
param_voltage_reverseRaten1_scale : in sfixed (2 downto -22);
param_voltage_inv_reverseRaten1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_reverseRaten1_r : out sfixed (18 downto -2);
derivedvariable_per_time_reverseRaten1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_reverseRaten1_r_in : in sfixed (18 downto -2);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end component;
signal n_Component_done : STD_LOGIC ; signal Exposure_none_n_fcond_internal : sfixed (18 downto -13);
signal Exposure_none_n_q_internal : sfixed (18 downto -13);
signal Exposure_per_time_n_forwardRaten1_r_internal : sfixed (18 downto -2);
signal Exposure_per_time_n_reverseRaten1_r_internal : sfixed (18 downto -2);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Begin Internal Processes
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Child EDComponent Instantiations and corresponding internal variables
---------------------------------------------------------------------
n_uut : n
port map (
clk => clk,
init_model => init_model,
step_once_go => step_once_go,
Component_done => n_Component_done,
param_none_instances => param_none_n_instances,
requirement_voltage_v => requirement_voltage_v,
Exposure_none_fcond => Exposure_none_n_fcond_internal,
Exposure_none_q => Exposure_none_n_q_internal,
statevariable_none_q_out => statevariable_none_n_q_out,
statevariable_none_q_in => statevariable_none_n_q_in,
derivedvariable_none_fcond_out => derivedvariable_none_n_fcond_out,
derivedvariable_none_fcond_in => derivedvariable_none_n_fcond_in,
param_per_time_forwardRaten1_rate => param_per_time_n_forwardRaten1_rate,
param_voltage_forwardRaten1_midpoint => param_voltage_n_forwardRaten1_midpoint,
param_voltage_forwardRaten1_scale => param_voltage_n_forwardRaten1_scale,
param_voltage_inv_forwardRaten1_scale_inv => param_voltage_inv_n_forwardRaten1_scale_inv,
Exposure_per_time_forwardRaten1_r => Exposure_per_time_n_forwardRaten1_r_internal,
derivedvariable_per_time_forwardRaten1_r_out => derivedvariable_per_time_n_forwardRaten1_r_out,
derivedvariable_per_time_forwardRaten1_r_in => derivedvariable_per_time_n_forwardRaten1_r_in,
param_per_time_reverseRaten1_rate => param_per_time_n_reverseRaten1_rate,
param_voltage_reverseRaten1_midpoint => param_voltage_n_reverseRaten1_midpoint,
param_voltage_reverseRaten1_scale => param_voltage_n_reverseRaten1_scale,
param_voltage_inv_reverseRaten1_scale_inv => param_voltage_inv_n_reverseRaten1_scale_inv,
Exposure_per_time_reverseRaten1_r => Exposure_per_time_n_reverseRaten1_r_internal,
derivedvariable_per_time_reverseRaten1_r_out => derivedvariable_per_time_n_reverseRaten1_r_out,
derivedvariable_per_time_reverseRaten1_r_in => derivedvariable_per_time_n_reverseRaten1_r_in,
sysparam_time_timestep => sysparam_time_timestep,
sysparam_time_simtime => sysparam_time_simtime
);
Exposure_none_n_fcond <= Exposure_none_n_fcond_internal;
Exposure_none_n_q <= Exposure_none_n_q_internal;
derived_variable_pre_process_comb :process ( sysparam_time_timestep,exposure_none_n_fcond_internal, derivedvariable_none_fopenHHratesTauInf_next , derivedvariable_none_conductanceScale_next , derivedvariable_none_fopenHHratesInf_next , derivedvariable_none_fopenHHratesTau_next , derivedvariable_none_fopenHHtauInf_next , derivedvariable_none_fopenHHrates_next , param_conductance_conductance, derivedvariable_none_fopen_next )
begin
end process derived_variable_pre_process_comb;
derived_variable_pre_process_syn :process ( clk, init_model )
begin
subprocess_der_int_pre_ready <= '1';
end process derived_variable_pre_process_syn;
--no complex steps in derived variables
subprocess_der_int_ready <= '1';
derived_variable_process_comb :process ( sysparam_time_timestep,exposure_none_n_fcond_internal, derivedvariable_none_fopenHHratesTauInf_next , derivedvariable_none_conductanceScale_next , derivedvariable_none_fopenHHratesInf_next , derivedvariable_none_fopenHHratesTau_next , derivedvariable_none_fopenHHtauInf_next , derivedvariable_none_fopenHHrates_next , param_conductance_conductance, derivedvariable_none_fopen_next )
begin
derivedvariable_none_fopenHHrates_next <= resize(( exposure_none_n_fcond_internal ),18,-13);
derivedvariable_none_fopen_next <= resize(( derivedvariable_none_fopenHHrates_next ),18,-13);
derivedvariable_conductance_g_next <= resize(( param_conductance_conductance * derivedvariable_none_fopen_next ),-22,-53);
subprocess_der_ready <= '1';
end process derived_variable_process_comb;
derived_variable_process_syn :process ( clk,init_model )
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
derivedvariable_none_fopenHHrates <= derivedvariable_none_fopenHHrates_next;
derivedvariable_none_fopen <= derivedvariable_none_fopen_next;
derivedvariable_conductance_g <= derivedvariable_conductance_g_next;
end if;
end if;
end process derived_variable_process_syn;
---------------------------------------------------------------------
dynamics_pre_process_comb :process ( sysparam_time_timestep )
begin
end process dynamics_pre_process_comb;
dynamics_pre_process_syn :process ( clk, init_model )
begin
subprocess_dyn_int_pre_ready <= '1';
end process dynamics_pre_process_syn;
--No dynamics with complex equations found
subprocess_dyn_int_ready <= '1';
state_variable_process_dynamics_comb :process (sysparam_time_timestep)
begin
subprocess_dyn_ready <= '1';
end process state_variable_process_dynamics_comb;
state_variable_process_dynamics_syn :process (CLK,init_model)
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
end if;
end if;
end process state_variable_process_dynamics_syn;
------------------------------------------------------------------------------------------------------
-- EDState Variable Drivers
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to exposures
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to output state variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign derived variables to exposures
---------------------------------------------------------------------
exposure_conductance_g <= derivedvariable_conductance_g_in;derivedvariable_conductance_g_out <= derivedvariable_conductance_g;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Subprocess ready process
---------------------------------------------------------------------
subprocess_all_ready_process: process(step_once_go,subprocess_der_int_ready,subprocess_der_int_pre_ready,subprocess_der_ready,subprocess_dyn_int_pre_ready,subprocess_dyn_int_ready,subprocess_dyn_ready,subprocess_model_ready)
begin
if step_once_go = '0' and subprocess_der_int_ready = '1' and subprocess_der_int_pre_ready = '1'and subprocess_der_ready ='1' and subprocess_dyn_int_ready = '1' and subprocess_dyn_int_pre_ready = '1' and subprocess_dyn_ready = '1' and subprocess_model_ready = '1' then
subprocess_all_ready <= '1';
else
subprocess_all_ready <= '0';
end if;
end process subprocess_all_ready_process;
subprocess_all_ready_shot_process : process(clk)
begin
if rising_edge(clk) then
if (init_model='1') then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '1';
else
if subprocess_all_ready = '1' and subprocess_all_ready_shotdone = '0' then
subprocess_all_ready_shot <= '1';
subprocess_all_ready_shotdone <= '1';
elsif subprocess_all_ready_shot = '1' then
subprocess_all_ready_shot <= '0';
elsif subprocess_all_ready = '0' then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '0';
end if;
end if;
end if;
end process subprocess_all_ready_shot_process;
---------------------------------------------------------------------
count_proc:process(clk)
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then COUNT <= "001";
component_done_int <= '1';
else if step_once_go = '1' then
COUNT <= "000";
component_done_int <= '0';
elsif COUNT = "001" then
component_done_int <= '1';
elsif subprocess_all_ready_shot = '1' then
COUNT <= COUNT + 1;
component_done_int <= '0';
end if;
end if;
end if;
end process count_proc;
childrenCombined_component_done_process:process(n_component_done,CLK)
begin
if (n_component_done = '1') then
childrenCombined_component_done <= '1';
else
childrenCombined_component_done <= '0';
end if;
end process childrenCombined_component_done_process;
component_done <= component_done_int and childrenCombined_component_done;
end RTL;
| lgpl-3.0 | 6ea7b0a368f3237b7aa8a3ab68f42ecb | 0.605661 | 3.604296 | false | false | false | false |
dangpzanco/sistemas-digitais | SUBT.vhd | 1 | 1,277 | library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity SUBT is
port (A, B: in std_logic_vector(7 downto 0);
F : out std_logic_vector(7 downto 0);
Flag: out std_logic_vector(3 downto 0)
);
end SUBT;
architecture c1_estr of SUBT is
signal c, Bin, S: std_logic_vector(7 downto 0);
component fulladder
port (a, b, c: in std_logic;
soma, carry: out std_logic);
end component;
begin
Bin(0) <= B(0) xor '1';
Bin(1) <= B(1) xor '1';
Bin(2) <= B(2) xor '1';
Bin(3) <= B(3) xor '1';
Bin(4) <= B(4) xor '1';
Bin(5) <= B(5) xor '1';
Bin(6) <= B(6) xor '1';
Bin(7) <= B(7) xor '1';
A0: fulladder port map (A(0), Bin(0), '1', S(0), c(0));
A1: fulladder port map (A(1), Bin(1), c(0), S(1), c(1));
A2: fulladder port map (A(2), Bin(2), c(1), S(2), c(2));
A3: fulladder port map (A(3), Bin(3), c(2), S(3), c(3));
A4: fulladder port map (A(4), Bin(4), c(3), S(4), c(4));
A5: fulladder port map (A(5), Bin(5), c(4), S(5), c(5));
A6: fulladder port map (A(6), Bin(6), c(5), S(6), c(6));
A7: fulladder port map (A(7), Bin(7), c(6), S(7), c(7));
Flag(3) <= not (S(7) or S(6) or S(5) or S(4) or S(3) or S(2) or S(1) or S(0));
Flag(2) <= c(7) xor c(6);
Flag(1) <= c(7);
Flag(0) <= S(7);
F <= S;
end c1_estr;
| mit | 5ff78ed5b10c93916e6e4c78c6b2d4d9 | 0.538763 | 2.100329 | false | false | false | false |
dangpzanco/sistemas-digitais | FSM_backup.vhd | 1 | 1,897 | library ieee;
use ieee.std_logic_1164.all;
entity FSM is
port (
Clk, Rst, Enter : in std_logic;
Operacao: in std_logic_vector(1 downto 0);
Sel: out std_logic_vector(1 downto 0);
Enable_1, Enable_2: out std_logic
);
end FSM;
architecture FSM_beh of FSM is
type states is (S0, S1, S2, S3, S4, S5, S6, S7);
signal EA, PE: states;
signal clock: std_logic;
signal reset: std_logic;
begin
clock <= Clk;
reset <= Rst;
P1: process (clock, reset)
begin
if reset = '0' then
EA <= S0;
elsif clock'event and clock = '1' then
EA <= PE;
end if;
end process;
P2: process (EA, Enter)
begin
case EA is
when S0 => -- Wait
if Enter = '1' then
PE <= S0;
else
PE <= S1;
end if;
Enable_1 <= '0';
Enable_2 <= '0';
when S1 => --Botão pressionado
Enable_1 <= '1';
Enable_2 <= '0';
if Enter = '1' then
PE <= S2;
else
PE <= S1;
end if;
when S2 => --Escolha da operação
Enable_1 <= '0';
Enable_2 <= '0';
if Operacao = "00" then
PE <= S3; -- Fazer SOMA
elsif Operacao = "01" then
PE <= S4; -- Fazer OR
elsif Operacao = "10" then
PE <= S5; -- Fazer XOR
else
PE <= S6; -- Fazer NOT
end if;
when S3 => --SOMA
Sel <= "00";
if Enter = '1' then
PE <= S3;
else
PE <= S7;
end if;
when S4 => --OU
Sel <= "11";
if Enter = '1' then
PE <= S4;
else
PE <= S7;
end if;
when S5 => --Shift_left
Sel <= "01";
Enable_2 <= '1';
PE <= S0;
when S6 => --Shift_right
Sel <= "10";
Enable_2 <= '1';
PE <= S0;
when S7 => --RESULTADO
Enable_2 <= '1';
PE <= S0;
end case;
end process;
end FSM_beh; -- fim da architecture
| mit | 45819ca0a7baeab086977d7704279a80 | 0.473601 | 2.769006 | false | false | false | false |
sergev/vak-opensource | hardware/s3esk-startup/kcpsm3.vhd | 1 | 67,765 | -- PicoBlaze
--
-- Constant (K) Coded Programmable State Machine for Spartan-3 Devices.
-- Also suitable for use with Virtex-II(PRO) and Virtex-4 devices.
--
-- Includes additional code for enhanced VHDL simulation.
--
-- Version : 1.30
-- Version Date : 14th June 2004
-- Reasons : Avoid issue caused when ENABLE INTERRUPT is used when interrupts are
-- already enabled when an an interrupt input is applied.
-- Improved design for faster ZERO and CARRY flag logic
--
--
-- Previous Version : 1.20
-- Version Date : 9th July 2003
--
-- Start of design entry : 19th May 2003
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- [email protected]
--
-- Instruction disassembly concept inspired by the work of Prof. Dr.-Ing. Bernhard Lang.
-- University of Applied Sciences, Osnabrueck, Germany.
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright Xilinx, Inc. 2003. This code may be contain portions patented by other
-- third parties. By providing this core as one possible implementation of a standard,
-- Xilinx is making no representation that the provided implementation of this standard
-- is free from any claims of infringement by any third party. Xilinx expressly
-- disclaims any warranty with respect to the adequacy of the implementation, including
-- but not limited to any warranty or representation that the implementation is free
-- from claims of any third party. Furthermore, Xilinx is providing this core as a
-- courtesy to you and suggests that you contact all third parties to obtain the
-- necessary rights to use this implementation.
--
------------------------------------------------------------------------------------
--
-- Format of this file.
--
-- This file contains the definition of KCPSM3 as one complete module with sections
-- created using generate loops. This 'flat' approach has been adopted to decrease
-- the time taken to load the module into simulators and the synthesis process.
--
-- The module defines the implementation of the logic using Xilinx primitives.
-- These ensure predictable synthesis results and maximise the density of the implementation.
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
------------------------------------------------------------------------------------
--
-- Library declarations
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
------------------------------------------------------------------------------------
--
-- Main Entity for KCPSM3
--
entity kcpsm3 is
Port ( address : out std_logic_vector(9 downto 0);
instruction : in std_logic_vector(17 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0);
interrupt : in std_logic;
interrupt_ack : out std_logic;
reset : in std_logic;
clk : in std_logic);
end kcpsm3;
--
------------------------------------------------------------------------------------
--
-- Start of Main Architecture for KCPSM3
--
architecture low_level_definition of kcpsm3 is
--
------------------------------------------------------------------------------------
--
-- Signals used in KCPSM3
--
------------------------------------------------------------------------------------
--
-- Fundamental control and decode signals
--
signal t_state : std_logic;
signal not_t_state : std_logic;
signal internal_reset : std_logic;
signal reset_delay : std_logic;
signal move_group : std_logic;
signal condition_met : std_logic;
signal normal_count : std_logic;
signal call_type : std_logic;
signal push_or_pop_type : std_logic;
signal valid_to_move : std_logic;
--
-- Flag signals
--
signal flag_type : std_logic;
signal flag_write : std_logic;
signal flag_enable : std_logic;
signal zero_flag : std_logic;
signal sel_shadow_zero : std_logic;
signal low_zero : std_logic;
signal high_zero : std_logic;
signal low_zero_carry : std_logic;
signal high_zero_carry : std_logic;
signal zero_carry : std_logic;
signal zero_fast_route : std_logic;
signal low_parity : std_logic;
signal high_parity : std_logic;
signal parity_carry : std_logic;
signal parity : std_logic;
signal carry_flag : std_logic;
signal sel_parity : std_logic;
signal sel_arith_carry : std_logic;
signal sel_shift_carry : std_logic;
signal sel_shadow_carry : std_logic;
signal sel_carry : std_logic_vector(3 downto 0);
signal carry_fast_route : std_logic;
--
-- Interrupt signals
--
signal active_interrupt : std_logic;
signal int_pulse : std_logic;
signal clean_int : std_logic;
signal shadow_carry : std_logic;
signal shadow_zero : std_logic;
signal int_enable : std_logic;
signal int_update_enable : std_logic;
signal int_enable_value : std_logic;
signal interrupt_ack_internal : std_logic;
--
-- Program Counter signals
--
signal pc : std_logic_vector(9 downto 0);
signal pc_vector : std_logic_vector(9 downto 0);
signal pc_vector_carry : std_logic_vector(8 downto 0);
signal inc_pc_vector : std_logic_vector(9 downto 0);
signal pc_value : std_logic_vector(9 downto 0);
signal pc_value_carry : std_logic_vector(8 downto 0);
signal inc_pc_value : std_logic_vector(9 downto 0);
signal pc_enable : std_logic;
--
-- Data Register signals
--
signal sx : std_logic_vector(7 downto 0);
signal sy : std_logic_vector(7 downto 0);
signal register_type : std_logic;
signal register_write : std_logic;
signal register_enable : std_logic;
signal second_operand : std_logic_vector(7 downto 0);
--
-- Scratch Pad Memory signals
--
signal memory_data : std_logic_vector(7 downto 0);
signal store_data : std_logic_vector(7 downto 0);
signal memory_type : std_logic;
signal memory_write : std_logic;
signal memory_enable : std_logic;
--
-- Stack signals
--
signal stack_pop_data : std_logic_vector(9 downto 0);
signal stack_ram_data : std_logic_vector(9 downto 0);
signal stack_address : std_logic_vector(4 downto 0);
signal half_stack_address : std_logic_vector(4 downto 0);
signal stack_address_carry : std_logic_vector(3 downto 0);
signal next_stack_address : std_logic_vector(4 downto 0);
signal stack_write_enable : std_logic;
signal not_active_interrupt : std_logic;
--
-- ALU signals
--
signal logical_result : std_logic_vector(7 downto 0);
signal logical_value : std_logic_vector(7 downto 0);
signal sel_logical : std_logic;
signal shift_result : std_logic_vector(7 downto 0);
signal shift_value : std_logic_vector(7 downto 0);
signal sel_shift : std_logic;
signal high_shift_in : std_logic;
signal low_shift_in : std_logic;
signal shift_in : std_logic;
signal shift_carry : std_logic;
signal shift_carry_value : std_logic;
signal arith_result : std_logic_vector(7 downto 0);
signal arith_value : std_logic_vector(7 downto 0);
signal half_arith : std_logic_vector(7 downto 0);
signal arith_internal_carry : std_logic_vector(7 downto 0);
signal sel_arith_carry_in : std_logic;
signal arith_carry_in : std_logic;
signal invert_arith_carry : std_logic;
signal arith_carry_out : std_logic;
signal sel_arith : std_logic;
signal arith_carry : std_logic;
--
-- ALU multiplexer signals
--
signal input_fetch_type : std_logic;
signal sel_group : std_logic;
signal alu_group : std_logic_vector(7 downto 0);
signal input_group : std_logic_vector(7 downto 0);
signal alu_result : std_logic_vector(7 downto 0);
--
-- read and write strobes
--
signal io_initial_decode : std_logic;
signal write_active : std_logic;
signal read_active : std_logic;
--
--
------------------------------------------------------------------------------------
--
-- Attributes to define LUT contents during implementation for primitives not
-- contained within generate loops. In each case the information is repeated
-- in the generic map for functional simulation
--
attribute INIT : string;
attribute INIT of t_state_lut : label is "1";
attribute INIT of int_pulse_lut : label is "0080";
attribute INIT of int_update_lut : label is "EAAA";
attribute INIT of int_value_lut : label is "04";
attribute INIT of move_group_lut : label is "7400";
attribute INIT of condition_met_lut : label is "5A3C";
attribute INIT of normal_count_lut : label is "2F";
attribute INIT of call_type_lut : label is "1000";
attribute INIT of push_pop_lut : label is "5400";
attribute INIT of valid_move_lut : label is "D";
attribute INIT of flag_type_lut : label is "41FC";
attribute INIT of flag_enable_lut : label is "8";
attribute INIT of low_zero_lut : label is "0001";
attribute INIT of high_zero_lut : label is "0001";
attribute INIT of sel_shadow_zero_lut : label is "3F";
attribute INIT of low_parity_lut : label is "6996";
attribute INIT of high_parity_lut : label is "6996";
attribute INIT of sel_parity_lut : label is "F3FF";
attribute INIT of sel_arith_carry_lut : label is "F3";
attribute INIT of sel_shift_carry_lut : label is "C";
attribute INIT of sel_shadow_carry_lut : label is "3";
attribute INIT of register_type_lut : label is "0145";
attribute INIT of register_enable_lut : label is "8";
attribute INIT of memory_type_lut : label is "0400";
attribute INIT of memory_enable_lut : label is "8000";
attribute INIT of sel_logical_lut : label is "FFE2";
attribute INIT of low_shift_in_lut : label is "E4";
attribute INIT of high_shift_in_lut : label is "E4";
attribute INIT of shift_carry_lut : label is "E4";
attribute INIT of sel_arith_lut : label is "1F";
attribute INIT of input_fetch_type_lut : label is "0002";
attribute INIT of io_decode_lut : label is "0010";
attribute INIT of write_active_lut : label is "4000";
attribute INIT of read_active_lut : label is "0100";
--
------------------------------------------------------------------------------------
--
-- Start of KCPSM3 circuit description
--
------------------------------------------------------------------------------------
--
begin
--
------------------------------------------------------------------------------------
--
-- Fundamental Control
--
-- Definition of T-state and internal reset
--
------------------------------------------------------------------------------------
--
t_state_lut: LUT1
--synthesis translate_off
generic map (INIT => X"1")
--synthesis translate_on
port map( I0 => t_state,
O => not_t_state );
toggle_flop: FDR
port map ( D => not_t_state,
Q => t_state,
R => internal_reset,
C => clk);
reset_flop1: FDS
port map ( D => '0',
Q => reset_delay,
S => reset,
C => clk);
reset_flop2: FDS
port map ( D => reset_delay,
Q => internal_reset,
S => reset,
C => clk);
--
------------------------------------------------------------------------------------
--
-- Interrupt input logic, Interrupt enable and shadow Flags.
--
-- Captures interrupt input and enables the shadow flags.
-- Decodes instructions which set and reset the interrupt enable flip-flop.
--
------------------------------------------------------------------------------------
--
-- Interrupt capture
int_capture_flop: FDR
port map ( D => interrupt,
Q => clean_int,
R => internal_reset,
C => clk);
int_pulse_lut: LUT4
--synthesis translate_off
generic map (INIT => X"0080")
--synthesis translate_on
port map( I0 => t_state,
I1 => clean_int,
I2 => int_enable,
I3 => active_interrupt,
O => int_pulse );
int_flop: FDR
port map ( D => int_pulse,
Q => active_interrupt,
R => internal_reset,
C => clk);
ack_flop: FD
port map ( D => active_interrupt,
Q => interrupt_ack_internal,
C => clk);
interrupt_ack <= interrupt_ack_internal;
-- Shadow flags
shadow_carry_flop: FDE
port map ( D => carry_flag,
Q => shadow_carry,
CE => active_interrupt,
C => clk);
shadow_zero_flop: FDE
port map ( D => zero_flag,
Q => shadow_zero,
CE => active_interrupt,
C => clk);
-- Decode instructions that set or reset interrupt enable
int_update_lut: LUT4
--synthesis translate_off
generic map (INIT => X"EAAA")
--synthesis translate_on
port map( I0 => active_interrupt,
I1 => instruction(15),
I2 => instruction(16),
I3 => instruction(17),
O => int_update_enable );
int_value_lut: LUT3
--synthesis translate_off
generic map (INIT => X"04")
--synthesis translate_on
port map( I0 => active_interrupt,
I1 => instruction(0),
I2 => interrupt_ack_internal,
O => int_enable_value );
int_enable_flop: FDRE
port map ( D => int_enable_value,
Q => int_enable,
CE => int_update_enable,
R => internal_reset,
C => clk);
--
------------------------------------------------------------------------------------
--
-- Decodes for the control of the program counter and CALL/RETURN stack
--
------------------------------------------------------------------------------------
--
move_group_lut: LUT4
--synthesis translate_off
generic map (INIT => X"7400")
--synthesis translate_on
port map( I0 => instruction(14),
I1 => instruction(15),
I2 => instruction(16),
I3 => instruction(17),
O => move_group );
condition_met_lut: LUT4
--synthesis translate_off
generic map (INIT => X"5A3C")
--synthesis translate_on
port map( I0 => carry_flag,
I1 => zero_flag,
I2 => instruction(10),
I3 => instruction(11),
O => condition_met );
normal_count_lut: LUT3
--synthesis translate_off
generic map (INIT => X"2F")
--synthesis translate_on
port map( I0 => instruction(12),
I1 => condition_met,
I2 => move_group,
O => normal_count );
call_type_lut: LUT4
--synthesis translate_off
generic map (INIT => X"1000")
--synthesis translate_on
port map( I0 => instruction(14),
I1 => instruction(15),
I2 => instruction(16),
I3 => instruction(17),
O => call_type );
push_pop_lut: LUT4
--synthesis translate_off
generic map (INIT => X"5400")
--synthesis translate_on
port map( I0 => instruction(14),
I1 => instruction(15),
I2 => instruction(16),
I3 => instruction(17),
O => push_or_pop_type );
valid_move_lut: LUT2
--synthesis translate_off
generic map (INIT => X"D")
--synthesis translate_on
port map( I0 => instruction(12),
I1 => condition_met,
O => valid_to_move );
--
------------------------------------------------------------------------------------
--
-- The ZERO and CARRY Flags
--
------------------------------------------------------------------------------------
--
-- Enable for flags
flag_type_lut: LUT4
--synthesis translate_off
generic map (INIT => X"41FC")
--synthesis translate_on
port map( I0 => instruction(14),
I1 => instruction(15),
I2 => instruction(16),
I3 => instruction(17),
O => flag_type );
flag_write_flop: FD
port map ( D => flag_type,
Q => flag_write,
C => clk);
flag_enable_lut: LUT2
--synthesis translate_off
generic map (INIT => X"8")
--synthesis translate_on
port map( I0 => t_state,
I1 => flag_write,
O => flag_enable );
-- Zero Flag
low_zero_lut: LUT4
--synthesis translate_off
generic map (INIT => X"0001")
--synthesis translate_on
port map( I0 => alu_result(0),
I1 => alu_result(1),
I2 => alu_result(2),
I3 => alu_result(3),
O => low_zero );
high_zero_lut: LUT4
--synthesis translate_off
generic map (INIT => X"0001")
--synthesis translate_on
port map( I0 => alu_result(4),
I1 => alu_result(5),
I2 => alu_result(6),
I3 => alu_result(7),
O => high_zero );
low_zero_muxcy: MUXCY
port map( DI => '0',
CI => '1',
S => low_zero,
O => low_zero_carry );
high_zero_cymux: MUXCY
port map( DI => '0',
CI => low_zero_carry,
S => high_zero,
O => high_zero_carry );
sel_shadow_zero_lut: LUT3
--synthesis translate_off
generic map (INIT => X"3F")
--synthesis translate_on
port map( I0 => shadow_zero,
I1 => instruction(16),
I2 => instruction(17),
O => sel_shadow_zero );
zero_cymux: MUXCY
port map( DI => shadow_zero,
CI => high_zero_carry,
S => sel_shadow_zero,
O => zero_carry );
zero_xor: XORCY
port map( LI => '0',
CI => zero_carry,
O => zero_fast_route);
zero_flag_flop: FDRE
port map ( D => zero_fast_route,
Q => zero_flag,
CE => flag_enable,
R => internal_reset,
C => clk);
-- Parity detection
low_parity_lut: LUT4
--synthesis translate_off
generic map (INIT => X"6996")
--synthesis translate_on
port map( I0 => logical_result(0),
I1 => logical_result(1),
I2 => logical_result(2),
I3 => logical_result(3),
O => low_parity );
high_parity_lut: LUT4
--synthesis translate_off
generic map (INIT => X"6996")
--synthesis translate_on
port map( I0 => logical_result(4),
I1 => logical_result(5),
I2 => logical_result(6),
I3 => logical_result(7),
O => high_parity );
parity_muxcy: MUXCY
port map( DI => '0',
CI => '1',
S => low_parity,
O => parity_carry );
parity_xor: XORCY
port map( LI => high_parity,
CI => parity_carry,
O => parity);
-- CARRY flag selection
sel_parity_lut: LUT4
--synthesis translate_off
generic map (INIT => X"F3FF")
--synthesis translate_on
port map( I0 => parity,
I1 => instruction(13),
I2 => instruction(15),
I3 => instruction(16),
O => sel_parity );
sel_arith_carry_lut: LUT3
--synthesis translate_off
generic map (INIT => X"F3")
--synthesis translate_on
port map( I0 => arith_carry,
I1 => instruction(16),
I2 => instruction(17),
O => sel_arith_carry );
sel_shift_carry_lut: LUT2
--synthesis translate_off
generic map (INIT => X"C")
--synthesis translate_on
port map( I0 => shift_carry,
I1 => instruction(15),
O => sel_shift_carry );
sel_shadow_carry_lut: LUT2
--synthesis translate_off
generic map (INIT => X"3")
--synthesis translate_on
port map( I0 => shadow_carry,
I1 => instruction(17),
O => sel_shadow_carry );
sel_shadow_muxcy: MUXCY
port map( DI => shadow_carry,
CI => '0',
S => sel_shadow_carry,
O => sel_carry(0) );
sel_shift_muxcy: MUXCY
port map( DI => shift_carry,
CI => sel_carry(0),
S => sel_shift_carry,
O => sel_carry(1) );
sel_arith_muxcy: MUXCY
port map( DI => arith_carry,
CI => sel_carry(1),
S => sel_arith_carry,
O => sel_carry(2) );
sel_parity_muxcy: MUXCY
port map( DI => parity,
CI => sel_carry(2),
S => sel_parity,
O => sel_carry(3) );
carry_xor: XORCY
port map( LI => '0',
CI => sel_carry(3),
O => carry_fast_route);
carry_flag_flop: FDRE
port map ( D => carry_fast_route,
Q => carry_flag,
CE => flag_enable,
R => internal_reset,
C => clk);
--
------------------------------------------------------------------------------------
--
-- The Program Counter
--
-- Definition of a 10-bit counter which can be loaded from two sources
--
------------------------------------------------------------------------------------
--
invert_enable: INV -- Inverter should be implemented in the CE to flip flops
port map( I => t_state,
O => pc_enable);
pc_loop: for i in 0 to 9 generate
--
-- Attribute to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation
--
attribute INIT : string;
attribute INIT of vector_select_mux : label is "E4";
attribute INIT of value_select_mux : label is "E4";
--
begin
vector_select_mux: LUT3
--synthesis translate_off
generic map (INIT => X"E4")
--synthesis translate_on
port map( I0 => instruction(15),
I1 => instruction(i),
I2 => stack_pop_data(i),
O => pc_vector(i) );
value_select_mux: LUT3
--synthesis translate_off
generic map (INIT => X"E4")
--synthesis translate_on
port map( I0 => normal_count,
I1 => inc_pc_vector(i),
I2 => pc(i),
O => pc_value(i) );
register_bit: FDRSE
port map ( D => inc_pc_value(i),
Q => pc(i),
R => internal_reset,
S => active_interrupt,
CE => pc_enable,
C => clk);
pc_lsb_carry: if i=0 generate
begin
pc_vector_muxcy: MUXCY
port map( DI => '0',
CI => instruction(13),
S => pc_vector(i),
O => pc_vector_carry(i));
pc_vector_xor: XORCY
port map( LI => pc_vector(i),
CI => instruction(13),
O => inc_pc_vector(i));
pc_value_muxcy: MUXCY
port map( DI => '0',
CI => normal_count,
S => pc_value(i),
O => pc_value_carry(i));
pc_value_xor: XORCY
port map( LI => pc_value(i),
CI => normal_count,
O => inc_pc_value(i));
end generate pc_lsb_carry;
pc_mid_carry: if i>0 and i<9 generate
begin
pc_vector_muxcy: MUXCY
port map( DI => '0',
CI => pc_vector_carry(i-1),
S => pc_vector(i),
O => pc_vector_carry(i));
pc_vector_xor: XORCY
port map( LI => pc_vector(i),
CI => pc_vector_carry(i-1),
O => inc_pc_vector(i));
pc_value_muxcy: MUXCY
port map( DI => '0',
CI => pc_value_carry(i-1),
S => pc_value(i),
O => pc_value_carry(i));
pc_value_xor: XORCY
port map( LI => pc_value(i),
CI => pc_value_carry(i-1),
O => inc_pc_value(i));
end generate pc_mid_carry;
pc_msb_carry: if i=9 generate
begin
pc_vector_xor: XORCY
port map( LI => pc_vector(i),
CI => pc_vector_carry(i-1),
O => inc_pc_vector(i));
pc_value_xor: XORCY
port map( LI => pc_value(i),
CI => pc_value_carry(i-1),
O => inc_pc_value(i));
end generate pc_msb_carry;
end generate pc_loop;
address <= pc;
--
------------------------------------------------------------------------------------
--
-- Register Bank and second operand selection.
--
-- Definition of an 8-bit dual port RAM with 16 locations
-- including write enable decode.
--
-- Outputs are assigned to PORT_ID and OUT_PORT.
--
------------------------------------------------------------------------------------
--
-- Forming decode signal
register_type_lut: LUT4
--synthesis translate_off
generic map (INIT => X"0145")
--synthesis translate_on
port map( I0 => active_interrupt,
I1 => instruction(15),
I2 => instruction(16),
I3 => instruction(17),
O => register_type );
register_write_flop: FD
port map ( D => register_type,
Q => register_write,
C => clk);
register_enable_lut: LUT2
--synthesis translate_off
generic map (INIT => X"8")
--synthesis translate_on
port map( I0 => t_state,
I1 => register_write,
O => register_enable );
reg_loop: for i in 0 to 7 generate
--
-- Attribute to define RAM contents during implementation
-- The information is repeated in the generic map for functional simulation
--
attribute INIT : string;
attribute INIT of register_bit : label is "0000";
attribute INIT of operand_select_mux : label is "E4";
--
begin
register_bit: RAM16X1D
--synthesis translate_off
generic map(INIT => X"0000")
--synthesis translate_on
port map ( D => alu_result(i),
WE => register_enable,
WCLK => clk,
A0 => instruction(8),
A1 => instruction(9),
A2 => instruction(10),
A3 => instruction(11),
DPRA0 => instruction(4),
DPRA1 => instruction(5),
DPRA2 => instruction(6),
DPRA3 => instruction(7),
SPO => sx(i),
DPO => sy(i));
operand_select_mux: LUT3
--synthesis translate_off
generic map (INIT => X"E4")
--synthesis translate_on
port map( I0 => instruction(12),
I1 => instruction(i),
I2 => sy(i),
O => second_operand(i) );
end generate reg_loop;
out_port <= sx;
port_id <= second_operand;
--
------------------------------------------------------------------------------------
--
-- Store Memory
--
-- Definition of an 8-bit single port RAM with 64 locations
-- including write enable decode.
--
------------------------------------------------------------------------------------
--
-- Forming decode signal
memory_type_lut: LUT4
--synthesis translate_off
generic map (INIT => X"0400")
--synthesis translate_on
port map( I0 => active_interrupt,
I1 => instruction(15),
I2 => instruction(16),
I3 => instruction(17),
O => memory_type );
memory_write_flop: FD
port map ( D => memory_type,
Q => memory_write,
C => clk);
memory_enable_lut: LUT4
--synthesis translate_off
generic map (INIT => X"8000")
--synthesis translate_on
port map( I0 => t_state,
I1 => instruction(13),
I2 => instruction(14),
I3 => memory_write,
O => memory_enable );
store_loop: for i in 0 to 7 generate
--
-- Attribute to define RAM contents during implementation
-- The information is repeated in the generic map for functional simulation
--
attribute INIT : string;
attribute INIT of memory_bit : label is "0000000000000000";
--
begin
memory_bit: RAM64X1S
--synthesis translate_off
generic map(INIT => X"0000000000000000")
--synthesis translate_on
port map ( D => sx(i),
WE => memory_enable,
WCLK => clk,
A0 => second_operand(0),
A1 => second_operand(1),
A2 => second_operand(2),
A3 => second_operand(3),
A4 => second_operand(4),
A5 => second_operand(5),
O => memory_data(i));
store_flop: FD
port map ( D => memory_data(i),
Q => store_data(i),
C => clk);
end generate store_loop;
--
------------------------------------------------------------------------------------
--
-- Logical operations
--
-- Definition of AND, OR, XOR and LOAD functions which also provides TEST.
-- Includes pipeline stage used to form ALU multiplexer including decode.
--
------------------------------------------------------------------------------------
--
sel_logical_lut: LUT4
--synthesis translate_off
generic map (INIT => X"FFE2")
--synthesis translate_on
port map( I0 => instruction(14),
I1 => instruction(15),
I2 => instruction(16),
I3 => instruction(17),
O => sel_logical );
logical_loop: for i in 0 to 7 generate
--
-- Attribute to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation
attribute INIT : string;
attribute INIT of logical_lut : label is "6E8A";
--
begin
logical_lut: LUT4
--synthesis translate_off
generic map (INIT => X"6E8A")
--synthesis translate_on
port map( I0 => second_operand(i),
I1 => sx(i),
I2 => instruction(13),
I3 => instruction(14),
O => logical_value(i));
logical_flop: FDR
port map ( D => logical_value(i),
Q => logical_result(i),
R => sel_logical,
C => clk);
end generate logical_loop;
--
--
------------------------------------------------------------------------------------
--
-- Shift and Rotate operations
--
-- Includes pipeline stage used to form ALU multiplexer including decode.
--
------------------------------------------------------------------------------------
--
sel_shift_inv: INV -- Inverter should be implemented in the reset to flip flops
port map( I => instruction(17),
O => sel_shift);
-- Bit to input to shift register
high_shift_in_lut: LUT3
--synthesis translate_off
generic map (INIT => X"E4")
--synthesis translate_on
port map( I0 => instruction(1),
I1 => sx(0),
I2 => instruction(0),
O => high_shift_in );
low_shift_in_lut: LUT3
--synthesis translate_off
generic map (INIT => X"E4")
--synthesis translate_on
port map( I0 => instruction(1),
I1 => carry_flag,
I2 => sx(7),
O => low_shift_in );
shift_in_muxf5: MUXF5
port map( I1 => high_shift_in,
I0 => low_shift_in,
S => instruction(2),
O => shift_in );
-- Forming shift carry signal
shift_carry_lut: LUT3
--synthesis translate_off
generic map (INIT => X"E4")
--synthesis translate_on
port map( I0 => instruction(3),
I1 => sx(7),
I2 => sx(0),
O => shift_carry_value );
pipeline_bit: FD
port map ( D => shift_carry_value,
Q => shift_carry,
C => clk);
shift_loop: for i in 0 to 7 generate
begin
lsb_shift: if i=0 generate
--
-- Attribute to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation
attribute INIT : string;
attribute INIT of shift_mux_lut : label is "E4";
--
begin
shift_mux_lut: LUT3
--synthesis translate_off
generic map (INIT => X"E4")
--synthesis translate_on
port map( I0 => instruction(3),
I1 => shift_in,
I2 => sx(i+1),
O => shift_value(i) );
end generate lsb_shift;
mid_shift: if i>0 and i<7 generate
--
-- Attribute to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation
attribute INIT : string;
attribute INIT of shift_mux_lut : label is "E4";
--
begin
shift_mux_lut: LUT3
--synthesis translate_off
generic map (INIT => X"E4")
--synthesis translate_on
port map( I0 => instruction(3),
I1 => sx(i-1),
I2 => sx(i+1),
O => shift_value(i) );
end generate mid_shift;
msb_shift: if i=7 generate
--
-- Attribute to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation
attribute INIT : string;
attribute INIT of shift_mux_lut : label is "E4";
--
begin
shift_mux_lut: LUT3
--synthesis translate_off
generic map (INIT => X"E4")
--synthesis translate_on
port map( I0 => instruction(3),
I1 => sx(i-1),
I2 => shift_in,
O => shift_value(i) );
end generate msb_shift;
shift_flop: FDR
port map ( D => shift_value(i),
Q => shift_result(i),
R => sel_shift,
C => clk);
end generate shift_loop;
--
------------------------------------------------------------------------------------
--
-- Arithmetic operations
--
-- Definition of ADD, ADDCY, SUB and SUBCY functions which also provides COMPARE.
-- Includes pipeline stage used to form ALU multiplexer including decode.
--
------------------------------------------------------------------------------------
--
sel_arith_lut: LUT3
--synthesis translate_off
generic map (INIT => X"1F")
--synthesis translate_on
port map( I0 => instruction(14),
I1 => instruction(15),
I2 => instruction(16),
O => sel_arith );
arith_loop: for i in 0 to 7 generate
--
-- Attribute to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation
attribute INIT : string;
attribute INIT of arith_lut : label is "96";
--
begin
lsb_arith: if i=0 generate
--
-- Attribute to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation
attribute INIT : string;
attribute INIT of arith_carry_in_lut : label is "6C";
--
begin
arith_carry_in_lut: LUT3
--synthesis translate_off
generic map (INIT => X"6C")
--synthesis translate_on
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => carry_flag,
O => sel_arith_carry_in );
arith_carry_in_muxcy: MUXCY
port map( DI => '0',
CI => '1',
S => sel_arith_carry_in,
O => arith_carry_in);
arith_muxcy: MUXCY
port map( DI => sx(i),
CI => arith_carry_in,
S => half_arith(i),
O => arith_internal_carry(i));
arith_xor: XORCY
port map( LI => half_arith(i),
CI => arith_carry_in,
O => arith_value(i));
end generate lsb_arith;
mid_arith: if i>0 and i<7 generate
begin
arith_muxcy: MUXCY
port map( DI => sx(i),
CI => arith_internal_carry(i-1),
S => half_arith(i),
O => arith_internal_carry(i));
arith_xor: XORCY
port map( LI => half_arith(i),
CI => arith_internal_carry(i-1),
O => arith_value(i));
end generate mid_arith;
msb_arith: if i=7 generate
--
-- Attribute to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation
attribute INIT : string;
attribute INIT of arith_carry_out_lut : label is "2";
--
begin
arith_muxcy: MUXCY
port map( DI => sx(i),
CI => arith_internal_carry(i-1),
S => half_arith(i),
O => arith_internal_carry(i));
arith_xor: XORCY
port map( LI => half_arith(i),
CI => arith_internal_carry(i-1),
O => arith_value(i));
arith_carry_out_lut: LUT1
--synthesis translate_off
generic map (INIT => X"2")
--synthesis translate_on
port map( I0 => instruction(14),
O => invert_arith_carry );
arith_carry_out_xor: XORCY
port map( LI => invert_arith_carry,
CI => arith_internal_carry(i),
O => arith_carry_out);
arith_carry_flop: FDR
port map ( D => arith_carry_out,
Q => arith_carry,
R => sel_arith,
C => clk);
end generate msb_arith;
arith_lut: LUT3
--synthesis translate_off
generic map (INIT => X"96")
--synthesis translate_on
port map( I0 => sx(i),
I1 => second_operand(i),
I2 => instruction(14),
O => half_arith(i));
arith_flop: FDR
port map ( D => arith_value(i),
Q => arith_result(i),
R => sel_arith,
C => clk);
end generate arith_loop;
--
--
------------------------------------------------------------------------------------
--
-- ALU multiplexer
--
------------------------------------------------------------------------------------
--
input_fetch_type_lut: LUT4
--synthesis translate_off
generic map (INIT => X"0002")
--synthesis translate_on
port map( I0 => instruction(14),
I1 => instruction(15),
I2 => instruction(16),
I3 => instruction(17),
O => input_fetch_type );
sel_group_flop: FD
port map ( D => input_fetch_type,
Q => sel_group,
C => clk);
alu_mux_loop: for i in 0 to 7 generate
--
-- Attribute to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation
attribute INIT : string;
attribute INIT of or_lut : label is "FE";
attribute INIT of mux_lut : label is "E4";
--
begin
or_lut: LUT3
--synthesis translate_off
generic map (INIT => X"FE")
--synthesis translate_on
port map( I0 => logical_result(i),
I1 => arith_result(i),
I2 => shift_result(i),
O => alu_group(i));
mux_lut: LUT3
--synthesis translate_off
generic map (INIT => X"E4")
--synthesis translate_on
port map( I0 => instruction(13),
I1 => in_port(i),
I2 => store_data(i),
O => input_group(i));
shift_in_muxf5: MUXF5
port map( I1 => input_group(i),
I0 => alu_group(i),
S => sel_group,
O => alu_result(i) );
end generate alu_mux_loop;
--
------------------------------------------------------------------------------------
--
-- Read and Write Strobes
--
------------------------------------------------------------------------------------
--
io_decode_lut: LUT4
--synthesis translate_off
generic map (INIT => X"0010")
--synthesis translate_on
port map( I0 => active_interrupt,
I1 => instruction(13),
I2 => instruction(14),
I3 => instruction(16),
O => io_initial_decode );
write_active_lut: LUT4
--synthesis translate_off
generic map (INIT => X"4000")
--synthesis translate_on
port map( I0 => t_state,
I1 => instruction(15),
I2 => instruction(17),
I3 => io_initial_decode,
O => write_active );
write_strobe_flop: FDR
port map ( D => write_active,
Q => write_strobe,
R => internal_reset,
C => clk);
read_active_lut: LUT4
--synthesis translate_off
generic map (INIT => X"0100")
--synthesis translate_on
port map( I0 => t_state,
I1 => instruction(15),
I2 => instruction(17),
I3 => io_initial_decode,
O => read_active );
read_strobe_flop: FDR
port map ( D => read_active,
Q => read_strobe,
R => internal_reset,
C => clk);
--
------------------------------------------------------------------------------------
--
-- Program CALL/RETURN stack
--
-- Provided the counter and memory for a 32 deep stack supporting nested
-- subroutine calls to a depth of 31 levels.
--
------------------------------------------------------------------------------------
--
-- Stack memory is 32 locations of 10-bit single port.
stack_ram_inv: INV -- Inverter should be implemented in the WE to RAM
port map( I => t_state,
O => stack_write_enable);
stack_ram_loop: for i in 0 to 9 generate
--
-- Attribute to define RAM contents during implementation
-- The information is repeated in the generic map for functional simulation
--
attribute INIT : string;
attribute INIT of stack_bit : label is "00000000";
--
begin
stack_bit: RAM32X1S
--synthesis translate_off
generic map(INIT => X"00000000")
--synthesis translate_on
port map ( D => pc(i),
WE => stack_write_enable,
WCLK => clk,
A0 => stack_address(0),
A1 => stack_address(1),
A2 => stack_address(2),
A3 => stack_address(3),
A4 => stack_address(4),
O => stack_ram_data(i));
stack_flop: FD
port map ( D => stack_ram_data(i),
Q => stack_pop_data(i),
C => clk);
end generate stack_ram_loop;
-- Stack address pointer is a 5-bit counter
stack_count_inv: INV -- Inverter should be implemented in the CE to the flip-flops
port map( I => active_interrupt,
O => not_active_interrupt);
stack_count_loop: for i in 0 to 4 generate
begin
register_bit: FDRE
port map ( D => next_stack_address(i),
Q => stack_address(i),
R => internal_reset,
CE => not_active_interrupt,
C => clk);
lsb_stack_count: if i=0 generate
--
-- Attribute to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation
--
attribute INIT : string;
attribute INIT of count_lut : label is "6555";
--
begin
count_lut: LUT4
--synthesis translate_off
generic map (INIT => X"6555")
--synthesis translate_on
port map( I0 => stack_address(i),
I1 => t_state,
I2 => valid_to_move,
I3 => push_or_pop_type,
O => half_stack_address(i) );
count_muxcy: MUXCY
port map( DI => stack_address(i),
CI => '0',
S => half_stack_address(i),
O => stack_address_carry(i));
count_xor: XORCY
port map( LI => half_stack_address(i),
CI => '0',
O => next_stack_address(i));
end generate lsb_stack_count;
mid_stack_count: if i>0 and i<4 generate
--
-- Attribute to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation
--
attribute INIT : string;
attribute INIT of count_lut : label is "A999";
--
begin
count_lut: LUT4
--synthesis translate_off
generic map (INIT => X"A999")
--synthesis translate_on
port map( I0 => stack_address(i),
I1 => t_state,
I2 => valid_to_move,
I3 => call_type,
O => half_stack_address(i) );
count_muxcy: MUXCY
port map( DI => stack_address(i),
CI => stack_address_carry(i-1),
S => half_stack_address(i),
O => stack_address_carry(i));
count_xor: XORCY
port map( LI => half_stack_address(i),
CI => stack_address_carry(i-1),
O => next_stack_address(i));
end generate mid_stack_count;
msb_stack_count: if i=4 generate
--
-- Attribute to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation
--
attribute INIT : string;
attribute INIT of count_lut : label is "A999";
--
begin
count_lut: LUT4
--synthesis translate_off
generic map (INIT => X"A999")
--synthesis translate_on
port map( I0 => stack_address(i),
I1 => t_state,
I2 => valid_to_move,
I3 => call_type,
O => half_stack_address(i) );
count_xor: XORCY
port map( LI => half_stack_address(i),
CI => stack_address_carry(i-1),
O => next_stack_address(i));
end generate msb_stack_count;
end generate stack_count_loop;
--
------------------------------------------------------------------------------------
--
-- End of description for KCPSM3 macro.
--
------------------------------------------------------------------------------------
--
--**********************************************************************************
-- Code for simulation purposes only after this line
--**********************************************************************************
--
------------------------------------------------------------------------------------
--
-- Code for simulation.
--
-- Disassemble the instruction codes to form a text string variable for display.
-- Determine status of reset and flags and present in the form of a text string.
-- Provide a local variables to simulate the contents of each register and scratch
-- pad memory location.
--
------------------------------------------------------------------------------------
--
--All of this section is ignored during synthesis.
--synthesis translate off
simulation: process (clk, instruction)
--
--complete instruction decode
--
variable kcpsm3_opcode : string(1 to 19);
--
--Status of flags and processor
--
variable kcpsm3_status : string(1 to 13):= "NZ, NC, Reset";
--
--contents of each register
--
variable s0_contents : std_logic_vector(7 downto 0):=X"00";
variable s1_contents : std_logic_vector(7 downto 0):=X"00";
variable s2_contents : std_logic_vector(7 downto 0):=X"00";
variable s3_contents : std_logic_vector(7 downto 0):=X"00";
variable s4_contents : std_logic_vector(7 downto 0):=X"00";
variable s5_contents : std_logic_vector(7 downto 0):=X"00";
variable s6_contents : std_logic_vector(7 downto 0):=X"00";
variable s7_contents : std_logic_vector(7 downto 0):=X"00";
variable s8_contents : std_logic_vector(7 downto 0):=X"00";
variable s9_contents : std_logic_vector(7 downto 0):=X"00";
variable sa_contents : std_logic_vector(7 downto 0):=X"00";
variable sb_contents : std_logic_vector(7 downto 0):=X"00";
variable sc_contents : std_logic_vector(7 downto 0):=X"00";
variable sd_contents : std_logic_vector(7 downto 0):=X"00";
variable se_contents : std_logic_vector(7 downto 0):=X"00";
variable sf_contents : std_logic_vector(7 downto 0):=X"00";
--
--contents of each scratch pad memory location
--
variable spm00_contents : std_logic_vector(7 downto 0):=X"00";
variable spm01_contents : std_logic_vector(7 downto 0):=X"00";
variable spm02_contents : std_logic_vector(7 downto 0):=X"00";
variable spm03_contents : std_logic_vector(7 downto 0):=X"00";
variable spm04_contents : std_logic_vector(7 downto 0):=X"00";
variable spm05_contents : std_logic_vector(7 downto 0):=X"00";
variable spm06_contents : std_logic_vector(7 downto 0):=X"00";
variable spm07_contents : std_logic_vector(7 downto 0):=X"00";
variable spm08_contents : std_logic_vector(7 downto 0):=X"00";
variable spm09_contents : std_logic_vector(7 downto 0):=X"00";
variable spm0a_contents : std_logic_vector(7 downto 0):=X"00";
variable spm0b_contents : std_logic_vector(7 downto 0):=X"00";
variable spm0c_contents : std_logic_vector(7 downto 0):=X"00";
variable spm0d_contents : std_logic_vector(7 downto 0):=X"00";
variable spm0e_contents : std_logic_vector(7 downto 0):=X"00";
variable spm0f_contents : std_logic_vector(7 downto 0):=X"00";
variable spm10_contents : std_logic_vector(7 downto 0):=X"00";
variable spm11_contents : std_logic_vector(7 downto 0):=X"00";
variable spm12_contents : std_logic_vector(7 downto 0):=X"00";
variable spm13_contents : std_logic_vector(7 downto 0):=X"00";
variable spm14_contents : std_logic_vector(7 downto 0):=X"00";
variable spm15_contents : std_logic_vector(7 downto 0):=X"00";
variable spm16_contents : std_logic_vector(7 downto 0):=X"00";
variable spm17_contents : std_logic_vector(7 downto 0):=X"00";
variable spm18_contents : std_logic_vector(7 downto 0):=X"00";
variable spm19_contents : std_logic_vector(7 downto 0):=X"00";
variable spm1a_contents : std_logic_vector(7 downto 0):=X"00";
variable spm1b_contents : std_logic_vector(7 downto 0):=X"00";
variable spm1c_contents : std_logic_vector(7 downto 0):=X"00";
variable spm1d_contents : std_logic_vector(7 downto 0):=X"00";
variable spm1e_contents : std_logic_vector(7 downto 0):=X"00";
variable spm1f_contents : std_logic_vector(7 downto 0):=X"00";
variable spm20_contents : std_logic_vector(7 downto 0):=X"00";
variable spm21_contents : std_logic_vector(7 downto 0):=X"00";
variable spm22_contents : std_logic_vector(7 downto 0):=X"00";
variable spm23_contents : std_logic_vector(7 downto 0):=X"00";
variable spm24_contents : std_logic_vector(7 downto 0):=X"00";
variable spm25_contents : std_logic_vector(7 downto 0):=X"00";
variable spm26_contents : std_logic_vector(7 downto 0):=X"00";
variable spm27_contents : std_logic_vector(7 downto 0):=X"00";
variable spm28_contents : std_logic_vector(7 downto 0):=X"00";
variable spm29_contents : std_logic_vector(7 downto 0):=X"00";
variable spm2a_contents : std_logic_vector(7 downto 0):=X"00";
variable spm2b_contents : std_logic_vector(7 downto 0):=X"00";
variable spm2c_contents : std_logic_vector(7 downto 0):=X"00";
variable spm2d_contents : std_logic_vector(7 downto 0):=X"00";
variable spm2e_contents : std_logic_vector(7 downto 0):=X"00";
variable spm2f_contents : std_logic_vector(7 downto 0):=X"00";
variable spm30_contents : std_logic_vector(7 downto 0):=X"00";
variable spm31_contents : std_logic_vector(7 downto 0):=X"00";
variable spm32_contents : std_logic_vector(7 downto 0):=X"00";
variable spm33_contents : std_logic_vector(7 downto 0):=X"00";
variable spm34_contents : std_logic_vector(7 downto 0):=X"00";
variable spm35_contents : std_logic_vector(7 downto 0):=X"00";
variable spm36_contents : std_logic_vector(7 downto 0):=X"00";
variable spm37_contents : std_logic_vector(7 downto 0):=X"00";
variable spm38_contents : std_logic_vector(7 downto 0):=X"00";
variable spm39_contents : std_logic_vector(7 downto 0):=X"00";
variable spm3a_contents : std_logic_vector(7 downto 0):=X"00";
variable spm3b_contents : std_logic_vector(7 downto 0):=X"00";
variable spm3c_contents : std_logic_vector(7 downto 0):=X"00";
variable spm3d_contents : std_logic_vector(7 downto 0):=X"00";
variable spm3e_contents : std_logic_vector(7 downto 0):=X"00";
variable spm3f_contents : std_logic_vector(7 downto 0):=X"00";
--
--temporary variables
--
variable sx_decode : string(1 to 2); --sX register specification
variable sy_decode : string(1 to 2); --sY register specification
variable kk_decode : string(1 to 2); --constant value specification
variable aaa_decode : string(1 to 3); --address specification
--
--------------------------------------------------------------------------------
--
-- Function to convert 4-bit binary nibble to hexadecimal character
--
--------------------------------------------------------------------------------
--
function hexcharacter (nibble: std_logic_vector(3 downto 0))
return character is
variable hex: character;
begin
case nibble is
when "0000" => hex := '0';
when "0001" => hex := '1';
when "0010" => hex := '2';
when "0011" => hex := '3';
when "0100" => hex := '4';
when "0101" => hex := '5';
when "0110" => hex := '6';
when "0111" => hex := '7';
when "1000" => hex := '8';
when "1001" => hex := '9';
when "1010" => hex := 'A';
when "1011" => hex := 'B';
when "1100" => hex := 'C';
when "1101" => hex := 'D';
when "1110" => hex := 'E';
when "1111" => hex := 'F';
when others => hex := 'x';
end case;
return hex;
end hexcharacter;
--
--------------------------------------------------------------------------------
--
begin
-- decode first register
sx_decode(1) := 's';
sx_decode(2) := hexcharacter(instruction(11 downto 8));
-- decode second register
sy_decode(1) := 's';
sy_decode(2) := hexcharacter(instruction(7 downto 4));
-- decode constant value
kk_decode(1) := hexcharacter(instruction(7 downto 4));
kk_decode(2) := hexcharacter(instruction(3 downto 0));
-- address value
aaa_decode(1) := hexcharacter("00" & instruction(9 downto 8));
aaa_decode(2) := hexcharacter(instruction(7 downto 4));
aaa_decode(3) := hexcharacter(instruction(3 downto 0));
-- decode instruction
case instruction(17 downto 12) is
when "000000" => kcpsm3_opcode := "LOAD " & sx_decode & ',' & kk_decode & " ";
when "000001" => kcpsm3_opcode := "LOAD " & sx_decode & ',' & sy_decode & " ";
when "001010" => kcpsm3_opcode := "AND " & sx_decode & ',' & kk_decode & " ";
when "001011" => kcpsm3_opcode := "AND " & sx_decode & ',' & sy_decode & " ";
when "001100" => kcpsm3_opcode := "OR " & sx_decode & ',' & kk_decode & " ";
when "001101" => kcpsm3_opcode := "OR " & sx_decode & ',' & sy_decode & " ";
when "001110" => kcpsm3_opcode := "XOR " & sx_decode & ',' & kk_decode & " ";
when "001111" => kcpsm3_opcode := "XOR " & sx_decode & ',' & sy_decode & " ";
when "010010" => kcpsm3_opcode := "TEST " & sx_decode & ',' & kk_decode & " ";
when "010011" => kcpsm3_opcode := "TEST " & sx_decode & ',' & sy_decode & " ";
when "011000" => kcpsm3_opcode := "ADD " & sx_decode & ',' & kk_decode & " ";
when "011001" => kcpsm3_opcode := "ADD " & sx_decode & ',' & sy_decode & " ";
when "011010" => kcpsm3_opcode := "ADDCY " & sx_decode & ',' & kk_decode & " ";
when "011011" => kcpsm3_opcode := "ADDCY " & sx_decode & ',' & sy_decode & " ";
when "011100" => kcpsm3_opcode := "SUB " & sx_decode & ',' & kk_decode & " ";
when "011101" => kcpsm3_opcode := "SUB " & sx_decode & ',' & sy_decode & " ";
when "011110" => kcpsm3_opcode := "SUBCY " & sx_decode & ',' & kk_decode & " ";
when "011111" => kcpsm3_opcode := "SUBCY " & sx_decode & ',' & sy_decode & " ";
when "010100" => kcpsm3_opcode := "COMPARE " & sx_decode & ',' & kk_decode & " ";
when "010101" => kcpsm3_opcode := "COMPARE " & sx_decode & ',' & sy_decode & " ";
when "100000" =>
case instruction(3 downto 0) is
when "0110" => kcpsm3_opcode := "SL0 " & sx_decode & " ";
when "0111" => kcpsm3_opcode := "SL1 " & sx_decode & " ";
when "0100" => kcpsm3_opcode := "SLX " & sx_decode & " ";
when "0000" => kcpsm3_opcode := "SLA " & sx_decode & " ";
when "0010" => kcpsm3_opcode := "RL " & sx_decode & " ";
when "1110" => kcpsm3_opcode := "SR0 " & sx_decode & " ";
when "1111" => kcpsm3_opcode := "SR1 " & sx_decode & " ";
when "1010" => kcpsm3_opcode := "SRX " & sx_decode & " ";
when "1000" => kcpsm3_opcode := "SRA " & sx_decode & " ";
when "1100" => kcpsm3_opcode := "RR " & sx_decode & " ";
when others => kcpsm3_opcode := "Invalid Instruction";
end case;
when "101100" => kcpsm3_opcode := "OUTPUT " & sx_decode & ',' & kk_decode & " ";
when "101101" => kcpsm3_opcode := "OUTPUT " & sx_decode & ",(" & sy_decode & ") ";
when "000100" => kcpsm3_opcode := "INPUT " & sx_decode & ',' & kk_decode & " ";
when "000101" => kcpsm3_opcode := "INPUT " & sx_decode & ",(" & sy_decode & ") ";
when "101110" => kcpsm3_opcode := "STORE " & sx_decode & ',' & kk_decode & " ";
when "101111" => kcpsm3_opcode := "STORE " & sx_decode & ",(" & sy_decode & ") ";
when "000110" => kcpsm3_opcode := "FETCH " & sx_decode & ',' & kk_decode & " ";
when "000111" => kcpsm3_opcode := "FETCH " & sx_decode & ",(" & sy_decode & ") ";
when "110100" => kcpsm3_opcode := "JUMP " & aaa_decode & " ";
when "110101" =>
case instruction(11 downto 10) is
when "00" => kcpsm3_opcode := "JUMP Z," & aaa_decode & " ";
when "01" => kcpsm3_opcode := "JUMP NZ," & aaa_decode & " ";
when "10" => kcpsm3_opcode := "JUMP C," & aaa_decode & " ";
when "11" => kcpsm3_opcode := "JUMP NC," & aaa_decode & " ";
when others => kcpsm3_opcode := "Invalid Instruction";
end case;
when "110000" => kcpsm3_opcode := "CALL " & aaa_decode & " ";
when "110001" =>
case instruction(11 downto 10) is
when "00" => kcpsm3_opcode := "CALL Z," & aaa_decode & " ";
when "01" => kcpsm3_opcode := "CALL NZ," & aaa_decode & " ";
when "10" => kcpsm3_opcode := "CALL C," & aaa_decode & " ";
when "11" => kcpsm3_opcode := "CALL NC," & aaa_decode & " ";
when others => kcpsm3_opcode := "Invalid Instruction";
end case;
when "101010" => kcpsm3_opcode := "RETURN ";
when "101011" =>
case instruction(11 downto 10) is
when "00" => kcpsm3_opcode := "RETURN Z ";
when "01" => kcpsm3_opcode := "RETURN NZ ";
when "10" => kcpsm3_opcode := "RETURN C ";
when "11" => kcpsm3_opcode := "RETURN NC ";
when others => kcpsm3_opcode := "Invalid Instruction";
end case;
when "111000" =>
case instruction(0) is
when '0' => kcpsm3_opcode := "RETURNI DISABLE ";
when '1' => kcpsm3_opcode := "RETURNI ENABLE ";
when others => kcpsm3_opcode := "Invalid Instruction";
end case;
when "111100" =>
case instruction(0) is
when '0' => kcpsm3_opcode := "DISABLE INTERRUPT ";
when '1' => kcpsm3_opcode := "ENABLE INTERRUPT ";
when others => kcpsm3_opcode := "Invalid Instruction";
end case;
when others => kcpsm3_opcode := "Invalid Instruction";
end case;
if clk'event and clk='1' then
--reset and flag status information
if reset='1' or reset_delay='1' then
kcpsm3_status := "NZ, NC, Reset";
else
kcpsm3_status(7 to 13) := " ";
if flag_enable='1' then
if zero_carry='1' then
kcpsm3_status(1 to 4) := " Z, ";
else
kcpsm3_status(1 to 4) := "NZ, ";
end if;
if sel_carry(3)='1' then
kcpsm3_status(5 to 6) := " C";
else
kcpsm3_status(5 to 6) := "NC";
end if;
end if;
end if;
--simulation of register contents
if register_enable='1' then
case instruction(11 downto 8) is
when "0000" => s0_contents := alu_result;
when "0001" => s1_contents := alu_result;
when "0010" => s2_contents := alu_result;
when "0011" => s3_contents := alu_result;
when "0100" => s4_contents := alu_result;
when "0101" => s5_contents := alu_result;
when "0110" => s6_contents := alu_result;
when "0111" => s7_contents := alu_result;
when "1000" => s8_contents := alu_result;
when "1001" => s9_contents := alu_result;
when "1010" => sa_contents := alu_result;
when "1011" => sb_contents := alu_result;
when "1100" => sc_contents := alu_result;
when "1101" => sd_contents := alu_result;
when "1110" => se_contents := alu_result;
when "1111" => sf_contents := alu_result;
when others => null;
end case;
end if;
--simulation of scratch pad memory contents
if memory_enable='1' then
case second_operand(5 downto 0) is
when "000000" => spm00_contents := sx;
when "000001" => spm01_contents := sx;
when "000010" => spm02_contents := sx;
when "000011" => spm03_contents := sx;
when "000100" => spm04_contents := sx;
when "000101" => spm05_contents := sx;
when "000110" => spm06_contents := sx;
when "000111" => spm07_contents := sx;
when "001000" => spm08_contents := sx;
when "001001" => spm09_contents := sx;
when "001010" => spm0a_contents := sx;
when "001011" => spm0b_contents := sx;
when "001100" => spm0c_contents := sx;
when "001101" => spm0d_contents := sx;
when "001110" => spm0e_contents := sx;
when "001111" => spm0f_contents := sx;
when "010000" => spm10_contents := sx;
when "010001" => spm11_contents := sx;
when "010010" => spm12_contents := sx;
when "010011" => spm13_contents := sx;
when "010100" => spm14_contents := sx;
when "010101" => spm15_contents := sx;
when "010110" => spm16_contents := sx;
when "010111" => spm17_contents := sx;
when "011000" => spm18_contents := sx;
when "011001" => spm19_contents := sx;
when "011010" => spm1a_contents := sx;
when "011011" => spm1b_contents := sx;
when "011100" => spm1c_contents := sx;
when "011101" => spm1d_contents := sx;
when "011110" => spm1e_contents := sx;
when "011111" => spm1f_contents := sx;
when "100000" => spm20_contents := sx;
when "100001" => spm21_contents := sx;
when "100010" => spm22_contents := sx;
when "100011" => spm23_contents := sx;
when "100100" => spm24_contents := sx;
when "100101" => spm25_contents := sx;
when "100110" => spm26_contents := sx;
when "100111" => spm27_contents := sx;
when "101000" => spm28_contents := sx;
when "101001" => spm29_contents := sx;
when "101010" => spm2a_contents := sx;
when "101011" => spm2b_contents := sx;
when "101100" => spm2c_contents := sx;
when "101101" => spm2d_contents := sx;
when "101110" => spm2e_contents := sx;
when "101111" => spm2f_contents := sx;
when "110000" => spm30_contents := sx;
when "110001" => spm31_contents := sx;
when "110010" => spm32_contents := sx;
when "110011" => spm33_contents := sx;
when "110100" => spm34_contents := sx;
when "110101" => spm35_contents := sx;
when "110110" => spm36_contents := sx;
when "110111" => spm37_contents := sx;
when "111000" => spm38_contents := sx;
when "111001" => spm39_contents := sx;
when "111010" => spm3a_contents := sx;
when "111011" => spm3b_contents := sx;
when "111100" => spm3c_contents := sx;
when "111101" => spm3d_contents := sx;
when "111110" => spm3e_contents := sx;
when "111111" => spm3f_contents := sx;
when others => null;
end case;
end if;
end if;
end process simulation;
--synthesis translate on
--
--**********************************************************************************
-- End of simulation code.
--**********************************************************************************
--
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- END OF FILE KCPSM3.VHD
--
------------------------------------------------------------------------------------
| apache-2.0 | ee0741c1d0eec1ca6c07f556a5968556 | 0.504656 | 3.97472 | false | false | false | false |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/common/openmac/src/master_handler.vhd | 5 | 16,722 | -------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity master_handler is
generic(
dma_highadr_g : integer := 31;
gen_tx_fifo_g : boolean := true;
tx_fifo_word_size_log2_g : natural := 5;
gen_rx_fifo_g : boolean := true;
rx_fifo_word_size_log2_g : natural := 5;
m_burstcount_width_g : integer := 4;
m_rx_burst_size_g : integer := 16;
m_tx_burst_size_g : integer := 16;
m_burst_wr_const_g : boolean := true;
fifo_data_width_g : integer := 16
);
port(
m_clk : in std_logic;
rst : in std_logic;
mac_tx_off : in std_logic;
mac_rx_off : in std_logic;
tx_wr_clk : in std_logic;
tx_wr_empty : in std_logic;
tx_wr_full : in std_logic;
rx_rd_clk : in std_logic;
rx_rd_empty : in std_logic;
rx_rd_full : in std_logic;
tx_wr_usedw : in std_logic_vector(tx_fifo_word_size_log2_g-1 downto 0);
rx_rd_usedw : in std_logic_vector(rx_fifo_word_size_log2_g-1 downto 0);
tx_aclr : out std_logic;
tx_wr_req : out std_logic;
rx_rd_req : out std_logic;
m_waitrequest : in std_logic;
m_readdatavalid : in std_logic;
m_write : out std_logic;
m_read : out std_logic;
m_address : out std_logic_vector(dma_highadr_g downto 0);
m_byteenable : out std_logic_vector(fifo_data_width_g/8-1 downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
dma_addr_in : in std_logic_vector(dma_highadr_g downto 1);
dma_len_rd : in std_logic_vector(11 downto 0);
dma_new_addr_wr : in std_logic;
dma_new_addr_rd : in std_logic;
dma_new_len_rd : in std_logic
);
end master_handler;
architecture master_handler of master_handler is
--clock signal
signal clk : std_logic;
--constants
constant tx_burst_size_c : integer := m_tx_burst_size_g; --(2**(m_burstcount_width_g-1));
constant rx_burst_size_c : integer := m_rx_burst_size_g; --(2**(m_burstcount_width_g-1));
---used to trigger rx/tx data transfers depending on fill level and burst size
constant tx_fifo_limit_c : integer := 2**tx_fifo_word_size_log2_g - tx_burst_size_c - 1; --fifo_size - burst size - 1
constant rx_fifo_limit_c : integer := rx_burst_size_c + 1; --burst size
--fsm
type transfer_t is (idle, run, finish);
signal tx_fsm, tx_fsm_next, rx_fsm, rx_fsm_next : transfer_t := idle;
--transfer signals
signal m_burstcount_s, m_burstcount_latch : std_logic_vector(m_burstcount'range);
signal m_address_latch : std_logic_vector(m_address'range);
signal m_write_s, m_read_s : std_logic;
signal rx_first_read_done, rx_rd_done : std_logic;
--fifo signals
signal arst : std_logic;
signal tx_fifo_limit, rx_fifo_limit : std_logic;
signal tx_wr_req_s, rx_rd_req_s, rx_first_rd_req : std_logic;
--generate addresses
signal tx_cnt, tx_cnt_next : std_logic_vector(m_address'range);
signal rx_cnt, rx_cnt_next : std_logic_vector(m_address'range);
--handle tx read transfer
signal tx_rd_cnt, tx_rd_cnt_next : std_logic_vector(dma_len_rd'range);
signal dma_len_rd_s : std_logic_vector(dma_len_rd'range);
begin
--m_clk, rx_rd_clk and tx_wr_clk are the same!
clk <= m_clk; --to ease typing
tx_aclr <= rst or arst;
--fifo limit is set to '1' if the fill level is equal/above the limit
tx_fifo_limit <= '1' when tx_wr_usedw >= conv_std_logic_vector(tx_fifo_limit_c, tx_wr_usedw'length) else '0';
rx_fifo_limit <= '1' when rx_rd_usedw >= conv_std_logic_vector(rx_fifo_limit_c, rx_rd_usedw'length) else '0';
process(clk, rst)
begin
if rst = '1' then
if gen_rx_fifo_g then
rx_fsm <= idle;
end if;
if gen_tx_fifo_g then
tx_fsm <= idle;
end if;
elsif clk = '1' and clk'event then
if gen_rx_fifo_g then
rx_fsm <= rx_fsm_next;
end if;
if gen_tx_fifo_g then
tx_fsm <= tx_fsm_next;
end if;
end if;
end process;
tx_fsm_next <= run when tx_fsm = idle and dma_new_addr_rd = '1' else
finish when tx_fsm = run and mac_tx_off = '1' else
idle when tx_fsm = finish and tx_wr_empty = '1' else --stay finish as long as tx fifo is filled
tx_fsm;
rx_fsm_next <= run when rx_fsm = idle and dma_new_addr_wr = '1' else
finish when rx_fsm = run and mac_rx_off = '1' else
idle when rx_fsm = finish and rx_rd_done = '1' else --stay finish as long the transfer process is not done
rx_fsm;
m_burstcount <= m_burstcount_latch when m_write_s = '1' and m_burst_wr_const_g else m_burstcount_s;
m_burstcounter <= m_burstcount_s; --output current burst counter value
m_write <= m_write_s;
m_read <= m_read_s;
--generate address
m_address <= m_address_latch when m_write_s = '1' and m_burst_wr_const_g else
rx_cnt when m_write_s = '1' and not m_burst_wr_const_g else
tx_cnt;
process(clk, rst)
begin
if rst = '1' then
if gen_tx_fifo_g then
tx_cnt <= (others => '0');
tx_rd_cnt <= (others => '0');
end if;
if gen_rx_fifo_g then
rx_cnt <= (others => '0');
end if;
elsif clk = '1' and clk'event then
if gen_tx_fifo_g then
tx_cnt <= tx_cnt_next;
tx_rd_cnt <= tx_rd_cnt_next;
end if;
if gen_rx_fifo_g then
rx_cnt <= rx_cnt_next;
end if;
end if;
end process;
dma_len_rd_s <= dma_len_rd + 1 when fifo_data_width_g = 16 else
dma_len_rd + 3 when fifo_data_width_g = 32 else
dma_len_rd;
tx_rd_cnt_next <= (others => '0') when gen_tx_fifo_g = false else
'0' & dma_len_rd_s(dma_len_rd_s'left downto 1) when dma_new_len_rd = '1' and fifo_data_width_g = 16 else
"00" & dma_len_rd_s(dma_len_rd_s'left downto 2) when dma_new_len_rd = '1' and fifo_data_width_g = 32 else
tx_rd_cnt - 1 when tx_wr_req_s = '1' and tx_rd_cnt /= 0 else
tx_rd_cnt;
tx_cnt_next <= (others => '0') when gen_tx_fifo_g = false else
tx_cnt + fifo_data_width_g/8 when tx_wr_req_s = '1' else
dma_addr_in & '0' when dma_new_addr_rd = '1' else
tx_cnt;
rx_cnt_next <= (others => '0') when gen_rx_fifo_g = false else
rx_cnt + fifo_data_width_g/8 when rx_rd_req_s = '1' else
dma_addr_in & '0' when dma_new_addr_wr = '1' else
rx_cnt;
m_byteenable <= (others => '1');
tx_wr_req_s <= m_readdatavalid;
tx_wr_req <= tx_wr_req_s;
rx_rd_req_s <= m_write_s and not m_waitrequest;
rx_rd_req <= rx_rd_req_s or rx_first_rd_req;
process(clk, rst)
--arbitration of rx and tx requests is done by process variable (tx overrules rx)
variable tx_is_the_owner_v : std_logic;
begin
if rst = '1' then
tx_is_the_owner_v := '0';
if gen_tx_fifo_g then
arst <= '0';
m_read_s <= '0';
end if;
if gen_rx_fifo_g then
rx_first_rd_req <= '0';
m_write_s <= '0';
rx_first_read_done <= '0';
rx_rd_done <= '0';
end if;
m_burstcount_s <= (others => '0');
if m_burst_wr_const_g then
m_burstcount_latch <= (others => '0');
m_address_latch <= (others => '0');
end if;
elsif clk = '1' and clk'event then
if gen_tx_fifo_g then
arst <= '0';
if m_readdatavalid = '1' then
--read was successful -> write to tx fifo
m_burstcount_s <= m_burstcount_s - 1;
end if;
case tx_fsm is
when idle =>
--no transfer in progress
when run =>
--read transfer base address is ready
if tx_fifo_limit = '0' and m_read_s = '0' and m_write_s = '0' and m_burstcount_s = 0 and tx_rd_cnt /= 0 then
--tx fifo is below defined limit -> there is place for at least one burst!
m_read_s <= '1';
if tx_rd_cnt > conv_std_logic_vector(tx_burst_size_c, tx_rd_cnt'length) then
m_burstcount_s <= conv_std_logic_vector(tx_burst_size_c, m_burstcount_s'length);
else
m_burstcount_s <= EXT(tx_rd_cnt, m_burstcount_s'length);
end if;
--a tx transfer is necessary and overrules necessary rx transfers...
tx_is_the_owner_v := '1';
elsif m_read_s = '1' and m_waitrequest = '0' then
--request is confirmed -> deassert request
m_read_s <= '0';
--so, we are done with tx requesting
tx_is_the_owner_v := '0';
end if;
when finish =>
--transfer done, MAC has its data...
---is there still a request?
if m_read_s = '1' and m_waitrequest = '0' then
--last request confirmed -> deassert request
m_read_s <= '0'; tx_is_the_owner_v := '0';
---is the burst transfer done?
elsif m_read_s = '0' and m_burstcount_s = 0 then
--burst transfer done, clear fifo
arst <= '1';
end if;
end case;
end if;
if gen_rx_fifo_g then
rx_first_rd_req <= '0';
rx_rd_done <= '0';
if m_write_s = '1' and m_waitrequest = '0' then
--write was successful
m_burstcount_s <= m_burstcount_s - 1;
end if;
case rx_fsm is
when idle =>
--no transfer in progress
rx_first_read_done <= '0';
when run =>
--a not empty fifo has to be read once, to get the very first pattern
if rx_first_read_done = '0' and rx_rd_empty = '0' then
rx_first_read_done <= '1';
rx_first_rd_req <= '1';
end if;
--write transfer base address is ready
if rx_fifo_limit = '1' and m_read_s = '0' and m_write_s = '0' and tx_is_the_owner_v = '0' and m_burstcount_s = 0 and rx_first_read_done = '1' then
--rx fifo is filled with enough data -> build burst transfer
m_write_s <= '1';
m_burstcount_s <= conv_std_logic_vector(rx_burst_size_c, m_burstcount_s'length);
if m_burst_wr_const_g then
m_burstcount_latch <= conv_std_logic_vector(rx_burst_size_c, m_burstcount_latch'length);
m_address_latch <= rx_cnt;
end if;
elsif m_write_s = '1' and m_waitrequest = '0' and m_burstcount_s = 1 then
--last transfer is done -> deassert write qualifiers
m_write_s <= '0';
end if;
when finish =>
--MAC is finished with RX, transfer rest of fifo
---note: The last word (part of crc32) is not transferred!
if rx_rd_empty = '0' and m_read_s = '0' and m_write_s = '0' and tx_is_the_owner_v = '0' and m_burstcount_s = 0 then
--rx fifo has some data left
m_write_s <= '1';
--verify how many patterns are left in the fifo
if rx_rd_usedw < conv_std_logic_vector(rx_burst_size_c, rx_rd_usedw'length) then
--start the smaller burst write transfer
m_burstcount_s <= EXT(rx_rd_usedw, m_burstcount_s'length);
if m_burst_wr_const_g then
m_burstcount_latch <= EXT(rx_rd_usedw, m_burstcount_latch'length);
m_address_latch <= rx_cnt;
end if;
--workaround: fifo is not empty but word level is zero => set to one
if rx_rd_usedw = 0 then
m_burstcount_s <= conv_std_logic_vector(1, m_burstcount_s'length);
m_burstcount_latch <= conv_std_logic_vector(1, m_burstcount_latch'length);
end if;
else
--start the maximum burst write transfer
m_burstcount_s <= conv_std_logic_vector(rx_burst_size_c, m_burstcount_s'length);
if m_burst_wr_const_g then
m_burstcount_latch <= conv_std_logic_vector(rx_burst_size_c, m_burstcount_latch'length);
m_address_latch <= rx_cnt;
end if;
end if;
elsif m_write_s = '1' and m_waitrequest = '0' and m_burstcount_s = 1 then
--transfer is done -> deassert write qualifiers
m_write_s <= '0';
--completely done?!
if rx_rd_empty = '1' then
--yes!
rx_rd_done <= '1';
end if;
elsif rx_rd_empty = '1' and m_write_s = '0' then
--nothing left in the fifo and we don't try to do anything -> done!
rx_rd_done <= '1';
end if;
end case;
end if;
end if;
end process;
end master_handler;
| gpl-2.0 | 912c8f9fc2a0f90b280ead502ba5a673 | 0.499223 | 3.808244 | false | false | false | false |
ShepardSiegel/ocpi | vhdl/biasWorker.vhd | 1 | 5,231 | -- biasWorker.vhd
-- Copyright (c) 2009 Atomic Rules LLC - ALL RIGHTS RESERVED
--
-- 2009-07-11 ssiegel creation
-- 2009-07-12 ssiegel run thorough XST
-- 2009-07-13 ssiegel adapt to use ocpiTypes
-- 2009-07-15 ssiegel controlOp decode
-- 2010-03-01 ssiegel Added Peer-Peer WSI Resets
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.ocpiTypes.all;
entity biasWorker is
port (
clk : in std_logic;
rst_n : in std_logic;
-- WCI Port
-- WCI Req...
wci_MCmd : in std_logic_vector( 2 downto 0);
wci_MAddrSpace : in std_logic_vector( 0 downto 0);
wci_MByteEn : in std_logic_vector( 3 downto 0);
wci_MAddr : in std_logic_vector(19 downto 0);
wci_MData : in std_logic_vector(31 downto 0);
-- WCI Resp...
wci_SResp : out std_logic_vector( 1 downto 0);
wci_SData : out std_logic_vector(31 downto 0);
-- WCI Util...
wci_MFlag : in std_logic_vector( 1 downto 0);
wci_SFlag : out std_logic_vector( 1 downto 0);
wci_SThreadBusy : out std_logic;
-- WSI Slave Port (WSI0)
wsi0_MReset_n : in std_logic; -- Reset in from WSI partner
wsi0_SReset_n : out std_logic; -- Reset out to WSI partner
-- WSI Req...
wsi0_MCmd : in std_logic_vector( 2 downto 0);
wsi0_MReqLast : in std_logic;
wsi0_MBurstPrecise : in std_logic;
wsi0_MBurstLength : in std_logic_vector(11 downto 0);
wsi0_MData : in std_logic_vector(31 downto 0);
wsi0_MByteEn : in std_logic_vector( 3 downto 0);
wsi0_MReqInfo : in std_logic_vector( 7 downto 0);
-- WSI Util...
wsi0_SThreadBusy : out std_logic;
-- WSI Master Port (WSI1)
wsi1_MReset_n : out std_logic; -- Reset out to WSI partner
wsi1_SReset_n : in std_logic; -- Reset in from WSI partner
-- WSI Req...
wsi1_MCmd : out std_logic_vector( 2 downto 0);
wsi1_MReqLast : out std_logic;
wsi1_MBurstPrecise : out std_logic;
wsi1_MBurstLength : out std_logic_vector(11 downto 0);
wsi1_MData : out std_logic_vector(31 downto 0);
wsi1_MByteEn : out std_logic_vector( 3 downto 0);
wsi1_MReqInfo : out std_logic_vector( 7 downto 0);
-- WSI Util...
wsi1_SThreadBusy : in std_logic);
end biasWorker;
architecture rtl of biasWorker is
signal biasValue : std_logic_vector(31 downto 0);
signal wci_ctlSt : wciCtlStT;
signal wci_cfg_write : std_logic;
signal wci_cfg_read : std_logic;
signal wci_ctl_op : std_logic;
begin
--When this worker is WCI reset, propagate reset out to WSI partners...
wsi0_SReset_n <= rst_n;
wsi1_MReset_n <= rst_n;
wci_cfg_write <= to_std_logic(wci_MCmd=ocpCmd_WR and wci_MAddrSpace(0)='1');
wci_cfg_read <= to_std_logic(wci_MCmd=ocpCmd_RD and wci_MAddrSpace(0)='1');
wci_ctl_op <= to_std_logic(wci_MCmd=ocpCmd_RD and wci_MAddrSpace(0)='0');
-- Pass the SThreadBusy upstream without pipelining...
wsi0_SThreadBusy <= wsi1_SThreadBusy or to_std_logic(wci_ctlSt/=wciCtlSt_Operating);
reg : process(clk) is
begin
if rising_edge(clk) then
if (wci_ctlSt = wciCtlSt_Operating ) then -- Implement the biasWorker function...
wsi1_MData <= std_logic_vector(unsigned(wsi0_MData) + unsigned(biasValue));
wsi1_MCmd <= wsi0_MCmd;
else -- Or block the WSI pipeline cleanly...
wsi1_MData <= (others=>'0');
wsi1_MCmd <= ocpCmd_IDLE;
end if;
-- Pass through signals of the WSI interface that we maintain, but do not use...
wsi1_MReqLast <= wsi0_MReqLast;
wsi1_MBurstPrecise <= wsi0_MBurstPrecise;
wsi1_MBurstLength <= wsi0_MBurstLength;
wsi1_MByteEn <= wsi0_MByteEn;
wsi1_MReqInfo <= wsi0_MReqInfo;
-- Implement minimal WCI attach logic...
wci_SThreadBusy <= '0';
wci_SResp <= ocpResp_NULL;
wci_reset_clause : if (rst_n='0') then
wci_ctlSt <= wciCtlSt_Exists;
wci_SResp <= ocpResp_NULL;
wci_SFlag <= "00";
wci_SThreadBusy <= '1';
biasValue <= X"0000_0000";
else
-- WCI Configuration Property Writes...
if wci_cfg_write='1' then
biasValue <= wci_MData;
wci_SResp <= ocpResp_DVA;
end if;
-- WCI Configuration Property Reads...
if wci_cfg_read='1' then
wci_SData <= biasValue;
wci_SResp <= ocpResp_DVA;
end if;
-- WCI Control Operations...
if wci_ctl_op='1' then
case wci_MAddr(4 downto 2) is
when wciCtlOp_Initialize => wci_ctlSt <= wciCtlSt_Initialized;
when wciCtlOp_Start => wci_ctlSt <= wciCtlSt_Operating;
when wciCtlOp_Stop => wci_ctlSt <= wciCtlSt_Suspended;
when wciCtlOp_Release => wci_ctlSt <= wciCtlSt_Exists;
when others => null;
end case;
wci_SData <= wciResp_OK;
wci_SResp <= ocpResp_DVA;
end if;
end if wci_reset_clause;
end if;
end process reg;
end rtl;
| lgpl-3.0 | 66bfaf8397ac469e814defb0d9106382 | 0.590709 | 2.912584 | false | false | false | false |
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