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masaruohashi/tic-tac-toe | logica_jogo/valida_caractere.vhd | 1 | 1,133 | -- VHDL que verifica se o caractere eh valido
library ieee;
use ieee.std_logic_1164.all;
entity valida_caractere is
port(
caractere : in std_logic_vector(6 downto 0);
caractere_valido : out std_logic
);
end valida_caractere;
architecture estrutural of valida_caractere is
signal sinal_caractere_valido: std_logic := '0';
begin
process (caractere)
begin
case caractere is
when "0110111" =>
sinal_caractere_valido <= '1';
when "0111000" =>
sinal_caractere_valido <= '1';
when "0111001" =>
sinal_caractere_valido <= '1';
when "0110100" =>
sinal_caractere_valido <= '1';
when "0110101" =>
sinal_caractere_valido <= '1';
when "0110110" =>
sinal_caractere_valido <= '1';
when "0110001" =>
sinal_caractere_valido <= '1';
when "0110010" =>
sinal_caractere_valido <= '1';
when "0110011" =>
sinal_caractere_valido <= '1';
when others =>
sinal_caractere_valido <= '0';
end case;
caractere_valido <= sinal_caractere_valido;
end process;
end estrutural;
| mit | 1fa32d04c6f5f7b1e2c7fa23ae6553cc | 0.593998 | 3.332353 | false | false | false | false |
Nixon-/VHDL_library | basic/nbit_2to1_mux.vhd | 1 | 634 | Library ieee;
use ieee.std_logic_1164.all;
entity nbit_2to1_mux is
generic(
bitsPerVector: integer:=4
);
port(
inputBus0,inputBus1: in std_logic_vector(bitsPerVector -1 downto 0);
selector: in std_logic;
enable: in std_logic;
outputBus: out std_logic_vector(bitsPerVector-1 downto 0)
);
end nbit_2to1_mux;
architecture primary of nbit_2to1_mux is
begin
process(inputBus0,inputBus1,selector,enable) begin
if(enable = '1') then
case selector is
when '0'=> outputBus <= inputBus0;
when '1'=> outputBus <= inputBus1;
end case;
else
outputBus <= (others => '0');
end if;
end process;
end primary;
| gpl-2.0 | 91dd33bfda83fcc000340beb8442472f | 0.697161 | 2.80531 | false | false | false | false |
masaruohashi/tic-tac-toe | interface_jogo/unidade_controle_tabuleiro.vhd | 1 | 1,820 | -- VHDL da Unidade de Controle do modulo de impressão do tabuleiro
library ieee;
use ieee.std_logic_1164.all;
entity unidade_controle_tabuleiro is
port(
clock: in std_logic;
reset: in std_logic;
start: in std_logic;
fim_contagem: in std_logic;
uart_livre: in std_logic;
transmite_dado: out std_logic;
atualiza_caractere: out std_logic;
pronto: out std_logic
);
end unidade_controle_tabuleiro;
architecture comportamental of unidade_controle_tabuleiro is
type tipo_estado is (inicial, prepara, imprime, final);
signal estado : tipo_estado;
begin
process (clock, estado, reset)
begin
if reset = '1' then
estado <= inicial;
elsif (clock'event and clock = '1') then
case estado is
when inicial => -- Aguarda sinal de start
if start = '1' then
estado <= prepara;
else
estado <= inicial;
end if;
when prepara =>
if fim_contagem = '1' then
estado <= final;
else
estado <= imprime;
end if;
when imprime => -- Imprime o tabuleiro no terminal
if uart_livre = '1' then
estado <= prepara;
else
estado <= imprime;
end if;
when final =>
estado <= inicial;
when others => -- Default
estado <= inicial;
end case;
end if;
end process;
-- logica de saída
with estado select
transmite_dado <= '1' when imprime,
'0' when others;
with estado select
atualiza_caractere <= '1' when prepara,
'0' when others;
with estado select
pronto <= '1' when final,
'0' when others;
end comportamental;
| mit | 2219d269a799bac4473ae9972884112f | 0.551155 | 4.085393 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/pcie_core/simulation/dsport/pcie_2_0_rport_v6.vhd | 1 | 107,438 | -------------------------------------------------------------------------------
--
-- (c) Copyright 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : pcie_2_0_rport_v6.vhd
-- Description: Spartan-6 solution wrapper : Root Port for PCI Express
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity pcie_2_0_rport_v6 is
generic (
REF_CLK_FREQ : integer := 0; -- 0 - 100MHz, 1 - 125 MHz, 2 - 250 MHz
PIPE_PIPELINE_STAGES : integer := 0; -- 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
PCIE_DRP_ENABLE : boolean := FALSE;
DS_PORT_HOT_RST : boolean := FALSE; -- FALSE - for ROOT PORT(default), TRUE - for DOWNSTREAM PORT
LINK_CAP_MAX_LINK_WIDTH_int : integer := 8;
LTSSM_MAX_LINK_WIDTH : bit_vector := X"01";
AER_BASE_PTR : bit_vector := X"128";
AER_CAP_ECRC_CHECK_CAPABLE : boolean := FALSE;
AER_CAP_ECRC_GEN_CAPABLE : boolean := FALSE;
AER_CAP_ID : bit_vector := X"1111";
AER_CAP_INT_MSG_NUM_MSI : bit_vector := X"0A";
AER_CAP_INT_MSG_NUM_MSIX : bit_vector := X"15";
AER_CAP_NEXTPTR : bit_vector := X"160";
AER_CAP_ON : boolean := FALSE;
AER_CAP_PERMIT_ROOTERR_UPDATE : boolean := TRUE;
AER_CAP_VERSION : bit_vector := X"1";
ALLOW_X8_GEN2 : boolean := FALSE;
BAR0 : bit_vector := X"00000000"; -- Memory aperture disabled
BAR1 : bit_vector := X"00000000"; -- Memory aperture disabled
BAR2 : bit_vector := X"00FFFFFF"; -- Constant for rport
BAR3 : bit_vector := X"FFFF0000"; -- IO Limit/Base Registers not implemented
BAR4 : bit_vector := X"FFF0FFF0"; -- Constant for rport
BAR5 : bit_vector := X"FFF1FFF1"; -- Prefetchable Memory Limit/Base Registers implemented
CAPABILITIES_PTR : bit_vector := X"40";
CARDBUS_CIS_POINTER : bit_vector := X"00000000";
CLASS_CODE : bit_vector := X"060400";
CMD_INTX_IMPLEMENTED : boolean := TRUE;
CPL_TIMEOUT_DISABLE_SUPPORTED : boolean := FALSE;
CPL_TIMEOUT_RANGES_SUPPORTED : bit_vector := X"0";
CRM_MODULE_RSTS : bit_vector := X"00";
DEVICE_ID : bit_vector := X"0007";
DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE : boolean := TRUE;
DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE : boolean := TRUE;
DEV_CAP_ENDPOINT_L0S_LATENCY : integer := 0;
DEV_CAP_ENDPOINT_L1_LATENCY : integer := 0;
DEV_CAP_EXT_TAG_SUPPORTED : boolean := TRUE;
DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE : boolean := FALSE;
DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer := 2;
DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT : integer := 0;
DEV_CAP_ROLE_BASED_ERROR : boolean := TRUE;
DEV_CAP_RSVD_14_12 : integer := 0;
DEV_CAP_RSVD_17_16 : integer := 0;
DEV_CAP_RSVD_31_29 : integer := 0;
DEV_CONTROL_AUX_POWER_SUPPORTED : boolean := FALSE;
DISABLE_ASPM_L1_TIMER : boolean := FALSE;
DISABLE_BAR_FILTERING : boolean := TRUE;
DISABLE_ID_CHECK : boolean := TRUE;
DISABLE_LANE_REVERSAL : boolean := FALSE;
DISABLE_RX_TC_FILTER : boolean := TRUE;
DISABLE_SCRAMBLING : boolean := FALSE;
DNSTREAM_LINK_NUM : bit_vector := X"00";
DSN_BASE_PTR : bit_vector := X"100";
DSN_CAP_ID : bit_vector := X"0003";
DSN_CAP_NEXTPTR : bit_vector := X"01C";
DSN_CAP_ON : boolean := TRUE;
DSN_CAP_VERSION : bit_vector := X"1";
ENABLE_MSG_ROUTE : bit_vector := X"000";
ENABLE_RX_TD_ECRC_TRIM : boolean := FALSE;
ENTER_RVRY_EI_L0 : boolean := TRUE;
EXIT_LOOPBACK_ON_EI : boolean := TRUE;
EXPANSION_ROM : bit_vector := X"00000000"; -- Memory aperture disabled
EXT_CFG_CAP_PTR : bit_vector := X"3F";
EXT_CFG_XP_CAP_PTR : bit_vector := X"3FF";
HEADER_TYPE : bit_vector := X"01";
INFER_EI : bit_vector := X"0C";
INTERRUPT_PIN : bit_vector := X"01";
IS_SWITCH : boolean := FALSE;
LAST_CONFIG_DWORD : bit_vector := X"042";
LINK_CAP_ASPM_SUPPORT : integer := 1;
LINK_CAP_CLOCK_POWER_MANAGEMENT : boolean := FALSE;
LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP : boolean := FALSE;
LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 : integer := 7;
LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 : integer := 7;
LINK_CAP_L0S_EXIT_LATENCY_GEN1 : integer := 7;
LINK_CAP_L0S_EXIT_LATENCY_GEN2 : integer := 7;
LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 : integer := 7;
LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 : integer := 7;
LINK_CAP_L1_EXIT_LATENCY_GEN1 : integer := 7;
LINK_CAP_L1_EXIT_LATENCY_GEN2 : integer := 7;
LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP : boolean := FALSE;
LINK_CAP_MAX_LINK_SPEED : bit_vector := X"1";
LINK_CAP_MAX_LINK_WIDTH : bit_vector := X"08";
LINK_CAP_RSVD_23_22 : integer := 0;
LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE : boolean := FALSE;
LINK_CONTROL_RCB : integer := 0;
LINK_CTRL2_DEEMPHASIS : boolean := FALSE;
LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE : boolean := FALSE;
LINK_CTRL2_TARGET_LINK_SPEED : bit_vector := X"2";
LINK_STATUS_SLOT_CLOCK_CONFIG : boolean := TRUE;
LL_ACK_TIMEOUT : bit_vector := X"0000";
LL_ACK_TIMEOUT_EN : boolean := FALSE;
LL_ACK_TIMEOUT_FUNC : integer := 0;
LL_REPLAY_TIMEOUT : bit_vector := X"0000";
LL_REPLAY_TIMEOUT_EN : boolean := FALSE;
LL_REPLAY_TIMEOUT_FUNC : integer := 0;
MSIX_BASE_PTR : bit_vector := X"9C";
MSIX_CAP_ID : bit_vector := X"11";
MSIX_CAP_NEXTPTR : bit_vector := X"00";
MSIX_CAP_ON : boolean := TRUE;
MSIX_CAP_PBA_BIR : integer := 0;
MSIX_CAP_PBA_OFFSET : bit_vector := X"00000050";
MSIX_CAP_TABLE_BIR : integer := 0;
MSIX_CAP_TABLE_OFFSET : bit_vector := X"00000040";
MSIX_CAP_TABLE_SIZE : bit_vector := X"000";
MSI_BASE_PTR : bit_vector := X"48";
MSI_CAP_64_BIT_ADDR_CAPABLE : boolean := TRUE;
MSI_CAP_ID : bit_vector := X"05";
MSI_CAP_MULTIMSGCAP : integer := 0;
MSI_CAP_MULTIMSG_EXTENSION : integer := 0;
MSI_CAP_NEXTPTR : bit_vector := X"60";
MSI_CAP_ON : boolean := TRUE;
MSI_CAP_PER_VECTOR_MASKING_CAPABLE : boolean := TRUE;
N_FTS_COMCLK_GEN1 : integer := 255;
N_FTS_COMCLK_GEN2 : integer := 255;
N_FTS_GEN1 : integer := 255;
N_FTS_GEN2 : integer := 255;
PCIE_BASE_PTR : bit_vector := X"60";
PCIE_CAP_CAPABILITY_ID : bit_vector := X"10";
PCIE_CAP_CAPABILITY_VERSION : bit_vector := X"2";
PCIE_CAP_DEVICE_PORT_TYPE : bit_vector := X"4";
PCIE_CAP_INT_MSG_NUM : bit_vector := X"00";
PCIE_CAP_NEXTPTR : bit_vector := X"9C";
PCIE_CAP_ON : boolean := TRUE;
PCIE_CAP_RSVD_15_14 : integer := 0;
PCIE_CAP_SLOT_IMPLEMENTED : boolean := TRUE;
PCIE_REVISION : integer := 2;
PGL0_LANE : integer := 0;
PGL1_LANE : integer := 1;
PGL2_LANE : integer := 2;
PGL3_LANE : integer := 3;
PGL4_LANE : integer := 4;
PGL5_LANE : integer := 5;
PGL6_LANE : integer := 6;
PGL7_LANE : integer := 7;
PL_AUTO_CONFIG : integer := 0;
PL_FAST_TRAIN : boolean := FALSE;
PM_BASE_PTR : bit_vector := X"40";
PM_CAP_AUXCURRENT : integer := 0;
PM_CAP_D1SUPPORT : boolean := TRUE;
PM_CAP_D2SUPPORT : boolean := TRUE;
PM_CAP_DSI : boolean := FALSE;
PM_CAP_ID : bit_vector := X"11";
PM_CAP_NEXTPTR : bit_vector := X"48";
PM_CAP_ON : boolean := TRUE;
PM_CAP_PMESUPPORT : bit_vector := X"0F";
PM_CAP_PME_CLOCK : boolean := FALSE;
PM_CAP_RSVD_04 : integer := 0;
PM_CAP_VERSION : integer := 3;
PM_CSR_B2B3 : boolean := FALSE;
PM_CSR_BPCCEN : boolean := FALSE;
PM_CSR_NOSOFTRST : boolean := TRUE;
PM_DATA0 : bit_vector := X"01";
PM_DATA1 : bit_vector := X"01";
PM_DATA2 : bit_vector := X"01";
PM_DATA3 : bit_vector := X"01";
PM_DATA4 : bit_vector := X"01";
PM_DATA5 : bit_vector := X"01";
PM_DATA6 : bit_vector := X"01";
PM_DATA7 : bit_vector := X"01";
PM_DATA_SCALE0 : bit_vector := X"1";
PM_DATA_SCALE1 : bit_vector := X"1";
PM_DATA_SCALE2 : bit_vector := X"1";
PM_DATA_SCALE3 : bit_vector := X"1";
PM_DATA_SCALE4 : bit_vector := X"1";
PM_DATA_SCALE5 : bit_vector := X"1";
PM_DATA_SCALE6 : bit_vector := X"1";
PM_DATA_SCALE7 : bit_vector := X"1";
RECRC_CHK : integer := 0;
RECRC_CHK_TRIM : boolean := FALSE;
REVISION_ID : bit_vector := X"00";
ROOT_CAP_CRS_SW_VISIBILITY : boolean := FALSE;
SELECT_DLL_IF : boolean := FALSE;
SIM_VERSION : string := "1.0";
SLOT_CAP_ATT_BUTTON_PRESENT : boolean := FALSE;
SLOT_CAP_ATT_INDICATOR_PRESENT : boolean := FALSE;
SLOT_CAP_ELEC_INTERLOCK_PRESENT : boolean := FALSE;
SLOT_CAP_HOTPLUG_CAPABLE : boolean := FALSE;
SLOT_CAP_HOTPLUG_SURPRISE : boolean := FALSE;
SLOT_CAP_MRL_SENSOR_PRESENT : boolean := FALSE;
SLOT_CAP_NO_CMD_COMPLETED_SUPPORT : boolean := FALSE;
SLOT_CAP_PHYSICAL_SLOT_NUM : bit_vector := X"0000";
SLOT_CAP_POWER_CONTROLLER_PRESENT : boolean := FALSE;
SLOT_CAP_POWER_INDICATOR_PRESENT : boolean := FALSE;
SLOT_CAP_SLOT_POWER_LIMIT_SCALE : integer := 0;
SLOT_CAP_SLOT_POWER_LIMIT_VALUE : bit_vector := X"00";
SPARE_BIT0 : integer := 0;
SPARE_BIT1 : integer := 0;
SPARE_BIT2 : integer := 0;
SPARE_BIT3 : integer := 0;
SPARE_BIT4 : integer := 0;
SPARE_BIT5 : integer := 0;
SPARE_BIT6 : integer := 0;
SPARE_BIT7 : integer := 0;
SPARE_BIT8 : integer := 0;
SPARE_BYTE0 : bit_vector := X"00";
SPARE_BYTE1 : bit_vector := X"00";
SPARE_BYTE2 : bit_vector := X"00";
SPARE_BYTE3 : bit_vector := X"00";
SPARE_WORD0 : bit_vector := X"00000000";
SPARE_WORD1 : bit_vector := X"00000000";
SPARE_WORD2 : bit_vector := X"00000000";
SPARE_WORD3 : bit_vector := X"00000000";
SUBSYSTEM_ID : bit_vector := X"0007";
SUBSYSTEM_VENDOR_ID : bit_vector := X"10EE";
TL_RBYPASS : boolean := FALSE;
TL_RX_RAM_RADDR_LATENCY : integer := 0;
TL_RX_RAM_RDATA_LATENCY : integer := 2;
TL_RX_RAM_WRITE_LATENCY : integer := 0;
TL_TFC_DISABLE : boolean := FALSE;
TL_TX_CHECKS_DISABLE : boolean := FALSE;
TL_TX_RAM_RADDR_LATENCY : integer := 0;
TL_TX_RAM_RDATA_LATENCY : integer := 2;
TL_TX_RAM_WRITE_LATENCY : integer := 0;
UPCONFIG_CAPABLE : boolean := TRUE;
UPSTREAM_FACING : boolean := FALSE;
UR_INV_REQ : boolean := TRUE;
USER_CLK_FREQ : integer := 3;
VC0_CPL_INFINITE : boolean := TRUE;
VC0_RX_RAM_LIMIT : bit_vector := X"03FF";
VC0_TOTAL_CREDITS_CD : integer := 127;
VC0_TOTAL_CREDITS_CH : integer := 31;
VC0_TOTAL_CREDITS_NPH : integer := 12;
VC0_TOTAL_CREDITS_PD : integer := 288;
VC0_TOTAL_CREDITS_PH : integer := 32;
VC0_TX_LASTPACKET : integer := 31;
VC_BASE_PTR : bit_vector := X"10C";
VC_CAP_ID : bit_vector := X"0002";
VC_CAP_NEXTPTR : bit_vector := X"128";
VC_CAP_ON : boolean := TRUE;
VC_CAP_REJECT_SNOOP_TRANSACTIONS : boolean := FALSE;
VC_CAP_VERSION : bit_vector := X"1";
VENDOR_ID : bit_vector := X"10EE";
VSEC_BASE_PTR : bit_vector := X"160";
VSEC_CAP_HDR_ID : bit_vector := X"1234";
VSEC_CAP_HDR_LENGTH : bit_vector := X"018";
VSEC_CAP_HDR_REVISION : bit_vector := X"1";
VSEC_CAP_ID : bit_vector := X"000B";
VSEC_CAP_IS_LINK_VISIBLE : boolean := TRUE;
VSEC_CAP_NEXTPTR : bit_vector := X"000";
VSEC_CAP_ON : boolean := TRUE;
VSEC_CAP_VERSION : bit_vector := X"1"
);
port (
---------------------------------------------------------
-- 1. PCI Express (pci_exp) Interface
---------------------------------------------------------
-- Tx
pci_exp_txp : out std_logic_vector(LINK_CAP_MAX_LINK_WIDTH_int - 1 downto 0);
pci_exp_txn : out std_logic_vector(LINK_CAP_MAX_LINK_WIDTH_int - 1 downto 0);
-- Rx
pci_exp_rxp : in std_logic_vector(LINK_CAP_MAX_LINK_WIDTH_int - 1 downto 0);
pci_exp_rxn : in std_logic_vector(LINK_CAP_MAX_LINK_WIDTH_int - 1 downto 0);
---------------------------------------------------------
-- 2. Transaction (TRN) Interface
---------------------------------------------------------
-- Common
trn_clk : out std_logic;
trn_reset_n : out std_logic;
trn_lnk_up_n : out std_logic;
-- Tx
trn_tbuf_av : out std_logic_vector(5 downto 0);
trn_tcfg_req_n : out std_logic;
trn_terr_drop_n : out std_logic;
trn_tdst_rdy_n : out std_logic;
trn_td : in std_logic_vector(63 downto 0);
trn_trem_n : in std_logic;
trn_tsof_n : in std_logic;
trn_teof_n : in std_logic;
trn_tsrc_rdy_n : in std_logic;
trn_tsrc_dsc_n : in std_logic;
trn_terrfwd_n : in std_logic;
trn_tcfg_gnt_n : in std_logic;
trn_tstr_n : in std_logic;
-- Rx
trn_rd : out std_logic_vector(63 downto 0);
trn_rrem_n : out std_logic;
trn_rsof_n : out std_logic;
trn_reof_n : out std_logic;
trn_rsrc_rdy_n : out std_logic;
trn_rsrc_dsc_n : out std_logic;
trn_rerrfwd_n : out std_logic;
trn_rbar_hit_n : out std_logic_vector(6 downto 0);
trn_rdst_rdy_n : in std_logic;
trn_rnp_ok_n : in std_logic;
trn_recrc_err_n : out std_logic;
-- Flow Control
trn_fc_cpld : out std_logic_vector(11 downto 0);
trn_fc_cplh : out std_logic_vector(7 downto 0);
trn_fc_npd : out std_logic_vector(11 downto 0);
trn_fc_nph : out std_logic_vector(7 downto 0);
trn_fc_pd : out std_logic_vector(11 downto 0);
trn_fc_ph : out std_logic_vector(7 downto 0);
trn_fc_sel : in std_logic_vector(2 downto 0);
---------------------------------------------------------
-- 3. Configuration (CFG) Interface
---------------------------------------------------------
cfg_do : out std_logic_vector(31 downto 0);
cfg_rd_wr_done_n : out std_logic;
cfg_di : in std_logic_vector(31 downto 0);
cfg_byte_en_n : in std_logic_vector(3 downto 0);
cfg_dwaddr : in std_logic_vector(9 downto 0);
cfg_wr_en_n : in std_logic;
cfg_wr_rw1c_as_rw_n : in std_logic;
cfg_rd_en_n : in std_logic;
cfg_err_cor_n : in std_logic;
cfg_err_ur_n : in std_logic;
cfg_err_ecrc_n : in std_logic;
cfg_err_cpl_timeout_n : in std_logic;
cfg_err_cpl_abort_n : in std_logic;
cfg_err_cpl_unexpect_n : in std_logic;
cfg_err_posted_n : in std_logic;
cfg_err_locked_n : in std_logic;
cfg_err_tlp_cpl_header : in std_logic_vector(47 downto 0);
cfg_err_cpl_rdy_n : out std_logic;
cfg_interrupt_n : in std_logic;
cfg_interrupt_rdy_n : out std_logic;
cfg_interrupt_assert_n : in std_logic;
cfg_interrupt_di : in std_logic_vector(7 downto 0);
cfg_interrupt_do : out std_logic_vector(7 downto 0);
cfg_interrupt_mmenable : out std_logic_vector(2 downto 0);
cfg_interrupt_msienable : out std_logic;
cfg_interrupt_msixenable : out std_logic;
cfg_interrupt_msixfm : out std_logic;
cfg_trn_pending_n : in std_logic;
cfg_pm_send_pme_to_n : in std_logic;
cfg_status : out std_logic_vector(15 downto 0);
cfg_command : out std_logic_vector(15 downto 0);
cfg_dstatus : out std_logic_vector(15 downto 0);
cfg_dcommand : out std_logic_vector(15 downto 0);
cfg_lstatus : out std_logic_vector(15 downto 0);
cfg_lcommand : out std_logic_vector(15 downto 0);
cfg_dcommand2 : out std_logic_vector(15 downto 0);
cfg_pcie_link_state_n : out std_logic_vector(2 downto 0);
cfg_dsn : in std_logic_vector(63 downto 0);
cfg_pmcsr_pme_en : out std_logic;
cfg_pmcsr_pme_status : out std_logic;
cfg_pmcsr_powerstate : out std_logic_vector(1 downto 0);
cfg_msg_received : out std_logic;
cfg_msg_data : out std_logic_vector(15 downto 0);
cfg_msg_received_err_cor : out std_logic;
cfg_msg_received_err_non_fatal : out std_logic;
cfg_msg_received_err_fatal : out std_logic;
cfg_msg_received_pme_to_ack : out std_logic;
cfg_msg_received_assert_inta : out std_logic;
cfg_msg_received_assert_intb : out std_logic;
cfg_msg_received_assert_intc : out std_logic;
cfg_msg_received_assert_intd : out std_logic;
cfg_msg_received_deassert_inta : out std_logic;
cfg_msg_received_deassert_intb : out std_logic;
cfg_msg_received_deassert_intc : out std_logic;
cfg_msg_received_deassert_intd : out std_logic;
cfg_ds_bus_number : in std_logic_vector(7 downto 0);
cfg_ds_device_number : in std_logic_vector(4 downto 0);
---------------------------------------------------------
-- 4. Physical Layer Control and Status (PL) Interface
---------------------------------------------------------
pl_initial_link_width : out std_logic_vector(2 downto 0);
pl_lane_reversal_mode : out std_logic_vector(1 downto 0);
pl_link_gen2_capable : out std_logic;
pl_link_partner_gen2_supported : out std_logic;
pl_link_upcfg_capable : out std_logic;
pl_ltssm_state : out std_logic_vector(5 downto 0);
pl_sel_link_rate : out std_logic;
pl_sel_link_width : out std_logic_vector(1 downto 0);
pl_directed_link_auton : in std_logic;
pl_directed_link_change : in std_logic_vector(1 downto 0);
pl_directed_link_speed : in std_logic;
pl_directed_link_width : in std_logic_vector(1 downto 0);
pl_upstream_prefer_deemph : in std_logic;
pl_transmit_hot_rst : in std_logic;
---------------------------------------------------------
-- 5. PCIe DRP (PCIe DRP) Interface
---------------------------------------------------------
pcie_drp_clk : in std_logic;
pcie_drp_den : in std_logic;
pcie_drp_dwe : in std_logic;
pcie_drp_daddr : in std_logic_vector(8 downto 0);
pcie_drp_di : in std_logic_vector(15 downto 0);
pcie_drp_do : out std_logic_vector(15 downto 0);
pcie_drp_drdy : out std_logic;
---------------------------------------------------------
-- 6. System (SYS) Interface
---------------------------------------------------------
sys_clk : in std_logic;
sys_reset_n : in std_logic
);
end pcie_2_0_rport_v6;
architecture v6_pcie of pcie_2_0_rport_v6 is
component pcie_reset_delay_v6
generic (
PL_FAST_TRAIN : boolean;
REF_CLK_FREQ : integer);
port (
ref_clk : in std_logic;
sys_reset_n : in std_logic;
delayed_sys_reset_n : out std_logic);
end component;
component pcie_clocking_v6
generic (
IS_ENDPOINT : boolean;
CAP_LINK_WIDTH : integer;
CAP_LINK_SPEED : integer;
REF_CLK_FREQ : integer;
USER_CLK_FREQ : integer);
port (
sys_clk : in std_logic;
gt_pll_lock : in std_logic;
sel_lnk_rate : in std_logic;
sel_lnk_width : in std_logic_vector(1 downto 0);
sys_clk_bufg : out std_logic;
pipe_clk : out std_logic;
user_clk : out std_logic;
block_clk : out std_logic;
drp_clk : out std_logic;
clock_locked : out std_logic);
end component;
component pcie_2_0_v6_rp
generic (
REF_CLK_FREQ : integer;
PIPE_PIPELINE_STAGES : integer;
LINK_CAP_MAX_LINK_WIDTH_int : integer;
AER_BASE_PTR : bit_vector;
AER_CAP_ECRC_CHECK_CAPABLE : boolean;
AER_CAP_ECRC_GEN_CAPABLE : boolean;
AER_CAP_ID : bit_vector;
AER_CAP_INT_MSG_NUM_MSI : bit_vector;
AER_CAP_INT_MSG_NUM_MSIX : bit_vector;
AER_CAP_NEXTPTR : bit_vector;
AER_CAP_ON : boolean;
AER_CAP_PERMIT_ROOTERR_UPDATE : boolean;
AER_CAP_VERSION : bit_vector;
ALLOW_X8_GEN2 : boolean;
BAR0 : bit_vector;
BAR1 : bit_vector;
BAR2 : bit_vector;
BAR3 : bit_vector;
BAR4 : bit_vector;
BAR5 : bit_vector;
CAPABILITIES_PTR : bit_vector;
CARDBUS_CIS_POINTER : bit_vector;
CLASS_CODE : bit_vector;
CMD_INTX_IMPLEMENTED : boolean;
CPL_TIMEOUT_DISABLE_SUPPORTED : boolean;
CPL_TIMEOUT_RANGES_SUPPORTED : bit_vector;
CRM_MODULE_RSTS : bit_vector;
DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE : boolean;
DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE : boolean;
DEV_CAP_ENDPOINT_L0S_LATENCY : integer;
DEV_CAP_ENDPOINT_L1_LATENCY : integer;
DEV_CAP_EXT_TAG_SUPPORTED : boolean;
DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE : boolean;
DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer;
DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT : integer;
DEV_CAP_ROLE_BASED_ERROR : boolean;
DEV_CAP_RSVD_14_12 : integer;
DEV_CAP_RSVD_17_16 : integer;
DEV_CAP_RSVD_31_29 : integer;
DEV_CONTROL_AUX_POWER_SUPPORTED : boolean;
DEVICE_ID : bit_vector;
DISABLE_ASPM_L1_TIMER : boolean;
DISABLE_BAR_FILTERING : boolean;
DISABLE_ID_CHECK : boolean;
DISABLE_LANE_REVERSAL : boolean;
DISABLE_RX_TC_FILTER : boolean;
DISABLE_SCRAMBLING : boolean;
DNSTREAM_LINK_NUM : bit_vector;
DSN_BASE_PTR : bit_vector;
DSN_CAP_ID : bit_vector;
DSN_CAP_NEXTPTR : bit_vector;
DSN_CAP_ON : boolean;
DSN_CAP_VERSION : bit_vector;
ENABLE_MSG_ROUTE : bit_vector;
ENABLE_RX_TD_ECRC_TRIM : boolean;
ENTER_RVRY_EI_L0 : boolean;
EXPANSION_ROM : bit_vector;
EXT_CFG_CAP_PTR : bit_vector;
EXT_CFG_XP_CAP_PTR : bit_vector;
HEADER_TYPE : bit_vector;
INFER_EI : bit_vector;
INTERRUPT_PIN : bit_vector;
IS_SWITCH : boolean;
LAST_CONFIG_DWORD : bit_vector;
LINK_CAP_ASPM_SUPPORT : integer;
LINK_CAP_CLOCK_POWER_MANAGEMENT : boolean;
LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP : boolean;
LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 : integer;
LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 : integer;
LINK_CAP_L0S_EXIT_LATENCY_GEN1 : integer;
LINK_CAP_L0S_EXIT_LATENCY_GEN2 : integer;
LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 : integer;
LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 : integer;
LINK_CAP_L1_EXIT_LATENCY_GEN1 : integer;
LINK_CAP_L1_EXIT_LATENCY_GEN2 : integer;
LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP : boolean;
LINK_CAP_MAX_LINK_SPEED : bit_vector;
LINK_CAP_MAX_LINK_WIDTH : bit_vector;
LINK_CAP_RSVD_23_22 : integer;
LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE : boolean;
LINK_CONTROL_RCB : integer;
LINK_CTRL2_DEEMPHASIS : boolean;
LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE : boolean;
LINK_CTRL2_TARGET_LINK_SPEED : bit_vector;
LINK_STATUS_SLOT_CLOCK_CONFIG : boolean;
LL_ACK_TIMEOUT : bit_vector;
LL_ACK_TIMEOUT_EN : boolean;
LL_ACK_TIMEOUT_FUNC : integer;
LL_REPLAY_TIMEOUT : bit_vector;
LL_REPLAY_TIMEOUT_EN : boolean;
LL_REPLAY_TIMEOUT_FUNC : integer;
LTSSM_MAX_LINK_WIDTH : bit_vector;
MSI_BASE_PTR : bit_vector;
MSI_CAP_ID : bit_vector;
MSI_CAP_MULTIMSGCAP : integer;
MSI_CAP_MULTIMSG_EXTENSION : integer;
MSI_CAP_NEXTPTR : bit_vector;
MSI_CAP_ON : boolean;
MSI_CAP_PER_VECTOR_MASKING_CAPABLE : boolean;
MSI_CAP_64_BIT_ADDR_CAPABLE : boolean;
MSIX_BASE_PTR : bit_vector;
MSIX_CAP_ID : bit_vector;
MSIX_CAP_NEXTPTR : bit_vector;
MSIX_CAP_ON : boolean;
MSIX_CAP_PBA_BIR : integer;
MSIX_CAP_PBA_OFFSET : bit_vector;
MSIX_CAP_TABLE_BIR : integer;
MSIX_CAP_TABLE_OFFSET : bit_vector;
MSIX_CAP_TABLE_SIZE : bit_vector;
N_FTS_COMCLK_GEN1 : integer;
N_FTS_COMCLK_GEN2 : integer;
N_FTS_GEN1 : integer;
N_FTS_GEN2 : integer;
PCIE_BASE_PTR : bit_vector;
PCIE_CAP_CAPABILITY_ID : bit_vector;
PCIE_CAP_CAPABILITY_VERSION : bit_vector;
PCIE_CAP_DEVICE_PORT_TYPE : bit_vector;
PCIE_CAP_INT_MSG_NUM : bit_vector;
PCIE_CAP_NEXTPTR : bit_vector;
PCIE_CAP_ON : boolean;
PCIE_CAP_RSVD_15_14 : integer;
PCIE_CAP_SLOT_IMPLEMENTED : boolean;
PCIE_REVISION : integer;
PGL0_LANE : integer;
PGL1_LANE : integer;
PGL2_LANE : integer;
PGL3_LANE : integer;
PGL4_LANE : integer;
PGL5_LANE : integer;
PGL6_LANE : integer;
PGL7_LANE : integer;
PL_AUTO_CONFIG : integer;
PL_FAST_TRAIN : boolean;
PM_BASE_PTR : bit_vector;
PM_CAP_AUXCURRENT : integer;
PM_CAP_DSI : boolean;
PM_CAP_D1SUPPORT : boolean;
PM_CAP_D2SUPPORT : boolean;
PM_CAP_ID : bit_vector;
PM_CAP_NEXTPTR : bit_vector;
PM_CAP_ON : boolean;
PM_CAP_PME_CLOCK : boolean;
PM_CAP_PMESUPPORT : bit_vector;
PM_CAP_RSVD_04 : integer;
PM_CAP_VERSION : integer;
PM_CSR_BPCCEN : boolean;
PM_CSR_B2B3 : boolean;
PM_CSR_NOSOFTRST : boolean;
PM_DATA0 : bit_vector;
PM_DATA1 : bit_vector;
PM_DATA2 : bit_vector;
PM_DATA3 : bit_vector;
PM_DATA4 : bit_vector;
PM_DATA5 : bit_vector;
PM_DATA6 : bit_vector;
PM_DATA7 : bit_vector;
PM_DATA_SCALE0 : bit_vector;
PM_DATA_SCALE1 : bit_vector;
PM_DATA_SCALE2 : bit_vector;
PM_DATA_SCALE3 : bit_vector;
PM_DATA_SCALE4 : bit_vector;
PM_DATA_SCALE5 : bit_vector;
PM_DATA_SCALE6 : bit_vector;
PM_DATA_SCALE7 : bit_vector;
RECRC_CHK : integer;
RECRC_CHK_TRIM : boolean;
REVISION_ID : bit_vector;
ROOT_CAP_CRS_SW_VISIBILITY : boolean;
SELECT_DLL_IF : boolean;
SLOT_CAP_ATT_BUTTON_PRESENT : boolean;
SLOT_CAP_ATT_INDICATOR_PRESENT : boolean;
SLOT_CAP_ELEC_INTERLOCK_PRESENT : boolean;
SLOT_CAP_HOTPLUG_CAPABLE : boolean;
SLOT_CAP_HOTPLUG_SURPRISE : boolean;
SLOT_CAP_MRL_SENSOR_PRESENT : boolean;
SLOT_CAP_NO_CMD_COMPLETED_SUPPORT : boolean;
SLOT_CAP_PHYSICAL_SLOT_NUM : bit_vector;
SLOT_CAP_POWER_CONTROLLER_PRESENT : boolean;
SLOT_CAP_POWER_INDICATOR_PRESENT : boolean;
SLOT_CAP_SLOT_POWER_LIMIT_SCALE : integer;
SLOT_CAP_SLOT_POWER_LIMIT_VALUE : bit_vector;
SPARE_BIT0 : integer;
SPARE_BIT1 : integer;
SPARE_BIT2 : integer;
SPARE_BIT3 : integer;
SPARE_BIT4 : integer;
SPARE_BIT5 : integer;
SPARE_BIT6 : integer;
SPARE_BIT7 : integer;
SPARE_BIT8 : integer;
SPARE_BYTE0 : bit_vector;
SPARE_BYTE1 : bit_vector;
SPARE_BYTE2 : bit_vector;
SPARE_BYTE3 : bit_vector;
SPARE_WORD0 : bit_vector;
SPARE_WORD1 : bit_vector;
SPARE_WORD2 : bit_vector;
SPARE_WORD3 : bit_vector;
SUBSYSTEM_ID : bit_vector;
SUBSYSTEM_VENDOR_ID : bit_vector;
TL_RBYPASS : boolean;
TL_RX_RAM_RADDR_LATENCY : integer;
TL_RX_RAM_RDATA_LATENCY : integer;
TL_RX_RAM_WRITE_LATENCY : integer;
TL_TFC_DISABLE : boolean;
TL_TX_CHECKS_DISABLE : boolean;
TL_TX_RAM_RADDR_LATENCY : integer;
TL_TX_RAM_RDATA_LATENCY : integer;
TL_TX_RAM_WRITE_LATENCY : integer;
UPCONFIG_CAPABLE : boolean;
UPSTREAM_FACING : boolean;
UR_INV_REQ : boolean;
USER_CLK_FREQ : integer;
EXIT_LOOPBACK_ON_EI : boolean;
VC_BASE_PTR : bit_vector;
VC_CAP_ID : bit_vector;
VC_CAP_NEXTPTR : bit_vector;
VC_CAP_ON : boolean;
VC_CAP_REJECT_SNOOP_TRANSACTIONS : boolean;
VC_CAP_VERSION : bit_vector;
VC0_CPL_INFINITE : boolean;
VC0_RX_RAM_LIMIT : bit_vector;
VC0_TOTAL_CREDITS_CD : integer;
VC0_TOTAL_CREDITS_CH : integer;
VC0_TOTAL_CREDITS_NPH : integer;
VC0_TOTAL_CREDITS_PD : integer;
VC0_TOTAL_CREDITS_PH : integer;
VC0_TX_LASTPACKET : integer;
VENDOR_ID : bit_vector;
VSEC_BASE_PTR : bit_vector;
VSEC_CAP_HDR_ID : bit_vector;
VSEC_CAP_HDR_LENGTH : bit_vector;
VSEC_CAP_HDR_REVISION : bit_vector;
VSEC_CAP_ID : bit_vector;
VSEC_CAP_IS_LINK_VISIBLE : boolean;
VSEC_CAP_NEXTPTR : bit_vector;
VSEC_CAP_ON : boolean;
VSEC_CAP_VERSION : bit_vector);
port (
PCIEXPRXN : in std_logic_vector(LINK_CAP_MAX_LINK_WIDTH_int - 1 downto 0);
PCIEXPRXP : in std_logic_vector(LINK_CAP_MAX_LINK_WIDTH_int - 1 downto 0);
PCIEXPTXN : out std_logic_vector(LINK_CAP_MAX_LINK_WIDTH_int - 1 downto 0);
PCIEXPTXP : out std_logic_vector(LINK_CAP_MAX_LINK_WIDTH_int - 1 downto 0);
SYSCLK : in std_logic;
FUNDRSTN : in std_logic;
TRNLNKUPN : out std_logic;
TRNCLK : out std_logic;
PHYRDYN : out std_logic;
USERRSTN : out std_logic;
RECEIVEDFUNCLVLRSTN : out std_logic;
LNKCLKEN : out std_logic;
SYSRSTN : in std_logic;
PLRSTN : in std_logic;
DLRSTN : in std_logic;
TLRSTN : in std_logic;
FUNCLVLRSTN : in std_logic;
CMRSTN : in std_logic;
CMSTICKYRSTN : in std_logic;
TRNRBARHITN : out std_logic_vector(6 downto 0);
TRNRD : out std_logic_vector(63 downto 0);
TRNRECRCERRN : out std_logic;
TRNREOFN : out std_logic;
TRNRERRFWDN : out std_logic;
TRNRREMN : out std_logic;
TRNRSOFN : out std_logic;
TRNRSRCDSCN : out std_logic;
TRNRSRCRDYN : out std_logic;
TRNRDSTRDYN : in std_logic;
TRNRNPOKN : in std_logic;
TRNTBUFAV : out std_logic_vector(5 downto 0);
TRNTCFGREQN : out std_logic;
TRNTDLLPDSTRDYN : out std_logic;
TRNTDSTRDYN : out std_logic;
TRNTERRDROPN : out std_logic;
TRNTCFGGNTN : in std_logic;
TRNTD : in std_logic_vector(63 downto 0);
TRNTDLLPDATA : in std_logic_vector(31 downto 0);
TRNTDLLPSRCRDYN : in std_logic;
TRNTECRCGENN : in std_logic;
TRNTEOFN : in std_logic;
TRNTERRFWDN : in std_logic;
TRNTREMN : in std_logic;
TRNTSOFN : in std_logic;
TRNTSRCDSCN : in std_logic;
TRNTSRCRDYN : in std_logic;
TRNTSTRN : in std_logic;
TRNFCCPLD : out std_logic_vector(11 downto 0);
TRNFCCPLH : out std_logic_vector(7 downto 0);
TRNFCNPD : out std_logic_vector(11 downto 0);
TRNFCNPH : out std_logic_vector(7 downto 0);
TRNFCPD : out std_logic_vector(11 downto 0);
TRNFCPH : out std_logic_vector(7 downto 0);
TRNFCSEL : in std_logic_vector(2 downto 0);
CFGAERECRCCHECKEN : out std_logic;
CFGAERECRCGENEN : out std_logic;
CFGCOMMANDBUSMASTERENABLE : out std_logic;
CFGCOMMANDINTERRUPTDISABLE : out std_logic;
CFGCOMMANDIOENABLE : out std_logic;
CFGCOMMANDMEMENABLE : out std_logic;
CFGCOMMANDSERREN : out std_logic;
CFGDEVCONTROLAUXPOWEREN : out std_logic;
CFGDEVCONTROLCORRERRREPORTINGEN : out std_logic;
CFGDEVCONTROLENABLERO : out std_logic;
CFGDEVCONTROLEXTTAGEN : out std_logic;
CFGDEVCONTROLFATALERRREPORTINGEN : out std_logic;
CFGDEVCONTROLMAXPAYLOAD : out std_logic_vector(2 downto 0);
CFGDEVCONTROLMAXREADREQ : out std_logic_vector(2 downto 0);
CFGDEVCONTROLNONFATALREPORTINGEN : out std_logic;
CFGDEVCONTROLNOSNOOPEN : out std_logic;
CFGDEVCONTROLPHANTOMEN : out std_logic;
CFGDEVCONTROLURERRREPORTINGEN : out std_logic;
CFGDEVCONTROL2CPLTIMEOUTDIS : out std_logic;
CFGDEVCONTROL2CPLTIMEOUTVAL : out std_logic_vector(3 downto 0);
CFGDEVSTATUSCORRERRDETECTED : out std_logic;
CFGDEVSTATUSFATALERRDETECTED : out std_logic;
CFGDEVSTATUSNONFATALERRDETECTED : out std_logic;
CFGDEVSTATUSURDETECTED : out std_logic;
CFGDO : out std_logic_vector(31 downto 0);
CFGERRAERHEADERLOGSETN : out std_logic;
CFGERRCPLRDYN : out std_logic;
CFGINTERRUPTDO : out std_logic_vector(7 downto 0);
CFGINTERRUPTMMENABLE : out std_logic_vector(2 downto 0);
CFGINTERRUPTMSIENABLE : out std_logic;
CFGINTERRUPTMSIXENABLE : out std_logic;
CFGINTERRUPTMSIXFM : out std_logic;
CFGINTERRUPTRDYN : out std_logic;
CFGLINKCONTROLRCB : out std_logic;
CFGLINKCONTROLASPMCONTROL : out std_logic_vector(1 downto 0);
CFGLINKCONTROLAUTOBANDWIDTHINTEN : out std_logic;
CFGLINKCONTROLBANDWIDTHINTEN : out std_logic;
CFGLINKCONTROLCLOCKPMEN : out std_logic;
CFGLINKCONTROLCOMMONCLOCK : out std_logic;
CFGLINKCONTROLEXTENDEDSYNC : out std_logic;
CFGLINKCONTROLHWAUTOWIDTHDIS : out std_logic;
CFGLINKCONTROLLINKDISABLE : out std_logic;
CFGLINKCONTROLRETRAINLINK : out std_logic;
CFGLINKSTATUSAUTOBANDWIDTHSTATUS : out std_logic;
CFGLINKSTATUSBANDWITHSTATUS : out std_logic;
CFGLINKSTATUSCURRENTSPEED : out std_logic_vector(1 downto 0);
CFGLINKSTATUSDLLACTIVE : out std_logic;
CFGLINKSTATUSLINKTRAINING : out std_logic;
CFGLINKSTATUSNEGOTIATEDWIDTH : out std_logic_vector(3 downto 0);
CFGMSGDATA : out std_logic_vector(15 downto 0);
CFGMSGRECEIVED : out std_logic;
CFGMSGRECEIVEDASSERTINTA : out std_logic;
CFGMSGRECEIVEDASSERTINTB : out std_logic;
CFGMSGRECEIVEDASSERTINTC : out std_logic;
CFGMSGRECEIVEDASSERTINTD : out std_logic;
CFGMSGRECEIVEDDEASSERTINTA : out std_logic;
CFGMSGRECEIVEDDEASSERTINTB : out std_logic;
CFGMSGRECEIVEDDEASSERTINTC : out std_logic;
CFGMSGRECEIVEDDEASSERTINTD : out std_logic;
CFGMSGRECEIVEDERRCOR : out std_logic;
CFGMSGRECEIVEDERRFATAL : out std_logic;
CFGMSGRECEIVEDERRNONFATAL : out std_logic;
CFGMSGRECEIVEDPMASNAK : out std_logic;
CFGMSGRECEIVEDPMETO : out std_logic;
CFGMSGRECEIVEDPMETOACK : out std_logic;
CFGMSGRECEIVEDPMPME : out std_logic;
CFGMSGRECEIVEDSETSLOTPOWERLIMIT : out std_logic;
CFGMSGRECEIVEDUNLOCK : out std_logic;
CFGPCIELINKSTATE : out std_logic_vector(2 downto 0);
CFGPMCSRPMEEN : out std_logic;
CFGPMCSRPMESTATUS : out std_logic;
CFGPMCSRPOWERSTATE : out std_logic_vector(1 downto 0);
CFGPMRCVASREQL1N : out std_logic;
CFGPMRCVENTERL1N : out std_logic;
CFGPMRCVENTERL23N : out std_logic;
CFGPMRCVREQACKN : out std_logic;
CFGRDWRDONEN : out std_logic;
CFGSLOTCONTROLELECTROMECHILCTLPULSE : out std_logic;
CFGTRANSACTION : out std_logic;
CFGTRANSACTIONADDR : out std_logic_vector(6 downto 0);
CFGTRANSACTIONTYPE : out std_logic;
CFGVCTCVCMAP : out std_logic_vector(6 downto 0);
CFGBYTEENN : in std_logic_vector(3 downto 0);
CFGDI : in std_logic_vector(31 downto 0);
CFGDSBUSNUMBER : in std_logic_vector(7 downto 0);
CFGDSDEVICENUMBER : in std_logic_vector(4 downto 0);
CFGDSFUNCTIONNUMBER : in std_logic_vector(2 downto 0);
CFGDSN : in std_logic_vector(63 downto 0);
CFGDWADDR : in std_logic_vector(9 downto 0);
CFGERRACSN : in std_logic;
CFGERRAERHEADERLOG : in std_logic_vector(127 downto 0);
CFGERRCORN : in std_logic;
CFGERRCPLABORTN : in std_logic;
CFGERRCPLTIMEOUTN : in std_logic;
CFGERRCPLUNEXPECTN : in std_logic;
CFGERRECRCN : in std_logic;
CFGERRLOCKEDN : in std_logic;
CFGERRPOSTEDN : in std_logic;
CFGERRTLPCPLHEADER : in std_logic_vector(47 downto 0);
CFGERRURN : in std_logic;
CFGINTERRUPTASSERTN : in std_logic;
CFGINTERRUPTDI : in std_logic_vector(7 downto 0);
CFGINTERRUPTN : in std_logic;
CFGPMDIRECTASPML1N : in std_logic;
CFGPMSENDPMACKN : in std_logic;
CFGPMSENDPMETON : in std_logic;
CFGPMSENDPMNAKN : in std_logic;
CFGPMTURNOFFOKN : in std_logic;
CFGPMWAKEN : in std_logic;
CFGPORTNUMBER : in std_logic_vector(7 downto 0);
CFGRDENN : in std_logic;
CFGTRNPENDINGN : in std_logic;
CFGWRENN : in std_logic;
CFGWRREADONLYN : in std_logic;
CFGWRRW1CASRWN : in std_logic;
PLINITIALLINKWIDTH : out std_logic_vector(2 downto 0);
PLLANEREVERSALMODE : out std_logic_vector(1 downto 0);
PLLINKGEN2CAP : out std_logic;
PLLINKPARTNERGEN2SUPPORTED : out std_logic;
PLLINKUPCFGCAP : out std_logic;
PLLTSSMSTATE : out std_logic_vector(5 downto 0);
PLPHYLNKUPN : out std_logic;
PLRECEIVEDHOTRST : out std_logic;
PLRXPMSTATE : out std_logic_vector(1 downto 0);
PLSELLNKRATE : out std_logic;
PLSELLNKWIDTH : out std_logic_vector(1 downto 0);
PLTXPMSTATE : out std_logic_vector(2 downto 0);
PLDIRECTEDLINKAUTON : in std_logic;
PLDIRECTEDLINKCHANGE : in std_logic_vector(1 downto 0);
PLDIRECTEDLINKSPEED : in std_logic;
PLDIRECTEDLINKWIDTH : in std_logic_vector(1 downto 0);
PLDOWNSTREAMDEEMPHSOURCE : in std_logic;
PLUPSTREAMPREFERDEEMPH : in std_logic;
PLTRANSMITHOTRST : in std_logic;
DBGSCLRA : out std_logic;
DBGSCLRB : out std_logic;
DBGSCLRC : out std_logic;
DBGSCLRD : out std_logic;
DBGSCLRE : out std_logic;
DBGSCLRF : out std_logic;
DBGSCLRG : out std_logic;
DBGSCLRH : out std_logic;
DBGSCLRI : out std_logic;
DBGSCLRJ : out std_logic;
DBGSCLRK : out std_logic;
DBGVECA : out std_logic_vector(63 downto 0);
DBGVECB : out std_logic_vector(63 downto 0);
DBGVECC : out std_logic_vector(11 downto 0);
PLDBGVEC : out std_logic_vector(11 downto 0);
DBGMODE : in std_logic_vector(1 downto 0);
DBGSUBMODE : in std_logic;
PLDBGMODE : in std_logic_vector(2 downto 0);
PCIEDRPDO : out std_logic_vector(15 downto 0);
PCIEDRPDRDY : out std_logic;
PCIEDRPCLK : in std_logic;
PCIEDRPDADDR : in std_logic_vector(8 downto 0);
PCIEDRPDEN : in std_logic;
PCIEDRPDI : in std_logic_vector(15 downto 0);
PCIEDRPDWE : in std_logic;
GTPLLLOCK : out std_logic;
PIPECLK : in std_logic;
USERCLK : in std_logic;
DRPCLK : in std_logic;
CLOCKLOCKED : in std_logic;
TxOutClk : out std_logic);
end component;
FUNCTION to_integer (
val_in : bit_vector) RETURN integer IS
CONSTANT vctr : bit_vector(val_in'high-val_in'low DOWNTO 0) := val_in;
VARIABLE ret : integer := 0;
BEGIN
FOR index IN vctr'RANGE LOOP
IF (vctr(index) = '1') THEN
ret := ret + (2**index);
END IF;
END LOOP;
RETURN(ret);
END to_integer;
FUNCTION to_stdlogic (
in_val : IN boolean) RETURN std_logic IS
BEGIN
IF (in_val) THEN
RETURN('1');
ELSE
RETURN('0');
END IF;
END to_stdlogic;
function lp_lnk_bw_notif (
link_width : integer;
link_spd : integer)
return boolean is
begin -- lp_lnk_bw_notif
if ((link_width > 1) or (link_spd > 1)) then
return true;
else
return false;
end if;
end lp_lnk_bw_notif;
function pad_gen (
in_vec : bit_vector;
op_len : integer)
return bit_vector is
variable ret : bit_vector(op_len-1 downto 0) := (others => '0');
constant len : integer := in_vec'length; -- length of input vector
begin -- pad_gen
for i in 0 to op_len-1 loop
if (i < len) then
ret(i) := in_vec(len-i-1);
else
ret(i) := '0';
end if;
end loop; -- i
return ret;
end pad_gen;
constant LINK_CAP_MAX_LINK_SPEED_int : integer := to_integer(LINK_CAP_MAX_LINK_SPEED);
constant LP_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP : boolean := lp_lnk_bw_notif(LINK_CAP_MAX_LINK_WIDTH_int, LINK_CAP_MAX_LINK_SPEED_int);
constant LINK_STATUS_SLOT_CLOCK_CONFIG_lstatus : std_logic := to_stdlogic(LINK_STATUS_SLOT_CLOCK_CONFIG);
signal rx_func_level_reset_n : std_logic;
signal block_clk : std_logic;
signal cfg_cmd_bme : std_logic;
signal cfg_cmd_intdis : std_logic;
signal cfg_cmd_io_en : std_logic;
signal cfg_cmd_mem_en : std_logic;
signal cfg_cmd_serr_en : std_logic;
signal cfg_dev_control_aux_power_en : std_logic;
signal cfg_dev_control_corr_err_reporting_en : std_logic;
signal cfg_dev_control_enable_relaxed_order : std_logic;
signal cfg_dev_control_ext_tag_en : std_logic;
signal cfg_dev_control_fatal_err_reporting_en : std_logic;
signal cfg_dev_control_maxpayload : std_logic_vector(2 downto 0);
signal cfg_dev_control_max_read_req : std_logic_vector(2 downto 0);
signal cfg_dev_control_non_fatal_reporting_en : std_logic;
signal cfg_dev_control_nosnoop_en : std_logic;
signal cfg_dev_control_phantom_en : std_logic;
signal cfg_dev_control_ur_err_reporting_en : std_logic;
signal cfg_dev_control2_cpltimeout_dis : std_logic;
signal cfg_dev_control2_cpltimeout_val : std_logic_vector(3 downto 0);
signal cfg_dev_status_corr_err_detected : std_logic;
signal cfg_dev_status_fatal_err_detected : std_logic;
signal cfg_dev_status_nonfatal_err_detected : std_logic;
signal cfg_dev_status_ur_detected : std_logic;
signal cfg_link_control_auto_bandwidth_int_en : std_logic;
signal cfg_link_control_bandwidth_int_en : std_logic;
signal cfg_link_control_hw_auto_width_dis : std_logic;
signal cfg_link_control_clock_pm_en : std_logic;
signal cfg_link_control_extended_sync : std_logic;
signal cfg_link_control_common_clock : std_logic;
signal cfg_link_control_retrain_link : std_logic;
signal cfg_link_control_linkdisable : std_logic;
signal cfg_link_control_rcb : std_logic;
signal cfg_link_control_aspm_control : std_logic_vector(1 downto 0);
signal cfg_link_status_auto_bandwidth_status : std_logic;
signal cfg_link_status_bandwidth_status : std_logic;
signal cfg_link_status_dll_active : std_logic;
signal cfg_link_status_link_training : std_logic;
signal cfg_link_status_negotiated_link_width : std_logic_vector(3 downto 0);
signal cfg_link_status_current_speed : std_logic_vector(1 downto 0);
signal sys_reset_n_d : std_logic;
signal phy_rdy_n : std_logic;
signal trn_lnk_up_n_int : std_logic;
signal trn_lnk_up_n_int1 : std_logic;
signal trn_reset_n_int : std_logic;
signal trn_reset_n_int1 : std_logic;
signal TxOutClk : std_logic;
signal TxOutClk_bufg : std_logic;
signal gt_pll_lock : std_logic;
signal user_clk : std_logic;
signal drp_clk : std_logic;
signal clock_locked : std_logic;
-- X-HDL generated signals
signal v6pcie63 : std_logic;
signal v6pcie64 : std_logic;
signal v6pcie65 : std_logic;
signal v6pcie66 : std_logic;
signal v6pcie67 : std_logic;
signal v6pcie68 : std_logic_vector(1 downto 0);
signal v6pcie69 : std_logic;
signal func_lvl_rstn : std_logic;
signal cm_rstn : std_logic;
-- Declare intermediate signals for referenced outputs
signal pci_exp_txp_v6pcie28 : std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
signal pci_exp_txn_v6pcie27 : std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
signal trn_clk_v6pcie41 : std_logic;
signal trn_reset_n_v6pcie54 : std_logic;
signal trn_lnk_up_n_v6pcie48 : std_logic;
signal trn_tbuf_av_v6pcie59 : std_logic_vector(5 downto 0);
signal trn_tcfg_req_n_v6pcie60 : std_logic;
signal trn_terr_drop_n_v6pcie62 : std_logic;
signal trn_tdst_rdy_n_v6pcie61 : std_logic;
signal trn_rd_v6pcie50 : std_logic_vector(63 downto 0);
signal trn_rrem_n_v6pcie55 : std_logic;
signal trn_rsof_n_v6pcie56 : std_logic;
signal trn_reof_n_v6pcie52 : std_logic;
signal trn_rsrc_rdy_n_v6pcie58 : std_logic;
signal trn_rsrc_dsc_n_v6pcie57 : std_logic;
signal trn_rerrfwd_n_v6pcie53 : std_logic;
signal trn_rbar_hit_n_v6pcie49 : std_logic_vector(6 downto 0);
signal trn_recrc_err_n_v6pcie51 : std_logic;
signal trn_fc_cpld_v6pcie42 : std_logic_vector(11 downto 0);
signal trn_fc_cplh_v6pcie43 : std_logic_vector(7 downto 0);
signal trn_fc_npd_v6pcie44 : std_logic_vector(11 downto 0);
signal trn_fc_nph_v6pcie45 : std_logic_vector(7 downto 0);
signal trn_fc_pd_v6pcie46 : std_logic_vector(11 downto 0);
signal trn_fc_ph_v6pcie47 : std_logic_vector(7 downto 0);
signal cfg_err_cpl_rdy_n_v6pcie1 : std_logic;
signal cfg_interrupt_rdy_n_v6pcie7 : std_logic;
signal cfg_interrupt_do_v6pcie2 : std_logic_vector(7 downto 0);
signal cfg_interrupt_mmenable_v6pcie3 : std_logic_vector(2 downto 0);
signal cfg_interrupt_msienable_v6pcie4 : std_logic;
signal cfg_interrupt_msixenable_v6pcie5 : std_logic;
signal cfg_interrupt_msixfm_v6pcie6 : std_logic;
signal cfg_pcie_link_state_n_v6pcie22 : std_logic_vector(2 downto 0);
signal cfg_pmcsr_pme_en_v6pcie23 : std_logic;
signal cfg_pmcsr_pme_status_v6pcie24 : std_logic;
signal cfg_pmcsr_powerstate_v6pcie25 : std_logic_vector(1 downto 0);
signal cfg_msg_received_v6pcie9 : std_logic;
signal cfg_msg_data_v6pcie8 : std_logic_vector(15 downto 0);
signal cfg_msg_received_err_cor_v6pcie18 : std_logic;
signal cfg_msg_received_err_non_fatal_v6pcie20 : std_logic;
signal cfg_msg_received_err_fatal_v6pcie19 : std_logic;
signal cfg_msg_received_pme_to_ack_v6pcie21 : std_logic;
signal cfg_msg_received_assert_inta_v6pcie10 : std_logic;
signal cfg_msg_received_assert_intb_v6pcie11 : std_logic;
signal cfg_msg_received_assert_intc_v6pcie12 : std_logic;
signal cfg_msg_received_assert_intd_v6pcie13 : std_logic;
signal cfg_msg_received_deassert_inta_v6pcie14 : std_logic;
signal cfg_msg_received_deassert_intb_v6pcie15 : std_logic;
signal cfg_msg_received_deassert_intc_v6pcie16 : std_logic;
signal cfg_msg_received_deassert_intd_v6pcie17 : std_logic;
signal pipe_clk : std_logic;
signal pl_phy_lnk_up_n : std_logic;
signal pl_initial_link_width_v6pcie32 : std_logic_vector(2 downto 0);
signal pl_lane_reversal_mode_v6pcie33 : std_logic_vector(1 downto 0);
signal pl_link_gen2_capable_v6pcie34 : std_logic;
signal pl_link_partner_gen2_supported_v6pcie35 : std_logic;
signal pl_link_upcfg_capable_v6pcie36 : std_logic;
signal pl_ltssm_state_v6pcie37 : std_logic_vector(5 downto 0);
signal pl_sel_link_rate_v6pcie39 : std_logic;
signal pl_sel_link_width_v6pcie40 : std_logic_vector(1 downto 0);
signal pcie_drp_do_v6pcie29 : std_logic_vector(15 downto 0);
signal pcie_drp_drdy_v6pcie30 : std_logic;
begin
-- Drive referenced outputs
pci_exp_txp <= pci_exp_txp_v6pcie28;
pci_exp_txn <= pci_exp_txn_v6pcie27;
trn_clk <= trn_clk_v6pcie41;
trn_reset_n <= trn_reset_n_v6pcie54;
trn_lnk_up_n <= trn_lnk_up_n_v6pcie48;
trn_tbuf_av <= trn_tbuf_av_v6pcie59;
trn_tcfg_req_n <= trn_tcfg_req_n_v6pcie60;
trn_terr_drop_n <= trn_terr_drop_n_v6pcie62;
trn_tdst_rdy_n <= trn_tdst_rdy_n_v6pcie61;
trn_rd <= trn_rd_v6pcie50;
trn_rrem_n <= trn_rrem_n_v6pcie55;
trn_rsof_n <= trn_rsof_n_v6pcie56;
trn_reof_n <= trn_reof_n_v6pcie52;
trn_rsrc_rdy_n <= trn_rsrc_rdy_n_v6pcie58;
trn_rsrc_dsc_n <= trn_rsrc_dsc_n_v6pcie57;
trn_rerrfwd_n <= trn_rerrfwd_n_v6pcie53;
trn_rbar_hit_n <= trn_rbar_hit_n_v6pcie49;
trn_recrc_err_n <= trn_recrc_err_n_v6pcie51;
trn_fc_cpld <= trn_fc_cpld_v6pcie42;
trn_fc_cplh <= trn_fc_cplh_v6pcie43;
trn_fc_npd <= trn_fc_npd_v6pcie44;
trn_fc_nph <= trn_fc_nph_v6pcie45;
trn_fc_pd <= trn_fc_pd_v6pcie46;
trn_fc_ph <= trn_fc_ph_v6pcie47;
cfg_err_cpl_rdy_n <= cfg_err_cpl_rdy_n_v6pcie1;
cfg_interrupt_rdy_n <= cfg_interrupt_rdy_n_v6pcie7;
cfg_interrupt_do <= cfg_interrupt_do_v6pcie2;
cfg_interrupt_mmenable <= cfg_interrupt_mmenable_v6pcie3;
cfg_interrupt_msienable <= cfg_interrupt_msienable_v6pcie4;
cfg_interrupt_msixenable <= cfg_interrupt_msixenable_v6pcie5;
cfg_interrupt_msixfm <= cfg_interrupt_msixfm_v6pcie6;
cfg_pcie_link_state_n <= cfg_pcie_link_state_n_v6pcie22;
cfg_pmcsr_pme_en <= cfg_pmcsr_pme_en_v6pcie23;
cfg_pmcsr_pme_status <= cfg_pmcsr_pme_status_v6pcie24;
cfg_pmcsr_powerstate <= cfg_pmcsr_powerstate_v6pcie25;
cfg_msg_received <= cfg_msg_received_v6pcie9;
cfg_msg_data <= cfg_msg_data_v6pcie8;
cfg_msg_received_err_cor <= cfg_msg_received_err_cor_v6pcie18;
cfg_msg_received_err_non_fatal <= cfg_msg_received_err_non_fatal_v6pcie20;
cfg_msg_received_err_fatal <= cfg_msg_received_err_fatal_v6pcie19;
cfg_msg_received_pme_to_ack <= cfg_msg_received_pme_to_ack_v6pcie21;
cfg_msg_received_assert_inta <= cfg_msg_received_assert_inta_v6pcie10;
cfg_msg_received_assert_intb <= cfg_msg_received_assert_intb_v6pcie11;
cfg_msg_received_assert_intc <= cfg_msg_received_assert_intc_v6pcie12;
cfg_msg_received_assert_intd <= cfg_msg_received_assert_intd_v6pcie13;
cfg_msg_received_deassert_inta <= cfg_msg_received_deassert_inta_v6pcie14;
cfg_msg_received_deassert_intb <= cfg_msg_received_deassert_intb_v6pcie15;
cfg_msg_received_deassert_intc <= cfg_msg_received_deassert_intc_v6pcie16;
cfg_msg_received_deassert_intd <= cfg_msg_received_deassert_intd_v6pcie17;
pl_initial_link_width <= pl_initial_link_width_v6pcie32;
pl_lane_reversal_mode <= pl_lane_reversal_mode_v6pcie33;
pl_link_gen2_capable <= pl_link_gen2_capable_v6pcie34;
pl_link_partner_gen2_supported <= pl_link_partner_gen2_supported_v6pcie35;
pl_link_upcfg_capable <= pl_link_upcfg_capable_v6pcie36;
pl_ltssm_state <= pl_ltssm_state_v6pcie37;
pl_sel_link_rate <= pl_sel_link_rate_v6pcie39;
pl_sel_link_width <= pl_sel_link_width_v6pcie40;
pcie_drp_do <= pcie_drp_do_v6pcie29;
pcie_drp_drdy <= pcie_drp_drdy_v6pcie30;
-- assigns to outputs
cfg_status <= "0000000000000000";
cfg_command <= ("00000" &
cfg_cmd_intdis &
'0' &
cfg_cmd_serr_en &
"00000" &
cfg_cmd_bme &
cfg_cmd_mem_en &
cfg_cmd_io_en);
cfg_dstatus <= ("0000000000" &
cfg_trn_pending_n &
'0' &
cfg_dev_status_ur_detected &
cfg_dev_status_fatal_err_detected &
cfg_dev_status_nonfatal_err_detected &
cfg_dev_status_corr_err_detected);
cfg_dcommand <= ('0' &
cfg_dev_control_max_read_req &
cfg_dev_control_nosnoop_en &
cfg_dev_control_aux_power_en &
cfg_dev_control_phantom_en &
cfg_dev_control_ext_tag_en &
cfg_dev_control_maxpayload &
cfg_dev_control_enable_relaxed_order &
cfg_dev_control_ur_err_reporting_en &
cfg_dev_control_fatal_err_reporting_en &
cfg_dev_control_non_fatal_reporting_en &
cfg_dev_control_corr_err_reporting_en);
cfg_lstatus <= (cfg_link_status_auto_bandwidth_status &
cfg_link_status_bandwidth_status &
cfg_link_status_dll_active &
LINK_STATUS_SLOT_CLOCK_CONFIG_lstatus &
cfg_link_status_link_training &
'0' &
("00" & cfg_link_status_negotiated_link_width) &
("00" & cfg_link_status_current_speed));
cfg_lcommand <= ("0000" &
cfg_link_control_auto_bandwidth_int_en &
cfg_link_control_bandwidth_int_en &
cfg_link_control_hw_auto_width_dis &
cfg_link_control_clock_pm_en &
cfg_link_control_extended_sync &
cfg_link_control_common_clock &
cfg_link_control_retrain_link &
cfg_link_control_linkdisable &
cfg_link_control_rcb &
'0' &
cfg_link_control_aspm_control);
cfg_dcommand2 <= ("00000000000" &
cfg_dev_control2_cpltimeout_dis &
cfg_dev_control2_cpltimeout_val);
-- Generate trn_lnk_up_n
trn_lnk_up_n_i : FDCP
generic map (
INIT => '1'
)
port map (
Q => trn_lnk_up_n_v6pcie48,
D => trn_lnk_up_n_int1,
C => trn_clk_v6pcie41,
CLR => '0',
PRE => '0'
);
trn_lnk_up_n_int_i : FDCP
generic map (
INIT => '1'
)
port map (
Q => trn_lnk_up_n_int1,
D => trn_lnk_up_n_int,
C => trn_clk_v6pcie41,
CLR => '0',
PRE => '0'
);
-- Generate trn_reset_n
v6pcie63 <= trn_reset_n_int1 and not(phy_rdy_n);
v6pcie64 <= not(sys_reset_n_d);
-- Generate trn_reset_n
trn_reset_n_i : FDCP
generic map (
INIT => '0'
)
port map (
Q => trn_reset_n_v6pcie54,
D => v6pcie63,
C => trn_clk_v6pcie41,
CLR => v6pcie64,
PRE => '0'
);
v6pcie65 <= trn_reset_n_int and not(phy_rdy_n);
v6pcie66 <= not(sys_reset_n_d);
trn_reset_n_int_i : FDCP
generic map (
INIT => '0'
)
port map (
Q => trn_reset_n_int1,
D => v6pcie65,
C => trn_clk_v6pcie41,
CLR => v6pcie66,
PRE => '0'
);
---------------------------------------------------------
-- PCI Express Reset Delay Module
---------------------------------------------------------
pcie_reset_delay_i : pcie_reset_delay_v6
generic map (
PL_FAST_TRAIN => PL_FAST_TRAIN,
REF_CLK_FREQ => REF_CLK_FREQ
)
port map (
ref_clk => TxOutClk_bufg,
sys_reset_n => sys_reset_n,
delayed_sys_reset_n => sys_reset_n_d
);
---------------------------------------------------------
-- PCI Express Clocking Module
---------------------------------------------------------
pcie_clocking_i : pcie_clocking_v6
generic map (
IS_ENDPOINT => FALSE,
CAP_LINK_WIDTH => LINK_CAP_MAX_LINK_WIDTH_int,
CAP_LINK_SPEED => LINK_CAP_MAX_LINK_SPEED_int,
REF_CLK_FREQ => REF_CLK_FREQ,
USER_CLK_FREQ => USER_CLK_FREQ
)
port map (
sys_clk => TxOutClk,
gt_pll_lock => gt_pll_lock,
sel_lnk_rate => pl_sel_link_rate_v6pcie39,
sel_lnk_width => pl_sel_link_width_v6pcie40,
sys_clk_bufg => TxOutClk_bufg,
pipe_clk => pipe_clk,
user_clk => user_clk,
block_clk => open,
drp_clk => drp_clk,
clock_locked => clock_locked
);
---------------------------------------------------------
-- Virtex6 PCI Express Block Module
---------------------------------------------------------
v6pcie67 <= not(phy_rdy_n);
v6pcie68 <= pl_directed_link_change;
v6pcie69 <= pl_directed_link_speed;
func_lvl_rstn <= not(pl_transmit_hot_rst) when DS_PORT_HOT_RST else
'1';
cm_rstn <= not(pl_transmit_hot_rst) when DS_PORT_HOT_RST else
'1';
pcie_2_0_i : pcie_2_0_v6_rp
generic map (
REF_CLK_FREQ => REF_CLK_FREQ,
PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES,
LINK_CAP_MAX_LINK_WIDTH_int => LINK_CAP_MAX_LINK_WIDTH_int,
AER_BASE_PTR => AER_BASE_PTR,
AER_CAP_ECRC_CHECK_CAPABLE => AER_CAP_ECRC_CHECK_CAPABLE,
AER_CAP_ECRC_GEN_CAPABLE => AER_CAP_ECRC_GEN_CAPABLE,
AER_CAP_ID => AER_CAP_ID,
AER_CAP_INT_MSG_NUM_MSI => AER_CAP_INT_MSG_NUM_MSI,
AER_CAP_INT_MSG_NUM_MSIX => AER_CAP_INT_MSG_NUM_MSIX,
AER_CAP_NEXTPTR => AER_CAP_NEXTPTR,
AER_CAP_ON => AER_CAP_ON,
AER_CAP_PERMIT_ROOTERR_UPDATE => AER_CAP_PERMIT_ROOTERR_UPDATE,
AER_CAP_VERSION => AER_CAP_VERSION,
ALLOW_X8_GEN2 => ALLOW_X8_GEN2,
BAR0 => pad_gen(BAR0, 32),
BAR1 => pad_gen(BAR1, 32),
BAR2 => pad_gen(BAR2, 32),
BAR3 => pad_gen(BAR3, 32),
BAR4 => pad_gen(BAR4, 32),
BAR5 => pad_gen(BAR5, 32),
CAPABILITIES_PTR => CAPABILITIES_PTR,
CARDBUS_CIS_POINTER => pad_gen(CARDBUS_CIS_POINTER, 32),
CLASS_CODE => pad_gen(CLASS_CODE, 24),
CMD_INTX_IMPLEMENTED => CMD_INTX_IMPLEMENTED,
CPL_TIMEOUT_DISABLE_SUPPORTED => CPL_TIMEOUT_DISABLE_SUPPORTED,
CPL_TIMEOUT_RANGES_SUPPORTED => pad_gen(CPL_TIMEOUT_RANGES_SUPPORTED, 4),
CRM_MODULE_RSTS => CRM_MODULE_RSTS,
DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE => DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE,
DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE => DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE,
DEV_CAP_ENDPOINT_L0S_LATENCY => DEV_CAP_ENDPOINT_L0S_LATENCY,
DEV_CAP_ENDPOINT_L1_LATENCY => DEV_CAP_ENDPOINT_L1_LATENCY,
DEV_CAP_EXT_TAG_SUPPORTED => DEV_CAP_EXT_TAG_SUPPORTED,
DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE => DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE,
DEV_CAP_MAX_PAYLOAD_SUPPORTED => DEV_CAP_MAX_PAYLOAD_SUPPORTED,
DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT => DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT,
DEV_CAP_ROLE_BASED_ERROR => DEV_CAP_ROLE_BASED_ERROR,
DEV_CAP_RSVD_14_12 => DEV_CAP_RSVD_14_12,
DEV_CAP_RSVD_17_16 => DEV_CAP_RSVD_17_16,
DEV_CAP_RSVD_31_29 => DEV_CAP_RSVD_31_29,
DEV_CONTROL_AUX_POWER_SUPPORTED => DEV_CONTROL_AUX_POWER_SUPPORTED,
DEVICE_ID => pad_gen(DEVICE_ID, 16),
DISABLE_ASPM_L1_TIMER => DISABLE_ASPM_L1_TIMER,
DISABLE_BAR_FILTERING => DISABLE_BAR_FILTERING,
DISABLE_ID_CHECK => DISABLE_ID_CHECK,
DISABLE_LANE_REVERSAL => DISABLE_LANE_REVERSAL,
DISABLE_RX_TC_FILTER => DISABLE_RX_TC_FILTER,
DISABLE_SCRAMBLING => DISABLE_SCRAMBLING,
DNSTREAM_LINK_NUM => DNSTREAM_LINK_NUM,
DSN_BASE_PTR => pad_gen(DSN_BASE_PTR, 12),
DSN_CAP_ID => DSN_CAP_ID,
DSN_CAP_NEXTPTR => pad_gen(DSN_CAP_NEXTPTR, 12),
DSN_CAP_ON => DSN_CAP_ON,
DSN_CAP_VERSION => DSN_CAP_VERSION,
ENABLE_MSG_ROUTE => pad_gen(ENABLE_MSG_ROUTE, 11),
ENABLE_RX_TD_ECRC_TRIM => ENABLE_RX_TD_ECRC_TRIM,
ENTER_RVRY_EI_L0 => ENTER_RVRY_EI_L0,
EXPANSION_ROM => pad_gen(EXPANSION_ROM, 32),
EXT_CFG_CAP_PTR => EXT_CFG_CAP_PTR,
EXT_CFG_XP_CAP_PTR => pad_gen(EXT_CFG_XP_CAP_PTR, 10),
HEADER_TYPE => pad_gen(HEADER_TYPE, 8),
INFER_EI => INFER_EI,
INTERRUPT_PIN => pad_gen(INTERRUPT_PIN, 8),
IS_SWITCH => IS_SWITCH,
LAST_CONFIG_DWORD => LAST_CONFIG_DWORD,
LINK_CAP_ASPM_SUPPORT => LINK_CAP_ASPM_SUPPORT,
LINK_CAP_CLOCK_POWER_MANAGEMENT => LINK_CAP_CLOCK_POWER_MANAGEMENT,
LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP => LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP,
LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP => LP_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP,
LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 => LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1,
LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 => LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2,
LINK_CAP_L0S_EXIT_LATENCY_GEN1 => LINK_CAP_L0S_EXIT_LATENCY_GEN1,
LINK_CAP_L0S_EXIT_LATENCY_GEN2 => LINK_CAP_L0S_EXIT_LATENCY_GEN2,
LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 => LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1,
LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 => LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2,
LINK_CAP_L1_EXIT_LATENCY_GEN1 => LINK_CAP_L1_EXIT_LATENCY_GEN1,
LINK_CAP_L1_EXIT_LATENCY_GEN2 => LINK_CAP_L1_EXIT_LATENCY_GEN2,
LINK_CAP_MAX_LINK_SPEED => pad_gen(LINK_CAP_MAX_LINK_SPEED, 4),
LINK_CAP_MAX_LINK_WIDTH => pad_gen(LINK_CAP_MAX_LINK_WIDTH, 6),
LINK_CAP_RSVD_23_22 => LINK_CAP_RSVD_23_22,
LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE => LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE,
LINK_CONTROL_RCB => LINK_CONTROL_RCB,
LINK_CTRL2_DEEMPHASIS => LINK_CTRL2_DEEMPHASIS,
LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE => LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE,
LINK_CTRL2_TARGET_LINK_SPEED => pad_gen(LINK_CTRL2_TARGET_LINK_SPEED, 4),
LINK_STATUS_SLOT_CLOCK_CONFIG => LINK_STATUS_SLOT_CLOCK_CONFIG,
LL_ACK_TIMEOUT => pad_gen(LL_ACK_TIMEOUT, 15),
LL_ACK_TIMEOUT_EN => LL_ACK_TIMEOUT_EN,
LL_ACK_TIMEOUT_FUNC => LL_ACK_TIMEOUT_FUNC,
LL_REPLAY_TIMEOUT => pad_gen(LL_REPLAY_TIMEOUT, 15),
LL_REPLAY_TIMEOUT_EN => LL_REPLAY_TIMEOUT_EN,
LL_REPLAY_TIMEOUT_FUNC => LL_REPLAY_TIMEOUT_FUNC,
LTSSM_MAX_LINK_WIDTH => pad_gen(LTSSM_MAX_LINK_WIDTH, 6),
MSI_BASE_PTR => MSI_BASE_PTR,
MSI_CAP_ID => MSI_CAP_ID,
MSI_CAP_MULTIMSGCAP => MSI_CAP_MULTIMSGCAP,
MSI_CAP_MULTIMSG_EXTENSION => MSI_CAP_MULTIMSG_EXTENSION,
MSI_CAP_NEXTPTR => MSI_CAP_NEXTPTR,
MSI_CAP_ON => MSI_CAP_ON,
MSI_CAP_PER_VECTOR_MASKING_CAPABLE => MSI_CAP_PER_VECTOR_MASKING_CAPABLE,
MSI_CAP_64_BIT_ADDR_CAPABLE => MSI_CAP_64_BIT_ADDR_CAPABLE,
MSIX_BASE_PTR => MSIX_BASE_PTR,
MSIX_CAP_ID => MSIX_CAP_ID,
MSIX_CAP_NEXTPTR => MSIX_CAP_NEXTPTR,
MSIX_CAP_ON => MSIX_CAP_ON,
MSIX_CAP_PBA_BIR => MSIX_CAP_PBA_BIR,
MSIX_CAP_PBA_OFFSET => pad_gen(MSIX_CAP_PBA_OFFSET, 29),
MSIX_CAP_TABLE_BIR => MSIX_CAP_TABLE_BIR,
MSIX_CAP_TABLE_OFFSET => pad_gen(MSIX_CAP_TABLE_OFFSET, 29),
MSIX_CAP_TABLE_SIZE => pad_gen(MSIX_CAP_TABLE_SIZE, 11),
N_FTS_COMCLK_GEN1 => N_FTS_COMCLK_GEN1,
N_FTS_COMCLK_GEN2 => N_FTS_COMCLK_GEN2,
N_FTS_GEN1 => N_FTS_GEN1,
N_FTS_GEN2 => N_FTS_GEN2,
PCIE_BASE_PTR => PCIE_BASE_PTR,
PCIE_CAP_CAPABILITY_ID => PCIE_CAP_CAPABILITY_ID,
PCIE_CAP_CAPABILITY_VERSION => PCIE_CAP_CAPABILITY_VERSION,
PCIE_CAP_DEVICE_PORT_TYPE => pad_gen(PCIE_CAP_DEVICE_PORT_TYPE, 4),
PCIE_CAP_INT_MSG_NUM => pad_gen(PCIE_CAP_INT_MSG_NUM, 5),
PCIE_CAP_NEXTPTR => pad_gen(PCIE_CAP_NEXTPTR, 8),
PCIE_CAP_ON => PCIE_CAP_ON,
PCIE_CAP_RSVD_15_14 => PCIE_CAP_RSVD_15_14,
PCIE_CAP_SLOT_IMPLEMENTED => PCIE_CAP_SLOT_IMPLEMENTED,
PCIE_REVISION => PCIE_REVISION,
PGL0_LANE => PGL0_LANE,
PGL1_LANE => PGL1_LANE,
PGL2_LANE => PGL2_LANE,
PGL3_LANE => PGL3_LANE,
PGL4_LANE => PGL4_LANE,
PGL5_LANE => PGL5_LANE,
PGL6_LANE => PGL6_LANE,
PGL7_LANE => PGL7_LANE,
PL_AUTO_CONFIG => PL_AUTO_CONFIG,
PL_FAST_TRAIN => PL_FAST_TRAIN,
PM_BASE_PTR => PM_BASE_PTR,
PM_CAP_AUXCURRENT => PM_CAP_AUXCURRENT,
PM_CAP_DSI => PM_CAP_DSI,
PM_CAP_D1SUPPORT => PM_CAP_D1SUPPORT,
PM_CAP_D2SUPPORT => PM_CAP_D2SUPPORT,
PM_CAP_ID => PM_CAP_ID,
PM_CAP_NEXTPTR => PM_CAP_NEXTPTR,
PM_CAP_ON => PM_CAP_ON,
PM_CAP_PME_CLOCK => PM_CAP_PME_CLOCK,
PM_CAP_PMESUPPORT => pad_gen(PM_CAP_PMESUPPORT, 5),
PM_CAP_RSVD_04 => PM_CAP_RSVD_04,
PM_CAP_VERSION => PM_CAP_VERSION,
PM_CSR_BPCCEN => PM_CSR_BPCCEN,
PM_CSR_B2B3 => PM_CSR_B2B3,
PM_CSR_NOSOFTRST => PM_CSR_NOSOFTRST,
PM_DATA_SCALE0 => pad_gen(PM_DATA_SCALE0, 2),
PM_DATA_SCALE1 => pad_gen(PM_DATA_SCALE1, 2),
PM_DATA_SCALE2 => pad_gen(PM_DATA_SCALE2, 2),
PM_DATA_SCALE3 => pad_gen(PM_DATA_SCALE3, 2),
PM_DATA_SCALE4 => pad_gen(PM_DATA_SCALE4, 2),
PM_DATA_SCALE5 => pad_gen(PM_DATA_SCALE5, 2),
PM_DATA_SCALE6 => pad_gen(PM_DATA_SCALE6, 2),
PM_DATA_SCALE7 => pad_gen(PM_DATA_SCALE7, 2),
PM_DATA0 => pad_gen(PM_DATA0, 8),
PM_DATA1 => pad_gen(PM_DATA1, 8),
PM_DATA2 => pad_gen(PM_DATA2, 8),
PM_DATA3 => pad_gen(PM_DATA3, 8),
PM_DATA4 => pad_gen(PM_DATA4, 8),
PM_DATA5 => pad_gen(PM_DATA5, 8),
PM_DATA6 => pad_gen(PM_DATA6, 8),
PM_DATA7 => pad_gen(PM_DATA7, 8),
RECRC_CHK => RECRC_CHK,
RECRC_CHK_TRIM => RECRC_CHK_TRIM,
REVISION_ID => pad_gen(REVISION_ID, 8),
ROOT_CAP_CRS_SW_VISIBILITY => ROOT_CAP_CRS_SW_VISIBILITY,
SELECT_DLL_IF => SELECT_DLL_IF,
SLOT_CAP_ATT_BUTTON_PRESENT => SLOT_CAP_ATT_BUTTON_PRESENT,
SLOT_CAP_ATT_INDICATOR_PRESENT => SLOT_CAP_ATT_INDICATOR_PRESENT,
SLOT_CAP_ELEC_INTERLOCK_PRESENT => SLOT_CAP_ELEC_INTERLOCK_PRESENT,
SLOT_CAP_HOTPLUG_CAPABLE => SLOT_CAP_HOTPLUG_CAPABLE,
SLOT_CAP_HOTPLUG_SURPRISE => SLOT_CAP_HOTPLUG_SURPRISE,
SLOT_CAP_MRL_SENSOR_PRESENT => SLOT_CAP_MRL_SENSOR_PRESENT,
SLOT_CAP_NO_CMD_COMPLETED_SUPPORT => SLOT_CAP_NO_CMD_COMPLETED_SUPPORT,
SLOT_CAP_PHYSICAL_SLOT_NUM => SLOT_CAP_PHYSICAL_SLOT_NUM,
SLOT_CAP_POWER_CONTROLLER_PRESENT => SLOT_CAP_POWER_CONTROLLER_PRESENT,
SLOT_CAP_POWER_INDICATOR_PRESENT => SLOT_CAP_POWER_INDICATOR_PRESENT,
SLOT_CAP_SLOT_POWER_LIMIT_SCALE => SLOT_CAP_SLOT_POWER_LIMIT_SCALE,
SLOT_CAP_SLOT_POWER_LIMIT_VALUE => SLOT_CAP_SLOT_POWER_LIMIT_VALUE,
SPARE_BIT0 => SPARE_BIT0,
SPARE_BIT1 => SPARE_BIT1,
SPARE_BIT2 => SPARE_BIT2,
SPARE_BIT3 => SPARE_BIT3,
SPARE_BIT4 => SPARE_BIT4,
SPARE_BIT5 => SPARE_BIT5,
SPARE_BIT6 => SPARE_BIT6,
SPARE_BIT7 => SPARE_BIT7,
SPARE_BIT8 => SPARE_BIT8,
SPARE_BYTE0 => SPARE_BYTE0,
SPARE_BYTE1 => SPARE_BYTE1,
SPARE_BYTE2 => SPARE_BYTE2,
SPARE_BYTE3 => SPARE_BYTE3,
SPARE_WORD0 => SPARE_WORD0,
SPARE_WORD1 => SPARE_WORD1,
SPARE_WORD2 => SPARE_WORD2,
SPARE_WORD3 => SPARE_WORD3,
SUBSYSTEM_ID => pad_gen(SUBSYSTEM_ID, 16),
SUBSYSTEM_VENDOR_ID => pad_gen(SUBSYSTEM_VENDOR_ID, 16),
TL_RBYPASS => TL_RBYPASS,
TL_RX_RAM_RADDR_LATENCY => TL_RX_RAM_RADDR_LATENCY,
TL_RX_RAM_RDATA_LATENCY => TL_RX_RAM_RDATA_LATENCY,
TL_RX_RAM_WRITE_LATENCY => TL_RX_RAM_WRITE_LATENCY,
TL_TFC_DISABLE => TL_TFC_DISABLE,
TL_TX_CHECKS_DISABLE => TL_TX_CHECKS_DISABLE,
TL_TX_RAM_RADDR_LATENCY => TL_TX_RAM_RADDR_LATENCY,
TL_TX_RAM_RDATA_LATENCY => TL_TX_RAM_RDATA_LATENCY,
TL_TX_RAM_WRITE_LATENCY => TL_TX_RAM_WRITE_LATENCY,
UPCONFIG_CAPABLE => UPCONFIG_CAPABLE,
UPSTREAM_FACING => UPSTREAM_FACING,
EXIT_LOOPBACK_ON_EI => EXIT_LOOPBACK_ON_EI,
UR_INV_REQ => UR_INV_REQ,
USER_CLK_FREQ => USER_CLK_FREQ,
VC_BASE_PTR => pad_gen(VC_BASE_PTR, 12),
VC_CAP_ID => VC_CAP_ID,
VC_CAP_NEXTPTR => pad_gen(VC_CAP_NEXTPTR, 12),
VC_CAP_ON => VC_CAP_ON,
VC_CAP_REJECT_SNOOP_TRANSACTIONS => VC_CAP_REJECT_SNOOP_TRANSACTIONS,
VC_CAP_VERSION => VC_CAP_VERSION,
VC0_CPL_INFINITE => VC0_CPL_INFINITE,
VC0_RX_RAM_LIMIT => pad_gen(VC0_RX_RAM_LIMIT, 13),
VC0_TOTAL_CREDITS_CD => VC0_TOTAL_CREDITS_CD,
VC0_TOTAL_CREDITS_CH => VC0_TOTAL_CREDITS_CH,
VC0_TOTAL_CREDITS_NPH => VC0_TOTAL_CREDITS_NPH,
VC0_TOTAL_CREDITS_PD => VC0_TOTAL_CREDITS_PD,
VC0_TOTAL_CREDITS_PH => VC0_TOTAL_CREDITS_PH,
VC0_TX_LASTPACKET => VC0_TX_LASTPACKET,
VENDOR_ID => pad_gen(VENDOR_ID, 16),
VSEC_BASE_PTR => pad_gen(VSEC_BASE_PTR, 12),
VSEC_CAP_HDR_ID => VSEC_CAP_HDR_ID,
VSEC_CAP_HDR_LENGTH => VSEC_CAP_HDR_LENGTH,
VSEC_CAP_HDR_REVISION => VSEC_CAP_HDR_REVISION,
VSEC_CAP_ID => VSEC_CAP_ID,
VSEC_CAP_IS_LINK_VISIBLE => VSEC_CAP_IS_LINK_VISIBLE,
VSEC_CAP_NEXTPTR => pad_gen(VSEC_CAP_NEXTPTR, 12),
VSEC_CAP_ON => VSEC_CAP_ON,
VSEC_CAP_VERSION => VSEC_CAP_VERSION
)
port map (
PCIEXPRXN => pci_exp_rxn,
PCIEXPRXP => pci_exp_rxp,
PCIEXPTXN => pci_exp_txn_v6pcie27,
PCIEXPTXP => pci_exp_txp_v6pcie28,
SYSCLK => sys_clk,
TRNLNKUPN => trn_lnk_up_n_int,
TRNCLK => trn_clk_v6pcie41,
FUNDRSTN => sys_reset_n_d,
PHYRDYN => phy_rdy_n,
LNKCLKEN => open,
USERRSTN => trn_reset_n_int,
RECEIVEDFUNCLVLRSTN => rx_func_level_reset_n,
SYSRSTN => v6pcie67,
PLRSTN => '1',
DLRSTN => '1',
TLRSTN => '1',
FUNCLVLRSTN => func_lvl_rstn,
CMRSTN => cm_rstn,
CMSTICKYRSTN => '1',
TRNRBARHITN => trn_rbar_hit_n_v6pcie49,
TRNRD => trn_rd_v6pcie50,
TRNRECRCERRN => trn_recrc_err_n_v6pcie51,
TRNREOFN => trn_reof_n_v6pcie52,
TRNRERRFWDN => trn_rerrfwd_n_v6pcie53,
TRNRREMN => trn_rrem_n_v6pcie55,
TRNRSOFN => trn_rsof_n_v6pcie56,
TRNRSRCDSCN => trn_rsrc_dsc_n_v6pcie57,
TRNRSRCRDYN => trn_rsrc_rdy_n_v6pcie58,
TRNRDSTRDYN => trn_rdst_rdy_n,
TRNRNPOKN => trn_rnp_ok_n,
TRNTBUFAV => trn_tbuf_av_v6pcie59,
TRNTCFGREQN => trn_tcfg_req_n_v6pcie60,
TRNTDLLPDSTRDYN => open,
TRNTDSTRDYN => trn_tdst_rdy_n_v6pcie61,
TRNTERRDROPN => trn_terr_drop_n_v6pcie62,
TRNTCFGGNTN => trn_tcfg_gnt_n,
TRNTD => trn_td,
TRNTDLLPDATA => "00000000000000000000000000000000",
TRNTDLLPSRCRDYN => '1',
TRNTECRCGENN => '1',
TRNTEOFN => trn_teof_n,
TRNTERRFWDN => trn_terrfwd_n,
TRNTREMN => trn_trem_n,
TRNTSOFN => trn_tsof_n,
TRNTSRCDSCN => trn_tsrc_dsc_n,
TRNTSRCRDYN => trn_tsrc_rdy_n,
TRNTSTRN => trn_tstr_n,
TRNFCCPLD => trn_fc_cpld_v6pcie42,
TRNFCCPLH => trn_fc_cplh_v6pcie43,
TRNFCNPD => trn_fc_npd_v6pcie44,
TRNFCNPH => trn_fc_nph_v6pcie45,
TRNFCPD => trn_fc_pd_v6pcie46,
TRNFCPH => trn_fc_ph_v6pcie47,
TRNFCSEL => trn_fc_sel,
CFGAERECRCCHECKEN => open,
CFGAERECRCGENEN => open,
CFGCOMMANDBUSMASTERENABLE => cfg_cmd_bme,
CFGCOMMANDINTERRUPTDISABLE => cfg_cmd_intdis,
CFGCOMMANDIOENABLE => cfg_cmd_io_en,
CFGCOMMANDMEMENABLE => cfg_cmd_mem_en,
CFGCOMMANDSERREN => cfg_cmd_serr_en,
CFGDEVCONTROLAUXPOWEREN => cfg_dev_control_aux_power_en,
CFGDEVCONTROLCORRERRREPORTINGEN => cfg_dev_control_corr_err_reporting_en,
CFGDEVCONTROLENABLERO => cfg_dev_control_enable_relaxed_order,
CFGDEVCONTROLEXTTAGEN => cfg_dev_control_ext_tag_en,
CFGDEVCONTROLFATALERRREPORTINGEN => cfg_dev_control_fatal_err_reporting_en,
CFGDEVCONTROLMAXPAYLOAD => cfg_dev_control_maxpayload,
CFGDEVCONTROLMAXREADREQ => cfg_dev_control_max_read_req,
CFGDEVCONTROLNONFATALREPORTINGEN => cfg_dev_control_non_fatal_reporting_en,
CFGDEVCONTROLNOSNOOPEN => cfg_dev_control_nosnoop_en,
CFGDEVCONTROLPHANTOMEN => cfg_dev_control_phantom_en,
CFGDEVCONTROLURERRREPORTINGEN => cfg_dev_control_ur_err_reporting_en,
CFGDEVCONTROL2CPLTIMEOUTDIS => cfg_dev_control2_cpltimeout_dis,
CFGDEVCONTROL2CPLTIMEOUTVAL => cfg_dev_control2_cpltimeout_val,
CFGDEVSTATUSCORRERRDETECTED => cfg_dev_status_corr_err_detected,
CFGDEVSTATUSFATALERRDETECTED => cfg_dev_status_fatal_err_detected,
CFGDEVSTATUSNONFATALERRDETECTED => cfg_dev_status_nonfatal_err_detected,
CFGDEVSTATUSURDETECTED => cfg_dev_status_ur_detected,
CFGDO => cfg_do,
CFGERRAERHEADERLOGSETN => open,
CFGERRCPLRDYN => cfg_err_cpl_rdy_n_v6pcie1,
CFGINTERRUPTDO => cfg_interrupt_do_v6pcie2,
CFGINTERRUPTMMENABLE => cfg_interrupt_mmenable_v6pcie3,
CFGINTERRUPTMSIENABLE => cfg_interrupt_msienable_v6pcie4,
CFGINTERRUPTMSIXENABLE => cfg_interrupt_msixenable_v6pcie5,
CFGINTERRUPTMSIXFM => cfg_interrupt_msixfm_v6pcie6,
CFGINTERRUPTRDYN => cfg_interrupt_rdy_n_v6pcie7,
CFGLINKCONTROLRCB => cfg_link_control_rcb,
CFGLINKCONTROLASPMCONTROL => cfg_link_control_aspm_control,
CFGLINKCONTROLAUTOBANDWIDTHINTEN => cfg_link_control_auto_bandwidth_int_en,
CFGLINKCONTROLBANDWIDTHINTEN => cfg_link_control_bandwidth_int_en,
CFGLINKCONTROLCLOCKPMEN => cfg_link_control_clock_pm_en,
CFGLINKCONTROLCOMMONCLOCK => cfg_link_control_common_clock,
CFGLINKCONTROLEXTENDEDSYNC => cfg_link_control_extended_sync,
CFGLINKCONTROLHWAUTOWIDTHDIS => cfg_link_control_hw_auto_width_dis,
CFGLINKCONTROLLINKDISABLE => cfg_link_control_linkdisable,
CFGLINKCONTROLRETRAINLINK => cfg_link_control_retrain_link,
CFGLINKSTATUSAUTOBANDWIDTHSTATUS => cfg_link_status_auto_bandwidth_status,
CFGLINKSTATUSBANDWITHSTATUS => cfg_link_status_bandwidth_status,
CFGLINKSTATUSCURRENTSPEED => cfg_link_status_current_speed,
CFGLINKSTATUSDLLACTIVE => cfg_link_status_dll_active,
CFGLINKSTATUSLINKTRAINING => cfg_link_status_link_training,
CFGLINKSTATUSNEGOTIATEDWIDTH => cfg_link_status_negotiated_link_width,
CFGMSGDATA => cfg_msg_data_v6pcie8,
CFGMSGRECEIVED => cfg_msg_received_v6pcie9,
CFGMSGRECEIVEDASSERTINTA => cfg_msg_received_assert_inta_v6pcie10,
CFGMSGRECEIVEDASSERTINTB => cfg_msg_received_assert_intb_v6pcie11,
CFGMSGRECEIVEDASSERTINTC => cfg_msg_received_assert_intc_v6pcie12,
CFGMSGRECEIVEDASSERTINTD => cfg_msg_received_assert_intd_v6pcie13,
CFGMSGRECEIVEDDEASSERTINTA => cfg_msg_received_deassert_inta_v6pcie14,
CFGMSGRECEIVEDDEASSERTINTB => cfg_msg_received_deassert_intb_v6pcie15,
CFGMSGRECEIVEDDEASSERTINTC => cfg_msg_received_deassert_intc_v6pcie16,
CFGMSGRECEIVEDDEASSERTINTD => cfg_msg_received_deassert_intd_v6pcie17,
CFGMSGRECEIVEDERRCOR => cfg_msg_received_err_cor_v6pcie18,
CFGMSGRECEIVEDERRFATAL => cfg_msg_received_err_fatal_v6pcie19,
CFGMSGRECEIVEDERRNONFATAL => cfg_msg_received_err_non_fatal_v6pcie20,
CFGMSGRECEIVEDPMASNAK => open,
CFGMSGRECEIVEDPMETO => open,
CFGMSGRECEIVEDPMETOACK => cfg_msg_received_pme_to_ack_v6pcie21,
CFGMSGRECEIVEDPMPME => open,
CFGMSGRECEIVEDSETSLOTPOWERLIMIT => open,
CFGMSGRECEIVEDUNLOCK => open,
CFGPCIELINKSTATE => cfg_pcie_link_state_n_v6pcie22,
CFGPMRCVASREQL1N => open,
CFGPMRCVENTERL1N => open,
CFGPMRCVENTERL23N => open,
CFGPMRCVREQACKN => open,
CFGPMCSRPMEEN => cfg_pmcsr_pme_en_v6pcie23,
CFGPMCSRPMESTATUS => cfg_pmcsr_pme_status_v6pcie24,
CFGPMCSRPOWERSTATE => cfg_pmcsr_powerstate_v6pcie25,
CFGRDWRDONEN => cfg_rd_wr_done_n,
CFGSLOTCONTROLELECTROMECHILCTLPULSE => open,
CFGTRANSACTION => open,
CFGTRANSACTIONADDR => open,
CFGTRANSACTIONTYPE => open,
CFGVCTCVCMAP => open,
CFGBYTEENN => cfg_byte_en_n,
CFGDI => cfg_di,
CFGDSBUSNUMBER => cfg_ds_bus_number,
CFGDSDEVICENUMBER => cfg_ds_device_number,
CFGDSFUNCTIONNUMBER => "000",
CFGDSN => cfg_dsn,
CFGDWADDR => cfg_dwaddr,
CFGERRACSN => '1',
CFGERRAERHEADERLOG => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
CFGERRCORN => cfg_err_cor_n,
CFGERRCPLABORTN => cfg_err_cpl_abort_n,
CFGERRCPLTIMEOUTN => cfg_err_cpl_timeout_n,
CFGERRCPLUNEXPECTN => cfg_err_cpl_unexpect_n,
CFGERRECRCN => cfg_err_ecrc_n,
CFGERRLOCKEDN => cfg_err_locked_n,
CFGERRPOSTEDN => cfg_err_posted_n,
CFGERRTLPCPLHEADER => cfg_err_tlp_cpl_header,
CFGERRURN => cfg_err_ur_n,
CFGINTERRUPTASSERTN => cfg_interrupt_assert_n,
CFGINTERRUPTDI => cfg_interrupt_di,
CFGINTERRUPTN => cfg_interrupt_n,
CFGPMDIRECTASPML1N => '1',
CFGPMSENDPMACKN => '1',
CFGPMSENDPMETON => cfg_pm_send_pme_to_n,
CFGPMSENDPMNAKN => '1',
CFGPMTURNOFFOKN => '1',
CFGPMWAKEN => '1',
CFGPORTNUMBER => "00000000",
CFGRDENN => cfg_rd_en_n,
CFGTRNPENDINGN => cfg_trn_pending_n,
CFGWRENN => cfg_wr_en_n,
CFGWRREADONLYN => '1',
CFGWRRW1CASRWN => '1',
PLINITIALLINKWIDTH => pl_initial_link_width_v6pcie32,
PLLANEREVERSALMODE => pl_lane_reversal_mode_v6pcie33,
PLLINKGEN2CAP => pl_link_gen2_capable_v6pcie34,
PLLINKPARTNERGEN2SUPPORTED => pl_link_partner_gen2_supported_v6pcie35,
PLLINKUPCFGCAP => pl_link_upcfg_capable_v6pcie36,
PLLTSSMSTATE => pl_ltssm_state_v6pcie37,
PLPHYLNKUPN => pl_phy_lnk_up_n,
PLRECEIVEDHOTRST => open,
PLRXPMSTATE => open,
PLSELLNKRATE => pl_sel_link_rate_v6pcie39,
PLSELLNKWIDTH => pl_sel_link_width_v6pcie40,
PLTXPMSTATE => open,
PLDIRECTEDLINKAUTON => pl_directed_link_auton,
PLDIRECTEDLINKCHANGE => v6pcie68,
PLDIRECTEDLINKSPEED => v6pcie69,
PLDIRECTEDLINKWIDTH => pl_directed_link_width,
PLDOWNSTREAMDEEMPHSOURCE => '0',
PLUPSTREAMPREFERDEEMPH => pl_upstream_prefer_deemph,
PLTRANSMITHOTRST => pl_transmit_hot_rst,
DBGSCLRA => open,
DBGSCLRB => open,
DBGSCLRC => open,
DBGSCLRD => open,
DBGSCLRE => open,
DBGSCLRF => open,
DBGSCLRG => open,
DBGSCLRH => open,
DBGSCLRI => open,
DBGSCLRJ => open,
DBGSCLRK => open,
DBGVECA => open,
DBGVECB => open,
DBGVECC => open,
PLDBGVEC => open,
DBGMODE => "00",
DBGSUBMODE => '0',
PLDBGMODE => "000",
PCIEDRPDO => pcie_drp_do_v6pcie29,
PCIEDRPDRDY => pcie_drp_drdy_v6pcie30,
PCIEDRPCLK => pcie_drp_clk,
PCIEDRPDADDR => pcie_drp_daddr,
PCIEDRPDEN => pcie_drp_den,
PCIEDRPDI => pcie_drp_di,
PCIEDRPDWE => pcie_drp_dwe,
GTPLLLOCK => gt_pll_lock,
PIPECLK => pipe_clk,
USERCLK => user_clk,
DRPCLK => drp_clk,
CLOCKLOCKED => clock_locked,
TxOutClk => TxOutClk );
end v6_pcie;
| gpl-3.0 | b998ae3a475c16c6d5edb52f675a41e0 | 0.459875 | 3.991604 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/pcie_core/example_design/PIO.vhd | 1 | 7,327 | -------------------------------------------------------------------------------
--
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : PIO.vhd
-- Description: Programmed I/O module. Design implements 8 KBytes of
-- programmable memory space. Host processor can access this
-- memory space using Memory Read 32 and Memory Write 32 TLPs.
-- Design accepts 1 Double Word (DW) payload length on Memory
-- Write 32 TLP and responds to 1 DW length Memory Read 32 TLPs
-- with a Completion with Data TLP (1DW payload).
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity PIO is
port (
trn_clk : in std_logic;
trn_reset_n : in std_logic;
trn_lnk_up_n : in std_logic;
trn_td : out std_logic_vector(31 downto 0);
trn_tsof_n : out std_logic;
trn_teof_n : out std_logic;
trn_tsrc_rdy_n : out std_logic;
trn_tsrc_dsc_n : out std_logic;
trn_tdst_rdy_n : in std_logic;
trn_tdst_dsc_n : in std_logic;
trn_rd : in std_logic_vector(31 downto 0);
trn_rsof_n : in std_logic;
trn_reof_n : in std_logic;
trn_rsrc_rdy_n : in std_logic;
trn_rsrc_dsc_n : in std_logic;
trn_rbar_hit_n : in std_logic_vector(6 downto 0);
trn_rdst_rdy_n : out std_logic;
cfg_to_turnoff_n : in std_logic;
cfg_turnoff_ok_n : out std_logic;
cfg_completer_id : in std_logic_vector(15 downto 0);
cfg_bus_mstr_enable : in std_logic
);
end PIO;
architecture rtl of PIO is
-- Local signals
signal req_compl : std_logic;
signal compl_done : std_logic;
signal pio_reset_n : std_logic;
component PIO_EP
port (
clk : in std_logic;
rst_n : in std_logic;
-- LocalLink Tx
trn_td : out std_logic_vector(31 downto 0);
trn_tsof_n : out std_logic;
trn_teof_n : out std_logic;
trn_tsrc_dsc_n : out std_logic;
trn_tsrc_rdy_n : out std_logic;
trn_tdst_dsc_n : in std_logic;
trn_tdst_rdy_n : in std_logic;
-- LocalLink Rx
trn_rd : in std_logic_vector(31 downto 0);
trn_rsof_n : in std_logic;
trn_reof_n : in std_logic;
trn_rsrc_rdy_n : in std_logic;
trn_rsrc_dsc_n : in std_logic;
trn_rbar_hit_n : in std_logic_vector(6 downto 0);
trn_rdst_rdy_n : out std_logic;
req_compl_o : out std_logic;
compl_done_o : out std_logic;
cfg_completer_id : in std_logic_vector(15 downto 0);
cfg_bus_mstr_enable : in std_logic
);
end component;
component PIO_TO_CTRL
port (
clk : in std_logic;
rst_n : in std_logic;
req_compl_i : in std_logic;
compl_done_i : in std_logic;
cfg_to_turnoff_n : in std_logic;
cfg_turnoff_ok_n : out std_logic
);
end component;
begin
pio_reset_n <= trn_reset_n and not trn_lnk_up_n;
--
-- PIO instance
--
PIO_EP_i : PIO_EP
port map (
clk => trn_clk, -- I
rst_n => pio_reset_n, -- I
trn_td => trn_td, -- O [63/31:0]
trn_tsof_n => trn_tsof_n, -- O
trn_teof_n => trn_teof_n, -- O
trn_tsrc_rdy_n => trn_tsrc_rdy_n, -- O
trn_tsrc_dsc_n => trn_tsrc_dsc_n, -- O
trn_tdst_rdy_n => trn_tdst_rdy_n, -- I
trn_tdst_dsc_n => trn_tdst_dsc_n, -- I
trn_rd => trn_rd, -- I [63/31:0]
trn_rsof_n => trn_rsof_n, -- I
trn_reof_n => trn_reof_n, -- I
trn_rsrc_rdy_n => trn_rsrc_rdy_n, -- I
trn_rsrc_dsc_n => trn_rsrc_dsc_n, -- I
trn_rbar_hit_n => trn_rbar_hit_n, -- I
trn_rdst_rdy_n => trn_rdst_rdy_n, -- O
req_compl_o => req_compl, -- O
compl_done_o => compl_done, -- O
cfg_completer_id => cfg_completer_id, -- I [15:0]
cfg_bus_mstr_enable => cfg_bus_mstr_enable -- I
);
--
-- Turn-Off controller
--
PIO_TO : PIO_TO_CTRL
port map (
clk => trn_clk, -- I
rst_n => trn_reset_n, -- I
req_compl_i => req_compl, -- I
compl_done_i => compl_done, -- I
cfg_to_turnoff_n => cfg_to_turnoff_n, -- I
cfg_turnoff_ok_n => cfg_turnoff_ok_n -- O
);
end rtl; -- PIO
| gpl-3.0 | 75f1f7dda83a5f18f4bff49d6ef17999 | 0.544015 | 3.50742 | false | false | false | false |
Nixon-/VHDL_library | basic/nbit_full_adder.vhd | 2 | 683 | Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity nbit_full_adder is
generic(n: integer:=4);
port(
opA,opB: in std_logic_vector(n-1 downto 0);
carry_in: in std_logic_vector(0 downto 0);
carry_out: out std_logic;
sum: out std_logic_vector(n-1 downto 0)
);
end nbit_full_adder;
architecture primary of nbit_full_adder is
signal tempSum: std_logic_vector(n downto 0);
signal intSum: integer;
begin
intSum <= to_integer(unsigned(opA)) + to_integer(unsigned(opB)) + to_integer(unsigned(carry_in));
tempSum <= std_logic_vector(to_unsigned(intSum,n+1));
carry_out <= tempSum(n);
sum <= tempSum(n-1 downto 0);
end primary; | gpl-2.0 | 5763a7211626d7683b814be2131d219d | 0.686676 | 2.754032 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/pcie_core/simulation/dsport/gtx_drp_chanalign_fix_3752_v6.vhd | 1 | 9,229 | -------------------------------------------------------------------------------
--
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : gtx_drp_chanalign_fix_3752_v6.vhd
-- Description: Virtex6 Workaround for deadlock due lane-lane skew Bug
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity GTX_DRP_CHANALIGN_FIX_3752_V6 is
generic (
C_SIMULATION : integer := 0 -- Set to 1 for simulation
);
port (
dwe : out std_logic;
din : out std_logic_vector(15 downto 0); --THIS IS THE INPUT TO THE DRP
den : out std_logic;
daddr : out std_logic_vector(7 downto 0);
drpstate : out std_logic_vector(3 downto 0); --DEBUG
write_ts1 : in std_logic;
write_fts : in std_logic;
dout : in std_logic_vector(15 downto 0); --THIS IS THE OUTPUT OF THE DRP
drdy : in std_logic;
Reset_n : in std_logic;
drp_clk : in std_logic
);
end GTX_DRP_CHANALIGN_FIX_3752_V6;
architecture v6_pcie of GTX_DRP_CHANALIGN_FIX_3752_V6 is
constant TCQ : integer := 1;
constant DRP_IDLE_FTS : std_logic_vector(3 downto 0) := "0001";
constant DRP_IDLE_TS1 : std_logic_vector(3 downto 0) := "0010";
constant DRP_RESET : std_logic_vector(3 downto 0) := "0011";
constant DRP_WRITE_FTS : std_logic_vector(3 downto 0) := "0110";
constant DRP_WRITE_DONE_FTS : std_logic_vector(3 downto 0) := "0111";
constant DRP_WRITE_TS1 : std_logic_vector(3 downto 0) := "1000";
constant DRP_WRITE_DONE_TS1 : std_logic_vector(3 downto 0) := "1001";
constant DRP_COM : std_logic_vector(9 downto 0) := "0110111100";
constant DRP_FTS : std_logic_vector(9 downto 0) := "0100111100";
constant DRP_TS1 : std_logic_vector(9 downto 0) := "0001001010";
signal next_daddr : std_logic_vector(7 downto 0);
signal next_drpstate : std_logic_vector(3 downto 0);
signal write_ts1_gated : std_logic;
signal write_fts_gated : std_logic;
-- Declare intermediate signals for referenced outputs
signal daddr_v6pcie : std_logic_vector(7 downto 0);
signal drpstate_v6pcie : std_logic_vector(3 downto 0);
begin
-- Drive referenced outputs
daddr <= daddr_v6pcie;
drpstate <= drpstate_v6pcie;
process (drp_clk)
begin
if (drp_clk'event and drp_clk = '1') then
if ((not(Reset_n)) = '1') then
daddr_v6pcie <= X"08" after (TCQ)*1 ps;
drpstate_v6pcie <= DRP_RESET after (TCQ)*1 ps;
write_ts1_gated <= '0' after (TCQ)*1 ps;
write_fts_gated <= '0' after (TCQ)*1 ps;
else
daddr_v6pcie <= next_daddr after (TCQ)*1 ps;
drpstate_v6pcie <= next_drpstate after (TCQ)*1 ps;
write_ts1_gated <= write_ts1 after (TCQ)*1 ps;
write_fts_gated <= write_fts after (TCQ)*1 ps;
end if;
end if;
end process;
process (drpstate_v6pcie, daddr_v6pcie, drdy, write_ts1_gated, write_fts_gated)
begin
-- DEFAULT CONDITIONS
next_drpstate <= drpstate_v6pcie;
next_daddr <= daddr_v6pcie;
den <= '0';
din <= (others => '0');
dwe <= '0';
case drpstate_v6pcie is
-- RESET CONDITION, WE NEED TO READ THE TOP 6 BITS OF THE DRP REGISTER WHEN WE GET THE WRITE FTS TRIGGER
when DRP_RESET =>
next_drpstate <= DRP_WRITE_TS1;
next_daddr <= X"08";
-- WRITE FTS SEQUENCE
when DRP_WRITE_FTS =>
den <= '1';
dwe <= '1';
if (daddr_v6pcie = X"08") then
din <= X"FD3C";
elsif (daddr_v6pcie = X"09") then
din <= X"C53C";
elsif (daddr_v6pcie = X"0A") then
din <= X"FDBC";
elsif (daddr_v6pcie = X"0B") then
din <= X"853C";
end if;
next_drpstate <= DRP_WRITE_DONE_FTS;
-- WAIT FOR FTS SEQUENCE WRITE TO FINISH, ONCE WE FINISH ALL WRITES GO TO FTS IDLE
when DRP_WRITE_DONE_FTS =>
if (drdy = '1') then
if (daddr_v6pcie = X"0B") then
next_drpstate <= DRP_IDLE_FTS;
next_daddr <= X"08";
else
next_drpstate <= DRP_WRITE_FTS;
next_daddr <= daddr_v6pcie + X"01";
end if;
end if;
-- FTS IDLE: WAIT HERE UNTIL WE NEED TO WRITE TS1
when DRP_IDLE_FTS =>
if (write_ts1_gated = '1') then
next_drpstate <= DRP_WRITE_TS1;
next_daddr <= X"08";
end if;
-- WRITE TS1 SEQUENCE
when DRP_WRITE_TS1 =>
den <= '1';
dwe <= '1';
if (daddr_v6pcie = X"08") then
din <= X"FC4A";
elsif (daddr_v6pcie = X"09") then
din <= X"DC4A";
elsif (daddr_v6pcie = X"0A") then
din <= X"C04A";
elsif (daddr_v6pcie = X"0B") then
din <= X"85BC";
end if;
next_drpstate <= DRP_WRITE_DONE_TS1;
-- WAIT FOR TS1 SEQUENCE WRITE TO FINISH, ONCE WE FINISH ALL WRITES GO TO TS1 IDLE
when DRP_WRITE_DONE_TS1 =>
if (drdy = '1') then
if (daddr_v6pcie = X"0B") then
next_drpstate <= DRP_IDLE_TS1;
next_daddr <= X"08";
else
next_drpstate <= DRP_WRITE_TS1;
next_daddr <= daddr_v6pcie + X"01";
end if;
end if;
-- TS1 IDLE: WAIT HERE UNTIL WE NEED TO WRITE FTS
when DRP_IDLE_TS1 =>
if (write_fts_gated = '1') then
next_drpstate <= DRP_WRITE_FTS;
next_daddr <= X"08";
end if;
when others =>
next_drpstate <= DRP_RESET;
next_daddr <= X"00";
end case;
end process;
end v6_pcie;
| gpl-3.0 | 4e093e11e6b5d8fdf76b783558ad5dd2 | 0.521942 | 4.105427 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/pcie_core/source/gtpa1_dual_wrapper_tile.vhd | 1 | 45,319 | -------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 1.7
-- \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
-- / / Filename : gtpa1_dual_wrapper_tile.vhd
-- /___/ /\ Timestamp :
-- \ \ / \
-- \___\/\___\
--
--
-- Module GTPA1_DUAL_WRAPPER_TILE (a GTPA1_DUAL Tile Wrapper)
-- Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
--
--
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
--***************************** Entity Declaration ****************************
entity GTPA1_DUAL_WRAPPER_TILE is
generic
(
-- Simulation attributes
TILE_SIM_GTPRESET_SPEEDUP : integer := 0; -- Set to 1 to speed up sim reset
TILE_CLK25_DIVIDER_0 : integer := 4;
TILE_CLK25_DIVIDER_1 : integer := 4;
TILE_PLL_DIVSEL_FB_0 : integer := 5;
TILE_PLL_DIVSEL_FB_1 : integer := 5;
TILE_PLL_DIVSEL_REF_0 : integer := 2;
TILE_PLL_DIVSEL_REF_1 : integer := 2;
--
TILE_PLL_SOURCE_0 : string := "PLL0";
TILE_PLL_SOURCE_1 : string := "PLL1"
);
port
(
------------------------ Loopback and Powerdown Ports ----------------------
RXPOWERDOWN0_IN : in std_logic_vector(1 downto 0);
RXPOWERDOWN1_IN : in std_logic_vector(1 downto 0);
TXPOWERDOWN0_IN : in std_logic_vector(1 downto 0);
TXPOWERDOWN1_IN : in std_logic_vector(1 downto 0);
--------------------------------- PLL Ports --------------------------------
CLK00_IN : in std_logic;
CLK01_IN : in std_logic;
GTPRESET0_IN : in std_logic;
GTPRESET1_IN : in std_logic;
PLLLKDET0_OUT : out std_logic;
PLLLKDET1_OUT : out std_logic;
RESETDONE0_OUT : out std_logic;
RESETDONE1_OUT : out std_logic;
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISK0_OUT : out std_logic_vector(1 downto 0);
RXCHARISK1_OUT : out std_logic_vector(1 downto 0);
RXDISPERR0_OUT : out std_logic_vector(1 downto 0);
RXDISPERR1_OUT : out std_logic_vector(1 downto 0);
RXNOTINTABLE0_OUT : out std_logic_vector(1 downto 0);
RXNOTINTABLE1_OUT : out std_logic_vector(1 downto 0);
---------------------- Receive Ports - Clock Correction --------------------
RXCLKCORCNT0_OUT : out std_logic_vector(2 downto 0);
RXCLKCORCNT1_OUT : out std_logic_vector(2 downto 0);
--------------- Receive Ports - Comma Detection and Alignment --------------
RXENMCOMMAALIGN0_IN : in std_logic;
RXENMCOMMAALIGN1_IN : in std_logic;
RXENPCOMMAALIGN0_IN : in std_logic;
RXENPCOMMAALIGN1_IN : in std_logic;
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA0_OUT : out std_logic_vector(15 downto 0);
RXDATA1_OUT : out std_logic_vector(15 downto 0);
RXRESET0_IN : in std_logic;
RXRESET1_IN : in std_logic;
RXUSRCLK0_IN : in std_logic;
RXUSRCLK1_IN : in std_logic;
RXUSRCLK20_IN : in std_logic;
RXUSRCLK21_IN : in std_logic;
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
GATERXELECIDLE0_IN : in std_logic;
GATERXELECIDLE1_IN : in std_logic;
IGNORESIGDET0_IN : in std_logic;
IGNORESIGDET1_IN : in std_logic;
RXELECIDLE0_OUT : out std_logic;
RXELECIDLE1_OUT : out std_logic;
RXN0_IN : in std_logic;
RXN1_IN : in std_logic;
RXP0_IN : in std_logic;
RXP1_IN : in std_logic;
----------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------
RXSTATUS0_OUT : out std_logic_vector(2 downto 0);
RXSTATUS1_OUT : out std_logic_vector(2 downto 0);
-------------- Receive Ports - RX Pipe Control for PCI Express -------------
PHYSTATUS0_OUT : out std_logic;
PHYSTATUS1_OUT : out std_logic;
RXVALID0_OUT : out std_logic;
RXVALID1_OUT : out std_logic;
-------------------- Receive Ports - RX Polarity Control -------------------
RXPOLARITY0_IN : in std_logic;
RXPOLARITY1_IN : in std_logic;
---------------------------- TX/RX Datapath Ports --------------------------
GTPCLKOUT0_OUT : out std_logic_vector(1 downto 0);
GTPCLKOUT1_OUT : out std_logic_vector(1 downto 0);
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TXCHARDISPMODE0_IN : in std_logic_vector(1 downto 0);
TXCHARDISPMODE1_IN : in std_logic_vector(1 downto 0);
TXCHARISK0_IN : in std_logic_vector(1 downto 0);
TXCHARISK1_IN : in std_logic_vector(1 downto 0);
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA0_IN : in std_logic_vector(15 downto 0);
TXDATA1_IN : in std_logic_vector(15 downto 0);
TXUSRCLK0_IN : in std_logic;
TXUSRCLK1_IN : in std_logic;
TXUSRCLK20_IN : in std_logic;
TXUSRCLK21_IN : in std_logic;
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXN0_OUT : out std_logic;
TXN1_OUT : out std_logic;
TXP0_OUT : out std_logic;
TXP1_OUT : out std_logic;
----------------- Transmit Ports - TX Ports for PCI Express ----------------
TXDETECTRX0_IN : in std_logic;
TXDETECTRX1_IN : in std_logic;
TXELECIDLE0_IN : in std_logic;
TXELECIDLE1_IN : in std_logic
);
end GTPA1_DUAL_WRAPPER_TILE;
architecture RTL of GTPA1_DUAL_WRAPPER_TILE is
--**************************** Signal Declarations ****************************
-- ground and tied_to_vcc_i signals
signal tied_to_ground_i : std_logic;
signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
signal tied_to_vcc_i : std_logic;
signal tied_to_vcc_vec_i : std_logic_vector(63 downto 0);
-- RX Datapath signals
signal rxdata0_i : std_logic_vector(31 downto 0);
signal rxchariscomma0_float_i : std_logic_vector(1 downto 0);
signal rxcharisk0_float_i : std_logic_vector(1 downto 0);
signal rxdisperr0_float_i : std_logic_vector(1 downto 0);
signal rxnotintable0_float_i : std_logic_vector(1 downto 0);
signal rxrundisp0_float_i : std_logic_vector(1 downto 0);
-- TX Datapath signals
signal txdata0_i : std_logic_vector(31 downto 0);
signal txkerr0_float_i : std_logic_vector(1 downto 0);
signal txrundisp0_float_i : std_logic_vector(1 downto 0);
-- RX Datapath signals
signal rxdata1_i : std_logic_vector(31 downto 0);
signal rxchariscomma1_float_i : std_logic_vector(1 downto 0);
signal rxcharisk1_float_i : std_logic_vector(1 downto 0);
signal rxdisperr1_float_i : std_logic_vector(1 downto 0);
signal rxnotintable1_float_i : std_logic_vector(1 downto 0);
signal rxrundisp1_float_i : std_logic_vector(1 downto 0);
-- TX Datapath signals
signal txdata1_i : std_logic_vector(31 downto 0);
signal txkerr1_float_i : std_logic_vector(1 downto 0);
signal txrundisp1_float_i : std_logic_vector(1 downto 0);
--******************************** Main Body of Code***************************
begin
--------------------------- Static signal Assignments ---------------------
tied_to_ground_i <= '0';
tied_to_ground_vec_i(63 downto 0) <= (others => '0');
tied_to_vcc_i <= '1';
tied_to_vcc_vec_i(63 downto 0) <= (others => '1');
------------------- GTP Datapath byte mapping -----------------
-- The GTP provides little endian data (first byte received on RXDATA(7 downto 0))
RXDATA0_OUT <= rxdata0_i(15 downto 0);
txdata0_i <= (tied_to_ground_vec_i(15 downto 0) & TXDATA0_IN);
-- The GTP provides little endian data (first byte received on RXDATA(7 downto 0))
RXDATA1_OUT <= rxdata1_i(15 downto 0);
txdata1_i <= (tied_to_ground_vec_i(15 downto 0) & TXDATA1_IN);
----------------------------- GTPA1_DUAL Instance --------------------------
gtpa1_dual_i:GTPA1_DUAL
generic map
(
--_______________________ Simulation-Only Attributes ___________________
SIM_RECEIVER_DETECT_PASS => (TRUE),
SIM_TX_ELEC_IDLE_LEVEL => ("Z"),
SIM_VERSION => ("2.0"),
SIM_REFCLK0_SOURCE => ("000"),
SIM_REFCLK1_SOURCE => ("000"),
SIM_GTPRESET_SPEEDUP => (TILE_SIM_GTPRESET_SPEEDUP),
CLK25_DIVIDER_0 => (TILE_CLK25_DIVIDER_0),
CLK25_DIVIDER_1 => (TILE_CLK25_DIVIDER_1),
PLL_DIVSEL_FB_0 => (TILE_PLL_DIVSEL_FB_0),
PLL_DIVSEL_FB_1 => (TILE_PLL_DIVSEL_FB_1),
PLL_DIVSEL_REF_0 => (TILE_PLL_DIVSEL_REF_0),
PLL_DIVSEL_REF_1 => (TILE_PLL_DIVSEL_REF_1),
--PLL Attributes
CLKINDC_B_0 => (TRUE),
CLKRCV_TRST_0 => (TRUE),
OOB_CLK_DIVIDER_0 => (4),
PLL_COM_CFG_0 => (x"21680a"),
PLL_CP_CFG_0 => (x"00"),
PLL_RXDIVSEL_OUT_0 => (1),
PLL_SATA_0 => (FALSE),
PLL_SOURCE_0 => (TILE_PLL_SOURCE_0),
PLL_TXDIVSEL_OUT_0 => (1),
PLLLKDET_CFG_0 => ("111"),
--
CLKINDC_B_1 => (TRUE),
CLKRCV_TRST_1 => (TRUE),
OOB_CLK_DIVIDER_1 => (4),
PLL_COM_CFG_1 => (x"21680a"),
PLL_CP_CFG_1 => (x"00"),
PLL_RXDIVSEL_OUT_1 => (1),
PLL_SATA_1 => (FALSE),
PLL_SOURCE_1 => (TILE_PLL_SOURCE_1),
PLL_TXDIVSEL_OUT_1 => (1),
PLLLKDET_CFG_1 => ("111"),
PMA_COM_CFG_EAST => (x"000008000"),
PMA_COM_CFG_WEST => (x"00000a000"),
TST_ATTR_0 => (x"00000000"),
TST_ATTR_1 => (x"00000000"),
--TX Interface Attributes
CLK_OUT_GTP_SEL_0 => ("REFCLKPLL0"),
TX_TDCC_CFG_0 => ("11"),
CLK_OUT_GTP_SEL_1 => ("REFCLKPLL1"),
TX_TDCC_CFG_1 => ("11"),
--TX Buffer and Phase Alignment Attributes
PMA_TX_CFG_0 => (x"00082"),
TX_BUFFER_USE_0 => (TRUE),
TX_XCLK_SEL_0 => ("TXOUT"),
TXRX_INVERT_0 => ("011"),
PMA_TX_CFG_1 => (x"00082"),
TX_BUFFER_USE_1 => (TRUE),
TX_XCLK_SEL_1 => ("TXOUT"),
TXRX_INVERT_1 => ("011"),
--TX Driver and OOB signalling Attributes
CM_TRIM_0 => ("00"),
TX_IDLE_DELAY_0 => ("010"),
CM_TRIM_1 => ("00"),
TX_IDLE_DELAY_1 => ("010"),
--TX PIPE/SATA Attributes
COM_BURST_VAL_0 => ("1111"),
COM_BURST_VAL_1 => ("1111"),
--RX Driver,OOB signalling,Coupling and Eq,CDR Attributes
AC_CAP_DIS_0 => (FALSE),
OOBDETECT_THRESHOLD_0 => ("111"),
PMA_CDR_SCAN_0 => (x"6404040"),
PMA_RX_CFG_0 => (x"05ce089"),
PMA_RXSYNC_CFG_0 => (x"00"),
RCV_TERM_GND_0 => (TRUE),
RCV_TERM_VTTRX_0 => (FALSE),
RXEQ_CFG_0 => ("01111011"),
TERMINATION_CTRL_0 => ("10100"),
TERMINATION_OVRD_0 => (FALSE),
TX_DETECT_RX_CFG_0 => (x"1832"),
AC_CAP_DIS_1 => (FALSE),
OOBDETECT_THRESHOLD_1 => ("111"),
PMA_CDR_SCAN_1 => (x"6404040"),
PMA_RX_CFG_1 => (x"05ce089"),
PMA_RXSYNC_CFG_1 => (x"00"),
RCV_TERM_GND_1 => (TRUE),
RCV_TERM_VTTRX_1 => (FALSE),
RXEQ_CFG_1 => ("01111011"),
TERMINATION_CTRL_1 => ("10100"),
TERMINATION_OVRD_1 => (FALSE),
TX_DETECT_RX_CFG_1 => (x"1832"),
--PRBS Detection Attributes
RXPRBSERR_LOOPBACK_0 => ('0'),
RXPRBSERR_LOOPBACK_1 => ('0'),
--Comma Detection and Alignment Attributes
ALIGN_COMMA_WORD_0 => (1),
COMMA_10B_ENABLE_0 => ("1111111111"),
DEC_MCOMMA_DETECT_0 => (TRUE),
DEC_PCOMMA_DETECT_0 => (TRUE),
DEC_VALID_COMMA_ONLY_0 => (TRUE),
MCOMMA_10B_VALUE_0 => ("1010000011"),
MCOMMA_DETECT_0 => (TRUE),
PCOMMA_10B_VALUE_0 => ("0101111100"),
PCOMMA_DETECT_0 => (TRUE),
RX_SLIDE_MODE_0 => ("PCS"),
ALIGN_COMMA_WORD_1 => (1),
COMMA_10B_ENABLE_1 => ("1111111111"),
DEC_MCOMMA_DETECT_1 => (TRUE),
DEC_PCOMMA_DETECT_1 => (TRUE),
DEC_VALID_COMMA_ONLY_1 => (TRUE),
MCOMMA_10B_VALUE_1 => ("1010000011"),
MCOMMA_DETECT_1 => (TRUE),
PCOMMA_10B_VALUE_1 => ("0101111100"),
PCOMMA_DETECT_1 => (TRUE),
RX_SLIDE_MODE_1 => ("PCS"),
--RX Loss-of-sync State Machine Attributes
RX_LOS_INVALID_INCR_0 => (8),
RX_LOS_THRESHOLD_0 => (128),
RX_LOSS_OF_SYNC_FSM_0 => (FALSE),
RX_LOS_INVALID_INCR_1 => (8),
RX_LOS_THRESHOLD_1 => (128),
RX_LOSS_OF_SYNC_FSM_1 => (FALSE),
--RX Elastic Buffer and Phase alignment Attributes
RX_BUFFER_USE_0 => (TRUE),
RX_EN_IDLE_RESET_BUF_0 => (TRUE),
RX_IDLE_HI_CNT_0 => ("1000"),
RX_IDLE_LO_CNT_0 => ("0000"),
RX_XCLK_SEL_0 => ("RXREC"),
RX_BUFFER_USE_1 => (TRUE),
RX_EN_IDLE_RESET_BUF_1 => (TRUE),
RX_IDLE_HI_CNT_1 => ("1000"),
RX_IDLE_LO_CNT_1 => ("0000"),
RX_XCLK_SEL_1 => ("RXREC"),
--Clock Correction Attributes
CLK_COR_ADJ_LEN_0 => (1),
CLK_COR_DET_LEN_0 => (1),
CLK_COR_INSERT_IDLE_FLAG_0 => (FALSE),
CLK_COR_KEEP_IDLE_0 => (FALSE),
CLK_COR_MAX_LAT_0 => (20),
CLK_COR_MIN_LAT_0 => (18),
CLK_COR_PRECEDENCE_0 => (TRUE),
CLK_COR_REPEAT_WAIT_0 => (0),
CLK_COR_SEQ_1_1_0 => ("0100011100"),
CLK_COR_SEQ_1_2_0 => ("0000000000"),
CLK_COR_SEQ_1_3_0 => ("0000000000"),
CLK_COR_SEQ_1_4_0 => ("0000000000"),
CLK_COR_SEQ_1_ENABLE_0 => ("0001"),
CLK_COR_SEQ_2_1_0 => ("0000000000"),
CLK_COR_SEQ_2_2_0 => ("0000000000"),
CLK_COR_SEQ_2_3_0 => ("0000000000"),
CLK_COR_SEQ_2_4_0 => ("0000000000"),
CLK_COR_SEQ_2_ENABLE_0 => ("0000"),
CLK_COR_SEQ_2_USE_0 => (FALSE),
CLK_CORRECT_USE_0 => (TRUE),
RX_DECODE_SEQ_MATCH_0 => (TRUE),
CLK_COR_ADJ_LEN_1 => (1),
CLK_COR_DET_LEN_1 => (1),
CLK_COR_INSERT_IDLE_FLAG_1 => (FALSE),
CLK_COR_KEEP_IDLE_1 => (FALSE),
CLK_COR_MAX_LAT_1 => (20),
CLK_COR_MIN_LAT_1 => (18),
CLK_COR_PRECEDENCE_1 => (TRUE),
CLK_COR_REPEAT_WAIT_1 => (0),
CLK_COR_SEQ_1_1_1 => ("0100011100"),
CLK_COR_SEQ_1_2_1 => ("0000000000"),
CLK_COR_SEQ_1_3_1 => ("0000000000"),
CLK_COR_SEQ_1_4_1 => ("0000000000"),
CLK_COR_SEQ_1_ENABLE_1 => ("0001"),
CLK_COR_SEQ_2_1_1 => ("0000000000"),
CLK_COR_SEQ_2_2_1 => ("0000000000"),
CLK_COR_SEQ_2_3_1 => ("0000000000"),
CLK_COR_SEQ_2_4_1 => ("0000000000"),
CLK_COR_SEQ_2_ENABLE_1 => ("0000"),
CLK_COR_SEQ_2_USE_1 => (FALSE),
CLK_CORRECT_USE_1 => (TRUE),
RX_DECODE_SEQ_MATCH_1 => (TRUE),
--Channel Bonding Attributes
CHAN_BOND_1_MAX_SKEW_0 => (1),
CHAN_BOND_2_MAX_SKEW_0 => (1),
CHAN_BOND_KEEP_ALIGN_0 => (FALSE),
CHAN_BOND_SEQ_1_1_0 => ("0001001010"),
CHAN_BOND_SEQ_1_2_0 => ("0001001010"),
CHAN_BOND_SEQ_1_3_0 => ("0001001010"),
CHAN_BOND_SEQ_1_4_0 => ("0110111100"),
CHAN_BOND_SEQ_1_ENABLE_0 => ("0000"),
CHAN_BOND_SEQ_2_1_0 => ("0100111100"),
CHAN_BOND_SEQ_2_2_0 => ("0100111100"),
CHAN_BOND_SEQ_2_3_0 => ("0110111100"),
CHAN_BOND_SEQ_2_4_0 => ("0100011100"),
CHAN_BOND_SEQ_2_ENABLE_0 => ("0000"),
CHAN_BOND_SEQ_2_USE_0 => (FALSE),
CHAN_BOND_SEQ_LEN_0 => (1),
RX_EN_MODE_RESET_BUF_0 => (TRUE),
CHAN_BOND_1_MAX_SKEW_1 => (1),
CHAN_BOND_2_MAX_SKEW_1 => (1),
CHAN_BOND_KEEP_ALIGN_1 => (FALSE),
CHAN_BOND_SEQ_1_1_1 => ("0001001010"),
CHAN_BOND_SEQ_1_2_1 => ("0001001010"),
CHAN_BOND_SEQ_1_3_1 => ("0001001010"),
CHAN_BOND_SEQ_1_4_1 => ("0110111100"),
CHAN_BOND_SEQ_1_ENABLE_1 => ("0000"),
CHAN_BOND_SEQ_2_1_1 => ("0100111100"),
CHAN_BOND_SEQ_2_2_1 => ("0100111100"),
CHAN_BOND_SEQ_2_3_1 => ("0110111100"),
CHAN_BOND_SEQ_2_4_1 => ("0100011100"),
CHAN_BOND_SEQ_2_ENABLE_1 => ("0000"),
CHAN_BOND_SEQ_2_USE_1 => (FALSE),
CHAN_BOND_SEQ_LEN_1 => (1),
RX_EN_MODE_RESET_BUF_1 => (TRUE),
--RX PCI Express Attributes
CB2_INH_CC_PERIOD_0 => (8),
CDR_PH_ADJ_TIME_0 => ("01010"),
PCI_EXPRESS_MODE_0 => (TRUE),
RX_EN_IDLE_HOLD_CDR_0 => (TRUE),
RX_EN_IDLE_RESET_FR_0 => (TRUE),
RX_EN_IDLE_RESET_PH_0 => (TRUE),
RX_STATUS_FMT_0 => ("PCIE"),
TRANS_TIME_FROM_P2_0 => (x"03c"),
TRANS_TIME_NON_P2_0 => (x"19"),
TRANS_TIME_TO_P2_0 => (x"064"),
CB2_INH_CC_PERIOD_1 => (8),
CDR_PH_ADJ_TIME_1 => ("01010"),
PCI_EXPRESS_MODE_1 => (TRUE),
RX_EN_IDLE_HOLD_CDR_1 => (TRUE),
RX_EN_IDLE_RESET_FR_1 => (TRUE),
RX_EN_IDLE_RESET_PH_1 => (TRUE),
RX_STATUS_FMT_1 => ("PCIE"),
TRANS_TIME_FROM_P2_1 => (x"03c"),
TRANS_TIME_NON_P2_1 => (x"19"),
TRANS_TIME_TO_P2_1 => (x"064"),
--RX SATA Attributes
SATA_BURST_VAL_0 => ("100"),
SATA_IDLE_VAL_0 => ("100"),
SATA_MAX_BURST_0 => (7),
SATA_MAX_INIT_0 => (22),
SATA_MAX_WAKE_0 => (7),
SATA_MIN_BURST_0 => (4),
SATA_MIN_INIT_0 => (12),
SATA_MIN_WAKE_0 => (4),
SATA_BURST_VAL_1 => ("100"),
SATA_IDLE_VAL_1 => ("100"),
SATA_MAX_BURST_1 => (7),
SATA_MAX_INIT_1 => (22),
SATA_MAX_WAKE_1 => (7),
SATA_MIN_BURST_1 => (4),
SATA_MIN_INIT_1 => (12),
SATA_MIN_WAKE_1 => (4)
)
port map
(
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK0 => tied_to_ground_vec_i(2 downto 0),
LOOPBACK1 => tied_to_ground_vec_i(2 downto 0),
RXPOWERDOWN0 => RXPOWERDOWN0_IN,
RXPOWERDOWN1 => RXPOWERDOWN1_IN,
TXPOWERDOWN0 => TXPOWERDOWN0_IN,
TXPOWERDOWN1 => TXPOWERDOWN1_IN,
--------------------------------- PLL Ports --------------------------------
CLK00 => CLK00_IN,
CLK01 => CLK01_IN,
CLK10 => tied_to_ground_i,
CLK11 => tied_to_ground_i,
CLKINEAST0 => tied_to_ground_i,
CLKINEAST1 => tied_to_ground_i,
CLKINWEST0 => tied_to_ground_i,
CLKINWEST1 => tied_to_ground_i,
GCLK00 => tied_to_ground_i,
GCLK01 => tied_to_ground_i,
GCLK10 => tied_to_ground_i,
GCLK11 => tied_to_ground_i,
GTPRESET0 => GTPRESET0_IN,
GTPRESET1 => GTPRESET1_IN,
GTPTEST0 => "00010000",
GTPTEST1 => "00010000",
INTDATAWIDTH0 => tied_to_vcc_i,
INTDATAWIDTH1 => tied_to_vcc_i,
PLLCLK00 => tied_to_ground_i,
PLLCLK01 => tied_to_ground_i,
PLLCLK10 => tied_to_ground_i,
PLLCLK11 => tied_to_ground_i,
PLLLKDET0 => PLLLKDET0_OUT,
PLLLKDET1 => PLLLKDET1_OUT,
PLLLKDETEN0 => tied_to_vcc_i,
PLLLKDETEN1 => tied_to_vcc_i,
PLLPOWERDOWN0 => tied_to_ground_i,
PLLPOWERDOWN1 => tied_to_ground_i,
REFCLKOUT0 => open,
REFCLKOUT1 => open,
REFCLKPLL0 => open,
REFCLKPLL1 => open,
REFCLKPWRDNB0 => tied_to_vcc_i,
REFCLKPWRDNB1 => tied_to_vcc_i,
REFSELDYPLL0 => tied_to_ground_vec_i(2 downto 0),
REFSELDYPLL1 => tied_to_ground_vec_i(2 downto 0),
RESETDONE0 => RESETDONE0_OUT,
RESETDONE1 => RESETDONE1_OUT,
TSTCLK0 => tied_to_ground_i,
TSTCLK1 => tied_to_ground_i,
TSTIN0 => tied_to_ground_vec_i(11 downto 0),
TSTIN1 => tied_to_ground_vec_i(11 downto 0),
TSTOUT0 => open,
TSTOUT1 => open,
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISCOMMA0 => open,
RXCHARISCOMMA1 => open,
RXCHARISK0(3 downto 2) => rxcharisk0_float_i,
RXCHARISK0(1 downto 0) => RXCHARISK0_OUT,
RXCHARISK1(3 downto 2) => rxcharisk1_float_i,
RXCHARISK1(1 downto 0) => RXCHARISK1_OUT,
RXDEC8B10BUSE0 => tied_to_vcc_i,
RXDEC8B10BUSE1 => tied_to_vcc_i,
RXDISPERR0(3 downto 2) => rxdisperr0_float_i,
RXDISPERR0(1 downto 0) => RXDISPERR0_OUT,
RXDISPERR1(3 downto 2) => rxdisperr1_float_i,
RXDISPERR1(1 downto 0) => RXDISPERR1_OUT,
RXNOTINTABLE0(3 downto 2) => rxnotintable0_float_i,
RXNOTINTABLE0(1 downto 0) => RXNOTINTABLE0_OUT,
RXNOTINTABLE1(3 downto 2) => rxnotintable1_float_i,
RXNOTINTABLE1(1 downto 0) => RXNOTINTABLE1_OUT,
RXRUNDISP0 => open,
RXRUNDISP1 => open,
USRCODEERR0 => tied_to_ground_i,
USRCODEERR1 => tied_to_ground_i,
---------------------- Receive Ports - Channel Bonding ---------------------
RXCHANBONDSEQ0 => open,
RXCHANBONDSEQ1 => open,
RXCHANISALIGNED0 => open,
RXCHANISALIGNED1 => open,
RXCHANREALIGN0 => open,
RXCHANREALIGN1 => open,
RXCHBONDI => tied_to_ground_vec_i(2 downto 0),
RXCHBONDMASTER0 => tied_to_ground_i,
RXCHBONDMASTER1 => tied_to_ground_i,
RXCHBONDO => open,
RXCHBONDSLAVE0 => tied_to_ground_i,
RXCHBONDSLAVE1 => tied_to_ground_i,
RXENCHANSYNC0 => tied_to_ground_i,
RXENCHANSYNC1 => tied_to_ground_i,
---------------------- Receive Ports - Clock Correction --------------------
RXCLKCORCNT0 => RXCLKCORCNT0_OUT,
RXCLKCORCNT1 => RXCLKCORCNT1_OUT,
--------------- Receive Ports - Comma Detection and Alignment --------------
RXBYTEISALIGNED0 => open,
RXBYTEISALIGNED1 => open,
RXBYTEREALIGN0 => open,
RXBYTEREALIGN1 => open,
RXCOMMADET0 => open,
RXCOMMADET1 => open,
RXCOMMADETUSE0 => tied_to_vcc_i,
RXCOMMADETUSE1 => tied_to_vcc_i,
RXENMCOMMAALIGN0 => RXENMCOMMAALIGN0_IN,
RXENMCOMMAALIGN1 => RXENMCOMMAALIGN1_IN,
RXENPCOMMAALIGN0 => RXENPCOMMAALIGN0_IN,
RXENPCOMMAALIGN1 => RXENPCOMMAALIGN1_IN,
RXSLIDE0 => tied_to_ground_i,
RXSLIDE1 => tied_to_ground_i,
----------------------- Receive Ports - PRBS Detection ---------------------
PRBSCNTRESET0 => tied_to_ground_i,
PRBSCNTRESET1 => tied_to_ground_i,
RXENPRBSTST0 => tied_to_ground_vec_i(2 downto 0),
RXENPRBSTST1 => tied_to_ground_vec_i(2 downto 0),
RXPRBSERR0 => open,
RXPRBSERR1 => open,
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA0 => rxdata0_i,
RXDATA1 => rxdata1_i,
RXDATAWIDTH0 => "01",
RXDATAWIDTH1 => "01",
RXRECCLK0 => open,
RXRECCLK1 => open,
RXRESET0 => RXRESET0_IN,
RXRESET1 => RXRESET1_IN,
RXUSRCLK0 => RXUSRCLK0_IN,
RXUSRCLK1 => RXUSRCLK1_IN,
RXUSRCLK20 => RXUSRCLK20_IN,
RXUSRCLK21 => RXUSRCLK21_IN,
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
GATERXELECIDLE0 => GATERXELECIDLE0_IN,
GATERXELECIDLE1 => GATERXELECIDLE1_IN,
IGNORESIGDET0 => IGNORESIGDET0_IN,
IGNORESIGDET1 => IGNORESIGDET1_IN,
RCALINEAST => tied_to_ground_vec_i(4 downto 0),
RCALINWEST => tied_to_ground_vec_i(4 downto 0),
RCALOUTEAST => open,
RCALOUTWEST => open,
RXCDRRESET0 => tied_to_ground_i,
RXCDRRESET1 => tied_to_ground_i,
RXELECIDLE0 => RXELECIDLE0_OUT,
RXELECIDLE1 => RXELECIDLE1_OUT,
RXEQMIX0 => "11",
RXEQMIX1 => "11",
RXN0 => RXN0_IN,
RXN1 => RXN1_IN,
RXP0 => RXP0_IN,
RXP1 => RXP1_IN,
----------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------
RXBUFRESET0 => tied_to_ground_i,
RXBUFRESET1 => tied_to_ground_i,
RXBUFSTATUS0 => open,
RXBUFSTATUS1 => open,
RXENPMAPHASEALIGN0 => tied_to_ground_i,
RXENPMAPHASEALIGN1 => tied_to_ground_i,
RXPMASETPHASE0 => tied_to_ground_i,
RXPMASETPHASE1 => tied_to_ground_i,
RXSTATUS0 => RXSTATUS0_OUT,
RXSTATUS1 => RXSTATUS1_OUT,
--------------- Receive Ports - RX Loss-of-sync State Machine --------------
RXLOSSOFSYNC0 => open,
RXLOSSOFSYNC1 => open,
-------------- Receive Ports - RX Pipe Control for PCI Express -------------
PHYSTATUS0 => PHYSTATUS0_OUT,
PHYSTATUS1 => PHYSTATUS1_OUT,
RXVALID0 => RXVALID0_OUT,
RXVALID1 => RXVALID1_OUT,
-------------------- Receive Ports - RX Polarity Control -------------------
RXPOLARITY0 => RXPOLARITY0_IN,
RXPOLARITY1 => RXPOLARITY1_IN,
------------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
DADDR => tied_to_ground_vec_i(7 downto 0),
DCLK => tied_to_ground_i,
DEN => tied_to_ground_i,
DI => tied_to_ground_vec_i(15 downto 0),
DRDY => open,
DRPDO => open,
DWE => tied_to_ground_i,
---------------------------- TX/RX Datapath Ports --------------------------
GTPCLKFBEAST => open,
GTPCLKFBSEL0EAST => "10",
GTPCLKFBSEL0WEST => "00",
GTPCLKFBSEL1EAST => "11",
GTPCLKFBSEL1WEST => "01",
GTPCLKFBWEST => open,
GTPCLKOUT0 => GTPCLKOUT0_OUT,
GTPCLKOUT1 => GTPCLKOUT1_OUT,
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TXBYPASS8B10B0 => tied_to_ground_vec_i(3 downto 0),
TXBYPASS8B10B1 => tied_to_ground_vec_i(3 downto 0),
TXCHARDISPMODE0(3 downto 2) => tied_to_ground_vec_i(1 downto 0),
TXCHARDISPMODE0(1 downto 0) => TXCHARDISPMODE0_IN,
TXCHARDISPMODE1(3 downto 2) => tied_to_ground_vec_i(1 downto 0),
TXCHARDISPMODE1(1 downto 0) => TXCHARDISPMODE1_IN,
TXCHARDISPVAL0 => tied_to_ground_vec_i(3 downto 0),
TXCHARDISPVAL1 => tied_to_ground_vec_i(3 downto 0),
TXCHARISK0(3 downto 2) => tied_to_ground_vec_i(1 downto 0),
TXCHARISK0(1 downto 0) => TXCHARISK0_IN,
TXCHARISK1(3 downto 2) => tied_to_ground_vec_i(1 downto 0),
TXCHARISK1(1 downto 0) => TXCHARISK1_IN,
TXENC8B10BUSE0 => tied_to_vcc_i,
TXENC8B10BUSE1 => tied_to_vcc_i,
TXKERR0 => open,
TXKERR1 => open,
TXRUNDISP0 => open,
TXRUNDISP1 => open,
--------------- Transmit Ports - TX Buffer and Phase Alignment -------------
TXBUFSTATUS0 => open,
TXBUFSTATUS1 => open,
TXENPMAPHASEALIGN0 => tied_to_ground_i,
TXENPMAPHASEALIGN1 => tied_to_ground_i,
TXPMASETPHASE0 => tied_to_ground_i,
TXPMASETPHASE1 => tied_to_ground_i,
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA0 => txdata0_i,
TXDATA1 => txdata1_i,
TXDATAWIDTH0 => "01",
TXDATAWIDTH1 => "01",
TXOUTCLK0 => open,
TXOUTCLK1 => open,
TXRESET0 => tied_to_ground_i,
TXRESET1 => tied_to_ground_i,
TXUSRCLK0 => TXUSRCLK0_IN,
TXUSRCLK1 => TXUSRCLK1_IN,
TXUSRCLK20 => TXUSRCLK20_IN,
TXUSRCLK21 => TXUSRCLK21_IN,
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXBUFDIFFCTRL0 => "101",
TXBUFDIFFCTRL1 => "101",
TXDIFFCTRL0 => "1001",
TXDIFFCTRL1 => "1001",
TXINHIBIT0 => tied_to_ground_i,
TXINHIBIT1 => tied_to_ground_i,
TXN0 => TXN0_OUT,
TXN1 => TXN1_OUT,
TXP0 => TXP0_OUT,
TXP1 => TXP1_OUT,
TXPREEMPHASIS0 => "000",
TXPREEMPHASIS1 => "000",
--------------------- Transmit Ports - TX PRBS Generator -------------------
TXENPRBSTST0 => tied_to_ground_vec_i(2 downto 0),
TXENPRBSTST1 => tied_to_ground_vec_i(2 downto 0),
TXPRBSFORCEERR0 => tied_to_ground_i,
TXPRBSFORCEERR1 => tied_to_ground_i,
-------------------- Transmit Ports - TX Polarity Control ------------------
TXPOLARITY0 => tied_to_ground_i,
TXPOLARITY1 => tied_to_ground_i,
----------------- Transmit Ports - TX Ports for PCI Express ----------------
TXDETECTRX0 => TXDETECTRX0_IN,
TXDETECTRX1 => TXDETECTRX1_IN,
TXELECIDLE0 => TXELECIDLE0_IN,
TXELECIDLE1 => TXELECIDLE1_IN,
TXPDOWNASYNCH0 => tied_to_ground_i,
TXPDOWNASYNCH1 => tied_to_ground_i,
--------------------- Transmit Ports - TX Ports for SATA -------------------
TXCOMSTART0 => tied_to_ground_i,
TXCOMSTART1 => tied_to_ground_i,
TXCOMTYPE0 => tied_to_ground_i,
TXCOMTYPE1 => tied_to_ground_i
);
end RTL;
| gpl-3.0 | cbea33364b9f690834e8c36ab2aed7f2 | 0.373243 | 4.520599 | false | false | false | false |
Nixon-/VHDL_library | memory/to_test/Mem_Async.vhd | 1 | 2,043 | ----------------------------------------------------------------------------------
-- Nicolas Primeau
--
-- Create Date: 13:24:12 03/15/2014
-- Design Name: Asynchronous Generic Memory
-- Module Name: Mem_Async - Behavioral
-- Description:
--
-- Asynchronous generic memory. CAREFUL, Do not write until the address has been
-- stablized or else you might write to an unpredictable place! This component is
-- much better when you only want to read from it with STABLE address bus. STABLE.
-- ADDRESS. BUS.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.math_real.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Mem_Async is
generic(memSize: integer:=8;
numAdr: integer:=512);
port(
dataIn: in std_logic_vector(memSize -1 downto 0);
dataOut: out std_logic_vector(memSize-1 downto 0);
addr: in std_logic_vector((integer(log2(real(numAdr))))-1 downto 0);
rd_wr: in std_logic; -- rd low, wr high
reset: in std_logic
);
end Mem_Async;
architecture Behavioral of Mem_Async is
type RAM is array (numAdr-1 downto 0) of std_logic_vector(memSize -1);
signal memory: RAM;
begin
if(reset = '1') then
for i in 0 to numAdr-1 loop
memory(i) <= std_logic_vector(to_unsigned(0,memSize));
end loop;
dataOut <= (others => '0');
elsif(rd_wr = '0') then
dataOut <= memory(to_integer(unsigned(addr)));
elsif(rd_wr = '1') then
memory(to_integer(unsigned(addr))) <= dataIn;
dataOut <= (others => '0');
else
dataOut <= (others=>'0');
end if;
end Behavioral;
| gpl-2.0 | b97c2e86e34d1cbf75c68f2b97fd5f90 | 0.612824 | 3.59051 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/pcie_core/simulation/dsport/pcie_pipe_v6.vhd | 1 | 62,379 | -------------------------------------------------------------------------------
--
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : pcie_pipe_v6.vhd
-- Description: PIPE module for Virtex6 PCIe Block
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity pcie_pipe_v6 is
generic (
NO_OF_LANES : integer := 8;
LINK_CAP_MAX_LINK_SPEED : bit_vector := X"1";
PIPE_PIPELINE_STAGES : integer := 0 -- 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
);
port (
-- Pipe Per-Link Signals
pipe_tx_rcvr_det_i : in std_logic;
pipe_tx_reset_i : in std_logic;
pipe_tx_rate_i : in std_logic;
pipe_tx_deemph_i : in std_logic;
pipe_tx_margin_i : in std_logic_vector(2 downto 0);
pipe_tx_swing_i : in std_logic;
pipe_tx_rcvr_det_o : out std_logic;
pipe_tx_reset_o : out std_logic;
pipe_tx_rate_o : out std_logic;
pipe_tx_deemph_o : out std_logic;
pipe_tx_margin_o : out std_logic_vector(2 downto 0);
pipe_tx_swing_o : out std_logic;
-- Pipe Per-Lane Signals - Lane 0
pipe_rx0_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_rx0_data_o : out std_logic_vector(15 downto 0);
pipe_rx0_valid_o : out std_logic;
pipe_rx0_chanisaligned_o : out std_logic;
pipe_rx0_status_o : out std_logic_vector(2 downto 0);
pipe_rx0_phy_status_o : out std_logic;
pipe_rx0_elec_idle_o : out std_logic;
pipe_rx0_polarity_i : in std_logic;
pipe_tx0_compliance_i : in std_logic;
pipe_tx0_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_tx0_data_i : in std_logic_vector(15 downto 0);
pipe_tx0_elec_idle_i : in std_logic;
pipe_tx0_powerdown_i : in std_logic_vector(1 downto 0);
pipe_rx0_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_rx0_data_i : in std_logic_vector(15 downto 0);
pipe_rx0_valid_i : in std_logic;
pipe_rx0_chanisaligned_i : in std_logic;
pipe_rx0_status_i : in std_logic_vector(2 downto 0);
pipe_rx0_phy_status_i : in std_logic;
pipe_rx0_elec_idle_i : in std_logic;
pipe_rx0_polarity_o : out std_logic;
pipe_tx0_compliance_o : out std_logic;
pipe_tx0_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_tx0_data_o : out std_logic_vector(15 downto 0);
pipe_tx0_elec_idle_o : out std_logic;
pipe_tx0_powerdown_o : out std_logic_vector(1 downto 0);
-- Pipe Per-Lane Signals - Lane 1
pipe_rx1_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_rx1_data_o : out std_logic_vector(15 downto 0);
pipe_rx1_valid_o : out std_logic;
pipe_rx1_chanisaligned_o : out std_logic;
pipe_rx1_status_o : out std_logic_vector(2 downto 0);
pipe_rx1_phy_status_o : out std_logic;
pipe_rx1_elec_idle_o : out std_logic;
pipe_rx1_polarity_i : in std_logic;
pipe_tx1_compliance_i : in std_logic;
pipe_tx1_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_tx1_data_i : in std_logic_vector(15 downto 0);
pipe_tx1_elec_idle_i : in std_logic;
pipe_tx1_powerdown_i : in std_logic_vector(1 downto 0);
pipe_rx1_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_rx1_data_i : in std_logic_vector(15 downto 0);
pipe_rx1_valid_i : in std_logic;
pipe_rx1_chanisaligned_i : in std_logic;
pipe_rx1_status_i : in std_logic_vector(2 downto 0);
pipe_rx1_phy_status_i : in std_logic;
pipe_rx1_elec_idle_i : in std_logic;
pipe_rx1_polarity_o : out std_logic;
pipe_tx1_compliance_o : out std_logic;
pipe_tx1_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_tx1_data_o : out std_logic_vector(15 downto 0);
pipe_tx1_elec_idle_o : out std_logic;
pipe_tx1_powerdown_o : out std_logic_vector(1 downto 0);
-- Pipe Per-Lane Signals - Lane 2
pipe_rx2_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_rx2_data_o : out std_logic_vector(15 downto 0);
pipe_rx2_valid_o : out std_logic;
pipe_rx2_chanisaligned_o : out std_logic;
pipe_rx2_status_o : out std_logic_vector(2 downto 0);
pipe_rx2_phy_status_o : out std_logic;
pipe_rx2_elec_idle_o : out std_logic;
pipe_rx2_polarity_i : in std_logic;
pipe_tx2_compliance_i : in std_logic;
pipe_tx2_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_tx2_data_i : in std_logic_vector(15 downto 0);
pipe_tx2_elec_idle_i : in std_logic;
pipe_tx2_powerdown_i : in std_logic_vector(1 downto 0);
pipe_rx2_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_rx2_data_i : in std_logic_vector(15 downto 0);
pipe_rx2_valid_i : in std_logic;
pipe_rx2_chanisaligned_i : in std_logic;
pipe_rx2_status_i : in std_logic_vector(2 downto 0);
pipe_rx2_phy_status_i : in std_logic;
pipe_rx2_elec_idle_i : in std_logic;
pipe_rx2_polarity_o : out std_logic;
pipe_tx2_compliance_o : out std_logic;
pipe_tx2_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_tx2_data_o : out std_logic_vector(15 downto 0);
pipe_tx2_elec_idle_o : out std_logic;
pipe_tx2_powerdown_o : out std_logic_vector(1 downto 0);
-- Pipe Per-Lane Signals - Lane 3
pipe_rx3_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_rx3_data_o : out std_logic_vector(15 downto 0);
pipe_rx3_valid_o : out std_logic;
pipe_rx3_chanisaligned_o : out std_logic;
pipe_rx3_status_o : out std_logic_vector(2 downto 0);
pipe_rx3_phy_status_o : out std_logic;
pipe_rx3_elec_idle_o : out std_logic;
pipe_rx3_polarity_i : in std_logic;
pipe_tx3_compliance_i : in std_logic;
pipe_tx3_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_tx3_data_i : in std_logic_vector(15 downto 0);
pipe_tx3_elec_idle_i : in std_logic;
pipe_tx3_powerdown_i : in std_logic_vector(1 downto 0);
pipe_rx3_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_rx3_data_i : in std_logic_vector(15 downto 0);
pipe_rx3_valid_i : in std_logic;
pipe_rx3_chanisaligned_i : in std_logic;
pipe_rx3_status_i : in std_logic_vector(2 downto 0);
pipe_rx3_phy_status_i : in std_logic;
pipe_rx3_elec_idle_i : in std_logic;
pipe_rx3_polarity_o : out std_logic;
pipe_tx3_compliance_o : out std_logic;
pipe_tx3_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_tx3_data_o : out std_logic_vector(15 downto 0);
pipe_tx3_elec_idle_o : out std_logic;
pipe_tx3_powerdown_o : out std_logic_vector(1 downto 0);
-- Pipe Per-Lane Signals - Lane 4
pipe_rx4_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_rx4_data_o : out std_logic_vector(15 downto 0);
pipe_rx4_valid_o : out std_logic;
pipe_rx4_chanisaligned_o : out std_logic;
pipe_rx4_status_o : out std_logic_vector(2 downto 0);
pipe_rx4_phy_status_o : out std_logic;
pipe_rx4_elec_idle_o : out std_logic;
pipe_rx4_polarity_i : in std_logic;
pipe_tx4_compliance_i : in std_logic;
pipe_tx4_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_tx4_data_i : in std_logic_vector(15 downto 0);
pipe_tx4_elec_idle_i : in std_logic;
pipe_tx4_powerdown_i : in std_logic_vector(1 downto 0);
pipe_rx4_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_rx4_data_i : in std_logic_vector(15 downto 0);
pipe_rx4_valid_i : in std_logic;
pipe_rx4_chanisaligned_i : in std_logic;
pipe_rx4_status_i : in std_logic_vector(2 downto 0);
pipe_rx4_phy_status_i : in std_logic;
pipe_rx4_elec_idle_i : in std_logic;
pipe_rx4_polarity_o : out std_logic;
pipe_tx4_compliance_o : out std_logic;
pipe_tx4_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_tx4_data_o : out std_logic_vector(15 downto 0);
pipe_tx4_elec_idle_o : out std_logic;
pipe_tx4_powerdown_o : out std_logic_vector(1 downto 0);
-- Pipe Per-Lane Signals - Lane 5
pipe_rx5_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_rx5_data_o : out std_logic_vector(15 downto 0);
pipe_rx5_valid_o : out std_logic;
pipe_rx5_chanisaligned_o : out std_logic;
pipe_rx5_status_o : out std_logic_vector(2 downto 0);
pipe_rx5_phy_status_o : out std_logic;
pipe_rx5_elec_idle_o : out std_logic;
pipe_rx5_polarity_i : in std_logic;
pipe_tx5_compliance_i : in std_logic;
pipe_tx5_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_tx5_data_i : in std_logic_vector(15 downto 0);
pipe_tx5_elec_idle_i : in std_logic;
pipe_tx5_powerdown_i : in std_logic_vector(1 downto 0);
pipe_rx5_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_rx5_data_i : in std_logic_vector(15 downto 0);
pipe_rx5_valid_i : in std_logic;
pipe_rx5_chanisaligned_i : in std_logic;
pipe_rx5_status_i : in std_logic_vector(2 downto 0);
pipe_rx5_phy_status_i : in std_logic;
pipe_rx5_elec_idle_i : in std_logic;
pipe_rx5_polarity_o : out std_logic;
pipe_tx5_compliance_o : out std_logic;
pipe_tx5_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_tx5_data_o : out std_logic_vector(15 downto 0);
pipe_tx5_elec_idle_o : out std_logic;
pipe_tx5_powerdown_o : out std_logic_vector(1 downto 0);
-- Pipe Per-Lane Signals - Lane 6
pipe_rx6_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_rx6_data_o : out std_logic_vector(15 downto 0);
pipe_rx6_valid_o : out std_logic;
pipe_rx6_chanisaligned_o : out std_logic;
pipe_rx6_status_o : out std_logic_vector(2 downto 0);
pipe_rx6_phy_status_o : out std_logic;
pipe_rx6_elec_idle_o : out std_logic;
pipe_rx6_polarity_i : in std_logic;
pipe_tx6_compliance_i : in std_logic;
pipe_tx6_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_tx6_data_i : in std_logic_vector(15 downto 0);
pipe_tx6_elec_idle_i : in std_logic;
pipe_tx6_powerdown_i : in std_logic_vector(1 downto 0);
pipe_rx6_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_rx6_data_i : in std_logic_vector(15 downto 0);
pipe_rx6_valid_i : in std_logic;
pipe_rx6_chanisaligned_i : in std_logic;
pipe_rx6_status_i : in std_logic_vector(2 downto 0);
pipe_rx6_phy_status_i : in std_logic;
pipe_rx6_elec_idle_i : in std_logic;
pipe_rx6_polarity_o : out std_logic;
pipe_tx6_compliance_o : out std_logic;
pipe_tx6_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_tx6_data_o : out std_logic_vector(15 downto 0);
pipe_tx6_elec_idle_o : out std_logic;
pipe_tx6_powerdown_o : out std_logic_vector(1 downto 0);
-- Pipe Per-Lane Signals - Lane 7
pipe_rx7_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_rx7_data_o : out std_logic_vector(15 downto 0);
pipe_rx7_valid_o : out std_logic;
pipe_rx7_chanisaligned_o : out std_logic;
pipe_rx7_status_o : out std_logic_vector(2 downto 0);
pipe_rx7_phy_status_o : out std_logic;
pipe_rx7_elec_idle_o : out std_logic;
pipe_rx7_polarity_i : in std_logic;
pipe_tx7_compliance_i : in std_logic;
pipe_tx7_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_tx7_data_i : in std_logic_vector(15 downto 0);
pipe_tx7_elec_idle_i : in std_logic;
pipe_tx7_powerdown_i : in std_logic_vector(1 downto 0);
pipe_rx7_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_rx7_data_i : in std_logic_vector(15 downto 0);
pipe_rx7_valid_i : in std_logic;
pipe_rx7_chanisaligned_i : in std_logic;
pipe_rx7_status_i : in std_logic_vector(2 downto 0);
pipe_rx7_phy_status_i : in std_logic;
pipe_rx7_elec_idle_i : in std_logic;
pipe_rx7_polarity_o : out std_logic;
pipe_tx7_compliance_o : out std_logic;
pipe_tx7_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_tx7_data_o : out std_logic_vector(15 downto 0);
pipe_tx7_elec_idle_o : out std_logic;
pipe_tx7_powerdown_o : out std_logic_vector(1 downto 0);
-- Non PIPE signals
pl_ltssm_state : in std_logic_vector(5 downto 0);
pipe_clk : in std_logic;
rst_n : in std_logic
);
end pcie_pipe_v6;
architecture v6_pcie of pcie_pipe_v6 is
component pcie_pipe_lane_v6 is
generic (
PIPE_PIPELINE_STAGES : integer := 0
);
port (
pipe_rx_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_rx_data_o : out std_logic_vector(15 downto 0);
pipe_rx_valid_o : out std_logic;
pipe_rx_chanisaligned_o : out std_logic;
pipe_rx_status_o : out std_logic_vector(2 downto 0);
pipe_rx_phy_status_o : out std_logic;
pipe_rx_elec_idle_o : out std_logic;
pipe_rx_polarity_i : in std_logic;
pipe_tx_compliance_i : in std_logic;
pipe_tx_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_tx_data_i : in std_logic_vector(15 downto 0);
pipe_tx_elec_idle_i : in std_logic;
pipe_tx_powerdown_i : in std_logic_vector(1 downto 0);
pipe_rx_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_rx_data_i : in std_logic_vector(15 downto 0);
pipe_rx_valid_i : in std_logic;
pipe_rx_chanisaligned_i : in std_logic;
pipe_rx_status_i : in std_logic_vector(2 downto 0);
pipe_rx_phy_status_i : in std_logic;
pipe_rx_elec_idle_i : in std_logic;
pipe_rx_polarity_o : out std_logic;
pipe_tx_compliance_o : out std_logic;
pipe_tx_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_tx_data_o : out std_logic_vector(15 downto 0);
pipe_tx_elec_idle_o : out std_logic;
pipe_tx_powerdown_o : out std_logic_vector(1 downto 0);
pipe_clk : in std_logic;
rst_n : in std_logic
);
end component;
component pcie_pipe_misc_v6 is
generic (
PIPE_PIPELINE_STAGES : integer := 0
);
port (
pipe_tx_rcvr_det_i : in std_logic;
pipe_tx_reset_i : in std_logic;
pipe_tx_rate_i : in std_logic;
pipe_tx_deemph_i : in std_logic;
pipe_tx_margin_i : in std_logic_vector(2 downto 0);
pipe_tx_swing_i : in std_logic;
pipe_tx_rcvr_det_o : out std_logic;
pipe_tx_reset_o : out std_logic;
pipe_tx_rate_o : out std_logic;
pipe_tx_deemph_o : out std_logic;
pipe_tx_margin_o : out std_logic_vector(2 downto 0);
pipe_tx_swing_o : out std_logic;
pipe_clk : in std_logic;
rst_n : in std_logic
);
end component;
--******************************************************************//
-- Reality check. //
--******************************************************************//
constant Tc2o : integer := 1; -- clock to out delay model
signal pipe_rx0_char_is_k_q : std_logic_vector(1 downto 0);
signal pipe_rx0_data_q : std_logic_vector(15 downto 0);
signal pipe_rx1_char_is_k_q : std_logic_vector(1 downto 0);
signal pipe_rx1_data_q : std_logic_vector(15 downto 0);
signal pipe_rx2_char_is_k_q : std_logic_vector(1 downto 0);
signal pipe_rx2_data_q : std_logic_vector(15 downto 0);
signal pipe_rx3_char_is_k_q : std_logic_vector(1 downto 0);
signal pipe_rx3_data_q : std_logic_vector(15 downto 0);
signal pipe_rx4_char_is_k_q : std_logic_vector(1 downto 0);
signal pipe_rx4_data_q : std_logic_vector(15 downto 0);
signal pipe_rx5_char_is_k_q : std_logic_vector(1 downto 0);
signal pipe_rx5_data_q : std_logic_vector(15 downto 0);
signal pipe_rx6_char_is_k_q : std_logic_vector(1 downto 0);
signal pipe_rx6_data_q : std_logic_vector(15 downto 0);
signal pipe_rx7_char_is_k_q : std_logic_vector(1 downto 0);
signal pipe_rx7_data_q : std_logic_vector(15 downto 0);
-- Declare intermediate signals for referenced outputs
signal pipe_tx_rcvr_det_o_v6pcie91 : std_logic;
signal pipe_tx_reset_o_v6pcie92 : std_logic;
signal pipe_tx_rate_o_v6pcie90 : std_logic;
signal pipe_tx_deemph_o_v6pcie88 : std_logic;
signal pipe_tx_margin_o_v6pcie89 : std_logic_vector(2 downto 0);
signal pipe_tx_swing_o_v6pcie93 : std_logic;
signal pipe_rx0_valid_o_v6pcie5 : std_logic;
signal pipe_rx0_chanisaligned_o_v6pcie0 : std_logic;
signal pipe_rx0_status_o_v6pcie4 : std_logic_vector(2 downto 0);
signal pipe_rx0_phy_status_o_v6pcie2 : std_logic;
signal pipe_rx0_elec_idle_o_v6pcie1 : std_logic;
signal pipe_rx0_polarity_o_v6pcie3 : std_logic;
signal pipe_tx0_compliance_o_v6pcie49 : std_logic;
signal pipe_tx0_char_is_k_o_v6pcie48 : std_logic_vector(1 downto 0);
signal pipe_tx0_data_o_v6pcie50 : std_logic_vector(15 downto 0);
signal pipe_tx0_elec_idle_o_v6pcie51 : std_logic;
signal pipe_tx0_powerdown_o_v6pcie52 : std_logic_vector(1 downto 0);
signal pipe_rx1_valid_o_v6pcie11 : std_logic;
signal pipe_rx1_chanisaligned_o_v6pcie6 : std_logic;
signal pipe_rx1_status_o_v6pcie10 : std_logic_vector(2 downto 0);
signal pipe_rx1_phy_status_o_v6pcie8 : std_logic;
signal pipe_rx1_elec_idle_o_v6pcie7 : std_logic;
signal pipe_rx1_polarity_o_v6pcie9 : std_logic;
signal pipe_tx1_compliance_o_v6pcie54 : std_logic;
signal pipe_tx1_char_is_k_o_v6pcie53 : std_logic_vector(1 downto 0);
signal pipe_tx1_data_o_v6pcie55 : std_logic_vector(15 downto 0);
signal pipe_tx1_elec_idle_o_v6pcie56 : std_logic;
signal pipe_tx1_powerdown_o_v6pcie57 : std_logic_vector(1 downto 0);
signal pipe_rx2_valid_o_v6pcie17 : std_logic;
signal pipe_rx2_chanisaligned_o_v6pcie12 : std_logic;
signal pipe_rx2_status_o_v6pcie16 : std_logic_vector(2 downto 0);
signal pipe_rx2_phy_status_o_v6pcie14 : std_logic;
signal pipe_rx2_elec_idle_o_v6pcie13 : std_logic;
signal pipe_rx2_polarity_o_v6pcie15 : std_logic;
signal pipe_tx2_compliance_o_v6pcie59 : std_logic;
signal pipe_tx2_char_is_k_o_v6pcie58 : std_logic_vector(1 downto 0);
signal pipe_tx2_data_o_v6pcie60 : std_logic_vector(15 downto 0);
signal pipe_tx2_elec_idle_o_v6pcie61 : std_logic;
signal pipe_tx2_powerdown_o_v6pcie62 : std_logic_vector(1 downto 0);
signal pipe_rx3_valid_o_v6pcie23 : std_logic;
signal pipe_rx3_chanisaligned_o_v6pcie18 : std_logic;
signal pipe_rx3_status_o_v6pcie22 : std_logic_vector(2 downto 0);
signal pipe_rx3_phy_status_o_v6pcie20 : std_logic;
signal pipe_rx3_elec_idle_o_v6pcie19 : std_logic;
signal pipe_rx3_polarity_o_v6pcie21 : std_logic;
signal pipe_tx3_compliance_o_v6pcie64 : std_logic;
signal pipe_tx3_char_is_k_o_v6pcie63 : std_logic_vector(1 downto 0);
signal pipe_tx3_data_o_v6pcie65 : std_logic_vector(15 downto 0);
signal pipe_tx3_elec_idle_o_v6pcie66 : std_logic;
signal pipe_tx3_powerdown_o_v6pcie67 : std_logic_vector(1 downto 0);
signal pipe_rx4_valid_o_v6pcie29 : std_logic;
signal pipe_rx4_chanisaligned_o_v6pcie24 : std_logic;
signal pipe_rx4_status_o_v6pcie28 : std_logic_vector(2 downto 0);
signal pipe_rx4_phy_status_o_v6pcie26 : std_logic;
signal pipe_rx4_elec_idle_o_v6pcie25 : std_logic;
signal pipe_rx4_polarity_o_v6pcie27 : std_logic;
signal pipe_tx4_compliance_o_v6pcie69 : std_logic;
signal pipe_tx4_char_is_k_o_v6pcie68 : std_logic_vector(1 downto 0);
signal pipe_tx4_data_o_v6pcie70 : std_logic_vector(15 downto 0);
signal pipe_tx4_elec_idle_o_v6pcie71 : std_logic;
signal pipe_tx4_powerdown_o_v6pcie72 : std_logic_vector(1 downto 0);
signal pipe_rx5_valid_o_v6pcie35 : std_logic;
signal pipe_rx5_chanisaligned_o_v6pcie30 : std_logic;
signal pipe_rx5_status_o_v6pcie34 : std_logic_vector(2 downto 0);
signal pipe_rx5_phy_status_o_v6pcie32 : std_logic;
signal pipe_rx5_elec_idle_o_v6pcie31 : std_logic;
signal pipe_rx5_polarity_o_v6pcie33 : std_logic;
signal pipe_tx5_compliance_o_v6pcie74 : std_logic;
signal pipe_tx5_char_is_k_o_v6pcie73 : std_logic_vector(1 downto 0);
signal pipe_tx5_data_o_v6pcie75 : std_logic_vector(15 downto 0);
signal pipe_tx5_elec_idle_o_v6pcie76 : std_logic;
signal pipe_tx5_powerdown_o_v6pcie77 : std_logic_vector(1 downto 0);
signal pipe_rx6_valid_o_v6pcie41 : std_logic;
signal pipe_rx6_chanisaligned_o_v6pcie36 : std_logic;
signal pipe_rx6_status_o_v6pcie40 : std_logic_vector(2 downto 0);
signal pipe_rx6_phy_status_o_v6pcie38 : std_logic;
signal pipe_rx6_elec_idle_o_v6pcie37 : std_logic;
signal pipe_rx6_polarity_o_v6pcie39 : std_logic;
signal pipe_tx6_compliance_o_v6pcie79 : std_logic;
signal pipe_tx6_char_is_k_o_v6pcie78 : std_logic_vector(1 downto 0);
signal pipe_tx6_data_o_v6pcie80 : std_logic_vector(15 downto 0);
signal pipe_tx6_elec_idle_o_v6pcie81 : std_logic;
signal pipe_tx6_powerdown_o_v6pcie82 : std_logic_vector(1 downto 0);
signal pipe_rx7_valid_o_v6pcie47 : std_logic;
signal pipe_rx7_chanisaligned_o_v6pcie42 : std_logic;
signal pipe_rx7_status_o_v6pcie46 : std_logic_vector(2 downto 0);
signal pipe_rx7_phy_status_o_v6pcie44 : std_logic;
signal pipe_rx7_elec_idle_o_v6pcie43 : std_logic;
signal pipe_rx7_polarity_o_v6pcie45 : std_logic;
signal pipe_tx7_compliance_o_v6pcie84 : std_logic;
signal pipe_tx7_char_is_k_o_v6pcie83 : std_logic_vector(1 downto 0);
signal pipe_tx7_data_o_v6pcie85 : std_logic_vector(15 downto 0);
signal pipe_tx7_elec_idle_o_v6pcie86 : std_logic;
signal pipe_tx7_powerdown_o_v6pcie87 : std_logic_vector(1 downto 0);
begin
-- Drive referenced outputs
pipe_tx_rcvr_det_o <= pipe_tx_rcvr_det_o_v6pcie91;
pipe_tx_reset_o <= pipe_tx_reset_o_v6pcie92;
pipe_tx_rate_o <= pipe_tx_rate_o_v6pcie90;
pipe_tx_deemph_o <= pipe_tx_deemph_o_v6pcie88;
pipe_tx_margin_o <= pipe_tx_margin_o_v6pcie89;
pipe_tx_swing_o <= pipe_tx_swing_o_v6pcie93;
pipe_rx0_valid_o <= pipe_rx0_valid_o_v6pcie5;
pipe_rx0_chanisaligned_o <= pipe_rx0_chanisaligned_o_v6pcie0;
pipe_rx0_status_o <= pipe_rx0_status_o_v6pcie4;
pipe_rx0_phy_status_o <= pipe_rx0_phy_status_o_v6pcie2;
pipe_rx0_elec_idle_o <= pipe_rx0_elec_idle_o_v6pcie1;
pipe_rx0_polarity_o <= pipe_rx0_polarity_o_v6pcie3;
pipe_tx0_compliance_o <= pipe_tx0_compliance_o_v6pcie49;
pipe_tx0_char_is_k_o <= pipe_tx0_char_is_k_o_v6pcie48;
pipe_tx0_data_o <= pipe_tx0_data_o_v6pcie50;
pipe_tx0_elec_idle_o <= pipe_tx0_elec_idle_o_v6pcie51;
pipe_tx0_powerdown_o <= pipe_tx0_powerdown_o_v6pcie52;
pipe_rx1_valid_o <= pipe_rx1_valid_o_v6pcie11;
pipe_rx1_chanisaligned_o <= pipe_rx1_chanisaligned_o_v6pcie6;
pipe_rx1_status_o <= pipe_rx1_status_o_v6pcie10;
pipe_rx1_phy_status_o <= pipe_rx1_phy_status_o_v6pcie8;
pipe_rx1_elec_idle_o <= pipe_rx1_elec_idle_o_v6pcie7;
pipe_rx1_polarity_o <= pipe_rx1_polarity_o_v6pcie9;
pipe_tx1_compliance_o <= pipe_tx1_compliance_o_v6pcie54;
pipe_tx1_char_is_k_o <= pipe_tx1_char_is_k_o_v6pcie53;
pipe_tx1_data_o <= pipe_tx1_data_o_v6pcie55;
pipe_tx1_elec_idle_o <= pipe_tx1_elec_idle_o_v6pcie56;
pipe_tx1_powerdown_o <= pipe_tx1_powerdown_o_v6pcie57;
pipe_rx2_valid_o <= pipe_rx2_valid_o_v6pcie17;
pipe_rx2_chanisaligned_o <= pipe_rx2_chanisaligned_o_v6pcie12;
pipe_rx2_status_o <= pipe_rx2_status_o_v6pcie16;
pipe_rx2_phy_status_o <= pipe_rx2_phy_status_o_v6pcie14;
pipe_rx2_elec_idle_o <= pipe_rx2_elec_idle_o_v6pcie13;
pipe_rx2_polarity_o <= pipe_rx2_polarity_o_v6pcie15;
pipe_tx2_compliance_o <= pipe_tx2_compliance_o_v6pcie59;
pipe_tx2_char_is_k_o <= pipe_tx2_char_is_k_o_v6pcie58;
pipe_tx2_data_o <= pipe_tx2_data_o_v6pcie60;
pipe_tx2_elec_idle_o <= pipe_tx2_elec_idle_o_v6pcie61;
pipe_tx2_powerdown_o <= pipe_tx2_powerdown_o_v6pcie62;
pipe_rx3_valid_o <= pipe_rx3_valid_o_v6pcie23;
pipe_rx3_chanisaligned_o <= pipe_rx3_chanisaligned_o_v6pcie18;
pipe_rx3_status_o <= pipe_rx3_status_o_v6pcie22;
pipe_rx3_phy_status_o <= pipe_rx3_phy_status_o_v6pcie20;
pipe_rx3_elec_idle_o <= pipe_rx3_elec_idle_o_v6pcie19;
pipe_rx3_polarity_o <= pipe_rx3_polarity_o_v6pcie21;
pipe_tx3_compliance_o <= pipe_tx3_compliance_o_v6pcie64;
pipe_tx3_char_is_k_o <= pipe_tx3_char_is_k_o_v6pcie63;
pipe_tx3_data_o <= pipe_tx3_data_o_v6pcie65;
pipe_tx3_elec_idle_o <= pipe_tx3_elec_idle_o_v6pcie66;
pipe_tx3_powerdown_o <= pipe_tx3_powerdown_o_v6pcie67;
pipe_rx4_valid_o <= pipe_rx4_valid_o_v6pcie29;
pipe_rx4_chanisaligned_o <= pipe_rx4_chanisaligned_o_v6pcie24;
pipe_rx4_status_o <= pipe_rx4_status_o_v6pcie28;
pipe_rx4_phy_status_o <= pipe_rx4_phy_status_o_v6pcie26;
pipe_rx4_elec_idle_o <= pipe_rx4_elec_idle_o_v6pcie25;
pipe_rx4_polarity_o <= pipe_rx4_polarity_o_v6pcie27;
pipe_tx4_compliance_o <= pipe_tx4_compliance_o_v6pcie69;
pipe_tx4_char_is_k_o <= pipe_tx4_char_is_k_o_v6pcie68;
pipe_tx4_data_o <= pipe_tx4_data_o_v6pcie70;
pipe_tx4_elec_idle_o <= pipe_tx4_elec_idle_o_v6pcie71;
pipe_tx4_powerdown_o <= pipe_tx4_powerdown_o_v6pcie72;
pipe_rx5_valid_o <= pipe_rx5_valid_o_v6pcie35;
pipe_rx5_chanisaligned_o <= pipe_rx5_chanisaligned_o_v6pcie30;
pipe_rx5_status_o <= pipe_rx5_status_o_v6pcie34;
pipe_rx5_phy_status_o <= pipe_rx5_phy_status_o_v6pcie32;
pipe_rx5_elec_idle_o <= pipe_rx5_elec_idle_o_v6pcie31;
pipe_rx5_polarity_o <= pipe_rx5_polarity_o_v6pcie33;
pipe_tx5_compliance_o <= pipe_tx5_compliance_o_v6pcie74;
pipe_tx5_char_is_k_o <= pipe_tx5_char_is_k_o_v6pcie73;
pipe_tx5_data_o <= pipe_tx5_data_o_v6pcie75;
pipe_tx5_elec_idle_o <= pipe_tx5_elec_idle_o_v6pcie76;
pipe_tx5_powerdown_o <= pipe_tx5_powerdown_o_v6pcie77;
pipe_rx6_valid_o <= pipe_rx6_valid_o_v6pcie41;
pipe_rx6_chanisaligned_o <= pipe_rx6_chanisaligned_o_v6pcie36;
pipe_rx6_status_o <= pipe_rx6_status_o_v6pcie40;
pipe_rx6_phy_status_o <= pipe_rx6_phy_status_o_v6pcie38;
pipe_rx6_elec_idle_o <= pipe_rx6_elec_idle_o_v6pcie37;
pipe_rx6_polarity_o <= pipe_rx6_polarity_o_v6pcie39;
pipe_tx6_compliance_o <= pipe_tx6_compliance_o_v6pcie79;
pipe_tx6_char_is_k_o <= pipe_tx6_char_is_k_o_v6pcie78;
pipe_tx6_data_o <= pipe_tx6_data_o_v6pcie80;
pipe_tx6_elec_idle_o <= pipe_tx6_elec_idle_o_v6pcie81;
pipe_tx6_powerdown_o <= pipe_tx6_powerdown_o_v6pcie82;
pipe_rx7_valid_o <= pipe_rx7_valid_o_v6pcie47;
pipe_rx7_chanisaligned_o <= pipe_rx7_chanisaligned_o_v6pcie42;
pipe_rx7_status_o <= pipe_rx7_status_o_v6pcie46;
pipe_rx7_phy_status_o <= pipe_rx7_phy_status_o_v6pcie44;
pipe_rx7_elec_idle_o <= pipe_rx7_elec_idle_o_v6pcie43;
pipe_rx7_polarity_o <= pipe_rx7_polarity_o_v6pcie45;
pipe_tx7_compliance_o <= pipe_tx7_compliance_o_v6pcie84;
pipe_tx7_char_is_k_o <= pipe_tx7_char_is_k_o_v6pcie83;
pipe_tx7_data_o <= pipe_tx7_data_o_v6pcie85;
pipe_tx7_elec_idle_o <= pipe_tx7_elec_idle_o_v6pcie86;
pipe_tx7_powerdown_o <= pipe_tx7_powerdown_o_v6pcie87;
--synthesis translate_off
-- initial begin
-- $display("[%t] %m NO_OF_LANES %0d PIPE_PIPELINE_STAGES %0d", $time, NO_OF_LANES, PIPE_PIPELINE_STAGES);
-- end
--synthesis translate_on
pipe_misc_i : pcie_pipe_misc_v6
generic map (
PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES
)
port map (
pipe_tx_rcvr_det_i => pipe_tx_rcvr_det_i,
pipe_tx_reset_i => pipe_tx_reset_i,
pipe_tx_rate_i => pipe_tx_rate_i,
pipe_tx_deemph_i => pipe_tx_deemph_i,
pipe_tx_margin_i => pipe_tx_margin_i,
pipe_tx_swing_i => pipe_tx_swing_i,
pipe_tx_rcvr_det_o => pipe_tx_rcvr_det_o_v6pcie91,
pipe_tx_reset_o => pipe_tx_reset_o_v6pcie92,
pipe_tx_rate_o => pipe_tx_rate_o_v6pcie90,
pipe_tx_deemph_o => pipe_tx_deemph_o_v6pcie88,
pipe_tx_margin_o => pipe_tx_margin_o_v6pcie89,
pipe_tx_swing_o => pipe_tx_swing_o_v6pcie93,
pipe_clk => pipe_clk,
rst_n => rst_n
);
pipe_lane_0_i : pcie_pipe_lane_v6
generic map (
PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES
)
port map (
pipe_rx_char_is_k_o => pipe_rx0_char_is_k_q,
pipe_rx_data_o => pipe_rx0_data_q,
pipe_rx_valid_o => pipe_rx0_valid_o_v6pcie5,
pipe_rx_chanisaligned_o => pipe_rx0_chanisaligned_o_v6pcie0,
pipe_rx_status_o => pipe_rx0_status_o_v6pcie4,
pipe_rx_phy_status_o => pipe_rx0_phy_status_o_v6pcie2,
pipe_rx_elec_idle_o => pipe_rx0_elec_idle_o_v6pcie1,
pipe_rx_polarity_i => pipe_rx0_polarity_i,
pipe_tx_compliance_i => pipe_tx0_compliance_i,
pipe_tx_char_is_k_i => pipe_tx0_char_is_k_i,
pipe_tx_data_i => pipe_tx0_data_i,
pipe_tx_elec_idle_i => pipe_tx0_elec_idle_i,
pipe_tx_powerdown_i => pipe_tx0_powerdown_i,
pipe_rx_char_is_k_i => pipe_rx0_char_is_k_i,
pipe_rx_data_i => pipe_rx0_data_i,
pipe_rx_valid_i => pipe_rx0_valid_i,
pipe_rx_chanisaligned_i => pipe_rx0_chanisaligned_i,
pipe_rx_status_i => pipe_rx0_status_i,
pipe_rx_phy_status_i => pipe_rx0_phy_status_i,
pipe_rx_elec_idle_i => pipe_rx0_elec_idle_i,
pipe_rx_polarity_o => pipe_rx0_polarity_o_v6pcie3,
pipe_tx_compliance_o => pipe_tx0_compliance_o_v6pcie49,
pipe_tx_char_is_k_o => pipe_tx0_char_is_k_o_v6pcie48,
pipe_tx_data_o => pipe_tx0_data_o_v6pcie50,
pipe_tx_elec_idle_o => pipe_tx0_elec_idle_o_v6pcie51,
pipe_tx_powerdown_o => pipe_tx0_powerdown_o_v6pcie52,
pipe_clk => pipe_clk,
rst_n => rst_n
);
v6pcie94 : if (NO_OF_LANES >= 2) generate
pipe_lane_1_i : pcie_pipe_lane_v6
generic map (
PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES
)
port map (
pipe_rx_char_is_k_o => pipe_rx1_char_is_k_q,
pipe_rx_data_o => pipe_rx1_data_q,
pipe_rx_valid_o => pipe_rx1_valid_o_v6pcie11,
pipe_rx_chanisaligned_o => pipe_rx1_chanisaligned_o_v6pcie6,
pipe_rx_status_o => pipe_rx1_status_o_v6pcie10,
pipe_rx_phy_status_o => pipe_rx1_phy_status_o_v6pcie8,
pipe_rx_elec_idle_o => pipe_rx1_elec_idle_o_v6pcie7,
pipe_rx_polarity_i => pipe_rx1_polarity_i,
pipe_tx_compliance_i => pipe_tx1_compliance_i,
pipe_tx_char_is_k_i => pipe_tx1_char_is_k_i,
pipe_tx_data_i => pipe_tx1_data_i,
pipe_tx_elec_idle_i => pipe_tx1_elec_idle_i,
pipe_tx_powerdown_i => pipe_tx1_powerdown_i,
pipe_rx_char_is_k_i => pipe_rx1_char_is_k_i,
pipe_rx_data_i => pipe_rx1_data_i,
pipe_rx_valid_i => pipe_rx1_valid_i,
pipe_rx_chanisaligned_i => pipe_rx1_chanisaligned_i,
pipe_rx_status_i => pipe_rx1_status_i,
pipe_rx_phy_status_i => pipe_rx1_phy_status_i,
pipe_rx_elec_idle_i => pipe_rx1_elec_idle_i,
pipe_rx_polarity_o => pipe_rx1_polarity_o_v6pcie9,
pipe_tx_compliance_o => pipe_tx1_compliance_o_v6pcie54,
pipe_tx_char_is_k_o => pipe_tx1_char_is_k_o_v6pcie53,
pipe_tx_data_o => pipe_tx1_data_o_v6pcie55,
pipe_tx_elec_idle_o => pipe_tx1_elec_idle_o_v6pcie56,
pipe_tx_powerdown_o => pipe_tx1_powerdown_o_v6pcie57,
pipe_clk => pipe_clk,
rst_n => rst_n
);
end generate;
v6pcie95 : if (not(NO_OF_LANES >= 2)) generate
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
pipe_rx1_char_is_k_q <= "00";
pipe_rx1_data_q <= "0000000000000000";
pipe_rx1_valid_o_v6pcie11 <= '0';
pipe_rx1_chanisaligned_o_v6pcie6 <= '0';
pipe_rx1_status_o_v6pcie10 <= "000";
pipe_rx1_phy_status_o_v6pcie8 <= '0';
pipe_rx1_elec_idle_o_v6pcie7 <= '1';
pipe_rx1_polarity_o_v6pcie9 <= '0';
pipe_tx1_compliance_o_v6pcie54 <= '0';
pipe_tx1_char_is_k_o_v6pcie53 <= "00";
pipe_tx1_data_o_v6pcie55 <= "0000000000000000";
pipe_tx1_elec_idle_o_v6pcie56 <= '1';
pipe_tx1_powerdown_o_v6pcie57 <= "00";
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
end generate;
v6pcie96 : if (NO_OF_LANES >= 4) generate
pipe_lane_2_i : pcie_pipe_lane_v6
generic map (
PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES
)
port map (
pipe_rx_char_is_k_o => pipe_rx2_char_is_k_q,
pipe_rx_data_o => pipe_rx2_data_q,
pipe_rx_valid_o => pipe_rx2_valid_o_v6pcie17,
pipe_rx_chanisaligned_o => pipe_rx2_chanisaligned_o_v6pcie12,
pipe_rx_status_o => pipe_rx2_status_o_v6pcie16,
pipe_rx_phy_status_o => pipe_rx2_phy_status_o_v6pcie14,
pipe_rx_elec_idle_o => pipe_rx2_elec_idle_o_v6pcie13,
pipe_rx_polarity_i => pipe_rx2_polarity_i,
pipe_tx_compliance_i => pipe_tx2_compliance_i,
pipe_tx_char_is_k_i => pipe_tx2_char_is_k_i,
pipe_tx_data_i => pipe_tx2_data_i,
pipe_tx_elec_idle_i => pipe_tx2_elec_idle_i,
pipe_tx_powerdown_i => pipe_tx2_powerdown_i,
pipe_rx_char_is_k_i => pipe_rx2_char_is_k_i,
pipe_rx_data_i => pipe_rx2_data_i,
pipe_rx_valid_i => pipe_rx2_valid_i,
pipe_rx_chanisaligned_i => pipe_rx2_chanisaligned_i,
pipe_rx_status_i => pipe_rx2_status_i,
pipe_rx_phy_status_i => pipe_rx2_phy_status_i,
pipe_rx_elec_idle_i => pipe_rx2_elec_idle_i,
pipe_rx_polarity_o => pipe_rx2_polarity_o_v6pcie15,
pipe_tx_compliance_o => pipe_tx2_compliance_o_v6pcie59,
pipe_tx_char_is_k_o => pipe_tx2_char_is_k_o_v6pcie58,
pipe_tx_data_o => pipe_tx2_data_o_v6pcie60,
pipe_tx_elec_idle_o => pipe_tx2_elec_idle_o_v6pcie61,
pipe_tx_powerdown_o => pipe_tx2_powerdown_o_v6pcie62,
pipe_clk => pipe_clk,
rst_n => rst_n
);
pipe_lane_3_i : pcie_pipe_lane_v6
generic map (
PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES
)
port map (
pipe_rx_char_is_k_o => pipe_rx3_char_is_k_q,
pipe_rx_data_o => pipe_rx3_data_q,
pipe_rx_valid_o => pipe_rx3_valid_o_v6pcie23,
pipe_rx_chanisaligned_o => pipe_rx3_chanisaligned_o_v6pcie18,
pipe_rx_status_o => pipe_rx3_status_o_v6pcie22,
pipe_rx_phy_status_o => pipe_rx3_phy_status_o_v6pcie20,
pipe_rx_elec_idle_o => pipe_rx3_elec_idle_o_v6pcie19,
pipe_rx_polarity_i => pipe_rx3_polarity_i,
pipe_tx_compliance_i => pipe_tx3_compliance_i,
pipe_tx_char_is_k_i => pipe_tx3_char_is_k_i,
pipe_tx_data_i => pipe_tx3_data_i,
pipe_tx_elec_idle_i => pipe_tx3_elec_idle_i,
pipe_tx_powerdown_i => pipe_tx3_powerdown_i,
pipe_rx_char_is_k_i => pipe_rx3_char_is_k_i,
pipe_rx_data_i => pipe_rx3_data_i,
pipe_rx_valid_i => pipe_rx3_valid_i,
pipe_rx_chanisaligned_i => pipe_rx3_chanisaligned_i,
pipe_rx_status_i => pipe_rx3_status_i,
pipe_rx_phy_status_i => pipe_rx3_phy_status_i,
pipe_rx_elec_idle_i => pipe_rx3_elec_idle_i,
pipe_rx_polarity_o => pipe_rx3_polarity_o_v6pcie21,
pipe_tx_compliance_o => pipe_tx3_compliance_o_v6pcie64,
pipe_tx_char_is_k_o => pipe_tx3_char_is_k_o_v6pcie63,
pipe_tx_data_o => pipe_tx3_data_o_v6pcie65,
pipe_tx_elec_idle_o => pipe_tx3_elec_idle_o_v6pcie66,
pipe_tx_powerdown_o => pipe_tx3_powerdown_o_v6pcie67,
pipe_clk => pipe_clk,
rst_n => rst_n
);
end generate;
v6pcie97 : if (not(NO_OF_LANES >= 4)) generate
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
pipe_rx2_char_is_k_q <= "00";
pipe_rx2_data_q <= "0000000000000000";
pipe_rx2_valid_o_v6pcie17 <= '0';
pipe_rx2_chanisaligned_o_v6pcie12 <= '0';
pipe_rx2_status_o_v6pcie16 <= "000";
pipe_rx2_phy_status_o_v6pcie14 <= '0';
pipe_rx2_elec_idle_o_v6pcie13 <= '1';
pipe_rx2_polarity_o_v6pcie15 <= '0';
pipe_tx2_compliance_o_v6pcie59 <= '0';
pipe_tx2_char_is_k_o_v6pcie58 <= "00";
pipe_tx2_data_o_v6pcie60 <= "0000000000000000";
pipe_tx2_elec_idle_o_v6pcie61 <= '1';
pipe_tx2_powerdown_o_v6pcie62 <= "00";
pipe_rx3_char_is_k_q <= "00";
pipe_rx3_data_q <= "0000000000000000";
pipe_rx3_valid_o_v6pcie23 <= '0';
pipe_rx3_chanisaligned_o_v6pcie18 <= '0';
pipe_rx3_status_o_v6pcie22 <= "000";
pipe_rx3_phy_status_o_v6pcie20 <= '0';
pipe_rx3_elec_idle_o_v6pcie19 <= '1';
pipe_rx3_polarity_o_v6pcie21 <= '0';
pipe_tx3_compliance_o_v6pcie64 <= '0';
pipe_tx3_char_is_k_o_v6pcie63 <= "00";
pipe_tx3_data_o_v6pcie65 <= "0000000000000000";
pipe_tx3_elec_idle_o_v6pcie66 <= '1';
pipe_tx3_powerdown_o_v6pcie67 <= "00";
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
end generate;
v6pcie98 : if (NO_OF_LANES >= 8) generate
pipe_lane_4_i : pcie_pipe_lane_v6
generic map (
PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES
)
port map (
pipe_rx_char_is_k_o => pipe_rx4_char_is_k_q,
pipe_rx_data_o => pipe_rx4_data_q,
pipe_rx_valid_o => pipe_rx4_valid_o_v6pcie29,
pipe_rx_chanisaligned_o => pipe_rx4_chanisaligned_o_v6pcie24,
pipe_rx_status_o => pipe_rx4_status_o_v6pcie28,
pipe_rx_phy_status_o => pipe_rx4_phy_status_o_v6pcie26,
pipe_rx_elec_idle_o => pipe_rx4_elec_idle_o_v6pcie25,
pipe_rx_polarity_i => pipe_rx4_polarity_i,
pipe_tx_compliance_i => pipe_tx4_compliance_i,
pipe_tx_char_is_k_i => pipe_tx4_char_is_k_i,
pipe_tx_data_i => pipe_tx4_data_i,
pipe_tx_elec_idle_i => pipe_tx4_elec_idle_i,
pipe_tx_powerdown_i => pipe_tx4_powerdown_i,
pipe_rx_char_is_k_i => pipe_rx4_char_is_k_i,
pipe_rx_data_i => pipe_rx4_data_i,
pipe_rx_valid_i => pipe_rx4_valid_i,
pipe_rx_chanisaligned_i => pipe_rx4_chanisaligned_i,
pipe_rx_status_i => pipe_rx4_status_i,
pipe_rx_phy_status_i => pipe_rx4_phy_status_i,
pipe_rx_elec_idle_i => pipe_rx4_elec_idle_i,
pipe_rx_polarity_o => pipe_rx4_polarity_o_v6pcie27,
pipe_tx_compliance_o => pipe_tx4_compliance_o_v6pcie69,
pipe_tx_char_is_k_o => pipe_tx4_char_is_k_o_v6pcie68,
pipe_tx_data_o => pipe_tx4_data_o_v6pcie70,
pipe_tx_elec_idle_o => pipe_tx4_elec_idle_o_v6pcie71,
pipe_tx_powerdown_o => pipe_tx4_powerdown_o_v6pcie72,
pipe_clk => pipe_clk,
rst_n => rst_n
);
pipe_lane_5_i : pcie_pipe_lane_v6
generic map (
PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES
)
port map (
pipe_rx_char_is_k_o => pipe_rx5_char_is_k_q,
pipe_rx_data_o => pipe_rx5_data_q,
pipe_rx_valid_o => pipe_rx5_valid_o_v6pcie35,
pipe_rx_chanisaligned_o => pipe_rx5_chanisaligned_o_v6pcie30,
pipe_rx_status_o => pipe_rx5_status_o_v6pcie34,
pipe_rx_phy_status_o => pipe_rx5_phy_status_o_v6pcie32,
pipe_rx_elec_idle_o => pipe_rx5_elec_idle_o_v6pcie31,
pipe_rx_polarity_i => pipe_rx5_polarity_i,
pipe_tx_compliance_i => pipe_tx5_compliance_i,
pipe_tx_char_is_k_i => pipe_tx5_char_is_k_i,
pipe_tx_data_i => pipe_tx5_data_i,
pipe_tx_elec_idle_i => pipe_tx5_elec_idle_i,
pipe_tx_powerdown_i => pipe_tx5_powerdown_i,
pipe_rx_char_is_k_i => pipe_rx5_char_is_k_i,
pipe_rx_data_i => pipe_rx5_data_i,
pipe_rx_valid_i => pipe_rx5_valid_i,
pipe_rx_chanisaligned_i => pipe_rx5_chanisaligned_i,
pipe_rx_status_i => pipe_rx5_status_i,
pipe_rx_phy_status_i => pipe_rx4_phy_status_i,
pipe_rx_elec_idle_i => pipe_rx4_elec_idle_i,
pipe_rx_polarity_o => pipe_rx5_polarity_o_v6pcie33,
pipe_tx_compliance_o => pipe_tx5_compliance_o_v6pcie74,
pipe_tx_char_is_k_o => pipe_tx5_char_is_k_o_v6pcie73,
pipe_tx_data_o => pipe_tx5_data_o_v6pcie75,
pipe_tx_elec_idle_o => pipe_tx5_elec_idle_o_v6pcie76,
pipe_tx_powerdown_o => pipe_tx5_powerdown_o_v6pcie77,
pipe_clk => pipe_clk,
rst_n => rst_n
);
pipe_lane_6_i : pcie_pipe_lane_v6
generic map (
PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES
)
port map (
pipe_rx_char_is_k_o => pipe_rx6_char_is_k_q,
pipe_rx_data_o => pipe_rx6_data_q,
pipe_rx_valid_o => pipe_rx6_valid_o_v6pcie41,
pipe_rx_chanisaligned_o => pipe_rx6_chanisaligned_o_v6pcie36,
pipe_rx_status_o => pipe_rx6_status_o_v6pcie40,
pipe_rx_phy_status_o => pipe_rx6_phy_status_o_v6pcie38,
pipe_rx_elec_idle_o => pipe_rx6_elec_idle_o_v6pcie37,
pipe_rx_polarity_i => pipe_rx6_polarity_i,
pipe_tx_compliance_i => pipe_tx6_compliance_i,
pipe_tx_char_is_k_i => pipe_tx6_char_is_k_i,
pipe_tx_data_i => pipe_tx6_data_i,
pipe_tx_elec_idle_i => pipe_tx6_elec_idle_i,
pipe_tx_powerdown_i => pipe_tx6_powerdown_i,
pipe_rx_char_is_k_i => pipe_rx6_char_is_k_i,
pipe_rx_data_i => pipe_rx6_data_i,
pipe_rx_valid_i => pipe_rx6_valid_i,
pipe_rx_chanisaligned_i => pipe_rx6_chanisaligned_i,
pipe_rx_status_i => pipe_rx6_status_i,
pipe_rx_phy_status_i => pipe_rx4_phy_status_i,
pipe_rx_elec_idle_i => pipe_rx6_elec_idle_i,
pipe_rx_polarity_o => pipe_rx6_polarity_o_v6pcie39,
pipe_tx_compliance_o => pipe_tx6_compliance_o_v6pcie79,
pipe_tx_char_is_k_o => pipe_tx6_char_is_k_o_v6pcie78,
pipe_tx_data_o => pipe_tx6_data_o_v6pcie80,
pipe_tx_elec_idle_o => pipe_tx6_elec_idle_o_v6pcie81,
pipe_tx_powerdown_o => pipe_tx6_powerdown_o_v6pcie82,
pipe_clk => pipe_clk,
rst_n => rst_n
);
pipe_lane_7_i : pcie_pipe_lane_v6
generic map (
PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES
)
port map (
pipe_rx_char_is_k_o => pipe_rx7_char_is_k_q,
pipe_rx_data_o => pipe_rx7_data_q,
pipe_rx_valid_o => pipe_rx7_valid_o_v6pcie47,
pipe_rx_chanisaligned_o => pipe_rx7_chanisaligned_o_v6pcie42,
pipe_rx_status_o => pipe_rx7_status_o_v6pcie46,
pipe_rx_phy_status_o => pipe_rx7_phy_status_o_v6pcie44,
pipe_rx_elec_idle_o => pipe_rx7_elec_idle_o_v6pcie43,
pipe_rx_polarity_i => pipe_rx7_polarity_i,
pipe_tx_compliance_i => pipe_tx7_compliance_i,
pipe_tx_char_is_k_i => pipe_tx7_char_is_k_i,
pipe_tx_data_i => pipe_tx7_data_i,
pipe_tx_elec_idle_i => pipe_tx7_elec_idle_i,
pipe_tx_powerdown_i => pipe_tx7_powerdown_i,
pipe_rx_char_is_k_i => pipe_rx7_char_is_k_i,
pipe_rx_data_i => pipe_rx7_data_i,
pipe_rx_valid_i => pipe_rx7_valid_i,
pipe_rx_chanisaligned_i => pipe_rx7_chanisaligned_i,
pipe_rx_status_i => pipe_rx7_status_i,
pipe_rx_phy_status_i => pipe_rx4_phy_status_i,
pipe_rx_elec_idle_i => pipe_rx7_elec_idle_i,
pipe_rx_polarity_o => pipe_rx7_polarity_o_v6pcie45,
pipe_tx_compliance_o => pipe_tx7_compliance_o_v6pcie84,
pipe_tx_char_is_k_o => pipe_tx7_char_is_k_o_v6pcie83,
pipe_tx_data_o => pipe_tx7_data_o_v6pcie85,
pipe_tx_elec_idle_o => pipe_tx7_elec_idle_o_v6pcie86,
pipe_tx_powerdown_o => pipe_tx7_powerdown_o_v6pcie87,
pipe_clk => pipe_clk,
rst_n => rst_n
);
end generate;
v6pcie99 : if (not(NO_OF_LANES >= 8)) generate
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
pipe_rx4_char_is_k_q <= "00";
pipe_rx4_data_q <= "0000000000000000";
pipe_rx4_valid_o_v6pcie29 <= '0';
pipe_rx4_chanisaligned_o_v6pcie24 <= '0';
pipe_rx4_status_o_v6pcie28 <= "000";
pipe_rx4_phy_status_o_v6pcie26 <= '0';
pipe_rx4_elec_idle_o_v6pcie25 <= '1';
pipe_rx4_polarity_o_v6pcie27 <= '0';
pipe_tx4_compliance_o_v6pcie69 <= '0';
pipe_tx4_char_is_k_o_v6pcie68 <= "00";
pipe_tx4_data_o_v6pcie70 <= "0000000000000000";
pipe_tx4_elec_idle_o_v6pcie71 <= '1';
pipe_tx4_powerdown_o_v6pcie72 <= "00";
pipe_rx5_char_is_k_q <= "00";
pipe_rx5_data_q <= "0000000000000000";
pipe_rx5_valid_o_v6pcie35 <= '0';
pipe_rx5_chanisaligned_o_v6pcie30 <= '0';
pipe_rx5_status_o_v6pcie34 <= "000";
pipe_rx5_phy_status_o_v6pcie32 <= '0';
pipe_rx5_elec_idle_o_v6pcie31 <= '1';
pipe_rx5_polarity_o_v6pcie33 <= '0';
pipe_tx5_compliance_o_v6pcie74 <= '0';
pipe_tx5_char_is_k_o_v6pcie73 <= "00";
pipe_tx5_data_o_v6pcie75 <= "0000000000000000";
pipe_tx5_elec_idle_o_v6pcie76 <= '1';
pipe_tx5_powerdown_o_v6pcie77 <= "00";
pipe_rx6_char_is_k_q <= "00";
pipe_rx6_data_q <= "0000000000000000";
pipe_rx6_valid_o_v6pcie41 <= '0';
pipe_rx6_chanisaligned_o_v6pcie36 <= '0';
pipe_rx6_status_o_v6pcie40 <= "000";
pipe_rx6_phy_status_o_v6pcie38 <= '0';
pipe_rx6_elec_idle_o_v6pcie37 <= '1';
pipe_rx6_polarity_o_v6pcie39 <= '0';
pipe_tx6_compliance_o_v6pcie79 <= '0';
pipe_tx6_char_is_k_o_v6pcie78 <= "00";
pipe_tx6_data_o_v6pcie80 <= "0000000000000000";
pipe_tx6_elec_idle_o_v6pcie81 <= '1';
pipe_tx6_powerdown_o_v6pcie82 <= "00";
pipe_rx7_char_is_k_q <= "00";
pipe_rx7_data_q <= "0000000000000000";
pipe_rx7_valid_o_v6pcie47 <= '0';
pipe_rx7_chanisaligned_o_v6pcie42 <= '0';
pipe_rx7_status_o_v6pcie46 <= "000";
pipe_rx7_phy_status_o_v6pcie44 <= '0';
pipe_rx7_elec_idle_o_v6pcie43 <= '1';
pipe_rx7_polarity_o_v6pcie45 <= '0';
pipe_tx7_compliance_o_v6pcie84 <= '0';
pipe_tx7_char_is_k_o_v6pcie83 <= "00";
pipe_tx7_data_o_v6pcie85 <= "0000000000000000";
pipe_tx7_elec_idle_o_v6pcie86 <= '1';
pipe_tx7_powerdown_o_v6pcie87 <= "00";
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
end generate;
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
pipe_rx0_char_is_k_o <= pipe_rx0_char_is_k_q;
pipe_rx0_data_o <= pipe_rx0_data_q;
pipe_rx1_char_is_k_o <= pipe_rx1_char_is_k_q;
pipe_rx1_data_o <= pipe_rx1_data_q;
pipe_rx2_char_is_k_o <= pipe_rx2_char_is_k_q;
pipe_rx2_data_o <= pipe_rx2_data_q;
pipe_rx3_char_is_k_o <= pipe_rx3_char_is_k_q;
pipe_rx3_data_o <= pipe_rx3_data_q;
pipe_rx4_char_is_k_o <= pipe_rx4_char_is_k_q;
pipe_rx4_data_o <= pipe_rx4_data_q;
pipe_rx5_char_is_k_o <= pipe_rx5_char_is_k_q;
pipe_rx5_data_o <= pipe_rx5_data_q;
pipe_rx6_char_is_k_o <= pipe_rx6_char_is_k_q;
pipe_rx6_data_o <= pipe_rx6_data_q;
pipe_rx7_char_is_k_o <= pipe_rx7_char_is_k_q;
pipe_rx7_data_o <= pipe_rx7_data_q;
end v6_pcie;
| gpl-3.0 | c753bfffdcb419a119dba33cfd19164b | 0.489908 | 3.24637 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/pcie_core/simulation/functional/board.vhd | 1 | 9,123 | -------------------------------------------------------------------------------
--
-- (c) Copyright 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : board.vhd
-- Description: Top level testbench
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity board is
generic
(
REF_CLK_FREQ : integer := 1 -- 0 - 100 MHz, 1 - 125 MHz
);
end board;
architecture rtl of board is
--
-- Functions
--
function REF_CLK_HALF_CYCLE(FREQ_SEL : integer) return integer is
begin
case FREQ_SEL is
when 0 => return 5000; -- 100 MHz / 5000 ps half-cycle
when 1 => return 4000; -- 125 MHz / 4000 ps half-cycle
when others => return 1; -- invalid case
end case;
end REF_CLK_HALF_CYCLE;
--
-- Components
--
component xilinx_pcie_1_1_ep_s6 is
generic
(
FAST_TRAIN : boolean := FALSE
);
port
(
pci_exp_txp : out std_logic;
pci_exp_txn : out std_logic;
pci_exp_rxp : in std_logic;
pci_exp_rxn : in std_logic;
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_reset_n : in std_logic;
led_0 : out std_logic;
led_1 : out std_logic;
led_2 : out std_logic
);
end component xilinx_pcie_1_1_ep_s6;
component xilinx_pcie_2_0_rport_v6 is
generic
(
REF_CLK_FREQ : integer := 0;
ALLOW_X8_GEN2 : boolean := FALSE;
PL_FAST_TRAIN : boolean := FALSE;
LINK_CAP_MAX_LINK_SPEED : bit_vector := X"1";
DEVICE_ID : bit_vector := X"0007";
LINK_CAP_MAX_LINK_WIDTH : bit_vector := X"08";
LTSSM_MAX_LINK_WIDTH : bit_vector := X"08";
LINK_CAP_MAX_LINK_WIDTH_int : integer := 8;
LINK_CTRL2_TARGET_LINK_SPEED : bit_vector := X"2";
DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer := 2;
USER_CLK_FREQ : integer := 3;
VC0_TX_LASTPACKET : integer := 31;
VC0_RX_RAM_LIMIT : bit_vector := X"03FF";
VC0_TOTAL_CREDITS_CD : integer := 154;
VC0_TOTAL_CREDITS_PD : integer := 154
);
port (
sys_clk : in std_logic;
sys_reset_n : in std_logic;
pci_exp_rxn : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
pci_exp_rxp : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
pci_exp_txn : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
pci_exp_txp : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0)
);
end component xilinx_pcie_2_0_rport_v6;
component sys_clk_gen is
generic
(
HALFCYCLE : integer := 500;
OFFSET : integer := 0
);
port
(
sys_clk : out std_logic
);
end component sys_clk_gen;
component sys_clk_gen_ds is
generic
(
HALFCYCLE : integer := 500;
OFFSET : integer := 0
);
port
(
sys_clk_p : out std_logic;
sys_clk_n : out std_logic
);
end component sys_clk_gen_ds;
--
-- System reset
--
signal sys_reset_n : std_logic;
--
-- System clocks
--
signal rp_sys_clk : std_logic;
signal ep_sys_clk_p : std_logic;
signal ep_sys_clk_n : std_logic;
--
-- PCI-Express Serial Interconnect
--
signal ep_pci_exp_txn : std_logic_vector(0 downto 0);
signal ep_pci_exp_txp : std_logic_vector(0 downto 0);
signal rp_pci_exp_txn : std_logic_vector(0 downto 0);
signal rp_pci_exp_txp : std_logic_vector(0 downto 0);
--
-- Misc. signals
--
signal led_0 : std_logic;
signal led_1 : std_logic;
signal led_2 : std_logic;
begin
--
-- PCI-Express Endpoint Instance
--
EP : xilinx_pcie_1_1_ep_s6
generic map (
FAST_TRAIN => TRUE
)
port map (
-- SYS Inteface
sys_clk_p => ep_sys_clk_p,
sys_clk_n => ep_sys_clk_n,
sys_reset_n => sys_reset_n,
-- PCI-Express Interface
pci_exp_txn => ep_pci_exp_txn(0),
pci_exp_txp => ep_pci_exp_txp(0),
pci_exp_rxn => rp_pci_exp_txn(0),
pci_exp_rxp => rp_pci_exp_txp(0),
-- Misc signals
led_0 => led_0,
led_1 => led_1,
led_2 => led_2
);
--
-- PCI-Express Model Root Port Instance
--
RP : xilinx_pcie_2_0_rport_v6
generic map (
REF_CLK_FREQ => REF_CLK_FREQ,
PL_FAST_TRAIN => TRUE,
ALLOW_X8_GEN2 => FALSE,
LINK_CAP_MAX_LINK_SPEED => X"1",
DEVICE_ID => X"0007",
LINK_CAP_MAX_LINK_WIDTH => X"01",
LTSSM_MAX_LINK_WIDTH => X"01",
LINK_CAP_MAX_LINK_WIDTH_int => 1,
LINK_CTRL2_TARGET_LINK_SPEED => X"1",
DEV_CAP_MAX_PAYLOAD_SUPPORTED => 2,
USER_CLK_FREQ => 3,
VC0_TX_LASTPACKET => 31,
VC0_RX_RAM_LIMIT => X"03FF",
VC0_TOTAL_CREDITS_CD => 154,
VC0_TOTAL_CREDITS_PD => 154
)
port map (
-- SYS Inteface
sys_clk => rp_sys_clk,
sys_reset_n => sys_reset_n,
-- PCI-Express Interface
pci_exp_txn => rp_pci_exp_txn,
pci_exp_txp => rp_pci_exp_txp,
pci_exp_rxn => ep_pci_exp_txn,
pci_exp_rxp => ep_pci_exp_txp
);
--
-- Generate system clocks and reset
--
CLK_GEN_RP : sys_clk_gen
generic map (
HALFCYCLE => REF_CLK_HALF_CYCLE(REF_CLK_FREQ),
OFFSET => 0
)
port map (
sys_clk => rp_sys_clk
);
CLK_GEN_EP : sys_clk_gen_ds
generic map (
HALFCYCLE => REF_CLK_HALF_CYCLE(REF_CLK_FREQ),
OFFSET => 0
)
port map (
sys_clk_p => ep_sys_clk_p,
sys_clk_n => ep_sys_clk_n
);
BOARD_INIT : process
begin
report("[" & time'image(now) & "] : System Reset Asserted...");
sys_reset_n <= '0';
for n in 0 to 499 loop
wait until rising_edge(ep_sys_clk_p);
end loop;
report("[" & time'image(now) & "] : System Reset De-asserted...");
sys_reset_n <= '1';
wait until falling_edge(sys_reset_n); -- forever
end process BOARD_INIT;
end; -- board
| gpl-3.0 | 318377dada0154188d9417d07047edf0 | 0.542037 | 3.618802 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/ddr3_controller/example_design/sim/functional/sim_tb_top.vhd | 1 | 27,898 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.9
-- \ \ Application : MIG
-- / / Filename : sim_tb_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:58 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
-- Device : Spartan-6
-- Design Name : DDR/DDR2/DDR3/LPDDR
-- Purpose : This is the simulation testbench which is used to verify the
-- design. The basic clocks and resets to the interface are
-- generated here. This also connects the memory interface to the
-- memory model.
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity sim_tb_top is
end entity sim_tb_top;
architecture arch of sim_tb_top is
-- ========================================================================== --
-- Parameters --
-- ========================================================================== --
constant DEBUG_EN : integer :=0;
constant C1_HW_TESTING : string := "FALSE";
constant C3_HW_TESTING : string := "FALSE";
function c1_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) ) return std_logic_vector is
begin
if (C1_HW_TESTING = "FALSE") then
return val1;
else
return val2;
end if;
end function;
function c3_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) ) return std_logic_vector is
begin
if (C3_HW_TESTING = "FALSE") then
return val1;
else
return val2;
end if;
end function;
constant C1_MEMCLK_PERIOD : integer := 2500;
constant C1_RST_ACT_LOW : integer := 0;
constant C1_INPUT_CLK_TYPE : string := "DIFFERENTIAL";
constant C1_CLK_PERIOD_NS : real := 2500.0 / 1000.0;
constant C1_TCYC_SYS : real := C1_CLK_PERIOD_NS/2.0;
constant C1_TCYC_SYS_DIV2 : time := C1_TCYC_SYS * 1 ns;
constant C1_NUM_DQ_PINS : integer := 16;
constant C1_MEM_ADDR_WIDTH : integer := 14;
constant C1_MEM_BANKADDR_WIDTH : integer := 3;
constant C1_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
constant C1_P0_MASK_SIZE : integer := 4;
constant C1_P0_DATA_PORT_SIZE : integer := 32;
constant C1_P1_MASK_SIZE : integer := 4;
constant C1_P1_DATA_PORT_SIZE : integer := 32;
constant C1_CALIB_SOFT_IP : string := "TRUE";
constant C1_SIMULATION : string := "TRUE";
constant C3_MEMCLK_PERIOD : integer := 2500;
constant C3_RST_ACT_LOW : integer := 0;
constant C3_INPUT_CLK_TYPE : string := "DIFFERENTIAL";
constant C3_CLK_PERIOD_NS : real := 2500.0 / 1000.0;
constant C3_TCYC_SYS : real := C3_CLK_PERIOD_NS/2.0;
constant C3_TCYC_SYS_DIV2 : time := C3_TCYC_SYS * 1 ns;
constant C3_NUM_DQ_PINS : integer := 16;
constant C3_MEM_ADDR_WIDTH : integer := 14;
constant C3_MEM_BANKADDR_WIDTH : integer := 3;
constant C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
constant C3_P0_MASK_SIZE : integer := 4;
constant C3_P0_DATA_PORT_SIZE : integer := 32;
constant C3_P1_MASK_SIZE : integer := 4;
constant C3_P1_DATA_PORT_SIZE : integer := 32;
constant C3_CALIB_SOFT_IP : string := "TRUE";
constant C3_SIMULATION : string := "TRUE";
-- ========================================================================== --
-- Component Declarations
-- ========================================================================== --
component example_top is
generic
(
C1_P0_MASK_SIZE : integer;
C1_P0_DATA_PORT_SIZE : integer;
C1_P1_MASK_SIZE : integer;
C1_P1_DATA_PORT_SIZE : integer;
C1_MEMCLK_PERIOD : integer;
C1_RST_ACT_LOW : integer;
C1_INPUT_CLK_TYPE : string;
DEBUG_EN : integer;
C1_CALIB_SOFT_IP : string;
C1_SIMULATION : string;
C1_HW_TESTING : string;
C1_MEM_ADDR_ORDER : string;
C1_NUM_DQ_PINS : integer;
C1_MEM_ADDR_WIDTH : integer;
C1_MEM_BANKADDR_WIDTH : integer;
C3_P0_MASK_SIZE : integer;
C3_P0_DATA_PORT_SIZE : integer;
C3_P1_MASK_SIZE : integer;
C3_P1_DATA_PORT_SIZE : integer;
C3_MEMCLK_PERIOD : integer;
C3_RST_ACT_LOW : integer;
C3_INPUT_CLK_TYPE : string;
C3_CALIB_SOFT_IP : string;
C3_SIMULATION : string;
C3_HW_TESTING : string;
C3_MEM_ADDR_ORDER : string;
C3_NUM_DQ_PINS : integer;
C3_MEM_ADDR_WIDTH : integer;
C3_MEM_BANKADDR_WIDTH : integer
);
port
(
calib_done : out std_logic;
error : out std_logic;
mcb1_dram_dq : inout std_logic_vector(C1_NUM_DQ_PINS-1 downto 0);
mcb1_dram_a : out std_logic_vector(C1_MEM_ADDR_WIDTH-1 downto 0);
mcb1_dram_ba : out std_logic_vector(C1_MEM_BANKADDR_WIDTH-1 downto 0);
mcb1_dram_ras_n : out std_logic;
mcb1_dram_cas_n : out std_logic;
mcb1_dram_we_n : out std_logic;
mcb1_dram_odt : out std_logic;
mcb1_dram_cke : out std_logic;
mcb1_dram_dm : out std_logic;
mcb1_rzq : inout std_logic;
mcb1_zio : inout std_logic;
c1_sys_clk_p : in std_logic;
c1_sys_clk_n : in std_logic;
c1_sys_rst_i : in std_logic;
mcb1_dram_dqs : inout std_logic;
mcb1_dram_dqs_n : inout std_logic;
mcb1_dram_ck : out std_logic;
mcb1_dram_ck_n : out std_logic;
mcb1_dram_udqs : inout std_logic;
mcb1_dram_udqs_n : inout std_logic;
mcb1_dram_udm : out std_logic;
mcb1_dram_reset_n : out std_logic;
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
c3_sys_clk_p : in std_logic;
c3_sys_clk_n : in std_logic;
c3_sys_rst_i : in std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_reset_n : out std_logic
);
end component;
component ddr3_model_c1 is
port (
ck : in std_logic;
ck_n : in std_logic;
cke : in std_logic;
cs_n : in std_logic;
ras_n : in std_logic;
cas_n : in std_logic;
we_n : in std_logic;
dm_tdqs : inout std_logic_vector((C1_NUM_DQ_PINS/16) downto 0);
ba : in std_logic_vector((C1_MEM_BANKADDR_WIDTH - 1) downto 0);
addr : in std_logic_vector((C1_MEM_ADDR_WIDTH - 1) downto 0);
dq : inout std_logic_vector((C1_NUM_DQ_PINS - 1) downto 0);
dqs : inout std_logic_vector((C1_NUM_DQ_PINS/16) downto 0);
dqs_n : inout std_logic_vector((C1_NUM_DQ_PINS/16) downto 0);
tdqs_n : out std_logic_vector((C1_NUM_DQ_PINS/16) downto 0);
odt : in std_logic;
rst_n : in std_logic
);
end component;
component ddr3_model_c3 is
port (
ck : in std_logic;
ck_n : in std_logic;
cke : in std_logic;
cs_n : in std_logic;
ras_n : in std_logic;
cas_n : in std_logic;
we_n : in std_logic;
dm_tdqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
ba : in std_logic_vector((C3_MEM_BANKADDR_WIDTH - 1) downto 0);
addr : in std_logic_vector((C3_MEM_ADDR_WIDTH - 1) downto 0);
dq : inout std_logic_vector((C3_NUM_DQ_PINS - 1) downto 0);
dqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
dqs_n : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
tdqs_n : out std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
odt : in std_logic;
rst_n : in std_logic
);
end component;
-- ========================================================================== --
-- Signal Declarations --
-- ========================================================================== --
-- Clocks
signal c1_sys_clk : std_logic := '0';
signal c1_sys_clk_p : std_logic;
signal c1_sys_clk_n : std_logic;
-- System Reset
signal c1_sys_rst : std_logic := '0';
signal c1_sys_rst_i : std_logic;
-- Design-Top Port Map
signal mcb1_dram_a : std_logic_vector(C1_MEM_ADDR_WIDTH-1 downto 0);
signal mcb1_dram_ba : std_logic_vector(C1_MEM_BANKADDR_WIDTH-1 downto 0);
signal mcb1_dram_ck : std_logic;
signal mcb1_dram_ck_n : std_logic;
signal mcb1_dram_dq : std_logic_vector(C1_NUM_DQ_PINS-1 downto 0);
signal mcb1_dram_dqs : std_logic;
signal mcb1_dram_dqs_n : std_logic;
signal mcb1_dram_dm : std_logic;
signal mcb1_dram_ras_n : std_logic;
signal mcb1_dram_cas_n : std_logic;
signal mcb1_dram_we_n : std_logic;
signal mcb1_dram_cke : std_logic;
signal mcb1_dram_odt : std_logic;
signal mcb1_dram_reset_n : std_logic;
signal calib_done : std_logic;
signal error : std_logic;
signal mcb1_dram_udqs : std_logic;
signal mcb1_dram_udqs_n : std_logic;
signal mcb1_dram_dqs_vector : std_logic_vector(1 downto 0);
signal mcb1_dram_dqs_n_vector : std_logic_vector(1 downto 0);
signal mcb1_dram_udm :std_logic; -- for X16 parts
signal mcb1_dram_dm_vector : std_logic_vector(1 downto 0);
signal mcb1_command : std_logic_vector(2 downto 0);
signal mcb1_enable1 : std_logic;
signal mcb1_enable2 : std_logic;
-- Clocks
signal c3_sys_clk : std_logic := '0';
signal c3_sys_clk_p : std_logic;
signal c3_sys_clk_n : std_logic;
-- System Reset
signal c3_sys_rst : std_logic := '0';
signal c3_sys_rst_i : std_logic;
-- Design-Top Port Map
signal mcb3_dram_a : std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
signal mcb3_dram_ba : std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
signal mcb3_dram_ck : std_logic;
signal mcb3_dram_ck_n : std_logic;
signal mcb3_dram_dq : std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
signal mcb3_dram_dqs : std_logic;
signal mcb3_dram_dqs_n : std_logic;
signal mcb3_dram_dm : std_logic;
signal mcb3_dram_ras_n : std_logic;
signal mcb3_dram_cas_n : std_logic;
signal mcb3_dram_we_n : std_logic;
signal mcb3_dram_cke : std_logic;
signal mcb3_dram_odt : std_logic;
signal mcb3_dram_reset_n : std_logic;
signal mcb3_dram_udqs : std_logic;
signal mcb3_dram_udqs_n : std_logic;
signal mcb3_dram_dqs_vector : std_logic_vector(1 downto 0);
signal mcb3_dram_dqs_n_vector : std_logic_vector(1 downto 0);
signal mcb3_dram_udm :std_logic; -- for X16 parts
signal mcb3_dram_dm_vector : std_logic_vector(1 downto 0);
signal mcb3_command : std_logic_vector(2 downto 0);
signal mcb3_enable1 : std_logic;
signal mcb3_enable2 : std_logic;
signal rzq1 : std_logic;
signal rzq3 : std_logic;
signal zio1 : std_logic;
signal zio3 : std_logic;
function vector (asi:std_logic) return std_logic_vector is
variable v : std_logic_vector(0 downto 0) ;
begin
v(0) := asi;
return(v);
end function vector;
begin
-- ========================================================================== --
-- Clocks Generation --
-- ========================================================================== --
process
begin
c1_sys_clk <= not c1_sys_clk;
wait for (C1_TCYC_SYS_DIV2);
end process;
c1_sys_clk_p <= c1_sys_clk;
c1_sys_clk_n <= not c1_sys_clk;
process
begin
c3_sys_clk <= not c3_sys_clk;
wait for (C3_TCYC_SYS_DIV2);
end process;
c3_sys_clk_p <= c3_sys_clk;
c3_sys_clk_n <= not c3_sys_clk;
-- ========================================================================== --
-- Reset Generation --
-- ========================================================================== --
process
begin
c1_sys_rst <= '0';
wait for 200 ns;
c1_sys_rst <= '1';
wait;
end process;
c1_sys_rst_i <= c1_sys_rst when (C1_RST_ACT_LOW = 1) else (not c1_sys_rst);
process
begin
c3_sys_rst <= '0';
wait for 200 ns;
c3_sys_rst <= '1';
wait;
end process;
c3_sys_rst_i <= c3_sys_rst when (C3_RST_ACT_LOW = 1) else (not c3_sys_rst);
-- The PULLDOWN component is connected to the ZIO signal primarily to avoid the
-- unknown state in simulation. In real hardware, ZIO should be a no connect(NC) pin.
zio_pulldown1 : PULLDOWN port map(O => zio1);
zio_pulldown3 : PULLDOWN port map(O => zio3);
rzq_pulldown1 : PULLDOWN port map(O => rzq1);
rzq_pulldown3 : PULLDOWN port map(O => rzq3);
-- ========================================================================== --
-- DESIGN TOP INSTANTIATION --
-- ========================================================================== --
design_top : example_top generic map
(
C1_P0_MASK_SIZE => C1_P0_MASK_SIZE,
C1_P0_DATA_PORT_SIZE => C1_P0_DATA_PORT_SIZE,
C1_P1_MASK_SIZE => C1_P1_MASK_SIZE,
C1_P1_DATA_PORT_SIZE => C1_P1_DATA_PORT_SIZE,
C1_MEMCLK_PERIOD => C1_MEMCLK_PERIOD,
C1_RST_ACT_LOW => C1_RST_ACT_LOW,
C1_INPUT_CLK_TYPE => C1_INPUT_CLK_TYPE,
DEBUG_EN => DEBUG_EN,
C1_MEM_ADDR_ORDER => C1_MEM_ADDR_ORDER,
C1_NUM_DQ_PINS => C1_NUM_DQ_PINS,
C1_MEM_ADDR_WIDTH => C1_MEM_ADDR_WIDTH,
C1_MEM_BANKADDR_WIDTH => C1_MEM_BANKADDR_WIDTH,
C1_HW_TESTING => C1_HW_TESTING,
C1_SIMULATION => C1_SIMULATION,
C1_CALIB_SOFT_IP => C1_CALIB_SOFT_IP,
C3_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C3_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C3_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C3_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C3_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
C3_RST_ACT_LOW => C3_RST_ACT_LOW,
C3_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
C3_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
C3_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C3_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
C3_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH,
C3_HW_TESTING => C3_HW_TESTING,
C3_SIMULATION => C3_SIMULATION,
C3_CALIB_SOFT_IP => C3_CALIB_SOFT_IP
)
port map (
calib_done => calib_done,
error => error,
c1_sys_clk_p => c1_sys_clk_p,
c1_sys_clk_n => c1_sys_clk_n,
c1_sys_rst_i => c1_sys_rst_i,
mcb1_dram_dq => mcb1_dram_dq,
mcb1_dram_a => mcb1_dram_a,
mcb1_dram_ba => mcb1_dram_ba,
mcb1_dram_ras_n => mcb1_dram_ras_n,
mcb1_dram_cas_n => mcb1_dram_cas_n,
mcb1_dram_we_n => mcb1_dram_we_n,
mcb1_dram_odt => mcb1_dram_odt,
mcb1_dram_cke => mcb1_dram_cke,
mcb1_dram_ck => mcb1_dram_ck,
mcb1_dram_ck_n => mcb1_dram_ck_n,
mcb1_dram_dqs_n => mcb1_dram_dqs_n,
mcb1_dram_reset_n => mcb1_dram_reset_n,
mcb1_dram_udqs => mcb1_dram_udqs, -- for X16 parts
mcb1_dram_udqs_n => mcb1_dram_udqs_n, -- for X16 parts
mcb1_dram_udm => mcb1_dram_udm, -- for X16 parts
mcb1_dram_dm => mcb1_dram_dm,
mcb1_rzq => rzq1,
mcb1_zio => zio1,
mcb1_dram_dqs => mcb1_dram_dqs,
c3_sys_clk_p => c3_sys_clk_p,
c3_sys_clk_n => c3_sys_clk_n,
c3_sys_rst_i => c3_sys_rst_i,
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_reset_n => mcb3_dram_reset_n,
mcb3_dram_udqs => mcb3_dram_udqs, -- for X16 parts
mcb3_dram_udqs_n => mcb3_dram_udqs_n, -- for X16 parts
mcb3_dram_udm => mcb3_dram_udm, -- for X16 parts
mcb3_dram_dm => mcb3_dram_dm,
mcb3_rzq => rzq3,
mcb3_zio => zio3,
mcb3_dram_dqs => mcb3_dram_dqs
);
-- ========================================================================== --
-- Memory model instances --
-- ========================================================================== --
mcb1_command <= (mcb1_dram_ras_n & mcb1_dram_cas_n & mcb1_dram_we_n);
process(mcb1_dram_ck)
begin
if (rising_edge(mcb1_dram_ck)) then
if (c1_sys_rst = '0') then
mcb1_enable1 <= '0';
mcb1_enable2 <= '0';
elsif (mcb1_command = "100") then
mcb1_enable2 <= '0';
elsif (mcb1_command = "101") then
mcb1_enable2 <= '1';
else
mcb1_enable2 <= mcb1_enable2;
end if;
mcb1_enable1 <= mcb1_enable2;
end if;
end process;
-----------------------------------------------------------------------------
--read
-----------------------------------------------------------------------------
mcb1_dram_dqs_vector(1 downto 0) <= (mcb1_dram_udqs & mcb1_dram_dqs)
when (mcb1_enable2 = '0' and mcb1_enable1 = '0')
else "ZZ";
mcb1_dram_dqs_n_vector(1 downto 0) <= (mcb1_dram_udqs_n & mcb1_dram_dqs_n)
when (mcb1_enable2 = '0' and mcb1_enable1 = '0')
else "ZZ";
-----------------------------------------------------------------------------
--write
-----------------------------------------------------------------------------
mcb1_dram_dqs <= mcb1_dram_dqs_vector(0)
when ( mcb1_enable1 = '1') else 'Z';
mcb1_dram_udqs <= mcb1_dram_dqs_vector(1)
when (mcb1_enable1 = '1') else 'Z';
mcb1_dram_dqs_n <= mcb1_dram_dqs_n_vector(0)
when (mcb1_enable1 = '1') else 'Z';
mcb1_dram_udqs_n <= mcb1_dram_dqs_n_vector(1)
when (mcb1_enable1 = '1') else 'Z';
mcb3_command <= (mcb3_dram_ras_n & mcb3_dram_cas_n & mcb3_dram_we_n);
process(mcb3_dram_ck)
begin
if (rising_edge(mcb3_dram_ck)) then
if (c3_sys_rst = '0') then
mcb3_enable1 <= '0';
mcb3_enable2 <= '0';
elsif (mcb3_command = "100") then
mcb3_enable2 <= '0';
elsif (mcb3_command = "101") then
mcb3_enable2 <= '1';
else
mcb3_enable2 <= mcb3_enable2;
end if;
mcb3_enable1 <= mcb3_enable2;
end if;
end process;
-----------------------------------------------------------------------------
--read
-----------------------------------------------------------------------------
mcb3_dram_dqs_vector(1 downto 0) <= (mcb3_dram_udqs & mcb3_dram_dqs)
when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
else "ZZ";
mcb3_dram_dqs_n_vector(1 downto 0) <= (mcb3_dram_udqs_n & mcb3_dram_dqs_n)
when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
else "ZZ";
-----------------------------------------------------------------------------
--write
-----------------------------------------------------------------------------
mcb3_dram_dqs <= mcb3_dram_dqs_vector(0)
when ( mcb3_enable1 = '1') else 'Z';
mcb3_dram_udqs <= mcb3_dram_dqs_vector(1)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_dqs_n <= mcb3_dram_dqs_n_vector(0)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_udqs_n <= mcb3_dram_dqs_n_vector(1)
when (mcb3_enable1 = '1') else 'Z';
mcb1_dram_dm_vector <= (mcb1_dram_udm & mcb1_dram_dm);
u_mem_c1 : ddr3_model_c1 port map
(
ck => mcb1_dram_ck,
ck_n => mcb1_dram_ck_n,
cke => mcb1_dram_cke,
cs_n => '0',
ras_n => mcb1_dram_ras_n,
cas_n => mcb1_dram_cas_n,
we_n => mcb1_dram_we_n,
dm_tdqs => mcb1_dram_dm_vector,
ba => mcb1_dram_ba,
addr => mcb1_dram_a,
dq => mcb1_dram_dq,
dqs => mcb1_dram_dqs_vector,
dqs_n => mcb1_dram_dqs_n_vector,
tdqs_n => open,
odt => mcb1_dram_odt,
rst_n => mcb1_dram_reset_n
);
mcb3_dram_dm_vector <= (mcb3_dram_udm & mcb3_dram_dm);
u_mem_c3 : ddr3_model_c3 port map
(
ck => mcb3_dram_ck,
ck_n => mcb3_dram_ck_n,
cke => mcb3_dram_cke,
cs_n => '0',
ras_n => mcb3_dram_ras_n,
cas_n => mcb3_dram_cas_n,
we_n => mcb3_dram_we_n,
dm_tdqs => mcb3_dram_dm_vector,
ba => mcb3_dram_ba,
addr => mcb3_dram_a,
dq => mcb3_dram_dq,
dqs => mcb3_dram_dqs_vector,
dqs_n => mcb3_dram_dqs_n_vector,
tdqs_n => open,
odt => mcb3_dram_odt,
rst_n => mcb3_dram_reset_n
);
-----------------------------------------------------------------------------
-- Reporting the test case status
-----------------------------------------------------------------------------
Logging: process
begin
wait for 200 us;
if (calib_done = '1') then
if (error = '0') then
report ("****TEST PASSED****");
else
report ("****TEST FAILED: DATA ERROR****");
end if;
else
report ("****TEST FAILED: INITIALIZATION DID NOT COMPLETE****");
end if;
end process;
end architecture;
| gpl-3.0 | 059fa2a8e509f61bc9389559c968a7ba | 0.467238 | 3.434445 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/pcie_core/simulation/dsport/pci_exp_usrapp_rx.vhd | 1 | 28,093 | -------------------------------------------------------------------------------
--
-- (c) Copyright 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : pci_exp_usrapp_rx.vhd
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity pci_exp_usrapp_rx is
generic (
TRN_RX_TIMEOUT : INTEGER :=10000
);
port (
trn_rdst_rdy_n : out std_logic;
trn_rnp_ok_n : out std_logic;
trn_rd : in std_logic_vector ((64 - 1) downto 0 );
trn_rrem_n : in std_logic_vector ((8 - 1) downto 0 );
trn_rsof_n : in std_logic;
trn_reof_n : in std_logic;
trn_rsrc_rdy_n : in std_logic;
trn_rsrc_dsc_n : in std_logic;
trn_rerrfwd_n : in std_logic;
trn_rbar_hit_n : in std_logic_vector ((7 - 1) downto 0 );
trn_clk : in std_logic;
trn_reset_n : in std_logic;
trn_lnk_up_n : in std_logic;
--sim_time : in TIME;
rx_tx_read_data : out std_logic_vector(31 downto 0);
rx_tx_read_data_valid : out std_logic;
tx_rx_read_data_valid : in std_logic
);
end pci_exp_usrapp_rx;
architecture rtl of pci_exp_usrapp_rx is
type BYTE_ARRAY is array (999 downto 0) of std_logic_vector(7 downto 0);
constant TRN_RX_RESET : std_logic_vector(4 downto 0) := "00001";
constant TRN_RX_DOWN : std_logic_vector(4 downto 0) := "00010";
constant TRN_RX_IDLE : std_logic_vector(4 downto 0) := "00100";
constant TRN_RX_ACTIVE : std_logic_vector(4 downto 0) := "01000";
constant TRN_RX_SRC_DSC : std_logic_vector(4 downto 0) := "10000";
constant PCI_EXP_MEM_READ32 : std_logic_vector(6 downto 0) := "0000000";
constant PCI_EXP_IO_READ : std_logic_vector(6 downto 0) := "0000010";
constant PCI_EXP_CFG_READ0 : std_logic_vector(6 downto 0) := "0000100";
constant PCI_EXP_COMPLETION_WO_DATA : std_logic_vector(6 downto 0) := "0001010";
constant PCI_EXP_MEM_READ64 : std_logic_vector(6 downto 0) := "0100000";
constant PCI_EXP_MSG_NODATA : std_logic_vector(6 downto 3) := "0110";
constant PCI_EXP_MEM_WRITE32 : std_logic_vector(6 downto 0) := "1000000";
constant PCI_EXP_IO_WRITE : std_logic_vector(6 downto 0) := "1000010";
constant PCI_EXP_CFG_WRITE0 : std_logic_vector(6 downto 0) := "1000100";
constant PCI_EXP_COMPLETION_DATA : std_logic_vector(6 downto 0) := "1001010";
constant PCI_EXP_MEM_WRITE64 : std_logic_vector(6 downto 0) := "1100000";
constant PCI_EXP_MSG_DATA : std_logic_vector(6 downto 3) := "1110";
constant COMPLETER_ID_CFG : std_logic_vector(15 downto 0) := X"01A0";
-- Global variables
shared variable frame_store_rx : BYTE_ARRAY;
shared variable frame_store_rx_idx : INTEGER;
shared variable next_trn_rx_timeout : INTEGER;
signal trn_rdst_rdy_n_c : std_logic;
signal trn_rnp_ok_n_c : std_logic;
signal read_data_valid_int : std_logic;
signal read_data_valid_int_d : std_logic; -- added to prevent race condition
signal trn_rx_state : std_logic_vector(4 downto 0);
file RX_file : TEXT open write_mode is "rx.dat";
--************************************************************
-- Proc : writeNowToRx
-- Inputs : Text String
-- Outputs : None
-- Description : Displays text string to Rx file pre-appended with
-- current simulation time..
-- *************************************************************/
procedure writeNowToRx (
text_string : in string
) is
variable L : line;
begin
write (L, String'("[ "));
write (L, now);
write (L, String'(" ] : "));
write (L, text_string);
writeline (rx_file, L);
end writeNowToRx;
--************************************************************
-- Proc : writeNowToScreen
-- Inputs : Text String
-- Outputs : None
-- Description : Displays current simulation time and text string to
-- standard output.
-- *************************************************************
procedure writeNowToScreen (
text_string : in string
) is
variable L : line;
begin
write (L, String'("[ "));
write (L, now);
write (L, String'(" ] : "));
write (L, text_string);
writeline (output, L);
end writeNowToScreen;
--************************************************************
-- Proc : writeHexToRx
-- Inputs : hex value with bit width that is multiple of 4
-- Outputs : None
-- Description : Displays nibble aligned hex value to Rx file
--
-- *************************************************************
procedure writeHexToRx (
text_string : in string;
hexValue : in std_logic_vector
) is
variable L : line;
begin
write (L, text_string);
hwrite(L, hexValue);
writeline (rx_file, L);
end writeHexToRx;
--************************************************************
-- Proc : PROC_READ_DATA
-- Inputs : None
-- Outputs : None
-- Description : Consume clocks.
-- *************************************************************/
procedure PROC_READ_DATA (
last : in INTEGER;
trn_d : in std_logic_vector (63 downto 0);
trn_rem : in std_logic_vector (7 downto 0)
) is
variable i : INTEGER;
variable data_byte : std_logic_vector (7 downto 0);
variable remain : INTEGER;
variable hi_index : INTEGER;
variable low_index : INTEGER;
variable my_line : line;
begin
hi_index := 63;
low_index := 56;
if (last = 1) then
if (trn_rem = X"0F") then
remain := 4;
else
remain := 8;
end if;
else
remain := 8;
end if;
for i in 0 to (remain - 1) loop
data_byte := trn_d( hi_index downto low_index);
hi_index := hi_index - 8;
low_index := low_index - 8;
frame_store_rx(frame_store_rx_idx) := data_byte;
frame_store_rx_idx := frame_store_rx_idx + 1;
end loop;
end PROC_READ_DATA;
--************************************************************
-- Proc : PROC_DECIPHER_FRAME
-- Inputs : None
-- Outputs : fmt, tlp_type, traffic_class, td, ep, attr, length
-- Description : Deciphers frame
-- *************************************************************/
procedure PROC_DECIPHER_FRAME (
fmt : out std_logic_vector (1 downto 0);
tlp_type : out std_logic_vector (4 downto 0);
traffic_class : out std_logic_vector (2 downto 0);
td : out std_logic;
ep : out std_logic;
attr : out std_logic_vector (1 downto 0);
length : out std_logic_vector (9 downto 0)
) is
begin
fmt := frame_store_rx(0)(6 downto 5);
tlp_type := frame_store_rx(0)(4 downto 0);
traffic_class := frame_store_rx(1)(6 downto 4);
td := frame_store_rx(2)(7);
ep := frame_store_rx(2)(6);
attr := frame_store_rx(2)(5 downto 4);
length(9 downto 8) := frame_store_rx(2)(1 downto 0);
length(7 downto 0) := frame_store_rx(3);
end PROC_DECIPHER_FRAME;
-- ************************************************************
-- Proc : PROC_3DW
-- Inputs : fmt, type, traffic_class, td, ep, attr, length,
-- payload,
-- Outputs : None
-- Description : Gets variables and prints frame
-- *************************************************************/
procedure PROC_3DW (
fmt : in std_logic_vector (1 downto 0);
tlp_type : in std_logic_vector (4 downto 0);
traffic_class : in std_logic_vector (2 downto 0);
td : in std_logic;
ep : in std_logic;
attr : in std_logic_vector (1 downto 0);
length : in std_logic_vector (9 downto 0);
payload : in INTEGER;
signal rx_tx_read_data : out std_logic_vector(31 downto 0);
signal read_data_valid_int : out std_logic
) is
variable requester_id : std_logic_vector (15 downto 0);
variable tag : std_logic_vector (7 downto 0);
variable byte_enables : std_logic_vector (7 downto 0);
variable address_low : std_logic_vector (31 downto 0);
variable completer_id : std_logic_vector (15 downto 0);
variable register_address : std_logic_vector (9 downto 0);
variable completion_status : std_logic_vector (2 downto 0);
variable i : INTEGER;
variable L : line;
variable fmt_type : std_logic_vector (6 downto 0);
begin
writeHexToRx (String'(" Traffic Class: 0x"), '0' & traffic_class);
write (L, String'(" TD: ")); write(L, td); writeline (rx_file, L);
write (L, String'(" EP: ")); write(L, ep); writeline (rx_file, L);
writeHexToRx (String'(" Attributes: 0x"), "00" & attr);
writeHexToRx (String'(" Length: 0x"), "00" & length);
fmt_type := fmt & tlp_type;
case (fmt_type) is
when PCI_EXP_CFG_READ0 | PCI_EXP_CFG_WRITE0 =>
requester_id := frame_store_rx(4) & frame_store_rx(5);
tag := frame_store_rx(6);
byte_enables := frame_store_rx(7);
completer_id := frame_store_rx(8) & frame_store_rx(9);
register_address(9 downto 8) := frame_store_rx(10)(1 downto 0);
register_address(7 downto 0) := frame_store_rx(11);
writeHexToRx ( String'(" Requester Id: 0x"), requester_id);
writeHexToRx ( String'(" Tag: 0x"), tag);
writeHexToRx ( String'(" Last and First Byte Enables: 0x"), byte_enables);
writeHexToRx ( String'(" Completer Id: 0x"), completer_id);
writeHexToRx (String'(" Register Address: 0x"), "00" & register_address);
if (payload = 1) then
write (L, String'("")); writeline(rx_file, L);
for i in 12 to (frame_store_rx_idx - 1) loop
writeHexToRx ( String'(" 0x"), frame_store_rx(i));
end loop;
end if;
write (L, String'("")); writeline(rx_file, L);
when PCI_EXP_COMPLETION_WO_DATA | PCI_EXP_COMPLETION_DATA=>
completer_id := frame_store_rx(4) & frame_store_rx(5);
completion_status(2 downto 0) := frame_store_rx(6)(7 downto 5);
requester_id := frame_store_rx(8) & frame_store_rx(9);
tag := frame_store_rx(10);
writeHexToRx ( String'(" Completer Id: 0x"), completer_id);
writeHexToRx ( String'(" Completion Status: 0x"), '0' & completion_status);
writeHexToRx ( String'(" Requester Id: 0x"), requester_id);
writeHexToRx ( String'(" Tag: 0x"), tag);
if (payload = 1) then
write (L, String'("")); writeline(rx_file, L);
for i in 12 to (frame_store_rx_idx - 1) loop
writeHexToRx ( String'(" 0x"), frame_store_rx(i));
end loop;
rx_tx_read_data <= frame_store_rx(15) & frame_store_rx(14) &
frame_store_rx(13) & frame_store_rx(12);
read_data_valid_int <= '1';
end if;
write (L, String'("")); writeline(rx_file, L);
when others =>
requester_id := frame_store_rx(4) & frame_store_rx(5);
tag := frame_store_rx(6);
byte_enables := frame_store_rx(7);
address_low(31 downto 24) := frame_store_rx(8);
address_low(23 downto 16) := frame_store_rx(9);
address_low(15 downto 8) := frame_store_rx(10);
address_low( 7 downto 0) := frame_store_rx(11);
writeHexToRx ( String'(" Requester Id: 0x"), requester_id);
writeHexToRx ( String'(" Tag: 0x"), tag);
writeHexToRx ( String'(" Last and First Byte Enables: 0x"), byte_enables);
writeHexToRx ( String'(" Address Low: 0x"), address_low);
if (payload = 1) then
write (L, String'("")); writeline(rx_file, L);
for i in 12 to (frame_store_rx_idx - 1) loop
writeHexToRx ( String'(" 0x"), frame_store_rx(i));
end loop;
end if;
write (L, String'("")); writeline(rx_file, L);
end case;
end PROC_3DW;
-- ************************************************************
-- Proc : PROC_4DW
-- Inputs : fmt, type, traffic_class, td, ep, attr, length
-- payload
-- Outputs : None
-- Description : Gets variables and prints frame
-- *************************************************************/
procedure PROC_4DW (
fmt : in std_logic_vector (1 downto 0);
tlp_type : in std_logic_vector (4 downto 0);
traffic_class : in std_logic_vector (2 downto 0);
td : in std_logic;
ep : in std_logic;
attr : in std_logic_vector (1 downto 0);
length : in std_logic_vector (9 downto 0);
payload : in INTEGER
) is
variable requester_id : std_logic_vector (15 downto 0);
variable tag : std_logic_vector (7 downto 0);
variable byte_enables : std_logic_vector (7 downto 0);
variable message_code : std_logic_vector (7 downto 0);
variable address_high : std_logic_vector (31 downto 0);
variable address_low : std_logic_vector (31 downto 0);
variable msg_type : std_logic_vector (2 downto 0);
variable i : INTEGER;
variable L : line;
variable fmt_type : std_logic_vector (6 downto 0);
begin
writeHexToRx (String'(" Traffic Class: 0x"), '0' & traffic_class);
write (L, String'(" TD: ")); write(L, td); writeline (rx_file, L);
write (L, String'(" EP: ")); write(L, ep); writeline (rx_file, L);
writeHexToRx (String'(" Attributes: 0x"), "00" & attr);
writeHexToRx (String'(" Length: 0x"), "00" & length);
requester_id := frame_store_rx(4) & frame_store_rx(5);
tag := frame_store_rx(6);
byte_enables := frame_store_rx(7);
message_code := frame_store_rx(7);
address_high(31 downto 24) := frame_store_rx(8);
address_high(23 downto 16) := frame_store_rx(9) ;
address_high(15 downto 8) := frame_store_rx(10);
address_high(7 downto 0) := frame_store_rx(11);
address_low(31 downto 24) := frame_store_rx(12);
address_low(23 downto 16) := frame_store_rx(13);
address_low(15 downto 8) := frame_store_rx(14) ;
address_low(7 downto 0) := frame_store_rx(15);
writeHexToRx ( String'(" Requester Id: 0x"), requester_id);
writeHexToRx ( String'(" Tag: 0x"), tag);
fmt_type := fmt & tlp_type;
if ((fmt_type(6 downto 3) = PCI_EXP_MSG_NODATA)
or (fmt_type(6 downto 3) = PCI_EXP_MSG_DATA)) then
msg_type := tlp_type(2 downto 0);
writeHexToRx ( String'(" Message Type: 0x"), '0' & msg_type);
writeHexToRx ( String'(" Message Code: 0x"), message_code);
writeHexToRx ( String'(" Address High: 0x"), address_high);
writeHexToRx ( String'(" Address Low: 0x"), address_low);
if (payload = 1) then
write (L, String'("")); writeline(rx_file, L);
for i in 16 to (frame_store_rx_idx - 1) loop
writeHexToRx ( String'(" 0x"), frame_store_rx(i));
end loop;
end if;
write (L, String'("")); writeline(rx_file, L);
else
case (fmt_type) is
when PCI_EXP_MEM_READ64 | PCI_EXP_MEM_WRITE64 =>
writeHexToRx ( String'(" Last and First Byte Enables: 0x"), byte_enables);
writeHexToRx ( String'(" Address High: 0x"), address_high);
writeHexToRx ( String'(" Address Low: 0x"), address_low);
if (payload = 1) then
write (L, String'("")); writeline(rx_file, L);
for i in 16 to (frame_store_rx_idx - 1) loop
writeHexToRx ( String'(" 0x"), frame_store_rx(i));
end loop;
end if;
write (L, String'("")); writeline(rx_file, L);
when others =>
write (L, String'(": Not a vaild frame")); writeline (rx_file, L); write (L, String'("")); writeline(rx_file, L);
assert (false)
report "Simulation Ended"
severity failure;
end case;
end if;
end PROC_4DW;
--************************************************************
-- Proc : PROC_PARSE_FRAME
-- Inputs : None
-- Outputs : None
-- Description : Parse frame data
-- *************************************************************/
procedure PROC_PARSE_FRAME (
signal rx_tx_read_data : out std_logic_vector(31 downto 0);
signal read_data_valid_int : out std_logic
) is
variable fmt : std_logic_vector (1 downto 0);
variable tlp_type : std_logic_vector (4 downto 0);
variable traffic_class : std_logic_vector (2 downto 0);
variable td : std_logic;
variable ep : std_logic;
variable attr : std_logic_vector (1 downto 0);
variable length : std_logic_vector (9 downto 0);
variable payload : INTEGER;
variable reqester_id : std_logic_vector(15 downto 0);
variable completer_id : std_logic_vector(15 downto 0);
variable tag : std_logic_vector(7 downto 0);
variable byte_enables : std_logic_vector(7 downto 0);
variable message_code : std_logic_vector(7 downto 0);
variable address_low : std_logic_vector(31 downto 0);
variable address_high : std_logic_vector(31 downto 0);
variable register_address : std_logic_vector (9 downto 0);
variable completion_status : std_logic_vector (2 downto 0);
variable log_file_ptr : std_logic_vector (31 downto 0);
variable frame_store_idx : INTEGER;
variable fmt_type : std_logic_vector (6 downto 0);
variable L : line;
begin
writeNowToScreen ( String'("PROC_PARSE_FRAME on Receive"));
PROC_DECIPHER_FRAME (fmt, tlp_type, traffic_class, td, ep, attr, length);
-- decode the packets received based on fmt and type
fmt_type := fmt & tlp_type;
if (fmt_type(6 downto 3) = PCI_EXP_MSG_NODATA) then
writeNowToRx("Message With No Data Frame");
payload := 0;
PROC_4DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload);
elsif (fmt_type(6 downto 3) = PCI_EXP_MSG_DATA) then
writeNowToRx("Message With Data Frame");
payload := 1;
PROC_4DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload);
else
case (fmt_type) is
when PCI_EXP_MEM_READ32 =>
writeNowToRx("Memory Read-32 Frame");
payload := 0;
PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload, rx_tx_read_data, read_data_valid_int );
when PCI_EXP_IO_READ =>
writeNowToRx("IO Read Frame");
payload := 0;
PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload, rx_tx_read_data, read_data_valid_int );
when PCI_EXP_CFG_READ0 =>
writeNowToRx("Config Read Type 0 Frame");
payload := 0;
PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload, rx_tx_read_data, read_data_valid_int );
when PCI_EXP_COMPLETION_WO_DATA =>
writeNowToRx("Completion Without Data Frame");
payload := 0;
PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload, rx_tx_read_data, read_data_valid_int );
when PCI_EXP_MEM_READ64 =>
writeNowToRx("Memory Read-64 Frame");
payload := 0;
PROC_4DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload); --, rx_tx_read_data, rx_tx_read_data_valid );
when PCI_EXP_MEM_WRITE32 =>
writeNowToRx("Memory Write-32 Frame");
payload := 1;
PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload, rx_tx_read_data, read_data_valid_int );
when PCI_EXP_IO_WRITE =>
writeNowToRx("IO Write Frame");
payload := 1;
PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload, rx_tx_read_data, read_data_valid_int );
when PCI_EXP_CFG_WRITE0 =>
writeNowToRx("Config Write Type 0 Frame");
payload := 1;
PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload, rx_tx_read_data, read_data_valid_int );
when PCI_EXP_COMPLETION_DATA =>
writeNowToRx("Completion With Data Frame");
payload := 1;
PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload, rx_tx_read_data, read_data_valid_int );
when PCI_EXP_MEM_WRITE64 =>
writeNowToRx("Memory Write-64 Frame");
payload := 1;
PROC_4DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload);
when others =>
writeNowToRx("Not a vaild frame. fmt_type = ");
write (L, fmt_type);
writeline (rx_file, L);
assert (false)
report "Simulation Ended"
severity failure;
end case;
end if;
frame_store_rx_idx := 0; -- reset frame pointer
end PROC_PARSE_FRAME;
begin
trn_rdst_rdy_n <= trn_rdst_rdy_n_c;
trn_rnp_ok_n <= '0';
trn_rdst_rdy_n_c <= '0';
-- Transaction Receive User Interface State Machine
process (trn_clk, trn_reset_n)
begin
if (trn_reset_n = '0' ) then
trn_rx_state <= TRN_RX_RESET;
frame_store_rx_idx := 0;
rx_tx_read_data <= X"FFFFFFFF";
read_data_valid_int <= '0';
else
if (trn_clk'event and trn_clk = '1') then
case (trn_rx_state) is
when TRN_RX_RESET =>
if (trn_reset_n = '0') then
trn_rx_state <= TRN_RX_RESET;
else
trn_rx_state <= TRN_RX_DOWN;
end if;
when TRN_RX_DOWN =>
if (trn_lnk_up_n = '1') then
trn_rx_state <= TRN_RX_DOWN;
else
trn_rx_state <= TRN_RX_IDLE;
end if;
when TRN_RX_IDLE =>
read_data_valid_int <= '0';
if (trn_reset_n = '0') then
trn_rx_state <= TRN_RX_RESET;
elsif (trn_lnk_up_n = '1') then
trn_rx_state <= TRN_RX_DOWN;
elsif ((trn_rsof_n = '0') and (trn_rsrc_rdy_n = '0') and (trn_rdst_rdy_n_c = '0')) then
PROC_READ_DATA (0, trn_rd, trn_rrem_n);
trn_rx_state <= TRN_RX_ACTIVE;
else
trn_rx_state <= TRN_RX_IDLE;
end if;
when TRN_RX_ACTIVE =>
if (trn_reset_n = '0') then
trn_rx_state <= TRN_RX_RESET;
elsif (trn_lnk_up_n = '1') then
trn_rx_state <= TRN_RX_DOWN;
elsif ((trn_rsrc_rdy_n = '0') and (trn_reof_n = '0') and (trn_rdst_rdy_n_c = '0')) then
PROC_READ_DATA (1, trn_rd, trn_rrem_n);
PROC_PARSE_FRAME (rx_tx_read_data , read_data_valid_int);
trn_rx_state <= TRN_RX_IDLE;
elsif ((trn_rsrc_rdy_n = '0') and (trn_rdst_rdy_n_c = '0')) then
PROC_READ_DATA (0, trn_rd, trn_rrem_n);
trn_rx_state <= TRN_RX_ACTIVE;
elsif ((trn_rsrc_rdy_n = '0') and (trn_reof_n = '0') and (trn_rsrc_dsc_n = '0')) then
PROC_READ_DATA (1, trn_rd, trn_rrem_n);
PROC_PARSE_FRAME (rx_tx_read_data , read_data_valid_int);
trn_rx_state <= TRN_RX_SRC_DSC;
else
trn_rx_state <= TRN_RX_ACTIVE;
end if;
when TRN_RX_SRC_DSC =>
if (trn_reset_n = '0') then
trn_rx_state <= TRN_RX_RESET;
elsif (trn_lnk_up_n = '1') then
trn_rx_state <= TRN_RX_DOWN;
else
trn_rx_state <= TRN_RX_IDLE;
end if;
when others =>
trn_rx_state <= TRN_RX_RESET;
end case;
end if;
end if;
end process;
process (trn_clk, trn_reset_n)
begin
if (trn_reset_n = '0' ) then
next_trn_rx_timeout := TRN_RX_TIMEOUT;
else
if (trn_clk'event and trn_clk = '1') then
if (next_trn_rx_timeout = 0) then
assert (false)
report "RX Simulation Timeout."
severity failure;
elsif (trn_lnk_up_n = '0') then
next_trn_rx_timeout := next_trn_rx_timeout - 1;
end if;
end if;
end if;
end process;
-- Following is used to allow rx to tx communication to occur over two trn clocks - avoiding race conditions
process (trn_clk)
begin
if (trn_clk'event and trn_clk = '1') then
read_data_valid_int_d <= read_data_valid_int;
end if;
end process;
process (trn_clk)
begin
if (trn_clk'event and trn_clk = '1') then
if (trn_lnk_up_n = '0') then
if ((tx_rx_read_data_valid = '1' ) and ((read_data_valid_int = '1') or (read_data_valid_int_d = '1'))) then
rx_tx_read_data_valid <= '1';
else
rx_tx_read_data_valid <= '0';
end if;
end if;
end if;
end process;
end; -- pci_exp_usrapp_rx
| gpl-3.0 | f0624bb506872a614b826739b0b496ee | 0.540882 | 3.533266 | false | false | false | false |
Nixon-/VHDL_library | processing/to_test/nbit_basic_alu.vhd | 1 | 1,251 | Library ieee;
use ieee.std_logic_1164.all;
entity nbit_basic_alu is
generic (bitsPerVector: integer:=4);
port(
enable : in std_logic;
opA : in std_logic_vector(bitsPerVector-1 downto 0);
opB : in std_logic_vector(bitsPerVector-1 downto 0);
result: out std_logic_vector(bitsPerVector-1 downto 0);
selector: in std_logic_vector(1 downto 0);
c_out: out std_logic;
c_in: in std_logic
);
end nbit_basic_alu;
architecture primary of nbit_basic_alu is
signal temp_res: std_logic_vector(bitsPerVector downto 0);
begin
process(opA,opB,enable,selector,temp_res)
variable opA_int,opB_int,res_int: integer;
begin
if(enable = '1') then
opA_int := to_integer(signed(opA));
opB_int := to_integer(signed(opB));
if(selector = "00") then
res_int := opA_int;
elsif(selector = "01) then
res_int := opA_int+1;
elsif(selector = "10") then
res_int := opA_int - opB_int -1;
elsif(selector = "11") then
res_int := opA_int - opB_int;
end if
res_int := res_int + to_integer(unsigned(c+in));
temp_res <= std_logic_vector(to_signed(res_int,bitsPerVector));
c_out <= temp_res(bitsPerVector);
result <= temp_res(bitsPerVector-1 downto 0);
else
result<= (others => '0');
c_out <= '0';
end if
end process;
end primary;
| gpl-2.0 | 08290c29f97e77cfffe2cd576db9e818 | 0.67546 | 2.869266 | false | false | false | false |
JavierRizzoA/Sacagawea | sources/ALU.vhd | 1 | 1,542 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:20:02 06/05/2016
-- Design Name:
-- Module Name: ALU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU is
port (s_muxa, s_muxb : in std_logic_vector(7 downto 0);
ctrl_alu : in std_logic_vector(3 downto 0);
s_alu : out std_logic_vector(7 downto 0);
flags : out std_logic_vector(2 downto 0)
);
end ALU;
architecture Behavioral of ALU is
signal result: signed(15 downto 0);
signal A, B : signed(15 downto 0);
begin
A <= signed("00000000" & s_muxa);
B <= signed("00000000" & s_muxb);
with ctrl_alu select
result <= B when "0000",
A + B when "0001",
A - B when "0010",
signed(s_muxa) * signed(s_muxb) when "0011",
A / B when "0100",
A and B when "0101",
A or B when "0110",
not A when "0111",
A srl 1 when "1000",
A sll 1 when "1001",
A + 1 when "1010",
A - 1 when "1011",
"XXXXXXXXXXXXXXXX" when others;
s_alu <= std_logic_vector(result(7 downto 0));
flags <= "001" when ((result(7 downto 0)) = "00000000") else
"010" when (result(7) = '1') else
"100";
end Behavioral; | mit | 4a959e7f09fa6ff2085977079715441d | 0.540208 | 3.19917 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/ddr3_controller/user_design/rtl/ddr3_controller.vhd | 1 | 59,790 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.9
-- \ \ Application : MIG
-- / / Filename : ddr3_controller.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:59 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This is the design top level. which instantiates top wrapper,
-- test bench top and infrastructure modules.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity ddr3_controller is
generic
(
C1_P0_MASK_SIZE : integer := 4;
C1_P0_DATA_PORT_SIZE : integer := 32;
C1_P1_MASK_SIZE : integer := 4;
C1_P1_DATA_PORT_SIZE : integer := 32;
C1_MEMCLK_PERIOD : integer := 2500;
-- Memory data transfer clock period.
C1_RST_ACT_LOW : integer := 0;
-- # = 1 for active low reset,
-- # = 0 for active high reset.
C1_INPUT_CLK_TYPE : string := "DIFFERENTIAL";
-- input clock type DIFFERENTIAL or SINGLE_ENDED.
C1_CALIB_SOFT_IP : string := "TRUE";
-- # = TRUE, Enables the soft calibration logic,
-- # = FALSE, Disables the soft calibration logic.
C1_SIMULATION : string := "FALSE";
-- # = TRUE, Simulating the design. Useful to reduce the simulation time,
-- # = FALSE, Implementing the design.
DEBUG_EN : integer := 0;
-- # = 1, Enable debug signals/controls,
-- = 0, Disable debug signals/controls.
C1_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
-- The order in which user address is provided to the memory controller,
-- ROW_BANK_COLUMN or BANK_ROW_COLUMN.
C1_NUM_DQ_PINS : integer := 16;
-- External memory data width.
C1_MEM_ADDR_WIDTH : integer := 14;
-- External memory address width.
C1_MEM_BANKADDR_WIDTH : integer := 3;
-- External memory bank address width.
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 2500;
-- Memory data transfer clock period.
C3_RST_ACT_LOW : integer := 0;
-- # = 1 for active low reset,
-- # = 0 for active high reset.
C3_INPUT_CLK_TYPE : string := "DIFFERENTIAL";
-- input clock type DIFFERENTIAL or SINGLE_ENDED.
C3_CALIB_SOFT_IP : string := "TRUE";
-- # = TRUE, Enables the soft calibration logic,
-- # = FALSE, Disables the soft calibration logic.
C3_SIMULATION : string := "FALSE";
-- # = TRUE, Simulating the design. Useful to reduce the simulation time,
-- # = FALSE, Implementing the design.
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
-- The order in which user address is provided to the memory controller,
-- ROW_BANK_COLUMN or BANK_ROW_COLUMN.
C3_NUM_DQ_PINS : integer := 16;
-- External memory data width.
C3_MEM_ADDR_WIDTH : integer := 14;
-- External memory address width.
C3_MEM_BANKADDR_WIDTH : integer := 3
-- External memory bank address width.
);
port
(
mcb1_dram_dq : inout std_logic_vector(C1_NUM_DQ_PINS-1 downto 0);
mcb1_dram_a : out std_logic_vector(C1_MEM_ADDR_WIDTH-1 downto 0);
mcb1_dram_ba : out std_logic_vector(C1_MEM_BANKADDR_WIDTH-1 downto 0);
mcb1_dram_ras_n : out std_logic;
mcb1_dram_cas_n : out std_logic;
mcb1_dram_we_n : out std_logic;
mcb1_dram_odt : out std_logic;
mcb1_dram_reset_n : out std_logic;
mcb1_dram_cke : out std_logic;
mcb1_dram_dm : out std_logic;
mcb1_dram_udqs : inout std_logic;
mcb1_dram_udqs_n : inout std_logic;
mcb1_rzq : inout std_logic;
mcb1_zio : inout std_logic;
mcb1_dram_udm : out std_logic;
c1_sys_clk_p : in std_logic;
c1_sys_clk_n : in std_logic;
c1_sys_rst_i : in std_logic;
c1_calib_done : out std_logic;
c1_clk0 : out std_logic;
c1_rst0 : out std_logic;
mcb1_dram_dqs : inout std_logic;
mcb1_dram_dqs_n : inout std_logic;
mcb1_dram_ck : out std_logic;
mcb1_dram_ck_n : out std_logic;
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_reset_n : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
c3_sys_clk_p : in std_logic;
c3_sys_clk_n : in std_logic;
c3_sys_rst_i : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
c1_p0_cmd_clk : in std_logic;
c1_p0_cmd_en : in std_logic;
c1_p0_cmd_instr : in std_logic_vector(2 downto 0);
c1_p0_cmd_bl : in std_logic_vector(5 downto 0);
c1_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c1_p0_cmd_empty : out std_logic;
c1_p0_cmd_full : out std_logic;
c1_p0_wr_clk : in std_logic;
c1_p0_wr_en : in std_logic;
c1_p0_wr_mask : in std_logic_vector(C1_P0_MASK_SIZE - 1 downto 0);
c1_p0_wr_data : in std_logic_vector(C1_P0_DATA_PORT_SIZE - 1 downto 0);
c1_p0_wr_full : out std_logic;
c1_p0_wr_empty : out std_logic;
c1_p0_wr_count : out std_logic_vector(6 downto 0);
c1_p0_wr_underrun : out std_logic;
c1_p0_wr_error : out std_logic;
c1_p0_rd_clk : in std_logic;
c1_p0_rd_en : in std_logic;
c1_p0_rd_data : out std_logic_vector(C1_P0_DATA_PORT_SIZE - 1 downto 0);
c1_p0_rd_full : out std_logic;
c1_p0_rd_empty : out std_logic;
c1_p0_rd_count : out std_logic_vector(6 downto 0);
c1_p0_rd_overflow : out std_logic;
c1_p0_rd_error : out std_logic;
c3_p0_cmd_clk : in std_logic;
c3_p0_cmd_en : in std_logic;
c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p0_cmd_empty : out std_logic;
c3_p0_cmd_full : out std_logic;
c3_p0_wr_clk : in std_logic;
c3_p0_wr_en : in std_logic;
c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_wr_full : out std_logic;
c3_p0_wr_empty : out std_logic;
c3_p0_wr_count : out std_logic_vector(6 downto 0);
c3_p0_wr_underrun : out std_logic;
c3_p0_wr_error : out std_logic;
c3_p0_rd_clk : in std_logic;
c3_p0_rd_en : in std_logic;
c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_rd_full : out std_logic;
c3_p0_rd_empty : out std_logic;
c3_p0_rd_count : out std_logic_vector(6 downto 0);
c3_p0_rd_overflow : out std_logic;
c3_p0_rd_error : out std_logic
);
end ddr3_controller;
architecture arc of ddr3_controller is
component memc1_infrastructure is
generic (
C_RST_ACT_LOW : integer;
C_INPUT_CLK_TYPE : string;
C_CLKOUT0_DIVIDE : integer;
C_CLKOUT1_DIVIDE : integer;
C_CLKOUT2_DIVIDE : integer;
C_CLKOUT3_DIVIDE : integer;
C_CLKFBOUT_MULT : integer;
C_DIVCLK_DIVIDE : integer;
C_INCLK_PERIOD : integer
);
port (
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_clk : in std_logic;
sys_rst_i : in std_logic;
clk0 : out std_logic;
rst0 : out std_logic;
async_rst : out std_logic;
sysclk_2x : out std_logic;
sysclk_2x_180 : out std_logic;
pll_ce_0 : out std_logic;
pll_ce_90 : out std_logic;
pll_lock : out std_logic;
mcb_drp_clk : out std_logic
);
end component;
component memc3_infrastructure is
generic (
C_RST_ACT_LOW : integer;
C_INPUT_CLK_TYPE : string;
C_CLKOUT0_DIVIDE : integer;
C_CLKOUT1_DIVIDE : integer;
C_CLKOUT2_DIVIDE : integer;
C_CLKOUT3_DIVIDE : integer;
C_CLKFBOUT_MULT : integer;
C_DIVCLK_DIVIDE : integer;
C_INCLK_PERIOD : integer
);
port (
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_clk : in std_logic;
sys_rst_i : in std_logic;
clk0 : out std_logic;
rst0 : out std_logic;
async_rst : out std_logic;
sysclk_2x : out std_logic;
sysclk_2x_180 : out std_logic;
pll_ce_0 : out std_logic;
pll_ce_90 : out std_logic;
pll_lock : out std_logic;
mcb_drp_clk : out std_logic
);
end component;
component memc1_wrapper is
generic (
C_MEMCLK_PERIOD : integer;
C_CALIB_SOFT_IP : string;
C_SIMULATION : string;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(2 downto 0);
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_MEM_ADDR_ORDER : string;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_DDR3_ODS : string;
C_MEM_DDR3_RTT : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_MOBILE_PA_SR : string;
C_MEM_MDDR_ODS : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_LDQSP_TAP_DELAY_VAL : integer;
C_LDQSN_TAP_DELAY_VAL : integer;
C_UDQSP_TAP_DELAY_VAL : integer;
C_UDQSN_TAP_DELAY_VAL : integer;
C_DQ0_TAP_DELAY_VAL : integer;
C_DQ1_TAP_DELAY_VAL : integer;
C_DQ2_TAP_DELAY_VAL : integer;
C_DQ3_TAP_DELAY_VAL : integer;
C_DQ4_TAP_DELAY_VAL : integer;
C_DQ5_TAP_DELAY_VAL : integer;
C_DQ6_TAP_DELAY_VAL : integer;
C_DQ7_TAP_DELAY_VAL : integer;
C_DQ8_TAP_DELAY_VAL : integer;
C_DQ9_TAP_DELAY_VAL : integer;
C_DQ10_TAP_DELAY_VAL : integer;
C_DQ11_TAP_DELAY_VAL : integer;
C_DQ12_TAP_DELAY_VAL : integer;
C_DQ13_TAP_DELAY_VAL : integer;
C_DQ14_TAP_DELAY_VAL : integer;
C_DQ15_TAP_DELAY_VAL : integer
);
port (
mcb1_dram_dq : inout std_logic_vector((C_NUM_DQ_PINS-1) downto 0);
mcb1_dram_a : out std_logic_vector((C_MEM_ADDR_WIDTH-1) downto 0);
mcb1_dram_ba : out std_logic_vector((C_MEM_BANKADDR_WIDTH-1) downto 0);
mcb1_dram_ras_n : out std_logic;
mcb1_dram_cas_n : out std_logic;
mcb1_dram_we_n : out std_logic;
mcb1_dram_odt : out std_logic;
mcb1_dram_reset_n : out std_logic;
mcb1_dram_cke : out std_logic;
mcb1_dram_dm : out std_logic;
mcb1_dram_udqs : inout std_logic;
mcb1_dram_udqs_n : inout std_logic;
mcb1_rzq : inout std_logic;
mcb1_zio : inout std_logic;
mcb1_dram_udm : out std_logic;
calib_done : out std_logic;
async_rst : in std_logic;
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
mcb_drp_clk : in std_logic;
mcb1_dram_dqs : inout std_logic;
mcb1_dram_dqs_n : inout std_logic;
mcb1_dram_ck : out std_logic;
mcb1_dram_ck_n : out std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 downto 0);
p0_cmd_bl : in std_logic_vector(5 downto 0);
p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 downto 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 downto 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
component memc3_wrapper is
generic (
C_MEMCLK_PERIOD : integer;
C_CALIB_SOFT_IP : string;
C_SIMULATION : string;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(2 downto 0);
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_MEM_ADDR_ORDER : string;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_DDR3_ODS : string;
C_MEM_DDR3_RTT : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_MOBILE_PA_SR : string;
C_MEM_MDDR_ODS : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_LDQSP_TAP_DELAY_VAL : integer;
C_LDQSN_TAP_DELAY_VAL : integer;
C_UDQSP_TAP_DELAY_VAL : integer;
C_UDQSN_TAP_DELAY_VAL : integer;
C_DQ0_TAP_DELAY_VAL : integer;
C_DQ1_TAP_DELAY_VAL : integer;
C_DQ2_TAP_DELAY_VAL : integer;
C_DQ3_TAP_DELAY_VAL : integer;
C_DQ4_TAP_DELAY_VAL : integer;
C_DQ5_TAP_DELAY_VAL : integer;
C_DQ6_TAP_DELAY_VAL : integer;
C_DQ7_TAP_DELAY_VAL : integer;
C_DQ8_TAP_DELAY_VAL : integer;
C_DQ9_TAP_DELAY_VAL : integer;
C_DQ10_TAP_DELAY_VAL : integer;
C_DQ11_TAP_DELAY_VAL : integer;
C_DQ12_TAP_DELAY_VAL : integer;
C_DQ13_TAP_DELAY_VAL : integer;
C_DQ14_TAP_DELAY_VAL : integer;
C_DQ15_TAP_DELAY_VAL : integer
);
port (
mcb3_dram_dq : inout std_logic_vector((C_NUM_DQ_PINS-1) downto 0);
mcb3_dram_a : out std_logic_vector((C_MEM_ADDR_WIDTH-1) downto 0);
mcb3_dram_ba : out std_logic_vector((C_MEM_BANKADDR_WIDTH-1) downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_reset_n : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
calib_done : out std_logic;
async_rst : in std_logic;
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
mcb_drp_clk : in std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 downto 0);
p0_cmd_bl : in std_logic_vector(5 downto 0);
p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 downto 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 downto 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
constant C1_CLKOUT0_DIVIDE : integer := 1;
constant C1_CLKOUT1_DIVIDE : integer := 1;
constant C1_CLKOUT2_DIVIDE : integer := 16;
constant C1_CLKOUT3_DIVIDE : integer := 8;
constant C1_CLKFBOUT_MULT : integer := 2;
constant C1_DIVCLK_DIVIDE : integer := 1;
constant C1_INCLK_PERIOD : integer := ((C1_MEMCLK_PERIOD * C1_CLKFBOUT_MULT) / (C1_DIVCLK_DIVIDE * C1_CLKOUT0_DIVIDE * 2));
constant C1_ARB_NUM_TIME_SLOTS : integer := 12;
constant C1_ARB_TIME_SLOT_0 : bit_vector(2 downto 0) := o"0";
constant C1_ARB_TIME_SLOT_1 : bit_vector(2 downto 0) := o"0";
constant C1_ARB_TIME_SLOT_2 : bit_vector(2 downto 0) := o"0";
constant C1_ARB_TIME_SLOT_3 : bit_vector(2 downto 0) := o"0";
constant C1_ARB_TIME_SLOT_4 : bit_vector(2 downto 0) := o"0";
constant C1_ARB_TIME_SLOT_5 : bit_vector(2 downto 0) := o"0";
constant C1_ARB_TIME_SLOT_6 : bit_vector(2 downto 0) := o"0";
constant C1_ARB_TIME_SLOT_7 : bit_vector(2 downto 0) := o"0";
constant C1_ARB_TIME_SLOT_8 : bit_vector(2 downto 0) := o"0";
constant C1_ARB_TIME_SLOT_9 : bit_vector(2 downto 0) := o"0";
constant C1_ARB_TIME_SLOT_10 : bit_vector(2 downto 0) := o"0";
constant C1_ARB_TIME_SLOT_11 : bit_vector(2 downto 0) := o"0";
constant C1_MEM_TRAS : integer := 36000;
constant C1_MEM_TRCD : integer := 13500;
constant C1_MEM_TREFI : integer := 7800000;
constant C1_MEM_TRFC : integer := 160000;
constant C1_MEM_TRP : integer := 13500;
constant C1_MEM_TWR : integer := 15000;
constant C1_MEM_TRTP : integer := 7500;
constant C1_MEM_TWTR : integer := 7500;
constant C1_MEM_TYPE : string := "DDR3";
constant C1_MEM_DENSITY : string := "2Gb";
constant C1_MEM_BURST_LEN : integer := 8;
constant C1_MEM_CAS_LATENCY : integer := 6;
constant C1_MEM_NUM_COL_BITS : integer := 10;
constant C1_MEM_DDR1_2_ODS : string := "FULL";
constant C1_MEM_DDR2_RTT : string := "50OHMS";
constant C1_MEM_DDR2_DIFF_DQS_EN : string := "YES";
constant C1_MEM_DDR2_3_PA_SR : string := "FULL";
constant C1_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
constant C1_MEM_DDR3_CAS_LATENCY : integer := 6;
constant C1_MEM_DDR3_ODS : string := "DIV6";
constant C1_MEM_DDR3_RTT : string := "DIV4";
constant C1_MEM_DDR3_CAS_WR_LATENCY : integer := 5;
constant C1_MEM_DDR3_AUTO_SR : string := "ENABLED";
constant C1_MEM_MOBILE_PA_SR : string := "FULL";
constant C1_MEM_MDDR_ODS : string := "FULL";
constant C1_MC_CALIB_BYPASS : string := "NO";
constant C1_MC_CALIBRATION_MODE : string := "CALIBRATION";
constant C1_MC_CALIBRATION_DELAY : string := "HALF";
constant C1_SKIP_IN_TERM_CAL : integer := 0;
constant C1_SKIP_DYNAMIC_CAL : integer := 0;
constant C1_LDQSP_TAP_DELAY_VAL : integer := 0;
constant C1_LDQSN_TAP_DELAY_VAL : integer := 0;
constant C1_UDQSP_TAP_DELAY_VAL : integer := 0;
constant C1_UDQSN_TAP_DELAY_VAL : integer := 0;
constant C1_DQ0_TAP_DELAY_VAL : integer := 0;
constant C1_DQ1_TAP_DELAY_VAL : integer := 0;
constant C1_DQ2_TAP_DELAY_VAL : integer := 0;
constant C1_DQ3_TAP_DELAY_VAL : integer := 0;
constant C1_DQ4_TAP_DELAY_VAL : integer := 0;
constant C1_DQ5_TAP_DELAY_VAL : integer := 0;
constant C1_DQ6_TAP_DELAY_VAL : integer := 0;
constant C1_DQ7_TAP_DELAY_VAL : integer := 0;
constant C1_DQ8_TAP_DELAY_VAL : integer := 0;
constant C1_DQ9_TAP_DELAY_VAL : integer := 0;
constant C1_DQ10_TAP_DELAY_VAL : integer := 0;
constant C1_DQ11_TAP_DELAY_VAL : integer := 0;
constant C1_DQ12_TAP_DELAY_VAL : integer := 0;
constant C1_DQ13_TAP_DELAY_VAL : integer := 0;
constant C1_DQ14_TAP_DELAY_VAL : integer := 0;
constant C1_DQ15_TAP_DELAY_VAL : integer := 0;
constant C1_SMALL_DEVICE : string := "FALSE"; -- The parameter is set to TRUE for all packages of xc6slx9 device
-- as most of them cannot fit the complete example design when the
-- Chip scope modules are enabled
constant C3_CLKOUT0_DIVIDE : integer := 1;
constant C3_CLKOUT1_DIVIDE : integer := 1;
constant C3_CLKOUT2_DIVIDE : integer := 16;
constant C3_CLKOUT3_DIVIDE : integer := 8;
constant C3_CLKFBOUT_MULT : integer := 2;
constant C3_DIVCLK_DIVIDE : integer := 1;
constant C3_INCLK_PERIOD : integer := ((C3_MEMCLK_PERIOD * C3_CLKFBOUT_MULT) / (C3_DIVCLK_DIVIDE * C3_CLKOUT0_DIVIDE * 2));
constant C3_ARB_NUM_TIME_SLOTS : integer := 12;
constant C3_ARB_TIME_SLOT_0 : bit_vector(2 downto 0) := o"0";
constant C3_ARB_TIME_SLOT_1 : bit_vector(2 downto 0) := o"0";
constant C3_ARB_TIME_SLOT_2 : bit_vector(2 downto 0) := o"0";
constant C3_ARB_TIME_SLOT_3 : bit_vector(2 downto 0) := o"0";
constant C3_ARB_TIME_SLOT_4 : bit_vector(2 downto 0) := o"0";
constant C3_ARB_TIME_SLOT_5 : bit_vector(2 downto 0) := o"0";
constant C3_ARB_TIME_SLOT_6 : bit_vector(2 downto 0) := o"0";
constant C3_ARB_TIME_SLOT_7 : bit_vector(2 downto 0) := o"0";
constant C3_ARB_TIME_SLOT_8 : bit_vector(2 downto 0) := o"0";
constant C3_ARB_TIME_SLOT_9 : bit_vector(2 downto 0) := o"0";
constant C3_ARB_TIME_SLOT_10 : bit_vector(2 downto 0) := o"0";
constant C3_ARB_TIME_SLOT_11 : bit_vector(2 downto 0) := o"0";
constant C3_MEM_TRAS : integer := 36000;
constant C3_MEM_TRCD : integer := 13500;
constant C3_MEM_TREFI : integer := 7800000;
constant C3_MEM_TRFC : integer := 160000;
constant C3_MEM_TRP : integer := 13500;
constant C3_MEM_TWR : integer := 15000;
constant C3_MEM_TRTP : integer := 7500;
constant C3_MEM_TWTR : integer := 7500;
constant C3_MEM_TYPE : string := "DDR3";
constant C3_MEM_DENSITY : string := "2Gb";
constant C3_MEM_BURST_LEN : integer := 8;
constant C3_MEM_CAS_LATENCY : integer := 6;
constant C3_MEM_NUM_COL_BITS : integer := 10;
constant C3_MEM_DDR1_2_ODS : string := "FULL";
constant C3_MEM_DDR2_RTT : string := "50OHMS";
constant C3_MEM_DDR2_DIFF_DQS_EN : string := "YES";
constant C3_MEM_DDR2_3_PA_SR : string := "FULL";
constant C3_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
constant C3_MEM_DDR3_CAS_LATENCY : integer := 6;
constant C3_MEM_DDR3_ODS : string := "DIV6";
constant C3_MEM_DDR3_RTT : string := "DIV4";
constant C3_MEM_DDR3_CAS_WR_LATENCY : integer := 5;
constant C3_MEM_DDR3_AUTO_SR : string := "ENABLED";
constant C3_MEM_MOBILE_PA_SR : string := "FULL";
constant C3_MEM_MDDR_ODS : string := "FULL";
constant C3_MC_CALIB_BYPASS : string := "NO";
constant C3_MC_CALIBRATION_MODE : string := "CALIBRATION";
constant C3_MC_CALIBRATION_DELAY : string := "HALF";
constant C3_SKIP_IN_TERM_CAL : integer := 0;
constant C3_SKIP_DYNAMIC_CAL : integer := 0;
constant C3_LDQSP_TAP_DELAY_VAL : integer := 0;
constant C3_LDQSN_TAP_DELAY_VAL : integer := 0;
constant C3_UDQSP_TAP_DELAY_VAL : integer := 0;
constant C3_UDQSN_TAP_DELAY_VAL : integer := 0;
constant C3_DQ0_TAP_DELAY_VAL : integer := 0;
constant C3_DQ1_TAP_DELAY_VAL : integer := 0;
constant C3_DQ2_TAP_DELAY_VAL : integer := 0;
constant C3_DQ3_TAP_DELAY_VAL : integer := 0;
constant C3_DQ4_TAP_DELAY_VAL : integer := 0;
constant C3_DQ5_TAP_DELAY_VAL : integer := 0;
constant C3_DQ6_TAP_DELAY_VAL : integer := 0;
constant C3_DQ7_TAP_DELAY_VAL : integer := 0;
constant C3_DQ8_TAP_DELAY_VAL : integer := 0;
constant C3_DQ9_TAP_DELAY_VAL : integer := 0;
constant C3_DQ10_TAP_DELAY_VAL : integer := 0;
constant C3_DQ11_TAP_DELAY_VAL : integer := 0;
constant C3_DQ12_TAP_DELAY_VAL : integer := 0;
constant C3_DQ13_TAP_DELAY_VAL : integer := 0;
constant C3_DQ14_TAP_DELAY_VAL : integer := 0;
constant C3_DQ15_TAP_DELAY_VAL : integer := 0;
constant C3_SMALL_DEVICE : string := "FALSE"; -- The parameter is set to TRUE for all packages of xc6slx9 device
-- as most of them cannot fit the complete example design when the
-- Chip scope modules are enabled
signal c1_sys_clk : std_logic;
signal c1_async_rst : std_logic;
signal c1_sysclk_2x : std_logic;
signal c1_sysclk_2x_180 : std_logic;
signal c1_pll_ce_0 : std_logic;
signal c1_pll_ce_90 : std_logic;
signal c1_pll_lock : std_logic;
signal c1_mcb_drp_clk : std_logic;
signal c1_cmp_error : std_logic;
signal c1_cmp_data_valid : std_logic;
signal c1_vio_modify_enable : std_logic;
signal c1_error_status : std_logic_vector(127 downto 0);
signal c1_vio_data_mode_value : std_logic_vector(2 downto 0);
signal c1_vio_addr_mode_value : std_logic_vector(2 downto 0);
signal c1_cmp_data : std_logic_vector(31 downto 0);
signal c3_sys_clk : std_logic;
signal c3_async_rst : std_logic;
signal c3_sysclk_2x : std_logic;
signal c3_sysclk_2x_180 : std_logic;
signal c3_pll_ce_0 : std_logic;
signal c3_pll_ce_90 : std_logic;
signal c3_pll_lock : std_logic;
signal c3_mcb_drp_clk : std_logic;
signal c3_cmp_error : std_logic;
signal c3_cmp_data_valid : std_logic;
signal c3_vio_modify_enable : std_logic;
signal c3_error_status : std_logic_vector(127 downto 0);
signal c3_vio_data_mode_value : std_logic_vector(2 downto 0);
signal c3_vio_addr_mode_value : std_logic_vector(2 downto 0);
signal c3_cmp_data : std_logic_vector(31 downto 0);
signal c1_selfrefresh_enter : std_logic;
signal c1_selfrefresh_mode : std_logic;
signal c3_selfrefresh_enter : std_logic;
signal c3_selfrefresh_mode : std_logic;
begin
c1_sys_clk <= '0';
c3_sys_clk <= '0';
c1_selfrefresh_enter <= '0';
c3_selfrefresh_enter <= '0';
memc1_infrastructure_inst : memc1_infrastructure
generic map
(
C_RST_ACT_LOW => C1_RST_ACT_LOW,
C_INPUT_CLK_TYPE => C1_INPUT_CLK_TYPE,
C_CLKOUT0_DIVIDE => C1_CLKOUT0_DIVIDE,
C_CLKOUT1_DIVIDE => C1_CLKOUT1_DIVIDE,
C_CLKOUT2_DIVIDE => C1_CLKOUT2_DIVIDE,
C_CLKOUT3_DIVIDE => C1_CLKOUT3_DIVIDE,
C_CLKFBOUT_MULT => C1_CLKFBOUT_MULT,
C_DIVCLK_DIVIDE => C1_DIVCLK_DIVIDE,
C_INCLK_PERIOD => C1_INCLK_PERIOD
)
port map
(
sys_clk_p => c1_sys_clk_p,
sys_clk_n => c1_sys_clk_n,
sys_clk => c1_sys_clk,
sys_rst_i => c1_sys_rst_i,
clk0 => c1_clk0,
rst0 => c1_rst0,
async_rst => c1_async_rst,
sysclk_2x => c1_sysclk_2x,
sysclk_2x_180 => c1_sysclk_2x_180,
pll_ce_0 => c1_pll_ce_0,
pll_ce_90 => c1_pll_ce_90,
pll_lock => c1_pll_lock,
mcb_drp_clk => c1_mcb_drp_clk
);
memc3_infrastructure_inst : memc3_infrastructure
generic map
(
C_RST_ACT_LOW => C3_RST_ACT_LOW,
C_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
C_CLKOUT0_DIVIDE => C3_CLKOUT0_DIVIDE,
C_CLKOUT1_DIVIDE => C3_CLKOUT1_DIVIDE,
C_CLKOUT2_DIVIDE => C3_CLKOUT2_DIVIDE,
C_CLKOUT3_DIVIDE => C3_CLKOUT3_DIVIDE,
C_CLKFBOUT_MULT => C3_CLKFBOUT_MULT,
C_DIVCLK_DIVIDE => C3_DIVCLK_DIVIDE,
C_INCLK_PERIOD => C3_INCLK_PERIOD
)
port map
(
sys_clk_p => c3_sys_clk_p,
sys_clk_n => c3_sys_clk_n,
sys_clk => c3_sys_clk,
sys_rst_i => c3_sys_rst_i,
clk0 => c3_clk0,
rst0 => c3_rst0,
async_rst => c3_async_rst,
sysclk_2x => c3_sysclk_2x,
sysclk_2x_180 => c3_sysclk_2x_180,
pll_ce_0 => c3_pll_ce_0,
pll_ce_90 => c3_pll_ce_90,
pll_lock => c3_pll_lock,
mcb_drp_clk => c3_mcb_drp_clk
);
-- wrapper instantiation
memc1_wrapper_inst : memc1_wrapper
generic map
(
C_MEMCLK_PERIOD => C1_MEMCLK_PERIOD,
C_CALIB_SOFT_IP => C1_CALIB_SOFT_IP,
C_SIMULATION => C1_SIMULATION,
C_P0_MASK_SIZE => C1_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C1_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C1_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C1_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C1_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => C1_ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => C1_ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => C1_ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => C1_ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => C1_ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => C1_ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => C1_ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => C1_ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => C1_ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => C1_ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => C1_ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => C1_ARB_TIME_SLOT_11,
C_MEM_TRAS => C1_MEM_TRAS,
C_MEM_TRCD => C1_MEM_TRCD,
C_MEM_TREFI => C1_MEM_TREFI,
C_MEM_TRFC => C1_MEM_TRFC,
C_MEM_TRP => C1_MEM_TRP,
C_MEM_TWR => C1_MEM_TWR,
C_MEM_TRTP => C1_MEM_TRTP,
C_MEM_TWTR => C1_MEM_TWTR,
C_MEM_ADDR_ORDER => C1_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C1_NUM_DQ_PINS,
C_MEM_TYPE => C1_MEM_TYPE,
C_MEM_DENSITY => C1_MEM_DENSITY,
C_MEM_BURST_LEN => C1_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C1_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C1_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C1_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C1_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C1_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C1_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C1_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C1_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C1_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C1_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C1_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C1_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C1_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C1_MEM_DDR3_AUTO_SR,
C_MEM_MOBILE_PA_SR => C1_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C1_MEM_MDDR_ODS,
C_MC_CALIB_BYPASS => C1_MC_CALIB_BYPASS,
C_MC_CALIBRATION_MODE => C1_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C1_MC_CALIBRATION_DELAY,
C_SKIP_IN_TERM_CAL => C1_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C1_SKIP_DYNAMIC_CAL,
C_LDQSP_TAP_DELAY_VAL => C1_LDQSP_TAP_DELAY_VAL,
C_LDQSN_TAP_DELAY_VAL => C1_LDQSN_TAP_DELAY_VAL,
C_UDQSP_TAP_DELAY_VAL => C1_UDQSP_TAP_DELAY_VAL,
C_UDQSN_TAP_DELAY_VAL => C1_UDQSN_TAP_DELAY_VAL,
C_DQ0_TAP_DELAY_VAL => C1_DQ0_TAP_DELAY_VAL,
C_DQ1_TAP_DELAY_VAL => C1_DQ1_TAP_DELAY_VAL,
C_DQ2_TAP_DELAY_VAL => C1_DQ2_TAP_DELAY_VAL,
C_DQ3_TAP_DELAY_VAL => C1_DQ3_TAP_DELAY_VAL,
C_DQ4_TAP_DELAY_VAL => C1_DQ4_TAP_DELAY_VAL,
C_DQ5_TAP_DELAY_VAL => C1_DQ5_TAP_DELAY_VAL,
C_DQ6_TAP_DELAY_VAL => C1_DQ6_TAP_DELAY_VAL,
C_DQ7_TAP_DELAY_VAL => C1_DQ7_TAP_DELAY_VAL,
C_DQ8_TAP_DELAY_VAL => C1_DQ8_TAP_DELAY_VAL,
C_DQ9_TAP_DELAY_VAL => C1_DQ9_TAP_DELAY_VAL,
C_DQ10_TAP_DELAY_VAL => C1_DQ10_TAP_DELAY_VAL,
C_DQ11_TAP_DELAY_VAL => C1_DQ11_TAP_DELAY_VAL,
C_DQ12_TAP_DELAY_VAL => C1_DQ12_TAP_DELAY_VAL,
C_DQ13_TAP_DELAY_VAL => C1_DQ13_TAP_DELAY_VAL,
C_DQ14_TAP_DELAY_VAL => C1_DQ14_TAP_DELAY_VAL,
C_DQ15_TAP_DELAY_VAL => C1_DQ15_TAP_DELAY_VAL
)
port map
(
mcb1_dram_dq => mcb1_dram_dq,
mcb1_dram_a => mcb1_dram_a,
mcb1_dram_ba => mcb1_dram_ba,
mcb1_dram_ras_n => mcb1_dram_ras_n,
mcb1_dram_cas_n => mcb1_dram_cas_n,
mcb1_dram_we_n => mcb1_dram_we_n,
mcb1_dram_odt => mcb1_dram_odt,
mcb1_dram_reset_n => mcb1_dram_reset_n,
mcb1_dram_cke => mcb1_dram_cke,
mcb1_dram_dm => mcb1_dram_dm,
mcb1_dram_udqs => mcb1_dram_udqs,
mcb1_dram_udqs_n => mcb1_dram_udqs_n,
mcb1_rzq => mcb1_rzq,
mcb1_zio => mcb1_zio,
mcb1_dram_udm => mcb1_dram_udm,
calib_done => c1_calib_done,
async_rst => c1_async_rst,
sysclk_2x => c1_sysclk_2x,
sysclk_2x_180 => c1_sysclk_2x_180,
pll_ce_0 => c1_pll_ce_0,
pll_ce_90 => c1_pll_ce_90,
pll_lock => c1_pll_lock,
mcb_drp_clk => c1_mcb_drp_clk,
mcb1_dram_dqs => mcb1_dram_dqs,
mcb1_dram_dqs_n => mcb1_dram_dqs_n,
mcb1_dram_ck => mcb1_dram_ck,
mcb1_dram_ck_n => mcb1_dram_ck_n,
p0_cmd_clk => c1_p0_cmd_clk,
p0_cmd_en => c1_p0_cmd_en,
p0_cmd_instr => c1_p0_cmd_instr,
p0_cmd_bl => c1_p0_cmd_bl,
p0_cmd_byte_addr => c1_p0_cmd_byte_addr,
p0_cmd_empty => c1_p0_cmd_empty,
p0_cmd_full => c1_p0_cmd_full,
p0_wr_clk => c1_p0_wr_clk,
p0_wr_en => c1_p0_wr_en,
p0_wr_mask => c1_p0_wr_mask,
p0_wr_data => c1_p0_wr_data,
p0_wr_full => c1_p0_wr_full,
p0_wr_empty => c1_p0_wr_empty,
p0_wr_count => c1_p0_wr_count,
p0_wr_underrun => c1_p0_wr_underrun,
p0_wr_error => c1_p0_wr_error,
p0_rd_clk => c1_p0_rd_clk,
p0_rd_en => c1_p0_rd_en,
p0_rd_data => c1_p0_rd_data,
p0_rd_full => c1_p0_rd_full,
p0_rd_empty => c1_p0_rd_empty,
p0_rd_count => c1_p0_rd_count,
p0_rd_overflow => c1_p0_rd_overflow,
p0_rd_error => c1_p0_rd_error,
selfrefresh_enter => c1_selfrefresh_enter,
selfrefresh_mode => c1_selfrefresh_mode
);
memc3_wrapper_inst : memc3_wrapper
generic map
(
C_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
C_CALIB_SOFT_IP => C3_CALIB_SOFT_IP,
C_SIMULATION => C3_SIMULATION,
C_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C3_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => C3_ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => C3_ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => C3_ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => C3_ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => C3_ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => C3_ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => C3_ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => C3_ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => C3_ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => C3_ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => C3_ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => C3_ARB_TIME_SLOT_11,
C_MEM_TRAS => C3_MEM_TRAS,
C_MEM_TRCD => C3_MEM_TRCD,
C_MEM_TREFI => C3_MEM_TREFI,
C_MEM_TRFC => C3_MEM_TRFC,
C_MEM_TRP => C3_MEM_TRP,
C_MEM_TWR => C3_MEM_TWR,
C_MEM_TRTP => C3_MEM_TRTP,
C_MEM_TWTR => C3_MEM_TWTR,
C_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C_MEM_TYPE => C3_MEM_TYPE,
C_MEM_DENSITY => C3_MEM_DENSITY,
C_MEM_BURST_LEN => C3_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C3_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C3_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C3_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C3_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C3_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C3_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C3_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C3_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C3_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C3_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C3_MEM_DDR3_AUTO_SR,
C_MEM_MOBILE_PA_SR => C3_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C3_MEM_MDDR_ODS,
C_MC_CALIB_BYPASS => C3_MC_CALIB_BYPASS,
C_MC_CALIBRATION_MODE => C3_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C3_MC_CALIBRATION_DELAY,
C_SKIP_IN_TERM_CAL => C3_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C3_SKIP_DYNAMIC_CAL,
C_LDQSP_TAP_DELAY_VAL => C3_LDQSP_TAP_DELAY_VAL,
C_LDQSN_TAP_DELAY_VAL => C3_LDQSN_TAP_DELAY_VAL,
C_UDQSP_TAP_DELAY_VAL => C3_UDQSP_TAP_DELAY_VAL,
C_UDQSN_TAP_DELAY_VAL => C3_UDQSN_TAP_DELAY_VAL,
C_DQ0_TAP_DELAY_VAL => C3_DQ0_TAP_DELAY_VAL,
C_DQ1_TAP_DELAY_VAL => C3_DQ1_TAP_DELAY_VAL,
C_DQ2_TAP_DELAY_VAL => C3_DQ2_TAP_DELAY_VAL,
C_DQ3_TAP_DELAY_VAL => C3_DQ3_TAP_DELAY_VAL,
C_DQ4_TAP_DELAY_VAL => C3_DQ4_TAP_DELAY_VAL,
C_DQ5_TAP_DELAY_VAL => C3_DQ5_TAP_DELAY_VAL,
C_DQ6_TAP_DELAY_VAL => C3_DQ6_TAP_DELAY_VAL,
C_DQ7_TAP_DELAY_VAL => C3_DQ7_TAP_DELAY_VAL,
C_DQ8_TAP_DELAY_VAL => C3_DQ8_TAP_DELAY_VAL,
C_DQ9_TAP_DELAY_VAL => C3_DQ9_TAP_DELAY_VAL,
C_DQ10_TAP_DELAY_VAL => C3_DQ10_TAP_DELAY_VAL,
C_DQ11_TAP_DELAY_VAL => C3_DQ11_TAP_DELAY_VAL,
C_DQ12_TAP_DELAY_VAL => C3_DQ12_TAP_DELAY_VAL,
C_DQ13_TAP_DELAY_VAL => C3_DQ13_TAP_DELAY_VAL,
C_DQ14_TAP_DELAY_VAL => C3_DQ14_TAP_DELAY_VAL,
C_DQ15_TAP_DELAY_VAL => C3_DQ15_TAP_DELAY_VAL
)
port map
(
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_reset_n => mcb3_dram_reset_n,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_udqs_n => mcb3_dram_udqs_n,
mcb3_rzq => mcb3_rzq,
mcb3_zio => mcb3_zio,
mcb3_dram_udm => mcb3_dram_udm,
calib_done => c3_calib_done,
async_rst => c3_async_rst,
sysclk_2x => c3_sysclk_2x,
sysclk_2x_180 => c3_sysclk_2x_180,
pll_ce_0 => c3_pll_ce_0,
pll_ce_90 => c3_pll_ce_90,
pll_lock => c3_pll_lock,
mcb_drp_clk => c3_mcb_drp_clk,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
p0_cmd_clk => c3_p0_cmd_clk,
p0_cmd_en => c3_p0_cmd_en,
p0_cmd_instr => c3_p0_cmd_instr,
p0_cmd_bl => c3_p0_cmd_bl,
p0_cmd_byte_addr => c3_p0_cmd_byte_addr,
p0_cmd_empty => c3_p0_cmd_empty,
p0_cmd_full => c3_p0_cmd_full,
p0_wr_clk => c3_p0_wr_clk,
p0_wr_en => c3_p0_wr_en,
p0_wr_mask => c3_p0_wr_mask,
p0_wr_data => c3_p0_wr_data,
p0_wr_full => c3_p0_wr_full,
p0_wr_empty => c3_p0_wr_empty,
p0_wr_count => c3_p0_wr_count,
p0_wr_underrun => c3_p0_wr_underrun,
p0_wr_error => c3_p0_wr_error,
p0_rd_clk => c3_p0_rd_clk,
p0_rd_en => c3_p0_rd_en,
p0_rd_data => c3_p0_rd_data,
p0_rd_full => c3_p0_rd_full,
p0_rd_empty => c3_p0_rd_empty,
p0_rd_count => c3_p0_rd_count,
p0_rd_overflow => c3_p0_rd_overflow,
p0_rd_error => c3_p0_rd_error,
selfrefresh_enter => c3_selfrefresh_enter,
selfrefresh_mode => c3_selfrefresh_mode
);
end arc;
| gpl-3.0 | 3b9a2f52d2bc59570f5b4594a4b3c5e1 | 0.447901 | 3.449489 | false | false | false | false |
VerticalResearchGroup/miaow | scripts/xilinx/base_microblaze_design_wrapper.vhd | 1 | 8,610 | --Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2015.1 (win64) Build 1215546 Mon Apr 27 19:22:08 MDT 2015
--Date : Thu Apr 14 15:33:49 2016
--Host : youko running 64-bit major release (build 9200)
--Command : generate_target base_microblaze_design_wrapper.bd
--Design : base_microblaze_design_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity base_microblaze_design_wrapper is
port (
ddr3_sdram_addr : out STD_LOGIC_VECTOR ( 13 downto 0 );
ddr3_sdram_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
ddr3_sdram_cas_n : out STD_LOGIC;
ddr3_sdram_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr3_sdram_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr3_sdram_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr3_sdram_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr3_sdram_dm : out STD_LOGIC_VECTOR ( 7 downto 0 );
ddr3_sdram_dq : inout STD_LOGIC_VECTOR ( 63 downto 0 );
ddr3_sdram_dqs_n : inout STD_LOGIC_VECTOR ( 7 downto 0 );
ddr3_sdram_dqs_p : inout STD_LOGIC_VECTOR ( 7 downto 0 );
ddr3_sdram_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr3_sdram_ras_n : out STD_LOGIC;
ddr3_sdram_reset_n : out STD_LOGIC;
ddr3_sdram_we_n : out STD_LOGIC;
led_8bits_tri_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
reset : in STD_LOGIC;
rs232_uart_rxd : in STD_LOGIC;
rs232_uart_txd : out STD_LOGIC;
sys_diff_clock_clk_n : in STD_LOGIC;
sys_diff_clock_clk_p : in STD_LOGIC
);
end base_microblaze_design_wrapper;
architecture STRUCTURE of base_microblaze_design_wrapper is
signal S_AXI_ACLK : std_logic;
signal S_AXI_ARESETN : std_logic;
signal S_AXI_AWADDR : std_logic_vector(10 downto 0);
signal S_AXI_AWPROT : std_logic_vector(2 downto 0);
signal S_AXI_AWVALID : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WDATA : std_logic_vector(31 downto 0);
signal S_AXI_WSTRB : std_logic_vector(3 downto 0);
signal S_AXI_WVALID : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BRESP : std_logic_vector(1 downto 0);
signal S_AXI_BVALID : std_logic;
signal S_AXI_BREADY : std_logic;
signal S_AXI_ARADDR : std_logic_vector(10 downto 0);
signal S_AXI_ARPROT : std_logic_vector(2 downto 0);
signal S_AXI_ARVALID : std_logic;
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RDATA : std_logic_vector(31 downto 0);
signal S_AXI_RRESP : std_logic_vector(1 downto 0);
signal S_AXI_RVALID : std_logic;
signal S_AXI_RREADY : std_logic;
component base_microblaze_design is
port (
sys_diff_clock_clk_p : in STD_LOGIC;
sys_diff_clock_clk_n : in STD_LOGIC;
rs232_uart_rxd : in STD_LOGIC;
rs232_uart_txd : out STD_LOGIC;
led_8bits_tri_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
ddr3_sdram_dq : inout STD_LOGIC_VECTOR ( 63 downto 0 );
ddr3_sdram_dqs_p : inout STD_LOGIC_VECTOR ( 7 downto 0 );
ddr3_sdram_dqs_n : inout STD_LOGIC_VECTOR ( 7 downto 0 );
ddr3_sdram_addr : out STD_LOGIC_VECTOR ( 13 downto 0 );
ddr3_sdram_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
ddr3_sdram_ras_n : out STD_LOGIC;
ddr3_sdram_cas_n : out STD_LOGIC;
ddr3_sdram_we_n : out STD_LOGIC;
ddr3_sdram_reset_n : out STD_LOGIC;
ddr3_sdram_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr3_sdram_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr3_sdram_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr3_sdram_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr3_sdram_dm : out STD_LOGIC_VECTOR ( 7 downto 0 );
ddr3_sdram_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
reset : in STD_LOGIC;
S_AXI_AWREADY : in STD_LOGIC;
S_AXI_ACLK : out STD_LOGIC;
S_AXI_BREADY : out STD_LOGIC;
S_AXI_ARESETN : out STD_LOGIC;
S_AXI_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ARVALID : out STD_LOGIC;
S_AXI_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ARADDR : out STD_LOGIC_VECTOR ( 10 downto 0 );
S_AXI_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_AWADDR : out STD_LOGIC_VECTOR ( 10 downto 0 );
S_AXI_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_WVALID : out STD_LOGIC;
S_AXI_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_WREADY : in STD_LOGIC;
S_AXI_ARREADY : in STD_LOGIC;
S_AXI_BVALID : in STD_LOGIC;
S_AXI_RVALID : in STD_LOGIC;
S_AXI_AWVALID : out STD_LOGIC;
S_AXI_RREADY : out STD_LOGIC
);
end component base_microblaze_design;
component compute_unit_fpga is
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(10 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(10 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component compute_unit_fpga;
begin
base_microblaze_design_i: component base_microblaze_design
port map (
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARADDR(10 downto 0) => S_AXI_ARADDR(10 downto 0),
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_ARPROT(2 downto 0) => S_AXI_ARPROT(2 downto 0),
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_AWADDR(10 downto 0) => S_AXI_AWADDR(10 downto 0),
S_AXI_AWPROT(2 downto 0) => S_AXI_AWPROT(2 downto 0),
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_BRESP(1 downto 0) => S_AXI_BRESP(1 downto 0),
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_RDATA(31 downto 0) => S_AXI_RDATA(31 downto 0),
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_RRESP(1 downto 0) => S_AXI_RRESP(1 downto 0),
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WDATA(31 downto 0) => S_AXI_WDATA(31 downto 0),
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_WSTRB(3 downto 0) => S_AXI_WSTRB(3 downto 0),
S_AXI_WVALID => S_AXI_WVALID,
ddr3_sdram_addr(13 downto 0) => ddr3_sdram_addr(13 downto 0),
ddr3_sdram_ba(2 downto 0) => ddr3_sdram_ba(2 downto 0),
ddr3_sdram_cas_n => ddr3_sdram_cas_n,
ddr3_sdram_ck_n(0) => ddr3_sdram_ck_n(0),
ddr3_sdram_ck_p(0) => ddr3_sdram_ck_p(0),
ddr3_sdram_cke(0) => ddr3_sdram_cke(0),
ddr3_sdram_cs_n(0) => ddr3_sdram_cs_n(0),
ddr3_sdram_dm(7 downto 0) => ddr3_sdram_dm(7 downto 0),
ddr3_sdram_dq(63 downto 0) => ddr3_sdram_dq(63 downto 0),
ddr3_sdram_dqs_n(7 downto 0) => ddr3_sdram_dqs_n(7 downto 0),
ddr3_sdram_dqs_p(7 downto 0) => ddr3_sdram_dqs_p(7 downto 0),
ddr3_sdram_odt(0) => ddr3_sdram_odt(0),
ddr3_sdram_ras_n => ddr3_sdram_ras_n,
ddr3_sdram_reset_n => ddr3_sdram_reset_n,
ddr3_sdram_we_n => ddr3_sdram_we_n,
led_8bits_tri_o(7 downto 0) => led_8bits_tri_o(7 downto 0),
reset => reset,
rs232_uart_rxd => rs232_uart_rxd,
rs232_uart_txd => rs232_uart_txd,
sys_diff_clock_clk_n => sys_diff_clock_clk_n,
sys_diff_clock_clk_p => sys_diff_clock_clk_p
);
compute_unit_fpga_i : component compute_unit_fpga
port map (
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWPROT => S_AXI_AWPROT,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARPROT => S_AXI_ARPROT,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY
);
end STRUCTURE;
| bsd-3-clause | 5019285b4490815f172027f61c6d2e7e | 0.622997 | 2.876712 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/pcie_core/example_design/PIO_EP_MEM_ACCESS.vhd | 1 | 15,616 | -------------------------------------------------------------------------------
--
-- (c) Copyright 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : PIO_EP_MEM_ACCESS.vhd
-- Description: Endpoint Memory Access Unit. This module provides access
-- functions to the Endpoint memory aperture.
--
-- Read Access: Module returns data for the specifed address and
-- byte enables selected.
--
-- Write Access: Module accepts data, byte enables and updates
-- data when write enable is asserted. Modules signals write busy
-- when data write is in progress.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity PIO_EP_MEM_ACCESS is
port (
clk : in std_logic;
rst_n : in std_logic;
-- Read Port
rd_addr_i : in std_logic_vector(10 downto 0);
rd_be_i : in std_logic_vector(3 downto 0);
rd_data_o : out std_logic_vector(31 downto 0);
-- Write Port
wr_addr_i : in std_logic_vector(10 downto 0);
wr_be_i : in std_logic_vector(7 downto 0);
wr_data_i : in std_logic_vector(31 downto 0);
wr_en_i : in std_logic;
wr_busy_o : out std_logic
);
end PIO_EP_MEM_ACCESS;
architecture rtl of PIO_EP_MEM_ACCESS is
constant TCQ : time := 1 ns;
type state_type is (PIO_MEM_ACCESS_WR_RST,
PIO_MEM_ACCESS_WR_WAIT,
PIO_MEM_ACCESS_WR_READ,
PIO_MEM_ACCESS_WR_WRITE
);
component PIO_EP_MEM port (
clk_i : in std_logic;
a_rd_a_i_0 : in std_logic_vector(8 downto 0);
a_rd_d_o_0 : out std_logic_vector(31 downto 0);
a_rd_en_i_0 : in std_logic;
b_wr_a_i_0 : in std_logic_vector(8 downto 0);
b_wr_d_i_0 : in std_logic_vector(31 downto 0);
b_wr_en_i_0 : in std_logic;
b_rd_d_o_0 : out std_logic_vector(31 downto 0);
b_rd_en_i_0 : in std_logic;
a_rd_a_i_1 : in std_logic_vector(8 downto 0);
a_rd_d_o_1 : out std_logic_vector(31 downto 0);
a_rd_en_i_1 : in std_logic;
b_wr_a_i_1 : in std_logic_vector(8 downto 0);
b_wr_d_i_1 : in std_logic_vector(31 downto 0);
b_wr_en_i_1 : in std_logic;
b_rd_d_o_1 : out std_logic_vector(31 downto 0);
b_rd_en_i_1 : in std_logic;
a_rd_a_i_2 : in std_logic_vector(8 downto 0);
a_rd_d_o_2 : out std_logic_vector(31 downto 0);
a_rd_en_i_2 : in std_logic;
b_wr_a_i_2 : in std_logic_vector(8 downto 0);
b_wr_d_i_2 : in std_logic_vector(31 downto 0);
b_wr_en_i_2 : in std_logic;
b_rd_d_o_2 : out std_logic_vector(31 downto 0);
b_rd_en_i_2 : in std_logic;
a_rd_a_i_3 : in std_logic_vector(8 downto 0);
a_rd_d_o_3 : out std_logic_vector(31 downto 0);
a_rd_en_i_3 : in std_logic;
b_wr_a_i_3 : in std_logic_vector(8 downto 0);
b_wr_d_i_3 : in std_logic_vector(31 downto 0);
b_wr_en_i_3 : in std_logic;
b_rd_d_o_3 : out std_logic_vector(31 downto 0);
b_rd_en_i_3 : in std_logic
);
end component;
signal rd_data_raw_o : std_logic_vector(31 downto 0);
signal rd_data0_o : std_logic_vector(31 downto 0);
signal rd_data1_o : std_logic_vector(31 downto 0);
signal rd_data2_o : std_logic_vector(31 downto 0);
signal rd_data3_o : std_logic_vector(31 downto 0);
signal write_en : std_logic;
signal post_wr_data : std_logic_vector(31 downto 0);
signal w_pre_wr_data : std_logic_vector(31 downto 0);
signal wr_mem_state : state_type;
signal pre_wr_data : std_logic_vector(31 downto 0);
signal w_pre_wr_data0 : std_logic_vector(31 downto 0);
signal w_pre_wr_data1 : std_logic_vector(31 downto 0);
signal w_pre_wr_data2 : std_logic_vector(31 downto 0);
signal w_pre_wr_data3 : std_logic_vector(31 downto 0);
--
-- Memory Write Process
--
--
-- Extract current data bytes. These need to be swizzled
-- BRAM storage format :
-- data[31:0] = { byte[3], byte[2], byte[1], byte[0] (lowest addr) }
--
signal w_pre_wr_data_b3 : std_logic_vector(7 downto 0);
signal w_pre_wr_data_b2 : std_logic_vector(7 downto 0);
signal w_pre_wr_data_b1 : std_logic_vector(7 downto 0);
signal w_pre_wr_data_b0 : std_logic_vector(7 downto 0);
--
-- Extract new data bytes from payload
-- TLP Payload format :
-- data[31:0] = { byte[0] (lowest addr), byte[2], byte[1], byte[3] }
--
signal w_wr_data_b3 : std_logic_vector(7 downto 0);
signal w_wr_data_b2 : std_logic_vector(7 downto 0);
signal w_wr_data_b1 : std_logic_vector(7 downto 0);
signal w_wr_data_b0 : std_logic_vector(7 downto 0);
signal w_wr_data0_int : std_logic_vector(7 downto 0);
signal w_wr_data1_int : std_logic_vector(7 downto 0);
signal w_wr_data2_int : std_logic_vector(7 downto 0);
signal w_wr_data3_int : std_logic_vector(7 downto 0);
signal rd_data0_en : std_logic;
signal rd_data1_en : std_logic;
signal rd_data2_en : std_logic;
signal rd_data3_en : std_logic;
signal rd_data_raw_int0 : std_logic_vector(7 downto 0);
signal rd_data_raw_int1 : std_logic_vector(7 downto 0);
signal rd_data_raw_int2 : std_logic_vector(7 downto 0);
signal rd_data_raw_int3 : std_logic_vector(7 downto 0);
signal b_wr_en_0 : std_logic;
signal b_wr_en_1 : std_logic;
signal b_wr_en_2 : std_logic;
signal b_wr_en_3 : std_logic;
signal wr_addr_0 : std_logic;
signal wr_addr_1 : std_logic;
signal wr_addr_2 : std_logic;
signal wr_addr_3 : std_logic;
begin
--
-- Extract current data bytes. These need to be swizzled
-- BRAM storage format :
-- data[31:0] = { byte[3], byte[2], byte[1], byte[0] (lowest addr) }
--
w_pre_wr_data_b3 <= pre_wr_data(31 downto 24);
w_pre_wr_data_b2 <= pre_wr_data(23 downto 16);
w_pre_wr_data_b1 <= pre_wr_data(15 downto 08);
w_pre_wr_data_b0 <= pre_wr_data(07 downto 00);
--
-- Extract new data bytes from payload
-- TLP Payload format :
-- data[31:0] = { byte[0] (lowest addr), byte[2], byte[1], byte[3] }
--
w_wr_data_b3 <= wr_data_i(7 downto 0);
w_wr_data_b2 <= wr_data_i(15 downto 8);
w_wr_data_b1 <= wr_data_i(23 downto 16);
w_wr_data_b0 <= wr_data_i(31 downto 24);
w_wr_data3_int <= w_wr_data_b3 when (wr_be_i(3) = '1') else w_pre_wr_data_b3;
w_wr_data2_int <= w_wr_data_b2 when (wr_be_i(2) = '1') else w_pre_wr_data_b2;
w_wr_data1_int <= w_wr_data_b1 when (wr_be_i(1) = '1') else w_pre_wr_data_b1;
w_wr_data0_int <= w_wr_data_b0 when (wr_be_i(0) = '1') else w_pre_wr_data_b0;
process begin
wait until rising_edge(clk);
if (rst_n = '0') then
write_en <= '0';
pre_wr_data <= (OTHERS => '0') after TCQ;
post_wr_data <= (OTHERS => '0') after TCQ;
pre_wr_data <= (OTHERS => '0') after TCQ;
wr_mem_state <= PIO_MEM_ACCESS_WR_RST after TCQ;
else
case (wr_mem_state) is
when PIO_MEM_ACCESS_WR_RST =>
if (wr_en_i = '1') then -- read state
-- Pipelining happens in RAM's internal output reg
wr_mem_state <= PIO_MEM_ACCESS_WR_WAIT after TCQ;
else
write_en <= '0' after TCQ;
wr_mem_state <= PIO_MEM_ACCESS_WR_RST after TCQ;
end if;
when PIO_MEM_ACCESS_WR_WAIT =>
--
-- Pipeline B port data before processing. Block RAMs
-- have internal output register enabled
--
write_en <= '0' after TCQ;
wr_mem_state <= PIO_MEM_ACCESS_WR_READ after TCQ;
when PIO_MEM_ACCESS_WR_READ =>
--
-- Now save the selected BRAM B port data out
--
pre_wr_data <= w_pre_wr_data after TCQ;
write_en <= '0' after TCQ;
wr_mem_state <= PIO_MEM_ACCESS_WR_WRITE after TCQ;
when PIO_MEM_ACCESS_WR_WRITE =>
--
-- Merge new enabled data and write target BlockRAM location
--
post_wr_data <= w_wr_data3_int &
w_wr_data2_int &
w_wr_data1_int &
w_wr_data0_int after TCQ;
write_en <= '1' after TCQ;
wr_mem_state <= PIO_MEM_ACCESS_WR_RST after TCQ;
when others => null;
wr_mem_state <= PIO_MEM_ACCESS_WR_RST after TCQ;
end case;
end if;
end process;
--
-- Write controller busy
--
wr_busy_o <= '1' when ((wr_mem_state /= PIO_MEM_ACCESS_WR_RST) or wr_en_i = '1') else '0';
--
-- Select BlockRAM output based on higher 2 address bits
--
process (wr_addr_i, w_pre_wr_data0, w_pre_wr_data1, w_pre_wr_data2,
w_pre_wr_data3) begin
case (wr_addr_i(10 downto 9)) is
when "00" => w_pre_wr_data <= w_pre_wr_data0;
when "01" => w_pre_wr_data <= w_pre_wr_data1;
when "10" => w_pre_wr_data <= w_pre_wr_data2;
when "11" => w_pre_wr_data <= w_pre_wr_data3;
when others => null;
end case;
end process;
--
-- Memory Read Controller
--
rd_data0_en <= '1' when (rd_addr_i(10 downto 9) = "00") else '0';
rd_data1_en <= '1' when (rd_addr_i(10 downto 9) = "01") else '0';
rd_data2_en <= '1' when (rd_addr_i(10 downto 9) = "10") else '0';
rd_data3_en <= '1' when (rd_addr_i(10 downto 9) = "11") else '0';
process(rd_addr_i, rd_data0_o, rd_data1_o,
rd_data2_o, rd_data3_o) begin
case (rd_addr_i(10 downto 9)) is
when "00" => rd_data_raw_o <= rd_data0_o;
when "01" => rd_data_raw_o <= rd_data1_o;
when "10" => rd_data_raw_o <= rd_data2_o;
when "11" => rd_data_raw_o <= rd_data3_o;
when others => null;
end case;
end process;
-- Handle Read byte enables --
rd_data_raw_int0 <= rd_data_raw_o(7 downto 0) when (rd_be_i(0) = '1')
else (others => '0');
rd_data_raw_int1 <= rd_data_raw_o(15 downto 8) when (rd_be_i(1) = '1')
else (others => '0');
rd_data_raw_int2 <= rd_data_raw_o(23 downto 16) when (rd_be_i(2) = '1')
else (others => '0');
rd_data_raw_int3 <= rd_data_raw_o (31 downto 24) when (rd_be_i(3) = '1')
else (others => '0');
rd_data_o <= rd_data_raw_int0 &
rd_data_raw_int1 &
rd_data_raw_int2 &
rd_data_raw_int3 ;
b_wr_en_0 <= write_en when (wr_addr_i(10 downto 9) = "00") else '0';
b_wr_en_1 <= write_en when (wr_addr_i(10 downto 9) = "01") else '0';
b_wr_en_2 <= write_en when (wr_addr_i(10 downto 9) = "10") else '0';
b_wr_en_3 <= write_en when (wr_addr_i(10 downto 9) = "11") else '0';
wr_addr_0 <= '1' when (wr_addr_i(10 downto 9) = "00") else '0';
wr_addr_1 <= '1' when (wr_addr_i(10 downto 9) = "01") else '0';
wr_addr_2 <= '1' when (wr_addr_i(10 downto 9) = "10") else '0';
wr_addr_3 <= '1' when (wr_addr_i(10 downto 9) = "11") else '0';
PIO_EP_MEM_inst : PIO_EP_MEM
port map (
clk_i => clk,
a_rd_a_i_0 => rd_addr_i(8 downto 0), -- I [8:0]
a_rd_en_i_0 => rd_data0_en, -- I [1:0]
a_rd_d_o_0 => rd_data0_o, -- O [31:0]
b_wr_a_i_0 => wr_addr_i(8 downto 0), -- I [8:0]
b_wr_d_i_0 => post_wr_data, -- I [31:0]
b_wr_en_i_0 => b_wr_en_0, -- I
b_rd_d_o_0 => w_pre_wr_data0(31 downto 0), -- O [31:0]
b_rd_en_i_0 => wr_addr_0, -- I
a_rd_a_i_1 => rd_addr_i(8 downto 0), -- I [8:0]
a_rd_en_i_1 => rd_data1_en, -- I [1:0]
a_rd_d_o_1 => rd_data1_o, -- O [31:0]
b_wr_a_i_1 => wr_addr_i(8 downto 0), -- I [8:0]
b_wr_d_i_1 => post_wr_data, -- I [31:0]
b_wr_en_i_1 => b_wr_en_1, -- I
b_rd_d_o_1 => w_pre_wr_data1(31 downto 0), -- O [31:0]
b_rd_en_i_1 => wr_addr_1, -- I
a_rd_a_i_2 => rd_addr_i(8 downto 0), -- I [8:0]
a_rd_en_i_2 => rd_data2_en, -- I [1:0]
a_rd_d_o_2 => rd_data2_o, -- O [31:0]
b_wr_a_i_2 => wr_addr_i(8 downto 0), -- I [8:0]
b_wr_d_i_2 => post_wr_data, -- I [31:0]
b_wr_en_i_2 => b_wr_en_2, -- I
b_rd_d_o_2 => w_pre_wr_data2(31 downto 0), -- I [31:0]
b_rd_en_i_2 => wr_addr_2, -- I
a_rd_a_i_3 => rd_addr_i(8 downto 0), -- I [8:0]
a_rd_en_i_3 => rd_data3_en, -- I [1:0]
a_rd_d_o_3 => rd_data3_o, -- O [31:0]
b_wr_a_i_3 => wr_addr_i(8 downto 0), -- I [8:0]
b_wr_d_i_3 => post_wr_data, -- I [31:0]
b_wr_en_i_3 => b_wr_en_3, -- I
b_rd_d_o_3 => w_pre_wr_data3(31 downto 0), -- I [31:0]
b_rd_en_i_3 => wr_addr_3 -- I
);
end rtl;
| gpl-3.0 | 617a73fab73687131660cbeb3233437c | 0.545082 | 2.886506 | false | false | false | false |
JavierRizzoA/Sacagawea | sources/test_mem_cntrl.vhd | 1 | 2,648 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:52:02 06/05/2016
-- Design Name:
-- Module Name: C:/Users/AlvaroMoreno/Desktop/proooc/sacagawea_copy/test_mem_cntrl.vhd
-- Project Name: Sacagawea
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: mem_control
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY test_mem_cntrl IS
END test_mem_cntrl;
ARCHITECTURE behavior OF test_mem_cntrl IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT mem_control
PORT(
IR : IN std_logic_vector(7 downto 0);
CONT : IN std_logic_vector(2 downto 0);
salida_mem_control : OUT std_logic_vector(24 downto 0)
);
END COMPONENT;
--Inputs
signal IR : std_logic_vector(7 downto 0) := (others => '0');
signal CONT : std_logic_vector(2 downto 0) := (others => '0');
--Outputs
signal salida_mem_control : std_logic_vector(24 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: mem_control PORT MAP (
IR => IR,
CONT => CONT,
salida_mem_control => salida_mem_control
);
-- Stimulus process
stim_proc: process
begin
wait for 100 ns;
IR <= X"00";
CONT <= "000";
wait for 100 ns;
CONT <= "001";
wait for 100 ns;
CONT <= "010";
wait for 100 ns;
IR <= X"E1";
cont <= "000";
wait for 100 ns;
cont <= "001";
wait for 100 ns;
cont <= "010";
wait for 100 ns;
cont <= "011";
wait for 100 ns;
cont <= "100";
wait for 100 ns;
cont <= "101";
wait for 100 ns;
wait;
end process;
END;
| mit | 687fe17634759c039f14b80f42c207fa | 0.557402 | 3.756028 | false | true | false | false |
Nixon-/VHDL_library | memory/to_test/nbit_shift_Register.vhd | 1 | 973 | Library ieee;
use ieee.std_logic_1164.all;
entity nbit_shift_register is
generic(n:integer:=4);
port(
clk,enable,arsh,alsh,load: in std_logic;
inputVector: in std_logic_vector(n-1 downto 0);
outputVector: out std_logic_vector(n-1 downto 0);
bit_in: in std_logic;
bit_out: out std_logic;
);
end nbit_shift_register;
architecture primary of nbit_shift_register is
begin
process(clk,enable,arsh,alsh,load,bit_in,inputVector)
variable cdata,ndata: std_logic_vector(n-1 downto 0);
begin
if(clk' event and clk = '1') then
if (enable = '1') then
if (load = '1') then
ndata := inputVector;
elsif (ashl = '1') then
for i in 0 to i-2 begin
ndata(i+1) := cdata(i);
end for;
b_out <= cdata(n-1);
elsif (ashr = '1') then
for i in 1 to n-1 begin
ndata(i-1) := cdata(i);
end for;
b_out <= cdata(0);
end if;
end if;
outputVector <= ndata;
cdata <= ndata;
end if;
end process;
end primary;
| gpl-2.0 | c9f5fa5dbd9c6e7d673ec42e81aef0e7 | 0.628983 | 2.870206 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/ddr3_controller/user_design/sim/memc1_tb_top.vhd | 2 | 21,803 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.9
-- \ \ Application : MIG
-- / / Filename : memc1_tb_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:59 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This is top level module for test bench. which instantiates
-- init_mem_pattern_ctr and mcb_traffic_gen modules for each user
-- port.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity memc1_tb_top is
generic
(
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_MEM_BURST_LEN : integer := 8;
C_SIMULATION : string := "FALSE";
C_MEM_NUM_COL_BITS : integer := 11;
C_NUM_DQ_PINS : integer := 8;
C_SMALL_DEVICE : string := "FALSE";
C_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000100";
C_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p0_END_ADDRESS : std_logic_vector(31 downto 0) := X"000002ff";
C_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffffc00";
C_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000100"
);
port
(
clk0 : in std_logic;
rst0 : in std_logic;
calib_done : in std_logic;
p0_mcb_cmd_en_o : out std_logic;
p0_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p0_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p0_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p0_mcb_cmd_full_i : in std_logic;
p0_mcb_wr_en_o : out std_logic;
p0_mcb_wr_mask_o : out std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_mcb_wr_data_o : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_wr_full_i : in std_logic;
p0_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p0_mcb_rd_en_o : out std_logic;
p0_mcb_rd_data_i : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_rd_empty_i : in std_logic;
p0_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
cmp_error : out std_logic;
cmp_data : out std_logic_vector(31 downto 0);
cmp_data_valid : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(127 downto 0)
);
end memc1_tb_top;
architecture arc of memc1_tb_top is
function ERROR_DQWIDTH (val_i : integer) return integer is
begin
if (val_i = 4) then
return 1;
else
return val_i/8;
end if;
end function ERROR_DQWIDTH;
constant DQ_ERROR_WIDTH : integer := ERROR_DQWIDTH(C_NUM_DQ_PINS);
component init_mem_pattern_ctr IS
generic (
FAMILY : string;
BEGIN_ADDRESS : std_logic_vector(31 downto 0);
END_ADDRESS : std_logic_vector(31 downto 0);
DWIDTH : integer;
CMD_SEED_VALUE : std_logic_vector(31 downto 0);
DATA_SEED_VALUE : std_logic_vector(31 downto 0);
DATA_MODE : std_logic_vector(3 downto 0);
PORT_MODE : string
);
PORT (
clk_i : in std_logic;
rst_i : in std_logic;
mcb_cmd_bl_i : in std_logic_vector(5 downto 0);
mcb_cmd_en_i : in std_logic;
mcb_cmd_instr_i : in std_logic_vector(2 downto 0);
mcb_init_done_i : in std_logic;
mcb_wr_en_i : in std_logic;
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
vio_bl_mode_value : in STD_LOGIC_VECTOR(1 downto 0);
vio_fixed_bl_value : in STD_LOGIC_VECTOR(5 downto 0);
cmp_error : in std_logic;
run_traffic_o : out std_logic;
start_addr_o : out std_logic_vector(31 downto 0);
end_addr_o : out std_logic_vector(31 downto 0);
cmd_seed_o : out std_logic_vector(31 downto 0);
data_seed_o : out std_logic_vector(31 downto 0);
load_seed_o : out std_logic;
addr_mode_o : out std_logic_vector(2 downto 0);
instr_mode_o : out std_logic_vector(3 downto 0);
bl_mode_o : out std_logic_vector(1 downto 0);
data_mode_o : out std_logic_vector(3 downto 0);
mode_load_o : out std_logic;
fixed_bl_o : out std_logic_vector(5 downto 0);
fixed_instr_o : out std_logic_vector(2 downto 0);
fixed_addr_o : out std_logic_vector(31 downto 0)
);
end component;
component mcb_traffic_gen is
generic (
FAMILY : string;
SIMULATION : string;
MEM_BURST_LEN : integer;
PORT_MODE : string;
DATA_PATTERN : string;
CMD_PATTERN : string;
ADDR_WIDTH : integer;
CMP_DATA_PIPE_STAGES : integer;
MEM_COL_WIDTH : integer;
NUM_DQ_PINS : integer;
DQ_ERROR_WIDTH : integer;
DWIDTH : integer;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0);
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0);
PRBS_EADDR : std_logic_vector(31 downto 0);
PRBS_SADDR : std_logic_vector(31 downto 0)
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
run_traffic_i : in std_logic;
manual_clear_error : in std_logic;
-- *** runtime parameter ***
start_addr_i : in std_logic_vector(31 downto 0);
end_addr_i : in std_logic_vector(31 downto 0);
cmd_seed_i : in std_logic_vector(31 downto 0);
data_seed_i : in std_logic_vector(31 downto 0);
load_seed_i : in std_logic;
addr_mode_i : in std_logic_vector(2 downto 0);
instr_mode_i : in std_logic_vector(3 downto 0);
bl_mode_i : in std_logic_vector(1 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
mode_load_i : in std_logic;
-- fixed pattern inputs interface
fixed_bl_i : in std_logic_vector(5 downto 0);
fixed_instr_i : in std_logic_vector(2 downto 0);
fixed_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : IN STD_LOGIC_VECTOR(DWIDTH-1 DOWNTO 0);
bram_cmd_i : in std_logic_vector(38 downto 0);
bram_valid_i : in std_logic;
bram_rdy_o : out std_logic;
--///////////////////////////////////////////////////////////////////////////
-- MCB INTERFACE
-- interface to mcb command port
mcb_cmd_en_o : out std_logic;
mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
mcb_cmd_addr_o : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
mcb_cmd_full_i : in std_logic;
-- interface to mcb wr data port
mcb_wr_en_o : out std_logic;
mcb_wr_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
mcb_wr_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
mcb_wr_data_end_o : OUT std_logic;
mcb_wr_full_i : in std_logic;
mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
-- interface to mcb rd data port
mcb_rd_en_o : out std_logic;
mcb_rd_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
mcb_rd_empty_i : in std_logic;
mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
--///////////////////////////////////////////////////////////////////////////
-- status feedback
counts_rst : in std_logic;
wr_data_counts : out std_logic_vector(47 downto 0);
rd_data_counts : out std_logic_vector(47 downto 0);
cmp_data : out std_logic_vector(DWIDTH - 1 downto 0);
cmp_data_valid : out std_logic;
cmp_error : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(64 + (2 * DWIDTH - 1) downto 0);
mem_rd_data : out std_logic_vector(DWIDTH - 1 downto 0);
dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
cumlative_dq_lane_error : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
);
end component;
-- Function to determine the number of data patterns to be generated
function DATA_PATTERN_CALC return string is
begin
if (C_SMALL_DEVICE = "FALSE") then
return "DGEN_ALL";
else
return "DGEN_ADDR";
end if;
end function;
constant FAMILY : string := "SPARTAN6";
constant DATA_PATTERN : string := DATA_PATTERN_CALC;
constant CMD_PATTERN : string := "CGEN_ALL";
constant ADDR_WIDTH : integer := 30;
constant CMP_DATA_PIPE_STAGES : integer := 0;
constant PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00007000";
constant PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFF8000";
constant PRBS_SADDR : std_logic_vector(31 downto 0) := X"00005000";
constant PRBS_EADDR : std_logic_vector(31 downto 0) := X"00007fff";
constant BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000000";
constant END_ADDRESS : std_logic_vector(31 downto 0) := X"00000fff";
constant DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant p0_DWIDTH : integer := 32;
constant p0_PORT_MODE : string := "BI_MODE";
--p0 Signal declarations
signal p0_tg_run_traffic : std_logic;
signal p0_tg_start_addr : std_logic_vector(31 downto 0);
signal p0_tg_end_addr : std_logic_vector(31 downto 0);
signal p0_tg_cmd_seed : std_logic_vector(31 downto 0);
signal p0_tg_data_seed : std_logic_vector(31 downto 0);
signal p0_tg_load_seed : std_logic;
signal p0_tg_addr_mode : std_logic_vector(2 downto 0);
signal p0_tg_instr_mode : std_logic_vector(3 downto 0);
signal p0_tg_bl_mode : std_logic_vector(1 downto 0);
signal p0_tg_data_mode : std_logic_vector(3 downto 0);
signal p0_tg_mode_load : std_logic;
signal p0_tg_fixed_bl : std_logic_vector(5 downto 0);
signal p0_tg_fixed_instr : std_logic_vector(2 downto 0);
signal p0_tg_fixed_addr : std_logic_vector(31 downto 0);
signal p0_error_status : std_logic_vector(64 + (2*p0_DWIDTH - 1) downto 0);
signal p0_error : std_logic;
signal p0_cmp_error : std_logic;
signal p0_cmp_data : std_logic_vector(p0_DWIDTH-1 downto 0);
signal p0_cmp_data_valid : std_logic;
signal p0_mcb_cmd_en_o_int : std_logic;
signal p0_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
signal p0_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
signal p0_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
signal p0_mcb_wr_en_o_int : std_logic;
--signal cmp_data : std_logic_vector(31 downto 0);
begin
cmp_error <= p0_cmp_error;
error <= p0_error;
error_status <= p0_error_status;
cmp_data <= p0_cmp_data(31 downto 0);
cmp_data_valid <= p0_cmp_data_valid;
p0_mcb_cmd_en_o <= p0_mcb_cmd_en_o_int;
p0_mcb_cmd_instr_o <= p0_mcb_cmd_instr_o_int;
p0_mcb_cmd_bl_o <= p0_mcb_cmd_bl_o_int;
p0_mcb_cmd_addr_o <= p0_mcb_cmd_addr_o_int;
p0_mcb_wr_en_o <= p0_mcb_wr_en_o_int;
init_mem_pattern_ctr_p0 :init_mem_pattern_ctr
generic map
(
DWIDTH => p0_DWIDTH,
FAMILY => FAMILY,
BEGIN_ADDRESS => C_p0_BEGIN_ADDRESS,
END_ADDRESS => C_p0_END_ADDRESS,
CMD_SEED_VALUE => X"56456783",
DATA_SEED_VALUE => X"12345678",
DATA_MODE => C_p0_DATA_MODE,
PORT_MODE => p0_PORT_MODE
)
port map
(
clk_i => clk0,
rst_i => rst0,
mcb_cmd_en_i => p0_mcb_cmd_en_o_int,
mcb_cmd_instr_i => p0_mcb_cmd_instr_o_int,
mcb_cmd_bl_i => p0_mcb_cmd_bl_o_int,
mcb_wr_en_i => p0_mcb_wr_en_o_int,
vio_modify_enable => vio_modify_enable,
vio_data_mode_value => vio_data_mode_value,
vio_addr_mode_value => vio_addr_mode_value,
vio_bl_mode_value => "10",--vio_bl_mode_value,
vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
mcb_init_done_i => calib_done,
cmp_error => p0_error,
run_traffic_o => p0_tg_run_traffic,
start_addr_o => p0_tg_start_addr,
end_addr_o => p0_tg_end_addr ,
cmd_seed_o => p0_tg_cmd_seed ,
data_seed_o => p0_tg_data_seed ,
load_seed_o => p0_tg_load_seed ,
addr_mode_o => p0_tg_addr_mode ,
instr_mode_o => p0_tg_instr_mode ,
bl_mode_o => p0_tg_bl_mode ,
data_mode_o => p0_tg_data_mode ,
mode_load_o => p0_tg_mode_load ,
fixed_bl_o => p0_tg_fixed_bl ,
fixed_instr_o => p0_tg_fixed_instr,
fixed_addr_o => p0_tg_fixed_addr
);
m_traffic_gen_p0 : mcb_traffic_gen
generic map(
MEM_BURST_LEN => C_MEM_BURST_LEN,
MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
NUM_DQ_PINS => C_NUM_DQ_PINS,
DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
PORT_MODE => p0_PORT_MODE,
DWIDTH => p0_DWIDTH,
CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
FAMILY => FAMILY,
SIMULATION => "FALSE",
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => "CGEN_ALL",
ADDR_WIDTH => 30,
PRBS_SADDR_MASK_POS => C_p0_PRBS_SADDR_MASK_POS,
PRBS_EADDR_MASK_POS => C_p0_PRBS_EADDR_MASK_POS,
PRBS_SADDR => C_p0_BEGIN_ADDRESS,
PRBS_EADDR => C_p0_END_ADDRESS
)
port map
(
clk_i => clk0,
rst_i => rst0,
run_traffic_i => p0_tg_run_traffic,
manual_clear_error => rst0,
-- runtime parameter
start_addr_i => p0_tg_start_addr ,
end_addr_i => p0_tg_end_addr ,
cmd_seed_i => p0_tg_cmd_seed ,
data_seed_i => p0_tg_data_seed ,
load_seed_i => p0_tg_load_seed,
addr_mode_i => p0_tg_addr_mode,
instr_mode_i => p0_tg_instr_mode ,
bl_mode_i => p0_tg_bl_mode ,
data_mode_i => p0_tg_data_mode ,
mode_load_i => p0_tg_mode_load ,
-- fixed pattern inputs interface
fixed_bl_i => p0_tg_fixed_bl,
fixed_instr_i => p0_tg_fixed_instr,
fixed_addr_i => p0_tg_fixed_addr,
fixed_data_i => (others => '0'),
-- BRAM interface.
bram_cmd_i => (others => '0'),
bram_valid_i => '0',
bram_rdy_o => open,
-- MCB INTERFACE
mcb_cmd_en_o => p0_mcb_cmd_en_o_int,
mcb_cmd_instr_o => p0_mcb_cmd_instr_o_int,
mcb_cmd_bl_o => p0_mcb_cmd_bl_o_int,
mcb_cmd_addr_o => p0_mcb_cmd_addr_o_int,
mcb_cmd_full_i => p0_mcb_cmd_full_i,
mcb_wr_en_o => p0_mcb_wr_en_o_int,
mcb_wr_mask_o => p0_mcb_wr_mask_o,
mcb_wr_data_o => p0_mcb_wr_data_o,
mcb_wr_data_end_o => open,
mcb_wr_full_i => p0_mcb_wr_full_i,
mcb_wr_fifo_counts => p0_mcb_wr_fifo_counts,
mcb_rd_en_o => p0_mcb_rd_en_o,
mcb_rd_data_i => p0_mcb_rd_data_i,
mcb_rd_empty_i => p0_mcb_rd_empty_i,
mcb_rd_fifo_counts => p0_mcb_rd_fifo_counts,
-- status feedback
counts_rst => rst0,
wr_data_counts => open,
rd_data_counts => open,
cmp_data => p0_cmp_data,
cmp_data_valid => p0_cmp_data_valid,
cmp_error => p0_cmp_error,
error => p0_error,
error_status => p0_error_status,
mem_rd_data => open,
dq_error_bytelane_cmp => open,
cumlative_dq_lane_error => open
);
end architecture;
| gpl-3.0 | b8c6389e9feebf7636eddfbdbc93772e | 0.489015 | 3.527994 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/pcie_core/source/pcie_core.vhd | 1 | 61,781 | -------------------------------------------------------------------------------
--
-- (c) Copyright 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : pcie_core.vhd
-- Description: Spartan-6 solution wrapper : Endpoint for PCI Express
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_bit.all;
library unisim;
use unisim.vcomponents.all;
--synthesis translate_off
use unisim.vpkg.all;
library secureip;
use secureip.all;
--synthesis translate_on
entity pcie_core is
generic (
TL_TX_RAM_RADDR_LATENCY : integer := 0;
TL_TX_RAM_RDATA_LATENCY : integer := 2;
TL_RX_RAM_RADDR_LATENCY : integer := 0;
TL_RX_RAM_RDATA_LATENCY : integer := 2;
TL_RX_RAM_WRITE_LATENCY : integer := 0;
VC0_TX_LASTPACKET : integer := 14;
VC0_RX_RAM_LIMIT : bit_vector := x"7FF";
VC0_TOTAL_CREDITS_PH : integer := 32;
VC0_TOTAL_CREDITS_PD : integer := 211;
VC0_TOTAL_CREDITS_NPH : integer := 8;
VC0_TOTAL_CREDITS_CH : integer := 40;
VC0_TOTAL_CREDITS_CD : integer := 211;
VC0_CPL_INFINITE : boolean := TRUE;
BAR0 : bit_vector := x"FFFFFC00";
BAR1 : bit_vector := x"FFFFC000";
BAR2 : bit_vector := x"FF000000";
BAR3 : bit_vector := x"00000000";
BAR4 : bit_vector := x"00000000";
BAR5 : bit_vector := x"00000000";
EXPANSION_ROM : bit_vector := "0000000000000000000000";
DISABLE_BAR_FILTERING : boolean := FALSE;
DISABLE_ID_CHECK : boolean := FALSE;
TL_TFC_DISABLE : boolean := FALSE;
TL_TX_CHECKS_DISABLE : boolean := FALSE;
USR_CFG : boolean := FALSE;
USR_EXT_CFG : boolean := FALSE;
DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer := 2;
CLASS_CODE : bit_vector := x"050000";
CARDBUS_CIS_POINTER : bit_vector := x"00000000";
PCIE_CAP_CAPABILITY_VERSION : bit_vector := x"1";
PCIE_CAP_DEVICE_PORT_TYPE : bit_vector := x"0";
PCIE_CAP_SLOT_IMPLEMENTED : boolean := FALSE;
PCIE_CAP_INT_MSG_NUM : bit_vector := "00000";
DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT : integer := 0;
DEV_CAP_EXT_TAG_SUPPORTED : boolean := FALSE;
DEV_CAP_ENDPOINT_L0S_LATENCY : integer := 7;
DEV_CAP_ENDPOINT_L1_LATENCY : integer := 7;
SLOT_CAP_ATT_BUTTON_PRESENT : boolean := FALSE;
SLOT_CAP_ATT_INDICATOR_PRESENT : boolean := FALSE;
SLOT_CAP_POWER_INDICATOR_PRESENT : boolean := FALSE;
DEV_CAP_ROLE_BASED_ERROR : boolean := TRUE;
LINK_CAP_ASPM_SUPPORT : integer := 1;
LINK_CAP_L0S_EXIT_LATENCY : integer := 7;
LINK_CAP_L1_EXIT_LATENCY : integer := 7;
LL_ACK_TIMEOUT : bit_vector := x"0000";
LL_ACK_TIMEOUT_EN : boolean := FALSE;
LL_REPLAY_TIMEOUT : bit_vector := x"0000";
LL_REPLAY_TIMEOUT_EN : boolean := FALSE;
MSI_CAP_MULTIMSGCAP : integer := 0;
MSI_CAP_MULTIMSG_EXTENSION : integer := 0;
LINK_STATUS_SLOT_CLOCK_CONFIG : boolean := FALSE;
PLM_AUTO_CONFIG : boolean := FALSE;
FAST_TRAIN : boolean := FALSE;
ENABLE_RX_TD_ECRC_TRIM : boolean := FALSE;
DISABLE_SCRAMBLING : boolean := FALSE;
PM_CAP_VERSION : integer := 3;
PM_CAP_PME_CLOCK : boolean := FALSE;
PM_CAP_DSI : boolean := FALSE;
PM_CAP_AUXCURRENT : integer := 0;
PM_CAP_D1SUPPORT : boolean := TRUE;
PM_CAP_D2SUPPORT : boolean := TRUE;
PM_CAP_PMESUPPORT : bit_vector := x"0F";
PM_DATA0 : bit_vector := x"00";
PM_DATA_SCALE0 : bit_vector := x"0";
PM_DATA1 : bit_vector := x"00";
PM_DATA_SCALE1 : bit_vector := x"0";
PM_DATA2 : bit_vector := x"00";
PM_DATA_SCALE2 : bit_vector := x"0";
PM_DATA3 : bit_vector := x"00";
PM_DATA_SCALE3 : bit_vector := x"0";
PM_DATA4 : bit_vector := x"00";
PM_DATA_SCALE4 : bit_vector := x"0";
PM_DATA5 : bit_vector := x"00";
PM_DATA_SCALE5 : bit_vector := x"0";
PM_DATA6 : bit_vector := x"00";
PM_DATA_SCALE6 : bit_vector := x"0";
PM_DATA7 : bit_vector := x"00";
PM_DATA_SCALE7 : bit_vector := x"0";
PCIE_GENERIC : bit_vector := "000011101111";
GTP_SEL : integer := 0;
CFG_VEN_ID : std_logic_vector(15 downto 0) := x"10EE";
CFG_DEV_ID : std_logic_vector(15 downto 0) := x"0007";
CFG_REV_ID : std_logic_vector(7 downto 0) := x"00";
CFG_SUBSYS_VEN_ID : std_logic_vector(15 downto 0) := x"10EE";
CFG_SUBSYS_ID : std_logic_vector(15 downto 0) := x"0007";
REF_CLK_FREQ : integer := 1
);
port (
-- PCI Express Fabric Interface
pci_exp_txp : out std_logic;
pci_exp_txn : out std_logic;
pci_exp_rxp : in std_logic;
pci_exp_rxn : in std_logic;
-- Transaction (TRN) Interface
trn_lnk_up_n : out std_logic;
-- Tx
trn_td : in std_logic_vector(31 downto 0);
trn_tsof_n : in std_logic;
trn_teof_n : in std_logic;
trn_tsrc_rdy_n : in std_logic;
trn_tdst_rdy_n : out std_logic;
trn_terr_drop_n : out std_logic;
trn_tsrc_dsc_n : in std_logic;
trn_terrfwd_n : in std_logic;
trn_tbuf_av : out std_logic_vector(5 downto 0);
trn_tstr_n : in std_logic;
trn_tcfg_req_n : out std_logic;
trn_tcfg_gnt_n : in std_logic;
-- Rx
trn_rd : out std_logic_vector(31 downto 0);
trn_rsof_n : out std_logic;
trn_reof_n : out std_logic;
trn_rsrc_rdy_n : out std_logic;
trn_rsrc_dsc_n : out std_logic;
trn_rdst_rdy_n : in std_logic;
trn_rerrfwd_n : out std_logic;
trn_rnp_ok_n : in std_logic;
trn_rbar_hit_n : out std_logic_vector(6 downto 0);
trn_fc_sel : in std_logic_vector(2 downto 0);
trn_fc_nph : out std_logic_vector(7 downto 0);
trn_fc_npd : out std_logic_vector(11 downto 0);
trn_fc_ph : out std_logic_vector(7 downto 0);
trn_fc_pd : out std_logic_vector(11 downto 0);
trn_fc_cplh : out std_logic_vector(7 downto 0);
trn_fc_cpld : out std_logic_vector(11 downto 0);
-- Host (CFG) Interface
cfg_do : out std_logic_vector(31 downto 0);
cfg_rd_wr_done_n : out std_logic;
cfg_dwaddr : in std_logic_vector(9 downto 0);
cfg_rd_en_n : in std_logic;
cfg_err_ur_n : in std_logic;
cfg_err_cor_n : in std_logic;
cfg_err_ecrc_n : in std_logic;
cfg_err_cpl_timeout_n : in std_logic;
cfg_err_cpl_abort_n : in std_logic;
cfg_err_posted_n : in std_logic;
cfg_err_locked_n : in std_logic;
cfg_err_tlp_cpl_header : in std_logic_vector(47 downto 0);
cfg_err_cpl_rdy_n : out std_logic;
cfg_interrupt_n : in std_logic;
cfg_interrupt_rdy_n : out std_logic;
cfg_interrupt_assert_n : in std_logic;
cfg_interrupt_do : out std_logic_vector(7 downto 0);
cfg_interrupt_di : in std_logic_vector(7 downto 0);
cfg_interrupt_mmenable : out std_logic_vector(2 downto 0);
cfg_interrupt_msienable : out std_logic;
cfg_turnoff_ok_n : in std_logic;
cfg_to_turnoff_n : out std_logic;
cfg_pm_wake_n : in std_logic;
cfg_pcie_link_state_n : out std_logic_vector(2 downto 0);
cfg_trn_pending_n : in std_logic;
cfg_dsn : in std_logic_vector(63 downto 0);
cfg_bus_number : out std_logic_vector(7 downto 0);
cfg_device_number : out std_logic_vector(4 downto 0);
cfg_function_number : out std_logic_vector(2 downto 0);
cfg_status : out std_logic_vector(15 downto 0);
cfg_command : out std_logic_vector(15 downto 0);
cfg_dstatus : out std_logic_vector(15 downto 0);
cfg_dcommand : out std_logic_vector(15 downto 0);
cfg_lstatus : out std_logic_vector(15 downto 0);
cfg_lcommand : out std_logic_vector(15 downto 0);
-- System Interface
sys_clk : in std_logic;
sys_reset_n : in std_logic;
trn_clk : out std_logic;
trn_reset_n : out std_logic;
received_hot_reset : out std_logic
);
end pcie_core;
architecture rtl of pcie_core is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of rtl : architecture is
"pcie_core,s6_pcie_v1_4,{TL_TX_RAM_RADDR_LATENCY=0,TL_TX_RAM_RDATA_LATENCY=2,TL_RX_RAM_RADDR_LATENCY=0,TL_RX_RAM_RDATA_LATENCY=2,TL_RX_RAM_WRITE_LATENCY=0,VC0_TX_LASTPACKET=14,VC0_RX_RAM_LIMIT=7FF,VC0_TOTAL_CREDITS_PH=32,VC0_TOTAL_CREDITS_PD=211,VC0_TOTAL_CREDITS_NPH=8,VC0_TOTAL_CREDITS_CH=40,VC0_TOTAL_CREDITS_CD=211,VC0_CPL_INFINITE=TRUE,BAR0=FFFFFC00,BAR1=FFFFC000,BAR2=FF000000,BAR3=00000000,BAR4=00000000,BAR5=00000000,EXPANSION_ROM=000000,USR_CFG=FALSE,USR_EXT_CFG=FALSE,DEV_CAP_MAX_PAYLOAD_SUPPORTED=2,CLASS_CODE=050000,CARDBUS_CIS_POINTER=00000000,PCIE_CAP_CAPABILITY_VERSION=1,PCIE_CAP_DEVICE_PORT_TYPE=0,DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT=0,DEV_CAP_EXT_TAG_SUPPORTED=FALSE,DEV_CAP_ENDPOINT_L0S_LATENCY=7,DEV_CAP_ENDPOINT_L1_LATENCY=7,LINK_CAP_ASPM_SUPPORT=1,MSI_CAP_MULTIMSGCAP=0,MSI_CAP_MULTIMSG_EXTENSION=0,LINK_STATUS_SLOT_CLOCK_CONFIG=FALSE,ENABLE_RX_TD_ECRC_TRIM=FALSE,DISABLE_SCRAMBLING=FALSE,PM_CAP_DSI=FALSE,PM_CAP_D1SUPPORT=TRUE,PM_CAP_D2SUPPORT=TRUE,PM_CAP_PMESUPPORT=0F,PM_DATA0=00,PM_DATA_SCALE0=0,PM_DATA1=00,PM_DATA_SCALE1=0,PM_DATA2=00,PM_DATA_SCALE2=0,PM_DATA3=00,PM_DATA_SCALE3=0,PM_DATA4=00,PM_DATA_SCALE4=0,PM_DATA5=00,PM_DATA_SCALE5=0,PM_DATA6=00,PM_DATA_SCALE6=0,PM_DATA7=00,PM_DATA_SCALE7=0,PCIE_GENERIC=000010101111,GTP_SEL=0,CFG_VEN_ID=10EE,CFG_DEV_ID=0007,CFG_REV_ID=00,CFG_SUBSYS_VEN_ID=10EE,CFG_SUBSYS_ID=0007,REF_CLK_FREQ=1}";
------------------------
-- Function Declarations
------------------------
function CALC_CLKFBOUT_MULT(FREQ_SEL : integer) return integer is
begin
case FREQ_SEL is
when 0 => return 5; -- 100 MHz
when others => return 4; -- 125 MHz
end case;
end CALC_CLKFBOUT_MULT;
function CALC_CLKIN_PERIOD(FREQ_SEL : integer) return real is
begin
case FREQ_SEL is
when 0 => return 10.0; -- 100 MHz
when others => return 8.0; -- 125 MHz
end case;
end CALC_CLKIN_PERIOD;
function CALC_CLK25_DIVIDER(FREQ_SEL : integer) return integer is
begin
case FREQ_SEL is
when 0 => return 4; -- 100 MHz
when others => return 5; -- 125 MHz
end case;
end CALC_CLK25_DIVIDER;
function CALC_PLL_DIVSEL_FB(FREQ_SEL : integer) return integer is
begin
case FREQ_SEL is
when 0 => return 5; -- 100 MHz
when others => return 2; -- 125 MHz
end case;
end CALC_PLL_DIVSEL_FB;
function CALC_PLL_DIVSEL_REF(FREQ_SEL : integer) return integer is
begin
case FREQ_SEL is
when 0 => return 2; -- 100 MHz
when others => return 1; -- 125 MHz
end case;
end CALC_PLL_DIVSEL_REF;
function SIM_INT(SIMULATION : boolean) return integer is
begin
if SIMULATION then
return 1;
else
return 0;
end if;
end SIM_INT;
------------------------
-- Constant Declarations
------------------------
constant CLKFBOUT_MULT : integer := CALC_CLKFBOUT_MULT(REF_CLK_FREQ);
constant CLKIN_PERIOD : real := CALC_CLKIN_PERIOD(REF_CLK_FREQ);
constant GT_CLK25_DIVIDER : integer := CALC_CLK25_DIVIDER(REF_CLK_FREQ);
constant GT_PLL_DIVSEL_FB : integer := CALC_PLL_DIVSEL_FB(REF_CLK_FREQ);
constant GT_PLL_DIVSEL_REF : integer := CALC_PLL_DIVSEL_REF(REF_CLK_FREQ);
-------------------------
-- Component Declarations
-------------------------
component pcie_bram_top_s6 is
generic (
DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer := 0;
VC0_TX_LASTPACKET : integer := 31;
TLM_TX_OVERHEAD : integer := 24;
TL_TX_RAM_RADDR_LATENCY : integer := 1;
TL_TX_RAM_RDATA_LATENCY : integer := 1;
TL_TX_RAM_WRITE_LATENCY : integer := 1;
VC0_RX_LIMIT : integer := 16#1FFF#;
TL_RX_RAM_RADDR_LATENCY : integer := 1;
TL_RX_RAM_RDATA_LATENCY : integer := 1;
TL_RX_RAM_WRITE_LATENCY : integer := 1
);
port (
user_clk_i : in std_logic;
reset_i : in std_logic;
mim_tx_wen : in std_logic;
mim_tx_waddr : in std_logic_vector(11 downto 0);
mim_tx_wdata : in std_logic_vector(35 downto 0);
mim_tx_ren : in std_logic;
mim_tx_rce : in std_logic;
mim_tx_raddr : in std_logic_vector(11 downto 0);
mim_tx_rdata : out std_logic_vector(35 downto 0);
mim_rx_wen : in std_logic;
mim_rx_waddr : in std_logic_vector(11 downto 0);
mim_rx_wdata : in std_logic_vector(35 downto 0);
mim_rx_ren : in std_logic;
mim_rx_rce : in std_logic;
mim_rx_raddr : in std_logic_vector(11 downto 0);
mim_rx_rdata : out std_logic_vector(35 downto 0)
);
end component pcie_bram_top_s6;
component GTPA1_DUAL_WRAPPER is
generic
(
-- Simulation attributes
WRAPPER_SIM_GTPRESET_SPEEDUP : integer := 0; -- Set to 1 to speed up sim reset
WRAPPER_CLK25_DIVIDER_0 : integer := 4;
WRAPPER_CLK25_DIVIDER_1 : integer := 4;
WRAPPER_PLL_DIVSEL_FB_0 : integer := 5;
WRAPPER_PLL_DIVSEL_FB_1 : integer := 5;
WRAPPER_PLL_DIVSEL_REF_0 : integer := 2;
WRAPPER_PLL_DIVSEL_REF_1 : integer := 2;
WRAPPER_SIMULATION : integer := 0 -- Set to 1 for simulation
);
port
(
--_________________________________________________________________________
--_________________________________________________________________________
--TILE0 (X0_Y0)
------------------------ Loopback and Powerdown Ports ----------------------
TILE0_RXPOWERDOWN0_IN : in std_logic_vector(1 downto 0);
TILE0_RXPOWERDOWN1_IN : in std_logic_vector(1 downto 0);
TILE0_TXPOWERDOWN0_IN : in std_logic_vector(1 downto 0);
TILE0_TXPOWERDOWN1_IN : in std_logic_vector(1 downto 0);
--------------------------------- PLL Ports --------------------------------
TILE0_CLK00_IN : in std_logic;
TILE0_CLK01_IN : in std_logic;
TILE0_GTPRESET0_IN : in std_logic;
TILE0_GTPRESET1_IN : in std_logic;
TILE0_PLLLKDET0_OUT : out std_logic;
TILE0_PLLLKDET1_OUT : out std_logic;
TILE0_RESETDONE0_OUT : out std_logic;
TILE0_RESETDONE1_OUT : out std_logic;
----------------------- Receive Ports - 8b10b Decoder ----------------------
TILE0_RXCHARISK0_OUT : out std_logic_vector(1 downto 0);
TILE0_RXCHARISK1_OUT : out std_logic_vector(1 downto 0);
TILE0_RXDISPERR0_OUT : out std_logic_vector(1 downto 0);
TILE0_RXDISPERR1_OUT : out std_logic_vector(1 downto 0);
TILE0_RXNOTINTABLE0_OUT : out std_logic_vector(1 downto 0);
TILE0_RXNOTINTABLE1_OUT : out std_logic_vector(1 downto 0);
---------------------- Receive Ports - Clock Correction --------------------
TILE0_RXCLKCORCNT0_OUT : out std_logic_vector(2 downto 0);
TILE0_RXCLKCORCNT1_OUT : out std_logic_vector(2 downto 0);
--------------- Receive Ports - Comma Detection and Alignment --------------
TILE0_RXENMCOMMAALIGN0_IN : in std_logic;
TILE0_RXENMCOMMAALIGN1_IN : in std_logic;
TILE0_RXENPCOMMAALIGN0_IN : in std_logic;
TILE0_RXENPCOMMAALIGN1_IN : in std_logic;
------------------- Receive Ports - RX Data Path interface -----------------
TILE0_RXDATA0_OUT : out std_logic_vector(15 downto 0);
TILE0_RXDATA1_OUT : out std_logic_vector(15 downto 0);
TILE0_RXRESET0_IN : in std_logic;
TILE0_RXRESET1_IN : in std_logic;
TILE0_RXUSRCLK0_IN : in std_logic;
TILE0_RXUSRCLK1_IN : in std_logic;
TILE0_RXUSRCLK20_IN : in std_logic;
TILE0_RXUSRCLK21_IN : in std_logic;
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
TILE0_GATERXELECIDLE0_IN : in std_logic;
TILE0_GATERXELECIDLE1_IN : in std_logic;
TILE0_IGNORESIGDET0_IN : in std_logic;
TILE0_IGNORESIGDET1_IN : in std_logic;
TILE0_RXELECIDLE0_OUT : out std_logic;
TILE0_RXELECIDLE1_OUT : out std_logic;
TILE0_RXN0_IN : in std_logic;
TILE0_RXN1_IN : in std_logic;
TILE0_RXP0_IN : in std_logic;
TILE0_RXP1_IN : in std_logic;
----------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------
TILE0_RXSTATUS0_OUT : out std_logic_vector(2 downto 0);
TILE0_RXSTATUS1_OUT : out std_logic_vector(2 downto 0);
-------------- Receive Ports - RX Pipe Control for PCI Express -------------
TILE0_PHYSTATUS0_OUT : out std_logic;
TILE0_PHYSTATUS1_OUT : out std_logic;
TILE0_RXVALID0_OUT : out std_logic;
TILE0_RXVALID1_OUT : out std_logic;
-------------------- Receive Ports - RX Polarity Control -------------------
TILE0_RXPOLARITY0_IN : in std_logic;
TILE0_RXPOLARITY1_IN : in std_logic;
---------------------------- TX/RX Datapath Ports --------------------------
TILE0_GTPCLKOUT0_OUT : out std_logic_vector(1 downto 0);
TILE0_GTPCLKOUT1_OUT : out std_logic_vector(1 downto 0);
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TILE0_TXCHARDISPMODE0_IN : in std_logic_vector(1 downto 0);
TILE0_TXCHARDISPMODE1_IN : in std_logic_vector(1 downto 0);
TILE0_TXCHARISK0_IN : in std_logic_vector(1 downto 0);
TILE0_TXCHARISK1_IN : in std_logic_vector(1 downto 0);
------------------ Transmit Ports - TX Data Path interface -----------------
TILE0_TXDATA0_IN : in std_logic_vector(15 downto 0);
TILE0_TXDATA1_IN : in std_logic_vector(15 downto 0);
TILE0_TXUSRCLK0_IN : in std_logic;
TILE0_TXUSRCLK1_IN : in std_logic;
TILE0_TXUSRCLK20_IN : in std_logic;
TILE0_TXUSRCLK21_IN : in std_logic;
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TILE0_TXN0_OUT : out std_logic;
TILE0_TXN1_OUT : out std_logic;
TILE0_TXP0_OUT : out std_logic;
TILE0_TXP1_OUT : out std_logic;
----------------- Transmit Ports - TX Ports for PCI Express ----------------
TILE0_TXDETECTRX0_IN : in std_logic;
TILE0_TXDETECTRX1_IN : in std_logic;
TILE0_TXELECIDLE0_IN : in std_logic;
TILE0_TXELECIDLE1_IN : in std_logic
);
end component GTPA1_DUAL_WRAPPER;
----------------------
-- Signal Declarations
----------------------
-- PLL Signals
signal mgt_clk : std_logic;
signal mgt_clk_2x : std_logic;
signal clock_locked : std_logic;
signal gt_refclk_out : std_logic_vector(1 downto 0);
signal gt_clk_fb_west_out : std_logic;
signal pll_rst : std_logic;
signal clk_125 : std_logic;
signal clk_250 : std_logic;
signal clk_62_5 : std_logic;
signal gt_refclk_buf : std_logic;
signal gt_refclk_fb : std_logic;
signal w_cfg_ven_id : std_logic_vector(15 downto 0);
signal w_cfg_dev_id : std_logic_vector(15 downto 0);
signal w_cfg_rev_id : std_logic_vector(7 downto 0);
signal w_cfg_subsys_ven_id : std_logic_vector(15 downto 0);
signal w_cfg_subsys_id : std_logic_vector(15 downto 0);
signal cfg_ltssm_state : std_logic_vector(4 downto 0);
signal cfg_link_control_aspm_control : std_logic_vector(1 downto 0);
signal cfg_link_control_rcb : std_logic;
signal cfg_link_control_common_clock : std_logic;
signal cfg_link_control_extended_sync : std_logic;
signal cfg_command_interrupt_disable : std_logic;
signal cfg_command_serr_en : std_logic;
signal cfg_command_bus_master_enable : std_logic;
signal cfg_command_mem_enable : std_logic;
signal cfg_command_io_enable : std_logic;
signal cfg_dev_status_ur_detected : std_logic;
signal cfg_dev_status_fatal_err_detected : std_logic;
signal cfg_dev_status_nonfatal_err_detected : std_logic;
signal cfg_dev_status_corr_err_detected : std_logic;
signal cfg_dev_control_max_read_req : std_logic_vector(2 downto 0);
signal cfg_dev_control_no_snoop_en : std_logic;
signal cfg_dev_control_aux_power_en : std_logic;
signal cfg_dev_control_phantom_en : std_logic;
signal cfg_dev_cntrol_ext_tag_en : std_logic;
signal cfg_dev_control_max_payload : std_logic_vector(2 downto 0);
signal cfg_dev_control_enable_ro : std_logic;
signal cfg_dev_control_ext_tag_en : std_logic;
signal cfg_dev_control_ur_err_reporting_en : std_logic;
signal cfg_dev_control_fatal_err_reporting_en : std_logic;
signal cfg_dev_control_non_fatal_reporting_en : std_logic;
signal cfg_dev_control_corr_err_reporting_en : std_logic;
signal mim_tx_waddr : std_logic_vector(11 downto 0);
signal mim_tx_raddr : std_logic_vector(11 downto 0);
signal mim_rx_waddr : std_logic_vector(11 downto 0);
signal mim_rx_raddr : std_logic_vector(11 downto 0);
signal mim_tx_wdata : std_logic_vector(35 downto 0);
signal mim_tx_rdata : std_logic_vector(35 downto 0);
signal mim_rx_wdata : std_logic_vector(34 downto 0);
signal mim_rx_rdata_unused : std_logic;
signal mim_rx_rdata : std_logic_vector(34 downto 0);
signal mim_tx_wen : std_logic;
signal mim_tx_ren : std_logic;
signal mim_rx_wen : std_logic;
signal mim_rx_ren : std_logic;
signal dbg_bad_dllp_status : std_logic;
signal dbg_bad_tlp_lcrc : std_logic;
signal dbg_bad_tlp_seq_num : std_logic;
signal dbg_bad_tlp_status : std_logic;
signal dbg_dl_protocol_status : std_logic;
signal dbg_fc_protocol_err_status : std_logic;
signal dbg_mlfrmd_length : std_logic;
signal dbg_mlfrmd_mps : std_logic;
signal dbg_mlfrmd_tcvc : std_logic;
signal dbg_mlfrmd_tlp_status : std_logic;
signal dbg_mlfrmd_unrec_type : std_logic;
signal dbg_poistlpstatus : std_logic;
signal dbg_rcvr_overflow_status : std_logic;
signal dbg_reg_detected_correctable : std_logic;
signal dbg_reg_detected_fatal : std_logic;
signal dbg_reg_detected_non_fatal : std_logic;
signal dbg_reg_detected_unsupported : std_logic;
signal dbg_rply_rollover_status : std_logic;
signal dbg_rply_timeout_status : std_logic;
signal dbg_ur_no_bar_hit : std_logic;
signal dbg_ur_pois_cfg_wr : std_logic;
signal dbg_ur_status : std_logic;
signal dbg_ur_unsup_msg : std_logic;
signal pipe_gt_power_down_a : std_logic_vector(1 downto 0);
signal pipe_gt_power_down_b : std_logic_vector(1 downto 0);
signal pipe_gt_reset_done_a : std_logic;
signal pipe_gt_reset_done_b : std_logic;
signal pipe_gt_tx_elec_idle_a : std_logic;
signal pipe_gt_tx_elec_idle_b : std_logic;
signal pipe_phy_status_a : std_logic;
signal pipe_phy_status_b : std_logic;
signal pipe_rx_charisk_a : std_logic_vector(1 downto 0);
signal pipe_rx_charisk_b : std_logic_vector(1 downto 0);
signal pipe_rx_data_a : std_logic_vector(15 downto 0);
signal pipe_rx_data_b : std_logic_vector(15 downto 0);
signal pipe_rx_enter_elec_idle_a : std_logic;
signal pipe_rx_enter_elec_idle_b : std_logic;
signal pipe_rx_polarity_a : std_logic;
signal pipe_rx_polarity_b : std_logic;
signal pipe_rxreset_a : std_logic;
signal pipe_rxreset_b : std_logic;
signal pipe_rx_status_a : std_logic_vector(2 downto 0);
signal pipe_rx_status_b : std_logic_vector(2 downto 0);
signal pipe_tx_char_disp_mode_a : std_logic_vector(1 downto 0);
signal pipe_tx_char_disp_mode_b : std_logic_vector(1 downto 0);
signal pipe_tx_char_disp_val_a : std_logic_vector(1 downto 0);
signal pipe_tx_char_disp_val_b : std_logic_vector(1 downto 0);
signal pipe_tx_char_is_k_a : std_logic_vector(1 downto 0);
signal pipe_tx_char_is_k_b : std_logic_vector(1 downto 0);
signal pipe_tx_data_a : std_logic_vector(15 downto 0);
signal pipe_tx_data_b : std_logic_vector(15 downto 0);
signal pipe_tx_rcvr_det_a : std_logic;
signal pipe_tx_rcvr_det_b : std_logic;
-- GT->PLM PIPE Interface rx
signal rx_char_is_k : std_logic_vector(1 downto 0);
signal rx_data : std_logic_vector(15 downto 0);
signal rx_enter_elecidle : std_logic;
signal rx_status : std_logic_vector(2 downto 0);
signal rx_polarity : std_logic;
-- GT<-PLM PIPE Interface tx
signal tx_char_disp_mode : std_logic_vector(1 downto 0);
signal tx_char_is_k : std_logic_vector(1 downto 0);
signal tx_rcvr_det : std_logic;
signal tx_data : std_logic_vector(15 downto 0);
-- GT<->PLM PIPE Interface Misc
signal phystatus : std_logic;
-- GT<->PLM PIPE Interface MGT Logic I/O
signal gt_reset_done : std_logic;
signal gt_rx_valid : std_logic;
signal gt_tx_elec_idle : std_logic;
signal gt_power_down : std_logic_vector(1 downto 0);
signal rxreset : std_logic;
signal gt_plllkdet_out : std_logic;
signal sys_reset : std_logic;
-- Core outputs which are also used in this module - must make local copies
signal trn_clk_c : std_logic;
signal trn_reset_n_c : std_logic;
signal trn_reset : std_logic;
begin
-- These values may be brought out and driven dynamically
-- from pins rather than attributes if desired. Note -
-- if they are not statically driven, the values must be
-- stable before sys_reset_n is released
w_cfg_ven_id <= CFG_VEN_ID;
w_cfg_dev_id <= CFG_DEV_ID;
w_cfg_rev_id <= CFG_REV_ID;
w_cfg_subsys_ven_id <= CFG_SUBSYS_VEN_ID;
w_cfg_subsys_id <= CFG_SUBSYS_ID;
-- Assign outputs from internal copies
trn_clk <= trn_clk_c;
trn_reset_n <= trn_reset_n_c;
trn_reset <= not trn_reset_n_c;
-- Buffer reference clock from MGT
gt_refclk_bufio2 : BUFIO2
port map (
DIVCLK => gt_refclk_buf,
IOCLK => OPEN,
SERDESSTROBE => OPEN,
I => gt_refclk_out(0)
);
pll_base_i : PLL_BASE
generic map (
CLKFBOUT_MULT => CLKFBOUT_MULT,
CLKFBOUT_PHASE => 0.0,
CLKIN_PERIOD => CLKIN_PERIOD,
CLKOUT0_DIVIDE => 2,
CLKOUT0_PHASE => 0.0,
CLKOUT1_DIVIDE => 4,
CLKOUT1_PHASE => 0.0,
CLKOUT2_DIVIDE => 8,
CLKOUT2_PHASE => 0.0,
COMPENSATION => "INTERNAL"
)
port map (
CLKIN => gt_refclk_buf,
CLKFBIN => gt_refclk_fb,
RST => pll_rst,
CLKOUT0 => clk_250,
CLKOUT1 => clk_125,
CLKOUT2 => clk_62_5,
CLKOUT3 => OPEN,
CLKOUT4 => OPEN,
CLKOUT5 => OPEN,
CLKFBOUT => gt_refclk_fb,
LOCKED => clock_locked
);
-------------------------------------
-- Instantiate buffers where required
-------------------------------------
mgt_bufg : BUFG port map (O => mgt_clk, I => clk_125);
mgt2x_bufg : BUFG port map (O => mgt_clk_2x, I => clk_250);
phy_bufg : BUFG port map (O => trn_clk_c, I => clk_62_5);
----------------------------
-- PCI Express BRAM Instance
----------------------------
pcie_bram_top: pcie_bram_top_s6
generic map (
DEV_CAP_MAX_PAYLOAD_SUPPORTED => DEV_CAP_MAX_PAYLOAD_SUPPORTED,
VC0_TX_LASTPACKET => VC0_TX_LASTPACKET,
TLM_TX_OVERHEAD => 20,
TL_TX_RAM_RADDR_LATENCY => TL_TX_RAM_RADDR_LATENCY,
TL_TX_RAM_RDATA_LATENCY => TL_TX_RAM_RDATA_LATENCY,
-- NOTE: use the RX value here since there is no separate TX value
TL_TX_RAM_WRITE_LATENCY => TL_RX_RAM_WRITE_LATENCY,
VC0_RX_LIMIT => conv_integer(to_stdlogicvector(VC0_RX_RAM_LIMIT)),
TL_RX_RAM_RADDR_LATENCY => TL_RX_RAM_RADDR_LATENCY,
TL_RX_RAM_RDATA_LATENCY => TL_RX_RAM_RDATA_LATENCY,
TL_RX_RAM_WRITE_LATENCY => TL_RX_RAM_WRITE_LATENCY
)
port map (
user_clk_i => trn_clk_c,
reset_i => trn_reset,
mim_tx_waddr => mim_tx_waddr,
mim_tx_wen => mim_tx_wen,
mim_tx_ren => mim_tx_ren,
mim_tx_rce => '1',
mim_tx_wdata => mim_tx_wdata,
mim_tx_raddr => mim_tx_raddr,
mim_tx_rdata => mim_tx_rdata,
mim_rx_waddr => mim_rx_waddr,
mim_rx_wen => mim_rx_wen,
mim_rx_ren => mim_rx_ren,
mim_rx_rce => '1',
mim_rx_wdata(35) => '0',
mim_rx_wdata(34 downto 0) => mim_rx_wdata,
mim_rx_raddr => mim_rx_raddr,
mim_rx_rdata(35) => mim_rx_rdata_unused,
mim_rx_rdata(34 downto 0) => mim_rx_rdata
);
---------------------------------
-- PCI Express GTA1_DUAL Instance
---------------------------------
sys_reset <= not sys_reset_n;
GT_i : GTPA1_DUAL_WRAPPER
generic map (
-- Simulation attributes
WRAPPER_SIM_GTPRESET_SPEEDUP => 1,
WRAPPER_CLK25_DIVIDER_0 => GT_CLK25_DIVIDER,
WRAPPER_CLK25_DIVIDER_1 => GT_CLK25_DIVIDER,
WRAPPER_PLL_DIVSEL_FB_0 => GT_PLL_DIVSEL_FB,
WRAPPER_PLL_DIVSEL_FB_1 => GT_PLL_DIVSEL_FB,
WRAPPER_PLL_DIVSEL_REF_0 => GT_PLL_DIVSEL_REF,
WRAPPER_PLL_DIVSEL_REF_1 => GT_PLL_DIVSEL_REF,
WRAPPER_SIMULATION => SIM_INT(FAST_TRAIN)
)
port map (
------------------------ Loopback and Powerdown Ports ----------------------
TILE0_RXPOWERDOWN0_IN => gt_power_down,
TILE0_RXPOWERDOWN1_IN => "10",
TILE0_TXPOWERDOWN0_IN => gt_power_down,
TILE0_TXPOWERDOWN1_IN => "10",
--------------------------------- PLL Ports --------------------------------
TILE0_CLK00_IN => sys_clk,
TILE0_CLK01_IN => '0',
TILE0_GTPRESET0_IN => sys_reset,
TILE0_GTPRESET1_IN => '1',
TILE0_PLLLKDET0_OUT => gt_plllkdet_out,
TILE0_PLLLKDET1_OUT => OPEN,
TILE0_RESETDONE0_OUT => gt_reset_done,
TILE0_RESETDONE1_OUT => OPEN,
----------------------- Receive Ports - 8b10b Decoder ----------------------
TILE0_RXCHARISK0_OUT(1) => rx_char_is_k(0),
TILE0_RXCHARISK0_OUT(0) => rx_char_is_k(1),
TILE0_RXCHARISK1_OUT => OPEN,
TILE0_RXDISPERR0_OUT => OPEN,
TILE0_RXDISPERR1_OUT => OPEN,
TILE0_RXNOTINTABLE0_OUT => OPEN,
TILE0_RXNOTINTABLE1_OUT => OPEN,
---------------------- Receive Ports - Clock Correction --------------------
TILE0_RXCLKCORCNT0_OUT => OPEN,
TILE0_RXCLKCORCNT1_OUT => OPEN,
--------------- Receive Ports - Comma Detection and Alignment --------------
TILE0_RXENMCOMMAALIGN0_IN => '1',
TILE0_RXENMCOMMAALIGN1_IN => '1',
TILE0_RXENPCOMMAALIGN0_IN => '1',
TILE0_RXENPCOMMAALIGN1_IN => '1',
------------------- Receive Ports - RX Data Path interface -----------------
TILE0_RXDATA0_OUT(15 downto 8) => rx_data(7 downto 0),
TILE0_RXDATA0_OUT(7 downto 0) => rx_data(15 downto 8),
TILE0_RXDATA1_OUT => OPEN,
TILE0_RXRESET0_IN => rxreset,
TILE0_RXRESET1_IN => '1',
TILE0_RXUSRCLK0_IN => mgt_clk_2x,
TILE0_RXUSRCLK1_IN => '0',
TILE0_RXUSRCLK20_IN => mgt_clk,
TILE0_RXUSRCLK21_IN => '0',
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
TILE0_GATERXELECIDLE0_IN => '0',
TILE0_GATERXELECIDLE1_IN => '0',
TILE0_IGNORESIGDET0_IN => '0',
TILE0_IGNORESIGDET1_IN => '0',
TILE0_RXELECIDLE0_OUT => rx_enter_elecidle,
TILE0_RXELECIDLE1_OUT => OPEN,
TILE0_RXN0_IN => pci_exp_rxn,
TILE0_RXN1_IN => '0',
TILE0_RXP0_IN => pci_exp_rxp,
TILE0_RXP1_IN => '0',
----------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------
TILE0_RXSTATUS0_OUT => rx_status,
TILE0_RXSTATUS1_OUT => OPEN,
-------------- Receive Ports - RX Pipe Control for PCI Express -------------
TILE0_PHYSTATUS0_OUT => phystatus,
TILE0_PHYSTATUS1_OUT => OPEN,
TILE0_RXVALID0_OUT => gt_rx_valid,
TILE0_RXVALID1_OUT => OPEN,
-------------------- Receive Ports - RX Polarity Control -------------------
TILE0_RXPOLARITY0_IN => rx_polarity,
TILE0_RXPOLARITY1_IN => '0',
---------------------------- TX/RX Datapath Ports --------------------------
TILE0_GTPCLKOUT0_OUT => gt_refclk_out,
TILE0_GTPCLKOUT1_OUT => OPEN,
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TILE0_TXCHARDISPMODE0_IN(1) => tx_char_disp_mode(0),
TILE0_TXCHARDISPMODE0_IN(0) => tx_char_disp_mode(1),
TILE0_TXCHARDISPMODE1_IN(1) => '0',
TILE0_TXCHARDISPMODE1_IN(0) => '0',
TILE0_TXCHARISK0_IN(1) => tx_char_is_k(0),
TILE0_TXCHARISK0_IN(0) => tx_char_is_k(1),
TILE0_TXCHARISK1_IN(1) => '0',
TILE0_TXCHARISK1_IN(0) => '0',
------------------ Transmit Ports - TX Data Path interface -----------------
TILE0_TXDATA0_IN(15 downto 8) => tx_data(7 downto 0),
TILE0_TXDATA0_IN(7 downto 0) => tx_data(15 downto 8),
TILE0_TXDATA1_IN(15 downto 8) => x"00",
TILE0_TXDATA1_IN(7 downto 0) => x"00",
TILE0_TXUSRCLK0_IN => mgt_clk_2x,
TILE0_TXUSRCLK1_IN => '0',
TILE0_TXUSRCLK20_IN => mgt_clk,
TILE0_TXUSRCLK21_IN => '0',
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TILE0_TXN0_OUT => pci_exp_txn,
TILE0_TXN1_OUT => OPEN,
TILE0_TXP0_OUT => pci_exp_txp,
TILE0_TXP1_OUT => OPEN,
----------------- Transmit Ports - TX Ports for PCI Express ----------------
TILE0_TXDETECTRX0_IN => tx_rcvr_det,
TILE0_TXDETECTRX1_IN => '0',
TILE0_TXELECIDLE0_IN => gt_tx_elec_idle,
TILE0_TXELECIDLE1_IN => '0' );
-- Generate the reset for the PLL
pll_rst <= (not gt_plllkdet_out) or (not sys_reset_n);
---------------------------------------------------------------------------
-- Generate the connection between PCIE_A1 block and the GTPA1_DUAL. When
-- the parameter GTP_SEL is 0, connect to PIPEA, when it is a 1, connect to
-- PIPEB.
---------------------------------------------------------------------------
PIPE_A_SEL : if (GTP_SEL = 0) generate
-- Signals from GTPA1_DUAL to PCIE_A1
pipe_rx_charisk_a <= rx_char_is_k;
pipe_rx_data_a <= rx_data;
pipe_rx_enter_elec_idle_a <= rx_enter_elecidle;
pipe_rx_status_a <= rx_status;
pipe_phy_status_a <= phystatus;
pipe_gt_reset_done_a <= gt_reset_done;
-- Unused PCIE_A1 inputs
pipe_rx_charisk_b <= "00";
pipe_rx_data_b <= x"0000";
pipe_rx_enter_elec_idle_b <= '0';
pipe_rx_status_b <= "000";
pipe_phy_status_b <= '0';
pipe_gt_reset_done_b <= '0';
-- Signals from PCIE_A1 to GTPA1_DUAL
rx_polarity <= pipe_rx_polarity_a;
tx_char_disp_mode <= pipe_tx_char_disp_mode_a;
tx_char_is_k <= pipe_tx_char_is_k_a;
tx_rcvr_det <= pipe_tx_rcvr_det_a;
tx_data <= pipe_tx_data_a;
gt_tx_elec_idle <= pipe_gt_tx_elec_idle_a;
gt_power_down <= pipe_gt_power_down_a;
rxreset <= pipe_rxreset_a;
end generate PIPE_A_SEL;
PIPE_B_SEL : if (GTP_SEL = 1) generate
-- Signals from GTPA1_DUAL to PCIE_A1
pipe_rx_charisk_b <= rx_char_is_k;
pipe_rx_data_b <= rx_data;
pipe_rx_enter_elec_idle_b <= rx_enter_elecidle;
pipe_rx_status_b <= rx_status;
pipe_phy_status_b <= phystatus;
pipe_gt_reset_done_b <= gt_reset_done;
-- Unused PCIE_A1 inputs
pipe_rx_charisk_a <= "00";
pipe_rx_data_a <= x"0000";
pipe_rx_enter_elec_idle_a <= '0';
pipe_rx_status_a <= "000";
pipe_phy_status_a <= '0';
pipe_gt_reset_done_a <= '0';
-- Signals from PCIE_A1 to GTPA1_DUAL
rx_polarity <= pipe_rx_polarity_b;
tx_char_disp_mode <= pipe_tx_char_disp_mode_b;
tx_char_is_k <= pipe_tx_char_is_k_b;
tx_rcvr_det <= pipe_tx_rcvr_det_b;
tx_data <= pipe_tx_data_b;
gt_tx_elec_idle <= pipe_gt_tx_elec_idle_b;
gt_power_down <= pipe_gt_power_down_b;
rxreset <= pipe_rxreset_b;
end generate PIPE_B_SEL;
---------------------------------------------------------------
-- Integrated Endpoint Block for PCI Express Instance (PCIE_A1)
---------------------------------------------------------------
PCIE_A1_inst : PCIE_A1
generic map (
BAR0 => BAR0,
BAR1 => BAR1,
BAR2 => BAR2,
BAR3 => BAR3,
BAR4 => BAR4,
BAR5 => BAR5,
CARDBUS_CIS_POINTER => CARDBUS_CIS_POINTER,
CLASS_CODE => CLASS_CODE,
DEV_CAP_ENDPOINT_L0S_LATENCY => DEV_CAP_ENDPOINT_L0S_LATENCY,
DEV_CAP_ENDPOINT_L1_LATENCY => DEV_CAP_ENDPOINT_L1_LATENCY,
DEV_CAP_EXT_TAG_SUPPORTED => DEV_CAP_EXT_TAG_SUPPORTED,
DEV_CAP_MAX_PAYLOAD_SUPPORTED => DEV_CAP_MAX_PAYLOAD_SUPPORTED,
DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT => DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT,
DEV_CAP_ROLE_BASED_ERROR => DEV_CAP_ROLE_BASED_ERROR,
DISABLE_BAR_FILTERING => DISABLE_BAR_FILTERING,
DISABLE_ID_CHECK => DISABLE_ID_CHECK,
DISABLE_SCRAMBLING => DISABLE_SCRAMBLING,
ENABLE_RX_TD_ECRC_TRIM => ENABLE_RX_TD_ECRC_TRIM,
EXPANSION_ROM => EXPANSION_ROM,
FAST_TRAIN => FAST_TRAIN,
GTP_SEL => GTP_SEL,
LINK_CAP_ASPM_SUPPORT => LINK_CAP_ASPM_SUPPORT,
LINK_CAP_L0S_EXIT_LATENCY => LINK_CAP_L0S_EXIT_LATENCY,
LINK_CAP_L1_EXIT_LATENCY => LINK_CAP_L1_EXIT_LATENCY,
LINK_STATUS_SLOT_CLOCK_CONFIG => LINK_STATUS_SLOT_CLOCK_CONFIG,
LL_ACK_TIMEOUT => LL_ACK_TIMEOUT,
LL_ACK_TIMEOUT_EN => LL_ACK_TIMEOUT_EN,
LL_REPLAY_TIMEOUT => LL_REPLAY_TIMEOUT,
LL_REPLAY_TIMEOUT_EN => LL_REPLAY_TIMEOUT_EN,
MSI_CAP_MULTIMSG_EXTENSION => MSI_CAP_MULTIMSG_EXTENSION,
MSI_CAP_MULTIMSGCAP => MSI_CAP_MULTIMSGCAP,
PCIE_CAP_CAPABILITY_VERSION => PCIE_CAP_CAPABILITY_VERSION,
PCIE_CAP_DEVICE_PORT_TYPE => PCIE_CAP_DEVICE_PORT_TYPE,
PCIE_CAP_INT_MSG_NUM => PCIE_CAP_INT_MSG_NUM,
PCIE_CAP_SLOT_IMPLEMENTED => PCIE_CAP_SLOT_IMPLEMENTED,
PCIE_GENERIC => PCIE_GENERIC,
PLM_AUTO_CONFIG => PLM_AUTO_CONFIG,
PM_CAP_AUXCURRENT => PM_CAP_AUXCURRENT,
PM_CAP_DSI => PM_CAP_DSI,
PM_CAP_D1SUPPORT => PM_CAP_D1SUPPORT,
PM_CAP_D2SUPPORT => PM_CAP_D2SUPPORT,
PM_CAP_PME_CLOCK => PM_CAP_PME_CLOCK,
PM_CAP_PMESUPPORT => PM_CAP_PMESUPPORT,
PM_CAP_VERSION => PM_CAP_VERSION,
PM_DATA_SCALE0 => PM_DATA_SCALE0,
PM_DATA_SCALE1 => PM_DATA_SCALE1,
PM_DATA_SCALE2 => PM_DATA_SCALE2,
PM_DATA_SCALE3 => PM_DATA_SCALE3,
PM_DATA_SCALE4 => PM_DATA_SCALE4,
PM_DATA_SCALE5 => PM_DATA_SCALE5,
PM_DATA_SCALE6 => PM_DATA_SCALE6,
PM_DATA_SCALE7 => PM_DATA_SCALE7,
PM_DATA0 => PM_DATA0,
PM_DATA1 => PM_DATA1,
PM_DATA2 => PM_DATA2,
PM_DATA3 => PM_DATA3,
PM_DATA4 => PM_DATA4,
PM_DATA5 => PM_DATA5,
PM_DATA6 => PM_DATA6,
PM_DATA7 => PM_DATA7,
SLOT_CAP_ATT_BUTTON_PRESENT => SLOT_CAP_ATT_BUTTON_PRESENT,
SLOT_CAP_ATT_INDICATOR_PRESENT => SLOT_CAP_ATT_INDICATOR_PRESENT,
SLOT_CAP_POWER_INDICATOR_PRESENT => SLOT_CAP_POWER_INDICATOR_PRESENT,
TL_RX_RAM_RADDR_LATENCY => TL_RX_RAM_RADDR_LATENCY,
TL_RX_RAM_RDATA_LATENCY => TL_RX_RAM_RDATA_LATENCY,
TL_RX_RAM_WRITE_LATENCY => TL_RX_RAM_WRITE_LATENCY,
TL_TFC_DISABLE => TL_TFC_DISABLE,
TL_TX_CHECKS_DISABLE => TL_TX_CHECKS_DISABLE,
TL_TX_RAM_RADDR_LATENCY => TL_TX_RAM_RADDR_LATENCY,
TL_TX_RAM_RDATA_LATENCY => TL_TX_RAM_RDATA_LATENCY,
USR_CFG => USR_CFG,
USR_EXT_CFG => USR_EXT_CFG,
VC0_CPL_INFINITE => VC0_CPL_INFINITE,
VC0_RX_RAM_LIMIT => VC0_RX_RAM_LIMIT,
VC0_TOTAL_CREDITS_CD => VC0_TOTAL_CREDITS_CD,
VC0_TOTAL_CREDITS_CH => VC0_TOTAL_CREDITS_CH,
VC0_TOTAL_CREDITS_NPH => VC0_TOTAL_CREDITS_NPH,
VC0_TOTAL_CREDITS_PD => VC0_TOTAL_CREDITS_PD,
VC0_TOTAL_CREDITS_PH => VC0_TOTAL_CREDITS_PH,
VC0_TX_LASTPACKET => VC0_TX_LASTPACKET
)
port map (
CFGBUSNUMBER => cfg_bus_number,
CFGCOMMANDBUSMASTERENABLE => cfg_command_bus_master_enable,
CFGCOMMANDINTERRUPTDISABLE => cfg_command_interrupt_disable,
CFGCOMMANDIOENABLE => cfg_command_io_enable,
CFGCOMMANDMEMENABLE => cfg_command_mem_enable,
CFGCOMMANDSERREN => cfg_command_serr_en,
CFGDEVCONTROLAUXPOWEREN => cfg_dev_control_aux_power_en,
CFGDEVCONTROLCORRERRREPORTINGEN => cfg_dev_control_corr_err_reporting_en,
CFGDEVCONTROLENABLERO => cfg_dev_control_enable_ro,
CFGDEVCONTROLEXTTAGEN => cfg_dev_control_ext_tag_en,
CFGDEVCONTROLFATALERRREPORTINGEN => cfg_dev_control_fatal_err_reporting_en,
CFGDEVCONTROLMAXPAYLOAD => cfg_dev_control_max_payload,
CFGDEVCONTROLMAXREADREQ => cfg_dev_control_max_read_req,
CFGDEVCONTROLNONFATALREPORTINGEN => cfg_dev_control_non_fatal_reporting_en,
CFGDEVCONTROLNOSNOOPEN => cfg_dev_control_no_snoop_en,
CFGDEVCONTROLPHANTOMEN => cfg_dev_control_phantom_en,
CFGDEVCONTROLURERRREPORTINGEN => cfg_dev_control_ur_err_reporting_en,
CFGDEVICENUMBER => cfg_device_number,
CFGDEVID => w_cfg_dev_id,
CFGDEVSTATUSCORRERRDETECTED => cfg_dev_status_corr_err_detected,
CFGDEVSTATUSFATALERRDETECTED => cfg_dev_status_fatal_err_detected,
CFGDEVSTATUSNONFATALERRDETECTED => cfg_dev_status_nonfatal_err_detected,
CFGDEVSTATUSURDETECTED => cfg_dev_status_ur_detected,
CFGDO => cfg_do,
CFGDSN => cfg_dsn,
CFGDWADDR => cfg_dwaddr,
CFGERRCORN => cfg_err_cor_n,
CFGERRCPLABORTN => cfg_err_cpl_abort_n,
CFGERRCPLRDYN => cfg_err_cpl_rdy_n,
CFGERRCPLTIMEOUTN => cfg_err_cpl_timeout_n,
CFGERRECRCN => cfg_err_ecrc_n,
CFGERRLOCKEDN => cfg_err_locked_n,
CFGERRPOSTEDN => cfg_err_posted_n,
CFGERRTLPCPLHEADER => cfg_err_tlp_cpl_header,
CFGERRURN => cfg_err_ur_n,
CFGFUNCTIONNUMBER => cfg_function_number,
CFGINTERRUPTASSERTN => cfg_interrupt_assert_n,
CFGINTERRUPTDI => cfg_interrupt_di,
CFGINTERRUPTDO => cfg_interrupt_do,
CFGINTERRUPTMMENABLE => cfg_interrupt_mmenable,
CFGINTERRUPTMSIENABLE => cfg_interrupt_msienable,
CFGINTERRUPTN => cfg_interrupt_n,
CFGINTERRUPTRDYN => cfg_interrupt_rdy_n,
CFGLINKCONTOLRCB => cfg_link_control_rcb,
CFGLINKCONTROLASPMCONTROL => cfg_link_control_aspm_control,
CFGLINKCONTROLCOMMONCLOCK => cfg_link_control_common_clock,
CFGLINKCONTROLEXTENDEDSYNC => cfg_link_control_extended_sync,
CFGLTSSMSTATE => cfg_ltssm_state,
CFGPCIELINKSTATEN => cfg_pcie_link_state_n,
CFGPMWAKEN => cfg_pm_wake_n,
CFGRDENN => cfg_rd_en_n,
CFGRDWRDONEN => cfg_rd_wr_done_n,
CFGREVID => w_cfg_rev_id,
CFGSUBSYSID => w_cfg_subsys_id,
CFGSUBSYSVENID => w_cfg_subsys_ven_id,
CFGTOTURNOFFN => cfg_to_turnoff_n,
CFGTRNPENDINGN => cfg_trn_pending_n,
CFGTURNOFFOKN => cfg_turnoff_ok_n,
CFGVENID => w_cfg_ven_id,
CLOCKLOCKED => clock_locked,
DBGBADDLLPSTATUS => dbg_bad_dllp_status,
DBGBADTLPLCRC => dbg_bad_tlp_lcrc,
DBGBADTLPSEQNUM => dbg_bad_tlp_seq_num,
DBGBADTLPSTATUS => dbg_bad_tlp_status,
DBGDLPROTOCOLSTATUS => dbg_dl_protocol_status,
DBGFCPROTOCOLERRSTATUS => dbg_fc_protocol_err_status,
DBGMLFRMDLENGTH => dbg_mlfrmd_length,
DBGMLFRMDMPS => dbg_mlfrmd_mps,
DBGMLFRMDTCVC => dbg_mlfrmd_tcvc,
DBGMLFRMDTLPSTATUS => dbg_mlfrmd_tlp_status,
DBGMLFRMDUNRECTYPE => dbg_mlfrmd_unrec_type,
DBGPOISTLPSTATUS => dbg_poistlpstatus,
DBGRCVROVERFLOWSTATUS => dbg_rcvr_overflow_status,
DBGREGDETECTEDCORRECTABLE => dbg_reg_detected_correctable,
DBGREGDETECTEDFATAL => dbg_reg_detected_fatal,
DBGREGDETECTEDNONFATAL => dbg_reg_detected_non_fatal,
DBGREGDETECTEDUNSUPPORTED => dbg_reg_detected_unsupported,
DBGRPLYROLLOVERSTATUS => dbg_rply_rollover_status,
DBGRPLYTIMEOUTSTATUS => dbg_rply_timeout_status,
DBGURNOBARHIT => dbg_ur_no_bar_hit,
DBGURPOISCFGWR => dbg_ur_pois_cfg_wr,
DBGURSTATUS => dbg_ur_status,
DBGURUNSUPMSG => dbg_ur_unsup_msg,
MGTCLK => mgt_clk,
MIMRXRADDR => mim_rx_raddr,
MIMRXRDATA => mim_rx_rdata,
MIMRXREN => mim_rx_ren,
MIMRXWADDR => mim_rx_waddr,
MIMRXWDATA => mim_rx_wdata,
MIMRXWEN => mim_rx_wen,
MIMTXRADDR => mim_tx_raddr,
MIMTXRDATA => mim_tx_rdata,
MIMTXREN => mim_tx_ren,
MIMTXWADDR => mim_tx_waddr,
MIMTXWDATA => mim_tx_wdata,
MIMTXWEN => mim_tx_wen,
PIPEGTPOWERDOWNA => pipe_gt_power_down_a,
PIPEGTPOWERDOWNB => pipe_gt_power_down_b,
PIPEGTRESETDONEA => pipe_gt_reset_done_a,
PIPEGTRESETDONEB => pipe_gt_reset_done_b,
PIPEGTTXELECIDLEA => pipe_gt_tx_elec_idle_a,
PIPEGTTXELECIDLEB => pipe_gt_tx_elec_idle_b,
PIPEPHYSTATUSA => pipe_phy_status_a,
PIPEPHYSTATUSB => pipe_phy_status_b,
PIPERXCHARISKA => pipe_rx_charisk_a,
PIPERXCHARISKB => pipe_rx_charisk_b,
PIPERXDATAA => pipe_rx_data_a,
PIPERXDATAB => pipe_rx_data_b,
PIPERXENTERELECIDLEA => pipe_rx_enter_elec_idle_a,
PIPERXENTERELECIDLEB => pipe_rx_enter_elec_idle_b,
PIPERXPOLARITYA => pipe_rx_polarity_a,
PIPERXPOLARITYB => pipe_rx_polarity_b,
PIPERXRESETA => pipe_rxreset_a,
PIPERXRESETB => pipe_rxreset_b,
PIPERXSTATUSA => pipe_rx_status_a,
PIPERXSTATUSB => pipe_rx_status_b,
PIPETXCHARDISPMODEA => pipe_tx_char_disp_mode_a,
PIPETXCHARDISPMODEB => pipe_tx_char_disp_mode_b,
PIPETXCHARDISPVALA => pipe_tx_char_disp_val_a,
PIPETXCHARDISPVALB => pipe_tx_char_disp_val_b,
PIPETXCHARISKA => pipe_tx_char_is_k_a,
PIPETXCHARISKB => pipe_tx_char_is_k_b,
PIPETXDATAA => pipe_tx_data_a,
PIPETXDATAB => pipe_tx_data_b,
PIPETXRCVRDETA => pipe_tx_rcvr_det_a,
PIPETXRCVRDETB => pipe_tx_rcvr_det_b,
RECEIVEDHOTRESET => received_hot_reset,
SYSRESETN => sys_reset_n,
TRNFCCPLD => trn_fc_cpld,
TRNFCCPLH => trn_fc_cplh,
TRNFCNPD => trn_fc_npd,
TRNFCNPH => trn_fc_nph,
TRNFCPD => trn_fc_pd,
TRNFCPH => trn_fc_ph,
TRNFCSEL => trn_fc_sel,
TRNLNKUPN => trn_lnk_up_n,
TRNRBARHITN => trn_rbar_hit_n,
TRNRD => trn_rd,
TRNRDSTRDYN => trn_rdst_rdy_n,
TRNREOFN => trn_reof_n,
TRNRERRFWDN => trn_rerrfwd_n,
TRNRNPOKN => trn_rnp_ok_n,
TRNRSOFN => trn_rsof_n,
TRNRSRCDSCN => trn_rsrc_dsc_n,
TRNRSRCRDYN => trn_rsrc_rdy_n,
TRNTBUFAV => trn_tbuf_av,
TRNTCFGGNTN => trn_tcfg_gnt_n,
TRNTCFGREQN => trn_tcfg_req_n,
TRNTD => trn_td,
TRNTDSTRDYN => trn_tdst_rdy_n,
TRNTEOFN => trn_teof_n,
TRNTERRDROPN => trn_terr_drop_n,
TRNTERRFWDN => trn_terrfwd_n,
TRNTSOFN => trn_tsof_n,
TRNTSRCDSCN => trn_tsrc_dsc_n,
TRNTSRCRDYN => trn_tsrc_rdy_n,
TRNTSTRN => trn_tstr_n,
USERCLK => trn_clk_c,
USERRSTN => trn_reset_n_c
);
----------------------------------------------------
-- Recreate wrapper outputs from the PCIE_A1 signals
----------------------------------------------------
cfg_status <= x"0000";
cfg_command <= "00000" &
cfg_command_interrupt_disable &
"0" &
cfg_command_serr_en &
"00000" &
cfg_command_bus_master_enable &
cfg_command_mem_enable &
cfg_command_io_enable;
cfg_dstatus <= "0000000000" &
not cfg_trn_pending_n &
'0' &
cfg_dev_status_ur_detected &
cfg_dev_status_fatal_err_detected &
cfg_dev_status_nonfatal_err_detected &
cfg_dev_status_corr_err_detected;
cfg_dcommand <= '0' &
cfg_dev_control_max_read_req &
cfg_dev_control_no_snoop_en &
cfg_dev_control_aux_power_en &
cfg_dev_control_phantom_en &
cfg_dev_control_ext_tag_en &
cfg_dev_control_max_payload &
cfg_dev_control_enable_ro &
cfg_dev_control_ur_err_reporting_en &
cfg_dev_control_fatal_err_reporting_en &
cfg_dev_control_non_fatal_reporting_en &
cfg_dev_control_corr_err_reporting_en;
cfg_lstatus <= x"0011";
cfg_lcommand <= x"00" &
cfg_link_control_extended_sync &
cfg_link_control_common_clock &
"00" &
cfg_link_control_rcb &
'0' &
cfg_link_control_aspm_control;
end rtl;
| gpl-3.0 | 97f0cf0d69f3c66ff81633ab647dd18e | 0.495071 | 3.68336 | false | false | false | false |
adelapie/noekeon_loop | tb_noekeon_loop.vhd | 1 | 4,253 |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_noekeon_loop IS
END tb_noekeon_loop;
ARCHITECTURE behavior OF tb_noekeon_loop IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT noekeon_loop
PORT(
clk : IN std_logic;
rst : IN std_logic;
enc : IN std_logic;
a_0_in : IN std_logic_vector(31 downto 0);
a_1_in : IN std_logic_vector(31 downto 0);
a_2_in : IN std_logic_vector(31 downto 0);
a_3_in : IN std_logic_vector(31 downto 0);
k_0_in : IN std_logic_vector(31 downto 0);
k_1_in : IN std_logic_vector(31 downto 0);
k_2_in : IN std_logic_vector(31 downto 0);
k_3_in : IN std_logic_vector(31 downto 0);
a_0_out : OUT std_logic_vector(31 downto 0);
a_1_out : OUT std_logic_vector(31 downto 0);
a_2_out : OUT std_logic_vector(31 downto 0);
a_3_out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal enc : std_logic := '0';
signal a_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_3_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_3_in : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal a_0_out : std_logic_vector(31 downto 0);
signal a_1_out : std_logic_vector(31 downto 0);
signal a_2_out : std_logic_vector(31 downto 0);
signal a_3_out : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: noekeon_loop PORT MAP (
clk => clk,
rst => rst,
enc => enc,
a_0_in => a_0_in,
a_1_in => a_1_in,
a_2_in => a_2_in,
a_3_in => a_3_in,
k_0_in => k_0_in,
k_1_in => k_1_in,
k_2_in => k_2_in,
k_3_in => k_3_in,
a_0_out => a_0_out,
a_1_out => a_1_out,
a_2_out => a_2_out,
a_3_out => a_3_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + clk_period;
rst <= '1';
enc <= '0';
a_0_in <= X"2a78421b";
a_1_in <= X"87c7d092";
a_2_in <= X"4f26113f";
a_3_in <= X"1d1349b2";
k_0_in <= X"b1656851";
k_1_in <= X"699e29fa";
k_2_in <= X"24b70148";
k_3_in <= X"503d2dfc";
wait for clk_period;
rst <= '0';
wait for clk_period*7 + clk_period/2;
assert a_0_out = X"e2f687e0"
report "ENCRYPT ERROR (a_0)" severity FAILURE;
assert a_1_out = X"7b75660f"
report "ENCRYPT ERROR (a_1)" severity FAILURE;
assert a_2_out = X"fc372233"
report "ENCRYPT ERROR (a_2)" severity FAILURE;
assert a_3_out = X"bc47532c"
report "ENCRYPT ERROR (a_3)" severity FAILURE;
wait;
end process;
END;
| gpl-3.0 | 2d9a1cd9a61c21793215cf414a9ce458 | 0.564072 | 3.061915 | false | false | false | false |
masaruohashi/tic-tac-toe | uart/unidade_controle_recepcao.vhd | 1 | 1,987 | -- VHDL da Unidade de Controle
library ieee;
use ieee.std_logic_1164.all;
entity unidade_controle_recepcao is
port(clock : in std_logic;
prepara : in std_logic;
fim : in std_logic;
reseta : in std_logic;
pronto : out std_logic;
saida : out std_logic_vector(5 downto 0)); -- limpa|carrega|zera|desloca|conta|pronto
end unidade_controle_recepcao;
architecture exemplo of unidade_controle_recepcao is
type tipo_estado is (inicial, preparacao, recebimento, final);
signal estado : tipo_estado;
begin
process (clock, estado, reseta)
begin
if reseta = '1' then
estado <= inicial;
elsif (clock'event and clock = '1') then
case estado is
when inicial => -- Aguarda de borda do sinal de clock
if prepara = '1' then
estado <= inicial;
else
estado <= preparacao;
end if;
when preparacao => -- Zera contador e latch
estado <= recebimento;
when recebimento => -- Desloca os bits no registrador lendo o dado serial
if fim = '1' then
estado <= final;
else
estado <= recebimento;
end if;
when final => -- Fim da recepção serial
estado <= inicial;
end case;
end if;
end process;
with estado select
pronto <= '1' when final,
'0' when others;
process (estado)
begin
case estado is -- limpa|carrega|zera|desloca|conta|pronto
when inicial =>
saida <= "010001";
when preparacao =>
saida <= "001000";
when recebimento =>
saida <= "000110";
when final =>
saida <= "000001";
end case;
end process;
end exemplo;
| mit | ac8c4ee7c6eac529572ecee31f75a864 | 0.508816 | 4.501134 | false | false | false | false |
JavierRizzoA/Sacagawea | sources/test_clock_counter_cntrl.vhd | 1 | 2,392 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:18:48 06/05/2016
-- Design Name:
-- Module Name: C:/Users/AlvaroMoreno/Desktop/proooc/sacagawea_copy/test_clock_counter_cntrl.vhd
-- Project Name: Sacagawea
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Cntrl_cont
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY test_clock_counter_cntrl IS
END test_clock_counter_cntrl;
ARCHITECTURE behavior OF test_clock_counter_cntrl IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Cntrl_cont
PORT(
clk : IN std_logic;
reset : IN std_logic;
sal_cont : OUT std_logic_vector(2 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal sal_cont : std_logic_vector(2 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Cntrl_cont PORT MAP (
clk => clk,
reset => reset,
sal_cont => sal_cont
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
clk <= '0';
wait for 100 ns;
clk <= '1';
wait for 100 ns;
clk <= '0';
wait for 100 ns;
clk <= '1';
wait for 100 ns;
clk <= '0';
wait for 100 ns;
clk <= '1';
wait for 100 ns;
clk <= '0';
wait for 100 ns;
clk <= '1';
wait for 100 ns;
wait;
end process;
END;
| mit | d79763a9ec684403921dbf22314a2620 | 0.549331 | 3.772871 | false | true | false | false |
srohrer32/beamformer | hdl/toplevel_nearfield.vhd | 1 | 4,727 | ----------------------------------------------------------------------------------
-- Created by Sam Rohrer --
-- Beamforms in the nearfield based on a generic for distance --
-- This is the toplevel file (to configure the FPGA) --
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity toplevel_nearfield is
generic(
sample_divisor : integer := 11
);
port(
sys_clock : in std_logic; -- system clk signal
swt_distance : in std_logic_vector (4 downto 0); -- switch 0 to 4
but_reset : in std_logic ; --Button D
pin_dataout : out std_logic_vector (7 downto 0); -- JA 0 to 7
pin_channel : out std_logic_vector (4 downto 0); -- JB 0 to 4
pin_datain_r : in std_logic_vector (7 downto 0); -- JC 0 to 7
pin_datain_l : in std_logic_vector (7 downto 0); -- JD 0 to 7
pin_int : in std_logic; -- JB5
pin_speaker_enable : out std_logic; --JB7
pin_rd : out std_logic --JB6
);
end toplevel_nearfield;
architecture Behavioral of toplevel_nearfield is
--******************* Signal Processing ***************--
component nearfield_processing is
generic(
divisor : integer := 50; -- difference between system clock 1 us
speed_sound : integer := 13397; -- in inches/second
speaker_distance : integer := 2; -- in inches
sample_period : integer := 22
);
port(
i_datain_r : in std_logic_vector (7 downto 0); -- 8 bit from memory
i_datain_l : in std_logic_vector (7 downto 0); -- 8 bit from memory
i_clock : in std_logic; --
i_distance : in std_logic_vector (4 downto 0); -- Switches determine distance
i_reset : in std_logic ; -- To reset the entire system
i_sampleclock : in std_logic ; -- Rate at which the music is playing
o_speaker_enable : out std_logic; --LDAC enable
o_dataout : out std_logic_vector (7 downto 0); -- 8 bit to be multiplexed
o_channel : out std_logic_vector (4 downto 0); -- 5 bit to select which DAC to enable
o_us_clock : out std_logic
);
end component;
--**************** User Signals ***************--
signal clockpulses : integer range 0 to 2200;
signal us_clockpulses : integer range 0 to 12;
signal sample_clock : std_logic;
signal us_clock : std_logic;
signal sig_datain_r : std_logic_vector (7 downto 0);
signal sig_datain_l : std_logic_vector (7 downto 0);
--**************** End User Signals ***********--
begin
--*************** User Processes **************--
sampleclock_division : process(but_reset, us_clock)
begin
if (but_reset = '1') then
us_clockpulses <= 0;
sample_clock <= '0';
elsif(rising_edge(us_clock)) then
us_clockpulses <= us_clockpulses + 1 ;
if(us_clockpulses = (sample_divisor-1)) then
sample_clock <= Not sample_clock;
us_clockpulses <= 0;
end if;
end if;
end process;
rd_control : process (but_reset, sys_clock, clockpulses, sample_clock)
begin
if (but_reset = '1' ) then
pin_rd <= '1';
clockpulses <= 0;
elsif (rising_edge(sys_clock)) then
clockpulses <= clockpulses + 1;
if (clockpulses = 0) then
pin_rd <= '0';
elsif (clockpulses = 250) then
pin_rd <= '1';
elsif(pin_int = '0') then
sig_datain_r <= pin_datain_r;
sig_datain_l <= pin_datain_l;
elsif(rising_edge(sample_clock)) then
clockpulses <= 0;
end if;
end if;
end process;
--*************** End User Processes **********--
--**************** Signal Processing Port Map ***********--
fpga : nearfield_processing
generic map(
divisor => 50,
speed_sound => 13397,
speaker_distance => 2,
sample_period => 22
)
port map(
i_datain_r => sig_datain_r,
i_datain_l => sig_datain_l,
i_clock => sys_clock,
i_distance => swt_distance,
i_reset => but_reset,
i_sampleclock => sample_clock,
o_speaker_enable => pin_speaker_enable,
o_dataout => pin_dataout,
o_channel => pin_channel,
o_us_clock => us_clock
);
end Behavioral; | apache-2.0 | 76f9a52e6969a64e72094c725a78a9b3 | 0.49799 | 3.611154 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/pcie_core/simulation/dsport/pcie_reset_delay_v6.vhd | 1 | 5,661 | -------------------------------------------------------------------------------
--
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : pcie_reset_delay_v6.vhd
-- Description: sys_reset_n delay (20ms) for Virtex6 PCIe Block
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity pcie_reset_delay_v6 is
generic (
PL_FAST_TRAIN : boolean := FALSE;
REF_CLK_FREQ : integer := 0 -- 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz
);
port (
ref_clk : in std_logic;
sys_reset_n : in std_logic;
delayed_sys_reset_n : out std_logic
);
end pcie_reset_delay_v6;
architecture v6_pcie of pcie_reset_delay_v6 is
constant TCQ : integer := 1;
function t_bit(
constant PL_FAST_TRAIN : boolean;
constant REF_CLK_FREQ : integer)
return integer is
variable tbit_out : integer := 2;
begin -- t_bit
if (PL_FAST_TRAIN) then
tbit_out := 2;
else
if (REF_CLK_FREQ = 0) then
tbit_out := 20;
elsif (REF_CLK_FREQ = 1) then
tbit_out := 20;
else
tbit_out := 21;
end if;
end if;
return tbit_out;
end t_bit;
constant TBIT : integer := t_bit(PL_FAST_TRAIN, REF_CLK_FREQ);
signal reg_count_7_0 : std_logic_vector(7 downto 0);
signal reg_count_15_8 : std_logic_vector(7 downto 0);
signal reg_count_23_16 : std_logic_vector(7 downto 0);
signal concat_count : std_logic_vector(23 downto 0);
-- X-HDL generated signals
signal v6pcie1 : std_logic_vector(7 downto 0);
signal v6pcie2 : std_logic_vector(7 downto 0);
-- Declare intermediate signals for referenced outputs
signal delayed_sys_reset_n_v6pcie0 : std_logic;
begin
-- Drive referenced outputs
delayed_sys_reset_n <= delayed_sys_reset_n_v6pcie0;
concat_count <= (reg_count_23_16 & reg_count_15_8 & reg_count_7_0);
v6pcie1 <= reg_count_15_8 + "00000001" when (reg_count_7_0 = "11111111") else
reg_count_15_8;
v6pcie2 <= reg_count_23_16 + "00000001" when ((reg_count_15_8 = "11111111") and (reg_count_7_0 = "11111111")) else
reg_count_23_16;
process (ref_clk, sys_reset_n)
begin
if ((not(sys_reset_n)) = '1') then
reg_count_7_0 <= "00000000" after (TCQ)*1 ps;
reg_count_15_8 <= "00000000" after (TCQ)*1 ps;
reg_count_23_16 <= "00000000" after (TCQ)*1 ps;
elsif (ref_clk'event and ref_clk = '1') then
if (delayed_sys_reset_n_v6pcie0 /= '1') then
reg_count_7_0 <= reg_count_7_0 + "00000001" after (TCQ)*1 ps;
reg_count_15_8 <= v6pcie1 after (TCQ)*1 ps;
reg_count_23_16 <= v6pcie2 after (TCQ)*1 ps;
end if;
end if;
end process;
delayed_sys_reset_n_v6pcie0 <= concat_count(TBIT);
end v6_pcie;
| gpl-3.0 | d052b156268a4124621ede180df0cc66 | 0.587882 | 3.912232 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/pcie_core/example_design/PIO_32_TX_ENGINE.vhd | 1 | 14,117 | -------------------------------------------------------------------------------
--
-- (c) Copyright 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : PIO_32_TX_ENGINE.vhd
-- Description: 32 bit LocalLink Transmit Unit.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity PIO_32_TX_ENGINE is
port (
clk : in std_logic;
rst_n : in std_logic;
trn_td : out std_logic_vector(31 downto 0);
trn_tsof_n : out std_logic;
trn_teof_n : out std_logic;
trn_tsrc_rdy_n : out std_logic;
trn_tsrc_dsc_n : out std_logic;
trn_tdst_rdy_n : in std_logic;
trn_tdst_dsc_n : in std_logic;
req_compl_i : in std_logic;
req_compl_with_data_i : in std_logic;
compl_done_o : out std_logic;
req_tc_i : in std_logic_vector(2 downto 0);
req_td_i : in std_logic;
req_ep_i : in std_logic;
req_attr_i : in std_logic_vector(1 downto 0);
req_len_i : in std_logic_vector(9 downto 0);
req_rid_i : in std_logic_vector(15 downto 0);
req_tag_i : in std_logic_vector(7 downto 0);
req_be_i : in std_logic_vector(7 downto 0);
req_addr_i : in std_logic_vector(12 downto 0);
rd_addr_o : out std_logic_vector(10 downto 0);
rd_be_o : out std_logic_vector(3 downto 0);
rd_data_i : in std_logic_vector(31 downto 0);
completer_id_i : in std_logic_vector(15 downto 0);
cfg_bus_mstr_enable_i : in std_logic
);
end pio_32_tx_engine;
architecture rtl of pio_32_tx_engine is
-- Clock-to-out delay
constant TCQ : time := 1 ns;
-- TLP Header format/type values
constant PIO_32_CPLD_FMT_TYPE : std_logic_vector(6 downto 0) := "1001010";
constant PIO_32_CPL_FMT_TYPE : std_logic_vector(6 downto 0) := "0001010";
-- States
type state_type is (
PIO_32_TX_RST_STATE,
PIO_32_TX_CPL_CPLD_DW1,
PIO_32_TX_CPL_CPLD_DW2,
PIO_32_TX_CPLD_DW3,
PIO_32_TX_WAIT_STATE
);
signal state : state_type;
-- Local signals
signal byte_count : std_logic_vector(11 downto 0);
signal lower_addr : std_logic_vector(6 downto 0);
signal cpl_w_data : std_logic;
signal req_compl_q : std_logic;
signal req_compl_with_data_q : std_logic;
signal rd_be_o_int : std_logic_vector(3 downto 0);
begin
rd_be_o <= rd_be_o_int;
--
-- Present address and byte enable to memory module
--
rd_addr_o <= req_addr_i(12 downto 2);
rd_be_o_int <= req_be_i(3 downto 0);
--
-- Calculate byte count based on byte enable
--
process(rd_be_o_int) begin
case rd_be_o_int(3 downto 0) is
when "1001" => byte_count <= X"004";
when "1011" => byte_count <= X"004";
when "1101" => byte_count <= X"004";
when "1111" => byte_count <= X"004";
when "0101" => byte_count <= X"003";
when "0111" => byte_count <= X"003";
when "1010" => byte_count <= X"003";
when "1110" => byte_count <= X"003";
when "0011" => byte_count <= X"002";
when "0110" => byte_count <= X"002";
when "1100" => byte_count <= X"002";
when "0001" => byte_count <= X"001";
when "0010" => byte_count <= X"001";
when "0100" => byte_count <= X"001";
when "1000" => byte_count <= X"001";
when others => byte_count <= X"001"; -- "0000"
end case;
end process;
--
-- Calculate lower address based on byte enable
--
process(rd_be_o_int, req_addr_i) begin
case (rd_be_o_int(3 downto 0)) is
when "0000" => lower_addr <= req_addr_i(6 downto 2) & "00";
when "0001" => lower_addr <= req_addr_i(6 downto 2) & "00";
when "0011" => lower_addr <= req_addr_i(6 downto 2) & "00";
when "0101" => lower_addr <= req_addr_i(6 downto 2) & "00";
when "0111" => lower_addr <= req_addr_i(6 downto 2) & "00";
when "1001" => lower_addr <= req_addr_i(6 downto 2) & "00";
when "1011" => lower_addr <= req_addr_i(6 downto 2) & "00";
when "1101" => lower_addr <= req_addr_i(6 downto 2) & "00";
when "1111" => lower_addr <= req_addr_i(6 downto 2) & "00";
when "0010" => lower_addr <= req_addr_i(6 downto 2) & "01";
when "0110" => lower_addr <= req_addr_i(6 downto 2) & "01";
when "1010" => lower_addr <= req_addr_i(6 downto 2) & "01";
when "1110" => lower_addr <= req_addr_i(6 downto 2) & "01";
when "0100" => lower_addr <= req_addr_i(6 downto 2) & "10";
when "1100" => lower_addr <= req_addr_i(6 downto 2) & "10";
when others => lower_addr <= req_addr_i(6 downto 2) & "11"; -- "1000"
end case;
end process;
process begin
wait until rising_edge(clk);
if (rst_n = '0') then
req_compl_q <= '0' after TCQ;
req_compl_with_data_q <= '1' after TCQ;
else
req_compl_q <= req_compl_i after TCQ;
req_compl_with_data_q <= req_compl_with_data_i after TCQ;
end if;
end process;
--
-- Generate Completion with 1 DW Payload or Completion with
-- no data
--
process begin
wait until rising_edge(clk);
if (rst_n = '0') then
trn_tsof_n <= '1' after TCQ;
trn_teof_n <= '1' after TCQ;
trn_tsrc_rdy_n <= '1' after TCQ;
trn_tsrc_dsc_n <= '1' after TCQ;
trn_td <= (others => '0') after TCQ; -- 32-bits
compl_done_o <= '0' after TCQ;
state <= PIO_32_TX_RST_STATE after TCQ;
else
compl_done_o <= '0' after TCQ;
case (state) is
when PIO_32_TX_RST_STATE =>
trn_tsrc_dsc_n <= '1' after TCQ;
if ((req_compl_q = '1') and (req_compl_with_data_q = '1') and (trn_tdst_dsc_n = '1')) then
-- Begin a CplD TLP
trn_tsof_n <= '0' after TCQ;
trn_teof_n <= '1' after TCQ;
trn_tsrc_rdy_n <= '0' after TCQ;
trn_td <= '0' &
PIO_32_CPLD_FMT_TYPE &
'0' &
req_tc_i &
"0000" &
req_td_i &
req_ep_i &
req_attr_i &
"00" &
req_len_i after TCQ;
cpl_w_data <= req_compl_with_data_q after TCQ;
state <= PIO_32_TX_CPL_CPLD_DW1 after TCQ;
elsif ((req_compl_q = '1') and (req_compl_with_data_q = '0') and (trn_tdst_dsc_n = '1')) then
-- Begin a Cpl TLP
trn_tsof_n <= '0' after TCQ;
trn_teof_n <= '1' after TCQ;
trn_tsrc_rdy_n <= '0' after TCQ;
trn_td <= '0' &
PIO_32_CPL_FMT_TYPE &
'0' &
req_tc_i &
"0000" &
req_td_i &
req_ep_i &
req_attr_i &
"00" &
req_len_i after TCQ;
cpl_w_data <= req_compl_with_data_q after TCQ;
state <= PIO_32_TX_CPL_CPLD_DW1 after TCQ;
else
trn_tsof_n <= '1' after TCQ;
trn_teof_n <= '1' after TCQ;
trn_tsrc_rdy_n <= '1' after TCQ;
trn_td <= (others => '0') after TCQ; -- 32-bit
state <= PIO_32_TX_RST_STATE after TCQ;
end if;
-- end of PIO_32_TX_RST_STATE
when PIO_32_TX_CPL_CPLD_DW1 =>
if (trn_tdst_dsc_n = '0') then
-- Core is aborting
trn_tsrc_dsc_n <= '0' after TCQ;
state <= PIO_32_TX_RST_STATE after TCQ;
elsif (trn_tdst_rdy_n = '0') then
-- Output next DW of TLP
trn_tsof_n <= '1' after TCQ;
trn_teof_n <= '1' after TCQ;
trn_tsrc_rdy_n <= '0' after TCQ;
trn_td <= completer_id_i &
"000" &
'0' &
byte_count after TCQ;
state <= PIO_32_TX_CPL_CPLD_DW2 after TCQ;
else
-- Wait for core to accept previous DW
state <= PIO_32_TX_CPL_CPLD_DW1 after TCQ;
end if;
-- end of PIO_32_TX_CPL_CPLD_DW1
when PIO_32_TX_CPL_CPLD_DW2 =>
if (trn_tdst_dsc_n = '0') then
-- Core is aborting
trn_tsrc_dsc_n <= '0' after TCQ;
state <= PIO_32_TX_RST_STATE after TCQ;
elsif (trn_tdst_rdy_n = '0') then
-- Output next DW of TLP
trn_tsof_n <= '1' after TCQ;
trn_tsrc_rdy_n <= '0' after TCQ;
trn_td <= req_rid_i &
req_tag_i &
'0' &
lower_addr after TCQ;
if (cpl_w_data = '1') then
-- For a CplD, there is one more DW
trn_teof_n <= '1' after TCQ;
state <= PIO_32_TX_CPLD_DW3 after TCQ;
else
-- For a Cpl, this is the final DW
trn_teof_n <= '0' after TCQ;
state <= PIO_32_TX_WAIT_STATE after TCQ;
end if;
else
-- Wait for core to accept previous DW
state <= PIO_32_TX_CPL_CPLD_DW2 after TCQ;
end if;
-- end of PIO_32_TX_CPL_CPLD_DW2
when PIO_32_TX_CPLD_DW3 =>
if (trn_tdst_dsc_n = '0') then
-- Core is aborting
trn_tsrc_dsc_n <= '1' after TCQ;
state <= PIO_32_TX_RST_STATE after TCQ;
elsif (trn_tdst_rdy_n = '0') then
-- Output next DW of TLP
trn_tsof_n <= '1' after TCQ;
trn_teof_n <= '0' after TCQ;
trn_tsrc_rdy_n <= '0' after TCQ;
trn_td <= rd_data_i after TCQ;
compl_done_o <= '1' after TCQ;
state <= PIO_32_TX_WAIT_STATE after TCQ;
else
-- Wait for core to accept previous DW
state <= PIO_32_TX_CPLD_DW3 after TCQ;
end if;
when PIO_32_TX_WAIT_STATE =>
if (trn_tdst_dsc_n = '0') then
-- Core is aborting
trn_tsrc_dsc_n <= '1' after TCQ;
state <= PIO_32_TX_RST_STATE after TCQ;
elsif (trn_tdst_rdy_n = '0') then
-- Core has accepted final DW of TLP
trn_tsrc_rdy_n <= '1' after TCQ;
compl_done_o <= '1' after TCQ;
state <= PIO_32_TX_RST_STATE after TCQ;
else
-- Wait for core to accept previous DW
state <= PIO_32_TX_WAIT_STATE after TCQ;
end if;
-- end of PIO_32_TX_WAIT_STATE
when others =>
state <= PIO_32_TX_RST_STATE after TCQ;
end case;
end if;
end process;
end rtl;
| gpl-3.0 | ce7789d06c080e7f92c40f20bcbd5b9d | 0.490047 | 3.583905 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/pcie_core/example_design/pcie_app_s6.vhd | 1 | 10,009 | -------------------------------------------------------------------------------
--
-- (c) Copyright 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : pcie_app_s6.vhd
-- Description: PCI Express Endpoint sample application design.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity pcie_app_s6 is
port (
trn_clk : in std_logic;
trn_reset_n : in std_logic;
trn_lnk_up_n : in std_logic;
-- Tx
trn_tbuf_av : in std_logic_vector(5 downto 0);
trn_tcfg_req_n : in std_logic;
trn_terr_drop_n : in std_logic;
trn_tdst_rdy_n : in std_logic;
trn_td : out std_logic_vector(31 downto 0);
trn_tsof_n : out std_logic;
trn_teof_n : out std_logic;
trn_tsrc_rdy_n : out std_logic;
trn_tsrc_dsc_n : out std_logic;
trn_terrfwd_n : out std_logic;
trn_tcfg_gnt_n : out std_logic;
trn_tstr_n : out std_logic;
-- Rx
trn_rd : in std_logic_vector(31 downto 0);
trn_rsof_n : in std_logic;
trn_reof_n : in std_logic;
trn_rsrc_rdy_n : in std_logic;
trn_rsrc_dsc_n : in std_logic;
trn_rerrfwd_n : in std_logic;
trn_rbar_hit_n : in std_logic_vector(6 downto 0);
trn_rdst_rdy_n : out std_logic;
trn_rnp_ok_n : out std_logic;
-- Flow Control
trn_fc_cpld : in std_logic_vector(11 downto 0);
trn_fc_cplh : in std_logic_vector(7 downto 0);
trn_fc_npd : in std_logic_vector(11 downto 0);
trn_fc_nph : in std_logic_vector(7 downto 0);
trn_fc_pd : in std_logic_vector(11 downto 0);
trn_fc_ph : in std_logic_vector(7 downto 0);
trn_fc_sel : out std_logic_vector(2 downto 0);
cfg_do : in std_logic_vector(31 downto 0);
cfg_rd_wr_done_n : in std_logic;
cfg_dwaddr : out std_logic_vector(9 downto 0);
cfg_rd_en_n : out std_logic;
cfg_err_cor_n : out std_logic;
cfg_err_ur_n : out std_logic;
cfg_err_ecrc_n : out std_logic;
cfg_err_cpl_timeout_n : out std_logic;
cfg_err_cpl_abort_n : out std_logic;
cfg_err_posted_n : out std_logic;
cfg_err_locked_n : out std_logic;
cfg_err_tlp_cpl_header : out std_logic_vector(47 downto 0);
cfg_err_cpl_rdy_n : in std_logic;
cfg_interrupt_n : out std_logic;
cfg_interrupt_rdy_n : in std_logic;
cfg_interrupt_assert_n : out std_logic;
cfg_interrupt_di : out std_logic_vector(7 downto 0);
cfg_interrupt_do : in std_logic_vector(7 downto 0);
cfg_interrupt_mmenable : in std_logic_vector(2 downto 0);
cfg_interrupt_msienable : in std_logic;
cfg_turnoff_ok_n : out std_logic;
cfg_to_turnoff_n : in std_logic;
cfg_trn_pending_n : out std_logic;
cfg_pm_wake_n : out std_logic;
cfg_bus_number : in std_logic_vector(7 downto 0);
cfg_device_number : in std_logic_vector(4 downto 0);
cfg_function_number : in std_logic_vector(2 downto 0);
cfg_status : in std_logic_vector(15 downto 0);
cfg_command : in std_logic_vector(15 downto 0);
cfg_dstatus : in std_logic_vector(15 downto 0);
cfg_dcommand : in std_logic_vector(15 downto 0);
cfg_lstatus : in std_logic_vector(15 downto 0);
cfg_lcommand : in std_logic_vector(15 downto 0);
cfg_pcie_link_state_n : in std_logic_vector(2 downto 0);
cfg_dsn : out std_logic_vector(63 downto 0)
);
end pcie_app_s6;
architecture rtl of pcie_app_s6 is
component PIO is
port (
trn_clk : in std_logic;
trn_reset_n : in std_logic;
trn_lnk_up_n : in std_logic;
trn_td : out std_logic_vector(31 downto 0);
trn_tsof_n : out std_logic;
trn_teof_n : out std_logic;
trn_tsrc_rdy_n : out std_logic;
trn_tsrc_dsc_n : out std_logic;
trn_tdst_rdy_n : in std_logic;
trn_tdst_dsc_n : in std_logic;
trn_rd : in std_logic_vector(31 downto 0);
trn_rsof_n : in std_logic;
trn_reof_n : in std_logic;
trn_rsrc_rdy_n : in std_logic;
trn_rsrc_dsc_n : in std_logic;
trn_rbar_hit_n : in std_logic_vector(6 downto 0);
trn_rdst_rdy_n : out std_logic;
cfg_to_turnoff_n : in std_logic;
cfg_turnoff_ok_n : out std_logic;
cfg_completer_id : in std_logic_vector(15 downto 0);
cfg_bus_mstr_enable : in std_logic
);
end component PIO;
constant PCI_EXP_EP_OUI : std_logic_vector(23 downto 0) := x"000A35";
constant PCI_EXP_EP_DSN_1 : std_logic_vector(31 downto 0) := x"01" & PCI_EXP_EP_OUI;
constant PCI_EXP_EP_DSN_2 : std_logic_vector(31 downto 0) := x"00000001";
signal cfg_completer_id : std_logic_vector(15 downto 0);
signal cfg_bus_mstr_enable : std_logic;
begin
--
-- Core input tie-offs
--
trn_fc_sel <= "000";
trn_rnp_ok_n <= '0';
trn_terrfwd_n <= '1';
trn_tcfg_gnt_n <= '0';
cfg_err_cor_n <= '1';
cfg_err_ur_n <= '1';
cfg_err_ecrc_n <= '1';
cfg_err_cpl_timeout_n <= '1';
cfg_err_cpl_abort_n <= '1';
cfg_err_posted_n <= '0';
cfg_err_locked_n <= '1';
cfg_pm_wake_n <= '1';
cfg_trn_pending_n <= '1';
trn_tstr_n <= '0';
cfg_interrupt_assert_n <= '1';
cfg_interrupt_n <= '1';
cfg_interrupt_di <= x"00";
cfg_err_tlp_cpl_header <= (OTHERS => '0');
cfg_dwaddr <= (OTHERS => '0');
cfg_rd_en_n <= '1';
cfg_dsn <= PCI_EXP_EP_DSN_2 & PCI_EXP_EP_DSN_1;
--
-- Programmed I/O Module
--
cfg_completer_id <= cfg_bus_number & cfg_device_number & cfg_function_number;
cfg_bus_mstr_enable <= cfg_command(2);
PIO_i : PIO
port map (
trn_clk => trn_clk, -- I
trn_reset_n => trn_reset_n, -- I
trn_lnk_up_n => trn_lnk_up_n, -- I
trn_td => trn_td, -- O [31:0]
trn_tsof_n => trn_tsof_n, -- O
trn_teof_n => trn_teof_n, -- O
trn_tsrc_rdy_n => trn_tsrc_rdy_n, -- O
trn_tsrc_dsc_n => trn_tsrc_dsc_n, -- O
trn_tdst_rdy_n => trn_tdst_rdy_n, -- I
trn_tdst_dsc_n => '1', -- I
trn_rd => trn_rd, -- I [31:0]
trn_rsof_n => trn_rsof_n, -- I
trn_reof_n => trn_reof_n, -- I
trn_rsrc_rdy_n => trn_rsrc_rdy_n, -- I
trn_rsrc_dsc_n => trn_rsrc_dsc_n, -- I
trn_rdst_rdy_n => trn_rdst_rdy_n, -- O
trn_rbar_hit_n => trn_rbar_hit_n, -- I [6:0]
cfg_to_turnoff_n => cfg_to_turnoff_n, -- I
cfg_turnoff_ok_n => cfg_turnoff_ok_n, -- O
cfg_completer_id => cfg_completer_id, -- I [15:0]
cfg_bus_mstr_enable => cfg_bus_mstr_enable -- I
);
end rtl;
| gpl-3.0 | a00b4bd3cc4c8795bafd424cf78348b6 | 0.539614 | 3.276268 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/pcie_core/simulation/dsport/pcie_bram_v6.vhd | 1 | 16,296 | -------------------------------------------------------------------------------
--
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : pcie_bram_v6.vhd
-- Description: BlockRAM module for Virtex6 PCIe Block
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity pcie_bram_v6 is
generic (
DOB_REG : integer := 0; -- 1 use the output register 0 don't use the output register
WIDTH : integer := 0 -- supported WIDTH's are: 4, 9, 18, 36 (uses RAMB36) and 72 (uses RAMB36SDP)
);
port (
user_clk_i : in std_logic; -- user clock
reset_i : in std_logic; -- bram reset
wen_i : in std_logic; -- write enable
waddr_i : in std_logic_vector(12 downto 0); -- write address
wdata_i : in std_logic_vector(WIDTH - 1 downto 0); -- write data
ren_i : in std_logic; -- read enable
rce_i : in std_logic; -- output register clock enable
raddr_i : in std_logic_vector(12 downto 0); -- read address
rdata_o : out std_logic_vector(WIDTH - 1 downto 0) -- read data
);
end pcie_bram_v6;
architecture v6_pcie of pcie_bram_v6 is
-- map the address bits
function msb_addr (
constant wdt : integer)
return integer is
variable addr_msb : integer := 8;
begin -- msb_addr
if (wdt = 4) then
addr_msb := 12;
elsif (wdt = 9) then
addr_msb := 11;
elsif (wdt = 18) then
addr_msb := 10;
elsif (wdt = 36) then
addr_msb := 9;
else
addr_msb := 8;
end if;
return addr_msb;
end msb_addr;
constant ADDR_MSB : integer := msb_addr(WIDTH);
-- set the width of the tied off low address bits
function alb (
constant wdt : integer)
return integer is
variable addr_lo_bit : integer := 8;
begin -- alb
if (wdt = 4) then
addr_lo_bit := 2;
elsif (wdt = 9) then
addr_lo_bit := 3;
elsif (wdt = 18) then
addr_lo_bit := 4;
elsif (wdt = 36) then
addr_lo_bit := 5;
else
addr_lo_bit := 0; -- for WIDTH 72 use RAMB36SDP
end if;
return addr_lo_bit;
end alb;
constant ADDR_LO_BITS : integer := alb(WIDTH);
-- map the data bits
function msb_d (
constant wdt : integer)
return integer is
variable dmsb : integer := 8;
begin -- msb_d
if (wdt = 4) then
dmsb := 3;
elsif (wdt = 9) then
dmsb := 7;
elsif (wdt = 18) then
dmsb := 15;
elsif (wdt = 36) then
dmsb := 31;
else
dmsb := 63;
end if;
return dmsb;
end msb_d;
constant D_MSB : integer := msb_d(WIDTH);
-- map the data parity bits
constant DP_LSB : integer := D_MSB + 1;
function msb_dp (
constant wdt : integer)
return integer is
variable dpmsb : integer := 8;
begin -- msb_dp
if (wdt = 4) then
dpmsb := 4;
elsif (wdt = 9) then
dpmsb := 8;
elsif (wdt = 18) then
dpmsb := 17;
elsif (wdt = 36) then
dpmsb := 35;
else
dpmsb := 71;
end if;
return dpmsb;
end msb_dp;
function pad_val (
in_vec : std_logic_vector;
range_hi : integer;
range_lo : integer;
pad : std_logic;
op_len : integer)
return std_logic_vector is
variable ret : std_logic_vector(op_len-1 downto 0) := (others => '0');
begin -- pad_val
for i in 0 to op_len-1 loop
if ((i >= range_lo) and (i <= range_hi)) then
ret(i) := in_vec(i - range_lo);
else
ret(i) := pad;
end if;
end loop; -- i
return ret;
end pad_val;
constant DP_MSB : integer := msb_dp(WIDTH);
constant DPW : integer := DP_MSB - DP_LSB + 1;
constant WRITE_MODE : string := "NO_CHANGE";
-- ground and tied_to_vcc_i signals
signal tied_to_ground_i : std_logic;
signal tied_to_ground_vec_i : std_logic_vector(31 downto 0);
signal tied_to_vcc_i : std_logic;
-- X-HDL generated signals
signal v6pcie2 : std_logic_vector(7 downto 0) := (others => '0');
signal v6pcie5 : std_logic_vector(15 downto 0) := (others => '0');
signal v6pcie7 : std_logic_vector(15 downto 0) := (others => '0');
signal v6pcie11 : std_logic_vector(31 downto 0) := (others => '0');
signal v6pcie12 : std_logic_vector(3 downto 0) := (others => '0');
signal v6pcie15 : std_logic_vector(63 downto 0) := (others => '0');
signal v6pcie16 : std_logic_vector(7 downto 0) := (others => '0');
signal v6pcie13 : std_logic_vector((DP_MSB - DP_LSB) downto 0) := (others => '0');
-- dob_unused and dopb_unused only needed when WIDTH < 36. how to declare
-- these accordingly.
signal dob_unused : std_logic_vector(31 - D_MSB - 1 downto 0);
signal dopb_unused : std_logic_vector(4 - DPW - 1 downto 0);
-- Declare intermediate signals for referenced outputs
signal rdata_o_v6pcie0 : std_logic_vector(WIDTH - 1 downto 0);
begin
--------------------------- Static signal Assignments ---------------------
tied_to_ground_i <= '0';
tied_to_ground_vec_i(31 downto 0) <= (others => '0');
tied_to_vcc_i <= '1';
-- Drive referenced outputs
rdata_o <= rdata_o_v6pcie0;
--synthesis translate_off
process
begin
--$display("[%t] %m DOB_REG %0d WIDTH %0d ADDR_MSB %0d ADDR_LO_BITS %0d DP_MSB %0d DP_LSB %0d D_MSB %0d",
-- $time, DOB_REG, WIDTH, ADDR_MSB, ADDR_LO_BITS, DP_MSB, DP_LSB, D_MSB);
case WIDTH is
when 4 | 9 | 18 | 36 | 72 =>
when others => -- case (WIDTH)
-- $display("[%t] %m Error WIDTH %0d not supported", now, to_stdlogic(WIDTH));
-- $finish();
end case;
wait;
end process;
--synthesis translate_on
use_ramb36sdp : if (WIDTH = 72) generate
v6pcie2 <= (others => wen_i);
rdata_o_v6pcie0 <= v6pcie16((DP_MSB - DP_LSB) downto 0) & v6pcie15(D_MSB downto 0);
-- use RAMB36SDP if the width is 72
ramb36sdp_i : RAMB36SDP
generic map (
DO_REG => DOB_REG
)
port map (
DBITERR => open,
ECCPARITY => open,
SBITERR => open,
WRCLK => user_clk_i,
SSR => '0',
WRADDR => waddr_i(ADDR_MSB downto 0),
DI => wdata_i(D_MSB downto 0),
DIP => wdata_i(DP_MSB downto DP_LSB),
WREN => wen_i,
WE => v6pcie2,
RDCLK => user_clk_i,
RDADDR => raddr_i(ADDR_MSB downto 0),
DO => v6pcie15,
DOP => v6pcie16,
RDEN => ren_i,
REGCE => rce_i
);
-- use RAMB36's if the width is 4, 9, 18, or 36
end generate;
use_ramb36_1 : if (WIDTH = 36) generate
v6pcie2 <= (others => wen_i);
v6pcie5 <= pad_val(waddr_i(ADDR_MSB downto 0), ADDR_MSB + ADDR_LO_BITS, ADDR_LO_BITS, '1', 16);
v6pcie7 <= pad_val(raddr_i(ADDR_MSB downto 0), ADDR_MSB + ADDR_LO_BITS, ADDR_LO_BITS, '1', 16);
rdata_o_v6pcie0 <= v6pcie16((DP_MSB - DP_LSB) downto 0) & v6pcie15(D_MSB downto 0);
ramb36_i : RAMB36
generic map (
DOA_REG => 0,
DOB_REG => DOB_REG,
READ_WIDTH_A => 0,
READ_WIDTH_B => WIDTH,
WRITE_WIDTH_A => WIDTH,
WRITE_WIDTH_B => 0,
WRITE_MODE_A => WRITE_MODE
)
port map (
CLKA => user_clk_i,
SSRA => '0',
REGCEA => '0',
CASCADEINLATA => '0',
CASCADEINREGA => '0',
CASCADEOUTLATA => open,
CASCADEOUTREGA => open,
DOA => open,
DOPA => open,
ADDRA => v6pcie5,
DIA => wdata_i(D_MSB downto 0),
DIPA => wdata_i(DP_MSB downto DP_LSB),
ENA => wen_i,
WEA => v6pcie2(3 downto 0),
CLKB => user_clk_i,
SSRB => '0',
WEB => "0000",
CASCADEINLATB => '0',
CASCADEINREGB => '0',
CASCADEOUTLATB => open,
CASCADEOUTREGB => open,
DIB => "00000000000000000000000000000000",
DIPB => "0000",
ADDRB => v6pcie7,
DOB => v6pcie15(31 downto 0),
DOPB => v6pcie16(3 downto 0),
ENB => ren_i,
REGCEB => rce_i
);
end generate;
use_ramb36_2 : if (WIDTH < 36 and WIDTH > 4) generate
v6pcie2 <= (others => wen_i);
v6pcie5 <= pad_val(waddr_i(ADDR_MSB downto 0), ADDR_MSB + ADDR_LO_BITS, ADDR_LO_BITS, '1', 16);
v6pcie7 <= pad_val(raddr_i(ADDR_MSB downto 0), ADDR_MSB + ADDR_LO_BITS, ADDR_LO_BITS, '1', 16);
v6pcie11 <= pad_val(wdata_i(D_MSB downto 0), D_MSB, 0, '0', 32);
v6pcie13 <= wdata_i(DP_MSB downto DP_LSB);
v6pcie12 <= pad_val(v6pcie13((DP_MSB - DP_LSB) downto 0), DP_MSB - DP_LSB, 0, '0', 4);
rdata_o_v6pcie0 <= v6pcie16((DP_MSB - DP_LSB) downto 0) & v6pcie15(D_MSB downto 0);
ramb36_i : RAMB36
generic map (
DOA_REG => 0,
DOB_REG => DOB_REG,
READ_WIDTH_A => 0,
READ_WIDTH_B => WIDTH,
WRITE_WIDTH_A => WIDTH,
WRITE_WIDTH_B => 0,
WRITE_MODE_A => WRITE_MODE
)
port map (
CLKA => user_clk_i,
SSRA => '0',
REGCEA => '0',
CASCADEINLATA => '0',
CASCADEINREGA => '0',
CASCADEOUTLATA => open,
CASCADEOUTREGA => open,
DOA => open,
DOPA => open,
ADDRA => v6pcie5,
DIA => v6pcie11,
DIPA => v6pcie12,
ENA => wen_i,
WEA => v6pcie2(3 downto 0),
CLKB => user_clk_i,
SSRB => '0',
WEB => "0000",
CASCADEINLATB => '0',
CASCADEINREGB => '0',
CASCADEOUTLATB => open,
CASCADEOUTREGB => open,
DIB => "00000000000000000000000000000000",
DIPB => "0000",
ADDRB => v6pcie7,
DOB => v6pcie15(31 downto 0),
DOPB => v6pcie16(3 downto 0),
ENB => ren_i,
REGCEB => rce_i
);
end generate;
use_ramb36_3 : if (WIDTH = 4) generate
v6pcie2 <= (others => wen_i);
v6pcie5 <= pad_val(waddr_i(ADDR_MSB downto 0), ADDR_MSB + ADDR_LO_BITS, ADDR_LO_BITS, '1', 16);
v6pcie7 <= pad_val(raddr_i(ADDR_MSB downto 0), ADDR_MSB + ADDR_LO_BITS, ADDR_LO_BITS, '1', 16);
v6pcie11 <= pad_val(wdata_i(D_MSB downto 0), D_MSB, 0, '0', 32);
rdata_o_v6pcie0 <= v6pcie15(D_MSB downto 0);
ramb36_i : RAMB36
generic map (
dob_reg => DOB_REG,
read_width_a => 0,
read_width_b => WIDTH,
write_width_a => WIDTH,
write_width_b => 0,
write_mode_a => WRITE_MODE
)
port map (
CLKA => user_clk_i,
SSRA => '0',
REGCEA => '0',
CASCADEINLATA => '0',
CASCADEINREGA => '0',
CASCADEOUTLATA => open,
CASCADEOUTREGA => open,
DOA => open,
DOPA => open,
ADDRA => v6pcie5,
DIA => v6pcie11,
DIPA => tied_to_ground_vec_i(3 downto 0),
ENA => wen_i,
WEA => v6pcie2(3 downto 0),
CLKB => user_clk_i,
SSRB => '0',
WEB => "0000",
CASCADEINLATB => '0',
CASCADEINREGB => '0',
CASCADEOUTLATB => open,
CASCADEOUTREGB => open,
ADDRB => v6pcie7,
DIB => tied_to_ground_vec_i,
DIPB => tied_to_ground_vec_i(3 downto 0),
DOB => v6pcie15(31 downto 0),
DOPB => open,
ENB => ren_i,
REGCEB => rce_i
);
-- block: use_ramb36
end generate;
-- pcie_bram_v6
end v6_pcie;
| gpl-3.0 | 4f64e10a65a9dfd0f999b60224ef9816 | 0.474043 | 3.940992 | false | false | false | false |
JavierRizzoA/Sacagawea | sources/RegistrosArriba_tb.vhd | 1 | 3,894 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:55:21 06/05/2016
-- Design Name:
-- Module Name: /home/tony/Sacagawea/sources/RegistrosArriba_tb.vhd
-- Project Name: Sacagawea
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: RegistrosArriba
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY RegistrosArriba_tb IS
END RegistrosArriba_tb;
ARCHITECTURE behavior OF RegistrosArriba_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT RegistrosArriba
PORT(
s_alu : IN std_logic_vector(7 downto 0);
clk : IN std_logic;
mbr_ld : IN std_logic;
ir_ld : IN std_logic;
ip_ld : IN std_logic;
temp_ld : IN std_logic;
ban_ld : IN std_logic;
ar_ld : IN std_logic;
mbr_sel : IN std_logic;
ar_sel : IN std_logic;
sum_sel : IN std_logic;
ir_sel : IN std_logic;
ip_sel2 : IN std_logic_vector(1 downto 0);
ME : IN std_logic;
Z : IN std_logic;
MA : IN std_logic;
bus_datos : INOUT std_logic_vector(7 downto 0);
ar_s : OUT std_logic_vector(11 downto 0)
);
END COMPONENT;
--Inputs
signal s_alu : std_logic_vector(7 downto 0) := (others => '0');
signal clk : std_logic := '0';
signal mbr_ld : std_logic := '0';
signal ir_ld : std_logic := '0';
signal ip_ld : std_logic := '0';
signal temp_ld : std_logic := '0';
signal ban_ld : std_logic := '0';
signal ar_ld : std_logic := '0';
signal mbr_sel : std_logic := '0';
signal ar_sel : std_logic := '0';
signal sum_sel : std_logic := '0';
signal ir_sel : std_logic := '0';
signal ip_sel2 : std_logic_vector(1 downto 0) := (others => '0');
signal ME : std_logic := '0';
signal Z : std_logic := '0';
signal MA : std_logic := '0';
--BiDirs
signal bus_datos : std_logic_vector(7 downto 0);
--Outputs
signal ar_s : std_logic_vector(11 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: RegistrosArriba PORT MAP (
s_alu => s_alu,
clk => clk,
mbr_ld => mbr_ld,
ir_ld => ir_ld,
ip_ld => ip_ld,
temp_ld => temp_ld,
ban_ld => ban_ld,
ar_ld => ar_ld,
mbr_sel => mbr_sel,
ar_sel => ar_sel,
sum_sel => sum_sel,
ir_sel => ir_sel,
ip_sel2 => ip_sel2,
ME => ME,
Z => Z,
MA => MA,
bus_datos => bus_datos,
ar_s => ar_s
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
bus_datos <= "10010011";
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
bus_datos <= "10010011";
ip_ld <= '1';
wait for 50ns;
ir_ld <= '1';
end process;
END;
| mit | 156d78ccf7303ba5baa560c8e89cb0f3 | 0.548023 | 3.418788 | false | false | false | false |
Nixon-/VHDL_library | basic/nbit_decoder.vhd | 1 | 660 | Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity nbit_decoder is
generic(
numInputs: integer:=3
);
port(
inputs: in std_logic_vector(numInputs-1 downto 0);
output: out std_logic_vector(numInputs**2 -1 downto 0)
enable: in std_logic;
);
end entity;
architecture primary of nbit_decoder is
signal bitToSet: integer;
signal tempOutput: std_logic_vector(numInputs**2 -1 downto 0);
begin
process(bitToSet,tempOutput,inputs,output,enable) begin
if(enable = '1') then
bitToSet <= to_integer(unsigned(inputs));
tempOutput(bitToSet) <= '1';
output <= tempOutput;
else
output <= (others => '0');
end if;
end primary;
| gpl-2.0 | f444fbf4b060357b632bd1a74b5f8210 | 0.715152 | 2.920354 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/pcie_core/simulation/dsport/pcie_clocking_v6.vhd | 1 | 16,368 | -------------------------------------------------------------------------------
--
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : pcie_clocking_v6.vhd
-- Description: Clocking module for Virtex6 PCIe Block
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity pcie_clocking_v6 is
generic (
IS_ENDPOINT : boolean := TRUE;
CAP_LINK_WIDTH : integer := 8; -- 1 - x1 , 2 - x2 , 4 - x4 , 8 - x8
CAP_LINK_SPEED : integer := 1; -- 1 - Gen1 , 2 - Gen2
REF_CLK_FREQ : integer := 0; -- 0 - 100 MHz , 1 - 125 MHz , 2 - 250 MHz
USER_CLK_FREQ : integer := 3 -- 0 - 31.25 MHz , 1 - 62.5 MHz , 2 - 125 MHz , 3 - 250 MHz , 4 - 500Mhz
);
port (
sys_clk : in std_logic;
gt_pll_lock : in std_logic;
sel_lnk_rate : in std_logic;
sel_lnk_width : in std_logic_vector(1 downto 0);
sys_clk_bufg : out std_logic;
pipe_clk : out std_logic;
user_clk : out std_logic;
block_clk : out std_logic;
drp_clk : out std_logic;
clock_locked : out std_logic
);
end pcie_clocking_v6;
architecture v6_pcie of pcie_clocking_v6 is
-- MMCM Configuration
function clkin_prd(
constant REF_CLK_FREQ : integer)
return real is
variable CLKIN_PERD : real := 0.0;
begin -- clkin_prd
if (REF_CLK_FREQ = 0) then
CLKIN_PERD := 10.0;
elsif (REF_CLK_FREQ = 1) then
CLKIN_PERD := 8.0;
elsif (REF_CLK_FREQ = 2) then
CLKIN_PERD := 4.0;
else
CLKIN_PERD := 0.0;
end if;
return CLKIN_PERD;
end clkin_prd;
constant mmcm_clockin_period : real := clkin_prd(REF_CLK_FREQ);
function clkfb_mul(
constant REF_CLK_FREQ : integer)
return real is
variable CLKFB_MULT : real := 0.0;
begin -- clkfb_mul
if (REF_CLK_FREQ = 0) then
CLKFB_MULT := 10.0;
elsif (REF_CLK_FREQ = 1) then
CLKFB_MULT := 8.0;
elsif (REF_CLK_FREQ = 2) then
CLKFB_MULT := 8.0;
else
CLKFB_MULT := 0.0;
end if;
return CLKFB_MULT;
end clkfb_mul;
constant mmcm_clockfb_mult : real := clkfb_mul(REF_CLK_FREQ);
function divclk_div(
constant REF_CLK_FREQ : integer)
return integer is
variable DIVCLK_DIVIDE : integer := 0;
begin -- divclk_div
if (REF_CLK_FREQ = 0) then
DIVCLK_DIVIDE := 1;
elsif (REF_CLK_FREQ = 1) then
DIVCLK_DIVIDE := 1;
elsif (REF_CLK_FREQ = 2) then
DIVCLK_DIVIDE := 2;
else
DIVCLK_DIVIDE := 0;
end if;
return DIVCLK_DIVIDE;
end divclk_div;
constant mmcm_divclk_divide : integer := divclk_div(REF_CLK_FREQ);
constant mmcm_clock0_div : real := 4.0;
constant mmcm_clock1_div : integer := 8;
constant TCQ : integer := 1;
function clk2_div(
constant LNK_WDT : integer;
constant LNK_SPD : integer;
constant USR_CLK_FREQ : integer)
return integer is
variable CLK_DIV : integer := 1;
begin -- clk2_div
if ((LNK_WDT = 1) and (LNK_SPD = 1) and (USR_CLK_FREQ = 0)) then
CLK_DIV := 32;
elsif ((LNK_WDT = 1) and (LNK_SPD = 1) and (USR_CLK_FREQ = 1)) then
CLK_DIV := 16;
elsif ((LNK_WDT = 1) and (LNK_SPD = 2) and (USR_CLK_FREQ = 1)) then
CLK_DIV := 16;
elsif ((LNK_WDT = 2) and (LNK_SPD = 1) and (USR_CLK_FREQ = 1)) then
CLK_DIV := 16;
else
CLK_DIV := 2;
end if;
return CLK_DIV;
end clk2_div;
constant mmcm_clock2_div : integer := clk2_div(CAP_LINK_WIDTH, CAP_LINK_SPEED, USER_CLK_FREQ);
constant mmcm_clock3_div : integer := 2;
signal mmcm_locked : std_logic;
signal mmcm_clkfbin : std_logic;
signal mmcm_clkfbout : std_logic;
signal mmcm_reset : std_logic;
signal clk_500 : std_logic;
signal clk_250 : std_logic;
signal clk_125 : std_logic;
signal user_clk_prebuf : std_logic;
signal sel_lnk_rate_d : std_logic;
signal reg_clock_locked : std_logic_vector(1 downto 0) := "11";
-- Declare intermediate signals for referenced outputs
signal sys_clk_bufg_v6pcie3 : std_logic;
signal pipe_clk_v6pcie : std_logic;
signal user_clk_v6pcie4 : std_logic;
signal block_clk_v6pcie0 : std_logic;
signal drp_clk_v6pcie1 : std_logic;
signal clock_locked_int : std_logic;
begin
-- Drive referenced outputs
sys_clk_bufg <= sys_clk_bufg_v6pcie3;
pipe_clk <= pipe_clk_v6pcie;
user_clk <= user_clk_v6pcie4;
block_clk <= block_clk_v6pcie0;
drp_clk <= drp_clk_v6pcie1;
clock_locked <= clock_locked_int and mmcm_locked;
clock_locked_int <= not(reg_clock_locked(1));
-- MMCM Reset
mmcm_reset <= '0';
-- PIPE Clock BUFG.
GEN1_LINK : if (CAP_LINK_SPEED = 1) generate
pipe_clk_bufg : BUFG port map (O => pipe_clk_v6pcie, I => clk_125 );
end generate;
GEN2_LINK : if (CAP_LINK_SPEED = 2) generate
sel_lnk_rate_delay : SRL16E generic map ( INIT => X"0000" )
port map (
Q => sel_lnk_rate_d,
D => sel_lnk_rate,
CLK => pipe_clk_v6pcie,
CE => clock_locked_int,
A3 => '1',
A2 => '1',
A1 => '1',
A0 => '1'
);
pipe_clk_bufgmux : BUFGMUX port map (
O => pipe_clk_v6pcie,
I0 => clk_125,
I1 => clk_250,
S => sel_lnk_rate_d
);
end generate;
ILLEGAL_LINK_SPEED : if ((CAP_LINK_SPEED /= 1) and (CAP_LINK_SPEED /= 2)) generate
--$display("Confiuration Error : CAP_LINK_SPEED = %d, must be either 1 or 2.", CAP_LINK_SPEED);
--$finish;
end generate;
-- User Clock BUFG.
x1_GEN1_31_25 : if ((CAP_LINK_WIDTH = 1) and (CAP_LINK_SPEED = 1) and (USER_CLK_FREQ = 0)) generate
user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => user_clk_prebuf );
end generate;
x1_GEN1_62_50 : if ((CAP_LINK_WIDTH = 1) and (CAP_LINK_SPEED = 1) and (USER_CLK_FREQ = 1)) generate
user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => user_clk_prebuf );
end generate;
x1_GEN1_125_00 : if ((CAP_LINK_WIDTH = 1) and (CAP_LINK_SPEED = 1) and (USER_CLK_FREQ = 2)) generate
user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_125 );
end generate;
x1_GEN1_250_00 : if ((CAP_LINK_WIDTH = 1) and (CAP_LINK_SPEED = 1) and (USER_CLK_FREQ = 3)) generate
user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_250 );
end generate;
x1_GEN2_62_50 : if ((CAP_LINK_WIDTH = 1) and (CAP_LINK_SPEED = 2) and (USER_CLK_FREQ = 1)) generate
user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => user_clk_prebuf );
end generate;
x1_GEN2_125_00 : if ((CAP_LINK_WIDTH = 1) and (CAP_LINK_SPEED = 2) and (USER_CLK_FREQ = 2)) generate
user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_125 );
end generate;
x1_GEN2_250_00 : if ((CAP_LINK_WIDTH = 1) and (CAP_LINK_SPEED = 2) and (USER_CLK_FREQ = 3)) generate
user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_250 );
end generate;
x2_GEN1_62_50 : if ((CAP_LINK_WIDTH = 2) and (CAP_LINK_SPEED = 1) and (USER_CLK_FREQ = 1)) generate
user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => user_clk_prebuf );
end generate;
x2_GEN1_125_00 : if ((CAP_LINK_WIDTH = 2) and (CAP_LINK_SPEED = 1) and (USER_CLK_FREQ = 2)) generate
user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_125 );
end generate;
x2_GEN1_250_00 : if ((CAP_LINK_WIDTH = 2) and (CAP_LINK_SPEED = 1) and (USER_CLK_FREQ = 3)) generate
user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_250 );
end generate;
x2_GEN2_125_00 : if ((CAP_LINK_WIDTH = 2) and (CAP_LINK_SPEED = 2) and (USER_CLK_FREQ = 2)) generate
user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_125 );
end generate;
x2_GEN2_250_00 : if ((CAP_LINK_WIDTH = 2) and (CAP_LINK_SPEED = 2) and (USER_CLK_FREQ = 3)) generate
user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_250 );
end generate;
x4_GEN1_125_00 : if ((CAP_LINK_WIDTH = 4) and (CAP_LINK_SPEED = 1) and (USER_CLK_FREQ = 2)) generate
user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_125 );
end generate;
x4_GEN1_250_00 : if ((CAP_LINK_WIDTH = 4) and (CAP_LINK_SPEED = 1) and (USER_CLK_FREQ = 3)) generate
user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_250 );
end generate;
x4_GEN2_250_00 : if ((CAP_LINK_WIDTH = 4) and (CAP_LINK_SPEED = 2) and (USER_CLK_FREQ = 3)) generate
user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_250 );
end generate;
x8_GEN1_250_00 : if ((CAP_LINK_WIDTH = 8) and (CAP_LINK_SPEED = 1) and (USER_CLK_FREQ = 3)) generate
user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_250 );
end generate;
x8_GEN2_250_00 : if ((CAP_LINK_WIDTH = 8) and (CAP_LINK_SPEED = 2) and (USER_CLK_FREQ = 4)) generate
user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_250 );
block_clk_bufg : BUFG port map ( O => block_clk_v6pcie0, I => clk_500 );
end generate;
-- v6pcie42 : if (not((CAP_LINK_WIDTH = 8) and (CAP_LINK_SPEED = 2) and (USER_CLK_FREQ = 4))) generate
--$display("Confiuration Error : Unsupported Link Width, Link Speed and User Clock Frequency Combination");
--$finish;
-- end generate;
-- DRP clk
drp_clk_bufg_i : BUFG port map ( O => drp_clk_v6pcie1, I => clk_125 );
-- Feedback BUFG. Required for Temp Compensation
clkfbin_bufg_i : BUFG port map ( O => mmcm_clkfbin, I => mmcm_clkfbout );
-- sys_clk BUFG.
sys_clk_bufg_i : BUFG port map ( O => sys_clk_bufg_v6pcie3, I => sys_clk );
mmcm_adv_i : MMCM_ADV
generic map (
-- 5 for 100 MHz , 4 for 125 MHz , 2 for 250 MHz
CLKFBOUT_MULT_F => mmcm_clockfb_mult,
DIVCLK_DIVIDE => mmcm_divclk_divide,
CLKFBOUT_PHASE => 0.0,
-- 10 for 100 MHz, 4 for 250 MHz
CLKIN1_PERIOD => mmcm_clockin_period,
CLKIN2_PERIOD => mmcm_clockin_period,
-- 500 MHz / mmcm_clockx_div
CLKOUT0_DIVIDE_F => mmcm_clock0_div,
CLKOUT0_PHASE => 0.0,
CLKOUT1_DIVIDE => mmcm_clock1_div,
CLKOUT1_PHASE => 0.0,
CLKOUT2_DIVIDE => mmcm_clock2_div,
CLKOUT2_PHASE => 0.0,
CLKOUT3_DIVIDE => mmcm_clock3_div,
CLKOUT3_PHASE => 0.0
)
port map (
clkfbout => mmcm_clkfbout,
clkout0 => clk_250, -- 250 MHz for pipe_clk
clkout1 => clk_125, -- 125 MHz for pipe_clk
clkout2 => user_clk_prebuf, -- user clk
clkout3 => clk_500,
clkout4 => open,
clkout5 => open,
clkout6 => open,
do => open,
drdy => open,
clkfboutb => open,
clkfbstopped => open,
clkinstopped => open,
clkout0b => open,
clkout1b => open,
clkout2b => open,
clkout3b => open,
psdone => open,
locked => mmcm_locked,
clkfbin => mmcm_clkfbin,
clkin1 => sys_clk,
clkin2 => '0',
clkinsel => '1',
daddr => "0000000",
dclk => '0',
den => '0',
di => "0000000000000000",
dwe => '0',
psen => '0',
psincdec => '0',
pwrdwn => '0',
psclk => '0',
rst => mmcm_reset
);
-- Synchronize MMCM locked output
process (pipe_clk_v6pcie, gt_pll_lock)
begin
if ((not(gt_pll_lock)) = '1') then
reg_clock_locked <= "11" after (TCQ)*1 ps;
elsif (pipe_clk_v6pcie'event and pipe_clk_v6pcie = '1') then
reg_clock_locked <= (reg_clock_locked(0) & '0') after (TCQ)*1 ps;
end if;
end process;
end v6_pcie;
| gpl-3.0 | 1234cf2683efcf183887870b3d0428b9 | 0.512158 | 3.680684 | false | false | false | false |
Pinwino/dbg_ohwr | debugger_gw/fmc-delay/top/spec_top_std.vhd | 1 | 31,662 | -------------------------------------------------------------------------------
-- Title : Fine Delay FMC SPEC (Simple PCI-Express FMC Carrier) top level
-- for stand alone opeartion.
-- Project : FMC DEL 1ns 4cha-stand-alone application (fmc-delay-1ns-4cha-sa)
-------------------------------------------------------------------------------
-- File : spec_top_std.vhd
-- Author : Jose Jimenez <[email protected]>
-- Company : FREE INDEPENDENT ALLIANCE OF MAKERS (or looking for one)
-- Created : 2014-06-08
-- Last update: 2014-07-31
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top level for the SPEC 1.1 (and later releases) cards with
-- one Fine Delay FMC operating in stand alone mode
-- Supports:
-- - SDB enumeration (SDB descriptor at 0x00000)
-- - White Rabbit and Etherbone
-- - Interrupts (via WR VIC)
-- - WB Debbuger component provding stand alone operation
-------------------------------------------------------------------------------
-- Adapted from
---- Title : Fine Delay FMC SPEC (Simple PCI-Express FMC Carrier) top level
---- Project : Fine Delay FMC (fmc-delay-1ns-4cha)
---- File : spec_top.vhd
---- Author : Tomasz Wlostowski
---- Company : CERN
---- Created : 2011-08-24
---- Last update: 2013-07-25
---- Platform : FPGA-generic
---- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-06-08 1.0 jjimenez Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.gn4124_core_pkg.all;
use work.gencores_pkg.all;
use work.wrcore_pkg.all;
use work.wr_fabric_pkg.all;
use work.wishbone_pkg.all;
use work.fine_delay_pkg.all;
use work.etherbone_pkg.all;
use work.wr_xilinx_pkg.all;
use work.genram_pkg.all;
use work.debugger_pkg.all;
use work.synthesis_descriptor.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity spec_top_std is
generic
(
g_simulation : integer := 0
);
port
(
-------------------------------------------------------------------------
-- Standard SPEC ports (Gennum bridge, LEDS, Etc. Do not modify
-------------------------------------------------------------------------
clk_20m_vcxo_i : in std_logic; -- 20MHz VCXO clock
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
clk_125m_pllref_n_i : in std_logic;
clk_125m_gtp_n_i : in std_logic; -- 125 MHz GTP reference
clk_125m_gtp_p_i : in std_logic;
l_rst_n : in std_logic; -- reset from gn4124 (rstout18_n)
-- general purpose interface
gpio : inout std_logic_vector(1 downto 0); -- gpio[0] -> gn4124 gpio8
-- gpio[1] -> gn4124 gpio9
-- pcie to local [inbound data] - rx
p2l_rdy : out std_logic; -- rx buffer full flag
p2l_clkn : in std_logic; -- receiver source synchronous clock-
p2l_clkp : in std_logic; -- receiver source synchronous clock+
p2l_data : in std_logic_vector(15 downto 0); -- parallel receive data
p2l_dframe : in std_logic; -- receive frame
p2l_valid : in std_logic; -- receive data valid
-- inbound buffer request/status
p_wr_req : in std_logic_vector(1 downto 0); -- pcie write request
p_wr_rdy : out std_logic_vector(1 downto 0); -- pcie write ready
rx_error : out std_logic; -- receive error
-- local to parallel [outbound data] - tx
l2p_data : out std_logic_vector(15 downto 0); -- parallel transmit data
l2p_dframe : out std_logic; -- transmit data frame
l2p_valid : out std_logic; -- transmit data valid
l2p_clkn : out std_logic; -- transmitter source synchronous clock-
l2p_clkp : out std_logic; -- transmitter source synchronous clock+
l2p_edb : out std_logic; -- packet termination and discard
-- outbound buffer status
l2p_rdy : in std_logic; -- tx buffer full flag
l_wr_rdy : in std_logic_vector(1 downto 0); -- local-to-pcie write
p_rd_d_rdy : in std_logic_vector(1 downto 0); -- pcie-to-local read response data ready
tx_error : in std_logic; -- transmit error
vc_rdy : in std_logic_vector(1 downto 0); -- channel ready
-- font panel leds
led_red : out std_logic;
led_green : out std_logic;
-------------------------------------------------------------------------
-- PLL VCXO DAC Drive
-------------------------------------------------------------------------
dac_sclk_o : out std_logic;
dac_din_o : out std_logic;
--dac_clr_n_o : out std_logic;
dac_cs1_n_o : out std_logic;
dac_cs2_n_o : out std_logic;
button1_i : in std_logic := '1';
button2_i : in std_logic;
fmc_scl_b : inout std_logic := '1';
fmc_sda_b : inout std_logic := '1';
carrier_onewire_b : inout std_logic := '1';
fmc_prsnt_m2c_l_i : in std_logic;
-------------------------------------------------------------------------
-- SFP pins
-------------------------------------------------------------------------
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic := '0';
sfp_rxn_i : in std_logic := '1';
sfp_mod_def0_b : in std_logic; -- detect pin
sfp_mod_def1_b : inout std_logic; -- scl
sfp_mod_def2_b : inout std_logic; -- sda
sfp_rate_select_b : inout std_logic := '0';
sfp_tx_fault_i : in std_logic := '0';
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic := '0';
-------------------------------------------------------------------------
-- Fine Delay Pins
-------------------------------------------------------------------------
fd_tdc_start_p_i : in std_logic;
fd_tdc_start_n_i : in std_logic;
fd_clk_ref_p_i : in std_logic;
fd_clk_ref_n_i : in std_logic;
fd_trig_a_i : in std_logic;
fd_tdc_cal_pulse_o : out std_logic;
fd_tdc_d_b : inout std_logic_vector(27 downto 0);
fd_tdc_emptyf_i : in std_logic;
fd_tdc_alutrigger_o : out std_logic;
fd_tdc_wr_n_o : out std_logic;
fd_tdc_rd_n_o : out std_logic;
fd_tdc_oe_n_o : out std_logic;
fd_led_trig_o : out std_logic;
fd_tdc_start_dis_o : out std_logic;
fd_tdc_stop_dis_o : out std_logic;
fd_spi_cs_dac_n_o : out std_logic;
fd_spi_cs_pll_n_o : out std_logic;
fd_spi_cs_gpio_n_o : out std_logic;
fd_spi_sclk_o : out std_logic;
fd_spi_mosi_o : out std_logic;
fd_spi_miso_i : in std_logic;
fd_delay_len_o : out std_logic_vector(3 downto 0);
fd_delay_val_o : out std_logic_vector(9 downto 0);
fd_delay_pulse_o : out std_logic_vector(3 downto 0);
fd_dmtd_clk_o : out std_logic;
fd_dmtd_fb_in_i : in std_logic;
fd_dmtd_fb_out_i : in std_logic;
fd_pll_status_i : in std_logic;
fd_ext_rst_n_o : out std_logic;
fd_onewire_b : inout std_logic;
-----------------------------------------
-- UART
-----------------------------------------
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic
);
end spec_top_std;
architecture rtl of spec_top_std is
signal wrpc_uart_rxd_i: std_logic;
signal wrpc_uart_txd_o: std_logic;
component spec_serial_dac_arb
generic(
g_invert_sclk : boolean;
g_num_extra_bits : integer);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
val1_i : in std_logic_vector(15 downto 0);
load1_i : in std_logic;
val2_i : in std_logic_vector(15 downto 0);
load2_i : in std_logic;
dac_cs_n_o : out std_logic_vector(1 downto 0);
dac_clr_n_o : out std_logic;
dac_sclk_o : out std_logic;
dac_din_o : out std_logic);
end component;
component fd_ddr_pll
port (
RST : in std_logic;
LOCKED : out std_logic;
CLK_IN1_P : in std_logic;
CLK_IN1_N : in std_logic;
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic);
end component;
component spec_reset_gen
port (
clk_sys_i : in std_logic;
rst_pcie_n_a_i : in std_logic;
rst_button_n_a_i : in std_logic;
rst_n_o : out std_logic);
end component;
function f_resize_slv (x : std_logic_vector; len : integer) return std_logic_vector is
variable tmp : std_logic_vector(len-1 downto 0);
begin
if(len > x'length) then
tmp(x'length-1 downto 0) := x;
tmp(len-1 downto x'length) := (others => '0');
elsif(len < x'length) then
tmp := x(len-1 downto 0);
else
tmp := x;
end if;
return tmp;
end f_resize_slv;
function f_int2bool (x : integer) return boolean is
begin
if(x = 0) then
return false;
else
return true;
end if;
end f_int2bool;
constant c_NUM_WB_MASTERS : integer := 4;
constant c_NUM_WB_SLAVES : integer := 3;
constant c_MASTER_GENNUM : integer := 0;
constant c_MASTER_ETHERBONE : integer := 1;
constant c_MASTER_DEBUGGER : integer := 2;
constant c_SLAVE_FD : integer := 0;
constant c_SLAVE_WRCORE : integer := 1;
constant c_SLAVE_VIC : integer := 2;
constant c_SLAVE_DEBG : integer := 3;
constant c_DESC_SYNTHESIS : integer := 4;
constant c_DESC_REPO_URL : integer := 5;
constant c_WRCORE_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(c_NUM_WB_MASTERS+1 downto 0) :=
(c_SLAVE_WRCORE => f_sdb_embed_bridge(c_WRCORE_BRIDGE_SDB, x"000c0000"),
c_SLAVE_FD => f_sdb_embed_device(c_FD_SDB_DEVICE, x"00080000"),
c_SLAVE_VIC => f_sdb_embed_device(c_xwb_vic_sdb, x"00090000"),
c_SLAVE_DEBG => f_sdb_embed_device(c_xwb_dbg_slave_sdb, x"00040000"),
c_DESC_SYNTHESIS => f_sdb_embed_synthesis(c_sdb_synthesis_info),
c_DESC_REPO_URL => f_sdb_embed_repo_url(c_sdb_repo_url));
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
constant c_VIC_VECTOR_TABLE : t_wishbone_address_array(0 to 0) :=
(0 => x"00080000");
signal pllout_clk_sys : std_logic;
signal pllout_clk_dmtd : std_logic;
signal pllout_clk_fb_pllref : std_logic;
signal pllout_clk_fb_dmtd : std_logic;
signal clk_20m_vcxo_buf : std_logic;
signal clk_125m_pllref : std_logic;
signal clk_125m_gtp : std_logic;
signal clk_sys : std_logic;
signal clk_dmtd : std_logic;
signal dac_hpll_load_p1 : std_logic;
signal dac_dpll_load_p1 : std_logic;
signal dac_hpll_data : std_logic_vector(15 downto 0);
signal dac_dpll_data : std_logic_vector(15 downto 0);
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_k : std_logic;
signal phy_tx_disparity : std_logic;
signal phy_tx_enc_err : std_logic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_rx_rbclk : std_logic;
signal phy_rx_k : std_logic;
signal phy_rx_enc_err : std_logic;
signal phy_rx_bitslide : std_logic_vector(3 downto 0);
signal phy_rst : std_logic;
signal phy_loopen : std_logic;
signal local_reset_n : std_logic;
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_in : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
signal cnx_slave_in : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0);
signal dcm_clk_ref_0, dcm_clk_ref_180 : std_logic;
signal fd_tdc_start : std_logic;
signal tdc_data_out, tdc_data_in : std_logic_vector(27 downto 0);
signal tdc_data_oe : std_logic;
signal tm_link_up : std_logic;
signal tm_utc : std_logic_vector(39 downto 0);
signal tm_cycles : std_logic_vector(27 downto 0);
signal tm_time_valid : std_logic;
signal tm_clk_aux_lock_en : std_logic;
signal tm_clk_aux_locked : std_logic;
signal tm_dac_value : std_logic_vector(23 downto 0);
signal tm_dac_wr : std_logic;
signal ddr_pll_reset : std_logic;
signal ddr_pll_locked, fd_pll_status : std_logic;
signal wrc_scl_out, wrc_scl_in, wrc_sda_out, wrc_sda_in : std_logic;
signal fd_scl_out, fd_scl_in, fd_sda_out, fd_sda_in : std_logic;
signal sfp_scl_out, sfp_scl_in, sfp_sda_out, sfp_sda_in : std_logic;
signal wrc_owr_en, wrc_owr_in : std_logic_vector(1 downto 0);
signal fd_owr_en, fd_owr_in : std_logic;
signal fd_irq : std_logic;
signal gn_wb_adr : std_logic_vector(31 downto 0);
signal pps : std_logic;
signal etherbone_rst_n : std_logic;
signal etherbone_src_out : t_wrf_source_out;
signal etherbone_src_in : t_wrf_source_in;
signal etherbone_snk_out : t_wrf_sink_out;
signal etherbone_snk_in : t_wrf_sink_in;
signal etherbone_cfg_in : t_wishbone_slave_in;
signal etherbone_cfg_out : t_wishbone_slave_out;
signal vic_irqs : std_logic_vector(31 downto 0);
attribute buffer_type : string; --" {bufgdll | ibufg | bufgp | ibuf | bufr | none}";
attribute buffer_type of clk_125m_pllref : signal is "BUFG";
begin
U_Reset_Generator : spec_reset_gen
port map (
clk_sys_i => clk_sys,
rst_pcie_n_a_i => l_rst_n,
rst_button_n_a_i => button1_i,
rst_n_o => local_reset_n);
U_Buf_CLK_PLL : IBUFGDS
generic map (
DIFF_TERM => true,
IBUF_LOW_PWR => true -- Low power (TRUE) vs. performance (FALSE) setting for referenced
)
port map (
O => clk_125m_pllref, -- Buffer output
I => clk_125m_pllref_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => clk_125m_pllref_n_i -- Diff_n buffer input (connect directly to top-level port)
);
U_Buf_CLK_GTP : IBUFDS
generic map (
DIFF_TERM => true,
IBUF_LOW_PWR => false -- Low power (TRUE) vs. performance (FALSE) setting for referenced
)
port map (
O => clk_125m_gtp,
I => clk_125m_gtp_p_i,
IB => clk_125m_gtp_n_i
);
cmp_sys_clk_pll : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 8,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 16, -- 62.5 MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 16, -- 125 MHz
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 16,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 8.0,
REF_JITTER => 0.016)
port map (
CLKFBOUT => pllout_clk_fb_pllref,
CLKOUT0 => pllout_clk_sys,
CLKOUT1 => open,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => open,
RST => '0',
CLKFBIN => pllout_clk_fb_pllref,
CLKIN => clk_125m_pllref);
cmp_dmtd_clk_pll : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 50,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 16, -- 62.5 MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 16, -- 62.5 MHz
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 8,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 50.0,
REF_JITTER => 0.016)
port map (
CLKFBOUT => pllout_clk_fb_dmtd,
CLKOUT0 => pllout_clk_dmtd,
CLKOUT1 => open, --pllout_clk_sys,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => open,
RST => '0',
CLKFBIN => pllout_clk_fb_dmtd,
CLKIN => clk_20m_vcxo_buf);
cmp_clk_sys_buf : BUFG
port map (
O => clk_sys,
I => pllout_clk_sys);
cmp_clk_dmtd_buf : BUFG
port map (
O => clk_dmtd,
I => pllout_clk_dmtd);
cmp_clk_vcxo : BUFG
port map (
O => clk_20m_vcxo_buf,
I => clk_20m_vcxo_i);
-------------------------------------------------------------------------------
-- Gennum core
-------------------------------------------------------------------------------
cmp_gn4124_core : gn4124_core
port map
(
---------------------------------------------------------
-- Control and status
rst_n_a_i => L_RST_N,
status_o => open,
---------------------------------------------------------
-- P2L Direction
--
-- Source Sync DDR related signals
p2l_clk_p_i => P2L_CLKp,
p2l_clk_n_i => P2L_CLKn,
p2l_data_i => P2L_DATA,
p2l_dframe_i => P2L_DFRAME,
p2l_valid_i => P2L_VALID,
-- P2L Control
p2l_rdy_o => P2L_RDY,
p_wr_req_i => P_WR_REQ,
p_wr_rdy_o => P_WR_RDY,
rx_error_o => RX_ERROR,
vc_rdy_i => VC_RDY,
---------------------------------------------------------
-- L2P Direction
--
-- Source Sync DDR related signals
l2p_clk_p_o => L2P_CLKp,
l2p_clk_n_o => L2P_CLKn,
l2p_data_o => L2P_DATA,
l2p_dframe_o => L2P_DFRAME,
l2p_valid_o => L2P_VALID,
-- L2P Control
l2p_edb_o => L2P_EDB,
l2p_rdy_i => L2P_RDY,
l_wr_rdy_i => L_WR_RDY,
p_rd_d_rdy_i => P_RD_D_RDY,
tx_error_i => TX_ERROR,
---------------------------------------------------------
-- Interrupt interface
dma_irq_o => open,
irq_p_i => '0',
irq_p_o => open,
dma_reg_clk_i => clk_sys,
---------------------------------------------------------
-- CSR wishbone interface (master pipelined)
csr_clk_i => clk_sys,
csr_adr_o => gn_wb_adr,
csr_dat_o => cnx_slave_in(c_MASTER_GENNUM).dat,
csr_sel_o => cnx_slave_in(c_MASTER_GENNUM).sel,
csr_stb_o => cnx_slave_in(c_MASTER_GENNUM).stb,
csr_we_o => cnx_slave_in(c_MASTER_GENNUM).we,
csr_cyc_o => cnx_slave_in(c_MASTER_GENNUM).cyc,
csr_dat_i => cnx_slave_out(c_MASTER_GENNUM).dat,
csr_ack_i => cnx_slave_out(c_MASTER_GENNUM).ack,
csr_stall_i => cnx_slave_out(c_MASTER_GENNUM).stall,
dma_clk_i => clk_sys,
dma_ack_i => '1',
dma_stall_i => '0',
dma_dat_i => (others => '0'),
dma_reg_adr_i => (others => '0'),
dma_reg_dat_i => (others => '0'),
dma_reg_sel_i => (others => '0'),
dma_reg_stb_i => '0',
dma_reg_cyc_i => '0',
dma_reg_we_i => '0'
);
cnx_slave_in(c_MASTER_GENNUM).adr <= gn_wb_adr(29 downto 0) & "00";
-------------------------------------------------------------------------------
-- Top level interconnect and interrupt controller
-------------------------------------------------------------------------------
U_Intercon : xwb_sdb_crossbar
generic map (
g_num_masters => c_NUM_WB_SLAVES,
g_num_slaves => c_NUM_WB_MASTERS,
g_registered => true,
g_wraparound => true,
g_layout => c_INTERCONNECT_LAYOUT,
g_sdb_addr => c_SDB_ADDRESS)
port map (
clk_sys_i => clk_sys,
rst_n_i => local_reset_n,
slave_i => cnx_slave_in,
slave_o => cnx_slave_out,
master_i => cnx_master_in,
master_o => cnx_master_out);
U_VIC : xwb_vic
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_num_interrupts => 1,
g_init_vectors => c_VIC_VECTOR_TABLE)
port map (
clk_sys_i => clk_sys,
rst_n_i => local_reset_n,
slave_i => cnx_master_out(c_SLAVE_VIC),
slave_o => cnx_master_in(c_SLAVE_VIC),
irqs_i(0) => fd_irq,
irq_master_o => GPIO(0));
-------------------------------------------------------------------------------
-- White Rabbit Core + PHY
-------------------------------------------------------------------------------
-- Tristates for FMC EEPROM
fmc_scl_b <= '0' when (wrc_scl_out = '0' or fd_scl_out = '0') else 'Z';
fmc_sda_b <= '0' when (wrc_sda_out = '0' or fd_sda_out = '0') else 'Z';
wrc_scl_in <= fmc_scl_b;
wrc_sda_in <= fmc_sda_b;
fd_scl_in <= fmc_scl_b;
fd_sda_in <= fmc_sda_b;
-- Tristates for SFP EEPROM
sfp_mod_def1_b <= '0' when sfp_scl_out = '0' else 'Z';
sfp_mod_def2_b <= '0' when sfp_sda_out = '0' else 'Z';
sfp_scl_in <= sfp_mod_def1_b;
sfp_sda_in <= sfp_mod_def2_b;
carrier_onewire_b <= '0' when wrc_owr_en(0) = '1' else 'Z';
wrc_owr_in(0) <= carrier_onewire_b;
U_WR_CORE : xwr_core
generic map (
g_simulation => g_simulation,
g_phys_uart => true,
g_virtual_uart => true,
g_with_external_clock_input => false,
g_aux_clks => 1,
g_dpram_initf => "wrc-ethb.ram",
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_softpll_enable_debugger => false,
g_aux_sdb => c_etherbone_sdb)
port map (
clk_sys_i => clk_sys,
clk_dmtd_i => clk_dmtd,
clk_ref_i => clk_125m_pllref,
clk_aux_i(0) => dcm_clk_ref_0,
rst_n_i => local_reset_n,
dac_hpll_load_p1_o => dac_hpll_load_p1,
dac_hpll_data_o => dac_hpll_data,
dac_dpll_load_p1_o => dac_dpll_load_p1,
dac_dpll_data_o => dac_dpll_data,
phy_ref_clk_i => clk_125m_pllref,
phy_tx_data_o => phy_tx_data,
phy_tx_k_o => phy_tx_k,
phy_tx_disparity_i => phy_tx_disparity,
phy_tx_enc_err_i => phy_tx_enc_err,
phy_rx_data_i => phy_rx_data,
phy_rx_rbclk_i => phy_rx_rbclk,
phy_rx_k_i => phy_rx_k,
phy_rx_enc_err_i => phy_rx_enc_err,
phy_rx_bitslide_i => phy_rx_bitslide,
phy_rst_o => phy_rst,
phy_loopen_o => phy_loopen,
led_act_o => open,
led_link_o => LED_GREEN,
scl_o => wrc_scl_out,
scl_i => wrc_scl_in,
sda_o => wrc_sda_out,
sda_i => wrc_sda_in,
sfp_scl_o => sfp_scl_out,
sfp_scl_i => sfp_scl_in,
sfp_sda_o => sfp_sda_out,
sfp_sda_i => sfp_sda_in,
sfp_det_i => sfp_mod_def0_b,
uart_rxd_i => wrpc_uart_rxd_i,
uart_txd_o => wrpc_uart_txd_o,
owr_en_o => wrc_owr_en,
owr_i => wrc_owr_in,
slave_i => cnx_master_out(c_SLAVE_WRCORE),
slave_o => cnx_master_in(c_SLAVE_WRCORE),
aux_master_o => etherbone_cfg_in,
aux_master_i => etherbone_cfg_out,
wrf_src_o => etherbone_snk_in,
wrf_src_i => etherbone_snk_out,
wrf_snk_o => etherbone_src_in,
wrf_snk_i => etherbone_src_out,
tm_link_up_o => tm_link_up,
tm_dac_value_o => tm_dac_value,
tm_dac_wr_o(0) => tm_dac_wr,
tm_clk_aux_lock_en_i(0) => tm_clk_aux_lock_en,
tm_clk_aux_locked_o(0) => tm_clk_aux_locked,
tm_time_valid_o => tm_time_valid,
tm_tai_o => tm_utc,
tm_cycles_o => tm_cycles,
btn1_i => '0',
btn2_i => '0',
rst_aux_n_o => etherbone_rst_n,
pps_p_o => pps
);
U_GTP : wr_gtp_phy_spartan6
generic map (
g_simulation => g_simulation,
g_enable_ch0 => 0,
g_enable_ch1 => 1)
port map (
gtp_clk_i => clk_125m_gtp,
ch0_ref_clk_i => clk_125m_pllref,
ch0_tx_data_i => x"00",
ch0_tx_k_i => '0',
ch0_tx_disparity_o => open,
ch0_tx_enc_err_o => open,
ch0_rx_rbclk_o => open,
ch0_rx_data_o => open,
ch0_rx_k_o => open,
ch0_rx_enc_err_o => open,
ch0_rx_bitslide_o => open,
ch0_rst_i => '1',
ch0_loopen_i => '0',
ch1_ref_clk_i => clk_125m_pllref,
ch1_tx_data_i => phy_tx_data,
ch1_tx_k_i => phy_tx_k,
ch1_tx_disparity_o => phy_tx_disparity,
ch1_tx_enc_err_o => phy_tx_enc_err,
ch1_rx_data_o => phy_rx_data,
ch1_rx_rbclk_o => phy_rx_rbclk,
ch1_rx_k_o => phy_rx_k,
ch1_rx_enc_err_o => phy_rx_enc_err,
ch1_rx_bitslide_o => phy_rx_bitslide,
ch1_rst_i => phy_rst,
ch1_loopen_i => '0', --phy_loopen,
pad_txn0_o => open,
pad_txp0_o => open,
pad_rxn0_i => '0',
pad_rxp0_i => '0',
pad_txn1_o => sfp_txn_o,
pad_txp1_o => sfp_txp_o,
pad_rxn1_i => sfp_rxn_i,
pad_rxp1_i => sfp_rxp_i);
U_Etherbone : eb_slave_core
generic map (
g_sdb_address => f_resize_slv(c_sdb_address, 64))
port map (
clk_i => clk_sys,
nRst_i => etherbone_rst_n,
src_o => etherbone_src_out,
src_i => etherbone_src_in,
snk_o => etherbone_snk_out,
snk_i => etherbone_snk_in,
cfg_slave_o => etherbone_cfg_out,
cfg_slave_i => etherbone_cfg_in,
master_o => cnx_slave_in(c_MASTER_ETHERBONE),
master_i => cnx_slave_out(c_MASTER_ETHERBONE));
--cnx_slave_in(c_MASTER_ETHERBONE).cyc <= '0';
U_DAC_ARB : spec_serial_dac_arb
generic map (
g_invert_sclk => false,
g_num_extra_bits => 8)
port map (
clk_i => clk_sys,
rst_n_i => local_reset_n,
val1_i => dac_dpll_data,
load1_i => dac_dpll_load_p1,
val2_i => dac_hpll_data,
load2_i => dac_hpll_load_p1,
dac_cs_n_o(0) => dac_cs1_n_o,
dac_cs_n_o(1) => dac_cs2_n_o,
-- dac_clr_n_o => open,
dac_sclk_o => dac_sclk_o,
dac_din_o => dac_din_o);
-- dac_clr_n_o <= '1';
sfp_tx_disable_o <= '0';
-------------------------------------------------------------------------------
-- FINE DELAY INSTANTIATION
-------------------------------------------------------------------------------
cmp_fd_tdc_start : IBUFDS
generic map (
DIFF_TERM => true,
IBUF_LOW_PWR => false -- Low power (TRUE) vs. performance (FALSE) setting for referenced
)
port map (
O => fd_tdc_start, -- Buffer output
I => fd_tdc_start_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => fd_tdc_start_n_i -- Diff_n buffer input (connect directly to top-level port)
);
U_DDR_PLL : fd_ddr_pll
port map (
RST => ddr_pll_reset,
LOCKED => ddr_pll_locked,
CLK_IN1_P => fd_clk_ref_p_i,
CLK_IN1_N => fd_clk_ref_n_i,
CLK_OUT1 => dcm_clk_ref_0,
CLK_OUT2 => dcm_clk_ref_180);
ddr_pll_reset <= not fd_pll_status_i;
fd_pll_status <= fd_pll_status_i and ddr_pll_locked;
U_FineDelay_Core : fine_delay_core
generic map (
g_with_wr_core => true,
g_simulation => f_int2bool(g_simulation),
g_interface_mode => PIPELINED,
g_address_granularity => BYTE)
port map (
clk_ref_0_i => dcm_clk_ref_0,
clk_ref_180_i => dcm_clk_ref_180,
clk_sys_i => clk_sys,
clk_dmtd_i => clk_dmtd,
rst_n_i => local_reset_n,
dcm_reset_o => open,
dcm_locked_i => ddr_pll_locked,
trig_a_i => fd_trig_a_i,
tdc_cal_pulse_o => fd_tdc_cal_pulse_o,
tdc_start_i => fd_tdc_start,
dmtd_fb_in_i => fd_dmtd_fb_in_i,
dmtd_fb_out_i => fd_dmtd_fb_out_i,
dmtd_samp_o => fd_dmtd_clk_o,
led_trig_o => fd_led_trig_o,
ext_rst_n_o => fd_ext_rst_n_o,
pll_status_i => fd_pll_status,
acam_d_o => tdc_data_out,
acam_d_i => tdc_data_in,
acam_d_oen_o => tdc_data_oe,
acam_emptyf_i => fd_tdc_emptyf_i,
acam_alutrigger_o => fd_tdc_alutrigger_o,
acam_wr_n_o => fd_tdc_wr_n_o,
acam_rd_n_o => fd_tdc_rd_n_o,
acam_start_dis_o => fd_tdc_start_dis_o,
acam_stop_dis_o => fd_tdc_stop_dis_o,
spi_cs_dac_n_o => fd_spi_cs_dac_n_o,
spi_cs_pll_n_o => fd_spi_cs_pll_n_o,
spi_cs_gpio_n_o => fd_spi_cs_gpio_n_o,
spi_sclk_o => fd_spi_sclk_o,
spi_mosi_o => fd_spi_mosi_o,
spi_miso_i => fd_spi_miso_i,
delay_len_o => fd_delay_len_o,
delay_val_o => fd_delay_val_o,
delay_pulse_o => fd_delay_pulse_o,
tm_link_up_i => tm_link_up,
tm_time_valid_i => tm_time_valid,
tm_cycles_i => tm_cycles,
tm_utc_i => tm_utc,
tm_clk_aux_lock_en_o => tm_clk_aux_lock_en,
tm_clk_aux_locked_i => tm_clk_aux_locked,
tm_clk_dmtd_locked_i => '1', -- FIXME: fan out real signal from the
-- WRCore
tm_dac_value_i => tm_dac_value,
tm_dac_wr_i => tm_dac_wr,
owr_en_o => fd_owr_en,
owr_i => fd_owr_in,
i2c_scl_oen_o => fd_scl_out,
i2c_scl_i => fd_scl_in,
i2c_sda_oen_o => fd_sda_out,
i2c_sda_i => fd_sda_in,
fmc_present_n_i => fmc_prsnt_m2c_l_i,
wb_adr_i => cnx_master_out(c_SLAVE_FD).adr,
wb_dat_i => cnx_master_out(c_SLAVE_FD).dat,
wb_dat_o => cnx_master_in(c_SLAVE_FD).dat,
wb_sel_i => cnx_master_out(c_SLAVE_FD).sel,
wb_cyc_i => cnx_master_out(c_SLAVE_FD).cyc,
wb_stb_i => cnx_master_out(c_SLAVE_FD).stb,
wb_we_i => cnx_master_out(c_SLAVE_FD).we,
wb_ack_o => cnx_master_in(c_SLAVE_FD).ack,
wb_stall_o => cnx_master_in(c_SLAVE_FD).stall,
wb_irq_o => fd_irq);
-- tristate buffer for the TDC data bus:
fd_tdc_d_b <= tdc_data_out when tdc_data_oe = '1' else (others => 'Z');
fd_tdc_oe_n_o <= '1';
tdc_data_in <= fd_tdc_d_b;
fd_onewire_b <= '0' when fd_owr_en = '1' else 'Z';
fd_owr_in <= fd_onewire_b;
U_Debugger : wb_debugger
generic map(
g_dbg_init_file => "FD_node"
)
port map(
clk_sys => clk_sys,
reset_n => local_reset_n,
master_i => cnx_slave_out(c_MASTER_DEBUGGER),
master_o => cnx_slave_in(c_MASTER_DEBUGGER),
slave_i => cnx_master_out(c_SLAVE_DEBG),
slave_o => cnx_master_in(c_SLAVE_DEBG),
wrpc_uart_rxd_i => wrpc_uart_rxd_i,
wrpc_uart_txd_o => wrpc_uart_txd_o,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
dbg_indicator => LED_RED,
dbg_control_select => button2_i
);
end rtl;
| gpl-3.0 | 1869daa0710c35b9b825c290d3bf969a | 0.502906 | 3.02696 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/pcie_core/example_design/PIO_EP.vhd | 1 | 13,056 | -------------------------------------------------------------------------------
--
-- (c) Copyright 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : PIO_EP.vhd
-- Description: Endpoint Programmed I/O module.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
entity PIO_EP is
port (
-- Common
clk : in std_logic;
rst_n : in std_logic;
-- LocalLink Tx
trn_td : out std_logic_vector(31 downto 0);
trn_tsof_n : out std_logic;
trn_teof_n : out std_logic;
trn_tsrc_dsc_n : out std_logic;
trn_tsrc_rdy_n : out std_logic;
trn_tdst_dsc_n : in std_logic;
trn_tdst_rdy_n : in std_logic;
-- LocalLink Rx
trn_rd : in std_logic_vector(31 downto 0);
trn_rsof_n : in std_logic;
trn_reof_n : in std_logic;
trn_rsrc_rdy_n : in std_logic;
trn_rsrc_dsc_n : in std_logic;
trn_rbar_hit_n : in std_logic_vector(6 downto 0);
trn_rdst_rdy_n : out std_logic;
-- Turn-off signaling
req_compl_o : out std_logic;
compl_done_o : out std_logic;
-- Configuration
cfg_completer_id : in std_logic_vector(15 downto 0);
cfg_bus_mstr_enable : in std_logic
);
end PIO_EP;
architecture rtl of PIO_EP is
-- Local signals
signal rd_addr : std_logic_vector(10 downto 0);
signal rd_be : std_logic_vector(3 downto 0);
signal rd_data : std_logic_vector(31 downto 0);
signal wr_addr : std_logic_vector(10 downto 0);
signal wr_be : std_logic_vector(7 downto 0);
signal wr_data : std_logic_vector(31 downto 0);
signal wr_en : std_logic;
signal wr_busy : std_logic;
signal req_compl : std_logic;
signal req_compl_with_data : std_logic;
signal compl_done : std_logic;
signal req_tc : std_logic_vector(2 downto 0);
signal req_td : std_logic;
signal req_ep : std_logic;
signal req_attr : std_logic_vector(1 downto 0);
signal req_len : std_logic_vector(9 downto 0);
signal req_rid : std_logic_vector(15 downto 0);
signal req_tag : std_logic_vector(7 downto 0);
signal req_be : std_logic_vector(7 downto 0);
signal req_addr : std_logic_vector(12 downto 0);
component PIO_32_RX_ENGINE is
port (
clk : in std_logic;
rst_n : in std_logic;
trn_rd : in std_logic_vector(31 downto 0);
trn_rsof_n : in std_logic;
trn_reof_n : in std_logic;
trn_rsrc_rdy_n : in std_logic;
trn_rsrc_dsc_n : in std_logic;
trn_rbar_hit_n : in std_logic_vector(6 downto 0);
trn_rdst_rdy_n : out std_logic;
req_compl_o : out std_logic;
req_compl_with_data_o : out std_logic;
compl_done_i : in std_logic;
req_tc_o : out std_logic_vector(2 downto 0); -- Memory Read TC
req_td_o : out std_logic; -- Memory Read TD
req_ep_o : out std_logic; -- Memory Read EP
req_attr_o : out std_logic_vector(1 downto 0); -- Memory Read Attribute
req_len_o : out std_logic_vector(9 downto 0); -- Memory Read Length (1DW)
req_rid_o : out std_logic_vector(15 downto 0); -- Memory Read Requestor ID
req_tag_o : out std_logic_vector(7 downto 0); -- Memory Read Tag
req_be_o : out std_logic_vector(7 downto 0); -- Memory Read Byte Enables
req_addr_o : out std_logic_vector(12 downto 0); -- Memory Read Address
wr_addr_o : out std_logic_vector(10 downto 0); -- Memory Write Address
wr_be_o : out std_logic_vector(7 downto 0); -- Memory Write Byte Enable
wr_data_o : out std_logic_vector(31 downto 0); -- Memory Write Data
wr_en_o : out std_logic; -- Memory Write Enable
wr_busy_i : in std_logic -- Memory Write Busy
);
end component;
component PIO_32_TX_ENGINE is
port (
clk : in std_logic;
rst_n : in std_logic;
trn_td : out std_logic_vector(31 downto 0);
trn_tsof_n : out std_logic;
trn_teof_n : out std_logic;
trn_tsrc_rdy_n : out std_logic;
trn_tsrc_dsc_n : out std_logic;
trn_tdst_rdy_n : in std_logic;
trn_tdst_dsc_n : in std_logic;
req_compl_i : in std_logic;
req_compl_with_data_i : in std_logic;
compl_done_o : out std_logic;
req_tc_i : in std_logic_vector(2 downto 0);
req_td_i : in std_logic;
req_ep_i : in std_logic;
req_attr_i : in std_logic_vector(1 downto 0);
req_len_i : in std_logic_vector(9 downto 0);
req_rid_i : in std_logic_vector(15 downto 0);
req_tag_i : in std_logic_vector(7 downto 0);
req_be_i : in std_logic_vector(7 downto 0);
req_addr_i : in std_logic_vector(12 downto 0);
rd_addr_o : out std_logic_vector(10 downto 0);
rd_be_o : out std_logic_vector(3 downto 0);
rd_data_i : in std_logic_vector(31 downto 0);
completer_id_i : in std_logic_vector(15 downto 0);
cfg_bus_mstr_enable_i : in std_logic
);
end component;
component PIO_EP_MEM_ACCESS is
port (
clk : in std_logic;
rst_n : in std_logic;
-- Read Port
rd_addr_i : in std_logic_vector(10 downto 0);
rd_be_i : in std_logic_vector(3 downto 0);
rd_data_o : out std_logic_vector(31 downto 0);
-- Write Port
wr_addr_i : in std_logic_vector(10 downto 0);
wr_be_i : in std_logic_vector(7 downto 0);
wr_data_i : in std_logic_vector(31 downto 0);
wr_en_i : in std_logic;
wr_busy_o : out std_logic
);
end component;
signal trn_td_int : std_logic_vector(31 downto 0);
begin
trn_td <= trn_td_int;
req_compl_o <= req_compl;
compl_done_o <= compl_done;
--
-- ENDPOINT MEMORY : 8KB memory aperture implemented in FPGA BlockRAM(*)
--
EP_MEM : PIO_EP_MEM_ACCESS
port map (
clk => clk, -- I
rst_n => rst_n, -- I
-- Read Port
rd_addr_i => rd_addr, -- I [10:0]
rd_be_i => rd_be, -- I [3:0]
rd_data_o => rd_data, -- O [31:0]
-- Write Port
wr_addr_i => wr_addr, -- I [10:0]
wr_be_i => wr_be, -- I [7:0]
wr_data_i => wr_data, -- I [31:0]
wr_en_i => wr_en, -- I
wr_busy_o => wr_busy -- O
);
--
-- Local-Link Receive Controller
--
EP_RX : PIO_32_RX_ENGINE
port map (
clk => clk, -- I
rst_n => rst_n, -- I
-- LocalLink Rx
trn_rd => trn_rd, -- I [31:0]
trn_rsof_n => trn_rsof_n, -- I
trn_reof_n => trn_reof_n, -- I
trn_rsrc_rdy_n => trn_rsrc_rdy_n, -- I
trn_rsrc_dsc_n => trn_rsrc_dsc_n, -- I
trn_rbar_hit_n => trn_rbar_hit_n, -- I [6:0]
trn_rdst_rdy_n => trn_rdst_rdy_n, -- O
-- Handshake with Tx engine
req_compl_o => req_compl, -- O
req_compl_with_data_o => req_compl_with_data, -- O
compl_done_i => compl_done, -- I
req_tc_o => req_tc, -- O [2:0]
req_td_o => req_td, -- O
req_ep_o => req_ep, -- O
req_attr_o => req_attr, -- O [1:0]
req_len_o => req_len, -- O [9:0]
req_rid_o => req_rid, -- O [15:0]
req_tag_o => req_tag, -- O [7:0]
req_be_o => req_be, -- O [7:0]
req_addr_o => req_addr, -- O [12:0]
-- Memory Write Port
wr_addr_o => wr_addr, -- O [10:0]
wr_be_o => wr_be, -- O [7:0]
wr_data_o => wr_data, -- O [31:0]
wr_en_o => wr_en, -- O
wr_busy_i => wr_busy -- I
);
--
-- Local-Link Transmit Controller
--
EP_TX : PIO_32_TX_ENGINE
port map (
clk => clk, -- I
rst_n => rst_n, -- I
-- LocalLink Tx
trn_td => trn_td_int, -- O [31:0]
trn_tsof_n => trn_tsof_n, -- O
trn_teof_n => trn_teof_n, -- O
trn_tsrc_dsc_n => trn_tsrc_dsc_n, -- O
trn_tsrc_rdy_n => trn_tsrc_rdy_n, -- O
trn_tdst_dsc_n => trn_tdst_dsc_n, -- I
trn_tdst_rdy_n => trn_tdst_rdy_n, -- I
-- Handshake with Rx engine
req_compl_i => req_compl, -- I
req_compl_with_data_i => req_compl_with_data, -- I
compl_done_o => compl_done, -- 0
req_tc_i => req_tc, -- I [2:0]
req_td_i => req_td, -- I
req_ep_i => req_ep, -- I
req_attr_i => req_attr, -- I [1:0]
req_len_i => req_len, -- I [9:0]
req_rid_i => req_rid, -- I [15:0]
req_tag_i => req_tag, -- I [7:0]
req_be_i => req_be, -- I [7:0]
req_addr_i => req_addr, -- I [12:0]
-- Read Port
rd_addr_o => rd_addr, -- O [10:0]
rd_be_o => rd_be, -- O [3:0]
rd_data_i => rd_data, -- I [31:0]
completer_id_i => cfg_completer_id, -- I [15:0]
cfg_bus_mstr_enable_i => cfg_bus_mstr_enable -- I
);
end rtl;
| gpl-3.0 | b83c2b4c82c35ee0e32910fe8af7e031 | 0.490809 | 3.430373 | false | false | false | false |
masaruohashi/tic-tac-toe | uart/contador_16_recepcao.vhd | 1 | 949 | -- VHDL de um contador de modulo 16
-- OBS: Para esse experimento so eh utilizada a contagem ate 11
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity contador_16_recepcao is
port(
clock : in std_logic;
enable : in std_logic;
zera : in std_logic;
conta : in std_logic;
contagem : out std_logic_vector(3 downto 0);
fim : out std_logic
);
end contador_16_recepcao;
architecture exemplo of contador_16_recepcao is
signal IQ: unsigned(3 downto 0);
begin
process (clock, conta, IQ, zera)
begin
if zera = '1' then
IQ <= (others => '0');
elsif clock'event and clock = '1' then
if (conta = '1' and enable = '1') then
IQ <= IQ + 1;
end if;
end if;
if IQ = 11 then
fim <= '1';
else
fim <= '0';
end if;
contagem <= std_logic_vector(IQ);
end process;
end exemplo;
| mit | a8f7b3642ed58f2eaad26f85c71876f1 | 0.572181 | 3.30662 | false | false | false | false |
masaruohashi/tic-tac-toe | uart/gerador_tick.vhd | 1 | 737 | -- gerador_tick.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity gerador_tick is
generic(
M: integer := 454545 -- para transmissao de 110 bauds
);
port(
clock, reset: in std_logic;
tick: out std_logic
);
end gerador_tick;
architecture arch of gerador_tick is
signal contagem, prox_contagem: integer;
begin
process(clock,reset)
begin
if (reset='1') then
contagem <= 0;
elsif (clock'event and clock='1') then
contagem <= prox_contagem;
end if;
end process;
-- logica de proximo estado
prox_contagem <= 0 when contagem=(M-1) else contagem + 1;
-- logica de saida
tick <= '1' when contagem=(M-1) else '0';
end arch;
| mit | 7b634ca93accd1b3d878be38cd36fa5f | 0.630936 | 3.476415 | false | false | false | false |
adelapie/noekeon_loop | noekeon_loop_k_4.vhd | 1 | 10,146 |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- This is loop unrolling (for K = 2) implementation of the NOEKEON block
-- cipher relying on the direct mode of the cipher. This means that
-- key schedule is not performed.
entity noekeon_loop_k_4 is
port(clk : in std_logic;
rst : in std_logic;
enc : in std_logic; -- (enc, 0) / (dec, 1)
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end noekeon_loop_k_4;
architecture Behavioral of noekeon_loop_k_4 is
component round_f is
port(enc : in std_logic;
rc_in : in std_logic_vector(31 downto 0);
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
component rc_shr is
port(clk : in std_logic;
rst : in std_logic;
rc_in : in std_logic_vector(71 downto 0);
rc_out : out std_logic_vector(7 downto 0));
end component;
component output_trans is
port(clk : in std_logic;
enc : in std_logic; -- (enc, 0) / (dec, 1)
rc_in : in std_logic_vector(31 downto 0);
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
component theta is
port(a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
signal rc_s : std_logic_vector(7 downto 0);
signal rc_2_s : std_logic_vector(7 downto 0);
signal rc_3_s : std_logic_vector(7 downto 0);
signal rc_4_s : std_logic_vector(7 downto 0);
signal rc_ext_s : std_logic_vector(31 downto 0);
signal rc_2_ext_s : std_logic_vector(31 downto 0);
signal rc_3_ext_s : std_logic_vector(31 downto 0);
signal rc_4_ext_s : std_logic_vector(31 downto 0);
signal a_0_in_s : std_logic_vector(31 downto 0);
signal a_1_in_s : std_logic_vector(31 downto 0);
signal a_2_in_s : std_logic_vector(31 downto 0);
signal a_3_in_s : std_logic_vector(31 downto 0);
signal out_t_a_0_in_s : std_logic_vector(31 downto 0);
signal out_t_a_1_in_s : std_logic_vector(31 downto 0);
signal out_t_a_2_in_s : std_logic_vector(31 downto 0);
signal out_t_a_3_in_s : std_logic_vector(31 downto 0);
signal a_0_out_s : std_logic_vector(31 downto 0);
signal a_1_out_s : std_logic_vector(31 downto 0);
signal a_2_out_s : std_logic_vector(31 downto 0);
signal a_3_out_s : std_logic_vector(31 downto 0);
signal stage_0_a_0_out_s : std_logic_vector(31 downto 0);
signal stage_0_a_1_out_s : std_logic_vector(31 downto 0);
signal stage_0_a_2_out_s : std_logic_vector(31 downto 0);
signal stage_0_a_3_out_s : std_logic_vector(31 downto 0);
signal stage_1_a_0_out_s : std_logic_vector(31 downto 0);
signal stage_1_a_1_out_s : std_logic_vector(31 downto 0);
signal stage_1_a_2_out_s : std_logic_vector(31 downto 0);
signal stage_1_a_3_out_s : std_logic_vector(31 downto 0);
signal stage_2_a_0_out_s : std_logic_vector(31 downto 0);
signal stage_2_a_1_out_s : std_logic_vector(31 downto 0);
signal stage_2_a_2_out_s : std_logic_vector(31 downto 0);
signal stage_2_a_3_out_s : std_logic_vector(31 downto 0);
signal k_0_d_s : std_logic_vector(31 downto 0);
signal k_1_d_s : std_logic_vector(31 downto 0);
signal k_2_d_s : std_logic_vector(31 downto 0);
signal k_3_d_s : std_logic_vector(31 downto 0);
signal k_0_mux_s : std_logic_vector(31 downto 0);
signal k_1_mux_s : std_logic_vector(31 downto 0);
signal k_2_mux_s : std_logic_vector(31 downto 0);
signal k_3_mux_s : std_logic_vector(31 downto 0);
signal init_val_shr_0 : std_logic_vector(71 downto 0);
signal init_val_shr_1 : std_logic_vector(71 downto 0);
signal init_val_shr_2 : std_logic_vector(71 downto 0);
signal init_val_shr_3 : std_logic_vector(71 downto 0);
begin
init_val_shr_0 <= X"80d82fc6d400000000";
init_val_shr_1 <= X"1bab5e97d400000000";
init_val_shr_2 <= X"364dbc35d400000000";
init_val_shr_3 <= X"6c9a636ad400000000";
RC_SHR_0 : rc_shr port map (clk, rst, init_val_shr_0, rc_s);
RC_SHR_1 : rc_shr port map (clk, rst, init_val_shr_1, rc_2_s);
RC_SHR_2 : rc_shr port map (clk, rst, init_val_shr_2, rc_3_s);
RC_SHR_3 : rc_shr port map (clk, rst, init_val_shr_3, rc_4_s);
rc_ext_s <= X"000000" & rc_s;
rc_2_ext_s <= X"000000" & rc_2_s;
rc_3_ext_s <= X"000000" & rc_3_s;
rc_4_ext_s <= X"000000" & rc_4_s;
ROUND_F_0 : round_f port map (enc,
rc_ext_s,
a_0_in_s,
a_1_in_s,
a_2_in_s,
a_3_in_s,
k_0_mux_s,
k_1_mux_s,
k_2_mux_s,
k_3_mux_s,
stage_0_a_0_out_s,
stage_0_a_1_out_s,
stage_0_a_2_out_s,
stage_0_a_3_out_s);
ROUND_F_1 : round_f port map (enc,
rc_2_ext_s,
stage_0_a_0_out_s,
stage_0_a_1_out_s,
stage_0_a_2_out_s,
stage_0_a_3_out_s,
k_0_mux_s,
k_1_mux_s,
k_2_mux_s,
k_3_mux_s,
stage_1_a_0_out_s,
stage_1_a_1_out_s,
stage_1_a_2_out_s,
stage_1_a_3_out_s);
ROUND_F_2 : round_f port map (enc,
rc_3_ext_s,
stage_1_a_0_out_s,
stage_1_a_1_out_s,
stage_1_a_2_out_s,
stage_1_a_3_out_s,
k_0_mux_s,
k_1_mux_s,
k_2_mux_s,
k_3_mux_s,
stage_2_a_0_out_s,
stage_2_a_1_out_s,
stage_2_a_2_out_s,
stage_2_a_3_out_s);
ROUND_F_3 : round_f port map (enc,
rc_4_ext_s,
stage_2_a_0_out_s,
stage_2_a_1_out_s,
stage_2_a_2_out_s,
stage_2_a_3_out_s,
k_0_mux_s,
k_1_mux_s,
k_2_mux_s,
k_3_mux_s,
a_0_out_s,
a_1_out_s,
a_2_out_s,
a_3_out_s);
pr_noe: process(clk, rst, enc)
begin
if rising_edge(clk) then
if rst = '1' then
a_0_in_s <= a_0_in;
a_1_in_s <= a_1_in;
a_2_in_s <= a_2_in;
a_3_in_s <= a_3_in;
else
a_0_in_s <= a_0_out_s;
a_1_in_s <= a_1_out_s;
a_2_in_s <= a_2_out_s;
a_3_in_s <= a_3_out_s;
end if;
end if;
end process;
-- Key decryption as k' = theta(0, k)
-- This is the key required for decryption
-- in NOEKEON
THETA_DECRYPT_0 : theta port map (
k_0_in,
k_1_in,
k_2_in,
k_3_in,
(others => '0'),
(others => '0'),
(others => '0'),
(others => '0'),
k_0_d_s,
k_1_d_s,
k_2_d_s,
k_3_d_s);
-- These multiplexers select the key that is used
-- in each mode i.e. during decryption the key generated
-- as k' = theta(0, k) (THETA_DECRYPT_0) is utilized.
k_0_mux_s <= k_0_in when enc = '0' else k_0_d_s;
k_1_mux_s <= k_1_in when enc = '0' else k_1_d_s;
k_2_mux_s <= k_2_in when enc = '0' else k_2_d_s;
k_3_mux_s <= k_3_in when enc = '0' else k_3_d_s;
out_trans_pr: process(clk, rst, a_0_out_s, a_1_out_s, a_2_out_s, a_3_out_s)
begin
if rising_edge(clk) then
out_t_a_0_in_s <= a_0_out_s;
out_t_a_1_in_s <= a_1_out_s;
out_t_a_2_in_s <= a_2_out_s;
out_t_a_3_in_s <= a_3_out_s;
end if;
end process;
-- This component performs the last operation
-- with theta.
OUT_TRANS_0 : output_trans port map (clk, enc, rc_ext_s,
out_t_a_0_in_s,
out_t_a_1_in_s,
out_t_a_2_in_s,
out_t_a_3_in_s,
k_0_mux_s,
k_1_mux_s,
k_2_mux_s,
k_3_mux_s,
a_0_out,
a_1_out,
a_2_out,
a_3_out);
end Behavioral;
| gpl-3.0 | f009c78974af816ef09ed1eddedcb30f | 0.584368 | 2.436014 | false | false | false | false |
Pinwino/dbg_ohwr | debugger_gw/debugger_pkg.vhd | 1 | 7,628 | -------------------------------------------------------------------------------
-- Title : Wishbone Debugger package
-- Project : FMC DEL 1ns 4cha-stand-alone application (fmc-delay-1ns-4cha-sa)
-------------------------------------------------------------------------------
-- File : debugger_pkg.vhd
-- Author : Jose Jimenez <[email protected]>
-- Company : University of Granada
-- Created : 2014-06-08
-- Last update: 2014-07-31
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Wihsbone master with slave configuration interface for gateware
-- debuggin porpuses. Also provides a framework for stand alone
-- operation.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-06-08 1.0 jjimenez Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
----use work.gn4124_core_pkg.all;
--use work.gencores_pkg.all;
--use work.wrcore_pkg.all;
----use work.wr_fabric_pkg.all;
--use work.wishbone_pkg.all;
----use work.fine_delay_pkg.all;
----use work.etherbone_pkg.all;
----use work.wr_xilinx_pkg.all;
--use work.genram_pkg.all;
--use work.wb_irq_pkg.all;
----use work.gencores_pkg.all;
use work.wishbone_pkg.all;
--use work.genram_pkg.all;
--use work.wb_irq_pkg.all;
--use work.debugger_pkg.all;
--
--use work.synthesis_descriptor.all;
package debugger_pkg is
------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
constant c_dbg_uart_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"0deafbee", -- she didn't listen & cames & goes
version => x"00000001",
date => x"20120305",
name => "WB-UART-Debugger ")));
constant c_dbg_irq_ctrl_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"0000000000000651", -- GSI
device_id => x"e1fb1ade", -- balanced, perfect grip, absolute control
version => x"00000001",
date => x"20120308",
name => "IRQ_CTRL-Debugger ")));
constant c_xwb_dbg_tics_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"00",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"0000000000000000",
product => (
vendor_id => x"000000000000CE42", -- GSIx
device_id => x"fade1eaf", -- Time is always ticking!
version => x"00000001",
date => x"20111004",
name => "WB-Tics-Debugger ")));
constant c_dbg_irq_timer_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"0000000000000651", -- GSI
device_id => x"deadface", -- eventully "the dead line" is going to arrive
version => x"00000001",
date => x"20120308",
name => "IRQ_TIMER-Debugger ")));
constant c_xwb_dbg_slave_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"00",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000003ffff",
product => (
vendor_id => x"a1eBEEFc0ffeeBED", -- Jose Jimenez Motel. Open 24/7. Next exit.
device_id => x"c0a110de", -- obvious (sadly)
version => x"00000001",
date => x"20140704",
name => "Debugger-Slave ")));
------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
function f_xwb_dbg_dpram(g_size : natural) return t_sdb_device
is
variable result : t_sdb_device;
begin
result.abi_class := x"0001"; -- RAM device
result.abi_ver_major := x"01";
result.abi_ver_minor := x"00";
result.wbd_width := x"7"; -- 32/16/8-bit supported
result.wbd_endian := c_sdb_endian_big;
result.sdb_component.addr_first := (others => '0');
result.sdb_component.addr_last := std_logic_vector(to_unsigned(g_size*4-1, 64));
result.sdb_component.product.vendor_id := x"000000000000CE42"; -- CERN
result.sdb_component.product.device_id := x"deafbeef"; -- she didn't listen & is as essential as protein
result.sdb_component.product.version := x"00000001";
result.sdb_component.product.date := x"20120305";
result.sdb_component.product.name := "BlockRAM-Debugger ";
return result;
end f_xwb_dbg_dpram;
------------------------------------------------------------------------------
-- Components declaration
-------------------------------------------------------------------------------
component wb_debugger is
generic (
g_dbg_dpram_size : integer := 40960/4;
g_dbg_init_file : string;
g_reset_vector : t_wishbone_address := x"00000000";
g_msi_queues : natural := 1;
g_profile : string := "medium_icache_debug";
g_internal_time_ref : boolean := true;
g_timers : integer := 1;
g_slave_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_slave_granularity : t_wishbone_address_granularity := BYTE
);
port (
clk_sys : in std_logic;
reset_n : in std_logic;
master_i : in t_wishbone_master_in;
master_o : out t_wishbone_master_out;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
wrpc_uart_rxd_i : inout std_logic;
wrpc_uart_txd_o : inout std_logic;
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
dbg_indicator : out std_logic;
dbg_control_select : in std_logic
);
end component;
end debugger_pkg;
package body debugger_pkg is
-- Notihg to include right now!!!
end debugger_pkg;
| gpl-3.0 | c55d9d6b369e3e2e4eb8d50069a22a13 | 0.499082 | 3.72825 | false | false | false | false |
JavierRizzoA/Sacagawea | sources/prueba_dispositivos.vhd | 1 | 3,920 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:38:10 06/05/2016
-- Design Name:
-- Module Name: C:/Users/AlvaroMoreno/Desktop/proooc/sacagawea_copy/prueba_dispositivos.vhd
-- Project Name: Sacagawea
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Dispositivos
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY prueba_dispositivos IS
END prueba_dispositivos;
ARCHITECTURE behavior OF prueba_dispositivos IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Dispositivos
PORT(
ar : in std_logic_vector(11 downto 0);
clk : in std_logic;
ram_w_r: in std_logic;
bus_datos : inout std_logic_vector(7 downto 0);
sal_leds_spartan : out std_logic_vector(7 downto 0);
in_switches_spartan : in std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal ar : std_logic_vector(11 downto 0) := (others => '0');
signal clk : std_logic := '0';
signal ram_w_r : std_logic := '0';
signal in_switches_spartan : std_logic_vector(7 downto 0) := (others => '0');
--BiDirs
signal bus_datos : std_logic_vector(7 downto 0);
--Outputs
signal sal_leds_spartan : std_logic_vector(7 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Dispositivos PORT MAP (
ar => ar,
clk => clk,
ram_w_r => ram_w_r,
bus_datos => bus_datos,
sal_leds_spartan => sal_leds_spartan,
in_switches_spartan => in_switches_spartan
);
-- Stimulus process
stim_proc: process
begin
wait for 100 ns;
clk <= '0';
ar <= X"0FF";
bus_datos <= "ZZZZZZZZ";
wait for 100 ns;
clk <= '1';
ar <= X"0FF"; --primer dato de ROM
wait for 100 ns;
clk <= '0';
ar <= X"099";
wait for 100 ns;
clk <= '1';
ar <= X"099"; --segundo dato de ROM
wait for 100 ns;
clk <= '0';
ar <= X"5FA";
ram_w_r <= '0';
wait for 100 ns;
clk <= '1';
bus_datos <= X"A5"; --escribir primer dato a RAM 10100101
ar <= X"5FA";
ram_w_r <= '1';
wait for 100 ns;
clk <= '0';
ar <= X"467";
ram_w_r <= '0';
wait for 100 ns;
clk <= '1';
bus_datos <= X"62"; --escribir segundo dato a RAM 01100010
ar <= X"467";
ram_w_r <= '1';
wait for 100 ns;
clk <= '0';
ar <= X"467";
ram_w_r <= '0';
wait for 100 ns;
clk <= '1';
ar <= X"467"; --se lee el dato en [467] -> X"62" -> 01100010
ram_w_r <= '0';
wait for 100 ns;
clk <= '0';
ar <= X"900";
bus_datos <= "ZZZZZZZZ";
wait for 100 ns;
clk <= '1';
bus_datos <= X"55"; --se escribe a leds 01010101
ar <= X"900";
wait for 100 ns;
clk <= '0';
in_switches_spartan <= X"A3";
--bus_datos <= "ZZZZZZZZ";
ar <= X"EFF";
wait for 100 ns;
clk <= '1';
in_switches_spartan <= X"A3"; --se meten a switches el numero A3 -> 10100011
ar <= X"EFF";
wait for 100 ns;
wait;
end process;
END;
| mit | 46f261464ba5be357e7d4dd9c5fb785d | 0.540306 | 3.250415 | false | false | false | false |
Nixon-/VHDL_library | basic/nbit_half_adder.vhd | 2 | 605 | Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity nbit_half_adder is
generic(n: integer:=4);
port(
opA,opB: in std_logic_vector(n-1 downto 0);
carry_out: out std_logic;
sum: out std_logic_vector(n-1 downto 0)
);
end nbit_half_adder;
architecture primary of nbit_half_adder is
signal tempSum: std_logic_vector(n downto 0);
signal intSum: integer;
begin
intSum <= to_integer(unsigned(opA)) + to_integer(unsigned(opB));
tempSum <= std_logic_vector(to_unsigned(intSum,n+1));
carry_out <= tempSum(n);
sum <= tempSum(n-1 downto 0);
end primary; | gpl-2.0 | bf787de96659a12788b814962c9331db | 0.684298 | 2.75 | false | false | false | false |
masaruohashi/tic-tac-toe | logica_jogo/registrador_jogada.vhd | 1 | 1,176 | -- VHDL do Sistema Digital
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity registrador_jogada is
port(
clock: in std_logic;
reset: in std_logic;
guarda_jogada: in std_logic;
jogador: in std_logic;
entrada: in std_logic_vector(3 downto 0);
jogadas_realizadas: out std_logic_vector(8 downto 0);
jogadas_jogador: out std_logic_vector(8 downto 0)
);
end registrador_jogada;
architecture comportamental of registrador_jogada is
signal sinal_jogadas: std_logic_vector(8 downto 0) := "000000000";
signal sinal_jogador: std_logic_vector(8 downto 0) := "000000000";
begin
process(clock, reset, guarda_jogada, jogador, entrada)
begin
if reset='1' then
sinal_jogadas <= (others => '0');
sinal_jogador <= (others => '0');
elsif clock'event and clock='1' then
if guarda_jogada='1' then
sinal_jogadas(to_integer(unsigned(entrada))) <= '1';
if jogador = '1' then
sinal_jogador(to_integer(unsigned(entrada))) <= '1';
end if;
end if;
end if;
jogadas_realizadas <= sinal_jogadas;
jogadas_jogador <= sinal_jogador;
end process;
end comportamental;
| mit | 1201bf7e1d5ac493b4ecacf99a239609 | 0.665816 | 3.303371 | false | false | false | false |
adelapie/noekeon_loop | tb_noekeon_loop_k_4.vhd | 1 | 4,677 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:15:32 02/25/2015
-- Design Name:
-- Module Name: C:/Users/vmr/Desktop/noekeon_loop/noekeon_loop/tb_noekeon_loop_k_4.vhd
-- Project Name: noekeon_loop
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: noekeon_loop_k_4
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_noekeon_loop_k_4 IS
END tb_noekeon_loop_k_4;
ARCHITECTURE behavior OF tb_noekeon_loop_k_4 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT noekeon_loop_k_4
PORT(
clk : IN std_logic;
rst : IN std_logic;
enc : IN std_logic;
a_0_in : IN std_logic_vector(31 downto 0);
a_1_in : IN std_logic_vector(31 downto 0);
a_2_in : IN std_logic_vector(31 downto 0);
a_3_in : IN std_logic_vector(31 downto 0);
k_0_in : IN std_logic_vector(31 downto 0);
k_1_in : IN std_logic_vector(31 downto 0);
k_2_in : IN std_logic_vector(31 downto 0);
k_3_in : IN std_logic_vector(31 downto 0);
a_0_out : OUT std_logic_vector(31 downto 0);
a_1_out : OUT std_logic_vector(31 downto 0);
a_2_out : OUT std_logic_vector(31 downto 0);
a_3_out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal enc : std_logic := '0';
signal a_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_3_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_3_in : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal a_0_out : std_logic_vector(31 downto 0);
signal a_1_out : std_logic_vector(31 downto 0);
signal a_2_out : std_logic_vector(31 downto 0);
signal a_3_out : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: noekeon_loop_k_4 PORT MAP (
clk => clk,
rst => rst,
enc => enc,
a_0_in => a_0_in,
a_1_in => a_1_in,
a_2_in => a_2_in,
a_3_in => a_3_in,
k_0_in => k_0_in,
k_1_in => k_1_in,
k_2_in => k_2_in,
k_3_in => k_3_in,
a_0_out => a_0_out,
a_1_out => a_1_out,
a_2_out => a_2_out,
a_3_out => a_3_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + clk_period;
rst <= '1';
enc <= '0';
a_0_in <= X"2a78421b";
a_1_in <= X"87c7d092";
a_2_in <= X"4f26113f";
a_3_in <= X"1d1349b2";
k_0_in <= X"b1656851";
k_1_in <= X"699e29fa";
k_2_in <= X"24b70148";
k_3_in <= X"503d2dfc";
wait for clk_period;
rst <= '0';
wait for clk_period*3 + clk_period/2;
assert a_0_out = X"e2f687e0"
report "ENCRYPT ERROR (a_0)" severity FAILURE;
assert a_1_out = X"7b75660f"
report "ENCRYPT ERROR (a_1)" severity FAILURE;
assert a_2_out = X"fc372233"
report "ENCRYPT ERROR (a_2)" severity FAILURE;
assert a_3_out = X"bc47532c"
report "ENCRYPT ERROR (a_3)" severity FAILURE;
wait;
end process;
END;
| gpl-3.0 | 2faade024af406dbd1c3ba6609978b5c | 0.545007 | 3.085092 | false | false | false | false |
JavierRizzoA/Sacagawea | sources/Alu_regs.vhd | 1 | 3,312 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:01:07 06/04/2016
-- Design Name:
-- Module Name: Alu_regs - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Alu_regs is
port(
clk: IN STD_LOGIC;
mbr_sal: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
control: IN STD_LOGIC_VECTOR(24 DOWNTO 0);
alu_sal: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
ma, me, z: OUT STD_LOGIC
);
end Alu_regs;
architecture Behavioral of Alu_regs is
component Alu
port (s_muxa, s_muxb : in std_logic_vector(7 downto 0);
ctrl_alu : in std_logic_vector(3 downto 0);
s_alu : out std_logic_vector(7 downto 0));
end component;
component Mux4to1_8bit
port(A, B, C, D : in std_logic_vector(7 downto 0);
sel : in std_logic_vector(1 downto 0);
S : out std_logic_vector(7 downto 0));
end component;
component Register8
Port (
d : in STD_LOGIC_VECTOR(7 downto 0); --Input.
load : in STD_LOGIC; --Load/Enable.
clr : in STD_LOGIC; --Async clear.
clk : in STD_LOGIC; --Clock.
q : out STD_LOGIC_VECTOR(7 downto 0) --Output
);
end component;
component Register4
Port (
d : in STD_LOGIC_VECTOR(3 downto 0); --Input.
load : in STD_LOGIC; --Load/Enable.
clr : in STD_LOGIC; --Async clear.
clk : in STD_LOGIC; --Clock.
q : out STD_LOGIC_VECTOR(3 downto 0) --Output
);
end component;
component ALUToFlag
Port (
alu_sal : in STD_LOGIC_VECTOR (7 downto 0);
ma : out STD_LOGIC;
me : out STD_LOGIC;
z : out STD_LOGIC);
end component;
SIGNAL mux_a_sal, mux_b_sal, alu_sal_gay : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL r0_sal, r1_sal, r2_sal : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL nomamez : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL flag_reg_sal : STD_LOGIC_VECTOR(3 DOWNTO 0);
begin
nomamez(3) <= '0';
aluvergas: Alu port map(mux_a_sal, mux_b_sal, control(22 DOWNTO 19), alu_sal_gay);
alu_sal <= alu_sal_gay;
muxa: Mux4to1_8bit port map(r0_sal, r1_sal, r2_sal, mbr_sal, control(3 DOWNTO 2), mux_a_sal);
muxb: Mux4to1_8bit port map(r0_sal, r1_sal, r2_sal, mbr_sal, control(1 DOWNTO 0), mux_b_sal);
r0: Register8 port map(alu_sal_gay, control(13), '0', clk, r0_sal);
r1: Register8 port map(alu_sal_gay, control(12), '0', clk, r1_sal);
r2: Register8 port map(alu_sal_gay, control(11), '0', clk, r2_sal);
aluflag: ALUToFlag port map(alu_sal_gay, nomamez(2), nomamez(1), nomamez(0));
flagreg: Register4 port map(nomamez, control(10), '0', clk, flag_reg_sal);
ma <= flag_reg_sal(2);
me <= flag_reg_sal(1);
z <= flag_reg_sal(0);
end Behavioral;
| mit | 8f9785f85b3073508735c6edff5ccb6c | 0.595713 | 3.069509 | false | false | false | false |
Nixon-/VHDL_library | arithmetic/to_test/booth_multiplier.vhd | 1 | 2,475 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:48:55 01/25/2014
-- Design Name: Nicolas Primeau
-- Module Name: booth_multiplier - Behavioral
-- Project Name: Booth Multiplier
-- Target Devices: Xilinx Spartan 6
-- Tool versions:
-- Description: A simple hardware implementation of a booth multiplier
--
-- Dependencies: ieee libraries
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity booth_multiplier is
generic(
n: integer:=4 -- number of bits per vector
);
port(
multiplicand: in std_logic_vector(n-1 downto 0);
multiplier: in std_logic_vector(n-1 downto 0);
result: out std_logic_vector(n*2 -1 downto 0);
clk,enable,load: in std_logic
);
end booth_multiplier;
architecture Behavioral of booth_multiplier is
signal Q: std_logic_vector(n-1 downto 0) := multiplier;
signal M: std_logic_vector(n-1 downto 0) := multiplicand;
signal notM: std_logic_vector(n-1 downto 0):= not(multiplier);
signal A: std_logic_vector(n-1 downto 0) := (others => '0');
signal Qright: std_logic:='0';
begin
process(clk,enable,load,Q,M,notM,A,Qright) is
variable cRes,nRes: std_logic_vector(n*2 -1 downto 0);
begin
if(clk' event and clk = '1') then
if(enable = '1') then
if(load = '1') then
nRes(n*2 -1 downto n) := A;
nRes(n-1 downto 0) := Q;
else
for I in n to 1 loop
if(cRes(0) = '0' AND Qright = '1') then
A <= std_logic_vector(to_unsigned((to_integer(unsigned(A)) + to_integer(unsigned(M))),n));
elsif (cRes(0) = '1' AND Qright = '0') then
A <= std_logic_vector(to_unsigned((to_integer(unsigned(A)) + to_integer(unsigned(notM))),n));
end if;
nRes(n*2 -2 downto n-1) := A; -- technically an arith shift right
nRes(n-2 downto 0):=cRes(n-1 downto 1); -- ^
Qright <= cRes(0);
end loop;
end if;
end if;
cRes := nRes;
result <= nRes;
end if;
end process;
end Behavioral;
| gpl-2.0 | d99176fde6d4273123a394d05d348216 | 0.603636 | 3.269485 | false | false | false | false |
masaruohashi/tic-tac-toe | interface_jogo/mapeador_caractere.vhd | 1 | 995 | -- VHDL de um mapeador de caracteres
library ieee;
use ieee.std_logic_1164.all;
entity mapeador_caractere is
port(
caractere: in std_logic_vector(6 downto 0);
posicao_memoria: out std_logic_vector(6 downto 0)
);
end mapeador_caractere;
architecture estrutural of mapeador_caractere is
begin
process (caractere)
begin
case caractere is
when "0110111" =>
posicao_memoria <= "0001011";
when "0111000" =>
posicao_memoria <= "0001111";
when "0111001" =>
posicao_memoria <= "0010011";
when "0110100" =>
posicao_memoria <= "0100011";
when "0110101" =>
posicao_memoria <= "0100111";
when "0110110" =>
posicao_memoria <= "0101011";
when "0110001" =>
posicao_memoria <= "0111011";
when "0110010" =>
posicao_memoria <= "0111111";
when "0110011" =>
posicao_memoria <= "1000011";
when others =>
null;
end case;
end process;
end estrutural;
| mit | 782b286ad0082aa40b03a036ef9600bc | 0.601005 | 3.856589 | false | false | false | false |
adelapie/noekeon_loop | rc_gen_stage_2.vhd | 1 | 1,685 |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity rc_gen_stage_2 is
port(clk : in std_logic;
rst : in std_logic;
enc : in std_logic; -- 0 (enc), 1 (dec)
rc_out : out std_logic_vector(7 downto 0));
end rc_gen_stage_2;
architecture Behavioral of rc_gen_stage_2 is
signal rc_s : std_logic_vector(7 downto 0);
begin
pr_gen: process(clk, rst, enc)
begin
if rising_edge(clk) then
if rst = '1' then
if enc = '0' then
rc_s <= X"1b"; --80
else
rc_s <= X"D4";
end if;
else
if enc = '0' then
if ((rc_s and X"80") = X"00") then
rc_s <= rc_s(6 downto 0) & '0';
else
rc_s <= (rc_s(6 downto 0) & '0') xor X"1B";
end if;
else
if ((rc_s and X"01") = X"00") then
rc_s <= '0' & rc_s(7 downto 1);
else
rc_s <= ('0' & rc_s(7 downto 1)) xor X"8D";
end if;
end if;
end if;
end if;
end process;
rc_out <= rc_s;
end Behavioral;
| gpl-3.0 | a93f9432839b5eb9fb660a272e351aaa | 0.602374 | 3.025135 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/ddr3_controller/user_design/sim/sim_tb_top.vhd | 1 | 49,537 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.9
-- \ \ Application : MIG
-- / / Filename : sim_tb_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:58 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
-- Device : Spartan-6
-- Design Name : DDR/DDR2/DDR3/LPDDR
-- Purpose : This is the simulation testbench which is used to verify the
-- design. The basic clocks and resets to the interface are
-- generated here. This also connects the memory interface to the
-- memory model.
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity sim_tb_top is
end entity sim_tb_top;
architecture arch of sim_tb_top is
-- ========================================================================== --
-- Parameters --
-- ========================================================================== --
constant DEBUG_EN : integer :=0;
constant C1_HW_TESTING : string := "FALSE";
constant C3_HW_TESTING : string := "FALSE";
function c1_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) ) return std_logic_vector is
begin
if (C1_HW_TESTING = "FALSE") then
return val1;
else
return val2;
end if;
end function;
function c3_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) ) return std_logic_vector is
begin
if (C3_HW_TESTING = "FALSE") then
return val1;
else
return val2;
end if;
end function;
constant C1_MEMCLK_PERIOD : integer := 2500;
constant C1_RST_ACT_LOW : integer := 0;
constant C1_INPUT_CLK_TYPE : string := "DIFFERENTIAL";
constant C1_CLK_PERIOD_NS : real := 2500.0 / 1000.0;
constant C1_TCYC_SYS : real := C1_CLK_PERIOD_NS/2.0;
constant C1_TCYC_SYS_DIV2 : time := C1_TCYC_SYS * 1 ns;
constant C1_NUM_DQ_PINS : integer := 16;
constant C1_MEM_ADDR_WIDTH : integer := 14;
constant C1_MEM_BANKADDR_WIDTH : integer := 3;
constant C1_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
constant C1_P0_MASK_SIZE : integer := 4;
constant C1_P0_DATA_PORT_SIZE : integer := 32;
constant C1_P1_MASK_SIZE : integer := 4;
constant C1_P1_DATA_PORT_SIZE : integer := 32;
constant C1_MEM_BURST_LEN : integer := 8;
constant C1_MEM_NUM_COL_BITS : integer := 10;
constant C1_SIMULATION : string := "TRUE";
constant C1_CALIB_SOFT_IP : string := "TRUE";
constant C3_MEMCLK_PERIOD : integer := 2500;
constant C3_RST_ACT_LOW : integer := 0;
constant C3_INPUT_CLK_TYPE : string := "DIFFERENTIAL";
constant C3_CLK_PERIOD_NS : real := 2500.0 / 1000.0;
constant C3_TCYC_SYS : real := C3_CLK_PERIOD_NS/2.0;
constant C3_TCYC_SYS_DIV2 : time := C3_TCYC_SYS * 1 ns;
constant C3_NUM_DQ_PINS : integer := 16;
constant C3_MEM_ADDR_WIDTH : integer := 14;
constant C3_MEM_BANKADDR_WIDTH : integer := 3;
constant C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
constant C3_P0_MASK_SIZE : integer := 4;
constant C3_P0_DATA_PORT_SIZE : integer := 32;
constant C3_P1_MASK_SIZE : integer := 4;
constant C3_P1_DATA_PORT_SIZE : integer := 32;
constant C3_MEM_BURST_LEN : integer := 8;
constant C3_MEM_NUM_COL_BITS : integer := 10;
constant C3_SIMULATION : string := "TRUE";
constant C3_CALIB_SOFT_IP : string := "TRUE";
constant C1_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c1_sim_hw (x"00000100", x"01000000");
constant C1_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant C1_p0_END_ADDRESS : std_logic_vector(31 downto 0) := c1_sim_hw (x"000002ff", x"02ffffff");
constant C1_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c1_sim_hw (x"fffffc00", x"fc000000");
constant C1_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c1_sim_hw (x"00000100", x"01000000");
constant C3_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000");
constant C3_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant C3_p0_END_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"000002ff", x"02ffffff");
constant C3_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"fffffc00", x"fc000000");
constant C3_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000");
-- ========================================================================== --
-- Component Declarations
-- ========================================================================== --
component ddr3_controller is
generic
(
C1_P0_MASK_SIZE : integer;
C1_P0_DATA_PORT_SIZE : integer;
C1_P1_MASK_SIZE : integer;
C1_P1_DATA_PORT_SIZE : integer;
C1_MEMCLK_PERIOD : integer;
C1_RST_ACT_LOW : integer;
C1_INPUT_CLK_TYPE : string;
DEBUG_EN : integer;
C1_CALIB_SOFT_IP : string;
C1_SIMULATION : string;
C1_MEM_ADDR_ORDER : string;
C1_NUM_DQ_PINS : integer;
C1_MEM_ADDR_WIDTH : integer;
C1_MEM_BANKADDR_WIDTH : integer;
C3_P0_MASK_SIZE : integer;
C3_P0_DATA_PORT_SIZE : integer;
C3_P1_MASK_SIZE : integer;
C3_P1_DATA_PORT_SIZE : integer;
C3_MEMCLK_PERIOD : integer;
C3_RST_ACT_LOW : integer;
C3_INPUT_CLK_TYPE : string;
C3_CALIB_SOFT_IP : string;
C3_SIMULATION : string;
C3_MEM_ADDR_ORDER : string;
C3_NUM_DQ_PINS : integer;
C3_MEM_ADDR_WIDTH : integer;
C3_MEM_BANKADDR_WIDTH : integer
);
port
(
mcb1_dram_dq : inout std_logic_vector(C1_NUM_DQ_PINS-1 downto 0);
mcb1_dram_a : out std_logic_vector(C1_MEM_ADDR_WIDTH-1 downto 0);
mcb1_dram_ba : out std_logic_vector(C1_MEM_BANKADDR_WIDTH-1 downto 0);
mcb1_dram_ras_n : out std_logic;
mcb1_dram_cas_n : out std_logic;
mcb1_dram_we_n : out std_logic;
mcb1_dram_odt : out std_logic;
mcb1_dram_cke : out std_logic;
mcb1_dram_dm : out std_logic;
mcb1_rzq : inout std_logic;
mcb1_zio : inout std_logic;
c1_sys_clk_p : in std_logic;
c1_sys_clk_n : in std_logic;
c1_sys_rst_i : in std_logic;
c1_calib_done : out std_logic;
c1_clk0 : out std_logic;
c1_rst0 : out std_logic;
mcb1_dram_dqs : inout std_logic;
mcb1_dram_dqs_n : inout std_logic;
mcb1_dram_ck : out std_logic;
mcb1_dram_udqs : inout std_logic;
mcb1_dram_udqs_n : inout std_logic;
mcb1_dram_udm : out std_logic;
mcb1_dram_ck_n : out std_logic;
mcb1_dram_reset_n : out std_logic; mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
c3_sys_clk_p : in std_logic;
c3_sys_clk_n : in std_logic;
c3_sys_rst_i : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_ck_n : out std_logic;
mcb3_dram_reset_n : out std_logic; c1_p0_cmd_clk : in std_logic;
c1_p0_cmd_en : in std_logic;
c1_p0_cmd_instr : in std_logic_vector(2 downto 0);
c1_p0_cmd_bl : in std_logic_vector(5 downto 0);
c1_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c1_p0_cmd_empty : out std_logic;
c1_p0_cmd_full : out std_logic;
c1_p0_wr_clk : in std_logic;
c1_p0_wr_en : in std_logic;
c1_p0_wr_mask : in std_logic_vector(C1_P0_MASK_SIZE - 1 downto 0);
c1_p0_wr_data : in std_logic_vector(C1_P0_DATA_PORT_SIZE - 1 downto 0);
c1_p0_wr_full : out std_logic;
c1_p0_wr_empty : out std_logic;
c1_p0_wr_count : out std_logic_vector(6 downto 0);
c1_p0_wr_underrun : out std_logic;
c1_p0_wr_error : out std_logic;
c1_p0_rd_clk : in std_logic;
c1_p0_rd_en : in std_logic;
c1_p0_rd_data : out std_logic_vector(C1_P0_DATA_PORT_SIZE - 1 downto 0);
c1_p0_rd_full : out std_logic;
c1_p0_rd_empty : out std_logic;
c1_p0_rd_count : out std_logic_vector(6 downto 0);
c1_p0_rd_overflow : out std_logic;
c1_p0_rd_error : out std_logic;
c3_p0_cmd_clk : in std_logic;
c3_p0_cmd_en : in std_logic;
c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p0_cmd_empty : out std_logic;
c3_p0_cmd_full : out std_logic;
c3_p0_wr_clk : in std_logic;
c3_p0_wr_en : in std_logic;
c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_wr_full : out std_logic;
c3_p0_wr_empty : out std_logic;
c3_p0_wr_count : out std_logic_vector(6 downto 0);
c3_p0_wr_underrun : out std_logic;
c3_p0_wr_error : out std_logic;
c3_p0_rd_clk : in std_logic;
c3_p0_rd_en : in std_logic;
c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_rd_full : out std_logic;
c3_p0_rd_empty : out std_logic;
c3_p0_rd_count : out std_logic_vector(6 downto 0);
c3_p0_rd_overflow : out std_logic;
c3_p0_rd_error : out std_logic
);
end component;
component ddr3_model_c1 is
port (
ck : in std_logic;
ck_n : in std_logic;
cke : in std_logic;
cs_n : in std_logic;
ras_n : in std_logic;
cas_n : in std_logic;
we_n : in std_logic;
dm_tdqs : inout std_logic_vector((C1_NUM_DQ_PINS/16) downto 0);
ba : in std_logic_vector((C1_MEM_BANKADDR_WIDTH - 1) downto 0);
addr : in std_logic_vector((C1_MEM_ADDR_WIDTH - 1) downto 0);
dq : inout std_logic_vector((C1_NUM_DQ_PINS - 1) downto 0);
dqs : inout std_logic_vector((C1_NUM_DQ_PINS/16) downto 0);
dqs_n : inout std_logic_vector((C1_NUM_DQ_PINS/16) downto 0);
tdqs_n : out std_logic_vector((C1_NUM_DQ_PINS/16) downto 0);
odt : in std_logic;
rst_n : in std_logic
);
end component;
component ddr3_model_c3 is
port (
ck : in std_logic;
ck_n : in std_logic;
cke : in std_logic;
cs_n : in std_logic;
ras_n : in std_logic;
cas_n : in std_logic;
we_n : in std_logic;
dm_tdqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
ba : in std_logic_vector((C3_MEM_BANKADDR_WIDTH - 1) downto 0);
addr : in std_logic_vector((C3_MEM_ADDR_WIDTH - 1) downto 0);
dq : inout std_logic_vector((C3_NUM_DQ_PINS - 1) downto 0);
dqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
dqs_n : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
tdqs_n : out std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
odt : in std_logic;
rst_n : in std_logic
);
end component;
component memc1_tb_top is
generic
(
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_MEM_BURST_LEN : integer := 8;
C_MEM_NUM_COL_BITS : integer := 11;
C_NUM_DQ_PINS : integer := 8;
C_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000100";
C_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p0_END_ADDRESS : std_logic_vector(31 downto 0) := X"000002ff";
C_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffffc00";
C_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000100"
);
port
(
clk0 : in std_logic;
rst0 : in std_logic;
calib_done : in std_logic;
p0_mcb_cmd_en_o : out std_logic;
p0_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p0_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p0_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p0_mcb_cmd_full_i : in std_logic;
p0_mcb_wr_en_o : out std_logic;
p0_mcb_wr_mask_o : out std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_mcb_wr_data_o : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_wr_full_i : in std_logic;
p0_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p0_mcb_rd_en_o : out std_logic;
p0_mcb_rd_data_i : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_rd_empty_i : in std_logic;
p0_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
cmp_error : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(127 downto 0)
);
end component;
component memc3_tb_top is
generic
(
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_MEM_BURST_LEN : integer := 8;
C_MEM_NUM_COL_BITS : integer := 11;
C_NUM_DQ_PINS : integer := 8;
C_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000100";
C_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p0_END_ADDRESS : std_logic_vector(31 downto 0) := X"000002ff";
C_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffffc00";
C_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000100"
);
port
(
clk0 : in std_logic;
rst0 : in std_logic;
calib_done : in std_logic;
p0_mcb_cmd_en_o : out std_logic;
p0_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p0_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p0_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p0_mcb_cmd_full_i : in std_logic;
p0_mcb_wr_en_o : out std_logic;
p0_mcb_wr_mask_o : out std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_mcb_wr_data_o : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_wr_full_i : in std_logic;
p0_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p0_mcb_rd_en_o : out std_logic;
p0_mcb_rd_data_i : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_rd_empty_i : in std_logic;
p0_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
cmp_error : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(127 downto 0)
);
end component;
-- ========================================================================== --
-- Signal Declarations --
-- ========================================================================== --
-- Clocks
-- Clocks
signal c1_sys_clk : std_logic := '0';
signal c1_sys_clk_p : std_logic;
signal c1_sys_clk_n : std_logic;
-- System Reset
signal c1_sys_rst : std_logic := '0';
signal c1_sys_rst_i : std_logic;
-- Design-Top Port Map
signal c1_error : std_logic;
signal c1_calib_done : std_logic;
signal c1_error_status : std_logic_vector(127 downto 0);
signal mcb1_dram_a : std_logic_vector(C1_MEM_ADDR_WIDTH-1 downto 0);
signal mcb1_dram_ba : std_logic_vector(C1_MEM_BANKADDR_WIDTH-1 downto 0);
signal mcb1_dram_ck : std_logic;
signal mcb1_dram_ck_n : std_logic;
signal mcb1_dram_dq : std_logic_vector(C1_NUM_DQ_PINS-1 downto 0);
signal mcb1_dram_dqs : std_logic;
signal mcb1_dram_dqs_n : std_logic;
signal mcb1_dram_dm : std_logic;
signal mcb1_dram_ras_n : std_logic;
signal mcb1_dram_cas_n : std_logic;
signal mcb1_dram_we_n : std_logic;
signal mcb1_dram_cke : std_logic;
signal mcb1_dram_odt : std_logic;
signal mcb1_dram_reset_n : std_logic;
signal mcb1_dram_udqs : std_logic;
signal mcb1_dram_udqs_n : std_logic;
signal mcb1_dram_dqs_vector : std_logic_vector(1 downto 0);
signal mcb1_dram_dqs_n_vector : std_logic_vector(1 downto 0);
signal mcb1_dram_udm :std_logic; -- for X16 parts
signal mcb1_dram_dm_vector : std_logic_vector(1 downto 0);
-- User design Sim
signal c1_clk0 : std_logic;
signal c1_rst0 : std_logic;
signal c1_cmp_error : std_logic;
signal c1_vio_modify_enable : std_logic;
signal c1_vio_data_mode_value : std_logic_vector(2 downto 0);
signal c1_vio_addr_mode_value : std_logic_vector(2 downto 0);
signal mcb1_command : std_logic_vector(2 downto 0);
signal mcb1_enable1 : std_logic;
signal mcb1_enable2 : std_logic;
signal c1_p0_cmd_en : std_logic;
signal c1_p0_cmd_instr : std_logic_vector(2 downto 0);
signal c1_p0_cmd_bl : std_logic_vector(5 downto 0);
signal c1_p0_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c1_p0_cmd_empty : std_logic;
signal c1_p0_cmd_full : std_logic;
signal c1_p0_wr_en : std_logic;
signal c1_p0_wr_mask : std_logic_vector(C1_P0_MASK_SIZE - 1 downto 0);
signal c1_p0_wr_data : std_logic_vector(C1_P0_DATA_PORT_SIZE - 1 downto 0);
signal c1_p0_wr_full : std_logic;
signal c1_p0_wr_empty : std_logic;
signal c1_p0_wr_count : std_logic_vector(6 downto 0);
signal c1_p0_wr_underrun : std_logic;
signal c1_p0_wr_error : std_logic;
signal c1_p0_rd_en : std_logic;
signal c1_p0_rd_data : std_logic_vector(C1_P0_DATA_PORT_SIZE - 1 downto 0);
signal c1_p0_rd_full : std_logic;
signal c1_p0_rd_empty : std_logic;
signal c1_p0_rd_count : std_logic_vector(6 downto 0);
signal c1_p0_rd_overflow : std_logic;
signal c1_p0_rd_error : std_logic;
signal c1_selfrefresh_enter : std_logic;
signal c1_selfrefresh_mode : std_logic;
-- Clocks
-- Clocks
signal c3_sys_clk : std_logic := '0';
signal c3_sys_clk_p : std_logic;
signal c3_sys_clk_n : std_logic;
-- System Reset
signal c3_sys_rst : std_logic := '0';
signal c3_sys_rst_i : std_logic;
-- Design-Top Port Map
signal c3_error : std_logic;
signal c3_calib_done : std_logic;
signal c3_error_status : std_logic_vector(127 downto 0);
signal mcb3_dram_a : std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
signal mcb3_dram_ba : std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
signal mcb3_dram_ck : std_logic;
signal mcb3_dram_ck_n : std_logic;
signal mcb3_dram_dq : std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
signal mcb3_dram_dqs : std_logic;
signal mcb3_dram_dqs_n : std_logic;
signal mcb3_dram_dm : std_logic;
signal mcb3_dram_ras_n : std_logic;
signal mcb3_dram_cas_n : std_logic;
signal mcb3_dram_we_n : std_logic;
signal mcb3_dram_cke : std_logic;
signal mcb3_dram_odt : std_logic;
signal mcb3_dram_reset_n : std_logic;
signal mcb3_dram_udqs : std_logic;
signal mcb3_dram_udqs_n : std_logic;
signal mcb3_dram_dqs_vector : std_logic_vector(1 downto 0);
signal mcb3_dram_dqs_n_vector : std_logic_vector(1 downto 0);
signal mcb3_dram_udm :std_logic; -- for X16 parts
signal mcb3_dram_dm_vector : std_logic_vector(1 downto 0);
-- User design Sim
signal c3_clk0 : std_logic;
signal c3_rst0 : std_logic;
signal c3_cmp_error : std_logic;
signal c3_vio_modify_enable : std_logic;
signal c3_vio_data_mode_value : std_logic_vector(2 downto 0);
signal c3_vio_addr_mode_value : std_logic_vector(2 downto 0);
signal mcb3_command : std_logic_vector(2 downto 0);
signal mcb3_enable1 : std_logic;
signal mcb3_enable2 : std_logic;
signal c3_p0_cmd_en : std_logic;
signal c3_p0_cmd_instr : std_logic_vector(2 downto 0);
signal c3_p0_cmd_bl : std_logic_vector(5 downto 0);
signal c3_p0_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c3_p0_cmd_empty : std_logic;
signal c3_p0_cmd_full : std_logic;
signal c3_p0_wr_en : std_logic;
signal c3_p0_wr_mask : std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
signal c3_p0_wr_data : std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
signal c3_p0_wr_full : std_logic;
signal c3_p0_wr_empty : std_logic;
signal c3_p0_wr_count : std_logic_vector(6 downto 0);
signal c3_p0_wr_underrun : std_logic;
signal c3_p0_wr_error : std_logic;
signal c3_p0_rd_en : std_logic;
signal c3_p0_rd_data : std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
signal c3_p0_rd_full : std_logic;
signal c3_p0_rd_empty : std_logic;
signal c3_p0_rd_count : std_logic_vector(6 downto 0);
signal c3_p0_rd_overflow : std_logic;
signal c3_p0_rd_error : std_logic;
signal c3_selfrefresh_enter : std_logic;
signal c3_selfrefresh_mode : std_logic;
signal rzq1 : std_logic;
signal rzq3 : std_logic;
signal zio1 : std_logic;
signal zio3 : std_logic;
signal calib_done : std_logic;
signal error : std_logic;
function vector (asi:std_logic) return std_logic_vector is
variable v : std_logic_vector(0 downto 0) ;
begin
v(0) := asi;
return(v);
end function vector;
begin
-- ========================================================================== --
-- Clocks Generation --
-- ========================================================================== --
process
begin
c1_sys_clk <= not c1_sys_clk;
wait for (C1_TCYC_SYS_DIV2);
end process;
c1_sys_clk_p <= c1_sys_clk;
c1_sys_clk_n <= not c1_sys_clk;
process
begin
c3_sys_clk <= not c3_sys_clk;
wait for (C3_TCYC_SYS_DIV2);
end process;
c3_sys_clk_p <= c3_sys_clk;
c3_sys_clk_n <= not c3_sys_clk;
-- ========================================================================== --
-- Reset Generation --
-- ========================================================================== --
process
begin
c1_sys_rst <= '0';
wait for 200 ns;
c1_sys_rst <= '1';
wait;
end process;
c1_sys_rst_i <= c1_sys_rst when (C1_RST_ACT_LOW = 1) else (not c1_sys_rst);
process
begin
c3_sys_rst <= '0';
wait for 200 ns;
c3_sys_rst <= '1';
wait;
end process;
c3_sys_rst_i <= c3_sys_rst when (C3_RST_ACT_LOW = 1) else (not c3_sys_rst);
error <= c1_error or c3_error;
calib_done <= c1_calib_done and c3_calib_done;
-- The PULLDOWN component is connected to the ZIO signal primarily to avoid the
-- unknown state in simulation. In real hardware, ZIO should be a no connect(NC) pin.
zio_pulldown1 : PULLDOWN port map(O => zio1);
zio_pulldown3 : PULLDOWN port map(O => zio3);
rzq_pulldown1 : PULLDOWN port map(O => rzq1);
rzq_pulldown3 : PULLDOWN port map(O => rzq3);
-- ========================================================================== --
-- DESIGN TOP INSTANTIATION --
-- ========================================================================== --
design_top : ddr3_controller generic map
(
C1_P0_MASK_SIZE => C1_P0_MASK_SIZE,
C1_P0_DATA_PORT_SIZE => C1_P0_DATA_PORT_SIZE,
C1_P1_MASK_SIZE => C1_P1_MASK_SIZE,
C1_P1_DATA_PORT_SIZE => C1_P1_DATA_PORT_SIZE,
C1_MEMCLK_PERIOD => C1_MEMCLK_PERIOD,
C1_RST_ACT_LOW => C1_RST_ACT_LOW,
C1_INPUT_CLK_TYPE => C1_INPUT_CLK_TYPE,
DEBUG_EN => DEBUG_EN,
C1_MEM_ADDR_ORDER => C1_MEM_ADDR_ORDER,
C1_NUM_DQ_PINS => C1_NUM_DQ_PINS,
C1_MEM_ADDR_WIDTH => C1_MEM_ADDR_WIDTH,
C1_MEM_BANKADDR_WIDTH => C1_MEM_BANKADDR_WIDTH,
C1_SIMULATION => C1_SIMULATION,
C1_CALIB_SOFT_IP => C1_CALIB_SOFT_IP,
C3_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C3_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C3_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C3_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C3_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
C3_RST_ACT_LOW => C3_RST_ACT_LOW,
C3_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
C3_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
C3_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C3_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
C3_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH,
C3_SIMULATION => C3_SIMULATION,
C3_CALIB_SOFT_IP => C3_CALIB_SOFT_IP
)
port map (
c1_sys_clk_p => c1_sys_clk_p,
c1_sys_clk_n => c1_sys_clk_n,
c1_sys_rst_i => c1_sys_rst_i,
mcb1_dram_dq => mcb1_dram_dq,
mcb1_dram_a => mcb1_dram_a,
mcb1_dram_ba => mcb1_dram_ba,
mcb1_dram_ras_n => mcb1_dram_ras_n,
mcb1_dram_cas_n => mcb1_dram_cas_n,
mcb1_dram_we_n => mcb1_dram_we_n,
mcb1_dram_odt => mcb1_dram_odt,
mcb1_dram_cke => mcb1_dram_cke,
mcb1_dram_ck => mcb1_dram_ck,
mcb1_dram_ck_n => mcb1_dram_ck_n,
mcb1_dram_dqs => mcb1_dram_dqs,
mcb1_dram_dqs_n => mcb1_dram_dqs_n,
mcb1_dram_reset_n => mcb1_dram_reset_n,
mcb1_dram_udqs => mcb1_dram_udqs, -- for X16 parts
mcb1_dram_udqs_n => mcb1_dram_udqs_n, -- for X16 parts
mcb1_dram_udm => mcb1_dram_udm, -- for X16 parts
mcb1_dram_dm => mcb1_dram_dm,
c1_clk0 => c1_clk0,
c1_rst0 => c1_rst0,
c1_calib_done => c1_calib_done,
mcb1_rzq => rzq1,
mcb1_zio => zio1,
c1_p0_cmd_clk => (c1_clk0),
c1_p0_cmd_en => c1_p0_cmd_en,
c1_p0_cmd_instr => c1_p0_cmd_instr,
c1_p0_cmd_bl => c1_p0_cmd_bl,
c1_p0_cmd_byte_addr => c1_p0_cmd_byte_addr,
c1_p0_cmd_empty => c1_p0_cmd_empty,
c1_p0_cmd_full => c1_p0_cmd_full,
c1_p0_wr_clk => (c1_clk0),
c1_p0_wr_en => c1_p0_wr_en,
c1_p0_wr_mask => c1_p0_wr_mask,
c1_p0_wr_data => c1_p0_wr_data,
c1_p0_wr_full => c1_p0_wr_full,
c1_p0_wr_empty => c1_p0_wr_empty,
c1_p0_wr_count => c1_p0_wr_count,
c1_p0_wr_underrun => c1_p0_wr_underrun,
c1_p0_wr_error => c1_p0_wr_error,
c1_p0_rd_clk => (c1_clk0),
c1_p0_rd_en => c1_p0_rd_en,
c1_p0_rd_data => c1_p0_rd_data,
c1_p0_rd_full => c1_p0_rd_full,
c1_p0_rd_empty => c1_p0_rd_empty,
c1_p0_rd_count => c1_p0_rd_count,
c1_p0_rd_overflow => c1_p0_rd_overflow,
c1_p0_rd_error => c1_p0_rd_error,
c3_sys_clk_p => c3_sys_clk_p,
c3_sys_clk_n => c3_sys_clk_n,
c3_sys_rst_i => c3_sys_rst_i,
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_reset_n => mcb3_dram_reset_n,
mcb3_dram_udqs => mcb3_dram_udqs, -- for X16 parts
mcb3_dram_udqs_n => mcb3_dram_udqs_n, -- for X16 parts
mcb3_dram_udm => mcb3_dram_udm, -- for X16 parts
mcb3_dram_dm => mcb3_dram_dm,
c3_clk0 => c3_clk0,
c3_rst0 => c3_rst0,
c3_calib_done => c3_calib_done,
mcb3_rzq => rzq3,
mcb3_zio => zio3,
c3_p0_cmd_clk => (c3_clk0),
c3_p0_cmd_en => c3_p0_cmd_en,
c3_p0_cmd_instr => c3_p0_cmd_instr,
c3_p0_cmd_bl => c3_p0_cmd_bl,
c3_p0_cmd_byte_addr => c3_p0_cmd_byte_addr,
c3_p0_cmd_empty => c3_p0_cmd_empty,
c3_p0_cmd_full => c3_p0_cmd_full,
c3_p0_wr_clk => (c3_clk0),
c3_p0_wr_en => c3_p0_wr_en,
c3_p0_wr_mask => c3_p0_wr_mask,
c3_p0_wr_data => c3_p0_wr_data,
c3_p0_wr_full => c3_p0_wr_full,
c3_p0_wr_empty => c3_p0_wr_empty,
c3_p0_wr_count => c3_p0_wr_count,
c3_p0_wr_underrun => c3_p0_wr_underrun,
c3_p0_wr_error => c3_p0_wr_error,
c3_p0_rd_clk => (c3_clk0),
c3_p0_rd_en => c3_p0_rd_en,
c3_p0_rd_data => c3_p0_rd_data,
c3_p0_rd_full => c3_p0_rd_full,
c3_p0_rd_empty => c3_p0_rd_empty,
c3_p0_rd_count => c3_p0_rd_count,
c3_p0_rd_overflow => c3_p0_rd_overflow,
c3_p0_rd_error => c3_p0_rd_error
);
-- user interface
memc1_tb_top_inst : memc1_tb_top generic map
(
C_NUM_DQ_PINS => C1_NUM_DQ_PINS,
C_MEM_BURST_LEN => C1_MEM_BURST_LEN,
C_MEM_NUM_COL_BITS => C1_MEM_NUM_COL_BITS,
C_P0_MASK_SIZE => C1_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C1_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C1_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C1_P1_DATA_PORT_SIZE,
C_p0_BEGIN_ADDRESS => C1_p0_BEGIN_ADDRESS,
C_p0_DATA_MODE => C1_p0_DATA_MODE,
C_p0_END_ADDRESS => C1_p0_END_ADDRESS,
C_p0_PRBS_EADDR_MASK_POS => C1_p0_PRBS_EADDR_MASK_POS,
C_p0_PRBS_SADDR_MASK_POS => C1_p0_PRBS_SADDR_MASK_POS
)
port map
(
clk0 => c1_clk0,
rst0 => c1_rst0,
calib_done => c1_calib_done,
cmp_error => c1_cmp_error,
error => c1_error,
error_status => c1_error_status,
vio_modify_enable => c1_vio_modify_enable,
vio_data_mode_value => c1_vio_data_mode_value,
vio_addr_mode_value => c1_vio_addr_mode_value,
p0_mcb_cmd_en_o => c1_p0_cmd_en,
p0_mcb_cmd_instr_o => c1_p0_cmd_instr,
p0_mcb_cmd_bl_o => c1_p0_cmd_bl,
p0_mcb_cmd_addr_o => c1_p0_cmd_byte_addr,
p0_mcb_cmd_full_i => c1_p0_cmd_full,
p0_mcb_wr_en_o => c1_p0_wr_en,
p0_mcb_wr_mask_o => c1_p0_wr_mask,
p0_mcb_wr_data_o => c1_p0_wr_data,
p0_mcb_wr_full_i => c1_p0_wr_full,
p0_mcb_wr_fifo_counts => c1_p0_wr_count,
p0_mcb_rd_en_o => c1_p0_rd_en,
p0_mcb_rd_data_i => c1_p0_rd_data,
p0_mcb_rd_empty_i => c1_p0_rd_empty,
p0_mcb_rd_fifo_counts => c1_p0_rd_count
);
-- user interface
memc3_tb_top_inst : memc3_tb_top generic map
(
C_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C_MEM_BURST_LEN => C3_MEM_BURST_LEN,
C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS,
C_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C_p0_BEGIN_ADDRESS => C3_p0_BEGIN_ADDRESS,
C_p0_DATA_MODE => C3_p0_DATA_MODE,
C_p0_END_ADDRESS => C3_p0_END_ADDRESS,
C_p0_PRBS_EADDR_MASK_POS => C3_p0_PRBS_EADDR_MASK_POS,
C_p0_PRBS_SADDR_MASK_POS => C3_p0_PRBS_SADDR_MASK_POS
)
port map
(
clk0 => c3_clk0,
rst0 => c3_rst0,
calib_done => c3_calib_done,
cmp_error => c3_cmp_error,
error => c3_error,
error_status => c3_error_status,
vio_modify_enable => c3_vio_modify_enable,
vio_data_mode_value => c3_vio_data_mode_value,
vio_addr_mode_value => c3_vio_addr_mode_value,
p0_mcb_cmd_en_o => c3_p0_cmd_en,
p0_mcb_cmd_instr_o => c3_p0_cmd_instr,
p0_mcb_cmd_bl_o => c3_p0_cmd_bl,
p0_mcb_cmd_addr_o => c3_p0_cmd_byte_addr,
p0_mcb_cmd_full_i => c3_p0_cmd_full,
p0_mcb_wr_en_o => c3_p0_wr_en,
p0_mcb_wr_mask_o => c3_p0_wr_mask,
p0_mcb_wr_data_o => c3_p0_wr_data,
p0_mcb_wr_full_i => c3_p0_wr_full,
p0_mcb_wr_fifo_counts => c3_p0_wr_count,
p0_mcb_rd_en_o => c3_p0_rd_en,
p0_mcb_rd_data_i => c3_p0_rd_data,
p0_mcb_rd_empty_i => c3_p0_rd_empty,
p0_mcb_rd_fifo_counts => c3_p0_rd_count
);
-- ========================================================================== --
-- Memory model instances --
-- ========================================================================== --
mcb1_command <= (mcb1_dram_ras_n & mcb1_dram_cas_n & mcb1_dram_we_n);
process(mcb1_dram_ck)
begin
if (rising_edge(mcb1_dram_ck)) then
if (c1_sys_rst = '0') then
mcb1_enable1 <= '0';
mcb1_enable2 <= '0';
elsif (mcb1_command = "100") then
mcb1_enable2 <= '0';
elsif (mcb1_command = "101") then
mcb1_enable2 <= '1';
else
mcb1_enable2 <= mcb1_enable2;
end if;
mcb1_enable1 <= mcb1_enable2;
end if;
end process;
-----------------------------------------------------------------------------
--read
-----------------------------------------------------------------------------
mcb1_dram_dqs_vector(1 downto 0) <= (mcb1_dram_udqs & mcb1_dram_dqs)
when (mcb1_enable2 = '0' and mcb1_enable1 = '0')
else "ZZ";
mcb1_dram_dqs_n_vector(1 downto 0) <= (mcb1_dram_udqs_n & mcb1_dram_dqs_n)
when (mcb1_enable2 = '0' and mcb1_enable1 = '0')
else "ZZ";
-----------------------------------------------------------------------------
--write
-----------------------------------------------------------------------------
mcb1_dram_dqs <= mcb1_dram_dqs_vector(0)
when ( mcb1_enable1 = '1') else 'Z';
mcb1_dram_udqs <= mcb1_dram_dqs_vector(1)
when (mcb1_enable1 = '1') else 'Z';
mcb1_dram_dqs_n <= mcb1_dram_dqs_n_vector(0)
when (mcb1_enable1 = '1') else 'Z';
mcb1_dram_udqs_n <= mcb1_dram_dqs_n_vector(1)
when (mcb1_enable1 = '1') else 'Z';
mcb3_command <= (mcb3_dram_ras_n & mcb3_dram_cas_n & mcb3_dram_we_n);
process(mcb3_dram_ck)
begin
if (rising_edge(mcb3_dram_ck)) then
if (c3_sys_rst = '0') then
mcb3_enable1 <= '0';
mcb3_enable2 <= '0';
elsif (mcb3_command = "100") then
mcb3_enable2 <= '0';
elsif (mcb3_command = "101") then
mcb3_enable2 <= '1';
else
mcb3_enable2 <= mcb3_enable2;
end if;
mcb3_enable1 <= mcb3_enable2;
end if;
end process;
-----------------------------------------------------------------------------
--read
-----------------------------------------------------------------------------
mcb3_dram_dqs_vector(1 downto 0) <= (mcb3_dram_udqs & mcb3_dram_dqs)
when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
else "ZZ";
mcb3_dram_dqs_n_vector(1 downto 0) <= (mcb3_dram_udqs_n & mcb3_dram_dqs_n)
when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
else "ZZ";
-----------------------------------------------------------------------------
--write
-----------------------------------------------------------------------------
mcb3_dram_dqs <= mcb3_dram_dqs_vector(0)
when ( mcb3_enable1 = '1') else 'Z';
mcb3_dram_udqs <= mcb3_dram_dqs_vector(1)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_dqs_n <= mcb3_dram_dqs_n_vector(0)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_udqs_n <= mcb3_dram_dqs_n_vector(1)
when (mcb3_enable1 = '1') else 'Z';
mcb1_dram_dm_vector <= (mcb1_dram_udm & mcb1_dram_dm);
u_mem_c1 : ddr3_model_c1 port map
(
ck => mcb1_dram_ck,
ck_n => mcb1_dram_ck_n,
cke => mcb1_dram_cke,
cs_n => '0',
ras_n => mcb1_dram_ras_n,
cas_n => mcb1_dram_cas_n,
we_n => mcb1_dram_we_n,
dm_tdqs => mcb1_dram_dm_vector,
ba => mcb1_dram_ba,
addr => mcb1_dram_a,
dq => mcb1_dram_dq,
dqs => mcb1_dram_dqs_vector,
dqs_n => mcb1_dram_dqs_n_vector,
tdqs_n => open,
odt => mcb1_dram_odt,
rst_n => mcb1_dram_reset_n
);
mcb3_dram_dm_vector <= (mcb3_dram_udm & mcb3_dram_dm);
u_mem_c3 : ddr3_model_c3 port map
(
ck => mcb3_dram_ck,
ck_n => mcb3_dram_ck_n,
cke => mcb3_dram_cke,
cs_n => '0',
ras_n => mcb3_dram_ras_n,
cas_n => mcb3_dram_cas_n,
we_n => mcb3_dram_we_n,
dm_tdqs => mcb3_dram_dm_vector,
ba => mcb3_dram_ba,
addr => mcb3_dram_a,
dq => mcb3_dram_dq,
dqs => mcb3_dram_dqs_vector,
dqs_n => mcb3_dram_dqs_n_vector,
tdqs_n => open,
odt => mcb3_dram_odt,
rst_n => mcb3_dram_reset_n
);
-----------------------------------------------------------------------------
-- Reporting the test case status
-----------------------------------------------------------------------------
Logging: process
begin
wait for 200 us;
if (calib_done = '1') then
if (error = '0') then
report ("****TEST PASSED****");
else
report ("****TEST FAILED: DATA ERROR****");
end if;
else
report ("****TEST FAILED: INITIALIZATION DID NOT COMPLETE****");
end if;
end process;
end architecture;
| gpl-3.0 | ac2c43ac48099e9c5e74ba2092750360 | 0.453156 | 3.273226 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/pcie_core/simulation/dsport/pcie_pipe_lane_v6.vhd | 1 | 15,451 | -------------------------------------------------------------------------------
--
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : pcie_pipe_lane_v6.vhd
-- Description: PIPE per lane module for Virtex6 PCIe Block
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity pcie_pipe_lane_v6 is
generic (
PIPE_PIPELINE_STAGES : integer := 0 -- 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
);
port (
pipe_rx_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_rx_data_o : out std_logic_vector(15 downto 0);
pipe_rx_valid_o : out std_logic;
pipe_rx_chanisaligned_o : out std_logic;
pipe_rx_status_o : out std_logic_vector(2 downto 0);
pipe_rx_phy_status_o : out std_logic;
pipe_rx_elec_idle_o : out std_logic;
pipe_rx_polarity_i : in std_logic;
pipe_tx_compliance_i : in std_logic;
pipe_tx_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_tx_data_i : in std_logic_vector(15 downto 0);
pipe_tx_elec_idle_i : in std_logic;
pipe_tx_powerdown_i : in std_logic_vector(1 downto 0);
pipe_rx_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_rx_data_i : in std_logic_vector(15 downto 0);
pipe_rx_valid_i : in std_logic;
pipe_rx_chanisaligned_i : in std_logic;
pipe_rx_status_i : in std_logic_vector(2 downto 0);
pipe_rx_phy_status_i : in std_logic;
pipe_rx_elec_idle_i : in std_logic;
pipe_rx_polarity_o : out std_logic;
pipe_tx_compliance_o : out std_logic;
pipe_tx_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_tx_data_o : out std_logic_vector(15 downto 0);
pipe_tx_elec_idle_o : out std_logic;
pipe_tx_powerdown_o : out std_logic_vector(1 downto 0);
pipe_clk : in std_logic;
rst_n : in std_logic
);
end pcie_pipe_lane_v6;
architecture v6_pcie of pcie_pipe_lane_v6 is
--******************************************************************//
-- Reality check. //
--******************************************************************//
constant TCQ : integer := 1; -- clock to out delay model
signal pipe_rx_char_is_k_q : std_logic_vector(1 downto 0);
signal pipe_rx_data_q : std_logic_vector(15 downto 0);
signal pipe_rx_valid_q : std_logic;
signal pipe_rx_chanisaligned_q : std_logic;
signal pipe_rx_status_q : std_logic_vector(2 downto 0);
signal pipe_rx_phy_status_q : std_logic;
signal pipe_rx_elec_idle_q : std_logic;
signal pipe_rx_polarity_q : std_logic;
signal pipe_tx_compliance_q : std_logic;
signal pipe_tx_char_is_k_q : std_logic_vector(1 downto 0);
signal pipe_tx_data_q : std_logic_vector(15 downto 0);
signal pipe_tx_elec_idle_q : std_logic;
signal pipe_tx_powerdown_q : std_logic_vector(1 downto 0);
signal pipe_rx_char_is_k_qq : std_logic_vector(1 downto 0);
signal pipe_rx_data_qq : std_logic_vector(15 downto 0);
signal pipe_rx_valid_qq : std_logic;
signal pipe_rx_chanisaligned_qq : std_logic;
signal pipe_rx_status_qq : std_logic_vector(2 downto 0);
signal pipe_rx_phy_status_qq : std_logic;
signal pipe_rx_elec_idle_qq : std_logic;
signal pipe_rx_polarity_qq : std_logic;
signal pipe_tx_compliance_qq : std_logic;
signal pipe_tx_char_is_k_qq : std_logic_vector(1 downto 0);
signal pipe_tx_data_qq : std_logic_vector(15 downto 0);
signal pipe_tx_elec_idle_qq : std_logic;
signal pipe_tx_powerdown_qq : std_logic_vector(1 downto 0);
begin
v6pcie0 : if (PIPE_PIPELINE_STAGES = 0) generate
pipe_rx_char_is_k_o <= pipe_rx_char_is_k_i;
pipe_rx_data_o <= pipe_rx_data_i;
pipe_rx_valid_o <= pipe_rx_valid_i;
pipe_rx_chanisaligned_o <= pipe_rx_chanisaligned_i;
pipe_rx_status_o <= pipe_rx_status_i;
pipe_rx_phy_status_o <= pipe_rx_phy_status_i;
pipe_rx_elec_idle_o <= pipe_rx_elec_idle_i;
pipe_rx_polarity_o <= pipe_rx_polarity_i;
pipe_tx_compliance_o <= pipe_tx_compliance_i;
pipe_tx_char_is_k_o <= pipe_tx_char_is_k_i;
pipe_tx_data_o <= pipe_tx_data_i;
pipe_tx_elec_idle_o <= pipe_tx_elec_idle_i;
pipe_tx_powerdown_o <= pipe_tx_powerdown_i;
end generate;
v6pcie1 : if (PIPE_PIPELINE_STAGES = 1) generate
process (pipe_clk)
begin
if (pipe_clk'event and pipe_clk = '1') then
if (rst_n = '1') then
pipe_rx_char_is_k_q <= "00" after (TCQ)*1 ps;
pipe_rx_data_q <= "0000000000000000" after (TCQ)*1 ps;
pipe_rx_valid_q <= '0' after (TCQ)*1 ps;
pipe_rx_chanisaligned_q <= '0' after (TCQ)*1 ps;
pipe_rx_status_q <= "000" after (TCQ)*1 ps;
pipe_rx_phy_status_q <= '0' after (TCQ)*1 ps;
pipe_rx_elec_idle_q <= '0' after (TCQ)*1 ps;
pipe_rx_polarity_q <= '0' after (TCQ)*1 ps;
pipe_tx_compliance_q <= '0' after (TCQ)*1 ps;
pipe_tx_char_is_k_q <= "00" after (TCQ)*1 ps;
pipe_tx_data_q <= "0000000000000000" after (TCQ)*1 ps;
pipe_tx_elec_idle_q <= '1' after (TCQ)*1 ps;
pipe_tx_powerdown_q <= "10" after (TCQ)*1 ps;
else
pipe_rx_char_is_k_q <= pipe_rx_char_is_k_i after (TCQ)*1 ps;
pipe_rx_data_q <= pipe_rx_data_i after (TCQ)*1 ps;
pipe_rx_valid_q <= pipe_rx_valid_i after (TCQ)*1 ps;
pipe_rx_chanisaligned_q <= pipe_rx_chanisaligned_i after (TCQ)*1 ps;
pipe_rx_status_q <= pipe_rx_status_i after (TCQ)*1 ps;
pipe_rx_phy_status_q <= pipe_rx_phy_status_i after (TCQ)*1 ps;
pipe_rx_elec_idle_q <= pipe_rx_elec_idle_i after (TCQ)*1 ps;
pipe_rx_polarity_q <= pipe_rx_polarity_i after (TCQ)*1 ps;
pipe_tx_compliance_q <= pipe_tx_compliance_i after (TCQ)*1 ps;
pipe_tx_char_is_k_q <= pipe_tx_char_is_k_i after (TCQ)*1 ps;
pipe_tx_data_q <= pipe_tx_data_i after (TCQ)*1 ps;
pipe_tx_elec_idle_q <= pipe_tx_elec_idle_i after (TCQ)*1 ps;
pipe_tx_powerdown_q <= pipe_tx_powerdown_i after (TCQ)*1 ps;
end if;
end if;
end process;
pipe_rx_char_is_k_o <= pipe_rx_char_is_k_q;
pipe_rx_data_o <= pipe_rx_data_q;
pipe_rx_valid_o <= pipe_rx_valid_q;
pipe_rx_chanisaligned_o <= pipe_rx_chanisaligned_q;
pipe_rx_status_o <= pipe_rx_status_q;
pipe_rx_phy_status_o <= pipe_rx_phy_status_q;
pipe_rx_elec_idle_o <= pipe_rx_elec_idle_q;
pipe_rx_polarity_o <= pipe_rx_polarity_q;
pipe_tx_compliance_o <= pipe_tx_compliance_q;
pipe_tx_char_is_k_o <= pipe_tx_char_is_k_q;
pipe_tx_data_o <= pipe_tx_data_q;
pipe_tx_elec_idle_o <= pipe_tx_elec_idle_q;
pipe_tx_powerdown_o <= pipe_tx_powerdown_q;
end generate;
v6pcie3 : if (PIPE_PIPELINE_STAGES = 2) generate
process (pipe_clk)
begin
if (pipe_clk'event and pipe_clk = '1') then
if (rst_n = '1') then
pipe_rx_char_is_k_q <= "00" after (TCQ)*1 ps;
pipe_rx_data_q <= "0000000000000000" after (TCQ)*1 ps;
pipe_rx_valid_q <= '0' after (TCQ)*1 ps;
pipe_rx_chanisaligned_q <= '0' after (TCQ)*1 ps;
pipe_rx_status_q <= "000" after (TCQ)*1 ps;
pipe_rx_phy_status_q <= '0' after (TCQ)*1 ps;
pipe_rx_elec_idle_q <= '0' after (TCQ)*1 ps;
pipe_rx_polarity_q <= '0' after (TCQ)*1 ps;
pipe_tx_compliance_q <= '0' after (TCQ)*1 ps;
pipe_tx_char_is_k_q <= "00" after (TCQ)*1 ps;
pipe_tx_data_q <= "0000000000000000" after (TCQ)*1 ps;
pipe_tx_elec_idle_q <= '1' after (TCQ)*1 ps;
pipe_tx_powerdown_q <= "10" after (TCQ)*1 ps;
pipe_rx_char_is_k_qq <= "00" after (TCQ)*1 ps;
pipe_rx_data_qq <= "0000000000000000" after (TCQ)*1 ps;
pipe_rx_valid_qq <= '0' after (TCQ)*1 ps;
pipe_rx_chanisaligned_qq <= '0' after (TCQ)*1 ps;
pipe_rx_status_qq <= "000" after (TCQ)*1 ps;
pipe_rx_phy_status_qq <= '0' after (TCQ)*1 ps;
pipe_rx_elec_idle_qq <= '0' after (TCQ)*1 ps;
pipe_rx_polarity_qq <= '0' after (TCQ)*1 ps;
pipe_tx_compliance_qq <= '0' after (TCQ)*1 ps;
pipe_tx_char_is_k_qq <= "00" after (TCQ)*1 ps;
pipe_tx_data_qq <= "0000000000000000" after (TCQ)*1 ps;
pipe_tx_elec_idle_qq <= '1' after (TCQ)*1 ps;
pipe_tx_powerdown_qq <= "10" after (TCQ)*1 ps;
else
pipe_rx_char_is_k_q <= pipe_rx_char_is_k_i after (TCQ)*1 ps;
pipe_rx_data_q <= pipe_rx_data_i after (TCQ)*1 ps;
pipe_rx_valid_q <= pipe_rx_valid_i after (TCQ)*1 ps;
pipe_rx_chanisaligned_q <= pipe_rx_chanisaligned_i after (TCQ)*1 ps;
pipe_rx_status_q <= pipe_rx_status_i after (TCQ)*1 ps;
pipe_rx_phy_status_q <= pipe_rx_phy_status_i after (TCQ)*1 ps;
pipe_rx_elec_idle_q <= pipe_rx_elec_idle_i after (TCQ)*1 ps;
pipe_rx_polarity_q <= pipe_rx_polarity_i after (TCQ)*1 ps;
pipe_tx_compliance_q <= pipe_tx_compliance_i after (TCQ)*1 ps;
pipe_tx_char_is_k_q <= pipe_tx_char_is_k_i after (TCQ)*1 ps;
pipe_tx_data_q <= pipe_tx_data_i after (TCQ)*1 ps;
pipe_tx_elec_idle_q <= pipe_tx_elec_idle_i after (TCQ)*1 ps;
pipe_tx_powerdown_q <= pipe_tx_powerdown_i after (TCQ)*1 ps;
pipe_rx_char_is_k_qq <= pipe_rx_char_is_k_q after (TCQ)*1 ps;
pipe_rx_data_qq <= pipe_rx_data_q after (TCQ)*1 ps;
pipe_rx_valid_qq <= pipe_rx_valid_q after (TCQ)*1 ps;
pipe_rx_chanisaligned_qq <= pipe_rx_chanisaligned_q after (TCQ)*1 ps;
pipe_rx_status_qq <= pipe_rx_status_q after (TCQ)*1 ps;
pipe_rx_phy_status_qq <= pipe_rx_phy_status_q after (TCQ)*1 ps;
pipe_rx_elec_idle_qq <= pipe_rx_elec_idle_q after (TCQ)*1 ps;
pipe_rx_polarity_qq <= pipe_rx_polarity_q after (TCQ)*1 ps;
pipe_tx_compliance_qq <= pipe_tx_compliance_q after (TCQ)*1 ps;
pipe_tx_char_is_k_qq <= pipe_tx_char_is_k_q after (TCQ)*1 ps;
pipe_tx_data_qq <= pipe_tx_data_q after (TCQ)*1 ps;
pipe_tx_elec_idle_qq <= pipe_tx_elec_idle_q after (TCQ)*1 ps;
pipe_tx_powerdown_qq <= pipe_tx_powerdown_q after (TCQ)*1 ps;
end if;
end if;
end process;
pipe_rx_char_is_k_o <= pipe_rx_char_is_k_qq;
pipe_rx_data_o <= pipe_rx_data_qq;
pipe_rx_valid_o <= pipe_rx_valid_qq;
pipe_rx_chanisaligned_o <= pipe_rx_chanisaligned_qq;
pipe_rx_status_o <= pipe_rx_status_qq;
pipe_rx_phy_status_o <= pipe_rx_phy_status_qq;
pipe_rx_elec_idle_o <= pipe_rx_elec_idle_qq;
pipe_rx_polarity_o <= pipe_rx_polarity_qq;
pipe_tx_compliance_o <= pipe_tx_compliance_qq;
pipe_tx_char_is_k_o <= pipe_tx_char_is_k_qq;
pipe_tx_data_o <= pipe_tx_data_qq;
pipe_tx_elec_idle_o <= pipe_tx_elec_idle_qq;
pipe_tx_powerdown_o <= pipe_tx_powerdown_qq;
end generate;
end v6_pcie;
| gpl-3.0 | 0b23bab46ddcf11a3113b3b2f7dacb99 | 0.517507 | 3.484664 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/top.vhd | 1 | 9,085 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity top is
generic(
C1_P0_MASK_SIZE : integer := 4;
C1_P0_DATA_PORT_SIZE : integer := 32;
C1_P1_MASK_SIZE : integer := 4;
C1_P1_DATA_PORT_SIZE : integer := 32;
C1_MEMCLK_PERIOD : integer := 2500; -- Memory data transfer clock period.
C1_RST_ACT_LOW : integer := 0; -- # = 1 for active low reset,# = 0 for active high reset.
C1_INPUT_CLK_TYPE : string := "DIFFERENTIAL"; -- input clock type DIFFERENTIAL or SINGLE_ENDED.
C1_CALIB_SOFT_IP : string := "TRUE"; -- # = TRUE, Enables the soft calibration logic, # = FALSE, Disables the soft calibration logic.
C1_SIMULATION : string := "FALSE"; -- # = TRUE, Simulating the design. Useful to reduce the simulation time, # = FALSE, Implementing the design.
C1_HW_TESTING : string := "FALSE"; -- Determines the address space accessed by the traffic generator, # = FALSE, Smaller address space, # = TRUE, Large address space.
DEBUG_EN : integer := 0; -- # = 1, Enable debug signals/controls, = 0, Disable debug signals/controls.
C1_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN"; -- The order in which user address is provided to the memory controller, ROW_BANK_COLUMN or BANK_ROW_COLUMN.
C1_NUM_DQ_PINS : integer := 16; -- External memory data width.
C1_MEM_ADDR_WIDTH : integer := 14; -- External memory address width.
C1_MEM_BANKADDR_WIDTH : integer := 3; -- External memory bank address width.
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 2500; -- Memory data transfer clock period.
C3_RST_ACT_LOW : integer := 0; -- # = 1 for active low reset, # = 0 for active high reset.
C3_INPUT_CLK_TYPE : string := "DIFFERENTIAL"; -- input clock type DIFFERENTIAL or SINGLE_ENDED.
C3_CALIB_SOFT_IP : string := "TRUE"; -- # = TRUE, Enables the soft calibration logic,# = FALSE, Disables the soft calibration logic.
C3_SIMULATION : string := "FALSE"; -- # = TRUE, Simulating the design. Useful to reduce the simulation time, # = FALSE, Implementing the design.
C3_HW_TESTING : string := "FALSE"; -- Determines the address space accessed by the traffic generator, # = FALSE, Smaller address space, # = TRUE, Large address space.
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN"; -- The order in which user address is provided to the memory controller, ROW_BANK_COLUMN or BANK_ROW_COLUMN.
C3_NUM_DQ_PINS : integer := 16; -- External memory data width.
C3_MEM_ADDR_WIDTH : integer := 14; -- External memory address width.
C3_MEM_BANKADDR_WIDTH : integer := 3); -- External memory bank address width.
port (
calib_done : out std_logic;
error : out std_logic;
mcb1_dram_dq : inout std_logic_vector(C1_NUM_DQ_PINS-1 downto 0);
mcb1_dram_a : out std_logic_vector(C1_MEM_ADDR_WIDTH-1 downto 0);
mcb1_dram_ba : out std_logic_vector(C1_MEM_BANKADDR_WIDTH-1 downto 0);
mcb1_dram_ras_n : out std_logic;
mcb1_dram_cas_n : out std_logic;
mcb1_dram_we_n : out std_logic;
mcb1_dram_odt : out std_logic;
mcb1_dram_reset_n : out std_logic;
mcb1_dram_cke : out std_logic;
mcb1_dram_dm : out std_logic;
mcb1_dram_udqs : inout std_logic;
mcb1_dram_udqs_n : inout std_logic;
mcb1_rzq : inout std_logic;
mcb1_zio : inout std_logic;
mcb1_dram_udm : out std_logic;
mcb1_c1_sys_clk_p : in std_logic;
mcb1_c1_sys_clk_n : in std_logic;
mcb1_c1_sys_rst_i : in std_logic;
mcb1_dram_dqs : inout std_logic;
mcb1_dram_dqs_n : inout std_logic;
mcb1_dram_ck : out std_logic;
mcb1_dram_ck_n : out std_logic;
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_reset_n : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_c3_sys_clk_p : in std_logic;
mcb3_c3_sys_clk_n : in std_logic;
mcb3_c3_sys_rst_i : in std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
pcie_txp : out std_logic;
pcie_txn : out std_logic;
pcie_rxp : in std_logic;
pcie_rxn : in std_logic;
pcie_sys_clk_p : in std_logic;
pcie_sys_clk_n : in std_logic;
pcie_sys_reset_n : in std_logic;
led : out std_logic_vector(2 downto 0));
end top;
architecture Behavioral of top is
begin
ddr3_inst: entity work.example_top port map(
calib_done => calib_done,
error => error,
mcb1_dram_dq => mcb1_dram_dq,
mcb1_dram_a => mcb1_dram_a,
mcb1_dram_ba => mcb1_dram_ba,
mcb1_dram_ras_n => mcb1_dram_ras_n,
mcb1_dram_cas_n => mcb1_dram_cas_n,
mcb1_dram_we_n => mcb1_dram_we_n,
mcb1_dram_odt => mcb1_dram_odt,
mcb1_dram_reset_n => mcb1_dram_reset_n,
mcb1_dram_cke => mcb1_dram_cke,
mcb1_dram_dm => mcb1_dram_dm,
mcb1_dram_udqs => mcb1_dram_udqs,
mcb1_dram_udqs_n => mcb1_dram_udqs_n,
mcb1_rzq => mcb1_rzq,
mcb1_zio => mcb1_zio,
mcb1_dram_udm => mcb1_dram_udm,
c1_sys_clk_p => mcb1_c1_sys_clk_p,
c1_sys_clk_n => mcb1_c1_sys_clk_n,
c1_sys_rst_i => mcb1_c1_sys_rst_i,
mcb1_dram_dqs => mcb1_dram_dqs,
mcb1_dram_dqs_n => mcb1_dram_dqs_n,
mcb1_dram_ck => mcb1_dram_ck,
mcb1_dram_ck_n => mcb1_dram_ck_n,
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_reset_n => mcb3_dram_reset_n,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_udqs_n => mcb3_dram_udqs_n,
mcb3_rzq => mcb3_rzq,
mcb3_zio => mcb3_zio,
mcb3_dram_udm => mcb3_dram_udm,
c3_sys_clk_p => mcb3_c3_sys_clk_p,
c3_sys_clk_n => mcb3_c3_sys_clk_n,
c3_sys_rst_i => mcb3_c3_sys_rst_i,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n);
pcie_inst: entity work.xilinx_pcie_1_1_ep_s6
generic map (FAST_TRAIN => FALSE)
port map (
pci_exp_txp => pcie_txp,
pci_exp_txn => pcie_txn,
pci_exp_rxp => pcie_rxp,
pci_exp_rxn => pcie_rxn,
sys_clk_p => pcie_sys_clk_p,
sys_clk_n => pcie_sys_clk_n,
sys_reset_n => pcie_sys_reset_n,
led_0 => led(0),
led_1 => led(1),
led_2 => led(2));
end Behavioral;
| gpl-3.0 | e3ef5d0955de196c219e6a6afadade24 | 0.498074 | 3.308449 | false | false | false | false |
adelapie/noekeon_loop | noekeon_loop.vhd | 1 | 8,237 |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- This is loop unrolling (for K = 4) implementation of the NOEKEON block
-- cipher relying on the direct mode of the cipher. This means that
-- key schedule is not performed.
entity noekeon_loop is
port(clk : in std_logic;
rst : in std_logic;
enc : in std_logic; -- (enc, 0) / (dec, 1)
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end noekeon_loop;
architecture Behavioral of noekeon_loop is
component round_f is
port(enc : in std_logic;
rc_in : in std_logic_vector(31 downto 0);
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
component rc_shr is
port(clk : in std_logic;
rst : in std_logic;
rc_in : in std_logic_vector(71 downto 0);
rc_out : out std_logic_vector(7 downto 0));
end component;
component output_trans is
port(clk : in std_logic;
enc : in std_logic; -- (enc, 0) / (dec, 1)
rc_in : in std_logic_vector(31 downto 0);
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
component theta is
port(a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
signal rc_s : std_logic_vector(7 downto 0);
signal rc_ext_s : std_logic_vector(31 downto 0);
signal rc_2_s : std_logic_vector(7 downto 0);
signal rc_2_ext_s : std_logic_vector(31 downto 0);
signal a_0_in_s : std_logic_vector(31 downto 0);
signal a_1_in_s : std_logic_vector(31 downto 0);
signal a_2_in_s : std_logic_vector(31 downto 0);
signal a_3_in_s : std_logic_vector(31 downto 0);
signal out_t_a_0_in_s : std_logic_vector(31 downto 0);
signal out_t_a_1_in_s : std_logic_vector(31 downto 0);
signal out_t_a_2_in_s : std_logic_vector(31 downto 0);
signal out_t_a_3_in_s : std_logic_vector(31 downto 0);
signal a_0_out_s : std_logic_vector(31 downto 0);
signal a_1_out_s : std_logic_vector(31 downto 0);
signal a_2_out_s : std_logic_vector(31 downto 0);
signal a_3_out_s : std_logic_vector(31 downto 0);
signal stage_0_a_0_out_s : std_logic_vector(31 downto 0);
signal stage_0_a_1_out_s : std_logic_vector(31 downto 0);
signal stage_0_a_2_out_s : std_logic_vector(31 downto 0);
signal stage_0_a_3_out_s : std_logic_vector(31 downto 0);
signal k_0_d_s : std_logic_vector(31 downto 0);
signal k_1_d_s : std_logic_vector(31 downto 0);
signal k_2_d_s : std_logic_vector(31 downto 0);
signal k_3_d_s : std_logic_vector(31 downto 0);
signal k_0_mux_s : std_logic_vector(31 downto 0);
signal k_1_mux_s : std_logic_vector(31 downto 0);
signal k_2_mux_s : std_logic_vector(31 downto 0);
signal k_3_mux_s : std_logic_vector(31 downto 0);
signal init_val_shr_0 : std_logic_vector(71 downto 0);
signal init_val_shr_1 : std_logic_vector(71 downto 0);
begin
init_val_shr_0 <= X"8036d84d2fbcc635d4";
init_val_shr_1 <= X"1b6cab9a5e63976ad4";
RC_SHR_0 : rc_shr port map (clk, rst, init_val_shr_0, rc_s);
RC_SHR_1 : rc_shr port map (clk, rst, init_val_shr_1, rc_2_s);
rc_ext_s <= X"000000" & rc_s;
rc_2_ext_s <= X"000000" & rc_2_s;
ROUND_F_0 : round_f port map (enc,
rc_ext_s,
a_0_in_s,
a_1_in_s,
a_2_in_s,
a_3_in_s,
k_0_mux_s,
k_1_mux_s,
k_2_mux_s,
k_3_mux_s,
stage_0_a_0_out_s,
stage_0_a_1_out_s,
stage_0_a_2_out_s,
stage_0_a_3_out_s);
ROUND_F_1 : round_f port map (enc,
rc_2_ext_s,
stage_0_a_0_out_s,
stage_0_a_1_out_s,
stage_0_a_2_out_s,
stage_0_a_3_out_s,
k_0_mux_s,
k_1_mux_s,
k_2_mux_s,
k_3_mux_s,
a_0_out_s,
a_1_out_s,
a_2_out_s,
a_3_out_s);
pr_noe: process(clk, rst, enc)
begin
if rising_edge(clk) then
if rst = '1' then
a_0_in_s <= a_0_in;
a_1_in_s <= a_1_in;
a_2_in_s <= a_2_in;
a_3_in_s <= a_3_in;
else
a_0_in_s <= a_0_out_s;
a_1_in_s <= a_1_out_s;
a_2_in_s <= a_2_out_s;
a_3_in_s <= a_3_out_s;
end if;
end if;
end process;
-- Key decryption as k' = theta(0, k)
-- This is the key required for decryption
-- in NOEKEON
THETA_DECRYPT_0 : theta port map (
k_0_in,
k_1_in,
k_2_in,
k_3_in,
(others => '0'),
(others => '0'),
(others => '0'),
(others => '0'),
k_0_d_s,
k_1_d_s,
k_2_d_s,
k_3_d_s);
-- These multiplexers select the key that is used
-- in each mode i.e. during decryption the key generated
-- as k' = theta(0, k) (THETA_DECRYPT_0) is utilized.
k_0_mux_s <= k_0_in when enc = '0' else k_0_d_s;
k_1_mux_s <= k_1_in when enc = '0' else k_1_d_s;
k_2_mux_s <= k_2_in when enc = '0' else k_2_d_s;
k_3_mux_s <= k_3_in when enc = '0' else k_3_d_s;
out_trans_pr: process(clk, rst, a_0_out_s, a_1_out_s, a_2_out_s, a_3_out_s)
begin
if rising_edge(clk) then
out_t_a_0_in_s <= a_0_out_s;
out_t_a_1_in_s <= a_1_out_s;
out_t_a_2_in_s <= a_2_out_s;
out_t_a_3_in_s <= a_3_out_s;
end if;
end process;
-- This component performs the last operation
-- with theta.
OUT_TRANS_0 : output_trans port map (clk, enc, rc_ext_s,
out_t_a_0_in_s,
out_t_a_1_in_s,
out_t_a_2_in_s,
out_t_a_3_in_s,
k_0_mux_s,
k_1_mux_s,
k_2_mux_s,
k_3_mux_s,
a_0_out,
a_1_out,
a_2_out,
a_3_out);
end Behavioral;
| gpl-3.0 | 173be3e5a115c9527296897cd030b0a7 | 0.595484 | 2.471347 | false | false | false | false |
masaruohashi/tic-tac-toe | logica_jogo/verifica_fim.vhd | 1 | 2,470 | -- VHDL de um verificador de fim de jogo para o jogo da velha
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity verifica_fim is
port(
jogador_atual: in std_logic; -- jogador atual de acordo com a memoria do tabuleiro
jogadas_realizadas: in std_logic_vector(8 downto 0); -- vetor com as jogadas(1 ocupado, 0 aberto)
jogador_responsavel: in std_logic_vector(8 downto 0); -- vetor com o jogador(1 jogador 1, 0 jogador 0)
fim_jogo: out std_logic; -- indica o fim do jogo
jogador_vencedor : out std_logic; -- indica o jogador vencedor
empate : out std_logic -- indica se houve empate
);
end verifica_fim;
architecture exemplo of verifica_fim is
signal sinal_fim: std_logic;
signal sinal_jogadas_jogador: std_logic_vector(8 downto 0);
signal sinal_jogador_vencedor, sinal_empate: std_logic;
begin
process (jogador_atual)
begin
if jogador_atual='1' then
sinal_jogadas_jogador <= jogadas_realizadas and jogador_responsavel;
else
sinal_jogadas_jogador <= jogadas_realizadas and (not jogador_responsavel);
end if;
sinal_fim <= ((sinal_jogadas_jogador(0) and sinal_jogadas_jogador(1) and sinal_jogadas_jogador(2)) or
(sinal_jogadas_jogador(3) and sinal_jogadas_jogador(4) and sinal_jogadas_jogador(5)) or
(sinal_jogadas_jogador(6) and sinal_jogadas_jogador(7) and sinal_jogadas_jogador(8)) or
(sinal_jogadas_jogador(0) and sinal_jogadas_jogador(3) and sinal_jogadas_jogador(6)) or
(sinal_jogadas_jogador(1) and sinal_jogadas_jogador(4) and sinal_jogadas_jogador(7)) or
(sinal_jogadas_jogador(2) and sinal_jogadas_jogador(5) and sinal_jogadas_jogador(8)) or
(sinal_jogadas_jogador(0) and sinal_jogadas_jogador(4) and sinal_jogadas_jogador(8)) or
(sinal_jogadas_jogador(6) and sinal_jogadas_jogador(4) and sinal_jogadas_jogador(2)));
fim_jogo <= sinal_fim;
end process;
process (sinal_fim, jogadas_realizadas)
begin
if sinal_fim = '1' then
sinal_jogador_vencedor <= jogador_atual;
elsif jogadas_realizadas="111111111" then
sinal_empate <= '1';
end if;
jogador_vencedor <= sinal_jogador_vencedor;
empate <= sinal_empate;
end process;
end exemplo;
| mit | 600d257d1a1c307d354f28f71c5bfd98 | 0.637652 | 3.29773 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/pcie_core/example_design/PIO_TO_CTRL.vhd | 1 | 3,978 | -------------------------------------------------------------------------------
--
-- (c) Copyright 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : PIO_TO_CTRL.vhd
-- Description: Turn-off Control Unit.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity PIO_TO_CTRL is
port (
clk : in std_logic;
rst_n : in std_logic;
req_compl_i : in std_logic;
compl_done_i : in std_logic;
cfg_to_turnoff_n : in std_logic;
cfg_turnoff_ok_n : out std_logic
);
end PIO_TO_CTRL;
architecture rtl of PIO_TO_CTRL is
constant TCQ : time := 1 ns;
signal trn_pending : std_logic;
begin
--
-- Check if completion is pending
--
process begin
wait until rising_edge(clk);
if (rst_n = '0') then
trn_pending <= '0' after TCQ;
else
if ((trn_pending = '0') and (req_compl_i = '1')) then
trn_pending <= '1' after TCQ;
elsif (compl_done_i = '1') then
trn_pending <= '0' after TCQ;
end if;
end if;
end process;
--
-- Turn-off OK if requested and no transaction is pending
--
process begin
wait until rising_edge(clk);
if (rst_n = '0') then
cfg_turnoff_ok_n <= '1' after TCQ;
else
if ((cfg_to_turnoff_n = '0') and (trn_pending = '0')) then
cfg_turnoff_ok_n <= '0' after TCQ;
else
cfg_turnoff_ok_n <= '1' after TCQ;
end if;
end if;
end process;
end rtl;
| gpl-3.0 | 6066e2f02e7c73a810e240dfb6c55ade | 0.624434 | 4.010081 | false | false | false | false |
srohrer32/beamformer | hdl/mem_access.vhd | 1 | 2,662 | -----------------------------------------------------------------------------------
-- Created by Sam Rohrer --
-- Beamforms in the nearfield based on a generic for distance --
-- Accesses memory for test data --
-- Uses cellular RAM --
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity mem_access is
port(
o_datain_r : out std_logic_vector (7 downto 0); -- 8 bit from memory
o_datain_l : out std_logic_vector (7 downto 0); -- 8 bit from memory
o_addressbus : out std_logic_vector (26 downto 1);
i_databus : in std_logic_vector (15 downto 0);
i_sampleclock : in std_logic;
i_clock : in std_logic;
i_reset : in std_logic
);
end mem_access;
architecture Behavioral of mem_access is
signal clockpulses : integer ;
signal counter : std_logic_vector (24 downto 0);
signal channel_select : std_logic;
begin
--*******************************************************--
data_access: process (i_sampleclock, i_reset, clockpulses)
begin
if (i_reset = '1') then
channel_select <= '0';
o_addressbus <= (others => '0');
o_datain_r <= X"00";
o_datain_l <= X"00";
counter <= (others => '0');
elsif (clockpulses = 0) then
channel_select <= '0';
o_addressbus <= channel_select & counter;
elsif (clockpulses = 75) then
o_datain_r <= i_databus (7 downto 0);
elsif (clockpulses = 100) then
channel_select <= '1';
o_addressbus <= channel_select & counter;
elsif (clockpulses = 175) then
channel_select <= '0';
o_addressbus <= channel_select & counter;
elsif (clockpulses = 275) then
o_datain_l <= i_databus (7 downto 0);
elsif (rising_edge(i_sampleclock)) then
counter <= counter + '1';
elsif (counter = "1111111111111111111111111") then
counter <= (others => '0');
end if;
end process;
--*******************************************************--
clkpulses_counter: process (i_clock, i_reset, i_sampleclock)
begin
if (i_reset = '1') then
clockpulses <= 0;
elsif (rising_edge(i_clock)) then
clockpulses <= clockpulses + 1;
end if;
if (rising_edge(i_sampleclock)) then
clockpulses <= 0;
end if;
end process;
--*******************************************************--
end Behavioral; | apache-2.0 | 0c90266b8957faf34a1ed9454fe53695 | 0.503757 | 3.712692 | false | false | false | false |
masaruohashi/tic-tac-toe | uart/transmissao_serial.vhd | 1 | 2,013 | -- transmissao_serial
-- VHDL do circuito de tranmissao serial completo
library ieee;
use ieee.std_logic_1164.all;
entity transmissao_serial is
port(
clock: in std_logic;
reset: in std_logic;
transmite_dado: in std_logic;
dados_trans: in std_logic_vector(6 downto 0);
saida: out std_logic;
transmissao_andamento: out std_logic;
fim_transmissao: out std_logic;
depuracao_tick: out std_logic
);
end transmissao_serial;
architecture estrutural of transmissao_serial is
component unidade_controle_interface_transmissao is
port(
clock: in std_logic;
reset: in std_logic;
transmite_dado: in std_logic;
pronto: in std_logic;
transmissao_andamento: out std_logic
);
end component;
component circuito_transmissao is
port(
dados_ascii: in std_logic_vector(6 downto 0);
tick_rx: in std_logic;
partida: in std_logic;
reset: in std_logic;
clock: in std_logic;
dado_serial: out std_logic;
pronto: out std_logic
);
end component;
component gerador_tick is
generic(
M: integer := 19200
);
port(
clock, reset: in std_logic;
tick: out std_logic
);
end component;
signal sinal_pronto: std_logic;
signal sinal_transmissao_andamento: std_logic;
signal sinal_tick: std_logic;
begin
uc_interface_transmissao: unidade_controle_interface_transmissao port map (clock, reset, transmite_dado, sinal_pronto, sinal_transmissao_andamento);
transmissao: circuito_transmissao port map(dados_trans, sinal_tick, sinal_transmissao_andamento, reset, clock, saida, sinal_pronto);
gera_tick: gerador_tick generic map (M => 454545) port map(clock, reset, sinal_tick);
--para teste usar a linha abaixo de comentar a de cima
--gera_tick: gerador_tick generic map (M => 16) port map(clock, reset, sinal_tick);
depuracao_tick <= sinal_tick;
transmissao_andamento <= sinal_transmissao_andamento;
fim_transmissao <= sinal_pronto;
end estrutural;
| mit | 47c51d8214660c6494c148c377bcbb39 | 0.690512 | 3.680073 | false | false | false | false |
timofonic/PHDL | misc/projects/Old.v1.0-projects/FMC_DAC/fmc_dac_fpga/top.vhd | 1 | 2,858 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity top is Port (
db1_p : out STD_LOGIC_VECTOR (13 downto 0);
db1_n : out STD_LOGIC_VECTOR (13 downto 0);
db0_p : out STD_LOGIC_VECTOR (13 downto 0);
db0_n : out STD_LOGIC_VECTOR (13 downto 0);
sync_out_p : out STD_LOGIC;
sync_out_n : out STD_LOGIC;
sync_in_p : in STD_LOGIC;
sync_in_n : in STD_LOGIC;
dco_p : out STD_LOGIC;
dco_n : out STD_LOGIC;
dci_p : in STD_LOGIC;
dci_n : in STD_LOGIC;
spi_sdi : in STD_LOGIC;
spi_sdo : out STD_LOGIC;
spi_cs : out STD_LOGIC;
spi_sclk : out STD_LOGIC;
reset : out STD_LOGIC);
end top;
architecture Behavioral of top is
signal dci, dco, sync_in, sync_out, spi_sdi_reg : std_logic;
signal sync_vec : std_logic_vector( 1 downto 0);
signal db0, db1 : std_logic_vector(13 downto 0);
signal count : std_logic_vector(63 downto 0);
begin
IBUFGDS_dci: IBUFGDS port map(O=>dci, I=>dci_p, IB=>dci_n);
IBUFDS_sync_in : IBUFDS port map(O=>sync_in, I=>sync_in_p, IB=>sync_in_n);
IDDR_sync_in : IDDR generic map(DDR_CLK_EDGE=>"SAME_EDGE") port map(Q1=>sync_vec(0), Q2=>sync_vec(1), C=>dci, CE=>'1', D=>sync_in, R=>'0', S=>'0');
ODDR_sync_out : ODDR generic map(DDR_CLK_EDGE=>"SAME_EDGE") port map(Q=>sync_out, C=>dci, CE=>'1', D1=>sync_vec(0), D2=>sync_vec(1), R=>'0', S=>'0');
OBUFDS_sync_out : OBUFDS port map(O=>sync_out_p, OB=>sync_out_n, I=>sync_out);
ODDR_dco : ODDR generic map(DDR_CLK_EDGE=>"SAME_EDGE") port map(Q=>dco, C=>dci, CE=>'1', D1=>'0', D2=>'1', R=>'0', S=>'0');
OBUFDS_dco : OBUFDS port map(O=>dco_p, OB=>dco_n, I=>dco);
dbx_gen: for i in db0_p'range generate begin
ODDR_db0 : ODDR generic map(DDR_CLK_EDGE=>"SAME_EDGE") port map(Q=>db0(i), C=>dci, CE=>'1', D1=>count(i+0), D2=>count(i+14), R=>'0', S=>'0');
ODDR_db1 : ODDR generic map(DDR_CLK_EDGE=>"SAME_EDGE") port map(Q=>db1(i), C=>dci, CE=>'1', D1=>count(i+28), D2=>count(i+42), R=>'0', S=>'0');
OBUFDS_db0 : OBUFDS port map(O=>db0_p(i), OB=>db0_n(i), I=>db0(i));
OBUFDS_db1 : OBUFDS port map(O=>db1_p(i), OB=>db1_n(i), I=>db1(i));
end generate;
count_proc:process
begin
wait until rising_edge(dci);
count <= std_logic_vector(unsigned(count)+1);
end process;
spi_regs_proc:process
begin
wait until rising_edge(dci);
spi_sdi_reg <= spi_sdi;
spi_sdo <= spi_sdi_reg;
spi_cs <= count(56);
reset <= count(57);
spi_sclk <= count(58);
end process;
end Behavioral;
| gpl-3.0 | 8ae2ddcc2e699b374b74e067bf7e3510 | 0.543737 | 2.878147 | false | false | false | false |
JavierRizzoA/Sacagawea | sources/Cntrl_cont.vhd | 1 | 1,361 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:31:06 06/05/2016
-- Design Name:
-- Module Name: Cntrl_cont - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Cntrl_cont is
Port ( clk : in STD_LOGIC;
reset : in std_logic;
sal_cont : out STD_LOGIC_VECTOR (2 downto 0)
);
end Cntrl_cont;
architecture Behavioral of Cntrl_cont is
signal temp : std_logic_vector(2 downto 0):= "000";
begin
process(clk)
begin
if(clk'event and clk = '1')then
if(reset = '1') then
temp <= "000";
else
temp <= temp + "001";
end if;
end if;
end process;
sal_cont <= temp;
end Behavioral;
| mit | 6475de1df20c92cb722fb1bed4f1ca46 | 0.555474 | 3.61008 | false | false | false | false |
JavierRizzoA/Sacagawea | sources/LEDS.vhd | 1 | 1,351 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:45:18 06/05/2016
-- Design Name:
-- Module Name: LEDS - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity LEDS is
Port (
clk : in std_logic;
leds_enable : in std_logic;
leds_input : in STD_LOGIC_VECTOR (7 downto 0);
leds_output : out STD_LOGIC_VECTOR (7 downto 0)
);
end LEDS;
architecture Behavioral of LEDS is
begin
process(clk)
begin
if (clk'event and clk='1') then
if (leds_enable = '1') then
leds_output <= leds_input;
else
--temp <= leds_input;
leds_output <= "ZZZZZZZZ";
end if;
end if;
end process;
end Behavioral;
| mit | 18a3b2396a9a5c57fe597ccb3d1e64eb | 0.549223 | 3.784314 | false | false | false | false |
masaruohashi/tic-tac-toe | logica_jogo/mapeador_jogada.vhd | 1 | 885 | -- VHDL de um mapeador de jogadas do usuario
library ieee;
use ieee.std_logic_1164.all;
entity mapeador_jogada is
port(
caractere: in std_logic_vector(6 downto 0);
jogada: out std_logic_vector(3 downto 0)
);
end mapeador_jogada;
architecture comportamental of mapeador_jogada is
begin
process (caractere)
begin
case caractere is
when "0110111" =>
jogada <= "0110";
when "0111000" =>
jogada <= "0111";
when "0111001" =>
jogada <= "1000";
when "0110100" =>
jogada <= "0011";
when "0110101" =>
jogada <= "0100";
when "0110110" =>
jogada <= "0101";
when "0110001" =>
jogada <= "0000";
when "0110010" =>
jogada <= "0001";
when "0110011" =>
jogada <= "0010";
when others =>
null;
end case;
end process;
end comportamental;
| mit | 9969cc4376f678a5616b4abb36e56b4e | 0.560452 | 3.582996 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/pcie_core/simulation/dsport/xilinx_pcie_2_0_rport_v6.vhd | 1 | 34,698 | -------------------------------------------------------------------------------
--
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : xilinx_pcie_2_0_rport_v6.vhd
-- Description: PCI Express Root Port example FPGA design
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
entity xilinx_pcie_2_0_rport_v6 is
generic (
REF_CLK_FREQ : integer := 0; -- 0 - 100MHz, 1 - 125 MHz, 2 - 250 MHz
ALLOW_X8_GEN2 : boolean := FALSE;
PL_FAST_TRAIN : boolean := FALSE;
LINK_CAP_MAX_LINK_SPEED : bit_vector := X"1";
DEVICE_ID : bit_vector := X"0007";
LINK_CAP_MAX_LINK_WIDTH : bit_vector := X"08";
LTSSM_MAX_LINK_WIDTH : bit_vector := X"08";
LINK_CAP_MAX_LINK_WIDTH_int : integer := 8;
LINK_CTRL2_TARGET_LINK_SPEED : bit_vector := X"2";
DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer := 2;
USER_CLK_FREQ : integer := 3;
VC0_TX_LASTPACKET : integer := 31;
VC0_RX_RAM_LIMIT : bit_vector := X"03FF";
VC0_TOTAL_CREDITS_CD : integer := 154;
VC0_TOTAL_CREDITS_PD : integer := 154
);
port (
pci_exp_txp : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
pci_exp_txn : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
pci_exp_rxp : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
pci_exp_rxn : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
sys_clk : in std_logic;
sys_reset_n : in std_logic
);
end xilinx_pcie_2_0_rport_v6;
architecture rtl of xilinx_pcie_2_0_rport_v6 is
component pcie_2_0_rport_v6
generic (
REF_CLK_FREQ : integer;
ALLOW_X8_GEN2 : boolean;
PL_FAST_TRAIN : boolean;
LINK_CAP_MAX_LINK_SPEED : bit_vector;
DEVICE_ID : bit_vector;
LINK_CAP_MAX_LINK_WIDTH : bit_vector;
LINK_CAP_MAX_LINK_WIDTH_int : integer;
LINK_CTRL2_TARGET_LINK_SPEED : bit_vector;
LTSSM_MAX_LINK_WIDTH : bit_vector;
DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer;
USER_CLK_FREQ : integer;
VC0_TX_LASTPACKET : integer;
VC0_RX_RAM_LIMIT : bit_vector;
VC0_TOTAL_CREDITS_CD : integer;
VC0_TOTAL_CREDITS_PD : integer
);
port (
pci_exp_txp : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
pci_exp_txn : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
pci_exp_rxp : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
pci_exp_rxn : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
trn_clk : out std_logic;
trn_reset_n : out std_logic;
trn_lnk_up_n : out std_logic;
trn_tbuf_av : out std_logic_vector(5 downto 0);
trn_tcfg_req_n : out std_logic;
trn_terr_drop_n : out std_logic;
trn_tdst_rdy_n : out std_logic;
trn_td : in std_logic_vector(63 downto 0);
trn_trem_n : in std_logic;
trn_tsof_n : in std_logic;
trn_teof_n : in std_logic;
trn_tsrc_rdy_n : in std_logic;
trn_tsrc_dsc_n : in std_logic;
trn_terrfwd_n : in std_logic;
trn_tcfg_gnt_n : in std_logic;
trn_tstr_n : in std_logic;
trn_rd : out std_logic_vector(63 downto 0);
trn_rrem_n : out std_logic;
trn_rsof_n : out std_logic;
trn_reof_n : out std_logic;
trn_rsrc_rdy_n : out std_logic;
trn_rsrc_dsc_n : out std_logic;
trn_rerrfwd_n : out std_logic;
trn_rbar_hit_n : out std_logic_vector(6 downto 0);
trn_rdst_rdy_n : in std_logic;
trn_rnp_ok_n : in std_logic;
trn_recrc_err_n : out std_logic;
trn_fc_cpld : out std_logic_vector(11 downto 0);
trn_fc_cplh : out std_logic_vector(7 downto 0);
trn_fc_npd : out std_logic_vector(11 downto 0);
trn_fc_nph : out std_logic_vector(7 downto 0);
trn_fc_pd : out std_logic_vector(11 downto 0);
trn_fc_ph : out std_logic_vector(7 downto 0);
trn_fc_sel : in std_logic_vector(2 downto 0);
cfg_do : out std_logic_vector(31 downto 0);
cfg_rd_wr_done_n : out std_logic;
cfg_di : in std_logic_vector(31 downto 0);
cfg_byte_en_n : in std_logic_vector(3 downto 0);
cfg_dwaddr : in std_logic_vector(9 downto 0);
cfg_wr_en_n : in std_logic;
cfg_wr_rw1c_as_rw_n : in std_logic;
cfg_rd_en_n : in std_logic;
cfg_err_cor_n : in std_logic;
cfg_err_ur_n : in std_logic;
cfg_err_ecrc_n : in std_logic;
cfg_err_cpl_timeout_n : in std_logic;
cfg_err_cpl_abort_n : in std_logic;
cfg_err_cpl_unexpect_n : in std_logic;
cfg_err_posted_n : in std_logic;
cfg_err_locked_n : in std_logic;
cfg_err_tlp_cpl_header : in std_logic_vector(47 downto 0);
cfg_err_cpl_rdy_n : out std_logic;
cfg_interrupt_n : in std_logic;
cfg_interrupt_rdy_n : out std_logic;
cfg_interrupt_assert_n : in std_logic;
cfg_interrupt_di : in std_logic_vector(7 downto 0);
cfg_interrupt_do : out std_logic_vector(7 downto 0);
cfg_interrupt_mmenable : out std_logic_vector(2 downto 0);
cfg_interrupt_msienable : out std_logic;
cfg_interrupt_msixenable : out std_logic;
cfg_interrupt_msixfm : out std_logic;
cfg_trn_pending_n : in std_logic;
cfg_pm_send_pme_to_n : in std_logic;
cfg_status : out std_logic_vector(15 downto 0);
cfg_command : out std_logic_vector(15 downto 0);
cfg_dstatus : out std_logic_vector(15 downto 0);
cfg_dcommand : out std_logic_vector(15 downto 0);
cfg_lstatus : out std_logic_vector(15 downto 0);
cfg_lcommand : out std_logic_vector(15 downto 0);
cfg_dcommand2 : out std_logic_vector(15 downto 0);
cfg_pcie_link_state_n : out std_logic_vector(2 downto 0);
cfg_dsn : in std_logic_vector(63 downto 0);
cfg_pmcsr_pme_en : out std_logic;
cfg_pmcsr_pme_status : out std_logic;
cfg_pmcsr_powerstate : out std_logic_vector(1 downto 0);
cfg_msg_received : out std_logic;
cfg_msg_data : out std_logic_vector(15 downto 0);
cfg_msg_received_err_cor : out std_logic;
cfg_msg_received_err_non_fatal : out std_logic;
cfg_msg_received_err_fatal : out std_logic;
cfg_msg_received_pme_to_ack : out std_logic;
cfg_msg_received_assert_inta : out std_logic;
cfg_msg_received_assert_intb : out std_logic;
cfg_msg_received_assert_intc : out std_logic;
cfg_msg_received_assert_intd : out std_logic;
cfg_msg_received_deassert_inta : out std_logic;
cfg_msg_received_deassert_intb : out std_logic;
cfg_msg_received_deassert_intc : out std_logic;
cfg_msg_received_deassert_intd : out std_logic;
cfg_ds_bus_number : in std_logic_vector(7 downto 0);
cfg_ds_device_number : in std_logic_vector(4 downto 0);
pl_initial_link_width : out std_logic_vector(2 downto 0);
pl_lane_reversal_mode : out std_logic_vector(1 downto 0);
pl_link_gen2_capable : out std_logic;
pl_link_partner_gen2_supported : out std_logic;
pl_link_upcfg_capable : out std_logic;
pl_ltssm_state : out std_logic_vector(5 downto 0);
pl_sel_link_rate : out std_logic;
pl_sel_link_width : out std_logic_vector(1 downto 0);
pl_directed_link_auton : in std_logic;
pl_directed_link_change : in std_logic_vector(1 downto 0);
pl_directed_link_speed : in std_logic;
pl_directed_link_width : in std_logic_vector(1 downto 0);
pl_upstream_prefer_deemph : in std_logic;
pl_transmit_hot_rst : in std_logic;
pcie_drp_clk : in std_logic;
pcie_drp_den : in std_logic;
pcie_drp_dwe : in std_logic;
pcie_drp_daddr : in std_logic_vector(8 downto 0);
pcie_drp_di : in std_logic_vector(15 downto 0);
pcie_drp_do : out std_logic_vector(15 downto 0);
pcie_drp_drdy : out std_logic;
sys_clk : in std_logic;
sys_reset_n : in std_logic);
end component;
component pci_exp_usrapp_cfg
port (
cfg_do : in std_logic_vector(31 downto 0);
cfg_di : out std_logic_vector(31 downto 0);
cfg_byte_en_n : out std_logic_vector(3 downto 0);
cfg_dwaddr : out std_logic_vector(9 downto 0);
cfg_wr_en_n : out std_logic;
cfg_rd_en_n : out std_logic;
cfg_rd_wr_done_n : in std_logic;
cfg_err_cor_n : out std_logic;
cfg_err_ur_n : out std_logic;
cfg_err_ecrc_n : out std_logic;
cfg_err_cpl_timeout_n : out std_logic;
cfg_err_cpl_abort_n : out std_logic;
cfg_err_cpl_unexpect_n : out std_logic;
cfg_err_posted_n : out std_logic;
cfg_err_tlp_cpl_header : out std_logic_vector(47 downto 0);
cfg_interrupt_n : out std_logic;
cfg_interrupt_rdy_n : in std_logic;
cfg_turnoff_ok_n : out std_logic;
cfg_to_turnoff_n : in std_logic;
cfg_pm_wake_n : out std_logic;
cfg_bus_number : in std_logic_vector((8 -1) downto 0);
cfg_device_number : in std_logic_vector((5 - 1) downto 0);
cfg_function_number : in std_logic_vector((3 - 1) downto 0);
cfg_status : in std_logic_vector((16 - 1) downto 0);
cfg_command : in std_logic_vector((16 - 1) downto 0);
cfg_dstatus : in std_logic_vector((16 - 1) downto 0);
cfg_dcommand : in std_logic_vector((16 - 1) downto 0);
cfg_lstatus : in std_logic_vector((16 - 1) downto 0);
cfg_lcommand : in std_logic_vector((16 - 1) downto 0);
cfg_pcie_link_state_n : in std_logic_vector((3 - 1) downto 0);
cfg_trn_pending_n : out std_logic;
trn_clk : in std_logic;
trn_reset_n : in std_logic);
end component;
component pci_exp_usrapp_rx
port (
trn_rdst_rdy_n : out std_logic;
trn_rnp_ok_n : out std_logic;
trn_rd : in std_logic_vector (63 downto 0);
trn_rrem_n : in std_logic_vector (7 downto 0);
trn_rsof_n : in std_logic;
trn_reof_n : in std_logic;
trn_rsrc_rdy_n : in std_logic;
trn_rsrc_dsc_n : in std_logic;
trn_rerrfwd_n : in std_logic;
trn_rbar_hit_n : in std_logic_vector (6 downto 0);
trn_clk : in std_logic;
trn_reset_n : in std_logic;
trn_lnk_up_n : in std_logic;
rx_tx_read_data : out std_logic_vector(31 downto 0);
rx_tx_read_data_valid : out std_logic;
tx_rx_read_data_valid : in std_logic);
end component;
component pci_exp_usrapp_tx
port (
trn_td : out std_logic_vector (63 downto 0);
trn_trem_n : out std_logic_vector (7 downto 0);
trn_tsof_n : out std_logic;
trn_teof_n : out std_logic;
trn_terrfwd_n : out std_logic;
trn_tsrc_rdy_n : out std_logic;
trn_tsrc_dsc_n : out std_logic;
trn_clk : in std_logic;
trn_reset_n : in std_logic;
trn_lnk_up_n : in std_logic;
trn_tdst_rdy_n : in std_logic;
trn_tdst_dsc_n : in std_logic;
trn_tbuf_av : in std_logic_vector (5 downto 0);
rx_tx_read_data : in std_logic_vector(31 downto 0);
rx_tx_read_data_valid : in std_logic;
tx_rx_read_data_valid : out std_logic);
end component;
component pci_exp_usrapp_pl
generic (
LINK_CAP_MAX_LINK_SPEED : integer);
port (
pl_initial_link_width : in std_logic_vector(2 downto 0);
pl_lane_reversal_mode : in std_logic_vector(1 downto 0);
pl_link_gen2_capable : in std_logic;
pl_link_partner_gen2_supported : in std_logic;
pl_link_upcfg_capable : in std_logic;
pl_ltssm_state : in std_logic_vector(5 downto 0);
pl_received_hot_rst : in std_logic;
pl_sel_link_rate : in std_logic;
pl_sel_link_width : in std_logic_vector(1 downto 0);
pl_directed_link_auton : out std_logic;
pl_directed_link_change : out std_logic_vector(1 downto 0);
pl_directed_link_speed : out std_logic;
pl_directed_link_width : out std_logic_vector(1 downto 0);
pl_upstream_prefer_deemph : out std_logic;
speed_change_done_n : out std_logic;
trn_lnk_up_n : in std_logic;
trn_clk : in std_logic;
trn_reset_n : in std_logic);
end component;
FUNCTION to_integer (
val_in : bit_vector) RETURN integer IS
CONSTANT vctr : bit_vector(val_in'high-val_in'low DOWNTO 0) := val_in;
VARIABLE ret : integer := 0;
BEGIN
FOR index IN vctr'RANGE LOOP
IF (vctr(index) = '1') THEN
ret := ret + (2**index);
END IF;
END LOOP;
RETURN(ret);
END to_integer;
constant LINK_CAP_MAX_LINK_SPEED_int : integer := to_integer(LINK_CAP_MAX_LINK_SPEED);
signal rx_tx_read_data : std_logic_vector(31 downto 0);
signal rx_tx_read_data_valid : std_logic;
signal tx_rx_read_data_valid : std_logic;
-- Tx
signal trn_tbuf_av : std_logic_vector(5 downto 0);
signal trn_tdst_dsc_n : std_logic;
signal trn_tdst_rdy_n : std_logic;
signal trn_td : std_logic_vector(63 downto 0);
signal trn_trem_n : std_logic;
signal trn_trem_n_out : std_logic_vector(7 downto 0);
signal trn_tsof_n : std_logic;
signal trn_teof_n : std_logic;
signal trn_tsrc_rdy_n : std_logic;
signal trn_tsrc_dsc_n : std_logic;
signal trn_terrfwd_n : std_logic;
-- Rx
signal trn_rd : std_logic_vector(63 downto 0);
signal trn_rrem_n : std_logic;
signal trn_rrem_n_in : std_logic_vector(7 downto 0);
signal trn_rsof_n : std_logic;
signal trn_reof_n : std_logic;
signal trn_rsrc_rdy_n : std_logic;
signal trn_rsrc_dsc_n : std_logic;
signal trn_rerrfwd_n : std_logic;
signal trn_rbar_hit_n : std_logic_vector(6 downto 0);
signal trn_rdst_rdy_n : std_logic;
signal trn_rnp_ok_n : std_logic;
signal trn_clk : std_logic;
signal trn_reset_n : std_logic;
signal trn_lnk_up_n : std_logic;
---------------------------------------------------------
-- 3. Configuration (CFG) Interface
---------------------------------------------------------
signal cfg_do : std_logic_vector(31 downto 0);
signal cfg_rd_wr_done_n : std_logic;
signal cfg_di : std_logic_vector(31 downto 0);
signal cfg_byte_en_n : std_logic_vector(3 downto 0);
signal cfg_dwaddr : std_logic_vector(9 downto 0);
signal cfg_wr_en_n : std_logic;
signal cfg_rd_en_n : std_logic;
signal cfg_err_cor_n: std_logic;
signal cfg_err_ur_n : std_logic;
signal cfg_err_ecrc_n : std_logic;
signal cfg_err_cpl_timeout_n : std_logic;
signal cfg_err_cpl_abort_n : std_logic;
signal cfg_err_cpl_unexpect_n : std_logic;
signal cfg_err_posted_n : std_logic;
signal cfg_err_tlp_cpl_header : std_logic_vector(47 downto 0);
signal cfg_err_cpl_rdy_n : std_logic;
signal cfg_interrupt_n : std_logic;
signal cfg_interrupt_rdy_n : std_logic;
signal cfg_interrupt_mmenable : std_logic_vector(2 downto 0);
signal cfg_interrupt_msienable : std_logic;
signal cfg_interrupt_msixenable : std_logic;
signal cfg_interrupt_msixfm : std_logic;
signal cfg_trn_pending_n : std_logic;
signal cfg_status : std_logic_vector(15 downto 0);
signal cfg_command : std_logic_vector(15 downto 0);
signal cfg_dstatus : std_logic_vector(15 downto 0);
signal cfg_dcommand : std_logic_vector(15 downto 0);
signal cfg_lstatus : std_logic_vector(15 downto 0);
signal cfg_lcommand : std_logic_vector(15 downto 0);
signal cfg_pcie_link_state_n : std_logic_vector(2 downto 0);
signal cfg_msg_received : std_logic;
signal cfg_msg_data : std_logic_vector(15 downto 0);
signal cfg_msg_received_err_cor : std_logic;
signal cfg_msg_received_err_non_fatal : std_logic;
signal cfg_msg_received_err_fatal : std_logic;
signal cfg_msg_received_pme_to_ack : std_logic;
signal cfg_msg_received_assert_inta : std_logic;
signal cfg_msg_received_assert_intb : std_logic;
signal cfg_msg_received_assert_intc : std_logic;
signal cfg_msg_received_assert_intd : std_logic;
signal cfg_msg_received_deassert_inta : std_logic;
signal cfg_msg_received_deassert_intb : std_logic;
signal cfg_msg_received_deassert_intc : std_logic;
signal cfg_msg_received_deassert_intd : std_logic;
---------------------------------------------------------
-- 4. Physical Layer Control and Status (PL) Interface
---------------------------------------------------------
signal pl_initial_link_width : std_logic_vector(2 downto 0);
signal pl_lane_reversal_mode : std_logic_vector(1 downto 0);
signal pl_link_gen2_capable : std_logic;
signal pl_link_partner_gen2_supported : std_logic;
signal pl_link_upcfg_capable : std_logic;
signal pl_ltssm_state : std_logic_vector(5 downto 0);
signal pl_sel_link_rate : std_logic;
signal pl_sel_link_width : std_logic_vector(1 downto 0);
signal pl_directed_link_auton : std_logic;
signal pl_directed_link_change : std_logic_vector(1 downto 0);
signal pl_directed_link_speed : std_logic;
signal pl_directed_link_width : std_logic_vector(1 downto 0);
signal pl_upstream_prefer_deemph : std_logic;
-------------------------------------------------------
begin
trn_trem_n <= '1' when (trn_trem_n_out = X"0F") else
'0';
trn_rrem_n_in <= X"0F" when (trn_rrem_n = '1') else
X"00";
rport : pcie_2_0_rport_v6
generic map(
REF_CLK_FREQ => REF_CLK_FREQ,
ALLOW_X8_GEN2 => ALLOW_X8_GEN2,
PL_FAST_TRAIN => PL_FAST_TRAIN,
LINK_CAP_MAX_LINK_SPEED => LINK_CAP_MAX_LINK_SPEED,
DEVICE_ID => DEVICE_ID,
LINK_CAP_MAX_LINK_WIDTH => LINK_CAP_MAX_LINK_WIDTH,
LINK_CAP_MAX_LINK_WIDTH_int => LINK_CAP_MAX_LINK_WIDTH_int,
LINK_CTRL2_TARGET_LINK_SPEED => LINK_CTRL2_TARGET_LINK_SPEED,
LTSSM_MAX_LINK_WIDTH => LTSSM_MAX_LINK_WIDTH,
DEV_CAP_MAX_PAYLOAD_SUPPORTED => DEV_CAP_MAX_PAYLOAD_SUPPORTED,
USER_CLK_FREQ => USER_CLK_FREQ,
VC0_TX_LASTPACKET => VC0_TX_LASTPACKET,
VC0_RX_RAM_LIMIT => VC0_RX_RAM_LIMIT,
VC0_TOTAL_CREDITS_CD => VC0_TOTAL_CREDITS_CD,
VC0_TOTAL_CREDITS_PD => VC0_TOTAL_CREDITS_CD
)
port map(
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
trn_clk => trn_clk ,
trn_reset_n => trn_reset_n ,
trn_lnk_up_n => trn_lnk_up_n ,
trn_tbuf_av => trn_tbuf_av ,
trn_tcfg_req_n => open,
trn_terr_drop_n => trn_tdst_dsc_n ,
trn_tdst_rdy_n => trn_tdst_rdy_n ,
trn_td => trn_td ,
trn_trem_n => trn_trem_n,
trn_tsof_n => trn_tsof_n ,
trn_teof_n => trn_teof_n ,
trn_tsrc_rdy_n => trn_tsrc_rdy_n ,
trn_tsrc_dsc_n => trn_tsrc_dsc_n ,
trn_terrfwd_n => trn_terrfwd_n ,
trn_tcfg_gnt_n => '0' ,
trn_tstr_n => '1' ,
trn_rd => trn_rd ,
trn_rrem_n => trn_rrem_n ,
trn_rsof_n => trn_rsof_n ,
trn_reof_n => trn_reof_n ,
trn_rsrc_rdy_n => trn_rsrc_rdy_n ,
trn_rsrc_dsc_n => trn_rsrc_dsc_n ,
trn_rerrfwd_n => trn_rerrfwd_n ,
trn_rbar_hit_n => trn_rbar_hit_n ,
trn_rdst_rdy_n => trn_rdst_rdy_n ,
trn_rnp_ok_n => trn_rnp_ok_n ,
trn_recrc_err_n => open,
trn_fc_cpld => open,
trn_fc_cplh => open,
trn_fc_npd => open,
trn_fc_nph => open,
trn_fc_pd => open,
trn_fc_ph => open,
trn_fc_sel => "000" ,
cfg_do => cfg_do ,
cfg_rd_wr_done_n => cfg_rd_wr_done_n,
cfg_di => cfg_di ,
cfg_byte_en_n => cfg_byte_en_n ,
cfg_dwaddr => cfg_dwaddr ,
cfg_wr_en_n => cfg_wr_en_n ,
cfg_wr_rw1c_as_rw_n => '1',
cfg_rd_en_n => cfg_rd_en_n ,
cfg_err_cor_n => cfg_err_cor_n ,
cfg_err_ur_n => cfg_err_ur_n ,
cfg_err_ecrc_n => cfg_err_ecrc_n ,
cfg_err_cpl_timeout_n => cfg_err_cpl_timeout_n ,
cfg_err_cpl_abort_n => cfg_err_cpl_abort_n ,
cfg_err_cpl_unexpect_n => cfg_err_cpl_unexpect_n ,
cfg_err_posted_n => cfg_err_posted_n ,
cfg_err_locked_n => '1',
cfg_err_tlp_cpl_header => cfg_err_tlp_cpl_header ,
cfg_err_cpl_rdy_n => open,
cfg_interrupt_n => cfg_interrupt_n ,
cfg_interrupt_rdy_n => cfg_interrupt_rdy_n ,
cfg_interrupt_assert_n => '1' ,
cfg_interrupt_di => X"00" ,
cfg_interrupt_do => open,
cfg_interrupt_mmenable => open,
cfg_interrupt_msienable => open,
cfg_interrupt_msixenable => open,
cfg_interrupt_msixfm => open,
cfg_trn_pending_n => cfg_trn_pending_n ,
cfg_pm_send_pme_to_n => '1' ,
cfg_status => cfg_status ,
cfg_command => cfg_command ,
cfg_dstatus => cfg_dstatus ,
cfg_dcommand => cfg_dcommand ,
cfg_lstatus => cfg_lstatus ,
cfg_lcommand => cfg_lcommand ,
cfg_dcommand2 => open,
cfg_pcie_link_state_n => cfg_pcie_link_state_n ,
cfg_dsn => (others => '0') ,
cfg_pmcsr_pme_en => open,
cfg_pmcsr_pme_status => open,
cfg_pmcsr_powerstate => open,
cfg_msg_received => cfg_msg_received ,
cfg_msg_data => cfg_msg_data ,
cfg_msg_received_err_cor => cfg_msg_received_err_cor ,
cfg_msg_received_err_non_fatal => cfg_msg_received_err_non_fatal ,
cfg_msg_received_err_fatal => cfg_msg_received_err_fatal ,
cfg_msg_received_pme_to_ack => cfg_msg_received_pme_to_ack ,
cfg_msg_received_assert_inta => cfg_msg_received_assert_inta ,
cfg_msg_received_assert_intb => cfg_msg_received_assert_intb ,
cfg_msg_received_assert_intc => cfg_msg_received_assert_intc ,
cfg_msg_received_assert_intd => cfg_msg_received_assert_intd ,
cfg_msg_received_deassert_inta => cfg_msg_received_deassert_inta ,
cfg_msg_received_deassert_intb => cfg_msg_received_deassert_intb ,
cfg_msg_received_deassert_intc => cfg_msg_received_deassert_intc ,
cfg_msg_received_deassert_intd => cfg_msg_received_deassert_intd ,
cfg_ds_bus_number => X"00",
cfg_ds_device_number => "00000",
pl_initial_link_width => pl_initial_link_width ,
pl_lane_reversal_mode => pl_lane_reversal_mode ,
pl_link_gen2_capable => pl_link_gen2_capable ,
pl_link_partner_gen2_supported => pl_link_partner_gen2_supported ,
pl_link_upcfg_capable => pl_link_upcfg_capable ,
pl_ltssm_state => pl_ltssm_state ,
pl_sel_link_rate => pl_sel_link_rate ,
pl_sel_link_width => pl_sel_link_width ,
pl_directed_link_auton => pl_directed_link_auton ,
pl_directed_link_change => pl_directed_link_change ,
pl_directed_link_speed => pl_directed_link_speed ,
pl_directed_link_width => pl_directed_link_width ,
pl_upstream_prefer_deemph => pl_upstream_prefer_deemph ,
pl_transmit_hot_rst => '0',
pcie_drp_clk => '0',
pcie_drp_den => '0',
pcie_drp_dwe => '0',
pcie_drp_daddr => "000000000",
pcie_drp_di => X"0000",
pcie_drp_do => open,
pcie_drp_drdy => open,
sys_clk => sys_clk ,
sys_reset_n => sys_reset_n
);
CFG_APP : pci_exp_usrapp_cfg
port map (
cfg_do => cfg_do,
cfg_di => cfg_di,
cfg_byte_en_n => cfg_byte_en_n,
cfg_dwaddr => cfg_dwaddr,
cfg_wr_en_n => cfg_wr_en_n,
cfg_rd_en_n => cfg_rd_en_n,
cfg_rd_wr_done_n => cfg_rd_wr_done_n,
cfg_err_cor_n => cfg_err_cor_n,
cfg_err_ur_n => cfg_err_ur_n,
cfg_err_ecrc_n => cfg_err_ecrc_n,
cfg_err_cpl_timeout_n => cfg_err_cpl_timeout_n,
cfg_err_cpl_abort_n => cfg_err_cpl_abort_n,
cfg_err_cpl_unexpect_n => cfg_err_cpl_unexpect_n,
cfg_err_posted_n => cfg_err_posted_n,
cfg_err_tlp_cpl_header => cfg_err_tlp_cpl_header,
cfg_interrupt_n => cfg_interrupt_n,
cfg_interrupt_rdy_n => cfg_interrupt_rdy_n,
cfg_turnoff_ok_n => open,
cfg_to_turnoff_n => '1',
cfg_pm_wake_n => open,
cfg_bus_number => X"00",
cfg_device_number => "00000",
cfg_function_number => "000",
cfg_status => cfg_status,
cfg_command => cfg_command,
cfg_dstatus => cfg_dstatus,
cfg_dcommand => cfg_dcommand,
cfg_lstatus => cfg_lstatus,
cfg_lcommand => cfg_lcommand,
cfg_pcie_link_state_n => cfg_pcie_link_state_n,
cfg_trn_pending_n => cfg_trn_pending_n,
trn_clk => trn_clk,
trn_reset_n => trn_reset_n);
RX_APP : pci_exp_usrapp_rx
port map (
trn_rdst_rdy_n => trn_rdst_rdy_n,
trn_rnp_ok_n => trn_rnp_ok_n,
trn_rd => trn_rd,
trn_rrem_n => trn_rrem_n_in,
trn_rsof_n => trn_rsof_n,
trn_reof_n => trn_reof_n,
trn_rsrc_rdy_n => trn_rsrc_rdy_n,
trn_rsrc_dsc_n => trn_rsrc_dsc_n,
trn_rerrfwd_n => trn_rerrfwd_n,
trn_rbar_hit_n => trn_rbar_hit_n,
trn_clk => trn_clk,
trn_reset_n => trn_reset_n,
trn_lnk_up_n => trn_lnk_up_n,
rx_tx_read_data => rx_tx_read_data,
rx_tx_read_data_valid => rx_tx_read_data_valid,
tx_rx_read_data_valid => tx_rx_read_data_valid);
TX_APP : pci_exp_usrapp_tx
port map (
trn_td => trn_td,
trn_trem_n => trn_trem_n_out,
trn_tsof_n => trn_tsof_n,
trn_teof_n => trn_teof_n,
trn_terrfwd_n => trn_terrfwd_n,
trn_tsrc_rdy_n => trn_tsrc_rdy_n,
trn_tsrc_dsc_n => trn_tsrc_dsc_n,
trn_clk => trn_clk,
trn_reset_n => trn_reset_n,
trn_lnk_up_n => trn_lnk_up_n,
trn_tdst_rdy_n => trn_tdst_rdy_n,
trn_tdst_dsc_n => trn_tdst_dsc_n,
trn_tbuf_av => trn_tbuf_av,
rx_tx_read_data => rx_tx_read_data,
rx_tx_read_data_valid => rx_tx_read_data_valid,
tx_rx_read_data_valid => tx_rx_read_data_valid);
PL_APP : pci_exp_usrapp_pl
generic map (
LINK_CAP_MAX_LINK_SPEED => LINK_CAP_MAX_LINK_SPEED_int)
port map (
pl_initial_link_width => pl_initial_link_width,
pl_lane_reversal_mode => pl_lane_reversal_mode,
pl_link_gen2_capable => pl_link_gen2_capable,
pl_link_partner_gen2_supported => pl_link_partner_gen2_supported,
pl_link_upcfg_capable => pl_link_upcfg_capable,
pl_ltssm_state => pl_ltssm_state,
pl_received_hot_rst => '0',
pl_sel_link_rate => pl_sel_link_rate,
pl_sel_link_width => pl_sel_link_width,
pl_directed_link_auton => pl_directed_link_auton,
pl_directed_link_change => pl_directed_link_change,
pl_directed_link_speed => pl_directed_link_speed,
pl_directed_link_width => pl_directed_link_width,
pl_upstream_prefer_deemph => pl_upstream_prefer_deemph,
speed_change_done_n => open,
trn_lnk_up_n => trn_lnk_up_n,
trn_clk => trn_clk,
trn_reset_n => trn_reset_n);
end rtl;
| gpl-3.0 | 944d98fafc6343ab2a4c2623d78ba8ec | 0.508329 | 3.425271 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/ddr3_controller/user_design/rtl/memc1_infrastructure.vhd | 2 | 12,267 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.9
-- \ \ Application : MIG
-- / / Filename : memc1_infrastructure.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:59 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : Clock generation/distribution and reset synchronization
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity memc1_infrastructure is
generic
(
C_INCLK_PERIOD : integer := 2500;
C_RST_ACT_LOW : integer := 1;
C_INPUT_CLK_TYPE : string := "DIFFERENTIAL";
C_CLKOUT0_DIVIDE : integer := 1;
C_CLKOUT1_DIVIDE : integer := 1;
C_CLKOUT2_DIVIDE : integer := 16;
C_CLKOUT3_DIVIDE : integer := 8;
C_CLKFBOUT_MULT : integer := 2;
C_DIVCLK_DIVIDE : integer := 1
);
port
(
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_clk : in std_logic;
sys_rst_i : in std_logic;
clk0 : out std_logic;
rst0 : out std_logic;
async_rst : out std_logic;
sysclk_2x : out std_logic;
sysclk_2x_180 : out std_logic;
mcb_drp_clk : out std_logic;
pll_ce_0 : out std_logic;
pll_ce_90 : out std_logic;
pll_lock : out std_logic
);
end entity;
architecture syn of memc1_infrastructure is
-- # of clock cycles to delay deassertion of reset. Needs to be a fairly
-- high number not so much for metastability protection, but to give time
-- for reset (i.e. stable clock cycles) to propagate through all state
-- machines and to all control signals (i.e. not all control signals have
-- resets, instead they rely on base state logic being reset, and the effect
-- of that reset propagating through the logic). Need this because we may not
-- be getting stable clock cycles while reset asserted (i.e. since reset
-- depends on PLL/DCM lock status)
constant RST_SYNC_NUM : integer := 25;
constant CLK_PERIOD_NS : real := (real(C_INCLK_PERIOD)) / 1000.0;
constant CLK_PERIOD_INT : integer := C_INCLK_PERIOD/1000;
signal clk_2x_0 : std_logic;
signal clk_2x_180 : std_logic;
signal clk0_bufg : std_logic;
signal clk0_bufg_in : std_logic;
signal mcb_drp_clk_bufg_in : std_logic;
signal clkfbout_clkfbin : std_logic;
signal rst_tmp : std_logic;
signal sys_clk_ibufg : std_logic;
signal sys_rst : std_logic;
signal rst0_sync_r : std_logic_vector(RST_SYNC_NUM-1 downto 0);
signal powerup_pll_locked : std_logic;
signal syn_clk0_powerup_pll_locked : std_logic;
signal locked : std_logic;
signal bufpll_mcb_locked : std_logic;
signal mcb_drp_clk_sig : std_logic;
attribute max_fanout : string;
attribute syn_maxfan : integer;
attribute KEEP : string;
attribute max_fanout of rst0_sync_r : signal is "10";
attribute syn_maxfan of rst0_sync_r : signal is 10;
attribute KEEP of sys_clk_ibufg : signal is "TRUE";
begin
sys_rst <= not(sys_rst_i) when (C_RST_ACT_LOW /= 0) else sys_rst_i;
clk0 <= clk0_bufg;
pll_lock <= bufpll_mcb_locked;
mcb_drp_clk <= mcb_drp_clk_sig;
diff_input_clk : if(C_INPUT_CLK_TYPE = "DIFFERENTIAL") generate
--***********************************************************************
-- Differential input clock input buffers
--***********************************************************************
u_ibufg_sys_clk : IBUFGDS
generic map (
DIFF_TERM => TRUE
)
port map (
I => sys_clk_p,
IB => sys_clk_n,
O => sys_clk_ibufg
);
end generate;
se_input_clk : if(C_INPUT_CLK_TYPE = "SINGLE_ENDED") generate
--***********************************************************************
-- SINGLE_ENDED input clock input buffers
--***********************************************************************
u_ibufg_sys_clk : IBUFG
port map (
I => sys_clk,
O => sys_clk_ibufg
);
end generate;
--***************************************************************************
-- Global clock generation and distribution
--***************************************************************************
u_pll_adv : PLL_ADV
generic map
(
BANDWIDTH => "OPTIMIZED",
CLKIN1_PERIOD => CLK_PERIOD_NS,
CLKIN2_PERIOD => CLK_PERIOD_NS,
CLKOUT0_DIVIDE => C_CLKOUT0_DIVIDE,
CLKOUT1_DIVIDE => C_CLKOUT1_DIVIDE,
CLKOUT2_DIVIDE => C_CLKOUT2_DIVIDE,
CLKOUT3_DIVIDE => C_CLKOUT3_DIVIDE,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
CLKOUT0_PHASE => 0.000,
CLKOUT1_PHASE => 180.000,
CLKOUT2_PHASE => 0.000,
CLKOUT3_PHASE => 0.000,
CLKOUT4_PHASE => 0.000,
CLKOUT5_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKOUT4_DUTY_CYCLE => 0.500,
CLKOUT5_DUTY_CYCLE => 0.500,
SIM_DEVICE => "SPARTAN6",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => C_DIVCLK_DIVIDE,
CLKFBOUT_MULT => C_CLKFBOUT_MULT,
CLKFBOUT_PHASE => 0.0,
REF_JITTER => 0.005000
)
port map
(
CLKFBIN => clkfbout_clkfbin,
CLKINSEL => '1',
CLKIN1 => sys_clk_ibufg,
CLKIN2 => '0',
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DWE => '0',
REL => '0',
RST => sys_rst,
CLKFBDCM => open,
CLKFBOUT => clkfbout_clkfbin,
CLKOUTDCM0 => open,
CLKOUTDCM1 => open,
CLKOUTDCM2 => open,
CLKOUTDCM3 => open,
CLKOUTDCM4 => open,
CLKOUTDCM5 => open,
CLKOUT0 => clk_2x_0,
CLKOUT1 => clk_2x_180,
CLKOUT2 => clk0_bufg_in,
CLKOUT3 => mcb_drp_clk_bufg_in,
CLKOUT4 => open,
CLKOUT5 => open,
DO => open,
DRDY => open,
LOCKED => locked
);
U_BUFG_CLK0 : BUFG
port map
(
O => clk0_bufg,
I => clk0_bufg_in
);
--U_BUFG_CLK1 : BUFG
-- port map (
-- O => mcb_drp_clk_sig,
-- I => mcb_drp_clk_bufg_in
-- );
U_BUFG_CLK1 : BUFGCE
port map (
O => mcb_drp_clk_sig,
I => mcb_drp_clk_bufg_in,
CE => locked
);
process (mcb_drp_clk_sig, sys_rst)
begin
if(sys_rst = '1') then
powerup_pll_locked <= '0';
elsif (mcb_drp_clk_sig'event and mcb_drp_clk_sig = '1') then
if (bufpll_mcb_locked = '1') then
powerup_pll_locked <= '1';
end if;
end if;
end process;
process (clk0_bufg, sys_rst)
begin
if(sys_rst = '1') then
syn_clk0_powerup_pll_locked <= '0';
elsif (clk0_bufg'event and clk0_bufg = '1') then
if (bufpll_mcb_locked = '1') then
syn_clk0_powerup_pll_locked <= '1';
end if;
end if;
end process;
--***************************************************************************
-- Reset synchronization
-- NOTES:
-- 1. shut down the whole operation if the PLL hasn't yet locked (and
-- by inference, this means that external sys_rst has been asserted -
-- PLL deasserts LOCKED as soon as sys_rst asserted)
-- 2. asynchronously assert reset. This was we can assert reset even if
-- there is no clock (needed for things like 3-stating output buffers).
-- reset deassertion is synchronous.
-- 3. asynchronous reset only look at pll_lock from PLL during power up. After
-- power up and pll_lock is asserted, the powerup_pll_locked will be asserted
-- forever until sys_rst is asserted again. PLL will lose lock when FPGA
-- enters suspend mode. We don't want reset to MCB get
-- asserted in the application that needs suspend feature.
--***************************************************************************
async_rst <= sys_rst or not(powerup_pll_locked);
-- async_rst <= rst_tmp;
rst_tmp <= sys_rst or not(syn_clk0_powerup_pll_locked);
-- rst_tmp <= sys_rst or not(powerup_pll_locked);
process (clk0_bufg, rst_tmp)
begin
if (rst_tmp = '1') then
rst0_sync_r <= (others => '1');
elsif (rising_edge(clk0_bufg)) then
rst0_sync_r <= rst0_sync_r(RST_SYNC_NUM-2 downto 0) & '0'; -- logical left shift by one (pads with 0)
end if;
end process;
rst0 <= rst0_sync_r(RST_SYNC_NUM-1);
BUFPLL_MCB_INST : BUFPLL_MCB
port map
( IOCLK0 => sysclk_2x,
IOCLK1 => sysclk_2x_180,
LOCKED => locked,
GCLK => mcb_drp_clk_sig,
SERDESSTROBE0 => pll_ce_0,
SERDESSTROBE1 => pll_ce_90,
PLLIN0 => clk_2x_0,
PLLIN1 => clk_2x_180,
LOCK => bufpll_mcb_locked
);
end architecture syn;
| gpl-3.0 | 90df4aea62d564228de552f1aa138b9d | 0.531181 | 3.967335 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/pcie_core/simulation/dsport/gtx_rx_valid_filter_v6.vhd | 1 | 17,824 | -------------------------------------------------------------------------------
--
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : gtx_rx_valid_filter_v6.vhd
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity GTX_RX_VALID_FILTER_V6 is
generic (
CLK_COR_MIN_LAT : integer := 28
);
port (
USER_RXCHARISK : out std_logic_vector(1 downto 0);
USER_RXDATA : out std_logic_vector(15 downto 0);
USER_RXVALID : out std_logic;
USER_RXELECIDLE : out std_logic;
USER_RX_STATUS : out std_logic_vector(2 downto 0);
USER_RX_PHY_STATUS : out std_logic;
GT_RXCHARISK : in std_logic_vector(1 downto 0);
GT_RXDATA : in std_logic_vector(15 downto 0);
GT_RXVALID : in std_logic;
GT_RXELECIDLE : in std_logic;
GT_RX_STATUS : in std_logic_vector(2 downto 0);
GT_RX_PHY_STATUS : in std_logic;
PLM_IN_L0 : in std_logic;
PLM_IN_RS : in std_logic;
USER_CLK : in std_logic;
RESET : in std_logic
);
end GTX_RX_VALID_FILTER_V6;
architecture v6_pcie of GTX_RX_VALID_FILTER_V6 is
constant TCQ : integer := 1;
constant EIOS_DET_IDL : std_logic_vector(4 downto 0) := "00001";
constant EIOS_DET_NO_STR0 : std_logic_vector(4 downto 0) := "00010";
constant EIOS_DET_STR0 : std_logic_vector(4 downto 0) := "00100";
constant EIOS_DET_STR1 : std_logic_vector(4 downto 0) := "01000";
constant EIOS_DET_DONE : std_logic_vector(4 downto 0) := "10000";
constant EIOS_COM : std_logic_vector(7 downto 0) := "10111100";
constant EIOS_IDL : std_logic_vector(7 downto 0) := "01111100";
constant USER_RXVLD_IDL : std_logic_vector(3 downto 0) := "0001";
constant USER_RXVLD_EI : std_logic_vector(3 downto 0) := "0010";
constant USER_RXVLD_EI_DB0 : std_logic_vector(3 downto 0) := "0100";
constant USER_RXVLD_EI_DB1 : std_logic_vector(3 downto 0) := "1000";
constant TS1_FILTER_IDLE : std_logic_vector(2 downto 0) := "001";
constant TS1_FILTER_WAITVALID : std_logic_vector(2 downto 0) := "010";
constant TS1_FILTER_DB : std_logic_vector(2 downto 0) := "100";
FUNCTION to_stdlogicvector (
val_in : IN integer;
length : IN integer) RETURN std_logic_vector IS
VARIABLE ret : std_logic_vector(length-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE num : integer := val_in;
VARIABLE x : integer;
BEGIN
FOR index IN 0 TO length-1 LOOP
x := num rem 2;
num := num/2;
IF (x = 1) THEN
ret(index) := '1';
ELSE
ret(index) := '0';
END IF;
END LOOP;
RETURN(ret);
END to_stdlogicvector;
signal reg_state_eios_det : std_logic_vector(4 downto 0);
signal state_eios_det : std_logic_vector(4 downto 0);
signal reg_eios_detected : std_logic;
signal eios_detected : std_logic;
signal reg_symbol_after_eios : std_logic;
signal symbol_after_eios : std_logic;
signal reg_state_rxvld_ei : std_logic_vector(3 downto 0);
signal state_rxvld_ei : std_logic_vector(3 downto 0);
signal reg_rxvld_count : std_logic_vector(4 downto 0);
signal rxvld_count : std_logic_vector(4 downto 0);
signal reg_rxvld_fallback : std_logic_vector(3 downto 0);
signal rxvld_fallback : std_logic_vector(3 downto 0);
signal gt_rxcharisk_q : std_logic_vector(1 downto 0);
signal gt_rxdata_q : std_logic_vector(15 downto 0);
signal gt_rxvalid_q : std_logic;
signal gt_rxelecidle_q : std_logic;
signal gt_rx_status_q : std_logic_vector(2 downto 0);
signal gt_rx_phy_status_q : std_logic;
signal ts1_state : std_logic_vector(2 downto 0);
signal next_ts1_state : std_logic_vector(2 downto 0);
signal ts1_resetcount : std_logic;
signal ts1_count : std_logic_vector(8 downto 0);
signal ts1_filter_done : std_logic;
signal next_ts1_filter_done : std_logic;
-- Declare intermediate signals for referenced outputs
signal USER_RXVALID_v6pcie1 : std_logic;
signal USER_RXELECIDLE_v6pcie0 : std_logic;
begin
-- Drive referenced outputs
USER_RXVALID <= USER_RXVALID_v6pcie1;
USER_RXELECIDLE <= USER_RXELECIDLE_v6pcie0;
-- EIOS detector
process (USER_CLK)
begin
if (USER_CLK'event and USER_CLK = '1') then
if (RESET = '1') then
reg_eios_detected <= '0' after (TCQ)*1 ps;
reg_state_eios_det <= EIOS_DET_IDL after (TCQ)*1 ps;
reg_symbol_after_eios <= '0' after (TCQ)*1 ps;
gt_rxcharisk_q <= "00" after (TCQ)*1 ps;
gt_rxdata_q <= "0000000000000000" after (TCQ)*1 ps;
gt_rxvalid_q <= '0' after (TCQ)*1 ps;
gt_rxelecidle_q <= '0' after (TCQ)*1 ps;
gt_rx_status_q <= "000" after (TCQ)*1 ps;
gt_rx_phy_status_q <= '0' after (TCQ)*1 ps;
else
reg_eios_detected <= '0' after (TCQ)*1 ps;
reg_symbol_after_eios <= '0' after (TCQ)*1 ps;
gt_rxcharisk_q <= GT_RXCHARISK after (TCQ)*1 ps;
gt_rxdata_q <= GT_RXDATA after (TCQ)*1 ps;
gt_rxvalid_q <= GT_RXVALID after (TCQ)*1 ps;
gt_rxelecidle_q <= GT_RXELECIDLE after (TCQ)*1 ps;
gt_rx_status_q <= GT_RX_STATUS after (TCQ)*1 ps;
gt_rx_phy_status_q <= GT_RX_PHY_STATUS after (TCQ)*1 ps;
case state_eios_det is
when EIOS_DET_IDL =>
if ((gt_rxcharisk_q(0) = '1') and (gt_rxdata_q(7 downto 0) = EIOS_COM) and (gt_rxcharisk_q(1) = '1') and (gt_rxdata_q(15 downto 8) = EIOS_IDL)) then
reg_state_eios_det <= EIOS_DET_NO_STR0 after (TCQ)*1 ps;
reg_eios_detected <= '1' after (TCQ)*1 ps;
elsif ((gt_rxcharisk_q(1) = '1') and (gt_rxdata_q(15 downto 8) = EIOS_COM)) then
reg_state_eios_det <= EIOS_DET_STR0 after (TCQ)*1 ps;
else
reg_state_eios_det <= EIOS_DET_IDL after (TCQ)*1 ps;
end if;
when EIOS_DET_NO_STR0 =>
if ((gt_rxcharisk_q(0) = '1') and (gt_rxdata_q(7 downto 0) = EIOS_IDL) and (gt_rxcharisk_q(1) = '1') and (gt_rxdata_q(15 downto 8) = EIOS_IDL)) then
reg_state_eios_det <= EIOS_DET_DONE after (TCQ)*1 ps;
else
reg_state_eios_det <= EIOS_DET_IDL after (TCQ)*1 ps;
end if;
when EIOS_DET_STR0 =>
if ((gt_rxcharisk_q(0) = '1') and (gt_rxdata_q(7 downto 0) = EIOS_IDL) and (gt_rxcharisk_q(1) = '1') and (gt_rxdata_q(15 downto 8) = EIOS_IDL)) then
reg_state_eios_det <= EIOS_DET_STR1 after (TCQ)*1 ps;
reg_eios_detected <= '1' after (TCQ)*1 ps;
reg_symbol_after_eios <= '1' after (TCQ)*1 ps;
else
reg_state_eios_det <= EIOS_DET_IDL after (TCQ)*1 ps;
end if;
when EIOS_DET_STR1 =>
if ((gt_rxcharisk_q(0) = '1') and (gt_rxdata_q(7 downto 0) = EIOS_IDL)) then
reg_state_eios_det <= EIOS_DET_DONE after (TCQ)*1 ps;
else
reg_state_eios_det <= EIOS_DET_IDL after (TCQ)*1 ps;
end if;
when EIOS_DET_DONE =>
reg_state_eios_det <= EIOS_DET_IDL after (TCQ)*1 ps;
when others =>
reg_state_eios_det <= EIOS_DET_IDL after (TCQ)*1 ps;
end case;
end if;
end if;
end process;
state_eios_det <= reg_state_eios_det;
eios_detected <= reg_eios_detected;
symbol_after_eios <= reg_symbol_after_eios;
-- user_rxvalid generation
process (USER_CLK)
begin
if (USER_CLK'event and USER_CLK = '1') then
if (RESET = '1') then
reg_state_rxvld_ei <= USER_RXVLD_IDL after (TCQ)*1 ps;
else
case state_rxvld_ei is
when USER_RXVLD_IDL =>
if (eios_detected = '1') then
reg_state_rxvld_ei <= USER_RXVLD_EI after (TCQ)*1 ps;
else
reg_state_rxvld_ei <= USER_RXVLD_IDL after (TCQ)*1 ps;
end if;
when USER_RXVLD_EI =>
if ((not(gt_rxvalid_q)) = '1') then
reg_state_rxvld_ei <= USER_RXVLD_EI_DB0 after (TCQ)*1 ps;
elsif (rxvld_fallback = "1111") then
reg_state_rxvld_ei <= USER_RXVLD_IDL after (TCQ)*1 ps;
else
reg_state_rxvld_ei <= USER_RXVLD_EI after (TCQ)*1 ps;
end if;
when USER_RXVLD_EI_DB0 =>
if (gt_rxvalid_q = '1') then
reg_state_rxvld_ei <= USER_RXVLD_EI_DB1 after (TCQ)*1 ps;
elsif ((not(PLM_IN_L0)) = '1') then
reg_state_rxvld_ei <= USER_RXVLD_IDL after (TCQ)*1 ps;
else
reg_state_rxvld_ei <= USER_RXVLD_EI_DB0 after (TCQ)*1 ps;
end if;
when USER_RXVLD_EI_DB1 =>
if (rxvld_count > to_stdlogicvector(CLK_COR_MIN_LAT, 5)) then
reg_state_rxvld_ei <= USER_RXVLD_IDL after (TCQ)*1 ps;
else
reg_state_rxvld_ei <= USER_RXVLD_EI_DB1 after (TCQ)*1 ps;
end if;
when others =>
reg_state_rxvld_ei <= USER_RXVLD_IDL after (TCQ)*1 ps;
end case;
end if;
end if;
end process;
state_rxvld_ei <= reg_state_rxvld_ei;
-- RxValid counter
process (USER_CLK)
begin
if (USER_CLK'event and USER_CLK = '1') then
if (RESET = '1') then
reg_rxvld_count <= "00000" after (TCQ)*1 ps;
else
if ((gt_rxvalid_q = '1') and (state_rxvld_ei = USER_RXVLD_EI_DB1)) then
reg_rxvld_count <= reg_rxvld_count + "00001" after (TCQ)*1 ps;
else
reg_rxvld_count <= "00000" after (TCQ)*1 ps;
end if;
end if;
end if;
end process;
rxvld_count <= reg_rxvld_count;
-- RxValid fallback
process (USER_CLK)
begin
if (USER_CLK'event and USER_CLK = '1') then
if (RESET = '1') then
reg_rxvld_fallback <= "0000" after (TCQ)*1 ps;
else
if (state_rxvld_ei = USER_RXVLD_EI) then
reg_rxvld_fallback <= reg_rxvld_fallback + "0001" after (TCQ)*1 ps;
else
reg_rxvld_fallback <= "0000" after (TCQ)*1 ps;
end if;
end if;
end if;
end process;
rxvld_fallback <= reg_rxvld_fallback;
-- Delay pipe_rx_elec_idle
rx_elec_idle_delay : SRL16E
generic map (
INIT => X"0000"
)
port map (
Q => USER_RXELECIDLE_v6pcie0,
D => gt_rxelecidle_q,
CLK => USER_CLK,
CE => '1',
A3 => '1',
A2 => '1',
A1 => '1',
A0 => '1'
);
process (ts1_state, ts1_filter_done, PLM_IN_RS, gt_rxvalid_q, gt_rxelecidle_q, ts1_count)
begin
next_ts1_state <= ts1_state;
ts1_resetcount <= '0';
next_ts1_filter_done <= ts1_filter_done;
case ts1_state is
when TS1_FILTER_IDLE =>
ts1_resetcount <= '1';
if (PLM_IN_RS = '1') then
if ((not(ts1_filter_done)) = '1') then
next_ts1_state <= TS1_FILTER_WAITVALID;
end if;
else
next_ts1_filter_done <= '0';
end if;
when TS1_FILTER_WAITVALID =>
ts1_resetcount <= '1';
next_ts1_filter_done <= '0';
if ((gt_rxvalid_q and not(gt_rxelecidle_q)) = '1') then
next_ts1_state <= TS1_FILTER_DB;
end if;
when TS1_FILTER_DB =>
next_ts1_filter_done <= '0';
if ((ts1_count(6)) = '1') then
next_ts1_state <= TS1_FILTER_IDLE;
next_ts1_filter_done <= '1';
end if;
when others =>
null;
end case;
end process;
process (USER_CLK)
begin
if (USER_CLK'event and USER_CLK = '1') then
if (RESET = '1') then
ts1_state <= TS1_FILTER_IDLE after (TCQ)*1 ps;
ts1_count <= "000000000" after (TCQ)*1 ps;
ts1_filter_done <= '0' after (TCQ)*1 ps;
else
ts1_state <= next_ts1_state after (TCQ)*1 ps;
ts1_filter_done <= next_ts1_filter_done after (TCQ)*1 ps;
if (ts1_resetcount = '1') then
ts1_count <= "000000000" after (TCQ)*1 ps;
else
ts1_count <= ts1_count + "000000001" after (TCQ)*1 ps;
end if;
end if;
end if;
end process;
USER_RXVALID_v6pcie1 <= gt_rxvalid_q when ((state_rxvld_ei = USER_RXVLD_IDL) and (ts1_state = TS1_FILTER_IDLE)) else
'0';
USER_RXCHARISK(0) <= gt_rxcharisk_q(0) when (USER_RXVALID_v6pcie1 = '1') else
'0';
USER_RXCHARISK(1) <= gt_rxcharisk_q(1) when ((USER_RXVALID_v6pcie1 and not(symbol_after_eios)) = '1') else
'0';
USER_RXDATA <= gt_rxdata_q;
USER_RX_STATUS <= gt_rx_status_q when (state_rxvld_ei = USER_RXVLD_IDL) else
"000";
USER_RX_PHY_STATUS <= gt_rx_phy_status_q;
end v6_pcie;
| gpl-3.0 | 536a1c79519045b3ca53858f1f6443c1 | 0.494614 | 3.754793 | false | false | false | false |
JavierRizzoA/Sacagawea | sources/test_cu.vhd | 1 | 2,815 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:28:44 06/05/2016
-- Design Name:
-- Module Name: C:/Users/AlvaroMoreno/Desktop/proooc/sacagawea_copy/test_cu.vhd
-- Project Name: Sacagawea
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Unidad_de_Control
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY test_cu IS
END test_cu;
ARCHITECTURE behavior OF test_cu IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Unidad_de_Control
PORT(
IR : IN std_logic_vector(7 downto 0);
clk : IN std_logic;
sal_control : OUT std_logic_vector(24 downto 0)
);
END COMPONENT;
--Inputs
signal IR : std_logic_vector(7 downto 0) := (others => '0');
signal clk : std_logic := '0';
--Outputs
signal sal_control : std_logic_vector(24 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Unidad_de_Control PORT MAP (
IR => IR,
clk => clk,
sal_control => sal_control
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
clk <= '0';
IR <= X"F1";
wait for 100 ns;
clk <= '1';
IR <= X"F1";
wait for 100 ns;
clk <= '0';
wait for 100 ns;
clk <= '1';
wait for 100 ns;
clk <= '0';
wait for 100 ns;
clk <= '1';
wait for 100 ns;
clk <= '0';
wait for 100 ns;
clk <= '1';
wait for 100 ns;
clk <= '0';
wait for 100 ns;
clk <= '1';
wait for 100 ns;
clk <= '0';
wait for 100 ns;
clk <= '1';
wait for 100 ns;
clk <= '0';
wait for 100 ns;
clk <= '1';
wait for 100 ns;
clk <= '0';
wait for 100 ns;
clk <= '1';
wait for 100 ns;
clk <= '0';
wait for 100 ns;
wait;
end process;
END;
| mit | dcc197fd01d0d5994c35c34298f8fb64 | 0.519361 | 3.608974 | false | true | false | false |
stereoboy/Study | Udemy/EmbeddedSystemDesignWithXilinxZynqFPGAAndVIVADO/Sec08/Lab 82 Sources/bcd_vhd.vhd | 1 | 1,448 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
port ( clk : in std_logic;
reset : in std_logic;
pause : in std_logic;
count_out : out std_logic_vector(3 downto 0));
end counter;
architecture Behavioral of counter is
signal temp_count : std_logic_vector(3 downto 0) := x"0";
signal slow_clk : std_logic;
-- Clock divider can be changed to suit application.
-- Clock (clk) is normally 100 MHz, so each clock cycle
-- is 10 ns. A clock divider of 'n' bits will make 1
-- slow_clk cycle equal 2^n clk cycles.
signal clk_divider : std_logic_vector(24 downto 0) := "0000000000000000000000000"; --25 binary bit value
begin
-- Process that makes slow clock go high only when MSB of
-- clk_divider goes high.
clk_division : process (clk, clk_divider)
begin
if (clk = '1' and clk'event) then
clk_divider <= clk_divider + 1;
end if;
slow_clk <= clk_divider(24);
end process;
counting : process(reset, pause, slow_clk, temp_count)
begin
if reset = '1' then
temp_count <= "0000"; -- Asynchronous reset.
elsif pause = '1' then
temp_count <= temp_count; -- Asynchronous count pause.
else
if slow_clk'event and slow_clk ='1' then -- Counting state
if temp_count < 9 then
temp_count <= temp_count + 1; -- Counter increase
else
temp_count <= "0000"; -- Rollover to zero
end if;
end if;
end if;
count_out <= temp_count; -- Output
end process;
end Behavioral; -- End module.
| mit | 16a8db369fc65ceb390c4499e7935dd6 | 0.706492 | 3.154684 | false | false | false | false |
masaruohashi/tic-tac-toe | interface_modem/unidade_controle_modem_transmissao.vhd | 1 | 2,456 | -- VHDL da Unidade de Controle da transmissão
library ieee;
use ieee.std_logic_1164.all;
entity unidade_controle_modem_transmissao is
port(clock : in std_logic;
reset : in std_logic;
liga : in std_logic;
enviar : in std_logic;
CTS : in std_logic;
DTR : out std_logic;
RTS : out std_logic;
envioOk : out std_logic;
saida : out std_logic_vector(3 downto 0)); -- controle de estados
end unidade_controle_modem_transmissao;
architecture unidade_controle of unidade_controle_modem_transmissao is
type tipo_estado is (inicial, preparacao, transmissao, desabilitado, final);
signal estado : tipo_estado;
begin
process (clock, estado, reset)
begin
if liga = '0' then
estado <= desabilitado;
elsif reset = '1' then
estado <= inicial;
elsif (clock'event and clock = '1') then
case estado is
when inicial => -- Aguarda sinal de inicio
if enviar = '1' then
estado <= preparacao;
end if;
when preparacao => -- Espera sinal de controle CTS do modem
if CTS = '0' then -- Ativo em baixo
estado <= transmissao;
end if;
when transmissao => -- Envia o que estiver na entrada de dados
if enviar = '0' then
estado <= final;
end if;
when final => -- Fim da transmissao serial
if CTS = '1' then
estado <= inicial;
end if;
when desabilitado => -- Circuito desabilitado
if liga = '1' then
estado <= inicial;
end if;
end case;
end if;
end process;
process (estado)
begin
case estado is
when inicial =>
saida <= "0000";
envioOk <= '0';
DTR <= '0';
RTS <= '1';
when preparacao =>
saida <= "0001";
envioOk <= '0';
DTR <= '0';
RTS <= '0';
when transmissao =>
saida <= "0010";
envioOk <= '1';
DTR <= '0';
RTS <= '0';
when final =>
saida <= "0011";
envioOk <= '0';
DTR <= '0';
RTS <= '1';
when desabilitado =>
saida <= "1111";
envioOk <= '0';
DTR <= '1';
RTS <= '1';
end case;
end process;
end unidade_controle; | mit | 902dc5644fa6cf207052f9c4571bf323 | 0.49613 | 4.078073 | false | false | false | false |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/pcie_core/simulation/dsport/pci_exp_usrapp_pl.vhd | 1 | 4,756 | -------------------------------------------------------------------------------
--
-- (c) Copyright 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : pci_exp_usrapp_pl.vhd
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity pci_exp_usrapp_pl is
generic (
LINK_CAP_MAX_LINK_SPEED : integer := 1);
port (
pl_initial_link_width : in std_logic_vector(2 downto 0);
pl_lane_reversal_mode : in std_logic_vector(1 downto 0);
pl_link_gen2_capable : in std_logic;
pl_link_partner_gen2_supported : in std_logic;
pl_link_upcfg_capable : in std_logic;
pl_ltssm_state : in std_logic_vector(5 downto 0);
pl_received_hot_rst : in std_logic;
pl_sel_link_rate : in std_logic;
pl_sel_link_width : in std_logic_vector(1 downto 0);
pl_directed_link_auton : out std_logic;
pl_directed_link_change : out std_logic_vector(1 downto 0);
pl_directed_link_speed : out std_logic;
pl_directed_link_width : out std_logic_vector(1 downto 0);
pl_upstream_prefer_deemph : out std_logic;
speed_change_done_n : out std_logic;
trn_lnk_up_n : in std_logic;
trn_clk : in std_logic;
trn_reset_n : in std_logic
);
end pci_exp_usrapp_pl;
architecture rtl of pci_exp_usrapp_pl is
constant Tcq : integer := 1;
begin
process
begin
pl_directed_link_auton <= '0';
pl_directed_link_change <= "00";
pl_directed_link_speed <= '0';
pl_directed_link_width <= "00";
pl_upstream_prefer_deemph <= '0';
speed_change_done_n <= '1';
if (LINK_CAP_MAX_LINK_SPEED = 2) then
wait until trn_lnk_up_n = '0';
pl_directed_link_speed <= '1';
pl_directed_link_change <= "10";
wait until pl_ltssm_state = "100000";
pl_directed_link_speed <= '0';
pl_directed_link_change <= "00";
wait until pl_sel_link_rate = '1';
speed_change_done_n <= '0';
end if;
wait;
end process;
end rtl;
-- pci_exp_usrapp_pl
| gpl-3.0 | 6aac9c972015af37c47a51e6b86ab096 | 0.600084 | 4.033927 | false | false | false | false |
qynvi/rtl-sgncounter | sngcounter.vhd | 1 | 859 | -- William Fan
-- 02/14/2011
-- Signed Counter RTL
package sgncounter is
component counter is
port (j,k: in std_logic;
out_bin: out std_logic);
end component;
end package;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.sgncounter.all;
entity scounter is
generic (N: integer := 4);
port (clk: in std_logic;
out_bin,out_gray: out std_logic_vector(N-1 downto 0));
end scounter;
architecture sc of scounter is
signal tmp1: std_logic_vector(N-1 downto 0);
signal tmp2: integer <= N-1;
function g2b (input,output: std_logic_vector) return std_logic_vector is
begin
output(N-1) <= input(N-1);
gen: For i in tmp2'RANGE generate
output(i-1) <= output(i) XOR input(i-1);
end generate;
end function;
begin
process (clk)
begin
if (clk'event and clk='1') then
end if;
end process;
end architecture;
| mit | 252a595b55df57c75045c4fd9ad75ba2 | 0.703143 | 2.788961 | false | false | false | false |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/common/lib/src/cntRtl.vhd | 3 | 3,878 | -------------------------------------------------------------------------------
--! @file cntRtl.vhd
--
--! @brief Terminal Counter
--
--! @details The terminal counter is a synchronous counter configured
--! by several generics.
--
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity cnt is
generic (
--! Width of counter
gCntWidth : natural := 32;
--! Value that triggers the counter reset
gTcntVal : natural := 1000
);
port (
iArst : in std_logic;
iClk : in std_logic;
iEnable : in std_logic;
iSrst : in std_logic;
oCnt : out std_logic_vector(gCntWidth-1 downto 0);
oTcnt : out std_logic
);
end entity;
architecture rtl of cnt is
constant cTcntVal : std_logic_vector(gCntWidth-1 downto 0) :=
std_logic_vector(to_unsigned(gTcntVal, gCntWidth));
signal cnt, cnt_next : std_logic_vector(gCntWidth-1 downto 0);
signal tc : std_logic;
begin
-- handle wrong generics
assert (gTcntVal > 0)
report "Terminal count value of 0 makes no sense!"
severity failure;
regClk : process(iArst, iClk)
begin
if iArst = cActivated then
cnt <= (others => cInactivated);
elsif rising_edge(iClk) then
cnt <= cnt_next;
end if;
end process;
tc <= cActivated when cnt = cTcntVal else
cInactivated;
oCnt <= cnt;
oTcnt <= tc;
comb : process(iSrst, iEnable, cnt, tc)
begin
--default
cnt_next <= cnt;
if iSrst = cActivated then
cnt_next <= (others => cInactivated);
elsif iEnable = cActivated then
if tc = cActivated then
cnt_next <= (others => cInactivated);
else
cnt_next <= std_logic_vector(unsigned(cnt) + 1);
end if;
end if;
end process;
end architecture;
| gpl-2.0 | cfdfa25ca0994356301a3779939f5516 | 0.612687 | 4.514552 | false | false | false | false |
SonicFrog/ArchOrd | transmitter.vhdl | 1 | 1,694 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity transmitter is
port (
start : in std_logic;
memdata : in std_logic_vector(7 downto 0);
memaddr : in std_logic_vector(7 downto 0);
acknum : in std_logic_vector(7 downto 0);
clk : in std_logic;
reset : in std_logic;
num : out std_logic_vector(7 downto 0);
data : out std_logic_vector(7 downto 0);
valid : out std_logic
);
end transmitter;
architecture synth of transmitter is
signal countNotZero : std_logic;
signal wordcount : std_logic_vector(7 downto 0);
signal next_wordcount : std_logic_vector(7 downto 0);
signal enable : std_logic;
signal lastack : std_logic_vector(7 downto 0);
begin
enable <= start or countNotZero;
countNotZero <= '0' when wordcount = 0 else '1';
num <= wordcount;
memaddr <= wordcount;
-- This processh handles changing the state synchronously
switch : process(clk, next_wordcount)
begin
if reset = '1' then
wordcount <= (others => '0');
elsif rising_edge(clk) then
wordcount <= next_wordcount;
end if;
end process;
-- This process handles the changing of the address of the word
count : process(clk, lastack, enable)
begin
next_wordcount <= wordcount;
if lastack + 4 = wordcount then
wordcount <= lastack + 1;
elsif enable = '1' then
next_wordcount <= wordcount + 1;
end if;
end process;
-- This process does stuff related to the ACK
ack : process(clk, acknum, ack)
begin
if reset = '1' then
lastack <= (others => '0');
elsif rising_edge(clk) then
if ack = '1' then
lastack <= acknum;
end if;
end if;
end process;
end architecture ; -- synth | gpl-2.0 | d00a2e7a51c4cb12ff83bd4c375763aa | 0.678276 | 2.880952 | false | false | false | false |
hpeng2/ECE492_Group4_Project | Ryans_stuff/tracking_camera/tracking_camera.vhd | 1 | 8,581 | -- Nancy Minderman
-- [email protected]
-- This file makes extensive use of Altera template structures.
-- This file is the top-level file for lab 1 winter 2014 for version 12.1sp1 on Windows 7
-- A library clause declares a name as a library. It
-- does not create the library; it simply forward declares
-- it.
library ieee;
-- Commonly imported packages:
-- STD_LOGIC and STD_LOGIC_VECTOR types, and relevant functions
use ieee.std_logic_1164.all;
-- SIGNED and UNSIGNED types, and relevant functions
use ieee.numeric_std.all;
-- Basic sequential functions and concurrent procedures
use ieee.VITAL_Primitives.all;
use work.DE2_CONSTANTS.all;
entity tracking_camera is
port
(
-- Input ports and 50 MHz Clock
KEY : in std_logic_vector (0 downto 0);
SW : in std_logic_vector (1 downto 0);
CLOCK_50 : in std_logic;
GPIO_0 : out std_logic_vector (0 downto 0);
-- Green leds on board
LEDG : out DE2_LED_GREEN;
-- LCD on board
LCD_BLON : out std_logic;
LCD_ON : out std_logic;
LCD_DATA : inout DE2_LCD_DATA_BUS;
LCD_RS : out std_logic;
LCD_EN : out std_logic;
LCD_RW : out std_logic;
-- SDRAM on board
--DRAM_ADDR : out std_logic_vector (11 downto 0);
DRAM_ADDR : out DE2_SDRAM_ADDR_BUS;
DRAM_BA_0 : out std_logic;
DRAM_BA_1 : out std_logic;
DRAM_CAS_N : out std_logic;
DRAM_CKE : out std_logic;
DRAM_CLK : out std_logic;
DRAM_CS_N : out std_logic;
--DRAM_DQ : inout std_logic_vector (15 downto 0);
DRAM_DQ : inout DE2_SDRAM_DATA_BUS;
DRAM_LDQM : out std_logic;
DRAM_UDQM : out std_logic;
DRAM_RAS_N : out std_logic;
DRAM_WE_N : out std_logic;
-- SRAM on board
SRAM_ADDR : out DE2_SRAM_ADDR_BUS;
SRAM_DQ : inout DE2_SRAM_DATA_BUS;
SRAM_WE_N : out std_logic;
SRAM_OE_N : out std_logic;
SRAM_UB_N : out std_logic;
SRAM_LB_N : out std_logic;
SRAM_CE_N : out std_logic
);
end tracking_camera;
architecture structure of tracking_camera is
-- Declarations (optional)
component tracking_camera_system is
port (
servo_pwm_0_conduit_end_0_export : out std_logic;
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
sdram_0_wire_addr : out DE2_SDRAM_ADDR_BUS; -- addr
sdram_0_wire_ba : out std_logic_vector(1 downto 0); -- ba
sdram_0_wire_cas_n : out std_logic; -- cas_n
sdram_0_wire_cke : out std_logic; -- cke
sdram_0_wire_cs_n : out std_logic; -- cs_n
sdram_0_wire_dq : inout DE2_SDRAM_DATA_BUS := (others => 'X'); -- dq
sdram_0_wire_dqm : out std_logic_vector(1 downto 0); -- dqm
sdram_0_wire_ras_n : out std_logic; -- ras_n
sdram_0_wire_we_n : out std_logic; -- we_n
altpll_0_c0_clk : out std_logic; -- clk
green_leds_external_connection_export : out DE2_LED_GREEN; -- export
switch_external_connection_export : in std_logic := 'X'; -- export
switch_0_external_connection_export : in std_logic := 'X';
sram_0_external_interface_DQ : inout DE2_SRAM_DATA_BUS := (others => 'X'); -- DQ
sram_0_external_interface_ADDR : out DE2_SRAM_ADDR_BUS; -- ADDR
sram_0_external_interface_LB_N : out std_logic; -- LB_N
sram_0_external_interface_UB_N : out std_logic; -- UB_N
sram_0_external_interface_CE_N : out std_logic; -- CE_N
sram_0_external_interface_OE_N : out std_logic; -- OE_N
sram_0_external_interface_WE_N : out std_logic; -- WE_N
character_lcd_0_external_interface_DATA : inout DE2_LCD_DATA_BUS := (others => 'X'); -- DATA
character_lcd_0_external_interface_ON : out std_logic; -- ON
character_lcd_0_external_interface_BLON : out std_logic; -- BLON
character_lcd_0_external_interface_EN : out std_logic; -- EN
character_lcd_0_external_interface_RS : out std_logic; -- RS
character_lcd_0_external_interface_RW : out std_logic -- RW
);
end component tracking_camera_system;
-- These signals are for matching the provided IP core to
-- The specific SDRAM chip in our system
signal BA : std_logic_vector (1 downto 0);
signal DQM : std_logic_vector (1 downto 0);
begin
DRAM_BA_1 <= BA(1);
DRAM_BA_0 <= BA(0);
DRAM_UDQM <= DQM(1);
DRAM_LDQM <= DQM(0);
-- Component Instantiation Statement (optional)
u0 : component tracking_camera_system
port map (
servo_pwm_0_conduit_end_0_export => GPIO_0(0),
clk_clk => CLOCK_50,
reset_reset_n => KEY(0),
sdram_0_wire_addr => DRAM_ADDR,
sdram_0_wire_ba => BA,
sdram_0_wire_cas_n => DRAM_CAS_N,
sdram_0_wire_cke => DRAM_CKE,
sdram_0_wire_cs_n => DRAM_CS_N,
sdram_0_wire_dq => DRAM_DQ,
sdram_0_wire_dqm => DQM,
sdram_0_wire_ras_n => DRAM_RAS_N,
sdram_0_wire_we_n => DRAM_WE_N,
altpll_0_c0_clk => DRAM_CLK,
green_leds_external_connection_export => LEDG,
switch_external_connection_export => SW(0),
switch_0_external_connection_export => SW(1),
sram_0_external_interface_DQ => SRAM_DQ,
sram_0_external_interface_ADDR => SRAM_ADDR,
sram_0_external_interface_LB_N => SRAM_LB_N,
sram_0_external_interface_UB_N => SRAM_UB_N,
sram_0_external_interface_CE_N => SRAM_CE_N,
sram_0_external_interface_OE_N => SRAM_OE_N,
sram_0_external_interface_WE_N => SRAM_WE_N,
character_lcd_0_external_interface_DATA => LCD_DATA,
character_lcd_0_external_interface_ON => LCD_ON,
character_lcd_0_external_interface_BLON => LCD_BLON,
character_lcd_0_external_interface_EN => LCD_EN,
character_lcd_0_external_interface_RS => LCD_RS,
character_lcd_0_external_interface_RW => LCD_RW
);
end structure;
library ieee;
-- Commonly imported packages:
-- STD_LOGIC and STD_LOGIC_VECTOR types, and relevant functions
use ieee.std_logic_1164.all;
package DE2_CONSTANTS is
type DE2_SDRAM_ADDR_BUS is array(11 downto 0) of std_logic;
type DE2_SDRAM_DATA_BUS is array(15 downto 0) of std_logic;
type DE2_LCD_DATA_BUS is array(7 downto 0) of std_logic;
type DE2_LED_GREEN is array(7 downto 0) of std_logic;
type DE2_SRAM_ADDR_BUS is array(17 downto 0) of std_logic;
type DE2_SRAM_DATA_BUS is array(15 downto 0) of std_logic;
end DE2_CONSTANTS;
| gpl-2.0 | 26fdf8c47310bfec25182cd981b7e938 | 0.470924 | 3.711505 | false | false | false | false |
hoglet67/ElectronFpga | src/altera/max10_pll1.vhd | 1 | 21,293 | -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: max10_pll1.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 17.1.0 Build 590 10/25/2017 SJ Lite Edition
-- ************************************************************
--Copyright (C) 2017 Intel Corporation. All rights reserved.
--Your use of Intel Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Intel Program License
--Subscription Agreement, the Intel Quartus Prime License Agreement,
--the Intel FPGA IP License Agreement, or other applicable license
--agreement, including, without limitation, that your use is for
--the sole purpose of programming logic devices manufactured by
--Intel and sold by Intel or its authorized distributors. Please
--refer to the applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY max10_pll1 IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
c3 : OUT STD_LOGIC ;
c4 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END max10_pll1;
ARCHITECTURE SYN OF max10_pll1 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire2_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC ;
SIGNAL sub_wire7 : STD_LOGIC ;
SIGNAL sub_wire8 : STD_LOGIC ;
SIGNAL sub_wire9 : STD_LOGIC ;
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
clk3_divide_by : NATURAL;
clk3_duty_cycle : NATURAL;
clk3_multiply_by : NATURAL;
clk3_phase_shift : STRING;
clk4_divide_by : NATURAL;
clk4_duty_cycle : NATURAL;
clk4_multiply_by : NATURAL;
clk4_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire2_bv(0 DOWNTO 0) <= "0";
sub_wire2 <= To_stdlogicvector(sub_wire2_bv);
sub_wire0 <= inclk0;
sub_wire1 <= sub_wire2(0 DOWNTO 0) & sub_wire0;
sub_wire8 <= sub_wire3(4);
sub_wire7 <= sub_wire3(3);
sub_wire6 <= sub_wire3(2);
sub_wire5 <= sub_wire3(1);
sub_wire4 <= sub_wire3(0);
c0 <= sub_wire4;
c1 <= sub_wire5;
c2 <= sub_wire6;
c3 <= sub_wire7;
c4 <= sub_wire8;
locked <= sub_wire9;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "0",
clk1_divide_by => 1,
clk1_duty_cycle => 50,
clk1_multiply_by => 6,
clk1_phase_shift => "-3000",
clk2_divide_by => 1,
clk2_duty_cycle => 50,
clk2_multiply_by => 6,
clk2_phase_shift => "0",
clk3_divide_by => 2,
clk3_duty_cycle => 50,
clk3_multiply_by => 5,
clk3_phase_shift => "0",
clk4_divide_by => 29,
clk4_duty_cycle => 50,
clk4_multiply_by => 60,
clk4_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 62500,
intended_device_family => "MAX 10",
lpm_hint => "CBX_MODULE_PREFIX=max10_pll1",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_USED",
port_clk4 => "PORT_USED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "ON",
width_clock => 5
)
PORT MAP (
areset => areset,
inclk => sub_wire1,
clk => sub_wire3,
locked => sub_wire9
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "29"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "16.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "96.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "96.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "40.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "33.103447"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "16.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "60"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "16.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "96.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "96.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "40.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-3.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "ps"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "max10_pll1.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK4 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA4 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "6"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-3000"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "6"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "29"
-- Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "60"
-- Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "62500"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
-- Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
-- Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL max10_pll1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL max10_pll1.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL max10_pll1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL max10_pll1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL max10_pll1.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL max10_pll1_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
| gpl-3.0 | 947fd6533489a6ab4509447ffa560471 | 0.700089 | 3.230127 | false | false | false | false |
DreamIP/GPStudio | support/process/fast/hdl/components/neighExtractor.vhd | 1 | 6,969 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.fast_types.all;
entity neighExtractor is
generic(
PIXEL_SIZE : integer;
IMAGE_WIDTH : integer;
KERNEL_SIZE : integer
);
port(
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
in_data : in std_logic_vector((PIXEL_SIZE-1) downto 0);
in_dv : in std_logic;
in_fv : in std_logic;
out_data : out pixel_array (0 to (KERNEL_SIZE * KERNEL_SIZE)- 1);
out_dv : out std_logic;
out_fv : out std_logic
);
end neighExtractor;
architecture rtl of neighExtractor is
-- signals
signal pixel_out : pixel_array(0 to KERNEL_SIZE-1);
-- components
component taps
generic (
PIXEL_SIZE : integer;
TAPS_WIDTH : integer;
KERNEL_SIZE : integer
);
port (
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
in_data : in std_logic_vector (PIXEL_SIZE-1 downto 0);
taps_data : out pixel_array (0 to KERNEL_SIZE -1 );
out_data : out std_logic_vector (PIXEL_SIZE-1 downto 0)
);
end component;
component bit_taps
generic (
TAPS_WIDTH : integer
);
port (
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
in_data : in std_logic;
out_data : out std_logic
);
end component;
signal all_valid : std_logic;
signal s_valid : std_logic;
signal tmp_dv : std_logic;
signal tmp_fv : std_logic;
begin
-- All valid : Logic and
all_valid <= in_dv and in_fv;
s_valid <= all_valid and enable;
----------------------------------------------------
-- SUPER FOR GENERATE : GO
----------------------------------------------------
taps_inst : for i in 0 to KERNEL_SIZE-1 generate
-- First line
gen_1 : if i=0 generate
gen1_inst : taps
generic map(
PIXEL_SIZE => PIXEL_SIZE,
TAPS_WIDTH => IMAGE_WIDTH ,
KERNEL_SIZE => KERNEL_SIZE
)
port map(
clk => clk,
reset_n => reset_n,
enable => s_valid,
in_data => in_data,
taps_data => out_data(0 to KERNEL_SIZE-1),
out_data => pixel_out(0)
);
end generate gen_1;
-- line i
gen_i : if i>0 and i<KERNEL_SIZE-1 generate
geni_inst : taps
generic map(
PIXEL_SIZE => PIXEL_SIZE,
TAPS_WIDTH => IMAGE_WIDTH,
KERNEL_SIZE => KERNEL_SIZE
)
port map(
clk => clk,
reset_n => reset_n,
enable => s_valid,
in_data => pixel_out(i-1),
taps_data => out_data(i * KERNEL_SIZE to KERNEL_SIZE*(i+1)-1),
out_data => pixel_out(i)
);
end generate gen_i;
-- Last line
gen_last : if i= (KERNEL_SIZE-1) generate
gen_last_inst : taps
generic map(
PIXEL_SIZE => PIXEL_SIZE,
TAPS_WIDTH => KERNEL_SIZE,
KERNEL_SIZE => KERNEL_SIZE
)
port map(
clk => clk,
reset_n => reset_n,
enable => s_valid,
in_data => pixel_out(i-1),
taps_data => out_data((KERNEL_SIZE-1) * KERNEL_SIZE to KERNEL_SIZE*KERNEL_SIZE - 1),
out_data => OPEN
);
end generate gen_last;
end generate taps_inst;
--------------------------------------------------------------------------
-- Manage out_dv and out_fv
--------------------------------------------------------------------------
dv_proc : process(clk)
-- 12 bits is enought to count until 4096
constant NBITS_DELAY : integer := 20;
variable delay_cmp : unsigned (NBITS_DELAY-1 downto 0) :=(others => '0');
variable edge_cmp : unsigned (NBITS_DELAY-1 downto 0) :=(others => '0');
begin
if (reset_n = '0') then
delay_cmp := (others => '0');
edge_cmp := (others => '0');
tmp_dv <='0';
tmp_fv <='0';
elsif (rising_edge(clk)) then
if(enable = '1') then
if (in_fv = '1') then
if(in_dv = '1') then
-- Initial delay : Wait until there is data in all the taps
if (delay_cmp >= to_unsigned((KERNEL_SIZE-1)*IMAGE_WIDTH + KERNEL_SIZE - 1 , NBITS_DELAY)) then
-- Taps are full : Frame can start
tmp_fv <= '1';
if ( edge_cmp > to_unsigned (IMAGE_WIDTH - KERNEL_SIZE, NBITS_DELAY)) then
-- If at edge : data is NOT valid
if ( edge_cmp = to_unsigned (IMAGE_WIDTH - 1, NBITS_DELAY)) then
edge_cmp := (others => '0');
tmp_dv <= '0';
else
edge_cmp := edge_cmp + to_unsigned(1,NBITS_DELAY);
tmp_dv <= '0';
end if;
-- Else : Data is valid
else
edge_cmp := edge_cmp + to_unsigned(1,NBITS_DELAY);
tmp_dv <= '1';
end if;
-- When taps are nor full : Frame is not valid , neither is data
else
delay_cmp := delay_cmp + to_unsigned(1,NBITS_DELAY);
tmp_dv <= '0';
tmp_fv <= '0';
end if;
else
tmp_dv <= '0';
end if;
-- When Fv = 0 (New frame comming): reset counters
else
delay_cmp := (others => '0');
edge_cmp := (others => '0');
tmp_dv <= '0';
tmp_fv <= '0';
end if;
-- When enable = 0
else
delay_cmp := (others => '0');
edge_cmp := (others => '0');
tmp_dv <= '0';
tmp_fv <= '0';
end if;
end if;
end process;
out_dv <= tmp_dv;
out_fv <= tmp_fv;
end architecture;
| gpl-3.0 | 8fc2e7773d40f7fe169ac3f7d3a755f3 | 0.399196 | 4.077823 | false | false | false | false |
DreamIP/GPStudio | support/process/dilate/hdl/dilate_process.vhd | 1 | 6,399 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity dilate_process is
generic (
LINE_WIDTH_MAX : integer;
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : in std_logic;
widthimg_reg_value : in std_logic_vector(15 downto 0);
di00_reg_m00 : in std_logic_vector(7 downto 0);
di01_reg_m01 : in std_logic_vector(7 downto 0);
di02_reg_m02 : in std_logic_vector(7 downto 0);
di10_reg_m10 : in std_logic_vector(7 downto 0);
di11_reg_m11 : in std_logic_vector(7 downto 0);
di12_reg_m12 : in std_logic_vector(7 downto 0);
di20_reg_m20 : in std_logic_vector(7 downto 0);
di21_reg_m21 : in std_logic_vector(7 downto 0);
di22_reg_m22 : in std_logic_vector(7 downto 0);
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic
);
end dilate_process;
architecture rtl of dilate_process is
component matrix_extractor
generic (
LINE_WIDTH_MAX : integer;
PIX_WIDTH : integer;
OUTVALUE_WIDTH : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- in flow -----------------------
in_data : in std_logic_vector((PIX_WIDTH-1) downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector((PIX_WIDTH-1) downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
------------------------ matrix out ---------------------
p00, p01, p02 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p10, p11, p12 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p20, p21, p22 : out std_logic_vector((PIX_WIDTH-1) downto 0);
matrix_dv : out std_logic;
---------------------- computed value -------------------
value_data : in std_logic_vector((PIX_WIDTH-1) downto 0);
value_dv : in std_logic;
------------------------- params ------------------------
enable_i : in std_logic;
widthimg_i : in std_logic_vector(15 downto 0)
);
end component;
-- neighbors extraction
signal p00, p01, p02 : std_logic_vector((IN_SIZE-1) downto 0);
signal p10, p11, p12 : std_logic_vector((IN_SIZE-1) downto 0);
signal p20, p21, p22 : std_logic_vector((IN_SIZE-1) downto 0);
signal matrix_dv : std_logic;
-- Dilation matrix
-- 0 1 0 d00 d01 d02
-- 1 1 1 d10 d11 d12
-- 0 1 0 d20 d21 d22
signal d00, d01, d02 : unsigned((IN_SIZE-1) downto 0);
signal d10, d11, d12 : unsigned((IN_SIZE-1) downto 0);
signal d20, d21, d22 : unsigned((IN_SIZE-1) downto 0);
-- parsing back from value to flow
signal value_data : std_logic_vector((IN_SIZE-1) downto 0);
signal value_dv : std_logic;
signal out_fv_s : std_logic;
signal enable_s : std_logic;
signal dilate_dv : std_logic;
begin
matrix_extractor_inst : matrix_extractor
generic map (
LINE_WIDTH_MAX => LINE_WIDTH_MAX,
PIX_WIDTH => IN_SIZE,
OUTVALUE_WIDTH => IN_SIZE
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
in_data => in_data,
in_fv => in_fv,
in_dv => in_dv,
p00 => p00, p01 => p01, p02 => p02,
p10 => p10, p11 => p11, p12 => p12,
p20 => p20, p21 => p21, p22 => p22,
matrix_dv => matrix_dv,
value_data => value_data,
value_dv => value_dv,
out_data => out_data,
out_fv => out_fv_s,
out_dv => out_dv,
enable_i => status_reg_enable_bit,
widthimg_i => widthimg_reg_value
);
data_process : process (clk_proc, reset_n, matrix_dv)
variable val : unsigned((IN_SIZE-1) downto 0);
begin
if(reset_n='0') then
enable_s <= '0';
dilate_dv <= '0';
value_dv <= '0';
elsif(rising_edge(clk_proc)) then
-- Waiting for an image flow
if(in_fv = '0') then
-- Update params here, between two images processing
enable_s <= status_reg_enable_bit;
d00 <= unsigned(di00_reg_m00);
d01 <= unsigned(di01_reg_m01);
d02 <= unsigned(di02_reg_m02);
d10 <= unsigned(di10_reg_m10);
d11 <= unsigned(di11_reg_m11);
d12 <= unsigned(di12_reg_m12);
d20 <= unsigned(di20_reg_m20);
d21 <= unsigned(di21_reg_m21);
d22 <= unsigned(di22_reg_m22);
value_dv <= '0';
end if;
-- A matrix is available to process
dilate_dv <= '0';
if(matrix_dv = '1' and enable_s = '1') then
val := (others => '0');
--
if(d00 /=0) then
if(val<unsigned(p00)) then
val := unsigned(p00);
end if;
end if;
--
if(d01 /=0) then
if(val<unsigned(p01)) then
val := unsigned(p01);
end if;
end if;
--
if(d02 /=0) then
if(val<unsigned(p02)) then
val := unsigned(p02);
end if;
end if;
--
if(d10 /=0) then
if(val<unsigned(p10)) then
val := unsigned(p10);
end if;
end if;
--
if(d11 /=0) then
if(val<unsigned(p11)) then
val := unsigned(p11);
end if;
end if;
--
if(d12 /=0) then
if(val<unsigned(p12)) then
val := unsigned(p12);
end if;
end if;
--
if(d20 /=0) then
if(val<unsigned(p20)) then
val := unsigned(p20);
end if;
end if;
--
if(d21 /=0) then
if(val<unsigned(p21)) then
val := unsigned(p21);
end if;
end if;
--
if(d22 /=0) then
if(val<unsigned(p22)) then
val := unsigned(p22);
end if;
end if;
dilate_dv <= '1';
end if;
-- Matrix process has ended
if(enable_s = '1' and dilate_dv = '1') then
value_data <= std_logic_vector(val)(OUT_SIZE -1 downto 0);
value_dv <= '1';
else
value_dv <= '0';
end if;
end if;
end process;
out_fv <= enable_s and out_fv_s;
end rtl;
| gpl-3.0 | 133b89a37abb1ddf297c0fcfc4e06659 | 0.524926 | 2.864369 | false | false | false | false |
INTI-CMNB-FPGA/fpga_lib | vhdl/numeric/testbench/numeric_tb.vhdl | 1 | 5,137 | --
-- Numeric testbench
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2016-2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library FPGALIB;
use FPGALIB.Numeric.all;
use FPGALIB.Simul.all;
entity Numeric_tb is
end entity Numeric_tb;
architecture Testbench of Numeric_tb is
begin
test: process
begin
print("* Testing minimum and maximum");
assert minimum(2,9)=2 report "minimum fail" severity failure;
assert maximum(2,9)=9 report "maximum fail" severity failure;
print("* Testing clog2");
assert clog2(1)=0 report "clog2(1) fail" severity failure;
assert clog2(2)=1 report "clog2(2) fail" severity failure;
assert clog2(3)=2 report "clog2(3) fail" severity failure;
assert clog2(4)=2 report "clog2(4) fail" severity failure;
assert clog2(5)=3 report "clog2(5) fail" severity failure;
assert clog2(6)=3 report "clog2(6) fail" severity failure;
assert clog2(7)=3 report "clog2(7) fail" severity failure;
assert clog2(8)=3 report "clog2(8) fail" severity failure;
assert clog2(9)=4 report "clog2(9) fail" severity failure;
assert clog2(1e3)=10 report "clog2(1e3) fail" severity failure;
assert clog2(1e4)=14 report "clog2(1e4) fail" severity failure;
assert clog2(1e5)=17 report "clog2(1e5) fail" severity failure;
assert clog2(1e9)=30 report "clog2(1e9) fail" severity failure;
print("* Testing convesions");
assert to_integer("00001001")=9 report "to_integer of 00001001 must be 9" severity failure;
assert to_integer('1')=1 report "to_integer of 1 must be 1" severity failure;
assert to_natural("00001001")=9 report "to_natural of 00001001 must be 9" severity failure;
assert to_logic(1)='1' report "to_logic of 1 must be 1" severity failure;
assert to_vector(9,8)="00001001" report "to_vector of 9 must be 00001001" severity failure;
print("* Testing Binary to Gray convesion");
assert bin2gray("0000")="0000" report "bin 0000 must be gray 0000" severity failure;
assert bin2gray("0001")="0001" report "bin 0001 must be gray 0001" severity failure;
assert bin2gray("0010")="0011" report "bin 0010 must be gray 0011" severity failure;
assert bin2gray("0011")="0010" report "bin 0011 must be gray 0010" severity failure;
assert bin2gray("0100")="0110" report "bin 0100 must be gray 0110" severity failure;
assert bin2gray("0101")="0111" report "bin 0101 must be gray 0111" severity failure;
assert bin2gray("0110")="0101" report "bin 0110 must be gray 0101" severity failure;
assert bin2gray("0111")="0100" report "bin 0111 must be gray 0100" severity failure;
assert bin2gray("1000")="1100" report "bin 1000 must be gray 1100" severity failure;
assert bin2gray("1001")="1101" report "bin 1001 must be gray 1101" severity failure;
assert bin2gray("1010")="1111" report "bin 1010 must be gray 1111" severity failure;
assert bin2gray("1011")="1110" report "bin 1011 must be gray 1110" severity failure;
assert bin2gray("1100")="1010" report "bin 1100 must be gray 1100" severity failure;
assert bin2gray("1101")="1011" report "bin 1101 must be gray 1101" severity failure;
assert bin2gray("1110")="1001" report "bin 1110 must be gray 1110" severity failure;
assert bin2gray("1111")="1000" report "bin 1111 must be gray 1000" severity failure;
print("* Testing Gray to Binary convesion");
assert gray2bin("0000")="0000" report "bin 0000 must be gray 0000" severity failure;
assert gray2bin("0001")="0001" report "bin 0001 must be gray 0001" severity failure;
assert gray2bin("0011")="0010" report "bin 0011 must be gray 0010" severity failure;
assert gray2bin("0010")="0011" report "bin 0010 must be gray 0011" severity failure;
assert gray2bin("0110")="0100" report "bin 0110 must be gray 0100" severity failure;
assert gray2bin("0111")="0101" report "bin 0111 must be gray 0101" severity failure;
assert gray2bin("0101")="0110" report "bin 0101 must be gray 0110" severity failure;
assert gray2bin("0100")="0111" report "bin 0100 must be gray 0111" severity failure;
assert gray2bin("1100")="1000" report "bin 1100 must be gray 0000" severity failure;
assert gray2bin("1101")="1001" report "bin 1101 must be gray 0001" severity failure;
assert gray2bin("1111")="1010" report "bin 1111 must be gray 0010" severity failure;
assert gray2bin("1110")="1011" report "bin 1110 must be gray 0011" severity failure;
assert gray2bin("1010")="1100" report "bin 1010 must be gray 0100" severity failure;
assert gray2bin("1011")="1101" report "bin 1011 must be gray 0101" severity failure;
assert gray2bin("1001")="1110" report "bin 1001 must be gray 0110" severity failure;
assert gray2bin("1000")="1111" report "bin 1000 must be gray 0111" severity failure;
wait;
end process test;
end architecture Testbench;
| bsd-3-clause | 7d32516f1d0128d2b350ea707c3961f7 | 0.683668 | 3.719768 | false | true | false | false |
DreamIP/GPStudio | support/io/eth_marvell_88e1111/hdl/RGMII_MAC/rgmii1000_io.vhd | 1 | 4,165 | -------------------------------------------------------------------------------
-- Title :
-- Project :
-------------------------------------------------------------------------------
-- File : rgmii_io.vhd
-- Author : liyi <[email protected]>
-- Company : OE@HUST
-- Created : 2012-10-26
-- Last update: 2013-05-15
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012 OE@HUST
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-10-26 1.0 liyi Created
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
-------------------------------------------------------------------------------
ENTITY rgmii1000_io IS
PORT (
iRst_n : IN STD_LOGIC;
---------------------------------------------------------------------------
-- RGMII Interface
---------------------------------------------------------------------------
TXC : OUT STD_LOGIC;
TX_CTL : OUT STD_LOGIC;
TD : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
RXC : IN STD_LOGIC;
RX_CTL : IN STD_LOGIC;
RD : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
---------------------------------------------------------------------------
-- data to PHY
---------------------------------------------------------------------------
iTxData : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
iTxEn : IN STD_LOGIC;
iTxErr : IN STD_LOGIC;
---------------------------------------------------------------------------
-- data from PHY
---------------------------------------------------------------------------
oRxData : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
oRxDV : OUT STD_LOGIC;
oRxErr : OUT STD_LOGIC;
---------------------------------------------------------------------------
-- clock for MAC controller
---------------------------------------------------------------------------
oEthClk : OUT STD_LOGIC
);
END ENTITY rgmii1000_io;
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF rgmii1000_io IS
SIGNAL ethIOClk, ethIOClk_ddout : STD_LOGIC;
SIGNAL outDataH, outDataL, outData : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL inDataH, inDataL, inData : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL pllLock : STD_LOGIC;
SIGNAL rstSync : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL rst_n : STD_LOGIC;
SIGNAL bufClk : STD_LOGIC;
SIGNAL ripple : BOOLEAN;
TYPE rxState_t IS (IDLE, RECEIVE);
SIGNAL rxState : rxState_t;
SIGNAL rxData : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL rxErr, rxDV : STD_LOGIC;
SIGNAL tmp : STD_LOGIC;
SIGNAL rxData2 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL rxErr2, rxDV2 : STD_LOGIC;
SIGNAL rdreq,wrreq : STD_LOGIC;
SIGNAL rdempty : STD_LOGIC;
SIGNAL din,dout : STD_LOGIC_VECTOR(9 DOWNTO 0);
signal clk_250M_stap_int : std_logic;
BEGIN -- ARCHITECTURE rtl
oEthClk <= ethIOClk;
--oEthClk <= RXC;
TXC <= RXC;
pll: entity work.rgmii1000_pll
PORT map
(
inclk0 => RXC,
c0 => ethIOClk,
c1 => clk_250M_stap_int
--c2 => ethIOClk_ddout
);
TD <= outData(3 DOWNTO 0);
TX_CTL <= outData(4);
outDataH <= iTxEn & iTxData(3 DOWNTO 0);
outDataL <= (iTxEn XOR iTxErr) & iTxData(7 DOWNTO 4);
eth_ddr_out_1 : ENTITY work.eth_ddr_out
PORT MAP (
datain_h => outDataH,
datain_l => outDataL,
outclock => ethIOClk,
dataout => outData);
inData <= RX_CTL & RD;
oRxDV <= inDataL(4);
oRxErr <= inDataH(4) XOR inDataL(4);
oRxData <= inDataH(3 DOWNTO 0) & inDataL(3 DOWNTO 0);
eth_ddr_in_1 : ENTITY work.eth_ddr_in
PORT MAP (
datain => inData,
inclock => ethIOClk, -- shift 180~360 degree compared to RXC
dataout_h => inDataH,
dataout_l => inDataL);
END ARCHITECTURE rtl;
| gpl-3.0 | ade69600875b7493601cc296633255b1 | 0.420648 | 4.267418 | false | false | false | false |
INTI-CMNB-FPGA/fpga_lib | vhdl/sync/sync_pkg.vhdl | 1 | 2,908 | --
-- Sync Package
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2015-2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--! Blocks to synchronize, such as FFs chains, frequency divisors and blocks for CDC.
package Sync is
component FFchain is
generic(
WIDTH : positive:=8;
DEPTH : positive:=2
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
ena_i : in std_logic;
data_i : in std_logic_vector(WIDTH-1 downto 0);
data_o : out std_logic_vector(WIDTH-1 downto 0)
);
end component FFchain;
component Gray_Sync is
generic(
WIDTH : positive:=8;
DEPTH : positive:=2
);
port(
clk_i : in std_logic;
data_i : in unsigned(WIDTH-1 downto 0);
data_o : out unsigned(WIDTH-1 downto 0)
);
end component Gray_Sync;
component Divider is
generic(
DIV : positive range 2 to positive'high:=2
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
ena_i : in std_logic:='1';
ena_o : out std_logic
);
end component Divider;
component Debounce is
generic(
FREQUENCY : positive:=50e6;
DEB_TIME : real:=50.0e-3
);
port(
clk_i : in std_logic;
deb_i : in std_logic;
deb_o : out std_logic
);
end component Debounce;
component SyncClockDomainsBase is
generic(
INBYLEVEL : boolean:=FALSE;
FFSTAGES : natural:= 2
);
port(
rst_i : in std_logic;
clka_i : in std_logic;
clkb_i : in std_logic;
a_i : in std_logic;
b_o : out std_logic;
ack_o : out std_logic
);
end component SyncClockDomainsBase;
component SyncClockDomains is
generic(
INBYLEVEL : boolean:=FALSE;
FFSTAGES : natural:= 2;
CHANNELS : positive:= 1
);
port(
rst_i : in std_logic;
clkA_i : in std_logic;
clkB_i : in std_logic;
a_i : in std_logic_vector(CHANNELS-1 downto 0);
b_o : out std_logic_vector(CHANNELS-1 downto 0);
ack_o : out std_logic_vector(CHANNELS-1 downto 0));
end component SyncClockDomains;
component Boundary is
generic(
BYTES : positive:=4
);
port(
clk_i : in std_logic;
pattern_i : in std_logic_vector(BYTES-1 downto 0);
comma_i : in std_logic_vector(BYTES-1 downto 0);
data_i : in std_logic_vector(BYTES*8-1 downto 0);
comma_o : out std_logic_vector(BYTES-1 downto 0);
data_o : out std_logic_vector(BYTES*8-1 downto 0)
);
end component Boundary;
end package Sync;
| bsd-3-clause | 60e621b0db2e24a7e1bf27f45a8d890c | 0.53989 | 3.524848 | false | false | false | false |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/niosII_microc_lab1/niosII_microc_lab1.vhd | 2 | 8,266 | -- Nancy Minderman
-- [email protected]
-- This file makes extensive use of Altera template structures.
-- This file is the top-level file for lab 1 winter 2014 for version 12.1sp1 on Windows 7
-- A library clause declares a name as a library. It
-- does not create the library; it simply forward declares
-- it.
library ieee;
-- Commonly imported packages:
-- STD_LOGIC and STD_LOGIC_VECTOR types, and relevant functions
use ieee.std_logic_1164.all;
-- SIGNED and UNSIGNED types, and relevant functions
use ieee.numeric_std.all;
-- Basic sequential functions and concurrent procedures
use ieee.VITAL_Primitives.all;
use work.DE2_CONSTANTS.all;
entity niosII_microc_lab1 is
port
(
-- Input ports and 50 MHz Clock
KEY : in std_logic_vector (0 downto 0);
SW : in std_logic_vector (0 downto 0);
CLOCK_50 : in std_logic;
-- Green leds on board
LEDG : out DE2_LED_GREEN;
-- LCD on board
LCD_BLON : out std_logic;
LCD_ON : out std_logic;
LCD_DATA : inout DE2_LCD_DATA_BUS;
LCD_RS : out std_logic;
LCD_EN : out std_logic;
LCD_RW : out std_logic;
-- SDRAM on board
--DRAM_ADDR : out std_logic_vector (11 downto 0);
DRAM_ADDR : out DE2_SDRAM_ADDR_BUS;
DRAM_BA_0 : out std_logic;
DRAM_BA_1 : out std_logic;
DRAM_CAS_N : out std_logic;
DRAM_CKE : out std_logic;
DRAM_CLK : out std_logic;
DRAM_CS_N : out std_logic;
--DRAM_DQ : inout std_logic_vector (15 downto 0);
DRAM_DQ : inout DE2_SDRAM_DATA_BUS;
DRAM_LDQM : out std_logic;
DRAM_UDQM : out std_logic;
DRAM_RAS_N : out std_logic;
DRAM_WE_N : out std_logic;
-- SRAM on board
SRAM_ADDR : out DE2_SRAM_ADDR_BUS;
SRAM_DQ : inout DE2_SRAM_DATA_BUS;
SRAM_WE_N : out std_logic;
SRAM_OE_N : out std_logic;
SRAM_UB_N : out std_logic;
SRAM_LB_N : out std_logic;
SRAM_CE_N : out std_logic
);
end niosII_microc_lab1;
architecture structure of niosII_microc_lab1 is
-- Declarations (optional)
component niosII_system is
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
sdram_0_wire_addr : out DE2_SDRAM_ADDR_BUS; -- addr
sdram_0_wire_ba : out std_logic_vector(1 downto 0); -- ba
sdram_0_wire_cas_n : out std_logic; -- cas_n
sdram_0_wire_cke : out std_logic; -- cke
sdram_0_wire_cs_n : out std_logic; -- cs_n
sdram_0_wire_dq : inout DE2_SDRAM_DATA_BUS := (others => 'X'); -- dq
sdram_0_wire_dqm : out std_logic_vector(1 downto 0); -- dqm
sdram_0_wire_ras_n : out std_logic; -- ras_n
sdram_0_wire_we_n : out std_logic; -- we_n
altpll_0_c0_clk : out std_logic; -- clk
green_leds_external_connection_export : out DE2_LED_GREEN; -- export
switch_external_connection_export : in std_logic := 'X'; -- export
sram_0_external_interface_DQ : inout DE2_SRAM_DATA_BUS := (others => 'X'); -- DQ
sram_0_external_interface_ADDR : out DE2_SRAM_ADDR_BUS; -- ADDR
sram_0_external_interface_LB_N : out std_logic; -- LB_N
sram_0_external_interface_UB_N : out std_logic; -- UB_N
sram_0_external_interface_CE_N : out std_logic; -- CE_N
sram_0_external_interface_OE_N : out std_logic; -- OE_N
sram_0_external_interface_WE_N : out std_logic; -- WE_N
character_lcd_0_external_interface_DATA : inout DE2_LCD_DATA_BUS := (others => 'X'); -- DATA
character_lcd_0_external_interface_ON : out std_logic; -- ON
character_lcd_0_external_interface_BLON : out std_logic; -- BLON
character_lcd_0_external_interface_EN : out std_logic; -- EN
character_lcd_0_external_interface_RS : out std_logic; -- RS
character_lcd_0_external_interface_RW : out std_logic -- RW
);
end component niosII_system;
-- These signals are for matching the provided IP core to
-- The specific SDRAM chip in our system
signal BA : std_logic_vector (1 downto 0);
signal DQM : std_logic_vector (1 downto 0);
begin
DRAM_BA_1 <= BA(1);
DRAM_BA_0 <= BA(0);
DRAM_UDQM <= DQM(1);
DRAM_LDQM <= DQM(0);
-- Component Instantiation Statement (optional)
u0 : component niosII_system
port map (
clk_clk => CLOCK_50,
reset_reset_n => KEY(0),
sdram_0_wire_addr => DRAM_ADDR,
sdram_0_wire_ba => BA,
sdram_0_wire_cas_n => DRAM_CAS_N,
sdram_0_wire_cke => DRAM_CKE,
sdram_0_wire_cs_n => DRAM_CS_N,
sdram_0_wire_dq => DRAM_DQ,
sdram_0_wire_dqm => DQM,
sdram_0_wire_ras_n => DRAM_RAS_N,
sdram_0_wire_we_n => DRAM_WE_N,
altpll_0_c0_clk => DRAM_CLK,
green_leds_external_connection_export => LEDG,
switch_external_connection_export => SW(0),
sram_0_external_interface_DQ => SRAM_DQ,
sram_0_external_interface_ADDR => SRAM_ADDR,
sram_0_external_interface_LB_N => SRAM_LB_N,
sram_0_external_interface_UB_N => SRAM_UB_N,
sram_0_external_interface_CE_N => SRAM_CE_N,
sram_0_external_interface_OE_N => SRAM_OE_N,
sram_0_external_interface_WE_N => SRAM_WE_N,
character_lcd_0_external_interface_DATA => LCD_DATA,
character_lcd_0_external_interface_ON => LCD_ON,
character_lcd_0_external_interface_BLON => LCD_BLON,
character_lcd_0_external_interface_EN => LCD_EN,
character_lcd_0_external_interface_RS => LCD_RS,
character_lcd_0_external_interface_RW => LCD_RW
);
end structure;
library ieee;
-- Commonly imported packages:
-- STD_LOGIC and STD_LOGIC_VECTOR types, and relevant functions
use ieee.std_logic_1164.all;
package DE2_CONSTANTS is
type DE2_SDRAM_ADDR_BUS is array(11 downto 0) of std_logic;
type DE2_SDRAM_DATA_BUS is array(15 downto 0) of std_logic;
type DE2_LCD_DATA_BUS is array(7 downto 0) of std_logic;
type DE2_LED_GREEN is array(7 downto 0) of std_logic;
type DE2_SRAM_ADDR_BUS is array(17 downto 0) of std_logic;
type DE2_SRAM_DATA_BUS is array(15 downto 0) of std_logic;
end DE2_CONSTANTS;
| gpl-2.0 | 11c67efa553818cda1b6de19b5527248 | 0.465521 | 3.73689 | false | false | false | false |
DreamIP/GPStudio | support/io/eth_marvell_88e1111/hdl/IP/IPv4.vhd | 1 | 6,502 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 16:20:42 06/01/2011
-- Design Name:
-- Module Name: IPv4 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle simple IP RX and TX
-- doesnt handle seg & reass
-- dest MAC addr resolution through ARP layer
-- Handle IPv4 protocol
-- Respond to ARP requests and replies
-- Ignore pkts that are not IP
-- Ignore pkts that are not addressed to us--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - separated RX and TX clocks
-- Revision 0.03 - Added mac_data_out_first
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
entity IPv4 is
Port (
-- IP Layer signals
ip_tx_start : in std_logic;
ip_tx : in ipv4_tx_type; -- IP tx cxns
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
ip_rx_start : out std_logic; -- indicates receipt of ip frame.
ip_rx : out ipv4_rx_type;
-- system control signals
rx_clk : in STD_LOGIC;
tx_clk : in STD_LOGIC;
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
-- system status signals
rx_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
-- ARP lookup signals
arp_req_req : out arp_req_req_type;
arp_req_rslt : in arp_req_rslt_type;
-- MAC layer RX signals
mac_data_in : in STD_LOGIC_VECTOR (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
mac_data_in_valid : in STD_LOGIC; -- indicates data_in valid on clock
mac_data_in_first : in STD_LOGIC;
mac_data_in_last : in STD_LOGIC; -- indicates last data in frame
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
mac_data_out_ready : in std_logic; -- indicates system ready to consume data
mac_data_out_valid : out std_logic; -- indicates data out is valid
mac_data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
mac_data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
mac_data_out : out std_logic_vector (7 downto 0) -- ethernet frame (from dst mac addr through to last byte of frame)
);
end IPv4;
architecture structural of IPv4 is
COMPONENT IPv4_TX
PORT(
-- IP Layer signals
ip_tx_start : in std_logic;
ip_tx : in ipv4_tx_type; -- IP tx cxns
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
-- system signals
clk : in STD_LOGIC; -- same clock used to clock mac data and ip data
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
-- ARP lookup signals
arp_req_req : out arp_req_req_type;
arp_req_rslt : in arp_req_rslt_type;
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
mac_data_out_ready : in std_logic; -- indicates system ready to consume data
mac_data_out_valid : out std_logic; -- indicates data out is valid
mac_data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
mac_data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
mac_data_out : out std_logic_vector (7 downto 0) -- ethernet frame (from dst mac addr through to last byte of frame)
);
END COMPONENT;
COMPONENT IPv4_RX
PORT(
-- IP Layer signals
ip_rx : out ipv4_rx_type;
ip_rx_start : out std_logic; -- indicates receipt of ip frame.
-- system signals
clk : in STD_LOGIC;
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
rx_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
-- MAC layer RX signals
mac_data_in : in STD_LOGIC_VECTOR (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
mac_data_in_valid : in STD_LOGIC; -- indicates data_in valid on clock
mac_data_in_first : in STD_LOGIC;
mac_data_in_last : in STD_LOGIC -- indicates last data in frame
);
END COMPONENT;
begin
TX : IPv4_TX PORT MAP (
ip_tx_start => ip_tx_start,
ip_tx => ip_tx,
ip_tx_result => ip_tx_result,
ip_tx_data_out_ready=> ip_tx_data_out_ready,
clk => tx_clk,
reset => reset,
our_ip_address => our_ip_address,
our_mac_address => our_mac_address,
arp_req_req => arp_req_req,
arp_req_rslt => arp_req_rslt,
mac_tx_req => mac_tx_req,
mac_tx_granted => mac_tx_granted,
mac_data_out_ready => mac_data_out_ready,
mac_data_out_valid => mac_data_out_valid,
mac_data_out_first => mac_data_out_first,
mac_data_out_last => mac_data_out_last,
mac_data_out => mac_data_out
);
RX : IPv4_RX PORT MAP (
ip_rx => ip_rx,
ip_rx_start => ip_rx_start,
clk => rx_clk,
reset => reset,
our_ip_address => our_ip_address,
rx_pkt_count => rx_pkt_count,
mac_data_in => mac_data_in,
mac_data_in_valid => mac_data_in_valid,
mac_data_in_first => mac_data_in_first,
mac_data_in_last => mac_data_in_last
);
end structural;
| gpl-3.0 | ad3e2544b17651d3330d0444bfc057f4 | 0.587512 | 3.115477 | false | false | false | false |
DreamIP/GPStudio | support/toolchain/caph/hdl/caph_lib/stream_in.vhd | 1 | 2,869 | -----------------------------------------------------------------------------------------
-- --
-- This file is part of the CAPH Compiler distribution --
-- http://caph.univ-bpclermont.fr --
-- --
-- Jocelyn SEROT --
-- [email protected] --
-- --
-- Copyright 2011-2015 Jocelyn SEROT. All rights reserved. --
-- This file is distributed under the terms of the GNU Library General Public License --
-- with the special exception on linking described in file ../LICENSE. --
-- --
-----------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
entity stream_in is
generic ( filename: string := "input.bin"; size: integer := 10; period: integer := 1; blanking: boolean := false );
port ( full : in std_logic;
dout : out std_logic_vector(size-1 downto 0);
wr : out std_logic;
clk : in std_logic;
rst : in std_logic
);
end stream_in;
architecture beh of stream_in is
begin
process
file input_file: text;
variable file_line: line;
variable line_out: line;
variable data: bit_vector(size-1 downto 0);
begin
if ( period < 1 ) then
report "stream_in(" & filename & ") : period < 1 !"
severity error;
end if;
wr <= '0';
file_open(input_file,filename,READ_MODE);
while not endfile(input_file) loop
readline (input_file,file_line);
read (file_line,data) ;
wait until rising_edge(clk);
for i in 0 to period-2 loop
wr <= '0';
wait until rising_edge(clk);
end loop;
assert (full='0')
report "stream_in(" & filename & ") : cannot write: downstream fifo is full !"
severity warning;
if ( blanking = false or data(size-1 downto size-2) /= "00" ) then
-- Note 2014-10-08, JS
-- This conditionnal is a hack for implementing blanking :
-- Special tokens 00xxxxx are supposed to mean "NO DATA"
-- These tokens will be generated in the input .bin file by the [txt2bin] utility
dout <= to_stdlogicvector(data);
wr <= '1';
else
wr <= '0';
end if;
end loop;
wait until rising_edge(clk);
wr <= '0';
file_close(input_file);
wait;
end process;
end;
| gpl-3.0 | 69434c5fb84d88f7f226c22606a80327 | 0.446846 | 4.619968 | false | false | false | false |
DreamIP/GPStudio | support/io/gps/hdl/gps_pkg.vhd | 1 | 1,682 | --------------------------------------------------------------------
-- Package containing several constant data
--------------------------------------------------------------------
library ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package gps_pkg is
constant LEN_3 : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"03";
constant LEN_4 : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"04";
constant LEN_5 : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"05";
constant ZERO : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"00";
constant ID_MODE : STD_LOGIC_VECTOR(15 DOWNTO 0) := x"6419";
constant MODE_GPS : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"01";
constant MODE_GPS_GL : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"03";
constant ID_BAUD_RATE : STD_LOGIC_VECTOR(15 DOWNTO 0) := x"0500";
constant BAUD_RATE_MAX : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"08";
constant ID_UPDATE_RATE : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"0E";
constant UPDATE_RATE_MAX_GL : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"14";
constant START_BYTES : STD_LOGIC_VECTOR(15 DOWNTO 0) := x"A0A1";
constant END_BYTES : STD_LOGIC_VECTOR(15 DOWNTO 0) := x"0D0A";
constant RESTART : STD_LOGIC_VECTOR(143 DOWNTO 0) := x"00_0F_01_01_07_D8_0B_0E_08_2E_03_09_C4_30_70_00_64_16";
constant LEN_CONF_MODE : UNSIGNED(7 DOWNTO 0) := x"0C";
constant LEN_CONF_BD_RATE : UNSIGNED(7 DOWNTO 0) := x"0B";
constant LEN_CONF_UPDATE : UNSIGNED(7 DOWNTO 0) := x"0A";
constant LEN_CONF_RESTART : UNSIGNED(7 DOWNTO 0) := x"16";
constant COUNT_BD_RATE_DEFAULT : UNSIGNED(15 DOWNTO 0) := x"1458";
constant COUNT_BD_RATE_MAX : UNSIGNED(15 DOWNTO 0) := x"0035";
end gps_pkg;
| gpl-3.0 | 728796c940547e34de1d11b8c6e7bd27 | 0.585612 | 2.789386 | false | false | false | false |
hoglet67/ElectronFpga | AtomBusMon/src/MOS6502CpuMonALS.vhd | 1 | 5,697 | --------------------------------------------------------------------------------
-- Copyright (c) 2019 David Banks
--
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : MOS6502CpuMonALS.vhd
-- /___/ /\ Timestamp : 20/09/2019
-- \ \ / \
-- \___\/\___\
--
--Design Name: MOS6502CpuMonALS
--Device: XC6SLX9
--
--
-- This is a small wrapper around MOS6502CpuMon that add the following signals:
-- OEAH_n
-- OEAL_n
-- OED_n
-- DIRD
-- BE
-- ML_n
-- VP_n
-- (these are not fully implemented yet)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity MOS6502CpuMonALS is
generic (
UseT65Core : boolean := true;
UseAlanDCore : boolean := false;
num_comparators : integer := 8;
avr_prog_mem_size : integer := 8 * 1024
);
port (
clock : in std_logic;
-- 6502 Signals
PhiIn : in std_logic;
Phi1Out : out std_logic;
Phi2Out : out std_logic;
IRQ_n : in std_logic;
NMI_n : in std_logic;
Sync : out std_logic;
Addr : out std_logic_vector(15 downto 0);
R_W_n : out std_logic_vector(1 downto 0);
Data : inout std_logic_vector(7 downto 0);
SO_n : in std_logic;
Res_n : in std_logic;
Rdy : in std_logic;
-- 65C02 Signals
BE : in std_logic;
ML_n : out std_logic;
VP_n : out std_logic;
-- Level Shifter Controls
OERW_n : out std_logic;
OEAH_n : out std_logic;
OEAL_n : out std_logic;
OED_n : out std_logic;
DIRD : out std_logic;
-- External trigger inputs
trig : in std_logic_vector(1 downto 0);
-- ID/mode inputs
mode : in std_logic;
id : in std_logic_vector(3 downto 0);
-- Serial Console
avr_RxD : in std_logic;
avr_TxD : out std_logic;
-- Switches
sw1 : in std_logic;
sw2 : in std_logic;
-- LEDs
led1 : out std_logic;
led2 : out std_logic;
led3 : out std_logic;
-- OHO_DY1 LED display
tmosi : out std_logic;
tdin : out std_logic;
tcclk : out std_logic
);
end MOS6502CpuMonALS;
architecture behavioral of MOS6502CpuMonALS is
signal R_W_n_int : std_logic;
signal sw_reset_cpu : std_logic;
signal sw_reset_avr : std_logic;
signal led_bkpt : std_logic;
signal led_trig0 : std_logic;
signal led_trig1 : std_logic;
signal PhiIn1 : std_logic;
signal PhiIn2 : std_logic;
signal PhiIn3 : std_logic;
signal PhiIn4 : std_logic;
begin
sw_reset_cpu <= not sw1;
sw_reset_avr <= not sw2;
led1 <= led_bkpt;
led2 <= led_trig0;
led3 <= led_trig1;
wrapper : entity work.MOS6502CpuMon
generic map (
UseT65Core => UseT65Core,
UseAlanDCore => UseAlanDCore,
ClkMult => 12,
ClkDiv => 25,
ClkPer => 20.000,
num_comparators => num_comparators,
avr_prog_mem_size => avr_prog_mem_size
)
port map (
clock => clock,
-- 6502 Signals
Phi0 => PhiIn,
Phi1 => Phi1Out,
Phi2 => Phi2Out,
IRQ_n => IRQ_n,
NMI_n => NMI_n,
Sync => Sync,
Addr => Addr,
R_W_n => R_W_n_int,
Data => Data,
SO_n => SO_n,
Res_n => Res_n,
Rdy => Rdy,
-- External trigger inputs
trig => trig,
-- Jumpers
fakeTube_n => '1',
-- Serial Console
avr_RxD => avr_RxD,
avr_TxD => avr_TxD,
-- Switches
sw_reset_cpu => sw_reset_cpu,
sw_reset_avr => sw_reset_avr,
-- LEDs
led_bkpt => led_bkpt,
led_trig0 => led_trig0,
led_trig1 => led_trig1,
-- OHO_DY1 LED display
tmosi => tmosi,
tdin => tdin,
tcclk => tcclk
);
-- 6502 Outputs
R_W_n <= R_W_n_int & R_W_n_int;
-- 65C02 Outputs
ML_n <= '1';
VP_n <= '1';
process(clock)
begin
if rising_edge(clock) then
PhiIn1 <= PhiIn;
PhiIn2 <= PhiIn1;
PhiIn3 <= PhiIn2;
PhiIn4 <= PhiIn3;
end if;
end process;
-- Level Shifter Controls
OERW_n <= '0'; -- not (BE);
OEAH_n <= '0'; -- not (BE);
OEAL_n <= '0'; -- not (BE);
OED_n <= not (BE and PhiIn and PhiIn4); -- TODO: might need to use a slightly delayed version of Phi2 here
DIRD <= R_W_n_int;
end behavioral;
| gpl-3.0 | 5a2a55cd7dc2977f288d27cd34400a00 | 0.402317 | 3.926258 | false | false | false | false |
hoglet67/ElectronFpga | AtomBusMon/src/Z80CpuMon.vhd | 1 | 24,058 | --------------------------------------------------------------------------------
-- Copyright (c) 2019 David Banks
--
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : Z80CpuMon.vhd
-- /___/ /\ Timestamp : 14/10/2018
-- \ \ / \
-- \___\/\___\
--
--Design Name: Z80CpuMon
--Device: multiple
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity Z80CpuMon is
generic (
ClkMult : integer;
ClkDiv : integer;
ClkPer : real;
num_comparators : integer;
avr_prog_mem_size : integer
);
port (
clock : in std_logic;
-- Z80 Signals
RESET_n : in std_logic;
CLK_n : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
Addr : out std_logic_vector(15 downto 0);
Data : inout std_logic_vector(7 downto 0);
-- Buffer Control Signals
DIRD : out std_logic;
tristate_n : out std_logic;
tristate_ad_n : out std_logic;
-- Mode jumper, tie low to generate NOPs when paused
mode : in std_logic;
-- External trigger inputs
trig : in std_logic_vector(1 downto 0);
-- Serial Console
avr_RxD : in std_logic;
avr_TxD : out std_logic;
-- Switches
sw_reset_cpu : in std_logic;
sw_reset_avr : in std_logic;
-- LEDs
led_bkpt : out std_logic;
led_trig0 : out std_logic;
led_trig1 : out std_logic;
-- OHO_DY1 connected to test connector
tmosi : out std_logic;
tdin : out std_logic;
tcclk : out std_logic;
-- Debugging signals
test1 : out std_logic;
test2 : out std_logic;
test3 : out std_logic;
test4 : out std_logic
);
end Z80CpuMon;
architecture behavioral of Z80CpuMon is
type state_type is (idle, nop_t1, nop_t2, nop_t3, nop_t4, rd_t1, rd_wa, rd_t2, rd_t3, wr_t1, wr_wa, wr_t2, wr_t3, busack);
signal state : state_type;
signal clock_avr : std_logic;
signal cpu_reset_n : std_logic;
signal cpu_clk : std_logic;
signal cpu_clken : std_logic;
signal busmon_clk : std_logic;
signal Addr_int : std_logic_vector(15 downto 0);
signal Addr1 : std_logic_vector(15 downto 0);
signal Addr2 : std_logic_vector(15 downto 0);
signal RD_n_int : std_logic;
signal WR_n_int : std_logic;
signal MREQ_n_int : std_logic;
signal IORQ_n_int : std_logic;
signal RFSH_n_int : std_logic;
signal M1_n_int : std_logic;
signal BUSAK_n_int : std_logic;
signal BUSAK_n_comb : std_logic;
signal WAIT_n_latched : std_logic;
signal TState : std_logic_vector(2 downto 0);
signal TState1 : std_logic_vector(2 downto 0);
signal SS_Single : std_logic;
signal SS_Step : std_logic;
signal SS_Step_held : std_logic;
signal CountCycle : std_logic;
signal special : std_logic_vector(2 downto 0);
signal skipNextOpcode : std_logic;
signal Regs : std_logic_vector(255 downto 0);
signal PdcData : std_logic_vector(7 downto 0);
signal io_not_mem : std_logic;
signal io_rd : std_logic;
signal io_wr : std_logic;
signal memory_rd : std_logic;
signal memory_wr : std_logic;
signal memory_addr : std_logic_vector(15 downto 0);
signal memory_dout : std_logic_vector(7 downto 0);
signal memory_din : std_logic_vector(7 downto 0);
signal memory_done : std_logic;
signal io_rd1 : std_logic;
signal io_wr1 : std_logic;
signal memory_rd1 : std_logic;
signal memory_wr1 : std_logic;
signal mon_m1_n : std_logic;
signal mon_xx_n : std_logic; -- shorten MREQ and RD in M1 NOP cycle
signal mon_yy : std_logic; -- delay IORQ/RD/WR in IO cycle
signal mon_mreq_n : std_logic;
signal mon_iorq_n : std_logic;
signal mon_rfsh_n : std_logic;
signal mon_rd_n : std_logic;
signal mon_wr_n : std_logic;
signal mon_busak_n1 : std_logic;
signal mon_busak_n2 : std_logic;
signal mon_busak_n : std_logic;
signal BUSRQ_n_sync : std_logic;
signal INT_n_sync : std_logic;
signal NMI_n_sync : std_logic;
signal Rdy : std_logic;
signal Read_n : std_logic;
signal Read_n0 : std_logic;
signal Read_n1 : std_logic;
signal Write_n : std_logic;
signal Write_n0 : std_logic;
signal ReadIO_n : std_logic;
signal ReadIO_n0 : std_logic;
signal ReadIO_n1 : std_logic;
signal WriteIO_n : std_logic;
signal WriteIO_n0 : std_logic;
signal Sync : std_logic;
signal Sync0 : std_logic;
signal Sync1 : std_logic;
signal Mem_IO_n : std_logic;
signal MemState : std_logic_vector(2 downto 0);
signal Din : std_logic_vector(7 downto 0);
signal Dout : std_logic_vector(7 downto 0);
signal Den : std_logic;
signal ex_data : std_logic_vector(7 downto 0);
signal rd_data : std_logic_vector(7 downto 0);
signal wr_data : std_logic_vector(7 downto 0);
signal mon_data : std_logic_vector(7 downto 0);
signal avr_TxD_int : std_logic;
signal rfsh_addr : std_logic_vector(15 downto 0);
begin
--------------------------------------------------------
-- Clocking
--------------------------------------------------------
inst_dcm0 : entity work.DCM0
generic map (
ClkMult => ClkMult,
ClkDiv => ClkDiv,
ClkPer => ClkPer
)
port map(
CLKIN_IN => clock,
CLKFX_OUT => clock_avr
);
cpu_clk <= CLK_n;
busmon_clk <= CLK_n;
--------------------------------------------------------
-- BusMonCore
--------------------------------------------------------
mon : entity work.BusMonCore
generic map (
num_comparators => num_comparators,
avr_prog_mem_size => avr_prog_mem_size
)
port map (
clock_avr => clock_avr,
busmon_clk => busmon_clk,
busmon_clken => '1',
cpu_clk => cpu_clk,
cpu_clken => '1',
Addr => Addr_int,
Data => mon_data,
Rd_n => Read_n,
Wr_n => Write_n,
RdIO_n => ReadIO_n,
WrIO_n => WriteIO_n,
Sync => Sync,
Rdy => open,
nRSTin => RESET_n,
nRSTout => cpu_reset_n,
CountCycle => CountCycle,
trig => trig,
avr_RxD => avr_RxD,
avr_TxD => avr_TxD_int,
sw_reset_cpu => sw_reset_cpu,
sw_reset_avr => sw_reset_avr,
led_bkpt => led_bkpt,
led_trig0 => led_trig0,
led_trig1 => led_trig1,
tmosi => tmosi,
tdin => tdin,
tcclk => tcclk,
Regs => Regs,
PdcData => PdcData,
RdMemOut => memory_rd,
WrMemOut => memory_wr,
RdIOOut => io_rd,
WrIOOut => io_wr,
AddrOut => memory_addr,
DataOut => memory_dout,
DataIn => memory_din,
Done => memory_done,
Special => special,
SS_Single => SS_Single,
SS_Step => SS_Step
);
--------------------------------------------------------
-- T80
--------------------------------------------------------
inst_t80: entity work.T80a port map (
TS => TState,
Regs => Regs,
PdcData => PdcData,
RESET_n => cpu_reset_n,
CLK_n => cpu_clk,
CEN => cpu_clken,
WAIT_n => WAIT_n,
INT_n => INT_n_sync,
NMI_n => NMI_n_sync,
BUSRQ_n => BUSRQ_n,
M1_n => M1_n_int,
MREQ_n => MREQ_n_int,
IORQ_n => IORQ_n_int,
RD_n => RD_n_int,
WR_n => WR_n_int,
RFSH_n => RFSH_n_int,
HALT_n => HALT_n,
BUSAK_n => BUSAK_n_int,
A => Addr_int,
Din => Din,
Dout => Dout,
DEn => Den
);
--------------------------------------------------------
-- Synchronise external interrupts
--------------------------------------------------------
int_gen : process(CLK_n)
begin
if rising_edge(CLK_n) then
BUSRQ_n_sync <= BUSRQ_n;
NMI_n_sync <= NMI_n or special(1);
INT_n_sync <= INT_n or special(0);
end if;
end process;
--------------------------------------------------------
-- Z80 specific single step / breakpoint logic
--------------------------------------------------------
CountCycle <= '1' when state = idle else '0';
-- The breakpoint logic stops the Z80 in M1/T3 using cpu_clken
cpu_clken <= '0' when state = idle and SS_Single = '1' and Sync1 = '1' else
'0' when state /= idle else
'1';
-- Logic to ignore the second M1 in multi-byte opcodes
skip_opcode_latch : process(CLK_n)
begin
if rising_edge(CLK_n) then
if (M1_n_int = '0' and WAIT_n_latched = '1' and TState = "010") then
if (skipNextOpcode = '0' and (Data = x"CB" or Data = x"DD" or Data = x"ED" or Data = x"FD")) then
skipNextOpcode <= '1';
else
skipNextOpcode <= '0';
end if;
end if;
end if;
end process;
-- For instruction breakpoints, we make the monitoring decision as early as possibe
-- to allow time to stop the current instruction, which is possible because we don't
-- really care about the data (it's re-read from memory by the disassembler).
Sync0 <= '1' when WAIT_n = '1' and M1_n_int = '0' and TState = "010" and skipNextOpcode = '0' else '0';
-- For memory reads/write breakpoints we make the monitoring decision in the middle of T2
-- but only if WAIT_n is '1' so we catch the right data.
Read_n0 <= not (WAIT_n and (not RD_n_int) and (not MREQ_n_int) and (M1_n_int)) when TState = "010" else '1';
Write_n0 <= not (WAIT_n and ( RD_n_int) and (not MREQ_n_int) and (M1_n_int)) when TState = "010" else '1';
-- For IO reads/writes we make the monitoring decision in the middle of the second T2 cycle
-- but only if WAIT_n is '1' so we catch the right data.
-- This one cycle delay accounts for the forced wait state
ReadIO_n0 <= not (WAIT_n and (not RD_n_int) and (not IORQ_n_int) and (M1_n_int)) when TState1 = "010" else '1';
WriteIO_n0 <= not (WAIT_n and ( RD_n_int) and (not IORQ_n_int) and (M1_n_int)) when TState1 = "010" else '1';
-- Hold the monitoring decision so it is valid on the rising edge of the clock
-- For instruction fetches and writes, the monitor sees these at the start of T3
-- For reads, the data can arrive in the middle of T3 so delay until end of T3
watch_gen : process(CLK_n)
begin
if falling_edge(CLK_n) then
Sync <= Sync0;
Read_n1 <= Read_n0;
Read_n <= Read_n1;
Write_n <= Write_n0;
ReadIO_n1 <= ReadIO_n0;
ReadIO_n <= ReadIO_n1;
WriteIO_n <= WriteIO_n0;
-- Latch wait seen by T80 on the falling edge, for use on the next rising edge
WAIT_n_latched <= WAIT_n;
end if;
end process;
-- Register the exec data on the rising at the end of T2
ex_data_latch : process(CLK_n)
begin
if rising_edge(CLK_n) then
TState1 <= TState;
if Sync = '1' then
ex_data <= Data;
end if;
end if;
end process;
-- Register the read data on the falling edge of clock in the middle of T3
rd_data_latch : process(CLK_n)
begin
if falling_edge(CLK_n) then
if Read_n1 = '0' or ReadIO_n1 = '0' then
rd_data <= Data;
end if;
memory_din <= Data;
end if;
end process;
-- Register the write data on the falling edge in the middle of T2
wr_data_latch : process(CLK_n)
begin
if falling_edge(CLK_n) then
if Write_n0 = '0' or WriteIO_n0 = '0' then
wr_data <= Data;
end if;
end if;
end process;
-- Mux the data seen by the bus monitor appropriately
mon_data <= rd_data when Read_n = '0' or ReadIO_n = '0' else
wr_data when Write_n = '0' or WriteIO_n = '0' else
ex_data;
-- Mark the memory access as done when t3 is reached
memory_done <= '1' when state = rd_t3 or state = wr_t3 else '0';
-- Multiplex the bus control signals
-- The _int versions come from the T80
-- The mon_ versions come from the state machine below
MREQ_n <= MREQ_n_int when state = idle else mon_mreq_n and mon_xx_n;
IORQ_n <= IORQ_n_int when state = idle else (mon_iorq_n or mon_yy);
WR_n <= WR_n_int when state = idle else (mon_wr_n or mon_yy);
RD_n <= RD_n_int when state = idle else (mon_rd_n or mon_yy) and mon_xx_n;
RFSH_n <= RFSH_n_int when state = idle else mon_rfsh_n;
M1_n <= M1_n_int when state = idle else mon_m1_n;
Addr1 <= x"0000" when state = nop_t1 or state = nop_t2 else
rfsh_addr when state = nop_t3 or state = nop_t4 else
memory_addr when state /= idle else
Addr_int;
tristate_n <= BUSAK_n_int when state = idle else mon_busak_n1;
BUSAK_n <= BUSAK_n_int when state = idle else mon_busak_n;
-- Force the address and databus to tristate when reset is asserted
tristate_ad_n <= '0' when RESET_n = '0' else
BUSAK_n_int when state = idle else
mon_busak_n1;
-- The Acorn Z80 Second Processor needs ~10ns of address hold time following M1
-- and MREQ being released at the start of T3. Otherwise, the ROM switching
-- during NMI doesn't work reliably due to glitches. See:
-- https://stardot.org.uk/forums/viewtopic.php?p=212096#p212096
--
-- Reordering the above Addr expression so Addr_int is last instead of
-- first seems to fix the issue, but is clearly very dependent on how the Xilinx
-- tools route the design.
--
-- If the problem recurs, we should switch to something like:
--
addr_delay : process(clock)
begin
if rising_edge(clock) then
Addr2 <= Addr1;
Addr <= Addr2;
end if;
end process;
Data <= memory_dout when (state = wr_t1 and io_not_mem = '1') or state = wr_wa or state = wr_t2 or state = wr_t3 else
Dout when state = idle and Den = '1' else
(others => 'Z');
DIRD <= '0' when (state = wr_t1 and io_not_mem = '1') or state = wr_wa or state = wr_t2 or state = wr_t3 else
'0' when state = idle and Den = '1' else
'1';
Din <= Data;
men_access_machine_rising : process(CLK_n, cpu_reset_n)
begin
if (cpu_reset_n = '0') then
state <= idle;
memory_rd1 <= '0';
memory_wr1 <= '0';
io_rd1 <= '0';
io_wr1 <= '0';
SS_Step_held <= '0';
mon_rfsh_n <= '1';
mon_m1_n <= '1';
mon_xx_n <= '1';
mon_yy <= '0';
mon_busak_n1 <= '1';
elsif rising_edge(CLK_n) then
-- Extend the 1-cycle long request strobes from BusMonCore
-- until we are ready to generate a bus cycle
if memory_rd = '1' then
memory_rd1 <= '1';
elsif state = rd_t1 then
memory_rd1 <= '0';
end if;
if memory_wr = '1' then
memory_wr1 <= '1';
elsif state = wr_t1 then
memory_wr1 <= '0';
end if;
if io_rd = '1' then
io_rd1 <= '1';
elsif state = rd_t1 then
io_rd1 <= '0';
end if;
if io_wr = '1' then
io_wr1 <= '1';
elsif state = wr_t1 then
io_wr1 <= '0';
end if;
if SS_Step = '1' then
SS_Step_held <= '1';
elsif state = idle then
SS_Step_held <= '0';
end if;
Sync1 <= Sync;
-- Main state machine, generating refresh, read and write cycles
-- (the timing should exactly match those of the Z80)
case state is
-- Idle is when T80 is running
when idle =>
if SS_Single = '1' and Sync1 = '1' then
-- Load the initial refresh address from I/R in the T80
rfsh_addr <= Regs(199 downto 192) & Regs(207 downto 200);
-- Start genering NOP cycles
mon_rfsh_n <= '0';
state <= nop_t3;
end if;
-- NOP cycle
when nop_t1 =>
state <= nop_t2;
-- Increment the refresh address (7 bits, just like the Z80)
rfsh_addr(6 downto 0) <= rfsh_addr(6 downto 0) + 1;
mon_xx_n <= mode;
when nop_t2 =>
if WAIT_n_latched = '1' then
mon_m1_n <= '1';
mon_xx_n <= '1';
if SS_Step_held = '1' or SS_Single = '0' then
state <= idle;
else
mon_rfsh_n <= '0';
state <= nop_t3;
end if;
end if;
when nop_t3 =>
state <= nop_t4;
when nop_t4 =>
mon_rfsh_n <= '1';
-- Sample BUSRQ_n at the *start* of the final T-state
-- (hence using BUSRQ_n_sync)
if BUSRQ_n_sync = '0' then
state <= busack;
mon_busak_n1 <= '0';
elsif memory_wr1 = '1' or io_wr1 = '1' then
state <= wr_t1;
io_not_mem <= io_wr1;
mon_yy <= io_wr1;
elsif memory_rd1 = '1' or io_rd1 = '1' then
state <= rd_t1;
io_not_mem <= io_rd1;
mon_yy <= io_rd1;
else
state <= nop_t1;
mon_m1_n <= mode;
end if;
-- Read cycle
when rd_t1 =>
mon_yy <= '0';
if io_not_mem = '1' then
state <= rd_wa;
else
state <= rd_t2;
end if;
when rd_wa =>
state <= rd_t2;
when rd_t2 =>
if WAIT_n_latched = '1' then
state <= rd_t3;
end if;
when rd_t3 =>
-- Sample BUSRQ_n at the *start* of the final T-state
-- (hence using BUSRQ_n_sync)
if BUSRQ_n_sync = '0' then
state <= busack;
mon_busak_n1 <= '0';
else
state <= nop_t1;
mon_m1_n <= mode;
end if;
-- Write cycle
when wr_t1 =>
mon_yy <= '0';
if io_not_mem = '1' then
state <= wr_wa;
else
state <= wr_t2;
end if;
when wr_wa =>
state <= wr_t2;
when wr_t2 =>
if WAIT_n_latched = '1' then
state <= wr_t3;
end if;
when wr_t3 =>
-- Sample BUSRQ_n at the *start* of the final T-state
-- (hence using BUSRQ_n_sync)
if BUSRQ_n_sync = '0' then
state <= busack;
mon_busak_n1 <= '0';
else
state <= nop_t1;
mon_m1_n <= mode;
end if;
-- Bus Request/Ack cycle
when busack =>
-- Release BUSAK_n on the next rising edge after BUSRQ_n seen
-- (hence using BUSRQ_n)
if BUSRQ_n_sync = '1' then
state <= nop_t1;
mon_m1_n <= mode;
mon_busak_n1 <= '1';
end if;
end case;
end if;
end process;
men_access_machine_falling : process(CLK_n)
begin
if falling_edge(CLK_n) then
-- For memory access cycles, mreq/iorq/rd/wr all change in the middle of
-- the t state, so retime these on the falling edge of clock
if state = rd_t1 or state = rd_wa or state = rd_t2 or state = wr_t1 or state = wr_wa or state = wr_t2 then
if io_not_mem = '0' then
-- Memory cycle
mon_mreq_n <= '0';
mon_iorq_n <= '1';
else
-- IO cycle
mon_mreq_n <= '1';
mon_iorq_n <= '0';
end if;
elsif (state = nop_t1 and mode = '0') or state = nop_t3 then
-- M1 cycle
mon_mreq_n <= '0';
mon_iorq_n <= '1';
else
-- Idle cycle
mon_mreq_n <= '1';
mon_iorq_n <= '1';
end if;
-- Read strobe
if (state = nop_t1 and mode = '0') or state = rd_t1 or state = rd_wa or state = rd_t2 then
mon_rd_n <= '0';
else
mon_rd_n <= '1';
end if;
-- Write strobe
if (state = wr_t1 and io_not_mem = '1') or state = wr_wa or state = wr_t2 then
mon_wr_n <= '0';
else
mon_wr_n <= '1';
end if;
-- Half-cycle delayed version of BUSRQ_n_sync
mon_busak_n2 <= BUSRQ_n_sync;
end if;
end process;
mon_busak_n <= mon_busak_n1 or mon_busak_n2;
avr_TxD <= avr_Txd_int;
test1 <= Sync1;
test2 <= TState(0);
test3 <= TState(1);
test4 <= TState(2);
end behavioral;
| gpl-3.0 | 0eae19dc7451fc6810cddda537d69fb9 | 0.448998 | 3.821763 | false | false | false | false |
hpeng2/ECE492_Group4_Project | Servo code/servo_pwm.vhd | 3 | 1,994 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.VITAL_Primitives.all;
entity servo_pwm is
port
(
clk : in std_logic;
reset_n : in std_logic;
coe_servo : out std_logic;
avs_s0_write_n : in std_logic;
avs_s0_writedata : in std_logic_vector (31 downto 0);
avs_s0_read_n : in std_logic;
avs_s0_readdata : out std_logic_vector (31 downto 0)
);
end servo_pwm;
architecture avalon of servo_pwm is
type state is (low, high);
signal current_state:state := high;
--signal CW :integer := 130000;
--signal CCW :integer := 170000;
--signal NEUTRAL :integer := 150000;
--signal REFRESH :integer := 2000000;
signal direction:std_logic_vector (31 downto 0);
begin
latch_direction: process(clk,avs_s0_write_n) is
begin
if falling_edge(avs_s0_write_n) then
direction <= avs_s0_writedata;
avs_s0_readdata <= direction;
end if;
end process;
pwm: process( reset_n, clk ) is
-- 100 MHz with a 20 ms refresh rate means period is 2000000 clk cycles between each puls
variable period_count: integer := 2000000; -- How man clocks to count from falling edge of first pulse to rising edge of second pulse
variable pulse_count: integer:= 150000; -- This is 1.5ms pulse for neurtral position
begin
if ( reset_n = '0' ) then
period_count := 2000000;
pulse_count := 150000;
elsif rising_edge(clk) then
if ( current_state = high ) then
if ( pulse_count > 0 ) then
pulse_count := pulse_count - 1;
coe_servo <= '1';
elsif ( pulse_count = 0 ) then
current_state <= low;
pulse_count := to_integer(unsigned(direction));
if (pulse_count = 0 ) then
pulse_count := 150000;
end if;
end if;
elsif ( current_state = low ) then
if ( period_count > 0 ) then
period_count := period_count - 1;
coe_servo <= '0';
elsif ( period_count = 0 ) then
period_count := 2000000;
current_state <= high;
end if;
end if;
end if;
end process;
end avalon;
| gpl-2.0 | 510c1bd19453b27d5dd4e50952076ad9 | 0.651956 | 3.007541 | false | false | false | false |
hoglet67/ElectronFpga | src/common/ElectronFpga_core.vhd | 1 | 13,483 | --------------------------------------------------------------------------------
-- Copyright (c) 2015 David Banks
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : ElectronFpga_core.vhd
-- /___/ /\ Timestamp : 28/07/2015
-- \ \ / \
-- \___\/\___\
--
--Design Name: ElectronFpga_core
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity ElectronFpga_core is
generic (
IncludeICEDebugger : boolean := false;
IncludeABRRegs : boolean := false;
IncludeJafaMode7 : boolean := false
);
port (
-- Clocks
clk_16M00 : in std_logic;
clk_24M00 : in std_logic; -- for Jafa Mode7
clk_32M00 : in std_logic; -- for Jafa Mode7
clk_33M33 : in std_logic;
clk_40M00 : in std_logic;
-- Hard reset (active low)
hard_reset_n : in std_logic;
-- Keyboard
ps2_clk : in std_logic;
ps2_data : in std_logic;
-- Video
video_red : out std_logic_vector (3 downto 0);
video_green : out std_logic_vector (3 downto 0);
video_blue : out std_logic_vector (3 downto 0);
video_vsync : out std_logic;
video_hsync : out std_logic;
-- Audio
audio_l : out std_logic;
audio_r : out std_logic;
-- External memory (e.g. SRAM and/or FLASH)
-- 512KB logical address space
ext_nOE : out std_logic;
ext_nWE : out std_logic;
ext_nCS : out std_logic;
ext_A : out std_logic_vector (18 downto 0);
ext_Dout : in std_logic_vector (7 downto 0);
ext_Din : out std_logic_vector (7 downto 0);
-- SD Card
SDMISO : in std_logic;
SDSS : out std_logic;
SDCLK : out std_logic;
SDMOSI : out std_logic;
-- KeyBoard LEDs (active high)
caps_led : out std_logic;
motor_led : out std_logic;
-- Casette Port
cassette_in : in std_logic;
cassette_out : out std_logic;
-- Format of Video
-- 00 - sRGB - interlaced
-- 01 - sRGB - non interlaced
-- 10 - SVGA - 50Hz
-- 11 - SVGA - 60Hz
vid_mode : in std_logic_vector(1 downto 0);
-- Test outputs
test : out std_logic_vector(7 downto 0);
-- ICE T65 Deubgger 57600 baud serial
avr_RxD : in std_logic;
avr_TxD : out std_logic;
cpu_addr : out std_logic_vector(15 downto 0)
);
end;
architecture behavioral of ElectronFpga_core is
signal RSTn : std_logic;
signal cpu_R_W_n : std_logic;
signal cpu_a : std_logic_vector (23 downto 0);
signal cpu_din : std_logic_vector (7 downto 0);
signal cpu_dout : std_logic_vector (7 downto 0);
signal cpu_IRQ_n : std_logic;
signal cpu_NMI_n : std_logic;
signal ROM_n : std_logic;
signal ula_data : std_logic_vector (7 downto 0);
signal ula_enable : std_logic;
signal key_break : std_logic;
signal key_turbo : std_logic_vector(1 downto 0);
signal sound : std_logic;
signal kbd_data : std_logic_vector(3 downto 0);
signal cpu_clken : std_logic;
signal cpu_clken_r : std_logic;
signal rom_latch : std_logic_vector(3 downto 0);
signal ext_enable : std_logic;
signal abr_enable : std_logic;
signal abr_lo_bank_lock : std_logic;
signal abr_hi_bank_lock : std_logic;
signal video_vsync_int : std_logic;
signal video_hsync_int : std_logic;
signal video_red_int : std_logic_vector(3 downto 0);
signal video_green_int : std_logic_vector(3 downto 0);
signal video_blue_int : std_logic_vector(3 downto 0);
begin
video_vsync <= video_vsync_int;
video_hsync <= video_hsync_int;
video_red <= video_red_int;
video_green <= video_green_int;
video_blue <= video_blue_int;
GenDebug: if IncludeICEDebugger generate
signal cpu_clken1 : std_logic;
begin
core : entity work.MOS6502CpuMonCore
generic map (
UseT65Core => true,
UseAlanDCore => false
)
port map (
clock_avr => clk_24M00,
busmon_clk => clk_16M00,
busmon_clken => cpu_clken1,
cpu_clk => clk_16M00,
cpu_clken => cpu_clken,
IRQ_n => cpu_IRQ_n,
NMI_n => cpu_NMI_n,
Sync => open,
Addr => cpu_a(15 downto 0),
R_W_n => cpu_R_W_n,
Din => cpu_din,
Dout => cpu_dout,
SO_n => '1',
Res_n => RSTn,
Rdy => '1',
trig => "00",
avr_RxD => avr_RxD,
avr_TxD => avr_TxD,
sw_reset_cpu => '0',
sw_reset_avr => not hard_reset_n,
led_bkpt => open,
led_trig0 => open,
led_trig1 => open,
tmosi => open,
tdin => open,
tcclk => open
);
process(clk_16M00)
begin
if rising_edge(clk_16M00) then
cpu_clken1 <= cpu_clken;
end if;
end process;
end generate;
GenNoDebugCore: if not IncludeICEDebugger generate
T65core : entity work.T65
port map (
Mode => "00",
Abort_n => '1',
SO_n => '1',
Res_n => RSTn,
Enable => cpu_clken,
Clk => clk_16M00,
Rdy => '1',
IRQ_n => cpu_IRQ_n,
NMI_n => cpu_NMI_n,
R_W_n => cpu_R_W_n,
Sync => open,
A => cpu_a,
DI => cpu_din,
DO => cpu_dout
);
avr_TxD <= avr_RxD;
end generate;
ula : entity work.ElectronULA
generic map (
IncludeMMC => true,
Include32KRAM => false,
IncludeVGA => true,
IncludeJafaMode7 => IncludeJafaMode7,
LimitROMSpeed => false,
LimitIOSpeed => false
)
port map (
clk_16M00 => clk_16M00,
clk_24M00 => clk_24M00,
clk_32M00 => clk_32M00,
clk_33M33 => clk_33M33,
clk_40M00 => clk_40M00,
-- CPU Interface
addr => cpu_a(15 downto 0),
data_in => cpu_dout,
data_out => ula_data,
data_en => ula_enable,
R_W_n => cpu_R_W_n,
RST_n => RSTn,
IRQ_n => cpu_IRQ_n,
NMI_n => cpu_NMI_n,
-- Rom Enable
ROM_n => ROM_n,
-- Video
red => video_red_int,
green => video_green_int,
blue => video_blue_int,
vsync => video_vsync_int,
hsync => video_hsync_int,
-- Audio
sound => sound,
-- SD Card
SDMISO => SDMISO,
SDSS => SDSS,
SDCLK => SDCLK,
SDMOSI => SDMOSI,
-- Casette
casIn => cassette_in,
casOut => cassette_out,
-- Keyboard
kbd => kbd_data,
-- MISC
caps => caps_led,
motor => motor_led,
rom_latch => rom_latch,
mode_init => vid_mode,
-- Clock Generation
cpu_clken_out => cpu_clken,
turbo => key_turbo
);
input : entity work.keyboard port map(
clk => clk_16M00,
rst_n => hard_reset_n, -- to avoid a loop when break pressed!
ps2_clk => ps2_clk,
ps2_data => ps2_data,
col => kbd_data,
row => cpu_a(13 downto 0),
break => key_break,
turbo => key_turbo
);
cpu_NMI_n <= '1';
RSTn <= hard_reset_n and key_break;
audio_l <= sound;
audio_r <= sound;
ext_enable <= '1' when
-- ROM accrss
ROM_n = '0' or
-- Non screen main memory access (0000-2FFF)
cpu_a(15 downto 13) = "000" or cpu_a(15 downto 12) = "0010" or
-- Sideways RAM Access
(cpu_a(15 downto 14) = "10" and rom_latch(3 downto 1) /= "100") else '0';
cpu_din <= ext_Dout when ext_enable = '1' else
ula_data when ula_enable = '1' else
x"F1";
-- Pipeline external memory interface
-- External addresses 00000-3FFFF are routed to FLASH 80000-DFFFFF
-- External addresses 40000-7FFFF are routed to SRAM
-- Note: the bottom 32K of CPU address space is mapped to SRAM, 20K of this is overlaid by the ULA
process(clk_16M00,hard_reset_n)
begin
if hard_reset_n = '0' then
ext_A <= (others => '0');
ext_Din <= (others => '0');
ext_nWE <= '1';
ext_nOE <= '1';
elsif rising_edge(clk_16M00) then
-- delayed cpu_clken for use as an external write signal
cpu_clken_r <= cpu_clken;
if cpu_a(15) = '0' then
-- exteral main memory access
ext_A <= "1" & "000" & cpu_a(14 downto 0);
elsif cpu_a(15 downto 14) = "11" then
-- The OS rom image lives in slot 8 as on the Elk this is where the
-- keyboard appears, which keeps the external memory image down to 256KB.
ext_A <= "0" & "1000" & cpu_a(13 downto 0);
elsif cpu_a(15 downto 14) = "10" and rom_latch(3 downto 2) = "00" then
-- Slots 0..3 are mapped to SRAM
ext_A <= "1" & rom_latch & cpu_a(13 downto 0);
elsif cpu_a(15 downto 14) = "10" and rom_latch(3 downto 0) = "0100" and cpu_a(13 downto 8) >= "110110" then
-- Slots 4 (MMFS) has B600 onwards as writeable for private workspace so mapped to SRAM
ext_A <= "1" & rom_latch & cpu_a(13 downto 0);
else
-- everyting else is ROM
ext_A <= "0" & rom_latch & cpu_a(13 downto 0);
end if;
ext_Din <= cpu_dout;
if cpu_R_W_n = '1' or ext_enable = '0' or cpu_clken_r = '0' then
-- Default is disable WE, except in a few cases
ext_nWE <= '1';
elsif cpu_a(15) = '0' then
-- exteral main memory access
ext_nWE <= '0';
elsif cpu_a(14) = '0' and rom_latch(3 downto 2) = "00" and rom_latch(0) = '0' and abr_lo_bank_lock = '0' then
-- Slots 0,2 are write protected with FCDC/FCDD
ext_nWE <= '0';
elsif cpu_a(14) = '0' and rom_latch(3 downto 2) = "00" and rom_latch(0) = '1' and abr_hi_bank_lock = '0' then
-- Slots 1,3 are write protected with FCDE/FCDF
ext_nWE <= '0';
elsif cpu_a(14) = '0' and rom_latch(3 downto 0) = "0100" and cpu_a(13 downto 8) >= "110110" then
-- Slots 4 (MMFS) has B600 onwards as writeable for private workspace
ext_nWE <= '0';
else
-- Other slots are read only
ext_nWE <= '1';
end if;
-- Could make this more restrictive
if cpu_R_W_n = '1' and ext_enable = '1' then
ext_nOE <= '0';
else
ext_nOE <= '1';
end if;
end if;
end process;
-- Always enabled
ext_nCS <= '0';
--------------------------------------------------------
-- ABR Lock Registers
--------------------------------------------------------
ABRIncluded: if IncludeABRRegs generate
abr_enable <= '1' when cpu_a(15 downto 2) & "00" = x"fcdc" else '0';
process(clk_16M00, RSTn)
begin
if RSTn = '0' then
abr_lo_bank_lock <= '1';
abr_hi_bank_lock <= '1';
elsif rising_edge(clk_16M00) then
if cpu_clken = '1' then
if abr_enable = '1' and cpu_R_W_n = '0' then
if cpu_a(1) = '0' then
abr_lo_bank_lock <= cpu_a(0);
else
abr_hi_bank_lock <= cpu_a(0);
end if;
end if;
end if;
end if;
end process;
end generate;
ABRExcluded: if not IncludeABRRegs generate
abr_lo_bank_lock <= '1';
abr_hi_bank_lock <= '1';
end generate;
cpu_addr <= cpu_a(15 downto 0);
test <= video_vsync_int & video_hsync_int & video_blue_int(3) & video_green_int(3) & video_red_int(3) & "00" & cpu_IRQ_n;
end behavioral;
| gpl-3.0 | 359a00a8524de3fc5366b7fa62123cff | 0.449158 | 3.69904 | false | false | false | false |
emusan/wifidar_fpga | src/preamp_config.vhd | 1 | 2,555 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
entity preamp_config is
port(
preamp_done: out std_logic;
send_data: in std_logic;
busy: out std_logic;
gain_in: in std_logic_vector(3 downto 0);
spi_mosi: out std_logic;
spi_sck: out std_logic;
clk: in std_logic
);
end preamp_config;
architecture Behavioral of preamp_config is
type spi_state is (reset,sending,waiting);
signal curr_state: spi_state;
signal divide_count: integer range 0 to 10;
signal divided_clk: std_logic;
signal spi_count: integer range 0 to 9;
signal spi_clk_sig: std_logic := '0';
begin
clk_div: process(clk)
begin
if(rising_edge(clk)) then
case curr_state is
when reset =>
divided_clk <= '0';
divide_count <= 0;
when sending =>
divided_clk <= '0';
divide_count <= divide_count + 1;
if(divide_count = 10) then
divide_count <= 0;
divided_clk <= '1';
end if;
when waiting =>
end case;
end if;
end process;
process(clk)
begin
if(rising_edge(clk)) then
case curr_state is
when reset =>
curr_state <= waiting;
when sending =>
busy <= '1';
if(divided_clk = '1') then
if(spi_count <= 9) then
spi_clk_sig <= not spi_clk_sig;
end if;
if(spi_clk_sig = '1') then
if(spi_count <= 9) then
spi_count <= spi_count + 1;
preamp_done <= '0';
spi_clk_sig <= '0';
else
preamp_done <= '1';
end if;
case spi_count is
when 0 =>
--amp_cs <= '1';
when 1 =>
--amp_cs <= '0';
spi_mosi <= '1';
when 2 =>
spi_mosi <= '0';
when 3 =>
spi_mosi <= '0';
when 4 =>
spi_mosi <= '0';
when 5 =>
spi_mosi <= gain_in(3);
when 6 =>
spi_mosi <= gain_in(2);
when 7 =>
spi_mosi <= gain_in(1);
when 8 =>
spi_mosi <= gain_in(0);
when others =>
spi_mosi <= '0';
--amp_cs <= '1';
preamp_done <= '1';
curr_state <= waiting;
spi_clk_sig <= '0';
end case;
end if;
end if;
when waiting =>
spi_clk_sig <= '0';
spi_count <= 0;
spi_mosi <= '0';
busy <= '0';
if(send_data = '1') then
curr_state <= sending;
end if;
end case;
end if;
end process;
spi_sck <= spi_clk_sig;
end Behavioral;
| mit | e105de69cb16d8b9d597d19de3478fc7 | 0.524853 | 2.977855 | false | false | false | false |
DreamIP/GPStudio | support/io/mpu/hdl/mpu_i2c_master.vhd | 1 | 15,136 | --------------------------------------------------------------------------------
--
-- FileName: i2c_master.vhd
-- Dependencies: none
-- Design Software: Quartus II 32-bit Version 11.1 Build 173 SJ Full Version
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
--
-- Version History
-- Version 1.0 11/1/2012 Scott Larson
-- Initial Public Release
-- Version 2.0 06/20/2014 Scott Larson
-- Added ability to interface with different slaves in the same transaction
-- Corrected ack_error bug where ack_error went 'Z' instead of '1' on error
-- Corrected timing of when ack_error signal clears
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY mpu_i2c_master IS
GENERIC(
input_clk : INTEGER := 50_000_000; --input clock speed from user logic in Hz
bus_clk : INTEGER := 400_000); --speed the i2c bus (scl) will run at in Hz
PORT(
clk : IN STD_LOGIC; --system clock
reset_n : IN STD_LOGIC; --active low reset
end_rw : out std_logic;
master_ack_flag : out std_logic;
op_counter : out std_logic;
fifo_wr_en : out std_logic;
ena : IN STD_LOGIC; --latch in command
addr : IN STD_LOGIC_VECTOR(6 DOWNTO 0); --address of target slave
rw : IN STD_LOGIC; --'0' is write, '1' is read
data_wr : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --data to write to slave
busy : OUT STD_LOGIC; --indicates transaction in progress
data_rd : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --data read from slave
ack_error : BUFFER STD_LOGIC; --flag if improper acknowledge from slave
sda : INOUT STD_LOGIC; --serial data output of i2c bus
scl : INOUT STD_LOGIC); --serial clock output of i2c bus
END mpu_i2c_master;
ARCHITECTURE logic OF mpu_i2c_master IS
CONSTANT divider : INTEGER := (input_clk/bus_clk)/4; --number of clocks in 1/4 cycle of scl
TYPE machine IS(ready, start, command, slv_ack1, wr, rd, slv_ack2, mstr_ack, stop); --needed states
SIGNAL state : machine; --state machine
SIGNAL data_clk : STD_LOGIC; --data clock for sda
SIGNAL data_clk_prev : STD_LOGIC; --data clock during previous system clock
SIGNAL scl_clk : STD_LOGIC; --constantly running internal scl
SIGNAL scl_ena : STD_LOGIC := '0'; --enables internal scl to output
SIGNAL sda_int : STD_LOGIC := '1'; --internal sda
SIGNAL sda_ena_n : STD_LOGIC; --enables internal sda to output
SIGNAL addr_rw : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in address and read/write
SIGNAL data_tx : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in data to write to slave
SIGNAL data_rx : STD_LOGIC_VECTOR(7 DOWNTO 0); --data received from slave
SIGNAL bit_cnt : INTEGER RANGE 0 TO 7 := 7; --tracks bit number in transaction
SIGNAL stretch : STD_LOGIC := '0'; --identifies if slave is stretching scl
signal read_op : std_logic;
BEGIN
--generate the timing for the bus clock (scl_clk) and the data clock (data_clk)
PROCESS(clk, reset_n)
VARIABLE count : INTEGER RANGE 0 TO divider*4; --timing for clock generation
BEGIN
IF(reset_n = '0') THEN --reset asserted
stretch <= '0';
count := 0;
ELSIF(clk'EVENT AND clk = '1') THEN
data_clk_prev <= data_clk; --store previous value of data clock
IF(count = divider*4-1) THEN --end of timing cycle
count := 0; --reset timer
ELSIF(stretch = '0') THEN --clock stretching from slave not detected
count := count + 1; --continue clock generation timing
END IF;
CASE count IS
WHEN 0 TO divider-1 => --first 1/4 cycle of clocking
scl_clk <= '0';
data_clk <= '0';
WHEN divider TO divider*2-1 => --second 1/4 cycle of clocking
scl_clk <= '0';
data_clk <= '1';
WHEN divider*2 TO divider*3-1 => --third 1/4 cycle of clocking
scl_clk <= '1'; --release scl
IF(scl = '0') THEN --detect if slave is stretching clock
stretch <= '1'; --------------------MODIF
ELSE
stretch <= '0';
END IF;
data_clk <= '1';
WHEN OTHERS => --last 1/4 cycle of clocking
scl_clk <= '1';
data_clk <= '0';
END CASE;
END IF;
END PROCESS;
--state machine and writing to sda during scl low (data_clk rising edge)
PROCESS(clk, reset_n)
BEGIN
IF(reset_n = '0') THEN --reset asserted
state <= ready; --return to initial state
busy <= '1'; --indicate not available
scl_ena <= '0'; --sets scl high impedance
sda_int <= '1'; --sets sda high impedance
ack_error <= '0'; --clear acknowledge error flag
bit_cnt <= 7; --restarts data bit counter
data_rd <= "00000000"; --clear data read port
read_op <= '0';
end_rw<='0';
fifo_wr_en <= '0';
ELSIF(clk'EVENT AND clk = '1') THEN
IF(data_clk = '1' AND data_clk_prev = '0') THEN --data clock rising edge
CASE state IS
WHEN ready => --idle state
op_counter <= '0';
IF(ena = '1') THEN --transaction requested
busy <= '1'; --flag busy
addr_rw <= addr & rw; --collect requested slave address and command
data_tx <= data_wr; --collect requested data to write
state <= start; --go to start bit
ELSE --remain idle
busy <= '0'; --unflag busy
state <= ready; --remain idle
END IF;
WHEN start => --start bit of transaction
busy <= '1'; --resume busy if continuous mode
sda_int <= addr_rw(bit_cnt); --set first address bit to bus
state <= command; --go to command
WHEN command => --address and command byte of transaction
IF(bit_cnt = 0) THEN --command transmit finished
sda_int <= '1'; --release sda for slave acknowledge
bit_cnt <= 7; --reset bit counter for "byte" states
state <= slv_ack1; --go to slave acknowledge (command)
ELSE --next clock cycle of command state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
sda_int <= addr_rw(bit_cnt-1); --write address/command bit to bus
state <= command; --continue with command
END IF;
WHEN slv_ack1 => --slave acknowledge bit (command)
IF(addr_rw(0) = '0') THEN --write command
sda_int <= data_tx(bit_cnt); --write first bit of data
state <= wr; --go to write byte
ELSE --read command
sda_int <= '1'; --release sda from incoming data
state <= rd; --go to read byte
END IF;
WHEN wr => --write byte of transaction
busy <= '1'; --resume busy if continuous mode
read_op <= '0';
IF(bit_cnt = 0) THEN --write byte transmit finished
sda_int <= '1'; --release sda for slave acknowledge
bit_cnt <= 7; --reset bit counter for "byte" states
state <= slv_ack2; --go to slave acknowledge (write)
end_rw<='1';
ELSE --next clock cycle of write state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
sda_int <= data_tx(bit_cnt-1); --write next bit to bus
state <= wr; --continue writing
END IF;
WHEN rd => --read byte of transaction
read_op <= '1';
busy <= '1'; --resume busy if continuous mode
IF(bit_cnt = 0) THEN --read byte receive finished
fifo_wr_en <= '1';
IF(ena = '1' AND addr_rw = addr & rw) THEN --continuing with another read at same address
sda_int <= '0'; --acknowledge the byte has been received
ELSE --stopping or continuing with a write
sda_int <= '1'; --send a no-acknowledge (before stop or repeated start)
END IF;
bit_cnt <= 7; --reset bit counter for "byte" states
data_rd <= data_rx; --output received data
state <= mstr_ack; --go to master acknowledge
end_rw<='1';
ELSE --next clock cycle of read state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
state <= rd; --continue reading
END IF;
WHEN slv_ack2 => --slave acknowledge bit (write)
end_rw<='0';
IF(ena = '1') THEN --continue transaction
busy <= '0'; --continue is accepted
addr_rw <= addr & rw; --collect requested slave address and command
data_tx <= data_wr; --collect requested data to write
IF(addr_rw = addr & rw) THEN --continue transaction with another write
sda_int <= data_wr(bit_cnt); --write first bit of data
state <= wr; --go to write byte
ELSE --continue transaction with a read or new slave
state <= start; --go to repeated start
END IF;
ELSE --complete transaction
state <= stop; --go to stop bit
END IF;
WHEN mstr_ack => --master acknowledge bit after a read
fifo_wr_en <='0';
end_rw<='0';
IF(ena = '1') THEN --continue transaction
busy <= '0'; --continue is accepted and data received is available on bus
addr_rw <= addr & rw; --collect requested slave address and command
data_tx <= data_wr; --collect requested data to write
IF(addr_rw = addr & rw) THEN --continue transaction with another read
sda_int <= '1'; --release sda from incoming data
state <= rd; --go to read byte
ELSE --continue transaction with a write or new slave
state <= start; --repeated start
END IF;
ELSE --complete transaction
-- sda_int <= '1';
state <= stop; --go to stop bit
END IF;
WHEN stop => --stop bit of transaction
if read_op='0' then
op_counter <= '1';
else
op_counter <= '0';
end if;
busy <= '0'; --unflag busy
state <= ready; --go to idle state
END CASE;
ELSIF(data_clk = '0' AND data_clk_prev = '1') THEN --data clock falling edge
CASE state IS
WHEN start =>
IF(scl_ena = '0') THEN --starting new transaction
scl_ena <= '1'; --enable scl output
ack_error <= '0'; --reset acknowledge error output
END IF;
WHEN slv_ack1 => --receiving slave acknowledge (command)
IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge
ack_error <= '1'; --set error output if no-acknowledge
END IF;
WHEN rd => --receiving slave data
data_rx(bit_cnt) <= sda; --receive current slave data bit
WHEN slv_ack2 => --receiving slave acknowledge (write)
IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge
ack_error <= '1'; --set error output if no-acknowledge
END IF;
WHEN stop =>
scl_ena <= '0'; --disable scl
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END IF;
END PROCESS;
--set sda output
WITH state SELECT
sda_ena_n <= data_clk_prev WHEN start, --generate start condition
NOT data_clk_prev WHEN stop, --generate stop condition
not ena when mstr_ack,
sda_int WHEN OTHERS; --set to internal sda signal
--set scl and sda outputs
scl <= '0' WHEN (scl_ena = '1' AND scl_clk = '0') ELSE 'Z';
sda <= '0' WHEN sda_ena_n = '0' ELSE 'Z';
with state select
master_ack_flag <= '1' when mstr_ack,
'0' when others;
END logic;
| gpl-3.0 | 45edee3e336b099cbc9f0738265febd7 | 0.46908 | 4.61745 | false | false | false | false |
DreamIP/GPStudio | support/toolchain/caph/hdl/caph_toplevel/src/caph_external_component.vhd | 1 | 5,164 | ------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.caph_flow_pkg.caph_ports_t;
package caph_external_component is
component caph_toplevel is
generic (
IN_SIZE :positive;
OUT_SIZE :positive;
INPUT_FREQ : positive;
IMAGE_WIDTH : positive;
IMAGE_HEIGHT: positive;
USE_PORTS : string :="NO";
NB_PORTS: positive;
MEM_ADDR_BUS_SIZE : POSITIVE := 4;
CLK_PROC_FREQ : positive;
CLK_CAPH_FREQ : positive
);
port (
clk_proc : in std_logic;
clk_caph : in std_logic;
reset : in std_logic;
in_data: in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
out_data : out std_logic_vector(OUT_SIZE-1 downto 0) ;
out_fv : out std_logic;
out_dv : out std_logic;
-- add param interface
-- param_addr_o: out std_logic_vector(MEM_ADDR_BUS_SIZE-1 DOWNTO 0);
-- param_data_i : in std_logic_vector(15 downto 0);
-- update_port_i : in std_logic
------ bus_sl ------
addr_rel_i : in std_logic_vector(4 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end component;
component params_to_ports
generic (
NB_PORTS: positive:= 1
);
port(
update_i : in std_logic;
param_data_i : in std_logic_vector(31 downto 0);
-- array of ports
ports : out caph_ports_t;
clk_i : in std_logic;
rst_n_i :in std_logic
);
end component;
component caph_pll
GENERIC
(
INPUT_FREQ: positive := 48
);
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC
);
END component;
component tokenize_flow is
generic (
DATA_INPUT_SIZE: integer := 8;
TOKEN_HEADER_SIZE: integer := 2;
TOKEN_SIZE: integer := 10;
IMAGE_WIDTH : integer := 500;
IMAGE_HEIGHT : integer := 2
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
dv_i : in std_logic;
enable_i : in std_logic;
data_i: in std_logic_vector(DATA_INPUT_SIZE-1 downto 0);
imwidth_i : in std_LOGIC_VECTOR(31 downto 0);
imheight_i : in std_LOGIC_VECTOR(31 downto 0);
clk_caph_i:in std_logic; -- clk fifo = clk_pixelx2
fifo_full_i:in std_logic; --fifo_full input
token_o : out std_logic_vector(TOKEN_SIZE-1 downto 0);
wr_fifo_o:out std_logic -- write fifo
);
end component;
component untokenize_flow is
generic(
IMAGE_WIDTH:integer := 320;
IMAGE_HEIGHT:integer := 240;
TOKEN_SIZE: integer := 10;
SIZE:integer:=8
);
port (
clk_caph: in std_logic;
clk_proc: in std_logic;
rst_n_i : in std_logic;
fifo_empty: in std_logic;
data_i : in std_logic_vector(TOKEN_SIZE-1 downto 0);
imwidth_i : in std_LOGIC_VECTOR(31 downto 0);
imheight_i : in std_LOGIC_VECTOR(31 downto 0);
fifo_unpile: out std_logic;
frame_valid_o :out std_logic;
data_valid_o :out std_logic;
data_o : out std_logic_vector (SIZE-1 downto 0)
);
end component;
component packet_generator
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
frame_valid_i : in std_logic;
data_valid_i : in std_logic;
data_i : in std_logic_vector(7 downto 0);
frame_valid_o : out std_logic;
data_valid_o : out std_logic;
data_o : out std_logic_vector(15 downto 0)
);
end component;
component bus2caph
generic (
NB_PORTS:positive := 0
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- quartus declaration
addr_i : in std_logic_vector(3 DOWNTO 0);
wr_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
enable_o : out std_logic;
-- port_o : out std_logic_vector(31 downto 0);
ports: out caph_ports_t;
imwidth_o : out std_logic_vector(31 downto 0);
imheight_o : out std_logic_vector(31 downto 0)
);
end component;
-- OLD components
component tokenize_mt9
generic (SIZE: integer := 10);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
frame_valid_i : in std_logic;
data_valid_i : in std_logic;
data_i: in std_logic_vector(7 downto 0);
token_o : out std_logic_vector(SIZE-1 downto 0);
-- CAPH fifo management
clk_caph_i:in std_logic; -- clk fifo = clk_pixelx2
fifo_full_i:in std_logic; --fifo_full input
wr_fifo_o:out std_logic -- write fifo
);
end component;
component untokenize_mt9
generic(SIZE:integer:=10);
port (
clk_i: in std_logic;
rst_n_i : in std_logic;
fifo_empty: in std_logic;
data_i : in std_logic_vector(SIZE-1 downto 0);
fifo_unpile: out std_logic;
frame_valid_o :out std_logic;
data_valid_o :out std_logic;
data_o : out std_logic_vector (7 downto 0)
);
end component;
end caph_external_component;
| gpl-3.0 | ecdc64bf2c77df4da277d27c05698775 | 0.577266 | 2.843612 | false | false | false | false |
ou-cse-378/vhdl-tetris | mux8g.vhd | 1 | 1,545 | -- =================================================================================
-- // Name: Bryan Mason, James Batcheler, & Brad McMahon
-- // File: mux2g.vhd
-- // Date: 12/9/2004
-- // Description: 8 channel, n bit mux
-- // Class: CSE 378
-- =================================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mux8g is
generic(width:positive);
Port (
a : in std_logic_vector(width-1 downto 0);
b : in std_logic_vector(width-1 downto 0);
c : in std_logic_vector(width-1 downto 0);
d : in std_logic_vector(width-1 downto 0);
e : in std_logic_vector(width-1 downto 0);
f : in std_logic_vector(width-1 downto 0);
g : in std_logic_vector(width-1 downto 0);
h : in std_logic_vector(width-1 downto 0);
sel : in std_logic_vector(2 downto 0);
y : out std_logic_vector(width-1 downto 0)
);
end mux8g;
architecture mux8g_arch of mux8g is
begin
process(a, b, c, d, e, f, g, h, sel)
begin
case sel is
when "000" => y <= a;
when "001" => y <= b;
when "010" => y <= c;
when "011" => y <= d;
when "100" => y <= e;
when "101" => y <= f;
when "110" => y <= g;
when others => y <= h;
end case;
end process;
end mux8g_arch;
| mit | e08d497708d0953e0f2445471b108e95 | 0.539159 | 3.22547 | false | false | false | false |
DreamIP/GPStudio | support/io/eth_marvell_88e1111/hdl/RGMII_MAC/rgmii_rx_top_2.vhd | 1 | 4,087 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity rgmii_rx_top_2 is
port(
iEthClk : IN STD_LOGIC;
iRst_n : IN STD_LOGIC;
iMAC_HAL : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
iEnetRxData : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
iEnetRxDv : IN STD_LOGIC;
iEnetRxErr : IN STD_LOGIC;
-- hardware checksum check
iCheckSumIPCheck : IN STD_LOGIC;
iCheckSumTCPCheck : IN STD_LOGIC;
iCheckSumUDPCheck : IN STD_LOGIC;
iCheckSumICMPCheck : IN STD_LOGIC;
--USR IF
iUDP_rx_rdy : IN STD_lOGIC;
oData_rx : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
oData_valid : OUT STD_LOGIC;
oSOF : OUT STD_LOGIC;
oEOF : OUT STD_LOGIC
);
end entity;
architecture rtl of rgmii_rx_top_2 is
COMPONENT rgmii_rx IS
PORT (
iClk : IN STD_LOGIC;
iRst_n : IN STD_LOGIC;
iRxData : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
iRxDV : IN STD_LOGIC;
iRxEr : IN STD_LOGIC;
-- these signals come from wishbone clock domian, NOT synchronized
iCheckSumIPCheck : IN STD_LOGIC;
iCheckSumTCPCheck : IN STD_LOGIC;
iCheckSumUDPCheck : IN STD_LOGIC;
iCheckSumICMPCheck : IN STD_LOGIC;
oEOF : OUT STD_LOGIC;
oSOF : OUT STD_LOGIC;
oCRCErr : OUT STD_LOGIC;
oRxErr : OUT STD_LOGIC;
oLenErr : OUT STD_LOGIC;
oCheckSumErr : OUT STD_LOGIC;
iMyMAC : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
oGetARP : OUT STD_LOGIC;
oGetIPv4 : BUFFER STD_LOGIC;
oGetCtrl : OUT STD_LOGIC;
oGetRaw : BUFFER STD_LOGIC;
oTaged : OUT STD_LOGIC;
oTagInfo : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
oStackTaged : BUFFER STD_LOGIC;
oTagInfo2 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
oLink : OUT STD_LOGIC;
oSpeed : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
oDuplex : OUT STD_LOGIC;
oPayloadLen : BUFFER UNSIGNED(15 DOWNTO 0);
oRxData : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
oRxDV : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL cSOF : STD_LOGIC;
SIGNAL cEof : STD_LOGIC;
SIGNAL cErrCrc : STD_LOGIC;
SIGNAL cErrLen : STD_LOGIC;
SIGNAL cGetArp : STD_LOGIC;
SIGNAL cErrCheckSum : STD_LOGIC;
SIGNAL cGetIPv4 : STD_LOGIC;
SIGNAL cGetCtrl : STD_LOGIC;
SIGNAL cGetRaw : STD_LOGIC;
SIGNAL cPayloadLen : UNSIGNED(15 DOWNTO 0);
SIGNAL cRxData : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL cRxDV : STD_LOGIC;
begin
rgmii_rx_1 : ENTITY work.rgmii_rx
PORT MAP (
iClk => iEthClk,
iRst_n => iRst_n,
iRxData => iEnetRxData,
iRxDV => iEnetRxDv,
iRxEr => iEnetRxErr,
iCheckSumIPCheck => iCheckSumIPCheck,
iCheckSumTCPCheck => iCheckSumTCPCheck,
iCheckSumUDPCheck => iCheckSumUDPCheck,
iCheckSumICMPCheck => iCheckSumICMPCheck,
oEOF => cEof,
oCRCErr => cErrCrc,
oRxErr => OPEN,
oLenErr => cErrLen,
oCheckSumErr => cErrCheckSum,
iMyMAC => iMAC_HAL,--MY_MAC,
oGetARP => cGetArp,
oGetIPv4 => cGetIPv4,
oGetCtrl => cGetCtrl,
oGetRaw => cGetRaw,
oSOF => cSOF,
oTaged => OPEN,
oTagInfo => OPEN,
oStackTaged => OPEN,
oTagInfo2 => OPEN,
oLink => OPEN,
oSpeed => OPEN,
oDuplex => OPEN,
oPayloadLen => cPayloadLen,
oRxData => cRxData,
oRxDV => cRxDV
);
-- rgmii_rx_2 : ENTITY work.rgmii_rx_2
-- PORT MAP(
-- iClk => iEthClk,
-- iRst_n => iRst_n,
--
-- iRxData => iEnetRxData,
-- iRxDV => iEnetRxDv,
-- iRxEr => iEnetRxErr,
--
-- iMAC_FPGA => iMAC_HAL,
--
-- iUdpRdy => iUDP_rx_rdy,
-- oRxData => cRxData,
-- oRxDV => cRxDV,
-- oEOF => cEof
-- );
oData_rx <= cRxData;
oData_valid <= cRxDV;
oSOF <= cSOF;
oEOF <= cEof;
end architecture; | gpl-3.0 | d46b6bfd2b3840444df27d20d946377f | 0.556643 | 3.036404 | false | false | false | false |
hoglet67/ElectronFpga | src/altera/ElectronULA_max10.vhd | 1 | 56,059 | --------------------------------------------------------------------------------
-- Copyright (c) 2016 David Banks
-- Copyright (c) 2019 Google LLC
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-- TODO figure out how to emulate BBC/Master keyboard reads using an internal CPU
entity ElectronULA_max10 is
generic (
-- Set this when running on board #1 with 74lvth162245 bus hold buffers
UsingBoardId1WithBusHoldBuffers : boolean := false;
-- Set this to true to generate SDRAM clock from PLL
FastSDRAM : boolean := true;
-- Set this to map banks 0-3 to flash
Banks_0_1_InFlash : boolean := true;
Banks_2_3_InFlash : boolean := true;
-- Set this to map banks 12-15 to flash
Banks_12_13_14_15_InFlash : boolean := true;
-- Set this to map banks 4-7 to RAM
Banks_4_5_6_7_InRAM : boolean := true;
-- Set this to true to include an internal 6502 core.
-- You MUST remove the CPU from the main board when doing this,
-- as the ULA will drive the address bus and RnW.
InternalCPU : boolean := true;
-- Set this to output a clock low edge *before* clocking the CPU, so external
-- devices have time to latch address and data.
AdvanceExternalClock : boolean := true;
-- Set this as true to include the experimental DAC code
IncludeAudio : boolean := true;
-- Set this as true to include JAFA Mode 7 support
IncludeMode7 : boolean := true;
-- Set this as true to include Mega Games Cartridge emulation
IncludeMGC : boolean := true;
-- Set this as true to include Plus1 emulation
IncludePlus1 : boolean := true
);
port (
-- 16 MHz clock from Electron
clk_in : in std_logic;
-- 16 MHz clock from oscillator
clk_osc : in std_logic;
-- QSPI flash chip
flash_nCE : out std_logic := '1'; -- pulled high on board
flash_SCK : out std_logic := '0';
flash_IO0 : inout std_logic := 'Z'; -- MOSI
flash_IO1 : inout std_logic := 'Z'; -- MISO
flash_IO2 : inout std_logic := 'Z'; -- /WP
flash_IO3 : inout std_logic := 'Z'; -- /HOLD or /RESET
-- SDRAM
sdram_DQ : inout std_logic_vector(15 downto 0) := (others => 'Z');
sdram_A : out std_logic_vector(12 downto 0) := (others => '1');
sdram_BA : out std_logic_vector(1 downto 0) := (others => '1');
sdram_nCS : out std_logic := '1'; -- pulled high on board
sdram_nWE : out std_logic := '1';
sdram_nCAS : out std_logic := '1';
sdram_nRAS : out std_logic := '1';
sdram_CLK : out std_logic := '1';
sdram_CKE : out std_logic := '0'; -- active high
sdram_UDQM : out std_logic := '1'; -- active low
sdram_LDQM : out std_logic := '1';
-- USB
USB_M : inout std_logic := 'Z';
USB_P : inout std_logic := 'Z';
USB_PU : out std_logic := 'Z';
-- Enable input buffer for kbd[3:0], NMI_n_in, IRQ_n_in, RnW_in, clk_in
input_buf_nOE : out std_logic := '0'; -- pulled high on board
-- Enable output buffer for clk_out, nHS, red, green, blue, csync, casMO, casOut
misc_buf_nOE : out std_logic := '0'; -- pulled high on board
-- CPU Interface
clk_out : out std_logic;
A_buf_nOE : out std_logic := '0'; -- default on; pulled high on board
A_buf_DIR : out std_logic := '1'; -- default to buffer from Elk to FPGA
addr : inout std_logic_vector(15 downto 0);
D_buf_nOE : out std_logic := '1'; -- default off; pulled high on board
D_buf_DIR : out std_logic := '1'; -- default to buffer from Elk to FPGA
data : inout std_logic_vector(7 downto 0);
RnW_in : in std_logic;
RnW_out : out std_logic := '1';
RnW_nOE : out std_logic := '1'; -- pulled high on board
RST_n_out : out std_logic := '1'; -- pulled high on board
RST_n_in : in std_logic;
IRQ_n_out : out std_logic := '1'; -- pulled high on board
IRQ_n_in : in std_logic;
NMI_n_in : in std_logic;
-- Rom Enable
ROM_n : out std_logic;
-- Video
red : out std_logic;
green : out std_logic;
blue : out std_logic;
csync : out std_logic;
HS_n : out std_logic := '1'; -- TODO is this unused?
-- Audio DAC
dac_dacdat : out std_logic := '0'; -- DAC data
dac_lrclk : out std_logic := '0'; -- Left/right clock
dac_bclk : out std_logic := '0'; -- Bit clock
dac_mclk : out std_logic := '0'; -- Master clock
dac_nmute : out std_logic := '0'; -- '0' for standby mode
-- Keyboard
kbd : in std_logic_vector(3 downto 0);
caps : out std_logic;
-- Cassette
casIn : in std_logic;
casOut : out std_logic;
casMO : out std_logic := '1';
-- SD card
sd_CLK_SCK : out std_logic;
sd_CMD_MOSI : out std_logic;
sd_DAT0_MISO : in std_logic;
sd_DAT1 : inout std_logic := 'Z';
sd_DAT2 : inout std_logic := 'Z';
sd_DAT3_nCS : out std_logic; -- pulled high on board
-- serial port
serial_RXD : out std_logic := '1'; --DEBUG in std_logic;
serial_TXD : out std_logic := '1';
-- Debug MCU interface
mcu_debug_RXD : in std_logic; -- prepping to switch ports around; out std_logic := '1';
mcu_debug_TXD : in std_logic; -- currently used to switch SPI port between flash (0) and boundary scan (1)
mcu_MOSI : in std_logic;
mcu_MISO : out std_logic := '1';
mcu_SCK : in std_logic;
mcu_SS : in std_logic
);
end;
architecture behavioral of ElectronULA_max10 is
-- Need to declare this as a component because Quartus can't do entity
-- instantiation with Verilog modules.
component qpi_flash is
port (
clk : in std_logic;
ready : out std_logic;
reset : in std_logic;
read : in std_logic;
addr : in std_logic_vector(23 downto 0);
data_out : out std_logic_vector(7 downto 0);
passthrough : in std_logic;
passthrough_nCE : in std_logic;
passthrough_SCK : in std_logic;
passthrough_MOSI : in std_logic;
flash_nCE : out std_logic;
flash_SCK : out std_logic;
flash_IO0 : inout std_logic;
flash_IO1 : inout std_logic;
flash_IO2 : inout std_logic;
flash_IO3 : inout std_logic
);
end component qpi_flash;
-- Maps to either clk_in or clk_osc depending which one we are using
signal clock_input : std_logic;
-- Generated clocks:
signal clock_16 : std_logic;
-- signal clock_24 : std_logic; -- TODO remove, if clken_ttxt works
signal clock_32 : std_logic := '1';
signal clock_33 : std_logic;
signal clock_40 : std_logic;
signal clock_96 : std_logic := '1';
signal clock_96_sdram : std_logic := '1';
signal clock_div_96_24 : std_logic_vector(1 downto 0) := (others => '0');
signal clock_div_96_32 : std_logic_vector(1 downto 0) := (others => '0');
signal clken_ttxt_counter : std_logic_vector(3 downto 0) := (others => '0');
signal clken_ttxt : std_logic := '0';
-- Divide clock_16 down to ~1 Hz to blink the caps LED
signal blinky_div : std_logic_vector(24 downto 0) := (others => '0');
-- Divide 96MHz / 833 = 115246 baud serial
signal serial_tx_count : std_logic_vector(9 downto 0) := (others => '0');
signal serial_rx_count : std_logic_vector(9 downto 0) := (others => '0');
signal pll_reset : std_logic := '1';
signal pll_reset_counter : std_logic_vector(1 downto 0) := (others => '0');
signal pll1_locked : std_logic;
signal pll_locked_sync : std_logic_vector(2 downto 0) := (others => '0');
signal pll_locked_sync_96 : std_logic_vector(2 downto 0) := (others => '0');
signal led_counter : std_logic_vector(23 downto 0);
signal clk_counter : std_logic_vector(2 downto 0);
signal cpu_clken_from_ula : std_logic;
signal cpu_clken_dly : std_logic; -- cpu_clken_from_ula delayed one clock
signal cpu_clken : std_logic; -- Clocks CPU + internal memories. Either cpu_clken_from_ula or cpu_clken_dly
signal clk_out_int : std_logic;
signal cpu_clken_16_sync : std_logic;
signal cpu_clken_96_sync : std_logic_vector(2 downto 0);
-- will go high for one clock_96 cycle when A/D are valid for a write
signal start_write_96 : std_logic;
-- will go high for one clock_96 cycle when A is valid for a read
signal start_read_96 : std_logic;
-- one shot timer to generate start_read_96
signal wait_for_ads_counter : std_logic_vector(4 downto 0) := (others => '1');
signal kbd_access : std_logic;
signal bus_write_from_internal_device : std_logic;
signal rom_enable_n : std_logic;
signal ula_enable : std_logic;
signal ula_data_out : std_logic_vector(7 downto 0);
signal ula_irq_n : std_logic;
signal video_red : std_logic_vector(3 downto 0);
signal video_green : std_logic_vector(3 downto 0);
signal video_blue : std_logic_vector(3 downto 0);
signal video_hsync : std_logic;
signal video_vsync : std_logic;
signal rom_latch : std_logic_vector(3 downto 0);
signal powerup_reset_n : std_logic := '0';
signal reset_counter : std_logic_vector (15 downto 0);
signal RST_n_sync_16 : std_logic_vector(1 downto 0);
signal NMI_n_sync_16 : std_logic_vector(1 downto 0);
-- Active high reset for flash and SDRAM; will be high until ~42us after the PLL locks
signal memory_reset_96 : std_logic := '1';
signal reset_counter_96 : std_logic_vector(12 downto 0);
-- Outbound CPU signals when soft CPU is being used
signal cpu_addr : std_logic_vector(23 downto 0);
signal cpu_data_out : std_logic_vector(7 downto 0);
signal cpu_RnW_out : std_logic;
-- Internal variable for data bus
signal data_in : std_logic_vector(7 downto 0);
signal RnW : std_logic;
signal turbo : std_logic_vector(1 downto 0);
signal caps_led : std_logic;
signal sound_bit : std_logic;
signal audio_bit_clock : std_logic := '0';
signal audio_lr_clock : std_logic := '0';
signal audio_data_out : std_logic := '0';
signal audio_counter : std_logic_vector(5 downto 0) := (others => '0');
signal audio_shifter : std_logic_vector(15 downto 0) := (others => '0');
-- SPI comms with microcontroller
signal mcu_MOSI_sync : std_logic_vector(2 downto 0) := "000";
signal mcu_SS_sync : std_logic_vector(2 downto 0) := "111";
signal mcu_SCK_sync : std_logic_vector(2 downto 0) := "000";
signal mcu_shifter : std_logic_vector(7 downto 0) := (others => '0');
signal mcu_shift_count : std_logic_vector(2 downto 0) := (others => '0');
signal mcu_shifter_byte : std_logic_vector(7 downto 0);
signal mcu_MISO_int : std_logic;
signal mcu_state : std_logic_vector(7 downto 0); -- state machine state
signal mcu_flash_passthrough : std_logic := '0'; -- sticky passthrough bit
signal mcu_flash_spi : std_logic := '0'; -- connect MCU to flash
signal mcu_flash_spi_clocking : std_logic := '0'; -- '0' during first clock cycle after connecting MCU to flash
--signal mcu_flash_qpi : std_logic := '0'; -- connect MCU to flash
--signal mcu_flash_qpi_cmd : std_logic := '0'; -- '1' when reading QPI rnw/command over SPI
--signal mcu_flash_qpi_rnw : std_logic := '1'; -- QPI RnW
--signal mcu_flash_qpi_txn : std_logic := '0'; -- QPI strobe
--signal mcu_flash_qpi_counter : std_logic_vector(1 downto 0);
-- debug boundary scan over SPI
signal boundary_scan : std_logic := '0';
signal debug_boundary_vector : std_logic_vector(47 downto 0);
-- USB serial port on FCA1 (status), FCA0 (data)
signal usb_serial_enable : std_logic := '0';
signal usb_serial_data : std_logic_vector(7 downto 0);
signal usb_elk_rx_reading : std_logic := '0';
signal usb_elk_rx_empty : std_logic := '0';
signal usb_elk_rx_byte : std_logic_vector(7 downto 0);
signal usb_elk_tx_full : std_logic := '0';
signal usb_elk_tx_byte : std_logic_vector(7 downto 0);
signal usb_elk_remote_has_byte : std_logic := '0';
signal usb_elk_tx_full_sent : std_logic := '0';
signal usb_elk_rx_empty_sent : std_logic := '0';
signal empty_bank_enable : std_logic;
signal flash_enable : std_logic := '0';
signal flash_bank : std_logic_vector(7 downto 0) := x"00"; -- bits 23-16 of flash address
signal flash_addr : std_logic_vector(23 downto 0);
signal flash_data_out : std_logic_vector(7 downto 0) := x"FF";
signal flash_ready : std_logic;
signal flash_reset : std_logic := '0';
signal flash_read : std_logic;
signal sdram_enable : std_logic; -- SDRAM selected by CPU
signal sdram_clken : std_logic := '0'; -- 48MHz clock enable
signal sdram_address : std_logic_vector(23 downto 0);
signal sdram_ready : std_logic;
signal sdram_done : std_logic;
signal sdram_data_out : std_logic_vector(15 downto 0) := x"8442";
--signal sdram_init : std_logic := '1'; -- Power on reset for sdram
signal sdram_access : std_logic := '0';
signal sdram_writing : std_logic;
signal sdram_refreshing : std_logic;
signal sdram_check_refresh : std_logic;
signal sdram_low_bank_en : std_logic;
signal sdram_high_bank_en : std_logic;
signal sdram_refresh_counter : std_logic_vector(4 downto 0) := (others => '0'); -- kicked off after cpu_clken
-- SAA5050 character ROM loader (copies from QPI flash to SAA5050 block RAM)
signal char_rom_loaded : std_logic := '0'; -- Holds system in reset until it transitions to '1'
signal char_rom_state : std_logic_vector(1 downto 0) := "00";
signal char_rom_read : std_logic := '0'; -- Read strobe to QPI controller
signal char_rom_we : std_logic := '0'; -- Write strobe to SAA5050 block RAM
signal char_rom_start : std_logic_vector(23 downto 0) := x"FFC000"; -- Char ROM lives in flash-16k (first 8k is MODE 7 ROM)
signal char_rom_addr : std_logic_vector(12 downto 0) := (others => '0'); -- "done" bit + 4k address counter
-- MGC registers
signal mgc_bank : std_logic_vector(6 downto 0) := (others => '0'); -- Low seven bits of the bank ID
signal mgc_high_bank : std_logic := '0'; -- High bit of the bank ID if mgc_use_both_banks==1
signal mgc_use_both_banks : std_logic := '0'; -- 0 to use two banks, 1 to use one
signal mgc_flash_addr : std_logic_vector(23 downto 0);
-- Plus 1 registers
signal plus1_status_selected : std_logic;
begin
--------------------------------------------------------
-- Debug SPI port + USB serial port
--------------------------------------------------------
-- SPI interface with mcu
spi : process(clock_96)
begin
if rising_edge(clock_96) then
-- Synchronous SPI; 48MHz ATSAMD MCU can do 12 MHz max, so we have plenty of time
-- Assume 12 MHz master, so we have 8 clocks per master clock.
-- clk 0 - sck=0 sync(0)=0 sync(1)=0 sync(2)=0
-- clk 1 - sck=1 sync(0)=0 sync(1)=0 sync(2)=0 -- master clocks in bit from us now
-- clk 2 - sck=1 sync(0)=1 sync(1)=0 sync(2)=0
-- clk 3 - sck=1 sync(0)=1 sync(1)=1 sync(2)=0
-- edge detected; our activity affects clk 4
-- clk 4 - sck=1 sync(0)=1 sync(1)=1 sync(2)=1
-- clk 5 - sck=1 sync(0)=1 sync(1)=1 sync(2)=1
-- clk 6 - sck=1 sync(0)=1 sync(1)=1 sync(2)=1
-- clk 7 - sck=1 sync(0)=1 sync(1)=1 sync(2)=1
-- clk 8 - sck=1 sync(0)=1 sync(1)=1 sync(2)=1
-- clk 9 - sck=0 sync(0)=1 sync(1)=1 sync(2)=1
-- clk 10 - sck=0 sync(0)=0 sync(1)=1 sync(2)=1
-- clk 11 - sck=0 sync(0)=0 sync(1)=0 sync(2)=1
-- edge detected; our activity affects clk 12
-- clk 12 - sck=0 sync(0)=0 sync(1)=0 sync(2)=0
-- clk 13 - sck=0 sync(0)=0 sync(1)=0 sync(2)=0
-- clk 14 - sck=0 sync(0)=0 sync(1)=0 sync(2)=0
-- clk 15 - sck=0 sync(0)=0 sync(1)=0 sync(2)=0
-- clk 16 - sck=0 sync(0)=0 sync(1)=0 sync(2)=0
-- clk 17 - sck=1 sync(0)=0 sync(1)=0 sync(2)=0 -- master clocks in bit from us now
-- clk 18 - sck=1 sync(0)=1 sync(1)=0 sync(2)=0
-- MOSI is stable except around clocks 10-13, so it should be
-- pretty safe for us to do everything in clock 3, and copy
-- mcu_shifter(7) into mcu_MISO_int on every clock. That way
-- we'll update MISO around clock 5.
-- SCK rise: detected
mcu_MOSI_sync <= mcu_MOSI_sync(1 downto 0) & mcu_MOSI;
mcu_SCK_sync <= mcu_SCK_sync(1 downto 0) & mcu_SCK;
mcu_SS_sync <= mcu_SS_sync(1 downto 0) & mcu_SS;
flash_reset <= '0';
if mcu_SS_sync(1) = '1' then
-- SS high; reset everything
mcu_shifter <= x"AA";
mcu_shift_count <= "000";
mcu_state <= x"00";
mcu_flash_spi <= '0';
mcu_flash_spi_clocking <= '0';
--mcu_flash_qpi <= '0';
--mcu_flash_qpi_cmd <= '0';
--mcu_flash_qpi_txn <= '0';
--mcu_flash_qpi_counter <= "00";
else
-- SS low
mcu_MISO_int <= mcu_shifter(7);
if mcu_SCK_sync(2) = '0' and mcu_SCK_sync(1) = '1' then
-- rising SCK edge happened 2-3 cycles ago
--mcu_MISO_int <= mcu_shifter(6);
mcu_shifter <= mcu_shifter_byte; -- {mcu_shifter[6:0], mcu_MOSI_sync[2]}
mcu_shift_count <= mcu_shift_count + 1;
if mcu_shift_count = "111" then
-- just received a byte: mcu_shifter_byte
case mcu_state is
when x"00" => -- command byte
mcu_state <= mcu_shifter_byte;
mcu_shifter <= x"55"; -- debug
case mcu_shifter_byte is
when x"02" =>
-- pass remainder of transaction through to flash
mcu_flash_spi <= '1';
--when x"03" =>
-- -- Starting a QPI flash transaction
-- flash_nCE <= '0';
-- mcu_flash_qpi <= '1';
-- mcu_flash_qpi_cmd <= '1';
when x"05" =>
-- Boundary scan
debug_boundary_vector <=
"10101010" & -- AA
x"FFFF" & flash_data_out &
-- addr & -- FF FF
-- data & -- FF
RnW & '0' & powerup_reset_n & RST_n_in & powerup_reset_n & IRQ_n_in & ula_irq_n & NMI_n_in & -- BF
kbd & '1' & '1' & '1' & '1'; -- FF
when x"07" =>
-- USB serial port transaction
-- Bit 0 set if we have buffer space to receive a byte
-- Bit 1 set if we have a byte to send to the MCU
mcu_shifter <= "000000" & usb_elk_tx_full & (usb_elk_rx_empty and not usb_elk_rx_reading);
usb_elk_tx_full_sent <= usb_elk_tx_full;
usb_elk_rx_empty_sent <= usb_elk_rx_empty and not usb_elk_rx_reading;
when others =>
end case;
when x"01" => -- configure passthrough
-- Bit 0 = flash passthrough (send 01 01 to set passthrough, 01 00 to unset)
mcu_flash_passthrough <= mcu_shifter_byte(0);
when x"02" => -- SPI to flash; no-op
--when x"03" => -- QPI to flash
-- -- Begin QPI tx/rx byte
-- -- Alternate command / data bytes
-- if mcu_flash_qpi_cmd = '1' then
-- -- Just read a command byte: 0 for tx, 1 for rx
-- if mcu_shifter_byte(0) = '0' then
-- -- TX
-- mcu_flash_qpi_rnw <= '0'; -- TX
-- mcu_flash_qpi_cmd <= '0'; -- Next byte is data
-- else
-- -- RX
-- mcu_flash_qpi_rnw <= '1'; -- RX
-- mcu_flash_qpi_txn <= '1'; -- Read now
-- end if;
-- else
-- -- Just read a data byte for a TX transaction
-- mcu_flash_qpi_cmd <= '1'; -- Next byte is command
-- mcu_flash_qpi_txn <= '1'; -- Write now
-- end if;
-- -- Result reads out during the next command byte.
when x"04" => -- NOP state; we end up here after a serial port transaction
when x"05" => -- Boundary scan
-- Copy in the next byte
mcu_shifter <= debug_boundary_vector(47 downto 40);
--mcu_MISO_int <= debug_boundary_vector(47); -- work around off by one error
debug_boundary_vector <= debug_boundary_vector(39 downto 0) & x"00";
when x"06" => -- Reset flash (06 00)
flash_reset <= '1';
when x"07" => -- USB serial port byte 1 of 2 (status)
-- mcu_shifter_byte contains remote status
-- Remote has buffer space if mcu_shifter_byte(0) is set
if usb_elk_tx_full_sent = '1' and mcu_shifter_byte(0) = '1' then
mcu_shifter <= usb_elk_tx_byte;
usb_elk_tx_full <= '0';
end if;
-- Remote has a byte for us if mcu_shifter_byte(1) is set
usb_elk_remote_has_byte <= mcu_shifter_byte(1);
mcu_state <= x"08";
when x"08" => -- USB serial port byte 2 of 2 (data)
if usb_elk_rx_empty_sent = '1' and usb_elk_remote_has_byte = '1' then
usb_elk_rx_byte <= mcu_shifter_byte;
usb_elk_rx_empty <= '0';
end if;
mcu_state <= x"04";
when others =>
end case;
end if;
elsif mcu_SCK_sync(2) = '1' and mcu_SCK_sync(1) = '0' then
-- falling SCK edge
if mcu_flash_spi = '1' then
-- We've just started SPI passthrough and have been waiting
-- for mcu_SCK to go low before starting to buffer it.
mcu_flash_spi_clocking <= '1';
end if;
end if;
end if;
-- QPI transaction (quick enough to perform between mcu_SCK clock edges!)
--if mcu_flash_qpi_txn = '1' then
-- mcu_flash_qpi_counter <= mcu_flash_qpi_counter + 1;
-- if mcu_flash_qpi_counter(0) = '1' then
-- if mcu_flash_qpi_rnw = '1' then
-- -- RX; clock data from flash_IO* into mcu_shifter
-- mcu_shifter <= mcu_shifter(3 downto 0) & flash_IO3 & flash_IO2 & flash_IO1 & flash_IO0;
-- else
-- -- TX; shift mcu_shifter to update flash_IO*
-- mcu_shifter <= mcu_shifter(3 downto 0) & "0000";
-- end if;
-- if mcu_flash_qpi_counter(1) = '1' then
-- mcu_flash_qpi_txn <= '0'; -- Done!
-- end if;
-- end if;
--end if;
-- Override all that if we're passing SPI through to the flash
if mcu_flash_spi_clocking = '1' then
mcu_MISO_int <= flash_IO1;
end if;
-- USB serial port: CPU interface
if usb_serial_enable = '1' and addr(0) = '0' then
if start_read_96 = '1' then
if usb_elk_rx_empty = '0' then
-- Flag that we're reading from the serial port to keep data
-- stable for the next clock
usb_elk_rx_reading <= '1';
usb_elk_rx_empty <= '1';
end if;
end if;
if start_write_96 = '1' then
-- Writing serial data
if usb_elk_tx_full = '0' then
usb_elk_tx_byte <= data_in;
usb_elk_tx_full <= '1';
end if;
end if;
end if;
-- Clear the "CPU reading; don't overwrite data" flag
if start_read_96 = '1' and usb_elk_rx_reading = '1' then
usb_elk_rx_reading <= '0';
end if;
end if;
end process;
mcu_shifter_byte <= mcu_shifter(6 downto 0) & mcu_MOSI_sync(2);
mcu_MISO <= mcu_MISO_int;
-- USB serial port: CPU interface
usb_serial_enable <= '1' when addr = x"FCA0" or addr = x"FCA1" else '0';
-- Bit 1 set if we can send a byte (!tx_full); bit 0 set if we have received a byte (!rx_empty)
usb_serial_data <= "000000" & (not usb_elk_tx_full) & (not usb_elk_rx_empty) when addr(0) = '1' else usb_elk_rx_byte;
-- DEBUG I/O
-- mcu_debug_RXD <= mcu_debug_TXD; -- loopback serial for MCU debugging
--serial_TXD <= '1' when serial_tx_count < 417 else '0'; -- verified on scope
--serial_TXD <= clock_16; -- verified on scope
--serial_TXD <= cpu_clken; -- verified on scope
--serial_TXD <= clk_out_int; -- verified on scope
--serial_TXD <= audio_bit_clock; -- verified 8MHz
--serial_TXD <= audio_data_out;
--serial_RXD <= kbd(3);
--serial_RXD <= kbd_access;
--serial_RXD <= audio_lr_clock; -- verified 125 kHz
--serial_RXD <= flash_ready; -- goes low for 0.26 us (250 ns in simulation, so that's about right)
--serial_TXD <= sdram_ready;
--serial_RXD <= sdram_done;
-- char_rom_read and char_rom_we both go high for 0.7141 s, i.e. 174 us * 4096
-- then there's a 1.109 ms period where they behave as expected
-- with a pulse on read every 0.27 us. so that's probably the full char rom read happening.
serial_TXD <= char_rom_read;
--serial_RXD <= char_rom_we;
serial_RXD <= flash_ready;
--------------------------------------------------------
-- ULA
--------------------------------------------------------
ula : entity work.ElectronULA
generic map (
IncludeMMC => true,
Include32KRAM => true,
IncludeVGA => false,
IncludeJafaMode7 => IncludeMode7,
UseClockMux => true,
UseTTxtClock => true,
IncludeTTxtROM => false
)
port map (
clk_16M00 => clock_16,
--clk_24M00 => clock_24,
clk_32M00 => clock_32,
clk_33M33 => clock_33,
clk_40M00 => clock_40,
clk_ttxt => clock_96,
clken_ttxt_12M => clken_ttxt,
-- CPU Interface
addr => addr,
data_in => data_in,
data_out => ula_data_out,
data_en => ula_enable,
R_W_n => RnW,
RST_n => RST_n_sync_16(1),
IRQ_n => ula_irq_n, -- IRQ output from ULA
NMI_n => NMI_n_sync_16(1),
-- Rom Enable
ROM_n => rom_enable_n,
-- Video
red => video_red,
green => video_green,
blue => video_blue,
vsync => video_vsync,
hsync => video_hsync,
-- Audio
sound => sound_bit,
-- SD Card
SDMISO => sd_DAT0_MISO,
SDSS => sd_DAT3_nCS,
SDCLK => sd_CLK_SCK,
SDMOSI => sd_CMD_MOSI,
-- Casette
casIn => casIn,
casOut => casOut,
-- Keyboard
kbd => kbd,
-- MISC
caps => caps_led,
motor => casMO,
rom_latch => rom_latch,
mode_init => "00",
-- Clock Generation
cpu_clken_out => cpu_clken_from_ula,
cpu_clk_out => clk_out_int,
turbo => turbo,
turbo_out => turbo,
-- SAA5050 character ROM loading
char_rom_we => char_rom_we,
char_rom_addr => char_rom_addr(11 downto 0),
char_rom_data => flash_data_out
);
ROM_n <= rom_enable_n;
red <= video_red(3);
green <= video_green(3);
blue <= video_blue(3);
csync <= video_hsync;
caps <= not caps_led;
-- Generate delayed cpu_clken, to provide hold time for external devices
cpu_clken_gen : process(clock_16)
begin
if rising_edge(clock_16) then
cpu_clken_dly <= cpu_clken_from_ula;
end if;
end process;
cpu_clken <= cpu_clken_dly when AdvanceExternalClock else cpu_clken_from_ula;
-- Blink CAPS at 1 Hz
--blink_caps : process(clock_16)
--begin
-- if rising_edge(clock_16) then
-- blinky_div <= blinky_div + 1;
-- end if;
--end process;
--caps <= blinky_div(blinky_div'high);
-- Light up CAPS on reset
--caps <= RST_n_sync_16(1);
-- IRQ_n_out drives the enable on an open collector buffer which pulls the external IRQ line down
IRQ_n_out <= ula_irq_n;
-- CPU data bus and RnW signal
data_in <= data;
RnW <= cpu_RnW_out when InternalCPU else RnW_in;
-- '1' when the CPU is reading from a device on the ULA PCB
bus_write_from_internal_device <= '1' when RnW = '1' and (
empty_bank_enable = '1'
or flash_enable = '1' -- Output from flash
or sdram_enable = '1' -- Output from SDRAM
or ula_enable = '1' -- Output from ULA
or usb_serial_enable = '1' -- Output from USB serial port
) else '0';
-- '0' to enable data bus buffer
D_buf_nOE <= '0' when (
InternalCPU -- Input to/output from internal CPU
or boundary_scan = '1' -- Input to boundary scan
or bus_write_from_internal_device = '1' -- Something local wants to write to the bus
or RnW = '0' -- External CPU is writing
) else '1';
-- DIR=1 buffers from Elk to FPGA, DIR=0 buffers from FPGA to Elk
D_buf_DIR <=
-- outwards when something local is writing to the bus
'0' when bus_write_from_internal_device = '1' else
-- inwards when the internal CPU is reading, outwards when it is writing
RnW when InternalCPU else
-- inwards when external CPU is writing
'1' when RnW = '0' else
-- inwards during boundary scan
'1' when boundary_scan = '1' else
-- default outwards (buffer should be disabled)
'0';
-- Order here should match D_buf_DIR expression above.
data <= ula_data_out when RnW = '1' and ula_enable = '1' else
x"FF" when RnW = '1' and empty_bank_enable = '1' else
x"FF" when RnW = '1' and plus1_status_selected = '1' else
flash_data_out when RnW = '1' and flash_enable = '1' else
sdram_data_out(15 downto 8) when RnW = '1' and sdram_enable = '1' and addr(0) = '1' else
sdram_data_out(7 downto 0) when RnW = '1' and sdram_enable = '1' and addr(0) = '0' else
usb_serial_data when RnW = '1' and usb_serial_enable = '1' else
cpu_data_out when RnW = '0' and InternalCPU else
"ZZZZZZZZ"; -- ext CPU, RnW = '0' or boundary_scan = '1'
--------------------------------------------------------
-- Internal CPU (optional)
--------------------------------------------------------
-- Plus 1 status register:
-- D4 = joystick fire button 0
-- D5 = joystick fire button 1
-- D6 = analog chip select
-- D7 = parallel port status
plus1_status_selected <= '1' when IncludePlus1 and addr = x"FC72" else '0';
-- Plus 1 analog data register
-- plus1_analog_selected <= '1' when IncludePlus1 and addr = x"FC70" else '0';
--------------------------------------------------------
-- Internal CPU (optional)
--------------------------------------------------------
GenCPU: if InternalCPU generate
T65core : entity work.T65
port map (
Mode => "00",
Abort_n => '1',
SO_n => '1', -- Signal not routed to the ULA
Res_n => RST_n_in,
Enable => cpu_clken,
Clk => clock_16,
Rdy => '1', -- Signal not routed to the ULA
IRQ_n => IRQ_n_in,
NMI_n => NMI_n_in,
R_W_n => cpu_RnW_out,
Sync => open, -- Signal not routed to the ULA
A => cpu_addr,
DI => data_in,
DO => cpu_data_out
);
-- Buffer address outwards
addr <= cpu_addr(15 downto 0);
A_buf_DIR <= '0';
-- Buffer RnW outwards
RnW_out <= cpu_RnW_out;
RnW_nOE <= '0';
end generate;
--------------------------------------------------------
-- Audio DAC
--------------------------------------------------------
GenDAC: if IncludeAudio generate
-- Simple I2S implementation for 1-bit mono output to the WM8524 DAC
-- Master clock runs at 16 MHz
-- Divide by 128 to get fs = 125 kHz sample rate
-- We need 17 BCLK times per sample because I2S requires a dummy BCLK cycle after a LRCLK transition
-- So BCLK >= fs * 17 * 2 = 6.375 MHz. 8 MHz is convenient so we'll use that.
-- So we have 64 BCLK periods per sample, or 32 per channel.
-- DACDAT and LRCLK inputs are sampled on the rising edge of BCLK, and need 7ns setup / 5ns hold.
-- BCLK has a period of 125ns so it's easy to meet these by just changing them on its falling edge.
dac_nmute <= '1';
dac_mclk <= clock_16;
dac_bclk <= audio_bit_clock;
dac_lrclk <= audio_lr_clock;
dac_dacdat <= audio_data_out;
i2s_process : process(clock_16)
begin
if rising_edge(clock_16) then
audio_bit_clock <= not audio_bit_clock;
if audio_bit_clock = '1' then
-- Update LRCLK and DACDAT on falling edge of BCLK
audio_counter <= audio_counter + 1;
audio_lr_clock <= audio_counter(5);
audio_data_out <= audio_shifter(15);
audio_shifter <= audio_shifter(14 downto 0) & '0';
-- Reload audio_shifter one clock after changing dac_lrclk
if audio_counter(4 downto 0) = "00000" then
--audio_shifter <= sound_bit & "000000000000000"; -- Full volume
audio_shifter <= "0" & sound_bit & "00000000000000"; -- Half volume
end if;
end if;
end if;
end process;
end generate;
NoGenDAC: if not IncludeAudio generate
-- Standby mode
dac_bclk <= clock_16;
dac_mclk <= clock_16;
dac_nmute <= '0';
end generate;
--------------------------------------------------------
-- Sideways bank enable logic
--------------------------------------------------------
-- Drive data bus with FF when nothing else is (required with bus hold buffers in v1)
empty_bank_enable <= '1' when (
UsingBoardId1WithBusHoldBuffers
and addr(15 downto 14) = "10"
and rom_latch >= 12
and rom_enable_n = '1' and flash_enable = '0' and sdram_enable = '0' and ula_enable = '0'
) else '0';
-- Sideways RAM
sdram_enable <= '1' when Banks_4_5_6_7_InRAM and addr(15 downto 14) = "10" and (rom_latch >= 4 and rom_latch < 8) else '0';
-- Provide ROMs using the QPI flash chip
flash_enable <= '1' when addr(15 downto 14) = "10" and (
(Banks_0_1_InFlash and rom_latch < 2)
or (Banks_2_3_InFlash and rom_latch >= 2 and rom_latch < 4)
or (Banks_12_13_14_15_InFlash and rom_latch >= 12)
) else '0';
-- Right now this maps to the first 16 x 16kB = 256kB of flash.
flash_addr <= char_rom_start + char_rom_addr(11 downto 0) when char_rom_read = '1'
else mgc_flash_addr when IncludeMGC and (rom_latch = 2 or rom_latch = 3)
else "000000" & rom_latch & addr(13 downto 0);
mgc_flash_addr <= "01" & (not mgc_high_bank) & mgc_bank & addr(13 downto 0) when mgc_use_both_banks = '1'
else "01" & rom_latch(0) & mgc_bank & addr(13 downto 0);
--------------------------------------------------------
-- SDRAM
--------------------------------------------------------
fast_sdram_clock : if FastSDRAM generate
sdram_CLK <= clock_96_sdram;
end generate;
gen_sdram_ctrls : process (clock_96)
begin
if rising_edge(clock_96) then
-- Signals from the controller update on cycles where sdram_clken = '1',
-- i.e. we should output a rising clock edge then.
-- Reset all triggers once the SDRAM has seen them.
if sdram_clken = '1' then
sdram_access <= '0';
sdram_refreshing <= '0';
end if;
if FastSDRAM then
-- SDRAM controller is active on every cycle when clocking at 96MHz
sdram_clken <= '1';
else
-- Clock it at 48 MHz, so I don't have to care too much about timing analysis
sdram_clken <= not sdram_clken;
sdram_CLK <= sdram_clken;
end if;
if (start_write_96 = '1' or start_read_96 = '1') and sdram_enable = '1' then
-- Set flags that need to stick around until a cycle where the SDRAM clock is enabled
sdram_access <= '1';
sdram_writing <= RnW;
sdram_address <= "0000000" & rom_latch(3 downto 0) & addr(13 downto 1);
sdram_high_bank_en <= not addr(0);
sdram_low_bank_en <= addr(0);
end if;
-- Generate refresh signal
if sdram_refresh_counter = 24 then
sdram_refreshing <= '1';
end if;
end if;
end process;
sdram_controller : entity work.sdram_simple PORT MAP (
-- Host side
clk_100m0_i => clock_96,
clk_en => sdram_clken,
reset_i => memory_reset_96,
refresh_i => sdram_refreshing,
rw_i => sdram_access,
we_i => sdram_writing,
addr_i => sdram_address,
data_i => data & data,
ub_i => sdram_high_bank_en,
lb_i => sdram_low_bank_en,
ready_o => sdram_ready,
done_o => sdram_done,
data_o => sdram_data_out,
-- SDRAM side
sdCke_o => sdram_CKE,
sdCe_bo => sdram_nCS,
sdRas_bo => sdram_nRAS,
sdCas_bo => sdram_nCAS,
sdWe_bo => sdram_nWE,
sdBs_o => sdram_BA,
sdAddr_o => sdram_A,
sdData_io => sdram_DQ,
sdDqmh_o => sdram_UDQM,
sdDqml_o => sdram_LDQM
);
-- TODO move all of this into ula_sdram.v
-- TODO start sdram read when start_read_96 = '1' and ram is selected
-- TODO start sdram write when start_write_96 = '1' and ram is selected
-- We clock the SDRAM at 96MHz, i.e. there are 24 cycles in 250 ns and 48 in 500 ns.
-- Two possibilities in a clock cycle:
-- start_write_96 asserted at start of PHI1 period; write takes the next 62.5 ns
-- start_read_96 asserted at PHI1+tADS; read takes the next 62.5 ns
-- In all cases, if it's time for a refresh (about every 7 us), we have
-- time for that after a read or write.
-- In 4MHz operation (250 ns clock), start_read_96 = PHI1+70ns, so we're done after 132.5 ns.
-- In 2MHz operation (500 ns clock), start_read_96 = PHI1+177ns, so we're done after 240 ns.
-- 0: ACTIVE -- nCS=0 RAS=0 CAS=1 WE=1 addr=row BA=bank
-- 1: NOP -- nCS=0 RAS=1 CAS=1 WE=1
-- 2: READ -- nCS=0 RAS=1 CAS=0 WE=1 addr=col BA1:0=bank A10=1 (enable auto precharge)
-- 3: NOP -- nCS=0 RAS=1 CAS=1 WE=1
-- 4: NOP -- register output data here
-- 5: NOP
-- 6: NOP
-- 7: NOP -- Now switch to refresh mode
-- 8: AUTO REFRESH --
-- 9: nCS=1
-- sdram_loop : process(clock_96)
-- begin
-- if rising_edge(clock_96) then
-- sdram_check_refresh <= '0';
--
-- if sdram_init = '1' then
-- if memory_reset_96 = '0' then
-- -- We're out of reset; start the SDRAM init process
-- sdram_CKE <= '1';
-- end if;
-- elsif sdram_reading = '1' then
-- elsif sdram_writing = '1' then
-- elsif sdram_refreshing = '1' then
-- end if;
--
-- if start_write_96 = '1' then
-- if sdram_enable = '1' then
-- sdram_writing <= '1';
-- else
-- sdram_check_refresh <= '1';
-- end if;
-- elsif start_read_96 = '1' then
-- if sdram_enable = '1' then
-- sdram_reading <= '1';
-- else
-- sdram_check_refresh <= '1';
-- end if;
-- end if;
--
-- if sdram_check_refresh = '1' then
-- -- TODO check sdram refresh timer and kick off a refresh if so
-- end if;
--
-- -- reset everything if we're just powering up
-- if memory_reset_96 = '1' then
-- sdram_CKE <= '0';
-- sdram_init <= '1';
-- sdram_reading <= '0';
-- sdram_writing <= '0';
-- sdram_refreshing <= '0';
-- sdram_check_refresh <= '0';
-- end if;
-- end if;
-- end process;
--------------------------------------------------------
-- QPI flash
--------------------------------------------------------
-- See above for bank enable logic
flash_controller : qpi_flash
port map (
clk => clock_96,
ready => flash_ready,
reset => memory_reset_96 or flash_reset,
read => char_rom_read or (start_read_96 and flash_enable), -- Read cycle trigger
addr => flash_addr,
data_out => flash_data_out,
-- Passthrough: when active (passthrough = '1'), IO1/2/3 are inputs with
-- a weak pullup, and nCE/SCK/IO0 are passed through (registered on clock_96).
passthrough => mcu_flash_spi_clocking or mcu_flash_passthrough,
passthrough_nCE => not mcu_flash_spi_clocking,
passthrough_SCK => mcu_SCK_sync(0),
passthrough_MOSI => mcu_MOSI_sync(0),
-- External pins
flash_nCE => flash_nCE,
flash_SCK => flash_SCK,
flash_IO0 => flash_IO0,
flash_IO1 => flash_IO1,
flash_IO2 => flash_IO2,
flash_IO3 => flash_IO3
);
gen_mgc : if IncludeMGC generate
process (clock_96)
begin
if rising_edge(clock_96) then
if start_write_96 = '1' then
if addr = x"FC00" then
mgc_bank <= data_in(6 downto 0);
end if;
if addr = x"FC08" then
mgc_high_bank <= data_in(1);
mgc_use_both_banks <= data_in(2);
end if;
end if;
if RST_n_sync_16(1) = '0' then
-- TODO sync with clock_96 instead
mgc_bank <= (others => '0');
mgc_use_both_banks <= '0';
mgc_high_bank <= '0';
end if;
end if;
end process;
end generate;
load_mode7_char_rom : if IncludeMode7 generate
-- On startup, load SAA5050 character ROM from QPI flash.
char_rom_loaded <= char_rom_addr(char_rom_addr'high);
process (clock_96)
begin
if rising_edge(clock_96) then
if char_rom_loaded = '0' then
char_rom_read <= '0';
char_rom_we <= '0';
case char_rom_state is
when "00" =>
-- Start a new read when flash ready
if flash_ready = '1' then
-- Start a new read
char_rom_read <= '1';
char_rom_state <= "01";
end if;
when "01" =>
-- Wait for data available then send it to the char rom
if flash_ready = '1' then
char_rom_we <= '1';
char_rom_state <= "10";
end if;
when "10" =>
-- Increment address for next read
char_rom_addr <= char_rom_addr + 1;
char_rom_state <= "00";
when "11" =>
-- Unused
end case;
end if;
end if;
end process;
end generate;
--------------------------------------------------------
-- Power Up Reset Generation
--------------------------------------------------------
reset_gen : process(clock_input)
begin
if rising_edge(clock_input) then
-- pll_reset_counter is a 2 bit counter, which holds the PLL in
-- reset for two clocks.
if (pll_reset_counter(pll_reset_counter'high) = '0') then
pll_reset_counter <= pll_reset_counter + 1;
end if;
pll_reset <= not pll_reset_counter(pll_reset_counter'high);
-- pll1_locked is asynchronous.
pll_locked_sync <= pll_locked_sync(1 downto 0) & pll1_locked;
-- reset_counter is a 16 bit counter, resulting in POR active for
-- 32768 clocks or 2.048 ms. It starts counting when the two PLLs
-- are locked.
if (pll_locked_sync(2) = '1' and reset_counter(reset_counter'high) = '0') then
reset_counter <= reset_counter + 1;
end if;
powerup_reset_n <= reset_counter(reset_counter'high);
end if;
end process;
-- Reset drives the enable on an open collector buffer which pulls the 5V RESET line down
RST_n_out <= '1' when
powerup_reset_n = '1' and
(IncludeMode7 = false or char_rom_loaded = '1') -- stay in reset until char rom loaded
else '0';
reset_gen_96 : process(clock_96)
begin
if rising_edge(clock_96) then
-- Serial flash needs at least 20 us to start up, and 30us after a software reset,
-- so delay at least 30 us (2880 clocks). Easy option: 4096 clocks (42.7 us).
-- Synchronize pll1_locked with clock_96, then release reset 4096 clocks later:
pll_locked_sync_96 <= pll_locked_sync_96(1 downto 0) & pll1_locked;
if pll_locked_sync_96(2) = '1' and reset_counter_96(reset_counter_96'high) = '0' then
reset_counter_96 <= reset_counter_96 + 1;
end if;
memory_reset_96 <= not reset_counter_96(reset_counter_96'high);
end if;
end process;
--------------------------------------------------------
-- Clock generation
--------------------------------------------------------
-- Both of these have been verified on real hardware
clock_input <= clk_osc; -- Use 16MHz oscillator
--clock_input <= clk_in; -- Use 16MHz clock from ULA pin
max10_pll1_inst : entity work.max10_pll1 PORT MAP (
areset => pll_reset,
inclk0 => clock_input, -- PLL input: 16MHz from oscillator or ULA pin
c0 => clock_16, -- main system clock / sRGB video clock
c1 => clock_96_sdram, -- phase-shifted output clock for SDRAM
c2 => clock_96, -- SDRAM/flash, divided to 24 for the SAA5050 in Mode 7 and 32 for
c3 => clock_40, -- video clock when in 60Hz VGA Mode
c4 => clock_33, -- video clock when in 50Hz VGA Mode
locked => pll1_locked
);
-- Generate a 250 ns low pulse on PHI OUT for four 16 MHz cycles after
-- cpu_clken == 1 (i.e. cpu_clken = '1' for the last 62.5ns of a PHI0
-- cycle) in 1MHz/2MHz mode, or a 125 ns low pulse in 4MHz mode.
clk_gen : process(clock_16)
begin
if rising_edge(clock_16) then
-- Synchronize reset and NMI for ULA
RST_n_sync_16 <= RST_n_sync_16(0) & RST_n_in;
NMI_n_sync_16 <= NMI_n_sync_16(0) & NMI_n_in;
-- Generate a signal that's synced to the rising edge, for cpu_clken_96_sync later
cpu_clken_16_sync <= cpu_clken;
end if;
end process;
clk_out <= clk_out_int;
kbd_access <= '1' when addr(15 downto 14) = "10" and (rom_latch = 8 or rom_latch = 9) else '0';
generate_start_read_write_signals : process(clock_96)
begin
if rising_edge(clock_96) then
-- cpu_clken_16_sync is synchronized with clock_16.
-- With InternalCPU, it will be high for the clock *after* a T65
-- cycle, so as soon as it goes low, it's safe for clock_96
-- processes to sample addr/data. Assuming aligned clock_16 and
-- clock_96 edges, cpu_clken_96_sync(1) will go low 20.83 ns
-- later.
-- With an external CPU, it will be low during the first 62.5 ns
-- of the low clk_out period. Assuming aligned clock_16 and
-- clock_96 edges, cpu_clken_96_sync(1) will go low 20.83 ns into
-- the low clk_out period. TODO figure out memory timing.
cpu_clken_96_sync <= cpu_clken_96_sync(1 downto 0) & cpu_clken_16_sync;
-- start_write_96: high for 1/96 us when it's safe to sample addr/data for a memory (sdram/flash) write.
-- start_read_96: high for 1/96 us when it's safe to sample addr for a memory (sdram/flash) read.
start_write_96 <= '0';
start_read_96 <= '0';
if sdram_refresh_counter /= 31 then
sdram_refresh_counter <= sdram_refresh_counter + 1;
end if;
If InternalCPU then
if cpu_clken_96_sync(2) = '1' and cpu_clken_96_sync(1) = '0' then
-- falling edge of cpu_clken_16_sync; T65 clock should be all done by now
if RnW = '0' then
start_write_96 <= '1';
else
start_read_96 <= '1';
end if;
sdram_refresh_counter <= (others => '0');
end if;
elsif cpu_clken_96_sync(2) = '0' and cpu_clken_96_sync(1) = '1' then
-- DMB: rising edge of cpu_clken_sync_16 is co-incident with PHI0 low
if RnW = '0' then
start_write_96 <= '1';
end if;
wait_for_ads_counter <= "00000";
elsif wait_for_ads_counter /= 15 then
-- A/RnW/D are valid for write at the start of the PHI0 low cycle (from the previous cpu cycle)
-- A/RnW are valid for read at the end of the PHI0 low cycle (for the current cycle).
-- For 2MHz parts -- R6502A: tRWS = tADS = 140 ns; UM6502B/BE: tRWS = tADS = 100ns
-- For 4MHz parts -- UM6502CE: tRWS = 60ns, tADS = 70 ns
-- For 14MHz parts -- W65C02S6TPG-14: tADS = 30 ns
-- These are referenced to PHI2, which can be delayed up to 30ns from PHI0.
-- So we really want a delay of about 170 ns (~17 * clock_96) from clk_out low to start_read_96 high.
-- DMB: three 96MHz cycles are lost in the cpu_clken_96_sync
-- chain, so reduce from 17 downto 14
if wait_for_ads_counter = 14 and RnW = '1' then
start_read_96 <= '1';
end if;
wait_for_ads_counter <= wait_for_ads_counter + 1;
end if;
end if;
end process;
-- divide clock_96 to get clock_24, clock_32, and clock_serial
divide_96mhz : process(clock_96)
begin
if rising_edge(clock_96) then
-- -- Divide 96/4 to get 24MHz
-- if clock_div_96_24 = "11" then
-- clock_24 <= not clock_24;
-- clock_div_96_24 <= "00";
-- else
-- clock_div_96_24 <= clock_div_96_24 + 1;
-- end if;
-- Divide 96/3 to get 32MHz
if clock_div_96_32 = "10" then
clock_32 <= not clock_32;
clock_div_96_32 <= "00";
else
clock_div_96_32 <= clock_div_96_32 + 1;
end if;
-- Generate a pulse on the 12MHz teletext clock enable
-- every 8 clock_96 cycles.
clken_ttxt <= '0';
if clken_ttxt_counter(clken_ttxt_counter'high) = '1' then
clken_ttxt <= '1';
clken_ttxt_counter <= "0001";
else
clken_ttxt_counter <= clken_ttxt_counter + 1;
end if;
-- Divide 96/833 to get serial clock
if serial_tx_count = 833 then
serial_tx_count <= (others => '0');
else
serial_tx_count <= serial_tx_count + 1;
end if;
-- TODO also reset serial_rx_count when we get a start bit
if serial_rx_count = 833 then
serial_rx_count <= (others => '0');
else
serial_rx_count <= serial_rx_count + 1;
end if;
end if;
end process;
end behavioral;
| gpl-3.0 | 627cc0c28d076d14b6add0feafc0f12b | 0.499724 | 3.784446 | false | false | false | false |
hpeng2/ECE492_Group4_Project | Ryans_stuff/tracking_camera/tracking_camera_system/testbench/tracking_camera_system_tb/simulation/submodules/altera_avalon_clock_source.vhd | 1 | 1,778 | -- (C) 2001-2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-- $File: //acds/main/ip/sopc/app/sopc_scripts/tbgen.tcl $
-- $Author: wkleong $
-- $Revision: #24 $
-- $Date: 2010/10/31 $
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity altera_avalon_clock_source is
-- default clock rate 10 MHz (100ns)
generic (CLOCK_RATE : integer :=10; -- clock rate
CLOCK_UNIT : integer :=1000000); -- clock rate unit MHz / kHz / Hz
port (clk : out std_logic);
end altera_avalon_clock_source;
architecture behavioral of altera_avalon_clock_source is
signal clk_temp : std_logic := '0';
constant CLOCK_PERIOD : time := 1 sec / CLOCK_RATE / CLOCK_UNIT;
constant HALF_PERIOD : time := CLOCK_PERIOD / 2;
begin
clk <= clk_temp;
internal_clock: process (clk_temp)
begin
clk_temp <= not clk_temp after HALF_PERIOD;
end process internal_clock;
end behavioral; | gpl-2.0 | 15dd7a86641839031733c9ee39e41750 | 0.660855 | 4.173709 | false | false | false | false |
DreamIP/GPStudio | support/component/matrix_extractor/hdl/matrix_extractor.vhd | 1 | 7,077 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.math_real.all;
library std;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity matrix_extractor is
generic (
LINE_WIDTH_MAX : integer;
PIX_WIDTH : integer;
OUTVALUE_WIDTH : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- in flow -----------------------
in_data : in std_logic_vector((PIX_WIDTH-1) downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector((PIX_WIDTH-1) downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
------------------------ matrix out ---------------------
p00 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p01 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p02 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p10 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p11 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p12 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p20 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p21 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p22 : out std_logic_vector((PIX_WIDTH-1) downto 0);
matrix_dv : out std_logic;
---------------------- computed value -------------------
value_data : in std_logic_vector((OUTVALUE_WIDTH-1) downto 0);
value_dv : in std_logic;
------------------------- params ------------------------
enable_i : in std_logic;
widthimg_i : in std_logic_vector(15 downto 0)
);
end matrix_extractor;
architecture rtl of matrix_extractor is
constant FIFO_LENGHT : integer := LINE_WIDTH_MAX;
constant FIFO_LENGHT_WIDTH : integer := integer(ceil(log2(real(FIFO_LENGHT))));
component gp_fifo
generic (
DATA_WIDTH : positive;
FIFO_DEPTH : positive
);
port (
clk : in std_logic;
reset_n : in std_logic;
data_wr : in std_logic;
data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
full : out std_logic;
data_rd : in std_logic;
data_out : out std_logic_vector(DATA_WIDTH-1 downto 0);
empty : out std_logic
);
end component;
signal enable_reg : std_logic;
signal x_pos : unsigned(15 downto 0);
signal y_pos : unsigned(15 downto 0);
signal p00_s, p01_s, p02_s : std_logic_vector((PIX_WIDTH-1) downto 0);
signal p10_s, p11_s, p12_s : std_logic_vector((PIX_WIDTH-1) downto 0);
signal p20_s, p21_s, p22_s : std_logic_vector((PIX_WIDTH-1) downto 0);
signal line_reset : std_logic;
signal line0_read : std_logic;
signal line0_out : std_logic_vector((PIX_WIDTH-1) downto 0);
signal line0_write : std_logic;
signal line0_empty : std_logic;
signal line0_pix_out : std_logic_vector((PIX_WIDTH-1) downto 0);
signal line1_read : std_logic;
signal line1_out : std_logic_vector((PIX_WIDTH-1) downto 0);
signal line1_write : std_logic;
signal line1_empty : std_logic;
signal line1_pix_out : std_logic_vector((PIX_WIDTH-1) downto 0);
signal dummy_dv : std_logic;
signal out_dv_s : std_logic;
signal cell : std_logic_vector((LINE_WIDTH_MAX-1) downto 0);
begin
line0_fifo : gp_fifo
generic map (
DATA_WIDTH => PIX_WIDTH,
FIFO_DEPTH => FIFO_LENGHT
)
port map (
data_in => p10_s,
clk => clk_proc,
data_wr => line0_write,
data_out => p02_s,
data_rd => line0_read,
reset_n => line_reset,
empty => line0_empty
);
line1_fifo : gp_fifo
generic map (
DATA_WIDTH => PIX_WIDTH,
FIFO_DEPTH => FIFO_LENGHT
)
port map (
data_in => p20_s,
clk => clk_proc,
data_wr => line1_write,
data_out => p12_s,
data_rd => line1_read,
reset_n => line_reset,
empty => line1_empty
);
process (clk_proc, reset_n)
begin
if(reset_n='0') then
x_pos <= to_unsigned(0, 16);
y_pos <= to_unsigned(0, 16);
line0_read <= '0';
line0_write <= '0';
line1_read <= '0';
line1_write <= '0';
line_reset <= '0';
elsif(rising_edge(clk_proc)) then
matrix_dv <= '0';
if(in_fv='0') then
x_pos <= to_unsigned(0, 16);
y_pos <= to_unsigned(0, 16);
line0_read <= '0';
line0_write <= '0';
line1_read <= '0';
line1_write <= '0';
line_reset <= '0';
matrix_dv <= '0';
else
line_reset <= '1';
if (line0_read='1') then
p01_s <= p02_s;
p00_s <= p01_s;
end if;
if (line1_read='1') then
p11_s <= p12_s;
p10_s <= p11_s;
end if;
if (in_dv='1') then
-- counter y_pos and x_pos
x_pos <= x_pos+1;
if(x_pos = unsigned(widthimg_i)-1) then
y_pos <= y_pos + 1;
x_pos <= to_unsigned(0, 16);
end if;
p22_s <= in_data;
p21_s <= p22_s;
p20_s <= p21_s;
-- line1 write command
if((y_pos = to_unsigned(0, 16)) and (x_pos >= to_unsigned(2, 16))) then
line1_write <= '1';
elsif(y_pos > to_unsigned(0, 16)) then
line1_write <= '1';
else
line1_write <= '0';
end if;
-- line0 write command
if(y_pos = to_unsigned(0, 16)) then
line0_write <= '0';
elsif((y_pos = to_unsigned(1, 16)) and (x_pos >= to_unsigned(2, 16))) then
line0_write <= '1';
elsif((y_pos > to_unsigned(1, 16))) then
line0_write <= '1';
else
line0_write <= '0';
end if;
-- matrix_dv_next command
if((x_pos >= to_unsigned(2, 16)) and (y_pos >= to_unsigned(2, 16))) then
matrix_dv <= '1';
end if;
-- line1 read command
if(y_pos = to_unsigned(0, 16)) then
if(x_pos = unsigned(widthimg_i)-2) then
line1_read <= '1';
else
line1_read <= '0';
end if;
else
line1_read <= '1';
end if;
-- line0 read command
if(y_pos = to_unsigned(0, 16)) then
line0_read <= '0';
elsif(y_pos = to_unsigned(1, 16)) then
if(x_pos = unsigned(widthimg_i)-2) then
line0_read <= '1';
else
line0_read <= '0';
end if;
else
line0_read <= '1';
end if;
else
line0_read <= '0';
line0_write <= '0';
line1_read <= '0';
line1_write <= '0';
end if;
end if;
end if;
end process;
p00 <= p00_s; p01 <= p01_s; p02 <= p02_s;
p10 <= p10_s; p11 <= p11_s; p12 <= p12_s;
p20 <= p20_s; p21 <= p21_s; p22 <= p22_s;
out_data <= value_data;
out_dv <= value_dv;
out_fv <= in_fv;
end rtl;
| gpl-3.0 | 9cc22a1b86d26d7931efcb109b5a5c5c | 0.500636 | 3.047804 | false | false | false | false |
DreamIP/GPStudio | support/process/sconv/hdl/kernel_3x3.vhd | 1 | 4,534 | -- Author : K. Abdelouahab
-- Company : DREAM - Institut Pascal - Unviersite Clermont Auvergne
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity kernel_3x3 is
generic(
PIX_WIDTH : integer
);
port (
reset_n : in std_logic;
clk_proc : in std_logic;
in_dv : in std_logic;
in_fv : in std_logic;
enable_i : in std_logic;
p11,p12,p13 : in std_logic_vector(PIX_WIDTH-1 downto 0);
p21,p22,p23 : in std_logic_vector(PIX_WIDTH-1 downto 0);
p31,p32,p33 : in std_logic_vector(PIX_WIDTH-1 downto 0);
ker11,ker12,ker13 : in std_logic_vector(PIX_WIDTH-1 downto 0);
ker21,ker22,ker23 : in std_logic_vector(PIX_WIDTH-1 downto 0);
ker31,ker32,ker33 : in std_logic_vector(PIX_WIDTH-1 downto 0);
norm : in std_logic_vector(PIX_WIDTH-1 downto 0);
out_data : out std_logic_vector(PIX_WIDTH-1 downto 0);
out_dv : out std_logic;
out_fv : out std_logic
);
end kernel_3x3;
architecture BHV of kernel_3x3 is
signal p11u,p12u,p13u : signed (PIX_WIDTH downto 0);
signal p21u,p22u,p23u : signed (PIX_WIDTH downto 0);
signal p31u,p32u,p33u : signed (PIX_WIDTH downto 0);
signal ker11u,ker12u,ker13u : signed (PIX_WIDTH downto 0);
signal ker21u,ker22u,ker23u : signed (PIX_WIDTH downto 0);
signal ker31u,ker32u,ker33u : signed (PIX_WIDTH downto 0);
signal normi : integer range 0 to 8;
begin
p11u <= signed( '0' & (p11));
p12u <= signed( '0' & (p12));
p13u <= signed( '0' & (p13));
p21u <= signed( '0' & (p21));
p22u <= signed( '0' & (p22));
p23u <= signed( '0' & (p23));
p31u <= signed( '0' & (p31));
p32u <= signed( '0' & (p32));
p33u <= signed( '0' & (p33));
ker11u <= signed(ker11(ker11'LEFT) & (ker11));
ker12u <= signed(ker12(ker12'LEFT) & (ker12));
ker13u <= signed(ker13(ker13'LEFT) & (ker13));
ker21u <= signed(ker21(ker21'LEFT) & (ker21));
ker22u <= signed(ker22(ker22'LEFT) & (ker22));
ker23u <= signed(ker23(ker23'LEFT) & (ker23));
ker31u <= signed(ker31(ker31'LEFT) & (ker31));
ker32u <= signed(ker32(ker32'LEFT) & (ker32));
ker33u <= signed(ker33(ker33'LEFT) & (ker33));
process (clk_proc)
variable m11 : signed (PIX_WIDTH + PIX_WIDTH + 1 downto 0);
variable m12 : signed (PIX_WIDTH + PIX_WIDTH + 1 downto 0);
variable m13 : signed (PIX_WIDTH + PIX_WIDTH + 1 downto 0);
variable m21 : signed (PIX_WIDTH + PIX_WIDTH + 1 downto 0);
variable m22 : signed (PIX_WIDTH + PIX_WIDTH + 1 downto 0);
variable m23 : signed (PIX_WIDTH + PIX_WIDTH + 1 downto 0);
variable m31 : signed (PIX_WIDTH + PIX_WIDTH + 1 downto 0);
variable m32 : signed (PIX_WIDTH + PIX_WIDTH + 1 downto 0);
variable m33 : signed (PIX_WIDTH + PIX_WIDTH + 1 downto 0);
variable sum : signed (PIX_WIDTH + PIX_WIDTH + 1 downto 0);
variable res : signed (PIX_WIDTH + PIX_WIDTH + 1 downto 0);
begin
if (reset_n = '0') then
sum := (others => '0');
elsif (RISING_EDGE(clk_proc)) then
if ((in_fv and in_dv and enable_i) = '1') then
m11 := ker11u * p11u ;
m12 := ker12u * p12u ;
m13 := ker13u * p13u ;
m21 := ker21u * p21u ;
m22 := ker22u * p22u ;
m23 := ker23u * p23u ;
m31 := ker31u * p31u ;
m32 := ker32u * p32u ;
m33 := ker33u * p33u ;
sum := m11 + m12 + m13 + m21 + m22 + m23 + m31 + m32 + m33;
if (sum(sum'left) = '1') then
sum := (others => '0');
end if;
normi <= to_integer (unsigned(norm));
res := sum srl normi;
out_data <= std_logic_vector (res(PIX_WIDTH -1 downto 0));
end if;
out_dv <= in_dv;
out_fv <= in_fv;
end if;
end process;
end BHV;
| gpl-3.0 | c915ae7c72fcf5c78c52d841eddffb15 | 0.48809 | 2.973115 | false | false | false | false |
DreamIP/GPStudio | support/io/com/hdl/hal/eth_marvell_88e1111/hdl/encapsulation/eth_tx_stream.vhd | 1 | 2,630 | ----------------------------------------------------------------------------------
-- Company: Laboratoire Leprince-Ringuet
-- Engineer:
--
-- Create Date: 11:58:40 10/14/2011
-- Design Name:
-- Module Name: eth_tx_stream - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity eth_tx_stream is Port(
CLK125 : in STD_LOGIC;
RESET : in STD_LOGIC;
TXD : out STD_LOGIC_VECTOR(7 downto 0);
TXCTRL : out STD_LOGIC;--phy data valid
--TXC : out STD_LOGIC;--gigabit phy tx clock
ETH_TX_STREAM : in STD_LOGIC_VECTOR(9 downto 0));
end eth_tx_stream;
architecture Behavioral of eth_tx_stream is
type multiple is ARRAY(7 downto 0) of STD_LOGIC_VECTOR(7 downto 0);
signal data_dly : multiple;
signal frm_dly : STD_LOGIC_VECTOR(7 downto 0) := x"00";
signal txdat_reg : STD_LOGIC_VECTOR(7 downto 0) := x"00";
signal txen_reg : STD_LOGIC;
signal txdat : STD_LOGIC_VECTOR(7 downto 0) := x"00";
signal txcontrol : STD_LOGIC := '0';
signal outcnt : unsigned(2 downto 0) := "000";
signal invert_clk : std_logic;
begin
TXD <= txdat;
TXCTRL <= txcontrol;
process(CLK125,RESET)
begin
if RESET = '0' then
for i in 0 to 7 loop
data_dly(i) <= x"00";
end loop;
frm_dly <= x"00";
txdat_reg <= x"00";
txen_reg <= '0';
txdat <= x"00";
txcontrol <= '0';
elsif CLK125'event and CLK125 = '1' then
if ETH_TX_STREAM(9) = '1' then
--delay the data by eight bytes to insert the preamble
data_dly(0) <= ETH_TX_STREAM(7 downto 0);
data_dly(7 downto 1) <= data_dly(6 downto 0);
frm_dly <= frm_dly(6 downto 0) & ETH_TX_STREAM(8);
--register the data byte to send
if frm_dly(7) = '1' then
txdat_reg <= data_dly(7);
elsif frm_dly(6) = '1' then
txdat_reg <= x"D5";
else
txdat_reg <= x"55";
end if;
txen_reg <= ETH_TX_STREAM(8) or frm_dly(7);
--handle the 100Mbps/1000Mbps modes
outcnt <= "000";
txdat <= txdat_reg;
txcontrol <= txen_reg;
else
if outcnt < "111" then
outcnt <= outcnt + "001";
else
outcnt <= outcnt;
end if;
if outcnt = "100" then
txdat <= x"0" & txdat(7 downto 4);
--else
--txdat <= txdat;
end if;
txcontrol <= txcontrol;
end if;
end if;
end process;
end Behavioral; | gpl-3.0 | 34e8f38ed1bc9fdef769bea907f83bc8 | 0.553992 | 2.978482 | false | false | false | false |
DreamIP/GPStudio | support/process/gaussian/hdl/gaussian_process.vhd | 1 | 5,319 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity gaussian_process is
generic (
LINE_WIDTH_MAX : integer;
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer;
WEIGHT_SIZE : integer := 8
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : in std_logic;
widthimg_reg_width : in std_logic_vector(15 downto 0);
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic
);
end gaussian_process;
architecture rtl of gaussian_process is
component matrix_extractor
generic (
LINE_WIDTH_MAX : integer;
PIX_WIDTH : integer;
OUTVALUE_WIDTH : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- in flow -----------------------
in_data : in std_logic_vector((PIX_WIDTH-1) downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector((PIX_WIDTH-1) downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
------------------------ matrix out ---------------------
p00, p01, p02 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p10, p11, p12 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p20, p21, p22 : out std_logic_vector((PIX_WIDTH-1) downto 0);
matrix_dv : out std_logic;
---------------------- computed value -------------------
value_data : in std_logic_vector((PIX_WIDTH-1) downto 0);
value_dv : in std_logic;
------------------------- params ------------------------
enable_i : in std_logic;
widthimg_i : in std_logic_vector(15 downto 0)
);
end component;
-- neighbors extraction
signal p00, p01, p02 : std_logic_vector((IN_SIZE-1) downto 0);
signal p10, p11, p12 : std_logic_vector((IN_SIZE-1) downto 0);
signal p20, p21, p22 : std_logic_vector((IN_SIZE-1) downto 0);
signal matrix_dv : std_logic;
-- products calculation
signal prod00, prod01, prod02 : signed((WEIGHT_SIZE + IN_SIZE) downto 0);
signal prod10, prod11, prod12 : signed((WEIGHT_SIZE + IN_SIZE) downto 0);
signal prod20, prod21, prod22 : signed((WEIGHT_SIZE + IN_SIZE) downto 0);
signal prod_dv : std_logic;
signal value_data : std_logic_vector((IN_SIZE-1) downto 0);
signal value_dv : std_logic;
signal out_fv_s : std_logic;
signal enable_s : std_logic;
begin
matrix_extractor_inst : matrix_extractor
generic map (
LINE_WIDTH_MAX => LINE_WIDTH_MAX,
PIX_WIDTH => IN_SIZE,
OUTVALUE_WIDTH => IN_SIZE
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
in_data => in_data,
in_fv => in_fv,
in_dv => in_dv,
p00 => p00, p01 => p01, p02 => p02,
p10 => p10, p11 => p11, p12 => p12,
p20 => p20, p21 => p21, p22 => p22,
matrix_dv => matrix_dv,
value_data => value_data,
value_dv => value_dv,
out_data => out_data,
out_fv => out_fv_s,
out_dv => out_dv,
enable_i => status_reg_enable_bit,
widthimg_i => widthimg_reg_width
);
process (clk_proc, reset_n, matrix_dv)
variable sum : signed((WEIGHT_SIZE + IN_SIZE) downto 0);
begin
if(reset_n='0') then
enable_s <= '0';
prod_dv <= '0';
value_dv <= '0';
elsif(rising_edge(clk_proc)) then
if(in_fv = '0') then
enable_s <= status_reg_enable_bit;
prod_dv <= '0';
value_dv <= '0';
end if;
-- product calculation pipeline stage
prod_dv <= '0';
if(matrix_dv = '1' and enable_s = '1') then
prod00 <= "00000001" * signed('0' & p00); -- w00 = 1
prod01 <= "00000010" * signed('0' & p01); -- w01 = 2
prod02 <= "00000001" * signed('0' & p02); -- w02 = 1
prod10 <= "00000010" * signed('0' & p10); -- w10 = 2
prod11 <= "00000100" * signed('0' & p11); -- w11 = 4
prod12 <= "00000010" * signed('0' & p12); -- w12 = 2
prod20 <= "00000001" * signed('0' & p20); -- w20 = 1
prod21 <= "00000010" * signed('0' & p21); -- w21 = 2
prod22 <= "00000001" * signed('0' & p22); -- w22 = 1
prod_dv <= '1';
end if;
value_dv <= '0';
if(prod_dv='1' and enable_s = '1') then
sum := prod00 + prod01 + prod02 +
prod10 + prod11 + prod12 +
prod20 + prod21 + prod22;
if (sum(sum'left) = '1') then
sum := (others => '0');
end if;
value_data <= std_logic_vector(shift_right(unsigned(sum),4))(OUT_SIZE -1 downto 0);
value_dv <= '1';
end if;
end if;
end process;
out_fv <= enable_s and out_fv_s;
end rtl;
| gpl-3.0 | f6426d781892fc736a5b10c0d4ac8943 | 0.49859 | 3.164188 | false | false | false | false |
DreamIP/GPStudio | support/process/fastfilter/hdl/components/neighExtractor2.vhd | 1 | 6,979 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.fastfilter_types.all;
entity neighExtractor2 is
generic(
PIXEL_SIZE : integer;
IMAGE_WIDTH : integer;
KERNEL_SIZE : integer
);
port(
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
in_data : in std_logic_vector((PIXEL_SIZE-1) downto 0);
in_dv : in std_logic;
in_fv : in std_logic;
out_data : out pixel_array (0 to (KERNEL_SIZE * KERNEL_SIZE)- 1);
out_dv : out std_logic;
out_fv : out std_logic
);
end neighExtractor2;
architecture rtl of neighExtractor2 is
-- signals
signal pixel_out : pixel_array(0 to KERNEL_SIZE-1);
-- components
component taps
generic (
PIXEL_SIZE : integer;
TAPS_WIDTH : integer;
KERNEL_SIZE : integer
);
port (
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
in_data : in std_logic_vector (PIXEL_SIZE-1 downto 0);
taps_data : out pixel_array (0 to KERNEL_SIZE -1 );
out_data : out std_logic_vector (PIXEL_SIZE-1 downto 0)
);
end component;
component bit_taps2
generic (
TAPS_WIDTH : integer
);
port (
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
in_data : in std_logic;
out_data : out std_logic
);
end component;
signal all_valid : std_logic;
signal s_valid : std_logic;
signal tmp_dv : std_logic;
signal tmp_fv : std_logic;
begin
-- All valid : Logic and
all_valid <= in_dv and in_fv;
s_valid <= all_valid and enable;
----------------------------------------------------
-- SUPER FOR GENERATE : GO
----------------------------------------------------
taps_inst : for i in 0 to KERNEL_SIZE-1 generate
-- First line
gen_1 : if i=0 generate
gen1_inst : taps
generic map(
PIXEL_SIZE => PIXEL_SIZE,
TAPS_WIDTH => IMAGE_WIDTH ,
KERNEL_SIZE => KERNEL_SIZE
)
port map(
clk => clk,
reset_n => reset_n,
enable => s_valid,
in_data => in_data,
taps_data => out_data(0 to KERNEL_SIZE-1),
out_data => pixel_out(0)
);
end generate gen_1;
-- line i
gen_i : if i>0 and i<KERNEL_SIZE-1 generate
geni_inst : taps
generic map(
PIXEL_SIZE => PIXEL_SIZE,
TAPS_WIDTH => IMAGE_WIDTH,
KERNEL_SIZE => KERNEL_SIZE
)
port map(
clk => clk,
reset_n => reset_n,
enable => s_valid,
in_data => pixel_out(i-1),
taps_data => out_data(i * KERNEL_SIZE to KERNEL_SIZE*(i+1)-1),
out_data => pixel_out(i)
);
end generate gen_i;
-- Last line
gen_last : if i= (KERNEL_SIZE-1) generate
gen_last_inst : taps
generic map(
PIXEL_SIZE => PIXEL_SIZE,
TAPS_WIDTH => KERNEL_SIZE,
KERNEL_SIZE => KERNEL_SIZE
)
port map(
clk => clk,
reset_n => reset_n,
enable => s_valid,
in_data => pixel_out(i-1),
taps_data => out_data((KERNEL_SIZE-1) * KERNEL_SIZE to KERNEL_SIZE*KERNEL_SIZE - 1),
out_data => OPEN
);
end generate gen_last;
end generate taps_inst;
--------------------------------------------------------------------------
-- Manage out_dv and out_fv
--------------------------------------------------------------------------
dv_proc : process(clk)
-- 12 bits is enought to count until 4096
constant NBITS_DELAY : integer := 20;
variable delay_cmp : unsigned (NBITS_DELAY-1 downto 0) :=(others => '0');
variable edge_cmp : unsigned (NBITS_DELAY-1 downto 0) :=(others => '0');
begin
if (reset_n = '0') then
delay_cmp := (others => '0');
edge_cmp := (others => '0');
tmp_dv <='0';
tmp_fv <='0';
elsif (rising_edge(clk)) then
if(enable = '1') then
if (in_fv = '1') then
if(in_dv = '1') then
-- Initial delay : Wait until there is data in all the taps
if (delay_cmp >= to_unsigned((KERNEL_SIZE-1)*IMAGE_WIDTH + KERNEL_SIZE - 1 , NBITS_DELAY)) then
-- Taps are full : Frame can start
tmp_fv <= '1';
if ( edge_cmp > to_unsigned (IMAGE_WIDTH - KERNEL_SIZE, NBITS_DELAY)) then
-- If at edge : data is NOT valid
if ( edge_cmp = to_unsigned (IMAGE_WIDTH - 1, NBITS_DELAY)) then
edge_cmp := (others => '0');
tmp_dv <= '0';
else
edge_cmp := edge_cmp + to_unsigned(1,NBITS_DELAY);
tmp_dv <= '0';
end if;
-- Else : Data is valid
else
edge_cmp := edge_cmp + to_unsigned(1,NBITS_DELAY);
tmp_dv <= '1';
end if;
-- When taps are nor full : Frame is not valid , neither is data
else
delay_cmp := delay_cmp + to_unsigned(1,NBITS_DELAY);
tmp_dv <= '0';
tmp_fv <= '0';
end if;
else
tmp_dv <= '0';
end if;
-- When Fv = 0 (New frame comming): reset counters
else
delay_cmp := (others => '0');
edge_cmp := (others => '0');
tmp_dv <= '0';
tmp_fv <= '0';
end if;
-- When enable = 0
else
delay_cmp := (others => '0');
edge_cmp := (others => '0');
tmp_dv <= '0';
tmp_fv <= '0';
end if;
end if;
end process;
out_dv <= tmp_dv;
out_fv <= tmp_fv;
end architecture;
| gpl-3.0 | 4c9e475fed1b6e6b241210c9a71c0e16 | 0.400057 | 4.071762 | false | false | false | false |
DreamIP/GPStudio | support/io/eth_marvell_88e1111/hdl/IP/IPv4_RX.vhd | 1 | 24,149 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 16:20:42 06/01/2011
-- Design Name:
-- Module Name: IPv4_RX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle simple IP RX
-- doesnt handle reassembly
-- checks and filters for IP protocol
-- checks and filters for IP addr
-- Handle IPv4 protocol
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - Improved error handling
-- Revision 0.03 - Added handling of broadcast address
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
entity IPv4_RX is
port (
-- IP Layer signals
ip_rx : out ipv4_rx_type;
ip_rx_start : out std_logic; -- indicates receipt of ip frame.
-- system signals
clk : in std_logic; -- same clock used to clock mac data and ip data
reset : in std_logic;
our_ip_address : in std_logic_vector (31 downto 0);
rx_pkt_count : out std_logic_vector(7 downto 0); -- number of IP pkts received for us
-- MAC layer RX signals
mac_data_in : in std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
mac_data_in_valid : in std_logic; -- indicates data_in valid on clock
mac_data_in_first : in std_logic;
mac_data_in_last : in std_logic -- indicates last data in frame
);
end IPv4_RX;
architecture Behavioral of IPv4_RX is
type rx_state_type is (IDLE, ETH_HDR, IP_HDR, USER_DATA, WAIT_END, ERR);
type rx_event_type is (NO_EVENT, START, DATA, DONE_ERR);
type count_mode_type is (RST, INCR, HOLD);
type settable_count_mode_type is (RST, INCR, SET_VAL, HOLD);
type set_clr_type is (SET, CLR, HOLD);
-- state variables
signal rx_state : rx_state_type;
signal rx_count : unsigned (15 downto 0);
signal src_ip : std_logic_vector (31 downto 0); -- src IP captured from input
signal dst_ip : std_logic_vector (23 downto 0); -- 1st 3 bytes of dst IP captured from input
signal is_broadcast_reg : std_logic;
signal protocol : std_logic_vector (7 downto 0); -- src protocol captured from input
signal data_len : std_logic_vector (15 downto 0); -- src data length captured from input
signal ip_rx_start_reg : std_logic; -- indicates start of user data
signal hdr_valid_reg : std_logic; -- indicates that hdr data is valid
signal frame_err_cnt : unsigned (7 downto 0); -- number of frame errors
signal error_code_reg : std_logic_vector (3 downto 0);
signal rx_pkt_counter : unsigned (7 downto 0); -- number of rx frames received for us
-- rx control signals
signal next_rx_state : rx_state_type;
signal set_rx_state : std_logic;
signal rx_event : rx_event_type;
signal rx_count_mode : settable_count_mode_type;
signal set_dst_ip3 : std_logic;
signal set_dst_ip2 : std_logic;
signal set_dst_ip1 : std_logic;
signal set_ip3 : std_logic;
signal set_ip2 : std_logic;
signal set_ip1 : std_logic;
signal set_ip0 : std_logic;
signal set_protocol : std_logic;
signal set_len_H : std_logic;
signal set_len_L : std_logic;
signal set_ip_rx_start : set_clr_type;
signal set_hdr_valid : set_clr_type;
signal set_frame_err_cnt : count_mode_type;
signal dataval : std_logic_vector (7 downto 0);
signal rx_count_val : unsigned (15 downto 0);
signal set_error_code : std_logic;
signal error_code_val : std_logic_vector (3 downto 0);
signal set_pkt_cnt : count_mode_type;
signal set_data_last : std_logic;
signal dst_ip_rx : std_logic_vector (31 downto 0);
signal set_is_broadcast : set_clr_type;
-- IP datagram header format
--
-- 0 4 8 16 19 24 31
-- --------------------------------------------------------------------------------------------
-- | Version | *Header | Service Type | Total Length including header |
-- | (4) | Length | (ignored) | (in bytes) |
-- --------------------------------------------------------------------------------------------
-- | Identification | Flags | Fragment Offset |
-- | | | (in 32 bit words) |
-- --------------------------------------------------------------------------------------------
-- | Time To Live | Protocol | Header Checksum |
-- | (ignored) | | |
-- --------------------------------------------------------------------------------------------
-- | Source IP Address |
-- | |
-- --------------------------------------------------------------------------------------------
-- | Destination IP Address |
-- | |
-- --------------------------------------------------------------------------------------------
-- | Options (if any - ignored) | Padding |
-- | | (if needed) |
-- --------------------------------------------------------------------------------------------
-- | Data |
-- | |
-- --------------------------------------------------------------------------------------------
-- | .... |
-- | |
-- --------------------------------------------------------------------------------------------
--
-- * - in 32 bit words
begin
-----------------------------------------------------------------------
-- combinatorial process to implement FSM and determine control signals
-----------------------------------------------------------------------
rx_combinatorial : process (
-- input signals
mac_data_in, mac_data_in_valid, mac_data_in_first, mac_data_in_last, our_ip_address,
-- state variables
rx_state, rx_count, src_ip, dst_ip, protocol, data_len, ip_rx_start_reg, hdr_valid_reg,
frame_err_cnt, error_code_reg, rx_pkt_counter, is_broadcast_reg,
-- control signals
next_rx_state, set_rx_state, rx_event, rx_count_mode,
set_ip3, set_ip2, set_ip1, set_ip0, set_protocol, set_len_H, set_len_L,
set_dst_ip3, set_dst_ip2, set_dst_ip1,
set_ip_rx_start, set_hdr_valid, set_frame_err_cnt, dataval, rx_count_val,
set_error_code, error_code_val, set_pkt_cnt, set_data_last, dst_ip_rx, set_is_broadcast
)
begin
-- set output followers
ip_rx_start <= ip_rx_start_reg;
ip_rx.hdr.is_valid <= hdr_valid_reg;
ip_rx.hdr.protocol <= protocol;
ip_rx.hdr.data_length <= data_len;
ip_rx.hdr.src_ip_addr <= src_ip;
ip_rx.hdr.num_frame_errors <= std_logic_vector(frame_err_cnt);
ip_rx.hdr.last_error_code <= error_code_reg;
ip_rx.hdr.is_broadcast <= is_broadcast_reg;
rx_pkt_count <= std_logic_vector(rx_pkt_counter);
-- transfer data upstream if in user data phase
if rx_state = USER_DATA then
ip_rx.data.data_in <= mac_data_in;
ip_rx.data.data_in_valid <= mac_data_in_valid;
ip_rx.data.data_in_last <= set_data_last;
else
ip_rx.data.data_in <= (others => '0');
ip_rx.data.data_in_valid <= '0';
ip_rx.data.data_in_last <= '0';
end if;
-- set signal defaults
next_rx_state <= IDLE;
set_rx_state <= '0';
rx_event <= NO_EVENT;
rx_count_mode <= HOLD;
set_ip3 <= '0';
set_ip2 <= '0';
set_ip1 <= '0';
set_ip0 <= '0';
set_dst_ip3 <= '0';
set_dst_ip2 <= '0';
set_dst_ip1 <= '0';
set_protocol <= '0';
set_len_H <= '0';
set_len_L <= '0';
set_ip_rx_start <= HOLD;
set_hdr_valid <= HOLD;
set_frame_err_cnt <= HOLD;
rx_count_val <= x"0000";
set_error_code <= '0';
error_code_val <= RX_EC_NONE;
set_pkt_cnt <= HOLD;
dataval <= (others => '0');
set_data_last <= '0';
dst_ip_rx <= (others => '0');
set_is_broadcast <= HOLD;
-- determine event (if any)
if mac_data_in_valid = '1' then
if mac_data_in_first = '1' then
rx_event <= START;
dataval <= mac_data_in;
else
rx_event <= DATA;
dataval <= mac_data_in;
end if;
else
if mac_data_in_last = '1' then
rx_event <= DONE_ERR;
dataval <= mac_data_in;
end if;
end if;
-- RX FSM
case rx_state is
when IDLE =>
rx_count_mode <= RST;
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA => -- (nothing to do)
when START =>
rx_count_mode <= INCR;
set_hdr_valid <= CLR;
next_rx_state <= ETH_HDR;
set_rx_state <= '1';
when DONE_ERR =>
end case;
when ETH_HDR =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when START => -- (nothing to do)
when DATA =>
if rx_count = x"000d" then
rx_count_mode <= RST;
next_rx_state <= IP_HDR;
set_rx_state <= '1';
else
rx_count_mode <= INCR;
end if;
-- handle early frame termination
if mac_data_in_last = '1' then
error_code_val <= RX_EC_ET_ETH;
set_error_code <= '1';
set_frame_err_cnt <= INCR;
set_ip_rx_start <= CLR;
set_data_last <= '1';
next_rx_state <= IDLE;
rx_count_mode <= RST;
set_rx_state <= '1';
else
case rx_count is
when x"000c" =>
if mac_data_in /= x"08" then -- ignore pkts that are not type=IP
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
when x"000d" =>
if mac_data_in /= x"00" then -- ignore pkts that are not type=IP
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
when others => -- ignore other bytes in eth header
end case;
end if;
when DONE_ERR =>
error_code_val <= RX_EC_ET_ETH;
set_error_code <= '1';
set_frame_err_cnt <= INCR;
set_ip_rx_start <= CLR;
set_data_last <= '1';
next_rx_state <= IDLE;
rx_count_mode <= RST;
set_rx_state <= '1';
end case;
when IP_HDR =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when START => -- (nothing to do)
when DATA =>
if rx_count = x"0013" then
rx_count_val <= x"0001"; -- start counter at 1
rx_count_mode <= SET_VAL;
else
rx_count_mode <= INCR;
end if;
-- handle early frame termination
if mac_data_in_last = '1' then
error_code_val <= RX_EC_ET_IP;
set_error_code <= '1';
set_frame_err_cnt <= INCR;
set_ip_rx_start <= CLR;
set_data_last <= '1';
next_rx_state <= IDLE;
rx_count_mode <= RST;
set_rx_state <= '1';
else
case rx_count is
when x"0000" =>
if mac_data_in /= x"45" then -- ignore pkts that are not v4 with 5 header words
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
when x"0002" => set_len_H <= '1';
when x"0003" => set_len_L <= '1';
when x"0006" =>
if (mac_data_in(7) = '1') or (mac_data_in (4 downto 0) /= "00000") then
-- ignore pkts that require reassembly (MF=1 or frag offst /= 0)
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
when x"0007" =>
if mac_data_in /= x"00" then -- ignore pkts that require reassembly (frag offst /= 0)
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
when x"0009" => set_protocol <= '1';
when x"000c" => set_ip3 <= '1';
when x"000d" => set_ip2 <= '1';
when x"000e" => set_ip1 <= '1';
when x"000f" => set_ip0 <= '1';
when x"0010" => set_dst_ip3 <= '1';
if ((mac_data_in /= our_ip_address(31 downto 24)) and
(mac_data_in /= IP_BC_ADDR(31 downto 24)))then -- ignore pkts that are not addressed to us
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
when x"0011" => set_dst_ip2 <= '1';
if ((mac_data_in /= our_ip_address(23 downto 16)) and
(mac_data_in /= IP_BC_ADDR(23 downto 16)))then -- ignore pkts that are not addressed to us
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
when x"0012" => set_dst_ip1 <= '1';
if ((mac_data_in /= our_ip_address(15 downto 8)) and
(mac_data_in /= IP_BC_ADDR(15 downto 8)))then -- ignore pkts that are not addressed to us
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
when x"0013" =>
if ((mac_data_in /= our_ip_address(7 downto 0)) and
(mac_data_in /= IP_BC_ADDR(7 downto 0)))then -- ignore pkts that are not addressed to us
next_rx_state <= WAIT_END;
set_rx_state <= '1';
else
next_rx_state <= USER_DATA;
set_pkt_cnt <= INCR; -- count another pkt
set_rx_state <= '1';
set_ip_rx_start <= SET;
end if;
-- now have the dst IP addr
dst_ip_rx <= dst_ip & mac_data_in;
if dst_ip_rx = IP_BC_ADDR then
set_is_broadcast <= SET;
else
set_is_broadcast <= CLR;
end if;
set_hdr_valid <= SET; -- header values are now valid, although the pkt may not be for us
--if dst_ip_rx = our_ip_address or dst_ip_rx = IP_BC_ADDR then
-- next_rx_state <= USER_DATA;
-- set_pkt_cnt <= INCR; -- count another pkt received
-- set_rx_state <= '1';
-- set_ip_rx_start <= SET;
--else
-- next_rx_state <= WAIT_END;
-- set_rx_state <= '1';
--end if;
when others => -- ignore other bytes in ip header
end case;
end if;
when DONE_ERR =>
error_code_val <= RX_EC_ET_IP;
set_error_code <= '1';
set_frame_err_cnt <= INCR;
set_ip_rx_start <= CLR;
set_data_last <= '1';
next_rx_state <= IDLE;
rx_count_mode <= RST;
set_rx_state <= '1';
end case;
when USER_DATA =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when START => -- (nothing to do)
when DATA => -- note: data gets transfered upstream as part of "output followers" processing
if rx_count = unsigned(data_len) then
set_ip_rx_start <= CLR;
rx_count_mode <= RST;
set_data_last <= '1';
if mac_data_in_last = '1' then
next_rx_state <= IDLE;
rx_count_mode <= RST;
set_ip_rx_start <= CLR;
else
next_rx_state <= WAIT_END;
end if;
set_rx_state <= '1';
else
rx_count_mode <= INCR;
-- check for early frame termination
if mac_data_in_last = '1' then
error_code_val <= RX_EC_ET_USER;
set_error_code <= '1';
set_frame_err_cnt <= INCR;
set_ip_rx_start <= CLR;
next_rx_state <= IDLE;
rx_count_mode <= RST;
set_rx_state <= '1';
end if;
end if;
when DONE_ERR =>
error_code_val <= RX_EC_ET_USER;
set_error_code <= '1';
set_frame_err_cnt <= INCR;
set_ip_rx_start <= CLR;
set_data_last <= '1';
next_rx_state <= IDLE;
rx_count_mode <= RST;
set_rx_state <= '1';
end case;
when ERR =>
set_frame_err_cnt <= INCR;
set_ip_rx_start <= CLR;
if mac_data_in_last = '0' then
set_data_last <= '1';
next_rx_state <= WAIT_END;
set_rx_state <= '1';
else
next_rx_state <= IDLE;
rx_count_mode <= RST;
set_rx_state <= '1';
end if;
when WAIT_END =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when START => -- (nothing to do)
when DATA =>
if mac_data_in_last = '1' then
set_data_last <= '1';
next_rx_state <= IDLE;
rx_count_mode <= RST;
set_rx_state <= '1';
set_ip_rx_start <= CLR;
end if;
when DONE_ERR =>
error_code_val <= RX_EC_ET_USER;
set_error_code <= '1';
set_frame_err_cnt <= INCR;
set_ip_rx_start <= CLR;
set_data_last <= '1';
next_rx_state <= IDLE;
rx_count_mode <= RST;
set_rx_state <= '1';
end case;
end case;
end process;
-----------------------------------------------------------------------------
-- sequential process to action control signals and change states and outputs
-----------------------------------------------------------------------------
rx_sequential : process (clk)--, reset)
begin
if rising_edge(clk) then
if reset = '1' then
-- reset state variables
rx_state <= IDLE;
rx_count <= x"0000";
src_ip <= (others => '0');
dst_ip <= (others => '0');
protocol <= (others => '0');
data_len <= (others => '0');
ip_rx_start_reg <= '0';
hdr_valid_reg <= '0';
is_broadcast_reg <= '0';
frame_err_cnt <= (others => '0');
error_code_reg <= RX_EC_NONE;
rx_pkt_counter <= x"00";
else
-- Next rx_state processing
if set_rx_state = '1' then
rx_state <= next_rx_state;
else
rx_state <= rx_state;
end if;
-- rx_count processing
case rx_count_mode is
when RST => rx_count <= x"0000";
when INCR => rx_count <= rx_count + 1;
when SET_VAL => rx_count <= rx_count_val;
when HOLD => rx_count <= rx_count;
end case;
-- frame error count processing
case set_frame_err_cnt is
when RST => frame_err_cnt <= x"00";
when INCR => frame_err_cnt <= frame_err_cnt + 1;
when HOLD => frame_err_cnt <= frame_err_cnt;
end case;
-- ip pkt processing
case set_pkt_cnt is
when RST => rx_pkt_counter <= x"00";
when INCR => rx_pkt_counter <= rx_pkt_counter + 1;
when HOLD => rx_pkt_counter <= rx_pkt_counter;
end case;
-- source ip capture
if (set_ip3 = '1') then src_ip(31 downto 24) <= dataval; end if;
if (set_ip2 = '1') then src_ip(23 downto 16) <= dataval; end if;
if (set_ip1 = '1') then src_ip(15 downto 8) <= dataval; end if;
if (set_ip0 = '1') then src_ip(7 downto 0) <= dataval; end if;
-- dst ip capture
if (set_dst_ip3 = '1') then dst_ip(23 downto 16) <= dataval; end if;
if (set_dst_ip2 = '1') then dst_ip(15 downto 8) <= dataval; end if;
if (set_dst_ip1 = '1') then dst_ip(7 downto 0) <= dataval; end if;
if (set_protocol = '1') then
protocol <= dataval;
else
protocol <= protocol;
end if;
if (set_len_H = '1') then
data_len (15 downto 8) <= dataval;
data_len (7 downto 0) <= x"00";
elsif (set_len_L = '1') then
-- compute data length, taking into account that we need to subtract the header length
data_len <= std_logic_vector(unsigned(data_len(15 downto 8) & dataval) - 20);
else
data_len <= data_len;
end if;
case set_ip_rx_start is
when SET => ip_rx_start_reg <= '1';
when CLR => ip_rx_start_reg <= '0';
when HOLD => ip_rx_start_reg <= ip_rx_start_reg;
end case;
case set_is_broadcast is
when SET => is_broadcast_reg <= '1';
when CLR => is_broadcast_reg <= '0';
when HOLD => is_broadcast_reg <= is_broadcast_reg;
end case;
case set_hdr_valid is
when SET => hdr_valid_reg <= '1';
when CLR => hdr_valid_reg <= '0';
when HOLD => hdr_valid_reg <= hdr_valid_reg;
end case;
-- set error code
if set_error_code = '1' then
error_code_reg <= error_code_val;
else
error_code_reg <= error_code_reg;
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 71a43e1d2f4cebb426ad40fa2de24d43 | 0.416705 | 3.983669 | false | false | false | false |
INTI-CMNB-FPGA/fpga_lib | vhdl/verif/testbench/loopcheck_tb.vhdl | 1 | 3,676 | --
-- LoopCheck Testbench
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2016-2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library FPGALIB;
use FPGALIB.Verif.all;
use FPGALIB.Simul.all;
entity LoopCheck_Tb is
end entity LoopCheck_Tb;
architecture Test of LoopCheck_Tb is
constant FREQUENCY1 : positive:=10;
constant FREQUENCY2 : positive:=9;
signal clk1, rst1 : std_logic;
signal clk2, rst2 : std_logic;
signal stop : boolean;
-- dut
constant DWIDTH : positive:=8;
signal data1i, data1o: std_logic_vector(DWIDTH-1 downto 0);
signal data2i : std_logic_vector(DWIDTH-1 downto 0);
signal stb1, stb2 : std_logic;
signal errors : std_logic_vector(4 downto 0);
-- mem
constant TOVAL : positive:=(2**DWIDTH)-1;
type mem_type is array(0 to TOVAL) of std_logic_vector (DWIDTH-1 downto 0);
signal ram : mem_type;
begin
do_clk1: Clock
generic map(FREQUENCY => FREQUENCY1)
port map(clk_o => clk1, rst_o => rst1, stop_i => stop);
do_clk2: Clock
generic map(FREQUENCY => FREQUENCY2)
port map(clk_o => clk2, rst_o => rst2, stop_i => stop);
dut: LoopCheck
generic map(DWIDTH => DWIDTH)
port map(
-- Tx side
tx_clk_i => clk1,
tx_rst_i => rst1,
tx_stb_i => stb1,
tx_data_i => data1i,
tx_data_o => data1o,
-- Rx side
rx_clk_i => clk2,
rx_rst_i => rst2,
rx_stb_i => stb2,
rx_data_i => data2i,
rx_errors_o => errors
);
do_read: process
begin
stb1 <= '0';
data1i <= (others => '0');
wait until rising_edge(clk1) and rst1='0';
for i in 0 to 255 loop
stb1 <= '1';
wait until rising_edge(clk1);
ram(i) <= data1o;
stb1 <= '0';
end loop;
wait;
end process do_read;
do_write: process
begin
stb2 <= '0';
wait until rising_edge(clk2) and rst2='0';
for i in 0 to 4 loop
wait until rising_edge(clk2);
end loop;
assert errors(0)='1' report "Not consumed must be '1' but is '0'" severity failure;
for i in 0 to 255 loop
stb2 <= '1';
if i=200 then
data2i <= (others => '1');
else
data2i <= ram(i);
end if;
wait until rising_edge(clk2);
if i <= 200 then
assert errors(1)='0' report "Value Missmatch must be '0' but is '1'" severity failure;
else
assert errors(1)='1' report "Value Missmatch must be '1' but is '0'" severity failure;
end if;
if i>0 then
assert errors(2)='1' report "Quantity Missmatch must be '1' but is '0'" severity failure;
assert errors(3)='1' report "Less must be '1' but is '0'("&to_str(errors)&")";-- severity failure;
end if;
end loop;
stb2 <= '0';
wait until rising_edge(clk2);
assert errors(0)='0' report "Not consumed must be '0' but is '1'" severity failure;
assert errors(2)='0' report "Quantity Missmatch must be '0' but is '1'" severity failure;
assert errors(3)='0' report "Less must be '0' but is '1'" severity failure;
stb2 <= '1';
wait until rising_edge(clk2);
stb2 <= '0';
assert errors(4)='0' report "Less must be '0' but is '1'" severity failure;
wait until rising_edge(clk2);
assert errors(4)='1' report "Less must be '1' but is '0'" severity failure;
stop <= TRUE;
wait;
end process do_write;
end architecture Test;
| bsd-3-clause | a02bc851deb76fe4411c6db34f0be53d | 0.560936 | 3.397412 | false | false | false | false |
DreamIP/GPStudio | support/process/maxPool/hdl/maxPool_process.vhd | 1 | 3,909 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity maxPool_process is
generic(
PIXEL_SIZE : integer;
IMAGE_WIDTH : integer;
KERNEL_SIZE : integer
);
port(
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
in_data : in std_logic_vector (PIXEL_SIZE - 1 downto 0);
in_dv : in std_logic;
in_fv : in std_logic;
out_data : out std_logic_vector (PIXEL_SIZE - 1 downto 0);
out_dv : out std_logic;
out_fv : out std_logic
);
end entity;
architecture rtl of maxPool_process is
--------------------------------------------------------------------------
-- Signals
--------------------------------------------------------------------------
signal connect_data : std_logic_vector (PIXEL_SIZE - 1 downto 0);
signal connect_dv : std_logic;
signal connect_fv : std_logic;
--------------------------------------------------------------------------
-- components
--------------------------------------------------------------------------
component poolH
generic(
PIXEL_SIZE : integer;
IMAGE_WIDTH : integer;
KERNEL_SIZE : integer
);
port(
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
in_data : in std_logic_vector (PIXEL_SIZE - 1 downto 0);
in_dv : in std_logic;
in_fv : in std_logic;
out_data : out std_logic_vector (PIXEL_SIZE - 1 downto 0);
out_dv : out std_logic;
out_fv : out std_logic
);
end component;
--------------------------------------------------------------------------
component poolV
generic(
PIXEL_SIZE : integer;
IMAGE_WIDTH : integer;
KERNEL_SIZE : integer
);
port(
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
in_data : in std_logic_vector (PIXEL_SIZE - 1 downto 0);
in_dv : in std_logic;
in_fv : in std_logic;
out_data : out std_logic_vector (PIXEL_SIZE - 1 downto 0);
out_dv : out std_logic;
out_fv : out std_logic
);
end component;
--------------------------------------------------------------------------
begin
poolV_inst : poolV
generic map (
PIXEL_SIZE => PIXEL_SIZE,
KERNEL_SIZE => KERNEL_SIZE,
IMAGE_WIDTH => IMAGE_WIDTH
)
port map (
clk => clk,
reset_n => reset_n,
enable => enable,
in_data => in_data,
in_dv => in_dv,
in_fv => in_fv,
out_data => connect_data,
out_dv => connect_dv,
out_fv => connect_fv
);
------------------------------------------------------------------------
poolh_inst : poolH
generic map (
PIXEL_SIZE => PIXEL_SIZE,
KERNEL_SIZE => KERNEL_SIZE,
IMAGE_WIDTH => IMAGE_WIDTH
)
port map (
clk => clk,
reset_n => reset_n,
enable => enable,
in_data => connect_data,
in_dv => connect_dv,
in_fv => connect_fv,
out_data => out_data,
out_dv => out_dv,
out_fv => out_fv
);
end rtl;
| gpl-3.0 | 2b9820e79cee0836eb8337f25feab627 | 0.362753 | 4.35786 | false | false | false | false |
DreamIP/GPStudio | support/process/lbp/hdl/lbp.vhd | 1 | 3,147 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity lbp is
generic (
LINE_WIDTH_MAX : integer;
IN_SIZE : integer;
OUT_SIZE : integer;
CLK_PROC_FREQ : integer := 48000000
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- in flow -----------------------
in_data : in std_logic_vector((IN_SIZE-1) downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector((OUT_SIZE-1) downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end lbp;
architecture rtl of lbp is
component lbp_slave
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0);
-- connections to lbp module
enable_o : out std_logic;
widthimg_o : out std_logic_vector(15 downto 0);
theshold_o : out std_logic_vector(7 downto 0)
);
end component;
component lbp_process
generic (
LINE_WIDTH_MAX : integer;
PIX_WIDTH : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- in flow -----------------------
in_data : in std_logic_vector((IN_SIZE-1) downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector((OUT_SIZE-1) downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
------------------------- params ------------------------
enable_i : in std_logic;
widthimg_i : in std_logic_vector(15 downto 0);
theshold_i : in std_logic_vector(7 downto 0)
);
end component;
-- signals part
signal enable_s : std_logic;
signal widthimg_s : std_logic_vector(15 downto 0);
signal theshold_s : std_logic_vector(7 downto 0);
begin
lbp_slave_inst : lbp_slave
port map (
clk_proc => clk_proc,
reset_n => reset_n,
-- bus_sl
addr_rel_i => addr_rel_i,
wr_i => wr_i,
rd_i => rd_i,
datawr_i => datawr_i,
datard_o => datard_o,
-- connections to lbp_process
enable_o => enable_s,
widthimg_o => widthimg_s,
theshold_o => theshold_s
);
lbp_process_inst : lbp_process
generic map (
LINE_WIDTH_MAX => LINE_WIDTH_MAX,
PIX_WIDTH => IN_SIZE
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
-- in flow
in_data => in_data,
in_fv => in_fv,
in_dv => in_dv,
-- out flow
out_data => out_data,
out_fv => out_fv,
out_dv => out_dv,
-- connections to lbp_slave
enable_i => enable_s,
widthimg_i => widthimg_s,
theshold_i => theshold_s
);
end rtl;
| gpl-3.0 | 1dacc884412c14037c4323198953347d | 0.542104 | 2.653457 | false | false | false | false |
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